| author | sujith <sujith.s@ti.com> | |
| Fri, 18 Dec 2020 13:37:10 +0000 (19:07 +0530) | ||
| committer | sujith <sujith.s@ti.com> | |
| Fri, 18 Dec 2020 13:37:10 +0000 (19:07 +0530) |
15 files changed:
index e27acf563ca29ba87412d89e337adfa67305766e..a296a97a4187195dab3c795346d7934b0c5ec3a2 100755 (executable)
@echo off\r
\r
set PDK_PATH=%1\r
+set PDK_INSTALL_PATH=%PDK_PATH%\r
set CG_TOOL_PATH=%2\r
set APP_PATH=%3\r
set APP_NAME=%4\r
index ed113c20d3aaf99b8aa2b5052e565847ddc7c507..20ffb8316a6cb9eff7577ce755ab2eea3f6026df 100755 (executable)
# *****************************************************************************
export PDK_PATH=$1
+export PDK_INSTALL_PATH=$PDK_PATH
export CG_TOOL_PATH=$2
export APP_PATH=$3
export APP_NAME=$4
diff --git a/packages/ti/board/src/flash/src_files_flash.mk b/packages/ti/board/src/flash/src_files_flash.mk
index 398fe16a0891befe41fc169ddccc9f3e083d24d0..79dd9c95f7b189b291388c38491128d981eab280 100755 (executable)
PACKAGE_SRCS_COMMON += src/flash/nor/ospi/nor_spi_patterns.c src/flash/nor/ospi/nor_spi_patterns.h
PACKAGE_SRCS_COMMON += src/flash/nor/ospi/nor_spi_phy_tune.c src/flash/nor/ospi/nor_spi_phy_tune.h
PACKAGE_SRCS_COMMON += src/flash/nor/ospi/nor_spi_patterns.bin
+
ifeq ($(BOARD),$(filter $(BOARD), am64x_svb))
PACKAGE_SRCS_COMMON += src/flash/nor/device/m35xu256.h
else
diff --git a/packages/ti/boot/sbl/build/sbl_mcu0_boot_perf_test.mk b/packages/ti/boot/sbl/build/sbl_mcu0_boot_perf_test.mk
index 4ff070a27cecc70e40a8328f996fe5e30f3d6b65..b5c56a829415a035ceeb7051640c417d60ecc203 100644 (file)
ifeq ($(filter $(SBL_CFLAGS), -DSBL_ENABLE_DEV_GRP_MCU), -DSBL_ENABLE_DEV_GRP_MCU)
EXTERNAL_LNKCMD_FILE_LOCAL = $(PDK_SBL_COMP_PATH)/example/k3MulticoreApp/mcuBootPerfLinker_small.lds
else
- ifeq ($(SOC),$(filter $(SOC), j7200))
+ ifeq ($(SOC),$(filter $(SOC), j7200 am65xx))
EXTERNAL_LNKCMD_FILE_LOCAL = $(PDK_SBL_COMP_PATH)/example/k3MulticoreApp/mcuBootPerfLinker_small.lds
else
SRCS_ASM_COMMON += sbl_boot_perf_r5.asm
diff --git a/packages/ti/boot/sbl/example/k3MulticoreApp/mcuBootPerfLinker_small.lds b/packages/ti/boot/sbl/example/k3MulticoreApp/mcuBootPerfLinker_small.lds
index 8f60178474a8686bd4e3995d91cf09cfce22031e..40551518bfc8686dc8236feb5d62e2915f8aa2a0 100644 (file)
/* Used for SYSFW initlization */
OCMRAM_SBL_SYSFW (RWIX) : origin=0x41C3E000 length=0x4000
OCMRAM_SBL_UNUSED (X) : origin=0x41C7E000 length=0x2000
+ /* Line below is not used / not needed for AM65xx */
OCMRAM_SBL_RM_PM_HAL (X): origin=0x41C80000 length=0x6000
/* App code resides here */
index 69db13797873734616855ab1f5003afbd9b6155d..c8c34c7b7c30f739d3bacfd9a241c00198ca6c34 100644 (file)
@@ -1179,7 +1179,7 @@ CUST_SBL_TEST_FLAGS =" -DSBL_USE_DMA=0 -DSBL_LOG_LEVEL=1 -DSBL_SCRATCH_MEM_START
# Custom ex: Early CAN response (NOTE: before using line below, comment out the line above)
#CUST_SBL_TEST_FLAGS =" -DSBL_USE_DMA=0 -DSBL_LOG_LEVEL=1 -DSBL_SCRATCH_MEM_START=0x41cc0000 -DSBL_SCRATCH_MEM_SIZE=0x40000 -DSBL_ENABLE_PLL -DSBL_ENABLE_CLOCKS -DSBL_SKIP_MCU_RESET -DBOOT_OSPI -DSBL_ENABLE_DEV_GRP_MCU -DSBL_HLOS_OWNS_FLASH -DSBL_SKIP_PINMUX_ENABLE -DSBL_SKIP_LATE_INIT -DSBL_USE_MCU_DOMAIN_ONLY"
else
-CUST_SBL_TEST_FLAGS =" -DSBL_USE_DMA=0 -DSBL_LOG_LEVEL=1 -DSBL_SCRATCH_MEM_START=0x70100000 -DSBL_SCRATCH_MEM_SIZE=0xF0000 -DSBL_ENABLE_PLL -DSBL_ENABLE_CLOCKS -DSBL_SKIP_MCU_RESET -DBOOT_OSPI -DSBL_ENABLE_DEV_GRP_MCU -DSBL_HLOS_OWNS_FLASH"
+CUST_SBL_TEST_FLAGS =" -DSBL_USE_DMA=0 -DSBL_LOG_LEVEL=1 -DSBL_SCRATCH_MEM_START=0x70100000 -DSBL_SCRATCH_MEM_SIZE=0xF0000 -DSBL_ENABLE_PLL -DSBL_ENABLE_CLOCKS -DSBL_SKIP_MCU_RESET -DBOOT_OSPI"
endif
#Custom configuration for AM64x OSPI Boot
#CUST_SBL_TEST_FLAGS =" -DSBL_USE_DMA=0 -DSBL_LOG_LEVEL=3 -DSBL_SCRATCH_MEM_START=0x70100000 -DSBL_SCRATCH_MEM_SIZE=0xF0000 -DSBL_ENABLE_PLL -DSBL_ENABLE_CLOCKS -DBOOT_OSPI -DSBL_ENABLE_DDR -DSBL_BYPASS_OSPI_DRIVER"
diff --git a/packages/ti/boot/sbl/soc/k3/sbl_sci_client.c b/packages/ti/boot/sbl/soc/k3/sbl_sci_client.c
index 6b0c44889763cad683e298fe7484acea2b4eadcb..f0a015c8f2c66144ad5a91175483f9ec3ff9c4a8 100755 (executable)
#ifndef SBL_SKIP_SYSFW_INIT
/* SYSFW board configurations */
Sciclient_DefaultBoardCfgInfo_t boardCfgInfo;
- Sciclient_ConfigPrms_t config =
- {
- SCICLIENT_SERVICE_OPERATION_MODE_POLLED,
- NULL,
- 1,
- 0,
- TRUE
- };
+ Sciclient_ConfigPrms_t config;
+ Sciclient_configPrmsInit(&config);
+ config.opModeFlag = SCICLIENT_SERVICE_OPERATION_MODE_POLLED;
+ config.pBoardCfgPrms = NULL;
+ config.isSecureMode = 1;
+ config.c66xRatRegion = 0;
+ config.skipLocalBoardCfgProcess = TRUE;
+
+#if defined(SOC_AM65XX)
+ config.isSecureMode = 0U;
+#endif /* AM65xx the default board cfg is for non-secure mode */
+
#endif
SBL_ADD_PROFILE_POINT;
diff --git a/packages/ti/boot/sbl/soc/k3/sbl_slave_core_boot.c b/packages/ti/boot/sbl/soc/k3/sbl_slave_core_boot.c
index b7d5773b12ebbb88ce41b3576958563b457a59d9..8199b43c04ae0b4b4a35f98ed89feb875e3d4366 100644 (file)
}
#endif
- SBL_log(SBL_LOG_MAX, "Sciclient_procBootSetProcessorCfg enabling TCMs...\n");
+ SBL_log(SBL_LOG_MAX, "Sciclient_procBootSetProcessorCfg update TCM enable/disable settings...\n");
status = Sciclient_procBootSetProcessorCfg(&proc_set_config_req, SCICLIENT_SERVICE_WAIT_FOREVER);
if (status != CSL_PASS)
{
@@ -679,7 +679,6 @@ void SBL_SlaveCoreBoot(cpu_core_id_t core_id, uint32_t freqHz, sblEntryPoint_t *
#if defined(SBL_SKIP_MCU_RESET) && (defined(SBL_SKIP_BRD_CFG_BOARD) || defined(SBL_SKIP_BRD_CFG_PM) || defined(SBL_SKIP_SYSFW_INIT))
/* Skip copy if R5 app entry point is already 0 */
-#if !defined(SOC_AM65XX) /* Pre-loading ATCM is not permitted for AM65xx */
if ((core_id == MCU1_CPU0_ID) &&
(pAppEntry->CpuEntryPoint[core_id]) &&
(pAppEntry->CpuEntryPoint[core_id] < SBL_INVALID_ENTRY_ADDR))
@@ -688,7 +687,6 @@ void SBL_SlaveCoreBoot(cpu_core_id_t core_id, uint32_t freqHz, sblEntryPoint_t *
memcpy(((void *)(SblAtcmAddr[core_id - MCU1_CPU0_ID])), (void *)(pAppEntry->CpuEntryPoint[core_id]), 128);
return;
}
-#endif
/* Finished processing images for all cores, start MCU_0 */
if ((core_id == MCU1_CPU1_ID) &&
@@ -886,7 +884,7 @@ void SBL_SlaveCoreBoot(cpu_core_id_t core_id, uint32_t freqHz, sblEntryPoint_t *
case MCU1_CPU0_ID:
/* Skip copy if R5 app entry point is already 0 */
-#if !defined(SOC_AM65XX) /* Pre-loading ATCM is not permitted for AM65xx */
+#if !defined(SOC_AM65XX) || defined(SBL_SKIP_MCU_RESET)
if (pAppEntry->CpuEntryPoint[core_id])
{
SBL_log(SBL_LOG_MAX, "Copying first 128 bytes from app to MCU ATCM @ 0x%x for core %d\n", SblAtcmAddr[core_id - MCU1_CPU0_ID], core_id);
diff --git a/packages/ti/boot/sbl/tools/scripts/K3ImageGen.bat b/packages/ti/boot/sbl/tools/scripts/K3ImageGen.bat
index 01b212248a6badf36d7b1be6b20c0bdde813e310..33da843e539c87e514db4cc86d082d894c8c0068 100644 (file)
if defined image_gen (
echo Generating MulticoreImage
"%TOOLS_PATH%\multicoreImageGen\bin\MulticoreImageGen.exe" LE %Dev_ID% %BIN_PATH%\%APP_OUT_NAME%.appimage %CORE_ID% %APP_RPRC%
-"powershell -executionpolicy unrestricted -command %PDK_INSTALL_PATH%\ti\build\makerules\x509CertificateGen.ps1" -b %BIN_PATH%\%APP_OUT_NAME%.appimage -o %BIN_PATH%\%APP_OUT_NAME%.appimage.signed -c R5 -l 0x0 -k %PDK_INSTALL_PATH%\ti\build\makerules\k3_dev_mpk.pem )
+powershell -executionpolicy unrestricted -command "%PDK_INSTALL_PATH%\ti\build\makerules\x509CertificateGen.ps1" -b %BIN_PATH%\%APP_OUT_NAME%.appimage -o %BIN_PATH%\%APP_OUT_NAME%.appimage.signed -c R5 -l 0x0 -k %PDK_INSTALL_PATH%\ti\build\makerules\k3_dev_mpk.pem )
if not defined image_gen (
echo. Error Application .out missing!! )
index 15b17e01f9f45cf197271123ad0a6b9a5332864b..305e6143daf710fd9f4586e0035f0f01d575b861 100644 (file)
include $(MAKERULEDIR)/common.mk
ifeq ($(SOC), $(filter $(SOC), am65xx))
-ifeq ($(CORE), $(filter $(CORE), mpu1_0))
+ifeq ($(CORE), $(filter $(CORE), mpu1_0 mcu1_0))
.PHONY: dualmac_fw
mpu1_0: dualmac_fw
+mcu1_0: dualmac_fw
dualmac_fw:
@echo "Building DualMac FW"
diff --git a/packages/ti/drv/emac/test/EmacLoopbackTest/am65xx/emacUnitTest_r5.cfg b/packages/ti/drv/emac/test/EmacLoopbackTest/am65xx/emacUnitTest_r5.cfg
index 95ef689cdd5a942fedcdcf71781e1d3702ad9c29..b1965c162216a4066d728e5ea63f97823c511139 100755 (executable)
var Timer = xdc.useModule('ti.sysbios.timers.dmtimer.Timer');
Timer.checkFrequency = false;
+/* Sysbios supports workaround for Silicon issue https://jira.itg.ti.com/browse/K3_OPEN_SI-148
+ * Details of silicon issue : https://confluence.itg.ti.com/display/PROCIPDEV/%2310+The+same+interrupt+cannot+be+nested+back-2-back+within+another+interrupt
+ * Sysbios Requirement Details: https://jira.itg.ti.com/browse/SYSBIOS-1419
+ * Workaround requires use of a resevred dummyIRQ.
+ * Using DummyIRQ#352 as per cslr_intr_mcu0.h it is a reserved interrupt not connected to any
+ * peripheral interrupt sources
+ */
+Hwi.dummyIRQ = 352;
+
var Reset = xdc.useModule("xdc.runtime.Reset");
Reset.fxns[Reset.fxns.length++] = "&utilsCopyVecs2ATcm";
Program.sectMap[".bss:emac_ddr_mem"] = "DDR0";
-Program.sectMap[".bss:emac_msmc_mem"] = "MSMC3_H";
+Program.sectMap[".bss:emac_msmc_mem"] = "MSMC3";
Program.sectMap[".vecs"] = "RESET_VECTORS";
/*
* Initialize MPU and enable it
diff --git a/packages/ti/drv/emac/test/EmacLoopbackTest/am65xx/emac_linker_r5.lds b/packages/ti/drv/emac/test/EmacLoopbackTest/am65xx/emac_linker_r5.lds
index 5bb3443d361f98d8870b5815a2888b1fab62172f..4ac1f37c75942fb6fd25c907e67a9deabfaf3944 100644 (file)
-/*----------------------------------------------------------------------------*/
-/* File: emac_linker_r5.cmd */
-/* Description: */
-/* Link command file for AM65XX M4 MCU 0 view */
-/* TI ARM Compiler version 15.12.3 LTS or later */
-/* */
-/* Platform: QT */
-/* (c) Texas Instruments 2017, All rights reserved. */
-/*----------------------------------------------------------------------------*/
-/* History: *'
-/* Aug 26th, 2016 Original version .......................... Loc Truong */
-/* Aug 01th, 2017 new TCM mem map .......................... Loc Truong */
-/* Nov 07th, 2017 Changes for R5F Init Code.................. Vivek Dhande */
-/*----------------------------------------------------------------------------*/
-/* Linker Settings */
-/* Standard linker options */
---retain="*(.intvecs)"
---retain="*(.intc_text)"
---retain="*(.rstvectors)"
+
+/* This is standard linker options used by examples applications and tests */
+/* Please refer user guide that came with this release for more details */
+/* on which sections could be used at load time and runtime */
+
--fill_value=0
---entry_point=ti_sysbios_family_arm_v7r_keystone3_Hwi_vectors /* Default BIOS */
---retain="*(.utilsCopyVecsToAtcm)"
+/* Retain entry point */
+-e __VECS_ENTRY_POINT
/*----------------------------------------------------------------------------*/
-/* Memory Map */
+/* Memory Sections */
MEMORY
{
- VECTORS (X) : origin=0x41C7F000 length=0x1000
- /* Reset Vectors base address(RESET_VECTORS) should be 64 bytes aligned */
- RESET_VECTORS (X) : origin=0x41C00000 length=0x100
- /* MCU0_R5F_0 local view */
- MCU0_R5F_TCMA_SBL_RSVD (X) : origin=0x0 length=0x100
- MCU0_R5F_TCMA (X) : origin=0x100 length=0x8000 - 0x100
- MCU0_R5F_TCMB0 (RWIX) : origin=0x41010000 length=0x8000
-
- /* MCU0_R5F_1 SoC view */
- MCU0_R5F1_ATCM (RWIX) : origin=0x41400000 length=0x8000
- MCU0_R5F1_BTCM (RWIX) : origin=0x41410000 length=0x8000
-
- /* Fully avaialble for apps. Used by SBL to load SYSFW */
- OCMRAM_LOW (RWIX) : origin=0x41C00100 length=0x40600 - 0x100 /* ~257KB */
-
- /* MCU0 memory used for SBL. Avaiable after boot for app starts for dynamic use */
- SBL_RESERVED (RWIX) : origin=0x41C40600 length=0x60000 - 0x40600 /* ~126KB */
-
- /* MCU0 share locations */
- OCMRAM (RWIX) : origin=0x41C60000 length=0x20000 - 0x1000 /* ~124KB */
-
- /* AM65XX M4 locations */
- MSMC3 (RWIX) : origin=0x70000000 length=0xF0000 /* 1MB - 64K */
- MSMC3_H (RWIX) : origin=0x70100000 length=0xE2000 /* 1MB -56K */
-
- /* Reserved for DMSC */
- MSMC3_DMSC (RWIX) : origin=0x701F0000 length=0x10000 /* 64K */
-
- DDR0 (RWIX) : origin=0x80000000 length=0x80000000 /* 2GB */
-
-/* Additional memory settings */
+ /* Refer the user guide for details on persistence of these sections */
+ /* Also, when these memories can be used by apps */
+ MCU0_ATCM_NOT_USED (R) : origin=0x0 length=0x7FFF
+ MCU0_BTCM_NOT_USED (R) : origin=0x41010000 length=0x7FFF
+ /* Used by SBL, can be used after APPs is started */
+ MCU_MSRAM_RSVD_UNUSED (R) : origin=0x41C00000 length=0x200
+ MCU_MSRAM_RSVD_SBL (RWIX) : origin=0x41C00200 length=0x3DE00
+
+ VECTORS (RWIX) : origin=0x41C3E000 length=0x100
+ RESET_VECTORS (RWIX) : origin=0x41C3E100 length=0x1000
+ OCMRAM (RWIX) : origin=0x41C3F100 length=0x40F00
+
+ /* COMPUTE_CLUSTER0_MSMC_SRAM */
+ MSMC3 (RWIX) : origin=0x70000000 length=0x1EFC00
+ /* The origin and length is determined by board cfg, */
+ /* refer user guide for details */
+ MSMC3_RSVD_DMSC (RWIX) : origin=0x701F0000 length=0x1000
+ DDR0 (RWIX) : origin=0x80000000 length=0x7FFFFFE4
} /* end of MEMORY */
SECTIONS
{
-/* 'intvecs' and 'intc_text' sections shall be placed within */
-/* a range of +\- 16 MB */
- .intvecs : {} palign(8) > VECTORS
- .intc_text : {} palign(8) > VECTORS
- .rstvectors : {} palign(8) > RESET_VECTORS
- .utilsCopyVecsToAtcm : {} palign(8) > MCU0_R5F_TCMB0
- .text : {} palign(8) > MSMC3
- .const : {} palign(8) > MSMC3
- .cinit : {} palign(8) > MSMC3
- .pinit : {} palign(8) > MSMC3
+ /* Place sysbios entry point - starts */
+ .vecs : { *(.vecs) } palign(8) > VECTORS
+ .vecs : { __VECS_ENTRY_POINT = .; } > VECTORS
+
+ xdc.meta (COPY): { *(xdc.meta) } > OCMRAM
+ .init_text : {
+ boot.*(.text)
+ *(.text:ti_sysbios_family_arm_MPU_*)
+ *(.text:ti_sysbios_family_arm_v7r_Cache_*)
+ } palign(8) > OCMRAM
+
+ .text:xdc_runtime_Startup_reset__I: {} palign(8) > OCMRAM
+
+ .bootCode : {} palign(8) > OCMRAM
+ .startupCode : {} palign(8) > OCMRAM
+ .startupData : {} palign(8) > OCMRAM, type = NOINIT
+ .utilsCopyVecsToAtcm : {} palign(8) > OCMRAM
+
+ /* Place sysbios entry point - ends */
+
+ .text : {} palign(8) > MSMC3
+ .const : {} palign(8) > MSMC3
+ .cinit : {} palign(8) > MSMC3
+ .pinit : {} palign(8) > MSMC3
/* For NDK packet memory, we need to map this sections before .bss*/
.bss:NDK_MMBUFFER (NOLOAD) {} ALIGN (128) > DDR0
.bss:NDK_PACKETMEM (NOLOAD) {} ALIGN (128) > DDR0
- .bss : {} align(4) > MSMC3
- .far : {} align(4) > DDR0
- .data : {} palign(128) > MSMC3
- .boardcfg_data : {} palign(128) > MSMC3
- .sysmem : {} > MSMC3
- .stack : {} align(4) > MSMC3 (HIGH)
+ .bss : {} align(8) > DDR0
+ .far : {} align(8) > DDR0
+ .data : {} palign(128)> MSMC3
+ .boardcfg_data : {} palign(128) > MSMC3
+ .sysmem : {} align(8) > MSMC3
+ .stack : {} align(8) > MSMC3 (HIGH)
/* SA sections */
- .scBufs : {} align(4) > DDR0
- .saSrcBuffers : {} align(4) > DDR0
- .saDstBuffers : {} align(4) > DDR0
+ .scBufs : {} align(8) > DDR0
+ .saSrcBuffers : {} align(8) > DDR0
+ .saDstBuffers : {} align(8) > DDR0
- /* USB or any other LLD buffer for benchmarking */
+ /* LLD buffer for benchmarking */
.benchmark_buffer (NOLOAD) {} ALIGN (8) > DDR0
-/* Additional sections settings */
+ /* Additional sections settings */
} /* end of SECTIONS */
diff --git a/packages/ti/fs/fatfs/example/console/am65xx/r5/mpu.xs b/packages/ti/fs/fatfs/example/console/am65xx/r5/mpu.xs
index bd89bbeebde449942016a42f08ee9ac9f9ff839f..94f4fbb014503dc8d895153f633fc72d169a1a85 100644 (file)
*/
/*
* ======== event_MPU.xs ========
- * MPU Settings for SIMMAXWELL device's Cortex-R5F
+ * MPU Settings for AM65XX device's Cortex-R5F
*/
/*
* |-------------------------------------------------------------------------------------------------------------|
* | 0 | 0x00000000 | 4GB | T | Strongly Ordered, Shareable | T | RW at PL 1 | 0x0 |
* |----|--------------|------|----|-------------------------------------------|----|---------------------|------|
- * | 1 | 0x00000000 | 1K | T | Write-Back, Write-Allocate, Non-Shareable | F | RW at PL 1 | 0x0 |
+ * | 1 | 0x00000000 | 1K | T | Non-cacheable, Non-Shareable | F | RW at PL 1 | 0x0 |
* |----|--------------|------|----|-------------------------------------------|----|---------------------|------|
- * | 2 | 0x41000000 | 32K | T | Write-Back, Write-Allocate, Non-Shareable | F | RW at PL 1 | 0x0 |
+ * | 2 | 0x41000000 | 32K | T | Non-cacheable Non-Shareable | F | RW at PL 1 | 0x0 |
* |----|--------------|------|----|-------------------------------------------|----|---------------------|------|
- * | 3 | 0x41010000 | 32K | T | Write-Back, Write-Allocate, Non-Shareable | F | RW at PL 1 | 0x0 |
+ * | 3 | 0x41010000 | 32K | T |Non-cacheable, Non-Shareable | F | RW at PL 1 | 0x0 |
* |----|--------------|------|----|-------------------------------------------|----|---------------------|------|
* | 4 | 0x41C00000 | 512K | T | Write-Back, Write-Allocate, Non-Shareable | F | RW at PL 1 | 0x0 |
+ * |----|--------------|------|----|-------------------------------------------|----|---------------------|------|
+ * | 5 | 0x4F800000 | 512K | T |Write-Back, Write-Allocate, Non-Shareable | F | RW at PL 1 | 0x0 |
+ * |----|--------------|------|----|-------------------------------------------|----|---------------------|------|
+ * | 6 | 0x70000000 | 2MB | T |Write-Back, Write-Allocate, Non-Shareable | F | RW at PL 1 | 0x0 |
+ * |----|--------------|------|----|-------------------------------------------|----|---------------------|------|
+ * | 7 | 0x04000000 | 2MB | T |Write-Back, Write-Allocate, Non-Shareable | F | RW at PL 1 | 0x0 |
+ * |----|--------------|------|----|-------------------------------------------|----|---------------------|------|
+ * | 8 | 0x80000000 | 2GB | T | Write-Back, Write-Allocate, Non-Shareable | F | RW at PL 1 | 0x0 |
* -------------------------------------------------------------------------------------------------------------
*/
MPU.setRegionMeta(0, 0x00000000, MPU.RegionSize_4G, attrs);
attrs.enable = true;
-attrs.bufferable = true;
-attrs.cacheable = true;
+attrs.bufferable = false;
+attrs.cacheable = false;
attrs.shareable = false;
attrs.noExecute = false;
attrs.accPerm = 1; /* RW at PL1 */
MPU.setRegionMeta(1, 0x00000000, MPU.RegionSize_32K, attrs);
attrs.enable = true;
-attrs.bufferable = true;
-attrs.cacheable = true;
+attrs.bufferable = false;
+attrs.cacheable = false;
attrs.shareable = false;
attrs.noExecute = false;
attrs.accPerm = 1; /* RW at PL1 */
MPU.setRegionMeta(2, 0x41000000, MPU.RegionSize_32K, attrs);
attrs.enable = true;
-attrs.bufferable = true;
-attrs.cacheable = true;
+attrs.bufferable = false;
+attrs.cacheable = false;
attrs.shareable = false;
attrs.noExecute = false;
attrs.accPerm = 1; /* RW at PL1 */
attrs.accPerm = 1; /* RW at PL1 */
attrs.tex = 1;
attrs.subregionDisableMask = 0;
-MPU.setRegionMeta(4, 0x4F800000, MPU.RegionSize_512K, attrs);
+MPU.setRegionMeta(5, 0x4F800000, MPU.RegionSize_512K, attrs);
attrs.enable = true;
attrs.accPerm = 1; /* RW at PL1 */
attrs.tex = 1;
attrs.subregionDisableMask = 0;
-MPU.setRegionMeta(5, 0x70000000, MPU.RegionSize_2M, attrs);
+MPU.setRegionMeta(6, 0x70000000, MPU.RegionSize_2M, attrs);
attrs.enable = true;
attrs.accPerm = 1; /* RW at PL1 */
attrs.tex = 1;
attrs.subregionDisableMask = 0;
-MPU.setRegionMeta(6, 0x04000000, MPU.RegionSize_2M, attrs);
+MPU.setRegionMeta(7, 0x04000000, MPU.RegionSize_2M, attrs);
+
+attrs.enable = true;
+attrs.bufferable = true;
+attrs.cacheable = true;
+attrs.shareable = false;
+attrs.noExecute = false;
+attrs.accPerm = 1; /* RW at PL1 */
+attrs.tex = 1;
+attrs.subregionDisableMask = 0;
+MPU.setRegionMeta(8, 0x80000000, MPU.RegionSize_2G, attrs);
diff --git a/packages/ti/transport/ndk/nimu/example/am65xx/nimuExample_r5.cfg b/packages/ti/transport/ndk/nimu/example/am65xx/nimuExample_r5.cfg
index 7ccdb036d547d24b9ffbd09503182fc14a018c49..05085097706a3fe68e4e23b69454089e79df7e00 100755 (executable)
var Timer = xdc.useModule('ti.sysbios.timers.dmtimer.Timer');
Timer.checkFrequency = false;
+/* Sysbios supports workaround for Silicon issue https://jira.itg.ti.com/browse/K3_OPEN_SI-148
+ * Details of silicon issue : https://confluence.itg.ti.com/display/PROCIPDEV/%2310+The+same+interrupt+cannot+be+nested+back-2-back+within+another+interrupt
+ * Sysbios Requirement Details: https://jira.itg.ti.com/browse/SYSBIOS-1419
+ * Workaround requires use of a resevred dummyIRQ.
+ * Using DummyIRQ#352 as per cslr_intr_mcu0.h it is a reserved interrupt not connected to any
+ * peripheral interrupt sources
+ */
+Hwi.dummyIRQ = 352;
+
var Reset = xdc.useModule("xdc.runtime.Reset");
Reset.fxns[Reset.fxns.length++] = "&utilsCopyVecs2ATcm";
}
Program.sectMap[".bss:nimu_ddr_mem"] = "DDR0";
-Program.sectMap[".bss:nimu_msmc_mem"] = "MSMC3_H";
+Program.sectMap[".bss:nimu_msmc_mem"] = "MSMC3";
/*
* Initialize MPU and enable it
*
diff --git a/packages/ti/transport/ndk/nimu/example/am65xx/nimu_linker_r5.lds b/packages/ti/transport/ndk/nimu/example/am65xx/nimu_linker_r5.lds
index cf0b99c23ac7f4e191a1148e2364452c0d58f749..4ac1f37c75942fb6fd25c907e67a9deabfaf3944 100644 (file)
-/*----------------------------------------------------------------------------*/
-/* File: k3m4_r5f_linker.cmd */
-/* Description: */
-/* Link command file for AM65XX M4 MCU 0 view */
-/* TI ARM Compiler version 15.12.3 LTS or later */
-/* */
-/* Platform: QT */
-/* (c) Texas Instruments 2017-2019, All rights reserved. */
-/*----------------------------------------------------------------------------*/
-/* History: *'
-/* Aug 26th, 2016 Original version .......................... Loc Truong */
-/* Aug 01th, 2017 new TCM mem map .......................... Loc Truong */
-/* Nov 07th, 2017 Changes for R5F Init Code.................. Vivek Dhande */
-/*----------------------------------------------------------------------------*/
-/* Linker Settings */
-/* Standard linker options */
---retain="*(.intvecs)"
---retain="*(.intc_text)"
---retain="*(.rstvectors)"
+
+/* This is standard linker options used by examples applications and tests */
+/* Please refer user guide that came with this release for more details */
+/* on which sections could be used at load time and runtime */
+
--fill_value=0
---entry_point=ti_sysbios_family_arm_v7r_keystone3_Hwi_vectors /* Default BIOS */
---retain="*(.utilsCopyVecsToAtcm)"
+/* Retain entry point */
+-e __VECS_ENTRY_POINT
/*----------------------------------------------------------------------------*/
-/* Memory Map */
+/* Memory Sections */
MEMORY
{
- VECTORS (X) : origin=0x41C7F000 length=0x1000
- /* Reset Vectors base address(RESET_VECTORS) should be 64 bytes aligned */
- RESET_VECTORS (X) : origin=0x41C00000 length=0x100
- /* MCU0_R5F_0 local view */
- MCU0_R5F_TCMA_SBL_RSVD (X) : origin=0x0 length=0x100
- MCU0_R5F_TCMA (X) : origin=0x100 length=0x8000 - 0x100
- MCU0_R5F_TCMB0 (RWIX) : origin=0x41010000 length=0x8000
+ /* Refer the user guide for details on persistence of these sections */
+ /* Also, when these memories can be used by apps */
+ MCU0_ATCM_NOT_USED (R) : origin=0x0 length=0x7FFF
+ MCU0_BTCM_NOT_USED (R) : origin=0x41010000 length=0x7FFF
+ /* Used by SBL, can be used after APPs is started */
+ MCU_MSRAM_RSVD_UNUSED (R) : origin=0x41C00000 length=0x200
+ MCU_MSRAM_RSVD_SBL (RWIX) : origin=0x41C00200 length=0x3DE00
+
+ VECTORS (RWIX) : origin=0x41C3E000 length=0x100
+ RESET_VECTORS (RWIX) : origin=0x41C3E100 length=0x1000
+ OCMRAM (RWIX) : origin=0x41C3F100 length=0x40F00
+
+ /* COMPUTE_CLUSTER0_MSMC_SRAM */
+ MSMC3 (RWIX) : origin=0x70000000 length=0x1EFC00
+ /* The origin and length is determined by board cfg, */
+ /* refer user guide for details */
+ MSMC3_RSVD_DMSC (RWIX) : origin=0x701F0000 length=0x1000
+ DDR0 (RWIX) : origin=0x80000000 length=0x7FFFFFE4
- /* MCU0_R5F_1 SoC view */
- MCU0_R5F1_ATCM (RWIX) : origin=0x41400000 length=0x8000
- MCU0_R5F1_BTCM (RWIX) : origin=0x41410000 length=0x8000
-
- /* Fully avaialble for apps. Used by SBL to load SYSFW */
- OCMRAM_LOW (RWIX) : origin=0x41C00100 length=0x40600 - 0x100 /* ~257KB */
-
- /* MCU0 memory used for SBL. Avaiable after boot for app starts for dynamic use */
- SBL_RESERVED (RWIX) : origin=0x41C40600 length=0x60000 - 0x40600 /* ~126KB */
+} /* end of MEMORY */
- /* MCU0 share locations */
- OCMRAM (RWIX) : origin=0x41C60000 length=0x20000 - 0x1000 /* ~124KB */
+/*----------------------------------------------------------------------------*/
+/* Section Configuration */
- /* AM65XX M4 locations */
- MSMC3 (RWIX) : origin=0x70000000 length=0xF0000 /* 1MB - 64K */
- MSMC3_H (RWIX) : origin=0x70100000 length=0xE2000 /* 1MB -56K */
+SECTIONS
+{
+ /* Place sysbios entry point - starts */
+ .vecs : { *(.vecs) } palign(8) > VECTORS
+ .vecs : { __VECS_ENTRY_POINT = .; } > VECTORS
- /* Reserved for DMSC */
- MSMC3_DMSC (RWIX) : origin=0x701F0000 length=0x10000 /* 64K */
+ xdc.meta (COPY): { *(xdc.meta) } > OCMRAM
+ .init_text : {
+ boot.*(.text)
+ *(.text:ti_sysbios_family_arm_MPU_*)
+ *(.text:ti_sysbios_family_arm_v7r_Cache_*)
+ } palign(8) > OCMRAM
- DDR0 (RWIX) : origin=0x80000000 length=0x80000000 /* 2GB */
+ .text:xdc_runtime_Startup_reset__I: {} palign(8) > OCMRAM
-/* Additional memory settings */
+ .bootCode : {} palign(8) > OCMRAM
+ .startupCode : {} palign(8) > OCMRAM
+ .startupData : {} palign(8) > OCMRAM, type = NOINIT
+ .utilsCopyVecsToAtcm : {} palign(8) > OCMRAM
-} /* end of MEMORY */
+ /* Place sysbios entry point - ends */
-/*----------------------------------------------------------------------------*/
-/* Section Configuration */
+ .text : {} palign(8) > MSMC3
+ .const : {} palign(8) > MSMC3
+ .cinit : {} palign(8) > MSMC3
+ .pinit : {} palign(8) > MSMC3
-SECTIONS
-{
-/* 'intvecs' and 'intc_text' sections shall be placed within */
-/* a range of +\- 16 MB */
- .intvecs : {} palign(8) > VECTORS
- .intc_text : {} palign(8) > VECTORS
- .rstvectors : {} palign(8) > RESET_VECTORS
- .utilsCopyVecsToAtcm : {} palign(8) > MCU0_R5F_TCMB0
- .text : {} palign(8) > MSMC3
- .const : {} palign(8) > DDR0
- .cinit : {} palign(8) > DDR0
- .pinit : {} palign(8) > DDR0
/* For NDK packet memory, we need to map this sections before .bss*/
.bss:NDK_MMBUFFER (NOLOAD) {} ALIGN (128) > DDR0
.bss:NDK_PACKETMEM (NOLOAD) {} ALIGN (128) > DDR0
- .bss : {} align(4) > DDR0
- .far : {} align(4) > DDR0
- .data : {} palign(128) > DDR0
- .boardcfg_data : {} palign(128) > DDR0
- .sysmem : {} > DDR0
- .stack : {} align(4) > DDR0
+
+ .bss : {} align(8) > DDR0
+ .far : {} align(8) > DDR0
+ .data : {} palign(128)> MSMC3
+ .boardcfg_data : {} palign(128) > MSMC3
+ .sysmem : {} align(8) > MSMC3
+ .stack : {} align(8) > MSMC3 (HIGH)
+
/* SA sections */
- .scBufs : {} align(4) > DDR0
- .saSrcBuffers : {} align(4) > DDR0
- .saDstBuffers : {} align(4) > DDR0
+ .scBufs : {} align(8) > DDR0
+ .saSrcBuffers : {} align(8) > DDR0
+ .saDstBuffers : {} align(8) > DDR0
- /* USB or any other LLD buffer for benchmarking */
+ /* LLD buffer for benchmarking */
.benchmark_buffer (NOLOAD) {} ALIGN (8) > DDR0
-/* Additional sections settings */
+ /* Additional sections settings */
} /* end of SECTIONS */