PDK-7718: Board: Fix for hyperflash stability issue at higher clock

 - Hyperflash operations are not stable at higher frequency on j7200 evm.
   Hyperbus datasheet recommends to enable the controller after clocks are stable.
   But hyperbus controller will be active while PLLs are being configured which is
   causing wrong MDLL code some times resulting data write failure.
   Resetting the hyperbus controller in board flash open to resync with PLL
   clocks configured.

diff --git a/packages/ti/board/src/flash/nor/hyperflash/nor_hyperflash.c b/packages/ti/board/src/flash/nor/hyperflash/nor_hyperflash.c
index 604fa14be937f6aa824e4cc37830ea51f68a3c6d..445c9c2dc0add32909f85561888cd279e8249d32 100755 (executable)
--- a/packages/ti/board/src/flash/nor/hyperflash/nor_hyperflash.c
+++ b/packages/ti/board/src/flash/nor/hyperflash/nor_hyperflash.c
@@ -32,6 +32,14 @@
  */\r
 \r
 #include <ti/board/src/flash/nor/hyperflash/nor_hyperflash.h>\r
  */\r
 \r
 #include <ti/board/src/flash/nor/hyperflash/nor_hyperflash.h>\r

+#if defined(j7200_evm)\r
+#include <ti/board/src/j7200_evm/include/board_clock.h>\r
+#include <ti/board/src/j7200_evm/include/board_utils.h>\r
+#else\r
+#include <ti/board/src/j721e_evm/include/board_clock.h>\r
+#include <ti/board/src/j721e_evm/include/board_utils.h>\r
+#endif\r
+#include <ti/drv/sciclient/sciclient.h>\r

 \r
 static NOR_HANDLE Nor_hpfOpen(uint32_t norIntf, uint32_t portNum, void *params);\r
 static void Nor_hpfClose(NOR_HANDLE handle);\r
 \r
 static NOR_HANDLE Nor_hpfOpen(uint32_t norIntf, uint32_t portNum, void *params);\r
 static void Nor_hpfClose(NOR_HANDLE handle);\r


@@ -132,6 +140,7 @@ static NOR_STATUS Nor_hpfReadId(NOR_Info *Nor_hpfInfo)
     uint16_t manfID, devID;\r
     uint16_t queryStr[3];\r
     uint32_t count = 0;\r
     uint16_t manfID, devID;\r
     uint16_t queryStr[3];\r
     uint32_t count = 0;\r

+    uint32_t idReadCount = 0;\r

 \r
     hpfObject = (HPF_Object *)Nor_hpfInfo->hwHandle;\r
 \r
 \r
     hpfObject = (HPF_Object *)Nor_hpfInfo->hwHandle;\r
 \r


@@ -151,13 +160,22 @@ static NOR_STATUS Nor_hpfReadId(NOR_Info *Nor_hpfInfo)
 \r
         if ((manfID == NOR_MANF_ID) && (devID == NOR_DEVICE_ID)\r
             && queryStr[0] == 'P' && queryStr[1] == 'R' && queryStr[2] == 'I')\r
 \r
         if ((manfID == NOR_MANF_ID) && (devID == NOR_DEVICE_ID)\r
             && queryStr[0] == 'P' && queryStr[1] == 'R' && queryStr[2] == 'I')\r

+        {\r
+            idReadCount++;\r
+        }\r
+        else\r
+        {\r
+            idReadCount = 0;\r
+        }\r
+        count++;\r
+\r
+        if(idReadCount >= 4)\r

         {\r
             Nor_hpfInfo->manufacturerId = manfID;\r
             Nor_hpfInfo->deviceId = devID;\r
             retVal = NOR_PASS;\r
             break;\r
         }\r
         {\r
             Nor_hpfInfo->manufacturerId = manfID;\r
             Nor_hpfInfo->deviceId = devID;\r
             retVal = NOR_PASS;\r
             break;\r
         }\r

-        count++;\r

     }\r
 \r
     HW_WR_REG16((hpfObject->baseAddr), NOR_CMD_RESET);\r
     }\r
 \r
     HW_WR_REG16((hpfObject->baseAddr), NOR_CMD_RESET);\r


@@ -180,10 +198,30 @@ NOR_HANDLE Nor_hpfOpen(uint32_t norIntf, uint32_t portNum, void *params)
     NOR_HANDLE              hpfHandle = 0;\r
     HPF_Params              hpfParams;  /* HyperFlash params structure */\r
     CSL_hyperbus_coreRegs   *hpbCoreRegs = (CSL_hyperbus_coreRegs *)CSL_FSS0_HPB_CTRL_BASE;\r
     NOR_HANDLE              hpfHandle = 0;\r
     HPF_Params              hpfParams;  /* HyperFlash params structure */\r
     CSL_hyperbus_coreRegs   *hpbCoreRegs = (CSL_hyperbus_coreRegs *)CSL_FSS0_HPB_CTRL_BASE;\r

+#if defined(SOC_J7200)\r
+    CSL_hyperbus_syscfgRegs *hpbSyscfgRegs = (CSL_hyperbus_syscfgRegs *)CSL_FSS0_HPB_SS_CFG_BASE;\r
+#endif\r

     int32_t retVal;\r
 \r
     if (gHpfObject.isOpen != TRUE)\r
     {\r
     int32_t retVal;\r
 \r
     if (gHpfObject.isOpen != TRUE)\r
     {\r

+        /* \r
+         * Hyperbus controller should be enabled after PLL clocks are stable for\r
+         * proper operation.\r
+         * Reset the hyperbus controller to re-intialize with PLL clocks configured.\r
+         */\r
+        Board_moduleClockDisable(TISCI_DEV_MCU_FSS0_HYPERBUS1P0_0);\r
+        Board_moduleClockEnable(TISCI_DEV_MCU_FSS0_HYPERBUS1P0_0);\r
+\r
+#if defined(SOC_J7200)\r
+        /* Wait for the MDLL to get locked */\r
+        while(!CSL_REG32_FEXT(&hpbSyscfgRegs->DLL_STAT_REG,\r
+               HYPERBUS_SYSCFG_DLL_STAT_REG_MDLL_LOCK));\r
+#else\r
+        /* MDLL Lock status is not proper on J721E. Need to rely on delay */\r
+        BOARD_delay(1000); // 1 msec delay to allow MDLL to get locked\r
+#endif\r
+\r

         /* Enabling hyperbus in FSS0 */\r
         CSL_REG32_WR(MCU_FSS0_SYSCONFIG, ENABLE_FSS0_HPB);\r
 \r
         /* Enabling hyperbus in FSS0 */\r
         CSL_REG32_WR(MCU_FSS0_SYSCONFIG, ENABLE_FSS0_HPB);\r
 \r

diff --git a/packages/ti/board/src/j7200_evm/include/board_clock.h b/packages/ti/board/src/j7200_evm/include/board_clock.h
index 543fe0c9a6983660b47803ab056ef3636d02556e..ab0d3c5b87d54beb5faddf733961105949a0a914 100644 (file)
--- a/packages/ti/board/src/j7200_evm/include/board_clock.h
+++ b/packages/ti/board/src/j7200_evm/include/board_clock.h
@@ -46,6 +46,24 @@ extern "C" {
 
 #include <ti/board/src/j7200_evm/include/board_internal.h>
 
 
 #include <ti/board/src/j7200_evm/include/board_internal.h>
 

+/**
+ * \brief Enables module clock
+ *
+ * \return  BOARD_SOK   - Clock enable sucessful. 
+ *          BOARD_FAIL  - Clock enable failed.
+ *
+ */
+Board_STATUS Board_moduleClockEnable(uint32_t moduleId);
+
+/**
+ * \brief Disables module clock
+ *
+ * \return  BOARD_SOK   - Clock disable successful.
+ *          BOARD_FAIL  - Clock disable failed.
+ *
+ */
+Board_STATUS Board_moduleClockDisable(uint32_t moduleId);
+

 #ifdef __cplusplus
 }
 #endif /* __cplusplus */
 #ifdef __cplusplus
 }
 #endif /* __cplusplus */

diff --git a/packages/ti/board/src/j721e_evm/include/board_clock.h b/packages/ti/board/src/j721e_evm/include/board_clock.h
index 4261d646eafe6f71e2bde8ee5160f6f78a03cff8..7d1897fb3a78b2c506216dd5d0f02b636b6f9282 100755 (executable)
--- a/packages/ti/board/src/j721e_evm/include/board_clock.h
+++ b/packages/ti/board/src/j721e_evm/include/board_clock.h
@@ -44,7 +44,25 @@
 extern "C" {
 #endif
 
 extern "C" {
 #endif
 

-#include "board_internal.h"
+#include <ti/board/src/j721e_evm/include/board_internal.h>
+
+/**
+ * \brief Enables module clock
+ *
+ * \return  BOARD_SOK   - Clock enable sucessful. 
+ *          BOARD_FAIL  - Clock enable failed.
+ *
+ */
+Board_STATUS Board_moduleClockEnable(uint32_t moduleId);
+
+/**
+ * \brief Disables module clock
+ *
+ * \return  BOARD_SOK   - Clock disable successful.
+ *          BOARD_FAIL  - Clock disable failed.
+ *
+ */
+Board_STATUS Board_moduleClockDisable(uint32_t moduleId);

 
 #ifdef __cplusplus
 }
 
 #ifdef __cplusplus
 }