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raw | patch | inline | side by side (parent: c884e40)
raw | patch | inline | side by side (parent: c884e40)
| author | M V Pratap Reddy <x0257344@ti.com> | |
| Sat, 12 Dec 2020 12:06:46 +0000 (17:36 +0530) | ||
| committer | M V Pratap Reddy <x0257344@ti.com> | |
| Sat, 12 Dec 2020 12:12:12 +0000 (17:42 +0530) |
- Increased the UART baudrate to 1.5mbps
- Enabled UART load support
- Enabled UART load support
diff --git a/packages/ti/board/src/am64x_evm/board_mmr.c b/packages/ti/board/src/am64x_evm/board_mmr.c
index 26639a041fc0c096b5077dff4e90735ce9972f27..5359cc131f92c6aa9080cf88abb11ece38b783ab 100644 (file)
#include <ti/csl/soc/am64x/src/cslr_mcu_pll_mmr.h>\r
#include "board_internal.h"\r
\r
-#define AVV_PASS (1U)\r
-#define AVV_FAIL (0U)\r
+#define BOARD_MMR_PASS (1U)\r
+#define BOARD_MMR_FAIL (0U)\r
\r
static const uint32_t main_ctrl_mmr_kick_offsets[]= { CSL_MAIN_CTRL_MMR_CFG0_LOCK0_KICK0,\r
CSL_MAIN_CTRL_MMR_CFG0_LOCK1_KICK0,\r
if(lock_state!= (uint32_t) target_state ){\r
//Could insert debug statement here\r
//printf("SAVV_DEBUG: Error in changing MMR lock state at address %llx", kick0 );\r
- return AVV_FAIL;\r
+ return BOARD_MMR_FAIL;\r
}\r
}\r
//Return pass if lock is already what we want or if changing lock succeeds\r
- return AVV_PASS;\r
+ return BOARD_MMR_PASS;\r
}\r
uint32_t generic_mmr_change_all_locks(mmr_lock_actions_t target_state, uint32_t base_addr, const uint32_t * offset_array, uint32_t array_size) {\r
uint32_t errors=0;\r
volatile uint32_t * kick0_ptr;\r
for(i=0;i<array_size;i++) {\r
kick0_ptr = (volatile uint32_t *) (base_addr + offset_array[i]);\r
- if(MMR_change_lock(target_state, kick0_ptr) == AVV_FAIL){\r
+ if(MMR_change_lock(target_state, kick0_ptr) == BOARD_MMR_FAIL){\r
errors++;\r
}\r
}\r
}\r
uint32_t MAIN_CTRL_MMR_change_all_locks(mmr_lock_actions_t target_state) {\r
uint32_t errors=generic_mmr_change_all_locks(target_state, (uint32_t) MAIN_MMR_BASE_ADDRESS, main_ctrl_mmr_kick_offsets, main_ctrl_mmr_kick_num);\r
- if(errors==0) { return AVV_PASS; }\r
- else { return AVV_FAIL; }\r
+ if(errors==0) { return BOARD_MMR_PASS; }\r
+ else { return BOARD_MMR_FAIL; }\r
}\r
//MCU_CTRL_MMR\r
uint32_t MCU_CTRL_MMR_unlock_all() {\r
}\r
uint32_t MCU_CTRL_MMR_change_all_locks(mmr_lock_actions_t target_state) {\r
uint32_t errors=generic_mmr_change_all_locks(target_state, (uint32_t) MCU_MMR_BASE_ADDRESS, mcu_ctrl_mmr_kick_offsets, mcu_ctrl_mmr_kick_num);\r
- if(errors==0) { return AVV_PASS; }\r
- else { return AVV_FAIL; }\r
+ if(errors==0) { return BOARD_MMR_PASS; }\r
+ else { return BOARD_MMR_FAIL; }\r
}\r
//MAIN_PLL_MMR\r
uint32_t MAIN_PLL_MMR_unlock_all() {\r
}\r
uint32_t MAIN_PLL_MMR_change_all_locks(mmr_lock_actions_t target_state) {\r
uint32_t errors=generic_mmr_change_all_locks(target_state, (uint32_t) MAIN_PLL_MMR_BASE_ADDRESS, main_pll_mmr_kick_offsets, main_pll_mmr_kick_num);\r
- if(errors==0) { return AVV_PASS; }\r
- else { return AVV_FAIL; }\r
+ if(errors==0) { return BOARD_MMR_PASS; }\r
+ else { return BOARD_MMR_FAIL; }\r
}\r
//MCU_PLL_MMR\r
uint32_t MCU_PLL_MMR_unlock_all() {\r
}\r
uint32_t MCU_PLL_MMR_change_all_locks(mmr_lock_actions_t target_state) {\r
uint32_t errors=generic_mmr_change_all_locks(target_state, (uint32_t) MCU_PLL_MMR_BASE_ADDRESS, mcu_pll_mmr_kick_offsets, mcu_pll_mmr_kick_num);\r
- if(errors==0) { return AVV_PASS; }\r
- else { return AVV_FAIL; }\r
+ if(errors==0) { return BOARD_MMR_PASS; }\r
+ else { return BOARD_MMR_FAIL; }\r
}\r
//MAIN_PADCONFIG_MMR\r
uint32_t MAIN_PADCONFIG_MMR_unlock_all() {\r
}\r
uint32_t MAIN_PADCONFIG_MMR_change_all_locks(mmr_lock_actions_t target_state) {\r
uint32_t errors=generic_mmr_change_all_locks(target_state, (uint32_t) MAIN_PADCONFIG_MMR_BASE_ADDRESS, main_padcfg_mmr_kick_offsets, main_padcfg_mmr_kick_num);\r
- if(errors==0) { return AVV_PASS; }\r
- else { return AVV_FAIL; }\r
+ if(errors==0) { return BOARD_MMR_PASS; }\r
+ else { return BOARD_MMR_FAIL; }\r
}\r
//MCU_PADCONFIG_MMR\r
uint32_t MCU_PADCONFIG_MMR_unlock_all() {\r
}\r
uint32_t MCU_PADCONFIG_MMR_change_all_locks(mmr_lock_actions_t target_state) {\r
uint32_t errors=generic_mmr_change_all_locks(target_state, (uint32_t) MCU_PADCONFIG_MMR_BASE_ADDRESS, mcu_padcfg_mmr_kick_offsets, mcu_padcfg_mmr_kick_num);\r
- if(errors==0) { return AVV_PASS; }\r
- else { return AVV_FAIL; }\r
+ if(errors==0) { return BOARD_MMR_PASS; }\r
+ else { return BOARD_MMR_FAIL; }\r
}\r
\r
/**\r
diff --git a/packages/ti/board/utils/uniflash/target/build/uart_make.mk b/packages/ti/board/utils/uniflash/target/build/uart_make.mk
index b27cbc1c6a27db5e25908e108c2317862c5b39b8..ae00cf76d1f824e8c12852e666441646daf24faa 100644 (file)
EXTERNAL_LNKCMD_FILE_LOCAL = $(UNIFLASH_BASE_DIR)/soc/k3/linker_am64x.cmd
endif
+ifeq ($(BOARD), $(filter $(BOARD), am64x_evm))
+SRCS_ASM_COMMON += ufp_init.asm ufp_misc.asm
+endif
+
ifeq ($(BOARD), $(filter $(BOARD), tpr12_evm))
SRCS_COMMON += qspi.c
EXTERNAL_LNKCMD_FILE_LOCAL = $(UNIFLASH_BASE_DIR)/soc/$(SOC)/linker.cmd
diff --git a/packages/ti/board/utils/uniflash/target/include/flash_programmer.h b/packages/ti/board/utils/uniflash/target/include/flash_programmer.h
index 3436dd472d34da2bd192064bb4e915d87d999189..6671e665eafa715b2c42873228a7a5dd73ee462d 100644 (file)
#endif
#if defined(am64x_evm)
-#define MAX_BAUDRATE_SUPPORTED (0x0U)
-#define MAX_BAUDRATE_SUPPORTED_LINUX (0x0U)
+#define MAX_BAUDRATE_SUPPORTED (0x8U) /* 1500000 */
+#define MAX_BAUDRATE_SUPPORTED_LINUX (0x8U) /* 1500000 */
#define OSPI_FLASH
#define EMMC_FLASH
diff --git a/packages/ti/board/utils/uniflash/target/soc/k3/linker_am64x.cmd b/packages/ti/board/utils/uniflash/target/soc/k3/linker_am64x.cmd
index 5d41e5c49057e868bc8f197890b91cc4413afeae..478c52cd343a66e3019df031de75fbfcca9e8b4d 100644 (file)
/*----------------------------------------------------------------------------*/
/* File: linker.cmd */
-/* Description: */
-/* Link command file for Maxwell SBL */
+/* Description: */
+/* Link command file for AM64x Uniflash Flash programmer */
/* */
-/* Platform: R5 Cores on AM65xx */
-/* (c) Texas Instruments 2018, All rights reserved. */
+/* Platform: R5 Cores on AM64xx */
+/* (c) Texas Instruments 2020, All rights reserved. */
/*----------------------------------------------------------------------------*/
--retain="*(.bootCode)"
--retain="*(.startupCode)"
--fill_value=0
--stack_size=0x2000
--heap_size=0x2000
---entry_point=_resetvectors /* SBL entry in SBL_init.asm */
+--entry_point=_ufpResetVectors
-stack 0x2000 /* SOFTWARE STACK SIZE */
-heap 0x2000 /* HEAP AREA SIZE */
{
/* Reset Vectors base address(RESET_VECTORS) should be 64 bytes aligned */
RESET_VECTORS (X) : origin=0x70000000 length=0x100
- /* MCU0 memory used for SBL. Available to app for dynamic use ~160KB */
- /* RBL uses 0x41C58000 and beyond. SBL, at load cannot cross this */
- OCMRAM_SBL (RWIX) : origin=0x70000100 length=0x3E000-0x100
-
- /* Used by SBL at runtime to load SYSFW. Available to app for dynamic use */
- OCMRAM_SBL_SYSFW (RWIX) : origin=0x7003E000 length=0x40000
+ OCMRAM_UFP (RWIX) : origin=0x70000100 length=0x3E000-0x100
+ OCMRAM_UFP_SYSFW (RWIX) : origin=0x7003E000 length=0x40000
} /* end of MEMORY */
/* 'intvecs' and 'intc_text' sections shall be placed within */
/* a range of +\- 16 MB */
.rstvectors : {} palign(8) > RESET_VECTORS
- .bootCode : {} palign(8) > OCMRAM_SBL
- .startupCode : {} palign(8) > OCMRAM_SBL
- .startupData : {} palign(8) > OCMRAM_SBL, type = NOINIT
- .sbl_profile_info : {} palign(8) > RESET_VECTORS (HIGH)
- .text : {} palign(8) > OCMRAM_SBL
- .const : {} palign(8) > OCMRAM_SBL
- .cinit : {} palign(8) > OCMRAM_SBL
- .pinit : {} palign(8) > OCMRAM_SBL
- .boardcfg_data : {} palign(128) > OCMRAM_SBL
+ .bootCode : {} palign(8) > OCMRAM_UFP
+ .startupCode : {} palign(8) > OCMRAM_UFP
+ .startupData : {} palign(8) > OCMRAM_UFP, type = NOINIT
+ .text : {} palign(8) > OCMRAM_UFP
+ .const : {} palign(8) > OCMRAM_UFP
+ .cinit : {} palign(8) > OCMRAM_UFP
+ .pinit : {} palign(8) > OCMRAM_UFP
+ .boardcfg_data : {} palign(128) > OCMRAM_UFP
- .data : {} palign(128) > OCMRAM_SBL
- .bss : {} align(4) > OCMRAM_SBL
- .sysmem : {} > OCMRAM_SBL
+ .data : {} palign(128) > OCMRAM_UFP
+ .bss : {} align(4) > OCMRAM_UFP
+ .sysmem : {} > OCMRAM_UFP
- .stack : {} align(4) > OCMRAM_SBL (HIGH)
- .irqStack : {. = . + __IRQ_STACK_SIZE;} align(4) > OCMRAM_SBL (HIGH)
+ .stack : {} align(4) > OCMRAM_UFP (HIGH)
+ .irqStack : {. = . + __IRQ_STACK_SIZE;} align(4) > OCMRAM_UFP (HIGH)
RUN_START(__IRQ_STACK_START)
RUN_END(__IRQ_STACK_END)
- .fiqStack : {. = . + __FIQ_STACK_SIZE;} align(4) > OCMRAM_SBL (HIGH)
+ .fiqStack : {. = . + __FIQ_STACK_SIZE;} align(4) > OCMRAM_UFP (HIGH)
RUN_START(__FIQ_STACK_START)
RUN_END(__FIQ_STACK_END)
- .abortStack : {. = . + __ABORT_STACK_SIZE;} align(4) > OCMRAM_SBL (HIGH)
+ .abortStack : {. = . + __ABORT_STACK_SIZE;} align(4) > OCMRAM_UFP (HIGH)
RUN_START(__ABORT_STACK_START)
RUN_END(__ABORT_STACK_END)
- .undStack : {. = . + __UND_STACK_SIZE;} align(4) > OCMRAM_SBL (HIGH)
+ .undStack : {. = . + __UND_STACK_SIZE;} align(4) > OCMRAM_UFP (HIGH)
RUN_START(__UND_STACK_START)
RUN_END(__UND_STACK_END)
- .svcStac : {. = . + __SVC_STACK_SIZE;} align(4) > OCMRAM_SBL (HIGH)
+ .svcStac : {. = . + __SVC_STACK_SIZE;} align(4) > OCMRAM_UFP (HIGH)
RUN_START(__SVC_STACK_START)
RUN_END(__SVC_STACK_END)
- .firmware : {} palign(8) > OCMRAM_SBL_SYSFW
+ .firmware : {} palign(8) > OCMRAM_UFP_SYSFW
} /* end of SECTIONS */
diff --git a/packages/ti/board/utils/uniflash/target/soc/k3/soc.c b/packages/ti/board/utils/uniflash/target/soc/k3/soc.c
index ce9f2eab6c68da52c3cba8a013fbec049b7cbf8d..61643232fef1769c3b24dd8551ba1674aa8054a9 100755 (executable)
#if defined(am64x_evm)
static int32_t UFP_isNoBootEnabled(void)
{
- return (TRUE);
+ uint32_t mainDevStat;
+
+ mainDevStat = HW_RD_REG32(UFP_MAIN_DEVSTAT_ADDR);
+
+ if((mainDevStat & UFP_MAIN_DEVSTAT_NOBOOT_MASK) == UFP_MAIN_DEVSTAT_NOBOOT_CFG)
+ {
+ return (TRUE);
+ }
+
+ return (FALSE);
}
#else
static int32_t UFP_isNoBootEnabled(void)
return (-1);
}
-#if !defined(am64x_evm)
+#if defined(SOC_AM64X)
+ Sciclient_pmSetModuleState(TISCI_DEV_RTI8,
+ TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF,
+ TISCI_MSG_FLAG_AOP,
+ SCICLIENT_SERVICE_WAIT_FOREVER);
+ Sciclient_pmSetModuleState(TISCI_DEV_RTI9,
+ TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF,
+ TISCI_MSG_FLAG_AOP,
+ SCICLIENT_SERVICE_WAIT_FOREVER);
+ Sciclient_pmSetModuleState(TISCI_DEV_RTI10,
+ TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF,
+ TISCI_MSG_FLAG_AOP,
+ SCICLIENT_SERVICE_WAIT_FOREVER);
+ Sciclient_pmSetModuleState(TISCI_DEV_RTI11,
+ TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF,
+ TISCI_MSG_FLAG_AOP,
+ SCICLIENT_SERVICE_WAIT_FOREVER);
+ Sciclient_pmSetModuleState(TISCI_DEV_MCU_RTI0,
+ TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF,
+ TISCI_MSG_FLAG_AOP,
+ SCICLIENT_SERVICE_WAIT_FOREVER);
+#else
/* RTI seems to be turned on by ROM. Turning it off so that Power domain can transition */
Sciclient_pmSetModuleState(TISCI_DEV_MCU_RTI0,
TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF,
diff --git a/packages/ti/board/utils/uniflash/target/soc/k3/soc_k3.h b/packages/ti/board/utils/uniflash/target/soc/k3/soc_k3.h
index 2ed3bf9b352c7d8059ae12528f7c228035f79f48..10a13ce1e8e0d9ca5ff3b336538a7ee6c149d0c2 100755 (executable)
#elif defined(SOC_AM65XX)
#define UFP_MCU_ARMSS_ATCM_BASE (CSL_MCU_ATCM_BASE)
#elif defined(SOC_AM64X)
-#define UFP_MCU_ARMSS_ATCM_BASE (0) // AM64x_TODO: Need check this address during the verification
+#define UFP_MCU_ARMSS_ATCM_BASE (CSL_R5FSS0_ATCM_BASE)
#endif
#define UFP_ROM_UART_MODULE_INPUT_CLK (48000000U)
+#if defined (SOC_AM64X)
+#define UFP_SYSFW_UART_MODULE_INPUT_CLK (48000000U)
+#else
#define UFP_SYSFW_UART_MODULE_INPUT_CLK (96000000U)
+#endif
#define UFP_SYSFW_NOT_PROCESSED (0x0U)
#define UFP_SYSFW_CLEAR_TEXT (0x55555555u)
#define UFP_MAIN_DEVSTAT_NOBOOT_MASK (0xEFU)
#define UFP_WKUP_DEVSTAT_NOBOOT_MASK (0xF8U)
#elif defined(SOC_AM64X)
-#define UFP_MAIN_DEVSTAT_NOBOOT_MASK (0xEFU)
+#define UFP_MAIN_DEVSTAT_NOBOOT_CFG (0xFBU)
+#define UFP_MAIN_DEVSTAT_NOBOOT_MASK (0xFFU)
#else
#define UFP_MAIN_DEVSTAT_NOBOOT_CFG (0)
#define UFP_WKUP_DEVSTAT_NOBOOT_CFG (0)
diff --git a/packages/ti/board/utils/uniflash/target/soc/k3/ufp_init.asm b/packages/ti/board/utils/uniflash/target/soc/k3/ufp_init.asm
--- /dev/null
@@ -0,0 +1,95 @@
+;******************************************************************************
+;* *
+;* Copyright (c) 2020 Texas Instruments Incorporated *
+;* http://www.ti.com/ *
+;* *
+;* Redistribution and use in source and binary forms, with or without *
+;* modification, are permitted provided that the following conditions *
+;* are met: *
+;* *
+;* Redistributions of source code must retain the above copyright *
+;* notice, this list of conditions and the following disclaimer. *
+;* *
+;* Redistributions in binary form must reproduce the above copyright *
+;* notice, this list of conditions and the following disclaimer in *
+;* the documentation and/or other materials provided with the *
+;* distribution. *
+;* *
+;* Neither the name of Texas Instruments Incorporated nor the names *
+;* of its contributors may be used to endorse or promote products *
+;* derived from this software without specific prior written *
+;* permission. *
+;* *
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS *
+;* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT *
+;* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR *
+;* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT *
+;* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, *
+;* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT *
+;* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, *
+;* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY *
+;* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT *
+;* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE *
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *
+;* *
+;******************************************************************************
+;****************************************************************************
+; Setup Reset Vectors
+;****************************************************************************
+ .arm
+
+ .sect ".rstvectors"
+ .global _ufpResetVectors
+
+_ufpResetVectors:
+ .asmfunc
+ LDR pc, ufpEntry ; Reset
+ B _ufpLoopForever ; Undefined Instruction
+ B _ufpLoopForever ; SVC call
+ B _ufpLoopForever ; Prefetch abort
+ B _ufpLoopForever ; Data abort
+ B _ufpLoopForever ; Hypervisor
+ B _ufpLoopForever ; IRQ
+ B _ufpLoopForever ; FIQ
+
+ufpEntry .long _ufpEntry
+ .endasmfunc
+
+;****************************************************************************
+; UFP Entry
+;****************************************************************************
+ .def _ufpEntry
+ .ref _c_int00
+ .ref _ufpTcmEn
+
+_c_int00_addr .long _c_int00
+_ufpTcmEnAddr .long _ufpTcmEn
+
+_ufpEntry:
+ .asmfunc
+
+ MRC p15, #0, r1, c0, c0, #5
+ BFC r1, #8, #24
+ CMP r1, #0
+ BNE _ufpLoopForever
+
+ ADR r1, _ufpTestStackBase
+ BIC r1, r1, #0xf
+ MOV sp, r1
+
+ LDR r1, _ufpTcmEnAddr
+ BLX r1
+
+ LDR r1, _c_int00_addr
+ BLX r1
+
+_ufpLoopForever:
+ WFI
+ B _ufpLoopForever
+
+ .endasmfunc
+
+_ufpTestStackTop:
+ .space 64
+_ufpTestStackBase:
+
diff --git a/packages/ti/board/utils/uniflash/target/soc/k3/ufp_misc.asm b/packages/ti/board/utils/uniflash/target/soc/k3/ufp_misc.asm
--- /dev/null
@@ -0,0 +1,130 @@
+;******************************************************************************
+;* *
+;* Copyright (c) 2020 Texas Instruments Incorporated *
+;* http://www.ti.com/ *
+;* *
+;* Redistribution and use in source and binary forms, with or without *
+;* modification, are permitted provided that the following conditions *
+;* are met: *
+;* *
+;* Redistributions of source code must retain the above copyright *
+;* notice, this list of conditions and the following disclaimer. *
+;* *
+;* Redistributions in binary form must reproduce the above copyright *
+;* notice, this list of conditions and the following disclaimer in *
+;* the documentation and/or other materials provided with the *
+;* distribution. *
+;* *
+;* Neither the name of Texas Instruments Incorporated nor the names *
+;* of its contributors may be used to endorse or promote products *
+;* derived from this software without specific prior written *
+;* permission. *
+;* *
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS *
+;* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT *
+;* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR *
+;* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT *
+;* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, *
+;* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT *
+;* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, *
+;* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY *
+;* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT *
+;* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE *
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *
+;* *
+;******************************************************************************
+ .arm
+
+;****************************************************************************
+; UFP Read ATCM Region Register
+;****************************************************************************
+ .sect ".text"
+ .global _ufpTcmEn
+
+_ufpTcmEn:
+ .asmfunc
+ ;Enable ATCM @0x0
+ MRC p15, #0, r0, c9, c1, #1
+ BFC r0, #12, #20
+ ORR r0, r0, #0x1
+ MCR p15, #0, r0, c9, c1, #1
+
+ ;Enable BTCM @0x41010000
+ LDR r1, ufp_btcm_base
+ MRC p15, #0, r0, c9, c1, #0
+ BFC r0, #12, #20
+ ORR r0, r0, r1
+ ORR r0, r0, #0x1
+ MCR p15, #0, r0, c9, c1, #0
+
+ BX lr
+
+ufp_btcm_base .word 0x41010000
+
+ .endasmfunc
+
+
+;****************************************************************************
+; UFP Read ATCM Size Register
+;****************************************************************************
+ .sect ".text"
+ .global ufpAtcmSize
+
+ufpAtcmSize:
+ .asmfunc
+ mrc p15, #0, r0, c9, c1, #1 ;; Read ATCM region Register
+ and r0, r0, #0xFF ;; Extract ATCM region Register
+ lsr r0, r0, #0x2 ;; Extract ATCM region Register
+ mov r1, #0x200 ;; Calculate size of ATCM in bytes
+ lsl r0, r1, r0 ;; Calculate size of ATCM in bytes
+
+ BX lr
+
+ .endasmfunc
+
+;****************************************************************************
+; UFP Read BTCM Size Register
+;****************************************************************************
+ .sect ".text"
+ .global ufpBtcmSize
+
+ufpBtcmSize:
+ .asmfunc
+ mrc p15, #0, r0, c9, c1, #0 ;; Read BTCM region Register
+ and r0, r0, #0xFF ;; Extract BTCM region Register
+ lsr r0, r0, #0x2 ;; Extract BTCM region Register
+ mov r1, #0x200 ;; Calculate size of BTCM in bytes
+ lsl r0, r1, r0 ;; Calculate size of BTCM in bytes
+
+ BX lr
+
+ .endasmfunc
+
+
+;****************************************************************************
+; Supress Klockworks Ptr Errors
+;****************************************************************************
+ .sect ".text"
+ .global uint32_to_void_ptr
+ .global uint32_to_const_void_ptr
+ .global uint32_to_uint32_ptr
+ .global uint32_ptr_to_void_ptr
+ .global const_uint8_ptr_to_void_ptr
+ .global uint32_to_int32
+ .global uint64_to_uint32
+ .global uint64_to_int32
+
+uint32_to_int32:
+uint32_to_void_ptr:
+uint32_to_const_void_ptr:
+uint32_to_uint32_ptr:
+uint32_ptr_to_void_ptr:
+const_uint8_ptr_to_void_ptr:
+uint64_to_uint32:
+uint64_to_int32:
+
+ .asmfunc
+
+ BX lr
+ .endasmfunc
+