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raw | patch | inline | side by side (parent: c12e766)
author | Rishabh Garg <rishabh@ti.com> | |
Mon, 23 May 2022 16:51:48 +0000 (22:21 +0530) | ||
committer | Rishabh Garg <rishabh@ti.com> | |
Mon, 23 May 2022 16:51:48 +0000 (22:21 +0530) |
Signed-off-by: Rishabh Garg <rishabh@ti.com>
99 files changed:
diff --git a/packages/ti/build/am335x/config_am335x_a8.bld b/packages/ti/build/am335x/config_am335x_a8.bld
+++ /dev/null
@@ -1,184 +0,0 @@
-/*
-* Copyright (c) 2016, Texas Instruments Incorporated
-* All rights reserved.
-*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions
-* are met:
-*
-* * Redistributions of source code must retain the above copyright
-* notice, this list of conditions and the following disclaimer.
-*
-* * Redistributions in binary form must reproduce the above copyright
-* notice, this list of conditions and the following disclaimer in the
-* documentation and/or other materials provided with the distribution.
-*
-* * Neither the name of Texas Instruments Incorporated nor the names of
-* its contributors may be used to endorse or promote products derived
-* from this software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
-* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
-* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
-* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
-
-/*
- * ======== config_am335x_a8.bld ========
- * Build configuration script for BSP drivers
- */
-/* load the required modules for the configuration */
-var A8 = xdc.useModule('gnu.targets.arm.A8F');
-/* A8 compiler directory path */
-A8.rootDir = java.lang.System.getenv("CGTOOLS_A8");
-
-/* Read the current board */
-var CurrentPlatform = java.lang.System.getenv("BOARD");
-
-if (CurrentPlatform == null)
-{
- /* The env variable is probably not set while running inside CCS */
- CurrentPlatform = java.lang.System.getProperty("BOARD");
-}
-
-/*add bspLib to support SemiHosting to enable system_printf on A8*/
-/* GCC bare metal targets */
-var gccArmTargets = xdc.loadPackage('gnu.targets.arm');
-gccArmTargets.A8F.bspLib = "rdimon";
-
-
-/*
-Memory map
-
-DDR: 0x80000000 (Ist 512MB - Cached)
-
-NOTE: APP_CACHED_DATA_BLK1_MEM is used to route sections which needs to be in a
-separate section preferably at the end of 512 MB memory.
-For example:
-Frame buffer memory can be less at runtime depending on boards with lesser DDR (as in TDA 12x12 POP boards).
-If the same is routed to APP_CACHED_DATA_MEM section then the linker will
-place the frame buffer before other data section and the other data will fall into
-region outside the DDR in the board. Hence separate section is used!!
-
-+-----------------------------+
-| APP_CODE_MEM | 2MB
-+-----------------------------+
-| APP_CACHED_DATA_BLK0_MEM | 1MB
-+-----------------------------+
-| APP_CACHED_DATA_MEM | 20MB
-+-----------------------------+
-| APP_CACHED_DATA_BLK1_MEM | 244MB
-+-----------------------------+
-| APP_CACHED_DATA_BLK2_MEM | 128MB
-+-----------------------------+
-| NOT USED | Remaining MB
-+-----------------------------+
-
-DDR: 0xA0000000 (2nd 512MB - Non-Cached)
-+-----------------------------+
-| |
-| APP_UNCACHED_DATA_BLK3_MEM | 2MB
-+-----------------------------+
-| NOT USED | Remaining MB
-+-----------------------------+
-
-*/
-
-var KB=1024;
-var MB=KB*KB;
-
-var DDR3_ADDR_0;
-var DDR3_ADDR_1;
-
-var APP_CODE_ADDR;
-var APP_CODE_SIZE;
-
-var APP_CACHED_DATA_ADDR;
-var APP_CACHED_DATA_SIZE;
-
-var APP_UNCACHED_DATA_BLK3_ADDR;
-var APP_UNCACHED_DATA_BLK3_SIZE;
-
-var APP_CACHED_DATA_BLK0_ADDR;
-var APP_CACHED_DATA_BLK0_SIZE;
-
-var APP_CACHED_DATA_BLK1_ADDR;
-var APP_CACHED_DATA_BLK1_SIZE;
-
-var APP_CACHED_DATA_BLK2_ADDR;
-var APP_CACHED_DATA_BLK2_SIZE;
-
-DDR3_ADDR_0 = 0x80000000;
-DDR3_ADDR_1 = 0xA0000000;
-
-APP_CODE_SIZE = 2*MB;
-APP_CACHED_DATA_BLK0_SIZE = 1*MB;
-APP_CACHED_DATA_SIZE = 20*MB;
-APP_CACHED_DATA_BLK1_SIZE = 244*MB;
-APP_CACHED_DATA_BLK2_SIZE = 128*MB;
-APP_UNCACHED_DATA_BLK3_SIZE = 2*MB;
-
-APP_CODE_ADDR = DDR3_ADDR_0;
-APP_CACHED_DATA_BLK0_ADDR = APP_CODE_ADDR + APP_CODE_SIZE;
-APP_CACHED_DATA_ADDR = APP_CACHED_DATA_BLK0_ADDR + APP_CACHED_DATA_BLK0_SIZE;
-APP_CACHED_DATA_BLK1_ADDR = APP_CACHED_DATA_ADDR + APP_CACHED_DATA_SIZE;
-APP_CACHED_DATA_BLK2_ADDR = APP_CACHED_DATA_BLK1_ADDR + APP_CACHED_DATA_BLK1_SIZE;
-APP_UNCACHED_DATA_BLK3_ADDR = DDR3_ADDR_1;
-
-
-
-myplatform = "ti.platforms.evmAM3359";
-
-
-Build.platformTable[myplatform] =
-{
- externalMemoryMap:
- [
- ["APP_CODE_MEM", {
- comment : "APP_CODE_MEM",
- name : "APP_CODE_MEM",
- base : APP_CODE_ADDR,
- len : APP_CODE_SIZE
- }],
- ["APP_CACHED_DATA_BLK0_MEM", {
- comment : "APP_CACHED_DATA_BLK0_MEM",
- name : "APP_CACHED_DATA_BLK0_MEM",
- base : APP_CACHED_DATA_BLK0_ADDR,
- len : APP_CACHED_DATA_BLK0_SIZE
- }],
- ["APP_CACHED_DATA_MEM", {
- comment : "APP_CACHED_DATA_MEM",
- name : "APP_CACHED_DATA_MEM",
- base : APP_CACHED_DATA_ADDR,
- len : APP_CACHED_DATA_SIZE
- }],
- ["APP_UNCACHED_DATA_BLK3_MEM", {
- comment : "APP_UNCACHED_DATA_BLK3_MEM",
- name : "APP_UNCACHED_DATA_BLK3_MEM",
- base : APP_UNCACHED_DATA_BLK3_ADDR,
- len : APP_UNCACHED_DATA_BLK3_SIZE
- }],
- ["APP_CACHED_DATA_BLK1_MEM", {
- comment : "APP_CACHED_DATA_BLK1_MEM",
- name : "APP_CACHED_DATA_BLK1_MEM",
- base : APP_CACHED_DATA_BLK1_ADDR,
- len : APP_CACHED_DATA_BLK1_SIZE
- }],
- ["APP_CACHED_DATA_BLK2_MEM", {
- comment : "APP_CACHED_DATA_BLK2_MEM",
- name : "APP_CACHED_DATA_BLK2_MEM",
- base : APP_CACHED_DATA_BLK2_ADDR,
- len : APP_CACHED_DATA_BLK2_SIZE
- }],
- ],
- codeMemory: "APP_CODE_MEM",
- dataMemory: "APP_CACHED_DATA_MEM",
- stackMemory: "APP_CACHED_DATA_MEM"
-};
diff --git a/packages/ti/build/am437x/config_am437x_a9.bld b/packages/ti/build/am437x/config_am437x_a9.bld
+++ /dev/null
@@ -1,181 +0,0 @@
-/*
-* Copyright (c) 2016, Texas Instruments Incorporated
-* All rights reserved.
-*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions
-* are met:
-*
-* * Redistributions of source code must retain the above copyright
-* notice, this list of conditions and the following disclaimer.
-*
-* * Redistributions in binary form must reproduce the above copyright
-* notice, this list of conditions and the following disclaimer in the
-* documentation and/or other materials provided with the distribution.
-*
-* * Neither the name of Texas Instruments Incorporated nor the names of
-* its contributors may be used to endorse or promote products derived
-* from this software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
-* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
-* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
-* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
-
-/*
- * ======== config_am437x_a9.bld ========
- * Build configuration script for BSP drivers
- */
-/* load the required modules for the configuration */
-var A9 = xdc.useModule('gnu.targets.arm.A9F');
-/* A9 compiler directory path */
-A9.rootDir = java.lang.System.getenv("CGTOOLS_A9");
-
-/* Read the current board */
-var CurrentPlatform = java.lang.System.getenv("BOARD");
-
-if (CurrentPlatform == null)
-{
- /* The env variable is probably not set while running inside CCS */
- CurrentPlatform = java.lang.System.getProperty("BOARD");
-}
-
-/*add bspLib to support SemiHosting to enable system_printf on A9*/
-/* GCC bare metal targets */
-var gccArmTargets = xdc.loadPackage('gnu.targets.arm');
-gccArmTargets.A9F.bspLib = "rdimon";
-
-/*
-Memory map
-
-DDR: 0x80000000 (Ist 512MB - Cached)
-
-NOTE: APP_CACHED_DATA_BLK1_MEM is used to route sections which needs to be in a
-separate section preferably at the end of 512 MB memory.
-For example:
-Frame buffer memory can be less at runtime depending on boards with lesser DDR (as in TDA 12x12 POP boards).
-If the same is routed to APP_CACHED_DATA_MEM section then the linker will
-place the frame buffer before other data section and the other data will fall into
-region outside the DDR in the board. Hence separate section is used!!
-
-+-----------------------------+
-| APP_CODE_MEM | 2MB
-+-----------------------------+
-| APP_CACHED_DATA_BLK0_MEM | 1MB
-+-----------------------------+
-| APP_CACHED_DATA_MEM | 20MB
-+-----------------------------+
-| APP_CACHED_DATA_BLK1_MEM | 244MB
-+-----------------------------+
-| APP_CACHED_DATA_BLK2_MEM | 128MB
-+-----------------------------+
-| NOT USED | Remaining MB
-+-----------------------------+
-
-DDR: 0xA0000000 (2nd 512MB - Non-Cached)
-+-----------------------------+
-| |
-| APP_UNCACHED_DATA_BLK3_MEM | 2MB
-+-----------------------------+
-| NOT USED | Remaining MB
-+-----------------------------+
-
-*/
-
-var KB=1024;
-var MB=KB*KB;
-
-var DDR3_ADDR_0;
-var DDR3_ADDR_1;
-
-var APP_CODE_ADDR;
-var APP_CODE_SIZE;
-
-var APP_CACHED_DATA_ADDR;
-var APP_CACHED_DATA_SIZE;
-
-var APP_UNCACHED_DATA_BLK3_ADDR;
-var APP_UNCACHED_DATA_BLK3_SIZE;
-
-var APP_CACHED_DATA_BLK0_ADDR;
-var APP_CACHED_DATA_BLK0_SIZE;
-
-var APP_CACHED_DATA_BLK1_ADDR;
-var APP_CACHED_DATA_BLK1_SIZE;
-
-var APP_CACHED_DATA_BLK2_ADDR;
-var APP_CACHED_DATA_BLK2_SIZE;
-
-DDR3_ADDR_0 = 0x80000000;
-DDR3_ADDR_1 = 0xA0000000;
-
-APP_CODE_SIZE = 2*MB;
-APP_CACHED_DATA_BLK0_SIZE = 1*MB;
-APP_CACHED_DATA_SIZE = 20*MB;
-APP_CACHED_DATA_BLK1_SIZE = 244*MB;
-APP_CACHED_DATA_BLK2_SIZE = 128*MB;
-APP_UNCACHED_DATA_BLK3_SIZE = 2*MB;
-
-APP_CODE_ADDR = DDR3_ADDR_0;
-APP_CACHED_DATA_BLK0_ADDR = APP_CODE_ADDR + APP_CODE_SIZE;
-APP_CACHED_DATA_ADDR = APP_CACHED_DATA_BLK0_ADDR + APP_CACHED_DATA_BLK0_SIZE;
-APP_CACHED_DATA_BLK1_ADDR = APP_CACHED_DATA_ADDR + APP_CACHED_DATA_SIZE;
-APP_CACHED_DATA_BLK2_ADDR = APP_CACHED_DATA_BLK1_ADDR + APP_CACHED_DATA_BLK1_SIZE;
-APP_UNCACHED_DATA_BLK3_ADDR = DDR3_ADDR_1;
-
-
-myplatform = "ti.platforms.evmAM437X";
-
-Build.platformTable[myplatform] =
-{
- externalMemoryMap:
- [
- ["APP_CODE_MEM", {
- comment : "APP_CODE_MEM",
- name : "APP_CODE_MEM",
- base : APP_CODE_ADDR,
- len : APP_CODE_SIZE
- }],
- ["APP_CACHED_DATA_BLK0_MEM", {
- comment : "APP_CACHED_DATA_BLK0_MEM",
- name : "APP_CACHED_DATA_BLK0_MEM",
- base : APP_CACHED_DATA_BLK0_ADDR,
- len : APP_CACHED_DATA_BLK0_SIZE
- }],
- ["APP_CACHED_DATA_MEM", {
- comment : "APP_CACHED_DATA_MEM",
- name : "APP_CACHED_DATA_MEM",
- base : APP_CACHED_DATA_ADDR,
- len : APP_CACHED_DATA_SIZE
- }],
- ["APP_UNCACHED_DATA_BLK3_MEM", {
- comment : "APP_UNCACHED_DATA_BLK3_MEM",
- name : "APP_UNCACHED_DATA_BLK3_MEM",
- base : APP_UNCACHED_DATA_BLK3_ADDR,
- len : APP_UNCACHED_DATA_BLK3_SIZE
- }],
- ["APP_CACHED_DATA_BLK1_MEM", {
- comment : "APP_CACHED_DATA_BLK1_MEM",
- name : "APP_CACHED_DATA_BLK1_MEM",
- base : APP_CACHED_DATA_BLK1_ADDR,
- len : APP_CACHED_DATA_BLK1_SIZE
- }],
- ["APP_CACHED_DATA_BLK2_MEM", {
- comment : "APP_CACHED_DATA_BLK2_MEM",
- name : "APP_CACHED_DATA_BLK2_MEM",
- base : APP_CACHED_DATA_BLK2_ADDR,
- len : APP_CACHED_DATA_BLK2_SIZE
- }],
- ],
- codeMemory: "APP_CODE_MEM",
- dataMemory: "APP_CACHED_DATA_MEM",
- stackMemory: "APP_CACHED_DATA_MEM"
-};
diff --git a/packages/ti/build/am571x/config_am571x.bld b/packages/ti/build/am571x/config_am571x.bld
+++ /dev/null
@@ -1,157 +0,0 @@
-/*
-* Copyright (c) 2016, Texas Instruments Incorporated
-* All rights reserved.
-*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions
-* are met:
-*
-* * Redistributions of source code must retain the above copyright
-* notice, this list of conditions and the following disclaimer.
-*
-* * Redistributions in binary form must reproduce the above copyright
-* notice, this list of conditions and the following disclaimer in the
-* documentation and/or other materials provided with the distribution.
-*
-* * Neither the name of Texas Instruments Incorporated nor the names of
-* its contributors may be used to endorse or promote products derived
-* from this software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
-* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
-* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
-* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
-/*
- * ======== config.bld ========
- * Build configuration script for BSP drivers
- */
-
-/* load the required modules for the configuration */
-var M4 = xdc.useModule('ti.targets.arm.elf.M4');
-/* M4 compiler directory path */
-M4.rootDir = java.lang.System.getenv("CGTOOLS");
-
-var CurrentPlatform = java.lang.System.getenv("BOARD");
-
-/*
-Memory map
-
-DDR: 0x80000000 (Ist 512MB - Cached)
-
-NOTE: APP_CACHED_DATA_BLK1_MEM is used to route sections which needs to be in a
-separate section preferably at the end of 512 MB memory.
-For example:
-Frame buffer memory can be less at runtime depending on boards with lesser DDR (as in TDA 12x12 POP boards).
-If the same is routed to APP_CACHED_DATA_MEM section then the linker will
-place the frame buffer before other data section and the other data will fall into
-region outside the DDR in the board. Hence separate section is used!!
-
-+-----------------------------+
-| APP_CODE_MEM | 3MB
-+-----------------------------+
-| APP_CACHED_DATA_MEM | 20MB
-+-----------------------------+
-| APP_CACHED_DATA_BLK1_MEM | 244MB
-+-----------------------------+
-| APP_CACHED_DATA_BLK2_MEM | 128MB
-+-----------------------------+
-| NOT USED | Remaining MB
-+-----------------------------+
-
-DDR: 0xA0000000 (2nd 512MB - Non-Cached)
-+-----------------------------+
-| |
-| APP_UNCACHED_DATA_BLK3_MEM | 2MB
-+-----------------------------+
-| NOT USED | Remaining MB
-+-----------------------------+
-
-*/
-
-var KB=1024;
-var MB=KB*KB;
-
-var DDR3_ADDR_0;
-var DDR3_ADDR_1;
-
-var APP_CODE_ADDR;
-var APP_CODE_SIZE;
-
-var APP_CACHED_DATA_ADDR;
-var APP_CACHED_DATA_SIZE;
-
-var APP_UNCACHED_DATA_BLK3_ADDR;
-var APP_UNCACHED_DATA_BLK3_SIZE;
-
-var APP_CACHED_DATA_BLK1_ADDR;
-var APP_CACHED_DATA_BLK1_SIZE;
-
-var APP_CACHED_DATA_BLK2_ADDR;
-var APP_CACHED_DATA_BLK2_SIZE;
-
-/* First 4KB reserved for components such as SBL */
-SBL_SIZE = 4*KB;
-DDR3_ADDR_0 = 0x80000000 + SBL_SIZE;
-DDR3_ADDR_1 = 0xA0000000;
-
-APP_CODE_SIZE = 3*MB - SBL_SIZE;
-APP_CACHED_DATA_SIZE = 20*MB;
-APP_CACHED_DATA_BLK1_SIZE = 244*MB;
-APP_CACHED_DATA_BLK2_SIZE = 128*MB;
-APP_UNCACHED_DATA_BLK3_SIZE = 2*MB;
-
-APP_CODE_ADDR = DDR3_ADDR_0;
-APP_CACHED_DATA_ADDR = APP_CODE_ADDR + APP_CODE_SIZE;
-APP_CACHED_DATA_BLK1_ADDR = APP_CACHED_DATA_ADDR + APP_CACHED_DATA_SIZE;
-APP_CACHED_DATA_BLK2_ADDR = APP_CACHED_DATA_BLK1_ADDR + APP_CACHED_DATA_BLK1_SIZE;
-APP_UNCACHED_DATA_BLK3_ADDR = DDR3_ADDR_1;
-
-myplatform = "ti.platforms.idkAM571X";
-
-Build.platformTable[myplatform] =
-{
- externalMemoryMap:
- [
- ["APP_CODE_MEM", {
- comment : "APP_CODE_MEM",
- name : "APP_CODE_MEM",
- base : APP_CODE_ADDR,
- len : APP_CODE_SIZE
- }],
- ["APP_CACHED_DATA_MEM", {
- comment : "APP_CACHED_DATA_MEM",
- name : "APP_CACHED_DATA_MEM",
- base : APP_CACHED_DATA_ADDR,
- len : APP_CACHED_DATA_SIZE
- }],
- ["APP_UNCACHED_DATA_BLK3_MEM", {
- comment : "APP_UNCACHED_DATA_BLK3_MEM",
- name : "APP_UNCACHED_DATA_BLK3_MEM",
- base : APP_UNCACHED_DATA_BLK3_ADDR,
- len : APP_UNCACHED_DATA_BLK3_SIZE
- }],
- ["APP_CACHED_DATA_BLK1_MEM", {
- comment : "APP_CACHED_DATA_BLK1_MEM",
- name : "APP_CACHED_DATA_BLK1_MEM",
- base : APP_CACHED_DATA_BLK1_ADDR,
- len : APP_CACHED_DATA_BLK1_SIZE
- }],
- ["APP_CACHED_DATA_BLK2_MEM", {
- comment : "APP_CACHED_DATA_BLK2_MEM",
- name : "APP_CACHED_DATA_BLK2_MEM",
- base : APP_CACHED_DATA_BLK2_ADDR,
- len : APP_CACHED_DATA_BLK2_SIZE
- }],
- ],
- codeMemory: "APP_CODE_MEM",
- dataMemory: "APP_CACHED_DATA_MEM",
- stackMemory: "APP_CACHED_DATA_MEM"
-};
diff --git a/packages/ti/build/am571x/config_am571x_a15.bld b/packages/ti/build/am571x/config_am571x_a15.bld
+++ /dev/null
@@ -1,169 +0,0 @@
-/*
-* Copyright (c) 2016, Texas Instruments Incorporated
-* All rights reserved.
-*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions
-* are met:
-*
-* * Redistributions of source code must retain the above copyright
-* notice, this list of conditions and the following disclaimer.
-*
-* * Redistributions in binary form must reproduce the above copyright
-* notice, this list of conditions and the following disclaimer in the
-* documentation and/or other materials provided with the distribution.
-*
-* * Neither the name of Texas Instruments Incorporated nor the names of
-* its contributors may be used to endorse or promote products derived
-* from this software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
-* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
-* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
-* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
-
-/*
- * ======== config_am572x_a15.bld ========
- * Build configuration script for BSP drivers
- */
-/* load the required modules for the configuration */
-var A15 = xdc.useModule('gnu.targets.arm.A15F');
-/* A15 compiler directory path */
-A15.rootDir = java.lang.System.getenv("CGTOOLS_A15");
-
-/* Read the current board */
-var CurrentPlatform = java.lang.System.getenv("BOARD");
-
-if (CurrentPlatform == null)
-{
- /* The env variable is probably not set while running inside CCS */
- CurrentPlatform = java.lang.System.getProperty("BOARD");
-}
-
-/*add bspLib to support SemiHosting to enable system_printf on A15*/
-/* GCC bare metal targets */
-var gccArmTargets = xdc.loadPackage('gnu.targets.arm');
-gccArmTargets.A15F.bspLib = "rdimon";
-
-/*
-Memory map
-
-DDR: 0x80000000 (Ist 512MB - Cached)
-
-NOTE: APP_CACHED_DATA_BLK1_MEM is used to route sections which needs to be in a
-separate section preferably at the end of 512 MB memory.
-For example:
-Frame buffer memory can be less at runtime depending on boards with lesser DDR (as in TDA 12x12 POP boards).
-If the same is routed to APP_CACHED_DATA_MEM section then the linker will
-place the frame buffer before other data section and the other data will fall into
-region outside the DDR in the board. Hence separate section is used!!
-
-+-----------------------------+
-| APP_CODE_MEM | 3MB
-+-----------------------------+
-| APP_CACHED_DATA_MEM | 20MB
-+-----------------------------+
-| APP_CACHED_DATA_BLK1_MEM | 244MB
-+-----------------------------+
-| APP_CACHED_DATA_BLK2_MEM | 128MB
-+-----------------------------+
-| NOT USED | Remaining MB
-+-----------------------------+
-
-DDR: 0xA0000000 (2nd 512MB - Non-Cached)
-+-----------------------------+
-| |
-| APP_UNCACHED_DATA_BLK3_MEM | 2MB
-+-----------------------------+
-| NOT USED | Remaining MB
-+-----------------------------+
-
-*/
-
-var KB=1024;
-var MB=KB*KB;
-
-var DDR3_ADDR_0;
-var DDR3_ADDR_1;
-
-var APP_CODE_ADDR;
-var APP_CODE_SIZE;
-
-var APP_CACHED_DATA_ADDR;
-var APP_CACHED_DATA_SIZE;
-
-var APP_UNCACHED_DATA_BLK3_ADDR;
-var APP_UNCACHED_DATA_BLK3_SIZE;
-
-var APP_CACHED_DATA_BLK1_ADDR;
-var APP_CACHED_DATA_BLK1_SIZE;
-
-var APP_CACHED_DATA_BLK2_ADDR;
-var APP_CACHED_DATA_BLK2_SIZE;
-
-/* First 4KB reserved for components such as SBL */
-SBL_SIZE = 4*KB;
-DDR3_ADDR_0 = 0x80000000 + SBL_SIZE;
-DDR3_ADDR_1 = 0xA0000000;
-
-APP_CODE_SIZE = 3*MB - SBL_SIZE;
-APP_CACHED_DATA_SIZE = 20*MB;
-APP_CACHED_DATA_BLK1_SIZE = 244*MB;
-APP_CACHED_DATA_BLK2_SIZE = 128*MB;
-APP_UNCACHED_DATA_BLK3_SIZE = 2*MB;
-
-APP_CODE_ADDR = DDR3_ADDR_0;
-APP_CACHED_DATA_ADDR = APP_CODE_ADDR + APP_CODE_SIZE;
-APP_CACHED_DATA_BLK1_ADDR = APP_CACHED_DATA_ADDR + APP_CACHED_DATA_SIZE;
-APP_CACHED_DATA_BLK2_ADDR = APP_CACHED_DATA_BLK1_ADDR + APP_CACHED_DATA_BLK1_SIZE;
-APP_UNCACHED_DATA_BLK3_ADDR = DDR3_ADDR_1;
-
-myplatform = "ti.platforms.idkAM571X";
-
-Build.platformTable[myplatform] =
-{
- externalMemoryMap:
- [
- ["APP_CODE_MEM", {
- comment : "APP_CODE_MEM",
- name : "APP_CODE_MEM",
- base : APP_CODE_ADDR,
- len : APP_CODE_SIZE
- }],
- ["APP_CACHED_DATA_MEM", {
- comment : "APP_CACHED_DATA_MEM",
- name : "APP_CACHED_DATA_MEM",
- base : APP_CACHED_DATA_ADDR,
- len : APP_CACHED_DATA_SIZE
- }],
- ["APP_UNCACHED_DATA_BLK3_MEM", {
- comment : "APP_UNCACHED_DATA_BLK3_MEM",
- name : "APP_UNCACHED_DATA_BLK3_MEM",
- base : APP_UNCACHED_DATA_BLK3_ADDR,
- len : APP_UNCACHED_DATA_BLK3_SIZE
- }],
- ["APP_CACHED_DATA_BLK1_MEM", {
- comment : "APP_CACHED_DATA_BLK1_MEM",
- name : "APP_CACHED_DATA_BLK1_MEM",
- base : APP_CACHED_DATA_BLK1_ADDR,
- len : APP_CACHED_DATA_BLK1_SIZE
- }],
- ["APP_CACHED_DATA_BLK2_MEM", {
- comment : "APP_CACHED_DATA_BLK2_MEM",
- name : "APP_CACHED_DATA_BLK2_MEM",
- base : APP_CACHED_DATA_BLK2_ADDR,
- len : APP_CACHED_DATA_BLK2_SIZE
- }],
- ],
- codeMemory: "APP_CODE_MEM",
- dataMemory: "APP_CACHED_DATA_MEM",
- stackMemory: "APP_CACHED_DATA_MEM"
-};
diff --git a/packages/ti/build/am571x/config_am571x_c66.bld b/packages/ti/build/am571x/config_am571x_c66.bld
+++ /dev/null
@@ -1,160 +0,0 @@
-/*
-* Copyright (c) 2016, Texas Instruments Incorporated
-* All rights reserved.
-*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions
-* are met:
-*
-* * Redistributions of source code must retain the above copyright
-* notice, this list of conditions and the following disclaimer.
-*
-* * Redistributions in binary form must reproduce the above copyright
-* notice, this list of conditions and the following disclaimer in the
-* documentation and/or other materials provided with the distribution.
-*
-* * Neither the name of Texas Instruments Incorporated nor the names of
-* its contributors may be used to endorse or promote products derived
-* from this software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
-* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
-* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
-* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
-/*
- * ======== config.bld ========
- * Sample Build configuration script
- */
-
-/* load the required modules for the configuration */
-var C66 = xdc.useModule('ti.targets.elf.C66');
-/* C66 compiler directory path */
-C66.rootDir = java.lang.System.getenv("CGTOOLS_DSP");
-
-/* compiler options */
-C66.ccOpts.suffix += " -mi10 -mo ";
-
-var CurrentPlatform = java.lang.System.getenv("BOARD");
-
-/*
-Memory map
-
-DDR: 0x80000000 (Ist 512MB - Cached)
-
-NOTE: APP_CACHED_DATA_BLK1_MEM is used to route sections which needs to be in a
-separate section preferably at the end of 512 MB memory.
-For example:
-Frame buffer memory can be less at runtime depending on boards with lesser DDR (as in TDA 12x12 POP boards).
-If the same is routed to APP_CACHED_DATA_MEM section then the linker will
-place the frame buffer before other data section and the other data will fall into
-region outside the DDR in the board. Hence separate section is used!!
-
-+-----------------------------+
-| APP_CODE_MEM | 3MB
-+-----------------------------+
-| APP_CACHED_DATA_MEM | 20MB
-+-----------------------------+
-| APP_CACHED_DATA_BLK1_MEM | 244MB
-+-----------------------------+
-| APP_CACHED_DATA_BLK2_MEM | 128MB
-+-----------------------------+
-| NOT USED | Remaining MB
-+-----------------------------+
-
-DDR: 0xA0000000 (2nd 512MB - Non-Cached)
-+-----------------------------+
-| |
-| APP_UNCACHED_DATA_BLK3_MEM | 2MB
-+-----------------------------+
-| NOT USED | Remaining MB
-+-----------------------------+
-
-*/
-
-var KB=1024;
-var MB=KB*KB;
-
-var DDR3_ADDR_0;
-var DDR3_ADDR_1;
-
-var APP_CODE_ADDR;
-var APP_CODE_SIZE;
-
-var APP_CACHED_DATA_ADDR;
-var APP_CACHED_DATA_SIZE;
-
-var APP_UNCACHED_DATA_BLK3_ADDR;
-var APP_UNCACHED_DATA_BLK3_SIZE;
-
-var APP_CACHED_DATA_BLK1_ADDR;
-var APP_CACHED_DATA_BLK1_SIZE;
-
-var APP_CACHED_DATA_BLK2_ADDR;
-var APP_CACHED_DATA_BLK2_SIZE;
-
-/* First 4KB reserved for components such as SBL */
-SBL_SIZE = 4*KB;
-DDR3_ADDR_0 = 0x80000000 + SBL_SIZE;
-DDR3_ADDR_1 = 0xA0000000;
-
-APP_CODE_SIZE = 3*MB - SBL_SIZE;
-APP_CACHED_DATA_SIZE = 20*MB;
-APP_CACHED_DATA_BLK1_SIZE = 244*MB;
-APP_CACHED_DATA_BLK2_SIZE = 128*MB;
-APP_UNCACHED_DATA_BLK3_SIZE = 2*MB;
-
-APP_CODE_ADDR = DDR3_ADDR_0;
-APP_CACHED_DATA_ADDR = APP_CODE_ADDR + APP_CODE_SIZE;
-APP_CACHED_DATA_BLK1_ADDR = APP_CACHED_DATA_ADDR + APP_CACHED_DATA_SIZE;
-APP_CACHED_DATA_BLK2_ADDR = APP_CACHED_DATA_BLK1_ADDR + APP_CACHED_DATA_BLK1_SIZE;
-APP_UNCACHED_DATA_BLK3_ADDR = DDR3_ADDR_1;
-
-myplatform = "ti.platforms.idkAM571X";
-
-Build.platformTable[myplatform] =
-{
- externalMemoryMap:
- [
- ["APP_CODE_MEM", {
- comment : "APP_CODE_MEM",
- name : "APP_CODE_MEM",
- base : APP_CODE_ADDR,
- len : APP_CODE_SIZE
- }],
- ["APP_CACHED_DATA_MEM", {
- comment : "APP_CACHED_DATA_MEM",
- name : "APP_CACHED_DATA_MEM",
- base : APP_CACHED_DATA_ADDR,
- len : APP_CACHED_DATA_SIZE
- }],
- ["APP_UNCACHED_DATA_BLK3_MEM", {
- comment : "APP_UNCACHED_DATA_BLK3_MEM",
- name : "APP_UNCACHED_DATA_BLK3_MEM",
- base : APP_UNCACHED_DATA_BLK3_ADDR,
- len : APP_UNCACHED_DATA_BLK3_SIZE
- }],
- ["APP_CACHED_DATA_BLK1_MEM", {
- comment : "APP_CACHED_DATA_BLK1_MEM",
- name : "APP_CACHED_DATA_BLK1_MEM",
- base : APP_CACHED_DATA_BLK1_ADDR,
- len : APP_CACHED_DATA_BLK1_SIZE
- }],
- ["APP_CACHED_DATA_BLK2_MEM", {
- comment : "APP_CACHED_DATA_BLK2_MEM",
- name : "APP_CACHED_DATA_BLK2_MEM",
- base : APP_CACHED_DATA_BLK2_ADDR,
- len : APP_CACHED_DATA_BLK2_SIZE
- }],
- ],
- codeMemory: "APP_CODE_MEM",
- dataMemory: "APP_CACHED_DATA_MEM",
- stackMemory: "APP_CACHED_DATA_MEM"
-};
diff --git a/packages/ti/build/am571x/mem_segment_definition_1024mb_bios.xs b/packages/ti/build/am571x/mem_segment_definition_1024mb_bios.xs
+++ /dev/null
@@ -1,261 +0,0 @@
-/*
-* Copyright (c) 2016, Texas Instruments Incorporated
-* All rights reserved.
-*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions
-* are met:
-*
-* * Redistributions of source code must retain the above copyright
-* notice, this list of conditions and the following disclaimer.
-*
-* * Redistributions in binary form must reproduce the above copyright
-* notice, this list of conditions and the following disclaimer in the
-* documentation and/or other materials provided with the distribution.
-*
-* * Neither the name of Texas Instruments Incorporated nor the names of
-* its contributors may be used to endorse or promote products derived
-* from this software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
-* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
-* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
-* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
-
-/*
- * ======== mem_segment_definition.xs ========
- * ======== Single file for the memory map configuration of all cores =========
- */
-
-KB=1024;
-MB=KB*KB;
-
-DDR3_ADDR = 0x80000000;
-DDR3_SIZE = 1024*MB;
-
-DDR3_BASE_ADDR_0 = 0x80000000;
-DDR3_BASE_SIZE_0 = 512*MB;
-
-/* The start address of the second mem section should be 16MB aligned.
- * for REMOTE_LOG_MEM sections.
- * tlb_config_eveX.c need to be modified otherwise
- */
-DDR3_BASE_ADDR_1 = 0xA0000000;
-DDR3_BASE_SIZE_1 = 512*MB;
-
-OCMC1_ADDR = 0x40300000;
-OCMC1_SIZE = 512*KB;
-
-DSP1_L2_SRAM_ADDR = 0x40800000;
-DSP1_L2_SRAM_SIZE = 288*KB;
-
-TOTAL_MEM_SIZE = (DDR3_SIZE);
-
-/* First 512 MB - cached */
-/* EVE vecs space should be align with 16MB boundary, and if possible try to fit
- * the entire vecs+code+data in 16MB section.
- * tlb_config_eveX.c need to be modified if any of these EVE memory sections or
- * SR1_FRAME_BUFFER_MEM section is modified.
- */
-IPU1_1_CODE_SIZE = 2*MB;
-IPU1_1_BSS_SIZE = 6*MB;
-IPU1_1_DATA_SIZE = 4*MB;
-IPU1_0_CODE_SIZE = 6*MB;
-IPU1_0_BSS_SIZE = 10*MB;
-IPU1_0_DATA_SIZE = 4*MB;
-SR1_FRAME_BUFFER_SIZE = 256*MB;
-DSP1_CODE_SIZE = 2*MB;
-DSP1_DATA_SIZE = 64*MB;
-/* A15_0_CODE_SIZE reduced since it is not used in .bld file.
- * Check .bld for details. Originally 2 + 14 MB.
- */
-A15_0_NDK_DATA_SIZE = 4*MB;
-A15_0_DATA_SIZE = 16*MB - A15_0_NDK_DATA_SIZE;
-
-
-
-/* Second 512 MB - non-cached */
-/* The start address of the second mem section should be 16MB aligned.
- * This alignment is a must as a single 16MB mapping is used for EMOTE_LOG_MEM sections.
- * tlb_config_eveX.c need to be modified otherwise
- */
-REMOTE_LOG_SIZE = 160*KB;
-SYSTEM_IPC_SHM_SIZE = 224*KB;
-LINK_STATS_SIZE = 256*KB;
-HDVPSS_DESC_SIZE = 1024*KB;
-SR0_SIZE = 128*KB;
-
-
-/* Cached Section */
-/* EVE vecs space should be align with 16MB boundary, and if possible try to fit
- * the entire vecs+code+data in 16MB section.
- * SR1_FRAME_BUFFER_MEM section is modified.
- */
-IPU1_1_CODE_ADDR = DDR3_BASE_ADDR_0;
-IPU1_1_DATA_ADDR = IPU1_1_CODE_ADDR + IPU1_1_CODE_SIZE;
-IPU1_1_BSS_ADDR = IPU1_1_DATA_ADDR + IPU1_1_DATA_SIZE;
-IPU1_0_CODE_ADDR = IPU1_1_BSS_ADDR + IPU1_1_BSS_SIZE;
-IPU1_0_DATA_ADDR = IPU1_0_CODE_ADDR + IPU1_0_CODE_SIZE;
-IPU1_0_BSS_ADDR = IPU1_0_DATA_ADDR + IPU1_0_DATA_SIZE;
-SR1_FRAME_BUFFER_ADDR = IPU1_0_BSS_ADDR + IPU1_0_BSS_SIZE;
-DSP1_CODE_ADDR = SR1_FRAME_BUFFER_ADDR + SR1_FRAME_BUFFER_SIZE;
-DSP1_DATA_ADDR = DSP1_CODE_ADDR + DSP1_CODE_SIZE;
-A15_0_NDK_DATA_ADDR = DSP1_DATA_ADDR + DSP1_DATA_SIZE;
-A15_0_DATA_ADDR = A15_0_NDK_DATA_ADDR + A15_0_NDK_DATA_SIZE;
-
-
-/* Non Cached Section */
-/* The start address of the second mem section should be 16MB aligned.
- * This alignment is a must as a single 16MB mapping is used for EMOTE_LOG_MEM sections.
- * tlb_config_eveX.c need to be modified otherwise
- */
-SR0_ADDR = DDR3_BASE_ADDR_1;
-REMOTE_LOG_ADDR = SR0_ADDR + SR0_SIZE;
-LINK_STATS_ADDR = REMOTE_LOG_ADDR + REMOTE_LOG_SIZE;
-SYSTEM_IPC_SHM_ADDR = LINK_STATS_ADDR + LINK_STATS_SIZE;
-HDVPSS_DESC_ADDR = SYSTEM_IPC_SHM_ADDR + SYSTEM_IPC_SHM_SIZE;
-
-if ((A15_0_DATA_ADDR + A15_0_DATA_SIZE) > (DDR3_BASE_ADDR_0 + DDR3_BASE_SIZE_0))
-{
- throw xdc.$$XDCException("MEMORY_MAP OVERFLOW ERROR ",
- "\nRegion End: " + "0x" + java.lang.Long.toHexString(DDR3_BASE_ADDR_0 + DDR3_BASE_SIZE_0) +
- "\nActual End: " + "0x" + java.lang.Long.toHexString(A15_0_DATA_ADDR + A15_0_DATA_SIZE));
-}
-
-if ((HDVPSS_DESC_ADDR + HDVPSS_DESC_SIZE) > (DDR3_BASE_ADDR_1 + DDR3_BASE_SIZE_1))
-{
- throw xdc.$$XDCException("MEMORY_MAP OVERFLOW ERROR ",
- "\nRegion End: " + "0x" + java.lang.Long.toHexString(DDR3_BASE_ADDR_1 + DDR3_BASE_SIZE_1) +
- "\nActual End: " + "0x" + java.lang.Long.toHexString(HDVPSS_DESC_ADDR + HDVPSS_DESC_SIZE));
-}
-
-if ((DDR3_BASE_SIZE_1 + DDR3_BASE_SIZE_0) > (TOTAL_MEM_SIZE))
-{
- throw xdc.$$XDCException("MEMORY_MAP EXCEEDS DDR SIZE ERROR ",
- "\nRegion End: " + "0x" + java.lang.Long.toHexString(DDR3_BASE_SIZE_1 + DDR3_BASE_SIZE_0) +
- "\nActual End: " + "0x" + java.lang.Long.toHexString(TOTAL_MEM_SIZE));
-}
-
-
-function getMemSegmentDefinition_external(core)
-{
- var memory = new Array();
- var index = 0;
-
- memory[index++] = ["IPU1_1_CODE_MEM", {
- comment : "IPU1_1_CODE_MEM",
- name : "IPU1_1_CODE_MEM",
- base : IPU1_1_CODE_ADDR,
- len : IPU1_1_CODE_SIZE
- }];
- memory[index++] = ["IPU1_1_DATA_MEM", {
- comment : "IPU1_1_DATA_MEM",
- name : "IPU1_1_DATA_MEM",
- base : IPU1_1_DATA_ADDR,
- len : IPU1_1_DATA_SIZE
- }];
- memory[index++] = ["IPU1_1_BSS_MEM", {
- comment : "IPU1_1_BSS_MEM",
- name : "IPU1_1_BSS_MEM",
- base : IPU1_1_BSS_ADDR,
- len : IPU1_1_BSS_SIZE
- }];
- memory[index++] = ["IPU1_0_CODE_MEM", {
- comment : "IPU1_0_CODE_MEM",
- name : "IPU1_0_CODE_MEM",
- base : IPU1_0_CODE_ADDR,
- len : IPU1_0_CODE_SIZE
- }];
- memory[index++] = ["IPU1_0_DATA_MEM", {
- comment : "IPU1_0_DATA_MEM",
- name : "IPU1_0_DATA_MEM",
- base : IPU1_0_DATA_ADDR,
- len : IPU1_0_DATA_SIZE
- }];
- memory[index++] = ["IPU1_0_BSS_MEM", {
- comment : "IPU1_0_BSS_MEM",
- name : "IPU1_0_BSS_MEM",
- base : IPU1_0_BSS_ADDR,
- len : IPU1_0_BSS_SIZE
- }];
- memory[index++] = ["DSP1_CODE_MEM", {
- comment : "DSP1_CODE_MEM",
- name : "DSP1_CODE_MEM",
- base : DSP1_CODE_ADDR,
- len : DSP1_CODE_SIZE
- }];
- memory[index++] = ["DSP1_DATA_MEM", {
- comment : "DSP1_DATA_MEM",
- name : "DSP1_DATA_MEM",
- base : DSP1_DATA_ADDR,
- len : DSP1_DATA_SIZE
- }];
-
- memory[index++] = ["A15_0_NDK_MEM", {
- comment : "A15_0_NDK_MEM",
- name : "A15_0_NDK_MEM",
- base : A15_0_NDK_DATA_ADDR,
- len : A15_0_NDK_DATA_SIZE
- }];
- memory[index++] = ["A15_0_DATA_MEM", {
- comment : "A15_0_DATA_MEM",
- name : "A15_0_DATA_MEM",
- base : A15_0_DATA_ADDR,
- len : A15_0_DATA_SIZE
- }];
- memory[index++] = ["SR1_FRAME_BUFFER_MEM", {
- comment : "SR1_FRAME_BUFFER_MEM",
- name : "SR1_FRAME_BUFFER_MEM",
- base : SR1_FRAME_BUFFER_ADDR,
- len : SR1_FRAME_BUFFER_SIZE
- }];
- memory[index++] = ["SR0", {
- comment : "SR0",
- name : "SR0",
- base : SR0_ADDR,
- len : SR0_SIZE
- }];
- memory[index++] = ["HDVPSS_DESC_MEM", {
- comment : "HDVPSS_DESC_MEM",
- name : "HDVPSS_DESC_MEM",
- base : HDVPSS_DESC_ADDR,
- len : HDVPSS_DESC_SIZE
- }];
- memory[index++] = ["REMOTE_LOG_MEM", {
- comment : "REMOTE_LOG_MEM",
- name : "REMOTE_LOG_MEM",
- base : REMOTE_LOG_ADDR,
- len : REMOTE_LOG_SIZE
- }];
- memory[index++] = ["LINK_STATS_MEM", {
- comment : "LINK_STATS_MEM",
- name : "LINK_STATS_MEM",
- base : LINK_STATS_ADDR,
- len : LINK_STATS_SIZE
- }];
- memory[index++] = ["SYSTEM_IPC_SHM_MEM", {
- comment : "SYSTEM_IPC_SHM_MEM",
- name : "SYSTEM_IPC_SHM_MEM",
- base : SYSTEM_IPC_SHM_ADDR,
- len : SYSTEM_IPC_SHM_SIZE
- }];
-
- xdc.print("# !!! Core is [" + core + "] !!!" );
-
- memory[index++] = ["DSP1_L2_SRAM", {
- comment: "DSP1_L2_SRAM",
- name: "DSP1_L2_SRAM",
- base: DSP1_L2_SRAM_ADDR,
- len: DSP1_L2_SRAM_SIZE
- }];
-
- return (memory);
-}
diff --git a/packages/ti/build/am572x/config_am572x.bld b/packages/ti/build/am572x/config_am572x.bld
+++ /dev/null
@@ -1,182 +0,0 @@
-/*
-* Copyright (c) 2016, Texas Instruments Incorporated
-* All rights reserved.
-*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions
-* are met:
-*
-* * Redistributions of source code must retain the above copyright
-* notice, this list of conditions and the following disclaimer.
-*
-* * Redistributions in binary form must reproduce the above copyright
-* notice, this list of conditions and the following disclaimer in the
-* documentation and/or other materials provided with the distribution.
-*
-* * Neither the name of Texas Instruments Incorporated nor the names of
-* its contributors may be used to endorse or promote products derived
-* from this software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
-* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
-* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
-* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
-/*
- * ======== config.bld ========
- * Build configuration script for BSP drivers
- */
-
-/* load the required modules for the configuration */
-var M4 = xdc.useModule('ti.targets.arm.elf.M4');
-/* M4 compiler directory path */
-M4.rootDir = java.lang.System.getenv("CGTOOLS");
-
-var CurrentPlatform = java.lang.System.getenv("BOARD");
-
-/*
-Memory map
-
-DDR: 0x80000000 (Ist 512MB - Cached)
-
-NOTE: APP_CACHED_DATA_BLK1_MEM is used to route sections which needs to be in a
-separate section preferably at the end of 512 MB memory.
-For example:
-Frame buffer memory can be less at runtime depending on boards with lesser DDR (as in TDA 12x12 POP boards).
-If the same is routed to APP_CACHED_DATA_MEM section then the linker will
-place the frame buffer before other data section and the other data will fall into
-region outside the DDR in the board. Hence separate section is used!!
-
-NOTE: APP_CACHED_DATA_BLK0_MEM is only used for AM572 with REV1 PRU-ICSS.
- .. This section will be referenced in the REV1 linker CMD file needed
- .. by AM3xx and AM4xx. It is (counterintuitively) the final section
- .. so as to not disturb the preferred section ordering.
-
-+-----------------------------+
-| APP_CODE_MEM | 2MB
-+-----------------------------+
-| APP_CACHED_DATA_MEM | 20MB
-+-----------------------------+
-| APP_CACHED_DATA_BLK1_MEM | 244MB
-+-----------------------------+
-| APP_CACHED_DATA_BLK2_MEM | 128MB
-+-----------------------------+
-| APP_CACHED_DATA_BLK0_MEM | 1MB
-+-----------------------------+
-| NOT USED | Remaining MB
-+-----------------------------+
-
-DDR: 0xA0000000 (2nd 512MB - Non-Cached)
-+-----------------------------+
-| |
-| APP_UNCACHED_DATA_BLK3_MEM | 2MB
-+-----------------------------+
-| NOT USED | Remaining MB
-+-----------------------------+
-
-*/
-
-var KB=1024;
-var MB=KB*KB;
-
-var DDR3_ADDR_0;
-var DDR3_ADDR_1;
-
-var APP_CODE_ADDR;
-var APP_CODE_SIZE;
-
-var APP_CACHED_DATA_ADDR;
-var APP_CACHED_DATA_SIZE;
-
-var APP_UNCACHED_DATA_BLK3_ADDR;
-var APP_UNCACHED_DATA_BLK3_SIZE;
-
-var APP_CACHED_DATA_BLK0_ADDR;
-var APP_CACHED_DATA_BLK0_SIZE;
-
-var APP_CACHED_DATA_BLK1_ADDR;
-var APP_CACHED_DATA_BLK1_SIZE;
-
-var APP_CACHED_DATA_BLK2_ADDR;
-var APP_CACHED_DATA_BLK2_SIZE;
-
-/* First 4KB reserved for components such as SBL */
-SBL_SIZE = 4*KB;
-DDR3_ADDR_0 = 0x80000000 + SBL_SIZE;
-DDR3_ADDR_1 = 0xA0000000;
-
-APP_CODE_SIZE = 3*MB - SBL_SIZE;
-APP_CACHED_DATA_SIZE = 20*MB;
-APP_CACHED_DATA_BLK0_SIZE = 1*MB;
-APP_CACHED_DATA_BLK1_SIZE = 244*MB;
-APP_CACHED_DATA_BLK2_SIZE = 128*MB;
-APP_UNCACHED_DATA_BLK3_SIZE = 2*MB;
-
-APP_CODE_ADDR = DDR3_ADDR_0;
-APP_CACHED_DATA_ADDR = APP_CODE_ADDR + APP_CODE_SIZE;
-APP_CACHED_DATA_BLK1_ADDR = APP_CACHED_DATA_ADDR + APP_CACHED_DATA_SIZE;
-APP_CACHED_DATA_BLK2_ADDR = APP_CACHED_DATA_BLK1_ADDR + APP_CACHED_DATA_BLK1_SIZE;
-APP_CACHED_DATA_BLK0_ADDR = APP_CACHED_DATA_BLK2_ADDR + APP_CACHED_DATA_BLK2_SIZE;
-APP_UNCACHED_DATA_BLK3_ADDR = DDR3_ADDR_1;
-
-if (CurrentPlatform == "evmAM572x")
-{
- myplatform = "ti.platforms.evmAM572X";
-}
-else
-{
- myplatform = "ti.platforms.idkAM572X";
-}
-
-Build.platformTable[myplatform] =
-{
- externalMemoryMap:
- [
- ["APP_CODE_MEM", {
- comment : "APP_CODE_MEM",
- name : "APP_CODE_MEM",
- base : APP_CODE_ADDR,
- len : APP_CODE_SIZE
- }],
- ["APP_CACHED_DATA_BLK0_MEM", {
- comment : "APP_CACHED_DATA_BLK0_MEM",
- name : "APP_CACHED_DATA_BLK0_MEM",
- base : APP_CACHED_DATA_BLK0_ADDR,
- len : APP_CACHED_DATA_BLK0_SIZE
- }],
- ["APP_CACHED_DATA_MEM", {
- comment : "APP_CACHED_DATA_MEM",
- name : "APP_CACHED_DATA_MEM",
- base : APP_CACHED_DATA_ADDR,
- len : APP_CACHED_DATA_SIZE
- }],
- ["APP_UNCACHED_DATA_BLK3_MEM", {
- comment : "APP_UNCACHED_DATA_BLK3_MEM",
- name : "APP_UNCACHED_DATA_BLK3_MEM",
- base : APP_UNCACHED_DATA_BLK3_ADDR,
- len : APP_UNCACHED_DATA_BLK3_SIZE
- }],
- ["APP_CACHED_DATA_BLK1_MEM", {
- comment : "APP_CACHED_DATA_BLK1_MEM",
- name : "APP_CACHED_DATA_BLK1_MEM",
- base : APP_CACHED_DATA_BLK1_ADDR,
- len : APP_CACHED_DATA_BLK1_SIZE
- }],
- ["APP_CACHED_DATA_BLK2_MEM", {
- comment : "APP_CACHED_DATA_BLK2_MEM",
- name : "APP_CACHED_DATA_BLK2_MEM",
- base : APP_CACHED_DATA_BLK2_ADDR,
- len : APP_CACHED_DATA_BLK2_SIZE
- }],
- ],
- codeMemory: "APP_CODE_MEM",
- dataMemory: "APP_CACHED_DATA_MEM",
- stackMemory: "APP_CACHED_DATA_MEM"
-};
diff --git a/packages/ti/build/am572x/config_am572x_a15.bld b/packages/ti/build/am572x/config_am572x_a15.bld
+++ /dev/null
@@ -1,194 +0,0 @@
-/*
-* Copyright (c) 2016, Texas Instruments Incorporated
-* All rights reserved.
-*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions
-* are met:
-*
-* * Redistributions of source code must retain the above copyright
-* notice, this list of conditions and the following disclaimer.
-*
-* * Redistributions in binary form must reproduce the above copyright
-* notice, this list of conditions and the following disclaimer in the
-* documentation and/or other materials provided with the distribution.
-*
-* * Neither the name of Texas Instruments Incorporated nor the names of
-* its contributors may be used to endorse or promote products derived
-* from this software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
-* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
-* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
-* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
-
-/*
- * ======== config_am572x_a15.bld ========
- * Build configuration script for BSP drivers
- */
-/* load the required modules for the configuration */
-var A15 = xdc.useModule('gnu.targets.arm.A15F');
-/* A15 compiler directory path */
-A15.rootDir = java.lang.System.getenv("CGTOOLS_A15");
-
-/* Read the current board */
-var CurrentPlatform = java.lang.System.getenv("BOARD");
-
-if (CurrentPlatform == null)
-{
- /* The env variable is probably not set while running inside CCS */
- CurrentPlatform = java.lang.System.getProperty("BOARD");
-}
-
-/*add bspLib to support SemiHosting to enable system_printf on A15*/
-/* GCC bare metal targets */
-var gccArmTargets = xdc.loadPackage('gnu.targets.arm');
-gccArmTargets.A15F.bspLib = "rdimon";
-
-/*
-Memory map
-
-DDR: 0x80000000 (Ist 512MB - Cached)
-
-NOTE: APP_CACHED_DATA_BLK1_MEM is used to route sections which needs to be in a
-separate section preferably at the end of 512 MB memory.
-For example:
-Frame buffer memory can be less at runtime depending on boards with lesser DDR (as in TDA 12x12 POP boards).
-If the same is routed to APP_CACHED_DATA_MEM section then the linker will
-place the frame buffer before other data section and the other data will fall into
-region outside the DDR in the board. Hence separate section is used!!
-
-NOTE: APP_CACHED_DATA_BLK0_MEM is only used for AM572 with REV1 PRU-ICSS.
- .. This section will be referenced in the REV1 linker CMD file needed
- .. by AM3xx and AM4xx. It is (counterintuitively) the final section
- .. so as to not disturb the preferred section ordering.
-
-+-----------------------------+
-| APP_CODE_MEM | 3MB
-+-----------------------------+
-| APP_CACHED_DATA_MEM | 20MB
-+-----------------------------+
-| APP_CACHED_DATA_BLK1_MEM | 244MB
-+-----------------------------+
-| APP_CACHED_DATA_BLK2_MEM | 128MB
-+-----------------------------+
-| APP_CACHED_DATA_BLK0_MEM | 1MB
-+-----------------------------+
-| NOT USED | Remaining MB
-+-----------------------------+
-
-DDR: 0xA0000000 (2nd 512MB - Non-Cached)
-+-----------------------------+
-| |
-| APP_UNCACHED_DATA_BLK3_MEM | 2MB
-+-----------------------------+
-| NOT USED | Remaining MB
-+-----------------------------+
-
-*/
-
-var KB=1024;
-var MB=KB*KB;
-
-var DDR3_ADDR_0;
-var DDR3_ADDR_1;
-
-var APP_CODE_ADDR;
-var APP_CODE_SIZE;
-
-var APP_CACHED_DATA_ADDR;
-var APP_CACHED_DATA_SIZE;
-
-var APP_UNCACHED_DATA_BLK3_ADDR;
-var APP_UNCACHED_DATA_BLK3_SIZE;
-
-var APP_CACHED_DATA_BLK0_ADDR;
-var APP_CACHED_DATA_BLK0_SIZE;
-
-var APP_CACHED_DATA_BLK1_ADDR;
-var APP_CACHED_DATA_BLK1_SIZE;
-
-var APP_CACHED_DATA_BLK2_ADDR;
-var APP_CACHED_DATA_BLK2_SIZE;
-
-/* First 4KB reserved for components such as SBL */
-SBL_SIZE = 4*KB;
-DDR3_ADDR_0 = 0x80000000 + SBL_SIZE;
-DDR3_ADDR_1 = 0xA0000000;
-
-APP_CODE_SIZE = 3*MB - SBL_SIZE;
-APP_CACHED_DATA_SIZE = 20*MB;
-APP_CACHED_DATA_BLK0_SIZE = 1*MB;
-APP_CACHED_DATA_BLK1_SIZE = 244*MB;
-APP_CACHED_DATA_BLK2_SIZE = 128*MB;
-APP_UNCACHED_DATA_BLK3_SIZE = 2*MB;
-
-APP_CODE_ADDR = DDR3_ADDR_0;
-APP_CACHED_DATA_ADDR = APP_CODE_ADDR + APP_CODE_SIZE;
-APP_CACHED_DATA_BLK1_ADDR = APP_CACHED_DATA_ADDR + APP_CACHED_DATA_SIZE;
-APP_CACHED_DATA_BLK2_ADDR = APP_CACHED_DATA_BLK1_ADDR + APP_CACHED_DATA_BLK1_SIZE;
-APP_CACHED_DATA_BLK0_ADDR = APP_CACHED_DATA_BLK2_ADDR + APP_CACHED_DATA_BLK2_SIZE;
-APP_UNCACHED_DATA_BLK3_ADDR = DDR3_ADDR_1;
-
-if (CurrentPlatform == "evmAM572x")
-{
- myplatform = "ti.platforms.evmAM572X";
-}
-else
-{
- myplatform = "ti.platforms.idkAM572X";
-}
-
-Build.platformTable[myplatform] =
-{
- externalMemoryMap:
- [
- ["APP_CODE_MEM", {
- comment : "APP_CODE_MEM",
- name : "APP_CODE_MEM",
- base : APP_CODE_ADDR,
- len : APP_CODE_SIZE
- }],
- ["APP_CACHED_DATA_BLK0_MEM", {
- comment : "APP_CACHED_DATA_BLK0_MEM",
- name : "APP_CACHED_DATA_BLK0_MEM",
- base : APP_CACHED_DATA_BLK0_ADDR,
- len : APP_CACHED_DATA_BLK0_SIZE
- }],
- ["APP_CACHED_DATA_MEM", {
- comment : "APP_CACHED_DATA_MEM",
- name : "APP_CACHED_DATA_MEM",
- base : APP_CACHED_DATA_ADDR,
- len : APP_CACHED_DATA_SIZE
- }],
- ["APP_UNCACHED_DATA_BLK3_MEM", {
- comment : "APP_UNCACHED_DATA_BLK3_MEM",
- name : "APP_UNCACHED_DATA_BLK3_MEM",
- base : APP_UNCACHED_DATA_BLK3_ADDR,
- len : APP_UNCACHED_DATA_BLK3_SIZE
- }],
- ["APP_CACHED_DATA_BLK1_MEM", {
- comment : "APP_CACHED_DATA_BLK1_MEM",
- name : "APP_CACHED_DATA_BLK1_MEM",
- base : APP_CACHED_DATA_BLK1_ADDR,
- len : APP_CACHED_DATA_BLK1_SIZE
- }],
- ["APP_CACHED_DATA_BLK2_MEM", {
- comment : "APP_CACHED_DATA_BLK2_MEM",
- name : "APP_CACHED_DATA_BLK2_MEM",
- base : APP_CACHED_DATA_BLK2_ADDR,
- len : APP_CACHED_DATA_BLK2_SIZE
- }],
- ],
- codeMemory: "APP_CODE_MEM",
- dataMemory: "APP_CACHED_DATA_MEM",
- stackMemory: "APP_CACHED_DATA_MEM"
-};
diff --git a/packages/ti/build/am572x/config_am572x_c66.bld b/packages/ti/build/am572x/config_am572x_c66.bld
+++ /dev/null
@@ -1,167 +0,0 @@
-/*
-* Copyright (c) 2016, Texas Instruments Incorporated
-* All rights reserved.
-*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions
-* are met:
-*
-* * Redistributions of source code must retain the above copyright
-* notice, this list of conditions and the following disclaimer.
-*
-* * Redistributions in binary form must reproduce the above copyright
-* notice, this list of conditions and the following disclaimer in the
-* documentation and/or other materials provided with the distribution.
-*
-* * Neither the name of Texas Instruments Incorporated nor the names of
-* its contributors may be used to endorse or promote products derived
-* from this software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
-* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
-* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
-* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
-/*
- * ======== config.bld ========
- * Sample Build configuration script
- */
-
-/* load the required modules for the configuration */
-var C66 = xdc.useModule('ti.targets.elf.C66');
-/* C66 compiler directory path */
-C66.rootDir = java.lang.System.getenv("CGTOOLS_DSP");
-
-/* compiler options */
-C66.ccOpts.suffix += " -mi10 -mo ";
-
-var CurrentPlatform = java.lang.System.getenv("BOARD");
-
-/*
-Memory map
-
-DDR: 0x80000000 (Ist 512MB - Cached)
-
-NOTE: APP_CACHED_DATA_BLK1_MEM is used to route sections which needs to be in a
-separate section preferably at the end of 512 MB memory.
-For example:
-Frame buffer memory can be less at runtime depending on boards with lesser DDR (as in TDA 12x12 POP boards).
-If the same is routed to APP_CACHED_DATA_MEM section then the linker will
-place the frame buffer before other data section and the other data will fall into
-region outside the DDR in the board. Hence separate section is used!!
-
-+-----------------------------+
-| APP_CODE_MEM | 3MB
-+-----------------------------+
-| APP_CACHED_DATA_MEM | 20MB
-+-----------------------------+
-| APP_CACHED_DATA_BLK1_MEM | 244MB
-+-----------------------------+
-| APP_CACHED_DATA_BLK2_MEM | 128MB
-+-----------------------------+
-| NOT USED | Remaining MB
-+-----------------------------+
-
-DDR: 0xA0000000 (2nd 512MB - Non-Cached)
-+-----------------------------+
-| |
-| APP_UNCACHED_DATA_BLK3_MEM | 2MB
-+-----------------------------+
-| NOT USED | Remaining MB
-+-----------------------------+
-
-*/
-
-var KB=1024;
-var MB=KB*KB;
-
-var DDR3_ADDR_0;
-var DDR3_ADDR_1;
-
-var APP_CODE_ADDR;
-var APP_CODE_SIZE;
-
-var APP_CACHED_DATA_ADDR;
-var APP_CACHED_DATA_SIZE;
-
-var APP_UNCACHED_DATA_BLK3_ADDR;
-var APP_UNCACHED_DATA_BLK3_SIZE;
-
-var APP_CACHED_DATA_BLK1_ADDR;
-var APP_CACHED_DATA_BLK1_SIZE;
-
-var APP_CACHED_DATA_BLK2_ADDR;
-var APP_CACHED_DATA_BLK2_SIZE;
-
-/* First 4KB reserved for components such as SBL */
-SBL_SIZE = 4*KB;
-DDR3_ADDR_0 = 0x80000000 + SBL_SIZE;
-DDR3_ADDR_1 = 0xA0000000;
-
-APP_CODE_SIZE = 3*MB - SBL_SIZE;
-APP_CACHED_DATA_SIZE = 20*MB;
-APP_CACHED_DATA_BLK1_SIZE = 244*MB;
-APP_CACHED_DATA_BLK2_SIZE = 128*MB;
-APP_UNCACHED_DATA_BLK3_SIZE = 2*MB;
-
-APP_CODE_ADDR = DDR3_ADDR_0;
-APP_CACHED_DATA_ADDR = APP_CODE_ADDR + APP_CODE_SIZE;
-APP_CACHED_DATA_BLK1_ADDR = APP_CACHED_DATA_ADDR + APP_CACHED_DATA_SIZE;
-APP_CACHED_DATA_BLK2_ADDR = APP_CACHED_DATA_BLK1_ADDR + APP_CACHED_DATA_BLK1_SIZE;
-APP_UNCACHED_DATA_BLK3_ADDR = DDR3_ADDR_1;
-
-if (CurrentPlatform == "evmAM572x")
-{
- myplatform = "ti.platforms.evmAM572X";
-}
-else
-{
- myplatform = "ti.platforms.idkAM572X";
-}
-
-Build.platformTable[myplatform] =
-{
- externalMemoryMap:
- [
- ["APP_CODE_MEM", {
- comment : "APP_CODE_MEM",
- name : "APP_CODE_MEM",
- base : APP_CODE_ADDR,
- len : APP_CODE_SIZE
- }],
- ["APP_CACHED_DATA_MEM", {
- comment : "APP_CACHED_DATA_MEM",
- name : "APP_CACHED_DATA_MEM",
- base : APP_CACHED_DATA_ADDR,
- len : APP_CACHED_DATA_SIZE
- }],
- ["APP_UNCACHED_DATA_BLK3_MEM", {
- comment : "APP_UNCACHED_DATA_BLK3_MEM",
- name : "APP_UNCACHED_DATA_BLK3_MEM",
- base : APP_UNCACHED_DATA_BLK3_ADDR,
- len : APP_UNCACHED_DATA_BLK3_SIZE
- }],
- ["APP_CACHED_DATA_BLK1_MEM", {
- comment : "APP_CACHED_DATA_BLK1_MEM",
- name : "APP_CACHED_DATA_BLK1_MEM",
- base : APP_CACHED_DATA_BLK1_ADDR,
- len : APP_CACHED_DATA_BLK1_SIZE
- }],
- ["APP_CACHED_DATA_BLK2_MEM", {
- comment : "APP_CACHED_DATA_BLK2_MEM",
- name : "APP_CACHED_DATA_BLK2_MEM",
- base : APP_CACHED_DATA_BLK2_ADDR,
- len : APP_CACHED_DATA_BLK2_SIZE
- }],
- ],
- codeMemory: "APP_CODE_MEM",
- dataMemory: "APP_CACHED_DATA_MEM",
- stackMemory: "APP_CACHED_DATA_MEM"
-};
diff --git a/packages/ti/build/am572x/mem_segment_definition_1024mb_bios.xs b/packages/ti/build/am572x/mem_segment_definition_1024mb_bios.xs
+++ /dev/null
@@ -1,538 +0,0 @@
-/*
-* Copyright (c) 2016, Texas Instruments Incorporated
-* All rights reserved.
-*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions
-* are met:
-*
-* * Redistributions of source code must retain the above copyright
-* notice, this list of conditions and the following disclaimer.
-*
-* * Redistributions in binary form must reproduce the above copyright
-* notice, this list of conditions and the following disclaimer in the
-* documentation and/or other materials provided with the distribution.
-*
-* * Neither the name of Texas Instruments Incorporated nor the names of
-* its contributors may be used to endorse or promote products derived
-* from this software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
-* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
-* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
-* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
-
-/*
- * ======== mem_segment_definition.xs ========
- * ======== Single file for the memory map configuration of all cores =========
- */
-
-var KB=1024;
-var MB=KB*KB;
-
-var DDR3_ADDR;
-var DDR3_SIZE;
-
-var DDR3_BASE_ADDR_0;
-var DDR3_BASE_SIZE_0;
-var DDR3_BASE_ADDR_1;
-var DDR3_BASE_SIZE_1;
-
-var OCMC1_ADDR;
-var OCMC2_ADDR;
-var OCMC3_ADDR;
-
-var OCMC1_SIZE;
-var OCMC2_SIZE;
-var OCMC3_SIZE;
-
-var DSP1_L2_SRAM_ADDR;
-var DSP1_L2_SRAM_SIZE;
-
-var DSP2_L2_SRAM_ADDR;
-var DSP2_L2_SRAM_SIZE;
-
-var EVE1_SRAM_ADDR;
-var EVE1_SRAM_SIZE;
-
-var EVE2_SRAM_ADDR;
-var EVE2_SRAM_SIZE;
-
-var EVE3_SRAM_ADDR;
-var EVE3_SRAM_SIZE;
-
-var EVE4_SRAM_ADDR;
-var EVE4_SRAM_SIZE;
-
-var SR0_ADDR;
-var SR0_SIZE;
-
-var IPU1_1_CODE_ADDR;
-var IPU1_1_CODE_SIZE;
-
-var IPU1_1_DATA_ADDR;
-var IPU1_1_DATA_SIZE;
-
-var IPU1_1_BSS_ADDR;
-var IPU1_1_BSS_SIZE;
-
-var SR1_FRAME_BUFFER_ADDR;
-var SR1_FRAME_BUFFER_SIZE;
-
-var IPU1_0_CODE_ADDR;
-var IPU1_0_CODE_SIZE;
-
-var IPU1_0_DATA_ADDR;
-var IPU1_0_DATA_SIZE;
-
-var IPU1_0_BSS_ADDR;
-var IPU1_0_BSS_SIZE;
-
-var DSP1_CODE_ADDR;
-var DSP1_CODE_SIZE;
-
-var DSP1_DATA_ADDR;
-var DSP1_DATA_SIZE;
-
-var DSP2_CODE_ADDR;
-var DSP2_CODE_SIZE;
-
-var DSP2_DATA_ADDR;
-var DSP2_DATA_SIZE;
-
-var EVE1_CODE_ADDR;
-var EVE1_CODE_SIZE;
-
-var EVE1_DATA_ADDR;
-var EVE1_DATA_SIZE;
-
-var EVE1_VECS_ADDR;
-var EVE1_VECS_SIZE;
-
-var EVE2_CODE_ADDR;
-var EVE2_CODE_SIZE;
-
-var EVE2_DATA_ADDR;
-var EVE2_DATA_SIZE;
-
-var EVE2_VECS_ADDR;
-var EVE2_VECS_SIZE;
-
-var EVE3_CODE_ADDR;
-var EVE3_CODE_SIZE;
-
-var EVE3_DATA_ADDR;
-var EVE3_DATA_SIZE;
-
-var EVE3_VECS_ADDR;
-var EVE3_VECS_SIZE;
-
-var EVE4_CODE_ADDR;
-var EVE4_CODE_SIZE;
-
-var EVE4_DATA_ADDR;
-var EVE4_DATA_SIZE;
-
-var EVE4_VECS_ADDR;
-var EVE4_VECS_SIZE;
-
-var A15_0_CODE_ADDR;
-var A15_0_CODE_SIZE;
-
-var A15_0_DATA_ADDR;
-var A15_0_DATA_SIZE;
-
-var HDVPSS_DESC_ADDR;
-var HDVPSS_DESC_SIZE;
-
-var REMOTE_LOG_ADDR;
-var REMOTE_LOG_SIZE;
-
-DDR3_ADDR = 0x80000000;
-DDR3_SIZE = 1024*MB;
-
-DDR3_BASE_ADDR_0 = 0x80000000;
-DDR3_BASE_SIZE_0 = 512*MB;
-
-/* The start address of the second mem section should be 16MB aligned.
- * This alignment is a must as a single 16MB mapping is used for EVE
- * to map SR0, REMOTE_LOG_MEM sections.
- * tlb_config_eveX.c need to be modified otherwise
- */
-DDR3_BASE_ADDR_1 = 0xA0000000;
-DDR3_BASE_SIZE_1 = 512*MB;
-
-OCMC1_ADDR = 0x40300000;
-OCMC1_SIZE = 512*KB;
-
-OCMC2_ADDR = 0x40400000;
-OCMC2_SIZE = 1*MB;
-
-OCMC3_ADDR = 0x40500000;
-OCMC3_SIZE = 1*MB;
-
-DSP1_L2_SRAM_ADDR = 0x40800000;
-DSP1_L2_SRAM_SIZE = 288*KB;
-
-DSP2_L2_SRAM_ADDR = 0x41000000;
-DSP2_L2_SRAM_SIZE = 288*KB;
-
-EVE1_SRAM_ADDR = 0x42000000;
-EVE1_SRAM_SIZE = 1*MB;
-
-EVE2_SRAM_ADDR = 0x42100000;
-EVE2_SRAM_SIZE = 1*MB;
-
-EVE3_SRAM_ADDR = 0x42200000;
-EVE3_SRAM_SIZE = 1*MB;
-
-EVE4_SRAM_ADDR = 0x42300000;
-EVE4_SRAM_SIZE = 1*MB;
-
-var TOTAL_MEM_SIZE = (DDR3_SIZE);
-
-/* First 512 MB - cached */
-/* EVE vecs space should be align with 16MB boundary, and if possible try to fit
- * the entire vecs+code+data in 16MB section. In this case a single TLB map would
- * be enough to map vecs+code+data of an EVE.
- * tlb_config_eveX.c need to be modified if any of these EVE memory sections or
- * SR1_FRAME_BUFFER_MEM section is modified.
- */
-EVE1_VECS_SIZE = 0.5*MB;
-EVE1_CODE_SIZE = 2*MB;
-EVE1_DATA_SIZE =13.5*MB;
-EVE2_VECS_SIZE = 0.5*MB;
-EVE2_CODE_SIZE = 2*MB;
-EVE2_DATA_SIZE =13.5*MB;
-EVE3_VECS_SIZE = 0.5*MB;
-EVE3_CODE_SIZE = 2*MB;
-EVE3_DATA_SIZE =13.5*MB;
-EVE4_VECS_SIZE = 0.5*MB;
-EVE4_CODE_SIZE = 2*MB;
-EVE4_DATA_SIZE =13.5*MB;
-IPU1_1_CODE_SIZE = 2*MB;
-IPU1_1_BSS_SIZE = 8*MB;
-IPU1_1_DATA_SIZE = 4*MB;
-IPU1_0_CODE_SIZE = 6*MB;
-IPU1_0_BSS_SIZE = 8*MB;
-IPU1_0_DATA_SIZE = 4*MB;
-SR1_FRAME_BUFFER_SIZE = 256*MB;
-DSP1_CODE_SIZE = 2*MB;
-DSP1_DATA_SIZE = 64*MB;
-DSP2_CODE_SIZE = 2*MB;
-DSP2_DATA_SIZE = 64*MB;
-A15_0_CODE_SIZE = 2*MB;
-A15_0_DATA_SIZE = 14*MB;
-
-
-
-/* Second 512 MB - non-cached */
-/* The start address of the second mem section should be 16MB aligned.
- * This alignment is a must as a single 16MB mapping is used for EVE
- * to map SR0, EMOTE_LOG_MEM sections.
- * tlb_config_eveX.c need to be modified otherwise
- */
-SR0_SIZE = 13*MB;
-REMOTE_LOG_SIZE =1024*KB;
-HDVPSS_DESC_SIZE = 2*MB;
-
-
-/* Cached Section */
-/* EVE vecs space should be align with 16MB boundary, and if possible try to fit
- * the entire vecs+code+data in 16MB section. In this case a single TLB map would
- * be enough to map vecs+code+data of an EVE.
- * tlb_config_eveX.c need to be modified if any of these EVE memory sections or
- * SR1_FRAME_BUFFER_MEM section is modified.
- */
-EVE1_VECS_ADDR = DDR3_BASE_ADDR_0;
-EVE1_CODE_ADDR = EVE1_VECS_ADDR + EVE1_VECS_SIZE;
-EVE1_DATA_ADDR = EVE1_CODE_ADDR + EVE1_CODE_SIZE;
-EVE2_VECS_ADDR = EVE1_DATA_ADDR + EVE1_DATA_SIZE;
-EVE2_CODE_ADDR = EVE2_VECS_ADDR + EVE2_VECS_SIZE;
-EVE2_DATA_ADDR = EVE2_CODE_ADDR + EVE2_CODE_SIZE;
-EVE3_VECS_ADDR = EVE2_DATA_ADDR + EVE2_DATA_SIZE;
-EVE3_CODE_ADDR = EVE3_VECS_ADDR + EVE3_VECS_SIZE;
-EVE3_DATA_ADDR = EVE3_CODE_ADDR + EVE3_CODE_SIZE;
-EVE4_VECS_ADDR = EVE3_DATA_ADDR + EVE3_DATA_SIZE;
-EVE4_CODE_ADDR = EVE4_VECS_ADDR + EVE4_VECS_SIZE;
-EVE4_DATA_ADDR = EVE4_CODE_ADDR + EVE4_CODE_SIZE;
-IPU1_1_CODE_ADDR = EVE4_DATA_ADDR + EVE4_DATA_SIZE;
-IPU1_1_DATA_ADDR = IPU1_1_CODE_ADDR + IPU1_1_CODE_SIZE;
-IPU1_1_BSS_ADDR = IPU1_1_DATA_ADDR + IPU1_1_DATA_SIZE;
-IPU1_0_CODE_ADDR = IPU1_1_BSS_ADDR + IPU1_1_BSS_SIZE;
-IPU1_0_DATA_ADDR = IPU1_0_CODE_ADDR + IPU1_0_CODE_SIZE;
-IPU1_0_BSS_ADDR = IPU1_0_DATA_ADDR + IPU1_0_DATA_SIZE;
-SR1_FRAME_BUFFER_ADDR = IPU1_0_BSS_ADDR + IPU1_0_BSS_SIZE;
-DSP1_CODE_ADDR = SR1_FRAME_BUFFER_ADDR + SR1_FRAME_BUFFER_SIZE;
-DSP1_DATA_ADDR = DSP1_CODE_ADDR + DSP1_CODE_SIZE;
-DSP2_CODE_ADDR = DSP1_DATA_ADDR + DSP1_DATA_SIZE;
-DSP2_DATA_ADDR = DSP2_CODE_ADDR + DSP2_CODE_SIZE;
-A15_0_CODE_ADDR = DSP2_DATA_ADDR + DSP2_DATA_SIZE;
-A15_0_DATA_ADDR = A15_0_CODE_ADDR + A15_0_CODE_SIZE;
-
-
-/* Non Cached Section */
-/* The start address of the second mem section should be 16MB aligned.
- * This alignment is a must as a single 16MB mapping is used for EVE
- * to map SR0, EMOTE_LOG_MEM sections.
- * tlb_config_eveX.c need to be modified otherwise
- */
-SR0_ADDR = DDR3_BASE_ADDR_1;
-REMOTE_LOG_ADDR = SR0_ADDR + SR0_SIZE;
-HDVPSS_DESC_ADDR = REMOTE_LOG_ADDR + REMOTE_LOG_SIZE;
-
-if ((A15_0_DATA_ADDR + A15_0_DATA_SIZE) > (DDR3_BASE_ADDR_0 + DDR3_BASE_SIZE_0))
-{
- throw xdc.$$XDCException("MEMORY_MAP OVERFLOW ERROR ",
- "\nRegion End: " + "0x" + java.lang.Long.toHexString(DDR3_BASE_ADDR_0 + DDR3_BASE_SIZE_0) +
- "\nActual End: " + "0x" + java.lang.Long.toHexString(A15_0_DATA_ADDR + A15_0_DATA_SIZE));
-}
-
-if ((HDVPSS_DESC_ADDR + HDVPSS_DESC_SIZE) > (DDR3_BASE_ADDR_1 + DDR3_BASE_SIZE_1))
-{
- throw xdc.$$XDCException("MEMORY_MAP OVERFLOW ERROR ",
- "\nRegion End: " + "0x" + java.lang.Long.toHexString(DDR3_BASE_ADDR_1 + DDR3_BASE_SIZE_1) +
- "\nActual End: " + "0x" + java.lang.Long.toHexString(HDVPSS_DESC_ADDR + HDVPSS_DESC_SIZE));
-}
-
-if ((DDR3_BASE_SIZE_1 + DDR3_BASE_SIZE_0) > (TOTAL_MEM_SIZE))
-{
- throw xdc.$$XDCException("MEMORY_MAP EXCEEDS 256mb ERROR ",
- "\nRegion End: " + "0x" + java.lang.Long.toHexString(DDR3_BASE_SIZE_1 + DDR3_BASE_SIZE_0) +
- "\nActual End: " + "0x" + java.lang.Long.toHexString(TOTAL_MEM_SIZE));
-}
-
-
-function getMemSegmentDefinition_external(core)
-{
- var memory = new Array();
- var index = 0;
-
- memory[index++] = ["IPU1_1_CODE_MEM", {
- comment : "IPU1_1_CODE_MEM",
- name : "IPU1_1_CODE_MEM",
- base : IPU1_1_CODE_ADDR,
- len : IPU1_1_CODE_SIZE
- }];
- memory[index++] = ["IPU1_1_DATA_MEM", {
- comment : "IPU1_1_DATA_MEM",
- name : "IPU1_1_DATA_MEM",
- base : IPU1_1_DATA_ADDR,
- len : IPU1_1_DATA_SIZE
- }];
- memory[index++] = ["IPU1_1_BSS_MEM", {
- comment : "IPU1_1_BSS_MEM",
- name : "IPU1_1_BSS_MEM",
- base : IPU1_1_BSS_ADDR,
- len : IPU1_1_BSS_SIZE
- }];
- memory[index++] = ["IPU1_0_CODE_MEM", {
- comment : "IPU1_0_CODE_MEM",
- name : "IPU1_0_CODE_MEM",
- base : IPU1_0_CODE_ADDR,
- len : IPU1_0_CODE_SIZE
- }];
- memory[index++] = ["IPU1_0_DATA_MEM", {
- comment : "IPU1_0_DATA_MEM",
- name : "IPU1_0_DATA_MEM",
- base : IPU1_0_DATA_ADDR,
- len : IPU1_0_DATA_SIZE
- }];
- memory[index++] = ["IPU1_0_BSS_MEM", {
- comment : "IPU1_0_BSS_MEM",
- name : "IPU1_0_BSS_MEM",
- base : IPU1_0_BSS_ADDR,
- len : IPU1_0_BSS_SIZE
- }];
- memory[index++] = ["DSP1_CODE_MEM", {
- comment : "DSP1_CODE_MEM",
- name : "DSP1_CODE_MEM",
- base : DSP1_CODE_ADDR,
- len : DSP1_CODE_SIZE
- }];
- memory[index++] = ["DSP1_DATA_MEM", {
- comment : "DSP1_DATA_MEM",
- name : "DSP1_DATA_MEM",
- base : DSP1_DATA_ADDR,
- len : DSP1_DATA_SIZE
- }];
-
- memory[index++] = ["DSP2_CODE_MEM", {
- comment : "DSP2_CODE_MEM",
- name : "DSP2_CODE_MEM",
- base : DSP2_CODE_ADDR,
- len : DSP2_CODE_SIZE
- }];
- memory[index++] = ["DSP2_DATA_MEM", {
- comment : "DSP2_DATA_MEM",
- name : "DSP2_DATA_MEM",
- base : DSP2_DATA_ADDR,
- len : DSP2_DATA_SIZE
- }];
-
- memory[index++] = ["A15_0_CODE_MEM", {
- comment : "A15_0_CODE_MEM",
- name : "A15_0_CODE_MEM",
- base : A15_0_CODE_ADDR,
- len : A15_0_CODE_SIZE
- }];
- memory[index++] = ["A15_0_DATA_MEM", {
- comment : "A15_0_DATA_MEM",
- name : "A15_0_DATA_MEM",
- base : A15_0_DATA_ADDR,
- len : A15_0_DATA_SIZE
- }];
-
-
- memory[index++] = ["EVE1_VECS_MEM", {
- comment : "EVE1_VECS_MEM",
- name : "EVE1_VECS_MEM",
- base : EVE1_VECS_ADDR,
- len : EVE1_VECS_SIZE
- }];
- memory[index++] = ["EVE1_CODE_MEM", {
- comment : "EVE1_CODE_MEM",
- name : "EVE1_CODE_MEM",
- base : EVE1_CODE_ADDR,
- len : EVE1_CODE_SIZE
- }];
- memory[index++] = ["EVE1_DATA_MEM", {
- comment : "EVE1_DATA_MEM",
- name : "EVE1_DATA_MEM",
- base : EVE1_DATA_ADDR,
- len : EVE1_DATA_SIZE
- }];
- memory[index++] = ["EVE2_VECS_MEM", {
- comment : "EVE2_VECS_MEM",
- name : "EVE2_VECS_MEM",
- base : EVE2_VECS_ADDR,
- len : EVE2_VECS_SIZE
- }];
- memory[index++] = ["EVE2_CODE_MEM", {
- comment : "EVE2_CODE_MEM",
- name : "EVE2_CODE_MEM",
- base : EVE2_CODE_ADDR,
- len : EVE2_CODE_SIZE
- }];
- memory[index++] = ["EVE2_DATA_MEM", {
- comment : "EVE2_DATA_MEM",
- name : "EVE2_DATA_MEM",
- base : EVE2_DATA_ADDR,
- len : EVE2_DATA_SIZE
- }];
- memory[index++] = ["EVE3_VECS_MEM", {
- comment : "EVE3_VECS_MEM",
- name : "EVE3_VECS_MEM",
- base : EVE3_VECS_ADDR,
- len : EVE3_VECS_SIZE
- }];
- memory[index++] = ["EVE3_CODE_MEM", {
- comment : "EVE3_CODE_MEM",
- name : "EVE3_CODE_MEM",
- base : EVE3_CODE_ADDR,
- len : EVE3_CODE_SIZE
- }];
- memory[index++] = ["EVE3_DATA_MEM", {
- comment : "EVE3_DATA_MEM",
- name : "EVE3_DATA_MEM",
- base : EVE3_DATA_ADDR,
- len : EVE3_DATA_SIZE
- }];
- memory[index++] = ["EVE4_VECS_MEM", {
- comment : "EVE4_VECS_MEM",
- name : "EVE4_VECS_MEM",
- base : EVE4_VECS_ADDR,
- len : EVE4_VECS_SIZE
- }];
- memory[index++] = ["EVE4_CODE_MEM", {
- comment : "EVE4_CODE_MEM",
- name : "EVE4_CODE_MEM",
- base : EVE4_CODE_ADDR,
- len : EVE4_CODE_SIZE
- }];
- memory[index++] = ["EVE4_DATA_MEM", {
- comment : "EVE4_DATA_MEM",
- name : "EVE4_DATA_MEM",
- base : EVE4_DATA_ADDR,
- len : EVE4_DATA_SIZE
- }];
- memory[index++] = ["SR1_FRAME_BUFFER_MEM", {
- comment : "SR1_FRAME_BUFFER_MEM",
- name : "SR1_FRAME_BUFFER_MEM",
- base : SR1_FRAME_BUFFER_ADDR,
- len : SR1_FRAME_BUFFER_SIZE
- }];
- memory[index++] = ["SR0", {
- comment : "SR0",
- name : "SR0",
- base : SR0_ADDR,
- len : SR0_SIZE
- }];
- memory[index++] = ["HDVPSS_DESC_MEM", {
- comment : "HDVPSS_DESC_MEM",
- name : "HDVPSS_DESC_MEM",
- base : HDVPSS_DESC_ADDR,
- len : HDVPSS_DESC_SIZE
- }];
- memory[index++] = ["REMOTE_LOG_MEM", {
- comment : "REMOTE_LOG_MEM",
- name : "REMOTE_LOG_MEM",
- base : REMOTE_LOG_ADDR,
- len : REMOTE_LOG_SIZE
- }];
-
-/* Memory name OCMC_RAM1, 2 & 3 are defined internally in evmDRA7XX platform
- So no need to specify them explicitly for IPU1, A15
-*/
- xdc.print("# !!! Core is [" + core + "] !!!" );
-
- if( core == "c66xdsp_1" ||
- core == "c66xdsp_2" ||
- core == "arp32_1" ||
- core == "arp32_2" ||
- core == "arp32_3" ||
- core == "arp32_4"
- )
- {
- memory[index++] = ["OCMC_RAM1", {
- comment: "OCMC_RAM1",
- name: "OCMC_RAM1",
- base: OCMC1_ADDR,
- len: OCMC1_SIZE
- }];
- memory[index++] = ["OCMC_RAM2", {
- comment: "OCMC_RAM2",
- name: "OCMC_RAM2",
- base: OCMC2_ADDR,
- len: OCMC2_SIZE
- }];
- memory[index++] = ["OCMC_RAM3", {
- comment: "OCMC_RAM3",
- name: "OCMC_RAM3",
- base: OCMC3_ADDR,
- len: OCMC3_SIZE
- }];
- }
- memory[index++] = ["DSP1_L2_SRAM", {
- comment: "DSP1_L2_SRAM",
- name: "DSP1_L2_SRAM",
- base: DSP1_L2_SRAM_ADDR,
- len: DSP1_L2_SRAM_SIZE
- }];
- memory[index++] = ["DSP2_L2_SRAM", {
- comment: "DSP2_L2_SRAM",
- name: "DSP2_L2_SRAM",
- base: DSP2_L2_SRAM_ADDR,
- len: DSP2_L2_SRAM_SIZE
- }];
-
- return (memory);
-}
diff --git a/packages/ti/build/am574x/config_am574x.bld b/packages/ti/build/am574x/config_am574x.bld
+++ /dev/null
@@ -1,157 +0,0 @@
-/*
-* Copyright (c) 2017, Texas Instruments Incorporated
-* All rights reserved.
-*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions
-* are met:
-*
-* * Redistributions of source code must retain the above copyright
-* notice, this list of conditions and the following disclaimer.
-*
-* * Redistributions in binary form must reproduce the above copyright
-* notice, this list of conditions and the following disclaimer in the
-* documentation and/or other materials provided with the distribution.
-*
-* * Neither the name of Texas Instruments Incorporated nor the names of
-* its contributors may be used to endorse or promote products derived
-* from this software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
-* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
-* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
-* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
-/*
- * ======== config.bld ========
- * Build configuration script for BSP drivers
- */
-
-/* load the required modules for the configuration */
-var M4 = xdc.useModule('ti.targets.arm.elf.M4');
-/* M4 compiler directory path */
-M4.rootDir = java.lang.System.getenv("CGTOOLS");
-
-var CurrentPlatform = java.lang.System.getenv("BOARD");
-
-/*
-Memory map
-
-DDR: 0x80000000 (Ist 512MB - Cached)
-
-NOTE: APP_CACHED_DATA_BLK1_MEM is used to route sections which needs to be in a
-separate section preferably at the end of 512 MB memory.
-For example:
-Frame buffer memory can be less at runtime depending on boards with lesser DDR (as in TDA 12x12 POP boards).
-If the same is routed to APP_CACHED_DATA_MEM section then the linker will
-place the frame buffer before other data section and the other data will fall into
-region outside the DDR in the board. Hence separate section is used!!
-
-+-----------------------------+
-| APP_CODE_MEM | 3MB
-+-----------------------------+
-| APP_CACHED_DATA_MEM | 20MB
-+-----------------------------+
-| APP_CACHED_DATA_BLK1_MEM | 244MB
-+-----------------------------+
-| APP_CACHED_DATA_BLK2_MEM | 128MB
-+-----------------------------+
-| NOT USED | Remaining MB
-+-----------------------------+
-
-DDR: 0xA0000000 (2nd 512MB - Non-Cached)
-+-----------------------------+
-| |
-| APP_UNCACHED_DATA_BLK3_MEM | 2MB
-+-----------------------------+
-| NOT USED | Remaining MB
-+-----------------------------+
-
-*/
-
-var KB=1024;
-var MB=KB*KB;
-
-var DDR3_ADDR_0;
-var DDR3_ADDR_1;
-
-var APP_CODE_ADDR;
-var APP_CODE_SIZE;
-
-var APP_CACHED_DATA_ADDR;
-var APP_CACHED_DATA_SIZE;
-
-var APP_UNCACHED_DATA_BLK3_ADDR;
-var APP_UNCACHED_DATA_BLK3_SIZE;
-
-var APP_CACHED_DATA_BLK1_ADDR;
-var APP_CACHED_DATA_BLK1_SIZE;
-
-var APP_CACHED_DATA_BLK2_ADDR;
-var APP_CACHED_DATA_BLK2_SIZE;
-
-/* First 4KB reserved for components such as SBL */
-SBL_SIZE = 4*KB;
-DDR3_ADDR_0 = 0x80000000 + SBL_SIZE;
-DDR3_ADDR_1 = 0xA0000000;
-
-APP_CODE_SIZE = 3*MB - SBL_SIZE;
-APP_CACHED_DATA_SIZE = 20*MB;
-APP_CACHED_DATA_BLK1_SIZE = 244*MB;
-APP_CACHED_DATA_BLK2_SIZE = 128*MB;
-APP_UNCACHED_DATA_BLK3_SIZE = 2*MB;
-
-APP_CODE_ADDR = DDR3_ADDR_0;
-APP_CACHED_DATA_ADDR = APP_CODE_ADDR + APP_CODE_SIZE;
-APP_CACHED_DATA_BLK1_ADDR = APP_CACHED_DATA_ADDR + APP_CACHED_DATA_SIZE;
-APP_CACHED_DATA_BLK2_ADDR = APP_CACHED_DATA_BLK1_ADDR + APP_CACHED_DATA_BLK1_SIZE;
-APP_UNCACHED_DATA_BLK3_ADDR = DDR3_ADDR_1;
-
-myplatform = "ti.platforms.idkAM572X";
-
-Build.platformTable[myplatform] =
-{
- externalMemoryMap:
- [
- ["APP_CODE_MEM", {
- comment : "APP_CODE_MEM",
- name : "APP_CODE_MEM",
- base : APP_CODE_ADDR,
- len : APP_CODE_SIZE
- }],
- ["APP_CACHED_DATA_MEM", {
- comment : "APP_CACHED_DATA_MEM",
- name : "APP_CACHED_DATA_MEM",
- base : APP_CACHED_DATA_ADDR,
- len : APP_CACHED_DATA_SIZE
- }],
- ["APP_UNCACHED_DATA_BLK3_MEM", {
- comment : "APP_UNCACHED_DATA_BLK3_MEM",
- name : "APP_UNCACHED_DATA_BLK3_MEM",
- base : APP_UNCACHED_DATA_BLK3_ADDR,
- len : APP_UNCACHED_DATA_BLK3_SIZE
- }],
- ["APP_CACHED_DATA_BLK1_MEM", {
- comment : "APP_CACHED_DATA_BLK1_MEM",
- name : "APP_CACHED_DATA_BLK1_MEM",
- base : APP_CACHED_DATA_BLK1_ADDR,
- len : APP_CACHED_DATA_BLK1_SIZE
- }],
- ["APP_CACHED_DATA_BLK2_MEM", {
- comment : "APP_CACHED_DATA_BLK2_MEM",
- name : "APP_CACHED_DATA_BLK2_MEM",
- base : APP_CACHED_DATA_BLK2_ADDR,
- len : APP_CACHED_DATA_BLK2_SIZE
- }],
- ],
- codeMemory: "APP_CODE_MEM",
- dataMemory: "APP_CACHED_DATA_MEM",
- stackMemory: "APP_CACHED_DATA_MEM"
-};
diff --git a/packages/ti/build/am574x/config_am574x_a15.bld b/packages/ti/build/am574x/config_am574x_a15.bld
+++ /dev/null
@@ -1,169 +0,0 @@
-/*
-* Copyright (c) 2017, Texas Instruments Incorporated
-* All rights reserved.
-*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions
-* are met:
-*
-* * Redistributions of source code must retain the above copyright
-* notice, this list of conditions and the following disclaimer.
-*
-* * Redistributions in binary form must reproduce the above copyright
-* notice, this list of conditions and the following disclaimer in the
-* documentation and/or other materials provided with the distribution.
-*
-* * Neither the name of Texas Instruments Incorporated nor the names of
-* its contributors may be used to endorse or promote products derived
-* from this software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
-* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
-* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
-* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
-
-/*
- * ======== config_am574x_a15.bld ========
- * Build configuration script for BSP drivers
- */
-/* load the required modules for the configuration */
-var A15 = xdc.useModule('gnu.targets.arm.A15F');
-/* A15 compiler directory path */
-A15.rootDir = java.lang.System.getenv("CGTOOLS_A15");
-
-/* Read the current board */
-var CurrentPlatform = java.lang.System.getenv("BOARD");
-
-if (CurrentPlatform == null)
-{
- /* The env variable is probably not set while running inside CCS */
- CurrentPlatform = java.lang.System.getProperty("BOARD");
-}
-
-/*add bspLib to support SemiHosting to enable system_printf on A15*/
-/* GCC bare metal targets */
-var gccArmTargets = xdc.loadPackage('gnu.targets.arm');
-gccArmTargets.A15F.bspLib = "rdimon";
-
-/*
-Memory map
-
-DDR: 0x80000000 (Ist 512MB - Cached)
-
-NOTE: APP_CACHED_DATA_BLK1_MEM is used to route sections which needs to be in a
-separate section preferably at the end of 512 MB memory.
-For example:
-Frame buffer memory can be less at runtime depending on boards with lesser DDR (as in TDA 12x12 POP boards).
-If the same is routed to APP_CACHED_DATA_MEM section then the linker will
-place the frame buffer before other data section and the other data will fall into
-region outside the DDR in the board. Hence separate section is used!!
-
-+-----------------------------+
-| APP_CODE_MEM | 3MB
-+-----------------------------+
-| APP_CACHED_DATA_MEM | 20MB
-+-----------------------------+
-| APP_CACHED_DATA_BLK1_MEM | 244MB
-+-----------------------------+
-| APP_CACHED_DATA_BLK2_MEM | 128MB
-+-----------------------------+
-| NOT USED | Remaining MB
-+-----------------------------+
-
-DDR: 0xA0000000 (2nd 512MB - Non-Cached)
-+-----------------------------+
-| |
-| APP_UNCACHED_DATA_BLK3_MEM | 2MB
-+-----------------------------+
-| NOT USED | Remaining MB
-+-----------------------------+
-
-*/
-
-var KB=1024;
-var MB=KB*KB;
-
-var DDR3_ADDR_0;
-var DDR3_ADDR_1;
-
-var APP_CODE_ADDR;
-var APP_CODE_SIZE;
-
-var APP_CACHED_DATA_ADDR;
-var APP_CACHED_DATA_SIZE;
-
-var APP_UNCACHED_DATA_BLK3_ADDR;
-var APP_UNCACHED_DATA_BLK3_SIZE;
-
-var APP_CACHED_DATA_BLK1_ADDR;
-var APP_CACHED_DATA_BLK1_SIZE;
-
-var APP_CACHED_DATA_BLK2_ADDR;
-var APP_CACHED_DATA_BLK2_SIZE;
-
-/* First 4KB reserved for components such as SBL */
-SBL_SIZE = 4*KB;
-DDR3_ADDR_0 = 0x80000000 + SBL_SIZE;
-DDR3_ADDR_1 = 0xA0000000;
-
-APP_CODE_SIZE = 3*MB - SBL_SIZE;
-APP_CACHED_DATA_SIZE = 20*MB;
-APP_CACHED_DATA_BLK1_SIZE = 244*MB;
-APP_CACHED_DATA_BLK2_SIZE = 128*MB;
-APP_UNCACHED_DATA_BLK3_SIZE = 2*MB;
-
-APP_CODE_ADDR = DDR3_ADDR_0;
-APP_CACHED_DATA_ADDR = APP_CODE_ADDR + APP_CODE_SIZE;
-APP_CACHED_DATA_BLK1_ADDR = APP_CACHED_DATA_ADDR + APP_CACHED_DATA_SIZE;
-APP_CACHED_DATA_BLK2_ADDR = APP_CACHED_DATA_BLK1_ADDR + APP_CACHED_DATA_BLK1_SIZE;
-APP_UNCACHED_DATA_BLK3_ADDR = DDR3_ADDR_1;
-
-myplatform = "ti.platforms.idkAM572X";
-
-Build.platformTable[myplatform] =
-{
- externalMemoryMap:
- [
- ["APP_CODE_MEM", {
- comment : "APP_CODE_MEM",
- name : "APP_CODE_MEM",
- base : APP_CODE_ADDR,
- len : APP_CODE_SIZE
- }],
- ["APP_CACHED_DATA_MEM", {
- comment : "APP_CACHED_DATA_MEM",
- name : "APP_CACHED_DATA_MEM",
- base : APP_CACHED_DATA_ADDR,
- len : APP_CACHED_DATA_SIZE
- }],
- ["APP_UNCACHED_DATA_BLK3_MEM", {
- comment : "APP_UNCACHED_DATA_BLK3_MEM",
- name : "APP_UNCACHED_DATA_BLK3_MEM",
- base : APP_UNCACHED_DATA_BLK3_ADDR,
- len : APP_UNCACHED_DATA_BLK3_SIZE
- }],
- ["APP_CACHED_DATA_BLK1_MEM", {
- comment : "APP_CACHED_DATA_BLK1_MEM",
- name : "APP_CACHED_DATA_BLK1_MEM",
- base : APP_CACHED_DATA_BLK1_ADDR,
- len : APP_CACHED_DATA_BLK1_SIZE
- }],
- ["APP_CACHED_DATA_BLK2_MEM", {
- comment : "APP_CACHED_DATA_BLK2_MEM",
- name : "APP_CACHED_DATA_BLK2_MEM",
- base : APP_CACHED_DATA_BLK2_ADDR,
- len : APP_CACHED_DATA_BLK2_SIZE
- }],
- ],
- codeMemory: "APP_CODE_MEM",
- dataMemory: "APP_CACHED_DATA_MEM",
- stackMemory: "APP_CACHED_DATA_MEM"
-};
diff --git a/packages/ti/build/am574x/config_am574x_c66.bld b/packages/ti/build/am574x/config_am574x_c66.bld
+++ /dev/null
@@ -1,160 +0,0 @@
-/*
-* Copyright (c) 2017, Texas Instruments Incorporated
-* All rights reserved.
-*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions
-* are met:
-*
-* * Redistributions of source code must retain the above copyright
-* notice, this list of conditions and the following disclaimer.
-*
-* * Redistributions in binary form must reproduce the above copyright
-* notice, this list of conditions and the following disclaimer in the
-* documentation and/or other materials provided with the distribution.
-*
-* * Neither the name of Texas Instruments Incorporated nor the names of
-* its contributors may be used to endorse or promote products derived
-* from this software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
-* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
-* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
-* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
-/*
- * ======== config.bld ========
- * Sample Build configuration script
- */
-
-/* load the required modules for the configuration */
-var C66 = xdc.useModule('ti.targets.elf.C66');
-/* C66 compiler directory path */
-C66.rootDir = java.lang.System.getenv("CGTOOLS_DSP");
-
-/* compiler options */
-C66.ccOpts.suffix += " -mi10 -mo ";
-
-var CurrentPlatform = java.lang.System.getenv("BOARD");
-
-/*
-Memory map
-
-DDR: 0x80000000 (Ist 512MB - Cached)
-
-NOTE: APP_CACHED_DATA_BLK1_MEM is used to route sections which needs to be in a
-separate section preferably at the end of 512 MB memory.
-For example:
-Frame buffer memory can be less at runtime depending on boards with lesser DDR (as in TDA 12x12 POP boards).
-If the same is routed to APP_CACHED_DATA_MEM section then the linker will
-place the frame buffer before other data section and the other data will fall into
-region outside the DDR in the board. Hence separate section is used!!
-
-+-----------------------------+
-| APP_CODE_MEM | 3MB
-+-----------------------------+
-| APP_CACHED_DATA_MEM | 20MB
-+-----------------------------+
-| APP_CACHED_DATA_BLK1_MEM | 244MB
-+-----------------------------+
-| APP_CACHED_DATA_BLK2_MEM | 128MB
-+-----------------------------+
-| NOT USED | Remaining MB
-+-----------------------------+
-
-DDR: 0xA0000000 (2nd 512MB - Non-Cached)
-+-----------------------------+
-| |
-| APP_UNCACHED_DATA_BLK3_MEM | 2MB
-+-----------------------------+
-| NOT USED | Remaining MB
-+-----------------------------+
-
-*/
-
-var KB=1024;
-var MB=KB*KB;
-
-var DDR3_ADDR_0;
-var DDR3_ADDR_1;
-
-var APP_CODE_ADDR;
-var APP_CODE_SIZE;
-
-var APP_CACHED_DATA_ADDR;
-var APP_CACHED_DATA_SIZE;
-
-var APP_UNCACHED_DATA_BLK3_ADDR;
-var APP_UNCACHED_DATA_BLK3_SIZE;
-
-var APP_CACHED_DATA_BLK1_ADDR;
-var APP_CACHED_DATA_BLK1_SIZE;
-
-var APP_CACHED_DATA_BLK2_ADDR;
-var APP_CACHED_DATA_BLK2_SIZE;
-
-/* First 4KB reserved for components such as SBL */
-SBL_SIZE = 4*KB;
-DDR3_ADDR_0 = 0x80000000 + SBL_SIZE;
-DDR3_ADDR_1 = 0xA0000000;
-
-APP_CODE_SIZE = 3*MB - SBL_SIZE;
-APP_CACHED_DATA_SIZE = 20*MB;
-APP_CACHED_DATA_BLK1_SIZE = 244*MB;
-APP_CACHED_DATA_BLK2_SIZE = 128*MB;
-APP_UNCACHED_DATA_BLK3_SIZE = 2*MB;
-
-APP_CODE_ADDR = DDR3_ADDR_0;
-APP_CACHED_DATA_ADDR = APP_CODE_ADDR + APP_CODE_SIZE;
-APP_CACHED_DATA_BLK1_ADDR = APP_CACHED_DATA_ADDR + APP_CACHED_DATA_SIZE;
-APP_CACHED_DATA_BLK2_ADDR = APP_CACHED_DATA_BLK1_ADDR + APP_CACHED_DATA_BLK1_SIZE;
-APP_UNCACHED_DATA_BLK3_ADDR = DDR3_ADDR_1;
-
-myplatform = "ti.platforms.idkAM572X";
-
-Build.platformTable[myplatform] =
-{
- externalMemoryMap:
- [
- ["APP_CODE_MEM", {
- comment : "APP_CODE_MEM",
- name : "APP_CODE_MEM",
- base : APP_CODE_ADDR,
- len : APP_CODE_SIZE
- }],
- ["APP_CACHED_DATA_MEM", {
- comment : "APP_CACHED_DATA_MEM",
- name : "APP_CACHED_DATA_MEM",
- base : APP_CACHED_DATA_ADDR,
- len : APP_CACHED_DATA_SIZE
- }],
- ["APP_UNCACHED_DATA_BLK3_MEM", {
- comment : "APP_UNCACHED_DATA_BLK3_MEM",
- name : "APP_UNCACHED_DATA_BLK3_MEM",
- base : APP_UNCACHED_DATA_BLK3_ADDR,
- len : APP_UNCACHED_DATA_BLK3_SIZE
- }],
- ["APP_CACHED_DATA_BLK1_MEM", {
- comment : "APP_CACHED_DATA_BLK1_MEM",
- name : "APP_CACHED_DATA_BLK1_MEM",
- base : APP_CACHED_DATA_BLK1_ADDR,
- len : APP_CACHED_DATA_BLK1_SIZE
- }],
- ["APP_CACHED_DATA_BLK2_MEM", {
- comment : "APP_CACHED_DATA_BLK2_MEM",
- name : "APP_CACHED_DATA_BLK2_MEM",
- base : APP_CACHED_DATA_BLK2_ADDR,
- len : APP_CACHED_DATA_BLK2_SIZE
- }],
- ],
- codeMemory: "APP_CODE_MEM",
- dataMemory: "APP_CACHED_DATA_MEM",
- stackMemory: "APP_CACHED_DATA_MEM"
-};
diff --git a/packages/ti/build/am574x/mem_segment_definition_1024mb_bios.xs b/packages/ti/build/am574x/mem_segment_definition_1024mb_bios.xs
+++ /dev/null
@@ -1,261 +0,0 @@
-/*
-* Copyright (c) 2017, Texas Instruments Incorporated
-* All rights reserved.
-*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions
-* are met:
-*
-* * Redistributions of source code must retain the above copyright
-* notice, this list of conditions and the following disclaimer.
-*
-* * Redistributions in binary form must reproduce the above copyright
-* notice, this list of conditions and the following disclaimer in the
-* documentation and/or other materials provided with the distribution.
-*
-* * Neither the name of Texas Instruments Incorporated nor the names of
-* its contributors may be used to endorse or promote products derived
-* from this software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
-* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
-* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
-* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
-
-/*
- * ======== mem_segment_definition.xs ========
- * ======== Single file for the memory map configuration of all cores =========
- */
-
-KB=1024;
-MB=KB*KB;
-
-DDR3_ADDR = 0x80000000;
-DDR3_SIZE = 1024*MB;
-
-DDR3_BASE_ADDR_0 = 0x80000000;
-DDR3_BASE_SIZE_0 = 512*MB;
-
-/* The start address of the second mem section should be 16MB aligned.
- * for REMOTE_LOG_MEM sections.
- * tlb_config_eveX.c need to be modified otherwise
- */
-DDR3_BASE_ADDR_1 = 0xA0000000;
-DDR3_BASE_SIZE_1 = 512*MB;
-
-OCMC1_ADDR = 0x40300000;
-OCMC1_SIZE = 512*KB;
-
-DSP1_L2_SRAM_ADDR = 0x40800000;
-DSP1_L2_SRAM_SIZE = 288*KB;
-
-TOTAL_MEM_SIZE = (DDR3_SIZE);
-
-/* First 512 MB - cached */
-/* EVE vecs space should be align with 16MB boundary, and if possible try to fit
- * the entire vecs+code+data in 16MB section.
- * tlb_config_eveX.c need to be modified if any of these EVE memory sections or
- * SR1_FRAME_BUFFER_MEM section is modified.
- */
-IPU1_1_CODE_SIZE = 2*MB;
-IPU1_1_BSS_SIZE = 6*MB;
-IPU1_1_DATA_SIZE = 4*MB;
-IPU1_0_CODE_SIZE = 6*MB;
-IPU1_0_BSS_SIZE = 10*MB;
-IPU1_0_DATA_SIZE = 4*MB;
-SR1_FRAME_BUFFER_SIZE = 256*MB;
-DSP1_CODE_SIZE = 2*MB;
-DSP1_DATA_SIZE = 64*MB;
-/* A15_0_CODE_SIZE reduced since it is not used in .bld file.
- * Check .bld for details. Originally 2 + 14 MB.
- */
-A15_0_NDK_DATA_SIZE = 4*MB;
-A15_0_DATA_SIZE = 16*MB - A15_0_NDK_DATA_SIZE;
-
-
-
-/* Second 512 MB - non-cached */
-/* The start address of the second mem section should be 16MB aligned.
- * This alignment is a must as a single 16MB mapping is used for EMOTE_LOG_MEM sections.
- * tlb_config_eveX.c need to be modified otherwise
- */
-REMOTE_LOG_SIZE = 160*KB;
-SYSTEM_IPC_SHM_SIZE = 224*KB;
-LINK_STATS_SIZE = 256*KB;
-HDVPSS_DESC_SIZE = 1024*KB;
-SR0_SIZE = 128*KB;
-
-
-/* Cached Section */
-/* EVE vecs space should be align with 16MB boundary, and if possible try to fit
- * the entire vecs+code+data in 16MB section.
- * SR1_FRAME_BUFFER_MEM section is modified.
- */
-IPU1_1_CODE_ADDR = DDR3_BASE_ADDR_0;
-IPU1_1_DATA_ADDR = IPU1_1_CODE_ADDR + IPU1_1_CODE_SIZE;
-IPU1_1_BSS_ADDR = IPU1_1_DATA_ADDR + IPU1_1_DATA_SIZE;
-IPU1_0_CODE_ADDR = IPU1_1_BSS_ADDR + IPU1_1_BSS_SIZE;
-IPU1_0_DATA_ADDR = IPU1_0_CODE_ADDR + IPU1_0_CODE_SIZE;
-IPU1_0_BSS_ADDR = IPU1_0_DATA_ADDR + IPU1_0_DATA_SIZE;
-SR1_FRAME_BUFFER_ADDR = IPU1_0_BSS_ADDR + IPU1_0_BSS_SIZE;
-DSP1_CODE_ADDR = SR1_FRAME_BUFFER_ADDR + SR1_FRAME_BUFFER_SIZE;
-DSP1_DATA_ADDR = DSP1_CODE_ADDR + DSP1_CODE_SIZE;
-A15_0_NDK_DATA_ADDR = DSP1_DATA_ADDR + DSP1_DATA_SIZE;
-A15_0_DATA_ADDR = A15_0_NDK_DATA_ADDR + A15_0_NDK_DATA_SIZE;
-
-
-/* Non Cached Section */
-/* The start address of the second mem section should be 16MB aligned.
- * This alignment is a must as a single 16MB mapping is used for EMOTE_LOG_MEM sections.
- * tlb_config_eveX.c need to be modified otherwise
- */
-SR0_ADDR = DDR3_BASE_ADDR_1;
-REMOTE_LOG_ADDR = SR0_ADDR + SR0_SIZE;
-LINK_STATS_ADDR = REMOTE_LOG_ADDR + REMOTE_LOG_SIZE;
-SYSTEM_IPC_SHM_ADDR = LINK_STATS_ADDR + LINK_STATS_SIZE;
-HDVPSS_DESC_ADDR = SYSTEM_IPC_SHM_ADDR + SYSTEM_IPC_SHM_SIZE;
-
-if ((A15_0_DATA_ADDR + A15_0_DATA_SIZE) > (DDR3_BASE_ADDR_0 + DDR3_BASE_SIZE_0))
-{
- throw xdc.$$XDCException("MEMORY_MAP OVERFLOW ERROR ",
- "\nRegion End: " + "0x" + java.lang.Long.toHexString(DDR3_BASE_ADDR_0 + DDR3_BASE_SIZE_0) +
- "\nActual End: " + "0x" + java.lang.Long.toHexString(A15_0_DATA_ADDR + A15_0_DATA_SIZE));
-}
-
-if ((HDVPSS_DESC_ADDR + HDVPSS_DESC_SIZE) > (DDR3_BASE_ADDR_1 + DDR3_BASE_SIZE_1))
-{
- throw xdc.$$XDCException("MEMORY_MAP OVERFLOW ERROR ",
- "\nRegion End: " + "0x" + java.lang.Long.toHexString(DDR3_BASE_ADDR_1 + DDR3_BASE_SIZE_1) +
- "\nActual End: " + "0x" + java.lang.Long.toHexString(HDVPSS_DESC_ADDR + HDVPSS_DESC_SIZE));
-}
-
-if ((DDR3_BASE_SIZE_1 + DDR3_BASE_SIZE_0) > (TOTAL_MEM_SIZE))
-{
- throw xdc.$$XDCException("MEMORY_MAP EXCEEDS DDR SIZE ERROR ",
- "\nRegion End: " + "0x" + java.lang.Long.toHexString(DDR3_BASE_SIZE_1 + DDR3_BASE_SIZE_0) +
- "\nActual End: " + "0x" + java.lang.Long.toHexString(TOTAL_MEM_SIZE));
-}
-
-
-function getMemSegmentDefinition_external(core)
-{
- var memory = new Array();
- var index = 0;
-
- memory[index++] = ["IPU1_1_CODE_MEM", {
- comment : "IPU1_1_CODE_MEM",
- name : "IPU1_1_CODE_MEM",
- base : IPU1_1_CODE_ADDR,
- len : IPU1_1_CODE_SIZE
- }];
- memory[index++] = ["IPU1_1_DATA_MEM", {
- comment : "IPU1_1_DATA_MEM",
- name : "IPU1_1_DATA_MEM",
- base : IPU1_1_DATA_ADDR,
- len : IPU1_1_DATA_SIZE
- }];
- memory[index++] = ["IPU1_1_BSS_MEM", {
- comment : "IPU1_1_BSS_MEM",
- name : "IPU1_1_BSS_MEM",
- base : IPU1_1_BSS_ADDR,
- len : IPU1_1_BSS_SIZE
- }];
- memory[index++] = ["IPU1_0_CODE_MEM", {
- comment : "IPU1_0_CODE_MEM",
- name : "IPU1_0_CODE_MEM",
- base : IPU1_0_CODE_ADDR,
- len : IPU1_0_CODE_SIZE
- }];
- memory[index++] = ["IPU1_0_DATA_MEM", {
- comment : "IPU1_0_DATA_MEM",
- name : "IPU1_0_DATA_MEM",
- base : IPU1_0_DATA_ADDR,
- len : IPU1_0_DATA_SIZE
- }];
- memory[index++] = ["IPU1_0_BSS_MEM", {
- comment : "IPU1_0_BSS_MEM",
- name : "IPU1_0_BSS_MEM",
- base : IPU1_0_BSS_ADDR,
- len : IPU1_0_BSS_SIZE
- }];
- memory[index++] = ["DSP1_CODE_MEM", {
- comment : "DSP1_CODE_MEM",
- name : "DSP1_CODE_MEM",
- base : DSP1_CODE_ADDR,
- len : DSP1_CODE_SIZE
- }];
- memory[index++] = ["DSP1_DATA_MEM", {
- comment : "DSP1_DATA_MEM",
- name : "DSP1_DATA_MEM",
- base : DSP1_DATA_ADDR,
- len : DSP1_DATA_SIZE
- }];
-
- memory[index++] = ["A15_0_NDK_MEM", {
- comment : "A15_0_NDK_MEM",
- name : "A15_0_NDK_MEM",
- base : A15_0_NDK_DATA_ADDR,
- len : A15_0_NDK_DATA_SIZE
- }];
- memory[index++] = ["A15_0_DATA_MEM", {
- comment : "A15_0_DATA_MEM",
- name : "A15_0_DATA_MEM",
- base : A15_0_DATA_ADDR,
- len : A15_0_DATA_SIZE
- }];
- memory[index++] = ["SR1_FRAME_BUFFER_MEM", {
- comment : "SR1_FRAME_BUFFER_MEM",
- name : "SR1_FRAME_BUFFER_MEM",
- base : SR1_FRAME_BUFFER_ADDR,
- len : SR1_FRAME_BUFFER_SIZE
- }];
- memory[index++] = ["SR0", {
- comment : "SR0",
- name : "SR0",
- base : SR0_ADDR,
- len : SR0_SIZE
- }];
- memory[index++] = ["HDVPSS_DESC_MEM", {
- comment : "HDVPSS_DESC_MEM",
- name : "HDVPSS_DESC_MEM",
- base : HDVPSS_DESC_ADDR,
- len : HDVPSS_DESC_SIZE
- }];
- memory[index++] = ["REMOTE_LOG_MEM", {
- comment : "REMOTE_LOG_MEM",
- name : "REMOTE_LOG_MEM",
- base : REMOTE_LOG_ADDR,
- len : REMOTE_LOG_SIZE
- }];
- memory[index++] = ["LINK_STATS_MEM", {
- comment : "LINK_STATS_MEM",
- name : "LINK_STATS_MEM",
- base : LINK_STATS_ADDR,
- len : LINK_STATS_SIZE
- }];
- memory[index++] = ["SYSTEM_IPC_SHM_MEM", {
- comment : "SYSTEM_IPC_SHM_MEM",
- name : "SYSTEM_IPC_SHM_MEM",
- base : SYSTEM_IPC_SHM_ADDR,
- len : SYSTEM_IPC_SHM_SIZE
- }];
-
- xdc.print("# !!! Core is [" + core + "] !!!" );
-
- memory[index++] = ["DSP1_L2_SRAM", {
- comment: "DSP1_L2_SRAM",
- name: "DSP1_L2_SRAM",
- base: DSP1_L2_SRAM_ADDR,
- len: DSP1_L2_SRAM_SIZE
- }];
-
- return (memory);
-}
diff --git a/packages/ti/build/am64x/config_am64x_a53.bld b/packages/ti/build/am64x/config_am64x_a53.bld
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
-* Copyright (c) 2019, Texas Instruments Incorporated
-* All rights reserved.
-*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions
-* are met:
-*
-* * Redistributions of source code must retain the above copyright
-* notice, this list of conditions and the following disclaimer.
-*
-* * Redistributions in binary form must reproduce the above copyright
-* notice, this list of conditions and the following disclaimer in the
-* documentation and/or other materials provided with the distribution.
-*
-* * Neither the name of Texas Instruments Incorporated nor the names of
-* its contributors may be used to endorse or promote products derived
-* from this software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
-* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
-* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
-* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
-
-/*
- * ======== config_am64x_a53.bld ========
- * Common build configuration script for BIOS
- */
-
-var gccArmTargets = xdc.loadPackage('gnu.targets.arm');
-gccArmTargets.A53F.rootDir = java.lang.System.getenv("CGTOOLS_A53");
-gccArmTargets.A53F.bspLib = "rdimon";
-
-Build.targets = [ gccArmTargets.A53F ];
diff --git a/packages/ti/build/am64x/config_am64x_r5f.bld b/packages/ti/build/am64x/config_am64x_r5f.bld
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
-* Copyright (c) 2019, Texas Instruments Incorporated
-* All rights reserved.
-*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions
-* are met:
-*
-* * Redistributions of source code must retain the above copyright
-* notice, this list of conditions and the following disclaimer.
-*
-* * Redistributions in binary form must reproduce the above copyright
-* notice, this list of conditions and the following disclaimer in the
-* documentation and/or other materials provided with the distribution.
-*
-* * Neither the name of Texas Instruments Incorporated nor the names of
-* its contributors may be used to endorse or promote products derived
-* from this software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
-* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
-* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
-* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
-
-/*
- * ======== config_am64x_r5.bld ========
- * Build configuration script for BSP drivers
- */
-/* load the required modules for the configuration */
-var xdc_disable_thumb_mode = java.lang.System.getenv("XDC_DISABLE_THUMB_MODE");
-if(xdc_disable_thumb_mode != '' && xdc_disable_thumb_mode != null)
-{
-/* If XDC thumb mode is disabled, use the non-thumb mode xdc target */
-var R5F = xdc.useModule('ti.targets.arm.elf.R5F');
-}
-else
-{
-var R5F = xdc.useModule('ti.targets.arm.elf.R5Ft');
-}
-/* R5F compiler directory path */
-R5F.rootDir = java.lang.System.getenv("CGTOOLS");
diff --git a/packages/ti/build/am64x/linker_a53.lds b/packages/ti/build/am64x/linker_a53.lds
+++ /dev/null
@@ -1,204 +0,0 @@
-__STACK_SIZE = 0x20000;
-__TI_STACK_SIZE = __STACK_SIZE;
-
-MEMORY
-{
- /* am64x MCMS3 locations */
-
- /* Reserved for SBL code/data */
- SBL_RSVD (X) : ORIGIN = 0x70000000, LENGTH = 0x80000
-
- /* am64x Reserved Memory for ARM Trusted Firmware */
- MSMC3_ARM_STARTUP (RWIX) : ORIGIN = 0x000070080000, LENGTH = 0x800
- MSMC_MPU2 (RWX) : ORIGIN = 0x000070080800, LENGTH = 0x800
- MSMC_MPU1 (RWX) : ORIGIN = 0x000070081000, LENGTH = 0x40000-0x1000
-
- /* Reserved for SYSFW Secure Proxy */
- MSMC3_H (RWIX) : ORIGIN = 0x700C0000, LENGTH = 0x100000
-
- /* Reserved by ROM for SYSFW */
- SYSFW_RSVD_1 (X) : ORIGIN = 0x71C00000, LENGTH = 0x20000
- SYSFW_RSVD_2 (X) : ORIGIN = 0x71E00000, LENGTH = 0x20000
-
- DDR_MPU1 (RWX) : ORIGIN = 0x80000000, LENGTH = 0x80000000
-
-}
-REGION_ALIAS("REGION_TEXT_EL3", DDR_MPU1);
-REGION_ALIAS("BOOTVECTOR_EL3", DDR_MPU1);
-REGION_ALIAS("BOOTVECTOR", DDR_MPU1);
-REGION_ALIAS("REGION_TEXT", DDR_MPU1);
-REGION_ALIAS("REGION_BSS", DDR_MPU1);
-REGION_ALIAS("REGION_DATA", DDR_MPU1);
-REGION_ALIAS("REGION_STACK", DDR_MPU1);
-REGION_ALIAS("REGION_HEAP", DDR_MPU1);
-REGION_ALIAS("REGION_ARM_EXIDX", DDR_MPU1);
-REGION_ALIAS("REGION_ARM_EXTAB", DDR_MPU1);
-REGION_ALIAS("REGION_TEXT_STARTUP", DDR_MPU1);
-REGION_ALIAS("REGION_DATA_BUFFER", DDR_MPU1);
-REGION_ALIAS("IPC_DATA_BUFFER_1", DDR_MPU1);
-
-SECTIONS {
-
- .vecs : {
- *(.vecs)
- } > BOOTVECTOR AT> DDR_MPU1
-
- .vectors : {
- *(.vectors)
- } > BOOTVECTOR_EL3 AT> DDR_MPU1
- .text.el3 : {
- *(.text.el3)
- /* Ensure 8-byte alignment for descriptors and ensure inclusion */
- . = ALIGN(8);
- __RT_SVC_DESCS_START__ = .;
- KEEP(*(rt_svc_descs))
- __RT_SVC_DESCS_END__ = .;
- } > REGION_TEXT_EL3 AT> DDR_MPU1
-
- .text.csl_a53_startup : {
- *(.text.csl_a53_startup)
- *(.Entry)
- } > REGION_TEXT_STARTUP AT> REGION_TEXT_STARTUP
-
- .text : {
- CREATE_OBJECT_SYMBOLS
- *(.text)
- *(.text.*)
- . = ALIGN(0x8);
- KEEP (*(.ctors))
- . = ALIGN(0x4);
- KEEP (*(.dtors))
- . = ALIGN(0x8);
- __init_array_start = .;
- KEEP (*(.init_array*))
- __init_array_end = .;
- *(.init)
- *(.fini*)
- } > REGION_TEXT AT> REGION_TEXT
-
- PROVIDE (__etext = .);
- PROVIDE (_etext = .);
- PROVIDE (etext = .);
-
- .rodata : {
- *(.rodata)
- *(.rodata*)
- } > REGION_TEXT AT> REGION_TEXT
-
- .data_buffer : ALIGN (8) {
- __data_buffer_load__ = LOADADDR (.data_buffer);
- __data_buffer_start__ = .;
- *(.data_buffer)
- *(.data_buffer*)
- . = ALIGN (8);
- __data_buffer_end__ = .;
- } > REGION_DATA_BUFFER AT> REGION_DATA_BUFFER
-
- .data : ALIGN (8) {
- __data_load__ = LOADADDR (.data);
- __data_start__ = .;
- *(.data)
- *(.data*)
- . = ALIGN (8);
- __data_end__ = .;
- } > REGION_DATA AT> REGION_TEXT
-
- .ARM.exidx : {
- __exidx_start = .;
- *(.ARM.exidx* .gnu.linkonce.armexidx.*)
- __exidx_end = .;
- } > REGION_ARM_EXIDX AT> REGION_ARM_EXIDX
-
- .ARM.extab : {
- *(.ARM.extab* .gnu.linkonce.armextab.*)
- } > REGION_ARM_EXTAB AT> REGION_ARM_EXTAB
-
- .bss:extMemCache:ramdisk : {
- } > DDR_MPU1 /* MSMC_MPU1 */
-
- /* USB or any other LLD buffer for benchmarking */
- .benchmark_buffer (NOLOAD) : ALIGN (32) {
- } > DDR_MPU1
-
- .bss:frameBuffer (NOLOAD) : ALIGN (32) {
- } > DDR_MPU1
-
- ipc_data_buffer (NOLOAD) : ALIGN (32) {
- } > IPC_DATA_BUFFER_1
-
- /* For NDK packet memory, we need to map this sections before .bss*/
- .bss:NDK_PACKETMEM (NOLOAD) : ALIGN (128) {} > DDR_MPU1
- .bss:NDK_MMBUFFER (NOLOAD) : ALIGN (128) {} > DDR_MPU1
-
- .bss : {
- __bss_start__ = .;
- *(.shbss)
- *(.bss)
- *(.bss.*)
- . = ALIGN (8);
- __bss_end__ = .;
- . = ALIGN (8);
- *(COMMON)
- } > REGION_BSS AT> REGION_BSS
-
- .heap : {
- __heap_start__ = .;
- end = __heap_start__;
- _end = end;
- __end = end;
- KEEP(*(.heap))
- __heap_end__ = .;
- __HeapLimit = __heap_end__;
- } > REGION_HEAP AT> REGION_HEAP
-
- .stack (NOLOAD) : ALIGN(16) {
- _stack = .;
- __stack = .;
- KEEP(*(.stack))
- } > REGION_STACK AT> REGION_STACK
-
- __TI_STACK_BASE = __stack;
-
- /* Stabs debugging sections. */
- .stab 0 : { *(.stab) }
- .stabstr 0 : { *(.stabstr) }
- .stab.excl 0 : { *(.stab.excl) }
- .stab.exclstr 0 : { *(.stab.exclstr) }
- .stab.index 0 : { *(.stab.index) }
- .stab.indexstr 0 : { *(.stab.indexstr) }
- .comment 0 : { *(.comment) }
- /*
- * DWARF debug sections.
- * Symbols in the DWARF debugging sections are relative to the beginning
- * of the section so we begin them at 0.
- */
- /* DWARF 1 */
- .debug 0 : { *(.debug) }
- .line 0 : { *(.line) }
- /* GNU DWARF 1 extensions */
- .debug_srcinfo 0 : { *(.debug_srcinfo) }
- .debug_sfnames 0 : { *(.debug_sfnames) }
- /* DWARF 1.1 and DWARF 2 */
- .debug_aranges 0 : { *(.debug_aranges) }
- .debug_pubnames 0 : { *(.debug_pubnames) }
- /* DWARF 2 */
- .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
- .debug_abbrev 0 : { *(.debug_abbrev) }
- .debug_line 0 : { *(.debug_line .debug_line.* .debug_line_end ) }
- .debug_frame 0 : { *(.debug_frame) }
- .debug_str 0 : { *(.debug_str) }
- .debug_loc 0 : { *(.debug_loc) }
- .debug_macinfo 0 : { *(.debug_macinfo) }
- /* SGI/MIPS DWARF 2 extensions */
- .debug_weaknames 0 : { *(.debug_weaknames) }
- .debug_funcnames 0 : { *(.debug_funcnames) }
- .debug_typenames 0 : { *(.debug_typenames) }
- .debug_varnames 0 : { *(.debug_varnames) }
- /* DWARF 3 */
- .debug_pubtypes 0 : { *(.debug_pubtypes) }
- .debug_ranges 0 : { *(.debug_ranges) }
- /* DWARF Extension. */
- .debug_macro 0 : { *(.debug_macro) }
- .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }
- /DISCARD/ : { *(.note.GNU-stack) *(.gnu_debuglink) *(.gnu.lto_*) }
-}
diff --git a/packages/ti/build/am64x/linker_m4f.lds b/packages/ti/build/am64x/linker_m4f.lds
+++ /dev/null
@@ -1,82 +0,0 @@
-/* Linker Settings */
---retain="*(.bootCode)"
---retain="*(.startupCode)"
---retain="*(.startupData)"
---retain="*(.intvecs)"
---retain="*(.intc_text)"
---retain="*(.rstvectors)"
---retain="*(.irqStack)"
---retain="*(.fiqStack)"
---retain="*(.abortStack)"
---retain="*(.undStack)"
---retain="*(.svcStack)"
---fill_value=0
---stack_size=0x2000
---heap_size=0x1000
-
--stack 0x2000 /* SOFTWARE STACK SIZE */
--heap 0x2000 /* HEAP AREA SIZE */
-
-/* Stack Sizes for various modes */
-__IRQ_STACK_SIZE = 0x1000;
-__FIQ_STACK_SIZE = 0x1000;
-__ABORT_STACK_SIZE = 0x1000;
-__UND_STACK_SIZE = 0x1000;
-__SVC_STACK_SIZE = 0x1000;
-
-/* Memory Map */
-MEMORY
-{
- VECS_M4F_MEM: org = 0x00000000 len = 0x040
- IRAM_M4F_INTC_MEM: org = 0x00000040 len = 0x400 - 0x040
- /* Memory assigned to move vector table for M4F core */
- IRAM_M4F_VTBL: org = 0x00000400 len = 0x800
- /* M4F internal memory locations */
- IRAM_M4F_MEM (RWIX) : origin=0x0C00 length=0x30000 - 0xC00
- DRAM_M4F_MEM (RWIX) : origin=0x30000 length=0x10000
- DDR0 (RWIX) : origin=0x80000000 length=0x80000000 /* 2GB */
-}
-
-/* SPECIFY THE SECTIONS ALLOCATION INTO MEMORY */
-
-SECTIONS
-{
-
- .intvecs : load > VECS_M4F_MEM
- .intc_text : load > IRAM_M4F_INTC_MEM
- .TI.noinit : load > IRAM_M4F_VTBL
-
- .bootCode : {} palign(8) > IRAM_M4F_MEM
- .startupCode : {} palign(8) > IRAM_M4F_MEM
- .startupData : {} palign(8) > DRAM_M4F_MEM, type = NOINIT
- .text : {} palign(8) > IRAM_M4F_MEM
- .const : {} palign(8) > DRAM_M4F_MEM
- .cinit : {} palign(8) > DRAM_M4F_MEM
- .pinit : {} palign(8) > IRAM_M4F_MEM
- .bss : {} align(4) > DRAM_M4F_MEM
- .far : {} align(4) > DRAM_M4F_MEM
- .data : {} palign(128) > DRAM_M4F_MEM
- .boardcfg_data : {} palign(128) > DRAM_M4F_MEM
- .sysmem : {} > DRAM_M4F_MEM
- .data_buffer : {} palign(128) > DRAM_M4F_MEM
-
- /* USB or any other LLD buffer for benchmarking */
- .benchmark_buffer (NOLOAD) {} ALIGN (8) > DDR0
-
- .stack : {} align(4) > DRAM_M4F_MEM
- .irqStack : {. = . + __IRQ_STACK_SIZE;} align(4) > DRAM_M4F_MEM
- RUN_START(__IRQ_STACK_START)
- RUN_END(__IRQ_STACK_END)
- .fiqStack : {. = . + __FIQ_STACK_SIZE;} align(4) > DRAM_M4F_MEM
- RUN_START(__FIQ_STACK_START)
- RUN_END(__FIQ_STACK_END)
- .abortStack : {. = . + __ABORT_STACK_SIZE;} align(4) > DRAM_M4F_MEM
- RUN_START(__ABORT_STACK_START)
- RUN_END(__ABORT_STACK_END)
- .undStack : {. = . + __UND_STACK_SIZE;} align(4) > DRAM_M4F_MEM
- RUN_START(__UND_STACK_START)
- RUN_END(__UND_STACK_END)
- .svcStack : {. = . + __SVC_STACK_SIZE;} align(4) > DRAM_M4F_MEM
- RUN_START(__SVC_STACK_START)
- RUN_END(__SVC_STACK_END)
-}
diff --git a/packages/ti/build/am64x/linker_r5.lds b/packages/ti/build/am64x/linker_r5.lds
+++ /dev/null
@@ -1,92 +0,0 @@
-/* Linker Settings */
---retain="*(.bootCode)"
---retain="*(.startupCode)"
---retain="*(.startupData)"
---retain="*(.intvecs)"
---retain="*(.intc_text)"
---retain="*(.rstvectors)"
---retain="*(.irqStack)"
---retain="*(.fiqStack)"
---retain="*(.abortStack)"
---retain="*(.undStack)"
---retain="*(.svcStack)"
---fill_value=0
---stack_size=0x2000
---heap_size=0x1000
---entry_point=_resetvectors /* Default C RTS boot.asm */
-
--stack 0x2000 /* SOFTWARE STACK SIZE */
--heap 0x2000 /* HEAP AREA SIZE */
-
-/* Stack Sizes for various modes */
-__IRQ_STACK_SIZE = 0x1000;
-__FIQ_STACK_SIZE = 0x1000;
-__ABORT_STACK_SIZE = 0x1000;
-__UND_STACK_SIZE = 0x1000;
-__SVC_STACK_SIZE = 0x1000;
-
-/* Memory Map */
-MEMORY
-{
-
- /* Reserved for SBL code/data */
- SBL_RSVD (X) : origin=0x70000000 length=0x80000
-
- /* Reset Vectors base address(RESET_VECTORS) should be 64 bytes aligned */
- RESET_VECTORS (X) : origin=0x70080000 length=0x100
- /* am64x MCMS3 locations */
- MSMC3 (RWIX) : origin=0x70080100 length=0x40000 - 0x1100
-
- VECTORS (X) : origin=0x700BF000 length=0x1000
- /* Reserved for SYSFW Secure Proxy */
- MSMC3_H (RWIX) : origin=0x700C0000 length=0x100000
-
- /* Reserved by ROM for SYSFW */
- SYSFW_RSVD_1 (X) : origin=0x71C00000 length=0x20000
- SYSFW_RSVD_2 (X) : origin=0x71E00000 length=0x20000
-
- DDR0 (RWIX) : origin=0x80000000 length=0x80000000 /* 2GB */
-}
-
-/* Section Configuration */
-SECTIONS
-{
- /* 'intvecs' and 'intc_text' sections shall be placed within */
- /* a range of +\- 16 MB */
- .intvecs : {} palign(8) > VECTORS
- .intc_text : {} palign(8) > VECTORS
- .rstvectors : {} palign(8) > RESET_VECTORS
- .bootCode : {} palign(8) > MSMC3
- .startupCode : {} palign(8) > MSMC3
- .startupData : {} palign(8) > MSMC3, type = NOINIT
- .text : {} palign(8) > DDR0
- .const : {} palign(8) > DDR0
- .cinit : {} palign(8) > DDR0
- .pinit : {} palign(8) > DDR0
- .bss : {} align(4) > DDR0
- .far : {} align(4) > DDR0
- .data : {} palign(128) > DDR0
- .boardcfg_data : {} palign(128) > DDR0
- .sysmem : {} > DDR0
- .data_buffer : {} palign(128) > DDR0
-
- /* USB or any other LLD buffer for benchmarking */
- .benchmark_buffer (NOLOAD) {} ALIGN (8) > DDR0
-
- .stack : {} align(4) > DDR0
- .irqStack : {. = . + __IRQ_STACK_SIZE;} align(4) > DDR0
- RUN_START(__IRQ_STACK_START)
- RUN_END(__IRQ_STACK_END)
- .fiqStack : {. = . + __FIQ_STACK_SIZE;} align(4) > DDR0
- RUN_START(__FIQ_STACK_START)
- RUN_END(__FIQ_STACK_END)
- .abortStack : {. = . + __ABORT_STACK_SIZE;} align(4) > DDR0
- RUN_START(__ABORT_STACK_START)
- RUN_END(__ABORT_STACK_END)
- .undStack : {. = . + __UND_STACK_SIZE;} align(4) > DDR0
- RUN_START(__UND_STACK_START)
- RUN_END(__UND_STACK_END)
- .svcStack : {. = . + __SVC_STACK_SIZE;} align(4) > DDR0
- RUN_START(__SVC_STACK_START)
- RUN_END(__SVC_STACK_END)
-}
diff --git a/packages/ti/build/am64x/linker_r5_sysbios.lds b/packages/ti/build/am64x/linker_r5_sysbios.lds
+++ /dev/null
@@ -1,56 +0,0 @@
-/* linker options */
---fill_value=0
---stack_size=0x2000
---heap_size=0x1000
-
--e __VECS_ENTRY_POINT
---retain="*(.utilsCopyVecsToAtcm)"
-
-MEMORY
-{
- /* Reserved for SBL code/data */
- SBL_RSVD (X) : origin=0x70000000 length=0x80000
-
- /* Reset Vectors base address(RESET_VECTORS) should be 64 bytes aligned */
- RESET_VECTORS (X) : origin=0x70080000 length=0x100
- /* am64x MCMS3 locations */
- MSMC3 (RWIX) : origin=0x70080100 length=0x40000 - 0x1100
-
- VECTORS (X) : origin=0x700BF000 length=0x1000
- /* Reserved for SYSFW Secure Proxy */
- MSMC3_H (RWIX) : origin=0x700C0000 length=0x100000
-
- /* Reserved by ROM for SYSFW */
- SYSFW_RSVD_1 (X) : origin=0x71C00000 length=0x20000
- SYSFW_RSVD_2 (X) : origin=0x71E00000 length=0x20000
-
- DDR0 (RWIX) : origin=0x80000000 length=0x80000000 /* 2GB */
-}
-
-SECTIONS
-{
- .vecs : {
- __VECS_ENTRY_POINT = .;
- } palign(8) > RESET_VECTORS
- .text_boot {
- *boot.aer5f*<*boot.o*>(.text)
- } palign(8) > MSMC3
- .text:xdc_runtime_Startup_reset__I : {} palign(8) > MSMC3
- .text:ti_sysbios_family_arm_v7r_Cache* : {} palign(8) > MSMC3
- .text:ti_sysbios_family_arm_MPU* : {} palign(8) > MSMC3
- .utilsCopyVecsToAtcm : {} palign(8) > MSMC3
-
- .text : {} palign(8) > DDR0
- .cinit : {} palign(8) > DDR0
- .bss : {} align(8) > DDR0
- .far : {} align(8) > DDR0
- .const : {} palign(8) > DDR0
- .data : {} palign(128) > DDR0
- .sysmem : {} align(8) > DDR0
- .stack : {} align(4) > DDR0
- .data_buffer: {} palign(128) > DDR0
-
- .benchmark_buffer: (NOLOAD) {} align (8) > DDR0
-
-
-}
diff --git a/packages/ti/build/am64x/r5_mpu.xs b/packages/ti/build/am64x/r5_mpu.xs
+++ /dev/null
@@ -1,159 +0,0 @@
-/*
- * Copyright (c) 2019, Texas Instruments Incorporated
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * * Neither the name of Texas Instruments Incorporated nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
- * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
- * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
- * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
- * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-/*
- * ======== event_MPU.xs ========
- * MPU Settings for am64x device's Cortex-R5F
- */
-
-/*
- * -------------------------------------------------------------------------------------------------------------
- * | Id | Base Address | Size | En | Cacheable | XN | AccPerm | Mask |
- * |----|--------------|------|----|-------------------------------------------|----|---------------------|------|
- * | 0 | 0x00000000 | 4GB | T | uncacheable, Shareable | F | RW at PL 1 & PL 2 | 0x0 |
- * |----|--------------|------|----|-------------------------------------------|----|---------------------|------|
- * | 1 | 0 (local TCM)| 32K | T | Write-Back, Write-Allocate, Non-Shareable | F | RW at PL 1 | 0x0 |
- * |----|--------------|------|----|-------------------------------------------|----|---------------------|------|
- * | 2 | 0x41000000 | 32K | T | Write-Back, Write-Allocate, Non-Shareable | F | RW at PL 1 | 0x0 |
- * |----|--------------|------|----|-------------------------------------------|----|---------------------|------|
- * | 3 | 0x41010000 | 32K | T | Write-Back, Write-Allocate, Non-Shareable | F | RW at PL 1 | 0x0 |
- * |----|--------------|------|----|-------------------------------------------|----|---------------------|------|
- * | 4 | 0x41C00000 | 1MB | T | Write-Back, Write-Allocate, Non-Shareable | F | RW at PL 1 | 0x0 |
- * -------------------------------------------------------------------------------------------------------------
- * | 5 | 0x70000000 | 8MB | T | MSMC Ram - Cachable | F | RW at PL 1 | 0x0 |
- * -------------------------------------------------------------------------------------------------------------
- * | 6 | 0x80000000 | 2GB | T | DDR - Strongly Ordered, Shareable | F | RW at PL 1 & PL 3 | 0x0 |
- * -------------------------------------------------------------------------------------------------------------
- * | 7 | 0xA5000000 | 8MB | T | DDR (VRing Buffer) - Uncacheble | F | RW at PL 1 & PL 3 | 0x0 |
- * |-------------------------------------------------------------------------------------------------------------|
- */
-
-/*
- * Note: Marking a region as shareable will cause the region to behave as outer shareable with write through
- * no write-allocate caching policy irrespective of the actual cache policy set. Therefore, only select
- * regions that are actually shared outside the R5 CPUSS must be marked as shared.
- */
-
-var MPU = xdc.useModule('ti.sysbios.family.arm.MPU');
-MPU.enableMPU = true;
-MPU.enableBackgroundRegion = true;
-
-var attrs = new MPU.RegionAttrs();
-MPU.initRegionAttrsMeta(attrs);
-
-/* This entry covers the whole 32 bit memory range
- Address: 0x00000000-0xffffffff */
-attrs.enable = true;
-attrs.bufferable = false;
-attrs.cacheable = false;
-attrs.shareable = true;
-attrs.noExecute = true;
-attrs.accPerm = 1; /* RW at PL1 */
-attrs.tex = 0;
-attrs.subregionDisableMask = 0;
-MPU.setRegionMeta(0, 0x00000000, MPU.RegionSize_4G, attrs);
-
-/* This entry covers the ATCM mapped to 0 */
-attrs.enable = true;
-attrs.bufferable = true;
-attrs.cacheable = true;
-attrs.shareable = true;
-attrs.noExecute = false;
-attrs.accPerm = 1; /* RW at PL1 */
-attrs.tex = 1;
-attrs.subregionDisableMask = 0;
-MPU.setRegionMeta(1, 0x00000000, MPU.RegionSize_32K, attrs);
-
-/* This entry covers ATCM if mapped to 0x41000000 */
-attrs.enable = true;
-attrs.bufferable = true;
-attrs.cacheable = true;
-attrs.shareable = false;
-attrs.noExecute = false;
-attrs.accPerm = 1; /* RW at PL1 */
-attrs.tex = 1;
-attrs.subregionDisableMask = 0;
-MPU.setRegionMeta(2, 0x41000000, MPU.RegionSize_32K, attrs);
-
-/* This entry covers BTCM if mapped to 0x41010000 */
-attrs.enable = true;
-attrs.bufferable = true;
-attrs.cacheable = true;
-attrs.shareable = false;
-attrs.noExecute = false;
-attrs.accPerm = 1; /* RW at PL1 */
-attrs.tex = 1;
-attrs.subregionDisableMask = 0x0;
-MPU.setRegionMeta(3, 0x41010000, MPU.RegionSize_32K, attrs);
-
-/* This entry covers RAM0 */
-attrs.enable = true;
-attrs.bufferable = true;
-attrs.cacheable = true;
-attrs.shareable = false;
-attrs.noExecute = false;
-attrs.accPerm = 1; /* RW at PL1 */
-attrs.tex = 1;
-attrs.subregionDisableMask = 0;
-MPU.setRegionMeta(4, 0x41C00000, MPU.RegionSize_1M, attrs);
-
-/* This entry covers MSMC SRAM */
-attrs.enable = true;
-attrs.bufferable = true;
-attrs.cacheable = true;
-attrs.shareable = false;
-attrs.noExecute = false;
-attrs.accPerm = 1; /* RW at PL1 */
-attrs.tex = 1;
-attrs.subregionDisableMask = 0;
-MPU.setRegionMeta(5, 0x70000000, MPU.RegionSize_8M, attrs);
-
-/* This entry covers DDR memory */
-attrs.enable = true;
-attrs.bufferable = true;
-attrs.cacheable = true;
-attrs.shareable = false;
-attrs.noExecute = false;
-attrs.accPerm = 0x3; /* RW at PL1 & PL2 */
-attrs.tex = 1;
-attrs.subregionDisableMask = 0;
-MPU.setRegionMeta(6, 0x80000000, MPU.RegionSize_2G, attrs);
-
-/* Ring Buffer uncached.... */
-attrs.enable = true;
-attrs.bufferable = false;
-attrs.cacheable = false;
-attrs.shareable = true;
-attrs.noExecute = true;
-attrs.accPerm = 3; /* RW at PL1 */
-attrs.tex = 0;
-attrs.subregionDisableMask = 0;
-MPU.setRegionMeta(7, 0xA5000000, MPU.RegionSize_8M, attrs);
diff --git a/packages/ti/build/am64x/sbl_mcux_0_dummy_app.map b/packages/ti/build/am64x/sbl_mcux_0_dummy_app.map
+++ /dev/null
@@ -1,393 +0,0 @@
-******************************************************************************
- TI ARM Linker Unix v20.2.0
-******************************************************************************
->> Linked Fri Dec 11 18:56:00 2020
-
-OUTPUT FILE NAME: </home/a0211050/ti/workarea2/pdk/packages/ti/binary/ipc_echo_baremetal_testb/bin/am64x_evm/ipc_echo_baremetal_testb_mcu1_0_release.xer5f>
-ENTRY POINT SYMBOL: "_resetvectors" address: 41010000
-
-
-MEMORY CONFIGURATION
-
- name origin length used unused attr fill
----------------------- -------- --------- -------- -------- ---- --------
- RESET_VECTORS 00000000 00000100 00000000 00000100 X
- MCU0_R5F_TCMA 00000100 00007f00 00000000 00007f00 X
- MCU1_R5F0_ATCM 41000000 00008000 00000000 00008000 RWIX
- MCU1_R5F0_BTCM_VECS 41010000 00000100 00000040 000000c0 RWIX
- MCU1_R5F0_BTCM 41010100 00007f00 00005248 00002cb8 RWIX
- OCMRAM 41c00100 0007ef00 00000000 0007ef00 RWIX
- MSMC3_ARM_FW 70000000 00040000 00000000 00040000 RWIX
- MSMC3 70040000 007b0000 00000000 007b0000 RWIX
- MSMC3_DMSC_FW 707f0000 00010000 00000000 00010000 RWIX
- DDR0_RESERVED 80000000 20000000 00000000 20000000 RWIX
- MCU1_0_IPC_DATA a0000000 00100000 00000000 00100000 RWIX
- MCU1_0_EXT_DATA a0100000 00100000 00000000 00100000 RWIX
- MCU1_0_R5F_MEM_TEXT a0200000 00100000 00000000 00100000 RWIX
- MCU1_0_R5F_MEM_DATA a0300000 00100000 00000000 00100000 RWIX
- MCU1_0_DDR_SPACE a0400000 00c00000 00000000 00c00000 RWIX
- MCU1_1_IPC_DATA a1000000 00100000 00000000 00100000 RWIX
- MCU1_1_EXT_DATA a1100000 00100000 00000000 00100000 RWIX
- MCU1_1_R5F_MEM_TEXT a1200000 00100000 00000000 00100000 RWIX
- MCU1_1_R5F_MEM_DATA a1300000 00100000 00000000 00100000 RWIX
- MCU1_1_DDR_SPACE a1400000 00c00000 00000000 00c00000 RWIX
- MCU2_0_IPC_DATA a2000000 00100000 00000000 00100000 RWIX
- MCU2_0_EXT_DATA a2100000 00100000 00000000 00100000 RWIX
- MCU2_0_R5F_MEM_TEXT a2200000 00100000 00000000 00100000 RWIX
- MCU2_0_R5F_MEM_DATA a2300000 00100000 00000000 00100000 RWIX
- MCU2_0_DDR_SPACE a2400000 00c00000 00000000 00c00000 RWIX
- MCU2_1_IPC_DATA a3000000 00100000 00000000 00100000 RWIX
- MCU2_1_EXT_DATA a3100000 00100000 00000000 00100000 RWIX
- MCU2_1_R5F_MEM_TEXT a3200000 00100000 00000000 00100000 RWIX
- MCU2_1_R5F_MEM_DATA a3300000 00100000 00000000 00100000 RWIX
- MCU2_1_DDR_SPACE a3400000 00c00000 00000000 00c00000 RWIX
-
-
-SEGMENT ALLOCATION MAP
-
-run origin load origin length init length attrs members
----------- ----------- ---------- ----------- ----- -------
-41010000 41010000 00000040 00000040 r-x
- 41010000 41010000 00000040 00000040 r-x .rstvectors
-41010100 41010100 00001e80 00001e80 rwx
- 41010100 41010100 00001e80 00001e80 rwx .data
-41011f80 41011f80 00000ec8 00000ec8 r-x
- 41011f80 41011f80 000004c8 000004c8 r-x .text
- 41012448 41012448 00000328 00000328 r-x .startupCode
- 41012770 41012770 00000318 00000318 r-- .startupData
- 41012a88 41012a88 000002c0 000002c0 r-- .const
- 41012d48 41012d48 00000100 00000100 r-x .bootCode
-41015b00 41015b00 00000500 00000000 r--
- 41015b00 41015b00 00000100 00000000 r-- .undStack
- 41015c00 41015c00 00000100 00000000 r-- .svcStack
- 41015d00 41015d00 00000100 00000000 r-- .irqStack
- 41015e00 41015e00 00000100 00000000 r-- .fiqStack
- 41015f00 41015f00 00000100 00000000 r-- .abortStack
-41016000 41016000 00002000 00000000 rw-
- 41016000 41016000 00002000 00000000 rw- .stack
-
-
-SECTION ALLOCATION MAP
-
- output attributes/
-section page origin length input sections
--------- ---- ---------- ---------- ----------------
-.rstvectors
-* 0 41010000 00000040
- 41010000 00000040 ti.csl.init.aer5f : boot.oer5f (.rstvectors)
-
-.text 0 41011f80 000004c8
- 41011f80 00000100 ti.csl.aer5f : interrupt.oer5f (.text:masterIsr)
- 41012080 00000078 : interrupt.oer5f (.text:dataAbortExptnHandler)
- 410120f8 00000078 : interrupt.oer5f (.text:fiqExptnHandler)
- 41012170 00000078 : interrupt.oer5f (.text:irqExptnHandler)
- 410121e8 00000078 : interrupt.oer5f (.text:prefetchAbortExptnHandler)
- 41012260 00000074 : interrupt.oer5f (.text:undefInstructionExptnHandler)
- 410122d4 00000068 rtsv7R4_A_le_v3D16_eabi.lib : autoinit.c.obj (.text:__TI_auto_init_nobinit_nopinit:__TI_auto_init_nobinit_nopinit)
- 4101233c 0000004c ti.csl.aer5f : interrupt.oer5f (.text:swIntrExptnHandler)
- 41012388 0000002c : csl_vim.oer5f (.text:CSL_vimGetActivePendingIntr)
- 410123b4 0000002a : csl_vim.oer5f (.text:CSL_vimClrIntrPending)
- 410123de 00000002 --HOLE-- [fill = 00000000]
- 410123e0 00000020 rtsv7R4_A_le_v3D16_eabi.lib : args_main.c.obj (.text:_args_main)
- 41012400 0000000c <whole-program> (.tramp.main.1)
- 4101240c 0000001a ti.csl.aer5f : csl_vim.oer5f (.text:CSL_vimAckIntr)
- 41012426 00000002 --HOLE-- [fill = 00000000]
- 41012428 00000014 main_baremetal.oer5f (.text:main)
- 4101243c 00000008 rtsv7R4_A_le_v3D16_eabi.lib : exit.c.obj (.text:abort:abort)
- 41012444 00000004 --HOLE-- [fill = 00000000]
-
-.startupCode
-* 0 41012448 00000328
- 41012448 0000017a ti.csl.init.aer5f : r5_startup.oer5f (.startupCode)
- 410125c2 00000002 : startup.oer5f (.startupCode:_system_post_cinit)
- 410125c4 000000b0 : startup.oer5f (.startupCode:CSL_armR5MPUCfg)
- 41012674 00000068 : startup.oer5f (.startupCode:__mpu_init)
- 410126dc 00000048 : startup.oer5f (.startupCode:CSL_startupVimSetIntrEnable)
- 41012724 0000002c : startup.oer5f (.startupCode:CSL_startupVimClrIntrPending)
- 41012750 0000001a : startup.oer5f (.startupCode:CSL_armR5StartupGetCpuID)
- 4101276a 00000004 : startup.oer5f (.startupCode:_system_pre_init)
- 4101276e 00000002 --HOLE-- [fill = 00000000]
-
-.startupData
-* 0 41012770 00000318
- 41012770 00000314 ti.csl.init.aer5f : startup.oer5f (.startupData)
- 41012a84 00000004 --HOLE-- [fill = 00000000]
-
-.const 0 41012a88 000002c0
- 41012a88 000002c0 r5f_mpu_am64x_default.oer5f (.const:gCslR5MpuCfg)
-
-.bootCode
-* 0 41012d48 00000100
- 41012d48 000000fc ti.csl.init.aer5f : boot.oer5f (.bootCode)
- 41012e44 00000004 --HOLE-- [fill = 00000000]
-
-.cinit 0 41010100 00000000 UNINITIALIZED
-
-.data 0 41010100 00001e80
- 41010100 00001e34 ti.csl.aer5f : interrupt.oer5f (.data:$O2$$)
- 41011f34 00000008 ti.csl.init.aer5f : boot.oer5f (.data)
- 41011f3c 00000004 main_baremetal.oer5f (.data)
- 41011f40 00000004 rtsv7R4_A_le_v3D16_eabi.lib : stkdepth_vars.c.obj (.data)
- 41011f44 0000003c --HOLE-- [fill = 00000000]
-
-.undStack
-* 0 41015b00 00000100 UNINITIALIZED
- 41015b00 00000100 --HOLE--
-
-.svcStack
-* 0 41015c00 00000100 UNINITIALIZED
- 41015c00 00000100 --HOLE--
-
-.irqStack
-* 0 41015d00 00000100 UNINITIALIZED
- 41015d00 00000100 --HOLE--
-
-.fiqStack
-* 0 41015e00 00000100 UNINITIALIZED
- 41015e00 00000100 --HOLE--
-
-.abortStack
-* 0 41015f00 00000100 UNINITIALIZED
- 41015f00 00000100 --HOLE--
-
-.resource_table
-* 0 a0100000 00000000 UNINITIALIZED
-
-.stack 0 41016000 00002000 UNINITIALIZED
- 41016000 00002000 --HOLE--
-
-__llvm_prf_cnts
-* 0 41010100 00000000 UNINITIALIZED
-
-MODULE SUMMARY
-
- Module code ro data rw data
- ------ ---- ------- -------
- /home/a0211050/ti/workarea2/pdk/packages/ti/binary/ipc_echo_baremetal_testb/obj/am64x_evm/mcu1_0/release/
- r5f_mpu_am64x_default.oer5f 0 704 0
- main_baremetal.oer5f 20 0 4
- +--+-----------------------------+------+---------+---------+
- Total: 20 704 4
-
- /tmp/
- TI5cm6zQbcy 12 0 0
- +--+-----------------------------+------+---------+---------+
- Total: 12 0 0
-
- /home/a0211050/ti/workarea2/pdk/packages/ti/csl/lib/am64x/r5f/release/ti.csl.aer5f
- interrupt.oer5f 928 0 7732
- csl_vim.oer5f 112 0 0
- +--+-----------------------------+------+---------+---------+
- Total: 1040 0 7732
-
- /home/a0211050/ti/workarea2/pdk/packages/ti/csl/lib/am64x/r5f/release/ti.csl.init.aer5f
- startup.oer5f 428 788 0
- r5_startup.oer5f 378 0 0
- boot.oer5f 324 0 0
- +--+-----------------------------+------+---------+---------+
- Total: 1130 788 0
-
- /home/a0211050/ti/workarea2/ti-cgt-arm_20.2.0.LTS/lib/rtsv7R4_A_le_v3D16_eabi.lib
- autoinit.c.obj 104 0 0
- args_main.c.obj 32 0 0
- exit.c.obj 8 0 0
- stkdepth_vars.c.obj 0 0 4
- +--+-----------------------------+------+---------+---------+
- Total: 144 0 4
-
- Stack: 0 0 8192
- +--+-----------------------------+------+---------+---------+
- Grand Total: 2346 1492 15932
-
-VENEERS
-
-callee name veneer name
- callee addr veneer addr call addr call info
--------------- ----------- --------- ----------------
-main $Ven$AT$L$PI$$main
- 41012429 41012400 410123f8 rtsv7R4_A_le_v3D16_eabi.lib : args_main.c.obj (.text:_args_main)
-
-[1 trampolines]
-[1 trampoline calls]
-
-
-GLOBAL SYMBOLS: SORTED ALPHABETICALLY BY Name
-
-address name
-------- ----
-4101243c C$$EXIT
-410125c5 CSL_armR5MPUCfg
-410125ad CSL_armR5SetDLFOBit
-41012449 CSL_armR5StartupCacheEnableAllCache
-41012499 CSL_armR5StartupCacheEnableDCache
-41012459 CSL_armR5StartupCacheEnableForceWrThru
-41012471 CSL_armR5StartupCacheEnableICache
-410124ed CSL_armR5StartupCacheInvalidateAllCache
-410124d7 CSL_armR5StartupCacheInvalidateAllDcache
-410124c1 CSL_armR5StartupCacheInvalidateAllIcache
-41012541 CSL_armR5StartupFpuEnable
-41012751 CSL_armR5StartupGetCpuID
-4101257d CSL_armR5StartupIntrEnableFiq
-41012595 CSL_armR5StartupIntrEnableIrq
-41012561 CSL_armR5StartupIntrEnableVic
-4101251d CSL_armR5StartupMpuCfgRegion
-410124fd CSL_armR5StartupMpuEnable
-41012537 CSL_armR5StartupReadMpidrReg
-41012725 CSL_startupVimClrIntrPending
-410126dd CSL_startupVimSetIntrEnable
-4101240d CSL_vimAckIntr
-410123b5 CSL_vimClrIntrPending
-41012389 CSL_vimGetActivePendingIntr
-41012e35 HF
-41016000 __ABORT_STACK_END
-00000100 __ABORT_STACK_SIZE
-41015f00 __ABORT_STACK_START
-41015f00 __FIQ_STACK_END
-00000100 __FIQ_STACK_SIZE
-41015e00 __FIQ_STACK_START
-41015e00 __IRQ_STACK_END
-00000100 __IRQ_STACK_SIZE
-41015d00 __IRQ_STACK_START
-a0100000 __RESOURCE_TABLE
-41018000 __STACK_END
-00002000 __STACK_SIZE
-41015d00 __SVC_STACK_END
-00000100 __SVC_STACK_SIZE
-41015c00 __SVC_STACK_START
-UNDEFED __TI_CINIT_Base
-UNDEFED __TI_CINIT_Limit
-UNDEFED __TI_Handler_Table_Base
-UNDEFED __TI_Handler_Table_Limit
-410122d4 __TI_auto_init_nobinit_nopinit
-ffffffff __TI_pprof_out_hndl
-ffffffff __TI_prof_data_size
-ffffffff __TI_prof_data_start
-41010000 __TI_static_base__
-41015c00 __UND_STACK_END
-00000100 __UND_STACK_SIZE
-41015b00 __UND_STACK_START
-ffffffff __binit__
-ffffffff __c_args__
-41012675 __mpu_init
-41016000 __stack
-41010100 __start___llvm_prf_cnts
-41010100 __stop___llvm_prf_cnts
-410123e0 _args_main
-41012d5c _c_int00
-41011f39 _cslRsvdHandler
-41010000 _resetvectors
-41011f34 _stkchk_called
-410125c3 _system_post_cinit
-4101276b _system_pre_init
-4101243c abort
-41010734 argArray
-ffffffff binit
-41012080 dataAbortExptnHandler
-410120f8 fiqExptnHandler
-41010f34 fxnArray
-41012a88 gCslR5MpuCfg
-41010104 gExptnHandlers
-41010100 gVimBaseAddr
-41010134 intrMap
-41010334 intrPri
-41011734 intrSrcType
-41012170 irqExptnHandler
-41011f3c loop_enable
-41012429 main
-41011f40 main_func_sp
-41011f80 masterIsr
-410121e8 prefetchAbortExptnHandler
-4101233c swIntrExptnHandler
-41012260 undefInstructionExptnHandler
-
-
-GLOBAL SYMBOLS: SORTED BY Symbol Address
-
-address name
-------- ----
-00000100 __ABORT_STACK_SIZE
-00000100 __FIQ_STACK_SIZE
-00000100 __IRQ_STACK_SIZE
-00000100 __SVC_STACK_SIZE
-00000100 __UND_STACK_SIZE
-00002000 __STACK_SIZE
-41010000 __TI_static_base__
-41010000 _resetvectors
-41010100 __start___llvm_prf_cnts
-41010100 __stop___llvm_prf_cnts
-41010100 gVimBaseAddr
-41010104 gExptnHandlers
-41010134 intrMap
-41010334 intrPri
-41010734 argArray
-41010f34 fxnArray
-41011734 intrSrcType
-41011f34 _stkchk_called
-41011f39 _cslRsvdHandler
-41011f3c loop_enable
-41011f40 main_func_sp
-41011f80 masterIsr
-41012080 dataAbortExptnHandler
-410120f8 fiqExptnHandler
-41012170 irqExptnHandler
-410121e8 prefetchAbortExptnHandler
-41012260 undefInstructionExptnHandler
-410122d4 __TI_auto_init_nobinit_nopinit
-4101233c swIntrExptnHandler
-41012389 CSL_vimGetActivePendingIntr
-410123b5 CSL_vimClrIntrPending
-410123e0 _args_main
-4101240d CSL_vimAckIntr
-41012429 main
-4101243c C$$EXIT
-4101243c abort
-41012449 CSL_armR5StartupCacheEnableAllCache
-41012459 CSL_armR5StartupCacheEnableForceWrThru
-41012471 CSL_armR5StartupCacheEnableICache
-41012499 CSL_armR5StartupCacheEnableDCache
-410124c1 CSL_armR5StartupCacheInvalidateAllIcache
-410124d7 CSL_armR5StartupCacheInvalidateAllDcache
-410124ed CSL_armR5StartupCacheInvalidateAllCache
-410124fd CSL_armR5StartupMpuEnable
-4101251d CSL_armR5StartupMpuCfgRegion
-41012537 CSL_armR5StartupReadMpidrReg
-41012541 CSL_armR5StartupFpuEnable
-41012561 CSL_armR5StartupIntrEnableVic
-4101257d CSL_armR5StartupIntrEnableFiq
-41012595 CSL_armR5StartupIntrEnableIrq
-410125ad CSL_armR5SetDLFOBit
-410125c3 _system_post_cinit
-410125c5 CSL_armR5MPUCfg
-41012675 __mpu_init
-410126dd CSL_startupVimSetIntrEnable
-41012725 CSL_startupVimClrIntrPending
-41012751 CSL_armR5StartupGetCpuID
-4101276b _system_pre_init
-41012a88 gCslR5MpuCfg
-41012d5c _c_int00
-41012e35 HF
-41015b00 __UND_STACK_START
-41015c00 __SVC_STACK_START
-41015c00 __UND_STACK_END
-41015d00 __IRQ_STACK_START
-41015d00 __SVC_STACK_END
-41015e00 __FIQ_STACK_START
-41015e00 __IRQ_STACK_END
-41015f00 __ABORT_STACK_START
-41015f00 __FIQ_STACK_END
-41016000 __ABORT_STACK_END
-41016000 __stack
-41018000 __STACK_END
-a0100000 __RESOURCE_TABLE
-ffffffff __TI_pprof_out_hndl
-ffffffff __TI_prof_data_size
-ffffffff __TI_prof_data_start
-ffffffff __binit__
-ffffffff __c_args__
-ffffffff binit
-UNDEFED __TI_CINIT_Base
-UNDEFED __TI_CINIT_Limit
-UNDEFED __TI_Handler_Table_Base
-UNDEFED __TI_Handler_Table_Limit
-
-[84 symbols]
diff --git a/packages/ti/build/am64x/sbl_mcux_0_dummy_app.rprc b/packages/ti/build/am64x/sbl_mcux_0_dummy_app.rprc
deleted file mode 100644 (file)
index 1df14d8..0000000
Binary files a/packages/ti/build/am64x/sbl_mcux_0_dummy_app.rprc and /dev/null differ
index 1df14d8..0000000
Binary files a/packages/ti/build/am64x/sbl_mcux_0_dummy_app.rprc and /dev/null differ
diff --git a/packages/ti/build/am64x/sysbios_a53.cfg b/packages/ti/build/am64x/sysbios_a53.cfg
+++ /dev/null
@@ -1,175 +0,0 @@
-
-/* =============================================================================
- * Copyright (c) Texas Instruments Incorporated 2019
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the
- * distribution.
- *
- * Neither the name of Texas Instruments Incorporated nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-var Defaults = xdc.useModule('xdc.runtime.Defaults');
-var Diags = xdc.useModule('xdc.runtime.Diags');
-var Error = xdc.useModule('xdc.runtime.Error');
-var Log = xdc.useModule('xdc.runtime.Log');
-var LoggerBuf = xdc.useModule('xdc.runtime.LoggerBuf');
-var Main = xdc.useModule('xdc.runtime.Main');
-var Memory = xdc.useModule('xdc.runtime.Memory');
-var System = xdc.useModule('xdc.runtime.System');
-var Text = xdc.useModule('xdc.runtime.Text');
-var Clock = xdc.useModule('ti.sysbios.knl.Clock');
-var Task = xdc.useModule('ti.sysbios.knl.Task');
-var Semaphore = xdc.useModule('ti.sysbios.knl.Semaphore');
-var HeapBuf = xdc.useModule('ti.sysbios.heaps.HeapBuf');
-var GateSwi = xdc.useModule('ti.sysbios.gates.GateSwi');
-var Event = xdc.useModule('ti.sysbios.knl.Event');
-var GateMutexPri = xdc.useModule('ti.sysbios.gates.GateMutexPri');
-
-var BIOS = xdc.useModule('ti.sysbios.BIOS');
-var Hwi = xdc.useModule('ti.sysbios.hal.Hwi');
-var HeapMem = xdc.useModule('ti.sysbios.heaps.HeapMem');
-var SysMin = xdc.useModule('xdc.runtime.SysMin');
-
-var Cache = xdc.module("ti.sysbios.hal.Cache");
-Cache.CacheProxy = xdc.useModule("ti.sysbios.family.arm.v8a.Cache");
-
-var Mmu = xdc.useModule('ti.sysbios.family.arm.v8a.Mmu');
-Mmu.initFunc = "&InitMmu";
-Mmu.tableArrayLen = 24;
-
-/*
- * Direct CIO to UART
- */
-/* System.SupportProxy = SysUart; */
-System.SupportProxy = SysMin;
-
-System.extendedFormats += "%f";
-/*
- * Program.argSize sets the size of the .args section.
- * The examples don't use command line args so argSize is set to 0.
- */
-Program.argSize = 0x0;
-
-
-/* System stack size (used by ISRs and Swis) */
-Program.stack = 0x4000;
-
-Task.defaultStackSize = 0x4000;
-/*
- * Uncomment this line to globally disable Asserts.
- * All modules inherit the default from the 'Defaults' module. You
- * can override these defaults on a per-module basis using Module.common$.
- * Disabling Asserts will save code space and improve runtime performance.
-Defaults.common$.diags_ASSERT = Diags.ALWAYS_OFF;
- */
-
-/*
- * Uncomment this line to keep module names from being loaded on the target.
- * The module name strings are placed in the .const section. Setting this
- * parameter to false will save space in the .const section. Error and
- * Assert messages will contain an "unknown module" prefix instead
- * of the actual module name.
-Defaults.common$.namedModule = false;
- */
-
-/* Create default heap and hook it into Memory */
-var heapMemParams = new HeapMem.Params;
-heapMemParams.size = 16384*5;
-var heap0 = HeapMem.create(heapMemParams);
-
-Memory.defaultHeapInstance = heap0;
-
-/*
- * Minimize exit handler array in System. The System module includes
- * an array of functions that are registered with System_atexit() to be
- * called by System_exit().
- */
-System.maxAtexitHandlers = 4;
-
-/*
- * Uncomment this line to disable the Error print function.
- * We lose error information when this is disabled since the errors are
- * not printed. Disabling the raiseHook will save some code space if
- * your app is not using System_printf() since the Error_print() function
- * calls System_printf().
-Error.raiseHook = null;
- */
-
-/*
- * Uncomment this line to keep Error, Assert, and Log strings from being
- * loaded on the target. These strings are placed in the .const section.
- * Setting this parameter to false will save space in the .const section.
- * Error, Assert and Log message will print raw ids and args instead of
- * a formatted message.
-Text.isLoaded = false;
- */
-
-/*
- * Uncomment this line to disable the output of characters by SysMin
- * when the program exits. SysMin writes characters to a circular buffer.
- * This buffer can be viewed using the SysMin Output view in ROV.
-SysMin.flushAtExit = false;
- */
-
-/*
- * Create and install logger for the whole system
- */
-var loggerBufParams = new LoggerBuf.Params();
-loggerBufParams.numEntries = 32;
-var logger0 = LoggerBuf.create(loggerBufParams);
-Defaults.common$.logger = logger0;
-Main.common$.diags_INFO = Diags.ALWAYS_ON;
-
-BIOS.libType = BIOS.LibType_Custom;
-BIOS.cpuFreq.lo = 1000000000;
-BIOS.cpuFreq.hi = 0;
-
-var Timer = xdc.useModule('ti.sysbios.family.arm.v8a.Timer');
-Timer.intFreq.lo = 250000000;
-Timer.intFreq.hi = 0;
-
-var DMTimer = xdc.useModule('ti.sysbios.timers.dmtimer.Timer');
-DMTimer.checkFrequency = false;
-for (var i=0; i < DMTimer.numTimerDevices; i++) {
- DMTimer.intFreqs[i].lo = 19200000;
- DMTimer.intFreqs[i].hi = 0;
-}
-
-var Load = xdc.useModule('ti.sysbios.utils.Load');
-
-/* load calculation related settings */
-Load.swiEnabled = true;
-Load.hwiEnabled = true;
-Load.taskEnabled = true;
-Load.updateInIdle = false;
-
-/* Check if application needs to update with custom configuration options */
-/* Caution: This should be at the end of this file after all other common cfg */
-var cfgUpdate = java.lang.System.getenv("XDC_CFG_UPDATE");
-if ((cfgUpdate != '')&&(cfgUpdate != null))
-{
- xdc.print("Loading configuration update " + cfgUpdate);
- xdc.loadCapsule(cfgUpdate);
-}
diff --git a/packages/ti/build/am64x/sysbios_r5f.cfg b/packages/ti/build/am64x/sysbios_r5f.cfg
+++ /dev/null
@@ -1,217 +0,0 @@
-/* =============================================================================
- * Copyright (c) Texas Instruments Incorporated 2019
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the
- * distribution.
- *
- * Neither the name of Texas Instruments Incorporated nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-var Defaults = xdc.useModule('xdc.runtime.Defaults');
-var Diags = xdc.useModule('xdc.runtime.Diags');
-var Error = xdc.useModule('xdc.runtime.Error');
-var Log = xdc.useModule('xdc.runtime.Log');
-var LoggerBuf = xdc.useModule('xdc.runtime.LoggerBuf');
-var Main = xdc.useModule('xdc.runtime.Main');
-var Memory = xdc.useModule('xdc.runtime.Memory')
-var System = xdc.useModule('xdc.runtime.System');
-var Text = xdc.useModule('xdc.runtime.Text');
-var Clock = xdc.useModule('ti.sysbios.knl.Clock');
-var Task = xdc.useModule('ti.sysbios.knl.Task');
-var Semaphore = xdc.useModule('ti.sysbios.knl.Semaphore');
-var HeapBuf = xdc.useModule('ti.sysbios.heaps.HeapBuf');
-var GateSwi = xdc.useModule('ti.sysbios.gates.GateSwi');
-var Event = xdc.useModule('ti.sysbios.knl.Event');
-var GateMutexPri = xdc.useModule('ti.sysbios.gates.GateMutexPri');
-
-var BIOS = xdc.useModule('ti.sysbios.BIOS');
-var Hwi = xdc.useModule('ti.sysbios.family.arm.v7r.keystone3.Hwi');
-var Core = xdc.useModule('ti.sysbios.family.arm.v7r.keystone3.Core');
-var HeapMem = xdc.useModule('ti.sysbios.heaps.HeapMem');
-var SysMin = xdc.useModule('xdc.runtime.SysMin');
-
-/* System stack size (used by ISRs and Swis) */
-Program.stack = 0x2000;
-
-/* Place vector table in separate section - by default this goes to 0x0 which
- * is reserved by SBL */
-Program.sectMap[".vecs"] = "RESET_VECTORS";
-
-var Task = xdc.useModule('ti.sysbios.knl.Task');
-Task.defaultStackSize = 0x4000;
-Task.common$.namedInstance = true;
-Task.common$.namedModule = true;
-
-/* Enable cache */
-var Cache = xdc.useModule('ti.sysbios.family.arm.v7r.Cache');
-Cache.enableCache = true;
-
-/*
- * Direct CIO to UART
- */
-/* System.SupportProxy = SysUart; */
-System.SupportProxy = SysMin;
-System.extendedFormats += "%f";
-/*
- * Program.argSize sets the size of the .args section.
- * The examples don't use command line args so argSize is set to 0.
- */
-Program.argSize = 0x0;
-
-/*
- * Uncomment this line to globally disable Asserts.
- * All modules inherit the default from the 'Defaults' module. You
- * can override these defaults on a per-module basis using Module.common$.
- * Disabling Asserts will save code space and improve runtime performance.
-Defaults.common$.diags_ASSERT = Diags.ALWAYS_OFF;
- */
-
-/*
- * Uncomment this line to keep module names from being loaded on the target.
- * The module name strings are placed in the .const section. Setting this
- * parameter to false will save space in the .const section. Error and
- * Assert messages will contain an "unknown module" prefix instead
- * of the actual module name.
-Defaults.common$.namedModule = false;
- */
-
-/* Create default heap and hook it into Memory */
-var heapMemParams = new HeapMem.Params;
-heapMemParams.size = 16384*4;
-var heap0 = HeapMem.create(heapMemParams);
-
-Memory.defaultHeapInstance = heap0;
-
-/*
- * Minimize exit handler array in System. The System module includes
- * an array of functions that are registered with System_atexit() to be
- * called by System_exit().
- */
-System.maxAtexitHandlers = 4;
-
-/*
- * Uncomment this line to disable the Error print function.
- * We lose error information when this is disabled since the errors are
- * not printed. Disabling the raiseHook will save some code space if
- * your app is not using System_printf() since the Error_print() function
- * calls System_printf().
-Error.raiseHook = null;
- */
-
-/*
- * Uncomment this line to keep Error, Assert, and Log strings from being
- * loaded on the target. These strings are placed in the .const section.
- * Setting this parameter to false will save space in the .const section.
- * Error, Assert and Log message will print raw ids and args instead of
- * a formatted message.
-Text.isLoaded = false;
- */
-
-/*
- * Uncomment this line to disable the output of characters by SysMin
- * when the program exits. SysMin writes characters to a circular buffer.
- * This buffer can be viewed using the SysMin Output view in ROV.
-SysMin.flushAtExit = false;
- */
-
-/*
- * Create and install logger for the whole system
- */
-var loggerBufParams = new LoggerBuf.Params();
-loggerBufParams.numEntries = 32;
-var logger0 = LoggerBuf.create(loggerBufParams);
-Defaults.common$.logger = logger0;
-Main.common$.diags_INFO = Diags.ALWAYS_ON;
-
-BIOS.libType = BIOS.LibType_Custom;
-BIOS.cpuFreq.lo = 800000000;
-BIOS.cpuFreq.hi = 0;
-
-var coreId = java.lang.System.getenv("CORE");
-
-var DMTimer = xdc.useModule('ti.sysbios.timers.dmtimer.Timer');
-DMTimer.checkFrequency = false;
-for (var i=0; i < DMTimer.numTimerDevices; i++) {
- DMTimer.intFreqs[i].lo = 19200000;
- DMTimer.intFreqs[i].hi = 0;
-}
-
-if(coreId=="mcu1_0")
-{
- Core.id = 0;
- /* DM timer cfg */
- Clock.timerId = 0;
-}
-if(coreId=="mcu1_1")
-{
- Core.id = 1;
- /* DM timer cfg */
- Clock.timerId = 1;
-}
-if(coreId=="mcu2_0")
-{
- Core.id = 0;
- Clock.timerId = 2;
-}
-if(coreId=="mcu2_1")
-{
- Core.id = 1;
- Clock.timerId = 3;
-}
-/* Sysbios supports workaround for Silicon issue https://jira.itg.ti.com/browse/K3_OPEN_SI-148
- * Details of silicon issue : https://confluence.itg.ti.com/display/PROCIPDEV/%2310+The+same+interrupt+cannot+be+nested+back-2-back+within+another+interrupt
- * Sysbios Requirement Details: https://jira.itg.ti.com/browse/SYSBIOS-1419
- * Workaround requires use of a resevred dummyIRQ.
- * Using DummyIRQ#179 as per cslr_intr_r5fss0.h it is a reserved interrupt not connected to any
- * peripheral interrupt sources
- */
-Hwi.dummyIRQ = 179;
-
-var Reset = xdc.useModule("xdc.runtime.Reset");
-Reset.fxns[Reset.fxns.length++] = "&utilsCopyVecs2ATcm";
-
-/*
- * Initialize MPU and enable it
- *
- * Note: MPU must be enabled and properly configured for caching to work.
- */
-xdc.loadCapsule("r5_mpu.xs");
-
-var Load = xdc.useModule('ti.sysbios.utils.Load');
-
-/* load calculation related settings */
-Load.swiEnabled = true;
-Load.hwiEnabled = true;
-Load.taskEnabled = true;
-Load.updateInIdle = false;
-
-/* Check if application needs to update with custom configuration options */
-/* Caution: This should be at the end of this file after all other common cfg */
-var cfgUpdate = java.lang.System.getenv("XDC_CFG_UPDATE")
-if ((cfgUpdate != '')&&(cfgUpdate != null))
-{
- xdc.print("Loading configuration update " + cfgUpdate);
- xdc.loadCapsule(cfgUpdate);
-}
diff --git a/packages/ti/build/am64x/sysbios_smp_a53.cfg b/packages/ti/build/am64x/sysbios_smp_a53.cfg
+++ /dev/null
@@ -1,185 +0,0 @@
-
-/* =============================================================================
- * Copyright (c) Texas Instruments Incorporated 2020
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the
- * distribution.
- *
- * Neither the name of Texas Instruments Incorporated nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-var Defaults = xdc.useModule('xdc.runtime.Defaults');
-var Diags = xdc.useModule('xdc.runtime.Diags');
-var Error = xdc.useModule('xdc.runtime.Error');
-var Log = xdc.useModule('xdc.runtime.Log');
-var LoggerBuf = xdc.useModule('ti.sysbios.smp.LoggerBuf');
-var Main = xdc.useModule('xdc.runtime.Main');
-var Memory = xdc.useModule('xdc.runtime.Memory');
-var System = xdc.useModule('xdc.runtime.System');
-var Text = xdc.useModule('xdc.runtime.Text');
-var Clock = xdc.useModule('ti.sysbios.knl.Clock');
-var Task = xdc.useModule('ti.sysbios.knl.Task');
-var Semaphore = xdc.useModule('ti.sysbios.knl.Semaphore');
-var HeapBuf = xdc.useModule('ti.sysbios.heaps.HeapBuf');
-var GateSwi = xdc.useModule('ti.sysbios.gates.GateSwi');
-var Event = xdc.useModule('ti.sysbios.knl.Event');
-var GateMutexPri = xdc.useModule('ti.sysbios.gates.GateMutexPri');
-
-var BIOS = xdc.useModule('ti.sysbios.BIOS');
-var Hwi = xdc.useModule('ti.sysbios.hal.Hwi');
-var HeapMem = xdc.useModule('ti.sysbios.heaps.HeapMem');
-var SysMin = xdc.useModule('ti.sysbios.smp.SysMin');
-var Core = xdc.useModule('ti.sysbios.family.arm.v8a.smp.Core');
-
-var Mmu = xdc.useModule('ti.sysbios.family.arm.v8a.Mmu');
-Mmu.initFunc = "&InitMmu";
-Mmu.tableArrayLen = 24;
-
-/*Enabling BIOS SMP mode */
-BIOS.smpEnabled = true;
-
-/* Enable cache */
-var Cache = xdc.module("ti.sysbios.hal.Cache");
-
-/*
- * Direct CIO to UART
- */
-/* System.SupportProxy = SysUart; */
-System.SupportProxy = SysMin;
-
-System.extendedFormats += "%f";
-/*
- * Program.argSize sets the size of the .args section.
- * The examples don't use command line args so argSize is set to 0.
- */
-Program.argSize = 0x0;
-
-
-/* System stack size (used by ISRs and Swis) */
-Program.stack = 0x4000;
-
-Task.defaultStackSize = 0x4000;
-
-/*
- * Uncomment this line to globally disable Asserts.
- * All modules inherit the default from the 'Defaults' module. You
- * can override these defaults on a per-module basis using Module.common$.
- * Disabling Asserts will save code space and improve runtime performance.
-Defaults.common$.diags_ASSERT = Diags.ALWAYS_OFF;
- */
-
-/*
- * Uncomment this line to keep module names from being loaded on the target.
- * The module name strings are placed in the .const section. Setting this
- * parameter to false will save space in the .const section. Error and
- * Assert messages will contain an "unknown module" prefix instead
- * of the actual module name.
-Defaults.common$.namedModule = false;
- */
-
-/* Create default heap and hook it into Memory */
-var heapMemParams = new HeapMem.Params;
-heapMemParams.size = 16384*18;
-var heap0 = HeapMem.create(heapMemParams);
-
-Memory.defaultHeapInstance = heap0;
-
-/*
- * Minimize exit handler array in System. The System module includes
- * an array of functions that are registered with System_atexit() to be
- * called by System_exit().
- */
-System.maxAtexitHandlers = 4;
-
-/*
- * Uncomment this line to disable the Error print function.
- * We lose error information when this is disabled since the errors are
- * not printed. Disabling the raiseHook will save some code space if
- * your app is not using System_printf() since the Error_print() function
- * calls System_printf().
-Error.raiseHook = null;
- */
-
-/*
- * Uncomment this line to keep Error, Assert, and Log strings from being
- * loaded on the target. These strings are placed in the .const section.
- * Setting this parameter to false will save space in the .const section.
- * Error, Assert and Log message will print raw ids and args instead of
- * a formatted message.
-Text.isLoaded = false;
- */
-
-/*
- * Uncomment this line to disable the output of characters by SysMin
- * when the program exits. SysMin writes characters to a circular buffer.
- * This buffer can be viewed using the SysMin Output view in ROV.
-SysMin.flushAtExit = false;
- */
-
-/*
- * Create and install logger for the whole system
- */
-var loggerBufParams = new LoggerBuf.Params();
-loggerBufParams.numEntries = 32;
-var logger0 = LoggerBuf.create(loggerBufParams);
-Defaults.common$.logger = logger0;
-Main.common$.diags_INFO = Diags.ALWAYS_ON;
-
-BIOS.libType = BIOS.LibType_Custom;
-BIOS.cpuFreq.lo = 2000000000;
-BIOS.cpuFreq.hi = 0;
-
-/* System stack size (used by ISRs and Swis) */
-Program.stack = 0x10000;
-
-Task.defaultStackSize = 0x4000;
-
-var Timer = xdc.useModule('ti.sysbios.family.arm.v8a.Timer');
-Timer.intFreq.lo = 250000000;
-Timer.intFreq.hi = 0;
-
-var DMTimer = xdc.useModule('ti.sysbios.timers.dmtimer.Timer');
-DMTimer.checkFrequency = false;
-for (var i=0; i < DMTimer.numTimerDevices; i++) {
- DMTimer.intFreqs[i].lo = 19200000;
- DMTimer.intFreqs[i].hi = 0;
-}
-
-var Load = xdc.useModule('ti.sysbios.utils.Load');
-
-/* load calculation related settings */
-Load.swiEnabled = true;
-Load.hwiEnabled = true;
-Load.taskEnabled = true;
-Load.updateInIdle = false;
-
-/* Check if application needs to update with custom configuration options */
-/* Caution: This should be at the end of this file after all other common cfg */
-var cfgUpdate = java.lang.System.getenv("XDC_CFG_UPDATE");
-if ((cfgUpdate != '')&&(cfgUpdate != null))
-{
- xdc.print("Loading configuration update " + cfgUpdate);
- xdc.loadCapsule(cfgUpdate);
-}
diff --git a/packages/ti/build/am65xx/config_am65xx_a53.bld b/packages/ti/build/am65xx/config_am65xx_a53.bld
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
-* Copyright (c) 2017, Texas Instruments Incorporated
-* All rights reserved.
-*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions
-* are met:
-*
-* * Redistributions of source code must retain the above copyright
-* notice, this list of conditions and the following disclaimer.
-*
-* * Redistributions in binary form must reproduce the above copyright
-* notice, this list of conditions and the following disclaimer in the
-* documentation and/or other materials provided with the distribution.
-*
-* * Neither the name of Texas Instruments Incorporated nor the names of
-* its contributors may be used to endorse or promote products derived
-* from this software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
-* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
-* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
-* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
-
-/*
- * ======== config_am65xx_a53.bld ========
- * Common build configuration script for BIOS
- */
-/* load the required modules for the configuration */
-var A53F = xdc.useModule('gnu.targets.arm.A53F');
-/* A53F compiler directory path */
-A53F.rootDir = java.lang.System.getenv("CGTOOLS_A53");
diff --git a/packages/ti/build/am65xx/config_am65xx_r5f.bld b/packages/ti/build/am65xx/config_am65xx_r5f.bld
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
-* Copyright (c) 2017, Texas Instruments Incorporated
-* All rights reserved.
-*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions
-* are met:
-*
-* * Redistributions of source code must retain the above copyright
-* notice, this list of conditions and the following disclaimer.
-*
-* * Redistributions in binary form must reproduce the above copyright
-* notice, this list of conditions and the following disclaimer in the
-* documentation and/or other materials provided with the distribution.
-*
-* * Neither the name of Texas Instruments Incorporated nor the names of
-* its contributors may be used to endorse or promote products derived
-* from this software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
-* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
-* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
-* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
-
-/*
- * ======== config_am65xx_r5.bld ========
- * Build configuration script for BSP drivers
- */
-/* load the required modules for the configuration */
-var xdc_disable_thumb_mode = java.lang.System.getenv("XDC_DISABLE_THUMB_MODE");
-if(xdc_disable_thumb_mode != '' && xdc_disable_thumb_mode != null)
-{
-/* If XDC thumb mode is disabled, use the non-thumb mode xdc target */
-var R5F = xdc.useModule('ti.targets.arm.elf.R5F');
-}
-else
-{
-var R5F = xdc.useModule('ti.targets.arm.elf.R5Ft');
-}
-
-/* R5F compiler directory path */
-R5F.rootDir = java.lang.System.getenv("CGTOOLS");
diff --git a/packages/ti/build/am65xx/linker_a53.lds b/packages/ti/build/am65xx/linker_a53.lds
+++ /dev/null
@@ -1,195 +0,0 @@
-/* File: linker_a53.lds
- * Semihosting supported gcc Linker script for AM65XX A53 for QT
- * Purpose: single core A53 C app
-*/
-__STACK_SIZE = 0x10000;
-__TI_STACK_SIZE = __STACK_SIZE;
-
-MEMORY
-{
- MCU_RESVD : ORIGIN = 0x000041C00000, LENGTH = 0x00060000 /* MCUSS-OCMC RAM RESERVED FOR MCUSS & SOC Boot - 384KB */
- OCMCRAM : ORIGIN = 0x000041C60000, LENGTH = 0x00020000 /* MCUSS-OCMC RAM - 128KB */
- BOOTVECTOR : ORIGIN = 0x000070000100, LENGTH = 0x00001000 - 0x100 /* MSMC RAM INIT CODE (4 KB) */
- MSMC_SRAM : ORIGIN = 0x000070001000, LENGTH = 0xEF000 /* MSMC RAM GENERAL USE */
- MSMC_SRAM_H : ORIGIN = 0x000070100000, LENGTH = 0xE2000 /* MSMC RAM GENERAL USE - High memory */
- MSMC_DMSC : ORIGIN = 0x0000701F0000, LENGTH = 0x10000 /* Reserved for DMSC */
-
- DDR_0 (RWX) : ORIGIN = 0x80000000, LENGTH = 0x10000000
- DDR_1 (RWX) : ORIGIN = 0x90000000, LENGTH = 0x10000000
- DDR_2 (RWX) : ORIGIN = 0xA0000000, LENGTH = 0x60000000
-}
-
-REGION_ALIAS("REGION_TEXT", MSMC_SRAM);
-REGION_ALIAS("REGION_BSS", MSMC_SRAM);
-REGION_ALIAS("REGION_DATA", MSMC_SRAM);
-REGION_ALIAS("REGION_STACK", MSMC_SRAM);
-REGION_ALIAS("REGION_HEAP", MSMC_SRAM);
-REGION_ALIAS("REGION_ARM_EXIDX", MSMC_SRAM);
-REGION_ALIAS("REGION_ARM_EXTAB", MSMC_SRAM);
-REGION_ALIAS("REGION_TEXT_STARTUP", MSMC_SRAM);
-REGION_ALIAS("REGION_DATA_BUFFER", DDR_0);
-REGION_ALIAS("REGION_FAR", DDR_0);
-
-SECTIONS {
-
- .vecs : {
- *(.vecs)
- } > BOOTVECTOR AT> BOOTVECTOR
-
- .text.csl_a53_startup : {
- *(.text.csl_a53_startup)
- *(.Entry)
- } > REGION_TEXT_STARTUP AT> REGION_TEXT_STARTUP
-
- .text : {
- CREATE_OBJECT_SYMBOLS
- *(.text)
- *(.text.*)
- . = ALIGN(0x8);
- KEEP (*(.ctors))
- . = ALIGN(0x4);
- KEEP (*(.dtors))
- . = ALIGN(0x8);
- __init_array_start = .;
- KEEP (*(.init_array*))
- __init_array_end = .;
- *(.init)
- *(.fini*)
- } > REGION_TEXT AT> REGION_TEXT
-
- PROVIDE (__etext = .);
- PROVIDE (_etext = .);
- PROVIDE (etext = .);
-
- .rodata : {
- *(.rodata)
- *(.rodata*)
- } > REGION_TEXT AT> REGION_TEXT
-
- .data_buffer : ALIGN (8) {
- __data_buffer_load__ = LOADADDR (.data_buffer);
- __data_buffer_start__ = .;
- *(.data_buffer)
- *(.data_buffer*)
- . = ALIGN (8);
- __data_buffer_end__ = .;
- } > REGION_DATA_BUFFER AT> REGION_DATA_BUFFER
-
- .data : ALIGN (8) {
- __data_load__ = LOADADDR (.data);
- __data_start__ = .;
- *(.data)
- *(.data*)
- . = ALIGN (8);
- __data_end__ = .;
- } > REGION_DATA AT> REGION_TEXT
-
- .ARM.exidx : {
- __exidx_start = .;
- *(.ARM.exidx* .gnu.linkonce.armexidx.*)
- __exidx_end = .;
- } > REGION_ARM_EXIDX AT> REGION_ARM_EXIDX
-
- .ARM.extab : {
- *(.ARM.extab* .gnu.linkonce.armextab.*)
- } > REGION_ARM_EXTAB AT> REGION_ARM_EXTAB
-
- /* usb application ramdisk buffer */
- .bss:extMemCache:ramdisk (NOLOAD) : ALIGN (32) {
- } > DDR_0
-
- /* For NDK packet memory, we need to map this sections before .bss*/
- .bss:NDK_PACKETMEM (NOLOAD) : ALIGN (128) {} > DDR_0
- .bss:NDK_MMBUFFER (NOLOAD) : ALIGN (128) {} > DDR_0
-
- /* USB or any other LLD buffer for benchmarking */
- .benchmark_buffer (NOLOAD) : ALIGN (32) {
- } > DDR_0
-
- /* cal's application buffer */
- .bss:frameBuffer (NOLOAD) : ALIGN (32) {
- } > DDR_0
-
-
- .bss : {
- __bss_start__ = .;
- *(.shbss)
- *(.bss)
- *(.bss.*)
- . = ALIGN (8);
- __bss_end__ = .;
- . = ALIGN (8);
- *(COMMON)
- } > REGION_BSS AT> REGION_BSS
-
- .far : {
- __far_start__ = .;
- *(.far)
- *(.far:*)
- *(.far.*)
- . = ALIGN (8);
- __far_end__ = .;
- . = ALIGN (8);
- } > REGION_FAR AT> REGION_FAR
-
- .heap : {
- __heap_start__ = .;
- end = __heap_start__;
- _end = end;
- __end = end;
- KEEP(*(.heap))
- __heap_end__ = .;
- __HeapLimit = __heap_end__;
- } > REGION_HEAP AT> REGION_HEAP
-
- .stack (NOLOAD) : ALIGN(16) {
- _stack = .;
- __stack = .;
- KEEP(*(.stack))
- } > REGION_STACK AT> REGION_STACK
-
- __TI_STACK_BASE = __stack;
-
- /* Stabs debugging sections. */
- .stab 0 : { *(.stab) }
- .stabstr 0 : { *(.stabstr) }
- .stab.excl 0 : { *(.stab.excl) }
- .stab.exclstr 0 : { *(.stab.exclstr) }
- .stab.index 0 : { *(.stab.index) }
- .stab.indexstr 0 : { *(.stab.indexstr) }
- .comment 0 : { *(.comment) }
- /*
- * DWARF debug sections.
- * Symbols in the DWARF debugging sections are relative to the beginning
- * of the section so we begin them at 0.
- */
- /* DWARF 1 */
- .debug 0 : { *(.debug) }
- .line 0 : { *(.line) }
- /* GNU DWARF 1 extensions */
- .debug_srcinfo 0 : { *(.debug_srcinfo) }
- .debug_sfnames 0 : { *(.debug_sfnames) }
- /* DWARF 1.1 and DWARF 2 */
- .debug_aranges 0 : { *(.debug_aranges) }
- .debug_pubnames 0 : { *(.debug_pubnames) }
- /* DWARF 2 */
- .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
- .debug_abbrev 0 : { *(.debug_abbrev) }
- .debug_line 0 : { *(.debug_line .debug_line.* .debug_line_end ) }
- .debug_frame 0 : { *(.debug_frame) }
- .debug_str 0 : { *(.debug_str) }
- .debug_loc 0 : { *(.debug_loc) }
- .debug_macinfo 0 : { *(.debug_macinfo) }
- /* SGI/MIPS DWARF 2 extensions */
- .debug_weaknames 0 : { *(.debug_weaknames) }
- .debug_funcnames 0 : { *(.debug_funcnames) }
- .debug_typenames 0 : { *(.debug_typenames) }
- .debug_varnames 0 : { *(.debug_varnames) }
- /* DWARF 3 */
- .debug_pubtypes 0 : { *(.debug_pubtypes) }
- .debug_ranges 0 : { *(.debug_ranges) }
- /* DWARF Extension. */
- .debug_macro 0 : { *(.debug_macro) }
- .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }
- /DISCARD/ : { *(.note.GNU-stack) *(.gnu_debuglink) *(.gnu.lto_*) }
-}
diff --git a/packages/ti/build/am65xx/linker_r5.lds b/packages/ti/build/am65xx/linker_r5.lds
+++ /dev/null
@@ -1,130 +0,0 @@
-
-/* This is standard linker options used by examples applications and tests */
-/* Please refer user guide that came with this release for more details */
-/* on which sections could be used at load time and runtime */
-
-
-/* Linker Settings */
-/* Standard linker options */
---retain="*(.intvecs)"
---retain="*(.intc_text)"
---retain="*(.rstvectors)"
---retain="*(.irqStack)"
---retain="*(.fiqStack)"
---retain="*(.abortStack)"
---retain="*(.undStack)"
---retain="*(.svcStack)"
---fill_value=0
---stack_size=0x2000
---heap_size=0x1000
---entry_point=_resetvectors /* Default C RTS boot.asm */
-
--stack 0x2000 /* SOFTWARE STACK SIZE */
--heap 0x2000 /* HEAP AREA SIZE */
-
-/* Stack Sizes for various modes */
-__IRQ_STACK_SIZE = 0x1000;
-__FIQ_STACK_SIZE = 0x1000;
-__ABORT_STACK_SIZE = 0x1000;
-__UND_STACK_SIZE = 0x1000;
-__SVC_STACK_SIZE = 0x1000;
-
-
-
-/*----------------------------------------------------------------------------*/
-/* Memory Sections */
-MEMORY
-{
- /* Refer the user guide for details on persistence of these sections */
- /* Also, when these memories can be used by apps */
- MCU0_ATCM_NOT_USED (R) : origin=0x0 length=0x7FFF
- MCU0_BTCM_NOT_USED (R) : origin=0x41010000 length=0x7FFF
- /* Used by SBL, can be used after APPs is started */
- MCU_MSRAM_RSVD_UNUSED (R) : origin=0x41C00000 length=0x200
- MCU_MSRAM_RSVD_SBL (RWIX) : origin=0x41C00200 length=0x3DE00
-
- VECTORS (RWIX) : origin=0x41C3E000 length=0x100
- RESET_VECTORS (RWIX) : origin=0x41C3E100 length=0x1000
- OCMRAM (RWIX) : origin=0x41C3F100 length=0x40F00
-
- /* COMPUTE_CLUSTER0_MSMC_SRAM */
- MSMC3 (RWIX) : origin=0x70000000 length=0x1EFC00
- /* The origin and length is determined by board cfg, */
- /* refer user guide for details */
- MSMC3_RSVD_DMSC (RWIX) : origin=0x701F0000 length=0x1000
-
- DDR0 (RWIX) : origin=0x80000000 length=0x7FFFFFE4
-
-} /* end of MEMORY */
-
-/*----------------------------------------------------------------------------*/
-/* Section Configuration */
-
-SECTIONS
-{
- .intvecs : {} palign(8) > VECTORS
- .intc_text : {} palign(8) > VECTORS
- .rstvectors : {} palign(8) > RESET_VECTORS
- .bootCode : {} palign(8) > MSMC3
- .startupCode : {} palign(8) > MSMC3
- .startupData : {} palign(8) > MSMC3, type = NOINIT
-
-
- .text : {} palign(8) > MSMC3
- .const : {} palign(8) > MSMC3
- .rodata : {} palign(8) > MSMC3
- .cinit : {} palign(8) > MSMC3
- .pinit : {} palign(8) > MSMC3
-
- /* For NDK packet memory, we need to map this sections before .bss*/
- .bss:NDK_MMBUFFER (NOLOAD) {} ALIGN (128) > DDR0
- .bss:NDK_PACKETMEM (NOLOAD) {} ALIGN (128) > DDR0
-
- .bss : {} align(8) > MSMC3
- .far : {} align(8) > DDR0
- .data : {} palign(128)> MSMC3
- .boardcfg_data : {} palign(128) > MSMC3
- .sysmem : {} align(8) > MSMC3
-
- /* USB ram disk dev-msc example */
- .bss:extMemCache:ramdisk : {} align (32) > DDR0
-
- /* SA sections */
- .scBufs : {} align(8) > DDR0
- .saSrcBuffers : {} align(8) > DDR0
- .saDstBuffers : {} align(8) > DDR0
-
- /* LLD buffer for benchmarking */
- .benchmark_buffer (NOLOAD) {} ALIGN (8) > DDR0
-
- .stack : {} align(8) > MSMC3 (HIGH)
- .irqStack : {. = . + __IRQ_STACK_SIZE;} align(8) > MSMC3 (HIGH)
- RUN_START(__IRQ_STACK_START)
- RUN_END(__IRQ_STACK_END)
-
- .fiqStack : {. = . + __FIQ_STACK_SIZE;} align(8) > MSMC3 (HIGH)
- RUN_START(__FIQ_STACK_START)
- RUN_END(__FIQ_STACK_END)
-
- .abortStack : {. = . + __ABORT_STACK_SIZE;} align(8) > MSMC3 (HIGH)
- RUN_START(__ABORT_STACK_START)
- RUN_END(__ABORT_STACK_END)
-
- .undStack : {. = . + __UND_STACK_SIZE;} align(8) > MSMC3 (HIGH)
- RUN_START(__UND_STACK_START)
- RUN_END(__UND_STACK_END)
-
- .svcStack : {. = . + __SVC_STACK_SIZE;} align(8) > MSMC3 (HIGH)
- RUN_START(__SVC_STACK_START)
- RUN_END(__SVC_STACK_END)
-
-
- /* Additional sections settings */
-
-} /* end of SECTIONS */
-
-/*----------------------------------------------------------------------------*/
-/* Misc linker settings */
-
-
-/*-------------------------------- END ---------------------------------------*/
diff --git a/packages/ti/build/am65xx/linker_r5_freertos.lds b/packages/ti/build/am65xx/linker_r5_freertos.lds
+++ /dev/null
@@ -1,124 +0,0 @@
-/* This is standard linker options used by examples applications and tests */
-/* Please refer user guide that came with this release for more details */
-/* on which sections could be used at load time and runtime */
-
-/*=========================*/
-/* Linker Settings */
-/*=========================*/
-
---retain="*(.bootCode)"
---retain="*(.startupCode)"
---retain="*(.startupData)"
---retain="*(.irqStack)"
---retain="*(.fiqStack)"
---retain="*(.abortStack)"
---retain="*(.undStack)"
---retain="*(.svcStack)"
-
---fill_value=0
---stack_size=0x4000
---heap_size=0x8000
---entry_point=_freertosresetvectors
-
--stack 0x4000 /* SOFTWARE STACK SIZE */
--heap 0x8000 /* HEAP AREA SIZE */
-
-/*-------------------------------------------*/
-/* Stack Sizes for various modes */
-/*-------------------------------------------*/
-__IRQ_STACK_SIZE = 0x1000;
-__FIQ_STACK_SIZE = 0x0100;
-__ABORT_STACK_SIZE = 0x0100;
-__UND_STACK_SIZE = 0x0100;
-__SVC_STACK_SIZE = 0x0100;
-
-/*--------------------------------------------------------------------------*/
-/* Memory Map */
-/*--------------------------------------------------------------------------*/
-MEMORY
-{
- /*--- Refer the user guide for details on persistence of these sections ---*/
- /*------------ Also, when these memories can be used by apps --------------*/
- MCU0_ATCM_NOT_USED (R) : ORIGIN = 0x00000000 LENGTH = 0x00007FFF
- MCU0_BTCM_NOT_USED (R) : ORIGIN = 0x41010000 LENGTH = 0x00007FFF
- /*----------- Used by SBL, can be used after APPs is started --------------*/
- MCU_MSRAM_RSVD_UNUSED (R) : ORIGIN = 0x41C00000 LENGTH = 0x00000200
- MCU_MSRAM_RSVD_SBL (RWIX) : ORIGIN = 0x41C00200 LENGTH = 0x0003DE00
-
- VECTORS (RWIX) : ORIGIN = 0x41C3E000 LENGTH = 0x00000100
- RESET_VECTORS (RWIX) : ORIGIN = 0x41C3E100 LENGTH = 0x00001000
- OCMC_RAM (RWIX) : ORIGIN = 0x41C3F100 LENGTH = 0x00040F00
-
- /*====================== COMPUTE_CLUSTER0_MSMC_SRAM =======================*/
- MSMC3 (RWIX) : ORIGIN = 0x70000000 LENGTH = 0x001EFC00
- /*---------- The ORIGIN and LENGTH is determined by board cfg, ----------*/
- /*------------------ refer user guide for details -------------------------*/
- MSMC3_RSVD_DMSC (RWIX) : ORIGIN = 0x701F0000 LENGTH = 0x00001000
-
- /*========================== AM65xx DDR LOCATION ==========================*/
- DDR0 (RWIX) : ORIGIN = 0x80000000 LENGTH = 0x7FFFFFE4
-
-}
-
-/*--------------------------------------------------------------*/
-/* Section Configuration */
-/*--------------------------------------------------------------*/
-SECTIONS
-{
- .intc_text : {} palign(8) > VECTORS
- .freertosrstvectors : {} palign(8) > RESET_VECTORS
- .bootCode : {} palign(8) > OCMC_RAM
- .startupCode : {} palign(8) > OCMC_RAM
- .startupData : {} palign(8) > OCMC_RAM, type = NOINIT
-
- .text : {} palign(8) > DDR0
- GROUP {
- .text.hwi : palign(8)
- .text.cache : palign(8)
- .text.mpu : palign(8)
- .text.boot : palign(8)
- } > DDR0
- .const : {} palign(8) > DDR0
- .rodata : {} palign(8) > DDR0
- .cinit : {} palign(8) > DDR0
- .pinit : {} palign(8) > DDR0
-
- .bss : {} align(8) > DDR0
- .far : {} align(8) > DDR0
- .data : {} palign(128)> DDR0
- .boardcfg_data : {} palign(128)> DDR0
- .sysmem : {} align(8) > DDR0
-
- /*------- USB ram disk dev-msc example ------*/
- .bss:extMemCache:ramdisk : {} align (32) > DDR0
-
- /*--------------- SA sections ---------------*/
- .scBufs : {} align(8) > DDR0
- .saSrcBuffers : {} align(8) > DDR0
- .saDstBuffers : {} align(8) > DDR0
-
- /*------- LLD buffer for benchmarking -------*/
- .benchmark_buffer (NOLOAD) {} ALIGN (8) > DDR0
-
- .stack : {} align(8) > DDR0 (HIGH)
-
- .irqStack : {. = . + __IRQ_STACK_SIZE;} align(8) > DDR0 (HIGH)
- RUN_START(__IRQ_STACK_START)
- RUN_END(__IRQ_STACK_END)
-
- .fiqStack : {. = . + __FIQ_STACK_SIZE;} align(8) > DDR0 (HIGH)
- RUN_START(__FIQ_STACK_START)
- RUN_END(__FIQ_STACK_END)
-
- .abortStack : {. = . + __ABORT_STACK_SIZE;} align(8) > DDR0 (HIGH)
- RUN_START(__ABORT_STACK_START)
- RUN_END(__ABORT_STACK_END)
-
- .undStack : {. = . + __UND_STACK_SIZE;} align(8) > DDR0 (HIGH)
- RUN_START(__UND_STACK_START)
- RUN_END(__UND_STACK_END)
-
- .svcStack : {. = . + __SVC_STACK_SIZE;} align(8) > DDR0 (HIGH)
- RUN_START(__SVC_STACK_START)
- RUN_END(__SVC_STACK_END)
-}
diff --git a/packages/ti/build/am65xx/linker_r5_sysbios.lds b/packages/ti/build/am65xx/linker_r5_sysbios.lds
+++ /dev/null
@@ -1,92 +0,0 @@
-
-/* This is standard linker options used by examples applications and tests */
-/* Please refer user guide that came with this release for more details */
-/* on which sections could be used at load time and runtime */
-
---fill_value=0
-/* Retain entry point */
--e __VECS_ENTRY_POINT
-
-/*----------------------------------------------------------------------------*/
-/* Memory Sections */
-MEMORY
-{
- /* Refer the user guide for details on persistence of these sections */
- /* Also, when these memories can be used by apps */
- MCU0_ATCM_NOT_USED (R) : origin=0x0 length=0x7FFF
- MCU0_BTCM_NOT_USED (R) : origin=0x41010000 length=0x7FFF
- /* Used by SBL, can be used after APPs is started */
- MCU_MSRAM_RSVD_UNUSED (R) : origin=0x41C00000 length=0x200
- MCU_MSRAM_RSVD_SBL (RWIX) : origin=0x41C00200 length=0x3DE00
-
- VECTORS (RWIX) : origin=0x41C3E000 length=0x100
- RESET_VECTORS (RWIX) : origin=0x41C3E100 length=0x1000
- OCMRAM (RWIX) : origin=0x41C3F100 length=0x40F00
-
- /* COMPUTE_CLUSTER0_MSMC_SRAM */
- MSMC3 (RWIX) : origin=0x70000000 length=0x1EFC00
- /* The origin and length is determined by board cfg, */
- /* refer user guide for details */
- MSMC3_RSVD_DMSC (RWIX) : origin=0x701F0000 length=0x1000
- DDR0 (RWIX) : origin=0x80000000 length=0x7FFFFFE4
-
-} /* end of MEMORY */
-
-/*----------------------------------------------------------------------------*/
-/* Section Configuration */
-
-SECTIONS
-{
- /* Place sysbios entry point - starts */
- .vecs : { *(.vecs) } palign(8) > VECTORS
- .vecs : { __VECS_ENTRY_POINT = .; } > VECTORS
-
- xdc.meta (COPY): { *(xdc.meta) } > OCMRAM
- .init_text : {
- boot.*(.text)
- *(.text:ti_sysbios_family_arm_MPU_*)
- *(.text:ti_sysbios_family_arm_v7r_Cache_*)
- } palign(8) > OCMRAM
-
- .text:xdc_runtime_Startup_reset__I: {} palign(8) > OCMRAM
-
- .bootCode : {} palign(8) > OCMRAM
- .startupCode : {} palign(8) > OCMRAM
- .startupData : {} palign(8) > OCMRAM, type = NOINIT
- .utilsCopyVecsToAtcm : {} palign(8) > OCMRAM
-
- /* Place sysbios entry point - ends */
-
- .text : {} palign(8) > MSMC3
- .const : {} palign(8) > MSMC3
- .cinit : {} palign(8) > MSMC3
- .pinit : {} palign(8) > MSMC3
-
- /* For NDK packet memory, we need to map this sections before .bss*/
- .bss:NDK_MMBUFFER (NOLOAD) {} ALIGN (128) > DDR0
- .bss:NDK_PACKETMEM (NOLOAD) {} ALIGN (128) > DDR0
-
- .bss : {} align(8) > MSMC3
- .far : {} align(8) > DDR0
- .data : {} palign(128)> MSMC3
- .boardcfg_data : {} palign(128) > MSMC3
- .sysmem : {} align(8) > MSMC3
- .stack : {} align(8) > MSMC3 (HIGH)
-
- /* SA sections */
- .scBufs : {} align(8) > DDR0
- .saSrcBuffers : {} align(8) > DDR0
- .saDstBuffers : {} align(8) > DDR0
-
- /* LLD buffer for benchmarking */
- .benchmark_buffer (NOLOAD) {} ALIGN (8) > DDR0
-
- /* Additional sections settings */
-
-} /* end of SECTIONS */
-
-/*----------------------------------------------------------------------------*/
-/* Misc linker settings */
-
-
-/*-------------------------------- END ---------------------------------------*/
diff --git a/packages/ti/build/am65xx/r5_mpu.xs b/packages/ti/build/am65xx/r5_mpu.xs
+++ /dev/null
@@ -1,135 +0,0 @@
-/*
- * Copyright (c) 2018, Texas Instruments Incorporated
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * * Neither the name of Texas Instruments Incorporated nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
- * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
- * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
- * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
- * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-/*
- * ======== event_MPU.xs ========
- * MPU Settings for AM65XX device's Cortex-R5F
- */
-
-/*
- * -------------------------------------------------------------------------------------------------------------
- * | Id | Base Address | Size | En | Cacheable | XN | AccPerm | Mask |
- * |-------------------------------------------------------------------------------------------------------------|
- * | 0 | 0x00000000 | 4GB | T | Strongly Ordered, Shareable | T | RW at PL 1 | 0x0 |
- * |----|--------------|------|----|-------------------------------------------|----|---------------------|------|
- * | 1 | 0x00000000 | 1K | T | Non-cacheable, Non-Shareable | F | RW at PL 1 | 0x0 |
- * |----|--------------|------|----|-------------------------------------------|----|---------------------|------|
- * | 2 | 0x41000000 | 32K | T | Non-cacheable, Non-Shareable | F | RW at PL 1 | 0x0 |
- * |----|--------------|------|----|-------------------------------------------|----|---------------------|------|
- * | 3 | 0x41010000 | 32K | T | Non-cacheable, Non-Shareable | F | RW at PL 1 | 0x0 |
- * |----|--------------|------|----|-------------------------------------------|----|---------------------|------|
- * | 4 | 0x41C00000 | 512K | T | Write-Back, Write-Allocate, Non-Shareable | F | RW at PL 1 | 0x0 |
- * -------------------------------------------------------------------------------------------------------------
- */
-
-/*
- * Note: Marking a region as shareable will cause the region to behave as outer shareable with write through
- * no write-allocate caching policy irrespective of the actual cache policy set. Therefore, only select
- * regions that are actually shared outside the R5 CPUSS must be marked as shared.
- */
-
-var MPU = xdc.useModule('ti.sysbios.family.arm.MPU');
-MPU.enableMPU = true;
-MPU.enableBackgroundRegion = true;
-
-var attrs = new MPU.RegionAttrs();
-MPU.initRegionAttrsMeta(attrs);
-
-attrs.enable = true;
-attrs.bufferable = false;
-attrs.cacheable = false;
-attrs.shareable = true;
-attrs.noExecute = true;
-attrs.accPerm = 1; /* RW at PL1 */
-attrs.tex = 0;
-attrs.subregionDisableMask = 0;
-MPU.setRegionMeta(0, 0x00000000, MPU.RegionSize_4G, attrs);
-
-attrs.enable = true;
-attrs.bufferable = false;
-attrs.cacheable = false;
-attrs.shareable = false;
-attrs.noExecute = false;
-attrs.accPerm = 1; /* RW at PL1 */
-attrs.tex = 1;
-attrs.subregionDisableMask = 0;
-MPU.setRegionMeta(1, 0x00000000, MPU.RegionSize_32K, attrs);
-
-attrs.enable = true;
-attrs.bufferable = false;
-attrs.cacheable = false;
-attrs.shareable = false;
-attrs.noExecute = false;
-attrs.accPerm = 1; /* RW at PL1 */
-attrs.tex = 1;
-attrs.subregionDisableMask = 0;
-MPU.setRegionMeta(2, 0x41000000, MPU.RegionSize_32K, attrs);
-
-attrs.enable = true;
-attrs.bufferable = false;
-attrs.cacheable = false;
-attrs.shareable = false;
-attrs.noExecute = false;
-attrs.accPerm = 1; /* RW at PL1 */
-attrs.tex = 1;
-attrs.subregionDisableMask = 0x0;
-MPU.setRegionMeta(3, 0x41010000, MPU.RegionSize_32K, attrs);
-
-attrs.enable = true;
-attrs.bufferable = true;
-attrs.cacheable = true;
-attrs.shareable = false;
-attrs.noExecute = false;
-attrs.accPerm = 1; /* RW at PL1 */
-attrs.tex = 1;
-attrs.subregionDisableMask = 0;
-MPU.setRegionMeta(4, 0x41C00000, MPU.RegionSize_512K, attrs);
-
-attrs.enable = true;
-attrs.bufferable = true;
-attrs.cacheable = true;
-attrs.shareable = false;
-attrs.noExecute = false;
-attrs.accPerm = 1; /* RW at PL1 */
-attrs.tex = 1;
-attrs.subregionDisableMask = 0;
-MPU.setRegionMeta(5, 0x70000000, MPU.RegionSize_2M, attrs);
-
-
-attrs.enable = true;
-attrs.bufferable = true;
-attrs.cacheable = true;
-attrs.shareable = false;
-attrs.noExecute = false;
-attrs.accPerm = 1; /* RW at PL1 */
-attrs.tex = 1;
-attrs.subregionDisableMask = 0;
-MPU.setRegionMeta(6, 0x80000000, MPU.RegionSize_2G, attrs);
diff --git a/packages/ti/build/am65xx/sbl_mcux_0_dummy_app.map b/packages/ti/build/am65xx/sbl_mcux_0_dummy_app.map
+++ /dev/null
@@ -1,353 +0,0 @@
-******************************************************************************
- TI ARM Linker Unix v18.12.1
-******************************************************************************
->> Linked Sat Jul 6 17:44:10 2019
-
-OUTPUT FILE NAME: </adasuser/sivaraj/k3/ti/j7presi/workarea/pdk/packages/ti/binary/udma_baremetal_memcpy_testapp/bin/j721e_evm/udma_baremetal_memcpy_testapp_mcu2_0_release.xer5f>
-ENTRY POINT SYMBOL: "_resetvectors" address: 41c00000
-
-
-MEMORY CONFIGURATION
-
- name origin length used unused attr fill
----------------------- -------- --------- -------- -------- ---- --------
- MCU0_R5F_TCMA_SBL_RSV 00000000 00000100 00000000 00000100 X
- MCU0_R5F_TCMA 00000100 00007f00 00000000 00007f00 X
- MCU0_R5F_TCMB0 41010000 00008000 00003450 00004bb0 RWIX
- MCU0_R5F1_ATCM 41400000 00008000 00000000 00008000 RWIX
- MCU0_R5F1_BTCM 41410000 00008000 00000000 00008000 RWIX
- RESET_VECTORS 41c00000 00000100 00000040 000000c0 X
- OCMRAM 41c00100 0007ef00 00000000 0007ef00 RWIX
- VECTORS 41c7f000 00001000 00000000 00001000 X
- MSMC3_ARM_FW 70000000 00040000 00000000 00040000 RWIX
- MSMC3 70040000 007b0000 00000000 007b0000 RWIX
- MSMC3_DMSC_FW 707f0000 00010000 00000000 00010000 RWIX
- DDR0 80000000 80000000 00000000 80000000 RWIX
-
-
-SEGMENT ALLOCATION MAP
-
-run origin load origin length init length attrs members
----------- ----------- ---------- ----------- ----- -------
-41010000 41010000 00001e80 00001e80 rwx
- 41010000 41010000 00001e80 00001e80 rwx .data
-41011e80 41011e80 00000cd0 00000cd0 r-x
- 41011e80 41011e80 00000598 00000598 r-x .text
- 41012418 41012418 00000420 00000420 r-x .startupCode
- 41012838 41012838 00000318 00000318 r-- .startupData
-41012b50 41012b50 00000100 00000000 rw-
- 41012b50 41012b50 00000100 00000000 rw- .sysmem
-41012c50 41012c50 00000100 00000100 r-x
- 41012c50 41012c50 00000100 00000100 r-x .bootCode
-41017900 41017900 00000500 00000000 r--
- 41017900 41017900 00000100 00000000 r-- .undStack
- 41017a00 41017a00 00000100 00000000 r-- .svcStack
- 41017b00 41017b00 00000100 00000000 r-- .irqStack
- 41017c00 41017c00 00000100 00000000 r-- .fiqStack
- 41017d00 41017d00 00000100 00000000 r-- .abortStack
-41017e00 41017e00 00000200 00000000 rw-
- 41017e00 41017e00 00000200 00000000 rw- .stack
-41c00000 41c00000 00000040 00000040 r-x
- 41c00000 41c00000 00000040 00000040 r-x .rstvectors
-
-
-SECTION ALLOCATION MAP
-
- output attributes/
-section page origin length input sections
--------- ---- ---------- ---------- ----------------
-.text 0 41011e80 00000598
- 41011e80 000000fc ti.csl.aer5f : interrupt.oer5f (.text:masterIsr)
- 41011f7c 00000094 : csl_vim.oer5f (.text:CSL_vimCfgIntr)
- 41012010 00000078 : interrupt.oer5f (.text:dataAbortExptnHandler)
- 41012088 00000078 : interrupt.oer5f (.text:fiqExptnHandler)
- 41012100 00000078 : interrupt.oer5f (.text:irqExptnHandler)
- 41012178 00000078 : interrupt.oer5f (.text:prefetchAbortExptnHandler)
- 410121f0 00000074 : interrupt.oer5f (.text:undefInstructionExptnHandler)
- 41012264 00000068 rtsv7R4_A_le_v3D16_eabi.lib : autoinit.c.obj (.text:__TI_auto_init_nobinit_nopinit:__TI_auto_init_nobinit_nopinit)
- 410122cc 0000004c ti.csl.aer5f : csl_vim.oer5f (.text:CSL_vimGetActivePendingIntr)
- 41012318 0000004c : interrupt.oer5f (.text:swIntrExptnHandler)
- 41012364 00000030 : csl_vim.oer5f (.text:CSL_vimClrIntrPending)
- 41012394 0000002c : csl_vim.oer5f (.text:CSL_vimAckIntr)
- 410123c0 00000020 main_baremetal.oer5f (.text:StartupEmulatorWaitFxn)
- 410123e0 00000020 rtsv7R4_A_le_v3D16_eabi.lib : args_main.c.obj (.text:_args_main)
- 41012400 00000010 main_baremetal.oer5f (.text:main)
- 41012410 00000008 rtsv7R4_A_le_v3D16_eabi.lib : exit.c.obj (.text:abort:abort)
-
-.startupCode
-* 0 41012418 00000420
- 41012418 000001b4 ti.csl.init.aer5f : r5_startup.oer5f (.startupCode)
- 410125cc 0000010c : startup.oer5f (.startupCode:CSL_armR5MPUCfg)
- 410126d8 00000094 : startup.oer5f (.startupCode:__mpu_init)
- 4101276c 00000058 : startup.oer5f (.startupCode:CSL_startupVimSetIntrEnable)
- 410127c4 0000003c : startup.oer5f (.startupCode:CSL_startupVimClrIntrPending)
- 41012800 00000028 : startup.oer5f (.startupCode:CSL_armR5StartupGetCpuID)
- 41012828 00000008 : startup.oer5f (.startupCode:_system_pre_init)
- 41012830 00000004 : startup.oer5f (.startupCode:_system_post_cinit)
- 41012834 00000004 --HOLE-- [fill = 00000000]
-
-.startupData
-* 0 41012838 00000318
- 41012838 00000314 ti.csl.init.aer5f : startup.oer5f (.startupData)
- 41012b4c 00000004 --HOLE-- [fill = 00000000]
-
-.bootCode
-* 0 41012c50 00000100
- 41012c50 000000fc ti.csl.init.aer5f : boot.oer5f (.bootCode)
- 41012d4c 00000004 --HOLE-- [fill = 00000000]
-
-.rstvectors
-* 0 41c00000 00000040
- 41c00000 00000040 ti.csl.init.aer5f : boot.oer5f (.rstvectors)
-
-.cinit 0 41010000 00000000 UNINITIALIZED
-
-.data 0 41010000 00001e80
- 41010000 00000e34 ti.csl.aer5f : interrupt.oer5f (.data:$O10$$)
- 41010e34 00000800 : interrupt.oer5f (.data:fxnArray)
- 41011634 00000800 : interrupt.oer5f (.data:intrSrcType)
- 41011e34 00000008 ti.csl.init.aer5f : boot.oer5f (.data)
- 41011e3c 00000004 rtsv7R4_A_le_v3D16_eabi.lib : stkdepth_vars.c.obj (.data)
- 41011e40 00000040 --HOLE-- [fill = 00000000]
-
-.sysmem 0 41012b50 00000100 UNINITIALIZED
- 41012b50 00000010 rtsv7R4_A_le_v3D16_eabi.lib : memory.c.obj (.sysmem)
- 41012b60 000000f0 --HOLE--
-
-.undStack
-* 0 41017900 00000100 UNINITIALIZED
- 41017900 00000100 --HOLE--
-
-.svcStack
-* 0 41017a00 00000100 UNINITIALIZED
- 41017a00 00000100 --HOLE--
-
-.irqStack
-* 0 41017b00 00000100 UNINITIALIZED
- 41017b00 00000100 --HOLE--
-
-.fiqStack
-* 0 41017c00 00000100 UNINITIALIZED
- 41017c00 00000100 --HOLE--
-
-.abortStack
-* 0 41017d00 00000100 UNINITIALIZED
- 41017d00 00000100 --HOLE--
-
-.stack 0 41017e00 00000200 UNINITIALIZED
- 41017e00 00000200 --HOLE--
-
-MODULE SUMMARY
-
- Module code ro data rw data
- ------ ---- ------- -------
- /adasuser/sivaraj/k3/ti/j7presi/workarea/pdk/packages/ti/binary/udma_baremetal_memcpy_testapp/obj/j721e_evm/mcu2_0/release/
- main_baremetal.oer5f 48 0 0
- +--+----------------------+------+---------+---------+
- Total: 48 0 0
-
- /adasuser/sivaraj/k3/ti/j7presi/workarea/pdk/packages/ti/csl/lib/j721e/r5f/release/ti.csl.aer5f
- interrupt.oer5f 924 0 7732
- csl_vim.oer5f 316 0 0
- +--+----------------------+------+---------+---------+
- Total: 1240 0 7732
-
- /adasuser/sivaraj/k3/ti/j7presi/workarea/pdk/packages/ti/csl/lib/j721e/r5f/release/ti.csl.init.aer5f
- startup.oer5f 616 788 0
- r5_startup.oer5f 436 0 0
- boot.oer5f 324 0 0
- +--+----------------------+------+---------+---------+
- Total: 1376 788 0
-
- /adasuser/sivaraj/k3/ti/j7presi/workarea/ti-cgt-arm_18.12.1.LTS/lib/rtsv7R4_A_le_v3D16_eabi.lib
- autoinit.c.obj 104 0 0
- args_main.c.obj 32 0 0
- exit.c.obj 8 0 0
- stkdepth_vars.c.obj 0 0 4
- +--+----------------------+------+---------+---------+
- Total: 144 0 4
-
- Heap: 0 0 256
- Stack: 0 0 512
- +--+----------------------+------+---------+---------+
- Grand Total: 2808 788 8504
-
-
-GLOBAL SYMBOLS: SORTED ALPHABETICALLY BY Name
-
-address name
-------- ----
-41012410 C$$EXIT
-410125cc CSL_armR5MPUCfg
-41012418 CSL_armR5StartupCacheEnableAllCache
-4101247c CSL_armR5StartupCacheEnableDCache
-4101242c CSL_armR5StartupCacheEnableForceWrThru
-4101244c CSL_armR5StartupCacheEnableICache
-410124dc CSL_armR5StartupCacheInvalidateAllCache
-410124c4 CSL_armR5StartupCacheInvalidateAllDcache
-410124ac CSL_armR5StartupCacheInvalidateAllIcache
-41012540 CSL_armR5StartupFpuEnable
-41012800 CSL_armR5StartupGetCpuID
-4101258c CSL_armR5StartupIntrEnableFiq
-410125ac CSL_armR5StartupIntrEnableIrq
-41012568 CSL_armR5StartupIntrEnableVic
-41012518 CSL_armR5StartupMpuCfgRegion
-410124f0 CSL_armR5StartupMpuEnable
-41012534 CSL_armR5StartupReadMpidrReg
-410127c4 CSL_startupVimClrIntrPending
-4101276c CSL_startupVimSetIntrEnable
-41012394 CSL_vimAckIntr
-41011f7c CSL_vimCfgIntr
-41012364 CSL_vimClrIntrPending
-410122cc CSL_vimGetActivePendingIntr
-41012d3c HF
-410123c0 StartupEmulatorWaitFxn
-41017e00 __ABORT_STACK_END
-00000100 __ABORT_STACK_SIZE
-41017d00 __ABORT_STACK_START
-41017d00 __FIQ_STACK_END
-00000100 __FIQ_STACK_SIZE
-41017c00 __FIQ_STACK_START
-41017c00 __IRQ_STACK_END
-00000100 __IRQ_STACK_SIZE
-41017b00 __IRQ_STACK_START
-41018000 __STACK_END
-00000200 __STACK_SIZE
-41017b00 __SVC_STACK_END
-00000100 __SVC_STACK_SIZE
-41017a00 __SVC_STACK_START
-00000100 __SYSMEM_SIZE
-UNDEFED __TI_CINIT_Base
-UNDEFED __TI_CINIT_Limit
-UNDEFED __TI_Handler_Table_Base
-UNDEFED __TI_Handler_Table_Limit
-41012264 __TI_auto_init_nobinit_nopinit
-ffffffff __TI_pprof_out_hndl
-ffffffff __TI_prof_data_size
-ffffffff __TI_prof_data_start
-41010000 __TI_static_base__
-41017a00 __UND_STACK_END
-00000100 __UND_STACK_SIZE
-41017900 __UND_STACK_START
-ffffffff __binit__
-ffffffff __c_args__
-410126d8 __mpu_init
-41017e00 __stack
-410123e0 _args_main
-41012c64 _c_int00
-41011e38 _cslRsvdHandler
-41c00000 _resetvectors
-41011e34 _stkchk_called
-41012b50 _sys_memory
-41012830 _system_post_cinit
-41012828 _system_pre_init
-41012410 abort
-41010634 argArray
-ffffffff binit
-41012010 dataAbortExptnHandler
-41012088 fiqExptnHandler
-41010e34 fxnArray
-4101288c gCslR5MpuCfg
-41010004 gExptnHandlers
-41010000 gVimBaseAddr
-41010034 intrMap
-41010234 intrPri
-41011634 intrSrcType
-41012100 irqExptnHandler
-41012400 main
-41011e3c main_func_sp
-41011e80 masterIsr
-41012178 prefetchAbortExptnHandler
-41012318 swIntrExptnHandler
-410121f0 undefInstructionExptnHandler
-
-
-GLOBAL SYMBOLS: SORTED BY Symbol Address
-
-address name
-------- ----
-00000100 __ABORT_STACK_SIZE
-00000100 __FIQ_STACK_SIZE
-00000100 __IRQ_STACK_SIZE
-00000100 __SVC_STACK_SIZE
-00000100 __SYSMEM_SIZE
-00000100 __UND_STACK_SIZE
-00000200 __STACK_SIZE
-41010000 __TI_static_base__
-41010000 gVimBaseAddr
-41010004 gExptnHandlers
-41010034 intrMap
-41010234 intrPri
-41010634 argArray
-41010e34 fxnArray
-41011634 intrSrcType
-41011e34 _stkchk_called
-41011e38 _cslRsvdHandler
-41011e3c main_func_sp
-41011e80 masterIsr
-41011f7c CSL_vimCfgIntr
-41012010 dataAbortExptnHandler
-41012088 fiqExptnHandler
-41012100 irqExptnHandler
-41012178 prefetchAbortExptnHandler
-410121f0 undefInstructionExptnHandler
-41012264 __TI_auto_init_nobinit_nopinit
-410122cc CSL_vimGetActivePendingIntr
-41012318 swIntrExptnHandler
-41012364 CSL_vimClrIntrPending
-41012394 CSL_vimAckIntr
-410123c0 StartupEmulatorWaitFxn
-410123e0 _args_main
-41012400 main
-41012410 C$$EXIT
-41012410 abort
-41012418 CSL_armR5StartupCacheEnableAllCache
-4101242c CSL_armR5StartupCacheEnableForceWrThru
-4101244c CSL_armR5StartupCacheEnableICache
-4101247c CSL_armR5StartupCacheEnableDCache
-410124ac CSL_armR5StartupCacheInvalidateAllIcache
-410124c4 CSL_armR5StartupCacheInvalidateAllDcache
-410124dc CSL_armR5StartupCacheInvalidateAllCache
-410124f0 CSL_armR5StartupMpuEnable
-41012518 CSL_armR5StartupMpuCfgRegion
-41012534 CSL_armR5StartupReadMpidrReg
-41012540 CSL_armR5StartupFpuEnable
-41012568 CSL_armR5StartupIntrEnableVic
-4101258c CSL_armR5StartupIntrEnableFiq
-410125ac CSL_armR5StartupIntrEnableIrq
-410125cc CSL_armR5MPUCfg
-410126d8 __mpu_init
-4101276c CSL_startupVimSetIntrEnable
-410127c4 CSL_startupVimClrIntrPending
-41012800 CSL_armR5StartupGetCpuID
-41012828 _system_pre_init
-41012830 _system_post_cinit
-4101288c gCslR5MpuCfg
-41012b50 _sys_memory
-41012c64 _c_int00
-41012d3c HF
-41017900 __UND_STACK_START
-41017a00 __SVC_STACK_START
-41017a00 __UND_STACK_END
-41017b00 __IRQ_STACK_START
-41017b00 __SVC_STACK_END
-41017c00 __FIQ_STACK_START
-41017c00 __IRQ_STACK_END
-41017d00 __ABORT_STACK_START
-41017d00 __FIQ_STACK_END
-41017e00 __ABORT_STACK_END
-41017e00 __stack
-41018000 __STACK_END
-41c00000 _resetvectors
-ffffffff __TI_pprof_out_hndl
-ffffffff __TI_prof_data_size
-ffffffff __TI_prof_data_start
-ffffffff __binit__
-ffffffff __c_args__
-ffffffff binit
-UNDEFED __TI_CINIT_Base
-UNDEFED __TI_CINIT_Limit
-UNDEFED __TI_Handler_Table_Base
-UNDEFED __TI_Handler_Table_Limit
-
-[83 symbols]
diff --git a/packages/ti/build/am65xx/sbl_mcux_0_dummy_app.rprc b/packages/ti/build/am65xx/sbl_mcux_0_dummy_app.rprc
deleted file mode 100755 (executable)
index bfd581f..0000000
Binary files a/packages/ti/build/am65xx/sbl_mcux_0_dummy_app.rprc and /dev/null differ
index bfd581f..0000000
Binary files a/packages/ti/build/am65xx/sbl_mcux_0_dummy_app.rprc and /dev/null differ
diff --git a/packages/ti/build/am65xx/sysbios_a53.cfg b/packages/ti/build/am65xx/sysbios_a53.cfg
+++ /dev/null
@@ -1,150 +0,0 @@
-
-/* =============================================================================
- * Copyright (c) Texas Instruments Incorporated 2018
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the
- * distribution.
- *
- * Neither the name of Texas Instruments Incorporated nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-var Defaults = xdc.useModule('xdc.runtime.Defaults');
-var Diags = xdc.useModule('xdc.runtime.Diags');
-var Error = xdc.useModule('xdc.runtime.Error');
-var Log = xdc.useModule('xdc.runtime.Log');
-var LoggerBuf = xdc.useModule('xdc.runtime.LoggerBuf');
-var Main = xdc.useModule('xdc.runtime.Main');
-var Memory = xdc.useModule('xdc.runtime.Memory');
-var System = xdc.useModule('xdc.runtime.System');
-var Text = xdc.useModule('xdc.runtime.Text');
-var Clock = xdc.useModule('ti.sysbios.knl.Clock');
-var Task = xdc.useModule('ti.sysbios.knl.Task');
-var Semaphore = xdc.useModule('ti.sysbios.knl.Semaphore');
-var Event = xdc.useModule('ti.sysbios.knl.Event');
-var GateMutexPri = xdc.useModule('ti.sysbios.gates.GateMutexPri');
-
-var BIOS = xdc.useModule('ti.sysbios.BIOS');
-var Hwi = xdc.useModule('ti.sysbios.hal.Hwi');
-var HeapMem = xdc.useModule('ti.sysbios.heaps.HeapMem');
-var SysMin = xdc.useModule('xdc.runtime.SysMin');
-
-var Cache = xdc.module("ti.sysbios.hal.Cache");
-Cache.CacheProxy = xdc.useModule("ti.sysbios.family.arm.v8a.Cache");
-
-var Mmu = xdc.useModule('ti.sysbios.family.arm.v8a.Mmu');
-Mmu.initFunc = "&InitMmu";
-Mmu.tableArrayLen = 24;
-Program.sectMap[".ti_sysbios_family_arm_v8a_Mmu_tableArray"] = "MSMC_SRAM";
-
-/*
- * Direct CIO to UART
- */
-/* System.SupportProxy = SysUart; */
-System.SupportProxy = SysMin;
-
-/*
- * Program.argSize sets the size of the .args section.
- * The examples don't use command line args so argSize is set to 0.
- */
-Program.argSize = 0x0;
-
-/*
- * Uncomment this line to globally disable Asserts.
- * All modules inherit the default from the 'Defaults' module. You
- * can override these defaults on a per-module basis using Module.common$.
- * Disabling Asserts will save code space and improve runtime performance.
-Defaults.common$.diags_ASSERT = Diags.ALWAYS_OFF;
- */
-
-/*
- * Uncomment this line to keep module names from being loaded on the target.
- * The module name strings are placed in the .const section. Setting this
- * parameter to false will save space in the .const section. Error and
- * Assert messages will contain an "unknown module" prefix instead
- * of the actual module name.
-Defaults.common$.namedModule = false;
- */
-
-/* Create default heap and hook it into Memory */
-var heapMemParams = new HeapMem.Params;
-heapMemParams.size = 16384*3;
-var heap0 = HeapMem.create(heapMemParams);
-
-Memory.defaultHeapInstance = heap0;
-
-/*
- * Minimize exit handler array in System. The System module includes
- * an array of functions that are registered with System_atexit() to be
- * called by System_exit().
- */
-System.maxAtexitHandlers = 4;
-
-/*
- * Uncomment this line to disable the Error print function.
- * We lose error information when this is disabled since the errors are
- * not printed. Disabling the raiseHook will save some code space if
- * your app is not using System_printf() since the Error_print() function
- * calls System_printf().
-Error.raiseHook = null;
- */
-
-/*
- * Uncomment this line to keep Error, Assert, and Log strings from being
- * loaded on the target. These strings are placed in the .const section.
- * Setting this parameter to false will save space in the .const section.
- * Error, Assert and Log message will print raw ids and args instead of
- * a formatted message.
-Text.isLoaded = false;
- */
-
-/*
- * Uncomment this line to disable the output of characters by SysMin
- * when the program exits. SysMin writes characters to a circular buffer.
- * This buffer can be viewed using the SysMin Output view in ROV.
-SysMin.flushAtExit = false;
- */
-
-/*
- * Create and install logger for the whole system
- */
-var loggerBufParams = new LoggerBuf.Params();
-loggerBufParams.numEntries = 32;
-var logger0 = LoggerBuf.create(loggerBufParams);
-Defaults.common$.logger = logger0;
-Main.common$.diags_INFO = Diags.ALWAYS_ON;
-
-BIOS.libType = BIOS.LibType_Custom;
-
-/* Disable Timer frequency check, workaround for QT test */
-var Timer = xdc.useModule('ti.sysbios.timers.dmtimer.Timer');
-Timer.checkFrequency = false;
-
-/* Check if application needs to update with custom configuration options */
-var cfgUpdate = java.lang.System.getenv("XDC_CFG_UPDATE")
-if(cfgUpdate != '' && cfgUpdate != null)
-{
- xdc.print("Loading configuration update " + cfgUpdate);
- xdc.loadCapsule(cfgUpdate);
-}
diff --git a/packages/ti/build/am65xx/sysbios_r5f.cfg b/packages/ti/build/am65xx/sysbios_r5f.cfg
+++ /dev/null
@@ -1,188 +0,0 @@
-
-/* =============================================================================
- * Copyright (c) Texas Instruments Incorporated 2018
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the
- * distribution.
- *
- * Neither the name of Texas Instruments Incorporated nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-var Defaults = xdc.useModule('xdc.runtime.Defaults');
-var Diags = xdc.useModule('xdc.runtime.Diags');
-var Error = xdc.useModule('xdc.runtime.Error');
-var Log = xdc.useModule('xdc.runtime.Log');
-var LoggerBuf = xdc.useModule('xdc.runtime.LoggerBuf');
-var Main = xdc.useModule('xdc.runtime.Main');
-var Memory = xdc.useModule('xdc.runtime.Memory')
-var System = xdc.useModule('xdc.runtime.System');
-var Text = xdc.useModule('xdc.runtime.Text');
-var Clock = xdc.useModule('ti.sysbios.knl.Clock');
-var Task = xdc.useModule('ti.sysbios.knl.Task');
-var Semaphore = xdc.useModule('ti.sysbios.knl.Semaphore');
-var Core = xdc.useModule('ti.sysbios.family.arm.v7r.keystone3.Core');
-var Event = xdc.useModule('ti.sysbios.knl.Event');
-var GateMutexPri = xdc.useModule('ti.sysbios.gates.GateMutexPri');
-
-var BIOS = xdc.useModule('ti.sysbios.BIOS');
-var Hwi = xdc.useModule('ti.sysbios.family.arm.v7r.keystone3.Hwi');
-var HeapMem = xdc.useModule('ti.sysbios.heaps.HeapMem');
-var SysMin = xdc.useModule('xdc.runtime.SysMin');
-
-/* System stack size (used by ISRs and Swis) */
-Program.stack = 0x2000;
-var Task = xdc.useModule('ti.sysbios.knl.Task');
-Task.defaultStackSize = 0x4000;
-Task.common$.namedInstance = true;
-Task.common$.namedModule = true;
-
-/* Enable cache */
-var Cache = xdc.useModule('ti.sysbios.family.arm.v7r.Cache');
-Cache.enableCache = true;
-
-/*
- * Direct CIO to UART
- */
-/* System.SupportProxy = SysUart; */
-System.SupportProxy = SysMin;
-
-/*
- * Program.argSize sets the size of the .args section.
- * The examples don't use command line args so argSize is set to 0.
- */
-Program.argSize = 0x0;
-
-/*
- * Uncomment this line to globally disable Asserts.
- * All modules inherit the default from the 'Defaults' module. You
- * can override these defaults on a per-module basis using Module.common$.
- * Disabling Asserts will save code space and improve runtime performance.
-Defaults.common$.diags_ASSERT = Diags.ALWAYS_OFF;
- */
-
-/*
- * Uncomment this line to keep module names from being loaded on the target.
- * The module name strings are placed in the .const section. Setting this
- * parameter to false will save space in the .const section. Error and
- * Assert messages will contain an "unknown module" prefix instead
- * of the actual module name.
-Defaults.common$.namedModule = false;
- */
-
-/* Create default heap and hook it into Memory */
-var heapMemParams = new HeapMem.Params;
-heapMemParams.size = 16384*3;
-var heap0 = HeapMem.create(heapMemParams);
-
-Memory.defaultHeapInstance = heap0;
-
-/*
- * Minimize exit handler array in System. The System module includes
- * an array of functions that are registered with System_atexit() to be
- * called by System_exit().
- */
-System.maxAtexitHandlers = 4;
-
-/*
- * Uncomment this line to disable the Error print function.
- * We lose error information when this is disabled since the errors are
- * not printed. Disabling the raiseHook will save some code space if
- * your app is not using System_printf() since the Error_print() function
- * calls System_printf().
-Error.raiseHook = null;
- */
-
-/*
- * Uncomment this line to keep Error, Assert, and Log strings from being
- * loaded on the target. These strings are placed in the .const section.
- * Setting this parameter to false will save space in the .const section.
- * Error, Assert and Log message will print raw ids and args instead of
- * a formatted message.
-Text.isLoaded = false;
- */
-
-/*
- * Uncomment this line to disable the output of characters by SysMin
- * when the program exits. SysMin writes characters to a circular buffer.
- * This buffer can be viewed using the SysMin Output view in ROV.
-SysMin.flushAtExit = false;
- */
-
-/*
- * Create and install logger for the whole system
- */
-var loggerBufParams = new LoggerBuf.Params();
-loggerBufParams.numEntries = 32;
-var logger0 = LoggerBuf.create(loggerBufParams);
-Defaults.common$.logger = logger0;
-Main.common$.diags_INFO = Diags.ALWAYS_ON;
-
-BIOS.libType = BIOS.LibType_Custom;
-
-/* Disable Timer frequency check, workaround for QT test */
-var Timer = xdc.useModule('ti.sysbios.timers.dmtimer.Timer');
-Timer.checkFrequency = false;
-
-/*
- * Initialize MPU and enable it
- *
- * Note: MPU must be enabled and properly configured for caching to work.
- */
-xdc.loadCapsule("r5_mpu.xs");
-
-/* Check if application needs to update with custom configuration options */
-var cfgUpdate = java.lang.System.getenv("XDC_CFG_UPDATE")
-if(cfgUpdate != '' && cfgUpdate != null)
-{
- xdc.print("Loading configuration update " + cfgUpdate);
- xdc.loadCapsule(cfgUpdate);
-}
-
-var coreId = java.lang.System.getenv("CORE");
-if(coreId=="mcu1_0")
-{
- Core.id = 0;
- /* DM timer cfg */
- Clock.timerId = 1;
-}
-if(coreId=="mcu1_1")
-{
- Core.id = 1;
- /* DM timer cfg */
- Clock.timerId = 2;
-}
-
-/* Sysbios supports workaround for Silicon issue https://jira.itg.ti.com/browse/K3_OPEN_SI-148
- * Details of silicon issue : https://confluence.itg.ti.com/display/PROCIPDEV/%2310+The+same+interrupt+cannot+be+nested+back-2-back+within+another+interrupt
- * Sysbios Requirement Details: https://jira.itg.ti.com/browse/SYSBIOS-1419
- * Workaround requires use of a resevred dummyIRQ.
- * Using DummyIRQ#352 as per cslr_intr_mcu0.h it is a reserved interrupt not connected to any
- * peripheral interrupt sources
- */
-Hwi.dummyIRQ = 352;
-
-/* Enable ATCM and copy the vector to same */
-var Reset = xdc.useModule("xdc.runtime.Reset");
-Reset.fxns[Reset.fxns.length++] = "&utilsCopyVecs2ATcm";
diff --git a/packages/ti/build/am65xx/sysbios_smp_a53.cfg b/packages/ti/build/am65xx/sysbios_smp_a53.cfg
+++ /dev/null
@@ -1,159 +0,0 @@
-
-/* =============================================================================
- * Copyright (c) Texas Instruments Incorporated 2019
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the
- * distribution.
- *
- * Neither the name of Texas Instruments Incorporated nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-var Defaults = xdc.useModule('xdc.runtime.Defaults');
-var Diags = xdc.useModule('xdc.runtime.Diags');
-var Error = xdc.useModule('xdc.runtime.Error');
-var Log = xdc.useModule('xdc.runtime.Log');
-var LoggerBuf = xdc.useModule('ti.sysbios.smp.LoggerBuf');
-var Main = xdc.useModule('xdc.runtime.Main');
-var Memory = xdc.useModule('xdc.runtime.Memory');
-var System = xdc.useModule('xdc.runtime.System');
-var Text = xdc.useModule('xdc.runtime.Text');
-var Clock = xdc.useModule('ti.sysbios.knl.Clock');
-var Task = xdc.useModule('ti.sysbios.knl.Task');
-var Semaphore = xdc.useModule('ti.sysbios.knl.Semaphore');
-var Event = xdc.useModule('ti.sysbios.knl.Event');
-var GateMutexPri = xdc.useModule('ti.sysbios.gates.GateMutexPri');
-
-var BIOS = xdc.useModule('ti.sysbios.BIOS');
-var Hwi = xdc.useModule('ti.sysbios.hal.Hwi');
-var HeapMem = xdc.useModule('ti.sysbios.heaps.HeapMem');
-var SysMin = xdc.useModule('ti.sysbios.smp.SysMin');
-var Core = xdc.useModule('ti.sysbios.family.arm.v8a.smp.Core');
-
-var Mmu = xdc.useModule('ti.sysbios.family.arm.v8a.Mmu');
-Mmu.initFunc = "&InitMmu";
-Mmu.tableArrayLen = 24;
-Program.sectMap[".ti_sysbios_family_arm_v8a_Mmu_tableArray"] = "MSMC_SRAM";
-
-/*Enabling BIOS SMP mode */
-BIOS.smpEnabled = true;
-
-/* Enable cache */
-var Cache = xdc.module("ti.sysbios.hal.Cache");
-
-/*
- * Direct CIO to UART
- */
-/* System.SupportProxy = SysUart; */
-System.SupportProxy = SysMin;
-
-/*
- * Program.argSize sets the size of the .args section.
- * The examples don't use command line args so argSize is set to 0.
- */
-Program.argSize = 0x0;
-
-/*
- * Uncomment this line to globally disable Asserts.
- * All modules inherit the default from the 'Defaults' module. You
- * can override these defaults on a per-module basis using Module.common$.
- * Disabling Asserts will save code space and improve runtime performance.
-Defaults.common$.diags_ASSERT = Diags.ALWAYS_OFF;
- */
-
-/*
- * Uncomment this line to keep module names from being loaded on the target.
- * The module name strings are placed in the .const section. Setting this
- * parameter to false will save space in the .const section. Error and
- * Assert messages will contain an "unknown module" prefix instead
- * of the actual module name.
-Defaults.common$.namedModule = false;
- */
-
-/* Create default heap and hook it into Memory */
-var heapMemParams = new HeapMem.Params;
-heapMemParams.size = 16384*18;
-var heap0 = HeapMem.create(heapMemParams);
-
-Memory.defaultHeapInstance = heap0;
-
-/*
- * Minimize exit handler array in System. The System module includes
- * an array of functions that are registered with System_atexit() to be
- * called by System_exit().
- */
-System.maxAtexitHandlers = 4;
-
-/*
- * Uncomment this line to disable the Error print function.
- * We lose error information when this is disabled since the errors are
- * not printed. Disabling the raiseHook will save some code space if
- * your app is not using System_printf() since the Error_print() function
- * calls System_printf().
-Error.raiseHook = null;
- */
-
-/*
- * Uncomment this line to keep Error, Assert, and Log strings from being
- * loaded on the target. These strings are placed in the .const section.
- * Setting this parameter to false will save space in the .const section.
- * Error, Assert and Log message will print raw ids and args instead of
- * a formatted message.
-Text.isLoaded = false;
- */
-
-/*
- * Uncomment this line to disable the output of characters by SysMin
- * when the program exits. SysMin writes characters to a circular buffer.
- * This buffer can be viewed using the SysMin Output view in ROV.
-SysMin.flushAtExit = false;
- */
-
-/*
- * Create and install logger for the whole system
- */
-var loggerBufParams = new LoggerBuf.Params();
-loggerBufParams.numEntries = 32;
-var logger0 = LoggerBuf.create(loggerBufParams);
-Defaults.common$.logger = logger0;
-Main.common$.diags_INFO = Diags.ALWAYS_ON;
-
-BIOS.libType = BIOS.LibType_Custom;
-
-/* System stack size (used by ISRs and Swis) */
-Program.stack = 0x10000;
-
-Task.defaultStackSize = 0x4000;
-
-/* Disable Timer frequency check, workaround for QT test */
-var Timer = xdc.useModule('ti.sysbios.timers.dmtimer.Timer');
-Timer.checkFrequency = false;
-
-/* Check if application needs to update with custom configuration options */
-var cfgUpdate = java.lang.System.getenv("XDC_CFG_UPDATE")
-if(cfgUpdate != '' && cfgUpdate != null)
-{
- xdc.print("Loading configuration update " + cfgUpdate);
- xdc.loadCapsule(cfgUpdate);
-}
diff --git a/packages/ti/build/awr294x/config_awr294x_c66.bld b/packages/ti/build/awr294x/config_awr294x_c66.bld
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
-* Copyright (c) 2020, Texas Instruments Incorporated
-* All rights reserved.
-*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions
-* are met:
-*
-* * Redistributions of source code must retain the above copyright
-* notice, this list of conditions and the following disclaimer.
-*
-* * Redistributions in binary form must reproduce the above copyright
-* notice, this list of conditions and the following disclaimer in the
-* documentation and/or other materials provided with the distribution.
-*
-* * Neither the name of Texas Instruments Incorporated nor the names of
-* its contributors may be used to endorse or promote products derived
-* from this software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
-* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
-* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
-* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
-
-/*
- * ======== config_awr294x_c66.bld ========
- * Build configuration script for BSP drivers
- */
-/* load the required modules for the configuration */
-var C66 = xdc.useModule('ti.targets.elf.C66');
-/* C66 compiler directory path */
-C66.rootDir = java.lang.System.getenv("C6X_GEN_INSTALL_PATH");
diff --git a/packages/ti/build/awr294x/config_awr294x_r5f.bld b/packages/ti/build/awr294x/config_awr294x_r5f.bld
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
-* Copyright (c) 2020, Texas Instruments Incorporated
-* All rights reserved.
-*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions
-* are met:
-*
-* * Redistributions of source code must retain the above copyright
-* notice, this list of conditions and the following disclaimer.
-*
-* * Redistributions in binary form must reproduce the above copyright
-* notice, this list of conditions and the following disclaimer in the
-* documentation and/or other materials provided with the distribution.
-*
-* * Neither the name of Texas Instruments Incorporated nor the names of
-* its contributors may be used to endorse or promote products derived
-* from this software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
-* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
-* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
-* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
-
-/*
- * ======== config_awr294x_r5.bld ========
- * Build configuration script for BSP drivers
- */
-/* load the required modules for the configuration */
-
-var xdc_disable_thumb_mode = java.lang.System.getenv("XDC_DISABLE_THUMB_MODE");
-if(xdc_disable_thumb_mode != '' && xdc_disable_thumb_mode != null)
-{
-/* If XDC thumb mode is disabled, use the non-thumb mode xdc target */
-var R5F = xdc.useModule('ti.targets.arm.elf.R5F');
-}
-else
-{
-var R5F = xdc.useModule('ti.targets.arm.elf.R5Ft');
-}
-/* R5F compiler directory path */
-R5F.rootDir = java.lang.System.getenv("CGTOOLS");
diff --git a/packages/ti/build/awr294x/linker_c66.cmd b/packages/ti/build/awr294x/linker_c66.cmd
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- * Copyright (c) 2016, Texas Instruments Incorporated
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * * Neither the name of Texas Instruments Incorporated nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
- * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
- * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
- * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
- * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#define L1P_CACHE_SIZE (16*1024)
-#define L1D_CACHE_SIZE (16*1024)
-
-MEMORY
-{
-PAGE 0:
-
-#if (L1P_CACHE_SIZE < 0x8000)
- L1PSRAM: o = 0x00E00000, l = (0x00008000 - L1P_CACHE_SIZE)
-#endif
-#if (L1D_CACHE_SIZE < 0x8000)
- L1DSRAM: o = 0x00F00000, l = (0x00008000 - L1D_CACHE_SIZE)
-#endif
- L2SRAM: o = 0x00800000, l = 0x00060000
- L3SRAM: o = 0x88000000, l = 0x00390000
- HWA_RAM: o = 0x82000000, l = 0x00020000
-
- /* PAGEs 1 and onwards are for overlay purposes for memory optimization.
- Some examples:
- 1. Overlay one-time only text with uninitialized data.
- 2. Overlay L1PSRAM data path processing fast code and use copy tables
- to page in (before entering data path) and out of L1PSRAM (when entering
- sleep/low power).
- */
-PAGE 1:
- L3SRAM: o = 0x88000000, l = 0x00390000
-}
-
--stack 0x2000 /* SOFTWARE STACK SIZE */
--heap 0x2000 /* HEAP AREA SIZE */
-
-/* Set L1D, L1P and L2 Cache Sizes */
-ti_sysbios_family_c66_Cache_l1dSize = L1D_CACHE_SIZE;
-ti_sysbios_family_c66_Cache_l1pSize = L1P_CACHE_SIZE;
-ti_sysbios_family_c66_Cache_l2Size = 0;
-
-SECTIONS
-{
- /* hard addresses forces vecs to be allocated there */
- .vecs: {. = align(32); } > 0x00800000
-
- .fardata: {} > L2SRAM
- .const: {} > L2SRAM
- .switch: {} > L2SRAM
- .cio: {} > L2SRAM
- .data: {} > L2SRAM
- .sysmem: {} > L2SRAM
-
- GROUP
- {
- .rodata:
- .bss:
- .neardata:
- } > L2SRAM
- .stack: {} > L2SRAM
- .cinit: {} > L2SRAM
- .far: {} > L2SRAM
-
- .text: {} > L2SRAM
-}
diff --git a/packages/ti/build/awr294x/linker_c66_baremetal.cmd b/packages/ti/build/awr294x/linker_c66_baremetal.cmd
+++ /dev/null
@@ -1,88 +0,0 @@
-/*
- * Copyright (c) 2016, Texas Instruments Incorporated
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * * Neither the name of Texas Instruments Incorporated nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
- * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
- * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
- * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
- * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#define L1P_CACHE_SIZE (16*1024)
-#define L1D_CACHE_SIZE (16*1024)
-
-MEMORY
-{
-PAGE 0:
-
-#if (L1P_CACHE_SIZE < 0x8000)
- L1PSRAM: o = 0x00E00000, l = (0x00008000 - L1P_CACHE_SIZE)
-#endif
-#if (L1D_CACHE_SIZE < 0x8000)
- L1DSRAM: o = 0x00F00000, l = (0x00008000 - L1D_CACHE_SIZE)
-#endif
- L2SRAM: o = 0x00800000, l = 0x00060000
- L3SRAM: o = 0x88000000, l = 0x00390000
- HWA_RAM: o = 0x82000000, l = 0x00020000
-
- /* PAGEs 1 and onwards are for overlay purposes for memory optimization.
- Some examples:
- 1. Overlay one-time only text with uninitialized data.
- 2. Overlay L1PSRAM data path processing fast code and use copy tables
- to page in (before entering data path) and out of L1PSRAM (when entering
- sleep/low power).
- */
-PAGE 1:
- L3SRAM: o = 0x88000000, l = 0x00390000
-}
-
--stack 0x2000 /* SOFTWARE STACK SIZE */
--heap 0x2000 /* HEAP AREA SIZE */
-
-
-SECTIONS
-{
- /* hard addresses forces vecs to be allocated there */
- .csl_vect: {. = align(32); } > 0x00800000
-
- .fardata: {} > L2SRAM
- .const: {} > L2SRAM
- .switch: {} > L2SRAM
- .cio: {} > L2SRAM
- .data: {} > L2SRAM
- .sysmem: {} > L2SRAM
-
- GROUP
- {
- .rodata:
- .bss:
- .neardata:
- } > L2SRAM
- .stack: {} > L2SRAM
- .cinit: {} > L2SRAM
- .far: {} > L2SRAM
-
- .text: {} > L2SRAM
-}
diff --git a/packages/ti/build/awr294x/linker_c66_freertos.cmd b/packages/ti/build/awr294x/linker_c66_freertos.cmd
+++ /dev/null
@@ -1,90 +0,0 @@
-/*
- * Copyright (c) 2016, Texas Instruments Incorporated
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * * Neither the name of Texas Instruments Incorporated nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
- * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
- * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
- * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
- * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#define L1P_CACHE_SIZE (16*1024)
-#define L1D_CACHE_SIZE (16*1024)
-
-MEMORY
-{
-PAGE 0:
-
-#if (L1P_CACHE_SIZE < 0x8000)
- L1PSRAM: o = 0x00E00000, l = (0x00008000 - L1P_CACHE_SIZE)
-#endif
-#if (L1D_CACHE_SIZE < 0x8000)
- L1DSRAM: o = 0x00F00000, l = (0x00008000 - L1D_CACHE_SIZE)
-#endif
- L2SRAM: o = 0x00800000, l = 0x00060000
- L3SRAM: o = 0x88000000, l = 0x00390000
- HWA_RAM: o = 0x82000000, l = 0x00020000
-
- /* PAGEs 1 and onwards are for overlay purposes for memory optimization.
- Some examples:
- 1. Overlay one-time only text with uninitialized data.
- 2. Overlay L1PSRAM data path processing fast code and use copy tables
- to page in (before entering data path) and out of L1PSRAM (when entering
- sleep/low power).
- */
-PAGE 1:
- L3SRAM: o = 0x88000000, l = 0x00390000
-}
-
--stack 0x2000 /* SOFTWARE STACK SIZE */
--heap 0x1000 /* HEAP AREA SIZE */
---symbol_map _Hwi_intcVectorTable=Hwi_intcVectorTable
-
-
-SECTIONS
-{
- /* hard addresses forces vecs to be allocated there */
- .hwi_vect: {. = align(32); } > 0x00800000
- .text:csl_entry:{} > L2SRAM
- .fardata: {} > L2SRAM
- .const: {} > L2SRAM
- .switch: {} > L2SRAM
- .cio: {} > L2SRAM
- .data: {} > L2SRAM
- .sysmem: {} > L2SRAM
-
- GROUP
- {
- .rodata:
- .bss:
- .neardata:
- } > L2SRAM
- .stack: {} > L2SRAM
- .cinit: {} > L2SRAM
- .far: {} > L2SRAM
-
- .text: {} > L2SRAM
-}
-
diff --git a/packages/ti/build/awr294x/linker_c66_safertos.cmd b/packages/ti/build/awr294x/linker_c66_safertos.cmd
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- * Copyright (c) 2016, Texas Instruments Incorporated
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * * Neither the name of Texas Instruments Incorporated nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
- * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
- * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
- * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
- * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#define L1P_CACHE_SIZE (16*1024)
-#define L1D_CACHE_SIZE (16*1024)
-
-MEMORY
-{
-PAGE 0:
-
-#if (L1P_CACHE_SIZE < 0x8000)
- L1PSRAM: o = 0x00E00000, l = (0x00008000 - L1P_CACHE_SIZE)
-#endif
-#if (L1D_CACHE_SIZE < 0x8000)
- L1DSRAM: o = 0x00F00000, l = (0x00008000 - L1D_CACHE_SIZE)
-#endif
- L2SRAM: o = 0x00800000, l = 0x00060000
- L3SRAM: o = 0x88000000, l = 0x00390000
- HWA_RAM: o = 0x82000000, l = 0x00020000
-
- /* PAGEs 1 and onwards are for overlay purposes for memory optimization.
- Some examples:
- 1. Overlay one-time only text with uninitialized data.
- 2. Overlay L1PSRAM data path processing fast code and use copy tables
- to page in (before entering data path) and out of L1PSRAM (when entering
- sleep/low power).
- */
-PAGE 1:
- L3SRAM: o = 0x88000000, l = 0x00390000
-}
-
--stack 0x2000 /* SOFTWARE STACK SIZE */
--heap 0x1000 /* HEAP AREA SIZE */
--u _Hwi_intcVectorTable
-
-SECTIONS
-{
- /* hard addresses forces vecs to be allocated there
- LOAD_START( lnkStartFlashAddress ), */
-
- .hwi_vect: {. = align(32); } > 0x00800000
-/*
- .kernel_function LOAD_START( lnkKernelFuncStartAddr ) LOAD_END( lnkKernelFuncEndAddr ) :
- {
- *(KERNEL_FUNCTION)
- } > L2SRAM
-
- .unpriv_flash palign(32), LOAD_END( lnkEndFlashAddress ) :
- {
- *(.text)
- *(.const)
- } > L2SRAM
-*/
- .text:csl_entry:{} > L2SRAM
- .fardata: {} > L2SRAM
- .const: {} > L2SRAM
- .switch: {} > L2SRAM
- .cio: {} > L2SRAM
- .data: {} > L2SRAM
- .sysmem: {} > L2SRAM
-
- GROUP
- {
- .rodata:
- .bss:
- .neardata:
- } > L2SRAM
-/*
- KERNEL_DATA LOAD_START( lnkKernelDataStartAddr ),
- LOAD_END( lnkKernelDataEndAddr ) : {} > L2SRAM
-*/
- .stack: {} > L2SRAM
- .cinit: {} > L2SRAM
- .far: {} > L2SRAM
-
- .text: {} > L2SRAM
-}
-
-/* lnkStartFlashAddress */
-/* lnkKernelFuncStartAddr */
-
-/* lnkKernelFuncEndAddr */
-/* lnkEndFlashAddress */
-
-/* lnkKernelDataStartAddr */
-/* lnkKernelDataEndAddr */
diff --git a/packages/ti/build/awr294x/linker_mcu1_0.lds b/packages/ti/build/awr294x/linker_mcu1_0.lds
+++ /dev/null
@@ -1,100 +0,0 @@
-/*----------------------------------------------------------------------------*/
-/* r5f_linker.cmd */
-/* */
-/* (c) Texas Instruments 2020, All rights reserved. */
-/* */
-
-/* USER CODE BEGIN (0) */
-/* USER CODE END */
---retain="*(.intvecs)"
---retain="*(.intc_text)"
---retain="*(.rstvectors)"
---retain="*(.irqStack)"
---retain="*(.fiqStack)"
---retain="*(.abortStack)"
---retain="*(.undStack)"
---retain="*(.svcStack)"
--stack 0x2000 /* SOFTWARE STACK SIZE */
--heap 0x2000 /* HEAP AREA SIZE */
-
-
-/* Stack Sizes for various modes */
-__IRQ_STACK_SIZE = 0x1000;
-__FIQ_STACK_SIZE = 0x1000;
-__ABORT_STACK_SIZE = 0x1000;
-__UND_STACK_SIZE = 0x1000;
-__SVC_STACK_SIZE = 0x1000;
-
-/*----------------------------------------------------------------------------*/
-/* Linker Settings */
---retain="*(.intvecs)"
--u _resetvectors
-
-/*----------------------------------------------------------------------------*/
-/* Memory Map */
-MEMORY{
-PAGE 0:
- /* Reset Vectors base address(RESET_VECTORS) should be 64 bytes aligned */
- RESET_VECTORS (X) : origin=0x00000000 length=0x100
- /* RESET_VECTORS (X) : origin=0x00020000 length=0x100 */
- TCMA_RAM (RX) : origin=0x00000100 length=0x00003F00
- TCMB_RAM (RW) : origin=0x00080000 length=0x00008000
- SBL_RESERVED_L2_RAM_0 (RW) : origin=0x10200000 length=0x00030000
- SBL_RESERVED_L2_RAM_1 (RW) : origin=0x10230000 length=0x00030000
- L2_RAM_0 (RW) : origin=0x10260000 length=0x00048000
- L2_RAM_1 (RW) : origin=0x102A8000 length=0x00048000
- L3_RAM_0 (RW) : origin=0x88000000 length=0x001C8000
- L3_RAM_1 (RW) : origin=0x881C8000 length=0x001C8000
- HWA_RAM_0 (RW) : origin=0x82000000 length=0x00010000
- HWA_RAM_1 (RW) : origin=0x82010000 length=0x00010000
-
-PAGE 1:
- L3_RAM_0 (RW) : origin=0x88000000 length=0x001C8000
- L3_RAM_1 (RW) : origin=0x881C8000 length=0x001C8000
-}
-
-/*----------------------------------------------------------------------------*/
-/* Section Configuration */
-SECTIONS{
- /* .intvecs : {} palign(8) > VECTORS */
- /* .intc_text : {} palign(8) > VECTORS */
- .rstvectors : {} palign(8) > RESET_VECTORS
- .bootCode : {} palign(8) > TCMA_RAM
- .startupCode : {} palign(8) > TCMA_RAM
- .startupData : {} palign(8) > TCMB_RAM, type = NOINIT
-
- /* The linker notation "X >> Y | Z" indicates section X is first allocated in Y
- and allowed to overflow into Z and can be split from Y to Z.
- The linker notation "X > Y | Z" indicates section X is first allocated in Y
- and allowed to overflow into Z and cannot be split from Y to Z. Some sections
- like bss are not allowed to be split so > notation is used for them
- */
- .text : {} >> TCMA_RAM | L2_RAM_0
-
- .const : {} > L2_RAM_0
- .switch : {} > L2_RAM_0
- .cio: : {} > SBL_RESERVED_L2_RAM_0 | L2_RAM_0
- .data: : {} > L2_RAM_0
-
- .cinit : {} > L2_RAM_0
- .pinit : {} > L2_RAM_0
- .bss : {} > SBL_RESERVED_L2_RAM_0 | L2_RAM_0
- .stack : {} > TCMB_RAM | SBL_RESERVED_L2_RAM_0 | L2_RAM_0
- .sysmem : {} > SBL_RESERVED_L2_RAM_0 | L2_RAM_0
- .irqStack : {. = . + __IRQ_STACK_SIZE;} align(4) > L2_RAM_0 (HIGH)
- RUN_START(__IRQ_STACK_START)
- RUN_END(__IRQ_STACK_END)
- .fiqStack : {. = . + __FIQ_STACK_SIZE;} align(4) > L2_RAM_0 (HIGH)
- RUN_START(__FIQ_STACK_START)
- RUN_END(__FIQ_STACK_END)
- .abortStack : {. = . + __ABORT_STACK_SIZE;} align(4)> L2_RAM_0 (HIGH)
- RUN_START(__ABORT_STACK_START)
- RUN_END(__ABORT_STACK_END)
- .undStack : {. = . + __UND_STACK_SIZE;} align(4) > L2_RAM_0 (HIGH)
- RUN_START(__UND_STACK_START)
- RUN_END(__UND_STACK_END)
- .svcStack : {. = . + __SVC_STACK_SIZE;} align(4) > L2_RAM_0 (HIGH)
- RUN_START(__SVC_STACK_START)
- RUN_END(__SVC_STACK_END)
-}
-/*----------------------------------------------------------------------------*/
diff --git a/packages/ti/build/awr294x/linker_mcu1_0_freertos.lds b/packages/ti/build/awr294x/linker_mcu1_0_freertos.lds
+++ /dev/null
@@ -1,96 +0,0 @@
-/*----------------------------------------------------------------------------*/
-/* r5f_linker.cmd */
-/* */
-/* (c) Texas Instruments 2020, All rights reserved. */
-/* */
-
-/* USER CODE BEGIN (0) */
-/* USER CODE END */
---retain="*(.intc_text)"
---retain="*(.irqStack)"
---retain="*(.fiqStack)"
---retain="*(.abortStack)"
---retain="*(.undStack)"
---retain="*(.svcStack)"
--stack 0x2000 /* SOFTWARE STACK SIZE */
--heap 0x1000 /* HEAP AREA SIZE */
-
--u _freertosresetvectors
-
-/* Stack Sizes for various modes */
-__IRQ_STACK_SIZE = 0x4000;
-__FIQ_STACK_SIZE = 0x4000;
-__ABORT_STACK_SIZE = 0x4000;
-__UND_STACK_SIZE = 0x4000;
-__SVC_STACK_SIZE = 0x4000;
-
-/*----------------------------------------------------------------------------*/
-/* Linker Settings */
-
-/*----------------------------------------------------------------------------*/
-/* Memory Map */
-MEMORY{
-PAGE 0:
- /* Reset Vectors base address(RESET_VECTORS) should be 64 bytes aligned */
- RESET_VECTORS (X) : origin=0x00000000 length=0x100
- /* RESET_VECTORS (X) : origin=0x00020000 length=0x100 */
- TCMA_RAM (RX) : origin=0x00000100 length=0x00003F00
- TCMB_RAM (RW) : origin=0x00080000 length=0x00008000
- SBL_RESERVED_L2_RAM_0 (RW) : origin=0x10200000 length=0x00030000
- SBL_RESERVED_L2_RAM_1 (RW) : origin=0x10230000 length=0x00030000
- L2_RAM_0 (RW) : origin=0x10260000 length=0x00048000
- L2_RAM_1 (RW) : origin=0x102A8000 length=0x00048000
- L3_RAM_0 (RW) : origin=0x88000000 length=0x001C8000
- L3_RAM_1 (RW) : origin=0x881C8000 length=0x001C8000
- HWA_RAM_0 (RW) : origin=0x82000000 length=0x00010000
- HWA_RAM_1 (RW) : origin=0x82010000 length=0x00010000
-
-PAGE 1:
- L3_RAM_0 (RW) : origin=0x88000000 length=0x001C8000
- L3_RAM_1 (RW) : origin=0x881C8000 length=0x001C8000
-}
-
-/*----------------------------------------------------------------------------*/
-/* Section Configuration */
-SECTIONS{
- .freertosrstvectors : {} palign(8) > RESET_VECTORS
- .bootCode : {} palign(8) > TCMA_RAM
- .startupCode : {} palign(8) > TCMA_RAM
- .text.hwi : {} palign(8) > TCMA_RAM
- .startupData : {} palign(8) > TCMB_RAM, type = NOINIT
-
- /* The linker notation "X >> Y | Z" indicates section X is first allocated in Y
- and allowed to overflow into Z and can be split from Y to Z.
- The linker notation "X > Y | Z" indicates section X is first allocated in Y
- and allowed to overflow into Z and cannot be split from Y to Z. Some sections
- like bss are not allowed to be split so > notation is used for them
- */
- .text : {} >> TCMA_RAM | L2_RAM_0
-
- .const : {} > L2_RAM_0
- .switch : {} > L2_RAM_0
- .cio: : {} > SBL_RESERVED_L2_RAM_0 | L2_RAM_0
- .data: : {} > L2_RAM_0
-
- .cinit : {} > L2_RAM_0
- .pinit : {} > L2_RAM_0
- .bss : {} > SBL_RESERVED_L2_RAM_0 | L2_RAM_0
- .stack : {} > TCMB_RAM | SBL_RESERVED_L2_RAM_0 | L2_RAM_0
- .sysmem : {} > SBL_RESERVED_L2_RAM_0 | L2_RAM_0
- .irqStack : {. = . + __IRQ_STACK_SIZE;} align(4) > L2_RAM_0 (HIGH)
- RUN_START(__IRQ_STACK_START)
- RUN_END(__IRQ_STACK_END)
- .fiqStack : {. = . + __FIQ_STACK_SIZE;} align(4) > L2_RAM_0 (HIGH)
- RUN_START(__FIQ_STACK_START)
- RUN_END(__FIQ_STACK_END)
- .abortStack : {. = . + __ABORT_STACK_SIZE;} align(4)> L2_RAM_0 (HIGH)
- RUN_START(__ABORT_STACK_START)
- RUN_END(__ABORT_STACK_END)
- .undStack : {. = . + __UND_STACK_SIZE;} align(4) > L2_RAM_0 (HIGH)
- RUN_START(__UND_STACK_START)
- RUN_END(__UND_STACK_END)
- .svcStack : {. = . + __SVC_STACK_SIZE;} align(4) > L2_RAM_0 (HIGH)
- RUN_START(__SVC_STACK_START)
- RUN_END(__SVC_STACK_END)
-}
-/*----------------------------------------------------------------------------*/
diff --git a/packages/ti/build/awr294x/linker_mcu1_0_sysbios.lds b/packages/ti/build/awr294x/linker_mcu1_0_sysbios.lds
+++ /dev/null
@@ -1,69 +0,0 @@
-/*----------------------------------------------------------------------------*/
-/* r4f_linker.cmd */
-/* */
-/* (c) Texas Instruments 2016, All rights reserved. */
-/* */
-
-/* USER CODE BEGIN (0) */
-/* USER CODE END */
-
-
-/*----------------------------------------------------------------------------*/
-/* Linker Settings */
---retain="*(.intvecs)"
-
-/*----------------------------------------------------------------------------*/
-/* Memory Map */
-MEMORY{
-PAGE 0:
- VECTORS (X) : origin=0x00000000 length=0x00000100
- TCMA_RAM (RX) : origin=0x00000100 length=0x00003F00
- TCMB_RAM (RW) : origin=0x00080000 length=0x00008000
- SBL_RESERVED_L2_RAM_0 (RW) : origin=0x10200000 length=0x00030000
- SBL_RESERVED_L2_RAM_1 (RW) : origin=0x10230000 length=0x00030000
- L2_RAM_0 (RW) : origin=0x10260000 length=0x00048000
- L2_RAM_1 (RW) : origin=0x102A8000 length=0x00048000
- L3_RAM_0 (RW) : origin=0x88000000 length=0x001C8000
- L3_RAM_1 (RW) : origin=0x881C8000 length=0x001C8000
- HWA_RAM_0 (RW) : origin=0x82000000 length=0x00010000
- HWA_RAM_1 (RW) : origin=0x82010000 length=0x00010000
-
-PAGE 1:
- L3_RAM_0 (RW) : origin=0x88000000 length=0x001C8000
- L3_RAM_1 (RW) : origin=0x881C8000 length=0x001C8000
-}
-
-/*----------------------------------------------------------------------------*/
-/* Section Configuration */
-SECTIONS{
- .intvecs : {} > VECTORS
-
- /* The linker notation "X >> Y | Z" indicates section X is first allocated in Y
- and allowed to overflow into Z and can be split from Y to Z.
- The linker notation "X > Y | Z" indicates section X is first allocated in Y
- and allowed to overflow into Z and cannot be split from Y to Z. Some sections
- like bss are not allowed to be split so > notation is used for them
- */
- .text : {} >> TCMA_RAM | L2_RAM_0
-
- .const : {} > L2_RAM_0
- .switch : {} > L2_RAM_0
- .cio: : {} > SBL_RESERVED_L2_RAM_0 | L2_RAM_0
- .data: : {} > L2_RAM_0
-
- .cinit : {} > L2_RAM_0
- .pinit : {} > L2_RAM_0
- .bss : {} > SBL_RESERVED_L2_RAM_0 | L2_RAM_0
- .stack : {} > TCMB_RAM | SBL_RESERVED_L2_RAM_0 | L2_RAM_0
-
- .boot:{
- *.*(*ti_sysbios_family_arm_MPU*)
- boot.aer5f*(*.text)
- *.*(*startup*)
- *.*(*Startup*)
- *.*(*Cache*)
- } > TCMA_RAM | TCMB_RAM
- .l3ram : {} > L3_RAM_0
- .l2ram : {} > SBL_RESERVED_L2_RAM_0 | L2_RAM_0
-}
-/*----------------------------------------------------------------------------*/
diff --git a/packages/ti/build/awr294x/linker_mcu1_1.lds b/packages/ti/build/awr294x/linker_mcu1_1.lds
+++ /dev/null
@@ -1,100 +0,0 @@
-/*----------------------------------------------------------------------------*/
-/* r5f_linker.cmd */
-/* */
-/* (c) Texas Instruments 2020, All rights reserved. */
-/* */
-
-/* USER CODE BEGIN (0) */
-/* USER CODE END */
---retain="*(.intvecs)"
---retain="*(.intc_text)"
---retain="*(.rstvectors)"
---retain="*(.irqStack)"
---retain="*(.fiqStack)"
---retain="*(.abortStack)"
---retain="*(.undStack)"
---retain="*(.svcStack)"
--stack 0x2000 /* SOFTWARE STACK SIZE */
--heap 0x2000 /* HEAP AREA SIZE */
-
-
-/* Stack Sizes for various modes */
-__IRQ_STACK_SIZE = 0x1000;
-__FIQ_STACK_SIZE = 0x1000;
-__ABORT_STACK_SIZE = 0x1000;
-__UND_STACK_SIZE = 0x1000;
-__SVC_STACK_SIZE = 0x1000;
-
-/*----------------------------------------------------------------------------*/
-/* Linker Settings */
---retain="*(.intvecs)"
--u _resetvectors
-
-/*----------------------------------------------------------------------------*/
-/* Memory Map */
-MEMORY{
-PAGE 0:
- /* Reset Vectors base address(RESET_VECTORS) should be 64 bytes aligned */
- RESET_VECTORS (X) : origin=0x00000000 length=0x100
- /* RESET_VECTORS (X) : origin=0x00020000 length=0x100 */
- TCMA_RAM (RX) : origin=0x00000100 length=0x00003F00
- TCMB_RAM (RW) : origin=0x00080000 length=0x00008000
- SBL_RESERVED_L2_RAM_0 (RW) : origin=0x10200000 length=0x00030000
- SBL_RESERVED_L2_RAM_1 (RW) : origin=0x10230000 length=0x00030000
- L2_RAM_0 (RW) : origin=0x10260000 length=0x00048000
- L2_RAM_1 (RW) : origin=0x102A8000 length=0x00048000
- L3_RAM_0 (RW) : origin=0x88000000 length=0x001C8000
- L3_RAM_1 (RW) : origin=0x881C8000 length=0x001C8000
- HWA_RAM_0 (RW) : origin=0x82000000 length=0x00010000
- HWA_RAM_1 (RW) : origin=0x82010000 length=0x00010000
-
-PAGE 1:
- L3_RAM_0 (RW) : origin=0x88000000 length=0x001C8000
- L3_RAM_1 (RW) : origin=0x881C8000 length=0x001C8000
-}
-
-/*----------------------------------------------------------------------------*/
-/* Section Configuration */
-SECTIONS{
- /* .intvecs : {} palign(8) > VECTORS */
- /* .intc_text : {} palign(8) > VECTORS */
- .rstvectors : {} palign(8) > RESET_VECTORS
- .bootCode : {} palign(8) > TCMA_RAM
- .startupCode : {} palign(8) > TCMA_RAM
- .startupData : {} palign(8) > TCMB_RAM, type = NOINIT
-
- /* The linker notation "X >> Y | Z" indicates section X is first allocated in Y
- and allowed to overflow into Z and can be split from Y to Z.
- The linker notation "X > Y | Z" indicates section X is first allocated in Y
- and allowed to overflow into Z and cannot be split from Y to Z. Some sections
- like bss are not allowed to be split so > notation is used for them
- */
- .text : {} >> TCMA_RAM | L2_RAM_1
-
- .const : {} > L2_RAM_1
- .switch : {} > L2_RAM_1
- .cio: : {} > SBL_RESERVED_L2_RAM_1 | L2_RAM_1
- .data: : {} > L2_RAM_1
-
- .cinit : {} > L2_RAM_1
- .pinit : {} > L2_RAM_1
- .bss : {} > SBL_RESERVED_L2_RAM_1 | L2_RAM_1
- .stack : {} > TCMB_RAM | SBL_RESERVED_L2_RAM_1 | L2_RAM_1
- .sysmem : {} > SBL_RESERVED_L2_RAM_1 | L2_RAM_1
- .irqStack : {. = . + __IRQ_STACK_SIZE;} align(4) > L2_RAM_1 (HIGH)
- RUN_START(__IRQ_STACK_START)
- RUN_END(__IRQ_STACK_END)
- .fiqStack : {. = . + __FIQ_STACK_SIZE;} align(4) > L2_RAM_1 (HIGH)
- RUN_START(__FIQ_STACK_START)
- RUN_END(__FIQ_STACK_END)
- .abortStack : {. = . + __ABORT_STACK_SIZE;} align(4)> L2_RAM_1 (HIGH)
- RUN_START(__ABORT_STACK_START)
- RUN_END(__ABORT_STACK_END)
- .undStack : {. = . + __UND_STACK_SIZE;} align(4) > L2_RAM_1 (HIGH)
- RUN_START(__UND_STACK_START)
- RUN_END(__UND_STACK_END)
- .svcStack : {. = . + __SVC_STACK_SIZE;} align(4) > L2_RAM_1 (HIGH)
- RUN_START(__SVC_STACK_START)
- RUN_END(__SVC_STACK_END)
-}
-/*----------------------------------------------------------------------------*/
diff --git a/packages/ti/build/awr294x/linker_mcu1_1_freertos.lds b/packages/ti/build/awr294x/linker_mcu1_1_freertos.lds
+++ /dev/null
@@ -1,96 +0,0 @@
-/*----------------------------------------------------------------------------*/
-/* r5f_linker.cmd */
-/* */
-/* (c) Texas Instruments 2020, All rights reserved. */
-/* */
-
-/* USER CODE BEGIN (0) */
-/* USER CODE END */
---retain="*(.intc_text)"
---retain="*(.irqStack)"
---retain="*(.fiqStack)"
---retain="*(.abortStack)"
---retain="*(.undStack)"
---retain="*(.svcStack)"
--stack 0x2000 /* SOFTWARE STACK SIZE */
--heap 0x1000 /* HEAP AREA SIZE */
-
--u _freertosresetvectors
-
-/* Stack Sizes for various modes */
-__IRQ_STACK_SIZE = 0x4000;
-__FIQ_STACK_SIZE = 0x4000;
-__ABORT_STACK_SIZE = 0x4000;
-__UND_STACK_SIZE = 0x4000;
-__SVC_STACK_SIZE = 0x4000;
-
-/*----------------------------------------------------------------------------*/
-/* Linker Settings */
-
-/*----------------------------------------------------------------------------*/
-/* Memory Map */
-MEMORY{
-PAGE 0:
- /* Reset Vectors base address(RESET_VECTORS) should be 64 bytes aligned */
- RESET_VECTORS (X) : origin=0x00000000 length=0x100
- /* RESET_VECTORS (X) : origin=0x00020000 length=0x100 */
- TCMA_RAM (RX) : origin=0x00000100 length=0x00003F00
- TCMB_RAM (RW) : origin=0x00080000 length=0x00008000
- SBL_RESERVED_L2_RAM_0 (RW) : origin=0x10200000 length=0x00030000
- SBL_RESERVED_L2_RAM_1 (RW) : origin=0x10230000 length=0x00030000
- L2_RAM_0 (RW) : origin=0x10260000 length=0x00048000
- L2_RAM_1 (RW) : origin=0x102A8000 length=0x00048000
- L3_RAM_0 (RW) : origin=0x88000000 length=0x001C8000
- L3_RAM_1 (RW) : origin=0x881C8000 length=0x001C8000
- HWA_RAM_0 (RW) : origin=0x82000000 length=0x00010000
- HWA_RAM_1 (RW) : origin=0x82010000 length=0x00010000
-
-PAGE 1:
- L3_RAM_0 (RW) : origin=0x88000000 length=0x001C8000
- L3_RAM_1 (RW) : origin=0x881C8000 length=0x001C8000
-}
-
-/*----------------------------------------------------------------------------*/
-/* Section Configuration */
-SECTIONS{
- .freertosrstvectors : {} palign(8) > RESET_VECTORS
- .bootCode : {} palign(8) > TCMA_RAM
- .startupCode : {} palign(8) > TCMA_RAM
- .text.hwi : {} palign(8) > TCMA_RAM
- .startupData : {} palign(8) > TCMB_RAM, type = NOINIT
-
- /* The linker notation "X >> Y | Z" indicates section X is first allocated in Y
- and allowed to overflow into Z and can be split from Y to Z.
- The linker notation "X > Y | Z" indicates section X is first allocated in Y
- and allowed to overflow into Z and cannot be split from Y to Z. Some sections
- like bss are not allowed to be split so > notation is used for them
- */
- .text : {} >> TCMA_RAM | L2_RAM_1
-
- .const : {} > L2_RAM_1
- .switch : {} > L2_RAM_1
- .cio: : {} > SBL_RESERVED_L2_RAM_1 | L2_RAM_1
- .data: : {} > L2_RAM_1
-
- .cinit : {} > L2_RAM_1
- .pinit : {} > L2_RAM_1
- .bss : {} > SBL_RESERVED_L2_RAM_1 | L2_RAM_1
- .stack : {} > TCMB_RAM | SBL_RESERVED_L2_RAM_1 | L2_RAM_1
- .sysmem : {} > SBL_RESERVED_L2_RAM_1 | L2_RAM_1
- .irqStack : {. = . + __IRQ_STACK_SIZE;} align(4) > L2_RAM_1 (HIGH)
- RUN_START(__IRQ_STACK_START)
- RUN_END(__IRQ_STACK_END)
- .fiqStack : {. = . + __FIQ_STACK_SIZE;} align(4) > L2_RAM_1 (HIGH)
- RUN_START(__FIQ_STACK_START)
- RUN_END(__FIQ_STACK_END)
- .abortStack : {. = . + __ABORT_STACK_SIZE;} align(4)> L2_RAM_1 (HIGH)
- RUN_START(__ABORT_STACK_START)
- RUN_END(__ABORT_STACK_END)
- .undStack : {. = . + __UND_STACK_SIZE;} align(4) > L2_RAM_1 (HIGH)
- RUN_START(__UND_STACK_START)
- RUN_END(__UND_STACK_END)
- .svcStack : {. = . + __SVC_STACK_SIZE;} align(4) > L2_RAM_1 (HIGH)
- RUN_START(__SVC_STACK_START)
- RUN_END(__SVC_STACK_END)
-}
-/*----------------------------------------------------------------------------*/
diff --git a/packages/ti/build/awr294x/linker_mcu1_1_sysbios.lds b/packages/ti/build/awr294x/linker_mcu1_1_sysbios.lds
+++ /dev/null
@@ -1,69 +0,0 @@
-/*----------------------------------------------------------------------------*/
-/* r4f_linker.cmd */
-/* */
-/* (c) Texas Instruments 2016, All rights reserved. */
-/* */
-
-/* USER CODE BEGIN (0) */
-/* USER CODE END */
-
-
-/*----------------------------------------------------------------------------*/
-/* Linker Settings */
---retain="*(.intvecs)"
-
-/*----------------------------------------------------------------------------*/
-/* Memory Map */
-MEMORY{
-PAGE 0:
- VECTORS (X) : origin=0x00000000 length=0x00000100
- TCMA_RAM (RX) : origin=0x00000100 length=0x00003F00
- TCMB_RAM (RW) : origin=0x00080000 length=0x00008000
- SBL_RESERVED_L2_RAM_0 (RW) : origin=0x10200000 length=0x00030000
- SBL_RESERVED_L2_RAM_1 (RW) : origin=0x10230000 length=0x00030000
- L2_RAM_0 (RW) : origin=0x10260000 length=0x00048000
- L2_RAM_1 (RW) : origin=0x102A8000 length=0x00048000
- L3_RAM_0 (RW) : origin=0x88000000 length=0x001C8000
- L3_RAM_1 (RW) : origin=0x881C8000 length=0x001C8000
- HWA_RAM_0 (RW) : origin=0x82000000 length=0x00010000
- HWA_RAM_1 (RW) : origin=0x82010000 length=0x00010000
-
-PAGE 1:
- L3_RAM_0 (RW) : origin=0x88000000 length=0x001C8000
- L3_RAM_1 (RW) : origin=0x881C8000 length=0x001C8000
-}
-
-/*----------------------------------------------------------------------------*/
-/* Section Configuration */
-SECTIONS{
- .intvecs : {} > VECTORS
-
- /* The linker notation "X >> Y | Z" indicates section X is first allocated in Y
- and allowed to overflow into Z and can be split from Y to Z.
- The linker notation "X > Y | Z" indicates section X is first allocated in Y
- and allowed to overflow into Z and cannot be split from Y to Z. Some sections
- like bss are not allowed to be split so > notation is used for them
- */
- .text : {} >> TCMA_RAM | L2_RAM_1
-
- .const : {} > L2_RAM_1
- .switch : {} > L2_RAM_1
- .cio: : {} > SBL_RESERVED_L2_RAM_1 | L2_RAM_1
- .data: : {} > L2_RAM_1
-
- .cinit : {} > L2_RAM_1
- .pinit : {} > L2_RAM_1
- .bss : {} > SBL_RESERVED_L2_RAM_1 | L2_RAM_1
- .stack : {} > TCMB_RAM | SBL_RESERVED_L2_RAM_1 | L2_RAM_1
-
- .boot:{
- *.*(*ti_sysbios_family_arm_MPU*)
- boot.aer5f*(*.text)
- *.*(*startup*)
- *.*(*Startup*)
- *.*(*Cache*)
- } > TCMA_RAM | TCMB_RAM
- .l3ram : {} > L3_RAM_1
- .l2ram : {} > SBL_RESERVED_L2_RAM_1 | L2_RAM_1
-}
-/*----------------------------------------------------------------------------*/
diff --git a/packages/ti/build/awr294x/r5_mpu.xs b/packages/ti/build/awr294x/r5_mpu.xs
+++ /dev/null
@@ -1,118 +0,0 @@
-/*
- * Copyright (c) 2020, Texas Instruments Incorporated
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * * Neither the name of Texas Instruments Incorporated nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
- * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
- * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
- * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
- * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-/*
- * ======== event_MPU.xs ========
- * MPU Settings for awr294x device's Cortex-R5F
- */
-
-/*
- * -------------------------------------------------------------------------------------------------------------
- * | Id | Base Address | Size | En | Cacheable | XN | AccPerm | Mask |
- * |-------------------------------------------------------------------------------------------------------------|
- * | 0 | 0x00000000 | 4GB | T | Strongly Ordered, Shareable | T | RW at PL 1 | 0x0 |
- * |----|--------------|------|----|-------------------------------------------|----|---------------------|------|
- * | 1 | 0x00000000 | 32K | T | Write-Back, Write-Allocate, Non-Shareable | F | RW at PL 1 | 0x0 |
- * |----|--------------|------|----|-------------------------------------------|----|---------------------|------|
- * | 2 | 0x00080000 | 32K | T | Write-Back, Write-Allocate, Non-Shareable | F | RW at PL 1 | 0x0 |
- * |----|--------------|------|----|-------------------------------------------|----|---------------------|------|
- * | 3 | 0x10200000 | 1M | T | Write-Back, Write-Allocate, Non-Shareable | F | RW at PL 1 | 0x0 |
- * |----|--------------|------|----|-------------------------------------------|----|---------------------|------|
- * | 4 | 0x88000000 | 4M | T | Write-Back, Write-Allocate, Non-Shareable | F | RW at PL 1 | 0x0 |
- * -------------------------------------------------------------------------------------------------------------
- */
-
-/*
- * Note: Marking a region as shareable will cause the region to behave as outer shareable with write through
- * no write-allocate caching policy irrespective of the actual cache policy set. Therefore, only select
- * regions that are actually shared outside the R5 CPUSS must be marked as shared.
- */
-
-var MPU = xdc.useModule('ti.sysbios.family.arm.MPU');
-MPU.enableMPU = true;
-MPU.enableBackgroundRegion = true;
-
-var attrs = new MPU.RegionAttrs();
-MPU.initRegionAttrsMeta(attrs);
-
-attrs.enable = true;
-attrs.bufferable = false;
-attrs.cacheable = false;
-attrs.shareable = true;
-attrs.noExecute = true;
-attrs.accPerm = 1; /* RW at PL1 */
-attrs.tex = 0;
-attrs.subregionDisableMask = 0;
-MPU.setRegionMeta(0, 0x00000000, MPU.RegionSize_4G, attrs);
-
-/* TCMA */
-attrs.enable = true;
-attrs.bufferable = true;
-attrs.cacheable = true;
-attrs.shareable = false;
-attrs.noExecute = false;
-attrs.accPerm = 1; /* RW at PL1 */
-attrs.tex = 1;
-attrs.subregionDisableMask = 0;
-MPU.setRegionMeta(1, 0x00000000, MPU.RegionSize_32K, attrs);
-
-/* TCMB */
-attrs.enable = true;
-attrs.bufferable = true;
-attrs.cacheable = true;
-attrs.shareable = false;
-attrs.noExecute = false;
-attrs.accPerm = 1; /* RW at PL1 */
-attrs.tex = 1;
-attrs.subregionDisableMask = 0;
-MPU.setRegionMeta(2, 0x00080000, MPU.RegionSize_32K, attrs);
-
-/* L2 */
-attrs.enable = true;
-attrs.bufferable = true;
-attrs.cacheable = true;
-attrs.shareable = false;
-attrs.noExecute = false;
-attrs.accPerm = 1; /* RW at PL1 */
-attrs.tex = 1;
-attrs.subregionDisableMask = 0;
-MPU.setRegionMeta(3, 0x10200000, MPU.RegionSize_1M, attrs);
-
-/* L3 */
-attrs.enable = true;
-attrs.bufferable = true;
-attrs.cacheable = true;
-attrs.shareable = false;
-attrs.noExecute = false;
-attrs.accPerm = 1; /* RW at PL1 */
-attrs.tex = 1;
-attrs.subregionDisableMask = 0;
-MPU.setRegionMeta(4, 0x88000000, MPU.RegionSize_4M, attrs);
diff --git a/packages/ti/build/awr294x/sysbios_c66.cfg b/packages/ti/build/awr294x/sysbios_c66.cfg
+++ /dev/null
@@ -1,90 +0,0 @@
-/* =============================================================================
- * Copyright (c) Texas Instruments Incorporated 2020
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the
- * distribution.
- *
- * Neither the name of Texas Instruments Incorporated nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-environment['xdc.cfg.check.fatal'] = 'false';
-
-/********************************************************************
- ************************** BIOS Modules ****************************
- ********************************************************************/
-var Memory = xdc.useModule('xdc.runtime.Memory');
-var BIOS = xdc.useModule('ti.sysbios.BIOS');
-var HeapMem = xdc.useModule('ti.sysbios.heaps.HeapMem');
-var HeapBuf = xdc.useModule('ti.sysbios.heaps.HeapBuf');
-var Task = xdc.useModule('ti.sysbios.knl.Task');
-var Idle = xdc.useModule('ti.sysbios.knl.Idle');
-var SEM = xdc.useModule('ti.sysbios.knl.Semaphore');
-var Event = xdc.useModule('ti.sysbios.knl.Event');
-var System = xdc.useModule('xdc.runtime.System');
-var SysStd = xdc.useModule('xdc.runtime.SysStd');
-var SysMin = xdc.useModule('xdc.runtime.SysMin');
-var Timestamp = xdc.useModule('xdc.runtime.Timestamp');
-var Hwi = xdc.useModule('ti.sysbios.family.c64p.Hwi');
-var EventCombiner = xdc.useModule('ti.sysbios.family.c64p.EventCombiner');
-var GateMutexPri = xdc.useModule('ti.sysbios.gates.GateMutexPri');
-
-/* Enable Timer */
-var Timer = xdc.useModule('ti.sysbios.timers.rti.Timer');
-
-/*
- * for (var i=0; i < Timer.numTimerDevices; i++) {
- * Timer.intFreqs[i].lo = 200000000;
- * Timer.intFreqs[i].hi = 0;
- *}
-*/
-SysMin.bufSize = 16 * 1024;
-SysMin.flushAtExit = false;
-System.SupportProxy = SysMin;
-
-/* Default Heap Creation: Local L2 memory */
-var heapMemParams = new HeapMem.Params();
-heapMemParams.size = 32*1024;
-Program.global.heap0 = HeapMem.create(heapMemParams);
-Memory.defaultHeapInstance = Program.global.heap0;
-
-/* Remove clock while we are profiling for cycles and don't want BIOS
- periodic interruption */
-BIOS.clockEnabled = true;
-
-/* Enable BIOS Task Scheduler */
-BIOS.taskEnabled = true;
-
-
-BIOS.cpuFreq.lo = 450000000;
-BIOS.cpuFreq.hi = 0;
-
-
-/* Check if application needs to update with custom configuration options */
-var cfgUpdate = java.lang.System.getenv("XDC_CFG_UPDATE")
-if ((cfgUpdate != '')&&(cfgUpdate != null))
-{
- xdc.print("Loading configuration update " + cfgUpdate);
- xdc.loadCapsule(cfgUpdate);
-}
diff --git a/packages/ti/build/awr294x/sysbios_r5f.cfg b/packages/ti/build/awr294x/sysbios_r5f.cfg
+++ /dev/null
@@ -1,138 +0,0 @@
-/* =============================================================================
- * Copyright (c) Texas Instruments Incorporated 2020
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the
- * distribution.
- *
- * Neither the name of Texas Instruments Incorporated nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-environment['xdc.cfg.check.fatal'] = 'false';
-
-/********************************************************************
- ************************** BIOS Modules ****************************
- ********************************************************************/
-var Memory = xdc.useModule('xdc.runtime.Memory');
-var BIOS = xdc.useModule('ti.sysbios.BIOS');
-var HeapMem = xdc.useModule('ti.sysbios.heaps.HeapMem');
-var HeapBuf = xdc.useModule('ti.sysbios.heaps.HeapBuf');
-var Task = xdc.useModule('ti.sysbios.knl.Task');
-var Idle = xdc.useModule('ti.sysbios.knl.Idle');
-var SEM = xdc.useModule('ti.sysbios.knl.Semaphore');
-var Event = xdc.useModule('ti.sysbios.knl.Event');
-var Hwi = xdc.useModule('ti.sysbios.family.arm.v7r.keystone3.Hwi');
-var Core = xdc.useModule('ti.sysbios.family.arm.v7r.keystone3.Core');
-var System = xdc.useModule('xdc.runtime.System');
-var SysStd = xdc.useModule('xdc.runtime.SysStd');
-var SysMin = xdc.useModule('xdc.runtime.SysMin');
-var Timestamp = xdc.useModule('xdc.runtime.Timestamp');
-var Pmu = xdc.useModule('ti.sysbios.family.arm.v7a.Pmu');
-var GateMutexPri = xdc.useModule('ti.sysbios.gates.GateMutexPri');
-
-/*
- * Initialize MPU and enable it
- *
- * Note: MPU must be enabled and properly configured for caching to work.
- */
-xdc.loadCapsule("r5_mpu.xs");
-
-/* Enable cache */
-var Cache = xdc.useModule('ti.sysbios.family.arm.v7r.Cache');
-Cache.enableCache = true;
-
-SysMin.bufSize = 16 * 1024;
-SysMin.flushAtExit = false;
-System.SupportProxy = SysMin;
-
-/* FIQ Stack Usage: */
-Hwi.fiqStackSize = 2048;
-Hwi.fiqStackSection = ".myFiqStack"
-
-/* Sysbios supports workaround for Silicon issue https://jira.itg.ti.com/browse/K3_OPEN_SI-148
- * Details of silicon issue : https://confluence.itg.ti.com/display/PROCIPDEV/%2310+The+same+interrupt+cannot+be+nested+back-2-back+within+another+interrupt
- * Sysbios Requirement Details: https://jira.itg.ti.com/browse/SYSBIOS-1419
- * Workaround requires use of a resevred dummyIRQ.
- * Using DummyIRQ#255 as per cslr_intr_mss.h it is a reserved interrupt not connected to any
- * peripheral interrupt sources
- */
-Hwi.dummyIRQ = 255;
-
-var coreId = java.lang.System.getenv("CORE");
-
-/* Set base address of Vector Interrupt Manager */
-if(coreId=="mcu1_0")
-{
- Core.id = 0;
- Hwi.vimBaseAddress = 0x02080000;
-}
-if(coreId=="mcu1_1")
-{
- Core.id = 1;
- Hwi.vimBaseAddress = 0x020A0000;
-}
-
-Program.sectMap[".myFiqStack"] = "TCMB_RAM";
-
-/* Default Heap Creation: Local L2 memory */
-var heapMemParams = new HeapMem.Params();
-heapMemParams.size = 32*1024;
-Program.global.heap0 = HeapMem.create(heapMemParams);
-Memory.defaultHeapInstance = Program.global.heap0;
-
-/* Enable Timer */
-var Timer = xdc.useModule('ti.sysbios.timers.rti.Timer');
-
-/*
- * for (var i=0; i < Timer.numTimerDevices; i++) {
- * Timer.intFreqs[i].lo = 200000000;
- * Timer.intFreqs[i].hi = 0;
- *}
-*/
-
-/* Remove clock while we are profiling for cycles and don't want BIOS
- periodic interruption. */
-BIOS.clockEnabled = true;
-
-/* Enable BIOS Task Scheduler */
-BIOS.taskEnabled = true;
-
-Program.sectMap[".vecs"] = "VECTORS";
-
-/* Make sure libraries are built with 32-bit enum types to be compatible with DSP enum types*/
-BIOS.includeXdcRuntime = true;
-BIOS.libType = BIOS.LibType_Custom;
-BIOS.customCCOpts += " --enum_type=int ";
-
-BIOS.cpuFreq.lo = 400000000;
-BIOS.cpuFreq.hi = 0;
-
-
-/* Check if application needs to update with custom configuration options */
-var cfgUpdate = java.lang.System.getenv("XDC_CFG_UPDATE")
-if ((cfgUpdate != '')&&(cfgUpdate != null))
-{
- xdc.print("Loading configuration update " + cfgUpdate);
- xdc.loadCapsule(cfgUpdate);
-}
diff --git a/packages/ti/build/dra7xx/linkcmd.xdt b/packages/ti/build/dra7xx/linkcmd.xdt
+++ /dev/null
@@ -1,52 +0,0 @@
-%/*
-% * ======== linkcmd.xdt ========
-% * This is template file illustrates how one can filter the linker command
-% * file that is normally generated from the template supplied by the
-% * executable's platform. This allows one to update the platform without
-% * having to update this file.
-% *
-% * This template is expanded after the configuration script runs and the
-% * results placed in a file (with extension .xdl) associated with the
-% * executable.
-% *
-% * Linker templates are passed the following arguments:
-% * $out - an open file stream for the generated linker
-% * command file
-% * $args - an array of zero or more libraries that should be linked
-% * with (in the order they appear in the argument list)
-% *
-% * These arguments are available via the standard Javascript arguments
-% * array; the first argument can also be accessed via the name "$out".
-% * In addition to these arguments, there is a global variable named
-% * 'this' that is set as follows:
-% * this - the program object
-% */
-%/* generate original command file from template into orig.xdl */
-%var tfile = this.platform.getLinkTemplate(this);
-%var template = xdc.loadTemplate(tfile);
-%template.genFile("orig.xdl", this, $args);
-%
-%/* read and output generated linker command file */
-%var line;
-//%var dir;
-%var file = new java.io.BufferedReader(java.io.FileReader("orig.xdl"));
-
-%while ((line = file.readLine()) != null)
-%{
- `String(line)`
-%}
-%/* Output the always required libraries to the linker command file */
-
-/* Provide virtual address locations for OCMC_RAM used by IPU applications
- * using AMMU.
- */
-MEMORY
-{
- /* OCMC_RAM1 mapped to 0x40300000 */
- OCMC_RAM1_VIRT: org = 0x00300000 len = 0x00040000
-%if (Program.build.cfgArgs.SOC.toLowerCase() == "dra75x")
-%{
- /* OCMC_RAM2 mapped to 0x40400000 */
- OCMC_RAM2_VIRT: org = 0x00400000 len = 0x00040000
-%}
-}
diff --git a/packages/ti/build/k2g/config_k2g_a15.bld b/packages/ti/build/k2g/config_k2g_a15.bld
+++ /dev/null
@@ -1,169 +0,0 @@
-/*
-* Copyright (c) 2016-2017, Texas Instruments Incorporated
-* All rights reserved.
-*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions
-* are met:
-*
-* * Redistributions of source code must retain the above copyright
-* notice, this list of conditions and the following disclaimer.
-*
-* * Redistributions in binary form must reproduce the above copyright
-* notice, this list of conditions and the following disclaimer in the
-* documentation and/or other materials provided with the distribution.
-*
-* * Neither the name of Texas Instruments Incorporated nor the names of
-* its contributors may be used to endorse or promote products derived
-* from this software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
-* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
-* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
-* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
-
-/*
- * ======== config_k2g_a15.bld ========
- * Build configuration script for BSP drivers
- */
-/* load the required modules for the configuration */
-var A15 = xdc.useModule('gnu.targets.arm.A15F');
-/* A15 compiler directory path */
-A15.rootDir = java.lang.System.getenv("CGTOOLS_A15");
-
-/* Read the current board */
-var CurrentPlatform = java.lang.System.getenv("BOARD");
-
-if (CurrentPlatform == null)
-{
- /* The env variable is probably not set while running inside CCS */
- CurrentPlatform = java.lang.System.getProperty("BOARD");
-}
-
-/*add bspLib to support SemiHosting to enable system_printf on A15*/
-/* GCC bare metal targets */
-var gccArmTargets = xdc.loadPackage('gnu.targets.arm');
-gccArmTargets.A15F.bspLib = "rdimon";
-
-/*
-Memory map
-
-DDR: 0x80000000 (Ist 512MB - Cached)
-
-NOTE: APP_CACHED_DATA_BLK1_MEM is used to route sections which needs to be in a
-separate section preferably at the end of 512 MB memory.
-For example:
-Frame buffer memory can be less at runtime depending on boards with lesser DDR (as in TDA 12x12 POP boards).
-If the same is routed to APP_CACHED_DATA_MEM section then the linker will
-place the frame buffer before other data section and the other data will fall into
-region outside the DDR in the board. Hence separate section is used!!
-
-+-----------------------------+
-| APP_CODE_MEM | 2MB
-+-----------------------------+
-| APP_CACHED_DATA_MEM | 20MB
-+-----------------------------+
-| APP_CACHED_DATA_BLK1_MEM | 244MB
-+-----------------------------+
-| APP_CACHED_DATA_BLK2_MEM | 128MB
-+-----------------------------+
-| NOT USED | Remaining MB
-+-----------------------------+
-
-DDR: 0xA0000000 (2nd 512MB - Non-Cached)
-+-----------------------------+
-| |
-| APP_UNCACHED_DATA_BLK3_MEM | 2MB
-+-----------------------------+
-| NOT USED | Remaining MB
-+-----------------------------+
-
-*/
-
-var KB=1024;
-var MB=KB*KB;
-
-var DDR3_ADDR_0;
-var DDR3_ADDR_1;
-
-var APP_CODE_ADDR;
-var APP_CODE_SIZE;
-
-var APP_CACHED_DATA_ADDR;
-var APP_CACHED_DATA_SIZE;
-
-var APP_UNCACHED_DATA_BLK3_ADDR;
-var APP_UNCACHED_DATA_BLK3_SIZE;
-
-var APP_CACHED_DATA_BLK1_ADDR;
-var APP_CACHED_DATA_BLK1_SIZE;
-
-var APP_CACHED_DATA_BLK2_ADDR;
-var APP_CACHED_DATA_BLK2_SIZE;
-
-/* First 4KB reserved for components such as SBL */
-SBL_SIZE = 4*KB;
-DDR3_ADDR_0 = 0x80000000 + SBL_SIZE;
-DDR3_ADDR_1 = 0xA0000000;
-
-APP_CODE_SIZE = 2*MB - SBL_SIZE;
-APP_CACHED_DATA_SIZE = 20*MB;
-APP_CACHED_DATA_BLK1_SIZE = 244*MB;
-APP_CACHED_DATA_BLK2_SIZE = 128*MB;
-APP_UNCACHED_DATA_BLK3_SIZE = 2*MB;
-
-APP_CODE_ADDR = DDR3_ADDR_0;
-APP_CACHED_DATA_ADDR = APP_CODE_ADDR + APP_CODE_SIZE;
-APP_CACHED_DATA_BLK1_ADDR = APP_CACHED_DATA_ADDR + APP_CACHED_DATA_SIZE;
-APP_CACHED_DATA_BLK2_ADDR = APP_CACHED_DATA_BLK1_ADDR + APP_CACHED_DATA_BLK1_SIZE;
-APP_UNCACHED_DATA_BLK3_ADDR = DDR3_ADDR_1;
-
-myplatform = "ti.platforms.evmTCI66AK2G02";
-
-Build.platformTable[myplatform] =
-{
- externalMemoryMap:
- [
- ["APP_CODE_MEM", {
- comment : "APP_CODE_MEM",
- name : "APP_CODE_MEM",
- base : APP_CODE_ADDR,
- len : APP_CODE_SIZE
- }],
- ["APP_CACHED_DATA_MEM", {
- comment : "APP_CACHED_DATA_MEM",
- name : "APP_CACHED_DATA_MEM",
- base : APP_CACHED_DATA_ADDR,
- len : APP_CACHED_DATA_SIZE
- }],
- ["APP_UNCACHED_DATA_BLK3_MEM", {
- comment : "APP_UNCACHED_DATA_BLK3_MEM",
- name : "APP_UNCACHED_DATA_BLK3_MEM",
- base : APP_UNCACHED_DATA_BLK3_ADDR,
- len : APP_UNCACHED_DATA_BLK3_SIZE
- }],
- ["APP_CACHED_DATA_BLK1_MEM", {
- comment : "APP_CACHED_DATA_BLK1_MEM",
- name : "APP_CACHED_DATA_BLK1_MEM",
- base : APP_CACHED_DATA_BLK1_ADDR,
- len : APP_CACHED_DATA_BLK1_SIZE
- }],
- ["APP_CACHED_DATA_BLK2_MEM", {
- comment : "APP_CACHED_DATA_BLK2_MEM",
- name : "APP_CACHED_DATA_BLK2_MEM",
- base : APP_CACHED_DATA_BLK2_ADDR,
- len : APP_CACHED_DATA_BLK2_SIZE
- }],
- ],
- codeMemory: "APP_CODE_MEM",
- dataMemory: "APP_CACHED_DATA_MEM",
- stackMemory: "APP_CACHED_DATA_MEM"
-};
diff --git a/packages/ti/build/k2g/config_k2g_c66.bld b/packages/ti/build/k2g/config_k2g_c66.bld
+++ /dev/null
@@ -1,166 +0,0 @@
-/*
-* Copyright (c) 2017, Texas Instruments Incorporated
-* All rights reserved.
-*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions
-* are met:
-*
-* * Redistributions of source code must retain the above copyright
-* notice, this list of conditions and the following disclaimer.
-*
-* * Redistributions in binary form must reproduce the above copyright
-* notice, this list of conditions and the following disclaimer in the
-* documentation and/or other materials provided with the distribution.
-*
-* * Neither the name of Texas Instruments Incorporated nor the names of
-* its contributors may be used to endorse or promote products derived
-* from this software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
-* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
-* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
-* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
-/*
- * ======== config.bld ========
- * Sample Build configuration script
- */
-
-/* load the required modules for the configuration */
-var C66 = xdc.useModule('ti.targets.elf.C66');
-/* C66 compiler directory path */
-C66.rootDir = java.lang.System.getenv("CGTOOLS_DSP");
-
-/* compiler options */
-C66.ccOpts.suffix += " -mi10 -mo ";
-
-var CurrentPlatform = java.lang.System.getenv("BOARD");
-
-if (CurrentPlatform == null)
-{
- /* The env variable is probably not set while running inside CCS */
- CurrentPlatform = java.lang.System.getProperty("BOARD");
-}
-
-/*
-Memory map
-
-DDR: 0x80000000 (Ist 512MB - Cached)
-
-NOTE: APP_CACHED_DATA_BLK1_MEM is used to route sections which needs to be in a
-separate section preferably at the end of 512 MB memory.
-For example:
-Frame buffer memory can be less at runtime depending on boards with lesser DDR (as in TDA 12x12 POP boards).
-If the same is routed to APP_CACHED_DATA_MEM section then the linker will
-place the frame buffer before other data section and the other data will fall into
-region outside the DDR in the board. Hence separate section is used!!
-
-+-----------------------------+
-| APP_CODE_MEM | 2MB
-+-----------------------------+
-| APP_CACHED_DATA_MEM | 20MB
-+-----------------------------+
-| APP_CACHED_DATA_BLK1_MEM | 244MB
-+-----------------------------+
-| APP_CACHED_DATA_BLK2_MEM | 128MB
-+-----------------------------+
-| NOT USED | Remaining MB
-+-----------------------------+
-
-DDR: 0xA0000000 (2nd 512MB - Non-Cached)
-+-----------------------------+
-| |
-| APP_UNCACHED_DATA_BLK3_MEM | 2MB
-+-----------------------------+
-| NOT USED | Remaining MB
-+-----------------------------+
-
-*/
-
-var KB=1024;
-var MB=KB*KB;
-
-var DDR3_ADDR_0;
-var DDR3_ADDR_1;
-
-var APP_CODE_ADDR;
-var APP_CODE_SIZE;
-
-var APP_CACHED_DATA_ADDR;
-var APP_CACHED_DATA_SIZE;
-
-var APP_UNCACHED_DATA_BLK3_ADDR;
-var APP_UNCACHED_DATA_BLK3_SIZE;
-
-var APP_CACHED_DATA_BLK1_ADDR;
-var APP_CACHED_DATA_BLK1_SIZE;
-
-var APP_CACHED_DATA_BLK2_ADDR;
-var APP_CACHED_DATA_BLK2_SIZE;
-
-/* First 4KB reserved for components such as SBL */
-SBL_SIZE = 4*KB;
-DDR3_ADDR_0 = 0x80000000 + SBL_SIZE;
-DDR3_ADDR_1 = 0xA0000000;
-
-APP_CODE_SIZE = 2*MB - SBL_SIZE;
-APP_CACHED_DATA_SIZE = 20*MB;
-APP_CACHED_DATA_BLK1_SIZE = 244*MB;
-APP_CACHED_DATA_BLK2_SIZE = 128*MB;
-APP_UNCACHED_DATA_BLK3_SIZE = 2*MB;
-
-APP_CODE_ADDR = DDR3_ADDR_0;
-APP_CACHED_DATA_ADDR = APP_CODE_ADDR + APP_CODE_SIZE;
-APP_CACHED_DATA_BLK1_ADDR = APP_CACHED_DATA_ADDR + APP_CACHED_DATA_SIZE;
-APP_CACHED_DATA_BLK2_ADDR = APP_CACHED_DATA_BLK1_ADDR + APP_CACHED_DATA_BLK1_SIZE;
-APP_UNCACHED_DATA_BLK3_ADDR = DDR3_ADDR_1;
-
-myplatform = "ti.platforms.evmTCI66AK2G02";
-
-Build.platformTable[myplatform] =
-{
- externalMemoryMap:
- [
- ["APP_CODE_MEM", {
- comment : "APP_CODE_MEM",
- name : "APP_CODE_MEM",
- base : APP_CODE_ADDR,
- len : APP_CODE_SIZE
- }],
- ["APP_CACHED_DATA_MEM", {
- comment : "APP_CACHED_DATA_MEM",
- name : "APP_CACHED_DATA_MEM",
- base : APP_CACHED_DATA_ADDR,
- len : APP_CACHED_DATA_SIZE
- }],
- ["APP_UNCACHED_DATA_BLK3_MEM", {
- comment : "APP_UNCACHED_DATA_BLK3_MEM",
- name : "APP_UNCACHED_DATA_BLK3_MEM",
- base : APP_UNCACHED_DATA_BLK3_ADDR,
- len : APP_UNCACHED_DATA_BLK3_SIZE
- }],
- ["APP_CACHED_DATA_BLK1_MEM", {
- comment : "APP_CACHED_DATA_BLK1_MEM",
- name : "APP_CACHED_DATA_BLK1_MEM",
- base : APP_CACHED_DATA_BLK1_ADDR,
- len : APP_CACHED_DATA_BLK1_SIZE
- }],
- ["APP_CACHED_DATA_BLK2_MEM", {
- comment : "APP_CACHED_DATA_BLK2_MEM",
- name : "APP_CACHED_DATA_BLK2_MEM",
- base : APP_CACHED_DATA_BLK2_ADDR,
- len : APP_CACHED_DATA_BLK2_SIZE
- }],
- ],
- codeMemory: "APP_CODE_MEM",
- dataMemory: "APP_CACHED_DATA_MEM",
- stackMemory: "APP_CACHED_DATA_MEM"
-};
diff --git a/packages/ti/build/omapl137/config_omapl137_arm9.bld b/packages/ti/build/omapl137/config_omapl137_arm9.bld
+++ /dev/null
@@ -1,188 +0,0 @@
-/*
-* Copyright (c) 2017-2019, Texas Instruments Incorporated
-* All rights reserved.
-*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions
-* are met:
-*
-* * Redistributions of source code must retain the above copyright
-* notice, this list of conditions and the following disclaimer.
-*
-* * Redistributions in binary form must reproduce the above copyright
-* notice, this list of conditions and the following disclaimer in the
-* documentation and/or other materials provided with the distribution.
-*
-* * Neither the name of Texas Instruments Incorporated nor the names of
-* its contributors may be used to endorse or promote products derived
-* from this software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
-* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
-* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
-* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
-
-/*
- * ======== config_omapl137_arm9.bld ========
- * Build configuration script for BSP drivers
- */
-/* load the required modules for the configuration */
-var ARM9 = xdc.useModule('ti.targets.arm.elf.Arm9');
-/* ARM9 compiler directory path */
-ARM9.rootDir = java.lang.System.getenv("CGTOOLS_ARM9");
-
-/* Read the current board */
-var CurrentPlatform = java.lang.System.getenv("BOARD");
-
-if (CurrentPlatform == null)
-{
- /* The env variable is probably not set while running inside CCS */
- CurrentPlatform = java.lang.System.getProperty("BOARD");
-}
-
-/*
-Memory map
-
-SDRAM: 0xC2000000 (16MB - Cached)
-
-NOTE: APP_CACHED_BIOS_RSVD is the SDRAM memory reserved by bios to share between ARM and DSP
-core. User can use this memory area without affecting the existing functionality.
-
-+------------------------------------------+
-| |
-| APP_CACHED_BIOS_RSVD | 16MB
-| |
-+------------------------------------------+
-
-SDRAM: 0xC3000000 (Ist 13MB - Cached)
-
-NOTE: APP_CACHED_DATA_BLK1_MEM is used to route sections which needs to be in a
-separate section preferably at the end of 13 MB memory.
-For example:
-Frame buffer memory can be less at runtime depending on boards with lesser DDR (as in TDA 12x12 POP boards).
-If the same is routed to APP_CACHED_DATA_MEM section then the linker will
-place the frame buffer before other data section and the other data will fall into
-region outside the DDR in the board. Hence separate section is used!!
-
-+-----------------------------+
-| APP_CODE_MEM | 2MB
-+-----------------------------+
-| APP_CACHED_DATA_MEM | 2MB
-+-----------------------------+
-| APP_CACHED_DATA_BLK1_MEM | 7MB
-+-----------------------------+
-| APP_CACHED_DATA_BLK2_MEM | 2MB
-+-----------------------------+
-
-SDRAM: 0xC3D00000 (2nd 3MB - Non-Cached)
-+-----------------------------+
-| |
-| APP_UNCACHED_DATA_BLK3_MEM | 2MB
-+-----------------------------+
-| NOT USED | Remaining MB
-+-----------------------------+
-
-*/
-
-var KB=1024;
-var MB=KB*KB;
-
-var SDRAM_ADDR_0;
-var SDRAM_ADDR_1;
-
-var APP_CODE_ADDR;
-var APP_CODE_SIZE;
-
-var APP_CACHED_DATA_ADDR;
-var APP_CACHED_DATA_SIZE;
-
-var APP_UNCACHED_DATA_BLK3_ADDR;
-var APP_UNCACHED_DATA_BLK3_SIZE;
-
-var APP_CACHED_DATA_BLK1_ADDR;
-var APP_CACHED_DATA_BLK1_SIZE;
-
-var APP_CACHED_DATA_BLK2_ADDR;
-var APP_CACHED_DATA_BLK2_SIZE;
-
-var APP_CACHED_BIOS_RSVD_ADDR;
-var APP_CACHED_BIOS_RSVD_SIZE;
-
-/* First 4KB reserved for components such as SBL */
-SBL_SIZE = 4*KB;
-SDRAM_ADDR_RSVD = 0xC2000000;
-SDRAM_ADDR_0 = 0xC3000000 + SBL_SIZE;
-SDRAM_ADDR_1 = 0xC3D00000;
-
-APP_CODE_SIZE = 2*MB - SBL_SIZE;
-APP_CACHED_DATA_SIZE = 4*MB;
-APP_CACHED_DATA_BLK1_SIZE = 4*MB;
-APP_CACHED_DATA_BLK2_SIZE = 2*MB;
-APP_UNCACHED_DATA_BLK3_SIZE = 2*MB;
-APP_CACHED_BIOS_RSVD_SIZE = 16*MB
-
-APP_CODE_ADDR = SDRAM_ADDR_0;
-APP_CACHED_DATA_ADDR = APP_CODE_ADDR + APP_CODE_SIZE;
-APP_CACHED_DATA_BLK1_ADDR = APP_CACHED_DATA_ADDR + APP_CACHED_DATA_SIZE;
-APP_CACHED_DATA_BLK2_ADDR = APP_CACHED_DATA_BLK1_ADDR + APP_CACHED_DATA_BLK1_SIZE;
-APP_UNCACHED_DATA_BLK3_ADDR = SDRAM_ADDR_1;
-APP_CACHED_BIOS_RSVD_ADDR = SDRAM_ADDR_RSVD;
-
-
-
-myplatform = "ti.platforms.evmOMAPL137";
-
-
-Build.platformTable[myplatform] =
-{
- externalMemoryMap:
- [
- ["APP_CODE_MEM", {
- comment : "APP_CODE_MEM",
- name : "APP_CODE_MEM",
- base : APP_CODE_ADDR,
- len : APP_CODE_SIZE
- }],
- ["APP_CACHED_DATA_MEM", {
- comment : "APP_CACHED_DATA_MEM",
- name : "APP_CACHED_DATA_MEM",
- base : APP_CACHED_DATA_ADDR,
- len : APP_CACHED_DATA_SIZE
- }],
- ["APP_UNCACHED_DATA_BLK3_MEM", {
- comment : "APP_UNCACHED_DATA_BLK3_MEM",
- name : "APP_UNCACHED_DATA_BLK3_MEM",
- base : APP_UNCACHED_DATA_BLK3_ADDR,
- len : APP_UNCACHED_DATA_BLK3_SIZE
- }],
- ["APP_CACHED_DATA_BLK1_MEM", {
- comment : "APP_CACHED_DATA_BLK1_MEM",
- name : "APP_CACHED_DATA_BLK1_MEM",
- base : APP_CACHED_DATA_BLK1_ADDR,
- len : APP_CACHED_DATA_BLK1_SIZE
- }],
- ["APP_CACHED_DATA_BLK2_MEM", {
- comment : "APP_CACHED_DATA_BLK2_MEM",
- name : "APP_CACHED_DATA_BLK2_MEM",
- base : APP_CACHED_DATA_BLK2_ADDR,
- len : APP_CACHED_DATA_BLK2_SIZE
- }],
- ["APP_CACHED_BIOS_RSVD_MEM", {
- comment : "APP_CACHED_BIOS_RSVD_MEM",
- name : "APP_CACHED_BIOS_RSVD_MEM",
- base : APP_CACHED_BIOS_RSVD_ADDR,
- len : APP_CACHED_BIOS_RSVD_SIZE
- }],
- ],
- codeMemory: "APP_CODE_MEM",
- dataMemory: "APP_CACHED_DATA_MEM",
- stackMemory: "APP_CACHED_DATA_MEM"
-};
diff --git a/packages/ti/build/omapl137/config_omapl137_c674x.bld b/packages/ti/build/omapl137/config_omapl137_c674x.bld
+++ /dev/null
@@ -1,188 +0,0 @@
-/*
-* Copyright (c) 2017-2019, Texas Instruments Incorporated
-* All rights reserved.
-*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions
-* are met:
-*
-* * Redistributions of source code must retain the above copyright
-* notice, this list of conditions and the following disclaimer.
-*
-* * Redistributions in binary form must reproduce the above copyright
-* notice, this list of conditions and the following disclaimer in the
-* documentation and/or other materials provided with the distribution.
-*
-* * Neither the name of Texas Instruments Incorporated nor the names of
-* its contributors may be used to endorse or promote products derived
-* from this software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
-* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
-* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
-* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
-
-/*
- * ======== config_omapl137_c674x.bld ========
- * Build configuration script for BSP drivers
- */
-/* load the required modules for the configuration */
-var C67x = xdc.useModule('ti.targets.elf.C674');
-/* C67x compiler directory path */
-C67x.rootDir = java.lang.System.getenv("CGTOOLS_DSP");
-
-/* Read the current board */
-var CurrentPlatform = java.lang.System.getenv("BOARD");
-
-if (CurrentPlatform == null)
-{
- /* The env variable is probably not set while running inside CCS */
- CurrentPlatform = java.lang.System.getProperty("BOARD");
-}
-
-/*
-Memory map
-
-SDRAM: 0xC2000000 (16MB - Cached)
-
-NOTE: APP_CACHED_BIOS_RSVD is the SDRAM memory reserved by bios to share between ARM and DSP
-core. User can use this memory area without affecting the existing functionality.
-
-+------------------------------------------+
-| |
-| APP_CACHED_BIOS_RSVD | 16MB
-| |
-+------------------------------------------+
-
-SDRAM: 0xC3000000 (Ist 13MB - Cached)
-
-NOTE: APP_CACHED_DATA_BLK1_MEM is used to route sections which needs to be in a
-separate section preferably at the end of 13 MB memory.
-For example:
-Frame buffer memory can be less at runtime depending on boards with lesser DDR (as in TDA 12x12 POP boards).
-If the same is routed to APP_CACHED_DATA_MEM section then the linker will
-place the frame buffer before other data section and the other data will fall into
-region outside the DDR in the board. Hence separate section is used!!
-
-+-----------------------------+
-| APP_CODE_MEM | 2MB
-+-----------------------------+
-| APP_CACHED_DATA_MEM | 2MB
-+-----------------------------+
-| APP_CACHED_DATA_BLK1_MEM | 7MB
-+-----------------------------+
-| APP_CACHED_DATA_BLK2_MEM | 2MB
-+-----------------------------+
-
-SDRAM: 0xC3D00000 (2nd 3MB - Non-Cached)
-+-----------------------------+
-| |
-| APP_UNCACHED_DATA_BLK3_MEM | 2MB
-+-----------------------------+
-| NOT USED | Remaining MB
-+-----------------------------+
-
-*/
-
-var KB=1024;
-var MB=KB*KB;
-
-var SDRAM_ADDR_0;
-var SDRAM_ADDR_1;
-
-var APP_CODE_ADDR;
-var APP_CODE_SIZE;
-
-var APP_CACHED_DATA_ADDR;
-var APP_CACHED_DATA_SIZE;
-
-var APP_UNCACHED_DATA_BLK3_ADDR;
-var APP_UNCACHED_DATA_BLK3_SIZE;
-
-var APP_CACHED_DATA_BLK1_ADDR;
-var APP_CACHED_DATA_BLK1_SIZE;
-
-var APP_CACHED_DATA_BLK2_ADDR;
-var APP_CACHED_DATA_BLK2_SIZE;
-
-var APP_CACHED_BIOS_RSVD_ADDR;
-var APP_CACHED_BIOS_RSVD_SIZE;
-
-/* First 4KB reserved for components such as SBL */
-SBL_SIZE = 4*KB;
-SDRAM_ADDR_RSVD = 0xC2000000;
-SDRAM_ADDR_0 = 0xC3000000 + SBL_SIZE;
-SDRAM_ADDR_1 = 0xC3D00000;
-
-APP_CODE_SIZE = 2*MB - SBL_SIZE;
-APP_CACHED_DATA_SIZE = 4*MB;
-APP_CACHED_DATA_BLK1_SIZE = 4*MB;
-APP_CACHED_DATA_BLK2_SIZE = 2*MB;
-APP_UNCACHED_DATA_BLK3_SIZE = 2*MB;
-APP_CACHED_BIOS_RSVD_SIZE = 16*MB
-
-APP_CODE_ADDR = SDRAM_ADDR_0;
-APP_CACHED_DATA_ADDR = APP_CODE_ADDR + APP_CODE_SIZE;
-APP_CACHED_DATA_BLK1_ADDR = APP_CACHED_DATA_ADDR + APP_CACHED_DATA_SIZE;
-APP_CACHED_DATA_BLK2_ADDR = APP_CACHED_DATA_BLK1_ADDR + APP_CACHED_DATA_BLK1_SIZE;
-APP_UNCACHED_DATA_BLK3_ADDR = SDRAM_ADDR_1;
-APP_CACHED_BIOS_RSVD_ADDR = SDRAM_ADDR_RSVD;
-
-
-
-myplatform = "ti.platforms.evmOMAPL137";
-
-
-Build.platformTable[myplatform] =
-{
- externalMemoryMap:
- [
- ["APP_CODE_MEM", {
- comment : "APP_CODE_MEM",
- name : "APP_CODE_MEM",
- base : APP_CODE_ADDR,
- len : APP_CODE_SIZE
- }],
- ["APP_CACHED_DATA_MEM", {
- comment : "APP_CACHED_DATA_MEM",
- name : "APP_CACHED_DATA_MEM",
- base : APP_CACHED_DATA_ADDR,
- len : APP_CACHED_DATA_SIZE
- }],
- ["APP_UNCACHED_DATA_BLK3_MEM", {
- comment : "APP_UNCACHED_DATA_BLK3_MEM",
- name : "APP_UNCACHED_DATA_BLK3_MEM",
- base : APP_UNCACHED_DATA_BLK3_ADDR,
- len : APP_UNCACHED_DATA_BLK3_SIZE
- }],
- ["APP_CACHED_DATA_BLK1_MEM", {
- comment : "APP_CACHED_DATA_BLK1_MEM",
- name : "APP_CACHED_DATA_BLK1_MEM",
- base : APP_CACHED_DATA_BLK1_ADDR,
- len : APP_CACHED_DATA_BLK1_SIZE
- }],
- ["APP_CACHED_DATA_BLK2_MEM", {
- comment : "APP_CACHED_DATA_BLK2_MEM",
- name : "APP_CACHED_DATA_BLK2_MEM",
- base : APP_CACHED_DATA_BLK2_ADDR,
- len : APP_CACHED_DATA_BLK2_SIZE
- }],
- ["APP_CACHED_BIOS_RSVD_MEM", {
- comment : "APP_CACHED_BIOS_RSVD_MEM",
- name : "APP_CACHED_BIOS_RSVD_MEM",
- base : APP_CACHED_BIOS_RSVD_ADDR,
- len : APP_CACHED_BIOS_RSVD_SIZE
- }],
- ],
- codeMemory: "APP_CODE_MEM",
- dataMemory: "APP_CACHED_DATA_MEM",
- stackMemory: "APP_CACHED_DATA_MEM"
-};
diff --git a/packages/ti/build/omapl138/config_omapl138_arm9.bld b/packages/ti/build/omapl138/config_omapl138_arm9.bld
+++ /dev/null
@@ -1,185 +0,0 @@
-/*
-* Copyright (c) 2017-2019, Texas Instruments Incorporated
-* All rights reserved.
-*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions
-* are met:
-*
-* * Redistributions of source code must retain the above copyright
-* notice, this list of conditions and the following disclaimer.
-*
-* * Redistributions in binary form must reproduce the above copyright
-* notice, this list of conditions and the following disclaimer in the
-* documentation and/or other materials provided with the distribution.
-*
-* * Neither the name of Texas Instruments Incorporated nor the names of
-* its contributors may be used to endorse or promote products derived
-* from this software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
-* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
-* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
-* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
-
-/*
- * ======== config_omapl138_arm9.bld ========
- * Build configuration script for BSP drivers
- */
-/* load the required modules for the configuration */
-var ARM9 = xdc.useModule('ti.targets.arm.elf.Arm9');
-/* ARM9 compiler directory path */
-ARM9.rootDir = java.lang.System.getenv("CGTOOLS_ARM9");
-
-/* Read the current board */
-var CurrentPlatform = java.lang.System.getenv("BOARD");
-
-if (CurrentPlatform == null)
-{
- /* The env variable is probably not set while running inside CCS */
- CurrentPlatform = java.lang.System.getProperty("BOARD");
-}
-
-/*
-Memory map
-
-DDR: 0xC2000000 (16MB - Cached)
-
-NOTE: APP_CACHED_BIOS_RSVD is the DDR memory reserved by bios to share between ARM and DSP
-core. User can use this memory area without affecting the existing functionality.
-
-+------------------------------------------+
-| |
-| APP_CACHED_BIOS_RSVD | 16MB
-| |
-+------------------------------------------+
-
-DDR: 0xC3000000 (Ist 13MB - Cached)
-
-NOTE: APP_CACHED_DATA_BLK1_MEM is used to route sections which needs to be in a
-separate section preferably at the end of 13 MB memory.
-For example:
-Frame buffer memory can be less at runtime depending on boards with lesser DDR (as in TDA 12x12 POP boards).
-If the same is routed to APP_CACHED_DATA_MEM section then the linker will
-place the frame buffer before other data section and the other data will fall into
-region outside the DDR in the board. Hence separate section is used!!
-
-+-----------------------------+
-| APP_CODE_MEM | 2MB
-+-----------------------------+
-| APP_CACHED_DATA_MEM | 2MB
-+-----------------------------+
-| APP_CACHED_DATA_BLK1_MEM | 7MB
-+-----------------------------+
-| APP_CACHED_DATA_BLK2_MEM | 2MB
-+-----------------------------+
-
-DDR: 0xC3D00000 (2nd 3MB - Non-Cached)
-+-----------------------------+
-| |
-| APP_UNCACHED_DATA_BLK3_MEM | 2MB
-+-----------------------------+
-| NOT USED | Remaining MB
-+-----------------------------+
-
-*/
-
-var KB=1024;
-var MB=KB*KB;
-
-var DDR_ADDR_0;
-var DDR_ADDR_1;
-
-var APP_CODE_ADDR;
-var APP_CODE_SIZE;
-
-var APP_CACHED_DATA_ADDR;
-var APP_CACHED_DATA_SIZE;
-
-var APP_UNCACHED_DATA_BLK3_ADDR;
-var APP_UNCACHED_DATA_BLK3_SIZE;
-
-var APP_CACHED_DATA_BLK1_ADDR;
-var APP_CACHED_DATA_BLK1_SIZE;
-
-var APP_CACHED_DATA_BLK2_ADDR;
-var APP_CACHED_DATA_BLK2_SIZE;
-
-/* First 4KB reserved for components such as SBL */
-SBL_SIZE = 4*KB;
-DDR2_ADDR_RSVD = 0xC2000000;
-DDR2_ADDR_0 = 0xC3000000 + SBL_SIZE;
-DDR2_ADDR_1 = 0xC3D00000;
-
-APP_CODE_SIZE = 2*MB - SBL_SIZE;
-APP_CACHED_DATA_SIZE = 4*MB;
-APP_CACHED_DATA_BLK1_SIZE = 4*MB;
-APP_CACHED_DATA_BLK2_SIZE = 2*MB;
-APP_UNCACHED_DATA_BLK3_SIZE = 2*MB;
-APP_CACHED_BIOS_RSVD_SIZE = 16*MB
-
-APP_CODE_ADDR = DDR2_ADDR_0;
-APP_CACHED_DATA_ADDR = APP_CODE_ADDR + APP_CODE_SIZE;
-APP_CACHED_DATA_BLK1_ADDR = APP_CACHED_DATA_ADDR + APP_CACHED_DATA_SIZE;
-APP_CACHED_DATA_BLK2_ADDR = APP_CACHED_DATA_BLK1_ADDR + APP_CACHED_DATA_BLK1_SIZE;
-APP_UNCACHED_DATA_BLK3_ADDR = DDR2_ADDR_1;
-APP_CACHED_BIOS_RSVD_ADDR = DDR2_ADDR_RSVD;
-
-
-
-myplatform = "ti.platforms.evmOMAPL138";
-
-
-Build.platformTable[myplatform] =
-{
- externalMemoryMap:
- [
- ["APP_CODE_MEM", {
- comment : "APP_CODE_MEM",
- name : "APP_CODE_MEM",
- base : APP_CODE_ADDR,
- len : APP_CODE_SIZE
- }],
- ["APP_CACHED_DATA_MEM", {
- comment : "APP_CACHED_DATA_MEM",
- name : "APP_CACHED_DATA_MEM",
- base : APP_CACHED_DATA_ADDR,
- len : APP_CACHED_DATA_SIZE
- }],
- ["APP_UNCACHED_DATA_BLK3_MEM", {
- comment : "APP_UNCACHED_DATA_BLK3_MEM",
- name : "APP_UNCACHED_DATA_BLK3_MEM",
- base : APP_UNCACHED_DATA_BLK3_ADDR,
- len : APP_UNCACHED_DATA_BLK3_SIZE
- }],
- ["APP_CACHED_DATA_BLK1_MEM", {
- comment : "APP_CACHED_DATA_BLK1_MEM",
- name : "APP_CACHED_DATA_BLK1_MEM",
- base : APP_CACHED_DATA_BLK1_ADDR,
- len : APP_CACHED_DATA_BLK1_SIZE
- }],
- ["APP_CACHED_DATA_BLK2_MEM", {
- comment : "APP_CACHED_DATA_BLK2_MEM",
- name : "APP_CACHED_DATA_BLK2_MEM",
- base : APP_CACHED_DATA_BLK2_ADDR,
- len : APP_CACHED_DATA_BLK2_SIZE
- }],
- ["APP_CACHED_BIOS_RSVD_MEM", {
- comment : "APP_CACHED_BIOS_RSVD_MEM",
- name : "APP_CACHED_BIOS_RSVD_MEM",
- base : APP_CACHED_BIOS_RSVD_ADDR,
- len : APP_CACHED_BIOS_RSVD_SIZE
- }],
- ],
- codeMemory: "APP_CODE_MEM",
- dataMemory: "APP_CACHED_DATA_MEM",
- stackMemory: "APP_CACHED_DATA_MEM"
-};
diff --git a/packages/ti/build/omapl138/config_omapl138_c674x.bld b/packages/ti/build/omapl138/config_omapl138_c674x.bld
+++ /dev/null
@@ -1,185 +0,0 @@
-/*
-* Copyright (c) 2017-2019, Texas Instruments Incorporated
-* All rights reserved.
-*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions
-* are met:
-*
-* * Redistributions of source code must retain the above copyright
-* notice, this list of conditions and the following disclaimer.
-*
-* * Redistributions in binary form must reproduce the above copyright
-* notice, this list of conditions and the following disclaimer in the
-* documentation and/or other materials provided with the distribution.
-*
-* * Neither the name of Texas Instruments Incorporated nor the names of
-* its contributors may be used to endorse or promote products derived
-* from this software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
-* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
-* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
-* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
-
-/*
- * ======== config_omapl138_c674x.bld ========
- * Build configuration script for BSP drivers
- */
-/* load the required modules for the configuration */
-var C67x = xdc.useModule('ti.targets.elf.C674');
-/* C67x compiler directory path */
-C67x.rootDir = java.lang.System.getenv("CGTOOLS_DSP");
-
-/* Read the current board */
-var CurrentPlatform = java.lang.System.getenv("BOARD");
-
-if (CurrentPlatform == null)
-{
- /* The env variable is probably not set while running inside CCS */
- CurrentPlatform = java.lang.System.getProperty("BOARD");
-}
-
-/*
-Memory map
-
-DDR: 0xC2000000 (16MB - Cached)
-
-NOTE: APP_CACHED_BIOS_RSVD is the DDR memory reserved by bios to share between ARM and DSP
-core. User can use this memory area without affecting the existing functionality.
-
-+------------------------------------------+
-| |
-| APP_CACHED_BIOS_RSVD | 16MB
-| |
-+------------------------------------------+
-
-DDR: 0xC3000000 (Ist 13MB - Cached)
-
-NOTE: APP_CACHED_DATA_BLK1_MEM is used to route sections which needs to be in a
-separate section preferably at the end of 13 MB memory.
-For example:
-Frame buffer memory can be less at runtime depending on boards with lesser DDR (as in TDA 12x12 POP boards).
-If the same is routed to APP_CACHED_DATA_MEM section then the linker will
-place the frame buffer before other data section and the other data will fall into
-region outside the DDR in the board. Hence separate section is used!!
-
-+-----------------------------+
-| APP_CODE_MEM | 2MB
-+-----------------------------+
-| APP_CACHED_DATA_MEM | 2MB
-+-----------------------------+
-| APP_CACHED_DATA_BLK1_MEM | 7MB
-+-----------------------------+
-| APP_CACHED_DATA_BLK2_MEM | 2MB
-+-----------------------------+
-
-DDR: 0xC3D00000 (2nd 3MB - Non-Cached)
-+-----------------------------+
-| |
-| APP_UNCACHED_DATA_BLK3_MEM | 2MB
-+-----------------------------+
-| NOT USED | Remaining MB
-+-----------------------------+
-
-*/
-
-var KB=1024;
-var MB=KB*KB;
-
-var DDR_ADDR_0;
-var DDR_ADDR_1;
-
-var APP_CODE_ADDR;
-var APP_CODE_SIZE;
-
-var APP_CACHED_DATA_ADDR;
-var APP_CACHED_DATA_SIZE;
-
-var APP_UNCACHED_DATA_BLK3_ADDR;
-var APP_UNCACHED_DATA_BLK3_SIZE;
-
-var APP_CACHED_DATA_BLK1_ADDR;
-var APP_CACHED_DATA_BLK1_SIZE;
-
-var APP_CACHED_DATA_BLK2_ADDR;
-var APP_CACHED_DATA_BLK2_SIZE;
-
-/* First 4KB reserved for components such as SBL */
-SBL_SIZE = 4*KB;
-DDR2_ADDR_RSVD = 0xC2000000;
-DDR2_ADDR_0 = 0xC3000000 + SBL_SIZE;
-DDR2_ADDR_1 = 0xC3D00000;
-
-APP_CODE_SIZE = 2*MB - SBL_SIZE;
-APP_CACHED_DATA_SIZE = 4*MB;
-APP_CACHED_DATA_BLK1_SIZE = 4*MB;
-APP_CACHED_DATA_BLK2_SIZE = 2*MB;
-APP_UNCACHED_DATA_BLK3_SIZE = 2*MB;
-APP_CACHED_BIOS_RSVD_SIZE = 16*MB
-
-APP_CODE_ADDR = DDR2_ADDR_0;
-APP_CACHED_DATA_ADDR = APP_CODE_ADDR + APP_CODE_SIZE;
-APP_CACHED_DATA_BLK1_ADDR = APP_CACHED_DATA_ADDR + APP_CACHED_DATA_SIZE;
-APP_CACHED_DATA_BLK2_ADDR = APP_CACHED_DATA_BLK1_ADDR + APP_CACHED_DATA_BLK1_SIZE;
-APP_UNCACHED_DATA_BLK3_ADDR = DDR2_ADDR_1;
-APP_CACHED_BIOS_RSVD_ADDR = DDR2_ADDR_RSVD;
-
-
-
-myplatform = "ti.platforms.evmOMAPL138";
-
-
-Build.platformTable[myplatform] =
-{
- externalMemoryMap:
- [
- ["APP_CODE_MEM", {
- comment : "APP_CODE_MEM",
- name : "APP_CODE_MEM",
- base : APP_CODE_ADDR,
- len : APP_CODE_SIZE
- }],
- ["APP_CACHED_DATA_MEM", {
- comment : "APP_CACHED_DATA_MEM",
- name : "APP_CACHED_DATA_MEM",
- base : APP_CACHED_DATA_ADDR,
- len : APP_CACHED_DATA_SIZE
- }],
- ["APP_UNCACHED_DATA_BLK3_MEM", {
- comment : "APP_UNCACHED_DATA_BLK3_MEM",
- name : "APP_UNCACHED_DATA_BLK3_MEM",
- base : APP_UNCACHED_DATA_BLK3_ADDR,
- len : APP_UNCACHED_DATA_BLK3_SIZE
- }],
- ["APP_CACHED_DATA_BLK1_MEM", {
- comment : "APP_CACHED_DATA_BLK1_MEM",
- name : "APP_CACHED_DATA_BLK1_MEM",
- base : APP_CACHED_DATA_BLK1_ADDR,
- len : APP_CACHED_DATA_BLK1_SIZE
- }],
- ["APP_CACHED_DATA_BLK2_MEM", {
- comment : "APP_CACHED_DATA_BLK2_MEM",
- name : "APP_CACHED_DATA_BLK2_MEM",
- base : APP_CACHED_DATA_BLK2_ADDR,
- len : APP_CACHED_DATA_BLK2_SIZE
- }],
- ["APP_CACHED_BIOS_RSVD_MEM", {
- comment : "APP_CACHED_BIOS_RSVD_MEM",
- name : "APP_CACHED_BIOS_RSVD_MEM",
- base : APP_CACHED_BIOS_RSVD_ADDR,
- len : APP_CACHED_BIOS_RSVD_SIZE
- }],
- ],
- codeMemory: "APP_CODE_MEM",
- dataMemory: "APP_CACHED_DATA_MEM",
- stackMemory: "APP_CACHED_DATA_MEM"
-};
diff --git a/packages/ti/build/pruss/PRU0_REV1_to_ARM.cmd b/packages/ti/build/pruss/PRU0_REV1_to_ARM.cmd
+++ /dev/null
@@ -1,19 +0,0 @@
---host_image
---image
---host_image:target=ARM
---host_image:endianness=little
-
---host_image:hidden_symbols
---host_image:show=shared_buf
-
---exclude=.resource_table
-
-ROMS
-{
- PAGE 0:
- PRU0_REV1_IMEM: o=0x00000000 l=0x00002000
-
- PAGE 1:
- PRU0_REV1_DMEM: o=0x00000000 l=0x00002000
- PRU0_REV1_EXT: o=0x80000000 l=0x00001000
-}
diff --git a/packages/ti/build/pruss/PRU0_REV1_to_C66.cmd b/packages/ti/build/pruss/PRU0_REV1_to_C66.cmd
+++ /dev/null
@@ -1,19 +0,0 @@
---host_image
---image
---host_image:target=C6000
---host_image:endianness=little
-
---host_image:hidden_symbols
---host_image:show=shared_buf
-
---exclude=.resource_table
-
-ROMS
-{
- PAGE 0:
- PRU0_REV1_IMEM: o=0x00000000 l=0x00002000
-
- PAGE 1:
- PRU0_REV1_DMEM: o=0x00000000 l=0x00002000
- PRU0_REV1_EXT: o=0x80000000 l=0x00001000
-}
diff --git a/packages/ti/build/pruss/PRU0_REV2_to_ARM.cmd b/packages/ti/build/pruss/PRU0_REV2_to_ARM.cmd
+++ /dev/null
@@ -1,19 +0,0 @@
---host_image
---image
---host_image:target=ARM
---host_image:endianness=little
-
---host_image:hidden_symbols
---host_image:show=shared_buf
-
---exclude=.resource_table
-
-ROMS
-{
- PAGE 0:
- PRU0_REV2_IMEM: o=0x00000000 l=0x00002000
-
- PAGE 1:
- PRU0_REV2_DMEM: o=0x00000000 l=0x00002000
- PRU0_REV2_EXT: o=0x80000000 l=0x00001000
-}
diff --git a/packages/ti/build/pruss/PRU0_REV2_to_C66.cmd b/packages/ti/build/pruss/PRU0_REV2_to_C66.cmd
+++ /dev/null
@@ -1,19 +0,0 @@
---host_image
---image
---host_image:target=C6000
---host_image:endianness=little
-
---host_image:hidden_symbols
---host_image:show=shared_buf
-
---exclude=.resource_table
-
-ROMS
-{
- PAGE 0:
- PRU0_REV2_IMEM: o=0x00000000 l=0x00002000
-
- PAGE 1:
- PRU0_REV2_DMEM: o=0x00000000 l=0x00002000
- PRU0_REV2_EXT: o=0x80000000 l=0x00001000
-}
diff --git a/packages/ti/build/pruss/PRU1_REV1_to_ARM.cmd b/packages/ti/build/pruss/PRU1_REV1_to_ARM.cmd
+++ /dev/null
@@ -1,19 +0,0 @@
---host_image
---image
---host_image:target=ARM
---host_image:endianness=little
-
---host_image:hidden_symbols
---host_image:show=shared_buf
-
---exclude=.resource_table
-
-ROMS
-{
- PAGE 0:
- PRU1_REV1_IMEM: o=0x00000000 l=0x00002000
-
- PAGE 1:
- PRU1_REV1_DMEM: o=0x00000000 l=0x00002000
- PRU1_REV1_EXT: o=0x80000000 l=0x00001000
-}
diff --git a/packages/ti/build/pruss/PRU1_REV1_to_C66.cmd b/packages/ti/build/pruss/PRU1_REV1_to_C66.cmd
+++ /dev/null
@@ -1,19 +0,0 @@
---host_image
---image
---host_image:target=C6000
---host_image:endianness=little
-
---host_image:hidden_symbols
---host_image:show=shared_buf
-
---exclude=.resource_table
-
-ROMS
-{
- PAGE 0:
- PRU1_REV1_IMEM: o=0x00000000 l=0x00002000
-
- PAGE 1:
- PRU1_REV1_DMEM: o=0x00000000 l=0x00002000
- PRU1_REV1_EXT: o=0x80000000 l=0x00001000
-}
diff --git a/packages/ti/build/pruss/PRU1_REV2_to_ARM.cmd b/packages/ti/build/pruss/PRU1_REV2_to_ARM.cmd
+++ /dev/null
@@ -1,19 +0,0 @@
---host_image
---image
---host_image:target=ARM
---host_image:endianness=little
-
---host_image:hidden_symbols
---host_image:show=shared_buf
-
---exclude=.resource_table
-
-ROMS
-{
- PAGE 0:
- PRU1_REV2_IMEM: o=0x00000000 l=0x00002000
-
- PAGE 1:
- PRU1_REV2_DMEM: o=0x00000000 l=0x00002000
- PRU1_REV2_EXT: o=0x80000000 l=0x00001000
-}
diff --git a/packages/ti/build/pruss/PRU1_REV2_to_C66.cmd b/packages/ti/build/pruss/PRU1_REV2_to_C66.cmd
+++ /dev/null
@@ -1,19 +0,0 @@
---host_image
---image
---host_image:target=C6000
---host_image:endianness=little
-
---host_image:hidden_symbols
---host_image:show=shared_buf
-
---exclude=.resource_table
-
-ROMS
-{
- PAGE 0:
- PRU1_REV2_IMEM: o=0x00000000 l=0x00002000
-
- PAGE 1:
- PRU1_REV2_DMEM: o=0x00000000 l=0x00002000
- PRU1_REV2_EXT: o=0x80000000 l=0x00001000
-}
diff --git a/packages/ti/build/pruss/lnk_a8_a9_a15_REV1.cmd b/packages/ti/build/pruss/lnk_a8_a9_a15_REV1.cmd
+++ /dev/null
@@ -1,33 +0,0 @@
-
-/* SPECIFY THE SYSTEM MEMORY MAP */
-SECTIONS
-{
- PRU0_REV1_IMEM : {
- pru_imem0_rev1_start = .;
- KEEP(*(PRU0_REV1_IMEM))
- pru_imem0_rev1_end = .;
- } > APP_CACHED_DATA_BLK0_MEM
- PRU0_REV1_DMEM : {
- pru_dmem0_rev1_start = .;
- KEEP (*(PRU0_REV1_DMEM))
- pru_dmem0_rev1_end = .;
- } > APP_CACHED_DATA_BLK0_MEM
- PRU0_REV1_EXT : {
- KEEP (*(PRU0_REV1_EXT))
- } > APP_CACHED_DATA_BLK0_MEM
- PRU1_REV1_IMEM : {
- pru_imem1_rev1_start = .;
- KEEP (*(PRU1_REV1_IMEM))
- pru_imem1_rev1_end = .;
- } > APP_CACHED_DATA_BLK0_MEM
- PRU1_REV1_DMEM : {
- pru_dmem1_rev1_start = .;
- KEEP (*(PRU1_REV1_DMEM))
- pru_dmem1_rev1_end = .;
- } > APP_CACHED_DATA_BLK0_MEM
- PRU1_REV1_EXT : {
- KEEP (*(PRU1_REV1_EXT))
- } > APP_CACHED_DATA_BLK0_MEM
-}
-
-
diff --git a/packages/ti/build/pruss/lnk_a8_a9_a15_REV1_linux.cmd b/packages/ti/build/pruss/lnk_a8_a9_a15_REV1_linux.cmd
+++ /dev/null
@@ -1,33 +0,0 @@
-
-/* SPECIFY THE SYSTEM MEMORY MAP */
-SECTIONS
-{
- PRU0_REV1_IMEM : {
- pru_imem0_rev1_start = .;
- KEEP(*(PRU0_REV1_IMEM))
- pru_imem0_rev1_end = .;
- }
- PRU0_REV1_DMEM : {
- pru_dmem0_rev1_start = .;
- KEEP (*(PRU0_REV1_DMEM))
- pru_dmem0_rev1_end = .;
- }
- PRU0_REV1_EXT : {
- KEEP (*(PRU0_REV1_EXT))
- }
- PRU1_REV1_IMEM : {
- pru_imem1_rev1_start = .;
- KEEP (*(PRU1_REV1_IMEM))
- pru_imem1_rev1_end = .;
- }
- PRU1_REV1_DMEM : {
- pru_dmem1_rev1_start = .;
- KEEP (*(PRU1_REV1_DMEM))
- pru_dmem1_rev1_end = .;
- }
- PRU1_REV1_EXT : {
- KEEP (*(PRU1_REV1_EXT))
- }
-}
-
-
diff --git a/packages/ti/build/pruss/lnk_a8_a9_a15_REV2.cmd b/packages/ti/build/pruss/lnk_a8_a9_a15_REV2.cmd
+++ /dev/null
@@ -1,33 +0,0 @@
-
-/* SPECIFY THE SYSTEM MEMORY MAP */
-SECTIONS
-{
- PRU0_REV2_IMEM : {
- pru_imem0_rev2_start = .;
- KEEP(*(PRU0_REV2_IMEM))
- pru_imem0_rev2_end = .;
- } > APP_CACHED_DATA_BLK1_MEM
- PRU0_REV2_DMEM : {
- pru_dmem0_rev2_start = .;
- KEEP (*(PRU0_REV2_DMEM))
- pru_dmem0_rev2_end = .;
- } > APP_CACHED_DATA_BLK1_MEM
- PRU0_REV2_EXT : {
- KEEP (*(PRU0_REV2_EXT))
- } > APP_CACHED_DATA_BLK1_MEM
- PRU1_REV2_IMEM : {
- pru_imem1_rev2_start = .;
- KEEP (*(PRU1_REV2_IMEM))
- pru_imem1_rev2_end = .;
- } > APP_CACHED_DATA_BLK1_MEM
- PRU1_REV2_DMEM : {
- pru_dmem1_rev2_start = .;
- KEEP (*(PRU1_REV2_DMEM))
- pru_dmem1_rev2_end = .;
- } > APP_CACHED_DATA_BLK1_MEM
- PRU1_REV2_EXT : {
- KEEP (*(PRU1_REV2_EXT))
- } > APP_CACHED_DATA_BLK1_MEM
-}
-
-
diff --git a/packages/ti/build/pruss/lnk_a8_a9_a15_REV2_linux.cmd b/packages/ti/build/pruss/lnk_a8_a9_a15_REV2_linux.cmd
+++ /dev/null
@@ -1,33 +0,0 @@
-
-/* SPECIFY THE SYSTEM MEMORY MAP */
-SECTIONS
-{
- PRU0_REV2_IMEM : {
- pru_imem0_rev2_start = .;
- KEEP(*(PRU0_REV2_IMEM))
- pru_imem0_rev2_end = .;
- }
- PRU0_REV2_DMEM : {
- pru_dmem0_rev2_start = .;
- KEEP (*(PRU0_REV2_DMEM))
- pru_dmem0_rev2_end = .;
- }
- PRU0_REV2_EXT : {
- KEEP (*(PRU0_REV2_EXT))
- }
- PRU1_REV2_IMEM : {
- pru_imem1_rev2_start = .;
- KEEP (*(PRU1_REV2_IMEM))
- pru_imem1_rev2_end = .;
- }
- PRU1_REV2_DMEM : {
- pru_dmem1_rev2_start = .;
- KEEP (*(PRU1_REV2_DMEM))
- pru_dmem1_rev2_end = .;
- }
- PRU1_REV2_EXT : {
- KEEP (*(PRU1_REV2_EXT))
- }
-}
-
-
diff --git a/packages/ti/build/pruss/lnk_c66_m4_REV1.cmd b/packages/ti/build/pruss/lnk_c66_m4_REV1.cmd
+++ /dev/null
@@ -1,39 +0,0 @@
-
---retain="*(PRU0*)"
---retain="*(PRU1*)"
-
-
-/* SPECIFY THE SYSTEM MEMORY MAP */
-SECTIONS
-{
- PRU0_REV1_IMEM : {
- pru_imem0_rev1_start = .;
- *(PRU0_REV1_IMEM)
- pru_imem0_rev1_end = .;
- } > APP_CACHED_DATA_BLK1_MEM
- PRU0_REV1_DMEM : {
- pru_dmem0_rev1_start = .;
- *(PRU0_REV1_DMEM)
- pru_dmem0_rev1_end = .;
- } > APP_CACHED_DATA_BLK1_MEM
- PRU0_REV1_EXT : {
- *(PRU0_REV1_EXT)
- } > APP_CACHED_DATA_BLK1_MEM
- PRU1_REV1_IMEM : {
- pru_imem1_rev1_start = .;
- *(PRU1_REV1_IMEM)
- pru_imem1_rev1_end = .;
- } > APP_CACHED_DATA_BLK1_MEM
- PRU1_REV1_DMEM : {
- pru_dmem1_rev1_start = .;
- *(PRU1_REV1_DMEM)
- pru_dmem1_rev1_end = .;
- } > APP_CACHED_DATA_BLK1_MEM
- PRU1_REV1_EXT : {
- *(PRU1_REV1_EXT)
- } > APP_CACHED_DATA_BLK1_MEM
-}
-
-
-
-
diff --git a/packages/ti/build/pruss/lnk_c66_m4_REV2.cmd b/packages/ti/build/pruss/lnk_c66_m4_REV2.cmd
+++ /dev/null
@@ -1,39 +0,0 @@
-
---retain="*(PRU0*)"
---retain="*(PRU1*)"
-
-
-/* SPECIFY THE SYSTEM MEMORY MAP */
-SECTIONS
-{
- PRU0_REV2_IMEM : {
- pru_imem0_rev2_start = .;
- *(PRU0_REV2_IMEM)
- pru_imem0_rev2_end = .;
- } > APP_CACHED_DATA_BLK1_MEM
- PRU0_REV2_DMEM : {
- pru_dmem0_rev2_start = .;
- *(PRU0_REV2_DMEM)
- pru_dmem0_rev2_end = .;
- } > APP_CACHED_DATA_BLK1_MEM
- PRU0_REV2_EXT : {
- *(PRU0_REV2_EXT)
- } > APP_CACHED_DATA_BLK1_MEM
- PRU1_REV2_IMEM : {
- pru_imem1_rev2_start = .;
- *(PRU1_REV2_IMEM)
- pru_imem1_rev2_end = .;
- } > APP_CACHED_DATA_BLK1_MEM
- PRU1_REV2_DMEM : {
- pru_dmem1_rev2_start = .;
- *(PRU1_REV2_DMEM)
- pru_dmem1_rev2_end = .;
- } > APP_CACHED_DATA_BLK1_MEM
- PRU1_REV2_EXT : {
- *(PRU1_REV2_EXT)
- } > APP_CACHED_DATA_BLK1_MEM
-}
-
-
-
-
diff --git a/packages/ti/build/tda2ex/config_tda2ex.bld b/packages/ti/build/tda2ex/config_tda2ex.bld
+++ /dev/null
@@ -1,139 +0,0 @@
-/*
-* Copyright (c) 2016, Texas Instruments Incorporated
-* All rights reserved.
-*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions
-* are met:
-*
-* * Redistributions of source code must retain the above copyright
-* notice, this list of conditions and the following disclaimer.
-*
-* * Redistributions in binary form must reproduce the above copyright
-* notice, this list of conditions and the following disclaimer in the
-* documentation and/or other materials provided with the distribution.
-*
-* * Neither the name of Texas Instruments Incorporated nor the names of
-* its contributors may be used to endorse or promote products derived
-* from this software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
-* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
-* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
-* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
-
-/* load the required modules for the configuration */
-var M4 = xdc.useModule('ti.targets.arm.elf.M4');
-/* M4 compiler directory path */
-M4.rootDir = java.lang.System.getenv("CGTOOLS");
-
-/*
-Memory map
-
-DDR: 0x80000000 (Ist 512MB - Cached)
-
-NOTE: APP_CACHED_DATA_BLK1_MEM is used to route sections which needs to be in a
-separate section preferably at the end of 512 MB memory.
-For example:
-Frame buffer memory can be less at runtime depending on boards with lesser DDR (as in TDA 12x12 POP boards).
-If the same is routed to APP_CACHED_DATA_MEM section then the linker will
-place the frame buffer before other data section and the other data will fall into
-region outside the DDR in the board. Hence separate section is used!!
-
-+-----------------------------+
-| APP_CODE_MEM | 2MB
-+-----------------------------+
-| APP_CACHED_DATA_MEM | 8MB
-+-----------------------------+
-| |
-| APP_CACHED_DATA_BLK1_MEM | 246MB
-+-----------------------------+
-| NOT USED | Remaining MB
-+-----------------------------+
-
-DDR: 0xA0000000 (2nd 512MB - Non-Cached - but mapped to above 512MB physical)
-
-+-----------------------------+
-| Mirrored Section | 256 MB (from 0x80000000)
-+-----------------------------+
-| APP_UNCACHED_DATA_BLK3_MEM | 2MB
-+-----------------------------+
-| NOT USED | Remaining MB
-+-----------------------------+
-
-*/
-
-var KB=1024;
-var MB=KB*KB;
-
-var DDR3_ADDR_0;
-var DDR3_ADDR_1;
-
-var APP_CODE_ADDR;
-var APP_CODE_SIZE;
-
-var APP_CACHED_DATA_ADDR;
-var APP_CACHED_DATA_SIZE;
-
-var APP_CACHED_DATA_BLK1_ADDR;
-var APP_CACHED_DATA_BLK1_SIZE;
-
-var APP_UNCACHED_DATA_BLK3_ADDR;
-var APP_UNCACHED_DATA_BLK3_SIZE;
-
-/* First 4KB used by SBL */
-SBL_SIZE = 4*KB;
-DDR3_ADDR_0 = 0x80000000 + SBL_SIZE;
-DDR3_ADDR_1 = 0xA0000000 + SBL_SIZE;
-
-APP_CODE_SIZE = 2*MB - SBL_SIZE;
-APP_CACHED_DATA_SIZE = 12*MB;
-APP_CACHED_DATA_BLK1_SIZE = 242*MB;
-APP_UNCACHED_DATA_BLK3_SIZE = 2*MB;
-
-APP_CODE_ADDR = DDR3_ADDR_0;
-APP_CACHED_DATA_ADDR = APP_CODE_ADDR + APP_CODE_SIZE;
-APP_CACHED_DATA_BLK1_ADDR = APP_CACHED_DATA_ADDR + APP_CACHED_DATA_SIZE;
-APP_UNCACHED_DATA_BLK3_ADDR = DDR3_ADDR_1 + APP_CODE_SIZE + APP_CACHED_DATA_SIZE + APP_CACHED_DATA_BLK1_SIZE;
-
-Build.platformTable["ti.platforms.evmDRA7XX"] =
-{
- externalMemoryMap:
- [
- ["APP_CODE_MEM", {
- comment : "APP_CODE_MEM",
- name : "APP_CODE_MEM",
- base : APP_CODE_ADDR,
- len : APP_CODE_SIZE
- }],
- ["APP_CACHED_DATA_MEM", {
- comment : "APP_CACHED_DATA_MEM",
- name : "APP_CACHED_DATA_MEM",
- base : APP_CACHED_DATA_ADDR,
- len : APP_CACHED_DATA_SIZE
- }],
- ["APP_UNCACHED_DATA_BLK3_MEM", {
- comment : "APP_UNCACHED_DATA_BLK3_MEM",
- name : "APP_UNCACHED_DATA_BLK3_MEM",
- base : APP_UNCACHED_DATA_BLK3_ADDR,
- len : APP_UNCACHED_DATA_BLK3_SIZE
- }],
- ["APP_CACHED_DATA_BLK1_MEM", {
- comment : "APP_CACHED_DATA_BLK1_MEM",
- name : "APP_CACHED_DATA_BLK1_MEM",
- base : APP_CACHED_DATA_BLK1_ADDR,
- len : APP_CACHED_DATA_BLK1_SIZE
- }],
- ],
- codeMemory: "APP_CODE_MEM",
- dataMemory: "APP_CACHED_DATA_MEM",
- stackMemory: "APP_CACHED_DATA_MEM"
-};
diff --git a/packages/ti/build/tda2ex/config_tda2ex_a15.bld b/packages/ti/build/tda2ex/config_tda2ex_a15.bld
+++ /dev/null
@@ -1,44 +0,0 @@
-/*******************************************************************************
- * *
- * Copyright (c) 2014 Texas Instruments Incorporated - http://www.ti.com/ *
- * ALL RIGHTS RESERVED *
- * *
- ******************************************************************************/
-
-/*
- * ======== config_tda2ex_a15.bld ========
- */
-var MemSegDefine = xdc.loadCapsule("mem_segment_definition_1024mb_bios.xs");
-
-var CurrentCore = java.lang.System.getenv("CORE");
-var CurrentPlatform = java.lang.System.getenv("BOARD");
-xdc.print("# !!! Current build platform is [" + CurrentPlatform + "] !!!" );
-
-var Build = xdc.useModule('xdc.bld.BuildEnvironment');
-var A15 = xdc.useModule('gnu.targets.arm.A15F');
-var buildReleaseConfig = true;
-
-/*add bspLib to support SemiHosting to enable system_printf on A15*/
-/* GCC bare metal targets */
-var gccArmTargets = xdc.loadPackage('gnu.targets.arm');
-gccArmTargets.A15F.bspLib = "rdimon";
-
-A15.rootDir = java.lang.System.getenv("CGTOOLS_A15");
-A15.ccOpts.suffix +=
-A15.lnkOpts.suffix +=
-//set default platform and list of all interested platforms for A15
-A15.platforms = ["ti.platforms.evmDRA7XX:Cortex_A15",
- ];
-A15.platform = A15.platforms[0];
-
-Build.targets = [
- A15,
- ];
-
-Build.platformTable["ti.platforms.evmDRA7XX:Cortex_A15"] =
-{
- externalMemoryMap: MemSegDefine.getMemSegmentDefinition_external(CurrentCore),
- codeMemory:"A15_0_DATA_MEM",
- dataMemory:"A15_0_DATA_MEM",
- stackMemory:"A15_0_DATA_MEM"
-};
diff --git a/packages/ti/build/tda2ex/config_tda2ex_c66.bld b/packages/ti/build/tda2ex/config_tda2ex_c66.bld
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * ======== config.bld ========
- * Sample Build configuration script
- */
-
-/* load the required modules for the configuration */
-var C66 = xdc.useModule('ti.targets.elf.C66');
-
-
-/* compiler paths for the CCS4.0 */
-var rootDirPre = java.lang.System.getenv("CGTOOLS_DSP");
-var rootDirPost = "";
-
-/**********************************C66******************************/
-
-/* configure the options for the c66 targets */
-
-/* c66 compiler directory path */
-C66.rootDir = rootDirPre + rootDirPost;
-
-/* compiler options */
-C66.ccOpts.suffix += " -mi10 -mo ";
-
-/* set default platform and list of all interested *
- * platforms for C66 */
-
-C66.platforms = [
- "ti.platforms.evmDRA7XX",
-
- ];
-/* select the default platform */
-C66.platform = C66.platforms[0];
-
-
-/* list interested targets in Build.targets array */
-Build.targets = [
- C66,
- ];
diff --git a/packages/ti/build/tda2ex/mem_segment_definition_1024mb_bios.xs b/packages/ti/build/tda2ex/mem_segment_definition_1024mb_bios.xs
+++ /dev/null
@@ -1,238 +0,0 @@
-/*
- *******************************************************************************
- *
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
- * ALL RIGHTS RESERVED
- *
- *******************************************************************************
- */
-
-/*
- * ======== mem_segment_definition.xs ========
- * ======== Single file for the memory map configuration of all cores =========
- */
-
-KB=1024;
-MB=KB*KB;
-
-DDR3_ADDR = 0x80000000;
-DDR3_SIZE = 1024*MB;
-
-DDR3_BASE_ADDR_0 = 0x80000000;
-DDR3_BASE_SIZE_0 = 512*MB;
-
-/* The start address of the second mem section should be 16MB aligned.
- * for REMOTE_LOG_MEM sections.
- * tlb_config_eveX.c need to be modified otherwise
- */
-DDR3_BASE_ADDR_1 = 0xA0000000;
-DDR3_BASE_SIZE_1 = 512*MB;
-
-OCMC1_ADDR = 0x40300000;
-OCMC1_SIZE = 512*KB;
-
-DSP1_L2_SRAM_ADDR = 0x40800000;
-DSP1_L2_SRAM_SIZE = 288*KB;
-
-TOTAL_MEM_SIZE = (DDR3_SIZE);
-
-/* First 512 MB - cached */
-/* EVE vecs space should be align with 16MB boundary, and if possible try to fit
- * the entire vecs+code+data in 16MB section.
- * tlb_config_eveX.c need to be modified if any of these EVE memory sections or
- * SR1_FRAME_BUFFER_MEM section is modified.
- */
-IPU1_1_CODE_SIZE = 2*MB;
-IPU1_1_BSS_SIZE = 6*MB;
-IPU1_1_DATA_SIZE = 4*MB;
-IPU1_0_CODE_SIZE = 6*MB;
-IPU1_0_BSS_SIZE = 10*MB;
-IPU1_0_DATA_SIZE = 4*MB;
-SR1_FRAME_BUFFER_SIZE = 256*MB;
-DSP1_CODE_SIZE = 2*MB;
-DSP1_DATA_SIZE = 64*MB;
-/* A15_0_CODE_SIZE reduced since it is not used in .bld file.
- * Check .bld for details. Originally 2 + 14 MB.
- */
-A15_0_NDK_DATA_SIZE = 4*MB;
-A15_0_DATA_SIZE = 16*MB - A15_0_NDK_DATA_SIZE;
-
-
-
-/* Second 512 MB - non-cached */
-/* The start address of the second mem section should be 16MB aligned.
- * This alignment is a must as a single 16MB mapping is used for EMOTE_LOG_MEM sections.
- * tlb_config_eveX.c need to be modified otherwise
- */
-REMOTE_LOG_SIZE = 160*KB;
-SYSTEM_IPC_SHM_SIZE = 224*KB;
-LINK_STATS_SIZE = 256*KB;
-HDVPSS_DESC_SIZE = 1024*KB;
-SR0_SIZE = 128*KB;
-
-
-/* Cached Section */
-/* EVE vecs space should be align with 16MB boundary, and if possible try to fit
- * the entire vecs+code+data in 16MB section.
- * SR1_FRAME_BUFFER_MEM section is modified.
- */
-IPU1_1_CODE_ADDR = DDR3_BASE_ADDR_0;
-IPU1_1_DATA_ADDR = IPU1_1_CODE_ADDR + IPU1_1_CODE_SIZE;
-IPU1_1_BSS_ADDR = IPU1_1_DATA_ADDR + IPU1_1_DATA_SIZE;
-IPU1_0_CODE_ADDR = IPU1_1_BSS_ADDR + IPU1_1_BSS_SIZE;
-IPU1_0_DATA_ADDR = IPU1_0_CODE_ADDR + IPU1_0_CODE_SIZE;
-IPU1_0_BSS_ADDR = IPU1_0_DATA_ADDR + IPU1_0_DATA_SIZE;
-SR1_FRAME_BUFFER_ADDR = IPU1_0_BSS_ADDR + IPU1_0_BSS_SIZE;
-DSP1_CODE_ADDR = SR1_FRAME_BUFFER_ADDR + SR1_FRAME_BUFFER_SIZE;
-DSP1_DATA_ADDR = DSP1_CODE_ADDR + DSP1_CODE_SIZE;
-A15_0_NDK_DATA_ADDR = DSP1_DATA_ADDR + DSP1_DATA_SIZE;
-A15_0_DATA_ADDR = A15_0_NDK_DATA_ADDR + A15_0_NDK_DATA_SIZE;
-
-
-/* Non Cached Section */
-/* The start address of the second mem section should be 16MB aligned.
- * This alignment is a must as a single 16MB mapping is used for EMOTE_LOG_MEM sections.
- * tlb_config_eveX.c need to be modified otherwise
- */
-SR0_ADDR = DDR3_BASE_ADDR_1;
-REMOTE_LOG_ADDR = SR0_ADDR + SR0_SIZE;
-LINK_STATS_ADDR = REMOTE_LOG_ADDR + REMOTE_LOG_SIZE;
-SYSTEM_IPC_SHM_ADDR = LINK_STATS_ADDR + LINK_STATS_SIZE;
-HDVPSS_DESC_ADDR = SYSTEM_IPC_SHM_ADDR + SYSTEM_IPC_SHM_SIZE;
-
-if ((A15_0_DATA_ADDR + A15_0_DATA_SIZE) > (DDR3_BASE_ADDR_0 + DDR3_BASE_SIZE_0))
-{
- throw xdc.$$XDCException("MEMORY_MAP OVERFLOW ERROR ",
- "\nRegion End: " + "0x" + java.lang.Long.toHexString(DDR3_BASE_ADDR_0 + DDR3_BASE_SIZE_0) +
- "\nActual End: " + "0x" + java.lang.Long.toHexString(A15_0_DATA_ADDR + A15_0_DATA_SIZE));
-}
-
-if ((HDVPSS_DESC_ADDR + HDVPSS_DESC_SIZE) > (DDR3_BASE_ADDR_1 + DDR3_BASE_SIZE_1))
-{
- throw xdc.$$XDCException("MEMORY_MAP OVERFLOW ERROR ",
- "\nRegion End: " + "0x" + java.lang.Long.toHexString(DDR3_BASE_ADDR_1 + DDR3_BASE_SIZE_1) +
- "\nActual End: " + "0x" + java.lang.Long.toHexString(HDVPSS_DESC_ADDR + HDVPSS_DESC_SIZE));
-}
-
-if ((DDR3_BASE_SIZE_1 + DDR3_BASE_SIZE_0) > (TOTAL_MEM_SIZE))
-{
- throw xdc.$$XDCException("MEMORY_MAP EXCEEDS DDR SIZE ERROR ",
- "\nRegion End: " + "0x" + java.lang.Long.toHexString(DDR3_BASE_SIZE_1 + DDR3_BASE_SIZE_0) +
- "\nActual End: " + "0x" + java.lang.Long.toHexString(TOTAL_MEM_SIZE));
-}
-
-
-function getMemSegmentDefinition_external(core)
-{
- var memory = new Array();
- var index = 0;
-
- memory[index++] = ["IPU1_1_CODE_MEM", {
- comment : "IPU1_1_CODE_MEM",
- name : "IPU1_1_CODE_MEM",
- base : IPU1_1_CODE_ADDR,
- len : IPU1_1_CODE_SIZE
- }];
- memory[index++] = ["IPU1_1_DATA_MEM", {
- comment : "IPU1_1_DATA_MEM",
- name : "IPU1_1_DATA_MEM",
- base : IPU1_1_DATA_ADDR,
- len : IPU1_1_DATA_SIZE
- }];
- memory[index++] = ["IPU1_1_BSS_MEM", {
- comment : "IPU1_1_BSS_MEM",
- name : "IPU1_1_BSS_MEM",
- base : IPU1_1_BSS_ADDR,
- len : IPU1_1_BSS_SIZE
- }];
- memory[index++] = ["IPU1_0_CODE_MEM", {
- comment : "IPU1_0_CODE_MEM",
- name : "IPU1_0_CODE_MEM",
- base : IPU1_0_CODE_ADDR,
- len : IPU1_0_CODE_SIZE
- }];
- memory[index++] = ["IPU1_0_DATA_MEM", {
- comment : "IPU1_0_DATA_MEM",
- name : "IPU1_0_DATA_MEM",
- base : IPU1_0_DATA_ADDR,
- len : IPU1_0_DATA_SIZE
- }];
- memory[index++] = ["IPU1_0_BSS_MEM", {
- comment : "IPU1_0_BSS_MEM",
- name : "IPU1_0_BSS_MEM",
- base : IPU1_0_BSS_ADDR,
- len : IPU1_0_BSS_SIZE
- }];
- memory[index++] = ["DSP1_CODE_MEM", {
- comment : "DSP1_CODE_MEM",
- name : "DSP1_CODE_MEM",
- base : DSP1_CODE_ADDR,
- len : DSP1_CODE_SIZE
- }];
- memory[index++] = ["DSP1_DATA_MEM", {
- comment : "DSP1_DATA_MEM",
- name : "DSP1_DATA_MEM",
- base : DSP1_DATA_ADDR,
- len : DSP1_DATA_SIZE
- }];
-
- memory[index++] = ["A15_0_NDK_MEM", {
- comment : "A15_0_NDK_MEM",
- name : "A15_0_NDK_MEM",
- base : A15_0_NDK_DATA_ADDR,
- len : A15_0_NDK_DATA_SIZE
- }];
- memory[index++] = ["A15_0_DATA_MEM", {
- comment : "A15_0_DATA_MEM",
- name : "A15_0_DATA_MEM",
- base : A15_0_DATA_ADDR,
- len : A15_0_DATA_SIZE
- }];
- memory[index++] = ["SR1_FRAME_BUFFER_MEM", {
- comment : "SR1_FRAME_BUFFER_MEM",
- name : "SR1_FRAME_BUFFER_MEM",
- base : SR1_FRAME_BUFFER_ADDR,
- len : SR1_FRAME_BUFFER_SIZE
- }];
- memory[index++] = ["SR0", {
- comment : "SR0",
- name : "SR0",
- base : SR0_ADDR,
- len : SR0_SIZE
- }];
- memory[index++] = ["HDVPSS_DESC_MEM", {
- comment : "HDVPSS_DESC_MEM",
- name : "HDVPSS_DESC_MEM",
- base : HDVPSS_DESC_ADDR,
- len : HDVPSS_DESC_SIZE
- }];
- memory[index++] = ["REMOTE_LOG_MEM", {
- comment : "REMOTE_LOG_MEM",
- name : "REMOTE_LOG_MEM",
- base : REMOTE_LOG_ADDR,
- len : REMOTE_LOG_SIZE
- }];
- memory[index++] = ["LINK_STATS_MEM", {
- comment : "LINK_STATS_MEM",
- name : "LINK_STATS_MEM",
- base : LINK_STATS_ADDR,
- len : LINK_STATS_SIZE
- }];
- memory[index++] = ["SYSTEM_IPC_SHM_MEM", {
- comment : "SYSTEM_IPC_SHM_MEM",
- name : "SYSTEM_IPC_SHM_MEM",
- base : SYSTEM_IPC_SHM_ADDR,
- len : SYSTEM_IPC_SHM_SIZE
- }];
-
- xdc.print("# !!! Core is [" + core + "] !!!" );
-
- memory[index++] = ["DSP1_L2_SRAM", {
- comment: "DSP1_L2_SRAM",
- name: "DSP1_L2_SRAM",
- base: DSP1_L2_SRAM_ADDR,
- len: DSP1_L2_SRAM_SIZE
- }];
-
- return (memory);
-}
diff --git a/packages/ti/build/tda2xx/config_tda2xx.bld b/packages/ti/build/tda2xx/config_tda2xx.bld
+++ /dev/null
@@ -1,151 +0,0 @@
-/*
-* Copyright (c) 2016, Texas Instruments Incorporated
-* All rights reserved.
-*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions
-* are met:
-*
-* * Redistributions of source code must retain the above copyright
-* notice, this list of conditions and the following disclaimer.
-*
-* * Redistributions in binary form must reproduce the above copyright
-* notice, this list of conditions and the following disclaimer in the
-* documentation and/or other materials provided with the distribution.
-*
-* * Neither the name of Texas Instruments Incorporated nor the names of
-* its contributors may be used to endorse or promote products derived
-* from this software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
-* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
-* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
-* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
-
-/* load the required modules for the configuration */
-var M4 = xdc.useModule('ti.targets.arm.elf.M4');
-/* M4 compiler directory path */
-M4.rootDir = java.lang.System.getenv("CGTOOLS");
-
-/*
-Memory map
-
-DDR: 0x80000000 (Ist 512MB - Cached)
-
-NOTE: APP_CACHED_DATA_BLK1_MEM is used to route sections which needs to be in a
-separate section preferably at the end of 512 MB memory.
-For example:
-Frame buffer memory can be less at runtime depending on boards with lesser DDR (as in TDA 12x12 POP boards).
-If the same is routed to APP_CACHED_DATA_MEM section then the linker will
-place the frame buffer before other data section and the other data will fall into
-region outside the DDR in the board. Hence separate section is used!!
-
-+-----------------------------+
-| APP_CODE_MEM | 2MB
-+-----------------------------+
-| APP_CACHED_DATA_MEM | 18MB
-+-----------------------------+
-| APP_CACHED_DATA_BLK1_MEM | 236MB
-+-----------------------------+
-| APP_CACHED_DATA_BLK2_MEM | 128MB
-+-----------------------------+
-| NOT USED | Remaining MB
-+-----------------------------+
-
-DDR: 0xA0000000 (2nd 512MB - Non-Cached - but mapped to above 512MB physical)
-
-+-----------------------------+
-| Mirrored Section | 256+128 MB (from 0x80000000)
-+-----------------------------+
-| APP_UNCACHED_DATA_BLK3_MEM | 2MB
-+-----------------------------+
-| NOT USED | Remaining MB
-+-----------------------------+
-
-*/
-
-var KB=1024;
-var MB=KB*KB;
-
-var DDR3_ADDR_0;
-var DDR3_ADDR_1;
-
-var APP_CODE_ADDR;
-var APP_CODE_SIZE;
-
-var APP_CACHED_DATA_ADDR;
-var APP_CACHED_DATA_SIZE;
-
-var APP_UNCACHED_DATA_BLK3_ADDR;
-var APP_UNCACHED_DATA_BLK3_SIZE;
-
-var APP_CACHED_DATA_BLK1_ADDR;
-var APP_CACHED_DATA_BLK1_SIZE;
-
-var APP_CACHED_DATA_BLK2_ADDR;
-var APP_CACHED_DATA_BLK2_SIZE;
-
-/* First 4KB used by SBL */
-SBL_SIZE = 4*KB;
-DDR3_ADDR_0 = 0x80000000 + SBL_SIZE;
-DDR3_ADDR_1 = 0xA0000000 + SBL_SIZE;
-
-APP_CODE_SIZE = 2*MB - SBL_SIZE;
-APP_CACHED_DATA_SIZE = 18*MB;
-APP_CACHED_DATA_BLK1_SIZE = 236*MB;
-APP_CACHED_DATA_BLK2_SIZE = 128*MB;
-APP_UNCACHED_DATA_BLK3_SIZE = 2*MB;
-
-APP_CODE_ADDR = DDR3_ADDR_0;
-APP_CACHED_DATA_ADDR = APP_CODE_ADDR + APP_CODE_SIZE;
-APP_CACHED_DATA_BLK1_ADDR = APP_CACHED_DATA_ADDR + APP_CACHED_DATA_SIZE;
-APP_CACHED_DATA_BLK2_ADDR = APP_CACHED_DATA_BLK1_ADDR + APP_CACHED_DATA_BLK1_SIZE;
-APP_UNCACHED_DATA_BLK3_ADDR = DDR3_ADDR_1 + APP_CODE_SIZE + APP_CACHED_DATA_SIZE + APP_CACHED_DATA_BLK1_SIZE + APP_CACHED_DATA_BLK2_SIZE;
-
-Build.platformTable["ti.platforms.evmDRA7XX"] =
-{
- externalMemoryMap:
- [
- ["APP_CODE_MEM", {
- comment : "APP_CODE_MEM",
- name : "APP_CODE_MEM",
- base : APP_CODE_ADDR,
- len : APP_CODE_SIZE
- }],
- ["APP_CACHED_DATA_MEM", {
- comment : "APP_CACHED_DATA_MEM",
- name : "APP_CACHED_DATA_MEM",
- base : APP_CACHED_DATA_ADDR,
- len : APP_CACHED_DATA_SIZE
- }],
- ["APP_UNCACHED_DATA_BLK3_MEM", {
- comment : "APP_UNCACHED_DATA_BLK3_MEM",
- name : "APP_UNCACHED_DATA_BLK3_MEM",
- base : APP_UNCACHED_DATA_BLK3_ADDR,
- len : APP_UNCACHED_DATA_BLK3_SIZE
- }],
- ["APP_CACHED_DATA_BLK1_MEM", {
- comment : "APP_CACHED_DATA_BLK1_MEM",
- name : "APP_CACHED_DATA_BLK1_MEM",
- base : APP_CACHED_DATA_BLK1_ADDR,
- len : APP_CACHED_DATA_BLK1_SIZE
- }],
- ["APP_CACHED_DATA_BLK2_MEM", {
- comment : "APP_CACHED_DATA_BLK2_MEM",
- name : "APP_CACHED_DATA_BLK2_MEM",
- base : APP_CACHED_DATA_BLK2_ADDR,
- len : APP_CACHED_DATA_BLK2_SIZE
- }],
- ],
- codeMemory: "APP_CODE_MEM",
- dataMemory: "APP_CACHED_DATA_MEM",
- stackMemory: "APP_CACHED_DATA_MEM"
-};
diff --git a/packages/ti/build/tda2xx/config_tda2xx_a15.bld b/packages/ti/build/tda2xx/config_tda2xx_a15.bld
+++ /dev/null
@@ -1,44 +0,0 @@
-/*******************************************************************************
- * *
- * Copyright (c) 2014 Texas Instruments Incorporated - http://www.ti.com/ *
- * ALL RIGHTS RESERVED *
- * *
- ******************************************************************************/
-
-/*
- * ======== config_tda2xx_a15.bld ========
- */
-var MemSegDefine = xdc.loadCapsule("mem_segment_definition_1024mb_bios.xs");
-
-var CurrentCore = java.lang.System.getenv("CORE");
-var CurrentPlatform = java.lang.System.getenv("BOARD");
-xdc.print("# !!! Current build platform is [" + CurrentPlatform + "] !!!" );
-
-var Build = xdc.useModule('xdc.bld.BuildEnvironment');
-var A15 = xdc.useModule('gnu.targets.arm.A15F');
-var buildReleaseConfig = true;
-
-/*add bspLib to support SemiHosting to enable system_printf on A15*/
-/* GCC bare metal targets */
-var gccArmTargets = xdc.loadPackage('gnu.targets.arm');
-gccArmTargets.A15F.bspLib = "rdimon";
-
-A15.rootDir = java.lang.System.getenv("CGTOOLS_A15");
-A15.ccOpts.suffix +=
-A15.lnkOpts.suffix +=
-//set default platform and list of all interested platforms for A15
-A15.platforms = ["ti.platforms.evmDRA7XX:Cortex_A15",
- ];
-A15.platform = A15.platforms[0];
-
-Build.targets = [
- A15,
- ];
-
-Build.platformTable["ti.platforms.evmDRA7XX:Cortex_A15"] =
-{
- externalMemoryMap: MemSegDefine.getMemSegmentDefinition_external(CurrentCore),
- codeMemory:"A15_0_CODE_MEM",
- dataMemory:"A15_0_DATA_MEM",
- stackMemory:"A15_0_DATA_MEM"
-};
diff --git a/packages/ti/build/tda2xx/config_tda2xx_c66.bld b/packages/ti/build/tda2xx/config_tda2xx_c66.bld
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * ======== config.bld ========
- * Sample Build configuration script
- */
-
-/* load the required modules for the configuration */
-var C66 = xdc.useModule('ti.targets.elf.C66');
-
-
-/* compiler paths for the CCS4.0 */
-var rootDirPre = java.lang.System.getenv("CGTOOLS_DSP");
-var rootDirPost = "";
-
-/**********************************C66******************************/
-
-/* configure the options for the c66 targets */
-
-/* c66 compiler directory path */
-C66.rootDir = rootDirPre + rootDirPost;
-
-/* compiler options */
-C66.ccOpts.suffix += " -mi10 -mo ";
-
-/* set default platform and list of all interested *
- * platforms for C66 */
-
-C66.platforms = [
- "ti.platforms.evmDRA7XX",
-
- ];
-/* select the default platform */
-C66.platform = C66.platforms[0];
-
-
-/* list interested targets in Build.targets array */
-Build.targets = [
- C66,
- ];
diff --git a/packages/ti/build/tda2xx/mem_segment_definition_1024mb_bios.xs b/packages/ti/build/tda2xx/mem_segment_definition_1024mb_bios.xs
+++ /dev/null
@@ -1,515 +0,0 @@
-/*
- *******************************************************************************
- *
- * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
- * ALL RIGHTS RESERVED
- *
- *******************************************************************************
- */
-
-/*
- * ======== mem_segment_definition.xs ========
- * ======== Single file for the memory map configuration of all cores =========
- */
-
-var KB=1024;
-var MB=KB*KB;
-
-var DDR3_ADDR;
-var DDR3_SIZE;
-
-var DDR3_BASE_ADDR_0;
-var DDR3_BASE_SIZE_0;
-var DDR3_BASE_ADDR_1;
-var DDR3_BASE_SIZE_1;
-
-var OCMC1_ADDR;
-var OCMC2_ADDR;
-var OCMC3_ADDR;
-
-var OCMC1_SIZE;
-var OCMC2_SIZE;
-var OCMC3_SIZE;
-
-var DSP1_L2_SRAM_ADDR;
-var DSP1_L2_SRAM_SIZE;
-
-var DSP2_L2_SRAM_ADDR;
-var DSP2_L2_SRAM_SIZE;
-
-var EVE1_SRAM_ADDR;
-var EVE1_SRAM_SIZE;
-
-var EVE2_SRAM_ADDR;
-var EVE2_SRAM_SIZE;
-
-var EVE3_SRAM_ADDR;
-var EVE3_SRAM_SIZE;
-
-var EVE4_SRAM_ADDR;
-var EVE4_SRAM_SIZE;
-
-var SR0_ADDR;
-var SR0_SIZE;
-
-var IPU1_1_CODE_ADDR;
-var IPU1_1_CODE_SIZE;
-
-var IPU1_1_DATA_ADDR;
-var IPU1_1_DATA_SIZE;
-
-var IPU1_1_BSS_ADDR;
-var IPU1_1_BSS_SIZE;
-
-var SR1_FRAME_BUFFER_ADDR;
-var SR1_FRAME_BUFFER_SIZE;
-
-var IPU1_0_CODE_ADDR;
-var IPU1_0_CODE_SIZE;
-
-var IPU1_0_DATA_ADDR;
-var IPU1_0_DATA_SIZE;
-
-var IPU1_0_BSS_ADDR;
-var IPU1_0_BSS_SIZE;
-
-var DSP1_CODE_ADDR;
-var DSP1_CODE_SIZE;
-
-var DSP1_DATA_ADDR;
-var DSP1_DATA_SIZE;
-
-var DSP2_CODE_ADDR;
-var DSP2_CODE_SIZE;
-
-var DSP2_DATA_ADDR;
-var DSP2_DATA_SIZE;
-
-var EVE1_CODE_ADDR;
-var EVE1_CODE_SIZE;
-
-var EVE1_DATA_ADDR;
-var EVE1_DATA_SIZE;
-
-var EVE1_VECS_ADDR;
-var EVE1_VECS_SIZE;
-
-var EVE2_CODE_ADDR;
-var EVE2_CODE_SIZE;
-
-var EVE2_DATA_ADDR;
-var EVE2_DATA_SIZE;
-
-var EVE2_VECS_ADDR;
-var EVE2_VECS_SIZE;
-
-var EVE3_CODE_ADDR;
-var EVE3_CODE_SIZE;
-
-var EVE3_DATA_ADDR;
-var EVE3_DATA_SIZE;
-
-var EVE3_VECS_ADDR;
-var EVE3_VECS_SIZE;
-
-var EVE4_CODE_ADDR;
-var EVE4_CODE_SIZE;
-
-var EVE4_DATA_ADDR;
-var EVE4_DATA_SIZE;
-
-var EVE4_VECS_ADDR;
-var EVE4_VECS_SIZE;
-
-var A15_0_CODE_ADDR;
-var A15_0_CODE_SIZE;
-
-var A15_0_DATA_ADDR;
-var A15_0_DATA_SIZE;
-
-var HDVPSS_DESC_ADDR;
-var HDVPSS_DESC_SIZE;
-
-var REMOTE_LOG_ADDR;
-var REMOTE_LOG_SIZE;
-
-DDR3_ADDR = 0x80000000;
-DDR3_SIZE = 1024*MB;
-
-DDR3_BASE_ADDR_0 = 0x80000000;
-DDR3_BASE_SIZE_0 = 512*MB;
-
-/* The start address of the second mem section should be 16MB aligned.
- * This alignment is a must as a single 16MB mapping is used for EVE
- * to map SR0, REMOTE_LOG_MEM sections.
- * tlb_config_eveX.c need to be modified otherwise
- */
-DDR3_BASE_ADDR_1 = 0xA0000000;
-DDR3_BASE_SIZE_1 = 512*MB;
-
-OCMC1_ADDR = 0x40300000;
-OCMC1_SIZE = 512*KB;
-
-OCMC2_ADDR = 0x40400000;
-OCMC2_SIZE = 1*MB;
-
-OCMC3_ADDR = 0x40500000;
-OCMC3_SIZE = 1*MB;
-
-DSP1_L2_SRAM_ADDR = 0x40800000;
-DSP1_L2_SRAM_SIZE = 288*KB;
-
-DSP2_L2_SRAM_ADDR = 0x41000000;
-DSP2_L2_SRAM_SIZE = 288*KB;
-
-EVE1_SRAM_ADDR = 0x42000000;
-EVE1_SRAM_SIZE = 1*MB;
-
-EVE2_SRAM_ADDR = 0x42100000;
-EVE2_SRAM_SIZE = 1*MB;
-
-EVE3_SRAM_ADDR = 0x42200000;
-EVE3_SRAM_SIZE = 1*MB;
-
-EVE4_SRAM_ADDR = 0x42300000;
-EVE4_SRAM_SIZE = 1*MB;
-
-var TOTAL_MEM_SIZE = (DDR3_SIZE);
-
-/* First 512 MB - cached */
-/* EVE vecs space should be align with 16MB boundary, and if possible try to fit
- * the entire vecs+code+data in 16MB section. In this case a single TLB map would
- * be enough to map vecs+code+data of an EVE.
- * tlb_config_eveX.c need to be modified if any of these EVE memory sections or
- * SR1_FRAME_BUFFER_MEM section is modified.
- */
-EVE1_VECS_SIZE = 0.5*MB;
-EVE1_CODE_SIZE = 2*MB;
-EVE1_DATA_SIZE =13.5*MB;
-EVE2_VECS_SIZE = 0.5*MB;
-EVE2_CODE_SIZE = 2*MB;
-EVE2_DATA_SIZE =13.5*MB;
-EVE3_VECS_SIZE = 0.5*MB;
-EVE3_CODE_SIZE = 2*MB;
-EVE3_DATA_SIZE =13.5*MB;
-EVE4_VECS_SIZE = 0.5*MB;
-EVE4_CODE_SIZE = 2*MB;
-EVE4_DATA_SIZE =13.5*MB;
-IPU1_1_CODE_SIZE = 2*MB;
-IPU1_1_BSS_SIZE = 8*MB;
-IPU1_1_DATA_SIZE = 4*MB;
-IPU1_0_CODE_SIZE = 6*MB;
-IPU1_0_BSS_SIZE = 8*MB;
-IPU1_0_DATA_SIZE = 4*MB;
-SR1_FRAME_BUFFER_SIZE = 256*MB;
-DSP1_CODE_SIZE = 2*MB;
-DSP1_DATA_SIZE = 64*MB;
-DSP2_CODE_SIZE = 2*MB;
-DSP2_DATA_SIZE = 64*MB;
-A15_0_CODE_SIZE = 2*MB;
-A15_0_DATA_SIZE = 14*MB;
-
-
-
-/* Second 512 MB - non-cached */
-/* The start address of the second mem section should be 16MB aligned.
- * This alignment is a must as a single 16MB mapping is used for EVE
- * to map SR0, EMOTE_LOG_MEM sections.
- * tlb_config_eveX.c need to be modified otherwise
- */
-SR0_SIZE = 13*MB;
-REMOTE_LOG_SIZE =1024*KB;
-HDVPSS_DESC_SIZE = 2*MB;
-
-
-/* Cached Section */
-/* EVE vecs space should be align with 16MB boundary, and if possible try to fit
- * the entire vecs+code+data in 16MB section. In this case a single TLB map would
- * be enough to map vecs+code+data of an EVE.
- * tlb_config_eveX.c need to be modified if any of these EVE memory sections or
- * SR1_FRAME_BUFFER_MEM section is modified.
- */
-EVE1_VECS_ADDR = DDR3_BASE_ADDR_0;
-EVE1_CODE_ADDR = EVE1_VECS_ADDR + EVE1_VECS_SIZE;
-EVE1_DATA_ADDR = EVE1_CODE_ADDR + EVE1_CODE_SIZE;
-EVE2_VECS_ADDR = EVE1_DATA_ADDR + EVE1_DATA_SIZE;
-EVE2_CODE_ADDR = EVE2_VECS_ADDR + EVE2_VECS_SIZE;
-EVE2_DATA_ADDR = EVE2_CODE_ADDR + EVE2_CODE_SIZE;
-EVE3_VECS_ADDR = EVE2_DATA_ADDR + EVE2_DATA_SIZE;
-EVE3_CODE_ADDR = EVE3_VECS_ADDR + EVE3_VECS_SIZE;
-EVE3_DATA_ADDR = EVE3_CODE_ADDR + EVE3_CODE_SIZE;
-EVE4_VECS_ADDR = EVE3_DATA_ADDR + EVE3_DATA_SIZE;
-EVE4_CODE_ADDR = EVE4_VECS_ADDR + EVE4_VECS_SIZE;
-EVE4_DATA_ADDR = EVE4_CODE_ADDR + EVE4_CODE_SIZE;
-IPU1_1_CODE_ADDR = EVE4_DATA_ADDR + EVE4_DATA_SIZE;
-IPU1_1_DATA_ADDR = IPU1_1_CODE_ADDR + IPU1_1_CODE_SIZE;
-IPU1_1_BSS_ADDR = IPU1_1_DATA_ADDR + IPU1_1_DATA_SIZE;
-IPU1_0_CODE_ADDR = IPU1_1_BSS_ADDR + IPU1_1_BSS_SIZE;
-IPU1_0_DATA_ADDR = IPU1_0_CODE_ADDR + IPU1_0_CODE_SIZE;
-IPU1_0_BSS_ADDR = IPU1_0_DATA_ADDR + IPU1_0_DATA_SIZE;
-SR1_FRAME_BUFFER_ADDR = IPU1_0_BSS_ADDR + IPU1_0_BSS_SIZE;
-DSP1_CODE_ADDR = SR1_FRAME_BUFFER_ADDR + SR1_FRAME_BUFFER_SIZE;
-DSP1_DATA_ADDR = DSP1_CODE_ADDR + DSP1_CODE_SIZE;
-DSP2_CODE_ADDR = DSP1_DATA_ADDR + DSP1_DATA_SIZE;
-DSP2_DATA_ADDR = DSP2_CODE_ADDR + DSP2_CODE_SIZE;
-A15_0_CODE_ADDR = DSP2_DATA_ADDR + DSP2_DATA_SIZE;
-A15_0_DATA_ADDR = A15_0_CODE_ADDR + A15_0_CODE_SIZE;
-
-
-/* Non Cached Section */
-/* The start address of the second mem section should be 16MB aligned.
- * This alignment is a must as a single 16MB mapping is used for EVE
- * to map SR0, EMOTE_LOG_MEM sections.
- * tlb_config_eveX.c need to be modified otherwise
- */
-SR0_ADDR = DDR3_BASE_ADDR_1;
-REMOTE_LOG_ADDR = SR0_ADDR + SR0_SIZE;
-HDVPSS_DESC_ADDR = REMOTE_LOG_ADDR + REMOTE_LOG_SIZE;
-
-if ((A15_0_DATA_ADDR + A15_0_DATA_SIZE) > (DDR3_BASE_ADDR_0 + DDR3_BASE_SIZE_0))
-{
- throw xdc.$$XDCException("MEMORY_MAP OVERFLOW ERROR ",
- "\nRegion End: " + "0x" + java.lang.Long.toHexString(DDR3_BASE_ADDR_0 + DDR3_BASE_SIZE_0) +
- "\nActual End: " + "0x" + java.lang.Long.toHexString(A15_0_DATA_ADDR + A15_0_DATA_SIZE));
-}
-
-if ((HDVPSS_DESC_ADDR + HDVPSS_DESC_SIZE) > (DDR3_BASE_ADDR_1 + DDR3_BASE_SIZE_1))
-{
- throw xdc.$$XDCException("MEMORY_MAP OVERFLOW ERROR ",
- "\nRegion End: " + "0x" + java.lang.Long.toHexString(DDR3_BASE_ADDR_1 + DDR3_BASE_SIZE_1) +
- "\nActual End: " + "0x" + java.lang.Long.toHexString(HDVPSS_DESC_ADDR + HDVPSS_DESC_SIZE));
-}
-
-if ((DDR3_BASE_SIZE_1 + DDR3_BASE_SIZE_0) > (TOTAL_MEM_SIZE))
-{
- throw xdc.$$XDCException("MEMORY_MAP EXCEEDS 256mb ERROR ",
- "\nRegion End: " + "0x" + java.lang.Long.toHexString(DDR3_BASE_SIZE_1 + DDR3_BASE_SIZE_0) +
- "\nActual End: " + "0x" + java.lang.Long.toHexString(TOTAL_MEM_SIZE));
-}
-
-
-function getMemSegmentDefinition_external(core)
-{
- var memory = new Array();
- var index = 0;
-
- memory[index++] = ["IPU1_1_CODE_MEM", {
- comment : "IPU1_1_CODE_MEM",
- name : "IPU1_1_CODE_MEM",
- base : IPU1_1_CODE_ADDR,
- len : IPU1_1_CODE_SIZE
- }];
- memory[index++] = ["IPU1_1_DATA_MEM", {
- comment : "IPU1_1_DATA_MEM",
- name : "IPU1_1_DATA_MEM",
- base : IPU1_1_DATA_ADDR,
- len : IPU1_1_DATA_SIZE
- }];
- memory[index++] = ["IPU1_1_BSS_MEM", {
- comment : "IPU1_1_BSS_MEM",
- name : "IPU1_1_BSS_MEM",
- base : IPU1_1_BSS_ADDR,
- len : IPU1_1_BSS_SIZE
- }];
- memory[index++] = ["IPU1_0_CODE_MEM", {
- comment : "IPU1_0_CODE_MEM",
- name : "IPU1_0_CODE_MEM",
- base : IPU1_0_CODE_ADDR,
- len : IPU1_0_CODE_SIZE
- }];
- memory[index++] = ["IPU1_0_DATA_MEM", {
- comment : "IPU1_0_DATA_MEM",
- name : "IPU1_0_DATA_MEM",
- base : IPU1_0_DATA_ADDR,
- len : IPU1_0_DATA_SIZE
- }];
- memory[index++] = ["IPU1_0_BSS_MEM", {
- comment : "IPU1_0_BSS_MEM",
- name : "IPU1_0_BSS_MEM",
- base : IPU1_0_BSS_ADDR,
- len : IPU1_0_BSS_SIZE
- }];
- memory[index++] = ["DSP1_CODE_MEM", {
- comment : "DSP1_CODE_MEM",
- name : "DSP1_CODE_MEM",
- base : DSP1_CODE_ADDR,
- len : DSP1_CODE_SIZE
- }];
- memory[index++] = ["DSP1_DATA_MEM", {
- comment : "DSP1_DATA_MEM",
- name : "DSP1_DATA_MEM",
- base : DSP1_DATA_ADDR,
- len : DSP1_DATA_SIZE
- }];
-
- memory[index++] = ["DSP2_CODE_MEM", {
- comment : "DSP2_CODE_MEM",
- name : "DSP2_CODE_MEM",
- base : DSP2_CODE_ADDR,
- len : DSP2_CODE_SIZE
- }];
- memory[index++] = ["DSP2_DATA_MEM", {
- comment : "DSP2_DATA_MEM",
- name : "DSP2_DATA_MEM",
- base : DSP2_DATA_ADDR,
- len : DSP2_DATA_SIZE
- }];
-
- memory[index++] = ["A15_0_CODE_MEM", {
- comment : "A15_0_CODE_MEM",
- name : "A15_0_CODE_MEM",
- base : A15_0_CODE_ADDR,
- len : A15_0_CODE_SIZE
- }];
- memory[index++] = ["A15_0_DATA_MEM", {
- comment : "A15_0_DATA_MEM",
- name : "A15_0_DATA_MEM",
- base : A15_0_DATA_ADDR,
- len : A15_0_DATA_SIZE
- }];
-
-
- memory[index++] = ["EVE1_VECS_MEM", {
- comment : "EVE1_VECS_MEM",
- name : "EVE1_VECS_MEM",
- base : EVE1_VECS_ADDR,
- len : EVE1_VECS_SIZE
- }];
- memory[index++] = ["EVE1_CODE_MEM", {
- comment : "EVE1_CODE_MEM",
- name : "EVE1_CODE_MEM",
- base : EVE1_CODE_ADDR,
- len : EVE1_CODE_SIZE
- }];
- memory[index++] = ["EVE1_DATA_MEM", {
- comment : "EVE1_DATA_MEM",
- name : "EVE1_DATA_MEM",
- base : EVE1_DATA_ADDR,
- len : EVE1_DATA_SIZE
- }];
- memory[index++] = ["EVE2_VECS_MEM", {
- comment : "EVE2_VECS_MEM",
- name : "EVE2_VECS_MEM",
- base : EVE2_VECS_ADDR,
- len : EVE2_VECS_SIZE
- }];
- memory[index++] = ["EVE2_CODE_MEM", {
- comment : "EVE2_CODE_MEM",
- name : "EVE2_CODE_MEM",
- base : EVE2_CODE_ADDR,
- len : EVE2_CODE_SIZE
- }];
- memory[index++] = ["EVE2_DATA_MEM", {
- comment : "EVE2_DATA_MEM",
- name : "EVE2_DATA_MEM",
- base : EVE2_DATA_ADDR,
- len : EVE2_DATA_SIZE
- }];
- memory[index++] = ["EVE3_VECS_MEM", {
- comment : "EVE3_VECS_MEM",
- name : "EVE3_VECS_MEM",
- base : EVE3_VECS_ADDR,
- len : EVE3_VECS_SIZE
- }];
- memory[index++] = ["EVE3_CODE_MEM", {
- comment : "EVE3_CODE_MEM",
- name : "EVE3_CODE_MEM",
- base : EVE3_CODE_ADDR,
- len : EVE3_CODE_SIZE
- }];
- memory[index++] = ["EVE3_DATA_MEM", {
- comment : "EVE3_DATA_MEM",
- name : "EVE3_DATA_MEM",
- base : EVE3_DATA_ADDR,
- len : EVE3_DATA_SIZE
- }];
- memory[index++] = ["EVE4_VECS_MEM", {
- comment : "EVE4_VECS_MEM",
- name : "EVE4_VECS_MEM",
- base : EVE4_VECS_ADDR,
- len : EVE4_VECS_SIZE
- }];
- memory[index++] = ["EVE4_CODE_MEM", {
- comment : "EVE4_CODE_MEM",
- name : "EVE4_CODE_MEM",
- base : EVE4_CODE_ADDR,
- len : EVE4_CODE_SIZE
- }];
- memory[index++] = ["EVE4_DATA_MEM", {
- comment : "EVE4_DATA_MEM",
- name : "EVE4_DATA_MEM",
- base : EVE4_DATA_ADDR,
- len : EVE4_DATA_SIZE
- }];
- memory[index++] = ["SR1_FRAME_BUFFER_MEM", {
- comment : "SR1_FRAME_BUFFER_MEM",
- name : "SR1_FRAME_BUFFER_MEM",
- base : SR1_FRAME_BUFFER_ADDR,
- len : SR1_FRAME_BUFFER_SIZE
- }];
- memory[index++] = ["SR0", {
- comment : "SR0",
- name : "SR0",
- base : SR0_ADDR,
- len : SR0_SIZE
- }];
- memory[index++] = ["HDVPSS_DESC_MEM", {
- comment : "HDVPSS_DESC_MEM",
- name : "HDVPSS_DESC_MEM",
- base : HDVPSS_DESC_ADDR,
- len : HDVPSS_DESC_SIZE
- }];
- memory[index++] = ["REMOTE_LOG_MEM", {
- comment : "REMOTE_LOG_MEM",
- name : "REMOTE_LOG_MEM",
- base : REMOTE_LOG_ADDR,
- len : REMOTE_LOG_SIZE
- }];
-
-/* Memory name OCMC_RAM1, 2 & 3 are defined internally in evmDRA7XX platform
- So no need to specify them explicitly for IPU1, A15
-*/
- xdc.print("# !!! Core is [" + core + "] !!!" );
-
- if( core == "c66xdsp_1" ||
- core == "c66xdsp_2" ||
- core == "arp32_1" ||
- core == "arp32_2" ||
- core == "arp32_3" ||
- core == "arp32_4"
- )
- {
- memory[index++] = ["OCMC_RAM1", {
- comment: "OCMC_RAM1",
- name: "OCMC_RAM1",
- base: OCMC1_ADDR,
- len: OCMC1_SIZE
- }];
- memory[index++] = ["OCMC_RAM2", {
- comment: "OCMC_RAM2",
- name: "OCMC_RAM2",
- base: OCMC2_ADDR,
- len: OCMC2_SIZE
- }];
- memory[index++] = ["OCMC_RAM3", {
- comment: "OCMC_RAM3",
- name: "OCMC_RAM3",
- base: OCMC3_ADDR,
- len: OCMC3_SIZE
- }];
- }
- memory[index++] = ["DSP1_L2_SRAM", {
- comment: "DSP1_L2_SRAM",
- name: "DSP1_L2_SRAM",
- base: DSP1_L2_SRAM_ADDR,
- len: DSP1_L2_SRAM_SIZE
- }];
- memory[index++] = ["DSP2_L2_SRAM", {
- comment: "DSP2_L2_SRAM",
- name: "DSP2_L2_SRAM",
- base: DSP2_L2_SRAM_ADDR,
- len: DSP2_L2_SRAM_SIZE
- }];
-
- return (memory);
-}
diff --git a/packages/ti/build/tda3xx/config_tda3xx.bld b/packages/ti/build/tda3xx/config_tda3xx.bld
+++ /dev/null
@@ -1,216 +0,0 @@
-/*
-* Copyright (c) 2016, Texas Instruments Incorporated
-* All rights reserved.
-*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions
-* are met:
-*
-* * Redistributions of source code must retain the above copyright
-* notice, this list of conditions and the following disclaimer.
-*
-* * Redistributions in binary form must reproduce the above copyright
-* notice, this list of conditions and the following disclaimer in the
-* documentation and/or other materials provided with the distribution.
-*
-* * Neither the name of Texas Instruments Incorporated nor the names of
-* its contributors may be used to endorse or promote products derived
-* from this software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
-* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
-* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
-* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
-
-/* load the required modules for the configuration */
-var M4 = xdc.useModule('ti.targets.arm.elf.M4');
-/* M4 compiler directory path */
-M4.rootDir = java.lang.System.getenv("CGTOOLS");
-
-/*
-Memory map
-
-DDR: 0x80000000 (Ist 512MB - Cached)
-
-NOTE: APP_CACHED_DATA_BLK1_MEM is used to route sections which needs to be in a
-separate section preferably at the end of 512 MB memory.
-For example:
-Frame buffer memory can be less at runtime depending on boards with lesser DDR (as in TDA 12x12 POP boards).
-If the same is routed to APP_CACHED_DATA_MEM section then the linker will
-place the frame buffer before other data section and the other data will fall into
-region outside the DDR in the board. Hence separate section is used!!
-
-+-----------------------------+
-| APP_CODE_MEM | (2MB - SBL_SIZE)
-+-----------------------------+
-| APP_CACHED_DATA_MEM | 8MB
-+-----------------------------+
-| APP_CODE2_MEM | 1MB
-+-----------------------------+
-| APP_CACHED_DATA2_MEM | 3MB
-+-----------------------------+
-| Mirrored Section | 2MB
-+-----------------------------+
-| APP_CACHED_DATA_BLK1_MEM | 240MB (Incase of 12x12, 48MB)
-+-----------------------------+
-
-DDR: 0xA0000000 (2nd 512MB - Non-Cached - but mapped to above 512MB physical)
-
-+-----------------------------+
-| Mirrored Section | 14MB for Code + Data
-+-----------------------------+
-| APP_UNCACHED_DATA_BLK3_MEM | 2MB
-+-----------------------------+
-| Mirrored Section | 240MB Frame Buffer (Incase of 12x12, 48MB)
-+-----------------------------+
-*/
-
-var KB=1024;
-var MB=KB*KB;
-
-var DDR3_ADDR_0;
-var DDR3_ADDR_1;
-var DDR3_SIZE;
-
-var APP_CODE_ADDR;
-var APP_CODE_SIZE;
-
-var APP_CACHED_DATA_ADDR;
-var APP_CACHED_DATA_SIZE;
-
-var APP_CODE2_ADDR;
-var APP_CODE2_SIZE;
-
-var APP_CACHED_DATA2_ADDR;
-var APP_CACHED_DATA2_SIZE;
-
-var APP_CACHED_DATA_BLK1_ADDR;
-var APP_CACHED_DATA_BLK1_SIZE;
-
-var APP_UNCACHED_DATA_BLK3_ADDR;
-var APP_UNCACHED_DATA_BLK3_SIZE;
-
-var SBL_ADDR;
-var SBL_SIZE;
-
-/*SBL will use 1 KB of space from address 0x80000000 for EVE */
-DDR3_ADDR_0 = 0x80000000;
-DDR3_ADDR_1 = 0xA0000000;
-DDR3_SIZE = 512*MB;
-
-SBL_SIZE = 0x400
-APP_CODE_SIZE = ((2*MB) - SBL_SIZE);
-APP_CACHED_DATA_SIZE = 8*MB;
-APP_CODE2_SIZE = 1*MB;
-APP_CACHED_DATA2_SIZE = 3*MB;
-APP_UNCACHED_DATA_BLK3_SIZE = 2*MB;
-APP_CACHED_DATA_BLK1_SIZE = 240*MB; /* Incase of 12x12, 48MB */
-
-SBL_ADDR = DDR3_ADDR_0
-APP_CODE_ADDR = SBL_ADDR + SBL_SIZE;
-APP_CACHED_DATA_ADDR = APP_CODE_ADDR + APP_CODE_SIZE;
-APP_CODE2_ADDR = APP_CACHED_DATA_ADDR + APP_CACHED_DATA_SIZE;
-APP_CACHED_DATA2_ADDR = APP_CODE2_ADDR + APP_CODE2_SIZE;
-APP_CACHED_DATA_BLK1_ADDR = APP_CACHED_DATA2_ADDR + APP_CACHED_DATA2_SIZE + APP_UNCACHED_DATA_BLK3_SIZE;
-
-APP_UNCACHED_DATA_BLK3_ADDR = DDR3_ADDR_1 + SBL_SIZE + APP_CODE_SIZE + APP_CACHED_DATA_SIZE + APP_CODE2_SIZE + APP_CACHED_DATA2_SIZE;
-
-Build.platformTable["ti.platforms.evmTDA3XX:IPU_1_0"] =
-{
- externalMemoryMap:
- [
- ["APP_CODE_MEM", {
- comment : "APP_CODE_MEM",
- name : "APP_CODE_MEM",
- base : APP_CODE_ADDR,
- len : APP_CODE_SIZE
- }],
- ["APP_CACHED_DATA_MEM", {
- comment : "APP_CACHED_DATA_MEM",
- name : "APP_CACHED_DATA_MEM",
- base : APP_CACHED_DATA_ADDR,
- len : APP_CACHED_DATA_SIZE
- }],
- ["APP_CODE2_MEM", {
- comment : "APP_CODE2_MEM",
- name : "APP_CODE2_MEM",
- base : APP_CODE2_ADDR,
- len : APP_CODE2_SIZE
- }],
- ["APP_CACHED_DATA2_MEM", {
- comment : "APP_CACHED_DATA2_MEM",
- name : "APP_CACHED_DATA2_MEM",
- base : APP_CACHED_DATA2_ADDR,
- len : APP_CACHED_DATA2_SIZE
- }],
- ["APP_UNCACHED_DATA_BLK3_MEM", {
- comment : "APP_UNCACHED_DATA_BLK3_MEM",
- name : "APP_UNCACHED_DATA_BLK3_MEM",
- base : APP_UNCACHED_DATA_BLK3_ADDR,
- len : APP_UNCACHED_DATA_BLK3_SIZE
- }],
- ["APP_CACHED_DATA_BLK1_MEM", {
- comment : "APP_CACHED_DATA_BLK1_MEM",
- name : "APP_CACHED_DATA_BLK1_MEM",
- base : APP_CACHED_DATA_BLK1_ADDR,
- len : APP_CACHED_DATA_BLK1_SIZE
- }],
- ],
- codeMemory: "APP_CODE_MEM",
- dataMemory: "APP_CACHED_DATA_MEM",
- stackMemory: "APP_CACHED_DATA_MEM"
-};
-
-Build.platformTable["ti.platforms.evmTDA3XX:IPU_1_1"] =
-{
- externalMemoryMap:
- [
- ["APP_CODE_MEM", {
- comment : "APP_CODE_MEM",
- name : "APP_CODE_MEM",
- base : APP_CODE_ADDR,
- len : APP_CODE_SIZE
- }],
- ["APP_CACHED_DATA_MEM", {
- comment : "APP_CACHED_DATA_MEM",
- name : "APP_CACHED_DATA_MEM",
- base : APP_CACHED_DATA_ADDR,
- len : APP_CACHED_DATA_SIZE
- }],
- ["APP_CODE2_MEM", {
- comment : "APP_CODE2_MEM",
- name : "APP_CODE2_MEM",
- base : APP_CODE2_ADDR,
- len : APP_CODE2_SIZE
- }],
- ["APP_CACHED_DATA2_MEM", {
- comment : "APP_CACHED_DATA2_MEM",
- name : "APP_CACHED_DATA2_MEM",
- base : APP_CACHED_DATA2_ADDR,
- len : APP_CACHED_DATA2_SIZE
- }],
- ["APP_UNCACHED_DATA_BLK3_MEM", {
- comment : "APP_UNCACHED_DATA_BLK3_MEM",
- name : "APP_UNCACHED_DATA_BLK3_MEM",
- base : APP_UNCACHED_DATA_BLK3_ADDR,
- len : APP_UNCACHED_DATA_BLK3_SIZE
- }],
- ["APP_CACHED_DATA_BLK1_MEM", {
- comment : "APP_CACHED_DATA_BLK1_MEM",
- name : "APP_CACHED_DATA_BLK1_MEM",
- base : APP_CACHED_DATA_BLK1_ADDR,
- len : APP_CACHED_DATA_BLK1_SIZE
- }],
- ],
- codeMemory: "APP_CODE2_MEM",
- dataMemory: "APP_CACHED_DATA2_MEM",
- stackMemory: "APP_CACHED_DATA2_MEM"
-};
diff --git a/packages/ti/build/tda3xx/config_tda3xx_c66.bld b/packages/ti/build/tda3xx/config_tda3xx_c66.bld
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * ======== config.bld ========
- * Sample Build configuration script
- */
-
-/* load the required modules for the configuration */
-var C66 = xdc.useModule('ti.targets.elf.C66');
-
-
-/* compiler paths for the CCS4.0 */
-var rootDirPre = java.lang.System.getenv("CGTOOLS_DSP");
-var rootDirPost = "";
-
-/**********************************C66******************************/
-
-/* configure the options for the c66 targets */
-
-/* c66 compiler directory path */
-C66.rootDir = rootDirPre + rootDirPost;
-
-/* compiler options */
-C66.ccOpts.suffix += " -mi10 -mo ";
-
-/* set default platform and list of all interested *
- * platforms for C66 */
-
-C66.platforms = [
- "ti.platforms.evmTDA3XX",
-
- ];
-/* select the default platform */
-C66.platform = C66.platforms[0];
-
-
-/* list interested targets in Build.targets array */
-Build.targets = [
- C66,
- ];
diff --git a/packages/ti/build/tpr12/config_tpr12_c66.bld b/packages/ti/build/tpr12/config_tpr12_c66.bld
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
-* Copyright (c) 2020, Texas Instruments Incorporated
-* All rights reserved.
-*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions
-* are met:
-*
-* * Redistributions of source code must retain the above copyright
-* notice, this list of conditions and the following disclaimer.
-*
-* * Redistributions in binary form must reproduce the above copyright
-* notice, this list of conditions and the following disclaimer in the
-* documentation and/or other materials provided with the distribution.
-*
-* * Neither the name of Texas Instruments Incorporated nor the names of
-* its contributors may be used to endorse or promote products derived
-* from this software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
-* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
-* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
-* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
-
-/*
- * ======== config_tpr12_c66.bld ========
- * Build configuration script for BSP drivers
- */
-/* load the required modules for the configuration */
-var C66 = xdc.useModule('ti.targets.elf.C66');
-/* C66 compiler directory path */
-C66.rootDir = java.lang.System.getenv("C6X_GEN_INSTALL_PATH");
diff --git a/packages/ti/build/tpr12/config_tpr12_r5f.bld b/packages/ti/build/tpr12/config_tpr12_r5f.bld
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
-* Copyright (c) 2020, Texas Instruments Incorporated
-* All rights reserved.
-*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions
-* are met:
-*
-* * Redistributions of source code must retain the above copyright
-* notice, this list of conditions and the following disclaimer.
-*
-* * Redistributions in binary form must reproduce the above copyright
-* notice, this list of conditions and the following disclaimer in the
-* documentation and/or other materials provided with the distribution.
-*
-* * Neither the name of Texas Instruments Incorporated nor the names of
-* its contributors may be used to endorse or promote products derived
-* from this software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
-* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
-* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
-* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
-* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
-
-/*
- * ======== config_tpr12_r5.bld ========
- * Build configuration script for BSP drivers
- */
-/* load the required modules for the configuration */
-
-var xdc_disable_thumb_mode = java.lang.System.getenv("XDC_DISABLE_THUMB_MODE");
-if(xdc_disable_thumb_mode != '' && xdc_disable_thumb_mode != null)
-{
-/* If XDC thumb mode is disabled, use the non-thumb mode xdc target */
-var R5F = xdc.useModule('ti.targets.arm.elf.R5F');
-}
-else
-{
-var R5F = xdc.useModule('ti.targets.arm.elf.R5Ft');
-}
-/* R5F compiler directory path */
-R5F.rootDir = java.lang.System.getenv("CGTOOLS");
diff --git a/packages/ti/build/tpr12/linker_c66.cmd b/packages/ti/build/tpr12/linker_c66.cmd
+++ /dev/null
@@ -1,93 +0,0 @@
-/*
- * Copyright (c) 2016, Texas Instruments Incorporated
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * * Neither the name of Texas Instruments Incorporated nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
- * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
- * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
- * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
- * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#define L1P_CACHE_SIZE (16*1024)
-#define L1D_CACHE_SIZE (16*1024)
-
-MEMORY
-{
-PAGE 0:
-
-#if (L1P_CACHE_SIZE < 0x8000)
- L1PSRAM: o = 0x00E00000, l = (0x00008000 - L1P_CACHE_SIZE)
-#endif
-#if (L1D_CACHE_SIZE < 0x8000)
- L1DSRAM: o = 0x00F00000, l = (0x00008000 - L1D_CACHE_SIZE)
-#endif
- L2SRAM: o = 0x00800000, l = 0x00060000
- L3SRAM: o = 0x88000000, l = 0x00390000
- HWA_RAM: o = 0x82000000, l = 0x00020000
-
- /* PAGEs 1 and onwards are for overlay purposes for memory optimization.
- Some examples:
- 1. Overlay one-time only text with uninitialized data.
- 2. Overlay L1PSRAM data path processing fast code and use copy tables
- to page in (before entering data path) and out of L1PSRAM (when entering
- sleep/low power).
- */
-PAGE 1:
- L3SRAM: o = 0x88000000, l = 0x00390000
-}
-
--stack 0x2000 /* SOFTWARE STACK SIZE */
--heap 0x2000 /* HEAP AREA SIZE */
-
-/* Set L1D, L1P and L2 Cache Sizes */
-ti_sysbios_family_c66_Cache_l1dSize = L1D_CACHE_SIZE;
-ti_sysbios_family_c66_Cache_l1pSize = L1P_CACHE_SIZE;
-ti_sysbios_family_c66_Cache_l2Size = 0;
-
-SECTIONS
-{
- /* hard addresses forces vecs to be allocated there */
- .vecs: {. = align(32); } > 0x00800000
-
- .fardata: {} > L2SRAM
- .const: {} > L2SRAM
- .switch: {} > L2SRAM
- .cio: {} > L2SRAM
- .data: {} > L2SRAM
- .sysmem: {} > L2SRAM
-
- GROUP
- {
- .rodata:
- .bss:
- .neardata:
- } > L2SRAM
- .stack: {} > L2SRAM
- .cinit: {} > L2SRAM
- .far: {} > L2SRAM
-
- .text: {} > L2SRAM
-}
-
diff --git a/packages/ti/build/tpr12/linker_c66_baremetal.cmd b/packages/ti/build/tpr12/linker_c66_baremetal.cmd
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- * Copyright (c) 2016, Texas Instruments Incorporated
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * * Neither the name of Texas Instruments Incorporated nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
- * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
- * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
- * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
- * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#define L1P_CACHE_SIZE (16*1024)
-#define L1D_CACHE_SIZE (16*1024)
-
-MEMORY
-{
-PAGE 0:
-
-#if (L1P_CACHE_SIZE < 0x8000)
- L1PSRAM: o = 0x00E00000, l = (0x00008000 - L1P_CACHE_SIZE)
-#endif
-#if (L1D_CACHE_SIZE < 0x8000)
- L1DSRAM: o = 0x00F00000, l = (0x00008000 - L1D_CACHE_SIZE)
-#endif
- L2SRAM: o = 0x00800000, l = 0x00060000
- L3SRAM: o = 0x88000000, l = 0x00390000
- HWA_RAM: o = 0x82000000, l = 0x00020000
-
- /* PAGEs 1 and onwards are for overlay purposes for memory optimization.
- Some examples:
- 1. Overlay one-time only text with uninitialized data.
- 2. Overlay L1PSRAM data path processing fast code and use copy tables
- to page in (before entering data path) and out of L1PSRAM (when entering
- sleep/low power).
- */
-PAGE 1:
- L3SRAM: o = 0x88000000, l = 0x00390000
-}
-
--stack 0x2000 /* SOFTWARE STACK SIZE */
--heap 0x2000 /* HEAP AREA SIZE */
-
-
-SECTIONS
-{
- /* hard addresses forces vecs to be allocated there */
- .csl_vect: {. = align(32); } > 0x00800000
-
- .fardata: {} > L2SRAM
- .const: {} > L2SRAM
- .switch: {} > L2SRAM
- .cio: {} > L2SRAM
- .data: {} > L2SRAM
- .sysmem: {} > L2SRAM
-
- GROUP
- {
- .rodata:
- .bss:
- .neardata:
- } > L2SRAM
- .stack: {} > L2SRAM
- .cinit: {} > L2SRAM
- .far: {} > L2SRAM
-
- .text: {} > L2SRAM
-}
-
diff --git a/packages/ti/build/tpr12/linker_c66_freertos.cmd b/packages/ti/build/tpr12/linker_c66_freertos.cmd
+++ /dev/null
@@ -1,90 +0,0 @@
-/*
- * Copyright (c) 2016, Texas Instruments Incorporated
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * * Neither the name of Texas Instruments Incorporated nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
- * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
- * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
- * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
- * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#define L1P_CACHE_SIZE (16*1024)
-#define L1D_CACHE_SIZE (16*1024)
-
-MEMORY
-{
-PAGE 0:
-
-#if (L1P_CACHE_SIZE < 0x8000)
- L1PSRAM: o = 0x00E00000, l = (0x00008000 - L1P_CACHE_SIZE)
-#endif
-#if (L1D_CACHE_SIZE < 0x8000)
- L1DSRAM: o = 0x00F00000, l = (0x00008000 - L1D_CACHE_SIZE)
-#endif
- L2SRAM: o = 0x00800000, l = 0x00060000
- L3SRAM: o = 0x88000000, l = 0x00390000
- HWA_RAM: o = 0x82000000, l = 0x00020000
-
- /* PAGEs 1 and onwards are for overlay purposes for memory optimization.
- Some examples:
- 1. Overlay one-time only text with uninitialized data.
- 2. Overlay L1PSRAM data path processing fast code and use copy tables
- to page in (before entering data path) and out of L1PSRAM (when entering
- sleep/low power).
- */
-PAGE 1:
- L3SRAM: o = 0x88000000, l = 0x00390000
-}
-
--stack 0x2000 /* SOFTWARE STACK SIZE */
--heap 0x1000 /* HEAP AREA SIZE */
---symbol_map _Hwi_intcVectorTable=Hwi_intcVectorTable
-
-
-SECTIONS
-{
- /* hard addresses forces vecs to be allocated there */
- .hwi_vect: {. = align(32); } > 0x00800000
- .text:csl_entry:{} > L2SRAM
- .fardata: {} > L2SRAM
- .const: {} > L2SRAM
- .switch: {} > L2SRAM
- .cio: {} > L2SRAM
- .data: {} > L2SRAM
- .sysmem: {} > L2SRAM
-
- GROUP
- {
- .rodata:
- .bss:
- .neardata:
- } > L2SRAM
- .stack: {} > L2SRAM
- .cinit: {} > L2SRAM
- .far: {} > L2SRAM
-
- .text: {} > L2SRAM
-}
-
diff --git a/packages/ti/build/tpr12/linker_c66_safertos.cmd b/packages/ti/build/tpr12/linker_c66_safertos.cmd
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- * Copyright (c) 2016, Texas Instruments Incorporated
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * * Neither the name of Texas Instruments Incorporated nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
- * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
- * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
- * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
- * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#define L1P_CACHE_SIZE (16*1024)
-#define L1D_CACHE_SIZE (16*1024)
-
-MEMORY
-{
-PAGE 0:
-
-#if (L1P_CACHE_SIZE < 0x8000)
- L1PSRAM: o = 0x00E00000, l = (0x00008000 - L1P_CACHE_SIZE)
-#endif
-#if (L1D_CACHE_SIZE < 0x8000)
- L1DSRAM: o = 0x00F00000, l = (0x00008000 - L1D_CACHE_SIZE)
-#endif
- L2SRAM: o = 0x00800000, l = 0x00060000
- L3SRAM: o = 0x88000000, l = 0x00390000
- HWA_RAM: o = 0x82000000, l = 0x00020000
-
- /* PAGEs 1 and onwards are for overlay purposes for memory optimization.
- Some examples:
- 1. Overlay one-time only text with uninitialized data.
- 2. Overlay L1PSRAM data path processing fast code and use copy tables
- to page in (before entering data path) and out of L1PSRAM (when entering
- sleep/low power).
- */
-PAGE 1:
- L3SRAM: o = 0x88000000, l = 0x00390000
-}
-
--stack 0x2000 /* SOFTWARE STACK SIZE */
--heap 0x1000 /* HEAP AREA SIZE */
--u _Hwi_intcVectorTable
-
-SECTIONS
-{
- /* hard addresses forces vecs to be allocated there
- LOAD_START( lnkStartFlashAddress ), */
-
- .hwi_vect: {. = align(32); } > 0x00800000
-/*
- .kernel_function LOAD_START( lnkKernelFuncStartAddr ) LOAD_END( lnkKernelFuncEndAddr ) :
- {
- *(KERNEL_FUNCTION)
- } > L2SRAM
-
- .unpriv_flash palign(32), LOAD_END( lnkEndFlashAddress ) :
- {
- *(.text)
- *(.const)
- } > L2SRAM
-*/
- .text:csl_entry:{} > L2SRAM
- .fardata: {} > L2SRAM
- .const: {} > L2SRAM
- .switch: {} > L2SRAM
- .cio: {} > L2SRAM
- .data: {} > L2SRAM
- .sysmem: {} > L2SRAM
-
- GROUP
- {
- .rodata:
- .bss:
- .neardata:
- } > L2SRAM
-/*
- KERNEL_DATA LOAD_START( lnkKernelDataStartAddr ),
- LOAD_END( lnkKernelDataEndAddr ) : {} > L2SRAM
-*/
- .stack: {} > L2SRAM
- .cinit: {} > L2SRAM
- .far: {} > L2SRAM
-
- .text: {} > L2SRAM
-}
-
-/* lnkStartFlashAddress */
-/* lnkKernelFuncStartAddr */
-
-/* lnkKernelFuncEndAddr */
-/* lnkEndFlashAddress */
-
-/* lnkKernelDataStartAddr */
-/* lnkKernelDataEndAddr */
diff --git a/packages/ti/build/tpr12/linker_mcu1_0.lds b/packages/ti/build/tpr12/linker_mcu1_0.lds
+++ /dev/null
@@ -1,100 +0,0 @@
-/*----------------------------------------------------------------------------*/
-/* r5f_linker.cmd */
-/* */
-/* (c) Texas Instruments 2020, All rights reserved. */
-/* */
-
-/* USER CODE BEGIN (0) */
-/* USER CODE END */
---retain="*(.intvecs)"
---retain="*(.intc_text)"
---retain="*(.rstvectors)"
---retain="*(.irqStack)"
---retain="*(.fiqStack)"
---retain="*(.abortStack)"
---retain="*(.undStack)"
---retain="*(.svcStack)"
--stack 0x2000 /* SOFTWARE STACK SIZE */
--heap 0x2000 /* HEAP AREA SIZE */
-
-
-/* Stack Sizes for various modes */
-__IRQ_STACK_SIZE = 0x1000;
-__FIQ_STACK_SIZE = 0x1000;
-__ABORT_STACK_SIZE = 0x1000;
-__UND_STACK_SIZE = 0x1000;
-__SVC_STACK_SIZE = 0x1000;
-
-/*----------------------------------------------------------------------------*/
-/* Linker Settings */
---retain="*(.intvecs)"
--u _resetvectors
-
-/*----------------------------------------------------------------------------*/
-/* Memory Map */
-MEMORY{
-PAGE 0:
- /* Reset Vectors base address(RESET_VECTORS) should be 64 bytes aligned */
- RESET_VECTORS (X) : origin=0x00000000 length=0x100
- /* RESET_VECTORS (X) : origin=0x00020000 length=0x100 */
- TCMA_RAM (RX) : origin=0x00000100 length=0x00003F00
- TCMB_RAM (RW) : origin=0x00080000 length=0x00008000
- SBL_RESERVED_L2_RAM_0 (RW) : origin=0x10200000 length=0x00030000
- SBL_RESERVED_L2_RAM_1 (RW) : origin=0x10230000 length=0x00030000
- L2_RAM_0 (RW) : origin=0x10260000 length=0x00048000
- L2_RAM_1 (RW) : origin=0x102A8000 length=0x00048000
- L3_RAM_0 (RW) : origin=0x88000000 length=0x001C8000
- L3_RAM_1 (RW) : origin=0x881C8000 length=0x001C8000
- HWA_RAM_0 (RW) : origin=0x82000000 length=0x00010000
- HWA_RAM_1 (RW) : origin=0x82010000 length=0x00010000
-
-PAGE 1:
- L3_RAM_0 (RW) : origin=0x88000000 length=0x001C8000
- L3_RAM_1 (RW) : origin=0x881C8000 length=0x001C8000
-}
-
-/*----------------------------------------------------------------------------*/
-/* Section Configuration */
-SECTIONS{
- /* .intvecs : {} palign(8) > VECTORS */
- /* .intc_text : {} palign(8) > VECTORS */
- .rstvectors : {} palign(8) > RESET_VECTORS
- .bootCode : {} palign(8) > TCMA_RAM
- .startupCode : {} palign(8) > TCMA_RAM
- .startupData : {} palign(8) > TCMB_RAM, type = NOINIT
-
- /* The linker notation "X >> Y | Z" indicates section X is first allocated in Y
- and allowed to overflow into Z and can be split from Y to Z.
- The linker notation "X > Y | Z" indicates section X is first allocated in Y
- and allowed to overflow into Z and cannot be split from Y to Z. Some sections
- like bss are not allowed to be split so > notation is used for them
- */
- .text : {} >> TCMA_RAM | L2_RAM_0
-
- .const : {} > L2_RAM_0
- .switch : {} > L2_RAM_0
- .cio: : {} > SBL_RESERVED_L2_RAM_0 | L2_RAM_0
- .data: : {} > L2_RAM_0
-
- .cinit : {} > L2_RAM_0
- .pinit : {} > L2_RAM_0
- .bss : {} > SBL_RESERVED_L2_RAM_0 | L2_RAM_0
- .stack : {} > TCMB_RAM | SBL_RESERVED_L2_RAM_0 | L2_RAM_0
- .sysmem : {} > SBL_RESERVED_L2_RAM_0 | L2_RAM_0
- .irqStack : {. = . + __IRQ_STACK_SIZE;} align(4) > L2_RAM_0 (HIGH)
- RUN_START(__IRQ_STACK_START)
- RUN_END(__IRQ_STACK_END)
- .fiqStack : {. = . + __FIQ_STACK_SIZE;} align(4) > L2_RAM_0 (HIGH)
- RUN_START(__FIQ_STACK_START)
- RUN_END(__FIQ_STACK_END)
- .abortStack : {. = . + __ABORT_STACK_SIZE;} align(4)> L2_RAM_0 (HIGH)
- RUN_START(__ABORT_STACK_START)
- RUN_END(__ABORT_STACK_END)
- .undStack : {. = . + __UND_STACK_SIZE;} align(4) > L2_RAM_0 (HIGH)
- RUN_START(__UND_STACK_START)
- RUN_END(__UND_STACK_END)
- .svcStack : {. = . + __SVC_STACK_SIZE;} align(4) > L2_RAM_0 (HIGH)
- RUN_START(__SVC_STACK_START)
- RUN_END(__SVC_STACK_END)
-}
-/*----------------------------------------------------------------------------*/
diff --git a/packages/ti/build/tpr12/linker_mcu1_0_freertos.lds b/packages/ti/build/tpr12/linker_mcu1_0_freertos.lds
+++ /dev/null
@@ -1,96 +0,0 @@
-/*----------------------------------------------------------------------------*/
-/* r5f_linker.cmd */
-/* */
-/* (c) Texas Instruments 2020, All rights reserved. */
-/* */
-
-/* USER CODE BEGIN (0) */
-/* USER CODE END */
---retain="*(.intc_text)"
---retain="*(.irqStack)"
---retain="*(.fiqStack)"
---retain="*(.abortStack)"
---retain="*(.undStack)"
---retain="*(.svcStack)"
--stack 0x2000 /* SOFTWARE STACK SIZE */
--heap 0x1000 /* HEAP AREA SIZE */
-
--u _freertosresetvectors
-
-/* Stack Sizes for various modes */
-__IRQ_STACK_SIZE = 0x4000;
-__FIQ_STACK_SIZE = 0x4000;
-__ABORT_STACK_SIZE = 0x4000;
-__UND_STACK_SIZE = 0x4000;
-__SVC_STACK_SIZE = 0x4000;
-
-/*----------------------------------------------------------------------------*/
-/* Linker Settings */
-
-/*----------------------------------------------------------------------------*/
-/* Memory Map */
-MEMORY{
-PAGE 0:
- /* Reset Vectors base address(RESET_VECTORS) should be 64 bytes aligned */
- RESET_VECTORS (X) : origin=0x00000000 length=0x100
- /* RESET_VECTORS (X) : origin=0x00020000 length=0x100 */
- TCMA_RAM (RX) : origin=0x00000100 length=0x00003F00
- TCMB_RAM (RW) : origin=0x00080000 length=0x00008000
- SBL_RESERVED_L2_RAM_0 (RW) : origin=0x10200000 length=0x00030000
- SBL_RESERVED_L2_RAM_1 (RW) : origin=0x10230000 length=0x00030000
- L2_RAM_0 (RW) : origin=0x10260000 length=0x00048000
- L2_RAM_1 (RW) : origin=0x102A8000 length=0x00048000
- L3_RAM_0 (RW) : origin=0x88000000 length=0x001C8000
- L3_RAM_1 (RW) : origin=0x881C8000 length=0x001C8000
- HWA_RAM_0 (RW) : origin=0x82000000 length=0x00010000
- HWA_RAM_1 (RW) : origin=0x82010000 length=0x00010000
-
-PAGE 1:
- L3_RAM_0 (RW) : origin=0x88000000 length=0x001C8000
- L3_RAM_1 (RW) : origin=0x881C8000 length=0x001C8000
-}
-
-/*----------------------------------------------------------------------------*/
-/* Section Configuration */
-SECTIONS{
- .freertosrstvectors : {} palign(8) > RESET_VECTORS
- .bootCode : {} palign(8) > TCMA_RAM
- .startupCode : {} palign(8) > TCMA_RAM
- .text.hwi : {} palign(8) > TCMA_RAM
- .startupData : {} palign(8) > TCMB_RAM, type = NOINIT
-
- /* The linker notation "X >> Y | Z" indicates section X is first allocated in Y
- and allowed to overflow into Z and can be split from Y to Z.
- The linker notation "X > Y | Z" indicates section X is first allocated in Y
- and allowed to overflow into Z and cannot be split from Y to Z. Some sections
- like bss are not allowed to be split so > notation is used for them
- */
- .text : {} >> TCMA_RAM | L2_RAM_0
-
- .const : {} > L2_RAM_0
- .switch : {} > L2_RAM_0
- .cio: : {} > SBL_RESERVED_L2_RAM_0 | L2_RAM_0
- .data: : {} > L2_RAM_0
-
- .cinit : {} > L2_RAM_0
- .pinit : {} > L2_RAM_0
- .bss : {} > SBL_RESERVED_L2_RAM_0 | L2_RAM_0
- .stack : {} > TCMB_RAM | SBL_RESERVED_L2_RAM_0 | L2_RAM_0
- .sysmem : {} > SBL_RESERVED_L2_RAM_0 | L2_RAM_0
- .irqStack : {. = . + __IRQ_STACK_SIZE;} align(4) > L2_RAM_0 (HIGH)
- RUN_START(__IRQ_STACK_START)
- RUN_END(__IRQ_STACK_END)
- .fiqStack : {. = . + __FIQ_STACK_SIZE;} align(4) > L2_RAM_0 (HIGH)
- RUN_START(__FIQ_STACK_START)
- RUN_END(__FIQ_STACK_END)
- .abortStack : {. = . + __ABORT_STACK_SIZE;} align(4)> L2_RAM_0 (HIGH)
- RUN_START(__ABORT_STACK_START)
- RUN_END(__ABORT_STACK_END)
- .undStack : {. = . + __UND_STACK_SIZE;} align(4) > L2_RAM_0 (HIGH)
- RUN_START(__UND_STACK_START)
- RUN_END(__UND_STACK_END)
- .svcStack : {. = . + __SVC_STACK_SIZE;} align(4) > L2_RAM_0 (HIGH)
- RUN_START(__SVC_STACK_START)
- RUN_END(__SVC_STACK_END)
-}
-/*----------------------------------------------------------------------------*/
diff --git a/packages/ti/build/tpr12/linker_mcu1_0_sysbios.lds b/packages/ti/build/tpr12/linker_mcu1_0_sysbios.lds
+++ /dev/null
@@ -1,69 +0,0 @@
-/*----------------------------------------------------------------------------*/
-/* r4f_linker.cmd */
-/* */
-/* (c) Texas Instruments 2016, All rights reserved. */
-/* */
-
-/* USER CODE BEGIN (0) */
-/* USER CODE END */
-
-
-/*----------------------------------------------------------------------------*/
-/* Linker Settings */
---retain="*(.intvecs)"
-
-/*----------------------------------------------------------------------------*/
-/* Memory Map */
-MEMORY{
-PAGE 0:
- VECTORS (X) : origin=0x00000000 length=0x00000100
- TCMA_RAM (RX) : origin=0x00000100 length=0x00003F00
- TCMB_RAM (RW) : origin=0x00080000 length=0x00008000
- SBL_RESERVED_L2_RAM_0 (RW) : origin=0x10200000 length=0x00030000
- SBL_RESERVED_L2_RAM_1 (RW) : origin=0x10230000 length=0x00030000
- L2_RAM_0 (RW) : origin=0x10260000 length=0x00048000
- L2_RAM_1 (RW) : origin=0x102A8000 length=0x00048000
- L3_RAM_0 (RW) : origin=0x88000000 length=0x001C8000
- L3_RAM_1 (RW) : origin=0x881C8000 length=0x001C8000
- HWA_RAM_0 (RW) : origin=0x82000000 length=0x00010000
- HWA_RAM_1 (RW) : origin=0x82010000 length=0x00010000
-
-PAGE 1:
- L3_RAM_0 (RW) : origin=0x88000000 length=0x001C8000
- L3_RAM_1 (RW) : origin=0x881C8000 length=0x001C8000
-}
-
-/*----------------------------------------------------------------------------*/
-/* Section Configuration */
-SECTIONS{
- .intvecs : {} > VECTORS
-
- /* The linker notation "X >> Y | Z" indicates section X is first allocated in Y
- and allowed to overflow into Z and can be split from Y to Z.
- The linker notation "X > Y | Z" indicates section X is first allocated in Y
- and allowed to overflow into Z and cannot be split from Y to Z. Some sections
- like bss are not allowed to be split so > notation is used for them
- */
- .text : {} >> TCMA_RAM | L2_RAM_0
-
- .const : {} > L2_RAM_0
- .switch : {} > L2_RAM_0
- .cio: : {} > SBL_RESERVED_L2_RAM_0 | L2_RAM_0
- .data: : {} > L2_RAM_0
-
- .cinit : {} > L2_RAM_0
- .pinit : {} > L2_RAM_0
- .bss : {} > SBL_RESERVED_L2_RAM_0 | L2_RAM_0
- .stack : {} > TCMB_RAM | SBL_RESERVED_L2_RAM_0 | L2_RAM_0
-
- .boot:{
- *.*(*ti_sysbios_family_arm_MPU*)
- boot.aer5f*(*.text)
- *.*(*startup*)
- *.*(*Startup*)
- *.*(*Cache*)
- } > TCMA_RAM | TCMB_RAM
- .l3ram : {} > L3_RAM_0
- .l2ram : {} > SBL_RESERVED_L2_RAM_0 | L2_RAM_0
-}
-/*----------------------------------------------------------------------------*/
diff --git a/packages/ti/build/tpr12/linker_mcu1_1.lds b/packages/ti/build/tpr12/linker_mcu1_1.lds
+++ /dev/null
@@ -1,100 +0,0 @@
-/*----------------------------------------------------------------------------*/
-/* r5f_linker.cmd */
-/* */
-/* (c) Texas Instruments 2020, All rights reserved. */
-/* */
-
-/* USER CODE BEGIN (0) */
-/* USER CODE END */
---retain="*(.intvecs)"
---retain="*(.intc_text)"
---retain="*(.rstvectors)"
---retain="*(.irqStack)"
---retain="*(.fiqStack)"
---retain="*(.abortStack)"
---retain="*(.undStack)"
---retain="*(.svcStack)"
--stack 0x2000 /* SOFTWARE STACK SIZE */
--heap 0x2000 /* HEAP AREA SIZE */
-
-
-/* Stack Sizes for various modes */
-__IRQ_STACK_SIZE = 0x1000;
-__FIQ_STACK_SIZE = 0x1000;
-__ABORT_STACK_SIZE = 0x1000;
-__UND_STACK_SIZE = 0x1000;
-__SVC_STACK_SIZE = 0x1000;
-
-/*----------------------------------------------------------------------------*/
-/* Linker Settings */
---retain="*(.intvecs)"
--u _resetvectors
-
-/*----------------------------------------------------------------------------*/
-/* Memory Map */
-MEMORY{
-PAGE 0:
- /* Reset Vectors base address(RESET_VECTORS) should be 64 bytes aligned */
- RESET_VECTORS (X) : origin=0x00000000 length=0x100
- /* RESET_VECTORS (X) : origin=0x00020000 length=0x100 */
- TCMA_RAM (RX) : origin=0x00000100 length=0x00003F00
- TCMB_RAM (RW) : origin=0x00080000 length=0x00008000
- SBL_RESERVED_L2_RAM_0 (RW) : origin=0x10200000 length=0x00030000
- SBL_RESERVED_L2_RAM_1 (RW) : origin=0x10230000 length=0x00030000
- L2_RAM_0 (RW) : origin=0x10260000 length=0x00048000
- L2_RAM_1 (RW) : origin=0x102A8000 length=0x00048000
- L3_RAM_0 (RW) : origin=0x88000000 length=0x001C8000
- L3_RAM_1 (RW) : origin=0x881C8000 length=0x001C8000
- HWA_RAM_0 (RW) : origin=0x82000000 length=0x00010000
- HWA_RAM_1 (RW) : origin=0x82010000 length=0x00010000
-
-PAGE 1:
- L3_RAM_0 (RW) : origin=0x88000000 length=0x001C8000
- L3_RAM_1 (RW) : origin=0x881C8000 length=0x001C8000
-}
-
-/*----------------------------------------------------------------------------*/
-/* Section Configuration */
-SECTIONS{
- /* .intvecs : {} palign(8) > VECTORS */
- /* .intc_text : {} palign(8) > VECTORS */
- .rstvectors : {} palign(8) > RESET_VECTORS
- .bootCode : {} palign(8) > TCMA_RAM
- .startupCode : {} palign(8) > TCMA_RAM
- .startupData : {} palign(8) > TCMB_RAM, type = NOINIT
-
- /* The linker notation "X >> Y | Z" indicates section X is first allocated in Y
- and allowed to overflow into Z and can be split from Y to Z.
- The linker notation "X > Y | Z" indicates section X is first allocated in Y
- and allowed to overflow into Z and cannot be split from Y to Z. Some sections
- like bss are not allowed to be split so > notation is used for them
- */
- .text : {} >> TCMA_RAM | L2_RAM_1
-
- .const : {} > L2_RAM_1
- .switch : {} > L2_RAM_1
- .cio: : {} > SBL_RESERVED_L2_RAM_1 | L2_RAM_1
- .data: : {} > L2_RAM_1
-
- .cinit : {} > L2_RAM_1
- .pinit : {} > L2_RAM_1
- .bss : {} > SBL_RESERVED_L2_RAM_1 | L2_RAM_1
- .stack : {} > TCMB_RAM | SBL_RESERVED_L2_RAM_1 | L2_RAM_1
- .sysmem : {} > SBL_RESERVED_L2_RAM_1 | L2_RAM_1
- .irqStack : {. = . + __IRQ_STACK_SIZE;} align(4) > L2_RAM_1 (HIGH)
- RUN_START(__IRQ_STACK_START)
- RUN_END(__IRQ_STACK_END)
- .fiqStack : {. = . + __FIQ_STACK_SIZE;} align(4) > L2_RAM_1 (HIGH)
- RUN_START(__FIQ_STACK_START)
- RUN_END(__FIQ_STACK_END)
- .abortStack : {. = . + __ABORT_STACK_SIZE;} align(4)> L2_RAM_1 (HIGH)
- RUN_START(__ABORT_STACK_START)
- RUN_END(__ABORT_STACK_END)
- .undStack : {. = . + __UND_STACK_SIZE;} align(4) > L2_RAM_1 (HIGH)
- RUN_START(__UND_STACK_START)
- RUN_END(__UND_STACK_END)
- .svcStack : {. = . + __SVC_STACK_SIZE;} align(4) > L2_RAM_1 (HIGH)
- RUN_START(__SVC_STACK_START)
- RUN_END(__SVC_STACK_END)
-}
-/*----------------------------------------------------------------------------*/
diff --git a/packages/ti/build/tpr12/linker_mcu1_1_freertos.lds b/packages/ti/build/tpr12/linker_mcu1_1_freertos.lds
+++ /dev/null
@@ -1,96 +0,0 @@
-/*----------------------------------------------------------------------------*/
-/* r5f_linker.cmd */
-/* */
-/* (c) Texas Instruments 2020, All rights reserved. */
-/* */
-
-/* USER CODE BEGIN (0) */
-/* USER CODE END */
---retain="*(.intc_text)"
---retain="*(.irqStack)"
---retain="*(.fiqStack)"
---retain="*(.abortStack)"
---retain="*(.undStack)"
---retain="*(.svcStack)"
--stack 0x2000 /* SOFTWARE STACK SIZE */
--heap 0x1000 /* HEAP AREA SIZE */
-
--u _freertosresetvectors
-
-/* Stack Sizes for various modes */
-__IRQ_STACK_SIZE = 0x4000;
-__FIQ_STACK_SIZE = 0x4000;
-__ABORT_STACK_SIZE = 0x4000;
-__UND_STACK_SIZE = 0x4000;
-__SVC_STACK_SIZE = 0x4000;
-
-/*----------------------------------------------------------------------------*/
-/* Linker Settings */
-
-/*----------------------------------------------------------------------------*/
-/* Memory Map */
-MEMORY{
-PAGE 0:
- /* Reset Vectors base address(RESET_VECTORS) should be 64 bytes aligned */
- RESET_VECTORS (X) : origin=0x00000000 length=0x100
- /* RESET_VECTORS (X) : origin=0x00020000 length=0x100 */
- TCMA_RAM (RX) : origin=0x00000100 length=0x00003F00
- TCMB_RAM (RW) : origin=0x00080000 length=0x00008000
- SBL_RESERVED_L2_RAM_0 (RW) : origin=0x10200000 length=0x00030000
- SBL_RESERVED_L2_RAM_1 (RW) : origin=0x10230000 length=0x00030000
- L2_RAM_0 (RW) : origin=0x10260000 length=0x00048000
- L2_RAM_1 (RW) : origin=0x102A8000 length=0x00048000
- L3_RAM_0 (RW) : origin=0x88000000 length=0x001C8000
- L3_RAM_1 (RW) : origin=0x881C8000 length=0x001C8000
- HWA_RAM_0 (RW) : origin=0x82000000 length=0x00010000
- HWA_RAM_1 (RW) : origin=0x82010000 length=0x00010000
-
-PAGE 1:
- L3_RAM_0 (RW) : origin=0x88000000 length=0x001C8000
- L3_RAM_1 (RW) : origin=0x881C8000 length=0x001C8000
-}
-
-/*----------------------------------------------------------------------------*/
-/* Section Configuration */
-SECTIONS{
- .freertosrstvectors : {} palign(8) > RESET_VECTORS
- .bootCode : {} palign(8) > TCMA_RAM
- .startupCode : {} palign(8) > TCMA_RAM
- .text.hwi : {} palign(8) > TCMA_RAM
- .startupData : {} palign(8) > TCMB_RAM, type = NOINIT
-
- /* The linker notation "X >> Y | Z" indicates section X is first allocated in Y
- and allowed to overflow into Z and can be split from Y to Z.
- The linker notation "X > Y | Z" indicates section X is first allocated in Y
- and allowed to overflow into Z and cannot be split from Y to Z. Some sections
- like bss are not allowed to be split so > notation is used for them
- */
- .text : {} >> TCMA_RAM | L2_RAM_1
-
- .const : {} > L2_RAM_1
- .switch : {} > L2_RAM_1
- .cio: : {} > SBL_RESERVED_L2_RAM_1 | L2_RAM_1
- .data: : {} > L2_RAM_1
-
- .cinit : {} > L2_RAM_1
- .pinit : {} > L2_RAM_1
- .bss : {} > SBL_RESERVED_L2_RAM_1 | L2_RAM_1
- .stack : {} > TCMB_RAM | SBL_RESERVED_L2_RAM_1 | L2_RAM_1
- .sysmem : {} > SBL_RESERVED_L2_RAM_1 | L2_RAM_1
- .irqStack : {. = . + __IRQ_STACK_SIZE;} align(4) > L2_RAM_1 (HIGH)
- RUN_START(__IRQ_STACK_START)
- RUN_END(__IRQ_STACK_END)
- .fiqStack : {. = . + __FIQ_STACK_SIZE;} align(4) > L2_RAM_1 (HIGH)
- RUN_START(__FIQ_STACK_START)
- RUN_END(__FIQ_STACK_END)
- .abortStack : {. = . + __ABORT_STACK_SIZE;} align(4)> L2_RAM_1 (HIGH)
- RUN_START(__ABORT_STACK_START)
- RUN_END(__ABORT_STACK_END)
- .undStack : {. = . + __UND_STACK_SIZE;} align(4) > L2_RAM_1 (HIGH)
- RUN_START(__UND_STACK_START)
- RUN_END(__UND_STACK_END)
- .svcStack : {. = . + __SVC_STACK_SIZE;} align(4) > L2_RAM_1 (HIGH)
- RUN_START(__SVC_STACK_START)
- RUN_END(__SVC_STACK_END)
-}
-/*----------------------------------------------------------------------------*/
diff --git a/packages/ti/build/tpr12/linker_mcu1_1_sysbios.lds b/packages/ti/build/tpr12/linker_mcu1_1_sysbios.lds
+++ /dev/null
@@ -1,69 +0,0 @@
-/*----------------------------------------------------------------------------*/
-/* r4f_linker.cmd */
-/* */
-/* (c) Texas Instruments 2016, All rights reserved. */
-/* */
-
-/* USER CODE BEGIN (0) */
-/* USER CODE END */
-
-
-/*----------------------------------------------------------------------------*/
-/* Linker Settings */
---retain="*(.intvecs)"
-
-/*----------------------------------------------------------------------------*/
-/* Memory Map */
-MEMORY{
-PAGE 0:
- VECTORS (X) : origin=0x00000000 length=0x00000100
- TCMA_RAM (RX) : origin=0x00000100 length=0x00003F00
- TCMB_RAM (RW) : origin=0x00080000 length=0x00008000
- SBL_RESERVED_L2_RAM_0 (RW) : origin=0x10200000 length=0x00030000
- SBL_RESERVED_L2_RAM_1 (RW) : origin=0x10230000 length=0x00030000
- L2_RAM_0 (RW) : origin=0x10260000 length=0x00048000
- L2_RAM_1 (RW) : origin=0x102A8000 length=0x00048000
- L3_RAM_0 (RW) : origin=0x88000000 length=0x001C8000
- L3_RAM_1 (RW) : origin=0x881C8000 length=0x001C8000
- HWA_RAM_0 (RW) : origin=0x82000000 length=0x00010000
- HWA_RAM_1 (RW) : origin=0x82010000 length=0x00010000
-
-PAGE 1:
- L3_RAM_0 (RW) : origin=0x88000000 length=0x001C8000
- L3_RAM_1 (RW) : origin=0x881C8000 length=0x001C8000
-}
-
-/*----------------------------------------------------------------------------*/
-/* Section Configuration */
-SECTIONS{
- .intvecs : {} > VECTORS
-
- /* The linker notation "X >> Y | Z" indicates section X is first allocated in Y
- and allowed to overflow into Z and can be split from Y to Z.
- The linker notation "X > Y | Z" indicates section X is first allocated in Y
- and allowed to overflow into Z and cannot be split from Y to Z. Some sections
- like bss are not allowed to be split so > notation is used for them
- */
- .text : {} >> TCMA_RAM | L2_RAM_1
-
- .const : {} > L2_RAM_1
- .switch : {} > L2_RAM_1
- .cio: : {} > SBL_RESERVED_L2_RAM_1 | L2_RAM_1
- .data: : {} > L2_RAM_1
-
- .cinit : {} > L2_RAM_1
- .pinit : {} > L2_RAM_1
- .bss : {} > SBL_RESERVED_L2_RAM_1 | L2_RAM_1
- .stack : {} > TCMB_RAM | SBL_RESERVED_L2_RAM_1 | L2_RAM_1
-
- .boot:{
- *.*(*ti_sysbios_family_arm_MPU*)
- boot.aer5f*(*.text)
- *.*(*startup*)
- *.*(*Startup*)
- *.*(*Cache*)
- } > TCMA_RAM | TCMB_RAM
- .l3ram : {} > L3_RAM_1
- .l2ram : {} > SBL_RESERVED_L2_RAM_1 | L2_RAM_1
-}
-/*----------------------------------------------------------------------------*/
diff --git a/packages/ti/build/tpr12/r5_mpu.xs b/packages/ti/build/tpr12/r5_mpu.xs
+++ /dev/null
@@ -1,119 +0,0 @@
-/*
- * Copyright (c) 2020, Texas Instruments Incorporated
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * * Neither the name of Texas Instruments Incorporated nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
- * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
- * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
- * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
- * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-/*
- * ======== event_MPU.xs ========
- * MPU Settings for TPR12 device's Cortex-R5F
- */
-
-/*
- * -------------------------------------------------------------------------------------------------------------
- * | Id | Base Address | Size | En | Cacheable | XN | AccPerm | Mask |
- * |-------------------------------------------------------------------------------------------------------------|
- * | 0 | 0x00000000 | 4GB | T | Strongly Ordered, Shareable | T | RW at PL 1 | 0x0 |
- * |----|--------------|------|----|-------------------------------------------|----|---------------------|------|
- * | 1 | 0x00000000 | 32K | T | Write-Back, Write-Allocate, Non-Shareable | F | RW at PL 1 | 0x0 |
- * |----|--------------|------|----|-------------------------------------------|----|---------------------|------|
- * | 2 | 0x00080000 | 32K | T | Write-Back, Write-Allocate, Non-Shareable | F | RW at PL 1 | 0x0 |
- * |----|--------------|------|----|-------------------------------------------|----|---------------------|------|
- * | 3 | 0x10200000 | 1M | T | Write-Back, Write-Allocate, Non-Shareable | F | RW at PL 1 | 0x0 |
- * |----|--------------|------|----|-------------------------------------------|----|---------------------|------|
- * | 4 | 0x88000000 | 4M | T | Write-Back, Write-Allocate, Non-Shareable | F | RW at PL 1 | 0x0 |
- * -------------------------------------------------------------------------------------------------------------
- */
-
-/*
- * Note: Marking a region as shareable will cause the region to behave as outer shareable with write through
- * no write-allocate caching policy irrespective of the actual cache policy set. Therefore, only select
- * regions that are actually shared outside the R5 CPUSS must be marked as shared.
- */
-
-var MPU = xdc.useModule('ti.sysbios.family.arm.MPU');
-MPU.enableMPU = true;
-MPU.enableBackgroundRegion = true;
-
-var attrs = new MPU.RegionAttrs();
-MPU.initRegionAttrsMeta(attrs);
-
-attrs.enable = true;
-attrs.bufferable = false;
-attrs.cacheable = false;
-attrs.shareable = true;
-attrs.noExecute = true;
-attrs.accPerm = 1; /* RW at PL1 */
-attrs.tex = 0;
-attrs.subregionDisableMask = 0;
-MPU.setRegionMeta(0, 0x00000000, MPU.RegionSize_4G, attrs);
-
-/* TCMA */
-attrs.enable = true;
-attrs.bufferable = true;
-attrs.cacheable = true;
-attrs.shareable = false;
-attrs.noExecute = false;
-attrs.accPerm = 1; /* RW at PL1 */
-attrs.tex = 1;
-attrs.subregionDisableMask = 0;
-MPU.setRegionMeta(1, 0x00000000, MPU.RegionSize_32K, attrs);
-
-/* TCMB */
-attrs.enable = true;
-attrs.bufferable = true;
-attrs.cacheable = true;
-attrs.shareable = false;
-attrs.noExecute = false;
-attrs.accPerm = 1; /* RW at PL1 */
-attrs.tex = 1;
-attrs.subregionDisableMask = 0;
-MPU.setRegionMeta(2, 0x00080000, MPU.RegionSize_32K, attrs);
-
-/* L2 */
-attrs.enable = true;
-attrs.bufferable = true;
-attrs.cacheable = true;
-attrs.shareable = false;
-attrs.noExecute = false;
-attrs.accPerm = 1; /* RW at PL1 */
-attrs.tex = 1;
-attrs.subregionDisableMask = 0;
-MPU.setRegionMeta(3, 0x10200000, MPU.RegionSize_1M, attrs);
-
-/* L3 */
-attrs.enable = true;
-attrs.bufferable = true;
-attrs.cacheable = true;
-attrs.shareable = false;
-attrs.noExecute = false;
-attrs.accPerm = 1; /* RW at PL1 */
-attrs.tex = 1;
-attrs.subregionDisableMask = 0;
-MPU.setRegionMeta(4, 0x88000000, MPU.RegionSize_4M, attrs);
-
diff --git a/packages/ti/build/tpr12/sysbios_c66.cfg b/packages/ti/build/tpr12/sysbios_c66.cfg
+++ /dev/null
@@ -1,92 +0,0 @@
-/* =============================================================================
- * Copyright (c) Texas Instruments Incorporated 2020
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the
- * distribution.
- *
- * Neither the name of Texas Instruments Incorporated nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-environment['xdc.cfg.check.fatal'] = 'false';
-
-/********************************************************************
- ************************** BIOS Modules ****************************
- ********************************************************************/
-var Memory = xdc.useModule('xdc.runtime.Memory');
-var BIOS = xdc.useModule('ti.sysbios.BIOS');
-var HeapMem = xdc.useModule('ti.sysbios.heaps.HeapMem');
-var HeapBuf = xdc.useModule('ti.sysbios.heaps.HeapBuf');
-var Task = xdc.useModule('ti.sysbios.knl.Task');
-var Idle = xdc.useModule('ti.sysbios.knl.Idle');
-var SEM = xdc.useModule('ti.sysbios.knl.Semaphore');
-var Event = xdc.useModule('ti.sysbios.knl.Event');
-var System = xdc.useModule('xdc.runtime.System');
-var SysStd = xdc.useModule('xdc.runtime.SysStd');
-var SysMin = xdc.useModule('xdc.runtime.SysMin');
-var Timestamp = xdc.useModule('xdc.runtime.Timestamp');
-var Hwi = xdc.useModule('ti.sysbios.family.c64p.Hwi');
-var EventCombiner = xdc.useModule('ti.sysbios.family.c64p.EventCombiner');
-var GateMutexPri = xdc.useModule('ti.sysbios.gates.GateMutexPri');
-
-/* Enable Timer */
-var Timer = xdc.useModule('ti.sysbios.timers.rti.Timer');
-
-/*
- * for (var i=0; i < Timer.numTimerDevices; i++) {
- * Timer.intFreqs[i].lo = 200000000;
- * Timer.intFreqs[i].hi = 0;
- *}
-*/
-SysMin.bufSize = 16 * 1024;
-SysMin.flushAtExit = false;
-System.SupportProxy = SysMin;
-
-/* Default Heap Creation: Local L2 memory */
-var heapMemParams = new HeapMem.Params();
-heapMemParams.size = 32*1024;
-Program.global.heap0 = HeapMem.create(heapMemParams);
-Memory.defaultHeapInstance = Program.global.heap0;
-
-/* Remove clock while we are profiling for cycles and don't want BIOS
- periodic interruption */
-BIOS.clockEnabled = true;
-
-/* Enable BIOS Task Scheduler */
-BIOS.taskEnabled = true;
-
-/*
- * BIOS.cpuFreq.lo = 450000000;
- * BIOS.cpuFreq.hi = 0;
- */
-
-/* Check if application needs to update with custom configuration options */
-var cfgUpdate = java.lang.System.getenv("XDC_CFG_UPDATE")
-if ((cfgUpdate != '')&&(cfgUpdate != null))
-{
- xdc.print("Loading configuration update " + cfgUpdate);
- xdc.loadCapsule(cfgUpdate);
-}
-
-
diff --git a/packages/ti/build/tpr12/sysbios_r5f.cfg b/packages/ti/build/tpr12/sysbios_r5f.cfg
+++ /dev/null
@@ -1,138 +0,0 @@
-/* =============================================================================
- * Copyright (c) Texas Instruments Incorporated 2020
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the
- * distribution.
- *
- * Neither the name of Texas Instruments Incorporated nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-environment['xdc.cfg.check.fatal'] = 'false';
-
-/********************************************************************
- ************************** BIOS Modules ****************************
- ********************************************************************/
-var Memory = xdc.useModule('xdc.runtime.Memory');
-var BIOS = xdc.useModule('ti.sysbios.BIOS');
-var HeapMem = xdc.useModule('ti.sysbios.heaps.HeapMem');
-var HeapBuf = xdc.useModule('ti.sysbios.heaps.HeapBuf');
-var Task = xdc.useModule('ti.sysbios.knl.Task');
-var Idle = xdc.useModule('ti.sysbios.knl.Idle');
-var SEM = xdc.useModule('ti.sysbios.knl.Semaphore');
-var Event = xdc.useModule('ti.sysbios.knl.Event');
-var Hwi = xdc.useModule('ti.sysbios.family.arm.v7r.keystone3.Hwi');
-var Core = xdc.useModule('ti.sysbios.family.arm.v7r.keystone3.Core');
-var System = xdc.useModule('xdc.runtime.System');
-var SysStd = xdc.useModule('xdc.runtime.SysStd');
-var SysMin = xdc.useModule('xdc.runtime.SysMin');
-var Timestamp = xdc.useModule('xdc.runtime.Timestamp');
-var Pmu = xdc.useModule('ti.sysbios.family.arm.v7a.Pmu');
-var GateMutexPri = xdc.useModule('ti.sysbios.gates.GateMutexPri');
-
-/*
- * Initialize MPU and enable it
- *
- * Note: MPU must be enabled and properly configured for caching to work.
- */
-xdc.loadCapsule("r5_mpu.xs");
-
-/* Enable cache */
-var Cache = xdc.useModule('ti.sysbios.family.arm.v7r.Cache');
-Cache.enableCache = true;
-
-SysMin.bufSize = 16 * 1024;
-SysMin.flushAtExit = false;
-System.SupportProxy = SysMin;
-
-/* FIQ Stack Usage: */
-Hwi.fiqStackSize = 2048;
-Hwi.fiqStackSection = ".myFiqStack"
-
-/* Sysbios supports workaround for Silicon issue https://jira.itg.ti.com/browse/K3_OPEN_SI-148
- * Details of silicon issue : https://confluence.itg.ti.com/display/PROCIPDEV/%2310+The+same+interrupt+cannot+be+nested+back-2-back+within+another+interrupt
- * Sysbios Requirement Details: https://jira.itg.ti.com/browse/SYSBIOS-1419
- * Workaround requires use of a resevred dummyIRQ.
- * Using DummyIRQ#255 as per cslr_intr_mss.h it is a reserved interrupt not connected to any
- * peripheral interrupt sources
- */
-Hwi.dummyIRQ = 255;
-
-var coreId = java.lang.System.getenv("CORE");
-
-/* Set base address of Vector Interrupt Manager */
-if(coreId=="mcu1_0")
-{
- Core.id = 0;
- Hwi.vimBaseAddress = 0x02080000;
-}
-if(coreId=="mcu1_1")
-{
- Core.id = 1;
- Hwi.vimBaseAddress = 0x020A0000;
-}
-
-Program.sectMap[".myFiqStack"] = "TCMB_RAM";
-
-/* Default Heap Creation: Local L2 memory */
-var heapMemParams = new HeapMem.Params();
-heapMemParams.size = 32*1024;
-Program.global.heap0 = HeapMem.create(heapMemParams);
-Memory.defaultHeapInstance = Program.global.heap0;
-
-/* Enable Timer */
-var Timer = xdc.useModule('ti.sysbios.timers.rti.Timer');
-
-/*
- * for (var i=0; i < Timer.numTimerDevices; i++) {
- * Timer.intFreqs[i].lo = 200000000;
- * Timer.intFreqs[i].hi = 0;
- *}
-*/
-
-/* Remove clock while we are profiling for cycles and don't want BIOS
- periodic interruption. */
-BIOS.clockEnabled = true;
-
-/* Enable BIOS Task Scheduler */
-BIOS.taskEnabled = true;
-
-Program.sectMap[".vecs"] = "VECTORS";
-
-/* Make sure libraries are built with 32-bit enum types to be compatible with DSP enum types*/
-BIOS.includeXdcRuntime = true;
-BIOS.libType = BIOS.LibType_Custom;
-BIOS.customCCOpts += " --enum_type=int ";
-/*
- * BIOS.cpuFreq.lo = 400000000;
- * BIOS.cpuFreq.hi = 0;
- */
-
-/* Check if application needs to update with custom configuration options */
-var cfgUpdate = java.lang.System.getenv("XDC_CFG_UPDATE")
-if ((cfgUpdate != '')&&(cfgUpdate != null))
-{
- xdc.print("Loading configuration update " + cfgUpdate);
- xdc.loadCapsule(cfgUpdate);
-}