summary | shortlog | log | commit | commitdiff | tree
raw | patch | inline | side by side (parent: 5d02f51)
raw | patch | inline | side by side (parent: 5d02f51)
author | Sheng Zhao <shengzhao@ti.com> | |
Wed, 20 Jan 2021 20:45:37 +0000 (14:45 -0600) | ||
committer | Sheng Zhao <shengzhao@ti.com> | |
Wed, 20 Jan 2021 20:45:37 +0000 (14:45 -0600) |
Updates to launch.js based on latest CSP package made for public consumption.
When R5 is connected, the DDR will not be configured automatically.
After the sciclient_ccs_init runs, the launch.js explicitly calls
AM64_DDR_Initialization_ECC_Disabled() to configure the DDR.
CSP commit:
https://bitbucket.itg.ti.com/projects/CPHWA/repos/k3_ccs/commits/662bc078f8ccee26024a80bd648803872a31b5e6
Signed-off-by: Sheng Zhao <shengzhao@ti.com>
When R5 is connected, the DDR will not be configured automatically.
After the sciclient_ccs_init runs, the launch.js explicitly calls
AM64_DDR_Initialization_ECC_Disabled() to configure the DDR.
CSP commit:
https://bitbucket.itg.ti.com/projects/CPHWA/repos/k3_ccs/commits/662bc078f8ccee26024a80bd648803872a31b5e6
Signed-off-by: Sheng Zhao <shengzhao@ti.com>
packages/ti/drv/sciclient/tools/ccsLoadDmsc/am64x/launch.js | patch | blob | history |
diff --git a/packages/ti/drv/sciclient/tools/ccsLoadDmsc/am64x/launch.js b/packages/ti/drv/sciclient/tools/ccsLoadDmsc/am64x/launch.js
index e54402ac837c0960c894d140e8b8c5e3949d668c..1a5c8b710e6c30672adf3ffc1f2d54a4be6c392d 100755 (executable)
dsMCU1_0.target.run();
/* Run the DDR Configuration */
- /* RAT Config for OCSRAM SYSFW load */
print("Running the DDR configuration... Wait till it completes!");
- dsDMSC_0.target.halt();
- /* Reconfigure RAT for the GEL script to run */
- dsDMSC_0.memory.writeWord(0, 0x44200034, 0x00080000);
- dsDMSC_0.memory.writeWord(0, 0x44200038, 0x44080000);
- dsDMSC_0.memory.writeWord(0, 0x4420003C, 0x00000000);
- dsDMSC_0.memory.writeWord(0, 0x44200030, 0x80000011);
-
- dsDMSC_0.memory.writeWord(0, 0x44200044, 0x60000000);
- dsDMSC_0.memory.writeWord(0, 0x44200048, 0x40000000);
- dsDMSC_0.memory.writeWord(0, 0x4420004C, 0x00000000);
- dsDMSC_0.memory.writeWord(0, 0x44200040, 0x8000001D);
-
- dsDMSC_0.memory.writeWord(0, 0x44200054, 0x80000000);
- dsDMSC_0.memory.writeWord(0, 0x44200058, 0x00000000);
- dsDMSC_0.memory.writeWord(0, 0x4420005C, 0x00000000);
- dsDMSC_0.memory.writeWord(0, 0x44200050, 0x8000001D);
-
- dsDMSC_0.expression.evaluate("DDR_Init()");
-
- dsDMSC_0.memory.writeWord(0, 0x44200034, 0x60000000);
- dsDMSC_0.memory.writeWord(0, 0x44200038, 0x00000000);
- dsDMSC_0.memory.writeWord(0, 0x4420003C, 0x00000000);
- dsDMSC_0.memory.writeWord(0, 0x44200030, 0x8000001D);
-
- dsDMSC_0.memory.writeWord(0, 0x44200044, 0x80000000);
- dsDMSC_0.memory.writeWord(0, 0x44200048, 0x20000000);
- dsDMSC_0.memory.writeWord(0, 0x4420004C, 0x00000000);
- dsDMSC_0.memory.writeWord(0, 0x44200040, 0x8000001D);
-
- dsDMSC_0.memory.writeWord(0, 0x44200054, 0xA0000000);
- dsDMSC_0.memory.writeWord(0, 0x44200058, 0x40000000);
- dsDMSC_0.memory.writeWord(0, 0x4420005C, 0x00000000);
- dsDMSC_0.memory.writeWord(0, 0x44200050, 0x8000001D);
-
- dsDMSC_0.target.runAsynch();
+ dsMCU1_0.target.halt();
+ dsMCU1_0.expression.evaluate("AM64_DDR_Initialization_ECC_Disabled()");
}
function disconnectTargets()