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raw | patch | inline | side by side (parent: 67b1a50)
author | Badri S <badri@ti.com> | |
Fri, 30 Oct 2020 13:22:22 +0000 (18:52 +0530) | ||
committer | Sivaraj R <sivaraj@ti.com> | |
Sat, 31 Oct 2020 04:09:47 +0000 (23:09 -0500) |
Common code affecting multiple SoC was modified during TPR12 bringup
The changes are reverted to not affect other SoCs and changes required
for TPR12 are added under SoC specific defines
Signed-off-by: Badri S <badri@ti.com>
The changes are reverted to not affect other SoCs and changes required
for TPR12 are added under SoC specific defines
Signed-off-by: Badri S <badri@ti.com>
packages/ti/drv/mibspi/src/mibspi_priv.c | patch | blob | history | |
packages/ti/drv/spi/test/qspi_flash/src/Flash_S25FL/S25FL.c | [changed mode: 0755->0644] | patch | blob | history |
packages/ti/osal/test/src/main_osal_test.c | patch | blob | history |
index ca2ab9ede5e5fcd45c286bd7b0dea7465668fac2..39a1bcb2a05f321412a4a0c2a484247f24abf703 100644 (file)
CSL_FINS(regVal, SPI_SPIPC0_CLKFUN, 1U);
CSL_FINS(regVal, SPI_SPIPC0_SIMOFUN0, 1U);
CSL_FINS(regVal, SPI_SPIPC0_SOMIFUN0, 1U);
-
- //CSL_FINS(regVal, SPI_SPIPC0_SOMIFUN, 0U);
- //CSL_FINS(regVal, SPI_SPIPC0_SOMIFUN, 0U);
ptrMibSpiReg->SPIPC0 = regVal; /* enable SOMI */
break;
diff --git a/packages/ti/drv/spi/test/qspi_flash/src/Flash_S25FL/S25FL.c b/packages/ti/drv/spi/test/qspi_flash/src/Flash_S25FL/S25FL.c
#ifdef SPI_DMA_ENABLE
if (hwAttrs->dmaEnable)
{
+/* TPR12 EVM flash PP (Page program) sequence supported segLen of 32 due to
+ * default wrap depth of the flash device. So setting segLen to 32 for TPR12_EVM
+ * build
+ */
+#if defined (tpr12_evm)
segLen = 32;
+#else
+ segLen = 128;
+#endif
}
#endif
remainSize = length;
return retVal;
}
+#if !defined(tpr12_evm)
+bool S25FLFlash_WriteEnable(S25FL_Handle flashHandle)
+{
+ SPI_Handle handle = flashHandle->spiHandle; /* SPI handle */
+ bool retVal = false; /* return value */
+ unsigned char writeVal; /* data to be written */
+ unsigned int operMode; /* temp variable to hold mode */
+ unsigned int rxLines; /* temp variable to hold rx lines */
+ unsigned int frmLength;
+ unsigned int transferType;
+ QSPI_v1_Object *object;
+ unsigned int rxLinesArg;
+
+ /* Get the pointer to the object and hwAttrs */
+ object = handle->object;
+
+ /* These operations require the qspi to be configured in the following mode
+ only: tx/rx single line and config mode. */
+
+ /* Save the current mode and rxLine configurations */
+ operMode = object->qspiMode;
+ rxLines = object->rxLines;
+
+ /* Update the mode and rxLines with the required values */
+ SPI_control(handle, SPI_V1_CMD_SETCONFIGMODE, NULL);
+
+ rxLinesArg = QSPI_RX_LINES_SINGLE;
+ SPI_control(handle, SPI_V1_CMD_SETRXLINES, (void *)&rxLinesArg);
+
+ /* transaction frame length in words (bytes) */
+ frmLength = 1;
+ SPI_control(handle, SPI_V1_CMD_SETFRAMELENGTH, (void *)&frmLength);
+
+ /* Write enable command */
+ writeVal = QSPI_LIB_CMD_WRITE_ENABLE;
+
+ /* Update transaction parameters */
+ transaction.txBuf = (unsigned char *)&writeVal;
+ transaction.rxBuf = NULL;
+ transaction.count = 1;
+
+ transferType = SPI_TRANSACTION_TYPE_WRITE;
+ SPI_control(handle, SPI_V1_CMD_TRANSFERMODE_RW, (void *)&transferType);
+ retVal = SPI_transfer(handle, &transaction);
+
+ /* Restore operating mode and rx Lines */
+ object->qspiMode = operMode;
+ SPI_control(handle, SPI_V1_CMD_SETRXLINES, (void *)&rxLines);
+
+ return retVal;
+}
+#else /* tpr12_evm case.
+ * tpr12_evm is under #else case instead of #if defined(tpr12_evm) so that
+ * diff in bitbucket shows the version for other SoC correctly as
+ * unchanged correctly
+ */
+/* TPR12 EVM flash requires WREN in a loop until WEL gets set.Hence needs
+ * different function for S25FLFlash_WriteEnable
+ */
bool S25FLFlash_WriteEnable(S25FL_Handle flashHandle)
{
SPI_Handle handle = flashHandle->spiHandle; /* SPI handle */
} while ((flashStatus & 0x2) == 0);
return retVal;
}
-
+#endif
bool S25FLFlash_Enable4ByteAddrMode(S25FL_Handle flashHandle,
bool enable4ByteMode)
rxLinesArg = QSPI_RX_LINES_SINGLE;
SPI_control(handle, SPI_V1_CMD_SETRXLINES, (void *)&rxLinesArg);
-
/* Set transfer length in bytes: Reading status register */
frmLength = 1 + 1;
SPI_control(handle, SPI_V1_CMD_SETFRAMELENGTH, (void *)&frmLength);
diff --git a/packages/ti/osal/test/src/main_osal_test.c b/packages/ti/osal/test/src/main_osal_test.c
index 6eb3512ac4825328e22cbbd7d57fba300a9ed505..cd3451838b79b6760434cbda69a0fdc226b92832 100644 (file)
BOARD_INIT_UART_STDIO;
#else
boardCfg = BOARD_INIT_PINMUX_CONFIG;
+ /* For TPR12 we dont do module clock init from app. This is done by
+ * GEL file or SBL. Doing Module Clock init causes OSAL RTI interrupts
+ * to stop if another core also runs OSAL test
+ */
+ #if !defined(SOC_TPR12)
#if !defined(_TMS320C6X)
boardCfg |= BOARD_INIT_MODULE_CLOCK;
#endif
+ #endif /* !defined(SOC_TPR12) */
#if defined (UART_CONSOLE)
boardCfg |= BOARD_INIT_UART_STDIO;
bool testFail = false;
Osal_StaticMemStatus pMemStats;
-// Board_initOSAL();
+ Board_initOSAL();
#ifdef BUILD_C7X_1
Osal_appC7xPreInit();