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raw | patch | inline | side by side (parent: e31d06e)
author | Vaibhav Jindal <v-jindal@ti.com> | |
Thu, 2 Feb 2023 05:57:13 +0000 (11:27 +0530) | ||
committer | Vaibhav Jindal <v-jindal@ti.com> | |
Thu, 2 Feb 2023 05:57:21 +0000 (11:27 +0530) |
add missing interrupt macros for ping and pong tasks for J784s4
Signed-off-by: Vaibhav Jindal <v-jindal@ti.com>
Signed-off-by: Vaibhav Jindal <v-jindal@ti.com>
packages/ti/transport/lwip/lwip-port/unit_test/test_sys_arch.c | patch | blob | history |
diff --git a/packages/ti/transport/lwip/lwip-port/unit_test/test_sys_arch.c b/packages/ti/transport/lwip/lwip-port/unit_test/test_sys_arch.c
index 4cdf03cc674b480e811abe10a85a3c48b2574d15..d1f0389b39779a55d1644ab9644efc921d8e53c9 100644 (file)
#endif
#endif
+#ifdef SOC_J784S4
+ #ifdef BUILD_MCU1_0
+ #define PING_INT_NUM (CSLR_MCU_R5FSS0_CORE0_INTR_MAIN2MCU_LVL_INTRTR0_OUTL_0)
+ #define PONG_INT_NUM (CSLR_MCU_R5FSS0_CORE0_INTR_MAIN2MCU_LVL_INTRTR0_OUTL_1)
+ #endif
+ #ifdef BUILD_MCU2_0
+ #define PING_INT_NUM (CSLR_R5FSS0_CORE0_INTR_COMPUTE_CLUSTER0_CLEC_SOC_EVENTS_OUT_LEVEL_0)
+ #define PONG_INT_NUM (CSLR_R5FSS0_CORE0_INTR_COMPUTE_CLUSTER0_CLEC_SOC_EVENTS_OUT_LEVEL_1)
+ #endif
+ #ifdef BUILD_MCU2_1
+ #define PING_INT_NUM (CSLR_R5FSS0_CORE1_INTR_COMPUTE_CLUSTER0_CLEC_SOC_EVENTS_OUT_LEVEL_0)
+ #define PONG_INT_NUM (CSLR_R5FSS0_CORE1_INTR_COMPUTE_CLUSTER0_CLEC_SOC_EVENTS_OUT_LEVEL_1)
+ #endif
+#endif
+
#define PING_TASK_SIZE (4U * 1024U)
#define PONG_TASK_SIZE (4U * 1024U)