summary | shortlog | log | commit | commitdiff | tree
raw | patch | inline | side by side (parent: e21ee65)
raw | patch | inline | side by side (parent: e21ee65)
| author | Sivaraj R <sivaraj@ti.com> | |
| Tue, 21 Apr 2020 02:37:44 +0000 (08:07 +0530) | ||
| committer | Sivaraj R <sivaraj@ti.com> | |
| Tue, 21 Apr 2020 02:37:44 +0000 (08:07 +0530) |
Signed-off-by: Sivaraj R <sivaraj@ti.com>
169 files changed:
index a99d0958d75aaf3350e217c12eb6e205a5b5e635..d00f0a1f8c9c98a53bb47b8197124c36154dea2a 100644 (file)
#elif defined (j7200_evm)
#include <ti/board/src/j7200_evm/include/board_cfg.h>
+#elif defined (am64x_evm)
+#include <ti/board/src/am64x_evm/include/board_cfg.h>
+
#elif defined (tpr12_evm)
#include <ti/board/src/tpr12_evm/include/board_cfg.h>
index 4c433332686f832608e10ec3178ba57cfdf22c7a..b4bce0db3bf77f80f8e139e4e517413593618dcb 100755 (executable)
ifeq ($(board_component_make_include), )
board_lib_BOARDLIST = evmAM335x icev2AM335x iceAMIC110 skAM335x bbbAM335x evmAM437x idkAM437x skAM437x evmAM572x idkAM571x idkAM572x evmK2H evmK2K evmK2E evmK2L evmK2G iceK2G \
- evmC6678 evmC6657 tda2xx-evm evmDRA75x tda2ex-evm evmDRA72x tda3xx-evm evmDRA78x evmOMAPL137 lcdkOMAPL138 idkAM574x am65xx_evm am65xx_idk j721e_sim j721e_qt j721e_evm j7200_evm \
- tpr12_evm
+ evmC6678 evmC6657 tda2xx-evm evmDRA75x tda2ex-evm evmDRA72x tda3xx-evm evmDRA78x evmOMAPL137 lcdkOMAPL138 idkAM574x am65xx_evm am65xx_idk j721e_sim j721e_qt j721e_evm j7200_evm am64x_evm tpr12_evm
board_lib_tda2xx_CORELIST = a15_0 ipu1_0 c66x
board_lib_tda2ex_CORELIST = a15_0 ipu1_0 c66x
board_lib_tda3xx_CORELIST = ipu1_0 c66x
board_lib_omapl137_CORELIST = arm9_0 c674x
board_lib_omapl138_CORELIST = arm9_0 c674x
board_lib_am65xx_CORELIST = mpu1_0 mcu1_0 mcu1_1
-board_lib_j721e_CORELIST = mpu1_0 mcu1_0 mcu1_1 mcu2_0 mcu2_1 mcu3_0 mcu3_1 c66xdsp_1 c66xdsp_2 c7x_1
-board_lib_j7200_CORELIST = mpu1_0 mcu1_0 mcu1_1 mcu2_0 mcu2_1
-board_lib_tpr12_CORELIST = mcu1_0 c66xdsp_1
+board_lib_j721e_CORELIST = mpu1_0 mcu1_0 mcu1_1 mcu2_0 mcu2_1 mcu3_0 mcu3_1 c66xdsp_1 c66xdsp_2 c7x_1
+board_lib_j7200_CORELIST = mpu1_0 mcu1_0 mcu1_1 mcu2_0 mcu2_1
+board_lib_am64x_CORELIST = mpu1_0 mcu1_0 mcu1_1 mcu2_0 mcu2_1 m4f_0
+board_lib_tpr12_CORELIST = mcu1_0 c66xdsp_1
############################
index 92b92988a743458b34c5c1400b9303a7bb158a2e..e57e99bb523893ce6a15032c33c9261905a62ff1 100644 (file)
PACKAGE_SRCS_COMMON =
-ifeq ($(BOARD),$(filter $(BOARD),evmAM335x icev2AM335x iceAMIC110 skAM335x bbbAM335x evmAM437x idkAM437x skAM437x evmAM572x idkAM571x idkAM572x evmK2H evmK2K evmK2E evmK2L evmK2G iceK2G evmC6678 evmC6657 evmOMAPL137 lcdkOMAPL138 idkAM574x am65xx_evm am65xx_idk tpr12_evm))
+ifeq ($(BOARD),$(filter $(BOARD),evmAM335x icev2AM335x iceAMIC110 skAM335x bbbAM335x evmAM437x idkAM437x skAM437x evmAM572x idkAM571x idkAM572x evmK2H evmK2K evmK2E evmK2L evmK2G iceK2G evmC6678 evmC6657 evmOMAPL137 lcdkOMAPL138 idkAM574x am65xx_evm am65xx_idk am64x_evm tpr12_evm))
# Common source files across all platforms and cores
SRCS_COMMON += board.c
endif
include $(PDK_BOARD_COMP_PATH)/src/j721e_sim/src_files_j721e_sim.mk
include $(PDK_BOARD_COMP_PATH)/src/flash/src_files_flash.mk
PACKAGE_SRCS_COMMON += src/j721e_sim
+CFLAGS_LOCAL_COMMON += -DVLAB_SIM
endif
ifeq ($(BOARD),$(filter $(BOARD), j721e_evm))
CFLAGS_LOCAL_$(BOARD) += -D$(BOARD)=$(BOARD)
endif
+ifeq ($(BOARD),$(filter $(BOARD), am64x_evm))
+CFLAGS_LOCAL_COMMON = $(PDK_CFLAGS)
+CFLAGS_LOCAL_COMMON += -DVLAB_SIM
+include $(PDK_BOARD_COMP_PATH)/src/$(BOARD)/src_files_$(BOARD).mk
+include $(PDK_BOARD_COMP_PATH)/src/flash/src_files_flash.mk
+PACKAGE_SRCS_COMMON += src/$(BOARD)
+endif
+
# List all the external components/interfaces, whose interface header files
# need to be included for this component
INCLUDE_EXTERNAL_INTERFACES = pdk edma
index a4b65f024e479788545cbc5990bc820b17c3093f..ef08f373ec588b0b451e02b39140db0e3dafd535 100644 (file)
targets: [A53LE],
}
+var am64x_evm = {
+ name: "am64x_evm",
+ ccOpts: "-Dam64x_evm -DSOC_AM64X",
+ targets: [A53LE],
+
var tpr12_evm = {
name: "tpr12_evm",
ccOpts: "-Dtpr12_evm -DSOC_TPR12",
/* List all the build targets here. */
Build.targets = [ C66LE, C66BE, A15LE, M4LE, A9LE, A8LE, ARM9LE, C674LE A53LE ];
-var boards = [ evmAM335x, icev2AM335x, skAM335x, bbbAM335x, evmAM437x, idkAM437x, skAM437x, evmAM572x, idkAM571x, idkAM572x, evmK2H, evmK2K, evmK2E, evmK2L, evmK2G, evmC6678, evmC6657, evmOMAPL137 idkAM574x am65xx_evm am65xx_idk ];
+var boards = [ evmAM335x, icev2AM335x, skAM335x, bbbAM335x, evmAM437x, idkAM437x, skAM437x, evmAM572x, idkAM571x, idkAM572x, evmK2H, evmK2K, evmK2E, evmK2L, evmK2G, evmC6678, evmC6657, evmOMAPL137 idkAM574x am65xx_evm am65xx_idk am64x_evm ];
diff --git a/packages/ti/board/diag/ospi/src/ospi_test.c b/packages/ti/board/diag/ospi/src/ospi_test.c
index bbce08093cb96951a6c1f951cc1711f74967bab9..984810292c889c363c1654abebfe2ab45e201304 100755 (executable)
/* Open the Board OSPI NOR device with SPI port 0
and use default OSPI configurations */
+#if defined(am64x_evm)
+ boardHandle = Board_flashOpen(BOARD_FLASH_ID_MT35XU256ABA1G12,
+ BOARD_OSPI_INSTANCE, NULL);
+#else
boardHandle = Board_flashOpen(BOARD_FLASH_ID_MT35XU512ABA1G12,
BOARD_OSPI_INSTANCE, NULL);
+#endif
if (!boardHandle)
{
UART_printf("\n Board_flashOpen Failed. \n");
/* Open the Board OSPI NOR device with OSPI port 0
and use default OSPI configurations */
+#if defined(am64x_evm)
+ boardHandle = Board_flashOpen(BOARD_FLASH_ID_MT35XU256ABA1G12,
+ BOARD_OSPI_INSTANCE, NULL);
+#else
boardHandle = Board_flashOpen(BOARD_FLASH_ID_MT35XU512ABA1G12,
BOARD_OSPI_INSTANCE, NULL);
+#endif
if (!boardHandle)
{
UART_printf("\n Board_flashOpen Failed. \n");
diff --git a/packages/ti/board/src/am64x_evm/board_clock.c b/packages/ti/board/src/am64x_evm/board_clock.c
--- /dev/null
@@ -0,0 +1,168 @@
+/******************************************************************************\r
+ * Copyright (c) 2019 Texas Instruments Incorporated - http://www.ti.com\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the\r
+ * distribution.\r
+ *\r
+ * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ *****************************************************************************/\r
+\r
+ /** \file board_clock.c\r
+ *\r
+ * \brief This file contains initialization of wakeup and main PSC\r
+ * configuration structures and function definitions to get the number\r
+ * of wakeup and main PSC config exists.\r
+ */\r
+\r
+#include "board_clock.h"\r
+#include <ti/drv/sciclient/sciclient.h>\r
+\r
+/**\r
+ * \brief wkup PSC configuration parameters\r
+ *\r
+ * This structure provides the device-level view with module association to\r
+ * the clock, power, and voltage domains.\r
+ * \r
+ * The PSC provides the user with an interface to control several important\r
+ * power and clock operations. The device has two PSC - WKUP_PSC0 and PSC0\r
+ * in WKUPSS and MAIN SoC, respectively.\r
+ * \r
+ * PSC: The Power Sleep Controller is the device has several power domains\r
+ * that can be turned ON for operation or OFF to minimize power dissipation,\r
+ * which includes a Global Power Sleep Controller(GPSC) and Local Power \r
+ * Sleep Controller(LPSC).\r
+ * \r
+ * GPSC: Global Power Sleep Controller, is used to control the power gating\r
+ * of various power domains.\r
+ * \r
+ * LPSC: Local Power Sleep Controller, manages the clock gating for to each \r
+ * logic block. For modules with a dedicated clock or multiple clocks, the \r
+ * LPSC communicates with the PLL controller to enable and disable that\r
+ * module's clock(s) at the source. For modules that share a clock with\r
+ * other modules, the LPSC controls the clock gating logic for each module. \r
+ */\r
+const pscConfig wkupPscConfigs[] =\r
+{\r
+\r
+};\r
+\r
+/**\r
+ * \brief main PSC configuration parameters\r
+ *\r
+ * This structure provides the device-level view with module association to\r
+ * the clock, power, and voltage domains.\r
+ * \r
+ * The PSC provides the user with an interface to control several important\r
+ * power and clock operations. The device has two PSC - WKUP_PSC0 and PSC0\r
+ * in WKUPSS and MAIN SoC, respectively.\r
+ * \r
+ * PSC: The Power Sleep Controller is the device has several power domains\r
+ * that can be turned ON for operation or OFF to minimize power dissipation,\r
+ * which includes a Global Power Sleep Controller(GPSC) and Local Power \r
+ * Sleep Controller(LPSC).\r
+ * \r
+ * GPSC: Global Power Sleep Controller, is used to control the power gating\r
+ * of various power domains.\r
+ * \r
+ * LPSC: Local Power Sleep Controller, manages the clock gating for to each \r
+ * logic block. For modules with a dedicated clock or multiple clocks, the \r
+ * LPSC communicates with the PLL controller to enable and disable that\r
+ * module's clock(s) at the source. For modules that share a clock with\r
+ * other modules, the LPSC controls the clock gating logic for each module. \r
+ */\r
+const pscConfig mainPscConfigs[] =\r
+{\r
+\r
+};\r
+\r
+/**\r
+ * \brief This function is used to get the number of \\r
+ * wkup PSC configs exists.\r
+ *\r
+ * \return\r
+ * \n uint32_t - Number of wkup PSC configs.\r
+ */\r
+uint32_t Board_getNumWkupPscCconfigs(void)\r
+{\r
+ return (sizeof(wkupPscConfigs) / sizeof(pscConfig));\r
+}\r
+\r
+/**\r
+ * \brief This function is used to get the number of \\r
+ * main PSC configs exists.\r
+ *\r
+ * \return\r
+ * \n uint32_t - Number of main PSC configs.\r
+ */\r
+uint32_t Board_getNumMainPscCconfigs(void)\r
+{\r
+ return (sizeof(mainPscConfigs) / sizeof(pscConfig));\r
+}\r
+\r
+Board_STATUS Board_moduleClockInit(void)\r
+{\r
+ Board_STATUS status = BOARD_SOK;\r
+#if defined(__TI_ARM_V7R4__)\r
+ int32_t ret;\r
+ uint64_t mcuClkFreq;\r
+#if 0\r
+ ret = Sciclient_pmGetModuleClkFreq(TISCI_DEV_MCU_ARMSS0_CPU0,\r
+ TISCI_DEV_MCU_ARMSS0_CPU0_BUS_CPU_CLK,\r
+ &mcuClkFreq,\r
+ SCICLIENT_SERVICE_WAIT_FOREVER);\r
+#else\r
+ /* \r
+ * Temporary hard-code R5 core clock to 800 MHz (default on Zebu)\r
+ * until Sciclent PM is supported\r
+ */\r
+ mcuClkFreq = 800000000U;\r
+ ret = 0U;\r
+#endif\r
+ if(ret == 0)\r
+ {\r
+ Osal_HwAttrs hwAttrs;\r
+ uint32_t ctrlBitmap;\r
+\r
+ ret = Osal_getHwAttrs(&hwAttrs);\r
+ if(ret == 0)\r
+ {\r
+ /*\r
+ * Change the timer input clock frequency configuration\r
+ based on R5 CPU clock configured\r
+ */\r
+ hwAttrs.cpuFreqKHz = (int32_t)(mcuClkFreq/1000U);\r
+ ctrlBitmap = OSAL_HWATTR_SET_CPU_FREQ;\r
+ ret = Osal_setHwAttrs(ctrlBitmap, &hwAttrs);\r
+ }\r
+ }\r
+ if(ret != 0)\r
+ {\r
+ status = BOARD_INIT_CLOCK_FAIL;\r
+ }\r
+#endif \r
+ return (status);\r
+}\r
diff --git a/packages/ti/board/src/am64x_evm/board_ddr.c b/packages/ti/board/src/am64x_evm/board_ddr.c
--- /dev/null
@@ -0,0 +1,57 @@
+/******************************************************************************\r
+ * Copyright (c) 2019 Texas Instruments Incorporated - http://www.ti.com\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the\r
+ * distribution.\r
+ *\r
+ * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ *****************************************************************************/\r
+\r
+/** \file board_ddr.c\r
+ *\r
+ * \brief This file used to configure the DDR timing parameters.\r
+ *\r
+ */\r
+\r
+#include "board_ddr.h"\r
+\r
+/**\r
+ * \brief DDR4 Initialization function\r
+ *\r
+ * Initializes the DDR timing parameters. Sets the DDR timing parameters\r
+ * based in the DDR PLL controller configuration done by the board library.\r
+ * Any changes to DDR PLL requires change to DDR timing.\r
+ *\r
+ * \param void\r
+ *\r
+ * \return BOARD_SOK in case of success or appropriate error code\r
+ *\r
+ */\r
+Board_STATUS Board_DDRInit(void)\r
+{\r
+ return BOARD_SOK;\r
+}\r
diff --git a/packages/ti/board/src/am64x_evm/board_ethernet_config.c b/packages/ti/board/src/am64x_evm/board_ethernet_config.c
--- /dev/null
@@ -0,0 +1,104 @@
+/******************************************************************************\r
+ * Copyright (c) 2019 Texas Instruments Incorporated - http://www.ti.com\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the\r
+ * distribution.\r
+ *\r
+ * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ *****************************************************************************/\r
+\r
+/**\r
+ * \file board_ethernet_config.c\r
+ *\r
+ * \brief\r
+ * This file contains the boards specific Ethernet PHY configurations.\r
+ *\r
+ */\r
+\r
+#include "board_ethernet_config.h"\r
+#include "board_internal.h"\r
+#include <ti/csl/soc.h>\r
+\r
+/**\r
+ * \brief Board specific configurations for MCU Ethernet PHY\r
+ *\r
+ * This function takes care of configuring the internal delays for MCU gigabit\r
+ * Ethernet PHY\r
+ * \r
+ * J7ES_TODO: Place holder. Needs update\r
+ *\r
+ * \return none\r
+ */\r
+Board_STATUS Board_mcuEthConfig(void)\r
+{\r
+ return BOARD_SOK;\r
+}\r
+\r
+/**\r
+ * \brief Board specific configurations for ICSS EMAC Ethernet PHYs\r
+ *\r
+ * This function takes care of configuring the internal delays for ICSS \r
+ * Ethernet PHY\r
+ *\r
+ * J7ES_TODO: Place holder. Needs update\r
+ *\r
+ * \return none\r
+ */\r
+Board_STATUS Board_icssEthConfig(void)\r
+{\r
+ return BOARD_SOK;\r
+}\r
+\r
+/**\r
+ * \brief Board specific configurations for CPSW RGMII Ethernet\r
+ *\r
+ * This function takes care of configuring the internal delays for CPSW9G \r
+ * RGMII Ethernet PHY\r
+ *\r
+ * J7ES_TODO: Place holder. Needs update\r
+ *\r
+ * \return none\r
+ */\r
+Board_STATUS Board_rgmiiEthConfig(void)\r
+{\r
+ return BOARD_SOK;\r
+}\r
+\r
+/**\r
+ * \brief Board specific configurations for SGMII Ethernet\r
+ *\r
+ * This function takes care of configuring the internal delays for \r
+ * SGMII Ethernet PHY\r
+ *\r
+ * J7ES_TODO: Place holder. Needs update\r
+ *\r
+ * \return none\r
+ */\r
+Board_STATUS Board_sgmiiEthConfig(void)\r
+{\r
+ return BOARD_SOK;\r
+}\r
diff --git a/packages/ti/board/src/am64x_evm/board_info.c b/packages/ti/board/src/am64x_evm/board_info.c
--- /dev/null
@@ -0,0 +1,100 @@
+/******************************************************************************\r
+ * Copyright (c) 2019 Texas Instruments Incorporated - http://www.ti.com\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the\r
+ * distribution.\r
+ *\r
+ * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ *****************************************************************************/\r
+\r
+/** \r
+ * \file board_info.c\r
+ *\r
+ * \brief This file contains the functions to read/write board info data \r
+ *\r
+ */\r
+\r
+#include "board_internal.h"\r
+#include "board_cfg.h"\r
+#include <stdio.h>\r
+#include <string.h>\r
+\r
+/**\r
+ * @brief This function is not supported by this platform.\r
+ *\r
+ * Function implementation for build backward compatibilty.\r
+ * Always returns 'BOARD_UNSUPPORTED_FEATURE'\r
+ *\r
+ */\r
+Board_STATUS Board_getIDInfo(Board_IDInfo *info)\r
+{\r
+ return BOARD_UNSUPPORTED_FEATURE;\r
+}\r
+\r
+/**\r
+ * @brief Get board information.\r
+ *\r
+ * @param[out] Board_STATUS\r
+ * Returns status on API call\r
+ * @param[out] info\r
+ * This structure will have board information on return\r
+ * @param[in] slaveAddress\r
+ * I2C slave address of EEPROM to be read\r
+ *\r
+ */\r
+Board_STATUS Board_getIDInfo_v2(Board_IDInfo_v2 *info, uint8_t slaveAddress)\r
+{\r
+ return BOARD_SOK;\r
+}\r
+\r
+/**\r
+ * @brief This function is not supported by this platform.\r
+ *\r
+ * Function implementation for build backward compatibilty.\r
+ * Always returns 'BOARD_UNSUPPORTED_FEATURE'\r
+ *\r
+ */\r
+Board_STATUS Board_writeIDInfo(Board_IDInfo *info)\r
+{\r
+ return BOARD_UNSUPPORTED_FEATURE;\r
+}\r
+\r
+/**\r
+ * @brief Write board id contents to specific EEPROM.\r
+ *\r
+ * @param[out] Board_STATUS\r
+ * Returns status on API call\r
+ * @param[out] info\r
+ * Structure contain board id contents to write\r
+ * @param[in] slaveAddress\r
+ * Address of eeprom\r
+ *\r
+ */\r
+Board_STATUS Board_writeIDInfo_v2(Board_IDInfo_v2 *info, uint8_t slaveAddress)\r
+{\r
+ return BOARD_SOK;\r
+}\r
diff --git a/packages/ti/board/src/am64x_evm/board_init.c b/packages/ti/board/src/am64x_evm/board_init.c
--- /dev/null
@@ -0,0 +1,184 @@
+/******************************************************************************\r
+ * Copyright (c) 2019 Texas Instruments Incorporated - http://www.ti.com\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the\r
+ * distribution.\r
+ *\r
+ * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ *****************************************************************************/\r
+/**\r
+ * \file board_init.c\r
+ *\r
+ * \brief Board library main file\r
+ *\r
+ * Board library provides basic functions to initialize the interfaces\r
+ * on a given HW platform. It takes care of configuring and enabling different\r
+ * modules like PLL, clocks inside SoC and HW components on the board which are\r
+ * required to make sure board is ready for running the application software.\r
+ *\r
+ * A common standard API Board_init() is exposed to the applications to invoke\r
+ * different board initialization routines. This function is common across the\r
+ * platforms maitaining the portability and can receive different input\r
+ * configuration flags based on the board capabilities allowing extendibility.\r
+ *\r
+ * Board library shall eliminate the use of any additional configurations like\r
+ * GEL files to initialize the board except the cases like DDR initialization\r
+ * for loading the code into DDR before calling the Board init function.\r
+ * Give this limitation, applications invoking board library functions to\r
+ * initialize PLL, DDR and pinmux are supposed to run from SoC internal memory.\r
+ *\r
+ */\r
+\r
+#include "board_internal.h"\r
+#include <ti/drv/sciclient/sciclient.h>\r
+\r
+Board_gblObj Board_obj = {NULL};\r
+\r
+static bool gBoardSysInitDone = 0;\r
+\r
+/**\r
+ * \brief Board global initilizations\r
+ *\r
+ * \return BOARD_SOK in case of success or appropriate error code\r
+ *\r
+ */\r
+static Board_STATUS Board_sysInit(void)\r
+{\r
+ Board_STATUS status = BOARD_SOK;\r
+ int32_t ret;\r
+ Sciclient_ConfigPrms_t config;\r
+\r
+ if(gBoardSysInitDone == 0)\r
+ {\r
+ Sciclient_configPrmsInit(&config);\r
+ ret = Sciclient_init(&config);\r
+ if(ret != 0)\r
+ {\r
+ status = BOARD_FAIL;\r
+ }\r
+\r
+ if(status == BOARD_SOK)\r
+ {\r
+ gBoardSysInitDone = 1;\r
+ }\r
+ }\r
+\r
+ return status;\r
+}\r
+\r
+/**\r
+ * \brief Board library initialization function\r
+ *\r
+ * Different board initialization routines are invoked by using configuration\r
+ * flags as described below\r
+ * BOARD_INIT_UNLOCK_MMR -\r
+ * Unlocks the MMR registers of the SoC. MMR registers should be\r
+ * enabled before any write access to MMR register address space.\r
+ *\r
+ * BOARD_INIT_PLL -\r
+ * Configures different PLL controller modules. This enables all the PLL\r
+ * controllers on the SoC with default configurations. Any custom values\r
+ * required for PLL output needs to be done separately\r
+ *\r
+ * BOARD_INIT_DDR -\r
+ * Initializes the DDR timing parameters. Sets the DDR timing parameters\r
+ * based in the DDR PLL controller configuration done by the board library.\r
+ * Any changes to DDR PLL requires change to DDR timing.\r
+ *\r
+ * BOARD_INIT_PINMUX_CONFIG -\r
+ * Enables pinmux for the board interfaces. Pin mux is done based on the\r
+ * default/primary functionality of the board. Any pins shared by multiple\r
+ * interfaces need to be reconfigured to access the secondary functionality.\r
+ *\r
+ * BOARD_INIT_UART_STDIO -\r
+ * Configures the UART module to use for serial console messages.\r
+ *\r
+ * BOARD_INIT_MODULE_CLOCK -\r
+ * Enables different power domains and peripheral clocks of the SoC.\r
+ * Some of the power domains and peripherals will be off by default.\r
+ * Enabling the power domains is mandatory before accessing using\r
+ * board interfaces connected to those peripherals.\r
+ *\r
+ * \param cfg [IN] Board configuration flags\r
+ *\r
+ * \return BOARD_SOK in case of success or appropriate error code\r
+ */\r
+Board_STATUS Board_init(Board_initCfg cfg)\r
+{ \r
+ Board_STATUS ret = BOARD_SOK;\r
+\r
+ ret = Board_sysInit();\r
+ if (ret != BOARD_SOK)\r
+ return ret;\r
+\r
+ if (cfg & BOARD_INIT_UNLOCK_MMR)\r
+ ret = Board_unlockMMR();\r
+ if (ret != BOARD_SOK)\r
+ return ret;\r
+\r
+ if (cfg & BOARD_INIT_MODULE_CLOCK)\r
+ ret = Board_moduleClockInit();\r
+ if (ret != BOARD_SOK)\r
+ return ret;\r
+\r
+ if (cfg & BOARD_INIT_PINMUX_CONFIG)\r
+ ret = Board_pinmuxConfig();\r
+ if (ret != BOARD_SOK)\r
+ return ret;\r
+\r
+ if (cfg & BOARD_INIT_PLL)\r
+ ret = Board_PLLInitAll();\r
+ if (ret != BOARD_SOK)\r
+ return ret;\r
+ \r
+ if (cfg & BOARD_INIT_DDR)\r
+ ret = Board_DDRInit();\r
+ if (ret != BOARD_SOK)\r
+ return ret;\r
+\r
+ if (cfg & BOARD_INIT_ETH_PHY)\r
+ ret = Board_mcuEthConfig();\r
+ if (ret != BOARD_SOK)\r
+ return ret;\r
+\r
+ if (cfg & BOARD_INIT_ICSS_ETH_PHY)\r
+ ret = Board_icssEthConfig();\r
+ if (ret != BOARD_SOK)\r
+ return ret;\r
+\r
+ if (cfg & BOARD_INIT_UART_STDIO)\r
+ ret = Board_uartStdioInit();\r
+ if (ret != BOARD_SOK)\r
+ return ret;\r
+\r
+ if (cfg & BOARD_INIT_SERDES_PHY)\r
+ ret = Board_serdesCfg();\r
+ if (ret != BOARD_SOK)\r
+ return ret;\r
+\r
+ return ret;\r
+}\r
diff --git a/packages/ti/board/src/am64x_evm/board_lld_init.c b/packages/ti/board/src/am64x_evm/board_lld_init.c
--- /dev/null
@@ -0,0 +1,73 @@
+/******************************************************************************\r
+ * Copyright (c) 2019 Texas Instruments Incorporated - http://www.ti.com\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the\r
+ * distribution.\r
+ *\r
+ * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ *****************************************************************************/\r
+\r
+/** \r
+ * \file board_lld_init.c\r
+ *\r
+ * \brief This file initializes UART and I2C LLD modules \r
+ *\r
+ */\r
+\r
+#include "board_internal.h"\r
+#include "board_cfg.h"\r
+\r
+/**\r
+ * \brief This function initializes the default UART instance for use for\r
+ * console operations.\r
+ *\r
+ * \return Board_STATUS in case of success or appropriate error code.\r
+ *\r
+ */\r
+Board_STATUS Board_uartStdioInit(void)\r
+{\r
+ UART_stdioInit(BOARD_UART_INSTANCE);\r
+\r
+ return BOARD_SOK;\r
+}\r
+\r
+/**\r
+ * \brief This function initializes the i2c instance connected to the\r
+ * board Id EEPROM.\r
+ *\r
+ * This function disables the interrupt mode as the Board i2c instance \r
+ * doesn't require interrupt mode and restores back original at the end.\r
+ *\r
+ * \param i2cInst [IN] I2C instance.\r
+ *\r
+ * \return Board_STATUS in case of success or appropriate error code.\r
+ *\r
+ */\r
+Board_STATUS Board_internalInitI2C(uint8_t i2cInst)\r
+{\r
+ return BOARD_SOK;\r
+}\r
diff --git a/packages/ti/board/src/am64x_evm/board_mmr.c b/packages/ti/board/src/am64x_evm/board_mmr.c
--- /dev/null
@@ -0,0 +1,53 @@
+/******************************************************************************\r
+ * Copyright (c) 2019 Texas Instruments Incorporated - http://www.ti.com\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the\r
+ * distribution.\r
+ *\r
+ * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ *****************************************************************************/\r
+/**\r
+ * \file board_mmr.c\r
+ *\r
+ * \brief MMR configuration file\r
+ *\r
+ * This file contains the function to unlock the MMR registers\r
+ *\r
+ */\r
+\r
+#include "board_internal.h"\r
+\r
+/**\r
+ * \brief Unlocks MMR registers\r
+ *\r
+ * \return Board_STATUS\r
+ */\r
+Board_STATUS Board_unlockMMR(void)\r
+{\r
+ return BOARD_SOK;\r
+}\r
+\r
diff --git a/packages/ti/board/src/am64x_evm/board_pinmux.c b/packages/ti/board/src/am64x_evm/board_pinmux.c
--- /dev/null
@@ -0,0 +1,130 @@
+/******************************************************************************\r
+ * Copyright (c) 2019 Texas Instruments Incorporated - http://www.ti.com\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the\r
+ * distribution.\r
+ *\r
+ * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ *****************************************************************************/\r
+\r
+/** \r
+ * \file board_pinmux.c\r
+ *\r
+ * \brief This file Enables pinmux for the board \r
+ *\r
+ */\r
+\r
+#include <ti/csl/soc.h> \r
+#include "board_internal.h"\r
+#include "board_pinmux.h"\r
+\r
+/**\r
+ * \brief This function used to set the specified pinMux\r
+ * mode for a specified pinMux offset address register.\r
+ *\r
+ * \param offset [IN] Pad config offset address\r
+ * mode [IN] Pad config mux mode.\r
+ *\r
+ * \return int8_t\r
+ * 0 - in case of success\r
+ * -1 - in case of failure.\r
+ *\r
+ */\r
+void Board_pinMuxSetMode(uint32_t offset, uint32_t mode)\r
+{\r
+ \r
+}\r
+\r
+/**\r
+ * \brief This function used to set the specified pinMux\r
+ * mode for a specified pinMux offset address register\r
+ * of a wkup domain.\r
+ *\r
+ * \param offset [IN] Pad config offset address\r
+ * mode [IN] Pad config mux mode.\r
+ *\r
+ * \return int8_t\r
+ * 0 - in case of success\r
+ * -1 - in case of failure.\r
+ *\r
+ */\r
+void Board_wkupPinMuxSetMode(uint32_t offset, uint32_t mode)\r
+{\r
+\r
+}\r
+\r
+/**\r
+ * \brief This function used to get the specified pinMux configuration\r
+ * for a specified pinMux offset address register of a specified\r
+ * domain.\r
+ *\r
+ * \param domainType [IN] enum variable to specify the domain\r
+ * offset [IN] Pad config offset address\r
+ * *dataBuff [IN/OUT] Pointer to data buffer.\r
+ *\r
+ * \return BOARD_SOK in case of success or appropriate error code\r
+ *\r
+ */\r
+Board_STATUS Board_pinMuxGetCfg(domainType_t domainType, uint32_t offset, uint32_t *dataBuff)\r
+{\r
+ return BOARD_SOK;\r
+}\r
+\r
+/**\r
+ * \brief This function used to set the specified pinMux configuration\r
+ * for a specified pinMux offset address register of a specified\r
+ * domain.\r
+ *\r
+ * \param domainType [IN] enum variable to specify the domain\r
+ * offset [IN] Pad config offset address\r
+ * cfgData [IN] Pad config pinmux data.\r
+ *\r
+ * \return BOARD_SOK in case of success or appropriate error code\r
+ *\r
+ */\r
+Board_STATUS Board_pinMuxSetCfg(domainType_t domainType, uint32_t offset, uint32_t cfgData)\r
+{\r
+ return BOARD_SOK;\r
+}\r
+\r
+/**\r
+ * \brief Board pinmuxing enable function\r
+ *\r
+ * Enables pinmux for the board interfaces. Pin mux is done based\r
+ * on the default/primary functionality of the board. Any pins shared by\r
+ * multiple interfaces need to be reconfigured to access the secondary\r
+ * functionality.\r
+ *\r
+ * \param void\r
+ *\r
+ * \return BOARD_SOK in case of success or appropriate error code\r
+ *\r
+ */\r
+Board_STATUS Board_pinmuxConfig (void)\r
+{\r
+ return BOARD_SOK;\r
+}\r
diff --git a/packages/ti/board/src/am64x_evm/board_pll.c b/packages/ti/board/src/am64x_evm/board_pll.c
--- /dev/null
@@ -0,0 +1,52 @@
+/******************************************************************************\r
+ * Copyright (c) 2019 Texas Instruments Incorporated - http://www.ti.com\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the\r
+ * distribution.\r
+ *\r
+ * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ *****************************************************************************/\r
+\r
+/**\r
+ * \file board_pll.c\r
+ *\r
+ * \brief Board pll configurations\r
+ *\r
+ */\r
+\r
+#include "board_internal.h"\r
+#include "board_pll.h"\r
+\r
+/**\r
+ * \brief Function to initialize all the PLL clocks with default values\r
+ *\r
+ * \return Board_STATUS\r
+ */\r
+Board_STATUS Board_PLLInitAll(void)\r
+{\r
+ return BOARD_SOK;\r
+}\r
diff --git a/packages/ti/board/src/am64x_evm/board_serdes_cfg.c b/packages/ti/board/src/am64x_evm/board_serdes_cfg.c
--- /dev/null
@@ -0,0 +1,55 @@
+/******************************************************************************\r
+ * Copyright (c) 2019 Texas Instruments Incorporated - http://www.ti.com\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the\r
+ * distribution.\r
+ *\r
+ * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ *****************************************************************************/\r
+/**\r
+ * \file board_cfg.c\r
+ *\r
+ * \brief EVM serdes configuration file\r
+ *\r
+ * Configures the serdes module.\r
+ *\r
+ */\r
+\r
+#include "board_serdes_cfg.h"\r
+\r
+/**\r
+ * \brief serdes configurations\r
+ *\r
+ * The function configures the serdes1 module for one lane pcie interface\r
+ *\r
+ * \return BOARD_SOK in case of success or appropriate error code\r
+ *\r
+ */\r
+Board_STATUS Board_serdesCfg(void)\r
+{\r
+ return BOARD_SOK;\r
+}\r
diff --git a/packages/ti/board/src/am64x_evm/include/board_cfg.h b/packages/ti/board/src/am64x_evm/include/board_cfg.h
--- /dev/null
@@ -0,0 +1,301 @@
+/******************************************************************************\r
+ * Copyright (c) 2019 Texas Instruments Incorporated - http://www.ti.com\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the\r
+ * distribution.\r
+ *\r
+ * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ *****************************************************************************/\r
+\r
+/**\r
+ * \brief Board library configurations\r
+ *\r
+ * This file configures the instance numbers, address and gpio reset\r
+ * details of different interfaces of the board.\r
+ *\r
+ */\r
+#ifndef BOARD_CFG_H_\r
+#define BOARD_CFG_H_\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/* Board ID information */\r
+#define BOARD_INFO_CPU_NAME "am64x"\r
+#define BOARD_INFO_BOARD_NAME "am64x_evm"\r
+\r
+/* Memory sections */\r
+#define BOARD_DDR_START_ADDR (0x80000000U)\r
+#define BOARD_DDR_SIZE (2048 * 1024 * 1024UL)\r
+#define BOARD_DDR_END_ADDR (0xFFFFFFFFU)\r
+\r
+/* UART LLD instance number for MAIN UART0 port */\r
+#define BOARD_UART0_INSTANCE (0U)\r
+/* UART LLD instance number for MCU UART0 port */\r
+#define BOARD_MCU_UART0_INSTANCE (7U)\r
+\r
+/* UART LLD instance number for primary UART port */\r
+#if defined (BUILD_MPU) || defined (BUILD_MCU)\r
+/* default UART instance for A53 and R5 cores in the Main domain */ \r
+#define BOARD_UART_INSTANCE (BOARD_UART0_INSTANCE)\r
+#else\r
+/* default UART instance for M4 core in the MCU domain */ \r
+#define BOARD_UART_INSTANCE (BOARD_MCU_UART0_INSTANCE)\r
+#endif\r
+\r
+/* ICSSG UART instance number */\r
+#define BOARD_ICSSG_UART_INSTANCE (4U)\r
+\r
+/* I2C instance connected to EEPROM - WKUP I2C0 */\r
+#define BOARD_I2C_EEPROM_INSTANCE (0U)\r
+\r
+/* I2C instance for BOOT EEPROM */\r
+#define BOARD_I2C_BOOT_EEPROM_INSTANCE (0U)\r
+\r
+/* I2C address for Boot EEPROM */\r
+#define BOARD_I2C_BOOT_EEPROM_ADDR (0x50U)\r
+#define BOARD_I2C_BOOT_EEPROM_ADDR2 (0x51U)\r
+\r
+/* I2C address for Board Id EEPROM */\r
+#define BOARD_I2C_EEPROM_ADDR (0x51U)\r
+\r
+/* QSPI instance number */\r
+#define BOARD_SPI_NOR_INSTANCE (1U)\r
+\r
+/* I2C Instance connected to clock generator */\r
+#define BOARD_CLOCK_GENERATOR_INSTANCE (0U)\r
+/* I2C slave address of clock generator */\r
+#define BOARD_I2C_CLOCK_GENERATOR1 (0) //Can be used later\r
+#define BOARD_I2C_CLOCK_GENERATOR2_ADDR1 (0x76)\r
+#define BOARD_I2C_CLOCK_GENERATOR2_ADDR2 (0x77)\r
+#define BOARD_I2C_QSGMII_CLOCK_GENERATOR (0x77)\r
+#define BOARD_I2C_PERI_CLOCK_GENERATOR (0x6D)\r
+\r
+/* OSPI instance connected to OSPI NOR flash */\r
+#define BOARD_OSPI_NOR_INSTANCE (0U)\r
+\r
+/* I2C instance connected to IO Expander */\r
+#define BOARD_I2C_IOEXP_DEVICE1_INSTANCE (0U)\r
+#define BOARD_I2C_IOEXP_DEVICE2_INSTANCE (0U)\r
+#define BOARD_I2C_IOEXP_DEVICE3_INSTANCE (3U)\r
+#define BOARD_I2C_IOEXP_DEVICE4_INSTANCE (0U)\r
+#define BOARD_I2C_IOEXP_DEVICE5_INSTANCE (1U)\r
+#define BOARD_I2C_AUDIO_IOEXP_DEVICE_INSTANCE (3U)\r
+#define BOARD_I2C_VIDEO_IOEXP_DEVICE_INSTANCE (0U)\r
+\r
+/* I2C IO Expander Slave devices */\r
+#define BOARD_I2C_IOEXP_DEVICE1_ADDR (0x20U)\r
+#define BOARD_I2C_IOEXP_DEVICE2_ADDR (0x22U)\r
+#define BOARD_I2C_IOEXP_DEVICE3_ADDR (0x20U)\r
+#define BOARD_I2C_IOEXP_DEVICE4_ADDR (0x20U)\r
+#define BOARD_I2C_IOEXP_DEVICE5_ADDR (0x20U)\r
+#define BOARD_I2C_AUDIO_IOEXP_DEVICE_ADDR (0x21U)\r
+#define BOARD_I2C_VIDEO_IOEXP_DEVICE_ADDR (0x21U)\r
+\r
+#define BOARD_GPIO_IOEXP_SPI_RST_PORT_NUM (0) //J7ES_TODO: need to update\r
+#define BOARD_GPIO_IOEXP_SPI_RST_PIN_NUM (0) //J7ES_TODO: need to update\r
+\r
+/* OSPI instance number */\r
+#define BOARD_OSPI_INSTANCE (0)\r
+\r
+#define BOARD_GPIO_IOEXP_OSPI_RST_PORT_NUM (0) //J7ES_TODO: need to update\r
+#define BOARD_GPIO_IOEXP_OSPI_RST_PIN_NUM (0) //J7ES_TODO: need to update\r
+\r
+/* GPIO port & pin numbers for MMC reset */\r
+#define GPIO_MMC_SDCD_PORT_NUM (0) //J7ES_TODO: need to update\r
+#define GPIO_MMC_SDCD_PIN_NUM (0) //J7ES_TODO: need to update\r
+\r
+#define BOARD_GPIO_IOEXP_EMMC_RST_PORT_NUM (0x00) //J7ES_TODO: need to update\r
+#define BOARD_GPIO_IOEXP_EMMC_RST_PIN_NUM (0x00) //J7ES_TODO: need to update\r
+\r
+/* I2C instance for External RTC */\r
+#define BOARD_I2C_EXT_RTC_INSTANCE (0U)\r
+\r
+/* I2C address for External RTC */\r
+#define BOARD_I2C_EXT_RTC_ADDR (0x6FU)\r
+\r
+#define BOARD_I2C_TOUCH_INSTANCE (0) //J7ES_TODO: need to update\r
+\r
+#define BOARD_I2C_TOUCH_SLAVE_ADDR (0) //J7ES_TODO: need to update\r
+\r
+/* I2C instance Board Presence Circuit */\r
+#define BOARD_PRES_WKUP_I2C_INSTANCE (0U) //J7ES_TODO: need to update\r
+/* I2C address Board Presence Circuit */\r
+#define BOARD_PRES_DETECT_SLAVE_ADDR (0) //J7ES_TODO: need to update\r
+\r
+/* User LED Pin Details */\r
+#define BOARD_I2C_USER_LED_INSTANCE (0U)\r
+\r
+#define BOARD_USER_LED1 (6U)\r
+#define BOARD_USER_LED2 (7U)\r
+\r
+#define BOARD_ICSS_EMAC_PORT_START (0) //J7ES_TODO: need to update\r
+#define BOARD_ICSS_EMAC_PORT_END (0) //J7ES_TODO: need to update\r
+#define BOARD_ICSS_EMAC_PORT_MAX (2) //J7ES_TODO: need to update\r
+#define BOARD_MCU_EMAC_PORT_MAX (0) //J7ES_TODO: need to update\r
+#define BOARD_MCU_ETH_PORT (0) //J7ES_TODO: need to update\r
+\r
+\r
+/* ICSS2 EMAC PHY register address */\r
+#define BOARD_ICSS2_EMAC_PHY0_ADDR (0x0) //J7ES_TODO: need to update\r
+#define BOARD_ICSS2_EMAC_PHY1_ADDR (0x3u) //J7ES_TODO: need to update\r
+\r
+\r
+/* PRG2_RGMII_RESETn */\r
+#define BOARD_GPIO_IOEXP_ICSS2_EMAC_RST_PORT_NUM (0) //J7ES_TODO: need to update\r
+#define BOARD_GPIO_IOEXP_ICSS2_EMAC_RST_PIN_NUM (0) //J7ES_TODO: need to update\r
+\r
+/* PRG2_RGMII_INTn */\r
+#define BOARD_GPIO_ICSS2_EMAC_INT_PORT_NUM (0) /* WKUP_GPIO0_24 */ //J7ES_TODO: need to update\r
+#define BOARD_GPIO_ICSS2_EMAC_INT_PIN_NUM (0) //J7ES_TODO: need to update\r
+\r
+/* PRG2_ETH1_LED_LINK */\r
+#define BOARD_GPIO_ICSS2_EMAC_PHY0_LED_LINK_PORT_NUM (0) /* GPIO1_13 */ //J7ES_TODO: need to update\r
+#define BOARD_GPIO_ICSS2_EMAC_PHY0_LED_LINK_PIN_NUM (0) //J7ES_TODO: need to update\r
+\r
+/* PRG2_ETH2_LED_LINK */\r
+#define BOARD_GPIO_ICSS2_EMAC_PHY1_LED_LINK_PORT_NUM (0) /* GPIO1_14 */ //J7ES_TODO: need to update\r
+#define BOARD_GPIO_ICSS2_EMAC_PHY1_LED_LINK_PIN_NUM (0) //J7ES_TODO: need to update\r
+\r
+/* GPIO to drive PRG2 LED0 */\r
+#define BOARD_GPIO_ICSS2_EMAC_LED0_PORT_NUM (0) /* WKUP_GPIO0_13 */ //J7ES_TODO: need to update\r
+#define BOARD_GPIO_ICSS2_EMAC_LED0_PIN_NUM (0) //J7ES_TODO: need to update\r
+\r
+/* GPIO to drive PRG2 LED1 */\r
+#define BOARD_GPIO_ICSS2_EMAC_LED1_PORT_NUM (0) /* WKUP_GPIO0_0 */ //J7ES_TODO: need to update\r
+#define BOARD_GPIO_ICSS2_EMAC_LED1_PIN_NUM (0) //J7ES_TODO: need to update\r
+\r
+/* GPIO to drive PRG2 LED2 */\r
+#define BOARD_GPIO_ICSS2_EMAC_LED2_PORT_NUM (0) /* WKUP_GPIO0_1 */ //J7ES_TODO: need to update\r
+#define BOARD_GPIO_ICSS2_EMAC_LED2_PIN_NUM (0) //J7ES_TODO: need to update\r
+\r
+/* GPIO to drive PRG2 LED3 */\r
+#define BOARD_GPIO_ICSS2_EMAC_LED3_PORT_NUM (0) /* WKUP_GPIO0_27 */ //J7ES_TODO: need to update\r
+#define BOARD_GPIO_ICSS2_EMAC_LED3_PIN_NUM (0) //J7ES_TODO: need to update\r
+\r
+/* MCU EMAC PHY MDIO address */\r
+#define BOARD_MCU_EMAC_PHY_ADDR (0U) //J7ES_TODO: need to update\r
+\r
+/* MCU EMAC MAX REG DUMP */\r
+#define BOARD_MCU_EMAC_REG_DUMP_MAX (0) //J7ES_TODO: need to update\r
+\r
+/* MCU EMAC PHY register address definitions for reading strap values */\r
+#define BOARD_MCU_EMAC_STRAP_STS1_ADDR (0) //J7ES_TODO: need to update\r
+#define BOARD_MCU_EMAC_STRAP_STS2_ADDR (0) //J7ES_TODO: need to update\r
+\r
+/* MCU EMAC PHY register address definitions for reading strap values */\r
+#define BOARD_ICSS_EMAC_STRAP_STS1_ADDR (0) //J7ES_TODO: need to update\r
+#define BOARD_ICSS_EMAC_STRAP_STS2_ADDR (0) //J7ES_TODO: need to update\r
+\r
+/* MCU_ETH1_RESETn */\r
+#define BOARD_GPIO_IOEXP_MCU_EMAC_RST_PORT_NUM (0) //J7ES_TODO: need to update\r
+#define BOARD_GPIO_IOEXP_MCU_EMAC_RST_PIN_NUM (0) //J7ES_TODO: need to update\r
+\r
+/* MCU_ETH1_INTn */\r
+#define BOARD_GPIO_MCU_EMAC_INT_PORT_NUM (0) /* WKUP_GPIO0_32 */ //J7ES_TODO: need to update\r
+#define BOARD_GPIO_MCU_EMAC_INT_PIN_NUM (0) //J7ES_TODO: need to update\r
+\r
+/* AUTOMATION HEADER */\r
+#define BOARD_TEST_HEADER_I2C_INSTANCE (2U)\r
+#define BOARD_I2C_BOOT_MODE_SW_ADDR (0x22U)\r
+\r
+/* TEST_GPIO1 */\r
+#define BOARD_GPIO_IOEXP_TEST_PORT_NUM (0) //J7ES_TODO: need to update\r
+#define BOARD_GPIO_IOEXP_TEST_PIN_NUM (0) //J7ES_TODO: need to update\r
+\r
+/* Temperature sensor i2c instance */\r
+#define BOARD_TEMP_SENSOR_I2C_INSTANCE (2U)\r
+\r
+/* Temperature sensor slave device addresses */\r
+#define BOARD_TEMP_SENSOR_I2C_SLAVE_DEVICE1_ADDR (0x48U)\r
+#define BOARD_TEMP_SENSOR_I2C_SLAVE_DEVICE2_ADDR (0x49U)\r
+\r
+#define BOARD_I2C_CURRENT_MONITOR_INSTANCE (2U)\r
+\r
+/* Instance for interfaces connected to MMCSD */\r
+#define BOARD_MMCSD_SD_INSTANCE (1U)\r
+#define BOARD_MMCSD_EMMC_INSTANCE (0)\r
+\r
+/* Enable NOR flash driver */\r
+#define BOARD_NOR_FLASH_IN //J7ES_TODO: need to update\r
+\r
+/* McSPI instance for master and slave test */\r
+#define BOARD_MCSPI_MASTER_INSTANCE (1) //J7ES_TODO: need to update\r
+#define BOARD_MCSPI_SLAVE_INSTANCE (1) //J7ES_TODO: need to update\r
+\r
+/* Maximum possible buffer length */\r
+#define BOARD_EEPROM_MAX_BUFF_LENGTH (0) //J7ES_TODO: need to update\r
+\r
+/* EEPROM board ID information */\r
+#define BOARD_EEPROM_HEADER_FIELD_SIZE (0) //J7ES_TODO: need to update\r
+#define BOARD_EEPROM_TYPE_SIZE (0) //J7ES_TODO: need to update\r
+#define BOARD_EEPROM_STRUCT_LENGTH_SIZE (0) //J7ES_TODO: need to update\r
+#define BOARD_EEPROM_MAGIC_NUMBER (0) //J7ES_TODO: need to update\r
+\r
+#define BOARD_BOARD_FIELD_TYPE (0) //J7ES_TODO: need to update\r
+#define BOARD_DDR_FIELD_TYPE (0) //J7ES_TODO: need to update\r
+#define BOARD_MACINFO_FIELD_TYPE (0) //J7ES_TODO: need to update\r
+#define BOARD_ENDLIST (0) //J7ES_TODO: need to update\r
+\r
+#define BOARD_EEPROM_HEADER_ADDR (0U) //J7ES_TODO: need to update\r
+\r
+/* PinMux data to be programmed to configure a pin to be a GPIO */\r
+#define PINMUX_GPIO_CFG (0x00050007U)\r
+\r
+typedef enum\r
+{\r
+ APP_CARD_DETECT = 0,\r
+ LCD_BRD_DETECT,\r
+ SERDES_BRD_DETECT,\r
+ HDMI_BRD_DETECT\r
+}boardPresDetect_t;\r
+\r
+typedef enum domainType\r
+{\r
+ MAIN_DOMAIN = 0U,\r
+ WKUP_DOMAIN\r
+}domainType_t;\r
+\r
+\r
+#define BOARD_EEPROM_HEADER_LENGTH (4U)\r
+#define BOARD_EEPROM_BOARD_NAME_LENGTH (8U)\r
+#define BOARD_EEPROM_VERSION_LENGTH (4U)\r
+#define BOARD_EEPROM_SERIAL_NO_LENGTH (12U)\r
+#define BOARD_EEPROM_CONFIG_LENGTH (32U)\r
+\r
+#define BOARD_EEPROM_BOARD_NAME_ADDR (BOARD_EEPROM_HEADER_ADDR + BOARD_EEPROM_HEADER_LENGTH)\r
+#define BOARD_EEPROM_VERSION_ADDR (BOARD_EEPROM_BOARD_NAME_ADDR + BOARD_EEPROM_BOARD_NAME_LENGTH)\r
+#define BOARD_EEPROM_SERIAL_NO_ADDR (BOARD_EEPROM_VERSION_ADDR + BOARD_EEPROM_VERSION_LENGTH)\r
+#define BOARD_EEPROM_CONFIG_ADDR (BOARD_EEPROM_SERIAL_NO_ADDR + BOARD_EEPROM_SERIAL_NO_LENGTH)\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif /* __cplusplus */\r
+\r
+#endif /* BOARD_CFG_H_ */\r
+\r
diff --git a/packages/ti/board/src/am64x_evm/include/board_clock.h b/packages/ti/board/src/am64x_evm/include/board_clock.h
--- /dev/null
@@ -0,0 +1,98 @@
+/******************************************************************************\r
+ * Copyright (c) 2019 Texas Instruments Incorporated - http://www.ti.com\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the\r
+ * distribution.\r
+ *\r
+ * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ *****************************************************************************/\r
+\r
+/** \file board_clock.h\r
+*\r
+* \brief This file contains structure, typedefs, functions and\r
+* prototypes used for clock configurations.\r
+*/\r
+ \r
+#ifndef BOARD_CLOCK_H\r
+#define BOARD_CLOCK_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+#include "board_internal.h"\r
+\r
+/**\r
+ * \brief PSC configuration parameters\r
+ *\r
+ * Each PSC in the device has several power domains that can be turned ON for\r
+ * operation or OFF to minimize power dissipation.\r
+ *\r
+ * GPSC: Global Power Sleep Controller, is used to control the power gating\r
+ * of various power domains.\r
+ * \r
+ * LPSC: Local Power Sleep Controller, manages the clock gating for to each \r
+ * logic block (or) module.\r
+ * \r
+ * domainNum: Power Domain Number\r
+ * \r
+ * moduleNum: Module Domain Number\r
+ *\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t domainNum;\r
+ uint32_t moduleNum;\r
+} pscConfig;\r
+\r
+extern const pscConfig wkupPscConfigs[];\r
+\r
+extern const pscConfig mainPscConfigs[];\r
+\r
+/**\r
+ * \brief This function is used to get the number of \\r
+ * wkup PSC configs exists.\r
+ *\r
+ * \return\r
+ * \n uint32_t - Number of wkup PSC configs.\r
+ */\r
+extern uint32_t Board_getNumWkupPscCconfigs();\r
+\r
+/**\r
+ * \brief This function is used to get the number of \\r
+ * main PSC configs exists.\r
+ *\r
+ * \return\r
+ * \n uint32_t - Number of main PSC configs.\r
+ */\r
+extern uint32_t Board_getNumMainPscCconfigs();\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif /* __cplusplus */\r
+\r
+#endif /* BOARD_CLOCK_H */\r
diff --git a/packages/ti/board/src/am64x_evm/include/board_ddr.h b/packages/ti/board/src/am64x_evm/include/board_ddr.h
--- /dev/null
@@ -0,0 +1,52 @@
+/******************************************************************************\r
+ * Copyright (c) 2019 Texas Instruments Incorporated - http://www.ti.com\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the\r
+ * distribution.\r
+ *\r
+ * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ *****************************************************************************/\r
+\r
+/** \file board_ddr.h\r
+ *\r
+ * \brief This file contains DDR timing parameters\r
+ */\r
+\r
+#ifndef BOARD_DDR_H_\r
+#define BOARD_DDR_H_\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+#include "board_internal.h"\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif /* __cplusplus */\r
+\r
+#endif /* BOARD_DDR_H_ */\r
diff --git a/packages/ti/board/src/am64x_evm/include/board_ethernet_config.h b/packages/ti/board/src/am64x_evm/include/board_ethernet_config.h
--- /dev/null
@@ -0,0 +1,86 @@
+/******************************************************************************\r
+ * Copyright (c) 2019 Texas Instruments Incorporated - http://www.ti.com\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the\r
+ * distribution.\r
+ *\r
+ * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ *****************************************************************************/\r
+\r
+ /**\r
+ * \brief board_ethernet_config.h\r
+ *\r
+ * This file contains Ethernet PHY configurations for the board\r
+ *\r
+ */\r
+\r
+#ifndef _BOARD_ETHERNET_CONFIG_H_\r
+#define _BOARD_ETHERNET_CONFIG_H_\r
+\r
+#include "board.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/**\r
+ * \brief Board specific configurations for ICSS EMAC Ethernet PHYs\r
+ *\r
+ * This function takes care of configuring the internal delays for ICSS\r
+ * Ethernet PHY\r
+ *\r
+ * \return none\r
+ */\r
+Board_STATUS Board_icssEthConfig(void);\r
+\r
+/**\r
+ * \brief Board specific configurations for MCU Ethernet PHY\r
+ *\r
+ * This function takes care of configuring the internal delays for MCU gigabit\r
+ * Ethernet PHY\r
+ *\r
+ * \return none\r
+ */\r
+Board_STATUS Board_mcuEthConfig(void);\r
+\r
+/**\r
+ * \brief Function to configure the Ethernet PHY speed\r
+ *\r
+ * \param port [IN] Ethernet PHY Port number (check above table)\r
+ * \param speed [IN] Speed selection\r
+ * 0 - 100 mpbs\r
+ * 1 - 1000 mpbs\r
+ *\r
+ * \return none\r
+ */\r
+Board_STATUS Board_ethPhySpeedConfig(int8_t port, uint8_t speed);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif /* __cplusplus */\r
+\r
+#endif /* _BOARD_ETHERNET_CONFIG_H_ */\r
diff --git a/packages/ti/board/src/am64x_evm/include/board_i2c_io_exp.h b/packages/ti/board/src/am64x_evm/include/board_i2c_io_exp.h
--- /dev/null
@@ -0,0 +1,365 @@
+/******************************************************************************\r
+ * Copyright (c) 2019 Texas Instruments Incorporated - http://www.ti.com\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the\r
+ * distribution.\r
+ *\r
+ * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ *****************************************************************************/\r
+\r
+/**\r
+ * \file board_i2c_io_exp.h\r
+ *\r
+ * \brief I2C IO Expander configurations header file\r
+ *\r
+ * This file includes the structures, enums and register offsets\r
+ * for configuring the slave devices connected to I2C IO expander.\r
+ *\r
+ */\r
+\r
+#ifndef _BOARD_I2C_IO_EXP_H_\r
+#define _BOARD_I2C_IO_EXP_H_\r
+\r
+#include "board_internal.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+#include <stdio.h>\r
+#include <stdint.h>\r
+#include <stdlib.h>\r
+#include <string.h>\r
+\r
+/* Input command for single port IO expander */\r
+#define BOARD_1PORT_IOEXP_INPUT_CMD (0x00U)\r
+\r
+/* Output command for single port IO expander */\r
+#define BOARD_1PORT_IOEXP_OUTPUT_CMD (0x01U)\r
+\r
+/* Polarity inversion command for single port IO expander */\r
+#define BOARD_1PORT_IOEXP_POLARITY_CMD (0x02U)\r
+\r
+/* Configuration command for single port IO expander */\r
+#define BOARD_1PORT_IOEXP_CONFIGURATION_CMD (0x03U)\r
+\r
+/* Input commands for two port IO expander */\r
+#define BOARD_2PORT_IOEXP_PORT0_INPUT_CMD (0x00U)\r
+#define BOARD_2PORT_IOEXP_PORT1_INPUT_CMD (0x01U)\r
+\r
+/* Output commands for two port IO expander */\r
+#define BOARD_2PORT_IOEXP_PORT0_OUTPUT_CMD (0x02U)\r
+#define BOARD_2PORT_IOEXP_PORT1_OUTPUT_CMD (0x03U)\r
+\r
+/* Polarity inversion commands for two port IO expander */\r
+#define BOARD_2PORT_IOEXP_PORT0_POLARITY_CMD (0x04U)\r
+#define BOARD_2PORT_IOEXP_PORT1_POLARITY_CMD (0x05U)\r
+\r
+/* Configuration commands for two port IO expander */\r
+#define BOARD_2PORT_IOEXP_PORT0_CONFIGURATION_CMD (0x06U)\r
+#define BOARD_2PORT_IOEXP_PORT1_CONFIGURATION_CMD (0x07U)\r
+\r
+/* Input commands for three port IO expander */\r
+#define BOARD_3PORT_IOEXP_PORT0_INPUT_CMD (0x00U)\r
+#define BOARD_3PORT_IOEXP_PORT1_INPUT_CMD (0x01U)\r
+#define BOARD_3PORT_IOEXP_PORT2_INPUT_CMD (0x02U)\r
+\r
+/* Output commands for three port IO expander */\r
+#define BOARD_3PORT_IOEXP_PORT0_OUTPUT_CMD (0x04U)\r
+#define BOARD_3PORT_IOEXP_PORT1_OUTPUT_CMD (0x05U)\r
+#define BOARD_3PORT_IOEXP_PORT2_OUTPUT_CMD (0x06U)\r
+\r
+/* Polarity inversion commands for three port IO expander */\r
+#define BOARD_3PORT_IOEXP_PORT0_POLARITY_CMD (0x08U)\r
+#define BOARD_3PORT_IOEXP_PORT1_POLARITY_CMD (0x09U)\r
+#define BOARD_3PORT_IOEXP_PORT2_POLARITY_CMD (0x0AU)\r
+\r
+/* Configuration commands for two port IO expander */\r
+#define BOARD_3PORT_IOEXP_PORT0_CONFIGURATION_CMD (0x0CU)\r
+#define BOARD_3PORT_IOEXP_PORT1_CONFIGURATION_CMD (0x0DU)\r
+#define BOARD_3PORT_IOEXP_PORT2_CONFIGURATION_CMD (0x0EU)\r
+\r
+/**\r
+ * \enum i2cIoExpType_t\r
+ *\r
+ * \brief specifies the available types of IO expander.\r
+ */\r
+typedef enum\r
+{\r
+ ONE_PORT_IOEXP = 0,\r
+ TWO_PORT_IOEXP,\r
+ THREE_PORT_IOEXP\r
+}i2cIoExpType_t;\r
+\r
+/**\r
+ * \enum i2cIoExpPortNumber_t\r
+ *\r
+ * \brief specifies the available port types.\r
+ */\r
+typedef enum\r
+{\r
+ PORTNUM_0 = 0,\r
+ PORTNUM_1,\r
+ PORTNUM_2\r
+}i2cIoExpPortNumber_t;\r
+\r
+/**\r
+ * \enum i2cIoExpPinNumber_t\r
+ *\r
+ * \brief specifies the available pin numbers.\r
+ */\r
+typedef enum\r
+{\r
+ PIN_NUM_0 = 0,\r
+ PIN_NUM_1,\r
+ PIN_NUM_2,\r
+ PIN_NUM_3,\r
+ PIN_NUM_4,\r
+ PIN_NUM_5,\r
+ PIN_NUM_6,\r
+ PIN_NUM_7\r
+}i2cIoExpPinNumber_t;\r
+\r
+/**\r
+ * \enum i2cIoExpPinDirection_t\r
+ *\r
+ * \brief specifies the available direction types.\r
+ */\r
+typedef enum\r
+{\r
+ PIN_DIRECTION_OUTPUT = 0,\r
+ PIN_DIRECTION_INPUT\r
+}i2cIoExpPinDirection_t;\r
+\r
+/**\r
+ * \enum i2cIoExpPinDirection_t\r
+ *\r
+ * \brief specifies the available signal levels.\r
+ */\r
+typedef enum\r
+{\r
+ GPIO_SIGNAL_LEVEL_LOW = 0,\r
+ GPIO_SIGNAL_LEVEL_HIGH\r
+}i2cIoExpSignalLevel_t;\r
+\r
+/**\r
+ * \brief Reads the current configuration of direction port.\r
+ *\r
+ * \param slaveAddr [IN] I2C Slave Address.\r
+ * \param ioExpType [IN] IO expander type.\r
+ * X_PORT_IOEXP - Total number of ports\r
+ * in slave device.\r
+ * \param portNum [IN] Port number of the i2c slave device\r
+ * PORTNUM_X - Port number of a slave\r
+ * device.\r
+ * \param data [IN/OUT] Pointer to the data buffer to store\r
+ * the pin level data of a specified port.\r
+ *\r
+ * \return Board_STATUS in case of success or appropriate error code.\r
+ *\r
+ */\r
+Board_STATUS Board_i2cIoExpReadDirPort(uint8_t slaveAddr,\r
+ i2cIoExpType_t ioExpType,\r
+ i2cIoExpPortNumber_t portNum,\r
+ uint8_t *data);\r
+\r
+/**\r
+ * \brief Reads the current configuration of output port.\r
+ *\r
+ * \param slaveAddr [IN] I2C Slave Address.\r
+ * \param ioExpType [IN] IO expander type.\r
+ * X_PORT_IOEXP - Total number of ports\r
+ * in slave device.\r
+ * \param portNum [IN] Port number of the i2c slave device\r
+ * PORTNUM_X - Port number of a slave\r
+ * device.\r
+ * \param data [IN/OUT] Pointer to the data buffer to store\r
+ * the pin level data of a specified port.\r
+ *\r
+ * \return Board_STATUS in case of success or appropriate error code.\r
+ *\r
+ */\r
+Board_STATUS Board_i2cIoExpReadOutputPort(uint8_t slaveAddr,\r
+ i2cIoExpType_t ioExpType,\r
+ i2cIoExpPortNumber_t portNum,\r
+ uint8_t *data);\r
+\r
+/**\r
+ * \brief Reads the signal level of all the pins of the specified port.\r
+ *\r
+ * \param slaveAddr [IN] I2C Slave Address.\r
+ * \param ioExpType [IN] IO expander type.\r
+ * X_PORT_IOEXP - Total number of ports\r
+ * in slave device.\r
+ * \param portNum [IN] Port number of the i2c slave device\r
+ * PORTNUM_X - Port number of a slave\r
+ * device.\r
+ * \param data [IN/OUT] Pointer to the data buffer to store\r
+ * the pin level data of a specified port.\r
+ *\r
+ * \return Board_STATUS in case of success or appropriate error code.\r
+ *\r
+ */\r
+Board_STATUS Board_i2cIoExpReadInputPort(uint8_t slaveAddr,\r
+ i2cIoExpType_t ioExpType,\r
+ i2cIoExpPortNumber_t portNum,\r
+ uint8_t *data);\r
+\r
+/**\r
+ * \brief Sets the direction of all the pins of the specified Port.\r
+ *\r
+ * \param slaveAddr [IN] I2C Slave Address.\r
+ * \param ioExpType [IN] IO expander type.\r
+ * X_PORT_IOEXP - Total number of ports\r
+ * in that slave device.\r
+ * \param portNum [IN] Port number of the i2c slave device\r
+ * PORTNUM_X - Port number of a\r
+ * slave device.\r
+ * \param data [IN] Register data to be configured.\r
+ *\r
+ * \return Board_STATUS in case of success or appropriate error code.\r
+ *\r
+ */\r
+Board_STATUS Board_i2cIoExpSetPortDirection(uint8_t slaveAddr,\r
+ i2cIoExpType_t ioExpType,\r
+ i2cIoExpPortNumber_t portNum,\r
+ uint8_t data);\r
+\r
+/**\r
+ * \brief Sets the direction of the specified pin of the specified port.\r
+ *\r
+ * \param slaveAddr [IN] I2C Slave Address.\r
+ * \param ioExpType [IN] IO expander type.\r
+ * X_PORT_IOEXP - Total number of ports\r
+ * in slave device.\r
+ * \param portNum [IN] Port number of the i2c slave device\r
+ * PORTNUM_X - Port number of a slave\r
+ * device.\r
+ * \param pinNum [IN] Pin with in the specified port of\r
+ * the i2c slave device.\r
+ * PIN_NUM_X - Pin number.\r
+ * \param direction [IN] Direction of the pin to be configured.\r
+ *\r
+ * \return Board_STATUS in case of success or appropriate error code.\r
+ *\r
+ */\r
+Board_STATUS Board_i2cIoExpSetPinDirection(uint8_t slaveAddr,\r
+ i2cIoExpType_t ioExpType,\r
+ i2cIoExpPortNumber_t portNum,\r
+ i2cIoExpPinNumber_t pinNum,\r
+ i2cIoExpPinDirection_t direction);\r
+\r
+/**\r
+ * \brief Sets the signal level of all the pins of the specified port.\r
+ *\r
+ * \param slaveAddr [IN] I2C Slave Address.\r
+ * \param ioExpType [IN] IO expander type.\r
+ * X_PORT_IOEXP - Total number of ports\r
+ * in slave device.\r
+ * \param portNum [IN] Port number of the i2c slave device\r
+ * PORTNUM_X - Port number of a slave\r
+ * device.\r
+ * \param data [IN] Signal level data of the pins to be\r
+ * configured.\r
+ *\r
+ * \return Board_STATUS in case of success or appropriate error code.\r
+ *\r
+ */\r
+Board_STATUS Board_i2cIoExpWritePort(uint8_t slaveAddr,\r
+ i2cIoExpType_t ioExpType,\r
+ i2cIoExpPortNumber_t portNum,\r
+ uint8_t data);\r
+\r
+/**\r
+ * \brief Sets the signal level of the specified pin of the specified port.\r
+ *\r
+ * \param slaveAddr [IN] I2C Slave Address.\r
+ * \param ioExpType [IN] IO expander type.\r
+ * X_PORT_IOEXP - Total number of ports\r
+ * in slave device.\r
+ * \param portNum [IN] Port number of the i2c slave device\r
+ * PORTNUM_X - Port number of a slave\r
+ * device.\r
+ * \param pinNum [IN] Pin with in the specified port of\r
+ * the i2c slave device.\r
+ * PIN_NUM_X - Pin number.\r
+ * \param signalLevel [IN] Signal level data of the pin to be\r
+ * configured.\r
+ *\r
+ * \return Board_STATUS in case of success or appropriate error code.\r
+ *\r
+ */\r
+Board_STATUS Board_i2cIoExpPinLevelSet(uint8_t slaveAddr,\r
+ i2cIoExpType_t ioExpType,\r
+ i2cIoExpPortNumber_t portNum,\r
+ i2cIoExpPinNumber_t pinNum,\r
+ i2cIoExpSignalLevel_t signalLevel);\r
+\r
+\r
+/**\r
+ * \brief Reads the signal level of specified pin of the specified port.\r
+ *\r
+ * \param slaveAddr [IN] I2C Slave Address.\r
+ * \param ioExpType [IN] IO expander type.\r
+ * X_PORT_IOEXP - Total number of ports\r
+ * in slave device.\r
+ * \param portNum [IN] Port number of the i2c slave device.\r
+ * PORTNUM_X - Port number of a slave\r
+ * device.\r
+ * \param pinNum [IN] Pin number of the specified port.\r
+ * PIN_NUM_X - Pin number.\r
+ * \param signalLevel [IN/OUT] Data buffer to store specified pin\r
+ * level of a specified port.\r
+ *\r
+ * \return Board_STATUS in case of success or appropriate error code.\r
+ *\r
+ */\r
+Board_STATUS Board_i2cIoExpPinLevelGet(uint8_t slaveAddr,\r
+ i2cIoExpType_t ioExpType,\r
+ i2cIoExpPortNumber_t portNum,\r
+ i2cIoExpPinNumber_t pinNum,\r
+ uint8_t *signalLevel);\r
+\r
+/**\r
+ * \brief Initializes the i2c instance connected to the i2c IO Expander.\r
+ *\r
+ * \return Board_STATUS in case of success or appropriate error code.\r
+ *\r
+ */\r
+Board_STATUS Board_i2cIoExpInit(uint8_t i2cInst);\r
+ \r
+/**\r
+ * \brief de-initializes the i2c instance connected to the i2c IO Expander.\r
+ *\r
+ */\r
+void Board_i2cIoExpDeInit(void);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif /* __cplusplus */\r
+\r
+#endif /* _BOARD_I2C_IO_EXP_H_ */\r
diff --git a/packages/ti/board/src/am64x_evm/include/board_internal.h b/packages/ti/board/src/am64x_evm/include/board_internal.h
--- /dev/null
@@ -0,0 +1,245 @@
+/******************************************************************************\r
+ * Copyright (c) 2019 Texas Instruments Incorporated - http://www.ti.com\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the\r
+ * distribution.\r
+ *\r
+ * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ *****************************************************************************/\r
+\r
+#ifndef BOARD_INTERNAL_H_\r
+#define BOARD_INTERNAL_H_\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/*****************************************************************************\r
+ * Include Files *\r
+ *****************************************************************************/\r
+#include <ti/csl/csl_types.h>\r
+#include <ti/csl/cslr_device.h>\r
+\r
+#include <ti/drv/i2c/I2C.h>\r
+#include <ti/drv/i2c/soc/I2C_soc.h>\r
+\r
+#include <ti/drv/uart/UART.h>\r
+#include <ti/drv/uart/UART_stdio.h>\r
+#include <ti/drv/uart/soc/UART_soc.h>\r
+\r
+#include <ti/board/board.h>\r
+#include <ti/csl/tistdtypes.h>\r
+#include <stdio.h>\r
+#include <stdbool.h>\r
+\r
+#define MODE_PIN_MASK (0xFU)\r
+#define PINMUX_BIT_MASK (0xFFF8FFF0U)\r
+#define GPIO_PIN_MUX_CFG (0x50007U)\r
+\r
+/* MAIN CTRL base address + offset to beginning of PAD CONFIG section */\r
+#define MAIN_PMUX_CTRL (0) //J7ES_TODO: Need to update\r
+\r
+/* WKUP CTRL base address + offset to beginning of PAD CONFIG section */\r
+#define WKUP_PMUX_CTRL (0) //J7ES_TODO: Need to update\r
+\r
+/*****************************************************************************\r
+ * Internal Objects *\r
+ *****************************************************************************/\r
+extern const I2C_Config I2C_config[];\r
+\r
+typedef struct\r
+{\r
+ I2C_Handle i2cHandle;\r
+} Board_gblObj;\r
+\r
+extern Board_gblObj Board_obj;\r
+\r
+/****************************************************************************/\r
+\r
+#define KICK0_UNLOCK_VAL (0x68EF3490U)\r
+#define KICK1_UNLOCK_VAL (0xD172BC5AU)\r
+\r
+/* The below macro are for temporary use only, Once the CSL macros are \r
+ * added these can be removed */ \r
+\r
+#define MAIN_PSC_ADDR_OFFSET (0x80000000U) //J7ES_TODO: Need to update\r
+#define WAKEUP_PSC_ADDR_OFFSET (0x20000000U) //J7ES_TODO: Need to update\r
+\r
+/*****************************************************************************\r
+ * Function Prototypes *\r
+ *****************************************************************************/\r
+\r
+/**\r
+ *\r
+ * \brief Board pinmuxing enable function\r
+ *\r
+ * Enables pinmux for the Maxwell idk board interfaces. Pin mux is done based on the\r
+ * default/primary functionality of the board. Any pins shared by multiple\r
+ * interfaces need to be reconfigured to access the secondary functionality.\r
+ *\r
+ * \return BOARD_SOK in case of success or appropriate error code\r
+ *\r
+ */\r
+Board_STATUS Board_pinmuxConfig(void);\r
+\r
+/**\r
+ *\r
+ * \brief Board PLL initialization function\r
+ *\r
+ * Configures different PLL controller modules. This enables all the PLL\r
+ * controllers on the SoC with default configurations.\r
+ *\r
+ * \return BOARD_SOK in case of success or appropriate error code\r
+ */\r
+Board_STATUS Board_PLLInit(uint32_t modId, uint32_t clkId, uint64_t clkRate);\r
+\r
+/**\r
+ *\r
+ * \brief DDR4 Initialization function\r
+ *\r
+ * Initializes the DDR timing parameters. Sets the DDR timing parameters\r
+ * based in the DDR PLL controller configuration done by the board library.\r
+ * Any changes to DDR PLL requires change to DDR timing.\r
+ *\r
+ * \return BOARD_SOK in case of success or appropriate error code\r
+ *\r
+ */\r
+Board_STATUS Board_DDRInit(void);\r
+\r
+/**\r
+ *\r
+ * \brief clock Initialization function\r
+ *\r
+ * Enables different power domains and peripheral clocks of the SoC.\r
+ * Some of the power domains and peripherals will be off by default.\r
+ * Enabling the power domains is mandatory before accessing using\r
+ * board interfaces connected to those peripherals.\r
+ *\r
+ * \return BOARD_SOK in case of success or appropriate error code\r
+ *\r
+ */\r
+Board_STATUS Board_moduleClockInit(void);\r
+\r
+/**\r
+ * \brief Board specific configurations for Gigabit Ethernet PHYs\r
+ *\r
+ * This function takes care of configuring the internal delays for gigabit\r
+ * Ethernet PHY. 2.25ns delay is configured for Rx, and .25ns delay is\r
+ * configured for Tx\r
+ *\r
+ * \return none\r
+ */\r
+Board_STATUS Board_mcuEthConfig(void);\r
+\r
+/**\r
+ * \brief Board specific configurations for ICSS EMAC Ethernet PHYs\r
+ *\r
+ * This function takes care of making several board level configurations\r
+ * required for ICSS EMAC PHY as listed below.\r
+ * - Disabling internal SoC pull up/down for the pins used for strapping\r
+ * - Setting the GPIOs for PHY reset, routing ICSS signals to PHYs,\r
+ * PHY interrupt lines.\r
+ * - Resetting the PHYs for proper address latching\r
+ * - MDIO initialization\r
+ * - MDIO configuration for setting MII mode\r
+ *\r
+ * \return none\r
+ */\r
+Board_STATUS Board_icssEthConfig(void);\r
+\r
+/**\r
+ * \brief This function initializes the default UART instance for use for\r
+ * console operations.\r
+ *\r
+ * \return Board_STATUS in case of success or appropriate error code.\r
+ *\r
+ */\r
+Board_STATUS Board_uartStdioInit(void);\r
+\r
+/**\r
+ * \brief This function initializes the i2c instance connected to the\r
+ * board Id EEPROM.\r
+ * This function disables the interrupt mode as the Board i2c instance\r
+ * doesn't require interrupt mode and restores back original at the end.\r
+ *\r
+ * \param i2cInst [IN] i2c instance connected to board Id EEPROM and\r
+ * IO expander device.\r
+ *\r
+ * \return Board_STATUS in case of success or appropriate error code.\r
+ *\r
+ */\r
+Board_STATUS Board_internalInitI2C(uint8_t i2cInst);\r
+\r
+/**\r
+ * \brief board detect test\r
+ *\r
+ * This function used to check whether the specified board exists.\r
+ *\r
+ * \param detectBoard [IN] enum used to send the name of the\r
+ * board going to be detected.\r
+ *\r
+ * \return bool\r
+ * true - In case of specified board detected\r
+ * false - In case of specified board not detected.\r
+ *\r
+ */\r
+bool Board_detectBoard(boardPresDetect_t detectBoard);\r
+\r
+/**\r
+ * \brief Unlocks MMR registers\r
+ *\r
+ * \return Board_STATUS\r
+ */\r
+Board_STATUS Board_unlockMMR(void);\r
+\r
+/**\r
+ * \brief Serdes configurations\r
+ *\r
+ * The function detects the personality boards connected and configures the\r
+ * respective module.\r
+ *\r
+ * \return BOARD_SOK in case of success or appropriate error code\r
+ *\r
+ */\r
+Board_STATUS Board_serdesCfg(void);\r
+\r
+/**\r
+ *\r
+ * \brief Board PLL initialization function\r
+ *\r
+ * Configures different PLL controller modules. This enables all the PLL\r
+ * controllers on the SoC with default configurations.\r
+ *\r
+ * \return BOARD_SOK in case of success or appropriate error code\r
+ */\r
+Board_STATUS Board_PLLInitAll(void);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif /* __cplusplus */\r
+\r
+#endif /* BOARD_INTERNAL_H_ */\r
diff --git a/packages/ti/board/src/am64x_evm/include/board_pinmux.h b/packages/ti/board/src/am64x_evm/include/board_pinmux.h
--- /dev/null
@@ -0,0 +1,102 @@
+/******************************************************************************\r
+ * Copyright (c) 2019 Texas Instruments Incorporated - http://www.ti.com\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the\r
+ * distribution.\r
+ *\r
+ * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ *****************************************************************************/\r
+\r
+#ifndef PINMUX_H\r
+#define PINMUX_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/**\r
+ * \file pinmux.h\r
+ *\r
+ * \brief Board pinmux header file\r
+ *\r
+ * This file includes the structures to enable the pinmux configurations\r
+ *\r
+ */\r
+\r
+#include <ti/csl/tistdtypes.h>\r
+\r
+/* ========================================================================== */\r
+/* Structures and Enums */\r
+/* ========================================================================== */\r
+\r
+/**\r
+ * \brief Structure defining the pin configuration parameters.\r
+ *\r
+ */\r
+typedef struct pinmuxPerCfg\r
+{\r
+ int16_t pinOffset;\r
+ /**< Register offset for configuring the pin */\r
+ int32_t pinSettings;\r
+ /**< Value to be configured,\r
+ - Active mode configurations like mux mode, pull resistor, and buffer mode\r
+ */\r
+}pinmuxPerCfg_t;\r
+\r
+/**\r
+ * \brief Structure defining the pin configuration for different instances of\r
+ * a module.\r
+ */\r
+typedef struct pinmuxModuleCfg\r
+{\r
+ int16_t modInstNum;\r
+ /**< Instance number of the ip */\r
+ int16_t doPinConfig;\r
+ /**< Flag indicating whether this instance has to be configured. This flag\r
+ can be altered with separate API (PinMuxConfigEnable()).\r
+ Default configuration will be set to TRUE, but can be altered for\r
+ different scenarios (like power management). */\r
+ pinmuxPerCfg_t* instPins;\r
+ /**< Pointer to list of pins corresponding to this instance */\r
+}pinmuxModuleCfg_t;\r
+\r
+/**\r
+ * \brief Structure defining the pin configuration of a board.\r
+ */\r
+typedef struct pinmuxBoardCfg\r
+{\r
+ int32_t moduleId;\r
+ /**< Module ID */\r
+ pinmuxModuleCfg_t* modulePinCfg;\r
+ /**< Pin config info of a module: #pinmuxModuleCfg_t */\r
+}pinmuxBoardCfg_t;\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif /* __cplusplus */\r
+\r
+#endif\r
diff --git a/packages/ti/board/src/am64x_evm/include/board_pll.h b/packages/ti/board/src/am64x_evm/include/board_pll.h
--- /dev/null
@@ -0,0 +1,60 @@
+/******************************************************************************\r
+ * Copyright (c) 2019 Texas Instruments Incorporated - http://www.ti.com\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the\r
+ * distribution.\r
+ *\r
+ * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ *****************************************************************************/\r
+ \r
+#ifndef BOARD_PLL_H\r
+#define BOARD_PLL_H\r
+\r
+#include "board_internal.h"\r
+#include "board_pll.h"\r
+#include "ti/csl/soc.h"\r
+#include <ti/csl/hw_types.h>\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/**\r
+ * \file board_pll.h\r
+ *\r
+ * \brief Board PLL configurations header file\r
+ *\r
+ * This file includes the structures, enums and register offsets\r
+ * for PLL configurations\r
+ *\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif /* __cplusplus */\r
+\r
+#endif /* BOARD_PLL_H */\r
diff --git a/packages/ti/board/src/am64x_evm/include/board_serdes_cfg.h b/packages/ti/board/src/am64x_evm/include/board_serdes_cfg.h
--- /dev/null
@@ -0,0 +1,77 @@
+/******************************************************************************\r
+ * Copyright (c) 2019 Texas Instruments Incorporated - http://www.ti.com\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the\r
+ * distribution.\r
+ *\r
+ * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ *****************************************************************************/\r
+\r
+/**\r
+ * \file board_serdes_cfg.h\r
+ *\r
+ * \brief Board serdes configurations header file.\r
+ *\r
+ * This file includes the structures, enums and register offsets\r
+ * for configuring the serdes module.\r
+ *\r
+ */\r
+\r
+#ifndef _BOARD_SERDES_CFG_H_\r
+#define _BOARD_SERDES_CFG_H_\r
+\r
+#include <stdio.h>\r
+#include <ti/csl/soc.h>\r
+#include <ti/csl/hw_types.h>\r
+#include <ti/csl/cslr.h>\r
+#include <ti/csl/csl_serdes.h>\r
+#include <ti/csl/csl_serdes_pcie.h>\r
+#include <ti/csl/csl_serdes_usb.h>\r
+\r
+#include "board.h"\r
+#include "board_internal.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/**\r
+ * \brief serdes configurations\r
+ *\r
+ * The function configures the serdes1 module for one lane pcie interface\r
+ *\r
+ * \return BOARD_SOK in case of success or appropriate error code\r
+ *\r
+ */\r
+Board_STATUS Board_serdesCfg(void);\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif /* __cplusplus */\r
+\r
+#endif /* _BOARD_SERDES_CFG_H_ */\r
diff --git a/packages/ti/board/src/am64x_evm/src_files_am64x_evm.mk b/packages/ti/board/src/am64x_evm/src_files_am64x_evm.mk
--- /dev/null
@@ -0,0 +1,9 @@
+\r
+SRCDIR += src/am64x_evm src/am64x_evm/include\r
+INCDIR += src/am64x_evm src/am64x_evm/include\r
+\r
+# Common source files across all platforms and cores\r
+SRCS_COMMON += board_init.c board_lld_init.c board_clock.c board_mmr.c board_pll.c\r
+SRCS_COMMON += board_ddr.c board_info.c board_ethernet_config.c board_pinmux.c board_serdes_cfg.c\r
+\r
+PACKAGE_SRCS_COMMON = src/am64x_evm/src_files_am64x_evm.mk\r
index e4de55cce638c875d7af397727f790ac4c9cd862..acb41311eceb4bbc4b88754c07fc588e45ddf9a4 100755 (executable)
break;\r
}\r
\r
+#if defined(VLAB_SIM)\r
case BOARD_FLASH_ID_MT35XU512ABA1G12:\r
+#else\r
+ case BOARD_FLASH_ID_MT35XU512ABA1G12:\r
+ case BOARD_FLASH_ID_MT35XU256ABA1G12:\r
+#endif\r
{\r
flashIntf = BOARD_FLASH_NOR_OSPI;\r
break;\r
@@ -138,6 +143,7 @@ Board_flashHandle Board_flashOpen(uint32_t deviceId, uint32_t portNum, void *par
(deviceId == BOARD_FLASH_ID_NORN25Q128A13ESF40F) || \\r
(deviceId == BOARD_FLASH_ID_MT25QU512ABB) || \\r
(deviceId == BOARD_FLASH_ID_MT35XU512ABA1G12) || \\r
+ (deviceId == BOARD_FLASH_ID_MT35XU256ABA1G12) || \\r
(deviceId == BOARD_FLASH_ID_S71KS512S)\r
)\r
{\r
(flashInfo->device_id == BOARD_FLASH_ID_NORN25Q128A13ESF40F) || \\r
(flashInfo->device_id == BOARD_FLASH_ID_MT25QU512ABB) || \\r
(flashInfo->device_id == BOARD_FLASH_ID_MT35XU512ABA1G12) || \\r
+ (flashInfo->device_id == BOARD_FLASH_ID_MT35XU256ABA1G12) || \\r
(flashInfo->device_id == BOARD_FLASH_ID_S71KS512S)\r
)\r
{\r
(flashInfo->device_id == BOARD_FLASH_ID_NORN25Q128A13ESF40F) || \\r
(flashInfo->device_id == BOARD_FLASH_ID_MT25QU512ABB) || \\r
(flashInfo->device_id == BOARD_FLASH_ID_MT35XU512ABA1G12) || \\r
+ (flashInfo->device_id == BOARD_FLASH_ID_MT35XU256ABA1G12) || \\r
(flashInfo->device_id == BOARD_FLASH_ID_S71KS512S)\r
)\r
{\r
(flashInfo->device_id == BOARD_FLASH_ID_NORN25Q128) || \\r
(flashInfo->device_id == BOARD_FLASH_ID_NORN25Q128A13ESF40F) || \\r
(flashInfo->device_id == BOARD_FLASH_ID_MT29F4G08ABAEAWP) || \\r
- (flashInfo->device_id == BOARD_FLASH_ID_MT35XU512ABA1G12)\r
+ (flashInfo->device_id == BOARD_FLASH_ID_MT35XU512ABA1G12) || \\r
+ (flashInfo->device_id == BOARD_FLASH_ID_MT35XU256ABA1G12)\r
)\r
{\r
block_count = flashInfo->block_count;\r
(flashInfo->device_id == BOARD_FLASH_ID_MT29F4G08ABAEAWP) || \\r
(flashInfo->device_id == BOARD_FLASH_ID_MT25QU512ABB) || \\r
(flashInfo->device_id == BOARD_FLASH_ID_MT35XU512ABA1G12) || \\r
+ (flashInfo->device_id == BOARD_FLASH_ID_MT35XU256ABA1G12) || \\r
(flashInfo->device_id == BOARD_FLASH_ID_S71KS512S)\r
)\r
{\r
(flashInfo->device_id == BOARD_FLASH_ID_MT29F4G08ABAEAWP) || \\r
(flashInfo->device_id == BOARD_FLASH_ID_MT25QU512ABB) || \\r
(flashInfo->device_id == BOARD_FLASH_ID_MT35XU512ABA1G12) || \\r
+ (flashInfo->device_id == BOARD_FLASH_ID_MT35XU256ABA1G12) || \\r
(flashInfo->device_id == BOARD_FLASH_ID_S71KS512S)\r
)\r
{\r
(flashInfo->device_id == BOARD_FLASH_ID_NORN25Q128A13ESF40F) || \\r
(flashInfo->device_id == BOARD_FLASH_ID_MT25QU512ABB) || \\r
(flashInfo->device_id == BOARD_FLASH_ID_MT35XU512ABA1G12) || \\r
+ (flashInfo->device_id == BOARD_FLASH_ID_MT35XU256ABA1G12) || \\r
(flashInfo->device_id == BOARD_FLASH_ID_S71KS512S)\r
)\r
{\r
(flashInfo->device_id == BOARD_FLASH_ID_NORN25Q128A13ESF40F) || \\r
(flashInfo->device_id == BOARD_FLASH_ID_MT25QU512ABB) || \\r
(flashInfo->device_id == BOARD_FLASH_ID_MT35XU512ABA1G12) || \\r
+ (flashInfo->device_id == BOARD_FLASH_ID_MT35XU256ABA1G12) || \\r
(flashInfo->device_id == BOARD_FLASH_ID_S71KS512S)\r
)\r
{\r
diff --git a/packages/ti/board/src/flash/include/board_flash.h b/packages/ti/board/src/flash/include/board_flash.h
index dcc1314a26d34817ec40e9d5705ab0430a86cdbb..814889f09f77314c5df6d966d0d387e9dfc977ac 100755 (executable)
#define BOARD_FLASH_ID_S25FL256S (0x0219U) /**< Spansion 32MB NOR flash */
#define BOARD_FLASH_ID_MT29W160EB (0x2249U) /**< Micron 2MB NOR flash */
#define BOARD_FLASH_ID_MT29F4G08ABAEAWP (0xDC90U) /**< Micron 512MB NAND flash */
-#if defined(j721e_sim)
-#define BOARD_FLASH_ID_MT35XU512ABA1G12 (0x2018U) /**< J7 VLAB */
+#if defined(VLAB_SIM)
+#define BOARD_FLASH_ID_MT35XU512ABA1G12 (0x5B1AU) /**< J7 VLAB SIM flash ID */
+#define BOARD_FLASH_ID_MT35XU256ABA1G12 (0x5B1AU) /**< AM64x VLAB SIM flash ID */
#else
#define BOARD_FLASH_ID_MT35XU512ABA1G12 (0x5B1AU) /**< Micro 512Mb NOR flash device Id */
-#define BOARD_FLASH_ID_MT25QU512ABB (0xBB20) /**< 64MB NOR Flash */
+#define BOARD_FLASH_ID_MT35XU256ABA1G12 (0x5B19U) /**< Micro 256Mb NOR flash device Id */
#endif
+#define BOARD_FLASH_ID_MT25QU512ABB (0xBB20) /**< 64MB NOR Flash */
#define BOARD_FLASH_ID_S71KS512S (0x007EU) /**< 512 Mb cypress Hyperflash device Id */
diff --git a/packages/ti/board/src/flash/nor/device/m35xu256.h b/packages/ti/board/src/flash/nor/device/m35xu256.h
--- /dev/null
@@ -0,0 +1,130 @@
+/*
+ * Copyright (c) 2020, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ *
+ * \file m35xu256.h
+ *
+ * \brief This file contains M35XU256 NOR device definitions
+ *
+ *****************************************************************************/
+#ifndef M35XU256_H_
+#define M35XU256_H_
+
+#include <ti/drv/spi/SPI.h>
+
+/**************************************************************************
+ ** Macro Definitions
+ **************************************************************************/
+
+/** Macro to enable 4 byte addressing */
+/* #define EXT_ADDRESS_ENABLE (0U) */
+
+/** FLASH device specific items (note: sizes are in bytes) */
+#define NOR_BLOCK_SIZE (128U * 1024U)
+#define NOR_SECTOR_SIZE (4U * 1024U)
+#define NOR_SIZE (32U * 1024U * 1024U)
+#define NOR_NUM_BLOCKS (NOR_SIZE / NOR_BLOCK_SIZE)
+#define NOR_NUM_SECTORS (NOR_SIZE / NOR_SECTOR_SIZE)
+#define NOR_PAGE_SIZE (256U)
+#define NOR_NUM_PAGES_PER_SECTOR (NOR_SECTOR_SIZE / NOR_PAGE_SIZE)
+#define NOR_NUM_PAGES_PER_BLOCK (NOR_BLOCK_SIZE / NOR_PAGE_SIZE)
+
+/** Flash device commands */
+#define NOR_BE_SECTOR_NUM (-1U)
+#define NOR_CMD_BULK_ERASE (0x60U)
+#define NOR_CMD_WRR (0x01U)
+#define NOR_CMD_WREN (0x06U)
+#define NOR_CMD_RDSR (0x05U)
+#define NOR_CMD_RDCR_VOL (0x85U)
+#define NOR_CMD_RDCR_NVOL (0xB5U)
+#define NOR_CMD_RDID (0x9FU)
+
+/** Different commands for 4 byte addressing and 3 byte addressing */
+#ifdef EXT_ADDRESS_ENABLE
+#define NOR_CMD_BLOCK_ERASE (0xDCU)
+#define NOR_CMD_SECTOR_ERASE (0x21U)
+#define NOR_CMD_READ (0x13U)
+#define NOR_CMD_FAST_READ (0x0CU)
+#define NOR_CMD_OCTAL_O_FAST_RD (0x7CU)
+#define NOR_CMD_OCTAL_IO_FAST_RD (0xCCU)
+#define NOR_CMD_OCTAL_READ (NOR_CMD_OCTAL_O_FAST_RD)
+#define NOR_CMD_PAGE_PROG (0x12U)
+#define NOR_CMD_OCTAL_FAST_PROG (0x84U)
+#define NOR_CMD_EXT_OCTAL_FAST_PROG (0x8EU)
+#define NOR_CMD_OCTAL_PROG (NOR_CMD_OCTAL_FAST_PROG)
+#else
+#define NOR_CMD_BLOCK_ERASE (0xD8U)
+#define NOR_CMD_SECTOR_ERASE (0x20U)
+#define NOR_CMD_READ (0x03U)
+#define NOR_CMD_FAST_READ (0x0BU)
+#define NOR_CMD_OCTAL_O_FAST_RD (0x8BU)
+#define NOR_CMD_OCTAL_IO_FAST_RD (0xCBU)
+#define NOR_CMD_OCTAL_DDR_O_FAST_RD (0x9DU)
+#define NOR_CMD_OCTAL_DDR_IO_FAST_RD (0xFDU)
+#define NOR_CMD_OCTAL_READ (NOR_CMD_OCTAL_O_FAST_RD)
+#define NOR_CMD_PAGE_PROG (0x02U)
+#define NOR_CMD_OCTAL_FAST_PROG (0x82U)
+#define NOR_CMD_EXT_OCTAL_FAST_PROG (0xC2U)
+#define NOR_CMD_OCTAL_PROG (NOR_CMD_OCTAL_FAST_PROG)
+#define NOR_CMD_WRITE_VCR (0x81U)
+#define NOR_CMD_READ_VCR (0x85U)
+#endif
+
+/* \brief Read ID command definitions */
+#define NOR_RDID_NUM_BYTES (0x3U)
+#define NOR_MANF_ID (0x2CU) /* Manufacturer ID */
+#if defined(VLAB_SIM)
+#define NOR_DEVICE_ID (0x5B1A) /* Device ID */
+#else
+#define NOR_DEVICE_ID (0x5B19) /* Device ID */
+#endif
+
+/** Status Register, Write-in-Progress bit */
+#define NOR_SR_WIP (1U << 0U)
+
+/** Dummy cycles for Read operation */
+/** Dummy cycles for Read operation */
+#define NOR_SINGLE_READ_DUMMY_CYCLE (0U)
+#define NOR_OCTAL_READ_DUMMY_CYCLE (16U)
+
+
+/** In Micro seconds */
+#define NOR_PAGE_PROG_TIMEOUT (400U)
+#define NOR_SECTOR_ERASE_TIMEOUT (600U * 1000U)
+#define NOR_WRR_WRITE_TIMEOUT (600U * 1000U)
+#define NOR_BULK_ERASE_TIMEOUT (110U * 1000U * 1000U)
+
+#endif /* M35XU256_H_ */
+
+/* Nothing past this point */
diff --git a/packages/ti/board/src/flash/nor/device/m35xu512.h b/packages/ti/board/src/flash/nor/device/m35xu512.h
index cf5212f462dff59a57e5877a1b865528afe8f71f..205e8ec6dd5778c3e1529f590206d81b7c655a5a 100644 (file)
/* \brief Read ID command definitions */
#define NOR_RDID_NUM_BYTES (0x3U)
-#if defined(j721e_sim)
-#define NOR_MANF_ID (0x01U) /* Manufacturer ID */
-#define NOR_DEVICE_ID (0x2018) /* Device ID */
-#else
#define NOR_MANF_ID (0x2CU) /* Manufacturer ID */
#define NOR_DEVICE_ID (0x5B1A) /* Device ID */
-#endif
/** Status Register, Write-in-Progress bit */
#define NOR_SR_WIP (1U << 0U)
index 44081f89305f5cd39a17fb6028e87ea7698e5b6f..273b691c2a6673f5df02758e1a51bdd5b7c5f5ee 100755 (executable)
NULL
}
};
-#elif defined (am65xx_evm) || defined (am65xx_idk)
+#elif defined (am65xx_evm) || defined (am65xx_idk) || defined (am64x_evm)
NOR_Config Nor_config[BOARD_FLASH_NOR_INTF_MAX] =
{
{
diff --git a/packages/ti/board/src/flash/nor/ospi/nor_ospi.c b/packages/ti/board/src/flash/nor/ospi/nor_ospi.c
index 8d6afca69c8ce35351c3f244c63761ee43509c3e..8ee48222613a44a0de32e20ba2dff1a69ed6f968 100755 (executable)
#if defined (j7200_evm)\r
/* SPI entry offset is at index 5 of SPI config array */\r
#define SPI_CONFIG_OFFSET (5U)\r
+#elif defined (am64x_evm)\r
+#define SPI_CONFIG_OFFSET (7U)\r
#else\r
#define SPI_CONFIG_OFFSET CSL_MCSPI_PER_CNT\r
#endif\r
diff --git a/packages/ti/board/src/flash/nor/ospi/nor_ospi.h b/packages/ti/board/src/flash/nor/ospi/nor_ospi.h
index defe1742130bf1f28cca53d41d87090a2cb5d327..ba044809a43f9b8555437007161ecfb92c51d936 100644 (file)
/*
- * Copyright (c) 2018, Texas Instruments Incorporated
+ * Copyright (c) 2018 - 2020, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
#include <ti/board/src/flash/nor/nor.h>
#include <ti/drv/spi/SPI.h>
#include <ti/drv/spi/soc/SPI_soc.h>
+#if defined(am64x_evm)
+#include <ti/board/src/flash/nor/device/m35xu256.h>
+#else
#include <ti/board/src/flash/nor/device/m35xu512.h>
+#endif
/**************************************************************************
** Macro Definitions
diff --git a/packages/ti/board/src/flash/src_files_flash.mk b/packages/ti/board/src/flash/src_files_flash.mk
index 9443dd072a32cce87f9bc11883e40cb76b6f6b71..68cfa013b06062b24b8b88cd6774c6053cdefb13 100755 (executable)
endif
-ifeq ($(BOARD),$(filter $(BOARD), am65xx_idk am65xx_evm j721e_sim j721e_evm j7200_evm))
+ifeq ($(BOARD),$(filter $(BOARD), am65xx_idk am65xx_evm j721e_sim j721e_evm j7200_evm am64x_evm))
SRCDIR += src/flash/nor src/flash/nor/device src/flash/nor/ospi
INCDIR += src/flash/nor src/flash/nor/device src/flash/nor/ospi
SRCS_COMMON += nor_ospi.c nor.c
PACKAGE_SRCS_COMMON += src/flash/nor/nor.c src/flash/nor/nor.h
PACKAGE_SRCS_COMMON += src/flash/nor/ospi/nor_ospi.c src/flash/nor/ospi/nor_ospi.h
+ifeq ($(BOARD),$(filter $(BOARD), am64x_evm))
+PACKAGE_SRCS_COMMON += src/flash/nor/device/m35xu256.h
+else
PACKAGE_SRCS_COMMON += src/flash/nor/device/m35xu512.h
endif
+endif
ifeq ($(BOARD),$(filter $(BOARD), j721e_sim j721e_evm j7200_evm))
SRCDIR += src/flash/nor/hyperflash
diff --git a/packages/ti/board/utils/uniflash/target/src/ospi/ospi.h b/packages/ti/board/utils/uniflash/target/src/ospi/ospi.h
index e1dee9b49a74357fab0720ed6aead2f2ce41d8c1..1349e53876d0f27cbe035b9255e068ad198d6b19 100755 (executable)
#if defined(SOC_AM65XX) || defined(j721e_evm)
#define OSPI_FLASH_ID BOARD_FLASH_ID_MT35XU512ABA1G12
+#else
+#define OSPI_FLASH_ID BOARD_FLASH_ID_MT35XU256ABA1G12
#endif
#define OSPI_WR_LEN (256U)
old mode 100755 (executable)
new mode 100644 (file)
new mode 100644 (file)
index 957f72628723e52ab6aae60cbac9fe64432696d3..0a62fcd6cbe45bf9a59ae111d49fbe1ac433d09f 100644 (file)
MEMORY
{
- OCMCRAM : ORIGIN = 0x000041C00000, LENGTH = 0x00080000 /* MCUSS-OCMC RAM - 512KB */
-
-
- DDR_MPU1 (RWX) : ORIGIN = 0x80000000, LENGTH = 0x08000000
- DDR_IPC (RWX) : ORIGIN = 0x90000000, LENGTH = 0x02000000
-
/* am64x MCMS3 locations */
/* am64x Reserved Memory for ARM Trusted Firmware */
- MSMC3_ARM_FW (RWIX) : ORIGIN = 0x000070000000, LENGTH = 0x40000 /* 256KB */
- BOOTVECTOR : ORIGIN = 0x000070040000, LENGTH = 0x1000 /* 4KB */
- BOOTVECTOR_EL3 : ORIGIN = 0x000070041000, LENGTH = 0x1000 /* 4KB */
- MSMC_MPU1 (RWX) : ORIGIN = 0x000070042000, LENGTH = 0x7AE000 /* 7864KB */
- /* am64x Reserved Memory for DMSC Firmware */
- MSMC3_DMSC_FW (RWIX) : ORIGIN = 0x0000707F0000, LENGTH = 0x10000 /* 64KB */
+ MSMC3_ARM_STARTUP (RWIX) : ORIGIN = 0x000070000000, LENGTH = 0x800
+ MSMC_MPU2 (RWX) : ORIGIN = 0x000070000800, LENGTH = 0x800
+ MSMC_MPU1 (RWX) : ORIGIN = 0x000070001000, LENGTH = 0x200000-0x1000
+ DDR_MPU1 (RWX) : ORIGIN = 0x80000000, LENGTH = 0x80000000
+
}
-REGION_ALIAS("REGION_TEXT_EL3", DDR_MPU1);
-REGION_ALIAS("REGION_TEXT", DDR_MPU1);
-REGION_ALIAS("REGION_BSS", DDR_MPU1);
-REGION_ALIAS("REGION_DATA", DDR_MPU1);
-REGION_ALIAS("REGION_STACK", DDR_MPU1);
-REGION_ALIAS("REGION_HEAP", DDR_MPU1);
-REGION_ALIAS("REGION_ARM_EXIDX", DDR_MPU1);
-REGION_ALIAS("REGION_ARM_EXTAB", DDR_MPU1);
-REGION_ALIAS("REGION_TEXT_STARTUP", DDR_MPU1);
-REGION_ALIAS("REGION_DATA_BUFFER", DDR_MPU1);
-REGION_ALIAS("IPC_DATA_BUFFER_1", DDR_MPU1);
+REGION_ALIAS("REGION_TEXT_EL3", MSMC_MPU2);
+REGION_ALIAS("BOOTVECTOR_EL3", MSMC_MPU2);
+REGION_ALIAS("BOOTVECTOR", MSMC_MPU2);
+REGION_ALIAS("REGION_TEXT", MSMC_MPU1);
+REGION_ALIAS("REGION_BSS", MSMC_MPU1);
+REGION_ALIAS("REGION_DATA", MSMC_MPU1);
+REGION_ALIAS("REGION_STACK", MSMC_MPU1);
+REGION_ALIAS("REGION_HEAP", MSMC_MPU1);
+REGION_ALIAS("REGION_ARM_EXIDX", MSMC_MPU1);
+REGION_ALIAS("REGION_ARM_EXTAB", MSMC_MPU1);
+REGION_ALIAS("REGION_TEXT_STARTUP", MSMC3_ARM_STARTUP);
+REGION_ALIAS("REGION_DATA_BUFFER", MSMC_MPU1);
+REGION_ALIAS("IPC_DATA_BUFFER_1", MSMC_MPU1);
SECTIONS {
.vecs : {
*(.vecs)
- } > BOOTVECTOR AT> BOOTVECTOR
+ } > BOOTVECTOR AT> MSMC_MPU2
.vectors : {
*(.vectors)
- } > BOOTVECTOR_EL3 AT> BOOTVECTOR_EL3
+ } > BOOTVECTOR_EL3 AT> MSMC_MPU2
.text.el3 : {
*(.text.el3)
/* Ensure 8-byte alignment for descriptors and ensure inclusion */
__RT_SVC_DESCS_START__ = .;
KEEP(*(rt_svc_descs))
__RT_SVC_DESCS_END__ = .;
- } > REGION_TEXT_EL3 AT> REGION_TEXT_EL3
+ } > REGION_TEXT_EL3 AT> MSMC_MPU2
- .text.csl_a72_startup : {
- *(.text.csl_a72_startup)
+ .text.csl_a53_startup : {
+ *(.text.csl_a53_startup)
*(.Entry)
} > REGION_TEXT_STARTUP AT> REGION_TEXT_STARTUP
diff --git a/packages/ti/build/am64x/linker_m4f.lds b/packages/ti/build/am64x/linker_m4f.lds
--- /dev/null
@@ -0,0 +1,82 @@
+/* Linker Settings */
+--retain="*(.bootCode)"
+--retain="*(.startupCode)"
+--retain="*(.startupData)"
+--retain="*(.intvecs)"
+--retain="*(.intc_text)"
+--retain="*(.rstvectors)"
+--retain="*(.irqStack)"
+--retain="*(.fiqStack)"
+--retain="*(.abortStack)"
+--retain="*(.undStack)"
+--retain="*(.svcStack)"
+--fill_value=0
+--stack_size=0x2000
+--heap_size=0x1000
+
+-stack 0x2000 /* SOFTWARE STACK SIZE */
+-heap 0x2000 /* HEAP AREA SIZE */
+
+/* Stack Sizes for various modes */
+__IRQ_STACK_SIZE = 0x1000;
+__FIQ_STACK_SIZE = 0x1000;
+__ABORT_STACK_SIZE = 0x1000;
+__UND_STACK_SIZE = 0x1000;
+__SVC_STACK_SIZE = 0x1000;
+
+/* Memory Map */
+MEMORY
+{
+ VECS_M4F_MEM: org = 0x00000000 len = 0x040
+ IRAM_M4F_INTC_MEM: org = 0x00000040 len = 0x400 - 0x040
+ /* Memory assigned to move vector table for M4F core */
+ IRAM_M4F_VTBL: org = 0x00000400 len = 0x800
+ /* M4F internal memory locations */
+ IRAM_M4F_MEM (RWIX) : origin=0x0C00 length=0x30000 - 0xC00
+ DRAM_M4F_MEM (RWIX) : origin=0x30000 length=0x10000
+ DDR0 (RWIX) : origin=0x80000000 length=0x80000000 /* 2GB */
+}
+
+/* SPECIFY THE SECTIONS ALLOCATION INTO MEMORY */
+
+SECTIONS
+{
+
+ .intvecs : load > VECS_M4F_MEM
+ .intc_text : load > IRAM_M4F_INTC_MEM
+ .TI.noinit : load > IRAM_M4F_VTBL
+
+ .bootCode : {} palign(8) > IRAM_M4F_MEM
+ .startupCode : {} palign(8) > IRAM_M4F_MEM
+ .startupData : {} palign(8) > DRAM_M4F_MEM, type = NOINIT
+ .text : {} palign(8) > IRAM_M4F_MEM
+ .const : {} palign(8) > DRAM_M4F_MEM
+ .cinit : {} palign(8) > DRAM_M4F_MEM
+ .pinit : {} palign(8) > IRAM_M4F_MEM
+ .bss : {} align(4) > DRAM_M4F_MEM
+ .far : {} align(4) > DRAM_M4F_MEM
+ .data : {} palign(128) > DRAM_M4F_MEM
+ .boardcfg_data : {} palign(128) > DRAM_M4F_MEM
+ .sysmem : {} > DRAM_M4F_MEM
+ .data_buffer : {} palign(128) > DRAM_M4F_MEM
+
+ /* USB or any other LLD buffer for benchmarking */
+ .benchmark_buffer (NOLOAD) {} ALIGN (8) > DDR0
+
+ .stack : {} align(4) > DRAM_M4F_MEM
+ .irqStack : {. = . + __IRQ_STACK_SIZE;} align(4) > DRAM_M4F_MEM
+ RUN_START(__IRQ_STACK_START)
+ RUN_END(__IRQ_STACK_END)
+ .fiqStack : {. = . + __FIQ_STACK_SIZE;} align(4) > DRAM_M4F_MEM
+ RUN_START(__FIQ_STACK_START)
+ RUN_END(__FIQ_STACK_END)
+ .abortStack : {. = . + __ABORT_STACK_SIZE;} align(4) > DRAM_M4F_MEM
+ RUN_START(__ABORT_STACK_START)
+ RUN_END(__ABORT_STACK_END)
+ .undStack : {. = . + __UND_STACK_SIZE;} align(4) > DRAM_M4F_MEM
+ RUN_START(__UND_STACK_START)
+ RUN_END(__UND_STACK_END)
+ .svcStack : {. = . + __SVC_STACK_SIZE;} align(4) > DRAM_M4F_MEM
+ RUN_START(__SVC_STACK_START)
+ RUN_END(__SVC_STACK_END)
+}
index 7c7af89d8735ce05b005c850d08b4c2e8c7b8a01..22399ceb4be472c80592ffb4dd97a328a5706751 100644 (file)
/* Memory Map */
MEMORY
{
- VECTORS (X) : origin=0x41C7F000 length=0x1000
+ VECTORS (X) : origin=0x70000000 length=0x1000
/* Reset Vectors base address(RESET_VECTORS) should be 64 bytes aligned */
- RESET_VECTORS (X) : origin=0x41C00000 length=0x100
- /* MCU0_R5F_0 local view */
- MCU0_R5F_TCMA_SBL_RSVD (X) : origin=0x0 length=0x100
- MCU0_R5F_TCMA (X) : origin=0x100 length=0x8000 - 0x100
- MCU0_R5F_TCMB0 (RWIX) : origin=0x41010000 length=0x8000
-
- /* MCU0_R5F_1 SoC view */
- MCU0_R5F1_ATCM (RWIX) : origin=0x41400000 length=0x8000
- MCU0_R5F1_BTCM (RWIX) : origin=0x41410000 length=0x8000
-
- /* MCU0 share locations */
- OCMRAM (RWIX) : origin=0x41C00100 length=0x80000 - 0x1100 /* ~510KB */
-
+ RESET_VECTORS (X) : origin=0x00000000 length=0x100
/* am64x MCMS3 locations */
- /* am64x Reserved Memory for ARM Trusted Firmware */
- MSMC3_ARM_FW (RWIX) : origin=0x70000000 length=0x40000 /* 256KB */
- MSMC3 (RWIX) : origin=0x70040000 length=0x7B0000 /* 8MB - 320KB */
- /* am64x Reserved Memory for DMSC Firmware */
- MSMC3_DMSC_FW (RWIX) : origin=0x707F0000 length=0x10000 /* 64KB */
+ MSMC3 (RWIX) : origin=0x70001000 length=0x170000-0x1000 /* ~(1.5MB - 0x1000) */
+
+ /* Reserved for SYSFW Secure Proxy */
+ MSMC3_H (RWIX) : origin=0x70170000 length=0x90000 /* ~0.5MB */
DDR0 (RWIX) : origin=0x80000000 length=0x80000000 /* 2GB */
}
/* a range of +\- 16 MB */
.intvecs : {} palign(8) > VECTORS
.intc_text : {} palign(8) > VECTORS
- .rstvectors : {} palign(8) > RESET_VECTORS
+ .rstvectors : {} palign(8) > RESET_VECTORS
.bootCode : {} palign(8) > MSMC3
.startupCode : {} palign(8) > MSMC3
.startupData : {} palign(8) > MSMC3, type = NOINIT
- .text : {} palign(8) > DDR0
- .const : {} palign(8) > DDR0
- .cinit : {} palign(8) > DDR0
- .pinit : {} palign(8) > DDR0
- .bss : {} align(4) > DDR0
- .far : {} align(4) > DDR0
- .data : {} palign(128) > DDR0
+ .text : {} palign(8) > MSMC3
+ .const : {} palign(8) > MSMC3
+ .cinit : {} palign(8) > MSMC3
+ .pinit : {} palign(8) > MSMC3
+ .bss : {} align(4) > MSMC3
+ .far : {} align(4) > MSMC3
+ .data : {} palign(128) > MSMC3
.boardcfg_data : {} palign(128) > MSMC3
- .sysmem : {} > DDR0
- .data_buffer : {} palign(128) > DDR0
+ .sysmem : {} > MSMC3
+ .data_buffer : {} palign(128) > MSMC3
/* USB or any other LLD buffer for benchmarking */
.benchmark_buffer (NOLOAD) {} ALIGN (8) > DDR0
- .stack : {} align(4) > DDR0 (HIGH)
- .irqStack : {. = . + __IRQ_STACK_SIZE;} align(4) > DDR0 (HIGH)
+ .stack : {} align(4) > MSMC3 (HIGH)
+ .irqStack : {. = . + __IRQ_STACK_SIZE;} align(4) > MSMC3 (HIGH)
RUN_START(__IRQ_STACK_START)
RUN_END(__IRQ_STACK_END)
- .fiqStack : {. = . + __FIQ_STACK_SIZE;} align(4) > DDR0 (HIGH)
+ .fiqStack : {. = . + __FIQ_STACK_SIZE;} align(4) > MSMC3 (HIGH)
RUN_START(__FIQ_STACK_START)
RUN_END(__FIQ_STACK_END)
- .abortStack : {. = . + __ABORT_STACK_SIZE;} align(4) > DDR0 (HIGH)
+ .abortStack : {. = . + __ABORT_STACK_SIZE;} align(4) > MSMC3 (HIGH)
RUN_START(__ABORT_STACK_START)
RUN_END(__ABORT_STACK_END)
- .undStack : {. = . + __UND_STACK_SIZE;} align(4) > DDR0 (HIGH)
+ .undStack : {. = . + __UND_STACK_SIZE;} align(4) > MSMC3 (HIGH)
RUN_START(__UND_STACK_START)
RUN_END(__UND_STACK_END)
- .svcStack : {. = . + __SVC_STACK_SIZE;} align(4) > DDR0 (HIGH)
+ .svcStack : {. = . + __SVC_STACK_SIZE;} align(4) > MSMC3 (HIGH)
RUN_START(__SVC_STACK_START)
RUN_END(__SVC_STACK_END)
}
diff --git a/packages/ti/build/am64x/linker_r5_sysbios.lds b/packages/ti/build/am64x/linker_r5_sysbios.lds
index bc2b6e3b08d606f0f3ee01790bc158396ac06bfd..40c5ffdb7135aad10368439b65e531258cab1be2 100644 (file)
MEMORY
{
- R5F_TCMA_SBL_RSVD(X): ORIGIN = 0x00000000 , LENGTH = 0x100
- RESET_VECTORS(X) : ORIGIN = 0x41c40000 , LENGTH = 0x100 /* Bottom 256 KB used by SBL */
+ /*R5F_TCMA_SBL_RSVD(X): ORIGIN = 0x00000000 , LENGTH = 0x100*/
+ RESET_VECTORS(X) : ORIGIN = 0x00000000 , LENGTH = 0x00008000
R5F_TCMB0(RWIX) : ORIGIN = 0x41010000 , LENGTH = 0x00008000
+ /* am64x MCMS3 locations */
+ MSMC3 (RWIX) : ORIGIN = 0x70000000 , LENGTH = 0x170000 /* ~1.5MB */
+ /* Reserved for SYSFW Secure Proxy */
+ MSMC3_H (RWIX) : ORIGIN = 0x70170000 , LENGTH = 0x90000 /* ~0.5MB */
DDR0 (RWIX) : ORIGIN = 0x80000000 , LENGTH = 0x80000000
}
index c0869a750ac022d2f3cda3a6219ddbf1cb17aea1..d8fac078bce36be6c8035e1acfd1da97347f05e9 100644 (file)
Main.common$.diags_INFO = Diags.ALWAYS_ON;
BIOS.libType = BIOS.LibType_Custom;
-BIOS.cpuFreq.lo = 2000000000;
+BIOS.cpuFreq.lo = 1000000000;
BIOS.cpuFreq.hi = 0;
var Timer = xdc.useModule('ti.sysbios.family.arm.v8a.Timer');
index a45f0cbd8f8e802d9093c9df235bcce99389df0d..c271aa33dde839b89c203a45aaad53db05b8fb1a 100644 (file)
var GateSwi = xdc.useModule('ti.sysbios.gates.GateSwi');
var BIOS = xdc.useModule('ti.sysbios.BIOS');
-var Hwi = xdc.useModule('ti.sysbios.family.arm.v7r.keystone3.Hwi');
var Core = xdc.useModule('ti.sysbios.family.arm.v7r.keystone3.Core');
var HeapMem = xdc.useModule('ti.sysbios.heaps.HeapMem');
var SysMin = xdc.useModule('xdc.runtime.SysMin');
Main.common$.diags_INFO = Diags.ALWAYS_ON;
BIOS.libType = BIOS.LibType_Custom;
-BIOS.cpuFreq.lo = 1000000000;
+BIOS.cpuFreq.lo = 800000000;
BIOS.cpuFreq.hi = 0;
var coreId = java.lang.System.getenv("CORE");
{
Core.id = 0;
/* DM timer cfg */
- Clock.timerId = 1;
+ Clock.timerId = 0;
}
if(coreId=="mcu1_1")
{
Core.id = 1;
/* DM timer cfg */
- Clock.timerId = 2;
-}
-if(coreId=="mcu2_0")
-{
- Core.id = 0;
- Clock.timerId = 0;
- /* DMTimer #12 - in general, address is 0x024x0000 where x is timer # */
- DMTimer.timerSettings[0].baseAddr = 0x024c0000;
- DMTimer.timerSettings[0].intNum = 168;
-}
-if(coreId=="mcu2_1")
-{
- Core.id = 1;
Clock.timerId = 1;
- /* DMTimer #13 - in general, address is 0x024x0000 where x is timer # */
- DMTimer.timerSettings[1].baseAddr = 0x024d0000;
- DMTimer.timerSettings[1].intNum = 169;
}
-if(coreId=="mcu3_0")
+if(coreId=="mcu2_0")
{
Core.id = 0;
Clock.timerId = 2;
- /* DMTimer #14 - in general, address is 0x024x0000 where x is timer # */
- DMTimer.timerSettings[2].baseAddr = 0x024e0000;
- DMTimer.timerSettings[2].intNum = 170;
}
-if(coreId=="mcu3_1")
+if(coreId=="mcu2_1")
{
Core.id = 1;
Clock.timerId = 3;
- /* DMTimer #15 - in general, address is 0x024x0000 where x is timer # */
- DMTimer.timerSettings[3].baseAddr = 0x024f0000;
- DMTimer.timerSettings[3].intNum = 171;
-}
-
-/* Set base address of Vector Interrupt Manager */
-if((coreId=="mcu2_0") || (coreId=="mcu2_1") || (coreId=="mcu3_0") || (coreId=="mcu3_1"))
-{
- var Hwi = xdc.useModule('ti.sysbios.family.arm.v7r.keystone3.Hwi');
- Hwi.vimBaseAddress = 0x0ff80000;
}
/*
diff --git a/packages/ti/build/am64x/sysbios_smp_a53.cfg b/packages/ti/build/am64x/sysbios_smp_a53.cfg
--- /dev/null
@@ -0,0 +1,183 @@
+
+/* =============================================================================
+ * Copyright (c) Texas Instruments Incorporated 2020
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+var Defaults = xdc.useModule('xdc.runtime.Defaults');
+var Diags = xdc.useModule('xdc.runtime.Diags');
+var Error = xdc.useModule('xdc.runtime.Error');
+var Log = xdc.useModule('xdc.runtime.Log');
+var LoggerBuf = xdc.useModule('ti.sysbios.smp.LoggerBuf');
+var Main = xdc.useModule('xdc.runtime.Main');
+var Memory = xdc.useModule('xdc.runtime.Memory');
+var System = xdc.useModule('xdc.runtime.System');
+var Text = xdc.useModule('xdc.runtime.Text');
+var Clock = xdc.useModule('ti.sysbios.knl.Clock');
+var Task = xdc.useModule('ti.sysbios.knl.Task');
+var Semaphore = xdc.useModule('ti.sysbios.knl.Semaphore');
+var HeapBuf = xdc.useModule('ti.sysbios.heaps.HeapBuf');
+var GateSwi = xdc.useModule('ti.sysbios.gates.GateSwi');
+
+var BIOS = xdc.useModule('ti.sysbios.BIOS');
+var Hwi = xdc.useModule('ti.sysbios.hal.Hwi');
+var HeapMem = xdc.useModule('ti.sysbios.heaps.HeapMem');
+var SysMin = xdc.useModule('ti.sysbios.smp.SysMin');
+var Core = xdc.useModule('ti.sysbios.family.arm.v8a.smp.Core');
+
+var Mmu = xdc.useModule('ti.sysbios.family.arm.v8a.Mmu');
+Mmu.initFunc = "&InitMmu";
+Mmu.tableArrayLen = 24;
+
+/*Enabling BIOS SMP mode */
+BIOS.smpEnabled = true;
+
+/* Enable cache */
+var Cache = xdc.module("ti.sysbios.hal.Cache");
+
+/*
+ * Direct CIO to UART
+ */
+/* System.SupportProxy = SysUart; */
+System.SupportProxy = SysMin;
+
+System.extendedFormats += "%f";
+/*
+ * Program.argSize sets the size of the .args section.
+ * The examples don't use command line args so argSize is set to 0.
+ */
+Program.argSize = 0x0;
+
+
+/* System stack size (used by ISRs and Swis) */
+Program.stack = 0x4000;
+
+Task.defaultStackSize = 0x4000;
+
+/*
+ * Uncomment this line to globally disable Asserts.
+ * All modules inherit the default from the 'Defaults' module. You
+ * can override these defaults on a per-module basis using Module.common$.
+ * Disabling Asserts will save code space and improve runtime performance.
+Defaults.common$.diags_ASSERT = Diags.ALWAYS_OFF;
+ */
+
+/*
+ * Uncomment this line to keep module names from being loaded on the target.
+ * The module name strings are placed in the .const section. Setting this
+ * parameter to false will save space in the .const section. Error and
+ * Assert messages will contain an "unknown module" prefix instead
+ * of the actual module name.
+Defaults.common$.namedModule = false;
+ */
+
+/* Create default heap and hook it into Memory */
+var heapMemParams = new HeapMem.Params;
+heapMemParams.size = 16384*18;
+var heap0 = HeapMem.create(heapMemParams);
+
+Memory.defaultHeapInstance = heap0;
+
+/*
+ * Minimize exit handler array in System. The System module includes
+ * an array of functions that are registered with System_atexit() to be
+ * called by System_exit().
+ */
+System.maxAtexitHandlers = 4;
+
+/*
+ * Uncomment this line to disable the Error print function.
+ * We lose error information when this is disabled since the errors are
+ * not printed. Disabling the raiseHook will save some code space if
+ * your app is not using System_printf() since the Error_print() function
+ * calls System_printf().
+Error.raiseHook = null;
+ */
+
+/*
+ * Uncomment this line to keep Error, Assert, and Log strings from being
+ * loaded on the target. These strings are placed in the .const section.
+ * Setting this parameter to false will save space in the .const section.
+ * Error, Assert and Log message will print raw ids and args instead of
+ * a formatted message.
+Text.isLoaded = false;
+ */
+
+/*
+ * Uncomment this line to disable the output of characters by SysMin
+ * when the program exits. SysMin writes characters to a circular buffer.
+ * This buffer can be viewed using the SysMin Output view in ROV.
+SysMin.flushAtExit = false;
+ */
+
+/*
+ * Create and install logger for the whole system
+ */
+var loggerBufParams = new LoggerBuf.Params();
+loggerBufParams.numEntries = 32;
+var logger0 = LoggerBuf.create(loggerBufParams);
+Defaults.common$.logger = logger0;
+Main.common$.diags_INFO = Diags.ALWAYS_ON;
+
+BIOS.libType = BIOS.LibType_Custom;
+BIOS.cpuFreq.lo = 2000000000;
+BIOS.cpuFreq.hi = 0;
+
+/* System stack size (used by ISRs and Swis) */
+Program.stack = 0x10000;
+
+Task.defaultStackSize = 0x4000;
+
+var Timer = xdc.useModule('ti.sysbios.family.arm.v8a.Timer');
+Timer.intFreq.lo = 250000000;
+Timer.intFreq.hi = 0;
+
+var DMTimer = xdc.useModule('ti.sysbios.timers.dmtimer.Timer');
+DMTimer.checkFrequency = false;
+for (var i=0; i < DMTimer.numTimerDevices; i++) {
+ DMTimer.intFreqs[i].lo = 19200000;
+ DMTimer.intFreqs[i].hi = 0;
+}
+
+var Load = xdc.useModule('ti.sysbios.utils.Load');
+
+/* load calculation related settings */
+Load.swiEnabled = true;
+Load.hwiEnabled = true;
+Load.taskEnabled = true;
+Load.updateInIdle = false;
+
+/* Check if application needs to update with custom configuration options */
+/* Caution: This should be at the end of this file after all other common cfg */
+var cfgUpdate = java.lang.System.getenv("XDC_CFG_UPDATE");
+if ((cfgUpdate != '')&&(cfgUpdate != null))
+{
+ xdc.print("Loading configuration update " + cfgUpdate);
+ xdc.loadCapsule(cfgUpdate);
+}
index 9f58671eefafd7a16d7a4a7c1733dc82059c21ee..2064c8b0e3e4f7904b8956d19e73c7a267809b00 100755 (executable)
ifeq ($(LIMIT_BOARDS),)
BOARD_LIST_ALL = evmDRA72x evmDRA75x evmDRA78x evmAM572x idkAM572x idkAM571x idkAM574x
BOARD_LIST_ALL += $(BOARD_LIST_J6_TDA)
-BOARD_LIST_ALL += am65xx_sim
BOARD_LIST_ALL += $(BOARD_LIST_J7_TDA)
BOARD_LIST_ALL += $(BOARD_LIST_TPR12)
+BOARD_LIST_ALL += am64x_evm
else
# If LIMIT_BOARDS is defined use it
BOARD_LIST_ALL = $(LIMIT_BOARDS)
ifeq ($(BOARD),$(filter $(BOARD), tpr12_evm))
CORE_LIST_ALL = $(CORE_LIST_tpr12)
endif
+ifeq ($(BOARD),$(filter $(BOARD), am64x_evm))
+ CORE_LIST_ALL = $(CORE_LIST_am64x)
+endif
else
# If LIMIT_CORES is defined use it
CORE_LIST_ALL = $(LIMIT_CORES)
diff --git a/packages/ti/build/makerules/build_config.mk b/packages/ti/build/makerules/build_config.mk
index a81efeeb86d5a80c88b366fc51f23710eb1ac86c..66343cbd411430b3afed91f102a98d8a589d73c8 100644 (file)
#
# MCU Cores
-ifeq ($(CORE),$(filter $(CORE), mcu1_0 mcu1_1 mcu2_0 mcu2_1 mcu3_0 mcu3_1))
+ifeq ($(CORE),$(filter $(CORE), mcu1_0 mcu1_1 mcu2_0 mcu2_1 mcu3_0 mcu3_1 m4f_0))
CFLAGS_GLOBAL_$(CORE) = -g -ms -DMAKEFILE_BUILD
LNKFLAGS_GLOBAL_$(CORE) = -x --zero_init=on
endif
CFLAGS_GLOBAL_ipu1_0 = -g -ms -DMAKEFILE_BUILD
LNKFLAGS_GLOBAL_ipu1_0 = -x --zero_init=on
+# m4f_0 - Cortex M4F
+CFLAGS_GLOBAL_m4f_0 = -g -ms -DMAKEFILE_BUILD
+LNKFLAGS_GLOBAL_m4f_0 = -x --zero_init=on
+
# ipu1_1 - Benneli - Core 0 (Cortex-M4)
CFLAGS_GLOBAL_ipu1_1 = -g -ms -DMAKEFILE_BUILD
LNKFLAGS_GLOBAL_ipu1_1 = -x --zero_init=on
index 2bebc9b644f603e36cd5ce9d6c6055363c0bfc41..8376458f832f4d04d0ed174715c5a81a6491abb6 100644 (file)
# Include make paths and options for all supported targets/boards
#
-.PHONY : all clean gendirs c7x_1 c66x c66xdsp_1 c66xdsp_2 ipu1_0 ipu1_1 ipu2_0 ipu2_1 m3 host a15_0 a8host a9host arp32_1 arp32_2 arp32_3 arp32_4 arm9_0 c674x mcu1_0 mcu1_1 mcu2_0 mcu2_1 mcu3_0 mcu3_1 mpu1_0 mpu1_1 mpu2_0 mpu2_1 c7x-hostemu qnx_mpu1_0 clean_appimagerprc sbl_appimagerprc
+.PHONY : all clean gendirs c7x_1 c66x c66xdsp_1 c66xdsp_2 ipu1_0 ipu1_1 ipu2_0 ipu2_1 m3 host a15_0 a8host a9host arp32_1 arp32_2 arp32_3 arp32_4 arm9_0 c674x mcu1_0 mcu1_1 mcu2_0 mcu2_1 mcu3_0 mcu3_1 mpu1_0 mpu1_1 mpu2_0 mpu2_1 c7x-hostemu qnx_mpu1_0 m4f_0 clean_appimagerprc sbl_appimagerprc
+
all : $(CORE)
# Define directories that are going to be created as a part of build process
index 93a90f7ce04d65d4cab11908d3a7e5a1449724e5..d4dc57d47520262978de7dc247fcd00749cde484 100644 (file)
PDK_LNKFLAGS += --define=QNX_OS --define=BUILD_MPU1_0
endif
+ifeq ($(CORE),$(filter $(CORE), m4f_0))
+ PDK_CFLAGS += -DBUILD_M4F_0 -DBUILD_M4F
+ PDK_LNKFLAGS += --define=BUILD_M4F_0 --define=BUILD_M4F
+endif
+
export PDK_CFLAGS
export PDK_LNKFLAGS
index 023f27421c0ab72bbaf155b591c79a92e8c69295..368bcad5a16c057e7737d5053afff03143225170 100644 (file)
CONFIG_BLD_LNK_a53 = $(pdk_PATH)/ti/build/$(SOC)/linker_a53.lds
endif
endif
+ ifeq ($(SOC),$(filter $(SOC), am64x))
+ ifeq ($(CONFIG_BLD_XDC_m4f),)
+ CONFIG_BLD_LNK_m4f = $(pdk_PATH)/ti/build/$(SOC)/linker_m4f.lds
+ endif
+ endif
ifeq ($(SOC),$(filter $(SOC), j721e am77x j7200))
ifeq ($(CONFIG_BLD_XDC_a72),)
CONFIG_BLD_LNK_a72 = $(pdk_PATH)/ti/build/$(SOC)/linker_a72_mpu1_0.lds
endif
ifeq ($(SOC),$(filter $(SOC), am65xx am64x))
ifeq ($(CONFIG_BLD_XDC_a53),)
- CONFIG_BLD_XDC_a53 = $(pdk_PATH)/ti/build/am65xx/config_$(SOC)_a53.bld
- CONFIG_BLD_LNK_a53 = $(pdk_PATH)/ti/build/am65xx/linker_a53.lds
+ CONFIG_BLD_XDC_a53 = $(pdk_PATH)/ti/build/$(SOC)/config_$(SOC)_a53.bld
+ CONFIG_BLD_LNK_a53 = $(pdk_PATH)/ti/build/$(SOC)/linker_a53.lds
endif
endif
index f15fe234b95c3e10a9e9c167e1397bcf39bd2007..9f57a1ebc0e9625d78f0300f49af5dd1c33976bb 100644 (file)
# AM64X
ifeq ($(BOARD),$(filter $(BOARD), am64x_evm))
SOC = am64x
- SBL_RUN_ADDRESS=0x41C00100
+ SBL_RUN_ADDRESS=0x70000100
SBL_DEV_ID=55
endif
ARCH = armv7m
endif
+# m4f single core
+ifeq ($(CORE),$(filter $(CORE), m4f_0))
+ ISA = m4f
+ ISA_EXT = m4f
+ ARCH = armv7m
+endif
+
# m3
ifeq ($(CORE),$(filter $(CORE), m3))
ISA = m3
ifeq ($(CORE),$(filter $(CORE), mcu1_0 mcu1_1 mcu2_0 mcu2_1 mcu3_0 mcu3_1))
ISA = r5f
ISA_EXT = r5f
- ARCH = armv7m
+ ARCH = armv7r
endif
# MPU
ASMEXT = s$(FORMAT_EXT)$(ISA_EXT)$(ENDIAN_EXT)
endif
-ifeq ($(ISA),m4)
+ifeq ($(ISA),$(filter $(ISA), m4 m4f))
ifeq ($(FORMAT),ELF)
TARGET_XDC = ti.targets.arm.elf.M4
FORMAT_EXT = e
PLATFORM_XDC = "ti.platforms.evmTDA3XX:IPU_1_1"
endif
endif
+
+ ifeq ($(BOARD),$(filter $(SOC), am64x_evm))
+ PLATFORM_XDC = "ti.platforms.cortexM:AM64X_M4F"
+ endif
endif
# If ENDIAN is set to "big", set ENDIAN_EXT to "e", that would be used in
endif
ifeq ($(BOARD),$(filter $(BOARD), am64x_evm))
- ifeq ($(CORE),$(filter $(CORE), mcu1_0 mcu1_1))
- PLATFORM_XDC = "ti.platforms.cortexR:AM64X_MCU"
- else
- PLATFORM_XDC = "ti.platforms.cortexR:AM64X_MAIN"
- endif
+ PLATFORM_XDC = "ti.platforms.cortexR:AM64X"
endif
ifeq ($(SOC),$(filter $(SOC), tpr12))
PLATFORM_XDC = "ti.platforms.cortexA:SIMMAXWELL"
endif
+ ifeq ($(BOARD),$(filter $(BOARD), am64x_evm))
+ PLATFORM_XDC = "ti.platforms.cortexA:AM64X"
+ endif
+
ENDIAN_EXT = fg
FORMAT_EXT =
PLATFORM_XDC = "ti.platforms.cortexA:J7200"
endif
- ifeq ($(BOARD),$(filter $(BOARD), am64x_evm))
- PLATFORM_XDC = "ti.platforms.cortexA:AM64X"
- endif
-
ENDIAN_EXT = fg
FORMAT_EXT =
diff --git a/packages/ti/build/makerules/rules_m4f.mk b/packages/ti/build/makerules/rules_m4f.mk
--- /dev/null
@@ -0,0 +1,17 @@
+# Filename: rules_m4f.mk
+#
+# Make rules for M4F - This file has all the common rules and defines required
+# for M4F ISA
+#
+# This file needs to change when:
+# 1. Code generation tool chain changes (currently it uses TMS470)
+# 2. Internal switches (which are normally not touched) has to change
+# 3. XDC specific switches change
+# 4. a rule common for R5F ISA has to be added or modified
+
+CGT_ISA = M4F
+CGT_EXT = m4f
+CGT_PATH = $(TOOLCHAIN_PATH_M4)
+include $(MAKERULEDIR)/rules_ti_cgt_arm.mk
+
+# Nothing beyond this point
diff --git a/packages/ti/build/makerules/rules_ti_cgt_arm.mk b/packages/ti/build/makerules/rules_ti_cgt_arm.mk
# 4. a rule common for M4/R5F ISA has to be added or modified
# Set compiler/archiver/linker commands and include paths
-CODEGEN_INCLUDE = $(TOOLCHAIN_PATH_$(CGT_ISA))/include
-CC = $(TOOLCHAIN_PATH_$(CGT_ISA))/bin/armcl
-AR = $(TOOLCHAIN_PATH_$(CGT_ISA))/bin/armar
-LNK = $(TOOLCHAIN_PATH_$(CGT_ISA))/bin/armcl
-STRP = $(TOOLCHAIN_PATH_$(CGT_ISA))/bin/armstrip
-SIZE = $(TOOLCHAIN_PATH_$(CGT_ISA))/bin/armofd
+ifeq ($(CGT_ISA),$(filter $(CGT_ISA), M4F))
+CGT_ISA_PATH_PRFX = M4
+else
+CGT_ISA_PATH_PRFX = $(CGT_ISA)
+endif
+
+CODEGEN_INCLUDE = $(TOOLCHAIN_PATH_$(CGT_ISA_PATH_PRFX))/include
+CC = $(TOOLCHAIN_PATH_$(CGT_ISA_PATH_PRFX))/bin/armcl
+AR = $(TOOLCHAIN_PATH_$(CGT_ISA_PATH_PRFX))/bin/armar
+LNK = $(TOOLCHAIN_PATH_$(CGT_ISA_PATH_PRFX))/bin/armcl
+STRP = $(TOOLCHAIN_PATH_$(CGT_ISA_PATH_PRFX))/bin/armstrip
+SIZE = $(TOOLCHAIN_PATH_$(CGT_ISA_PATH_PRFX))/bin/armofd
# Derive a part of RTS Library name based on ENDIAN: little/big
ifeq ($(ENDIAN),little)
else ifeq ($(CGT_ISA), Arm9)
CFLAGS_INTERNAL = -c -qq -pdsw225 --endian=$(ENDIAN) -mv5e --float_support=vfplib --abi=$(CSWITCH_FORMAT) -eo.$(OBJEXT) -ea.$(ASMEXT) --symdebug:dwarf --embed_inline_assembly
endif
+
+# Reset the CFLAGS_INTERNAL flag for M4F
+ifeq ($(CGT_ISA), M4F)
+ CFLAGS_INTERNAL = -c -qq -pdsw225 --endian=$(ENDIAN) -mv7M4 --abi=$(CSWITCH_FORMAT) -eo.$(OBJEXT) -ea.$(ASMEXT) --symdebug:dwarf --embed_inline_assembly
+ CFLAGS_INTERNAL += --float_support=FPv4SPD16
+endif
+
ifeq ($(TREAT_WARNINGS_AS_ERROR), yes)
CFLAGS_INTERNAL += --emit_warnings_as_errors
LNKFLAGS_INTERNAL_COMMON += --emit_warnings_as_errors
EXTERNAL_LNKCMD_FILE = $(EXTERNAL_LNKCMD_FILE_LOCAL)
else
EXTERNAL_LNKCMD_FILE = $(CONFIG_BLD_LNK_r5f)
- endif
-
+ endif
else
XDC_TARGET_NAME=$(CGT_ISA)
endif
+# Reset the XDC_TARGET_NAME for M4F
+ifeq ($(CGT_ISA),$(filter $(CGT_ISA),M4F))
+ XDC_TARGET_NAME=M4
+
+ ifneq ($(EXTERNAL_LNKCMD_FILE_LOCAL),)
+ EXTERNAL_LNKCMD_FILE = $(EXTERNAL_LNKCMD_FILE_LOCAL)
+ else
+ EXTERNAL_LNKCMD_FILE = $(CONFIG_BLD_LNK_m4f)
+ endif
+endif
+
XDC_HFILE_NAME = $(basename $(notdir $(XDC_CFG_FILE_$(CORE))))
ifneq ($(PEXT_BIOS),)
CFLAGS_XDCINTERNAL += -Dxdc_cfg__header__='$(CONFIGURO_DIR)/package/cfg/$(XDC_HFILE_NAME)_$(XDC_HFILE_EXT).h'
endif
endif
+ ifeq ($(CGT_ISA),$(filter $(CGT_ISA), M4F))
+ # LNKFLAGS_INTERNAL_BUILD_PROFILE = --opt='--float_support=FPv4SPD16 --endian=$(ENDIAN) -mv7M4 --abi=$(CSWITCH_FORMAT) -qq -pdsw225 $(CFLAGS_GLOBAL_$(CORE)) -oe --symdebug:dwarf -ms -op2 -O3 -os --optimize_with_debug --inline_recursion_limit=20 --diag_suppress=23000' --strict_compatibility=on
+ LNKFLAGS_INTERNAL_BUILD_PROFILE = -qq --diag_warning=225 --diag_suppress=23000 $(LNKFLAGS_GLOBAL_$(CORE))
+ CFLAGS_INTERNAL += -ms -oe -O3 -op0 -os --optimize_with_debug --inline_recursion_limit=20
+ endif
endif
# Assemble CFLAGS from all other CFLAGS definitions
LNKFLAGS_INTERNAL_COMMON += -mv7R5
#--diag_suppress=10063 supresses 'warning: entry point other than _c_int00 specified'
LNKFLAGS_INTERNAL_COMMON += --diag_suppress=10063
+else
+ifeq ($(CGT_ISA), M4F)
+ LNKFLAGS_INTERNAL_COMMON +=
+else
+ifeq ($(CGT_ISA), Arm9)
+ LNKFLAGS_INTERNAL_COMMON +=
+else
+ LNKFLAGS_INTERNAL_COMMON += --silicon_version=7$(CGT_ISA)
+endif
+endif
endif
# Assemble Linker flags from all other LNKFLAGS definitions
index 9802fdb8524cb9b750efc36997708aa54a083c15..6165110040ab286f8224d08c8941e2a4c1b7fef7 100644 (file)
CG_XML_VERSION=2.61.00
#Component versions for non-TDA builds
+ BIOS_VERSION=6_76_03_01
+ XDC_VERSION=3_55_02_22_core
+ CGT_VERSION=8.3.2
ifeq ($(BOARD),$(filter $(BOARD), tpr12_evm))
BIOS_VERSION=6_82_00_16
XDC_VERSION=3_61_00_16_core
CGT_VERSION=8.3.3
-else
- BIOS_VERSION=6_76_03_01
- XDC_VERSION=3_55_02_22_core
- CGT_VERSION=8.3.2
+endif
+ifeq ($(BOARD),$(filter $(BOARD), am64x_evm))
+ BIOS_VERSION=6_83_00_01_eng
+ XDC_VERSION=3_61_00_16_core
endif
EDMA_VERSION=2_12_05_30E
index e7cd4d85ff9676ce9f092225e42bd71a98cf2a27..343e3aa18d39e2c1e499b101b4dd9449f02984f9 100644 (file)
include $(PDK_INSTALL_PATH)/ti/build/soc_info.mk
# Below are the supported PDK_SOCs in Processor SDK
-export PROCSDK_SUPPORTED_PDK_SOCS = am335x am437x am437x-hs am57xx omapl137 omapl138 k2hk k2e k2l k2g k2g-hs c665x c667x am65xx am65xx-hs j7 tpr12
+export PROCSDK_SUPPORTED_PDK_SOCS = am335x am437x am437x-hs am57xx omapl137 omapl138 k2hk k2e k2l k2g k2g-hs c665x c667x am65xx am65xx-hs j7 am64x tpr12
#if PDK_SOC is specified , derive LIMIT_SOCS/LIMIT_BOARDS/LIMIT_CORES from it (if not specified explicitly)
ifneq ($(PDK_SOC),)
LIMIT_CORES_c667x = $(CORE_LIST_c6678)
LIMIT_CORES_am65xx = $(CORE_LIST_am65xx)
LIMIT_CORES_am65xx-hs = $(CORE_LIST_am65xx)
+LIMIT_CORES_am64x = $(CORE_LIST_am64x)
LIMIT_CORES_tpr12 = $(CORE_LIST_tpr12)
# Filter out c7x-hostemu as Processor SDK does not build use it
LIMIT_CORES_j7 = $(filter-out c7x-hostemu,$(sort $(CORE_LIST_j721e) $(CORE_LIST_j7200)))
LIMIT_SOCS_am335x = am335x
LIMIT_SOCS_am65xx = am65xx
LIMIT_SOCS_am65xx-hs = am65xx
+LIMIT_SOCS_am64x = am64x
LIMIT_SOCS_j7 = j721e j7200
LIMIT_SOCS_tpr12 = tpr12
LIMIT_SOCS_omapl137 = omapl137
LIMIT_BOARDS_k2e = $(BOARD_LIST_k2e)
LIMIT_BOARDS_am65xx = $(BOARD_LIST_am65xx)
LIMIT_BOARDS_am65xx-hs = $(BOARD_LIST_am65xx)
+LIMIT_BOARDS_am64x = $(BOARD_LIST_am64x)
LIMIT_BOARDS_c665x = $(BOARD_LIST_c6657)
LIMIT_BOARDS_c667x = $(BOARD_LIST_c6678)
LIMIT_BOARDS_omapl138 = $(BOARD_LIST_omapl138)
index 4f6a1839a2e64b7b8aa3e7317c5f758766da0b2b..108774be649c023a5acb2872a6673541e05eb9d3 100644 (file)
BOARD_LIST_omapl137 = evmOMAPL137
BOARD_LIST_omapl138 = lcdkOMAPL138
BOARD_LIST_am65xx = am65xx_evm am65xx_idk
+BOARD_LIST_am64x = am64x_evm
BOARD_LIST_j721e = j721e_evm
BOARD_LIST_j7200 = j7200_evm
BOARD_LIST_tpr12 = tpr12_evm
CORE_LIST_am65xx = mpu1_0 mcu1_0 mcu1_1 mpu1_1 mpu2_0 mpu2_1
CORE_LIST_j721e = mpu1_0 mcu1_0 mcu1_1 mcu2_0 mcu2_1 mcu3_0 mcu3_1 c66xdsp_1 c66xdsp_2 c7x_1 mpu1_1
CORE_LIST_j7200 = mpu1_0 mcu1_0 mcu1_1 mcu2_0 mcu2_1 mpu1_1
-CORE_LIST_am64x = mpu1_0 mcu1_0 mcu1_1 mcu2_0 mcu2_1 ipu1_0
+CORE_LIST_am64x = mpu1_0 mcu1_0 mcu1_1 mcu2_0 mcu2_1 m4f_0
CORE_LIST_k3_CORELIST = m3
CORE_LIST_PRU = pru_0 pru_1
CORE_LIST_tpr12 = mcu1_0 c66xdsp_1
diff --git a/packages/ti/drv/gpio/src/src_files_common.mk b/packages/ti/drv/gpio/src/src_files_common.mk
index 3f14032198505cddcf84a5bd3c9daf39475585e7..f83241e1c991eb81a7d0178a8606330af24930f8 100644 (file)
-SOC_DEP_LIB_SOCS=k2h k2hk k2l k2e k2g c6678 c6657 omapl137 omapl138 am65xx j721e am77x j7200
+SOC_DEP_LIB_SOCS=k2h k2hk k2l k2e k2g c6678 c6657 omapl137 omapl138 am65xx j721e am77x j7200 am64x
# Common source files across all platforms and cores
ifeq ($(SOC),$(filter $(SOC),$(SOC_DEP_LIB_SOCS) ))
index c7e84812ad30575f70d65dda72b3c9f25883b765..98b908fa696e933d1d04d58ad16f06f6dbf45483 100644 (file)
include $(PDK_I2C_COMP_PATH)/src/src_files_common.mk
-ifeq ($(SOC),$(filter $(SOC), tda2xx tda2px dra72x dra75x tda2ex am571x am572x am574x tda3xx dra78x k2h k2k k2l k2e k2g c6678 c6657 am437x am335x omapl137 omapl138 am65xx j721e j7200))
+ifeq ($(SOC),$(filter $(SOC), tda2xx tda2px dra72x dra75x tda2ex am571x am572x am574x tda3xx dra78x k2h k2k k2l k2e k2g c6678 c6657 am437x am335x omapl137 omapl138 am65xx j721e j7200 am64x))
SRCDIR += soc/$(SOC)
INCDIR += soc
# Common source files across all platforms and cores
# need to be included for this component
INCLUDE_EXTERNAL_INTERFACES = pdk
-ifeq ($(SOC),$(filter $(SOC), tda2xx tda2px dra72x dra75x tda2ex am571x am572x am574x tda3xx dra78x k2h k2k k2l k2e k2g c6678 c6657 am437x am335x omapl137 omapl138 j721e j7200))
+ifeq ($(SOC),$(filter $(SOC), tda2xx tda2px dra72x dra75x tda2ex am571x am572x am574x tda3xx dra78x k2h k2k k2l k2e k2g c6678 c6657 am437x am335x omapl137 omapl138 j721e j7200 am64x))
PACKAGE_SRCS_COMMON += soc/$(SOC) soc/I2C_soc.h
endif
diff --git a/packages/ti/drv/i2c/build/makefile_profile.mk b/packages/ti/drv/i2c/build/makefile_profile.mk
index f03ce0c9599aeeea5bb4d6d779cbabde1eca0a87..acab5a5f951b70196ced7a994c3100f89b061bac 100644 (file)
include $(PDK_I2C_COMP_PATH)/src/src_files_common.mk
-ifeq ($(SOC),$(filter $(SOC), tda2xx tda2px dra72x dra75x tda2ex am571x am572x am574x tda3xx k2h k2k k2l k2e k2g c6678 c6657 am437x am335x omapl137 omapl138 am65xx j721e j7200))
+ifeq ($(SOC),$(filter $(SOC), tda2xx tda2px dra72x dra75x tda2ex am571x am572x am574x tda3xx k2h k2k k2l k2e k2g c6678 c6657 am437x am335x omapl137 omapl138 am65xx j721e j7200 am64x))
SRCDIR += soc/$(SOC)
INCDIR += soc
# Common source files across all platforms and cores
# need to be included for this component
INCLUDE_EXTERNAL_INTERFACES = pdk
-ifeq ($(SOC),$(filter $(SOC), tda2xx tda2px dra72x dra75x tda2ex am571x am572x am574x tda3xx k2h k2k k2l k2e k2g c6678 c6657 am437x am335x omapl137 omapl138 am65xx j721e j7200))
+ifeq ($(SOC),$(filter $(SOC), tda2xx tda2px dra72x dra75x tda2ex am571x am572x am574x tda3xx k2h k2k k2l k2e k2g c6678 c6657 am437x am335x omapl137 omapl138 am65xx j721e j7200 am64x))
PACKAGE_SRCS_COMMON += soc/$(SOC) soc/I2C_soc.h
endif
index cc5052e17a2fbf84dd41bc66ca0e5702fce127eb..5e33529c48250a20b2198ea6da7d32f32d791ad1 100755 (executable)
#
ifeq ($(i2c_component_make_include), )
-drvi2c_BOARDLIST = am65xx_evm am65xx_idk j721e_sim j721e_evm j7200_evm
-drvi2c_BOARDLISTLIM = am65xx_evm am65xx_idk
-drvi2c_SOCLIST = am574x am572x am571x tda2xx tda2px tda2ex tda3xx dra78x dra72x dra75x k2h k2k k2l k2e k2g c6678 c6657 am437x am335x omapl137 omapl138 am65xx j721e j7200
-drvi2c_SOCLISTLIM = am574x am572x am571x tda2xx tda2px tda2ex tda3xx dra78x dra72x dra75x k2h k2k k2l k2e k2g c6678 c6657 am437x am335x omapl137 omapl138 am65xx
+drvi2c_BOARDLIST = am65xx_evm am65xx_idk j721e_sim j721e_evm j7200_evm am64x_evm
+drvi2c_BOARDLISTLIM = am65xx_evm am65xx_idk am64x_evm
+drvi2c_SOCLIST = am574x am572x am571x tda2xx tda2px tda2ex tda3xx dra78x dra72x dra75x k2h k2k k2l k2e k2g c6678 c6657 am437x am335x omapl137 omapl138 am65xx j721e j7200 am64x
+drvi2c_SOCLISTLIM = am574x am572x am571x tda2xx tda2px tda2ex tda3xx dra78x dra72x dra75x k2h k2k k2l k2e k2g c6678 c6657 am437x am335x omapl137 omapl138 am65xx am64x
drvi2c_tda2xx_CORELIST = ipu1_0
drvi2c_tda2px_CORELIST = ipu1_0
drvi2c_tda2ex_CORELIST = ipu1_0
drvi2c_am65xx_CORELIST = mpu1_0 mcu1_0 mcu1_1
drvi2c_j721e_CORELIST = $(DEFAULT_j721e_CORELIST)
drvi2c_j721e_CORELISTARM = mpu1_0 mcu1_0 mcu1_1 mcu2_0 mcu2_1 mcu3_0 mcu3_1
-drvi2c_j7200_CORELIST = mpu1_0 mcu1_0 mcu1_1 mcu2_0 mcu2_1
+drvi2c_j7200_CORELIST = mpu1_0 mcu1_0 mcu1_1 mcu2_0 mcu2_1
+drvi2c_am64x_CORELIST = mpu1_0 mcu1_0 mcu1_1 mcu2_0 mcu2_1 m4f_0
+
############################
# i2c package
# List of components included under i2c lib
# All the tests mentioned in list are built when test target is called
# List below all examples for allowed values
############################
+ifeq ($(SOC),$(filter $(SOC), am64x))
+i2c_EXAMPLE_LIST = I2C_Baremetal_Eeprom_TestApp
+else
i2c_EXAMPLE_LIST = drv_i2c_led_blink_test I2C_Baremetal_Eeprom_TestApp I2C_Eeprom_TestApp I2C_Eeprom_SMP_TestApp drv_i2c_utility
+endif
drvi2c_EXAMPLE_LIST = $(i2c_EXAMPLE_LIST)
#
export I2C_Eeprom_SMP_TestApp_MAKEFILE
I2C_Eeprom_SMP_TestApp_PKG_LIST = I2C_Eeprom_SMP_TestApp
I2C_Eeprom_SMP_TestApp_INCLUDE = $(I2C_Eeprom_SMP_TestApp_PATH)
-I2C_Eeprom_SMP_TestApp_BOARDLIST = $(drvi2c_BOARDLISTLIM)
+I2C_Eeprom_SMP_TestApp_BOARDLIST = am65xx_evm am65xx_idk j721e_evm
export I2C_Eeprom_SMP_TestApp_BOARDLIST
I2C_Eeprom_SMP_TestApp_$(SOC)_CORELIST = mpu1_0
export I2C_Eeprom_SMP_TestApp_$(SOC)_CORELIST
index dd3ac7b9243743a2bbf928cbd617e9dbc048aa0f..e8430a1576a1b5e1fa7b023e73c0edb9f43d86a3 100644 (file)
'c6747',
'am65xx',
'j721e',
- 'j7200'
+ 'j7200',
+ 'am64x'
];
/* Get the SOC */
index 9a2aa3dcbf0b72ca413789e2bdd46423af906089..3acb8b8b6c303b775809c6dbfd0c0d56b6471fea 100644 (file)
#elif defined(SOC_J721E) || defined(SOC_J7200)
#define I2C_HWIP_MAX_CNT (7U)
+#elif defined(SOC_AM64X)
+#define I2C_HWIP_MAX_CNT (6U)
+
#endif
/* I2C SoC HW IP level API */
extern int32_t I2C_socGetInitCfg(uint32_t index, I2C_HwAttrs *cfg);
diff --git a/packages/ti/drv/i2c/soc/am64x/I2C_soc.c b/packages/ti/drv/i2c/soc/am64x/I2C_soc.c
--- /dev/null
@@ -0,0 +1,274 @@
+/**
+ * \file am64x/I2C_soc.c
+ *
+ * \brief AM64X SoC specific I2C hardware attributes.
+ *
+ * This file contains the hardware attributes of I2C peripheral like
+ * base address, interrupt number etc.
+ */
+
+/*
+ * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include <ti/csl/soc/am64x/src/cslr_soc.h>
+#include <ti/drv/i2c/I2C.h>
+#include <ti/drv/i2c/soc/I2C_soc.h>
+
+/* I2C configuration structure */
+I2C_HwAttrs i2cInitCfg[I2C_HWIP_MAX_CNT] =
+{
+ {
+ /* I2C0 on the Main domain */
+ CSL_I2C0_CFG_BASE, /* baseAddr */
+#if defined (BUILD_MPU)
+ /* A53 cores on the Main domain */
+ CSLR_GICSS0_SPI_I2C0_POINTRPEND_0, /* intNum */
+#elif defined (BUILD_MCU)
+ /* R5 cores on the Main domain */
+ CSLR_R5FSS0_CORE0_INTR_I2C0_POINTRPEND_0,
+#else
+ /* M4 core on the MCU Channel */
+ 0U, /* TBD, no I2C9 interrupt routed to M4 core */
+#endif
+ 0, /* eventId */
+ 96000000,
+ true,
+ {
+ /* default own slave addresses */
+ 0x70, 0x0, 0x0, 0x0
+ },
+ },
+ {
+ /* I2C1 on the Main domain */
+ CSL_I2C1_CFG_BASE,
+#if defined (BUILD_MPU)
+ CSLR_GICSS0_SPI_I2C1_POINTRPEND_0,
+#elif defined (BUILD_MCU)
+ CSLR_R5FSS0_CORE0_INTR_I2C1_POINTRPEND_0,
+#else
+ 0U, /* TBD, no I2C1 interrupt routed to M4 core */
+#endif
+ 0,
+ 96000000,
+ true,
+ {
+ 0x71, 0x0, 0x0, 0x0
+ },
+ },
+ {
+ /* I2C2 on the Main domain */
+ CSL_I2C2_CFG_BASE,
+#if defined (BUILD_MPU)
+ CSLR_GICSS0_SPI_I2C2_POINTRPEND_0,
+#elif defined (BUILD_MCU)
+ CSLR_R5FSS0_CORE0_INTR_I2C2_POINTRPEND_0,
+#else
+ 0U, /* TBD, no I2C2 interrupt routed to M4 core */
+#endif
+ 0,
+ 96000000,
+ true,
+ {
+ 0x72, 0x0, 0x0, 0x0
+ },
+ },
+ {
+ /* I2C3 on the Main domain */
+ CSL_I2C3_CFG_BASE,
+#if defined (BUILD_MPU)
+ CSLR_GICSS0_SPI_I2C3_POINTRPEND_0,
+#elif defined (BUILD_MCU)
+ CSLR_R5FSS0_CORE0_INTR_I2C1_POINTRPEND_0,
+#else
+ 0U, /* TBD, no I2C1 interrupt routed to M4 core */
+#endif
+ 0,
+ 96000000,
+ true,
+ {
+ 0x73, 0x0, 0x0, 0x0
+ },
+ },
+ {
+ /* I2C0 on the MCU channel */
+ CSL_MCU_I2C0_CFG_BASE,
+#if defined (BUILD_MPU)
+ CSLR_GICSS0_SPI_MCU_I2C0_POINTRPEND_0,
+#elif defined (BUILD_MCU)
+ CSLR_R5FSS0_CORE0_INTR_MCU_I2C0_POINTRPEND_0,
+#else
+ CSLR_MCU_M4FSS0_CORE0_NVIC_MCU_I2C0_POINTRPEND_0,
+#endif
+ 0,
+ 96000000,
+ true,
+ {
+ 0x70, 0x0, 0x0, 0x0
+ },
+ },
+ {
+ /* I2C1 on the MCU channel */
+ CSL_MCU_I2C1_CFG_BASE,
+#if defined (BUILD_MPU)
+ CSLR_GICSS0_SPI_MCU_I2C1_POINTRPEND_0,
+#elif defined (BUILD_MCU)
+ CSLR_R5FSS0_CORE0_INTR_MCU_I2C1_POINTRPEND_0,
+#else
+ CSLR_MCU_M4FSS0_CORE0_NVIC_MCU_I2C1_POINTRPEND_0,
+#endif
+ 0,
+ 96000000,
+ true,
+ {
+ 0x70, 0x0, 0x0, 0x0
+ },
+ },
+};
+
+
+/* I2C objects */
+I2C_v1_Object I2cObjects[I2C_HWIP_MAX_CNT];
+
+
+/* I2C configuration structure */
+CSL_PUBLIC_CONST I2C_config_list I2C_config = {
+ {
+ &I2C_v1_FxnTable,
+ &I2cObjects[0],
+ &i2cInitCfg[0]
+ },
+
+ {
+ &I2C_v1_FxnTable,
+ &I2cObjects[1],
+ &i2cInitCfg[1]
+ },
+
+ {
+ &I2C_v1_FxnTable,
+ &I2cObjects[2],
+ &i2cInitCfg[2]
+ },
+
+ {
+ &I2C_v1_FxnTable,
+ &I2cObjects[3],
+ &i2cInitCfg[3]
+ },
+
+ {
+ &I2C_v1_FxnTable,
+ &I2cObjects[4],
+ &i2cInitCfg[4]
+ },
+
+ {
+ &I2C_v1_FxnTable,
+ &I2cObjects[5],
+ &i2cInitCfg[5]
+ },
+
+ {NULL, NULL, NULL},
+ {NULL, NULL, NULL},
+ {NULL, NULL, NULL},
+ {NULL, NULL, NULL},
+ {NULL, NULL, NULL},
+ {NULL, NULL, NULL},
+ {NULL, NULL, NULL},
+ {NULL, NULL, NULL}
+};
+
+/**
+ * \brief This API gets the SoC level of I2C intial configuration
+ *
+ * \param index I2C instance index.
+ * \param cfg Pointer to I2C SOC initial config.
+ *
+ * \return 0 success: -1: error
+ *
+ */
+int32_t I2C_socGetInitCfg(uint32_t index, I2C_HwAttrs *cfg)
+{
+ int32_t ret = 0;
+
+ if (index < I2C_HWIP_MAX_CNT)
+ {
+ *cfg = i2cInitCfg[index];
+ }
+ else
+ {
+ ret = (int32_t)(-1);
+ }
+
+ return ret;
+}
+
+/**
+ * \brief This API sets the SoC level of I2C intial configuration
+ *
+ * \param index I2C instance index.
+ * \param cfg Pointer to I2C SOC initial config.
+ *
+ * \return 0 success: -1: error
+ *
+ */
+int32_t I2C_socSetInitCfg(uint32_t index, const I2C_HwAttrs *cfg)
+{
+ int32_t ret = 0;
+
+ if (index < I2C_HWIP_MAX_CNT)
+ {
+ i2cInitCfg[index] = *cfg;
+ }
+ else
+ {
+ ret = (int32_t)(-1);
+ }
+
+ return ret;
+}
+
+#if defined (BUILD_MCU)
+/**
+ * \brief This API initializes the SoC level of I2C configuration
+ * based on the core and domain
+ *
+ * \param none
+ *
+ * \return none
+ *
+ */
+void I2C_socInit(void)
+{
+}
+#endif
diff --git a/packages/ti/drv/i2c/src/src_files_common.mk b/packages/ti/drv/i2c/src/src_files_common.mk
index 5fa2710a83989c243076c93d7e42f7be1cb79756..05cfad8cda4242d59da58347d11feebdc21e8c03 100644 (file)
PACKAGE_SRCS_COMMON += src/v1 soc/I2C_v1.h
# For all non-TDA devices, component contains all source files in library and package
-ifneq ($(SOC),$(filter $(SOC), tda2xx tda2px dra75x tda2ex tda3xx dra78x j721e j7200 am65xx))
+ifneq ($(SOC),$(filter $(SOC), tda2xx tda2px dra75x tda2ex tda3xx dra78x j721e j7200 am65xx am64x))
SRCDIR += src/v0
INCDIR += src/v0
SRCS_COMMON += I2C_v0.c
diff --git a/packages/ti/drv/i2c/test/eeprom_read/src/main_test.c b/packages/ti/drv/i2c/test/eeprom_read/src/main_test.c
index e4ea7f8d0eebe691ab64a42f4cc49150a58a00a7..70f5df968a9de2135d59f5a60e9b94456c133008 100644 (file)
@@ -141,7 +141,7 @@ char eepromData[I2C_EEPROM_TEST_LENGTH] = {0x55, 0x33, 0xEE, 0x41, 0x4d, 0x35, 0
#elif defined (evmK2H) || defined (evmK2K) || defined (evmK2E) || defined (evmK2L) || defined (evmK2G) || defined (iceK2G) || defined (EVM_OMAPL137)
char eepromData[I2C_EEPROM_TEST_LENGTH] = {0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08,
0x09, 0x10};
-#elif defined (evmC6678) || defined (evmC6657) || defined (am65xx_evm) || defined (am65xx_idk) || defined (j721e_sim) || defined (j721e_evm) || defined(j7200_evm)
+#elif defined (evmC6678) || defined (evmC6657) || defined (am65xx_evm) || defined (am65xx_idk) || defined (j721e_sim) || defined (j721e_evm) || defined(j7200_evm) || defined (am64x_evm)
char eepromData[I2C_EEPROM_TEST_LENGTH] = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00};
#else
goto Err;
}
-#if defined (evmK2H) || defined (evmK2K) || defined (evmK2E) || defined (evmK2L) || defined (evmK2G) || defined (iceK2G) || defined (am65xx_evm) || defined (am65xx_idk) || defined (j721e_sim) || defined (j721e_evm) || defined (j7200_evm)
+#if defined (evmK2H) || defined (evmK2K) || defined (evmK2E) || defined (evmK2L) || defined (evmK2G) || defined (iceK2G) || defined (am65xx_evm) || defined (am65xx_idk) || defined (j721e_sim) || defined (j721e_evm) || defined (j7200_evm) || defined (am64x_evm)
BOARD_delay(I2C_EEPROM_TEST_DELAY);
#endif
#else
-#if defined (evmK2H) || defined (evmK2K) || defined (evmK2E) || defined (evmK2L) || defined (evmK2G) || defined (iceK2G) || defined (EVM_OMAPL137) || defined (am65xx_evm) || defined (am65xx_idk) || defined (j721e_sim) || defined (j721e_evm) || defined(j7200)
+#if defined (evmK2H) || defined (evmK2K) || defined (evmK2E) || defined (evmK2L) || defined (evmK2G) || defined (iceK2G) || defined (EVM_OMAPL137) || defined (am65xx_evm) || defined (am65xx_idk) || defined (j721e_sim) || defined (j721e_evm) || defined(j7200) || defined (am64x_evm)
/* EEPROM write disabled on K2, need copy data */
copyData = TRUE;
#endif
}
else
{
-#if defined (evmC6678) || defined (evmC6657) || defined (am65xx_evm) || defined (am65xx_idk) || defined (j721e_sim) || defined (j721e_evm) || defined (j7200_evm)
+#if defined (evmC6678) || defined (evmC6657) || defined (am65xx_evm) || defined (am65xx_idk) || defined (j721e_sim) || defined (j721e_evm) || defined (j7200_evm) || defined (am64x_evm)
copyData = TRUE;
#endif
index f503c7f83b0832cd192c36d0528d409f4b74ba1c..263de1ba8df9db96c9690fb3c595874bc2e11300 100644 (file)
MODULE_NAME = pruss
-ifeq ($(SOC),$(filter $(SOC), am571x am572x am437x am335x k2g am574x am65xx j721e))
+ifeq ($(SOC),$(filter $(SOC), am571x am572x am437x am335x k2g am574x am65xx j721e am64x))
SRCDIR += soc/$(SOC)
INCDIR += soc
# Common source files across all platforms and cores
index 96cc3742460cd9463f3978687699a6be3d032665..dfdc89710912127329dbf0a23e622621bfcbd5e3 100644 (file)
'am335x',
'am437x',
'k2g',
- 'am65xx'
+ 'am65xx',
+ 'am64x',
];
/* Get the SOC */
index 97cb3526c5ca5f2d77a5fc448cc15442f37c5677..903d50b205e0b33fe52b3337a6a1204f9786147e 100644 (file)
# under other list
drvpruss_BOARDLIST = icev2AM335x idkAM437x idkAM571x idkAM572x iceK2G idkAM574x
-drvpruss_SOCLIST = am574x am572x am571x am437x am335x k2g am65xx j721e
+drvpruss_SOCLIST = am574x am572x am571x am437x am335x k2g am65xx j721e am64x
drvpruss_am574x_CORELIST = c66x a15_0 ipu1_0 pru_0 pru_1
drvpruss_am572x_CORELIST = c66x a15_0 ipu1_0 pru_0 pru_1
drvpruss_k2g_CORELIST = c66x a15_0 pru_0 pru_1
drvpruss_am335x_CORELIST = a8host pru_0 pru_1
drvpruss_am65xx_CORELIST = mpu1_0 mcu1_0
drvpruss_j721e_CORELIST = mcu1_0 mpu1_0
+drvpruss_am64x_CORELIST = mpu1_0 mcu1_0 mcu1_1 mcu2_0 mcu2_1 ipu1_0
############################
# uart package
diff --git a/packages/ti/drv/pruss/soc/am64x/pruicss_soc.c b/packages/ti/drv/pruss/soc/am64x/pruicss_soc.c
--- /dev/null
@@ -0,0 +1,134 @@
+/**
+ * @file pruicss_soc.c
+ *
+ * @brief This is device specific configuration file .
+ */
+/*
+ * Copyright (c) 2019, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/** ============================================================================*/
+
+#include <ti/csl/soc.h>
+#include <ti/drv/pruss/pruicss.h>
+#include <ti/drv/pruss/soc/pruicss_v1.h>
+
+/* PRUICSS configuration structure */
+PRUICSS_HwAttrs prussInitCfg[PRUICCSS_INSTANCE_MAX-1] =
+{
+ {
+ CSL_PRU_ICSSG0_DRAM0_SLV_RAM_BASE, /* baseAddr */
+ 0, /* version */
+ CSL_PRU_ICSSG0_PR1_PDSP0_IRAM_BASE, /* prussPru0CtrlRegBase */
+ CSL_PRU_ICSSG0_PR1_PDSP1_IRAM_BASE, /* prussPru1CtrlRegBase */
+ CSL_PRU_ICSSG0_PR1_ICSS_INTC_INTC_SLV_BASE, /* prussIntcRegBase */
+ CSL_PRU_ICSSG0_PR1_CFG_SLV_BASE, /* prussCfgRegBase */
+ CSL_PRU_ICSSG0_PR1_ICSS_UART_UART_SLV_BASE, /* prussUartRegBase */
+ CSL_PRU_ICSSG0_IEP0_BASE, /* prussIepRegBase */
+ CSL_PRU_ICSSG0_PR1_ICSS_ECAP0_ECAP_SLV_BASE, /* prussEcapRegBase */
+ CSL_PRU_ICSSG0_PR1_MII_RT_PR1_MII_RT_CFG_BASE, /* prussMiiRtCfgRegBase */
+ CSL_PRU_ICSSG0_PR1_MDIO_V1P7_MDIO_BASE, /* prussMiiMdioRegBase */
+ CSL_PRU_ICSSG0_DRAM0_SLV_RAM_BASE, /* prussPru0DramBase */
+ CSL_PRU_ICSSG0_DRAM1_SLV_RAM_BASE, /* prussPru1DramBase */
+ CSL_PRU_ICSSG0_PR1_PDSP0_IRAM_RAM_BASE, /* prussPru0IramBase */
+ CSL_PRU_ICSSG0_PR1_PDSP1_IRAM_RAM_BASE, /* prussPru1IramBase */
+ CSL_PRU_ICSSG0_RAM_SLV_RAM_BASE, /* prussSharedDramBase */
+ CSL_PRU_ICSSG0_PR1_RTU0_PR1_RTU0_IRAM_RAM_BASE, /* prussRtu0IramBase */
+ CSL_PRU_ICSSG0_PR1_RTU1_PR1_RTU1_IRAM_RAM_BASE, /* prussRtu1IramBase */
+ CSL_PRU_ICSSG0_PR1_RTU0_PR1_RTU0_IRAM_BASE, /* prussRtu0CtrlRegBase */
+ CSL_PRU_ICSSG0_PR1_RTU1_PR1_RTU1_IRAM_BASE, /* prussRtu1CtrlRegBase */
+ CSL_PRU_ICSSG0_PR1_PDSP_TX0_IRAM_BASE, /* prussTxPru0CtrlRegBase */
+ CSL_PRU_ICSSG0_PR1_PDSP_TX1_IRAM_BASE, /* prussTxPru1CtrlRegBase */
+ CSL_PRU_ICSSG0_PR1_PDSP_TX0_IRAM_RAM_BASE, /* prussTxPru0IramBase */
+ CSL_PRU_ICSSG0_PR1_PDSP_TX1_IRAM_RAM_BASE, /* prussTxPru1IramBase */
+ CSL_PRU_ICSSG0_DRAM0_SLV_RAM_SIZE, /* prussPru0DramSize */
+ CSL_PRU_ICSSG0_DRAM1_SLV_RAM_SIZE, /* prussPru1DramSize */
+ CSL_PRU_ICSSG0_PR1_PDSP0_IRAM_SIZE, /* prussPru0IramSize */
+ CSL_PRU_ICSSG0_PR1_PDSP1_IRAM_SIZE, /* prussPru1IramSize */
+ CSL_PRU_ICSSG0_RAM_SLV_RAM_SIZE, /* prussSharedDramSize */
+ CSL_PRU_ICSSG0_PR1_RTU0_PR1_RTU0_IRAM_RAM_SIZE, /* prussRtu0IramSize */
+ CSL_PRU_ICSSG0_PR1_RTU1_PR1_RTU1_IRAM_RAM_SIZE, /* prussRtu1IramSize */
+ CSL_PRU_ICSSG0_PR1_PDSP_TX0_IRAM_RAM_SIZE, /* prussTxPru0IramSize */
+ CSL_PRU_ICSSG0_PR1_PDSP_TX1_IRAM_RAM_SIZE /* prussTxPru1IramSize */
+ },
+ {
+ CSL_PRU_ICSSG1_DRAM0_SLV_RAM_BASE, /* baseAddr */
+ 0, /* version */
+ CSL_PRU_ICSSG1_PR1_PDSP0_IRAM_BASE, /* prussPru0CtrlRegBase */
+ CSL_PRU_ICSSG1_PR1_PDSP1_IRAM_BASE, /* prussPru1CtrlRegBase */
+ CSL_PRU_ICSSG1_PR1_ICSS_INTC_INTC_SLV_BASE, /* prussIntcRegBase */
+ CSL_PRU_ICSSG1_PR1_CFG_SLV_BASE, /* prussCfgRegBase */
+ CSL_PRU_ICSSG1_PR1_ICSS_UART_UART_SLV_BASE, /* prussUartRegBase */
+ CSL_PRU_ICSSG1_IEP0_BASE, /* prussIepRegBase */
+ CSL_PRU_ICSSG1_PR1_ICSS_ECAP0_ECAP_SLV_BASE, /* prussEcapRegBase */
+ CSL_PRU_ICSSG1_PR1_MII_RT_PR1_MII_RT_CFG_BASE, /* prussMiiRtCfgRegBase */
+ CSL_PRU_ICSSG1_PR1_MDIO_V1P7_MDIO_BASE, /* prussMiiMdioRegBase */
+ CSL_PRU_ICSSG1_DRAM0_SLV_RAM_BASE, /* prussPru0DramBase */
+ CSL_PRU_ICSSG1_DRAM1_SLV_RAM_BASE, /* prussPru1DramBase */
+ CSL_PRU_ICSSG1_PR1_PDSP0_IRAM_RAM_BASE, /* prussPru0IramBase */
+ CSL_PRU_ICSSG1_PR1_PDSP1_IRAM_RAM_BASE, /* prussPru1IramBase */
+ CSL_PRU_ICSSG1_RAM_SLV_RAM_BASE, /* prussSharedDramBase */
+ CSL_PRU_ICSSG1_PR1_RTU0_PR1_RTU0_IRAM_RAM_BASE, /* prussRtu0IramBase */
+ CSL_PRU_ICSSG1_PR1_RTU1_PR1_RTU1_IRAM_RAM_BASE, /* prussRtu1IramBase */
+ CSL_PRU_ICSSG1_PR1_RTU0_PR1_RTU0_IRAM_BASE, /* prussRtu0CtrlRegBase */
+ CSL_PRU_ICSSG1_PR1_RTU1_PR1_RTU1_IRAM_BASE, /* prussRtu1CtrlRegBase */
+ CSL_PRU_ICSSG1_PR1_PDSP_TX0_IRAM_BASE, /* prussTxPru0CtrlRegBase */
+ CSL_PRU_ICSSG1_PR1_PDSP_TX1_IRAM_BASE, /* prussTxPru1CtrlRegBase */
+ CSL_PRU_ICSSG1_PR1_PDSP_TX0_IRAM_RAM_BASE, /* prussTxPru0IramBase */
+ CSL_PRU_ICSSG1_PR1_PDSP_TX1_IRAM_RAM_BASE, /* prussTxPru1IramBase */
+ CSL_PRU_ICSSG1_DRAM0_SLV_RAM_SIZE, /* prussPru0DramSize */
+ CSL_PRU_ICSSG1_DRAM1_SLV_RAM_SIZE, /* prussPru1DramSize */
+ CSL_PRU_ICSSG1_PR1_PDSP0_IRAM_SIZE, /* prussPru0IramSize */
+ CSL_PRU_ICSSG1_PR1_PDSP1_IRAM_SIZE, /* prussPru1IramSize */
+ CSL_PRU_ICSSG1_RAM_SLV_RAM_SIZE, /* prussSharedDramSize */
+ CSL_PRU_ICSSG1_PR1_RTU0_PR1_RTU0_IRAM_RAM_SIZE, /* prussRtu0IramSize */
+ CSL_PRU_ICSSG1_PR1_RTU1_PR1_RTU1_IRAM_RAM_SIZE, /* prussRtu1IramSize */
+ CSL_PRU_ICSSG1_PR1_PDSP_TX0_IRAM_RAM_SIZE, /* prussTxPru0IramSize */
+ CSL_PRU_ICSSG1_PR1_PDSP_TX1_IRAM_RAM_SIZE /* prussTxPru1IramSize */
+ }
+};
+
+/* PRUICSS objects */
+PRUICSS_V1_Object prussObjects[PRUICCSS_INSTANCE_MAX-1];
+
+/* PRUICSS configuration structure */
+PRUICSS_Config pruss_config[PRUICCSS_INSTANCE_MAX-1] = {
+ {
+ &prussObjects[0],
+ &prussInitCfg[0]
+ },
+ {
+ &prussObjects[1],
+ &prussInitCfg[1]
+ }
+};
+
+
+
index eb685fc022adf53eb42ade490b71abf4191ab08f..5bdfee715136f42f8fc493acf0db35cc9417f8ed 100644 (file)
PRUICCSS_INSTANCE_THREE=3,
PRUICCSS_INSTANCE_MAX=4
}PRUICSS_MaxInstances;
-#elif defined(SOC_J721E)
+#elif defined(SOC_J721E) || defined(SOC_AM64X)
/*!
* @brief PRUICSS Instance IDs
*/
diff --git a/packages/ti/drv/sciclient/examples/sciclient_ccs_init/linker_r5_lite.lds b/packages/ti/drv/sciclient/examples/sciclient_ccs_init/linker_r5_lite.lds
--- /dev/null
@@ -0,0 +1,99 @@
+/*----------------------------------------------------------------------------*/\r
+/* File: k3m4_r5f_linker.cmd */\r
+/* Description: */\r
+/* Link command file for Maxwell M4 MCU 0 view */\r
+/* TI ARM Compiler version 15.12.3 LTS or later */\r
+/* */\r
+/* Platform: QT */\r
+/* (c) Texas Instruments 2017, All rights reserved. */\r
+/*----------------------------------------------------------------------------*/\r
+/* History: *'\r
+/* Aug 26th, 2016 Original version .......................... Loc Truong */\r
+/* Aug 01th, 2017 new TCM mem map .......................... Loc Truong */\r
+/* Nov 07th, 2017 Changes for R5F Init Code.................. Vivek Dhande */\r
+/* Feb 07th, 2017 Copied and changed for sciclient to build.. Piyali G. */\r
+/* Mar 26th, 2019 Changes for R5F startup Code............... Vivek Dhande */\r
+/*----------------------------------------------------------------------------*/\r
+/* Linker Settings */\r
+/* Standard linker options */\r
+--retain="*(.bootCode)"\r
+--retain="*(.startupCode)"\r
+--retain="*(.startupData)"\r
+--retain="*(.intvecs)"\r
+--retain="*(.intc_text)"\r
+--retain="*(.rstvectors)"\r
+--retain="*(.irqStack)"\r
+--retain="*(.fiqStack)"\r
+--retain="*(.abortStack)"\r
+--retain="*(.undStack)"\r
+--retain="*(.svcStack)"\r
+--fill_value=0\r
+--stack_size=0x2000\r
+--heap_size=0x2000\r
+\r
+-stack 0x2000 /* SOFTWARE STACK SIZE */\r
+-heap 0x2000 /* HEAP AREA SIZE */\r
+\r
+/* Stack Sizes for various modes */\r
+__IRQ_STACK_SIZE = 0x100;\r
+__FIQ_STACK_SIZE = 0x100;\r
+__ABORT_STACK_SIZE = 0x100;\r
+__UND_STACK_SIZE = 0x100;\r
+__SVC_STACK_SIZE = 0x100;\r
+\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/* Memory Map */\r
+/*----------------------------------------------------------------------------*/\r
+/* Memory Map */\r
+MEMORY\r
+{\r
+ /* Reset Vectors base address(RESET_VECTORS) should be 64 bytes aligned */\r
+ RESET_VECTORS (X) : origin=0x70000000 length=0x100\r
+ /* Last 64K of the OSMCRAM is used by SYSFW for the Secure Proxy Backing RAM */\r
+ OCMRAM_sciclientTest (RWIX) : origin=0x70000100 length=0x180000-0x100-0x10000 /* 1.5MB - 0x1100 */\r
+\r
+} /* end of MEMORY */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/* Section Configuration */\r
+\r
+SECTIONS\r
+{\r
+/* 'intvecs' and 'intc_text' sections shall be placed within */\r
+/* a range of +\- 16 MB */\r
+ .rstvectors : {} palign(8) > RESET_VECTORS\r
+ .bootCode : {} palign(8) > OCMRAM_sciclientTest\r
+ .startupCode : {} palign(8) > OCMRAM_sciclientTest\r
+ .startupData : {} palign(8) > OCMRAM_sciclientTest, type = NOINIT\r
+ .text : {} palign(8) > OCMRAM_sciclientTest\r
+ .const : {} palign(8) > OCMRAM_sciclientTest\r
+ .cinit : {} palign(8) > OCMRAM_sciclientTest\r
+ .pinit : {} palign(8) > OCMRAM_sciclientTest\r
+ .data : {} palign(128) > OCMRAM_sciclientTest\r
+ .boardcfg_data : {} palign(128) > OCMRAM_sciclientTest\r
+ .bss : {} align(4) > OCMRAM_sciclientTest\r
+ .sysmem : {} > OCMRAM_sciclientTest\r
+ .stack : {} align(4) > OCMRAM_sciclientTest (HIGH)\r
+ .irqStack : {. = . + __IRQ_STACK_SIZE;} align(4) > OCMRAM_sciclientTest (HIGH)\r
+ RUN_START(__IRQ_STACK_START)\r
+ RUN_END(__IRQ_STACK_END)\r
+ .fiqStack : {. = . + __FIQ_STACK_SIZE;} align(4) > OCMRAM_sciclientTest (HIGH)\r
+ RUN_START(__FIQ_STACK_START)\r
+ RUN_END(__FIQ_STACK_END)\r
+ .abortStack : {. = . + __ABORT_STACK_SIZE;} align(4) > OCMRAM_sciclientTest (HIGH)\r
+ RUN_START(__ABORT_STACK_START)\r
+ RUN_END(__ABORT_STACK_END)\r
+ .undStack : {. = . + __UND_STACK_SIZE;} align(4) > OCMRAM_sciclientTest (HIGH)\r
+ RUN_START(__UND_STACK_START)\r
+ RUN_END(__UND_STACK_END)\r
+ .svcStac : {. = . + __SVC_STACK_SIZE;} align(4) > OCMRAM_sciclientTest (HIGH)\r
+ RUN_START(__SVC_STACK_START)\r
+ RUN_END(__SVC_STACK_END)\r
+} /* end of SECTIONS */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+/* Misc linker settings */\r
+\r
+\r
+/*-------------------------------- END ---------------------------------------*/\r
diff --git a/packages/ti/drv/sciclient/examples/sciclient_ccs_init/makefile b/packages/ti/drv/sciclient/examples/sciclient_ccs_init/makefile
index 7a535fe968fafe3d991b2d5bbc418f9bbe9a2af1..869b69d0d120e20878570e7ce62a65a39c317ee5 100644 (file)
CFLAGS_LOCAL_COMMON = $(PDK_CFLAGS)
PACKAGE_SRCS_COMMON = . ../common
+ifeq ($(SOC),$(filter $(SOC), am64x))
+CONFIG_BLD_LNK_r5f = linker_r5_lite.lds
+else
CONFIG_BLD_LNK_r5f = linker_r5.lds
+endif
# Core/SoC/platform specific source files and CFLAGS
# Example:
diff --git a/packages/ti/drv/sciclient/examples/sciclient_ccs_init/sciclient_ccs_init_main.c b/packages/ti/drv/sciclient/examples/sciclient_ccs_init/sciclient_ccs_init_main.c
index 511143fa3cc28d8dcbd50a2733e6775d03d81095..112426b8e9847ea744f16f0abe5ede07143ad32e 100755 (executable)
/* Host-ID allowed to send SCI-message for main isolation.
* If mismatch, SCI message will be rejected with NAK.
*/
+#if defined (SOC_AM64X)
+ .main_isolation_hostid = TISCI_HOST_ID_MAIN_0_R5_0,
+#else
.main_isolation_hostid = TISCI_HOST_ID_R5_1,
+#endif
},
/* tisci_boardcfg_sec_proxy */
/* ========================================================================== */
static int32_t App_getRevisionTest(void);
-#if !defined (SOC_J721E)
+#if defined (SOC_AM65XX)
static int32_t setPLLClk(uint32_t modId, uint32_t clkId, uint64_t clkRate);
#endif
status = Sciclient_init(&config);
dmtimer0_enable();
+#if !defined (SOC_AM64X)
if (CSL_PASS == status)
{
Sciclient_BoardCfgPrms_t boardCfgPrms =
dmtimer0_read();
status = Sciclient_boardCfgPm(&boardCfgPrms_pm);
dmtimer0_read();
+
if (status == CSL_PASS)
{
uint32_t boardCfgLow[] = SCICLIENT_BOARDCFG_RM;
{
printf("\nSciclient Devgrp_01 Board Configuration has failed \n");
}
+#else
+ if (CSL_PASS == status)
+ {
+ printf(" \nDMSC Board Configuration with Debug enable \n");
+ dmtimer0_read();
+ status = Sciclient_boardCfg(NULL);
+ dmtimer0_read();
+ }
+ else
+ {
+ printf("\nSciclient Init Failed.\n");
+ }
+ if (CSL_PASS == status)
+ {
+ if (status == CSL_PASS)
+ {
+ dmtimer0_read();
+ status = Sciclient_boardCfgPm(NULL);
+ dmtimer0_read();
+ }
+ }
+ else
+ {
+ printf("\nSciclient Common Board Configuration has failed \n");
+ }
+ if (CSL_PASS == status)
+ {
+ if (status == CSL_PASS)
+ {
+ dmtimer0_read();
+ status = Sciclient_boardCfgRm(NULL);
+ dmtimer0_read();
+ }
+ }
+ else
+ {
+ printf("\nSciclient PM Board Configuration has failed \n");
+ }
+ if (status != CSL_PASS)
+ {
+ printf("\nSciclient RM Board Configuration has failed \n");
+ }
+#endif
if (status == CSL_PASS)
{
status = Sciclient_service(&reqPrm, &respPrm);
}
/* Set DDR PLL to 400 Mhz. SYSFW default sets this to 333.33 Mhz */
/* Comment this code if LPDDR is used */
- #if !defined(SOC_J721E)
+ #if defined(SOC_AM65XX)
if (status == CSL_PASS)
{
/* Set DDR PLL to 400 Mhz. SYSFW default sets this to 333.33 Mhz */
return status;
}
-#if !defined(SOC_J721E)
+#if defined(SOC_AM65XX)
/**
* \brief PLL clock configuration
*
diff --git a/packages/ti/drv/sciclient/examples/sciclient_firmware_boot_TestApp/boot_init.asm b/packages/ti/drv/sciclient/examples/sciclient_firmware_boot_TestApp/boot_init.asm
index 5a899f6549082a659fed01e5d56f446299e2c326..3ea2847a55d57dfa24be97490b6ba1d6c9d2351b 100755 (executable)
_sciclientTestEntry:\r
.asmfunc\r
\r
- LDR r0, _atcm_start ; Start address of ATCM\r
- LDR r1, _atcm_end ; End address of ATCM\r
- MOV r2, #0\r
-Loop:\r
- STR r2, [r0], #4 ; Clear one word in ATCM\r
- CMP r0, r1\r
- BLE Loop ; Clear till ATCM end\r
-\r
LDR r0, _btcm_start ; Start address of BTCM\r
LDR r1, _btcm_end ; End address of BTCM\r
MOV r2, #0\r
\r
.endasmfunc\r
\r
-_atcm_start:\r
- .word 0x0\r
-_atcm_end:\r
- .word 0x7FFC\r
_btcm_start:\r
.word 0x41010000\r
_btcm_end:\r
diff --git a/packages/ti/drv/sciclient/examples/sciclient_firmware_boot_TestApp/linker_r5_am64x.lds b/packages/ti/drv/sciclient/examples/sciclient_firmware_boot_TestApp/linker_r5_am64x.lds
--- /dev/null
@@ -0,0 +1,111 @@
+/*----------------------------------------------------------------------------*/
+/* File: k3m4_r5f_linker.cmd */
+/* Description: */
+/* Link command file for Maxwell M4 MCU 0 view */
+/* TI ARM Compiler version 15.12.3 LTS or later */
+/* */
+/* Platform: QT */
+/* (c) Texas Instruments 2017, All rights reserved. */
+/*----------------------------------------------------------------------------*/
+/* History: *'
+/* Aug 26th, 2016 Original version .......................... Loc Truong */
+/* Aug 01th, 2017 new TCM mem map .......................... Loc Truong */
+/* Nov 07th, 2017 Changes for R5F Init Code.................. Vivek Dhande */
+/* Feb 07th, 2017 Copied and changed for sciclient to build.. Piyali G. */
+/* Mar 26th, 2019 Changes for R5F startup Code............... Vivek Dhande */
+/*----------------------------------------------------------------------------*/
+/* Linker Settings */
+/* Standard linker options */
+--retain="*(.bootCode)"
+--retain="*(.startupCode)"
+--retain="*(.startupData)"
+--retain="*(.intvecs)"
+--retain="*(.intc_text)"
+--retain="*(.rstvectors)"
+--retain="*(.irqStack)"
+--retain="*(.fiqStack)"
+--retain="*(.abortStack)"
+--retain="*(.undStack)"
+--retain="*(.svcStack)"
+--fill_value=0
+--stack_size=0x2000
+--heap_size=0x2000
+--entry_point=_sciclientTestResetVectors
+
+-stack 0x2000 /* SOFTWARE STACK SIZE */
+-heap 0x2000 /* HEAP AREA SIZE */
+
+/* Stack Sizes for various modes */
+__IRQ_STACK_SIZE = 0x100;
+__FIQ_STACK_SIZE = 0x100;
+__ABORT_STACK_SIZE = 0x100;
+__UND_STACK_SIZE = 0x100;
+__SVC_STACK_SIZE = 0x100;
+
+
+/*----------------------------------------------------------------------------*/
+/* Memory Map */
+/*----------------------------------------------------------------------------*/
+/* Memory Map */
+MEMORY
+{
+ /* MCU0_R5F_0 local view */
+ MCU0_R5F_TCMA (X) : origin=0x0 length=0x8000
+ MCU0_R5F_TCMB0 (RWIX) : origin=0x41010000 length=0x8000
+
+ /* Reset Vectors base address(RESET_VECTORS) should be 64 bytes aligned */
+ RESET_VECTORS (X) : origin=0x70000100 length=0x100
+
+ /* MCU0 memory used for sciclientTest. Available to app for dynamic use ~160KB */
+ /* RBL uses 0x41C58000 and beyond. sciclientTest, at load cannot cross this */
+ OCMRAM_sciclientTest (RWIX) : origin=0x70000200 length=0x3F000-0x200
+
+ /* Used by sciclientTest at runtime to load SYSFW. Available to app for dynamic use */
+ OCMRAM_sciclientTest_SYSFW (RWIX) : origin=0x7003F000 length=0x41000
+
+} /* end of MEMORY */
+
+/*----------------------------------------------------------------------------*/
+/* Section Configuration */
+
+SECTIONS
+{
+/* 'intvecs' and 'intc_text' sections shall be placed within */
+/* a range of +\- 16 MB */
+ .rstvectors : {} palign(8) > RESET_VECTORS
+ .bootCode : {} palign(8) > OCMRAM_sciclientTest
+ .startupCode : {} palign(8) > OCMRAM_sciclientTest
+ .startupData : {} palign(8) > OCMRAM_sciclientTest, type = NOINIT
+ .text : {} palign(8) > OCMRAM_sciclientTest
+ .const : {} palign(8) > OCMRAM_sciclientTest
+ .cinit : {} palign(8) > OCMRAM_sciclientTest
+ .pinit : {} palign(8) > OCMRAM_sciclientTest
+ .data : {} palign(128) > OCMRAM_sciclientTest
+ .boardcfg_data : {} palign(128) > OCMRAM_sciclientTest
+ .bss : {} align(4) > MCU0_R5F_TCMB0
+ .sysmem : {} > MCU0_R5F_TCMB0
+ .stack : {} align(4) > MCU0_R5F_TCMB0 (HIGH)
+ .irqStack : {. = . + __IRQ_STACK_SIZE;} align(4) > MCU0_R5F_TCMB0 (HIGH)
+ RUN_START(__IRQ_STACK_START)
+ RUN_END(__IRQ_STACK_END)
+ .fiqStack : {. = . + __FIQ_STACK_SIZE;} align(4) > MCU0_R5F_TCMB0 (HIGH)
+ RUN_START(__FIQ_STACK_START)
+ RUN_END(__FIQ_STACK_END)
+ .abortStack : {. = . + __ABORT_STACK_SIZE;} align(4) > MCU0_R5F_TCMB0 (HIGH)
+ RUN_START(__ABORT_STACK_START)
+ RUN_END(__ABORT_STACK_END)
+ .undStack : {. = . + __UND_STACK_SIZE;} align(4) > MCU0_R5F_TCMB0 (HIGH)
+ RUN_START(__UND_STACK_START)
+ RUN_END(__UND_STACK_END)
+ .svcStac : {. = . + __SVC_STACK_SIZE;} align(4) > MCU0_R5F_TCMB0 (HIGH)
+ RUN_START(__SVC_STACK_START)
+ RUN_END(__SVC_STACK_END)
+ .firmware : {} palign(8) > OCMRAM_sciclientTest_SYSFW
+
+} /* end of SECTIONS */
+
+/*----------------------------------------------------------------------------*/
+/* Misc linker settings */
+
+
+/*-------------------------------- END ---------------------------------------*/
diff --git a/packages/ti/drv/sciclient/examples/sciclient_firmware_boot_TestApp/makefile b/packages/ti/drv/sciclient/examples/sciclient_firmware_boot_TestApp/makefile
index 3d0a3c26674b246d725b9612a56995e9683756ea..51172aa3b05ee3094cb65c5eed3c25bddbed8273 100755 (executable)
sciclient_appCommon.c
ifeq ($(CORE), mcu1_0)
+ifeq ($(SOC),$(filter $(SOC), am65xx))
COMP_LIST_COMMON += mmcsd fatfs_indp
+endif
SRCS_ASM_COMMON += boot_init.asm
endif
CFLAGS_LOCAL_COMMON = $(PDK_CFLAGS) -DBARE_METAL
PACKAGE_SRCS_COMMON = . ../common
+ifeq ($(SOC),$(filter $(SOC), am64x))
+CONFIG_BLD_LNK_r5f = $(PDK_INSTALL_PATH)/ti/drv/sciclient/examples/$(APP_NAME)/linker_r5_am64x.lds
+else
CONFIG_BLD_LNK_r5f = $(PDK_INSTALL_PATH)/ti/drv/sciclient/examples/$(APP_NAME)/linker_r5.lds
+endif
ifeq ($(CORE),mpu1_0)
LNKFLAGS_LOCAL_mpu1_0 += --entry Entry
diff --git a/packages/ti/drv/sciclient/examples/sciclient_firmware_boot_TestApp/sciclient_firmware_boot_main.c b/packages/ti/drv/sciclient/examples/sciclient_firmware_boot_TestApp/sciclient_firmware_boot_main.c
index 26d8d13deca19f0e449197962293030f8460fa93..8d186a07c11b245b38bce984d0d1c104cf33fa1e 100755 (executable)
--- a/packages/ti/drv/sciclient/examples/sciclient_firmware_boot_TestApp/sciclient_firmware_boot_main.c
+++ b/packages/ti/drv/sciclient/examples/sciclient_firmware_boot_TestApp/sciclient_firmware_boot_main.c
#if defined (SOC_J721E)
/* Relocate CSL Vectors to ATCM*/
memcpy((void *)CSL_MCU_ARMSS_ATCM_BASE, (void *)_resetvectors, 0x100);
-#else
+#elif defined (SOC_AM65XX)
/* Relocate CSL Vectors to ATCM*/
memcpy((void *)CSL_MCU_ATCM_BASE, (void *)_resetvectors, 0x100);
App_sciclientConsoleInit();
+#else
+ /* Relocate CSL Vectors to ATCM*/
+ memcpy((void *)CSL_R5FSS0_ATCM_BASE, (void *)_resetvectors, 0x100);
+ App_sciclientConsoleInit();
#endif
App_loadFirmwareTest();
App_getRevisionTestPol();
NULL
};
+ struct tisci_msg_version_req request;
const Sciclient_ReqPrm_t reqPrm =
{
TISCI_MSG_VERSION,
TISCI_MSG_FLAG_AOP,
- NULL,
- 0,
+ (uint8_t *) &request,
+ sizeof(request),
SCICLIENT_SERVICE_WAIT_FOREVER
};
(uint8_t *) &response,
sizeof (response)
};
+
start_ticks = TimerP_getTimeInUsecs();
status = Sciclient_init(&config);
" Board configuration for RM test...FAILED \n");
status = CSL_EFAIL;
}
-
+#if !defined (SOC_AM64X)
if (Sciclient_boardCfgSec(NULL) == CSL_PASS)
{
App_sciclientPrintf(
" Board configuration for SECURITY test...FAILED \n");
status = CSL_EFAIL;
}
+#endif
}
else
{
diff --git a/packages/ti/drv/sciclient/include/sciclient_soc.h b/packages/ti/drv/sciclient/include/sciclient_soc.h
index b74ba921b36e267d6462769277eb41b7c67b901c..1450c9c62ff46549d9214fa77552fd7d07353278 100644 (file)
#include <ti/drv/sciclient/soc/V1/sciclient_firmware_V1.h>\r
#endif\r
\r
+#if defined (SOC_AM64X)\r
+#include <ti/drv/sciclient/soc/sysfw/include/am64x/tisci_resasg_types.h>\r
+#include <ti/drv/sciclient/soc/V3/sciclient_fmwMsgParams.h>\r
+#include <ti/drv/sciclient/soc/V3/sciclient_firmware_V3.h>\r
+#endif\r
+\r
+\r
#ifdef __cplusplus\r
extern "C" {\r
#endif\r
index c906e8f797285f3ef29cb4d4a7ed2c0d1dc8ca30..55a8b554240d53c3961a35aa65fa12f7fef3547a 100644 (file)
'am65xx',
'j721e',
'j7200',
+ 'am64x',
];
var libNames = [
'sciclient'
index e16d0ef17b46ae1e3655b7ae39daff65cca32ff1..2e2497fe2a453e14e327cf46374f615dc6951db4 100755 (executable)
#include <ti/drv/sciclient/soc/sysfw/include/j721e/tisci_sec_proxy.h>
#include <ti/drv/sciclient/soc/sysfw/include/j721e/tisci_boardcfg_constraints.h>
#endif
+#if defined (SOC_AM64X)
+#include <ti/drv/sciclient/soc/sysfw/include/am64x/tisci_resasg_types.h>
+#include <ti/drv/sciclient/soc/sysfw/include/am64x/tisci_hosts.h>
+#include <ti/drv/sciclient/soc/sysfw/include/am64x/tisci_sec_proxy.h>
+#include <ti/drv/sciclient/soc/sysfw/include/am64x/tisci_boardcfg_constraints.h>
+#endif
#include <ti/drv/sciclient/soc/sysfw/include/tisci/security/tisci_sec_macros.h>
#include <ti/drv/sciclient/soc/sysfw/include/tisci/security/tisci_firewall.h>
#include <ti/drv/sciclient/soc/sysfw/include/tisci/security/tisci_procboot.h>
diff --git a/packages/ti/drv/sciclient/sciclient_component.mk b/packages/ti/drv/sciclient/sciclient_component.mk
index a51bc169815fa095a88e9f53cd42ca048fb39c1b..e48f1a2f651476af4c2ef8a1860e8cb484691d90 100644 (file)
############################
sciclient_LIB_LIST = sciclient
-drvsciclient_BOARDLIST = am65xx_evm am65xx_idk j721e_sim j721e_evm j7200_evm
-drvsciclient_SOCLIST = am65xx j721e j7200
+drvsciclient_BOARDLIST = am65xx_evm am65xx_idk j721e_sim j721e_evm j7200_evm am64x_evm
+drvsciclient_SOCLIST = am65xx j721e j7200 am64x
drvsciclient_am65xx_CORELIST = mcu1_0 mcu1_1 mpu1_0
drvsciclient_j721e_CORELIST = mpu1_0 mcu1_0 mcu1_1 mcu2_0 mcu2_1 mcu3_0 mcu3_1 c66xdsp_1 c66xdsp_2 c7x_1 c7x-hostemu
drvsciclient_j7200_CORELIST = mpu1_0 mcu1_0 mcu1_1 mcu2_0 mcu2_1
+drvsciclient_am64x_CORELIST = mpu1_0 mcu1_0 mcu1_1 mcu2_0 mcu2_1 m4f_0
drvsciclient_DISABLE_PARALLEL_MAKE = yes
sciclient_COMP_LIST = sciclient
export sciclient_firmware_boot_TestApp_CORE_DEPENDENCY
sciclient_firmware_boot_TestApp_PKG_LIST = sciclient_firmware_boot_TestApp
sciclient_firmware_boot_TestApp_INCLUDE = $(sciclient_firmware_boot_TestApp_PATH)
-sciclient_firmware_boot_TestApp_BOARDLIST = am65xx_evm
+sciclient_firmware_boot_TestApp_BOARDLIST = am65xx_evm am64x_evm
export sciclient_firmware_boot_TestApp_BOARDLIST
sciclient_firmware_boot_TestApp_$(SOC)_CORELIST = mcu1_0
export sciclient_firmware_boot_TestApp_$(SOC)_CORELIST
export sciclient_ccs_init_CORE_DEPENDENCY
sciclient_ccs_init_PKG_LIST = sciclient_ccs_init
sciclient_ccs_init_INCLUDE = $(sciclient_ccs_init_PATH)
-sciclient_ccs_init_BOARDLIST = am65xx_evm j721e_sim j721e_evm
+sciclient_ccs_init_BOARDLIST = am65xx_evm j721e_sim j721e_evm am64x_evm
export sciclient_ccs_init_BOARDLIST
# This application is only for mcu1_0
sciclient_ccs_init_$(SOC)_CORELIST = mcu1_0
diff --git a/packages/ti/drv/sciclient/soc/V3/sciclient_defaultBoardcfg.c b/packages/ti/drv/sciclient/soc/V3/sciclient_defaultBoardcfg.c
--- /dev/null
@@ -0,0 +1,138 @@
+/*
+ * Copyright (c) 2018, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/**
+ * \file V3/sciclient_defaultBoardcfg.c
+ *
+ * \brief File containing the boardcfg default data structure to
+ * send TISCI_MSG_BOARD_CONFIG message.
+ *
+ */
+/* ========================================================================== */
+/* Include Files */
+/* ========================================================================== */
+#include <ti/drv/sciclient/soc/V3/sciclient_defaultBoardcfg.h>
+
+/* ========================================================================== */
+/* Global Variables */
+/* ========================================================================== */
+
+#if defined (BUILD_MCU1_0)
+const struct tisci_boardcfg gBoardConfigLow
+__attribute__(( aligned(128), section(".boardcfg_data") )) =
+{
+ /* tisci_boardcfg_abi_rev */
+ .rev = {
+ .tisci_boardcfg_abi_maj = TISCI_BOARDCFG_ABI_MAJ_VALUE,
+ .tisci_boardcfg_abi_min = TISCI_BOARDCFG_ABI_MIN_VALUE,
+ },
+
+ /* tisci_boardcfg_control */
+ .control = {
+ .subhdr = {
+ .magic = TISCI_BOARDCFG_CONTROL_MAGIC_NUM,
+ .size = sizeof(struct tisci_boardcfg_control),
+ },
+ /* Enable/disable support for System Firmware main isolation.
+ * If disabled, main isolation SCI message will be rejected with NAK.
+ */
+ .main_isolation_enable = 0x5A,
+ /* Host-ID allowed to send SCI-message for main isolation.
+ * If mismatch, SCI message will be rejected with NAK.
+ */
+ .main_isolation_hostid = TISCI_HOST_ID_MAIN_0_R5_0,
+ },
+
+ /* tisci_boardcfg_sec_proxy */
+ .secproxy = {
+ .subhdr = {
+ .magic = TISCI_BOARDCFG_SECPROXY_MAGIC_NUM,
+ .size = sizeof(struct tisci_boardcfg_secproxy),
+ },
+ /* Memory allocation for messages scaling factor. In current design,
+ * only value of “1” is supported. For future design, a value of “2”
+ * would double all memory allocations and credits, “3” would triple,
+ * and so on.
+ */
+ .scaling_factor = 0x1,
+ /* Memory allocation for messages profile number. In current design,
+ * only a value of “1” is supported. “0” is always invalid due to
+ * fault tolerance.
+ */
+ .scaling_profile = 0x1,
+ /* Do not configure main nav secure proxy. This removes all MSMC memory
+ * demands from System Firmware but limits MPU channels to one set of
+ * secure and one set of insecure. In current design, supports only “0”.
+ */
+ .disable_main_nav_secure_proxy = 0,
+ },
+
+ /* tisci_boardcfg_msmc */
+ .msmc = {
+ .subhdr = {
+ .magic = TISCI_BOARDCFG_MSMC_MAGIC_NUM,
+ .size = sizeof(struct tisci_boardcfg_msmc),
+ },
+ /* If the whole memory is X MB the value you write to this field is n.
+ * The value of n sets the cache size as n * X/32. The value of n should
+ * be given in steps of 4, which makes the size of cache to be
+ * configured in steps on X/8 MB.
+ */
+ .msmc_cache_size = 0x00,
+ },
+
+ /* boardcfg_dbg_cfg */
+ .debug_cfg = {
+ .subhdr = {
+ .magic = TISCI_BOARDCFG_DBG_CFG_MAGIC_NUM,
+ .size = sizeof(struct tisci_boardcfg_dbg_cfg),
+ },
+ /* This enables the trace for DMSC logging. Should be used only for
+ * debug.
+ */
+ /* Uncomment for Debug */
+ /*
+ .trace_dst_enables = (TISCI_BOARDCFG_TRACE_DST_UART0 |
+ TISCI_BOARDCFG_TRACE_DST_ITM |
+ TISCI_BOARDCFG_TRACE_DST_MEM),
+ .trace_src_enables = (TISCI_BOARDCFG_TRACE_SRC_PM |
+ TISCI_BOARDCFG_TRACE_SRC_RM |
+ TISCI_BOARDCFG_TRACE_SRC_SEC |
+ TISCI_BOARDCFG_TRACE_SRC_BASE |
+ TISCI_BOARDCFG_TRACE_SRC_USER |
+ TISCI_BOARDCFG_TRACE_SRC_SUPR)
+ */
+ .trace_dst_enables = 0,
+ .trace_src_enables = 0
+ },
+};
+#endif
+
diff --git a/packages/ti/drv/sciclient/soc/V3/sciclient_defaultBoardcfg.h b/packages/ti/drv/sciclient/soc/V3/sciclient_defaultBoardcfg.h
--- /dev/null
@@ -0,0 +1,85 @@
+/*
+ * Copyright (c) 2018, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/**
+ * \file V3/sciclient_defaultBoardcfg.h
+ *
+ * \brief File defining tisci_local_rm_boardcfg for boardCfg RM .
+ *
+ */
+
+#ifndef SCICLIENT_DEFAULTBOARDCFG_
+#define SCICLIENT_DEFAULTBOARDCFG_
+
+/* ========================================================================== */
+/* Include Files */
+/* ========================================================================== */
+#include <ti/csl/csl_types.h>
+#include <ti/drv/sciclient/sciclient.h>
+#include <ti/drv/sciclient/soc/sysfw/include/tisci/tisci_boardcfg.h>
+#include <ti/drv/sciclient/soc/sysfw/include/am64x/tisci_resasg_types.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* ========================================================================== */
+/* Global Variables */
+/* ========================================================================== */
+#if defined (BUILD_MCU1_0)
+
+/* Default board config structure */
+extern const struct tisci_boardcfg gBoardConfigLow;
+
+/* Default board config structure for RM*/
+extern const struct tisci_local_rm_boardcfg gBoardConfigLow_rm;
+
+/* Default board config structure for SECURITY */
+extern const struct tisci_boardcfg_sec gBoardConfigLow_security;
+
+/* ========================================================================== */
+/* Macros & Typedefs */
+/* ========================================================================== */
+
+/* \brief Structure to hold the RM board configuration */
+struct tisci_local_rm_boardcfg {
+ struct tisci_boardcfg_rm rm_boardcfg;
+ /**< Board configuration parameter */
+ struct tisci_boardcfg_rm_resasg_entry resasg_entries[TISCI_BOARDCFG_RM_RESASG_ENTRIES_MAX];
+ /**< Resource assignment entries */
+};
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #ifndef SCICLIENT_DEFAULTBOARDCFG_ */
diff --git a/packages/ti/drv/sciclient/soc/V3/sciclient_defaultBoardcfg_hex.h b/packages/ti/drv/sciclient/soc/V3/sciclient_defaultBoardcfg_hex.h
--- /dev/null
@@ -0,0 +1,72 @@
+/*
+ * Copyright (C) 2018 Texas Instruments Incorporated
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+/**
+* \file sciclient_defaultBoardcfg_hex.h
+*
+* \brief File containing the Binary in a C array.
+*
+*/
+
+/* ========================================================================== */
+/* Include Files */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/* Macros & Typedefs */
+/* ========================================================================== */
+
+#define SCICLIENT_BOARDCFG_SIZE_IN_BYTES (29U)
+
+/* ========================================================================== */
+/* Structure Declarations */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/* Function Declarations */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/* Global Variables */
+/* ========================================================================== */
+
+#define SCICLIENT_BOARDCFG { \
+ 0xc1d30100U, 0x235a0007U, 0x07120700U, 0x00010100U, \
+ 0x0005a5c3U, 0x08020c00U, 0x00000000U, 0x00000000U\
+} /* 29 bytes */
diff --git a/packages/ti/drv/sciclient/soc/V3/sciclient_defaultBoardcfg_pm.c b/packages/ti/drv/sciclient/soc/V3/sciclient_defaultBoardcfg_pm.c
--- /dev/null
@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2018-2020, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/**
+ * \file V0/sciclient_defaultBoardcfg.c
+ *
+ * \brief File containing the boardcfg default data structure to
+ * send TISCI_MSG_BOARD_CONFIG message.
+ *
+ */
+/* ========================================================================== */
+/* Include Files */
+/* ========================================================================== */
+
+#include <ti/drv/sciclient/soc/sysfw/include/am64x/tisci_hosts.h>
+#include <ti/drv/sciclient/soc/sysfw/include/am64x/tisci_boardcfg_constraints.h>
+#include <ti/drv/sciclient/soc/V3/sciclient_defaultBoardcfg.h>
+
+/* ========================================================================== */
+/* Global Variables */
+/* ========================================================================== */
+
+#if defined (BUILD_MCU1_0)
+struct tisci_boardcfg_pm {
+ struct tisci_boardcfg_abi_rev rev;
+} __attribute__((__packed__));
+
+const struct tisci_boardcfg_pm gBoardConfigLow_pm = {
+ /* boardcfg_abi_rev */
+ .rev =
+ {
+ .tisci_boardcfg_abi_maj = TISCI_BOARDCFG_RM_ABI_MAJ_VALUE,
+ .tisci_boardcfg_abi_min = TISCI_BOARDCFG_RM_ABI_MIN_VALUE
+ }
+};
+#endif
+
diff --git a/packages/ti/drv/sciclient/soc/V3/sciclient_defaultBoardcfg_pm_hex.h b/packages/ti/drv/sciclient/soc/V3/sciclient_defaultBoardcfg_pm_hex.h
--- /dev/null
@@ -0,0 +1,71 @@
+/*
+ * Copyright (C) 2018 Texas Instruments Incorporated
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the
+* distribution.
+*
+* Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*/
+
+/**
+* \file sciclient_defaultBoardcfg_pm_hex.h
+*
+* \brief File containing the Binary in a C array.
+*
+*/
+
+/* ========================================================================== */
+/* Include Files */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/* Macros & Typedefs */
+/* ========================================================================== */
+
+#define SCICLIENT_BOARDCFG_PM_SIZE_IN_BYTES (2U)
+
+/* ========================================================================== */
+/* Structure Declarations */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/* Function Declarations */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/* Global Variables */
+/* ========================================================================== */
+
+#define SCICLIENT_BOARDCFG_PM { \
+ 0x00000100U,\
+} /* 2 bytes */
diff --git a/packages/ti/drv/sciclient/soc/V3/sciclient_defaultBoardcfg_rm.c b/packages/ti/drv/sciclient/soc/V3/sciclient_defaultBoardcfg_rm.c
--- /dev/null
@@ -0,0 +1,922 @@
+/*
+ * Copyright (c) 2018, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/**
+ * \file V3/sciclient_defaultBoardcfg.c
+ *
+ * \brief File containing the boardcfg default data structure to
+ * send TISCI_MSG_BOARD_CONFIG message.
+ *
+ */
+/* ========================================================================== */
+/* Include Files */
+/* ========================================================================== */
+#include <ti/drv/sciclient/soc/V3/sciclient_defaultBoardcfg.h>
+
+/* ========================================================================== */
+/* Global Variables */
+/* ========================================================================== */
+
+#if defined (BUILD_MCU1_0)
+const struct tisci_local_rm_boardcfg gBoardConfigLow_rm
+__attribute__(( aligned(128), section(".boardcfg_data") )) =
+{
+ .rm_boardcfg = {
+ .rev = {
+ .tisci_boardcfg_abi_maj = 0x0,
+ .tisci_boardcfg_abi_min = 0x1,
+ },
+ .host_cfg = {
+ .subhdr = {
+ .magic = TISCI_BOARDCFG_RM_HOST_CFG_MAGIC_NUM,
+ .size = sizeof(struct tisci_boardcfg_rm_host_cfg),
+ },
+ .host_cfg_entries = {0},
+ },
+ .resasg = {
+ .subhdr = {
+ .magic = TISCI_BOARDCFG_RM_RESASG_MAGIC_NUM,
+ .size = sizeof(struct tisci_boardcfg_rm_resasg),
+ },
+ .resasg_entries_size = TISCI_RESASG_UTYPE_CNT * sizeof(struct tisci_boardcfg_rm_resasg_entry),
+ },
+ },
+ .resasg_entries = {
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_MCU_M4FSS0_CORE0, TISCI_RESASG_SUBTYPE_MCU_M4FSS0_CORE0_NVIC_IRQ_GROUP0_FROM_MCU_MCU_GPIOMUX_INTROUTER0),
+ .start_resource = 0U,
+ .num_resource = 4U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_MCU_M4FSS0_CORE0, TISCI_RESASG_SUBTYPE_MCU_M4FSS0_CORE0_NVIC_IRQ_GROUP0_FROM_DMASS0_INTAGGR_0),
+ .start_resource = 32U,
+ .num_resource = 16U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_CPSW0, TISCI_RESASG_SUBTYPE_CPSW0_CPTS_HW1_PUSH_IRQ_GROUP0_FROM_TIMESYNC_EVENT_INTROUTER0),
+ .start_resource = 0U,
+ .num_resource = 1U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_CPSW0, TISCI_RESASG_SUBTYPE_CPSW0_CPTS_HW2_PUSH_IRQ_GROUP0_FROM_TIMESYNC_EVENT_INTROUTER0),
+ .start_resource = 1U,
+ .num_resource = 1U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_CPSW0, TISCI_RESASG_SUBTYPE_CPSW0_CPTS_HW3_PUSH_IRQ_GROUP0_FROM_TIMESYNC_EVENT_INTROUTER0),
+ .start_resource = 2U,
+ .num_resource = 1U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_CPSW0, TISCI_RESASG_SUBTYPE_CPSW0_CPTS_HW4_PUSH_IRQ_GROUP0_FROM_TIMESYNC_EVENT_INTROUTER0),
+ .start_resource = 3U,
+ .num_resource = 1U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_CPSW0, TISCI_RESASG_SUBTYPE_CPSW0_CPTS_HW5_PUSH_IRQ_GROUP0_FROM_TIMESYNC_EVENT_INTROUTER0),
+ .start_resource = 4U,
+ .num_resource = 1U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_CPSW0, TISCI_RESASG_SUBTYPE_CPSW0_CPTS_HW6_PUSH_IRQ_GROUP0_FROM_TIMESYNC_EVENT_INTROUTER0),
+ .start_resource = 5U,
+ .num_resource = 1U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_CPSW0, TISCI_RESASG_SUBTYPE_CPSW0_CPTS_HW7_PUSH_IRQ_GROUP0_FROM_TIMESYNC_EVENT_INTROUTER0),
+ .start_resource = 6U,
+ .num_resource = 1U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_CPSW0, TISCI_RESASG_SUBTYPE_CPSW0_CPTS_HW8_PUSH_IRQ_GROUP0_FROM_TIMESYNC_EVENT_INTROUTER0),
+ .start_resource = 7U,
+ .num_resource = 1U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_RA_ERROR_OES),
+ .start_resource = 0U,
+ .num_resource = 1U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_GLOBAL_EVENT_TRIGGER),
+ .start_resource = 50176U,
+ .num_resource = 136U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_UDMAP_GLOBAL_CONFIG),
+ .start_resource = 0U,
+ .num_resource = 1U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_RING_BLOCK_COPY_CHAN),
+ .start_resource = 0U,
+ .num_resource = 28U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_RX_CHAN),
+ .start_resource = 48U,
+ .num_resource = 20U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_RING_SPLIT_TR_TX_CHAN),
+ .start_resource = 28U,
+ .num_resource = 20U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_BLOCK_COPY_CHAN),
+ .start_resource = 0U,
+ .num_resource = 28U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_SPLIT_TR_RX_CHAN),
+ .start_resource = 0U,
+ .num_resource = 20U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_BCDMA_0, TISCI_RESASG_SUBTYPE_BCDMA_SPLIT_TR_TX_CHAN),
+ .start_resource = 0U,
+ .num_resource = 20U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_INTAGGR_0, TISCI_RESASG_SUBTYPE_DMASS0_INTAGGR_0_INTAGGR_LEVI_PEND_IRQ_GROUP0_FROM_CMP_EVENT_INTROUTER0),
+ .start_resource = 0U,
+ .num_resource = 8U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_INTAGGR_0, TISCI_RESASG_SUBTYPE_DMASS0_INTAGGR_0_INTAGGR_LEVI_PEND_IRQ_GROUP0_FROM_TIMESYNC_EVENT_INTROUTER0),
+ .start_resource = 8U,
+ .num_resource = 8U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_INTAGGR_0, TISCI_RESASG_SUBTYPE_DMASS0_INTAGGR_0_INTAGGR_LEVI_PEND_IRQ_GROUP0_FROM_MAIN_GPIOMUX_INTROUTER0),
+ .start_resource = 16U,
+ .num_resource = 8U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_INTAGGR_0, TISCI_RESASG_SUBTYPE_DMASS0_INTAGGR_0_INTAGGR_LEVI_PEND_IRQ_GROUP1_FROM_MAIN_GPIOMUX_INTROUTER0),
+ .start_resource = 24U,
+ .num_resource = 2U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_INTAGGR_0, TISCI_RESASG_SUBTYPE_GLOBAL_EVENT_SEVT),
+ .start_resource = 15U,
+ .num_resource = 1521U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_INTAGGR_0, TISCI_RESASG_SUBTYPE_IA_VINT_TO_GICSS0),
+ .start_resource = 4U,
+ .num_resource = 36U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_INTAGGR_0, TISCI_RESASG_SUBTYPE_IA_VINT_TO_R5FSS0_CORE0_AND_R5FSS0_CORE1),
+ .start_resource = 44U,
+ .num_resource = 28U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_INTAGGR_0, TISCI_RESASG_SUBTYPE_IA_VINT_TO_R5FSS0_CORE0),
+ .start_resource = 72U,
+ .num_resource = 8U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_INTAGGR_0, TISCI_RESASG_SUBTYPE_IA_VINT_TO_R5FSS0_CORE1),
+ .start_resource = 80U,
+ .num_resource = 8U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_INTAGGR_0, TISCI_RESASG_SUBTYPE_IA_VINT_TO_R5FSS1_CORE0_AND_R5FSS1_CORE1),
+ .start_resource = 92U,
+ .num_resource = 28U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_INTAGGR_0, TISCI_RESASG_SUBTYPE_IA_VINT_TO_R5FSS1_CORE0),
+ .start_resource = 120U,
+ .num_resource = 8U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_INTAGGR_0, TISCI_RESASG_SUBTYPE_IA_VINT_TO_R5FSS1_CORE1),
+ .start_resource = 128U,
+ .num_resource = 8U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_INTAGGR_0, TISCI_RESASG_SUBTYPE_IA_VINT_TO_PRU_ICSSG0),
+ .start_resource = 152U,
+ .num_resource = 8U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_INTAGGR_0, TISCI_RESASG_SUBTYPE_IA_VINT_TO_PRU_ICSSG1),
+ .start_resource = 160U,
+ .num_resource = 8U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_INTAGGR_0, TISCI_RESASG_SUBTYPE_IA_VINT_TO_MCU_M4FSS0_CORE0),
+ .start_resource = 168U,
+ .num_resource = 16U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_INTAGGR_0, TISCI_RESASG_SUBTYPE_IA_TIMERMGR_EVT_OES),
+ .start_resource = 0U,
+ .num_resource = 1024U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_INTAGGR_0, TISCI_RESASG_SUBTYPE_IA_PKTDMA_TX_CHAN_ERROR_OES),
+ .start_resource = 4096U,
+ .num_resource = 42U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_INTAGGR_0, TISCI_RESASG_SUBTYPE_IA_PKTDMA_TX_FLOW_COMPLETION_OES),
+ .start_resource = 4608U,
+ .num_resource = 112U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_INTAGGR_0, TISCI_RESASG_SUBTYPE_IA_PKTDMA_RX_CHAN_ERROR_OES),
+ .start_resource = 5120U,
+ .num_resource = 29U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_INTAGGR_0, TISCI_RESASG_SUBTYPE_IA_PKTDMA_RX_FLOW_COMPLETION_OES),
+ .start_resource = 5632U,
+ .num_resource = 176U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_INTAGGR_0, TISCI_RESASG_SUBTYPE_IA_PKTDMA_RX_FLOW_STARVATION_OES),
+ .start_resource = 6144U,
+ .num_resource = 176U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_INTAGGR_0, TISCI_RESASG_SUBTYPE_IA_PKTDMA_RX_FLOW_FIREWALL_OES),
+ .start_resource = 6656U,
+ .num_resource = 176U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_INTAGGR_0, TISCI_RESASG_SUBTYPE_IA_BCDMA_CHAN_ERROR_OES),
+ .start_resource = 8192U,
+ .num_resource = 28U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_INTAGGR_0, TISCI_RESASG_SUBTYPE_IA_BCDMA_CHAN_DATA_COMPLETION_OES),
+ .start_resource = 8704U,
+ .num_resource = 28U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_INTAGGR_0, TISCI_RESASG_SUBTYPE_IA_BCDMA_CHAN_RING_COMPLETION_OES),
+ .start_resource = 9216U,
+ .num_resource = 28U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_INTAGGR_0, TISCI_RESASG_SUBTYPE_IA_BCDMA_TX_CHAN_ERROR_OES),
+ .start_resource = 9728U,
+ .num_resource = 20U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_INTAGGR_0, TISCI_RESASG_SUBTYPE_IA_BCDMA_TX_CHAN_DATA_COMPLETION_OES),
+ .start_resource = 10240U,
+ .num_resource = 20U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_INTAGGR_0, TISCI_RESASG_SUBTYPE_IA_BCDMA_TX_CHAN_RING_COMPLETION_OES),
+ .start_resource = 10752U,
+ .num_resource = 20U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_INTAGGR_0, TISCI_RESASG_SUBTYPE_IA_BCDMA_RX_CHAN_ERROR_OES),
+ .start_resource = 11264U,
+ .num_resource = 20U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_INTAGGR_0, TISCI_RESASG_SUBTYPE_IA_BCDMA_RX_CHAN_DATA_COMPLETION_OES),
+ .start_resource = 11776U,
+ .num_resource = 20U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_INTAGGR_0, TISCI_RESASG_SUBTYPE_IA_BCDMA_RX_CHAN_RING_COMPLETION_OES),
+ .start_resource = 12288U,
+ .num_resource = 20U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_RA_ERROR_OES),
+ .start_resource = 0U,
+ .num_resource = 1U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_UDMAP_GLOBAL_CONFIG),
+ .start_resource = 0U,
+ .num_resource = 1U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_TX_CHAN),
+ .start_resource = 0U,
+ .num_resource = 16U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_RING_CPSW_TX_CHAN),
+ .start_resource = 16U,
+ .num_resource = 64U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_RING_SAUL_TX_0_CHAN),
+ .start_resource = 80U,
+ .num_resource = 8U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_RING_SAUL_TX_1_CHAN),
+ .start_resource = 88U,
+ .num_resource = 8U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_RING_ICSSG_0_TX_CHAN),
+ .start_resource = 96U,
+ .num_resource = 8U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_RING_ICSSG_1_TX_CHAN),
+ .start_resource = 104U,
+ .num_resource = 8U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_RING_UNMAPPED_RX_CHAN),
+ .start_resource = 112U,
+ .num_resource = 16U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_RING_CPSW_RX_CHAN),
+ .start_resource = 128U,
+ .num_resource = 16U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_RING_SAUL_RX_0_CHAN),
+ .start_resource = 144U,
+ .num_resource = 8U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_RING_SAUL_RX_1_CHAN),
+ .start_resource = 144U,
+ .num_resource = 8U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_RING_SAUL_RX_2_CHAN),
+ .start_resource = 152U,
+ .num_resource = 8U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_RING_SAUL_RX_3_CHAN),
+ .start_resource = 152U,
+ .num_resource = 8U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_RING_ICSSG_0_RX_CHAN),
+ .start_resource = 160U,
+ .num_resource = 64U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_RING_ICSSG_1_RX_CHAN),
+ .start_resource = 224U,
+ .num_resource = 64U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_UNMAPPED_TX_CHAN),
+ .start_resource = 0U,
+ .num_resource = 16U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_CPSW_TX_CHAN),
+ .start_resource = 16U,
+ .num_resource = 8U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_SAUL_TX_0_CHAN),
+ .start_resource = 24U,
+ .num_resource = 1U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_SAUL_TX_1_CHAN),
+ .start_resource = 25U,
+ .num_resource = 1U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_ICSSG_0_TX_CHAN),
+ .start_resource = 26U,
+ .num_resource = 8U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_ICSSG_1_TX_CHAN),
+ .start_resource = 34U,
+ .num_resource = 8U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_UNMAPPED_RX_CHAN),
+ .start_resource = 0U,
+ .num_resource = 16U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_FLOW_UNMAPPED_RX_CHAN),
+ .start_resource = 0U,
+ .num_resource = 16U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_CPSW_RX_CHAN),
+ .start_resource = 16U,
+ .num_resource = 1U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_FLOW_CPSW_RX_CHAN),
+ .start_resource = 16U,
+ .num_resource = 16U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_SAUL_RX_0_CHAN),
+ .start_resource = 17U,
+ .num_resource = 1U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_FLOW_SAUL_RX_0_CHAN),
+ .start_resource = 32U,
+ .num_resource = 8U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_SAUL_RX_1_CHAN),
+ .start_resource = 18U,
+ .num_resource = 1U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_FLOW_SAUL_RX_1_CHAN),
+ .start_resource = 32U,
+ .num_resource = 8U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_SAUL_RX_2_CHAN),
+ .start_resource = 19U,
+ .num_resource = 1U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_FLOW_SAUL_RX_2_CHAN),
+ .start_resource = 40U,
+ .num_resource = 8U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_SAUL_RX_3_CHAN),
+ .start_resource = 20U,
+ .num_resource = 1U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_FLOW_SAUL_RX_3_CHAN),
+ .start_resource = 40U,
+ .num_resource = 8U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_ICSSG_0_RX_CHAN),
+ .start_resource = 21U,
+ .num_resource = 4U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_FLOW_ICSSG_0_RX_CHAN),
+ .start_resource = 48U,
+ .num_resource = 64U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_ICSSG_1_RX_CHAN),
+ .start_resource = 25U,
+ .num_resource = 4U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_FLOW_ICSSG_1_RX_CHAN),
+ .start_resource = 112U,
+ .num_resource = 64U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_ERROR_OES),
+ .start_resource = 0U,
+ .num_resource = 1U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_VIRTID),
+ .start_resource = 64U,
+ .num_resource = 64U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_DMASS0_RINGACC_0, TISCI_RESASG_SUBTYPE_RA_GENERIC_IPC),
+ .start_resource = 20U,
+ .num_resource = 12U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_MCU_ESM0, TISCI_RESASG_SUBTYPE_MCU_ESM0_ESM_PLS_EVENT0_IRQ_GROUP0_FROM_MCU_MCU_GPIOMUX_INTROUTER0),
+ .start_resource = 88U,
+ .num_resource = 4U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_MCU_ESM0, TISCI_RESASG_SUBTYPE_MCU_ESM0_ESM_PLS_EVENT1_IRQ_GROUP0_FROM_MCU_MCU_GPIOMUX_INTROUTER0),
+ .start_resource = 92U,
+ .num_resource = 4U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_MCU_ESM0, TISCI_RESASG_SUBTYPE_MCU_ESM0_ESM_PLS_EVENT2_IRQ_GROUP0_FROM_MCU_MCU_GPIOMUX_INTROUTER0),
+ .start_resource = 96U,
+ .num_resource = 4U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_GICSS0, TISCI_RESASG_SUBTYPE_GICSS0_SPI_IRQ_GROUP0_FROM_MAIN_GPIOMUX_INTROUTER0),
+ .start_resource = 32U,
+ .num_resource = 16U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_GICSS0, TISCI_RESASG_SUBTYPE_GICSS0_SPI_IRQ_GROUP0_FROM_CMP_EVENT_INTROUTER0),
+ .start_resource = 48U,
+ .num_resource = 16U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_GICSS0, TISCI_RESASG_SUBTYPE_GICSS0_SPI_IRQ_GROUP0_FROM_DMASS0_INTAGGR_0),
+ .start_resource = 68U,
+ .num_resource = 36U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_GICSS0, TISCI_RESASG_SUBTYPE_GICSS0_SPI_IRQ_GROUP0_FROM_MCU_MCU_GPIOMUX_INTROUTER0),
+ .start_resource = 104U,
+ .num_resource = 4U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_PRU_ICSSG0, TISCI_RESASG_SUBTYPE_PRU_ICSSG0_PR1_EDC0_LATCH0_IN_IRQ_GROUP0_FROM_TIMESYNC_EVENT_INTROUTER0),
+ .start_resource = 0U,
+ .num_resource = 1U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_PRU_ICSSG0, TISCI_RESASG_SUBTYPE_PRU_ICSSG0_PR1_EDC0_LATCH1_IN_IRQ_GROUP0_FROM_TIMESYNC_EVENT_INTROUTER0),
+ .start_resource = 1U,
+ .num_resource = 1U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_PRU_ICSSG0, TISCI_RESASG_SUBTYPE_PRU_ICSSG0_PR1_EDC1_LATCH0_IN_IRQ_GROUP0_FROM_TIMESYNC_EVENT_INTROUTER0),
+ .start_resource = 2U,
+ .num_resource = 1U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_PRU_ICSSG0, TISCI_RESASG_SUBTYPE_PRU_ICSSG0_PR1_EDC1_LATCH1_IN_IRQ_GROUP0_FROM_TIMESYNC_EVENT_INTROUTER0),
+ .start_resource = 3U,
+ .num_resource = 1U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_PRU_ICSSG0, TISCI_RESASG_SUBTYPE_PRU_ICSSG0_PR1_IEP0_CAP_INTR_REQ_IRQ_GROUP0_FROM_MAIN_GPIOMUX_INTROUTER0),
+ .start_resource = 4U,
+ .num_resource = 6U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_PRU_ICSSG0, TISCI_RESASG_SUBTYPE_PRU_ICSSG0_PR1_IEP1_CAP_INTR_REQ_IRQ_GROUP0_FROM_MAIN_GPIOMUX_INTROUTER0),
+ .start_resource = 10U,
+ .num_resource = 6U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_PRU_ICSSG0, TISCI_RESASG_SUBTYPE_PRU_ICSSG0_PR1_SLV_INTR_IRQ_GROUP0_FROM_DMASS0_INTAGGR_0),
+ .start_resource = 16U,
+ .num_resource = 8U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_PRU_ICSSG0, TISCI_RESASG_SUBTYPE_PRU_ICSSG0_PR1_SLV_INTR_IRQ_GROUP0_FROM_MAIN_GPIOMUX_INTROUTER0),
+ .start_resource = 46U,
+ .num_resource = 8U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_PRU_ICSSG1, TISCI_RESASG_SUBTYPE_PRU_ICSSG1_PR1_EDC0_LATCH0_IN_IRQ_GROUP0_FROM_TIMESYNC_EVENT_INTROUTER0),
+ .start_resource = 0U,
+ .num_resource = 1U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_PRU_ICSSG1, TISCI_RESASG_SUBTYPE_PRU_ICSSG1_PR1_EDC0_LATCH1_IN_IRQ_GROUP0_FROM_TIMESYNC_EVENT_INTROUTER0),
+ .start_resource = 1U,
+ .num_resource = 1U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_PRU_ICSSG1, TISCI_RESASG_SUBTYPE_PRU_ICSSG1_PR1_EDC1_LATCH0_IN_IRQ_GROUP0_FROM_TIMESYNC_EVENT_INTROUTER0),
+ .start_resource = 2U,
+ .num_resource = 1U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_PRU_ICSSG1, TISCI_RESASG_SUBTYPE_PRU_ICSSG1_PR1_EDC1_LATCH1_IN_IRQ_GROUP0_FROM_TIMESYNC_EVENT_INTROUTER0),
+ .start_resource = 3U,
+ .num_resource = 1U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ .type = TISCI_RESASG_UTYPE(TISCI_DEV_PRU_ICSSG1, TISCI_RESASG_SUBTYPE_PRU_ICSSG1_PR1_IEP0_CAP_INTR_REQ_IRQ_GROUP0_FROM_MAIN_GPIOMUX_INTROUTER0),
+ .start_resource = 4U,
+ .num_resource = 6U,
+ .host_id = TISCI_HOST_ID_ALL,
+ },
+ {
+ &