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raw | patch | inline | side by side (parent: 923ecc5)
raw | patch | inline | side by side (parent: 923ecc5)
author | Badri S <badri@ti.com> | |
Sun, 11 Oct 2020 13:38:54 +0000 (19:08 +0530) | ||
committer | Sivaraj R <sivaraj@ti.com> | |
Sat, 31 Oct 2020 04:09:46 +0000 (23:09 -0500) |
Support timeout for UART SBL mode for TPR12.
Also move the module clock init out of SBL lib
to SBL image and moved it board folder
Signed-off-by: Badri S <badri@ti.com>
Also move the module clock init out of SBL lib
to SBL image and moved it board folder
Signed-off-by: Badri S <badri@ti.com>
diff --git a/packages/ti/boot/sbl/board/evmTPR12/sbl_main.c b/packages/ti/boot/sbl/board/evmTPR12/sbl_main.c
index 838481ee54f0bf8f82c30b512f053fd9446aa707..40cc0a5dbf8852980f0f0939a7375ca36ba9c2e0 100644 (file)
{
UART_HwAttrs uart_cfg;
UART_Params uartPrms;
+ Rcm_Return retVal;
UART_socGetInitCfg(BOARD_UART_INSTANCE, &uart_cfg);
/* Use UART fclk freq setup by ROM */
- uart_cfg.clockFrequency = SBL_RcmGetPeripheralClockFrequency(Rcm_PeripheralClockSource_SYS_CLK);
+ retVal = SBL_RcmGetPeripheralFreq(Rcm_PeripheralId_MSS_SCIA, &uart_cfg.clockFrequency);
+ DebugP_assert(retVal == Rcm_Return_SUCCESS);
/* Disable the UART interrupt */
uart_cfg.enableInterrupt = FALSE;
/* Disable the DMA mode for UART */
diff --git a/packages/ti/boot/sbl/board/evmTPR12/sbl_module_clock_config.c b/packages/ti/boot/sbl/board/evmTPR12/sbl_module_clock_config.c
--- /dev/null
@@ -0,0 +1,301 @@
+/*
+ * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include <ti/osal/DebugP.h>
+#include "sbl_soc.h"
+#include "sbl_soc_cfg.h"
+#include "sbl_rcm.h"
+
+
+/**
+ * @brief
+ * Peripheral Clock config
+ *
+ */
+typedef struct Sbl_ModuleClockConfig_s
+{
+ Rcm_PeripheralId peripheralId;
+ Rcm_PeripheralClockSource clkSource;
+ uint32_t freqHz;
+} Sbl_ModuleClockConfig;
+
+static const Sbl_ModuleClockConfig SBLModuleClockCfgTbl[] =
+{
+ /* Generate 96 MHz CSIRX Control Clock */
+ //HW_WR_REG32(CSL_MSS_TOPRCM_U_BASE+CSIRX_CLK_SRC_SEL, 0x222);
+ //HW_WR_REG32(CSL_MSS_TOPRCM_U_BASE+CSIRX_DIV_VAL, 0x000);
+ {
+ .peripheralId = Rcm_PeripheralId_CSIRX,
+ .clkSource = Rcm_PeripheralClockSource_DPLL_PER_HSDIV0_CLKOUT2,
+ .freqHz = SBL_CSIRX_FREQ_HZ,
+ },
+ //HW_WR_REG32(CSL_MSS_RCM_U_BASE+MSS_MCANA_CLK_DIV_VAL, 0x444); //MSS_MCANA_CLK_DIV_VAL_CLKDIVR = 0x444; 400/5
+ //HW_WR_REG32(CSL_MSS_RCM_U_BASE+MSS_MCANA_CLK_SRC_SEL, 0x444); //MSS_MCANA_CLK_SRC_SEL_CLKSRCSEL = 0x222;
+ {
+ .peripheralId = Rcm_PeripheralId_MSS_MCANA,
+ .clkSource = Rcm_PeripheralClockSource_DPLL_CORE_HSDIV0_CLKOUT2,
+ .freqHz = SBL_MCANA_FREQ_HZ,
+ },
+ //HW_WR_REG32(CSL_MSS_RCM_U_BASE+MSS_MCANB_CLK_DIV_VAL, 0x444); //MSS_MCANB_CLK_DIV_VAL_CLKDIVR = 0x444;
+ //HW_WR_REG32(CSL_MSS_RCM_U_BASE+MSS_MCANB_CLK_SRC_SEL, 0x444); //MSS_MCANB_CLK_SRC_SEL_CLKSRCSEL = 0x222;
+ {
+ .peripheralId = Rcm_PeripheralId_MSS_MCANB,
+ .clkSource = Rcm_PeripheralClockSource_DPLL_CORE_HSDIV0_CLKOUT2,
+ .freqHz = SBL_MCANB_FREQ_HZ,
+ },
+ //HW_WR_REG32(CSL_MSS_RCM_U_BASE+MSS_RTIA_CLK_DIV_VAL, 0x000); //MSS_RTIA_CLK_DIV_VAL_CLKDIVR = 0x444; 200/1
+ //HW_WR_REG32(CSL_MSS_RCM_U_BASE+MSS_RTIA_CLK_SRC_SEL, 0x222); //MSS_RTIA_CLK_SRC_SEL_CLKSRCSEL = 0x222;
+ {
+ .peripheralId = Rcm_PeripheralId_MSS_RTIA,
+ .clkSource = Rcm_PeripheralClockSource_SYS_CLK,
+ .freqHz = SBL_MSS_RTIA_FREQ_HZ,
+ },
+ //HW_WR_REG32(CSL_MSS_RCM_U_BASE+MSS_RTIB_CLK_DIV_VAL, 0x000); //MSS_RTIB_CLK_DIV_VAL_CLKDIVR = 0x444;
+ //HW_WR_REG32(CSL_MSS_RCM_U_BASE+MSS_RTIB_CLK_SRC_SEL, 0x222); //MSS_RTIB_CLK_SRC_SEL_CLKSRCSEL = 0x222;
+ {
+ .peripheralId = Rcm_PeripheralId_MSS_RTIB,
+ .clkSource = Rcm_PeripheralClockSource_SYS_CLK,
+ .freqHz = SBL_MSS_RTIB_FREQ_HZ,
+ },
+ //HW_WR_REG32(CSL_MSS_RCM_U_BASE+MSS_RTIC_CLK_DIV_VAL, 0x000); //MSS_RTIC_CLK_DIV_VAL_CLKDIVR = 0x444;
+ //HW_WR_REG32(CSL_MSS_RCM_U_BASE+MSS_RTIC_CLK_SRC_SEL, 0x222); //MSS_RTIC_CLK_SRC_SEL_CLKSRCSEL = 0x222;
+ {
+ .peripheralId = Rcm_PeripheralId_MSS_RTIC,
+ .clkSource = Rcm_PeripheralClockSource_SYS_CLK,
+ .freqHz = SBL_MSS_RTIC_FREQ_HZ,
+ },
+ //HW_WR_REG32(CSL_MSS_RCM_U_BASE+MSS_WDT_CLK_DIV_VAL, 0x000); //MSS_WDT_CLK_DIV_VAL_CLKDIVR = 0x444;
+ //HW_WR_REG32(CSL_MSS_RCM_U_BASE+MSS_WDT_CLK_SRC_SEL, 0x222); //MSS_WDT_CLK_SRC_SEL_CLKSRCSEL = 0x222;
+ {
+ .peripheralId = Rcm_PeripheralId_MSS_WDT,
+ .clkSource = Rcm_PeripheralClockSource_SYS_CLK,
+ .freqHz = SBL_MSS_WDT_FREQ_HZ,
+ },
+ //HW_WR_REG32(CSL_MSS_RCM_U_BASE+MSS_QSPI_CLK_DIV_VAL, 0x444); //MSS_QSPI_CLK_DIV_VAL_CLKDIVR = 0x444; 400/5
+ //HW_WR_REG32(CSL_MSS_RCM_U_BASE+MSS_QSPI_CLK_SRC_SEL, 0x444); //MSS_QSPI_CLK_SRC_SEL_CLKSRCSEL = 0x444;
+ {
+ .peripheralId = Rcm_PeripheralId_MSS_QSPI,
+ .clkSource = Rcm_PeripheralClockSource_DPLL_CORE_HSDIV0_CLKOUT2,
+ .freqHz = SBL_QSPI_FREQ_HZ,
+ },
+ //HW_WR_REG32(CSL_MSS_RCM_U_BASE+MSS_SPIA_CLK_DIV_VAL, 0x000); //MSS_SPIA_CLK_DIV_VAL_CLKDIVR = 0x000; 200/1
+ //HW_WR_REG32(CSL_MSS_RCM_U_BASE+MSS_SPIA_CLK_SRC_SEL, 0x222); //MSS_SPIA_CLK_SRC_SEL_CLKSRCSEL = 0x222;
+ {
+ .peripheralId = Rcm_PeripheralId_MSS_SPIA,
+ .clkSource = Rcm_PeripheralClockSource_SYS_CLK,
+ .freqHz = SBL_MSS_SPIA_FREQ_HZ,
+ },
+ //HW_WR_REG32(CSL_MSS_RCM_U_BASE+MSS_SPIB_CLK_SRC_SEL, 0x222); //MSS_SPIB_CLK_SRC_SEL_CLKSRCSEL = 0x222;
+ //HW_WR_REG32(CSL_MSS_RCM_U_BASE+MSS_SPIB_CLK_DIV_VAL, 0x000); //MSS_SPIB_CLK_DIV_VAL_CLKDIVR = 0x000;
+ {
+ .peripheralId = Rcm_PeripheralId_MSS_SPIB,
+ .clkSource = Rcm_PeripheralClockSource_SYS_CLK,
+ .freqHz = SBL_MSS_SPIB_FREQ_HZ,
+ },
+ //HW_WR_REG32(CSL_MSS_RCM_U_BASE+MSS_I2C_CLK_DIV_VAL, 0x000); //MSS_I2C_CLK_DIV_VAL_CLKDIVR = 0x000; 200/1
+ //HW_WR_REG32(CSL_MSS_RCM_U_BASE+MSS_I2C_CLK_SRC_SEL, 0x222); //MSS_I2C_CLK_SRC_SEL_CLKSRCSEL = 0x222;
+ {
+ .peripheralId = Rcm_PeripheralId_MSS_I2C,
+ .clkSource = Rcm_PeripheralClockSource_SYS_CLK,
+ .freqHz = SBL_MSS_I2C_FREQ_HZ,
+ },
+ //HW_WR_REG32(CSL_MSS_RCM_U_BASE+MSS_SCIA_CLK_DIV_VAL, 0x000); //MSS_SCIA_CLK_DIV_VAL_CLKDIVR = 0x000; 200/1
+ //HW_WR_REG32(CSL_MSS_RCM_U_BASE+MSS_SCIA_CLK_SRC_SEL, 0x222); //MSS_SCIA_CLK_SRC_SEL_CLKSRCSEL = 0x222;
+ {
+ .peripheralId = Rcm_PeripheralId_MSS_SCIA,
+ .clkSource = Rcm_PeripheralClockSource_SYS_CLK,
+ .freqHz = SBL_MSS_SCIA_FREQ_HZ,
+ },
+ //HW_WR_REG32(CSL_MSS_RCM_U_BASE+MSS_SCIB_CLK_DIV_VAL, 0x000); //MSS_SCIB_CLK_DIV_VAL_CLKDIVR = 0x000;
+ //HW_WR_REG32(CSL_MSS_RCM_U_BASE+MSS_SCIB_CLK_SRC_SEL, 0x222); //MSS_SCIB_CLK_SRC_SEL_CLKSRCSEL = 0x222;
+ {
+ .peripheralId = Rcm_PeripheralId_MSS_SCIB,
+ .clkSource = Rcm_PeripheralClockSource_SYS_CLK,
+ .freqHz = SBL_MSS_SCIB_FREQ_HZ,
+ },
+ //HW_WR_REG32(CSL_MSS_RCM_U_BASE+MSS_CPSW_CLK_DIV_VAL, 0x111); //MSS_CPSW_CLK_DIV_VAL_CLKDIVR = 0x000; 400/2
+ //HW_WR_REG32(CSL_MSS_RCM_U_BASE+MSS_CPSW_CLK_SRC_SEL, 0x444); //MSS_CPSW_CLK_SRC_SEL_CLKSRCSEL = 0x222;
+ {
+ .peripheralId = Rcm_PeripheralId_MSS_CPSW,
+ .clkSource = Rcm_PeripheralClockSource_DPLL_CORE_HSDIV0_CLKOUT2,
+ .freqHz = SBL_CPSW_FREQ_HZ,
+ },
+ //HW_WR_REG32(CSL_MSS_RCM_U_BASE+MSS_CPTS_CLK_DIV_VAL, 0x111); //MSS_CPTS_CLK_DIV_VAL_CLKDIVR = 0x000; 400/2
+ //HW_WR_REG32(CSL_MSS_RCM_U_BASE+MSS_CPTS_CLK_SRC_SEL, 0x444); //MSS_CPTS_CLK_SRC_SEL_CLKSRCSEL = 0x222;
+ {
+ .peripheralId = Rcm_PeripheralId_MSS_CPTS,
+ .clkSource = Rcm_PeripheralClockSource_DPLL_CORE_HSDIV0_CLKOUT2,
+ .freqHz = SBL_CPTS_FREQ_HZ,
+ },
+ //HW_WR_REG32(CSL_DSS_RCM_U_BASE+DSS_RTIA_CLK_DIV_VAL, 0x000); //DSS_RTIA_CLK_DIV_VAL_CLKDIVR = 0x444; 200/1
+ //HW_WR_REG32(CSL_DSS_RCM_U_BASE+DSS_RTIA_CLK_SRC_SEL, 0x222); //DSS_RTIA_CLK_SRC_SEL_CLKSRCSEL = 0x222;
+ {
+ .peripheralId = Rcm_PeripheralId_DSS_RTIA,
+ .clkSource = Rcm_PeripheralClockSource_SYS_CLK,
+ .freqHz = SBL_DSS_RTIA_FREQ_HZ,
+ },
+ //HW_WR_REG32(CSL_DSS_RCM_U_BASE+DSS_RTIB_CLK_DIV_VAL, 0x000); //DSS_RTIB_CLK_DIV_VAL_CLKDIVR = 0x444;
+ //HW_WR_REG32(CSL_DSS_RCM_U_BASE+DSS_RTIB_CLK_SRC_SEL, 0x222); //DSS_RTIB_CLK_SRC_SEL_CLKSRCSEL = 0x222;
+ {
+ .peripheralId = Rcm_PeripheralId_DSS_RTIB,
+ .clkSource = Rcm_PeripheralClockSource_SYS_CLK,
+ .freqHz = SBL_DSS_RTIB_FREQ_HZ,
+ },
+ //HW_WR_REG32(CSL_DSS_RCM_U_BASE+DSS_WDT_CLK_DIV_VAL, 0x000); //DSS_WDT_CLK_DIV_VAL_CLKDIVR = 0x444;
+ //HW_WR_REG32(CSL_DSS_RCM_U_BASE+DSS_WDT_CLK_SRC_SEL, 0x222); //DSS_WDT_CLK_SRC_SEL_CLKSRCSEL = 0x222;
+ {
+ .peripheralId = Rcm_PeripheralId_DSS_WDT,
+ .clkSource = Rcm_PeripheralClockSource_SYS_CLK,
+ .freqHz = SBL_DSS_WDT_FREQ_HZ,
+ },
+ //HW_WR_REG32(CSL_DSS_RCM_U_BASE+DSS_SCIA_CLK_DIV_VAL, 0x000); //DSS_SCIA_CLK_DIV_VAL_CLKDIVR = 0x000; 200/1
+ //HW_WR_REG32(CSL_DSS_RCM_U_BASE+DSS_SCIA_CLK_SRC_SEL, 0x222); //DSS_SCIA_CLK_SRC_SEL_CLKSRCSEL = 0x222;
+ {
+ .peripheralId = Rcm_PeripheralId_DSS_SCIA,
+ .clkSource = Rcm_PeripheralClockSource_SYS_CLK,
+ .freqHz = SBL_DSS_SCIA_FREQ_HZ,
+ },
+ //HW_WR_REG32(CSL_RCSS_RCM_U_BASE+RCSS_SPIA_CLK_DIV_VAL, 0x000); //RCSS_SPIA_CLK_DIV_VAL_CLKDIVR = 0x000; 200/1
+ //HW_WR_REG32(CSL_RCSS_RCM_U_BASE+RCSS_SPIA_CLK_SRC_SEL, 0x222); //RCSS_SPIA_CLK_SRC_SEL_CLKSRCSEL = 0x222;
+ {
+ .peripheralId = Rcm_PeripheralId_RCSS_SCIA,
+ .clkSource = Rcm_PeripheralClockSource_SYS_CLK,
+ .freqHz = SBL_RCSS_SCIA_FREQ_HZ,
+ },
+ //HW_WR_REG32(CSL_RCSS_RCM_U_BASE+RCSS_SPIA_CLK_DIV_VAL, 0x000); //RCSS_SPIA_CLK_DIV_VAL_CLKDIVR = 0x000; 200/1
+ //HW_WR_REG32(CSL_RCSS_RCM_U_BASE+RCSS_SPIA_CLK_SRC_SEL, 0x222); //RCSS_SPIA_CLK_SRC_SEL_CLKSRCSEL = 0x222;
+ {
+ .peripheralId = Rcm_PeripheralId_RCSS_SPIA,
+ .clkSource = Rcm_PeripheralClockSource_SYS_CLK,
+ .freqHz = SBL_RCSS_SPIA_FREQ_HZ,
+ },
+ //HW_WR_REG32(CSL_RCSS_RCM_U_BASE+RCSS_SPIB_CLK_DIV_VAL, 0x000); //RCSS_SPIB_CLK_DIV_VAL_CLKDIVR = 0x000; 200/1
+ //HW_WR_REG32(CSL_RCSS_RCM_U_BASE+RCSS_SPIB_CLK_SRC_SEL, 0x222); //RCSS_SPIB_CLK_SRC_SEL_CLKSRCSEL = 0x222;
+ {
+ .peripheralId = Rcm_PeripheralId_RCSS_SPIB,
+ .clkSource = Rcm_PeripheralClockSource_SYS_CLK,
+ .freqHz = SBL_RCSS_SPIB_FREQ_HZ,
+ },
+ //HW_WR_REG32(CSL_RCSS_RCM_U_BASE+RCSS_I2CA_CLK_DIV_VAL, 0x000); //RCSS_I2CA_CLK_DIV_VAL_CLKDIVR = 0x000; 200/1
+ //HW_WR_REG32(CSL_RCSS_RCM_U_BASE+RCSS_I2CA_CLK_SRC_SEL, 0x222); //RCSS_I2CA_CLK_SRC_SEL_CLKSRCSEL = 0x222;
+ {
+ .peripheralId = Rcm_PeripheralId_RCSS_I2CA,
+ .clkSource = Rcm_PeripheralClockSource_SYS_CLK,
+ .freqHz = SBL_RCSS_I2CA_FREQ_HZ,
+ },
+ //HW_WR_REG32(CSL_RCSS_RCM_U_BASE+RCSS_I2CB_CLK_DIV_VAL, 0x000); //RCSS_I2CB_CLK_DIV_VAL_CLKDIVR = 0x000; 200/1
+ //HW_WR_REG32(CSL_RCSS_RCM_U_BASE+RCSS_I2CB_CLK_SRC_SEL, 0x222); //RCSS_I2CB_CLK_SRC_SEL_CLKSRCSEL = 0x222;
+ {
+ .peripheralId = Rcm_PeripheralId_RCSS_I2CB,
+ .clkSource = Rcm_PeripheralClockSource_SYS_CLK,
+ .freqHz = SBL_RCSS_I2CB_FREQ_HZ,
+ },
+ //HW_WR_REG32(CSL_RCSS_RCM_U_BASE+RCSS_ATL_CLK_DIV_VAL, 0x111); //RCSS_ATL_CLK_DIV_VAL_CLKDIVR = 0x000; 240/2
+ //HW_WR_REG32(CSL_RCSS_RCM_U_BASE+RCSS_ATL_CLK_SRC_SEL, 0x666); //RCSS_ATL_CLK_SRC_SEL_CLKSRCSEL = 0x222;
+ {
+ .peripheralId = Rcm_PeripheralId_RCSS_ATL,
+ .clkSource = Rcm_PeripheralClockSource_DPLL_PER_HSDIV0_CLKOUT3,
+ .freqHz = SBL_RCSS_ATL_FREQ_HZ,
+ },
+ //HW_WR_REG32(CSL_RCSS_RCM_U_BASE+RCSS_MCASPA_AUX_CLK_DIV_VAL, 0x111); //RCSS_MCASPA_AUX_CLK_DIV_VAL_CLKDIVR = 0x111; 192/2
+ //HW_WR_REG32(CSL_RCSS_RCM_U_BASE+RCSS_MCASPA_AUX_CLK_SRC_SEL, 0x222); //RCSS_MCASPA_AUX_CLK_SRC_SEL_CLKSRCSEL = 0x222;
+ {
+ .peripheralId = Rcm_PeripheralId_RCSS_MCASPA_AUX,
+ .clkSource = Rcm_PeripheralClockSource_DPLL_PER_HSDIV0_CLKOUT1,
+ .freqHz = SBL_RCSS_MCASPA_AUX_FREQ_HZ,
+ },
+ //HW_WR_REG32(CSL_RCSS_RCM_U_BASE+RCSS_MCASPB_AUX_CLK_DIV_VAL, 0x111); //RCSS_MCASPB_AUX_CLK_DIV_VAL_CLKDIVR = 0x111; 192/2
+ //HW_WR_REG32(CSL_RCSS_RCM_U_BASE+RCSS_MCASPB_AUX_CLK_SRC_SEL, 0x222); //RCSS_MCASPB_AUX_CLK_SRC_SEL_CLKSRCSEL = 0x222;
+ {
+ .peripheralId = Rcm_PeripheralId_RCSS_MCASPB_AUX,
+ .clkSource = Rcm_PeripheralClockSource_DPLL_PER_HSDIV0_CLKOUT1,
+ .freqHz = SBL_RCSS_MCASPB_AUX_FREQ_HZ,
+ },
+ //HW_WR_REG32(CSL_RCSS_RCM_U_BASE+RCSS_MCASPC_AUX_CLK_DIV_VAL, 0x111); //RCSS_MCASPB_AUX_CLK_DIV_VAL_CLKDIVR = 0x111; 192/2
+ //HW_WR_REG32(CSL_RCSS_RCM_U_BASE+RCSS_MCASPC_AUX_CLK_SRC_SEL, 0x222); //RCSS_MCASPB_AUX_CLK_SRC_SEL_CLKSRCSEL = 0x222;
+ {
+ .peripheralId = Rcm_PeripheralId_RCSS_MCASPC_AUX,
+ .clkSource = Rcm_PeripheralClockSource_DPLL_PER_HSDIV0_CLKOUT1,
+ .freqHz = SBL_RCSS_MCASPC_AUX_FREQ_HZ,
+ },
+ /* TODO: Rcm Library support for Rcm_PeripheralClockSource_RCSS_ATL_CLKOUT0 clock source */
+ //HW_WR_REG32(CSL_RCSS_RCM_U_BASE+RCSS_MCASPA_REF0_CLK_DIV_VAL, 0x111); //RCSS_MCASPA_REF0_CLK_DIV_VAL_CLKDIVR = 0x111; 200/2
+ //HW_WR_REG32(CSL_RCSS_RCM_U_BASE+RCSS_MCASPA_REF0_CLK_SRC_SEL, 0x111); //RCSS_MCASPA_REF0_CLK_SRC_SEL_CLKSRCSEL = 0x111;
+ //SBL_RcmSetPeripheralClock(Rcm_PeripheralId_RCSS_MCASPA_REF0, Rcm_PeripheralClockSource_RCSS_ATL_CLKOUT0 , SBL_RCSS_MCASPA_REF0_FREQ_HZ);
+
+ //HW_WR_REG32(CSL_RCSS_RCM_U_BASE+RCSS_MCASPB_REF0_CLK_DIV_VAL, 0x111); //RCSS_MCASPB_REF0_CLK_DIV_VAL_CLKDIVR = 0x111; 200/2
+ //HW_WR_REG32(CSL_RCSS_RCM_U_BASE+RCSS_MCASPB_REF0_CLK_SRC_SEL, 0x111); //RCSS_MCASPB_REF0_CLK_SRC_SEL_CLKSRCSEL = 0x111;
+
+ //HW_WR_REG32(CSL_RCSS_RCM_U_BASE+RCSS_MCASPC_REF0_CLK_DIV_VAL, 0x111); //RCSS_MCASPB_REF0_CLK_DIV_VAL_CLKDIVR = 0x111; 200/2
+ //HW_WR_REG32(CSL_RCSS_RCM_U_BASE+RCSS_MCASPC_REF0_CLK_SRC_SEL, 0x111); //RCSS_MCASPB_REF0_CLK_SRC_SEL_CLKSRCSEL = 0x111;
+
+ //HW_WR_REG32(CSL_RCSS_RCM_U_BASE+RCSS_MCASPA_REF1_CLK_DIV_VAL, 0x111); //RCSS_MCASPA_REF1_CLK_DIV_VAL_CLKDIVR = 0x111; 200/2
+ //HW_WR_REG32(CSL_RCSS_RCM_U_BASE+RCSS_MCASPA_REF1_CLK_SRC_SEL, 0x111); //RCSS_MCASPA_REF1_CLK_SRC_SEL_CLKSRCSEL = 0x111;
+
+ //HW_WR_REG32(CSL_RCSS_RCM_U_BASE+RCSS_MCASPB_REF1_CLK_DIV_VAL, 0x111); //RCSS_MCASPB_REF1_CLK_DIV_VAL_CLKDIVR = 0x111; 200/2
+ //HW_WR_REG32(CSL_RCSS_RCM_U_BASE+RCSS_MCASPB_REF1_CLK_SRC_SEL, 0x111); //RCSS_MCASPB_REF1_CLK_SRC_SEL_CLKSRCSEL = 0x111;
+
+ //HW_WR_REG32(CSL_RCSS_RCM_U_BASE+RCSS_MCASPC_REF1_CLK_DIV_VAL, 0x111); //RCSS_MCASPB_REF1_CLK_DIV_VAL_CLKDIVR = 0x111; 200/2
+ //HW_WR_REG32(CSL_RCSS_RCM_U_BASE+RCSS_MCASPC_REF1_CLK_SRC_SEL, 0x111); //RCSS_MCASPB_REF1_CLK_SRC_SEL_CLKSRCSEL = 0x111;
+};
+
+
+/**
+ * \brief clock Initialization function
+ *
+ * Enables different power domains and peripheral clocks of the SoC.
+ * Some of the power domains and peripherals will be OFF by default.
+ * Enabling the power domains is mandatory before accessing using
+ * board interfaces connected to those peripherals.
+ *
+ * \return BOARD_SOK - Clock initialization sucessful.
+ * BOARD_INIT_CLOCK_FAIL - Clock initialization failed.
+ *
+ */
+void SBL_moduleClockInit(void)
+{
+ Rcm_Return retVal;
+ uint32_t i;
+
+ for (i = 0;
+ i < sizeof(SBLModuleClockCfgTbl)/sizeof(SBLModuleClockCfgTbl[0]);
+ i++)
+ {
+ retVal = SBL_RcmSetPeripheralClock(SBLModuleClockCfgTbl[i].peripheralId,
+ SBLModuleClockCfgTbl[i].clkSource,
+ SBLModuleClockCfgTbl[i].freqHz);
+ DebugP_assert(retVal == Rcm_Return_SUCCESS);
+ }
+}
+
+
index b452d3c5c7e9cbec0cf707904645c2025b951838..af7b484f93c853b81e53b0f03fbb1d136b05dcf8 100644 (file)
ifeq ($(SOC), tpr12)
SRCS_COMMON += sbl_pinmux.c
+ SRCS_COMMON += sbl_module_clock_config.c
endif
index 681fbfc79b8ff8db3e735ae3b054f4e40dd88bd5..1a3c4882ce5d7854b671322ff0a021daa247f517 100644 (file)
************************** RCM Functions *****************************
**************************************************************************/
+static uint32_t getClkSrcFromClkSelVal(uint16_t *clkSelTbl, uint32_t numEntries, uint32_t clkSelMatchVal)
+{
+ uint32_t i;
+ uint32_t clkSource;
+
+ for (i = 0; i < numEntries; i++)
+ {
+ if (clkSelMatchVal == clkSelTbl[i])
+ {
+ break;
+ }
+ }
+ if (i < numEntries)
+ {
+ clkSource = i;
+ }
+ else
+ {
+ clkSource = ~0U;
+ }
+ return clkSource;
+}
+
/**
* @b Description
return;
}
+/**
+ * @b Description
+ * @n
+ * This API returns Clk Src Selection register, Clk Divider Register for
+ * specified peripheral. It also returns the Clk Src Selection value for a
+ * specified clock
+ *
+ * @param[in] PeriphID
+ * Peripheral Id
+ * @param[in] clkSource
+ * Clock Source
+ * @param[out] clkSrcVal
+ * Value to be programmed corresponding to the ClkSource
+ * @param[out] clkSrcReg
+ * Register Address for programming Clock Source Selection
+ * @param[in] clkdDivReg
+ * PRegister Address for programming Clock Divider Selection
+ *
+ * @retval None
+ */
+static Rcm_Return getClkSrcAndDivValue (Rcm_PeripheralId PeriphID,
+ Rcm_PeripheralClockSource *clkSource,
+ volatile uint32_t *clkDiv)
+{
+ CSL_mss_rcmRegs *ptrMSSRCMRegs;
+ CSL_dss_rcmRegs *ptrDSSRCMRegs;
+ CSL_rcss_rcmRegs *ptrRCSSRCMRegs;
+ CSL_mss_toprcmRegs *ptrTOPRCMRegs;
+ uint32_t clkSrc;
+ uint32_t clkSrcId;
+ Rcm_Return retVal = Rcm_Return_SUCCESS;
+
+ ptrMSSRCMRegs = CSL_RCM_getBaseAddress ();
+ ptrDSSRCMRegs = CSL_DSSRCM_getBaseAddress ();
+ ptrTOPRCMRegs = CSL_TopRCM_getBaseAddress ();
+ ptrRCSSRCMRegs = CSL_RCSSRCM_getBaseAddress ();
+
+ switch (PeriphID)
+ {
+ case Rcm_PeripheralId_MSS_RTIA:
+ {
+ clkSrc = ptrMSSRCMRegs->MSS_RTIA_CLK_SRC_SEL;
+ *clkDiv = ptrMSSRCMRegs->MSS_RTIA_CLK_DIV_VAL;
+ clkSrcId = getClkSrcFromClkSelVal(gRtiClkSrcValMap, SBL_UTILS_ARRAYSIZE(gRtiClkSrcValMap), clkSrc);
+ DebugP_assert(clkSrcId != ~0U);
+ *clkSource = (Rcm_PeripheralClockSource) clkSrcId;
+ break;
+ }
+ case Rcm_PeripheralId_MSS_RTIB:
+ {
+ clkSrc = ptrMSSRCMRegs->MSS_RTIB_CLK_SRC_SEL;
+ *clkDiv = ptrMSSRCMRegs->MSS_RTIB_CLK_DIV_VAL;
+ clkSrcId = getClkSrcFromClkSelVal(gRtiClkSrcValMap, SBL_UTILS_ARRAYSIZE(gRtiClkSrcValMap), clkSrc);
+ DebugP_assert(clkSrcId != ~0U);
+ *clkSource = (Rcm_PeripheralClockSource) clkSrcId;
+ break;
+ }
+ case Rcm_PeripheralId_MSS_RTIC:
+ {
+ clkSrc = ptrMSSRCMRegs->MSS_RTIC_CLK_SRC_SEL;
+ *clkDiv = ptrMSSRCMRegs->MSS_RTIC_CLK_DIV_VAL;
+ clkSrcId = getClkSrcFromClkSelVal(gRtiClkSrcValMap, SBL_UTILS_ARRAYSIZE(gRtiClkSrcValMap), clkSrc);
+ DebugP_assert(clkSrcId != ~0U);
+ *clkSource = (Rcm_PeripheralClockSource) clkSrcId;
+
+ break;
+ }
+ case Rcm_PeripheralId_MSS_WDT:
+ {
+ clkSrc = ptrMSSRCMRegs->MSS_WDT_CLK_SRC_SEL;
+ *clkDiv = ptrMSSRCMRegs->MSS_WDT_CLK_DIV_VAL;
+ clkSrcId = getClkSrcFromClkSelVal(gRtiClkSrcValMap, SBL_UTILS_ARRAYSIZE(gRtiClkSrcValMap), clkSrc);
+ DebugP_assert(clkSrcId != ~0U);
+ *clkSource = (Rcm_PeripheralClockSource) clkSrcId;
+ break;
+ }
+ case Rcm_PeripheralId_MSS_SCIA:
+ {
+ clkSrc = ptrMSSRCMRegs->MSS_SCIA_CLK_SRC_SEL;
+ *clkDiv = ptrMSSRCMRegs->MSS_SCIA_CLK_DIV_VAL;
+ clkSrcId = getClkSrcFromClkSelVal(gSciClkSrcValMap, SBL_UTILS_ARRAYSIZE(gSciClkSrcValMap), clkSrc);
+ DebugP_assert(clkSrcId != ~0U);
+ *clkSource = (Rcm_PeripheralClockSource) clkSrcId;
+ break;
+ }
+ case Rcm_PeripheralId_MSS_SCIB:
+ {
+ clkSrc = ptrMSSRCMRegs->MSS_SCIB_CLK_SRC_SEL;
+ *clkDiv = ptrMSSRCMRegs->MSS_SCIB_CLK_DIV_VAL;
+ clkSrcId = getClkSrcFromClkSelVal(gSciClkSrcValMap, SBL_UTILS_ARRAYSIZE(gSciClkSrcValMap), clkSrc);
+ DebugP_assert(clkSrcId != ~0U);
+ *clkSource = (Rcm_PeripheralClockSource) clkSrcId;
+ break;
+ }
+ case Rcm_PeripheralId_MSS_SPIA:
+ {
+ clkSrc = ptrMSSRCMRegs->MSS_SPIA_CLK_SRC_SEL;
+ *clkDiv = ptrMSSRCMRegs->MSS_SPIA_CLK_DIV_VAL;
+ clkSrcId = getClkSrcFromClkSelVal(gSpiClkSrcValMap, SBL_UTILS_ARRAYSIZE(gSpiClkSrcValMap), clkSrc);
+ DebugP_assert(clkSrcId != ~0U);
+ *clkSource = (Rcm_PeripheralClockSource) clkSrcId;
+ break;
+ }
+ case Rcm_PeripheralId_MSS_SPIB:
+ {
+ clkSrc = ptrMSSRCMRegs->MSS_SPIB_CLK_SRC_SEL;
+ *clkDiv = ptrMSSRCMRegs->MSS_SPIB_CLK_DIV_VAL;
+ clkSrcId = getClkSrcFromClkSelVal(gSpiClkSrcValMap, SBL_UTILS_ARRAYSIZE(gSpiClkSrcValMap), clkSrc);
+ DebugP_assert(clkSrcId != ~0U);
+ *clkSource = (Rcm_PeripheralClockSource) clkSrcId;
+ break;
+ }
+ case Rcm_PeripheralId_MSS_I2C:
+ {
+ clkSrc = ptrMSSRCMRegs->MSS_I2C_CLK_SRC_SEL;
+ *clkDiv = ptrMSSRCMRegs->MSS_I2C_CLK_DIV_VAL;
+ clkSrcId = getClkSrcFromClkSelVal(gI2CClkSrcValMap, SBL_UTILS_ARRAYSIZE(gI2CClkSrcValMap), clkSrc);
+ DebugP_assert(clkSrcId != ~0U);
+ *clkSource = (Rcm_PeripheralClockSource) clkSrcId;
+ break;
+ }
+ case Rcm_PeripheralId_MSS_QSPI:
+ {
+ clkSrc = ptrMSSRCMRegs->MSS_QSPI_CLK_SRC_SEL;
+ *clkDiv = ptrMSSRCMRegs->MSS_QSPI_CLK_DIV_VAL;
+ clkSrcId = getClkSrcFromClkSelVal(gQspiClkSrcValMap, SBL_UTILS_ARRAYSIZE(gQspiClkSrcValMap), clkSrc);
+ DebugP_assert(clkSrcId != ~0U);
+ *clkSource = (Rcm_PeripheralClockSource) clkSrcId;
+ break;
+ }
+ case Rcm_PeripheralId_MSS_MCANA:
+ {
+ clkSrc = ptrMSSRCMRegs->MSS_MCANA_CLK_SRC_SEL;
+ *clkDiv = ptrMSSRCMRegs->MSS_MCANA_CLK_DIV_VAL;
+ clkSrcId = getClkSrcFromClkSelVal(gMcanClkSrcValMap, SBL_UTILS_ARRAYSIZE(gMcanClkSrcValMap), clkSrc);
+ DebugP_assert(clkSrcId != ~0U);
+ *clkSource = (Rcm_PeripheralClockSource) clkSrcId;
+ break;
+ }
+ case Rcm_PeripheralId_MSS_MCANB:
+ {
+ clkSrc = ptrMSSRCMRegs->MSS_MCANB_CLK_SRC_SEL;
+ *clkDiv = ptrMSSRCMRegs->MSS_MCANB_CLK_DIV_VAL;
+ clkSrcId = getClkSrcFromClkSelVal(gMcanClkSrcValMap, SBL_UTILS_ARRAYSIZE(gMcanClkSrcValMap), clkSrc);
+ DebugP_assert(clkSrcId != ~0U);
+ *clkSource = (Rcm_PeripheralClockSource) clkSrcId;
+ break;
+ }
+ case Rcm_PeripheralId_MSS_CPSW:
+ {
+ clkSrc = ptrMSSRCMRegs->MSS_CPSW_CLK_SRC_SEL;
+ *clkDiv = ptrMSSRCMRegs->MSS_CPSW_CLK_DIV_VAL;
+ clkSrcId = getClkSrcFromClkSelVal(gCpswClkSrcValMap, SBL_UTILS_ARRAYSIZE(gCpswClkSrcValMap), clkSrc);
+ DebugP_assert(clkSrcId != ~0U);
+ *clkSource = (Rcm_PeripheralClockSource) clkSrcId;
+ break;
+ }
+ case Rcm_PeripheralId_MSS_CPTS:
+ {
+ clkSrc = ptrMSSRCMRegs->MSS_CPTS_CLK_SRC_SEL;
+ *clkDiv = ptrMSSRCMRegs->MSS_CPTS_CLK_DIV_VAL;
+ clkSrcId = getClkSrcFromClkSelVal(gCptsClkSrcValMap, SBL_UTILS_ARRAYSIZE(gCptsClkSrcValMap), clkSrc);
+ DebugP_assert(clkSrcId != ~0U);
+ *clkSource = (Rcm_PeripheralClockSource) clkSrcId;
+ break;
+ }
+ case Rcm_PeripheralId_CSIRX:
+ {
+ clkSrc = ptrTOPRCMRegs->CSIRX_CLK_SRC_SEL;
+ *clkDiv = ptrTOPRCMRegs->CSIRX_DIV_VAL;
+ clkSrcId = getClkSrcFromClkSelVal(gCsiRxClkSrcValMap, SBL_UTILS_ARRAYSIZE(gCsiRxClkSrcValMap), clkSrc);
+ DebugP_assert(clkSrcId != ~0U);
+ *clkSource = (Rcm_PeripheralClockSource) clkSrcId;
+ break;
+ }
+ case Rcm_PeripheralId_DSS_RTIA:
+ {
+ clkSrc = ptrDSSRCMRegs->DSS_RTIA_CLK_SRC_SEL;
+ *clkDiv = ptrDSSRCMRegs->DSS_RTIA_CLK_DIV_VAL;
+ clkSrcId = getClkSrcFromClkSelVal(gDssRtiClkSrcValMap, SBL_UTILS_ARRAYSIZE(gDssRtiClkSrcValMap), clkSrc);
+ DebugP_assert(clkSrcId != ~0U);
+ *clkSource = (Rcm_PeripheralClockSource) clkSrcId;
+ break;
+ }
+ case Rcm_PeripheralId_DSS_RTIB:
+ {
+ clkSrc = ptrDSSRCMRegs->DSS_RTIB_CLK_SRC_SEL;
+ *clkDiv = ptrDSSRCMRegs->DSS_RTIB_CLK_DIV_VAL;
+ clkSrcId = getClkSrcFromClkSelVal(gDssRtiClkSrcValMap, SBL_UTILS_ARRAYSIZE(gDssRtiClkSrcValMap), clkSrc);
+ DebugP_assert(clkSrcId != ~0U);
+ *clkSource = (Rcm_PeripheralClockSource) clkSrcId;
+ break;
+ }
+ case Rcm_PeripheralId_DSS_WDT:
+ {
+ clkSrc = ptrDSSRCMRegs->DSS_WDT_CLK_SRC_SEL;
+ *clkDiv = ptrDSSRCMRegs->DSS_WDT_CLK_DIV_VAL;
+ clkSrcId = getClkSrcFromClkSelVal(gDssRtiClkSrcValMap, SBL_UTILS_ARRAYSIZE(gDssRtiClkSrcValMap), clkSrc);
+ DebugP_assert(clkSrcId != ~0U);
+ *clkSource = (Rcm_PeripheralClockSource) clkSrcId;
+ break;
+ }
+ case Rcm_PeripheralId_DSS_SCIA:
+ {
+ clkSrc = ptrDSSRCMRegs->DSS_SCIA_CLK_SRC_SEL;
+ *clkDiv = ptrDSSRCMRegs->DSS_SCIA_CLK_DIV_VAL;
+ clkSrcId = getClkSrcFromClkSelVal(gDssSciClkSrcValMap, SBL_UTILS_ARRAYSIZE(gDssSciClkSrcValMap), clkSrc);
+ DebugP_assert(clkSrcId != ~0U);
+ *clkSource = (Rcm_PeripheralClockSource) clkSrcId;
+ break;
+ }
+ case Rcm_PeripheralId_RCSS_SCIA:
+ {
+ clkSrc = ptrRCSSRCMRegs->RCSS_SCIA_CLK_SRC_SEL;
+ *clkDiv = ptrRCSSRCMRegs->RCSS_SCIA_CLK_DIV_VAL;
+ clkSrcId = getClkSrcFromClkSelVal(gRcssSciClkSrcValMap, SBL_UTILS_ARRAYSIZE(gRcssSciClkSrcValMap), clkSrc);
+ DebugP_assert(clkSrcId != ~0U);
+ *clkSource = (Rcm_PeripheralClockSource) clkSrcId;
+ break;
+ }
+ case Rcm_PeripheralId_RCSS_SPIA:
+ {
+ clkSrc = ptrRCSSRCMRegs->RCSS_SPIA_CLK_SRC_SEL;
+ *clkDiv = ptrRCSSRCMRegs->RCSS_SPIA_CLK_DIV_VAL;
+ clkSrcId = getClkSrcFromClkSelVal(gRcssSpiClkSrcValMap, SBL_UTILS_ARRAYSIZE(gRcssSpiClkSrcValMap), clkSrc);
+ DebugP_assert(clkSrcId != ~0U);
+ *clkSource = (Rcm_PeripheralClockSource) clkSrcId;
+ break;
+ }
+ case Rcm_PeripheralId_RCSS_SPIB:
+ {
+ clkSrc = ptrRCSSRCMRegs->RCSS_SPIB_CLK_SRC_SEL;
+ *clkDiv = ptrRCSSRCMRegs->RCSS_SPIB_CLK_DIV_VAL;
+ clkSrcId = getClkSrcFromClkSelVal(gRcssSpiClkSrcValMap, SBL_UTILS_ARRAYSIZE(gRcssSpiClkSrcValMap), clkSrc);
+ DebugP_assert(clkSrcId != ~0U);
+ *clkSource = (Rcm_PeripheralClockSource) clkSrcId;
+ break;
+ }
+ case Rcm_PeripheralId_RCSS_I2CA:
+ {
+ clkSrc = ptrRCSSRCMRegs->RCSS_I2CA_CLK_SRC_SEL;
+ *clkDiv = ptrRCSSRCMRegs->RCSS_I2CA_CLK_DIV_VAL;
+ clkSrcId = getClkSrcFromClkSelVal(gRcssI2CClkSrcValMap, SBL_UTILS_ARRAYSIZE(gRcssI2CClkSrcValMap), clkSrc);
+ DebugP_assert(clkSrcId != ~0U);
+ *clkSource = (Rcm_PeripheralClockSource) clkSrcId;
+ break;
+ }
+ case Rcm_PeripheralId_RCSS_I2CB:
+ {
+ clkSrc = ptrRCSSRCMRegs->RCSS_I2CB_CLK_SRC_SEL;
+ *clkDiv = ptrRCSSRCMRegs->RCSS_I2CB_CLK_DIV_VAL;
+ clkSrcId = getClkSrcFromClkSelVal(gRcssI2CClkSrcValMap, SBL_UTILS_ARRAYSIZE(gRcssI2CClkSrcValMap), clkSrc);
+ DebugP_assert(clkSrcId != ~0U);
+ *clkSource = (Rcm_PeripheralClockSource) clkSrcId;
+ break;
+ }
+ case Rcm_PeripheralId_RCSS_ATL:
+ {
+ clkSrc = ptrRCSSRCMRegs->RCSS_ATL_CLK_SRC_SEL;
+ *clkDiv = ptrRCSSRCMRegs->RCSS_ATL_CLK_DIV_VAL;
+ clkSrcId = getClkSrcFromClkSelVal(gRcssATLClkSrcValMap, SBL_UTILS_ARRAYSIZE(gRcssATLClkSrcValMap), clkSrc);
+ DebugP_assert(clkSrcId != ~0U);
+ *clkSource = (Rcm_PeripheralClockSource) clkSrcId;
+ break;
+ }
+ case Rcm_PeripheralId_RCSS_MCASPA_AUX:
+ {
+ clkSrc = ptrRCSSRCMRegs->RCSS_MCASPA_AUX_CLK_SRC_SEL;
+ *clkDiv = ptrRCSSRCMRegs->RCSS_MCASPA_AUX_CLK_DIV_VAL;
+ clkSrcId = getClkSrcFromClkSelVal(gRcssMCASPAuxClkSrcValMap, SBL_UTILS_ARRAYSIZE(gRcssMCASPAuxClkSrcValMap), clkSrc);
+ DebugP_assert(clkSrcId != ~0U);
+ *clkSource = (Rcm_PeripheralClockSource) clkSrcId;
+ break;
+ }
+ case Rcm_PeripheralId_RCSS_MCASPB_AUX:
+ {
+ clkSrc = ptrRCSSRCMRegs->RCSS_MCASPB_AUX_CLK_SRC_SEL;
+ *clkDiv = ptrRCSSRCMRegs->RCSS_MCASPB_AUX_CLK_DIV_VAL;
+ clkSrcId = getClkSrcFromClkSelVal(gRcssMCASPAuxClkSrcValMap, SBL_UTILS_ARRAYSIZE(gRcssMCASPAuxClkSrcValMap), clkSrc);
+ DebugP_assert(clkSrcId != ~0U);
+ *clkSource = (Rcm_PeripheralClockSource) clkSrcId;
+ break;
+ }
+ case Rcm_PeripheralId_RCSS_MCASPC_AUX:
+ {
+ clkSrc = ptrRCSSRCMRegs->RCSS_MCASPC_AUX_CLK_SRC_SEL;
+ *clkDiv = ptrRCSSRCMRegs->RCSS_MCASPC_AUX_CLK_DIV_VAL;
+ clkSrcId = getClkSrcFromClkSelVal(gRcssMCASPAuxClkSrcValMap, SBL_UTILS_ARRAYSIZE(gRcssMCASPAuxClkSrcValMap), clkSrc);
+ DebugP_assert(clkSrcId != ~0U);
+ *clkSource = (Rcm_PeripheralClockSource) clkSrcId;
+ break;
+ }
+ default:
+ {
+ *clkDiv = 0U;
+ retVal = Rcm_Return_ERROR;
+ }
+ }
+ return retVal;
+}
+
/**
* @b Description
* @n
return;
}
+
+static Rcm_Return getDSPClkSrcAndDivValue(Rcm_DSPClockSource *clkSource,
+ uint32_t *clkDiv)
+{
+ uint32_t clkSrc, clkSrcId;
+ Rcm_Return retVal = Rcm_Return_SUCCESS;
+ CSL_dss_rcmRegs *ptrDSSRCMRegs;
+
+ ptrDSSRCMRegs = CSL_DSSRCM_getBaseAddress ();
+ clkSrc = ptrDSSRCMRegs->DSS_DSP_CLK_SRC_SEL;
+ *clkDiv = ptrDSSRCMRegs->DSS_DSP_CLK_DIV_VAL;
+ clkSrcId = getClkSrcFromClkSelVal(gDspcoreClkSrcValMap, SBL_UTILS_ARRAYSIZE(gDspcoreClkSrcValMap), clkSrc);
+ DebugP_assert(clkSrcId != ~0U);
+ if (clkSrcId != ~0U)
+ {
+ *clkSource = (Rcm_DSPClockSource) clkSrcId;
+ }
+ else
+ {
+ retVal = Rcm_Return_ERROR;
+ }
+ return retVal;
+}
+
/**
* @b Description
* @n
return moduleClkDivRegVal;
}
+static uint32_t SBL_RcmGetModuleClkDivFromRegVal(uint32_t moduleClkDivRegVal)
+{
+ uint32_t moduleClkDivVal;
+
+ moduleClkDivVal = ((moduleClkDivRegVal & 0xF) + 1);
+ return moduleClkDivVal;
+}
+
void SBL_RcmSetCR5SysClock(uint32_t cr5FreqHz, uint32_t sysClkFreqHz)
{
CSL_mss_toprcmRegs *ptrTopRCMRegs;
ptrTopRCMRegs->MSS_CR5_CLK_SRC_SEL = CSL_insert16 (ptrTopRCMRegs->MSS_CR5_CLK_SRC_SEL, 11U, 0U, gCR5ClkSrcValMap[Rcm_CR5ClockSource_DPLL_CORE_HSDIV0_CLKOUT2]);
}
+uint32_t SBL_RcmGetCR5Freq(void)
+{
+ uint32_t Finp;
+ uint32_t moduleClkDivRegVal;
+ uint32_t clkDivVal;
+ CSL_mss_toprcmRegs *ptrTopRCMRegs;
+
+ ptrTopRCMRegs = CSL_TopRCM_getBaseAddress ();
+ Finp = SBL_RcmGetCR5SysclkInFrequency();
+ moduleClkDivRegVal = ptrTopRCMRegs->MSS_CR5_DIV_VAL;
+ clkDivVal = SBL_RcmGetModuleClkDivFromRegVal(moduleClkDivRegVal);
+ return (Finp / clkDivVal);
+}
/**
* @b Description
return (retVal);
}
+/**
+ * @b Description
+ * @n
+ * This API gets the frequency configured for a specified peripheral Id.
+ *
+ * @param[in] periphID
+ * Peripheral Id
+ * @param[in] clkSource
+ * Clock Source
+ * @param[in] clkDivisor
+ * Clock Divider Value
+ *
+ * \ingroup DRIVER_RCM_FUNCTIONS
+ *
+ * @retval Rcm_Return
+ */
+Rcm_Return SBL_RcmGetPeripheralFreq (Rcm_PeripheralId periphID,
+ uint32_t *freqHz)
+{
+ uint32_t clkDivisorRegVal;
+ uint32_t clkDivisor;
+ Rcm_Return retVal;
+ uint32_t Finp;
+ Rcm_PeripheralClockSource clkSource;
+
+ retVal = getClkSrcAndDivValue(periphID, &clkSource, &clkDivisorRegVal);
+ DebugP_assert(retVal == Rcm_Return_SUCCESS);
+ if (Rcm_Return_SUCCESS == retVal)
+ {
+ Finp = SBL_RcmGetPeripheralClockFrequency(clkSource);
+ clkDivisor = SBL_RcmGetModuleClkDivFromRegVal(clkDivisorRegVal);
+ *freqHz = Finp / clkDivisor;
+ }
+ return (retVal);
+}
+
/**
* @b Description
* @n
* @n
* This API returns the frequency of the clock which is passed as parameter
* @param[in] clkSource
-5 * clock source for which frequency is requested
+ * clock source for which frequency is requested
*
* \ingroup DRIVER_RCM_FUNCTIONS
*
return (clkFreq);
}
+/**
+ * @b Description
+ * @n
+ * This API get the c66x core configured frequency
+ *
+ * @param[out] freqHz
+ * c66x core clock frequency
+ *
+ * \ingroup DRIVER_RCM_FUNCTIONS
+ *
+ * @retval Rcm_Return
+ */
+Rcm_Return SBL_RcmGetDspCoreFreq (uint32_t *freqHz)
+{
+ Rcm_Return retVal;
+ CSL_dss_rcmRegs *ptrDSSRcmRegs = CSL_DSSRCM_getBaseAddress();
+ uint32_t pllFout;
+ uint32_t clkDivisorRegVal;
+ uint32_t clkDiv;
+ Rcm_DSPClockSource clkSource;
+
+
+ CSL_DSSRCM_enableAccess(ptrDSSRcmRegs);
+ retVal= getDSPClkSrcAndDivValue (&clkSource, &clkDivisorRegVal);
+
+ DebugP_assert(retVal == Rcm_Return_SUCCESS);
+ if (Rcm_Return_SUCCESS == retVal)
+ {
+ pllFout = SBL_RcmGetDSPClockFrequency(clkSource);
+ clkDiv = SBL_RcmGetModuleClkDivFromRegVal(clkDivisorRegVal);
+ *freqHz = (pllFout / clkDiv);
+ }
+ return (retVal);
+}
static Rcm_ADPLLJConfig_t const * SBL_getADPLLJConfig(uint32_t Finp, Rcm_PllFoutFreqId foutFreqId)
index 28bcf2b19402f9dc9b2e9bd606fea70d768f2082..509645d781ee00cbee5baccdd200833b485d9703 100644 (file)
extern void SBL_RcmGetEfuseQSPIConfig(Rcm_EfuseQspiConfig *qspiEfuseCfg);
+extern Rcm_Return SBL_RcmGetPeripheralFreq (Rcm_PeripheralId periphID,
+ uint32_t *freqHz);
+extern uint32_t SBL_RcmGetCR5Freq(void);
+
#ifdef __cplusplus
}
#endif
index aa6c2255d4ed7446377ca393591b26c01fea09d4..02b36a5846c98d56ac65b34c86f4ed0e1f9704e2 100644 (file)
#include <ti/board/board.h>
-#define SBL_NEVER_AUTH_APP (0x55555555u)
-#define SBL_ALWAYS_AUTH_APP (0xAAAAAAAAu)
-#define SBL_SYSFW_MAX_SIZE (0x42000U)
-
-
-#define SBL_SYS_STATUS_REG (0x44234100U)
-#define SBL_SYS_STATUS_DEV_TYPE_MASK (0x0000000FU)
-#define SBL_SYS_STATUS_DEV_SUBTYPE_MASK (0x00000F00U)
-
-
-#define SBL_SYS_STATUS_DEV_TYPE_GP (0x3U)
-#define SBL_SYS_STATUS_DEV_TYPE_TEST (0x5U)
-#define SBL_SYS_STATUS_DEV_SUBTYPE_FS (0x00000A00U)
-
sblProfileInfo_t sblProfileLog[MAX_PROFILE_LOG_ENTRIES];
uint32_t sblProfileLogIndx = 0, sblProfileLogOvrFlw = 0;
void SBL_cpuGetFreq(uint32_t coreId, uint64_t *cpu_clk_freq)
{
- *cpu_clk_freq = 250000000;
+ *cpu_clk_freq = SBL_RcmGetCR5Freq();
}
-int32_t SBL_procBootAuthAndStart(uint32_t cert_load_addr)
-{
- return CSL_PASS;
-
-}
#ifdef __cplusplus
#pragma FUNC_EXT_CALLED()
}
-uint32_t SBL_GetCertLen(uint8_t *x509_cert_ptr)
-{
- uint32_t cert_len = 0;
- uint8_t *cert_len_ptr = (uint8_t *)&cert_len;
-
- SBL_ADD_PROFILE_POINT;
-
- SBL_log(SBL_LOG_MAX,"Searching for X509 certificate ...");
- if ( *x509_cert_ptr != 0x30)
- {
- SBL_log(SBL_LOG_MAX,"not found\r\n");
- SBL_ADD_PROFILE_POINT;
- return 0;
- }
-
- cert_len = *(x509_cert_ptr + 1);
-
- /* If you need more than 2 bytes to store the cert length */
- /* it means that the cert length is greater than 64 Kbytes */
- /* and we do not support it */
- if ((cert_len > 0x80) &&
- (cert_len != 0x82))
- {
- SBL_log(SBL_LOG_MAX,"size invalid\r\n");
- SBL_ADD_PROFILE_POINT;
- return 0;
- }
-
- SBL_log(SBL_LOG_MAX,"found @0x%x, ", x509_cert_ptr);
-
- if ( cert_len == 0x82)
- {
- *cert_len_ptr = *(x509_cert_ptr + 3);
- *(cert_len_ptr + 1) = *(x509_cert_ptr + 2);
-
- /* add current offset from start of x509 cert */
- cert_len += 3;
- }
- else
- {
- /* add current offset from start of x509 cert */
- /* if cert len was obtained from 2nd byte i.e. */
- /* cert size is 127 bytes or less */
- cert_len += 1;
- }
-
- /* cert_len now contains the offset of the last byte */
- /* of the cert from the ccert_start. To get the size */
- /* of certificate, add 1 */
- SBL_log(SBL_LOG_MAX,"size = %d bytes\r\n", cert_len + 1);
-
- SBL_ADD_PROFILE_POINT;
- return cert_len + 1;
-}
-
-uint8_t *SBL_FindSeq(uint8_t *x509_cert_ptr, uint32_t x509_cert_size, uint8_t *seq_oid, uint8_t seq_len)
-{
- uint8_t *x509_cert_end = x509_cert_ptr + x509_cert_size - seq_len;
-
- SBL_ADD_PROFILE_POINT;
-
- /* searching for the following byte seq in the cert */
- /* seq_id(0x30) seq_len(< 0x80) 0x06 0x09 0x2B... */
- while (x509_cert_ptr < x509_cert_end)
- {
- if ((*x509_cert_ptr == seq_oid[0]) &&
- (*(x509_cert_ptr + 2) == seq_oid[2]) &&
- (*(x509_cert_ptr - 2) == 0x30))
- {
- if ((bcmp((const void *)x509_cert_ptr, (const void *)seq_oid, seq_len)) == 0)
- {
- SBL_ADD_PROFILE_POINT;
- /* return start boot_seq */
- return (x509_cert_ptr - 2);
- }
- }
- x509_cert_ptr++;
- }
-
- SBL_ADD_PROFILE_POINT;
-
- return NULL;
-}
-
-uint32_t SBL_GetMsgLen(uint8_t *x509_cert_ptr, uint32_t x509_cert_size)
-{
- uint8_t *boot_seq_ptr;
- uint32_t msg_len = 0, boot_seq_len;
- uint8_t *msg_len_ptr = (uint8_t *)&msg_len;
- /* oid encoding of boot_seq extension - 1.3.6.1.4.1.294.1.1 */
- uint8_t boot_seq_oid[] = {0x06, 0x09, 0x2B, 0x06, 0x01, 0x04, 0x01, 0x82, 0x26, 0x01, 0x01};
-
- SBL_ADD_PROFILE_POINT;
-
- boot_seq_ptr = SBL_FindSeq(x509_cert_ptr, x509_cert_size, boot_seq_oid, sizeof(boot_seq_oid));
- SBL_log(SBL_LOG_MAX,"Found seq @ 0x%x\r\n", boot_seq_ptr);
-
- /* length of seq is stored in the byte after the 0x30 seq_id */
- /* length of seq is stored as offset of the last byte of seq */
- /* from current offset. Jump to the end of the boot seq as */
- /* the length of the message is the last field of this seq */
- boot_seq_len = *(++boot_seq_ptr);
- boot_seq_ptr = boot_seq_ptr + boot_seq_len;
-
- /* The last integer in this sequence is the msg length */
- /* integers are tagged 0x20, so search backwards for 0x20 */
- /* The msg size can be encoded in 1, 2, 3 or 4 bytes */
- /* 0x02 0x01 0x## */
- /* 0x02 0x02 0x## 0x## */
- /* 0x02 0x03 0x## 0x## 0x## */
- /* 0x02 0x04 0x## 0x## 0x## 0x## */
- if ( (*(boot_seq_ptr - 5) == 0x02) &&
- (*(boot_seq_ptr - 4) == 0x04) )
- {
- /* msg length encoded in 4 bytes */
- *msg_len_ptr = *boot_seq_ptr;
- *(msg_len_ptr + 1) = *(boot_seq_ptr - 1);
- *(msg_len_ptr + 2) = *(boot_seq_ptr - 2);
- *(msg_len_ptr + 3) = *(boot_seq_ptr - 3);
- }
- else if ( (*(boot_seq_ptr - 4) == 0x02) &&
- (*(boot_seq_ptr - 3) == 0x03) )
- {
- /* msg length encoded in 3 bytes */
- *msg_len_ptr = *boot_seq_ptr;
- *(msg_len_ptr + 1) = *(boot_seq_ptr - 1);
- *(msg_len_ptr + 2) = *(boot_seq_ptr - 2);
- }
- else if ( (*(boot_seq_ptr - 3) == 0x02) &&
- (*(boot_seq_ptr - 2) == 0x02) )
- {
- /* msg length encoded in 2 bytes */
- *msg_len_ptr = *boot_seq_ptr;
- *(msg_len_ptr + 1) = *(boot_seq_ptr - 1);
- }
- else if ( (*(boot_seq_ptr - 2) == 0x02) &&
- (*(boot_seq_ptr - 1) == 0x01) )
- {
- /* msg length encoded in 1 byte */
- *msg_len_ptr = *boot_seq_ptr;
- }
-
- SBL_log(SBL_LOG_MAX,"image length = %d bytes\r\n", msg_len);
- SBL_ADD_PROFILE_POINT;
- return msg_len;
-}
/* Keep all boot media read offsets and read sizes */
/* word aligned throughout the function in case */
uint8_t *scratch_mem,
uint32_t scratch_sz)
{
-/* X509 Certificate parsing is TBD */
-#if 0
- uint8_t *scratch_mem_ptr;
- uint32_t cert_len = 0, img_len, cert_load_addr;
- int32_t retVal = E_FAIL, auth_retval = E_FAIL;
- uint32_t SBL_GetCertLen(uint8_t *x509_cert_ptr);
- uint32_t SBL_GetMsgLen(uint8_t *x509_cert_ptr, uint32_t x509_cert_size);
-
- SBL_ADD_PROFILE_POINT;
-
- if ((fp_readData != NULL) && (fp_seek != NULL))
- {
- uint8_t x509Header[4];
- /* Read first 4 bytes of image to */
- /* determine if it is a x509 img */
- fp_readData(x509Header, *img_handle, 4);
- fp_seek(*img_handle, *ImageOffsetPtr);
- cert_len = SBL_GetCertLen(x509Header);
- }
-
- /* Check if cert size is within valid range */
- if ((cert_len > 0x100) &&
- (cert_len < 0x800) &&
- (scratch_mem !=NULL) &&
- (scratch_sz != 0))
- {
- uint8_t unaligned_bytes = cert_len % 4;
- uint8_t pad_align = 4 - unaligned_bytes;
-
- SBL_log(SBL_LOG_MAX,"SBL reserved memory Found: Start = @ 0x%x, Size = 0x%x\r\n", scratch_mem, scratch_sz);
- /* adjust cert load addr so that the */
- /* msg is always word aligned */
- scratch_mem_ptr = scratch_mem + pad_align;
- SBL_log(SBL_LOG_MAX,"Copying %d bytes from app to 0x%x\r\n", cert_len + pad_align, scratch_mem_ptr);
- fp_readData(scratch_mem_ptr, *img_handle, cert_len + pad_align);
- fp_seek(*img_handle, *ImageOffsetPtr);
- cert_load_addr = (uint32_t)scratch_mem_ptr;
-
- img_len = SBL_GetMsgLen(scratch_mem_ptr, cert_len);
- if ((scratch_mem_ptr + cert_len + img_len) <
- (scratch_mem + scratch_sz))
- {
- fp_seek(*img_handle, (*ImageOffsetPtr + cert_len - unaligned_bytes));
- scratch_mem_ptr += (cert_len - unaligned_bytes);
-
- img_len += unaligned_bytes;
- unaligned_bytes = img_len % 4;
- pad_align = 4 - unaligned_bytes;
- img_len += pad_align;
-
- SBL_log(SBL_LOG_MAX,"Copying %d bytes from offset 0x%x to 0x%x...", img_len, *ImageOffsetPtr + cert_len - unaligned_bytes, scratch_mem_ptr);
- fp_readData(scratch_mem_ptr, *img_handle, img_len);
- fp_seek(*img_handle, *ImageOffsetPtr);
-
- /* Request DMSC to authenticate the image */
- SBL_log(SBL_LOG_MAX,"Cert @ 0x%x ...", cert_load_addr);
-
- SBL_ADD_PROFILE_POINT;
-
- retVal = auth_retval = SBL_procBootAuthAndStart(cert_load_addr);
- if (retVal == CSL_PASS)
- {
- SBL_log(SBL_LOG_MAX,"Verify Passed...");
- }
- else
- {
- if (SBL_IsAuthReq() == SBL_NEVER_AUTH_APP)
- {
- SBL_log(SBL_LOG_MAX,"Ignored on GP...");
- }
- else
- {
- SBL_log(SBL_LOG_ERR,"Verify Failed!!\n\r");
- SBL_log(SBL_LOG_ERR,"Boot Halted!!\n\r");
- SblErrLoop(__FILE__, __LINE__);
- }
- }
-
- SBL_ADD_PROFILE_POINT;
-
- /* Image is loaded. RPRC parsing no longer */
- /* neeeds to access the boot media. Update */
- /* caller with image load address */
- SBL_SetMulticoreImageImgReadfxn((void *)SBL_ReadMem, (void *)SBL_SeekMem);
- *img_handle = (void *)(cert_load_addr+cert_len);
- *ImageOffsetPtr = 0;
- SBL_log(SBL_LOG_MAX,"done\r\n", img_len, scratch_mem_ptr);
- retVal = E_PASS;
- }
- }
-
- if ((auth_retval != CSL_PASS) &&
- (SBL_IsAuthReq() != SBL_NEVER_AUTH_APP))
- {
- SBL_log(SBL_LOG_ERR,"Is app signed correctly??\n\r");
- SBL_log(SBL_LOG_ERR,"App verification fails!! Boot Halted!!\n\r");
- SblErrLoop(__FILE__, __LINE__);
- }
- SBL_ADD_PROFILE_POINT;
-
- return retVal;
-#else
+ /* X509 Certificate parsing is TBD */
return E_PASS;
-#endif
}
/**********************************************************************
******************* SoC Specific Initilization ***********************
**********************************************************************/
-uint32_t SBL_IsAuthReq(void)
-{
- uint32_t retVal = SBL_ALWAYS_AUTH_APP;
- uint32_t dev_type;
- uint32_t dev_subtype;
-
- SBL_ADD_PROFILE_POINT;
-
- //TODO: Reduce EFUSE to determine device type
-// dev_type = CSL_REG32_RD(SBL_SYS_STATUS_REG) & SBL_SYS_STATUS_DEV_TYPE_MASK;
-// dev_subtype = CSL_REG32_RD(SBL_SYS_STATUS_REG) & SBL_SYS_STATUS_DEV_SUBTYPE_MASK;
-
- dev_type = SBL_SYS_STATUS_DEV_TYPE_GP;
- dev_subtype = SBL_SYS_STATUS_DEV_SUBTYPE_FS;
- /* No auth possible, if valid SMPK/BMPK is not present */
- if ((dev_subtype == SBL_SYS_STATUS_DEV_SUBTYPE_FS) ||
- (dev_type == SBL_SYS_STATUS_DEV_TYPE_GP) ||
- (dev_type == SBL_SYS_STATUS_DEV_TYPE_TEST))
- {
- retVal = SBL_NEVER_AUTH_APP;
- }
-
- SBL_ADD_PROFILE_POINT;
-
- return retVal;
-}
-
-void SBL_UARTAInitPwrClk(void)
-{
- Rcm_Return retVal;
-
- /* Setup UART clock source */
- retVal = SBL_RcmSetPeripheralClock(Rcm_PeripheralId_MSS_SCIA, Rcm_PeripheralClockSource_SYS_CLK, SBL_MSS_SCIA_FREQ_HZ);
- DebugP_assert(retVal == Rcm_Return_SUCCESS);
-}
-
-
-
void SBL_SocEarlyInit(void)
{
}
-
-/**
- * \brief clock Initialization function
- *
- * Enables different power domains and peripheral clocks of the SoC.
- * Some of the power domains and peripherals will be OFF by default.
- * Enabling the power domains is mandatory before accessing using
- * board interfaces connected to those peripherals.
- *
- * \return BOARD_SOK - Clock initialization sucessful.
- * BOARD_INIT_CLOCK_FAIL - Clock initialization failed.
- *
- */
-void SBL_moduleClockInit(void)
-{
- Rcm_Return retVal;
- Rcm_EfuseQspiConfig qspiCfg;
- uint32_t qspiClkFreq;
-
- /* Generate 96 MHz CSIRX Control Clock */
- //HW_WR_REG32(CSL_MSS_TOPRCM_U_BASE+CSIRX_CLK_SRC_SEL, 0x222);
- //HW_WR_REG32(CSL_MSS_TOPRCM_U_BASE+CSIRX_DIV_VAL, 0x000);
- retVal = SBL_RcmSetPeripheralClock(Rcm_PeripheralId_CSIRX, Rcm_PeripheralClockSource_DPLL_PER_HSDIV0_CLKOUT2, SBL_CSIRX_FREQ_HZ);
- DebugP_assert(retVal == Rcm_Return_SUCCESS);
-
- //HW_WR_REG32(CSL_MSS_RCM_U_BASE+MSS_MCANA_CLK_DIV_VAL, 0x444); //MSS_MCANA_CLK_DIV_VAL_CLKDIVR = 0x444; 400/5
- //HW_WR_REG32(CSL_MSS_RCM_U_BASE+MSS_MCANA_CLK_SRC_SEL, 0x444); //MSS_MCANA_CLK_SRC_SEL_CLKSRCSEL = 0x222;
- retVal = SBL_RcmSetPeripheralClock(Rcm_PeripheralId_MSS_MCANA, Rcm_PeripheralClockSource_DPLL_CORE_HSDIV0_CLKOUT2, SBL_MCANA_FREQ_HZ);
- DebugP_assert(retVal == Rcm_Return_SUCCESS);
-
- //HW_WR_REG32(CSL_MSS_RCM_U_BASE+MSS_MCANB_CLK_DIV_VAL, 0x444); //MSS_MCANB_CLK_DIV_VAL_CLKDIVR = 0x444;
- //HW_WR_REG32(CSL_MSS_RCM_U_BASE+MSS_MCANB_CLK_SRC_SEL, 0x444); //MSS_MCANB_CLK_SRC_SEL_CLKSRCSEL = 0x222;
- retVal = SBL_RcmSetPeripheralClock(Rcm_PeripheralId_MSS_MCANB, Rcm_PeripheralClockSource_DPLL_CORE_HSDIV0_CLKOUT2, SBL_MCANB_FREQ_HZ);
- DebugP_assert(retVal == Rcm_Return_SUCCESS);
-
- //HW_WR_REG32(CSL_MSS_RCM_U_BASE+MSS_RTIA_CLK_DIV_VAL, 0x000); //MSS_RTIA_CLK_DIV_VAL_CLKDIVR = 0x444; 200/1
- //HW_WR_REG32(CSL_MSS_RCM_U_BASE+MSS_RTIA_CLK_SRC_SEL, 0x222); //MSS_RTIA_CLK_SRC_SEL_CLKSRCSEL = 0x222;
- retVal = SBL_RcmSetPeripheralClock(Rcm_PeripheralId_MSS_RTIA, Rcm_PeripheralClockSource_SYS_CLK, SBL_MSS_RTIA_FREQ_HZ);
- DebugP_assert(retVal == Rcm_Return_SUCCESS);
-
- //HW_WR_REG32(CSL_MSS_RCM_U_BASE+MSS_RTIB_CLK_DIV_VAL, 0x000); //MSS_RTIB_CLK_DIV_VAL_CLKDIVR = 0x444;
- //HW_WR_REG32(CSL_MSS_RCM_U_BASE+MSS_RTIB_CLK_SRC_SEL, 0x222); //MSS_RTIB_CLK_SRC_SEL_CLKSRCSEL = 0x222;
- retVal = SBL_RcmSetPeripheralClock(Rcm_PeripheralId_MSS_RTIB, Rcm_PeripheralClockSource_SYS_CLK, SBL_MSS_RTIB_FREQ_HZ);
- DebugP_assert(retVal == Rcm_Return_SUCCESS);
-
- //HW_WR_REG32(CSL_MSS_RCM_U_BASE+MSS_RTIC_CLK_DIV_VAL, 0x000); //MSS_RTIC_CLK_DIV_VAL_CLKDIVR = 0x444;
- //HW_WR_REG32(CSL_MSS_RCM_U_BASE+MSS_RTIC_CLK_SRC_SEL, 0x222); //MSS_RTIC_CLK_SRC_SEL_CLKSRCSEL = 0x222;
- retVal = SBL_RcmSetPeripheralClock(Rcm_PeripheralId_MSS_RTIC, Rcm_PeripheralClockSource_SYS_CLK, SBL_MSS_RTIC_FREQ_HZ);
- DebugP_assert(retVal == Rcm_Return_SUCCESS);
-
- //HW_WR_REG32(CSL_MSS_RCM_U_BASE+MSS_WDT_CLK_DIV_VAL, 0x000); //MSS_WDT_CLK_DIV_VAL_CLKDIVR = 0x444;
- //HW_WR_REG32(CSL_MSS_RCM_U_BASE+MSS_WDT_CLK_SRC_SEL, 0x222); //MSS_WDT_CLK_SRC_SEL_CLKSRCSEL = 0x222;
- retVal = SBL_RcmSetPeripheralClock(Rcm_PeripheralId_MSS_WDT, Rcm_PeripheralClockSource_SYS_CLK, SBL_MSS_WDT_FREQ_HZ);
- DebugP_assert(retVal == Rcm_Return_SUCCESS);
-
- //HW_WR_REG32(CSL_MSS_RCM_U_BASE+MSS_QSPI_CLK_DIV_VAL, 0x444); //MSS_QSPI_CLK_DIV_VAL_CLKDIVR = 0x444; 400/5
- //HW_WR_REG32(CSL_MSS_RCM_U_BASE+MSS_QSPI_CLK_SRC_SEL, 0x444); //MSS_QSPI_CLK_SRC_SEL_CLKSRCSEL = 0x444;
- SBL_RcmGetEfuseQSPIConfig(&qspiCfg);
- switch (qspiCfg.QSPIClockFreqConfig)
- {
- case RCM_EFUSE_QSPICLOCKFREQ_40MHz:
- qspiClkFreq = SBL_FREQ_MHZ2HZ(40U);
- break;
- case RCM_EFUSE_QSPICLOCKFREQ_60MHz:
- qspiClkFreq = SBL_FREQ_MHZ2HZ(60U);
- break;
- case RCM_EFUSE_QSPICLOCKFREQ_80MHz:
- qspiClkFreq = SBL_FREQ_MHZ2HZ(80U);
- break;
- default:
- qspiClkFreq = SBL_QSPI_FREQ_HZ;
- }
- retVal = SBL_RcmSetPeripheralClock(Rcm_PeripheralId_MSS_QSPI, Rcm_PeripheralClockSource_DPLL_CORE_HSDIV0_CLKOUT2, qspiClkFreq);
- DebugP_assert(retVal == Rcm_Return_SUCCESS);
-
- //HW_WR_REG32(CSL_MSS_RCM_U_BASE+MSS_SPIA_CLK_DIV_VAL, 0x000); //MSS_SPIA_CLK_DIV_VAL_CLKDIVR = 0x000; 200/1
- //HW_WR_REG32(CSL_MSS_RCM_U_BASE+MSS_SPIA_CLK_SRC_SEL, 0x222); //MSS_SPIA_CLK_SRC_SEL_CLKSRCSEL = 0x222;
- retVal = SBL_RcmSetPeripheralClock(Rcm_PeripheralId_MSS_SPIA, Rcm_PeripheralClockSource_SYS_CLK, SBL_MSS_SPIA_FREQ_HZ);
- DebugP_assert(retVal == Rcm_Return_SUCCESS);
-
- //HW_WR_REG32(CSL_MSS_RCM_U_BASE+MSS_SPIB_CLK_SRC_SEL, 0x222); //MSS_SPIB_CLK_SRC_SEL_CLKSRCSEL = 0x222;
- //HW_WR_REG32(CSL_MSS_RCM_U_BASE+MSS_SPIB_CLK_DIV_VAL, 0x000); //MSS_SPIB_CLK_DIV_VAL_CLKDIVR = 0x000;
- retVal = SBL_RcmSetPeripheralClock(Rcm_PeripheralId_MSS_SPIB, Rcm_PeripheralClockSource_SYS_CLK, SBL_MSS_SPIB_FREQ_HZ);
- DebugP_assert(retVal == Rcm_Return_SUCCESS);
-
- //HW_WR_REG32(CSL_MSS_RCM_U_BASE+MSS_I2C_CLK_DIV_VAL, 0x000); //MSS_I2C_CLK_DIV_VAL_CLKDIVR = 0x000; 200/1
- //HW_WR_REG32(CSL_MSS_RCM_U_BASE+MSS_I2C_CLK_SRC_SEL, 0x222); //MSS_I2C_CLK_SRC_SEL_CLKSRCSEL = 0x222;
- retVal = SBL_RcmSetPeripheralClock(Rcm_PeripheralId_MSS_I2C, Rcm_PeripheralClockSource_SYS_CLK, SBL_MSS_I2C_FREQ_HZ);
- DebugP_assert(retVal == Rcm_Return_SUCCESS);
-
- //HW_WR_REG32(CSL_MSS_RCM_U_BASE+MSS_SCIA_CLK_DIV_VAL, 0x000); //MSS_SCIA_CLK_DIV_VAL_CLKDIVR = 0x000; 200/1
- //HW_WR_REG32(CSL_MSS_RCM_U_BASE+MSS_SCIA_CLK_SRC_SEL, 0x222); //MSS_SCIA_CLK_SRC_SEL_CLKSRCSEL = 0x222;
- retVal = SBL_RcmSetPeripheralClock(Rcm_PeripheralId_MSS_SCIA, Rcm_PeripheralClockSource_SYS_CLK, SBL_MSS_SCIA_FREQ_HZ);
- DebugP_assert(retVal == Rcm_Return_SUCCESS);
-
- //HW_WR_REG32(CSL_MSS_RCM_U_BASE+MSS_SCIB_CLK_DIV_VAL, 0x000); //MSS_SCIB_CLK_DIV_VAL_CLKDIVR = 0x000;
- //HW_WR_REG32(CSL_MSS_RCM_U_BASE+MSS_SCIB_CLK_SRC_SEL, 0x222); //MSS_SCIB_CLK_SRC_SEL_CLKSRCSEL = 0x222;
- retVal = SBL_RcmSetPeripheralClock(Rcm_PeripheralId_MSS_SCIB, Rcm_PeripheralClockSource_SYS_CLK, SBL_MSS_SCIB_FREQ_HZ);
- DebugP_assert(retVal == Rcm_Return_SUCCESS);
-
- //HW_WR_REG32(CSL_MSS_RCM_U_BASE+MSS_CPSW_CLK_DIV_VAL, 0x111); //MSS_CPSW_CLK_DIV_VAL_CLKDIVR = 0x000; 400/2
- //HW_WR_REG32(CSL_MSS_RCM_U_BASE+MSS_CPSW_CLK_SRC_SEL, 0x444); //MSS_CPSW_CLK_SRC_SEL_CLKSRCSEL = 0x222;
- retVal = SBL_RcmSetPeripheralClock(Rcm_PeripheralId_MSS_CPSW, Rcm_PeripheralClockSource_DPLL_CORE_HSDIV0_CLKOUT2, SBL_CPSW_FREQ_HZ);
- DebugP_assert(retVal == Rcm_Return_SUCCESS);
-
- //HW_WR_REG32(CSL_MSS_RCM_U_BASE+MSS_CPTS_CLK_DIV_VAL, 0x111); //MSS_CPTS_CLK_DIV_VAL_CLKDIVR = 0x000; 400/2
- //HW_WR_REG32(CSL_MSS_RCM_U_BASE+MSS_CPTS_CLK_SRC_SEL, 0x444); //MSS_CPTS_CLK_SRC_SEL_CLKSRCSEL = 0x222;
- retVal = SBL_RcmSetPeripheralClock(Rcm_PeripheralId_MSS_CPTS, Rcm_PeripheralClockSource_DPLL_CORE_HSDIV0_CLKOUT2, SBL_CPTS_FREQ_HZ);
- DebugP_assert(retVal == Rcm_Return_SUCCESS);
-
- /* add more modules, add DSP and RCSS */
- //HW_WR_REG32(CSL_DSS_RCM_U_BASE+DSS_RTIA_CLK_DIV_VAL, 0x000); //DSS_RTIA_CLK_DIV_VAL_CLKDIVR = 0x444; 200/1
- //HW_WR_REG32(CSL_DSS_RCM_U_BASE+DSS_RTIA_CLK_SRC_SEL, 0x222); //DSS_RTIA_CLK_SRC_SEL_CLKSRCSEL = 0x222;
- retVal = SBL_RcmSetPeripheralClock(Rcm_PeripheralId_DSS_RTIA, Rcm_PeripheralClockSource_SYS_CLK, SBL_DSS_RTIA_FREQ_HZ);
- DebugP_assert(retVal == Rcm_Return_SUCCESS);
-
- //HW_WR_REG32(CSL_DSS_RCM_U_BASE+DSS_RTIB_CLK_DIV_VAL, 0x000); //DSS_RTIB_CLK_DIV_VAL_CLKDIVR = 0x444;
- //HW_WR_REG32(CSL_DSS_RCM_U_BASE+DSS_RTIB_CLK_SRC_SEL, 0x222); //DSS_RTIB_CLK_SRC_SEL_CLKSRCSEL = 0x222;
- retVal = SBL_RcmSetPeripheralClock(Rcm_PeripheralId_DSS_RTIB, Rcm_PeripheralClockSource_SYS_CLK, SBL_DSS_RTIB_FREQ_HZ);
- DebugP_assert(retVal == Rcm_Return_SUCCESS);
-
- //HW_WR_REG32(CSL_DSS_RCM_U_BASE+DSS_WDT_CLK_DIV_VAL, 0x000); //DSS_WDT_CLK_DIV_VAL_CLKDIVR = 0x444;
- //HW_WR_REG32(CSL_DSS_RCM_U_BASE+DSS_WDT_CLK_SRC_SEL, 0x222); //DSS_WDT_CLK_SRC_SEL_CLKSRCSEL = 0x222;
- retVal = SBL_RcmSetPeripheralClock(Rcm_PeripheralId_DSS_WDT, Rcm_PeripheralClockSource_SYS_CLK, SBL_DSS_WDT_FREQ_HZ);
- DebugP_assert(retVal == Rcm_Return_SUCCESS);
-
- //HW_WR_REG32(CSL_DSS_RCM_U_BASE+DSS_SCIA_CLK_DIV_VAL, 0x000); //DSS_SCIA_CLK_DIV_VAL_CLKDIVR = 0x000; 200/1
- //HW_WR_REG32(CSL_DSS_RCM_U_BASE+DSS_SCIA_CLK_SRC_SEL, 0x222); //DSS_SCIA_CLK_SRC_SEL_CLKSRCSEL = 0x222;
- retVal = SBL_RcmSetPeripheralClock(Rcm_PeripheralId_DSS_SCIA, Rcm_PeripheralClockSource_SYS_CLK, SBL_DSS_SCIA_FREQ_HZ);
- DebugP_assert(retVal == Rcm_Return_SUCCESS);
-
- //HW_WR_REG32(CSL_RCSS_RCM_U_BASE+RCSS_SPIA_CLK_DIV_VAL, 0x000); //RCSS_SPIA_CLK_DIV_VAL_CLKDIVR = 0x000; 200/1
- //HW_WR_REG32(CSL_RCSS_RCM_U_BASE+RCSS_SPIA_CLK_SRC_SEL, 0x222); //RCSS_SPIA_CLK_SRC_SEL_CLKSRCSEL = 0x222;
- retVal = SBL_RcmSetPeripheralClock(Rcm_PeripheralId_RCSS_SCIA, Rcm_PeripheralClockSource_SYS_CLK, SBL_RCSS_SCIA_FREQ_HZ);
- DebugP_assert(retVal == Rcm_Return_SUCCESS);
-
- //HW_WR_REG32(CSL_RCSS_RCM_U_BASE+RCSS_SPIA_CLK_DIV_VAL, 0x000); //RCSS_SPIA_CLK_DIV_VAL_CLKDIVR = 0x000; 200/1
- //HW_WR_REG32(CSL_RCSS_RCM_U_BASE+RCSS_SPIA_CLK_SRC_SEL, 0x222); //RCSS_SPIA_CLK_SRC_SEL_CLKSRCSEL = 0x222;
- retVal = SBL_RcmSetPeripheralClock(Rcm_PeripheralId_RCSS_SPIA, Rcm_PeripheralClockSource_SYS_CLK, SBL_RCSS_SPIA_FREQ_HZ);
- DebugP_assert(retVal == Rcm_Return_SUCCESS);
-
- //HW_WR_REG32(CSL_RCSS_RCM_U_BASE+RCSS_SPIB_CLK_DIV_VAL, 0x000); //RCSS_SPIB_CLK_DIV_VAL_CLKDIVR = 0x000; 200/1
- //HW_WR_REG32(CSL_RCSS_RCM_U_BASE+RCSS_SPIB_CLK_SRC_SEL, 0x222); //RCSS_SPIB_CLK_SRC_SEL_CLKSRCSEL = 0x222;
- retVal = SBL_RcmSetPeripheralClock(Rcm_PeripheralId_RCSS_SPIB, Rcm_PeripheralClockSource_SYS_CLK, SBL_RCSS_SPIB_FREQ_HZ);
- DebugP_assert(retVal == Rcm_Return_SUCCESS);
-
- //HW_WR_REG32(CSL_RCSS_RCM_U_BASE+RCSS_I2CA_CLK_DIV_VAL, 0x000); //RCSS_I2CA_CLK_DIV_VAL_CLKDIVR = 0x000; 200/1
- //HW_WR_REG32(CSL_RCSS_RCM_U_BASE+RCSS_I2CA_CLK_SRC_SEL, 0x222); //RCSS_I2CA_CLK_SRC_SEL_CLKSRCSEL = 0x222;
- retVal = SBL_RcmSetPeripheralClock(Rcm_PeripheralId_RCSS_I2CA, Rcm_PeripheralClockSource_SYS_CLK, SBL_RCSS_I2CA_FREQ_HZ);
- DebugP_assert(retVal == Rcm_Return_SUCCESS);
-
- //HW_WR_REG32(CSL_RCSS_RCM_U_BASE+RCSS_I2CB_CLK_DIV_VAL, 0x000); //RCSS_I2CB_CLK_DIV_VAL_CLKDIVR = 0x000; 200/1
- //HW_WR_REG32(CSL_RCSS_RCM_U_BASE+RCSS_I2CB_CLK_SRC_SEL, 0x222); //RCSS_I2CB_CLK_SRC_SEL_CLKSRCSEL = 0x222;
- retVal = SBL_RcmSetPeripheralClock(Rcm_PeripheralId_RCSS_I2CB, Rcm_PeripheralClockSource_SYS_CLK, SBL_RCSS_I2CB_FREQ_HZ);
- DebugP_assert(retVal == Rcm_Return_SUCCESS);
-
- //HW_WR_REG32(CSL_RCSS_RCM_U_BASE+RCSS_ATL_CLK_DIV_VAL, 0x111); //RCSS_ATL_CLK_DIV_VAL_CLKDIVR = 0x000; 240/2
- //HW_WR_REG32(CSL_RCSS_RCM_U_BASE+RCSS_ATL_CLK_SRC_SEL, 0x666); //RCSS_ATL_CLK_SRC_SEL_CLKSRCSEL = 0x222;
- retVal = SBL_RcmSetPeripheralClock(Rcm_PeripheralId_RCSS_ATL, Rcm_PeripheralClockSource_DPLL_PER_HSDIV0_CLKOUT3, SBL_RCSS_ATL_FREQ_HZ);
- DebugP_assert(retVal == Rcm_Return_SUCCESS);
-
- //HW_WR_REG32(CSL_RCSS_RCM_U_BASE+RCSS_MCASPA_AUX_CLK_DIV_VAL, 0x111); //RCSS_MCASPA_AUX_CLK_DIV_VAL_CLKDIVR = 0x111; 192/2
- //HW_WR_REG32(CSL_RCSS_RCM_U_BASE+RCSS_MCASPA_AUX_CLK_SRC_SEL, 0x222); //RCSS_MCASPA_AUX_CLK_SRC_SEL_CLKSRCSEL = 0x222;
- retVal = SBL_RcmSetPeripheralClock(Rcm_PeripheralId_RCSS_MCASPA_AUX, Rcm_PeripheralClockSource_DPLL_PER_HSDIV0_CLKOUT1 , SBL_RCSS_MCASPA_AUX_FREQ_HZ);
- DebugP_assert(retVal == Rcm_Return_SUCCESS);
-
- //HW_WR_REG32(CSL_RCSS_RCM_U_BASE+RCSS_MCASPB_AUX_CLK_DIV_VAL, 0x111); //RCSS_MCASPB_AUX_CLK_DIV_VAL_CLKDIVR = 0x111; 192/2
- //HW_WR_REG32(CSL_RCSS_RCM_U_BASE+RCSS_MCASPB_AUX_CLK_SRC_SEL, 0x222); //RCSS_MCASPB_AUX_CLK_SRC_SEL_CLKSRCSEL = 0x222;
- retVal = SBL_RcmSetPeripheralClock(Rcm_PeripheralId_RCSS_MCASPB_AUX, Rcm_PeripheralClockSource_DPLL_PER_HSDIV0_CLKOUT1 , SBL_RCSS_MCASPB_AUX_FREQ_HZ);
- DebugP_assert(retVal == Rcm_Return_SUCCESS);
-
- //HW_WR_REG32(CSL_RCSS_RCM_U_BASE+RCSS_MCASPC_AUX_CLK_DIV_VAL, 0x111); //RCSS_MCASPB_AUX_CLK_DIV_VAL_CLKDIVR = 0x111; 192/2
- //HW_WR_REG32(CSL_RCSS_RCM_U_BASE+RCSS_MCASPC_AUX_CLK_SRC_SEL, 0x222); //RCSS_MCASPB_AUX_CLK_SRC_SEL_CLKSRCSEL = 0x222;
- retVal = SBL_RcmSetPeripheralClock(Rcm_PeripheralId_RCSS_MCASPC_AUX, Rcm_PeripheralClockSource_DPLL_PER_HSDIV0_CLKOUT1 , SBL_RCSS_MCASPC_AUX_FREQ_HZ);
- DebugP_assert(retVal == Rcm_Return_SUCCESS);
-
- /* TODO: Rcm Library support for Rcm_PeripheralClockSource_RCSS_ATL_CLKOUT0 clock source */
- //HW_WR_REG32(CSL_RCSS_RCM_U_BASE+RCSS_MCASPA_REF0_CLK_DIV_VAL, 0x111); //RCSS_MCASPA_REF0_CLK_DIV_VAL_CLKDIVR = 0x111; 200/2
- //HW_WR_REG32(CSL_RCSS_RCM_U_BASE+RCSS_MCASPA_REF0_CLK_SRC_SEL, 0x111); //RCSS_MCASPA_REF0_CLK_SRC_SEL_CLKSRCSEL = 0x111;
- //SBL_RcmSetPeripheralClock(Rcm_PeripheralId_RCSS_MCASPA_REF0, Rcm_PeripheralClockSource_RCSS_ATL_CLKOUT0 , SBL_RCSS_MCASPA_REF0_FREQ_HZ);
-
- //HW_WR_REG32(CSL_RCSS_RCM_U_BASE+RCSS_MCASPB_REF0_CLK_DIV_VAL, 0x111); //RCSS_MCASPB_REF0_CLK_DIV_VAL_CLKDIVR = 0x111; 200/2
- //HW_WR_REG32(CSL_RCSS_RCM_U_BASE+RCSS_MCASPB_REF0_CLK_SRC_SEL, 0x111); //RCSS_MCASPB_REF0_CLK_SRC_SEL_CLKSRCSEL = 0x111;
-
- //HW_WR_REG32(CSL_RCSS_RCM_U_BASE+RCSS_MCASPC_REF0_CLK_DIV_VAL, 0x111); //RCSS_MCASPB_REF0_CLK_DIV_VAL_CLKDIVR = 0x111; 200/2
- //HW_WR_REG32(CSL_RCSS_RCM_U_BASE+RCSS_MCASPC_REF0_CLK_SRC_SEL, 0x111); //RCSS_MCASPB_REF0_CLK_SRC_SEL_CLKSRCSEL = 0x111;
-
- //HW_WR_REG32(CSL_RCSS_RCM_U_BASE+RCSS_MCASPA_REF1_CLK_DIV_VAL, 0x111); //RCSS_MCASPA_REF1_CLK_DIV_VAL_CLKDIVR = 0x111; 200/2
- //HW_WR_REG32(CSL_RCSS_RCM_U_BASE+RCSS_MCASPA_REF1_CLK_SRC_SEL, 0x111); //RCSS_MCASPA_REF1_CLK_SRC_SEL_CLKSRCSEL = 0x111;
-
- //HW_WR_REG32(CSL_RCSS_RCM_U_BASE+RCSS_MCASPB_REF1_CLK_DIV_VAL, 0x111); //RCSS_MCASPB_REF1_CLK_DIV_VAL_CLKDIVR = 0x111; 200/2
- //HW_WR_REG32(CSL_RCSS_RCM_U_BASE+RCSS_MCASPB_REF1_CLK_SRC_SEL, 0x111); //RCSS_MCASPB_REF1_CLK_SRC_SEL_CLKSRCSEL = 0x111;
-
- //HW_WR_REG32(CSL_RCSS_RCM_U_BASE+RCSS_MCASPC_REF1_CLK_DIV_VAL, 0x111); //RCSS_MCASPB_REF1_CLK_DIV_VAL_CLKDIVR = 0x111; 200/2
- //HW_WR_REG32(CSL_RCSS_RCM_U_BASE+RCSS_MCASPC_REF1_CLK_SRC_SEL, 0x111); //RCSS_MCASPB_REF1_CLK_SRC_SEL_CLKSRCSEL = 0x111;
-
-}
-
#ifdef __cplusplus
#pragma RETAIN
#pragma LOCATION(SBL_SCRATCH_MEM_START);
diff --git a/packages/ti/boot/sbl/soc/tpr12/sbl_soc_cfg.h b/packages/ti/boot/sbl/soc/tpr12/sbl_soc_cfg.h
index e49eb94cacdc50fe9f012d870c3f71ba325871a5..1228d57e97c7fa31f1c3b68fdf2e1a92cd5fab09 100644 (file)
/* ========================================================================== */
void SBL_SocEarlyInit(void);
void SBL_SocLateInit(void);
-void SBL_moduleClockInit(void);
+extern void SBL_moduleClockInit(void);
+
#endif
diff --git a/packages/ti/boot/sbl/src/qspi/sbl_qspi_boardflash.c b/packages/ti/boot/sbl/src/qspi/sbl_qspi_boardflash.c
index 205ecf59d1f0e883d57b0961c2d9f7315ba3c97e..c7145177c33c2c1ae25ad8c31f732bd5d3e36979 100644 (file)
#include <ti/drv/edma/edma.h>
#endif
+#include <ti/osal/DebugP.h>
#include <ti/drv/spi/src/SPI_osal.h>
#include <ti/drv/uart/UART_stdio.h>
#include <ti/drv/spi/soc/SPI_soc.h>
#if !defined(SBL_BYPASS_QSPI_DRIVER)
Board_flashHandle h = *(Board_flashHandle *) handle;
int32_t retVal;
- Rcm_EfuseQspiConfig qspiEfuseCfg;
uint32_t qspiClkFreq;
SBL_ADD_PROFILE_POINT;
}
retVal = QSPI_socGetInitCfg(BOARD_QSPI_NOR_INSTANCE, &qspi_cfg);
DebugP_assert(retVal == 0);
-
- SBL_RcmGetEfuseQSPIConfig(&qspiEfuseCfg);
- switch (qspiEfuseCfg.QSPIClockFreqConfig)
- {
- case RCM_EFUSE_QSPICLOCKFREQ_40MHz:
- qspiClkFreq = SBL_FREQ_MHZ2HZ(40U);
- break;
- case RCM_EFUSE_QSPICLOCKFREQ_60MHz:
- qspiClkFreq = SBL_FREQ_MHZ2HZ(60U);
- break;
- case RCM_EFUSE_QSPICLOCKFREQ_80MHz:
- qspiClkFreq = SBL_FREQ_MHZ2HZ(80U);
- break;
- default:
- qspiClkFreq = SBL_QSPI_FREQ_HZ;
- }
-#if !defined(SBL_SKIP_BRD_CFG_PM)
+#ifdef SOC_TPR12
{
- retVal = SBL_RcmSetPeripheralClock(Rcm_PeripheralId_MSS_QSPI, Rcm_PeripheralClockSource_DPLL_CORE_HSDIV0_CLKOUT2, qspiClkFreq);
- DebugP_assert(retVal == Rcm_Return_SUCCESS);
+ Rcm_Return rcmRetVal;
+
+ rcmRetVal = SBL_RcmGetPeripheralFreq(Rcm_PeripheralId_MSS_QSPI, &qspiClkFreq);
+ DebugP_assert(rcmRetVal == Rcm_Return_SUCCESS);
}
+#else
+ #error "Configure QSPI qspiClkFreq for the SOC"
+ qspiClkFreq = 0;
#endif
qspi_cfg.funcClk = qspiClkFreq;
SBL_log(SBL_LOG_MAX, "qspiFunClk = %d Hz \n", qspi_cfg.funcClk);
index 695f2786aad6795059e16c5e822c4f9fb7587ed4..2a8374dd284ed5abf4170a1a60315b9f958dc116 100644 (file)
/* depending on whether SysFwConfigPm has run */
/* or not */
#if defined(SOC_TPR12)
- SBL_uartInit(SBL_RcmGetPeripheralClockFrequency(Rcm_PeripheralClockSource_SYS_CLK));
+ {
+ uint32_t uartFreq;
+ Rcm_Return rcmRetVal;
+
+ rcmRetVal = SBL_RcmGetPeripheralFreq(Rcm_PeripheralId_MSS_SCIA, &uartFreq);
+ DebugP_assert(rcmRetVal == Rcm_Return_SUCCESS);
+ SBL_uartInit(uartFreq);
+ }
#else
#if defined(DSBL_SKIP_BRD_CFG_PM) || defined(SBL_SKIP_SYSFW_INIT)
SBL_uartInit(SBL_ROM_UART_MODULE_INPUT_CLK);
diff --git a/packages/ti/boot/sbl/src/uart/sbl_xmodem.c b/packages/ti/boot/sbl/src/uart/sbl_xmodem.c
index 5be41f17150bcab1883fc4f6e789e169c58ffd8d..aa8eb5d796473ca755f2b86d4a8f37251fb72c32 100644 (file)
#define SBL_XMODEM_DELAY (0x3FFFFF)
#ifdef SOC_TPR12
#include <ti/csl/soc.h>
+#include <ti/csl/cslr_sci.h>
+
+/* TPR12 Does not have CSL-FL layer for UART. Som implementing the
+ * UART character read function here
+ */
+
+static uint32_t UartSci_isRxFree (const CSL_sciRegs* ptrSCIRegs)
+{
+ return CSL_FEXT(ptrSCIRegs->SCIFLR, SCI_SCIFLR_RXRDY);
+}
+
+static uint8_t UartSci_getCh (const CSL_sciRegs* ptrSCIRegs)
+{
+ return (uint8_t)CSL_FEXT(ptrSCIRegs->SCIRD, SCI_SCIRD_RD);
+}
+
uint32_t READBYTE_WITH_TIMEOUT(uint32_t xmodemUartAddr, uint32_t delayMs, uint8_t *pData)
{
- *pData = UART_getc();
- return TRUE;
+ int32_t timeCounter = delayMs;
+ bool charReceived = false;
+ const CSL_sciRegs* ptrSCIRegs = (const CSL_sciRegs*)xmodemUartAddr;
+
+ /* Is the receiver free? */
+ while (timeCounter > 10)
+ {
+ if (UartSci_isRxFree(ptrSCIRegs) == 1U)
+ {
+ /* YES: Read out a character from the buffer. */
+ *pData = UartSci_getCh (ptrSCIRegs);
+ charReceived = true;
+ break;
+ }
+ timeCounter--;
+ }
+ return charReceived;
}
#else
#ifdef SOC_K2G