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raw | patch | inline | side by side (parent: 9065169)
raw | patch | inline | side by side (parent: 9065169)
author | Danny Jochelson <dsjochel@ti.com> | |
Thu, 3 Sep 2020 15:06:04 +0000 (10:06 -0500) | ||
committer | Sivaraj R <a0393606@ti.com> | |
Fri, 18 Sep 2020 15:43:29 +0000 (10:43 -0500) |
Added reception of ECC events from both MCU ESM and Main ESM.
For MSMC ECC Aggregator base address, the SDR needs to use RAT to
map the address.
Added more details in ECC callback to report bitErrorOffset, group,
and RAM ID.
Added RAT mapping of ECC Aggregators for MSMC instance.
Confirmed through ECC example that we can use these SDR updates to
receive MSMC Interconnect ECC events properly, and MCU R5F wrapper
and interconnect ECC events.
Added basic CBASS ECC aggegator support.
Added Group information for a single Interconnect RAM ID on MCU R5F
ECC aggregator.
Tied in updated J721E CSLR values for ECC aggregators and RAM ID's.
Ensured that AM65xx SDR still builds correctly.
Modified how SDR memEntries tables are searched (since there is no
guarantee that Wrapper types start at index 0).
For MSMC ECC Aggregator base address, the SDR needs to use RAT to
map the address.
Added more details in ECC callback to report bitErrorOffset, group,
and RAM ID.
Added RAT mapping of ECC Aggregators for MSMC instance.
Confirmed through ECC example that we can use these SDR updates to
receive MSMC Interconnect ECC events properly, and MCU R5F wrapper
and interconnect ECC events.
Added basic CBASS ECC aggegator support.
Added Group information for a single Interconnect RAM ID on MCU R5F
ECC aggregator.
Tied in updated J721E CSLR values for ECC aggregators and RAM ID's.
Ensured that AM65xx SDR still builds correctly.
Modified how SDR memEntries tables are searched (since there is no
guarantee that Wrapper types start at index 0).
17 files changed:
index a295417e7c36f6353f4652a774b96c9aa1b94eac..1fe318e85e84658b0ec3ab5c50c2a10ebc3c7988 100644 (file)
#include <stdint.h>
#include <stdbool.h>
+#include <sdr_esm.h>
#include "sdr_common.h"
SDR_INJECT_ECC_ERROR_FORCING_2BIT_N_ROW_REPEAT = 8,
} SDR_ECC_InjectErrorType;
+
+/** ---------------------------------------------------------------------------
+ * \brief This enumerator defines the different ECC RAM ID types
+ * ----------------------------------------------------------------------------
+ */
+typedef enum {
+ SDR_ECC_RAM_ID_TYPE_WRAPPER = 0,
+ /**< Ecc RAM ID Wrapper type */
+ SDR_ECC_RAM_ID_TYPE_INTERCONNECT = 1,
+ /**< Ecc RAM ID Interconnect/CBASS type */
+} SDR_ECC_RamIdType;
+
/* @} */
/**
*/
typedef uint32_t SDR_ECC_MemType;
+
/** \brief Select RAM MCU R5F core 0 memory type */
#define SDR_ECC_MEMTYPE_MCU_R5F0_CORE (0u)
/** \brief Select RAM MCU R5F core 1 memory type */
#define SDR_ECC_MEMTYPE_MCU_PDMA1 (13u)
/** \brief Select MCU PSRAM0 type */
#define SDR_ECC_MEMTYPE_MCU_PSRAM0 (14u)
+/** \brief Select MCU CBASS type */
+#define SDR_ECC_MEMTYPE_MCU_CBASS_ECC_AGGR0 (15u)
+
+
+/* These aggregators require using RAT to map into memory space */
+
+/** \brief Select Main MSMC AGGR0 type */
+#define SDR_ECC_MEMTYPE_MAIN_MSMC_AGGR0 (16u)
+/** \brief Select Main MSMC AGGR1 type */
+#define SDR_ECC_MEMTYPE_MAIN_MSMC_AGGR1 (17u)
+/** \brief Select Main MSMC AGGR2 type */
+#define SDR_ECC_MEMTYPE_MAIN_MSMC_AGGR2 (18u)
+
+// TODO - REMOVE
+/** \brief Select Main A72 AGGR0 type */
+#define SDR_ECC_MEMTYPE_MAIN_A72_AGGR0 (19u)
+
/** ---------------------------------------------------------------------------
* \brief This enumerator indicate ECC memory Sub Type
*/
typedef uint32_t SDR_ECC_MemSubType;
+/* The following are the memory sub type for Memory type
+ SDR_ECC_MEMTYPE_MCU_R5F0_CORE & SDR_ECC_MEMTYPE_MCU_R5F1_CORE */
+
/** \brief Select memory subtype ITAG RAM0 */
#define SDR_ECC_R5F_MEM_SUBTYPE_ITAG_RAM0_VECTOR_ID (0U)
/** \brief Select memory subtype ITAG RAM1 */
/** \brief Select memory subtype ECC AGGR EDC */
#define SDR_ECC_R5F_MEM_SUBTYPE_ECC_AGGR_EDC_ID (35U)
+/** \brief Select memory subtype MSMC MMR BusECC */
+#define SDR_ECC_MAIN_MSMC_MEM_INTERCONN_SUBTYPE (20) /* CSL_ECC_AGGR_COMPUTE_CLUSTER0_MSMC_ES_ECC_AGGR0_MSMC_MMR_BUSECC_ID */
+/** \brief Select memory subtype MSMC CLEC SRAM ECC */
+#define SDR_ECC_MAIN_MSMC_MEM_WRAPPER_SUBTYPE (100) /* CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CLEC_SRAM_RAMECC_ID */
+
+/* The following are the memory sub type for Memory type
+ SDR_ECC_MEMTYPE_MCU_CBASS */
+
+/** \brief Select memory subtype write ramecc */
+#define SDR_ECC_MCU_CBASS_MEM_SUBTYPE_WR_RAMECC_ID (0U)
+/** \brief Select memory subtype read ramecc */
+#define SDR_ECC_MCU_CBASS_MEM_SUBTYPE_RD_RAMECC_ID (1U)
+/** \brief Select memory subtype edc control */
+#define SDR_ECC_MCU_CBASS_MEM_SUBTYPE_EDC_CTRL_ID (2U)
+
+
+
+/** ---------------------------------------------------------------------------
+ * \brief This enumerator defines the different types of ECC memory Checker
+ * Group types for Interconnect RAM ID's
+ * ----------------------------------------------------------------------------
+ */
+typedef enum {
+ SDR_ECC_GROUP_CHECKER_TYPE_REDUNDANT = 0,
+ /**< Ecc Group Checker Redundant type */
+ SDR_ECC_GROUP_CHECKER_TYPE_PARITY = 1,
+ /**< Ecc Group Checker Parity type */
+ SDR_ECC_GROUP_CHECKER_TYPE_EDC = 2,
+ /**< Ecc Group Checker EDC type */
+} SDR_ECC_GrpChkType;
+
+
+/** ---------------------------------------------------------------------------
+ * \brief This enumerator indicates ECC memory SubSubType (Checker Groups)
+ * for SDR_ECC_R5F_MEM_SUBTYPE_VBUSM2AXI_EDC_VECTOR_ID Memory Subtype
+ * (Interconnect RAM ID Type)
+ *
+ * ----------------------------------------------------------------------------
+ */
+typedef uint32_t SDR_ECC_MemSubSubType;
+
+/** \brief Select memory subsubtype VBUSM2AXI_EDC_VECTOR_SRC_CREQ */
+#define SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_SRC_CREQ (0U)
+/** \brief Select memory subsubtype VBUSM2AXI_EDC_VECTOR_INT_UNCOR_CROUTEID */
+#define SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_INT_UNCOR_CROUTEID (1U)
+/** \brief Select memory subsubtype VBUSM2AXI_EDC_VECTOR_INT_UNCOR_CORDERID */
+#define SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_INT_UNCOR_CORDERID (2U)
+/** \brief Select memory subsubtype VBUSM2AXI_EDC_VECTOR_INT_UNCOR_CID */
+#define SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_INT_UNCOR_CID (3U)
+/** \brief Select memory subsubtype VBUSM2AXI_EDC_VECTOR_INT_UNCOR_CADDRESS */
+#define SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_INT_UNCOR_CADDRESS (4U)
+/** \brief Select memory subsubtype VBUSM2AXI_EDC_VECTOR_INT_UNCOR_CDIR */
+#define SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_INT_UNCOR_CDIR (5U)
+/** \brief Select memory subsubtype VBUSM2AXI_EDC_VECTOR_INT_UNCOR_CBYTECNT */
+#define SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_INT_UNCOR_CBYTECNT (6U)
+/** \brief Select memory subsubtype VBUSM2AXI_EDC_VECTOR_INT_UNCOR_CAMODE */
+#define SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_INT_UNCOR_CAMODE (7U)
+/** \brief Select memory subsubtype VBUSM2AXI_EDC_VECTOR_INT_UNCOR_CCLSIZE */
+#define SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_INT_UNCOR_CCLSIZE (8U)
+/** \brief Select memory subsubtype VBUSM2AXI_EDC_VECTOR_INT_UNCOR_CSECURE */
+#define SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_INT_UNCOR_CSECURE (9U)
+/** \brief Select memory subsubtype VBUSM2AXI_EDC_VECTOR_INT_UNCOR_CPRIV */
+#define SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_INT_UNCOR_CPRIV (10U)
+/** \brief Select memory subsubtype VBUSM2AXI_EDC_VECTOR_INT_UNCOR_CDTYPE */
+#define SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_INT_UNCOR_CDTYPE (11U)
+/** \brief Select memory subsubtype VBUSM2AXI_EDC_VECTOR_INT_UNCOR_CEMUDBG */
+#define SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_INT_UNCOR_CEMUDBG (12U)
+/** \brief Select memory subsubtype VBUSM2AXI_EDC_VECTOR_INT_UNCOR_CINTEREST */
+#define SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_INT_UNCOR_CINTEREST (13U)
+/** \brief Select memory subsubtype VBUSM2AXI_EDC_VECTOR_INT_UNCOR_CFLUSH */
+#define SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_INT_UNCOR_CFLUSH (14U)
+/** \brief Select memory subsubtype VBUSM2AXI_EDC_VECTOR_INT_UNCOR_CPRIORITY */
+#define SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_INT_UNCOR_CPRIORITY (15U)
+/** \brief Select memory subsubtype VBUSM2AXI_EDC_VECTOR_INT_UNCOR_CRSEL */
+#define SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_INT_UNCOR_CRSEL (16U)
+/** \brief Select memory subsubtype VBUSM2AXI_EDC_VECTOR_INT_UNCOR_CCINNER */
+#define SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_INT_UNCOR_CCINNER (17U)
+/** \brief Select memory subsubtype VBUSM2AXI_EDC_VECTOR_INT_UNCOR_CMEMTYPE */
+#define SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_INT_UNCOR_CMEMTYPE (18U)
+/** \brief Select memory subsubtype VBUSM2AXI_EDC_VECTOR_INT_UNCOR_CSDOMAIN */
+#define SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_INT_UNCOR_CSDOMAIN (19U)
+/** \brief Select memory subsubtype VBUSM2AXI_EDC_VECTOR_SRC_WREQ */
+#define SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_SRC_WREQ (20U)
+/** \brief Select memory subsubtype VBUSM2AXI_EDC_VECTOR_INT_UNCOR_WDATA_31_0 */
+#define SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_INT_UNCOR_WDATA_31_0 (21U)
+/** \brief Select memory subsubtype VBUSM2AXI_EDC_VECTOR_INT_UNCOR_WDATA_63_32 */
+#define SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_INT_UNCOR_WDATA_63_32 (22U)
+/** \brief Select memory subsubtype VBUSM2AXI_EDC_VECTOR_INT_UNCOR_WBYTEN */
+#define SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_INT_UNCOR_WBYTEN (23U)
+/** \brief Select memory subsubtype VBUSM2AXI_EDC_VECTOR_SRC_SREADY */
+#define SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_SRC_SREADY (24U)
+/** \brief Select memory subsubtype VBUSM2AXI_EDC_VECTOR_SRC_RMREADY */
+#define SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_SRC_RMREADY (25U)
+/** \brief Select memory subsubtype VBUSM2AXI_EDC_VECTOR_CFIFO_STATE */
+#define SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_CFIFO_STATE (26U)
+/** \brief Select memory subsubtype VBUSM2AXI_EDC_VECTOR_WCFIFO_WR_PTR */
+#define SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_WCFIFO_WR_PTR (27U)
+/** \brief Select memory subsubtype VBUSM2AXI_EDC_VECTOR_WCFIFO_RD_PTR */
+#define SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_WCFIFO_RD_PTR (28U)
+/** \brief Select memory subsubtype VBUSM2AXI_EDC_VECTOR_WCFIFO_OCC */
+#define SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_WCFIFO_OCC (29U)
+/** \brief Select memory subsubtype VBUSM2AXI_EDC_VECTOR_WCFIFO_AOCC */
+#define SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_WCFIFO_AOCC (30U)
+/** \brief Select memory subsubtype VBUSM2AXI_EDC_VECTOR_WCFIFO_RD_RDY */
+#define SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_WCFIFO_RD_RDY (31U)
+/** \brief Select memory subsubtype VBUSM2AXI_EDC_VECTOR_WCFIFO_WR_RDY */
+#define SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_WCFIFO_WR_RDY (32U)
+/** \brief Select memory subsubtype VBUSM2AXI_EDC_VECTOR_WCFIFO_OCC_IS_ONE */
+#define SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_WCFIFO_OCC_IS_ONE (33U)
+/** \brief Select memory subsubtype VBUSM2AXI_EDC_VECTOR_WCFIFO_OCC_IS_ZERO */
+#define SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_WCFIFO_OCC_IS_ZERO (34U)
+/** \brief Select memory subsubtype VBUSM2AXI_EDC_VECTOR_WDFIFO_STATE */
+#define SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_WDFIFO_STATE (35U)
+/** \brief Select memory subsubtype VBUSM2AXI_EDC_VECTOR_WSFIFO_STATE */
+#define SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_WSFIFO_STATE (36U)
+/** \brief Select memory subsubtype VBUSM2AXI_EDC_VECTOR_SFIFO_OCC */
+#define SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_SFIFO_OCC (37U)
+/** \brief Select memory subsubtype VBUSM2AXI_EDC_VECTOR_SFIFO_AOCC */
+#define SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_SFIFO_AOCC (38U)
+/** \brief Select memory subsubtype VBUSM2AXI_EDC_VECTOR_SFIFO_RD_RDY */
+#define SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_SFIFO_RD_RDY (39U)
+/** \brief Select memory subsubtype VBUSM2AXI_EDC_VECTOR_SFIFO_WR_RDY */
+#define SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_SFIFO_WR_RDY (40U)
+/** \brief Select memory subsubtype VBUSM2AXI_EDC_VECTOR_SFIFO_OCC_IS_ONE */
+#define SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_SFIFO_OCC_IS_ONE (41U)
+/** \brief Select memory subsubtype VBUSM2AXI_EDC_VECTOR_SFIFO_OCC_IS_ZERO */
+#define SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_SFIFO_OCC_IS_ZERO (42U)
+/** \brief Select memory subsubtype VBUSM2AXI_EDC_VECTOR_RDFIFO_OCC */
+#define SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_RDFIFO_OCC (43U)
+/** \brief Select memory subsubtype VBUSM2AXI_EDC_VECTOR_RDFIFO_AOCC */
+#define SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_RDFIFO_AOCC (44U)
+/** \brief Select memory subsubtype VBUSM2AXI_EDC_VECTOR_RDFIFO_RD_RDY */
+#define SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_RDFIFO_RD_RDY (45U)
+/** \brief Select memory subsubtype VBUSM2AXI_EDC_VECTOR_RDFIFO_WR_RDY */
+#define SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_RDFIFO_WR_RDY (46U)
+/** \brief Select memory subsubtype VBUSM2AXI_EDC_VECTOR_RDFIFO_OCC_IS_ONE */
+#define SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_RDFIFO_OCC_IS_ONE (47U)
+/** \brief Select memory subsubtype VBUSM2AXI_EDC_VECTOR_RDFIFO_OCC_IS_ZERO */
+#define SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_RDFIFO_OCC_IS_ZERO (48U)
+
/** /brief Format of ECC error Call back function */
typedef void (*SDR_ECC_ErrorCallback_t) (uint32_t errorSrc, uint32_t address);
/**< Address to inject error */
uint32_t flipBitMask;
/**< Bit location to flip bits */
+ SDR_ECC_MemSubSubType chkGrp;
+ /**< Group checker (for Interconnect RAM ID's only) */
} SDR_ECC_InjectErrorConfig_t;
/* @} */
* @{
*/
+/** ============================================================================*
+ *
+ * \brief Initializes an ESM module for usage with ECC module
+ *
+ * \param esmInstType: Instance of ESM
+ *
+ * \return SDR_PASS : Success; SDR_FAIL for failures
+ */
+SDR_Result SDR_ECC_initEsm (const SDR_ESM_InstanceType esmInstType);
+
/** ============================================================================*
*
* \brief Initializes ECC module for ECC detection
*
* \param errorSrc: Error source for the ECC error event.
* \param address: Address at which the ECC error occurred.
+ * \param ramId: RAM ID at which the ECC error occurred.
+ * \param bitLocation: bitLocation at which the ECC error occurred.
+ * \param bitErrorGroup: group checker that reported the error
+ * (Interconnect ECC type only).
*
*
* \return None
*/
-void SDR_ECC_applicationCallbackFunction(uint32_t errorSrc, uint32_t address);
+void SDR_ECC_applicationCallbackFunction(uint32_t errorSrc,
+ uint32_t address,
+ uint32_t ramId,
+ uint64_t bitErrorOffset,
+ uint32_t bitErrorGroup);
/* @} */
index 920e8cfde74b871c3d0f5eb342fb444ce863fbe8..2fac043344bfbd893df1de34b3eb5079003343cd 100644 (file)
/** \brief Address field: Error Address invalid */
#define SDR_ESM_ERRORADDR_INVALID (0xffffffffu)
+/** \brief Address field: Error RAM ID invalid */
+#define SDR_ESM_ERRORRAMID_INVALID (0xffffffffu)
+
+/** \brief Address field: Error Bit Error Offset invalid */
+#define SDR_ESM_ERRORBITOFFSET_INVALID (0xffffffffffffffffu)
+
+/** \brief Address field: Error Bit Error Group invalid */
+#define SDR_ESM_ERRORBITGROUP_INVALID (0xffffffffu)
+
/** \brief Maximum number of EVENT words */
#define SDR_ESM_MAX_EVENT_MAP_NUM_WORDS (32u)
#define SDR_ESM_ECC_PARAM_MCU_CPU1_SEC_ERROR (3u)
/** \brief MCU CPU1 detected 2-bit ECC error source */
#define SDR_ESM_ECC_PARAM_MCU_CPU1_DED_ERROR (4u)
+/** \brief MCU CBASS detected 1-bit ECC error source */
+#define SDR_ESM_ECC_PARAM_MCU_CBASS_SEC_ERROR (5u)
+/** \brief MCU CBASS detected 2-bit ECC error source */
+#define SDR_ESM_ECC_PARAM_MCU_CBASS_DED_ERROR (6u)
+
+
+/** \brief Main MSMC ECC AGGR0 detected 1-bit ECC error source */
+#define SDR_ESM_ECC_PARAM_MAIN_MSMC_AGGR0_SEC_ERROR (10001u)
+/** \brief Main MSMC ECC AGGR0 detected 2-bit ECC error source */
+#define SDR_ESM_ECC_PARAM_MAIN_MSMC_AGGR0_DED_ERROR (10002u)
+/** \brief Main A72 ECC AGGR0 detected 1-bit ECC error source */
+#define SDR_ESM_ECC_PARAM_MAIN_A72_AGGR0_SEC_ERROR (10003u)
+/** \brief Main A72 ECC AGGR0 detected 2-bit ECC error source */
+#define SDR_ESM_ECC_PARAM_MAIN_A72_AGGR0_DED_ERROR (10004u)
+
/* @} */
/* @} */
index f9f1583f7c1576d6893c93e20d6d97fca8d14ac8..0e695ecf37382a1a9a01492c7d6a6c1d2a539908 100644 (file)
/** \brief Format of Call back function for ECC error events */
-typedef void (*SDR_EXCEPTION_ECCCallback_t) (uint32_t intSource, uint32_t errorAddr);
+typedef void (*SDR_EXCEPTION_ECCCallback_t) (uint32_t intSource,
+ uint32_t errorAddr,
+ uint32_t ramId,
+ uint64_t bitErrorOffset,
+ uint32_t bitErrorGroup);
/** \brief Format of Call back function for exception */
typedef void (*SDR_EXCEPTION_Callback_t) (void);
diff --git a/packages/ti/diag/sdr/src/am65xx/sdr_ecc_soc.h b/packages/ti/diag/sdr/src/am65xx/sdr_ecc_soc.h
index 3cd1ec21b0582461f8c4572d9cd1f3bc4fd57293..ee0a59ad6b6f1e8552e141594286d5f0e4080c9f 100644 (file)
/* define MAX entry based on list of Subtypes */
#define SDR_PULSAR_CPU_RAM_ID_TABLE_MAX_ENTRIES (CSL_ECCAGGR_PULSAR_SL_CPU0_KS_VIM_RAMECC_VECTOR_ID+1u)
+
+/* ECC Row Widths for MCU Pulsar RAM ID's with Wrapper type
+ * metadata width = (ecc_row_width) + 2 + log2(ecc_row_width) */
+#define CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM0_ROW_SIZE (22U)
+#define CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM1_ROW_SIZE (22U)
+#define CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM2_ROW_SIZE (22U)
+#define CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM3_ROW_SIZE (22U)
+#define CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK0_ROW_SIZE (64U)
+#define CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK1_ROW_SIZE (64U)
+#define CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK2_ROW_SIZE (64U)
+#define CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK3_ROW_SIZE (64U)
+#define CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM0_ROW_SIZE (22U)
+#define CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM1_ROW_SIZE (22U)
+#define CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM2_ROW_SIZE (22U)
+#define CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM3_ROW_SIZE (22U)
+#define CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDIRTY_RAM_ROW_SIZE (22U)
+#define CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM0_ROW_SIZE (32U)
+#define CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM1_ROW_SIZE (32U)
+#define CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM2_ROW_SIZE (32U)
+#define CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM3_ROW_SIZE (32U)
+#define CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM4_ROW_SIZE (32U)
+#define CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM5_ROW_SIZE (32U)
+#define CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM6_ROW_SIZE (32U)
+#define CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM7_ROW_SIZE (32U)
+#define CSL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_ROW_SIZE (32U)
+#define CSL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_ROW_SIZE (32U)
+#define CSL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_ROW_SIZE (32U)
+#define CSL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_ROW_SIZE (32U)
+#define CSL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_ROW_SIZE (32U)
+#define CSL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_ROW_SIZE (32U)
+#define CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_ROW_SIZE (32U)
+
+
+
/** ---------------------------------------------------------------------------
* @brief This structure holds the list of Ram Ids for each memory subtype
* ----------------------------------------------------------------------------
@@ -89,34 +123,90 @@ const SDR_RAMIdEntry_t SDR_ECC_mcuArmssRamIdTable[SDR_PULSAR_CPU_RAM_ID_TABLE_MA
*/
const SDR_MemConfig_t SDR_ECC_mcuArmssMemEntries[SDR_PULSAR_CPU_RAM_ID_TABLE_MAX_ENTRIES] =
{
- {0u, CSL_ECCAGGR_PULSAR_SL_CPU0_ITAG_RAM0_SIZE, 4u, ((bool)false) },
- {0u, CSL_ECCAGGR_PULSAR_SL_CPU0_ITAG_RAM1_SIZE, 4u, ((bool)false) },
- {0u, CSL_ECCAGGR_PULSAR_SL_CPU0_ITAG_RAM2_SIZE, 4u, ((bool)false) },
- {0u, CSL_ECCAGGR_PULSAR_SL_CPU0_ITAG_RAM3_SIZE, 4u, ((bool)false) },
- {0u, CSL_ECCAGGR_PULSAR_SL_CPU0_IDATA_BANK0_SIZE, 4u, ((bool)false) },
- {0u, CSL_ECCAGGR_PULSAR_SL_CPU0_IDATA_BANK1_SIZE, 4u, ((bool)false) },
- {0u, CSL_ECCAGGR_PULSAR_SL_CPU0_IDATA_BANK2_SIZE, 4u, ((bool)false) },
- {0u, CSL_ECCAGGR_PULSAR_SL_CPU0_IDATA_BANK3_SIZE, 4u, ((bool)false) },
- {0u, CSL_ECCAGGR_PULSAR_SL_CPU0_DTAG_RAM0_SIZE, 4u, ((bool)false) },
- {0u, CSL_ECCAGGR_PULSAR_SL_CPU0_DTAG_RAM1_SIZE, 4u, ((bool)false) },
- {0u, CSL_ECCAGGR_PULSAR_SL_CPU0_DTAG_RAM2_SIZE, 4u, ((bool)false) },
- {0u, CSL_ECCAGGR_PULSAR_SL_CPU0_DTAG_RAM3_SIZE, 4u, ((bool)false) },
- {0u, CSL_ECCAGGR_PULSAR_SL_CPU0_DDIRTY_RAM_SIZE, 4u, ((bool)false) },
- {0u, CSL_ECCAGGR_PULSAR_SL_CPU0_DDATA_RAM0_SIZE, 4u, ((bool)false) },
- {0u, CSL_ECCAGGR_PULSAR_SL_CPU0_DDATA_RAM1_SIZE, 4u, ((bool)false) },
- {0u, CSL_ECCAGGR_PULSAR_SL_CPU0_DDATA_RAM2_SIZE, 4u, ((bool)false) },
- {0u, CSL_ECCAGGR_PULSAR_SL_CPU0_DDATA_RAM3_SIZE, 4u, ((bool)false) },
- {0u, CSL_ECCAGGR_PULSAR_SL_CPU0_DDATA_RAM4_SIZE, 4u, ((bool)false) },
- {0u, CSL_ECCAGGR_PULSAR_SL_CPU0_DDATA_RAM5_SIZE, 4u, ((bool)false) },
- {0u, CSL_ECCAGGR_PULSAR_SL_CPU0_DDATA_RAM6_SIZE, 4u, ((bool)false) },
- {0u, CSL_ECCAGGR_PULSAR_SL_CPU0_DDATA_RAM7_SIZE, 4u, ((bool)false) },
- {0u, CSL_ECCAGGR_PULSAR_SL_CPU0_ATCM0_BANK0_SIZE, 8u, ((bool)true) },
- {0x4u, CSL_ECCAGGR_PULSAR_SL_CPU0_ATCM0_BANK1_SIZE, 8u, ((bool)true) },
- {0x41010000u, CSL_ECCAGGR_PULSAR_SL_CPU0_B0TCM0_BANK0_SIZE, 16u, ((bool)true) },
- {0x41010004u, CSL_ECCAGGR_PULSAR_SL_CPU0_B0TCM0_BANK1_SIZE, 16u, ((bool)true) },
- {0x41010008u, CSL_ECCAGGR_PULSAR_SL_CPU0_B1TCM0_BANK0_SIZE, 16u, ((bool)true) },
- {0x4101000cu, CSL_ECCAGGR_PULSAR_SL_CPU0_B1TCM0_BANK1_SIZE, 16u, ((bool)true) },
- {0x40f82000u, CSL_ECCAGGR_PULSAR_SL_CPU0_KS_VIM_RAMECC_SIZE, 4u, ((bool)true) },
+ {SDR_ECC_R5F_MEM_SUBTYPE_ITAG_RAM0_VECTOR_ID, 0u,
+ CSL_ECCAGGR_PULSAR_SL_CPU0_ITAG_RAM0_SIZE, 4u,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM0_ROW_SIZE, ((bool)false) },
+ {SDR_ECC_R5F_MEM_SUBTYPE_ITAG_RAM1_VECTOR_ID, 0u,
+ CSL_ECCAGGR_PULSAR_SL_CPU0_ITAG_RAM1_SIZE, 4u,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM1_ROW_SIZE, ((bool)false) },
+ {SDR_ECC_R5F_MEM_SUBTYPE_ITAG_RAM2_VECTOR_ID, 0u,
+ CSL_ECCAGGR_PULSAR_SL_CPU0_ITAG_RAM2_SIZE, 4u,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM2_ROW_SIZE, ((bool)false) },
+ {SDR_ECC_R5F_MEM_SUBTYPE_ITAG_RAM3_VECTOR_ID, 0u,
+ CSL_ECCAGGR_PULSAR_SL_CPU0_ITAG_RAM3_SIZE, 4u,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM3_ROW_SIZE, ((bool)false) },
+ {SDR_ECC_R5F_MEM_SUBTYPE_IDATA_BANK0_VECTOR_ID, 0u,
+ CSL_ECCAGGR_PULSAR_SL_CPU0_IDATA_BANK0_SIZE, 4u,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK0_ROW_SIZE, ((bool)false) },
+ {SDR_ECC_R5F_MEM_SUBTYPE_IDATA_BANK1_VECTOR_ID, 0u,
+ CSL_ECCAGGR_PULSAR_SL_CPU0_IDATA_BANK1_SIZE, 4u,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK1_ROW_SIZE, ((bool)false) },
+ {SDR_ECC_R5F_MEM_SUBTYPE_IDATA_BANK2_VECTOR_ID, 0u,
+ CSL_ECCAGGR_PULSAR_SL_CPU0_IDATA_BANK2_SIZE, 4u,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK2_ROW_SIZE, ((bool)false) },
+ {SDR_ECC_R5F_MEM_SUBTYPE_IDATA_BANK3_VECTOR_ID, 0u,
+ CSL_ECCAGGR_PULSAR_SL_CPU0_IDATA_BANK3_SIZE, 4u,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK3_ROW_SIZE, ((bool)false) },
+ {SDR_ECC_R5F_MEM_SUBTYPE_DTAG_RAM0_VECTOR_ID, 0u,
+ CSL_ECCAGGR_PULSAR_SL_CPU0_DTAG_RAM0_SIZE, 4u,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM0_ROW_SIZE, ((bool)false) },
+ {SDR_ECC_R5F_MEM_SUBTYPE_DTAG_RAM1_VECTOR_ID, 0u,
+ CSL_ECCAGGR_PULSAR_SL_CPU0_DTAG_RAM1_SIZE, 4u,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM1_ROW_SIZE, ((bool)false) },
+ {SDR_ECC_R5F_MEM_SUBTYPE_DTAG_RAM2_VECTOR_ID, 0u,
+ CSL_ECCAGGR_PULSAR_SL_CPU0_DTAG_RAM2_SIZE, 4u,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM2_ROW_SIZE, ((bool)false) },
+ {SDR_ECC_R5F_MEM_SUBTYPE_DTAG_RAM3_VECTOR_ID, 0u,
+ CSL_ECCAGGR_PULSAR_SL_CPU0_DTAG_RAM3_SIZE, 4u,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM3_ROW_SIZE, ((bool)false) },
+ {SDR_ECC_R5F_MEM_SUBTYPE_DDIRTY_RAM_VECTOR_ID, 0u,
+ CSL_ECCAGGR_PULSAR_SL_CPU0_DDIRTY_RAM_SIZE, 4u,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDIRTY_RAM_ROW_SIZE, ((bool)false) },
+ {SDR_ECC_R5F_MEM_SUBTYPE_DDATA_RAM0_VECTOR_ID, 0u,
+ CSL_ECCAGGR_PULSAR_SL_CPU0_DDATA_RAM0_SIZE, 4u,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM0_ROW_SIZE, ((bool)false) },
+ {SDR_ECC_R5F_MEM_SUBTYPE_DDATA_RAM1_VECTOR_ID, 0u,
+ CSL_ECCAGGR_PULSAR_SL_CPU0_DDATA_RAM1_SIZE, 4u,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM1_ROW_SIZE, ((bool)false) },
+ {SDR_ECC_R5F_MEM_SUBTYPE_DDATA_RAM2_VECTOR_ID, 0u,
+ CSL_ECCAGGR_PULSAR_SL_CPU0_DDATA_RAM2_SIZE, 4u,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM2_ROW_SIZE, ((bool)false) },
+ {SDR_ECC_R5F_MEM_SUBTYPE_DDATA_RAM3_VECTOR_ID, 0u,
+ CSL_ECCAGGR_PULSAR_SL_CPU0_DDATA_RAM3_SIZE, 4u,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM3_ROW_SIZE, ((bool)false) },
+ {SDR_ECC_R5F_MEM_SUBTYPE_DDATA_RAM4_VECTOR_ID ,0u,
+ CSL_ECCAGGR_PULSAR_SL_CPU0_DDATA_RAM4_SIZE, 4u,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM4_ROW_SIZE, ((bool)false) },
+ {SDR_ECC_R5F_MEM_SUBTYPE_DDATA_RAM5_VECTOR_ID, 0u,
+ CSL_ECCAGGR_PULSAR_SL_CPU0_DDATA_RAM5_SIZE, 4u,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM5_ROW_SIZE, ((bool)false) },
+ {SDR_ECC_R5F_MEM_SUBTYPE_DDATA_RAM6_VECTOR_ID, 0u,
+ CSL_ECCAGGR_PULSAR_SL_CPU0_DDATA_RAM6_SIZE, 4u,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM6_ROW_SIZE, ((bool)false) },
+ {SDR_ECC_R5F_MEM_SUBTYPE_DDATA_RAM7_VECTOR_ID, 0u,
+ CSL_ECCAGGR_PULSAR_SL_CPU0_DDATA_RAM7_SIZE, 4u,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM7_ROW_SIZE, ((bool)false) },
+ {SDR_ECC_R5F_MEM_SUBTYPE_ATCM0_BANK0_VECTOR_ID, 0u,
+ CSL_ECCAGGR_PULSAR_SL_CPU0_ATCM0_BANK0_SIZE, 8u,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_ROW_SIZE, ((bool)true) },
+ {SDR_ECC_R5F_MEM_SUBTYPE_ATCM0_BANK1_VECTOR_ID, 0x4u,
+ CSL_ECCAGGR_PULSAR_SL_CPU0_ATCM0_BANK1_SIZE, 8u,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_ROW_SIZE, ((bool)true) },
+ {SDR_ECC_R5F_MEM_SUBTYPE_B0TCM0_BANK0_VECTOR_ID, 0x41010000u,
+ CSL_ECCAGGR_PULSAR_SL_CPU0_B0TCM0_BANK0_SIZE, 16u,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_ROW_SIZE, ((bool)true) },
+ {SDR_ECC_R5F_MEM_SUBTYPE_B0TCM0_BANK1_VECTOR_ID, 0x41010004u,
+ CSL_ECCAGGR_PULSAR_SL_CPU0_B0TCM0_BANK1_SIZE, 16u,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_ROW_SIZE, ((bool)true) },
+ {SDR_ECC_R5F_MEM_SUBTYPE_B1TCM0_BANK0_VECTOR_ID, 0x41010008u,
+ CSL_ECCAGGR_PULSAR_SL_CPU0_B1TCM0_BANK0_SIZE, 16u,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_ROW_SIZE, ((bool)true) },
+ {SDR_ECC_R5F_MEM_SUBTYPE_B1TCM0_BANK1_VECTOR_ID, 0x4101000cu,
+ CSL_ECCAGGR_PULSAR_SL_CPU0_B1TCM0_BANK1_SIZE, 16u,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_ROW_SIZE, ((bool)true) },
+ {SDR_ECC_R5F_MEM_SUBTYPE_KS_VIM_RAM_VECTOR_ID, 0x40f82000u,
+ CSL_ECCAGGR_PULSAR_SL_CPU0_KS_VIM_RAMECC_SIZE, 4u,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_ROW_SIZE, ((bool)true) },
};
/* Max entries based on max mem type */
diff --git a/packages/ti/diag/sdr/src/j721e/r5/sdr_esm_core.h b/packages/ti/diag/sdr/src/j721e/r5/sdr_esm_core.h
index b8b4d5a0ee0d3f669dd4a2bbd52c0235e9626c55..871f5b8442eed47343ed969332f385ba634a3039 100755 (executable)
#define SDR_ESM_MCU_R5_VIM_BUS_CMP_ERR_INT CSLR_MCU_ESM0_ESM_PLS_EVENT0_MCU_R5FSS0_VIM_COMPARE_ERR_PULSE_0
#define SDR_ESM_MCU_R5_CCM_STAT_ERR_INT CSLR_MCU_ESM0_ESM_PLS_EVENT0_MCU_R5FSS0_CCM_COMPARE_STAT_PULSE_INTR_0
+#define SDR_ESM_MAIN_MSMC_ECC_AGGR0_DED_INT CSLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_CLEC_ESM_EVENTS_OUT_LEVEL_0
+#define SDR_ESM_MAIN_MSMC_ECC_AGGR0_SEC_INT CSLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_CLEC_ESM_EVENTS_OUT_LEVEL_1
+#define SDR_ESM_MAIN_MSMC_ECC_AGGR1_DED_INT CSLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_CLEC_ESM_EVENTS_OUT_LEVEL_2
+#define SDR_ESM_MAIN_MSMC_ECC_AGGR1_SEC_INT CSLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_CLEC_ESM_EVENTS_OUT_LEVEL_3
+#define SDR_ESM_MAIN_MSMC_ECC_AGGR2_DED_INT CSLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_CLEC_ESM_EVENTS_OUT_LEVEL_4
+#define SDR_ESM_MAIN_MSMC_ECC_AGGR2_SEC_INT CSLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_CLEC_ESM_EVENTS_OUT_LEVEL_5
+#define SDR_ESM_MAIN_A72_ECC_AGGR0_DED_INT CSLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_CLEC_ESM_EVENTS_OUT_LEVEL_7
+#define SDR_ESM_MAIN_A72_ECC_AGGR0_SEC_INT CSLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_CLEC_ESM_EVENTS_OUT_LEVEL_8
+#define SDR_ESM_MAIN_A72_ECC_AGGR1_DED_INT CSLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_CLEC_ESM_EVENTS_OUT_LEVEL_9
+#define SDR_ESM_MAIN_A72_ECC_AGGR1_SEC_INT CSLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_CLEC_ESM_EVENTS_OUT_LEVEL_10
+#define SDR_ESM_MAIN_A72_ECC_AGGR2_DED_INT CSLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_CLEC_ESM_EVENTS_OUT_LEVEL_11
+#define SDR_ESM_MAIN_A72_ECC_AGGR2_SEC_INT CSLR_ESM0_ESM_LVL_EVENT_COMPUTE_CLUSTER0_CLEC_ESM_EVENTS_OUT_LEVEL_12
+
+#define SDR_ESM_MCU_CBASS_ECC_AGGR_SEC_INT CSLR_MCU_ESM0_ESM_LVL_EVENT_MCU_ECC_AGGR0_CORR_LEVEL_0
+#define SDR_ESM_MCU_CBASS_ECC_AGGR_DED_INT CSLR_MCU_ESM0_ESM_LVL_EVENT_MCU_ECC_AGGR0_UNCORR_LEVEL_0
+
#endif /* INCLUDE_SDR_ESM_CORE_H_ */
diff --git a/packages/ti/diag/sdr/src/j721e/sdr_ecc_soc.h b/packages/ti/diag/sdr/src/j721e/sdr_ecc_soc.h
index a76fd42648e434c7f14086a842a68802fb3ea6c1..9964cc675859b0006bac30ebdb9f27ce3336b861 100644 (file)
#include "sdr_ecc_priv.h"
+#define NOT_USE_CSLR
+
+// TODO - Macros defined within NOT_USE_CSLR to be used until CSLR values for J721E defined
+#if defined(NOT_USE_CSLR)
+
+#define CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CLEC_SRAM_RAMECC_SIZE (40U) //TBD
+
+
+/* ECC Row Widths for MCU Pulsar RAM ID's with Wrapper type
+ * metadata width = (ecc_row_width) + 2 + log2(ecc_row_width) */
+#define CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM0_ROW_SIZE (22U)
+#define CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM1_ROW_SIZE (22U)
+#define CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM2_ROW_SIZE (22U)
+#define CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM3_ROW_SIZE (22U)
+#define CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK0_ROW_SIZE (64U)
+#define CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK1_ROW_SIZE (64U)
+#define CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK2_ROW_SIZE (64U)
+#define CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK3_ROW_SIZE (64U)
+#define CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM0_ROW_SIZE (22U)
+#define CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM1_ROW_SIZE (22U)
+#define CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM2_ROW_SIZE (22U)
+#define CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM3_ROW_SIZE (22U)
+#define CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDIRTY_RAM_ROW_SIZE (22U)
+#define CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM0_ROW_SIZE (32U)
+#define CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM1_ROW_SIZE (32U)
+#define CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM2_ROW_SIZE (32U)
+#define CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM3_ROW_SIZE (32U)
+#define CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM4_ROW_SIZE (32U)
+#define CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM5_ROW_SIZE (32U)
+#define CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM6_ROW_SIZE (32U)
+#define CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM7_ROW_SIZE (32U)
+#define CSL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_ROW_SIZE (32U)
+#define CSL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_ROW_SIZE (32U)
+#define CSL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_ROW_SIZE (32U)
+#define CSL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_ROW_SIZE (32U)
+#define CSL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_ROW_SIZE (32U)
+#define CSL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_ROW_SIZE (32U)
+//#define CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_ROW_SIZE (30U)
+#define CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_ROW_SIZE (32U)
+
+// MCU_CBASS_
+#define CSL_MCU_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_WR_RAMECC_ID (0U)
+#define CSL_MCU_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_WR_RAMECC_ECC_TYPE (1U)
+#define CSL_MCU_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_WR_RAMECC_INJECT_TYPE (0U)
+#define CSL_MCU_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_WR_RAMECC_RAM_SIZE (0U) // TBD
+
+#define CSL_MCU_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_RD_RAMECC_ID (1U)
+#define CSL_MCU_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_RD_RAMECC_ECC_TYPE (1U)
+#define CSL_MCU_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_RD_RAMECC_INJECT_TYPE (0U)
+#define CSL_MCU_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_RD_RAMECC_RAM_SIZE (0U) // TBD
+
+#define CSL_MCU_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_ID (2U)
+#define CSL_MCU_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_ECC_TYPE (1U)
+#define CSL_MCU_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_INJECT_TYPE (0U)
+#define CSL_MCU_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_RAM_SIZE (0U)
+#define CSL_MCU_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_ACCESSIBLE (0U)
+#endif /* #if defined(NOT_USE_CSLR) */
+
/* define MAX entry based on list of Subtypes */
-#define SDR_PULSAR_CPU_RAM_ID_TABLE_MAX_ENTRIES (CSL_ECCAGGR_PULSAR_SL_CPU0_KS_VIM_RAMECC_VECTOR_ID+1u)
+#define SDR_PULSAR_CPU_RAM_ID_TABLE_MAX_ENTRIES (CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_ID+1u)
+#define SDR_MSMC_AGGR0_RAM_ID_TABLE_MAX_ENTRIES (CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CLEC_J7ES_CLEC_EDC_CTRL_BUSECC_ID+1u)
+#define SDR_MCU_CBASS_RAM_ID_TABLE_MAX_ENTRIES (CSL_MCU_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_ID+1u)
+
+/* define Max memEntries for each aggregator (i.e. the number of RAM ID's with
+ * Wrapper type) */
+#define SDR_PULSAR_CPU_WRAPPER_RAM_IDS_TOTAL_ENTRIES (28U)
+#define SDR_MSMC_AGGR0_WRAPPER_RAM_IDS_TOTAL_ENTRIES (1U)
+#define SDR_MCU_CBASS_WRAPPER_RAM_IDS_TOTAL_ENTRIES (2U)
+
+#define SDR_PULSAR_CPU_RAM_ID_VBUSM2_AXI_EDC_VECTOR_GRP_MAX_ENTRIES (49U)
-/** ---------------------------------------------------------------------------
- * @brief This structure holds the list of Ram Ids for each memory subtype
- * ----------------------------------------------------------------------------
+/** ------------------------------------------------------------------------------------
+ * @brief This structure holds the list of Ram Ids for each memory subtype in MCU domain
+ * -------------------------------------------------------------------------------------
*/
const SDR_RAMIdEntry_t SDR_ECC_mcuArmssRamIdTable[SDR_PULSAR_CPU_RAM_ID_TABLE_MAX_ENTRIES] =
{
- { CSL_ECCAGGR_PULSAR_SL_CPU0_ITAG_RAM0_VECTOR_ID, ((bool)true) },
- { CSL_ECCAGGR_PULSAR_SL_CPU0_ITAG_RAM1_VECTOR_ID, ((bool)true) },
- { CSL_ECCAGGR_PULSAR_SL_CPU0_ITAG_RAM2_VECTOR_ID, ((bool)true) },
- { CSL_ECCAGGR_PULSAR_SL_CPU0_ITAG_RAM3_VECTOR_ID, ((bool)true) },
- { CSL_ECCAGGR_PULSAR_SL_CPU0_IDATA_BANK0_VECTOR_ID, ((bool)true) },
- { CSL_ECCAGGR_PULSAR_SL_CPU0_IDATA_BANK1_VECTOR_ID, ((bool)true) },
- { CSL_ECCAGGR_PULSAR_SL_CPU0_IDATA_BANK2_VECTOR_ID, ((bool)true) },
- { CSL_ECCAGGR_PULSAR_SL_CPU0_IDATA_BANK3_VECTOR_ID, ((bool)true) },
- { CSL_ECCAGGR_PULSAR_SL_CPU0_DTAG_RAM0_VECTOR_ID, ((bool)true) },
- { CSL_ECCAGGR_PULSAR_SL_CPU0_DTAG_RAM1_VECTOR_ID, ((bool)true) },
- { CSL_ECCAGGR_PULSAR_SL_CPU0_DTAG_RAM2_VECTOR_ID, ((bool)true) },
- { CSL_ECCAGGR_PULSAR_SL_CPU0_DTAG_RAM3_VECTOR_ID, ((bool)true) },
- { CSL_ECCAGGR_PULSAR_SL_CPU0_DDIRTY_RAM_VECTOR_ID, ((bool)true) },
- { CSL_ECCAGGR_PULSAR_SL_CPU0_DDATA_RAM0_VECTOR_ID, ((bool)true) },
- { CSL_ECCAGGR_PULSAR_SL_CPU0_DDATA_RAM1_VECTOR_ID, ((bool)true) },
- { CSL_ECCAGGR_PULSAR_SL_CPU0_DDATA_RAM2_VECTOR_ID, ((bool)true) },
- { CSL_ECCAGGR_PULSAR_SL_CPU0_DDATA_RAM3_VECTOR_ID, ((bool)true) },
- { CSL_ECCAGGR_PULSAR_SL_CPU0_DDATA_RAM4_VECTOR_ID, ((bool)true) },
- { CSL_ECCAGGR_PULSAR_SL_CPU0_DDATA_RAM5_VECTOR_ID, ((bool)true) },
- { CSL_ECCAGGR_PULSAR_SL_CPU0_DDATA_RAM6_VECTOR_ID, ((bool)true) },
- { CSL_ECCAGGR_PULSAR_SL_CPU0_DDATA_RAM7_VECTOR_ID, ((bool)true) },
- { CSL_ECCAGGR_PULSAR_SL_CPU0_ATCM0_BANK0_VECTOR_ID, ((bool)true) },
- { CSL_ECCAGGR_PULSAR_SL_CPU0_ATCM0_BANK1_VECTOR_ID, ((bool)true) },
- { CSL_ECCAGGR_PULSAR_SL_CPU0_B0TCM0_BANK0_VECTOR_ID, ((bool)true) },
- { CSL_ECCAGGR_PULSAR_SL_CPU0_B0TCM0_BANK1_VECTOR_ID, ((bool)true) },
- { CSL_ECCAGGR_PULSAR_SL_CPU0_B1TCM0_BANK0_VECTOR_ID, ((bool)true) },
- { CSL_ECCAGGR_PULSAR_SL_CPU0_B1TCM0_BANK1_VECTOR_ID, ((bool)true) },
- { CSL_ECCAGGR_PULSAR_SL_CPU0_KS_VIM_RAMECC_VECTOR_ID, ((bool)false) },
+ { CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM0_ID,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM0_INJECT_TYPE,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM0_ECC_TYPE },
+ { CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM1_ID,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM1_INJECT_TYPE,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM1_ECC_TYPE },
+ { CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM2_ID,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM2_INJECT_TYPE,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM2_ECC_TYPE },
+ { CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM3_ID,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM3_INJECT_TYPE,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM3_ECC_TYPE },
+ { CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK0_ID,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK0_INJECT_TYPE,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK0_ECC_TYPE },
+ { CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK1_ID,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK1_INJECT_TYPE,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK1_ECC_TYPE },
+ { CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK2_ID,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK2_INJECT_TYPE,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK2_ECC_TYPE },
+ { CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK3_ID,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK3_INJECT_TYPE,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK3_ECC_TYPE },
+ { CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM0_ID,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM0_INJECT_TYPE,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM0_ECC_TYPE },
+ { CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM1_ID,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM1_INJECT_TYPE,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM1_ECC_TYPE },
+ { CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM2_ID,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM2_INJECT_TYPE,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM2_ECC_TYPE },
+ { CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM3_ID,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM3_INJECT_TYPE,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM3_ECC_TYPE },
+ { CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDIRTY_RAM_ID,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDIRTY_RAM_INJECT_TYPE,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDIRTY_RAM_ECC_TYPE },
+ { CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM0_ID,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM0_INJECT_TYPE,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM0_ECC_TYPE },
+ { CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM1_ID,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM1_INJECT_TYPE,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM1_ECC_TYPE },
+ { CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM2_ID,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM2_INJECT_TYPE,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM2_ECC_TYPE },
+ { CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM3_ID,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM3_INJECT_TYPE,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM3_ECC_TYPE },
+ { CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM4_ID,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM4_INJECT_TYPE,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM4_ECC_TYPE },
+ { CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM5_ID,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM5_INJECT_TYPE,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM5_ECC_TYPE },
+ { CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM6_ID,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM6_INJECT_TYPE,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM6_ECC_TYPE },
+ { CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM7_ID,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM7_INJECT_TYPE,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM7_ECC_TYPE },
+ { CSL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_ID,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_INJECT_TYPE,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_ECC_TYPE },
+ { CSL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_ID,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_INJECT_TYPE,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_ECC_TYPE },
+ { CSL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_ID,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_INJECT_TYPE,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_ECC_TYPE },
+ { CSL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_ID,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_INJECT_TYPE,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_ECC_TYPE },
+ { CSL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_ID,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_INJECT_TYPE,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_ECC_TYPE },
+ { CSL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_ID,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_INJECT_TYPE,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_ECC_TYPE },
+ { CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_ID,
+ 0U, // TODO - Update this value to CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_INJECT_TYPE when it is properly set to 0U in CSLR
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_ECC_TYPE },
+ { CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_ID,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_INJECT_TYPE,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_KSBUS_VBUSM2AXI0_EDC_CTRL_ECC_TYPE }, // 28 - Interconnect Type
+ { CSL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_ID,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_INJECT_TYPE,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_ECC_TYPE }, // 29 - Interconnect Type
+ { CSL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_ID,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_INJECT_TYPE,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_MEM_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_ECC_TYPE }, // 30 - Interconnect Type
+ { CSL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_ID,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_INJECT_TYPE,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_W_EDC_CTRL_ECC_TYPE }, // 31 - Interconnect Type
+ { CSL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_ID,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_INJECT_TYPE,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_PERIPH_M_MST0_KSBUS_AXI2VBUSM_R_EDC_CTRL_ECC_TYPE }, // 32 - Interconnect Type
+ { CSL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_ID,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_INJECT_TYPE,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_AHB2VBUSP_CPU0_EDC_CTRL_ECC_TYPE }, // 33 - Interconnect Type
+ { CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_ID,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_INJECT_TYPE,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_CFG_SCRP_INTERFACE0_GCLK_CLK_EDC_CTRL_ECC_TYPE }, // 34 - Interconnect Type
+ { CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_ID,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_INJECT_TYPE,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ECC_AGGR_EDC_CTRL_ECC_TYPE }, // 35 - Interconnect Type
};
-/** ---------------------------------------------------------------------------
- * @brief This structure holds the memory config for each memory subtype
- * ----------------------------------------------------------------------------
+/** ----------------------------------------------------------------------------------
+ * @brief This structure holds the memory config for each memory subtype in MCU domain
+ * -----------------------------------------------------------------------------------
*/
-const SDR_MemConfig_t SDR_ECC_mcuArmssMemEntries[SDR_PULSAR_CPU_RAM_ID_TABLE_MAX_ENTRIES] =
+// TODO - Utilize CSLR sizes when confirmed accurate
+const SDR_MemConfig_t SDR_ECC_mcuArmssMemEntries[SDR_PULSAR_CPU_WRAPPER_RAM_IDS_TOTAL_ENTRIES] =
{
- {0u, CSL_ECCAGGR_PULSAR_SL_CPU0_ITAG_RAM0_SIZE, 4u, ((bool)false) },
- {0u, CSL_ECCAGGR_PULSAR_SL_CPU0_ITAG_RAM1_SIZE, 4u, ((bool)false) },
- {0u, CSL_ECCAGGR_PULSAR_SL_CPU0_ITAG_RAM2_SIZE, 4u, ((bool)false) },
- {0u, CSL_ECCAGGR_PULSAR_SL_CPU0_ITAG_RAM3_SIZE, 4u, ((bool)false) },
- {0u, CSL_ECCAGGR_PULSAR_SL_CPU0_IDATA_BANK0_SIZE, 4u, ((bool)false) },
- {0u, CSL_ECCAGGR_PULSAR_SL_CPU0_IDATA_BANK1_SIZE, 4u, ((bool)false) },
- {0u, CSL_ECCAGGR_PULSAR_SL_CPU0_IDATA_BANK2_SIZE, 4u, ((bool)false) },
- {0u, CSL_ECCAGGR_PULSAR_SL_CPU0_IDATA_BANK3_SIZE, 4u, ((bool)false) },
- {0u, CSL_ECCAGGR_PULSAR_SL_CPU0_DTAG_RAM0_SIZE, 4u, ((bool)false) },
- {0u, CSL_ECCAGGR_PULSAR_SL_CPU0_DTAG_RAM1_SIZE, 4u, ((bool)false) },
- {0u, CSL_ECCAGGR_PULSAR_SL_CPU0_DTAG_RAM2_SIZE, 4u, ((bool)false) },
- {0u, CSL_ECCAGGR_PULSAR_SL_CPU0_DTAG_RAM3_SIZE, 4u, ((bool)false) },
- {0u, CSL_ECCAGGR_PULSAR_SL_CPU0_DDIRTY_RAM_SIZE, 4u, ((bool)false) },
- {0u, CSL_ECCAGGR_PULSAR_SL_CPU0_DDATA_RAM0_SIZE, 4u, ((bool)false) },
- {0u, CSL_ECCAGGR_PULSAR_SL_CPU0_DDATA_RAM1_SIZE, 4u, ((bool)false) },
- {0u, CSL_ECCAGGR_PULSAR_SL_CPU0_DDATA_RAM2_SIZE, 4u, ((bool)false) },
- {0u, CSL_ECCAGGR_PULSAR_SL_CPU0_DDATA_RAM3_SIZE, 4u, ((bool)false) },
- {0u, CSL_ECCAGGR_PULSAR_SL_CPU0_DDATA_RAM4_SIZE, 4u, ((bool)false) },
- {0u, CSL_ECCAGGR_PULSAR_SL_CPU0_DDATA_RAM5_SIZE, 4u, ((bool)false) },
- {0u, CSL_ECCAGGR_PULSAR_SL_CPU0_DDATA_RAM6_SIZE, 4u, ((bool)false) },
- {0u, CSL_ECCAGGR_PULSAR_SL_CPU0_DDATA_RAM7_SIZE, 4u, ((bool)false) },
- {0u, CSL_ECCAGGR_PULSAR_SL_CPU0_ATCM0_BANK0_SIZE, 8u, ((bool)true) },
- {0x4u, CSL_ECCAGGR_PULSAR_SL_CPU0_ATCM0_BANK1_SIZE, 8u, ((bool)true) },
- {0x41010000u, CSL_ECCAGGR_PULSAR_SL_CPU0_B0TCM0_BANK0_SIZE, 16u, ((bool)true) },
- {0x41010004u, CSL_ECCAGGR_PULSAR_SL_CPU0_B0TCM0_BANK1_SIZE, 16u, ((bool)true) },
- {0x41010008u, CSL_ECCAGGR_PULSAR_SL_CPU0_B1TCM0_BANK0_SIZE, 16u, ((bool)true) },
- {0x4101000cu, CSL_ECCAGGR_PULSAR_SL_CPU0_B1TCM0_BANK1_SIZE, 16u, ((bool)true) },
- {0x40f82000u, CSL_ECCAGGR_PULSAR_SL_CPU0_KS_VIM_RAMECC_SIZE, 4u, ((bool)true) },
+ {SDR_ECC_R5F_MEM_SUBTYPE_ITAG_RAM0_VECTOR_ID, 0u,
+ CSL_ECCAGGR_PULSAR_SL_CPU0_ITAG_RAM0_SIZE, 4u,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM0_ROW_SIZE, ((bool)false) },
+ {SDR_ECC_R5F_MEM_SUBTYPE_ITAG_RAM1_VECTOR_ID, 0u,
+ CSL_ECCAGGR_PULSAR_SL_CPU0_ITAG_RAM1_SIZE, 4u,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM1_ROW_SIZE, ((bool)false) },
+ {SDR_ECC_R5F_MEM_SUBTYPE_ITAG_RAM2_VECTOR_ID, 0u,
+ CSL_ECCAGGR_PULSAR_SL_CPU0_ITAG_RAM2_SIZE, 4u,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM2_ROW_SIZE, ((bool)false) },
+ {SDR_ECC_R5F_MEM_SUBTYPE_ITAG_RAM3_VECTOR_ID, 0u,
+ CSL_ECCAGGR_PULSAR_SL_CPU0_ITAG_RAM3_SIZE, 4u,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_ITAG_RAM3_ROW_SIZE, ((bool)false) },
+ {SDR_ECC_R5F_MEM_SUBTYPE_IDATA_BANK0_VECTOR_ID, 0u,
+ CSL_ECCAGGR_PULSAR_SL_CPU0_IDATA_BANK0_SIZE, 4u,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK0_ROW_SIZE, ((bool)false) },
+ {SDR_ECC_R5F_MEM_SUBTYPE_IDATA_BANK1_VECTOR_ID, 0u,
+ CSL_ECCAGGR_PULSAR_SL_CPU0_IDATA_BANK1_SIZE, 4u,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK1_ROW_SIZE, ((bool)false) },
+ {SDR_ECC_R5F_MEM_SUBTYPE_IDATA_BANK2_VECTOR_ID, 0u,
+ CSL_ECCAGGR_PULSAR_SL_CPU0_IDATA_BANK2_SIZE, 4u,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK2_ROW_SIZE, ((bool)false) },
+ {SDR_ECC_R5F_MEM_SUBTYPE_IDATA_BANK3_VECTOR_ID, 0u,
+ CSL_ECCAGGR_PULSAR_SL_CPU0_IDATA_BANK3_SIZE, 4u,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_IDATA_BANK3_ROW_SIZE, ((bool)false) },
+ {SDR_ECC_R5F_MEM_SUBTYPE_DTAG_RAM0_VECTOR_ID, 0u,
+ CSL_ECCAGGR_PULSAR_SL_CPU0_DTAG_RAM0_SIZE, 4u,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM0_ROW_SIZE, ((bool)false) },
+ {SDR_ECC_R5F_MEM_SUBTYPE_DTAG_RAM1_VECTOR_ID, 0u,
+ CSL_ECCAGGR_PULSAR_SL_CPU0_DTAG_RAM1_SIZE, 4u,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM1_ROW_SIZE, ((bool)false) },
+ {SDR_ECC_R5F_MEM_SUBTYPE_DTAG_RAM2_VECTOR_ID, 0u,
+ CSL_ECCAGGR_PULSAR_SL_CPU0_DTAG_RAM2_SIZE, 4u,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM2_ROW_SIZE, ((bool)false) },
+ {SDR_ECC_R5F_MEM_SUBTYPE_DTAG_RAM3_VECTOR_ID, 0u,
+ CSL_ECCAGGR_PULSAR_SL_CPU0_DTAG_RAM3_SIZE, 4u,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DTAG_RAM3_ROW_SIZE, ((bool)false) },
+ {SDR_ECC_R5F_MEM_SUBTYPE_DDIRTY_RAM_VECTOR_ID, 0u,
+ CSL_ECCAGGR_PULSAR_SL_CPU0_DDIRTY_RAM_SIZE, 4u,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDIRTY_RAM_ROW_SIZE, ((bool)false) },
+ {SDR_ECC_R5F_MEM_SUBTYPE_DDATA_RAM0_VECTOR_ID, 0u,
+ CSL_ECCAGGR_PULSAR_SL_CPU0_DDATA_RAM0_SIZE, 4u,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM0_ROW_SIZE, ((bool)false) },
+ {SDR_ECC_R5F_MEM_SUBTYPE_DDATA_RAM1_VECTOR_ID, 0u,
+ CSL_ECCAGGR_PULSAR_SL_CPU0_DDATA_RAM1_SIZE, 4u,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM1_ROW_SIZE, ((bool)false) },
+ {SDR_ECC_R5F_MEM_SUBTYPE_DDATA_RAM2_VECTOR_ID, 0u,
+ CSL_ECCAGGR_PULSAR_SL_CPU0_DDATA_RAM2_SIZE, 4u,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM2_ROW_SIZE, ((bool)false) },
+ {SDR_ECC_R5F_MEM_SUBTYPE_DDATA_RAM3_VECTOR_ID, 0u,
+ CSL_ECCAGGR_PULSAR_SL_CPU0_DDATA_RAM3_SIZE, 4u,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM3_ROW_SIZE, ((bool)false) },
+ {SDR_ECC_R5F_MEM_SUBTYPE_DDATA_RAM4_VECTOR_ID ,0u,
+ CSL_ECCAGGR_PULSAR_SL_CPU0_DDATA_RAM4_SIZE, 4u,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM4_ROW_SIZE, ((bool)false) },
+ {SDR_ECC_R5F_MEM_SUBTYPE_DDATA_RAM5_VECTOR_ID, 0u,
+ CSL_ECCAGGR_PULSAR_SL_CPU0_DDATA_RAM5_SIZE, 4u,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM5_ROW_SIZE, ((bool)false) },
+ {SDR_ECC_R5F_MEM_SUBTYPE_DDATA_RAM6_VECTOR_ID, 0u,
+ CSL_ECCAGGR_PULSAR_SL_CPU0_DDATA_RAM6_SIZE, 4u,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM6_ROW_SIZE, ((bool)false) },
+ {SDR_ECC_R5F_MEM_SUBTYPE_DDATA_RAM7_VECTOR_ID, 0u,
+ CSL_ECCAGGR_PULSAR_SL_CPU0_DDATA_RAM7_SIZE, 4u,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_DDATA_RAM7_ROW_SIZE, ((bool)false) },
+ {SDR_ECC_R5F_MEM_SUBTYPE_ATCM0_BANK0_VECTOR_ID, 0u,
+ CSL_ECCAGGR_PULSAR_SL_CPU0_ATCM0_BANK0_SIZE, 8u,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK0_ROW_SIZE, ((bool)true) },
+ {SDR_ECC_R5F_MEM_SUBTYPE_ATCM0_BANK1_VECTOR_ID, 0x4u,
+ CSL_ECCAGGR_PULSAR_SL_CPU0_ATCM0_BANK1_SIZE, 8u,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_ATCM0_BANK1_ROW_SIZE, ((bool)true) },
+ {SDR_ECC_R5F_MEM_SUBTYPE_B0TCM0_BANK0_VECTOR_ID, 0x41010000u,
+ CSL_ECCAGGR_PULSAR_SL_CPU0_B0TCM0_BANK0_SIZE, 16u,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK0_ROW_SIZE, ((bool)true) },
+ {SDR_ECC_R5F_MEM_SUBTYPE_B0TCM0_BANK1_VECTOR_ID, 0x41010004u,
+ CSL_ECCAGGR_PULSAR_SL_CPU0_B0TCM0_BANK1_SIZE, 16u,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B0TCM0_BANK1_ROW_SIZE, ((bool)true) },
+ {SDR_ECC_R5F_MEM_SUBTYPE_B1TCM0_BANK0_VECTOR_ID, 0x41010008u,
+ CSL_ECCAGGR_PULSAR_SL_CPU0_B1TCM0_BANK0_SIZE, 16u,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK0_ROW_SIZE, ((bool)true) },
+ {SDR_ECC_R5F_MEM_SUBTYPE_B1TCM0_BANK1_VECTOR_ID, 0x4101000cu,
+ CSL_ECCAGGR_PULSAR_SL_CPU0_B1TCM0_BANK1_SIZE, 16u,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_PULSAR_SL_B1TCM0_BANK1_ROW_SIZE, ((bool)true) },
+ {SDR_ECC_R5F_MEM_SUBTYPE_KS_VIM_RAM_VECTOR_ID, 0x40f82000u,
+ CSL_ECCAGGR_PULSAR_SL_CPU0_KS_VIM_RAMECC_SIZE, 4u,
+ CSL_MCU_R5FSS0_CORE0_ECC_AGGR_CPU0_KS_VIM_RAMECC_ROW_SIZE, ((bool)true) },
};
/* Max entries based on max mem type */
-#define SDR_ECC_AGGREGATOR_MAX_ENTRIES (SDR_ECC_MEMTYPE_MCU_PSRAM0+1u)
+#define SDR_ECC_AGGREGATOR_MAX_LOW_ENTRIES (SDR_ECC_MEMTYPE_MCU_CBASS_ECC_AGGR0+1u)
+
+#define SDR_ECC_AGGREGATOR_MAX_HIGH_ENTRIES (SDR_ECC_MEMTYPE_MAIN_MSMC_AGGR2 - \
+ SDR_ECC_MEMTYPE_MAIN_MSMC_AGGR0 + 1u)
+
+/* Max entries based on max mem type */
+#define SDR_ECC_AGGREGATOR_MAX_ENTRIES (SDR_ECC_AGGREGATOR_MAX_LOW_ENTRIES + \
+ SDR_ECC_AGGREGATOR_MAX_HIGH_ENTRIES)
-CSL_ecc_aggrRegs * const SDR_ECC_aggrBaseAddressTable[SDR_ECC_AGGREGATOR_MAX_ENTRIES] =
+/** -----------------------------------------------------------------------------------
+ * @brief This structure holds the base addresses for each memory subtype in MCU domain
+ * ------------------------------------------------------------------------------------
+ */
+CSL_ecc_aggrRegs * const SDR_ECC_aggrBaseAddressTable[SDR_ECC_AGGREGATOR_MAX_LOW_ENTRIES] =
{
((CSL_ecc_aggrRegs *)((uintptr_t)CSL_MCU_R5FSS0_CORE0_ECC_AGGR_BASE)),
((CSL_ecc_aggrRegs *)((uintptr_t)0U)),
@@ -139,27 +355,449 @@ CSL_ecc_aggrRegs * const SDR_ECC_aggrBaseAddressTable[SDR_ECC_AGGREGATOR_MAX_ENT
((CSL_ecc_aggrRegs *)((uintptr_t)0U)),
((CSL_ecc_aggrRegs *)((uintptr_t)0U)),
((CSL_ecc_aggrRegs *)((uintptr_t)CSL_PSRAMECC0_ECC_AGGR_BASE)),
+ ((CSL_ecc_aggrRegs *)((uintptr_t)CSL_MCU_ECC_AGGR0_ECC_AGGR_BASE)),
};
-const SDR_RAMIdEntry_t SDR_ECC_MSRAMRamIdTable =
+/* Addresses will be cast to CSL_ecc_aggrRegs after RAT translation */
+uint64_t const SDR_ECC_aggrHighBaseAddressTable[SDR_ECC_AGGREGATOR_MAX_HIGH_ENTRIES] =
{
- 0u, ((bool)false)
+ (uint64_t)CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_BASE,
+ (uint64_t)CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR1_BASE,
+ (uint64_t)CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR2_BASE,
};
-const SDR_MemConfig_t SDR_ECC_MSRAMMemEntry =
+CSL_ecc_aggrRegs * SDR_ECC_aggrHighBaseAddressTableTrans[SDR_ECC_AGGREGATOR_MAX_HIGH_ENTRIES];
+
+/** -------------------------------------------------------------------------------------
+ * @brief This structure holds the list of Ram Ids for each memory subtype in MSMC AGGR0
+ * --------------------------------------------------------------------------------------
+ */
+/* Note: While this table lists all the possible RAM ID's for the MSMC AGGR0, only the following
+ * 2 RAM ID's have been tested:
+ * CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_ID = 20 (Interconnect type)
+ * CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CLEC_CLEC_SRAM_ID = 100 (Wrapper type) */
+const SDR_RAMIdEntry_t SDR_ECC_mainMsmcAggr0RamIdTable[SDR_MSMC_AGGR0_RAM_ID_TABLE_MAX_ENTRIES] =
{
- CSL_MCU_MSRAM_1MB0_RAM_BASE, CSL_MCU_MSRAM_1MB0_RAM_SIZE, 4u, ((bool)true)
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_J7ES_ECC_AGGR0_EDC_CTRL_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_J7ES_ECC_AGGR0_EDC_CTRL_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_J7ES_ECC_AGGR0_EDC_CTRL_ECC_TYPE }, // 0
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CC_MSMC_EN_MSMC_8MB_MSMC_DATA_RAM0_MSMC_MSMC_CORE_CORE_MSMC_QOR_MSMC_CORE_DRU_DRU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CC_MSMC_EN_MSMC_8MB_MSMC_DATA_RAM0_MSMC_MSMC_CORE_CORE_MSMC_QOR_MSMC_CORE_DRU_DRU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CC_MSMC_EN_MSMC_8MB_MSMC_DATA_RAM0_MSMC_MSMC_CORE_CORE_MSMC_QOR_MSMC_CORE_DRU_DRU_CBASS_CBASS_INT_DMSC_SCR_EDC_CTRL_ECC_TYPE }, // 1
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SLV_BRDG_EDC_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SLV_BRDG_EDC_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_DMSC_SLV_BRDG_EDC_ECC_TYPE }, // 2
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_EDC_CTRL_ECC_TYPE }, // 3
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_CFG_EDC_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_CFG_EDC_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_CFG_EDC_ECC_TYPE }, // 4
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_EDC_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_EDC_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRDG_EDC_ECC_TYPE }, // 5
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRIDGE_EDC_DUMMY_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRIDGE_EDC_DUMMY_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_BRIDGE_EDC_DUMMY_ECC_TYPE }, // 6
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_CFG_EDC_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_CFG_EDC_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_CFG_EDC_ECC_TYPE }, // 7
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_EDC_ECC_TYPE }, // 8
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_FW_CH_BR_EDC_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_FW_CH_BR_EDC_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_FW_CH_BR_EDC_ECC_TYPE }, // 9
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_FW_CH_EDC_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_FW_CH_EDC_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_MMR_FW_CH_EDC_ECC_TYPE }, // 10
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SCR_EDC_ECC_TYPE }, // 11
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SLV_BRDG_ECC_EDC_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SLV_BRDG_ECC_EDC_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CBASS_SLV_BRDG_ECC_EDC_ECC_TYPE }, // 12
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CORE_PSIL_CMD_EDC_CTRL_0_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CORE_PSIL_CMD_EDC_CTRL_0_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_CORE_PSIL_CMD_EDC_CTRL_0_ECC_TYPE }, // 13
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_0_EDC_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_0_EDC_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_0_EDC_ECC_TYPE }, // 14
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_1_EDC_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_1_EDC_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_1_EDC_ECC_TYPE }, // 15
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ATTR_EDC_DUMMY_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ATTR_EDC_DUMMY_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ATTR_EDC_DUMMY_ECC_TYPE }, // 16
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_ENG_EDC_ECC_TYPE }, // 17
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_QUEUE_EDC_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_QUEUE_EDC_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_QUEUE_EDC_ECC_TYPE }, // 18
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_RD_BUF_EDC_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_RD_BUF_EDC_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU_RD_BUF_EDC_ECC_TYPE }, // 19
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_MMR_BUSECC_ECC_TYPE }, // 20
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_POSTARB_PIPE_CFG_BUSECC_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_POSTARB_PIPE_CFG_BUSECC_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_POSTARB_PIPE_CFG_BUSECC_ECC_TYPE }, // 21
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_SLV_LOCAL_ARB_BUSECC_ECC_TYPE }, // 22
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_SLV_LOCAL_ARB_BUSECC_ECC_TYPE }, // 23
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_MST_LOCAL_ARB_BUSECC_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_MST_LOCAL_ARB_BUSECC_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU0_MST_LOCAL_ARB_BUSECC_ECC_TYPE }, // 24
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_MST_LOCAL_ARB_BUSECC_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_MST_LOCAL_ARB_BUSECC_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DRU1_MST_LOCAL_ARB_BUSECC_ECC_TYPE }, // 25
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_SLV_PIPE_BUSECC_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_SLV_PIPE_BUSECC_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_SLV_PIPE_BUSECC_ECC_TYPE }, // 26
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_MST_PIPE_BUSECC_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_MST_PIPE_BUSECC_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF0_MST_PIPE_BUSECC_ECC_TYPE }, // 27
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_SLV_LOCAL_ARB_BUSECC_ECC_TYPE }, // 28
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_MST_LOCAL_ARB_BUSECC_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_MST_LOCAL_ARB_BUSECC_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU0_MST_LOCAL_ARB_BUSECC_ECC_TYPE }, // 29
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU1_SLV_LOCAL_ARB_BUSECC_DUMMY_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU1_SLV_LOCAL_ARB_BUSECC_DUMMY_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU1_SLV_LOCAL_ARB_BUSECC_DUMMY_ECC_TYPE }, // 30
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU1_MST_LOCAL_ARB_BUSECC_DUMMY_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU1_MST_LOCAL_ARB_BUSECC_DUMMY_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU1_MST_LOCAL_ARB_BUSECC_DUMMY_ECC_TYPE }, // 31
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU2_SLV_LOCAL_ARB_BUSECC_DUMMY_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU2_SLV_LOCAL_ARB_BUSECC_DUMMY_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU2_SLV_LOCAL_ARB_BUSECC_DUMMY_ECC_TYPE }, // 32
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU2_MST_LOCAL_ARB_BUSECC_DUMMY_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU2_MST_LOCAL_ARB_BUSECC_DUMMY_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU2_MST_LOCAL_ARB_BUSECC_DUMMY_ECC_TYPE }, // 33
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU3_SLV_LOCAL_ARB_BUSECC_DUMMY_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU3_SLV_LOCAL_ARB_BUSECC_DUMMY_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU3_SLV_LOCAL_ARB_BUSECC_DUMMY_ECC_TYPE }, // 34
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU3_MST_LOCAL_ARB_BUSECC_DUMMY_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU3_MST_LOCAL_ARB_BUSECC_DUMMY_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU3_MST_LOCAL_ARB_BUSECC_DUMMY_ECC_TYPE }, // 35
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_SLV_LOCAL_ARB_BUSECC_ECC_TYPE }, // 36
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_MST_LOCAL_ARB_BUSECC_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_MST_LOCAL_ARB_BUSECC_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU4_MST_LOCAL_ARB_BUSECC_ECC_TYPE }, // 37
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU5_SLV_LOCAL_ARB_BUSECC_DUMMY_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU5_SLV_LOCAL_ARB_BUSECC_DUMMY_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU5_SLV_LOCAL_ARB_BUSECC_DUMMY_ECC_TYPE }, // 38
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU5_MST_LOCAL_ARB_BUSECC_DUMMY_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU5_MST_LOCAL_ARB_BUSECC_DUMMY_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU5_MST_LOCAL_ARB_BUSECC_DUMMY_ECC_TYPE }, // 39
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU6_SLV_LOCAL_ARB_BUSECC_DUMMY_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU6_SLV_LOCAL_ARB_BUSECC_DUMMY_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU6_SLV_LOCAL_ARB_BUSECC_DUMMY_ECC_TYPE }, // 40
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU6_MST_LOCAL_ARB_BUSECC_DUMMY_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU6_MST_LOCAL_ARB_BUSECC_DUMMY_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU6_MST_LOCAL_ARB_BUSECC_DUMMY_ECC_TYPE }, // 41
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU7_SLV_LOCAL_ARB_BUSECC_DUMMY_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU7_SLV_LOCAL_ARB_BUSECC_DUMMY_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU7_SLV_LOCAL_ARB_BUSECC_DUMMY_ECC_TYPE }, // 42
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU7_MST_LOCAL_ARB_BUSECC_DUMMY_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU7_MST_LOCAL_ARB_BUSECC_DUMMY_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU7_MST_LOCAL_ARB_BUSECC_DUMMY_ECC_TYPE }, // 43
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_SLV_LOCAL_ARB_BUSECC_ECC_TYPE }, // 44
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_MST_LOCAL_ARB_BUSECC_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_MST_LOCAL_ARB_BUSECC_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU8_MST_LOCAL_ARB_BUSECC_ECC_TYPE }, // 45
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_SLV_LOCAL_ARB_BUSECC_ECC_TYPE }, // 46
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_MST_LOCAL_ARB_BUSECC_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_MST_LOCAL_ARB_BUSECC_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CPU9_MST_LOCAL_ARB_BUSECC_ECC_TYPE }, // 47
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_DATA_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_DATA_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_DATA_ECC_TYPE }, // 48
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_BUSECC_ECC_TYPE }, // 49
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_DST_BUSECC_DUMMY_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_DST_BUSECC_DUMMY_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_DST_BUSECC_DUMMY_ECC_TYPE }, // 50
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_SRC_BUSECC_DUMMY_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_SRC_BUSECC_DUMMY_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_VBUSP_CFG_SRC_P2M_SRC_BUSECC_DUMMY_ECC_TYPE }, // 51
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_VBUSP_CFG_SRC_M2M_SRC_BUSECC_DUMMY_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_VBUSP_CFG_SRC_M2M_SRC_BUSECC_DUMMY_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P0_VBUSP_CFG_SRC_M2M_SRC_BUSECC_DUMMY_ECC_TYPE }, // 52
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P1_BUSECC_DUMMY_DATA_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P1_BUSECC_DUMMY_DATA_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P1_BUSECC_DUMMY_DATA_ECC_TYPE }, // 53
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P1_BUSECC_DUMMY_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P1_BUSECC_DUMMY_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P1_BUSECC_DUMMY_ECC_TYPE }, // 54
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P1_VBUSP_CFG_SRC_P2M_DST_BUSECC_DUMMY_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P1_VBUSP_CFG_SRC_P2M_DST_BUSECC_DUMMY_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P1_VBUSP_CFG_SRC_P2M_DST_BUSECC_DUMMY_ECC_TYPE }, // 55
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P1_VBUSP_CFG_SRC_P2M_SRC_BUSECC_DUMMY_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P1_VBUSP_CFG_SRC_P2M_SRC_BUSECC_DUMMY_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P1_VBUSP_CFG_SRC_P2M_SRC_BUSECC_DUMMY_ECC_TYPE }, // 56
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P1_VBUSP_CFG_SRC_M2M_SRC_BUSECC_DUMMY_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P1_VBUSP_CFG_SRC_M2M_SRC_BUSECC_DUMMY_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P1_VBUSP_CFG_SRC_M2M_SRC_BUSECC_DUMMY_ECC_TYPE }, // 57
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P2_BUSECC_DUMMY_DATA_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P2_BUSECC_DUMMY_DATA_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P2_BUSECC_DUMMY_DATA_ECC_TYPE }, // 58
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P2_BUSECC_DUMMY_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P2_BUSECC_DUMMY_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P2_BUSECC_DUMMY_ECC_TYPE }, // 59
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P2_VBUSP_CFG_SRC_P2M_DST_BUSECC_DUMMY_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P2_VBUSP_CFG_SRC_P2M_DST_BUSECC_DUMMY_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P2_VBUSP_CFG_SRC_P2M_DST_BUSECC_DUMMY_ECC_TYPE }, // 60
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P2_VBUSP_CFG_SRC_P2M_SRC_BUSECC_DUMMY_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P2_VBUSP_CFG_SRC_P2M_SRC_BUSECC_DUMMY_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P2_VBUSP_CFG_SRC_P2M_SRC_BUSECC_DUMMY_ECC_TYPE }, // 61
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P2_VBUSP_CFG_SRC_M2M_SRC_BUSECC_DUMMY_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P2_VBUSP_CFG_SRC_M2M_SRC_BUSECC_DUMMY_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P2_VBUSP_CFG_SRC_M2M_SRC_BUSECC_DUMMY_ECC_TYPE }, // 62
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P3_BUSECC_DUMMY_DATA_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P3_BUSECC_DUMMY_DATA_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P3_BUSECC_DUMMY_DATA_ECC_TYPE }, // 63
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P3_BUSECC_DUMMY_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P3_BUSECC_DUMMY_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P3_BUSECC_DUMMY_ECC_TYPE }, // 64
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P3_VBUSP_CFG_SRC_P2M_DST_BUSECC_DUMMY_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P3_VBUSP_CFG_SRC_P2M_DST_BUSECC_DUMMY_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P3_VBUSP_CFG_SRC_P2M_DST_BUSECC_DUMMY_ECC_TYPE }, // 65
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P3_VBUSP_CFG_SRC_P2M_SRC_BUSECC_DUMMY_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P3_VBUSP_CFG_SRC_P2M_SRC_BUSECC_DUMMY_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P3_VBUSP_CFG_SRC_P2M_SRC_BUSECC_DUMMY_ECC_TYPE }, // 66
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P3_VBUSP_CFG_SRC_M2M_SRC_BUSECC_DUMMY_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P3_VBUSP_CFG_SRC_M2M_SRC_BUSECC_DUMMY_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EN_MSMC_P3_VBUSP_CFG_SRC_M2M_SRC_BUSECC_DUMMY_ECC_TYPE }, // 67
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_BUSECC_ECC_TYPE }, // 68
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_CACHE_TAG_PIPE_BUSECC_ECC_TYPE }, // 69
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_ECC_TYPE }, // 70
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_QUEUE_BUSECC_1_ECC_TYPE }, // 71
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_RMW_TAG_UPDATE_BUSECC_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_RMW_TAG_UPDATE_BUSECC_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_RMW_TAG_UPDATE_BUSECC_ECC_TYPE }, // 72
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_SRAM_SF_PIPE_BUSECC_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_SRAM_SF_PIPE_BUSECC_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW0_SRAM_SF_PIPE_BUSECC_ECC_TYPE }, // 73
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM0_BUSECC_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM0_BUSECC_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM0_BUSECC_ECC_TYPE }, // 74
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK0_BUSECC_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK0_BUSECC_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK0_BUSECC_ECC_TYPE }, // 75
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_BUSECC_ECC_TYPE }, // 76
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_CACHE_TAG_PIPE_BUSECC_ECC_TYPE }, // 77
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_0_ECC_TYPE }, // 78
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_QUEUE_BUSECC_1_ECC_TYPE }, // 79
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_RMW_TAG_UPDATE_BUSECC_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_RMW_TAG_UPDATE_BUSECC_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_RMW_TAG_UPDATE_BUSECC_ECC_TYPE }, // 80
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_SRAM_SF_PIPE_BUSECC_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_SRAM_SF_PIPE_BUSECC_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW1_SRAM_SF_PIPE_BUSECC_ECC_TYPE }, // 81
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM1_BUSECC_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM1_BUSECC_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM1_BUSECC_ECC_TYPE }, // 82
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK1_BUSECC_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK1_BUSECC_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK1_BUSECC_ECC_TYPE }, // 83
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_BUSECC_ECC_TYPE }, // 84
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_CACHE_TAG_PIPE_BUSECC_ECC_TYPE }, // 85
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_0_ECC_TYPE }, // 86
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_QUEUE_BUSECC_1_ECC_TYPE }, // 87
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_RMW_TAG_UPDATE_BUSECC_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_RMW_TAG_UPDATE_BUSECC_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_RMW_TAG_UPDATE_BUSECC_ECC_TYPE }, // 88
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_SRAM_SF_PIPE_BUSECC_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_SRAM_SF_PIPE_BUSECC_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW2_SRAM_SF_PIPE_BUSECC_ECC_TYPE }, // 89
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM2_BUSECC_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM2_BUSECC_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM2_BUSECC_ECC_TYPE }, // 90
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK2_BUSECC_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK2_BUSECC_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK2_BUSECC_ECC_TYPE }, // 91
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_BUSECC_ECC_TYPE }, // 92
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_CACHE_TAG_PIPE_BUSECC_ECC_TYPE }, // 93
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_0_ECC_TYPE }, // 94
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_QUEUE_BUSECC_1_ECC_TYPE }, // 95
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_RMW_TAG_UPDATE_BUSECC_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_RMW_TAG_UPDATE_BUSECC_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_RMW_TAG_UPDATE_BUSECC_ECC_TYPE }, // 96
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_SRAM_SF_PIPE_BUSECC_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_SRAM_SF_PIPE_BUSECC_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_RMW3_SRAM_SF_PIPE_BUSECC_ECC_TYPE }, // 97
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM3_BUSECC_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM3_BUSECC_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_SRAM3_BUSECC_ECC_TYPE }, // 98
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK3_BUSECC_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK3_BUSECC_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_DATARAM_BANK3_BUSECC_ECC_TYPE }, // 99
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CLEC_CLEC_SRAM_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CLEC_CLEC_SRAM_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CLEC_CLEC_SRAM_ECC_TYPE }, // 100
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_VBUSP_CFG_ECC_AGGR0_P2P_SRC_BUSECC_DUMMY_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_VBUSP_CFG_ECC_AGGR0_P2P_SRC_BUSECC_DUMMY_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_VBUSP_CFG_ECC_AGGR0_P2P_SRC_BUSECC_DUMMY_ECC_TYPE }, // 101
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_J7ES_ECC_AGGR0_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_J7ES_ECC_AGGR0_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_MSMC_J7ES_ECC_AGGR0_P2P_BRIDGE_CORE_DST_EDC_CTRL_0_ECC_TYPE }, // 102
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF1_SLV_PIPE_BUSECC_DUMMY_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF1_SLV_PIPE_BUSECC_DUMMY_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF1_SLV_PIPE_BUSECC_DUMMY_ECC_TYPE }, // 103
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF1_MST_PIPE_BUSECC_DUMMY_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF1_MST_PIPE_BUSECC_DUMMY_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF1_MST_PIPE_BUSECC_DUMMY_ECC_TYPE }, // 104
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_VBUSP_CFG_DSP4_P2P_DST_BUSECC_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_VBUSP_CFG_DSP4_P2P_DST_BUSECC_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_VBUSP_CFG_DSP4_P2P_DST_BUSECC_ECC_TYPE }, // 105
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF_0_VSAFE_SI_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF_0_VSAFE_SI_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_EMIF_0_VSAFE_SI_ECC_TYPE }, // 106
+ { CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CLEC_J7ES_CLEC_EDC_CTRL_BUSECC_ID,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CLEC_J7ES_CLEC_EDC_CTRL_BUSECC_INJECT_TYPE,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CLEC_J7ES_CLEC_EDC_CTRL_BUSECC_ECC_TYPE }, // 107
};
-const SDR_RAMIdEntry_t SDR_ECC_MainMSMCECC0RamIdTable =
+const SDR_RAMIdEntry_t SDR_ECC_mcuEccAggr0RamIdTable[SDR_MSMC_AGGR0_RAM_ID_TABLE_MAX_ENTRIES] =
{
- 0u, ((bool)false)
+ { CSL_MCU_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_WR_RAMECC_ID,
+ CSL_MCU_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_WR_RAMECC_INJECT_TYPE,
+ CSL_MCU_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_WR_RAMECC_ECC_TYPE }, // 0 - Wrapper Type
+ { CSL_MCU_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_RD_RAMECC_ID,
+ CSL_MCU_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_RD_RAMECC_INJECT_TYPE,
+ CSL_MCU_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_RD_RAMECC_ECC_TYPE }, // 1 - Wrapper Type
+ { CSL_MCU_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_ID,
+ CSL_MCU_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_INJECT_TYPE,
+ CSL_MCU_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_EDC_CTRL_ECC_TYPE }, // 2 - Interconnect Type
};
-const SDR_MemConfig_t SDR_ECC_MainMSMCECC0MemEntry =
+/** ----------------------------------------------------------------------------------
+ * @brief This structure holds the memory config for each memory subtype in MCU domain
+ * -----------------------------------------------------------------------------------
+ */
+const SDR_MemConfig_t SDR_ECC_mainMsmcAggr0MemEntries[SDR_MSMC_AGGR0_WRAPPER_RAM_IDS_TOTAL_ENTRIES] =
{
- CSL_MSRAM16KX256E0_RAM_BASE, CSL_MSRAM16KX256E0_RAM_SIZE, 4u, ((bool)true)
+ {SDR_ECC_MAIN_MSMC_MEM_WRAPPER_SUBTYPE, 0u,
+ CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CLEC_SRAM_RAMECC_SIZE, 4u, ((bool)false) },
};
+/** ----------------------------------------------------------------------------------
+ * @brief This structure holds the memory config for each memory subtype in MCU CBASS
+ * -----------------------------------------------------------------------------------
+ */
+const SDR_MemConfig_t SDR_ECC_MCUCBASSMemEntries[SDR_MCU_CBASS_WRAPPER_RAM_IDS_TOTAL_ENTRIES] =
+{
+ {SDR_ECC_MCU_CBASS_MEM_SUBTYPE_WR_RAMECC_ID, 0u,
+ CSL_MCU_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_WR_RAMECC_RAM_SIZE, 4u, ((bool)false) },
+ {SDR_ECC_MCU_CBASS_MEM_SUBTYPE_RD_RAMECC_ID, 0u,
+ CSL_MCU_ECC_AGGR0_IMCU_COR_FW_VBUSP_32B_SOC_FW_SAFEG_RD_RAMECC_RAM_SIZE, 4u, ((bool)false) },
+};
+
+/** ----------------------------------------------------------------------------------
+ * @brief This structure holds the ECC interconnect Group Checker information for
+ * SDR_ECC_R5F_MEM_SUBTYPE_VBUSM2AXI_EDC_VECTOR_ID RAM ID
+ * -----------------------------------------------------------------------------------
+ */
+const SDR_GrpChkConfig_t SDR_ECC_ramIdVbusM2AxiEdcVectorGrpEntries[SDR_PULSAR_CPU_RAM_ID_VBUSM2_AXI_EDC_VECTOR_GRP_MAX_ENTRIES] =
+{
+ {SDR_ECC_GROUP_CHECKER_TYPE_REDUNDANT, 1u, 1u},
+ {SDR_ECC_GROUP_CHECKER_TYPE_PARITY, 12u, 1u},
+ {SDR_ECC_GROUP_CHECKER_TYPE_PARITY, 4u, 1u},
+ {SDR_ECC_GROUP_CHECKER_TYPE_PARITY, 12u, 1u},
+ {SDR_ECC_GROUP_CHECKER_TYPE_PARITY, 23u, 2u},
+ {SDR_ECC_GROUP_CHECKER_TYPE_PARITY, 1u, 1u},
+ {SDR_ECC_GROUP_CHECKER_TYPE_PARITY, 10u, 1u},
+ {SDR_ECC_GROUP_CHECKER_TYPE_PARITY, 2u, 1u},
+ {SDR_ECC_GROUP_CHECKER_TYPE_PARITY, 3u, 1u},
+ {SDR_ECC_GROUP_CHECKER_TYPE_PARITY, 1u, 1u},
+ {SDR_ECC_GROUP_CHECKER_TYPE_PARITY, 2u, 1u},
+ {SDR_ECC_GROUP_CHECKER_TYPE_PARITY, 2u, 1u},
+ {SDR_ECC_GROUP_CHECKER_TYPE_PARITY, 1u, 1u},
+ {SDR_ECC_GROUP_CHECKER_TYPE_PARITY, 1u, 1u},
+ {SDR_ECC_GROUP_CHECKER_TYPE_PARITY, 1u, 1u},
+ {SDR_ECC_GROUP_CHECKER_TYPE_PARITY, 3u, 1u},
+ {SDR_ECC_GROUP_CHECKER_TYPE_PARITY, 4u, 1u},
+ {SDR_ECC_GROUP_CHECKER_TYPE_PARITY, 2u, 1u},
+ {SDR_ECC_GROUP_CHECKER_TYPE_PARITY, 2u, 1u},
+ {SDR_ECC_GROUP_CHECKER_TYPE_PARITY, 2u, 1u},
+ {SDR_ECC_GROUP_CHECKER_TYPE_REDUNDANT, 1u, 1u},
+ {SDR_ECC_GROUP_CHECKER_TYPE_EDC, 32u, 7u},
+ {SDR_ECC_GROUP_CHECKER_TYPE_EDC, 32u, 7u},
+ {SDR_ECC_GROUP_CHECKER_TYPE_PARITY, 8u, 2u},
+ {SDR_ECC_GROUP_CHECKER_TYPE_REDUNDANT, 1u, 1u},
+ {SDR_ECC_GROUP_CHECKER_TYPE_REDUNDANT, 1u, 1u},
+ {SDR_ECC_GROUP_CHECKER_TYPE_PARITY, 10u, 2u},
+ {SDR_ECC_GROUP_CHECKER_TYPE_PARITY, 3u, 1u},
+ {SDR_ECC_GROUP_CHECKER_TYPE_PARITY, 3u, 1u},
+ {SDR_ECC_GROUP_CHECKER_TYPE_PARITY, 4u, 1u},
+ {SDR_ECC_GROUP_CHECKER_TYPE_PARITY, 4u, 1u},
+ {SDR_ECC_GROUP_CHECKER_TYPE_PARITY, 1u, 1u},
+ {SDR_ECC_GROUP_CHECKER_TYPE_PARITY, 1u, 1u},
+ {SDR_ECC_GROUP_CHECKER_TYPE_PARITY, 1u, 1u},
+ {SDR_ECC_GROUP_CHECKER_TYPE_PARITY, 1u, 1u},
+ {SDR_ECC_GROUP_CHECKER_TYPE_PARITY, 10u, 2u},
+ {SDR_ECC_GROUP_CHECKER_TYPE_PARITY, 7u, 1u},
+ {SDR_ECC_GROUP_CHECKER_TYPE_PARITY, 2u, 1u},
+ {SDR_ECC_GROUP_CHECKER_TYPE_PARITY, 2u, 1u},
+ {SDR_ECC_GROUP_CHECKER_TYPE_PARITY, 1u, 1u},
+ {SDR_ECC_GROUP_CHECKER_TYPE_PARITY, 1u, 1u},
+ {SDR_ECC_GROUP_CHECKER_TYPE_PARITY, 1u, 1u},
+ {SDR_ECC_GROUP_CHECKER_TYPE_PARITY, 1u, 1u},
+ {SDR_ECC_GROUP_CHECKER_TYPE_PARITY, 2u, 1u},
+ {SDR_ECC_GROUP_CHECKER_TYPE_PARITY, 2u, 1u},
+ {SDR_ECC_GROUP_CHECKER_TYPE_PARITY, 1u, 1u},
+ {SDR_ECC_GROUP_CHECKER_TYPE_PARITY, 1u, 1u},
+ {SDR_ECC_GROUP_CHECKER_TYPE_PARITY, 1u, 1u},
+ {SDR_ECC_GROUP_CHECKER_TYPE_PARITY, 1u, 1u},
+};
+
+// TODO - NEED TO ADD MSMC INTERCONNECT GROUP CHECKER FOR MSMC RAM ID
+
#endif /* INCLUDE_SDR_ECC_SOC_H_ */
diff --git a/packages/ti/diag/sdr/src/r5/sdr_esm_core.c b/packages/ti/diag/sdr/src/r5/sdr_esm_core.c
index 1f8b7a55a70141a37823d1d249786c15c26e4c30..e099fbce76b173908d2f04ed872c57d8be76bb32 100644 (file)
return (instValid);
}
-
-
-
/** ============================================================================
*
* \brief Handle any event that needs to be handled locally before
@@ -264,7 +261,61 @@ bool SDR_ESM_handleIntSrc(const SDR_ESM_Instance_t *pInstance, uint32_t intSrc)
handledFlag = pInstance->WDTCallBackFunction(SDR_ESM_TIMER_ID_1);
}
break;
+#ifdef SOC_J721E
+ case SDR_ESM_MAIN_MSMC_ECC_AGGR0_SEC_INT:
+ if ((void *)pInstance->eccCallBackFunction != ((void *)0u)) {
+ /* Call back function for Single bit ECC error */
+ pInstance->eccCallBackFunction(SDR_ESM_ECC_PARAM_MAIN_MSMC_AGGR0_SEC_ERROR,
+ SDR_ESM_ERRORADDR_INVALID);
+ handledFlag = ((bool)true);
+ }
+ break;
+
+ case SDR_ESM_MAIN_MSMC_ECC_AGGR0_DED_INT:
+ if ((void *)pInstance->eccCallBackFunction != ((void *)0u)) {
+ /* Call back function for Double bit ECC error */
+ pInstance->eccCallBackFunction(SDR_ESM_ECC_PARAM_MAIN_MSMC_AGGR0_DED_ERROR,
+ SDR_ESM_ERRORADDR_INVALID);
+ handledFlag = ((bool)true);
+ }
+ break;
+ case SDR_ESM_MAIN_A72_ECC_AGGR0_SEC_INT:
+ if ((void *)pInstance->eccCallBackFunction != ((void *)0u)) {
+ /* Call back function for Single bit ECC error */
+ pInstance->eccCallBackFunction(SDR_ESM_ECC_PARAM_MAIN_A72_AGGR0_SEC_ERROR,
+ SDR_ESM_ERRORADDR_INVALID);
+ handledFlag = ((bool)true);
+ }
+ break;
+
+ case SDR_ESM_MAIN_A72_ECC_AGGR0_DED_INT:
+ if ((void *)pInstance->eccCallBackFunction != ((void *)0u)) {
+ /* Call back function for Double bit ECC error */
+ pInstance->eccCallBackFunction(SDR_ESM_ECC_PARAM_MAIN_A72_AGGR0_DED_ERROR ,
+ SDR_ESM_ERRORADDR_INVALID);
+ handledFlag = ((bool)true);
+ }
+ break;
+
+ case SDR_ESM_MCU_CBASS_ECC_AGGR_SEC_INT:
+ if ((void *)pInstance->eccCallBackFunction != ((void *)0u)) {
+ /* Call back function for Single bit ECC error */
+ pInstance->eccCallBackFunction(SDR_ESM_ECC_PARAM_MCU_CBASS_SEC_ERROR,
+ SDR_ESM_ERRORADDR_INVALID);
+ handledFlag = ((bool)true);
+ }
+ break;
+
+ case SDR_ESM_MCU_CBASS_ECC_AGGR_DED_INT:
+ if ((void *)pInstance->eccCallBackFunction != ((void *)0u)) {
+ /* Call back function for Single bit ECC error */
+ pInstance->eccCallBackFunction(SDR_ESM_ECC_PARAM_MCU_CBASS_DED_ERROR,
+ SDR_ESM_ERRORADDR_INVALID);
+ handledFlag = ((bool)true);
+ }
+ break;
+#endif
default:
/* No actions for other ESM Events */
break;
diff --git a/packages/ti/diag/sdr/src/r5/sdr_exception.c b/packages/ti/diag/sdr/src/r5/sdr_exception.c
index 39dd9179fad330d8b9620fcbb678c130b36d0d84..5f0ebd7842754ac855d3dc5c16b8f2822efeea5b 100644 (file)
if ((void *)SDR_EXCEPTION_instance.ECCCallBackFunction != ((void *)0u)) {
SDR_EXCEPTION_instance.ECCCallBackFunction(
SDR_LOCAL_EXCEPTION_DED_ERROR,
- ifarValue);
+ ifarValue,
+ SDR_ESM_ERRORRAMID_INVALID,
+ SDR_ESM_ERRORBITOFFSET_INVALID,
+ SDR_ESM_ERRORBITGROUP_INVALID);
}
} else if ((ifsrValue & SDR_EXCEPTION_ASYNC_PARITY_OR_ECC_ERROR_MASK)
== SDR_EXCEPTION_ASYNC_PARITY_OR_ECC_ERROR_MASK) {
if ((void *)SDR_EXCEPTION_instance.ECCCallBackFunction != ((void *)0u)) {
SDR_EXCEPTION_instance.ECCCallBackFunction(
SDR_LOCAL_EXCEPTION_DED_ERROR,
- SDR_ESM_ERRORADDR_INVALID);
+ SDR_ESM_ERRORADDR_INVALID,
+ SDR_ESM_ERRORRAMID_INVALID,
+ SDR_ESM_ERRORBITOFFSET_INVALID,
+ SDR_ESM_ERRORBITGROUP_INVALID);
}
} else {
/* Execute callback function */
if ((void *)SDR_EXCEPTION_instance.ECCCallBackFunction != ((void *)0u)) {
SDR_EXCEPTION_instance.ECCCallBackFunction(
SDR_ESM_ECC_PARAM_MCU_CPU0_DED_ERROR,
- dfarValue);
+ dfarValue,
+ SDR_ESM_ERRORRAMID_INVALID,
+ SDR_ESM_ERRORBITOFFSET_INVALID,
+ SDR_ESM_ERRORBITGROUP_INVALID);
}
} else if ((dfsrValue & SDR_EXCEPTION_ASYNC_PARITY_OR_ECC_ERROR_MASK)
== SDR_EXCEPTION_ASYNC_PARITY_OR_ECC_ERROR_MASK) {
if ((void *)SDR_EXCEPTION_instance.ECCCallBackFunction != ((void *)0u)) {
SDR_EXCEPTION_instance.ECCCallBackFunction(
SDR_ESM_ECC_PARAM_MCU_CPU0_DED_ERROR,
- SDR_ESM_ERRORADDR_INVALID);
+ SDR_ESM_ERRORADDR_INVALID,
+ SDR_ESM_ERRORRAMID_INVALID,
+ SDR_ESM_ERRORBITOFFSET_INVALID,
+ SDR_ESM_ERRORBITGROUP_INVALID);
}
} else {
/* Get the fault address */
index 7a395fa8e6c12995ca17eb12843b124c64d0a9ec..7c3c411fb94ba8bc9acf3e7ad68e26094b3fb053 100644 (file)
#include <sdr_esm.h>
#include <sdr_exception.h>
-
+#include <ti/csl/csl_rat.h>
#include <ti/csl/csl_ecc_aggr.h>
#include "sdr_utils.h"
#define ECC_AGGR_LINE_SIZE (4)
+#define SDR_ECC_INVALID_SELF_TEST_RAM_ID (0xffffffffu)
+
/** ---------------------------------------------------------------------------
* @brief This enumerator defines the values for ecc self test flag
* ----------------------------------------------------------------------------
/* Global objects */
static SDR_ECC_Instance_t SDR_ECC_instance[SDR_ECC_AGGREGATOR_MAX_ENTRIES];
-extern const SDR_RAMIdEntry_t SDR_ECC_mcuArmssRamIdTable[SDR_PULSAR_CPU_RAM_ID_TABLE_MAX_ENTRIES];
-
/* Local functions */
static SDR_Result SDR_ECC_getRamId(SDR_ECC_MemType eccMemType, SDR_ECC_MemSubType memSubType,
- uint32_t *ramIdP);
-static SDR_Result SDR_ECC_getAggregatorType(SDR_ECC_MemType eccMemType, SDR_ECC_MemSubType memSubType,
- bool *pIinjectOnly);
+ uint32_t *ramIdP, uint32_t *pRAMIdType);
+static SDR_Result SDR_ECC_getAggregatorType(SDR_ECC_MemType eccMemType,
+ SDR_ECC_MemSubType memSubType, uint32_t *pIinjectOnly);
+static SDR_Result SDR_ECC_getAggrBaseAddr(SDR_ECC_MemType eccMemType, CSL_ecc_aggrRegs **pEccAggr);
static SDR_Result SDR_ECC_memoryRefresh(uint32_t *memAddr, size_t size);
static void SDR_ECC_triggerAccessForEcc(const uint32_t *memoryAccessAddr);
uint32_t *bitLocation);
static void SDR_ECC_handleEccAggrEvent (SDR_ECC_MemType eccMemType, uint32_t errorSrc,
uint32_t errorAddr);
-static void SDR_ECC_ESMCallBackFunction (uint32_t errorSrc, uint32_t errorAddr);
+static void SDR_ECC_ESMCallBackFunction_MCU (uint32_t errorSrc, uint32_t errorAddr);
+#ifdef SOC_J721E
+static void SDR_ECC_ESMCallBackFunction_MAIN (uint32_t errorSrc, uint32_t errorAddr);
+#endif
static SDR_Result SDR_ECC_checkMemoryType(SDR_ECC_MemType eccMemType, SDR_ECC_MemSubType memSubType);
+static SDR_Result SDR_ECC_searchMemEntryTable(SDR_ECC_MemSubType memSubType,
+ const SDR_MemConfig_t memEntryTable[],
+ uint32_t tableSize,
+ SDR_MemConfig_t *pMemConfig);
+
+#ifdef SOC_J721E
+#pragma DATA_SECTION(mappedEccRegs, ".my_aggr_reg");
+/* Note that this example provide a single instance of mappedEccRegs (which is RAT-mapped
+ * ECC aggregator configuration registers that lie in larger address space than the 32-bit
+ * address space on the MCU. If more ECC aggregator registers need to be mapped, additional
+ * global variables are needed for each set of aggregator registers, and SDR_ECC_init() needs
+ * to be modified to make SDR_ECC_mapEccAggrReg() calls for each one that needs to be mapped.
+ * The expectation is that this mapping will be retained in perpetuity because in order to obtain
+ * information about the ECC errors, the ECC Aggregator configuration registers require to be
+ * visible from the MCU. */
+CSL_ecc_aggrRegs mappedEccRegs;
+#endif
+
/** ============================================================================*
*
* \brief Get the Error Source corresponding to the inject error
@@ -155,6 +177,76 @@ static uint32_t SDR_ECC_getDetectErrorSource (SDR_ECC_InjectErrorType injectEror
return errorSource;
}
+#ifdef SOC_J721E
+
+/* Returns index >= 0 if successful, otherwise returns -1 if failure */
+static int32_t SDR_ECC_mapRatEccAggrBaseAddress(uint64_t highEccAggrAddr, int32_t desiredMapIdx, CSL_ecc_aggrRegs **ppEccAggr)
+{
+ bool result;
+ int32_t mappedIdx;
+
+ CSL_RatTranslationCfgInfo translationCfg;
+
+ /* Add RAT configuration to access address > 32bit address range */
+ translationCfg.translatedAddress = highEccAggrAddr;
+ translationCfg.sizeInBytes = sizeof(CSL_ecc_aggrRegs);
+ translationCfg.baseAddress = (uint32_t)(*ppEccAggr);
+
+ /* Set up RAT translation */
+ result = CSL_ratConfigRegionTranslation((CSL_ratRegs *)CSL_MCU_ARMSS_RAT_CFG_BASE,
+ desiredMapIdx, &translationCfg);
+ if (result == false) {
+ mappedIdx = -1;
+ } else {
+ mappedIdx = desiredMapIdx;
+ }
+
+ return (mappedIdx);
+}
+
+
+
+/** ============================================================================*
+ *
+ * \brief Map an ECC Aggregator using the RAT
+ *
+ * @n This function is called prior to SDR_ECC_init() for an ECC aggregator
+ * where the base address of the ECC Aggegator is greater than 32-bits, so
+ * needs a mapping by the RAT.
+ *
+ * \param1 errorType: error Type
+ *
+ * \return error Source or SDR_ECC_INVALID_ERROR_SOURCE in case of error
+ */
+/* Returns index >= 0 if successful, otherwise returns -1 if failure */
+SDR_Result SDR_ECC_mapEccAggrReg(SDR_ECC_MemType eccMemType, CSL_ecc_aggrRegs **ppEccAggr)
+{
+ SDR_Result retVal = SDR_PASS;
+ CSL_ecc_aggrRegs *eccAggrRegs;
+ int32_t mapIdx;
+
+ if ((NULL == ppEccAggr) || (NULL == *ppEccAggr))
+ {
+ retVal = SDR_BADARGS;
+ } else {
+ eccAggrRegs = *ppEccAggr;
+ mapIdx = SDR_ECC_mapRatEccAggrBaseAddress(SDR_ECC_aggrHighBaseAddressTable[eccMemType - \
+ SDR_ECC_MEMTYPE_MAIN_MSMC_AGGR0],
+ eccMemType - SDR_ECC_MEMTYPE_MAIN_MSMC_AGGR0,
+ &eccAggrRegs);
+ if (mapIdx < 0) {
+ retVal = SDR_FAIL;
+ } else {
+ /* Mapping was successful, so fill the array with the local address */
+ SDR_ECC_aggrHighBaseAddressTableTrans[mapIdx] = eccAggrRegs;
+ }
+ }
+
+ return retVal;
+}
+
+#endif
+
/** ============================================================================*
*
* \brief Ecc call back function registered with exception handler
@@ -169,15 +261,21 @@ static void SDR_ECC_handleEccAggrEvent (SDR_ECC_MemType eccMemType, uint32_t err
uint32_t errorAddr)
{
CSL_ecc_aggrRegs *eccAggrRegs;
+ CSL_Ecc_AggrEccRamErrorStatusInfo eccErrorStatusWrap;
+ CSL_Ecc_AggrEDCInterconnectErrorStatusInfo eccErrorStatusInterconn;
+ uint8_t bitErrCnt;
uint32_t ramId=0;
+ uint32_t ramIdType=0;
SDR_Result retVal;
SDR_ECC_MemSubType memSubType;
+ SDR_MemConfig_t memConfig;
uint32_t i;
+ uint64_t bitErrorOffset, bitErrorGroup;
bool eventFound = ((bool)false);
bool eventFound1;
int32_t cslResult;
- eccAggrRegs = (SDR_ECC_aggrBaseAddressTable[eccMemType]);
+ SDR_ECC_getAggrBaseAddr(eccMemType, &eccAggrRegs);
/* Check which Ram Id triggered the error */
for (i = ((uint32_t)0U);
@@ -185,19 +283,71 @@ static void SDR_ECC_handleEccAggrEvent (SDR_ECC_MemType eccMemType, uint32_t err
i++) {
/* Get corresponding ram Id */
memSubType = SDR_ECC_instance[eccMemType].eccInitConfig.pMemSubTypeList[i];
- retVal = SDR_ECC_getRamId(eccMemType, memSubType, &ramId);
+ retVal = SDR_ECC_getRamId(eccMemType, memSubType, &ramId, &ramIdType);
if (retVal != SDR_PASS) {
/* Unexpected FAILURE: call Assert */
SDR_assertExternalFunction(SDR_ECC_RAM_ID_NOT_FOUND);
continue;
}
- /* Check if this event in triggered, by reading the ECC aggregator status register */
- cslResult = CSL_ecc_aggrIsEccRamIntrPending(eccAggrRegs, ramId, errorSrc, &eventFound1);
+ /* Check if this event in triggered, by reading the ECC aggregator status
+ * register */
+ if (ramIdType == SDR_ECC_RAM_ID_TYPE_WRAPPER) {
+ cslResult = CSL_ecc_aggrIsEccRamIntrPending(eccAggrRegs,
+ ramId,
+ errorSrc,
+ &eventFound1);
+ } else if (ramIdType == SDR_ECC_RAM_ID_TYPE_INTERCONNECT) {
+ cslResult = CSL_ecc_aggrIsEDCInterconnectIntrPending(eccAggrRegs,
+ ramId,
+ errorSrc,
+ &eventFound1);
+ }
+
if((cslResult == CSL_PASS) && (eventFound1)) {
eventFound = ((bool)true);
- /* Clear the event */
- (void)CSL_ecc_aggrClrEccRamIntrPending(eccAggrRegs, ramId, errorSrc);
+
+ /* Read the locations of the bit errors */
+ if (ramIdType == SDR_ECC_RAM_ID_TYPE_WRAPPER) {
+ /* Get the error status information for Wrapper type */
+ (void)CSL_ecc_aggrGetEccRamErrorStatus(eccAggrRegs,
+ ramId,
+ &eccErrorStatusWrap);
+ /* Get the total number of interrupts pending */
+ if (errorSrc == CSL_ECC_AGGR_INTR_SRC_SINGLE_BIT) {
+ bitErrCnt = eccErrorStatusWrap.singleBitErrorCount;
+ } else if (errorSrc == CSL_ECC_AGGR_INTR_SRC_DOUBLE_BIT) {
+ bitErrCnt = eccErrorStatusWrap.doubleBitErrorCount;
+ }
+ } else if (ramIdType == SDR_ECC_RAM_ID_TYPE_INTERCONNECT) {
+ (void)CSL_ecc_aggrGetEDCInterconnectErrorStatus(eccAggrRegs,
+ ramId,
+ &eccErrorStatusInterconn);
+
+ /* Get the total number of Inject interrupts pending. Note that
+ * "Inject" interrupts are separate from "Normal" interrupts for
+ * Interconnect ECC type */
+ if (errorSrc == CSL_ECC_AGGR_INTR_SRC_SINGLE_BIT) {
+ bitErrCnt = eccErrorStatusInterconn.injectSingleBitErrorCount;
+ } else if (errorSrc == CSL_ECC_AGGR_INTR_SRC_DOUBLE_BIT) {
+ bitErrCnt = eccErrorStatusInterconn.injectDoubleBitErrorCount;
+ }
+ }
+
+ /* Clear the event(s) */
+ if (ramIdType == SDR_ECC_RAM_ID_TYPE_WRAPPER) {
+ (void)CSL_ecc_aggrClrEccRamNIntrPending(eccAggrRegs,
+ ramId,
+ errorSrc,
+ bitErrCnt);
+ } else if (ramIdType == SDR_ECC_RAM_ID_TYPE_INTERCONNECT) {
+ (void)CSL_ecc_aggrClrEDCInterconnectNIntrPending(eccAggrRegs,
+ ramId,
+ errorSrc,
+ CSL_ECC_AGGR_ERROR_SUBTYPE_INJECT,
+ bitErrCnt);
+ }
+
/* If it matches self test set flag */
if ((errorSrc
== SDR_ECC_getDetectErrorSource(SDR_ECC_instance[eccMemType].eccSelfTestErrorType))
@@ -205,14 +355,42 @@ static void SDR_ECC_handleEccAggrEvent (SDR_ECC_MemType eccMemType, uint32_t err
SDR_ECC_instance[eccMemType].eccErrorFlag = SDR_ECC_ERROR_FLAG_TRIGGERED;
} else {
+ if (ramIdType == SDR_ECC_RAM_ID_TYPE_WRAPPER) {
+ retVal = SDR_ECC_getMemConfig(eccMemType, ramId, &memConfig);
+ if (retVal == SDR_PASS) {
+ if (errorSrc == CSL_ECC_AGGR_INTR_SRC_SINGLE_BIT) {
+ bitErrorOffset = eccErrorStatusWrap.eccRow * memConfig.rowSize +
+ eccErrorStatusWrap.eccBit1;
+ } else if (errorSrc == CSL_ECC_AGGR_INTR_SRC_DOUBLE_BIT) {
+ /* In case of DED error, eccBit1 is not valid, so calculate
+ * the bit offset of the start of the row with the DED error */
+ bitErrorOffset = eccErrorStatusWrap.eccRow * memConfig.rowSize;
+ }
+ }
+ /* Bit error group not used for Wrapper type */
+ bitErrorGroup = 0;
+ } else if (ramIdType == SDR_ECC_RAM_ID_TYPE_INTERCONNECT) {
+ bitErrorGroup = eccErrorStatusInterconn.eccGroup;
+ if (errorSrc == CSL_ECC_AGGR_INTR_SRC_SINGLE_BIT) {
+ bitErrorOffset = eccErrorStatusInterconn.eccBit1;
+ } else if (errorSrc == CSL_ECC_AGGR_INTR_SRC_DOUBLE_BIT) {
+ /* In case of DED error, eccBit1 is not valid */
+ bitErrorOffset = 0;
+ }
+ }
+
/* Call application callback function to indicate error */
- SDR_ECC_applicationCallbackFunction(errorSrc, errorAddr);
+ SDR_ECC_applicationCallbackFunction(errorSrc,
+ errorAddr,
+ ramId,
+ bitErrorOffset,
+ bitErrorGroup);
}
- }
- }
+ } /* if((cslResult == CSL_PASS) && (eventFound1)) { */
+ } /* RAM ID for loop */
/* Ack Ecc aggregator error */
- cslResult = CSL_ecc_aggrAckIntr(eccAggrRegs, CSL_ECC_AGGR_INTR_SRC_SINGLE_BIT);
+ cslResult = CSL_ecc_aggrAckIntr(eccAggrRegs, errorSrc);
if ((cslResult != CSL_PASS) || (!eventFound)) {
/* Unexpected event; Call assert */
SDR_assertExternalFunction(SDR_ECC_INTERRUPT_WITH_NOEVENT);
@@ -228,10 +406,20 @@ static void SDR_ECC_handleEccAggrEvent (SDR_ECC_MemType eccMemType, uint32_t err
*
* \param1 errorSrc: source of the ECC error reported.
* \param2 errorAddr: Error address at which the actual error happened
+ * \param3 ramId: ramId at which the actual error happened
+ * \param4 bitErrorOffset: offset within the ramId that the bit error occurred
+ * For SEC errors, this contains the exact bit location for the single
+ * corrected error. For DED Wrapper errors, this contains the bit location
+ * of the start of the row where the double error occurred. For DED
+ * Interconnect errors, this field is invalid and set to 0.
+ * \param5 bitErrorGroup: group checker that reported the error
+ * (Interconnect ECC type only).
*
* \return None
*/
-static void SDR_ECC_callBackFunction (uint32_t errorSrc, uint32_t errorAddr)
+static void SDR_ECC_callBackFunction (uint32_t errorSrc, uint32_t errorAddr,
+ uint32_t ramId, uint64_t bitErrorOffset,
+ uint32_t bitErrorGroup)
{
SDR_ECC_MemType eccMemType;
SDR_ECC_instance[eccMemType].eccErrorFlag = SDR_ECC_ERROR_FLAG_TRIGGERED;
} else {
/* Execute call back */
- SDR_ECC_applicationCallbackFunction(errorSrc, errorAddr);
+ SDR_ECC_applicationCallbackFunction(errorSrc,
+ errorAddr,
+ ramId,
+ bitErrorOffset,
+ bitErrorGroup);
}
break;
/** ============================================================================*
*
- * \brief Ecc call back function registered with ESM handler
+ * \brief Ecc call back function registered with MCU ESM handler
*
* \param1 errorSrc: Error source
*
* \return None
*/
-static void SDR_ECC_ESMCallBackFunction (uint32_t errorSrc, uint32_t errorAddr)
+static void SDR_ECC_ESMCallBackFunction_MCU (uint32_t errorSrc, uint32_t errorAddr)
{
SDR_ECC_MemType eccMemType;
-
+ CSL_Ecc_AggrIntrSrc intrSrcType;
/* Check Error Source and call acknowledge appropriate interrupt */
switch (errorSrc) {
@@ -300,24 +492,45 @@ static void SDR_ECC_ESMCallBackFunction (uint32_t errorSrc, uint32_t errorAddr)
case SDR_ESM_ECC_PARAM_MCU_CPU0_DED_ERROR:
case SDR_ESM_ECC_PARAM_MCU_CPU1_SEC_ERROR:
case SDR_ESM_ECC_PARAM_MCU_CPU1_DED_ERROR:
+ case SDR_ESM_ECC_PARAM_MCU_CBASS_SEC_ERROR:
+ case SDR_ESM_ECC_PARAM_MCU_CBASS_DED_ERROR:
/* Get corresponding Memory type */
switch(errorSrc)
{
default:
case SDR_ESM_ECC_PARAM_MCU_CPU0_SEC_ERROR:
+ intrSrcType = CSL_ECC_AGGR_INTR_SRC_SINGLE_BIT;
+ eccMemType = SDR_ECC_MEMTYPE_MCU_R5F0_CORE;
+ break;
+
case SDR_ESM_ECC_PARAM_MCU_CPU0_DED_ERROR:
- eccMemType = SDR_ECC_MEMTYPE_MCU_R5F0_CORE;
+ intrSrcType = CSL_ECC_AGGR_INTR_SRC_DOUBLE_BIT;
+ eccMemType = SDR_ECC_MEMTYPE_MCU_R5F0_CORE;
break;
case SDR_ESM_ECC_PARAM_MCU_CPU1_SEC_ERROR:
+ intrSrcType = CSL_ECC_AGGR_INTR_SRC_SINGLE_BIT;
+ eccMemType = SDR_ECC_MEMTYPE_MCU_R5F1_CORE;
+ break;
+
case SDR_ESM_ECC_PARAM_MCU_CPU1_DED_ERROR:
- eccMemType = SDR_ECC_MEMTYPE_MCU_R5F1_CORE;
+ intrSrcType = CSL_ECC_AGGR_INTR_SRC_DOUBLE_BIT;
+ eccMemType = SDR_ECC_MEMTYPE_MCU_R5F1_CORE;
+ break;
+
+ case SDR_ESM_ECC_PARAM_MCU_CBASS_SEC_ERROR:
+ intrSrcType = CSL_ECC_AGGR_INTR_SRC_SINGLE_BIT;
+ eccMemType = SDR_ECC_MEMTYPE_MCU_CBASS_ECC_AGGR0;
break;
+ case SDR_ESM_ECC_PARAM_MCU_CBASS_DED_ERROR:
+ intrSrcType = CSL_ECC_AGGR_INTR_SRC_DOUBLE_BIT;
+ eccMemType = SDR_ECC_MEMTYPE_MCU_CBASS_ECC_AGGR0;
+ break;
}
/* Handle ECC Aggregator event */
- SDR_ECC_handleEccAggrEvent(eccMemType, errorSrc, errorAddr);
+ SDR_ECC_handleEccAggrEvent(eccMemType, intrSrcType, errorAddr);
break;
@@ -327,6 +540,91 @@ static void SDR_ECC_ESMCallBackFunction (uint32_t errorSrc, uint32_t errorAddr)
}
+
+#ifdef SOC_J721E
+/** ============================================================================*
+ *
+ * \brief Ecc call back function registered with Main Domain ESM handler
+ *
+ * \param1 errorSrc: Error source
+ *
+ * \return None
+ */
+static void SDR_ECC_ESMCallBackFunction_MAIN (uint32_t errorSrc, uint32_t errorAddr)
+{
+ SDR_ECC_MemType eccMemType;
+ uint32_t eccEventType;
+
+ /* Check Error Source and call acknowledge appropriate interrupt */
+ switch (errorSrc) {
+ case SDR_ESM_ECC_PARAM_MAIN_MSMC_AGGR0_SEC_ERROR:
+ case SDR_ESM_ECC_PARAM_MAIN_MSMC_AGGR0_DED_ERROR:
+ case SDR_ESM_ECC_PARAM_MAIN_A72_AGGR0_SEC_ERROR:
+ case SDR_ESM_ECC_PARAM_MAIN_A72_AGGR0_DED_ERROR:
+ /* Get corresponding Memory type */
+ switch(errorSrc)
+ {
+ default:
+ case SDR_ESM_ECC_PARAM_MAIN_MSMC_AGGR0_SEC_ERROR:
+ eccMemType = SDR_ECC_MEMTYPE_MAIN_MSMC_AGGR0;
+ eccEventType = CSL_ECC_AGGR_INTR_SRC_SINGLE_BIT;
+ break;
+ case SDR_ESM_ECC_PARAM_MAIN_MSMC_AGGR0_DED_ERROR:
+ eccMemType = SDR_ECC_MEMTYPE_MAIN_MSMC_AGGR0;
+ eccEventType = CSL_ECC_AGGR_INTR_SRC_DOUBLE_BIT;
+ break;
+ case SDR_ESM_ECC_PARAM_MAIN_A72_AGGR0_SEC_ERROR:
+ eccMemType = SDR_ECC_MEMTYPE_MAIN_A72_AGGR0;
+ eccEventType = CSL_ECC_AGGR_INTR_SRC_SINGLE_BIT;
+ break;
+ case SDR_ESM_ECC_PARAM_MAIN_A72_AGGR0_DED_ERROR:
+ eccMemType = SDR_ECC_MEMTYPE_MAIN_A72_AGGR0;
+ eccEventType = CSL_ECC_AGGR_INTR_SRC_DOUBLE_BIT;
+ break;
+ }
+ /* Handle ECC Aggregator event */
+ SDR_ECC_handleEccAggrEvent(eccMemType, eccEventType, errorAddr);
+
+ break;
+
+ default:
+ break;
+ }
+
+
+}
+#endif
+
+/** ============================================================================*
+ *
+ * \brief Initializes an ESM module for usage with ECC module
+ *
+ * \param esmInstType: Instance of ESM
+ *
+ * \return SDR_PASS : Success; SDR_FAIL for failures
+ */
+SDR_Result SDR_ECC_initEsm (const SDR_ESM_InstanceType esmInstType)
+{
+#ifdef SOC_J721E
+ if (esmInstType == SDR_ESM_INSTANCE_MAIN)
+ {
+ (void)SDR_ESM_registerECCHandler(esmInstType,
+ &SDR_ECC_ESMCallBackFunction_MAIN);
+
+ } else { /* MCU domain */
+#endif
+ (void)SDR_ESM_registerECCHandler(esmInstType,
+ &SDR_ECC_ESMCallBackFunction_MCU);
+ /* currently as this is not reported by ESM, register with
+ exception handler */
+ SDR_EXCEPTION_registerECCHandler(&SDR_ECC_callBackFunction);
+#ifdef SOC_J721E
+ }
+#endif
+
+ return SDR_PASS;
+}
+
/** ============================================================================*
*
* \brief Initializes ECC module for ECC detection
CSL_ecc_aggrRegs *eccAggrRegs;
uint32_t numMemRegions;
SDR_Result retVal = SDR_PASS;
- uint32_t ramId;
+ uint32_t ramId, ramIdType;
uint32_t i;
int32_t cslResult;
SDR_ECC_MemSubType memSubType;
- bool injectOnlyFlag;
+ uint32_t injectOnlyFlag;
if (pECCInitConfig == NULL) {
retVal = SDR_BADARGS;
}
if (retVal == SDR_PASS) {
-
+#ifdef SOC_J721E
+ if (eccMemType >= SDR_ECC_MEMTYPE_MAIN_MSMC_AGGR0)
+ {
+ /* Currently, only MAIN MSMC AGGR0 configuration registers can be
+ * mapped by this code. To expand to other aggregators, additional
+ * instances of "mappedEccRegs" are needed and should be mapped to
+ * those additional aggregators. */
+ eccAggrRegs = &mappedEccRegs;
+ retVal = SDR_ECC_mapEccAggrReg(eccMemType, &eccAggrRegs);
+ } else {
+ eccAggrRegs = (SDR_ECC_aggrBaseAddressTable[eccMemType]);
+ }
+#else
eccAggrRegs = (SDR_ECC_aggrBaseAddressTable[eccMemType]);
+#endif
/* Disable all interrupts to start clean */
(void)CSL_ecc_aggrDisableAllIntrs(eccAggrRegs);
}
}
if (retVal == SDR_PASS) {
-
- /* Register error interrupt call back function */
- /* No need to check return value , as it is just based on null check*/
- (void)SDR_ESM_registerECCHandler(SDR_ESM_INSTANCE_MCU,
- &SDR_ECC_ESMCallBackFunction);
- /* currently as this is not reported by ESM, register with
- exception handler */
- SDR_EXCEPTION_registerECCHandler(&SDR_ECC_callBackFunction);
-
/* Enable ECC */
for ( i = ((uint32_t)0U); i < pECCInitConfig->numRams; i++) {
memSubType = pECCInitConfig->pMemSubTypeList[i];
/* Get the corresponding ram Id */
- retVal = SDR_ECC_getRamId(eccMemType, memSubType, &ramId);
+ retVal = SDR_ECC_getRamId(eccMemType, memSubType, &ramId, &ramIdType);
if (retVal == SDR_PASS) {
/* Get the corresponding ram Id */
retVal = SDR_FAIL;
}
} else {
-
- /* Enables ECC, ecc checkmreg, rmw parity errors */
- cslResult = CSL_ecc_aggrConfigEccRam(eccAggrRegs,
- ramId, (bool)true, (bool)true, (bool)true);
- if (cslResult != CSL_PASS) {
- retVal = SDR_FAIL;
+ if (ramIdType == SDR_ECC_RAM_ID_TYPE_INTERCONNECT)
+ {
+ /* Enables ECC, ecc checkmreg, rmw parity errors */
+ cslResult = CSL_ecc_aggrConfigEDCInterconnect(eccAggrRegs,
+ ramId, (bool)true);
+ if (cslResult != CSL_PASS) {
+ retVal = SDR_FAIL;
+ }
+ }
+ else
+ {
+ /* Enables ECC, ecc checkmreg, rmw parity errors */
+ cslResult = CSL_ecc_aggrConfigEccRam(eccAggrRegs,
+ ramId, (bool)true, (bool)true, (bool)true);
+ if (cslResult != CSL_PASS) {
+ retVal = SDR_FAIL;
+ }
}
}
}
/* Initialize object for self test */
SDR_ECC_instance[eccMemType].eccErrorFlag = SDR_ECC_ERROR_FLAG_NONE;
SDR_ECC_instance[eccMemType].eccSelfTestErrorType = SDR_INJECT_ECC_NO_ERROR;
- SDR_ECC_instance[eccMemType].eccSelfTestRamId = ((uint32_t)0u);
+ SDR_ECC_instance[eccMemType].eccSelfTestRamId = (SDR_ECC_INVALID_SELF_TEST_RAM_ID);
SDR_ECC_instance[eccMemType].eccSelfTestAddr = NULL;
}
{
SDR_Result result=SDR_PASS;
SDR_MemConfig_t memConfig;
+ uint32_t ramId, ramIdType;
- /* Get memory configuration */
- result = SDR_ECC_getMemConfig(eccMemType, memSubType, &memConfig);
- if (result == SDR_PASS) {
+ /* Get Ram Id to check if memSubType is of Wrapper RAM ID type */
+ result = SDR_ECC_getRamId(eccMemType, memSubType, &ramId, &ramIdType);
- /* Initialize only if readable */
- if (memConfig.readable) {
- /* Initialised the whole memory so that ECC is updated */
- result = SDR_ECC_memoryRefresh((uint32_t *)memConfig.memStartAddr,
- (size_t)memConfig.size);
+ if ((result == SDR_PASS) && (ramIdType == SDR_ECC_RAM_ID_TYPE_WRAPPER))
+ {
+ /* Get memory configuration for memSubType of Wrapper RAM ID type */
+ result = SDR_ECC_getMemConfig(eccMemType, memSubType, &memConfig);
+ if (result == SDR_PASS) {
+
+ /* Initialize only if readable */
+ if (memConfig.readable) {
+ /* Initialised the whole memory so that ECC is updated */
+ result = SDR_ECC_memoryRefresh((uint32_t *)memConfig.memStartAddr,
+ (size_t)memConfig.size);
+ }
}
}
+ /* If RAM ID was found, but ramIdType is SDR_ECC_RAM_ID_TYPE_INTERCONNECT,
+ * then no initialization is required and success is returned */
return result;
}
SDR_Result retVal = SDR_PASS;
uint32_t timeCount = 0;
uint32_t testLocationPreserve;
- uint32_t ramId;
+ uint32_t ramId, ramIdType;
uint32_t retVal2;
uint32_t *testLocationAddress;
SDR_MemConfig_t memConfig;
/* Configure error configuration based on Test type */
/* Get Ram Id */
retVal = SDR_ECC_getRamId(eccMemType, memSubType,
- &ramId);
+ &ramId, &ramIdType);
}
if (retVal == SDR_PASS) {
- /* Get memory configuration */
- retVal = SDR_ECC_getMemConfig(eccMemType, memSubType, &memConfig);
+ if (ramIdType == SDR_ECC_RAM_ID_TYPE_WRAPPER) {
+ /* Get memory configuration only for Wrapper RAM ID's */
+ retVal = SDR_ECC_getMemConfig(eccMemType, memSubType, &memConfig);
+ }
}
if (retVal == SDR_PASS) {
/* Reset self test error flag */
SDR_ECC_instance[eccMemType].eccErrorFlag = SDR_ECC_ERROR_FLAG_NONE;
+ SDR_ECC_instance[eccMemType].eccSelfTestErrorType = SDR_INJECT_ECC_NO_ERROR;
+ SDR_ECC_instance[eccMemType].eccSelfTestRamId = (SDR_ECC_INVALID_SELF_TEST_RAM_ID);
+ SDR_ECC_instance[eccMemType].eccSelfTestAddr = NULL;
return retVal;
}
volatile uint32_t regValue2;
uint32_t firstBitLocation, secondBitLocation;
uint32_t errAddrOffset;
+ CSL_Ecc_AggrEDCInterconnectErrorInfo eccErrInjInfo;
CSL_ecc_aggrRegs *eccAggrRegs;
- uint32_t ramId;
+ uint32_t ramId, ramIdType;
SDR_Result retVal = SDR_PASS;
int32_t cslRetval;
SDR_MemConfig_t memConfig;
}
if (retVal == SDR_PASS) {
-
- eccAggrRegs = (SDR_ECC_aggrBaseAddressTable[eccMemType]);
-
- /* Get Ram Id */
- retVal = SDR_ECC_getRamId(eccMemType, memSubType,
- &ramId);
+ /* Based on ECC MemType (i.e. which aggregator), find the appropriate base address
+ * for that ECC Aggegator. */
+ retVal = SDR_ECC_getAggrBaseAddr(eccMemType, &eccAggrRegs);
}
if (retVal == SDR_PASS) {
- /* Get memory configuration */
- retVal = SDR_ECC_getMemConfig(eccMemType, memSubType, &memConfig);
+ /* Get Ram Id */
+ retVal = SDR_ECC_getRamId(eccMemType, memSubType,
+ &ramId, &ramIdType);
}
- if (retVal == SDR_PASS) {
- if ( ((uintptr_t)pECCErrorConfig->pErrMem) < memConfig.memStartAddr) {
- retVal = SDR_FAIL;
- } else {
- /* Calculate error offset */
- errAddrOffset = ((uintptr_t)pECCErrorConfig->pErrMem - memConfig.memStartAddr)
- / (memConfig.stride);
+ if (ramIdType == SDR_ECC_RAM_ID_TYPE_WRAPPER) {
+ if (retVal == SDR_PASS) {
+ /* Get memory configuration */
+ retVal = SDR_ECC_getMemConfig(eccMemType, memSubType, &memConfig);
}
- }
- if (retVal == SDR_PASS) {
- /* Set error Address */
- cslRetval = CSL_ecc_aggrWriteEccRamErrCtrlReg(eccAggrRegs,
- ramId, 0u,
- errAddrOffset);
- if (cslRetval != CSL_PASS) {
- retVal = SDR_FAIL;
+ if (retVal == SDR_PASS) {
+ if ( ((uintptr_t)pECCErrorConfig->pErrMem) < memConfig.memStartAddr) {
+ retVal = SDR_FAIL;
+ } else {
+ /* Calculate error offset */
+ errAddrOffset = ((uintptr_t)pECCErrorConfig->pErrMem - memConfig.memStartAddr)
+ / (memConfig.stride);
+ }
}
- }
- if (retVal == SDR_PASS) {
+ if (retVal == SDR_PASS) {
+ /* Set error Address in ECC Wrapper RAM ID */
+ cslRetval = CSL_ecc_aggrWriteEccRamErrCtrlReg(eccAggrRegs,
+ ramId, 0u,
+ errAddrOffset);
+ if (cslRetval != CSL_PASS) {
+ retVal = SDR_FAIL;
+ }
+ }
- /* Read ECC Ram Control Register */
- cslRetval = CSL_ecc_aggrReadEccRamCtrlReg(eccAggrRegs,
- ramId, ®Value);
- if (cslRetval != CSL_PASS) {
- retVal = SDR_FAIL;
+ if (retVal == SDR_PASS) {
+ /* Read ECC Ram Control Register */
+ cslRetval = CSL_ecc_aggrReadEccRamCtrlReg(eccAggrRegs,
+ ramId, ®Value);
+ if (cslRetval != CSL_PASS) {
+ retVal = SDR_FAIL;
+ }
}
- }
- if (retVal == SDR_PASS) {
+ if (retVal == SDR_PASS) {
- switch (errorType) {
- case SDR_INJECT_ECC_ERROR_FORCING_1BIT_ONCE:
- case SDR_INJECT_ECC_ERROR_FORCING_1BIT_REPEAT:
- case SDR_INJECT_ECC_ERROR_FORCING_1BIT_N_ROW_ONCE:
- case SDR_INJECT_ECC_ERROR_FORCING_1BIT_N_ROW_REPEAT:
- /* Get bit location */
- retVal = SDR_ECC_getBitLocation(pECCErrorConfig->flipBitMask,
- 0u, &firstBitLocation);
- if (retVal != SDR_PASS) {
- break;
- }
+ switch (errorType) {
+ case SDR_INJECT_ECC_ERROR_FORCING_1BIT_ONCE:
+ case SDR_INJECT_ECC_ERROR_FORCING_1BIT_REPEAT:
+ case SDR_INJECT_ECC_ERROR_FORCING_1BIT_N_ROW_ONCE:
+ case SDR_INJECT_ECC_ERROR_FORCING_1BIT_N_ROW_REPEAT:
+ /* Get bit location */
+ retVal = SDR_ECC_getBitLocation(pECCErrorConfig->flipBitMask,
+ 0u, &firstBitLocation);
+ if (retVal != SDR_PASS) {
+ break;
+ }
- /* Write bit error configuration for single bit */
- cslRetval = CSL_ecc_aggrWriteEccRamErrCtrlReg(eccAggrRegs,
- ramId, 1, firstBitLocation);
- if (cslRetval != CSL_PASS) {
- retVal = SDR_FAIL;
+ /* Write bit error configuration for single bit */
+ cslRetval = CSL_ecc_aggrWriteEccRamErrCtrlReg(eccAggrRegs,
+ ramId, 1, firstBitLocation);
+ if (cslRetval != CSL_PASS) {
+ retVal = SDR_FAIL;
+ break;
+ }
+
+ if ((errorType == SDR_INJECT_ECC_ERROR_FORCING_1BIT_ONCE) ||
+ (errorType == SDR_INJECT_ECC_ERROR_FORCING_1BIT_N_ROW_ONCE)){
+ /* Configure settings for inject error once */
+ regValue |= CSL_ECC_RAM_CTRL_ERROR_ONCE_MASK;
+ } else {
+ /* Configure settings for inject error repeat */
+ regValue = (regValue & (~CSL_ECC_RAM_CTRL_ERROR_ONCE_MASK));
+ }
+ if ((errorType == SDR_INJECT_ECC_ERROR_FORCING_1BIT_ONCE) ||
+ (errorType == SDR_INJECT_ECC_ERROR_FORCING_1BIT_REPEAT)){
+ /* Configure settings for single bit error, specific row */
+ regValue = (regValue
+ & (~(CSL_ECC_RAM_CTRL_FORCE_N_ROW_MASK | CSL_ECC_RAM_CTRL_FORCE_DED_MASK)))
+ | CSL_ECC_RAM_CTRL_FORCE_SEC_MASK;
+ } else {
+ /* Configure settings for Single bit error N Row */
+ regValue = (regValue
+ & (~CSL_ECC_RAM_CTRL_FORCE_DED_MASK))
+ | CSL_ECC_RAM_CTRL_FORCE_SEC_MASK
+ | CSL_ECC_RAM_CTRL_FORCE_N_ROW_MASK;
+ }
break;
- }
- if ((errorType == SDR_INJECT_ECC_ERROR_FORCING_1BIT_ONCE) ||
- (errorType == SDR_INJECT_ECC_ERROR_FORCING_1BIT_N_ROW_ONCE)){
- /* Configure settings for inject error once */
- regValue |= CSL_ECC_RAM_CTRL_ERROR_ONCE_MASK;
- } else {
- /* Configure settings for inject error repeat */
- regValue = (regValue & (~CSL_ECC_RAM_CTRL_ERROR_ONCE_MASK));
- }
- if ((errorType == SDR_INJECT_ECC_ERROR_FORCING_1BIT_ONCE) ||
- (errorType == SDR_INJECT_ECC_ERROR_FORCING_1BIT_REPEAT)){
- /* Configure settings for single bit error, specific row */
- regValue = (regValue
- & (~(CSL_ECC_RAM_CTRL_FORCE_N_ROW_MASK | CSL_ECC_RAM_CTRL_FORCE_DED_MASK)))
- | CSL_ECC_RAM_CTRL_FORCE_SEC_MASK;
- } else {
- /* Configure settings for Single bit error N Row */
- regValue = (regValue
- & (~CSL_ECC_RAM_CTRL_FORCE_DED_MASK))
- | CSL_ECC_RAM_CTRL_FORCE_SEC_MASK
- | CSL_ECC_RAM_CTRL_FORCE_N_ROW_MASK;
- }
- break;
- case SDR_INJECT_ECC_ERROR_FORCING_2BIT_ONCE:
- case SDR_INJECT_ECC_ERROR_FORCING_2BIT_REPEAT:
- case SDR_INJECT_ECC_ERROR_FORCING_2BIT_N_ROW_ONCE:
- case SDR_INJECT_ECC_ERROR_FORCING_2BIT_N_ROW_REPEAT:
- /* Get bit location */
- retVal = SDR_ECC_getBitLocation(pECCErrorConfig->flipBitMask,
- 0, &firstBitLocation);
- if (retVal != SDR_PASS) {
+ case SDR_INJECT_ECC_ERROR_FORCING_2BIT_ONCE:
+ case SDR_INJECT_ECC_ERROR_FORCING_2BIT_REPEAT:
+ case SDR_INJECT_ECC_ERROR_FORCING_2BIT_N_ROW_ONCE:
+ case SDR_INJECT_ECC_ERROR_FORCING_2BIT_N_ROW_REPEAT:
+ /* Get bit location */
+ retVal = SDR_ECC_getBitLocation(pECCErrorConfig->flipBitMask,
+ 0, &firstBitLocation);
+ if (retVal != SDR_PASS) {
+ break;
+ }
+
+ /* Get Second bit location */
+ retVal = SDR_ECC_getBitLocation(pECCErrorConfig->flipBitMask,
+ firstBitLocation+1u, &secondBitLocation);
+ if (retVal != SDR_PASS) {
+ break;
+ }
+
+ /* Record double bit error position */
+ regValue2 = firstBitLocation | (secondBitLocation << 16);
+
+ /* Set bit error configuration settings to register */
+ cslRetval = CSL_ecc_aggrWriteEccRamErrCtrlReg(eccAggrRegs,
+ ramId, 1, regValue2);
+ if (cslRetval != CSL_PASS) {
+ retVal = SDR_FAIL;
+ break;
+ }
+
+ if ((errorType == SDR_INJECT_ECC_ERROR_FORCING_2BIT_ONCE) ||
+ (errorType == SDR_INJECT_ECC_ERROR_FORCING_2BIT_N_ROW_ONCE)){
+ /* Configure settings for Double bit error */
+ regValue |= CSL_ECC_RAM_CTRL_ERROR_ONCE_MASK;
+ } else {
+ /* Configure settings for single bit error */
+ regValue = (regValue & (~CSL_ECC_RAM_CTRL_ERROR_ONCE_MASK));
+ }
+
+ if ((errorType == SDR_INJECT_ECC_ERROR_FORCING_2BIT_ONCE) ||
+ (errorType == SDR_INJECT_ECC_ERROR_FORCING_2BIT_REPEAT)) {
+ /* Configure settings for double bit error, specific row */
+ regValue = (regValue
+ & (~(CSL_ECC_RAM_CTRL_FORCE_N_ROW_MASK+CSL_ECC_RAM_CTRL_FORCE_SEC_MASK)))
+ | CSL_ECC_RAM_CTRL_FORCE_DED_MASK;
+ } else {
+ /* Configure settings for Double bit error N Row*/
+ regValue = (regValue
+ & (~CSL_ECC_RAM_CTRL_FORCE_SEC_MASK))
+ | CSL_ECC_RAM_CTRL_FORCE_DED_MASK
+ | CSL_ECC_RAM_CTRL_FORCE_N_ROW_MASK;
+ }
break;
- }
- /* Get Second bit location */
- retVal = SDR_ECC_getBitLocation(pECCErrorConfig->flipBitMask,
- firstBitLocation+1u, &secondBitLocation);
- if (retVal != SDR_PASS) {
+ default:
break;
- }
+ }
+ }
- /* Record double bit error position */
- regValue2 = firstBitLocation | (secondBitLocation << 16);
+ if (retVal == SDR_PASS) {
+ /* Write bit error configuration to register */
+ cslRetval = CSL_ecc_aggrWriteEccRamCtrlReg(eccAggrRegs,
+ ramId, regValue);
+ if (cslRetval != CSL_PASS) {
+ retVal = SDR_FAIL;
+ }
+ }
- /* Set bit error configuration settings to register */
- cslRetval = CSL_ecc_aggrWriteEccRamErrCtrlReg(eccAggrRegs,
- ramId, 1, regValue2);
- if (cslRetval != CSL_PASS) {
- retVal = SDR_FAIL;
- break;
- }
- if ((errorType == SDR_INJECT_ECC_ERROR_FORCING_2BIT_ONCE) ||
- (errorType == SDR_INJECT_ECC_ERROR_FORCING_2BIT_N_ROW_ONCE)){
- /* Configure settings for Double bit error */
- regValue |= CSL_ECC_RAM_CTRL_ERROR_ONCE_MASK;
- } else {
- /* Configure settings for single bit error */
- regValue = (regValue & (~CSL_ECC_RAM_CTRL_ERROR_ONCE_MASK));
- }
- if ((errorType == SDR_INJECT_ECC_ERROR_FORCING_2BIT_ONCE) ||
- (errorType == SDR_INJECT_ECC_ERROR_FORCING_2BIT_REPEAT)) {
- /* Configure settings for double bit error, specific row */
- regValue = (regValue
- & (~(CSL_ECC_RAM_CTRL_FORCE_N_ROW_MASK+CSL_ECC_RAM_CTRL_FORCE_SEC_MASK)))
- | CSL_ECC_RAM_CTRL_FORCE_DED_MASK;
- } else {
- /* Configure settings for Double bit error N Row*/
- regValue = (regValue
- & (~CSL_ECC_RAM_CTRL_FORCE_SEC_MASK))
- | CSL_ECC_RAM_CTRL_FORCE_DED_MASK
- | CSL_ECC_RAM_CTRL_FORCE_N_ROW_MASK;
- }
- break;
+ if (retVal == SDR_PASS) {
+ /* Just read back ctrl register to confirm write */
+ /* NOTE: The read value may not be same as what is written as some fields
+ * in the register are not writable or can self clear
+ */
+ cslRetval = CSL_ecc_aggrReadEccRamCtrlReg(eccAggrRegs,
+ ramId,
+ (uint32_t *)(®Value2));
+ if (cslRetval != CSL_PASS) {
+ retVal = SDR_FAIL;
+ }
+ }
+ } /* if (ramIdType == SDR_ECC_RAM_ID_TYPE_WRAPPER) {*/
+ else if (ramIdType == SDR_ECC_RAM_ID_TYPE_INTERCONNECT) {
+ eccErrInjInfo.eccGroup = pECCErrorConfig->chkGrp;
+ // TODO - NEED TO LOOK UP IN RAM ID's GROUP CHECKER TABLE WHAT WIDTH AND TYPE IS BEING CHOSEN, and THEN LATER AFTER getBitLocation() make sure it is not wider than the WIDTH
+ // USE SINGLE ERROR WITH PARITY - when inserting with single bit, we expect to get a double bit error
+ eccErrInjInfo.bNextBit = FALSE;
+ eccErrInjInfo.eccPattern = 2U;
- default:
- break;
- }
- }
+ switch (errorType) {
+ case SDR_INJECT_ECC_ERROR_FORCING_1BIT_ONCE:
+ /* Get bit location */
+ retVal = SDR_ECC_getBitLocation(pECCErrorConfig->flipBitMask,
+ 0u, &firstBitLocation);
+ if (retVal != SDR_PASS) {
+ break;
+ }
+ eccErrInjInfo.eccBit1 = firstBitLocation;
+ eccErrInjInfo.eccBit2 = 0u;
+ eccErrInjInfo.intrSrc = CSL_ECC_AGGR_INTR_SRC_SINGLE_BIT;
+ break;
+
+ case SDR_INJECT_ECC_ERROR_FORCING_2BIT_ONCE:
+ /* Get bit location */
+ retVal = SDR_ECC_getBitLocation(pECCErrorConfig->flipBitMask,
+ 0u, &firstBitLocation);
+ if (retVal != SDR_PASS) {
+ break;
+ }
+ eccErrInjInfo.eccBit1 = firstBitLocation;
- if (retVal == SDR_PASS) {
- /* Write bit error configuration to register */
- cslRetval = CSL_ecc_aggrWriteEccRamCtrlReg(eccAggrRegs,
- ramId, regValue);
- if (cslRetval != CSL_PASS) {
- retVal = SDR_FAIL;
+ /* Get Second bit location */
+ retVal = SDR_ECC_getBitLocation(pECCErrorConfig->flipBitMask,
+ firstBitLocation+1u, &secondBitLocation);
+ if (retVal != SDR_PASS) {
+ break;
+ }
+ eccErrInjInfo.eccBit2 = secondBitLocation;
+ eccErrInjInfo.intrSrc = CSL_ECC_AGGR_INTR_SRC_DOUBLE_BIT;
+ break;
+
+ default:
+ retVal = SDR_FAIL;
+ break;
}
- }
- if (retVal == SDR_PASS) {
- /* Just read back ctrl register to confirm write */
- /* NOTE: The read value may not be same as what is written as some fields
- * in the register are not writable or can self clear
- */
- cslRetval = CSL_ecc_aggrReadEccRamCtrlReg(eccAggrRegs,
- ramId,
- (uint32_t *)(®Value2));
- if (cslRetval != CSL_PASS) {
- retVal = SDR_FAIL;
+ if (retVal == SDR_PASS) {
+
+ cslRetval = CSL_ecc_aggrForceEDCInterconnectError(eccAggrRegs,
+ ramId,
+ &eccErrInjInfo);
+ if (cslRetval != CSL_PASS) {
+ retVal = SDR_FAIL;
+ }
}
- }
+ } /* else if (ramIdType == SDR_ECC_RAM_ID_TYPE_INTERCONNECT) { */
return retVal;
}
* \param1 eccMemType: Memory type for self test
* \param2 memSubType: Memory subtype for self test
* \param3 pRAMId: pointer to return Ram Id
+ * \param4 pRAMIdType: pointer to return Ram Id Type
*
* @return SDR_PASS : Success; SDR_FAIL for failures
*/
static SDR_Result SDR_ECC_getRamId(SDR_ECC_MemType eccMemType, SDR_ECC_MemSubType memSubType,
- uint32_t *pRAMId)
+ uint32_t *pRAMId, uint32_t *pRAMIdType)
{
SDR_Result retVal = SDR_PASS;
retVal = SDR_ECC_checkMemoryType(eccMemType, memSubType);
if (retVal == SDR_PASS) {
- if (eccMemType == SDR_ECC_MEMTYPE_MCU_R5F0_CORE) {
-
- /* Get ram Id from table */
- *pRAMId = SDR_ECC_mcuArmssRamIdTable[memSubType].RAMId;
-
- /* To support other ecc aggregator instances,
- * need to add switch cases here
- */
- } else {
- retVal = SDR_FAIL;
+ /* Get ram Id from table for the particular aggregator */
+ switch (eccMemType) {
+ case SDR_ECC_MEMTYPE_MCU_R5F0_CORE:
+ *pRAMId = SDR_ECC_mcuArmssRamIdTable[memSubType].RAMId;
+ *pRAMIdType = SDR_ECC_mcuArmssRamIdTable[memSubType].ramIdType;
+ break;
+
+#ifdef SOC_J721E
+ case SDR_ECC_MEMTYPE_MAIN_MSMC_AGGR0:
+ *pRAMId = SDR_ECC_mainMsmcAggr0RamIdTable[memSubType].RAMId;
+ *pRAMIdType = SDR_ECC_mainMsmcAggr0RamIdTable[memSubType].ramIdType;
+ break;
+
+ case SDR_ECC_MEMTYPE_MCU_CBASS_ECC_AGGR0:
+ *pRAMId = SDR_ECC_mcuEccAggr0RamIdTable[memSubType].RAMId;
+ *pRAMIdType = SDR_ECC_mcuEccAggr0RamIdTable[memSubType].ramIdType;
+ break;
+#endif
+
+ default:
+ retVal = SDR_FAIL;
+ break;
}
}
return retVal;
@@ -911,19 +1313,41 @@ static SDR_Result SDR_ECC_checkMemoryType(SDR_ECC_MemType eccMemType, SDR_ECC_Me
{
SDR_Result retVal = SDR_PASS;
- if (eccMemType == SDR_ECC_MEMTYPE_MCU_R5F0_CORE) {
- /* Do bound check */
- if (((uint32_t)memSubType)
- >= ((uint32_t)(sizeof(SDR_ECC_mcuArmssRamIdTable)/sizeof(SDR_ECC_mcuArmssRamIdTable[0])))) {
- retVal = SDR_FAIL;
- }
+ switch (eccMemType) {
+ case SDR_ECC_MEMTYPE_MCU_R5F0_CORE:
+ /* Do bound check */
+ if (((uint32_t)memSubType)
+ >= ((uint32_t)(sizeof(SDR_ECC_mcuArmssRamIdTable) /
+ sizeof(SDR_ECC_mcuArmssRamIdTable[0])))) {
+ retVal = SDR_FAIL;
+ }
+ break;
- /* To support other ecc aggregator instances,
- * need to add switch cases here
- */
- } else {
- retVal = SDR_FAIL;
+#ifdef SOC_J721E
+ case SDR_ECC_MEMTYPE_MAIN_MSMC_AGGR0:
+ /* Do bound check */
+ if (((uint32_t)memSubType)
+ >= ((uint32_t)(sizeof(SDR_ECC_mainMsmcAggr0RamIdTable) /
+ sizeof(SDR_ECC_mainMsmcAggr0RamIdTable[0])))) {
+ retVal = SDR_FAIL;
+ }
+ break;
+
+ case SDR_ECC_MEMTYPE_MCU_CBASS_ECC_AGGR0:
+ /* Do bound check */
+ if (((uint32_t)memSubType)
+ >= ((uint32_t)(sizeof(SDR_ECC_mcuEccAggr0RamIdTable) /
+ sizeof(SDR_ECC_mcuEccAggr0RamIdTable[0])))) {
+ retVal = SDR_FAIL;
+ }
+ break;
+#endif
+
+ default:
+ retVal = SDR_FAIL;
+ break;
}
+
return retVal;
}
@@ -938,22 +1362,90 @@ static SDR_Result SDR_ECC_checkMemoryType(SDR_ECC_MemType eccMemType, SDR_ECC_Me
*
* @return SDR_PASS : Success; SDR_FAIL for failures
*/
-static SDR_Result SDR_ECC_getAggregatorType(SDR_ECC_MemType eccMemType, SDR_ECC_MemSubType memSubType,
- bool *pIinjectOnly)
+static SDR_Result SDR_ECC_getAggregatorType(SDR_ECC_MemType eccMemType,
+ SDR_ECC_MemSubType memSubType,
+ uint32_t *pIinjectOnly)
{
SDR_Result retVal = SDR_PASS;
retVal = SDR_ECC_checkMemoryType(eccMemType, memSubType);
if (retVal == SDR_PASS) {
- if (eccMemType == SDR_ECC_MEMTYPE_MCU_R5F0_CORE) {
- /* Get ram Id from table */
- *pIinjectOnly = SDR_ECC_mcuArmssRamIdTable[memSubType].aggregatorTypeInjectOnly;
+ switch (eccMemType) {
+ case SDR_ECC_MEMTYPE_MCU_R5F0_CORE:
+ *pIinjectOnly = SDR_ECC_mcuArmssRamIdTable[memSubType].aggregatorTypeInjectOnly;
+ break;
+
+#ifdef SOC_J721E
+ case SDR_ECC_MEMTYPE_MAIN_MSMC_AGGR0:
+ *pIinjectOnly = SDR_ECC_mainMsmcAggr0RamIdTable[memSubType].aggregatorTypeInjectOnly;
+ break;
+
+ case SDR_ECC_MEMTYPE_MCU_CBASS_ECC_AGGR0:
+ *pIinjectOnly = SDR_ECC_mcuEccAggr0RamIdTable[memSubType].aggregatorTypeInjectOnly;
+ break;
+#endif
+
+ default:
+ retVal = SDR_FAIL;
+ break;
+ }
+ }
+
+ return retVal;
+}
+
+/** ============================================================================
+ *
+ * \brief Get ECC memory configuration for given memory subtype (only valid for
+ * Wrapper RAM ID's).
+ *
+ * \param1 memSubType: Memory subtype for which we are searching for memory
+ * configuration
+ * \param2 memEntryTable: Memory configuration table for all Wrapper RAM ID's
+ * for a particular memType (i.e. ECC aggregator).
+ * \param3 tableSize: Size of the memory configuration table to search
+
+ * \param4 pMemConfig: pointer to memory configuration structure that will be
+ * filled upon successful retrieval.
+ *
+ * @return SDR_PASS : Success; SDR_FAIL for failures
+ */
+static SDR_Result SDR_ECC_searchMemEntryTable(SDR_ECC_MemSubType memSubType,
+ const SDR_MemConfig_t memEntryTable[],
+ uint32_t tableSize,
+ SDR_MemConfig_t *pMemConfig)
+{
+ SDR_Result retVal = SDR_FAIL;
+ uint32_t length = tableSize;
+ uint32_t first, last, middle;
+
+ /* Binary search, as the assumption is that memSubTypes in table are
+ * in order */
+ first = 0;
+ last = length - 1;
+ middle = (first + last) / 2;
+
+ while (first <= last) {
+ if (memEntryTable[middle].memSubType < memSubType) {
+ first = middle + 1;
+ } else if (memEntryTable[middle].memSubType == memSubType) {
+ /* Fill the memory configuration structure */
+ *pMemConfig = memEntryTable[middle];
+ retVal = SDR_PASS;
+ break;
} else {
- retVal = SDR_FAIL;
+ last = middle - 1;
}
+
+ middle = (first + last) / 2;
}
+ if (first > last) {
+ retVal = SDR_FAIL;
+ }
+
return retVal;
}
+
/** ============================================================================
*
* \brief Get Ram Id for given memory and memory subtype
@@ -968,13 +1460,36 @@ static SDR_Result SDR_ECC_getMemConfig(SDR_ECC_MemType eccMemType, SDR_ECC_MemSu
SDR_MemConfig_t *pMemConfig)
{
SDR_Result retVal = SDR_PASS;
+ uint32_t tableSize;
retVal = SDR_ECC_checkMemoryType(eccMemType, memSubType);
if (retVal == SDR_PASS) {
+ /* Get memory configuration from table */
if (eccMemType == SDR_ECC_MEMTYPE_MCU_R5F0_CORE) {
- /* Get memory configuration from table */
- *pMemConfig = SDR_ECC_mcuArmssMemEntries[memSubType];
+ tableSize = sizeof(SDR_ECC_mcuArmssMemEntries) /
+ sizeof(SDR_ECC_mcuArmssMemEntries[0]);
+ retVal = SDR_ECC_searchMemEntryTable(memSubType,
+ SDR_ECC_mcuArmssMemEntries,
+ tableSize,
+ pMemConfig);
+#ifdef SOC_J721E
+ } else if (eccMemType == SDR_ECC_MEMTYPE_MAIN_MSMC_AGGR0) {
+ tableSize = sizeof(SDR_ECC_mainMsmcAggr0MemEntries) /
+ sizeof(SDR_ECC_mainMsmcAggr0MemEntries[0]);
+ retVal = SDR_ECC_searchMemEntryTable(memSubType,
+ SDR_ECC_mainMsmcAggr0MemEntries,
+ tableSize,
+ pMemConfig);
+
+ } else if (eccMemType == SDR_ECC_MEMTYPE_MCU_CBASS_ECC_AGGR0) {
+ tableSize = sizeof(SDR_ECC_MCUCBASSMemEntries) /
+ sizeof(SDR_ECC_MCUCBASSMemEntries[0]);
+ retVal = SDR_ECC_searchMemEntryTable(memSubType,
+ SDR_ECC_MCUCBASSMemEntries,
+ tableSize,
+ pMemConfig);
+#endif
} else {
retVal = SDR_FAIL;
}
@@ -982,3 +1497,34 @@ static SDR_Result SDR_ECC_getMemConfig(SDR_ECC_MemType eccMemType, SDR_ECC_MemSu
return retVal;
}
+
+/** ============================================================================
+ *
+ * \brief Get Ecc Aggregator Base Address for given memory type
+ *
+ * \param1 eccMemType: Memory type for self test
+ * \param2 pEccAggr: pointer to Ecc Aggregator address
+ *
+ * @return SDR_PASS : Success; SDR_FAIL for failures
+ */
+static SDR_Result SDR_ECC_getAggrBaseAddr(SDR_ECC_MemType eccMemType, CSL_ecc_aggrRegs **pEccAggr)
+{
+ SDR_Result retVal = SDR_PASS;
+
+ if ((eccMemType == SDR_ECC_MEMTYPE_MCU_R5F0_CORE)
+ || (eccMemType == SDR_ECC_MEMTYPE_MCU_CBASS_ECC_AGGR0)){
+ /* Note in the SDR_ECC_aggrBaseAddressTable only the above are
+ * supported currently
+ */
+ *pEccAggr = SDR_ECC_aggrBaseAddressTable[eccMemType];
+#ifdef SOC_J721E
+ } else if (eccMemType >= SDR_ECC_MEMTYPE_MAIN_MSMC_AGGR0) {
+ *pEccAggr = SDR_ECC_aggrHighBaseAddressTableTrans[eccMemType - \
+ SDR_ECC_MEMTYPE_MAIN_MSMC_AGGR0];
+#endif
+ } else {
+ retVal = SDR_FAIL;
+ }
+
+ return retVal;
+}
index c7c9ce85cc7af28ae14a4f8821aca71af86890ef..149e3b48f0678c81ff707db717164bc4f183b0e3 100644 (file)
{
uint32_t RAMId;
/**< Unique Ram Identifier */
- bool aggregatorTypeInjectOnly;
+ uint32_t aggregatorTypeInjectOnly;
/**< Variable to track if the ECC aggregator configuration
* is only inject only or a full fledged ecc aggregator
- * including tracking of error status */
+ * including tracking of error status
+ * A value of 1 represents "Inject Only", and a value of
+ * 0 represents "Inject with Error Capture" */
+ uint32_t ramIdType;
+ /**< Variable to track if the RAM ID is interconnect type (1)
+ * or wrapper type (0) */
} SDR_RAMIdEntry_t;
/** ---------------------------------------------------------------------------
*/
typedef struct SDR_MemConfig_s
{
+ SDR_ECC_MemSubType memSubType;
+ /**< Memory subtype - used to index/search for these memory configs */
uintptr_t memStartAddr;
/**< Memory start address */
uint32_t size;
/**< Size of memory in bytes */
uint32_t stride;
/**< Stride of memory in bytes */
+ uint32_t rowSize;
+ /**< Size of each row in the memory in number of bits */
bool readable;
/**< Memory section whether it is directly readable */
} SDR_MemConfig_t;
+/** ---------------------------------------------------------------------------
+ * \brief This structure defines the elements of ECC Group checker for Interconnect
+ * SDR_ECC_RamIdType
+ * ----------------------------------------------------------------------------
+ */
+typedef struct SDR_GrpChkConfig_s
+{
+ SDR_ECC_GrpChkType grpChkType;
+ /**< Group Checker type */
+ uint32_t stride;
+ /**< Stride of memory bus in bits */
+ uint32_t dataWidth;
+ /**< Length of memory bus covered in bits */
+} SDR_GrpChkConfig_t;
+
#endif /* INCLUDE_SDR_ECC_PRIV_H_ */
diff --git a/packages/ti/diag/sdr/test/sdtf-test/build/r5f/linker_r5.lds b/packages/ti/diag/sdr/test/sdtf-test/build/r5f/am65xx/linker_r5.lds
similarity index 100%
rename from packages/ti/diag/sdr/test/sdtf-test/build/r5f/linker_r5.lds
rename to packages/ti/diag/sdr/test/sdtf-test/build/r5f/am65xx/linker_r5.lds
rename from packages/ti/diag/sdr/test/sdtf-test/build/r5f/linker_r5.lds
rename to packages/ti/diag/sdr/test/sdtf-test/build/r5f/am65xx/linker_r5.lds
diff --git a/packages/ti/diag/sdr/test/sdtf-test/build/r5f/j721e/linker_r5.lds b/packages/ti/diag/sdr/test/sdtf-test/build/r5f/j721e/linker_r5.lds
--- /dev/null
@@ -0,0 +1,206 @@
+/*
+ * SDR TEST
+ *
+ * Software Diagnostics Reference Test
+ *
+ * Copyright (c) Texas Instruments Incorporated 2018-2020
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/*----------------------------------------------------------------------------*/
+/* File: linker_r5.lds */
+/* Description: */
+/* Link command file for AM65XX M4 MCU 0 view */
+/*----------------------------------------------------------------------------*/
+/* Linker Settings */
+/* Standard linker options */
+--retain="*(.intvecs)"
+--retain="*(.intc_text)"
+--retain="*(.rstvectors)"
+--retain="*(.irqStack)"
+--retain="*(.fiqStack)"
+--retain="*(.abortStack)"
+--retain="*(.undStack)"
+--retain="*(.svcStack)"
+--fill_value=0
+--stack_size=0x2000
+--heap_size=0x1000
+--entry_point=_resetvectors /* Default C RTS boot.asm */
+
+-stack 0x2000 /* SOFTWARE STACK SIZE */
+-heap 0x2000 /* HEAP AREA SIZE */
+
+/* Stack Sizes for various modes */
+__IRQ_STACK_SIZE = 0x1000;
+__FIQ_STACK_SIZE = 0x1000;
+__ABORT_STACK_SIZE = 0x1000;
+__UND_STACK_SIZE = 0x1000;
+__SVC_STACK_SIZE = 0x1000;
+
+/*----------------------------------------------------------------------------*/
+/* Memory Map */
+MEMORY
+{
+ VECTORS (X) : origin=0x41C7F000 length=0x1000
+ /* Reset Vectors base address(RESET_VECTORS) should be 64 bytes aligned */
+ RESET_VECTORS (X) : origin=0x41C00000 length=0x100
+ /* MCU0_R5F_0 local view */
+ MCU0_R5F_TCMA (X) : origin=0x0 length=0x7c00 fill=0xffffffff
+ MCU0_R5F_TCMA_TEST (X) : origin=0x7c00 length=0x400 fill=0xffffffff
+ MCU0_R5F_TCMB0 (RWIX) : origin=0x41010000 length=0x8000
+
+ /* MCU0_R5F_1 SoC view */
+ MCU0_R5F1_ATCM (RWIX) : origin=0x41400000 length=0x8000
+ MCU0_R5F1_BTCM (RWIX) : origin=0x41410000 length=0x8000
+
+ /* MCU0 memory used for SBL and SYSFW. Avaiable after boot for appi starts for dynamic use */
+ SBL_RESERVED (RWIX) : origin=0x41C00100 length=0x60000 - 0x100 /* ~383KB */
+
+ /* MCU0 share locations */
+ OCMRAM (RWIX) : origin=0x41C60000 length=0x20000 - 0x2000 /* ~124KB */
+
+ /* MCU0 Location RESERVED for SDR RAT Self Test */
+ SDR_OCMC_RAT_SELFTEST (R) : origin=0x41C7EFC0 length=32
+
+ /* MCU0 Location RESERVED for SDR MPU Self Test */
+ SDR_OCMC_MPU_SELFTEST (R) : origin=0x41C7EFE0 length=32
+
+ ECC_CFG_SCRATCH (RWIX) : origin=0x60000000 length=0x1000 /* 4 K */
+
+ /* AM65XX M4 locations */
+ MSMC3_SDR (RWIX) : origin=0x70000000 length=0x20000 /* 128 K */
+ MSMC3 (RWIX) : origin=0x70020000 length=0xD0000 /* 840 K */
+ /* Reserved for DMSC */
+ MSMC3_DMSC (RWIX) : origin=0x700F0000 length=0x10000 /* 64K */
+ MSMC3_H (RWIX) : origin=0x70100000 length=0xF2000 /* 1MB -56K */
+ MSMC3_NOCACHE (RWIX) : origin=0x701F2000 length=0xE000 /* 56K */
+ DDR0 (RWIX) : origin=0x80000000 length=0x80000000 /* 2GB */
+
+/* Additional memory settings */
+
+} /* end of MEMORY */
+
+/*----------------------------------------------------------------------------*/
+/* Section Configuration */
+
+SECTIONS
+{
+/* 'intvecs' and 'intc_text' sections shall be placed within */
+/* a range of +\- 16 MB */
+ .intvecs : {} palign(8) > VECTORS
+ .intc_text : {} palign(8) > VECTORS
+ .rstvectors : {} palign(8) > MCU0_R5F_TCMA
+ .sdr_text_esm align(8) : {
+ sdr.*<sdr_esm.o*> (.text)
+ } > MSMC3_SDR
+ .sdr_text_ecc align(8) : {
+ sdr.*<sdr_ecc.o*> (.text)
+ } > MSMC3_SDR
+ .sdr_text_ccm align(8) : {
+ sdr.*<sdr_ccm.o*> (.text)
+ } > MSMC3_SDR
+ .sdr_text_crc align(8) : {
+ sdr.*<sdr_crc.o*> (.text)
+ } > MSMC3_SDR
+ .sdr_text_mpu align(8) : {
+ sdr.*<sdr_mpu.o*> (.text)
+ } > MSMC3_SDR
+ .sdr_text_wdt align(8) : {
+ sdr.*<sdr_wdt.o*> (.text)
+ } > MSMC3_SDR
+ .sdr__esm align(8) : {
+ } > MSMC3_SDR
+ .sdr_data_ecc align(8) : {
+ sdr.*<sdr_ecc.o*> (.const)
+ } > MSMC3_SDR
+ .sdr_data_mpu align(8) : {
+ sdr.*<sdr_mpu*> (.const)
+ } > MSMC3_SDR
+ .sdr_bss_ecc align(8) : {
+ sdr.*<sdr_ecc.o*> (.bss)
+ } > MSMC3_SDR
+ .sdr_bss_ccm align(8) : {
+ sdr.*<sdr_ccm.o*> (.bss)
+ } > MSMC3_SDR
+ .sdr_bss_crc align(8) : {
+ sdr.*<sdr_crc.o*> (.bss)
+ } > MSMC3_SDR
+ .sdr_bss_mpu align(8) : {
+ sdr.*<sdr_mpu.o*> (.bss)
+ } > MSMC3_SDR
+ .sdr_bss_wdt align(8) : {
+ sdr.*<sdr_wdt.o*> (.bss)
+ } > MSMC3_SDR
+ .sdr_bss_exception align(8) : {
+ sdr.*<sdr_exception*> (.bss)
+ } > MSMC3_SDR
+
+ .bootCode : {} palign(8) > MSMC3
+ .startupCode: {} palign(8) > MSMC3
+ .text : {} palign(8) > MSMC3
+ .const : {} palign(8) > MSMC3
+ .cinit : {} palign(8) > MSMC3
+ .pinit : {} palign(8) > MSMC3
+ .bss : {} align(4) > MSMC3
+ .data : {} palign(128) > MSMC3
+ .my_aggr_reg : {*(.my_aggr_reg)} > ECC_CFG_SCRATCH, type = NOINIT
+ .boardcfg_data : {} palign(128) > MSMC3
+ .sysmem : {} > MSMC3
+ .bss:extMemCache:ramdisk : {} align (32) > DDR0
+ .stack : {} align(4) > MSMC3 (HIGH)
+ .irqStack : {. = . + __IRQ_STACK_SIZE;} align(4) > MSMC3 (HIGH)
+ RUN_START(__IRQ_STACK_START)
+ RUN_END(__IRQ_STACK_END)
+ .fiqStack : {. = . + __FIQ_STACK_SIZE;} align(4) > MSMC3 (HIGH)
+ RUN_START(__FIQ_STACK_START)
+ RUN_END(__FIQ_STACK_END)
+ .abortStack : {. = . + __ABORT_STACK_SIZE;} align(4) > MSMC3 (HIGH)
+ RUN_START(__ABORT_STACK_START)
+ RUN_END(__ABORT_STACK_END)
+ .undStack : {. = . + __UND_STACK_SIZE;} align(4) > MSMC3 (HIGH)
+ RUN_START(__UND_STACK_START)
+ RUN_END(__UND_STACK_END)
+ .svcStack : {. = . + __SVC_STACK_SIZE;} align(4) > MSMC3 (HIGH)
+ RUN_START(__SVC_STACK_START)
+ RUN_END(__SVC_STACK_END)
+
+/* Additional sections settings */
+ .sdtf_rat_testsection : {} palign(32) > SDR_OCMC_RAT_SELFTEST
+
+ .sdtf_ecc_testcodesection : {} palign(32) > MCU0_R5F_TCMA_TEST
+
+} /* end of SECTIONS */
+
+/*----------------------------------------------------------------------------*/
+/* Misc linker settings */
+
+
+/*-------------------------------- END ---------------------------------------*/
diff --git a/packages/ti/diag/sdr/test/sdtf-test/makefile.mk b/packages/ti/diag/sdr/test/sdtf-test/makefile.mk
index f63c5c0196dd19c5ddc89656bd2fbb46f14c8be4..7122c67fda2ecbc4531f1c7b2ab2618a49cb48e7 100644 (file)
ifeq ($(ISA),$(filter $(ISA), a53, a72))
LNKFLAGS_LOCAL_$(CORE) += --entry Entry
endif
-ifeq ($(SOC),$(filter $(SOC), j721e am65xx))
- EXTERNAL_LNKCMD_FILE_LOCAL = $(PDK_INSTALL_PATH)/ti/diag/sdr/test/sdtf-test/build/r5f/linker_r5.lds
-endif
+
+EXTERNAL_LNKCMD_FILE_LOCAL = $(PDK_INSTALL_PATH)/ti/diag/sdr/test/sdtf-test/build/r5f/$(SOC)/linker_r5.lds
# Common source files and CFLAGS across all platforms and cores
PACKAGE_SRCS_COMMON = . ../ ../../
diff --git a/packages/ti/diag/sdr/test/sdtf-test/src/sdtf_ecc.c b/packages/ti/diag/sdr/test/sdtf-test/src/sdtf_ecc.c
index f7d729fa35a35ff8062c99c71fc452fae35e9dfe..570f9734b28f86ee79b0317e9d5f5bd45d58f61b 100644 (file)
*/
#include <stdint.h>
+#include <string.h>
#include <sdr_ecc.h>
return retVal;
}
+
+
+/*********************************************************************
+ * @fn SDTF_runECC1BitCBASSSelfTest
+ *
+ * @brief Execute ECC Single bit error self test on CBASS ECC aggregator
+ *
+ * @param None
+ *
+ * @return 0 : Success; < 0 for failures
+ */
+int32_t SDTF_runECC1BitCBASSSelfTest(void)
+{
+ SDR_Result result;
+ int32_t retVal=0;
+ uint32_t subType;
+
+ SDR_ECC_InjectErrorConfig_t injectErrorConfig;
+
+ SDTF_printf("\n CBASS Single bit error self test: starting");
+
+ memset(&injectErrorConfig, 0, sizeof(injectErrorConfig));
+
+ SDTF_profileBegin(SDTF_PROFILE_ONESHOT);
+ /* Run one shot test for CBASS 2 bit error */
+ /* Note the address is relative to start of ram */
+ injectErrorConfig.pErrMem = (uint32_t *)(0u);
+
+ injectErrorConfig.flipBitMask = 0x1;
+ injectErrorConfig.chkGrp = 0x0;
+ subType = SDR_ECC_MCU_CBASS_MEM_SUBTYPE_EDC_CTRL_ID;
+
+ result = SDR_ECC_selfTest(SDR_ECC_MEMTYPE_MCU_CBASS_ECC_AGGR0,
+ subType,
+ SDR_INJECT_ECC_ERROR_FORCING_1BIT_ONCE,
+ &injectErrorConfig,
+ 1000);
+
+ SDTF_profileEnd(SDTF_PROFILE_ONESHOT);
+
+ if (result != SDR_PASS ) {
+ SDTF_printf("\n CBASS Single bit error self test: Subtype %d: test failed",
+ subType);
+ retVal = -1;
+ } else {
+ SDTF_printf("\n CBASS Single bit error self test: Subtype 0x%p test complete",
+ subType);
+ SDTF_printf("\n Cycles taken %u", SDTF_profileDelta(SDTF_PROFILE_ONESHOT));
+ }
+
+ return retVal;
+}
+
+/*********************************************************************
+ * @fn SDTF_runECC1BitCBASSInjectTest
+ *
+ * @brief Execute ECC Single bit error inject test on CBASS ECC aggregator
+ *
+ * @param None
+ *
+ * @return 0 : Success; < 0 for failures
+ */
+int32_t SDTF_runECC1BitCBASSInjectTest(void)
+{
+ SDR_Result result;
+ int32_t retVal=0;
+ uint32_t subType;
+
+ SDR_ECC_InjectErrorConfig_t injectErrorConfig;
+
+ memset(&injectErrorConfig, 0, sizeof(injectErrorConfig));
+
+ SDTF_printf("\n CBASS Single bit error inject test: starting");
+
+ SDTF_profileBegin(SDTF_PROFILE_ONESHOT);
+ /* Run one shot test for CBASS 2 bit error */
+ /* Note the address is relative to start of ram */
+ injectErrorConfig.pErrMem = (uint32_t *)(0u);
+
+ injectErrorConfig.flipBitMask = 0x1;
+ injectErrorConfig.chkGrp = 0x0;
+ subType = SDR_ECC_MCU_CBASS_MEM_SUBTYPE_EDC_CTRL_ID;
+ result = SDR_ECC_injectError(SDR_ECC_MEMTYPE_MCU_CBASS_ECC_AGGR0,
+ subType,
+ SDR_INJECT_ECC_ERROR_FORCING_1BIT_ONCE,
+ &injectErrorConfig
+ );
+
+ SDTF_profileEnd(SDTF_PROFILE_ONESHOT);
+
+ if (result != SDR_PASS ) {
+ SDTF_printf("\n CBASS Single bit error inject test: Subtype %d: test failed",
+ subType);
+ retVal = -1;
+ } else {
+ SDTF_printf("\n CBASS Single bit error inject test: Subtype 0x%p test complete",
+ subType);
+ SDTF_printf("\n Cycles taken %u", SDTF_profileDelta(SDTF_PROFILE_ONESHOT));
+ }
+
+ return retVal;
+}
+
+
+/*********************************************************************
+ * @fn SDTF_runECC2BitCBASSSelfTest
+ *
+ * @brief Execute ECC Double bit error self test on CBASS ECC aggregator
+ *
+ * @param None
+ *
+ * @return 0 : Success; < 0 for failures
+ */
+int32_t SDTF_runECC2BitCBASSSelfTest(void)
+{
+ SDR_Result result;
+ int32_t retVal=0;
+ uint32_t subType;
+
+ SDR_ECC_InjectErrorConfig_t injectErrorConfig;
+
+ SDTF_printf("\n CBASS Double bit error self test: starting");
+
+ memset(&injectErrorConfig, 0, sizeof(injectErrorConfig));
+
+ SDTF_profileBegin(SDTF_PROFILE_ONESHOT);
+ /* Run one shot test for CBASS 2 bit error */
+ /* Note the address is relative to start of ram */
+ injectErrorConfig.pErrMem = (uint32_t *)(0u);
+
+ injectErrorConfig.flipBitMask = 0x5;
+ injectErrorConfig.chkGrp = 0x0;
+ subType = SDR_ECC_MCU_CBASS_MEM_SUBTYPE_EDC_CTRL_ID;
+
+ result = SDR_ECC_selfTest(SDR_ECC_MEMTYPE_MCU_CBASS_ECC_AGGR0,
+ subType,
+ SDR_INJECT_ECC_ERROR_FORCING_2BIT_ONCE,
+ &injectErrorConfig,
+ 1000);
+
+ SDTF_profileEnd(SDTF_PROFILE_ONESHOT);
+
+ if (result != SDR_PASS ) {
+ SDTF_printf("\n CBASS Double bit error self test: Subtype %d: fixed location once test failed",
+ subType);
+ retVal = -1;
+ } else {
+ SDTF_printf("\n CBASS Double bit error self test: Subtype 0x%p fixed location once test complete",
+ subType);
+ SDTF_printf("\n Cycles taken %u", SDTF_profileDelta(SDTF_PROFILE_ONESHOT));
+ }
+
+ return retVal;
+}
+
+/*********************************************************************
+ * @fn SDTF_runECC2BitCBASSInjectTest
+ *
+ * @brief Execute ECC Doule bit error inject test on CBASS ECC aggregator
+ *
+ * @param None
+ *
+ * @return 0 : Success; < 0 for failures
+ */
+int32_t SDTF_runECC2BitCBASSInjectTest(void)
+{
+ SDR_Result result;
+ int32_t retVal=0;
+ uint32_t subType;
+
+ SDR_ECC_InjectErrorConfig_t injectErrorConfig;
+
+ memset(&injectErrorConfig, 0, sizeof(injectErrorConfig));
+
+ SDTF_printf("\n CBASS Double bit error inject test: starting");
+
+ SDTF_profileBegin(SDTF_PROFILE_ONESHOT);
+ /* Run one shot test for CBASS 2 bit error */
+ /* Note the address is relative to start of ram */
+ injectErrorConfig.pErrMem = (uint32_t *)(0u);
+
+ injectErrorConfig.flipBitMask = 0x5;
+ injectErrorConfig.chkGrp = 0x0;
+ subType = SDR_ECC_MCU_CBASS_MEM_SUBTYPE_EDC_CTRL_ID;
+ result = SDR_ECC_injectError(SDR_ECC_MEMTYPE_MCU_CBASS_ECC_AGGR0,
+ subType,
+ SDR_INJECT_ECC_ERROR_FORCING_2BIT_ONCE,
+ &injectErrorConfig
+ );
+
+ SDTF_profileEnd(SDTF_PROFILE_ONESHOT);
+
+ if (result != SDR_PASS ) {
+ SDTF_printf("\n CBASS Double bit error inject test: Subtype %d: test failed",
+ subType);
+ retVal = -1;
+ } else {
+ SDTF_printf("\n CBASS Double bit error inject test: Subtype 0x%p test complete",
+ subType);
+ SDTF_printf("\n Cycles taken %u", SDTF_profileDelta(SDTF_PROFILE_ONESHOT));
+ }
+
+ return retVal;
+}
static bool SDTF_ECC_DEDTriggerFlag = false;
/*********************************************************************
diff --git a/packages/ti/diag/sdr/test/sdtf-test/src/sdtf_ecc.h b/packages/ti/diag/sdr/test/sdtf-test/src/sdtf_ecc.h
index b5113c0999fc96eebc1b6bb62400d8158dbf0915..6e4fa982be8abc84bbd1ff858298860cf9352c12 100644 (file)
*/
int32_t SDTF_runECC2BitCodeInjectTest(void);
+
+/*********************************************************************
+ * @fn SDTF_runECC2BitCBASSSelfTest
+ *
+ * @brief Execute ECC Double bit error self test on CBASS ECC aggregator
+ *
+ * @param None
+ *
+ * @return 0 : Success; < 0 for failures
+ */
+int32_t SDTF_runECC2BitCBASSSelfTest(void);
+
+/*********************************************************************
+ * @fn SDTF_runECC2BitCBASSInjectTest
+ *
+ * @brief Execute ECC Doule bit error inject test on CBASS ECC aggregator
+ *
+ * @param None
+ *
+ * @return 0 : Success; < 0 for failures
+ */
+int32_t SDTF_runECC2BitCBASSInjectTest(void);
+
+
+/*********************************************************************
+ * @fn SDTF_runECC1BitCBASSSelfTest
+ *
+ * @brief Execute ECC Single bit error self test on CBASS ECC aggregator
+ *
+ * @param None
+ *
+ * @return 0 : Success; < 0 for failures
+ */
+int32_t SDTF_runECC1BitCBASSSelfTest(void);
+
+/*********************************************************************
+ * @fn SDTF_runECC1BitCBASSInjectTest
+ *
+ * @brief Execute ECC Single bit error inject test on CBASS ECC aggregator
+ *
+ * @param None
+ *
+ * @return 0 : Success; < 0 for failures
+ */
+int32_t SDTF_runECC1BitCBASSInjectTest(void);
+
+
#endif /* _INCLUDE_SDTF_ECC_H_ */
diff --git a/packages/ti/diag/sdr/test/sdtf-test/src/sdtf_init.c b/packages/ti/diag/sdr/test/sdtf-test/src/sdtf_init.c
index ccb4ff7d19006c5dfbc0c6a8fedce570ca2499c4..c4db114be8375e9499e56c16be54bacb824584d4 100644 (file)
#endif\r
\r
/* Defines */\r
-#define MAX_MEM_SECTIONS (8u)\r
+#define MCU_R5F_MAX_MEM_SECTIONS (8u)\r
+#define MCU_CBASS_MAX_MEM_SECTIONS (3u)\r
\r
/* Function prototypes */\r
void SDTF_copyResetVector(void);\r
* and PCIE events */\r
};\r
\r
-static SDR_ECC_MemSubType SDTF_R5FCoresubMemTypeList[MAX_MEM_SECTIONS] =\r
+static SDR_ECC_MemSubType SDTF_R5FCoresubMemTypeList[MCU_R5F_MAX_MEM_SECTIONS] =\r
{\r
SDR_ECC_R5F_MEM_SUBTYPE_ATCM0_BANK0_VECTOR_ID,\r
SDR_ECC_R5F_MEM_SUBTYPE_ATCM0_BANK1_VECTOR_ID,\r
};\r
static SDR_ECC_InitConfig_t SDTF_R5FCoreECCInitConfig =\r
{\r
- .numRams = MAX_MEM_SECTIONS,\r
+ .numRams = MCU_R5F_MAX_MEM_SECTIONS,\r
/**< Number of Rams ECC is enabled */\r
.pMemSubTypeList = &(SDTF_R5FCoresubMemTypeList[0]),\r
/**< Sub type list */\r
};\r
\r
+static SDR_ECC_MemSubType SDTF_MCUCBASSsubMemTypeList[MCU_CBASS_MAX_MEM_SECTIONS] =\r
+{\r
+ SDR_ECC_MCU_CBASS_MEM_SUBTYPE_WR_RAMECC_ID,\r
+ SDR_ECC_MCU_CBASS_MEM_SUBTYPE_RD_RAMECC_ID,\r
+ SDR_ECC_MCU_CBASS_MEM_SUBTYPE_EDC_CTRL_ID,\r
+};\r
+\r
+static SDR_ECC_InitConfig_t SDTF_MCUCBASSECCInitConfig =\r
+{\r
+ .numRams = MCU_CBASS_MAX_MEM_SECTIONS,\r
+ /**< Number of Rams ECC is enabled */\r
+ .pMemSubTypeList = &(SDTF_MCUCBASSsubMemTypeList[0]),\r
+ /**< Sub type list */\r
+};\r
+\r
+\r
HwiP_Handle SDTF_EsmHiHwiPHandle;\r
HwiP_Handle SDTF_EsmLoHwiPHandle;\r
HwiP_Handle SDTF_EsmCfgHwiPHandle;\r
retValue = -1;\r
}\r
}\r
+\r
+ if (retValue == 0) {\r
+ result = SDR_ECC_init(SDR_ECC_MEMTYPE_MCU_CBASS_ECC_AGGR0, NULL);\r
+ if (result == SDR_PASS) {\r
+ /* Negative test failed */\r
+ SDTF_printf("SDTF_init: Error ECC Negative tests: result = %d\n", result);\r
+ retValue = -1;\r
+ }\r
+ }\r
return retValue;\r
}\r
#endif\r
\r
-\r
/*********************************************************************\r
* @fn SDTF_init\r
*\r
int32_t SDTF_init (void)\r
{\r
int32_t retValue=0;\r
+\r
SDR_Result result;\r
#ifdef SDTF_BOARD\r
Board_initCfg boardCfg;\r
}\r
}\r
\r
+ if (retValue == 0) {\r
+ /* Initialize ECC */\r
+ result = SDR_ECC_init(SDR_ECC_MEMTYPE_MCU_CBASS_ECC_AGGR0, &SDTF_MCUCBASSECCInitConfig);\r
+ if (result != SDR_PASS) {\r
+ /* print error and quit */\r
+ SDTF_printf("SDTF_init: Error initializing R5F core ECC: result = %d\n", result);\r
+\r
+ retValue = -1;\r
+ } else {\r
+ SDTF_printf("\nSDTF_init: R5F Core Init ECC complete \n");\r
+ }\r
+ }\r
+\r
+ if (retValue == 0) {\r
+ /* Initialize ECC callbacks within the MCU ESM */\r
+ result = SDR_ECC_initEsm(SDR_ESM_INSTANCE_MCU);\r
+ if (result != SDR_PASS) {\r
+ /* print error and quit */\r
+ SDTF_printf("SDTF_init: Error initializing ECC callback for MCU ESM: result = %d\n", result);\r
+\r
+ retValue = -1;\r
+ } else {\r
+ SDTF_printf("\nSDTF_init: ECC Callback Init complete for MCU ESM \n");\r
+ }\r
+ }\r
+\r
+ if (retValue == 0) {\r
+ /* Initialize ECC callbacks within the Main ESM */\r
+ result = SDR_ECC_initEsm(SDR_ESM_INSTANCE_MAIN);\r
+ if (result != SDR_PASS) {\r
+ /* print error and quit */\r
+ SDTF_printf("SDTF_init: Error initializing ECC callback for Main ESM: result = %d\n", result);\r
+\r
+ retValue = -1;\r
+ } else {\r
+ SDTF_printf("\nSDTF_init: ECC Callback Init complete for Main ESM \n");\r
+ }\r
+ }\r
+\r
if (retValue == 0) {\r
/* Initialize VIM ECC memory ; This is specifically for VIM in lockstep*/\r
/* All other memories are auto initialized by hardware */\r
\r
}\r
\r
-void SDR_ECC_applicationCallbackFunction(uint32_t errorSrc, uint32_t address){\r
+void SDR_ECC_applicationCallbackFunction(uint32_t errorSrc,\r
+ uint32_t address,\r
+ uint32_t ramId,\r
+ uint64_t bitErrorOffset,\r
+ uint32_t bitErrorGroup){\r
\r
- SDTF_printf("\n ECC Error Call back function called : errorSrc 0x%x, address 0x%x. \n",\r
- errorSrc, address);\r
+ SDTF_printf("\n ECC Error Call back function called : errorSrc 0x%x, address 0x%x, " \\r
+ "ramId %d, bitErrorOffset 0x%04x%04x, bitErrorGroup %d\n",\r
+ errorSrc, address, ramId, (uint32_t)(bitErrorOffset >> 32),\r
+ (uint32_t)(bitErrorOffset & 0x00000000FFFFFFFF), bitErrorGroup);\r
SDTF_printf(" Take action \n");\r
\r
/* Any additional customer specific actions can be added here */\r
diff --git a/packages/ti/diag/sdr/test/sdtf-test/src/sdtf_test.c b/packages/ti/diag/sdr/test/sdtf-test/src/sdtf_test.c
index 4bcb923a6249e59d9406d0257090ad90b30d3ef4..9abdee8fa6e2d25484a71600bc69ccf6e99421cf 100755 (executable)
/* Number of commands run by the "run_all" command
* Note: This should match number of entries in the tables below
*/
-#define SDTF_NUM_RUNALL_TEST_COMMANDS (35u)
+#define SDTF_NUM_RUNALL_TEST_COMMANDS (37u)
/* Other commands not covered by run_all */
#define SDTF_NUM_OTHER_TEST_COMMANDS (6u)
/* Number of commands run by the "run_all" command
* Note: This should match number of entries in the tables below
*/
-#define SDTF_NUM_RUNALL_TEST_COMMANDS (41u)
+#define SDTF_NUM_RUNALL_TEST_COMMANDS (43u)
/* Other commands not covered by run_all */
#define SDTF_NUM_OTHER_TEST_COMMANDS (0u)
{ "ecc2_programinject", SDTF_runECC2BitCodeInjectTest },
{ "exception_runapitests", SDTF_runExceptionApiTests },
{ "ecc1_inject", SDTF_runECC1BitInjectTest },
+ { "cbass2_inject", SDTF_runECC2BitCBASSInjectTest },
+ { "cbass2_selftest", SDTF_runECC2BitCBASSSelfTest },
{ "ecc2_vimramdedvector", SDTF_runECC2BitVIMRAMDEDvector },
{ "ccm_selftest", SDTF_runCCMSelfTest },
{ "ccm_selftest_polarityinvert", SDTF_runCCMSelfTestErrorForce },