PDK-8367: Board: Updated SPI EEPROM diag test for AM64x EVM
authorM V Pratap Reddy <x0257344@ti.com>
Sat, 16 Jan 2021 10:36:52 +0000 (16:06 +0530)
committerVishal Mahaveer <vishalm@ti.com>
Mon, 18 Jan 2021 13:58:47 +0000 (07:58 -0600)
packages/ti/board/diag/spi_eeprom/build/makefile
packages/ti/board/diag/spi_eeprom/src/spi_eeprom.c [deleted file]
packages/ti/board/diag/spi_eeprom/src/spi_eeprom.h [deleted file]
packages/ti/board/diag/spi_eeprom/src/spi_eeprom_test.c
packages/ti/board/diag/spi_eeprom/src/spi_eeprom_test.h [new file with mode: 0644]

index 85a437d2ba4bf1c82601a6883f3d5890634e1bfa..19218726aff65994b33505abb0aeb83802faaf2b 100755 (executable)
@@ -72,7 +72,7 @@ PACKAGE_SRCS_COMMON += ../../common/$(SOC)
 PACKAGE_SRCS_COMMON += ../../board_diag_component.mk\r
 PACKAGE_SRCS_COMMON += ../../create_sd.bat ../../create_sd.sh\r
 \r
-SRCS_COMMON += spi_eeprom_test.c spi_eeprom.c diag_common_cfg.c\r
+SRCS_COMMON += spi_eeprom_test.c diag_common_cfg.c\r
 \r
 ifeq ($(CORE),$(filter $(CORE), mcu1_0))\r
 SRCS_ASM_COMMON += diag_entry_r5.asm\r
diff --git a/packages/ti/board/diag/spi_eeprom/src/spi_eeprom.c b/packages/ti/board/diag/spi_eeprom/src/spi_eeprom.c
deleted file mode 100755 (executable)
index 86ef902..0000000
+++ /dev/null
@@ -1,287 +0,0 @@
-/*\r
- * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/\r
- *\r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions\r
- * are met:\r
- *\r
- * Redistributions of source code must retain the above copyright\r
- * notice, this list of conditions and the following disclaimer.\r
- *\r
- * Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in the\r
- * documentation and/or other materials provided with the\r
- * distribution.\r
- *\r
- * Neither the name of Texas Instruments Incorporated nor the names of\r
- * its contributors may be used to endorse or promote products derived\r
- * from this software without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
- *\r
- */\r
-\r
- /**\r
- *  \file   spi_eeprom.c\r
- *\r
- *  \brief  This file contains spi eeprom data transfer functions.\r
- *          \r
- */\r
-\r
-#include <stdio.h>\r
-#include <stdlib.h>\r
-#include <string.h>\r
-\r
-#include <ti/drv/spi/SPI.h>\r
-#include <ti/drv/spi/soc/SPI_soc.h>\r
-#include <ti/drv/uart/UART_stdio.h>\r
-\r
-#include "board.h"\r
-#include "board_cfg.h"\r
-#include "spi_eeprom.h"\r
-\r
-/*\r
- *  \brief  Activate SPI transfer\r
- *\r
- *  Command code used with SPI_control(). arg is a pointer to an uint32_t\r
- *  that contains the enable/disable value to be placed into the SPI register.\r
- *\r
- *  Command argument 0: (1: enable, 0: disable)\r
- */\r
-#define SPI_V0_CMD_XFER_ACTIVATE   (SPI_CMD_RESERVED + 0U)\r
-\r
-extern void BOARD_delay(uint32_t usecs);\r
-\r
-/**\r
- *  \brief    This function is used to perform spi command\r
- *            read\r
- *\r
- *  \param    handle  spi handle specific to spi instance\r
- *                       *cmd    spi command to be read\r
- *                       cmdLen  length of the spi command\r
- *            *rxbuf  pionter to the receive buffer\r
- *            rxlen   length of the receive buffer\r
- *\r
- * \return    bool\r
- * \n         true  - command read successfully\r
- * \n         false - command read failed\r
- * \r
- */\r
-static bool spieeprom_cmd_read(SPI_Handle handle,\r
-                               uint8_t *cmd,\r
-                               uint32_t cmdLen,\r
-                               uint8_t *rxbuf,\r
-                               uint32_t rxlen)\r
-{\r
-    SPI_Transaction transaction;     /* SPI transaction structure */\r
-    uint32_t        xferEnable;\r
-    uint32_t        terminateXfer = 0;\r
-    bool            retVal = false;\r
-\r
-    /* Enable transfer */\r
-    xferEnable = 1;\r
-    SPI_control(handle, SPI_V0_CMD_XFER_ACTIVATE, (void *)&xferEnable);\r
-\r
-    /* If no read data, release CS at the end of write */\r
-    if (rxlen == 0)\r
-               terminateXfer = 1;\r
-\r
-    /* Write Command */\r
-    transaction.txBuf = cmd;\r
-    transaction.rxBuf = NULL;\r
-    transaction.count = cmdLen;\r
-    transaction.arg = (void *)&terminateXfer;\r
-\r
-    retVal = SPI_transfer(handle, &transaction);\r
-       if (retVal == false)\r
-        return retVal;\r
-\r
-    /* Receive the data */\r
-    if (rxlen)\r
-    {\r
-        /* Read Device ID */\r
-        transaction.txBuf = NULL;\r
-        transaction.rxBuf = rxbuf;\r
-        transaction.count = rxlen;\r
-        terminateXfer = 1;\r
-        transaction.arg = (void *)&terminateXfer;\r
-\r
-        retVal = SPI_transfer(handle, &transaction);\r
-    }\r
-\r
-    /* Disable transfer */\r
-    xferEnable = 0;\r
-    SPI_control(handle, SPI_V0_CMD_XFER_ACTIVATE, (void *)&xferEnable);\r
-    return retVal;\r
-}\r
-\r
-/**\r
- *  \brief    This function is used to perform spi command\r
- *            write\r
- *\r
- *  \param    handle  spi handle specific to spi instance\r
- *                       *cmd    spi command to write\r
- *                       cmdLen  length of the spi command\r
- *            *txbuf  pionter to the transfer buffer\r
- *            txlen   length of the transfer buffer\r
- *\r
- * \return    bool\r
- * \n         true  - command written successfully\r
- * \n         false - command write failed\r
- * \r
- */\r
-static bool spieeprom_cmd_write(SPI_Handle handle,\r
-                                uint8_t *cmd,\r
-                                uint32_t cmdLen,\r
-                                uint8_t *txbuf,\r
-                                uint32_t txlen)\r
-{\r
-    SPI_Transaction transaction;     /* SPI transaction structure */\r
-    uint32_t        xferEnable;\r
-    uint32_t        terminateXfer = 0;\r
-    bool            retVal = false;\r
-\r
-    /* Enable transfer */\r
-    xferEnable = 1;\r
-    SPI_control(handle, SPI_V0_CMD_XFER_ACTIVATE, (void *)&xferEnable);\r
-\r
-    /* If no read data, release CS at the end of write */\r
-    if (txlen == 0)\r
-               terminateXfer = 1;\r
-\r
-    /* Write Command */\r
-    transaction.txBuf = cmd;\r
-    transaction.rxBuf = NULL;\r
-    transaction.count = cmdLen;\r
-    transaction.arg = (void *)&terminateXfer;\r
-\r
-    retVal = SPI_transfer(handle, &transaction);\r
-       if (retVal == false)\r
-        return retVal;\r
-\r
-    /* write data */\r
-    if (txlen)\r
-    {\r
-        /* Write data */\r
-        transaction.txBuf = txbuf;\r
-        transaction.rxBuf = NULL;\r
-        transaction.count = txlen;\r
-        terminateXfer = 1;\r
-        transaction.arg = (void *)&terminateXfer;\r
-\r
-        retVal = SPI_transfer(handle, &transaction);\r
-    }\r
-\r
-    /* Disable transfer */\r
-    xferEnable = 0;\r
-    SPI_control(handle, SPI_V0_CMD_XFER_ACTIVATE, (void *)&xferEnable);\r
-    return retVal;\r
-}\r
-\r
-/**\r
- *  \brief    This function is used to perform spi write enable\r
- *\r
- *  \param    handle  spi handle specific to spi instance\r
- *                       \r
- * \return    bool\r
- * \n         true  - write enabled successfully\r
- * \n         false - write enable failed\r
- * \r
- */\r
-static bool spieeprom_write_enable(SPI_Handle handle)\r
-{\r
-    uint8_t         cmd = SPI_EEPROM_CMD_WREN;\r
-    bool            retVal;\r
-\r
-    retVal = spieeprom_cmd_read(handle, &cmd, 1, NULL, 0);\r
-\r
-    return retVal;\r
-}\r
-\r
-/**\r
- *  \brief    This function is used to write data to eeprom\r
- *\r
- *  \param    handle          spi handle specific to spi instance\r
- *            spiTransaction  pointer to spi transaction struct access\r
- *            length          length of data buffer\r
- *            addr            address to be written\r
- *                       \r
- * \return    int8_t\r
- * \n         TEST_PASS  - eeprom write passed\r
- * \n         TEST_FAIL  - eeprom write failed\r
- * \r
- */\r
-int8_t spiEepromWrite(SPI_Handle handle,\r
-                           SPI_Transaction* spiTransaction,\r
-                                                  int8_t length,\r
-                                                  uint32_t addr)\r
-{\r
-    uint8_t         cmd[3];\r
-    bool            retVal;\r
-\r
-       /* Send Write Enable command */\r
-    retVal = spieeprom_write_enable(handle);\r
-    if (retVal == false)\r
-        return TEST_FAIL;\r
-\r
-    cmd[0]  = SPI_EEPROM_CMD_WRITE;\r
-    cmd[1]  = (uint8_t)(addr >> 8);\r
-    cmd[2]  = (uint8_t)addr;\r
-\r
-    retVal = spieeprom_cmd_write(handle, cmd, 3, spiTransaction->txBuf, length);\r
-       if (retVal == false)\r
-       {\r
-        return TEST_FAIL;\r
-       }\r
-       else\r
-       {\r
-               return TEST_PASS;\r
-       }\r
-}\r
-\r
-/**\r
- *  \brief    This function is used to read data from eeprom\r
- *\r
- *  \param    handle          spi handle specific to spi instance\r
- *            spiTransaction  pointer to spi transaction struct access\r
- *            length          length of data buffer\r
- *            addr            address to be read\r
- *                       \r
- * \return    int8_t\r
- * \n         TEST_PASS  - eeprom write passed\r
- * \n         TEST_FAIL  - eeprom write failed\r
- * \r
- */\r
-int8_t spiEepromRead(SPI_Handle handle,\r
-                          SPI_Transaction* spiTransaction,\r
-                                                 int8_t length,\r
-                                                 uint32_t addr)\r
-{\r
-    uint8_t       cmd[3];\r
-    bool          retVal;\r
-\r
-    /* Initialize the command to be sent serially */\r
-    cmd[0] = SPI_EEPROM_CMD_READ;\r
-    cmd[1] = (uint8_t)(addr >> 8);\r
-    cmd[2] = (uint8_t)addr;\r
-\r
-    retVal = spieeprom_cmd_read(handle, cmd, 3, spiTransaction->rxBuf, length);\r
-       if (retVal == false)\r
-       {\r
-               return TEST_FAIL;\r
-       }\r
-       else\r
-       {\r
-               return TEST_PASS;\r
-       }\r
-}\r
diff --git a/packages/ti/board/diag/spi_eeprom/src/spi_eeprom.h b/packages/ti/board/diag/spi_eeprom/src/spi_eeprom.h
deleted file mode 100755 (executable)
index 6c0616a..0000000
+++ /dev/null
@@ -1,67 +0,0 @@
-/*\r
- * Copyright (c) 2020, Texas Instruments Incorporated\r
- * All rights reserved.\r
- *\r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions\r
- * are met:\r
- *\r
- * *  Redistributions of source code must retain the above copyright\r
- *    notice, this list of conditions and the following disclaimer.\r
- *\r
- * *  Redistributions in binary form must reproduce the above copyright\r
- *    notice, this list of conditions and the following disclaimer in the\r
- *    documentation and/or other materials provided with the distribution.\r
- *\r
- * *  Neither the name of Texas Instruments Incorporated nor the names of\r
- *    its contributors may be used to endorse or promote products derived\r
- *    from this software without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\r
- * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\r
- * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\r
- * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\r
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\r
- * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\r
- * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
- *\r
- */\r
-\r
-/**\r
- * \file      spi_eeprom.h\r
- *\r
- * \brief     This file contains spi eeprom specific structure, typedefs,\r
- *            function prototypes.\r
- *\r
- */\r
-\r
-#ifndef _SPI_EEPROM_H_\r
-#define _SPI_EEPROM_H_\r
-\r
-/* Platform test return codes */\r
-#define TEST_PASS     (0)\r
-#define TEST_FAIL     (-1)\r
-\r
-/* EEPROM Commands */\r
-#define SPI_EEPROM_CMD_WRSR            (0x01)\r
-#define SPI_EEPROM_CMD_WRITE           (0x02)\r
-#define SPI_EEPROM_CMD_READ            (0x03)\r
-#define SPI_EEPROM_CMD_WRDI            (0x04)\r
-#define SPI_EEPROM_CMD_RDSR            (0x05)\r
-#define SPI_EEPROM_CMD_WREN            (0x06)\r
-\r
-int8_t spiEepromWrite(SPI_Handle handle,\r
-                           SPI_Transaction* spiTransaction,\r
-                                                  int8_t length,\r
-                                                  uint32_t addr);\r
-\r
-int8_t spiEepromRead(SPI_Handle handle,\r
-                                                 SPI_Transaction* spiTransaction,\r
-                                                 int8_t length,\r
-                                                 uint32_t addr);\r
-\r
-#endif // _SPI_EEPROM_H_\r
index d905f298d8a9cd7ec6a10d9cc36bddbaa7904898..78f5d5db778f531ba58d821d97f9938d474f8fa5 100755 (executable)
-/*\r
- * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/\r
+/******************************************************************************\r
+ * Copyright (c) 2020 Texas Instruments Incorporated - http://www.ti.com\r
  *\r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions\r
- * are met:\r
+ *  Redistribution and use in source and binary forms, with or without\r
+ *  modification, are permitted provided that the following conditions\r
+ *  are met:\r
  *\r
- * Redistributions of source code must retain the above copyright\r
- * notice, this list of conditions and the following disclaimer.\r
+ *    Redistributions of source code must retain the above copyright\r
+ *    notice, this list of conditions and the following disclaimer.\r
  *\r
- * Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in the\r
- * documentation and/or other materials provided with the\r
- * distribution.\r
+ *    Redistributions in binary form must reproduce the above copyright\r
+ *    notice, this list of conditions and the following disclaimer in the\r
+ *    documentation and/or other materials provided with the\r
+ *    distribution.\r
  *\r
- * Neither the name of Texas Instruments Incorporated nor the names of\r
- * its contributors may be used to endorse or promote products derived\r
- * from this software without specific prior written permission.\r
+ *    Neither the name of Texas Instruments Incorporated nor the names of\r
+ *    its contributors may be used to endorse or promote products derived\r
+ *    from this software without specific prior written permission.\r
  *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
  *\r
+ *****************************************************************************/\r
+\r
+/**\r
+ * \file   spi_eeprom_test.c\r
+ *\r
+ * \brief  spi eeprom diagnostic test file.\r
+ *\r
+ * Targeted Functionality: Verifies the spi eeprom.\r
+ *\r
+ * Operation: This test verifies by writing and reading the data\r
+ *             to eeprom through SPI.\r
+ *\r
+ * Supported SoCs: AM64X.\r
+ *\r
+ * Supported Platforms: am64x_evm.\r
  */\r
\r
+\r
+#include "spi_eeprom_test.h"\r
+\r
+uint32_t gChNum  = 0;\r
+/* Buffer containing the known data that needs to be written to Eeprom */\r
+uint16_t txBuf[BOARD_DIAG_MAX_BUFF_SIZE];\r
+/* Buffer containing the received data */\r
+uint16_t rxBuf[BOARD_DIAG_MAX_BUFF_SIZE];\r
+uint16_t cmdBuf[BOARD_DIAG_MAX_BUFF_SIZE];\r
+\r
 /**\r
- *  \file   spi_eeprom_test.c\r
+ *  \brief    Function to enable SPI for data transfers\r
  *\r
- *  \brief  This file contains spi eeprom test functions.\r
- *          \r
  */\r
+static void BoardDiag_spiEepromStartTransfer(void)\r
+{\r
+    /* Enable the transmitter FIFO of McSPI peripheral.*/\r
+    McSPITxFIFOConfig(BOARD_DIAG_SPI0_BASE_ADDRESS, MCSPI_TX_FIFO_ENABLE, MCSPI_CHANNEL_0);\r
+\r
+    /* Enable the receiver FIFO of McSPI peripheral.*/\r
+    McSPIRxFIFOConfig(BOARD_DIAG_SPI0_BASE_ADDRESS, MCSPI_RX_FIFO_ENABLE, MCSPI_CHANNEL_0);\r
+\r
+    /* Enable the McSPI channel for communication.*/\r
+    McSPIChannelEnable(BOARD_DIAG_SPI0_BASE_ADDRESS, MCSPI_CHANNEL_0);\r
+\r
+    /* SPIEN line is forced to low state.*/\r
+    McSPICSAssert(BOARD_DIAG_SPI0_BASE_ADDRESS, MCSPI_CHANNEL_0);\r
+}\r
 \r
\r
-#include <stdio.h>\r
-#include <stdlib.h>\r
-#include <string.h>\r
-\r
-#include <ti/csl/soc.h>\r
-#include <ti/drv/spi/SPI.h>\r
-#include <ti/drv/spi/soc/SPI_soc.h>\r
-#include <ti/drv/uart/UART_stdio.h>\r
-\r
-#include "board.h"\r
-#include "board_cfg.h"\r
-\r
-/* Platform test return codes */\r
-#define TEST_PASS     (0)\r
-#define TEST_FAIL     (-1)\r
-#define CSL_SPI_CNT   (1U)\r
-\r
-/*SPI data buffer length in bytes*/\r
-#define BOARD_DIAG_SPI_TEST_BUF_LENGTH             (64U)\r
-\r
-/* SPI EEPROM TEST DELAY in usec */\r
-#define BOARD_DIAG_SPI_EEPROM_TEST_DELAY           (100000U)\r
-\r
-/* SPI EEPROM CLOCK FREQUENCY in Hz */\r
-#define BOARD_DIAG_SPI_EEPROM_CLOCK_FREQUENCY      (5000000U)\r
-\r
-/* SPI CLOCK FREQUENCY in Hz */\r
-#define BOARD_DIAG_SPI_CLOCK_FREQUENCY             (1000000U)\r
-\r
-extern const SPI_Config SPI_config[];\r
-extern void BOARD_delay(uint32_t usecs);\r
-extern int8_t spiEepromWrite(SPI_Handle handle,\r
-                           SPI_Transaction* spiTransaction,\r
-                                                  int8_t length,\r
-                                                  uint32_t addr);\r
-\r
-extern int8_t spiEepromRead(SPI_Handle handle,\r
-                                                 SPI_Transaction* spiTransaction,\r
-                                                 int8_t length,\r
-                                                 uint32_t addr);\r
-                                                 \r
-int8_t eepromData[BOARD_DIAG_SPI_TEST_BUF_LENGTH] = {0x01, 0x02, 0x03, 0x04, 0x05,\r
-                                                     0x06, 0x07, 0x08, 0x09, 0x0A,\r
-                                                                                                0x0B, 0x0C, 0x0D, 0x0E, 0x0F,\r
-                                                                                                0x10, 0x11, 0x12, 0x13, 0x14,\r
-                                                                                                0x15, 0x16, 0x17, 0x18, 0x19,\r
-                                                                                                0x1A, 0x1B, 0x1C, 0x1D, 0x1E,\r
-                                                                                                0x1F, 0x20, 0x21, 0x22, 0x23,\r
-                                                                                                0x24, 0x25, 0x26, 0x27, 0x28,\r
-                                                                                                0x29, 0x2A, 0x2B, 0x2C, 0x2D,\r
-                                                                                                0x2E, 0x2F, 0x30, 0x31, 0x32,\r
-                                                                                                0x33, 0x34, 0x35, 0x36, 0x37,\r
-                                                                                                0x38, 0x39, 0x3A, 0x3B, 0x3C,\r
-                                                                                                0x3D, 0x3E, 0x3F, 0x40};\r
-\r
-int8_t txbuf[BOARD_DIAG_SPI_TEST_BUF_LENGTH];\r
-int8_t rxbuf[BOARD_DIAG_SPI_TEST_BUF_LENGTH];                                                                                          \r
+/**\r
+ *  \brief    Function to disable SPI for data transfers\r
+ *\r
+ */\r
+static void BoardDiag_spiEepromStopTransfer(void)\r
+{\r
+    /* Force SPIEN line to the inactive state.*/\r
+    McSPICSDeAssert(BOARD_DIAG_SPI0_BASE_ADDRESS, MCSPI_CHANNEL_0);\r
+    /* Disable the McSPI channel.*/\r
+    McSPIChannelDisable(BOARD_DIAG_SPI0_BASE_ADDRESS, MCSPI_CHANNEL_0);\r
+}\r
 \r
 /**\r
- *  \brief    This function compares data between two buffers\r
+ *  \brief    Writes a block of data to SPI module\r
  *\r
- *  \param    *expData  pointer to the reference buffer\r
- *            *rxData   pointer to the buffer to be compared\r
- *            length    length of the buffer\r
+ *  \param    dataBuf    [IN]   Buffer with data to write\r
+ *  \param    length     [IN]   Length of data to write\r
  *\r
  * \return\r
- * \n         TEST_PASS  - Test Passed\r
- * \n         TEST_FAIL  - Test Failed\r
- */                                                                                    \r
-static int8_t CompareData(int8_t *expData, \r
-                                                          int8_t *rxData, \r
-                                                          uint16_t length)\r
+ * \n      0   - Success\r
+ * \n      -1  - Failure\r
+ */\r
+static int8_t BoardDiag_spiEepromWriteData(uint16_t *dataBuf, uint16_t length)\r
 {\r
-    uint32_t idx = 0;\r
-    uint32_t match = 1;\r
+    uint16_t dataCount = 0;\r
+    uint32_t dummyByte = 0;\r
+    volatile uint32_t channelStatus = 0;\r
 \r
-    for(idx = 0; ((idx < length) && (match != 0)); idx++)\r
+    dummyByte = dummyByte;\r
+\r
+    while( dataCount < length)\r
     {\r
-        if(*expData != *rxData) match = 0;\r
-        expData++;\r
-        rxData++;\r
+        channelStatus = McSPIChannelStatusGet(BOARD_DIAG_SPI0_BASE_ADDRESS, MCSPI_CHANNEL_0);\r
+        if ((channelStatus & CSL_MCSPI_CH0STAT_TXS_MASK) == CSL_MCSPI_CH0STAT_TXS_MASK)\r
+        {\r
+            McSPITransmitData(BOARD_DIAG_SPI0_BASE_ADDRESS, *dataBuf, MCSPI_CHANNEL_0);\r
+            dataCount++;\r
+            dataBuf++;\r
+\r
+            /* Wait till the transfer is complete */\r
+            while((McSPIChannelStatusGet(BOARD_DIAG_SPI0_BASE_ADDRESS, MCSPI_CHANNEL_0) & CSL_MCSPI_CH0STAT_EOT_MASK) != CSL_MCSPI_CH0STAT_EOT_MASK);\r
+        }\r
+        else\r
+        {\r
+            UART_printf("Getting SPI channel status failed\n");\r
+            return (int8_t)channelStatus;\r
+        }\r
+\r
+        /* Flush the data dummy data from the Rx buffer */\r
+        if((channelStatus & CSL_MCSPI_CH0STAT_RXS_MASK) == CSL_MCSPI_CH0STAT_RXS_MASK)\r
+        {\r
+            dummyByte = McSPIReceiveData(BOARD_DIAG_SPI0_BASE_ADDRESS, MCSPI_CHANNEL_0);\r
+        }\r
     }\r
 \r
-    if(match == 1)\r
-       {\r
-               return TEST_PASS;\r
-       }\r
+    return 0;\r
+}\r
 \r
-    return TEST_FAIL;\r
+/**\r
+ *  \brief    Reads a block of data from SPI module\r
+ *\r
+ *  \param    dataBuf    [IN]   Buffer to store the data read\r
+ *  \param    length     [IN]   Length of data to read\r
+ *\r
+ */\r
+static void BoardDiag_spiEepromReadData(uint16_t *dataBuf, uint16_t length)\r
+{\r
+    uint16_t dataCount = 0;\r
+    uint32_t dummyByte = 0;\r
+    volatile uint32_t channelStatus = 0;\r
+\r
+    /* Flush the dummy data from the Rx buffer */\r
+    channelStatus = McSPIChannelStatusGet(BOARD_DIAG_SPI0_BASE_ADDRESS, MCSPI_CHANNEL_0);\r
+    while((channelStatus & CSL_MCSPI_CH0STAT_RXS_MASK) == CSL_MCSPI_CH0STAT_RXS_MASK)\r
+    {\r
+        dummyByte = McSPIReceiveData(BOARD_DIAG_SPI0_BASE_ADDRESS, MCSPI_CHANNEL_0);\r
+        channelStatus = McSPIChannelStatusGet(BOARD_DIAG_SPI0_BASE_ADDRESS, MCSPI_CHANNEL_0);\r
+    }\r
+\r
+    dummyByte = 0;\r
+\r
+    while( dataCount < length)\r
+    {\r
+        channelStatus = McSPIChannelStatusGet(BOARD_DIAG_SPI0_BASE_ADDRESS, MCSPI_CHANNEL_0);\r
+        if ((channelStatus & CSL_MCSPI_CH0STAT_RXS_MASK) == CSL_MCSPI_CH0STAT_RXS_MASK)\r
+        {\r
+            *(uint16_t *)dataBuf = (uint16_t)McSPIReceiveData(BOARD_DIAG_SPI0_BASE_ADDRESS, MCSPI_CHANNEL_0);\r
+            dataCount++;\r
+            dataBuf++;\r
+        }\r
+\r
+        if ((channelStatus & CSL_MCSPI_CH0STAT_TXS_MASK) == CSL_MCSPI_CH0STAT_TXS_MASK)\r
+        {\r
+            McSPITransmitData(BOARD_DIAG_SPI0_BASE_ADDRESS, dummyByte, MCSPI_CHANNEL_0);\r
+\r
+            /* Wait till the transfer is complete */\r
+            while((McSPIChannelStatusGet(BOARD_DIAG_SPI0_BASE_ADDRESS, MCSPI_CHANNEL_0) & CSL_MCSPI_CH0STAT_EOT_MASK) != CSL_MCSPI_CH0STAT_EOT_MASK);\r
+        }\r
+    }\r
 }\r
 \r
 /**\r
- *  \brief    This function writes and reads data in eeprom\r
+ *  \brief    Writes a SPI Eeprom page\r
  *\r
- *  \param    spi_instance spi instance on which device is connected\r
- *            \r
+ *  \param    dataBuf    [IN]   Buffer with data to write\r
+ *  \param    pageOffset [IN]   Eeprom page offset\r
+ *  \param    length     [IN]   Length of data to write\r
  *\r
  * \return\r
- * \n         TEST_PASS  - Test Passed\r
- * \n         TEST_FAIL  - Test Failed\r
+ * \n      0   - Success\r
+ * \n      -1  - Failure\r
  */\r
-static int8_t spi_eeprom_access_test(uint8_t spi_instance)\r
+static int8_t BoardDiag_spiEepromWritePage(uint16_t *dataBuf, uint16_t pageOffset, uint16_t length)\r
 {\r
-       uint32_t index;\r
-       uint32_t addr;\r
-       SPI_Params spiParams;\r
-    SPI_Handle handle = NULL;\r
-    SPI_Transaction spiTransaction;\r
-       int8_t length;\r
-    int8_t status;\r
-       \r
-       for (index=0; index<CSL_SPI_CNT; index++)\r
+    uint16_t cmd[1];\r
+    int8_t testStatus = 0;\r
+\r
+    BoardDiag_spiEepromStartTransfer();\r
+\r
+    cmd[0] = BOARD_DIAG_NOR_CMD_PAGE_PROG | pageOffset;\r
+    testStatus = BoardDiag_spiEepromWriteData(cmd, 1);\r
+    if(testStatus != 0)\r
     {\r
-        ((SPI_v1_HWAttrs *)SPI_config[index].hwAttrs)->enableIntr = false;\r
+        UART_printf("\nSPI Eeprom page programming Failed\n");\r
+        return -1;\r
     }\r
-       \r
-    SPI_init();\r
-\r
-       /* Default SPI configuration parameters */\r
-    SPI_Params_init(&spiParams);\r
-       spiParams.bitRate = BOARD_DIAG_SPI_EEPROM_CLOCK_FREQUENCY;\r
-       spiParams.frameFormat  = SPI_POL0_PHA1;\r
-       spiParams.transferMode = (SPI_TransferMode)SPI_OPER_MODE_BLOCKING;\r
-\r
-    handle = SPI_open(spi_instance, &spiParams);\r
-       if(handle == NULL)\r
-       {\r
-               UART_printf("SPI Handle open failed\n");\r
-               return(TEST_FAIL);\r
-       }\r
-\r
-    /* populating buffers with data */\r
-       for(index=0; index<BOARD_DIAG_SPI_TEST_BUF_LENGTH; index++)\r
-       {\r
-               txbuf[index] = eepromData[index];\r
-               rxbuf[index] = 0U;\r
-       }\r
-       \r
-       /* Write to EEPROM */\r
-       UART_printf("Writing data to EEPROM\n");\r
-       addr = 0;\r
-       length = BOARD_DIAG_SPI_TEST_BUF_LENGTH;\r
-    spiTransaction.txBuf = txbuf;\r
-       spiTransaction.rxBuf = rxbuf;\r
-    status = spiEepromWrite(handle, &spiTransaction,length,addr);\r
-       BOARD_delay(BOARD_DIAG_SPI_EEPROM_TEST_DELAY);\r
-\r
-       /* Read from EEPROM */\r
-       UART_printf("Reading data from EEPROM\n");\r
-       length = BOARD_DIAG_SPI_TEST_BUF_LENGTH;\r
-    spiTransaction.txBuf = NULL;\r
-    spiTransaction.rxBuf = rxbuf;\r
-    status = spiEepromRead(handle, &spiTransaction,length,addr);\r
-\r
-    SPI_close(handle);\r
-\r
-    status = CompareData(&eepromData[0], &rxbuf[0], BOARD_DIAG_SPI_TEST_BUF_LENGTH);\r
-       if(status == TEST_PASS) \r
-       {\r
-               UART_printf("Data Matched\n");\r
-       }\r
-       else\r
-       {\r
-               UART_printf("Data Mismatch!\n");\r
-       }\r
-    return status;\r
+\r
+    /* 16-bit data transfer */\r
+    McSPIWordLengthSet(BOARD_DIAG_SPI0_BASE_ADDRESS, MCSPI_WORD_LENGTH(16), gChNum);\r
+    testStatus = BoardDiag_spiEepromWriteData(dataBuf, length);\r
+    if(testStatus != 0)\r
+    {\r
+        UART_printf("\nSPI Eeprom write data Failed\n");\r
+        return -1;\r
+    }\r
+    BoardDiag_spiEepromStopTransfer();\r
+    McSPIWordLengthSet(BOARD_DIAG_SPI0_BASE_ADDRESS, MCSPI_WORD_LENGTH(9), gChNum);\r
+    return 0;\r
 }\r
 \r
 /**\r
- *  \brief    This function is used to perform soc level \r
- *            initialisation of spi\r
+ *  \brief    Reads a SPI Eeprom page\r
  *\r
- *  \param    spi_instance  instance which has to be initialised\r
+ *  \param    dataBuf    [IN]   Buffer to store the data read\r
+ *  \param    pageOffset [IN]   Eeprom page offset\r
+ *  \param    length     [IN]   Length of data to read\r
  *\r
- * \return    void\r
- * \r
  */\r
-static void soc_initspi(uint8_t spi_instance)\r
+static void BoardDiag_spiEepromReadPage(uint16_t *dataBuf, uint16_t pageOffset, uint16_t length)\r
 {\r
-       SPI_v1_HWAttrs spi_cfg;\r
-       \r
-       /* Get the default SPI init configurations */\r
-    SPI_socGetInitCfg(spi_instance, &spi_cfg);\r
-       spi_cfg.chNum = 0;\r
-\r
-    /* Set the default SPI init configurations */\r
-    SPI_socSetInitCfg(spi_instance, &spi_cfg);\r
+    uint16_t cmd[1];\r
+\r
+    BoardDiag_spiEepromStartTransfer();\r
+\r
+    cmd[0] = BOARD_DIAG_NOR_CMD_READ | pageOffset;\r
+\r
+    McSPIWordLengthSet(BOARD_DIAG_SPI0_BASE_ADDRESS, MCSPI_WORD_LENGTH(9), gChNum);\r
+    BoardDiag_spiEepromWriteData(cmd, 1);\r
+    BOARD_delay(50000); /* 50msec delay to complete write */\r
+\r
+    /* 17 clock cycle requires to read data (Dummy 0 bit is preceding the data */\r
+    McSPIWordLengthSet(BOARD_DIAG_SPI0_BASE_ADDRESS, MCSPI_WORD_LENGTH(17), gChNum);\r
+    BoardDiag_spiEepromReadData(dataBuf, length);\r
+\r
+    /* Setting bit length to 9 */\r
+    McSPIWordLengthSet(BOARD_DIAG_SPI0_BASE_ADDRESS, MCSPI_WORD_LENGTH(9), gChNum);\r
+\r
+    BoardDiag_spiEepromStopTransfer();\r
 }\r
 \r
 /**\r
- *  \brief    This function is used to perform ioexp spi eeprom \r
- *            read/write test\r
+ *  \brief    Sends a command to Eeprom\r
  *\r
- *  \param    void\r
+ *  \param    cmdBuf [IN]   Command buffer pointer\r
+ *  \param    length [IN]   Length of command in bytes\r
  *\r
  * \return\r
- * \n         TEST_PASS  - Test Passed\r
- * \n         TEST_FAIL  - Test Failed\r
+ * \n      0   - Success\r
+ * \n      -1  - Failure\r
  */\r
-static int8_t run_ioexp_spi_eeprom_test(void)\r
+static int8_t BoardDiag_spiEepromSendCmd(uint16_t *cmdBuf, uint16_t length)\r
 {\r
-       int8_t testStatus;\r
-       \r
-       soc_initspi(BOARD_EEPROM_SPI0_PORT);\r
-       UART_printf("\nRunning SPI1 EEPROM access Test\n\n");\r
-       \r
-       testStatus = spi_eeprom_access_test(BOARD_EEPROM_SPI0_PORT);\r
-    if(testStatus != TEST_PASS)\r
-    {\r
-           UART_printf("\nSPI1 EEPROM access Test Failed!!\n");\r
-               return (testStatus);\r
-       }\r
-       else\r
-       {\r
-               UART_printf("\nSPI1 EEPROM access Test Passed!\n");\r
-       }\r
-       return (testStatus);\r
+    BoardDiag_spiEepromStartTransfer();\r
+    BoardDiag_spiEepromWriteData(cmdBuf, length);\r
+    BoardDiag_spiEepromStopTransfer();\r
+    return 0;\r
 }\r
 \r
 /**\r
- * \brief This function performs ioexp spi eeprom test\r
+ *  \brief    Executes SPI Eeprom memory test\r
+ *\r
+ *  \param    pageOffset [IN]   Eeprom page offset\r
  *\r
- * \param void\r
+ * \return\r
+ * \n      0   - Success\r
+ * \n      -1  - Failure\r
+ */\r
+static int8_t BoardDiag_spiEepromRunTest(uint16_t  pageOffset)\r
+{\r
+    uint8_t count;\r
+    uint8_t index;\r
+    uint16_t pageOff;\r
+    uint32_t failIndex;\r
+    int8_t testStatus = 0;\r
+\r
+    BoardDiag_genPattern((uint8_t *)cmdBuf, BOARD_DIAG_MAX_BUFF_SIZE,\r
+                         BOARD_DIAG_TEST_PATTERN_NULL);\r
+#if defined(DIAG_COMPLIANCE_TEST)\r
+    BoardDiag_genPattern((uint8_t *)txBuf, BOARD_DIAG_MAX_BUFF_SIZE,\r
+                         BOARD_DIAG_TEST_PATTERN_AA_55);\r
+#else\r
+    /* Data byte is 2, but buffer size converter into 1 byte */\r
+    BoardDiag_genPattern((uint8_t *)txBuf, (BOARD_DIAG_MAX_BUFF_SIZE * 2),\r
+                         BOARD_DIAG_TEST_PATTERN_RANDOM);\r
+#endif\r
+    BoardDiag_genPattern((uint8_t *)rxBuf, BOARD_DIAG_MAX_BUFF_SIZE,\r
+                         BOARD_DIAG_TEST_PATTERN_NULL);\r
+\r
+    /* Write Enable */\r
+    cmdBuf[0] = BOARD_DIAG_NOR_CMD_WREN;\r
+    count = 1U;\r
+    testStatus = BoardDiag_spiEepromSendCmd(cmdBuf, count);\r
+    if(testStatus != 0)\r
+    {\r
+        UART_printf("\nSPI Eeprom write enable Failed\n");\r
+        return -1;\r
+    }\r
+\r
+    /* Erasing the complete memory */\r
+    cmdBuf[0] = BOARD_DIAG_NOR_CMD_ERASE_ALL;\r
+    count = 1U;\r
+\r
+    testStatus = BoardDiag_spiEepromSendCmd(cmdBuf, count);\r
+    if(testStatus != 0)\r
+    {\r
+        UART_printf("\nSPI Eeprom erase all Failed\n");\r
+        return -1;\r
+    }\r
+    BOARD_delay(50000); /* 50msec delay to complete erase */\r
+\r
+    pageOff = pageOffset;\r
+    /* Write to SPI Eeprom */\r
+    UART_printf("\nWriting EEPROM...\n");\r
+    for (index = 0; index < BOARD_DIAG_MAX_BUFF_SIZE; index++)\r
+    {\r
+        testStatus = BoardDiag_spiEepromWritePage(&(txBuf[index]), pageOff, 1U);\r
+        if(testStatus != 0)\r
+        {\r
+            UART_printf("\nSPI Eeprom write page Failed\n");\r
+            return -1;\r
+        }\r
+\r
+        pageOff++;\r
+        BOARD_delay(50000); /* 50msec delay to complete write */\r
+    }\r
+\r
+    UART_printf("\nReading EEPROM...\n");\r
+    /* Read from SPI Eeprom */\r
+    for (index = 0; index < BOARD_DIAG_MAX_BUFF_SIZE; index++)\r
+    {\r
+        BoardDiag_spiEepromReadPage(&(rxBuf[index]), pageOffset, 1U);\r
+        BOARD_delay(50000);\r
+\r
+        pageOffset++;\r
+    }\r
+\r
+    if(BoardDiag_memCompare((uint8_t *)txBuf, (uint8_t *)rxBuf, (BOARD_DIAG_MAX_BUFF_SIZE * 2), &failIndex) == true)\r
+    {\r
+        UART_printf("\nData Read matches with Data written to page\n");\r
+    }\r
+    else\r
+    {\r
+        UART_printf("\nSPI Eeprom Data mismatch at index = 0x%x\n", failIndex);\r
+        return -1;\r
+    }\r
+\r
+    return 0;\r
+}\r
+\r
+/**\r
+ *  \brief    Function to initialize SPI module\r
  *\r
  * \return\r
- * \n      TEST_PASS  - Test Passed\r
- * \n      TEST_FAIL  - Test Failed\r
+ * \n      0   - Success\r
+ * \n      -1  - Failure\r
+ */\r
+static int8_t BoardDiag_spiEepromInit(void)\r
+{\r
+    int8_t status = 1U;\r
+\r
+    /* Reset the McSPI instance.*/\r
+    McSPIReset(BOARD_DIAG_SPI0_BASE_ADDRESS);\r
+\r
+    /* CLOCKACTIVITY bit - OCP and Functional clocks are maintained           */\r
+    /* SIDLEMODE     bit - Ignore the idle request and configure in normal mode\r
+     */\r
+    /* AUTOIDLE      bit - Disable (OCP clock is running free, no gating)     */\r
+    MCSPISysConfigSetup(BOARD_DIAG_SPI0_BASE_ADDRESS,\r
+                        MCSPI_CLOCKS_OCP_ON_FUNC_ON,\r
+                        MCSPI_SIDLEMODE_NO,\r
+                        MCSPI_WAKEUP_DISABLE,\r
+                        MCSPI_AUTOIDLE_OFF);\r
+\r
+    /* Enable chip select pin.*/\r
+    McSPICSEnable(BOARD_DIAG_SPI0_BASE_ADDRESS);\r
+\r
+    /* Enable master mode of operation.*/\r
+    McSPIMasterModeEnable(BOARD_DIAG_SPI0_BASE_ADDRESS);\r
+\r
+    /* Perform the necessary configuration for master mode. */\r
+    status = McSPIMasterModeConfig(BOARD_DIAG_SPI0_BASE_ADDRESS,\r
+                                   MCSPI_SINGLE_CH,\r
+                                   MCSPI_TX_RX_MODE,\r
+                                   MCSPI_DATA_LINE_COMM_MODE_6,\r
+                                   gChNum);\r
+    if(status == 0)\r
+    {\r
+        UART_printf("MCSPI communication failed\n");\r
+        return -1;\r
+    }\r
+\r
+    /* Configure the McSPI bus clock depending on clock mode. */\r
+    McSPIClkConfig(BOARD_DIAG_SPI0_BASE_ADDRESS,\r
+                   BOARD_DIAG_MCSPI_IN_CLK,\r
+                   BOARD_DIAG_MCSPI_OUT_FREQ,\r
+                   gChNum,\r
+                   MCSPI_CLK_MODE_0);\r
+\r
+    /* Configure the word length.*/\r
+    McSPIWordLengthSet(BOARD_DIAG_SPI0_BASE_ADDRESS,\r
+                       MCSPI_WORD_LENGTH(9),\r
+                       gChNum);\r
+\r
+    /* Set polarity of SPIEN to low.*/\r
+    McSPICSPolarityConfig(BOARD_DIAG_SPI0_BASE_ADDRESS,\r
+                          MCSPI_CS_POL_HIGH,\r
+                          gChNum);\r
+\r
+    /* SPI_CS1 is connected to a level translator on IDK application card\r
+       which should be pulled high by default for proper operation of Eeprom\r
+     */\r
+    McSPICSPolarityConfig(BOARD_DIAG_SPI0_BASE_ADDRESS,\r
+                          MCSPI_CS_POL_LOW,\r
+                          1);\r
+    return 0;\r
+}\r
+\r
+/**\r
+ *  \brief    Executes SPI Eeprom test\r
  *\r
+ * \return\r
+ * \n      0   - Test Passed\r
+ * \n      -1  - Test Failed\r
  */\r
-static int8_t ioexp_spi_eeprom_test(void)\r
+int8_t BoardDiag_spiEepromTest(void)\r
 {\r
-       int8_t status = 0;\r
-\r
-       UART_printf  ("*************************\n"); \r
-       UART_printf  ("*    SPI EEPROM Test    *\n");\r
-       UART_printf  ("*************************\n");\r
-       \r
-       status = run_ioexp_spi_eeprom_test();\r
-       if (status != 0)\r
-       {\r
-               UART_printf("\nSPI EEPROM Test FAILED!\n");\r
-       }\r
-       else\r
-       {\r
-               UART_printf("\nSPI EEPROM Test PASSED!\n");\r
-       }\r
-\r
-       UART_printf("\nSPI EEPROM tests completed\n");\r
-       return status;\r
+    uint16_t pageOffset = 0;\r
+    int8_t testStatus;\r
+\r
+#ifdef DIAG_STRESS_TEST\r
+    UART_printf("\n************************************************\n");\r
+    UART_printf  ("*            SPI EEPROM Stress Test             *\n");\r
+    UART_printf  ("************************************************\n");\r
+#else\r
+    UART_printf("\n***************************************\n");\r
+    UART_printf  ("*            SPI EEPROM Test          *\n");\r
+    UART_printf  ("***************************************\n");\r
+#endif\r
+\r
+    testStatus = BoardDiag_spiEepromInit();\r
+    if(testStatus != 0)\r
+    {\r
+        UART_printf("\nSPI Eeprom init Failed\n");\r
+        return -1;\r
+    }\r
+\r
+    UART_printf("\nVerifying %d Bytes from offset - 0x%x\n", BOARD_DIAG_MAX_BUFF_SIZE, pageOffset);\r
+\r
+    testStatus = BoardDiag_spiEepromRunTest(pageOffset);\r
+    if(testStatus != 0)\r
+    {\r
+        UART_printf("\nSPI EEPROM Test Failed\n");\r
+        return -1;\r
+    }\r
+    else\r
+    {\r
+        UART_printf("\nSPI EEPROM Test Passed\n");\r
+    }\r
+    return testStatus;\r
 }\r
 \r
-/*\r
- *  ======== main ========\r
+/**\r
+ * \brief  main function\r
+ *\r
+ *  This function performs board intializations and calls spi test\r
+ *\r
+ * \return  int\r
+ *              0  - in case of success\r
+ *             -1  - in case of failure\r
  */\r
 int main(void)\r
 {\r
+    Board_STATUS status;\r
     Board_initCfg boardCfg;\r
+\r
 #ifdef PDK_RAW_BOOT\r
-    boardCfg = BOARD_INIT_PINMUX_CONFIG | \r
-        BOARD_INIT_UART_STDIO;\r
+    boardCfg = BOARD_INIT_MODULE_CLOCK  |\r
+               BOARD_INIT_PINMUX_CONFIG |\r
+               BOARD_INIT_UART_STDIO;\r
 #else\r
-    boardCfg = BOARD_INIT_UART_STDIO;\r
+    boardCfg = BOARD_INIT_UART_STDIO |\r
+               BOARD_INIT_PINMUX_CONFIG;\r
 #endif\r
-    Board_init(boardCfg);\r
 \r
-       return ioexp_spi_eeprom_test();\r
+    status = Board_init(boardCfg);\r
+    if(status != BOARD_SOK)\r
+    {\r
+        return -1;\r
+    }\r
+\r
+    return BoardDiag_spiEepromTest();\r
 }\r
diff --git a/packages/ti/board/diag/spi_eeprom/src/spi_eeprom_test.h b/packages/ti/board/diag/spi_eeprom/src/spi_eeprom_test.h
new file mode 100644 (file)
index 0000000..ea66be7
--- /dev/null
@@ -0,0 +1,104 @@
+/******************************************************************************
+ * Copyright (c) 2020 Texas Instruments Incorporated - http://www.ti.com
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *****************************************************************************/
+
+/**
+ * \file      spi_eeprom_test.h
+ *
+ * \brief     This file contains spi eeprom specific structure, typedefs,
+ *            function prototypes.
+ *
+ */
+
+#ifndef _SPI_EEPROM_TEST_H_
+#define _SPI_EEPROM_TEST_H_
+
+#include <stdlib.h>
+
+#include <ti/drv/spi/SPI.h>
+#include <ti/board/src/flash/include/board_flash.h>
+#include <ti/drv/spi/soc/SPI_soc.h>
+#include <ti/drv/uart/UART_stdio.h>
+
+#include <ti/csl/src/ip/mcspi/V0/mcspi.h>
+#include <ti/csl/src/ip/mcspi/V0/hw_mcspi.h>
+
+#include "board.h"
+#include "board_cfg.h"
+#include "diag_common_cfg.h"
+#include "soc.h"
+
+#ifdef DIAG_STRESS_TEST
+/* Total memory is 64 * 2 bytes is 128 bytes or 1Kb */
+#define BOARD_DIAG_MAX_BUFF_SIZE               (64U)
+#else
+#define BOARD_DIAG_MAX_BUFF_SIZE               (32U)
+#endif
+
+#define BOARD_DIAG_NOR_CMD_SECTOR_ERASE        (0x1C0U)
+#define BOARD_DIAG_NOR_CMD_ERASE_ALL           (0x120U)
+#define BOARD_DIAG_NOR_CMD_WREN                (0x130U)
+#define BOARD_DIAG_NOR_CMD_READ                (0x180U) /* Read opcode - 10, address trying to read is 0x0 */
+#define BOARD_DIAG_NOR_CMD_PAGE_PROG           (0x140U) /* Write opcode - 01, address is 0x0 */
+#define BOARD_DIAG_NOR_CMD_WRITE_ALL           (0x110U) /* Opcode - 00, LAst 4 bits are don't care */
+
+#define BOARD_DIAG_SPI0_BASE_ADDRESS           CSL_MCSPI0_CFG_BASE
+
+#define BOARD_DIAG_MCSPI_OUT_FREQ              (1000000U)
+#define BOARD_DIAG_MCSPI_IN_CLK                (48000000U)
+
+/**
+ * \brief  spi flash test function
+ *
+ *  This test executes SPI NOR flash memory access test and boundary test.
+ *  Memory access test can be verified using the erase, read and write commands
+ *  Boundary test can be verified by performing memory access test on first and last
+ *  pages of the memory.
+ *
+ * \return  int
+ *             0  - in case of success
+ *             -1  - in case of failure
+ */
+int BoardDiag_SpiFlashTest(void);
+
+/**
+ * \brief  spi test function
+ *
+ * This function executes spi flash test
+ *
+ * \return  int
+ *              0  - in case of success
+ *             -1  - in case of failure
+ */
+int BoardDiag_SpiTest(void);
+
+#endif // _SPI_EEPROM_TEST_H_