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raw | patch | inline | side by side (parent: e34ee48)
raw | patch | inline | side by side (parent: e34ee48)
author | sujith <sujith.s@ti.com> | |
Tue, 14 Jul 2020 22:54:49 +0000 (04:24 +0530) | ||
committer | Sivaraj R <sivaraj@ti.com> | |
Thu, 16 Jul 2020 09:44:32 +0000 (04:44 -0500) |
Signed-off-by: sujith <sujith.s@ti.com>
packages/ti/drv/spi/example/mcspi_slavemode/j7200/linker_mcu.lds | [new file with mode: 0644] | patch | blob |
packages/ti/drv/spi/example/mcspi_slavemode/j7200/linker_mcu_sysbios.lds | [new file with mode: 0644] | patch | blob |
packages/ti/drv/spi/example/mcspi_slavemode/makefile | patch | blob | history |
diff --git a/packages/ti/drv/spi/example/mcspi_slavemode/j7200/linker_mcu.lds b/packages/ti/drv/spi/example/mcspi_slavemode/j7200/linker_mcu.lds
--- /dev/null
@@ -0,0 +1,95 @@
+/* Linker Settings */
+--retain="*(.bootCode)"
+--retain="*(.startupCode)"
+--retain="*(.startupData)"
+--retain="*(.intvecs)"
+--retain="*(.intc_text)"
+--retain="*(.rstvectors)"
+--retain="*(.irqStack)"
+--retain="*(.fiqStack)"
+--retain="*(.abortStack)"
+--retain="*(.undStack)"
+--retain="*(.svcStack)"
+--fill_value=0
+--stack_size=0x2000
+--heap_size=0x1000
+--entry_point=_resetvectors /* Default C RTS boot.asm */
+
+-stack 0x2000 /* SOFTWARE STACK SIZE */
+-heap 0x2000 /* HEAP AREA SIZE */
+
+/* Stack Sizes for various modes */
+__IRQ_STACK_SIZE = 0x1000;
+__FIQ_STACK_SIZE = 0x1000;
+__ABORT_STACK_SIZE = 0x1000;
+__UND_STACK_SIZE = 0x1000;
+__SVC_STACK_SIZE = 0x1000;
+
+/* Memory Map */
+MEMORY
+{
+ VECTORS (X) : origin=0x41C7F000 length=0x1000
+ /* Reset Vectors base address(RESET_VECTORS) should be 64 bytes aligned */
+ RESET_VECTORS (X) : origin=0x41C00000 length=0x100
+ /* MCU0_R5F_0 local view */
+ MCU0_R5F_TCMA_SBL_RSVD (X) : origin=0x0 length=0x100
+ MCU0_R5F_TCMA (X) : origin=0x100 length=0x8000 - 0x100
+ MCU0_R5F_TCMB0 (RWIX) : origin=0x41010000 length=0x8000
+
+ /* MCU0_R5F_1 SoC view */
+ MCU0_R5F1_ATCM (RWIX) : origin=0x41400000 length=0x8000
+ MCU0_R5F1_BTCM (RWIX) : origin=0x41410000 length=0x8000
+
+ /* MCU0 share locations */
+ OCMRAM (RWIX) : origin=0x41C00100 length=0x80000 - 0x1100 /* ~510KB */
+
+ /* j7200 MCMS3 locations */
+ /* j7200 Reserved Memory for ARM Trusted Firmware */
+ MSMC3_ARM_FW (RWIX) : origin=0x70000000 length=0x40000 /* 256KB */
+ MSMC3 (RWIX) : origin=0x70040000 length=0xC0000
+
+ DDR0 (RWIX) : origin=0x80000000 length=0x80000000 /* 2GB */
+}
+
+/* Section Configuration */
+SECTIONS
+{
+ /* 'intvecs' and 'intc_text' sections shall be placed within */
+ /* a range of +\- 16 MB */
+ .intvecs : {} palign(8) > VECTORS
+ .intc_text : {} palign(8) > VECTORS
+ .rstvectors : {} palign(8) > RESET_VECTORS
+ .bootCode : {} palign(8) > OCMRAM
+ .startupCode : {} palign(8) > OCMRAM
+ .startupData : {} palign(8) > OCMRAM, type = NOINIT
+ .text : {} palign(8) > OCMRAM
+ .const : {} palign(8) > OCMRAM
+ .cinit : {} palign(8) > OCMRAM
+ .pinit : {} palign(8) > OCMRAM
+ .bss : {} align(4) > OCMRAM
+ .far : {} align(4) > OCMRAM
+ .data : {} palign(128) > OCMRAM
+ .boardcfg_data : {} palign(128) > OCMRAM
+ .sysmem : {} > OCMRAM
+ .data_buffer : {} palign(128) > OCMRAM
+
+ /* USB or any other LLD buffer for benchmarking */
+ .benchmark_buffer (NOLOAD) {} ALIGN (8) > OCMRAM
+
+ .stack : {} align(4) > OCMRAM (HIGH)
+ .irqStack : {. = . + __IRQ_STACK_SIZE;} align(4) > OCMRAM (HIGH)
+ RUN_START(__IRQ_STACK_START)
+ RUN_END(__IRQ_STACK_END)
+ .fiqStack : {. = . + __FIQ_STACK_SIZE;} align(4) > OCMRAM (HIGH)
+ RUN_START(__FIQ_STACK_START)
+ RUN_END(__FIQ_STACK_END)
+ .abortStack : {. = . + __ABORT_STACK_SIZE;} align(4) > OCMRAM (HIGH)
+ RUN_START(__ABORT_STACK_START)
+ RUN_END(__ABORT_STACK_END)
+ .undStack : {. = . + __UND_STACK_SIZE;} align(4) > OCMRAM (HIGH)
+ RUN_START(__UND_STACK_START)
+ RUN_END(__UND_STACK_END)
+ .svcStack : {. = . + __SVC_STACK_SIZE;} align(4) > OCMRAM (HIGH)
+ RUN_START(__SVC_STACK_START)
+ RUN_END(__SVC_STACK_END)
+}
diff --git a/packages/ti/drv/spi/example/mcspi_slavemode/j7200/linker_mcu_sysbios.lds b/packages/ti/drv/spi/example/mcspi_slavemode/j7200/linker_mcu_sysbios.lds
--- /dev/null
@@ -0,0 +1,39 @@
+/* linker options */
+--fill_value=0
+--stack_size=0x2000
+--heap_size=0x1000
+
+-e __VECS_ENTRY_POINT
+--retain="*(.utilsCopyVecsToAtcm)"
+
+MEMORY
+{
+ R5F_TCMA_SBL_RSVD(X): ORIGIN = 0x00000000 , LENGTH = 0x100
+ RESET_VECTORS(X) : ORIGIN = 0x41c40000 , LENGTH = 0x100 /* Bottom 256 KB used by SBL */
+ R5F_TCMB0(RWIX) : ORIGIN = 0x41010000 , LENGTH = 0x00008000
+ MSMC3(RWIX) : ORIGIN = 0x70040000 , LENGTH = 0xC0000
+ DDR0(RWIX) : ORIGIN = 0x80000000 , LENGTH = 0x80000000
+}
+
+SECTIONS
+{
+ .vecs : {
+ __VECS_ENTRY_POINT = .;
+ } palign(8) > RESET_VECTORS
+ .text_boot {
+ *boot.aer5f*<*boot.o*>(.text)
+ } palign(8) > R5F_TCMB0
+ .text:xdc_runtime_Startup_reset__I : {} palign(8) > R5F_TCMB0
+ .text:ti_sysbios_family_arm_v7r_Cache* : {} palign(8) > R5F_TCMB0
+ .text:ti_sysbios_family_arm_MPU* : {} palign(8) > R5F_TCMB0
+ .utilsCopyVecsToAtcm : {} palign(8) > R5F_TCMB0
+
+ .text : {} palign(8) > MSMC3
+ .cinit : {} palign(8) > MSMC3
+ .bss : {} align(8) > MSMC3
+ .far : {} align(8) > MSMC3
+ .const : {} palign(8) > MSMC3
+ .data : {} palign(128) > MSMC3
+ .sysmem : {} align(8) > MSMC3
+ .stack : {} align(4) > MSMC3
+}
diff --git a/packages/ti/drv/spi/example/mcspi_slavemode/makefile b/packages/ti/drv/spi/example/mcspi_slavemode/makefile
index 44cc1a9c5e19d4628f74e98f07947c56a2135b54..44442144ffe082d78088577130f0d53c40b57bce 100644 (file)
ifeq ($(SOC),$(filter $(SOC), j721e j7200))
# Slave uses local linker command file to avoid code/data memory conflict with master application
ifeq ($(IS_BAREMETAL),yes)
-EXTERNAL_LNKCMD_FILE_LOCAL = $(PDK_INSTALL_PATH)/ti/drv/spi/example/mcspi_slavemode/j721e/linker_mcu.lds
+EXTERNAL_LNKCMD_FILE_LOCAL = $(PDK_INSTALL_PATH)/ti/drv/spi/example/mcspi_slavemode/$(SOC)/linker_mcu.lds
else
-EXTERNAL_LNKCMD_FILE_LOCAL = $(PDK_INSTALL_PATH)/ti/drv/spi/example/mcspi_slavemode/j721e/linker_mcu_sysbios.lds
+EXTERNAL_LNKCMD_FILE_LOCAL = $(PDK_INSTALL_PATH)/ti/drv/spi/example/mcspi_slavemode/$(SOC)/linker_mcu_sysbios.lds
endif
endif