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raw | patch | inline | side by side (parent: e85bacf)
author | Prasad Konnur <prasadkonnur@ti.com> | |
Wed, 28 Oct 2020 17:15:36 +0000 (22:45 +0530) | ||
committer | Sivaraj R <sivaraj@ti.com> | |
Mon, 9 Nov 2020 10:59:28 +0000 (04:59 -0600) |
Signed-off-by: Prasad Konnur <prasadkonnur@ti.com>
diff --git a/packages/ti/drv/spi/example/mcspi_slavemode/j7200/linker_mcu_sysbios.lds b/packages/ti/drv/spi/example/mcspi_slavemode/j7200/linker_mcu_sysbios.lds
index 4a312cf8076078981593fd5cef8ec8d041668da2..3004dc79a584e6b60ec70d6d9d17cfa8aaef66e0 100755 (executable)
-e __VECS_ENTRY_POINT
--retain="*(.utilsCopyVecsToAtcm)"
+
MEMORY
{
R5F_TCMA_SBL_RSVD(X): ORIGIN = 0x00000000 , LENGTH = 0x100
+ RESET_VECTORS(X) : ORIGIN = 0x41c40000 , LENGTH = 0x100 /* Bottom 256 KB used by SBL */
R5F_TCMB0(RWIX) : ORIGIN = 0x41010000 , LENGTH = 0x00008000
-
- /* Refer the user guide for details on persistence of these sections */
- OCMC_RAM_BOARD_CFG (RWIX) : origin=0x41C80000 length=0x2000
- OCMC_RAM_SCISERVER (RWIX) : origin=0x41C82000 length=0x60000
- RESET_VECTORS (X) : origin=0x41CE2000 length=0x100
- OCMC_RAM (RWIX) : origin=0x41CE2100 length=0x1DA00
- OCMC_RAM_X509_HEADER (RWIX) : origin=0x41CFFB00 length=0x500
-
- MSMC3(RWIX) : ORIGIN = 0x70040000 , LENGTH = 0xC0000
- DDR0(RWIX) : ORIGIN = 0x80000000 , LENGTH = 0x80000000
+ DDR0(RWIX) : ORIGIN = 0x88000000 , LENGTH = 0x8000000
+ MSMC3 (RWIX) : ORIGIN = 0x70040000 , LENGTH = 0xB0000 /* 1MB - 320KB */
}
SECTIONS
.text:ti_sysbios_family_arm_MPU* : {} palign(8) > R5F_TCMB0
.utilsCopyVecsToAtcm : {} palign(8) > R5F_TCMB0
- .text : {} palign(8) > MSMC3
- .cinit : {} palign(8) > MSMC3
- .bss : {} align(8) > MSMC3
- .far : {} align(8) > MSMC3
- .const : {} palign(8) > MSMC3
- .data : {} palign(128) > MSMC3
- .sysmem : {} align(8) > MSMC3
- .stack : {} align(4) > MSMC3
- .bss.devgroup* : {} align(4) > DDR0
- .const.devgroup*: {} align(4) > DDR0
- .boardcfg_data : {} align(4) > DDR0
+ .text : {} palign(8) > DDR0
+ .cinit : {} palign(8) > DDR0
+ .bss : {} align(8) > DDR0
+ .far : {} align(8) > DDR0
+ .const : {} palign(8) > DDR0
+ .data : {} palign(128) > DDR0
+ .sysmem : {} align(8) > DDR0
+ .stack : {} align(4) > DDR0
+ .data_buffer: {} palign(128) > DDR0
+ .bss.devgroup*: {} align(4) > DDR0
+ .const.devgroup*: {} align(4) > DDR0
+ .boardcfg_data: {} align(4) > DDR0
+
+ /* USB or any other LLD buffer for benchmarking */
+ .benchmark_buffer: (NOLOAD) {} align (8) > DDR0
+
+
}
diff --git a/packages/ti/drv/spi/example/mcspi_slavemode/j721e/linker_mcu_sysbios.lds b/packages/ti/drv/spi/example/mcspi_slavemode/j721e/linker_mcu_sysbios.lds
index dc8b1e3aef49de8383f52f85cfb5e988265c1a8c..76ef5d9143d1376c33c90dd6284297bc074aed07 100755 (executable)
OCMC_RAM (RWIX) : origin=0x41CE2100 length=0x1DA00
OCMC_RAM_X509_HEADER (RWIX) : origin=0x41CFFB00 length=0x500
+ /* Donot use MSMC. Used by MPU. */
MSMC3(RWIX) : ORIGIN = 0x70080000 , LENGTH = 0x770000
- DDR0(RWIX) : ORIGIN = 0x80000000 , LENGTH = 0x80000000
+ DDR0(RWIX) : ORIGIN = 0x88000000 , LENGTH = 0x8000000
}
SECTIONS
.text:ti_sysbios_family_arm_MPU* : {} palign(8) > R5F_TCMB0
.utilsCopyVecsToAtcm : {} palign(8) > R5F_TCMB0
- .text : {} palign(8) > MSMC3
- .cinit : {} palign(8) > MSMC3
- .bss : {} align(8) > MSMC3
- .far : {} align(8) > MSMC3
- .const : {} palign(8) > MSMC3
- .data : {} palign(128) > MSMC3
- .sysmem : {} align(8) > MSMC3
- .stack : {} align(4) > MSMC3
+ .text : {} palign(8) > DDR0
+ .cinit : {} palign(8) > DDR0
+ .bss : {} align(8) > DDR0
+ .far : {} align(8) > DDR0
+ .const : {} palign(8) > DDR0
+ .data : {} palign(128) > DDR0
+ .sysmem : {} align(8) > DDR0
+ .stack : {} align(4) > DDR0
.data_buffer: {} palign(128) > DDR0
.bss.devgroup* : {} align(4) > DDR0
.const.devgroup*: {} align(4) > DDR0
diff --git a/packages/ti/drv/spi/example/mcspi_slavemode/makefile b/packages/ti/drv/spi/example/mcspi_slavemode/makefile
index 44442144ffe082d78088577130f0d53c40b57bce..7ec572c1b25f25fdb117a506c4eaab3c3902bcaa 100644 (file)
@@ -109,6 +109,12 @@ ifeq ($(BOARD),$(filter $(BOARD), am65xx_evm am65xx_idk j721e_sim j721e_evm j720
CFLAGS_SPI_UT = -DMCSPI_MULT_CHANNEL
endif
+ifeq ($(SOC),$(filter $(SOC), j721e j7200))
+ ifeq ($(CORE),mcu1_0)
+ COMP_LIST_COMMON += sciserver_tirtos
+ endif
+endif
+
PACKAGE_SRCS_COMMON = .
CFLAGS_LOCAL_COMMON = $(PDK_CFLAGS) $(CFLAGS_SPI_UT) $(CFLAGS_SPI_DMA) $(CFLAGS_SPI_MS) $(CFLAGS_OS_DEFINES)
diff --git a/packages/ti/drv/spi/example/mcspi_slavemode/src/main_mcspi_slave_mode.c b/packages/ti/drv/spi/example/mcspi_slavemode/src/main_mcspi_slave_mode.c
index c722c70a9ef7d2088f60121b26bd3cd70f2d70e1..6c71a06699423f790bdefccddc8e227e61c2dc8d 100644 (file)
#include <xdc/runtime/System.h>
#include <stdio.h>
#include <ti/sysbios/knl/Task.h>
+#include <ti/sysbios/hal/Hwi.h>
/* BIOS Header files */
#include <ti/sysbios/BIOS.h>
#endif
#endif
+#if (defined (SOC_J721E) || defined (SOC_J7200))
+#include <ti/drv/sciclient/sciclient.h>
+#if defined (BUILD_MCU1_0)
+#include <ti/drv/sciclient/sciserver_tirtos.h>
+/* Aligned address at which the X509 header is placed */
+#define SCISERVER_COMMON_X509_HEADER_ADDR (0x41cffb00)
+#endif
+#endif
+
/* Define the SPI test interface */
typedef struct SPI_Tests_s
{
#endif
{NULL, },
};
-
+#if defined (SOC_J721E) || defined (SOC_J7200)
+#define MCSPI_SYNC_ADDR (0x90000000U)
+#endif
/*
* ======== slaveTaskFxn ========
* The task is part of separate slave example project.
bool testFail = false;
SPI_Tests *test;
+ SPI_log("Starting SPI Slave test. \n");
+
SPI_init();
+#if defined (SOC_J721E) || defined (SOC_J7200)
+ *((volatile uint32_t *)(MCSPI_SYNC_ADDR)) = 0x12341234U;
+ CacheP_wb((void *)MCSPI_SYNC_ADDR, 4);
+#endif
+
for (i = 0; ; i++)
{
if (loopBackTest == true)
bool testFail = false;
SPI_Tests *test;
+ SPI_log("Starting SPI Master test. \n");
+
+#if defined (SOC_J721E) || defined (SOC_J7200)
+ while ( *((volatile uint32_t *)(MCSPI_SYNC_ADDR)) != 0x12341234U)
+ {
+ Task_yield();
+ /* wait for slave to start. */
+ CacheP_Inv((void *)MCSPI_SYNC_ADDR, 4);
+ }
+#endif
+
SPI_init();
for (i = 0; ; i++)
}
}
+#if (defined (USE_BIOS) && (defined (SOC_J721E) || defined (SOC_J7200)))
+#if defined (BUILD_MCU1_0)
+void MCSPI_setupSciServer(void)
+{
+
+ Sciserver_TirtosCfgPrms_t appPrms;
+ int32_t ret = CSL_PASS;
+
+ ret = Sciserver_tirtosInitPrms_Init(&appPrms);
+
+ appPrms.taskPriority[SCISERVER_TASK_USER_LO] =
+ 4;
+ appPrms.taskPriority[SCISERVER_TASK_USER_HI] =
+ 5;
+
+ if (ret == CSL_PASS)
+ {
+ ret = Sciserver_tirtosInit(&appPrms);
+ }
+
+ if (ret == CSL_PASS)
+ {
+ System_printf("Starting Sciserver..... PASSED\n");
+ }
+ else
+ {
+ System_printf("Starting Sciserver..... FAILED\n");
+ }
+
+ return;
+}
+#endif
+
+void MCSPI_initSciclient()
+{
+ int32_t ret = CSL_PASS;
+ Sciclient_ConfigPrms_t config;
+
+ /* Now reinitialize it as default parameter */
+ ret = Sciclient_configPrmsInit(&config);
+ if (ret != CSL_PASS)
+ {
+ System_printf("Sciclient_configPrmsInit Failed\n");
+ }
+
+#if defined (BUILD_MCU1_0)
+ if (ret == CSL_PASS)
+ {
+ ret = Sciclient_boardCfgParseHeader(
+ (uint8_t *)SCISERVER_COMMON_X509_HEADER_ADDR,
+ &config.inPmPrms, &config.inRmPrms);
+ if (ret != CSL_PASS)
+ {
+ System_printf("Sciclient_boardCfgParseHeader Failed\n");
+ }
+ }
+#endif
+
+ if (ret == CSL_PASS)
+ {
+ ret = Sciclient_init(&config);
+ if (ret != CSL_PASS)
+ {
+ System_printf("Sciclient_init Failed\n");
+ }
+ }
+}
+
+#endif
+
/*
* ======== main ========
*/
#endif /* Soc type */
#endif /* #ifdef USE_BIOS */
+#if (defined (USE_BIOS) && (defined (SOC_J721E) || defined (SOC_J7200)))
+#if defined (BUILD_MCU1_0)
+ MCSPI_setupSciServer();
+#endif
+ /* It must be called before board init */
+ MCSPI_initSciclient();
+#endif
+
#if defined(SOC_AM65XX) || defined(SOC_J721E) || defined(SOC_J7200)
/*
* For AM65XX/J721E/J7200, master and slave apps are
BOARD_INIT_MODULE_CLOCK |
BOARD_INIT_UART_STDIO;
#else
- boardCfg = BOARD_INIT_MODULE_CLOCK |
+ boardCfg = BOARD_INIT_PINMUX_CONFIG |
+ BOARD_INIT_MODULE_CLOCK |
BOARD_INIT_UART_STDIO;
#endif
#else