PRSDK-4441:am65xx: adding support for nimu-icss
authorTinku Mannan <tmannan@ti.com>
Wed, 4 Mar 2020 17:41:17 +0000 (12:41 -0500)
committerMahesh Radhakrishnan <a0875154@ti.com>
Thu, 5 Mar 2020 22:59:11 +0000 (16:59 -0600)
 library updates
 adding basic example and FTP example NDK NIMU-ICSS apps

Signed-off-by: Tinku Mannan <tmannan@ti.com>
packages/ti/transport/.gitignore
packages/ti/transport/ndk/nimu_icss/build/makefile_profile_indp.mk
packages/ti/transport/ndk/nimu_icss/example/am65xx/a53/bios/NIMU_ICSS_BasicExample_am65xx_evm_wSocLib_mpuExampleproject.txt [new file with mode: 0644]
packages/ti/transport/ndk/nimu_icss/example/am65xx/a53/bios/nimu_icss_arm_wSocLib.cfg [new file with mode: 0644]
packages/ti/transport/ndk/nimu_icss/example/ftpApp/am65xx/a53/bios/NIMU_ICSS_FtpExample_am65xx_evm_wSocLib_mpuExampleproject.txt [new file with mode: 0644]
packages/ti/transport/ndk/nimu_icss/example/src/main_a53.c [new file with mode: 0644]
packages/ti/transport/ndk/nimu_icss/nimu_icss_component.mk
packages/ti/transport/ndk/nimu_icss/package.xs
packages/ti/transport/ndk/nimu_icss/src/nimu_icssEthDriver.c
packages/ti/transport/ndk/nimu_icss/src/nimu_icssSwitchEmac.c

index 987590e7b213ef5f9a5165918fd121ce632162ec..4894fd7f37ffad308be471571d7d6877692049b0 100644 (file)
@@ -9,7 +9,7 @@ pacages
 .interfaces
 Settings.h
 Settings.xdc
-ndk/nimu_icss/example/*/*/bios
+ndk/nimu_icss/example/*/*/bios/src
 ndk/*/docs/doxygen/html
 timeSync/docs/doxygen/html
 timeSync/example/src/bios/ccsProjects/*/src/
index 8ba94071892486f41cc8744d65833ce7923467b8..6a7395e9926b9aa9385d30d47dd3fc18f63b806b 100644 (file)
@@ -41,7 +41,7 @@ CFLAGS_LOCAL_COMMON = $(PDK_CFLAGS) -DNDK_NOUSERAPIS
 INCLUDE_EXTERNAL_INTERFACES = xdc pdk ndk bios
 
 ifeq ($(BUILDTYPE),$(filter $(BUILDTYPE), profile profiledma))
-  ifeq ($(CORE),$(filter $(CORE), a15_0 a9host a8host))
+  ifeq ($(CORE),$(filter $(CORE), a15_0 a9host a8host mpu1_0))
     CFLAGS_LOCAL_COMMON += -finstrument-functions -gdwarf-3 -g -D_ENABLE_BM
   else
     CFLAGS_LOCAL_COMMON += --entry_parm=address --exit_hook=ti_utils_exit --exit_parm=address --entry_hook=ti_utils_entry -g -D_ENABLE_BM
diff --git a/packages/ti/transport/ndk/nimu_icss/example/am65xx/a53/bios/NIMU_ICSS_BasicExample_am65xx_evm_wSocLib_mpuExampleproject.txt b/packages/ti/transport/ndk/nimu_icss/example/am65xx/a53/bios/NIMU_ICSS_BasicExample_am65xx_evm_wSocLib_mpuExampleproject.txt
new file mode 100644 (file)
index 0000000..61c9e0a
--- /dev/null
@@ -0,0 +1,20 @@
+-ccs.linkFile "PDK_INSTALL_PATH/ti/transport/ndk/nimu_icss/example/src/main_a53.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/transport/ndk/nimu_icss/example/src/netHooks.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/transport/ndk/nimu_icss/example/src/osdrv_ndkdeviceconfig.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/uart/soc/am65xx/UART_soc.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/gpio/soc/am65xx/GPIO_soc.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/icss_emac/soc/am65xx/icss_emacSoc.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/icss_emac/test/am65xx/a53/bios/icss_emac_a53.lds"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/i2c/soc/am65xx/I2C_soc.c" 
+-ccs.linkFile "PDK_INSTALL_PATH\ti\osal\src\tirtos\TimerP_tirtos.c"
+
+-ccs.setCompilerOptions "-I${PDK_INSTALL_PATH}/ti/board/src/am65xx_idk/include"
+-ccs.setCompilerOptions "-I${PDK_INSTALL_PATH}/ti/csl"
+-ccs.setCompilerOptions "-I${PDK_INSTALL_PATH}/ti/board"
+
+-ccs.linkFile "PDK_INSTALL_PATH\ti\transport\ndk\nimu_icss\example\am65xx\a53\bios\nimu_icss_arm_wSocLib.cfg"
+
+-ccs.setCompilerOptions "-c -mcpu=cortex-a53+fp+simd -mabi=lp64 -mfix-cortex-a53-835769 -mfix-cortex-a53-843419 -mstrict-align -Wno-int-to-pointer-cast -Wno-pointer-to-int-cast -DSOC_AM65XX -Dam65xx_evm -DMEM_BARRIER_DISABLE -g -gstrict-dwarf -gdwarf-3  -Wall -MMD -MP -I${PDK_INSTALL_PATH}/ti/drv/icss_emac/src -I${PDK_INSTALL_PATH}/ti/drv/icss_emac -I${PDK_INSTALL_PATH}\ti\osal -I${PDK_INSTALL_PATH} "  -rtsc.enableRtsc
+-ccs.setLinkerOptions "-lrdimon -lgcc -lm -lnosys -nostartfiles -static --gc-sections -L${NDK_INSTALL_DIR}/packages/ti/ndk/os/lib"
+
+-rtsc.setConfiguroOptions "-b ${PDK_INSTALL_PATH}/ti/build/am65xx/config_am65xx_a53.bld -DBOARD=am65xx_evm"
diff --git a/packages/ti/transport/ndk/nimu_icss/example/am65xx/a53/bios/nimu_icss_arm_wSocLib.cfg b/packages/ti/transport/ndk/nimu_icss/example/am65xx/a53/bios/nimu_icss_arm_wSocLib.cfg
new file mode 100644 (file)
index 0000000..235620b
--- /dev/null
@@ -0,0 +1,264 @@
+
+/* =============================================================================
+ *   Copyright (c) Texas Instruments Incorporated 2018
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+var enableStaticIP         = 1;
+68
+
+var Defaults = xdc.useModule('xdc.runtime.Defaults');
+var Diags = xdc.useModule('xdc.runtime.Diags');
+var Error = xdc.useModule('xdc.runtime.Error');
+var Log = xdc.useModule('xdc.runtime.Log');
+var LoggerBuf = xdc.useModule('xdc.runtime.LoggerBuf');
+var Main = xdc.useModule('xdc.runtime.Main');
+var Memory = xdc.useModule('xdc.runtime.Memory')
+var System = xdc.useModule('xdc.runtime.System');
+var Text = xdc.useModule('xdc.runtime.Text');
+var Clock = xdc.useModule('ti.sysbios.knl.Clock');
+var Task = xdc.useModule('ti.sysbios.knl.Task');
+var Semaphore = xdc.useModule('ti.sysbios.knl.Semaphore');
+//var Timer = xdc.useModule('ti.sysbios.hal.Timer');
+
+var BIOS = xdc.useModule('ti.sysbios.BIOS');
+var Hwi = xdc.useModule('ti.sysbios.hal.Hwi');
+var HeapMem = xdc.useModule('ti.sysbios.heaps.HeapMem');
+var SysMin = xdc.useModule('xdc.runtime.SysMin');
+
+
+
+
+
+
+/* NDK modules */
+var Global          = xdc.useModule('ti.ndk.config.Global');
+var Ip              = xdc.useModule('ti.ndk.config.Ip');
+var Tcp             = xdc.useModule('ti.ndk.config.Tcp');
+var Udp             = xdc.useModule('ti.ndk.config.Udp');
+var Telnet          = xdc.useModule('ti.ndk.config.Telnet');
+
+Tcp.transmitBufSize    = 8192;
+Tcp.receiveBufSize     = 65536;
+Tcp.receiveBufLimit    = 65536;
+Global.pktNumFrameBufs = 384;
+
+
+Global.networkOpenHook = "&netOpenHook";
+Global.networkCloseHook = "&netCloseHook";
+
+if (enableStaticIP)
+{
+    /* Settings for static IP configuration */
+    Ip.ResolveIP = false;
+    Ip.CallByIP = false;
+    Ip.autoIp = false;
+    Ip.address = "192.168.2.3";
+    Ip.mask = "255.255.255.0";
+    Ip.gatewayIpAddr = "192.168.2.1";
+    Ip.ifIdx = 2;
+
+}
+else
+{
+    Ip.dhcpClientMode = Ip.CIS_FLG_IFIDXVALID;
+}
+Global.stackInitHook = "&stackInitHook";
+Global.ndkTickPeriod = 100;
+Global.kernTaskPriLevel = 11;
+Global.serviceReportHook = null;
+Global.IPv6 = false;
+
+
+/*NDK module end*/
+
+var Load                = xdc.useModule('ti.sysbios.utils.Load');
+/*
+ * CPU Load
+ */
+Load.swiEnabled = true;
+Load.hwiEnabled = true;
+Load.taskEnabled = true;
+
+
+var Uart                       = xdc.loadPackage('ti.drv.uart');
+
+
+var deviceType           = "am65xx";
+var Csl                = xdc.loadPackage('ti.csl');
+Csl.Settings.deviceType  = deviceType;
+
+
+
+
+/* Load the spi package */
+var socType          = "am65xx";
+var Spi              = xdc.loadPackage('ti.drv.spi');
+Spi.Settings.socType = socType;
+
+var I2c                        = xdc.loadPackage('ti.drv.i2c');
+//I2c.Settings.socType = socType;
+
+var Pruss                      = xdc.loadPackage('ti.drv.pruss');
+Pruss.Settings.socType = socType;
+
+/* SCICLIENT */
+//var socType                    = "am65xx";
+var SciClient                  = xdc.loadPackage('ti.drv.sciclient');
+SciClient.Settings.socType     = socType;
+
+
+var Gpio                       = xdc.loadPackage('ti.drv.gpio');
+Gpio.Settings.socType = socType;
+
+/* Disable Timer frequency check, workaround for QT test */
+var Timer = xdc.useModule('ti.sysbios.timers.dmtimer.Timer');
+Timer.checkFrequency = false;
+//Timer.Settings.socType = socType;
+
+
+
+/* Load the board package */
+var Board = xdc.loadPackage('ti.board');
+Board.Settings.boardName = "am65xx_idk";
+
+/* Load the ICSS_EMAC package */
+var Icss_Emac = xdc.loadPackage('ti.drv.icss_emac');
+Icss_Emac.Settings.enableProfiling = false;
+Icss_Emac.Settings.socType  = socType;
+
+
+/*Load the NIMU_ICSS package*/
+var Nimu_Icss  = xdc.loadPackage('ti.transport.ndk.nimu_icss');
+
+var Cache = xdc.module("ti.sysbios.hal.Cache");
+Cache.CacheProxy = xdc.useModule("ti.sysbios.family.arm.v8a.Cache");
+
+/* Load the OSAL package */ 
+var osType = "tirtos"
+var Osal = xdc.useModule('ti.osal.Settings');
+Osal.osType = osType;
+
+/*
+ * Direct CIO to UART
+ */
+/* System.SupportProxy = SysUart; */
+System.SupportProxy = SysMin;
+
+/*
+ * Program.argSize sets the size of the .args section.
+ * The examples don't use command line args so argSize is set to 0.
+ */
+Program.argSize = 0x0;
+
+/*
+ * Uncomment this line to globally disable Asserts.
+ * All modules inherit the default from the 'Defaults' module.  You
+ * can override these defaults on a per-module basis using Module.common$.
+ * Disabling Asserts will save code space and improve runtime performance.
+Defaults.common$.diags_ASSERT = Diags.ALWAYS_OFF;
+ */
+
+/*
+ * Uncomment this line to keep module names from being loaded on the target.
+ * The module name strings are placed in the .const section. Setting this
+ * parameter to false will save space in the .const section.  Error and
+ * Assert messages will contain an "unknown module" prefix instead
+ * of the actual module name.
+Defaults.common$.namedModule = false;
+ */
+
+
+/* Create default heap and hook it into Memory */
+var heapMemParams = new HeapMem.Params;
+heapMemParams.size = 16384*9*3;
+//heapMemParams.size = 3391500;
+var heap0 = HeapMem.create(heapMemParams);
+
+Memory.defaultHeapInstance = heap0;
+
+/*
+ * Minimize exit handler array in System.  The System module includes
+ * an array of functions that are registered with System_atexit() to be
+ * called by System_exit().
+ */
+System.maxAtexitHandlers = 4;
+
+/*
+ * Uncomment this line to disable the Error print function.
+ * We lose error information when this is disabled since the errors are
+ * not printed.  Disabling the raiseHook will save some code space if
+ * your app is not using System_printf() since the Error_print() function
+ * calls System_printf().
+Error.raiseHook = null;
+ */
+
+/*
+ * Uncomment this line to keep Error, Assert, and Log strings from being
+ * loaded on the target.  These strings are placed in the .const section.
+ * Setting this parameter to false will save space in the .const section.
+ * Error, Assert and Log message will print raw ids and args instead of
+ * a formatted message.
+Text.isLoaded = false;
+ */
+
+/*
+ * Uncomment this line to disable the output of characters by SysMin
+ * when the program exits.  SysMin writes characters to a circular buffer.
+ * This buffer can be viewed using the SysMin Output view in ROV.
+SysMin.flushAtExit = false;
+ */
+
+/* System stack size (used by ISRs and Swis) */
+Program.stack = 0x20000;
+
+Task.defaultStackSize = 0x8000;
+/* 
+ * Create and install logger for the whole system
+ */
+var loggerBufParams = new LoggerBuf.Params();
+loggerBufParams.numEntries = 32;
+var logger0 = LoggerBuf.create(loggerBufParams);
+Defaults.common$.logger = logger0;
+Main.common$.diags_INFO = Diags.ALWAYS_ON;
+
+BIOS.libType = BIOS.LibType_Custom;
+
+
+
+
+
+var Mmu = xdc.useModule('ti.sysbios.family.arm.v8a.Mmu');
+Mmu.tableArrayLen = 24;
+Mmu.initFunc = "&InitMmu";
+
+Program.sectMap[".ti_sysbios_family_arm_v8a_Mmu_tableArray"] = "MSMC_SRAM";
diff --git a/packages/ti/transport/ndk/nimu_icss/example/ftpApp/am65xx/a53/bios/NIMU_ICSS_FtpExample_am65xx_evm_wSocLib_mpuExampleproject.txt b/packages/ti/transport/ndk/nimu_icss/example/ftpApp/am65xx/a53/bios/NIMU_ICSS_FtpExample_am65xx_evm_wSocLib_mpuExampleproject.txt
new file mode 100644 (file)
index 0000000..d8c528b
--- /dev/null
@@ -0,0 +1,25 @@
+-ccs.linkFile "PDK_INSTALL_PATH/ti/transport/ndk/nimu_icss/example/src/main_a53.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/transport/ndk/nimu_icss/example/src/netHooks.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/transport/ndk/nimu_icss/example/src/osdrv_ndkdeviceconfig.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/transport/ndk/nimu/example/ftpApp/ftpserver/ftp_commands.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/transport/ndk/nimu/example/ftpApp/ftpserver/ftp_filerout.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/transport/ndk/nimu/example/ftpApp/ftpserver/ftpserver.c"
+
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/uart/soc/am65xx/UART_soc.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/gpio/soc/am65xx/GPIO_soc.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/icss_emac/soc/am65xx/icss_emacSoc.c"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/icss_emac/test/am65xx/a53/bios/icss_emac_a53.lds"
+-ccs.linkFile "PDK_INSTALL_PATH/ti/drv/i2c/soc/am65xx/I2C_soc.c" 
+
+-ccs.linkFile "PDK_INSTALL_PATH\ti\osal\src\tirtos\TimerP_tirtos.c"
+
+-ccs.setCompilerOptions "-I${PDK_INSTALL_PATH}/ti/board/src/am65xx_idk/include"
+-ccs.setCompilerOptions "-I${PDK_INSTALL_PATH}/ti/csl"
+-ccs.setCompilerOptions "-I${PDK_INSTALL_PATH}/ti/board"
+
+-ccs.linkFile "PDK_INSTALL_PATH\ti\transport\ndk\nimu_icss\example\am65xx\a53\bios\nimu_icss_arm_wSocLib.cfg"
+
+-ccs.setCompilerOptions "-c -mcpu=cortex-a53+fp+simd -mabi=lp64 -mfix-cortex-a53-835769 -mfix-cortex-a53-843419 -mstrict-align -Wno-int-to-pointer-cast -Wno-pointer-to-int-cast -DSOC_AM65XX -Dam65xx_evm -DNIMU_FTP_APP -DMEM_BARRIER_DISABLE -g -gstrict-dwarf -gdwarf-3  -Wall -MMD -MP -I${PDK_INSTALL_PATH}/ti/drv/icss_emac/src -I${PDK_INSTALL_PATH}/ti/drv/icss_emac -I${PDK_INSTALL_PATH}\ti\osal -I${PDK_INSTALL_PATH} "  -rtsc.enableRtsc
+-ccs.setLinkerOptions "-lrdimon -lgcc -lm -lnosys -nostartfiles -static --gc-sections -L${NDK_INSTALL_DIR}/packages/ti/ndk/os/lib"
+
+-rtsc.setConfiguroOptions "-b ${PDK_INSTALL_PATH}/ti/build/am65xx/config_am65xx_a53.bld -DBOARD=am65xx_evm"
\ No newline at end of file
diff --git a/packages/ti/transport/ndk/nimu_icss/example/src/main_a53.c b/packages/ti/transport/ndk/nimu_icss/example/src/main_a53.c
new file mode 100644 (file)
index 0000000..b7193d8
--- /dev/null
@@ -0,0 +1,965 @@
+/*
+ * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
+ * 
+ * 
+ *  Redistribution and use in source and binary forms, with or without 
+ *  modification, are permitted provided that the following conditions 
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright 
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the 
+ *    documentation and/or other materials provided with the   
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+
+#include <xdc/std.h>
+#include <xdc/runtime/Error.h>
+#include <xdc/runtime/System.h>
+#include <xdc/runtime/knl/Cache.h>
+
+#include <ti/sysbios/BIOS.h>
+#include <ti/sysbios/knl/Task.h>
+#include <ti/sysbios/hal/Core.h>
+
+#include <ti/csl/soc.h>
+#include <ti/drv/uart/UART_stdio.h>
+#include<ti/drv/pruss/soc/pruicss_v1.h>
+
+#include <ti/drv/icss_emac/icss_emacDrv.h>
+#include <ti/drv/icss_emac/soc/icss_emacSoc.h>
+
+#include<ti/drv/icss_emac/test/src/tiemac_pruss_intc_mapping.h>
+#include<ti/transport/ndk/nimu_icss/nimu_icssEth.h>
+#include<ti/transport/ndk/nimu_icss/example/src/osdrv_ndkdeviceconfig.h>
+
+#include <ti/drv/icss_emac/test/src/fw_mem_section.h>
+#include <ti\drv\icss_emac\firmware\icss_dualemac\bin\am65xx\a53_0\REV2\PRU0_bin.h>
+#include <ti\drv\icss_emac\firmware\icss_dualemac\bin\am65xx\a53_0\REV2\PRU1_bin.h>
+#include <ti/board/board.h>
+
+#define BOARD_ICSS_EMAC_APP_BOARDID_ADDR   (0x52U)
+#define BOARD_BOARD_NAME_LEN     (16U)
+
+PRUICSS_Handle pruIcssHandle;
+ICSS_EmacHandle emachandle;
+ICSS_EmacHandle emachandle1;
+uint8_t lclMac[6];
+uint8_t lclMac1[6];
+
+
+extern char *LocalIPAddr;
+extern ICSS_EmacBaseAddrCfgParams icss_EmacBaseAddrCfgParams[3];
+
+/* Static IP Address settings for Interface 0 */
+char *ipAddr      = "192.168.1.4";
+char *ipMask      = "255.255.255.0";
+char *ipGateway   = "192.168.1.1";
+
+/***********************************************************************/
+/* local functions declaration                                         */
+/***********************************************************************/
+uint8_t NIMU_ICSS_EmacTestDrvInit(ICSS_EmacHandle handle, uint8_t instance);
+void NIMU_ICSS_EmacTestGetPortMacAddr(uint32_t portNum, uint8_t *pMacAddr);
+void TaskFxn(UArg a0, UArg a1);
+/***********************************************************************/
+/* function definitions                                                */
+/***********************************************************************/
+
+/*
+ *    ---task to initialize PRU---
+ */
+Void NIMU_ICSS_EmacTestPruIcssInit(UArg a0, UArg a1)
+{
+    while(NIMU_ICSS_getNdkStatus(0)== NIMU_STAT_PROGRESS || NIMU_ICSS_getNdkStatus(0)==NIMU_STAT_UNKNOWN)
+    {
+        Task_sleep(100);
+    }
+    PRUICSS_pruDisable(pruIcssHandle, ICSS_EMAC_PORT_1-1);
+    PRUICSS_pruDisable(pruIcssHandle, ICSS_EMAC_PORT_2-1);
+
+
+    uint32_t result_flag = 0;
+    result_flag = (PRUICSS_pruWriteMemory(pruIcssHandle, PRU_ICSS_IRAM(0) , 0,
+                              (uint32_t *) PRU0_b00,
+                              sizeof(PRU0_b00)));
+    if(result_flag)
+    {
+        UART_printf("load to PRU0 passed\n");
+    }
+    else
+    {
+        UART_printf("load to PRU0 failed\n");
+    }
+    result_flag = (PRUICSS_pruWriteMemory(pruIcssHandle, PRU_ICSS_IRAM(1) , 0,
+                                  (uint32_t *) PRU1_b00,
+                                  sizeof(PRU1_b00)));
+    if(result_flag)
+    {
+        UART_printf("load to PRU1 passed\n");
+    }
+    else
+    {
+        UART_printf("load to PRU0 failed\n");
+    }
+
+    if( result_flag)
+    {
+        PRUICSS_pruEnable(pruIcssHandle, ICSS_EMAC_PORT_1-1);
+        PRUICSS_pruEnable(pruIcssHandle, ICSS_EMAC_PORT_2-1);
+    }
+
+}
+
+
+/*
+ *  ======== main ========
+ */
+int main()
+{
+    Error_Block eb;
+    Task_Params taskParams;
+    int32_t ret;
+    PRUICSS_Config  *pruIcssCfg;
+
+    Board_initCfg cfg;
+    memset(&cfg, 0, sizeof(Board_initCfg));
+    cfg = BOARD_INIT_UART_STDIO | BOARD_INIT_PINMUX_CONFIG | BOARD_INIT_MODULE_CLOCK | BOARD_INIT_ICSS_ETH_PHY | BOARD_INIT_ICSS_PINMUX;
+    Error_init(&eb);
+    Board_init(cfg);
+
+    ret  = PRUICSS_socGetInitCfg(&pruIcssCfg);
+    if (ret  != PRUICSS_RETURN_SUCCESS)
+        return (ret);
+    pruIcssHandle = PRUICSS_create((PRUICSS_Config*) pruIcssCfg,PRUICCSS_INSTANCE_TWO);
+    mii_init();
+
+    Board_STATUS status;
+    Board_IDInfo_v2 info = {0};
+    status = Board_getIDInfo_v2(&info, BOARD_ICSS_EMAC_APP_BOARDID_ADDR);
+
+    UART_printf("\r\nBoard info return status = %d ", status);
+    UART_printf("\r\nBoard Name           : ");
+    UART_dataWrite((char *)&info.boardInfo.boardName, BOARD_BOARD_NAME_LEN);
+    UART_printf("\r\nBuild Timestamp      : %s %s", __DATE__, __TIME__);
+
+    Task_Params_init(&taskParams);
+    taskParams.priority = 15;
+    taskParams.instance->name = "SwitchTask";
+    Task_create((Task_FuncPtr)NIMU_ICSS_EmacTestPruIcssInit, &taskParams, &eb);
+
+    /*Port I initializations*/
+    emachandle = (ICSS_EmacHandle)malloc(sizeof(ICSS_EmacConfig));
+
+    ICSS_EmacInitConfig* switchEmacCfg;
+    switchEmacCfg = (ICSS_EmacInitConfig*)malloc(sizeof(ICSS_EmacInitConfig));
+    if ((emachandle == NULL) || (switchEmacCfg == NULL))
+    {
+        UART_printf("main: malloc returned null\n");
+    }
+
+    switchEmacCfg->phyAddr[0]=0;
+    switchEmacCfg->portMask = ICSS_EMAC_MODE_MAC1;
+    switchEmacCfg->ethPrioQueue = ICSS_EMAC_QUEUE1;
+    switchEmacCfg->halfDuplexEnable = 1;
+    switchEmacCfg->enableIntrPacing = ICSS_EMAC_DISABLE_PACING;
+    switchEmacCfg->pacingThreshold = 100;
+    switchEmacCfg->learningEn = 0;
+    switchEmacCfg->rxIntNum = 294;
+    switchEmacCfg->linkIntNum=294+6;
+
+    //NIMU_ICSS_EmacTestGetPortMacAddr(0,lclMac);
+    memcpy(lclMac, &info.macInfo.macAddress[0], 6);
+    switchEmacCfg->macId = lclMac;
+
+    NIMU_ICSS_EmacTestDrvInit(emachandle, 2);     // ICSS_M instance 0
+
+    ((ICSS_EmacObject*)emachandle->object)->pruIcssHandle = pruIcssHandle;
+    ((ICSS_EmacObject*)emachandle->object)->emacInitcfg = switchEmacCfg;
+
+
+    /*PORT2 Initializations*/
+    emachandle1 = (ICSS_EmacHandle)malloc(sizeof(ICSS_EmacConfig));
+
+    ICSS_EmacInitConfig* switchEmacCfg1;
+    switchEmacCfg1 = (ICSS_EmacInitConfig*)malloc(sizeof(ICSS_EmacInitConfig));
+    if ((emachandle1 == NULL) || (switchEmacCfg1 == NULL))
+    {
+        UART_printf("main: malloc returned null\n");
+    }
+
+    switchEmacCfg1->phyAddr[0]=3;
+    switchEmacCfg1->portMask = ICSS_EMAC_MODE_MAC2;
+    switchEmacCfg1->ethPrioQueue = ICSS_EMAC_QUEUE3;
+    switchEmacCfg1->enableIntrPacing = ICSS_EMAC_DISABLE_PACING;
+    switchEmacCfg1->pacingThreshold = 100;
+    switchEmacCfg1->learningEn = 0;
+    switchEmacCfg1->rxIntNum = 295;
+    switchEmacCfg1->linkIntNum=295+6;
+
+    memcpy(lclMac1, &info.macInfo.macAddress[1], 6);
+    switchEmacCfg1->macId = lclMac1;
+
+    NIMU_ICSS_EmacTestDrvInit(emachandle1, 2);
+
+    ((ICSS_EmacObject*)emachandle1->object)->pruIcssHandle = pruIcssHandle;
+    ((ICSS_EmacObject*)emachandle1->object)->emacInitcfg = switchEmacCfg1;
+
+    PRUICSS_IntcInitData pruss_intc_initdata = PRUSS_INTC_INITDATA;
+    ICSS_EmacInit(emachandle,&pruss_intc_initdata,ICSS_EMAC_MODE_MAC1|ICSS_EMAC_MODE_DUALMAC);
+    ICSS_EmacInit(emachandle1,&pruss_intc_initdata,ICSS_EMAC_MODE_MAC2|ICSS_EMAC_MODE_DUALMAC);
+#if 1
+    Task_Params_init(&taskParams);
+    taskParams.priority = 10;
+    taskParams.instance->name = (char*)"port0_rxTaskFnc";
+    taskParams.stackSize = 0x1000;
+    taskParams.arg0 = (UArg)emachandle;
+
+    ((ICSS_EmacObject*)emachandle->object)->rxTaskHandle = Task_create((Task_FuncPtr)ICSS_EMacOsRxTaskFnc, &taskParams, NULL);
+
+    if(((ICSS_EmacObject*)emachandle->object)->rxTaskHandle==NULL)
+    {
+        return -2;
+    }
+    Task_Params_init(&taskParams);
+    taskParams.priority = 10;
+    taskParams.instance->name = (char*)"port0_linkTaskFnc";
+    taskParams.stackSize = 0x1000;
+    taskParams.arg0 = (UArg)emachandle;
+    ((ICSS_EmacObject*)emachandle->object)->linkTaskHandle = Task_create((Task_FuncPtr)ICSS_EMacOsLinkTaskFnc, &taskParams, NULL);
+
+    if(((ICSS_EmacObject*)emachandle->object)->linkTaskHandle==NULL)
+    {
+        return -2;
+    }
+
+    Task_Params_init(&taskParams);
+    taskParams.priority = 10;
+    taskParams.instance->name = (char*)"port1_rxTaskFnc";
+    taskParams.stackSize = 0x1000;
+    taskParams.arg0 = (UArg)emachandle1;
+    ((ICSS_EmacObject*)emachandle1->object)->rxTaskHandle = Task_create((Task_FuncPtr)ICSS_EMacOsRxTaskFnc, &taskParams, NULL);
+    if(((ICSS_EmacObject*)emachandle1->object)->rxTaskHandle==NULL)
+    {
+        return -2;
+    }
+
+    Task_Params_init(&taskParams);
+    taskParams.priority = 10;
+    taskParams.instance->name = (char*)"port1_linkTaskFnc";
+    taskParams.stackSize = 0x1000;
+    taskParams.arg0 = (UArg)emachandle1;
+    ((ICSS_EmacObject*)emachandle1->object)->linkTaskHandle = Task_create((Task_FuncPtr)ICSS_EMacOsLinkTaskFnc, &taskParams, NULL);
+
+
+    if(((ICSS_EmacObject*)emachandle1->object)->linkTaskHandle==NULL)
+    {
+        return -2;
+    }
+#endif
+
+    Task_Params_init(&taskParams);
+    taskParams.priority = 5;
+    taskParams.stackSize = 0x1400;
+    Task_create ((Task_FuncPtr)TaskFxn, &taskParams, NULL);
+
+    if(OSDRV_addNetifEntry((NIMUInitFn)&NIMU_ICSS_EmacInit,emachandle) == 0)
+        BIOS_exit(0);
+    if(OSDRV_addNetifEntry((NIMUInitFn)&NIMU_ICSS_EmacInit,emachandle1) == 0)
+            BIOS_exit(0);
+
+    BIOS_start();
+    return(0);
+}
+
+void NIMU_ICSS_EmacTestGetPortMacAddr(uint32_t portNum, uint8_t *pMacAddr)
+{
+    uint32_t tempVal;
+
+    if(portNum == 0)
+    {
+
+        tempVal = HW_RD_REG32(0x4A002518);
+        pMacAddr[0U] =  (uint8_t)((tempVal >> 16U) & 0xFFU);
+        pMacAddr[1U] =  (uint8_t)((tempVal >> 8U) & 0xFFU);
+        pMacAddr[2U] =  (uint8_t)(tempVal & 0xFFU);
+
+        tempVal = HW_RD_REG32(0x4A002514);
+        pMacAddr[3U] =  (uint8_t)((tempVal >> 16U) & 0xFFU);
+        pMacAddr[4U] =  (uint8_t)((tempVal >> 8U) & 0xFFU);
+        pMacAddr[5U] =  (uint8_t)(tempVal & 0xFFU);
+     }
+    else
+    {
+        tempVal = HW_RD_REG32(0x4A002520);
+        pMacAddr[0U] =  (uint8_t)((tempVal >> 16U) & 0xFFU);
+        pMacAddr[1U] =  (uint8_t)((tempVal >> 8U) & 0xFFU);
+        pMacAddr[2U] =  (uint8_t)(tempVal  & 0xFFU);
+
+        tempVal = HW_RD_REG32(0x4A00251c);
+        pMacAddr[3U] =  (uint8_t)((tempVal >> 16U) & 0xFFU);
+        pMacAddr[4U] =  (uint8_t)((tempVal >> 8U) & 0xFFU);
+        pMacAddr[5U] =  (uint8_t)(tempVal & 0xFFU);
+    }
+}
+
+
+int32_t ICSS_EMAC_testCallbackRxPacket2(void* queueNum, void* ICSS_EmacSubSysHandle)
+{
+    UART_printf("packet received by host");
+}
+
+int32_t ICSS_EMAC_testCallbackTxComplete(void* ICSS_EmacSubSysHandle, void* queueNum)
+{
+    UART_printf("packet transmitted by host");
+}
+
+uint8_t NIMU_ICSS_EmacTestDrvInit(ICSS_EmacHandle handle, uint8_t instance) {
+    uint8_t retVal = -1;
+
+    /* LLD attributes mallocs */
+    handle->object = (ICSS_EmacObject*)malloc(sizeof(ICSS_EmacObject));
+    handle->hwAttrs= (ICSS_EmacHwAttrs*)malloc(sizeof(ICSS_EmacHwAttrs));
+    memset(handle->object, 0, sizeof(ICSS_EmacObject));
+    memset(handle->hwAttrs, 0, sizeof(ICSS_EmacHwAttrs));
+
+    /* Callback mallocs */
+    ICSS_EmacCallBackObject* callBackObj = (ICSS_EmacCallBackObject*)malloc(sizeof(ICSS_EmacCallBackObject));
+    memset(callBackObj, 0, sizeof(ICSS_EmacCallBackObject));
+
+    callBackObj->learningExCallBack=(ICSS_EmacCallBackConfig*)malloc(sizeof(ICSS_EmacCallBackConfig));
+    callBackObj->rxRTCallBack=(ICSS_EmacCallBackConfig*)malloc(sizeof(ICSS_EmacCallBackConfig));
+    callBackObj->rxCallBack=(ICSS_EmacCallBackConfig*)malloc(sizeof(ICSS_EmacCallBackConfig));
+    callBackObj->txCallBack=(ICSS_EmacCallBackConfig*)malloc(sizeof(ICSS_EmacCallBackConfig));
+    callBackObj->rxCallBack->userArg=NULL;
+    memset(callBackObj->learningExCallBack, 0, sizeof(ICSS_EmacCallBackConfig));
+    memset(callBackObj->rxRTCallBack, 0, sizeof(ICSS_EmacCallBackConfig));
+    memset(callBackObj->rxCallBack, 0, sizeof(ICSS_EmacCallBackConfig));
+    memset(callBackObj->txCallBack, 0, sizeof(ICSS_EmacCallBackConfig));
+    ICSS_EmacRegisterHwIntTx(handle, (ICSS_EmacCallBack)ICSS_EMAC_testCallbackTxComplete);
+
+    ((ICSS_EmacObject*)handle->object)->callBackHandle = callBackObj;
+
+    /*Allocate memory for learning*/
+    ((ICSS_EmacObject*)handle->object)->macTablePtr = (HashTable_t*)malloc(NUM_PORTS * sizeof(HashTable_t));
+
+    /*Allocate memory for PRU Statistics*/
+    ((ICSS_EmacObject*)handle->object)->pruStat = (ICSS_EmacPruStatistics_t*)malloc(NUM_PORTS * sizeof(ICSS_EmacPruStatistics_t));
+
+    /*Allocate memory for Host Statistics*/
+    ((ICSS_EmacObject*)handle->object)->hostStat = (ICSS_EmacHostStatistics_t*)malloc(NUM_PORTS * sizeof(ICSS_EmacHostStatistics_t));
+
+    /*Allocate memory for Storm Prevention*/
+    ((ICSS_EmacObject*)handle->object)->stormPrevPtr = (stormPrevention_t*)malloc(NUM_PORTS * sizeof(stormPrevention_t));
+
+   // ICSS_EmacRegisterHwIntRx(handle, (ICSS_EmacCallBack)ICSS_EMAC_testCallbackRxPacket2);
+    //ICSS_EmacRegisterHwIntTx(handle, (ICSS_EmacCallBack)ICSS_EMAC_testCallbackTxComplete);
+    /* Base address initialization */
+    if(NULL == ((ICSS_EmacHwAttrs*)handle->hwAttrs)->emacBaseAddrCfg) {
+        ((ICSS_EmacHwAttrs*)handle->hwAttrs)->emacBaseAddrCfg =
+                        (ICSS_EmacBaseAddressHandle_T)malloc(sizeof(ICSS_EmacBaseAddrCfgParams));
+    }
+    ICSS_EmacBaseAddressHandle_T emacBaseAddr = ((ICSS_EmacHwAttrs*)handle->hwAttrs)->emacBaseAddrCfg;
+
+    ICSS_EmacSocGetInitCfg((instance-1), emacBaseAddr );
+
+    emacBaseAddr->l3OcmcBaseAddr =0x70100000;
+
+    ICSS_EmacSocSetInitCfg((instance-1), emacBaseAddr );
+
+    return retVal;
+}
+
+
+
+    /*
+     *  ======== TAskFxn: FTP server init task ========
+     */
+void TaskFxn(UArg a0, UArg a1)
+{
+    UART_printf("\n\rSYS/BIOS Ethernet/IP (NIMU_ICSS) Sample application, EVM IP address I/F 0: %s\n\r", ipAddr);
+    #ifdef NIMU_FTP_APP
+        ftpserver_init();
+    #endif
+
+        //while(1){
+            //ICSS_EmacPollControl(emachandle,7);
+            //Task_sleep(1);
+        //}
+
+}
+
+
+
+/*
+ * ======== stackInitHook ========
+ * hook called from ti_nkd_config_Global_stackThread() to run user setup code
+ */
+void stackInitHook(HANDLE hCfg)
+{
+    CI_IPNET NA;
+    CI_ROUTE RT;
+
+    /* Add IP address for interface 1 */
+    bzero(&NA, sizeof(NA));
+    NA.IPAddr = inet_addr(ipAddr);
+    NA.IPMask = inet_addr(ipMask);
+    CfgAddEntry(hCfg, CFGTAG_IPNET, 1, 0, sizeof(CI_IPNET),
+                (uint8_t *)&NA, 0);
+
+    /*
+     * Add gateway for interface 1
+     * --> I *think* the below should work but you may need different values ...
+     */
+    bzero(&RT, sizeof(RT));
+    RT.IPDestAddr = 0;
+    RT.IPDestMask = 0;
+    RT.IPGateAddr = inet_addr(ipGateway);
+
+    CfgAddEntry(hCfg, CFGTAG_ROUTE, 0, 0,
+                sizeof(CI_ROUTE), (uint8_t *)&RT, 0);
+}
+
+
+/**********************************************************************************************************/
+#include <ti/board/src/am65xx_idk/include/pinmux.h>
+#include <ti/board/src/am65xx_idk/am65xx_idk_pinmux.h>
+#include <ti/csl/src/ip/icss/V2/cslr_icss_g.h>
+#include <ti/sysbios/family/arm/v8a/Mmu.h>
+#include <ti/csl/csl_rat.h>
+int8_t Board_getPhyAddress(uint8_t instance, uint8_t portNumber);
+
+#define DPPHY_REGCR_REG         0x0D
+#define DPPHY_ADDR_REG          0x0E
+#define DPPHY_RGMIICTL          0x32
+#define DPPHY_GPIO_MUX_CTRL2    0x172
+#define EXT_REG_ADDRESS_ACCESS      0x001F
+#define EXT_REG_DATA_NORMAL_ACCESS  0x401F
+
+void mii_init()
+{
+    //MII pinmux
+    tiesc_mii_pinmuxConfig();
+    //Making the clock for ICSSG core and IEP same
+    (*((volatile uint32_t *)(CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_ICSSG0_CLKSEL))) |= 0x01;
+    (*((volatile uint32_t *)(CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_ICSSG1_CLKSEL))) |= 0x01;
+    (*((volatile uint32_t *)(CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_ICSSG2_CLKSEL))) |= 0x01;
+
+    /* Selecting MII-RT mode in GPCFG mux */
+    (*((volatile uint32_t *)((((PRUICSS_HwAttrs *)(pruIcssHandle->hwAttrs))->prussCfgRegBase) + CSL_ICSSCFG_GPCFG0))) = 0x8000003;
+    (*((volatile uint32_t *)((((PRUICSS_HwAttrs *)(pruIcssHandle->hwAttrs))->prussCfgRegBase) + CSL_ICSSCFG_GPCFG1))) = 0x8000003;
+
+    // ICSS_G_CFG make it MII
+    (*((volatile uint32_t *)((((PRUICSS_HwAttrs *)(pruIcssHandle->hwAttrs))->prussMiiRtCfgRegBase) + 0x1000 + CSL_ICSS_G_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_ICSS_G_CFG))) = (0x10001);
+
+    /* Setting up RX_ER/GPIO pin on the PHY as RX_ERR pin and COL/GPIO pin as LED_3 */
+    MDIO_phyExtRegWrite((((PRUICSS_HwAttrs *)(pruIcssHandle->hwAttrs))->prussMiiMdioRegBase), Board_getPhyAddress(PRUICCSS_INSTANCE_TWO, 1), DPPHY_GPIO_MUX_CTRL2, 0x60);
+    MDIO_phyExtRegWrite((((PRUICSS_HwAttrs *)(pruIcssHandle->hwAttrs))->prussMiiMdioRegBase), Board_getPhyAddress(PRUICCSS_INSTANCE_TWO, 2), DPPHY_GPIO_MUX_CTRL2, 0x60);
+
+    /* Disable RGMII interface */
+    MDIO_phyExtRegWrite((((PRUICSS_HwAttrs *)(pruIcssHandle->hwAttrs))->prussMiiMdioRegBase), Board_getPhyAddress(PRUICCSS_INSTANCE_TWO, 1), DPPHY_RGMIICTL, 0x50);
+    MDIO_phyExtRegWrite((((PRUICSS_HwAttrs *)(pruIcssHandle->hwAttrs))->prussMiiMdioRegBase), Board_getPhyAddress(PRUICCSS_INSTANCE_TWO, 2), DPPHY_RGMIICTL, 0x50);
+
+    PRUICSS_pinMuxConfig(pruIcssHandle, 0x0);   // PRUSS pinmuxing
+
+    /* I2C Init */
+    //Board_i2cLedInit();
+
+    /* Rotary Switch Init */
+    //Board_initRotarySwitch();
+
+    //QSPI_init();
+
+    CSL_ratRegs *pICSSGRat0Regs = (CSL_ratRegs *)((((PRUICSS_HwAttrs *)((
+                                      pruIcssHandle)->hwAttrs))->baseAddr) + CSL_ICSS_G_RAT_REGS_0_BASE);
+    CSL_ratRegs *pICSSGRat1Regs = (CSL_ratRegs *)((((PRUICSS_HwAttrs *)((
+                                      pruIcssHandle)->hwAttrs))->baseAddr) + CSL_ICSS_G_RAT_REGS_1_BASE);
+    CSL_RatTranslationCfgInfo TranslationCfg;
+
+    /*ICSSG RAT Entry 0 pointing to ICSSG_CROSS_PRU0_DMEM_CONST -> c15 */
+    TranslationCfg.sizeInBytes =
+            0xE2000;     // sizeInBytes
+    TranslationCfg.baseAddress =
+            (0xE0100000);//0x60000000;                            // c15 baseAddress
+    TranslationCfg.translatedAddress =
+            0x70100000;//cross_ICSSG_dmem0_offset;               // translatedAddress
+
+    CSL_ratEnableRegionTranslation(pICSSGRat0Regs, 0);
+    CSL_ratConfigRegionTranslation(pICSSGRat0Regs, 0, &TranslationCfg);
+
+    CSL_ratEnableRegionTranslation(pICSSGRat1Regs, 0);
+    CSL_ratConfigRegionTranslation(pICSSGRat1Regs, 0, &TranslationCfg);
+}
+
+
+
+//MII pin mux code
+#if 1
+static pinmuxPerCfg_t gPru_icssg0_mii_g_rt0PinCfg[] =
+{
+    /* MyPRU_ICSSG0_MII_G_RT1 -> pr0_mii_mt0_clk -> AC24 */
+    {
+        PIN_PRG0_PRU1_GPO16, PIN_MODE(1) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyPRU_ICSSG0_MII_G_RT1 -> pr0_mii0_txen -> AE27 */
+    {
+        PIN_PRG0_PRU1_GPO15, PIN_MODE(0) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
+    },
+    /* MyPRU_ICSSG0_MII_G_RT1 -> pr0_mii0_txd3 -> AD24 */
+    {
+        PIN_PRG0_PRU1_GPO14, PIN_MODE(0) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
+    },
+    /* MyPRU_ICSSG0_MII_G_RT1 -> pr0_mii0_txd2 -> AD25 */
+    {
+        PIN_PRG0_PRU1_GPO13, PIN_MODE(0) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
+    },
+    /* MyPRU_ICSSG0_MII_G_RT1 -> pr0_mii0_txd1 -> AC25 */
+    {
+        PIN_PRG0_PRU1_GPO12, PIN_MODE(0) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
+    },
+    /* MyPRU_ICSSG0_MII_G_RT1 -> pr0_mii0_txd0 -> AB24 */
+    {
+        PIN_PRG0_PRU1_GPO11, PIN_MODE(0) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
+    },
+    /* MyPRU_ICSSG0_MII_G_RT1 -> pr0_mii0_rxdv -> Y24 */
+    {
+        PIN_PRG0_PRU0_GPO4, PIN_MODE(1) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyPRU_ICSSG0_MII_G_RT1 -> pr0_mii_mr0_clk -> Y25 */
+    {
+        PIN_PRG0_PRU0_GPO6, PIN_MODE(1) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyPRU_ICSSG0_MII_G_RT1 -> pr0_mii0_rxd3 -> AA27 */
+    {
+        PIN_PRG0_PRU0_GPO3, PIN_MODE(1) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyPRU_ICSSG0_MII_G_RT1 -> pr0_mii0_rxd2 -> W24 */
+    {
+        PIN_PRG0_PRU0_GPO2, PIN_MODE(1) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyPRU_ICSSG0_MII_G_RT1 -> pr0_mii0_rxer -> V28 */
+    {
+        PIN_PRG0_PRU0_GPO5, PIN_MODE(1) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyPRU_ICSSG0_MII_G_RT1 -> pr0_mii0_rxd1 -> W25 */
+    {
+        PIN_PRG0_PRU0_GPO1, PIN_MODE(1) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyPRU_ICSSG0_MII_G_RT1 -> pr0_mii0_rxd0 -> V24 */
+    {
+        PIN_PRG0_PRU0_GPO0, PIN_MODE(1) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyPRU_ICSSG0_MII_G_RT1 -> pr0_mii0_rxlink -> V27 */
+    {
+        PIN_PRG0_PRU0_GPO8, PIN_MODE(1) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyPRU_ICSSG0_MII_G_RT1 -> pr0_mii_mt1_clk -> AD28 */
+    {
+        PIN_PRG0_PRU0_GPO16, PIN_MODE(1) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyPRU_ICSSG0_MII_G_RT1 -> pr0_mii1_txen -> AA24 */
+    {
+        PIN_PRG0_PRU0_GPO15, PIN_MODE(0) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
+    },
+    /* MyPRU_ICSSG0_MII_G_RT1 -> pr0_mii1_txd3 -> AD26 */
+    {
+        PIN_PRG0_PRU0_GPO14, PIN_MODE(0) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
+    },
+    /* MyPRU_ICSSG0_MII_G_RT1 -> pr0_mii1_txd2 -> AC26 */
+    {
+        PIN_PRG0_PRU0_GPO13, PIN_MODE(0) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
+    },
+    /* MyPRU_ICSSG0_MII_G_RT1 -> pr0_mii1_txd1 -> AD27 */
+    {
+        PIN_PRG0_PRU0_GPO12, PIN_MODE(0) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
+    },
+    /* MyPRU_ICSSG0_MII_G_RT1 -> pr0_mii1_txd0 -> AB25 */
+    {
+        PIN_PRG0_PRU0_GPO11, PIN_MODE(0) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
+    },
+    /* MyPRU_ICSSG0_MII_G_RT1 -> pr0_mii1_rxdv -> AA25 */
+    {
+        PIN_PRG0_PRU1_GPO4, PIN_MODE(1) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyPRU_ICSSG0_MII_G_RT1 -> pr0_mii_mr1_clk -> AB27 */
+    {
+        PIN_PRG0_PRU1_GPO6, PIN_MODE(1) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyPRU_ICSSG0_MII_G_RT1 -> pr0_mii1_rxd3 -> AB26 */
+    {
+        PIN_PRG0_PRU1_GPO3, PIN_MODE(1) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyPRU_ICSSG0_MII_G_RT1 -> pr0_mii1_rxd2 -> AC27 */
+    {
+        PIN_PRG0_PRU1_GPO2, PIN_MODE(1) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyPRU_ICSSG0_MII_G_RT1 -> pr0_mii1_rxer -> U23 */
+    {
+        PIN_PRG0_PRU1_GPO5, PIN_MODE(1) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyPRU_ICSSG0_MII_G_RT1 -> pr0_mii1_rxd1 -> AC28 */
+    {
+        PIN_PRG0_PRU1_GPO1, PIN_MODE(1) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyPRU_ICSSG0_MII_G_RT1 -> pr0_mii1_rxd0 -> AB28 */
+    {
+        PIN_PRG0_PRU1_GPO0, PIN_MODE(1) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyPRU_ICSSG0_MII_G_RT1 -> pr0_mii1_rxlink -> W27 */
+    {
+        PIN_PRG0_PRU1_GPO8, PIN_MODE(1) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    {PINMUX_END}
+};
+
+static pinmuxModuleCfg_t gPru_icssg0_mii_g_rtPinCfg[] =
+{
+    {0, TRUE, gPru_icssg0_mii_g_rt0PinCfg},
+    {PINMUX_END}
+};
+
+
+static pinmuxPerCfg_t gPru_icssg1_mii_g_rt0PinCfg[] =
+{
+    /* MyPRU_ICSSG1_MII_G_RT1 -> pr1_mii_mt0_clk -> AE19 */
+    {
+        PIN_PRG1_PRU1_GPO16, PIN_MODE(1) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyPRU_ICSSG1_MII_G_RT1 -> pr1_mii0_txen -> AG19 */
+    {
+        PIN_PRG1_PRU1_GPO15, PIN_MODE(0) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
+    },
+    /* MyPRU_ICSSG1_MII_G_RT1 -> pr1_mii0_txd3 -> AH19 */
+    {
+        PIN_PRG1_PRU1_GPO14, PIN_MODE(0) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
+    },
+    /* MyPRU_ICSSG1_MII_G_RT1 -> pr1_mii0_txd2 -> AF19 */
+    {
+        PIN_PRG1_PRU1_GPO13, PIN_MODE(0) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
+    },
+    /* MyPRU_ICSSG1_MII_G_RT1 -> pr1_mii0_txd1 -> AE20 */
+    {
+        PIN_PRG1_PRU1_GPO12, PIN_MODE(0) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
+    },
+    /* MyPRU_ICSSG1_MII_G_RT1 -> pr1_mii0_txd0 -> AC20 */
+    {
+        PIN_PRG1_PRU1_GPO11, PIN_MODE(0) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
+    },
+    /* MyPRU_ICSSG1_MII_G_RT1 -> pr1_mii0_rxdv -> AG23 */
+    {
+        PIN_PRG1_PRU0_GPO4, PIN_MODE(1) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyPRU_ICSSG1_MII_G_RT1 -> pr1_mii_mr0_clk -> AF22 */
+    {
+        PIN_PRG1_PRU0_GPO6, PIN_MODE(1) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyPRU_ICSSG1_MII_G_RT1 -> pr1_mii0_rxd3 -> AD21 */
+    {
+        PIN_PRG1_PRU0_GPO3, PIN_MODE(1) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyPRU_ICSSG1_MII_G_RT1 -> pr1_mii0_rxd2 -> AF23 */
+    {
+        PIN_PRG1_PRU0_GPO2, PIN_MODE(1) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyPRU_ICSSG1_MII_G_RT1 -> pr1_mii0_rxer -> AF27 */
+    {
+        PIN_PRG1_PRU0_GPO5, PIN_MODE(1) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyPRU_ICSSG1_MII_G_RT1 -> pr1_mii0_rxd1 -> AG24 */
+    {
+        PIN_PRG1_PRU0_GPO1, PIN_MODE(1) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyPRU_ICSSG1_MII_G_RT1 -> pr1_mii0_rxd0 -> AE22 */
+    {
+        PIN_PRG1_PRU0_GPO0, PIN_MODE(1) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyPRU_ICSSG1_MII_G_RT1 -> pr1_mii0_rxlink -> AF28 */
+    {
+        PIN_PRG1_PRU0_GPO8, PIN_MODE(1) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyPRU_ICSSG1_MII_G_RT1 -> pr1_mii_mt1_clk -> AD20 */
+    {
+        PIN_PRG1_PRU0_GPO16, PIN_MODE(1) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyPRU_ICSSG1_MII_G_RT1 -> pr1_mii1_txen -> AD19 */
+    {
+        PIN_PRG1_PRU0_GPO15, PIN_MODE(0) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
+    },
+    /* MyPRU_ICSSG1_MII_G_RT1 -> pr1_mii1_txd3 -> AG20 */
+    {
+        PIN_PRG1_PRU0_GPO14, PIN_MODE(0) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
+    },
+    /* MyPRU_ICSSG1_MII_G_RT1 -> pr1_mii1_txd2 -> AH21 */
+    {
+        PIN_PRG1_PRU0_GPO13, PIN_MODE(0) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
+    },
+    /* MyPRU_ICSSG1_MII_G_RT1 -> pr1_mii1_txd1 -> AH20 */
+    {
+        PIN_PRG1_PRU0_GPO12, PIN_MODE(0) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
+    },
+    /* MyPRU_ICSSG1_MII_G_RT1 -> pr1_mii1_txd0 -> AF21 */
+    {
+        PIN_PRG1_PRU0_GPO11, PIN_MODE(0) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
+    },
+    /* MyPRU_ICSSG1_MII_G_RT1 -> pr1_mii1_rxdv -> AE21 */
+    {
+        PIN_PRG1_PRU1_GPO4, PIN_MODE(1) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyPRU_ICSSG1_MII_G_RT1 -> pr1_mii_mr1_clk -> AG22 */
+    {
+        PIN_PRG1_PRU1_GPO6, PIN_MODE(1) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyPRU_ICSSG1_MII_G_RT1 -> pr1_mii1_rxd3 -> AH22 */
+    {
+        PIN_PRG1_PRU1_GPO3, PIN_MODE(1) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyPRU_ICSSG1_MII_G_RT1 -> pr1_mii1_rxd2 -> AG21 */
+    {
+        PIN_PRG1_PRU1_GPO2, PIN_MODE(1) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyPRU_ICSSG1_MII_G_RT1 -> pr1_mii1_rxer -> AC22 */
+    {
+        PIN_PRG1_PRU1_GPO5, PIN_MODE(1) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyPRU_ICSSG1_MII_G_RT1 -> pr1_mii1_rxd1 -> AH23 */
+    {
+        PIN_PRG1_PRU1_GPO1, PIN_MODE(1) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyPRU_ICSSG1_MII_G_RT1 -> pr1_mii1_rxd0 -> AH24 */
+    {
+        PIN_PRG1_PRU1_GPO0, PIN_MODE(1) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyPRU_ICSSG1_MII_G_RT1 -> pr1_mii1_rxlink -> AE24 */
+    {
+        PIN_PRG1_PRU1_GPO8, PIN_MODE(1) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    {PINMUX_END}
+};
+
+static pinmuxModuleCfg_t gPru_icssg1_mii_g_rtPinCfg[] =
+{
+    {0, TRUE, gPru_icssg1_mii_g_rt0PinCfg},
+    {PINMUX_END}
+};
+
+pinmuxBoardCfg_t gAM65xxMIIPinmuxData[] =
+{
+    {0, gPru_icssg0_mii_g_rtPinCfg},
+    {1, gPru_icssg1_mii_g_rtPinCfg},
+    {PINMUX_END}
+};
+
+void tiesc_mii_pinmuxConfig (void)
+{
+    pinmuxModuleCfg_t* pModuleData = NULL;
+    pinmuxPerCfg_t* pInstanceData = NULL;
+    int32_t i, j, k;
+    uint32_t rdRegVal;
+
+    for(i = 0; PINMUX_END != gAM65xxMIIPinmuxData[i].moduleId; i++)
+    {
+        pModuleData = gAM65xxMIIPinmuxData[i].modulePinCfg;
+        for(j = 0; (PINMUX_END != pModuleData[j].modInstNum); j++)
+        {
+            if(pModuleData[j].doPinConfig == TRUE)
+            {
+                pInstanceData = pModuleData[j].instPins;
+                for(k = 0; (PINMUX_END != pInstanceData[k].pinOffset); k++)
+                {
+                    rdRegVal = HW_RD_REG32((MAIN_PMUX_CTRL + pInstanceData[k].pinOffset));
+                    rdRegVal = (rdRegVal & PINMUX_BIT_MASK);
+                    HW_WR_REG32((MAIN_PMUX_CTRL + pInstanceData[k].pinOffset),
+                                (pInstanceData[k].pinSettings));
+                }
+            }
+        }
+    }
+
+    return;
+}
+#endif
+
+
+//board setting related API's
+int8_t Board_getPhyAddress(uint8_t instance, uint8_t portNumber)
+{
+    if(1u == portNumber)
+    {
+        return 0;
+    }
+
+    else if(2u == portNumber)
+    {
+        return 3;
+    }
+}
+
+void MDIO_phyExtRegWrite(uint32_t mdioBaseAddress, uint32_t phyNum,
+                         uint32_t regNum, uint16_t phyregval)
+{
+    CSL_MDIO_phyRegWrite(mdioBaseAddress, phyNum, DPPHY_REGCR_REG,
+                         EXT_REG_ADDRESS_ACCESS);
+    CSL_MDIO_phyRegWrite(mdioBaseAddress, phyNum, DPPHY_ADDR_REG, regNum);
+    CSL_MDIO_phyRegWrite(mdioBaseAddress, phyNum, DPPHY_REGCR_REG,
+                         EXT_REG_DATA_NORMAL_ACCESS);
+    CSL_MDIO_phyRegWrite(mdioBaseAddress, phyNum, DPPHY_ADDR_REG, phyregval);
+    return;
+}
+
+//mmu configuration
+#if defined (__aarch64__)
+struct MmuCfg_t
+{
+    uint64_t    vaddr;
+    uint64_t    paddr;
+    size_t      size;
+    int         attrInd;
+} MmuCfgTbl[] =
+{
+    { 0x00100000, 0x00100000, 0x00900000, 0 }, /* Main MMR0     */
+    { 0x00400000, 0x00400000, 0x00001000, 0 }, /* PSC0          */
+    { 0x00A40000, 0x00A40000, 0x00001000, 0 }, /* TimeSyncRouter     */
+    { 0x01800000, 0x01800000, 0x00100000, 0 }, /* gicv3         */
+    { 0x02400000, 0x02400000, 0x000c0000, 0 }, /* dmtimer       */
+    { 0x02800000, 0x02800000, 0x00001000, 0 }, /* uart          */
+    { 0x02000000, 0x02000000, 0x00100000, 0 }, /* I2C           */
+    { 0x02100000, 0x02100000, 0x00080000, 0 }, /* McSPI         */
+    { 0x40F00000, 0x40F00000, 0x00020000, 0 }, /* MCU MMR0      */
+    { 0x40d00000, 0x40d00000, 0x00002000, 0 }, /* PLL0          */
+    { 0x47000000, 0x47000000, 0x00100000, 0 }, /* FSS0 cfg          */
+    { 0x400000000, 0x400000000, 0x400000000, 0 }, /* FSS0 data          */
+    { 0x40f90000, 0x40f90000, 0x00001000, 0 }, /* RAT cfg          */
+    { 0x42120000, 0x42120000, 0x00001000, 0 }, /* WKUP I2C0     */
+    { 0x43000000, 0x43000000, 0x00020000, 0 }, /* WKUP MMR0     */
+    { 0x02C40000, 0x02C40000, 0x00100000, 0 }, /* pinmux ctrl   */
+    { 0x30800000, 0x30800000, 0x0C000000, 0 }, /* main navss    */
+    { 0x28380000, 0x28380000, 0x03880000, 0 }, /* mcu navss     */
+    { 0x30000000, 0x30000000, 0x0F000000, 0 }, /* ctrcontrol0   */
+   // { 0x01000000, 0x01000000, 0x00400000, 0 }, /* GIC0 ITS   */
+    //{ 0x02a22000, 0x02a22000, 0x00000400, 0 }, /* GIC0 AGGR   */
+    {
+        CSL_MCU_CPSW0_NUSS_BASE, CSL_MCU_CPSW0_NUSS_BASE,
+        (CSL_MCU_CPSW0_NUSS_SIZE * 2), 0
+    },      /* for CPSW      */
+    { 0x0b000000, 0x0b000000, 0x00100000, 0 }, /* ICSS-G 0      */
+    { 0x0b100000, 0x0b100000, 0x00100000, 0 }, /* ICSS-G 1      */
+    { 0x0b200000, 0x0b200000, 0x00100000, 0 }, /* ICSS-G 2      */
+    { 0x42000000, 0x42000000, 0x00001000, 0 }, /* PSC WKUP      */
+    { 0x03802000, 0x03802000, 0x00001000, 0 }, /* NB0_CFG_MMRS  */
+    { 0x70000000, 0x70000000, 0x04000000, 7 }, /* msmc          */
+    { 0x41C00000, 0x41C00000, 0x00080000, 7 }, /* ocmc          */
+    { 0x80000000, 0x80000000, 0x10000000, 7 }, /* ddr_0          */
+    { 0, 0, 0, 8 } /* attrInd = 8 -> end of table */
+};
+
+void InitMmu(void)
+{
+    bool        retVal = FALSE;
+    uint32_t    j = 0;
+    Mmu_MapAttrs attrs;
+    Mmu_initMapAttrs(&attrs);
+
+    while(MmuCfgTbl[j].attrInd < 8)
+    {
+        attrs.attrIndx = MmuCfgTbl[j].attrInd;
+        retVal = Mmu_map(MmuCfgTbl[j].vaddr, MmuCfgTbl[j].paddr, MmuCfgTbl[j].size,
+                         &attrs);
+
+        if(retVal == FALSE)
+        {
+            break;
+        }
+
+        j++;
+    }
+
+    if(retVal == FALSE)
+    {
+        UART_printf("Mmu_map idx %d returned error %d", j, retVal);
+
+        while(1);
+    }
+}
+#endif // __aarch64__
+
+/**********************************************************************************************************/
index 67ac55758f39a31e80c25b7b5879d5ebd7924e43..ebdd85397da919be74f1a3c35ee31e0d509fcc07 100644 (file)
@@ -68,14 +68,14 @@ ifeq ($(nimu_icss_component_make_include), )
 
 # under other list
 drvnimu_icss_BOARDLIST       = 
-drvnimu_icss_SOCLIST         = am335x am437x am574x am572x am571x k2g
+drvnimu_icss_SOCLIST         = am335x am437x am574x am572x am571x k2g am65xx
 drvnimu_icss_am574x_CORELIST = c66x a15_0 ipu1_0
 drvnimu_icss_am572x_CORELIST = c66x a15_0 ipu1_0
 drvnimu_icss_am571x_CORELIST = c66x a15_0 ipu1_0
 drvnimu_icss_am437x_CORELIST = a9host
 drvnimu_icss_am335x_CORELIST = a8host
 drvnimu_icss_k2g_CORELIST    = c66x a15_0
-
+drvnimu_icss_am65xx_CORELIST = mpu1_0 mcu1_0
 ############################
 # uart package
 # List of components included under uart lib
index 221582b3bbe961ca0345dc5125b642d63e24dfcc..9e6724a5e86d2a669898a77dd0ee7e8960dd2142 100644 (file)
@@ -39,6 +39,10 @@ function getLibs(prog)
         lib = lib + "/a9";\r
     else if (java.lang.String(suffix).contains('a8') )\r
         lib = lib + "/a8";        \r
+    else if (java.lang.String(suffix).contains('a53') )\r
+        lib = lib + "/a53";\r
+    else if (java.lang.String(suffix).contains('r5f') )\r
+        lib = lib + "/r5f";\r
     else\r
         throw new Error("\tUnknown target for: " + this.packageBase + lib);\r
    \r
index c6b857beeff091517d12b6f1bb6a8dad241411b7..728c1ac319f49a5252f7147628e816c4f62eb4bf 100644 (file)
@@ -95,7 +95,7 @@ void NIMU_ICSS_interruptEnd(NIMU_IcssPdInfo* pi)
 * @retval none
 */
 int32_t NIMU_ICSS_interruptInit(NIMU_IcssPdInfo* pi); /* misra warning */
-#if defined (__ARM_ARCH_7A__) || defined (__TI_ARM_V7M4__)
+#if defined (__ARM_ARCH_7A__) || defined (__TI_ARM_V7M4__) || defined(__aarch64__) || defined(__TI_ARM_V7R4__)
 int32_t NIMU_ICSS_interruptInit(NIMU_IcssPdInfo* pi)
 {
     int32_t retVal = 0;
@@ -230,7 +230,7 @@ void NIMU_ICSS_interruptDisable(NIMU_IcssPdInfo * pi)
     ICSS_EmacHandle handle = pi->nimuDrvHandle;
     key = ICSS_EMAC_osalHardwareIntDisable();
 
-#if defined (__ARM_ARCH_7A__) || defined (__TI_ARM_V7M4__)
+#if defined (__ARM_ARCH_7A__) || defined (__TI_ARM_V7M4__) || defined(__aarch64__) || defined(__TI_ARM_V7R4__)
     ICSS_EMAC_osalHardwareInterruptDisable((((ICSS_EmacObject*)handle->object)->emacInitcfg)->linkIntNum);
     ICSS_EMAC_osalHardwareInterruptDisable((((ICSS_EmacObject*)handle->object)->emacInitcfg)->rxIntNum);
 
@@ -257,8 +257,7 @@ void NIMU_ICSS_interruptDisable(NIMU_IcssPdInfo * pi)
 static void EnableEMACInterrupts(NIMU_IcssPdInfo * pi); /* misra warning */
 static void EnableEMACInterrupts(NIMU_IcssPdInfo * pi)
 {
-
-#if defined (__ARM_ARCH_7A__) || defined (__TI_ARM_V7M4__)
+#if defined (__ARM_ARCH_7A__) || defined (__TI_ARM_V7M4__) || defined(__aarch64__) || defined(__TI_ARM_V7R4__)
     uint32_t key = 0;
 
     ICSS_EmacHandle handle = pi->nimuDrvHandle;
index 75c6f33ae693a00ab9dd948194ad53fc1d721322..4aeec41381e760b2b8906c4da34971bfeb7bcf45 100644 (file)
@@ -42,6 +42,8 @@
 #include <ti/csl/src/ip/mdio/V2/cslr_mdio.h>
 #include <ti/csl/src/ip/mdio/V2/csl_mdio.h>
 #include <ti/csl/src/ip/mdio/V2/csl_mdioAux.h>
+#elif defined (SOC_AM65XX)
+#include <ti/csl/csl_mdio.h>
 #else
 #include <ti/csl/csl_mdioAux.h>
 #endif
@@ -399,6 +401,21 @@ static void NIMU_ICSS_macClose(uint32_t hPort,NIMU_IcssPdInfo * pi)
 
 }
 
+#if defined (__aarch64__) || defined (__TI_ARM_V7R4__)
+static void NIMU_ICSS_MDIO_init(uint32_t baseAddr,
+              uint32_t mdioInputFreq,
+              uint32_t mdioOutputFreq)
+{
+    uint32_t clkDiv = (mdioInputFreq/mdioOutputFreq) - 1U;
+    uint32_t regVal = 0U;
+
+    HW_SET_FIELD(regVal, CSL_MDIO_CONTROL_REG_ENABLE, CSL_MDIO_CONTROL_REG_ENABLE_0X1);
+    HW_SET_FIELD(regVal,  CSL_MDIO_CONTROL_REG_PREAMBLE, CSL_MDIO_CONTROL_REG_PREAMBLE_EN_0X1);
+    HW_SET_FIELD(regVal, CSL_MDIO_CONTROL_REG_FAULT_DETECT_ENABLE, CSL_MDIO_CONTROL_REG_FAULT_DETECT_ENABLE_0X1);
+    HW_SET_FIELD(regVal, CSL_MDIO_CONTROL_REG_CLKDIV, clkDiv);
+    HW_WR_REG32(baseAddr + CSL_MDIO_CONTROL_REG, regVal);
+}
+#endif
 void NIMU_ICSS_openPeripheral(NIMU_IcssPdInfo *pi)
 {
     uint32_t              i;
@@ -414,8 +431,13 @@ void NIMU_ICSS_openPeripheral(NIMU_IcssPdInfo *pi)
     }
     if(ICSS_EMAC_MODE_MAC2 != (((ICSS_EmacObject*)(pi->nimuDrvHandle)->object)->emacInitcfg)->portMask)
     {
+#if defined (__aarch64__) || defined (__TI_ARM_V7R4__)
+        NIMU_ICSS_MDIO_init((((ICSS_EmacHwAttrs*)(pi->nimuDrvHandle)->hwAttrs)->emacBaseAddrCfg)->prussMiiMdioRegs,
+                                 NIMU_ICSS_DEFAULT_MDIOCLOCKFREQ,NIMU_ICSS_DEFAULT_MDIOBUSFREQ);
+#else
         CSL_MDIO_init((((ICSS_EmacHwAttrs*)(pi->nimuDrvHandle)->hwAttrs)->emacBaseAddrCfg)->prussMiiMdioRegs,
                                  NIMU_ICSS_DEFAULT_MDIOCLOCKFREQ,NIMU_ICSS_DEFAULT_MDIOBUSFREQ);
+#endif
     }
 
     /* Open all ports */