[PDK-8894] AM64x RM: Update BoardCfg and UDMA RM to allign with latest from SysConfig...
authorDon Dominic <a0486429@ti.com>
Fri, 11 Dec 2020 15:00:41 +0000 (20:30 +0530)
committerDon Dominic <a0486429@ti.com>
Fri, 11 Dec 2020 15:09:35 +0000 (20:39 +0530)
- Update BoardCfg with changes in CPSW resources
  - Allocate all resources to A53
- Udpate udma_rmcfg.c to be alligned with this
- Regenrate scilcient_boardcfg and sciclient_ccs_init

- Updates in allignment with https://bitbucket.itg.ti.com/projects/PSDKLA/repos/k3-resource-partitioning/pull-requests/11/overview

Signed-off-by: Don Dominic <a0486429@ti.com>
packages/ti/drv/sciclient/soc/V3/sciclient_defaultBoardcfg_rm.c
packages/ti/drv/sciclient/soc/V3/sciclient_defaultBoardcfg_rm_hex.h
packages/ti/drv/sciclient/tools/ccsLoadDmsc/am64x/sciclient_ccs_init_mcu1_0_release.xer5f
packages/ti/drv/udma/soc/am64x/udma_rmcfg.c

index be780f455f3fbc5e2651e2a04f6349d1b0dc1388..3265ec688fd293b33997c1fa8ecff405906300c2 100755 (executable)
@@ -122,7 +122,7 @@ __attribute__(( aligned(128), section(".boardcfg_data") )) =
                 .magic = TISCI_BOARDCFG_RM_RESASG_MAGIC_NUM,
                 .size = (uint16_t) sizeof(struct tisci_boardcfg_rm_resasg),
             },
-            .resasg_entries_size = 204 * sizeof(struct tisci_boardcfg_rm_resasg_entry),
+            .resasg_entries_size = 180 * sizeof(struct tisci_boardcfg_rm_resasg_entry),
         },
     },
     .resasg_entries = {
@@ -703,47 +703,11 @@ __attribute__(( aligned(128), section(".boardcfg_data") )) =
             .host_id = TISCI_HOST_ID_M4_0,
         },
         {
-            .num_resource = 16,
+            .num_resource = 64,
             .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_RING_CPSW_TX_CHAN),
             .start_resource = 16,
             .host_id = TISCI_HOST_ID_A53_2,
         },
-        {
-            .num_resource = 16,
-            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_RING_CPSW_TX_CHAN),
-            .start_resource = 32,
-            .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
-        },
-        {
-            .num_resource = 16,
-            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_RING_CPSW_TX_CHAN),
-            .start_resource = 32,
-            .host_id = TISCI_HOST_ID_MAIN_0_R5_1,
-        },
-        {
-            .num_resource = 8,
-            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_RING_CPSW_TX_CHAN),
-            .start_resource = 48,
-            .host_id = TISCI_HOST_ID_MAIN_0_R5_3,
-        },
-        {
-            .num_resource = 8,
-            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_RING_CPSW_TX_CHAN),
-            .start_resource = 56,
-            .host_id = TISCI_HOST_ID_MAIN_1_R5_1,
-        },
-        {
-            .num_resource = 8,
-            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_RING_CPSW_TX_CHAN),
-            .start_resource = 64,
-            .host_id = TISCI_HOST_ID_MAIN_1_R5_3,
-        },
-        {
-            .num_resource = 8,
-            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_RING_CPSW_TX_CHAN),
-            .start_resource = 72,
-            .host_id = TISCI_HOST_ID_M4_0,
-        },
         {
             .num_resource = 7,
             .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_RING_SAUL_TX_0_CHAN),
@@ -835,47 +799,11 @@ __attribute__(( aligned(128), section(".boardcfg_data") )) =
             .host_id = TISCI_HOST_ID_M4_0,
         },
         {
-            .num_resource = 11,
+            .num_resource = 16,
             .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_RING_CPSW_RX_CHAN),
             .start_resource = 128,
             .host_id = TISCI_HOST_ID_A53_2,
         },
-        {
-            .num_resource = 1,
-            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_RING_CPSW_RX_CHAN),
-            .start_resource = 139,
-            .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
-        },
-        {
-            .num_resource = 1,
-            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_RING_CPSW_RX_CHAN),
-            .start_resource = 139,
-            .host_id = TISCI_HOST_ID_MAIN_0_R5_1,
-        },
-        {
-            .num_resource = 1,
-            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_RING_CPSW_RX_CHAN),
-            .start_resource = 140,
-            .host_id = TISCI_HOST_ID_MAIN_0_R5_3,
-        },
-        {
-            .num_resource = 1,
-            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_RING_CPSW_RX_CHAN),
-            .start_resource = 141,
-            .host_id = TISCI_HOST_ID_MAIN_1_R5_1,
-        },
-        {
-            .num_resource = 1,
-            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_RING_CPSW_RX_CHAN),
-            .start_resource = 142,
-            .host_id = TISCI_HOST_ID_MAIN_1_R5_3,
-        },
-        {
-            .num_resource = 1,
-            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_RING_CPSW_RX_CHAN),
-            .start_resource = 143,
-            .host_id = TISCI_HOST_ID_M4_0,
-        },
         {
             .num_resource = 7,
             .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_RING_SAUL_RX_0_CHAN),
@@ -979,47 +907,11 @@ __attribute__(( aligned(128), section(".boardcfg_data") )) =
             .host_id = TISCI_HOST_ID_M4_0,
         },
         {
-            .num_resource = 2,
+            .num_resource = 8,
             .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_CPSW_TX_CHAN),
             .start_resource = 16,
             .host_id = TISCI_HOST_ID_A53_2,
         },
-        {
-            .num_resource = 2,
-            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_CPSW_TX_CHAN),
-            .start_resource = 18,
-            .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
-        },
-        {
-            .num_resource = 2,
-            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_CPSW_TX_CHAN),
-            .start_resource = 18,
-            .host_id = TISCI_HOST_ID_MAIN_0_R5_1,
-        },
-        {
-            .num_resource = 1,
-            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_CPSW_TX_CHAN),
-            .start_resource = 20,
-            .host_id = TISCI_HOST_ID_MAIN_0_R5_3,
-        },
-        {
-            .num_resource = 1,
-            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_CPSW_TX_CHAN),
-            .start_resource = 21,
-            .host_id = TISCI_HOST_ID_MAIN_1_R5_1,
-        },
-        {
-            .num_resource = 1,
-            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_CPSW_TX_CHAN),
-            .start_resource = 22,
-            .host_id = TISCI_HOST_ID_MAIN_1_R5_3,
-        },
-        {
-            .num_resource = 1,
-            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_CPSW_TX_CHAN),
-            .start_resource = 23,
-            .host_id = TISCI_HOST_ID_M4_0,
-        },
         {
             .num_resource = 1,
             .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_SAUL_TX_1_CHAN),
@@ -1153,47 +1045,11 @@ __attribute__(( aligned(128), section(".boardcfg_data") )) =
             .host_id = TISCI_HOST_ID_A53_2,
         },
         {
-            .num_resource = 11,
+            .num_resource = 16,
             .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_FLOW_CPSW_RX_CHAN),
             .start_resource = 16,
             .host_id = TISCI_HOST_ID_A53_2,
         },
-        {
-            .num_resource = 1,
-            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_FLOW_CPSW_RX_CHAN),
-            .start_resource = 27,
-            .host_id = TISCI_HOST_ID_MAIN_0_R5_0,
-        },
-        {
-            .num_resource = 1,
-            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_FLOW_CPSW_RX_CHAN),
-            .start_resource = 27,
-            .host_id = TISCI_HOST_ID_MAIN_0_R5_1,
-        },
-        {
-            .num_resource = 1,
-            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_FLOW_CPSW_RX_CHAN),
-            .start_resource = 28,
-            .host_id = TISCI_HOST_ID_MAIN_0_R5_3,
-        },
-        {
-            .num_resource = 1,
-            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_FLOW_CPSW_RX_CHAN),
-            .start_resource = 29,
-            .host_id = TISCI_HOST_ID_MAIN_1_R5_1,
-        },
-        {
-            .num_resource = 1,
-            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_FLOW_CPSW_RX_CHAN),
-            .start_resource = 30,
-            .host_id = TISCI_HOST_ID_MAIN_1_R5_3,
-        },
-        {
-            .num_resource = 1,
-            .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_FLOW_CPSW_RX_CHAN),
-            .start_resource = 31,
-            .host_id = TISCI_HOST_ID_M4_0,
-        },
         {
             .num_resource = 8,
             .type = TISCI_RESASG_UTYPE (TISCI_DEV_DMASS0_PKTDMA_0, TISCI_RESASG_SUBTYPE_PKTDMA_FLOW_SAUL_RX_0_CHAN),
index bce7a0353dbea8d60de551c769d72957ed53c8b3..cbd8f75b2d558093c82bd7af58857f6d4cc094ca 100644 (file)
@@ -89,7 +89,7 @@
     0x00000000U,     0x00000000U,     0x00000000U,     0x00000000U, \
     0x00000000U,     0x00000000U,     0x00000000U,     0x00000000U, \
     0x00000000U,     0x00000000U,     0x00000000U,     0x00000000U, \
-    0x00000000U,     0x7b250000U,     0x06600008U,     0x00000000U, \
+    0x00000000U,     0x7b250000U,     0x05a00008U,     0x00000000U, \
     0x00400010U,     0x0010000cU,     0x00400004U,     0x00100023U, \
     0x00400004U,     0x00140024U,     0x00400004U,     0x00180026U, \
     0x00400004U,     0x001c0029U,     0x00400004U,     0x0000002bU, \
     0x07900003U,     0x00040023U,     0x07900003U,     0x00070024U, \
     0x07900002U,     0x00090026U,     0x07900004U,     0x000d0029U, \
     0x07900002U,     0x000f002bU,     0x07900001U,     0x0010001eU, \
-    0x07910010U,     0x0020000cU,     0x07910010U,     0x00200023U, \
-    0x07910010U,     0x00300024U,     0x07910008U,     0x00380026U, \
-    0x07910008U,     0x00400029U,     0x07910008U,     0x0048002bU, \
-    0x07910008U,     0x0051001eU,     0x07920007U,     0x00580080U, \
+    0x07910040U,     0x0051000cU,     0x07920007U,     0x00580080U, \
     0x07930008U,     0x0060000cU,     0x07940004U,     0x0064000cU, \
     0x07940004U,     0x00640023U,     0x07940004U,     0x00680024U, \
     0x07950004U,     0x006c000cU,     0x07950004U,     0x006c0023U, \
     0x07960003U,     0x00740023U,     0x07960003U,     0x00770024U, \
     0x07960002U,     0x00790026U,     0x07960004U,     0x007d0029U, \
     0x07960002U,     0x007f002bU,     0x07960001U,     0x0080001eU, \
-    0x0797000bU,     0x008b000cU,     0x07970001U,     0x008b0023U, \
-    0x07970001U,     0x008c0024U,     0x07970001U,     0x008d0026U, \
-    0x07970001U,     0x008e0029U,     0x07970001U,     0x008f002bU, \
-    0x07970001U,     0x0091001eU,     0x07980007U,     0x00900080U, \
+    0x07970010U,     0x0091000cU,     0x07980007U,     0x00900080U, \
     0x07990008U,     0x00980080U,     0x079a0008U,     0x0098000cU, \
     0x079b0008U,     0x00a0000cU,     0x079c0020U,     0x00c0000cU, \
     0x079c0020U,     0x00c00023U,     0x079c0020U,     0x00e00024U, \
     0x07a30003U,     0x00040023U,     0x07a30003U,     0x00070024U, \
     0x07a30002U,     0x00090026U,     0x07a30004U,     0x000d0029U, \
     0x07a30002U,     0x000f002bU,     0x07a30001U,     0x0010001eU, \
-    0x07a40002U,     0x0012000cU,     0x07a40002U,     0x00120023U, \
-    0x07a40002U,     0x00140024U,     0x07a40001U,     0x00150026U, \
-    0x07a40001U,     0x00160029U,     0x07a40001U,     0x0017002bU, \
-    0x07a40001U,     0x0019001eU,     0x07a60001U,     0x001a000cU, \
+    0x07a40008U,     0x0019000cU,     0x07a60001U,     0x001a000cU, \
     0x07a70004U,     0x001e000cU,     0x07a70004U,     0x001e0023U, \
     0x07a70004U,     0x00220024U,     0x07a80004U,     0x0026000cU, \
     0x07a80004U,     0x00260023U,     0x07a80004U,     0x00000024U, \
     0x07aa0003U,     0x00040023U,     0x07aa0003U,     0x00070024U, \
     0x07aa0002U,     0x00090026U,     0x07aa0004U,     0x000d0029U, \
     0x07aa0002U,     0x000f002bU,     0x07aa0001U,     0x0010001eU, \
-    0x07ab0001U,     0x0010000cU,     0x07ac000bU,     0x001b000cU, \
-    0x07ac0001U,     0x001b0023U,     0x07ac0001U,     0x001c0024U, \
-    0x07ac0001U,     0x001d0026U,     0x07ac0001U,     0x001e0029U, \
-    0x07ac0001U,     0x001f002bU,     0x07ac0001U,     0x0020001eU, \
+    0x07ab0001U,     0x0010000cU,     0x07ac0010U,     0x0020000cU, \
     0x07ae0008U,     0x00200080U,     0x07b00008U,     0x00130080U, \
     0x07b10001U,     0x0028000cU,     0x07b20008U,     0x0014000cU, \
     0x07b30001U,     0x0028000cU,     0x07b40008U,     0x0015000cU, \
     0x00000000U,     0x00000000U,     0x00000000U,     0x00000000U, \
     0x00000000U,     0x00000000U,     0x00000000U,     0x00000000U, \
     0x00000000U,     0x00000000U,     0x00000000U,     0x00000000U, \
+    0x00000000U,     0x00000000U,     0x00000000U,     0x00000000U, \
+    0x00000000U,     0x00000000U,     0x00000000U,     0x00000000U, \
+    0x00000000U,     0x00000000U,     0x00000000U,     0x00000000U, \
+    0x00000000U,     0x00000000U,     0x00000000U,     0x00000000U, \
+    0x00000000U,     0x00000000U,     0x00000000U,     0x00000000U, \
+    0x00000000U,     0x00000000U,     0x00000000U,     0x00000000U, \
+    0x00000000U,     0x00000000U,     0x00000000U,     0x00000000U, \
+    0x00000000U,     0x00000000U,     0x00000000U,     0x00000000U, \
+    0x00000000U,     0x00000000U,     0x00000000U,     0x00000000U, \
+    0x00000000U,     0x00000000U,     0x00000000U,     0x00000000U, \
+    0x00000000U,     0x00000000U,     0x00000000U,     0x00000000U, \
+    0x00000000U,     0x00000000U,     0x00000000U,     0x00000000U, \
     0x00000000U,     0x00000000U,     0x00000000U,     0x00000000U\
 } /* 3246 bytes */
index aca1948ce2b9d65c4623e377b980069ba62583b9..c8ffe56ed91d517cf39ebaec61d1239684f38cac 100644 (file)
Binary files a/packages/ti/drv/sciclient/tools/ccsLoadDmsc/am64x/sciclient_ccs_init_mcu1_0_release.xer5f and b/packages/ti/drv/sciclient/tools/ccsLoadDmsc/am64x/sciclient_ccs_init_mcu1_0_release.xer5f differ
index 697cb37ecc05b3b7e76f60939ab4b71d851a2483..da7d78eeae135fbdac81ab26f7bc8783d92b38c1 100644 (file)
@@ -462,13 +462,13 @@ const Udma_RmInitPrms gUdmaRmDefCfg_Pktdma[UDMA_NUM_CORE] =
         4U,         /* numRxCh */
 
         {16U, 25U, 26U, 34U},  /* startMappedTxCh[] */
-        {2U,  1U,  4U,  4U},   /* numMappedTxCh[] */
+        {8U,  1U,  4U,  4U},   /* numMappedTxCh[] */
 
         {16U, 19U, 21U, 25U},  /* startMappedRxCh[] */
         {1U,  2U,  2U,  2U},   /* numMappedRxCh[] */
 
         {16U, 88U, 96U, 104U, 128U, 152U, 160U, 224U},   /* startMappedRing[] */
-        {16U, 8U,  4U,  4U,   11U,  8U,   32U,  32U},    /* numMappedRing[] */
+        {64U, 8U,  4U,  4U,   16U,  8U,   32U,  32U},    /* numMappedRing[] */
 
         0U,         /* startFreeFlow */
         0U,         /* numFreeFlow */
@@ -515,14 +515,14 @@ const Udma_RmInitPrms gUdmaRmDefCfg_Pktdma[UDMA_NUM_CORE] =
         9U,         /* startRxCh */
         4U,         /* numRxCh */
 
-        {21U, 0U, 0U, 0U},  /* startMappedTxCh[] */
-        {1U, 0U, 0U, 0U},   /* numMappedTxCh[] */
+        {0U, 0U, 0U, 0U},  /* startMappedTxCh[] */
+        {0U, 0U, 0U, 0U},  /* numMappedTxCh[] */
 
         {0U, 0U, 0U, 0U},  /* startMappedRxCh[] */
         {0U, 0U, 0U, 0U},  /* numMappedRxCh[] */
 
-        {56U, 0U, 0U, 0U, 141U, 0U, 0U, 0U},   /* startMappedRing[] */
-        {8U,  0U, 0U, 0U, 1U,   0U, 0U, 0U},   /* numMappedRing[] */
+        {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U},   /* startMappedRing[] */
+        {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U},   /* numMappedRing[] */
 
         0U,         /* startFreeFlow */
         0U,         /* numFreeFlow */
@@ -569,14 +569,14 @@ const Udma_RmInitPrms gUdmaRmDefCfg_Pktdma[UDMA_NUM_CORE] =
         13U,        /* startRxCh */
         2U,         /* numRxCh */
 
-        {22U, 0U, 0U, 0U},  /* startMappedTxCh[] */
-        {1U, 0U, 0U, 0U},   /* numMappedTxCh[] */
+        {0U, 0U, 0U, 0U},   /* startMappedTxCh[] */
+        {0U, 0U, 0U, 0U},   /* numMappedTxCh[] */
 
         {0U, 0U, 0U, 0U},   /* startMappedRxCh[] */
         {0U, 0U, 0U, 0U},   /* numMappedRxCh[] */
 
-        {64U, 0U, 0U, 0U, 142U, 0U, 0U, 0U},   /* startMappedRing[] */
-        {8U,  0U, 0U, 0U, 1U,   0U, 0U, 0U},   /* numMappedRing[] */
+        {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U},   /* startMappedRing[] */
+        {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U},   /* numMappedRing[] */
 
         0U,         /* startFreeFlow */
         0U,         /* numFreeFlow */
@@ -623,14 +623,14 @@ const Udma_RmInitPrms gUdmaRmDefCfg_Pktdma[UDMA_NUM_CORE] =
         4U,         /* startRxCh */
         3U,         /* numRxCh */
 
-        {18U, 0U,  30U, 38U},  /* startMappedTxCh[] */
-        {2U,  0U,  4U,  4U},   /* numMappedTxCh[] */
+        {0U, 0U,  30U, 38U},  /* startMappedTxCh[] */
+        {0U,  0U,  4U,  4U},   /* numMappedTxCh[] */
 
         {0U, 0U,  23U, 27U},  /* startMappedRxCh[] */
         {0U, 0U,  2U,  2U},   /* numMappedRxCh[] */
 
-        {32U, 0U, 100U, 108U, 139U, 0U, 192U, 256U},   /* startMappedRing[] */
-        {16U, 0U, 4U,   4U,   1U,   0U, 32U,  32U},    /* numMappedRing[] */
+        {0U, 0U, 100U, 108U, 0U, 0U, 192U, 256U},   /* startMappedRing[] */
+        {0U, 0U, 4U,   4U,   0U, 0U, 32U,  32U},    /* numMappedRing[] */
 
         0U,         /* startFreeFlow */
         0U,         /* numFreeFlow */
@@ -677,14 +677,14 @@ const Udma_RmInitPrms gUdmaRmDefCfg_Pktdma[UDMA_NUM_CORE] =
         7U,         /* startRxCh */
         2U,         /* numRxCh */
 
-        {20U, 0U, 0U, 0U},  /* startMappedTxCh[] */
-        {1U, 0U, 0U, 0U},   /* numMappedTxCh[] */
+        {0U, 0U, 0U, 0U},  /* startMappedTxCh[] */
+        {0U, 0U, 0U, 0U},  /* numMappedTxCh[] */
 
         {0U, 0U, 0U, 0U},  /* startMappedRxCh[] */
         {0U, 0U, 0U, 0U},  /* numMappedRxCh[] */
 
-        {48U, 0U, 0U, 0U, 140U, 0U, 0U, 0U},   /* startMappedRing[] */
-        {8U,  0U, 0U, 0U, 1U,   0U, 0U, 0U},   /* numMappedRing[] */
+        {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U},   /* startMappedRing[] */
+        {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U},   /* numMappedRing[] */
 
         0U,         /* startFreeFlow */
         0U,         /* numFreeFlow */
@@ -731,14 +731,14 @@ const Udma_RmInitPrms gUdmaRmDefCfg_Pktdma[UDMA_NUM_CORE] =
         15U,        /* startRxCh */
         1U,         /* numRxCh */
 
-        {23U, 0U, 0U, 0U},  /* startMappedTxCh[] */
-        {1U, 0U, 0U, 0U},   /* numMappedTxCh[] */
+        {0U, 0U, 0U, 0U},  /* startMappedTxCh[] */
+        {0U, 0U, 0U, 0U},  /* numMappedTxCh[] */
 
         {0U, 0U, 0U, 0U},  /* startMappedRxCh[] */
         {0U, 0U, 0U, 0U},  /* numMappedRxCh[] */
 
-        {72U, 0U, 0U, 0U, 143U, 0U, 0U, 0U},   /* startMappedRing[] */
-        {8U,  0U, 0U, 0U, 1U,   0U, 0U, 0U},   /* numMappedRing[] */
+        {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U},   /* startMappedRing[] */
+        {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U},   /* numMappedRing[] */
 
         0U,         /* startFreeFlow */
         0U,         /* numFreeFlow */