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raw | patch | inline | side by side (parent: bf8cb33)
raw | patch | inline | side by side (parent: bf8cb33)
author | Rishabh Garg <rishabh@ti.com> | |
Fri, 24 Jun 2022 16:01:26 +0000 (21:31 +0530) | ||
committer | Rishabh Garg <rishabh@ti.com> | |
Fri, 24 Jun 2022 16:09:52 +0000 (11:09 -0500) |
- For NAVSS INTR, the output destination should be queried separately for both base event num and current event num
- Made corresponding changes in CLEC registration
Signed-off-by: Rishabh Garg <rishabh@ti.com>
- Made corresponding changes in CLEC registration
Signed-off-by: Rishabh Garg <rishabh@ti.com>
packages/ti/drv/ipc/soc/V4/ipc_soc.c | patch | blob | history |
index bf2d225521115f99c3f048697ff2b7d050bf3622..219adc212222795ef4b48ca3b676cffc41921673 100755 (executable)
#define IPC_INTERRUPT_OFFSET (5U)
#define IPC_INTERRUPT_OFFSET (5U)
+extern uint32_t g_ipc_mBoxCnt;
+
/**
* \brief Main NavSS512 - Mailbox input line
*/
/**
* \brief Main NavSS512 - Mailbox input line
*/
@@ -460,7 +462,9 @@ int32_t Ipc_setCoreEventId(uint32_t selfId, Ipc_MbConfig* cfg, uint32_t intrCnt)
{
int32_t retVal = IPC_SOK;
uint32_t outIntrBaseNum = 0;
{
int32_t retVal = IPC_SOK;
uint32_t outIntrBaseNum = 0;
+ uint32_t outIntrNum = 0;
uint32_t vimEventBaseNum = 0;
uint32_t vimEventBaseNum = 0;
+ uint32_t vimEventNum = 0;
uint16_t proc_irq = 0;
/*
uint16_t proc_irq = 0;
/*
@@ -496,6 +500,7 @@ int32_t Ipc_setCoreEventId(uint32_t selfId, Ipc_MbConfig* cfg, uint32_t intrCnt)
offset = range;
}
outIntrBaseNum = (start + range) - offset;
offset = range;
}
outIntrBaseNum = (start + range) - offset;
+ outIntrNum = outIntrBaseNum + intrCnt;
/* Translate to CorePack IRQ number */
/* Translation must happen after this offset */
/* Translate to CorePack IRQ number */
/* Translation must happen after this offset */
@@ -506,6 +511,15 @@ int32_t Ipc_setCoreEventId(uint32_t selfId, Ipc_MbConfig* cfg, uint32_t intrCnt)
vimEventBaseNum = proc_irq;
}
vimEventBaseNum = proc_irq;
}
+ /* Translation must happen after this offset */
+ proc_irq = 0;
+ retVal = Ipc_sciclientIrqTranslate((uint16_t)selfId, outIntrNum,
+ &proc_irq);
+ if (CSL_PASS == retVal)
+ {
+ vimEventNum = proc_irq;
+ }
+
}
else
{
}
else
{
@@ -574,8 +588,8 @@ int32_t Ipc_setCoreEventId(uint32_t selfId, Ipc_MbConfig* cfg, uint32_t intrCnt)
break;
}
#endif
break;
}
#endif
- cfg->outputIntrNum = outIntrBaseNum + intrCnt;
- cfg->eventId = vimEventBaseNum + intrCnt;
+ cfg->outputIntrNum = outIntrNum;
+ cfg->eventId = vimEventNum;
cfg->eventIdBase = vimEventBaseNum;
return retVal;
cfg->eventIdBase = vimEventBaseNum;
return retVal;
@@ -621,7 +635,7 @@ uint32_t Ipc_configClecRouter(uint32_t corePackEvent, uint32_t corePackEventBase
/* Even though same CLEC is shared b/w all C7x cores, CLEC can broadcast the
* event to any C7x core and CPU IRQ(corepackIrq) is core specific.
* Hence same Mailbox Interrupt offset can be used for both C7x cores. */
/* Even though same CLEC is shared b/w all C7x cores, CLEC can broadcast the
* event to any C7x core and CPU IRQ(corepackIrq) is core specific.
* Hence same Mailbox Interrupt offset can be used for both C7x cores. */
- corepackIrq = (corePackEvent - corePackEventBase) + IPC_C7X_MBINTR_OFFSET;
+ corepackIrq = (g_ipc_mBoxCnt) + IPC_C7X_MBINTR_OFFSET;
/* corePackEvent is derived from the NAVSS IR o/p range returned from BoardCfg,
* based on core specific allocation. And this is different for each C7x.
/* corePackEvent is derived from the NAVSS IR o/p range returned from BoardCfg,
* based on core specific allocation. And this is different for each C7x.