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raw | patch | inline | side by side (parent: e5623a9)
raw | patch | inline | side by side (parent: e5623a9)
author | Mahesh Radhkrishnan <uda0875154local@UDA0875154> | |
Mon, 17 Aug 2020 19:46:30 +0000 (15:46 -0400) | ||
committer | Sivaraj R <sivaraj@ti.com> | |
Tue, 18 Aug 2020 03:38:19 +0000 (22:38 -0500) |
diff --git a/packages/ti/boot/sbl/build/sbl_mcu0_boot_xip_entry.mk b/packages/ti/boot/sbl/build/sbl_mcu0_boot_xip_entry.mk
index 152df8773a093d71fd8766bc10cfdbc6160aca55..c08cae00eaa2ef0453c138759bbc2367fcde762a 100644 (file)
SRCS_COMMON += xip_stub.c
SRCS_ASM_COMMON = xip_entry.asm
-EXTERNAL_LNKCMD_FILE_LOCAL = $(PDK_SBL_COMP_PATH)/example/k3MulticoreApp/xip_entry.lds
+EXTERNAL_LNKCMD_FILE_LOCAL = $(PDK_SBL_COMP_PATH)/example/k3MulticoreApp/$(SOC)/xip_entry.lds
# Core/SoC/platform specific source files and CFLAGS
# Example:
diff --git a/packages/ti/boot/sbl/build/sbl_mcu0_boot_xip_test.mk b/packages/ti/boot/sbl/build/sbl_mcu0_boot_xip_test.mk
index 36585f39d9d85edda0f4cb131a0b7b1111478330..1675b240c8096fb818850b286251c37b2a56dd09 100644 (file)
SRCS_COMMON += sbl_amp_multicore.c sbl_printf.c
SRCS_ASM_COMMON = sbl_multicore_r5_xip.asm
-EXTERNAL_LNKCMD_FILE_LOCAL = $(PDK_SBL_COMP_PATH)/example/k3MulticoreApp/mcuXiplinker.lds
+EXTERNAL_LNKCMD_FILE_LOCAL = $(PDK_SBL_COMP_PATH)/example/k3MulticoreApp/$(SOC)/mcuXiplinker.lds
# Core/SoC/platform specific source files and CFLAGS
# Example:
diff --git a/packages/ti/boot/sbl/example/k3MulticoreApp/am64x/mcuXiplinker.lds b/packages/ti/boot/sbl/example/k3MulticoreApp/am64x/mcuXiplinker.lds
--- /dev/null
@@ -0,0 +1,26 @@
+/*----------------------------------------------------------------------------*/
+/* File: mcuXiplinker.cmd */
+/* Description: */
+/* Link command file for Maxwell Multicore Testcase */
+/* */
+/* Platform: R5 Cores on AM65xx */
+/* (c) Texas Instruments 2019, All rights reserved. */
+/*----------------------------------------------------------------------------*/
+
+--entry_point=_sblTestResetVectors
+--stack_size=0x1000
+
+MEMORY
+{
+ OSPI_MCU1_CPU0_XIP_VEC : origin=0x600e0000 length=0x40 /* 64B */
+ OSPI_MCU1_CPU0_XIP : origin=0x600e0040 length=0x2000 - 0x40 /* 8KB - 64B*/
+ OCMRAM_SBL_SYSFW : origin=0x70080000 length=0x2000 - 0x800 /* 8KB */
+}
+
+SECTIONS
+{
+ .rstvectors : {} palign(8) > OSPI_MCU1_CPU0_XIP_VEC
+ .sbl_mcu_1_0_resetvector : {} palign(8) > OSPI_MCU1_CPU0_XIP
+ .stack : {} palign(8) > OCMRAM_SBL_SYSFW
+}
+
diff --git a/packages/ti/boot/sbl/example/k3MulticoreApp/am64x/xip_entry.lds b/packages/ti/boot/sbl/example/k3MulticoreApp/am64x/xip_entry.lds
--- /dev/null
@@ -0,0 +1,23 @@
+/*----------------------------------------------------------------------------*/
+/* File: xip_entry.lds */
+/* Description: */
+/* Link command file for Maxwell Multicore Testcase */
+/* */
+/* Platform: R5 Cores on AM65xx */
+/* (c) Texas Instruments 2019, All rights reserved. */
+/*----------------------------------------------------------------------------*/
+
+_xipAppEntry=0x600e0000;
+--entry_point=_xipAppEntry
+--retain="_xipAppEntry"
+--retain="_xip_stub"
+
+MEMORY
+{
+ OCMRAM_SBL_SYSFW : origin=0x70080000 length=0x2000 /* 8KB */
+}
+
+SECTIONS
+{
+ .xip_entry : {} palign(8) > OCMRAM_SBL_SYSFW
+}
diff --git a/packages/ti/boot/sbl/example/k3MulticoreApp/mcuXiplinker.lds b/packages/ti/boot/sbl/example/k3MulticoreApp/am65xx/mcuXiplinker.lds
similarity index 100%
rename from packages/ti/boot/sbl/example/k3MulticoreApp/mcuXiplinker.lds
rename to packages/ti/boot/sbl/example/k3MulticoreApp/am65xx/mcuXiplinker.lds
rename from packages/ti/boot/sbl/example/k3MulticoreApp/mcuXiplinker.lds
rename to packages/ti/boot/sbl/example/k3MulticoreApp/am65xx/mcuXiplinker.lds
diff --git a/packages/ti/boot/sbl/example/k3MulticoreApp/xip_entry.lds b/packages/ti/boot/sbl/example/k3MulticoreApp/am65xx/xip_entry.lds
similarity index 100%
rename from packages/ti/boot/sbl/example/k3MulticoreApp/xip_entry.lds
rename to packages/ti/boot/sbl/example/k3MulticoreApp/am65xx/xip_entry.lds
rename from packages/ti/boot/sbl/example/k3MulticoreApp/xip_entry.lds
rename to packages/ti/boot/sbl/example/k3MulticoreApp/am65xx/xip_entry.lds
diff --git a/packages/ti/boot/sbl/example/k3MulticoreApp/j7200/mcuXiplinker.lds b/packages/ti/boot/sbl/example/k3MulticoreApp/j7200/mcuXiplinker.lds
--- /dev/null
@@ -0,0 +1,26 @@
+/*----------------------------------------------------------------------------*/
+/* File: mcuXiplinker.cmd */
+/* Description: */
+/* Link command file for Maxwell Multicore Testcase */
+/* */
+/* Platform: R5 Cores on AM65xx */
+/* (c) Texas Instruments 2019, All rights reserved. */
+/*----------------------------------------------------------------------------*/
+
+--entry_point=_sblTestResetVectors
+--stack_size=0x1000
+
+MEMORY
+{
+ OSPI_MCU1_CPU0_XIP_VEC : origin=0x500e0000 length=0x40 /* 64B */
+ OSPI_MCU1_CPU0_XIP : origin=0x500e0040 length=0x2000 - 0x40 /* 8KB - 64B*/
+ OCMRAM_SBL_SYSFW : origin=0x41C3E000 length=0x2000 - 0x800 /* 8KB */
+}
+
+SECTIONS
+{
+ .rstvectors : {} palign(8) > OSPI_MCU1_CPU0_XIP_VEC
+ .sbl_mcu_1_0_resetvector : {} palign(8) > OSPI_MCU1_CPU0_XIP
+ .stack : {} palign(8) > OCMRAM_SBL_SYSFW
+}
+
diff --git a/packages/ti/boot/sbl/example/k3MulticoreApp/j7200/xip_entry.lds b/packages/ti/boot/sbl/example/k3MulticoreApp/j7200/xip_entry.lds
--- /dev/null
@@ -0,0 +1,23 @@
+/*----------------------------------------------------------------------------*/
+/* File: xip_entry.lds */
+/* Description: */
+/* Link command file for Maxwell Multicore Testcase */
+/* */
+/* Platform: R5 Cores on AM65xx */
+/* (c) Texas Instruments 2019, All rights reserved. */
+/*----------------------------------------------------------------------------*/
+
+_xipAppEntry=0x500e0000;
+--entry_point=_xipAppEntry
+--retain="_xipAppEntry"
+--retain="_xip_stub"
+
+MEMORY
+{
+ OCMRAM_SBL_SYSFW : origin=0x41C3E000 length=0x2000 /* 8KB */
+}
+
+SECTIONS
+{
+ .xip_entry : {} palign(8) > OCMRAM_SBL_SYSFW
+}
diff --git a/packages/ti/boot/sbl/example/k3MulticoreApp/j721e/mcuXiplinker.lds b/packages/ti/boot/sbl/example/k3MulticoreApp/j721e/mcuXiplinker.lds
--- /dev/null
@@ -0,0 +1,26 @@
+/*----------------------------------------------------------------------------*/
+/* File: mcuXiplinker.cmd */
+/* Description: */
+/* Link command file for Maxwell Multicore Testcase */
+/* */
+/* Platform: R5 Cores on AM65xx */
+/* (c) Texas Instruments 2019, All rights reserved. */
+/*----------------------------------------------------------------------------*/
+
+--entry_point=_sblTestResetVectors
+--stack_size=0x1000
+
+MEMORY
+{
+ OSPI_MCU1_CPU0_XIP_VEC : origin=0x500e0000 length=0x40 /* 64B */
+ OSPI_MCU1_CPU0_XIP : origin=0x500e0040 length=0x2000 - 0x40 /* 8KB - 64B*/
+ OCMRAM_SBL_SYSFW : origin=0x41C3E000 length=0x2000 - 0x800 /* 8KB */
+}
+
+SECTIONS
+{
+ .rstvectors : {} palign(8) > OSPI_MCU1_CPU0_XIP_VEC
+ .sbl_mcu_1_0_resetvector : {} palign(8) > OSPI_MCU1_CPU0_XIP
+ .stack : {} palign(8) > OCMRAM_SBL_SYSFW
+}
+
diff --git a/packages/ti/boot/sbl/example/k3MulticoreApp/j721e/xip_entry.lds b/packages/ti/boot/sbl/example/k3MulticoreApp/j721e/xip_entry.lds
--- /dev/null
@@ -0,0 +1,23 @@
+/*----------------------------------------------------------------------------*/
+/* File: xip_entry.lds */
+/* Description: */
+/* Link command file for Maxwell Multicore Testcase */
+/* */
+/* Platform: R5 Cores on AM65xx */
+/* (c) Texas Instruments 2019, All rights reserved. */
+/*----------------------------------------------------------------------------*/
+
+_xipAppEntry=0x500e0000;
+--entry_point=_xipAppEntry
+--retain="_xipAppEntry"
+--retain="_xip_stub"
+
+MEMORY
+{
+ OCMRAM_SBL_SYSFW : origin=0x41C3E000 length=0x2000 /* 8KB */
+}
+
+SECTIONS
+{
+ .xip_entry : {} palign(8) > OCMRAM_SBL_SYSFW
+}
index 117a3d86d6fbb7fba564519988b1ec5c67297ec0..f544b5b3b136cd13ed15890ae2c85d73b081b2a8 100644 (file)
export sbl_boot_xip_test_BOARDLIST
sbl_boot_xip_test_$(SOC)_CORELIST = mcu1_0
export sbl_boot_xip_test_$(SOC)_CORELIST
-ifneq ($(SOC),$(filter $(SOC), am64x tpr12))
+ifneq ($(SOC),$(filter $(SOC), tpr12))
sbl_EXAMPLE_LIST += sbl_boot_xip_test
endif
sbl_boot_xip_test_SBL_APPIMAGEGEN = yes
export sbl_boot_xip_entry_BOARDLIST
sbl_boot_xip_entry_$(SOC)_CORELIST = mcu1_0
export sbl_boot_xip_entry_$(SOC)_CORELIST
-ifneq ($(SOC),$(filter $(SOC), am64x tpr12))
+ifneq ($(SOC),$(filter $(SOC), tpr12))
sbl_EXAMPLE_LIST += sbl_boot_xip_entry
endif
sbl_boot_xip_entry_SBL_APPIMAGEGEN = yes