PDK-5377 Updates for SBL serdes sharing feature

Signed-off-by: Rishabh Garg <rishabh@ti.com>

diff --git a/packages/ti/board/src/j721e_evm/board_init.c b/packages/ti/board/src/j721e_evm/board_init.c
index 523d6014e9695a52395debbfa30ee8ec8529f421..ea7ded738acd59fb678f24a181e89a1477ee1b3e 100755 (executable)
--- a/packages/ti/board/src/j721e_evm/board_init.c
+++ b/packages/ti/board/src/j721e_evm/board_init.c
@@ -308,6 +308,11 @@ Board_STATUS Board_init(Board_initCfg cfg)
     if (ret != BOARD_SOK)
         return ret;
 
+    if (cfg & BOARD_INIT_SERDES_PHY)
+        ret = Board_serdesCfg();
+    if (ret != BOARD_SOK)
+        return ret;
+
     return ret;
 }
 

diff --git a/packages/ti/board/src/j721e_evm/board_serdes_cfg.c b/packages/ti/board/src/j721e_evm/board_serdes_cfg.c
index f871b04b7339fbc1537f1ac42dd093f875c4ecbc..ee505291eb44f5ec54a6fffeb968e05ea902ac77 100755 (executable)
--- a/packages/ti/board/src/j721e_evm/board_serdes_cfg.c
+++ b/packages/ti/board/src/j721e_evm/board_serdes_cfg.c
@@ -125,17 +125,13 @@ static Board_STATUS Board_CfgQsgmii(void)
     serdesLane0EnableParams.refClock          = CSL_SERDES_REF_CLOCK_100M;\r
     serdesLane0EnableParams.refClkSrc         = CSL_SERDES_REF_CLOCK_INT;\r
     serdesLane0EnableParams.linkRate          = CSL_SERDES_LINK_RATE_5G;\r
-    serdesLane0EnableParams.numLanes          = 0x2;\r
-    serdesLane0EnableParams.laneMask          = 0x3;\r
+    serdesLane0EnableParams.numLanes          = 1;\r
+    serdesLane0EnableParams.laneMask          = 0x2;\r
     serdesLane0EnableParams.SSC_mode          = CSL_SERDES_NO_SSC;\r
     serdesLane0EnableParams.phyType           = CSL_SERDES_PHY_TYPE_QSGMII;\r
     serdesLane0EnableParams.operatingMode     = CSL_SERDES_FUNCTIONAL_MODE;\r
     serdesLane0EnableParams.phyInstanceNum    = SERDES_LANE_SELECT_CPSW;\r
-    serdesLane0EnableParams.pcieGenType        = CSL_SERDES_PCIE_GEN4;\r
-\r
-    serdesLane0EnableParams.laneCtrlRate[0]   = CSL_SERDES_LANE_FULL_RATE;\r
-    serdesLane0EnableParams.loopbackMode[0]   = CSL_SERDES_LOOPBACK_DISABLED;\r
-\r
+    serdesLane0EnableParams.pcieGenType       = CSL_SERDES_PCIE_GEN4;\r
     serdesLane0EnableParams.laneCtrlRate[1]   = CSL_SERDES_LANE_FULL_RATE;\r
     serdesLane0EnableParams.loopbackMode[1]   = CSL_SERDES_LOOPBACK_DISABLED;\r
 \r
@@ -160,8 +156,6 @@ static Board_STATUS Board_CfgQsgmii(void)
     {\r
         return BOARD_FAIL;\r
     }\r
-    /* Assert PHY reset and disable all lanes */\r
-    CSL_serdesDisablePllAndLanes(serdesLane0EnableParams.baseAddr, serdesLane0EnableParams.numLanes, serdesLane0EnableParams.laneMask);\r
 \r
     /* Load the Serdes Config File */\r
     result = CSL_serdesEthernetInit(&serdesLane0EnableParams);\r
@@ -181,6 +175,188 @@ static Board_STATUS Board_CfgQsgmii(void)
     return BOARD_SOK;\r
 }\r
 \r
+static Board_STATUS Board_CfgSierra0Clks(void)\r
+{\r
+    uint64_t clkRateHz = 100000000U, clkRateRead = 0U;\r
+    uint32_t moduleId  = TISCI_DEV_SERDES_16G0;\r
+    int32_t i, result;\r
+    uint32_t clkID[] = { TISCI_DEV_SERDES_16G0_CORE_REF1_CLK,\r
+                         TISCI_DEV_SERDES_16G0_CORE_REF_CLK };\r
+    uint32_t parentID[] = { TISCI_DEV_SERDES_16G0_CORE_REF1_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK,\r
+                            TISCI_DEV_SERDES_16G0_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK };\r
+\r
+    for(i=0; i< sizeof(clkID)/sizeof(clkID[0]); i++)\r
+    {\r
+        /* Disable the clock */\r
+        result = Sciclient_pmModuleClkRequest(moduleId,\r
+                                              clkID[i],\r
+                                              TISCI_MSG_VALUE_CLOCK_SW_STATE_UNREQ,\r
+                                              0U,\r
+                                              SCICLIENT_SERVICE_WAIT_FOREVER);\r
+        if (result != CSL_SERDES_NO_ERR)\r
+        {\r
+            return BOARD_FAIL;\r
+        }\r
+\r
+        /* Set the parent */\r
+        result = Sciclient_pmSetModuleClkParent(moduleId,\r
+                                                clkID[i],\r
+                                                parentID[i],\r
+                                                SCICLIENT_SERVICE_WAIT_FOREVER);\r
+\r
+        if (result != CSL_SERDES_NO_ERR)\r
+        {\r
+            return BOARD_FAIL;\r
+        }\r
+\r
+        /* Set the clock at the desirable frequency */\r
+        result = Sciclient_pmSetModuleClkFreq(moduleId,\r
+                                              clkID[i],\r
+                                              clkRateHz,\r
+                                              TISCI_MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE,\r
+                                              SCICLIENT_SERVICE_WAIT_FOREVER);\r
+\r
+        if (result != CSL_SERDES_NO_ERR)\r
+        {\r
+            return BOARD_FAIL;\r
+        }\r
+\r
+        /* Confirm if clock is set */\r
+        clkRateRead = 0U;\r
+        result = Sciclient_pmGetModuleClkFreq(moduleId,\r
+                                              clkID[i],\r
+                                              &clkRateRead,\r
+                                              SCICLIENT_SERVICE_WAIT_FOREVER);\r
+\r
+        if ((result != CSL_SERDES_NO_ERR) || (clkRateRead != clkRateHz))\r
+        {\r
+            return BOARD_FAIL;\r
+        }\r
+    }\r
+\r
+    /* Set module to ON state */\r
+    result = Sciclient_pmSetModuleState(moduleId,\r
+                                        TISCI_MSG_VALUE_DEVICE_SW_STATE_ON,\r
+                                        (TISCI_MSG_FLAG_AOP | TISCI_MSG_FLAG_DEVICE_RESET_ISO),\r
+                                        SCICLIENT_SERVICE_WAIT_FOREVER);\r
+    if (result != CSL_SERDES_NO_ERR)\r
+    {\r
+        return BOARD_FAIL;\r
+    }\r
+\r
+    /* Reset if changed state to enabled */\r
+    result = Sciclient_pmSetModuleRst(moduleId,\r
+                                      0x0U /*resetBit*/,\r
+                                      SCICLIENT_SERVICE_WAIT_FOREVER);\r
+\r
+    if (result != CSL_SERDES_NO_ERR)\r
+    {\r
+        return BOARD_FAIL;\r
+    }\r
+\r
+\r
+    return BOARD_SOK;\r
+}\r
+\r
+static Board_STATUS Board_CfgMultilinkPcieQsgmii(void)\r
+{\r
+    CSL_SerdesResult result;\r
+    CSL_SerdesMultilink multiLinkId = CSL_SERDES_PCIe_QSGMII_MULTILINK;\r
+    CSL_SerdesInstance serdesInstanceId = CSL_SIERRA_SERDES0;\r
+    CSL_SerdesLaneEnableStatus laneRetVal = CSL_SERDES_LANE_ENABLE_NO_ERR;\r
+    CSL_SerdesLaneEnableParams serdesLane0EnableParams;\r
+    CSL_SerdesLaneEnableParams serdesLane1EnableParams;\r
+\r
+    memset(&serdesLane0EnableParams, 0, sizeof(serdesLane0EnableParams));\r
+    memset(&serdesLane1EnableParams, 0, sizeof(serdesLane1EnableParams));\r
+\r
+    /* PCIe Config */\r
+    serdesLane0EnableParams.serdesInstance    = CSL_SIERRA_SERDES0;\r
+    serdesLane0EnableParams.baseAddr          = CSL_SERDES_16G0_BASE;\r
+    serdesLane0EnableParams.refClock          = CSL_SERDES_REF_CLOCK_100M;\r
+    serdesLane0EnableParams.refClkSrc         = CSL_SERDES_REF_CLOCK_INT;\r
+    serdesLane0EnableParams.linkRate          = CSL_SERDES_LINK_RATE_5G;\r
+    serdesLane0EnableParams.numLanes          = 1U;\r
+    serdesLane0EnableParams.laneMask          = 0x1U;\r
+    serdesLane0EnableParams.SSC_mode          = CSL_SERDES_NO_SSC;\r
+    serdesLane0EnableParams.phyType           = CSL_SERDES_PHY_TYPE_PCIe;\r
+    serdesLane0EnableParams.operatingMode     = CSL_SERDES_FUNCTIONAL_MODE;\r
+    serdesLane0EnableParams.phyInstanceNum    = SERDES_PCIE_PHY_INST_NUM;\r
+    serdesLane0EnableParams.pcieGenType       = CSL_SERDES_PCIE_GEN4;\r
+    serdesLane0EnableParams.laneCtrlRate[0]   = CSL_SERDES_LANE_FULL_RATE;\r
+    serdesLane0EnableParams.loopbackMode[0]   = CSL_SERDES_LOOPBACK_DISABLED;\r
+\r
+    /* QSGMII Config */\r
+    serdesLane1EnableParams.serdesInstance    = CSL_SIERRA_SERDES0;\r
+    serdesLane1EnableParams.baseAddr          = CSL_SERDES_16G0_BASE;\r
+    serdesLane1EnableParams.refClock          = CSL_SERDES_REF_CLOCK_100M;\r
+    serdesLane1EnableParams.refClkSrc         = CSL_SERDES_REF_CLOCK_INT;\r
+    serdesLane1EnableParams.linkRate          = CSL_SERDES_LINK_RATE_5G;\r
+    serdesLane1EnableParams.numLanes          = 1U;\r
+    serdesLane1EnableParams.laneMask          = 0x2U;\r
+    serdesLane1EnableParams.SSC_mode          = CSL_SERDES_NO_SSC;\r
+    serdesLane1EnableParams.phyType           = CSL_SERDES_PHY_TYPE_QSGMII;\r
+    serdesLane1EnableParams.operatingMode     = CSL_SERDES_FUNCTIONAL_MODE;\r
+    serdesLane1EnableParams.phyInstanceNum    = SERDES_LANE_SELECT_CPSW;\r
+    serdesLane1EnableParams.pcieGenType       = CSL_SERDES_PCIE_GEN4;\r
+    serdesLane1EnableParams.laneCtrlRate[1]   = CSL_SERDES_LANE_FULL_RATE;\r
+    serdesLane1EnableParams.loopbackMode[1]   = CSL_SERDES_LOOPBACK_DISABLED;\r
+\r
+    CSL_serdesPorReset(CSL_SERDES_16G0_BASE);\r
+\r
+    /* Select the IP type, IP instance num, Serdes Lane Number for PCIe */\r
+    CSL_serdesIPSelect(CSL_CTRL_MMR0_CFG0_BASE,\r
+                       serdesLane0EnableParams.phyType,\r
+                       serdesLane0EnableParams.phyInstanceNum,\r
+                       serdesLane0EnableParams.serdesInstance,\r
+                       PCIE0_LANE_NUM);\r
+\r
+    /* Select the IP type, IP instance num, Serdes Lane Number for QSGMII */\r
+    CSL_serdesIPSelect(CSL_CTRL_MMR0_CFG0_BASE,\r
+                       serdesLane1EnableParams.phyType,\r
+                       serdesLane1EnableParams.phyInstanceNum,\r
+                       serdesLane1EnableParams.serdesInstance,\r
+                       SGMII_LANE_NUM);\r
+\r
+    result = CSL_serdesRefclkSel(CSL_CTRL_MMR0_CFG0_BASE,\r
+                                 CSL_SERDES_16G0_BASE,\r
+                                 CSL_SERDES_REF_CLOCK_100M,\r
+                                 CSL_SERDES_REF_CLOCK_INT,\r
+                                 CSL_SIERRA_SERDES0,\r
+                                 0U /* unused */);\r
+\r
+    if (result != CSL_SERDES_NO_ERR)\r
+    {\r
+        return BOARD_FAIL;\r
+    }\r
+\r
+    /* Load the Serdes Config File */\r
+    result = CSL_serdesMultiLinkInit(multiLinkId,\r
+                                     serdesInstanceId,\r
+                                     &serdesLane0EnableParams,\r
+                                     &serdesLane1EnableParams);\r
+    if (result != CSL_SERDES_NO_ERR)\r
+    {\r
+        return BOARD_FAIL;\r
+    }\r
+\r
+    /* Enable PCIe lane */\r
+    laneRetVal = CSL_serdesLaneEnable(&serdesLane0EnableParams);\r
+    if (laneRetVal != CSL_SERDES_LANE_ENABLE_NO_ERR)\r
+    {\r
+        return BOARD_FAIL;\r
+    }\r
+\r
+    /* Enable QSGMII lane */\r
+    laneRetVal = CSL_serdesLaneEnable(&serdesLane1EnableParams);\r
+    if (laneRetVal != CSL_SERDES_LANE_ENABLE_NO_ERR)\r
+    {\r
+        return BOARD_FAIL;\r
+    }\r
+\r
+    return BOARD_SOK;\r
+}\r
+\r
 /**\r
  *  \brief serdes configurations\r
  *\r
@@ -238,3 +414,32 @@ int32_t Board_serdesCfgStatus(void)
 \r
     return ret;\r
 }\r
+\r
+/**\r
+ *  \brief serdes configurations\r
+ *\r
+ *  The function configures the serdes for multi-link on Sierra0: PCIe and QSGMII\r
+ *\r
+ *  \return   BOARD_SOK in case of success or appropriate error code\r
+ *\r
+ */\r
+Board_STATUS Board_serdesCfg(void)\r
+{\r
+    Board_STATUS ret;\r
+\r
+    /* Configure SERDES clocks */\r
+    ret = Board_CfgSierra0Clks();\r
+    if(ret != BOARD_SOK)\r
+    {\r
+        return ret;\r
+    }\r
+\r
+    /* SERDES0 Initializations */\r
+    ret = Board_CfgMultilinkPcieQsgmii();\r
+    if(ret != BOARD_SOK)\r
+    {\r
+        return ret;\r
+    }\r
+\r
+    return BOARD_SOK;\r
+}\r

diff --git a/packages/ti/board/src/j721e_evm/include/board_serdes_cfg.h b/packages/ti/board/src/j721e_evm/include/board_serdes_cfg.h
index 0bb18a5768ac78040e96592b490410300ada77c6..70dc449bd9528b4a9aaecd2b9d2b498c0621d95e 100755 (executable)
--- a/packages/ti/board/src/j721e_evm/include/board_serdes_cfg.h
+++ b/packages/ti/board/src/j721e_evm/include/board_serdes_cfg.h
@@ -53,6 +53,8 @@
 #include <ti/csl/csl_serdes_pcie.h>\r
 #include <ti/csl/cslr_pcie.h>\r
 #include <ti/csl/csl_serdes_ethernet.h>\r
+#include <ti/csl/csl_serdes_multilink.h>\r
+#include <ti/drv/sciclient/sciclient.h>\r
 \r
 #include <ti/board/board.h>\r
 #include <ti/board/src/j721e_evm/include/board_internal.h>\r
@@ -76,6 +78,8 @@ extern "C" {
 /* Select SERDES lane functionality. 0 value means CPSW SGMII/QSGMII. */\r
 #define SERDES_LANE_SELECT_CPSW     (0U)\r
 \r
+#define SERDES_PCIE_PHY_INST_NUM    (0U)\r
+\r
 /**\r
  *  \brief serdes configurations for Sierra 1 in SGMII mode\r
  *\r

diff --git a/packages/ti/boot/sbl/board/k3/sbl_main.c b/packages/ti/boot/sbl/board/k3/sbl_main.c
index 0464c133c5420ab6d3179da63532aecb2a0ca86e..2a7994909cfbe0d474394c80be115c944b01aecd 100755 (executable)
--- a/packages/ti/boot/sbl/board/k3/sbl_main.c
+++ b/packages/ti/boot/sbl/board/k3/sbl_main.c
@@ -492,6 +492,12 @@ int main()
     SBL_log(SBL_LOG_MAX, "done.\n");
 #endif
 
+#if defined(SBL_ENABLE_SERDES)
+    SBL_log(SBL_LOG_MIN, "Initlialzing SERDES ...");
+    Board_init(BOARD_INIT_SERDES_PHY);
+    SBL_log(SBL_LOG_MIN, "done.\n");
+#endif
+
 #if !defined(SBL_USE_MCU_DOMAIN_ONLY) && !defined(SBL_ENABLE_DEV_GRP_MCU)
     /* Enable GTC */
     SBL_log(SBL_LOG_MAX, "Initializing GTC ...");

diff --git a/packages/ti/boot/sbl/sbl_component.mk b/packages/ti/boot/sbl/sbl_component.mk
index be7c43c68d977d63900b2c1878c5cc4fa0321d34..3cf8c79e282a9c13226dfa6856154dd289cf6e17 100644 (file)
--- a/packages/ti/boot/sbl/sbl_component.mk
+++ b/packages/ti/boot/sbl/sbl_component.mk
@@ -1327,6 +1327,10 @@ SBL_CFLAGS += -DSBL_ENABLE_PLL
 SBL_CFLAGS += -DSBL_ENABLE_CLOCKS
 SBL_CFLAGS += -DSBL_ENABLE_DDR
 
+ifeq ($(SOC), $(filter $(SOC), j721e))
+SBL_CFLAGS += -DSBL_ENABLE_SERDES
+endif
+
 ############################################
 # DISABLING the options above this caption
 # improves boot time at the cost of moving