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raw | patch | inline | side by side (parent: 4c32fe3)
raw | patch | inline | side by side (parent: 4c32fe3)
author | Don Dominic <a0486429@ti.com> | |
Thu, 5 Nov 2020 17:39:21 +0000 (23:09 +0530) | ||
committer | Sivaraj R <sivaraj@ti.com> | |
Fri, 6 Nov 2020 03:13:08 +0000 (21:13 -0600) |
- As per BoardCfg, there no HC Block Copy Channel assigned for any core.
- In this case, use the resource assigned for HC RX/TX channels
- to test various HC Block Copy testcases.
- This is with the assumption that, the range of this resources are same
- for both RX and TX High Capacity channels
- Also remove macors for START of resource, since its no longer used to override rm prms.
Signed-off-by: Don Dominic <a0486429@ti.com>
- In this case, use the resource assigned for HC RX/TX channels
- to test various HC Block Copy testcases.
- This is with the assumption that, the range of this resources are same
- for both RX and TX High Capacity channels
- Also remove macors for START of resource, since its no longer used to override rm prms.
Signed-off-by: Don Dominic <a0486429@ti.com>
diff --git a/packages/ti/drv/udma/unit_test/udma_ut/src/soc/am65xx/udma_test_soc.h b/packages/ti/drv/udma/unit_test/udma_ut/src/soc/am65xx/udma_test_soc.h
index 1ab390ff2c2b6afa113d9721b2d0b743c5a690a4..8e170826b19845e9946c612127ba807dc77ee120 100644 (file)
#define UDMA_TEST_INST_ID_MAIN_BC (UDMA_INST_ID_MAIN_0)
#define UDMA_TEST_INST_ID_MCU_BC (UDMA_INST_ID_MCU_0)
-#define UDMA_TEST_RF_MAIN_BC_HC (0U)
+#define UDMA_TEST_RF_MAIN_BC_HC (UDMA_TEST_RF_SOC | UDMA_TEST_RF_CORE_ALL | UDMA_TEST_RF_CFG_DEF)
#define UDMA_TEST_RF_MAIN_BC (UDMA_TEST_RF_SOC | UDMA_TEST_RF_CORE_ALL | UDMA_TEST_RF_CFG_DEF)
-#define UDMA_TEST_RF_MCU_BC_HC (0U)
+#define UDMA_TEST_RF_MCU_BC_HC (UDMA_TEST_RF_SOC | UDMA_TEST_RF_CORE_MCU1_0 | UDMA_TEST_RF_CFG_DEF)
#define UDMA_TEST_RF_MCU_BC (UDMA_TEST_RF_SOC | UDMA_TEST_RF_CORE_ALL | UDMA_TEST_RF_CFG_DEF)
#define UDMA_TEST_RF_MCU_BC_INTERNAL_MEM (UDMA_TEST_RF_MCU_BC)
#define UDMA_TEST_RF_DRU (UDMA_TEST_RF_SOC | UDMA_TEST_RF_CORE_ALL | UDMA_TEST_RF_CFG_DEF)
#define UDMA_TEST_RF_FLOW (UDMA_TEST_RF_SOC | UDMA_TEST_RF_CORE_ALL | UDMA_TEST_RF_CFG_DEF)
-#define UDMA_TEST_MAIN_UHC_START (0U)
-#define UDMA_TEST_MCU_UHC_START (0U)
#if defined (BUILD_MPU1_0)
#define UDMA_TEST_RF_CORE (UDMA_TEST_RF_CORE_MPU1_0)
#define UDMA_TEST_MAX_MAIN_BC_UHC_CH (0U)
-#define UDMA_TEST_MAX_MAIN_BC_HC_CH (0U)
+#define UDMA_TEST_MAX_MAIN_BC_HC_CH (2U)
#define UDMA_TEST_MAX_MAIN_BC_CH (4U)
#define UDMA_TEST_MAX_MCU_BC_UHC_CH (0U)
#define UDMA_TEST_MAX_MCU_BC_HC_CH (0U)
#define UDMA_TEST_MAX_MCU_BC_CH (2U)
#define UDMA_TEST_MAX_DRU_CH (4U)
-#define UDMA_TEST_MAIN_HC_START (0U)
-#define UDMA_TEST_MCU_HC_START (0U)
#endif
#if defined (BUILD_MCU1_0)
#define UDMA_TEST_RF_CORE (UDMA_TEST_RF_CORE_MCU1_0)
#define UDMA_TEST_MAX_MAIN_BC_UHC_CH (0U)
-#define UDMA_TEST_MAX_MAIN_BC_HC_CH (0U)
+#define UDMA_TEST_MAX_MAIN_BC_HC_CH (2U)
#define UDMA_TEST_MAX_MAIN_BC_CH (4U)
#define UDMA_TEST_MAX_MCU_BC_UHC_CH (0U)
-#define UDMA_TEST_MAX_MCU_BC_HC_CH (0U)
+#define UDMA_TEST_MAX_MCU_BC_HC_CH (2U)
#define UDMA_TEST_MAX_MCU_BC_CH (4U)
#define UDMA_TEST_MAX_DRU_CH (4U)
-#define UDMA_TEST_MAIN_HC_START (0U)
-#define UDMA_TEST_MCU_HC_START (0U)
#endif
#if defined (BUILD_MCU1_1)
#define UDMA_TEST_RF_CORE (UDMA_TEST_RF_CORE_MCU1_1)
#define UDMA_TEST_MAX_MAIN_BC_UHC_CH (0U)
-#define UDMA_TEST_MAX_MAIN_BC_HC_CH (0U)
+#define UDMA_TEST_MAX_MAIN_BC_HC_CH (2U)
#define UDMA_TEST_MAX_MAIN_BC_CH (2U)
#define UDMA_TEST_MAX_MCU_BC_UHC_CH (0U)
#define UDMA_TEST_MAX_MCU_BC_HC_CH (0U)
#define UDMA_TEST_MAX_MCU_BC_CH (2U)
#define UDMA_TEST_MAX_DRU_CH (4U)
-#define UDMA_TEST_MAIN_HC_START (0U)
-#define UDMA_TEST_MCU_HC_START (0U)
#endif
#define UDMA_TEST_MAIN_BC_TCNAME_PREFIX "Main NAVSS "
diff --git a/packages/ti/drv/udma/unit_test/udma_ut/src/soc/j7200/udma_test_soc.h b/packages/ti/drv/udma/unit_test/udma_ut/src/soc/j7200/udma_test_soc.h
index b4d62557450f0834a2cf783e395798330daa2b90..23b531b459f2b3f9a2657eaa308a710c5ca151c2 100644 (file)
#define UDMA_TEST_INST_ID_MAIN_BC (UDMA_INST_ID_MAIN_0)
#define UDMA_TEST_INST_ID_MCU_BC (UDMA_INST_ID_MCU_0)
-#define UDMA_TEST_RF_MAIN_BC_HC (0U)
+#define UDMA_TEST_RF_MAIN_BC_HC (UDMA_TEST_RF_SOC | \
+ UDMA_TEST_RF_CORE_MPU1_0 | \
+ UDMA_TEST_RF_CORE_MCU2_0 | \
+ UDMA_TEST_RF_CFG_DEF)
#define UDMA_TEST_RF_MAIN_BC (UDMA_TEST_RF_SOC | UDMA_TEST_RF_CORE_ALL | UDMA_TEST_RF_CFG_DEF)
#define UDMA_TEST_RF_MCU_BC_HC (0U)
#define UDMA_TEST_RF_MCU_BC (UDMA_TEST_RF_SOC | \
#define UDMA_TEST_RF_CHAIN (UDMA_TEST_RF_SOC | UDMA_TEST_RF_CORE_ALL | UDMA_TEST_RF_CFG_DEF)
/* Multipe task testcases - some have only one instance. Doesn't make sense to run from 1 task */
-#define UDMA_TEST_RF_MAIN_BC_HC_MT (UDMA_TEST_RF_MAIN_BC_HC)
+#define UDMA_TEST_RF_MAIN_BC_HC_MT (0U)
#define UDMA_TEST_RF_MAIN_BC_MT (UDMA_TEST_RF_MAIN_BC)
-#define UDMA_TEST_RF_MCU_BC_HC_MT (UDMA_TEST_RF_MCU_BC_HC)
+#define UDMA_TEST_RF_MCU_BC_HC_MT (0U)
/* Temp disable MCU NAVSS MT testcase on mpu1_0 until PDK-6611 is resolved
#define UDMA_TEST_RF_MCU_BC_MT (UDMA_TEST_RF_MCU_BC)
*/
#define UDMA_TEST_RF_MAIN_BC_PACING (UDMA_TEST_RF_MAIN_BC)
#define UDMA_TEST_RF_MAIN_BC_PAUSE (UDMA_TEST_RF_MAIN_BC)
-#define UDMA_TEST_MAIN_UHC_START (0U)
-#define UDMA_TEST_MCU_UHC_START (0U)
#if defined (BUILD_MPU1_0)
#define UDMA_TEST_RF_CORE (UDMA_TEST_RF_CORE_MPU1_0)
#define UDMA_TEST_MAX_MAIN_BC_UHC_CH (0U)
-#define UDMA_TEST_MAX_MAIN_BC_HC_CH (0U)
+#define UDMA_TEST_MAX_MAIN_BC_HC_CH (1U)
#define UDMA_TEST_MAX_MAIN_BC_CH (4U)
#define UDMA_TEST_MAX_MCU_BC_UHC_CH (0U)
#define UDMA_TEST_MAX_MCU_BC_HC_CH (0U)
#define UDMA_TEST_MAX_MCU_BC_CH (3U)
#define UDMA_TEST_MAX_DRU_CH (0U)
-#define UDMA_TEST_MAIN_HC_START (0U)
-#define UDMA_TEST_MCU_HC_START (0U)
#endif
#if defined (BUILD_MCU2_0)
#define UDMA_TEST_RF_CORE (UDMA_TEST_RF_CORE_MCU2_0)
#define UDMA_TEST_MAX_MAIN_BC_UHC_CH (0U)
-#define UDMA_TEST_MAX_MAIN_BC_HC_CH (0U)
+#define UDMA_TEST_MAX_MAIN_BC_HC_CH (1U)
#define UDMA_TEST_MAX_MAIN_BC_CH (2U)
#define UDMA_TEST_MAX_MCU_BC_UHC_CH (0U)
#define UDMA_TEST_MAX_MCU_BC_HC_CH (0U)
#define UDMA_TEST_MAX_MCU_BC_CH (2U)
#define UDMA_TEST_MAX_DRU_CH (0U)
-#define UDMA_TEST_MAIN_HC_START (0U)
-#define UDMA_TEST_MCU_HC_START (0U)
#endif
#if defined (BUILD_MCU2_1)
#define UDMA_TEST_RF_CORE (UDMA_TEST_RF_CORE_MCU2_1)
#define UDMA_TEST_MAX_MCU_BC_HC_CH (0U)
#define UDMA_TEST_MAX_MCU_BC_CH (2U)
#define UDMA_TEST_MAX_DRU_CH (0U)
-#define UDMA_TEST_MAIN_HC_START (0U)
-#define UDMA_TEST_MCU_HC_START (0U)
#endif
#if defined (BUILD_MCU1_0)
#define UDMA_TEST_RF_CORE (UDMA_TEST_RF_CORE_MCU1_0)
#define UDMA_TEST_MAX_MAIN_BC_HC_CH (0U)
#define UDMA_TEST_MAX_MAIN_BC_CH (2U)
#define UDMA_TEST_MAX_MCU_BC_UHC_CH (0U)
-#define UDMA_TEST_MAX_MCU_BC_HC_CH (0U)
+#define UDMA_TEST_MAX_MCU_BC_HC_CH (1U)
#define UDMA_TEST_MAX_MCU_BC_CH (2U)
#define UDMA_TEST_MAX_DRU_CH (0U)
-#define UDMA_TEST_MAIN_HC_START (0U)
-#define UDMA_TEST_MCU_HC_START (0U)
#endif
#if defined (BUILD_MCU1_1)
#define UDMA_TEST_RF_CORE (UDMA_TEST_RF_CORE_MCU1_1)
#define UDMA_TEST_MAX_MCU_BC_HC_CH (0U)
#define UDMA_TEST_MAX_MCU_BC_CH (2U)
#define UDMA_TEST_MAX_DRU_CH (0U)
-#define UDMA_TEST_MAIN_HC_START (0U)
-#define UDMA_TEST_MCU_HC_START (0U)
#endif
#define UDMA_TEST_MAIN_BC_TCNAME_PREFIX "Main NAVSS "
diff --git a/packages/ti/drv/udma/unit_test/udma_ut/src/soc/j721e/udma_test_soc.h b/packages/ti/drv/udma/unit_test/udma_ut/src/soc/j721e/udma_test_soc.h
index 24d009226a91ee788e3a0e922df4de7940257b72..ab5c49fc925dba542f5899b8a147b4cd5fb5577d 100644 (file)
#define UDMA_TEST_INST_ID_MAIN_BC (UDMA_INST_ID_MAIN_0)
#define UDMA_TEST_INST_ID_MCU_BC (UDMA_INST_ID_MCU_0)
-#define UDMA_TEST_RF_MAIN_BC_HC (0U)
+#define UDMA_TEST_RF_MAIN_BC_HC (UDMA_TEST_RF_SOC | \
+ UDMA_TEST_RF_CORE_MPU1_0 | \
+ UDMA_TEST_RF_CORE_MCU2_0 | \
+ UDMA_TEST_RF_CFG_DEF)
#define UDMA_TEST_RF_MAIN_BC (UDMA_TEST_RF_SOC | UDMA_TEST_RF_CORE_ALL | UDMA_TEST_RF_CFG_DEF)
-#define UDMA_TEST_RF_MCU_BC_HC (0U)
+#define UDMA_TEST_RF_MCU_BC_HC (UDMA_TEST_RF_SOC | \
+ UDMA_TEST_RF_CORE_MCU1_0 | \
+ UDMA_TEST_RF_CFG_DEF)
#define UDMA_TEST_RF_MCU_BC (UDMA_TEST_RF_SOC | \
UDMA_TEST_RF_CORE_MPU1_0 | \
UDMA_TEST_RF_CORE_MCU2_0 | \
#define UDMA_TEST_RF_MAIN_BC_PACING (UDMA_TEST_RF_MAIN_BC)
#define UDMA_TEST_RF_MAIN_BC_PAUSE (UDMA_TEST_RF_MAIN_BC)
-#define UDMA_TEST_MAIN_UHC_START (0U)
-#define UDMA_TEST_MCU_UHC_START (0U)
#if defined (BUILD_MPU1_0)
#define UDMA_TEST_RF_CORE (UDMA_TEST_RF_CORE_MPU1_0)
#define UDMA_TEST_MAX_MAIN_BC_UHC_CH (0U)
-#define UDMA_TEST_MAX_MAIN_BC_HC_CH (0U)
+#define UDMA_TEST_MAX_MAIN_BC_HC_CH (4U)
#define UDMA_TEST_MAX_MAIN_BC_CH (4U)
#define UDMA_TEST_MAX_MCU_BC_UHC_CH (0U)
#define UDMA_TEST_MAX_MCU_BC_HC_CH (0U)
#define UDMA_TEST_MAX_MCU_BC_CH (3U)
#define UDMA_TEST_MAX_DRU_CH (0U)
-#define UDMA_TEST_MAIN_HC_START (0U)
-#define UDMA_TEST_MCU_HC_START (0U)
#endif
#if defined (BUILD_MCU2_0)
#define UDMA_TEST_RF_CORE (UDMA_TEST_RF_CORE_MCU2_0)
#define UDMA_TEST_MAX_MAIN_BC_UHC_CH (0U)
-#define UDMA_TEST_MAX_MAIN_BC_HC_CH (0U)
+#define UDMA_TEST_MAX_MAIN_BC_HC_CH (4U)
#define UDMA_TEST_MAX_MAIN_BC_CH (4U)
#define UDMA_TEST_MAX_MCU_BC_UHC_CH (0U)
#define UDMA_TEST_MAX_MCU_BC_HC_CH (0U)
#define UDMA_TEST_MAX_MCU_BC_CH (1U)
#define UDMA_TEST_MAX_DRU_CH (2U)
-#define UDMA_TEST_MAIN_HC_START (0U)
-#define UDMA_TEST_MCU_HC_START (0U)
#endif
#if defined (BUILD_MCU2_1)
#define UDMA_TEST_RF_CORE (UDMA_TEST_RF_CORE_MCU2_1)
#define UDMA_TEST_MAX_MCU_BC_HC_CH (0U)
#define UDMA_TEST_MAX_MCU_BC_CH (1U)
#define UDMA_TEST_MAX_DRU_CH (0U)
-#define UDMA_TEST_MAIN_HC_START (0U)
-#define UDMA_TEST_MCU_HC_START (0U)
#endif
#if defined (BUILD_MCU3_0)
#define UDMA_TEST_RF_CORE (UDMA_TEST_RF_CORE_MCU3_0)
#define UDMA_TEST_MAX_MCU_BC_HC_CH (0U)
#define UDMA_TEST_MAX_MCU_BC_CH (1U)
#define UDMA_TEST_MAX_DRU_CH (0U)
-#define UDMA_TEST_MAIN_HC_START (0U)
-#define UDMA_TEST_MCU_HC_START (0U)
#endif
#if defined (BUILD_MCU3_1)
#define UDMA_TEST_RF_CORE (UDMA_TEST_RF_CORE_MCU3_1)
#define UDMA_TEST_MAX_MCU_BC_HC_CH (0U)
#define UDMA_TEST_MAX_MCU_BC_CH (1U)
#define UDMA_TEST_MAX_DRU_CH (0U)
-#define UDMA_TEST_MAIN_HC_START (0U)
-#define UDMA_TEST_MCU_HC_START (0U)
#endif
#if defined (BUILD_C7X_1)
#define UDMA_TEST_RF_CORE (UDMA_TEST_RF_CORE_C7X_1)
#define UDMA_TEST_MAX_MCU_BC_HC_CH (0U)
#define UDMA_TEST_MAX_MCU_BC_CH (1U)
#define UDMA_TEST_MAX_DRU_CH (4U)
-#define UDMA_TEST_MAIN_HC_START (0U)
-#define UDMA_TEST_MCU_HC_START (0U)
#endif
#if defined (BUILD_C66X_1)
#define UDMA_TEST_RF_CORE (UDMA_TEST_RF_CORE_C66X_1)
#define UDMA_TEST_MAX_MCU_BC_HC_CH (0U)
#define UDMA_TEST_MAX_MCU_BC_CH (1U)
#define UDMA_TEST_MAX_DRU_CH (4U)
-#define UDMA_TEST_MAIN_HC_START (0U)
-#define UDMA_TEST_MCU_HC_START (0U)
#endif
#if defined (BUILD_C66X_2)
#define UDMA_TEST_RF_CORE (UDMA_TEST_RF_CORE_C66X_2)
#define UDMA_TEST_MAX_MCU_BC_HC_CH (0U)
#define UDMA_TEST_MAX_MCU_BC_CH (1U)
#define UDMA_TEST_MAX_DRU_CH (4U)
-#define UDMA_TEST_MAIN_HC_START (0U)
-#define UDMA_TEST_MCU_HC_START (0U)
#endif
#if defined (BUILD_MCU1_0)
#define UDMA_TEST_RF_CORE (UDMA_TEST_RF_CORE_MCU1_0)
#define UDMA_TEST_MAX_MAIN_BC_HC_CH (0U)
#define UDMA_TEST_MAX_MAIN_BC_CH (2U)
#define UDMA_TEST_MAX_MCU_BC_UHC_CH (0U)
-#define UDMA_TEST_MAX_MCU_BC_HC_CH (0U)
+#define UDMA_TEST_MAX_MCU_BC_HC_CH (2U)
#define UDMA_TEST_MAX_MCU_BC_CH (2U)
#define UDMA_TEST_MAX_DRU_CH (0U)
-#define UDMA_TEST_MAIN_HC_START (0U)
-#define UDMA_TEST_MCU_HC_START (0U)
#endif
#if defined (BUILD_MCU1_1)
#define UDMA_TEST_RF_CORE (UDMA_TEST_RF_CORE_MCU1_1)
#define UDMA_TEST_MAX_MCU_BC_HC_CH (0U)
#define UDMA_TEST_MAX_MCU_BC_CH (0U)
#define UDMA_TEST_MAX_DRU_CH (0U)
-#define UDMA_TEST_MAIN_HC_START (0U)
-#define UDMA_TEST_MCU_HC_START (0U)
#endif
#define UDMA_TEST_MAIN_BC_TCNAME_PREFIX "Main NAVSS "
diff --git a/packages/ti/drv/udma/unit_test/udma_ut/src/udma_test_common.c b/packages/ti/drv/udma/unit_test/udma_ut/src/udma_test_common.c
index ecc606fb668765656811f236e696315067993ee0..1f36ec60e20a6f191a868e170f2bcd39ddce225a 100755 (executable)
initPrms.virtToPhyFxn = &Udma_appVirtToPhyFxn;
initPrms.phyToVirtFxn = &Udma_appPhyToVirtFxn;
initPrms.printFxn = &udmaDrvPrint;
+#if (UDMA_SOC_CFG_UDMAP_PRESENT == 1)
+ /* As per BoardCfg, there no HC Block Copy Channel assigned for any core.
+ * In this case, use the resource assigned for HC RX/TX channels
+ * to test various HC Block Copy testcases.
+ * This is with the assumption that, the range of this resources are same
+ * for both RX and TX High Capacity channels. */
+ initPrms.rmInitPrms.startBlkCopyHcCh = initPrms.rmInitPrms.startRxHcCh;
+ initPrms.rmInitPrms.numBlkCopyHcCh = initPrms.rmInitPrms.numRxHcCh;
+#endif
retVal += Udma_init(drvHandle, &initPrms);
if(UDMA_SOK != retVal)
{