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raw | patch | inline | side by side (parent: ae256cf)
| author | M V Pratap Reddy <x0257344@ti.com> | |
| Thu, 31 Mar 2022 16:10:50 +0000 (21:40 +0530) | ||
| committer | Rishabh Garg <rishabh@ti.com> | |
| Thu, 28 Apr 2022 08:38:22 +0000 (03:38 -0500) |
- Merging the board library changes from bringup branch to master
49 files changed:
index 642483fd9a37add54213517a2c18904a97d584bd..21e66802b45f72b70316292bcbc61d4abf713b42 100755 (executable)
#define BOARD_INIT_DEFAULT BOARD_INIT_ALL
#define BOARD_INIT_CPSW5G_ETH_PHY (BOARD_INIT_CPSW9G_ETH_PHY)
#define BOARD_INIT_ENETCTRL_CPSW5G (BOARD_INIT_ENETCTRL_CPSW9G)
+#define BOARD_INIT_CPSW2G_MAIN_ETH_PHY (BOARD_INIT_CPSW9G_ETH_PHY)
+#define BOARD_INIT_ENETCTRL_CPSW2G_MAIN (BOARD_INIT_ENETCTRL_CPSW9G)
#define BOARD_DEINIT_ALL (0xFFFFFFFFU)
#define BOARD_DEINIT_LOCK_MMR (1 << 1U)
index 3e247e8e18cc15b534e0336365e6ca6ebb3145d1..cb4b9672a06871eca9cce7dfebae4fce0e3970da 100644 (file)
/*
- * Copyright (c) 2017-2020, Texas Instruments Incorporated
+ * Copyright (c) 2017-2022, Texas Instruments Incorporated
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
#elif defined (j7200_evm)
#include <ti/board/src/j7200_evm/include/board_cfg.h>
+#elif defined (j721s2_evm)
+#include <ti/board/src/j721s2_evm/include/board_cfg.h>
+#include <ti/board/src/j721s2_evm/include/board_pinmux.h>
+
#elif defined (am64x_evm)
#include <ti/board/src/am64x_evm/include/board_cfg.h>
#include <ti/board/src/am64x_evm/include/board_pinmux.h>
index 9e56b51b88d865f70b53af7facc7c97864fa8f06..779db527a10bea992f1529989d522b80155898c7 100644 (file)
#
-# Copyright (c) 2017-2020, Texas Instruments Incorporated
+# Copyright (c) 2017-2022, Texas Instruments Incorporated
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
board_lib_BOARDLIST = evmAM335x icev2AM335x iceAMIC110 skAM335x bbbAM335x evmAM437x idkAM437x skAM437x evmAM572x idkAM571x idkAM572x evmK2H evmK2K evmK2E evmK2L evmK2G iceK2G \
evmC6678 evmC6657 tda2xx-evm evmDRA75x tda2ex-evm evmDRA72x tda3xx-evm evmDRA78x evmOMAPL137 lcdkOMAPL138 idkAM574x am65xx_evm am65xx_idk j721e_sim j721e_qt \
- j721e_evm j7200_evm am64x_evm am64x_svb tpr12_evm tpr12_qt awr294x_evm
+ j721e_evm j7200_evm j721s2_evm am64x_evm am64x_svb tpr12_evm tpr12_qt awr294x_evm
board_lib_tda2xx_CORELIST = a15_0 ipu1_0 c66x
board_lib_tda2ex_CORELIST = a15_0 ipu1_0 c66x
board_lib_tda3xx_CORELIST = ipu1_0 c66x
board_lib_omapl138_CORELIST = arm9_0 c674x
board_lib_am65xx_CORELIST = mpu1_0 mcu1_0 mcu1_1
board_lib_j721e_CORELIST = mpu1_0 mcu1_0 mcu1_1 mcu2_0 mcu2_1 mcu3_0 mcu3_1 c66xdsp_1 c66xdsp_2 c7x_1
+board_lib_j721s2_CORELIST = mpu1_0 mcu1_0 mcu1_1 mcu2_0 mcu2_1 mcu3_0 mcu3_1 c7x_1 c7x_2 mpu1_1
board_lib_j7200_CORELIST = mpu1_0 mcu1_0 mcu1_1 mcu2_0 mcu2_1
board_lib_am64x_CORELIST = mpu1_0 mcu1_0 mcu1_1 mcu2_0 mcu2_1 m4f_0
board_lib_tpr12_CORELIST = mcu1_0 c66xdsp_1
index 340d250a4d3c00fe47339e900b9d9b02db161c29..fb72c312dcaa43656912aa2b63fed98c8c98fc31 100644 (file)
#
-# Copyright (c) 2016-2020, Texas Instruments Incorporated
+# Copyright (c) 2016-2022, Texas Instruments Incorporated
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
SRCS_COMMON += board.c
endif
-ifeq ($(BOARD),$(filter $(BOARD),evmAM335x icev2AM335x iceAMIC110 skAM335x bbbAM335x evmAM437x idkAM437x skAM437x evmAM572x idkAM571x idkAM572x evmK2H evmK2K evmK2E evmK2L iceK2G evmC6678 evmC6657 evmOMAPL137 lcdkOMAPL138 idkAM574x evmDRA72x evmDRA75x evmDRA78x evmTDAxx j721e_sim j721e_qt j7200_evm tpr12_evm tpr12_qt awr294x_evm))
+ifeq ($(BOARD),$(filter $(BOARD),evmAM335x icev2AM335x iceAMIC110 skAM335x bbbAM335x evmAM437x idkAM437x skAM437x evmAM572x idkAM571x idkAM572x evmK2H evmK2K evmK2E evmK2L iceK2G evmC6678 evmC6657 evmOMAPL137 lcdkOMAPL138 idkAM574x evmDRA72x evmDRA75x evmDRA78x evmTDAxx j721e_sim j721e_qt j721s2_evm j7200_evm tpr12_evm tpr12_qt awr294x_evm))
# Board stub function enabled for all the boards except evmK2G
SRCS_COMMON += boardStub.c
endif
PACKAGE_SRCS_COMMON += src/devices
endif
+ifeq ($(BOARD),$(filter $(BOARD), j721s2_evm))
+CFLAGS_LOCAL_COMMON = $(PDK_CFLAGS)
+include $(PDK_BOARD_COMP_PATH)/src/$(BOARD)/src_files_$(BOARD).mk
+include $(PDK_BOARD_COMP_PATH)/src/flash/src_files_flash.mk
+include $(PDK_BOARD_COMP_PATH)/src/devices/src_files_devices.mk
+PACKAGE_SRCS_COMMON += src/$(BOARD)
+PACKAGE_SRCS_COMMON += src/devices
+endif
+
ifeq ($(BOARD),$(filter $(BOARD), j7200_evm))
CFLAGS_LOCAL_COMMON = $(PDK_CFLAGS)
include $(PDK_BOARD_COMP_PATH)/src/$(BOARD)/src_files_$(BOARD).mk
PACKAGE_SRCS_COMMON += board_cfg.h build
PACKAGE_SRCS_COMMON += config_mk.bld package.bld package.xdc package.xs
PACKAGE_SRCS_COMMON += Settings.xdc.xdt utils.xs
-ifeq ($(BOARD),$(filter $(BOARD), j721e_sim j721e_qt j721e_evm j7200_evm tpr12_evm tpr12_qt awr294x_evm))
+ifeq ($(BOARD),$(filter $(BOARD), j721e_sim j721e_qt j721e_evm j7200_evm j721s2_evm tpr12_evm tpr12_qt awr294x_evm))
PACKAGE_SRCS_COMMON += src/board.c src/boardStub.c src/Module.xs
PACKAGE_SRCS_COMMON += src/src_files_lld.mk src/src_files_starterware.mk
PACKAGE_SRCS_COMMON += diag/common/$(SOC)
diff --git a/packages/ti/board/src/devices/board_devices.h b/packages/ti/board/src/devices/board_devices.h
index 299cff995f04b1ac40cf82923c693b5252510e61..66ceaca3085cf39aa827f92100cea4bbaf9a75db 100755 (executable)
/******************************************************************************\r
- * Copyright (c) 2019-2020 Texas Instruments Incorporated - http://www.ti.com\r
+ * Copyright (c) 2019-2022 Texas Instruments Incorporated - http://www.ti.com\r
*\r
* Redistribution and use in source and binary forms, with or without\r
* modification, are permitted provided that the following conditions\r
#include <ti/board/src/devices/fpd/ds90ub926.h>\r
#include <ti/board/src/devices/combos/ds90ub92x_afe8310.h>\r
#endif\r
-
-#if defined(am65xx_evm) || defined(am65xx_idk)
-#include <ti/board/src/devices/pmic/tps62363.h>
-#endif
+\r
+#if defined(am65xx_evm) || defined(am65xx_idk)\r
+#include <ti/board/src/devices/pmic/tps62363.h>\r
+#endif\r
+\r
+#if defined(j721s2_evm)\r
+#include <ti/board/src/devices/common/common.h>\r
+\r
+#include <ti/board/src/devices/audio/pcm3168A.h>\r
+#include <ti/board/src/devices/fpd/ds90ub953.h>\r
+#include <ti/board/src/devices/fpd/ds90ub960.h>\r
+#include <ti/board/src/devices/fpd/ds90ub9702.h>\r
+#endif\r
\r
#ifdef __cplusplus\r
extern "C" {\r
diff --git a/packages/ti/board/src/devices/fpd/ds90ub960.c b/packages/ti/board/src/devices/fpd/ds90ub960.c
index da1a5eaf31773335e44a762f01b3741272e845cf..e49dbf9b185adf0d247ec569c44eb2c66a83f134 100755 (executable)
//J7_TODO: Need to update to make it generic across the devices and platforms
if (csiInst == BOARD_CSI_INST_0)
{
+#if defined (SOC_J721S2)
+ *chNum = 5U;
+#endif
+#if defined (SOC_J721E)
*chNum = 6U;
+#endif
*i2cAddr = 0x3DU;
}
else if (csiInst == BOARD_CSI_INST_1)
{
+#if defined (SOC_J721S2)
+ *chNum = 5U;
+#endif
+#if defined (SOC_J721E)
*chNum = 6U;
+#endif
*i2cAddr = 0x36U;
}
else
diff --git a/packages/ti/board/src/devices/src_files_devices.mk b/packages/ti/board/src/devices/src_files_devices.mk
index 32145c212757523a1b5c20c87a1009e4c41c22b0..4f42f6284d7148fe93b77236d1039a38f6649d43 100755 (executable)
SRCS_COMMON += common.c pcm3168A.c ds90ub925.c ds90ub926.c ds90ub92x_afe8310.c
endif
+ifeq ($(BOARD),$(filter $(BOARD), j721s2_evm))
+SRCDIR += src/devices/audio src/devices/common src/devices/fpd src/devices/sensors
+INCDIR += src/devices/audio src/devices/common src/devices/fpd src/devices/sensors
+SRCS_COMMON += common.c pcm3168A.c ds90ub953.c ds90ub960.c imx390.c ds90ub9702.c
+endif
+
ifeq ($(BOARD),$(filter $(BOARD), am65xx_evm am65xx_idk))
SRCDIR += src/devices/common src/devices/pmic
INCDIR += src/devices/common src/devices/pmic
index 7b827490b3abcb696a83a394f9646bfad77ac442..b090ed3350f180daf5223cea3daeeca90f813533 100644 (file)
{
flashIntf = BOARD_FLASH_NOR_OSPI;
}
- else if(BOARD_FLASH_ID_S71KS512S)
+ else if(deviceId == BOARD_FLASH_ID_S71KS512S)
{
flashIntf = BOARD_FLASH_NOR_HPF;
}
+ else if(deviceId == BOARD_FLASH_ID_W35N01JWTBAG)
+ {
+ flashIntf = BOARD_FLASH_NAND_OSPI;
+ }
else
{
/* Unknown flash type */
@@ -172,29 +176,31 @@ Board_flashHandle Board_flashOpen(uint32_t deviceId, uint32_t portNum, void *par
return (Board_flashHandle)&(Board_flashInfo);
}
-#elif defined (BOARD_NAND_FLASH_IN)
- NAND_HANDLE flashHandle;
+#endif
+#if defined (BOARD_NAND_FLASH_IN)
+ NAND_HANDLE nandFlashHandle;
NAND_Info *nandInfo;
if ((deviceId == BOARD_FLASH_ID_MT29F4G08ABAEAWP) || \
- (deviceId == BOARD_FLASH_ID_MT29F4G16ABAFAH) || \
- (deviceId == BOARD_FLASH_ID_MT29F8G16ABACAWP))
+ (deviceId == BOARD_FLASH_ID_MT29F4G16ABAFAH) || \
+ (deviceId == BOARD_FLASH_ID_MT29F8G16ABACAWP) || \
+ (deviceId == BOARD_FLASH_ID_W35N01JWTBAG))
{
/* Open the Nand flash */
- flashHandle = NAND_open(flashIntf, portNum, params);
- if (!flashHandle)
+ nandFlashHandle = NAND_open(flashIntf, portNum, params);
+ if (!nandFlashHandle)
{
return 0;
}
- nandInfo = (NAND_Info *)flashHandle;
+ nandInfo = (NAND_Info *)nandFlashHandle;
if (deviceId != nandInfo->deviceId)
{
- NAND_close(flashHandle);
+ NAND_close(nandFlashHandle);
return 0;
}
- flashInfo->flashHandle = flashHandle;
+ flashInfo->flashHandle = nandFlashHandle;
flashInfo->manufacturer_id = nandInfo->manufacturerId;
flashInfo->device_id = nandInfo->deviceId;
flashInfo->type = BOARD_FLASH_NAND;
{
NOR_close(flashInfo->flashHandle);
}
-#elif defined (BOARD_NAND_FLASH_IN)
+#endif
+#if defined (BOARD_NAND_FLASH_IN)
if ((flashInfo->device_id == BOARD_FLASH_ID_MT29F4G08ABAEAWP) || \
- (flashInfo->device_id == BOARD_FLASH_ID_MT29F4G16ABAFAH) || \
- (flashInfo->device_id == BOARD_FLASH_ID_MT29F8G16ABACAWP))
+ (flashInfo->device_id == BOARD_FLASH_ID_MT29F4G16ABAFAH) || \
+ (flashInfo->device_id == BOARD_FLASH_ID_MT29F8G16ABACAWP) || \
+ (flashInfo->device_id == BOARD_FLASH_ID_W35N01JWTBAG))
{
NAND_close(flashInfo->flashHandle);
}
}
return BOARD_FLASH_EOK;
}
-#elif defined (BOARD_NAND_FLASH_IN)
+#endif
+#if defined (BOARD_NAND_FLASH_IN)
if ((flashInfo->device_id == BOARD_FLASH_ID_MT29F4G08ABAEAWP) || \
- (flashInfo->device_id == BOARD_FLASH_ID_MT29F4G16ABAFAH) || \
- (flashInfo->device_id == BOARD_FLASH_ID_MT29F8G16ABACAWP))
+ (flashInfo->device_id == BOARD_FLASH_ID_MT29F4G16ABAFAH) || \
+ (flashInfo->device_id == BOARD_FLASH_ID_MT29F8G16ABACAWP) || \
+ (flashInfo->device_id == BOARD_FLASH_ID_W35N01JWTBAG))
{
if (NAND_read(flashInfo->flashHandle, offset, len, buf) \
!= NAND_PASS)
(flashInfo->device_id == BOARD_FLASH_ID_GD25B64CW2G) || \
(flashInfo->device_id == BOARD_FLASH_ID_W25Q16FWSF) || \
(flashInfo->device_id == BOARD_FLASH_ID_MX25V1635F) || \
- (flashInfo->device_id == BOARD_FLASH_ID_MT28EW256ABA)
+ (flashInfo->device_id == BOARD_FLASH_ID_MT28EW256ABA) || \
+ (flashInfo->device_id == BOARD_FLASH_ID_W35N01JWTBAG)
)
{
block_count = flashInfo->block_count;
}
return BOARD_FLASH_EOK;
}
-#elif defined (BOARD_NAND_FLASH_IN)
+#endif
+#if defined (BOARD_NAND_FLASH_IN)
if ((flashInfo->device_id == BOARD_FLASH_ID_MT29F4G08ABAEAWP) || \
- (flashInfo->device_id == BOARD_FLASH_ID_MT29F4G16ABAFAH) || \
- (flashInfo->device_id == BOARD_FLASH_ID_MT29F8G16ABACAWP))
+ (flashInfo->device_id == BOARD_FLASH_ID_MT29F4G16ABAFAH) || \
+ (flashInfo->device_id == BOARD_FLASH_ID_MT29F8G16ABACAWP) || \
+ (flashInfo->device_id == BOARD_FLASH_ID_W35N01JWTBAG))
{
if (NAND_write(flashInfo->flashHandle, offset, len, buf) != NAND_PASS)
{
}
return BOARD_FLASH_EOK;
}
-#elif defined (BOARD_NAND_FLASH_IN)
+#endif
+#if defined (BOARD_NAND_FLASH_IN)
NAND_STATUS status;
if ((flashInfo->device_id == BOARD_FLASH_ID_MT29F4G08ABAEAWP) || \
- (flashInfo->device_id == BOARD_FLASH_ID_MT29F4G16ABAFAH) || \
- (flashInfo->device_id == BOARD_FLASH_ID_MT29F8G16ABACAWP))
+ (flashInfo->device_id == BOARD_FLASH_ID_MT29F4G16ABAFAH) || \
+ (flashInfo->device_id == BOARD_FLASH_ID_MT29F8G16ABACAWP) || \
+ (flashInfo->device_id == BOARD_FLASH_ID_W35N01JWTBAG))
{
if (flashInfo->bblist[blk_num] == NAND_BAD_BLOCK)
{
diff --git a/packages/ti/board/src/flash/include/board_flash.h b/packages/ti/board/src/flash/include/board_flash.h
index 930092a278678c8552f9b20149f01912b3b7ab45..ea6d011fccbd12b9dda3df55bc336398c6412ff7 100644 (file)
#if defined(BOARD_NOR_FLASH_IN)
#include <ti/board/src/flash/nor/nor.h>
-#elif defined (BOARD_NAND_FLASH_IN)
+#endif
+#if defined (BOARD_NAND_FLASH_IN)
#include <ti/board/src/flash/nand/nand.h>
-#else
#endif
/**
#define BOARD_FLASH_ID_MT29F8G16ABACAWP (0x2C00U) /* Device Id code 1 */
#define BOARD_FLASH_ID_MT28EW256ABA (0x227EU) /* Device Id code 1 */
#define BOARD_FLASH_ID_CY7C10612G (0)
+#define BOARD_FLASH_ID_W35N01JWTBAG (0xDC21U) /**< Winbond 1GB NAND flash */
/**
* @brief Board specific Flash Device Identifiers.
/**<NAND GPMC peripheral interface */
BOARD_FLASH_NAND_EMIF16,
/**<NAND EMIF16 peripheral interface */
+ BOARD_FLASH_NAND_OSPI,
+ /**<NAND OSPI peripheral interface */
BOARD_FLASH_NAND_INTF_MAX
/**<End of NAND peripheral interface */
} Board_flashNandPeriType;
diff --git a/packages/ti/board/src/flash/nand/device/w35n01jwtbag.h b/packages/ti/board/src/flash/nand/device/w35n01jwtbag.h
--- /dev/null
@@ -0,0 +1,121 @@
+/*
+ * Copyright (c) 2021, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ *
+ * \file w35n01jwtbag.h
+ *
+ * \brief This file contains W35N01JWTBAG NAND device definitions
+ *
+ *****************************************************************************/
+#ifndef W35N01JWTBAG_H_
+#define W35N01JWTBAG_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**************************************************************************
+ ** Macro Definitions
+ **************************************************************************/
+
+/** \brief FLASH device specific items (note: sizes are in bytes) */
+#define NAND_BLOCK_SIZE (256U * 1024U)
+#define NAND_SECTOR_SIZE (0U) /* TO DO */
+#define NAND_SIZE (128U * 1024U * 1024U)
+#define NAND_NUM_SECTORS (0U) /* TO DO */
+#define NAND_NUM_BLOCKS (NAND_SIZE / NAND_BLOCK_SIZE)
+#define NAND_PAGE_SIZE (4U * 1024U)
+#define NAND_NUM_PAGES_PER_BLOCK (NAND_BLOCK_SIZE / NAND_PAGE_SIZE)
+#define NAND_SPARE_AREA_SIZE (128U)
+
+/** \brief Flash device commands */
+#define NAND_CMD_RSTEN (0x66U)
+#define NAND_CMD_RST_MEM (0x99U)
+#define NAND_CMD_RDID (0x9FU)
+#define NAND_CMD_RDSR (0x0FU)
+#define NAND_CMD_WRITE_STATUS (0x1FU)
+#define NAND_CMD_VCR_READ (0x85U)
+#define NAND_CMD_WRITE_VCR (0x81U)
+#define NAND_CMD_WREN (0x06U)
+#define NAND_CMD_WR_DISABLE (0x04U)
+#define NAND_CMD_BBM (0xA1U)
+#define NAND_CMD_READ_BBM_LUT (0xA5U)
+#define NAND_CMD_LAST_ECC_ADD (0xA9U)
+#define NAND_CMD_BLOCK_ERASE (0xD8U)
+#define NAND_CMD_PAGE_READ (0x13U)
+#define NAND_CMD_READ (0x03U)
+#define NAND_CMD_FAST_READ (0x0BU)
+#define NAND_CMD_OCTAL_DDR_O_FAST_RD (0x8BU)
+#define NAND_CMD_OCTAL_IO_FAST_RD (0xCBU)
+#define NAND_CMD_FAST_READ_DDR (0x9DU)
+#define NAND_CMD_PAGE_PROG (0x84U)
+#define NAND_CMD_PAGE_PROG_EXECUTE (0x10U)
+#define NAND_CMD_EXT_OCTAL_FAST_PROG (0x82U)
+#define NAND_CMD_OCTAL_FAST_PROG (0xC4U)
+
+/** Dummy cycles for Read operation */
+#define NAND_OCTAL_READ_DUMMY_CYCLE (0x08U)
+#define NAND_OCTAL_READ_DUMMY_CYCLE_LC (0x08U)
+#define NAND_OCTAL_READ_DUMMY_CYCLE_INDAC (0x08U)
+#define NAND_OCTAL_READ_DUMMY_CYCLE_INDAC_LC (0x08U)
+#define NAND_SINGLE_READ_DUMMY_CYCLE (0x08U)
+#define NAND_SINGLE_READ_DUMMY_CYCLE_LC (0x08U)
+#define NAND_OCTAL_DDR_CMD_READ_DUMMY_CYCLE (0x08U)
+#define NAND_OCTAL_SDR_CMD_READ_DUMMY_CYCLE (0x08U)
+#define NAND_SINGLE_CMD_READ_DUMMY_CYCLE (0x08U)
+
+/** In Micro seconds */
+#define NAND_PAGE_PROG_TIMEOUT (1000U) /* TO DO */
+#define NAND_SECTOR_ERASE_TIMEOUT (1000U) /* TO DO */
+#define NAND_WRR_WRITE_TIMEOUT (1000U) /* TO DO */
+#define NAND_BULK_ERASE_TIMEOUT (1000U) /* TO DO */
+
+/* \brief Read ID command definitions */
+#define NAND_RDID_NUM_BYTES (0x03U)
+#define NAND_MANF_ID (0xEFU) /* Manufacturer ID */
+#define NAND_DEVICE_ID (0xDC21U) /* Device ID */
+
+/** Status Register, Write-in-Progress bit */
+#define NAND_SR3_ADDR (0xC0U)
+
+/** Status Register, Write-in-Progress bit */
+#define NAND_SR_WIP (1U << 0U)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* W35N01JWTBAG_H_ */
+
+/* Nothing past this point */
index 3fccb75e034ffacfe6febb7e7f3090808a8415a2..84ab202a2a148e3aacf6ad2687fa68f06a315bea 100644 (file)
{\r
&Nand_gpmcFxnTable\r
},\r
+ {\r
+ NULL\r
+ },\r
{\r
NULL\r
}\r
},\r
{\r
NULL\r
+ },\r
+ {\r
+ &Nand_ospiFxnTable\r
}\r
};\r
#endif\r
index 2ef86579ded71418d2a5cc2793987341248e69b8..16861ba9fdd8c1adae844014afe7c6ff561a9345 100644 (file)
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions\r
- * are met:\r
- *\r
- * * Redistributions of source code must retain the above copyright\r
- * notice, this list of conditions and the following disclaimer.\r
- *\r
- * * Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in the\r
- * documentation and/or other materials provided with the distribution.\r
- *\r
- * * Neither the name of Texas Instruments Incorporated nor the names of\r
- * its contributors may be used to endorse or promote products derived\r
- * from this software without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\r
- * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\r
- * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\r
- * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\r
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\r
- * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
- * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\r
- * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
- * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
- *\r
- */\r
-\r
-/**\r
- *\r
- * \file nand.h\r
- *\r
- * \brief This file contains structure, typedefs, functions and\r
- * prototypes used for NAND flash.\r
- *\r
- *****************************************************************************/\r
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ *
+ * \file nand.h
+ *
+ * \brief This file contains structure, typedefs, functions and
+ * prototypes used for NAND flash.
+ *
+ *****************************************************************************/
#ifndef NAND_H_
#define NAND_H_
#include <stdint.h>
#include <stddef.h>
-/**\r
- * @brief This type defines the handle returned to a NAND flash interface that is opened.\r
- * The handle must be used in all subsequent operations.\r
- *\r
- */\r
-typedef uint32_t NAND_HANDLE;\r
-\r
-/** NAND function return status */\r
-#define NAND_STATUS int32_t\r
-\r
-/** NAND return type macros */\r
-/** \brief On Success. */\r
-#define NAND_PASS (0U)\r
-\r
-/** \brief On Failure. */\r
-#define NAND_FAIL (-1U)\r
-\r
-/** \brief Error code for Timeout. */\r
-#define NAND_TIMEOUT (-2U)\r
-\r
-/** \brief Error code to indicate mode not supported. */\r
-#define NAND_MODE_NOT_SUPP (-3U)\r
-\r
-/** \brief Error code to indicate invalid parameter. */\r
-#define NAND_INVALID_PARAM (-4U)\r
-\r
-/** \brief Error code to indicate DMA operation failure. */\r
-#define NAND_DMA_FAIL (-5U)\r
-\r
-/** \brief Error code to indicate NAND device is Busy. */\r
-#define NAND_DEV_BUSY (-6U)\r
-\r
-/** \brief Error code to indicate NAND device is Write Protected. */\r
-#define NAND_DEV_PROTECTED (-7U)\r
-\r
-/** \brief Error code to indicate ECC error for the last access. */\r
-#define NAND_ECC_ERR (-8U)\r
-\r
-/** \brief Error code to indicate ECC error is corrected. */\r
-#define NAND_ECC_ERR_CORRECTED (-9U)\r
-\r
-/** \brief Error code to indicate Uncorrectable ecc errrors. */\r
-#define NAND_ECC_UNCORRECTABLE (-10U)\r
-\r
-/** \brief Error code to indicate Block is good to read/write. */\r
-#define NAND_BLOCK_GOOD (-11U)\r
-\r
-/** \brief Error code to indicate Block is marked as Bad. */\r
-#define NAND_BLOCK_BAD (-12U)\r
-\r
-/** \brief Error code to indicate failure in reading the spare area of the\r
- page. */\r
-#define NAND_SPARE_AREA_READ_FAIL (-13U)\r
-\r
-/*\r
-* \breif NAND device size (bus width) in bits\r
-* @{\r
-*/\r
-#define NAND_BUSWIDTH_8BITS (0U)\r
-#define NAND_BUSWIDTH_16BITS (1U)\r
-#define NAND_BUSWIDTH_32BITS (2U)\r
-\r
-/*\r
-* \breif NAND bad block flags\r
-*/\r
-#define NAND_BAD_BLOCK (1U)\r
-#define NAND_GOOD_BLOCK (0U)\r
-\r
-/** \brief Enumerates the different ECC algorithms used for Error Correction. */\r
-typedef enum NAND_EccAlgo\r
-{\r
- NAND_ECC_ALGO_NONE = 0U,\r
- /**< Value to denote no usage of ECC for Read/Write. */\r
- NAND_ECC_ALGO_HAMMING_1BIT,\r
- /**< Value to represent the Hamming Code ECC algorithm to correct up to\r
- one bit error in a block. */\r
- NAND_ECC_ALGO_BCH_4BIT,\r
- /**< Value to represent the BCH ECC algorithm to correct up to 4 bits of\r
- errors in a block.*/\r
- NAND_ECC_ALGO_BCH_8BIT,\r
- /**< Value to represent the BCH ECC algorithm to correct up to 8 bits of\r
- errors in a block.*/\r
- NAND_ECC_ALGO_BCH_16BIT\r
- /**< Value to represent the BCH ECC algorithm to correct up to 8 bits of\r
- errors in a block.*/\r
-\r
-}NAND_EccAlgo;\r
-\r
-/**\r
- * @brief This structure contains information about the NAND flash device\r
- *\r
- */\r
-typedef struct\r
-{\r
- /*! NAND HW interface handle */\r
- uint32_t hwHandle;\r
- /*! manufacturer ID*/\r
- uint32_t manufacturerId;\r
- /*! Manufacturers device ID */\r
- uint32_t deviceId;\r
- /*! bus width in bits */\r
- uint32_t busWidth;\r
- /*! Total blocks. First block starts at 0. */\r
- uint32_t blockCnt;\r
- /*! Page count per block*/\r
- uint32_t pageCnt;\r
- /*! Number of bytes in a page including spare area */\r
- uint32_t pageSize;\r
- /*! Spare area size in bytes*/\r
- uint32_t spareSize;\r
- /*! Offset into spare area to check for a bad block */\r
- uint32_t bbOffset;\r
- /*! Bad Block list or NULL if device does not support one */\r
- uint8_t *bbList;\r
- /*! ECC algorithm supported */\r
- uint32_t eccAlgo;\r
- /*! ECC Offset value in OOB */\r
- uint32_t eccOffset;\r
- /*! ECC byte count value in OOB */\r
- uint32_t eccByteCount;\r
-\r
-} NAND_Info;\r
-\r
-/*!\r
- * @brief A function pointer to a driver specific implementation of\r
- * NAND_open().\r
- */\r
-typedef NAND_HANDLE (*NAND_OpenFxn)(uint32_t nandIntf, uint32_t portNum, void *params);\r
-\r
-/*!\r
- * @brief A function pointer to a driver specific implementation of\r
- * NAND_CloseFxn().\r
- */\r
-typedef void (*NAND_CloseFxn)(NAND_HANDLE handle);\r
-\r
-/*!\r
- * @brief A function pointer to a driver specific implementation of\r
- * NAND_ReadFxn().\r
- */\r
-typedef NAND_STATUS (*NAND_ReadFxn)(NAND_HANDLE handle,\r
- uint32_t addr,\r
- uint32_t len,\r
- uint8_t *buf);\r
-\r
-/*!\r
- * @brief A function pointer to a driver specific implementation of\r
- * NAND_WriteFxn().\r
- */\r
-typedef NAND_STATUS (*NAND_WriteFxn)(NAND_HANDLE handle,\r
- uint32_t addr,\r
- uint32_t len,\r
- uint8_t *buf);\r
-\r
-/*!\r
- * @brief A function pointer to a driver specific implementation of\r
- * NAND_EraseFxn().\r
- */\r
-typedef NAND_STATUS (*NAND_EraseFxn)(NAND_HANDLE handle,\r
- int32_t blk);\r
-\r
-\r
-typedef struct NAND_FxnTable_s {\r
- /*! Function to initialize the given data object */\r
- NAND_OpenFxn openFxn;\r
- /*! Function to close the specified peripheral */\r
- NAND_CloseFxn closeFxn;\r
- /*! Function to read from the specified peripheral */\r
- NAND_ReadFxn readFxn;\r
- /*! Function to write from the specified peripheral */\r
- NAND_WriteFxn writeFxn;\r
- /*! Function to erase blocks from the specified peripheral */\r
- NAND_EraseFxn eraseFxn;\r
-\r
-} NAND_FxnTable;\r
-\r
-\r
-/*! @brief NAND Global configuration */\r
-typedef struct NAND_Config_s {\r
- /*! Pointer to a table of a driver-specific implementation of NAND functions */\r
- const NAND_FxnTable *fxnTablePtr;\r
-\r
-} NAND_Config;\r
-\r
-\r
-/*!\r
- * @brief Function to open the NAND peripheral\r
- *\r
- * @param nandIntf NAND peripheral interface ID\r
- * @param portNum port number of a peripheral interface connecting to the NAND device\r
- * @param params pointer to the configuration parameters of the peripheral\r
- *\r
- * @pre The NAND_config structure must exist and be persistent before this\r
- * function can be called. This function must also be called before\r
- * any other NAND driver APIs.\r
- *\r
- * @return A NAND_HANDLE on success or a NULL on an error or if it has been\r
- * already initialized\r
- */\r
-extern NAND_HANDLE NAND_open(uint32_t nandIntf, uint32_t portNum, void *params);\r
-\r
-/*!\r
- * @brief Function to close the NAND peripheral specified by the nand\r
- * handle.\r
- *\r
- * @pre NAND_open() had to be called first.\r
- *\r
- * @param handle A NAND_HANDLE returned from NAND_open\r
- *\r
- * @return NAND_STATUS.\r
- *\r
- * @sa NAND_open\r
- */\r
-extern void NAND_close(NAND_HANDLE handle);\r
-\r
-\r
-/*!\r
- * @brief Function that read data from NAND\r
- *\r
- * This function initiates an operation to read data from NAND.\r
- *\r
- *\r
- * @param handle A NAND_HANDLE\r
- * @param addr data address of the NAND flash device to read\r
- * @param len The number of bytes to read\r
- * @param buffer A pointer to an empty buffer in which read data should be\r
- * written to\r
- *\r
- * @return NAND_STATUS.\r
- */\r
-extern NAND_STATUS NAND_read(NAND_HANDLE handle, uint32_t addr, uint32_t len, uint8_t *buf);\r
-\r
-/*!\r
- * @brief Function that writes data to the NAND\r
- *\r
- * This function initiates an operation to write data to the NAND.\r
- *\r
- * @param handle A NAND_HANDLE\r
- * @param addr data address of the NAND flash device to write\r
- * @param len The number of bytes to write\r
- * @param buffer A pointer to buffer containing data to be written to NAND\r
- *\r
- * @return NAND_STATUS.\r
- */\r
-extern NAND_STATUS NAND_write(NAND_HANDLE handle, uint32_t addr, uint32_t len, uint8_t *buf);\r
-\r
-/*!\r
- * @brief Function that erase a NAND block or NAND chip\r
- *\r
- * This function initiates an operation to erase NAND block or chip.\r
- *\r
- * NAND_write will not return until all the data was written to the NAND.\r
- *\r
- * @param handle A NAND_HANDLE\r
- * @param blk NAND flash block number to erase\r
- *\r
- * @return NAND_STATUS.\r
- */\r
-extern NAND_STATUS NAND_erase(NAND_HANDLE handle, int32_t blk);\r
+/**
+ * @brief This type defines the handle returned to a NAND flash interface that is opened.
+ * The handle must be used in all subsequent operations.
+ *
+ */
+typedef uintptr_t NAND_HANDLE;
+
+/** NAND function return status */
+#define NAND_STATUS int32_t
+
+/** NAND return type macros */
+/** \brief On Success. */
+#define NAND_PASS (0U)
+
+/** \brief On Failure. */
+#define NAND_FAIL (-1U)
+
+/** \brief Error code for Timeout. */
+#define NAND_TIMEOUT (-2U)
+
+/** \brief Error code to indicate mode not supported. */
+#define NAND_MODE_NOT_SUPP (-3U)
+
+/** \brief Error code to indicate invalid parameter. */
+#define NAND_INVALID_PARAM (-4U)
+
+/** \brief Error code to indicate DMA operation failure. */
+#define NAND_DMA_FAIL (-5U)
+
+/** \brief Error code to indicate NAND device is Busy. */
+#define NAND_DEV_BUSY (-6U)
+
+/** \brief Error code to indicate NAND device is Write Protected. */
+#define NAND_DEV_PROTECTED (-7U)
+
+/** \brief Error code to indicate ECC error for the last access. */
+#define NAND_ECC_ERR (-8U)
+
+/** \brief Error code to indicate ECC error is corrected. */
+#define NAND_ECC_ERR_CORRECTED (-9U)
+
+/** \brief Error code to indicate Uncorrectable ecc errrors. */
+#define NAND_ECC_UNCORRECTABLE (-10U)
+
+/** \brief Error code to indicate Block is good to read/write. */
+#define NAND_BLOCK_GOOD (-11U)
+
+/** \brief Error code to indicate Block is marked as Bad. */
+#define NAND_BLOCK_BAD (-12U)
+
+/** \brief Error code to indicate failure in reading the spare area of the
+ page. */
+#define NAND_SPARE_AREA_READ_FAIL (-13U)
+
+/*
+* \breif NAND device size (bus width) in bits
+* @{
+*/
+#define NAND_BUSWIDTH_8BITS (0U)
+#define NAND_BUSWIDTH_16BITS (1U)
+#define NAND_BUSWIDTH_32BITS (2U)
+
+/*
+* \breif NAND bad block flags
+*/
+#define NAND_BAD_BLOCK (1U)
+#define NAND_GOOD_BLOCK (0U)
+
+/** \brief Enumerates the different ECC algorithms used for Error Correction. */
+typedef enum NAND_EccAlgo
+{
+ NAND_ECC_ALGO_NONE = 0U,
+ /**< Value to denote no usage of ECC for Read/Write. */
+ NAND_ECC_ALGO_HAMMING_1BIT,
+ /**< Value to represent the Hamming Code ECC algorithm to correct up to
+ one bit error in a block. */
+ NAND_ECC_ALGO_BCH_4BIT,
+ /**< Value to represent the BCH ECC algorithm to correct up to 4 bits of
+ errors in a block.*/
+ NAND_ECC_ALGO_BCH_8BIT,
+ /**< Value to represent the BCH ECC algorithm to correct up to 8 bits of
+ errors in a block.*/
+ NAND_ECC_ALGO_BCH_16BIT
+ /**< Value to represent the BCH ECC algorithm to correct up to 8 bits of
+ errors in a block.*/
+
+}NAND_EccAlgo;
+
+/**
+ * @brief This structure contains information about the NAND flash device
+ *
+ */
+typedef struct
+{
+ /*! NAND HW interface handle */
+ uintptr_t hwHandle;
+ /*! manufacturer ID*/
+ uint32_t manufacturerId;
+ /*! Manufacturers device ID */
+ uint32_t deviceId;
+ /*! bus width in bits */
+ uint32_t busWidth;
+ /*! Total blocks. First block starts at 0. */
+ uint32_t blockCnt;
+ /*! Page count per block*/
+ uint32_t pageCnt;
+ /*! Number of bytes in a page including spare area */
+ uint32_t pageSize;
+ /*! Spare area size in bytes*/
+ uint32_t spareSize;
+ /*! Offset into spare area to check for a bad block */
+ uint32_t bbOffset;
+ /*! Bad Block list or NULL if device does not support one */
+ uint8_t *bbList;
+ /*! ECC algorithm supported */
+ uint32_t eccAlgo;
+ /*! ECC Offset value in OOB */
+ uint32_t eccOffset;
+ /*! ECC byte count value in OOB */
+ uint32_t eccByteCount;
+
+} NAND_Info;
+
+/*!
+ * @brief A function pointer to a driver specific implementation of
+ * NAND_open().
+ */
+typedef NAND_HANDLE (*NAND_OpenFxn)(uint32_t nandIntf, uint32_t portNum, void *params);
+
+/*!
+ * @brief A function pointer to a driver specific implementation of
+ * NAND_CloseFxn().
+ */
+typedef void (*NAND_CloseFxn)(NAND_HANDLE handle);
+
+/*!
+ * @brief A function pointer to a driver specific implementation of
+ * NAND_ReadFxn().
+ */
+typedef NAND_STATUS (*NAND_ReadFxn)(NAND_HANDLE handle,
+ uint32_t addr,
+ uint32_t len,
+ uint8_t *buf);
+
+/*!
+ * @brief A function pointer to a driver specific implementation of
+ * NAND_WriteFxn().
+ */
+typedef NAND_STATUS (*NAND_WriteFxn)(NAND_HANDLE handle,
+ uint32_t addr,
+ uint32_t len,
+ uint8_t *buf);
+
+/*!
+ * @brief A function pointer to a driver specific implementation of
+ * NAND_EraseFxn().
+ */
+typedef NAND_STATUS (*NAND_EraseFxn)(NAND_HANDLE handle,
+ int32_t blk);
+
+
+typedef struct NAND_FxnTable_s {
+ /*! Function to initialize the given data object */
+ NAND_OpenFxn openFxn;
+ /*! Function to close the specified peripheral */
+ NAND_CloseFxn closeFxn;
+ /*! Function to read from the specified peripheral */
+ NAND_ReadFxn readFxn;
+ /*! Function to write from the specified peripheral */
+ NAND_WriteFxn writeFxn;
+ /*! Function to erase blocks from the specified peripheral */
+ NAND_EraseFxn eraseFxn;
+
+} NAND_FxnTable;
+
+
+/*! @brief NAND Global configuration */
+typedef struct NAND_Config_s {
+ /*! Pointer to a table of a driver-specific implementation of NAND functions */
+ const NAND_FxnTable *fxnTablePtr;
+
+} NAND_Config;
+
+
+/*!
+ * @brief Function to open the NAND peripheral
+ *
+ * @param nandIntf NAND peripheral interface ID
+ * @param portNum port number of a peripheral interface connecting to the NAND device
+ * @param params pointer to the configuration parameters of the peripheral
+ *
+ * @pre The NAND_config structure must exist and be persistent before this
+ * function can be called. This function must also be called before
+ * any other NAND driver APIs.
+ *
+ * @return A NAND_HANDLE on success or a NULL on an error or if it has been
+ * already initialized
+ */
+extern NAND_HANDLE NAND_open(uint32_t nandIntf, uint32_t portNum, void *params);
+
+/*!
+ * @brief Function to close the NAND peripheral specified by the nand
+ * handle.
+ *
+ * @pre NAND_open() had to be called first.
+ *
+ * @param handle A NAND_HANDLE returned from NAND_open
+ *
+ * @return NAND_STATUS.
+ *
+ * @sa NAND_open
+ */
+extern void NAND_close(NAND_HANDLE handle);
+
+
+/*!
+ * @brief Function that read data from NAND
+ *
+ * This function initiates an operation to read data from NAND.
+ *
+ *
+ * @param handle A NAND_HANDLE
+ * @param addr data address of the NAND flash device to read
+ * @param len The number of bytes to read
+ * @param buffer A pointer to an empty buffer in which read data should be
+ * written to
+ *
+ * @return NAND_STATUS.
+ */
+extern NAND_STATUS NAND_read(NAND_HANDLE handle, uint32_t addr, uint32_t len, uint8_t *buf);
+
+/*!
+ * @brief Function that writes data to the NAND
+ *
+ * This function initiates an operation to write data to the NAND.
+ *
+ * @param handle A NAND_HANDLE
+ * @param addr data address of the NAND flash device to write
+ * @param len The number of bytes to write
+ * @param buffer A pointer to buffer containing data to be written to NAND
+ *
+ * @return NAND_STATUS.
+ */
+extern NAND_STATUS NAND_write(NAND_HANDLE handle, uint32_t addr, uint32_t len, uint8_t *buf);
+
+/*!
+ * @brief Function that erase a NAND block or NAND chip
+ *
+ * This function initiates an operation to erase NAND block or chip.
+ *
+ * NAND_write will not return until all the data was written to the NAND.
+ *
+ * @param handle A NAND_HANDLE
+ * @param blk NAND flash block number to erase
+ *
+ * @return NAND_STATUS.
+ */
+extern NAND_STATUS NAND_erase(NAND_HANDLE handle, int32_t blk);
extern const NAND_FxnTable Nand_gpmcFxnTable;
+extern const NAND_FxnTable Nand_ospiFxnTable;
#ifdef __cplusplus
}
diff --git a/packages/ti/board/src/flash/nand/ospi/nand_ospi.c b/packages/ti/board/src/flash/nand/ospi/nand_ospi.c
--- /dev/null
@@ -0,0 +1,938 @@
+/*
+ * Copyright (c) 2021, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include <ti/board/src/flash/nand/ospi/nand_ospi.h>
+#include <ti/drv/spi/soc/SPI_soc.h>
+#include <ti/csl/soc.h>
+
+#if defined(j721s2_evm)
+/* SPI entry offset is at index 5 of SPI config array */
+#define SPI_CONFIG_OFFSET (5U)
+#endif
+
+static NAND_HANDLE Nand_ospiOpen(uint32_t nandIntf, uint32_t portNum, void *params);
+static void Nand_ospiClose(NAND_HANDLE handle);
+static NAND_STATUS Nand_ospiRead(NAND_HANDLE handle, uint32_t addr,
+ uint32_t len, uint8_t *buf);
+static NAND_STATUS Nand_ospiWrite(NAND_HANDLE handle, uint32_t addr,
+ uint32_t len, uint8_t *buf);
+static NAND_STATUS Nand_ospiErase(NAND_HANDLE handle, int32_t eraseCnt);
+
+static NAND_STATUS Nand_ospiCmdWrite(SPI_Handle handle, uint8_t *cmdBuf,
+ uint32_t cmdLen, uint32_t dataLen);
+
+static NAND_STATUS Nand_ospiWaitReady(SPI_Handle handle, uint32_t timeOut);
+
+/* NAND function table for NAND OSPI interface implementation */
+const NAND_FxnTable Nand_ospiFxnTable =
+{
+ &Nand_ospiOpen,
+ &Nand_ospiClose,
+ &Nand_ospiRead,
+ &Nand_ospiWrite,
+ &Nand_ospiErase,
+};
+
+NAND_Info Nand_ospiInfo =
+{
+ 0, /* hwHandle */
+ 0, /* manufacturerId */
+ 0, /* deviceId */
+ 0, /* busWidth */
+ NAND_NUM_BLOCKS, /* blockCnt */
+ NAND_NUM_PAGES_PER_BLOCK, /* pageCnt */
+ NAND_PAGE_SIZE, /* pageSize */
+ 0, /* baseAddr */
+ NAND_SECTOR_SIZE /* sectorSize */
+};
+
+static bool gPhyEnable;
+static bool gDtrEnable;
+
+static NAND_STATUS NAND_ospiCmdRead(SPI_Handle handle, uint8_t *cmdBuf,
+ uint32_t cmdLen, uint8_t *rxBuf, uint32_t rxLen)
+{
+ SPI_Transaction transaction;
+ uint32_t transferType = SPI_TRANSACTION_TYPE_READ;
+ bool ret;
+
+ /* Update the mode and transfer type with the required values */
+ SPI_control(handle, SPI_V0_CMD_SET_CFG_MODE, NULL);
+ SPI_control(handle, SPI_V0_CMD_XFER_MODE_RW, (void *)&transferType);
+ SPI_control(handle, SPI_V0_CMD_EXT_RD_CMD_LEN, (void *)&cmdLen);
+
+ transaction.txBuf = (void *)cmdBuf;
+ transaction.rxBuf = (void *)rxBuf;
+ transaction.count = cmdLen + rxLen;
+
+ ret = SPI_transfer(handle, &transaction);
+ if (ret == true)
+ {
+ return NAND_PASS;
+ }
+ else
+ {
+ return NAND_FAIL;
+ }
+}
+
+static NAND_STATUS Nand_ospiReadId(SPI_Handle handle)
+{
+ NAND_STATUS retVal;
+ uint8_t idCode[NAND_RDID_NUM_BYTES];
+ uint8_t cmd = NAND_CMD_RDID;
+ uint32_t manfID, devID;
+ uint32_t cmdDummyCycles;
+ OSPI_v0_HwAttrs const *hwAttrs= (OSPI_v0_HwAttrs const *)handle->hwAttrs;
+
+ if (hwAttrs->xferLines == OSPI_XFER_LINES_OCTAL)
+ {
+ cmdDummyCycles = 8;
+ SPI_control(handle, SPI_V0_CMD_EXT_RD_DUMMY_CLKS, (void *)&cmdDummyCycles);
+ }
+
+ retVal = NAND_ospiCmdRead(handle, &cmd, 1, idCode, NAND_RDID_NUM_BYTES);
+
+ if (hwAttrs->xferLines == OSPI_XFER_LINES_OCTAL)
+ {
+ cmdDummyCycles = 8;
+ SPI_control(handle, SPI_V0_CMD_EXT_RD_DUMMY_CLKS, (void *)&cmdDummyCycles);
+ }
+
+ if (retVal == NAND_PASS)
+ {
+ manfID = (uint32_t)idCode[0];
+ devID = ((uint32_t)idCode[1] << 8) | ((uint32_t)idCode[2]);
+ if ((manfID == NAND_MANF_ID) && (devID == NAND_DEVICE_ID))
+ {
+ Nand_ospiInfo.manufacturerId = manfID;
+ Nand_ospiInfo.deviceId = devID;
+ }
+ else
+ {
+ retVal = NAND_FAIL;
+ }
+ }
+
+ return (retVal);
+}
+
+static NAND_STATUS Nand_ospiEnableOctalDDR(SPI_Handle handle)
+{
+ NAND_STATUS retVal = NAND_PASS;
+ uint8_t cmdWren = NAND_CMD_WREN;
+ uint32_t data[3];
+
+ /* Send Write Enable command */
+ if(Nand_ospiCmdWrite(handle, &cmdWren, 1, 0))
+ {
+ retVal = NAND_FAIL;
+ }
+
+ /* Check BUSY bit of Flash */
+ if (Nand_ospiWaitReady(handle, NAND_WRR_WRITE_TIMEOUT))
+ {
+ retVal = NAND_FAIL;
+ }
+
+ /* Enable double transfer rate mode */
+ if (retVal == NAND_PASS)
+ {
+ /* send write VCR command to reg addr 0x0 to set to DDR mode */
+ data[0] = (NAND_CMD_WRITE_VCR << 24) | /* write volatile config reg cmd */
+ (0 << 23) | /* read data disable */
+ (7 << 20) | /* read 8 data bytes */
+ (1 << 19) | /* enable cmd adddr */
+ (2 << 16) | /* 3 address bytes */
+ (1 << 15); /* write data enable */
+ data[1] = 0; /* Non-volatile config register address */
+ data[2] = 0xE7U; /* set to Octal SPI DDR with DS in Nonvolatile Config Reg 0x0 */
+ SPI_control(handle, SPI_V0_CMD_ENABLE_DDR, (void *)data);
+ }
+
+ return retVal;
+}
+
+static NAND_STATUS Nand_ospiEnableOctalSDR(SPI_Handle handle)
+{
+ NAND_STATUS retVal = NAND_PASS;
+ uint8_t cmdWren = NAND_CMD_WREN;
+ uint32_t data[3];
+
+ /* Send Write Enable command */
+ if(Nand_ospiCmdWrite(handle, &cmdWren, 1, 0))
+ {
+ retVal = NAND_FAIL;
+ }
+
+ /* Check BUSY bit of Flash */
+ if (Nand_ospiWaitReady(handle, NAND_WRR_WRITE_TIMEOUT))
+ {
+ retVal = NAND_FAIL;
+ }
+
+ /* Enable single transfer rate mode */
+ if (retVal == NAND_PASS)
+ {
+ /* send write VCR command to reg addr 0x0 to set to SDR mode */
+ data[0] = (NAND_CMD_WRITE_VCR << 24) | /* write volatile config reg cmd */
+ (0 << 23) | /* read data disable */
+ (7 << 20) | /* read 8 data bytes */
+ (1 << 19) | /* enable cmd adddr */
+ (2 << 16) | /* 3 address bytes */
+ (1 << 15); /* write data enable */
+ data[1] = 0; /* Non-volatile config register address */
+ data[2] = 0xDFU; /* set to Octal SPI SDR without DS in Nonvolatile Config Reg 0x0 */
+ SPI_control(handle, SPI_V0_CMD_ENABLE_SDR, (void *)data);
+
+ }
+
+ return retVal;
+}
+
+static NAND_STATUS Nand_ospiEnableSingleSDR(SPI_Handle handle)
+{
+ NAND_STATUS retVal = NAND_PASS;
+ uint8_t cmdWren = NAND_CMD_WREN;
+ uint32_t data[3];
+
+ /* Send Write Enable command */
+ if(Nand_ospiCmdWrite(handle, &cmdWren, 1, 0))
+ {
+ retVal = NAND_FAIL;
+ }
+
+ /* Check BUSY bit of Flash */
+ if (Nand_ospiWaitReady(handle, NAND_WRR_WRITE_TIMEOUT))
+ {
+ retVal = NAND_FAIL;
+ }
+
+ /* Enable single transfer rate mode */
+ if (retVal == NAND_PASS)
+ {
+ /* send write VCR command to reg addr 0x0 to set to SDR mode */
+ data[0] = (NAND_CMD_WRITE_VCR << 24) | /* write volatile config reg cmd */
+ (0 << 23) | /* read data disable */
+ (7 << 20) | /* read 8 data bytes */
+ (1 << 19) | /* enable cmd adddr */
+ (2 << 16) | /* 3 address bytes */
+ (1 << 15); /* write data enable */
+ data[1] = 0; /* Non-volatile config register address */
+ data[2] = 0xFFU; /* set to Single SPI SDR with DS in Nonvolatile Config Reg 0x0 */
+ SPI_control(handle, SPI_V0_CMD_ENABLE_SDR, (void *)data);
+
+ }
+
+ return retVal;
+}
+
+static NAND_STATUS Nand_ospiResetMemory(SPI_Handle handle)
+{
+ NAND_STATUS retVal = NAND_PASS;
+ uint8_t cmd;
+
+ /* Send Reset Enable command */
+ cmd = NAND_CMD_RSTEN;
+ retVal = Nand_ospiCmdWrite(handle, &cmd, 1, 0);
+
+ if (retVal == NAND_PASS)
+ {
+ /* Send Reset Device Memory command */
+ cmd = NAND_CMD_RST_MEM;
+ retVal = Nand_ospiCmdWrite(handle, &cmd, 1, 0);
+ }
+
+ return (retVal);
+}
+
+static NAND_STATUS Nand_ospiSetDummyCycle(SPI_Handle handle, uint32_t dummyCycle)
+{
+ NAND_STATUS retVal = NAND_PASS;
+ uint8_t cmdWren = NAND_CMD_WREN;
+ uint32_t data[3];
+
+ /* Send Write Enable command */
+ if(Nand_ospiCmdWrite(handle, &cmdWren, 1, 0))
+ {
+ retVal = NAND_FAIL;
+ }
+
+ /* Check BUSY bit of Flash */
+ if (Nand_ospiWaitReady(handle, NAND_WRR_WRITE_TIMEOUT))
+ {
+ retVal = NAND_FAIL;
+ }
+
+ /* send the dummy cycle value to reg addr 0x1 */
+ if (retVal == NAND_PASS)
+ {
+ data[0] = (NAND_CMD_WRITE_VCR << 24) | /* write volatile config reg cmd */
+ (0 << 23) | /* read data disable */
+ (7 << 20) | /* read 8 data bytes */
+ (1 << 19) | /* enable cmd adddr */
+ (2 << 16) | /* 3 address bytes */
+ (1 << 15); /* write data enable */
+ data[1] = 0x00000001; /* Dummy cycle config register address */
+ data[2] = dummyCycle; /* Dummy cycle # */
+ SPI_control(handle, SPI_V0_CMD_CFG_DUMMY_CYCLE, (void *)data);
+ }
+
+ return retVal;
+}
+
+static NAND_STATUS Nand_ospiDisableWriteProtection(SPI_Handle handle)
+{
+ NAND_STATUS retVal = NAND_PASS;
+ uint32_t data[3];
+ uint32_t retry = 10;
+ volatile uint32_t delay = 1000;
+ uint32_t idleFlag = FALSE;
+ OSPI_v0_HwAttrs const *hwAttrs = (OSPI_v0_HwAttrs const *)handle->hwAttrs;
+ const CSL_ospi_flash_cfgRegs *pRegs = (const CSL_ospi_flash_cfgRegs *)hwAttrs->baseAddr;
+
+ data[0] = (NAND_CMD_WRITE_STATUS << 24) | /* write volatile config reg cmd */
+ (0 << 23) | /* read data disable */
+ (0 << 20) | /* read 0 data bytes */
+ (1 << 19) | /* enable cmd adddr */
+ (0 << 16) | /* 1 address bytes */
+ (1 << 15) | /* write data enable */
+ (0 << 12); /* write 1 data bytes */
+ data[1] = 0x000000A0; /* status register 1 address */
+ data[2] = 0x00000000; /* Value to disable all protection */
+
+ CSL_ospiFlashStig((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr), data[0], data[1], data[2]);
+
+ while (idleFlag == FALSE)
+ {
+ idleFlag = CSL_ospiIsIdle(pRegs);
+ }
+
+ /* Start to execute flash read/write command */
+ CSL_ospiFlashExecCmd(pRegs);
+
+ while (retry != 0U)
+ {
+ /* Check the command execution status */
+ if (CSL_ospiFlashExecCmdComplete(pRegs) == TRUE)
+ {
+ break;
+ }
+ while(delay--);
+ delay = 1000;
+ retry--;
+ }
+
+ if (retry == 0U)
+ {
+ retVal = (int32_t)(-1);
+ }
+
+ idleFlag = FALSE;
+ while (idleFlag == FALSE)
+ {
+ idleFlag = CSL_ospiIsIdle(pRegs);
+ }
+
+ return retVal;
+}
+
+static void Nand_ospiSetOpcode(SPI_Handle handle)
+{
+ uint32_t data[6];
+ uint32_t rdDummyCycles = 0;
+ uint32_t cmdDummyCycles = 0;
+ uint32_t readCmd;
+ uint32_t progCmd;
+ uint32_t rx_lines;
+ OSPI_v0_HwAttrs const *hwAttrs= (OSPI_v0_HwAttrs const *)handle->hwAttrs;
+
+ rx_lines = hwAttrs->xferLines;
+ if (rx_lines == OSPI_XFER_LINES_OCTAL)
+ {
+ if (hwAttrs->dacEnable)
+ {
+ rdDummyCycles = NAND_OCTAL_READ_DUMMY_CYCLE;
+ }
+ else
+ {
+ rdDummyCycles = NAND_OCTAL_READ_DUMMY_CYCLE_INDAC;
+ }
+
+ if (gDtrEnable == true)
+ {
+ cmdDummyCycles = NAND_OCTAL_DDR_CMD_READ_DUMMY_CYCLE;
+ readCmd = NAND_CMD_FAST_READ_DDR;
+ progCmd = NAND_CMD_PAGE_PROG;
+ }
+ else
+ {
+ cmdDummyCycles = NAND_OCTAL_SDR_CMD_READ_DUMMY_CYCLE;
+ readCmd = NAND_CMD_OCTAL_IO_FAST_RD;
+ progCmd = NAND_CMD_EXT_OCTAL_FAST_PROG;
+ }
+ }
+ else
+ {
+ /* Set to legacy SPI mode 1-1-1 if not Octal mode */
+ rdDummyCycles = NAND_SINGLE_READ_DUMMY_CYCLE;
+ cmdDummyCycles = NAND_SINGLE_CMD_READ_DUMMY_CYCLE;
+ readCmd = NAND_CMD_READ;
+ progCmd = NAND_CMD_PAGE_PROG;
+ }
+
+ data[0] = readCmd;
+ data[1] = progCmd;
+ data[2] = NAND_CMD_RDSR;
+ data[3] = NAND_SR3_ADDR;
+
+ /* Update the read opCode, rx lines and read dummy cycles */
+ SPI_control(handle, SPI_V0_CMD_RD_DUMMY_CLKS, (void *)&rdDummyCycles);
+ SPI_control(handle, SPI_V0_CMD_SET_XFER_LINES, (void *)&rx_lines);
+ SPI_control(handle, SPI_V0_CMD_XFER_OPCODE, (void *)data);
+ SPI_control(handle, SPI_V0_CMD_EXT_RD_DUMMY_CLKS, (void *)&cmdDummyCycles);
+
+ /* Set device size cofigurations */
+ CSL_ospiSetDevSize((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr),
+ 1,
+ 256,
+ 16);
+
+ if (rx_lines == OSPI_XFER_LINES_OCTAL)
+ {
+ /* Set the opcodes for dual opcode mode */
+ data[0] = 0x00;
+ data[1] = 0xFA;
+ data[2] = readCmd;
+ data[3] = progCmd;
+ data[4] = 0xF9;
+ data[5] = 0x06;
+ SPI_control(handle, SPI_V0_CMD_XFER_OPCODE_EXT, (void *)data);
+ }
+ else
+ {
+ CSL_ospiSetDualByteOpcodeMode((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr), FALSE);
+ }
+
+ return;
+}
+
+NAND_HANDLE Nand_ospiOpen(uint32_t nandIntf, uint32_t portNum, void *params)
+{
+ SPI_Params spiParams; /* SPI params structure */
+ SPI_Handle hwHandle; /* SPI handle */
+ NAND_HANDLE nandHandle = 0;
+ OSPI_v0_HwAttrs ospiCfg;
+ NAND_STATUS retVal;
+ uint32_t data;
+
+ /* Get the OSPI SoC configurations */
+ OSPI_socGetInitCfg(portNum, &ospiCfg);
+
+ /* Save the DTR enable flag */
+ gDtrEnable = ospiCfg.dtrEnable;
+
+ /* Reset the PHY tunning configuration data when enabled */
+ data = *(uint32_t *)params;
+ if (data != 0)
+ {
+ /* TO DO - Implement PHY tuning */
+ /*
+ Nand_spiPhyTuneReset(gDtrEnable);
+ */
+ }
+
+ /* Save the PHY enable flag */
+ gPhyEnable = ospiCfg.phyEnable;
+ if (gPhyEnable == (bool)true)
+ {
+ /*
+ * phyEnable is turned on only for DAC read,
+ * it turned off for open/erase/write operation
+ */
+ ospiCfg.phyEnable = false;
+ OSPI_socSetInitCfg(portNum, &ospiCfg);
+ }
+
+ /* Use default SPI config params if no params provided */
+ SPI_Params_init(&spiParams);
+ hwHandle = (SPI_Handle)SPI_open(portNum + SPI_CONFIG_OFFSET, &spiParams);
+ if (hwHandle)
+ {
+ retVal = NAND_PASS;
+ if (retVal == NAND_PASS)
+ {
+ OSPI_v0_HwAttrs *hwAttrs = (OSPI_v0_HwAttrs *)hwHandle->hwAttrs;
+ CSL_ospiSetDualByteOpcodeMode((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr), FALSE);
+ if (ospiCfg.xferLines == OSPI_XFER_LINES_OCTAL)
+ {
+ /* Disable write protection */
+ Nand_ospiDisableWriteProtection(hwHandle);
+ /* Set read dummy cycles to the flash device */
+ Nand_ospiSetDummyCycle(hwHandle, 0x08);
+ /* Enable DDR or SDR mode for Octal lines */
+ if (gDtrEnable == (bool)true)
+ {
+ Nand_ospiEnableOctalDDR(hwHandle);
+ }
+ else
+ {
+ Nand_ospiEnableOctalSDR(hwHandle);
+ }
+ }
+ else
+ {
+ /* Reset device memory for all the other lines */
+ Nand_ospiResetMemory(hwHandle);
+ /* Disable write protection */
+ Nand_ospiDisableWriteProtection(hwHandle);
+ /* Set read dummy cycles to the flash device */
+ Nand_ospiSetDummyCycle(hwHandle, 0x08);
+ /* Enable Single SDR mode */
+ Nand_ospiEnableSingleSDR(hwHandle);
+ }
+
+ /* Set read/write opcode and read dummy cycles */
+ Nand_ospiSetOpcode(hwHandle);
+
+ /* Read the flash ID to ensure correct config */
+ if (Nand_ospiReadId(hwHandle) == NAND_PASS)
+ {
+ Nand_ospiInfo.hwHandle = (uintptr_t)hwHandle;
+ nandHandle = (NAND_HANDLE)(&Nand_ospiInfo);
+ }
+ }
+
+ if (nandHandle == 0)
+ {
+ SPI_close(hwHandle);
+ }
+ }
+
+ return (nandHandle);
+}
+
+void Nand_ospiClose(NAND_HANDLE handle)
+{
+ NAND_Info *nandOspiInfo;
+ SPI_Handle spiHandle;
+
+ if (handle)
+ {
+ nandOspiInfo = (NAND_Info *)handle;
+ spiHandle = (SPI_Handle)nandOspiInfo->hwHandle;
+
+ if (spiHandle)
+ {
+ SPI_close(spiHandle);
+ }
+ }
+}
+
+static NAND_STATUS Nand_ospiCmdWrite(SPI_Handle handle, uint8_t *cmdBuf,
+ uint32_t cmdLen, uint32_t dataLen)
+{
+ SPI_Transaction transaction;
+ uint32_t transferType = SPI_TRANSACTION_TYPE_WRITE;
+ bool ret;
+
+ /* Update the mode and transfer type with the required values */
+ SPI_control(handle, SPI_V0_CMD_SET_CFG_MODE, NULL);
+ SPI_control(handle, SPI_V0_CMD_XFER_MODE_RW, (void *)&transferType);
+
+ transaction.txBuf = (void *)cmdBuf; /* Buffer includes command and write data */
+ transaction.count = cmdLen + dataLen;
+ transaction.rxBuf = NULL;
+ transaction.arg = (void *)(uintptr_t)dataLen;
+
+ ret = SPI_transfer(handle, &transaction);
+ if (ret == true)
+ {
+ return NAND_PASS;
+ }
+ else
+ {
+ return NAND_FAIL;
+ }
+}
+
+static NAND_STATUS Nand_ospiWaitReady(SPI_Handle handle, uint32_t timeOut)
+{
+ uint8_t status;
+ uint8_t cmd[3];
+ uint32_t cmdDummyCycles = 0;
+ OSPI_v0_HwAttrs const *hwAttrs= (OSPI_v0_HwAttrs const *)handle->hwAttrs;
+
+ if(CSL_ospiGetDualByteOpcodeMode((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr)))
+ {
+ cmd[0] = NAND_CMD_RDSR;
+ cmd[1] = NAND_SR3_ADDR; /* Address Bytes */
+ cmd[2] = 0x00;
+
+ cmdDummyCycles = 7;
+ SPI_control(handle, SPI_V0_CMD_EXT_RD_DUMMY_CLKS, (void *)&cmdDummyCycles);
+
+ do
+ {
+ if (NAND_ospiCmdRead(handle, cmd, 3, &status, 1))
+ {
+ return NAND_FAIL;
+ }
+ if ((status & NAND_SR_WIP) == 0)
+ {
+ break;
+ }
+
+ timeOut--;
+ if (!timeOut) {
+ status = 0;
+ break;
+ }
+
+ } while (1);
+ cmdDummyCycles = 8;
+ SPI_control(handle, SPI_V0_CMD_EXT_RD_DUMMY_CLKS, (void *)&cmdDummyCycles);
+ }
+ else
+ {
+ cmd[0] = NAND_CMD_RDSR;
+ cmd[1] = NAND_SR3_ADDR; /* Address Bytes */
+
+ cmdDummyCycles = 0;
+ SPI_control(handle, SPI_V0_CMD_EXT_RD_DUMMY_CLKS, (void *)&cmdDummyCycles);
+
+ do
+ {
+ if (NAND_ospiCmdRead(handle, cmd, 2, &status, 1))
+ {
+ return NAND_FAIL;
+ }
+ if ((status & NAND_SR_WIP) == 0)
+ {
+ break;
+ }
+
+ timeOut--;
+ if (!timeOut) {
+ break;
+ }
+
+ } while (1);
+ cmdDummyCycles = 8;
+ SPI_control(handle, SPI_V0_CMD_EXT_RD_DUMMY_CLKS, (void *)&cmdDummyCycles);
+ }
+
+ if ((status & NAND_SR_WIP) == 0)
+ {
+ return NAND_PASS;
+ }
+
+ /* Timed out */
+ return NAND_FAIL;
+}
+
+static SPI_Transaction transaction;
+NAND_STATUS Nand_ospiRead(NAND_HANDLE handle, uint32_t addr, uint32_t len, uint8_t *buf)
+{
+ NAND_Info *nandOspiInfo;
+ SPI_Handle spiHandle;
+ uint32_t rdAddr;
+ uint32_t pageAddr;
+ uint32_t colmAddr;
+ bool ret = TRUE;
+ uint32_t transferType = SPI_TRANSACTION_TYPE_READ;
+ OSPI_v0_HwAttrs *hwAttrs;
+ uint8_t pageReadCmd[4];
+ uint32_t pageReadCmdLen = 4;
+
+ if (!handle)
+ {
+ return NAND_FAIL;
+ }
+
+ nandOspiInfo = (NAND_Info *)handle;
+ if (!nandOspiInfo->hwHandle)
+ {
+ return NAND_FAIL;
+ }
+ spiHandle = (SPI_Handle)nandOspiInfo->hwHandle;
+ hwAttrs = (OSPI_v0_HwAttrs *)spiHandle->hwAttrs;
+
+ if (gPhyEnable == (bool)true)
+ {
+ /* TO DO - Implement PHY tuning */
+ /*
+ if (Nand_spiPhyTune(spiHandle, NAND_TUNING_DATA_OFFSET) == NAND_FAIL)
+ return NAND_FAIL;
+ */
+ }
+ /* Validate address input */
+ if ((addr + len) > NAND_SIZE)
+ {
+ return NAND_FAIL;
+ }
+
+ for(rdAddr = addr; rdAddr < (addr+len); rdAddr += NAND_PAGE_SIZE)
+ {
+ /* Split the page and column addresses */
+ pageAddr = rdAddr / NAND_PAGE_SIZE;
+ colmAddr = rdAddr % NAND_PAGE_SIZE;
+
+ if (hwAttrs->xferLines == OSPI_XFER_LINES_OCTAL)
+ {
+ /* Send the page read command */
+ pageReadCmd[0] = NAND_CMD_PAGE_READ;
+ pageReadCmd[1] = (pageAddr >> 8) & 0xff; /* page address 2 bytes */
+ pageReadCmd[2] = (pageAddr >> 0) & 0xff;
+ pageReadCmdLen = 3;
+ Nand_ospiCmdWrite(spiHandle, pageReadCmd, pageReadCmdLen, 0);
+ }
+ else
+ {
+ /* Send the page read command */
+ pageReadCmd[0] = NAND_CMD_PAGE_READ;
+ pageReadCmd[1] = 0x00; /* Dummy Byte */
+ pageReadCmd[2] = (pageAddr >> 8) & 0xff; /* page address 2 bytes */
+ pageReadCmd[3] = (pageAddr >> 0) & 0xff;
+ pageReadCmdLen = 4;
+ Nand_ospiCmdWrite(spiHandle, pageReadCmd, pageReadCmdLen, 0);
+ }
+
+ /* Check BUSY bit of Flash */
+ if (Nand_ospiWaitReady(spiHandle, NAND_WRR_WRITE_TIMEOUT))
+ {
+ return NAND_FAIL;
+ }
+
+ /* Set transfer mode and read type */
+ SPI_control(spiHandle, SPI_V0_CMD_SET_XFER_MODE, NULL);
+ SPI_control(spiHandle, SPI_V0_CMD_XFER_MODE_RW, (void *)&transferType);
+
+ transaction.arg = (void *)(uintptr_t)colmAddr;
+ transaction.txBuf = NULL;
+ transaction.rxBuf = (void *)(buf+rdAddr-addr);
+ transaction.count = NAND_PAGE_SIZE;
+
+ ret = SPI_transfer(spiHandle, &transaction);
+ if (ret == false)
+ {
+ return NAND_FAIL;
+ }
+ }
+ return NAND_PASS;
+}
+
+NAND_STATUS Nand_ospiWrite(NAND_HANDLE handle, uint32_t addr, uint32_t len, uint8_t *buf)
+{
+ NAND_Info *nandOspiInfo;
+ SPI_Handle spiHandle;
+ bool ret;
+ uint32_t byteAddr;
+ uint32_t pageAddr;
+ uint32_t colmAddr;
+ uint32_t wrSize = len;
+ uint32_t chunkLen;
+ uint32_t actual;
+ uint32_t transferType = SPI_TRANSACTION_TYPE_WRITE;
+ OSPI_v0_HwAttrs *hwAttrs;
+ uint8_t progExecuteCmd[4];
+ uint32_t progExecuteCmdLen = 4;
+ uint8_t cmdWren = NAND_CMD_WREN;
+
+ if (!handle)
+ {
+ return NAND_FAIL;
+ }
+
+ nandOspiInfo = (NAND_Info *)handle;
+ if (!nandOspiInfo->hwHandle)
+ {
+ return NAND_FAIL;
+ }
+
+ /* Validate address input */
+ if ((addr + len) > NAND_SIZE)
+ {
+ return NAND_FAIL;
+ }
+
+ spiHandle = (SPI_Handle)nandOspiInfo->hwHandle;
+ hwAttrs = (OSPI_v0_HwAttrs *)spiHandle->hwAttrs;
+
+ wrSize = NAND_PAGE_SIZE;
+ byteAddr = addr & (wrSize - 1);
+
+ for (actual = 0; actual < len; actual += chunkLen)
+ {
+ /* Send Write Enable command */
+ if(Nand_ospiCmdWrite(spiHandle, &cmdWren, 1, 0))
+ {
+ return NAND_FAIL;
+ }
+
+ /* Check BUSY bit of Flash */
+ if (Nand_ospiWaitReady(spiHandle, NAND_WRR_WRITE_TIMEOUT))
+ {
+ return NAND_FAIL;
+ }
+
+ /* Set the transfer mode, write op code and tx lines */
+ SPI_control(spiHandle, SPI_V0_CMD_SET_XFER_MODE, NULL);
+ SPI_control(spiHandle, SPI_V0_CMD_XFER_MODE_RW, (void *)&transferType);
+
+ /* Send Page Program command */
+ chunkLen = ((len - actual) < (wrSize - byteAddr) ?
+ (len - actual) : (wrSize - byteAddr));
+
+ /* Split the page and column addresses */
+ pageAddr = addr / NAND_PAGE_SIZE;
+ colmAddr = addr % NAND_PAGE_SIZE;
+
+ transaction.arg = (void *)(uintptr_t)colmAddr;
+ transaction.txBuf = (void *)(buf + actual);
+ transaction.rxBuf = NULL;
+ transaction.count = chunkLen;
+
+ ret = SPI_transfer(spiHandle, &transaction);
+ if (ret == false)
+ {
+ return NAND_FAIL;
+ }
+
+ /* Check BUSY bit of Flash */
+ if (Nand_ospiWaitReady(spiHandle, NAND_WRR_WRITE_TIMEOUT))
+ {
+ return NAND_FAIL;
+ }
+
+ if (hwAttrs->xferLines == OSPI_XFER_LINES_OCTAL)
+ {
+ progExecuteCmd[0] = NAND_CMD_PAGE_PROG_EXECUTE;
+ progExecuteCmd[1] = (pageAddr >> 8) & 0xff; /* page address 2 bytes */
+ progExecuteCmd[2] = (pageAddr >> 0) & 0xff;
+ progExecuteCmdLen = 3;
+ Nand_ospiCmdWrite(spiHandle, progExecuteCmd, progExecuteCmdLen, 0);
+ }
+ else
+ {
+ progExecuteCmd[0] = NAND_CMD_PAGE_PROG_EXECUTE;
+ progExecuteCmd[1] = 0x00; /* Dummy Byte */
+ progExecuteCmd[2] = (pageAddr >> 8) & 0xff; /* page address 2 bytes */
+ progExecuteCmd[3] = (pageAddr >> 0) & 0xff;
+ progExecuteCmdLen = 4;
+ Nand_ospiCmdWrite(spiHandle, progExecuteCmd, progExecuteCmdLen, 0);
+ }
+ addr += chunkLen;
+ byteAddr = 0;
+
+ /* Wait till the write operation completes */
+ if (Nand_ospiWaitReady(spiHandle, NAND_WRR_WRITE_TIMEOUT))
+ {
+ return NAND_FAIL;
+ }
+ }
+
+ return NAND_PASS;
+}
+
+NAND_STATUS Nand_ospiErase(NAND_HANDLE handle, int32_t erLoc)
+{
+ uint8_t cmd[4];
+ uint32_t cmdLen;
+ uint32_t address = 0;
+ uint32_t pageAddr = 0;
+ uint8_t cmdWren = NAND_CMD_WREN;
+ NAND_Info *nandOspiInfo;
+ SPI_Handle spiHandle;
+ OSPI_v0_HwAttrs *hwAttrs;
+
+ if (!handle)
+ {
+ return NAND_FAIL;
+ }
+
+ nandOspiInfo = (NAND_Info *)handle;
+ if (!nandOspiInfo->hwHandle)
+ {
+ return NAND_FAIL;
+ }
+ spiHandle = (SPI_Handle)nandOspiInfo->hwHandle;
+ hwAttrs = (OSPI_v0_HwAttrs *)spiHandle->hwAttrs;
+
+ if (erLoc >= NAND_NUM_BLOCKS)
+ {
+ return NAND_FAIL;
+ }
+ address = erLoc * NAND_BLOCK_SIZE;
+
+ /* Get the page addresses */
+ pageAddr = address / NAND_PAGE_SIZE;
+
+ if (hwAttrs->xferLines == OSPI_XFER_LINES_OCTAL)
+ {
+ cmd[0] = NAND_CMD_BLOCK_ERASE;
+ cmd[1] = (pageAddr >> 8) & 0xff; /* page address 2 bytes */
+ cmd[2] = (pageAddr >> 0) & 0xff;
+ cmdLen = 3;
+ }
+ else
+ {
+ cmd[0] = NAND_CMD_BLOCK_ERASE;
+ cmd[1] = 0x00; /* Dummy Byte */
+ cmd[2] = (pageAddr >> 8) & 0xff; /* page address 2 bytes */
+ cmd[3] = (pageAddr >> 0) & 0xff;
+ cmdLen = 4;
+ }
+
+ if (Nand_ospiCmdWrite(spiHandle, &cmdWren, 1, 0))
+ {
+ return NAND_FAIL;
+ }
+
+ if (Nand_ospiWaitReady(spiHandle, NAND_WRR_WRITE_TIMEOUT))
+ {
+ return NAND_FAIL;
+ }
+
+ if (Nand_ospiCmdWrite(spiHandle, cmd, cmdLen, 0))
+ {
+ return NAND_FAIL;
+ }
+
+ if (Nand_ospiWaitReady(spiHandle, NAND_BULK_ERASE_TIMEOUT))
+ {
+ return NAND_FAIL;
+ }
+
+ return NAND_PASS;
+}
diff --git a/packages/ti/board/src/flash/nand/ospi/nand_ospi.h b/packages/ti/board/src/flash/nand/ospi/nand_ospi.h
--- /dev/null
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2021, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ *
+ * \file nand_ospi.h
+ *
+ * \brief This file contains structure, typedefs, functions and
+ * prototypes used for OSPI interface for NOR flash.
+ *
+ *****************************************************************************/
+#ifndef NAND_OSPI_H_
+#define NAND_OSPI_H_
+
+#include <string.h>
+
+#include <ti/board/src/flash/nand/nand.h>
+#include <ti/drv/spi/SPI.h>
+#include <ti/drv/spi/soc/SPI_soc.h>
+#include <ti/board/src/flash/nand/device/w35n01jwtbag.h>
+
+#endif /* NAND_OSPI_H_ */
+
+/* Nothing past this point */
index d6549dbc9248cf1e2525d439b24bbc19a28eaf77..ea535477f2643a80ab6a2f1a999248128bf3b220 100644 (file)
&Nor_hpfFxnTable
}
};
+#elif defined(j721s2_evm)
+NOR_Config Nor_config[BOARD_FLASH_NOR_INTF_MAX] =
+{
+ {
+ NULL
+ },
+ {
+ &Nor_qspiFxnTable
+ },
+ {
+ NULL
+ },
+ {
+ &Nor_xspiFxnTable
+ },
+ {
+ NULL
+ }
+};
#elif defined(am64x_evm)
NOR_Config Nor_config[BOARD_FLASH_NOR_INTF_MAX] =
{
diff --git a/packages/ti/board/src/flash/nor/ospi/nor_ospi.c b/packages/ti/board/src/flash/nor/ospi/nor_ospi.c
index 61e2d947f07ea55af85307736408ec6b8e6d5b06..641049777f9c3b7c34174537fbebfd85dae59995 100755 (executable)
/*\r
- * Copyright (c) 2018 - 2020, Texas Instruments Incorporated\r
+ * Copyright (c) 2018 - 2022, Texas Instruments Incorporated\r
* All rights reserved.\r
*\r
* Redistribution and use in source and binary forms, with or without\r
#include <ti/drv/spi/soc/SPI_soc.h>\r
#include <ti/csl/soc.h>\r
\r
-#if (defined (am65xx_evm) || defined (am65xx_idk) || defined (j7200_evm) || defined (j721e_evm))\r
+#if (defined (am65xx_evm) || defined (am65xx_idk) || defined (j7200_evm) || defined (j721e_evm) || defined(j721s2_evm))\r
/* SPI entry offset is at index 5 of SPI config array */\r
#define SPI_CONFIG_OFFSET (5U)\r
#elif defined (am64x_evm) || defined (am64x_svb)\r
diff --git a/packages/ti/board/src/flash/nor/ospi/nor_qspi.c b/packages/ti/board/src/flash/nor/ospi/nor_qspi.c
index bdb1c9af8098e6e11609c629de9c80cec16dcd56..368a643af3ffcf2bfc38a5540f3bf322cc5c84a2 100755 (executable)
/*\r
- * Copyright (c) 2018 - 2020, Texas Instruments Incorporated\r
+ * Copyright (c) 2018 - 2022, Texas Instruments Incorporated\r
* All rights reserved.\r
*\r
* Redistribution and use in source and binary forms, with or without\r
#include <ti/drv/spi/soc/SPI_soc.h>\r
#include <ti/csl/soc.h>\r
\r
-#if (defined (j7200_evm) || defined (j721e_evm))\r
+#if (defined (j7200_evm) || defined (j721e_evm) || defined(j721s2_evm))\r
/* SPI entry offset is at index 5 of SPI config array */\r
#define SPI_CONFIG_OFFSET (5U)\r
#elif defined (am64x_evm) || defined (am64x_svb)\r
\r
hwAttrs = (OSPI_v0_HwAttrs const *)handle->hwAttrs;\r
\r
-#if defined (j721e_evm) || defined (j7200_evm) || defined (am64x_svb) || defined (am640x_svb)\r
+#if defined (j721e_evm) || defined (j7200_evm) || defined (am64x_svb) || defined (am640x_svb) || defined (j721s2_evm)\r
/* Send Write Enable command */\r
if (Nor_qspiCmdWrite(handle, &cmdWren, 1, 0))\r
{\r
\r
hwAttrs = (OSPI_v0_HwAttrs const *)handle->hwAttrs;\r
\r
-#if defined (j721e_evm) || defined (j7200_evm) || defined (am64x_svb) || defined (am640x_svb)\r
+#if defined (j721e_evm) || defined (j7200_evm) || defined (am64x_svb) || defined (am640x_svb) || defined (j721s2_evm)\r
/* Send Write Enable command */\r
if (Nor_qspiCmdWrite(handle, &cmdWren, 1, 0))\r
{\r
diff --git a/packages/ti/board/src/flash/nor/ospi/nor_spi_phy_tune.c b/packages/ti/board/src/flash/nor/ospi/nor_spi_phy_tune.c
index 4c6a63fddde5e7e803273bf7c5fb0fd38eb23640..400477ff21ecfa2dce4749f170aa3e68a14d91ab 100755 (executable)
#include <ti/drv/spi/SPI.h>\r
#include <ti/drv/spi/soc/SPI_soc.h>\r
#include <ti/board/src/flash/nor/nor.h>\r
-#if defined (j7200_evm) || defined (am64x_evm)\r
+#if defined (j7200_evm) || defined (am64x_evm) || defined(j721s2_evm)\r
#include <ti/board/src/flash/nor/ospi/nor_xspi.h>\r
#else\r
#include <ti/board/src/flash/nor/ospi/nor_ospi.h>\r
uint32_t statReg; /* VTM temperature sensor status register addr */\r
uint32_t ctrlReg; /* VTM temperature sensor control register addr */\r
\r
-#if defined (SOC_J721E) || defined (SOC_J7200)\r
+#if defined (SOC_J721E) || defined (SOC_J7200) || defined(SOC_J721S2)\r
statReg = CSL_WKUP_VTM0_MMR_VBUSP_CFG1_BASE + 0x308U;\r
ctrlReg = CSL_WKUP_VTM0_MMR_VBUSP_CFG2_BASE + 0x300U;\r
#elif defined (SOC_AM65XX)\r
diff --git a/packages/ti/board/src/flash/nor/ospi/nor_xspi.c b/packages/ti/board/src/flash/nor/ospi/nor_xspi.c
index 16c83ddf8d7def01010d4e6a1d32a4f2e2e39dbb..94e3e99e83cfc44bd503d0cd2bdc61e22dbb38e2 100755 (executable)
/*\r
- * Copyright (c) 2020, Texas Instruments Incorporated\r
+ * Copyright (c) 2020-2022, Texas Instruments Incorporated\r
* All rights reserved.\r
*\r
* Redistribution and use in source and binary forms, with or without\r
#include <ti/drv/spi/soc/SPI_soc.h>\r
#include <ti/csl/soc.h>\r
\r
-#if (defined (j7200_evm) || defined (j721e_evm))\r
+#if (defined (j7200_evm) || defined (j721e_evm) || defined(j721s2_evm))\r
/* SPI entry offset is at index 5 of SPI config array */\r
#define SPI_CONFIG_OFFSET (5U)\r
#elif defined (am64x_evm) || defined (am64x_svb)\r
diff --git a/packages/ti/board/src/flash/nor/ospi/nor_xspi.h b/packages/ti/board/src/flash/nor/ospi/nor_xspi.h
index 7e8da8fbc17e9ef7e28ed8f0a0d3af3af60af634..804e346ed0598e8f90c21adaca73b4b4d9ff9cf0 100755 (executable)
#include <ti/board/src/flash/nor/nor.h>\r
#include <ti/drv/spi/SPI.h>\r
#include <ti/drv/spi/soc/SPI_soc.h>\r
-#if defined(j7200_evm) || defined(am64x_evm) || defined(am64x_svb)\r
+#if defined(j7200_evm) || defined(am64x_evm) || defined(am64x_svb) || defined(j721s2_evm)\r
#include <ti/board/src/flash/nor/device/s28hs512t.h>\r
#endif\r
#include <ti/board/src/flash/nor/ospi/nor_spi_phy_tune.h>\r
diff --git a/packages/ti/board/src/flash/src_files_flash.mk b/packages/ti/board/src/flash/src_files_flash.mk
index 191cca1f2f9c5b5d905eaa7523651a6b6022e90c..f80ec3e113276345c674680409c3ee014f169c41 100644 (file)
#
-# Copyright (c) 2016 - 2020, Texas Instruments Incorporated
+# Copyright (c) 2016 - 2022, Texas Instruments Incorporated
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
PACKAGE_SRCS_COMMON += src/flash/nor/device/s25fl256s.h
endif
+ifeq ($(BOARD),$(filter $(BOARD), j721s2_evm))
+SRCDIR += src/flash/nor src/flash/nor/device src/flash/nor/ospi
+SRCDIR += src/flash/nand src/flash/nand/device src/flash/nand/ospi
+INCDIR += src/flash/nor src/flash/nor/device src/flash/nor/ospi
+INCDIR += src/flash/nand src/flash/nand/device src/flash/nand/ospi
+SRCS_COMMON += nor_xspi.c nor.c nor_spi_patterns.c nor_spi_phy_tune.c
+SRCS_COMMON += nand.c nand_ospi.c
+SRCS_COMMON += nor_qspi.c
+PACKAGE_SRCS_COMMON += src/flash/nor/nor.c src/flash/nor/nor.h
+PACKAGE_SRCS_COMMON += src/flash/nand/nand.c src/flash/nand/nand.h
+PACKAGE_SRCS_COMMON += src/flash/nor/ospi/nor_xspi.c src/flash/nor/ospi/nor_xspi.h
+PACKAGE_SRCS_COMMON += src/flash/nand/ospi/nand_ospi.c src/flash/nand/ospi/nand_ospi.h
+PACKAGE_SRCS_COMMON += src/flash/nor/ospi/nor_qspi.c src/flash/nor/ospi/nor_qspi.h
+PACKAGE_SRCS_COMMON += src/flash/nor/device/s28hs512t.h
+PACKAGE_SRCS_COMMON += src/flash/nand/device/w35n01jwtbag.h
+PACKAGE_SRCS_COMMON += src/flash/nor/device/mt25qu512abb.h
+PACKAGE_SRCS_COMMON += src/flash/nor/ospi/nor_spi_patterns.c src/flash/nor/ospi/nor_spi_patterns.h
+PACKAGE_SRCS_COMMON += src/flash/nor/ospi/nor_spi_phy_tune.c src/flash/nor/ospi/nor_spi_phy_tune.h
+PACKAGE_SRCS_COMMON += src/flash/nor/ospi/nor_spi_patterns.bin
+endif
+
ifeq ($(BOARD),$(filter $(BOARD), am64x_evm am64x_svb am640x_svb))
SRCS_COMMON += nor_qspi.c
PACKAGE_SRCS_COMMON += src/flash/nor/ospi/nor_qspi.c src/flash/nor/ospi/nor_qspi.h
diff --git a/packages/ti/board/src/j721s2_evm/J721S2_pinmux.h b/packages/ti/board/src/j721s2_evm/J721S2_pinmux.h
--- /dev/null
@@ -0,0 +1,220 @@
+/**
+ * Note: This file was auto-generated by TI PinMux on 10/24/2021.
+ *
+ * \file J721S2_pinmux.h
+ *
+ * \brief This file contains pad configure register offsets and bit-field
+ * value macros for different configurations,
+ *
+ * BIT[21] TXDISABLE disable the pin's output driver
+ * BIT[18] RXACTIVE enable the pin's input buffer (typically kept enabled)
+ * BIT[17] PULLTYPESEL set the iternal resistor pull direction high or low (if enabled)
+ * BIT[16] PULLUDEN internal resistor disable (0 = enabled / 1 = disabled)
+ * BIT[3:0] MUXMODE select the desired function on the given pin
+ *
+ * \copyright Copyright (CU) 2021 Texas Instruments Incorporated -
+ * http://www.ti.com/
+ */
+
+#ifndef _J721S2_PIN_MUX_H_
+#define _J721S2_PIN_MUX_H_
+
+/* ========================================================================== */
+/* Include Files */
+/* ========================================================================== */
+
+#include "ti/board/src/j721s2_evm/include/pinmux.h"
+#include "ti/csl/csl_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* ========================================================================== */
+/* Macros & Typedefs */
+/* ========================================================================== */
+#define PIN_MODE(mode) (mode)
+#define PINMUX_END (-1)
+
+/** \brief Active mode configurations */
+/** \brief Resistor enable */
+#define PIN_PULL_DISABLE (0x1U << 16U)
+/** \brief Pull direction */
+#define PIN_PULL_DIRECTION (0x1U << 17U)
+/** \brief Receiver enable */
+#define PIN_INPUT_ENABLE (0x1U << 18U)
+/** \brief Driver disable */
+#define PIN_OUTPUT_DISABLE (0x1U << 21U)
+/** \brief Wakeup enable */
+#define PIN_WAKEUP_ENABLE (0x1U << 29U)
+
+/** \brief Pad config register offset in control module */
+
+enum pinMainOffsets
+{
+ PIN_MCASP1_AXR0 = 0x0C0,
+ PIN_MCASP1_AFSX = 0x0BC,
+ PIN_MCASP1_ACLKX = 0x0B8,
+ PIN_MCASP0_AXR12 = 0x0A0,
+ PIN_MCASP0_AXR13 = 0x0A4,
+ PIN_MCASP0_AXR14 = 0x0A8,
+ PIN_MCASP1_AXR3 = 0x0B0,
+ PIN_MCASP0_AXR15 = 0x0AC,
+ PIN_MCASP0_AXR7 = 0x08C,
+ PIN_MCASP0_AXR8 = 0x090,
+ PIN_MCASP0_AXR9 = 0x094,
+ PIN_MCASP0_AXR10 = 0x098,
+ PIN_MCASP1_AXR4 = 0x0B4,
+ PIN_MCASP0_AXR11 = 0x09C,
+ PIN_MCAN13_TX = 0x00C,
+ PIN_MCAN15_RX = 0x020,
+ PIN_GPIO0_11 = 0x02C,
+ PIN_PMIC_WAKE0 = 0x034,
+ PIN_MCASP0_AXR2 = 0x048,
+ PIN_MCASP2_AXR0 = 0x05C,
+ PIN_MCAN0_RX = 0x068,
+ PIN_MCAN1_RX = 0x070,
+ PIN_SPI0_CS0 = 0x0CC,
+ PIN_I2C0_SCL = 0x0E0,
+ PIN_I2C0_SDA = 0x0E4,
+ PIN_ECAP0_IN_APWM_OUT = 0x0C4,
+ PIN_EXT_REFCLK1 = 0x0C8,
+ PIN_MCAN0_TX = 0x064,
+ PIN_MCASP2_AXR1 = 0x060,
+ PIN_MCAN14_TX = 0x014,
+ PIN_MCAN13_RX = 0x010,
+ PIN_MCAN15_TX = 0x01C,
+ PIN_MCAN14_RX = 0x018,
+ PIN_MCAN16_RX = 0x028,
+ PIN_MCAN16_TX = 0x024,
+ PIN_MCASP0_AXR4 = 0x080,
+ PIN_MCASP0_AXR3 = 0x07C,
+ PIN_MCASP0_AFSX = 0x03C,
+ PIN_MCASP0_ACLKX = 0x038,
+ PIN_MCASP0_AXR6 = 0x088,
+ PIN_MCASP0_AXR5 = 0x084,
+ PIN_MMC1_CLK = 0x104,
+ PIN_MMC1_CMD = 0x108,
+ PIN_MMC1_CLKLB = 0x100,
+ PIN_MMC1_DAT0 = 0x0FC,
+ PIN_MMC1_DAT1 = 0x0F8,
+ PIN_MMC1_DAT2 = 0x0F4,
+ PIN_MMC1_DAT3 = 0x0F0,
+ PIN_TIMER_IO0 = 0x0E8,
+ PIN_EXTINTN = 0x000,
+ PIN_RESETSTATZ = 0x10C,
+ PIN_SOC_SAFETY_ERRORN = 0x110,
+ PIN_MCASP0_AXR0 = 0x040,
+ PIN_MCASP0_AXR1 = 0x044,
+ PIN_SPI0_CS1 = 0x0D0,
+ PIN_SPI0_CLK = 0x0D4,
+ PIN_SPI0_D0 = 0x0D8,
+ PIN_SPI0_D1 = 0x0DC,
+ PIN_MCAN12_RX = 0x008,
+ PIN_MCAN12_TX = 0x004,
+ PIN_MCAN2_TX = 0x074,
+ PIN_MCAN2_RX = 0x078,
+ PIN_GPIO0_12 = 0x030,
+ PIN_MCAN1_TX = 0x06C,
+ PIN_MCASP1_AXR1 = 0x04C,
+ PIN_MCASP1_AXR2 = 0x050,
+ PIN_TIMER_IO1 = 0x0EC,
+};
+
+enum pinWkupOffsets
+{
+ PIN_MCU_ADC0_AIN0 = 0x134,
+ PIN_MCU_ADC0_AIN1 = 0x138,
+ PIN_MCU_ADC0_AIN2 = 0x13C,
+ PIN_MCU_ADC0_AIN3 = 0x140,
+ PIN_MCU_ADC0_AIN4 = 0x144,
+ PIN_MCU_ADC0_AIN5 = 0x148,
+ PIN_MCU_ADC0_AIN6 = 0x14C,
+ PIN_MCU_ADC0_AIN7 = 0x150,
+ PIN_MCU_ADC1_AIN0 = 0x154,
+ PIN_MCU_ADC1_AIN1 = 0x158,
+ PIN_MCU_ADC1_AIN2 = 0x15C,
+ PIN_MCU_ADC1_AIN3 = 0x160,
+ PIN_MCU_ADC1_AIN4 = 0x164,
+ PIN_MCU_ADC1_AIN5 = 0x168,
+ PIN_MCU_ADC1_AIN6 = 0x16C,
+ PIN_MCU_ADC1_AIN7 = 0x170,
+ PIN_MCU_RGMII1_RD0 = 0x094,
+ PIN_MCU_RGMII1_RD1 = 0x090,
+ PIN_MCU_RGMII1_RD2 = 0x08C,
+ PIN_MCU_RGMII1_RD3 = 0x088,
+ PIN_MCU_RGMII1_RXC = 0x084,
+ PIN_MCU_RGMII1_RX_CTL = 0x06C,
+ PIN_MCU_RGMII1_TD0 = 0x07C,
+ PIN_MCU_RGMII1_TD1 = 0x078,
+ PIN_MCU_RGMII1_TD2 = 0x074,
+ PIN_MCU_RGMII1_TD3 = 0x070,
+ PIN_MCU_RGMII1_TXC = 0x080,
+ PIN_MCU_RGMII1_TX_CTL = 0x068,
+ PIN_MCU_I2C0_SCL = 0x108,
+ PIN_MCU_I2C0_SDA = 0x10C,
+ PIN_WKUP_GPIO0_8 = 0x0E0,
+ PIN_WKUP_GPIO0_9 = 0x0E4,
+ PIN_WKUP_GPIO0_11 = 0x0EC,
+ PIN_MCU_MCAN0_RX = 0x0BC,
+ PIN_MCU_MCAN0_TX = 0x0B8,
+ PIN_WKUP_GPIO0_5 = 0x0D4,
+ PIN_WKUP_GPIO0_4 = 0x0D0,
+ PIN_MCU_MDIO0_MDC = 0x09C,
+ PIN_MCU_MDIO0_MDIO = 0x098,
+ PIN_MCU_OSPI0_CLK = 0x000,
+ PIN_MCU_OSPI0_CSN0 = 0x02C,
+ PIN_MCU_OSPI0_D0 = 0x00C,
+ PIN_MCU_OSPI0_D1 = 0x010,
+ PIN_MCU_OSPI0_D2 = 0x014,
+ PIN_MCU_OSPI0_D3 = 0x018,
+ PIN_MCU_OSPI0_D4 = 0x01C,
+ PIN_MCU_OSPI0_D5 = 0x020,
+ PIN_MCU_OSPI0_D6 = 0x024,
+ PIN_MCU_OSPI0_D7 = 0x028,
+ PIN_MCU_OSPI0_DQS = 0x008,
+ PIN_MCU_OSPI0_CSN3 = 0x03C,
+ PIN_MCU_OSPI0_CSN2 = 0x038,
+ PIN_MCU_OSPI1_CLK = 0x040,
+ PIN_MCU_OSPI1_CSN0 = 0x05C,
+ PIN_MCU_OSPI1_D0 = 0x04C,
+ PIN_MCU_OSPI1_D1 = 0x050,
+ PIN_MCU_OSPI1_D2 = 0x054,
+ PIN_MCU_OSPI1_D3 = 0x058,
+ PIN_MCU_OSPI1_DQS = 0x048,
+ PIN_MCU_OSPI1_LBCLKO = 0x044,
+ PIN_WKUP_GPIO0_14 = 0x0F8,
+ PIN_WKUP_GPIO0_15 = 0x0FC,
+ PIN_WKUP_GPIO0_13 = 0x0F4,
+ PIN_WKUP_GPIO0_12 = 0x0F0,
+ PIN_WKUP_GPIO0_0 = 0x0C0,
+ PIN_WKUP_GPIO0_1 = 0x0C4,
+ PIN_WKUP_GPIO0_2 = 0x0C8,
+ PIN_WKUP_GPIO0_3 = 0x0CC,
+ PIN_WKUP_GPIO0_6 = 0x0D8,
+ PIN_WKUP_GPIO0_7 = 0x0DC,
+ PIN_MCU_OSPI1_CSN1 = 0x060,
+ PIN_WKUP_GPIO0_49 = 0x190,
+ PIN_MCU_SPI0_D0 = 0x0A4,
+ PIN_WKUP_GPIO0_56 = 0x120,
+ PIN_MCU_SPI0_D1 = 0x0A8,
+ PIN_MCU_SPI0_CS0 = 0x0AC,
+ PIN_WKUP_I2C0_SCL = 0x100,
+ PIN_WKUP_I2C0_SDA = 0x104,
+ PIN_WKUP_UART0_RXD = 0x0B0,
+ PIN_WKUP_UART0_TXD = 0x0B4,
+};
+
+/* ========================================================================== */
+/* Global Variables */
+/* ========================================================================== */
+
+/** \brief Pinmux configuration data for the board. Auto-generated from
+ Pinmux tool. */
+extern pinmuxBoardCfg_t gJ721S2_MainPinmuxData[];
+extern pinmuxBoardCfg_t gJ721S2_WkupPinmuxData[];
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _J721S2_PIN_MUX_H_ */
diff --git a/packages/ti/board/src/j721s2_evm/J721S2_pinmux_data.c b/packages/ti/board/src/j721s2_evm/J721S2_pinmux_data.c
--- /dev/null
@@ -0,0 +1,1103 @@
+/**
+* Note: This file was auto-generated by TI PinMux on 10/24/2021 at 3:31:41 AM.
+*
+* \file J721S2_pinmux_data.c
+*
+* \brief This file contains the pin mux configurations for the boards.
+* These are prepared based on how the peripherals are extended on
+* the boards.
+*
+* \copyright Copyright (CU) 2021 Texas Instruments Incorporated -
+* http://www.ti.com/
+*/
+
+/* ========================================================================== */
+/* Include Files */
+/* ========================================================================== */
+
+#include "J721S2_pinmux.h"
+
+/** Peripheral Pin Configurations */
+
+
+static pinmuxPerCfg_t gCpsw2g0PinCfg[] =
+{
+ /* MyCPSW2G0 -> MDIO0_MDC -> T28 */
+ {
+ PIN_MCASP1_AXR0, PIN_MODE(6) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyCPSW2G0 -> MDIO0_MDIO -> V28 */
+ {
+ PIN_MCASP1_AFSX, PIN_MODE(6) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyCPSW2G0 -> RGMII1_RD0 -> AA24 */
+ {
+ PIN_MCASP1_ACLKX, PIN_MODE(6) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyCPSW2G0 -> RGMII1_RD1 -> AB25 */
+ {
+ PIN_MCASP0_AXR12, PIN_MODE(6) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyCPSW2G0 -> RGMII1_RD2 -> T23 */
+ {
+ PIN_MCASP0_AXR13, PIN_MODE(6) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyCPSW2G0 -> RGMII1_RD3 -> U24 */
+ {
+ PIN_MCASP0_AXR14, PIN_MODE(6) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyCPSW2G0 -> RGMII1_RXC -> AD26 */
+ {
+ PIN_MCASP1_AXR3, PIN_MODE(6) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyCPSW2G0 -> RGMII1_RX_CTL -> AC25 */
+ {
+ PIN_MCASP0_AXR15, PIN_MODE(6) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyCPSW2G0 -> RGMII1_TD0 -> T25 */
+ {
+ PIN_MCASP0_AXR7, PIN_MODE(6) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyCPSW2G0 -> RGMII1_TD1 -> W24 */
+ {
+ PIN_MCASP0_AXR8, PIN_MODE(6) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyCPSW2G0 -> RGMII1_TD2 -> AA25 */
+ {
+ PIN_MCASP0_AXR9, PIN_MODE(6) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyCPSW2G0 -> RGMII1_TD3 -> V25 */
+ {
+ PIN_MCASP0_AXR10, PIN_MODE(6) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyCPSW2G0 -> RGMII1_TXC -> U25 */
+ {
+ PIN_MCASP1_AXR4, PIN_MODE(6) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyCPSW2G0 -> RGMII1_TX_CTL -> T24 */
+ {
+ PIN_MCASP0_AXR11, PIN_MODE(6) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ {PINMUX_END}
+};
+
+static pinmuxModuleCfg_t gCpsw2gPinCfg[] =
+{
+ {0, TRUE, gCpsw2g0PinCfg},
+ {PINMUX_END}
+};
+
+
+static pinmuxPerCfg_t gGpio0PinCfg[] =
+{
+ /* MyGPIO0 -> GPIO0_3 -> AE28 */
+ {
+ PIN_MCAN13_TX, PIN_MODE(7) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyGPIO0 -> GPIO0_8 -> AA23 */
+ {
+ PIN_MCAN15_RX, PIN_MODE(7) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyGPIO0 -> GPIO0_11 -> V23 */
+ {
+ PIN_GPIO0_11, PIN_MODE(7) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyGPIO0 -> GPIO0_13 -> AD24 */
+ {
+ PIN_PMIC_WAKE0, PIN_MODE(7) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyGPIO0 -> GPIO0_18 -> AB27 */
+ {
+ PIN_MCASP0_AXR2, PIN_MODE(7) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyGPIO0 -> GPIO0_23 -> AA26 */
+ {
+ PIN_MCASP2_AXR0, PIN_MODE(7) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyGPIO0 -> GPIO0_26 -> U28 */
+ {
+ PIN_MCAN0_RX, PIN_MODE(7) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyGPIO0 -> GPIO0_28 -> R27 */
+ {
+ PIN_MCAN1_RX, PIN_MODE(7) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyGPIO0 -> GPIO0_51 -> AE27 */
+ {
+ PIN_SPI0_CS0, PIN_MODE(7) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ {PINMUX_END}
+};
+
+static pinmuxModuleCfg_t gGpioPinCfg[] =
+{
+ {0, TRUE, gGpio0PinCfg},
+ {PINMUX_END}
+};
+
+
+static pinmuxPerCfg_t gI2c0PinCfg[] =
+{
+ /* MyI2C0 -> I2C0_SCL -> AH25 */
+ {
+ PIN_I2C0_SCL, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyI2C0 -> I2C0_SDA -> AE24 */
+ {
+ PIN_I2C0_SDA, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ {PINMUX_END}
+};
+
+static pinmuxPerCfg_t gI2c1PinCfg[] =
+{
+ /* MyI2C1 -> I2C1_SCL -> AB26 */
+ {
+ PIN_ECAP0_IN_APWM_OUT, PIN_MODE(13) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyI2C1 -> I2C1_SDA -> AD28 */
+ {
+ PIN_EXT_REFCLK1, PIN_MODE(13) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ {PINMUX_END}
+};
+
+static pinmuxPerCfg_t gI2c3PinCfg[] =
+{
+ /* MyI2C3 -> I2C3_SCL -> W28 */
+ {
+ PIN_MCAN0_TX, PIN_MODE(13) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyI2C3 -> I2C3_SDA -> AC27 */
+ {
+ PIN_MCASP2_AXR1, PIN_MODE(13) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ {PINMUX_END}
+};
+
+static pinmuxPerCfg_t gI2c4PinCfg[] =
+{
+ /* MyI2C4 -> I2C4_SCL -> AD25 */
+ {
+ PIN_MCAN14_TX, PIN_MODE(8) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyI2C4 -> I2C4_SDA -> AF28 */
+ {
+ PIN_MCAN13_RX, PIN_MODE(8) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ {PINMUX_END}
+};
+
+static pinmuxPerCfg_t gI2c5PinCfg[] =
+{
+ /* MyI2C5 -> I2C5_SCL -> Y24 */
+ {
+ PIN_MCAN15_TX, PIN_MODE(8) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyI2C5 -> I2C5_SDA -> W23 */
+ {
+ PIN_MCAN14_RX, PIN_MODE(8) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ {PINMUX_END}
+};
+
+static pinmuxModuleCfg_t gI2cPinCfg[] =
+{
+ {0, TRUE, gI2c0PinCfg},
+ {1, TRUE, gI2c1PinCfg},
+ {3, TRUE, gI2c3PinCfg},
+ {4, TRUE, gI2c4PinCfg},
+ {5, TRUE, gI2c5PinCfg},
+ {PINMUX_END}
+};
+
+
+static pinmuxPerCfg_t gMcan6PinCfg[] =
+{
+ /* MyMCAN16 -> MCAN16_RX -> AB24 */
+ {
+ PIN_MCAN16_RX, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyMCAN16 -> MCAN16_TX -> Y28 */
+ {
+ PIN_MCAN16_TX, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ {PINMUX_END}
+};
+
+static pinmuxPerCfg_t gMcan3PinCfg[] =
+{
+ /* MyMCAN3 -> MCAN3_RX -> U26 */
+ {
+ PIN_MCASP0_AXR4, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyMCAN3 -> MCAN3_TX -> T27 */
+ {
+ PIN_MCASP0_AXR3, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ {PINMUX_END}
+};
+
+static pinmuxPerCfg_t gMcan5PinCfg[] =
+{
+ /* MyMCAN5 -> MCAN5_RX -> U27 */
+ {
+ PIN_MCASP0_AFSX, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyMCAN5 -> MCAN5_TX -> AB28 */
+ {
+ PIN_MCASP0_ACLKX, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ {PINMUX_END}
+};
+
+static pinmuxPerCfg_t gMcan4PinCfg[] =
+{
+ /* MyMCAN4 -> MCAN4_RX -> AD27 */
+ {
+ PIN_MCASP0_AXR6, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyMCAN4 -> MCAN4_TX -> AA28 */
+ {
+ PIN_MCASP0_AXR5, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ {PINMUX_END}
+};
+
+static pinmuxModuleCfg_t gMcanPinCfg[] =
+{
+ {6, TRUE, gMcan6PinCfg},
+ {3, TRUE, gMcan3PinCfg},
+ {5, TRUE, gMcan5PinCfg},
+ {4, TRUE, gMcan4PinCfg},
+ {PINMUX_END}
+};
+
+
+static pinmuxPerCfg_t gMcu_adc0PinCfg[] =
+{
+ /* MyMCU_ADC0 -> MCU_ADC0_AIN0 -> L25 */
+ {
+ PIN_MCU_ADC0_AIN0, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyMCU_ADC0 -> MCU_ADC0_AIN1 -> K25 */
+ {
+ PIN_MCU_ADC0_AIN1, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyMCU_ADC0 -> MCU_ADC0_AIN2 -> M24 */
+ {
+ PIN_MCU_ADC0_AIN2, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyMCU_ADC0 -> MCU_ADC0_AIN3 -> L24 */
+ {
+ PIN_MCU_ADC0_AIN3, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyMCU_ADC0 -> MCU_ADC0_AIN4 -> L27 */
+ {
+ PIN_MCU_ADC0_AIN4, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyMCU_ADC0 -> MCU_ADC0_AIN5 -> K24 */
+ {
+ PIN_MCU_ADC0_AIN5, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyMCU_ADC0 -> MCU_ADC0_AIN6 -> M27 */
+ {
+ PIN_MCU_ADC0_AIN6, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyMCU_ADC0 -> MCU_ADC0_AIN7 -> M26 */
+ {
+ PIN_MCU_ADC0_AIN7, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ {PINMUX_END}
+};
+
+static pinmuxPerCfg_t gMcu_adc1PinCfg[] =
+{
+ /* MyMCU_ADC1 -> MCU_ADC1_AIN0 -> P25 */
+ {
+ PIN_MCU_ADC1_AIN0, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyMCU_ADC1 -> MCU_ADC1_AIN1 -> R25 */
+ {
+ PIN_MCU_ADC1_AIN1, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyMCU_ADC1 -> MCU_ADC1_AIN2 -> P28 */
+ {
+ PIN_MCU_ADC1_AIN2, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyMCU_ADC1 -> MCU_ADC1_AIN3 -> P27 */
+ {
+ PIN_MCU_ADC1_AIN3, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyMCU_ADC1 -> MCU_ADC1_AIN4 -> N25 */
+ {
+ PIN_MCU_ADC1_AIN4, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyMCU_ADC1 -> MCU_ADC1_AIN5 -> P26 */
+ {
+ PIN_MCU_ADC1_AIN5, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyMCU_ADC1 -> MCU_ADC1_AIN6 -> N26 */
+ {
+ PIN_MCU_ADC1_AIN6, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyMCU_ADC1 -> MCU_ADC1_AIN7 -> N27 */
+ {
+ PIN_MCU_ADC1_AIN7, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ {PINMUX_END}
+};
+
+static pinmuxModuleCfg_t gMcu_adcPinCfg[] =
+{
+ {0, TRUE, gMcu_adc0PinCfg},
+ {1, TRUE, gMcu_adc1PinCfg},
+ {PINMUX_END}
+};
+
+
+static pinmuxPerCfg_t gMcu_cpsw2g0PinCfg[] =
+{
+ /* MyMCU_CPSW2G0 -> MCU_RGMII1_RD0 -> B22 */
+ {
+ PIN_MCU_RGMII1_RD0, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyMCU_CPSW2G0 -> MCU_RGMII1_RD1 -> B21 */
+ {
+ PIN_MCU_RGMII1_RD1, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyMCU_CPSW2G0 -> MCU_RGMII1_RD2 -> C22 */
+ {
+ PIN_MCU_RGMII1_RD2, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyMCU_CPSW2G0 -> MCU_RGMII1_RD3 -> D23 */
+ {
+ PIN_MCU_RGMII1_RD3, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyMCU_CPSW2G0 -> MCU_RGMII1_RXC -> D22 */
+ {
+ PIN_MCU_RGMII1_RXC, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyMCU_CPSW2G0 -> MCU_RGMII1_RX_CTL -> E23 */
+ {
+ PIN_MCU_RGMII1_RX_CTL, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyMCU_CPSW2G0 -> MCU_RGMII1_TD0 -> F23 */
+ {
+ PIN_MCU_RGMII1_TD0, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyMCU_CPSW2G0 -> MCU_RGMII1_TD1 -> G22 */
+ {
+ PIN_MCU_RGMII1_TD1, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyMCU_CPSW2G0 -> MCU_RGMII1_TD2 -> E21 */
+ {
+ PIN_MCU_RGMII1_TD2, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyMCU_CPSW2G0 -> MCU_RGMII1_TD3 -> E22 */
+ {
+ PIN_MCU_RGMII1_TD3, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyMCU_CPSW2G0 -> MCU_RGMII1_TXC -> F21 */
+ {
+ PIN_MCU_RGMII1_TXC, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyMCU_CPSW2G0 -> MCU_RGMII1_TX_CTL -> F22 */
+ {
+ PIN_MCU_RGMII1_TX_CTL, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ {PINMUX_END}
+};
+
+static pinmuxModuleCfg_t gMcu_cpsw2gPinCfg[] =
+{
+ {0, TRUE, gMcu_cpsw2g0PinCfg},
+ {PINMUX_END}
+};
+
+
+static pinmuxPerCfg_t gMcu_i2c0PinCfg[] =
+{
+ /* MyMCU_I2C0 -> MCU_I2C0_SCL -> G24 */
+ {
+ PIN_MCU_I2C0_SCL, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyMCU_I2C0 -> MCU_I2C0_SDA -> J25 */
+ {
+ PIN_MCU_I2C0_SDA, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ {PINMUX_END}
+};
+
+static pinmuxModuleCfg_t gMcu_i2cPinCfg[] =
+{
+ {0, TRUE, gMcu_i2c0PinCfg},
+ {PINMUX_END}
+};
+
+
+static pinmuxPerCfg_t gMcu_i3c0PinCfg[] =
+{
+ /* MyMCU_I3C1 -> MCU_I3C0_SCL -> F24 */
+ {
+ PIN_WKUP_GPIO0_8, PIN_MODE(3) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyMCU_I3C1 -> MCU_I3C0_SDA -> H26 */
+ {
+ PIN_WKUP_GPIO0_9, PIN_MODE(3) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyMCU_I3C1 -> MCU_I3C0_SDAPULLEN -> F25 */
+ {
+ PIN_WKUP_GPIO0_11, PIN_MODE(5) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ {PINMUX_END}
+};
+
+static pinmuxModuleCfg_t gMcu_i3cPinCfg[] =
+{
+ {0, TRUE, gMcu_i3c0PinCfg},
+ {PINMUX_END}
+};
+
+
+static pinmuxPerCfg_t gMcu_mcan0PinCfg[] =
+{
+ /* MyMCU_MCAN0 -> MCU_MCAN0_RX -> E28 */
+ {
+ PIN_MCU_MCAN0_RX, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyMCU_MCAN0 -> MCU_MCAN0_TX -> E27 */
+ {
+ PIN_MCU_MCAN0_TX, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ {PINMUX_END}
+};
+
+static pinmuxPerCfg_t gMcu_mcan1PinCfg[] =
+{
+ /* MyMCU_MCAN1 -> MCU_MCAN1_RX -> F26 */
+ {
+ PIN_WKUP_GPIO0_5, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyMCU_MCAN1 -> MCU_MCAN1_TX -> C23 */
+ {
+ PIN_WKUP_GPIO0_4, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ {PINMUX_END}
+};
+
+static pinmuxModuleCfg_t gMcu_mcanPinCfg[] =
+{
+ {0, TRUE, gMcu_mcan0PinCfg},
+ {1, TRUE, gMcu_mcan1PinCfg},
+ {PINMUX_END}
+};
+
+
+static pinmuxPerCfg_t gMcu_mdio0PinCfg[] =
+{
+ /* MyMCU_MDIO0 -> MCU_MDIO0_MDC -> A21 */
+ {
+ PIN_MCU_MDIO0_MDC, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyMCU_MDIO0 -> MCU_MDIO0_MDIO -> A22 */
+ {
+ PIN_MCU_MDIO0_MDIO, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ {PINMUX_END}
+};
+
+static pinmuxModuleCfg_t gMcu_mdioPinCfg[] =
+{
+ {0, TRUE, gMcu_mdio0PinCfg},
+ {PINMUX_END}
+};
+
+
+static pinmuxPerCfg_t gMcu_ospi0PinCfg[] =
+{
+ /* MyMCU_OSPI0 -> MCU_OSPI0_CLK -> D19 */
+ {
+ PIN_MCU_OSPI0_CLK, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyMCU_OSPI0 -> MCU_OSPI0_CSn0 -> F15 */
+ {
+ PIN_MCU_OSPI0_CSN0, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyMCU_OSPI0 -> MCU_OSPI0_D0 -> C19 */
+ {
+ PIN_MCU_OSPI0_D0, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyMCU_OSPI0 -> MCU_OSPI0_D1 -> F16 */
+ {
+ PIN_MCU_OSPI0_D1, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyMCU_OSPI0 -> MCU_OSPI0_D2 -> G15 */
+ {
+ PIN_MCU_OSPI0_D2, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyMCU_OSPI0 -> MCU_OSPI0_D3 -> F18 */
+ {
+ PIN_MCU_OSPI0_D3, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyMCU_OSPI0 -> MCU_OSPI0_D4 -> E19 */
+ {
+ PIN_MCU_OSPI0_D4, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyMCU_OSPI0 -> MCU_OSPI0_D5 -> G19 */
+ {
+ PIN_MCU_OSPI0_D5, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyMCU_OSPI0 -> MCU_OSPI0_D6 -> F19 */
+ {
+ PIN_MCU_OSPI0_D6, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyMCU_OSPI0 -> MCU_OSPI0_D7 -> F20 */
+ {
+ PIN_MCU_OSPI0_D7, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyMCU_OSPI0 -> MCU_OSPI0_DQS -> E18 */
+ {
+ PIN_MCU_OSPI0_DQS, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyMCU_OSPI0 -> MCU_OSPI0_ECC_FAIL -> F17 */
+ {
+ PIN_MCU_OSPI0_CSN3, PIN_MODE(6) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyMCU_OSPI0 -> MCU_OSPI0_RESET_OUT0 -> F14 */
+ {
+ PIN_MCU_OSPI0_CSN2, PIN_MODE(6) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ {PINMUX_END}
+};
+
+static pinmuxPerCfg_t gMcu_ospi1PinCfg[] =
+{
+ /* MyMCU_OSPI1 -> MCU_OSPI1_CLK -> A19 */
+ {
+ PIN_MCU_OSPI1_CLK, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyMCU_OSPI1 -> MCU_OSPI1_CSn0 -> D20 */
+ {
+ PIN_MCU_OSPI1_CSN0, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyMCU_OSPI1 -> MCU_OSPI1_D0 -> D21 */
+ {
+ PIN_MCU_OSPI1_D0, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyMCU_OSPI1 -> MCU_OSPI1_D1 -> G20 */
+ {
+ PIN_MCU_OSPI1_D1, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyMCU_OSPI1 -> MCU_OSPI1_D2 -> C20 */
+ {
+ PIN_MCU_OSPI1_D2, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyMCU_OSPI1 -> MCU_OSPI1_D3 -> A20 */
+ {
+ PIN_MCU_OSPI1_D3, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyMCU_OSPI1 -> MCU_OSPI1_DQS -> B19 */
+ {
+ PIN_MCU_OSPI1_DQS, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyMCU_OSPI1 -> MCU_OSPI1_LBCLKO -> B20 */
+ {
+ PIN_MCU_OSPI1_LBCLKO, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ {PINMUX_END}
+};
+
+static pinmuxModuleCfg_t gMcu_ospiPinCfg[] =
+{
+ {0, TRUE, gMcu_ospi0PinCfg},
+ {1, TRUE, gMcu_ospi1PinCfg},
+ {PINMUX_END}
+};
+
+
+static pinmuxPerCfg_t gMcu_uart0PinCfg[] =
+{
+ /* MyMCU_UART0 -> MCU_UART0_CTSn -> B24 */
+ {
+ PIN_WKUP_GPIO0_14, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyMCU_UART0 -> MCU_UART0_RTSn -> D25 */
+ {
+ PIN_WKUP_GPIO0_15, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyMCU_UART0 -> MCU_UART0_RXD -> C24 */
+ {
+ PIN_WKUP_GPIO0_13, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyMCU_UART0 -> MCU_UART0_TXD -> C25 */
+ {
+ PIN_WKUP_GPIO0_12, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ {PINMUX_END}
+};
+
+static pinmuxModuleCfg_t gMcu_uartPinCfg[] =
+{
+ {0, TRUE, gMcu_uart0PinCfg},
+ {PINMUX_END}
+};
+
+
+static pinmuxPerCfg_t gMmcsd1PinCfg[] =
+{
+ /* MyMMCSD1 -> MMC1_CLK -> P23 */
+ {
+ PIN_MMC1_CLK, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyMMCSD1 -> MMC1_CMD -> N24 */
+ {
+ PIN_MMC1_CMD, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyMMCSD1 -> MMC1_DAT0 -> M23 */
+ {
+ PIN_MMC1_DAT0, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyMMCSD1 -> MMC1_DAT1 -> P24 */
+ {
+ PIN_MMC1_DAT1, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyMMCSD1 -> MMC1_DAT2 -> R24 */
+ {
+ PIN_MMC1_DAT2, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyMMCSD1 -> MMC1_DAT3 -> R22 */
+ {
+ PIN_MMC1_DAT3, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyMMCSD1 -> MMC1_SDCD -> AE25 */
+ {
+ PIN_TIMER_IO0, PIN_MODE(8) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyMMC1 -> MMC1_CLKLB */
+ {
+ PIN_MMC1_CLKLB, PIN_MODE(0) | \
+ ((PIN_PULL_DIRECTION | PIN_INPUT_ENABLE) & (~PIN_PULL_DISABLE))
+ },
+ {PINMUX_END}
+};
+
+static pinmuxModuleCfg_t gMmcsdPinCfg[] =
+{
+ {1, TRUE, gMmcsd1PinCfg},
+ {PINMUX_END}
+};
+
+
+static pinmuxPerCfg_t gSystem0PinCfg[] =
+{
+ /* MySYSTEM0 -> EXTINTn -> AG24 */
+ {
+ PIN_EXTINTN, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MySYSTEM0 -> RESETSTATz -> AF27 */
+ {
+ PIN_RESETSTATZ, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MySYSTEM0 -> SOC_SAFETY_ERRORn -> AF25 */
+ {
+ PIN_SOC_SAFETY_ERRORN, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ {PINMUX_END}
+};
+
+static pinmuxModuleCfg_t gSystemPinCfg[] =
+{
+ {0, TRUE, gSystem0PinCfg},
+ {PINMUX_END}
+};
+
+
+static pinmuxPerCfg_t gUart8PinCfg[] =
+{
+ /* MyUART8 -> UART8_CTSn -> AC28 */
+ {
+ PIN_MCASP0_AXR0, PIN_MODE(14) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyUART8 -> UART8_RTSn -> Y26 */
+ {
+ PIN_MCASP0_AXR1, PIN_MODE(14) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyUART8 -> UART8_RXD -> AF26 */
+ {
+ PIN_SPI0_CS1, PIN_MODE(11) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyUART8 -> UART8_TXD -> AH27 */
+ {
+ PIN_SPI0_CLK, PIN_MODE(11) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ {PINMUX_END}
+};
+
+static pinmuxPerCfg_t gUart2PinCfg[] =
+{
+ /* MyUART2 -> UART2_RXD -> AG26 */
+ {
+ PIN_SPI0_D0, PIN_MODE(11) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyUART2 -> UART2_TXD -> AH26 */
+ {
+ PIN_SPI0_D1, PIN_MODE(11) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ {PINMUX_END}
+};
+
+static pinmuxPerCfg_t gUart5PinCfg[] =
+{
+ /* MyUART5 -> UART5_RXD -> AC24 */
+ {
+ PIN_MCAN12_RX, PIN_MODE(11) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyUART5 -> UART5_TXD -> W25 */
+ {
+ PIN_MCAN12_TX, PIN_MODE(11) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ {PINMUX_END}
+};
+
+static pinmuxPerCfg_t gUart3PinCfg[] =
+{
+ /* MyUART3 -> UART3_RXD -> R28 */
+ {
+ PIN_MCAN2_TX, PIN_MODE(11) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyUART3 -> UART3_TXD -> Y25 */
+ {
+ PIN_MCAN2_RX, PIN_MODE(11) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ {PINMUX_END}
+};
+
+static pinmuxPerCfg_t gUart6PinCfg[] =
+{
+ /* MyUART6 -> UART6_RXD -> T26 */
+ {
+ PIN_GPIO0_12, PIN_MODE(12) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyUART6 -> UART6_TXD -> V26 */
+ {
+ PIN_MCAN1_TX, PIN_MODE(11) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ {PINMUX_END}
+};
+
+static pinmuxPerCfg_t gUart9PinCfg[] =
+{
+ /* MyUART9 -> UART9_RXD -> V27 */
+ {
+ PIN_MCASP1_AXR1, PIN_MODE(12) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyUART9 -> UART9_TXD -> W27 */
+ {
+ PIN_MCASP1_AXR2, PIN_MODE(12) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ {PINMUX_END}
+};
+
+static pinmuxModuleCfg_t gUartPinCfg[] =
+{
+ {8, TRUE, gUart8PinCfg},
+ {2, TRUE, gUart2PinCfg},
+ {5, TRUE, gUart5PinCfg},
+ {3, TRUE, gUart3PinCfg},
+ {6, TRUE, gUart6PinCfg},
+ {9, TRUE, gUart9PinCfg},
+ {PINMUX_END}
+};
+
+
+static pinmuxPerCfg_t gUsb0PinCfg[] =
+{
+ /* MyUSB0 -> USB0_DRVVBUS -> AG25 */
+ {
+ PIN_TIMER_IO1, PIN_MODE(6) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ {PINMUX_END}
+};
+
+static pinmuxModuleCfg_t gUsbPinCfg[] =
+{
+ {0, TRUE, gUsb0PinCfg},
+ {PINMUX_END}
+};
+
+
+static pinmuxPerCfg_t gWkup_gpio0PinCfg[] =
+{
+ /* MyWKUP_GPIO0 -> WKUP_GPIO0_0 -> D26 */
+ {
+ PIN_WKUP_GPIO0_0, PIN_MODE(7) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyWKUP_GPIO0 -> WKUP_GPIO0_1 -> E24 */
+ {
+ PIN_WKUP_GPIO0_1, PIN_MODE(7) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyWKUP_GPIO0 -> WKUP_GPIO0_2 -> C28 */
+ {
+ PIN_WKUP_GPIO0_2, PIN_MODE(7) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyWKUP_GPIO0 -> WKUP_GPIO0_3 -> C27 */
+ {
+ PIN_WKUP_GPIO0_3, PIN_MODE(7) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyWKUP_GPIO0 -> WKUP_GPIO0_6 -> E25 */
+ {
+ PIN_WKUP_GPIO0_6, PIN_MODE(7) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyWKUP_GPIO0 -> WKUP_GPIO0_7 -> F28 */
+ {
+ PIN_WKUP_GPIO0_7, PIN_MODE(7) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyWKUP_GPIO0 -> WKUP_GPIO0_39 -> C21 */
+ {
+ PIN_MCU_OSPI1_CSN1, PIN_MODE(7) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyWKUP_GPIO0 -> WKUP_GPIO0_49 -> K26 */
+ {
+ PIN_WKUP_GPIO0_49, PIN_MODE(7) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyWKUP_GPIO0 -> WKUP_GPIO0_55 -> D24 */
+ {
+ PIN_MCU_SPI0_D0, PIN_MODE(7) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyWKUP_GPIO0 -> WKUP_GPIO0_56 -> G27 */
+ {
+ PIN_WKUP_GPIO0_56, PIN_MODE(7) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyWKUP_GPIO0 -> WKUP_GPIO0_69 -> B25 */
+ {
+ PIN_MCU_SPI0_D1, PIN_MODE(7) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyWKUP_GPIO0 -> WKUP_GPIO0_70 -> B26 */
+ {
+ PIN_MCU_SPI0_CS0, PIN_MODE(7) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ {PINMUX_END}
+};
+
+static pinmuxModuleCfg_t gWkup_gpioPinCfg[] =
+{
+ {0, TRUE, gWkup_gpio0PinCfg},
+ {PINMUX_END}
+};
+
+
+static pinmuxPerCfg_t gWkup_i2c0PinCfg[] =
+{
+ /* MyWKUP_I2C0 -> WKUP_I2C0_SCL -> H24 */
+ {
+ PIN_WKUP_I2C0_SCL, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyWKUP_I2C0 -> WKUP_I2C0_SDA -> H27 */
+ {
+ PIN_WKUP_I2C0_SDA, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ {PINMUX_END}
+};
+
+static pinmuxModuleCfg_t gWkup_i2cPinCfg[] =
+{
+ {0, TRUE, gWkup_i2c0PinCfg},
+ {PINMUX_END}
+};
+
+
+static pinmuxPerCfg_t gWkup_uart0PinCfg[] =
+{
+ /* MyWKUP_UART0 -> WKUP_UART0_RXD -> D28 */
+ {
+ PIN_WKUP_UART0_RXD, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ /* MyWKUP_UART0 -> WKUP_UART0_TXD -> D27 */
+ {
+ PIN_WKUP_UART0_TXD, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+ },
+ {PINMUX_END}
+};
+
+static pinmuxModuleCfg_t gWkup_uartPinCfg[] =
+{
+ {0, TRUE, gWkup_uart0PinCfg},
+ {PINMUX_END}
+};
+
+
+pinmuxBoardCfg_t gJ721S2_MainPinmuxData[] =
+{
+ {0, gCpsw2gPinCfg},
+ {1, gGpioPinCfg},
+ {2, gI2cPinCfg},
+ {3, gMcanPinCfg},
+ {4, gMmcsdPinCfg},
+ {5, gSystemPinCfg},
+ {6, gUartPinCfg},
+ {7, gUsbPinCfg},
+ {PINMUX_END}
+};
+
+pinmuxBoardCfg_t gJ721S2_WkupPinmuxData[] =
+{
+ {0, gMcu_adcPinCfg},
+ {1, gMcu_cpsw2gPinCfg},
+ {2, gMcu_i2cPinCfg},
+ {3, gMcu_i3cPinCfg},
+ {4, gMcu_mcanPinCfg},
+ {5, gMcu_mdioPinCfg},
+ {6, gMcu_ospiPinCfg},
+ {7, gMcu_uartPinCfg},
+ {8, gWkup_gpioPinCfg},
+ {9, gWkup_i2cPinCfg},
+ {10, gWkup_uartPinCfg},
+ {PINMUX_END}
+};
diff --git a/packages/ti/board/src/j721s2_evm/board_clock.c b/packages/ti/board/src/j721s2_evm/board_clock.c
--- /dev/null
@@ -0,0 +1,538 @@
+/******************************************************************************
+ * Copyright (c) 2021 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *****************************************************************************/
+
+ /** \file board_clock.c
+ *
+ * \brief This file contains initialization of wakeup and main PSC
+ * configuration structures and function definitions to get the number
+ * of wakeup and main PSC config exists.
+ */
+
+#include "board_clock.h"
+#include "board_utils.h"
+#include <ti/drv/sciclient/sciclient.h>
+
+extern Board_initParams_t gBoardInitParams;
+
+uint32_t gBoardClkModuleMcuIDInitGroupl[] = {
+ TISCI_DEV_MCU_TIMER0,
+ TISCI_DEV_MCU_FSS0_OSPI_0,
+ TISCI_DEV_MCU_FSS0_OSPI_1,
+ TISCI_DEV_MCU_FSS0_FSAS_0,
+ TISCI_DEV_MCU_FSS0_HYPERBUS1P0_0,
+ TISCI_DEV_MCU_FSS0,
+ TISCI_DEV_MCU_UART0,
+ TISCI_DEV_WKUP_I2C0,
+ TISCI_DEV_WKUP_UART0,
+};
+
+uint32_t gBoardClkModuleMcuIDInitGroup2[] = {
+ TISCI_DEV_MCU_ADC12FC_16FFC0,
+ TISCI_DEV_MCU_ADC12FC_16FFC1,
+ TISCI_DEV_MCU_CPSW0,
+ TISCI_DEV_WKUP_GPIO0,
+ TISCI_DEV_WKUP_GPIO1,
+ TISCI_DEV_WKUP_GPIOMUX_INTRTR0,
+ TISCI_DEV_MCU_MCAN0,
+ TISCI_DEV_MCU_MCAN1,
+ TISCI_DEV_MCU_I2C0,
+ TISCI_DEV_MCU_I2C1,
+ TISCI_DEV_MCU_CPT2_AGGR0,
+ TISCI_DEV_MCU_DCC0,
+ TISCI_DEV_MCU_DCC1,
+ TISCI_DEV_MCU_DCC2,
+ TISCI_DEV_MCU_TIMER1,
+ TISCI_DEV_MCU_TIMER2,
+ TISCI_DEV_MCU_TIMER3,
+ TISCI_DEV_MCU_TIMER4,
+ TISCI_DEV_MCU_TIMER5,
+ TISCI_DEV_MCU_TIMER6,
+ TISCI_DEV_MCU_TIMER7,
+ TISCI_DEV_MCU_TIMER8,
+ TISCI_DEV_MCU_TIMER9,
+ TISCI_DEV_WKUP_ESM0,
+ TISCI_DEV_MCU_ESM0,
+ TISCI_DEV_MCU_MCSPI0,
+ TISCI_DEV_MCU_MCSPI1,
+ TISCI_DEV_MCU_MCSPI2,
+};
+
+uint32_t gBoardClkModuleMcuIDDeinitGroupl[] = {
+ TISCI_DEV_MCU_FSS0_OSPI_0,
+ TISCI_DEV_MCU_FSS0_OSPI_1,
+ TISCI_DEV_MCU_FSS0_FSAS_0,
+ TISCI_DEV_MCU_FSS0_HYPERBUS1P0_0,
+ TISCI_DEV_MCU_FSS0,
+ TISCI_DEV_WKUP_I2C0,
+};
+
+uint32_t gBoardClkModuleMainIDInitGroup1[] = {
+ TISCI_DEV_DDR0,
+ TISCI_DEV_DDR1,
+ TISCI_DEV_EMIF_DATA_0_VD,
+ TISCI_DEV_EMIF_DATA_1_VD,
+ TISCI_DEV_MMCSD0,
+ TISCI_DEV_MMCSD1,
+ TISCI_DEV_GPIO4,
+ TISCI_DEV_UART8,
+ TISCI_DEV_GTC0,
+};
+
+uint32_t gBoardClkModuleMainIDDeinitGroup1[] = {
+ TISCI_DEV_MMCSD0,
+ TISCI_DEV_MMCSD1,
+ TISCI_DEV_GTC0,
+};
+
+uint32_t gBoardClkModuleMainIDGroup2[] = {
+ TISCI_DEV_ATL0,
+ TISCI_DEV_CPSW1,
+ TISCI_DEV_CPT2_AGGR1,
+ TISCI_DEV_CPT2_AGGR5,
+ TISCI_DEV_CPT2_AGGR2,
+ TISCI_DEV_CPT2_AGGR4,
+ TISCI_DEV_CPT2_AGGR3,
+ TISCI_DEV_CPT2_AGGR0,
+ TISCI_DEV_CSI_RX_IF0,
+ TISCI_DEV_CSI_RX_IF1,
+ TISCI_DEV_CSI_TX_IF_V2_0,
+ TISCI_DEV_CSI_TX_IF_V2_1,
+ TISCI_DEV_STM0,
+ TISCI_DEV_DCC0,
+ TISCI_DEV_DCC1,
+ TISCI_DEV_DCC2,
+ TISCI_DEV_DCC3,
+ TISCI_DEV_DCC4,
+ TISCI_DEV_DCC5,
+ TISCI_DEV_DCC6,
+ TISCI_DEV_DCC7,
+ TISCI_DEV_DCC8,
+ TISCI_DEV_DCC9,
+ TISCI_DEV_TIMER0,
+ TISCI_DEV_TIMER1,
+ TISCI_DEV_TIMER2,
+ TISCI_DEV_TIMER3,
+ TISCI_DEV_TIMER4,
+ TISCI_DEV_TIMER5,
+ TISCI_DEV_TIMER6,
+ TISCI_DEV_TIMER7,
+ TISCI_DEV_TIMER8,
+ TISCI_DEV_TIMER9,
+ TISCI_DEV_TIMER10,
+ TISCI_DEV_TIMER11,
+ TISCI_DEV_TIMER12,
+ TISCI_DEV_TIMER13,
+ TISCI_DEV_TIMER14,
+ TISCI_DEV_TIMER15,
+ TISCI_DEV_TIMER16,
+ TISCI_DEV_TIMER17,
+ TISCI_DEV_TIMER18,
+ TISCI_DEV_TIMER19,
+ TISCI_DEV_ESM0,
+ TISCI_DEV_ELM0,
+ TISCI_DEV_GPIO0,
+ TISCI_DEV_GPIO2,
+ TISCI_DEV_GPIO6,
+ TISCI_DEV_MCAN0,
+ TISCI_DEV_MCAN1,
+ TISCI_DEV_MCAN2,
+ TISCI_DEV_MCAN3,
+ TISCI_DEV_MCAN4,
+ TISCI_DEV_MCAN5,
+ TISCI_DEV_MCAN6,
+ TISCI_DEV_MCAN7,
+ TISCI_DEV_MCAN8,
+ TISCI_DEV_MCAN9,
+ TISCI_DEV_MCAN10,
+ TISCI_DEV_MCAN11,
+ TISCI_DEV_MCAN12,
+ TISCI_DEV_MCAN13,
+ TISCI_DEV_MCAN14,
+ TISCI_DEV_MCAN15,
+ TISCI_DEV_MCAN16,
+ TISCI_DEV_MCAN17,
+ TISCI_DEV_MCASP0,
+ TISCI_DEV_MCASP1,
+ TISCI_DEV_MCASP2,
+ TISCI_DEV_MCASP3,
+ TISCI_DEV_MCASP4,
+ TISCI_DEV_I2C0,
+ TISCI_DEV_I2C1,
+ TISCI_DEV_I2C2,
+ TISCI_DEV_I2C3,
+ TISCI_DEV_I2C4,
+ TISCI_DEV_I2C5,
+ TISCI_DEV_I2C6,
+ TISCI_DEV_PCIE1,
+ TISCI_DEV_UART0,
+ TISCI_DEV_UART1,
+ TISCI_DEV_UART2,
+ TISCI_DEV_UART3,
+ TISCI_DEV_UART4,
+ TISCI_DEV_UART5,
+ TISCI_DEV_UART6,
+ TISCI_DEV_UART7,
+ TISCI_DEV_UART9,
+ TISCI_DEV_USB0,
+ TISCI_DEV_SERDES_10G0,
+ TISCI_DEV_GPMC0,
+ TISCI_DEV_LED0,
+ TISCI_DEV_DPHY_RX0,
+ TISCI_DEV_DPHY_RX1,
+ TISCI_DEV_DSS_DSI0,
+ TISCI_DEV_DSS_DSI1,
+ TISCI_DEV_DSS_EDP0,
+ TISCI_DEV_DSS0,
+ TISCI_DEV_DPHY_TX0,
+ TISCI_DEV_DPHY_TX1
+};
+
+/**
+ * \brief Disables module clock
+ *
+ * \return BOARD_SOK - Clock disable successful.
+ * BOARD_FAIL - Clock disable failed.
+ *
+ */
+Board_STATUS Board_moduleClockDisable(uint32_t moduleId)
+{
+ Board_STATUS retVal = BOARD_SOK;
+ int32_t status = CSL_EFAIL;
+ uint32_t moduleState = 0U;
+ uint32_t resetState = 0U;
+ uint32_t contextLossState = 0U;
+
+ /* Get the module state.
+ No need to change the module state if it
+ is already OFF
+ */
+ status = Sciclient_pmGetModuleState(moduleId,
+ &moduleState,
+ &resetState,
+ &contextLossState,
+ SCICLIENT_SERVICE_WAIT_FOREVER);
+ if(moduleState != TISCI_MSG_VALUE_DEVICE_HW_STATE_OFF)
+ {
+ status = Sciclient_pmSetModuleState(moduleId,
+ TISCI_MSG_VALUE_DEVICE_SW_STATE_AUTO_OFF,
+ (TISCI_MSG_FLAG_AOP |
+ TISCI_MSG_FLAG_DEVICE_RESET_ISO),
+ SCICLIENT_SERVICE_WAIT_FOREVER);
+ if (status == CSL_PASS)
+ {
+ status = Sciclient_pmSetModuleRst (moduleId,
+ 0x1U,
+ SCICLIENT_SERVICE_WAIT_FOREVER);
+ if (status != CSL_PASS)
+ {
+ retVal = BOARD_FAIL;
+ }
+ }
+ else
+ {
+ retVal = BOARD_FAIL;
+ }
+ }
+
+ return retVal;
+}
+
+/**
+ * \brief Enables module clock
+ *
+ * \return BOARD_SOK - Clock enable sucessful.
+ * BOARD_FAIL - Clock enable failed.
+ *
+ */
+Board_STATUS Board_moduleClockEnable(uint32_t moduleId)
+{
+ Board_STATUS retVal = BOARD_SOK;
+ int32_t status = CSL_EFAIL;
+ uint32_t moduleState = 0U;
+ uint32_t resetState = 0U;
+ uint32_t contextLossState = 0U;
+
+ /* Get the module state.
+ No need to change the module state if it
+ is already ON
+ */
+ status = Sciclient_pmGetModuleState(moduleId,
+ &moduleState,
+ &resetState,
+ &contextLossState,
+ SCICLIENT_SERVICE_WAIT_FOREVER);
+ if(moduleState == TISCI_MSG_VALUE_DEVICE_HW_STATE_OFF)
+ {
+ if(gBoardInitParams.pscMode == BOARD_PSC_DEVICE_MODE_NONEXCLUSIVE)
+ {
+ status = Sciclient_pmSetModuleState(moduleId,
+ TISCI_MSG_VALUE_DEVICE_SW_STATE_ON,
+ (TISCI_MSG_FLAG_AOP |
+ TISCI_MSG_FLAG_DEVICE_RESET_ISO),
+ SCICLIENT_SERVICE_WAIT_FOREVER);
+ }
+ else
+ {
+ status = Sciclient_pmSetModuleState(moduleId,
+ TISCI_MSG_VALUE_DEVICE_SW_STATE_ON,
+ (TISCI_MSG_FLAG_AOP |
+ TISCI_MSG_FLAG_DEVICE_EXCLUSIVE |
+ TISCI_MSG_FLAG_DEVICE_RESET_ISO),
+ SCICLIENT_SERVICE_WAIT_FOREVER);
+ }
+ if (status == CSL_PASS)
+ {
+ status = Sciclient_pmSetModuleRst (moduleId,
+ 0x0U,
+ SCICLIENT_SERVICE_WAIT_FOREVER);
+ if (status != CSL_PASS)
+ {
+ retVal = BOARD_FAIL;
+ }
+ }
+ else
+ {
+ retVal = BOARD_FAIL;
+ }
+ }
+
+ return retVal;
+}
+
+/**
+ * \brief clock Initialization function
+ *
+ * \return BOARD_SOK - Clock initialization successful.
+ * BOARD_INIT_CLOCK_FAIL - Clock initialization failed.
+ *
+ */
+static Board_STATUS Board_moduleClockInit(uint32_t *clkData, uint32_t size)
+{
+ Board_STATUS status = BOARD_SOK;
+ uint32_t index;
+
+ for(index = 0; index < size; index++)
+ {
+ status = Board_moduleClockEnable(clkData[index]);
+ if(status != BOARD_SOK)
+ {
+ status = BOARD_INIT_CLOCK_FAIL;
+ break;
+ }
+ }
+
+ return status;
+}
+
+/**
+ * \brief Clock de-initialization function
+ *
+ *
+ * \return BOARD_SOK - Clock de-initialization successful.
+ * BOARD_INIT_CLOCK_FAIL - Clock de-initialization failed.
+ *
+ */
+static Board_STATUS Board_moduleClockDeinit(uint32_t *clkData, uint32_t size)
+{
+ Board_STATUS status = BOARD_SOK;
+ uint32_t index;
+
+ for(index = 0; index < size; index++)
+ {
+ status = Board_moduleClockDisable(clkData[index]);
+ if(status != BOARD_SOK)
+ {
+ status = BOARD_INIT_CLOCK_FAIL;
+ break;
+ }
+ }
+
+ return status;
+}
+
+/**
+ * \brief clock Initialization function for MCU domain
+ *
+ * Enables different power domains and peripheral clocks of the MCU.
+ * Some of the power domains and peripherals will be OFF by default.
+ * Enabling the power domains is mandatory before accessing using
+ * board interfaces connected to those peripherals.
+ *
+ * \return BOARD_SOK - Clock initialization sucessful.
+ * BOARD_INIT_CLOCK_FAIL - Clock initialization failed.
+ *
+ */
+Board_STATUS Board_moduleClockInitMcu(void)
+{
+ Board_STATUS status = BOARD_SOK;
+ uint32_t size;
+
+ /* Restoring MCU DMtimer0 FCLK to HFOSC0 (changed by ROM) */
+ HW_WR_REG32((CSL_MCU_CTRL_MMR0_CFG0_BASE + CSL_MCU_CTRL_MMR_CFG0_MCU_TIMER0_CLKSEL), 0);
+
+ if((gBoardInitParams.mcuClkGrp == BOARD_MCU_CLOCK_GROUP_ALL) ||
+ (gBoardInitParams.mcuClkGrp == BOARD_MCU_CLOCK_GROUP1))
+ {
+ size = sizeof(gBoardClkModuleMcuIDInitGroupl) / sizeof(uint32_t);
+ status = Board_moduleClockInit(gBoardClkModuleMcuIDInitGroupl, size);
+ if(status != BOARD_SOK)
+ {
+ return status;
+ }
+ }
+
+ if((gBoardInitParams.mcuClkGrp == BOARD_MCU_CLOCK_GROUP_ALL) ||
+ (gBoardInitParams.mcuClkGrp == BOARD_MCU_CLOCK_GROUP2))
+ {
+ size = sizeof(gBoardClkModuleMcuIDInitGroup2) / sizeof(uint32_t);
+ status = Board_moduleClockInit(gBoardClkModuleMcuIDInitGroup2, size);
+ if(status != BOARD_SOK)
+ {
+ return status;
+ }
+ }
+
+ return status;
+}
+
+/**
+ * \brief clock Initialization function for MAIN domain
+ *
+ * Enables different power domains and peripheral clocks of the SoC.
+ * Some of the power domains and peripherals will be OFF by default.
+ * Enabling the power domains is mandatory before accessing using
+ * board interfaces connected to those peripherals.
+ *
+ * \return BOARD_SOK - Clock initialization successful.
+ * BOARD_INIT_CLOCK_FAIL - Clock initialization failed.
+ *
+ */
+Board_STATUS Board_moduleClockInitMain(void)
+{
+ Board_STATUS status = BOARD_SOK;
+ uint32_t size;
+
+ if((gBoardInitParams.mainClkGrp == BOARD_MAIN_CLOCK_GROUP_ALL) ||
+ (gBoardInitParams.mainClkGrp == BOARD_MAIN_CLOCK_GROUP1))
+ {
+ size = sizeof(gBoardClkModuleMainIDInitGroup1) / sizeof(uint32_t);
+ status = Board_moduleClockInit(gBoardClkModuleMainIDInitGroup1, size);
+ if(status != BOARD_SOK)
+ {
+ return status;
+ }
+ }
+
+ if((gBoardInitParams.mainClkGrp == BOARD_MAIN_CLOCK_GROUP_ALL) ||
+ (gBoardInitParams.mainClkGrp == BOARD_MAIN_CLOCK_GROUP2))
+ {
+ size = sizeof(gBoardClkModuleMainIDGroup2) / sizeof(uint32_t);
+ status = Board_moduleClockInit(gBoardClkModuleMainIDGroup2, size);
+ }
+
+ return status;
+}
+
+/**
+ * \brief clock de-initialization function for MCU domain
+ *
+ * Disables different power domains and peripheral clocks of the SoC.
+ *
+ * \return BOARD_SOK - Clock de-initialization successful.
+ * BOARD_INIT_CLOCK_FAIL - Clock de-initialization failed.
+ *
+ */
+Board_STATUS Board_moduleClockDeinitMcu(void)
+{
+ Board_STATUS status = BOARD_SOK;
+ uint32_t size;
+
+ if((gBoardInitParams.mcuClkGrp == BOARD_MCU_CLOCK_GROUP_ALL) ||
+ (gBoardInitParams.mcuClkGrp == BOARD_MCU_CLOCK_GROUP1))
+ {
+ size = sizeof(gBoardClkModuleMcuIDDeinitGroupl) / sizeof(uint32_t);
+ status = Board_moduleClockDeinit(gBoardClkModuleMcuIDDeinitGroupl, size);
+ if(status != BOARD_SOK)
+ {
+ return status;
+ }
+ }
+
+ if((gBoardInitParams.mcuClkGrp == BOARD_MCU_CLOCK_GROUP_ALL) ||
+ (gBoardInitParams.mcuClkGrp == BOARD_MCU_CLOCK_GROUP2))
+ {
+ size = sizeof(gBoardClkModuleMcuIDInitGroup2) / sizeof(uint32_t);
+ status = Board_moduleClockDeinit(gBoardClkModuleMcuIDInitGroup2, size);
+ if(status != BOARD_SOK)
+ {
+ return status;
+ }
+ }
+
+ return status;
+}
+
+/**
+ * \brief clock de-initialization function for MAIN domain
+ *
+ * Disables different power domains and peripheral clocks of the SoC.
+ *
+ * \return BOARD_SOK - Clock de-initialization successful.
+ * BOARD_INIT_CLOCK_FAIL - Clock de-initialization failed.
+ *
+ */
+Board_STATUS Board_moduleClockDeinitMain(void)
+{
+ Board_STATUS status = BOARD_SOK;
+ uint32_t size;
+
+ if((gBoardInitParams.mainClkGrp == BOARD_MAIN_CLOCK_GROUP_ALL) ||
+ (gBoardInitParams.mainClkGrp == BOARD_MAIN_CLOCK_GROUP1))
+ {
+ size = sizeof(gBoardClkModuleMainIDDeinitGroup1) / sizeof(uint32_t);
+ status = Board_moduleClockDeinit(gBoardClkModuleMainIDDeinitGroup1, size);
+ if(status != BOARD_SOK)
+ {
+ return status;
+ }
+ }
+
+ if((gBoardInitParams.mainClkGrp == BOARD_MAIN_CLOCK_GROUP_ALL) ||
+ (gBoardInitParams.mainClkGrp == BOARD_MAIN_CLOCK_GROUP2))
+ {
+ size = sizeof(gBoardClkModuleMainIDGroup2) / sizeof(uint32_t);
+ status = Board_moduleClockDeinit(gBoardClkModuleMainIDGroup2, size);
+ }
+
+ return status;
+}
diff --git a/packages/ti/board/src/j721s2_evm/board_control.c b/packages/ti/board/src/j721s2_evm/board_control.c
--- /dev/null
@@ -0,0 +1,259 @@
+/******************************************************************************
+ * Copyright (c) 2021 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *****************************************************************************/
+
+/**
+ * \file board_control.c
+ *
+ * \brief Implements multiple board control functions
+ *
+ */
+
+#include "board_control.h"
+
+/**
+ * \brief Configures IO expander pins
+ *
+ * \return Board_SOK in case of success or appropriate error code.
+ *
+ */
+static Board_STATUS Board_setIoExpPinOutput(Board_IoExpCfg_t *cfg)
+{
+ Board_I2cInitCfg_t i2cCfg;
+ Board_STATUS status;
+
+ i2cCfg.i2cInst = cfg->i2cInst;
+ i2cCfg.socDomain = cfg->socDomain;
+ i2cCfg.enableIntr = cfg->enableIntr;
+ Board_setI2cInitConfig(&i2cCfg);
+
+ status = Board_i2cIoExpInit();
+ if(status == BOARD_SOK)
+ {
+ /* Setting the pin direction as output */
+ status = Board_i2cIoExpSetPinDirection(cfg->slaveAddr,
+ cfg->ioExpType,
+ cfg->portNum,
+ cfg->pinNum,
+ PIN_DIRECTION_OUTPUT);
+ BOARD_delay(1000);
+ /* Pulling the hdmi power pin to low */
+ status |= Board_i2cIoExpPinLevelSet(cfg->slaveAddr,
+ cfg->ioExpType,
+ cfg->portNum,
+ cfg->pinNum,
+ cfg->signalLevel);
+ BOARD_delay(1000);
+
+ Board_i2cIoExpDeInit();
+ }
+
+ return status;
+}
+
+/**
+ * \brief Configures IO mux on SoM board
+ *
+ * \param mask [IN] Mask value for the IO expander pins to be configured
+ * \param value [IN] Value to be written to IO expander pins
+ *
+ * \return Board_SOK in case of success or appropriate error code.
+ *
+ */
+static Board_STATUS Board_setSomMux(uint8_t mask,
+ uint8_t value)
+{
+ Board_I2cInitCfg_t i2cCfg;
+ Board_STATUS status;
+ uint8_t ioExpData;
+
+ i2cCfg.i2cInst = BOARD_I2C_IOEXP_SOM_INSTANCE;
+ i2cCfg.socDomain = BOARD_SOC_DOMAIN_MAIN;
+ i2cCfg.enableIntr = false;
+ Board_setI2cInitConfig(&i2cCfg);
+
+ status = Board_i2cIoExpInit();
+ if(status == BOARD_SOK)
+ {
+ /* Setting the port direction as output */
+ status = Board_i2cIoExpSetPortDirection(BOARD_I2C_IOEXP_SOM_ADDR,
+ ONE_PORT_IOEXP,
+ PORTNUM_0,
+ 0);
+ BOARD_delay(1000);
+
+ /* Reading the IO expander current port settings */
+ status |= Board_i2cIoExpReadOutputPort(BOARD_I2C_IOEXP_SOM_ADDR,
+ ONE_PORT_IOEXP,
+ PORTNUM_0,
+ &ioExpData);
+ BOARD_delay(1000);
+
+ ioExpData = (ioExpData & ~(mask)) | value;
+
+ /* Modify the IO expander port settings to enable audio Mux */
+ status |= Board_i2cIoExpWritePort(BOARD_I2C_IOEXP_SOM_ADDR,
+ ONE_PORT_IOEXP,
+ PORTNUM_0,
+ ioExpData);
+
+ BOARD_delay(1000);
+
+ Board_i2cIoExpDeInit();
+ }
+
+ return status;
+}
+
+/**
+ * \brief Configures the mux on SoM board to route port A to Port B1
+ *
+ * \return Board_SOK in case of success or appropriate error code.
+ *
+ */
+static Board_STATUS Board_setSoMMUXPortB1(void)
+{
+ Board_STATUS status;
+
+ status = Board_setSomMux(BOARD_CTRL_CMD_SOM_MUX_PORTB_MASK,
+ BOARD_CTRL_CMD_SOM_MUX_PORTB1_ENABLE);
+
+ return status;
+}
+
+/**
+ * \brief Configures the mux on SoM board to route port A to Port B2
+ *
+ * \return Board_SOK in case of success or appropriate error code.
+ *
+ */
+static Board_STATUS Board_setSoMMUXPortB2(void)
+{
+ Board_STATUS status;
+
+ status = Board_setSomMux(BOARD_CTRL_CMD_SOM_MUX_PORTB_MASK,
+ BOARD_CTRL_CMD_SOM_MUX_PORTB2_ENABLE);
+
+ return status;
+}
+
+/**
+ * \brief Configures the mux on SoM board to route port A to Port B3
+ *
+ * \return Board_SOK in case of success or appropriate error code.
+ *
+ */
+static Board_STATUS Board_setSoMMUXPortB3(void)
+{
+ Board_STATUS status;
+
+ status = Board_setSomMux(BOARD_CTRL_CMD_SOM_MUX_PORTB_MASK,
+ BOARD_CTRL_CMD_SOM_MUX_PORTB3_ENABLE);
+
+ return status;
+}
+
+/**
+ * \brief Configures DSI to EDP bridge enable pin to high
+ *
+ * \return Board_SOK in case of success or appropriate error code.
+ *
+ */
+static Board_STATUS Board_enableDSI2EDPBridge(void)
+{
+ Board_IoExpCfg_t ioExpCfg;
+ Board_STATUS status;
+
+ ioExpCfg.i2cInst = BOARD_I2C_IOEXP_SOM_INSTANCE;
+ ioExpCfg.socDomain = BOARD_SOC_DOMAIN_MAIN;
+ ioExpCfg.slaveAddr = BOARD_I2C_IOEXP_SOM_ADDR;
+ ioExpCfg.enableIntr = false;
+ ioExpCfg.ioExpType = ONE_PORT_IOEXP;
+ ioExpCfg.portNum = PORTNUM_0;
+ ioExpCfg.pinNum = PIN_NUM_5;
+ ioExpCfg.signalLevel = GPIO_SIGNAL_LEVEL_HIGH;
+
+ status = Board_setIoExpPinOutput(&ioExpCfg);
+ if(status != BOARD_SOK)
+ {
+ return status;
+ }
+
+ return status;
+}
+
+/**
+ * \brief Board control function
+ *
+ * \param cmd [IN] Board control command
+ * \param arg [IN] Control command argument.
+ * Changes based on the command
+ *
+ * \return TRUE if the given board is detected else 0.
+ * SoM board will be always connected to the base board.
+ * For SoM boardID return value TRUE indicates dual PMIC
+ * SoM and FALSE indicates alternate PMIC SoM
+ *
+ */
+Board_STATUS Board_control(uint32_t cmd, void *arg)
+{
+ Board_STATUS status;
+
+ switch (cmd)
+ {
+ case BOARD_CTRL_CMD_SET_IO_EXP_PIN_OUT:
+ status = Board_setIoExpPinOutput((Board_IoExpCfg_t *)arg);
+ break;
+
+ case BOARD_CTRL_CMD_SET_SOM_MUX_PORTB1:
+ status = Board_setSoMMUXPortB1();
+ break;
+
+ case BOARD_CTRL_CMD_SET_SOM_MUX_PORTB2:
+ status = Board_setSoMMUXPortB2();
+ break;
+
+ case BOARD_CTRL_CMD_SET_SOM_MUX_PORTB3:
+ status = Board_setSoMMUXPortB3();
+ break;
+
+ case BOARD_CTRL_CMD_ENABLE_DSI2DP_BRIDGE:
+ status = Board_enableDSI2EDPBridge();
+ break;
+
+ default:
+ status = BOARD_INVALID_PARAM;
+ break;
+ }
+
+ return status;
+}
diff --git a/packages/ti/board/src/j721s2_evm/board_ddr.c b/packages/ti/board/src/j721s2_evm/board_ddr.c
--- /dev/null
@@ -0,0 +1,501 @@
+/******************************************************************************
+ * Copyright (c) 2021 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *****************************************************************************/
+#include <string.h>
+#include "board_ddr.h"
+#include "board_ddrRegInit.h"
+
+Board_DdrObject_t gBoardDdrObject[BOARD_DDR_INSTANCE_MAX];
+
+/**
+ * \brief Set DDR PLL clock value
+ *
+ * \return BOARD_SOK in case of success or appropriate error code
+ */
+static Board_STATUS Board_DDRSetPLLClock(uint32_t ddrInstance, uint64_t frequency)
+{
+ Board_STATUS status = BOARD_SOK;
+
+ if(ddrInstance == 0)
+ {
+ status = Board_PLLInit(TISCI_DEV_DDR0,
+ TISCI_DEV_DDR0_DDRSS_DDR_PLL_CLK,
+ frequency);
+ }
+ else
+ {
+ status = Board_PLLInit(TISCI_DEV_DDR1,
+ TISCI_DEV_DDR1_DDRSS_DDR_PLL_CLK,
+ frequency);
+ }
+
+ if(status != BOARD_SOK)
+ {
+ BOARD_DEBUG_LOG("Failed to Set the DDR PLL Clock Frequency\n");
+ }
+
+ return status;
+}
+
+/**
+ * \brief Controls the DDR PLL clock change sequence during inits
+ *
+ * \return None
+ */
+static void Board_DDRChangeFreqAck(uint32_t ddrInstance)
+{
+ uint32_t reqType;
+ uint32_t regVal;
+ volatile uint32_t counter;
+ volatile uint32_t counter2;
+ volatile uint32_t temp = 0;
+
+ temp = temp; /* To suppress compiler warning */
+ BOARD_DEBUG_LOG("--->>> LPDDR4 Initialization is in progress ... <<<---\n");
+
+ for(counter = 0; counter < DDRSS_PLL_FHS_CNT; counter++)
+ {
+ /* wait for freq change request */
+ regVal = HW_RD_REG32((BOARD_DDR_FSP_CLKCHNG_REQ_ADDR + (0x10 * ddrInstance))) & 0x80;
+ BOARD_DEBUG_LOG("Reg Value: %d \n", regVal);
+
+ while(regVal == 0x0)
+ {
+ regVal = HW_RD_REG32((BOARD_DDR_FSP_CLKCHNG_REQ_ADDR + (0x10 * ddrInstance))) & 0x80;
+ BOARD_DEBUG_LOG("Reg Value: %d \n", regVal);
+ }
+
+ reqType = HW_RD_REG32((BOARD_DDR_FSP_CLKCHNG_REQ_ADDR + (0x10 * ddrInstance))) & 0x03;
+ BOARD_DEBUG_LOG("Frequency Change type %d request from Controller \n", reqType);
+
+ if(reqType == 1)
+ {
+ Board_DDRSetPLLClock(ddrInstance, DDRSS_PLL_FREQUENCY_1);
+ }
+ else if(reqType == 2)
+ {
+ Board_DDRSetPLLClock(ddrInstance, DDRSS_PLL_FREQUENCY_2);
+ }
+ else if(reqType == 0)
+ {
+ Board_DDRSetPLLClock(ddrInstance, DDRSS_PLL_FREQUENCY_0);
+ }
+ else
+ {
+ BOARD_DEBUG_LOG("Invalid Request Type\n");
+ }
+
+ counter2 = 0;
+ while(counter2 < 200)
+ {
+ temp = HW_RD_REG32((BOARD_DDR_FSP_CLKCHNG_REQ_ADDR + (0x10 * ddrInstance)));
+ counter2++;
+ }
+
+ HW_WR_REG32((BOARD_DDR_FSP_CLKCHNG_ACK_ADDR + (0x10 * ddrInstance)), 0x1);
+
+ counter2 = 0;
+ while(counter2 < 10)
+ {
+ temp = HW_RD_REG32((BOARD_DDR_FSP_CLKCHNG_REQ_ADDR + (0x10 * ddrInstance)));
+ counter2++;
+ }
+
+ while((HW_RD_REG32((BOARD_DDR_FSP_CLKCHNG_REQ_ADDR + (0x10 * ddrInstance))) & 0x80) == 0x80);
+
+ counter2 = 0;
+ while(counter2 < 10)
+ {
+ temp = HW_RD_REG32((BOARD_DDR_FSP_CLKCHNG_REQ_ADDR + (0x10 * ddrInstance)));
+ counter2++;
+ }
+
+ HW_WR_REG32((BOARD_DDR_FSP_CLKCHNG_ACK_ADDR + (0x10 * ddrInstance)), 0x0);
+
+ counter2 = 0;
+ while(counter2 < 10)
+ {
+ temp= HW_RD_REG32((BOARD_DDR_FSP_CLKCHNG_REQ_ADDR + (0x10 * ddrInstance)));
+ counter2++;
+ }
+ }
+
+ BOARD_DEBUG_LOG("--->>> Frequency Change request handshake is completed... <<<---\n");
+}
+
+/**
+ * \brief Function to handle the configuration requests from DDR lib
+ *
+ * \return None
+ */
+static void Board_DDRInfoHandler(const LPDDR4_PrivateData *pd, LPDDR4_InfoType infotype)
+{
+ Board_DdrHandle ddrHandle;
+
+ if (infotype == LPDDR4_DRV_SOC_PLL_UPDATE)
+ {
+ ddrHandle = (Board_DdrHandle)pd->ddr_instance;
+ Board_DDRChangeFreqAck(ddrHandle->ddrInst);
+ }
+}
+
+/**
+ * \brief DDR probe function
+ *
+ * \return BOARD_SOK in case of success or appropriate error code
+ */
+static Board_STATUS Board_DDRProbe(Board_DdrHandle ddrHandle)
+{
+ uint32_t status = 0U;
+ uint16_t configsize = 0U;
+
+ status = LPDDR4_Probe(&ddrHandle->boardDdrCfg, &configsize);
+
+ if ((status != 0) || (configsize != sizeof(LPDDR4_PrivateData)) ||
+ (configsize > BOARD_DDR_SRAM_MAX))
+ {
+ BOARD_DEBUG_LOG("Board_DDRProbe: FAIL\n");
+ return BOARD_FAIL;
+ }
+ else
+ {
+ BOARD_DEBUG_LOG("Board_DDRProbe: PASS\n");
+ }
+
+ return BOARD_SOK;
+}
+
+/**
+ * \brief DDR driver initialization function
+ *
+ * \return BOARD_SOK in case of success or appropriate error code
+ */
+static Board_STATUS Board_DDRInitDrv(Board_DdrHandle ddrHandle)
+{
+ uint32_t status = 0U;
+ LPDDR4_Config *pBoardDdrCfg;
+ LPDDR4_PrivateData *pBoardDdrPd;
+
+ if(ddrHandle == NULL)
+ {
+ BOARD_DEBUG_LOG("Board_DDRInitDrv: FAIL\n");
+ return BOARD_FAIL;
+ }
+
+ pBoardDdrCfg = &ddrHandle->boardDdrCfg;
+ pBoardDdrPd = &ddrHandle->boardDdrPd;
+
+ if ((sizeof(ddrHandle->boardDdrPd) != sizeof(LPDDR4_PrivateData)) ||
+ (sizeof(ddrHandle->boardDdrPd) > BOARD_DDR_SRAM_MAX))
+ {
+ BOARD_DEBUG_LOG("Board_DDRInitDrv: FAIL\n");
+ return BOARD_FAIL;
+ }
+
+ pBoardDdrCfg->ctlBase = (struct LPDDR4_CtlRegs_s *)ddrHandle->ddrCtlAddr;
+ pBoardDdrCfg->infoHandler = (LPDDR4_InfoCallback) Board_DDRInfoHandler;
+
+ status = LPDDR4_Init(pBoardDdrPd, pBoardDdrCfg);
+
+ if ((status > 0U) ||
+ (pBoardDdrPd->ctlBase != (struct LPDDR4_CtlRegs_s *)pBoardDdrCfg->ctlBase) ||
+ (pBoardDdrPd->ctlInterruptHandler != pBoardDdrCfg->ctlInterruptHandler) ||
+ (pBoardDdrPd->phyIndepInterruptHandler != pBoardDdrCfg->phyIndepInterruptHandler))
+ {
+ BOARD_DEBUG_LOG("Board_DDRInitDrv: FAIL\n");
+ return BOARD_FAIL;
+ }
+ else
+ {
+ BOARD_DEBUG_LOG("Board_DDRInitDrv: PASS\n");
+ }
+
+ return BOARD_SOK;
+}
+
+/**
+ * \brief DDR registers initialization function
+ *
+ * \return BOARD_SOK in case of success or appropriate error code
+ */
+static Board_STATUS Board_DDRHWRegInit(Board_DdrHandle ddrHandle)
+{
+ uint32_t status = 0U;
+
+ status = LPDDR4_WriteCtlConfig(&ddrHandle->boardDdrPd,
+ ddrHandle->ddrCtlReg,
+ DDRSS_ctlRegNum,
+ (uint16_t)DDRSS_CTL_REG_INIT_COUNT);
+ if (!status)
+ {
+ status = LPDDR4_WritePhyIndepConfig(&ddrHandle->boardDdrPd,
+ ddrHandle->ddrPhyIndepReg,
+ DDRSS_phyIndepRegNum,
+ (uint16_t)DDRSS_PHY_INDEP_REG_INIT_COUNT);
+ }
+
+ if (!status)
+ {
+ status = LPDDR4_WritePhyConfig(&ddrHandle->boardDdrPd,
+ ddrHandle->ddrPhyReg,
+ DDRSS_phyRegNum,
+ (uint16_t)DDRSS_PHY_REG_INIT_COUNT);
+ }
+
+ if (status)
+ {
+ BOARD_DEBUG_LOG(" ERROR: Board_DDRHWRegInit failed!!\n");
+ return BOARD_FAIL;
+ }
+
+ return BOARD_SOK;
+}
+
+/**
+ * \brief DDR start function
+ *
+ * \return BOARD_SOK in case of success or appropriate error code
+ */
+static Board_STATUS Board_DDRStart(Board_DdrHandle ddrHandle)
+{
+ uint32_t status = 0U;
+ uint32_t regval = 0U;
+ uint32_t offset = 0U;
+ LPDDR4_PrivateData *pBoardDdrPd;
+
+ if(ddrHandle == NULL)
+ {
+ BOARD_DEBUG_LOG("Board_DDRStart: FAIL\n");
+ return BOARD_FAIL;
+ }
+
+ pBoardDdrPd = &ddrHandle->boardDdrPd;
+ offset = BOARD_DDR_CTL_REG_OFFSET;
+
+ status = LPDDR4_ReadReg(pBoardDdrPd, LPDDR4_CTL_REGS, offset, ®val);
+ if ((status > 0U) || ((regval & 0x1U) != 0U))
+ {
+ BOARD_DEBUG_LOG("Board_DDRStart: FAIL\n");
+ return BOARD_FAIL;
+ }
+
+ status = LPDDR4_Start(pBoardDdrPd);
+ if (status > 0U)
+ {
+ BOARD_DEBUG_LOG("Board_DDRStart: FAIL\n");
+ return BOARD_FAIL;
+ }
+
+ status = LPDDR4_ReadReg(pBoardDdrPd, LPDDR4_CTL_REGS, offset, ®val);
+ if ((status > 0U) || ((regval & 0x1U) != 1U))
+ {
+ BOARD_DEBUG_LOG("Board_DDRStart: FAIL\n");
+ return BOARD_FAIL;
+ }
+ else
+ {
+ BOARD_DEBUG_LOG("LPDDR4_Start: PASS\n");
+ }
+
+ return BOARD_SOK;
+}
+
+/**
+ * \brief DDR4 Configuration function
+ *
+ * Invokes DDR CSL APIs to configure the DDR timing parameters and ECC configuration
+ *
+ * \return BOARD_SOK in case of success or appropriate error code
+ *
+ */
+static Board_STATUS Board_DDRConfig(Board_DdrHandle ddrHandle, Bool eccEnable)
+{
+ Board_STATUS status = BOARD_SOK;
+
+ status = Board_DDRProbe(ddrHandle);
+ if(status != BOARD_SOK)
+ {
+ return status;
+ }
+
+ status = Board_DDRInitDrv(ddrHandle);
+ if(status != BOARD_SOK)
+ {
+ return status;
+ }
+
+ status = Board_DDRHWRegInit(ddrHandle);
+ if(status != BOARD_SOK)
+ {
+ return status;
+ }
+
+ status = Board_DDRStart(ddrHandle);
+ if(status != BOARD_SOK)
+ {
+ return status;
+ }
+
+ return status;
+}
+
+/**
+ * \brief Opens and initializes a DDR instances
+ *
+ * \return BOARD_SOK in case of success or appropriate error code
+ *
+ */
+static Board_DdrHandle Board_DDROpen(uint32_t ddrInstance)
+{
+ Board_DdrHandle ddrHandle = NULL;
+
+ if(ddrInstance < BOARD_DDR_INSTANCE_MAX)
+ {
+ if(gBoardDdrObject[ddrInstance].isOpen == FALSE)
+ {
+ ddrHandle = &gBoardDdrObject[ddrInstance];
+ ddrHandle->isOpen = TRUE;
+ ddrHandle->boardDdrPd.ddr_instance = ddrHandle;
+ ddrHandle->ddrInst = ddrInstance;
+
+ switch (ddrInstance)
+ {
+ case BOARD_DDR_INSTANCE_0:
+ ddrHandle->ddrCtlAddr = (void *)BOARD_DDR0_CTL_CFG_BASE;
+ ddrHandle->ddrCtlReg = DDRSS0_ctlReg;
+ ddrHandle->ddrPhyIndepReg = DDRSS0_phyIndepReg;
+ ddrHandle->ddrPhyReg = DDRSS0_phyReg;
+ break;
+ case BOARD_DDR_INSTANCE_1:
+ ddrHandle->ddrCtlAddr = (void *)BOARD_DDR1_CTL_CFG_BASE;
+ ddrHandle->ddrCtlReg = DDRSS1_ctlReg;
+ ddrHandle->ddrPhyIndepReg = DDRSS1_phyIndepReg;
+ ddrHandle->ddrPhyReg = DDRSS1_phyReg;
+ break;
+ }
+ }
+ }
+
+ return ddrHandle;
+}
+
+/**
+ * \brief Closes DDR instances
+ *
+ * \return BOARD_SOK in case of success or appropriate error code
+ *
+ */
+static Board_STATUS Board_DDRClose(Board_DdrHandle ddrHandle)
+{
+ Board_STATUS status = BOARD_FAIL;
+
+ if(ddrHandle != NULL)
+ {
+ ddrHandle->isOpen = FALSE;
+ status = BOARD_SOK;
+ }
+
+ return status;
+}
+
+/**
+ * \brief DDR4 Initialization function
+ *
+ * \return BOARD_SOK in case of success or appropriate error code
+ *
+ */
+Board_STATUS Board_DDRInit(Bool eccEnable)
+{
+ Board_STATUS status = BOARD_SOK;
+ uint32_t multiDdrCfgVal0;
+ uint32_t multiDdrCfgVal1;
+ uint32_t ddrInstance;
+ Board_DdrHandle ddrHandle;
+
+ /* Unlock the PLL register access for DDR clock bypass */
+ HW_WR_REG32(BOARD_PLL12_LOCK0, KICK0_UNLOCK);
+ HW_WR_REG32(BOARD_PLL12_LOCK1, KICK1_UNLOCK);
+
+ HW_WR_REG32(BOARD_DDR_LOCK0, KICK0_UNLOCK);
+ HW_WR_REG32(BOARD_DDR_LOCK1, KICK1_UNLOCK);
+
+ multiDdrCfgVal0 = (MULTI_DDR_CFG_INTRLV_GRAN << 24) |
+ (MULTI_DDR_CFG_INTRLV_SIZE << 16) |
+ (BOARD_MULTI_DDR_CFG_INTRLV_HEARTBEAT << 0);
+
+ multiDdrCfgVal1 = (MULTI_DDR_CFG_ECC_ENABLE << 16) |
+ (MULTI_DDR_CFG_HYBRID_SELECT << 8) |
+ (MULTI_DDR_CFG_EMIFS_ACTIVE << 0);
+
+ HW_WR_REG32(BOARD_MULTI_DDR_CFG0, multiDdrCfgVal0);
+ HW_WR_REG32(BOARD_MULTI_DDR_CFG1, multiDdrCfgVal1);
+ HW_WR_REG32(BOARD_DDR_CFG_LOAD, BOARD_DDR_CFG_LOAD_VALUE);
+
+ /* Wait until DDR config load is complete */
+ while(HW_RD_REG32(BOARD_DDR_CFG_LOAD & 0x1) == 0x0);
+
+ /* Partition5 lockkey0 */
+ HW_WR_REG32(BOARD_CTRL_MMR_PART5_LOCK0, KICK0_UNLOCK);
+ /* Partition5 lockkey1 */
+ HW_WR_REG32(BOARD_CTRL_MMR_PART5_LOCK1, KICK1_UNLOCK);
+
+ for(ddrInstance = 0; ddrInstance < BOARD_DDR_INSTANCE_MAX; ddrInstance++)
+ {
+ /* Set to Boot Frequency(F0) while configuring the DDR */
+ Board_DDRSetPLLClock(ddrInstance, DDRSS_PLL_FREQUENCY_0);
+ ddrHandle = Board_DDROpen(ddrInstance);
+ if(ddrHandle == NULL)
+ {
+ BOARD_DEBUG_LOG("Board_DDROpen: FAIL\n");
+ return BOARD_FAIL;
+ }
+
+ status = Board_DDRConfig(ddrHandle, 0);
+ if(status != BOARD_SOK)
+ {
+ BOARD_DEBUG_LOG("Board_DDRConfig: FAIL\n");
+ return status;
+ }
+
+ Board_DDRClose(ddrHandle);
+ }
+
+ /* Lock the register access */
+ HW_WR_REG32(BOARD_PLL12_LOCK0, KICK_LOCK);
+ HW_WR_REG32(BOARD_PLL12_LOCK1, KICK_LOCK);
+ HW_WR_REG32(BOARD_DDR_LOCK0, KICK_LOCK);
+ HW_WR_REG32(BOARD_DDR_LOCK1, KICK_LOCK);
+ HW_WR_REG32(BOARD_CTRL_MMR_PART5_LOCK0, KICK_LOCK);
+ HW_WR_REG32(BOARD_CTRL_MMR_PART5_LOCK1, KICK_LOCK);
+
+ return status;
+}
diff --git a/packages/ti/board/src/j721s2_evm/board_ethernet_config.c b/packages/ti/board/src/j721s2_evm/board_ethernet_config.c
--- /dev/null
@@ -0,0 +1,473 @@
+/******************************************************************************
+ * Copyright (c) 2021 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *****************************************************************************/
+
+/**
+ * \file board_ethernet_config.c
+ *
+ * \brief
+ * This file contains the boards specific Ethernet PHY configurations.
+ *
+ */
+
+#include "board_ethernet_config.h"
+#include "board_internal.h"
+#include <ti/csl/soc.h>
+#include <ti/csl/cslr_mdio.h>
+
+/**
+ * \brief Function to initialize MDIO
+ *
+ * \param baseAddr [IN] MDIO base address
+ *
+ * \return uint32_t
+ TRUE Read is successful.
+ * FALSE Read is not acknowledged properly.
+ */
+static void Board_mdioInit(uint32_t baseAddr)
+{
+ HW_WR_REG32((baseAddr + BOARD_MDIO_CTRL_REG_OFFSET),
+ (CSL_FMKT(MDIO_CONTROL_REG_ENABLE, YES) |
+ CSL_FMK(MDIO_CONTROL_REG_CLKDIV,
+ BOARD_MDIO_CLK_DIV_CFG)));
+}
+
+/**
+ * \brief PHY register write function
+ *
+ * This function is used to writes a PHY register using MDIO.
+ *
+ * \param baseAddr [IN] MDIO base address
+ * phyAddr [IN] PHY Address
+ * regAddr [IN] Register offset to be written
+ * data [IN] Value to be written
+ *
+ */
+static void Board_ethPhyRegWrite(uint32_t baseAddr, uint32_t phyAddr,
+ uint32_t regAddr, uint16_t data)
+{
+ uint32_t regVal = 0U;
+
+ /* Wait till transaction completion if any */
+ while(HW_RD_FIELD32(baseAddr + CSL_MDIO_USER_GROUP_USER_ACCESS_REG(0U),
+ CSL_MDIO_USER_GROUP_USER_ACCESS_REG_GO) == 1)
+ {}
+
+ HW_SET_FIELD(regVal, CSL_MDIO_USER_GROUP_USER_ACCESS_REG_GO, 1);
+ HW_SET_FIELD(regVal, CSL_MDIO_USER_GROUP_USER_ACCESS_REG_WRITE, 1);
+ HW_SET_FIELD(regVal, CSL_MDIO_USER_GROUP_USER_ACCESS_REG_PHYADR, phyAddr);
+ HW_SET_FIELD(regVal, CSL_MDIO_USER_GROUP_USER_ACCESS_REG_REGADR, regAddr);
+ HW_SET_FIELD(regVal, CSL_MDIO_USER_GROUP_USER_ACCESS_REG_DATA, data);
+ HW_WR_REG32(baseAddr + CSL_MDIO_USER_GROUP_USER_ACCESS_REG(0U), regVal);
+
+ /* wait for command completion */
+ while(HW_RD_FIELD32(baseAddr + CSL_MDIO_USER_GROUP_USER_ACCESS_REG(0U),
+ CSL_MDIO_USER_GROUP_USER_ACCESS_REG_GO) == 1)
+ {}
+}
+
+/**
+ * \brief PHY register read function
+ *
+ * This function is used to Read a PHY register using MDIO.
+ *
+ * \param baseAddr [IN] MDIO base address
+ * phyAddr [IN] PHY Address
+ * regAddr [IN] Register offset to be written
+ * regData [OUT] Pointer where the read value shall be written
+ *
+ * \return uint32_t
+ TRUE Read is successful.
+ * FALSE Read is not acknowledged properly.
+ */
+static uint32_t BoardDiag_ethPhyRegRead(uint32_t baseAddr, uint32_t phyAddr,
+ uint32_t regAddr, uint16_t *regData)
+{
+ uint32_t regVal = 0U;
+ uint32_t retVal = 0U;
+
+ /* Wait till transaction completion if any */
+ while(HW_RD_FIELD32(baseAddr + CSL_MDIO_USER_GROUP_USER_ACCESS_REG(0U),
+ CSL_MDIO_USER_GROUP_USER_ACCESS_REG_GO) == 1)
+ {}
+ HW_SET_FIELD(regVal, CSL_MDIO_USER_GROUP_USER_ACCESS_REG_GO,1);
+ HW_SET_FIELD(regVal, CSL_MDIO_USER_GROUP_USER_ACCESS_REG_WRITE, 0);
+ HW_SET_FIELD(regVal, CSL_MDIO_USER_GROUP_USER_ACCESS_REG_PHYADR, phyAddr);
+ HW_SET_FIELD(regVal, CSL_MDIO_USER_GROUP_USER_ACCESS_REG_REGADR, regAddr);
+ HW_WR_REG32(baseAddr + CSL_MDIO_USER_GROUP_USER_ACCESS_REG(0U), regVal);
+
+ /* wait for command completion */
+ while(HW_RD_FIELD32(baseAddr + CSL_MDIO_USER_GROUP_USER_ACCESS_REG(0U),
+ CSL_MDIO_USER_GROUP_USER_ACCESS_REG_GO) == 1)
+ {}
+
+ /* Store the data if the read is acknowledged */
+ if(HW_RD_FIELD32(baseAddr + CSL_MDIO_USER_GROUP_USER_ACCESS_REG(0U),
+ CSL_MDIO_USER_GROUP_USER_ACCESS_REG_ACK) == 1)
+ {
+ *regData = (uint16_t)(HW_RD_FIELD32(baseAddr + \
+ CSL_MDIO_USER_GROUP_USER_ACCESS_REG(0U),
+ CSL_MDIO_USER_GROUP_USER_ACCESS_REG_DATA));
+ retVal = (uint32_t)TRUE;
+ }
+ else
+ {
+ retVal = (uint32_t)FALSE;
+ }
+
+ return(retVal);
+}
+
+/**
+ * \brief Function to write extended address registers of Ethernet PHY
+ *
+ * \param baseAddr [IN] MDIO base address
+ * phyAddr [IN] Ethernet PHY address
+ * regNum [IN] PHY Register address
+ * pData [OUT] Values read from register
+ *
+ */
+static void Board_ethPhyExtendedRegRead (uint32_t baseAddr,
+ uint32_t phyAddr,
+ uint32_t regNum,
+ uint16_t *pData)
+{
+ Board_ethPhyRegWrite(baseAddr, phyAddr,
+ BOARD_ETHPHY_REGCR_REG_ADDR,
+ BOARD_ETHPHY_REGCR_ADDR_EN);
+ Board_ethPhyRegWrite(baseAddr, phyAddr,
+ BOARD_ETHPHY_ADDAR_REG_ADDR, regNum);
+ Board_ethPhyRegWrite(baseAddr, phyAddr,
+ BOARD_ETHPHY_REGCR_REG_ADDR,
+ BOARD_ETHPHY_REGCR_DATA_EN);
+ BoardDiag_ethPhyRegRead(baseAddr, phyAddr,
+ BOARD_ETHPHY_ADDAR_REG_ADDR, pData);
+}
+
+/**
+ * \brief Function to write extended address registers of Ethernet PHY
+ *
+ * \param baseAddr [IN] MDIO base address
+ * \param phyAddr [IN] Ethernet PHY address
+ * \param regNum [IN] PHY Register address
+ * \param regVal [IN] Register value to be written
+ *
+ * \return none
+ */
+static void Board_ethPhyExtendedRegWrite(uint32_t baseAddr,
+ uint32_t phyAddr,
+ uint32_t regNum,
+ uint16_t regVal)
+{
+ Board_ethPhyRegWrite(baseAddr, phyAddr,
+ BOARD_ETHPHY_REGCR_REG_ADDR,
+ BOARD_ETHPHY_REGCR_ADDR_EN);
+ Board_ethPhyRegWrite(baseAddr, phyAddr,
+ BOARD_ETHPHY_ADDAR_REG_ADDR, regNum);
+ Board_ethPhyRegWrite(baseAddr, phyAddr,
+ BOARD_ETHPHY_REGCR_REG_ADDR,
+ BOARD_ETHPHY_REGCR_DATA_EN);
+ Board_ethPhyRegWrite(baseAddr, phyAddr,
+ BOARD_ETHPHY_ADDAR_REG_ADDR, regVal);
+}
+
+/**
+ * \brief Board specific configurations for CPSW2G Main Domain Ethernet PHYs
+ *
+ * This function takes care of configuring the internal delays for CPSW2G Main Domain
+ * Ethernet PHYs
+ *
+ * \return BOARD_SOK in case of success or appropriate error code
+ */
+Board_STATUS Board_cpsw2gMainEthPhyConfig(void)
+{
+ uint32_t baseAddr;
+ uint8_t phyAddr;
+ uint16_t regData = 0;
+ Board_STATUS status = BOARD_SOK;
+
+ baseAddr = (CSL_CPSW1_NUSS_BASE + 0x0F00);
+ phyAddr = BOARD_MAIN_EMAC_PHY_ADDR;
+
+ Board_mdioInit(baseAddr);
+
+ /* Enable the PHY delay configurations */
+ Board_ethPhyExtendedRegWrite(baseAddr, phyAddr,
+ BOARD_ETHPHY_RGMIICTL_REG_ADDR,
+ BOARD_ETHPHY_DELAY_CTRL);
+
+ /* Setting delay */
+ Board_ethPhyExtendedRegWrite(baseAddr, phyAddr,
+ BOARD_ETHPHY_RGMIIDCTL_REG_ADDR,
+ BOARD_ETHPHY_CPSW2G_MAIN_DELAY);
+
+ /*Setting IO impedance to 35ohms */
+ Board_ethPhyExtendedRegWrite(baseAddr, phyAddr,
+ BOARD_ETHPHY_GPIO_MUX_CFG_REG_ADDR,
+ BOARD_ETHPHY_IO_IMPEDANCE);
+
+ /* Enable PHY speed LED functionality */
+ Board_ethPhyExtendedRegRead(baseAddr, phyAddr,
+ BOARD_ETHPHY_GPIO_MUX_CTRL2_REG_ADDR,
+ ®Data);
+ regData = (regData & ~(BOARD_ETHPHY_GPIO_MUX_CTRL2_REG_MASK)) | 0x6;
+ Board_ethPhyExtendedRegWrite(baseAddr, phyAddr,
+ BOARD_ETHPHY_GPIO_MUX_CTRL2_REG_ADDR,
+ regData);
+
+ regData = 0;
+ BoardDiag_ethPhyRegRead(baseAddr, phyAddr,
+ BOARD_ETHPHY_LEDCR1_REG_ADDR, ®Data);
+ regData = (regData & ~(BOARD_ETHPHY_LEDCR1_REG_MASK)) |
+ BOARD_ETHPHY_LEDCR1_REG_CFG;
+ Board_ethPhyRegWrite(baseAddr, phyAddr,
+ BOARD_ETHPHY_LEDCR1_REG_ADDR, regData);
+
+ /* When the Phy is strapped to enable Fast Link Drop (FLD) feature,
+ * the detect threshold value becomes 0x2 in bit 2:0 instead of 0x1
+ * in the FLD_THRESH (0x2e) register as in non strapped case.
+ * This causes the phy link to be unstable.
+ * As a workaround, write a value of 0x1 in this bit field if
+ * bit 10 of STRAP_STS2 (0x6f) register is set (enable FLD).
+ */
+ regData = 0;
+ Board_ethPhyExtendedRegRead(baseAddr, phyAddr,
+ BOARD_ETHPHY_STRAP_STS2_REG_ADDR,
+ ®Data);
+ if (regData & BOARD_ETHPHY_STRAP_FLD_MASK)
+ {
+ regData = 0;
+ Board_ethPhyExtendedRegRead(baseAddr, phyAddr,
+ BOARD_ETHPHY_FLD_THRESH_REG_ADDR,
+ ®Data);
+ if (regData == BOARD_ETHPHY_STRAP_FLD_THS_CHECK_FLAG)
+ {
+ regData &= ~0x7;
+ Board_ethPhyExtendedRegWrite(baseAddr, phyAddr,
+ BOARD_ETHPHY_FLD_THRESH_REG_ADDR,
+ (regData | 0x1));
+ }
+ }
+
+ return status;
+}
+
+/**
+ * \brief Board specific configurations for CPSW2G Ethernet PHY
+ *
+ * This function takes care of configuring the internal delays for MCU gigabit
+ * Ethernet PHY
+ *
+ * \return BOARD_SOK in case of success or appropriate error code
+ */
+Board_STATUS Board_cpsw2gEthPhyConfig(void)
+{
+ uint32_t baseAddr;
+ uint16_t regData = 0;
+
+ baseAddr = (CSL_MCU_CPSW0_NUSS_BASE + 0x0F00);
+
+ Board_mdioInit(baseAddr);
+
+ /* Enable PHY speed LED functionality */
+ Board_ethPhyExtendedRegRead(baseAddr, BOARD_MCU_EMAC_PHY_ADDR,
+ BOARD_ETHPHY_GPIO_MUX_CTRL2_REG_ADDR,
+ ®Data);
+ regData = (regData & ~(BOARD_ETHPHY_GPIO_MUX_CTRL2_REG_MASK)) |
+ BOARD_ETHPHY_GPIO_MUX_CTRL2_REG_CFG;
+ Board_ethPhyExtendedRegWrite(baseAddr, BOARD_MCU_EMAC_PHY_ADDR,
+ BOARD_ETHPHY_GPIO_MUX_CTRL2_REG_ADDR,
+ regData);
+
+ regData = 0;
+ BoardDiag_ethPhyRegRead(baseAddr, BOARD_MCU_EMAC_PHY_ADDR,
+ BOARD_ETHPHY_LEDCR1_REG_ADDR, ®Data);
+ regData = (regData & ~(BOARD_ETHPHY_LEDCR1_REG_MASK)) |
+ BOARD_ETHPHY_LEDCR1_REG_CFG;
+ Board_ethPhyRegWrite(baseAddr, BOARD_MCU_EMAC_PHY_ADDR,
+ BOARD_ETHPHY_LEDCR1_REG_ADDR, regData);
+
+ /* When the Phy is strapped to enable Fast Link Drop (FLD) feature,
+ * the detect threshold value becomes 0x2 in bit 2:0 instead of 0x1
+ * in the FLD_THRESH (0x2e) register as in non strapped case.
+ * This causes the phy link to be unstable.
+ * As a workaround, write a value of 0x1 in this bit field if
+ * bit 10 of STRAP_STS2 (0x6f) register is set (enable FLD).
+ */
+ regData = 0;
+ Board_ethPhyExtendedRegRead(baseAddr, BOARD_MCU_EMAC_PHY_ADDR,
+ BOARD_ETHPHY_STRAP_STS2_REG_ADDR,
+ ®Data);
+ if (regData & BOARD_ETHPHY_STRAP_FLD_MASK)
+ {
+ regData = 0;
+ Board_ethPhyExtendedRegRead(baseAddr, BOARD_MCU_EMAC_PHY_ADDR,
+ BOARD_ETHPHY_FLD_THRESH_REG_ADDR,
+ ®Data);
+ if (regData == BOARD_ETHPHY_STRAP_FLD_THS_CHECK_FLAG)
+ {
+ regData &= ~0x7;
+ Board_ethPhyExtendedRegWrite(baseAddr, BOARD_MCU_EMAC_PHY_ADDR,
+ BOARD_ETHPHY_FLD_THRESH_REG_ADDR,
+ (regData | 0x1));
+ }
+ }
+
+ /* Enabling the TX and RX delay */
+ Board_ethPhyExtendedRegRead(baseAddr, BOARD_MCU_EMAC_PHY_ADDR,
+ BOARD_ETHPHY_RGMIICTL_REG_ADDR, ®Data);
+ regData = regData | 0x3;
+ Board_ethPhyExtendedRegWrite(baseAddr, BOARD_MCU_EMAC_PHY_ADDR,
+ BOARD_ETHPHY_RGMIICTL_REG_ADDR, regData);
+
+ /* Setting delay */
+ Board_ethPhyExtendedRegWrite(baseAddr, BOARD_MCU_EMAC_PHY_ADDR,
+ BOARD_ETHPHY_RGMIIDCTL_REG_ADDR,
+ BOARD_ETHPHY_CPSW2G_DELAY);
+
+ return BOARD_SOK;
+
+}
+
+
+/**
+ * \brief Configures the CPSW2G Main Domain Subsytem for RGMII and RMII mode
+ *
+ * \param mode [IN] Mode selection for the specified port number
+ * 000 - GMII
+ * 001 - RMII
+ * 010 - RGMII
+ * 011 - SGMII
+ * 100 - QSGMII
+ *
+ * \return BOARD_SOK in case of success or appropriate error code
+ */
+Board_STATUS Board_cpsw2gMainEthConfig(uint8_t mode)
+{
+ uint32_t status;
+ uintptr_t modeSel;
+ uint32_t regData;
+
+ Board_unlockMMR();
+
+ modeSel = CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_CPSW2_ENET1_CTRL;
+ regData = CSL_REG32_RD(modeSel);
+ regData = mode;
+ if (RGMII == mode)
+ {
+ regData |= (RGMII_ID_DISABLE_MASK);
+ }
+ CSL_REG32_WR(modeSel , regData);
+ status = CSL_REG32_RD(modeSel);
+ if (status != regData)
+ {
+ return BOARD_FAIL;
+ }
+ return BOARD_SOK;
+}
+
+/**
+ * \brief Configures the CPSW2G Subsytem for RGMII mode
+ *
+ * \param mode [IN] Mode selection for the specified port number
+ * 00 - GMII
+ * 01 - RMII
+ * 10 - RGMII
+ * 11 - SGMII
+ *
+ * \return BOARD_SOK in case of success or appropriate error code
+ */
+Board_STATUS Board_cpsw2gMacModeConfig(uint8_t mode)
+{
+ uint32_t status;
+ uintptr_t ethModeCtrl;
+ uint32_t regData;
+
+ ethModeCtrl = CSL_MCU_CTRL_MMR0_CFG0_BASE + CSL_MCU_CTRL_MMR_CFG0_MCU_ENET_CTRL;
+ regData = CSL_REG32_RD(ethModeCtrl);
+ regData = mode;
+ if (RGMII == mode)
+ {
+ regData |= (RGMII_ID_DISABLE_MASK);
+ }
+
+ CSL_REG32_WR(ethModeCtrl , regData);
+ status = CSL_REG32_RD(ethModeCtrl);
+ if (status != regData)
+ {
+ return BOARD_FAIL;
+ }
+
+ return BOARD_SOK;
+}
+
+/**
+ * \brief Board specific configurations for CPSW2G Ethernet ports
+ *
+ * This function used to configures CPSW2G Ethernet controllers with the respective modes
+ *
+ * \return BOARD_SOK in case of success or appropriate error code
+ */
+Board_STATUS Board_ethConfigCpsw2g(void)
+{
+ Board_STATUS status = BOARD_SOK;
+
+ Board_unlockMMR();
+
+ /* Configures the MCU Ethernet */
+ status = Board_cpsw2gMacModeConfig(RGMII);
+ if(status != BOARD_SOK)
+ {
+ return BOARD_FAIL;
+ }
+
+ return BOARD_SOK;
+}
+
+/**
+ * \brief Board specific configurations for CPSW2G MAIN Domain Ethernet ports
+ *
+ * This function used to configures CPSW2G MAIN Domain Ethernet controllers with the respective modes
+ *
+ * \return BOARD_SOK in case of success or appropriate error code
+ */
+Board_STATUS Board_ethConfigCpsw2gMain(void)
+{
+ Board_STATUS status = BOARD_SOK;
+ /* Configures the CPSW2G Main Domain RGMII ports */
+ status = Board_cpsw2gMainEthConfig(RGMII);
+ if(status != BOARD_SOK)
+ {
+ return BOARD_FAIL;
+ }
+ return BOARD_SOK;
+}
diff --git a/packages/ti/board/src/j721s2_evm/board_i2c_io_exp.c b/packages/ti/board/src/j721s2_evm/board_i2c_io_exp.c
--- /dev/null
@@ -0,0 +1,779 @@
+/******************************************************************************
+ * Copyright (c) 2018 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *****************************************************************************/
+
+/**
+ * \file board_i2c_io_exp.c
+ *
+ * \brief This file contains the API's for accessing the i2c IO Expander.
+ *
+ */
+
+#include "board_i2c_io_exp.h"
+
+I2C_Handle gIoExpI2cHandle = NULL;
+extern Board_I2cInitCfg_t gBoardI2cInitCfg;
+
+/**
+ * \brief Reads the current configuration of direction port.
+ *
+ * \param slaveAddr [IN] I2C Slave Address.
+ * \param ioExpType [IN] IO expander type.
+ * X_PORT_IOEXP - Total number of ports
+ * in slave device.
+ * \param portNum [IN] Port number of the i2c slave device
+ * PORTNUM_X - Port number of a slave
+ * device.
+ * \param data [IN/OUT] Pointer to the data buffer to store
+ * the pin level data of a specified port.
+ *
+ * \return Board_STATUS in case of success or appropriate error code.
+ *
+ */
+Board_STATUS Board_i2cIoExpReadDirPort(uint8_t slaveAddr,
+ i2cIoExpType_t ioExpType,
+ i2cIoExpPortNumber_t portNum,
+ uint8_t *data)
+{
+ Board_STATUS ret = BOARD_SOK;
+ uint8_t subAddr;
+ I2C_Transaction transaction;
+
+ if(gIoExpI2cHandle == NULL)
+ {
+ return BOARD_INVALID_PARAM;
+ }
+
+ if (ioExpType == ONE_PORT_IOEXP)
+ {
+ subAddr = BOARD_1PORT_IOEXP_CONFIGURATION_CMD;
+ }
+ else if (ioExpType == TWO_PORT_IOEXP)
+ {
+ if(portNum == PORTNUM_0)
+ {
+ subAddr = BOARD_2PORT_IOEXP_PORT0_CONFIGURATION_CMD;
+ }
+ else if(portNum == PORTNUM_1)
+ {
+ subAddr = BOARD_2PORT_IOEXP_PORT1_CONFIGURATION_CMD;
+ }
+ else
+ {
+ return BOARD_INVALID_PARAM;
+ }
+ }
+ else if (ioExpType == THREE_PORT_IOEXP)
+ {
+ if(portNum == PORTNUM_0)
+ {
+ subAddr = BOARD_3PORT_IOEXP_PORT0_CONFIGURATION_CMD;
+ }
+ else if(portNum == PORTNUM_1)
+ {
+ subAddr = BOARD_3PORT_IOEXP_PORT1_CONFIGURATION_CMD;
+ }
+ else if(portNum == PORTNUM_2)
+ {
+ subAddr = BOARD_3PORT_IOEXP_PORT2_CONFIGURATION_CMD;
+ }
+ else
+ {
+ return BOARD_INVALID_PARAM;
+ }
+ }
+ else
+ {
+ return BOARD_INVALID_PARAM;
+ }
+
+ /* Initializes the I2C transaction structure with default values */
+ I2C_transactionInit(&transaction);
+
+ /*Control Byte followed by read bit */
+ transaction.slaveAddress = slaveAddr;
+ transaction.writeBuf = &subAddr;
+ transaction.readBuf = data;
+ transaction.writeCount = 1;
+ transaction.readCount = 0;
+
+ BOARD_delay(200);
+
+ ret = I2C_transfer(gIoExpI2cHandle, &transaction);
+ if(ret != I2C_STS_SUCCESS)
+ {
+ ret = BOARD_I2C_TRANSFER_FAIL;
+ return ret;
+ }
+
+ transaction.writeCount = 0;
+ transaction.readCount = 1;
+
+ BOARD_delay(20000);
+
+ ret = I2C_transfer(gIoExpI2cHandle, &transaction);
+ if(ret != I2C_STS_SUCCESS)
+ {
+ ret = BOARD_I2C_TRANSFER_FAIL;
+ return ret;
+ }
+
+ return BOARD_SOK;
+}
+
+/**
+ * \brief Reads the current configuration of output port.
+ *
+ * \param slaveAddr [IN] I2C Slave Address.
+ * \param ioExpType [IN] IO expander type.
+ * X_PORT_IOEXP - Total number of ports
+ * in slave device.
+ * \param portNum [IN] Port number of the i2c slave device
+ * PORTNUM_X - Port number of a slave
+ * device.
+ * \param data [IN/OUT] Pointer to the data buffer to store
+ * the pin level data of a specified port.
+ *
+ * \return Board_STATUS in case of success or appropriate error code.
+ *
+ */
+Board_STATUS Board_i2cIoExpReadOutputPort(uint8_t slaveAddr,
+ i2cIoExpType_t ioExpType,
+ i2cIoExpPortNumber_t portNum,
+ uint8_t *data)
+{
+ Board_STATUS ret = BOARD_SOK;
+ uint8_t subAddr;
+ I2C_Transaction transaction;
+
+ if(gIoExpI2cHandle == NULL)
+ {
+ return BOARD_INVALID_PARAM;
+ }
+
+ if (ioExpType == ONE_PORT_IOEXP)
+ {
+ subAddr = BOARD_1PORT_IOEXP_OUTPUT_CMD;
+ }
+ else if (ioExpType == TWO_PORT_IOEXP)
+ {
+ if(portNum == PORTNUM_0)
+ {
+ subAddr = BOARD_2PORT_IOEXP_PORT0_OUTPUT_CMD;
+ }
+ else if(portNum == PORTNUM_1)
+ {
+ subAddr = BOARD_2PORT_IOEXP_PORT1_OUTPUT_CMD;
+ }
+ else
+ {
+ return BOARD_INVALID_PARAM;
+ }
+ }
+ else if (ioExpType == THREE_PORT_IOEXP)
+ {
+ if(portNum == PORTNUM_0)
+ {
+ subAddr = BOARD_3PORT_IOEXP_PORT0_OUTPUT_CMD;
+ }
+ else if(portNum == PORTNUM_1)
+ {
+ subAddr = BOARD_3PORT_IOEXP_PORT1_OUTPUT_CMD;
+ }
+ else if(portNum == PORTNUM_2)
+ {
+ subAddr = BOARD_3PORT_IOEXP_PORT2_OUTPUT_CMD;
+ }
+ else
+ {
+ return BOARD_INVALID_PARAM;
+ }
+ }
+ else
+ {
+ return BOARD_INVALID_PARAM;
+ }
+
+ /* Initializes the I2C transaction structure with default values */
+ I2C_transactionInit(&transaction);
+
+ /*Control Byte followed by read bit */
+ transaction.slaveAddress = slaveAddr;
+ transaction.writeBuf = &subAddr;
+ transaction.readBuf = data;
+ transaction.writeCount = 1;
+ transaction.readCount = 0;
+
+ BOARD_delay(200);
+
+ ret = I2C_transfer(gIoExpI2cHandle, &transaction);
+ if(ret != I2C_STS_SUCCESS)
+ {
+ ret = BOARD_I2C_TRANSFER_FAIL;
+ return ret;
+ }
+
+ transaction.writeCount = 0;
+ transaction.readCount = 1;
+
+ BOARD_delay(20000);
+
+ ret = I2C_transfer(gIoExpI2cHandle, &transaction);
+ if(ret != I2C_STS_SUCCESS)
+ {
+ ret = BOARD_I2C_TRANSFER_FAIL;
+ return ret;
+ }
+
+ return BOARD_SOK;
+}
+
+/**
+ * \brief Reads the signal level of all the pins of the specified port.
+ *
+ * \param slaveAddr [IN] I2C Slave Address.
+ * \param ioExpType [IN] IO expander type.
+ * X_PORT_IOEXP - Total number of ports
+ * in slave device.
+ * \param portNum [IN] Port number of the i2c slave device
+ * PORTNUM_X - Port number of a slave
+ * device.
+ * \param data [IN/OUT] Pointer to the data buffer to store
+ * the pin level data of a specified port.
+ *
+ * \return Board_STATUS in case of success or appropriate error code.
+ *
+ */
+Board_STATUS Board_i2cIoExpReadInputPort(uint8_t slaveAddr,
+ i2cIoExpType_t ioExpType,
+ i2cIoExpPortNumber_t portNum,
+ uint8_t *data)
+{
+ Board_STATUS ret = BOARD_SOK;
+ uint8_t subAddr;
+ I2C_Transaction transaction;
+
+ if(gIoExpI2cHandle == NULL)
+ {
+ return BOARD_INVALID_PARAM;
+ }
+
+ if (ioExpType == ONE_PORT_IOEXP)
+ {
+ subAddr = BOARD_1PORT_IOEXP_INPUT_CMD;
+ }
+ else if (ioExpType == TWO_PORT_IOEXP)
+ {
+ if(portNum == PORTNUM_0)
+ {
+ subAddr = BOARD_2PORT_IOEXP_PORT0_INPUT_CMD;
+ }
+ else if(portNum == PORTNUM_1)
+ {
+ subAddr = BOARD_2PORT_IOEXP_PORT1_INPUT_CMD;
+ }
+ else
+ {
+ return BOARD_INVALID_PARAM;
+ }
+ }
+ else if (ioExpType == THREE_PORT_IOEXP)
+ {
+ if(portNum == PORTNUM_0)
+ {
+ subAddr = BOARD_3PORT_IOEXP_PORT0_INPUT_CMD;
+ }
+ else if(portNum == PORTNUM_1)
+ {
+ subAddr = BOARD_3PORT_IOEXP_PORT1_INPUT_CMD;
+ }
+ else if(portNum == PORTNUM_2)
+ {
+ subAddr = BOARD_3PORT_IOEXP_PORT2_INPUT_CMD;
+ }
+ else
+ {
+ return BOARD_INVALID_PARAM;
+ }
+ }
+ else
+ {
+ return BOARD_INVALID_PARAM;
+ }
+
+ /* Initializes the I2C transaction structure with default values */
+ I2C_transactionInit(&transaction);
+
+ /*Control Byte followed by read bit */
+ transaction.slaveAddress = slaveAddr;
+ transaction.writeBuf = &subAddr;
+ transaction.readBuf = data;
+ transaction.writeCount = 1;
+ transaction.readCount = 0;
+
+ BOARD_delay(200);
+
+ ret = I2C_transfer(gIoExpI2cHandle, &transaction);
+ if(ret != I2C_STS_SUCCESS)
+ {
+ ret = BOARD_I2C_TRANSFER_FAIL;
+ return ret;
+ }
+
+ transaction.writeCount = 0;
+ transaction.readCount = 1;
+
+ BOARD_delay(20000);
+
+ ret = I2C_transfer(gIoExpI2cHandle, &transaction);
+ if(ret != I2C_STS_SUCCESS)
+ {
+ ret = BOARD_I2C_TRANSFER_FAIL;
+ return ret;
+ }
+
+ return BOARD_SOK;
+}
+
+/**
+ * \brief Sets the direction of all the pins of the specified Port.
+ *
+ * \param slaveAddr [IN] I2C Slave Address.
+ * \param ioExpType [IN] IO expander type.
+ * X_PORT_IOEXP - Total number of ports
+ * in that slave device.
+ * \param portNum [IN] Port number of the i2c slave device
+ * PORTNUM_X - Port number of a
+ * slave device.
+ * \param data [IN] Register data to be configured.
+ *
+ * \return Board_STATUS in case of success or appropriate error code.
+ *
+ */
+Board_STATUS Board_i2cIoExpSetPortDirection(uint8_t slaveAddr,
+ i2cIoExpType_t ioExpType,
+ i2cIoExpPortNumber_t portNum,
+ uint8_t data)
+{
+ Board_STATUS ret = BOARD_SOK;
+ uint8_t dataBuff[2] = {0};
+ I2C_Transaction transaction;
+
+ if(gIoExpI2cHandle == NULL)
+ {
+ return BOARD_INVALID_PARAM;
+ }
+
+ if (ioExpType == ONE_PORT_IOEXP)
+ {
+ dataBuff[0] = BOARD_1PORT_IOEXP_CONFIGURATION_CMD;
+ }
+ else if (ioExpType == TWO_PORT_IOEXP)
+ {
+ if(portNum == PORTNUM_0)
+ {
+ dataBuff[0] = BOARD_2PORT_IOEXP_PORT0_CONFIGURATION_CMD;
+ }
+ else if(portNum == PORTNUM_1)
+ {
+ dataBuff[0] = BOARD_2PORT_IOEXP_PORT1_CONFIGURATION_CMD;
+ }
+ else
+ {
+ return -1;
+ }
+ }
+ else if (ioExpType == THREE_PORT_IOEXP)
+ {
+ if(portNum == PORTNUM_0)
+ {
+ dataBuff[0] = BOARD_3PORT_IOEXP_PORT0_CONFIGURATION_CMD;
+ }
+ else if(portNum == PORTNUM_1)
+ {
+ dataBuff[0] = BOARD_3PORT_IOEXP_PORT1_CONFIGURATION_CMD;
+ }
+ else if(portNum == PORTNUM_2)
+ {
+ dataBuff[0] = BOARD_3PORT_IOEXP_PORT2_CONFIGURATION_CMD;
+ }
+ else
+ {
+ return -1;
+ }
+ }
+ else
+ {
+ return -1;
+ }
+
+ dataBuff[1] = data;
+
+ /* Initializes the I2C transaction structure with default values */
+ I2C_transactionInit(&transaction);
+
+ /* Control Byte followed by write bit */
+ transaction.slaveAddress = slaveAddr;
+ transaction.writeBuf = &dataBuff;
+ transaction.writeCount = 2;
+ transaction.readCount = 0;
+
+ BOARD_delay(200);
+
+ ret = I2C_transfer(gIoExpI2cHandle, &transaction);
+ if(ret != I2C_STS_SUCCESS)
+ {
+ ret = BOARD_I2C_TRANSFER_FAIL;
+ return ret;
+ }
+
+ return BOARD_SOK;
+}
+
+/**
+ * \brief Sets the direction of the specified pin of the specified port.
+ *
+ * \param slaveAddr [IN] I2C Slave Address.
+ * \param ioExpType [IN] IO expander type.
+ * X_PORT_IOEXP - Total number of ports
+ * in slave device.
+ * \param portNum [IN] Port number of the i2c slave device
+ * PORTNUM_X - Port number of a slave
+ * device.
+ * \param pinNum [IN] Pin with in the specified port of
+ * the i2c slave device.
+ * PIN_NUM_X - Pin number.
+ * \param direction [IN] Direction of the pin to be configured.
+ *
+ * \return Board_STATUS in case of success or appropriate error code.
+ *
+ */
+Board_STATUS Board_i2cIoExpSetPinDirection(uint8_t slaveAddr,
+ i2cIoExpType_t ioExpType,
+ i2cIoExpPortNumber_t portNum,
+ i2cIoExpPinNumber_t pinNum,
+ i2cIoExpPinDirection_t direction)
+{
+ Board_STATUS ret = BOARD_SOK;
+ uint8_t dataBuff[2] = {0};
+ uint8_t data;
+ I2C_Transaction transaction;
+
+ if(gIoExpI2cHandle == NULL)
+ {
+ return BOARD_INVALID_PARAM;
+ }
+
+ if (ioExpType == ONE_PORT_IOEXP)
+ {
+ dataBuff[0] = BOARD_1PORT_IOEXP_CONFIGURATION_CMD;
+ }
+ else if (ioExpType == TWO_PORT_IOEXP)
+ {
+ if(portNum == PORTNUM_0)
+ {
+ dataBuff[0] = BOARD_2PORT_IOEXP_PORT0_CONFIGURATION_CMD;
+ }
+ else if(portNum == PORTNUM_1)
+ {
+ dataBuff[0] = BOARD_2PORT_IOEXP_PORT1_CONFIGURATION_CMD;
+ }
+ else
+ {
+ return BOARD_INVALID_PARAM;
+ }
+ }
+ else if (ioExpType == THREE_PORT_IOEXP)
+ {
+ if(portNum == PORTNUM_0)
+ {
+ dataBuff[0] = BOARD_3PORT_IOEXP_PORT0_CONFIGURATION_CMD;
+ }
+ else if(portNum == PORTNUM_1)
+ {
+ dataBuff[0] = BOARD_3PORT_IOEXP_PORT1_CONFIGURATION_CMD;
+ }
+ else if(portNum == PORTNUM_2)
+ {
+ dataBuff[0] = BOARD_3PORT_IOEXP_PORT2_CONFIGURATION_CMD;
+ }
+ else
+ {
+ return BOARD_INVALID_PARAM;
+ }
+ }
+ else
+ {
+ return BOARD_INVALID_PARAM;
+ }
+
+ Board_i2cIoExpReadDirPort(slaveAddr, ioExpType, portNum, &data);
+ if(direction == PIN_DIRECTION_OUTPUT)
+ {
+ dataBuff[1] = ((data & ~(1 << pinNum)) | (0 << pinNum));
+ }
+ else
+ {
+ dataBuff[1] = ((data & ~(1 << pinNum)) | (1 << pinNum));
+ }
+
+ /* Initializes the I2C transaction structure with default values */
+ I2C_transactionInit(&transaction);
+
+ /* Control Byte followed by write bit */
+ transaction.slaveAddress = slaveAddr;
+ transaction.writeBuf = &dataBuff;
+ transaction.writeCount = 2;
+ transaction.readCount = 0;
+
+ BOARD_delay(200);
+
+ ret = I2C_transfer(gIoExpI2cHandle, &transaction);
+ if(ret != I2C_STS_SUCCESS)
+ {
+ ret = BOARD_I2C_TRANSFER_FAIL;
+ return ret;
+ }
+
+ return BOARD_SOK;
+}
+
+/**
+ * \brief Sets the signal level of all the pins of the specified port.
+ *
+ * \param slaveAddr [IN] I2C Slave Address.
+ * \param ioExpType [IN] IO expander type.
+ * X_PORT_IOEXP - Total number of ports
+ * in slave device.
+ * \param portNum [IN] Port number of the i2c slave device
+ * PORTNUM_X - Port number of a slave
+ * device.
+ * \param data [IN] Signal level data of the pins to be
+ * configured.
+ *
+ * \return Board_STATUS in case of success or appropriate error code.
+ *
+ */
+Board_STATUS Board_i2cIoExpWritePort(uint8_t slaveAddr,
+ i2cIoExpType_t ioExpType,
+ i2cIoExpPortNumber_t portNum,
+ uint8_t data)
+{
+ Board_STATUS ret = BOARD_SOK;
+ uint8_t dataBuff[2] = {0};
+ I2C_Transaction transaction;
+
+ if(gIoExpI2cHandle == NULL)
+ {
+ return BOARD_INVALID_PARAM;
+ }
+
+ if (ioExpType == ONE_PORT_IOEXP)
+ {
+ dataBuff[0] = BOARD_1PORT_IOEXP_OUTPUT_CMD;
+ }
+ else if (ioExpType == TWO_PORT_IOEXP)
+ {
+ if(portNum == PORTNUM_0)
+ {
+ dataBuff[0] = BOARD_2PORT_IOEXP_PORT0_OUTPUT_CMD;
+ }
+ else if(portNum == PORTNUM_1)
+ {
+ dataBuff[0] = BOARD_2PORT_IOEXP_PORT1_OUTPUT_CMD;
+ }
+ else
+ {
+ return BOARD_INVALID_PARAM;
+ }
+ }
+ else if (ioExpType == THREE_PORT_IOEXP)
+ {
+ if(portNum == PORTNUM_0)
+ {
+ dataBuff[0] = BOARD_3PORT_IOEXP_PORT0_OUTPUT_CMD;
+ }
+ else if(portNum == PORTNUM_1)
+ {
+ dataBuff[0] = BOARD_3PORT_IOEXP_PORT1_OUTPUT_CMD;
+ }
+ else if(portNum == PORTNUM_2)
+ {
+ dataBuff[0] = BOARD_3PORT_IOEXP_PORT2_OUTPUT_CMD;
+ }
+ else
+ {
+ return BOARD_INVALID_PARAM;
+ }
+ }
+ else
+ {
+ return BOARD_INVALID_PARAM;
+ }
+
+ dataBuff[1] = data;
+
+ /* Initializes the I2C transaction structure with default values */
+ I2C_transactionInit(&transaction);
+
+ /* Control Byte followed by write bit */
+ transaction.slaveAddress = slaveAddr;
+ transaction.writeBuf = &dataBuff;
+ transaction.writeCount = 2;
+ transaction.readCount = 0;
+
+ BOARD_delay(200);
+
+ ret = I2C_transfer(gIoExpI2cHandle, &transaction);
+ if(ret != I2C_STS_SUCCESS)
+ {
+ ret = BOARD_I2C_TRANSFER_FAIL;
+ return ret;
+ }
+
+ return BOARD_SOK;
+}
+
+/**
+ * \brief Sets the signal level of the specified pin of the specified port.
+ *
+ * \param slaveAddr [IN] I2C Slave Address.
+ * \param ioExpType [IN] IO expander type.
+ * X_PORT_IOEXP - Total number of ports
+ * in slave device.
+ * \param portNum [IN] Port number of the i2c slave device
+ * PORTNUM_X - Port number of a slave
+ * device.
+ * \param pinNum [IN] Pin with in the specified port of
+ * the i2c slave device.
+ * PIN_NUM_X - Pin number.
+ * \param signalLevel [IN] Signal level data of the pin to be
+ * configured.
+ *
+ * \return Board_STATUS in case of success or appropriate error code.
+ *
+ */
+Board_STATUS Board_i2cIoExpPinLevelSet(uint8_t slaveAddr,
+ i2cIoExpType_t ioExpType,
+ i2cIoExpPortNumber_t portNum,
+ i2cIoExpPinNumber_t pinNum,
+ i2cIoExpSignalLevel_t signalLevel)
+{
+ Board_STATUS ret = BOARD_SOK;
+ uint8_t dataBuff;
+ uint8_t data;
+
+ ret = Board_i2cIoExpReadOutputPort(slaveAddr, ioExpType, portNum, &data);
+ if(ret != BOARD_SOK)
+ {
+ ret = BOARD_I2C_TRANSFER_FAIL;
+ return ret;
+ }
+
+ dataBuff = (signalLevel << pinNum);
+ data = ((data & ~(1 << pinNum)) | dataBuff);
+ return (Board_i2cIoExpWritePort(slaveAddr, ioExpType, portNum, data));
+}
+
+/**
+ * \brief Reads the signal level of specified pin of the specified port.
+ *
+ * \param slaveAddr [IN] I2C Slave Address.
+ * \param ioExpType [IN] IO expander type.
+ * X_PORT_IOEXP - Total number of ports
+ * in slave device.
+ * \param portNum [IN] Port number of the i2c slave device.
+ * PORTNUM_X - Port number of a slave
+ * device.
+ * \param pinNum [IN] Pin number of the specified port.
+ * PIN_NUM_X - Pin number.
+ * \param signalLevel [IN/OUT] Data buffer to store specified pin
+ * level of a specified port.
+ *
+ * \return Board_STATUS in case of success or appropriate error code.
+ *
+ */
+Board_STATUS Board_i2cIoExpPinLevelGet(uint8_t slaveAddr,
+ i2cIoExpType_t ioExpType,
+ i2cIoExpPortNumber_t portNum,
+ i2cIoExpPinNumber_t pinNum,
+ uint8_t *signalLevel)
+{
+ Board_STATUS ret = BOARD_SOK;
+ uint8_t data;
+
+ ret = Board_i2cIoExpReadInputPort(slaveAddr, ioExpType, portNum, &data);
+ if(ret != BOARD_SOK)
+ {
+ ret = BOARD_I2C_TRANSFER_FAIL;
+ return ret;
+ }
+
+ *signalLevel = (((1 << pinNum) & (data)) >> pinNum);
+
+ return BOARD_SOK;
+}
+
+/**
+ * \brief Initializes the i2c instance connected to the i2c IO Expander.
+ *
+ * \return BOARD_SOK in case of success or appropriate error code.
+ *
+ */
+Board_STATUS Board_i2cIoExpInit(void)
+{
+ Board_STATUS ret = BOARD_SOK;
+
+ /* If handle not opened yet, initializes i2c */
+ if (gIoExpI2cHandle == NULL)
+ {
+ gIoExpI2cHandle = Board_getI2CHandle(gBoardI2cInitCfg.socDomain,
+ gBoardI2cInitCfg.i2cInst);
+ if(gIoExpI2cHandle == NULL)
+ {
+ ret = BOARD_I2C_OPEN_FAIL;
+ }
+ }
+
+ return ret;
+}
+
+/**
+ * \brief de-initializes the i2c instance connected to the i2c IO Expander.
+ *
+ */
+void Board_i2cIoExpDeInit(void)
+{
+ /* Closing the i2c IO Exp Instance */
+ Board_i2cDeInit();
+ gIoExpI2cHandle = NULL;
+}
diff --git a/packages/ti/board/src/j721s2_evm/board_info.c b/packages/ti/board/src/j721s2_evm/board_info.c
--- /dev/null
@@ -0,0 +1,378 @@
+/******************************************************************************
+ * Copyright (c) 2021 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *****************************************************************************/
+
+/**
+ * \file board_info.c
+ *
+ * \brief This file contains the functions to read/write board info data
+ *
+ */
+
+#include "board_utils.h"
+#include "board_internal.h"
+#include "board_cfg.h"
+#include <stdio.h>
+#include <string.h>
+
+extern Board_I2cInitCfg_t gBoardI2cInitCfg;
+
+/**
+ * @brief This function is not supported by this platform.
+ *
+ * Function implementation for build backward compatibilty.
+ * Always returns 'BOARD_UNSUPPORTED_FEATURE'
+ *
+ */
+Board_STATUS Board_getIDInfo(Board_IDInfo *info)
+{
+ return BOARD_UNSUPPORTED_FEATURE;
+}
+
+/**
+ * @brief Get board information.
+ *
+ * This function requires the information of I2C instance and domain
+ * to which board ID EEPROM is connected. This need to be set using
+ * Board_setI2cInitConfig() before calling this function.
+ *
+ * @param[out] Board_STATUS
+ * Returns status on API call
+ * @param[out] info
+ * This structure will have board information on return
+ * @param[in] slaveAddress
+ * I2C slave address of EEPROM to be read
+ *
+ */
+Board_STATUS Board_getIDInfo_v2(Board_IDInfo_v2 *info, uint8_t slaveAddress)
+{
+ Board_STATUS ret = BOARD_SOK;
+ I2C_Transaction i2cTransaction;
+ I2C_Handle handle = NULL;
+ uint16_t offsetAddress = BOARD_EEPROM_HEADER_ADDR;
+ uint8_t rdBuff[3];
+ char txBuf[2] = {0x00, 0x00};
+ bool status;
+
+ handle = Board_getI2CHandle(gBoardI2cInitCfg.socDomain,
+ gBoardI2cInitCfg.i2cInst);
+ if(handle == NULL)
+ {
+ ret = BOARD_I2C_OPEN_FAIL;
+ }
+
+ I2C_transactionInit(&i2cTransaction);
+
+ i2cTransaction.slaveAddress = slaveAddress;
+ i2cTransaction.writeBuf = (uint8_t *)&txBuf[0];
+ i2cTransaction.writeCount = 2;
+
+ /* Get header info */
+ txBuf[0] = (char)(((uint32_t) 0xFF00 & offsetAddress)>>8);
+ txBuf[1] = (char)((uint32_t) 0xFF & offsetAddress);
+ i2cTransaction.readBuf = &info->headerInfo;
+ i2cTransaction.readCount = BOARD_EEPROM_HEADER_FIELD_SIZE;
+
+ status = I2C_transfer(handle, &i2cTransaction);
+ if (status == false)
+ {
+ ret = BOARD_I2C_TRANSFER_FAIL;
+ Board_i2cDeInit();
+ return ret;
+ }
+
+ /* Checking whether the board contents are flashed or not */
+ if (info->headerInfo.magicNumber == BOARD_EEPROM_MAGIC_NUMBER)
+ {
+ offsetAddress = offsetAddress + i2cTransaction.readCount;
+ txBuf[0] = (char)(((uint32_t) 0xFF00 & offsetAddress) >> 8);
+ txBuf[1] = (char)((uint32_t) 0xFF & offsetAddress);
+ i2cTransaction.readBuf = &info->boardInfo;
+ i2cTransaction.readCount = BOARD_EEPROM_TYPE_SIZE +
+ BOARD_EEPROM_STRUCT_LENGTH_SIZE;
+ status = I2C_transfer(handle, &i2cTransaction);
+ if (status == false)
+ {
+ ret = BOARD_I2C_TRANSFER_FAIL;
+ Board_i2cDeInit();
+ return ret;
+ }
+
+ offsetAddress = offsetAddress + i2cTransaction.readCount;
+ txBuf[0] = (char)(((uint32_t) 0xFF00 & offsetAddress) >> 8);
+ txBuf[1] = (char)((uint32_t) 0xFF & offsetAddress);
+ i2cTransaction.readBuf = info->boardInfo.boardName;
+ i2cTransaction.readCount = info->boardInfo.boardInfoLength;
+
+ status = I2C_transfer(handle, &i2cTransaction);
+ if (status == false)
+ {
+ ret = BOARD_I2C_TRANSFER_FAIL;
+ Board_i2cDeInit();
+ return ret;
+ }
+
+ offsetAddress = offsetAddress + i2cTransaction.readCount;
+ txBuf[0] = (char)(((uint32_t) 0xFF00 & offsetAddress) >> 8);
+ txBuf[1] = (char)((uint32_t) 0xFF & offsetAddress);
+ i2cTransaction.readBuf = &rdBuff[0];
+ i2cTransaction.readCount = BOARD_EEPROM_TYPE_SIZE +
+ BOARD_EEPROM_STRUCT_LENGTH_SIZE;
+
+ status = I2C_transfer(handle, &i2cTransaction);
+ if (status == false)
+ {
+ ret = BOARD_I2C_TRANSFER_FAIL;
+ Board_i2cDeInit();
+ return ret;
+ }
+
+ /* Checking whether DDR field is present or not */
+ if (rdBuff[0] == BOARD_DDR_FIELD_TYPE)
+ {
+ memcpy(&info->ddrInfo, &rdBuff[0], sizeof(rdBuff));
+
+ offsetAddress = offsetAddress + i2cTransaction.readCount;
+ txBuf[0] = (char)(((uint32_t) 0xFF00 & offsetAddress)>>8);
+ txBuf[1] = (char)((uint32_t) 0xFF & offsetAddress);
+ i2cTransaction.readBuf = &info->ddrInfo.ddrCtrl;
+ i2cTransaction.readCount = info->ddrInfo.ddrStructLen;
+
+ status = I2C_transfer(handle, &i2cTransaction);
+ if (status == false)
+ {
+ ret = BOARD_I2C_TRANSFER_FAIL;
+ Board_i2cDeInit();
+ return ret;
+ }
+
+ offsetAddress = offsetAddress + i2cTransaction.readCount;
+ txBuf[0] = (char)(((uint32_t) 0xFF00 & offsetAddress) >> 8);
+ txBuf[1] = (char)((uint32_t) 0xFF & offsetAddress);
+ i2cTransaction.readBuf = &rdBuff[0];
+ i2cTransaction.readCount = BOARD_EEPROM_TYPE_SIZE +
+ BOARD_EEPROM_STRUCT_LENGTH_SIZE;
+ status = I2C_transfer(handle, &i2cTransaction);
+ if (status == false)
+ {
+ ret = BOARD_I2C_TRANSFER_FAIL;
+ Board_i2cDeInit();
+ return ret;
+ }
+ }
+
+ /* Checking whether MAC id field is present or not */
+ if(rdBuff[0] == BOARD_MACINFO_FIELD_TYPE)
+ {
+ memcpy(&info->macInfo, &rdBuff[0], sizeof(rdBuff));
+
+ offsetAddress = offsetAddress + i2cTransaction.readCount;
+ txBuf[0] = (char)(((uint32_t) 0xFF00 & offsetAddress) >> 8);
+ txBuf[1] = (char)((uint32_t) 0xFF & offsetAddress);
+ i2cTransaction.readBuf = &info->macInfo.macControl;
+ i2cTransaction.readCount = info->macInfo.macLength;
+
+ status = I2C_transfer(handle, &i2cTransaction);
+ if (status == false)
+ {
+ ret = BOARD_I2C_TRANSFER_FAIL;
+ Board_i2cDeInit();
+ return ret;
+ }
+
+ offsetAddress = offsetAddress + i2cTransaction.readCount;
+ txBuf[0] = (char)(((uint32_t) 0xFF00 & offsetAddress)>>8);
+ txBuf[1] = (char)((uint32_t) 0xFF & offsetAddress);
+ i2cTransaction.readBuf = &rdBuff[0];
+ i2cTransaction.readCount = BOARD_EEPROM_TYPE_SIZE;
+
+ status = I2C_transfer(handle, &i2cTransaction);
+ if (status == false)
+ {
+ ret = BOARD_I2C_TRANSFER_FAIL;
+ Board_i2cDeInit();
+ return ret;
+ }
+ }
+
+ if(rdBuff[0] == BOARD_ENDLIST)
+ {
+ info->endList = rdBuff[0];
+ }
+ }
+ else
+ {
+ ret = BOARD_INVALID_PARAM;
+ Board_i2cDeInit();
+ return ret;
+ }
+
+ Board_i2cDeInit();
+
+ return ret;
+}
+
+/**
+ * @brief This function is not supported by this platform.
+ *
+ * Function implementation for build backward compatibilty.
+ * Always returns 'BOARD_UNSUPPORTED_FEATURE'
+ *
+ */
+Board_STATUS Board_writeIDInfo(Board_IDInfo *info)
+{
+ return BOARD_UNSUPPORTED_FEATURE;
+}
+
+/**
+ * @brief Write board id contents to specific EEPROM.
+ *
+ * This function requires the information of I2C instance and domain
+ * to which board ID EEPROM is connected. This need to be set using
+ * Board_setI2cInitConfig() before calling this function.
+ *
+ * @param[out] Board_STATUS
+ * Returns status on API call
+ * @param[out] info
+ * Structure contain board id contents to write
+ * @param[in] slaveAddress
+ * Address of eeprom
+ *
+ */
+Board_STATUS Board_writeIDInfo_v2(Board_IDInfo_v2 *info, uint8_t slaveAddress)
+{
+ Board_STATUS ret = BOARD_SOK;
+ I2C_Transaction i2cTransaction;
+ I2C_Handle handle = NULL;
+ uint16_t offsetSize = 2;
+ uint16_t offsetAddress = BOARD_EEPROM_HEADER_ADDR;
+ char txBuf[BOARD_EEPROM_MAX_BUFF_LENGTH + 2 + 1];
+ bool status;
+
+ /* Checking the structure is valid or not */
+ if (info->headerInfo.magicNumber != BOARD_EEPROM_MAGIC_NUMBER)
+ {
+ ret = BOARD_INVALID_PARAM;
+ return ret;
+ }
+
+ handle = Board_getI2CHandle(gBoardI2cInitCfg.socDomain,
+ gBoardI2cInitCfg.i2cInst);
+ if(handle == NULL)
+ {
+ ret = BOARD_I2C_OPEN_FAIL;
+ }
+
+ I2C_transactionInit(&i2cTransaction);
+
+ /* Transferring Header and Board Info field */
+ i2cTransaction.slaveAddress = slaveAddress;
+ i2cTransaction.writeBuf = &txBuf[0];
+ i2cTransaction.writeCount = BOARD_EEPROM_HEADER_FIELD_SIZE +
+ BOARD_EEPROM_TYPE_SIZE +
+ BOARD_EEPROM_STRUCT_LENGTH_SIZE +
+ info->boardInfo.boardInfoLength +
+ offsetSize;
+ txBuf[0] = (char)(((uint32_t) 0xFF00 & offsetAddress) >> 8);
+ txBuf[1] = (char)((uint32_t) 0xFF & offsetAddress);
+ memcpy(&txBuf[2], &info->headerInfo, i2cTransaction.writeCount);
+
+ i2cTransaction.readBuf = NULL;
+ i2cTransaction.readCount = 0;
+
+ status = I2C_transfer(handle, &i2cTransaction);
+ if (status == false)
+ {
+ ret = BOARD_I2C_TRANSFER_FAIL;
+ Board_i2cDeInit();
+ return ret;
+ }
+
+ /* Checking whether DDR field is included or not */
+ if (info->ddrInfo.ddrStructType == BOARD_DDR_FIELD_TYPE)
+ {
+ offsetAddress = offsetAddress + i2cTransaction.writeCount;
+ i2cTransaction.writeCount = info->ddrInfo.ddrStructLen +
+ BOARD_EEPROM_TYPE_SIZE +
+ BOARD_EEPROM_STRUCT_LENGTH_SIZE +
+ offsetSize;
+ txBuf[0] = (char)(((uint32_t) 0xFF00 & offsetAddress) >> 8);
+ txBuf[1] = (char)((uint32_t) 0xFF & offsetAddress);
+ memcpy(&txBuf[2], &info->ddrInfo, i2cTransaction.writeCount);
+
+ status = I2C_transfer(handle, &i2cTransaction);
+ if (status == false)
+ {
+ ret = BOARD_I2C_TRANSFER_FAIL;
+ Board_i2cDeInit();
+ return ret;
+ }
+ }
+
+ /* Checking whether MAC id field is included or not */
+ if (info->macInfo.macStructType == BOARD_MACINFO_FIELD_TYPE)
+ {
+ offsetAddress = offsetAddress + i2cTransaction.writeCount;
+ i2cTransaction.writeCount = info->macInfo.macLength +
+ BOARD_EEPROM_TYPE_SIZE +
+ BOARD_EEPROM_STRUCT_LENGTH_SIZE +
+ offsetSize;
+ txBuf[0] = (char)(((uint32_t) 0xFF00 & offsetAddress) >> 8);
+ txBuf[1] = (char)((uint32_t) 0xFF & offsetAddress);
+ memcpy(&txBuf[2], &info->macInfo, i2cTransaction.writeCount);
+
+ status = I2C_transfer(handle, &i2cTransaction);
+ if (status == false)
+ {
+ ret = BOARD_I2C_TRANSFER_FAIL;
+ Board_i2cDeInit();
+ return ret;
+ }
+ }
+
+ offsetAddress = offsetAddress + i2cTransaction.writeCount;
+ i2cTransaction.writeCount = BOARD_EEPROM_TYPE_SIZE + offsetSize;
+ txBuf[0] = (char)(((uint32_t) 0xFF00 & offsetAddress)>>8);
+ txBuf[1] = (char)((uint32_t) 0xFF & offsetAddress);
+ memcpy(&txBuf[2], &info->endList, i2cTransaction.writeCount);
+
+ status = I2C_transfer(handle, &i2cTransaction);
+ if (status == false)
+ {
+ ret = BOARD_I2C_TRANSFER_FAIL;
+ Board_i2cDeInit();
+ return ret;
+ }
+
+ Board_i2cDeInit();
+ return ret;
+}
diff --git a/packages/ti/board/src/j721s2_evm/board_init.c b/packages/ti/board/src/j721s2_evm/board_init.c
--- /dev/null
@@ -0,0 +1,422 @@
+/******************************************************************************
+ * Copyright (c) 2021 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *****************************************************************************/
+/**
+ * \file board_init.c
+ *
+ * \brief Board library main file
+ *
+ * Board library provides basic functions to initialize the interfaces
+ * on a given HW platform. It takes care of configuring and enabling different
+ * modules like PLL, clocks inside SoC and HW components on the board which are
+ * required to make sure board is ready for running the application software.
+ *
+ * A common standard API Board_init() is exposed to the applications to invoke
+ * different board initialization routines. This function is common across the
+ * platforms maitaining the portability and can receive different input
+ * configuration flags based on the board capabilities allowing extendibility.
+ *
+ * Board library shall eliminate the use of any additional configurations like
+ * GEL files to initialize the board except the cases like DDR initialization
+ * for loading the code into DDR before calling the Board init function.
+ * Give this limitation, applications invoking board library functions to
+ * initialize PLL, DDR and pinmux are supposed to run from SoC internal memory.
+ *
+ */
+
+#include "board_internal.h"
+#include "board_ethernet_config.h"
+#include "board_utils.h"
+#include <ti/drv/sciclient/sciclient.h>
+#include <ti/drv/sciclient/sciserver.h>
+
+static bool gBoardSysInitDone = 0;
+
+/**
+ * \brief Board global initializations
+ *
+ * \return BOARD_SOK in case of success or appropriate error code
+ *
+ */
+static Board_STATUS Board_sysInit(void)
+{
+ Board_STATUS status = BOARD_SOK;
+ int32_t ret;
+ Sciclient_ConfigPrms_t config;
+
+ if(gBoardSysInitDone == 0)
+ {
+ Sciclient_configPrmsInit(&config);
+
+ ret = Sciclient_init(&config);
+ if(ret != 0)
+ {
+ status = BOARD_FAIL;
+ }
+
+ if(status == BOARD_SOK)
+ {
+ gBoardSysInitDone = 1;
+ }
+ }
+
+ return status;
+}
+
+/**
+ * \brief Board global de-initializations
+ *
+ * \return BOARD_SOK in case of success or appropriate error code
+ *
+ */
+static Board_STATUS Board_sysDeinit(void)
+{
+ Board_STATUS status = BOARD_SOK;
+ int32_t ret;
+
+ if(gBoardSysInitDone == 1)
+ {
+ ret = Sciclient_deinit();
+ if(ret != 0)
+ {
+ status = BOARD_FAIL;
+ }
+
+ if(status == BOARD_SOK)
+ {
+ gBoardSysInitDone = 0;
+ }
+ }
+
+ return status;
+}
+
+/**
+ * \brief Board library initialization function
+ *
+ * Different board initialization routines are invoked by using configuration
+ * flags as described below
+ * BOARD_INIT_UNLOCK_MMR -
+ * Unlocks the MMR registers of the SoC. MMR registers should be
+ * enabled before any write access to MMR register address space.
+ *
+ * BOARD_INIT_PLL -
+ * Configures different PLL controller modules. This enables all the PLL
+ * controllers on the SoC with default configurations. Any custom values
+ * required for PLL output needs to be done separately
+ *
+ * BOARD_INIT_PLL_MCU -
+ * Configures different PLL controller modules in the MCU domain. This
+ * enables all the PLL controllers in the MCUSS with default configurations.
+ * Any custom values required for PLL output needs to be done separately
+ *
+ * BOARD_INIT_PLL_MAIN -
+ * Configures different PLL controller modules in the MAIN domain. This
+ * enables all the PLL controllers in the MAIN domain with default configurations.
+ * Any custom values required for PLL output needs to be done separately
+ *
+ * BOARD_INIT_DDR -
+ * Initializes the DDR timing parameters. Sets the DDR timing parameters
+ * based in the DDR PLL controller configuration done by the board library.
+ * Any changes to DDR PLL requires change to DDR timing.
+ *
+ * BOARD_INIT_PINMUX_CONFIG -
+ * Enables pinmux for the board interfaces. Pin mux is done based on the
+ * default/primary functionality of the board. Any pins shared by multiple
+ * interfaces need to be reconfigured to access the secondary functionality.
+ *
+ * BOARD_INIT_PINMUX_CONFIG_MAIN -
+ * Enables pinmux for the board interfaces in MAIN domain. Pin mux is done
+ * based on the default/primary functionality of the board. Any pins shared
+ * by multiple interfaces need to be reconfigured to access the secondary
+ * functionality.
+ *
+ * BOARD_INIT_PINMUX_CONFIG_MCU -
+ * Enables pinmux for the board interfaces in MCU domain. Pin mux is done
+ * based on the default/primary functionality of the board. Any pins shared
+ * by multiple interfaces need to be reconfigured to access the secondary
+ * functionality.
+ *
+ * BOARD_INIT_UART_STDIO -
+ * Configures the UART module to use for serial console messages.
+ *
+ * BOARD_INIT_MODULE_CLOCK -
+ * Enables different power domains and peripheral clocks of the SoC.
+ * Some of the power domains and peripherals will be off by default.
+ * Enabling the power domains is mandatory before accessing using
+ * board interfaces connected to those peripherals.
+ *
+ * BOARD_INIT_MODULE_CLOCK_MCU -
+ * Enables different power domains and peripheral clocks in the MCU domain.
+ * Some of the power domains and peripherals will be off by default.
+ * Enabling the power domains is mandatory before accessing using
+ * board interfaces connected to those peripherals.
+ *
+ * BOARD_INIT_MODULE_CLOCK_MAIN -
+ * Enables different power domains and peripheral clocks in the MAIN domain.
+ * Some of the power domains and peripherals will be off by default.
+ * Enabling the power domains is mandatory before accessing using
+ * board interfaces connected to those peripherals.
+ *
+ * BOARD_INIT_ENETCTRL_CPSW2G -
+ * Enabled configurations for CPSW2G MCU Domain Ethernet ports with the respective modes
+ *
+ * BOARD_INIT_ENETCTRL_CPSW2G_MAIN -
+ * Enabled configurations for CPSW2G MAIN Domain Ethernet ports with the respective modes
+ *
+ *
+ * \param cfg [IN] Board configuration flags
+ *
+ * \return BOARD_SOK in case of success or appropriate error code
+ */
+Board_STATUS Board_init(Board_initCfg cfg)
+{
+ Board_STATUS ret = BOARD_SOK;
+
+ if(!gBoardSysInitDone)
+ {
+ Board_sysInit();
+ }
+
+ if (cfg & BOARD_INIT_UNLOCK_MMR)
+ ret = Board_unlockMMR();
+ if (ret != BOARD_SOK)
+ return ret;
+
+ if (cfg & BOARD_INIT_ENETCTRL_CPSW2G)
+ ret = Board_ethConfigCpsw2g();
+ if (ret != BOARD_SOK)
+ return ret;
+
+ if (cfg & BOARD_INIT_ENETCTRL_CPSW2G_MAIN)
+ ret = Board_ethConfigCpsw2gMain();
+ if (ret != BOARD_SOK)
+ return ret;
+
+ if (cfg & BOARD_INIT_MODULE_CLOCK)
+ {
+ ret = Board_moduleClockInitMcu();
+ if (ret != BOARD_SOK)
+ return ret;
+ ret = Board_moduleClockInitMain();
+ if (ret != BOARD_SOK)
+ return ret;
+ }
+
+ if (cfg & BOARD_INIT_MODULE_CLOCK_MCU)
+ ret = Board_moduleClockInitMcu();
+ if (ret != BOARD_SOK)
+ return ret;
+
+ if (cfg & BOARD_INIT_MODULE_CLOCK_MAIN)
+ ret = Board_moduleClockInitMain();
+ if (ret != BOARD_SOK)
+ return ret;
+
+ if (cfg & BOARD_INIT_PINMUX_CONFIG)
+ ret = Board_pinmuxConfig();
+ if (ret != BOARD_SOK)
+ return ret;
+
+ if (cfg & BOARD_INIT_PINMUX_CONFIG_MAIN)
+ ret = Board_pinmuxConfigMain();
+ if (ret != BOARD_SOK)
+ return ret;
+
+ if (cfg & BOARD_INIT_PINMUX_CONFIG_MCU)
+ ret = Board_pinmuxConfigWkup();
+ if (ret != BOARD_SOK)
+ return ret;
+
+ if (cfg & BOARD_INIT_PLL)
+ {
+ ret = Board_PLLInitMcu();
+ if (ret != BOARD_SOK)
+ return ret;
+ ret = Board_PLLInitMain();
+ if (ret != BOARD_SOK)
+ return ret;
+ }
+
+ if (cfg & BOARD_INIT_PLL_MCU)
+ ret = Board_PLLInitMcu();
+ if (ret != BOARD_SOK)
+ return ret;
+
+ if (cfg & BOARD_INIT_PLL_MAIN)
+ ret = Board_PLLInitMain();
+ if (ret != BOARD_SOK)
+ return ret;
+
+ if (cfg & BOARD_INIT_DDR)
+ {
+ if (cfg & BOARD_INIT_DDR_ECC)
+ {
+ ret = Board_DDRInit(true);
+ }
+ else
+ {
+ ret = Board_DDRInit(false);
+ }
+ }
+
+ if (ret != BOARD_SOK)
+ return ret;
+
+ if (cfg & BOARD_INIT_ETH_PHY)
+ ret = Board_cpsw2gEthPhyConfig();
+ if (ret != BOARD_SOK)
+ return ret;
+
+ if (cfg & BOARD_INIT_CPSW2G_MAIN_ETH_PHY)
+ ret = Board_cpsw2gMainEthPhyConfig();
+ if (ret != BOARD_SOK)
+ return ret;
+
+ if (cfg & BOARD_INIT_UART_STDIO)
+ ret = Board_uartStdioInit();
+ if (ret != BOARD_SOK)
+ return ret;
+
+ return ret;
+}
+
+/**
+ * \brief Board library de-initialization function
+ *
+ * Different board de-initialization routines are invoked by using configuration
+ * flags as described below
+ * BOARD_DEINIT_LOCK_MMR -
+ * Locks the MMR registers of the SoC.
+ *
+ * BOARD_DEINIT_UART_STDIO -
+ * Closes the board UART instance configured for serial console logs
+ *
+ * BOARD_DEINIT_MODULE_CLOCK -
+ * Disables PSC modules clocks which are enabled by Board_init function
+ *
+ * BOARD_DEINIT_UART_STDIO -
+ * Deinitializes the UART module.
+ *
+ * \param cfg [IN] Board configuration flags
+ *
+ * \return BOARD_SOK in case of success or appropriate error code
+ */
+Board_STATUS Board_deinit(Board_initCfg cfg)
+{
+ Board_STATUS ret = BOARD_SOK;
+
+ Board_sysDeinit();
+
+ if (cfg & BOARD_DEINIT_UART_STDIO)
+ ret = Board_uartDeInit();
+ if (ret != BOARD_SOK)
+ return ret;
+
+ if (cfg & BOARD_DEINIT_MODULE_CLOCK)
+ {
+ ret = Board_moduleClockDeinitMcu();
+ if (ret != BOARD_SOK)
+ return ret;
+ ret = Board_moduleClockDeinitMain();
+ if (ret != BOARD_SOK)
+ return ret;
+ }
+
+ if (cfg & BOARD_DEINIT_LOCK_MMR)
+ ret = Board_lockMMR();
+ if (ret != BOARD_SOK)
+ return ret;
+
+ return ret;
+}
+
+/**
+ * \brief Board library function to release the resources
+ *
+ * resourceID selects the resource to be released as per below IDs.
+ * Only one resource sould be released in one function call.
+ *
+ * BOARD_RESOURCE_MMR -
+ * Locks the MMR registers of the SoC.
+ *
+ * BOARD_RESOURCE_UART_STDIO -
+ * Closes the board UART instance configured for serial console logs
+ *
+ * BOARD_RESOURCE_MODULE_CLOCK -
+ * Releases the PSC clocks for all the modules listed by the clock groups
+ *
+ * BOARD_RESOURCE_ALL -
+ * Releases All the resources held by board library
+ *
+ * \param resourceID [IN] Resource ID
+ *
+ * \return BOARD_SOK in case of success or appropriate error code
+ */
+Board_STATUS Board_releaseResource (uint32_t resourceID)
+{
+ Board_STATUS ret = BOARD_SOK;
+
+ switch(resourceID)
+ {
+ case BOARD_RESOURCE_UART_STDIO:
+ ret = Board_uartDeInit();
+ break;
+
+ case BOARD_RESOURCE_MODULE_CLOCK:
+ ret = Board_moduleClockDeinitMcu();
+ ret |= Board_moduleClockDeinitMain();
+ break;
+
+ case BOARD_RESOURCE_MMR:
+ ret = Board_lockMMR();
+ break;
+
+ case BOARD_RESOURCE_SCICLIENT:
+ ret = Board_sysDeinit();
+ break;
+
+ case BOARD_RESOURCE_ALL:
+ ret = Board_uartDeInit();
+ ret |= Board_moduleClockDeinitMcu();
+ ret |= Board_moduleClockDeinitMain();
+ ret |= Board_lockMMR();
+ ret |= Board_sysDeinit();
+ break;
+
+ default:
+ ret = BOARD_INVALID_PARAM;
+ break;
+ }
+
+ return ret;
+}
diff --git a/packages/ti/board/src/j721s2_evm/board_lld_init.c b/packages/ti/board/src/j721s2_evm/board_lld_init.c
--- /dev/null
@@ -0,0 +1,403 @@
+/******************************************************************************
+ * Copyright (c) 2021 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *****************************************************************************/
+
+/**
+ * \file board_lld_init.c
+ *
+ * \brief This file initializes UART and I2C LLD modules
+ *
+ */
+
+#include <ti/csl/arch/csl_arch.h>
+#include "board_internal.h"
+#include "board_utils.h"
+#include "board_cfg.h"
+#include "board_control.h"
+
+extern Board_I2cInitCfg_t gBoardI2cInitCfg;
+extern Board_initParams_t gBoardInitParams;
+static uint32_t gUARTBaseAddr = 0;
+static uint32_t gUARTClkFreq = 0;
+
+uint32_t gBoardI2cBaseAddr[BOARD_SOC_DOMAIN_MAX][I2C_HWIP_MAX_CNT] =
+ {{CSL_I2C0_CFG_BASE, CSL_I2C1_CFG_BASE, CSL_I2C2_CFG_BASE, CSL_I2C3_CFG_BASE,
+ CSL_I2C4_CFG_BASE, CSL_I2C5_CFG_BASE, CSL_I2C6_CFG_BASE},
+ {CSL_WKUP_I2C0_CFG_BASE, 0, 0, 0, 0, 0, 0},
+ {CSL_MCU_I2C0_CFG_BASE, CSL_MCU_I2C1_CFG_BASE, 0, 0, 0, 0, 0}};
+
+Board_I2cObj_t gBoardI2cObj[BOARD_I2C_PORT_CNT] = {
+ {NULL, BOARD_SOC_DOMAIN_MAIN, 0, 0},
+ {NULL, BOARD_SOC_DOMAIN_MAIN, 1, 0},
+ {NULL, BOARD_SOC_DOMAIN_MAIN, 2, 0},
+ {NULL, BOARD_SOC_DOMAIN_MAIN, 3, 0},
+ {NULL, BOARD_SOC_DOMAIN_MAIN, 4, 0},
+ {NULL, BOARD_SOC_DOMAIN_MAIN, 5, 0},
+ {NULL, BOARD_SOC_DOMAIN_MAIN, 6, 0}
+};
+
+uint32_t gBoardUartBaseAddr[BOARD_SOC_DOMAIN_MAX][CSL_UART_MAIN_CNT] =
+ {{CSL_UART0_BASE, CSL_UART1_BASE, CSL_UART2_BASE, CSL_UART3_BASE, CSL_UART4_BASE,
+ CSL_UART5_BASE, CSL_UART6_BASE, CSL_UART7_BASE, CSL_UART8_BASE, CSL_UART9_BASE},
+ {CSL_WKUP_UART0_BASE, 0, 0, 0, 0, 0, 0, 0, 0, 0},
+ {CSL_MCU_UART0_BASE, 0, 0, 0, 0, 0, 0, 0, 0, 0}};
+
+/**
+ * \brief Returns base address of given I2C instance
+ *
+ * \param instNum [IN] I2C instance
+ *
+ * \param domain [IN] Domain of I2C controller
+ * BOARD_SOC_DOMAIN_MAIN - Main Domain
+ * BOARD_SOC_DOMAIN_WKUP - Wakeup domain
+ * BOARD_SOC_DOMAIN_MCU - MCU domain
+ *
+ * \return Valid base address in case of success or 0
+ *
+ */
+static uint32_t Board_getI2cBaseAddr(uint8_t instNum,
+ uint8_t domain)
+{
+ uint32_t baseAddr = 0;
+
+ if((instNum < I2C_HWIP_MAX_CNT) &&
+ (domain <= BOARD_SOC_DOMAIN_MCU))
+ {
+ baseAddr = gBoardI2cBaseAddr[domain][instNum];
+ }
+
+ return (baseAddr);
+}
+
+/**
+ * \brief Returns base address of given UART instance
+ *
+ * \param instNum [IN] UART instance
+ *
+ * \param domain [IN] Domain of UART controller
+ * BOARD_SOC_DOMAIN_MAIN - Main Domain
+ * BOARD_SOC_DOMAIN_WKUP - Wakeup domain
+ * BOARD_SOC_DOMAIN_MCU - MCU domain
+ *
+ * \return Valid base address in case of success or 0
+ *
+ */
+static uint32_t Board_getUartBaseAddr(uint8_t instNum,
+ uint8_t domain)
+{
+ uint32_t baseAddr = 0;
+
+ if((instNum < CSL_UART_MAIN_CNT) &&
+ (domain <= BOARD_SOC_DOMAIN_MCU))
+ {
+ baseAddr = gBoardUartBaseAddr[domain][instNum];
+ }
+
+ return (baseAddr);
+}
+
+/**
+ * \brief This function initializes the default UART instance for use for
+ * console operations.
+ *
+ * \return Board_STATUS in case of success or appropriate error code.
+ *
+ */
+Board_STATUS Board_uartStdioInit(void)
+{
+ UART_HwAttrs uart_cfg;
+ uint32_t uartInst;
+ uint32_t uartBaseAddr;
+ uint32_t socDomainUART;
+ uint32_t socDomainCore;
+
+#ifdef BUILD_MCU
+ CSL_ArmR5CPUInfo info;
+
+ CSL_armR5GetCpuID(&info);
+ if (info.grpId != (uint32_t)CSL_ARM_R5_CLUSTER_GROUP_ID_0)
+ {
+ /* Main R5 cores will use main domain UART instances */
+ socDomainUART = BOARD_SOC_DOMAIN_MAIN;
+ uartInst = gBoardInitParams.uartInst;
+ }
+ else
+ {
+ socDomainUART = gBoardInitParams.uartSocDomain;
+ if(socDomainUART == BOARD_SOC_DOMAIN_MCU)
+ {
+ uartInst = BOARD_MCU_UART_INSTANCE;
+ }
+ else
+ {
+ uartInst = gBoardInitParams.uartInst;
+ }
+ }
+#else
+ socDomainUART = gBoardInitParams.uartSocDomain;
+ uartInst = gBoardInitParams.uartInst;
+#endif
+
+ socDomainCore = Board_getSocDomain();
+
+ /* Disable the UART interrupt */
+ UART_socGetInitCfg(uartInst, &uart_cfg);
+
+ if(socDomainUART != socDomainCore)
+ {
+ uartBaseAddr = Board_getUartBaseAddr(uartInst, socDomainUART);
+ if(uartBaseAddr != 0)
+ {
+ gUARTBaseAddr = uart_cfg.baseAddr;
+ uart_cfg.baseAddr = uartBaseAddr;
+ }
+ else
+ {
+ return BOARD_INVALID_PARAM;
+ }
+
+ gUARTClkFreq = uart_cfg.frequency;
+ if(socDomainUART == BOARD_SOC_DOMAIN_MAIN)
+ {
+ uart_cfg.frequency = BOARD_UART_CLK_MAIN;
+ }
+ else
+ {
+ uart_cfg.frequency = BOARD_UART_CLK_WKUP;
+ }
+ }
+
+ uart_cfg.enableInterrupt = false;
+ UART_socSetInitCfg(uartInst, &uart_cfg);
+
+ UART_stdioInit(uartInst);
+
+ return BOARD_SOK;
+}
+
+/**
+ * \brief This function is to get the i2c handle of the requested
+ * instance of the specifed domain
+ *
+ * \param domainType [IN] Domain of I2C controller
+ * BOARD_SOC_DOMAIN_MAIN - Main Domain
+ * BOARD_SOC_DOMAIN_WKUP - Wakeup domain
+ * BOARD_SOC_DOMAIN_MCU - MCU domain
+ *
+ * \param i2cInst [IN] I2C instance
+ *
+ * \return Valid I2C handle in case of success or NULL in case of failure.
+ *
+ */
+I2C_Handle Board_getI2CHandle(uint8_t domainType,
+ uint32_t i2cInst)
+{
+ Board_STATUS status;
+ Board_I2cInitCfg_t i2cCfg;
+
+ i2cCfg.i2cInst = i2cInst;
+ i2cCfg.socDomain = domainType;
+ i2cCfg.enableIntr = false;
+ Board_setI2cInitConfig(&i2cCfg);
+
+ status = Board_i2cInit();
+ if(status != BOARD_SOK)
+ {
+ return NULL;
+ }
+
+ return (gBoardI2cObj[i2cInst].i2cHandle);
+}
+
+/**
+ * \brief This function is to release the i2c handle acquired using
+ * Board_getI2CHandle function
+ *
+ * \param hI2c [IN] I2C handle
+ *
+ * \return Board_STATUS in case of success or appropriate error code.
+ *
+ */
+Board_STATUS Board_releaseI2CHandle(I2C_Handle hI2c)
+{
+ Board_STATUS status = BOARD_FAIL;
+ I2C_HwAttrs i2c_cfg;
+ uint32_t coreDomain;
+ uint32_t i2cInst;
+
+ if(hI2c != NULL)
+ {
+ for (i2cInst = 0; i2cInst < BOARD_I2C_PORT_CNT; i2cInst++)
+ {
+ if((hI2c == gBoardI2cObj[i2cInst].i2cHandle))
+ {
+ break;
+ }
+ }
+
+ if(i2cInst != BOARD_I2C_PORT_CNT)
+ {
+ I2C_close(gBoardI2cObj[i2cInst].i2cHandle);
+ gBoardI2cObj[i2cInst].i2cHandle = NULL;
+
+ coreDomain = Board_getSocDomain();
+
+ if(gBoardI2cObj[i2cInst].i2cDomain != coreDomain)
+ {
+ I2C_socGetInitCfg(i2cInst, &i2c_cfg);
+ i2c_cfg.baseAddr = gBoardI2cObj[i2cInst].i2cBaseAddr;
+ I2C_socSetInitCfg(i2cInst, &i2c_cfg);
+ }
+
+ status = BOARD_SOK;
+ }
+ }
+
+ return status;
+}
+
+/**
+ * \brief This function initializes the i2c instance set using
+ * Board_setI2cInitConfig API.
+ *
+ * \return Board_STATUS in case of success or appropriate error code.
+ *
+ */
+Board_STATUS Board_i2cInit(void)
+{
+ I2C_Params i2cParams;
+ I2C_HwAttrs i2c_cfg;
+ uint32_t i2cInst;
+ uint32_t i2cBaseAddr;
+ uint32_t i2cDomain;
+ uint32_t coreDomain;
+
+ i2cInst = gBoardI2cInitCfg.i2cInst;
+ i2cDomain = gBoardI2cInitCfg.socDomain;
+
+ if(gBoardI2cObj[i2cInst].i2cHandle == NULL)
+ {
+ coreDomain = Board_getSocDomain();
+
+ I2C_init();
+ I2C_socGetInitCfg(i2cInst, &i2c_cfg);
+
+ if(i2cDomain != coreDomain)
+ {
+ i2cBaseAddr = Board_getI2cBaseAddr(i2cInst, i2cDomain);
+ if(i2cBaseAddr != 0)
+ {
+ gBoardI2cObj[i2cInst].i2cBaseAddr = i2c_cfg.baseAddr;
+ i2c_cfg.baseAddr = i2cBaseAddr;
+ }
+ else
+ {
+ return BOARD_INVALID_PARAM;
+ }
+ }
+
+ i2c_cfg.enableIntr = gBoardI2cInitCfg.enableIntr;
+
+ I2C_socSetInitCfg(i2cInst, &i2c_cfg);
+ I2C_Params_init(&i2cParams);
+
+ gBoardI2cObj[i2cInst].i2cHandle = I2C_open(i2cInst, &i2cParams);
+ if (gBoardI2cObj[i2cInst].i2cHandle == NULL)
+ {
+ return BOARD_I2C_OPEN_FAIL;
+ }
+
+ gBoardI2cObj[i2cInst].i2cDomain = i2cDomain;
+ gBoardI2cObj[i2cInst].instNum = i2cInst;
+ }
+ else
+ {
+ if(gBoardI2cObj[i2cInst].i2cDomain != i2cDomain)
+ {
+ return BOARD_I2C_OPEN_FAIL;
+ }
+ }
+
+ return BOARD_SOK;
+}
+
+/**
+ * \brief This function is used to close the initialized board I2C handle.
+ */
+Board_STATUS Board_i2cDeInit(void)
+{
+ uint32_t coreDomain;
+ I2C_HwAttrs i2c_cfg;
+ uint32_t i2cInst;
+
+ i2cInst = gBoardI2cInitCfg.i2cInst;
+
+ if(gBoardI2cObj[i2cInst].i2cHandle != NULL)
+ {
+ I2C_close(gBoardI2cObj[i2cInst].i2cHandle);
+ gBoardI2cObj[i2cInst].i2cHandle = NULL;
+
+ coreDomain = Board_getSocDomain();
+
+ if(gBoardI2cObj[i2cInst].i2cDomain != coreDomain)
+ {
+ I2C_socGetInitCfg(i2cInst, &i2c_cfg);
+ i2c_cfg.baseAddr = gBoardI2cObj[i2cInst].i2cBaseAddr;
+ I2C_socSetInitCfg(i2cInst, &i2c_cfg);
+ }
+ }
+
+ return BOARD_SOK;
+}
+
+/**
+ * \brief This function is used to de-initialize board UART handles.
+ */
+Board_STATUS Board_uartDeInit(void)
+{
+ UART_HwAttrs uart_cfg;
+ uint32_t socDomainCore;
+
+ UART_stdioDeInit();
+
+ socDomainCore = Board_getSocDomain();
+
+ if(gBoardInitParams.uartSocDomain != socDomainCore)
+ {
+ UART_socGetInitCfg(gBoardInitParams.uartInst, &uart_cfg);
+ uart_cfg.baseAddr = gUARTBaseAddr;
+ uart_cfg.frequency = gUARTClkFreq;
+ UART_socSetInitCfg(gBoardInitParams.uartInst, &uart_cfg);
+ }
+
+ return BOARD_SOK;
+}
diff --git a/packages/ti/board/src/j721s2_evm/board_mmr.c b/packages/ti/board/src/j721s2_evm/board_mmr.c
--- /dev/null
@@ -0,0 +1,222 @@
+/******************************************************************************
+ * Copyright (c) 2021 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *****************************************************************************/
+/**
+ * \file board_mmr.c
+ *
+ * \brief MMR configuration file
+ *
+ * This file contains the function to unlock the MMR registers
+ *
+ */
+
+#include "board_internal.h"
+#include <ti/csl/soc/j721s2/src/cslr_wkup_ctrl_mmr.h>
+
+/**
+ * \brief Configures kick registers to lock/unlock MMR access
+ *
+ * \param kick0 [IN] KICK0 register address
+ * \param kick1 [IN] KICK1 register address
+ * \param lockCtrl [IN] Register lock/unlock control
+ * 0 - Unlocks the MMR register write access
+ * 1 - Locks the MMR register write access
+ *
+ * \return BOARD_SOK - MMR kick register configurations successful
+ * BOARD_FAIL - MMR kick register configurations failed
+ */
+static Board_STATUS MMR_config(uint32_t *kick0, uint32_t *kick1, uint8_t lockCtrl)
+{
+ /* Initialize the status variable */
+ Board_STATUS status = BOARD_SOK;
+
+ if(lockCtrl == 0)
+ {
+ /* If either of the kick lock registers are locked */
+ if(!(*kick0 & 0x01))
+ {
+ /* Unlock the partition by writing the unlock values to the kick lock registers */
+ *kick0 = BOARD_KICK0_UNLOCK_VAL;
+ *kick1 = BOARD_KICK1_UNLOCK_VAL;
+ }
+
+ /* Confirm both the kick registers are unlocked */
+ if(!(*kick0 & 0x01))
+ {
+ status = BOARD_FAIL;
+ }
+ }
+ else
+ {
+ /* Lock the partition by writing the lock values to the kick lock registers */
+ *kick0 = BOARD_KICK0_LOCK_VAL;
+ *kick1 = BOARD_KICK1_LOCK_VAL;
+
+ /* Confirm both the kick registers are locked */
+ if(*kick0 & 0x01)
+ {
+ status = BOARD_FAIL;
+ }
+ }
+
+ return status;
+}
+
+/**
+ * \brief Unlocks MMR registers
+ *
+ * \param lockCtrl [IN] Register lock/unlock control
+ * 0 - Unlocks the MMR register write access
+ * 1 - Locks the MMR register write access
+ *
+ * \return BOARD_SOK - MMR kick register configurations successful
+ * BOARD_FAIL - MMR kick register configurations failed
+ */
+Board_STATUS Board_ctrlMMR(uint8_t lockCtrl)
+{
+ Board_STATUS status = BOARD_SOK;
+ uint32_t *lock0;
+ uint32_t *lock1;
+
+ Board_setRATCfg();
+
+ /* Unlock MAIN MMR registers */
+ lock0 = (uint32_t *)(BOARD_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_LOCK0_KICK0);
+ lock1 = (uint32_t *)(BOARD_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_LOCK0_KICK1);
+ status = MMR_config(lock0, lock1, lockCtrl);
+
+ lock0 = (uint32_t *)(BOARD_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_LOCK1_KICK0);
+ lock1 = (uint32_t *)(BOARD_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_LOCK1_KICK1);
+ status |= MMR_config(lock0, lock1, lockCtrl);
+
+ lock0 = (uint32_t *)(BOARD_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_LOCK2_KICK0);
+ lock1 = (uint32_t *)(BOARD_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_LOCK2_KICK1);
+ status |= MMR_config(lock0, lock1, lockCtrl);
+
+ lock0 = (uint32_t *)(BOARD_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_LOCK3_KICK0);
+ lock1 = (uint32_t *)(BOARD_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_LOCK3_KICK1);
+ status |= MMR_config(lock0, lock1, lockCtrl);
+
+ lock0 = (uint32_t *)(BOARD_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_LOCK5_KICK0);
+ lock1 = (uint32_t *)(BOARD_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_LOCK5_KICK1);
+ status |= MMR_config(lock0, lock1, lockCtrl);
+
+ lock0 = (uint32_t *)(BOARD_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_LOCK7_KICK0);
+ lock1 = (uint32_t *)(BOARD_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_LOCK7_KICK1);
+ status |= MMR_config(lock0, lock1, lockCtrl);
+
+ /* Unlock wakeup MMR registers */
+ lock0 = (uint32_t *)(CSL_WKUP_CTRL_MMR0_CFG0_BASE + CSL_WKUP_CTRL_MMR_CFG0_LOCK0_KICK0);
+ lock1 = (uint32_t *)(CSL_WKUP_CTRL_MMR0_CFG0_BASE + CSL_WKUP_CTRL_MMR_CFG0_LOCK0_KICK1);
+ status |= MMR_config(lock0, lock1, lockCtrl);
+
+ lock0 = (uint32_t *)(CSL_WKUP_CTRL_MMR0_CFG0_BASE + CSL_WKUP_CTRL_MMR_CFG0_LOCK1_KICK0);
+ lock1 = (uint32_t *)(CSL_WKUP_CTRL_MMR0_CFG0_BASE + CSL_WKUP_CTRL_MMR_CFG0_LOCK1_KICK1);
+ status |= MMR_config(lock0, lock1, lockCtrl);
+
+ lock0 = (uint32_t *)(CSL_WKUP_CTRL_MMR0_CFG0_BASE + CSL_WKUP_CTRL_MMR_CFG0_LOCK2_KICK0);
+ lock1 = (uint32_t *)(CSL_WKUP_CTRL_MMR0_CFG0_BASE + CSL_WKUP_CTRL_MMR_CFG0_LOCK2_KICK1);
+ status |= MMR_config(lock0, lock1, lockCtrl);
+
+ lock0 = (uint32_t *)(CSL_WKUP_CTRL_MMR0_CFG0_BASE + CSL_WKUP_CTRL_MMR_CFG0_LOCK3_KICK0);
+ lock1 = (uint32_t *)(CSL_WKUP_CTRL_MMR0_CFG0_BASE + CSL_WKUP_CTRL_MMR_CFG0_LOCK3_KICK1);
+ status |= MMR_config(lock0, lock1, lockCtrl);
+
+ lock0 = (uint32_t *)(CSL_WKUP_CTRL_MMR0_CFG0_BASE + CSL_WKUP_CTRL_MMR_CFG0_LOCK4_KICK0);
+ lock1 = (uint32_t *)(CSL_WKUP_CTRL_MMR0_CFG0_BASE + CSL_WKUP_CTRL_MMR_CFG0_LOCK4_KICK1);
+ status |= MMR_config(lock0, lock1, lockCtrl);
+
+ lock0 = (uint32_t *)(CSL_WKUP_CTRL_MMR0_CFG0_BASE + CSL_WKUP_CTRL_MMR_CFG0_LOCK5_KICK0);
+ lock1 = (uint32_t *)(CSL_WKUP_CTRL_MMR0_CFG0_BASE + CSL_WKUP_CTRL_MMR_CFG0_LOCK5_KICK1);
+ status |= MMR_config(lock0, lock1, lockCtrl);
+
+ lock0 = (uint32_t *)(CSL_WKUP_CTRL_MMR0_CFG0_BASE + CSL_WKUP_CTRL_MMR_CFG0_LOCK6_KICK0);
+ lock1 = (uint32_t *)(CSL_WKUP_CTRL_MMR0_CFG0_BASE + CSL_WKUP_CTRL_MMR_CFG0_LOCK6_KICK1);
+ status |= MMR_config(lock0, lock1, lockCtrl);
+
+ lock0 = (uint32_t *)(CSL_WKUP_CTRL_MMR0_CFG0_BASE + CSL_WKUP_CTRL_MMR_CFG0_LOCK7_KICK0);
+ lock1 = (uint32_t *)(CSL_WKUP_CTRL_MMR0_CFG0_BASE + CSL_WKUP_CTRL_MMR_CFG0_LOCK7_KICK1);
+ status |= MMR_config(lock0, lock1, lockCtrl);
+
+ /* Unlock MCU MMR registers */
+ lock0 = (uint32_t *)(CSL_MCU_CTRL_MMR0_CFG0_BASE + CSL_MCU_CTRL_MMR_CFG0_LOCK0_KICK0);
+ lock1 = (uint32_t *)(CSL_MCU_CTRL_MMR0_CFG0_BASE + CSL_MCU_CTRL_MMR_CFG0_LOCK0_KICK1);
+ status |= MMR_config(lock0, lock1, lockCtrl);
+
+ lock0 = (uint32_t *)(CSL_MCU_CTRL_MMR0_CFG0_BASE + CSL_MCU_CTRL_MMR_CFG0_LOCK1_KICK0);
+ lock1 = (uint32_t *)(CSL_MCU_CTRL_MMR0_CFG0_BASE + CSL_MCU_CTRL_MMR_CFG0_LOCK1_KICK1);
+ status |= MMR_config(lock0, lock1, lockCtrl);
+
+ lock0 = (uint32_t *)(CSL_MCU_CTRL_MMR0_CFG0_BASE + CSL_MCU_CTRL_MMR_CFG0_LOCK2_KICK0);
+ lock1 = (uint32_t *)(CSL_MCU_CTRL_MMR0_CFG0_BASE + CSL_MCU_CTRL_MMR_CFG0_LOCK2_KICK1);
+ status |= MMR_config(lock0, lock1, lockCtrl);
+
+ lock0 = (uint32_t *)(CSL_MCU_CTRL_MMR0_CFG0_BASE + CSL_MCU_CTRL_MMR_CFG0_LOCK3_KICK0);
+ lock1 = (uint32_t *)(CSL_MCU_CTRL_MMR0_CFG0_BASE + CSL_MCU_CTRL_MMR_CFG0_LOCK3_KICK1);
+ status |= MMR_config(lock0, lock1, lockCtrl);
+
+ lock0 = (uint32_t *)(CSL_MCU_CTRL_MMR0_CFG0_BASE + CSL_MCU_CTRL_MMR_CFG0_LOCK4_KICK0);
+ lock1 = (uint32_t *)(CSL_MCU_CTRL_MMR0_CFG0_BASE + CSL_MCU_CTRL_MMR_CFG0_LOCK4_KICK1);
+ status |= MMR_config(lock0, lock1, lockCtrl);
+
+ Board_restoreRATCfg();
+
+ return status;
+}
+
+/**
+ * \brief Locks MMR registers
+ *
+ * \return Board_STATUS
+ */
+Board_STATUS Board_lockMMR(void)
+{
+ Board_STATUS status;
+
+ status = Board_ctrlMMR(1);
+
+ return status;
+}
+
+/**
+ * \brief Unlocks MMR registers
+ *
+ * \return Board_STATUS
+ */
+Board_STATUS Board_unlockMMR(void)
+{
+ Board_STATUS status;
+
+ status = Board_ctrlMMR(0);
+
+ return status;
+}
diff --git a/packages/ti/board/src/j721s2_evm/board_pinmux.c b/packages/ti/board/src/j721s2_evm/board_pinmux.c
--- /dev/null
@@ -0,0 +1,430 @@
+/******************************************************************************
+ * Copyright (c) 2021 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *****************************************************************************/
+
+/**
+ * \file board_pinmux.c
+ *
+ * \brief This file enables pinmux for the board
+ *
+ */
+
+#include <ti/csl/soc.h>
+#include "board_internal.h"
+#include "board_pinmux.h"
+
+static Board_PinmuxConfig_t gBoardPinmuxCfg = {BOARD_PINMUX_CUSTOM};
+
+/**
+ * \brief Gets base address of padconfig registers
+ *
+ * \param domain [IN] SoC domain for pinmux
+ * \n BOARD_SOC_DOMAIN_MAIN - Main domain
+ * \n BOARD_SOC_DOMAIN_WKUP - Wakeup domain
+ *
+ * \return Valid address in case success or 0 in case of failure
+ */
+static uint32_t Board_pinmuxGetBaseAddr(uint8_t domain)
+{
+ uint32_t baseAddr;
+
+ switch(domain)
+ {
+ case BOARD_SOC_DOMAIN_MAIN:
+ baseAddr = BOARD_MAIN_PMUX_CTRL_ADDR;
+ break;
+ case BOARD_SOC_DOMAIN_WKUP:
+ baseAddr = BOARD_WKUP_PMUX_CTRL_ADDR;
+ break;
+ default:
+ baseAddr = 0;
+ break;
+ }
+
+ return baseAddr;
+}
+
+/**
+ * \brief Writes data into padconfig registers
+ *
+ * \param domain [IN] SoC domain for pinmux
+ * \n BOARD_SOC_DOMAIN_MAIN - Main domain
+ * \n BOARD_SOC_DOMAIN_WKUP - Wakeup domain
+ *
+ * \return Valid address in case success or 0 in case of failure
+ */
+static void Board_pinmuxWriteReg(uint8_t domain,
+ uint32_t baseAddr,
+ uint32_t regVal)
+{
+ /* Write PAD config MMR register */
+ HW_WR_REG32(baseAddr, regVal);
+}
+
+/**
+ * \brief Sets pinmux mode for a pin in main domain
+ *
+ * Only pinmux mode is updated by this function. Other values of
+ * padconfig register remains unchanged after this function call.
+ *
+ * \param offset [IN] Pad config offset of the pin
+ * \param mode [IN] Pad config mux mode.
+ *
+ * \return None
+ */
+void Board_pinMuxSetMode(uint32_t offset, uint32_t mode)
+{
+ uint32_t baseAddr;
+ uint32_t regVal;
+
+ Board_unlockMMR();
+
+ baseAddr = Board_pinmuxGetBaseAddr(BOARD_SOC_DOMAIN_MAIN);
+
+ regVal = HW_RD_REG32((baseAddr + offset));
+ regVal &= ~(BOARD_MODE_PIN_MASK);
+ mode &= BOARD_MODE_PIN_MASK;
+ regVal |= mode;
+ Board_pinmuxWriteReg(BOARD_SOC_DOMAIN_MAIN,
+ (baseAddr + offset),
+ regVal);
+}
+
+/**
+ * \brief Sets pinmux mode for a pin in wake-up domain
+ *
+ * Only pinmux mode is updated by this function. Other values of
+ * padconfig register remains unchanged after this function call.
+ *
+ * \param offset [IN] Pad config offset of the pin
+ * \param mode [IN] Pad config mux mode.
+ *
+ * \return None
+ */
+void Board_pinMuxSetModeWkup(uint32_t offset, uint32_t mode)
+{
+ uint32_t baseAddr;
+ uint32_t regVal;
+
+ Board_unlockMMR();
+
+ baseAddr = Board_pinmuxGetBaseAddr(BOARD_SOC_DOMAIN_WKUP);
+
+ regVal = HW_RD_REG32((baseAddr + offset));
+ regVal &= ~(BOARD_MODE_PIN_MASK);
+ mode &= BOARD_MODE_PIN_MASK;
+ regVal |= mode;
+ Board_pinmuxWriteReg(BOARD_SOC_DOMAIN_WKUP,
+ (baseAddr + offset),
+ regVal);
+}
+
+/**
+ * \brief Sets padconfig register of a pin at given offset
+ *
+ * Configures whole padconfig register of the pin at given offset
+ * with the value in 'muxData'.
+ *
+ * \param domain [IN] SoC domain for pinmux
+ * \n BOARD_SOC_DOMAIN_MAIN - Main domain
+ * \n BOARD_SOC_DOMAIN_WKUP - Wakeup domain
+ *
+ * \param offset [IN] Pad config offset of the pin
+ * \param muxData [IN] Value to be written to padconfig register
+ *
+ * \return BOARD_SOK in case of success or appropriate error code
+ *
+ */
+Board_STATUS Board_pinmuxSetReg(uint8_t domain,
+ uint32_t offset,
+ uint32_t muxData)
+{
+ uint32_t baseAddr;
+ Board_STATUS status = BOARD_SOK;
+
+ Board_unlockMMR();
+
+ baseAddr = Board_pinmuxGetBaseAddr(domain);
+ if(baseAddr != 0)
+ {
+ Board_pinmuxWriteReg(domain,
+ (baseAddr + offset),
+ muxData);
+ }
+ else
+ {
+ status = BOARD_INVALID_PARAM;
+ }
+
+ return status;
+}
+
+/**
+ * \brief Gets padconfig register of a pin at given offset
+ *
+ * \param domain [IN] SoC domain for pinmux
+ * \n BOARD_SOC_DOMAIN_MAIN - Main domain
+ * \n BOARD_SOC_DOMAIN_WKUP - Wakeup domain
+ * \param offset [IN] Pad config offset of the pin
+ * \param muxData [OUT] Value of padconfig register
+ *
+ * \return BOARD_SOK in case of success or appropriate error code
+ *
+ */
+Board_STATUS Board_pinmuxGetReg(uint8_t domain,
+ uint32_t offset,
+ uint32_t *muxData)
+{
+ uint32_t baseAddr;
+ Board_STATUS status = BOARD_SOK;
+
+ baseAddr = Board_pinmuxGetBaseAddr(domain);
+ if(baseAddr != 0)
+ {
+ *muxData = HW_RD_REG32((baseAddr + offset));
+ }
+ else
+ {
+ status = BOARD_INVALID_PARAM;
+ }
+
+ return status;
+}
+
+/**
+ * \brief Sets the board pinmux configuration.
+ *
+ * There are multiple addon cards that can connected to baseboard and
+ * multiple addon cards can be connected to one expansion connector.
+ * Pinmux configured through Board_init will be set to a default
+ * combination of the boards which can be changed using this function.
+ *
+ * \n Usage:
+ * \n - Call Board_pinmuxGetCfg to get default pinmux config
+ * \n - Call Board_pinmuxSetCfg to change pinmux config
+ * \n - Call Board_init with pinmux flag to apply the updated pinmux config
+ *
+ * \param pinmuxCfg [IN] Pinmux configurations
+ *
+ * \return BOARD_SOK in case of success or appropriate error code
+ *
+ */
+Board_STATUS Board_pinmuxSetCfg(Board_PinmuxConfig_t *pinmuxCfg)
+{
+ gBoardPinmuxCfg = *pinmuxCfg;
+
+ return BOARD_SOK;
+}
+
+/**
+ * \brief Gets the board pinmux configuration.
+ *
+ * There are multiple addon cards that can connected to baseboard and
+ * multiple addon cards can be connected to one expansion connector.
+ * Pinmux configured through Board_init will be set to a default
+ * combination of the boards which can be read using this function.
+ *
+ * \param pinmuxCfg [IN] Pinmux configurations
+ *
+ * \return BOARD_SOK in case of success or appropriate error code
+ *
+ */
+Board_STATUS Board_pinmuxGetCfg(Board_PinmuxConfig_t *pinmuxCfg)
+{
+ *pinmuxCfg = gBoardPinmuxCfg;
+
+ return BOARD_SOK;
+}
+
+/**
+ * \brief Board pinmuxing update function
+ *
+ * Provides the option to configure/update the pinmux.
+ * This function can be used to change the pinmux set by
+ * Board_init by default.
+ *
+ * \param pinmuxData [IN] Pinmux data structure
+ * \param domain [IN] SoC domain for pinmux
+ * \n BOARD_SOC_DOMAIN_MAIN - Main domain
+ * \n BOARD_SOC_DOMAIN_WKUP - Wakeup domain
+ *
+ * \return BOARD_SOK in case of success or appropriate error code
+ *
+ */
+Board_STATUS Board_pinmuxUpdate (pinmuxBoardCfg_t *pinmuxData,
+ uint32_t domain)
+{
+ pinmuxModuleCfg_t *pModuleData = NULL;
+ pinmuxPerCfg_t *pInstanceData = NULL;
+ int32_t i, j, k;
+ uint32_t rdRegVal;
+ uint32_t baseAddr;
+ Board_STATUS status = BOARD_SOK;
+
+ Board_unlockMMR();
+
+ /* MAIN domain pinmux needs RAT configuration for C66x core. */
+ if(domain == BOARD_SOC_DOMAIN_MAIN)
+ {
+ Board_setRATCfg();
+ }
+
+ baseAddr = Board_pinmuxGetBaseAddr(domain);
+ if(baseAddr != 0)
+ {
+ for(i = 0; PINMUX_END != pinmuxData[i].moduleId; i++)
+ {
+ pModuleData = pinmuxData[i].modulePinCfg;
+ for(j = 0; (PINMUX_END != pModuleData[j].modInstNum); j++)
+ {
+ if(pModuleData[j].doPinConfig == TRUE)
+ {
+ pInstanceData = pModuleData[j].instPins;
+ for(k = 0; (PINMUX_END != pInstanceData[k].pinOffset); k++)
+ {
+ rdRegVal = HW_RD_REG32((baseAddr + pInstanceData[k].pinOffset));
+ rdRegVal = (rdRegVal & BOARD_PINMUX_BIT_MASK);
+ Board_pinmuxWriteReg(domain,
+ (baseAddr + pInstanceData[k].pinOffset),
+ (pInstanceData[k].pinSettings));
+ }
+ }
+ }
+ }
+ }
+ else
+ {
+ status = BOARD_INVALID_PARAM;
+ }
+
+ if(domain == BOARD_SOC_DOMAIN_MAIN)
+ {
+ /* Clear the RAT configuration to allow applications to use the region */
+ Board_restoreRATCfg();
+ }
+
+ return status;
+}
+
+/**
+ * \brief Board pinmuxing enable function
+ *
+ * Enables pinmux for the board interfaces. Pin mux is done based
+ * on the default/primary functionality of the board. Any pins shared by
+ * multiple interfaces need to be reconfigured to access the secondary
+ * functionality.
+ *
+ * \param void
+ *
+ * \return BOARD_SOK in case of success or appropriate error code
+ *
+ */
+Board_STATUS Board_pinmuxConfig (void)
+{
+ Board_STATUS status = BOARD_SOK;
+
+ /* Pinmux for baseboard */
+ Board_pinmuxUpdate(gJ721S2_MainPinmuxData,
+ BOARD_SOC_DOMAIN_MAIN);
+ Board_pinmuxUpdate(gJ721S2_WkupPinmuxData,
+ BOARD_SOC_DOMAIN_WKUP);
+
+ return status;
+}
+
+/**
+ * \brief Board pinmuxing enable function for main domain
+ *
+ * Enables pinmux for the board interfaces connected to main domain.
+ * Pin mux is done based on the default/primary functionality of the board.
+ * Any pins shared by multiple interfaces need to be reconfigured to access
+ * the secondary functionality.
+ *
+ * \param void
+ *
+ * \return BOARD_SOK in case of success or appropriate error code
+ *
+ */
+Board_STATUS Board_pinmuxConfigMain (void)
+{
+ Board_STATUS status = BOARD_SOK;
+
+ /* Pinmux for baseboard */
+ status = Board_pinmuxUpdate(gJ721S2_MainPinmuxData,
+ BOARD_SOC_DOMAIN_MAIN);
+
+ return status;
+}
+
+/**
+ * \brief Board pinmuxing enable function for wakeup/mcu domain
+ *
+ * Enables pinmux for the board interfaces connected to wakeup/mcu domain.
+ * Pin mux is done based on the default/primary functionality of the board.
+ * Any pins shared by multiple interfaces need to be reconfigured to access
+ * the secondary functionality.
+ *
+ * \param void
+ *
+ * \return BOARD_SOK in case of success or appropriate error code
+ *
+ */
+Board_STATUS Board_pinmuxConfigWkup (void)
+{
+ Board_STATUS status = BOARD_SOK;
+
+ /* Pinmux for baseboard */
+ status = Board_pinmuxUpdate(gJ721S2_WkupPinmuxData,
+ BOARD_SOC_DOMAIN_WKUP);
+
+ return status;
+}
+
+/**
+ * \brief Board UART Tx pinmux config function
+ *
+ * Enables pinmux for UART Tx lines
+ *
+ * \param void
+ *
+ * \return None
+ *
+ */
+void Board_uartTxPinmuxConfig(void)
+{
+ /* Unlock partition lock kick */
+ HW_WR_REG32(BOARD_MCU_UART_TX_LOCK_KICK_ADDR, BOARD_KICK0_UNLOCK_VAL);
+ HW_WR_REG32(BOARD_MCU_UART_TX_LOCK_KICK_ADDR + 4U, BOARD_KICK1_UNLOCK_VAL);
+
+ /* Configure pinmux for UART Tx pin */
+ HW_WR_REG32(BOARD_MCU_UART_TX_PINMUX_ADDR, BOARD_MCU_UART_TX_PINMUX_VAL);
+}
diff --git a/packages/ti/board/src/j721s2_evm/board_pll.c b/packages/ti/board/src/j721s2_evm/board_pll.c
--- /dev/null
@@ -0,0 +1,346 @@
+/******************************************************************************
+ * Copyright (c) 2021 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *****************************************************************************/
+
+/**
+ * \file board_pll.c
+ *
+ * \brief Board pll configurations
+ *
+ */
+
+#include "board_internal.h"
+#include "board_pll.h"
+#include <ti/drv/sciclient/sciclient.h>
+
+static Board_PllClkCfg_t gBoardPllClkCfgMcu[] =
+{
+ { TISCI_DEV_MCU_MCAN0,
+ TISCI_DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT2_CLK,
+ 80000000
+ }, //MCU_PLL1_HSDIV2_CLKOUT
+ { TISCI_DEV_MCU_UART0,
+ TISCI_DEV_MCU_UART0_FCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT3_CLK,
+ 96000000
+ }, //MCU_PLL1_HSDIV3_CLKOUT,
+ { TISCI_DEV_MCU_FSS0_OSPI_0,
+ TISCI_DEV_MCU_FSS0_OSPI_0_OSPI_RCLK_CLK,
+ 133333333
+ }, //MCU_PLL1_HSDIV4_CLKOUT
+ { TISCI_DEV_MCU_FSS0_OSPI_1,
+ TISCI_DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK,
+ 133333333
+ }, //MCU_PLL1_HSDIV4_CLKOUT
+ /* MCU PLL2 Clockout */
+ { TISCI_DEV_MCU_CPSW0,
+ TISCI_DEV_MCU_CPSW0_RGMII_MHZ_250_CLK,
+ 250000000
+ }, //MCU_PLL2_HSDIV0_CLKOUT
+ { TISCI_DEV_MCU_CPSW0,
+ TISCI_DEV_MCU_CPSW0_CPTS_RFT_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT1_CLK,
+ 200000000
+ }, //MCU_PLL2_HSDIV1_CLKOUT
+ { TISCI_DEV_MCU_MCAN0,
+ TISCI_DEV_MCU_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MCU_2_HSDIVOUT3_CLK,
+ 80000000
+ }, //MCU_PLL2_HSDIV3_CLKOUT
+};
+
+static Board_PllClkCfg_t gBoardPllClkCfgMain[] =
+{
+ { TISCI_DEV_MMCSD0,
+ TISCI_DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT2_CLK,
+ 200000000
+ }, //MAIN_PLL0_HSDIV2_CLKOUT
+ { TISCI_DEV_MCAN0,
+ TISCI_DEV_MCAN0_MCANSS_CCLK_CLK_PARENT_HSDIV4_16FFT_MAIN_0_HSDIVOUT4_CLK,
+ 80000000
+ }, //MAIN_PLL0_HSDIV4_CLKOUT
+ { TISCI_DEV_MCSPI0,
+ TISCI_DEV_MCSPI0_CLKSPIREF_CLK,
+ 50000000
+ }, //MAIN_PLL0_HSDIV5_CLKOUT
+ { TISCI_DEV_MMCSD1,
+ TISCI_DEV_MMCSD1_EMMCSDSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_1_HSDIVOUT2_CLK,
+ 192000000
+ }, //MAIN_PLL1_HSDIV2_CLKOUT
+ { TISCI_DEV_MCU_UART0,
+ TISCI_DEV_MCU_UART0_FCLK_CLK_PARENT_POSTDIV3_16FFT_MAIN_1_HSDIVOUT5_CLK,
+ 192000000
+ }, //MAIN_PLL1_HSDIV5_CLKOUT
+ /* MAIN PLL2(PER1_PLL) Clockout */
+ { TISCI_DEV_MMCSD0,
+ TISCI_DEV_MMCSD0_EMMCSS_XIN_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT2_CLK,
+ 200000000
+ }, //MAIN_PLL2_HSDIV2_CLKOUTT
+ /* MAIN PLL4((AUDIO0_PLL) Clockout */
+ { TISCI_DEV_MCASP0,
+ TISCI_DEV_MCASP0_AUX_CLK_PARENT_HSDIV2_16FFT_MAIN_4_HSDIVOUT0_CLK,
+ 196608000
+ },//MAIN_PLL4_HSDIV0_CLKOUT
+ { TISCI_DEV_CPSW1,
+ TISCI_DEV_CPSW1_RGMII_MHZ_250_CLK,
+ 250000000
+ }, //MAIN_PLL3_HSDIV0_CLKOUT
+ { TISCI_DEV_CPSW1,
+ TISCI_DEV_CPSW1_CPTS_RFT_CLK,
+ 200000000
+ }, //MAIN_PLL3_HSDIV1_CLKOUT
+ { TISCI_DEV_CPSW1,
+ TISCI_DEV_CPSW1_CPPI_CLK_CLK,
+ 320000000
+ }, //MAIN_PLL1_HSDIV1_CLKOUT
+};
+
+/**
+ * \brief PLL clock enable
+ *
+ * This function is used to set the PLL Module clock frequency
+ *
+ * \param moduleId [IN] Module for which the state should be set.
+ * Refer Sciclient_PmDeviceIds in sciclient_fmwMsgParams.h
+ * \param clockId [IN] Clock Id for the module.
+ * Refer Sciclient_PmModuleClockIds in sciclient_fmwMsgParams.h
+ * \param clkRate [IN] Value of the clock frequency to be set
+ *
+ * \return int32_t
+ * CSL_PASS - on Success
+ * CSL_EFAIL - on Failure
+ *
+ */
+static int32_t Board_PLLSetModuleClkFreq(uint32_t modId,
+ uint32_t clkId,
+ uint64_t clkRate)
+{
+ uint32_t i = 0U;
+ int32_t status = CSL_EFAIL;
+ uint64_t respClkRate = 0;
+ uint32_t numParents = 0U;
+ uint32_t moduleClockParentChanged = 0U;
+ uint32_t clockStatus = 0U;
+ uint32_t origParent = 0U;
+ uint32_t foundParent = 0U;
+
+ /* Check if the clock is enabled or not */
+ status = Sciclient_pmModuleGetClkStatus(modId,
+ clkId,
+ &clockStatus,
+ SCICLIENT_SERVICE_WAIT_FOREVER);
+ if (status == CSL_PASS)
+ {
+ /* Get the number of parents for the clock */
+ status = Sciclient_pmGetModuleClkNumParent(modId,
+ clkId,
+ &numParents,
+ SCICLIENT_SERVICE_WAIT_FOREVER);
+ if ((status == CSL_PASS) && (numParents > 1U))
+ {
+ status = Sciclient_pmGetModuleClkParent(modId, clkId, &origParent,
+ SCICLIENT_SERVICE_WAIT_FOREVER);
+ }
+ }
+ if (status == CSL_PASS)
+ {
+ /* Disabling the clock */
+ status = Sciclient_pmModuleClkRequest(
+ modId,
+ clkId,
+ TISCI_MSG_VALUE_CLOCK_SW_STATE_UNREQ,
+ 0U,
+ SCICLIENT_SERVICE_WAIT_FOREVER);
+ }
+ if (status == CSL_PASS)
+ {
+ foundParent = 0U;
+ /* Try to loop and change parents of the clock */
+ for(i=0U;i<numParents;i++)
+ {
+ if (numParents > 1U)
+ {
+ /* Setting the new parent */
+ status = Sciclient_pmSetModuleClkParent(
+ modId,
+ clkId,
+ clkId+i+1,
+ SCICLIENT_SERVICE_WAIT_FOREVER);
+ /* Check if the clock can be set to desirable freq. */
+ if (status == CSL_PASS)
+ {
+ moduleClockParentChanged = 1U;
+ }
+ }
+ if (status == CSL_PASS)
+ {
+ status = Sciclient_pmQueryModuleClkFreq(modId,
+ clkId,
+ clkRate,
+ &respClkRate,
+ SCICLIENT_SERVICE_WAIT_FOREVER);
+ }
+ if ((status == CSL_PASS) && (respClkRate == clkRate))
+ {
+ foundParent = 1U;
+ break;
+ }
+ }
+ }
+
+ if ((status == CSL_PASS) && (numParents == 0U))
+ {
+ status = Sciclient_pmQueryModuleClkFreq(modId,
+ clkId,
+ clkRate,
+ &respClkRate,
+ SCICLIENT_SERVICE_WAIT_FOREVER);
+ if ((status == CSL_PASS) && (respClkRate == clkRate))
+ {
+ foundParent = 1U;
+ }
+ }
+
+ if (foundParent == 1U)
+ {
+ /* Set the clock at the desirable frequency*/
+ status = Sciclient_pmSetModuleClkFreq(
+ modId,
+ clkId,
+ clkRate,
+ TISCI_MSG_FLAG_CLOCK_ALLOW_FREQ_CHANGE,
+ SCICLIENT_SERVICE_WAIT_FOREVER);
+ }
+ else
+ {
+ status = CSL_EFAIL;
+ }
+ if ((status == CSL_PASS) &&
+ (clockStatus == TISCI_MSG_VALUE_CLOCK_SW_STATE_UNREQ))
+ {
+ /* Restore the clock again to original state */
+ status = Sciclient_pmModuleClkRequest(
+ modId,
+ clkId,
+ clockStatus,
+ 0U,
+ SCICLIENT_SERVICE_WAIT_FOREVER);
+ }
+ if ((status != CSL_PASS) && (moduleClockParentChanged == 1U))
+ {
+ /* Setting the original parent if failure */
+ status = Sciclient_pmSetModuleClkParent(
+ modId,
+ clkId,
+ origParent,
+ SCICLIENT_SERVICE_WAIT_FOREVER);
+ }
+ return status;
+}
+
+/**
+ * \brief Function to initialize module clock frequency
+ *
+ * \param moduleId [IN] Module for which the state should be set.
+ * Refer Sciclient_PmDeviceIds in sciclient_fmwMsgParams.h
+ * \param clockId [IN] Clock Id for the module.
+ * Refer Sciclient_PmModuleClockIds in sciclient_fmwMsgParams.h
+ * \param clkRate [IN] Value of the clock frequency to be set
+
+ * \return Board_STATUS
+ */
+Board_STATUS Board_PLLInit(uint32_t modId,
+ uint32_t clkId,
+ uint64_t clkRate)
+{
+ int32_t status = CSL_EFAIL;
+
+ status = Board_PLLSetModuleClkFreq(modId, clkId, clkRate);
+ if(status != CSL_PASS)
+ {
+ return BOARD_FAIL;
+ }
+
+ return BOARD_SOK;
+}
+
+/**
+ * \brief Function to initialize the MCU domain PLL clocks with default values
+ *
+ * \return Board_STATUS
+ */
+Board_STATUS Board_PLLInitMcu(void)
+{
+ Board_STATUS status = BOARD_SOK;
+ uint32_t index;
+ uint32_t loopCount;
+
+ loopCount = sizeof (gBoardPllClkCfgMcu)/sizeof(Board_PllClkCfg_t);
+
+ for (index = 0; index < loopCount; index++)
+ {
+ status = Board_PLLInit(gBoardPllClkCfgMcu[index].tisciDevID,
+ gBoardPllClkCfgMcu[index].tisciClkID,
+ gBoardPllClkCfgMcu[index].clkRate);
+ if(status != BOARD_SOK)
+ {
+ BOARD_DEBUG_LOG("Failed to set the PLL clock freq at index =%d\n\n",index);
+ }
+ }
+
+ return status;
+}
+
+/**
+ * \brief Function to initialize the MAIN domain PLL clocks with default values
+ *
+ * \return Board_STATUS
+ */
+Board_STATUS Board_PLLInitMain(void)
+{
+ Board_STATUS status = BOARD_SOK;
+ uint32_t index;
+ uint32_t loopCount;
+
+ loopCount = sizeof (gBoardPllClkCfgMain)/sizeof(Board_PllClkCfg_t);
+
+ for (index = 0; index < loopCount; index++)
+ {
+ status = Board_PLLInit(gBoardPllClkCfgMain[index].tisciDevID,
+ gBoardPllClkCfgMain[index].tisciClkID,
+ gBoardPllClkCfgMain[index].clkRate);
+ if(status != BOARD_SOK)
+ {
+ BOARD_DEBUG_LOG("Failed to set the PLL clock freq at index =%d\n\n",index);
+ }
+ }
+
+ return status;
+}
+
diff --git a/packages/ti/board/src/j721s2_evm/board_utils.c b/packages/ti/board/src/j721s2_evm/board_utils.c
--- /dev/null
@@ -0,0 +1,548 @@
+/******************************************************************************
+ * Copyright (c) 2021 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *****************************************************************************/
+
+/**
+ * \file board_utils.c
+ *
+ * \brief Implements multiple board utility functions
+ *
+ */
+
+#include <stdio.h>
+#include <string.h>
+#include <ti/csl/arch/csl_arch.h>
+#include "board_internal.h"
+#include "board_utils.h"
+#include "board_cfg.h"
+#include <ti/drv/mmcsd/MMCSD.h>
+#include <ti/drv/mmcsd/soc/MMCSD_soc.h>
+
+Board_DetectCfg_t gBoardDetCfg[BOARD_ID_MAX_BOARDS] =
+ {{BOARD_COMMON_EEPROM_I2C_INST, BOARD_GESI_EEPROM_SLAVE_ADDR, BOARD_SOC_DOMAIN_WKUP, "J7X-GESI-EXP"},
+ {BOARD_CSI2_EEPROM_I2C_INST, BOARD_CSI2_EEPROM_SLAVE_ADDR, BOARD_SOC_DOMAIN_MAIN, "J7X-FUSION2-CSI"},
+ {BOARD_COMMON_EEPROM_I2C_INST, BOARD_SOM_EEPROM_SLAVE_ADDR, BOARD_SOC_DOMAIN_WKUP, "J721EX-PM2-SOM"},
+ {BOARD_COMMON_EEPROM_I2C_INST, BOARD_CP_EEPROM_SLAVE_ADDR, BOARD_SOC_DOMAIN_WKUP, "J7X-BASE-CPB"}};
+
+Board_I2cInitCfg_t gBoardI2cInitCfg = {0, BOARD_SOC_DOMAIN_MAIN, 0};
+Board_initParams_t gBoardInitParams = {BOARD_UART_INSTANCE, BOARD_UART_SOC_DOMAIN, BOARD_PSC_DEVICE_MODE_NONEXCLUSIVE,
+ BOARD_MAIN_CLOCK_GROUP_ALL, BOARD_MCU_CLOCK_GROUP_ALL};
+
+/* Variables to store and restore the RAT configurations on DSP core */
+#if defined (_TMS320C6X)
+static uint32_t gRatOffsetHi;
+static uint32_t gRatOffsetLo;
+static uint32_t gRatCfg;
+#endif
+
+/**
+ * \brief Function to configure SD card voltage control gpio configuration.
+ *
+ * \param gpioValue [IN] GPIO pin value.
+ * 1 for GPIO pin high
+ * 0 for GPIO pin low
+ *
+ * \return BOARD_SOK in case of success or appropriate error code
+ *
+ */
+static void Board_sdVoltageCtrlGpioCfg(uint8_t gpioValue)
+{
+ uint32_t regVal;
+
+ /* Setting the GPIO direction to output */
+ regVal = HW_RD_REG32(CSL_GPIO0_BASE + 0x10);
+ regVal &= ~(0x01 << (BOARD_SDIO_1V8_EN_PIN_NUM % 32));
+ HW_WR_REG32((CSL_GPIO0_BASE + 0x10), regVal);
+
+ /* Setting the GPIO value */
+ regVal = HW_RD_REG32(CSL_GPIO0_BASE + 0x18);
+
+ if(gpioValue == 0)
+ {
+ regVal &= ~(0x01 << (BOARD_SDIO_1V8_EN_PIN_NUM % 32));
+ HW_WR_REG32((CSL_GPIO0_BASE + 0x18), regVal);
+ }
+ else
+ {
+ regVal |= (gpioValue << (BOARD_SDIO_1V8_EN_PIN_NUM % 32));
+ HW_WR_REG32((CSL_GPIO0_BASE + 0x18), regVal);
+ }
+}
+
+/**
+ * \brief Board ID read function
+ *
+ * \param info [IN] Board info structure
+ * \param boardID [IN] ID of the board to be detected
+ * \n BOARD_ID_GESI(0x0) - GESI Board
+ * \n BOARD_ID_FUSION2(0x1) - Fusion 2 Board
+ * \n BOARD_ID_SOM(0x2) - SoM Board
+ * \n BOARD_ID_CP(0x3) - CP Board
+ *
+ * \return BOARD_SOK in case of success or appropriate error code.
+ *
+ */
+Board_STATUS Board_getBoardData(Board_IDInfo_v2 *info, uint32_t boardID)
+{
+ Board_I2cInitCfg_t i2cCfg;
+ Board_STATUS status;
+
+ i2cCfg.i2cInst = gBoardDetCfg[boardID].i2cInst;
+ i2cCfg.socDomain = gBoardDetCfg[boardID].socDomain;
+ i2cCfg.enableIntr = false;
+ Board_setI2cInitConfig(&i2cCfg);
+
+ status = Board_getIDInfo_v2(info, gBoardDetCfg[boardID].slaveAddr);
+
+ return status;
+}
+
+/**
+ * \brief Board detect function
+ *
+ * Checks if the board with given 'boardID' is connected to the
+ * base board.
+ *
+ * \n Note: Board ID EEPROM should be programmed for this function
+ * to work properly.
+ *
+ * \param boardID [IN] ID of the board to be detected
+ * \n BOARD_ID_GESI(0x0) - GESI Board
+ * \n BOARD_ID_FUSION2(0x1) - Fusion 2 Board
+ * \n BOARD_ID_SOM(0x2) - SoM Board
+ * \n BOARD_ID_CP(0x3) - CP Board
+ *
+ * \return TRUE if the given board is detected else FALSE.
+ * SoM board will be always connected to the base board.
+ * For SoM boardID return value TRUE indicates dual PMIC
+ * SoM and FALSE indicates alternate PMIC SoM
+ *
+ */
+bool Board_detectBoard(uint32_t boardID)
+{
+ Board_IDInfo_v2 info;
+ Board_STATUS status;
+ bool bDet = FALSE;
+
+ if(boardID <= BOARD_ID_SOM)
+ {
+ status = Board_getBoardData(&info, boardID);
+ if(status == 0)
+ {
+ if(!(strncmp(info.boardInfo.boardName,
+ gBoardDetCfg[boardID].bName,
+ BOARD_BOARD_NAME_LEN)))
+ {
+ bDet = TRUE;
+ }
+ }
+ }
+
+ return bDet;
+}
+
+/**
+ * \brief Checks for Alpha board revision
+ *
+ * \param boardID [IN] ID of the board to be detected
+ * \n BOARD_ID_GESI(0x0) - GESI Board
+ * \n BOARD_ID_FUSION2(0x1) - Fusion 2 Board
+ * \n BOARD_ID_SOM(0x2) - SoM Board
+ * \n BOARD_ID_CP(0x3) - CP Board
+ *
+ * \return TRUE if board revision is E2, FALSE for all other cases
+ */
+bool Board_isAlpha(uint32_t boardID)
+{
+ Board_IDInfo_v2 info;
+ Board_STATUS status;
+ bool alphaBoard = FALSE;
+
+ status = Board_getBoardData(&info, boardID);
+ if(status == 0)
+ {
+ if(boardID == BOARD_ID_SOM)
+ {
+ if(!(strncmp(info.boardInfo.designRev, "E1", BOARD_DESIGN_REV_LEN)))
+ {
+ alphaBoard = TRUE;
+ }
+ }
+ else
+ {
+ if(!(strncmp(info.boardInfo.designRev,
+ "E2",
+ BOARD_DESIGN_REV_LEN)))
+ {
+ alphaBoard = TRUE;
+ }
+ }
+ }
+
+ return alphaBoard;
+}
+
+/**
+ * \brief Function to detect ENET expansion application card type
+ *
+ * Not Supported on J721S2. Dummy function for backward compatibility
+ *
+ * \return
+ */
+int32_t Board_detectEnetCard(void)
+{
+ return 0;
+}
+
+/**
+ * \brief Read MAC ID function
+ *
+ * This function reads the MAC addresses programmed to the board ID EEPROM
+ * on the boards with Ethernet ports. Exception is for MCU Ethernet port
+ * which is supposed to use MAC ID from SoC MMR registers.
+ *
+ * There can be multiple MAC IDs stored in the EEPROM based on the
+ * number of Ethernet ports on the board. Number of MAC IDs copied
+ * to 'macAddrBuf' can be read using 'macAddrCnt' parameters.
+ *
+ * Each MAC address will be 6 bytes long. MAC IDs will be copied to buffer
+ * based on 'macBufSize'. If the buffer size is long enough, all the MAC
+ * addresses from EEPROM will be copied to 'macAddrBuf' else fewer MAC
+ * IDs to fit within 'macBufSize'. MAC count for a given board can be
+ * read using Board_readMacAddrCount() function.
+ *
+ * \n Note: Board ID EEPROM should be programmed for this function
+ * to work properly.
+ *
+ * \param boardID [IN] ID of the board to be detected
+ * \n BOARD_ID_GESI(0x0) - GESI Board
+ * \n BOARD_ID_FUSION2(0x1) - Fusion 2 Board
+ * \n BOARD_ID_SOM(0x2) - SoM Board
+ * \n BOARD_ID_CP(0x3) - CP Board
+ * \param macAddrBuf[OUT] Buffer to write MAC IDs read from EEPROM
+ * \param macBufSize[IN] Size of the macAddrBuf
+ * \param macAddrCnt[OUT] Number of valid MAC addresses programmed to the EEPROM
+ * This an optional variable to read the MAC ID count
+ * filled to the 'macAddrBuf'.
+ * Pass a valid address to get MAC ID count.
+ *
+ * \return BOARD_SOK in case of success or appropriate error code.
+ *
+ */
+Board_STATUS Board_readMacAddr(uint32_t boardID,
+ uint8_t *macAddrBuf,
+ uint32_t macBufSize,
+ uint32_t *macAddrCnt)
+{
+ Board_IDInfo_v2 info;
+ Board_STATUS status;
+ uint8_t macCount = 0;
+
+ if((boardID <= BOARD_ID_SOM) && (macAddrBuf != NULL))
+ {
+ status = Board_getBoardData(&info, boardID);
+ if(status == 0)
+ {
+ macCount = ((info.macInfo.macControl & BOARD_MAC_COUNT_MASK)
+ >> BOARD_MAC_COUNT_SHIFT) + 1;
+ if(macBufSize < (macCount * BOARD_MAC_ADDR_BYTES))
+ {
+ macCount = (macBufSize / BOARD_MAC_ADDR_BYTES);
+ }
+
+ memcpy(macAddrBuf, &(info.macInfo.macAddress[0]),
+ (macCount * BOARD_MAC_ADDR_BYTES));
+ }
+ }
+ else
+ {
+ status = BOARD_INVALID_PARAM;
+ }
+
+ if(macAddrCnt != NULL)
+ {
+ *macAddrCnt = macCount;
+ }
+
+ return status;
+}
+
+/**
+ * \brief Read MAC ID count
+ *
+ * This function reads the number of MAC addresses programmed to
+ * board ID EEPROM on the boards with Ethernet ports. Exception is
+ * for MCU Ethernet port which is supposed to use MAC ID from SoC
+ * MMR registers. Each MAC address programmed to EEPROM is 6 bytes long.
+ *
+ * \n Note: Board ID EEPROM should be programmed for this function
+ * to work properly.
+ *
+ * \param boardID [IN] ID of the board to be detected
+ * \n BOARD_ID_GESI(0x0) - GESI Board
+ * \n BOARD_ID_FUSION2(0x1) - Fusion 2 Board
+ * \n BOARD_ID_SOM(0x2) - SoM Board
+ * \n BOARD_ID_CP(0x3) - CP Board
+ * \param macAddrCnt[OUT] Number of valid MAC addresses programmed to the EEPROM
+ *
+ * \return BOARD_SOK in case of success or appropriate error code.
+ *
+ */
+Board_STATUS Board_readMacAddrCount(uint32_t boardID,
+ uint32_t *macAddrCnt)
+{
+ Board_IDInfo_v2 info;
+ Board_STATUS status;
+
+ if((boardID <= BOARD_ID_SOM) && (macAddrCnt != NULL))
+ {
+ status = Board_getBoardData(&info, boardID);
+ if(status == 0)
+ {
+ *macAddrCnt = ((info.macInfo.macControl & BOARD_MAC_COUNT_MASK)
+ >> BOARD_MAC_COUNT_SHIFT) + 1;
+ }
+ }
+ else
+ {
+ status = BOARD_INVALID_PARAM;
+ }
+
+ return status;
+}
+
+/**
+ * \brief Function to configure I2C configurations used by board
+ *
+ * This function is used to set the I2C controller instance and
+ * SoC domain used by the board module for IO expander and board
+ * ID info read.
+ *
+ * Usage:
+ * Call Board_setI2cInitConfig to set the I2C configurations
+ * Call IO expander Init or Board ID info read/write
+ *
+ * \return BOARD_SOK in case of success or appropriate error code.
+ *
+ */
+Board_STATUS Board_setI2cInitConfig(Board_I2cInitCfg_t *i2cCfg)
+{
+ if(i2cCfg == NULL)
+ {
+ return BOARD_INVALID_PARAM;
+ }
+
+ gBoardI2cInitCfg = *i2cCfg;
+
+ return BOARD_SOK;
+}
+
+/**
+ * \brief Function to get board init params
+ *
+ * This function shall be used to know the current board init
+ * parameters and update them if needed using the function Board_setInitParams.
+ *
+ * \param initParams [IN] Board init params structure
+ *
+ * \return BOARD_SOK in case of success or appropriate error code.
+ *
+ */
+Board_STATUS Board_getInitParams(Board_initParams_t *initParams)
+{
+ if(initParams == NULL)
+ {
+ return BOARD_INVALID_PARAM;
+ }
+
+ *initParams = gBoardInitParams;
+
+ return BOARD_SOK;
+}
+
+/**
+ * \brief Function to configure board init parameters
+ *
+ * Board init params includes the parameters used by Board_init
+ * function for different operations. Default init parameters
+ * used by Board_init can be updated using this function.
+ * All the default params can be overwritten by calling this function
+ * or some of can be changed by reading the existing init parameters
+ * using Board_getInitParams function.
+ *
+ * Usage:
+ * Call Board_getInitParams to get the default board init parameters
+ * Update the parameters as needed
+ * Call Board_setInitParams to update the default board init parameters
+ *
+ * \param initCfg [IN] Board Init config structure
+ *
+ * \return BOARD_SOK in case of success or appropriate error code.
+ *
+ */
+Board_STATUS Board_setInitParams(Board_initParams_t *initParams)
+{
+ if(initParams == NULL)
+ {
+ return BOARD_INVALID_PARAM;
+ }
+
+ gBoardInitParams = *initParams;
+
+ return BOARD_SOK;
+}
+
+/**
+ * \brief Voltage Switching function for MMCSD
+ *
+ * Functionality: Change the voltage of the MMC CMD & DAT lines.
+ * This function is called by the MMCSD card driver (if the driver is
+ * configured to use this function at init time by the application) to change
+ * the CMD & DAT voltage from 3.0V to 1.8V if a UHS-I card is found.
+ * This function configures the PMIC controller of the board to switch the voltage
+ *
+ * Note: This function uses non-standard board API naming and return type
+ * to align with existing platforms.
+ *
+ * \param instance [IN] Device instance
+ * \param switchVoltage [IN] MMCSD IO voltage value
+ *
+ */
+MMCSD_Error Board_mmc_voltageSwitchFxn(uint32_t instance,
+ MMCSD_BusVoltage_e switchVoltage)
+{
+ MMCSD_Error mmcRetVal = MMCSD_OK;
+
+ if(switchVoltage == MMCSD_BUS_VOLTAGE_1_8V)
+ {
+ Board_sdVoltageCtrlGpioCfg(0);
+ }
+ else if(switchVoltage == MMCSD_BUS_VOLTAGE_3_3V)
+ {
+ Board_sdVoltageCtrlGpioCfg(1);
+ }
+ else
+ {
+ mmcRetVal = MMCSD_ERR;
+ }
+
+ return(mmcRetVal);
+}
+
+/**
+ * \brief Function to get the SoC domain
+ *
+ * This function returns the domain of the SoC core on which
+ * it is executing.
+ *
+ * \return SoC domain of the core.
+ *
+ */
+uint32_t Board_getSocDomain(void)
+{
+ uint32_t socDomain = BOARD_SOC_DOMAIN_MAIN;
+
+#ifdef BUILD_MCU
+ CSL_ArmR5CPUInfo info;
+
+ CSL_armR5GetCpuID(&info);
+ if (info.grpId == (uint32_t)CSL_ARM_R5_CLUSTER_GROUP_ID_0)
+ {
+ socDomain = BOARD_SOC_DOMAIN_MCU;
+ }
+#endif
+
+ return socDomain;
+}
+
+/**
+ * \brief Sets RAT configuration
+ *
+ * MAIN padconfig registers are not directly accessible for C66x core
+ * which requires RAT configuration for the access.
+ *
+ * \return None
+ */
+void Board_setRATCfg(void)
+{
+#if defined (_TMS320C6X)
+ gRatOffsetLo = HW_RD_REG32(CSL_C66_COREPAC_C66_RATCFG_BASE + 0x24);
+ gRatOffsetHi = HW_RD_REG32(CSL_C66_COREPAC_C66_RATCFG_BASE + 0x28);
+ gRatCfg = HW_RD_REG32(CSL_C66_COREPAC_C66_RATCFG_BASE + 0x20);
+ HW_WR_REG32((CSL_C66_COREPAC_C66_RATCFG_BASE + 0x24),
+ BOARD_C66X_RAT_OFFSET);
+ HW_WR_REG32((CSL_C66_COREPAC_C66_RATCFG_BASE + 0x28), 0);
+ HW_WR_REG32((CSL_C66_COREPAC_C66_RATCFG_BASE + 0x20),
+ BOARD_C66X_RAT_CONFIG);
+#endif
+}
+
+/**
+ * \brief Restores RAT configuration
+ *
+ * \return None
+ */
+void Board_restoreRATCfg(void)
+{
+#if defined (_TMS320C6X)
+ HW_WR_REG32((CSL_C66_COREPAC_C66_RATCFG_BASE + 0x20), gRatCfg);
+ HW_WR_REG32((CSL_C66_COREPAC_C66_RATCFG_BASE + 0x24), gRatOffsetLo);
+ HW_WR_REG32((CSL_C66_COREPAC_C66_RATCFG_BASE + 0x28), gRatOffsetHi);
+#endif
+}
+
+/**
+ * \brief Function to generate delay in micro seconds
+ *
+ * This function takes the delay parameters in usecs but the generated
+ * delay will be in multiples of msecs due to the osal function which
+ * generates delay in msecs. Delay parameter passed will be converted to
+ * msecs and fractional value will be adjusted to nearest msecs value.
+ * Minimum delay generated by this function is 1 msec.
+ * Function parameter is kept in usecs to match with existing
+ * platforms which has delay function for usecs.
+ *
+ * \param usecs [IN] Specifies the time to delay in micro seconds.
+ *
+ */
+void BOARD_delay(uint32_t usecs)
+{
+ uint32_t msecs;
+
+ msecs = usecs/1000;
+ if(usecs%1000)
+ {
+ msecs += 1;
+ }
+
+ Osal_delay(msecs);
+}
diff --git a/packages/ti/board/src/j721s2_evm/include/board_cfg.h b/packages/ti/board/src/j721s2_evm/include/board_cfg.h
--- /dev/null
@@ -0,0 +1,431 @@
+/******************************************************************************
+ * Copyright (c) 2021 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *****************************************************************************/
+
+/**
+ * \brief Board library configurations
+ *
+ * This file configures the instance numbers, address and gpio reset
+ * details of different interfaces of the board.
+ *
+ */
+#ifndef BOARD_CFG_H_
+#define BOARD_CFG_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <ti/board/board.h>
+
+/* Board ID information */
+#define BOARD_INFO_CPU_NAME "j721s2"
+#define BOARD_INFO_BOARD_NAME "j721s2_evm"
+
+/* Memory sections */
+#define BOARD_DDR_START_ADDR (0x80000000U)
+#define BOARD_DDR_SIZE (2048 * 1024 * 1024UL)
+#define BOARD_DDR_END_ADDR (0xFFFFFFFFU)
+/* Note with ECC enabled, all memory is not usable: 1/8 memory used for inline ECC */
+#define BOARD_DDR_ECC_END_ADDR (0xF1FFFFFFU)
+/* Enable/Disable DDR Memory Prime for ECC. Define the following macro to enable. */
+#undef BOARD_DDR_ENABLE_DDR_MEM_PRIME
+
+/* UART LLD instance number for primary UART port */
+#define BOARD_UART_INSTANCE (8U)
+/* UART LLD instance number for MAIN UART1 port */
+#define BOARD_UART1_INSTANCE (1U)
+/* UART LLD instance number for MAIN UART2 port */
+#define BOARD_UART2_INSTANCE (2U)
+/* UART LLD instance number for MAIN UART4 port */
+#define BOARD_UART4_INSTANCE (4U)
+/* UART LLD instance number for MAIN UART5 port */
+#define BOARD_UART5_INSTANCE (5U)
+/* MCU UART LLD instance number */
+#define BOARD_MCU_UART_INSTANCE (0U)
+/* WKUP UART LLD instance number */
+#define BOARD_WKUP_UART_INSTANCE (0U)
+/* ICSSG UART instance number */
+#define BOARD_ICSSG_UART_INSTANCE (4U)
+
+/* INFO and GESI board ID EEPROM address */
+#define BOARD_EXP_CON_BOARDID_EEPROM_ADDRS (0x52U)
+
+/* I2C instance connected to EEPROM - WKUP I2C0 */
+#define BOARD_I2C_EEPROM_INSTANCE (0U)
+
+/* I2C instance for BOOT EEPROM */
+#define BOARD_I2C_BOOT_EEPROM_INSTANCE (0U)
+
+/* I2C address for Boot EEPROM */
+#define BOARD_I2C_BOOT_EEPROM_ADDR (0x50U)
+#define BOARD_I2C_BOOT_EEPROM_ADDR2 (0x51U)
+
+/* I2C address for Board Id EEPROM */
+#define BOARD_I2C_EEPROM_ADDR (0x50U)
+
+/* QSPI instance number */
+#define BOARD_SPI_NOR_INSTANCE (1U)
+
+/* I2C Instance connected to clock generator */
+#define BOARD_CLOCK_GENERATOR_INSTANCE (0U)
+/* I2C slave address of clock generator */
+#define BOARD_I2C_CLOCK_GENERATOR1 (0)
+#define BOARD_I2C_CLOCK_GENERATOR2_ADDR1 (0x76)
+#define BOARD_I2C_CLOCK_GENERATOR2_ADDR2 (0x77)
+#define BOARD_I2C_QSGMII_CLOCK_GENERATOR_ADDR1 (0x76)
+#define BOARD_I2C_QSGMII_CLOCK_GENERATOR_ADDR2 (0x77)
+#define BOARD_I2C_PERI_CLOCK_GENERATOR (0x6D)
+
+/* OSPI instance connected to OSPI NOR flash */
+#define BOARD_OSPI_NOR_INSTANCE (0U)
+
+/* OSPI instance connected to OSPI NOR flash */
+#define BOARD_OSPI_NAND_INSTANCE (0U)
+
+/* HyperFlash instance number */
+#define BOARD_HPF_INSTANCE (0)
+
+/* I2C instance connected to IO Expander */
+#define BOARD_I2C_IOEXP_SOM_INSTANCE (0U)
+#define BOARD_I2C_IOEXP_SOM_DEVICE1_INSTANCE (BOARD_I2C_IOEXP_SOM_INSTANCE)
+#define BOARD_I2C_IOEXP_DEVICE1_INSTANCE (0U)
+#define BOARD_I2C_IOEXP_DEVICE2_INSTANCE (0U)
+#define BOARD_I2C_IOEXP_DEVICE3_INSTANCE (3U)
+#define BOARD_I2C_IOEXP_DEVICE4_INSTANCE (4U)
+#define BOARD_I2C_IOEXP_DEVICE5_INSTANCE (6U)
+#define BOARD_I2C_AUDIO_IOEXP_DEVICE_INSTANCE (3U)
+#define BOARD_I2C_VIDEO_IOEXP_DEVICE_INSTANCE (1U)
+#define BOARD_I2C_DSI2DP_DEVICE_INSTANCE (4U)
+
+/* I2C IO Expander Slave devices */
+#define BOARD_I2C_IOEXP_SOM_ADDR (0x21U)
+#define BOARD_I2C_IOEXP_DEVICE1_ADDR (0x20U)
+#define BOARD_I2C_IOEXP_DEVICE2_ADDR (0x22U)
+#define BOARD_I2C_IOEXP_DEVICE3_ADDR (0x20U)
+#define BOARD_I2C_IOEXP_DEVICE4_ADDR (0x20U)
+#define BOARD_I2C_IOEXP_DEVICE5_ADDR (0x20U)
+#define BOARD_I2C_AUDIO_IOEXP_DEVICE_ADDR (0x21U)
+#define BOARD_I2C_VIDEO_IOEXP_DEVICE_ADDR (0x21U)
+
+/* I2C instance connected to PMIC - WKUP I2C0 */
+#define BOARD_I2C_PMIC_INSTANCE (0U)
+
+/* I2C slave address of Leo PMICs */
+#define BOARD_I2C_LEO_PMIC_A_ADDR (0x48U)
+#define BOARD_I2C_LEO_PMIC_B_ADDR (0x4CU)
+#define BOARD_I2C_LEO_PMIC_A_WDT_ADDR (0x12U)
+#define BOARD_I2C_LEO_PMIC_B_WDT_ADDR (0x13U)
+
+/* OSPI instance number */
+#define BOARD_OSPI_INSTANCE (0)
+
+/* I2C instance for External RTC */
+#define BOARD_I2C_EXT_RTC_INSTANCE (0U)
+
+/* I2C address for External RTC */
+#define BOARD_I2C_EXT_RTC_ADDR (0x6FU)
+
+/* Number of LEDS connected to IO expander on CP board */
+#define BOARD_GPIO_LED_NUM (2U)
+
+/* User LED Pin Details */
+#define BOARD_I2C_USER_LED_INSTANCE (0U)
+
+#define BOARD_USER_LED1 (6U)
+#define BOARD_USER_LED2 (7U)
+#define BOARD_USER_LED_IOEXP_PORT (2U)
+
+#define BOARD_ICSS_EMAC_PORT_MAX (1)
+#define BOARD_CPSW9G_EMAC_PORT_MAX (0)
+#define BOARD_CPSW9G_PORT_MAX (0)
+
+
+/* ICSS0 EMAC PHY register address */
+#define BOARD_ICSS0_EMAC_PHY0_ADDR (0x0)
+#define BOARD_ICSS0_EMAC_PHY1_ADDR (0x3u)
+
+/* ICSS1 EMAC PHY register address */
+#define BOARD_ICSS1_EMAC_PHY0_ADDR (0xCu)
+#define BOARD_ICSS1_EMAC_PHY1_ADDR (0xFu)
+
+
+/* PRG0_RGMII_RESETn */
+#define BOARD_GPIO_IOEXP_ICSS0_EMAC_RST_PORT_NUM (0U) /* GPIO0_61 */
+#define BOARD_GPIO_IOEXP_ICSS0_EMAC_RST_PIN_NUM (0x3DU)
+
+/* PRG0_RGMII_INTn */
+#define BOARD_GPIO_ICSS0_EMAC_INT_PORT_NUM (1U) /* GPIO1_23 */
+#define BOARD_GPIO_ICSS0_EMAC_INT_PIN_NUM (0x17U)
+
+/* PRG1_RGMII_RESETn */
+#define BOARD_GPIO_IOEXP_ICSS1_EMAC_RST_PORT_NUM (0U) /* GPIO0_62 */
+#define BOARD_GPIO_IOEXP_ICSS1_EMAC_RST_PIN_NUM (0x3EU)
+
+/* PRG1_RGMII_INTn */
+#define BOARD_GPIO_ICSS1_EMAC_INT_PORT_NUM (1U) /* GPIO1_24 */
+#define BOARD_GPIO_ICSS1_EMAC_INT_PIN_NUM (0x18U)
+
+/* MCU EMAC PHY MDIO address */
+#define BOARD_MCU_EMAC_PHY_ADDR (0U)
+
+/* MAIN EMAC PHY MDIO address */
+#define BOARD_MAIN_EMAC_PHY_ADDR (0U)
+
+/* HDMI IO Exp instances */
+#define BOARD_HDMI_IO_EXP_INSTANCE (1U)
+#define BOARD_HDMI_IO_SLAVE_ADDR (0x21U)
+
+/* MCU EMAC MAX REG DUMP */
+#define BOARD_MCU_EMAC_REG_DUMP_MAX ((16U))
+
+/* MCU EMAC PHY register address definitions for reading strap values */
+#define BOARD_MCU_EMAC_STRAP_STS1_ADDR (0x6EU)
+#define BOARD_MCU_EMAC_STRAP_STS2_ADDR (0x6FU)
+
+/* ICSS EMAC PHY register address definitions for reading strap values */
+#define BOARD_ICSS_EMAC_STRAP_STS1_ADDR (0x6EU)
+#define BOARD_ICSS_EMAC_STRAP_STS2_ADDR (0x6FU)
+
+/* MCU_ETH1_RESETn */
+#define BOARD_GPIO_IOEXP_MCU_EMAC_RST_PORT_NUM (0U) /* WKUP_GPIO0_3 */
+#define BOARD_GPIO_IOEXP_MCU_EMAC_RST_PIN_NUM (0x03U)
+
+/* MCU_ETH1_INTn */
+#define BOARD_GPIO_MCU_EMAC_INT_PORT_NUM (0U) /* WKUP_GPIO0_55 */
+#define BOARD_GPIO_MCU_EMAC_INT_PIN_NUM (0X37U)
+
+/* AUTOMATION HEADER */
+#define BOARD_TEST_HEADER_I2C_INSTANCE (1U)
+#define BOARD_I2C_BOOT_MODE_SW_ADDR (0x22U)
+
+/* Temperature sensor i2c instance */
+#define BOARD_TEMP_SENSOR_I2C_INSTANCE (0U)
+
+/* Temperature sensor slave device addresses */
+#define BOARD_TEMP_SENSOR_I2C_SLAVE_DEVICE1_ADDR (0x48U)
+#define BOARD_TEMP_SENSOR_I2C_SLAVE_DEVICE2_ADDR (0x49U)
+
+#define BOARD_I2C_CURRENT_MONITOR_INSTANCE (1U)
+
+/* Instance for interfaces connected to MMCSD */
+#define BOARD_MMCSD_SD_INSTANCE (1U)
+#define BOARD_MMCSD_EMMC_INSTANCE (0U)
+
+/* Enable NOR flash driver */
+#define BOARD_NOR_FLASH_IN
+
+/* Enable NAND flash driver */
+#define BOARD_NAND_FLASH_IN
+
+/* Maximum possible buffer length */
+#define BOARD_EEPROM_MAX_BUFF_LENGTH (197U)
+
+/* EEPROM board ID information */
+#define BOARD_EEPROM_HEADER_FIELD_SIZE (7U)
+#define BOARD_EEPROM_TYPE_SIZE (1U)
+#define BOARD_EEPROM_STRUCT_LENGTH_SIZE (2U)
+#define BOARD_EEPROM_MAGIC_NUMBER (0xEE3355AA)
+
+#define BOARD_BOARD_FIELD_TYPE (0x10)
+#define BOARD_DDR_FIELD_TYPE (0x11)
+#define BOARD_MACINFO_FIELD_TYPE (0x13)
+#define BOARD_ENDLIST (0xFE)
+
+#define BOARD_EEPROM_HEADER_ADDR (0U)
+
+/* PinMux data to be programmed to configure a pin to be a GPIO */
+#define PINMUX_GPIO_CFG (0x00050007U)
+
+/* Maximum number of SoC domains */
+#define BOARD_SOC_DOMAIN_MAX (3U)
+/* Value for indicating SoC main domain */
+#define BOARD_SOC_DOMAIN_MAIN (0)
+/* Value for indicating SoC wake-up domain */
+#define BOARD_SOC_DOMAIN_WKUP (1U)
+/* Value for indicating SoC MCU domain */
+#define BOARD_SOC_DOMAIN_MCU (2U)
+/* Maximum I2C instance number common across the domain */
+#define BOARD_I2C_DOMAIN_INSTANCE_MAX (2U)
+
+/* SoC domain used by UART module */
+#if (__ARM_ARCH == 7) && (__ARM_ARCH_PROFILE == 'R') && defined(__ARM_FEATURE_IDIV)
+#define BOARD_UART_SOC_DOMAIN (BOARD_SOC_DOMAIN_MCU)
+#else
+#define BOARD_UART_SOC_DOMAIN (BOARD_SOC_DOMAIN_MAIN)
+#endif
+
+/* Clock frequency for UART module */
+#define BOARD_UART_CLK_MAIN (48000000U)
+#define BOARD_UART_CLK_WKUP (96000000U)
+
+/* Board detect ID for GESI */
+#define BOARD_ID_GESI (0x0)
+/* Board detect ID for Fusion2 */
+#define BOARD_ID_FUSION2 (0x1U)
+/* Board detect ID for dual PMIC SoM */
+#define BOARD_ID_SOM (0x2U)
+/* Board detect ID for CP Board */
+#define BOARD_ID_CP (0x3U)
+
+/* Maximum number of supporting board ID */
+#define BOARD_ID_MAX_BOARDS (0x4U)
+
+#define BOARD_EEPROM_HEADER_LENGTH (4U)
+#define BOARD_EEPROM_BOARD_NAME_LENGTH (8U)
+#define BOARD_EEPROM_VERSION_LENGTH (4U)
+#define BOARD_EEPROM_SERIAL_NO_LENGTH (12U)
+#define BOARD_EEPROM_CONFIG_LENGTH (32U)
+
+#define BOARD_EEPROM_BOARD_NAME_ADDR (BOARD_EEPROM_HEADER_ADDR + BOARD_EEPROM_HEADER_LENGTH)
+#define BOARD_EEPROM_VERSION_ADDR (BOARD_EEPROM_BOARD_NAME_ADDR + BOARD_EEPROM_BOARD_NAME_LENGTH)
+#define BOARD_EEPROM_SERIAL_NO_ADDR (BOARD_EEPROM_VERSION_ADDR + BOARD_EEPROM_VERSION_LENGTH)
+#define BOARD_EEPROM_CONFIG_ADDR (BOARD_EEPROM_SERIAL_NO_ADDR + BOARD_EEPROM_SERIAL_NO_LENGTH)
+
+#define BOARD_SOM_EEPROM_SLAVE_ADDR (0x50U)
+#define BOARD_CP_EEPROM_SLAVE_ADDR (0x51U)
+#define BOARD_ENET_EEPROM_SLAVE_ADDR (0x54U)
+#define BOARD_GESI_EEPROM_SLAVE_ADDR (0x52U)
+#define BOARD_CSI2_EEPROM_SLAVE_ADDR (0x52U)
+#define BOARD_DISPLAY_EEPROM_SLAVE_ADDR (0x00U) //J7ES_TBD: Need to update salve addr when board design is complete
+
+#define BOARD_COMMON_EEPROM_I2C_INST (0)
+#define BOARD_CSI2_EEPROM_I2C_INST (6)
+
+#define BOARD_MMC_VOLTAGESWITCH_FN Board_mmc_voltageSwitchFxn
+
+/* Below macros are retained for compatibility with other K3 platforms.
+ Need to review and remove them */
+/* PRG0_ETH1_LED_LINK */
+#define BOARD_GPIO_ICSS0_EMAC_PHY0_LED_LINK_PORT_NUM (0)
+#define BOARD_GPIO_ICSS0_EMAC_PHY0_LED_LINK_PIN_NUM (0)
+
+/* PRG0_ETH2_LED_LINK */
+#define BOARD_GPIO_ICSS0_EMAC_PHY1_LED_LINK_PORT_NUM (0)
+#define BOARD_GPIO_ICSS0_EMAC_PHY1_LED_LINK_PIN_NUM (0)
+
+/* GPIO to drive PRG0 LED0 */
+#define BOARD_GPIO_ICSS0_EMAC_LED0_PORT_NUM (0)
+#define BOARD_GPIO_ICSS0_EMAC_LED0_PIN_NUM (0)
+
+/* GPIO to drive PRG0 LED1 */
+#define BOARD_GPIO_ICSS0_EMAC_LED1_PORT_NUM (0)
+#define BOARD_GPIO_ICSS0_EMAC_LED1_PIN_NUM (0)
+
+/* GPIO to drive PRG0 LED2 */
+#define BOARD_GPIO_ICSS0_EMAC_LED2_PORT_NUM (0)
+#define BOARD_GPIO_ICSS0_EMAC_LED2_PIN_NUM (0)
+
+/* GPIO to drive PRG0 LED3 */
+#define BOARD_GPIO_ICSS0_EMAC_LED3_PORT_NUM (0)
+#define BOARD_GPIO_ICSS0_EMAC_LED3_PIN_NUM (0)
+
+#define BOARD_GPIO_IOEXP_SPI_RST_PORT_NUM (0)
+#define BOARD_GPIO_IOEXP_SPI_RST_PIN_NUM (0)
+
+/* TEST_GPIO1 */
+#define BOARD_GPIO_IOEXP_TEST_PORT_NUM (0)
+#define BOARD_GPIO_IOEXP_TEST_PIN_NUM (0)
+
+/* PRG1_ETH1_LED_LINK */
+#define BOARD_GPIO_ICSS1_EMAC_PHY0_LED_LINK_PORT_NUM (0)
+#define BOARD_GPIO_ICSS1_EMAC_PHY0_LED_LINK_PIN_NUM (0)
+
+/* PRG1_ETH2_LED_LINK */
+#define BOARD_GPIO_ICSS1_EMAC_PHY1_LED_LINK_PORT_NUM (0)
+#define BOARD_GPIO_ICSS1_EMAC_PHY1_LED_LINK_PIN_NUM (0)
+
+/* GPIO to drive PRG1 LED0 */
+#define BOARD_GPIO_ICSS1_EMAC_LED0_PORT_NUM (0)
+#define BOARD_GPIO_ICSS1_EMAC_LED0_PIN_NUM (0)
+
+/* GPIO to drive PRG1 LED1 */
+#define BOARD_GPIO_ICSS1_EMAC_LED1_PORT_NUM (0)
+#define BOARD_GPIO_ICSS1_EMAC_LED1_PIN_NUM (0)
+
+/* GPIO to drive PRG1 LED2 */
+#define BOARD_GPIO_ICSS1_EMAC_LED2_PORT_NUM (0)
+#define BOARD_GPIO_ICSS1_EMAC_LED2_PIN_NUM (0)
+
+/* GPIO to drive PRG1 LED3 */
+#define BOARD_GPIO_ICSS1_EMAC_LED3_PORT_NUM (0)
+#define BOARD_GPIO_ICSS1_EMAC_LED3_PIN_NUM (0)
+
+#define BOARD_GPIO_IOEXP_OSPI_RST_PORT_NUM (0)
+#define BOARD_GPIO_IOEXP_OSPI_RST_PIN_NUM (0)
+
+/* GPIO port & pin numbers for MMC reset */
+#define GPIO_MMC_SDCD_PORT_NUM (0)
+#define GPIO_MMC_SDCD_PIN_NUM (0)
+
+#define BOARD_GPIO_IOEXP_EMMC_RST_PORT_NUM (0x00)
+#define BOARD_GPIO_IOEXP_EMMC_RST_PIN_NUM (0x00)
+
+#define BOARD_I2C_TOUCH_INSTANCE (0)
+#define BOARD_I2C_TOUCH_SLAVE_ADDR (0)
+
+#define BOARD_I2C_FPD_UB926_INSTANCE (3U)
+#define BOARD_I2C_FPD_UB926_ADDR (0x2CU)
+
+/* I2C instance Board Presence Circuit */
+#define BOARD_PRES_WKUP_I2C_INSTANCE (0U)
+/* I2C address Board Presence Circuit */
+#define BOARD_PRES_DETECT_SLAVE_ADDR (0)
+
+/* McSPI instance for master and slave test */
+#define BOARD_MCSPI_MASTER_INSTANCE (1)
+#define BOARD_MCSPI_SLAVE_INSTANCE (1)
+
+/* LIN uart instance */
+#define BOARD_LIN1_UART_INSTANCE (6U)
+#define BOARD_LIN1_UART_BASE (CSL_UART6_BASE)
+
+#define BOARD_LIN2_UART_INSTANCE (3U)
+#define BOARD_LIN2_UART_BASE (CSL_UART3_BASE)
+
+#define BOARD_LIN3_UART_INSTANCE (9U)
+#define BOARD_LIN3_UART_BASE (CSL_UART9_BASE)
+
+/* Default pinmux configuration of UART Tx pin used by ROM/SBL */
+#define BOARD_MCU_UART_TX_PINMUX_VAL (PIN_MODE(0U) | ((PIN_PULL_DISABLE) & \
+ (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE)))
+#define BOARD_MCU_UART_TX_PINMUX_ADDR (BOARD_WKUP_PMUX_CTRL_ADDR + PIN_WKUP_GPIO0_12)
+#define BOARD_MCU_UART_TX_LOCK_KICK_ADDR (CSL_WKUP_CTRL_MMR0_CFG0_BASE + \
+ CSL_WKUP_CTRL_MMR_CFG0_LOCK7_KICK0)
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* BOARD_CFG_H_ */
+
diff --git a/packages/ti/board/src/j721s2_evm/include/board_clock.h b/packages/ti/board/src/j721s2_evm/include/board_clock.h
--- /dev/null
@@ -0,0 +1,71 @@
+/******************************************************************************
+ * Copyright (c) 2021 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *****************************************************************************/
+
+/** \file board_clock.h
+*
+* \brief This file contains structure, typedefs, functions and
+* prototypes used for clock configurations.
+*/
+
+#ifndef BOARD_CLOCK_H
+#define BOARD_CLOCK_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <ti/board/src/j721s2_evm/include/board_internal.h>
+
+/**
+ * \brief Enables module clock
+ *
+ * \return BOARD_SOK - Clock enable sucessful.
+ * BOARD_FAIL - Clock enable failed.
+ *
+ */
+Board_STATUS Board_moduleClockEnable(uint32_t moduleId);
+
+/**
+ * \brief Disables module clock
+ *
+ * \return BOARD_SOK - Clock disable successful.
+ * BOARD_FAIL - Clock disable failed.
+ *
+ */
+Board_STATUS Board_moduleClockDisable(uint32_t moduleId);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* BOARD_CLOCK_H */
diff --git a/packages/ti/board/src/j721s2_evm/include/board_control.h b/packages/ti/board/src/j721s2_evm/include/board_control.h
--- /dev/null
@@ -0,0 +1,151 @@
+/******************************************************************************
+ * Copyright (c) 2021 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *****************************************************************************/
+
+/**
+ * \file board_control.h
+ *
+ * \brief Board control functions header file
+ *
+ */
+
+#ifndef _BOARD_CONTROL_H_
+#define _BOARD_CONTROL_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*****************************************************************************
+ * Include Files *
+ *****************************************************************************/
+#include <ti/csl/csl_types.h>
+#include <ti/csl/cslr_device.h>
+
+#include <ti/board/board.h>
+#include <ti/csl/tistdtypes.h>
+#include <stdio.h>
+#include <stdbool.h>
+
+#include "board_internal.h"
+#include "board_utils.h"
+#include "board_i2c_io_exp.h"
+
+#define BOARD_CTRL_CMD_SET_IO_EXP_PIN_OUT (0U)
+
+/*
+ * Enables Port A to Port B1 routing on SoM Mux which enables below IOs
+ * - Debug Trace Data
+ * - McASP
+ */
+#define BOARD_CTRL_CMD_SET_SOM_MUX_PORTB1 (1U)
+
+/*
+ * Enables Port A to Port B2 routing on SoM Mux which enables below IOs
+ * - UARTs for LIN
+ * - MCAN3, MCAN4, MCAN5
+ * - I2C1, I2C3
+ * - UART8 CTS & RTS
+ * - GPIO0_18 (DP0_HPD)
+ * - GPIO0_23 (GPIO_RGMII1_INT#)
+ * - GPIO0_26 (CSI2_EXP_A_GPIO2)
+ * - GPIO0_28 (CSI2_EXP_A_GPIO4)
+ */
+#define BOARD_CTRL_CMD_SET_SOM_MUX_PORTB2 (2U)
+
+/*
+ * Enables Port A to Port B3 routing on SoM Mux which enables below IOs
+ * - Hyperlink0, Hyperlink1
+ * - SPI5
+ */
+#define BOARD_CTRL_CMD_SET_SOM_MUX_PORTB3 (3U)
+
+/* Enables the DSI to eDP bridge */
+#define BOARD_CTRL_CMD_ENABLE_DSI2DP_BRIDGE (4U)
+
+#define BOARD_CTRL_CMD_SOM_MUX_PORTB_MASK (0x7U)
+#define BOARD_CTRL_CMD_SOM_MUX_PORTB1_ENABLE (0x4U)
+#define BOARD_CTRL_CMD_SOM_MUX_PORTB2_ENABLE (0x7U)
+#define BOARD_CTRL_CMD_SOM_MUX_PORTB3_ENABLE (0x3U)
+
+/* Below macros are not supprted on J721S2 but kept for the build compatibility */
+#define BOARD_CTRL_CMD_SET_HDMI_MUX (1)
+#define BOARD_CTRL_CMD_SET_HDMI_PD_HIGH (2U)
+#define BOARD_CTRL_CMD_SET_ICSSG_MDIO_MUX (3U)
+#define BOARD_CTRL_CMD_SET_GESI_CPSW_MDIO_MUX (4U)
+#define BOARD_CTRL_CMD_SET_PRG1_RGMII_MDIO_MUX (5U)
+#define BOARD_CTRL_CMD_SET_RS485_UART4_EN_MUX (6U)
+#define BOARD_CTRL_CMD_SET_RMII_DATA_MUX (7U)
+
+/**
+ * \brief Structure to configure the board I2C parameters
+ */
+typedef struct Board_IoExpCfg_s
+{
+ /** IO expander slave address */
+ uint32_t slaveAddr;
+ /** I2C controller instance */
+ uint32_t i2cInst;
+ /** SoC domain of the I2C controller */
+ uint8_t socDomain;
+ /** I2C controller interrupt enable/disable flag */
+ bool enableIntr;
+ /** IO expander type */
+ i2cIoExpType_t ioExpType;
+ /** IO expander port number */
+ i2cIoExpPortNumber_t portNum;
+ /** IO expander pin number */
+ i2cIoExpPinNumber_t pinNum;
+ /** IO expander signal level */
+ i2cIoExpSignalLevel_t signalLevel;
+} Board_IoExpCfg_t;
+
+/**
+ * \brief Board control function
+ *
+ * \param cmd [IN] Board control command
+ * \param arg [IN] Control command argument.
+ * Changes based on the command
+ *
+ * \return TRUE if the given board is detected else 0.
+ * SoM board will be always connected to the base board.
+ * For SoM boardID return value TRUE indicates dual PMIC
+ * SoM and FALSE indicates alternate PMIC SoM
+ *
+ */
+Board_STATUS Board_control(uint32_t cmd, void *arg);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _BOARD_CONTROL_H_ */
diff --git a/packages/ti/board/src/j721s2_evm/include/board_ddr.h b/packages/ti/board/src/j721s2_evm/include/board_ddr.h
--- /dev/null
@@ -0,0 +1,125 @@
+/******************************************************************************
+ * Copyright (c) 2021 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *****************************************************************************/
+
+/** \file board_ddr.h
+ *
+ * \brief This file contains DDR timing parameters
+ */
+
+#ifndef BOARD_DDR_H_
+#define BOARD_DDR_H_
+
+#include <ti/csl/soc.h>
+#include <ti/csl/hw_types.h>
+#include <ti/csl/csl_lpddr.h>
+#include <ti/csl/csl_emif.h>
+#include <ti/drv/sciclient/sciclient.h>
+
+#include "board.h"
+#include "board_pll.h"
+#include "board_utils.h"
+#include "board_internal.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define BOARD_DDR0_CTL_CFG_BASE (CSL_COMPUTE_CLUSTER0_CTL_CFG_BASE)
+#define BOARD_DDR1_CTL_CFG_BASE (CSL_COMPUTE_CLUSTER0_DDR1_1_CTL_CFG_BASE)
+
+#define BOARD_DDR_FSP_CLKCHNG_REQ_ADDR (0x00114080U)
+#define BOARD_DDR_FSP_CLKCHNG_ACK_ADDR (0x001140C0U)
+
+#define BOARD_CTRL_MMR_PART5_LOCK0 (0x115008U)
+#define BOARD_CTRL_MMR_PART5_LOCK1 (0x11500CU)
+
+#define BOARD_PLL12_LOCK0 (0x68C010U)
+#define BOARD_PLL12_LOCK1 (0x68C014U)
+
+#define BOARD_DDR_SRAM_MAX (512U)
+
+#define BOARD_DDR_CTL_REG_OFFSET (0)
+
+#define LPDDR4__AUTO_TEMPCHK_VAL_0__REG_OFFSET (162U)
+#define LPDDR4__AUTO_TEMPCHK_VAL_0_MASK (0x00FFFF00U)
+#define LPDDR4__AUTO_TEMPCHK_VAL_0_SHIFT (8U)
+#define LPDDR4__AUTO_TEMPCHK_OP0_MASK (7U)
+
+#define BOARD_MAX_TEMP_CHECK_REFRESH_RATE_VALUE (7U)
+#define BOARD_TEMP_CHECK_REFRESH_RATE_VALUE_0_25_DERATING (6U)
+
+
+#define BOARD_MULTI_DDR_CFG_INTRLV_HEARTBEAT (3U)
+#define BOARD_MULTI_DDR_CFG0 (0x114100U)
+#define BOARD_MULTI_DDR_CFG1 (0x114104U)
+#define BOARD_DDR_CFG_LOAD (0x114110U)
+
+#define BOARD_DDR_INSTANCE_0 (0U)
+#define BOARD_DDR_INSTANCE_1 (1U)
+#define BOARD_DDR_INSTANCE_MAX (2U)
+
+#define BOARD_DDR_LOCK0 (0x115008U)
+#define BOARD_DDR_LOCK1 (0x11500CU)
+
+#define BOARD_DDR_CFG_LOAD_VALUE (0x11500CU)
+
+/**
+ * \brief DDR object structure
+ */
+typedef struct Board_DdrObject_s
+{
+ /** DDR controller instance */
+ uint32_t ddrInst;
+ /** DDR instance open flag */
+ bool isOpen;
+ /** DDR Controller base addres */
+ void *ddrCtlAddr;
+ /** DDR Config data */
+ LPDDR4_Config boardDdrCfg;
+ /** DDR Private data */
+ LPDDR4_PrivateData boardDdrPd;
+ /** Pointer to DDR control register array */
+ uint32_t *ddrCtlReg;
+ /** Pointer to DDR PHY register array */
+ uint32_t *ddrPhyIndepReg;
+ /** Pointer to DDR PHY register array */
+ uint32_t *ddrPhyReg;
+} Board_DdrObject_t;
+
+typedef Board_DdrObject_t * Board_DdrHandle;
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* BOARD_DDR_H_ */
diff --git a/packages/ti/board/src/j721s2_evm/include/board_ddrRegInit.h b/packages/ti/board/src/j721s2_evm/include/board_ddrRegInit.h
--- /dev/null
@@ -0,0 +1,6621 @@
+/* Copyright (c) 2021, Texas Instruments Incorporated
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
+
+/*
+ * This file was generated by the Jacinto7_DDRSS_RegConfigTool, Revision: 0.7.0
+ * This file was generated on 10/25/2021
+*/
+
+#define DDRSS_PLL_FHS_CNT 10
+#define DDRSS_PLL_FREQUENCY_0 27500000
+#define DDRSS_PLL_FREQUENCY_1 1066500000
+#define DDRSS_PLL_FREQUENCY_2 1066500000
+
+#define DDRSS_CTL_REG_INIT_COUNT (459U)
+#define DDRSS_PHY_INDEP_REG_INIT_COUNT (300U)
+#define DDRSS_PHY_REG_INIT_COUNT (1423U)
+
+#define MULTI_DDR_CFG_INTRLV_GRAN 0
+#define MULTI_DDR_CFG_INTRLV_SIZE 11
+#define MULTI_DDR_CFG_ECC_ENABLE 0
+#define MULTI_DDR_CFG_HYBRID_SELECT 0
+#define MULTI_DDR_CFG_EMIFS_ACTIVE 3
+
+uint32_t DDRSS0_ctlReg[] = {
+ 0x00000B00U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00002AF8U,
+ 0x0001ADAFU,
+ 0x00000005U,
+ 0x0000006EU,
+ 0x000681C8U,
+ 0x004111C9U,
+ 0x00000005U,
+ 0x000010A9U,
+ 0x000681C8U,
+ 0x004111C9U,
+ 0x00000005U,
+ 0x000010A9U,
+ 0x01010000U,
+ 0x02011001U,
+ 0x02010000U,
+ 0x00020100U,
+ 0x0000000BU,
+ 0x0000001CU,
+ 0x00000000U,
+ 0x00000000U,
+ 0x03020200U,
+ 0x00005656U,
+ 0x00100000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x040C0000U,
+ 0x12481248U,
+ 0x00050804U,
+ 0x09040008U,
+ 0x15000204U,
+ 0x1760008BU,
+ 0x1500422BU,
+ 0x1760008BU,
+ 0x2000422BU,
+ 0x000A0A09U,
+ 0x0400078AU,
+ 0x1E161104U,
+ 0x10012458U,
+ 0x1E161110U,
+ 0x10012458U,
+ 0x02030410U,
+ 0x2C040500U,
+ 0x08292C29U,
+ 0x14000E0AU,
+ 0x04010A0AU,
+ 0x01010004U,
+ 0x04545408U,
+ 0x04313104U,
+ 0x00003131U,
+ 0x00010100U,
+ 0x03010000U,
+ 0x00001508U,
+ 0x000000CEU,
+ 0x0000032BU,
+ 0x00002073U,
+ 0x0000032BU,
+ 0x00002073U,
+ 0x00000005U,
+ 0x00050000U,
+ 0x00CB0012U,
+ 0x00CB0408U,
+ 0x00400408U,
+ 0x00120103U,
+ 0x00100005U,
+ 0x2F080010U,
+ 0x0505012FU,
+ 0x0401030AU,
+ 0x041E100BU,
+ 0x100B0401U,
+ 0x0001041EU,
+ 0x00160016U,
+ 0x033B033BU,
+ 0x033B033BU,
+ 0x03050505U,
+ 0x03010303U,
+ 0x200B100BU,
+ 0x04041004U,
+ 0x200B100BU,
+ 0x04041004U,
+ 0x03010000U,
+ 0x00010000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x01000000U,
+ 0x80104002U,
+ 0x00000000U,
+ 0x00040005U,
+ 0x00000000U,
+ 0x00050000U,
+ 0x00000004U,
+ 0x00000000U,
+ 0x00040005U,
+ 0x00000000U,
+ 0x00003380U,
+ 0x00003380U,
+ 0x00003380U,
+ 0x00003380U,
+ 0x00003380U,
+ 0x00000000U,
+ 0x000005A2U,
+ 0x00081CC0U,
+ 0x00081CC0U,
+ 0x00081CC0U,
+ 0x00081CC0U,
+ 0x00081CC0U,
+ 0x00000000U,
+ 0x0000E325U,
+ 0x00081CC0U,
+ 0x00081CC0U,
+ 0x00081CC0U,
+ 0x00081CC0U,
+ 0x00081CC0U,
+ 0x00000000U,
+ 0x0000E325U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x0B030500U,
+ 0x00040B04U,
+ 0x0A090000U,
+ 0x0A090701U,
+ 0x0900000EU,
+ 0x0907010AU,
+ 0x00000E0AU,
+ 0x07010A09U,
+ 0x000E0A09U,
+ 0x07000401U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x08080000U,
+ 0x01000000U,
+ 0x800000C0U,
+ 0x800000C0U,
+ 0x800000C0U,
+ 0x00000000U,
+ 0x00001500U,
+ 0x00000000U,
+ 0x00000001U,
+ 0x00000002U,
+ 0x0000100EU,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x000B0000U,
+ 0x000E0006U,
+ 0x000E0404U,
+ 0x00D601ABU,
+ 0x10100216U,
+ 0x01AB0216U,
+ 0x021600D6U,
+ 0x02161010U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x3FF40084U,
+ 0x33003FF4U,
+ 0x00003333U,
+ 0x56000000U,
+ 0x27270056U,
+ 0x0F0F0000U,
+ 0x16000000U,
+ 0x00841616U,
+ 0x3FF43FF4U,
+ 0x33333300U,
+ 0x00000000U,
+ 0x00565600U,
+ 0x00002727U,
+ 0x00000F0FU,
+ 0x16161600U,
+ 0x00000020U,
+ 0x00000000U,
+ 0x00000001U,
+ 0x00000000U,
+ 0x01000000U,
+ 0x00000001U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x02000000U,
+ 0x01080101U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00001000U,
+ 0x006403E8U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x15110000U,
+ 0x00040C18U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00030000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x01000200U,
+ 0x00370040U,
+ 0x00020008U,
+ 0x00400100U,
+ 0x00400855U,
+ 0x01000200U,
+ 0x08550040U,
+ 0x00000040U,
+ 0x006B0003U,
+ 0x0100006BU,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000202U,
+ 0x00001FFFU,
+ 0x3FFF2000U,
+ 0x03FF0000U,
+ 0x000103FFU,
+ 0x0FFF0B00U,
+ 0x01010001U,
+ 0x01010101U,
+ 0x01180101U,
+ 0x00030000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00040101U,
+ 0x04010100U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x03030300U,
+ 0x00000001U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x01000000U,
+ 0x00020201U,
+ 0x01000101U,
+ 0x01010001U,
+ 0x00010101U,
+ 0x050A0A03U,
+ 0x10081F1FU,
+ 0x00090310U,
+ 0x0B0C030FU,
+ 0x0B0C0306U,
+ 0x0C090006U,
+ 0x0100000CU,
+ 0x08040801U,
+ 0x00000004U,
+ 0x00000000U,
+ 0x00010000U,
+ 0x00280D00U,
+ 0x00000001U,
+ 0x00030001U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x01000000U,
+ 0x00000001U,
+ 0x00010100U,
+ 0x03030000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x000556AAU,
+ 0x000AAAAAU,
+ 0x000AA955U,
+ 0x00055555U,
+ 0x000B3133U,
+ 0x0004CD33U,
+ 0x0004CECCU,
+ 0x000B32CCU,
+ 0x00010300U,
+ 0x03000100U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00010000U,
+ 0x00000404U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x3A3A1B00U,
+ 0x000A0000U,
+ 0x0000019CU,
+ 0x00000200U,
+ 0x00000200U,
+ 0x00000200U,
+ 0x00000200U,
+ 0x000004D4U,
+ 0x00001018U,
+ 0x00000204U,
+ 0x000040E6U,
+ 0x00000200U,
+ 0x00000200U,
+ 0x00000200U,
+ 0x00000200U,
+ 0x0000C2B2U,
+ 0x000288FCU,
+ 0x00000E15U,
+ 0x000040E6U,
+ 0x00000200U,
+ 0x00000200U,
+ 0x00000200U,
+ 0x00000200U,
+ 0x0000C2B2U,
+ 0x000288FCU,
+ 0x02020E15U,
+ 0x03030202U,
+ 0x00000022U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00001403U,
+ 0x000007D0U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00030000U,
+ 0x0007001FU,
+ 0x001B0033U,
+ 0x001B0033U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x02000000U,
+ 0x01000404U,
+ 0x0B1E0B1EU,
+ 0x00000105U,
+ 0x00010101U,
+ 0x00010101U,
+ 0x00010001U,
+ 0x00000101U,
+ 0x02000201U,
+ 0x02010000U,
+ 0x00000200U,
+ 0x28060000U,
+ 0x00000128U,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+};
+
+uint32_t DDRSS0_phyIndepReg[] = {
+ 0x00000B00U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000101U,
+ 0x00640000U,
+ 0x00000001U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000007U,
+ 0x00010002U,
+ 0x0800000FU,
+ 0x00000103U,
+ 0x00000005U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00010100U,
+ 0x00280A00U,
+ 0x00000000U,
+ 0x0F000000U,
+ 0x00003200U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x01010102U,
+ 0x00000000U,
+ 0x000000AAU,
+ 0x00000055U,
+ 0x000000B5U,
+ 0x0000004AU,
+ 0x00000056U,
+ 0x000000A9U,
+ 0x000000A9U,
+ 0x000000B5U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x000F0F00U,
+ 0x0000001BU,
+ 0x000007D0U,
+ 0x00000300U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x01000000U,
+ 0x00010101U,
+ 0x00000000U,
+ 0x00030000U,
+ 0x0F000000U,
+ 0x00000017U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x0A0A140AU,
+ 0x10020101U,
+ 0x00020805U,
+ 0x01000404U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000100U,
+ 0x0001010FU,
+ 0x00340000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x0000FFFFU,
+ 0x00000000U,
+ 0x00080000U,
+ 0x02000200U,
+ 0x01000100U,
+ 0x01000000U,
+ 0x02000200U,
+ 0x00000200U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000400U,
+ 0x02010000U,
+ 0x00080003U,
+ 0x00080000U,
+ 0x00000001U,
+ 0x00000000U,
+ 0x0000AA00U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00010000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000008U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000002U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x0000000AU,
+ 0x00000019U,
+ 0x00000100U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x01000000U,
+ 0x00010003U,
+ 0x02000101U,
+ 0x01030001U,
+ 0x00010400U,
+ 0x06000105U,
+ 0x01070001U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00010001U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000401U,
+ 0x00000000U,
+ 0x00010000U,
+ 0x00000000U,
+ 0x2B2B0200U,
+ 0x00000034U,
+ 0x00000064U,
+ 0x00020064U,
+ 0x02000200U,
+ 0x48120C04U,
+ 0x00154812U,
+ 0x000000CEU,
+ 0x0000032BU,
+ 0x00002073U,
+ 0x0000032BU,
+ 0x04002073U,
+ 0x01010404U,
+ 0x00001501U,
+ 0x00150015U,
+ 0x01000100U,
+ 0x00000100U,
+ 0x00000000U,
+ 0x01010101U,
+ 0x00000101U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x15040000U,
+ 0x0E0E0215U,
+ 0x00040402U,
+ 0x000D0035U,
+ 0x00218049U,
+ 0x00218049U,
+ 0x01010101U,
+ 0x0004000EU,
+ 0x00040216U,
+ 0x01000216U,
+ 0x000F000FU,
+ 0x02170100U,
+ 0x01000217U,
+ 0x02170217U,
+ 0x32103200U,
+ 0x01013210U,
+ 0x0A070601U,
+ 0x1F130A0DU,
+ 0x1F130A14U,
+ 0x0000C014U,
+ 0x00C01000U,
+ 0x00C01000U,
+ 0x00021000U,
+ 0x0024000EU,
+ 0x00240216U,
+ 0x00110216U,
+ 0x32000056U,
+ 0x00000301U,
+ 0x005B0036U,
+ 0x03013212U,
+ 0x00003600U,
+ 0x3212005BU,
+ 0x09000301U,
+ 0x04010504U,
+ 0x040006C9U,
+ 0x0A032001U,
+ 0x2C31110AU,
+ 0x00002918U,
+ 0x6001071CU,
+ 0x1E202008U,
+ 0x2C311116U,
+ 0x00002918U,
+ 0x6001071CU,
+ 0x1E202008U,
+ 0x00019C16U,
+ 0x00001018U,
+ 0x000040E6U,
+ 0x000288FCU,
+ 0x000040E6U,
+ 0x000288FCU,
+ 0x033B0016U,
+ 0x0303033BU,
+ 0x002AF803U,
+ 0x0001ADAFU,
+ 0x00000005U,
+ 0x0000006EU,
+ 0x00000016U,
+ 0x000681C8U,
+ 0x0001ADAFU,
+ 0x00000005U,
+ 0x000010A9U,
+ 0x0000033BU,
+ 0x000681C8U,
+ 0x0001ADAFU,
+ 0x00000005U,
+ 0x000010A9U,
+ 0x0100033BU,
+ 0x00370040U,
+ 0x00010008U,
+ 0x08550040U,
+ 0x00010040U,
+ 0x08550040U,
+ 0x00000340U,
+ 0x006B006BU,
+ 0x08040404U,
+ 0x00000055U,
+ 0x55083C5AU,
+ 0x5A000000U,
+ 0x0055083CU,
+ 0x3C5A0000U,
+ 0x00005508U,
+ 0x0C3C5A00U,
+ 0x080F0E0DU,
+ 0x000B0A09U,
+ 0x00030201U,
+ 0x01000000U,
+ 0x04020201U,
+ 0x00080804U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00330084U,
+ 0x00160000U,
+ 0x56333FF4U,
+ 0x00160F27U,
+ 0x56333FF4U,
+ 0x00160F27U,
+ 0x00330084U,
+ 0x00160000U,
+ 0x56333FF4U,
+ 0x00160F27U,
+ 0x56333FF4U,
+ 0x00160F27U,
+ 0x00330084U,
+ 0x00160000U,
+ 0x56333FF4U,
+ 0x00160F27U,
+ 0x56333FF4U,
+ 0x00160F27U,
+ 0x00330084U,
+ 0x00160000U,
+ 0x56333FF4U,
+ 0x00160F27U,
+ 0x56333FF4U,
+ 0x00160F27U,
+ 0x00000000U,
+};
+
+uint32_t DDRSS0_phyReg[] = {
+ 0x000004F0U,
+ 0x00000000U,
+ 0x00030200U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x01030000U,
+ 0x00010000U,
+ 0x01030004U,
+ 0x01000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x01000001U,
+ 0x00000100U,
+ 0x000800C0U,
+ 0x060100CCU,
+ 0x00030066U,
+ 0x00000000U,
+ 0x00000301U,
+ 0x0000AAAAU,
+ 0x00005555U,
+ 0x0000B5B5U,
+ 0x00004A4AU,
+ 0x00005656U,
+ 0x0000A9A9U,
+ 0x0000A9A9U,
+ 0x0000B5B5U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x2A000000U,
+ 0x00000808U,
+ 0x0F000000U,
+ 0x00000F0FU,
+ 0x10200000U,
+ 0x0C002006U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x55555555U,
+ 0xAAAAAAAAU,
+ 0x55555555U,
+ 0xAAAAAAAAU,
+ 0x00005555U,
+ 0x01000100U,
+ 0x00800180U,
+ 0x00000001U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
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+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000100U,
+ 0x00000200U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00400000U,
+ 0x00000080U,
+ 0x00DCBA98U,
+ 0x03000000U,
+ 0x00200000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x0000002AU,
+ 0x00000015U,
+ 0x00000015U,
+ 0x0000002AU,
+ 0x00000033U,
+ 0x0000000CU,
+ 0x0000000CU,
+ 0x00000033U,
+ 0x00543210U,
+ 0x003F0000U,
+ 0x000F013FU,
+ 0x20202003U,
+ 0x00202020U,
+ 0x20008008U,
+ 0x00000810U,
+ 0x00000F00U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x000305CCU,
+ 0x00030000U,
+ 0x00000300U,
+ 0x00000300U,
+ 0x00000300U,
+ 0x00000300U,
+ 0x00000300U,
+ 0x42080010U,
+ 0x0000803EU,
+ 0x00000001U,
+ 0x01000102U,
+ 0x00008000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00010100U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00050000U,
+ 0x04000000U,
+ 0x00000055U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00002001U,
+ 0x0000400FU,
+ 0x50020028U,
+ 0x01010000U,
+ 0x80080001U,
+ 0x10200000U,
+ 0x00000008U,
+ 0x00000000U,
+ 0x01090E00U,
+ 0x00040101U,
+ 0x0000010FU,
+ 0x00000000U,
+ 0x0000FFFFU,
+ 0x00000000U,
+ 0x01010000U,
+ 0x01080402U,
+ 0x01200F02U,
+ 0x00194280U,
+ 0x00000004U,
+ 0x00052000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x01000000U,
+ 0x00000705U,
+ 0x00000054U,
+ 0x00030820U,
+ 0x00010820U,
+ 0x00010820U,
+ 0x00010820U,
+ 0x00010820U,
+ 0x00010820U,
+ 0x00010820U,
+ 0x00010820U,
+ 0x00010820U,
+ 0x00000000U,
+ 0x00000074U,
+ 0x00000400U,
+ 0x00000108U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x03000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x04102006U,
+ 0x00041020U,
+ 0x01C98C98U,
+ 0x3F400000U,
+ 0x3F3F1F3FU,
+ 0x0000001FU,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00010000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x76543210U,
+ 0x00010198U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00040700U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000002U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00080000U,
+ 0x000007FFU,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x000FFFFFU,
+ 0x000FFFFFU,
+ 0x0000FFFFU,
+ 0xFFFFFFF0U,
+ 0x030FFFFFU,
+ 0x01FFFFFFU,
+ 0x0000FFFFU,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x0001F7C0U,
+ 0x00000003U,
+ 0x00000000U,
+ 0x00001142U,
+ 0x010207ABU,
+ 0x01000080U,
+ 0x03900390U,
+ 0x03900390U,
+ 0x00000390U,
+ 0x00000390U,
+ 0x00000390U,
+ 0x00000390U,
+ 0x00000005U,
+ 0x01813FCCU,
+ 0x000000CCU,
+ 0x0C000DFFU,
+ 0x30000DFFU,
+ 0x3F0DFF11U,
+ 0x000100F0U,
+ 0x780DFFCCU,
+ 0x00007E31U,
+ 0x000CBF11U,
+ 0x01990010U,
+ 0x000CBF11U,
+ 0x01990010U,
+ 0x3F0DFF11U,
+ 0x00EF00F0U,
+ 0x3F0DFF11U,
+ 0x01FF00F0U,
+ 0x20040006U,
+};
+
+uint32_t DDRSS1_ctlReg[] = {
+ 0x00000B00U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00002AF8U,
+ 0x0001ADAFU,
+ 0x00000005U,
+ 0x0000006EU,
+ 0x000681C8U,
+ 0x004111C9U,
+ 0x00000005U,
+ 0x000010A9U,
+ 0x000681C8U,
+ 0x004111C9U,
+ 0x00000005U,
+ 0x000010A9U,
+ 0x01010000U,
+ 0x02011001U,
+ 0x02010000U,
+ 0x00020100U,
+ 0x0000000BU,
+ 0x0000001CU,
+ 0x00000000U,
+ 0x00000000U,
+ 0x03020200U,
+ 0x00005656U,
+ 0x00100000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x040C0000U,
+ 0x12481248U,
+ 0x00050804U,
+ 0x09040008U,
+ 0x15000204U,
+ 0x1760008BU,
+ 0x1500422BU,
+ 0x1760008BU,
+ 0x2000422BU,
+ 0x000A0A09U,
+ 0x0400078AU,
+ 0x1E161104U,
+ 0x10012458U,
+ 0x1E161110U,
+ 0x10012458U,
+ 0x02030410U,
+ 0x2C040500U,
+ 0x08292C29U,
+ 0x14000E0AU,
+ 0x04010A0AU,
+ 0x01010004U,
+ 0x04545408U,
+ 0x04313104U,
+ 0x00003131U,
+ 0x00010100U,
+ 0x03010000U,
+ 0x00001508U,
+ 0x000000CEU,
+ 0x0000032BU,
+ 0x00002073U,
+ 0x0000032BU,
+ 0x00002073U,
+ 0x00000005U,
+ 0x00050000U,
+ 0x00CB0012U,
+ 0x00CB0408U,
+ 0x00400408U,
+ 0x00120103U,
+ 0x00100005U,
+ 0x2F080010U,
+ 0x0505012FU,
+ 0x0401030AU,
+ 0x041E100BU,
+ 0x100B0401U,
+ 0x0001041EU,
+ 0x00160016U,
+ 0x033B033BU,
+ 0x033B033BU,
+ 0x03050505U,
+ 0x03010303U,
+ 0x200B100BU,
+ 0x04041004U,
+ 0x200B100BU,
+ 0x04041004U,
+ 0x03010000U,
+ 0x00010000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x01000000U,
+ 0x80104002U,
+ 0x00000000U,
+ 0x00040005U,
+ 0x00000000U,
+ 0x00050000U,
+ 0x00000004U,
+ 0x00000000U,
+ 0x00040005U,
+ 0x00000000U,
+ 0x00003380U,
+ 0x00003380U,
+ 0x00003380U,
+ 0x00003380U,
+ 0x00003380U,
+ 0x00000000U,
+ 0x000005A2U,
+ 0x00081CC0U,
+ 0x00081CC0U,
+ 0x00081CC0U,
+ 0x00081CC0U,
+ 0x00081CC0U,
+ 0x00000000U,
+ 0x0000E325U,
+ 0x00081CC0U,
+ 0x00081CC0U,
+ 0x00081CC0U,
+ 0x00081CC0U,
+ 0x00081CC0U,
+ 0x00000000U,
+ 0x0000E325U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x0B030500U,
+ 0x00040B04U,
+ 0x0A090000U,
+ 0x0A090701U,
+ 0x0900000EU,
+ 0x0907010AU,
+ 0x00000E0AU,
+ 0x07010A09U,
+ 0x000E0A09U,
+ 0x07000401U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x08080000U,
+ 0x01000000U,
+ 0x800000C0U,
+ 0x800000C0U,
+ 0x800000C0U,
+ 0x00000000U,
+ 0x00001500U,
+ 0x00000000U,
+ 0x00000001U,
+ 0x00000002U,
+ 0x0000100EU,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x000B0000U,
+ 0x000E0006U,
+ 0x000E0404U,
+ 0x00D601ABU,
+ 0x10100216U,
+ 0x01AB0216U,
+ 0x021600D6U,
+ 0x02161010U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x3FF40084U,
+ 0x33003FF4U,
+ 0x00003333U,
+ 0x56000000U,
+ 0x27270056U,
+ 0x0F0F0000U,
+ 0x16000000U,
+ 0x00841616U,
+ 0x3FF43FF4U,
+ 0x33333300U,
+ 0x00000000U,
+ 0x00565600U,
+ 0x00002727U,
+ 0x00000F0FU,
+ 0x16161600U,
+ 0x00000020U,
+ 0x00000000U,
+ 0x00000001U,
+ 0x00000000U,
+ 0x01000000U,
+ 0x00000001U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x02000000U,
+ 0x01080101U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00001000U,
+ 0x006403E8U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x15110000U,
+ 0x00040C18U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00030000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x01000200U,
+ 0x00370040U,
+ 0x00020008U,
+ 0x00400100U,
+ 0x00400855U,
+ 0x01000200U,
+ 0x08550040U,
+ 0x00000040U,
+ 0x006B0003U,
+ 0x0100006BU,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000202U,
+ 0x00001FFFU,
+ 0x3FFF2000U,
+ 0x03FF0000U,
+ 0x000103FFU,
+ 0x0FFF0B00U,
+ 0x01010001U,
+ 0x01010101U,
+ 0x01180101U,
+ 0x00030000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00040101U,
+ 0x04010100U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x03030300U,
+ 0x00000001U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x01000000U,
+ 0x00020201U,
+ 0x01000101U,
+ 0x01010001U,
+ 0x00010101U,
+ 0x050A0A03U,
+ 0x10081F1FU,
+ 0x00090310U,
+ 0x0B0C030FU,
+ 0x0B0C0306U,
+ 0x0C090006U,
+ 0x0100000CU,
+ 0x08040801U,
+ 0x00000004U,
+ 0x00000000U,
+ 0x00010000U,
+ 0x00280D00U,
+ 0x00000001U,
+ 0x00030001U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x01000000U,
+ 0x00000001U,
+ 0x00010100U,
+ 0x03030000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x000556AAU,
+ 0x000AAAAAU,
+ 0x000AA955U,
+ 0x00055555U,
+ 0x000B3133U,
+ 0x0004CD33U,
+ 0x0004CECCU,
+ 0x000B32CCU,
+ 0x00010300U,
+ 0x03000100U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00010000U,
+ 0x00000404U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x3A3A1B00U,
+ 0x000A0000U,
+ 0x0000019CU,
+ 0x00000200U,
+ 0x00000200U,
+ 0x00000200U,
+ 0x00000200U,
+ 0x000004D4U,
+ 0x00001018U,
+ 0x00000204U,
+ 0x000040E6U,
+ 0x00000200U,
+ 0x00000200U,
+ 0x00000200U,
+ 0x00000200U,
+ 0x0000C2B2U,
+ 0x000288FCU,
+ 0x00000E15U,
+ 0x000040E6U,
+ 0x00000200U,
+ 0x00000200U,
+ 0x00000200U,
+ 0x00000200U,
+ 0x0000C2B2U,
+ 0x000288FCU,
+ 0x02020E15U,
+ 0x03030202U,
+ 0x00000022U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00001403U,
+ 0x000007D0U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00030000U,
+ 0x0007001FU,
+ 0x001B0033U,
+ 0x001B0033U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x02000000U,
+ 0x01000404U,
+ 0x0B1E0B1EU,
+ 0x00000105U,
+ 0x00010101U,
+ 0x00010101U,
+ 0x00010001U,
+ 0x00000101U,
+ 0x02000201U,
+ 0x02010000U,
+ 0x00000200U,
+ 0x28060000U,
+ 0x00000128U,
+ 0xFFFFFFFFU,
+ 0xFFFFFFFFU,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+};
+
+uint32_t DDRSS1_phyIndepReg[] = {
+ 0x00000B00U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000101U,
+ 0x00640000U,
+ 0x00000001U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000007U,
+ 0x00010002U,
+ 0x0800000FU,
+ 0x00000103U,
+ 0x00000005U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00010100U,
+ 0x00280A00U,
+ 0x00000000U,
+ 0x0F000000U,
+ 0x00003200U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x01010102U,
+ 0x00000000U,
+ 0x000000AAU,
+ 0x00000055U,
+ 0x000000B5U,
+ 0x0000004AU,
+ 0x00000056U,
+ 0x000000A9U,
+ 0x000000A9U,
+ 0x000000B5U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x000F0F00U,
+ 0x0000001BU,
+ 0x000007D0U,
+ 0x00000300U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x01000000U,
+ 0x00010101U,
+ 0x00000000U,
+ 0x00030000U,
+ 0x0F000000U,
+ 0x00000017U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x0A0A140AU,
+ 0x10020101U,
+ 0x00020805U,
+ 0x01000404U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000100U,
+ 0x0001010FU,
+ 0x00340000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x0000FFFFU,
+ 0x00000000U,
+ 0x00080000U,
+ 0x02000200U,
+ 0x01000100U,
+ 0x01000000U,
+ 0x02000200U,
+ 0x00000200U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000400U,
+ 0x02010000U,
+ 0x00080003U,
+ 0x00080000U,
+ 0x00000001U,
+ 0x00000000U,
+ 0x0000AA00U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00010000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000008U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000002U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x0000000AU,
+ 0x00000019U,
+ 0x00000100U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x01000000U,
+ 0x00010003U,
+ 0x02000101U,
+ 0x01030001U,
+ 0x00010400U,
+ 0x06000105U,
+ 0x01070001U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00010001U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000401U,
+ 0x00000000U,
+ 0x00010000U,
+ 0x00000000U,
+ 0x2B2B0200U,
+ 0x00000034U,
+ 0x00000064U,
+ 0x00020064U,
+ 0x02000200U,
+ 0x48120C04U,
+ 0x00154812U,
+ 0x000000CEU,
+ 0x0000032BU,
+ 0x00002073U,
+ 0x0000032BU,
+ 0x04002073U,
+ 0x01010404U,
+ 0x00001501U,
+ 0x00150015U,
+ 0x01000100U,
+ 0x00000100U,
+ 0x00000000U,
+ 0x01010101U,
+ 0x00000101U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x15040000U,
+ 0x0E0E0215U,
+ 0x00040402U,
+ 0x000D0035U,
+ 0x00218049U,
+ 0x00218049U,
+ 0x01010101U,
+ 0x0004000EU,
+ 0x00040216U,
+ 0x01000216U,
+ 0x000F000FU,
+ 0x02170100U,
+ 0x01000217U,
+ 0x02170217U,
+ 0x32103200U,
+ 0x01013210U,
+ 0x0A070601U,
+ 0x1F130A0DU,
+ 0x1F130A14U,
+ 0x0000C014U,
+ 0x00C01000U,
+ 0x00C01000U,
+ 0x00021000U,
+ 0x0024000EU,
+ 0x00240216U,
+ 0x00110216U,
+ 0x32000056U,
+ 0x00000301U,
+ 0x005B0036U,
+ 0x03013212U,
+ 0x00003600U,
+ 0x3212005BU,
+ 0x09000301U,
+ 0x04010504U,
+ 0x040006C9U,
+ 0x0A032001U,
+ 0x2C31110AU,
+ 0x00002918U,
+ 0x6001071CU,
+ 0x1E202008U,
+ 0x2C311116U,
+ 0x00002918U,
+ 0x6001071CU,
+ 0x1E202008U,
+ 0x00019C16U,
+ 0x00001018U,
+ 0x000040E6U,
+ 0x000288FCU,
+ 0x000040E6U,
+ 0x000288FCU,
+ 0x033B0016U,
+ 0x0303033BU,
+ 0x002AF803U,
+ 0x0001ADAFU,
+ 0x00000005U,
+ 0x0000006EU,
+ 0x00000016U,
+ 0x000681C8U,
+ 0x0001ADAFU,
+ 0x00000005U,
+ 0x000010A9U,
+ 0x0000033BU,
+ 0x000681C8U,
+ 0x0001ADAFU,
+ 0x00000005U,
+ 0x000010A9U,
+ 0x0100033BU,
+ 0x00370040U,
+ 0x00010008U,
+ 0x08550040U,
+ 0x00010040U,
+ 0x08550040U,
+ 0x00000340U,
+ 0x006B006BU,
+ 0x08040404U,
+ 0x00000055U,
+ 0x55083C5AU,
+ 0x5A000000U,
+ 0x0055083CU,
+ 0x3C5A0000U,
+ 0x00005508U,
+ 0x0C3C5A00U,
+ 0x080F0E0DU,
+ 0x000B0A09U,
+ 0x00030201U,
+ 0x01000000U,
+ 0x04020201U,
+ 0x00080804U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00330084U,
+ 0x00160000U,
+ 0x56333FF4U,
+ 0x00160F27U,
+ 0x56333FF4U,
+ 0x00160F27U,
+ 0x00330084U,
+ 0x00160000U,
+ 0x56333FF4U,
+ 0x00160F27U,
+ 0x56333FF4U,
+ 0x00160F27U,
+ 0x00330084U,
+ 0x00160000U,
+ 0x56333FF4U,
+ 0x00160F27U,
+ 0x56333FF4U,
+ 0x00160F27U,
+ 0x00330084U,
+ 0x00160000U,
+ 0x56333FF4U,
+ 0x00160F27U,
+ 0x56333FF4U,
+ 0x00160F27U,
+ 0x00000000U,
+};
+
+uint32_t DDRSS1_phyReg[] = {
+ 0x000004F0U,
+ 0x00000000U,
+ 0x00030200U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x01030000U,
+ 0x00010000U,
+ 0x01030004U,
+ 0x01000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x01000001U,
+ 0x00000100U,
+ 0x000800C0U,
+ 0x060100CCU,
+ 0x00030066U,
+ 0x00000000U,
+ 0x00000301U,
+ 0x0000AAAAU,
+ 0x00005555U,
+ 0x0000B5B5U,
+ 0x00004A4AU,
+ 0x00005656U,
+ 0x0000A9A9U,
+ 0x0000A9A9U,
+ 0x0000B5B5U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x2A000000U,
+ 0x00000808U,
+ 0x0F000000U,
+ 0x00000F0FU,
+ 0x10200000U,
+ 0x0C002006U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x55555555U,
+ 0xAAAAAAAAU,
+ 0x55555555U,
+ 0xAAAAAAAAU,
+ 0x00005555U,
+ 0x01000100U,
+ 0x00800180U,
+ 0x00000001U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000104U,
+ 0x00000120U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000001U,
+ 0x07FF0000U,
+ 0x0080081FU,
+ 0x00081020U,
+ 0x04010000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000100U,
+ 0x01CC0C01U,
+ 0x1003CC0CU,
+ 0x20000140U,
+ 0x07FF0200U,
+ 0x0000DD01U,
+ 0x10100303U,
+ 0x10101010U,
+ 0x10101010U,
+ 0x00021010U,
+ 0x00100010U,
+ 0x00100010U,
+ 0x00100010U,
+ 0x00100010U,
+ 0x00050010U,
+ 0x51517041U,
+ 0x31C06001U,
+ 0x07AB0340U,
+ 0x00C0C001U,
+ 0x0E0D0001U,
+ 0x10001000U,
+ 0x0C083E42U,
+ 0x0F0C3701U,
+ 0x01000140U,
+ 0x0C000420U,
+ 0x00000198U,
+ 0x0A0000D0U,
+ 0x00030200U,
+ 0x02800000U,
+ 0x80800000U,
+ 0x000E2010U,
+ 0x76543210U,
+ 0x00000008U,
+ 0x02800280U,
+ 0x02800280U,
+ 0x02800280U,
+ 0x02800280U,
+ 0x00000280U,
+ 0x0000A000U,
+ 0x00A000A0U,
+ 0x00A000A0U,
+ 0x00A000A0U,
+ 0x00A000A0U,
+ 0x00A000A0U,
+ 0x00A000A0U,
+ 0x00A000A0U,
+ 0x00A000A0U,
+ 0x01C200A0U,
+ 0x01A00005U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00080200U,
+ 0x00000000U,
+ 0x20202000U,
+ 0x20202020U,
+ 0xF0F02020U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x000004F0U,
+ 0x00000000U,
+ 0x00030200U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x01030000U,
+ 0x00010000U,
+ 0x01030004U,
+ 0x01000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x01000001U,
+ 0x00000100U,
+ 0x000800C0U,
+ 0x060100CCU,
+ 0x00030066U,
+ 0x00000000U,
+ 0x00000301U,
+ 0x0000AAAAU,
+ 0x00005555U,
+ 0x0000B5B5U,
+ 0x00004A4AU,
+ 0x00005656U,
+ 0x0000A9A9U,
+ 0x0000A9A9U,
+ 0x0000B5B5U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x2A000000U,
+ 0x00000808U,
+ 0x0F000000U,
+ 0x00000F0FU,
+ 0x10200000U,
+ 0x0C002006U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x55555555U,
+ 0xAAAAAAAAU,
+ 0x55555555U,
+ 0xAAAAAAAAU,
+ 0x00005555U,
+ 0x01000100U,
+ 0x00800180U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000104U,
+ 0x00000120U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000001U,
+ 0x07FF0000U,
+ 0x0080081FU,
+ 0x00081020U,
+ 0x04010000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000100U,
+ 0x01CC0C01U,
+ 0x1003CC0CU,
+ 0x20000140U,
+ 0x07FF0200U,
+ 0x0000DD01U,
+ 0x10100303U,
+ 0x10101010U,
+ 0x10101010U,
+ 0x00021010U,
+ 0x00100010U,
+ 0x00100010U,
+ 0x00100010U,
+ 0x00100010U,
+ 0x00050010U,
+ 0x51517041U,
+ 0x31C06001U,
+ 0x07AB0340U,
+ 0x00C0C001U,
+ 0x0E0D0001U,
+ 0x10001000U,
+ 0x0C083E42U,
+ 0x0F0C3701U,
+ 0x01000140U,
+ 0x0C000420U,
+ 0x00000198U,
+ 0x0A0000D0U,
+ 0x00030200U,
+ 0x02800000U,
+ 0x80800000U,
+ 0x000E2010U,
+ 0x76543210U,
+ 0x00000008U,
+ 0x02800280U,
+ 0x02800280U,
+ 0x02800280U,
+ 0x02800280U,
+ 0x00000280U,
+ 0x0000A000U,
+ 0x00A000A0U,
+ 0x00A000A0U,
+ 0x00A000A0U,
+ 0x00A000A0U,
+ 0x00A000A0U,
+ 0x00A000A0U,
+ 0x00A000A0U,
+ 0x00A000A0U,
+ 0x01C200A0U,
+ 0x01A00005U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00080200U,
+ 0x00000000U,
+ 0x20202000U,
+ 0x20202020U,
+ 0xF0F02020U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x000004F0U,
+ 0x00000000U,
+ 0x00030200U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x01030000U,
+ 0x00010000U,
+ 0x01030004U,
+ 0x01000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x01000001U,
+ 0x00000100U,
+ 0x000800C0U,
+ 0x060100CCU,
+ 0x00030066U,
+ 0x00000000U,
+ 0x00000301U,
+ 0x0000AAAAU,
+ 0x00005555U,
+ 0x0000B5B5U,
+ 0x00004A4AU,
+ 0x00005656U,
+ 0x0000A9A9U,
+ 0x0000A9A9U,
+ 0x0000B5B5U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x2A000000U,
+ 0x00000808U,
+ 0x0F000000U,
+ 0x00000F0FU,
+ 0x10200000U,
+ 0x0C002006U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x55555555U,
+ 0xAAAAAAAAU,
+ 0x55555555U,
+ 0xAAAAAAAAU,
+ 0x00005555U,
+ 0x01000100U,
+ 0x00800180U,
+ 0x00000001U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000104U,
+ 0x00000120U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000001U,
+ 0x07FF0000U,
+ 0x0080081FU,
+ 0x00081020U,
+ 0x04010000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000100U,
+ 0x01CC0C01U,
+ 0x1003CC0CU,
+ 0x20000140U,
+ 0x07FF0200U,
+ 0x0000DD01U,
+ 0x10100303U,
+ 0x10101010U,
+ 0x10101010U,
+ 0x00021010U,
+ 0x00100010U,
+ 0x00100010U,
+ 0x00100010U,
+ 0x00100010U,
+ 0x00050010U,
+ 0x51517041U,
+ 0x31C06001U,
+ 0x07AB0340U,
+ 0x00C0C001U,
+ 0x0E0D0001U,
+ 0x10001000U,
+ 0x0C083E42U,
+ 0x0F0C3701U,
+ 0x01000140U,
+ 0x0C000420U,
+ 0x00000198U,
+ 0x0A0000D0U,
+ 0x00030200U,
+ 0x02800000U,
+ 0x80800000U,
+ 0x000E2010U,
+ 0x76543210U,
+ 0x00000008U,
+ 0x02800280U,
+ 0x02800280U,
+ 0x02800280U,
+ 0x02800280U,
+ 0x00000280U,
+ 0x0000A000U,
+ 0x00A000A0U,
+ 0x00A000A0U,
+ 0x00A000A0U,
+ 0x00A000A0U,
+ 0x00A000A0U,
+ 0x00A000A0U,
+ 0x00A000A0U,
+ 0x00A000A0U,
+ 0x01C200A0U,
+ 0x01A00005U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00080200U,
+ 0x00000000U,
+ 0x20202000U,
+ 0x20202020U,
+ 0xF0F02020U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x000004F0U,
+ 0x00000000U,
+ 0x00030200U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x01030000U,
+ 0x00010000U,
+ 0x01030004U,
+ 0x01000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x01000001U,
+ 0x00000100U,
+ 0x000800C0U,
+ 0x060100CCU,
+ 0x00030066U,
+ 0x00000000U,
+ 0x00000301U,
+ 0x0000AAAAU,
+ 0x00005555U,
+ 0x0000B5B5U,
+ 0x00004A4AU,
+ 0x00005656U,
+ 0x0000A9A9U,
+ 0x0000A9A9U,
+ 0x0000B5B5U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x2A000000U,
+ 0x00000808U,
+ 0x0F000000U,
+ 0x00000F0FU,
+ 0x10200000U,
+ 0x0C002006U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x55555555U,
+ 0xAAAAAAAAU,
+ 0x55555555U,
+ 0xAAAAAAAAU,
+ 0x00005555U,
+ 0x01000100U,
+ 0x00800180U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000104U,
+ 0x00000120U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000001U,
+ 0x07FF0000U,
+ 0x0080081FU,
+ 0x00081020U,
+ 0x04010000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000100U,
+ 0x01CC0C01U,
+ 0x1003CC0CU,
+ 0x20000140U,
+ 0x07FF0200U,
+ 0x0000DD01U,
+ 0x10100303U,
+ 0x10101010U,
+ 0x10101010U,
+ 0x00021010U,
+ 0x00100010U,
+ 0x00100010U,
+ 0x00100010U,
+ 0x00100010U,
+ 0x00050010U,
+ 0x51517041U,
+ 0x31C06001U,
+ 0x07AB0340U,
+ 0x00C0C001U,
+ 0x0E0D0001U,
+ 0x10001000U,
+ 0x0C083E42U,
+ 0x0F0C3701U,
+ 0x01000140U,
+ 0x0C000420U,
+ 0x00000198U,
+ 0x0A0000D0U,
+ 0x00030200U,
+ 0x02800000U,
+ 0x80800000U,
+ 0x000E2010U,
+ 0x76543210U,
+ 0x00000008U,
+ 0x02800280U,
+ 0x02800280U,
+ 0x02800280U,
+ 0x02800280U,
+ 0x00000280U,
+ 0x0000A000U,
+ 0x00A000A0U,
+ 0x00A000A0U,
+ 0x00A000A0U,
+ 0x00A000A0U,
+ 0x00A000A0U,
+ 0x00A000A0U,
+ 0x00A000A0U,
+ 0x00A000A0U,
+ 0x01C200A0U,
+ 0x01A00005U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00080200U,
+ 0x00000000U,
+ 0x20202000U,
+ 0x20202020U,
+ 0xF0F02020U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000100U,
+ 0x00000200U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00400000U,
+ 0x00000080U,
+ 0x00DCBA98U,
+ 0x03000000U,
+ 0x00200000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x0000002AU,
+ 0x00000015U,
+ 0x00000015U,
+ 0x0000002AU,
+ 0x00000033U,
+ 0x0000000CU,
+ 0x0000000CU,
+ 0x00000033U,
+ 0x00543210U,
+ 0x003F0000U,
+ 0x000F013FU,
+ 0x20202003U,
+ 0x00202020U,
+ 0x20008008U,
+ 0x00000810U,
+ 0x00000F00U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x000305CCU,
+ 0x00030000U,
+ 0x00000300U,
+ 0x00000300U,
+ 0x00000300U,
+ 0x00000300U,
+ 0x00000300U,
+ 0x42080010U,
+ 0x0000803EU,
+ 0x00000001U,
+ 0x01000102U,
+ 0x00008000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00010100U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00050000U,
+ 0x04000000U,
+ 0x00000055U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00002001U,
+ 0x0000400FU,
+ 0x50020028U,
+ 0x01010000U,
+ 0x80080001U,
+ 0x10200000U,
+ 0x00000008U,
+ 0x00000000U,
+ 0x01090E00U,
+ 0x00040101U,
+ 0x0000010FU,
+ 0x00000000U,
+ 0x0000FFFFU,
+ 0x00000000U,
+ 0x01010000U,
+ 0x01080402U,
+ 0x01200F02U,
+ 0x00194280U,
+ 0x00000004U,
+ 0x00052000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x01000000U,
+ 0x00000705U,
+ 0x00000054U,
+ 0x00030820U,
+ 0x00010820U,
+ 0x00010820U,
+ 0x00010820U,
+ 0x00010820U,
+ 0x00010820U,
+ 0x00010820U,
+ 0x00010820U,
+ 0x00010820U,
+ 0x00000000U,
+ 0x00000074U,
+ 0x00000400U,
+ 0x00000108U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x03000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x04102006U,
+ 0x00041020U,
+ 0x01C98C98U,
+ 0x3F400000U,
+ 0x3F3F1F3FU,
+ 0x0000001FU,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00010000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x76543210U,
+ 0x00010198U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00040700U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000002U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00080000U,
+ 0x000007FFU,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x000FFFFFU,
+ 0x000FFFFFU,
+ 0x0000FFFFU,
+ 0xFFFFFFF0U,
+ 0x030FFFFFU,
+ 0x01FFFFFFU,
+ 0x0000FFFFU,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x00000000U,
+ 0x0001F7C0U,
+ 0x00000003U,
+ 0x00000000U,
+ 0x00001142U,
+ 0x010207ABU,
+ 0x01000080U,
+ 0x03900390U,
+ 0x03900390U,
+ 0x00000390U,
+ 0x00000390U,
+ 0x00000390U,
+ 0x00000390U,
+ 0x00000005U,
+ 0x01813FCCU,
+ 0x000000CCU,
+ 0x0C000DFFU,
+ 0x30000DFFU,
+ 0x3F0DFF11U,
+ 0x000100F0U,
+ 0x780DFFCCU,
+ 0x00007E31U,
+ 0x000CBF11U,
+ 0x01990010U,
+ 0x000CBF11U,
+ 0x01990010U,
+ 0x3F0DFF11U,
+ 0x00EF00F0U,
+ 0x3F0DFF11U,
+ 0x01FF00F0U,
+ 0x20040006U,
+};
+
+uint16_t DDRSS_ctlRegNum[] = {
+ 0,
+ 1,
+ 2,
+ 3,
+ 4,
+ 5,
+ 6,
+ 7,
+ 8,
+ 9,
+ 10,
+ 11,
+ 12,
+ 13,
+ 14,
+ 15,
+ 16,
+ 17,
+ 18,
+ 19,
+ 20,
+ 21,
+ 22,
+ 23,
+ 24,
+ 25,
+ 26,
+ 27,
+ 28,
+ 29,
+ 30,
+ 31,
+ 32,
+ 33,
+ 34,
+ 35,
+ 36,
+ 37,
+ 38,
+ 39,
+ 40,
+ 41,
+ 42,
+ 43,
+ 44,
+ 45,
+ 46,
+ 47,
+ 48,
+ 49,
+ 50,
+ 51,
+ 52,
+ 53,
+ 54,
+ 55,
+ 56,
+ 57,
+ 58,
+ 59,
+ 60,
+ 61,
+ 62,
+ 63,
+ 64,
+ 65,
+ 66,
+ 67,
+ 68,
+ 69,
+ 70,
+ 71,
+ 72,
+ 73,
+ 74,
+ 75,
+ 76,
+ 77,
+ 78,
+ 79,
+ 80,
+ 81,
+ 82,
+ 83,
+ 84,
+ 85,
+ 86,
+ 87,
+ 88,
+ 89,
+ 90,
+ 91,
+ 92,
+ 93,
+ 94,
+ 95,
+ 96,
+ 97,
+ 98,
+ 99,
+ 100,
+ 101,
+ 102,
+ 103,
+ 104,
+ 105,
+ 106,
+ 107,
+ 108,
+ 109,
+ 110,
+ 111,
+ 112,
+ 113,
+ 114,
+ 115,
+ 116,
+ 117,
+ 118,
+ 119,
+ 120,
+ 121,
+ 122,
+ 123,
+ 124,
+ 125,
+ 126,
+ 127,
+ 128,
+ 129,
+ 130,
+ 131,
+ 132,
+ 133,
+ 134,
+ 135,
+ 136,
+ 137,
+ 138,
+ 139,
+ 140,
+ 141,
+ 142,
+ 143,
+ 144,
+ 145,
+ 146,
+ 147,
+ 148,
+ 149,
+ 150,
+ 151,
+ 152,
+ 153,
+ 154,
+ 155,
+ 156,
+ 157,
+ 158,
+ 159,
+ 160,
+ 161,
+ 162,
+ 163,
+ 164,
+ 165,
+ 166,
+ 167,
+ 168,
+ 169,
+ 170,
+ 171,
+ 172,
+ 173,
+ 174,
+ 175,
+ 176,
+ 177,
+ 178,
+ 179,
+ 180,
+ 181,
+ 182,
+ 183,
+ 184,
+ 185,
+ 186,
+ 187,
+ 188,
+ 189,
+ 190,
+ 191,
+ 192,
+ 193,
+ 194,
+ 195,
+ 196,
+ 197,
+ 198,
+ 199,
+ 200,
+ 201,
+ 202,
+ 203,
+ 204,
+ 205,
+ 206,
+ 207,
+ 208,
+ 209,
+ 210,
+ 211,
+ 212,
+ 213,
+ 214,
+ 215,
+ 216,
+ 217,
+ 218,
+ 219,
+ 220,
+ 221,
+ 222,
+ 223,
+ 224,
+ 225,
+ 226,
+ 227,
+ 228,
+ 229,
+ 230,
+ 231,
+ 232,
+ 233,
+ 234,
+ 235,
+ 236,
+ 237,
+ 238,
+ 239,
+ 240,
+ 241,
+ 242,
+ 243,
+ 244,
+ 245,
+ 246,
+ 247,
+ 248,
+ 249,
+ 250,
+ 251,
+ 252,
+ 253,
+ 254,
+ 255,
+ 256,
+ 257,
+ 258,
+ 259,
+ 260,
+ 261,
+ 262,
+ 263,
+ 264,
+ 265,
+ 266,
+ 267,
+ 268,
+ 269,
+ 270,
+ 271,
+ 272,
+ 273,
+ 274,
+ 275,
+ 276,
+ 277,
+ 278,
+ 279,
+ 280,
+ 281,
+ 282,
+ 283,
+ 284,
+ 285,
+ 286,
+ 287,
+ 288,
+ 289,
+ 290,
+ 291,
+ 292,
+ 293,
+ 294,
+ 295,
+ 296,
+ 297,
+ 298,
+ 299,
+ 300,
+ 301,
+ 302,
+ 303,
+ 304,
+ 305,
+ 306,
+ 307,
+ 308,
+ 309,
+ 310,
+ 311,
+ 312,
+ 313,
+ 314,
+ 315,
+ 316,
+ 317,
+ 318,
+ 319,
+ 320,
+ 321,
+ 322,
+ 323,
+ 324,
+ 325,
+ 326,
+ 327,
+ 328,
+ 329,
+ 330,
+ 331,
+ 332,
+ 333,
+ 334,
+ 335,
+ 336,
+ 337,
+ 338,
+ 339,
+ 340,
+ 341,
+ 342,
+ 343,
+ 344,
+ 345,
+ 346,
+ 347,
+ 348,
+ 349,
+ 350,
+ 351,
+ 352,
+ 353,
+ 354,
+ 355,
+ 356,
+ 357,
+ 358,
+ 359,
+ 360,
+ 361,
+ 362,
+ 363,
+ 364,
+ 365,
+ 366,
+ 367,
+ 368,
+ 369,
+ 370,
+ 371,
+ 372,
+ 373,
+ 374,
+ 375,
+ 376,
+ 377,
+ 378,
+ 379,
+ 380,
+ 381,
+ 382,
+ 383,
+ 384,
+ 385,
+ 386,
+ 387,
+ 388,
+ 389,
+ 390,
+ 391,
+ 392,
+ 393,
+ 394,
+ 395,
+ 396,
+ 397,
+ 398,
+ 399,
+ 400,
+ 401,
+ 402,
+ 403,
+ 404,
+ 405,
+ 406,
+ 407,
+ 408,
+ 409,
+ 410,
+ 411,
+ 412,
+ 413,
+ 414,
+ 415,
+ 416,
+ 417,
+ 418,
+ 419,
+ 420,
+ 421,
+ 422,
+ 423,
+ 424,
+ 425,
+ 426,
+ 427,
+ 428,
+ 429,
+ 430,
+ 431,
+ 432,
+ 433,
+ 434,
+ 435,
+ 436,
+ 437,
+ 438,
+ 439,
+ 440,
+ 441,
+ 442,
+ 443,
+ 444,
+ 445,
+ 446,
+ 447,
+ 448,
+ 449,
+ 450,
+ 451,
+ 452,
+ 453,
+ 454,
+ 455,
+ 456,
+ 457,
+ 458,
+};
+
+uint16_t DDRSS_phyIndepRegNum[] = {
+ 0,
+ 1,
+ 2,
+ 3,
+ 4,
+ 5,
+ 6,
+ 7,
+ 8,
+ 9,
+ 10,
+ 11,
+ 12,
+ 13,
+ 14,
+ 15,
+ 16,
+ 17,
+ 18,
+ 19,
+ 20,
+ 21,
+ 22,
+ 23,
+ 24,
+ 25,
+ 26,
+ 27,
+ 28,
+ 29,
+ 30,
+ 31,
+ 32,
+ 33,
+ 34,
+ 35,
+ 36,
+ 37,
+ 38,
+ 39,
+ 40,
+ 41,
+ 42,
+ 43,
+ 44,
+ 45,
+ 46,
+ 47,
+ 48,
+ 49,
+ 50,
+ 51,
+ 52,
+ 53,
+ 54,
+ 55,
+ 56,
+ 57,
+ 58,
+ 59,
+ 60,
+ 61,
+ 62,
+ 63,
+ 64,
+ 65,
+ 66,
+ 67,
+ 68,
+ 69,
+ 70,
+ 71,
+ 72,
+ 73,
+ 74,
+ 75,
+ 76,
+ 77,
+ 78,
+ 79,
+ 80,
+ 81,
+ 82,
+ 83,
+ 84,
+ 85,
+ 86,
+ 87,
+ 88,
+ 89,
+ 90,
+ 91,
+ 92,
+ 93,
+ 94,
+ 95,
+ 96,
+ 97,
+ 98,
+ 99,
+ 100,
+ 101,
+ 102,
+ 103,
+ 104,
+ 105,
+ 106,
+ 107,
+ 108,
+ 109,
+ 110,
+ 111,
+ 112,
+ 113,
+ 114,
+ 115,
+ 116,
+ 117,
+ 118,
+ 119,
+ 120,
+ 121,
+ 122,
+ 123,
+ 124,
+ 125,
+ 126,
+ 127,
+ 128,
+ 129,
+ 130,
+ 131,
+ 132,
+ 133,
+ 134,
+ 135,
+ 136,
+ 137,
+ 138,
+ 139,
+ 140,
+ 141,
+ 142,
+ 143,
+ 144,
+ 145,
+ 146,
+ 147,
+ 148,
+ 149,
+ 150,
+ 151,
+ 152,
+ 153,
+ 154,
+ 155,
+ 156,
+ 157,
+ 158,
+ 159,
+ 160,
+ 161,
+ 162,
+ 163,
+ 164,
+ 165,
+ 166,
+ 167,
+ 168,
+ 169,
+ 170,
+ 171,
+ 172,
+ 173,
+ 174,
+ 175,
+ 176,
+ 177,
+ 178,
+ 179,
+ 180,
+ 181,
+ 182,
+ 183,
+ 184,
+ 185,
+ 186,
+ 187,
+ 188,
+ 189,
+ 190,
+ 191,
+ 192,
+ 193,
+ 194,
+ 195,
+ 196,
+ 197,
+ 198,
+ 199,
+ 200,
+ 201,
+ 202,
+ 203,
+ 204,
+ 205,
+ 206,
+ 207,
+ 208,
+ 209,
+ 210,
+ 211,
+ 212,
+ 213,
+ 214,
+ 215,
+ 216,
+ 217,
+ 218,
+ 219,
+ 220,
+ 221,
+ 222,
+ 223,
+ 224,
+ 225,
+ 226,
+ 227,
+ 228,
+ 229,
+ 230,
+ 231,
+ 232,
+ 233,
+ 234,
+ 235,
+ 236,
+ 237,
+ 238,
+ 239,
+ 240,
+ 241,
+ 242,
+ 243,
+ 244,
+ 245,
+ 246,
+ 247,
+ 248,
+ 249,
+ 250,
+ 251,
+ 252,
+ 253,
+ 254,
+ 255,
+ 256,
+ 257,
+ 258,
+ 259,
+ 260,
+ 261,
+ 262,
+ 263,
+ 264,
+ 265,
+ 266,
+ 267,
+ 268,
+ 269,
+ 270,
+ 271,
+ 272,
+ 273,
+ 274,
+ 275,
+ 276,
+ 277,
+ 278,
+ 279,
+ 280,
+ 281,
+ 282,
+ 283,
+ 284,
+ 285,
+ 286,
+ 287,
+ 288,
+ 289,
+ 290,
+ 291,
+ 292,
+ 293,
+ 294,
+ 295,
+ 296,
+ 297,
+ 298,
+ 299,
+};
+
+uint16_t DDRSS_phyRegNum[] = {
+ 0,
+ 1,
+ 2,
+ 3,
+ 4,
+ 5,
+ 6,
+ 7,
+ 8,
+ 9,
+ 10,
+ 11,
+ 12,
+ 13,
+ 14,
+ 15,
+ 16,
+ 17,
+ 18,
+ 19,
+ 20,
+ 21,
+ 22,
+ 23,
+ 24,
+ 25,
+ 26,
+ 27,
+ 28,
+ 29,
+ 30,
+ 31,
+ 32,
+ 33,
+ 34,
+ 35,
+ 36,
+ 37,
+ 38,
+ 39,
+ 40,
+ 41,
+ 42,
+ 43,
+ 44,
+ 45,
+ 46,
+ 47,
+ 48,
+ 49,
+ 50,
+ 51,
+ 52,
+ 53,
+ 54,
+ 55,
+ 56,
+ 57,
+ 58,
+ 59,
+ 60,
+ 61,
+ 62,
+ 63,
+ 64,
+ 65,
+ 66,
+ 67,
+ 68,
+ 69,
+ 70,
+ 71,
+ 72,
+ 73,
+ 74,
+ 75,
+ 76,
+ 77,
+ 78,
+ 79,
+ 80,
+ 81,
+ 82,
+ 83,
+ 84,
+ 85,
+ 86,
+ 87,
+ 88,
+ 89,
+ 90,
+ 91,
+ 92,
+ 93,
+ 94,
+ 95,
+ 96,
+ 97,
+ 98,
+ 99,
+ 100,
+ 101,
+ 102,
+ 103,
+ 104,
+ 105,
+ 106,
+ 107,
+ 108,
+ 109,
+ 110,
+ 111,
+ 112,
+ 113,
+ 114,
+ 115,
+ 116,
+ 117,
+ 118,
+ 119,
+ 120,
+ 121,
+ 122,
+ 123,
+ 124,
+ 125,
+ 126,
+ 127,
+ 128,
+ 129,
+ 130,
+ 131,
+ 132,
+ 133,
+ 134,
+ 135,
+ 136,
+ 137,
+ 138,
+ 139,
+ 140,
+ 141,
+ 142,
+ 143,
+ 144,
+ 145,
+ 146,
+ 147,
+ 148,
+ 149,
+ 150,
+ 151,
+ 152,
+ 153,
+ 154,
+ 155,
+ 156,
+ 157,
+ 158,
+ 159,
+ 160,
+ 161,
+ 162,
+ 163,
+ 164,
+ 165,
+ 166,
+ 167,
+ 168,
+ 169,
+ 170,
+ 171,
+ 172,
+ 173,
+ 174,
+ 175,
+ 176,
+ 177,
+ 178,
+ 179,
+ 180,
+ 181,
+ 182,
+ 183,
+ 184,
+ 185,
+ 186,
+ 187,
+ 188,
+ 189,
+ 190,
+ 191,
+ 192,
+ 193,
+ 194,
+ 195,
+ 196,
+ 197,
+ 198,
+ 199,
+ 200,
+ 201,
+ 202,
+ 203,
+ 204,
+ 205,
+ 206,
+ 207,
+ 208,
+ 209,
+ 210,
+ 211,
+ 212,
+ 213,
+ 214,
+ 215,
+ 216,
+ 217,
+ 218,
+ 219,
+ 220,
+ 221,
+ 222,
+ 223,
+ 224,
+ 225,
+ 226,
+ 227,
+ 228,
+ 229,
+ 230,
+ 231,
+ 232,
+ 233,
+ 234,
+ 235,
+ 236,
+ 237,
+ 238,
+ 239,
+ 240,
+ 241,
+ 242,
+ 243,
+ 244,
+ 245,
+ 246,
+ 247,
+ 248,
+ 249,
+ 250,
+ 251,
+ 252,
+ 253,
+ 254,
+ 255,
+ 256,
+ 257,
+ 258,
+ 259,
+ 260,
+ 261,
+ 262,
+ 263,
+ 264,
+ 265,
+ 266,
+ 267,
+ 268,
+ 269,
+ 270,
+ 271,
+ 272,
+ 273,
+ 274,
+ 275,
+ 276,
+ 277,
+ 278,
+ 279,
+ 280,
+ 281,
+ 282,
+ 283,
+ 284,
+ 285,
+ 286,
+ 287,
+ 288,
+ 289,
+ 290,
+ 291,
+ 292,
+ 293,
+ 294,
+ 295,
+ 296,
+ 297,
+ 298,
+ 299,
+ 300,
+ 301,
+ 302,
+ 303,
+ 304,
+ 305,
+ 306,
+ 307,
+ 308,
+ 309,
+ 310,
+ 311,
+ 312,
+ 313,
+ 314,
+ 315,
+ 316,
+ 317,
+ 318,
+ 319,
+ 320,
+ 321,
+ 322,
+ 323,
+ 324,
+ 325,
+ 326,
+ 327,
+ 328,
+ 329,
+ 330,
+ 331,
+ 332,
+ 333,
+ 334,
+ 335,
+ 336,
+ 337,
+ 338,
+ 339,
+ 340,
+ 341,
+ 342,
+ 343,
+ 344,
+ 345,
+ 346,
+ 347,
+ 348,
+ 349,
+ 350,
+ 351,
+ 352,
+ 353,
+ 354,
+ 355,
+ 356,
+ 357,
+ 358,
+ 359,
+ 360,
+ 361,
+ 362,
+ 363,
+ 364,
+ 365,
+ 366,
+ 367,
+ 368,
+ 369,
+ 370,
+ 371,
+ 372,
+ 373,
+ 374,
+ 375,
+ 376,
+ 377,
+ 378,
+ 379,
+ 380,
+ 381,
+ 382,
+ 383,
+ 384,
+ 385,
+ 386,
+ 387,
+ 388,
+ 389,
+ 390,
+ 391,
+ 392,
+ 393,
+ 394,
+ 395,
+ 396,
+ 397,
+ 398,
+ 399,
+ 400,
+ 401,
+ 402,
+ 403,
+ 404,
+ 405,
+ 406,
+ 407,
+ 408,
+ 409,
+ 410,
+ 411,
+ 412,
+ 413,
+ 414,
+ 415,
+ 416,
+ 417,
+ 418,
+ 419,
+ 420,
+ 421,
+ 422,
+ 423,
+ 424,
+ 425,
+ 426,
+ 427,
+ 428,
+ 429,
+ 430,
+ 431,
+ 432,
+ 433,
+ 434,
+ 435,
+ 436,
+ 437,
+ 438,
+ 439,
+ 440,
+ 441,
+ 442,
+ 443,
+ 444,
+ 445,
+ 446,
+ 447,
+ 448,
+ 449,
+ 450,
+ 451,
+ 452,
+ 453,
+ 454,
+ 455,
+ 456,
+ 457,
+ 458,
+ 459,
+ 460,
+ 461,
+ 462,
+ 463,
+ 464,
+ 465,
+ 466,
+ 467,
+ 468,
+ 469,
+ 470,
+ 471,
+ 472,
+ 473,
+ 474,
+ 475,
+ 476,
+ 477,
+ 478,
+ 479,
+ 480,
+ 481,
+ 482,
+ 483,
+ 484,
+ 485,
+ 486,
+ 487,
+ 488,
+ 489,
+ 490,
+ 491,
+ 492,
+ 493,
+ 494,
+ 495,
+ 496,
+ 497,
+ 498,
+ 499,
+ 500,
+ 501,
+ 502,
+ 503,
+ 504,
+ 505,
+ 506,
+ 507,
+ 508,
+ 509,
+ 510,
+ 511,
+ 512,
+ 513,
+ 514,
+ 515,
+ 516,
+ 517,
+ 518,
+ 519,
+ 520,
+ 521,
+ 522,
+ 523,
+ 524,
+ 525,
+ 526,
+ 527,
+ 528,
+ 529,
+ 530,
+ 531,
+ 532,
+ 533,
+ 534,
+ 535,
+ 536,
+ 537,
+ 538,
+ 539,
+ 540,
+ 541,
+ 542,
+ 543,
+ 544,
+ 545,
+ 546,
+ 547,
+ 548,
+ 549,
+ 550,
+ 551,
+ 552,
+ 553,
+ 554,
+ 555,
+ 556,
+ 557,
+ 558,
+ 559,
+ 560,
+ 561,
+ 562,
+ 563,
+ 564,
+ 565,
+ 566,
+ 567,
+ 568,
+ 569,
+ 570,
+ 571,
+ 572,
+ 573,
+ 574,
+ 575,
+ 576,
+ 577,
+ 578,
+ 579,
+ 580,
+ 581,
+ 582,
+ 583,
+ 584,
+ 585,
+ 586,
+ 587,
+ 588,
+ 589,
+ 590,
+ 591,
+ 592,
+ 593,
+ 594,
+ 595,
+ 596,
+ 597,
+ 598,
+ 599,
+ 600,
+ 601,
+ 602,
+ 603,
+ 604,
+ 605,
+ 606,
+ 607,
+ 608,
+ 609,
+ 610,
+ 611,
+ 612,
+ 613,
+ 614,
+ 615,
+ 616,
+ 617,
+ 618,
+ 619,
+ 620,
+ 621,
+ 622,
+ 623,
+ 624,
+ 625,
+ 626,
+ 627,
+ 628,
+ 629,
+ 630,
+ 631,
+ 632,
+ 633,
+ 634,
+ 635,
+ 636,
+ 637,
+ 638,
+ 639,
+ 640,
+ 641,
+ 642,
+ 643,
+ 644,
+ 645,
+ 646,
+ 647,
+ 648,
+ 649,
+ 650,
+ 651,
+ 652,
+ 653,
+ 654,
+ 655,
+ 656,
+ 657,
+ 658,
+ 659,
+ 660,
+ 661,
+ 662,
+ 663,
+ 664,
+ 665,
+ 666,
+ 667,
+ 668,
+ 669,
+ 670,
+ 671,
+ 672,
+ 673,
+ 674,
+ 675,
+ 676,
+ 677,
+ 678,
+ 679,
+ 680,
+ 681,
+ 682,
+ 683,
+ 684,
+ 685,
+ 686,
+ 687,
+ 688,
+ 689,
+ 690,
+ 691,
+ 692,
+ 693,
+ 694,
+ 695,
+ 696,
+ 697,
+ 698,
+ 699,
+ 700,
+ 701,
+ 702,
+ 703,
+ 704,
+ 705,
+ 706,
+ 707,
+ 708,
+ 709,
+ 710,
+ 711,
+ 712,
+ 713,
+ 714,
+ 715,
+ 716,
+ 717,
+ 718,
+ 719,
+ 720,
+ 721,
+ 722,
+ 723,
+ 724,
+ 725,
+ 726,
+ 727,
+ 728,
+ 729,
+ 730,
+ 731,
+ 732,
+ 733,
+ 734,
+ 735,
+ 736,
+ 737,
+ 738,
+ 739,
+ 740,
+ 741,
+ 742,
+ 743,
+ 744,
+ 745,
+ 746,
+ 747,
+ 748,
+ 749,
+ 750,
+ 751,
+ 752,
+ 753,
+ 754,
+ 755,
+ 756,
+ 757,
+ 758,
+ 759,
+ 760,
+ 761,
+ 762,
+ 763,
+ 764,
+ 765,
+ 766,
+ 767,
+ 768,
+ 769,
+ 770,
+ 771,
+ 772,
+ 773,
+ 774,
+ 775,
+ 776,
+ 777,
+ 778,
+ 779,
+ 780,
+ 781,
+ 782,
+ 783,
+ 784,
+ 785,
+ 786,
+ 787,
+ 788,
+ 789,
+ 790,
+ 791,
+ 792,
+ 793,
+ 794,
+ 795,
+ 796,
+ 797,
+ 798,
+ 799,
+ 800,
+ 801,
+ 802,
+ 803,
+ 804,
+ 805,
+ 806,
+ 807,
+ 808,
+ 809,
+ 810,
+ 811,
+ 812,
+ 813,
+ 814,
+ 815,
+ 816,
+ 817,
+ 818,
+ 819,
+ 820,
+ 821,
+ 822,
+ 823,
+ 824,
+ 825,
+ 826,
+ 827,
+ 828,
+ 829,
+ 830,
+ 831,
+ 832,
+ 833,
+ 834,
+ 835,
+ 836,
+ 837,
+ 838,
+ 839,
+ 840,
+ 841,
+ 842,
+ 843,
+ 844,
+ 845,
+ 846,
+ 847,
+ 848,
+ 849,
+ 850,
+ 851,
+ 852,
+ 853,
+ 854,
+ 855,
+ 856,
+ 857,
+ 858,
+ 859,
+ 860,
+ 861,
+ 862,
+ 863,
+ 864,
+ 865,
+ 866,
+ 867,
+ 868,
+ 869,
+ 870,
+ 871,
+ 872,
+ 873,
+ 874,
+ 875,
+ 876,
+ 877,
+ 878,
+ 879,
+ 880,
+ 881,
+ 882,
+ 883,
+ 884,
+ 885,
+ 886,
+ 887,
+ 888,
+ 889,
+ 890,
+ 891,
+ 892,
+ 893,
+ 894,
+ 895,
+ 896,
+ 897,
+ 898,
+ 899,
+ 900,
+ 901,
+ 902,
+ 903,
+ 904,
+ 905,
+ 906,
+ 907,
+ 908,
+ 909,
+ 910,
+ 911,
+ 912,
+ 913,
+ 914,
+ 915,
+ 916,
+ 917,
+ 918,
+ 919,
+ 920,
+ 921,
+ 922,
+ 923,
+ 924,
+ 925,
+ 926,
+ 927,
+ 928,
+ 929,
+ 930,
+ 931,
+ 932,
+ 933,
+ 934,
+ 935,
+ 936,
+ 937,
+ 938,
+ 939,
+ 940,
+ 941,
+ 942,
+ 943,
+ 944,
+ 945,
+ 946,
+ 947,
+ 948,
+ 949,
+ 950,
+ 951,
+ 952,
+ 953,
+ 954,
+ 955,
+ 956,
+ 957,
+ 958,
+ 959,
+ 960,
+ 961,
+ 962,
+ 963,
+ 964,
+ 965,
+ 966,
+ 967,
+ 968,
+ 969,
+ 970,
+ 971,
+ 972,
+ 973,
+ 974,
+ 975,
+ 976,
+ 977,
+ 978,
+ 979,
+ 980,
+ 981,
+ 982,
+ 983,
+ 984,
+ 985,
+ 986,
+ 987,
+ 988,
+ 989,
+ 990,
+ 991,
+ 992,
+ 993,
+ 994,
+ 995,
+ 996,
+ 997,
+ 998,
+ 999,
+ 1000,
+ 1001,
+ 1002,
+ 1003,
+ 1004,
+ 1005,
+ 1006,
+ 1007,
+ 1008,
+ 1009,
+ 1010,
+ 1011,
+ 1012,
+ 1013,
+ 1014,
+ 1015,
+ 1016,
+ 1017,
+ 1018,
+ 1019,
+ 1020,
+ 1021,
+ 1022,
+ 1023,
+ 1024,
+ 1025,
+ 1026,
+ 1027,
+ 1028,
+ 1029,
+ 1030,
+ 1031,
+ 1032,
+ 1033,
+ 1034,
+ 1035,
+ 1036,
+ 1037,
+ 1038,
+ 1039,
+ 1040,
+ 1041,
+ 1042,
+ 1043,
+ 1044,
+ 1045,
+ 1046,
+ 1047,
+ 1048,
+ 1049,
+ 1050,
+ 1051,
+ 1052,
+ 1053,
+ 1054,
+ 1055,
+ 1056,
+ 1057,
+ 1058,
+ 1059,
+ 1060,
+ 1061,
+ 1062,
+ 1063,
+ 1064,
+ 1065,
+ 1066,
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+ 1068,
+ 1069,
+ 1070,
+ 1071,
+ 1072,
+ 1073,
+ 1074,
+ 1075,
+ 1076,
+ 1077,
+ 1078,
+ 1079,
+ 1080,
+ 1081,
+ 1082,
+ 1083,
+ 1084,
+ 1085,
+ 1086,
+ 1087,
+ 1088,
+ 1089,
+ 1090,
+ 1091,
+ 1092,
+ 1093,
+ 1094,
+ 1095,
+ 1096,
+ 1097,
+ 1098,
+ 1099,
+ 1100,
+ 1101,
+ 1102,
+ 1103,
+ 1104,
+ 1105,
+ 1106,
+ 1107,
+ 1108,
+ 1109,
+ 1110,
+ 1111,
+ 1112,
+ 1113,
+ 1114,
+ 1115,
+ 1116,
+ 1117,
+ 1118,
+ 1119,
+ 1120,
+ 1121,
+ 1122,
+ 1123,
+ 1124,
+ 1125,
+ 1126,
+ 1127,
+ 1128,
+ 1129,
+ 1130,
+ 1131,
+ 1132,
+ 1133,
+ 1134,
+ 1135,
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+ 1138,
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+ 1140,
+ 1141,
+ 1142,
+ 1143,
+ 1144,
+ 1145,
+ 1146,
+ 1147,
+ 1148,
+ 1149,
+ 1150,
+ 1151,
+ 1152,
+ 1153,
+ 1154,
+ 1155,
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+ 1157,
+ 1158,
+ 1159,
+ 1160,
+ 1161,
+ 1162,
+ 1163,
+ 1164,
+ 1165,
+ 1166,
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+ 1168,
+ 1169,
+ 1170,
+ 1171,
+ 1172,
+ 1173,
+ 1174,
+ 1175,
+ 1176,
+ 1177,
+ 1178,
+ 1179,
+ 1180,
+ 1181,
+ 1182,
+ 1183,
+ 1184,
+ 1185,
+ 1186,
+ 1187,
+ 1188,
+ 1189,
+ 1190,
+ 1191,
+ 1192,
+ 1193,
+ 1194,
+ 1195,
+ 1196,
+ 1197,
+ 1198,
+ 1199,
+ 1200,
+ 1201,
+ 1202,
+ 1203,
+ 1204,
+ 1205,
+ 1206,
+ 1207,
+ 1208,
+ 1209,
+ 1210,
+ 1211,
+ 1212,
+ 1213,
+ 1214,
+ 1215,
+ 1216,
+ 1217,
+ 1218,
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+ 1220,
+ 1221,
+ 1222,
+ 1223,
+ 1224,
+ 1225,
+ 1226,
+ 1227,
+ 1228,
+ 1229,
+ 1230,
+ 1231,
+ 1232,
+ 1233,
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+ 1235,
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+ 1238,
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+ 1240,
+ 1241,
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+ 1244,
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+ 1246,
+ 1247,
+ 1248,
+ 1249,
+ 1250,
+ 1251,
+ 1252,
+ 1253,
+ 1254,
+ 1255,
+ 1256,
+ 1257,
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+ 1260,
+ 1261,
+ 1262,
+ 1263,
+ 1264,
+ 1265,
+ 1266,
+ 1267,
+ 1268,
+ 1269,
+ 1270,
+ 1271,
+ 1272,
+ 1273,
+ 1274,
+ 1275,
+ 1276,
+ 1277,
+ 1278,
+ 1279,
+ 1280,
+ 1281,
+ 1282,
+ 1283,
+ 1284,
+ 1285,
+ 1286,
+ 1287,
+ 1288,
+ 1289,
+ 1290,
+ 1291,
+ 1292,
+ 1293,
+ 1294,
+ 1295,
+ 1296,
+ 1297,
+ 1298,
+ 1299,
+ 1300,
+ 1301,
+ 1302,
+ 1303,
+ 1304,
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+ 1310,
+ 1311,
+ 1312,
+ 1313,
+ 1314,
+ 1315,
+ 1316,
+ 1317,
+ 1318,
+ 1319,
+ 1320,
+ 1321,
+ 1322,
+ 1323,
+ 1324,
+ 1325,
+ 1326,
+ 1327,
+ 1328,
+ 1329,
+ 1330,
+ 1331,
+ 1332,
+ 1333,
+ 1334,
+ 1335,
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+ 1340,
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+ 1344,
+ 1345,
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+ 1348,
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+ 1350,
+ 1351,
+ 1352,
+ 1353,
+ 1354,
+ 1355,
+ 1356,
+ 1357,
+ 1358,
+ 1359,
+ 1360,
+ 1361,
+ 1362,
+ 1363,
+ 1364,
+ 1365,
+ 1366,
+ 1367,
+ 1368,
+ 1369,
+ 1370,
+ 1371,
+ 1372,
+ 1373,
+ 1374,
+ 1375,
+ 1376,
+ 1377,
+ 1378,
+ 1379,
+ 1380,
+ 1381,
+ 1382,
+ 1383,
+ 1384,
+ 1385,
+ 1386,
+ 1387,
+ 1388,
+ 1389,
+ 1390,
+ 1391,
+ 1392,
+ 1393,
+ 1394,
+ 1395,
+ 1396,
+ 1397,
+ 1398,
+ 1399,
+ 1400,
+ 1401,
+ 1402,
+ 1403,
+ 1404,
+ 1405,
+ 1406,
+ 1407,
+ 1408,
+ 1409,
+ 1410,
+ 1411,
+ 1412,
+ 1413,
+ 1414,
+ 1415,
+ 1416,
+ 1417,
+ 1418,
+ 1419,
+ 1420,
+ 1421,
+ 1422,
+};
diff --git a/packages/ti/board/src/j721s2_evm/include/board_ethernet_config.h b/packages/ti/board/src/j721s2_evm/include/board_ethernet_config.h
--- /dev/null
@@ -0,0 +1,146 @@
+/******************************************************************************
+ * Copyright (c) 2021 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *****************************************************************************/
+
+ /**
+ * \brief board_ethernet_config.h
+ *
+ * This file contains Ethernet PHY configurations for the board
+ *
+ */
+
+#ifndef _BOARD_ETHERNET_CONFIG_H_
+#define _BOARD_ETHERNET_CONFIG_H_
+
+#include <ti/board/board.h>
+#include <ti/board/src/j721s2_evm/include/board_i2c_io_exp.h>
+#include <ti/board/src/j721s2_evm/include/board_control.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define RGMII_ID_DISABLE_MASK (0x10)
+
+typedef struct Board_pruicssMdioInfo
+{
+ uint32_t mdioBaseAddrs;
+ uint8_t phyAddrs;
+}Board_pruicssMdioInfo;
+
+/**
+ * \enum emac_mode
+ *
+ * \brief specifies the available emac mode types.
+ */
+typedef enum
+{
+ GMII = 0,
+ RMII,
+ RGMII,
+ SGMII,
+ QSGMII,
+ XFI,
+ QSGMII_SUB
+}emac_mode;
+
+/**
+ * \brief Board specific configurations for CPSW2G Main Domain Ethernet PHYs
+ *
+ * This function takes care of configuring the internal delays for CPSW2G Main Domain
+ * Ethernet PHYs
+ *
+ * \return BOARD_SOK in case of success or appropriate error code
+ */
+Board_STATUS Board_cpsw2gMainEthPhyConfig(void);
+
+/**
+ * \brief Board specific configurations for CPSW2G Ethernet PHY
+ *
+ * This function takes care of configuring the internal delays for MCU gigabit
+ * Ethernet PHY
+ *
+ * \return BOARD_SOK in case of success or appropriate error code
+ */
+Board_STATUS Board_cpsw2gEthPhyConfig(void);
+
+/**
+ * \brief Board specific configurations for CPSW2G Ethernet ports
+ *
+ * This function used to configures CPSW2G Ethernet controllers with the respective modes
+ *
+ * \return BOARD_SOK in case of success or appropriate error code
+ */
+Board_STATUS Board_ethConfigCpsw2g(void);
+
+/**
+ * \brief Board specific configurations for CPSW2G MAIN Domain Ethernet ports
+ *
+ * This function used to configures CPSW2G MAIN Domain Ethernet controllers with the respective modes
+ *
+ * \return BOARD_SOK in case of success or appropriate error code
+ */
+Board_STATUS Board_ethConfigCpsw2gMain(void);
+
+/**
+ * \brief Configures the CPSW2G Subsytem for RGMII mode
+ *
+ * \param portNum [IN] EMAC port number
+ * \param mode [IN] Mode selection for the specified port number
+ * 00 - GMII
+ * 01 - RMII
+ * 10 - RGMII
+ * 11 - SGMII
+ *
+ * \return BOARD_SOK in case of success or appropriate error code
+ */
+Board_STATUS Board_cpsw2gMacModeConfig(uint8_t mode);
+
+/**
+ * \brief Configures the CPSW2G Main Subsytem for RGMII and RMII mode
+ *
+ * \param mode [IN] Mode selection for the specified port number
+ * 000 - GMII
+ * 001 - RMII
+ * 010 - RGMII
+ * 011 - SGMII
+ * 100 - QSGMII
+ *
+ * \return BOARD_SOK in case of success or appropriate error code
+ */
+Board_STATUS Board_cpsw2gMainEthConfig(uint8_t mode);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _BOARD_ETHERNET_CONFIG_H_ */
diff --git a/packages/ti/board/src/j721s2_evm/include/board_i2c_io_exp.h b/packages/ti/board/src/j721s2_evm/include/board_i2c_io_exp.h
--- /dev/null
@@ -0,0 +1,366 @@
+/******************************************************************************
+ * Copyright (c) 2019 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *****************************************************************************/
+
+/**
+ * \file board_i2c_io_exp.h
+ *
+ * \brief I2C IO Expander configurations header file
+ *
+ * This file includes the structures, enums and register offsets
+ * for configuring the slave devices connected to I2C IO expander.
+ *
+ */
+
+#ifndef _BOARD_I2C_IO_EXP_H_
+#define _BOARD_I2C_IO_EXP_H_
+
+#include "board_internal.h"
+#include "board_utils.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdio.h>
+#include <stdint.h>
+#include <stdlib.h>
+#include <string.h>
+
+/* Input command for single port IO expander */
+#define BOARD_1PORT_IOEXP_INPUT_CMD (0x00U)
+
+/* Output command for single port IO expander */
+#define BOARD_1PORT_IOEXP_OUTPUT_CMD (0x01U)
+
+/* Polarity inversion command for single port IO expander */
+#define BOARD_1PORT_IOEXP_POLARITY_CMD (0x02U)
+
+/* Configuration command for single port IO expander */
+#define BOARD_1PORT_IOEXP_CONFIGURATION_CMD (0x03U)
+
+/* Input commands for two port IO expander */
+#define BOARD_2PORT_IOEXP_PORT0_INPUT_CMD (0x00U)
+#define BOARD_2PORT_IOEXP_PORT1_INPUT_CMD (0x01U)
+
+/* Output commands for two port IO expander */
+#define BOARD_2PORT_IOEXP_PORT0_OUTPUT_CMD (0x02U)
+#define BOARD_2PORT_IOEXP_PORT1_OUTPUT_CMD (0x03U)
+
+/* Polarity inversion commands for two port IO expander */
+#define BOARD_2PORT_IOEXP_PORT0_POLARITY_CMD (0x04U)
+#define BOARD_2PORT_IOEXP_PORT1_POLARITY_CMD (0x05U)
+
+/* Configuration commands for two port IO expander */
+#define BOARD_2PORT_IOEXP_PORT0_CONFIGURATION_CMD (0x06U)
+#define BOARD_2PORT_IOEXP_PORT1_CONFIGURATION_CMD (0x07U)
+
+/* Input commands for three port IO expander */
+#define BOARD_3PORT_IOEXP_PORT0_INPUT_CMD (0x00U)
+#define BOARD_3PORT_IOEXP_PORT1_INPUT_CMD (0x01U)
+#define BOARD_3PORT_IOEXP_PORT2_INPUT_CMD (0x02U)
+
+/* Output commands for three port IO expander */
+#define BOARD_3PORT_IOEXP_PORT0_OUTPUT_CMD (0x04U)
+#define BOARD_3PORT_IOEXP_PORT1_OUTPUT_CMD (0x05U)
+#define BOARD_3PORT_IOEXP_PORT2_OUTPUT_CMD (0x06U)
+
+/* Polarity inversion commands for three port IO expander */
+#define BOARD_3PORT_IOEXP_PORT0_POLARITY_CMD (0x08U)
+#define BOARD_3PORT_IOEXP_PORT1_POLARITY_CMD (0x09U)
+#define BOARD_3PORT_IOEXP_PORT2_POLARITY_CMD (0x0AU)
+
+/* Configuration commands for two port IO expander */
+#define BOARD_3PORT_IOEXP_PORT0_CONFIGURATION_CMD (0x0CU)
+#define BOARD_3PORT_IOEXP_PORT1_CONFIGURATION_CMD (0x0DU)
+#define BOARD_3PORT_IOEXP_PORT2_CONFIGURATION_CMD (0x0EU)
+
+/**
+ * \enum i2cIoExpType_t
+ *
+ * \brief specifies the available types of IO expander.
+ */
+typedef enum
+{
+ ONE_PORT_IOEXP = 0,
+ TWO_PORT_IOEXP,
+ THREE_PORT_IOEXP
+}i2cIoExpType_t;
+
+/**
+ * \enum i2cIoExpPortNumber_t
+ *
+ * \brief specifies the available port types.
+ */
+typedef enum
+{
+ PORTNUM_0 = 0,
+ PORTNUM_1,
+ PORTNUM_2
+}i2cIoExpPortNumber_t;
+
+/**
+ * \enum i2cIoExpPinNumber_t
+ *
+ * \brief specifies the available pin numbers.
+ */
+typedef enum
+{
+ PIN_NUM_0 = 0,
+ PIN_NUM_1,
+ PIN_NUM_2,
+ PIN_NUM_3,
+ PIN_NUM_4,
+ PIN_NUM_5,
+ PIN_NUM_6,
+ PIN_NUM_7
+}i2cIoExpPinNumber_t;
+
+/**
+ * \enum i2cIoExpPinDirection_t
+ *
+ * \brief specifies the available direction types.
+ */
+typedef enum
+{
+ PIN_DIRECTION_OUTPUT = 0,
+ PIN_DIRECTION_INPUT
+}i2cIoExpPinDirection_t;
+
+/**
+ * \enum i2cIoExpPinDirection_t
+ *
+ * \brief specifies the available signal levels.
+ */
+typedef enum
+{
+ GPIO_SIGNAL_LEVEL_LOW = 0,
+ GPIO_SIGNAL_LEVEL_HIGH
+}i2cIoExpSignalLevel_t;
+
+/**
+ * \brief Reads the current configuration of direction port.
+ *
+ * \param slaveAddr [IN] I2C Slave Address.
+ * \param ioExpType [IN] IO expander type.
+ * X_PORT_IOEXP - Total number of ports
+ * in slave device.
+ * \param portNum [IN] Port number of the i2c slave device
+ * PORTNUM_X - Port number of a slave
+ * device.
+ * \param data [IN/OUT] Pointer to the data buffer to store
+ * the pin level data of a specified port.
+ *
+ * \return Board_STATUS in case of success or appropriate error code.
+ *
+ */
+Board_STATUS Board_i2cIoExpReadDirPort(uint8_t slaveAddr,
+ i2cIoExpType_t ioExpType,
+ i2cIoExpPortNumber_t portNum,
+ uint8_t *data);
+
+/**
+ * \brief Reads the current configuration of output port.
+ *
+ * \param slaveAddr [IN] I2C Slave Address.
+ * \param ioExpType [IN] IO expander type.
+ * X_PORT_IOEXP - Total number of ports
+ * in slave device.
+ * \param portNum [IN] Port number of the i2c slave device
+ * PORTNUM_X - Port number of a slave
+ * device.
+ * \param data [IN/OUT] Pointer to the data buffer to store
+ * the pin level data of a specified port.
+ *
+ * \return Board_STATUS in case of success or appropriate error code.
+ *
+ */
+Board_STATUS Board_i2cIoExpReadOutputPort(uint8_t slaveAddr,
+ i2cIoExpType_t ioExpType,
+ i2cIoExpPortNumber_t portNum,
+ uint8_t *data);
+
+/**
+ * \brief Reads the signal level of all the pins of the specified port.
+ *
+ * \param slaveAddr [IN] I2C Slave Address.
+ * \param ioExpType [IN] IO expander type.
+ * X_PORT_IOEXP - Total number of ports
+ * in slave device.
+ * \param portNum [IN] Port number of the i2c slave device
+ * PORTNUM_X - Port number of a slave
+ * device.
+ * \param data [IN/OUT] Pointer to the data buffer to store
+ * the pin level data of a specified port.
+ *
+ * \return Board_STATUS in case of success or appropriate error code.
+ *
+ */
+Board_STATUS Board_i2cIoExpReadInputPort(uint8_t slaveAddr,
+ i2cIoExpType_t ioExpType,
+ i2cIoExpPortNumber_t portNum,
+ uint8_t *data);
+
+/**
+ * \brief Sets the direction of all the pins of the specified Port.
+ *
+ * \param slaveAddr [IN] I2C Slave Address.
+ * \param ioExpType [IN] IO expander type.
+ * X_PORT_IOEXP - Total number of ports
+ * in that slave device.
+ * \param portNum [IN] Port number of the i2c slave device
+ * PORTNUM_X - Port number of a
+ * slave device.
+ * \param data [IN] Register data to be configured.
+ *
+ * \return Board_STATUS in case of success or appropriate error code.
+ *
+ */
+Board_STATUS Board_i2cIoExpSetPortDirection(uint8_t slaveAddr,
+ i2cIoExpType_t ioExpType,
+ i2cIoExpPortNumber_t portNum,
+ uint8_t data);
+
+/**
+ * \brief Sets the direction of the specified pin of the specified port.
+ *
+ * \param slaveAddr [IN] I2C Slave Address.
+ * \param ioExpType [IN] IO expander type.
+ * X_PORT_IOEXP - Total number of ports
+ * in slave device.
+ * \param portNum [IN] Port number of the i2c slave device
+ * PORTNUM_X - Port number of a slave
+ * device.
+ * \param pinNum [IN] Pin with in the specified port of
+ * the i2c slave device.
+ * PIN_NUM_X - Pin number.
+ * \param direction [IN] Direction of the pin to be configured.
+ *
+ * \return Board_STATUS in case of success or appropriate error code.
+ *
+ */
+Board_STATUS Board_i2cIoExpSetPinDirection(uint8_t slaveAddr,
+ i2cIoExpType_t ioExpType,
+ i2cIoExpPortNumber_t portNum,
+ i2cIoExpPinNumber_t pinNum,
+ i2cIoExpPinDirection_t direction);
+
+/**
+ * \brief Sets the signal level of all the pins of the specified port.
+ *
+ * \param slaveAddr [IN] I2C Slave Address.
+ * \param ioExpType [IN] IO expander type.
+ * X_PORT_IOEXP - Total number of ports
+ * in slave device.
+ * \param portNum [IN] Port number of the i2c slave device
+ * PORTNUM_X - Port number of a slave
+ * device.
+ * \param data [IN] Signal level data of the pins to be
+ * configured.
+ *
+ * \return Board_STATUS in case of success or appropriate error code.
+ *
+ */
+Board_STATUS Board_i2cIoExpWritePort(uint8_t slaveAddr,
+ i2cIoExpType_t ioExpType,
+ i2cIoExpPortNumber_t portNum,
+ uint8_t data);
+
+/**
+ * \brief Sets the signal level of the specified pin of the specified port.
+ *
+ * \param slaveAddr [IN] I2C Slave Address.
+ * \param ioExpType [IN] IO expander type.
+ * X_PORT_IOEXP - Total number of ports
+ * in slave device.
+ * \param portNum [IN] Port number of the i2c slave device
+ * PORTNUM_X - Port number of a slave
+ * device.
+ * \param pinNum [IN] Pin with in the specified port of
+ * the i2c slave device.
+ * PIN_NUM_X - Pin number.
+ * \param signalLevel [IN] Signal level data of the pin to be
+ * configured.
+ *
+ * \return Board_STATUS in case of success or appropriate error code.
+ *
+ */
+Board_STATUS Board_i2cIoExpPinLevelSet(uint8_t slaveAddr,
+ i2cIoExpType_t ioExpType,
+ i2cIoExpPortNumber_t portNum,
+ i2cIoExpPinNumber_t pinNum,
+ i2cIoExpSignalLevel_t signalLevel);
+
+
+/**
+ * \brief Reads the signal level of specified pin of the specified port.
+ *
+ * \param slaveAddr [IN] I2C Slave Address.
+ * \param ioExpType [IN] IO expander type.
+ * X_PORT_IOEXP - Total number of ports
+ * in slave device.
+ * \param portNum [IN] Port number of the i2c slave device.
+ * PORTNUM_X - Port number of a slave
+ * device.
+ * \param pinNum [IN] Pin number of the specified port.
+ * PIN_NUM_X - Pin number.
+ * \param signalLevel [IN/OUT] Data buffer to store specified pin
+ * level of a specified port.
+ *
+ * \return Board_STATUS in case of success or appropriate error code.
+ *
+ */
+Board_STATUS Board_i2cIoExpPinLevelGet(uint8_t slaveAddr,
+ i2cIoExpType_t ioExpType,
+ i2cIoExpPortNumber_t portNum,
+ i2cIoExpPinNumber_t pinNum,
+ uint8_t *signalLevel);
+
+/**
+ * \brief Initializes the i2c instance connected to the i2c IO Expander.
+ *
+ * \return Board_STATUS in case of success or appropriate error code.
+ *
+ */
+Board_STATUS Board_i2cIoExpInit(void);
+
+/**
+ * \brief de-initializes the i2c instance connected to the i2c IO Expander.
+ *
+ */
+void Board_i2cIoExpDeInit(void);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _BOARD_I2C_IO_EXP_H_ */
diff --git a/packages/ti/board/src/j721s2_evm/include/board_internal.h b/packages/ti/board/src/j721s2_evm/include/board_internal.h
--- /dev/null
@@ -0,0 +1,438 @@
+/******************************************************************************
+ * Copyright (c) 2021 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *****************************************************************************/
+
+#ifndef BOARD_INTERNAL_H_
+#define BOARD_INTERNAL_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*****************************************************************************
+ * Include Files *
+ *****************************************************************************/
+#include <ti/csl/csl_types.h>
+#include <ti/csl/cslr_device.h>
+
+#include <ti/drv/i2c/I2C.h>
+#include <ti/drv/i2c/soc/I2C_soc.h>
+
+#include <ti/drv/uart/UART.h>
+#include <ti/drv/uart/UART_stdio.h>
+#include <ti/drv/uart/soc/UART_soc.h>
+
+#include <ti/board/board.h>
+#include <ti/csl/tistdtypes.h>
+#include <stdio.h>
+#include <stdbool.h>
+
+#define BOARD_I2C_PORT_CNT (I2C_HWIP_MAX_CNT)
+
+#undef ENABLE_LOGS
+
+#if !defined(BOARD_DEBUG_LOG)
+#if defined(ENABLE_LOGS)
+#define BOARD_DEBUG_LOG UART_printf
+#else
+#define BOARD_DEBUG_LOG(x, ...)
+#endif
+#endif /* #if !defined(BOARD_DEBUG_LOG) */
+
+/*****************************************************************************
+ * Internal Objects *
+ *****************************************************************************/
+extern I2C_config_list I2C_config;
+
+typedef struct Board_I2cObj_s
+{
+ I2C_Handle i2cHandle;
+ uint8_t i2cDomain;
+ uint32_t instNum;
+ uint32_t i2cBaseAddr;
+} Board_I2cObj_t;
+
+/****************************************************************************/
+
+#define BOARD_KICK0_UNLOCK_VAL (0x68EF3490U)
+#define BOARD_KICK1_UNLOCK_VAL (0xD172BC5AU)
+
+#define BOARD_KICK0_LOCK_VAL (0)
+#define BOARD_KICK1_LOCK_VAL (0)
+
+#define BOARD_MAC_COUNT_SHIFT (3U)
+#define BOARD_MAC_COUNT_MASK (0x00F8U)
+
+/* Ethenet board library MACROs */
+#define BOARD_ETHPHY_REGCR_REG_ADDR (0xDU)
+#define BOARD_ETHPHY_REGCR_ADDR_EN (0x1FU)
+#define BOARD_ETHPHY_REGCR_DATA_EN (0x401FU)
+#define BOARD_ETHPHY_ADDAR_REG_ADDR (0xEU)
+
+#define BOARD_ETHPHY_LEDCR1_REG_ADDR (0x18U)
+
+#define BOARD_ETHPHY_FLD_THRESH_REG_ADDR (0x2EU)
+
+#define BOARD_ETHPHY_RGMIICTL_REG_ADDR (0x32U)
+#define BOARD_ETHPHY_RGMIICTL_CLKDELAY_MASK (0x3U)
+#define BOARD_ETHPHY_RGMIICTL_TXDELAY_EN (0x2U)
+#define BOARD_ETHPHY_RGMIICTL_RXDELAY_EN (0x1U)
+
+#define BOARD_ETHPHY_STRAP_STS1_REG_ADDR (0x6EU)
+#define BOARD_ETHPHY_STRAP_STS2_REG_ADDR (0x6FU)
+
+#define BOARD_ETHPHY_RGMIIDCTL_REG_ADDR (0x86U)
+
+#define BOARD_ETHPHY_GPIO_MUX_CTRL2_REG_ADDR (0x172U)
+
+#define BOARD_ETHPHY_GPIO_MUX_CFG_REG_ADDR (0x170U)
+
+#define BOARD_ETHPHY_GPIO_MUX_CTRL2_REG_MASK (0xFU)
+#define BOARD_ETHPHY_GPIO_MUX_CTRL2_REG_CFG (0x6U)
+
+#define BOARD_ETHPHY_LEDCR1_REG_MASK (0xF000U)
+#define BOARD_ETHPHY_LEDCR1_REG_CFG (0x8000U)
+
+#define BOARD_ETHPHY_CPSW2G_MAIN_DELAY (0xA9U)
+#define BOARD_ETHPHY_CPSW9G_DELAY (0xA9U)
+#define BOARD_ETHPHY_CPSW2G_DELAY (0x77U)
+#define BOARD_ETHPHY_DELAY_CTRL (0xD3U)
+#define BOARD_ETHPHY_IO_IMPEDANCE (0x0C1FU)
+#define BOARD_CPSW_MDIO_REG_OFFSET (0xF00U)
+
+#define BOARD_MDIO_CTRL_REG_OFFSET (0x4U)
+#define BOARD_MDIO_CLK_DIV_CFG (0xFFU)
+#define BOARD_EMAC_DELAY_CFG (0x01000000U)
+
+#define BOARD_ETHPHY_STRAP_FLD_MASK (0x0400U)
+#define BOARD_ETHPHY_STRAP_FLD_THS_CHECK_FLAG (0x222U)
+
+#define BOARD_C66X_RAT_OFFSET (0x20000000U)
+#define BOARD_C66X_RAT_CONFIG (0x8000001DU)
+
+#if defined (_TMS320C6X)
+#define BOARD_CTRL_MMR0_CFG0_BASE (CSL_CTRL_MMR0_CFG0_BASE + BOARD_C66X_RAT_OFFSET)
+#else
+#define BOARD_CTRL_MMR0_CFG0_BASE (CSL_CTRL_MMR0_CFG0_BASE)
+#endif
+
+/* MAIN CTRL base address + offset to beginning of PAD CONFIG section */
+#define BOARD_MAIN_PMUX_CTRL_ADDR (BOARD_CTRL_MMR0_CFG0_BASE + 0x1C000)
+
+/* WKUP CTRL base address + offset to beginning of PAD CONFIG section proxy address */
+#define BOARD_WKUP_PMUX_CTRL_ADDR (CSL_WKUP_CTRL_MMR0_CFG0_BASE + 0x1C000)
+
+/* WKUP CTRL base address + offset to beginning of PAD CONFIG section */
+#define BOARD_MMR_PROXY1_OFFSET (0x2000U)
+
+#define BOARD_MAIN_MMR_P7_CLAIM_ADDR (0x11D100U)
+#define BOARD_WKUP_MMR_P7_CLAIM_ADDR (0x4301D100U)
+#define BOARD_WKUP_MMR_P7_CLAIM_OFFSET (0x1C000U)
+#define BOARD_MMR_CLAIM_ADDR_PER_REG (128U)
+
+/*********************XXXXXXXXXXXXXXXXXXXXX**********************/
+
+/*****************************************************************************
+ * Function Prototypes *
+ *****************************************************************************/
+
+
+/**
+ * \brief This function is to get the i2c handle of the requested
+ * instance of the specifed domain
+ *
+ * \param domainType [IN] Domain of I2C controller
+ * BOARD_SOC_DOMAIN_MAIN - Main Domain
+ * BOARD_SOC_DOMAIN_WKUP - Wakeup domain
+ * BOARD_SOC_DOMAIN_MCU - MCU domain
+ *
+ * \param i2cInst [IN] I2C instance
+ *
+ * \return Board_STATUS in case of success or appropriate error code.
+ *
+ */
+I2C_Handle Board_getI2CHandle(uint8_t domainType,
+ uint32_t i2cInst);
+
+/**
+ *
+ * \brief Board pinmuxing enable function
+ *
+ * Enables pinmux for the Maxwell idk board interfaces. Pin mux is done based on the
+ * default/primary functionality of the board. Any pins shared by multiple
+ * interfaces need to be reconfigured to access the secondary functionality.
+ *
+ * \return BOARD_SOK in case of success or appropriate error code
+ *
+ */
+Board_STATUS Board_pinmuxConfig(void);
+
+/**
+ * \brief Board pinmuxing enable function for main domain
+ *
+ * Enables pinmux for the board interfaces connected to main domain.
+ * Pin mux is done based on the default/primary functionality of the board.
+ * Any pins shared by multiple interfaces need to be reconfigured to access
+ * the secondary functionality.
+ *
+ * \param void
+ *
+ * \return BOARD_SOK in case of success or appropriate error code
+ *
+ */
+Board_STATUS Board_pinmuxConfigMain (void);
+
+/**
+ * \brief Board pinmuxing enable function for wakeup/mcu domain
+ *
+ * Enables pinmux for the board interfaces connected to wakeup/mcu domain.
+ * Pin mux is done based on the default/primary functionality of the board.
+ * Any pins shared by multiple interfaces need to be reconfigured to access
+ * the secondary functionality.
+ *
+ * \param void
+ *
+ * \return BOARD_SOK in case of success or appropriate error code
+ *
+ */
+Board_STATUS Board_pinmuxConfigWkup (void);
+
+/**
+ *
+ * \brief Board PLL initialization function
+ *
+ * Configures different PLL controller modules. This enables all the PLL
+ * controllers on the SoC with default configurations.
+ *
+ * \return BOARD_SOK in case of success or appropriate error code
+ */
+Board_STATUS Board_PLLInit(uint32_t modId, uint32_t clkId, uint64_t clkRate);
+
+/**
+ *
+ * \brief DDR4 Initialization function
+ *
+ * Initializes the DDR timing parameters. Sets the DDR timing parameters
+ * based in the DDR PLL controller configuration done by the board library.
+ * Any changes to DDR PLL requires change to DDR timing. Also supports
+ * enabling ECC
+ *
+ * \return BOARD_SOK in case of success or appropriate error code
+ *
+ */
+Board_STATUS Board_DDRInit(Bool eccEnable);
+
+#ifdef BOARD_DDR_ENABLE_DDR_MEM_PRIME
+/**
+ *
+ * \brief DDR4 Prime with UDMA Function
+ *
+ * Prime DDR memory using UDMA for ECC
+ *
+ * \param startAddr [in] Base Address
+ * \param size [in] Size in bytes
+ *
+ * \return BOARD_SOK in case of success or appropriate error code
+ *
+ */
+Board_STATUS BOARD_udmaPrimeDDR(void *startAddr, uint32_t size);
+#endif
+
+/**
+ * \brief clock Initialization function for MCU domain
+ *
+ * Enables different power domains and peripheral clocks of the MCU.
+ * Some of the power domains and peripherals will be OFF by default.
+ * Enabling the power domains is mandatory before accessing using
+ * board interfaces connected to those peripherals.
+ *
+ * \return BOARD_SOK - Clock initialization successful.
+ * BOARD_INIT_CLOCK_FAIL - Clock initialization failed.
+ *
+ */
+Board_STATUS Board_moduleClockInitMcu(void);
+
+/**
+ * \brief clock Initialization function for MAIN domain
+ *
+ * Enables different power domains and peripheral clocks of the SoC.
+ * Some of the power domains and peripherals will be OFF by default.
+ * Enabling the power domains is mandatory before accessing using
+ * board interfaces connected to those peripherals.
+ *
+ * \return BOARD_SOK - Clock initialization successful.
+ * BOARD_INIT_CLOCK_FAIL - Clock initialization failed.
+ *
+ */
+Board_STATUS Board_moduleClockInitMain(void);
+
+/**
+ * \brief clock de-initialization function for MCU domain
+ *
+ * Disables different power domains and peripheral clocks of the MCU.
+ *
+ * \return BOARD_SOK - Clock de-initialization successful.
+ * BOARD_INIT_CLOCK_FAIL - Clock de-initialization failed.
+ *
+ */
+Board_STATUS Board_moduleClockDeinitMcu(void);
+
+/**
+ * \brief clock de-initialization function for MAIN domain
+ *
+ * Disables different power domains and peripheral clocks of the SoC.
+ *
+ * \return BOARD_SOK - Clock de-initialization successful.
+ * BOARD_INIT_CLOCK_FAIL - Clock de-initialization failed.
+ *
+ */
+Board_STATUS Board_moduleClockDeinitMain(void);
+
+/**
+ * \brief Board specific configurations for CPSW2G Ethernet PHY
+ *
+ * This function takes care of configuring the internal delays for MCU gigabit
+ * Ethernet PHY
+ *
+ * \return BOARD_SOK in case of success or appropriate error code
+ */
+Board_STATUS Board_cpsw2gEthPhyConfig(void);
+
+/**
+ * \brief This function initializes the default UART instance for use for
+ * console operations.
+ *
+ * \return Board_STATUS in case of success or appropriate error code.
+ *
+ */
+Board_STATUS Board_uartStdioInit(void);
+
+/**
+ * \brief Locks MMR registers
+ *
+ * \return Board_STATUS
+ */
+Board_STATUS Board_lockMMR(void);
+
+/**
+ * \brief Unlocks MMR registers
+ *
+ * \return Board_STATUS
+ */
+Board_STATUS Board_unlockMMR(void);
+
+/**
+ *
+ * \brief Board PLL initialization function for MCU domain
+ *
+ * Configures different PLL controller modules. This enables all the PLL
+ * controllers in the MCU domain with default configurations.
+ *
+ * \return BOARD_SOK in case of success or appropriate error code
+ */
+Board_STATUS Board_PLLInitMcu(void);
+
+/**
+ *
+ * \brief Board PLL initialization function for MAIN domain
+ *
+ * Configures different PLL controller modules. This enables all the PLL
+ * controllers in the MAIN domain with default configurations.
+ *
+ * \return BOARD_SOK in case of success or appropriate error code
+ */
+Board_STATUS Board_PLLInitMain(void);
+
+/**
+ * \brief This function initializes the i2c instance connected to
+ * different control modules on the board
+ *
+ * This function disables the interrupt mode as the Board i2c instance
+ * doesn't require interrupt mode and restores back original at the end.
+ *
+ * \return Board_STATUS in case of success or appropriate error code.
+ *
+ */
+Board_STATUS Board_i2cInit(void);
+
+/**
+ * \brief This function is used to close all the initialized board I2C handles.
+ *
+ * \return Board_STATUS in case of success or appropriate error code.
+ */
+Board_STATUS Board_i2cDeInit(void);
+
+/**
+ * \brief Function to programs VDD_CORE to 0.9V.
+ *
+ * \return BOARD_SOK in case of success or appropriate error code
+ *
+ */
+Board_STATUS Board_pmVDDCoreVoltageCfg(void);
+
+/**
+ * \brief Function to configure SD card voltage.
+ *
+ * \param vsel [IN] SD voltage selection. 0 for 1.8v, 1 for 3.3v
+ *
+ * \return BOARD_SOK in case of success or appropriate error code
+ *
+ */
+Board_STATUS Board_pmSdVoltageCtrl(uint8_t vsel);
+
+/**
+ * \brief This function is used to de-initialize board UART handles.
+ */
+Board_STATUS Board_uartDeInit(void);
+
+/**
+ * \brief Sets RAT configuration
+ *
+ * MAIN padconfig registers are not directly accessible for C66x core
+ * which requires RAT configuration for the access.
+ *
+ * \return None
+ */
+void Board_setRATCfg(void);
+
+/**
+ * \brief Restores RAT configuration
+ *
+ * \return None
+ */
+void Board_restoreRATCfg(void);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* BOARD_INTERNAL_H_ */
diff --git a/packages/ti/board/src/j721s2_evm/include/board_pinmux.h b/packages/ti/board/src/j721s2_evm/include/board_pinmux.h
--- /dev/null
@@ -0,0 +1,225 @@
+/******************************************************************************
+ * Copyright (c) 2021 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *****************************************************************************/
+
+/**
+ * \file board_pinmux.h
+ *
+ * \brief Board pinmux header files
+ *
+ */
+
+#ifndef _BOARD_PIN_MUX_H_
+#define _BOARD_PIN_MUX_H_
+
+/* ========================================================================== */
+/* Include Files */
+/* ========================================================================== */
+
+#include <ti/board/src/j721s2_evm/include/pinmux.h>
+#include <ti/board/src/j721s2_evm/J721S2_pinmux.h>
+#include <ti/csl/csl_types.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define BOARD_MODE_PIN_MASK (0xFU)
+#define BOARD_PINMUX_BIT_MASK (0xFFF8FFF0U)
+#define BOARD_GPIO_PIN_MUX_CFG (0x50007U)
+
+#define BOARD_PINMUX_CUSTOM (0) // Default
+#define BOARD_PINMUX_AUTO (1U)
+
+/* Structure to set the board pinmux configuration */
+typedef struct Board_PinmuxConfig_s
+{
+ /**
+ * Pinmux auto config control
+ * BOARD_PINMUX_CUSTOM(0) - Pinmux is based on other add-on card
+ * settings of the pinmux config.
+ * BOARD_PINMUX_AUTO(1) - Pinmux is based on board detection by
+ * reading the board ID info from EEPROM.
+ * When auto mode is enabled, all other below fields of
+ * pinmux config will be ignored.
+ */
+ uint8_t autoCfg;
+
+} Board_PinmuxConfig_t;
+
+/**
+ * \brief Sets pinmux mode for a pin in main domain
+ *
+ * Only pinmux mode is updated by this function. Other values of
+ * padconfig register remains unchanged after this function call.
+ *
+ * \param offset [IN] Pad config offset of the pin
+ * \param mode [IN] Pad config mux mode.
+ *
+ * \return None
+ */
+void Board_pinMuxSetMode(uint32_t offset, uint32_t mode);
+
+/**
+ * \brief Sets pinmux mode for a pin in wake-up domain
+ *
+ * Only pinmux mode is updated by this function. Other values of
+ * padconfig register remains unchanged after this function call.
+ *
+ * \param offset [IN] Pad config offset of the pin
+ * \param mode [IN] Pad config mux mode.
+ *
+ * \return None
+ */
+void Board_pinMuxSetModeWkup(uint32_t offset, uint32_t mode);
+
+/**
+ * \brief Sets padconfig register of a pin at given offset
+ *
+ * Configures whole padconfig register of the pin at given offset
+ * with the value in 'muxData'.
+ *
+ * \param domain [IN] SoC domain for pinmux
+ * \n BOARD_SOC_MAIN_DOMAIN - Main domain
+ * \n BOARD_SOC_WKUP_DOMAIN - Wakeup domain
+ *
+ * \param offset [IN] Pad config offset of the pin
+ * \param muxData [IN] Value to be written to padconfig register
+ *
+ * \return BOARD_SOK in case of success or appropriate error code
+ *
+ */
+Board_STATUS Board_pinmuxSetReg(uint8_t domain,
+ uint32_t offset,
+ uint32_t muxData);
+
+/**
+ * \brief Gets padconfig register of a pin at given offset
+ *
+ * \param domain [IN] SoC domain for pinmux
+ * \n BOARD_SOC_MAIN_DOMAIN - Main domain
+ * \n BOARD_SOC_WKUP_DOMAIN - Wakeup domain
+ * \param offset [IN] Pad config offset of the pin
+ * \param muxData [OUT] Value of padconfig register
+ *
+ * \return BOARD_SOK in case of success or appropriate error code
+ *
+ */
+Board_STATUS Board_pinmuxGetReg(uint8_t domain,
+ uint32_t offset,
+ uint32_t *muxData);
+
+/**
+ * \brief Sets the board pinmux configuration.
+ *
+ * There are multiple addon cards that can connected to baseboard and
+ * multiple addon cards can be connected to one expansion connector.
+ * Pinmux configured through Board_init will be set to a default
+ * combination of the boards which can be changed using this function.
+ *
+ * \n Usage:
+ * \n - Call Board_pinmuxGetCfg to get default pinmux config
+ * \n - Call Board_pinmuxSetCfg to change pinmux config
+ * \n - Call Board_init with pinmux flag to apply the updated pinmux config
+ *
+ * \param pinmuxCfg [IN] Pinmux configurations
+ *
+ * \return BOARD_SOK in case of success or appropriate error code
+ *
+ */
+Board_STATUS Board_pinmuxSetCfg(Board_PinmuxConfig_t *pinmuxCfg);
+
+/**
+ * \brief Gets the board pinmux configuration.
+ *
+ * There are multiple addon cards that can connected to baseboard and
+ * multiple addon cards can be connected to one expansion connector.
+ * Pinmux configured through Board_init will be set to a default
+ * combination of the boards which can be read using this function.
+ *
+ * \param pinmuxCfg [IN] Pinmux configurations
+ *
+ * \return BOARD_SOK in case of success or appropriate error code
+ *
+ */
+Board_STATUS Board_pinmuxGetCfg(Board_PinmuxConfig_t *pinmuxCfg);
+
+/**
+ * \brief Board pinmuxing update function
+ *
+ * Provides the option to configure/update the pinmux.
+ * This function can be used to change the pinmux set by
+ * Board_init by default.
+ *
+ * \param pinmuxData [IN] Pinmux data structure
+ * \param domain [IN] SoC domain for pinmux
+ * \n BOARD_SOC_MAIN_DOMAIN - Main domain
+ * \n BOARD_SOC_WKUP_DOMAIN - Wakeup domain
+ *
+ * \return BOARD_SOK in case of success or appropriate error code
+ *
+ */
+Board_STATUS Board_pinmuxUpdate (pinmuxBoardCfg_t *pinmuxData,
+ uint32_t domain);
+
+/**
+ * \brief Board pinmuxing enable function
+ *
+ * Enables pinmux for the board interfaces. Pin mux is done based
+ * on the default/primary functionality of the board. Any pins shared by
+ * multiple interfaces need to be reconfigured to access the secondary
+ * functionality.
+ *
+ * \param void
+ *
+ * \return BOARD_SOK in case of success or appropriate error code
+ *
+ */
+Board_STATUS Board_pinmuxConfig (void);
+
+/**
+ * \brief Board UART Tx pinmuxing enable function
+ *
+ * Enables pinmux for the UART Tx pin of the default UART instance used
+ * by ROM/SBL.
+ *
+ * \param void
+ *
+ * \return void
+ *
+ */
+void Board_uartTxPinmuxConfig(void);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* _BOARD_PIN_MUX_H_ */
diff --git a/packages/ti/board/src/j721s2_evm/include/board_pll.h b/packages/ti/board/src/j721s2_evm/include/board_pll.h
--- /dev/null
@@ -0,0 +1,1549 @@
+/******************************************************************************
+ * Copyright (c) 2021 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *****************************************************************************/
+
+/**
+ * \file board_pll.h
+ *
+ * \brief Board PLL configurations header file
+ *
+ * This file includes the structures, enums and register offsets
+ * for PLL configurations
+ *
+ */
+
+#ifndef BOARD_PLL_H
+#define BOARD_PLL_H
+
+#include "board_internal.h"
+#include "board_pll.h"
+#include "ti/csl/soc.h"
+#include <ti/csl/hw_types.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//Global definitions
+#define DEBUG 0 //turn on this for debugging messages
+
+#define M3_MCU_OFFSET (0x20000000)
+#define M3_MAIN_OFFSET (0x80000000)
+
+#define KICK0_UNLOCK 0x68EF3490
+#define KICK1_UNLOCK 0xD172BC5A
+#define KICK_LOCK 0x00000000
+
+#define MAIN_DOMAIN 0
+#define MCU_DOMAIN 1
+
+#define CENTER_SPREAD 0
+#define DOWN_SPREAD 1
+
+#define FRAC_PLL 0
+#define FRAC_F_PLL 1
+#define DESKEW_PLL 2
+
+#define CSL_MAIN_PLL_MMR_CFG_PLL0_PID (0x00000000U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL0_MMR_CFG (0x00000008U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL0_LOCKKEY0 (0x00000010U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL0_LOCKKEY1 (0x00000014U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL0_CTRL (0x00000020U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL0_STAT (0x00000024U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL0_FREQ_CTRL0 (0x00000030U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL0_FREQ_CTRL1 (0x00000034U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL0_DIV_CTRL (0x00000038U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL0_SS_CTRL (0x00000040U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL0_SS_SPREAD (0x00000044U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL0_HSDIV_CTRL0 (0x00000080U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL0_HSDIV_CTRL1 (0x00000084U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL0_HSDIV_CTRL2 (0x00000088U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL0_HSDIV_CTRL3 (0x0000008CU)
+#define CSL_MAIN_PLL_MMR_CFG_PLL0_HSDIV_CTRL4 (0x00000090U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL0_HSDIV_CTRL5 (0x00000094U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL0_HSDIV_CTRL6 (0x00000098U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL0_HSDIV_CTRL7 (0x0000009CU)
+#define CSL_MAIN_PLL_MMR_CFG_PLL0_HSDIV_CTRL8 (0x000000A0U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL1_PID (0x00001000U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL1_MMR_CFG (0x00001008U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL1_LOCKKEY0 (0x00001010U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL1_LOCKKEY1 (0x00001014U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL1_CTRL (0x00001020U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL1_STAT (0x00001024U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL1_FREQ_CTRL0 (0x00001030U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL1_FREQ_CTRL1 (0x00001034U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL1_DIV_CTRL (0x00001038U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL1_SS_CTRL (0x00001040U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL1_SS_SPREAD (0x00001044U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL1_HSDIV_CTRL0 (0x00001080U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL1_HSDIV_CTRL1 (0x00001084U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL1_HSDIV_CTRL2 (0x00001088U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL1_HSDIV_CTRL3 (0x0000108CU)
+#define CSL_MAIN_PLL_MMR_CFG_PLL1_HSDIV_CTRL4 (0x00001090U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL1_HSDIV_CTRL5 (0x00001094U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL1_HSDIV_CTRL6 (0x00001098U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL1_HSDIV_CTRL7 (0x0000109CU)
+#define CSL_MAIN_PLL_MMR_CFG_PLL1_HSDIV_CTRL8 (0x000010A0U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL2_PID (0x00002000U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL2_MMR_CFG (0x00002008U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL2_LOCKKEY0 (0x00002010U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL2_LOCKKEY1 (0x00002014U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL2_CTRL (0x00002020U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL2_STAT (0x00002024U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL2_FREQ_CTRL0 (0x00002030U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL2_FREQ_CTRL1 (0x00002034U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL2_DIV_CTRL (0x00002038U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL2_SS_CTRL (0x00002040U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL2_SS_SPREAD (0x00002044U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL2_HSDIV_CTRL0 (0x00002080U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL2_HSDIV_CTRL1 (0x00002084U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL2_HSDIV_CTRL2 (0x00002088U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL2_HSDIV_CTRL3 (0x0000208CU)
+#define CSL_MAIN_PLL_MMR_CFG_PLL2_HSDIV_CTRL4 (0x00002090U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL2_HSDIV_CTRL5 (0x00002094U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL2_HSDIV_CTRL6 (0x00002098U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL2_HSDIV_CTRL7 (0x0000209CU)
+#define CSL_MAIN_PLL_MMR_CFG_PLL3_PID (0x00003000U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL3_MMR_CFG (0x00003008U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL3_LOCKKEY0 (0x00003010U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL3_LOCKKEY1 (0x00003014U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL3_CTRL (0x00003020U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL3_STAT (0x00003024U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL3_FREQ_CTRL0 (0x00003030U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL3_FREQ_CTRL1 (0x00003034U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL3_DIV_CTRL (0x00003038U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL3_SS_CTRL (0x00003040U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL3_SS_SPREAD (0x00003044U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL3_HSDIV_CTRL0 (0x00003080U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL3_HSDIV_CTRL1 (0x00003084U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL3_HSDIV_CTRL2 (0x00003088U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL3_HSDIV_CTRL3 (0x0000308CU)
+#define CSL_MAIN_PLL_MMR_CFG_PLL3_HSDIV_CTRL4 (0x00003090U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL4_PID (0x00004000U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL4_MMR_CFG (0x00004008U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL4_LOCKKEY0 (0x00004010U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL4_LOCKKEY1 (0x00004014U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL4_CTRL (0x00004020U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL4_STAT (0x00004024U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL4_FREQ_CTRL0 (0x00004030U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL4_FREQ_CTRL1 (0x00004034U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL4_DIV_CTRL (0x00004038U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL4_SS_CTRL (0x00004040U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL4_SS_SPREAD (0x00004044U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL4_HSDIV_CTRL0 (0x00004080U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL4_HSDIV_CTRL1 (0x00004084U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL4_HSDIV_CTRL2 (0x00004088U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL4_HSDIV_CTRL3 (0x0000408CU)
+#define CSL_MAIN_PLL_MMR_CFG_PLL5_PID (0x00005000U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL5_MMR_CFG (0x00005008U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL5_LOCKKEY0 (0x00005010U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL5_LOCKKEY1 (0x00005014U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL5_CTRL (0x00005020U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL5_STAT (0x00005024U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL5_FREQ_CTRL0 (0x00005030U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL5_FREQ_CTRL1 (0x00005034U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL5_DIV_CTRL (0x00005038U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL5_SS_CTRL (0x00005040U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL5_SS_SPREAD (0x00005044U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL5_HSDIV_CTRL0 (0x00005080U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL5_HSDIV_CTRL1 (0x00005084U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL5_HSDIV_CTRL2 (0x00005088U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL5_HSDIV_CTRL3 (0x0000508CU)
+#define CSL_MAIN_PLL_MMR_CFG_PLL6_PID (0x00006000U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL6_MMR_CFG (0x00006008U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL6_LOCKKEY0 (0x00006010U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL6_LOCKKEY1 (0x00006014U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL6_CTRL (0x00006020U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL6_STAT (0x00006024U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL6_FREQ_CTRL0 (0x00006030U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL6_FREQ_CTRL1 (0x00006034U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL6_DIV_CTRL (0x00006038U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL6_SS_CTRL (0x00006040U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL6_SS_SPREAD (0x00006044U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL6_HSDIV_CTRL0 (0x00006080U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL7_PID (0x00007000U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL7_MMR_CFG (0x00007008U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL7_LOCKKEY0 (0x00007010U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL7_LOCKKEY1 (0x00007014U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL7_CTRL (0x00007020U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL7_STAT (0x00007024U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL7_FREQ_CTRL0 (0x00007030U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL7_FREQ_CTRL1 (0x00007034U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL7_DIV_CTRL (0x00007038U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL7_SS_CTRL (0x00007040U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL7_SS_SPREAD (0x00007044U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL7_HSDIV_CTRL0 (0x00007080U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL8_PID (0x00008000U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL8_MMR_CFG (0x00008008U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL8_LOCKKEY0 (0x00008010U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL8_LOCKKEY1 (0x00008014U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL8_CTRL (0x00008020U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL8_STAT (0x00008024U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL8_FREQ_CTRL0 (0x00008030U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL8_FREQ_CTRL1 (0x00008034U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL8_DIV_CTRL (0x00008038U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL8_SS_CTRL (0x00008040U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL8_SS_SPREAD (0x00008044U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL8_HSDIV_CTRL0 (0x00008080U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL9_PID (0x00009000U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL9_MMR_CFG (0x00009008U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL9_LOCKKEY0 (0x00009010U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL9_LOCKKEY1 (0x00009014U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL9_CTRL (0x00009020U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL9_STAT (0x00009024U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL9_FREQ_CTRL0 (0x00009030U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL9_FREQ_CTRL1 (0x00009034U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL9_DIV_CTRL (0x00009038U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL9_SS_CTRL (0x00009040U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL9_SS_SPREAD (0x00009044U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL9_HSDIV_CTRL0 (0x00009080U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL12_PID (0x0000C000U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL12_MMR_CFG (0x0000C008U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL12_LOCKKEY0 (0x0000C010U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL12_LOCKKEY1 (0x0000C014U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL12_CTRL (0x0000C020U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL12_STAT (0x0000C024U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL12_FREQ_CTRL0 (0x0000C030U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL12_FREQ_CTRL1 (0x0000C034U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL12_DIV_CTRL (0x0000C038U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL12_SS_CTRL (0x0000C040U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL12_SS_SPREAD (0x0000C044U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL12_CAL_CTRL (0x0000C060U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL12_CAL_STAT (0x0000C064U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL12_HSDIV_CTRL0 (0x0000C080U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL13_PID (0x0000D000U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL13_MMR_CFG (0x0000D008U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL13_LOCKKEY0 (0x0000D010U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL13_LOCKKEY1 (0x0000D014U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL13_CTRL (0x0000D020U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL13_STAT (0x0000D024U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL13_FREQ_CTRL0 (0x0000D030U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL13_FREQ_CTRL1 (0x0000D034U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL13_DIV_CTRL (0x0000D038U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL13_SS_CTRL (0x0000D040U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL13_SS_SPREAD (0x0000D044U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL13_HSDIV_CTRL0 (0x0000D080U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL13_HSDIV_CTRL1 (0x0000D084U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL13_HSDIV_CTRL2 (0x0000D088U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL13_HSDIV_CTRL3 (0x0000D08CU)
+#define CSL_MAIN_PLL_MMR_CFG_PLL14_PID (0x0000E000U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL14_MMR_CFG (0x0000E008U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL14_LOCKKEY0 (0x0000E010U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL14_LOCKKEY1 (0x0000E014U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL14_CTRL (0x0000E020U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL14_STAT (0x0000E024U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL14_FREQ_CTRL0 (0x0000E030U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL14_FREQ_CTRL1 (0x0000E034U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL14_DIV_CTRL (0x0000E038U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL14_SS_CTRL (0x0000E040U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL14_SS_SPREAD (0x0000E044U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL14_HSDIV_CTRL0 (0x0000E080U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL14_HSDIV_CTRL1 (0x0000E084U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL15_PID (0x0000F000U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL15_MMR_CFG (0x0000F008U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL15_LOCKKEY0 (0x0000F010U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL15_LOCKKEY1 (0x0000F014U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL15_CTRL (0x0000F020U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL15_STAT (0x0000F024U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL15_FREQ_CTRL0 (0x0000F030U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL15_FREQ_CTRL1 (0x0000F034U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL15_DIV_CTRL (0x0000F038U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL15_SS_CTRL (0x0000F040U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL15_SS_SPREAD (0x0000F044U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL15_HSDIV_CTRL0 (0x0000F080U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL15_HSDIV_CTRL1 (0x0000F084U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL15_HSDIV_CTRL2 (0x0000F088U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL15_HSDIV_CTRL3 (0x0000F08CU)
+#define CSL_MAIN_PLL_MMR_CFG_PLL16_PID (0x00010000U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL16_MMR_CFG (0x00010008U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL16_LOCKKEY0 (0x00010010U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL16_LOCKKEY1 (0x00010014U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL16_CTRL (0x00010020U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL16_STAT (0x00010024U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL16_FREQ_CTRL0 (0x00010030U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL16_FREQ_CTRL1 (0x00010034U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL16_DIV_CTRL (0x00010038U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL16_SS_CTRL (0x00010040U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL16_SS_SPREAD (0x00010044U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL16_HSDIV_CTRL0 (0x00010080U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL16_HSDIV_CTRL1 (0x00010084U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL17_PID (0x00011000U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL17_MMR_CFG (0x00011008U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL17_LOCKKEY0 (0x00011010U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL17_LOCKKEY1 (0x00011014U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL17_CTRL (0x00011020U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL17_STAT (0x00011024U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL17_FREQ_CTRL0 (0x00011030U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL17_FREQ_CTRL1 (0x00011034U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL17_DIV_CTRL (0x00011038U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL17_SS_CTRL (0x00011040U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL17_SS_SPREAD (0x00011044U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL17_HSDIV_CTRL0 (0x00011080U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL17_HSDIV_CTRL1 (0x00011084U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL18_PID (0x00012000U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL18_MMR_CFG (0x00012008U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL18_LOCKKEY0 (0x00012010U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL18_LOCKKEY1 (0x00012014U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL18_CTRL (0x00012020U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL18_STAT (0x00012024U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL18_FREQ_CTRL0 (0x00012030U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL18_FREQ_CTRL1 (0x00012034U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL18_DIV_CTRL (0x00012038U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL18_SS_CTRL (0x00012040U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL18_SS_SPREAD (0x00012044U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL18_HSDIV_CTRL0 (0x00012080U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL18_HSDIV_CTRL1 (0x00012084U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL19_PID (0x00013000U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL19_MMR_CFG (0x00013008U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL19_LOCKKEY0 (0x00013010U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL19_LOCKKEY1 (0x00013014U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL19_CTRL (0x00013020U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL19_STAT (0x00013024U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL19_FREQ_CTRL0 (0x00013030U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL19_FREQ_CTRL1 (0x00013034U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL19_DIV_CTRL (0x00013038U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL19_SS_CTRL (0x00013040U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL19_SS_SPREAD (0x00013044U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL19_HSDIV_CTRL0 (0x00013080U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL19_HSDIV_CTRL1 (0x00013084U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL20_PID (0x00014000U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL20_MMR_CFG (0x00014008U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL20_LOCKKEY0 (0x00014010U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL20_LOCKKEY1 (0x00014014U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL20_CTRL (0x00014020U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL20_STAT (0x00014024U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL20_FREQ_CTRL0 (0x00014030U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL20_FREQ_CTRL1 (0x00014034U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL20_DIV_CTRL (0x00014038U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL20_SS_CTRL (0x00014040U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL20_SS_SPREAD (0x00014044U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL20_HSDIV_CTRL0 (0x00014080U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL20_HSDIV_CTRL1 (0x00014084U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL21_PID (0x00015000U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL21_MMR_CFG (0x00015008U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL21_LOCKKEY0 (0x00015010U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL21_LOCKKEY1 (0x00015014U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL21_CTRL (0x00015020U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL21_STAT (0x00015024U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL21_FREQ_CTRL0 (0x00015030U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL21_FREQ_CTRL1 (0x00015034U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL21_DIV_CTRL (0x00015038U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL21_SS_CTRL (0x00015040U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL21_SS_SPREAD (0x00015044U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL21_HSDIV_CTRL0 (0x00015080U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL21_HSDIV_CTRL1 (0x00015084U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL22_PID (0x00016000U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL22_MMR_CFG (0x00016008U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL22_LOCKKEY0 (0x00016010U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL22_LOCKKEY1 (0x00016014U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL22_CTRL (0x00016020U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL22_STAT (0x00016024U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL22_FREQ_CTRL0 (0x00016030U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL22_FREQ_CTRL1 (0x00016034U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL22_DIV_CTRL (0x00016038U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL22_SS_CTRL (0x00016040U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL22_SS_SPREAD (0x00016044U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL22_HSDIV_CTRL0 (0x00016080U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL22_HSDIV_CTRL1 (0x00016084U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL23_PID (0x00017000U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL23_MMR_CFG (0x00017008U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL23_LOCKKEY0 (0x00017010U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL23_LOCKKEY1 (0x00017014U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL23_CTRL (0x00017020U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL23_STAT (0x00017024U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL23_FREQ_CTRL0 (0x00017030U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL23_FREQ_CTRL1 (0x00017034U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL23_DIV_CTRL (0x00017038U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL23_SS_CTRL (0x00017040U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL23_SS_SPREAD (0x00017044U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL23_HSDIV_CTRL0 (0x00017080U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL23_HSDIV_CTRL1 (0x00017084U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL24_PID (0x00018000U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL24_MMR_CFG (0x00018008U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL24_LOCKKEY0 (0x00018010U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL24_LOCKKEY1 (0x00018014U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL24_PLL_CTRL (0x00018020U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL24_DSPLL_STAT (0x00018024U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL24_PLL_DIV_CTRL (0x00018038U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL24_PLL_TEST_CTRL (0x00018050U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL24_DSCAL_CTRL (0x00018060U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL24_DSCAL_STAT (0x00018064U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL24_HSDIV_CTRL0 (0x00018080U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL25_PID (0x00019000U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL25_MMR_CFG (0x00019008U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL25_LOCKKEY0 (0x00019010U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL25_LOCKKEY1 (0x00019014U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL25_CTRL (0x00019020U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL25_STAT (0x00019024U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL25_FREQ_CTRL0 (0x00019030U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL25_FREQ_CTRL1 (0x00019034U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL25_DIV_CTRL (0x00019038U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL25_SS_CTRL (0x00019040U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL25_SS_SPREAD (0x00019044U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL25_HSDIV_CTRL0 (0x00019080U)
+#define CSL_MAIN_PLL_MMR_CFG_PLL25_HSDIV_CTRL1 (0x00019084U)
+
+//MCU PLL ---------------------------------------------------------------------
+
+#define CSL_MCU_PLL_MMR_CFG_PLL0_PID (0x00000000U)
+#define CSL_MCU_PLL_MMR_CFG_PLL0_MMR_CFG (0x00000008U)
+#define CSL_MCU_PLL_MMR_CFG_PLL0_LOCKKEY0 (0x00000010U)
+#define CSL_MCU_PLL_MMR_CFG_PLL0_LOCKKEY1 (0x00000014U)
+#define CSL_MCU_PLL_MMR_CFG_PLL0_CTRL (0x00000020U)
+#define CSL_MCU_PLL_MMR_CFG_PLL0_STAT (0x00000024U)
+#define CSL_MCU_PLL_MMR_CFG_PLL0_FREQ_CTRL0 (0x00000030U)
+#define CSL_MCU_PLL_MMR_CFG_PLL0_FREQ_CTRL1 (0x00000034U)
+#define CSL_MCU_PLL_MMR_CFG_PLL0_DIV_CTRL (0x00000038U)
+#define CSL_MCU_PLL_MMR_CFG_PLL0_SS_CTRL (0x00000040U)
+#define CSL_MCU_PLL_MMR_CFG_PLL0_SS_SPREAD (0x00000044U)
+#define CSL_MCU_PLL_MMR_CFG_PLL0_HSDIV_CTRL0 (0x00000080U)
+#define CSL_MCU_PLL_MMR_CFG_PLL0_HSDIV_CTRL1 (0x00000084U)
+#define CSL_MCU_PLL_MMR_CFG_PLL1_PID (0x00001000U)
+#define CSL_MCU_PLL_MMR_CFG_PLL1_MMR_CFG (0x00001008U)
+#define CSL_MCU_PLL_MMR_CFG_PLL1_LOCKKEY0 (0x00001010U)
+#define CSL_MCU_PLL_MMR_CFG_PLL1_LOCKKEY1 (0x00001014U)
+#define CSL_MCU_PLL_MMR_CFG_PLL1_CTRL (0x00001020U)
+#define CSL_MCU_PLL_MMR_CFG_PLL1_STAT (0x00001024U)
+#define CSL_MCU_PLL_MMR_CFG_PLL1_FREQ_CTRL0 (0x00001030U)
+#define CSL_MCU_PLL_MMR_CFG_PLL1_FREQ_CTRL1 (0x00001034U)
+#define CSL_MCU_PLL_MMR_CFG_PLL1_DIV_CTRL (0x00001038U)
+#define CSL_MCU_PLL_MMR_CFG_PLL1_SS_CTRL (0x00001040U)
+#define CSL_MCU_PLL_MMR_CFG_PLL1_SS_SPREAD (0x00001044U)
+#define CSL_MCU_PLL_MMR_CFG_PLL1_HSDIV_CTRL0 (0x00001080U)
+#define CSL_MCU_PLL_MMR_CFG_PLL1_HSDIV_CTRL1 (0x00001084U)
+#define CSL_MCU_PLL_MMR_CFG_PLL1_HSDIV_CTRL2 (0x00001088U)
+#define CSL_MCU_PLL_MMR_CFG_PLL1_HSDIV_CTRL3 (0x0000108CU)
+#define CSL_MCU_PLL_MMR_CFG_PLL1_HSDIV_CTRL4 (0x00001090U)
+#define CSL_MCU_PLL_MMR_CFG_PLL2_PID (0x00002000U)
+#define CSL_MCU_PLL_MMR_CFG_PLL2_MMR_CFG (0x00002008U)
+#define CSL_MCU_PLL_MMR_CFG_PLL2_LOCKKEY0 (0x00002010U)
+#define CSL_MCU_PLL_MMR_CFG_PLL2_LOCKKEY1 (0x00002014U)
+#define CSL_MCU_PLL_MMR_CFG_PLL2_CTRL (0x00002020U)
+#define CSL_MCU_PLL_MMR_CFG_PLL2_STAT (0x00002024U)
+#define CSL_MCU_PLL_MMR_CFG_PLL2_FREQ_CTRL0 (0x00002030U)
+#define CSL_MCU_PLL_MMR_CFG_PLL2_FREQ_CTRL1 (0x00002034U)
+#define CSL_MCU_PLL_MMR_CFG_PLL2_DIV_CTRL (0x00002038U)
+#define CSL_MCU_PLL_MMR_CFG_PLL2_SS_CTRL (0x00002040U)
+#define CSL_MCU_PLL_MMR_CFG_PLL2_SS_SPREAD (0x00002044U)
+#define CSL_MCU_PLL_MMR_CFG_PLL2_HSDIV_CTRL0 (0x00002080U)
+#define CSL_MCU_PLL_MMR_CFG_PLL2_HSDIV_CTRL1 (0x00002084U)
+#define CSL_MCU_PLL_MMR_CFG_PLL2_HSDIV_CTRL2 (0x00002088U)
+#define CSL_MCU_PLL_MMR_CFG_PLL2_HSDIV_CTRL3 (0x0000208CU)
+#define CSL_MCU_PLL_MMR_CFG_PLL2_HSDIV_CTRL4 (0x00002090U)
+
+//PLL controller register offsets
+#define PLL_CTRL_PLLCTL_OFFSET 0x0100
+#define PLL_CTRL_OCSEL_OFFSET 0x0104
+#define PLL_CTRL_PREDIV_OFFSET 0x0114
+#define PLL_CTRL_PLLDIV1_OFFSET 0x0118
+#define PLL_CTRL_PLLDIV2_OFFSET 0x011C
+#define PLL_CTRL_PLLDIV3_OFFSET 0x0120
+#define PLL_CTRL_OSCDIV1_OFFSET 0x0124
+#define PLL_CTRL_POSTDIV_OFFSET 0x0128
+#define PLL_CTRL_BPDIV_OFFSET 0x012C
+#define PLL_CTRL_PLLCMD_OFFSET 0x0138
+#define PLL_CTRL_PLLSTAT_OFFSET 0x013C
+#define PLL_CTRL_ALNCTL_OFFSET 0x0140
+#define PLL_CTRL_CKEN_OFFSET 0x0148
+#define PLL_CTRL_CKSTAT_OFFSET 0x014C
+#define PLL_CTRL_SYSTAT_OFFSET 0x0150
+#define PLL_CTRL_PLLDIV4_OFFSET 0x0160
+#define PLL_CTRL_PLLDIV5_OFFSET 0x0164
+#define PLL_CTRL_PLLDIV6_OFFSET 0x0168
+#define PLL_CTRL_PLLDIV7_OFFSET 0x016C
+#define PLL_CTRL_PLLDIV8_OFFSET 0x0170
+#define PLL_CTRL_PLLDIV9_OFFSET 0x0174
+#define PLL_CTRL_PLLDIV10_OFFSET 0x0178
+#define PLL_CTRL_PLLDIV11_OFFSET 0x017C
+#define PLL_CTRL_PLLDIV12_OFFSET 0x0180
+#define PLL_CTRL_PLLDIV13_OFFSET 0x0184
+#define PLL_CTRL_PLLDIV14_OFFSET 0x0188
+#define PLL_CTRL_PLLDIV15_OFFSET 0x018C
+#define PLL_CTRL_PLLDIV16_OFFSET 0x0190
+
+//PLL Index Map
+#define MAIN_PLL_INDEX 0
+#define PER0_PLL_INDEX 1
+#define PER1_PLL_INDEX 2
+#define CPSW9_PLL_INDEX 3
+#define AUDIO0_PLL_INDEX 4
+#define VIDEO_PLL_INDEX 5
+#define GPU_PLL_INDEX 6
+#define C7X_PLL_INDEX 7
+#define ARM0_PLL_INDEX 8
+#define DDR_PLL_INDEX 12
+#define C66_PLL_INDEX 13
+#define MAIN_R5F_PLL_INDEX 14
+#define AUDIO1_PLL_INDEX 15
+#define DSS0_PLL_INDEX 16
+#define DSS1_PLL_INDEX 17
+#define DSS2_PLL_INDEX 18
+#define DSS3_PLL_INDEX 19
+#define DSS7_PLL_INDEX 23
+#define MLB_PLL_INDEX 24
+#define VISION_PLL_INDEX 25
+#define MCU_R5F_PLL_INDEX 0
+#define MCU_DOM_PLL_INDEX 1
+#define MCU_CPSW_PLL_INDEX 2
+
+//OFFSETS
+#define PLL_PID (0x00)
+#define PLL_CONFIG (0x08)
+#define CONTROL (0x20)
+#define STATUS (0x24)
+#define FREQ_CONTROL_0 (0x30)
+#define FREQ_CONTROL_1 (0x34)
+#define OUTPUT_DIV_CONTROL (0x38)
+#define SSMOD_CONTROL (0x40)
+#define SSMOD_SPREAD (0x44)
+#define HSDIV_0_CONTROL (0x80)
+#define HSDIV_1_CONTROL (0x84)
+#define HSDIV_2_CONTROL (0x88)
+#define HSDIV_3_CONTROL (0x8C)
+#define HSDIV_4_CONTROL (0x90)
+#define HSDIV_5_CONTROL (0x94)
+#define HSDIV_6_CONTROL (0x98)
+#define HSDIV_7_CONTROL (0x9C)
+
+//Special Programming Indices
+#define OFC1 0
+#define ARM_250MHZ 1
+#define ARM_500MHZ 2
+#define ARM_1GHZ 3
+#define ARM_2GHZ 4
+#define VPAC_720 5
+#define DMPAC_520 6
+#define DDR_BYPASS 7
+#define DDR_400 8
+#define DDR_800 9
+#define DDR_1066 10
+#define DDR_1600 11
+#define DDR_1866 12
+#define DDR_2133 13
+#define DDR_3200 14
+#define DSS_2970 15
+#define DSS_2345 16
+#define DSS_2898 17
+#define DSS_2613 18
+#define DSS_2133 19
+
+
+
+
+/*
+Note: if the HSDIV value is -1 that means it's either nonexistent or not used.
+Note: if the mod_div value is -1 that means it isn't programmed beyond the default value of "1", which means the input divider is set to divide-by-1.
+Note: the divider values here are directly programmed tothe HSDIV control MMR. They don't factor in the +1 that's added in the hardware.
+ Users should add +1 to the HSDIV divider values they add in here for any calculations they make outside of the GEL framework and the hardware.
+Note: This is configured for OFC1 as defined by SOCDV + Venkat.
+*/
+
+#define FREF 20.0 //20MHz HFOSC0 reference clock on QT
+#define FREF_SVB 25.0 //25MHz HFOSC0 reference clock on SVB
+
+/*#define CLKINP_QT 20.0
+#define CLKINP_SVB 25.0*/
+
+//PLL0: Main PLL
+/* Frequencies:
+
+PLL input: 20MHz
+VCO output: 2GHz
+POSTDIV output: 1GHz
+HSDIV0 output: 500MHz
+HSDIV1 output: 250MHz
+HSDIV2 output: 200MHz
+HSDIV3 output: 133.33MHz
+HSDIV4 output: 80MHz
+HSDIV5 output: 50MHz
+HSDIV6 output: 250MHz
+HSDIV7 output: 200MHz
+HSDIV8 output: 333.33MHz
+MODSS configuration:
+- Spread: 3.125%
+- Modulator Divider: %-by-1
+- Downspread or centerspread: downspread
+
+ */
+#define MAIN_PLL0_FBDIV 100 //fbdiv
+#define MAIN_PLL0_FRACDIV -1 //fracdiv
+#define MAIN_PLL0_PREDIV 1 //prediv
+#define MAIN_PLL0_POSTDIV1 2 //postdiv1
+#define MAIN_PLL0_POSTDIV2 1 //postdiv2
+#define MAIN_PLL0_HSDIV0_DIV_VAL 3 //4
+#define MAIN_PLL0_HSDIV1_DIV_VAL 7 //8
+#define MAIN_PLL0_HSDIV2_DIV_VAL 9 //10
+#define MAIN_PLL0_HSDIV3_DIV_VAL 14 //15
+#define MAIN_PLL0_HSDIV4_DIV_VAL 24 //25
+#define MAIN_PLL0_HSDIV5_DIV_VAL 19 //20
+#define MAIN_PLL0_HSDIV6_DIV_VAL 3 //4
+#define MAIN_PLL0_HSDIV7_DIV_VAL 4 //5
+#define MAIN_PLL0_HSDIV8_DIV_VAL 2 //3
+#define MAIN_PLL0_SSMOD_SPREAD 0x1F //spread
+#define MAIN_PLL0_SSMOD_MODDIV -1 //mod_div
+#define MAIN_PLL0_SSMOD_DOWNSPREAD 1 //downspread
+
+//Main PLL0 PLL Controller Parameters
+#define MAIN_CTRL_BPDIV 0 //AUXCLK=BPCLK=REFCLK for controller
+#define MAIN_CTRL_OD1 0 //OBSCLK=REFCLK for controller
+#define MAIN_CTRL_DIV1 1 //500MHZ SYSCLK1 from HSDIV_CLKOUT1
+
+
+//PLL1: Peripheral 0 PLL
+/* Frequencies:
+
+PLL input: 20MHz
+VCO output: 1920MHz
+POSTDIV output: 960MHz
+HSDIV0 output: 192MHz
+HSDIV1 output: 320MHz
+HSDIV2 output: 192MHz
+HSDIV3 output: 192MHz
+HSDIV4 output: N/A
+HSDIV5 output: 192MHz
+HSDIV6 output: 19.2MHz
+HSDIV7 output: 24MHz
+HSDIV8 output: 20MHz
+MODSS configuration:
+- Spread: 3.125%
+- Modulator Divider: %-by-1
+- Downspread or centerspread: downspread
+
+ */
+#define MAIN_PLL1_FBDIV 96
+#define MAIN_PLL1_FRACDIV -1
+#define MAIN_PLL1_PREDIV 1
+#define MAIN_PLL1_POSTDIV1 2
+#define MAIN_PLL1_POSTDIV2 1
+#define MAIN_PLL1_HSDIV0_DIV_VAL 9 //10
+#define MAIN_PLL1_HSDIV1_DIV_VAL 5 //6
+#define MAIN_PLL1_HSDIV2_DIV_VAL 9 //10
+#define MAIN_PLL1_HSDIV3_DIV_VAL 9 //10
+#define MAIN_PLL1_HSDIV4_DIV_VAL -1 //No HSDIV
+#define MAIN_PLL1_HSDIV5_DIV_VAL 4 //5
+#define MAIN_PLL1_HSDIV6_DIV_VAL 49 //50
+#define MAIN_PLL1_HSDIV7_DIV_VAL 39 //40
+#define MAIN_PLL1_HSDIV8_DIV_VAL 47 //48
+#define MAIN_PLL1_SSMOD_SPREAD 0x1F
+#define MAIN_PLL1_SSMOD_MODDIV -1
+#define MAIN_PLL1_SSMOD_DOWNSPREAD 1
+
+
+//PLL2: Peripheral 1 PLL
+/* Frequencies:
+
+PLL input: 20MHz
+VCO output: 1800MHz
+POSTDIV output: 900MHz
+HSDIV0 output: 360MHz
+HSDIV1 output: 600MHz
+HSDIV2 output: 200MHz
+HSDIV3 output: 300MHz
+HSDIV4 output: 100MHz
+HSDIV5 output: 450MHz
+HSDIV6 output: 225MHz
+HSDIV7 output: 120MHz
+HSDIV8 output: N/A
+MODSS configuration:
+- Spread: 3.125%
+- Modulator Divider: %-by-1
+- Downspread or centerspread: downspread
+
+ */
+#define MAIN_PLL2_FBDIV 90
+#define MAIN_PLL2_FRACDIV -1
+#define MAIN_PLL2_PREDIV 1
+#define MAIN_PLL2_POSTDIV1 2
+#define MAIN_PLL2_POSTDIV2 1
+#define MAIN_PLL2_HSDIV0_DIV_VAL 4 //5
+#define MAIN_PLL2_HSDIV1_DIV_VAL 2 //3
+#define MAIN_PLL2_HSDIV2_DIV_VAL 8 //9
+#define MAIN_PLL2_HSDIV3_DIV_VAL 5 //6
+#define MAIN_PLL2_HSDIV4_DIV_VAL 17 //18
+#define MAIN_PLL2_HSDIV5_DIV_VAL 1 //2
+#define MAIN_PLL2_HSDIV6_DIV_VAL 3 //4
+#define MAIN_PLL2_HSDIV7_DIV_VAL 14 //15
+#define MAIN_PLL2_HSDIV8_DIV_VAL -1 //No HSDIV
+#define MAIN_PLL2_SSMOD_SPREAD 0x1F
+#define MAIN_PLL2_SSMOD_MODDIV -1
+#define MAIN_PLL2_SSMOD_DOWNSPREAD 1
+
+
+//PLL3: CPSW9x PLL
+/* Frequencies:
+
+PLL input: 20MHz
+VCO output: 2000MHz
+POSTDIV output: 2000MHz
+HSDIV0 output: 250MHz
+HSDIV1 output: 250MHz
+HSDIV2 output: 200MHz
+HSDIV3 output: 250MHz
+HSDIV4 output: 153MHz (approx 156.25MHz)
+HSDIV5 output: N/A
+HSDIV6 output: N/A
+HSDIV7 output: N/A
+HSDIV8 output: N/A
+MODSS configuration:
+- Spread: 3.125%
+- Modulator Divider: %-by-1
+- Downspread or centerspread: downspread
+
+ */
+#define MAIN_PLL3_FBDIV 100
+#define MAIN_PLL3_FRACDIV -1
+#define MAIN_PLL3_PREDIV 1
+#define MAIN_PLL3_POSTDIV1 1
+#define MAIN_PLL3_POSTDIV2 1
+#define MAIN_PLL3_HSDIV0_DIV_VAL 7 //8
+#define MAIN_PLL3_HSDIV1_DIV_VAL 7 //8
+#define MAIN_PLL3_HSDIV2_DIV_VAL 9 //10
+#define MAIN_PLL3_HSDIV3_DIV_VAL 7 //8
+#define MAIN_PLL3_HSDIV4_DIV_VAL 12 //13
+#define MAIN_PLL3_HSDIV5_DIV_VAL -1
+#define MAIN_PLL3_HSDIV6_DIV_VAL -1
+#define MAIN_PLL3_HSDIV7_DIV_VAL -1
+#define MAIN_PLL3_HSDIV8_DIV_VAL -1
+#define MAIN_PLL3_SSMOD_SPREAD 0x1F
+#define MAIN_PLL3_SSMOD_MODDIV -1
+#define MAIN_PLL3_SSMOD_DOWNSPREAD 1
+
+
+//PLL4: Audio PLL 0
+/* Frequencies:
+
+PLL input: 20MHz
+VCO output: 1180MHz
+POSTDIV output: 1180MHz
+HSDIV0 output: 196.67MHz
+HSDIV1 output: 295MHz
+HSDIV2 output: 196.67MHz
+HSDIV3 output: 12.292MHz
+HSDIV4 output: N/A
+HSDIV5 output: N/A
+HSDIV6 output: N/A
+HSDIV7 output: N/A
+HSDIV8 output: N/A
+MODSS configuration:
+- Spread: 3.125%
+- Modulator Divider: %-by-1
+- Downspread or centerspread: downspread
+
+ */
+#define MAIN_PLL4_FBDIV 59
+#define MAIN_PLL4_FRACDIV -1
+#define MAIN_PLL4_PREDIV 1
+#define MAIN_PLL4_POSTDIV1 1
+#define MAIN_PLL4_POSTDIV2 1
+#define MAIN_PLL4_HSDIV0_DIV_VAL 5 //6
+#define MAIN_PLL4_HSDIV1_DIV_VAL 3 //4
+#define MAIN_PLL4_HSDIV2_DIV_VAL 5 //6
+#define MAIN_PLL4_HSDIV3_DIV_VAL 95 //96
+#define MAIN_PLL4_HSDIV4_DIV_VAL -1
+#define MAIN_PLL4_HSDIV5_DIV_VAL -1
+#define MAIN_PLL4_HSDIV6_DIV_VAL -1
+#define MAIN_PLL4_HSDIV7_DIV_VAL -1
+#define MAIN_PLL4_HSDIV8_DIV_VAL -1
+#define MAIN_PLL4_SSMOD_SPREAD 0x1F
+#define MAIN_PLL4_SSMOD_MODDIV -1
+#define MAIN_PLL4_SSMOD_DOWNSPREAD 1
+
+
+//PLL5: Video PLL
+/* Frequencies:
+
+PLL input: 20MHz
+VCO output: 2750MHz
+POSTDIV output: 2750MHz
+HSDIV0 output: 687.5MHz (approx)
+HSDIV1 output: 550MHz (approx)
+HSDIV2 output: N/A
+HSDIV3 output: N/A
+HSDIV4 output: N/A
+HSDIV5 output: N/A
+HSDIV6 output: N/A
+HSDIV7 output: N/A
+HSDIV8 output: N/A
+MODSS configuration:
+- Spread: 3.125%
+- Modulator Divider: %-by-1
+- Downspread or centerspread: downspread
+
+ */
+#define MAIN_PLL5_FBDIV 137
+#define MAIN_PLL5_FRACDIV -1
+#define MAIN_PLL5_PREDIV 1
+#define MAIN_PLL5_POSTDIV1 1
+#define MAIN_PLL5_POSTDIV2 1
+#define MAIN_PLL5_HSDIV0_DIV_VAL 3 //4
+#define MAIN_PLL5_HSDIV1_DIV_VAL 4 //5
+#define MAIN_PLL5_HSDIV2_DIV_VAL -1
+#define MAIN_PLL5_HSDIV3_DIV_VAL -1
+#define MAIN_PLL5_HSDIV4_DIV_VAL -1
+#define MAIN_PLL5_HSDIV5_DIV_VAL -1
+#define MAIN_PLL5_HSDIV6_DIV_VAL -1
+#define MAIN_PLL5_HSDIV7_DIV_VAL -1
+#define MAIN_PLL5_HSDIV8_DIV_VAL -1
+#define MAIN_PLL5_SSMOD_SPREAD 0x1F
+#define MAIN_PLL5_SSMOD_MODDIV -1
+#define MAIN_PLL5_SSMOD_DOWNSPREAD 1
+
+
+//PLL6: GPU PLL
+/* Frequencies:
+
+PLL input: 20MHz
+VCO output: 3GHz
+POSTDIV output: 3GHz
+HSDIV0 output: 750MHz
+HSDIV1 output: N/A
+HSDIV2 output: N/A
+HSDIV3 output: N/A
+HSDIV4 output: N/A
+HSDIV5 output: N/A
+HSDIV6 output: N/A
+HSDIV7 output: N/A
+HSDIV8 output: N/A
+MODSS configuration:
+- Spread: 3.125%
+- Modulator Divider: %-by-1
+- Downspread or centerspread: downspread
+
+ */
+#define MAIN_PLL6_FBDIV 150
+#define MAIN_PLL6_FRACDIV -1
+#define MAIN_PLL6_PREDIV 1
+#define MAIN_PLL6_POSTDIV1 1
+#define MAIN_PLL6_POSTDIV2 1
+#define MAIN_PLL6_HSDIV0_DIV_VAL 3 //4
+#define MAIN_PLL6_HSDIV1_DIV_VAL -1
+#define MAIN_PLL6_HSDIV2_DIV_VAL -1
+#define MAIN_PLL6_HSDIV3_DIV_VAL -1
+#define MAIN_PLL6_HSDIV4_DIV_VAL -1
+#define MAIN_PLL6_HSDIV5_DIV_VAL -1
+#define MAIN_PLL6_HSDIV6_DIV_VAL -1
+#define MAIN_PLL6_HSDIV7_DIV_VAL -1
+#define MAIN_PLL6_HSDIV8_DIV_VAL -1
+#define MAIN_PLL6_SSMOD_SPREAD 0x1F
+#define MAIN_PLL6_SSMOD_MODDIV -1
+#define MAIN_PLL6_SSMOD_DOWNSPREAD 1
+
+
+//PLL7: C7x PLL
+/* Frequencies:
+
+PLL input: 20MHz
+VCO output: 3GHz
+POSTDIV output: 3GHz
+HSDIV0 output: 1GHz
+HSDIV1 output: N/A
+HSDIV2 output: N/A
+HSDIV3 output: N/A
+HSDIV4 output: N/A
+HSDIV5 output: N/A
+HSDIV6 output: N/A
+HSDIV7 output: N/A
+HSDIV8 output: N/A
+MODSS configuration:
+- Spread: 3.125%
+- Modulator Divider: %-by-1
+- Downspread or centerspread: downspread
+
+ */
+#define MAIN_PLL7_FBDIV 150
+#define MAIN_PLL7_FRACDIV -1
+#define MAIN_PLL7_PREDIV 1
+#define MAIN_PLL7_POSTDIV1 1
+#define MAIN_PLL7_POSTDIV2 1
+#define MAIN_PLL7_HSDIV0_DIV_VAL 2 //3
+#define MAIN_PLL7_HSDIV1_DIV_VAL -1
+#define MAIN_PLL7_HSDIV2_DIV_VAL -1
+#define MAIN_PLL7_HSDIV3_DIV_VAL -1
+#define MAIN_PLL7_HSDIV4_DIV_VAL -1
+#define MAIN_PLL7_HSDIV5_DIV_VAL -1
+#define MAIN_PLL7_HSDIV6_DIV_VAL -1
+#define MAIN_PLL7_HSDIV7_DIV_VAL -1
+#define MAIN_PLL7_HSDIV8_DIV_VAL -1
+#define MAIN_PLL7_SSMOD_SPREAD 0x1F
+#define MAIN_PLL7_SSMOD_MODDIV -1
+#define MAIN_PLL7_SSMOD_DOWNSPREAD 1
+
+
+//PLL8: ARM0 PLL
+/* Frequencies:
+
+PLL input: 20MHz
+VCO output: 2000MHz
+POSTDIV output: 2000MHz
+HSDIV0 output: 2GHz
+HSDIV1 output: N/A
+HSDIV2 output: N/A
+HSDIV3 output: N/A
+HSDIV4 output: N/A
+HSDIV5 output: N/A
+HSDIV6 output: N/A
+HSDIV7 output: N/A
+HSDIV8 output: N/A
+MODSS configuration:
+- Spread: 3.125%
+- Modulator Divider: %-by-1
+- Downspread or centerspread: downspread
+
+ */
+#define MAIN_PLL8_FBDIV 100
+#define MAIN_PLL8_FRACDIV -1
+#define MAIN_PLL8_PREDIV 1
+#define MAIN_PLL8_POSTDIV1 1
+#define MAIN_PLL8_POSTDIV2 1
+#define MAIN_PLL8_HSDIV0_DIV_VAL 0 //1
+#define MAIN_PLL8_HSDIV1_DIV_VAL -1
+#define MAIN_PLL8_HSDIV2_DIV_VAL -1
+#define MAIN_PLL8_HSDIV3_DIV_VAL -1
+#define MAIN_PLL8_HSDIV4_DIV_VAL -1
+#define MAIN_PLL8_HSDIV5_DIV_VAL -1
+#define MAIN_PLL8_HSDIV6_DIV_VAL -1
+#define MAIN_PLL8_HSDIV7_DIV_VAL -1
+#define MAIN_PLL8_HSDIV8_DIV_VAL -1
+#define MAIN_PLL8_SSMOD_SPREAD 0x1F
+#define MAIN_PLL8_SSMOD_MODDIV -1
+#define MAIN_PLL8_SSMOD_DOWNSPREAD 1
+
+
+//PLL9: Not Present **************************************
+//PLL10: Not Present *************************************
+//PLL11: Not Present *************************************
+
+
+//PLL12: DDR FracF PLL
+/* Frequencies:
+
+PLL input: 20MHz
+VCO output: 2130MHz
+POSTDIV output: 2130MHz
+HSDIV0 output: 1065MHz
+HSDIV1 output: N/A
+HSDIV2 output: N/A
+HSDIV3 output: N/A
+HSDIV4 output: N/A
+HSDIV5 output: N/A
+HSDIV6 output: N/A
+HSDIV7 output: N/A
+HSDIV8 output: N/A
+MODSS configuration:
+- Spread: 3.125%
+- Modulator Divider: %-by-1
+- Downspread or centerspread: downspread
+
+ */
+#define MAIN_PLL12_FBDIV 111
+#define MAIN_PLL12_FRACDIV 1572864
+#define MAIN_PLL12_PREDIV 1
+#define MAIN_PLL12_POSTDIV1 1
+#define MAIN_PLL12_POSTDIV2 1
+#define MAIN_PLL12_HSDIV0_DIV_VAL 1 //2
+#define MAIN_PLL12_HSDIV1_DIV_VAL -1
+#define MAIN_PLL12_HSDIV2_DIV_VAL -1
+#define MAIN_PLL12_HSDIV3_DIV_VAL -1
+#define MAIN_PLL12_HSDIV4_DIV_VAL -1
+#define MAIN_PLL12_HSDIV5_DIV_VAL -1
+#define MAIN_PLL12_HSDIV6_DIV_VAL -1
+#define MAIN_PLL12_HSDIV7_DIV_VAL -1
+#define MAIN_PLL12_HSDIV8_DIV_VAL -1
+#define MAIN_PLL12_SSMOD_SPREAD -1
+#define MAIN_PLL12_SSMOD_MODDIV -1
+#define MAIN_PLL12_SSMOD_DOWNSPREAD -1
+
+#define MAIN_PLL12_FBDIV_DDR_1866 93
+#define MAIN_PLL12_FRACDIV_DDR_1866 10066329
+
+#define MAIN_PLL12_FBDIV_DDR_1600 80
+#define MAIN_PLL12_FRACDIV_DDR_1600 0
+
+#define MAIN_PLL12_FBDIV_DDR_3200 160
+#define MAIN_PLL12_FRACDIV_DDR_3200 0
+
+
+//PLL13: C66 PLL
+/* Frequencies:
+
+PLL input: 20MHz
+VCO output: 2.7GHz
+POSTDIV output: 2.7GHz
+HSDIV0 output: 1.35GHz
+HSDIV1 output: 1.35GHz
+HSDIV2 output: 67.5MHz (not connected to anything)
+HSDIV3 output: N/A
+HSDIV4 output: N/A
+HSDIV5 output: N/A
+HSDIV6 output: N/A
+HSDIV7 output: N/A
+HSDIV8 output: N/A
+MODSS configuration:
+- Spread: 3.125%
+- Modulator Divider: %-by-1
+- Downspread or centerspread: downspread
+
+ */
+#define MAIN_PLL13_FBDIV 135
+#define MAIN_PLL13_FRACDIV -1
+#define MAIN_PLL13_PREDIV 1
+#define MAIN_PLL13_POSTDIV1 1
+#define MAIN_PLL13_POSTDIV2 1
+#define MAIN_PLL13_HSDIV0_DIV_VAL 1 //2
+#define MAIN_PLL13_HSDIV1_DIV_VAL 1 //2
+#define MAIN_PLL13_HSDIV2_DIV_VAL 39 //40
+#define MAIN_PLL13_HSDIV3_DIV_VAL -1
+#define MAIN_PLL13_HSDIV4_DIV_VAL -1
+#define MAIN_PLL13_HSDIV5_DIV_VAL -1
+#define MAIN_PLL13_HSDIV6_DIV_VAL -1
+#define MAIN_PLL13_HSDIV7_DIV_VAL -1
+#define MAIN_PLL13_HSDIV8_DIV_VAL -1
+#define MAIN_PLL13_SSMOD_SPREAD 0x1F
+#define MAIN_PLL13_SSMOD_MODDIV -1
+#define MAIN_PLL13_SSMOD_DOWNSPREAD 1
+
+
+//PLL14: Main Pulsar PLL
+/* Frequencies:
+
+PLL input: 20MHz
+VCO output: 3GHz
+POSTDIV output: 3GHz
+HSDIV0 output: 1GHz
+HSDIV1 output: 1GHz
+HSDIV2 output: N/A
+HSDIV3 output: N/A
+HSDIV4 output: N/A
+HSDIV5 output: N/A
+HSDIV6 output: N/A
+HSDIV7 output: N/A
+HSDIV8 output: N/A
+MODSS configuration:
+- Spread: 3.125%
+- Modulator Divider: %-by-1
+- Downspread or centerspread: downspread
+
+ */
+#define MAIN_PLL14_FBDIV 150
+#define MAIN_PLL14_FRACDIV -1
+#define MAIN_PLL14_PREDIV 1
+#define MAIN_PLL14_POSTDIV1 1
+#define MAIN_PLL14_POSTDIV2 1
+#define MAIN_PLL14_HSDIV0_DIV_VAL 2 //3
+#define MAIN_PLL14_HSDIV1_DIV_VAL 2 //3
+#define MAIN_PLL14_HSDIV2_DIV_VAL -1
+#define MAIN_PLL14_HSDIV3_DIV_VAL -1
+#define MAIN_PLL14_HSDIV4_DIV_VAL -1
+#define MAIN_PLL14_HSDIV5_DIV_VAL -1
+#define MAIN_PLL14_HSDIV6_DIV_VAL -1
+#define MAIN_PLL14_HSDIV7_DIV_VAL -1
+#define MAIN_PLL14_HSDIV8_DIV_VAL -1
+#define MAIN_PLL14_SSMOD_SPREAD 0x1F
+#define MAIN_PLL14_SSMOD_MODDIV -1
+#define MAIN_PLL14_SSMOD_DOWNSPREAD 1
+
+
+//PLL15: Audio PLL 1
+/* Frequencies:
+
+PLL input: 20MHz
+VCO output: 1180MHz
+POSTDIV output: 1180MHz
+HSDIV0 output: 196.7MHz
+HSDIV1 output: 295MHz
+HSDIV2 output: 196.7MHz
+HSDIV3 output: 12.29MHz
+HSDIV4 output: N/A
+HSDIV5 output: N/A
+HSDIV6 output: N/A
+HSDIV7 output: N/A
+HSDIV8 output: N/A
+MODSS configuration:
+- Spread: 3.125%
+- Modulator Divider: %-by-1
+- Downspread or centerspread: downspread
+
+ */
+#define MAIN_PLL15_FBDIV 59
+#define MAIN_PLL15_FRACDIV -1
+#define MAIN_PLL15_PREDIV 1
+#define MAIN_PLL15_POSTDIV1 1
+#define MAIN_PLL15_POSTDIV2 1
+#define MAIN_PLL15_HSDIV0_DIV_VAL 5 //6
+#define MAIN_PLL15_HSDIV1_DIV_VAL 3 //4
+#define MAIN_PLL15_HSDIV2_DIV_VAL 5 //6
+#define MAIN_PLL15_HSDIV3_DIV_VAL 95 //96
+#define MAIN_PLL15_HSDIV4_DIV_VAL -1
+#define MAIN_PLL15_HSDIV5_DIV_VAL -1
+#define MAIN_PLL15_HSDIV6_DIV_VAL -1
+#define MAIN_PLL15_HSDIV7_DIV_VAL -1
+#define MAIN_PLL15_HSDIV8_DIV_VAL -1
+#define MAIN_PLL15_SSMOD_SPREAD 0x1F
+#define MAIN_PLL15_SSMOD_MODDIV -1
+#define MAIN_PLL15_SSMOD_DOWNSPREAD 1
+
+
+//PLL16: DSS PLL0
+/* Frequencies:
+
+PLL input: 20MHz
+VCO output: 3GHz
+POSTDIV output: 3GHz
+HSDIV0 output: 600MHz
+HSDIV1 output: 600MHz
+HSDIV2 output: N/A
+HSDIV3 output: N/A
+HSDIV4 output: N/A
+HSDIV5 output: N/A
+HSDIV6 output: N/A
+HSDIV7 output: N/A
+HSDIV8 output: N/A
+MODSS configuration:
+- Spread: 3.125%
+- Modulator Divider: %-by-1
+- Downspread or centerspread: downspread
+
+ */
+#define MAIN_PLL16_FBDIV 150
+#define MAIN_PLL16_FRACDIV 0
+#define MAIN_PLL16_PREDIV 1
+#define MAIN_PLL16_POSTDIV1 1
+#define MAIN_PLL16_POSTDIV2 1
+#define MAIN_PLL16_HSDIV0_DIV_VAL 4 //5
+#define MAIN_PLL16_HSDIV1_DIV_VAL 4 //5
+#define MAIN_PLL16_HSDIV2_DIV_VAL -1
+#define MAIN_PLL16_HSDIV3_DIV_VAL -1
+#define MAIN_PLL16_HSDIV4_DIV_VAL -1
+#define MAIN_PLL16_HSDIV5_DIV_VAL -1
+#define MAIN_PLL16_HSDIV6_DIV_VAL -1
+#define MAIN_PLL16_HSDIV7_DIV_VAL -1
+#define MAIN_PLL16_HSDIV8_DIV_VAL -1
+#define MAIN_PLL16_SSMOD_SPREAD 0x1F
+#define MAIN_PLL16_SSMOD_MODDIV -1
+#define MAIN_PLL16_SSMOD_DOWNSPREAD 1
+
+#define MAIN_PLL16_FBDIV_DSS_2970 148
+#define MAIN_PLL16_FRACDIV_DSS_2970 8388608
+
+#define MAIN_PLL16_FBDIV_DSS_2345 117
+#define MAIN_PLL16_FRACDIV_DSS_2345 4949279
+
+#define MAIN_PLL16_FBDIV_DSS_2898 144
+#define MAIN_PLL16_FRACDIV_DSS_2898 15099494
+
+#define MAIN_PLL16_FBDIV_DSS_2613 130
+#define MAIN_PLL16_FRACDIV_DSS_2613 10963911
+
+#define MAIN_PLL16_FBDIV_DSS_2133 106
+#define MAIN_PLL16_FRACDIV_DSS_2133 10905190
+
+
+//PLL17: DSS PLL1
+/* Frequencies:
+
+PLL input: 20MHz
+VCO output: 3GHz
+POSTDIV output: 3GHz
+HSDIV0 output: 600MHz
+HSDIV1 output: 600MHz
+HSDIV2 output: N/A
+HSDIV3 output: N/A
+HSDIV4 output: N/A
+HSDIV5 output: N/A
+HSDIV6 output: N/A
+HSDIV7 output: N/A
+HSDIV8 output: N/A
+MODSS configuration:
+- Spread: 3.125%
+- Modulator Divider: %-by-1
+- Downspread or centerspread: downspread
+
+ */
+#define MAIN_PLL17_FBDIV 150
+#define MAIN_PLL17_FRACDIV 0
+#define MAIN_PLL17_PREDIV 1
+#define MAIN_PLL17_POSTDIV1 1
+#define MAIN_PLL17_POSTDIV2 1
+#define MAIN_PLL17_HSDIV0_DIV_VAL 4 //5
+#define MAIN_PLL17_HSDIV1_DIV_VAL 4 //5
+#define MAIN_PLL17_HSDIV2_DIV_VAL -1
+#define MAIN_PLL17_HSDIV3_DIV_VAL -1
+#define MAIN_PLL17_HSDIV4_DIV_VAL -1
+#define MAIN_PLL17_HSDIV5_DIV_VAL -1
+#define MAIN_PLL17_HSDIV6_DIV_VAL -1
+#define MAIN_PLL17_HSDIV7_DIV_VAL -1
+#define MAIN_PLL17_HSDIV8_DIV_VAL -1
+#define MAIN_PLL17_SSMOD_SPREAD 0x1F
+#define MAIN_PLL17_SSMOD_MODDIV -1
+#define MAIN_PLL17_SSMOD_DOWNSPREAD 1
+
+#define MAIN_PLL17_FBDIV_DSS_2970 148
+#define MAIN_PLL17_FRACDIV_DSS_2970 8388608
+
+#define MAIN_PLL17_FBDIV_DSS_2345 117
+#define MAIN_PLL17_FRACDIV_DSS_2345 4949279
+
+#define MAIN_PLL17_FBDIV_DSS_2898 144
+#define MAIN_PLL17_FRACDIV_DSS_2898 15099494
+
+#define MAIN_PLL17_FBDIV_DSS_2613 130
+#define MAIN_PLL17_FRACDIV_DSS_2613 10963911
+
+#define MAIN_PLL17_FBDIV_DSS_2133 106
+#define MAIN_PLL17_FRACDIV_DSS_2133 10905190
+
+
+//PLL18: DSS PLL2
+/* Frequencies:
+
+PLL input: 20MHz
+VCO output: 3GHz
+POSTDIV output: 3GHz
+HSDIV0 output: 600MHz
+HSDIV1 output: 600MHz
+HSDIV2 output: N/A
+HSDIV3 output: N/A
+HSDIV4 output: N/A
+HSDIV5 output: N/A
+HSDIV6 output: N/A
+HSDIV7 output: N/A
+HSDIV8 output: N/A
+MODSS configuration:
+- Spread: 3.125%
+- Modulator Divider: %-by-1
+- Downspread or centerspread: downspread
+
+ */
+#define MAIN_PLL18_FBDIV 150
+#define MAIN_PLL18_FRACDIV 0
+#define MAIN_PLL18_PREDIV 1
+#define MAIN_PLL18_POSTDIV1 1
+#define MAIN_PLL18_POSTDIV2 1
+#define MAIN_PLL18_HSDIV0_DIV_VAL 4 //5
+#define MAIN_PLL18_HSDIV1_DIV_VAL 4 //5
+#define MAIN_PLL18_HSDIV2_DIV_VAL -1
+#define MAIN_PLL18_HSDIV3_DIV_VAL -1
+#define MAIN_PLL18_HSDIV4_DIV_VAL -1
+#define MAIN_PLL18_HSDIV5_DIV_VAL -1
+#define MAIN_PLL18_HSDIV6_DIV_VAL -1
+#define MAIN_PLL18_HSDIV7_DIV_VAL -1
+#define MAIN_PLL18_HSDIV8_DIV_VAL -1
+#define MAIN_PLL18_SSMOD_SPREAD 0x1F
+#define MAIN_PLL18_SSMOD_MODDIV -1
+#define MAIN_PLL18_SSMOD_DOWNSPREAD 1
+
+#define MAIN_PLL18_FBDIV_DSS_2970 148
+#define MAIN_PLL18_FRACDIV_DSS_2970 8388608
+
+#define MAIN_PLL18_FBDIV_DSS_2345 117
+#define MAIN_PLL18_FRACDIV_DSS_2345 4949279
+
+#define MAIN_PLL18_FBDIV_DSS_2898 144
+#define MAIN_PLL18_FRACDIV_DSS_2898 15099494
+
+
+//PLL19: DSS PLL3
+/* Frequencies:
+
+PLL input: 20MHz
+VCO output: 3GHz
+POSTDIV output: 3GHz
+HSDIV0 output: 600MHz
+HSDIV1 output: 600MHz
+HSDIV2 output: N/A
+HSDIV3 output: N/A
+HSDIV4 output: N/A
+HSDIV5 output: N/A
+HSDIV6 output: N/A
+HSDIV7 output: N/A
+HSDIV8 output: N/A
+MODSS configuration:
+- Spread: 3.125%
+- Modulator Divider: %-by-1
+- Downspread or centerspread: downspread
+
+ */
+#define MAIN_PLL19_FBDIV 150
+#define MAIN_PLL19_FRACDIV 0
+#define MAIN_PLL19_PREDIV 1
+#define MAIN_PLL19_POSTDIV1 1
+#define MAIN_PLL19_POSTDIV2 1
+#define MAIN_PLL19_HSDIV0_DIV_VAL 4 //5
+#define MAIN_PLL19_HSDIV1_DIV_VAL 4 //5
+#define MAIN_PLL19_HSDIV2_DIV_VAL -1
+#define MAIN_PLL19_HSDIV3_DIV_VAL -1
+#define MAIN_PLL19_HSDIV4_DIV_VAL -1
+#define MAIN_PLL19_HSDIV5_DIV_VAL -1
+#define MAIN_PLL19_HSDIV6_DIV_VAL -1
+#define MAIN_PLL19_HSDIV7_DIV_VAL -1
+#define MAIN_PLL19_HSDIV8_DIV_VAL -1
+#define MAIN_PLL19_SSMOD_SPREAD 0x1F
+#define MAIN_PLL19_SSMOD_MODDIV -1
+#define MAIN_PLL19_SSMOD_DOWNSPREAD 1
+
+#define MAIN_PLL19_FBDIV_DSS_2970 148
+#define MAIN_PLL19_FRACDIV_DSS_2970 8388608
+
+
+
+//PLL20: Not Present *************************************
+//PLL21: Not Present *************************************
+//PLL22: Not Present *************************************
+
+
+//PLL23: DSS PLL7
+/* Frequencies:
+
+PLL input: 20MHz
+VCO output: 3GHz
+POSTDIV output: 3GHz
+HSDIV0 output: 600MHz
+HSDIV1 output: 600MHz
+HSDIV2 output: N/A
+HSDIV3 output: N/A
+HSDIV4 output: N/A
+HSDIV5 output: N/A
+HSDIV6 output: N/A
+HSDIV7 output: N/A
+HSDIV8 output: N/A
+MODSS configuration:
+- Spread: 3.125%
+- Modulator Divider: %-by-1
+- Downspread or centerspread: downspread:
+
+ */
+#define MAIN_PLL23_FBDIV 150
+#define MAIN_PLL23_FRACDIV 0
+#define MAIN_PLL23_PREDIV 1
+#define MAIN_PLL23_POSTDIV1 1
+#define MAIN_PLL23_POSTDIV2 1
+#define MAIN_PLL23_HSDIV0_DIV_VAL 4 //5
+#define MAIN_PLL23_HSDIV1_DIV_VAL 4 //5
+#define MAIN_PLL23_HSDIV2_DIV_VAL -1
+#define MAIN_PLL23_HSDIV3_DIV_VAL -1
+#define MAIN_PLL23_HSDIV4_DIV_VAL -1
+#define MAIN_PLL23_HSDIV5_DIV_VAL -1
+#define MAIN_PLL23_HSDIV6_DIV_VAL -1
+#define MAIN_PLL23_HSDIV7_DIV_VAL -1
+#define MAIN_PLL23_HSDIV8_DIV_VAL -1
+#define MAIN_PLL23_SSMOD_SPREAD 0x1F
+#define MAIN_PLL23_SSMOD_MODDIV -1
+#define MAIN_PLL23_SSMOD_DOWNSPREAD 1
+
+#define MAIN_PLL23_FBDIV_DSS_2970 148
+#define MAIN_PLL23_FRACDIV_DSS_2970 8388608
+
+
+//PLL25: Image Processing PLL
+/* Frequencies:
+
+PLL input: 20MHz
+VCO output: 2880MHz
+POSTDIV output: 2880MHz
+HSDIV0 output: 480MHz
+HSDIV1 output: 720MHz
+HSDIV2 output: N/A
+HSDIV3 output: N/A
+HSDIV4 output: N/A
+HSDIV5 output: N/A
+HSDIV6 output: N/A
+HSDIV7 output: N/A
+HSDIV8 output: N/A
+MODSS configuration:
+- Spread: 3.125%
+- Modulator Divider: %-by-1
+- Downspread or centerspread: downspread
+
+ */
+#define MAIN_PLL25_FBDIV 144
+#define MAIN_PLL25_FRACDIV -1
+#define MAIN_PLL25_PREDIV 1
+#define MAIN_PLL25_POSTDIV1 1
+#define MAIN_PLL25_POSTDIV2 1
+#define MAIN_PLL25_HSDIV0_DIV_VAL 5 //6
+#define MAIN_PLL25_HSDIV1_DIV_VAL 3 //4
+#define MAIN_PLL25_HSDIV2_DIV_VAL -1
+#define MAIN_PLL25_HSDIV3_DIV_VAL -1
+#define MAIN_PLL25_HSDIV4_DIV_VAL -1
+#define MAIN_PLL25_HSDIV5_DIV_VAL -1
+#define MAIN_PLL25_HSDIV6_DIV_VAL -1
+#define MAIN_PLL25_HSDIV7_DIV_VAL -1
+#define MAIN_PLL25_HSDIV8_DIV_VAL -1
+#define MAIN_PLL25_SSMOD_SPREAD 0x1F
+#define MAIN_PLL25_SSMOD_MODDIV -1
+#define MAIN_PLL25_SSMOD_DOWNSPREAD 1
+
+#define MAIN_PLL25_FBDIV_DMPAC_520 130 // 2600MHz VCO output
+#define MAIN_PLL25_FRACDIV_DMPAC_520 -1 // 2600MHz VCO output
+#define MAIN_PLL25_HSDIV0_DMPAC_520_DIV_VAL 4 //5 (this is going to DMPAC)
+#define MAIN_PLL25_HSDIV1_DMPAC_520_DIV_VAL 3 //4 (this is going to VPAC)
+
+
+//MCU PLL0: MCU PLL
+/* Frequencies:
+
+PLL input: 20MHz
+VCO output: 2000MHz
+POSTDIV output: 2GHz
+HSDIV0 output: 1GHz
+HSDIV1 output: 60.6MHz
+HSDIV2 output: N/A
+HSDIV3 output: N/A
+HSDIV4 output: N/A
+HSDIV5 output: N/A
+HSDIV6 output: N/A
+HSDIV7 output: N/A
+HSDIV8 output: N/A
+MODSS configuration:
+- Spread: 3.125%
+- Modulator Divider: %-by-1
+- Downspread or centerspread: downspread
+
+ */
+#define MCU_PLL0_FBDIV 100
+#define MCU_PLL0_FRACDIV -1
+#define MCU_PLL0_PREDIV 1
+#define MCU_PLL0_POSTDIV1 1
+#define MCU_PLL0_POSTDIV2 1
+#define MCU_PLL0_HSDIV0_DIV_VAL 1 //2
+#define MCU_PLL0_HSDIV1_DIV_VAL 32 //33
+#define MCU_PLL0_HSDIV2_DIV_VAL -1
+#define MCU_PLL0_HSDIV3_DIV_VAL -1
+#define MCU_PLL0_HSDIV4_DIV_VAL -1
+#define MCU_PLL0_HSDIV5_DIV_VAL -1
+#define MCU_PLL0_HSDIV6_DIV_VAL -1
+#define MCU_PLL0_HSDIV7_DIV_VAL -1
+#define MCU_PLL0_HSDIV8_DIV_VAL -1
+#define MCU_PLL0_SSMOD_SPREAD 0x1F
+#define MCU_PLL0_SSMOD_MODDIV -1
+#define MCU_PLL0_SSMOD_DOWNSPREAD 1
+
+//MCU0 PLL PLL Controller Parameters
+#define MCU_CTRL_BPDIV 0 //AUXCLK=BPCLK=REFCLK for controller
+#define MCU_CTRL_OD1 0 //OBSCLK=REFCLK for controller
+#define MCU_CTRL_DIV1 1 //1000MHZ SYSCLK1 from MCU PLL CLKOUT
+
+
+//MCU PLL1: MCU Pulsar PLL
+/* Frequencies:
+
+PLL input: 20MHz
+VCO output: 2400MHz
+POSTDIV output: 2400MHz
+HSDIV0 output: 400MHz
+HSDIV1 output: 60MHz
+HSDIV2 output: 80MHz
+HSDIV3 output: 96MHz
+HSDIV4 output: 400MHz
+HSDIV5 output: N/A
+HSDIV6 output: N/A
+HSDIV7 output: N/A
+HSDIV8 output: N/A
+MODSS configuration:
+- Spread: 3.125%
+- Modulator Divider: %-by-1
+- Downspread or centerspread: downspread
+
+ */
+#define MCU_PLL1_FBDIV 120
+#define MCU_PLL1_FRACDIV -1
+#define MCU_PLL1_PREDIV 1
+#define MCU_PLL1_POSTDIV1 1
+#define MCU_PLL1_POSTDIV2 1
+#define MCU_PLL1_HSDIV0_DIV_VAL 5 //6
+#define MCU_PLL1_HSDIV1_DIV_VAL 39 //40
+#define MCU_PLL1_HSDIV2_DIV_VAL 29 //30
+#define MCU_PLL1_HSDIV3_DIV_VAL 24 //25
+#define MCU_PLL1_HSDIV4_DIV_VAL 5 //6
+#define MCU_PLL1_HSDIV5_DIV_VAL -1
+#define MCU_PLL1_HSDIV6_DIV_VAL -1
+#define MCU_PLL1_HSDIV7_DIV_VAL -1
+#define MCU_PLL1_HSDIV8_DIV_VAL -1
+#define MCU_PLL1_SSMOD_SPREAD 0x1F
+#define MCU_PLL1_SSMOD_MODDIV -1
+#define MCU_PLL1_SSMOD_DOWNSPREAD 1
+
+
+//MCU PLL2: MCU CPSW PLL
+/* Frequencies:
+
+PLL input: 20MHz
+VCO output: 2000MHz
+POSTDIV output: 2000MHz
+HSDIV0 output: 250MHz
+HSDIV1 output: 200MHz
+HSDIV2 output: 200MHz
+HSDIV3 output: 80MHz
+HSDIV4 output: 333.33MHz
+HSDIV5 output: N/A
+HSDIV6 output: N/A
+HSDIV7 output: N/A
+HSDIV8 output: N/A
+MODSS configuration:
+- Spread: 3.125%
+- Modulator Divider: %-by-1
+- Downspread or centerspread: downspread
+
+ */
+#define MCU_PLL2_FBDIV 100
+#define MCU_PLL2_FRACDIV -1
+#define MCU_PLL2_PREDIV 1
+#define MCU_PLL2_POSTDIV1 1
+#define MCU_PLL2_POSTDIV2 1
+#define MCU_PLL2_HSDIV0_DIV_VAL 7 //8
+#define MCU_PLL2_HSDIV1_DIV_VAL 9 //10
+#define MCU_PLL2_HSDIV2_DIV_VAL 9 //10
+#define MCU_PLL2_HSDIV3_DIV_VAL 24 //25
+#define MCU_PLL2_HSDIV4_DIV_VAL 11 //5 //6
+#define MCU_PLL2_HSDIV5_DIV_VAL -1
+#define MCU_PLL2_HSDIV6_DIV_VAL -1
+#define MCU_PLL2_HSDIV7_DIV_VAL -1
+#define MCU_PLL2_HSDIV8_DIV_VAL -1
+#define MCU_PLL2_SSMOD_SPREAD 0x1F
+#define MCU_PLL2_SSMOD_MODDIV -1
+#define MCU_PLL2_SSMOD_DOWNSPREAD 1
+
+typedef struct Board_PllClkCfg_s
+{
+ uint32_t tisciDevID;
+ uint32_t tisciClkID;
+ uint64_t clkRate;
+
+} Board_PllClkCfg_t;
+
+/* END OF FILE */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* BOARD_PLL_H */
diff --git a/packages/ti/board/src/j721s2_evm/include/board_utils.h b/packages/ti/board/src/j721s2_evm/include/board_utils.h
--- /dev/null
@@ -0,0 +1,358 @@
+/******************************************************************************
+ * Copyright (c) 2021 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *****************************************************************************/
+
+/**
+ * \file board_utils.h
+ *
+ * \brief Board utility functions header file
+ *
+ */
+
+#ifndef _BOARD_UTILS_H_
+#define _BOARD_UTILS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*****************************************************************************
+ * Include Files *
+ *****************************************************************************/
+#include <ti/csl/csl_types.h>
+#include <ti/csl/cslr_device.h>
+
+#include <ti/board/board.h>
+#include <ti/csl/tistdtypes.h>
+#include <stdio.h>
+#include <stdbool.h>
+
+#define BOARD_PSC_DEVICE_MODE_EXCLUSIVE (0)
+#define BOARD_PSC_DEVICE_MODE_NONEXCLUSIVE (1U)
+
+#define BOARD_MAIN_CLOCK_GROUP_ALL (0U)
+#define BOARD_MAIN_CLOCK_GROUP1 (1U)
+#define BOARD_MAIN_CLOCK_GROUP2 (2U)
+
+#define BOARD_MCU_CLOCK_GROUP_ALL (0U)
+#define BOARD_MCU_CLOCK_GROUP1 (1U)
+#define BOARD_MCU_CLOCK_GROUP2 (2U)
+
+
+#define BOARD_MAC_ADDR_BYTES (6U)
+
+#define BOARD_ENET_NONE (0)
+#define BOARD_ENET_QSGMII (1U)
+#define BOARD_ENET_SGMII (2U)
+#define BOARD_ENET_UNKOWN (-1)
+
+/* GPIO port and pin numbers for SDIO 1V8 enable */
+#define BOARD_SDIO_1V8_EN_PIN_NUM (8U) //GPIO0_8 - SEL_SDIO_3V3_1V8n
+
+
+/**
+ * \brief Structure to configure the board I2C parameters
+ */
+typedef struct Board_I2cInitCfg_s
+{
+ /** I2C controller instance */
+ uint32_t i2cInst;
+ /** SoC domain of the I2C controller */
+ uint32_t socDomain;
+ /** I2C controller interrupt enable/disable flag */
+ bool enableIntr;
+} Board_I2cInitCfg_t;
+
+/**
+ * \brief Structure to configure the board init parameters
+ */
+typedef struct Board_initParams_s
+{
+ /** UART controller instance */
+ uint32_t uartInst;
+ /** SoC domain of the UART controller */
+ uint32_t uartSocDomain;
+ /** Mode for PSC clock enable
+ BOARD_PSC_DEVICE_MODE_EXCLUSIVE - Exclusive access to the core requesting access
+ BOARD_PSC_DEVICE_MODE_NONEXCLUSIVE - Non-exclusive which allows other cores to get access */
+ uint8_t pscMode;
+ /** Group selection for MAIN domain clock enable
+ BOARD_MAIN_CLOCK_GROUP_ALL - Enable clock for all groups in main domain
+ BOARD_MAIN_CLOCK_GROUP1 - Enable clock for all group1 in main domain
+ BOARD_MAIN_CLOCK_GROUP2 - Enable clock for all group2 in main domain */
+ uint8_t mainClkGrp;
+ /** Group selection for MCU domain clock enable
+ BOARD_MCU_CLOCK_GROUP_ALL - Enable clock for all groups in mcu domain
+ BOARD_MCU_CLOCK_GROUP1 - Enable clock for all group1 in mcu domain
+ BOARD_MCU_CLOCK_GROUP2 - Enable clock for all group2 in mcu domain */
+ uint8_t mcuClkGrp;
+} Board_initParams_t;
+
+/**
+ * \brief Structure to configure the board I2C parameters
+ */
+typedef struct Board_DetectCfg_s
+{
+ /** I2C controller instance */
+ uint32_t i2cInst;
+ /** Board ID EEPROM slave address */
+ uint32_t slaveAddr;
+ /** Board ID EEPROM I2C soc domain */
+ uint8_t socDomain;
+ /** Board name */
+ char bName[20];
+} Board_DetectCfg_t;
+
+/**
+ * \brief Board ID read function
+ *
+ * \param info [IN] Board info structure
+ * \param boardID [IN] ID of the board to be detected
+ * \n BOARD_ID_GESI(0x0) - GESI Board
+ * \n BOARD_ID_FUSION2(0x1) - Fusion 2 Board
+ * \n BOARD_ID_SOM(0x2) - SoM Board
+ * \n BOARD_ID_CP(0x3) - CP Board
+ *
+ * \return BOARD_SOK in case of success or appropriate error code.
+ *
+ */
+Board_STATUS Board_getBoardData(Board_IDInfo_v2 *info, uint32_t boardID);
+
+/**
+ * \brief Board detect function
+ *
+ * Checks if the board with given 'boardID' is connected to the
+ * base board.
+ *
+ * \n Note: Board ID EEPROM should be programmed for this function
+ * to work properly.
+ *
+ * \param boardID [IN] ID of the board to be detected
+ * \n BOARD_ID_GESI(0x0) - GESI Board
+ * \n BOARD_ID_FUSION2(0x1) - Fusion 2 Board
+ * \n BOARD_ID_SOM(0x2) - SoM Board
+ * \n BOARD_ID_CP(0x3) - CP Board
+ *
+ * \return TRUE if the given board is detected else FALSE.
+ * SoM board will be always connected to the base board.
+ * For SoM boardID return value TRUE indicates dual PMIC
+ * SoM and FALSE indicates alternate PMIC SoM
+ *
+ */
+bool Board_detectBoard(uint32_t boardID);
+
+/**
+ * \brief Checks for Alpha board revision
+ *
+ * \param boardID [IN] ID of the board to be detected
+ * \n BOARD_ID_GESI(0x0) - GESI Board
+ * \n BOARD_ID_FUSION2(0x1) - Fusion 2 Board
+ * \n BOARD_ID_SOM(0x2) - SoM Board
+ * \n BOARD_ID_CP(0x3) - CP Board
+ *
+ * \return TRUE if board revision is E2, FALSE for all other cases
+ */
+bool Board_isAlpha(uint32_t boardID);
+
+/**
+ * \brief Function to detect ENET expansion application card type
+ *
+ * Not Supported on J721S2. Dummy function for backward compatibility
+ *
+ * \return
+ */
+int32_t Board_detectEnetCard(void);
+
+/**
+ * \brief Read MAC ID function
+ *
+ * This function reads the MAC addresses programmed to the board ID EEPROM
+ * on the boards with Ethernet ports. Exception is for MCU Ethernet port
+ * which is supposed to use MAC ID from SoC MMR registers.
+ *
+ * There can be multiple MAC IDs stored in the EEPROM based on the
+ * number of Ethernet ports on the board. Number of MAC IDs copied
+ * to 'macAddrBuf' can be read using 'macAddrCnt' parameters.
+ *
+ * Each MAC address will be 6 bytes long. MAC IDs will be copied to buffer
+ * based on 'macBufSize'. If the buffer size is long enough, all the MAC
+ * addresses from EEPROM will be copied to 'macAddrBuf' else fewer MAC
+ * IDs to fit within 'macBufSize'. MAC count for a given board can be
+ * read using Board_readMacAddrCount() function.
+ *
+ * \n Note: Board ID EEPROM should be programmed for this function
+ * to work properly.
+ *
+ * \param boardID [IN] ID of the board to be detected
+ * \n BOARD_ID_GESI(0x0) - GESI Board
+ * \n BOARD_ID_FUSION2(0x1) - Fusion 2 Board
+ * \n BOARD_ID_SOM(0x2) - SoM Board
+ * \n BOARD_ID_CP(0x3) - CP Board
+ * \param macAddrBuf[OUT] Buffer to write MAC IDs read from EEPROM
+ * \param macBufSize[IN] Size of the macAddrBuf
+ * \param macAddrCnt[OUT] Number of valid MAC addresses programmed to the EEPROM
+ * This an optional variable to read the MAC ID count
+ * filled to the 'macAddrBuf'.
+ * Pass a valid address to get MAC ID count.
+ *
+ * \return BOARD_SOK in case of success or appropriate error code.
+ *
+ */
+Board_STATUS Board_readMacAddr(uint32_t boardID,
+ uint8_t *macAddrBuf,
+ uint32_t macBufSize,
+ uint32_t *macAddrCnt);
+
+/**
+ * \brief Read MAC ID count
+ *
+ * This function reads the number of MAC addresses programmed to
+ * board ID EEPROM on the boards with Ethernet ports. Exception is
+ * for MCU Ethernet port which is supposed to use MAC ID from SoC
+ * MMR registers. Each MAC address programmed to EEPROM is 6 bytes long.
+ *
+ * \n Note: Board ID EEPROM should be programmed for this function
+ * to work properly.
+ *
+ * \param boardID [IN] ID of the board to be detected
+ * \n BOARD_ID_GESI(0x0) - GESI Board
+ * \n BOARD_ID_FUSION2(0x1) - Fusion 2 Board
+ * \n BOARD_ID_SOM(0x2) - SoM Board
+ * \n BOARD_ID_CP(0x3) - CP Board
+ * \param macAddrCnt[OUT] Number of valid MAC addresses programmed to the EEPROM
+ *
+ * \return BOARD_SOK in case of success or appropriate error code.
+ *
+ */
+Board_STATUS Board_readMacAddrCount(uint32_t boardID,
+ uint32_t *macAddrCnt);
+
+/**
+ * \brief Function to configure I2C configurations used by board
+ *
+ * This function is used to set the I2C controller instance and
+ * SoC domain used by the board module for IO expander and board
+ * ID info read.
+ *
+ * Usage:
+ * Call Board_setI2cInitConfig to set the I2C configurations
+ * Call IO expander Init or Board ID info read/write
+ *
+ * \return BOARD_SOK in case of success or appropriate error code.
+ *
+ */
+Board_STATUS Board_setI2cInitConfig(Board_I2cInitCfg_t *i2cCfg);
+
+/**
+ * \brief Function to get board init params
+ *
+ * This function shall be used to know the current board init
+ * parameters and update them if needed using the function Board_setInitParams.
+ *
+ * \param initParams [IN] Board init params structure
+ *
+ * \return BOARD_SOK in case of success or appropriate error code.
+ *
+ */
+Board_STATUS Board_getInitParams(Board_initParams_t *initParams);
+
+/**
+ * \brief Function to configure board init parameters
+ *
+ * Board init params includes the parameters used by Board_init
+ * function for different operations. Default init parameters
+ * used by Board_init can be updated using this function.
+ * All the default params can be overwritten by calling this function
+ * or some of can be changed by reading the existing init parameters
+ * using Board_getInitParams function.
+ *
+ * Usage:
+ * Call Board_getInitParams to get the default board init parameters
+ * Update the parameters as needed
+ * Call Board_setInitParams to update the default board init parameters
+ *
+ * \param initCfg [IN] Board Init config structure
+ *
+ * \return BOARD_SOK in case of success or appropriate error code.
+ *
+ */
+Board_STATUS Board_setInitParams(Board_initParams_t *initParams);
+
+/**
+ * \brief Function to get the SoC domain
+ *
+ * This function returns the domain of the SoC core on which
+ * it is executing.
+ *
+ * \return SoC domain of the core.
+ *
+ */
+uint32_t Board_getSocDomain(void);
+
+/**
+ * \brief Sets RAT configuration
+ *
+ * MAIN padconfig registers are not directly accessible for C66x core
+ * which requires RAT configuration for the access.
+ *
+ * \return None
+ */
+void Board_setRATCfg(void);
+
+/**
+ * \brief Restores RAT configuration
+ *
+ * \return None
+ */
+void Board_restoreRATCfg(void);
+
+/**
+ * \brief Function to generate delay in micro seconds
+ *
+ * This function takes the delay parameters in usecs but the generated
+ * delay will be in multiples of msecs due to the osal function which
+ * generates delay in msecs. Delay parameter passed will be converted to
+ * msecs and fractional value will be adjusted to nearest msecs value.
+ * Minimum delay generated by this function is 1 msec.
+ * Function parameter is kept in usecs to match with existing
+ * platforms which has delay function for usecs.
+ *
+ * \param usecs [IN] Specifies the time to delay in micro seconds.
+ *
+ */
+void BOARD_delay(uint32_t usecs);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _BOARD_UTILS_H_ */
diff --git a/packages/ti/board/src/j721s2_evm/include/pinmux.h b/packages/ti/board/src/j721s2_evm/include/pinmux.h
--- /dev/null
@@ -0,0 +1,102 @@
+/******************************************************************************
+ * Copyright (c) 2019 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *****************************************************************************/
+
+/**
+ * \file pinmux.h
+ *
+ * \brief Pinmux header file
+ *
+ * This file includes the pinmux configuration structures
+ *
+ */
+
+#ifndef PINMUX_H
+#define PINMUX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <ti/csl/tistdtypes.h>
+
+/* ========================================================================== */
+/* Structures and Enums */
+/* ========================================================================== */
+
+/**
+ * \brief Structure defining the pin configuration parameters.
+ *
+ */
+typedef struct pinmuxPerCfg
+{
+ int16_t pinOffset;
+ /**< Register offset for configuring the pin */
+ int32_t pinSettings;
+ /**< Value to be configured,
+ - Active mode configurations like mux mode, pull resistor, and buffer mode
+ */
+}pinmuxPerCfg_t;
+
+/**
+ * \brief Structure defining the pin configuration for different instances of
+ * a module.
+ */
+typedef struct pinmuxModuleCfg
+{
+ int16_t modInstNum;
+ /**< Instance number of the ip */
+ int16_t doPinConfig;
+ /**< Flag indicating whether this instance has to be configured. This flag
+ can be altered with separate API (PinMuxConfigEnable()).
+ Default configuration will be set to TRUE, but can be altered for
+ different scenarios (like power management). */
+ pinmuxPerCfg_t* instPins;
+ /**< Pointer to list of pins corresponding to this instance */
+}pinmuxModuleCfg_t;
+
+/**
+ * \brief Structure defining the pin configuration of a board.
+ */
+typedef struct pinmuxBoardCfg
+{
+ int32_t moduleId;
+ /**< Module ID */
+ pinmuxModuleCfg_t* modulePinCfg;
+ /**< Pin config info of a module: #pinmuxModuleCfg_t */
+}pinmuxBoardCfg_t;
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif
diff --git a/packages/ti/board/src/j721s2_evm/j721s2_evm_baseboard_pinmux.syscfg b/packages/ti/board/src/j721s2_evm/j721s2_evm_baseboard_pinmux.syscfg
--- /dev/null
@@ -0,0 +1,712 @@
+/**
+ * These arguments were used when this file was generated. They will be automatically applied on subsequent loads
+ * via the GUI or CLI. Run CLI with '--help' for additional information on how to override these arguments.
+ * @cliArgs --device "J721S2_beta" --package "ALZ" --part "Default"
+ * @versions {"data":"20211013","tool":"1.9.0+2015","templates":"20210927"}
+ */
+
+/**
+ * These are the peripherals and settings in this configuration
+ */
+const iAUXPHY1 = scripting.addPeripheral("AUXPHY");
+iAUXPHY1.$name = "MyAUXPHY0";
+iAUXPHY1.AUXN.$assign = "ball.AG11";
+iAUXPHY1.AUXP.$assign = "ball.AF11";
+const iCPSW2G1 = scripting.addPeripheral("CPSW2G");
+iCPSW2G1.$name = "MyCPSW2G0";
+iCPSW2G1.$assign = "CPSW2G_0";
+iCPSW2G1.CLKOUT.$used = false;
+iCPSW2G1.CRS_DV.$used = false;
+iCPSW2G1.MDC.$assign = "ball.T28";
+iCPSW2G1.MDIO.$assign = "ball.V28";
+iCPSW2G1.RD0.$assign = "ball.AA24";
+iCPSW2G1.RD1.$assign = "ball.AB25";
+iCPSW2G1.RD2.$assign = "ball.T23";
+iCPSW2G1.RD3.$assign = "ball.U24";
+iCPSW2G1.RMII_REF_CLK.$used = false;
+iCPSW2G1.RXC.$assign = "ball.AD26";
+iCPSW2G1.RXD0.$used = false;
+iCPSW2G1.RXD1.$used = false;
+iCPSW2G1.RX_CTL.$assign = "ball.AC25";
+iCPSW2G1.RX_ER.$used = false;
+iCPSW2G1.TD0.$assign = "ball.T25";
+iCPSW2G1.TD1.$assign = "ball.W24";
+iCPSW2G1.TD2.$assign = "ball.AA25";
+iCPSW2G1.TD3.$assign = "ball.V25";
+iCPSW2G1.TXC.$assign = "ball.U25";
+iCPSW2G1.TXD0.$used = false;
+iCPSW2G1.TXD1.$used = false;
+iCPSW2G1.TX_CTL.$assign = "ball.T24";
+iCPSW2G1.TX_EN.$used = false;
+const iCSI1 = scripting.addPeripheral("CSI");
+iCSI1.$name = "MyCSIRX0";
+iCSI1.RXCLKN.$assign = "ball.AH19";
+iCSI1.RXCLKP.$assign = "ball.AH20";
+iCSI1.RXN0.$assign = "ball.AG18";
+iCSI1.RXN1.$assign = "ball.AF19";
+iCSI1.RXN2.$assign = "ball.AE18";
+iCSI1.RXN3.$assign = "ball.AD19";
+iCSI1.RXP0.$assign = "ball.AG19";
+iCSI1.RXP1.$assign = "ball.AF20";
+iCSI1.RXP2.$assign = "ball.AE19";
+iCSI1.RXP3.$assign = "ball.AD20";
+iCSI1.RXRCALIB.$assign = "ball.AC18";
+iCSI1.TXCLKN.$used = false;
+iCSI1.TXCLKP.$used = false;
+iCSI1.TXN0.$used = false;
+iCSI1.TXN1.$used = false;
+iCSI1.TXN2.$used = false;
+iCSI1.TXN3.$used = false;
+iCSI1.TXP0.$used = false;
+iCSI1.TXP1.$used = false;
+iCSI1.TXP2.$used = false;
+iCSI1.TXP3.$used = false;
+const iCSI2 = scripting.addPeripheral("CSI");
+iCSI2.$name = "MyCSIRX1";
+iCSI2.RXCLKN.$assign = "ball.AH22";
+iCSI2.RXCLKP.$assign = "ball.AH23";
+iCSI2.RXN0.$assign = "ball.AG21";
+iCSI2.RXN1.$assign = "ball.AF22";
+iCSI2.RXN2.$assign = "ball.AE21";
+iCSI2.RXN3.$assign = "ball.AD22";
+iCSI2.RXP0.$assign = "ball.AG22";
+iCSI2.RXP1.$assign = "ball.AF23";
+iCSI2.RXP2.$assign = "ball.AE22";
+iCSI2.RXP3.$assign = "ball.AD23";
+iCSI2.RXRCALIB.$assign = "ball.AC21";
+iCSI2.TXCLKN.$used = false;
+iCSI2.TXCLKP.$used = false;
+iCSI2.TXN0.$used = false;
+iCSI2.TXN1.$used = false;
+iCSI2.TXN2.$used = false;
+iCSI2.TXN3.$used = false;
+iCSI2.TXP0.$used = false;
+iCSI2.TXP1.$used = false;
+iCSI2.TXP2.$used = false;
+iCSI2.TXP3.$used = false;
+const iDDRSS1 = scripting.addPeripheral("DDRSS");
+iDDRSS1.$name = "MyDDRSS0";
+iDDRSS1.$assign = "DDR_0";
+iDDRSS1.CA0.$assign = "ball.P3";
+iDDRSS1.CA1.$assign = "ball.P5";
+iDDRSS1.CA2.$assign = "ball.N5";
+iDDRSS1.CA3.$assign = "ball.P2";
+iDDRSS1.CA4.$assign = "ball.P4";
+iDDRSS1.CA5.$assign = "ball.R3";
+iDDRSS1.CAL0.$assign = "ball.R8";
+iDDRSS1.CKE0.$assign = "ball.R2";
+iDDRSS1.CKE1.$assign = "ball.R4";
+iDDRSS1.CKN.$assign = "ball.R1";
+iDDRSS1.CKP.$assign = "ball.P1";
+iDDRSS1.CSn0_0.$assign = "ball.V5";
+iDDRSS1.CSn0_1.$assign = "ball.W5";
+iDDRSS1.CSn1_0.$assign = "ball.T5";
+iDDRSS1.CSn1_1.$assign = "ball.U6";
+iDDRSS1.DM0.$assign = "ball.H5";
+iDDRSS1.DM1.$assign = "ball.M3";
+iDDRSS1.DM2.$assign = "ball.U4";
+iDDRSS1.DM3.$assign = "ball.AD1";
+iDDRSS1.DQ0.$assign = "ball.F3";
+iDDRSS1.DQ1.$assign = "ball.G4";
+iDDRSS1.DQ10.$assign = "ball.K3";
+iDDRSS1.DQ11.$assign = "ball.K1";
+iDDRSS1.DQ12.$assign = "ball.N4";
+iDDRSS1.DQ13.$assign = "ball.N2";
+iDDRSS1.DQ14.$assign = "ball.L4";
+iDDRSS1.DQ15.$assign = "ball.L2";
+iDDRSS1.DQ16.$assign = "ball.T1";
+iDDRSS1.DQ17.$assign = "ball.T3";
+iDDRSS1.DQ18.$assign = "ball.V3";
+iDDRSS1.DQ19.$assign = "ball.U2";
+iDDRSS1.DQ2.$assign = "ball.F5";
+iDDRSS1.DQ20.$assign = "ball.W2";
+iDDRSS1.DQ21.$assign = "ball.W4";
+iDDRSS1.DQ22.$assign = "ball.Y1";
+iDDRSS1.DQ23.$assign = "ball.Y3";
+iDDRSS1.DQ24.$assign = "ball.AB3";
+iDDRSS1.DQ25.$assign = "ball.AA2";
+iDDRSS1.DQ26.$assign = "ball.AA4";
+iDDRSS1.DQ27.$assign = "ball.Y5";
+iDDRSS1.DQ28.$assign = "ball.AC2";
+iDDRSS1.DQ29.$assign = "ball.AB5";
+iDDRSS1.DQ3.$assign = "ball.F1";
+iDDRSS1.DQ30.$assign = "ball.AD2";
+iDDRSS1.DQ31.$assign = "ball.AC4";
+iDDRSS1.DQ4.$assign = "ball.J4";
+iDDRSS1.DQ5.$assign = "ball.H3";
+iDDRSS1.DQ6.$assign = "ball.J2";
+iDDRSS1.DQ7.$assign = "ball.G2";
+iDDRSS1.DQ8.$assign = "ball.K5";
+iDDRSS1.DQ9.$assign = "ball.M5";
+iDDRSS1.DQS0N.$assign = "ball.H1";
+iDDRSS1.DQS0P.$assign = "ball.G1";
+iDDRSS1.DQS1N.$assign = "ball.M1";
+iDDRSS1.DQS1P.$assign = "ball.L1";
+iDDRSS1.DQS2N.$assign = "ball.U1";
+iDDRSS1.DQS2P.$assign = "ball.V1";
+iDDRSS1.DQS3N.$assign = "ball.AC1";
+iDDRSS1.DQS3P.$assign = "ball.AB1";
+iDDRSS1.RESETn.$assign = "ball.R5";
+iDDRSS1.RET.$assign = "ball.T8";
+const iDDRSS2 = scripting.addPeripheral("DDRSS");
+iDDRSS2.$name = "MyDDRSS1";
+iDDRSS2.$assign = "DDR_1";
+iDDRSS2.CA0.$assign = "ball.C10";
+iDDRSS2.CA1.$assign = "ball.E10";
+iDDRSS2.CA2.$assign = "ball.E9";
+iDDRSS2.CA3.$assign = "ball.B10";
+iDDRSS2.CA4.$assign = "ball.D10";
+iDDRSS2.CA5.$assign = "ball.C9";
+iDDRSS2.CAL0.$assign = "ball.E8";
+iDDRSS2.CKE0.$assign = "ball.B9";
+iDDRSS2.CKE1.$assign = "ball.D9";
+iDDRSS2.CKN.$assign = "ball.A9";
+iDDRSS2.CKP.$assign = "ball.A10";
+iDDRSS2.CSn0_0.$assign = "ball.F9";
+iDDRSS2.CSn0_1.$assign = "ball.F8";
+iDDRSS2.CSn1_0.$assign = "ball.F11";
+iDDRSS2.CSn1_1.$assign = "ball.F10";
+iDDRSS2.DM0.$assign = "ball.D16";
+iDDRSS2.DM1.$assign = "ball.E13";
+iDDRSS2.DM2.$assign = "ball.F7";
+iDDRSS2.DM3.$assign = "ball.B3";
+iDDRSS2.DQ0.$assign = "ball.B18";
+iDDRSS2.DQ1.$assign = "ball.E17";
+iDDRSS2.DQ10.$assign = "ball.C13";
+iDDRSS2.DQ11.$assign = "ball.C11";
+iDDRSS2.DQ12.$assign = "ball.E11";
+iDDRSS2.DQ13.$assign = "ball.A11";
+iDDRSS2.DQ14.$assign = "ball.B12";
+iDDRSS2.DQ15.$assign = "ball.D12";
+iDDRSS2.DQ16.$assign = "ball.B7";
+iDDRSS2.DQ17.$assign = "ball.D7";
+iDDRSS2.DQ18.$assign = "ball.C8";
+iDDRSS2.DQ19.$assign = "ball.A8";
+iDDRSS2.DQ2.$assign = "ball.D18";
+iDDRSS2.DQ20.$assign = "ball.C6";
+iDDRSS2.DQ21.$assign = "ball.E6";
+iDDRSS2.DQ22.$assign = "ball.B5";
+iDDRSS2.DQ23.$assign = "ball.D5";
+iDDRSS2.DQ24.$assign = "ball.B1";
+iDDRSS2.DQ25.$assign = "ball.A4";
+iDDRSS2.DQ26.$assign = "ball.C4";
+iDDRSS2.DQ27.$assign = "ball.E4";
+iDDRSS2.DQ28.$assign = "ball.D1";
+iDDRSS2.DQ29.$assign = "ball.D3";
+iDDRSS2.DQ3.$assign = "ball.A17";
+iDDRSS2.DQ30.$assign = "ball.C2";
+iDDRSS2.DQ31.$assign = "ball.E2";
+iDDRSS2.DQ4.$assign = "ball.E15";
+iDDRSS2.DQ5.$assign = "ball.B16";
+iDDRSS2.DQ6.$assign = "ball.C15";
+iDDRSS2.DQ7.$assign = "ball.C17";
+iDDRSS2.DQ8.$assign = "ball.B14";
+iDDRSS2.DQ9.$assign = "ball.D14";
+iDDRSS2.DQS0N.$assign = "ball.A15";
+iDDRSS2.DQS0P.$assign = "ball.A16";
+iDDRSS2.DQS1N.$assign = "ball.A12";
+iDDRSS2.DQS1P.$assign = "ball.A13";
+iDDRSS2.DQS2N.$assign = "ball.A7";
+iDDRSS2.DQS2P.$assign = "ball.A6";
+iDDRSS2.DQS3N.$assign = "ball.A2";
+iDDRSS2.DQS3P.$assign = "ball.A3";
+iDDRSS2.RESETn.$assign = "ball.F12";
+iDDRSS2.RET.$assign = "ball.J10";
+const iDP1 = scripting.addPeripheral("DP");
+iDP1.$name = "MyDP0";
+iDP1.HPD.$used = false;
+iDP1.TXN0.$assign = "ball.AG5";
+iDP1.TXN1.$assign = "ball.AD7";
+iDP1.TXN2.$used = false;
+iDP1.TXN3.$used = false;
+iDP1.TXP0.$assign = "ball.AG6";
+iDP1.TXP1.$assign = "ball.AD8";
+iDP1.TXP2.$used = false;
+iDP1.TXP3.$used = false;
+const iDSI1 = scripting.addPeripheral("DSI");
+iDSI1.$name = "MyDSI0";
+iDSI1.$assign = "DSI_TX_0";
+iDSI1.TXCLKN.$assign = "ball.AH13";
+iDSI1.TXCLKP.$assign = "ball.AH14";
+iDSI1.TXN0.$assign = "ball.AG12";
+iDSI1.TXN1.$assign = "ball.AF13";
+iDSI1.TXN2.$assign = "ball.AE12";
+iDSI1.TXN3.$assign = "ball.AD13";
+iDSI1.TXP0.$assign = "ball.AG13";
+iDSI1.TXP1.$assign = "ball.AF14";
+iDSI1.TXP2.$assign = "ball.AE13";
+iDSI1.TXP3.$assign = "ball.AD14";
+iDSI1.TXRCALIB.$assign = "ball.AC13";
+const iGPIO1 = scripting.addPeripheral("GPIO");
+iGPIO1["0"].$used = false;
+iGPIO1["1"].$used = false;
+iGPIO1["2"].$used = false;
+iGPIO1["3"].$assign = "ball.AE28";
+iGPIO1["4"].$used = false;
+iGPIO1["5"].$used = false;
+iGPIO1["6"].$used = false;
+iGPIO1["7"].$used = false;
+iGPIO1["8"].$assign = "ball.AA23";
+iGPIO1["9"].$used = false;
+iGPIO1["10"].$used = false;
+iGPIO1["11"].$assign = "ball.V23";
+iGPIO1["12"].$used = false;
+iGPIO1["13"].$assign = "ball.AD24";
+iGPIO1["14"].$used = false;
+iGPIO1["15"].$used = false;
+iGPIO1["16"].$used = false;
+iGPIO1["17"].$used = false;
+iGPIO1["18"].$assign = "ball.AB27";
+iGPIO1["19"].$used = false;
+iGPIO1["20"].$used = false;
+iGPIO1["21"].$used = false;
+iGPIO1["22"].$used = false;
+iGPIO1["23"].$assign = "ball.AA26";
+iGPIO1["24"].$used = false;
+iGPIO1["25"].$used = false;
+iGPIO1["26"].$assign = "ball.U28";
+iGPIO1["27"].$used = false;
+iGPIO1["28"].$assign = "ball.R27";
+iGPIO1["29"].$used = false;
+iGPIO1["30"].$used = false;
+iGPIO1["31"].$used = false;
+iGPIO1["32"].$used = false;
+iGPIO1["33"].$used = false;
+iGPIO1["34"].$used = false;
+iGPIO1["35"].$used = false;
+iGPIO1["36"].$used = false;
+iGPIO1["37"].$used = false;
+iGPIO1["38"].$used = false;
+iGPIO1["39"].$used = false;
+iGPIO1["40"].$used = false;
+iGPIO1["41"].$used = false;
+iGPIO1["42"].$used = false;
+iGPIO1["43"].$used = false;
+iGPIO1["44"].$used = false;
+iGPIO1["45"].$used = false;
+iGPIO1["46"].$used = false;
+iGPIO1["47"].$used = false;
+iGPIO1["48"].$used = false;
+iGPIO1["49"].$used = false;
+iGPIO1["50"].$used = false;
+iGPIO1["51"].$assign = "ball.AE27";
+iGPIO1["52"].$used = false;
+iGPIO1["53"].$used = false;
+iGPIO1["54"].$used = false;
+iGPIO1["55"].$used = false;
+iGPIO1["56"].$used = false;
+iGPIO1["57"].$used = false;
+iGPIO1["58"].$used = false;
+iGPIO1["59"].$used = false;
+iGPIO1["60"].$used = false;
+iGPIO1["61"].$used = false;
+iGPIO1["62"].$used = false;
+iGPIO1["63"].$used = false;
+iGPIO1["64"].$used = false;
+iGPIO1["65"].$used = false;
+iGPIO1.$name = "MyGPIO0";
+iGPIO1.$assign = "GPIO_0";
+const iI2C1 = scripting.addPeripheral("I2C");
+iI2C1.$name = "MyI2C0";
+iI2C1.$assign = "I2C_0";
+iI2C1.SCL.$assign = "ball.AH25";
+iI2C1.SDA.$assign = "ball.AE24";
+const iI2C2 = scripting.addPeripheral("I2C");
+iI2C2.$name = "MyI2C1";
+iI2C2.$assign = "I2C_1";
+iI2C2.SCL.$assign = "ball.AB26";
+iI2C2.SDA.$assign = "ball.AD28";
+const iI2C3 = scripting.addPeripheral("I2C");
+iI2C3.$name = "MyI2C3";
+iI2C3.$assign = "I2C_3";
+iI2C3.SCL.$assign = "ball.W28";
+iI2C3.SDA.$assign = "ball.AC27";
+const iI2C4 = scripting.addPeripheral("I2C");
+iI2C4.$name = "MyI2C4";
+iI2C4.$assign = "I2C_4";
+iI2C4.SCL.$assign = "ball.AD25";
+iI2C4.SDA.$assign = "ball.AF28";
+const iI2C5 = scripting.addPeripheral("I2C");
+iI2C5.$name = "MyI2C5";
+iI2C5.$assign = "I2C_5";
+iI2C5.SCL.$assign = "ball.Y24";
+iI2C5.SDA.$assign = "ball.W23";
+const iMCAN1 = scripting.addPeripheral("MCAN");
+iMCAN1.$name = "MyMCAN16";
+iMCAN1.$assign = "MCAN_16";
+iMCAN1.RX.$assign = "ball.AB24";
+iMCAN1.TX.$assign = "ball.Y28";
+const iMCU_ADC1 = scripting.addPeripheral("MCU_ADC");
+iMCU_ADC1.$name = "MyMCU_ADC0";
+iMCU_ADC1.$assign = "MCU_ADC_0";
+iMCU_ADC1.AIN0.$assign = "ball.L25";
+iMCU_ADC1.AIN1.$assign = "ball.K25";
+iMCU_ADC1.AIN2.$assign = "ball.M24";
+iMCU_ADC1.AIN3.$assign = "ball.L24";
+iMCU_ADC1.AIN4.$assign = "ball.L27";
+iMCU_ADC1.AIN5.$assign = "ball.K24";
+iMCU_ADC1.AIN6.$assign = "ball.M27";
+iMCU_ADC1.AIN7.$assign = "ball.M26";
+const iMCU_ADC2 = scripting.addPeripheral("MCU_ADC");
+iMCU_ADC2.$name = "MyMCU_ADC1";
+iMCU_ADC2.AIN0.$assign = "ball.P25";
+iMCU_ADC2.AIN1.$assign = "ball.R25";
+iMCU_ADC2.AIN2.$assign = "ball.P28";
+iMCU_ADC2.AIN3.$assign = "ball.P27";
+iMCU_ADC2.AIN4.$assign = "ball.N25";
+iMCU_ADC2.AIN5.$assign = "ball.P26";
+iMCU_ADC2.AIN6.$assign = "ball.N26";
+iMCU_ADC2.AIN7.$assign = "ball.N27";
+const iMCU_CPSW2G1 = scripting.addPeripheral("MCU_CPSW2G");
+iMCU_CPSW2G1.$name = "MyMCU_CPSW2G0";
+iMCU_CPSW2G1.$assign = "MCU_CPSW2G_0";
+iMCU_CPSW2G1.CRS_DV.$used = false;
+iMCU_CPSW2G1.RD0.$assign = "ball.B22";
+iMCU_CPSW2G1.RD1.$assign = "ball.B21";
+iMCU_CPSW2G1.RD2.$assign = "ball.C22";
+iMCU_CPSW2G1.RD3.$assign = "ball.D23";
+iMCU_CPSW2G1.REF_CLK.$used = false;
+iMCU_CPSW2G1.RXC.$assign = "ball.D22";
+iMCU_CPSW2G1.RXD0.$used = false;
+iMCU_CPSW2G1.RXD1.$used = false;
+iMCU_CPSW2G1.RX_CTL.$assign = "ball.E23";
+iMCU_CPSW2G1.RX_ER.$used = false;
+iMCU_CPSW2G1.TD0.$assign = "ball.F23";
+iMCU_CPSW2G1.TD1.$assign = "ball.G22";
+iMCU_CPSW2G1.TD2.$assign = "ball.E21";
+iMCU_CPSW2G1.TD3.$assign = "ball.E22";
+iMCU_CPSW2G1.TXC.$assign = "ball.F21";
+iMCU_CPSW2G1.TXD0.$used = false;
+iMCU_CPSW2G1.TXD1.$used = false;
+iMCU_CPSW2G1.TX_CTL.$assign = "ball.F22";
+iMCU_CPSW2G1.TX_EN.$used = false;
+const iMCU_I2C1 = scripting.addPeripheral("MCU_I2C");
+iMCU_I2C1.$name = "MyMCU_I2C0";
+iMCU_I2C1.$assign = "MCU_I2C_0";
+iMCU_I2C1.SCL.$assign = "ball.G24";
+iMCU_I2C1.SDA.$assign = "ball.J25";
+const iMCU_I3C1 = scripting.addPeripheral("MCU_I3C");
+iMCU_I3C1.$name = "MyMCU_I3C1";
+iMCU_I3C1.$assign = "MCU_I3C_0";
+iMCU_I3C1.SCL.$assign = "ball.F24";
+iMCU_I3C1.SDA.$assign = "ball.H26";
+iMCU_I3C1.SDAPULLEN.$assign = "ball.F25";
+const iMCU_MCAN1 = scripting.addPeripheral("MCU_MCAN");
+iMCU_MCAN1.$name = "MyMCU_MCAN0";
+iMCU_MCAN1.$assign = "MCU_MCAN_0";
+iMCU_MCAN1.RX.$assign = "ball.E28";
+iMCU_MCAN1.TX.$assign = "ball.E27";
+const iMCU_MCAN2 = scripting.addPeripheral("MCU_MCAN");
+iMCU_MCAN2.$name = "MyMCU_MCAN1";
+iMCU_MCAN2.$assign = "MCU_MCAN_1";
+iMCU_MCAN2.RX.$assign = "ball.F26";
+iMCU_MCAN2.TX.$assign = "ball.C23";
+const iMCU_MDIO1 = scripting.addPeripheral("MCU_MDIO");
+iMCU_MDIO1.$name = "MyMCU_MDIO0";
+iMCU_MDIO1.$assign = "MCU_MDIO_0";
+iMCU_MDIO1.MDC.$assign = "ball.A21";
+iMCU_MDIO1.MDIO.$assign = "ball.A22";
+const iMCU_OSPI1 = scripting.addPeripheral("MCU_OSPI");
+iMCU_OSPI1.$name = "MyMCU_OSPI0";
+iMCU_OSPI1.CLK.$assign = "ball.D19";
+iMCU_OSPI1.CSn0.$assign = "ball.F15";
+iMCU_OSPI1.CSn1.$used = false;
+iMCU_OSPI1.CSn2.$used = false;
+iMCU_OSPI1.CSn3.$used = false;
+iMCU_OSPI1.D0.$assign = "ball.C19";
+iMCU_OSPI1.D1.$assign = "ball.F16";
+iMCU_OSPI1.D2.$assign = "ball.G15";
+iMCU_OSPI1.D3.$assign = "ball.F18";
+iMCU_OSPI1.D4.$assign = "ball.E19";
+iMCU_OSPI1.D5.$assign = "ball.G19";
+iMCU_OSPI1.D6.$assign = "ball.F19";
+iMCU_OSPI1.D7.$assign = "ball.F20";
+iMCU_OSPI1.DQS.$assign = "ball.E18";
+iMCU_OSPI1.ECC_FAIL.$assign = "ball.F17";
+iMCU_OSPI1.LBCLKO.$used = false;
+iMCU_OSPI1.RESET_OUT0.$assign = "ball.F14";
+iMCU_OSPI1.RESET_OUT1.$used = false;
+const iMCU_OSPI2 = scripting.addPeripheral("MCU_OSPI");
+iMCU_OSPI2.$name = "MyMCU_OSPI1";
+iMCU_OSPI2.CLK.$assign = "ball.A19";
+iMCU_OSPI2.CSn0.$assign = "ball.D20";
+iMCU_OSPI2.CSn1.$used = false;
+iMCU_OSPI2.CSn2.$used = false;
+iMCU_OSPI2.CSn3.$used = false;
+iMCU_OSPI2.D0.$assign = "ball.D21";
+iMCU_OSPI2.D1.$assign = "ball.G20";
+iMCU_OSPI2.D2.$assign = "ball.C20";
+iMCU_OSPI2.D3.$assign = "ball.A20";
+iMCU_OSPI2.D4.$used = false;
+iMCU_OSPI2.D5.$used = false;
+iMCU_OSPI2.D6.$used = false;
+iMCU_OSPI2.D7.$used = false;
+iMCU_OSPI2.DQS.$assign = "ball.B19";
+iMCU_OSPI2.ECC_FAIL.$used = false;
+iMCU_OSPI2.LBCLKO.$assign = "ball.B20";
+iMCU_OSPI2.RESET_OUT0.$used = false;
+iMCU_OSPI2.RESET_OUT1.$used = false;
+const iMCU_UART1 = scripting.addPeripheral("MCU_UART");
+iMCU_UART1.$name = "MyMCU_UART0";
+iMCU_UART1.$assign = "MCU_USART_0";
+iMCU_UART1.CTSn.$assign = "ball.B24";
+iMCU_UART1.RTSn.$assign = "ball.D25";
+iMCU_UART1.RXD.$assign = "ball.C24";
+iMCU_UART1.TXD.$assign = "ball.C25";
+const iMMCSD1 = scripting.addPeripheral("MMCSD");
+iMMCSD1.$name = "MyMMCSD0";
+iMMCSD1.$assign = "MMC_0";
+iMMCSD1.CALPAD.$assign = "ball.AF1";
+iMMCSD1.CLK.$assign = "ball.AC6";
+iMMCSD1.CMD.$assign = "ball.AF2";
+iMMCSD1.DAT0.$assign = "ball.AF4";
+iMMCSD1.DAT1.$assign = "ball.AD3";
+iMMCSD1.DAT2.$assign = "ball.AD4";
+iMMCSD1.DAT3.$assign = "ball.AF3";
+iMMCSD1.DAT4.$assign = "ball.AE2";
+iMMCSD1.DAT5.$assign = "ball.AG3";
+iMMCSD1.DAT6.$assign = "ball.AE1";
+iMMCSD1.DAT7.$assign = "ball.AG1";
+iMMCSD1.DS.$assign = "ball.AE3";
+iMMCSD1.SDCD.$used = false;
+iMMCSD1.SDWP.$used = false;
+const iMMCSD2 = scripting.addPeripheral("MMCSD");
+iMMCSD2.$name = "MyMMCSD1";
+iMMCSD2.$assign = "MMC_1";
+iMMCSD2.CALPAD.$used = false;
+iMMCSD2.CLK.$assign = "ball.P23";
+iMMCSD2.CMD.$assign = "ball.N24";
+iMMCSD2.DAT0.$assign = "ball.M23";
+iMMCSD2.DAT1.$assign = "ball.P24";
+iMMCSD2.DAT2.$assign = "ball.R24";
+iMMCSD2.DAT3.$assign = "ball.R22";
+iMMCSD2.DAT4.$used = false;
+iMMCSD2.DAT5.$used = false;
+iMMCSD2.DAT6.$used = false;
+iMMCSD2.DAT7.$used = false;
+iMMCSD2.DS.$used = false;
+iMMCSD2.SDCD.$assign = "ball.AE25";
+iMMCSD2.SDWP.$used = false;
+const iOSC1 = scripting.addPeripheral("OSC");
+iOSC1.$name = "MyOSC1";
+iOSC1.$assign = "OSC_1";
+iOSC1.XI.$assign = "ball.M28";
+iOSC1.XO.$assign = "ball.L28";
+const iPCIE1 = scripting.addPeripheral("PCIE");
+iPCIE1.$name = "MyPCIE1";
+iPCIE1.REFCLKN.$used = false;
+iPCIE1.REFCLKP.$used = false;
+iPCIE1.CLKREQn.$used = false;
+iPCIE1.RXN0.$assign = "ball.AF9";
+iPCIE1.RXN1.$used = false;
+iPCIE1.RXN2.$used = false;
+iPCIE1.RXN3.$used = false;
+iPCIE1.RXP0.$assign = "ball.AF10";
+iPCIE1.RXP1.$used = false;
+iPCIE1.RXP2.$used = false;
+iPCIE1.RXP3.$used = false;
+iPCIE1.TXN0.$assign = "ball.AH7";
+iPCIE1.TXN1.$used = false;
+iPCIE1.TXN2.$used = false;
+iPCIE1.TXN3.$used = false;
+iPCIE1.TXP0.$assign = "ball.AH8";
+iPCIE1.TXP1.$used = false;
+iPCIE1.TXP2.$used = false;
+iPCIE1.TXP3.$used = false;
+const iSERDES1 = scripting.addPeripheral("SERDES");
+iSERDES1.$name = "MySERDES0";
+iSERDES1.REFCLK_N.$assign = "ball.AH4";
+iSERDES1.REFCLK_P.$assign = "ball.AH5";
+iSERDES1.REXT.$assign = "ball.AC10";
+const iSYSTEM1 = scripting.addPeripheral("SYSTEM");
+iSYSTEM1.$name = "MySYSTEM0";
+iSYSTEM1.$assign = "SYSTEM_0";
+iSYSTEM1.MCU_ADC_EXT_TRIGGER0.$used = false;
+iSYSTEM1.MCU_ADC_EXT_TRIGGER1.$used = false;
+iSYSTEM1.AUDIO_EXT_REFCLK0.$used = false;
+iSYSTEM1.AUDIO_EXT_REFCLK1.$used = false;
+iSYSTEM1.EXTINTn.$assign = "ball.AG24";
+iSYSTEM1.EXT_REFCLK1.$used = false;
+iSYSTEM1.FCLK_MUX.$used = false;
+iSYSTEM1.OBSCLK0.$used = false;
+iSYSTEM1.OBSCLK1.$used = false;
+iSYSTEM1.RESETSTATz.$assign = "ball.AF27";
+iSYSTEM1.SOC_SAFETY_ERRORn.$assign = "ball.AF25";
+iSYSTEM1.SYSCLKOUT0.$used = false;
+const iUART1 = scripting.addPeripheral("UART");
+iUART1.$name = "MyUART8";
+iUART1.$assign = "USART_8";
+iUART1.CTSn.$assign = "ball.AC28";
+iUART1.DCDn.$used = false;
+iUART1.DSRn.$used = false;
+iUART1.DTRn.$used = false;
+iUART1.RIn.$used = false;
+iUART1.RTSn.$assign = "ball.Y26";
+iUART1.RXD.$assign = "ball.AF26";
+iUART1.TXD.$assign = "ball.AH27";
+const iUART2 = scripting.addPeripheral("UART");
+iUART2.$name = "MyUART2";
+iUART2.$assign = "USART_2";
+iUART2.CTSn.$used = false;
+iUART2.DCDn.$used = false;
+iUART2.DSRn.$used = false;
+iUART2.DTRn.$used = false;
+iUART2.RIn.$used = false;
+iUART2.RTSn.$used = false;
+iUART2.RXD.$assign = "ball.AG26";
+iUART2.TXD.$assign = "ball.AH26";
+const iUART3 = scripting.addPeripheral("UART");
+iUART3.$name = "MyUART5";
+iUART3.$assign = "USART_5";
+iUART3.CTSn.$used = false;
+iUART3.DCDn.$used = false;
+iUART3.DSRn.$used = false;
+iUART3.DTRn.$used = false;
+iUART3.RIn.$used = false;
+iUART3.RTSn.$used = false;
+iUART3.RXD.$assign = "ball.AC24";
+iUART3.TXD.$assign = "ball.W25";
+const iUSB1 = scripting.addPeripheral("USB");
+iUSB1.$name = "MyUSB0";
+iUSB1.DM.$assign = "ball.AG2";
+iUSB1.DP.$assign = "ball.AH2";
+iUSB1.DRVVBUS.$assign = "ball.AG25";
+iUSB1.ID.$assign = "ball.AC9";
+iUSB1.RCALIB.$assign = "ball.AA6";
+iUSB1.SSRX1N.$used = false;
+iUSB1.SSRX1P.$used = false;
+iUSB1.SSRX2N.$assign = "ball.AE8";
+iUSB1.SSRX2P.$assign = "ball.AE9";
+iUSB1.SSTX1N.$used = false;
+iUSB1.SSTX1P.$used = false;
+iUSB1.SSTX2N.$assign = "ball.AG8";
+iUSB1.SSTX2P.$assign = "ball.AG9";
+iUSB1.VBUS.$assign = "ball.AA8";
+const iWKUP_GPIO1 = scripting.addPeripheral("WKUP_GPIO");
+iWKUP_GPIO1["0"].$assign = "ball.D26";
+iWKUP_GPIO1["1"].$assign = "ball.E24";
+iWKUP_GPIO1["2"].$assign = "ball.C28";
+iWKUP_GPIO1["3"].$assign = "ball.C27";
+iWKUP_GPIO1["4"].$used = false;
+iWKUP_GPIO1["5"].$used = false;
+iWKUP_GPIO1["6"].$assign = "ball.E25";
+iWKUP_GPIO1["7"].$assign = "ball.F28";
+iWKUP_GPIO1["8"].$used = false;
+iWKUP_GPIO1["9"].$used = false;
+iWKUP_GPIO1["10"].$used = false;
+iWKUP_GPIO1["11"].$used = false;
+iWKUP_GPIO1["12"].$used = false;
+iWKUP_GPIO1["13"].$used = false;
+iWKUP_GPIO1["14"].$used = false;
+iWKUP_GPIO1["15"].$used = false;
+iWKUP_GPIO1["16"].$used = false;
+iWKUP_GPIO1["17"].$used = false;
+iWKUP_GPIO1["18"].$used = false;
+iWKUP_GPIO1["19"].$used = false;
+iWKUP_GPIO1["20"].$used = false;
+iWKUP_GPIO1["21"].$used = false;
+iWKUP_GPIO1["22"].$used = false;
+iWKUP_GPIO1["23"].$used = false;
+iWKUP_GPIO1["24"].$used = false;
+iWKUP_GPIO1["25"].$used = false;
+iWKUP_GPIO1["26"].$used = false;
+iWKUP_GPIO1["27"].$used = false;
+iWKUP_GPIO1["28"].$used = false;
+iWKUP_GPIO1["29"].$used = false;
+iWKUP_GPIO1["30"].$used = false;
+iWKUP_GPIO1["31"].$used = false;
+iWKUP_GPIO1["32"].$used = false;
+iWKUP_GPIO1["33"].$used = false;
+iWKUP_GPIO1["34"].$used = false;
+iWKUP_GPIO1["35"].$used = false;
+iWKUP_GPIO1["36"].$used = false;
+iWKUP_GPIO1["37"].$used = false;
+iWKUP_GPIO1["38"].$used = false;
+iWKUP_GPIO1["39"].$assign = "ball.C21";
+iWKUP_GPIO1["40"].$used = false;
+iWKUP_GPIO1["41"].$used = false;
+iWKUP_GPIO1["42"].$used = false;
+iWKUP_GPIO1["43"].$used = false;
+iWKUP_GPIO1["44"].$used = false;
+iWKUP_GPIO1["45"].$used = false;
+iWKUP_GPIO1["46"].$used = false;
+iWKUP_GPIO1["47"].$used = false;
+iWKUP_GPIO1["48"].$used = false;
+iWKUP_GPIO1["49"].$assign = "ball.K26";
+iWKUP_GPIO1["50"].$used = false;
+iWKUP_GPIO1["51"].$used = false;
+iWKUP_GPIO1["52"].$used = false;
+iWKUP_GPIO1["53"].$used = false;
+iWKUP_GPIO1["54"].$assign = "ball.B27";
+iWKUP_GPIO1["54"].$used = false;
+iWKUP_GPIO1["55"].$assign = "ball.D24";
+iWKUP_GPIO1["56"].$assign = "ball.G27";
+iWKUP_GPIO1["57"].$assign = "ball.J26";
+iWKUP_GPIO1["57"].$used = false;
+iWKUP_GPIO1["58"].$used = false;
+iWKUP_GPIO1["59"].$used = false;
+iWKUP_GPIO1["60"].$used = false;
+iWKUP_GPIO1["61"].$used = false;
+iWKUP_GPIO1["62"].$used = false;
+iWKUP_GPIO1["63"].$used = false;
+iWKUP_GPIO1["64"].$used = false;
+iWKUP_GPIO1["65"].$used = false;
+iWKUP_GPIO1["66"].$assign = "ball.G25";
+iWKUP_GPIO1["66"].$used = false;
+iWKUP_GPIO1["67"].$used = false;
+iWKUP_GPIO1["68"].$used = false;
+iWKUP_GPIO1["69"].$assign = "ball.B25";
+iWKUP_GPIO1["70"].$assign = "ball.B26";
+iWKUP_GPIO1["71"].$used = false;
+iWKUP_GPIO1["72"].$used = false;
+iWKUP_GPIO1["73"].$used = false;
+iWKUP_GPIO1["74"].$used = false;
+iWKUP_GPIO1["75"].$used = false;
+iWKUP_GPIO1["76"].$used = false;
+iWKUP_GPIO1["77"].$used = false;
+iWKUP_GPIO1["78"].$used = false;
+iWKUP_GPIO1["79"].$used = false;
+iWKUP_GPIO1["80"].$used = false;
+iWKUP_GPIO1["81"].$used = false;
+iWKUP_GPIO1["82"].$used = false;
+iWKUP_GPIO1["83"].$used = false;
+iWKUP_GPIO1["84"].$used = false;
+iWKUP_GPIO1["85"].$used = false;
+iWKUP_GPIO1["86"].$used = false;
+iWKUP_GPIO1["87"].$used = false;
+iWKUP_GPIO1["88"].$used = false;
+iWKUP_GPIO1.$name = "MyWKUP_GPIO0";
+iWKUP_GPIO1.$assign = "WKUP_GPIO_0";
+const iWKUP_I2C1 = scripting.addPeripheral("WKUP_I2C");
+iWKUP_I2C1.$name = "MyWKUP_I2C0";
+iWKUP_I2C1.$assign = "WKUP_I2C_0";
+iWKUP_I2C1.SCL.$assign = "ball.H24";
+iWKUP_I2C1.SDA.$assign = "ball.H27";
+const iWKUP_OSC1 = scripting.addPeripheral("WKUP_OSC");
+iWKUP_OSC1.$name = "MyWKUP_OSC1";
+iWKUP_OSC1.$assign = "WKUP_OSC_0";
+iWKUP_OSC1.XI.$assign = "ball.H28";
+iWKUP_OSC1.XO.$assign = "ball.J28";
+const iWKUP_UART1 = scripting.addPeripheral("WKUP_UART");
+iWKUP_UART1.$name = "MyWKUP_UART0";
+iWKUP_UART1.CTSn.$used = false;
+iWKUP_UART1.RTSn.$used = false;
+iWKUP_UART1.RXD.$assign = "ball.D28";
+iWKUP_UART1.TXD.$assign = "ball.D27";
+
+/**
+ * Pinmux solution for unlocked pins/peripherals. This ensures that minor changes to the automatic solver in a future
+ * version of the tool will not impact the pinmux you originally saw. These lines can be completely deleted in order to
+ * re-solve from scratch.
+ */
+iAUXPHY1.$suggestSolution = "AUXPHY_0";
+iCSI1.$suggestSolution = "CSI_RX_0";
+iCSI2.$suggestSolution = "CSI_RX_1";
+iDP1.$suggestSolution = "DP_0";
+iMCU_ADC2.$suggestSolution = "MCU_ADC_1";
+iMCU_OSPI1.$suggestSolution = "MCU_OSPI_0";
+iMCU_OSPI2.$suggestSolution = "MCU_OSPI_1";
+iPCIE1.$suggestSolution = "PCIE_1";
+iSERDES1.$suggestSolution = "SERDES_0";
+iUSB1.$suggestSolution = "USB_0";
+iWKUP_UART1.$suggestSolution = "WKUP_USART_0";
diff --git a/packages/ti/board/src/j721s2_evm/src_files_j721s2_evm.mk b/packages/ti/board/src/j721s2_evm/src_files_j721s2_evm.mk
--- /dev/null
@@ -0,0 +1,9 @@
+
+SRCDIR += src/j721s2_evm src/j721s2_evm/include
+INCDIR += src/j721s2_evm src/j721s2_evm/include
+
+# Common source files across all platforms and cores
+SRCS_COMMON += board_init.c board_lld_init.c board_clock.c board_mmr.c board_pll.c
+SRCS_COMMON += board_ddr.c board_info.c board_ethernet_config.c board_utils.c board_control.c board_i2c_io_exp.c
+SRCS_COMMON += board_pinmux.c J721S2_pinmux_data.c
+PACKAGE_SRCS_COMMON = src/j721s2_evm/src_files_j721s2_evm.mk