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raw | patch | inline | side by side (parent: 58a4f79)
raw | patch | inline | side by side (parent: 58a4f79)
author | Hao Zhang <hzhang@ti.com> | |
Thu, 29 Oct 2020 13:56:15 +0000 (09:56 -0400) | ||
committer | Sivaraj R <sivaraj@ti.com> | |
Fri, 30 Oct 2020 09:30:46 +0000 (04:30 -0500) |
Signed-off-by: Hao Zhang <hzhang@ti.com>
diff --git a/packages/ti/board/src/flash/nor/device/s25fl256s.h b/packages/ti/board/src/flash/nor/device/s25fl256s.h
index cf97b7706a0c099b28f9c292d1a7b16cf5e47624..5efafe13d517494076356019f9b8098909b03d58 100644 (file)
/*\r
- * Copyright (c) 2016 - 2019, Texas Instruments Incorporated\r
+ * Copyright (c) 2016 - 2020, Texas Instruments Incorporated\r
* All rights reserved.\r
*\r
* Redistribution and use in source and binary forms, with or without\r
#define NOR_CMD_QUAD_READ (0x6CU)\r
#define NOR_CMD_PAGE_PROG (0x12U)\r
#define NOR_CMD_QUAD_PAGE_PROG (0x34U)\r
+#define NOR_CMD_QUAD_DDR_IO_READ (0xEEU)\r
#else\r
#define NOR_CMD_BLOCK_ERASE (0xD8U)\r
#define NOR_CMD_SECTOR_ERASE (0x20U)\r
#define NOR_CMD_QUAD_READ (0x6BU)\r
#define NOR_CMD_PAGE_PROG (0x02U)\r
#define NOR_CMD_QUAD_PAGE_PROG (0x32U)\r
+#define NOR_CMD_QUAD_DDR_IO_READ (0xEDU)\r
#endif\r
\r
/* \brief Read ID command definitions */\r
index ff40c4fe446f2bb08a3e4403c6a99c21dfd44975..d609c6f03d94c470d6c56c4050e0d1e3db127ce1 100755 (executable)
NULL
}
};
-#elif defined (am65xx_evm) || defined (am65xx_idk) || defined (am64x_evm) || defined(am64x_svb)
+#elif defined (am65xx_evm) || defined (am65xx_idk)
NOR_Config Nor_config[BOARD_FLASH_NOR_INTF_MAX] =
{
{
NULL
}
};
+#elif defined (am64x_evm) || defined(am64x_svb)
+NOR_Config Nor_config[BOARD_FLASH_NOR_INTF_MAX] =
+{
+ {
+ NULL
+ },
+ {
+ &Nor_qspiFxnTable
+ },
+ {
+ NULL
+ },
+ {
+ &Nor_ospiFxnTable
+ },
+ {
+ NULL
+ }
+};
#elif defined (j721e_sim) || defined (j721e_evm)
NOR_Config Nor_config[BOARD_FLASH_NOR_INTF_MAX] =
{
diff --git a/packages/ti/board/src/flash/nor/ospi/nor_qspi.c b/packages/ti/board/src/flash/nor/ospi/nor_qspi.c
index 6e99604797d47166c4edaa10a842b1e8196552a3..f599d65a1cce727a3276485b37f5843f9900a01a 100755 (executable)
/*\r
- * Copyright (c) 2018 - 2019, Texas Instruments Incorporated\r
+ * Copyright (c) 2018 - 2020, Texas Instruments Incorporated\r
* All rights reserved.\r
*\r
* Redistribution and use in source and binary forms, with or without\r
#if defined (j7200_evm)\r
/* Entry offset is at index 5 of SPI config array*/\r
#define SPI_CONFIG_OFFSET (5U)\r
+#elif defined (am64x_evm)\r
+#define SPI_CONFIG_OFFSET (7U)\r
#else\r
#define SPI_CONFIG_OFFSET CSL_MCSPI_PER_CNT\r
#endif\r
static NOR_STATUS Nor_qspiEnableDDR(SPI_Handle handle)\r
{\r
OSPI_v0_HwAttrs const *hwAttrs;\r
- NOR_STATUS retVal;\r
+ NOR_STATUS retVal = NOR_PASS;\r
uint8_t cmdWren = NOR_CMD_WREN;\r
+ uint8_t data[3];\r
uint32_t opCode[3];\r
uint32_t dummyCycles;\r
uint32_t rx_lines;\r
- uint8_t data[3];\r
\r
hwAttrs = (OSPI_v0_HwAttrs const *)handle->hwAttrs;\r
\r
+#if defined (j721e_evm) || defined (j7200_evm)\r
/* Send Write Enable command */\r
if (Nor_qspiCmdWrite(handle, &cmdWren, 1, 0))\r
{\r
SPI_control(handle, SPI_V0_CMD_SET_XFER_LINES, (void *)&rx_lines);\r
SPI_control(handle, SPI_V0_CMD_XFER_OPCODE, (void *)opCode);\r
}\r
+#else\r
+ /* Send Write Enable command */\r
+ if (Nor_qspiCmdWrite(handle, &cmdWren, 1, 0))\r
+ {\r
+ return NOR_FAIL;\r
+ }\r
\r
+ if (Nor_qspiWaitReady(handle, NOR_WRR_WRITE_TIMEOUT))\r
+ {\r
+ return NOR_FAIL;\r
+ }\r
+\r
+ /* Write CR1 register to enable QSPI mode */\r
+ data[0] = NOR_CMD_WRR;\r
+ data[1] = 0x02;\r
+ retVal = Nor_qspiCmdWrite(handle, data, 1, 1);\r
+ if (retVal == NOR_PASS)\r
+ {\r
+ if (Nor_qspiWaitReady(handle, NOR_WRR_WRITE_TIMEOUT))\r
+ {\r
+ return NOR_FAIL;\r
+ }\r
+\r
+ /* Set opcodes */\r
+ dummyCycles = NOR_QUAD_READ_DUMMY_CYCLE;\r
+ rx_lines = OSPI_XFER_LINES_QUAD;\r
+ opCode[0] = NOR_CMD_QUAD_DDR_IO_READ;\r
+ opCode[1] = NOR_CMD_QUAD_PAGE_PROG;\r
+ opCode[2] = NOR_CMD_RDSR;\r
+\r
+ /* Update the read opCode, rx lines and read dummy cycles */\r
+ SPI_control(handle, SPI_V0_CMD_RD_DUMMY_CLKS, (void *)&dummyCycles);\r
+ SPI_control(handle, SPI_V0_CMD_SET_XFER_LINES, (void *)&rx_lines);\r
+ SPI_control(handle, SPI_V0_CMD_XFER_OPCODE, (void *)opCode);\r
+ }\r
+#endif\r
CSL_ospiDtrEnable((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr), TRUE);\r
\r
return retVal;\r
{\r
OSPI_v0_HwAttrs const *hwAttrs;\r
CSL_ospi_flash_cfgRegs *regAddr;\r
- NOR_STATUS retVal;\r
+ NOR_STATUS retVal = NOR_PASS;\r
uint8_t cmdWren = NOR_CMD_WREN;\r
+ uint8_t data[3];\r
uint32_t opCode[3];\r
uint32_t dummyCycles;\r
uint32_t rx_lines;\r
- uint8_t data[3];\r
uint32_t regVal;\r
\r
hwAttrs = (OSPI_v0_HwAttrs const *)handle->hwAttrs;\r
\r
+#if defined (j721e_evm) || defined (j7200_evm)\r
/* Send Write Enable command */\r
if (Nor_qspiCmdWrite(handle, &cmdWren, 1, 0))\r
{\r
retVal = Nor_qspiCmdWrite(handle, data, 1, 1);\r
if (retVal == NOR_PASS)\r
{\r
+ if (Nor_qspiWaitReady(handle, NOR_WRR_WRITE_TIMEOUT))\r
+ {\r
+ return NOR_FAIL;\r
+ }\r
+\r
dummyCycles = NOR_QUAD_READ_DUMMY_CYCLE;\r
rx_lines = OSPI_XFER_LINES_QUAD;\r
opCode[0] = NOR_CMD_QUAD_IO_FAST_RD;\r
SPI_control(handle, SPI_V0_CMD_SET_XFER_LINES, (void *)&rx_lines);\r
SPI_control(handle, SPI_V0_CMD_XFER_OPCODE, (void *)opCode);\r
}\r
+#else\r
+ /* Send Write Enable command */\r
+ if (Nor_qspiCmdWrite(handle, &cmdWren, 1, 0))\r
+ {\r
+ return NOR_FAIL;\r
+ }\r
\r
+ if (Nor_qspiWaitReady(handle, NOR_WRR_WRITE_TIMEOUT))\r
+ {\r
+ return NOR_FAIL;\r
+ }\r
+\r
+ /* Write CR1 register to enable QSPI mode */\r
+ data[0] = NOR_CMD_WRR;\r
+ data[1] = 0x02;\r
+ retVal = Nor_qspiCmdWrite(handle, data, 1, 1);\r
+ if (retVal == NOR_PASS)\r
+ {\r
+ rx_lines = OSPI_XFER_LINES_QUAD;\r
+ opCode[0] = NOR_CMD_QUAD_READ;\r
+ opCode[1] = NOR_CMD_PAGE_PROG;\r
+ opCode[2] = NOR_CMD_RDSR;\r
+\r
+ SPI_control(handle, SPI_V0_CMD_RD_DUMMY_CLKS, (void *)&dummyCycles);\r
+ SPI_control(handle, SPI_V0_CMD_SET_XFER_LINES, (void *)&rx_lines);\r
+ SPI_control(handle, SPI_V0_CMD_XFER_OPCODE, (void *)opCode);\r
+ }\r
+#endif\r
/* Flash device requires 4-bit access for command as well in quad mode */\r
regAddr = (CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr);\r
regVal = CSL_REG32_RD(®Addr->DEV_INSTR_RD_CONFIG_REG);\r
regVal |= 0x200;\r
CSL_REG32_WR(®Addr->DEV_INSTR_RD_CONFIG_REG, regVal);\r
\r
- return NOR_PASS;\r
+ return retVal;\r
}\r
\r
static NOR_STATUS Nor_qspiXipEnable(SPI_Handle handle)\r
diff --git a/packages/ti/board/src/flash/nor/ospi/nor_qspi.h b/packages/ti/board/src/flash/nor/ospi/nor_qspi.h
index 9d3aecaf3aa7a2cefc76eca0446e6acf6ae331e5..694fb8f58f2a0659ce01bbf9a436e1e1d48074dd 100755 (executable)
/*\r
- * Copyright (c) 2018, Texas Instruments Incorporated\r
+ * Copyright (c) 2018 - 2020, Texas Instruments Incorporated\r
* All rights reserved.\r
*\r
* Redistribution and use in source and binary forms, with or without\r
\r
#include <ti/board/src/flash/nor/nor.h>\r
#include <ti/drv/spi/SPI.h>\r
-//#include <ti/drv/spi/src/v0/OSPI_v0.h>\r
#include <ti/drv/spi/soc/SPI_soc.h>\r
+#if defined (am64x_evm)\r
+#include <ti/board/src/flash/nor/device/s25fl256s.h>\r
+#else\r
#include <ti/board/src/flash/nor/device/mt25qu512abb.h>\r
+#endif\r
\r
/**************************************************************************\r
** Macro Definitions\r
diff --git a/packages/ti/board/src/flash/src_files_flash.mk b/packages/ti/board/src/flash/src_files_flash.mk
index 816e821b7df90506d9cd342829574e150d3c4656..55d2f6e3fcf976485dd11fd446d01f11bc93a4f8 100755 (executable)
@@ -109,6 +109,13 @@ PACKAGE_SRCS_COMMON += src/flash/nor/ospi/nor_qspi.c src/flash/nor/ospi/nor_qspi
PACKAGE_SRCS_COMMON += src/flash/nor/hyperflash/nor_hyperflash.c src/flash/nor/hyperflash/nor_hyperflash.h
PACKAGE_SRCS_COMMON += src/flash/nor/device/s71ks512s.h
PACKAGE_SRCS_COMMON += src/flash/nor/device/mt25qu512abb.h
+PACKAGE_SRCS_COMMON += src/flash/nor/device/s25fl256s.h
+endif
+
+ifeq ($(BOARD),$(filter $(BOARD), am64x_evm))
+SRCS_COMMON += nor_qspi.c
+PACKAGE_SRCS_COMMON += src/flash/nor/ospi/nor_qspi.c src/flash/nor/ospi/nor_qspi.h
+PACKAGE_SRCS_COMMON += src/flash/nor/device/s25fl256s.h
endif
ifeq ($(BOARD),$(filter $(BOARD), tpr12_evm tpr12_qt))
diff --git a/packages/ti/drv/spi/test/ospi_flash/src/main_ospi_flash_test.c b/packages/ti/drv/spi/test/ospi_flash/src/main_ospi_flash_test.c
index adb64da140719e7307486353fd95b97100c2924a..afe6cf3c55c9776a57ade36e3aaccef9b57cf774 100644 (file)
#define OSPI_PROFILE /* Enable profiling */
#define OSPI_WRITE /* Enable write */
#define OSPI_WRITE_TUNING /* Enable write tuning data pattern to the falsh */
+#undef OSPI_QSPI_FLASH /* Enable QSPI flash test using OSPI controller */
/* OSPI test ID definitions */
#define OSPI_TEST_ID_DAC_133M 0 /* OSPI flash test in Direct Acess Controller mode at 133MHz RCLK */
/* Get the default OSPI init configurations */
OSPI_socGetInitCfg(BOARD_OSPI_NOR_INSTANCE, &ospi_cfg);
+#ifdef OSPI_QSPI_FLASH
+ ospi_cfg.xferLines = OSPI_XFER_LINES_QUAD;
+#endif
+
/* Modify the default OSPI configurations */
ospi_cfg.dacEnable = test->dacMode;
if (test->dacMode)
deviceId = BOARD_FLASH_ID_MT35XU512ABA1G12;
#if defined(SOC_AM64X)
+#ifdef OSPI_QSPI_FLASH
+ deviceId = BOARD_FLASH_ID_S25FL256S;
+#else
deviceId = BOARD_FLASH_ID_MT35XU256ABA1G12;
#endif
+#endif
#if defined(SOC_J7200)
deviceId = BOARD_FLASH_ID_S28HS512T;