PDK-6948: Board: Enabled PLL configurations in am64x board library
authorM V Pratap Reddy <x0257344@ti.com>
Fri, 27 Nov 2020 09:36:25 +0000 (15:06 +0530)
committerM V Pratap Reddy <x0257344@ti.com>
Fri, 27 Nov 2020 09:36:25 +0000 (15:06 +0530)
 - Enabling only limited PLL configurations as most of the PLL clocks
   are fixed and should be configured by default.

packages/ti/board/src/am64x_evm/board_pll.c
packages/ti/board/src/am64x_evm/include/board_pll.h

index e975c303af76f344da553b7f22880af50b3004a7..1aec47411550163c3ac0de85107a3e92a38c07c1 100644 (file)
 #include "board_pll.h"\r
 #include <ti/drv/sciclient/sciclient.h>\r
 \r
+static Board_PllClkCfg_t gBoardPllClkCfg[] =\r
+{\r
+\r
+ { TISCI_DEV_MCU_UART0,\r
+   TISCI_DEV_MCU_UART0_FCLK_CLK,\r
+   96000000\r
+ }, //MCU_PLL0_HSDIV2_CLKOUT,\r
+\r
+ { TISCI_DEV_MCU_I2C0,\r
+   TISCI_DEV_MCU_UART0_FCLK_CLK,\r
+   96000000\r
+ }, //MCU_PLL0_HSDIV1_CLKOUT,\r
+\r
+ { TISCI_DEV_UART0,\r
+   TISCI_DEV_UART0_FCLK_CLK,\r
+   48000000\r
+ }, //MAIN_PLL1_HSDIV1_CLKOUT,\r
+\r
+ { TISCI_DEV_FSS0_OSPI_0,\r
+   TISCI_DEV_FSS0_OSPI_0_OSPI_RCLK_CLK,\r
+   166666666\r
+ }, //MAIN_PLL0_HSDIV1_CLKOUT,\r
+\r
+ { TISCI_DEV_PRU_ICSSG0,\r
+   TISCI_DEV_PRU_ICSSG0_CORE_CLK,\r
+   225000000\r
+ }, //MAIN_PLL2_HSDIV0_CLKOUT,\r
+\r
+ { TISCI_DEV_PRU_ICSSG0,\r
+   TISCI_DEV_PRU_ICSSG0_UCLK_CLK,\r
+   192000000\r
+ }, //MAIN_PLL1_HSDIV0_CLKOUT,\r
+\r
+ { TISCI_DEV_PRU_ICSSG0,\r
+   TISCI_DEV_PRU_ICSSG0_RGMII_MHZ_250_CLK,\r
+   250000000\r
+ }, //MAIN_PLL0_HSDIV4_CLKOUT,\r
+\r
+ { TISCI_DEV_MCAN0,\r
+   TISCI_DEV_MCAN0_MCANSS_CCLK_CLK,\r
+   80000000\r
+ }, //MAIN_PLL0_HSDIV2_CLKOUT,\r
+\r
+};\r
+\r
 /**\r
  * \brief  PLL clock enable\r
  *\r
@@ -205,5 +250,22 @@ Board_STATUS Board_PLLInit(uint32_t modId,
  */\r
 Board_STATUS Board_PLLInitAll(void)\r
 {\r
-    return BOARD_SOK;\r
+    Board_STATUS  status = BOARD_SOK;\r
+    uint32_t index;\r
+    uint32_t loopCount;\r
+\r
+    loopCount = sizeof (gBoardPllClkCfg)/sizeof(Board_PllClkCfg_t);\r
+\r
+    for (index = 0; index < loopCount; index++)\r
+    {\r
+        status = Board_PLLInit(gBoardPllClkCfg[index].tisciDevID,\r
+                               gBoardPllClkCfg[index].tisciClkID,\r
+                               gBoardPllClkCfg[index].clkRate);\r
+        if(status != BOARD_SOK)\r
+        {\r
+            BOARD_DEBUG_LOG("Failed to set the PLL clock freq at index =%d\n\n",index);\r
+        }\r
+    }\r
+\r
+    return status;\r
 }\r
index d2cc59944d2b132273bd4b0b54e3c91907c41740..9257c50a41fadbae744ce6ca0351a10745292ac1 100644 (file)
@@ -59,6 +59,13 @@ extern "C" {
 \r
 #define DDR_PLL_INDEX          12\r
 \r
+typedef struct Board_PllClkCfg_s\r
+{\r
+    uint32_t tisciDevID;\r
+    uint32_t tisciClkID;\r
+    uint64_t clkRate;\r
+} Board_PllClkCfg_t;\r
+\r
 #ifdef __cplusplus\r
 }\r
 #endif /* __cplusplus */\r