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raw | patch | inline | side by side (parent: e01683b)
raw | patch | inline | side by side (parent: e01683b)
author | Vivek Dhande <a0132295@ti.com> | |
Mon, 18 Oct 2021 05:28:04 +0000 (10:58 +0530) | ||
committer | Ankur <ankurbaranwal@ti.com> | |
Mon, 18 Oct 2021 05:43:18 +0000 (00:43 -0500) |
Signed-off-by: Vivek Dhande <a0132295@ti.com>
index 6b82b63ae6a04e8fd0289bb8ba8fee9104fc0e61..45b8a9d32908ab2172947457581392cac1c30dcf 100644 (file)
SDR_MemConfig_t *pMemConfig);
#ifdef SOC_J721E
-#pragma DATA_SECTION(mappedEccRegs, ".my_aggr_reg");
/* Note that this example provide a single instance of mappedEccRegs (which is RAT-mapped
* ECC aggregator configuration registers that lie in larger address space than the 32-bit
* address space on the MCU. If more ECC aggregator registers need to be mapped, additional
* The expectation is that this mapping will be retained in perpetuity because in order to obtain
* information about the ECC errors, the ECC Aggregator configuration registers require to be
* visible from the MCU. */
-CSL_ecc_aggrRegs mappedEccRegs;
+__attribute((section(".my_aggr_reg"))) CSL_ecc_aggrRegs mappedEccRegs;
#endif
/** ============================================================================*
index 0fcf0c4308ab105bbc9e4156f6f4eb8e30492fe6..c7477a0d4ff92ad391c8400cdd34ce35387073a4 100644 (file)
lpm_example_$(1)_PKG_LIST = lpm_example_$(1)
lpm_example_$(1)_INCLUDE = $(lpm_example_$(1)_PATH)
export lpm_example_$(1)_BOARDLIST = j721e_evm j7200_evm
-export lpm_example_$(1)_$(SOC)_CORELIST = mcu1_0
+export lpm_example_$(1)_$(SOC)_CORELIST = $(filter $(DEFAULT_$(SOC)_CORELIST_$(1)), $(lpm_$(SOC)_CORELIST))
export lpm_example_$(1)_SBL_APPIMAGEGEN = yes
lpm_EXAMPLE_LIST += lpm_example_$(1)
index 726ba4d1f53ab481fb6450c43d98ecfd8243f9b0..293aeb81650b7f4372f4edd4c56b1d893913c929 100644 (file)
@@ -300,7 +300,7 @@ static int32_t Lpm_ospiBootStageImage(sblEntryPoint_t *pEntry, uint32_t address)
{
int32_t status = E_FAIL;
- if ((NULL != address) && (NULL != pEntry))
+ if (((uint32_t)NULL != address) && ((sblEntryPoint_t *)NULL != pEntry))
{
if (address != MAIN_DOMAIN_HLOS)
{
if ((k3xx_evmEntry.CpuEntryPoint[core_id] != SBL_INVALID_ENTRY_ADDR) &&
((core_id != MCU1_CPU1_ID) && (core_id != MCU1_CPU0_ID)))
{
- SBL_SlaveCoreBoot(core_id, NULL, &k3xx_evmEntry, SBL_REQUEST_CORE);
+ SBL_SlaveCoreBoot(core_id, (uint32_t)NULL, &k3xx_evmEntry, SBL_REQUEST_CORE);
TaskP_sleep(1*1000);
#if defined(UART_PRINT_DEBUG)
AppUtils_Printf(MSG_NORMAL,
index 26d6d71a7e386445984bd2d1a232688112b2f18f..9a3351ec9a6346306dc06f3568fb5cecdd61a177 100644 (file)
uint32_t rpmsgDataSize = RPMSG_DATA_SIZE;
-#pragma DATA_SECTION(Ipc_traceBuffer, ".tracebuf")
-char Ipc_traceBuffer[IPC_TRACE_BUFFER_MAX_SIZE];
+__attribute((section(".tracebuf"))) char Ipc_traceBuffer[IPC_TRACE_BUFFER_MAX_SIZE];
uint8_t gOcmcShadowRscTable[0x8C];
uint8_t *pOcmcShadowRscTable = gOcmcShadowRscTable;
index 9bcb1d8a7f7cd6e7a25cd2df5cc1b28b344a5e2e..3075e7715621146411004a833bdcfb8b5e12d3ec 100644 (file)
struct tisci_boardcfg_rm_resasg_entry resasg_entries[TISCI_RESASG_ENTRIES_MAX];
};
-#pragma DATA_SECTION(bootAppBoardCfg, ".sysfw_data_cfg_board")
-struct tisci_boardcfg bootAppBoardCfg;
-#pragma DATA_SECTION(bootAppBoardCfg_rm, ".sysfw_data_cfg_board_rm")
-struct bootApp_local_rm_boardcfg bootAppBoardCfg_rm;
-#pragma DATA_SECTION(bootAppBoardCfg_sec, ".sysfw_data_cfg_board_sec")
-struct tisci_boardcfg_sec bootAppBoardCfg_sec;
+__attribute((section(".sysfw_data_cfg_board"))) struct tisci_boardcfg bootAppBoardCfg;
+__attribute((section(".sysfw_data_cfg_board_rm"))) struct bootApp_local_rm_boardcfg bootAppBoardCfg_rm;
+__attribute((section(".sysfw_data_cfg_board_sec"))) struct tisci_boardcfg_sec bootAppBoardCfg_sec;
/* ========================================================================== */
/* Internal Function Declarations */