PDK-5918: ECC Example application functional 6/6 use cases.
authorDanny Jochelson <dsjochel@ti.com>
Thu, 24 Sep 2020 20:00:40 +0000 (15:00 -0500)
committerSivaraj R <sivaraj@ti.com>
Wed, 30 Sep 2020 05:24:16 +0000 (00:24 -0500)
All 6 use cases are functional.

13 files changed:
packages/ti/diag/examples/diag_ex_component.mk
packages/ti/diag/examples/ecc_example_app/ecc_inject.c [new file with mode: 0644]
packages/ti/diag/examples/ecc_example_app/ecc_inject.h [new file with mode: 0644]
packages/ti/diag/examples/ecc_example_app/esm.c [new file with mode: 0644]
packages/ti/diag/examples/ecc_example_app/esm.h [new file with mode: 0644]
packages/ti/diag/examples/ecc_example_app/j721e/ecc_trigger_func.c [new file with mode: 0644]
packages/ti/diag/examples/ecc_example_app/j721e/ecc_trigger_func.h [new file with mode: 0644]
packages/ti/diag/examples/ecc_example_app/j721e/linker_mcu1_0.lds [new file with mode: 0644]
packages/ti/diag/examples/ecc_example_app/j721e/platform.h [new file with mode: 0644]
packages/ti/diag/examples/ecc_example_app/main.c [new file with mode: 0644]
packages/ti/diag/examples/ecc_example_app/makefile [new file with mode: 0644]
packages/ti/diag/sdr/src/j721e/sdr_ecc_soc.h
packages/ti/diag/sdr/src/sdr_ecc.c

index 4bd1285d2ffe7d0379d073c00a8db1542a908b46..400d51ecdfbbf1e1a09b889b2c49a20993519542 100644 (file)
@@ -92,6 +92,27 @@ export diag_ex_esm_example_app_SBL_APPIMAGEGEN = yes
 
 diag_ex_EXAMPLE_LIST += diag_ex_esm_example_app
 
+# ECC example
+diag_ex_ecc_example_app_COMP_LIST = diag_ex_ecc_example_app
+diag_ex_ecc_example_app_RELPATH = ti/diag/examples/ecc_example_app
+diag_ex_ecc_example_app_PATH = $(PDK_DIAG_EX_COMP_PATH)/ecc_example_app
+diag_ex_ecc_example_app_MAKEFILE = -f makefile
+diag_ex_ecc_example_app_BOARD_DEPENDENCY = yes
+diag_ex_ecc_example_app_CORE_DEPENDENCY = yes
+export diag_ex_ecc_example_app_COMP_LIST
+export diag_ex_ecc_example_app_BOARD_DEPENDENCY
+export diag_ex_ecc_example_app_CORE_DEPENDENCY
+export diag_ex_ecc_example_app_MAKEFILE
+diag_ex_ecc_example_app_PKG_LIST = diag_ex_ecc_example_app
+diag_ex_ecc_example_app_INCLUDE = $(diag_ex_ecc_example_app_PATH)
+diag_ex_ecc_example_app_BOARDLIST = $(diag_ex_BOARDLIST)
+export diag_ex_ecc_example_app_BOARDLIST
+diag_ex_ecc_example_app_$(SOC)_CORELIST = $(diag_ex_$(SOC)_CORELIST)
+export diag_ex_ecc_example_app_$(SOC)_CORELIST
+export diag_ex_ecc_example_app_SBL_APPIMAGEGEN = yes
+
+diag_ex_EXAMPLE_LIST += diag_ex_ecc_example_app
+
 export diag_ex_LIB_LIST
 export diag_ex_EXAMPLE_LIST
 
diff --git a/packages/ti/diag/examples/ecc_example_app/ecc_inject.c b/packages/ti/diag/examples/ecc_example_app/ecc_inject.c
new file mode 100644 (file)
index 0000000..676abf8
--- /dev/null
@@ -0,0 +1,504 @@
+/*
+ * ECC Example
+ *
+ * Error Correcting Code (ECC) Example Application
+ *
+ *  Copyright (c) 2020 Texas Instruments Incorporated
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+/**
+ *  \file ecc_inject.c
+ *
+ *  \brief This file contains functions that provide input ECC event triggers
+ *         for the Error Correcting Code Module (ECC) application.
+ */
+
+/* ========================================================================== */
+/*                             Include Files                                  */
+/* ========================================================================== */
+#include <stdint.h>
+#include <diag_utils.h>
+#include <sdr_ecc.h>
+
+#include "ecc_trigger_func.h"
+#include "ecc_inject.h"
+
+
+/* ========================================================================== */
+/*                           Macros & Typedefs                                */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/*                         Structure Declarations                             */
+/* ========================================================================== */
+
+/* Use case definition structure */
+typedef struct diag_ecc_use_case_s
+{
+    SDR_ECC_MemType         eccAggrId;     /* ECC Aggregator ID */
+    SDR_ECC_MemSubType      eccRamId;      /* ECC RAM ID */
+    SDR_ECC_InjectErrorType secInjErrType; /* SEC Inject Error Type */
+    uint32_t                secFlipMask;   /* SEC Error injection bitmask */
+    SDR_ECC_InjectErrorType dedInjErrType; /* DED Inject Error Type */
+    uint32_t                dedFlipMask;   /* DED Error injection bitmask */
+    SDR_ECC_RamIdType       ramIdType;     /* ECC RAM ID Type - Wrapper or Interconnect */
+    SDR_ECC_MemSubSubType   chkGrp;        /* ECC Checker Group - Only for Interconnect Type */
+    uint32_t                testAddressTrigLoc;    /* Memory location to read for event trigger.
+                                                      For accessible Wrapper types only. */
+    int32_t                 (*testTrigFunc)(void); /* Function to run for event trigger.
+                                                      For inaccessible Wrapper types only. */
+} diag_ecc_use_case_t;
+
+/* ========================================================================== */
+/*                          Function Declarations                             */
+/* ========================================================================== */
+
+static int32_t runSingleSECEvent(SDR_ECC_MemType eccAggrId,
+                                 SDR_ECC_MemSubType eccRamId,
+                                 SDR_ECC_InjectErrorType injErrType,
+                                 uint32_t flipMask,
+                                 uint32_t ramIdType,
+                                 SDR_ECC_MemSubSubType chkGrp,
+                                 uint32_t testAddressTrigLoc,
+                                 int32_t (*testTrigFunc)(void) );
+
+static int32_t runSingleDEDEvent(SDR_ECC_MemType eccAggrId,
+                                 SDR_ECC_MemSubType eccRamId,
+                                 SDR_ECC_InjectErrorType injErrType,
+                                 uint32_t flipMask,
+                                 uint32_t ramIdType,
+                                 SDR_ECC_MemSubSubType chkGrp,
+                                 uint32_t testAddressTrigLoc,
+                                 int32_t (*testTrigFunc)(void) );
+
+/* ========================================================================== */
+/*                            Global Variables                                */
+/* ========================================================================== */
+
+
+/* List all needed values/ID's for all the use cases */
+diag_ecc_use_case_t useCaseArray[6] =
+{
+    /* MCU ESM, MCU_R5FSS0_0 ECC Aggregator, Interconnect ECC Type */
+    {SDR_ECC_MEMTYPE_MCU_R5F0_CORE,                   /* eccAggrId of type SDR_ECC_MemType */
+     SDR_ECC_R5F_MEM_SUBTYPE_VBUSM2AXI_EDC_VECTOR_ID, /* RAM ID = 28 */
+     SDR_INJECT_ECC_ERROR_FORCING_1BIT_ONCE,          /* SEC Inject Error Type */
+     0x10,                                            /* secFlipMask of type uint32_t */
+     SDR_INJECT_ECC_ERROR_FORCING_2BIT_ONCE,          /* DED Inject Error Type */
+     0x101,                                           /* dedFlipMask of type uint32_t */
+     SDR_ECC_RAM_ID_TYPE_INTERCONNECT,                /* ramIdType of type SDR_ECC_RamIdType */
+     SDR_ECC_R5F_MEM_SUBSUBTYPE_VBUSM2AXI_EDC_VECTOR_INT_UNCOR_WDATA_31_0, /* EDC Group Type */
+     0x0,                                             /* testAddressTrigLoc of type uint32_t,
+                                                       * not used for Interconnect Type */
+     NULL                                             /* testTrigFunc filled in initialization function */
+    },
+    /* MCU ESM, MCU_R5FSS0_0 ECC Aggregator, Wrapper ECC Type */
+    {SDR_ECC_MEMTYPE_MCU_R5F0_CORE,                    /* eccAggrId of type SDR_ECC_MemType */
+     SDR_ECC_R5F_MEM_SUBTYPE_KS_VIM_RAM_VECTOR_ID,     /* eccRamId of type SDR_ECC_MemSubType - CSL_ECC_AGGR_MCU_R5FSS0_R5_ECC_AGGR_0_CPU0_KS_VIM_RAMECC_ID  */
+     SDR_INJECT_ECC_ERROR_FORCING_1BIT_ONCE,           /* SEC Inject Error Type */
+     0x10,                                             /* secFlipMask of type uint32_t */
+     SDR_INJECT_ECC_ERROR_FORCING_2BIT_ONCE,           /* DED Inject Error Type */
+     0x101,                                            /* dedFlipMask of type uint32_t */
+     SDR_ECC_RAM_ID_TYPE_WRAPPER,                      /* ramIdType of type SDR_ECC_RamIdType */
+     0,                                                /* Wrapper type, so no Group checker ID */
+     0x40F82004u,                                      /* testAddressTrigLoc of type uint32_t */ // TODO - BASE OFF CSLR BASE ADDRESS VALUE, FIND RIGHT VALUE
+     NULL                                              /* testTrigFunc filled in initialization function */
+    },
+    /* Main ESM, MSMC ECC Aggregator, Interconnect ECC Type */
+    {SDR_ECC_MEMTYPE_MAIN_MSMC_AGGR0,                  /* eccAggrId of type SDR_ECC_MemType */
+     SDR_ECC_MAIN_MSMC_MEM_INTERCONN_SUBTYPE,          /* eccRamId of type SDR_ECC_MemSubType *///CSL_ECC_AGGR_COMPUTE_CLUSTER0_MSMC_ES_ECC_AGGR0_RMW0_QUEUE_BUSECC_0_ID 
+     SDR_INJECT_ECC_ERROR_FORCING_1BIT_ONCE,           /* SEC Inject Error Type */
+     0x10,                                             /* secFlipMask of type uint32_t */
+     SDR_INJECT_ECC_ERROR_FORCING_2BIT_ONCE,           /* DED Inject Error Type */
+     0x101,                                            /* dedFlipMask of type uint32_t */
+     SDR_ECC_RAM_ID_TYPE_INTERCONNECT,                 /* ramIdType of type SDR_ECC_RamIdType */
+     0,                                                /* Choose Group checker ID of 0 */
+     0x0,                                              /* testAddressTrigLoc of type uint32_t,
+                                                        * not used for Interconnect Type */
+     NULL                                              /* testTrigFunc filled in initialization function */
+    },
+    /* Main ESM, MSMC ECC Aggregator, Wrapper ECC Type */
+    {SDR_ECC_MEMTYPE_MAIN_MSMC_AGGR0,                  /* eccAggrId of type SDR_ECC_MemType */
+     SDR_ECC_MAIN_MSMC_MEM_WRAPPER_SUBTYPE,            /* eccRamId of type SDR_ECC_MemSubType */ 
+     SDR_INJECT_ECC_ERROR_FORCING_1BIT_N_ROW_ONCE,     /* SEC Inject Error Type */
+     0x10,                                             /* secFlipMask of type uint32_t */
+     SDR_INJECT_ECC_ERROR_FORCING_2BIT_N_ROW_ONCE,     /* DED Inject Error Type */
+     0x101,                                            /* dedFlipMask of type uint32_t */
+     SDR_ECC_RAM_ID_TYPE_WRAPPER,                      /* ramIdType of type SDR_ECC_RamIdType */
+     0,                                                /* Wrapper type, so no Group checker ID */
+     0x0,                                              /* testAddressTrigLoc of type uint32_t,
+                                                        * not used for this inaccesible Wrapper type */
+     NULL                                              /* testTrigFunc filled in initialization function */
+    },
+    /* Multiple iterations on Main ESM, MSMC ECC Aggregator, Interconnect ECC Type */
+    {SDR_ECC_MEMTYPE_MAIN_MSMC_AGGR0,                  /* eccAggrId of type SDR_ECC_MemType */
+     SDR_ECC_MAIN_MSMC_MEM_INTERCONN_SUBTYPE,          /* eccRamId of type SDR_ECC_MemSubType */
+     SDR_INJECT_ECC_ERROR_FORCING_1BIT_ONCE,           /* SEC Inject Error Type */
+     0x10,                                             /* secFlipMask of type uint32_t */
+     SDR_INJECT_ECC_ERROR_FORCING_2BIT_ONCE,           /* DED Inject Error Type */
+     0x101,                                            /* dedFlipMask of type uint32_t */
+     SDR_ECC_RAM_ID_TYPE_INTERCONNECT,                 /* ramIdType of type SDR_ECC_RamIdType */
+     0,                                                /* Choose Group checker ID of 0 */
+     0x0,                                              /* testAddressTrigLoc of type uint32_t,
+                                                        * not used for Interconnect Type */
+     NULL                                              /* testTrigFunc filled in initialization function */
+    },
+    /* Main ESM, MSMC ECC Aggregator, Wrapper ECC Type */
+    {SDR_ECC_MEMTYPE_MAIN_MSMC_AGGR0,                  /* eccAggrId of type SDR_ECC_MemType */
+     SDR_ECC_MAIN_MSMC_MEM_WRAPPER_SUBTYPE,            /* eccRamId of type SDR_ECC_MemSubType */
+     SDR_INJECT_ECC_ERROR_FORCING_1BIT_N_ROW_ONCE,     /* SEC Inject Error Type */
+     0x10,                                             /* secFlipMask of type uint32_t */
+     SDR_INJECT_ECC_ERROR_FORCING_2BIT_N_ROW_ONCE,     /* DED Inject Error Type */
+     0x101,                                            /* dedFlipMask of type uint32_t */
+     SDR_ECC_RAM_ID_TYPE_WRAPPER,                      /* ramIdType of type SDR_ECC_RamIdType */
+     0,                                                /* Wrapper type, so no Group checker ID */
+     0x0,                                              /* testAddressTrigLoc of type uint32_t,
+                                                        * not used for this inaccessible Wrapper type */
+     NULL                                              /* testTrigFunc filled in initialization function */
+    },
+};
+
+/* ========================================================================== */
+/*                            External Variables                              */
+/* ========================================================================== */
+
+extern volatile uint32_t gEsmEventRcvdFlag;
+
+extern volatile uint32_t eccEventInputTrig[6];
+
+extern int32_t (*useCaseTriggerFuncArray[6])();
+
+/* ========================================================================== */
+/*                          Function Definitions                              */
+/* ========================================================================== */
+
+/*********************************************************************
+ * @fn      runSingleSECEvent
+ *
+ * @brief   Execute ECC 1 bit inject test
+ *
+ * @param   eccAggrId - ID of the ECC Aggregator
+ * @param   eccRamId - RAM ID into which the error will be injected
+ * @param   injErrType - inject error type
+ * @param   flipMask - bit mask that indicates what bit to inject the error
+ * @param   ramIdType - type of RAM ID (either Wrapper or Interconnect Type)
+ * @param   chkGrp - check group ID (only valid for Interconnect Type, otherwise set to 0)
+ * @param   testAddressTrigLoc - memory address that needs to be read to trigger
+ *                               SEC event.
+ * @param   testTrigFunc - function that needs to be run to trigger SEC event.
+ *                         It is expected that only testAddressTrigLoc or testTrigFunc
+ *                         is needed for each use case (and cannot be both).
+ *
+ * @return  0 : Success; < 0 for failures
+ */
+static int32_t runSingleSECEvent(SDR_ECC_MemType eccAggrId,
+                                 SDR_ECC_MemSubType eccRamId,
+                                 SDR_ECC_InjectErrorType injErrType,
+                                 uint32_t flipMask,
+                                 uint32_t ramIdType,
+                                 SDR_ECC_MemSubSubType chkGrp, 
+                                 uint32_t testAddressTrigLoc,
+                                 int32_t (*testTrigFunc)(void) )
+{
+    SDR_Result result;
+    int32_t retVal=0;
+
+    SDR_ECC_InjectErrorConfig_t injectErrorConfig;
+    volatile uint32_t testLocationValue;
+#ifdef DEBUG_PRINT
+    DIAG_printf("\n Single bit error inject: test starting for eccAggr %d, eccRamId %d, " \
+                "flipMask 0x%x, ramIdType %d, testAddressTrigLoc = 0x%x\n",
+                 eccAggrId, eccRamId, flipMask, ramIdType, testAddressTrigLoc);    
+#endif
+    /* Note the address is Actual error address */
+    injectErrorConfig.pErrMem = (uint32_t *)(testAddressTrigLoc);
+
+    /* Run one shot test for 1 bit error */
+    injectErrorConfig.flipBitMask = flipMask;
+    injectErrorConfig.chkGrp      = chkGrp;
+
+    result = SDR_ECC_injectError(eccAggrId,
+                                 eccRamId,
+                                 injErrType,
+                                 &injectErrorConfig);
+    if (result != SDR_PASS ) {
+        DIAG_printf("\n Single bit error inject at pErrMem 0x%p test failed",
+                    injectErrorConfig.pErrMem);
+        retVal = -1;
+    } else {
+        if (testAddressTrigLoc != 0) {
+            /* Access the memory where injection is expected */
+            testLocationValue = injectErrorConfig.pErrMem[0];
+        } else if (testTrigFunc != NULL) {
+            /* Call function to trigger error */
+            retVal = (*testTrigFunc)();
+            if (retVal != 0) {
+                DIAG_printf("\n Single bit error inject: testTrigFunc call failed");
+            }
+        }
+
+#ifdef DEBUG_PRINT
+        /* Note this should result in actual error call back */
+        DIAG_printf("\n Single bit error inject at pErrMem 0x%p: test complete",
+                    injectErrorConfig.pErrMem);
+#endif
+    }
+
+    return retVal;
+} 
+
+/*********************************************************************
+ * @fn      runSingleDEDEvent
+ *
+ * @brief   Execute ECC 2 bit inject test
+ *
+ * @param   eccAggrId - ID of the ECC Aggregator
+ * @param   eccRamId - RAM ID into which the error will be injected
+ * @param   injErrType - inject error type
+ * @param   flipMask - bit mask that indicates what bit to inject the error
+ * @param   ramIdType - type of RAM ID (either Wrapper or Interconnect Type)
+ * @param   chkGrp - check group ID (only valid for Interconnect Type, otherwise set to 0)
+ * @param   testAddressTrigLoc - memory address that needs to be read to trigger
+ *                               SEC event.
+ * @param   testTrigFunc - function that needs to be run to trigger SEC event.
+ *                         It is expected that only testAddressTrigLoc or testTrigFunc
+ *                         is needed for each use case (and cannot be both).
+ *
+ * @return  0 : Success; < 0 for failures
+ */
+static int32_t runSingleDEDEvent(SDR_ECC_MemType eccAggrId,
+                                 SDR_ECC_MemSubType eccRamId,
+                                 SDR_ECC_InjectErrorType injErrType,
+                                 uint32_t flipMask, 
+                                 uint32_t ramIdType,
+                                 SDR_ECC_MemSubSubType chkGrp, 
+                                 uint32_t testAddressTrigLoc,
+                                 int32_t (*testTrigFunc)(void) )
+{
+    SDR_Result result;
+    int32_t retVal=0;
+
+    SDR_ECC_InjectErrorConfig_t injectErrorConfig;
+    volatile uint32_t testLocationValue;
+#ifdef DEBUG_PRINT
+    DIAG_printf("\n Double bit error inject: test starting for eccAggr %d, eccRamId %d, " \
+                "flipMask 0x%x, ramIdType %d, testAddressTrigLoc = 0x%x\n",
+                 eccAggrId, eccRamId, flipMask, ramIdType, testAddressTrigLoc);    
+#endif
+    /* Note the address is Actual error address */
+    injectErrorConfig.pErrMem = (uint32_t *)(testAddressTrigLoc);
+
+    /* Run one shot test for 2 bit error */
+    injectErrorConfig.flipBitMask = flipMask;
+    injectErrorConfig.chkGrp      = chkGrp;
+
+    result = SDR_ECC_injectError(eccAggrId,
+                                 eccRamId,
+                                 injErrType,
+                                 &injectErrorConfig);
+
+    if (result != SDR_PASS ) {
+        DIAG_printf("\n Double bit error inject at pErrMem 0x%p test failed",
+                    injectErrorConfig.pErrMem);
+        retVal = -1;
+    } else {
+        if (testAddressTrigLoc != 0) {
+            /* Access the memory where injection is expected */
+            testLocationValue = injectErrorConfig.pErrMem[0];
+        } else if (testTrigFunc != NULL) {
+            retVal = (*testTrigFunc)();
+            if (retVal != 0) {
+                DIAG_printf("\n Double bit error inject: testTrigFunc call failed");
+            }
+        }
+#ifdef DEBUG_PRINT
+        /* Note this should result in actual error call back */
+        DIAG_printf("\n Double bit error inject at pErrMem 0x%p: test complete",
+                    injectErrorConfig.pErrMem);
+#endif
+    }
+
+    return retVal;
+} 
+
+
+/*********************************************************************
+ * @fn      diag_ecc_initUseCases
+ *
+ * @brief   Perform any remaining initialization of the use cases
+ *          based on SoC-specific definitions
+ *
+ * @return  0 : Success; < 0 for failures
+ */
+int32_t diag_ecc_initUseCases(void)
+{
+    int8_t i;
+    int32_t retValue;
+
+    /* Populate the Use Cases with any SoC-specific testTrigFunc */
+    for (i = 0; i < 6; i++) {
+        useCaseArray[i].testTrigFunc = useCaseTriggerFuncArray[i];
+    }
+
+    retValue = eventTriggerSetup();
+
+    return (retValue);
+}
+
+/*********************************************************************
+ * @fn      diag_ecc_runUseCaseTrigger
+ *
+ * @brief   Initiate the input trigger event(s) for each use case
+ *
+ * @param   useCaseId - use case instance for which trigger event(s)
+ *          should be initiated
+ *
+ * @return  0 : Success; < 0 for failures
+ */
+int32_t diag_ecc_runUseCaseTrigger(uint8_t useCaseId)
+{
+    int32_t retVal1, retVal2, numMultiSecEvents, numMultiDedEvents, i;
+    int32_t status = 0;
+
+    DIAG_printf("\nStarting Use Case %d \n", useCaseId);
+    switch(useCaseId)
+    {
+        case 0:
+            /* UC-1: Single SEC/DED events on MCU_ESM0 with Interconnect ECC type */
+        case 1:
+            /* UC-2: Single SEC/DED events on MCU_ESM0 with Wrapper ECC type */
+        case 2:
+            /* UC-3: Single SEC/DED events on Main Domain ESM0 with Interconnect ECC type */
+        case 3:
+            /* UC-4: Single SEC/DED events on Main Domain ESM0 with Wrapper ECC type. */
+            gEsmEventRcvdFlag = ESM_EVENT_NOT_RCVD;
+
+            /* Trigger a single SEC event */
+            retVal1 = runSingleSECEvent(useCaseArray[useCaseId].eccAggrId,
+                                        useCaseArray[useCaseId].eccRamId,
+                                        useCaseArray[useCaseId].secInjErrType,
+                                        useCaseArray[useCaseId].secFlipMask,
+                                        useCaseArray[useCaseId].ramIdType,
+                                        useCaseArray[useCaseId].chkGrp,
+                                        useCaseArray[useCaseId].testAddressTrigLoc,
+                                        useCaseArray[useCaseId].testTrigFunc);
+
+            /* Wait for the ESM event to complete */
+            while(gEsmEventRcvdFlag == ESM_EVENT_NOT_RCVD) {}
+
+            /* Trigger a single DED event */
+            retVal2 = runSingleDEDEvent(useCaseArray[useCaseId].eccAggrId,
+                                        useCaseArray[useCaseId].eccRamId,
+                                        useCaseArray[useCaseId].dedInjErrType,
+                                        useCaseArray[useCaseId].dedFlipMask,
+                                        useCaseArray[useCaseId].ramIdType,
+                                        useCaseArray[useCaseId].chkGrp,
+                                        useCaseArray[useCaseId].testAddressTrigLoc,
+                                        useCaseArray[useCaseId].testTrigFunc);
+
+            if ((retVal1 == 0) && (retVal2 == 0)) {
+                eccEventInputTrig[useCaseId] = USE_CASE_STATUS_COMPLETED_SUCCESS;
+            } else {
+                eccEventInputTrig[useCaseId] = USE_CASE_STATUS_COMPLETED_FAILURE;
+            }
+            break;
+
+        case 4:
+            /* UC-5: Multiple SEC and DED events on Main Domain ESM0 with Interconnect ECC type */
+        case 5:
+            /* UC-6: Multiple SEC and DED events on Main Domain ESM0 with Wrapper ECC type */
+            numMultiSecEvents = 0;
+            numMultiDedEvents = 0;
+            for (i = 0; i < NUM_MULTIPLE_SEC_EVENTS; i++)
+            {
+                gEsmEventRcvdFlag = ESM_EVENT_NOT_RCVD;
+                /* Trigger a single SEC event */
+                retVal1 = runSingleSECEvent(useCaseArray[useCaseId].eccAggrId,
+                                            useCaseArray[useCaseId].eccRamId,
+                                            useCaseArray[useCaseId].secInjErrType,
+                                            useCaseArray[useCaseId].secFlipMask,
+                                            useCaseArray[useCaseId].ramIdType,
+                                            useCaseArray[useCaseId].chkGrp,
+                                            useCaseArray[useCaseId].testAddressTrigLoc,
+                                            useCaseArray[useCaseId].testTrigFunc);
+
+                /* Wait for the ESM event to complete */
+                while(gEsmEventRcvdFlag == ESM_EVENT_NOT_RCVD) {}
+
+                if (retVal1 != 0) {
+                    break;
+                } else {
+                    numMultiSecEvents++;
+                }
+            }
+
+            for (i = 0; i < NUM_MULTIPLE_DED_EVENTS; i++)
+            {
+                gEsmEventRcvdFlag = ESM_EVENT_NOT_RCVD;
+                /* Trigger a single DED event */
+                retVal2 = runSingleDEDEvent(useCaseArray[useCaseId].eccAggrId,
+                                            useCaseArray[useCaseId].eccRamId,
+                                            useCaseArray[useCaseId].dedInjErrType,
+                                            useCaseArray[useCaseId].dedFlipMask,
+                                            useCaseArray[useCaseId].ramIdType,
+                                            useCaseArray[useCaseId].chkGrp,
+                                            useCaseArray[useCaseId].testAddressTrigLoc,
+                                            useCaseArray[useCaseId].testTrigFunc);
+
+                /* Wait for the ESM event to complete */
+                while(gEsmEventRcvdFlag == ESM_EVENT_NOT_RCVD) {}
+
+                if (retVal2 != 0) {
+                    break;
+                } else {
+                    numMultiDedEvents++;
+                }
+            }
+
+            if ((retVal1 == 0) && (numMultiSecEvents == NUM_MULTIPLE_SEC_EVENTS) &&
+                (retVal2 == 0) && (numMultiDedEvents == NUM_MULTIPLE_DED_EVENTS)) {
+                eccEventInputTrig[useCaseId] = USE_CASE_STATUS_COMPLETED_SUCCESS;
+            } else {
+                eccEventInputTrig[useCaseId] = USE_CASE_STATUS_COMPLETED_FAILURE;
+            }
+            break;
+
+        default:
+            DIAG_printf("ERR: Invalid Use Case ID %d \n", useCaseId);
+            status = -1;
+            break;
+    }
+
+    return (status);
+}
+
diff --git a/packages/ti/diag/examples/ecc_example_app/ecc_inject.h b/packages/ti/diag/examples/ecc_example_app/ecc_inject.h
new file mode 100644 (file)
index 0000000..82e3eac
--- /dev/null
@@ -0,0 +1,57 @@
+/*
+ * ECC Example
+ *
+ * Error Correcting Code (ECC) Example Application
+ *
+ *  Copyright (c) 2020 Texas Instruments Incorporated
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef INCLUDE_ECC_INJECT_H_
+#define INCLUDE_ECC_INJECT_H_
+
+/*===========================================================================*/
+/*                         Internal function declarations                    */
+/*===========================================================================*/
+
+int32_t eventTriggerSetup(void);
+int32_t diag_ecc_initUseCases(void);
+int32_t diag_ecc_runUseCaseTrigger(uint8_t useCaseId);
+
+#define NUM_MULTIPLE_SEC_EVENTS 10
+#define NUM_MULTIPLE_DED_EVENTS 10
+
+#define USE_CASE_STATUS_NOT_RUN           (0u)
+#define USE_CASE_STATUS_COMPLETED_SUCCESS (1u)
+#define USE_CASE_STATUS_COMPLETED_FAILURE (2u)
+
+#define ESM_EVENT_NOT_RCVD (0u)
+#define ESM_EVENT_RCVD     (1u)
+
+#endif /*  INCLUDE_ECC_INJECT_H_ */
diff --git a/packages/ti/diag/examples/ecc_example_app/esm.c b/packages/ti/diag/examples/ecc_example_app/esm.c
new file mode 100644 (file)
index 0000000..d3707a4
--- /dev/null
@@ -0,0 +1,958 @@
+/*
+ * ECC Example
+ *
+ * Error Correcting Code (ECC) Example Application
+ *
+ *  Copyright (c) 2020 Texas Instruments Incorporated
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/**
+ *  \file esm.c
+ *
+ *  \brief ESM utility functions and handler ISR's for ESM and ECC
+ */
+
+/* ========================================================================== */
+/*                             Include Files                                  */
+/* ========================================================================== */
+
+#include <stdio.h>
+#include <stdint.h>
+/* For Timer functions */
+#include <ti/osal/osal.h>
+
+/* For interrupt ID numbers */
+#include <ti/csl/soc/cslr_soc_intr.h>
+#include <ti/csl/csl_ecc_aggr.h>
+
+/* Diagnostic example utility functions, e.g. print outputs */
+#include <diag_utils.h>
+#include <sdr_esm.h>
+#include <sdr_ecc.h>
+
+#include "esm.h"
+#include "ecc_inject.h"
+
+/* ========================================================================== */
+/*                           Macros & Typedefs                                */
+/* ========================================================================== */
+
+#define SINGLE_SEC_DED_EVENT_USE_CASES 4
+
+#define MAX_ESM_EVENTS_LOGGED (50)
+#define MAX_ESM_INSTANCE      (SDR_ESM_INSTANCE_MAIN)
+#define MAX_ESM_INT_TYPE      (SDR_ESM_INT_TYPE_CFG)
+
+#define MAX_MEM_MSMC_SECTIONS (2u)
+#define MAX_MEM_R5F_SECTIONS  (9u)
+
+/* ESM event log entry */
+typedef struct
+{
+    /* Type of ECC Error Received
+     * Possible values are SDR_INJECT_ECC_ERROR_FORCING_1BIT_ONCE = 1, or
+     * SDR_INJECT_ECC_ERROR_FORCING_2BIT_ONCE = 2 */
+    uint32_t             errorSrc;
+    uint32_t             address;
+    /* Ram ID for the memory where the error occurred */
+    uint32_t             ramId;
+    /* Offset into the Ram ID where the error occurred */
+    uint64_t             bitErrorOffset;
+    uint32_t             bitErrorGroup;
+    uint8_t              useCaseNum;
+} ECC_Example_log_entry_t;
+
+/* ========================================================================== */
+/*                         Structure Declarations                             */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/*                          Function Declarations                             */
+/* ========================================================================== */
+
+static int32_t ECC_Example_EsmInitHandlerInit(SDR_ESM_InstanceType esmInstType);
+
+static const char *printEccErrorType(SDR_ECC_InjectErrorType eccErrorType);
+static int32_t checkUseCaseStructs(uint8_t actualLogSlot, uint8_t expectedLogSlot);
+static int32_t checkUseCaseOutputs(uint8_t useCaseNum);
+
+/* ========================================================================== */
+/*                            Global Variables                                */
+/* ========================================================================== */
+
+volatile uint32_t gEsmEventRcvdFlag = ESM_EVENT_NOT_RCVD;
+
+static volatile ECC_Example_log_entry_t eccEventLog[MAX_ESM_EVENTS_LOGGED];
+static volatile uint32_t totalEccEventsLogged              = 0;
+static volatile uint32_t totalEccEventsPerUseCase[6]       = {0, 0, 0, 0, 0, 0};
+static volatile uint32_t totalExpectedEccEvtsPerUseCase[6] = {2, 2, 2, 2, 20, 20};
+
+
+static ECC_Example_log_entry_t expectedEccEventLog[MAX_ESM_EVENTS_LOGGED] =
+{
+    {CSL_ECC_AGGR_INTR_SRC_SINGLE_BIT,                /* errorSrc */
+     SDR_ESM_ERRORADDR_INVALID,                       /* address */
+     SDR_ECC_R5F_MEM_SUBTYPE_VBUSM2AXI_EDC_VECTOR_ID, /* ramId */
+     0x0000000000000004,                              /* bitErrorOffset */
+     21,                                              /* bitErrorGroup */
+     0                                                /* useCaseNum */
+    },
+    {CSL_ECC_AGGR_INTR_SRC_DOUBLE_BIT,                /* errorSrc */
+     SDR_ESM_ERRORADDR_INVALID,                       /* address */
+     SDR_ECC_R5F_MEM_SUBTYPE_VBUSM2AXI_EDC_VECTOR_ID, /* ramId */
+     0x0000000000000000,                              /* bitErrorOffset */
+     21,                                              /* bitErrorGroup */
+     0                                                /* useCaseNum */
+    },
+    {CSL_ECC_AGGR_INTR_SRC_SINGLE_BIT,                /* errorSrc */
+     SDR_ESM_ERRORADDR_INVALID,                       /* address */
+     SDR_ECC_R5F_MEM_SUBTYPE_KS_VIM_RAM_VECTOR_ID,    /* ramId */
+     0x0000000000000024,                              /* bitErrorOffset */
+     0,                                               /* bitErrorGroup */
+     1                                                /* useCaseNum */
+    },
+    {CSL_ECC_AGGR_INTR_SRC_DOUBLE_BIT,                /* errorSrc */
+     SDR_ESM_ERRORADDR_INVALID,                       /* address */
+     SDR_ECC_R5F_MEM_SUBTYPE_KS_VIM_RAM_VECTOR_ID,    /* ramId */
+     0x0000000000000020,                              /* bitErrorOffset */
+     0,                                               /* bitErrorGroup */
+     1                                                /* useCaseNum */
+    },
+    {CSL_ECC_AGGR_INTR_SRC_SINGLE_BIT,                /* errorSrc */
+     SDR_ESM_ERRORADDR_INVALID,                       /* address */
+     SDR_ECC_MAIN_MSMC_MEM_INTERCONN_SUBTYPE,         /* ramId */
+     0x0000000000000004,                              /* bitErrorOffset */
+     0,                                               /* bitErrorGroup */
+     2                                                /* useCaseNum */
+    },
+    {CSL_ECC_AGGR_INTR_SRC_DOUBLE_BIT,                /* errorSrc */
+     SDR_ESM_ERRORADDR_INVALID,                       /* address */
+     SDR_ECC_MAIN_MSMC_MEM_INTERCONN_SUBTYPE,         /* ramId */
+     0x0000000000000000,                              /* bitErrorOffset */
+     0,                                               /* bitErrorGroup */
+     2                                                /* useCaseNum */
+    },
+    {CSL_ECC_AGGR_INTR_SRC_SINGLE_BIT,                /* errorSrc */
+     SDR_ESM_ERRORADDR_INVALID,                       /* address */
+     SDR_ECC_MAIN_MSMC_MEM_WRAPPER_SUBTYPE,           /* ramId */
+     0x000000000000010c,                              /* bitErrorOffset - Note that
+                                                       * this value can vary, so it is
+                                                       * not checked */
+     0,                                               /* bitErrorGroup */
+     3                                                /* useCaseNum */
+    },
+    {CSL_ECC_AGGR_INTR_SRC_DOUBLE_BIT,                /* errorSrc */
+     SDR_ESM_ERRORADDR_INVALID,                       /* address */
+     SDR_ECC_MAIN_MSMC_MEM_WRAPPER_SUBTYPE,           /* ramId */
+     0x0000000000000108,                              /* bitErrorOffset - Note that
+                                                       * this value can vary, so it is
+                                                       * not checked */
+     0,                                               /* bitErrorGroup */
+     3                                                /* useCaseNum */
+    },
+    /* Multiple SEC events consecutively - the following entry should occur
+     * NUM_MULTIPLE_SEC_EVENTS times */
+    {CSL_ECC_AGGR_INTR_SRC_SINGLE_BIT,                /* errorSrc */
+     SDR_ESM_ERRORADDR_INVALID,                       /* address */
+     SDR_ECC_MAIN_MSMC_MEM_INTERCONN_SUBTYPE,         /* ramId */
+     0x0000000000000004,                              /* bitErrorOffset */
+     0,                                               /* bitErrorGroup */
+     4                                                /* useCaseNum */
+    },
+    /* Multiple DED events consecutively - the following entry should occur
+     * NUM_MULTIPLE_DED_EVENTS times */
+    {CSL_ECC_AGGR_INTR_SRC_DOUBLE_BIT,                /* errorSrc */
+     SDR_ESM_ERRORADDR_INVALID,                       /* address */
+     SDR_ECC_MAIN_MSMC_MEM_INTERCONN_SUBTYPE,         /* ramId */
+     0x0000000000000000,                              /* bitErrorOffset */
+     0,                                               /* bitErrorGroup */
+     4                                                /* useCaseNum */
+    },
+    /* Multiple SEC events consecutively - the following entry should occur
+     * NUM_MULTIPLE_SEC_EVENTS times */
+    {CSL_ECC_AGGR_INTR_SRC_SINGLE_BIT,                /* errorSrc */
+     SDR_ESM_ERRORADDR_INVALID,                       /* address */
+     SDR_ECC_MAIN_MSMC_MEM_WRAPPER_SUBTYPE,           /* ramId */
+     0x000000000000010c,                              /* bitErrorOffset - Note that
+                                                       * this value can vary, so it is
+                                                       * not checked */
+     0,                                               /* bitErrorGroup */
+     5                                                /* useCaseNum */
+    },
+    /* Multiple DED events consecutively - the following entry should occur
+     * NUM_MULTIPLE_DED_EVENTS times */
+    {CSL_ECC_AGGR_INTR_SRC_DOUBLE_BIT,                /* errorSrc */
+     SDR_ESM_ERRORADDR_INVALID,                       /* address */
+     SDR_ECC_MAIN_MSMC_MEM_WRAPPER_SUBTYPE,           /* ramId */
+     0x0000000000000108,                              /* bitErrorOffset - Note that
+                                                       * this value can vary, so it is
+                                                       * not checked */
+     0,                                               /* bitErrorGroup */
+     5                                                /* useCaseNum */
+    },
+};
+
+/* Initialization structure for MCU ESM instance */
+static SDR_ESM_InitConfig_t ECC_Example_esmInitConfig_MCU =
+{
+    .esmErrorConfig = {0u, 3u}, /* Self test error config */
+    .eventMap = {0xffffffffu, 0x033fffffu, 0x7fffffffu, 0xffffffe7u,
+                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                },
+     /**< All events enable: except timer and self test  events, */
+    /*    and Main ESM output.  Disabling vim compare error as well.
+     *    Exclude MCU Timer 0, which is left on by SBL in continuous mode.
+     *    Ensure inclusion of the following ESM events that will be used in the
+     *    example application:
+     *    MCU_R5FSS0_CORE0_ECC_CORRECTED_LEVEL_0 interrupt to MCU_ESM0_LVL_IN_32
+     *    MCU_R5FSS0_CORE0_ECC_UNCORRECTED_LEVEL_0 interrupt to MCU_ESM0_LVL_IN_33
+     */
+    .eventPriorityMap = {0xffffffffu, 0x033ffffeu, 0x7fffffffu, 0xffffffe7u,
+                         0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                         0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                         0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                         0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                         0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                         0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                         0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                        },
+    /**< All events high priority: except timer, selftest error events,
+     *   and Main ESM output. Exclude MCU Timer 0, which is left on by
+     *   SBL in continuous mode.
+     *   MCU_R5FSS0_CORE0_ECC_CORRECTED_LEVEL_0 interrupt to MCU_ESM0_LVL_IN_32 set
+     *   to Low Priority.
+     *   MCU_R5FSS0_CORE0_ECC_UNCORRECTED_LEVEL_0 interrupt to MCU_ESM0_LVL_IN_33 set
+     *   to High Priority.
+     */
+    .errorOutputMap = {0xffffffffu, 0x033ffffeu, 0x7fffffffu, 0xffffffe7u,
+                       0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                       0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                       0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                       0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                       0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                       0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                       0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                      },
+    /**< All events high priority: except timer, selftest error events,
+     *   and Main ESM output. Exclude MCU Timer 0, which is left on by
+     *   SBL in continuous mode, and MCU Timer 1, which is used for controlling
+     *   the Output pin clearing.
+     *   MCU_R5FSS0_CORE0_ECC_CORRECTED_LEVEL_0 interrupt to MCU_ESM0_LVL_IN_32 set
+     *   to Low Priority with no Output pin routing.
+     *   MCU_R5FSS0_CORE0_ECC_UNCORRECTED_LEVEL_0 interrupt to MCU_ESM0_LVL_IN_33 set
+     *   to High Priority with Output pin routing.
+     */
+};
+
+/* Initialization structure for Main ESM instance */
+static SDR_ESM_InitConfig_t ECC_Example_esmInitConfig_MAIN =
+{
+    .esmErrorConfig = {1u, 8u}, /* Self test error config */
+    .eventMap = {0x00000000u, 0xfffffffbu, 0x7fffffffu, 0xffffffffu,
+                 0xffffffffu, 0xffffffffu, 0xffffffffu, 0xffffffffu,
+                 0xffffffffu, 0xffffffffu, 0xffffffffu, 0xffffffffu,
+                 0xffffffffu, 0xffffffffu, 0xffffffffu, 0x00000000u,
+                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                 0xffffffffu, 0x00000000u, 0x00000000u, 0x00000000u,
+                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                 0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                },
+     /**< All events enable: except clkstop events for unused clocks
+      *   and PCIE events.
+      *   This example enables the following Main ESM input events that are
+      *   enabled here:
+      *   COMPUTE_CLUSTER0_CLEC_ESM_EVENTS_OUT_LEVEL_0 (MSMC Uncorrected DED ECC error)
+      *   interrupt to ESM0_LVL_IN_48.
+      *   COMPUTE_CLUSTER0_CLEC_ESM_EVENTS_OUT_LEVEL_1 (MSMC Corrected SEC ECC error)
+      *   interrupt to ESM0_LVL_IN_49.
+      *   COMPUTE_CLUSTER0_CLEC_ESM_EVENTS_OUT_LEVEL_7 (A72 Uncorrected DED ECC error)
+      *   interrupt to ESM0_LVL_IN_55.
+      *   COMPUTE_CLUSTER0_CLEC_ESM_EVENTS_OUT_LEVEL_8 (A72 Corrected SEC ECC error)
+      *   interrupt to ESM0_LVL_IN_56.
+      */
+    .eventPriorityMap = {0x00000000u, 0xffedfffbu, 0x7fffffffu, 0xffffffffu,
+                         0xffffffffu, 0xffffffffu, 0xffffffffu, 0xffffffffu,
+                         0xffffffffu, 0xffffffffu, 0xffffffffu, 0xffffffffu,
+                         0xffffffffu, 0xffffffffu, 0xffffffffu, 0x00000000u,
+                         0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                         0xffffffffu, 0x00000000u, 0x00000000u, 0x00000000u,
+                         0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                         0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                        },
+    /**< All events high priority: except clkstop events for unused clocks
+     *   and PCIE events.
+     *   This example sets the following Main ESM input events as high
+     *   priority events:
+     *   COMPUTE_CLUSTER0_CLEC_ESM_EVENTS_OUT_LEVEL_0 (MSMC Uncorrected DED ECC error)
+     *   interrupt to ESM0_LVL_IN_48.
+     *   COMPUTE_CLUSTER0_CLEC_ESM_EVENTS_OUT_LEVEL_7 (A72 Uncorrected DED ECC error)
+     *   interrupt to ESM0_LVL_IN_55.
+     *   This example sets the following Main ESM input events as low
+     *   priority events:
+     *   COMPUTE_CLUSTER0_CLEC_ESM_EVENTS_OUT_LEVEL_1 (MSMC Corrected SEC ECC error)
+     *   interrupt to ESM0_LVL_IN_49.
+     *   COMPUTE_CLUSTER0_CLEC_ESM_EVENTS_OUT_LEVEL_8 (A72 Corrected SEC ECC error)
+     *   interrupt to ESM0_LVL_IN_56.
+     */
+    .errorOutputMap = {0x00000000u, 0xffedfffbu, 0x7fffffffu, 0xffffffffu,
+                       0xffffffffu, 0xffffffffu, 0xffffffffu, 0xffffffffu,
+                       0xffffffffu, 0xffffffffu, 0xffffffffu, 0xffffffffu,
+                       0xffffffffu, 0xffffffffu, 0xffffffffu, 0x00000000u,
+                       0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                       0xffffffffu, 0x00000000u, 0x00000000u, 0x00000000u,
+                       0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                       0x00000000u, 0x00000000u, 0x00000000u, 0x00000000u,
+                      },
+    /**< All events high priority: except clkstop for unused clocks
+     *   and PCIE events
+     *   This example sets the following Main ESM input events as high
+     *   priority events with Output Pin routing:
+     *   COMPUTE_CLUSTER0_CLEC_ESM_EVENTS_OUT_LEVEL_0 (MSMC Uncorrected DED ECC error)
+     *   interrupt to ESM0_LVL_IN_48.
+     *   COMPUTE_CLUSTER0_CLEC_ESM_EVENTS_OUT_LEVEL_7 (A72 Uncorrected DED ECC error)
+     *   interrupt to ESM0_LVL_IN_55.
+     *   This example sets the following Main ESM input events as low
+     *   priority events with no Output Pin routing:
+     *   COMPUTE_CLUSTER0_CLEC_ESM_EVENTS_OUT_LEVEL_1 (MSMC Corrected SEC ECC error)
+     *   interrupt to ESM0_LVL_IN_49.
+     *   COMPUTE_CLUSTER0_CLEC_ESM_EVENTS_OUT_LEVEL_8 (A72 Corrected SEC ECC error)
+     *   interrupt to ESM0_LVL_IN_56.
+     *   */
+};
+
+static SDR_ECC_MemSubType ECC_Example_R5FCoresubMemTypeList[MAX_MEM_R5F_SECTIONS] =
+{
+    SDR_ECC_R5F_MEM_SUBTYPE_ATCM0_BANK0_VECTOR_ID,
+    SDR_ECC_R5F_MEM_SUBTYPE_ATCM0_BANK1_VECTOR_ID,
+    SDR_ECC_R5F_MEM_SUBTYPE_KS_VIM_RAM_VECTOR_ID,
+    SDR_ECC_R5F_MEM_SUBTYPE_B0TCM0_BANK0_VECTOR_ID,
+    SDR_ECC_R5F_MEM_SUBTYPE_B0TCM0_BANK1_VECTOR_ID,
+    SDR_ECC_R5F_MEM_SUBTYPE_B1TCM0_BANK0_VECTOR_ID,
+    SDR_ECC_R5F_MEM_SUBTYPE_B1TCM0_BANK1_VECTOR_ID,
+    SDR_ECC_R5F_MEM_SUBTYPE_VBUSM2AXI_EDC_VECTOR_ID,
+    SDR_ECC_R5F_MEM_SUBTYPE_AXI2VBUSM_MEM_MST_WRITE_EDC_VECTOR_ID
+};
+
+static SDR_ECC_InitConfig_t ECC_Example_R5FCoreECCInitConfig =
+{
+    .numRams = MAX_MEM_R5F_SECTIONS,
+    /**< Number of Rams ECC is enabled  */
+    .pMemSubTypeList = &(ECC_Example_R5FCoresubMemTypeList[0]),
+    /**< Sub type list  */
+};
+
+
+static SDR_ECC_MemSubType ECC_Example_MSMCsubMemTypeList[MAX_MEM_MSMC_SECTIONS] =
+{
+    SDR_ECC_MAIN_MSMC_MEM_INTERCONN_SUBTYPE,
+    SDR_ECC_MAIN_MSMC_MEM_WRAPPER_SUBTYPE
+};
+
+static SDR_ECC_InitConfig_t ECC_Example_MSMCMemECCInitConfig =
+{
+    .numRams = MAX_MEM_MSMC_SECTIONS,
+    /**< Number of Rams ECC is enabled  */
+    .pMemSubTypeList = &(ECC_Example_MSMCsubMemTypeList[0]),
+    /**< Sub type list  */
+};
+
+static HwiP_Handle ECC_Example_EsmHiHwiPHandle;
+static HwiP_Handle ECC_Example_EsmLoHwiPHandle;
+static HwiP_Handle ECC_Example_EsmCfgHwiPHandle;
+
+/* ========================================================================== */
+/*                            External Variables                              */
+/* ========================================================================== */
+
+/* Completion of Use Case from ESM Handler perspective updates these flags */
+extern volatile uint32_t eccOutputResult[6];
+/* Current use case being run */
+extern volatile uint8_t  currUseCase;
+
+/* ========================================================================== */
+/*                          Function Definitions                              */
+/* ========================================================================== */
+
+void SDR_ECC_applicationCallbackFunction(uint32_t errorSrc,
+                                         uint32_t address,
+                                         uint32_t ramId,
+                                         uint64_t bitErrorOffset,
+                                         uint32_t bitErrorGroup){
+
+    int32_t useCaseCheck;
+
+#ifdef PRINT_EVENTS
+    DIAG_printf("\n  ECC Error Call back function called : errorSrc 0x%x, address 0x%x, " \
+                "ramId %d, bitErrorOffset 0x%08x%08x, bitErrorGroup %d\n",
+                errorSrc, address, ramId, (uint32_t)(bitErrorOffset >> 32),
+                (uint32_t)(bitErrorOffset & 0x00000000FFFFFFFF), bitErrorGroup);
+    DIAG_printf("  Take action \n");
+#endif
+
+    /* Log the event */
+    eccEventLog[totalEccEventsLogged].useCaseNum     = currUseCase;
+    eccEventLog[totalEccEventsLogged].errorSrc       = errorSrc;
+    eccEventLog[totalEccEventsLogged].address        = address;
+    eccEventLog[totalEccEventsLogged].ramId          = ramId;
+    eccEventLog[totalEccEventsLogged].bitErrorOffset = bitErrorOffset;
+    eccEventLog[totalEccEventsLogged].bitErrorGroup  = bitErrorGroup;
+
+    gEsmEventRcvdFlag = ESM_EVENT_RCVD;
+
+    totalEccEventsLogged++;
+    totalEccEventsPerUseCase[currUseCase]++;
+
+    if (totalEccEventsPerUseCase[currUseCase] ==
+        totalExpectedEccEvtsPerUseCase[currUseCase])
+    {
+        /* Check all the events from this use case*/
+        useCaseCheck = checkUseCaseOutputs(currUseCase);
+        if (useCaseCheck == 0) {
+            eccOutputResult[currUseCase] = USE_CASE_STATUS_COMPLETED_SUCCESS;
+        } else {
+            eccOutputResult[currUseCase] = USE_CASE_STATUS_COMPLETED_FAILURE;
+        }
+    }
+    /* Any additional customer specific actions can be added here */
+
+}
+
+/*********************************************************************
+* @fn      ECC_Example_esmInit
+*
+* @brief   Initializes ESM instances and ECC instances
+*
+* @param   None
+*
+* @return    0 : Success; < 0 for failures
+*/
+int32_t ECC_Example_esmInit (void)
+{
+    int32_t retValue=0;
+    SDR_Result result;
+
+#ifdef UART_PRINTF
+    /* Initialize UART instance */
+    DIAG_uartStdioInit();
+#endif
+
+    DIAG_printf("\nECC_Example_esmInit: UART ready to print, proceeding with ESM init \n");
+
+    if (retValue == 0) {
+        /* Initialize MCU ESM module */
+        result = SDR_ESM_init(SDR_ESM_INSTANCE_MCU, &ECC_Example_esmInitConfig_MCU);
+        if (result != SDR_PASS) {
+            /* print error and quit */
+            DIAG_printf("ECC_Example_esmInit: Error initializing MCU ESM: result = %d\n",
+                        result);
+
+            retValue = -1;
+        } else {
+            DIAG_printf("\nECC_Example_esmInit: Init MCU ESM complete \n");
+        }
+    }
+
+    if (retValue == 0) {
+        /* Initialize MAIN ESM module */
+        result = SDR_ESM_init(SDR_ESM_INSTANCE_MAIN, &ECC_Example_esmInitConfig_MAIN);
+        if (result != SDR_PASS) {
+            /* print error and quit */
+            DIAG_printf("ECC_Example_esmInit: Error initializing MAIN ESM: result = %d\n",
+                        result);
+
+            retValue = -1;
+        } else {
+            DIAG_printf("\nECC_Example_esmInit: Init MAIN ESM complete \n");
+        }
+    }
+
+    if (retValue == 0) {
+        /* Initialize ECC callbacks within the MCU ESM */
+        result = SDR_ECC_initEsm(SDR_ESM_INSTANCE_MCU);
+        if (result != SDR_PASS) {
+            /* print error and quit */
+             DIAG_printf("ECC_Example_esmInit: Error initializing ECC callback for " \
+                         "MCU ESM: result = %d\n",
+                         result);
+
+            retValue = -1;
+        } else {
+            DIAG_printf("\nECC_Example_esmInit: ECC Callback Init complete for MCU ESM \n");
+        }
+    }
+
+    /* Initialize all ECC aggregators that desire monitoring that report events to the
+     * MCU ESM instance.
+     * This example only shows MCU R5F ECC aggregator instance.  If additional
+     * ECC aggregators are needed, they should also be initialized here. */
+    if (retValue == 0) {
+        /* Initialize ECC */
+        result = SDR_ECC_init(SDR_ECC_MEMTYPE_MCU_R5F0_CORE,
+                              &ECC_Example_R5FCoreECCInitConfig);
+        if (result != SDR_PASS) {
+            /* print error and quit */
+             DIAG_printf("ECC_Example_esmInit: Error initializing R5F core " \
+                         "ECC: result = %d\n",
+                         result);
+
+            retValue = -1;
+        } else {
+            DIAG_printf("\nECC_Example_esmInit: R5F Core Init ECC complete \n");
+        }
+    }
+
+
+
+    if (retValue == 0) {
+        /* Initialize ECC callbacks within the Main ESM */
+        result = SDR_ECC_initEsm(SDR_ESM_INSTANCE_MAIN);
+        if (result != SDR_PASS) {
+            /* print error and quit */
+             DIAG_printf("ECC_Example_esmInit: Error initializing ECC callback for " \
+                         "Main ESM: result = %d\n",
+                         result);
+
+            retValue = -1;
+        } else {
+            DIAG_printf("\nECC_Example_esmInit: ECC Callback Init complete for Main ESM \n");
+        }
+    }
+
+    if (retValue == 0) {
+        /* Initialize VIM ECC memory ; This is specifically for VIM in lockstep*/
+        /* All other memories are auto initialized by hardware */
+        result = SDR_ECC_initMemory(SDR_ECC_MEMTYPE_MCU_R5F0_CORE,
+                                    SDR_ECC_R5F_MEM_SUBTYPE_KS_VIM_RAM_VECTOR_ID);
+        if (result != SDR_PASS) {
+             /* print error and quit */
+             DIAG_printf("ECC_Example_esmInit: Error initializing ECC memory: result = %d\n",
+                         result);
+             retValue = -1;;
+         } else {
+             DIAG_printf("\nECC_Example_esmInit: ECC Memory init complete \n");
+         }
+    }
+
+    /* Initialize all ECC aggregators that desire monitoring that report events to the
+     * Main ESM instance.
+     * This example only shows MSMC_AGGR0 instance.  If additional ECC aggregators are needed,
+     * they should also be initialized here. */
+    if (retValue == 0) {
+        /* Initialize ECC */
+        result = SDR_ECC_init(SDR_ECC_MEMTYPE_MAIN_MSMC_AGGR0,
+                              &ECC_Example_MSMCMemECCInitConfig);
+        if (result != SDR_PASS) {
+            /* print error and quit */
+             DIAG_printf("ECC_Example_esmInit: Error initializing MSMC ECC: result = %d\n",
+                         result);
+
+            retValue = -1;
+        } else {
+            DIAG_printf("\nECC_Example_esmInit: MSMC Init ECC complete \n");
+        }
+    }
+
+    if (retValue == 0) {
+        /* Register MCU Esm handlers */
+        retValue = ECC_Example_EsmInitHandlerInit(SDR_ESM_INSTANCE_MCU);
+        if (retValue != 0) {
+            DIAG_printf("\nECC_Example_esmInit: Init MCU ESM handlers failed \n");
+        } else {
+            DIAG_printf("\nECC_Example_esmInit: Init MCU ESM handlers complete \n");
+        }
+
+        /* Register Main Esm handlers */
+        retValue = ECC_Example_EsmInitHandlerInit(SDR_ESM_INSTANCE_MAIN);
+        if (retValue != 0) {
+            DIAG_printf("\nECC_Example_esmInit: Init MAIN ESM handlers failed \n");
+        } else {
+            DIAG_printf("\nECC_Example_esmInit: Init MAIN ESM handlers complete \n");
+        }
+    }
+
+    return retValue;
+}
+
+/*********************************************************************
+* @fn      ECC_Example_EsmInitHandlerInit
+*
+* @brief   Register all callbacks for an ESM instance
+*
+* @param   esmInstType: Instance type of ESM 
+*
+* @return    0 : Success; < 0 for failures
+*/
+static int32_t ECC_Example_EsmInitHandlerInit(SDR_ESM_InstanceType esmInstType)
+{
+    int32_t result = 0;
+    uint32_t intNumHi, intNumLo, intNumCfg;
+    HwiP_Params       hwiParams;
+    void (*pHiInterruptHandler)(uintptr_t);
+    void (*pLoInterruptHandler)(uintptr_t);
+    void (*pConfigInterruptHandler)(uintptr_t);
+
+    switch (esmInstType) {
+        case (SDR_ESM_INSTANCE_WKUP):
+            pHiInterruptHandler = &SDR_ESM_hiInterruptHandler_WKUP;
+            pLoInterruptHandler = &SDR_ESM_loInterruptHandler_WKUP;
+            pConfigInterruptHandler = &SDR_ESM_configInterruptHandler_WKUP;
+            break;
+
+        case (SDR_ESM_INSTANCE_MAIN):
+            pHiInterruptHandler = &SDR_ESM_hiInterruptHandler_MAIN;
+            pLoInterruptHandler = &SDR_ESM_loInterruptHandler_MAIN;
+            pConfigInterruptHandler = &SDR_ESM_configInterruptHandler_MAIN;
+            break;
+
+        case (SDR_ESM_INSTANCE_MCU):
+        default:
+            pHiInterruptHandler = &SDR_ESM_hiInterruptHandler_MCU;
+            pLoInterruptHandler = &SDR_ESM_loInterruptHandler_MCU;
+            pConfigInterruptHandler = &SDR_ESM_configInterruptHandler_MCU;
+            break;
+    }
+
+    /* Get the interrupt number corresponding to ESM HI interrupt */
+    intNumHi = SDR_ESM_getIntNumber(esmInstType,
+                                    SDR_ESM_INT_TYPE_HI);
+    if ( intNumHi == SDR_ESM_INTNUMBER_INVALID ) {
+        result = -1;
+    } else {
+        /* Get the interrupt number corresponding to ESM LO interrupt */
+        intNumLo = SDR_ESM_getIntNumber(esmInstType,
+                                        SDR_ESM_INT_TYPE_LO);
+        if ( intNumLo == SDR_ESM_INTNUMBER_INVALID ) {
+            result = -1;
+        } else {
+            /* Get the interrupt number corresponding to ESM Config interrupt */
+            intNumCfg = SDR_ESM_getIntNumber(esmInstType,
+                                             SDR_ESM_INT_TYPE_CFG);
+            if ( intNumCfg == SDR_ESM_INTNUMBER_INVALID ) {
+                result = -1;
+            } else {
+                DIAG_printf("\n ECC_Example_EsmInitHandlerInit: " \
+                            "Obtain interrupt number complete \n");
+                /* Clear all interrupts first */
+                HwiP_disableInterrupt(intNumHi);
+                HwiP_disableInterrupt(intNumLo);
+                HwiP_disableInterrupt(intNumCfg);
+
+                DIAG_printf("\n ECC_Example_EsmInitHandlerInit: " \
+                            "Disable interrupts complete \n");
+
+                /* Default parameter initialization */
+                HwiP_Params_init(&hwiParams);
+
+                hwiParams.arg = intNumHi;
+                DIAG_printf("\n ECC_Example_EsmInitHandlerInit: " \
+                            "HwiP_Params_init complete \n");
+
+                /* Register call back function for ESM Hi Interrupt */
+                ECC_Example_EsmHiHwiPHandle = HwiP_create(intNumHi,
+                                                          (HwiP_Fxn)(*pHiInterruptHandler),
+                                                          (void *)&hwiParams);
+                DIAG_printf("\n ECC_Example_EsmInitHandlerInit: " \
+                            "intNumHi registration complete \n");
+                if (ECC_Example_EsmHiHwiPHandle == (HwiP_Handle) NULL) {
+                    result = -1;
+                } else {
+                    hwiParams.arg = intNumLo;
+                    /* Register call back function for ESM Lo Interrupt */
+                    ECC_Example_EsmLoHwiPHandle = HwiP_create(intNumLo,
+                                                              (HwiP_Fxn)(*pLoInterruptHandler),
+                                                              (void *)&hwiParams);
+                    DIAG_printf("\n ECC_Example_EsmInitHandlerInit: " \
+                                "intNumLo registration complete \n");
+                    if (ECC_Example_EsmLoHwiPHandle == (HwiP_Handle) NULL) {
+                        result = -1;
+                    } else {
+                        hwiParams.arg = intNumCfg;
+                        /* Register call back function for ESM Config Interrupt */
+                        ECC_Example_EsmCfgHwiPHandle = HwiP_create(intNumCfg,
+                                                   (HwiP_Fxn)(*pConfigInterruptHandler),
+                                                   (void *)&hwiParams);
+                        DIAG_printf("\n ECC_Example_EsmInitHandlerInit: " \
+                                    "intNumCfg registration complete \n");
+                        if (ECC_Example_EsmCfgHwiPHandle == (HwiP_Handle) NULL) {
+                            result = -1;
+                        } else {
+                            /* Enable all ESM Interrupts */
+                            HwiP_enableInterrupt(intNumHi);
+                            HwiP_enableInterrupt(intNumLo);
+                            HwiP_enableInterrupt(intNumCfg);
+                       }
+                    }
+                }
+            }
+        }
+    }
+
+    return result;
+}
+
+#ifdef PRINT_EVENTS
+static const char *printEsmIntType(SDR_ESM_IntType esmIntType)
+{
+    char *pStr;
+
+    switch(esmIntType)
+    {
+        case SDR_ESM_INT_TYPE_HI:
+            pStr = "High Priority ESM event";
+            break;
+        case SDR_ESM_INT_TYPE_LO:
+            pStr = "Low Priority ESM event";
+            break;
+        case SDR_ESM_INT_TYPE_CFG:
+            pStr = "Config ESM event";
+            break;
+        default:
+            pStr = NULL;
+            break;
+    }
+
+    return pStr;
+}
+#endif
+
+static const char *printEccErrorType(SDR_ECC_InjectErrorType eccErrorType)
+{
+    char *pStr;
+
+    switch(eccErrorType)
+    {
+        case SDR_INJECT_ECC_NO_ERROR:
+            pStr = "No ECC Error";
+            break;
+        case SDR_INJECT_ECC_ERROR_FORCING_1BIT_ONCE:
+            pStr = "1-Bit ECC Error";
+            break;
+        case SDR_INJECT_ECC_ERROR_FORCING_2BIT_ONCE:
+            pStr = "2-Bit ECC Error";
+            break;
+        default:
+            pStr = NULL;
+            break;
+    }
+
+    return pStr;
+
+}
+
+/*********************************************************************
+* @fn      ECC_Example_printSummary
+*
+* @brief   Print summary of all the example use cases run
+*
+* @param   None
+*
+* @return  None
+*/
+void ECC_Example_printSummary(void)
+{
+    int32_t i;
+
+    DIAG_printf("\n\n");
+    DIAG_printf("ECC Example Application summary\n");
+    DIAG_printf("-------------------------------\n");
+    DIAG_printf("Completed %d Use Cases\n", currUseCase);
+
+    DIAG_printf("Received Total of %d ECC Events\n", totalEccEventsLogged);
+
+    DIAG_printf("\nUse Case Event Log\n");
+    DIAG_printf("------------------\n");
+    for (i = 0; i < totalEccEventsLogged; i++) {
+        DIAG_printf("\nUse Case %d: ECC Call back function called : \n"
+                    "    ECC Error Type = %s, address 0x%x, \n" \
+                    "    ramId %d, bitErrorOffset 0x%08x%08x, bitErrorGroup %d\n",
+                    eccEventLog[i].useCaseNum,
+                    printEccErrorType((SDR_ECC_InjectErrorType)eccEventLog[i].errorSrc),
+                    eccEventLog[i].address,
+                    eccEventLog[i].ramId,
+                    (uint32_t)(eccEventLog[i].bitErrorOffset >> 32),
+                    (uint32_t)(eccEventLog[i].bitErrorOffset & 0x00000000FFFFFFFF),
+                    eccEventLog[i].bitErrorGroup);
+    }
+    for (i = 0; i < 6; i++) {
+        DIAG_printf("\nUse Case %d received %d ECC events\n", i, totalEccEventsPerUseCase[i]);
+    }
+}
+
+static int32_t checkUseCaseStructs(uint8_t actualLogSlot, uint8_t expectedLogSlot)
+{
+    int32_t retValue = 0;
+    char *pStrErrType;
+    uint8_t useCaseNum = eccEventLog[actualLogSlot].useCaseNum;
+
+    if (expectedEccEventLog[expectedLogSlot].errorSrc == CSL_ECC_AGGR_INTR_SRC_SINGLE_BIT)
+    {
+        pStrErrType = "SEC";
+    } else if (expectedEccEventLog[expectedLogSlot].errorSrc == CSL_ECC_AGGR_INTR_SRC_DOUBLE_BIT)
+    {
+        pStrErrType = "DED";
+    }
+
+    /* Check event for proper information */
+    if (expectedEccEventLog[expectedLogSlot].errorSrc !=
+        eccEventLog[actualLogSlot].errorSrc) {
+        DIAG_printf("Error - Incorrect errorSrc for %s event in " \
+                    "Use Case %d\n", pStrErrType, useCaseNum);
+        retValue = -1;
+    }
+    if (expectedEccEventLog[expectedLogSlot].address !=
+        eccEventLog[actualLogSlot].address) {
+        DIAG_printf("Error - Incorrect address for %s event in " \
+                    "Use Case %d\n", pStrErrType, useCaseNum);
+        retValue = -1;
+    }
+    if (expectedEccEventLog[expectedLogSlot].ramId !=
+        eccEventLog[actualLogSlot].ramId) {
+        DIAG_printf("Error - Incorrect ramId for %s event in " \
+                    "Use Case %d\n", pStrErrType, useCaseNum);
+        retValue = -1;
+    }
+    /* bitErrorOffset is not checked in case of MSMC Wrapper Use Cases,
+     * since exact location of the error depends on triggering of CLEC
+     * events (and not a direct access to a memory location */
+    if ((useCaseNum != 3) && (useCaseNum != 5))
+    {
+        if (expectedEccEventLog[expectedLogSlot].bitErrorOffset !=
+            eccEventLog[actualLogSlot].bitErrorOffset) {
+            DIAG_printf("Error - Incorrect bitErrorOffset for %s event in " \
+                        "Use Case %d\n", pStrErrType, useCaseNum);
+            retValue = -1;
+        }
+    }
+    if (expectedEccEventLog[expectedLogSlot].bitErrorGroup !=
+        eccEventLog[actualLogSlot].bitErrorGroup) {
+        DIAG_printf("Error - Incorrect bitErrorGroup for %s event in " \
+                    "Use Case %d\n", pStrErrType, useCaseNum);
+        retValue = -1;
+    }
+
+    return retValue;
+
+}
+
+
+static int32_t checkUseCaseOutputs(uint8_t useCaseNum)
+{
+    uint8_t i;
+    int32_t status = 0;
+    int32_t retValue;
+    uint8_t useCaseLogStartSlot;
+
+#ifdef DEBUG_PRINT
+    DIAG_printf("Checking values for Use Case %d\n", useCaseNum);
+#endif
+    if (useCaseNum == 5) {
+        useCaseLogStartSlot = SINGLE_SEC_DED_EVENT_USE_CASES * 2 +
+                              NUM_MULTIPLE_SEC_EVENTS + NUM_MULTIPLE_DED_EVENTS;
+    } else if (useCaseNum == 4) {
+        useCaseLogStartSlot = SINGLE_SEC_DED_EVENT_USE_CASES * 2;
+    } else {
+        useCaseLogStartSlot = useCaseNum * 2;
+    }
+
+    if ((useCaseNum == 4) || (useCaseNum == 5)) {
+        /* Check all NUM_MULTIPLE_SEC_EVENTS for proper information */
+        for (i = 0; i < NUM_MULTIPLE_SEC_EVENTS; i++) {
+            retValue = checkUseCaseStructs(useCaseLogStartSlot + i, 2 * useCaseNum);
+            if (retValue != 0) {
+                status = -1;
+            }
+        }
+        /* Check all NUM_MULTIPLE_DED_EVENTS for proper information */
+        for (i = 0; i < NUM_MULTIPLE_DED_EVENTS; i++) {
+            retValue = checkUseCaseStructs(useCaseLogStartSlot + i + NUM_MULTIPLE_SEC_EVENTS,
+                                           2 * useCaseNum + 1);
+            if (retValue != 0) {
+                status = -1;
+            }
+        }
+    } else {
+        /* Use Case only has single SEC event and single DED event */
+        /* Check SEC event */
+        retValue = checkUseCaseStructs(2 * useCaseNum, 2 * useCaseNum);
+        if (retValue != 0) {
+            status = -1;
+        }
+        /* Check DED event */
+        retValue = checkUseCaseStructs(2 * useCaseNum + 1, 2 * useCaseNum + 1);
+        if (retValue != 0) {
+            status = -1;
+        }
+    }
+
+    return status;
+}
+
+
+void SDR_ESM_applicationCallbackFunction(SDR_ESM_InstanceType esmInstType,
+                                         SDR_ESM_IntType esmIntType,
+                                         uint32_t grpChannel,
+                                         uint32_t index,
+                                         uint32_t intSrc)
+{
+    /* All ECC events should be received via the ECC application callback */
+    /* This function just needs to be defined for proper linking with the SDR
+     * binary which expects the application to define this function */
+    /* Any additional customer-specific actions to address other ESM events
+     * separate from ECC events can be added here */
+#ifdef PRINT_EVENTS
+    /* Print information to screen */
+    DIAG_printf("\n  ESM Call back function called : instType 0x%x, intType 0x%x, " \
+                "grpChannel 0x%x, index 0x%x, intSrc 0x%x \n",
+                esmInstType, esmIntType, grpChannel, index, intSrc);
+    DIAG_printf("  Take action \n");
+
+    DIAG_printf("  ESM instance #%d, ESM interrupt type = %s\n",
+                esmInstType, printEsmIntType(esmIntType));
+#endif
+
+    return;
+}
+
+void SDR_assertExternalFunction(SDR_assertErrorNumber errorNumber)
+{
+
+    DIAG_printf("\n  Assert called with error Number %d \n",
+                errorNumber);
+    /* Asserts are fatal: Currently just wait for ever */
+    while(1);
+}
diff --git a/packages/ti/diag/examples/ecc_example_app/esm.h b/packages/ti/diag/examples/ecc_example_app/esm.h
new file mode 100644 (file)
index 0000000..1533c91
--- /dev/null
@@ -0,0 +1,65 @@
+/*
+ * ESM Example
+ *
+ * Error Signaling Module (ESM) Example Application
+ *
+ *  Copyright (c) 2020 Texas Instruments Incorporated
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef INCLUDE_ESM_H_
+#define INCLUDE_ESM_H_
+
+/*===========================================================================*/
+/*                         Internal function declarations                    */
+/*===========================================================================*/
+
+/*********************************************************************
+* @fn      ECC_Example_esmInit
+*
+* @brief   Initializes Board and ESM module
+*
+* @param   None
+*
+* @return    0 : Success; < 0 for failures
+*/
+int32_t ECC_Example_esmInit (void);
+
+/*********************************************************************
+* @fn      ECC_Example_printSummary
+*
+* @brief   Print summary of all the example use cases run
+*
+* @param   None
+*
+* @return  None
+*/
+void ECC_Example_printSummary(void);
+
+#endif /*  INCLUDE_ESM_H_ */
diff --git a/packages/ti/diag/examples/ecc_example_app/j721e/ecc_trigger_func.c b/packages/ti/diag/examples/ecc_example_app/j721e/ecc_trigger_func.c
new file mode 100644 (file)
index 0000000..ce6ca98
--- /dev/null
@@ -0,0 +1,306 @@
+/*
+ * ECC Example
+ *
+ * Error Correcting Code (ECC) Example Application
+ *
+ *  Copyright (c) 2020 Texas Instruments Incorporated
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+/**
+ *  \file ecc_trigger_func.c
+ *
+ *  \brief This file contains SoC-specific functions that need to be run as
+ *         part of the ECC error event input triggers by the Error Correcting
+ *         Code Module (ECC) application.
+ */
+
+/* ========================================================================== */
+/*                             Include Files                                  */
+/* ========================================================================== */
+#include <stdint.h>
+
+#include <ti/csl/soc.h>
+#include <ti/csl/csl_cbass.h>
+#include <ti/csl/csl_clec.h>
+#include <ti/drv/sciclient/sciclient.h>
+
+#include <ti/osal/HwiP.h>
+
+#include <diag_utils.h>
+
+#include <sdr_ecc.h>
+
+/* ========================================================================== */
+/*                           Macros & Typedefs                                */
+/* ========================================================================== */
+
+#define FW_MCU_R5F0_PRIVID (96U)
+
+#define CLEC_EVENT         CSLR_COMPUTE_CLUSTER0_CLEC_MSMC_EVENT_IN_COMPUTE_CLUSTER0_CORE_CORE_MSMC_INTR_12
+
+/* ========================================================================== */
+/*                         Structure Declarations                             */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/*                          Function Declarations                             */
+/* ========================================================================== */
+
+static void    eventHandler(void);
+static int32_t CLEC_setFirewall(void);
+static int32_t configCLEC(void);
+static int32_t sendClecEvent(void);
+
+/* ========================================================================== */
+/*                            Global Variables                                */
+/* ========================================================================== */
+
+/* The following array defines trigger functions needed for each Use Case
+ * (if needed). If no trigger functions are needed, then the array slot value
+ * is set to NULL. */
+
+int32_t (*useCaseTriggerFuncArray[6])() =
+{
+    NULL,
+    NULL,
+    NULL,
+    sendClecEvent,
+    NULL,
+    sendClecEvent
+};
+
+/* ========================================================================== */
+/*                            External Variables                              */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/*                          Function Definitions                              */
+/* ========================================================================== */
+
+/* This function performs any high-level event trigger setup that should be done
+ * before any of the use cases in the ECC example application start. */
+int32_t eventTriggerSetup(void)
+{
+    int32_t retValue = 0;
+    CSL_ErrType_t status;
+
+    /* Add firewall entry to gain access to CLEC registers */
+    status = CLEC_setFirewall();
+    if (status != CSL_PASS)
+    {
+        DIAG_printf(" CLEC_setFirewall failed \n");
+        retValue = -1;
+    }
+    
+    retValue = configCLEC();
+
+    return retValue;
+}
+
+static int32_t configCLEC(void)
+{
+    int32_t retValue = 0;
+    CSL_ErrType_t status;
+    CSL_ClecEventConfig evtCfg;
+    HwiP_Params hwiParams;
+    HwiP_Handle hwiPHandle;
+
+    evtCfg.secureClaimEnable = 1U;
+    evtCfg.evtSendEnable     = 1U;
+    evtCfg.extEvtNum         = CLEC_EVENT;
+    evtCfg.rtMap             = 2U;
+    evtCfg.c7xEvtNum         = 0U;
+
+    /* Configure interrupt router to ensure that interrupt event will trigger ECC
+     * interrept when ECC error is injected */
+    status =  CSL_clecConfigEvent((CSL_CLEC_EVTRegs *)CSL_COMPUTE_CLUSTER0_CLEC_REGS_BASE,
+                                  CLEC_EVENT,
+                                  &evtCfg);
+    if (status != CSL_PASS)
+    {
+        DIAG_printf(" CSL_clecConfigEvent failed \n");
+        retValue = -1;
+    }
+
+
+    /* Disable interrupt */
+    HwiP_disableInterrupt(CSLR_MCU_R5FSS0_CORE0_INTR_COMPUTE_CLUSTER0_CLEC_SOC_EVENTS_OUT_LEVEL_12);
+
+    /* Default parameter initialization */
+    HwiP_Params_init(&hwiParams);
+
+#ifdef DEBUG_PRINT
+    DIAG_printf("\n HwiP_Params_init complete \n");
+#endif
+    /* Register call back function for Interrupt */
+    hwiPHandle = HwiP_create(CSLR_MCU_R5FSS0_CORE0_INTR_COMPUTE_CLUSTER0_CLEC_SOC_EVENTS_OUT_LEVEL_12,
+                             (HwiP_Fxn)eventHandler,
+                             (void *)&hwiParams);
+    if (hwiPHandle == NULL)
+    {
+        DIAG_printf(" Interrupt registration failed \n");
+        retValue = -1;
+    }
+
+    return retValue;
+}
+
+
+void eventHandler(void)
+{
+    CSL_ErrType_t status;
+
+#ifdef DEBUG_PRINT
+    DIAG_printf("Got CLEC event\n");
+#endif
+
+    /* Clear C7x PBIST interrupt event in CLEC */
+    status = CSL_clecClearEvent((CSL_CLEC_EVTRegs *)CSL_COMPUTE_CLUSTER0_CLEC_REGS_BASE,
+                   CSLR_COMPUTE_CLUSTER0_CLEC_MSMC_EVENT_IN_COMPUTE_CLUSTER0_CORE_CORE_MSMC_INTR_12);
+    if (status != CSL_PASS) {
+        DIAG_printf("eventHandler: Clearing CLEC event failed \n");
+    }
+
+    return;
+}
+
+static int32_t sendClecEvent(void)
+{
+    CSL_CLEC_EVTRegs *pRegs = (CSL_CLEC_EVTRegs *)CSL_COMPUTE_CLUSTER0_CLEC_REGS_BASE;
+    int32_t           status;
+
+    uint32_t evtNum = CLEC_EVENT;
+    status = CSL_clecSendEvent(pRegs, evtNum);
+
+    return status;
+}
+
+/* CLEC_setFirewall: Sets firewall settings to be able to access CLEC registers */
+static int32_t CLEC_setFirewall(void)
+{
+    int32_t retVal = CSL_PASS;
+    uint32_t reqFlag = TISCI_MSG_FLAG_AOP | TISCI_MSG_FLAG_DEVICE_EXCLUSIVE;
+    uint32_t timeout =  SCICLIENT_SERVICE_WAIT_FOREVER;
+    struct  tisci_msg_fwl_set_firewall_region_req request;
+    Sciclient_ReqPrm_t reqParam;
+    Sciclient_RespPrm_t respParam;
+
+    request.fwl_id       = (uint32_t)CSL_STD_FW_NAVSS0_NAV_SRAM0_ID;
+    request.region = (uint32_t) 0U; /* Pick up any unused region : 0 */
+    request.n_permission_regs = CSL_FW_NUM_CBASS_FW_EP_REGION_PERMISSION;
+    request.control = (CSL_FW_REGION_ENABLE & CSL_CBASS_ISC_EP_REGION_CONTROL_ENABLE_MASK);
+    request.permissions[0] = (FW_MCU_R5F0_PRIVID << CSL_CBASS_FW_EP_REGION_PERMISSION_PRIV_ID_SHIFT)
+                             | (1U << CSL_CBASS_FW_EP_REGION_PERMISSION_SEC_SUPV_WRITE_SHIFT)
+                             | (1U << CSL_CBASS_FW_EP_REGION_PERMISSION_SEC_SUPV_READ_SHIFT)
+                             | (0U << CSL_CBASS_FW_EP_REGION_PERMISSION_SEC_SUPV_CACHEABLE_SHIFT)
+                             | (1U << CSL_CBASS_FW_EP_REGION_PERMISSION_SEC_SUPV_DEBUG_SHIFT)
+                             | (1U << CSL_CBASS_FW_EP_REGION_PERMISSION_SEC_USER_WRITE_SHIFT)
+                             | (1U << CSL_CBASS_FW_EP_REGION_PERMISSION_SEC_USER_READ_SHIFT)
+                             | (0U << CSL_CBASS_FW_EP_REGION_PERMISSION_SEC_USER_CACHEABLE_SHIFT)
+                             | (1U << CSL_CBASS_FW_EP_REGION_PERMISSION_SEC_USER_DEBUG_SHIFT)
+                             | (1U << CSL_CBASS_FW_EP_REGION_PERMISSION_NONSEC_SUPV_WRITE_SHIFT)
+                             | (1U << CSL_CBASS_FW_EP_REGION_PERMISSION_NONSEC_SUPV_READ_SHIFT)
+                             | (0U << CSL_CBASS_FW_EP_REGION_PERMISSION_NONSEC_SUPV_CACHEABLE_SHIFT)
+                             | (1U << CSL_CBASS_FW_EP_REGION_PERMISSION_NONSEC_SUPV_DEBUG_SHIFT)
+                             | (1U << CSL_CBASS_FW_EP_REGION_PERMISSION_NONSEC_USER_WRITE_SHIFT)
+                             | (1U << CSL_CBASS_FW_EP_REGION_PERMISSION_NONSEC_USER_READ_SHIFT)
+                             | (0U << CSL_CBASS_FW_EP_REGION_PERMISSION_NONSEC_USER_CACHEABLE_SHIFT)
+                             | (1U << CSL_CBASS_FW_EP_REGION_PERMISSION_NONSEC_USER_DEBUG_SHIFT);
+    request.permissions[1] = (FW_MCU_R5F0_PRIVID << CSL_CBASS_FW_EP_REGION_PERMISSION_PRIV_ID_SHIFT)
+                             | (1U << CSL_CBASS_FW_EP_REGION_PERMISSION_SEC_SUPV_WRITE_SHIFT)
+                             | (1U << CSL_CBASS_FW_EP_REGION_PERMISSION_SEC_SUPV_READ_SHIFT)
+                             | (0U << CSL_CBASS_FW_EP_REGION_PERMISSION_SEC_SUPV_CACHEABLE_SHIFT)
+                             | (1U << CSL_CBASS_FW_EP_REGION_PERMISSION_SEC_SUPV_DEBUG_SHIFT)
+                             | (1U << CSL_CBASS_FW_EP_REGION_PERMISSION_SEC_USER_WRITE_SHIFT)
+                             | (1U << CSL_CBASS_FW_EP_REGION_PERMISSION_SEC_USER_READ_SHIFT)
+                             | (0U << CSL_CBASS_FW_EP_REGION_PERMISSION_SEC_USER_CACHEABLE_SHIFT)
+                             | (1U << CSL_CBASS_FW_EP_REGION_PERMISSION_SEC_USER_DEBUG_SHIFT)
+                             | (1U << CSL_CBASS_FW_EP_REGION_PERMISSION_NONSEC_SUPV_WRITE_SHIFT)
+                             | (1U << CSL_CBASS_FW_EP_REGION_PERMISSION_NONSEC_SUPV_READ_SHIFT)
+                             | (0U << CSL_CBASS_FW_EP_REGION_PERMISSION_NONSEC_SUPV_CACHEABLE_SHIFT)
+                             | (1U << CSL_CBASS_FW_EP_REGION_PERMISSION_NONSEC_SUPV_DEBUG_SHIFT)
+                             | (1U << CSL_CBASS_FW_EP_REGION_PERMISSION_NONSEC_USER_WRITE_SHIFT)
+                             | (1U << CSL_CBASS_FW_EP_REGION_PERMISSION_NONSEC_USER_READ_SHIFT)
+                             | (0U << CSL_CBASS_FW_EP_REGION_PERMISSION_NONSEC_USER_CACHEABLE_SHIFT)
+                             | (1U << CSL_CBASS_FW_EP_REGION_PERMISSION_NONSEC_USER_DEBUG_SHIFT);
+    request.permissions[2] = (FW_MCU_R5F0_PRIVID << CSL_CBASS_FW_EP_REGION_PERMISSION_PRIV_ID_SHIFT)
+                             | (1U << CSL_CBASS_FW_EP_REGION_PERMISSION_SEC_SUPV_WRITE_SHIFT)
+                             | (1U << CSL_CBASS_FW_EP_REGION_PERMISSION_SEC_SUPV_READ_SHIFT)
+                             | (0U << CSL_CBASS_FW_EP_REGION_PERMISSION_SEC_SUPV_CACHEABLE_SHIFT)
+                             | (1U << CSL_CBASS_FW_EP_REGION_PERMISSION_SEC_SUPV_DEBUG_SHIFT)
+                             | (1U << CSL_CBASS_FW_EP_REGION_PERMISSION_SEC_USER_WRITE_SHIFT)
+                             | (1U << CSL_CBASS_FW_EP_REGION_PERMISSION_SEC_USER_READ_SHIFT)
+                             | (0U << CSL_CBASS_FW_EP_REGION_PERMISSION_SEC_USER_CACHEABLE_SHIFT)
+                             | (1U << CSL_CBASS_FW_EP_REGION_PERMISSION_SEC_USER_DEBUG_SHIFT)
+                             | (1U << CSL_CBASS_FW_EP_REGION_PERMISSION_NONSEC_SUPV_WRITE_SHIFT)
+                             | (1U << CSL_CBASS_FW_EP_REGION_PERMISSION_NONSEC_SUPV_READ_SHIFT)
+                             | (0U << CSL_CBASS_FW_EP_REGION_PERMISSION_NONSEC_SUPV_CACHEABLE_SHIFT)
+                             | (1U << CSL_CBASS_FW_EP_REGION_PERMISSION_NONSEC_SUPV_DEBUG_SHIFT)
+                             | (1U << CSL_CBASS_FW_EP_REGION_PERMISSION_NONSEC_USER_WRITE_SHIFT)
+                             | (1U << CSL_CBASS_FW_EP_REGION_PERMISSION_NONSEC_USER_READ_SHIFT)
+                             | (0U << CSL_CBASS_FW_EP_REGION_PERMISSION_NONSEC_USER_CACHEABLE_SHIFT)
+                             | (1U << CSL_CBASS_FW_EP_REGION_PERMISSION_NONSEC_USER_DEBUG_SHIFT);
+
+    request.start_address = CSL_COMPUTE_CLUSTER0_CLEC_REGS_BASE;
+    request.end_address = CSL_COMPUTE_CLUSTER0_CLEC_REGS_BASE + CSL_COMPUTE_CLUSTER0_CLEC_REGS_SIZE;
+
+    reqParam.messageType    = (uint16_t) TISCI_MSG_SET_FWL_REGION;
+    reqParam.flags          = (uint32_t) reqFlag;
+    reqParam.pReqPayload    = (const uint8_t *) &request;
+    reqParam.reqPayloadSize = (uint32_t) sizeof (request);
+    reqParam.timeout        = (uint32_t) timeout;
+
+    respParam.flags           = (uint32_t) 0;   /* Populated by the API */
+    respParam.pRespPayload    = (uint8_t *) 0;
+    respParam.respPayloadSize = (uint32_t) 0;
+
+
+    if (((reqFlag & TISCI_MSG_FLAG_AOP) != TISCI_MSG_FLAG_AOP)&&
+        (reqFlag != 0U))
+    {
+        retVal = CSL_EFAIL;
+    }
+    if (retVal == CSL_PASS)
+    {
+        retVal = Sciclient_service(&reqParam, &respParam);
+    }
+    if ((retVal != CSL_PASS) ||
+        ((reqFlag != 0U) &&
+        ((respParam.flags & TISCI_MSG_FLAG_ACK) != TISCI_MSG_FLAG_ACK)))
+    {
+        retVal = CSL_EFAIL;
+    }
+    return retVal;
+}
diff --git a/packages/ti/diag/examples/ecc_example_app/j721e/ecc_trigger_func.h b/packages/ti/diag/examples/ecc_example_app/j721e/ecc_trigger_func.h
new file mode 100644 (file)
index 0000000..f84344f
--- /dev/null
@@ -0,0 +1,45 @@
+/*
+ * ECC Example
+ *
+ * Error Correcting Code (ECC) Example Application
+ *
+ *  Copyright (c) 2020 Texas Instruments Incorporated
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef INCLUDE_ECC_TRIGGER_FUNC_H_
+#define INCLUDE_ECC_TRIGGER_FUNC_H_
+
+/*===========================================================================*/
+/*                         Internal function declarations                    */
+/*===========================================================================*/
+
+int32_t eventTriggerSetup(void);
+
+#endif /*  INCLUDE_ECC_TRIGGER_FUNC_H_ */
diff --git a/packages/ti/diag/examples/ecc_example_app/j721e/linker_mcu1_0.lds b/packages/ti/diag/examples/ecc_example_app/j721e/linker_mcu1_0.lds
new file mode 100644 (file)
index 0000000..8b23a06
--- /dev/null
@@ -0,0 +1,100 @@
+/* Linker Settings */
+--retain="*(.bootCode)"
+--retain="*(.startupCode)"
+--retain="*(.startupData)"
+--retain="*(.intvecs)"
+--retain="*(.intc_text)"
+--retain="*(.rstvectors)"
+--retain="*(.irqStack)"
+--retain="*(.fiqStack)"
+--retain="*(.abortStack)"
+--retain="*(.undStack)"
+--retain="*(.svcStack)"
+--fill_value=0
+--stack_size=0x2000
+--heap_size=0x1000
+--entry_point=_resetvectors     /* Default C RTS boot.asm   */
+
+-stack  0x2000                              /* SOFTWARE STACK SIZE           */
+-heap   0x2000                              /* HEAP AREA SIZE                */
+
+/* Stack Sizes for various modes */
+__IRQ_STACK_SIZE = 0x1000;
+__FIQ_STACK_SIZE = 0x1000;
+__ABORT_STACK_SIZE = 0x1000;
+__UND_STACK_SIZE = 0x1000;
+__SVC_STACK_SIZE = 0x1000;
+
+/* Memory Map */
+MEMORY
+{
+    VECTORS (X)             : origin=0x41C7F000 length=0x1000
+    /*  Reset Vectors base address(RESET_VECTORS) should be 64 bytes aligned  */
+    RESET_VECTORS (X)       : origin=0x41C00000 length=0x100
+    /* MCU0_R5F_0 local view */
+    MCU0_R5F_TCMA_SBL_RSVD (X)  : origin=0x0        length=0x100
+    MCU0_R5F_TCMA (X)       : origin=0x100      length=0x8000 - 0x100
+    MCU0_R5F_TCMB0 (RWIX)   : origin=0x41010000 length=0x8000
+
+    /* MCU0_R5F_1 SoC view */
+    MCU0_R5F1_ATCM (RWIX)   : origin=0x41400000 length=0x8000
+    MCU0_R5F1_BTCM (RWIX)   : origin=0x41410000 length=0x8000
+
+    /* MCU0 share locations */
+    OCMRAM  (RWIX)          : origin=0x41C00100 length=0x80000 - 0x1100      /* ~510KB */
+
+    ECC_CFG_SCRATCH (RWIX)  : origin=0x60000000 length=0x1000          /* 64 KB */
+
+    /* j721e MCMS3 locations */
+    /* j721e Reserved Memory for ARM Trusted Firmware */
+    MSMC3_ARM_FW   (RWIX)   : origin=0x70000000 length=0x40000         /* 256KB */
+    MSMC3   (RWIX)          : origin=0x70040000 length=0x7B0000        /* 8MB - 320KB */
+    /* j721e Reserved Memory for DMSC Firmware */
+    MSMC3_DMSC_FW  (RWIX)   : origin=0x707F0000 length=0x10000         /* 64KB */
+
+    DDR0    (RWIX)          : origin=0x80000000 length=0x80000000      /* 2GB */
+}
+
+/* Section Configuration */
+SECTIONS
+{
+    /* 'intvecs' and 'intc_text' sections shall be placed within */
+    /* a range of +\- 16 MB */
+    .intvecs       : {} palign(8)      > VECTORS
+    .intc_text     : {} palign(8)      > VECTORS
+    .rstvectors    : {} palign(8)      > RESET_VECTORS
+    .bootCode      : {} palign(8)      > MSMC3
+    .startupCode   : {} palign(8)      > MSMC3
+    .startupData   : {} palign(8)      > MSMC3, type = NOINIT
+    .text          : {} palign(8)      > DDR0
+    .const         : {} palign(8)      > DDR0
+    .cinit         : {} palign(8)      > DDR0
+    .pinit         : {} palign(8)      > DDR0
+    .bss           : {} align(4)       > DDR0
+    .far           : {} align(4)       > DDR0
+    .data          : {} palign(128)    > DDR0
+    .boardcfg_data : {} palign(128)    > MSMC3
+    .my_aggr_reg   : {*(.my_aggr_reg)} > ECC_CFG_SCRATCH, type = NOINIT
+    .sysmem        : {}                > DDR0
+    .data_buffer   : {} palign(128)    > DDR0
+
+    /* USB or any other LLD buffer for benchmarking */
+    .benchmark_buffer (NOLOAD) {} ALIGN (8) > DDR0
+
+    .stack      : {} align(4)       > DDR0  (HIGH)
+    .irqStack   : {. = . + __IRQ_STACK_SIZE;} align(4)      > DDR0  (HIGH)
+    RUN_START(__IRQ_STACK_START)
+    RUN_END(__IRQ_STACK_END)
+    .fiqStack   : {. = . + __FIQ_STACK_SIZE;} align(4)      > DDR0  (HIGH)
+    RUN_START(__FIQ_STACK_START)
+    RUN_END(__FIQ_STACK_END)
+    .abortStack : {. = . + __ABORT_STACK_SIZE;} align(4)    > DDR0  (HIGH)
+    RUN_START(__ABORT_STACK_START)
+    RUN_END(__ABORT_STACK_END)
+    .undStack   : {. = . + __UND_STACK_SIZE;} align(4)      > DDR0  (HIGH)
+    RUN_START(__UND_STACK_START)
+    RUN_END(__UND_STACK_END)
+    .svcStack   : {. = . + __SVC_STACK_SIZE;} align(4)      > DDR0  (HIGH)
+    RUN_START(__SVC_STACK_START)
+    RUN_END(__SVC_STACK_END)
+}
diff --git a/packages/ti/diag/examples/ecc_example_app/j721e/platform.h b/packages/ti/diag/examples/ecc_example_app/j721e/platform.h
new file mode 100644 (file)
index 0000000..113df40
--- /dev/null
@@ -0,0 +1,43 @@
+/*
+ * ECC Example app
+ *
+ * Error Correcting Code (ECC) example application
+ *
+ *  Copyright (c) Texas Instruments Incorporated 2020
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef _INCLUDE_PLATFORM_H_
+#define _INCLUDE_PLATFORM_H_
+
+#define UART_INSTANCE 0
+
+#endif /* _INCLUDE_PLATFORM_H_ */
diff --git a/packages/ti/diag/examples/ecc_example_app/main.c b/packages/ti/diag/examples/ecc_example_app/main.c
new file mode 100644 (file)
index 0000000..066dd9b
--- /dev/null
@@ -0,0 +1,288 @@
+/*
+ * ECC Example
+ *
+ * Error Correcting Code (ECC) Example Application
+ *
+ *  Copyright (c) 2020 Texas Instruments Incorporated
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/**
+ *  \file main.c
+ *
+ *  \brief This file demonstrates using the Error Correcting Code Module (ECC),
+ *         utilizing the ECC and ESM Software Diagnostic Reference (SDR) functions.
+ */
+
+/* ========================================================================== */
+/*                             Include Files                                  */
+/* ========================================================================== */
+
+/* For Timer functions */
+#include <ti/osal/osal.h>
+
+#include <ti/board/board.h>
+
+/* Diagnostic example utility functions, e.g. print outputs */
+#include <diag_utils.h>
+
+#include "ecc_inject.h"
+#include "esm.h"
+
+#ifdef UNITY_INCLUDE_CONFIG_H
+#include <ti/build/unit-test/Unity/src/unity.h>
+#include <ti/build/unit-test/config/unity_config.h>
+#endif
+
+/* ========================================================================== */
+/*                           Macros & Typedefs                                */
+/* ========================================================================== */
+
+#define USE_CASES_RUN         (6)
+#define USE_CASES             (6)
+#define START_USE_CASE        (0)
+
+/* ========================================================================== */
+/*                         Structure Declarations                             */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/*                          Function Declarations                             */
+/* ========================================================================== */
+
+/* Unity functions */
+void diag_ex_ecc_example_app_runner(void);
+void ecc_example_app(void);
+
+static const char *printUseCaseStepResult(uint32_t result);
+
+/* ========================================================================== */
+/*                            Global Variables                                */
+/* ========================================================================== */
+
+/* State variable for each use case indicating input event trigger
+ * has been completed */
+volatile uint32_t eccEventInputTrig[USE_CASES] = {USE_CASE_STATUS_NOT_RUN,
+                                                  USE_CASE_STATUS_NOT_RUN,
+                                                  USE_CASE_STATUS_NOT_RUN,
+                                                  USE_CASE_STATUS_NOT_RUN,
+                                                  USE_CASE_STATUS_NOT_RUN,
+                                                  USE_CASE_STATUS_NOT_RUN};
+
+/* State variable for each use case indicating the ISR for the use case
+ * has been completed */
+volatile uint32_t eccOutputResult[USE_CASES] = {USE_CASE_STATUS_NOT_RUN,
+                                                USE_CASE_STATUS_NOT_RUN,
+                                                USE_CASE_STATUS_NOT_RUN,
+                                                USE_CASE_STATUS_NOT_RUN,
+                                                USE_CASE_STATUS_NOT_RUN,
+                                                USE_CASE_STATUS_NOT_RUN};
+volatile uint8_t currUseCase = START_USE_CASE;
+
+/* ========================================================================== */
+/*                            External Variables                              */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/*                          Function Definitions                              */
+/* ========================================================================== */
+
+/*****************************************************************************
+ * This is the main function for the Error Correcting Code (ECC) example
+ * application.
+ * It runs through 5 use cases to demonstrate usage of the ECC modules
+ * for receiving and interpretting ECC errors.
+ */
+void ecc_example_app(void)
+{
+    int32_t testErrCount = 0;
+    int32_t retValue;
+    uint8_t i;
+
+    Board_initCfg boardCfg;
+    Board_STATUS  boardStatus;
+
+    boardCfg = BOARD_INIT_PINMUX_CONFIG |
+               BOARD_INIT_UART_STDIO;
+    boardStatus = Board_init(boardCfg);
+    if (boardStatus != BOARD_SOK)
+    {
+        DIAG_printf("[Error] Board init failed!!\n");
+    } else {
+
+        /* Initialize the ESM instances and handlers */
+        retValue = ECC_Example_esmInit();
+#if defined (UNITY_INCLUDE_CONFIG_H)
+        TEST_ASSERT_GREATER_OR_EQUAL_INT32_MESSAGE(0, retValue,
+                                                   "\nERR: ECC_example_esmInit failed");
+#else
+        if (retValue < 0) {
+            /* print and exit */
+            DIAG_printf("\nERR: ECC_example_init failed");
+            testErrCount++;
+        }
+#endif
+        retValue = diag_ecc_initUseCases();
+
+#if defined (UNITY_INCLUDE_CONFIG_H)
+        TEST_ASSERT_GREATER_OR_EQUAL_INT32_MESSAGE(0, retValue,
+                                                   "\nERR: diag_ecc_initUseCases failed");
+#else
+        if (retValue < 0) {
+            /* print and exit */
+            DIAG_printf("\nERR: ECC_example_init failed");
+            testErrCount++;
+        }
+#endif
+        DIAG_printf("\nECC example init complete");
+
+        /* Trigger each Use Case */
+        for (i = START_USE_CASE; i < USE_CASES_RUN; i++) {
+            retValue = diag_ecc_runUseCaseTrigger(i);
+#if defined (UNITY_INCLUDE_CONFIG_H)
+            TEST_ASSERT_EQUAL_MESSAGE(0, retValue,
+                                      "\nERR: Use Case Trigger for Use Case %d failed \n");
+#else
+            if (retValue != 0) {
+                DIAG_printf("\nERR: Use Case Trigger for Use Case %d failed \n",
+                            retValue);
+                break;
+            }
+#endif
+            while((eccEventInputTrig[i] == USE_CASE_STATUS_NOT_RUN) ||
+                  (eccOutputResult[i] == USE_CASE_STATUS_NOT_RUN))
+            {
+#ifdef DEBUG_PRINT
+                DIAG_printf("InputTrig = %d, OutputResult = %d\n",
+                            eccEventInputTrig[i],
+                            eccOutputResult[i]);
+#endif
+            }
+            DIAG_printf("\nUse Case %d completed: Input Event Trigger = %s, \n" \
+                        "                       Event Handler Complete = %s, \n",
+                        i,
+                        printUseCaseStepResult(eccEventInputTrig[i]),
+                        printUseCaseStepResult(eccOutputResult[i]));
+            currUseCase++;
+        }
+
+        /* Check results of all the tests */
+        for (i = 0; i < USE_CASES_RUN; i++) {
+            if ((eccEventInputTrig[i] != USE_CASE_STATUS_COMPLETED_SUCCESS) ||
+                (eccOutputResult[i] != USE_CASE_STATUS_COMPLETED_SUCCESS)) {
+                testErrCount++;
+            }
+        }
+
+        /* Print results and logs of the Use Cases */
+        ECC_Example_printSummary();
+        DIAG_printf("\nECC Example Application: Complete");
+
+        if (testErrCount == 0)
+        {
+            DIAG_printf("\n All tests have passed. \n");
+        }
+        else
+        {
+            DIAG_printf("\n ESM Example app failed. \n");
+        }
+
+#if defined (UNITY_INCLUDE_CONFIG_H)
+        TEST_ASSERT_EQUAL_INT32(0, testErrCount);
+#endif
+
+    } /* else clause for if (boardStatus != BOARD_SOK) */
+
+    return;
+}
+
+static const char *printUseCaseStepResult(uint32_t result)
+{
+    char *pStr;
+
+    switch(result)
+    {
+        case USE_CASE_STATUS_NOT_RUN:
+            pStr = "Step Not yet run";
+            break;
+        case USE_CASE_STATUS_COMPLETED_SUCCESS:
+            pStr = "Step completed successfully";
+            break;
+        case USE_CASE_STATUS_COMPLETED_FAILURE:
+            pStr = "Step completed with failure";
+            break;
+        default:
+            pStr = NULL;
+            break;
+    }
+
+    return pStr;
+}
+
+int32_t main(void)
+{
+    (void) diag_ex_ecc_example_app_runner();
+
+    while (true)
+    {
+    }
+}
+
+#ifdef UNITY_INCLUDE_CONFIG_H
+/*
+ *  ======== Unity set up and tear down ========
+ */
+void setUp(void)
+{
+    /* Do nothing */
+}
+
+void tearDown(void)
+{
+    /* Do nothing */
+}
+#endif
+
+void diag_ex_ecc_example_app_runner(void)
+{
+#if defined(UNITY_INCLUDE_CONFIG_H)
+    UNITY_BEGIN();
+    RUN_TEST (ecc_example_app);
+    UNITY_END();
+    /* Function to print results defined in our unity_config.h file */
+    print_unityOutputBuffer_usingUARTstdio();
+#else
+    ecc_example_app();
+#endif
+    return;
+}
diff --git a/packages/ti/diag/examples/ecc_example_app/makefile b/packages/ti/diag/examples/ecc_example_app/makefile
new file mode 100644 (file)
index 0000000..02c4582
--- /dev/null
@@ -0,0 +1,86 @@
+#
+# This file is the makefile for building Software Diagnostics ECC Example app.
+#
+#   Copyright (c) Texas Instruments Incorporated 2020
+#
+include $(PDK_INSTALL_PATH)/ti/build/Rules.make
+
+APP_NAME = diag_ex_ecc_example_app
+
+BUILD_OS_TYPE=baremetal
+
+SRCDIR = . ../common $(SOC)
+INCDIR =
+
+INCDIR += $(SOC)/. ../common
+
+# List all the external components/interfaces, whose interface header files
+#  need to be included for this component
+INCLUDE_EXTERNAL_INTERFACES = pdk sdr
+
+# List all the components required by the application
+COMP_LIST_COMMON = csl_utils_common csl_uart_console
+COMP_LIST_COMMON += sdr
+
+ifeq ($(SOC),$(filter $(SOC), j721e))
+  COMP_LIST_COMMON += $(PDK_COMMON_BAREMETAL_COMP)
+endif
+
+ifeq ($(CSL_BUILD),$(filter $(CSL_BUILD), CSL))
+  ifneq ($(SOC),$(filter $(SOC), j721e))
+    COMP_LIST_COMMON = csl
+  endif
+else
+  COMP_LIST_COMMON := $(filter-out csl,$(COMP_LIST_COMMON))
+  COMP_LIST_COMMON = csl2 csl_trim
+endif
+
+# Common source files and CFLAGS across all platforms and cores
+PACKAGE_SRCS_COMMON = . ../common ../diag_ex_component.mk
+
+ifeq ($(SOC),$(filter $(SOC), j721e))
+  SRCS_COMMON = main.c esm.c ecc_inject.c diag_utils.c
+  SRCS_COMMON += ecc_trigger_func.c
+endif
+LNKFLAGS_LOCAL_mpu1_0 += --entry Entry
+CFLAGS_LOCAL_COMMON = $(PDK_CFLAGS)
+
+CFLAGS_LOCAL_COMMON += -DUART_PRINTF
+
+# To print events to UART during the flow of the Use Case itself,
+# uncomment this line
+# By default, this macro is disabled
+#CFLAGS_LOCAL_COMMON += -DPRINT_EVENTS
+# To print more verbose prints, uncomment this build flag
+#CFLAGS_LOCAL_COMMON += -DDEBUG_PRINT
+
+ifeq ($(SOC),$(filter $(SOC), j721e))
+ SRCDIR += $(PDK_INSTALL_PATH)/ti/build/unit-test/Unity/src
+ SRCDIR += $(PDK_INSTALL_PATH)/ti/build/unit-test/config
+ INCDIR += $(PDK_INSTALL_PATH)/ti/build/unit-test/Unity/src
+ INCDIR += $(PDK_INSTALL_PATH)/ti/build/unit-test/config
+ SRCS_COMMON += unity_config.c unity.c
+ CFLAGS_LOCAL_COMMON += -DUNITY_INCLUDE_CONFIG_H
+endif
+
+ifeq ($(SOC),$(filter $(SOC), j721e))
+  EXTERNAL_LNKCMD_FILE_LOCAL = $(PDK_INSTALL_PATH)/ti/diag/examples/ecc_example_app/${SOC}/linker_mcu1_0.lds
+endif
+
+# Core/SoC/platform specific source files and CFLAGS
+# Example:
+#   SRCS_<core/SoC/platform-name> =
+#   CFLAGS_LOCAL_<core/SoC/platform-name> =
+
+# Include common make files
+ifeq ($(MAKERULEDIR), )
+#Makerule path not defined, define this and assume relative path from ROOTDIR
+  MAKERULEDIR := $(ROOTDIR)/ti/build/makerules
+  export MAKERULEDIR
+endif
+include $(MAKERULEDIR)/common.mk
+
+# OBJs and libraries are built by using rule defined in rules_<target>.mk
+#     and need not be explicitly specified here
+
+# Nothing beyond this point
index 9964cc675859b0006bac30ebdb9f27ce3336b861..8be30df39e97ae2f49d11b4c1abc989d9c29cdf1 100644 (file)
@@ -49,7 +49,8 @@
 // TODO - Macros defined within NOT_USE_CSLR to be used until CSLR values for J721E defined
 #if defined(NOT_USE_CSLR)
 
-#define CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CLEC_SRAM_RAMECC_SIZE                         (40U) //TBD
+#define CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CLEC_SRAM_RAMECC_ROW_WIDTH                    (22U)
+#define CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CLEC_SRAM_RAMECC_SIZE                         (5632U)
 
 
 /* ECC Row Widths for MCU Pulsar RAM ID's with Wrapper type
@@ -724,7 +725,8 @@ const SDR_RAMIdEntry_t SDR_ECC_mcuEccAggr0RamIdTable[SDR_MSMC_AGGR0_RAM_ID_TABLE
 const SDR_MemConfig_t SDR_ECC_mainMsmcAggr0MemEntries[SDR_MSMC_AGGR0_WRAPPER_RAM_IDS_TOTAL_ENTRIES] =
 {
     {SDR_ECC_MAIN_MSMC_MEM_WRAPPER_SUBTYPE, 0u,
-         CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CLEC_SRAM_RAMECC_SIZE, 4u, ((bool)false) },
+         CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CLEC_SRAM_RAMECC_SIZE, 4u,
+         CSL_COMPUTE_CLUSTER0_MSMC_ECC_AGGR0_CLEC_SRAM_RAMECC_ROW_WIDTH, ((bool)false) },
 };
 
 /** ----------------------------------------------------------------------------------
index a4228fc83bb94656f6f56ba94869295641d34ceb..2dc7760a902f122ce5f054d94df62d4007763a2a 100644 (file)
@@ -291,7 +291,7 @@ static void SDR_ECC_handleEccAggrEvent (SDR_ECC_MemType eccMemType, uint32_t err
             continue;
         }
 
-        /* Check if this event in triggered, by reading the ECC aggregator status
+        /* Check if this event is triggered, by reading the ECC aggregator status
          * register */
         if (ramIdType == SDR_ECC_RAM_ID_TYPE_WRAPPER) {
             cslResult = CSL_ecc_aggrIsEccRamIntrPending(eccAggrRegs,
@@ -1050,23 +1050,26 @@ SDR_Result SDR_ECC_injectError(SDR_ECC_MemType eccMemType,
             retVal = SDR_ECC_getMemConfig(eccMemType, memSubType, &memConfig);
         }
 
-        if (retVal == SDR_PASS) {
-            if ( ((uintptr_t)pECCErrorConfig->pErrMem) < memConfig.memStartAddr) {
-                retVal = SDR_FAIL;
-            } else {
-                /* Calculate error offset */
-                errAddrOffset =  ((uintptr_t)pECCErrorConfig->pErrMem - memConfig.memStartAddr)
-                                / (memConfig.stride);
+        if ((retVal == SDR_PASS) && (memConfig.readable == true))
+        {
+            if (retVal == SDR_PASS) {
+                if ( ((uintptr_t)pECCErrorConfig->pErrMem) < memConfig.memStartAddr) {
+                    retVal = SDR_FAIL;
+                } else {
+                    /* Calculate error offset */
+                    errAddrOffset =  ((uintptr_t)pECCErrorConfig->pErrMem - memConfig.memStartAddr)
+                                    / (memConfig.stride);
+                }
             }
-        }
 
-        if (retVal == SDR_PASS) {
-            /* Set error Address in ECC Wrapper RAM ID */
-            cslRetval = CSL_ecc_aggrWriteEccRamErrCtrlReg(eccAggrRegs,
-                                                          ramId, 0u,
-                                                          errAddrOffset);
-            if (cslRetval != CSL_PASS) {
-                retVal = SDR_FAIL;
+            if (retVal == SDR_PASS) {
+                /* Set error Address in ECC Wrapper RAM ID */
+                cslRetval = CSL_ecc_aggrWriteEccRamErrCtrlReg(eccAggrRegs,
+                                                              ramId, 0u,
+                                                              errAddrOffset);
+                if (cslRetval != CSL_PASS) {
+                    retVal = SDR_FAIL;
+                }
             }
         }