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raw | patch | inline | side by side (parent: 4bd8bfd)
raw | patch | inline | side by side (parent: 4bd8bfd)
author | Kamath <r-kamath@ti.com> | |
Fri, 16 Oct 2020 09:13:13 +0000 (14:43 +0530) | ||
committer | Sivaraj R <sivaraj@ti.com> | |
Sat, 31 Oct 2020 04:09:47 +0000 (23:09 -0500) |
Signed-off-by: Kamath <r-kamath@ti.com>
diff --git a/packages/ti/board/src/tpr12_evm/TPR12_pinmux_data.c b/packages/ti/board/src/tpr12_evm/TPR12_pinmux_data.c
index ed1fa5a4b125ad2be86d746dcc526a36b3cae489..197f13e3645f0b5fe4431d9cfd6550699e14d6e6 100644 (file)
},
{PINMUX_END}
};
+
+
static pinmuxPerCfg_t gTpr12_mss_gpio8PinCfg[] =
{
- /* MyMSS_GPIO1 -> MSS_GPIO8_PIN -> B3 */
+ /* MyRCSS_GPIO1 -> MSS_GPIO_8 -> U18 FE1 Host Intr*/
{
- CSL_MSS_IOMUX_PADDM_CFG_REG, PIN_MODE(0) | \
+ CSL_MSS_IOMUX_PADCS_CFG_REG, PIN_MODE(3) | \
((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
},
{PINMUX_END}
},
{PINMUX_END}
};
+
+
+
+static pinmuxPerCfg_t gTpr12_mss_gpio18PinCfg[] =
+{
+ /* MyRCSS_GPIO1 -> MSS_GPIO18_PIN -> B15 FE1 NRESET*/
+ {
+ CSL_MSS_IOMUX_PADDW_CFG_REG, PIN_MODE(0) | \
+ ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
+ },
+ {PINMUX_END}
+};
+
+
static pinmuxModuleCfg_t gMss_gpioPinCfg[] =
{
{ 28, TRUE, gTpr12_mss_gpio28PinCfg},
{ 10, TRUE, gTpr12_mss_gpio10PinCfg},
{ 11, TRUE, gTpr12_mss_gpio11PinCfg},
{ 13, TRUE, gTpr12_mss_gpio13PinCfg},
+ { 18, TRUE, gTpr12_mss_gpio18PinCfg},
{PINMUX_END}
};
{PINMUX_END}
};
-static pinmuxPerCfg_t gTpr12_rcss_gpio50PinCfg[] =
-{
- /* MyRCSS_GPIO1 -> RCSS_GPIO50_PIN -> B15 */
- {
- CSL_MSS_IOMUX_PADDW_CFG_REG, PIN_MODE(12) | \
- ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
- },
- {PINMUX_END}
-};
-static pinmuxPerCfg_t gTpr12_rcss_gpio34PinCfg[] =
-{
- /* MyRCSS_GPIO1 -> RCSS_GPIO34_PIN -> U18 */
- {
- CSL_MSS_IOMUX_PADCS_CFG_REG, PIN_MODE(7) | \
- ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION))
- },
- {PINMUX_END}
-};
+
static pinmuxPerCfg_t gTpr12_rcss_gpio48PinCfg[] =
{
/* MyRCSS_GPIO1 -> RCSS_GPIO48_PIN -> C15 */
};
static pinmuxModuleCfg_t gRcss_gpioPinCfg[] =
{
- { 50, TRUE, gTpr12_rcss_gpio50PinCfg},
- { 34, TRUE, gTpr12_rcss_gpio34PinCfg},
{ 48, TRUE, gTpr12_rcss_gpio48PinCfg},
{ 42, TRUE, gTpr12_rcss_gpio42PinCfg},
{ 51, TRUE, gTpr12_rcss_gpio51PinCfg},
index 71dd1d7a4586bd74595ff270e9d75564845e74c1..a6c7059a67bd83df316a62b62e492571e15fdfda 100644 (file)
interruptRegParams.corepacConfig.arg = (uintptr_t)(instIndex);
interruptRegParams.corepacConfig.corepacEventNum = gpioHwAttr->highInterruptNum;
-#if defined(SOC_TPR12) /* All TPR12 interrupts are pulse and not level */
- interruptRegParams.corepacConfig.triggerSensitivity = OSAL_ARM_GIC_TRIG_TYPE_EDGE;
-#endif
#if defined(_TMS320C6X)
interruptRegParams.corepacConfig.intVecNum = OSAL_REGINT_INTVEC_EVENT_COMBINER;
#else
interruptRegParams.corepacConfig.intVecNum = gpioHwAttr->highInterruptNum;
#endif
-
+#if defined(SOC_TPR12) /* All TPR12 interrupts are pulse and not level */
+ interruptRegParams.corepacConfig.triggerSensitivity = OSAL_ARM_GIC_TRIG_TYPE_EDGE;
+#endif
GPIO_osalRegisterInterrupt(&interruptRegParams,&(gGPIOMCB.hwiHandleHigh[instIndex]));
/* Register the Low Priority Interrupt: */
#else
interruptRegParams.corepacConfig.intVecNum = gpioHwAttr->lowInterruptNum;
#endif
-
+#if defined(SOC_TPR12) /* All TPR12 interrupts are pulse and not level */
+ interruptRegParams.corepacConfig.triggerSensitivity = OSAL_ARM_GIC_TRIG_TYPE_EDGE;
+#endif
GPIO_osalRegisterInterrupt(&interruptRegParams,&(gGPIOMCB.hwiHandleLow[instIndex]));
}
}
}
else
{
- /* Output: Set the data direction */
- GPIO_setOutputDataDirection (baseAddr, port, pin, 1U);
-
/* Is the GPIO Port/Pin open open drain? */
if (pinConfig & GPIO_CFG_OUT_OD_NOPULL)
{
/* YES: Open Drain */
GPIO_setOpenDrainStatus (baseAddr, port, pin, 1U);
}
+
+ /* Output: Set the data direction */
+ GPIO_setOutputDataDirection (baseAddr, port, pin, 1U);
+
}
/* Update pinConfig with the latest GPIO configuration */
}
/* Do we need to handle interrupts on both edges? */
- if (pinConfig & GPIO_CFG_IN_INT_BOTH_EDGES)
+ if ((pinConfig & GPIO_CFG_IN_INT_BOTH_EDGES) == GPIO_CFG_IN_INT_BOTH_EDGES)
{
/* YES: Ignore the polarity since interrupts can be triggered on either edge */
GPIO_ignorePolarity (baseAddr, port, pin);
diff --git a/packages/ti/drv/mibspi/soc/dma/v0/MIBSPI_dma.c b/packages/ti/drv/mibspi/soc/dma/v0/MIBSPI_dma.c
index 98f0f3cb6cac4f44951d1c2b58988d89402f1dcc..e1c0810080c5b5d996317e87b24aab74ea639356 100644 (file)
*/
#include <string.h>
+#include <ti/csl/soc.h>
#include <ti/drv/mibspi/MIBSPI.h>
#include <ti/drv/mibspi/src/mibspi_priv.h>
#include <ti/drv/mibspi/src/mibspi_utils.h>
else
{
/* destinationAddress is address of memory location named buffer.*/
- rxParamSet->paramSetConfig.destinationAddress = (uintptr_t)(&ptrMibSpiDriver->rxScratchBuffer);
+ rxParamSet->paramSetConfig.destinationAddress = CSL_locToGlobAddr((uintptr_t)(&ptrMibSpiDriver->rxScratchBuffer));
}
Mibspi_assert(xferSizeInfo->elemSize <= 2);
else
{
/* sourceAddress holds address of memory location buffer. */
- txParamSet->paramSetConfig.sourceAddress = (uintptr_t) &ptrMibSpiDriver->txScratchBuffer;
+ txParamSet->paramSetConfig.sourceAddress = CSL_locToGlobAddr((uintptr_t) &ptrMibSpiDriver->txScratchBuffer);
}
/* destinationAddress holds address of SPIDAT1 register. */
txParamSet->paramSetConfig.destinationAddress = xferAddrInfo->daddr;
else
{
/* Source address */
- rxParamSet->paramSetConfig.destinationAddress = (uintptr_t) &ptrMibSpiDriver->rxScratchBuffer;
+ rxParamSet->paramSetConfig.destinationAddress = CSL_locToGlobAddr((uintptr_t) &ptrMibSpiDriver->rxScratchBuffer);
}
/* aCount holds the number of bytes in an array.*/
}
else
{
- txParamSet->paramSetConfig.sourceAddress = (uintptr_t)(&ptrMibSpiDriver->txScratchBuffer);
+ txParamSet->paramSetConfig.sourceAddress = CSL_locToGlobAddr((uintptr_t)(&ptrMibSpiDriver->txScratchBuffer));
}
/* destinationAddress holds address of SPIDAT1 register. */
index 87b0dd477783e44cc78942138d97d85483a88ecc..ca2ab9ede5e5fcd45c286bd7b0dea7465668fac2 100644 (file)
CSL_FINS(regVal, SPI_SPIPC0_CLKFUN, 1U);
CSL_FINS(regVal, SPI_SPIPC0_SIMOFUN0, 1U);
CSL_FINS(regVal, SPI_SPIPC0_SOMIFUN0, 1U);
+
+ //CSL_FINS(regVal, SPI_SPIPC0_SOMIFUN, 0U);
+ //CSL_FINS(regVal, SPI_SPIPC0_SOMIFUN, 0U);
ptrMibSpiReg->SPIPC0 = regVal; /* enable SOMI */
break;
/* Case 1: SrcData=NULL, DstData!=NULL => Read data from SPI with dummy write */
dmaXferInfo.dmaReqLine = group;
- dmaXferInfo.tx.saddr = MibspiUtils_virtToPhy(srcData);
+ if (srcData != NULL)
+ {
+ dmaXferInfo.tx.saddr = MibspiUtils_virtToPhy(srcData);
+ }
+ else
+ {
+ dmaXferInfo.tx.saddr = NULL;
+ }
dmaXferInfo.tx.daddr = MibspiUtils_virtToPhy((const void *)txRAMAddr);
dmaXferInfo.rx.saddr = MibspiUtils_virtToPhy((const void *)rxRAMAddr);
- dmaXferInfo.rx.daddr = MibspiUtils_virtToPhy(dstData);
+ if (dstData != NULL)
+ {
+ dmaXferInfo.rx.daddr = MibspiUtils_virtToPhy(dstData);
+ }
+ else
+ {
+ dmaXferInfo.rx.daddr = NULL;
+ }
if(ptrMibSpiDriver->params.dataSize == 8U)
{
dmaXferInfo.size.elemSize = 1;