PDK-6948: Board: Added ICSS MII pinmux support for am64x evm
authorM V Pratap Reddy <x0257344@ti.com>
Fri, 27 Nov 2020 09:44:59 +0000 (15:14 +0530)
committerM V Pratap Reddy <x0257344@ti.com>
Fri, 27 Nov 2020 09:44:59 +0000 (15:14 +0530)
packages/ti/board/src/am64x_evm/AM64x_pinmux.h
packages/ti/board/src/am64x_evm/AM64x_pinmux_data_icssMII.c [new file with mode: 0644]
packages/ti/board/src/am64x_evm/am64x_evm_icss.syscfg [new file with mode: 0644]
packages/ti/board/src/am64x_evm/board_pinmux.c
packages/ti/board/src/am64x_evm/include/board_internal.h
packages/ti/board/src/am64x_evm/include/board_pinmux.h
packages/ti/board/src/am64x_evm/src_files_am64x_evm.mk
packages/ti/build/makerules/rules_ti_cgt_arm.mk

index 98d176dcc1ed40229aaf7bdc07f0cc79dc880b61..f3ab4b0a241df168a5222ffdab5321a4da3af135 100755 (executable)
@@ -177,6 +177,7 @@ enum pinMainOffsets
        PIN_PRG1_PRU0_GPO3               = 0x00C4,\r
        PIN_PRG1_PRU0_GPO6               = 0x00D0,\r
        PIN_PRG1_PRU0_GPO4               = 0x00C8,\r
+       PIN_PRG1_PRU0_GPO8               = 0x00D8,\r
        PIN_PRG1_PRU0_GPO11              = 0x00E4,\r
        PIN_PRG1_PRU0_GPO12              = 0x00E8,\r
        PIN_PRG1_PRU0_GPO13              = 0x00EC,\r
@@ -267,6 +268,7 @@ enum pinWkupOffsets
            Pinmux tool. */\r
 extern pinmuxBoardCfg_t gAM64x_MainPinmuxData[];\r
 extern pinmuxBoardCfg_t gAM64x_WkupPinmuxData[];\r
+extern pinmuxBoardCfg_t gAM64x_MainPinmuxDataIcssMII[];\r
 \r
 #ifdef __cplusplus\r
 }\r
diff --git a/packages/ti/board/src/am64x_evm/AM64x_pinmux_data_icssMII.c b/packages/ti/board/src/am64x_evm/AM64x_pinmux_data_icssMII.c
new file mode 100644 (file)
index 0000000..408a751
--- /dev/null
@@ -0,0 +1,204 @@
+/**
+* Note: This file was auto-generated by TI PinMux on 11/27/2020 at 10:24:11 AM.
+*
+* \file  AM64x_pinmux_data.c
+*
+* \brief  This file contains the pin mux configurations for the boards.
+*         These are prepared based on how the peripherals are extended on
+*         the boards.
+*
+* \copyright Copyright (CU) 2020 Texas Instruments Incorporated -
+*             http://www.ti.com/
+*/
+
+/* ========================================================================== */
+/*                             Include Files                                  */
+/* ========================================================================== */
+
+#include "AM64x_pinmux.h"
+
+/** Peripheral Pin Configurations */
+
+
+static pinmuxPerCfg_t gPru_icssg1_mii_g_rt0PinCfg[] =
+{
+    /* MyPRU_ICSSG1_MII_G_RT1 -> PR1_MII_MT0_CLK -> V9 */
+    {
+        PIN_PRG1_PRU0_GPO16, PIN_MODE(1) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyPRU_ICSSG1_MII_G_RT1 -> PR1_MII0_TXEN -> Y9 */
+    {
+        PIN_PRG1_PRU0_GPO15, PIN_MODE(0) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
+    },
+    /* MyPRU_ICSSG1_MII_G_RT1 -> PR1_MII0_TXD3 -> AA9 */
+    {
+        PIN_PRG1_PRU0_GPO14, PIN_MODE(0) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
+    },
+    /* MyPRU_ICSSG1_MII_G_RT1 -> PR1_MII0_TXD2 -> W9 */
+    {
+        PIN_PRG1_PRU0_GPO13, PIN_MODE(0) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
+    },
+    /* MyPRU_ICSSG1_MII_G_RT1 -> PR1_MII0_TXD1 -> U9 */
+    {
+        PIN_PRG1_PRU0_GPO12, PIN_MODE(0) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
+    },
+    /* MyPRU_ICSSG1_MII_G_RT1 -> PR1_MII0_TXD0 -> AA8 */
+    {
+        PIN_PRG1_PRU0_GPO11, PIN_MODE(0) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
+    },
+    /* MyPRU_ICSSG1_MII_G_RT1 -> PR1_MII0_RXDV -> Y8 */
+    {
+        PIN_PRG1_PRU0_GPO4, PIN_MODE(1) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyPRU_ICSSG1_MII_G_RT1 -> PR1_MII_MR0_CLK -> AA7 */
+    {
+        PIN_PRG1_PRU0_GPO6, PIN_MODE(1) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyPRU_ICSSG1_MII_G_RT1 -> PR1_MII0_RXD3 -> V8 */
+    {
+        PIN_PRG1_PRU0_GPO3, PIN_MODE(1) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyPRU_ICSSG1_MII_G_RT1 -> PR1_MII0_RXD2 -> W8 */
+    {
+        PIN_PRG1_PRU0_GPO2, PIN_MODE(1) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyPRU_ICSSG1_MII_G_RT1 -> PR1_MII0_CRS -> U14 */
+    {
+        PIN_PRG1_PRU0_GPO10, PIN_MODE(1) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyPRU_ICSSG1_MII_G_RT1 -> PR1_MII0_RXER -> V13 */
+    {
+        PIN_PRG1_PRU0_GPO5, PIN_MODE(1) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyPRU_ICSSG1_MII_G_RT1 -> PR1_MII0_RXD1 -> U8 */
+    {
+        PIN_PRG1_PRU0_GPO1, PIN_MODE(1) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyPRU_ICSSG1_MII_G_RT1 -> PR1_MII0_RXD0 -> Y7 */
+    {
+        PIN_PRG1_PRU0_GPO0, PIN_MODE(1) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyPRU_ICSSG1_MII_G_RT1 -> PR1_MII0_COL -> U15 */
+    {
+        PIN_PRG1_PRU0_GPO9, PIN_MODE(1) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyPRU_ICSSG1_MII_G_RT1 -> PR1_MII0_RXLINK -> W13 */
+    {
+        PIN_PRG1_PRU0_GPO8, PIN_MODE(1) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyPRU_ICSSG1_MII_G_RT1 -> PR1_MII_MT1_CLK -> Y10 */
+    {
+        PIN_PRG1_PRU1_GPO16, PIN_MODE(1) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyPRU_ICSSG1_MII_G_RT1 -> PR1_MII1_TXEN -> Y11 */
+    {
+        PIN_PRG1_PRU1_GPO15, PIN_MODE(0) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
+    },
+    /* MyPRU_ICSSG1_MII_G_RT1 -> PR1_MII1_TXD3 -> AA11 */
+    {
+        PIN_PRG1_PRU1_GPO14, PIN_MODE(0) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
+    },
+    /* MyPRU_ICSSG1_MII_G_RT1 -> PR1_MII1_TXD2 -> U10 */
+    {
+        PIN_PRG1_PRU1_GPO13, PIN_MODE(0) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
+    },
+    /* MyPRU_ICSSG1_MII_G_RT1 -> PR1_MII1_TXD1 -> V10 */
+    {
+        PIN_PRG1_PRU1_GPO12, PIN_MODE(0) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
+    },
+    /* MyPRU_ICSSG1_MII_G_RT1 -> PR1_MII1_TXD0 -> AA10 */
+    {
+        PIN_PRG1_PRU1_GPO11, PIN_MODE(0) | \
+        ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))
+    },
+    /* MyPRU_ICSSG1_MII_G_RT1 -> PR1_MII1_RXDV -> W12 */
+    {
+        PIN_PRG1_PRU1_GPO4, PIN_MODE(1) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyPRU_ICSSG1_MII_G_RT1 -> PR1_MII_MR1_CLK -> U11 */
+    {
+        PIN_PRG1_PRU1_GPO6, PIN_MODE(1) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyPRU_ICSSG1_MII_G_RT1 -> PR1_MII1_RXD3 -> Y12 */
+    {
+        PIN_PRG1_PRU1_GPO3, PIN_MODE(1) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyPRU_ICSSG1_MII_G_RT1 -> PR1_MII1_RXD2 -> AA12 */
+    {
+        PIN_PRG1_PRU1_GPO2, PIN_MODE(1) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyPRU_ICSSG1_MII_G_RT1 -> PR1_MII1_CRS -> W14 */
+    {
+        PIN_PRG1_PRU1_GPO10, PIN_MODE(1) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyPRU_ICSSG1_MII_G_RT1 -> PR1_MII1_RXER -> AA13 */
+    {
+        PIN_PRG1_PRU1_GPO5, PIN_MODE(1) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyPRU_ICSSG1_MII_G_RT1 -> PR1_MII1_RXD1 -> V11 */
+    {
+        PIN_PRG1_PRU1_GPO1, PIN_MODE(1) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyPRU_ICSSG1_MII_G_RT1 -> PR1_MII1_RXD0 -> W11 */
+    {
+        PIN_PRG1_PRU1_GPO0, PIN_MODE(1) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyPRU_ICSSG1_MII_G_RT1 -> PR1_MII1_COL -> V14 */
+    {
+        PIN_PRG1_PRU1_GPO9, PIN_MODE(1) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    /* MyPRU_ICSSG1_MII_G_RT1 -> PR1_MII1_RXLINK -> U12 */
+    {
+        PIN_PRG1_PRU1_GPO8, PIN_MODE(1) | \
+        ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))
+    },
+    {PINMUX_END}
+};
+
+static pinmuxModuleCfg_t gPru_icssg1_mii_g_rtPinCfg[] =
+{
+    {0, TRUE, gPru_icssg1_mii_g_rt0PinCfg},
+    {PINMUX_END}
+};
+
+
+pinmuxBoardCfg_t gAM64x_MainPinmuxDataIcssMII[] =
+{
+    {0, gPru_icssg1_mii_g_rtPinCfg},
+    {PINMUX_END}
+};
+
+pinmuxBoardCfg_t gAM64x_WkupPinmuxDataIcssMII[] =
+{
+    {PINMUX_END}
+};
diff --git a/packages/ti/board/src/am64x_evm/am64x_evm_icss.syscfg b/packages/ti/board/src/am64x_evm/am64x_evm_icss.syscfg
new file mode 100644 (file)
index 0000000..f57f8c1
--- /dev/null
@@ -0,0 +1,45 @@
+/**
+ * These arguments were used when this file was generated. They will be automatically applied on subsequent loads
+ * via the GUI or CLI. Run CLI with '--help' for additional information on how to override these arguments.
+ * @cliArgs --device "AM64x_beta" --package "ALV" --part "Default"
+ * @versions {"data":"20201908","timestamp":"2020110405","tool":"1.6.0+1543","templates":"20190604"}
+ */
+
+/**
+ * These are the peripherals and settings in this configuration
+ */
+const iPRU_ICSSG1_MII_G_RT1               = scripting.addPeripheral("PRU_ICSSG1_MII_G_RT");
+iPRU_ICSSG1_MII_G_RT1.$name               = "MyPRU_ICSSG1_MII_G_RT1";
+iPRU_ICSSG1_MII_G_RT1.$assign             = "PRU_ICSSG1_MII_G_RT";
+iPRU_ICSSG1_MII_G_RT1.MII_MT0_CLK.$assign = "PRG1_PRU0_GPO16";
+iPRU_ICSSG1_MII_G_RT1.MII0_TXEN.$assign   = "PRG1_PRU0_GPO15";
+iPRU_ICSSG1_MII_G_RT1.MII0_TXD3.$assign   = "PRG1_PRU0_GPO14";
+iPRU_ICSSG1_MII_G_RT1.MII0_TXD2.$assign   = "PRG1_PRU0_GPO13";
+iPRU_ICSSG1_MII_G_RT1.MII0_TXD1.$assign   = "PRG1_PRU0_GPO12";
+iPRU_ICSSG1_MII_G_RT1.MII0_TXD0.$assign   = "PRG1_PRU0_GPO11";
+iPRU_ICSSG1_MII_G_RT1.MII0_RXDV.$assign   = "PRG1_PRU0_GPO4";
+iPRU_ICSSG1_MII_G_RT1.MII_MR0_CLK.$assign = "PRG1_PRU0_GPO6";
+iPRU_ICSSG1_MII_G_RT1.MII0_RXD3.$assign   = "PRG1_PRU0_GPO3";
+iPRU_ICSSG1_MII_G_RT1.MII0_RXD2.$assign   = "PRG1_PRU0_GPO2";
+iPRU_ICSSG1_MII_G_RT1.MII0_CRS.$assign    = "PRG1_PRU0_GPO10";
+iPRU_ICSSG1_MII_G_RT1.MII0_RXER.$assign   = "PRG1_PRU0_GPO5";
+iPRU_ICSSG1_MII_G_RT1.MII0_RXD1.$assign   = "PRG1_PRU0_GPO1";
+iPRU_ICSSG1_MII_G_RT1.MII0_RXD0.$assign   = "PRG1_PRU0_GPO0";
+iPRU_ICSSG1_MII_G_RT1.MII0_COL.$assign    = "PRG1_PRU0_GPO9";
+iPRU_ICSSG1_MII_G_RT1.MII0_RXLINK.$assign = "PRG1_PRU0_GPO8";
+iPRU_ICSSG1_MII_G_RT1.MII_MT1_CLK.$assign = "PRG1_PRU1_GPO16";
+iPRU_ICSSG1_MII_G_RT1.MII1_TXEN.$assign   = "PRG1_PRU1_GPO15";
+iPRU_ICSSG1_MII_G_RT1.MII1_TXD3.$assign   = "PRG1_PRU1_GPO14";
+iPRU_ICSSG1_MII_G_RT1.MII1_TXD2.$assign   = "PRG1_PRU1_GPO13";
+iPRU_ICSSG1_MII_G_RT1.MII1_TXD1.$assign   = "PRG1_PRU1_GPO12";
+iPRU_ICSSG1_MII_G_RT1.MII1_TXD0.$assign   = "PRG1_PRU1_GPO11";
+iPRU_ICSSG1_MII_G_RT1.MII1_RXDV.$assign   = "PRG1_PRU1_GPO4";
+iPRU_ICSSG1_MII_G_RT1.MII_MR1_CLK.$assign = "PRG1_PRU1_GPO6";
+iPRU_ICSSG1_MII_G_RT1.MII1_RXD3.$assign   = "PRG1_PRU1_GPO3";
+iPRU_ICSSG1_MII_G_RT1.MII1_RXD2.$assign   = "PRG1_PRU1_GPO2";
+iPRU_ICSSG1_MII_G_RT1.MII1_CRS.$assign    = "PRG1_PRU1_GPO10";
+iPRU_ICSSG1_MII_G_RT1.MII1_RXER.$assign   = "PRG1_PRU1_GPO5";
+iPRU_ICSSG1_MII_G_RT1.MII1_RXD1.$assign   = "PRG1_PRU1_GPO1";
+iPRU_ICSSG1_MII_G_RT1.MII1_RXD0.$assign   = "PRG1_PRU1_GPO0";
+iPRU_ICSSG1_MII_G_RT1.MII1_COL.$assign    = "PRG1_PRU1_GPO9";
+iPRU_ICSSG1_MII_G_RT1.MII1_RXLINK.$assign = "PRG1_PRU1_GPO8";
index c290da5a18e0fe13dc37e41bdca36e03fe11af11..43b7b483e28e7b89c7207be402f58d5d148d444c 100644 (file)
 #define BOARD_UART_TX_LOCK_KICK_ADDR        (MAIN_PADCONFIG_CTRL_BASE + \\r
                                                  CSL_MAIN_PADCFG_CTRL_MMR_CFG0_LOCK1_KICK0)\r
 \r
+static Board_PinmuxConfig_t gBoardPinmuxCfg = {BOARD_PINMUX_DEFAULT,\r
+                                               BOARD_PINMUX_ICSS_RGMII,\r
+                                               0};\r
 \r
-Board_STATUS Board_pinmuxConfig (void)\r
+/**\r
+ *  \brief  Gets base address of padconfig registers\r
+ *\r
+ *  \param   domain [IN]  SoC domain for pinmux\r
+ *  \n                     BOARD_SOC_DOMAIN_MAIN - Main domain\r
+ *  \n                     BOARD_SOC_DOMAIN_MCU  - MCU domain\r
+ *\r
+ *  \return   Valid address in case success or 0 in case of failure\r
+ */\r
+static uint32_t Board_pinmuxGetBaseAddr(uint8_t domain)\r
 {\r
+    uint32_t baseAddr;\r
 \r
-    Board_unlockMMR();\r
+    switch(domain)\r
+    {\r
+        case BOARD_SOC_DOMAIN_MAIN:\r
+            baseAddr = BOARD_MAIN_PMUX_CTRL;\r
+        break;\r
+        case BOARD_SOC_DOMAIN_MCU:\r
+            baseAddr = BOARD_WKUP_PMUX_CTRL;\r
+        break;\r
+        default:\r
+            baseAddr = 0;\r
+        break;\r
+    }\r
+\r
+    return baseAddr;\r
+}\r
+\r
+/**\r
+ *  \brief Sets the board pinmux configuration.\r
+ *\r
+ *  This API allows to change the default pinmux configurations\r
+ *  in the board library.\r
+ *\r
+ *  \n Usage:\r
+ *  \n - Call Board_pinmuxGetCfg to get default pinmux config\r
+ *  \n - Call Board_pinmuxSetCfg to change pinmux config\r
+ *  \n - Call Board_init with pinmux flag to apply the updated pinmux config\r
+ *\r
+ *  \param   pinmuxCfg [IN]  Pinmux configurations\r
+ *\r
+ *  \return  BOARD_SOK in case of success or appropriate error code\r
+ *\r
+ */\r
+Board_STATUS Board_pinmuxSetCfg(Board_PinmuxConfig_t *pinmuxCfg)\r
+{\r
+    gBoardPinmuxCfg = *pinmuxCfg;\r
+\r
+    return BOARD_SOK;\r
+}\r
+\r
+/**\r
+ *  \brief Gets the board pinmux configuration.\r
+ *\r
+ *  \param   pinmuxCfg [IN]  Pinmux configurations\r
+ *\r
+ *  \return  BOARD_SOK in case of success or appropriate error code\r
+ *\r
+ */\r
+Board_STATUS Board_pinmuxGetCfg(Board_PinmuxConfig_t *pinmuxCfg)\r
+{\r
+    *pinmuxCfg = gBoardPinmuxCfg;\r
+\r
+    return BOARD_SOK;\r
+}\r
 \r
-    pinmuxModuleCfg_t* pModuleData = NULL;\r
-    pinmuxPerCfg_t* pInstanceData = NULL;\r
+/**\r
+ * \brief  Board pinmuxing update function\r
+ *\r
+ * Provides the option to configure/update the pinmux.\r
+ * This function can be used to change the pinmux set by\r
+ * Board_init by default.\r
+ *\r
+ * \param   pinmuxData [IN]  Pinmux data structure\r
+ * \param   domain     [IN]  SoC domain for pinmux\r
+ *  \n                        BOARD_SOC_DOMAIN_MAIN - Main domain\r
+ *  \n                        BOARD_SOC_DOMAIN_MCU - MCU domain\r
+ *\r
+ * \return  BOARD_SOK in case of success or appropriate error code\r
+ *\r
+ */\r
+Board_STATUS Board_pinmuxUpdate (pinmuxBoardCfg_t *pinmuxData,\r
+                                 uint32_t domain)\r
+{\r
+    pinmuxModuleCfg_t *pModuleData = NULL;\r
+    pinmuxPerCfg_t *pInstanceData = NULL;\r
     int32_t i, j, k;\r
+    uint32_t baseAddr;\r
+    Board_STATUS status = BOARD_SOK;\r
 \r
-    for(i = 0; PINMUX_END != gAM64x_MainPinmuxData[i].moduleId; i++)\r
+    Board_unlockMMR();\r
+\r
+    baseAddr = Board_pinmuxGetBaseAddr(domain);\r
+    if(baseAddr != 0)\r
     {\r
-        pModuleData = gAM64x_MainPinmuxData[i].modulePinCfg;\r
-        for(j = 0; (PINMUX_END != pModuleData[j].modInstNum); j++)\r
+        for(i = 0; PINMUX_END != pinmuxData[i].moduleId; i++)\r
         {\r
-            if(pModuleData[j].doPinConfig == TRUE)\r
+            pModuleData = pinmuxData[i].modulePinCfg;\r
+            for(j = 0; (PINMUX_END != pModuleData[j].modInstNum); j++)\r
             {\r
-                pInstanceData = pModuleData[j].instPins;\r
-                for(k = 0; (PINMUX_END != pInstanceData[k].pinOffset); k++)\r
+                if(pModuleData[j].doPinConfig == TRUE)\r
                 {\r
-                    HW_WR_REG32((MAIN_PADCONFIG_CTRL_BASE + 0x4000 + pInstanceData[k].pinOffset),\r
-                                (pInstanceData[k].pinSettings));\r
+                    pInstanceData = pModuleData[j].instPins;\r
+                    for(k = 0; (PINMUX_END != pInstanceData[k].pinOffset); k++)\r
+                    {\r
+                        HW_WR_REG32((baseAddr + pInstanceData[k].pinOffset),\r
+                                    (pInstanceData[k].pinSettings));\r
+                    }\r
                 }\r
             }\r
         }\r
     }\r
+    else\r
+    {\r
+        status = BOARD_INVALID_PARAM;\r
+    }\r
+\r
+    Board_lockMMR();\r
+\r
+    return status;\r
+}\r
+\r
+/**\r
+ * \brief  Board pinmuxing enable function\r
+ *\r
+ * Enables pinmux for the board interfaces. Pin mux is done based\r
+ * on the default/primary functionality of the board. Any pins shared by\r
+ * multiple interfaces need to be reconfigured to access the secondary\r
+ * functionality.\r
+ *\r
+ * \param   void\r
+ *\r
+ * \return  BOARD_SOK in case of success or appropriate error code\r
+ *\r
+ */\r
+Board_STATUS Board_pinmuxConfig (void)\r
+{\r
+    Board_STATUS status = BOARD_SOK;\r
+\r
+    Board_pinmuxUpdate(gAM64x_MainPinmuxData,\r
+                       BOARD_SOC_DOMAIN_MAIN);\r
+    Board_pinmuxUpdate(gAM64x_WkupPinmuxData,\r
+                       BOARD_SOC_DOMAIN_MCU);\r
 \r
-       for(i = 0; PINMUX_END != gAM64x_WkupPinmuxData[i].moduleId; i++)\r
+    /* Note: EVM Specific config.\r
+     * Code below be removed for custom boards */\r
+    if(gBoardPinmuxCfg.muxCfg == BOARD_PINMUX_CUSTOM)\r
     {\r
-        pModuleData = gAM64x_WkupPinmuxData[i].modulePinCfg;\r
-        for(j = 0; (PINMUX_END != pModuleData[j].modInstNum); j++)\r
+        if(gBoardPinmuxCfg.icssMux == BOARD_PINMUX_ICSS_MII)\r
         {\r
-            if(pModuleData[j].doPinConfig == TRUE)\r
-            {\r
-                pInstanceData = pModuleData[j].instPins;\r
-                for(k = 0; (PINMUX_END != pInstanceData[k].pinOffset); k++)\r
-                {\r
-                    HW_WR_REG32((MCU_PADCONFIG_CTRL_BASE + 0x4000 + pInstanceData[k].pinOffset),\r
-                                 (pInstanceData[k].pinSettings));\r
-                }\r
-            }\r
+            Board_pinmuxUpdate(gAM64x_MainPinmuxDataIcssMII,\r
+                               BOARD_SOC_DOMAIN_MAIN);\r
         }\r
     }\r
 \r
-    Board_lockMMR();\r
-    return BOARD_SOK;\r
+    return status;\r
 }\r
 \r
 void Board_uartTxPinmuxConfig(void)\r
@@ -125,35 +240,6 @@ void Board_uartTxPinmuxConfig(void)
     HW_WR_REG32(BOARD_UART_TX_LOCK_KICK_ADDR, 0);\r
 }\r
 \r
-/**\r
- *  \brief  Gets base address of padconfig registers\r
- *\r
- *  \param   domain [IN]  SoC domain for pinmux\r
- *  \n                     BOARD_SOC_DOMAIN_MAIN - Main domain\r
- *  \n                     BOARD_SOC_DOMAIN_MCU  - MCU domain\r
- *\r
- *  \return   Valid address in case success or 0 in case of failure\r
- */\r
-static uint32_t Board_pinmuxGetBaseAddr(uint8_t domain)\r
-{\r
-    uint32_t baseAddr;\r
-\r
-    switch(domain)\r
-    {\r
-        case BOARD_SOC_DOMAIN_MAIN:\r
-            baseAddr = BOARD_MAIN_PMUX_CTRL;\r
-        break;\r
-        case BOARD_SOC_DOMAIN_MCU:\r
-            baseAddr = BOARD_WKUP_PMUX_CTRL;\r
-        break;\r
-        default:\r
-            baseAddr = 0;\r
-        break;\r
-    }\r
-\r
-    return baseAddr;\r
-}\r
-\r
 /**\r
  *  \brief Sets padconfig register of a pin at given offset\r
  *\r
index 4971b06e2ccabca7c4cec2ff99a7c357ff5bb8e5..1165d125b8b3d719610be9f1eef15f9176b8577f 100644 (file)
@@ -70,13 +70,65 @@ extern "C" {
 #define PINMUX_BIT_MASK                      (0xFFF8FFF0U)\r
 #define GPIO_PIN_MUX_CFG                     (0x50007U)\r
 \r
-#define BOARD_PADCFG_PMUX_OFFSET             (0x4000)\r
+#ifdef BUILD_M4F\r
+#define BOARD_PADCFG_PMUX_OFFSET             (0x4000U + 0x60000000U)\r
+#else\r
+#define BOARD_PADCFG_PMUX_OFFSET             (0x4000U)\r
+#endif\r
+\r
 /* MAIN CTRL pinmux base address */\r
 #define BOARD_MAIN_PMUX_CTRL                (CSL_PADCFG_CTRL0_CFG0_BASE + BOARD_PADCFG_PMUX_OFFSET)\r
 \r
 /* WKUP CTRL pinmux base address */\r
 #define BOARD_WKUP_PMUX_CTRL                 (CSL_MCU_PADCFG_CTRL0_CFG0_BASE + BOARD_PADCFG_PMUX_OFFSET)\r
 \r
+\r
+/* Ethenet board library MACROs */\r
+#define BOARD_ETHPHY_PHYID1_REG_ADDR            (0x2U)\r
+#define BOARD_ETHPHY_PHYID2_REG_ADDR            (0x3U)\r
+#define BOARD_ETHPHY_REGCR_REG_ADDR             (0xDU)\r
+#define BOARD_ETHPHY_REGCR_ADDR_EN              (0x1FU)\r
+#define BOARD_ETHPHY_REGCR_DATA_EN              (0x401FU)\r
+#define BOARD_ETHPHY_ADDAR_REG_ADDR             (0xEU)\r
+\r
+#define BOARD_ETHPHY_LEDCR1_REG_ADDR            (0x18U)\r
+\r
+#define BOARD_ETHPHY_FLD_THRESH_REG_ADDR        (0x2EU)\r
+\r
+#define BOARD_ETHPHY_RGMIICTL_REG_ADDR          (0x32U)\r
+#define BOARD_ETHPHY_RGMIICTL_CLKDELAY_MASK     (0x3U)\r
+#define BOARD_ETHPHY_RGMIICTL_TXDELAY_EN        (0x2U)\r
+#define BOARD_ETHPHY_RGMIICTL_RXDELAY_EN        (0x1U)\r
+\r
+#define BOARD_ETHPHY_STRAP_STS1_REG_ADDR        (0x6EU)\r
+#define BOARD_ETHPHY_STRAP_STS2_REG_ADDR        (0x6FU)\r
+\r
+#define BOARD_ETHPHY_RGMIIDCTL_REG_ADDR         (0x86U)\r
+\r
+#define BOARD_ETHPHY_GPIO_MUX_CTRL2_REG_ADDR    (0x172U)\r
+\r
+#define BOARD_ETHPHY_GPIO_MUX_CFG_REG_ADDR      (0x170U)\r
+\r
+#define BOARD_ETHPHY_GPIO_MUX_CTRL2_REG_MASK    (0xFU)\r
+#define BOARD_ETHPHY_GPIO_MUX_CTRL2_REG_CFG     (0x6U)\r
+\r
+#define BOARD_ETHPHY_LEDCR1_REG_MASK            (0xF000U)\r
+#define BOARD_ETHPHY_LEDCR1_REG_CFG             (0x8000U)\r
+\r
+#define BOARD_ETHPHY_ICSSG_DELAY                (0xA9U)\r
+#define BOARD_ETHPHY_CPSW9G_DELAY               (0xA9U)\r
+#define BOARD_ETHPHY_CPSW2G_DELAY               (0x77U)\r
+#define BOARD_ETHPHY_DELAY_CTRL                 (0xD3U)\r
+#define BOARD_ETHPHY_IO_IMPEDANCE               (0x0C1FU)\r
+#define BOARD_CPSW_MDIO_REG_OFFSET              (0xF00U)\r
+\r
+#define BOARD_MDIO_CTRL_REG_OFFSET              (0x4U)\r
+#define BOARD_MDIO_CLK_DIV_CFG                  (0xFFU)\r
+#define BOARD_EMAC_DELAY_CFG                    (0x01000000U)\r
+\r
+#define BOARD_ETHPHY_STRAP_FLD_MASK             (0x0400U)\r
+#define BOARD_ETHPHY_STRAP_FLD_THS_CHECK_FLAG   (0x222U)\r
+\r
 /*****************************************************************************\r
  * Internal Objects                                                          *\r
  *****************************************************************************/\r
index 689d90b266316bb3143a5c38659456a60d6fda12..07d577502a5efee24465e0c8cface3f130f1f1dc 100644 (file)
@@ -52,12 +52,125 @@ extern "C" {
 \r
 #define BOARD_GPIO_PIN_MUX_CFG         (0x50007U)\r
 \r
+#define BOARD_PINMUX_ICSS_RGMII            (0U)  /* Default */\r
+#define BOARD_PINMUX_ICSS_MII              (1U)\r
+\r
+#define BOARD_PINMUX_CUSTOM                (0)\r
+#define BOARD_PINMUX_DEFAULT               (1U)   /* Default */\r
+\r
+/* Structure to set the board pinmux configuration */\r
+typedef struct Board_PinmuxConfig_s\r
+{\r
+    /**\r
+     * Pinmux config control\r
+     *  BOARD_PINMUX_CUSTOM(0) - Pinmux is based custom pinmux config set from apps\r
+     *  BOARD_PINMUX_DEFAULT(1) - Pinmux is based on default board pinmux config\r
+     */\r
+    uint8_t muxCfg;\r
+\r
+    /**\r
+     * Pinmux config control for ICSS interface\r
+     *  BOARD_PINMUX_ICSS_RGMII(0) - Enables ICSS RGMII mode\r
+     *  BOARD_PINMUX_ICSS_MII(1) - Enables ICSS MII mode\r
+     */\r
+    uint8_t icssMux;\r
+\r
+    /**\r
+     * Pinmux config control for application cards\r
+     *  Note in use.\r
+     *  Placeholder in case specific pinmux is needed for expansion boards.\r
+     */\r
+    uint8_t expBoardMux;\r
+\r
+} Board_PinmuxConfig_t;\r
+\r
 /* ========================================================================== */\r
 /*                         Structures and Enums                               */\r
 /* ========================================================================== */\r
 \r
 void Board_uartTxPinmuxConfig(void);\r
 \r
+/**\r
+ *  \brief Sets padconfig register of a pin at given offset\r
+ *\r
+ *  Configures whole padconfig register of the pin at given offset\r
+ *  with the value in 'muxData'.\r
+ *\r
+ *  \param   domain  [IN]  SoC domain for pinmux\r
+ *  \n                      BOARD_SOC_MAIN_DOMAIN - Main domain\r
+ *  \n                      BOARD_SOC_MCU_DOMAIN - MCU domain\r
+ *\r
+ *  \param   offset  [IN]  Pad config offset of the pin\r
+ *  \param   muxData [IN]  Value to be written to padconfig register\r
+ *\r
+ *  \return   BOARD_SOK in case of success or appropriate error code\r
+ *\r
+ */\r
+Board_STATUS Board_pinmuxSetReg(uint8_t  domain,\r
+                                uint32_t offset,\r
+                                uint32_t muxData);\r
+\r
+/**\r
+ *  \brief Sets the board pinmux configuration.\r
+ *\r
+ *  This API allows to change the default pinmux configurations\r
+ *  in the board library.\r
+ *\r
+ *  \n Usage:\r
+ *  \n - Call Board_pinmuxGetCfg to get default pinmux config\r
+ *  \n - Call Board_pinmuxSetCfg to change pinmux config\r
+ *  \n - Call Board_init with pinmux flag to apply the updated pinmux config\r
+ *\r
+ *  \param   pinmuxCfg [IN]  Pinmux configurations\r
+ *\r
+ *  \return  BOARD_SOK in case of success or appropriate error code\r
+ *\r
+ */\r
+Board_STATUS Board_pinmuxSetCfg(Board_PinmuxConfig_t *pinmuxCfg);\r
+\r
+/**\r
+ *  \brief Gets the board pinmux configuration.\r
+ *\r
+ *  \param   pinmuxCfg [IN]  Pinmux configurations\r
+ *\r
+ *  \return  BOARD_SOK in case of success or appropriate error code\r
+ *\r
+ */\r
+Board_STATUS Board_pinmuxGetCfg(Board_PinmuxConfig_t *pinmuxCfg);\r
+\r
+/**\r
+ * \brief  Board pinmuxing update function\r
+ *\r
+ * Provides the option to configure/update the pinmux.\r
+ * This function can be used to change the pinmux set by\r
+ * Board_init by default.\r
+ *\r
+ * \param   pinmuxData [IN]  Pinmux data structure\r
+ * \param   domain     [IN]  SoC domain for pinmux\r
+ *  \n                        BOARD_SOC_MAIN_DOMAIN - Main domain\r
+ *  \n                        BOARD_SOC_WKUP_DOMAIN - Wakeup domain\r
+ *\r
+ * \return  BOARD_SOK in case of success or appropriate error code\r
+ *\r
+ */\r
+Board_STATUS Board_pinmuxUpdate (pinmuxBoardCfg_t *pinmuxData,\r
+                                 uint32_t domain);\r
+\r
+/**\r
+ * \brief  Board pinmuxing enable function\r
+ *\r
+ * Enables pinmux for the board interfaces. Pin mux is done based\r
+ * on the default/primary functionality of the board. Any pins shared by\r
+ * multiple interfaces need to be reconfigured to access the secondary\r
+ * functionality.\r
+ *\r
+ * \param   void\r
+ *\r
+ * \return  BOARD_SOK in case of success or appropriate error code\r
+ *\r
+ */\r
+Board_STATUS Board_pinmuxConfig (void);\r
+\r
 #ifdef __cplusplus\r
 }\r
 #endif /* __cplusplus */\r
index 38daba86453ee1f87a7ad538b2e4729e80913e1c..58eb49d752fc522faaf9583c5a77b46d052f3f8b 100644 (file)
@@ -5,5 +5,6 @@ INCDIR += src/am64x_evm src/am64x_evm/include
 # Common source files across all platforms and cores\r
 SRCS_COMMON += board_init.c board_lld_init.c board_clock.c board_mmr.c board_pll.c board_utils.c board_i2c_io_exp.c\r
 SRCS_COMMON += board_ddr.c board_info.c board_ethernet_config.c board_pinmux.c board_serdes_cfg.c AM64x_pinmux_data.c\r
+SRCS_COMMON += AM64x_pinmux_data_icssMII.c\r
 \r
 PACKAGE_SRCS_COMMON = src/am64x_evm/src_files_am64x_evm.mk\r
index 046719bd3ed7642af62e9fc8214d363974abec51..cc3135ffa4dbfe62bb67356968a28991d03f8688 100644 (file)
@@ -152,7 +152,7 @@ ifeq ($(BUILD_PROFILE_$(CORE)), release)
  ifeq ($(CGT_ISA),$(filter $(CGT_ISA), M4 R5 M3))
    LNKFLAGS_INTERNAL_BUILD_PROFILE = -qq --diag_warning=225 --diag_suppress=23000 $(LNKFLAGS_GLOBAL_$(CORE))
    ifeq ($(CGT_ISA),$(filter $(CGT_ISA), R5))
-     CFLAGS_INTERNAL += -ms -O4 -s
+#     CFLAGS_INTERNAL += -ms -O4 -s
    else
      CFLAGS_INTERNAL += -ms -O4 -op0 -os --optimize_with_debug --inline_recursion_limit=20
    endif