author | Sivaraj R <sivaraj@ti.com> | |
Fri, 13 Dec 2019 01:27:12 +0000 (19:27 -0600) | ||
committer | Sivaraj R <sivaraj@ti.com> | |
Fri, 13 Dec 2019 01:27:12 +0000 (19:27 -0600) |
* commit 'a0a8498acabec771080e25784002c9a3732a0d21':
McSPI: PRSDK-7663: fix nightly build error for J721e
McSPI: PRSDK-7120: fix McSPI master/slave test failure
McSPI: PRSDK-7663: fix nightly build error for J721e
McSPI: PRSDK-7120: fix McSPI master/slave test failure
36 files changed:
diff --git a/packages/ti/board/src/j721e_evm/board_ddr.c b/packages/ti/board/src/j721e_evm/board_ddr.c
-/******************************************************************************
- * Copyright (c) 2019 Texas Instruments Incorporated - http://www.ti.com
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- *
- * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the
- * distribution.
- *
- * Neither the name of Texas Instruments Incorporated nor the names of
- * its contributors may be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *****************************************************************************/
-
-/** \file board_ddr.c
- *
- * \brief This file used to configure the DDR timing parameters.
- *
- */
-
-#include "board_ddr.h"
-#include "board_utils.h"
-#include <ti/drv/sciclient/sciclient.h>
-
-/* ************************************************************************* */
-/* Global Helper Functions */
-/* ************************************************************************* */
-
-/* Write to a specific field in an MMR. */
-static void Board_DDRWriteMMRField(uint32_t mmrAddr,
- uint32_t fieldVal,
- uint32_t width,
- uint32_t leftshift)
-{
- uint32_t pMMR;
- uint32_t mask;
- pMMR = HW_RD_REG32(mmrAddr); //Grab the MMR value
- mask = (((1 << width) - 1) << leftshift); //Build a mask of 1s for the field.
- mask = ~(mask); //Invert the mask so that the field will be zero'd out with the AND operation.
- pMMR &= mask; //Zero out the field in the register.
- pMMR |= (fieldVal << leftshift); //Assign the value to that specific field.
- HW_WR_REG32(mmrAddr, pMMR);
-}
-
-/**
- * \brief Write the unlocking keys to the locking registers.
- *
- * \param kick0 The first lock register.
- *
- * \param kick1 The second lock register.
- *
- * \return status This should return 0 on a successful unlock.
- */
-static uint32_t Board_DDRMMRUnlockOne(uint32_t kick0, uint32_t kick1)
-{
- // initialize the status variable
- uint32_t status = 1;
-
- // if either of the kick lock registers are locked
- if (!(kick0 & 0x1) | !(kick1 & 0x1)){
- // unlock the partition by writing the unlock values to the kick lock registers
- kick0 = KICK0_UNLOCK;
- kick1 = KICK1_UNLOCK;
- }
-
- // check to see if either of the kick registers are unlocked.
- if (!(kick0 & 0x1)){
- status = 0;
- }
-
- // return the status to the calling program
- return status;
-
-}
-
-/**
- * \brief Unlock the partition for a specific PLL.
- *
- * \param BaseAddr The base address of the PLL MMR instance.
- * \param addrOffset MMR register offset.
- * \param PLLIndex The index of the PLL (one PLL per partition).
- *
- * \return none
- */
-static void Board_DDRUnlockPLLMMR(uint32_t BaseAddr,
- uint32_t addrOffset,
- uint32_t PLLIndex)
-{
- uint32_t firstMMR;
- uint32_t secondMMR;
-
- //Calculate the first lock register address based on the PLL index.
- firstMMR = 0x10 + (PLLIndex * 0x1000) + BaseAddr + addrOffset;
- //Calculate tthe second lock register address based on the PLL index.
- secondMMR = 0x14 + (PLLIndex * 0x1000) + BaseAddr + addrOffset;
- //Unlock the MMR region with those addresses.
- Board_DDRMMRUnlockOne(HW_RD_REG32(firstMMR), HW_RD_REG32(secondMMR));
-}
-
-/**
- * \brief Set DDR PLL to bypass, efectively 20MHz or 19.2MHz (on silicon).
- *
- * \param none
- *
- * \return none
- */
-static void Board_DDRSetPLLExtBypass(void)
-{
-
- uint32_t addrOffset = 0x00000000;
- uint32_t BaseAddr = CSL_PLL0_CFG_BASE;
- uint32_t PLLIndex = DDR_PLL_INDEX;
-
- Board_DDRUnlockPLLMMR(CSL_PLL0_CFG_BASE, addrOffset, PLLIndex);
- //BOARD_DEBUG_LOG("Setting DDR PLL to 20MHz/19.2MHz on silicon (bypass)\n");
- //Put the PLL in external bypass first. Write "1" to bit #31 in the control register.
- Board_DDRWriteMMRField((BaseAddr + addrOffset + (PLLIndex * 0x1000) + CONTROL), 1, 1, 31);
- //BOARD_DEBUG_LOG("Set PLL to external bypass\n");
-}
-
-/**
- * \brief Set DDR PLL clock value
- *
- * \param none
- *
- * \return none
- */
-static void Board_DDRSetPLLClock(void)
-{
- Board_STATUS status = BOARD_SOK;
- status = Board_PLLInit(TISCI_DEV_DDR0,
- TISCI_DEV_DDR0_DDRSS_DDR_PLL_CLK,
- DDRSS_PLL_FREQUENCY);
- if(status != BOARD_SOK)
- {
- BOARD_DEBUG_LOG("Failed to set the PLL clock freq\n");
- }
-}
-
-static void Board_DDRChangeFreqAck(void)
-{
- uint32_t reqType, regVal;
- volatile uint32_t counter, counter2;
- volatile uint32_t temp = 0;
-
- temp = temp; /* To suppress compiler warning */
- BOARD_DEBUG_LOG("--->>> LPDDR4 Initialization is in progress ... <<<---\n");
-
- for(counter = 0; counter < DDRSS_PLL_FHS_CNT; counter++)
- {
- //wait for freq change request
- regVal = HW_RD_REG32(0x00114080) & 0x80;
- BOARD_DEBUG_LOG("Reg Value: %d \n",,,,, regVal);
- while(regVal == 0x0){
- regVal = HW_RD_REG32(0x00114080) & 0x80;
- BOARD_DEBUG_LOG("Reg Value: %d \n",,,,, regVal);
- }
-
- reqType = HW_RD_REG32(0x00114080) & 0x03;
- BOARD_DEBUG_LOG("Frequency Change type %d request from Controller \n",,,,, reqType);
-
- if(reqType == 1){
- Board_DDRSetPLLClock();
- }else if(reqType == 2){
- Board_DDRSetPLLClock(); //Set_DDR_PLL_933MHz
- }else if(reqType == 0){
- Board_DDRSetPLLExtBypass();
- }else{
- //BOARD_DEBUG_LOG("error\n",,,,,);
- }
-
- counter2 = 0;
- while(counter2 < 200){
- temp = HW_RD_REG32(0x00114080);
- counter2++;
- }
-
- HW_WR_REG32(0x001140C0, 0x1); //set the ack bit
-
- counter2 = 0;
- while(counter2 < 10){
- temp = HW_RD_REG32(0x00114080);
- counter2++;
- }
-
- while((HW_RD_REG32(0x00114080) & 0x80) == 0x80);
-
- counter2 = 0;
- while(counter2 < 10){
- temp = HW_RD_REG32(0x00114080);
- counter2++;
- }
-
- HW_WR_REG32(0x001140C0, 0x0); //clear the ack bit
-
- counter2 = 0;
- while(counter2 < 10){
- temp= HW_RD_REG32(0x00114080);
- counter2++;
- }
- }
-
- BOARD_DEBUG_LOG("--->>> Frequency Change request handshake is completed... <<<---\n");
-}
-
-/**
- * \brief DDR4 Initialization function
- *
- * Initializes the DDR timing parameters. Sets the DDR timing parameters
- * based in the DDR PLL controller configuration done by the board library.
- * Any changes to DDR PLL requires change to DDR timing.
- *
- * \param void
- *
- * \return BOARD_SOK in case of success or appropriate error code
- *
- */
-Board_STATUS Board_DDRInit(void)
-{
- Board_unlockMMR();
-
- Board_DDRSetPLLExtBypass();
-
- //Program the DDR Controller
- BOARD_DEBUG_LOG("--->>> DDR controller programming in progress.. <<<---\n");
- BOARD_delay(100000);
-
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_0_OFFSET, DDRSS_CTL_00_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_1_OFFSET, DDRSS_CTL_01_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_2_OFFSET, DDRSS_CTL_02_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_3_OFFSET, DDRSS_CTL_03_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_4_OFFSET, DDRSS_CTL_04_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_5_OFFSET, DDRSS_CTL_05_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_6_OFFSET, DDRSS_CTL_06_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_7_OFFSET, DDRSS_CTL_07_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_8_OFFSET, DDRSS_CTL_08_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_9_OFFSET, DDRSS_CTL_09_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_10_OFFSET, DDRSS_CTL_10_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_11_OFFSET, DDRSS_CTL_11_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_12_OFFSET, DDRSS_CTL_12_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_13_OFFSET, DDRSS_CTL_13_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_14_OFFSET, DDRSS_CTL_14_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_15_OFFSET, DDRSS_CTL_15_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_16_OFFSET, DDRSS_CTL_16_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_17_OFFSET, DDRSS_CTL_17_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_18_OFFSET, DDRSS_CTL_18_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_19_OFFSET, DDRSS_CTL_19_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_20_OFFSET, DDRSS_CTL_20_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_21_OFFSET, DDRSS_CTL_21_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_22_OFFSET, DDRSS_CTL_22_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_23_OFFSET, DDRSS_CTL_23_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_24_OFFSET, DDRSS_CTL_24_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_25_OFFSET, DDRSS_CTL_25_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_26_OFFSET, DDRSS_CTL_26_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_27_OFFSET, DDRSS_CTL_27_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_28_OFFSET, DDRSS_CTL_28_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_29_OFFSET, DDRSS_CTL_29_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_30_OFFSET, DDRSS_CTL_30_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_31_OFFSET, DDRSS_CTL_31_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_32_OFFSET, DDRSS_CTL_32_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_33_OFFSET, DDRSS_CTL_33_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_34_OFFSET, DDRSS_CTL_34_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_35_OFFSET, DDRSS_CTL_35_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_36_OFFSET, DDRSS_CTL_36_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_37_OFFSET, DDRSS_CTL_37_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_38_OFFSET, DDRSS_CTL_38_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_39_OFFSET, DDRSS_CTL_39_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_40_OFFSET, DDRSS_CTL_40_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_41_OFFSET, DDRSS_CTL_41_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_42_OFFSET, DDRSS_CTL_42_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_43_OFFSET, DDRSS_CTL_43_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_44_OFFSET, DDRSS_CTL_44_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_45_OFFSET, DDRSS_CTL_45_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_46_OFFSET, DDRSS_CTL_46_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_47_OFFSET, DDRSS_CTL_47_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_48_OFFSET, DDRSS_CTL_48_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_49_OFFSET, DDRSS_CTL_49_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_50_OFFSET, DDRSS_CTL_50_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_51_OFFSET, DDRSS_CTL_51_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_52_OFFSET, DDRSS_CTL_52_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_53_OFFSET, DDRSS_CTL_53_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_54_OFFSET, DDRSS_CTL_54_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_55_OFFSET, DDRSS_CTL_55_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_56_OFFSET, DDRSS_CTL_56_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_57_OFFSET, DDRSS_CTL_57_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_58_OFFSET, DDRSS_CTL_58_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_59_OFFSET, DDRSS_CTL_59_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_60_OFFSET, DDRSS_CTL_60_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_61_OFFSET, DDRSS_CTL_61_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_62_OFFSET, DDRSS_CTL_62_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_63_OFFSET, DDRSS_CTL_63_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_64_OFFSET, DDRSS_CTL_64_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_65_OFFSET, DDRSS_CTL_65_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_66_OFFSET, DDRSS_CTL_66_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_67_OFFSET, DDRSS_CTL_67_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_68_OFFSET, DDRSS_CTL_68_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_69_OFFSET, DDRSS_CTL_69_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_70_OFFSET, DDRSS_CTL_70_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_71_OFFSET, DDRSS_CTL_71_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_72_OFFSET, DDRSS_CTL_72_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_73_OFFSET, DDRSS_CTL_73_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_74_OFFSET, DDRSS_CTL_74_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_75_OFFSET, DDRSS_CTL_75_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_76_OFFSET, DDRSS_CTL_76_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_77_OFFSET, DDRSS_CTL_77_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_78_OFFSET, DDRSS_CTL_78_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_79_OFFSET, DDRSS_CTL_79_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_80_OFFSET, DDRSS_CTL_80_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_81_OFFSET, DDRSS_CTL_81_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_82_OFFSET, DDRSS_CTL_82_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_83_OFFSET, DDRSS_CTL_83_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_84_OFFSET, DDRSS_CTL_84_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_85_OFFSET, DDRSS_CTL_85_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_86_OFFSET, DDRSS_CTL_86_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_87_OFFSET, DDRSS_CTL_87_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_88_OFFSET, DDRSS_CTL_88_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_89_OFFSET, DDRSS_CTL_89_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_90_OFFSET, DDRSS_CTL_90_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_91_OFFSET, DDRSS_CTL_91_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_92_OFFSET, DDRSS_CTL_92_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_93_OFFSET, DDRSS_CTL_93_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_94_OFFSET, DDRSS_CTL_94_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_95_OFFSET, DDRSS_CTL_95_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_96_OFFSET, DDRSS_CTL_96_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_97_OFFSET, DDRSS_CTL_97_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_98_OFFSET, DDRSS_CTL_98_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_99_OFFSET, DDRSS_CTL_99_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_100_OFFSET, DDRSS_CTL_100_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_101_OFFSET, DDRSS_CTL_101_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_102_OFFSET, DDRSS_CTL_102_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_103_OFFSET, DDRSS_CTL_103_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_104_OFFSET, DDRSS_CTL_104_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_105_OFFSET, DDRSS_CTL_105_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_106_OFFSET, DDRSS_CTL_106_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_107_OFFSET, DDRSS_CTL_107_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_108_OFFSET, DDRSS_CTL_108_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_109_OFFSET, DDRSS_CTL_109_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_110_OFFSET, DDRSS_CTL_110_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_111_OFFSET, DDRSS_CTL_111_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_112_OFFSET, DDRSS_CTL_112_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_113_OFFSET, DDRSS_CTL_113_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_114_OFFSET, DDRSS_CTL_114_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_115_OFFSET, DDRSS_CTL_115_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_116_OFFSET, DDRSS_CTL_116_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_117_OFFSET, DDRSS_CTL_117_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_118_OFFSET, DDRSS_CTL_118_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_119_OFFSET, DDRSS_CTL_119_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_120_OFFSET, DDRSS_CTL_120_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_121_OFFSET, DDRSS_CTL_121_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_122_OFFSET, DDRSS_CTL_122_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_123_OFFSET, DDRSS_CTL_123_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_124_OFFSET, DDRSS_CTL_124_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_125_OFFSET, DDRSS_CTL_125_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_126_OFFSET, DDRSS_CTL_126_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_127_OFFSET, DDRSS_CTL_127_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_128_OFFSET, DDRSS_CTL_128_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_129_OFFSET, DDRSS_CTL_129_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_130_OFFSET, DDRSS_CTL_130_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_131_OFFSET, DDRSS_CTL_131_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_132_OFFSET, DDRSS_CTL_132_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_133_OFFSET, DDRSS_CTL_133_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_134_OFFSET, DDRSS_CTL_134_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_135_OFFSET, DDRSS_CTL_135_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_136_OFFSET, DDRSS_CTL_136_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_137_OFFSET, DDRSS_CTL_137_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_138_OFFSET, DDRSS_CTL_138_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_139_OFFSET, DDRSS_CTL_139_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_140_OFFSET, DDRSS_CTL_140_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_141_OFFSET, DDRSS_CTL_141_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_142_OFFSET, DDRSS_CTL_142_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_143_OFFSET, DDRSS_CTL_143_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_144_OFFSET, DDRSS_CTL_144_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_145_OFFSET, DDRSS_CTL_145_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_146_OFFSET, DDRSS_CTL_146_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_147_OFFSET, DDRSS_CTL_147_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_148_OFFSET, DDRSS_CTL_148_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_149_OFFSET, DDRSS_CTL_149_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_150_OFFSET, DDRSS_CTL_150_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_151_OFFSET, DDRSS_CTL_151_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_152_OFFSET, DDRSS_CTL_152_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_153_OFFSET, DDRSS_CTL_153_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_154_OFFSET, DDRSS_CTL_154_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_155_OFFSET, DDRSS_CTL_155_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_156_OFFSET, DDRSS_CTL_156_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_157_OFFSET, DDRSS_CTL_157_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_158_OFFSET, DDRSS_CTL_158_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_159_OFFSET, DDRSS_CTL_159_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_160_OFFSET, DDRSS_CTL_160_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_161_OFFSET, DDRSS_CTL_161_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_162_OFFSET, DDRSS_CTL_162_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_163_OFFSET, DDRSS_CTL_163_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_164_OFFSET, DDRSS_CTL_164_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_165_OFFSET, DDRSS_CTL_165_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_166_OFFSET, DDRSS_CTL_166_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_167_OFFSET, DDRSS_CTL_167_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_168_OFFSET, DDRSS_CTL_168_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_169_OFFSET, DDRSS_CTL_169_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_170_OFFSET, DDRSS_CTL_170_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_171_OFFSET, DDRSS_CTL_171_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_172_OFFSET, DDRSS_CTL_172_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_173_OFFSET, DDRSS_CTL_173_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_174_OFFSET, DDRSS_CTL_174_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_175_OFFSET, DDRSS_CTL_175_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_176_OFFSET, DDRSS_CTL_176_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_177_OFFSET, DDRSS_CTL_177_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_178_OFFSET, DDRSS_CTL_178_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_179_OFFSET, DDRSS_CTL_179_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_180_OFFSET, DDRSS_CTL_180_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_181_OFFSET, DDRSS_CTL_181_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_182_OFFSET, DDRSS_CTL_182_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_183_OFFSET, DDRSS_CTL_183_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_184_OFFSET, DDRSS_CTL_184_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_185_OFFSET, DDRSS_CTL_185_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_186_OFFSET, DDRSS_CTL_186_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_187_OFFSET, DDRSS_CTL_187_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_188_OFFSET, DDRSS_CTL_188_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_189_OFFSET, DDRSS_CTL_189_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_190_OFFSET, DDRSS_CTL_190_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_191_OFFSET, DDRSS_CTL_191_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_192_OFFSET, DDRSS_CTL_192_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_193_OFFSET, DDRSS_CTL_193_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_194_OFFSET, DDRSS_CTL_194_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_195_OFFSET, DDRSS_CTL_195_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_196_OFFSET, DDRSS_CTL_196_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_197_OFFSET, DDRSS_CTL_197_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_198_OFFSET, DDRSS_CTL_198_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_199_OFFSET, DDRSS_CTL_199_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_200_OFFSET, DDRSS_CTL_200_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_201_OFFSET, DDRSS_CTL_201_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_202_OFFSET, DDRSS_CTL_202_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_203_OFFSET, DDRSS_CTL_203_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_204_OFFSET, DDRSS_CTL_204_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_205_OFFSET, DDRSS_CTL_205_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_206_OFFSET, DDRSS_CTL_206_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_207_OFFSET, DDRSS_CTL_207_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_208_OFFSET, DDRSS_CTL_208_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_209_OFFSET, DDRSS_CTL_209_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_210_OFFSET, DDRSS_CTL_210_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_211_OFFSET, DDRSS_CTL_211_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_212_OFFSET, DDRSS_CTL_212_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_213_OFFSET, DDRSS_CTL_213_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_214_OFFSET, DDRSS_CTL_214_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_215_OFFSET, DDRSS_CTL_215_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_216_OFFSET, DDRSS_CTL_216_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_217_OFFSET, DDRSS_CTL_217_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_218_OFFSET, DDRSS_CTL_218_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_219_OFFSET, DDRSS_CTL_219_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_220_OFFSET, DDRSS_CTL_220_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_221_OFFSET, DDRSS_CTL_221_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_222_OFFSET, DDRSS_CTL_222_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_223_OFFSET, DDRSS_CTL_223_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_224_OFFSET, DDRSS_CTL_224_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_225_OFFSET, DDRSS_CTL_225_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_226_OFFSET, DDRSS_CTL_226_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_227_OFFSET, DDRSS_CTL_227_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_228_OFFSET, DDRSS_CTL_228_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_229_OFFSET, DDRSS_CTL_229_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_230_OFFSET, DDRSS_CTL_230_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_231_OFFSET, DDRSS_CTL_231_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_232_OFFSET, DDRSS_CTL_232_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_233_OFFSET, DDRSS_CTL_233_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_234_OFFSET, DDRSS_CTL_234_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_235_OFFSET, DDRSS_CTL_235_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_236_OFFSET, DDRSS_CTL_236_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_237_OFFSET, DDRSS_CTL_237_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_238_OFFSET, DDRSS_CTL_238_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_239_OFFSET, DDRSS_CTL_239_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_240_OFFSET, DDRSS_CTL_240_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_241_OFFSET, DDRSS_CTL_241_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_242_OFFSET, DDRSS_CTL_242_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_243_OFFSET, DDRSS_CTL_243_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_244_OFFSET, DDRSS_CTL_244_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_245_OFFSET, DDRSS_CTL_245_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_246_OFFSET, DDRSS_CTL_246_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_247_OFFSET, DDRSS_CTL_247_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_248_OFFSET, DDRSS_CTL_248_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_249_OFFSET, DDRSS_CTL_249_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_250_OFFSET, DDRSS_CTL_250_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_251_OFFSET, DDRSS_CTL_251_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_252_OFFSET, DDRSS_CTL_252_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_253_OFFSET, DDRSS_CTL_253_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_254_OFFSET, DDRSS_CTL_254_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_255_OFFSET, DDRSS_CTL_255_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_256_OFFSET, DDRSS_CTL_256_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_257_OFFSET, DDRSS_CTL_257_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_258_OFFSET, DDRSS_CTL_258_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_259_OFFSET, DDRSS_CTL_259_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_260_OFFSET, DDRSS_CTL_260_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_261_OFFSET, DDRSS_CTL_261_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_262_OFFSET, DDRSS_CTL_262_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_263_OFFSET, DDRSS_CTL_263_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_264_OFFSET, DDRSS_CTL_264_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_265_OFFSET, DDRSS_CTL_265_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_266_OFFSET, DDRSS_CTL_266_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_267_OFFSET, DDRSS_CTL_267_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_268_OFFSET, DDRSS_CTL_268_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_269_OFFSET, DDRSS_CTL_269_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_270_OFFSET, DDRSS_CTL_270_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_271_OFFSET, DDRSS_CTL_271_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_272_OFFSET, DDRSS_CTL_272_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_273_OFFSET, DDRSS_CTL_273_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_274_OFFSET, DDRSS_CTL_274_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_275_OFFSET, DDRSS_CTL_275_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_276_OFFSET, DDRSS_CTL_276_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_277_OFFSET, DDRSS_CTL_277_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_278_OFFSET, DDRSS_CTL_278_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_279_OFFSET, DDRSS_CTL_279_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_280_OFFSET, DDRSS_CTL_280_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_281_OFFSET, DDRSS_CTL_281_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_282_OFFSET, DDRSS_CTL_282_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_283_OFFSET, DDRSS_CTL_283_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_284_OFFSET, DDRSS_CTL_284_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_285_OFFSET, DDRSS_CTL_285_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_286_OFFSET, DDRSS_CTL_286_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_287_OFFSET, DDRSS_CTL_287_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_288_OFFSET, DDRSS_CTL_288_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_289_OFFSET, DDRSS_CTL_289_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_290_OFFSET, DDRSS_CTL_290_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_291_OFFSET, DDRSS_CTL_291_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_292_OFFSET, DDRSS_CTL_292_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_293_OFFSET, DDRSS_CTL_293_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_294_OFFSET, DDRSS_CTL_294_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_295_OFFSET, DDRSS_CTL_295_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_296_OFFSET, DDRSS_CTL_296_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_297_OFFSET, DDRSS_CTL_297_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_298_OFFSET, DDRSS_CTL_298_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_299_OFFSET, DDRSS_CTL_299_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_300_OFFSET, DDRSS_CTL_300_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_301_OFFSET, DDRSS_CTL_301_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_302_OFFSET, DDRSS_CTL_302_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_303_OFFSET, DDRSS_CTL_303_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_304_OFFSET, DDRSS_CTL_304_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_305_OFFSET, DDRSS_CTL_305_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_306_OFFSET, DDRSS_CTL_306_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_307_OFFSET, DDRSS_CTL_307_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_308_OFFSET, DDRSS_CTL_308_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_309_OFFSET, DDRSS_CTL_309_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_310_OFFSET, DDRSS_CTL_310_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_311_OFFSET, DDRSS_CTL_311_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_312_OFFSET, DDRSS_CTL_312_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_313_OFFSET, DDRSS_CTL_313_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_314_OFFSET, DDRSS_CTL_314_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_315_OFFSET, DDRSS_CTL_315_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_316_OFFSET, DDRSS_CTL_316_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_317_OFFSET, DDRSS_CTL_317_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_318_OFFSET, DDRSS_CTL_318_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_319_OFFSET, DDRSS_CTL_319_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_320_OFFSET, DDRSS_CTL_320_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_321_OFFSET, DDRSS_CTL_321_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_322_OFFSET, DDRSS_CTL_322_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_323_OFFSET, DDRSS_CTL_323_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_324_OFFSET, DDRSS_CTL_324_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_325_OFFSET, DDRSS_CTL_325_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_326_OFFSET, DDRSS_CTL_326_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_327_OFFSET, DDRSS_CTL_327_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_328_OFFSET, DDRSS_CTL_328_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_329_OFFSET, DDRSS_CTL_329_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_330_OFFSET, DDRSS_CTL_330_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_331_OFFSET, DDRSS_CTL_331_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_332_OFFSET, DDRSS_CTL_332_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_333_OFFSET, DDRSS_CTL_333_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_334_OFFSET, DDRSS_CTL_334_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_335_OFFSET, DDRSS_CTL_335_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_336_OFFSET, DDRSS_CTL_336_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_337_OFFSET, DDRSS_CTL_337_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_338_OFFSET, DDRSS_CTL_338_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_339_OFFSET, DDRSS_CTL_339_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_340_OFFSET, DDRSS_CTL_340_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_341_OFFSET, DDRSS_CTL_341_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_342_OFFSET, DDRSS_CTL_342_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_343_OFFSET, DDRSS_CTL_343_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_344_OFFSET, DDRSS_CTL_344_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_345_OFFSET, DDRSS_CTL_345_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_346_OFFSET, DDRSS_CTL_346_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_347_OFFSET, DDRSS_CTL_347_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_348_OFFSET, DDRSS_CTL_348_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_349_OFFSET, DDRSS_CTL_349_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_350_OFFSET, DDRSS_CTL_350_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_351_OFFSET, DDRSS_CTL_351_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_352_OFFSET, DDRSS_CTL_352_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_353_OFFSET, DDRSS_CTL_353_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_354_OFFSET, DDRSS_CTL_354_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_355_OFFSET, DDRSS_CTL_355_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_356_OFFSET, DDRSS_CTL_356_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_357_OFFSET, DDRSS_CTL_357_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_358_OFFSET, DDRSS_CTL_358_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_359_OFFSET, DDRSS_CTL_359_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_360_OFFSET, DDRSS_CTL_360_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_361_OFFSET, DDRSS_CTL_361_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_362_OFFSET, DDRSS_CTL_362_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_363_OFFSET, DDRSS_CTL_363_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_364_OFFSET, DDRSS_CTL_364_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_365_OFFSET, DDRSS_CTL_365_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_366_OFFSET, DDRSS_CTL_366_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_367_OFFSET, DDRSS_CTL_367_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_368_OFFSET, DDRSS_CTL_368_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_369_OFFSET, DDRSS_CTL_369_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_370_OFFSET, DDRSS_CTL_370_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_371_OFFSET, DDRSS_CTL_371_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_372_OFFSET, DDRSS_CTL_372_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_373_OFFSET, DDRSS_CTL_373_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_374_OFFSET, DDRSS_CTL_374_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_375_OFFSET, DDRSS_CTL_375_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_376_OFFSET, DDRSS_CTL_376_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_377_OFFSET, DDRSS_CTL_377_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_378_OFFSET, DDRSS_CTL_378_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_379_OFFSET, DDRSS_CTL_379_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_380_OFFSET, DDRSS_CTL_380_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_381_OFFSET, DDRSS_CTL_381_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_382_OFFSET, DDRSS_CTL_382_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_383_OFFSET, DDRSS_CTL_383_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_384_OFFSET, DDRSS_CTL_384_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_385_OFFSET, DDRSS_CTL_385_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_386_OFFSET, DDRSS_CTL_386_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_387_OFFSET, DDRSS_CTL_387_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_388_OFFSET, DDRSS_CTL_388_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_389_OFFSET, DDRSS_CTL_389_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_390_OFFSET, DDRSS_CTL_390_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_391_OFFSET, DDRSS_CTL_391_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_392_OFFSET, DDRSS_CTL_392_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_393_OFFSET, DDRSS_CTL_393_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_394_OFFSET, DDRSS_CTL_394_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_395_OFFSET, DDRSS_CTL_395_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_396_OFFSET, DDRSS_CTL_396_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_397_OFFSET, DDRSS_CTL_397_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_398_OFFSET, DDRSS_CTL_398_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_399_OFFSET, DDRSS_CTL_399_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_400_OFFSET, DDRSS_CTL_400_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_401_OFFSET, DDRSS_CTL_401_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_402_OFFSET, DDRSS_CTL_402_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_403_OFFSET, DDRSS_CTL_403_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_404_OFFSET, DDRSS_CTL_404_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_405_OFFSET, DDRSS_CTL_405_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_406_OFFSET, DDRSS_CTL_406_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_407_OFFSET, DDRSS_CTL_407_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_408_OFFSET, DDRSS_CTL_408_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_409_OFFSET, DDRSS_CTL_409_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_410_OFFSET, DDRSS_CTL_410_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_411_OFFSET, DDRSS_CTL_411_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_412_OFFSET, DDRSS_CTL_412_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_413_OFFSET, DDRSS_CTL_413_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_414_OFFSET, DDRSS_CTL_414_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_415_OFFSET, DDRSS_CTL_415_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_416_OFFSET, DDRSS_CTL_416_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_417_OFFSET, DDRSS_CTL_417_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_418_OFFSET, DDRSS_CTL_418_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_419_OFFSET, DDRSS_CTL_419_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_420_OFFSET, DDRSS_CTL_420_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_421_OFFSET, DDRSS_CTL_421_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_422_OFFSET, DDRSS_CTL_422_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_423_OFFSET, DDRSS_CTL_423_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_424_OFFSET, DDRSS_CTL_424_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_425_OFFSET, DDRSS_CTL_425_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_426_OFFSET, DDRSS_CTL_426_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_427_OFFSET, DDRSS_CTL_427_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_428_OFFSET, DDRSS_CTL_428_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_429_OFFSET, DDRSS_CTL_429_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_430_OFFSET, DDRSS_CTL_430_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_431_OFFSET, DDRSS_CTL_431_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_432_OFFSET, DDRSS_CTL_432_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_433_OFFSET, DDRSS_CTL_433_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_434_OFFSET, DDRSS_CTL_434_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_435_OFFSET, DDRSS_CTL_435_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_436_OFFSET, DDRSS_CTL_436_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_437_OFFSET, DDRSS_CTL_437_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_438_OFFSET, DDRSS_CTL_438_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_439_OFFSET, DDRSS_CTL_439_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_440_OFFSET, DDRSS_CTL_440_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_441_OFFSET, DDRSS_CTL_441_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_442_OFFSET, DDRSS_CTL_442_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_443_OFFSET, DDRSS_CTL_443_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_444_OFFSET, DDRSS_CTL_444_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_445_OFFSET, DDRSS_CTL_445_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_446_OFFSET, DDRSS_CTL_446_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_447_OFFSET, DDRSS_CTL_447_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_448_OFFSET, DDRSS_CTL_448_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_449_OFFSET, DDRSS_CTL_449_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_450_OFFSET, DDRSS_CTL_450_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_451_OFFSET, DDRSS_CTL_451_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_452_OFFSET, DDRSS_CTL_452_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_453_OFFSET, DDRSS_CTL_453_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_454_OFFSET, DDRSS_CTL_454_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_455_OFFSET, DDRSS_CTL_455_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_456_OFFSET, DDRSS_CTL_456_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_457_OFFSET, DDRSS_CTL_457_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_458_OFFSET, DDRSS_CTL_458_DATA );
-
- BOARD_DEBUG_LOG("--->>> DDR controller programming completed... <<<---\n");
-
- //Program the PI module
- BOARD_DEBUG_LOG("--->>> DDR PI programming in progress.. <<<---\n");
-
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_0_OFFSET, DDRSS_PI_00_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_1_OFFSET, DDRSS_PI_01_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_2_OFFSET, DDRSS_PI_02_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_3_OFFSET, DDRSS_PI_03_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_4_OFFSET, DDRSS_PI_04_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_5_OFFSET, DDRSS_PI_05_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_6_OFFSET, DDRSS_PI_06_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_7_OFFSET, DDRSS_PI_07_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_8_OFFSET, DDRSS_PI_08_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_9_OFFSET, DDRSS_PI_09_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_10_OFFSET, DDRSS_PI_10_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_11_OFFSET, DDRSS_PI_11_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_12_OFFSET, DDRSS_PI_12_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_13_OFFSET, DDRSS_PI_13_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_14_OFFSET, DDRSS_PI_14_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_15_OFFSET, DDRSS_PI_15_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_16_OFFSET, DDRSS_PI_16_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_17_OFFSET, DDRSS_PI_17_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_18_OFFSET, DDRSS_PI_18_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_19_OFFSET, DDRSS_PI_19_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_20_OFFSET, DDRSS_PI_20_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_21_OFFSET, DDRSS_PI_21_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_22_OFFSET, DDRSS_PI_22_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_23_OFFSET, DDRSS_PI_23_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_24_OFFSET, DDRSS_PI_24_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_25_OFFSET, DDRSS_PI_25_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_26_OFFSET, DDRSS_PI_26_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_27_OFFSET, DDRSS_PI_27_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_28_OFFSET, DDRSS_PI_28_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_29_OFFSET, DDRSS_PI_29_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_30_OFFSET, DDRSS_PI_30_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_31_OFFSET, DDRSS_PI_31_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_32_OFFSET, DDRSS_PI_32_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_33_OFFSET, DDRSS_PI_33_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_34_OFFSET, DDRSS_PI_34_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_35_OFFSET, DDRSS_PI_35_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_36_OFFSET, DDRSS_PI_36_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_37_OFFSET, DDRSS_PI_37_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_38_OFFSET, DDRSS_PI_38_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_39_OFFSET, DDRSS_PI_39_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_40_OFFSET, DDRSS_PI_40_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_41_OFFSET, DDRSS_PI_41_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_42_OFFSET, DDRSS_PI_42_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_43_OFFSET, DDRSS_PI_43_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_44_OFFSET, DDRSS_PI_44_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_45_OFFSET, DDRSS_PI_45_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_46_OFFSET, DDRSS_PI_46_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_47_OFFSET, DDRSS_PI_47_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_48_OFFSET, DDRSS_PI_48_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_49_OFFSET, DDRSS_PI_49_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_50_OFFSET, DDRSS_PI_50_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_51_OFFSET, DDRSS_PI_51_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_52_OFFSET, DDRSS_PI_52_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_53_OFFSET, DDRSS_PI_53_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_54_OFFSET, DDRSS_PI_54_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_55_OFFSET, DDRSS_PI_55_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_56_OFFSET, DDRSS_PI_56_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_57_OFFSET, DDRSS_PI_57_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_58_OFFSET, DDRSS_PI_58_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_59_OFFSET, DDRSS_PI_59_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_60_OFFSET, DDRSS_PI_60_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_61_OFFSET, DDRSS_PI_61_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_62_OFFSET, DDRSS_PI_62_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_63_OFFSET, DDRSS_PI_63_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_64_OFFSET, DDRSS_PI_64_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_65_OFFSET, DDRSS_PI_65_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_66_OFFSET, DDRSS_PI_66_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_67_OFFSET, DDRSS_PI_67_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_68_OFFSET, DDRSS_PI_68_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_69_OFFSET, DDRSS_PI_69_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_70_OFFSET, DDRSS_PI_70_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_71_OFFSET, DDRSS_PI_71_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_72_OFFSET, DDRSS_PI_72_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_73_OFFSET, DDRSS_PI_73_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_74_OFFSET, DDRSS_PI_74_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_75_OFFSET, DDRSS_PI_75_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_76_OFFSET, DDRSS_PI_76_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_77_OFFSET, DDRSS_PI_77_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_78_OFFSET, DDRSS_PI_78_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_79_OFFSET, DDRSS_PI_79_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_80_OFFSET, DDRSS_PI_80_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_81_OFFSET, DDRSS_PI_81_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_82_OFFSET, DDRSS_PI_82_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_83_OFFSET, DDRSS_PI_83_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_84_OFFSET, DDRSS_PI_84_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_85_OFFSET, DDRSS_PI_85_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_86_OFFSET, DDRSS_PI_86_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_87_OFFSET, DDRSS_PI_87_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_88_OFFSET, DDRSS_PI_88_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_89_OFFSET, DDRSS_PI_89_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_90_OFFSET, DDRSS_PI_90_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_91_OFFSET, DDRSS_PI_91_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_92_OFFSET, DDRSS_PI_92_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_93_OFFSET, DDRSS_PI_93_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_94_OFFSET, DDRSS_PI_94_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_95_OFFSET, DDRSS_PI_95_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_96_OFFSET, DDRSS_PI_96_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_97_OFFSET, DDRSS_PI_97_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_98_OFFSET, DDRSS_PI_98_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_99_OFFSET, DDRSS_PI_99_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_100_OFFSET, DDRSS_PI_100_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_101_OFFSET, DDRSS_PI_101_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_102_OFFSET, DDRSS_PI_102_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_103_OFFSET, DDRSS_PI_103_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_104_OFFSET, DDRSS_PI_104_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_105_OFFSET, DDRSS_PI_105_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_106_OFFSET, DDRSS_PI_106_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_107_OFFSET, DDRSS_PI_107_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_108_OFFSET, DDRSS_PI_108_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_109_OFFSET, DDRSS_PI_109_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_110_OFFSET, DDRSS_PI_110_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_111_OFFSET, DDRSS_PI_111_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_112_OFFSET, DDRSS_PI_112_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_113_OFFSET, DDRSS_PI_113_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_114_OFFSET, DDRSS_PI_114_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_115_OFFSET, DDRSS_PI_115_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_116_OFFSET, DDRSS_PI_116_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_117_OFFSET, DDRSS_PI_117_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_118_OFFSET, DDRSS_PI_118_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_119_OFFSET, DDRSS_PI_119_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_120_OFFSET, DDRSS_PI_120_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_121_OFFSET, DDRSS_PI_121_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_122_OFFSET, DDRSS_PI_122_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_123_OFFSET, DDRSS_PI_123_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_124_OFFSET, DDRSS_PI_124_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_125_OFFSET, DDRSS_PI_125_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_126_OFFSET, DDRSS_PI_126_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_127_OFFSET, DDRSS_PI_127_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_128_OFFSET, DDRSS_PI_128_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_129_OFFSET, DDRSS_PI_129_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_130_OFFSET, DDRSS_PI_130_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_131_OFFSET, DDRSS_PI_131_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_132_OFFSET, DDRSS_PI_132_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_133_OFFSET, DDRSS_PI_133_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_134_OFFSET, DDRSS_PI_134_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_135_OFFSET, DDRSS_PI_135_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_136_OFFSET, DDRSS_PI_136_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_137_OFFSET, DDRSS_PI_137_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_138_OFFSET, DDRSS_PI_138_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_139_OFFSET, DDRSS_PI_139_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_140_OFFSET, DDRSS_PI_140_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_141_OFFSET, DDRSS_PI_141_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_142_OFFSET, DDRSS_PI_142_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_143_OFFSET, DDRSS_PI_143_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_144_OFFSET, DDRSS_PI_144_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_145_OFFSET, DDRSS_PI_145_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_146_OFFSET, DDRSS_PI_146_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_147_OFFSET, DDRSS_PI_147_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_148_OFFSET, DDRSS_PI_148_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_149_OFFSET, DDRSS_PI_149_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_150_OFFSET, DDRSS_PI_150_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_151_OFFSET, DDRSS_PI_151_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_152_OFFSET, DDRSS_PI_152_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_153_OFFSET, DDRSS_PI_153_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_154_OFFSET, DDRSS_PI_154_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_155_OFFSET, DDRSS_PI_155_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_156_OFFSET, DDRSS_PI_156_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_157_OFFSET, DDRSS_PI_157_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_158_OFFSET, DDRSS_PI_158_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_159_OFFSET, DDRSS_PI_159_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_160_OFFSET, DDRSS_PI_160_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_161_OFFSET, DDRSS_PI_161_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_162_OFFSET, DDRSS_PI_162_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_163_OFFSET, DDRSS_PI_163_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_164_OFFSET, DDRSS_PI_164_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_165_OFFSET, DDRSS_PI_165_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_166_OFFSET, DDRSS_PI_166_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_167_OFFSET, DDRSS_PI_167_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_168_OFFSET, DDRSS_PI_168_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_169_OFFSET, DDRSS_PI_169_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_170_OFFSET, DDRSS_PI_170_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_171_OFFSET, DDRSS_PI_171_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_172_OFFSET, DDRSS_PI_172_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_173_OFFSET, DDRSS_PI_173_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_174_OFFSET, DDRSS_PI_174_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_175_OFFSET, DDRSS_PI_175_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_176_OFFSET, DDRSS_PI_176_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_177_OFFSET, DDRSS_PI_177_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_178_OFFSET, DDRSS_PI_178_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_179_OFFSET, DDRSS_PI_179_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_180_OFFSET, DDRSS_PI_180_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_181_OFFSET, DDRSS_PI_181_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_182_OFFSET, DDRSS_PI_182_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_183_OFFSET, DDRSS_PI_183_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_184_OFFSET, DDRSS_PI_184_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_185_OFFSET, DDRSS_PI_185_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_186_OFFSET, DDRSS_PI_186_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_187_OFFSET, DDRSS_PI_187_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_188_OFFSET, DDRSS_PI_188_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_189_OFFSET, DDRSS_PI_189_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_190_OFFSET, DDRSS_PI_190_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_191_OFFSET, DDRSS_PI_191_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_192_OFFSET, DDRSS_PI_192_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_193_OFFSET, DDRSS_PI_193_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_194_OFFSET, DDRSS_PI_194_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_195_OFFSET, DDRSS_PI_195_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_196_OFFSET, DDRSS_PI_196_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_197_OFFSET, DDRSS_PI_197_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_198_OFFSET, DDRSS_PI_198_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_199_OFFSET, DDRSS_PI_199_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_200_OFFSET, DDRSS_PI_200_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_201_OFFSET, DDRSS_PI_201_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_202_OFFSET, DDRSS_PI_202_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_203_OFFSET, DDRSS_PI_203_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_204_OFFSET, DDRSS_PI_204_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_205_OFFSET, DDRSS_PI_205_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_206_OFFSET, DDRSS_PI_206_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_207_OFFSET, DDRSS_PI_207_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_208_OFFSET, DDRSS_PI_208_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_209_OFFSET, DDRSS_PI_209_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_210_OFFSET, DDRSS_PI_210_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_211_OFFSET, DDRSS_PI_211_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_212_OFFSET, DDRSS_PI_212_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_213_OFFSET, DDRSS_PI_213_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_214_OFFSET, DDRSS_PI_214_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_215_OFFSET, DDRSS_PI_215_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_216_OFFSET, DDRSS_PI_216_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_217_OFFSET, DDRSS_PI_217_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_218_OFFSET, DDRSS_PI_218_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_219_OFFSET, DDRSS_PI_219_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_220_OFFSET, DDRSS_PI_220_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_221_OFFSET, DDRSS_PI_221_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_222_OFFSET, DDRSS_PI_222_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_223_OFFSET, DDRSS_PI_223_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_224_OFFSET, DDRSS_PI_224_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_225_OFFSET, DDRSS_PI_225_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_226_OFFSET, DDRSS_PI_226_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_227_OFFSET, DDRSS_PI_227_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_228_OFFSET, DDRSS_PI_228_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_229_OFFSET, DDRSS_PI_229_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_230_OFFSET, DDRSS_PI_230_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_231_OFFSET, DDRSS_PI_231_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_232_OFFSET, DDRSS_PI_232_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_233_OFFSET, DDRSS_PI_233_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_234_OFFSET, DDRSS_PI_234_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_235_OFFSET, DDRSS_PI_235_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_236_OFFSET, DDRSS_PI_236_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_237_OFFSET, DDRSS_PI_237_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_238_OFFSET, DDRSS_PI_238_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_239_OFFSET, DDRSS_PI_239_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_240_OFFSET, DDRSS_PI_240_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_241_OFFSET, DDRSS_PI_241_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_242_OFFSET, DDRSS_PI_242_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_243_OFFSET, DDRSS_PI_243_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_244_OFFSET, DDRSS_PI_244_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_245_OFFSET, DDRSS_PI_245_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_246_OFFSET, DDRSS_PI_246_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_247_OFFSET, DDRSS_PI_247_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_248_OFFSET, DDRSS_PI_248_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_249_OFFSET, DDRSS_PI_249_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_250_OFFSET, DDRSS_PI_250_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_251_OFFSET, DDRSS_PI_251_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_252_OFFSET, DDRSS_PI_252_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_253_OFFSET, DDRSS_PI_253_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_254_OFFSET, DDRSS_PI_254_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_255_OFFSET, DDRSS_PI_255_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_256_OFFSET, DDRSS_PI_256_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_257_OFFSET, DDRSS_PI_257_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_258_OFFSET, DDRSS_PI_258_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_259_OFFSET, DDRSS_PI_259_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_260_OFFSET, DDRSS_PI_260_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_261_OFFSET, DDRSS_PI_261_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_262_OFFSET, DDRSS_PI_262_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_263_OFFSET, DDRSS_PI_263_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_264_OFFSET, DDRSS_PI_264_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_265_OFFSET, DDRSS_PI_265_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_266_OFFSET, DDRSS_PI_266_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_267_OFFSET, DDRSS_PI_267_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_268_OFFSET, DDRSS_PI_268_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_269_OFFSET, DDRSS_PI_269_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_270_OFFSET, DDRSS_PI_270_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_271_OFFSET, DDRSS_PI_271_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_272_OFFSET, DDRSS_PI_272_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_273_OFFSET, DDRSS_PI_273_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_274_OFFSET, DDRSS_PI_274_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_275_OFFSET, DDRSS_PI_275_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_276_OFFSET, DDRSS_PI_276_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_277_OFFSET, DDRSS_PI_277_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_278_OFFSET, DDRSS_PI_278_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_279_OFFSET, DDRSS_PI_279_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_280_OFFSET, DDRSS_PI_280_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_281_OFFSET, DDRSS_PI_281_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_282_OFFSET, DDRSS_PI_282_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_283_OFFSET, DDRSS_PI_283_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_284_OFFSET, DDRSS_PI_284_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_285_OFFSET, DDRSS_PI_285_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_286_OFFSET, DDRSS_PI_286_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_287_OFFSET, DDRSS_PI_287_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_288_OFFSET, DDRSS_PI_288_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_289_OFFSET, DDRSS_PI_289_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_290_OFFSET, DDRSS_PI_290_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_291_OFFSET, DDRSS_PI_291_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_292_OFFSET, DDRSS_PI_292_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_293_OFFSET, DDRSS_PI_293_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_294_OFFSET, DDRSS_PI_294_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_295_OFFSET, DDRSS_PI_295_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_296_OFFSET, DDRSS_PI_296_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_297_OFFSET, DDRSS_PI_297_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_298_OFFSET, DDRSS_PI_298_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_299_OFFSET, DDRSS_PI_299_DATA );
-
- BOARD_DEBUG_LOG("--->>> DDR PI programming completed... <<<---\n");
-
- //Program the data slice 0
- BOARD_DEBUG_LOG("--->>> DDR PHY Data Slice 0 programming in progress.. <<<---\n");
-
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_0_OFFSET, DDRSS_PHY_00_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1_OFFSET, DDRSS_PHY_01_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_2_OFFSET, DDRSS_PHY_02_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_3_OFFSET, DDRSS_PHY_03_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_4_OFFSET, DDRSS_PHY_04_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_5_OFFSET, DDRSS_PHY_05_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_6_OFFSET, DDRSS_PHY_06_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_7_OFFSET, DDRSS_PHY_07_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_8_OFFSET, DDRSS_PHY_08_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_9_OFFSET, DDRSS_PHY_09_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_10_OFFSET, DDRSS_PHY_10_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_11_OFFSET, DDRSS_PHY_11_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_12_OFFSET, DDRSS_PHY_12_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_13_OFFSET, DDRSS_PHY_13_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_14_OFFSET, DDRSS_PHY_14_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_15_OFFSET, DDRSS_PHY_15_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_16_OFFSET, DDRSS_PHY_16_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_17_OFFSET, DDRSS_PHY_17_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_18_OFFSET, DDRSS_PHY_18_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_19_OFFSET, DDRSS_PHY_19_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_20_OFFSET, DDRSS_PHY_20_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_21_OFFSET, DDRSS_PHY_21_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_22_OFFSET, DDRSS_PHY_22_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_23_OFFSET, DDRSS_PHY_23_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_24_OFFSET, DDRSS_PHY_24_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_25_OFFSET, DDRSS_PHY_25_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_26_OFFSET, DDRSS_PHY_26_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_27_OFFSET, DDRSS_PHY_27_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_28_OFFSET, DDRSS_PHY_28_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_29_OFFSET, DDRSS_PHY_29_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_30_OFFSET, DDRSS_PHY_30_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_31_OFFSET, DDRSS_PHY_31_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_32_OFFSET, DDRSS_PHY_32_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_33_OFFSET, DDRSS_PHY_33_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_34_OFFSET, DDRSS_PHY_34_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_35_OFFSET, DDRSS_PHY_35_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_36_OFFSET, DDRSS_PHY_36_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_37_OFFSET, DDRSS_PHY_37_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_38_OFFSET, DDRSS_PHY_38_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_39_OFFSET, DDRSS_PHY_39_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_40_OFFSET, DDRSS_PHY_40_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_41_OFFSET, DDRSS_PHY_41_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_42_OFFSET, DDRSS_PHY_42_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_43_OFFSET, DDRSS_PHY_43_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_44_OFFSET, DDRSS_PHY_44_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_45_OFFSET, DDRSS_PHY_45_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_46_OFFSET, DDRSS_PHY_46_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_47_OFFSET, DDRSS_PHY_47_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_48_OFFSET, DDRSS_PHY_48_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_49_OFFSET, DDRSS_PHY_49_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_50_OFFSET, DDRSS_PHY_50_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_51_OFFSET, DDRSS_PHY_51_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_52_OFFSET, DDRSS_PHY_52_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_53_OFFSET, DDRSS_PHY_53_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_54_OFFSET, DDRSS_PHY_54_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_55_OFFSET, DDRSS_PHY_55_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_56_OFFSET, DDRSS_PHY_56_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_57_OFFSET, DDRSS_PHY_57_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_58_OFFSET, DDRSS_PHY_58_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_59_OFFSET, DDRSS_PHY_59_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_60_OFFSET, DDRSS_PHY_60_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_61_OFFSET, DDRSS_PHY_61_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_62_OFFSET, DDRSS_PHY_62_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_63_OFFSET, DDRSS_PHY_63_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_64_OFFSET, DDRSS_PHY_64_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_65_OFFSET, DDRSS_PHY_65_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_66_OFFSET, DDRSS_PHY_66_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_67_OFFSET, DDRSS_PHY_67_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_68_OFFSET, DDRSS_PHY_68_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_69_OFFSET, DDRSS_PHY_69_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_70_OFFSET, DDRSS_PHY_70_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_71_OFFSET, DDRSS_PHY_71_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_72_OFFSET, DDRSS_PHY_72_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_73_OFFSET, DDRSS_PHY_73_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_74_OFFSET, DDRSS_PHY_74_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_75_OFFSET, DDRSS_PHY_75_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_76_OFFSET, DDRSS_PHY_76_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_77_OFFSET, DDRSS_PHY_77_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_78_OFFSET, DDRSS_PHY_78_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_79_OFFSET, DDRSS_PHY_79_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_80_OFFSET, DDRSS_PHY_80_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_81_OFFSET, DDRSS_PHY_81_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_82_OFFSET, DDRSS_PHY_82_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_83_OFFSET, DDRSS_PHY_83_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_84_OFFSET, DDRSS_PHY_84_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_85_OFFSET, DDRSS_PHY_85_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_86_OFFSET, DDRSS_PHY_86_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_87_OFFSET, DDRSS_PHY_87_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_88_OFFSET, DDRSS_PHY_88_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_89_OFFSET, DDRSS_PHY_89_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_90_OFFSET, DDRSS_PHY_90_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_91_OFFSET, DDRSS_PHY_91_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_92_OFFSET, DDRSS_PHY_92_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_93_OFFSET, DDRSS_PHY_93_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_94_OFFSET, DDRSS_PHY_94_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_95_OFFSET, DDRSS_PHY_95_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_96_OFFSET, DDRSS_PHY_96_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_97_OFFSET, DDRSS_PHY_97_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_98_OFFSET, DDRSS_PHY_98_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_99_OFFSET, DDRSS_PHY_99_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_100_OFFSET, DDRSS_PHY_100_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_101_OFFSET, DDRSS_PHY_101_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_102_OFFSET, DDRSS_PHY_102_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_103_OFFSET, DDRSS_PHY_103_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_104_OFFSET, DDRSS_PHY_104_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_105_OFFSET, DDRSS_PHY_105_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_106_OFFSET, DDRSS_PHY_106_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_107_OFFSET, DDRSS_PHY_107_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_108_OFFSET, DDRSS_PHY_108_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_109_OFFSET, DDRSS_PHY_109_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_110_OFFSET, DDRSS_PHY_110_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_111_OFFSET, DDRSS_PHY_111_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_112_OFFSET, DDRSS_PHY_112_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_113_OFFSET, DDRSS_PHY_113_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_114_OFFSET, DDRSS_PHY_114_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_115_OFFSET, DDRSS_PHY_115_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_116_OFFSET, DDRSS_PHY_116_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_117_OFFSET, DDRSS_PHY_117_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_118_OFFSET, DDRSS_PHY_118_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_119_OFFSET, DDRSS_PHY_119_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_120_OFFSET, DDRSS_PHY_120_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_121_OFFSET, DDRSS_PHY_121_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_122_OFFSET, DDRSS_PHY_122_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_123_OFFSET, DDRSS_PHY_123_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_124_OFFSET, DDRSS_PHY_124_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_125_OFFSET, DDRSS_PHY_125_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_126_OFFSET, DDRSS_PHY_126_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_127_OFFSET, DDRSS_PHY_127_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_128_OFFSET, DDRSS_PHY_128_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_129_OFFSET, DDRSS_PHY_129_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_130_OFFSET, DDRSS_PHY_130_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_131_OFFSET, DDRSS_PHY_131_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_132_OFFSET, DDRSS_PHY_132_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_133_OFFSET, DDRSS_PHY_133_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_134_OFFSET, DDRSS_PHY_134_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_135_OFFSET, DDRSS_PHY_135_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_136_OFFSET, DDRSS_PHY_136_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_137_OFFSET, DDRSS_PHY_137_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_138_OFFSET, DDRSS_PHY_138_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_139_OFFSET, DDRSS_PHY_139_DATA );
- BOARD_DEBUG_LOG("--->>> DDR PHY Data Slice 0 programming completed... <<<---\n");
-
- BOARD_DEBUG_LOG("--->>> DDR PHY Data Slice 1 programming in progress.. <<<---\n");
-
- //Program the data slice 1
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_256_OFFSET, DDRSS_PHY_256_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_257_OFFSET, DDRSS_PHY_257_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_258_OFFSET, DDRSS_PHY_258_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_259_OFFSET, DDRSS_PHY_259_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_260_OFFSET, DDRSS_PHY_260_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_261_OFFSET, DDRSS_PHY_261_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_262_OFFSET, DDRSS_PHY_262_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_263_OFFSET, DDRSS_PHY_263_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_264_OFFSET, DDRSS_PHY_264_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_265_OFFSET, DDRSS_PHY_265_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_266_OFFSET, DDRSS_PHY_266_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_267_OFFSET, DDRSS_PHY_267_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_268_OFFSET, DDRSS_PHY_268_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_269_OFFSET, DDRSS_PHY_269_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_270_OFFSET, DDRSS_PHY_270_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_271_OFFSET, DDRSS_PHY_271_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_272_OFFSET, DDRSS_PHY_272_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_273_OFFSET, DDRSS_PHY_273_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_274_OFFSET, DDRSS_PHY_274_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_275_OFFSET, DDRSS_PHY_275_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_276_OFFSET, DDRSS_PHY_276_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_277_OFFSET, DDRSS_PHY_277_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_278_OFFSET, DDRSS_PHY_278_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_279_OFFSET, DDRSS_PHY_279_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_280_OFFSET, DDRSS_PHY_280_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_281_OFFSET, DDRSS_PHY_281_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_282_OFFSET, DDRSS_PHY_282_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_283_OFFSET, DDRSS_PHY_283_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_284_OFFSET, DDRSS_PHY_284_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_285_OFFSET, DDRSS_PHY_285_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_286_OFFSET, DDRSS_PHY_286_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_287_OFFSET, DDRSS_PHY_287_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_288_OFFSET, DDRSS_PHY_288_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_289_OFFSET, DDRSS_PHY_289_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_290_OFFSET, DDRSS_PHY_290_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_291_OFFSET, DDRSS_PHY_291_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_292_OFFSET, DDRSS_PHY_292_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_293_OFFSET, DDRSS_PHY_293_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_294_OFFSET, DDRSS_PHY_294_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_295_OFFSET, DDRSS_PHY_295_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_296_OFFSET, DDRSS_PHY_296_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_297_OFFSET, DDRSS_PHY_297_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_298_OFFSET, DDRSS_PHY_298_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_299_OFFSET, DDRSS_PHY_299_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_300_OFFSET, DDRSS_PHY_300_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_301_OFFSET, DDRSS_PHY_301_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_302_OFFSET, DDRSS_PHY_302_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_303_OFFSET, DDRSS_PHY_303_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_304_OFFSET, DDRSS_PHY_304_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_305_OFFSET, DDRSS_PHY_305_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_306_OFFSET, DDRSS_PHY_306_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_307_OFFSET, DDRSS_PHY_307_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_308_OFFSET, DDRSS_PHY_308_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_309_OFFSET, DDRSS_PHY_309_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_310_OFFSET, DDRSS_PHY_310_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_311_OFFSET, DDRSS_PHY_311_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_312_OFFSET, DDRSS_PHY_312_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_313_OFFSET, DDRSS_PHY_313_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_314_OFFSET, DDRSS_PHY_314_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_315_OFFSET, DDRSS_PHY_315_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_316_OFFSET, DDRSS_PHY_316_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_317_OFFSET, DDRSS_PHY_317_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_318_OFFSET, DDRSS_PHY_318_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_319_OFFSET, DDRSS_PHY_319_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_320_OFFSET, DDRSS_PHY_320_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_321_OFFSET, DDRSS_PHY_321_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_322_OFFSET, DDRSS_PHY_322_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_323_OFFSET, DDRSS_PHY_323_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_324_OFFSET, DDRSS_PHY_324_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_325_OFFSET, DDRSS_PHY_325_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_326_OFFSET, DDRSS_PHY_326_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_327_OFFSET, DDRSS_PHY_327_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_328_OFFSET, DDRSS_PHY_328_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_329_OFFSET, DDRSS_PHY_329_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_330_OFFSET, DDRSS_PHY_330_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_331_OFFSET, DDRSS_PHY_331_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_332_OFFSET, DDRSS_PHY_332_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_333_OFFSET, DDRSS_PHY_333_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_334_OFFSET, DDRSS_PHY_334_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_335_OFFSET, DDRSS_PHY_335_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_336_OFFSET, DDRSS_PHY_336_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_337_OFFSET, DDRSS_PHY_337_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_338_OFFSET, DDRSS_PHY_338_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_339_OFFSET, DDRSS_PHY_339_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_340_OFFSET, DDRSS_PHY_340_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_341_OFFSET, DDRSS_PHY_341_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_342_OFFSET, DDRSS_PHY_342_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_343_OFFSET, DDRSS_PHY_343_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_344_OFFSET, DDRSS_PHY_344_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_345_OFFSET, DDRSS_PHY_345_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_346_OFFSET, DDRSS_PHY_346_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_347_OFFSET, DDRSS_PHY_347_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_348_OFFSET, DDRSS_PHY_348_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_349_OFFSET, DDRSS_PHY_349_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_350_OFFSET, DDRSS_PHY_350_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_351_OFFSET, DDRSS_PHY_351_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_352_OFFSET, DDRSS_PHY_352_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_353_OFFSET, DDRSS_PHY_353_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_354_OFFSET, DDRSS_PHY_354_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_355_OFFSET, DDRSS_PHY_355_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_356_OFFSET, DDRSS_PHY_356_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_357_OFFSET, DDRSS_PHY_357_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_358_OFFSET, DDRSS_PHY_358_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_359_OFFSET, DDRSS_PHY_359_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_360_OFFSET, DDRSS_PHY_360_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_361_OFFSET, DDRSS_PHY_361_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_362_OFFSET, DDRSS_PHY_362_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_363_OFFSET, DDRSS_PHY_363_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_364_OFFSET, DDRSS_PHY_364_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_365_OFFSET, DDRSS_PHY_365_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_366_OFFSET, DDRSS_PHY_366_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_367_OFFSET, DDRSS_PHY_367_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_368_OFFSET, DDRSS_PHY_368_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_369_OFFSET, DDRSS_PHY_369_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_370_OFFSET, DDRSS_PHY_370_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_371_OFFSET, DDRSS_PHY_371_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_372_OFFSET, DDRSS_PHY_372_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_373_OFFSET, DDRSS_PHY_373_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_374_OFFSET, DDRSS_PHY_374_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_375_OFFSET, DDRSS_PHY_375_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_376_OFFSET, DDRSS_PHY_376_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_377_OFFSET, DDRSS_PHY_377_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_378_OFFSET, DDRSS_PHY_378_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_379_OFFSET, DDRSS_PHY_379_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_380_OFFSET, DDRSS_PHY_380_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_381_OFFSET, DDRSS_PHY_381_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_382_OFFSET, DDRSS_PHY_382_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_383_OFFSET, DDRSS_PHY_383_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_384_OFFSET, DDRSS_PHY_384_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_385_OFFSET, DDRSS_PHY_385_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_386_OFFSET, DDRSS_PHY_386_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_387_OFFSET, DDRSS_PHY_387_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_388_OFFSET, DDRSS_PHY_388_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_389_OFFSET, DDRSS_PHY_389_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_390_OFFSET, DDRSS_PHY_390_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_391_OFFSET, DDRSS_PHY_391_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_392_OFFSET, DDRSS_PHY_392_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_393_OFFSET, DDRSS_PHY_393_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_394_OFFSET, DDRSS_PHY_394_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS + DDRSS_PHY_395_OFFSET, DDRSS_PHY_395_DATA );
-
- BOARD_DEBUG_LOG("--->>> DDR PHY Data Slice 1 programming completed... <<<---\n");
- BOARD_DEBUG_LOG("--->>> DDR PHY Data Slice 2 programming in progress.. <<<---\n");
-
- //Program the data slice 2);
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_512_OFFSET, DDRSS_PHY_512_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_513_OFFSET, DDRSS_PHY_513_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_514_OFFSET, DDRSS_PHY_514_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_515_OFFSET, DDRSS_PHY_515_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_516_OFFSET, DDRSS_PHY_516_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_517_OFFSET, DDRSS_PHY_517_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_518_OFFSET, DDRSS_PHY_518_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_519_OFFSET, DDRSS_PHY_519_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_520_OFFSET, DDRSS_PHY_520_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_521_OFFSET, DDRSS_PHY_521_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_522_OFFSET, DDRSS_PHY_522_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_523_OFFSET, DDRSS_PHY_523_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_524_OFFSET, DDRSS_PHY_524_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_525_OFFSET, DDRSS_PHY_525_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_526_OFFSET, DDRSS_PHY_526_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_527_OFFSET, DDRSS_PHY_527_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_528_OFFSET, DDRSS_PHY_528_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_529_OFFSET, DDRSS_PHY_529_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_530_OFFSET, DDRSS_PHY_530_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_531_OFFSET, DDRSS_PHY_531_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_532_OFFSET, DDRSS_PHY_532_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_533_OFFSET, DDRSS_PHY_533_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_534_OFFSET, DDRSS_PHY_534_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_535_OFFSET, DDRSS_PHY_535_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_536_OFFSET, DDRSS_PHY_536_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_537_OFFSET, DDRSS_PHY_537_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_538_OFFSET, DDRSS_PHY_538_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_539_OFFSET, DDRSS_PHY_539_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_540_OFFSET, DDRSS_PHY_540_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_541_OFFSET, DDRSS_PHY_541_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_542_OFFSET, DDRSS_PHY_542_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_543_OFFSET, DDRSS_PHY_543_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_544_OFFSET, DDRSS_PHY_544_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_545_OFFSET, DDRSS_PHY_545_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_546_OFFSET, DDRSS_PHY_546_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_547_OFFSET, DDRSS_PHY_547_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_548_OFFSET, DDRSS_PHY_548_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_549_OFFSET, DDRSS_PHY_549_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_550_OFFSET, DDRSS_PHY_550_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_551_OFFSET, DDRSS_PHY_551_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_552_OFFSET, DDRSS_PHY_552_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_553_OFFSET, DDRSS_PHY_553_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_554_OFFSET, DDRSS_PHY_554_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_555_OFFSET, DDRSS_PHY_555_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_556_OFFSET, DDRSS_PHY_556_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_557_OFFSET, DDRSS_PHY_557_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_558_OFFSET, DDRSS_PHY_558_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_559_OFFSET, DDRSS_PHY_559_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_560_OFFSET, DDRSS_PHY_560_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_561_OFFSET, DDRSS_PHY_561_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_562_OFFSET, DDRSS_PHY_562_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_563_OFFSET, DDRSS_PHY_563_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_564_OFFSET, DDRSS_PHY_564_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_565_OFFSET, DDRSS_PHY_565_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_566_OFFSET, DDRSS_PHY_566_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_567_OFFSET, DDRSS_PHY_567_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_568_OFFSET, DDRSS_PHY_568_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_569_OFFSET, DDRSS_PHY_569_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_570_OFFSET, DDRSS_PHY_570_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_571_OFFSET, DDRSS_PHY_571_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_572_OFFSET, DDRSS_PHY_572_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_573_OFFSET, DDRSS_PHY_573_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_574_OFFSET, DDRSS_PHY_574_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_575_OFFSET, DDRSS_PHY_575_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_576_OFFSET, DDRSS_PHY_576_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_577_OFFSET, DDRSS_PHY_577_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_578_OFFSET, DDRSS_PHY_578_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_579_OFFSET, DDRSS_PHY_579_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_580_OFFSET, DDRSS_PHY_580_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_581_OFFSET, DDRSS_PHY_581_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_582_OFFSET, DDRSS_PHY_582_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_583_OFFSET, DDRSS_PHY_583_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_584_OFFSET, DDRSS_PHY_584_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_585_OFFSET, DDRSS_PHY_585_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_586_OFFSET, DDRSS_PHY_586_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_587_OFFSET, DDRSS_PHY_587_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_588_OFFSET, DDRSS_PHY_588_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_589_OFFSET, DDRSS_PHY_589_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_590_OFFSET, DDRSS_PHY_590_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_591_OFFSET, DDRSS_PHY_591_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_592_OFFSET, DDRSS_PHY_592_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_593_OFFSET, DDRSS_PHY_593_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_594_OFFSET, DDRSS_PHY_594_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_595_OFFSET, DDRSS_PHY_595_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_596_OFFSET, DDRSS_PHY_596_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_597_OFFSET, DDRSS_PHY_597_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_598_OFFSET, DDRSS_PHY_598_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_599_OFFSET, DDRSS_PHY_599_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_600_OFFSET, DDRSS_PHY_600_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_601_OFFSET, DDRSS_PHY_601_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_602_OFFSET, DDRSS_PHY_602_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_603_OFFSET, DDRSS_PHY_603_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_604_OFFSET, DDRSS_PHY_604_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_605_OFFSET, DDRSS_PHY_605_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_606_OFFSET, DDRSS_PHY_606_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_607_OFFSET, DDRSS_PHY_607_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_608_OFFSET, DDRSS_PHY_608_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_609_OFFSET, DDRSS_PHY_609_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_610_OFFSET, DDRSS_PHY_610_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_611_OFFSET, DDRSS_PHY_611_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_612_OFFSET, DDRSS_PHY_612_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_613_OFFSET, DDRSS_PHY_613_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_614_OFFSET, DDRSS_PHY_614_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_615_OFFSET, DDRSS_PHY_615_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_616_OFFSET, DDRSS_PHY_616_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_617_OFFSET, DDRSS_PHY_617_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_618_OFFSET, DDRSS_PHY_618_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_619_OFFSET, DDRSS_PHY_619_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_620_OFFSET, DDRSS_PHY_620_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_621_OFFSET, DDRSS_PHY_621_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_622_OFFSET, DDRSS_PHY_622_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_623_OFFSET, DDRSS_PHY_623_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_624_OFFSET, DDRSS_PHY_624_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_625_OFFSET, DDRSS_PHY_625_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_626_OFFSET, DDRSS_PHY_626_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_627_OFFSET, DDRSS_PHY_627_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_628_OFFSET, DDRSS_PHY_628_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_629_OFFSET, DDRSS_PHY_629_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_630_OFFSET, DDRSS_PHY_630_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_631_OFFSET, DDRSS_PHY_631_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_632_OFFSET, DDRSS_PHY_632_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_633_OFFSET, DDRSS_PHY_633_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_634_OFFSET, DDRSS_PHY_634_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_635_OFFSET, DDRSS_PHY_635_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_636_OFFSET, DDRSS_PHY_636_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_637_OFFSET, DDRSS_PHY_637_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_638_OFFSET, DDRSS_PHY_638_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_639_OFFSET, DDRSS_PHY_639_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_640_OFFSET, DDRSS_PHY_640_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_641_OFFSET, DDRSS_PHY_641_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_642_OFFSET, DDRSS_PHY_642_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_643_OFFSET, DDRSS_PHY_643_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_644_OFFSET, DDRSS_PHY_644_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_645_OFFSET, DDRSS_PHY_645_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_646_OFFSET, DDRSS_PHY_646_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_647_OFFSET, DDRSS_PHY_647_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_648_OFFSET, DDRSS_PHY_648_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_649_OFFSET, DDRSS_PHY_649_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_650_OFFSET, DDRSS_PHY_650_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS + DDRSS_PHY_651_OFFSET, DDRSS_PHY_651_DATA );
-
- BOARD_DEBUG_LOG("--->>> DDR PHY Data Slice 2 programming completed... <<<---\n");
- BOARD_DEBUG_LOG("--->>> DDR PHY Data Slice 3 programming in progress.. <<<---\n");
-
- //Program the data slice 3
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_768_OFFSET, DDRSS_PHY_768_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_769_OFFSET, DDRSS_PHY_769_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_770_OFFSET, DDRSS_PHY_770_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_771_OFFSET, DDRSS_PHY_771_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_772_OFFSET, DDRSS_PHY_772_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_773_OFFSET, DDRSS_PHY_773_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_774_OFFSET, DDRSS_PHY_774_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_775_OFFSET, DDRSS_PHY_775_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_776_OFFSET, DDRSS_PHY_776_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_777_OFFSET, DDRSS_PHY_777_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_778_OFFSET, DDRSS_PHY_778_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_779_OFFSET, DDRSS_PHY_779_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_780_OFFSET, DDRSS_PHY_780_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_781_OFFSET, DDRSS_PHY_781_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_782_OFFSET, DDRSS_PHY_782_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_783_OFFSET, DDRSS_PHY_783_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_784_OFFSET, DDRSS_PHY_784_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_785_OFFSET, DDRSS_PHY_785_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_786_OFFSET, DDRSS_PHY_786_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_787_OFFSET, DDRSS_PHY_787_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_788_OFFSET, DDRSS_PHY_788_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_789_OFFSET, DDRSS_PHY_789_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_790_OFFSET, DDRSS_PHY_790_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_791_OFFSET, DDRSS_PHY_791_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_792_OFFSET, DDRSS_PHY_792_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_793_OFFSET, DDRSS_PHY_793_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_794_OFFSET, DDRSS_PHY_794_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_795_OFFSET, DDRSS_PHY_795_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_796_OFFSET, DDRSS_PHY_796_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_797_OFFSET, DDRSS_PHY_797_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_798_OFFSET, DDRSS_PHY_798_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_799_OFFSET, DDRSS_PHY_799_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_800_OFFSET, DDRSS_PHY_800_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_801_OFFSET, DDRSS_PHY_801_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_802_OFFSET, DDRSS_PHY_802_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_803_OFFSET, DDRSS_PHY_803_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_804_OFFSET, DDRSS_PHY_804_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_805_OFFSET, DDRSS_PHY_805_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_806_OFFSET, DDRSS_PHY_806_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_807_OFFSET, DDRSS_PHY_807_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_808_OFFSET, DDRSS_PHY_808_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_809_OFFSET, DDRSS_PHY_809_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_810_OFFSET, DDRSS_PHY_810_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_811_OFFSET, DDRSS_PHY_811_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_812_OFFSET, DDRSS_PHY_812_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_813_OFFSET, DDRSS_PHY_813_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_814_OFFSET, DDRSS_PHY_814_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_815_OFFSET, DDRSS_PHY_815_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_816_OFFSET, DDRSS_PHY_816_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_817_OFFSET, DDRSS_PHY_817_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_818_OFFSET, DDRSS_PHY_818_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_819_OFFSET, DDRSS_PHY_819_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_820_OFFSET, DDRSS_PHY_820_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_821_OFFSET, DDRSS_PHY_821_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_822_OFFSET, DDRSS_PHY_822_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_823_OFFSET, DDRSS_PHY_823_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_824_OFFSET, DDRSS_PHY_824_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_825_OFFSET, DDRSS_PHY_825_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_826_OFFSET, DDRSS_PHY_826_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_827_OFFSET, DDRSS_PHY_827_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_828_OFFSET, DDRSS_PHY_828_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_829_OFFSET, DDRSS_PHY_829_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_830_OFFSET, DDRSS_PHY_830_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_831_OFFSET, DDRSS_PHY_831_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_832_OFFSET, DDRSS_PHY_832_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_833_OFFSET, DDRSS_PHY_833_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_834_OFFSET, DDRSS_PHY_834_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_835_OFFSET, DDRSS_PHY_835_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_836_OFFSET, DDRSS_PHY_836_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_837_OFFSET, DDRSS_PHY_837_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_838_OFFSET, DDRSS_PHY_838_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_839_OFFSET, DDRSS_PHY_839_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_840_OFFSET, DDRSS_PHY_840_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_841_OFFSET, DDRSS_PHY_841_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_842_OFFSET, DDRSS_PHY_842_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_843_OFFSET, DDRSS_PHY_843_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_844_OFFSET, DDRSS_PHY_844_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_845_OFFSET, DDRSS_PHY_845_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_846_OFFSET, DDRSS_PHY_846_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_847_OFFSET, DDRSS_PHY_847_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_848_OFFSET, DDRSS_PHY_848_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_849_OFFSET, DDRSS_PHY_849_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_850_OFFSET, DDRSS_PHY_850_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_851_OFFSET, DDRSS_PHY_851_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_852_OFFSET, DDRSS_PHY_852_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_853_OFFSET, DDRSS_PHY_853_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_854_OFFSET, DDRSS_PHY_854_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_855_OFFSET, DDRSS_PHY_855_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_856_OFFSET, DDRSS_PHY_856_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_857_OFFSET, DDRSS_PHY_857_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_858_OFFSET, DDRSS_PHY_858_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_859_OFFSET, DDRSS_PHY_859_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_860_OFFSET, DDRSS_PHY_860_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_861_OFFSET, DDRSS_PHY_861_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_862_OFFSET, DDRSS_PHY_862_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_863_OFFSET, DDRSS_PHY_863_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_864_OFFSET, DDRSS_PHY_864_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_865_OFFSET, DDRSS_PHY_865_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_866_OFFSET, DDRSS_PHY_866_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_867_OFFSET, DDRSS_PHY_867_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_868_OFFSET, DDRSS_PHY_868_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_869_OFFSET, DDRSS_PHY_869_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_870_OFFSET, DDRSS_PHY_870_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_871_OFFSET, DDRSS_PHY_871_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_872_OFFSET, DDRSS_PHY_872_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_873_OFFSET, DDRSS_PHY_873_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_874_OFFSET, DDRSS_PHY_874_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_875_OFFSET, DDRSS_PHY_875_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_876_OFFSET, DDRSS_PHY_876_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_877_OFFSET, DDRSS_PHY_877_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_878_OFFSET, DDRSS_PHY_878_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_879_OFFSET, DDRSS_PHY_879_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_880_OFFSET, DDRSS_PHY_880_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_881_OFFSET, DDRSS_PHY_881_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_882_OFFSET, DDRSS_PHY_882_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_883_OFFSET, DDRSS_PHY_883_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_884_OFFSET, DDRSS_PHY_884_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_885_OFFSET, DDRSS_PHY_885_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_886_OFFSET, DDRSS_PHY_886_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_887_OFFSET, DDRSS_PHY_887_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_888_OFFSET, DDRSS_PHY_888_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_889_OFFSET, DDRSS_PHY_889_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_890_OFFSET, DDRSS_PHY_890_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_891_OFFSET, DDRSS_PHY_891_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_892_OFFSET, DDRSS_PHY_892_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_893_OFFSET, DDRSS_PHY_893_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_894_OFFSET, DDRSS_PHY_894_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_895_OFFSET, DDRSS_PHY_895_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_896_OFFSET, DDRSS_PHY_896_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_897_OFFSET, DDRSS_PHY_897_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_898_OFFSET, DDRSS_PHY_898_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_899_OFFSET, DDRSS_PHY_899_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_900_OFFSET, DDRSS_PHY_900_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_901_OFFSET, DDRSS_PHY_901_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_902_OFFSET, DDRSS_PHY_902_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_903_OFFSET, DDRSS_PHY_903_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_904_OFFSET, DDRSS_PHY_904_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_905_OFFSET, DDRSS_PHY_905_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_906_OFFSET, DDRSS_PHY_906_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS + DDRSS_PHY_907_OFFSET, DDRSS_PHY_907_DATA );
-
- BOARD_DEBUG_LOG("--->>> DDR PHY Data Slice 3 programming completed... <<<---\n");
-
- BOARD_DEBUG_LOG("--->>> DDR PHY Address slice 0 programming in progress.. <<<---\n");
- //Program the Addres slice 0
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1024_OFFSET, DDRSS_PHY_1024_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1025_OFFSET, DDRSS_PHY_1025_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1026_OFFSET, DDRSS_PHY_1026_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1027_OFFSET, DDRSS_PHY_1027_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1028_OFFSET, DDRSS_PHY_1028_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1029_OFFSET, DDRSS_PHY_1029_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1030_OFFSET, DDRSS_PHY_1030_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1031_OFFSET, DDRSS_PHY_1031_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1032_OFFSET, DDRSS_PHY_1032_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1033_OFFSET, DDRSS_PHY_1033_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1034_OFFSET, DDRSS_PHY_1034_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1035_OFFSET, DDRSS_PHY_1035_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1036_OFFSET, DDRSS_PHY_1036_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1037_OFFSET, DDRSS_PHY_1037_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1038_OFFSET, DDRSS_PHY_1038_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1039_OFFSET, DDRSS_PHY_1039_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1040_OFFSET, DDRSS_PHY_1040_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1041_OFFSET, DDRSS_PHY_1041_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1042_OFFSET, DDRSS_PHY_1042_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1043_OFFSET, DDRSS_PHY_1043_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1044_OFFSET, DDRSS_PHY_1044_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1045_OFFSET, DDRSS_PHY_1045_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1046_OFFSET, DDRSS_PHY_1046_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1047_OFFSET, DDRSS_PHY_1047_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1048_OFFSET, DDRSS_PHY_1048_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1049_OFFSET, DDRSS_PHY_1049_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1050_OFFSET, DDRSS_PHY_1050_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1051_OFFSET, DDRSS_PHY_1051_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1052_OFFSET, DDRSS_PHY_1052_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1053_OFFSET, DDRSS_PHY_1053_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1054_OFFSET, DDRSS_PHY_1054_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1055_OFFSET, DDRSS_PHY_1055_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1056_OFFSET, DDRSS_PHY_1056_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1057_OFFSET, DDRSS_PHY_1057_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1058_OFFSET, DDRSS_PHY_1058_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1059_OFFSET, DDRSS_PHY_1059_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1060_OFFSET, DDRSS_PHY_1060_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1061_OFFSET, DDRSS_PHY_1061_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1062_OFFSET, DDRSS_PHY_1062_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1063_OFFSET, DDRSS_PHY_1063_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1064_OFFSET, DDRSS_PHY_1064_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1065_OFFSET, DDRSS_PHY_1065_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1066_OFFSET, DDRSS_PHY_1066_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1067_OFFSET, DDRSS_PHY_1067_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1068_OFFSET, DDRSS_PHY_1068_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1069_OFFSET, DDRSS_PHY_1069_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1070_OFFSET, DDRSS_PHY_1070_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1071_OFFSET, DDRSS_PHY_1071_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1072_OFFSET, DDRSS_PHY_1072_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1073_OFFSET, DDRSS_PHY_1073_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1074_OFFSET, DDRSS_PHY_1074_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS + DDRSS_PHY_1075_OFFSET, DDRSS_PHY_1075_DATA );
-
- BOARD_DEBUG_LOG("--->>> DDR PHY Address Slice 0 programming completed... <<<---\n");
- BOARD_DEBUG_LOG("--->>> DDR PHY programming in progress.. <<<---\n");
-
- BOARD_DEBUG_LOG("--->>> Set PHY registers for F1 freq... <<<---\n");
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1281_OFFSET, 0x00000100 );
-
- //Program the PHY
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1280_OFFSET, DDRSS_PHY_1280_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1281_OFFSET, DDRSS_PHY_1281_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1282_OFFSET, DDRSS_PHY_1282_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1283_OFFSET, DDRSS_PHY_1283_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1284_OFFSET, DDRSS_PHY_1284_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1285_OFFSET, DDRSS_PHY_1285_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1286_OFFSET, DDRSS_PHY_1286_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1287_OFFSET, DDRSS_PHY_1287_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1288_OFFSET, DDRSS_PHY_1288_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1289_OFFSET, DDRSS_PHY_1289_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1290_OFFSET, DDRSS_PHY_1290_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1291_OFFSET, DDRSS_PHY_1291_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1292_OFFSET, DDRSS_PHY_1292_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1293_OFFSET, DDRSS_PHY_1293_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1294_OFFSET, DDRSS_PHY_1294_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1295_OFFSET, DDRSS_PHY_1295_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1296_OFFSET, DDRSS_PHY_1296_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1297_OFFSET, DDRSS_PHY_1297_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1298_OFFSET, DDRSS_PHY_1298_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1299_OFFSET, DDRSS_PHY_1299_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1300_OFFSET, DDRSS_PHY_1300_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1301_OFFSET, DDRSS_PHY_1301_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1302_OFFSET, DDRSS_PHY_1302_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1303_OFFSET, DDRSS_PHY_1303_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1304_OFFSET, DDRSS_PHY_1304_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1305_OFFSET, DDRSS_PHY_1305_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1306_OFFSET, DDRSS_PHY_1306_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1307_OFFSET, DDRSS_PHY_1307_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1308_OFFSET, DDRSS_PHY_1308_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1309_OFFSET, DDRSS_PHY_1309_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1310_OFFSET, DDRSS_PHY_1310_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1311_OFFSET, DDRSS_PHY_1311_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1312_OFFSET, DDRSS_PHY_1312_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1313_OFFSET, DDRSS_PHY_1313_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1314_OFFSET, DDRSS_PHY_1314_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1315_OFFSET, DDRSS_PHY_1315_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1316_OFFSET, DDRSS_PHY_1316_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1317_OFFSET, DDRSS_PHY_1317_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1318_OFFSET, DDRSS_PHY_1318_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1319_OFFSET, DDRSS_PHY_1319_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1320_OFFSET, DDRSS_PHY_1320_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1321_OFFSET, DDRSS_PHY_1321_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1322_OFFSET, DDRSS_PHY_1322_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1323_OFFSET, DDRSS_PHY_1323_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1324_OFFSET, DDRSS_PHY_1324_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1325_OFFSET, DDRSS_PHY_1325_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1326_OFFSET, DDRSS_PHY_1326_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1327_OFFSET, DDRSS_PHY_1327_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1328_OFFSET, DDRSS_PHY_1328_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1329_OFFSET, DDRSS_PHY_1329_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1330_OFFSET, DDRSS_PHY_1330_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1331_OFFSET, DDRSS_PHY_1331_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1332_OFFSET, DDRSS_PHY_1332_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1333_OFFSET, DDRSS_PHY_1333_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1334_OFFSET, DDRSS_PHY_1334_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1335_OFFSET, DDRSS_PHY_1335_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1336_OFFSET, DDRSS_PHY_1336_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1337_OFFSET, DDRSS_PHY_1337_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1338_OFFSET, DDRSS_PHY_1338_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1339_OFFSET, DDRSS_PHY_1339_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1340_OFFSET, DDRSS_PHY_1340_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1341_OFFSET, DDRSS_PHY_1341_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1342_OFFSET, DDRSS_PHY_1342_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1343_OFFSET, DDRSS_PHY_1343_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1344_OFFSET, DDRSS_PHY_1344_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1345_OFFSET, DDRSS_PHY_1345_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1346_OFFSET, DDRSS_PHY_1346_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1347_OFFSET, DDRSS_PHY_1347_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1348_OFFSET, DDRSS_PHY_1348_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1349_OFFSET, DDRSS_PHY_1349_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1350_OFFSET, DDRSS_PHY_1350_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1351_OFFSET, DDRSS_PHY_1351_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1352_OFFSET, DDRSS_PHY_1352_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1353_OFFSET, DDRSS_PHY_1353_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1354_OFFSET, DDRSS_PHY_1354_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1355_OFFSET, DDRSS_PHY_1355_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1356_OFFSET, DDRSS_PHY_1356_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1357_OFFSET, DDRSS_PHY_1357_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1358_OFFSET, DDRSS_PHY_1358_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1359_OFFSET, DDRSS_PHY_1359_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1360_OFFSET, DDRSS_PHY_1360_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1361_OFFSET, DDRSS_PHY_1361_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1362_OFFSET, DDRSS_PHY_1362_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1363_OFFSET, DDRSS_PHY_1363_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1364_OFFSET, DDRSS_PHY_1364_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1365_OFFSET, DDRSS_PHY_1365_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1366_OFFSET, DDRSS_PHY_1366_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1367_OFFSET, DDRSS_PHY_1367_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1368_OFFSET, DDRSS_PHY_1368_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1369_OFFSET, DDRSS_PHY_1369_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1370_OFFSET, DDRSS_PHY_1370_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1371_OFFSET, DDRSS_PHY_1371_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1372_OFFSET, DDRSS_PHY_1372_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1373_OFFSET, DDRSS_PHY_1373_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1374_OFFSET, DDRSS_PHY_1374_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1375_OFFSET, DDRSS_PHY_1375_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1376_OFFSET, DDRSS_PHY_1376_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1377_OFFSET, DDRSS_PHY_1377_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1378_OFFSET, DDRSS_PHY_1378_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1379_OFFSET, DDRSS_PHY_1379_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1380_OFFSET, DDRSS_PHY_1380_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1381_OFFSET, DDRSS_PHY_1381_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1382_OFFSET, DDRSS_PHY_1382_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1383_OFFSET, DDRSS_PHY_1383_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1384_OFFSET, DDRSS_PHY_1384_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1385_OFFSET, DDRSS_PHY_1385_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1386_OFFSET, DDRSS_PHY_1386_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1387_OFFSET, DDRSS_PHY_1387_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1388_OFFSET, DDRSS_PHY_1388_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1389_OFFSET, DDRSS_PHY_1389_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1390_OFFSET, DDRSS_PHY_1390_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1391_OFFSET, DDRSS_PHY_1391_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1392_OFFSET, DDRSS_PHY_1392_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1393_OFFSET, DDRSS_PHY_1393_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1394_OFFSET, DDRSS_PHY_1394_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1395_OFFSET, DDRSS_PHY_1395_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1396_OFFSET, DDRSS_PHY_1396_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1397_OFFSET, DDRSS_PHY_1397_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1398_OFFSET, DDRSS_PHY_1398_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1399_OFFSET, DDRSS_PHY_1399_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1400_OFFSET, DDRSS_PHY_1400_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1401_OFFSET, DDRSS_PHY_1401_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1402_OFFSET, DDRSS_PHY_1402_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1403_OFFSET, DDRSS_PHY_1403_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1404_OFFSET, DDRSS_PHY_1404_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1405_OFFSET, DDRSS_PHY_1405_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1406_OFFSET, DDRSS_PHY_1406_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1407_OFFSET, DDRSS_PHY_1407_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1408_OFFSET, DDRSS_PHY_1408_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1409_OFFSET, DDRSS_PHY_1409_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1410_OFFSET, DDRSS_PHY_1410_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1411_OFFSET, DDRSS_PHY_1411_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1412_OFFSET, DDRSS_PHY_1412_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1413_OFFSET, DDRSS_PHY_1413_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1414_OFFSET, DDRSS_PHY_1414_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1415_OFFSET, DDRSS_PHY_1415_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1416_OFFSET, DDRSS_PHY_1416_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1417_OFFSET, DDRSS_PHY_1417_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1418_OFFSET, DDRSS_PHY_1418_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1419_OFFSET, DDRSS_PHY_1419_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1420_OFFSET, DDRSS_PHY_1420_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1421_OFFSET, DDRSS_PHY_1421_DATA );
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PHY_Core_REGISTER_BLOCK__OFFS + DDRSS_PHY_1422_OFFSET, DDRSS_PHY_1422_DATA );
-
- BOARD_DEBUG_LOG("--->>> DDR PHY programming completed... <<<---\n");
-
- BOARD_DEBUG_LOG("--->>> Set PHY registers for F2 freq... <<<---\n");
-
- //trigger the start bit
-
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_0_OFFSET, 0x00000B01 );
-
- //BOARD_DEBUG_LOG("--->>> DDR PI initialization started... <<<---\n");
- BOARD_delay(100000);
-
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_0_OFFSET, 0x00000B01 );
-
- //Partition5 lockkey0
- HW_WR_REG32((M3_RAT_OFFSET + 0x115008), 0x68EF3490);
- //Partition5 lockkey1
- HW_WR_REG32((M3_RAT_OFFSET + 0x11500C), 0xD172BC5A);
- Board_DDRChangeFreqAck();
-
- BOARD_DEBUG_LOG("--->>> Waiting..CP1 <<<---\n");
-
- while(((HW_RD_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_79_OFFSET)) & 0x1) != 0x1);
-
- BOARD_DEBUG_LOG("--->>> Waiting..CP2 <<<---\n");
-
- while((HW_RD_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_293_OFFSET)!= 0x200)); //181108 rls - change to 293
-
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_PI_REGISTER_BLOCK__OFFS + DDRSS_PI_80_OFFSET, 0x1 );
-
- HW_WR_REG32(J7ES_DDR_SS_BASE + DDRSS_CTL_295_OFFSET, 0x200 );
-
- BOARD_DEBUG_LOG("--->>> DDR 3733MTs Initialization completed... <<<---\n");
-
- return BOARD_SOK;
-}
+/******************************************************************************\r
+ * Copyright (c) 2019 Texas Instruments Incorporated - http://www.ti.com\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the\r
+ * distribution.\r
+ *\r
+ * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ *****************************************************************************/\r
+\r
+#include "board_ddr.h"\r
+\r
+/* Global variables */\r
+static LPDDR4_Config gBoardDdrCfg;\r
+static LPDDR4_PrivateData gBoardDdrPd;\r
+\r
+/**\r
+ * \brief Set DDR PLL to bypass, efectively 20MHz or 19.2MHz (on silicon).\r
+ *\r
+ * \return none\r
+ */\r
+static void Board_DDRSetPLLExtBypass(void)\r
+{\r
+ uint32_t addrOffset = 0x00000000;\r
+ uint32_t baseAddr = CSL_PLL0_CFG_BASE;\r
+ uint32_t regVal;\r
+ uint32_t fieldVal;\r
+ uint32_t regAddr;\r
+\r
+ fieldVal = 1;\r
+ regAddr = (baseAddr + addrOffset + (DDR_PLL_INDEX * 0x1000) + CONTROL);\r
+ regVal = HW_RD_REG32(regAddr);\r
+ regVal |= (fieldVal << 31);\r
+ HW_WR_REG32(regAddr, regVal);\r
+}\r
+\r
+/**\r
+ * \brief Set DDR PLL clock value\r
+ *\r
+ * \return BOARD_SOK in case of success or appropriate error code\r
+ */\r
+static Board_STATUS Board_DDRSetPLLClock(void)\r
+{\r
+ Board_STATUS status = BOARD_SOK;\r
+\r
+ status = Board_PLLInit(TISCI_DEV_DDR0,\r
+ TISCI_DEV_DDR0_DDRSS_DDR_PLL_CLK,\r
+ DDRSS_PLL_FREQUENCY_1);\r
+ if(status != BOARD_SOK)\r
+ {\r
+ BOARD_DEBUG_LOG("Failed to Set the DDR PLL Clock Frequency\n");\r
+ }\r
+\r
+ return status;\r
+}\r
+\r
+/**\r
+ * \brief Controls the DDR PLL clock change sequence during inits\r
+ *\r
+ * \return None\r
+ */\r
+static void Board_DDRChangeFreqAck(void)\r
+{\r
+ uint32_t reqType;\r
+ uint32_t regVal;\r
+ volatile uint32_t counter;\r
+ volatile uint32_t counter2;\r
+ volatile uint32_t temp = 0;\r
+\r
+ temp = temp; /* To suppress compiler warning */\r
+ BOARD_DEBUG_LOG("--->>> LPDDR4 Initialization is in progress ... <<<---\n");\r
+\r
+ for(counter = 0; counter < DDRSS_PLL_FHS_CNT; counter++)\r
+ {\r
+ /* wait for freq change request */\r
+ regVal = HW_RD_REG32(BOARD_DDR_FSP_CLKCHNG_REQ_ADDR) & 0x80;\r
+ BOARD_DEBUG_LOG("Reg Value: %d \n", regVal);\r
+\r
+ while(regVal == 0x0)\r
+ {\r
+ regVal = HW_RD_REG32(BOARD_DDR_FSP_CLKCHNG_REQ_ADDR) & 0x80;\r
+ BOARD_DEBUG_LOG("Reg Value: %d \n", regVal);\r
+ }\r
+\r
+ reqType = HW_RD_REG32(BOARD_DDR_FSP_CLKCHNG_REQ_ADDR) & 0x03;\r
+ BOARD_DEBUG_LOG("Frequency Change type %d request from Controller \n", reqType);\r
+\r
+ if(reqType == 1)\r
+ {\r
+ Board_DDRSetPLLClock();\r
+ }\r
+ else if(reqType == 2)\r
+ {\r
+ Board_DDRSetPLLClock();\r
+ }\r
+ else if(reqType == 0)\r
+ {\r
+ Board_DDRSetPLLExtBypass();\r
+ }\r
+ else\r
+ {\r
+ BOARD_DEBUG_LOG("Invalid Request Type\n");\r
+ }\r
+\r
+ counter2 = 0;\r
+ while(counter2 < 200)\r
+ {\r
+ temp = HW_RD_REG32(BOARD_DDR_FSP_CLKCHNG_REQ_ADDR);\r
+ counter2++;\r
+ }\r
+\r
+ HW_WR_REG32(BOARD_DDR_FSP_CLKCHNG_ACK_ADDR, 0x1);\r
+\r
+ counter2 = 0;\r
+ while(counter2 < 10)\r
+ {\r
+ temp = HW_RD_REG32(BOARD_DDR_FSP_CLKCHNG_REQ_ADDR);\r
+ counter2++;\r
+ }\r
+\r
+ while((HW_RD_REG32(BOARD_DDR_FSP_CLKCHNG_REQ_ADDR) & 0x80) == 0x80);\r
+\r
+ counter2 = 0;\r
+ while(counter2 < 10)\r
+ {\r
+ temp = HW_RD_REG32(BOARD_DDR_FSP_CLKCHNG_REQ_ADDR);\r
+ counter2++;\r
+ }\r
+\r
+ HW_WR_REG32(BOARD_DDR_FSP_CLKCHNG_ACK_ADDR, 0x0);\r
+\r
+ counter2 = 0;\r
+ while(counter2 < 10)\r
+ {\r
+ temp= HW_RD_REG32(BOARD_DDR_FSP_CLKCHNG_REQ_ADDR);\r
+ counter2++;\r
+ }\r
+ }\r
+\r
+ BOARD_DEBUG_LOG("--->>> Frequency Change request handshake is completed... <<<---\n");\r
+}\r
+\r
+/**\r
+ * \brief Function to handle the configuration requests from DDR lib\r
+ *\r
+ * \return None\r
+ */\r
+static void Board_DDRInfoHandler(const LPDDR4_PrivateData *pd, LPDDR4_InfoType infotype)\r
+{\r
+ if (infotype == LPDDR4_DRV_SOC_PLL_UPDATE)\r
+ {\r
+ Board_DDRChangeFreqAck();\r
+ }\r
+}\r
+\r
+/**\r
+ * \brief DDR probe function\r
+ *\r
+ * \return BOARD_SOK in case of success or appropriate error code\r
+ */\r
+static Board_STATUS Board_DDRProbe(void)\r
+{\r
+ uint32_t status = 0U;\r
+ uint16_t configsize = 0U;\r
+\r
+ status = LPDDR4_Probe(&gBoardDdrCfg, &configsize);\r
+\r
+ if ((status != 0) || (configsize != sizeof(LPDDR4_PrivateData)) ||\r
+ (configsize > BOARD_DDR_SRAM_MAX))\r
+ {\r
+ BOARD_DEBUG_LOG("Board_DDRProbe: FAIL\n");\r
+ return BOARD_FAIL;\r
+ }\r
+ else\r
+ {\r
+ BOARD_DEBUG_LOG("Board_DDRProbe: PASS\n");\r
+ }\r
+\r
+ return BOARD_SOK;\r
+}\r
+\r
+/**\r
+ * \brief DDR driver initialization function\r
+ *\r
+ * \return BOARD_SOK in case of success or appropriate error code\r
+ */\r
+static Board_STATUS Board_DDRInitDrv(void)\r
+{\r
+ uint32_t status = 0U;\r
+\r
+ if ((sizeof(gBoardDdrPd) != sizeof(LPDDR4_PrivateData)) ||\r
+ (sizeof(gBoardDdrPd) > BOARD_DDR_SRAM_MAX))\r
+ {\r
+ BOARD_DEBUG_LOG("Board_DDRInitDrv: FAIL\n");\r
+ return BOARD_FAIL;\r
+ }\r
+\r
+ gBoardDdrCfg.ctlBase = (struct LPDDR4_CtlRegs_s *)BOARD_DDR_SS_BASE;\r
+ gBoardDdrCfg.infoHandler = (LPDDR4_InfoCallback) Board_DDRInfoHandler;\r
+\r
+ status = LPDDR4_Init(&gBoardDdrPd, &gBoardDdrCfg);\r
+\r
+ if ((status > 0U) ||\r
+ (gBoardDdrPd.ctlBase != (struct LPDDR4_CtlRegs_s *)gBoardDdrCfg.ctlBase) ||\r
+ (gBoardDdrPd.ctlInterruptHandler != gBoardDdrCfg.ctlInterruptHandler) ||\r
+ (gBoardDdrPd.phyIndepInterruptHandler != gBoardDdrCfg.phyIndepInterruptHandler))\r
+ {\r
+ BOARD_DEBUG_LOG("Board_DDRInitDrv: FAIL\n");\r
+ return BOARD_FAIL;\r
+ }\r
+ else\r
+ {\r
+ BOARD_DEBUG_LOG("Board_DDRInitDrv: PASS\n");\r
+ }\r
+\r
+ return BOARD_SOK;\r
+}\r
+\r
+/**\r
+ * \brief DDR registers initialization function\r
+ *\r
+ * \return BOARD_SOK in case of success or appropriate error code\r
+ */\r
+static Board_STATUS Board_DDRHWRegInit(void)\r
+{\r
+ uint32_t status = 0U;\r
+\r
+ status = LPDDR4_WriteCtlConfig(&gBoardDdrPd,\r
+ DDRSS_ctlReg,\r
+ DDRSS_ctlRegNum,\r
+ (uint16_t)DDRSS_CTL_REG_INIT_COUNT);\r
+ if (!status)\r
+ {\r
+ status = LPDDR4_WritePhyIndepConfig(&gBoardDdrPd,\r
+ DDRSS_phyIndepReg,\r
+ DDRSS_phyIndepRegNum,\r
+ (uint16_t)DDRSS_PHY_INDEP_REG_INIT_COUNT);\r
+ }\r
+\r
+ if (!status)\r
+ {\r
+ status = LPDDR4_WritePhyConfig(&gBoardDdrPd,\r
+ DDRSS_phyReg,\r
+ DDRSS_phyRegNum,\r
+ (uint16_t)DDRSS_PHY_REG_INIT_COUNT);\r
+ }\r
+\r
+ if (status)\r
+ {\r
+ BOARD_DEBUG_LOG(" ERROR: Board_DDRHWRegInit failed!!\n");\r
+ return BOARD_FAIL;\r
+ }\r
+\r
+ return BOARD_SOK;\r
+}\r
+\r
+/**\r
+ * \brief DDR start function\r
+ *\r
+ * \return BOARD_SOK in case of success or appropriate error code\r
+ */\r
+static Board_STATUS Board_DDRStart(void)\r
+{\r
+ uint32_t status = 0U;\r
+ uint32_t regval = 0U;\r
+ uint32_t offset = 0U;\r
+\r
+ offset = BOARD_DDR_CTL_REG_OFFSET;\r
+\r
+ status = LPDDR4_ReadReg(&gBoardDdrPd, LPDDR4_CTL_REGS, offset, ®val);\r
+ if ((status > 0U) || ((regval & 0x1U) != 0U))\r
+ {\r
+ BOARD_DEBUG_LOG("Board_DDRStart: FAIL\n");\r
+ return BOARD_FAIL;\r
+ }\r
+\r
+ status = LPDDR4_Start(&gBoardDdrPd);\r
+ if (status > 0U)\r
+ {\r
+ BOARD_DEBUG_LOG("Board_DDRStart: FAIL\n");\r
+ return BOARD_FAIL;\r
+ }\r
+\r
+ status = LPDDR4_ReadReg(&gBoardDdrPd, LPDDR4_CTL_REGS, offset, ®val);\r
+ if ((status > 0U) || ((regval & 0x1U) != 1U))\r
+ {\r
+ BOARD_DEBUG_LOG("Board_DDRStart: FAIL\n");\r
+ return BOARD_FAIL;\r
+ }\r
+ else\r
+ {\r
+ BOARD_DEBUG_LOG("LPDDR4_Start: PASS\n");\r
+ }\r
+\r
+ return BOARD_SOK;\r
+}\r
+\r
+/**\r
+ * \brief DDR4 Initialization function\r
+ *\r
+ * Invokes DDR CSL APIs to configure the DDR timing parameters\r
+ *\r
+ * \return BOARD_SOK in case of success or appropriate error code\r
+ *\r
+ */\r
+Board_STATUS Board_DDRInit(void)\r
+{\r
+ Board_STATUS status = BOARD_SOK;\r
+ /* PLL should be bypassed while configuring the DDR */\r
+ Board_DDRSetPLLExtBypass();\r
+\r
+ /* Partition5 lockkey0 */\r
+ HW_WR_REG32(BOARD_CTRL_MMR_PART5_LOCK0, KICK0_UNLOCK);\r
+ /* Partition5 lockkey1 */\r
+ HW_WR_REG32(BOARD_CTRL_MMR_PART5_LOCK1, KICK1_UNLOCK);\r
+\r
+ status = Board_DDRProbe();\r
+ if(status != BOARD_SOK)\r
+ {\r
+ return status;\r
+ }\r
+\r
+ status = Board_DDRInitDrv();\r
+ if(status != BOARD_SOK)\r
+ {\r
+ return status;\r
+ }\r
+\r
+ status = Board_DDRHWRegInit();\r
+ if(status != BOARD_SOK)\r
+ {\r
+ return status;\r
+ }\r
+\r
+ status = Board_DDRStart();\r
+ if(status != BOARD_SOK)\r
+ {\r
+ return status;\r
+ }\r
+\r
+ return status;\r
+}\r
diff --git a/packages/ti/board/src/j721e_evm/board_init.c b/packages/ti/board/src/j721e_evm/board_init.c
index b5d4373cf8cf150a6ea4a40035ea3435081c785f..b47f8a8269256f49632a7d147f085708c51c61f7 100755 (executable)
if(gBoardSysInitDone == 0)
{
Sciclient_configPrmsInit(&config);
+ #if defined(BUILD_C7X_1)
+ config.isSecureMode = 1;
+ #endif
ret = Sciclient_init(&config);
if(ret != 0)
diff --git a/packages/ti/board/src/j721e_evm/include/board_ddr.h b/packages/ti/board/src/j721e_evm/include/board_ddr.h
#ifndef BOARD_DDR_H_\r
#define BOARD_DDR_H_\r
\r
-#include "board_pll.h"\r
-\r
-#include "ti/csl/soc.h"\r
+#include <ti/csl/soc.h>\r
#include <ti/csl/hw_types.h>\r
+#include <ti/csl/csl_lpddr.h>\r
+#include <ti/drv/sciclient/sciclient.h>\r
\r
+#include "board_ddrRegInit.h"\r
+#include "board.h"\r
+#include "board_pll.h"\r
+#include "board_utils.h"\r
#include "board_internal.h"\r
\r
-#include "board_power.h"\r
-\r
#ifdef __cplusplus\r
extern "C" {\r
#endif\r
\r
-#define CAL_CONTROL (0x60)\r
-#define CAL_STATUS (0x64)\r
-#define FRAC_F_PLL 1\r
-\r
-/** File Name: DDRSS_addr_map_sfr_offs_ew_32bit.gel */\r
-\r
-#define J7ES_DDR_SS_BASE 0x02990000U //When running from Main cores\r
-#define M3_RAT_OFFSET 0x00000000 //Direct access. \r
-\r
-#define DDRSS_PLL_FREQUENCY (933000000U)\r
-#define DDRSS_PLL_FHS_CNT (10U)\r
-\r
-#define DDRSS_CTL_0_OFFSET 0x0\r
-#define DDRSS_CTL_1_OFFSET 0x4\r
-#define DDRSS_CTL_2_OFFSET 0x8\r
-#define DDRSS_CTL_3_OFFSET 0xc\r
-#define DDRSS_CTL_4_OFFSET 0x10\r
-#define DDRSS_CTL_5_OFFSET 0x14\r
-#define DDRSS_CTL_6_OFFSET 0x18\r
-#define DDRSS_CTL_7_OFFSET 0x1c\r
-#define DDRSS_CTL_8_OFFSET 0x20\r
-#define DDRSS_CTL_9_OFFSET 0x24\r
-#define DDRSS_CTL_10_OFFSET 0x28\r
-#define DDRSS_CTL_11_OFFSET 0x2c\r
-#define DDRSS_CTL_12_OFFSET 0x30\r
-#define DDRSS_CTL_13_OFFSET 0x34\r
-#define DDRSS_CTL_14_OFFSET 0x38\r
-#define DDRSS_CTL_15_OFFSET 0x3c\r
-#define DDRSS_CTL_16_OFFSET 0x40\r
-#define DDRSS_CTL_17_OFFSET 0x44\r
-#define DDRSS_CTL_18_OFFSET 0x48\r
-#define DDRSS_CTL_19_OFFSET 0x4c\r
-#define DDRSS_CTL_20_OFFSET 0x50\r
-#define DDRSS_CTL_21_OFFSET 0x54\r
-#define DDRSS_CTL_22_OFFSET 0x58\r
-#define DDRSS_CTL_23_OFFSET 0x5c\r
-#define DDRSS_CTL_24_OFFSET 0x60\r
-#define DDRSS_CTL_25_OFFSET 0x64\r
-#define DDRSS_CTL_26_OFFSET 0x68\r
-#define DDRSS_CTL_27_OFFSET 0x6c\r
-#define DDRSS_CTL_28_OFFSET 0x70\r
-#define DDRSS_CTL_29_OFFSET 0x74\r
-#define DDRSS_CTL_30_OFFSET 0x78\r
-#define DDRSS_CTL_31_OFFSET 0x7c\r
-#define DDRSS_CTL_32_OFFSET 0x80\r
-#define DDRSS_CTL_33_OFFSET 0x84\r
-#define DDRSS_CTL_34_OFFSET 0x88\r
-#define DDRSS_CTL_35_OFFSET 0x8c\r
-#define DDRSS_CTL_36_OFFSET 0x90\r
-#define DDRSS_CTL_37_OFFSET 0x94\r
-#define DDRSS_CTL_38_OFFSET 0x98\r
-#define DDRSS_CTL_39_OFFSET 0x9c\r
-#define DDRSS_CTL_40_OFFSET 0xa0\r
-#define DDRSS_CTL_41_OFFSET 0xa4\r
-#define DDRSS_CTL_42_OFFSET 0xa8\r
-#define DDRSS_CTL_43_OFFSET 0xac\r
-#define DDRSS_CTL_44_OFFSET 0xb0\r
-#define DDRSS_CTL_45_OFFSET 0xb4\r
-#define DDRSS_CTL_46_OFFSET 0xb8\r
-#define DDRSS_CTL_47_OFFSET 0xbc\r
-#define DDRSS_CTL_48_OFFSET 0xc0\r
-#define DDRSS_CTL_49_OFFSET 0xc4\r
-#define DDRSS_CTL_50_OFFSET 0xc8\r
-#define DDRSS_CTL_51_OFFSET 0xcc\r
-#define DDRSS_CTL_52_OFFSET 0xd0\r
-#define DDRSS_CTL_53_OFFSET 0xd4\r
-#define DDRSS_CTL_54_OFFSET 0xd8\r
-#define DDRSS_CTL_55_OFFSET 0xdc\r
-#define DDRSS_CTL_56_OFFSET 0xe0\r
-#define DDRSS_CTL_57_OFFSET 0xe4\r
-#define DDRSS_CTL_58_OFFSET 0xe8\r
-#define DDRSS_CTL_59_OFFSET 0xec\r
-#define DDRSS_CTL_60_OFFSET 0xf0\r
-#define DDRSS_CTL_61_OFFSET 0xf4\r
-#define DDRSS_CTL_62_OFFSET 0xf8\r
-#define DDRSS_CTL_63_OFFSET 0xfc\r
-#define DDRSS_CTL_64_OFFSET 0x100\r
-#define DDRSS_CTL_65_OFFSET 0x104\r
-#define DDRSS_CTL_66_OFFSET 0x108\r
-#define DDRSS_CTL_67_OFFSET 0x10c\r
-#define DDRSS_CTL_68_OFFSET 0x110\r
-#define DDRSS_CTL_69_OFFSET 0x114\r
-#define DDRSS_CTL_70_OFFSET 0x118\r
-#define DDRSS_CTL_71_OFFSET 0x11c\r
-#define DDRSS_CTL_72_OFFSET 0x120\r
-#define DDRSS_CTL_73_OFFSET 0x124\r
-#define DDRSS_CTL_74_OFFSET 0x128\r
-#define DDRSS_CTL_75_OFFSET 0x12c\r
-#define DDRSS_CTL_76_OFFSET 0x130\r
-#define DDRSS_CTL_77_OFFSET 0x134\r
-#define DDRSS_CTL_78_OFFSET 0x138\r
-#define DDRSS_CTL_79_OFFSET 0x13c\r
-#define DDRSS_CTL_80_OFFSET 0x140\r
-#define DDRSS_CTL_81_OFFSET 0x144\r
-#define DDRSS_CTL_82_OFFSET 0x148\r
-#define DDRSS_CTL_83_OFFSET 0x14c\r
-#define DDRSS_CTL_84_OFFSET 0x150\r
-#define DDRSS_CTL_85_OFFSET 0x154\r
-#define DDRSS_CTL_86_OFFSET 0x158\r
-#define DDRSS_CTL_87_OFFSET 0x15c\r
-#define DDRSS_CTL_88_OFFSET 0x160\r
-#define DDRSS_CTL_89_OFFSET 0x164\r
-#define DDRSS_CTL_90_OFFSET 0x168\r
-#define DDRSS_CTL_91_OFFSET 0x16c\r
-#define DDRSS_CTL_92_OFFSET 0x170\r
-#define DDRSS_CTL_93_OFFSET 0x174\r
-#define DDRSS_CTL_94_OFFSET 0x178\r
-#define DDRSS_CTL_95_OFFSET 0x17c\r
-#define DDRSS_CTL_96_OFFSET 0x180\r
-#define DDRSS_CTL_97_OFFSET 0x184\r
-#define DDRSS_CTL_98_OFFSET 0x188\r
-#define DDRSS_CTL_99_OFFSET 0x18c\r
-#define DDRSS_CTL_100_OFFSET 0x190\r
-#define DDRSS_CTL_101_OFFSET 0x194\r
-#define DDRSS_CTL_102_OFFSET 0x198\r
-#define DDRSS_CTL_103_OFFSET 0x19c\r
-#define DDRSS_CTL_104_OFFSET 0x1a0\r
-#define DDRSS_CTL_105_OFFSET 0x1a4\r
-#define DDRSS_CTL_106_OFFSET 0x1a8\r
-#define DDRSS_CTL_107_OFFSET 0x1ac\r
-#define DDRSS_CTL_108_OFFSET 0x1b0\r
-#define DDRSS_CTL_109_OFFSET 0x1b4\r
-#define DDRSS_CTL_110_OFFSET 0x1b8\r
-#define DDRSS_CTL_111_OFFSET 0x1bc\r
-#define DDRSS_CTL_112_OFFSET 0x1c0\r
-#define DDRSS_CTL_113_OFFSET 0x1c4\r
-#define DDRSS_CTL_114_OFFSET 0x1c8\r
-#define DDRSS_CTL_115_OFFSET 0x1cc\r
-#define DDRSS_CTL_116_OFFSET 0x1d0\r
-#define DDRSS_CTL_117_OFFSET 0x1d4\r
-#define DDRSS_CTL_118_OFFSET 0x1d8\r
-#define DDRSS_CTL_119_OFFSET 0x1dc\r
-#define DDRSS_CTL_120_OFFSET 0x1e0\r
-#define DDRSS_CTL_121_OFFSET 0x1e4\r
-#define DDRSS_CTL_122_OFFSET 0x1e8\r
-#define DDRSS_CTL_123_OFFSET 0x1ec\r
-#define DDRSS_CTL_124_OFFSET 0x1f0\r
-#define DDRSS_CTL_125_OFFSET 0x1f4\r
-#define DDRSS_CTL_126_OFFSET 0x1f8\r
-#define DDRSS_CTL_127_OFFSET 0x1fc\r
-#define DDRSS_CTL_128_OFFSET 0x200\r
-#define DDRSS_CTL_129_OFFSET 0x204\r
-#define DDRSS_CTL_130_OFFSET 0x208\r
-#define DDRSS_CTL_131_OFFSET 0x20c\r
-#define DDRSS_CTL_132_OFFSET 0x210\r
-#define DDRSS_CTL_133_OFFSET 0x214\r
-#define DDRSS_CTL_134_OFFSET 0x218\r
-#define DDRSS_CTL_135_OFFSET 0x21c\r
-#define DDRSS_CTL_136_OFFSET 0x220\r
-#define DDRSS_CTL_137_OFFSET 0x224\r
-#define DDRSS_CTL_138_OFFSET 0x228\r
-#define DDRSS_CTL_139_OFFSET 0x22c\r
-#define DDRSS_CTL_140_OFFSET 0x230\r
-#define DDRSS_CTL_141_OFFSET 0x234\r
-#define DDRSS_CTL_142_OFFSET 0x238\r
-#define DDRSS_CTL_143_OFFSET 0x23c\r
-#define DDRSS_CTL_144_OFFSET 0x240\r
-#define DDRSS_CTL_145_OFFSET 0x244\r
-#define DDRSS_CTL_146_OFFSET 0x248\r
-#define DDRSS_CTL_147_OFFSET 0x24c\r
-#define DDRSS_CTL_148_OFFSET 0x250\r
-#define DDRSS_CTL_149_OFFSET 0x254\r
-#define DDRSS_CTL_150_OFFSET 0x258\r
-#define DDRSS_CTL_151_OFFSET 0x25c\r
-#define DDRSS_CTL_152_OFFSET 0x260\r
-#define DDRSS_CTL_153_OFFSET 0x264\r
-#define DDRSS_CTL_154_OFFSET 0x268\r
-#define DDRSS_CTL_155_OFFSET 0x26c\r
-#define DDRSS_CTL_156_OFFSET 0x270\r
-#define DDRSS_CTL_157_OFFSET 0x274\r
-#define DDRSS_CTL_158_OFFSET 0x278\r
-#define DDRSS_CTL_159_OFFSET 0x27c\r
-#define DDRSS_CTL_160_OFFSET 0x280\r
-#define DDRSS_CTL_161_OFFSET 0x284\r
-#define DDRSS_CTL_162_OFFSET 0x288\r
-#define DDRSS_CTL_163_OFFSET 0x28c\r
-#define DDRSS_CTL_164_OFFSET 0x290\r
-#define DDRSS_CTL_165_OFFSET 0x294\r
-#define DDRSS_CTL_166_OFFSET 0x298\r
-#define DDRSS_CTL_167_OFFSET 0x29c\r
-#define DDRSS_CTL_168_OFFSET 0x2a0\r
-#define DDRSS_CTL_169_OFFSET 0x2a4\r
-#define DDRSS_CTL_170_OFFSET 0x2a8\r
-#define DDRSS_CTL_171_OFFSET 0x2ac\r
-#define DDRSS_CTL_172_OFFSET 0x2b0\r
-#define DDRSS_CTL_173_OFFSET 0x2b4\r
-#define DDRSS_CTL_174_OFFSET 0x2b8\r
-#define DDRSS_CTL_175_OFFSET 0x2bc\r
-#define DDRSS_CTL_176_OFFSET 0x2c0\r
-#define DDRSS_CTL_177_OFFSET 0x2c4\r
-#define DDRSS_CTL_178_OFFSET 0x2c8\r
-#define DDRSS_CTL_179_OFFSET 0x2cc\r
-#define DDRSS_CTL_180_OFFSET 0x2d0\r
-#define DDRSS_CTL_181_OFFSET 0x2d4\r
-#define DDRSS_CTL_182_OFFSET 0x2d8\r
-#define DDRSS_CTL_183_OFFSET 0x2dc\r
-#define DDRSS_CTL_184_OFFSET 0x2e0\r
-#define DDRSS_CTL_185_OFFSET 0x2e4\r
-#define DDRSS_CTL_186_OFFSET 0x2e8\r
-#define DDRSS_CTL_187_OFFSET 0x2ec\r
-#define DDRSS_CTL_188_OFFSET 0x2f0\r
-#define DDRSS_CTL_189_OFFSET 0x2f4\r
-#define DDRSS_CTL_190_OFFSET 0x2f8\r
-#define DDRSS_CTL_191_OFFSET 0x2fc\r
-#define DDRSS_CTL_192_OFFSET 0x300\r
-#define DDRSS_CTL_193_OFFSET 0x304\r
-#define DDRSS_CTL_194_OFFSET 0x308\r
-#define DDRSS_CTL_195_OFFSET 0x30c\r
-#define DDRSS_CTL_196_OFFSET 0x310\r
-#define DDRSS_CTL_197_OFFSET 0x314\r
-#define DDRSS_CTL_198_OFFSET 0x318\r
-#define DDRSS_CTL_199_OFFSET 0x31c\r
-#define DDRSS_CTL_200_OFFSET 0x320\r
-#define DDRSS_CTL_201_OFFSET 0x324\r
-#define DDRSS_CTL_202_OFFSET 0x328\r
-#define DDRSS_CTL_203_OFFSET 0x32c\r
-#define DDRSS_CTL_204_OFFSET 0x330\r
-#define DDRSS_CTL_205_OFFSET 0x334\r
-#define DDRSS_CTL_206_OFFSET 0x338\r
-#define DDRSS_CTL_207_OFFSET 0x33c\r
-#define DDRSS_CTL_208_OFFSET 0x340\r
-#define DDRSS_CTL_209_OFFSET 0x344\r
-#define DDRSS_CTL_210_OFFSET 0x348\r
-#define DDRSS_CTL_211_OFFSET 0x34c\r
-#define DDRSS_CTL_212_OFFSET 0x350\r
-#define DDRSS_CTL_213_OFFSET 0x354\r
-#define DDRSS_CTL_214_OFFSET 0x358\r
-#define DDRSS_CTL_215_OFFSET 0x35c\r
-#define DDRSS_CTL_216_OFFSET 0x360\r
-#define DDRSS_CTL_217_OFFSET 0x364\r
-#define DDRSS_CTL_218_OFFSET 0x368\r
-#define DDRSS_CTL_219_OFFSET 0x36c\r
-#define DDRSS_CTL_220_OFFSET 0x370\r
-#define DDRSS_CTL_221_OFFSET 0x374\r
-#define DDRSS_CTL_222_OFFSET 0x378\r
-#define DDRSS_CTL_223_OFFSET 0x37c\r
-#define DDRSS_CTL_224_OFFSET 0x380\r
-#define DDRSS_CTL_225_OFFSET 0x384\r
-#define DDRSS_CTL_226_OFFSET 0x388\r
-#define DDRSS_CTL_227_OFFSET 0x38c\r
-#define DDRSS_CTL_228_OFFSET 0x390\r
-#define DDRSS_CTL_229_OFFSET 0x394\r
-#define DDRSS_CTL_230_OFFSET 0x398\r
-#define DDRSS_CTL_231_OFFSET 0x39c\r
-#define DDRSS_CTL_232_OFFSET 0x3a0\r
-#define DDRSS_CTL_233_OFFSET 0x3a4\r
-#define DDRSS_CTL_234_OFFSET 0x3a8\r
-#define DDRSS_CTL_235_OFFSET 0x3ac\r
-#define DDRSS_CTL_236_OFFSET 0x3b0\r
-#define DDRSS_CTL_237_OFFSET 0x3b4\r
-#define DDRSS_CTL_238_OFFSET 0x3b8\r
-#define DDRSS_CTL_239_OFFSET 0x3bc\r
-#define DDRSS_CTL_240_OFFSET 0x3c0\r
-#define DDRSS_CTL_241_OFFSET 0x3c4\r
-#define DDRSS_CTL_242_OFFSET 0x3c8\r
-#define DDRSS_CTL_243_OFFSET 0x3cc\r
-#define DDRSS_CTL_244_OFFSET 0x3d0\r
-#define DDRSS_CTL_245_OFFSET 0x3d4\r
-#define DDRSS_CTL_246_OFFSET 0x3d8\r
-#define DDRSS_CTL_247_OFFSET 0x3dc\r
-#define DDRSS_CTL_248_OFFSET 0x3e0\r
-#define DDRSS_CTL_249_OFFSET 0x3e4\r
-#define DDRSS_CTL_250_OFFSET 0x3e8\r
-#define DDRSS_CTL_251_OFFSET 0x3ec\r
-#define DDRSS_CTL_252_OFFSET 0x3f0\r
-#define DDRSS_CTL_253_OFFSET 0x3f4\r
-#define DDRSS_CTL_254_OFFSET 0x3f8\r
-#define DDRSS_CTL_255_OFFSET 0x3fc\r
-#define DDRSS_CTL_256_OFFSET 0x400\r
-#define DDRSS_CTL_257_OFFSET 0x404\r
-#define DDRSS_CTL_258_OFFSET 0x408\r
-#define DDRSS_CTL_259_OFFSET 0x40c\r
-#define DDRSS_CTL_260_OFFSET 0x410\r
-#define DDRSS_CTL_261_OFFSET 0x414\r
-#define DDRSS_CTL_262_OFFSET 0x418\r
-#define DDRSS_CTL_263_OFFSET 0x41c\r
-#define DDRSS_CTL_264_OFFSET 0x420\r
-#define DDRSS_CTL_265_OFFSET 0x424\r
-#define DDRSS_CTL_266_OFFSET 0x428\r
-#define DDRSS_CTL_267_OFFSET 0x42c\r
-#define DDRSS_CTL_268_OFFSET 0x430\r
-#define DDRSS_CTL_269_OFFSET 0x434\r
-#define DDRSS_CTL_270_OFFSET 0x438\r
-#define DDRSS_CTL_271_OFFSET 0x43c\r
-#define DDRSS_CTL_272_OFFSET 0x440\r
-#define DDRSS_CTL_273_OFFSET 0x444\r
-#define DDRSS_CTL_274_OFFSET 0x448\r
-#define DDRSS_CTL_275_OFFSET 0x44c\r
-#define DDRSS_CTL_276_OFFSET 0x450\r
-#define DDRSS_CTL_277_OFFSET 0x454\r
-#define DDRSS_CTL_278_OFFSET 0x458\r
-#define DDRSS_CTL_279_OFFSET 0x45c\r
-#define DDRSS_CTL_280_OFFSET 0x460\r
-#define DDRSS_CTL_281_OFFSET 0x464\r
-#define DDRSS_CTL_282_OFFSET 0x468\r
-#define DDRSS_CTL_283_OFFSET 0x46c\r
-#define DDRSS_CTL_284_OFFSET 0x470\r
-#define DDRSS_CTL_285_OFFSET 0x474\r
-#define DDRSS_CTL_286_OFFSET 0x478\r
-#define DDRSS_CTL_287_OFFSET 0x47c\r
-#define DDRSS_CTL_288_OFFSET 0x480\r
-#define DDRSS_CTL_289_OFFSET 0x484\r
-#define DDRSS_CTL_290_OFFSET 0x488\r
-#define DDRSS_CTL_291_OFFSET 0x48c\r
-#define DDRSS_CTL_292_OFFSET 0x490\r
-#define DDRSS_CTL_293_OFFSET 0x494\r
-#define DDRSS_CTL_294_OFFSET 0x498\r
-#define DDRSS_CTL_295_OFFSET 0x49c\r
-#define DDRSS_CTL_296_OFFSET 0x4a0\r
-#define DDRSS_CTL_297_OFFSET 0x4a4\r
-#define DDRSS_CTL_298_OFFSET 0x4a8\r
-#define DDRSS_CTL_299_OFFSET 0x4ac\r
-#define DDRSS_CTL_300_OFFSET 0x4b0\r
-#define DDRSS_CTL_301_OFFSET 0x4b4\r
-#define DDRSS_CTL_302_OFFSET 0x4b8\r
-#define DDRSS_CTL_303_OFFSET 0x4bc\r
-#define DDRSS_CTL_304_OFFSET 0x4c0\r
-#define DDRSS_CTL_305_OFFSET 0x4c4\r
-#define DDRSS_CTL_306_OFFSET 0x4c8\r
-#define DDRSS_CTL_307_OFFSET 0x4cc\r
-#define DDRSS_CTL_308_OFFSET 0x4d0\r
-#define DDRSS_CTL_309_OFFSET 0x4d4\r
-#define DDRSS_CTL_310_OFFSET 0x4d8\r
-#define DDRSS_CTL_311_OFFSET 0x4dc\r
-#define DDRSS_CTL_312_OFFSET 0x4e0\r
-#define DDRSS_CTL_313_OFFSET 0x4e4\r
-#define DDRSS_CTL_314_OFFSET 0x4e8\r
-#define DDRSS_CTL_315_OFFSET 0x4ec\r
-#define DDRSS_CTL_316_OFFSET 0x4f0\r
-#define DDRSS_CTL_317_OFFSET 0x4f4\r
-#define DDRSS_CTL_318_OFFSET 0x4f8\r
-#define DDRSS_CTL_319_OFFSET 0x4fc\r
-#define DDRSS_CTL_320_OFFSET 0x500\r
-#define DDRSS_CTL_321_OFFSET 0x504\r
-#define DDRSS_CTL_322_OFFSET 0x508\r
-#define DDRSS_CTL_323_OFFSET 0x50c\r
-#define DDRSS_CTL_324_OFFSET 0x510\r
-#define DDRSS_CTL_325_OFFSET 0x514\r
-#define DDRSS_CTL_326_OFFSET 0x518\r
-#define DDRSS_CTL_327_OFFSET 0x51c\r
-#define DDRSS_CTL_328_OFFSET 0x520\r
-#define DDRSS_CTL_329_OFFSET 0x524\r
-#define DDRSS_CTL_330_OFFSET 0x528\r
-#define DDRSS_CTL_331_OFFSET 0x52c\r
-#define DDRSS_CTL_332_OFFSET 0x530\r
-#define DDRSS_CTL_333_OFFSET 0x534\r
-#define DDRSS_CTL_334_OFFSET 0x538\r
-#define DDRSS_CTL_335_OFFSET 0x53c\r
-#define DDRSS_CTL_336_OFFSET 0x540\r
-#define DDRSS_CTL_337_OFFSET 0x544\r
-#define DDRSS_CTL_338_OFFSET 0x548\r
-#define DDRSS_CTL_339_OFFSET 0x54c\r
-#define DDRSS_CTL_340_OFFSET 0x550\r
-#define DDRSS_CTL_341_OFFSET 0x554\r
-#define DDRSS_CTL_342_OFFSET 0x558\r
-#define DDRSS_CTL_343_OFFSET 0x55c\r
-#define DDRSS_CTL_344_OFFSET 0x560\r
-#define DDRSS_CTL_345_OFFSET 0x564\r
-#define DDRSS_CTL_346_OFFSET 0x568\r
-#define DDRSS_CTL_347_OFFSET 0x56c\r
-#define DDRSS_CTL_348_OFFSET 0x570\r
-#define DDRSS_CTL_349_OFFSET 0x574\r
-#define DDRSS_CTL_350_OFFSET 0x578\r
-#define DDRSS_CTL_351_OFFSET 0x57c\r
-#define DDRSS_CTL_352_OFFSET 0x580\r
-#define DDRSS_CTL_353_OFFSET 0x584\r
-#define DDRSS_CTL_354_OFFSET 0x588\r
-#define DDRSS_CTL_355_OFFSET 0x58c\r
-#define DDRSS_CTL_356_OFFSET 0x590\r
-#define DDRSS_CTL_357_OFFSET 0x594\r
-#define DDRSS_CTL_358_OFFSET 0x598\r
-#define DDRSS_CTL_359_OFFSET 0x59c\r
-#define DDRSS_CTL_360_OFFSET 0x5a0\r
-#define DDRSS_CTL_361_OFFSET 0x5a4\r
-#define DDRSS_CTL_362_OFFSET 0x5a8\r
-#define DDRSS_CTL_363_OFFSET 0x5ac\r
-#define DDRSS_CTL_364_OFFSET 0x5b0\r
-#define DDRSS_CTL_365_OFFSET 0x5b4\r
-#define DDRSS_CTL_366_OFFSET 0x5b8\r
-#define DDRSS_CTL_367_OFFSET 0x5bc\r
-#define DDRSS_CTL_368_OFFSET 0x5c0\r
-#define DDRSS_CTL_369_OFFSET 0x5c4\r
-#define DDRSS_CTL_370_OFFSET 0x5c8\r
-#define DDRSS_CTL_371_OFFSET 0x5cc\r
-#define DDRSS_CTL_372_OFFSET 0x5d0\r
-#define DDRSS_CTL_373_OFFSET 0x5d4\r
-#define DDRSS_CTL_374_OFFSET 0x5d8\r
-#define DDRSS_CTL_375_OFFSET 0x5dc\r
-#define DDRSS_CTL_376_OFFSET 0x5e0\r
-#define DDRSS_CTL_377_OFFSET 0x5e4\r
-#define DDRSS_CTL_378_OFFSET 0x5e8\r
-#define DDRSS_CTL_379_OFFSET 0x5ec\r
-#define DDRSS_CTL_380_OFFSET 0x5f0\r
-#define DDRSS_CTL_381_OFFSET 0x5f4\r
-#define DDRSS_CTL_382_OFFSET 0x5f8\r
-#define DDRSS_CTL_383_OFFSET 0x5fc\r
-#define DDRSS_CTL_384_OFFSET 0x600\r
-#define DDRSS_CTL_385_OFFSET 0x604\r
-#define DDRSS_CTL_386_OFFSET 0x608\r
-#define DDRSS_CTL_387_OFFSET 0x60c\r
-#define DDRSS_CTL_388_OFFSET 0x610\r
-#define DDRSS_CTL_389_OFFSET 0x614\r
-#define DDRSS_CTL_390_OFFSET 0x618\r
-#define DDRSS_CTL_391_OFFSET 0x61c\r
-#define DDRSS_CTL_392_OFFSET 0x620\r
-#define DDRSS_CTL_393_OFFSET 0x624\r
-#define DDRSS_CTL_394_OFFSET 0x628\r
-#define DDRSS_CTL_395_OFFSET 0x62c\r
-#define DDRSS_CTL_396_OFFSET 0x630\r
-#define DDRSS_CTL_397_OFFSET 0x634\r
-#define DDRSS_CTL_398_OFFSET 0x638\r
-#define DDRSS_CTL_399_OFFSET 0x63c\r
-#define DDRSS_CTL_400_OFFSET 0x640\r
-#define DDRSS_CTL_401_OFFSET 0x644\r
-#define DDRSS_CTL_402_OFFSET 0x648\r
-#define DDRSS_CTL_403_OFFSET 0x64c\r
-#define DDRSS_CTL_404_OFFSET 0x650\r
-#define DDRSS_CTL_405_OFFSET 0x654\r
-#define DDRSS_CTL_406_OFFSET 0x658\r
-#define DDRSS_CTL_407_OFFSET 0x65c\r
-#define DDRSS_CTL_408_OFFSET 0x660\r
-#define DDRSS_CTL_409_OFFSET 0x664\r
-#define DDRSS_CTL_410_OFFSET 0x668\r
-#define DDRSS_CTL_411_OFFSET 0x66c\r
-#define DDRSS_CTL_412_OFFSET 0x670\r
-#define DDRSS_CTL_413_OFFSET 0x674\r
-#define DDRSS_CTL_414_OFFSET 0x678\r
-#define DDRSS_CTL_415_OFFSET 0x67c\r
-#define DDRSS_CTL_416_OFFSET 0x680\r
-#define DDRSS_CTL_417_OFFSET 0x684\r
-#define DDRSS_CTL_418_OFFSET 0x688\r
-#define DDRSS_CTL_419_OFFSET 0x68c\r
-#define DDRSS_CTL_420_OFFSET 0x690\r
-#define DDRSS_CTL_421_OFFSET 0x694\r
-#define DDRSS_CTL_422_OFFSET 0x698\r
-#define DDRSS_CTL_423_OFFSET 0x69c\r
-#define DDRSS_CTL_424_OFFSET 0x6a0\r
-#define DDRSS_CTL_425_OFFSET 0x6a4\r
-#define DDRSS_CTL_426_OFFSET 0x6a8\r
-#define DDRSS_CTL_427_OFFSET 0x6ac\r
-#define DDRSS_CTL_428_OFFSET 0x6b0\r
-#define DDRSS_CTL_429_OFFSET 0x6b4\r
-#define DDRSS_CTL_430_OFFSET 0x6b8\r
-#define DDRSS_CTL_431_OFFSET 0x6bc\r
-#define DDRSS_CTL_432_OFFSET 0x6c0\r
-#define DDRSS_CTL_433_OFFSET 0x6c4\r
-#define DDRSS_CTL_434_OFFSET 0x6c8\r
-#define DDRSS_CTL_435_OFFSET 0x6cc\r
-#define DDRSS_CTL_436_OFFSET 0x6d0\r
-#define DDRSS_CTL_437_OFFSET 0x6d4\r
-#define DDRSS_CTL_438_OFFSET 0x6d8\r
-#define DDRSS_CTL_439_OFFSET 0x6dc\r
-#define DDRSS_CTL_440_OFFSET 0x6e0\r
-#define DDRSS_CTL_441_OFFSET 0x6e4\r
-#define DDRSS_CTL_442_OFFSET 0x6e8\r
-#define DDRSS_CTL_443_OFFSET 0x6ec\r
-#define DDRSS_CTL_444_OFFSET 0x6f0\r
-#define DDRSS_CTL_445_OFFSET 0x6f4\r
-#define DDRSS_CTL_446_OFFSET 0x6f8\r
-#define DDRSS_CTL_447_OFFSET 0x6fc\r
-#define DDRSS_CTL_448_OFFSET 0x700\r
-#define DDRSS_CTL_449_OFFSET 0x704\r
-#define DDRSS_CTL_450_OFFSET 0x708\r
-#define DDRSS_CTL_451_OFFSET 0x70c\r
-#define DDRSS_CTL_452_OFFSET 0x710\r
-#define DDRSS_CTL_453_OFFSET 0x714\r
-#define DDRSS_CTL_454_OFFSET 0x718\r
-#define DDRSS_CTL_455_OFFSET 0x71c\r
-#define DDRSS_CTL_456_OFFSET 0x720\r
-#define DDRSS_CTL_457_OFFSET 0x724\r
-#define DDRSS_CTL_458_OFFSET 0x728\r
-\r
-/* Macros for register block PI */\r
-#define DDRSS_PI_REGISTER_BLOCK__OFFS 0x2000\r
-\r
-#define DDRSS_PI_0_OFFSET 0x0\r
-#define DDRSS_PI_1_OFFSET 0x4\r
-#define DDRSS_PI_2_OFFSET 0x8\r
-#define DDRSS_PI_3_OFFSET 0xc\r
-#define DDRSS_PI_4_OFFSET 0x10\r
-#define DDRSS_PI_5_OFFSET 0x14\r
-#define DDRSS_PI_6_OFFSET 0x18\r
-#define DDRSS_PI_7_OFFSET 0x1c\r
-#define DDRSS_PI_8_OFFSET 0x20\r
-#define DDRSS_PI_9_OFFSET 0x24\r
-#define DDRSS_PI_10_OFFSET 0x28\r
-#define DDRSS_PI_11_OFFSET 0x2c\r
-#define DDRSS_PI_12_OFFSET 0x30\r
-#define DDRSS_PI_13_OFFSET 0x34\r
-#define DDRSS_PI_14_OFFSET 0x38\r
-#define DDRSS_PI_15_OFFSET 0x3c\r
-#define DDRSS_PI_16_OFFSET 0x40\r
-#define DDRSS_PI_17_OFFSET 0x44\r
-#define DDRSS_PI_18_OFFSET 0x48\r
-#define DDRSS_PI_19_OFFSET 0x4c\r
-#define DDRSS_PI_20_OFFSET 0x50\r
-#define DDRSS_PI_21_OFFSET 0x54\r
-#define DDRSS_PI_22_OFFSET 0x58\r
-#define DDRSS_PI_23_OFFSET 0x5c\r
-#define DDRSS_PI_24_OFFSET 0x60\r
-#define DDRSS_PI_25_OFFSET 0x64\r
-#define DDRSS_PI_26_OFFSET 0x68\r
-#define DDRSS_PI_27_OFFSET 0x6c\r
-#define DDRSS_PI_28_OFFSET 0x70\r
-#define DDRSS_PI_29_OFFSET 0x74\r
-#define DDRSS_PI_30_OFFSET 0x78\r
-#define DDRSS_PI_31_OFFSET 0x7c\r
-#define DDRSS_PI_32_OFFSET 0x80\r
-#define DDRSS_PI_33_OFFSET 0x84\r
-#define DDRSS_PI_34_OFFSET 0x88\r
-#define DDRSS_PI_35_OFFSET 0x8c\r
-#define DDRSS_PI_36_OFFSET 0x90\r
-#define DDRSS_PI_37_OFFSET 0x94\r
-#define DDRSS_PI_38_OFFSET 0x98\r
-#define DDRSS_PI_39_OFFSET 0x9c\r
-#define DDRSS_PI_40_OFFSET 0xa0\r
-#define DDRSS_PI_41_OFFSET 0xa4\r
-#define DDRSS_PI_42_OFFSET 0xa8\r
-#define DDRSS_PI_43_OFFSET 0xac\r
-#define DDRSS_PI_44_OFFSET 0xb0\r
-#define DDRSS_PI_45_OFFSET 0xb4\r
-#define DDRSS_PI_46_OFFSET 0xb8\r
-#define DDRSS_PI_47_OFFSET 0xbc\r
-#define DDRSS_PI_48_OFFSET 0xc0\r
-#define DDRSS_PI_49_OFFSET 0xc4\r
-#define DDRSS_PI_50_OFFSET 0xc8\r
-#define DDRSS_PI_51_OFFSET 0xcc\r
-#define DDRSS_PI_52_OFFSET 0xd0\r
-#define DDRSS_PI_53_OFFSET 0xd4\r
-#define DDRSS_PI_54_OFFSET 0xd8\r
-#define DDRSS_PI_55_OFFSET 0xdc\r
-#define DDRSS_PI_56_OFFSET 0xe0\r
-#define DDRSS_PI_57_OFFSET 0xe4\r
-#define DDRSS_PI_58_OFFSET 0xe8\r
-#define DDRSS_PI_59_OFFSET 0xec\r
-#define DDRSS_PI_60_OFFSET 0xf0\r
-#define DDRSS_PI_61_OFFSET 0xf4\r
-#define DDRSS_PI_62_OFFSET 0xf8\r
-#define DDRSS_PI_63_OFFSET 0xfc\r
-#define DDRSS_PI_64_OFFSET 0x100\r
-#define DDRSS_PI_65_OFFSET 0x104\r
-#define DDRSS_PI_66_OFFSET 0x108\r
-#define DDRSS_PI_67_OFFSET 0x10c\r
-#define DDRSS_PI_68_OFFSET 0x110\r
-#define DDRSS_PI_69_OFFSET 0x114\r
-#define DDRSS_PI_70_OFFSET 0x118\r
-#define DDRSS_PI_71_OFFSET 0x11c\r
-#define DDRSS_PI_72_OFFSET 0x120\r
-#define DDRSS_PI_73_OFFSET 0x124\r
-#define DDRSS_PI_74_OFFSET 0x128\r
-#define DDRSS_PI_75_OFFSET 0x12c\r
-#define DDRSS_PI_76_OFFSET 0x130\r
-#define DDRSS_PI_77_OFFSET 0x134\r
-#define DDRSS_PI_78_OFFSET 0x138\r
-#define DDRSS_PI_79_OFFSET 0x13c\r
-#define DDRSS_PI_80_OFFSET 0x140\r
-#define DDRSS_PI_81_OFFSET 0x144\r
-#define DDRSS_PI_82_OFFSET 0x148\r
-#define DDRSS_PI_83_OFFSET 0x14c\r
-#define DDRSS_PI_84_OFFSET 0x150\r
-#define DDRSS_PI_85_OFFSET 0x154\r
-#define DDRSS_PI_86_OFFSET 0x158\r
-#define DDRSS_PI_87_OFFSET 0x15c\r
-#define DDRSS_PI_88_OFFSET 0x160\r
-#define DDRSS_PI_89_OFFSET 0x164\r
-#define DDRSS_PI_90_OFFSET 0x168\r
-#define DDRSS_PI_91_OFFSET 0x16c\r
-#define DDRSS_PI_92_OFFSET 0x170\r
-#define DDRSS_PI_93_OFFSET 0x174\r
-#define DDRSS_PI_94_OFFSET 0x178\r
-#define DDRSS_PI_95_OFFSET 0x17c\r
-#define DDRSS_PI_96_OFFSET 0x180\r
-#define DDRSS_PI_97_OFFSET 0x184\r
-#define DDRSS_PI_98_OFFSET 0x188\r
-#define DDRSS_PI_99_OFFSET 0x18c\r
-#define DDRSS_PI_100_OFFSET 0x190\r
-#define DDRSS_PI_101_OFFSET 0x194\r
-#define DDRSS_PI_102_OFFSET 0x198\r
-#define DDRSS_PI_103_OFFSET 0x19c\r
-#define DDRSS_PI_104_OFFSET 0x1a0\r
-#define DDRSS_PI_105_OFFSET 0x1a4\r
-#define DDRSS_PI_106_OFFSET 0x1a8\r
-#define DDRSS_PI_107_OFFSET 0x1ac\r
-#define DDRSS_PI_108_OFFSET 0x1b0\r
-#define DDRSS_PI_109_OFFSET 0x1b4\r
-#define DDRSS_PI_110_OFFSET 0x1b8\r
-#define DDRSS_PI_111_OFFSET 0x1bc\r
-#define DDRSS_PI_112_OFFSET 0x1c0\r
-#define DDRSS_PI_113_OFFSET 0x1c4\r
-#define DDRSS_PI_114_OFFSET 0x1c8\r
-#define DDRSS_PI_115_OFFSET 0x1cc\r
-#define DDRSS_PI_116_OFFSET 0x1d0\r
-#define DDRSS_PI_117_OFFSET 0x1d4\r
-#define DDRSS_PI_118_OFFSET 0x1d8\r
-#define DDRSS_PI_119_OFFSET 0x1dc\r
-#define DDRSS_PI_120_OFFSET 0x1e0\r
-#define DDRSS_PI_121_OFFSET 0x1e4\r
-#define DDRSS_PI_122_OFFSET 0x1e8\r
-#define DDRSS_PI_123_OFFSET 0x1ec\r
-#define DDRSS_PI_124_OFFSET 0x1f0\r
-#define DDRSS_PI_125_OFFSET 0x1f4\r
-#define DDRSS_PI_126_OFFSET 0x1f8\r
-#define DDRSS_PI_127_OFFSET 0x1fc\r
-#define DDRSS_PI_128_OFFSET 0x200\r
-#define DDRSS_PI_129_OFFSET 0x204\r
-#define DDRSS_PI_130_OFFSET 0x208\r
-#define DDRSS_PI_131_OFFSET 0x20c\r
-#define DDRSS_PI_132_OFFSET 0x210\r
-#define DDRSS_PI_133_OFFSET 0x214\r
-#define DDRSS_PI_134_OFFSET 0x218\r
-#define DDRSS_PI_135_OFFSET 0x21c\r
-#define DDRSS_PI_136_OFFSET 0x220\r
-#define DDRSS_PI_137_OFFSET 0x224\r
-#define DDRSS_PI_138_OFFSET 0x228\r
-#define DDRSS_PI_139_OFFSET 0x22c\r
-#define DDRSS_PI_140_OFFSET 0x230\r
-#define DDRSS_PI_141_OFFSET 0x234\r
-#define DDRSS_PI_142_OFFSET 0x238\r
-#define DDRSS_PI_143_OFFSET 0x23c\r
-#define DDRSS_PI_144_OFFSET 0x240\r
-#define DDRSS_PI_145_OFFSET 0x244\r
-#define DDRSS_PI_146_OFFSET 0x248\r
-#define DDRSS_PI_147_OFFSET 0x24c\r
-#define DDRSS_PI_148_OFFSET 0x250\r
-#define DDRSS_PI_149_OFFSET 0x254\r
-#define DDRSS_PI_150_OFFSET 0x258\r
-#define DDRSS_PI_151_OFFSET 0x25c\r
-#define DDRSS_PI_152_OFFSET 0x260\r
-#define DDRSS_PI_153_OFFSET 0x264\r
-#define DDRSS_PI_154_OFFSET 0x268\r
-#define DDRSS_PI_155_OFFSET 0x26c\r
-#define DDRSS_PI_156_OFFSET 0x270\r
-#define DDRSS_PI_157_OFFSET 0x274\r
-#define DDRSS_PI_158_OFFSET 0x278\r
-#define DDRSS_PI_159_OFFSET 0x27c\r
-#define DDRSS_PI_160_OFFSET 0x280\r
-#define DDRSS_PI_161_OFFSET 0x284\r
-#define DDRSS_PI_162_OFFSET 0x288\r
-#define DDRSS_PI_163_OFFSET 0x28c\r
-#define DDRSS_PI_164_OFFSET 0x290\r
-#define DDRSS_PI_165_OFFSET 0x294\r
-#define DDRSS_PI_166_OFFSET 0x298\r
-#define DDRSS_PI_167_OFFSET 0x29c\r
-#define DDRSS_PI_168_OFFSET 0x2a0\r
-#define DDRSS_PI_169_OFFSET 0x2a4\r
-#define DDRSS_PI_170_OFFSET 0x2a8\r
-#define DDRSS_PI_171_OFFSET 0x2ac\r
-#define DDRSS_PI_172_OFFSET 0x2b0\r
-#define DDRSS_PI_173_OFFSET 0x2b4\r
-#define DDRSS_PI_174_OFFSET 0x2b8\r
-#define DDRSS_PI_175_OFFSET 0x2bc\r
-#define DDRSS_PI_176_OFFSET 0x2c0\r
-#define DDRSS_PI_177_OFFSET 0x2c4\r
-#define DDRSS_PI_178_OFFSET 0x2c8\r
-#define DDRSS_PI_179_OFFSET 0x2cc\r
-#define DDRSS_PI_180_OFFSET 0x2d0\r
-#define DDRSS_PI_181_OFFSET 0x2d4\r
-#define DDRSS_PI_182_OFFSET 0x2d8\r
-#define DDRSS_PI_183_OFFSET 0x2dc\r
-#define DDRSS_PI_184_OFFSET 0x2e0\r
-#define DDRSS_PI_185_OFFSET 0x2e4\r
-#define DDRSS_PI_186_OFFSET 0x2e8\r
-#define DDRSS_PI_187_OFFSET 0x2ec\r
-#define DDRSS_PI_188_OFFSET 0x2f0\r
-#define DDRSS_PI_189_OFFSET 0x2f4\r
-#define DDRSS_PI_190_OFFSET 0x2f8\r
-#define DDRSS_PI_191_OFFSET 0x2fc\r
-#define DDRSS_PI_192_OFFSET 0x300\r
-#define DDRSS_PI_193_OFFSET 0x304\r
-#define DDRSS_PI_194_OFFSET 0x308\r
-#define DDRSS_PI_195_OFFSET 0x30c\r
-#define DDRSS_PI_196_OFFSET 0x310\r
-#define DDRSS_PI_197_OFFSET 0x314\r
-#define DDRSS_PI_198_OFFSET 0x318\r
-#define DDRSS_PI_199_OFFSET 0x31c\r
-#define DDRSS_PI_200_OFFSET 0x320\r
-#define DDRSS_PI_201_OFFSET 0x324\r
-#define DDRSS_PI_202_OFFSET 0x328\r
-#define DDRSS_PI_203_OFFSET 0x32c\r
-#define DDRSS_PI_204_OFFSET 0x330\r
-#define DDRSS_PI_205_OFFSET 0x334\r
-#define DDRSS_PI_206_OFFSET 0x338\r
-#define DDRSS_PI_207_OFFSET 0x33c\r
-#define DDRSS_PI_208_OFFSET 0x340\r
-#define DDRSS_PI_209_OFFSET 0x344\r
-#define DDRSS_PI_210_OFFSET 0x348\r
-#define DDRSS_PI_211_OFFSET 0x34c\r
-#define DDRSS_PI_212_OFFSET 0x350\r
-#define DDRSS_PI_213_OFFSET 0x354\r
-#define DDRSS_PI_214_OFFSET 0x358\r
-#define DDRSS_PI_215_OFFSET 0x35c\r
-#define DDRSS_PI_216_OFFSET 0x360\r
-#define DDRSS_PI_217_OFFSET 0x364\r
-#define DDRSS_PI_218_OFFSET 0x368\r
-#define DDRSS_PI_219_OFFSET 0x36c\r
-#define DDRSS_PI_220_OFFSET 0x370\r
-#define DDRSS_PI_221_OFFSET 0x374\r
-#define DDRSS_PI_222_OFFSET 0x378\r
-#define DDRSS_PI_223_OFFSET 0x37c\r
-#define DDRSS_PI_224_OFFSET 0x380\r
-#define DDRSS_PI_225_OFFSET 0x384\r
-#define DDRSS_PI_226_OFFSET 0x388\r
-#define DDRSS_PI_227_OFFSET 0x38c\r
-#define DDRSS_PI_228_OFFSET 0x390\r
-#define DDRSS_PI_229_OFFSET 0x394\r
-#define DDRSS_PI_230_OFFSET 0x398\r
-#define DDRSS_PI_231_OFFSET 0x39c\r
-#define DDRSS_PI_232_OFFSET 0x3a0\r
-#define DDRSS_PI_233_OFFSET 0x3a4\r
-#define DDRSS_PI_234_OFFSET 0x3a8\r
-#define DDRSS_PI_235_OFFSET 0x3ac\r
-#define DDRSS_PI_236_OFFSET 0x3b0\r
-#define DDRSS_PI_237_OFFSET 0x3b4\r
-#define DDRSS_PI_238_OFFSET 0x3b8\r
-#define DDRSS_PI_239_OFFSET 0x3bc\r
-#define DDRSS_PI_240_OFFSET 0x3c0\r
-#define DDRSS_PI_241_OFFSET 0x3c4\r
-#define DDRSS_PI_242_OFFSET 0x3c8\r
-#define DDRSS_PI_243_OFFSET 0x3cc\r
-#define DDRSS_PI_244_OFFSET 0x3d0\r
-#define DDRSS_PI_245_OFFSET 0x3d4\r
-#define DDRSS_PI_246_OFFSET 0x3d8\r
-#define DDRSS_PI_247_OFFSET 0x3dc\r
-#define DDRSS_PI_248_OFFSET 0x3e0\r
-#define DDRSS_PI_249_OFFSET 0x3e4\r
-#define DDRSS_PI_250_OFFSET 0x3e8\r
-#define DDRSS_PI_251_OFFSET 0x3ec\r
-#define DDRSS_PI_252_OFFSET 0x3f0\r
-#define DDRSS_PI_253_OFFSET 0x3f4\r
-#define DDRSS_PI_254_OFFSET 0x3f8\r
-#define DDRSS_PI_255_OFFSET 0x3fc\r
-#define DDRSS_PI_256_OFFSET 0x400\r
-#define DDRSS_PI_257_OFFSET 0x404\r
-#define DDRSS_PI_258_OFFSET 0x408\r
-#define DDRSS_PI_259_OFFSET 0x40c\r
-#define DDRSS_PI_260_OFFSET 0x410\r
-#define DDRSS_PI_261_OFFSET 0x414\r
-#define DDRSS_PI_262_OFFSET 0x418\r
-#define DDRSS_PI_263_OFFSET 0x41c\r
-#define DDRSS_PI_264_OFFSET 0x420\r
-#define DDRSS_PI_265_OFFSET 0x424\r
-#define DDRSS_PI_266_OFFSET 0x428\r
-#define DDRSS_PI_267_OFFSET 0x42c\r
-#define DDRSS_PI_268_OFFSET 0x430\r
-#define DDRSS_PI_269_OFFSET 0x434\r
-#define DDRSS_PI_270_OFFSET 0x438\r
-#define DDRSS_PI_271_OFFSET 0x43c\r
-#define DDRSS_PI_272_OFFSET 0x440\r
-#define DDRSS_PI_273_OFFSET 0x444\r
-#define DDRSS_PI_274_OFFSET 0x448\r
-#define DDRSS_PI_275_OFFSET 0x44c\r
-#define DDRSS_PI_276_OFFSET 0x450\r
-#define DDRSS_PI_277_OFFSET 0x454\r
-#define DDRSS_PI_278_OFFSET 0x458\r
-#define DDRSS_PI_279_OFFSET 0x45c\r
-#define DDRSS_PI_280_OFFSET 0x460\r
-#define DDRSS_PI_281_OFFSET 0x464\r
-#define DDRSS_PI_282_OFFSET 0x468\r
-#define DDRSS_PI_283_OFFSET 0x46c\r
-#define DDRSS_PI_284_OFFSET 0x470\r
-#define DDRSS_PI_285_OFFSET 0x474\r
-#define DDRSS_PI_286_OFFSET 0x478\r
-#define DDRSS_PI_287_OFFSET 0x47c\r
-#define DDRSS_PI_288_OFFSET 0x480\r
-#define DDRSS_PI_289_OFFSET 0x484\r
-#define DDRSS_PI_290_OFFSET 0x488\r
-#define DDRSS_PI_291_OFFSET 0x48c\r
-#define DDRSS_PI_292_OFFSET 0x490\r
-#define DDRSS_PI_293_OFFSET 0x494\r
-#define DDRSS_PI_294_OFFSET 0x498\r
-#define DDRSS_PI_295_OFFSET 0x49c\r
-#define DDRSS_PI_296_OFFSET 0x4a0\r
-#define DDRSS_PI_297_OFFSET 0x4a4\r
-#define DDRSS_PI_298_OFFSET 0x4a8\r
-#define DDRSS_PI_299_OFFSET 0x4ac\r
-\r
-/* Macros for register block Data_Slice_0 */\r
-#define DDRSS_Data_Slice_0_REGISTER_BLOCK__OFFS 0x4000\r
-\r
-#define DDRSS_PHY_0_OFFSET 0x0\r
-#define DDRSS_PHY_1_OFFSET 0x4\r
-#define DDRSS_PHY_2_OFFSET 0x8\r
-#define DDRSS_PHY_3_OFFSET 0xc\r
-#define DDRSS_PHY_4_OFFSET 0x10\r
-#define DDRSS_PHY_5_OFFSET 0x14\r
-#define DDRSS_PHY_6_OFFSET 0x18\r
-#define DDRSS_PHY_7_OFFSET 0x1c\r
-#define DDRSS_PHY_8_OFFSET 0x20\r
-#define DDRSS_PHY_9_OFFSET 0x24\r
-#define DDRSS_PHY_10_OFFSET 0x28\r
-#define DDRSS_PHY_11_OFFSET 0x2c\r
-#define DDRSS_PHY_12_OFFSET 0x30\r
-#define DDRSS_PHY_13_OFFSET 0x34\r
-#define DDRSS_PHY_14_OFFSET 0x38\r
-#define DDRSS_PHY_15_OFFSET 0x3c\r
-#define DDRSS_PHY_16_OFFSET 0x40\r
-#define DDRSS_PHY_17_OFFSET 0x44\r
-#define DDRSS_PHY_18_OFFSET 0x48\r
-#define DDRSS_PHY_19_OFFSET 0x4c\r
-#define DDRSS_PHY_20_OFFSET 0x50\r
-#define DDRSS_PHY_21_OFFSET 0x54\r
-#define DDRSS_PHY_22_OFFSET 0x58\r
-#define DDRSS_PHY_23_OFFSET 0x5c\r
-#define DDRSS_PHY_24_OFFSET 0x60\r
-#define DDRSS_PHY_25_OFFSET 0x64\r
-#define DDRSS_PHY_26_OFFSET 0x68\r
-#define DDRSS_PHY_27_OFFSET 0x6c\r
-#define DDRSS_PHY_28_OFFSET 0x70\r
-#define DDRSS_PHY_29_OFFSET 0x74\r
-#define DDRSS_PHY_30_OFFSET 0x78\r
-#define DDRSS_PHY_31_OFFSET 0x7c\r
-#define DDRSS_PHY_32_OFFSET 0x80\r
-#define DDRSS_PHY_33_OFFSET 0x84\r
-#define DDRSS_PHY_34_OFFSET 0x88\r
-#define DDRSS_PHY_35_OFFSET 0x8c\r
-#define DDRSS_PHY_36_OFFSET 0x90\r
-#define DDRSS_PHY_37_OFFSET 0x94\r
-#define DDRSS_PHY_38_OFFSET 0x98\r
-#define DDRSS_PHY_39_OFFSET 0x9c\r
-#define DDRSS_PHY_40_OFFSET 0xa0\r
-#define DDRSS_PHY_41_OFFSET 0xa4\r
-#define DDRSS_PHY_42_OFFSET 0xa8\r
-#define DDRSS_PHY_43_OFFSET 0xac\r
-#define DDRSS_PHY_44_OFFSET 0xb0\r
-#define DDRSS_PHY_45_OFFSET 0xb4\r
-#define DDRSS_PHY_46_OFFSET 0xb8\r
-#define DDRSS_PHY_47_OFFSET 0xbc\r
-#define DDRSS_PHY_48_OFFSET 0xc0\r
-#define DDRSS_PHY_49_OFFSET 0xc4\r
-#define DDRSS_PHY_50_OFFSET 0xc8\r
-#define DDRSS_PHY_51_OFFSET 0xcc\r
-#define DDRSS_PHY_52_OFFSET 0xd0\r
-#define DDRSS_PHY_53_OFFSET 0xd4\r
-#define DDRSS_PHY_54_OFFSET 0xd8\r
-#define DDRSS_PHY_55_OFFSET 0xdc\r
-#define DDRSS_PHY_56_OFFSET 0xe0\r
-#define DDRSS_PHY_57_OFFSET 0xe4\r
-#define DDRSS_PHY_58_OFFSET 0xe8\r
-#define DDRSS_PHY_59_OFFSET 0xec\r
-#define DDRSS_PHY_60_OFFSET 0xf0\r
-#define DDRSS_PHY_61_OFFSET 0xf4\r
-#define DDRSS_PHY_62_OFFSET 0xf8\r
-#define DDRSS_PHY_63_OFFSET 0xfc\r
-#define DDRSS_PHY_64_OFFSET 0x100\r
-#define DDRSS_PHY_65_OFFSET 0x104\r
-#define DDRSS_PHY_66_OFFSET 0x108\r
-#define DDRSS_PHY_67_OFFSET 0x10c\r
-#define DDRSS_PHY_68_OFFSET 0x110\r
-#define DDRSS_PHY_69_OFFSET 0x114\r
-#define DDRSS_PHY_70_OFFSET 0x118\r
-#define DDRSS_PHY_71_OFFSET 0x11c\r
-#define DDRSS_PHY_72_OFFSET 0x120\r
-#define DDRSS_PHY_73_OFFSET 0x124\r
-#define DDRSS_PHY_74_OFFSET 0x128\r
-#define DDRSS_PHY_75_OFFSET 0x12c\r
-#define DDRSS_PHY_76_OFFSET 0x130\r
-#define DDRSS_PHY_77_OFFSET 0x134\r
-#define DDRSS_PHY_78_OFFSET 0x138\r
-#define DDRSS_PHY_79_OFFSET 0x13c\r
-#define DDRSS_PHY_80_OFFSET 0x140\r
-#define DDRSS_PHY_81_OFFSET 0x144\r
-#define DDRSS_PHY_82_OFFSET 0x148\r
-#define DDRSS_PHY_83_OFFSET 0x14c\r
-#define DDRSS_PHY_84_OFFSET 0x150\r
-#define DDRSS_PHY_85_OFFSET 0x154\r
-#define DDRSS_PHY_86_OFFSET 0x158\r
-#define DDRSS_PHY_87_OFFSET 0x15c\r
-#define DDRSS_PHY_88_OFFSET 0x160\r
-#define DDRSS_PHY_89_OFFSET 0x164\r
-#define DDRSS_PHY_90_OFFSET 0x168\r
-#define DDRSS_PHY_91_OFFSET 0x16c\r
-#define DDRSS_PHY_92_OFFSET 0x170\r
-#define DDRSS_PHY_93_OFFSET 0x174\r
-#define DDRSS_PHY_94_OFFSET 0x178\r
-#define DDRSS_PHY_95_OFFSET 0x17c\r
-#define DDRSS_PHY_96_OFFSET 0x180\r
-#define DDRSS_PHY_97_OFFSET 0x184\r
-#define DDRSS_PHY_98_OFFSET 0x188\r
-#define DDRSS_PHY_99_OFFSET 0x18c\r
-#define DDRSS_PHY_100_OFFSET 0x190\r
-#define DDRSS_PHY_101_OFFSET 0x194\r
-#define DDRSS_PHY_102_OFFSET 0x198\r
-#define DDRSS_PHY_103_OFFSET 0x19c\r
-#define DDRSS_PHY_104_OFFSET 0x1a0\r
-#define DDRSS_PHY_105_OFFSET 0x1a4\r
-#define DDRSS_PHY_106_OFFSET 0x1a8\r
-#define DDRSS_PHY_107_OFFSET 0x1ac\r
-#define DDRSS_PHY_108_OFFSET 0x1b0\r
-#define DDRSS_PHY_109_OFFSET 0x1b4\r
-#define DDRSS_PHY_110_OFFSET 0x1b8\r
-#define DDRSS_PHY_111_OFFSET 0x1bc\r
-#define DDRSS_PHY_112_OFFSET 0x1c0\r
-#define DDRSS_PHY_113_OFFSET 0x1c4\r
-#define DDRSS_PHY_114_OFFSET 0x1c8\r
-#define DDRSS_PHY_115_OFFSET 0x1cc\r
-#define DDRSS_PHY_116_OFFSET 0x1d0\r
-#define DDRSS_PHY_117_OFFSET 0x1d4\r
-#define DDRSS_PHY_118_OFFSET 0x1d8\r
-#define DDRSS_PHY_119_OFFSET 0x1dc\r
-#define DDRSS_PHY_120_OFFSET 0x1e0\r
-#define DDRSS_PHY_121_OFFSET 0x1e4\r
-#define DDRSS_PHY_122_OFFSET 0x1e8\r
-#define DDRSS_PHY_123_OFFSET 0x1ec\r
-#define DDRSS_PHY_124_OFFSET 0x1f0\r
-#define DDRSS_PHY_125_OFFSET 0x1f4\r
-#define DDRSS_PHY_126_OFFSET 0x1f8\r
-#define DDRSS_PHY_127_OFFSET 0x1fc\r
-#define DDRSS_PHY_128_OFFSET 0x200\r
-#define DDRSS_PHY_129_OFFSET 0x204\r
-#define DDRSS_PHY_130_OFFSET 0x208\r
-#define DDRSS_PHY_131_OFFSET 0x20c\r
-#define DDRSS_PHY_132_OFFSET 0x210\r
-#define DDRSS_PHY_133_OFFSET 0x214\r
-#define DDRSS_PHY_134_OFFSET 0x218\r
-#define DDRSS_PHY_135_OFFSET 0x21c\r
-#define DDRSS_PHY_136_OFFSET 0x220\r
-#define DDRSS_PHY_137_OFFSET 0x224\r
-#define DDRSS_PHY_138_OFFSET 0x228\r
-#define DDRSS_PHY_139_OFFSET 0x22c\r
-\r
-/* Macros for register block Data_Slice_1 */\r
-#define DDRSS_Data_Slice_1_REGISTER_BLOCK__OFFS 0x4400\r
-\r
-#define DDRSS_PHY_256_OFFSET 0x0\r
-#define DDRSS_PHY_257_OFFSET 0x4\r
-#define DDRSS_PHY_258_OFFSET 0x8\r
-#define DDRSS_PHY_259_OFFSET 0xc\r
-#define DDRSS_PHY_260_OFFSET 0x10\r
-#define DDRSS_PHY_261_OFFSET 0x14\r
-#define DDRSS_PHY_262_OFFSET 0x18\r
-#define DDRSS_PHY_263_OFFSET 0x1c\r
-#define DDRSS_PHY_264_OFFSET 0x20\r
-#define DDRSS_PHY_265_OFFSET 0x24\r
-#define DDRSS_PHY_266_OFFSET 0x28\r
-#define DDRSS_PHY_267_OFFSET 0x2c\r
-#define DDRSS_PHY_268_OFFSET 0x30\r
-#define DDRSS_PHY_269_OFFSET 0x34\r
-#define DDRSS_PHY_270_OFFSET 0x38\r
-#define DDRSS_PHY_271_OFFSET 0x3c\r
-#define DDRSS_PHY_272_OFFSET 0x40\r
-#define DDRSS_PHY_273_OFFSET 0x44\r
-#define DDRSS_PHY_274_OFFSET 0x48\r
-#define DDRSS_PHY_275_OFFSET 0x4c\r
-#define DDRSS_PHY_276_OFFSET 0x50\r
-#define DDRSS_PHY_277_OFFSET 0x54\r
-#define DDRSS_PHY_278_OFFSET 0x58\r
-#define DDRSS_PHY_279_OFFSET 0x5c\r
-#define DDRSS_PHY_280_OFFSET 0x60\r
-#define DDRSS_PHY_281_OFFSET 0x64\r
-#define DDRSS_PHY_282_OFFSET 0x68\r
-#define DDRSS_PHY_283_OFFSET 0x6c\r
-#define DDRSS_PHY_284_OFFSET 0x70\r
-#define DDRSS_PHY_285_OFFSET 0x74\r
-#define DDRSS_PHY_286_OFFSET 0x78\r
-#define DDRSS_PHY_287_OFFSET 0x7c\r
-#define DDRSS_PHY_288_OFFSET 0x80\r
-#define DDRSS_PHY_289_OFFSET 0x84\r
-#define DDRSS_PHY_290_OFFSET 0x88\r
-#define DDRSS_PHY_291_OFFSET 0x8c\r
-#define DDRSS_PHY_292_OFFSET 0x90\r
-#define DDRSS_PHY_293_OFFSET 0x94\r
-#define DDRSS_PHY_294_OFFSET 0x98\r
-#define DDRSS_PHY_295_OFFSET 0x9c\r
-#define DDRSS_PHY_296_OFFSET 0xa0\r
-#define DDRSS_PHY_297_OFFSET 0xa4\r
-#define DDRSS_PHY_298_OFFSET 0xa8\r
-#define DDRSS_PHY_299_OFFSET 0xac\r
-#define DDRSS_PHY_300_OFFSET 0xb0\r
-#define DDRSS_PHY_301_OFFSET 0xb4\r
-#define DDRSS_PHY_302_OFFSET 0xb8\r
-#define DDRSS_PHY_303_OFFSET 0xbc\r
-#define DDRSS_PHY_304_OFFSET 0xc0\r
-#define DDRSS_PHY_305_OFFSET 0xc4\r
-#define DDRSS_PHY_306_OFFSET 0xc8\r
-#define DDRSS_PHY_307_OFFSET 0xcc\r
-#define DDRSS_PHY_308_OFFSET 0xd0\r
-#define DDRSS_PHY_309_OFFSET 0xd4\r
-#define DDRSS_PHY_310_OFFSET 0xd8\r
-#define DDRSS_PHY_311_OFFSET 0xdc\r
-#define DDRSS_PHY_312_OFFSET 0xe0\r
-#define DDRSS_PHY_313_OFFSET 0xe4\r
-#define DDRSS_PHY_314_OFFSET 0xe8\r
-#define DDRSS_PHY_315_OFFSET 0xec\r
-#define DDRSS_PHY_316_OFFSET 0xf0\r
-#define DDRSS_PHY_317_OFFSET 0xf4\r
-#define DDRSS_PHY_318_OFFSET 0xf8\r
-#define DDRSS_PHY_319_OFFSET 0xfc\r
-#define DDRSS_PHY_320_OFFSET 0x100\r
-#define DDRSS_PHY_321_OFFSET 0x104\r
-#define DDRSS_PHY_322_OFFSET 0x108\r
-#define DDRSS_PHY_323_OFFSET 0x10c\r
-#define DDRSS_PHY_324_OFFSET 0x110\r
-#define DDRSS_PHY_325_OFFSET 0x114\r
-#define DDRSS_PHY_326_OFFSET 0x118\r
-#define DDRSS_PHY_327_OFFSET 0x11c\r
-#define DDRSS_PHY_328_OFFSET 0x120\r
-#define DDRSS_PHY_329_OFFSET 0x124\r
-#define DDRSS_PHY_330_OFFSET 0x128\r
-#define DDRSS_PHY_331_OFFSET 0x12c\r
-#define DDRSS_PHY_332_OFFSET 0x130\r
-#define DDRSS_PHY_333_OFFSET 0x134\r
-#define DDRSS_PHY_334_OFFSET 0x138\r
-#define DDRSS_PHY_335_OFFSET 0x13c\r
-#define DDRSS_PHY_336_OFFSET 0x140\r
-#define DDRSS_PHY_337_OFFSET 0x144\r
-#define DDRSS_PHY_338_OFFSET 0x148\r
-#define DDRSS_PHY_339_OFFSET 0x14c\r
-#define DDRSS_PHY_340_OFFSET 0x150\r
-#define DDRSS_PHY_341_OFFSET 0x154\r
-#define DDRSS_PHY_342_OFFSET 0x158\r
-#define DDRSS_PHY_343_OFFSET 0x15c\r
-#define DDRSS_PHY_344_OFFSET 0x160\r
-#define DDRSS_PHY_345_OFFSET 0x164\r
-#define DDRSS_PHY_346_OFFSET 0x168\r
-#define DDRSS_PHY_347_OFFSET 0x16c\r
-#define DDRSS_PHY_348_OFFSET 0x170\r
-#define DDRSS_PHY_349_OFFSET 0x174\r
-#define DDRSS_PHY_350_OFFSET 0x178\r
-#define DDRSS_PHY_351_OFFSET 0x17c\r
-#define DDRSS_PHY_352_OFFSET 0x180\r
-#define DDRSS_PHY_353_OFFSET 0x184\r
-#define DDRSS_PHY_354_OFFSET 0x188\r
-#define DDRSS_PHY_355_OFFSET 0x18c\r
-#define DDRSS_PHY_356_OFFSET 0x190\r
-#define DDRSS_PHY_357_OFFSET 0x194\r
-#define DDRSS_PHY_358_OFFSET 0x198\r
-#define DDRSS_PHY_359_OFFSET 0x19c\r
-#define DDRSS_PHY_360_OFFSET 0x1a0\r
-#define DDRSS_PHY_361_OFFSET 0x1a4\r
-#define DDRSS_PHY_362_OFFSET 0x1a8\r
-#define DDRSS_PHY_363_OFFSET 0x1ac\r
-#define DDRSS_PHY_364_OFFSET 0x1b0\r
-#define DDRSS_PHY_365_OFFSET 0x1b4\r
-#define DDRSS_PHY_366_OFFSET 0x1b8\r
-#define DDRSS_PHY_367_OFFSET 0x1bc\r
-#define DDRSS_PHY_368_OFFSET 0x1c0\r
-#define DDRSS_PHY_369_OFFSET 0x1c4\r
-#define DDRSS_PHY_370_OFFSET 0x1c8\r
-#define DDRSS_PHY_371_OFFSET 0x1cc\r
-#define DDRSS_PHY_372_OFFSET 0x1d0\r
-#define DDRSS_PHY_373_OFFSET 0x1d4\r
-#define DDRSS_PHY_374_OFFSET 0x1d8\r
-#define DDRSS_PHY_375_OFFSET 0x1dc\r
-#define DDRSS_PHY_376_OFFSET 0x1e0\r
-#define DDRSS_PHY_377_OFFSET 0x1e4\r
-#define DDRSS_PHY_378_OFFSET 0x1e8\r
-#define DDRSS_PHY_379_OFFSET 0x1ec\r
-#define DDRSS_PHY_380_OFFSET 0x1f0\r
-#define DDRSS_PHY_381_OFFSET 0x1f4\r
-#define DDRSS_PHY_382_OFFSET 0x1f8\r
-#define DDRSS_PHY_383_OFFSET 0x1fc\r
-#define DDRSS_PHY_384_OFFSET 0x200\r
-#define DDRSS_PHY_385_OFFSET 0x204\r
-#define DDRSS_PHY_386_OFFSET 0x208\r
-#define DDRSS_PHY_387_OFFSET 0x20c\r
-#define DDRSS_PHY_388_OFFSET 0x210\r
-#define DDRSS_PHY_389_OFFSET 0x214\r
-#define DDRSS_PHY_390_OFFSET 0x218\r
-#define DDRSS_PHY_391_OFFSET 0x21c\r
-#define DDRSS_PHY_392_OFFSET 0x220\r
-#define DDRSS_PHY_393_OFFSET 0x224\r
-#define DDRSS_PHY_394_OFFSET 0x228\r
-#define DDRSS_PHY_395_OFFSET 0x22c\r
-\r
-/* Macros for register block Data_Slice_2 */\r
-#define DDRSS_Data_Slice_2_REGISTER_BLOCK__OFFS 0x4800\r
-\r
-#define DDRSS_PHY_512_OFFSET 0x0\r
-#define DDRSS_PHY_513_OFFSET 0x4\r
-#define DDRSS_PHY_514_OFFSET 0x8\r
-#define DDRSS_PHY_515_OFFSET 0xc\r
-#define DDRSS_PHY_516_OFFSET 0x10\r
-#define DDRSS_PHY_517_OFFSET 0x14\r
-#define DDRSS_PHY_518_OFFSET 0x18\r
-#define DDRSS_PHY_519_OFFSET 0x1c\r
-#define DDRSS_PHY_520_OFFSET 0x20\r
-#define DDRSS_PHY_521_OFFSET 0x24\r
-#define DDRSS_PHY_522_OFFSET 0x28\r
-#define DDRSS_PHY_523_OFFSET 0x2c\r
-#define DDRSS_PHY_524_OFFSET 0x30\r
-#define DDRSS_PHY_525_OFFSET 0x34\r
-#define DDRSS_PHY_526_OFFSET 0x38\r
-#define DDRSS_PHY_527_OFFSET 0x3c\r
-#define DDRSS_PHY_528_OFFSET 0x40\r
-#define DDRSS_PHY_529_OFFSET 0x44\r
-#define DDRSS_PHY_530_OFFSET 0x48\r
-#define DDRSS_PHY_531_OFFSET 0x4c\r
-#define DDRSS_PHY_532_OFFSET 0x50\r
-#define DDRSS_PHY_533_OFFSET 0x54\r
-#define DDRSS_PHY_534_OFFSET 0x58\r
-#define DDRSS_PHY_535_OFFSET 0x5c\r
-#define DDRSS_PHY_536_OFFSET 0x60\r
-#define DDRSS_PHY_537_OFFSET 0x64\r
-#define DDRSS_PHY_538_OFFSET 0x68\r
-#define DDRSS_PHY_539_OFFSET 0x6c\r
-#define DDRSS_PHY_540_OFFSET 0x70\r
-#define DDRSS_PHY_541_OFFSET 0x74\r
-#define DDRSS_PHY_542_OFFSET 0x78\r
-#define DDRSS_PHY_543_OFFSET 0x7c\r
-#define DDRSS_PHY_544_OFFSET 0x80\r
-#define DDRSS_PHY_545_OFFSET 0x84\r
-#define DDRSS_PHY_546_OFFSET 0x88\r
-#define DDRSS_PHY_547_OFFSET 0x8c\r
-#define DDRSS_PHY_548_OFFSET 0x90\r
-#define DDRSS_PHY_549_OFFSET 0x94\r
-#define DDRSS_PHY_550_OFFSET 0x98\r
-#define DDRSS_PHY_551_OFFSET 0x9c\r
-#define DDRSS_PHY_552_OFFSET 0xa0\r
-#define DDRSS_PHY_553_OFFSET 0xa4\r
-#define DDRSS_PHY_554_OFFSET 0xa8\r
-#define DDRSS_PHY_555_OFFSET 0xac\r
-#define DDRSS_PHY_556_OFFSET 0xb0\r
-#define DDRSS_PHY_557_OFFSET 0xb4\r
-#define DDRSS_PHY_558_OFFSET 0xb8\r
-#define DDRSS_PHY_559_OFFSET 0xbc\r
-#define DDRSS_PHY_560_OFFSET 0xc0\r
-#define DDRSS_PHY_561_OFFSET 0xc4\r
-#define DDRSS_PHY_562_OFFSET 0xc8\r
-#define DDRSS_PHY_563_OFFSET 0xcc\r
-#define DDRSS_PHY_564_OFFSET 0xd0\r
-#define DDRSS_PHY_565_OFFSET 0xd4\r
-#define DDRSS_PHY_566_OFFSET 0xd8\r
-#define DDRSS_PHY_567_OFFSET 0xdc\r
-#define DDRSS_PHY_568_OFFSET 0xe0\r
-#define DDRSS_PHY_569_OFFSET 0xe4\r
-#define DDRSS_PHY_570_OFFSET 0xe8\r
-#define DDRSS_PHY_571_OFFSET 0xec\r
-#define DDRSS_PHY_572_OFFSET 0xf0\r
-#define DDRSS_PHY_573_OFFSET 0xf4\r
-#define DDRSS_PHY_574_OFFSET 0xf8\r
-#define DDRSS_PHY_575_OFFSET 0xfc\r
-#define DDRSS_PHY_576_OFFSET 0x100\r
-#define DDRSS_PHY_577_OFFSET 0x104\r
-#define DDRSS_PHY_578_OFFSET 0x108\r
-#define DDRSS_PHY_579_OFFSET 0x10c\r
-#define DDRSS_PHY_580_OFFSET 0x110\r
-#define DDRSS_PHY_581_OFFSET 0x114\r
-#define DDRSS_PHY_582_OFFSET 0x118\r
-#define DDRSS_PHY_583_OFFSET 0x11c\r
-#define DDRSS_PHY_584_OFFSET 0x120\r
-#define DDRSS_PHY_585_OFFSET 0x124\r
-#define DDRSS_PHY_586_OFFSET 0x128\r
-#define DDRSS_PHY_587_OFFSET 0x12c\r
-#define DDRSS_PHY_588_OFFSET 0x130\r
-#define DDRSS_PHY_589_OFFSET 0x134\r
-#define DDRSS_PHY_590_OFFSET 0x138\r
-#define DDRSS_PHY_591_OFFSET 0x13c\r
-#define DDRSS_PHY_592_OFFSET 0x140\r
-#define DDRSS_PHY_593_OFFSET 0x144\r
-#define DDRSS_PHY_594_OFFSET 0x148\r
-#define DDRSS_PHY_595_OFFSET 0x14c\r
-#define DDRSS_PHY_596_OFFSET 0x150\r
-#define DDRSS_PHY_597_OFFSET 0x154\r
-#define DDRSS_PHY_598_OFFSET 0x158\r
-#define DDRSS_PHY_599_OFFSET 0x15c\r
-#define DDRSS_PHY_600_OFFSET 0x160\r
-#define DDRSS_PHY_601_OFFSET 0x164\r
-#define DDRSS_PHY_602_OFFSET 0x168\r
-#define DDRSS_PHY_603_OFFSET 0x16c\r
-#define DDRSS_PHY_604_OFFSET 0x170\r
-#define DDRSS_PHY_605_OFFSET 0x174\r
-#define DDRSS_PHY_606_OFFSET 0x178\r
-#define DDRSS_PHY_607_OFFSET 0x17c\r
-#define DDRSS_PHY_608_OFFSET 0x180\r
-#define DDRSS_PHY_609_OFFSET 0x184\r
-#define DDRSS_PHY_610_OFFSET 0x188\r
-#define DDRSS_PHY_611_OFFSET 0x18c\r
-#define DDRSS_PHY_612_OFFSET 0x190\r
-#define DDRSS_PHY_613_OFFSET 0x194\r
-#define DDRSS_PHY_614_OFFSET 0x198\r
-#define DDRSS_PHY_615_OFFSET 0x19c\r
-#define DDRSS_PHY_616_OFFSET 0x1a0\r
-#define DDRSS_PHY_617_OFFSET 0x1a4\r
-#define DDRSS_PHY_618_OFFSET 0x1a8\r
-#define DDRSS_PHY_619_OFFSET 0x1ac\r
-#define DDRSS_PHY_620_OFFSET 0x1b0\r
-#define DDRSS_PHY_621_OFFSET 0x1b4\r
-#define DDRSS_PHY_622_OFFSET 0x1b8\r
-#define DDRSS_PHY_623_OFFSET 0x1bc\r
-#define DDRSS_PHY_624_OFFSET 0x1c0\r
-#define DDRSS_PHY_625_OFFSET 0x1c4\r
-#define DDRSS_PHY_626_OFFSET 0x1c8\r
-#define DDRSS_PHY_627_OFFSET 0x1cc\r
-#define DDRSS_PHY_628_OFFSET 0x1d0\r
-#define DDRSS_PHY_629_OFFSET 0x1d4\r
-#define DDRSS_PHY_630_OFFSET 0x1d8\r
-#define DDRSS_PHY_631_OFFSET 0x1dc\r
-#define DDRSS_PHY_632_OFFSET 0x1e0\r
-#define DDRSS_PHY_633_OFFSET 0x1e4\r
-#define DDRSS_PHY_634_OFFSET 0x1e8\r
-#define DDRSS_PHY_635_OFFSET 0x1ec\r
-#define DDRSS_PHY_636_OFFSET 0x1f0\r
-#define DDRSS_PHY_637_OFFSET 0x1f4\r
-#define DDRSS_PHY_638_OFFSET 0x1f8\r
-#define DDRSS_PHY_639_OFFSET 0x1fc\r
-#define DDRSS_PHY_640_OFFSET 0x200\r
-#define DDRSS_PHY_641_OFFSET 0x204\r
-#define DDRSS_PHY_642_OFFSET 0x208\r
-#define DDRSS_PHY_643_OFFSET 0x20c\r
-#define DDRSS_PHY_644_OFFSET 0x210\r
-#define DDRSS_PHY_645_OFFSET 0x214\r
-#define DDRSS_PHY_646_OFFSET 0x218\r
-#define DDRSS_PHY_647_OFFSET 0x21c\r
-#define DDRSS_PHY_648_OFFSET 0x220\r
-#define DDRSS_PHY_649_OFFSET 0x224\r
-#define DDRSS_PHY_650_OFFSET 0x228\r
-#define DDRSS_PHY_651_OFFSET 0x22c\r
-\r
-/* Macros for register block Data_Slice_3 */\r
-#define DDRSS_Data_Slice_3_REGISTER_BLOCK__OFFS 0x4c00\r
-\r
-#define DDRSS_PHY_768_OFFSET 0x0\r
-#define DDRSS_PHY_769_OFFSET 0x4\r
-#define DDRSS_PHY_770_OFFSET 0x8\r
-#define DDRSS_PHY_771_OFFSET 0xc\r
-#define DDRSS_PHY_772_OFFSET 0x10\r
-#define DDRSS_PHY_773_OFFSET 0x14\r
-#define DDRSS_PHY_774_OFFSET 0x18\r
-#define DDRSS_PHY_775_OFFSET 0x1c\r
-#define DDRSS_PHY_776_OFFSET 0x20\r
-#define DDRSS_PHY_777_OFFSET 0x24\r
-#define DDRSS_PHY_778_OFFSET 0x28\r
-#define DDRSS_PHY_779_OFFSET 0x2c\r
-#define DDRSS_PHY_780_OFFSET 0x30\r
-#define DDRSS_PHY_781_OFFSET 0x34\r
-#define DDRSS_PHY_782_OFFSET 0x38\r
-#define DDRSS_PHY_783_OFFSET 0x3c\r
-#define DDRSS_PHY_784_OFFSET 0x40\r
-#define DDRSS_PHY_785_OFFSET 0x44\r
-#define DDRSS_PHY_786_OFFSET 0x48\r
-#define DDRSS_PHY_787_OFFSET 0x4c\r
-#define DDRSS_PHY_788_OFFSET 0x50\r
-#define DDRSS_PHY_789_OFFSET 0x54\r
-#define DDRSS_PHY_790_OFFSET 0x58\r
-#define DDRSS_PHY_791_OFFSET 0x5c\r
-#define DDRSS_PHY_792_OFFSET 0x60\r
-#define DDRSS_PHY_793_OFFSET 0x64\r
-#define DDRSS_PHY_794_OFFSET 0x68\r
-#define DDRSS_PHY_795_OFFSET 0x6c\r
-#define DDRSS_PHY_796_OFFSET 0x70\r
-#define DDRSS_PHY_797_OFFSET 0x74\r
-#define DDRSS_PHY_798_OFFSET 0x78\r
-#define DDRSS_PHY_799_OFFSET 0x7c\r
-#define DDRSS_PHY_800_OFFSET 0x80\r
-#define DDRSS_PHY_801_OFFSET 0x84\r
-#define DDRSS_PHY_802_OFFSET 0x88\r
-#define DDRSS_PHY_803_OFFSET 0x8c\r
-#define DDRSS_PHY_804_OFFSET 0x90\r
-#define DDRSS_PHY_805_OFFSET 0x94\r
-#define DDRSS_PHY_806_OFFSET 0x98\r
-#define DDRSS_PHY_807_OFFSET 0x9c\r
-#define DDRSS_PHY_808_OFFSET 0xa0\r
-#define DDRSS_PHY_809_OFFSET 0xa4\r
-#define DDRSS_PHY_810_OFFSET 0xa8\r
-#define DDRSS_PHY_811_OFFSET 0xac\r
-#define DDRSS_PHY_812_OFFSET 0xb0\r
-#define DDRSS_PHY_813_OFFSET 0xb4\r
-#define DDRSS_PHY_814_OFFSET 0xb8\r
-#define DDRSS_PHY_815_OFFSET 0xbc\r
-#define DDRSS_PHY_816_OFFSET 0xc0\r
-#define DDRSS_PHY_817_OFFSET 0xc4\r
-#define DDRSS_PHY_818_OFFSET 0xc8\r
-#define DDRSS_PHY_819_OFFSET 0xcc\r
-#define DDRSS_PHY_820_OFFSET 0xd0\r
-#define DDRSS_PHY_821_OFFSET 0xd4\r
-#define DDRSS_PHY_822_OFFSET 0xd8\r
-#define DDRSS_PHY_823_OFFSET 0xdc\r
-#define DDRSS_PHY_824_OFFSET 0xe0\r
-#define DDRSS_PHY_825_OFFSET 0xe4\r
-#define DDRSS_PHY_826_OFFSET 0xe8\r
-#define DDRSS_PHY_827_OFFSET 0xec\r
-#define DDRSS_PHY_828_OFFSET 0xf0\r
-#define DDRSS_PHY_829_OFFSET 0xf4\r
-#define DDRSS_PHY_830_OFFSET 0xf8\r
-#define DDRSS_PHY_831_OFFSET 0xfc\r
-#define DDRSS_PHY_832_OFFSET 0x100\r
-#define DDRSS_PHY_833_OFFSET 0x104\r
-#define DDRSS_PHY_834_OFFSET 0x108\r
-#define DDRSS_PHY_835_OFFSET 0x10c\r
-#define DDRSS_PHY_836_OFFSET 0x110\r
-#define DDRSS_PHY_837_OFFSET 0x114\r
-#define DDRSS_PHY_838_OFFSET 0x118\r
-#define DDRSS_PHY_839_OFFSET 0x11c\r
-#define DDRSS_PHY_840_OFFSET 0x120\r
-#define DDRSS_PHY_841_OFFSET 0x124\r
-#define DDRSS_PHY_842_OFFSET 0x128\r
-#define DDRSS_PHY_843_OFFSET 0x12c\r
-#define DDRSS_PHY_844_OFFSET 0x130\r
-#define DDRSS_PHY_845_OFFSET 0x134\r
-#define DDRSS_PHY_846_OFFSET 0x138\r
-#define DDRSS_PHY_847_OFFSET 0x13c\r
-#define DDRSS_PHY_848_OFFSET 0x140\r
-#define DDRSS_PHY_849_OFFSET 0x144\r
-#define DDRSS_PHY_850_OFFSET 0x148\r
-#define DDRSS_PHY_851_OFFSET 0x14c\r
-#define DDRSS_PHY_852_OFFSET 0x150\r
-#define DDRSS_PHY_853_OFFSET 0x154\r
-#define DDRSS_PHY_854_OFFSET 0x158\r
-#define DDRSS_PHY_855_OFFSET 0x15c\r
-#define DDRSS_PHY_856_OFFSET 0x160\r
-#define DDRSS_PHY_857_OFFSET 0x164\r
-#define DDRSS_PHY_858_OFFSET 0x168\r
-#define DDRSS_PHY_859_OFFSET 0x16c\r
-#define DDRSS_PHY_860_OFFSET 0x170\r
-#define DDRSS_PHY_861_OFFSET 0x174\r
-#define DDRSS_PHY_862_OFFSET 0x178\r
-#define DDRSS_PHY_863_OFFSET 0x17c\r
-#define DDRSS_PHY_864_OFFSET 0x180\r
-#define DDRSS_PHY_865_OFFSET 0x184\r
-#define DDRSS_PHY_866_OFFSET 0x188\r
-#define DDRSS_PHY_867_OFFSET 0x18c\r
-#define DDRSS_PHY_868_OFFSET 0x190\r
-#define DDRSS_PHY_869_OFFSET 0x194\r
-#define DDRSS_PHY_870_OFFSET 0x198\r
-#define DDRSS_PHY_871_OFFSET 0x19c\r
-#define DDRSS_PHY_872_OFFSET 0x1a0\r
-#define DDRSS_PHY_873_OFFSET 0x1a4\r
-#define DDRSS_PHY_874_OFFSET 0x1a8\r
-#define DDRSS_PHY_875_OFFSET 0x1ac\r
-#define DDRSS_PHY_876_OFFSET 0x1b0\r
-#define DDRSS_PHY_877_OFFSET 0x1b4\r
-#define DDRSS_PHY_878_OFFSET 0x1b8\r
-#define DDRSS_PHY_879_OFFSET 0x1bc\r
-#define DDRSS_PHY_880_OFFSET 0x1c0\r
-#define DDRSS_PHY_881_OFFSET 0x1c4\r
-#define DDRSS_PHY_882_OFFSET 0x1c8\r
-#define DDRSS_PHY_883_OFFSET 0x1cc\r
-#define DDRSS_PHY_884_OFFSET 0x1d0\r
-#define DDRSS_PHY_885_OFFSET 0x1d4\r
-#define DDRSS_PHY_886_OFFSET 0x1d8\r
-#define DDRSS_PHY_887_OFFSET 0x1dc\r
-#define DDRSS_PHY_888_OFFSET 0x1e0\r
-#define DDRSS_PHY_889_OFFSET 0x1e4\r
-#define DDRSS_PHY_890_OFFSET 0x1e8\r
-#define DDRSS_PHY_891_OFFSET 0x1ec\r
-#define DDRSS_PHY_892_OFFSET 0x1f0\r
-#define DDRSS_PHY_893_OFFSET 0x1f4\r
-#define DDRSS_PHY_894_OFFSET 0x1f8\r
-#define DDRSS_PHY_895_OFFSET 0x1fc\r
-#define DDRSS_PHY_896_OFFSET 0x200\r
-#define DDRSS_PHY_897_OFFSET 0x204\r
-#define DDRSS_PHY_898_OFFSET 0x208\r
-#define DDRSS_PHY_899_OFFSET 0x20c\r
-#define DDRSS_PHY_900_OFFSET 0x210\r
-#define DDRSS_PHY_901_OFFSET 0x214\r
-#define DDRSS_PHY_902_OFFSET 0x218\r
-#define DDRSS_PHY_903_OFFSET 0x21c\r
-#define DDRSS_PHY_904_OFFSET 0x220\r
-#define DDRSS_PHY_905_OFFSET 0x224\r
-#define DDRSS_PHY_906_OFFSET 0x228\r
-#define DDRSS_PHY_907_OFFSET 0x22c\r
-\r
-/* Macros for register block Address_Slice_0 */\r
-#define DDRSS_Address_Slice_0_REGISTER_BLOCK__OFFS 0x5000\r
-\r
-#define DDRSS_PHY_1024_OFFSET 0x0\r
-#define DDRSS_PHY_1025_OFFSET 0x4\r
-#define DDRSS_PHY_1026_OFFSET 0x8\r
-#define DDRSS_PHY_1027_OFFSET 0xc\r
-#define DDRSS_PHY_1028_OFFSET 0x10\r
-#define DDRSS_PHY_1029_OFFSET 0x14\r
-#define DDRSS_PHY_1030_OFFSET 0x18\r
-#define DDRSS_PHY_1031_OFFSET 0x1c\r
-#define DDRSS_PHY_1032_OFFSET 0x20\r
-#define DDRSS_PHY_1033_OFFSET 0x24\r
-#define DDRSS_PHY_1034_OFFSET 0x28\r
-#define DDRSS_PHY_1035_OFFSET 0x2c\r
-#define DDRSS_PHY_1036_OFFSET 0x30\r
-#define DDRSS_PHY_1037_OFFSET 0x34\r
-#define DDRSS_PHY_1038_OFFSET 0x38\r
-#define DDRSS_PHY_1039_OFFSET 0x3c\r
-#define DDRSS_PHY_1040_OFFSET 0x40\r
-#define DDRSS_PHY_1041_OFFSET 0x44\r
-#define DDRSS_PHY_1042_OFFSET 0x48\r
-#define DDRSS_PHY_1043_OFFSET 0x4c\r
-#define DDRSS_PHY_1044_OFFSET 0x50\r
-#define DDRSS_PHY_1045_OFFSET 0x54\r
-#define DDRSS_PHY_1046_OFFSET 0x58\r
-#define DDRSS_PHY_1047_OFFSET 0x5c\r
-#define DDRSS_PHY_1048_OFFSET 0x60\r
-#define DDRSS_PHY_1049_OFFSET 0x64\r
-#define DDRSS_PHY_1050_OFFSET 0x68\r
-#define DDRSS_PHY_1051_OFFSET 0x6c\r
-#define DDRSS_PHY_1052_OFFSET 0x70\r
-#define DDRSS_PHY_1053_OFFSET 0x74\r
-#define DDRSS_PHY_1054_OFFSET 0x78\r
-#define DDRSS_PHY_1055_OFFSET 0x7c\r
-#define DDRSS_PHY_1056_OFFSET 0x80\r
-#define DDRSS_PHY_1057_OFFSET 0x84\r
-#define DDRSS_PHY_1058_OFFSET 0x88\r
-#define DDRSS_PHY_1059_OFFSET 0x8c\r
-#define DDRSS_PHY_1060_OFFSET 0x90\r
-#define DDRSS_PHY_1061_OFFSET 0x94\r
-#define DDRSS_PHY_1062_OFFSET 0x98\r
-#define DDRSS_PHY_1063_OFFSET 0x9c\r
-#define DDRSS_PHY_1064_OFFSET 0xa0\r
-#define DDRSS_PHY_1065_OFFSET 0xa4\r
-#define DDRSS_PHY_1066_OFFSET 0xa8\r
-#define DDRSS_PHY_1067_OFFSET 0xac\r
-#define DDRSS_PHY_1068_OFFSET 0xb0\r
-#define DDRSS_PHY_1069_OFFSET 0xb4\r
-#define DDRSS_PHY_1070_OFFSET 0xb8\r
-#define DDRSS_PHY_1071_OFFSET 0xbc\r
-#define DDRSS_PHY_1072_OFFSET 0xc0\r
-#define DDRSS_PHY_1073_OFFSET 0xc4\r
-#define DDRSS_PHY_1074_OFFSET 0xc8\r
-#define DDRSS_PHY_1075_OFFSET 0xcc\r
-\r
-/* Macros for register block PHY_Core */\r
-#define DDRSS_PHY_Core_REGISTER_BLOCK__OFFS 0x5400\r
-\r
-#define DDRSS_PHY_1280_OFFSET 0x0\r
-#define DDRSS_PHY_1281_OFFSET 0x4\r
-#define DDRSS_PHY_1282_OFFSET 0x8\r
-#define DDRSS_PHY_1283_OFFSET 0xc\r
-#define DDRSS_PHY_1284_OFFSET 0x10\r
-#define DDRSS_PHY_1285_OFFSET 0x14\r
-#define DDRSS_PHY_1286_OFFSET 0x18\r
-#define DDRSS_PHY_1287_OFFSET 0x1c\r
-#define DDRSS_PHY_1288_OFFSET 0x20\r
-#define DDRSS_PHY_1289_OFFSET 0x24\r
-#define DDRSS_PHY_1290_OFFSET 0x28\r
-#define DDRSS_PHY_1291_OFFSET 0x2c\r
-#define DDRSS_PHY_1292_OFFSET 0x30\r
-#define DDRSS_PHY_1293_OFFSET 0x34\r
-#define DDRSS_PHY_1294_OFFSET 0x38\r
-#define DDRSS_PHY_1295_OFFSET 0x3c\r
-#define DDRSS_PHY_1296_OFFSET 0x40\r
-#define DDRSS_PHY_1297_OFFSET 0x44\r
-#define DDRSS_PHY_1298_OFFSET 0x48\r
-#define DDRSS_PHY_1299_OFFSET 0x4c\r
-#define DDRSS_PHY_1300_OFFSET 0x50\r
-#define DDRSS_PHY_1301_OFFSET 0x54\r
-#define DDRSS_PHY_1302_OFFSET 0x58\r
-#define DDRSS_PHY_1303_OFFSET 0x5c\r
-#define DDRSS_PHY_1304_OFFSET 0x60\r
-#define DDRSS_PHY_1305_OFFSET 0x64\r
-#define DDRSS_PHY_1306_OFFSET 0x68\r
-#define DDRSS_PHY_1307_OFFSET 0x6c\r
-#define DDRSS_PHY_1308_OFFSET 0x70\r
-#define DDRSS_PHY_1309_OFFSET 0x74\r
-#define DDRSS_PHY_1310_OFFSET 0x78\r
-#define DDRSS_PHY_1311_OFFSET 0x7c\r
-#define DDRSS_PHY_1312_OFFSET 0x80\r
-#define DDRSS_PHY_1313_OFFSET 0x84\r
-#define DDRSS_PHY_1314_OFFSET 0x88\r
-#define DDRSS_PHY_1315_OFFSET 0x8c\r
-#define DDRSS_PHY_1316_OFFSET 0x90\r
-#define DDRSS_PHY_1317_OFFSET 0x94\r
-#define DDRSS_PHY_1318_OFFSET 0x98\r
-#define DDRSS_PHY_1319_OFFSET 0x9c\r
-#define DDRSS_PHY_1320_OFFSET 0xa0\r
-#define DDRSS_PHY_1321_OFFSET 0xa4\r
-#define DDRSS_PHY_1322_OFFSET 0xa8\r
-#define DDRSS_PHY_1323_OFFSET 0xac\r
-#define DDRSS_PHY_1324_OFFSET 0xb0\r
-#define DDRSS_PHY_1325_OFFSET 0xb4\r
-#define DDRSS_PHY_1326_OFFSET 0xb8\r
-#define DDRSS_PHY_1327_OFFSET 0xbc\r
-#define DDRSS_PHY_1328_OFFSET 0xc0\r
-#define DDRSS_PHY_1329_OFFSET 0xc4\r
-#define DDRSS_PHY_1330_OFFSET 0xc8\r
-#define DDRSS_PHY_1331_OFFSET 0xcc\r
-#define DDRSS_PHY_1332_OFFSET 0xd0\r
-#define DDRSS_PHY_1333_OFFSET 0xd4\r
-#define DDRSS_PHY_1334_OFFSET 0xd8\r
-#define DDRSS_PHY_1335_OFFSET 0xdc\r
-#define DDRSS_PHY_1336_OFFSET 0xe0\r
-#define DDRSS_PHY_1337_OFFSET 0xe4\r
-#define DDRSS_PHY_1338_OFFSET 0xe8\r
-#define DDRSS_PHY_1339_OFFSET 0xec\r
-#define DDRSS_PHY_1340_OFFSET 0xf0\r
-#define DDRSS_PHY_1341_OFFSET 0xf4\r
-#define DDRSS_PHY_1342_OFFSET 0xf8\r
-#define DDRSS_PHY_1343_OFFSET 0xfc\r
-#define DDRSS_PHY_1344_OFFSET 0x100\r
-#define DDRSS_PHY_1345_OFFSET 0x104\r
-#define DDRSS_PHY_1346_OFFSET 0x108\r
-#define DDRSS_PHY_1347_OFFSET 0x10c\r
-#define DDRSS_PHY_1348_OFFSET 0x110\r
-#define DDRSS_PHY_1349_OFFSET 0x114\r
-#define DDRSS_PHY_1350_OFFSET 0x118\r
-#define DDRSS_PHY_1351_OFFSET 0x11c\r
-#define DDRSS_PHY_1352_OFFSET 0x120\r
-#define DDRSS_PHY_1353_OFFSET 0x124\r
-#define DDRSS_PHY_1354_OFFSET 0x128\r
-#define DDRSS_PHY_1355_OFFSET 0x12c\r
-#define DDRSS_PHY_1356_OFFSET 0x130\r
-#define DDRSS_PHY_1357_OFFSET 0x134\r
-#define DDRSS_PHY_1358_OFFSET 0x138\r
-#define DDRSS_PHY_1359_OFFSET 0x13c\r
-#define DDRSS_PHY_1360_OFFSET 0x140\r
-#define DDRSS_PHY_1361_OFFSET 0x144\r
-#define DDRSS_PHY_1362_OFFSET 0x148\r
-#define DDRSS_PHY_1363_OFFSET 0x14c\r
-#define DDRSS_PHY_1364_OFFSET 0x150\r
-#define DDRSS_PHY_1365_OFFSET 0x154\r
-#define DDRSS_PHY_1366_OFFSET 0x158\r
-#define DDRSS_PHY_1367_OFFSET 0x15c\r
-#define DDRSS_PHY_1368_OFFSET 0x160\r
-#define DDRSS_PHY_1369_OFFSET 0x164\r
-#define DDRSS_PHY_1370_OFFSET 0x168\r
-#define DDRSS_PHY_1371_OFFSET 0x16c\r
-#define DDRSS_PHY_1372_OFFSET 0x170\r
-#define DDRSS_PHY_1373_OFFSET 0x174\r
-#define DDRSS_PHY_1374_OFFSET 0x178\r
-#define DDRSS_PHY_1375_OFFSET 0x17c\r
-#define DDRSS_PHY_1376_OFFSET 0x180\r
-#define DDRSS_PHY_1377_OFFSET 0x184\r
-#define DDRSS_PHY_1378_OFFSET 0x188\r
-#define DDRSS_PHY_1379_OFFSET 0x18c\r
-#define DDRSS_PHY_1380_OFFSET 0x190\r
-#define DDRSS_PHY_1381_OFFSET 0x194\r
-#define DDRSS_PHY_1382_OFFSET 0x198\r
-#define DDRSS_PHY_1383_OFFSET 0x19c\r
-#define DDRSS_PHY_1384_OFFSET 0x1a0\r
-#define DDRSS_PHY_1385_OFFSET 0x1a4\r
-#define DDRSS_PHY_1386_OFFSET 0x1a8\r
-#define DDRSS_PHY_1387_OFFSET 0x1ac\r
-#define DDRSS_PHY_1388_OFFSET 0x1b0\r
-#define DDRSS_PHY_1389_OFFSET 0x1b4\r
-#define DDRSS_PHY_1390_OFFSET 0x1b8\r
-#define DDRSS_PHY_1391_OFFSET 0x1bc\r
-#define DDRSS_PHY_1392_OFFSET 0x1c0\r
-#define DDRSS_PHY_1393_OFFSET 0x1c4\r
-#define DDRSS_PHY_1394_OFFSET 0x1c8\r
-#define DDRSS_PHY_1395_OFFSET 0x1cc\r
-#define DDRSS_PHY_1396_OFFSET 0x1d0\r
-#define DDRSS_PHY_1397_OFFSET 0x1d4\r
-#define DDRSS_PHY_1398_OFFSET 0x1d8\r
-#define DDRSS_PHY_1399_OFFSET 0x1dc\r
-#define DDRSS_PHY_1400_OFFSET 0x1e0\r
-#define DDRSS_PHY_1401_OFFSET 0x1e4\r
-#define DDRSS_PHY_1402_OFFSET 0x1e8\r
-#define DDRSS_PHY_1403_OFFSET 0x1ec\r
-#define DDRSS_PHY_1404_OFFSET 0x1f0\r
-#define DDRSS_PHY_1405_OFFSET 0x1f4\r
-#define DDRSS_PHY_1406_OFFSET 0x1f8\r
-#define DDRSS_PHY_1407_OFFSET 0x1fc\r
-#define DDRSS_PHY_1408_OFFSET 0x200\r
-#define DDRSS_PHY_1409_OFFSET 0x204\r
-#define DDRSS_PHY_1410_OFFSET 0x208\r
-#define DDRSS_PHY_1411_OFFSET 0x20c\r
-#define DDRSS_PHY_1412_OFFSET 0x210\r
-#define DDRSS_PHY_1413_OFFSET 0x214\r
-#define DDRSS_PHY_1414_OFFSET 0x218\r
-#define DDRSS_PHY_1415_OFFSET 0x21c\r
-#define DDRSS_PHY_1416_OFFSET 0x220\r
-#define DDRSS_PHY_1417_OFFSET 0x224\r
-#define DDRSS_PHY_1418_OFFSET 0x228\r
-#define DDRSS_PHY_1419_OFFSET 0x22c\r
-#define DDRSS_PHY_1420_OFFSET 0x230\r
-#define DDRSS_PHY_1421_OFFSET 0x234\r
-#define DDRSS_PHY_1422_OFFSET 0x238\r
+#define BOARD_DDR_SS_BASE (0x02990000U)\r
\r
+#define BOARD_DDR_FSP_CLKCHNG_REQ_ADDR (0x00114080U)\r
+#define BOARD_DDR_FSP_CLKCHNG_ACK_ADDR (0x001140C0U)\r
\r
+#define BOARD_CTRL_MMR_PART5_LOCK0 (0x115008U)\r
+#define BOARD_CTRL_MMR_PART5_LOCK1 (0x11500CU)\r
\r
-#define DDRSS_CTL_00_DATA 0x00000B00\r
-#define DDRSS_CTL_01_DATA 0x00000000\r
-#define DDRSS_CTL_02_DATA 0x00000000\r
-#define DDRSS_CTL_03_DATA 0x00000000\r
-#define DDRSS_CTL_04_DATA 0x00000000\r
-#define DDRSS_CTL_05_DATA 0x00000000\r
-#define DDRSS_CTL_06_DATA 0x00000000\r
-#define DDRSS_CTL_07_DATA 0x00002710\r
-#define DDRSS_CTL_08_DATA 0x000186A0\r
-#define DDRSS_CTL_09_DATA 0x00000005\r
-#define DDRSS_CTL_10_DATA 0x00000064\r
-#define DDRSS_CTL_11_DATA 0x0005B18F\r
-#define DDRSS_CTL_12_DATA 0x0038EF90\r
-#define DDRSS_CTL_13_DATA 0x00000005\r
-#define DDRSS_CTL_14_DATA 0x00000E94\r
-#define DDRSS_CTL_15_DATA 0x0005B18F\r
-#define DDRSS_CTL_16_DATA 0x0038EF90\r
-#define DDRSS_CTL_17_DATA 0x00000005\r
-#define DDRSS_CTL_18_DATA 0x00000E94\r
-#define DDRSS_CTL_19_DATA 0x01010000\r
-#define DDRSS_CTL_20_DATA 0x02011001\r
-#define DDRSS_CTL_21_DATA 0x02010000\r
-#define DDRSS_CTL_22_DATA 0x00020100\r
-#define DDRSS_CTL_23_DATA 0x0000000A\r
-#define DDRSS_CTL_24_DATA 0x00000019\r
-#define DDRSS_CTL_25_DATA 0x00000000\r
-#define DDRSS_CTL_26_DATA 0x00000000\r
-#define DDRSS_CTL_27_DATA 0x02020200\r
-#define DDRSS_CTL_28_DATA 0x00004B4B\r
-#define DDRSS_CTL_29_DATA 0x00100000\r
-#define DDRSS_CTL_30_DATA 0x00000000\r
-#define DDRSS_CTL_31_DATA 0x00000000\r
-#define DDRSS_CTL_32_DATA 0x00000000\r
-#define DDRSS_CTL_33_DATA 0x00000000\r
-#define DDRSS_CTL_34_DATA 0x040C0000\r
-#define DDRSS_CTL_35_DATA 0x10401040\r
-#define DDRSS_CTL_36_DATA 0x00050804\r
-#define DDRSS_CTL_37_DATA 0x09040008\r
-#define DDRSS_CTL_38_DATA 0x12000204\r
-#define DDRSS_CTL_39_DATA 0x1854007A\r
-#define DDRSS_CTL_40_DATA 0x12003A26\r
-#define DDRSS_CTL_41_DATA 0x1854007A\r
-#define DDRSS_CTL_42_DATA 0x20003A26\r
-#define DDRSS_CTL_43_DATA 0x000A0A09\r
-#define DDRSS_CTL_44_DATA 0x040006DB\r
-#define DDRSS_CTL_45_DATA 0x1B130F04\r
-#define DDRSS_CTL_46_DATA 0x0E00FFCD\r
-#define DDRSS_CTL_47_DATA 0x1B130F0E\r
-#define DDRSS_CTL_48_DATA 0x0E00FFCD\r
-#define DDRSS_CTL_49_DATA 0x0203040E\r
-#define DDRSS_CTL_50_DATA 0x26040500\r
-#define DDRSS_CTL_51_DATA 0x08282628\r
-#define DDRSS_CTL_52_DATA 0x14000D0A\r
-#define DDRSS_CTL_53_DATA 0x03010A0A\r
-#define DDRSS_CTL_54_DATA 0x01010003\r
-#define DDRSS_CTL_55_DATA 0x044E4E08\r
-#define DDRSS_CTL_56_DATA 0x042B2B04\r
-#define DDRSS_CTL_57_DATA 0x00002B2B\r
-#define DDRSS_CTL_58_DATA 0x00010100\r
-#define DDRSS_CTL_59_DATA 0x03010000\r
-#define DDRSS_CTL_60_DATA 0x00000E08\r
-#define DDRSS_CTL_61_DATA 0x000000BB\r
-#define DDRSS_CTL_62_DATA 0x0000020B\r
-#define DDRSS_CTL_63_DATA 0x00001C64\r
-#define DDRSS_CTL_64_DATA 0x0000020B\r
-#define DDRSS_CTL_65_DATA 0x00001C64\r
-#define DDRSS_CTL_66_DATA 0x00000005\r
-#define DDRSS_CTL_67_DATA 0x00030000\r
-#define DDRSS_CTL_68_DATA 0x00830010\r
-#define DDRSS_CTL_69_DATA 0x00830386\r
-#define DDRSS_CTL_70_DATA 0x00400386\r
-#define DDRSS_CTL_71_DATA 0x00120103\r
-#define DDRSS_CTL_72_DATA 0x000E0005\r
-#define DDRSS_CTL_73_DATA 0x2908000E\r
-#define DDRSS_CTL_74_DATA 0x05050129\r
-#define DDRSS_CTL_75_DATA 0x0401030A\r
-#define DDRSS_CTL_76_DATA 0x041B0E0A\r
-#define DDRSS_CTL_77_DATA 0x0E0A0401\r
-#define DDRSS_CTL_78_DATA 0x0001041B\r
-#define DDRSS_CTL_79_DATA 0x000F000F\r
-#define DDRSS_CTL_80_DATA 0x02190219\r
-#define DDRSS_CTL_81_DATA 0x02190219\r
-#define DDRSS_CTL_82_DATA 0x03050505\r
-#define DDRSS_CTL_83_DATA 0x03010303\r
-#define DDRSS_CTL_84_DATA 0x1C0A0E0A\r
-#define DDRSS_CTL_85_DATA 0x04040E04\r
-#define DDRSS_CTL_86_DATA 0x1C0A0E0A\r
-#define DDRSS_CTL_87_DATA 0x04040E04\r
-#define DDRSS_CTL_88_DATA 0x03010000\r
-#define DDRSS_CTL_89_DATA 0x00010000\r
-#define DDRSS_CTL_90_DATA 0x00000000\r
-#define DDRSS_CTL_91_DATA 0x00000000\r
-#define DDRSS_CTL_92_DATA 0x01000000\r
-#define DDRSS_CTL_93_DATA 0x80104002\r
-#define DDRSS_CTL_94_DATA 0x00000000\r
-#define DDRSS_CTL_95_DATA 0x00040005\r
-#define DDRSS_CTL_96_DATA 0x00000000\r
-#define DDRSS_CTL_97_DATA 0x00050000\r
-#define DDRSS_CTL_98_DATA 0x00000004\r
-#define DDRSS_CTL_99_DATA 0x00000000\r
-#define DDRSS_CTL_100_DATA 0x00040005\r
-#define DDRSS_CTL_101_DATA 0x00000000\r
-#define DDRSS_CTL_102_DATA 0x00002EC0\r
-#define DDRSS_CTL_103_DATA 0x00002EC0\r
-#define DDRSS_CTL_104_DATA 0x00002EC0\r
-#define DDRSS_CTL_105_DATA 0x00002EC0\r
-#define DDRSS_CTL_106_DATA 0x00002EC0\r
-#define DDRSS_CTL_107_DATA 0x00000000\r
-#define DDRSS_CTL_108_DATA 0x0000051D\r
-#define DDRSS_CTL_109_DATA 0x00071900\r
-#define DDRSS_CTL_110_DATA 0x00071900\r
-#define DDRSS_CTL_111_DATA 0x00071900\r
-#define DDRSS_CTL_112_DATA 0x00071900\r
-#define DDRSS_CTL_113_DATA 0x00071900\r
-#define DDRSS_CTL_114_DATA 0x00000000\r
-#define DDRSS_CTL_115_DATA 0x0000C6BC\r
-#define DDRSS_CTL_116_DATA 0x00071900\r
-#define DDRSS_CTL_117_DATA 0x00071900\r
-#define DDRSS_CTL_118_DATA 0x00071900\r
-#define DDRSS_CTL_119_DATA 0x00071900\r
-#define DDRSS_CTL_120_DATA 0x00071900\r
-#define DDRSS_CTL_121_DATA 0x00000000\r
-#define DDRSS_CTL_122_DATA 0x0000C6BC\r
-#define DDRSS_CTL_123_DATA 0x00000000\r
-#define DDRSS_CTL_124_DATA 0x00000000\r
-#define DDRSS_CTL_125_DATA 0x00000000\r
-#define DDRSS_CTL_126_DATA 0x00000000\r
-#define DDRSS_CTL_127_DATA 0x00000000\r
-#define DDRSS_CTL_128_DATA 0x00000000\r
-#define DDRSS_CTL_129_DATA 0x00000000\r
-#define DDRSS_CTL_130_DATA 0x00000000\r
-#define DDRSS_CTL_131_DATA 0x0A030500\r
-#define DDRSS_CTL_132_DATA 0x00040A04\r
-#define DDRSS_CTL_133_DATA 0x0A090000\r
-#define DDRSS_CTL_134_DATA 0x0A090701\r
-#define DDRSS_CTL_135_DATA 0x0900000E\r
-#define DDRSS_CTL_136_DATA 0x0907010A\r
-#define DDRSS_CTL_137_DATA 0x00000E0A\r
-#define DDRSS_CTL_138_DATA 0x07010A09\r
-#define DDRSS_CTL_139_DATA 0x000E0A09\r
-#define DDRSS_CTL_140_DATA 0x07000401\r
-#define DDRSS_CTL_141_DATA 0x00000000\r
-#define DDRSS_CTL_142_DATA 0x00000000\r
-#define DDRSS_CTL_143_DATA 0x00000000\r
-#define DDRSS_CTL_144_DATA 0x00000000\r
-#define DDRSS_CTL_145_DATA 0x00000000\r
-#define DDRSS_CTL_146_DATA 0x00000000\r
-#define DDRSS_CTL_147_DATA 0x00000000\r
-#define DDRSS_CTL_148_DATA 0x08080000\r
-#define DDRSS_CTL_149_DATA 0x01000000\r
-#define DDRSS_CTL_150_DATA 0x800000C0\r
-#define DDRSS_CTL_151_DATA 0x800000C0\r
-#define DDRSS_CTL_152_DATA 0x800000C0\r
-#define DDRSS_CTL_153_DATA 0x00000000\r
-#define DDRSS_CTL_154_DATA 0x00001500\r
-#define DDRSS_CTL_155_DATA 0x00000000\r
-#define DDRSS_CTL_156_DATA 0x00000001\r
-#define DDRSS_CTL_157_DATA 0x00000002\r
-#define DDRSS_CTL_158_DATA 0x0000100E\r
-#define DDRSS_CTL_159_DATA 0x00000000\r
-#define DDRSS_CTL_160_DATA 0x00000000\r
-#define DDRSS_CTL_161_DATA 0x00000000\r
-#define DDRSS_CTL_162_DATA 0x00000000\r
-#define DDRSS_CTL_163_DATA 0x00000000\r
-#define DDRSS_CTL_164_DATA 0x000A0000\r
-#define DDRSS_CTL_165_DATA 0x000D0005\r
-#define DDRSS_CTL_166_DATA 0x000D0404\r
-#define DDRSS_CTL_167_DATA 0x00BB0176\r
-#define DDRSS_CTL_168_DATA 0x0E0E01D3\r
-#define DDRSS_CTL_169_DATA 0x017601D3\r
-#define DDRSS_CTL_170_DATA 0x01D300BB\r
-#define DDRSS_CTL_171_DATA 0x01D30E0E\r
-#define DDRSS_CTL_172_DATA 0x00000000\r
-#define DDRSS_CTL_173_DATA 0x00000000\r
-#define DDRSS_CTL_174_DATA 0x00000000\r
-#define DDRSS_CTL_175_DATA 0x36E40084\r
-#define DDRSS_CTL_176_DATA 0x330036E4\r
-#define DDRSS_CTL_177_DATA 0x00003333\r
-#define DDRSS_CTL_178_DATA 0x56000000\r
-#define DDRSS_CTL_179_DATA 0x27270056\r
-#define DDRSS_CTL_180_DATA 0x0F0F0000\r
-#define DDRSS_CTL_181_DATA 0x00000000\r
-#define DDRSS_CTL_182_DATA 0x00840606\r
-#define DDRSS_CTL_183_DATA 0x36E436E4\r
-#define DDRSS_CTL_184_DATA 0x33333300\r
-#define DDRSS_CTL_185_DATA 0x00000000\r
-#define DDRSS_CTL_186_DATA 0x00565600\r
-#define DDRSS_CTL_187_DATA 0x00002727\r
-#define DDRSS_CTL_188_DATA 0x00000F0F\r
-#define DDRSS_CTL_189_DATA 0x06060000\r
-#define DDRSS_CTL_190_DATA 0x00000020\r
-#define DDRSS_CTL_191_DATA 0x00000000\r
-#define DDRSS_CTL_192_DATA 0x00000001\r
-#define DDRSS_CTL_193_DATA 0x00000000\r
-#define DDRSS_CTL_194_DATA 0x01000000\r
-#define DDRSS_CTL_195_DATA 0x00000001\r
-#define DDRSS_CTL_196_DATA 0x00000000\r
-#define DDRSS_CTL_197_DATA 0x00000000\r
-#define DDRSS_CTL_198_DATA 0x00000000\r
-#define DDRSS_CTL_199_DATA 0x00000000\r
-#define DDRSS_CTL_200_DATA 0x00000000\r
-#define DDRSS_CTL_201_DATA 0x00000000\r
-#define DDRSS_CTL_202_DATA 0x00000000\r
-#define DDRSS_CTL_203_DATA 0x00000000\r
-#define DDRSS_CTL_204_DATA 0x00000000\r
-#define DDRSS_CTL_205_DATA 0x00000000\r
-#define DDRSS_CTL_206_DATA 0x02000000\r
-#define DDRSS_CTL_207_DATA 0x01080101\r
-#define DDRSS_CTL_208_DATA 0x00000000\r
-#define DDRSS_CTL_209_DATA 0x00000000\r
-#define DDRSS_CTL_210_DATA 0x00000000\r
-#define DDRSS_CTL_211_DATA 0x00000000\r
-#define DDRSS_CTL_212_DATA 0x00000000\r
-#define DDRSS_CTL_213_DATA 0x00000000\r
-#define DDRSS_CTL_214_DATA 0x00000000\r
-#define DDRSS_CTL_215_DATA 0x00000000\r
-#define DDRSS_CTL_216_DATA 0x00000000\r
-#define DDRSS_CTL_217_DATA 0x00000000\r
-#define DDRSS_CTL_218_DATA 0x00000000\r
-#define DDRSS_CTL_219_DATA 0x00000000\r
-#define DDRSS_CTL_220_DATA 0x00000000\r
-#define DDRSS_CTL_221_DATA 0x00000000\r
-#define DDRSS_CTL_222_DATA 0x00001000\r
-#define DDRSS_CTL_223_DATA 0x006403E8\r
-#define DDRSS_CTL_224_DATA 0x00000000\r
-#define DDRSS_CTL_225_DATA 0x00000000\r
-#define DDRSS_CTL_226_DATA 0x00000000\r
-#define DDRSS_CTL_227_DATA 0x15110000\r
-#define DDRSS_CTL_228_DATA 0x00040C18\r
-#define DDRSS_CTL_229_DATA 0x00000000\r
-#define DDRSS_CTL_230_DATA 0x00000000\r
-#define DDRSS_CTL_231_DATA 0x00000000\r
-#define DDRSS_CTL_232_DATA 0x00000000\r
-#define DDRSS_CTL_233_DATA 0x00000000\r
-#define DDRSS_CTL_234_DATA 0x00000000\r
-#define DDRSS_CTL_235_DATA 0x00000000\r
-#define DDRSS_CTL_236_DATA 0x00000000\r
-#define DDRSS_CTL_237_DATA 0x00000000\r
-#define DDRSS_CTL_238_DATA 0x00000000\r
-#define DDRSS_CTL_239_DATA 0x00000000\r
-#define DDRSS_CTL_240_DATA 0x00000000\r
-#define DDRSS_CTL_241_DATA 0x00000000\r
-#define DDRSS_CTL_242_DATA 0x00030000\r
-#define DDRSS_CTL_243_DATA 0x00000000\r
-#define DDRSS_CTL_244_DATA 0x00000000\r
-#define DDRSS_CTL_245_DATA 0x00000000\r
-#define DDRSS_CTL_246_DATA 0x00000000\r
-#define DDRSS_CTL_247_DATA 0x00000000\r
-#define DDRSS_CTL_248_DATA 0x00000000\r
-#define DDRSS_CTL_249_DATA 0x00000000\r
-#define DDRSS_CTL_250_DATA 0x00000000\r
-#define DDRSS_CTL_251_DATA 0x00000000\r
-#define DDRSS_CTL_252_DATA 0x00000000\r
-#define DDRSS_CTL_253_DATA 0x00000000\r
-#define DDRSS_CTL_254_DATA 0x00000000\r
-#define DDRSS_CTL_255_DATA 0x00000000\r
-#define DDRSS_CTL_256_DATA 0x00000000\r
-#define DDRSS_CTL_257_DATA 0x01000200\r
-#define DDRSS_CTL_258_DATA 0x00320040\r
-#define DDRSS_CTL_259_DATA 0x00020008\r
-#define DDRSS_CTL_260_DATA 0x00400100\r
-#define DDRSS_CTL_261_DATA 0x0038074A\r
-#define DDRSS_CTL_262_DATA 0x01000200\r
-#define DDRSS_CTL_263_DATA 0x074A0040\r
-#define DDRSS_CTL_264_DATA 0x00000038\r
-#define DDRSS_CTL_265_DATA 0x005E0003\r
-#define DDRSS_CTL_266_DATA 0x0100005E\r
-#define DDRSS_CTL_267_DATA 0x00000000\r
-#define DDRSS_CTL_268_DATA 0x01010000\r
-#define DDRSS_CTL_269_DATA 0x00000202\r
-#define DDRSS_CTL_270_DATA 0x00000FFF\r
-#define DDRSS_CTL_271_DATA 0x1FFF1000\r
-#define DDRSS_CTL_272_DATA 0x01FF0000\r
-#define DDRSS_CTL_273_DATA 0x000101FF\r
-#define DDRSS_CTL_274_DATA 0x0FFF0B00\r
-#define DDRSS_CTL_275_DATA 0x01010001\r
-#define DDRSS_CTL_276_DATA 0x01010101\r
-#define DDRSS_CTL_277_DATA 0x01180101\r
-#define DDRSS_CTL_278_DATA 0x00030000\r
-#define DDRSS_CTL_279_DATA 0x00000000\r
-#define DDRSS_CTL_280_DATA 0x00000000\r
-#define DDRSS_CTL_281_DATA 0x00000000\r
-#define DDRSS_CTL_282_DATA 0x00000000\r
-#define DDRSS_CTL_283_DATA 0x00000000\r
-#define DDRSS_CTL_284_DATA 0x00000000\r
-#define DDRSS_CTL_285_DATA 0x00000000\r
-#define DDRSS_CTL_286_DATA 0x00040101\r
-#define DDRSS_CTL_287_DATA 0x04010100\r
-#define DDRSS_CTL_288_DATA 0x00000000\r
-#define DDRSS_CTL_289_DATA 0x00000000\r
-#define DDRSS_CTL_290_DATA 0x03030300\r
-#define DDRSS_CTL_291_DATA 0x00000001\r
-#define DDRSS_CTL_292_DATA 0x00000000\r
-#define DDRSS_CTL_293_DATA 0x00000000\r
-#define DDRSS_CTL_294_DATA 0x00000000\r
-#define DDRSS_CTL_295_DATA 0x00000000\r
-#define DDRSS_CTL_296_DATA 0x00000000\r
-#define DDRSS_CTL_297_DATA 0x00000000\r
-#define DDRSS_CTL_298_DATA 0x00000000\r
-#define DDRSS_CTL_299_DATA 0x00000000\r
-#define DDRSS_CTL_300_DATA 0x00000000\r
-#define DDRSS_CTL_301_DATA 0x00000000\r
-#define DDRSS_CTL_302_DATA 0x00000000\r
-#define DDRSS_CTL_303_DATA 0x00000000\r
-#define DDRSS_CTL_304_DATA 0x00000000\r
-#define DDRSS_CTL_305_DATA 0x00000000\r
-#define DDRSS_CTL_306_DATA 0x00000000\r
-#define DDRSS_CTL_307_DATA 0x00000000\r
-#define DDRSS_CTL_308_DATA 0x00000000\r
-#define DDRSS_CTL_309_DATA 0x00000000\r
-#define DDRSS_CTL_310_DATA 0x00000000\r
-#define DDRSS_CTL_311_DATA 0x00000000\r
-#define DDRSS_CTL_312_DATA 0x00000000\r
-#define DDRSS_CTL_313_DATA 0x01000000\r
-#define DDRSS_CTL_314_DATA 0x00020201\r
-#define DDRSS_CTL_315_DATA 0x01000101\r
-#define DDRSS_CTL_316_DATA 0x01010001\r
-#define DDRSS_CTL_317_DATA 0x00010101\r
-#define DDRSS_CTL_318_DATA 0x05090903\r
-#define DDRSS_CTL_319_DATA 0x0E081B1B\r
-#define DDRSS_CTL_320_DATA 0x0009030E\r
-#define DDRSS_CTL_321_DATA 0x0A0D030F\r
-#define DDRSS_CTL_322_DATA 0x0A0D0306\r
-#define DDRSS_CTL_323_DATA 0x0D090006\r
-#define DDRSS_CTL_324_DATA 0x0100000D\r
-#define DDRSS_CTL_325_DATA 0x07030701\r
-#define DDRSS_CTL_326_DATA 0x00000003\r
-#define DDRSS_CTL_327_DATA 0x00000000\r
-#define DDRSS_CTL_328_DATA 0x00010000\r
-#define DDRSS_CTL_329_DATA 0x00280D00\r
-#define DDRSS_CTL_330_DATA 0x00000001\r
-#define DDRSS_CTL_331_DATA 0x00030001\r
-#define DDRSS_CTL_332_DATA 0x00000000\r
-#define DDRSS_CTL_333_DATA 0x00000000\r
-#define DDRSS_CTL_334_DATA 0x00000000\r
-#define DDRSS_CTL_335_DATA 0x00000000\r
-#define DDRSS_CTL_336_DATA 0x00000000\r
-#define DDRSS_CTL_337_DATA 0x00000000\r
-#define DDRSS_CTL_338_DATA 0x00000000\r
-#define DDRSS_CTL_339_DATA 0x00000000\r
-#define DDRSS_CTL_340_DATA 0x01000000\r
-#define DDRSS_CTL_341_DATA 0x00000001\r
-#define DDRSS_CTL_342_DATA 0x00010100\r
-#define DDRSS_CTL_343_DATA 0x03030000\r
-#define DDRSS_CTL_344_DATA 0x00000000\r
-#define DDRSS_CTL_345_DATA 0x00000000\r
-#define DDRSS_CTL_346_DATA 0x00000000\r
-#define DDRSS_CTL_347_DATA 0x00000000\r
-#define DDRSS_CTL_348_DATA 0x00000000\r
-#define DDRSS_CTL_349_DATA 0x00000000\r
-#define DDRSS_CTL_350_DATA 0x00000000\r
-#define DDRSS_CTL_351_DATA 0x00000000\r
-#define DDRSS_CTL_352_DATA 0x00000000\r
-#define DDRSS_CTL_353_DATA 0x00000000\r
-#define DDRSS_CTL_354_DATA 0x00000000\r
-#define DDRSS_CTL_355_DATA 0x00000000\r
-#define DDRSS_CTL_356_DATA 0x00000000\r
-#define DDRSS_CTL_357_DATA 0x00000000\r
-#define DDRSS_CTL_358_DATA 0x00000000\r
-#define DDRSS_CTL_359_DATA 0x00000000\r
-#define DDRSS_CTL_360_DATA 0x000556AA\r
-#define DDRSS_CTL_361_DATA 0x000AAAAA\r
-#define DDRSS_CTL_362_DATA 0x000AA955\r
-#define DDRSS_CTL_363_DATA 0x00055555\r
-#define DDRSS_CTL_364_DATA 0x000B3133\r
-#define DDRSS_CTL_365_DATA 0x0004CD33\r
-#define DDRSS_CTL_366_DATA 0x0004CECC\r
-#define DDRSS_CTL_367_DATA 0x000B32CC\r
-#define DDRSS_CTL_368_DATA 0x00010300\r
-#define DDRSS_CTL_369_DATA 0x03000100\r
-#define DDRSS_CTL_370_DATA 0x00000000\r
-#define DDRSS_CTL_371_DATA 0x00000000\r
-#define DDRSS_CTL_372_DATA 0x00000000\r
-#define DDRSS_CTL_373_DATA 0x00000000\r
-#define DDRSS_CTL_374_DATA 0x00000000\r
-#define DDRSS_CTL_375_DATA 0x00000000\r
-#define DDRSS_CTL_376_DATA 0x00000000\r
-#define DDRSS_CTL_377_DATA 0x00010000\r
-#define DDRSS_CTL_378_DATA 0x00000404\r
-#define DDRSS_CTL_379_DATA 0x00000000\r
-#define DDRSS_CTL_380_DATA 0x00000000\r
-#define DDRSS_CTL_381_DATA 0x00000000\r
-#define DDRSS_CTL_382_DATA 0x00000000\r
-#define DDRSS_CTL_383_DATA 0x00000000\r
-#define DDRSS_CTL_384_DATA 0x00000000\r
-#define DDRSS_CTL_385_DATA 0x00000000\r
-#define DDRSS_CTL_386_DATA 0x00000000\r
-#define DDRSS_CTL_387_DATA 0x37371B00\r
-#define DDRSS_CTL_388_DATA 0x000A0000\r
-#define DDRSS_CTL_389_DATA 0x00000176\r
-#define DDRSS_CTL_390_DATA 0x00000200\r
-#define DDRSS_CTL_391_DATA 0x00000200\r
-#define DDRSS_CTL_392_DATA 0x00000200\r
-#define DDRSS_CTL_393_DATA 0x00000200\r
-#define DDRSS_CTL_394_DATA 0x00000462\r
-#define DDRSS_CTL_395_DATA 0x00000E9C\r
-#define DDRSS_CTL_396_DATA 0x00000204\r
-#define DDRSS_CTL_397_DATA 0x000038C8\r
-#define DDRSS_CTL_398_DATA 0x00000200\r
-#define DDRSS_CTL_399_DATA 0x00000200\r
-#define DDRSS_CTL_400_DATA 0x00000200\r
-#define DDRSS_CTL_401_DATA 0x00000200\r
-#define DDRSS_CTL_402_DATA 0x0000AA58\r
-#define DDRSS_CTL_403_DATA 0x000237D0\r
-#define DDRSS_CTL_404_DATA 0x00000C12\r
-#define DDRSS_CTL_405_DATA 0x000038C8\r
-#define DDRSS_CTL_406_DATA 0x00000200\r
-#define DDRSS_CTL_407_DATA 0x00000200\r
-#define DDRSS_CTL_408_DATA 0x00000200\r
-#define DDRSS_CTL_409_DATA 0x00000200\r
-#define DDRSS_CTL_410_DATA 0x0000AA58\r
-#define DDRSS_CTL_411_DATA 0x000237D0\r
-#define DDRSS_CTL_412_DATA 0x02020C12\r
-#define DDRSS_CTL_413_DATA 0x03030202\r
-#define DDRSS_CTL_414_DATA 0x00000022\r
-#define DDRSS_CTL_415_DATA 0x00000000\r
-#define DDRSS_CTL_416_DATA 0x00000000\r
-#define DDRSS_CTL_417_DATA 0x00001403\r
-#define DDRSS_CTL_418_DATA 0x000007D0\r
-#define DDRSS_CTL_419_DATA 0x00000000\r
-#define DDRSS_CTL_420_DATA 0x00000000\r
-#define DDRSS_CTL_421_DATA 0x00030000\r
-#define DDRSS_CTL_422_DATA 0x0006001E\r
-#define DDRSS_CTL_423_DATA 0x00190031\r
-#define DDRSS_CTL_424_DATA 0x00190031\r
-#define DDRSS_CTL_425_DATA 0x00000000\r
-#define DDRSS_CTL_426_DATA 0x00000000\r
-#define DDRSS_CTL_427_DATA 0x02000000\r
-#define DDRSS_CTL_428_DATA 0x01000404\r
-#define DDRSS_CTL_429_DATA 0x091A091A\r
-#define DDRSS_CTL_430_DATA 0x00000105\r
-#define DDRSS_CTL_431_DATA 0x00010101\r
-#define DDRSS_CTL_432_DATA 0x00010101\r
-#define DDRSS_CTL_433_DATA 0x00010001\r
-#define DDRSS_CTL_434_DATA 0x00000101\r
-#define DDRSS_CTL_435_DATA 0x02000201\r
-#define DDRSS_CTL_436_DATA 0x02010000\r
-#define DDRSS_CTL_437_DATA 0x00000200\r
-#define DDRSS_CTL_438_DATA 0x22060000\r
-#define DDRSS_CTL_439_DATA 0x00000122\r
-#define DDRSS_CTL_440_DATA 0xFFFFFFFF\r
-#define DDRSS_CTL_441_DATA 0xFFFFFFFF\r
-#define DDRSS_CTL_442_DATA 0x00000000\r
-#define DDRSS_CTL_443_DATA 0x00000000\r
-#define DDRSS_CTL_444_DATA 0x00000000\r
-#define DDRSS_CTL_445_DATA 0x00000000\r
-#define DDRSS_CTL_446_DATA 0x00000000\r
-#define DDRSS_CTL_447_DATA 0x00000000\r
-#define DDRSS_CTL_448_DATA 0x00000000\r
-#define DDRSS_CTL_449_DATA 0x00000000\r
-#define DDRSS_CTL_450_DATA 0x00000000\r
-#define DDRSS_CTL_451_DATA 0x00000000\r
-#define DDRSS_CTL_452_DATA 0x00000000\r
-#define DDRSS_CTL_453_DATA 0x00000000\r
-#define DDRSS_CTL_454_DATA 0x00000000\r
-#define DDRSS_CTL_455_DATA 0x00000000\r
-#define DDRSS_CTL_456_DATA 0x00000000\r
-#define DDRSS_CTL_457_DATA 0x00000000\r
-#define DDRSS_CTL_458_DATA 0x00000000\r
+#define BOARD_DDR_SRAM_MAX (512U)\r
\r
-#define DDRSS_PI_00_DATA 0x00000B00\r
-#define DDRSS_PI_01_DATA 0x00000000\r
-#define DDRSS_PI_02_DATA 0x00000000\r
-#define DDRSS_PI_03_DATA 0x00000000\r
-#define DDRSS_PI_04_DATA 0x00000000\r
-#define DDRSS_PI_05_DATA 0x00000101\r
-#define DDRSS_PI_06_DATA 0x00640000\r
-#define DDRSS_PI_07_DATA 0x00000001\r
-#define DDRSS_PI_08_DATA 0x00000000\r
-#define DDRSS_PI_09_DATA 0x00000000\r
-#define DDRSS_PI_10_DATA 0x00000000\r
-#define DDRSS_PI_11_DATA 0x00000000\r
-#define DDRSS_PI_12_DATA 0x00000007\r
-#define DDRSS_PI_13_DATA 0x00010002\r
-#define DDRSS_PI_14_DATA 0x0800000F\r
-#define DDRSS_PI_15_DATA 0x00000103\r
-#define DDRSS_PI_16_DATA 0x00000005\r
-#define DDRSS_PI_17_DATA 0x00000000\r
-#define DDRSS_PI_18_DATA 0x00000000\r
-#define DDRSS_PI_19_DATA 0x00000000\r
-#define DDRSS_PI_20_DATA 0x00000000\r
-#define DDRSS_PI_21_DATA 0x00000000\r
-#define DDRSS_PI_22_DATA 0x00000000\r
-#define DDRSS_PI_23_DATA 0x00000000\r
-#define DDRSS_PI_24_DATA 0x00000000\r
-#define DDRSS_PI_25_DATA 0x00000000\r
-#define DDRSS_PI_26_DATA 0x00010100\r
-#define DDRSS_PI_27_DATA 0x00280A00\r
-#define DDRSS_PI_28_DATA 0x00000000\r
-#define DDRSS_PI_29_DATA 0x0F000000\r
-#define DDRSS_PI_30_DATA 0x00003200\r
-#define DDRSS_PI_31_DATA 0x00000000\r
-#define DDRSS_PI_32_DATA 0x00000000\r
-#define DDRSS_PI_33_DATA 0x01010102\r
-#define DDRSS_PI_34_DATA 0x00000000\r
-#define DDRSS_PI_35_DATA 0x000000AA\r
-#define DDRSS_PI_36_DATA 0x00000055\r
-#define DDRSS_PI_37_DATA 0x000000B5\r
-#define DDRSS_PI_38_DATA 0x0000004A\r
-#define DDRSS_PI_39_DATA 0x00000056\r
-#define DDRSS_PI_40_DATA 0x000000A9\r
-#define DDRSS_PI_41_DATA 0x000000A9\r
-#define DDRSS_PI_42_DATA 0x000000B5\r
-#define DDRSS_PI_43_DATA 0x00000000\r
-#define DDRSS_PI_44_DATA 0x00000000\r
-#define DDRSS_PI_45_DATA 0x000F0F00\r
-#define DDRSS_PI_46_DATA 0x00000019\r
-#define DDRSS_PI_47_DATA 0x000007D0\r
-#define DDRSS_PI_48_DATA 0x00000300\r
-#define DDRSS_PI_49_DATA 0x00000000\r
-#define DDRSS_PI_50_DATA 0x00000000\r
-#define DDRSS_PI_51_DATA 0x01000000\r
-#define DDRSS_PI_52_DATA 0x00010101\r
-#define DDRSS_PI_53_DATA 0x00000000\r
-#define DDRSS_PI_54_DATA 0x00030000\r
-#define DDRSS_PI_55_DATA 0x0F000000\r
-#define DDRSS_PI_56_DATA 0x00000017\r
-#define DDRSS_PI_57_DATA 0x00000000\r
-#define DDRSS_PI_58_DATA 0x00000000\r
-#define DDRSS_PI_59_DATA 0x00000000\r
-#define DDRSS_PI_60_DATA 0x0A0A140A\r
-#define DDRSS_PI_61_DATA 0x10020101\r
-#define DDRSS_PI_62_DATA 0x00020805\r
-#define DDRSS_PI_63_DATA 0x01000404\r
-#define DDRSS_PI_64_DATA 0x00000000\r
-#define DDRSS_PI_65_DATA 0x00000000\r
-#define DDRSS_PI_66_DATA 0x00000101\r
-#define DDRSS_PI_67_DATA 0x0001010F\r
-#define DDRSS_PI_68_DATA 0x00340000\r
-#define DDRSS_PI_69_DATA 0x00000000\r
-#define DDRSS_PI_70_DATA 0x00000000\r
-#define DDRSS_PI_71_DATA 0x00000000\r
-#define DDRSS_PI_72_DATA 0x01000000\r
-#define DDRSS_PI_73_DATA 0x00080100\r
-#define DDRSS_PI_74_DATA 0x02000200\r
-#define DDRSS_PI_75_DATA 0x01000100\r
-#define DDRSS_PI_76_DATA 0x01000000\r
-#define DDRSS_PI_77_DATA 0x02000200\r
-#define DDRSS_PI_78_DATA 0x00000200\r
-#define DDRSS_PI_79_DATA 0x00000000\r
-#define DDRSS_PI_80_DATA 0x00000000\r
-#define DDRSS_PI_81_DATA 0x00000000\r
-#define DDRSS_PI_82_DATA 0x00000000\r
-#define DDRSS_PI_83_DATA 0x00000000\r
-#define DDRSS_PI_84_DATA 0x00000000\r
-#define DDRSS_PI_85_DATA 0x00000000\r
-#define DDRSS_PI_86_DATA 0x00000000\r
-#define DDRSS_PI_87_DATA 0x00000000\r
-#define DDRSS_PI_88_DATA 0x00000000\r
-#define DDRSS_PI_89_DATA 0x00000000\r
-#define DDRSS_PI_90_DATA 0x00000000\r
-#define DDRSS_PI_91_DATA 0x00000400\r
-#define DDRSS_PI_92_DATA 0x02010000\r
-#define DDRSS_PI_93_DATA 0x00080003\r
-#define DDRSS_PI_94_DATA 0x00080000\r
-#define DDRSS_PI_95_DATA 0x00000001\r
-#define DDRSS_PI_96_DATA 0x00000000\r
-#define DDRSS_PI_97_DATA 0x0000AA00\r
-#define DDRSS_PI_98_DATA 0x00000000\r
-#define DDRSS_PI_99_DATA 0x00000000\r
-#define DDRSS_PI_100_DATA 0x00010000\r
-#define DDRSS_PI_101_DATA 0x00000000\r
-#define DDRSS_PI_102_DATA 0x00000000\r
-#define DDRSS_PI_103_DATA 0x00000000\r
-#define DDRSS_PI_104_DATA 0x00000000\r
-#define DDRSS_PI_105_DATA 0x00000000\r
-#define DDRSS_PI_106_DATA 0x00000000\r
-#define DDRSS_PI_107_DATA 0x00000000\r
-#define DDRSS_PI_108_DATA 0x00000000\r
-#define DDRSS_PI_109_DATA 0x00000000\r
-#define DDRSS_PI_110_DATA 0x00000000\r
-#define DDRSS_PI_111_DATA 0x00000000\r
-#define DDRSS_PI_112_DATA 0x00000000\r
-#define DDRSS_PI_113_DATA 0x00000000\r
-#define DDRSS_PI_114_DATA 0x00000000\r
-#define DDRSS_PI_115_DATA 0x00000000\r
-#define DDRSS_PI_116_DATA 0x00000000\r
-#define DDRSS_PI_117_DATA 0x00000000\r
-#define DDRSS_PI_118_DATA 0x00000000\r
-#define DDRSS_PI_119_DATA 0x00000000\r
-#define DDRSS_PI_120_DATA 0x00000000\r
-#define DDRSS_PI_121_DATA 0x00000000\r
-#define DDRSS_PI_122_DATA 0x00000000\r
-#define DDRSS_PI_123_DATA 0x00000000\r
-#define DDRSS_PI_124_DATA 0x00000000\r
-#define DDRSS_PI_125_DATA 0x00000008\r
-#define DDRSS_PI_126_DATA 0x00000000\r
-#define DDRSS_PI_127_DATA 0x00000000\r
-#define DDRSS_PI_128_DATA 0x00000000\r
-#define DDRSS_PI_129_DATA 0x00000000\r
-#define DDRSS_PI_130_DATA 0x00000000\r
-#define DDRSS_PI_131_DATA 0x00000000\r
-#define DDRSS_PI_132_DATA 0x00000000\r
-#define DDRSS_PI_133_DATA 0x00000000\r
-#define DDRSS_PI_134_DATA 0x00000002\r
-#define DDRSS_PI_135_DATA 0x00000000\r
-#define DDRSS_PI_136_DATA 0x00000000\r
-#define DDRSS_PI_137_DATA 0x0000000A\r
-#define DDRSS_PI_138_DATA 0x00000019\r
-#define DDRSS_PI_139_DATA 0x00000100\r
-#define DDRSS_PI_140_DATA 0x00000000\r
-#define DDRSS_PI_141_DATA 0x00000000\r
-#define DDRSS_PI_142_DATA 0x00000000\r
-#define DDRSS_PI_143_DATA 0x00000000\r
-#define DDRSS_PI_144_DATA 0x01000000\r
-#define DDRSS_PI_145_DATA 0x00010003\r
-#define DDRSS_PI_146_DATA 0x02000101\r
-#define DDRSS_PI_147_DATA 0x01030001\r
-#define DDRSS_PI_148_DATA 0x00010400\r
-#define DDRSS_PI_149_DATA 0x06000105\r
-#define DDRSS_PI_150_DATA 0x01070001\r
-#define DDRSS_PI_151_DATA 0x00000000\r
-#define DDRSS_PI_152_DATA 0x00000000\r
-#define DDRSS_PI_153_DATA 0x00000000\r
-#define DDRSS_PI_154_DATA 0x00010001\r
-#define DDRSS_PI_155_DATA 0x00000000\r
-#define DDRSS_PI_156_DATA 0x00000000\r
-#define DDRSS_PI_157_DATA 0x00000000\r
-#define DDRSS_PI_158_DATA 0x00000000\r
-#define DDRSS_PI_159_DATA 0x00000401\r
-#define DDRSS_PI_160_DATA 0x00000000\r
-#define DDRSS_PI_161_DATA 0x00010000\r
-#define DDRSS_PI_162_DATA 0x00000000\r
-#define DDRSS_PI_163_DATA 0x26260100\r
-#define DDRSS_PI_164_DATA 0x00000034\r
-#define DDRSS_PI_165_DATA 0x0000005E\r
-#define DDRSS_PI_166_DATA 0x0002005E\r
-#define DDRSS_PI_167_DATA 0x02000200\r
-#define DDRSS_PI_168_DATA 0x40100C04\r
-#define DDRSS_PI_169_DATA 0x000E4010\r
-#define DDRSS_PI_170_DATA 0x000000BB\r
-#define DDRSS_PI_171_DATA 0x0000020B\r
-#define DDRSS_PI_172_DATA 0x00001C64\r
-#define DDRSS_PI_173_DATA 0x0000020B\r
-#define DDRSS_PI_174_DATA 0x04001C64\r
-#define DDRSS_PI_175_DATA 0x01010404\r
-#define DDRSS_PI_176_DATA 0x00001501\r
-#define DDRSS_PI_177_DATA 0x00150015\r
-#define DDRSS_PI_178_DATA 0x01000100\r
-#define DDRSS_PI_179_DATA 0x00000100\r
-#define DDRSS_PI_180_DATA 0x00000000\r
-#define DDRSS_PI_181_DATA 0x01010101\r
-#define DDRSS_PI_182_DATA 0x00000101\r
-#define DDRSS_PI_183_DATA 0x00000000\r
-#define DDRSS_PI_184_DATA 0x00000000\r
-#define DDRSS_PI_185_DATA 0x12040000\r
-#define DDRSS_PI_186_DATA 0x0C0C0212\r
-#define DDRSS_PI_187_DATA 0x00040402\r
-#define DDRSS_PI_188_DATA 0x000C8034\r
-#define DDRSS_PI_189_DATA 0x001F0047\r
-#define DDRSS_PI_190_DATA 0x001F0047\r
-#define DDRSS_PI_191_DATA 0x01010101\r
-#define DDRSS_PI_192_DATA 0x0003000D\r
-#define DDRSS_PI_193_DATA 0x000301D3\r
-#define DDRSS_PI_194_DATA 0x010001D3\r
-#define DDRSS_PI_195_DATA 0x000E000E\r
-#define DDRSS_PI_196_DATA 0x01D40100\r
-#define DDRSS_PI_197_DATA 0x010001D4\r
-#define DDRSS_PI_198_DATA 0x01D401D4\r
-#define DDRSS_PI_199_DATA 0x32103200\r
-#define DDRSS_PI_200_DATA 0x01013210\r
-#define DDRSS_PI_201_DATA 0x0A070601\r
-#define DDRSS_PI_202_DATA 0x1C11090D\r
-#define DDRSS_PI_203_DATA 0x1C110913\r
-#define DDRSS_PI_204_DATA 0x0000C013\r
-#define DDRSS_PI_205_DATA 0x00C01000\r
-#define DDRSS_PI_206_DATA 0x00C01000\r
-#define DDRSS_PI_207_DATA 0x00021000\r
-#define DDRSS_PI_208_DATA 0x0021000D\r
-#define DDRSS_PI_209_DATA 0x002101D3\r
-#define DDRSS_PI_210_DATA 0x001101D3\r
-#define DDRSS_PI_211_DATA 0x32000056\r
-#define DDRSS_PI_212_DATA 0x00000101\r
-#define DDRSS_PI_213_DATA 0x005A0035\r
-#define DDRSS_PI_214_DATA 0x01013212\r
-#define DDRSS_PI_215_DATA 0x00003500\r
-#define DDRSS_PI_216_DATA 0x3212005A\r
-#define DDRSS_PI_217_DATA 0x09000101\r
-#define DDRSS_PI_218_DATA 0x04010504\r
-#define DDRSS_PI_219_DATA 0x0400062B\r
-#define DDRSS_PI_220_DATA 0x0A032001\r
-#define DDRSS_PI_221_DATA 0x262B0F0A\r
-#define DDRSS_PI_222_DATA 0x00002819\r
-#define DDRSS_PI_223_DATA 0x5400E638\r
-#define DDRSS_PI_224_DATA 0x1B1C2007\r
-#define DDRSS_PI_225_DATA 0x262B0F13\r
-#define DDRSS_PI_226_DATA 0x00002819\r
-#define DDRSS_PI_227_DATA 0x5400E638\r
-#define DDRSS_PI_228_DATA 0x1B1C2007\r
-#define DDRSS_PI_229_DATA 0x00017613\r
-#define DDRSS_PI_230_DATA 0x00000E9C\r
-#define DDRSS_PI_231_DATA 0x000038C8\r
-#define DDRSS_PI_232_DATA 0x000237D0\r
-#define DDRSS_PI_233_DATA 0x000038C8\r
-#define DDRSS_PI_234_DATA 0x000237D0\r
-#define DDRSS_PI_235_DATA 0x0219000F\r
-#define DDRSS_PI_236_DATA 0x03030219\r
-#define DDRSS_PI_237_DATA 0x00271003\r
-#define DDRSS_PI_238_DATA 0x000186A0\r
-#define DDRSS_PI_239_DATA 0x00000005\r
-#define DDRSS_PI_240_DATA 0x00000064\r
-#define DDRSS_PI_241_DATA 0x0000000F\r
-#define DDRSS_PI_242_DATA 0x0005B18F\r
-#define DDRSS_PI_243_DATA 0x000186A0\r
-#define DDRSS_PI_244_DATA 0x00000005\r
-#define DDRSS_PI_245_DATA 0x00000E94\r
-#define DDRSS_PI_246_DATA 0x00000219\r
-#define DDRSS_PI_247_DATA 0x0005B18F\r
-#define DDRSS_PI_248_DATA 0x000186A0\r
-#define DDRSS_PI_249_DATA 0x00000005\r
-#define DDRSS_PI_250_DATA 0x00000E94\r
-#define DDRSS_PI_251_DATA 0x01000219\r
-#define DDRSS_PI_252_DATA 0x00320040\r
-#define DDRSS_PI_253_DATA 0x00010008\r
-#define DDRSS_PI_254_DATA 0x074A0040\r
-#define DDRSS_PI_255_DATA 0x00010038\r
-#define DDRSS_PI_256_DATA 0x074A0040\r
-#define DDRSS_PI_257_DATA 0x00000338\r
-#define DDRSS_PI_258_DATA 0x005E005E\r
-#define DDRSS_PI_259_DATA 0x00040404\r
-#define DDRSS_PI_260_DATA 0x00000055\r
-#define DDRSS_PI_261_DATA 0x55003C5A\r
-#define DDRSS_PI_262_DATA 0x5A000000\r
-#define DDRSS_PI_263_DATA 0x0055003C\r
-#define DDRSS_PI_264_DATA 0x3C5A0000\r
-#define DDRSS_PI_265_DATA 0x00005500\r
-#define DDRSS_PI_266_DATA 0x0C3C5A00\r
-#define DDRSS_PI_267_DATA 0x080F0E0D\r
-#define DDRSS_PI_268_DATA 0x000B0A09\r
-#define DDRSS_PI_269_DATA 0x00030201\r
-#define DDRSS_PI_270_DATA 0x01000000\r
-#define DDRSS_PI_271_DATA 0x04020201\r
-#define DDRSS_PI_272_DATA 0x00080804\r
-#define DDRSS_PI_273_DATA 0x00000000\r
-#define DDRSS_PI_274_DATA 0x00000000\r
-#define DDRSS_PI_275_DATA 0x00330084\r
-#define DDRSS_PI_276_DATA 0x00160000\r
-#define DDRSS_PI_277_DATA 0x563336E4\r
-#define DDRSS_PI_278_DATA 0x00160F27\r
-#define DDRSS_PI_279_DATA 0x563336E4\r
-#define DDRSS_PI_280_DATA 0x00160F27\r
-#define DDRSS_PI_281_DATA 0x00330084\r
-#define DDRSS_PI_282_DATA 0x00160000\r
-#define DDRSS_PI_283_DATA 0x563336E4\r
-#define DDRSS_PI_284_DATA 0x00160F27\r
-#define DDRSS_PI_285_DATA 0x563336E4\r
-#define DDRSS_PI_286_DATA 0x00160F27\r
-#define DDRSS_PI_287_DATA 0x00330084\r
-#define DDRSS_PI_288_DATA 0x00160000\r
-#define DDRSS_PI_289_DATA 0x563336E4\r
-#define DDRSS_PI_290_DATA 0x00160F27\r
-#define DDRSS_PI_291_DATA 0x563336E4\r
-#define DDRSS_PI_292_DATA 0x00160F27\r
-#define DDRSS_PI_293_DATA 0x00330084\r
-#define DDRSS_PI_294_DATA 0x00160000\r
-#define DDRSS_PI_295_DATA 0x563336E4\r
-#define DDRSS_PI_296_DATA 0x00160F27\r
-#define DDRSS_PI_297_DATA 0x563336E4\r
-#define DDRSS_PI_298_DATA 0x00160F27\r
-#define DDRSS_PI_299_DATA 0x00000000\r
+#define TH_MACRO_EXP(fld, str) (fld##str)\r
\r
-#define DDRSS_PHY_00_DATA 0x000004F0\r
-#define DDRSS_PHY_01_DATA 0x00000000\r
-#define DDRSS_PHY_02_DATA 0x00030200\r
-#define DDRSS_PHY_03_DATA 0x00000000\r
-#define DDRSS_PHY_04_DATA 0x00000000\r
-#define DDRSS_PHY_05_DATA 0x01030000\r
-#define DDRSS_PHY_06_DATA 0x00010000\r
-#define DDRSS_PHY_07_DATA 0x01030004\r
-#define DDRSS_PHY_08_DATA 0x01000000\r
-#define DDRSS_PHY_09_DATA 0x00000000\r
-#define DDRSS_PHY_10_DATA 0x00000000\r
-#define DDRSS_PHY_11_DATA 0x01000001\r
-#define DDRSS_PHY_12_DATA 0x00000100\r
-#define DDRSS_PHY_13_DATA 0x000800C0\r
-#define DDRSS_PHY_14_DATA 0x060100CC\r
-#define DDRSS_PHY_15_DATA 0x00030066\r
-#define DDRSS_PHY_16_DATA 0x00000000\r
-#define DDRSS_PHY_17_DATA 0x00000001\r
-#define DDRSS_PHY_18_DATA 0x0000AAAA\r
-#define DDRSS_PHY_19_DATA 0x00005555\r
-#define DDRSS_PHY_20_DATA 0x0000B5B5\r
-#define DDRSS_PHY_21_DATA 0x00004A4A\r
-#define DDRSS_PHY_22_DATA 0x00005656\r
-#define DDRSS_PHY_23_DATA 0x0000A9A9\r
-#define DDRSS_PHY_24_DATA 0x0000A9A9\r
-#define DDRSS_PHY_25_DATA 0x0000B5B5\r
-#define DDRSS_PHY_26_DATA 0x00000000\r
-#define DDRSS_PHY_27_DATA 0x00000000\r
-#define DDRSS_PHY_28_DATA 0x2A000000\r
-#define DDRSS_PHY_29_DATA 0x00000808\r
-#define DDRSS_PHY_30_DATA 0x0F000000\r
-#define DDRSS_PHY_31_DATA 0x00000F0F\r
-#define DDRSS_PHY_32_DATA 0x10200000\r
-#define DDRSS_PHY_33_DATA 0x0C002004\r
-#define DDRSS_PHY_34_DATA 0x00000000\r
-#define DDRSS_PHY_35_DATA 0x00000000\r
-#define DDRSS_PHY_36_DATA 0x55555555\r
-#define DDRSS_PHY_37_DATA 0xAAAAAAAA\r
-#define DDRSS_PHY_38_DATA 0x55555555\r
-#define DDRSS_PHY_39_DATA 0xAAAAAAAA\r
-#define DDRSS_PHY_40_DATA 0x00005555\r
-#define DDRSS_PHY_41_DATA 0x01000100\r
-#define DDRSS_PHY_42_DATA 0x00800180\r
-#define DDRSS_PHY_43_DATA 0x00000001\r
-#define DDRSS_PHY_44_DATA 0x00000000\r
-#define DDRSS_PHY_45_DATA 0x00000000\r
-#define DDRSS_PHY_46_DATA 0x00000000\r
-#define DDRSS_PHY_47_DATA 0x00000000\r
-#define DDRSS_PHY_48_DATA 0x00000000\r
-#define DDRSS_PHY_49_DATA 0x00000000\r
-#define DDRSS_PHY_50_DATA 0x00000000\r
-#define DDRSS_PHY_51_DATA 0x00000000\r
-#define DDRSS_PHY_52_DATA 0x00000000\r
-#define DDRSS_PHY_53_DATA 0x00000000\r
-#define DDRSS_PHY_54_DATA 0x00000000\r
-#define DDRSS_PHY_55_DATA 0x00000000\r
-#define DDRSS_PHY_56_DATA 0x00000000\r
-#define DDRSS_PHY_57_DATA 0x00000000\r
-#define DDRSS_PHY_58_DATA 0x00000000\r
-#define DDRSS_PHY_59_DATA 0x00000000\r
-#define DDRSS_PHY_60_DATA 0x00000000\r
-#define DDRSS_PHY_61_DATA 0x00000000\r
-#define DDRSS_PHY_62_DATA 0x00000000\r
-#define DDRSS_PHY_63_DATA 0x00000000\r
-#define DDRSS_PHY_64_DATA 0x00000000\r
-#define DDRSS_PHY_65_DATA 0x00000000\r
-#define DDRSS_PHY_66_DATA 0x00000104\r
-#define DDRSS_PHY_67_DATA 0x00000120\r
-#define DDRSS_PHY_68_DATA 0x00000000\r
-#define DDRSS_PHY_69_DATA 0x00000000\r
-#define DDRSS_PHY_70_DATA 0x00000000\r
-#define DDRSS_PHY_71_DATA 0x00000000\r
-#define DDRSS_PHY_72_DATA 0x00000000\r
-#define DDRSS_PHY_73_DATA 0x00000000\r
-#define DDRSS_PHY_74_DATA 0x00000000\r
-#define DDRSS_PHY_75_DATA 0x00000001\r
-#define DDRSS_PHY_76_DATA 0x07FF0000\r
-#define DDRSS_PHY_77_DATA 0x0080081F\r
-#define DDRSS_PHY_78_DATA 0x00081020\r
-#define DDRSS_PHY_79_DATA 0x04010000\r
-#define DDRSS_PHY_80_DATA 0x00000000\r
-#define DDRSS_PHY_81_DATA 0x00000000\r
-#define DDRSS_PHY_82_DATA 0x00000000\r
-#define DDRSS_PHY_83_DATA 0x00000100\r
-#define DDRSS_PHY_84_DATA 0x01CC0C01\r
-#define DDRSS_PHY_85_DATA 0x0003CC0C\r
-#define DDRSS_PHY_86_DATA 0x20000140\r
-#define DDRSS_PHY_87_DATA 0x07FF0200\r
-#define DDRSS_PHY_88_DATA 0x0000DD01\r
-#define DDRSS_PHY_89_DATA 0x10100303\r
-#define DDRSS_PHY_90_DATA 0x10101010\r
-#define DDRSS_PHY_91_DATA 0x10101010\r
-#define DDRSS_PHY_92_DATA 0x00041010\r
-#define DDRSS_PHY_93_DATA 0x00100010\r
-#define DDRSS_PHY_94_DATA 0x00100010\r
-#define DDRSS_PHY_95_DATA 0x00100010\r
-#define DDRSS_PHY_96_DATA 0x00100010\r
-#define DDRSS_PHY_97_DATA 0x00050010\r
-#define DDRSS_PHY_98_DATA 0x51517041\r
-#define DDRSS_PHY_99_DATA 0x31C06000\r
-#define DDRSS_PHY_100_DATA 0x07AB0340\r
-#define DDRSS_PHY_101_DATA 0x00C0C001\r
-#define DDRSS_PHY_102_DATA 0x0D0C0001\r
-#define DDRSS_PHY_103_DATA 0x10001000\r
-#define DDRSS_PHY_104_DATA 0x0C063E42\r
-#define DDRSS_PHY_105_DATA 0x0F0C3201\r
-#define DDRSS_PHY_106_DATA 0x01000140\r
-#define DDRSS_PHY_107_DATA 0x0C000420\r
-#define DDRSS_PHY_108_DATA 0x000002DD\r
-#define DDRSS_PHY_109_DATA 0x0A0000D0\r
-#define DDRSS_PHY_110_DATA 0x00030200\r
-#define DDRSS_PHY_111_DATA 0x02800000\r
-#define DDRSS_PHY_112_DATA 0x80800000\r
-#define DDRSS_PHY_113_DATA 0x000D2010\r
-#define DDRSS_PHY_114_DATA 0x76543210\r
-#define DDRSS_PHY_115_DATA 0x00000008\r
-#define DDRSS_PHY_116_DATA 0x02800280\r
-#define DDRSS_PHY_117_DATA 0x02800280\r
-#define DDRSS_PHY_118_DATA 0x02800280\r
-#define DDRSS_PHY_119_DATA 0x02800280\r
-#define DDRSS_PHY_120_DATA 0x00000280\r
-#define DDRSS_PHY_121_DATA 0x0000A000\r
-#define DDRSS_PHY_122_DATA 0x00A000A0\r
-#define DDRSS_PHY_123_DATA 0x00A000A0\r
-#define DDRSS_PHY_124_DATA 0x00A000A0\r
-#define DDRSS_PHY_125_DATA 0x00A000A0\r
-#define DDRSS_PHY_126_DATA 0x00A000A0\r
-#define DDRSS_PHY_127_DATA 0x00A000A0\r
-#define DDRSS_PHY_128_DATA 0x00A000A0\r
-#define DDRSS_PHY_129_DATA 0x00A000A0\r
-#define DDRSS_PHY_130_DATA 0x006D00A0\r
-#define DDRSS_PHY_131_DATA 0x01A00005\r
-#define DDRSS_PHY_132_DATA 0x00000000\r
-#define DDRSS_PHY_133_DATA 0x00000000\r
-#define DDRSS_PHY_134_DATA 0x00080200\r
-#define DDRSS_PHY_135_DATA 0x00000000\r
-#define DDRSS_PHY_136_DATA 0x20202020\r
-#define DDRSS_PHY_137_DATA 0x20202020\r
-#define DDRSS_PHY_138_DATA 0xF0F02020\r
-#define DDRSS_PHY_139_DATA 0x00000000\r
-#define DDRSS_PHY_140_DATA 0x00000000\r
-#define DDRSS_PHY_141_DATA 0x00000000\r
-#define DDRSS_PHY_142_DATA 0x00000000\r
-#define DDRSS_PHY_143_DATA 0x00000000\r
-#define DDRSS_PHY_144_DATA 0x00000000\r
-#define DDRSS_PHY_145_DATA 0x00000000\r
-#define DDRSS_PHY_146_DATA 0x00000000\r
-#define DDRSS_PHY_147_DATA 0x00000000\r
-#define DDRSS_PHY_148_DATA 0x00000000\r
-#define DDRSS_PHY_149_DATA 0x00000000\r
-#define DDRSS_PHY_150_DATA 0x00000000\r
-#define DDRSS_PHY_151_DATA 0x00000000\r
-#define DDRSS_PHY_152_DATA 0x00000000\r
-#define DDRSS_PHY_153_DATA 0x00000000\r
-#define DDRSS_PHY_154_DATA 0x00000000\r
-#define DDRSS_PHY_155_DATA 0x00000000\r
-#define DDRSS_PHY_156_DATA 0x00000000\r
-#define DDRSS_PHY_157_DATA 0x00000000\r
-#define DDRSS_PHY_158_DATA 0x00000000\r
-#define DDRSS_PHY_159_DATA 0x00000000\r
-#define DDRSS_PHY_160_DATA 0x00000000\r
-#define DDRSS_PHY_161_DATA 0x00000000\r
-#define DDRSS_PHY_162_DATA 0x00000000\r
-#define DDRSS_PHY_163_DATA 0x00000000\r
-#define DDRSS_PHY_164_DATA 0x00000000\r
-#define DDRSS_PHY_165_DATA 0x00000000\r
-#define DDRSS_PHY_166_DATA 0x00000000\r
-#define DDRSS_PHY_167_DATA 0x00000000\r
-#define DDRSS_PHY_168_DATA 0x00000000\r
-#define DDRSS_PHY_169_DATA 0x00000000\r
-#define DDRSS_PHY_170_DATA 0x00000000\r
-#define DDRSS_PHY_171_DATA 0x00000000\r
-#define DDRSS_PHY_172_DATA 0x00000000\r
-#define DDRSS_PHY_173_DATA 0x00000000\r
-#define DDRSS_PHY_174_DATA 0x00000000\r
-#define DDRSS_PHY_175_DATA 0x00000000\r
-#define DDRSS_PHY_176_DATA 0x00000000\r
-#define DDRSS_PHY_177_DATA 0x00000000\r
-#define DDRSS_PHY_178_DATA 0x00000000\r
-#define DDRSS_PHY_179_DATA 0x00000000\r
-#define DDRSS_PHY_180_DATA 0x00000000\r
-#define DDRSS_PHY_181_DATA 0x00000000\r
-#define DDRSS_PHY_182_DATA 0x00000000\r
-#define DDRSS_PHY_183_DATA 0x00000000\r
-#define DDRSS_PHY_184_DATA 0x00000000\r
-#define DDRSS_PHY_185_DATA 0x00000000\r
-#define DDRSS_PHY_186_DATA 0x00000000\r
-#define DDRSS_PHY_187_DATA 0x00000000\r
-#define DDRSS_PHY_188_DATA 0x00000000\r
-#define DDRSS_PHY_189_DATA 0x00000000\r
-#define DDRSS_PHY_190_DATA 0x00000000\r
-#define DDRSS_PHY_191_DATA 0x00000000\r
-#define DDRSS_PHY_192_DATA 0x00000000\r
-#define DDRSS_PHY_193_DATA 0x00000000\r
-#define DDRSS_PHY_194_DATA 0x00000000\r
-#define DDRSS_PHY_195_DATA 0x00000000\r
-#define DDRSS_PHY_196_DATA 0x00000000\r
-#define DDRSS_PHY_197_DATA 0x00000000\r
-#define DDRSS_PHY_198_DATA 0x00000000\r
-#define DDRSS_PHY_199_DATA 0x00000000\r
-#define DDRSS_PHY_200_DATA 0x00000000\r
-#define DDRSS_PHY_201_DATA 0x00000000\r
-#define DDRSS_PHY_202_DATA 0x00000000\r
-#define DDRSS_PHY_203_DATA 0x00000000\r
-#define DDRSS_PHY_204_DATA 0x00000000\r
-#define DDRSS_PHY_205_DATA 0x00000000\r
-#define DDRSS_PHY_206_DATA 0x00000000\r
-#define DDRSS_PHY_207_DATA 0x00000000\r
-#define DDRSS_PHY_208_DATA 0x00000000\r
-#define DDRSS_PHY_209_DATA 0x00000000\r
-#define DDRSS_PHY_210_DATA 0x00000000\r
-#define DDRSS_PHY_211_DATA 0x00000000\r
-#define DDRSS_PHY_212_DATA 0x00000000\r
-#define DDRSS_PHY_213_DATA 0x00000000\r
-#define DDRSS_PHY_214_DATA 0x00000000\r
-#define DDRSS_PHY_215_DATA 0x00000000\r
-#define DDRSS_PHY_216_DATA 0x00000000\r
-#define DDRSS_PHY_217_DATA 0x00000000\r
-#define DDRSS_PHY_218_DATA 0x00000000\r
-#define DDRSS_PHY_219_DATA 0x00000000\r
-#define DDRSS_PHY_220_DATA 0x00000000\r
-#define DDRSS_PHY_221_DATA 0x00000000\r
-#define DDRSS_PHY_222_DATA 0x00000000\r
-#define DDRSS_PHY_223_DATA 0x00000000\r
-#define DDRSS_PHY_224_DATA 0x00000000\r
-#define DDRSS_PHY_225_DATA 0x00000000\r
-#define DDRSS_PHY_226_DATA 0x00000000\r
-#define DDRSS_PHY_227_DATA 0x00000000\r
-#define DDRSS_PHY_228_DATA 0x00000000\r
-#define DDRSS_PHY_229_DATA 0x00000000\r
-#define DDRSS_PHY_230_DATA 0x00000000\r
-#define DDRSS_PHY_231_DATA 0x00000000\r
-#define DDRSS_PHY_232_DATA 0x00000000\r
-#define DDRSS_PHY_233_DATA 0x00000000\r
-#define DDRSS_PHY_234_DATA 0x00000000\r
-#define DDRSS_PHY_235_DATA 0x00000000\r
-#define DDRSS_PHY_236_DATA 0x00000000\r
-#define DDRSS_PHY_237_DATA 0x00000000\r
-#define DDRSS_PHY_238_DATA 0x00000000\r
-#define DDRSS_PHY_239_DATA 0x00000000\r
-#define DDRSS_PHY_240_DATA 0x00000000\r
-#define DDRSS_PHY_241_DATA 0x00000000\r
-#define DDRSS_PHY_242_DATA 0x00000000\r
-#define DDRSS_PHY_243_DATA 0x00000000\r
-#define DDRSS_PHY_244_DATA 0x00000000\r
-#define DDRSS_PHY_245_DATA 0x00000000\r
-#define DDRSS_PHY_246_DATA 0x00000000\r
-#define DDRSS_PHY_247_DATA 0x00000000\r
-#define DDRSS_PHY_248_DATA 0x00000000\r
-#define DDRSS_PHY_249_DATA 0x00000000\r
-#define DDRSS_PHY_250_DATA 0x00000000\r
-#define DDRSS_PHY_251_DATA 0x00000000\r
-#define DDRSS_PHY_252_DATA 0x00000000\r
-#define DDRSS_PHY_253_DATA 0x00000000\r
-#define DDRSS_PHY_254_DATA 0x00000000\r
-#define DDRSS_PHY_255_DATA 0x00000000\r
-#define DDRSS_PHY_256_DATA 0x000004F0\r
-#define DDRSS_PHY_257_DATA 0x00000000\r
-#define DDRSS_PHY_258_DATA 0x00030200\r
-#define DDRSS_PHY_259_DATA 0x00000000\r
-#define DDRSS_PHY_260_DATA 0x00000000\r
-#define DDRSS_PHY_261_DATA 0x01030000\r
-#define DDRSS_PHY_262_DATA 0x00010000\r
-#define DDRSS_PHY_263_DATA 0x01030004\r
-#define DDRSS_PHY_264_DATA 0x01000000\r
-#define DDRSS_PHY_265_DATA 0x00000000\r
-#define DDRSS_PHY_266_DATA 0x00000000\r
-#define DDRSS_PHY_267_DATA 0x01000001\r
-#define DDRSS_PHY_268_DATA 0x00000100\r
-#define DDRSS_PHY_269_DATA 0x000800C0\r
-#define DDRSS_PHY_270_DATA 0x060100CC\r
-#define DDRSS_PHY_271_DATA 0x00030066\r
-#define DDRSS_PHY_272_DATA 0x00000000\r
-#define DDRSS_PHY_273_DATA 0x00000001\r
-#define DDRSS_PHY_274_DATA 0x0000AAAA\r
-#define DDRSS_PHY_275_DATA 0x00005555\r
-#define DDRSS_PHY_276_DATA 0x0000B5B5\r
-#define DDRSS_PHY_277_DATA 0x00004A4A\r
-#define DDRSS_PHY_278_DATA 0x00005656\r
-#define DDRSS_PHY_279_DATA 0x0000A9A9\r
-#define DDRSS_PHY_280_DATA 0x0000A9A9\r
-#define DDRSS_PHY_281_DATA 0x0000B5B5\r
-#define DDRSS_PHY_282_DATA 0x00000000\r
-#define DDRSS_PHY_283_DATA 0x00000000\r
-#define DDRSS_PHY_284_DATA 0x2A000000\r
-#define DDRSS_PHY_285_DATA 0x00000808\r
-#define DDRSS_PHY_286_DATA 0x0F000000\r
-#define DDRSS_PHY_287_DATA 0x00000F0F\r
-#define DDRSS_PHY_288_DATA 0x10200000\r
-#define DDRSS_PHY_289_DATA 0x0C002004\r
-#define DDRSS_PHY_290_DATA 0x00000000\r
-#define DDRSS_PHY_291_DATA 0x00000000\r
-#define DDRSS_PHY_292_DATA 0x55555555\r
-#define DDRSS_PHY_293_DATA 0xAAAAAAAA\r
-#define DDRSS_PHY_294_DATA 0x55555555\r
-#define DDRSS_PHY_295_DATA 0xAAAAAAAA\r
-#define DDRSS_PHY_296_DATA 0x00005555\r
-#define DDRSS_PHY_297_DATA 0x01000100\r
-#define DDRSS_PHY_298_DATA 0x00800180\r
-#define DDRSS_PHY_299_DATA 0x00000000\r
-#define DDRSS_PHY_300_DATA 0x00000000\r
-#define DDRSS_PHY_301_DATA 0x00000000\r
-#define DDRSS_PHY_302_DATA 0x00000000\r
-#define DDRSS_PHY_303_DATA 0x00000000\r
-#define DDRSS_PHY_304_DATA 0x00000000\r
-#define DDRSS_PHY_305_DATA 0x00000000\r
-#define DDRSS_PHY_306_DATA 0x00000000\r
-#define DDRSS_PHY_307_DATA 0x00000000\r
-#define DDRSS_PHY_308_DATA 0x00000000\r
-#define DDRSS_PHY_309_DATA 0x00000000\r
-#define DDRSS_PHY_310_DATA 0x00000000\r
-#define DDRSS_PHY_311_DATA 0x00000000\r
-#define DDRSS_PHY_312_DATA 0x00000000\r
-#define DDRSS_PHY_313_DATA 0x00000000\r
-#define DDRSS_PHY_314_DATA 0x00000000\r
-#define DDRSS_PHY_315_DATA 0x00000000\r
-#define DDRSS_PHY_316_DATA 0x00000000\r
-#define DDRSS_PHY_317_DATA 0x00000000\r
-#define DDRSS_PHY_318_DATA 0x00000000\r
-#define DDRSS_PHY_319_DATA 0x00000000\r
-#define DDRSS_PHY_320_DATA 0x00000000\r
-#define DDRSS_PHY_321_DATA 0x00000000\r
-#define DDRSS_PHY_322_DATA 0x00000104\r
-#define DDRSS_PHY_323_DATA 0x00000120\r
-#define DDRSS_PHY_324_DATA 0x00000000\r
-#define DDRSS_PHY_325_DATA 0x00000000\r
-#define DDRSS_PHY_326_DATA 0x00000000\r
-#define DDRSS_PHY_327_DATA 0x00000000\r
-#define DDRSS_PHY_328_DATA 0x00000000\r
-#define DDRSS_PHY_329_DATA 0x00000000\r
-#define DDRSS_PHY_330_DATA 0x00000000\r
-#define DDRSS_PHY_331_DATA 0x00000001\r
-#define DDRSS_PHY_332_DATA 0x07FF0000\r
-#define DDRSS_PHY_333_DATA 0x0080081F\r
-#define DDRSS_PHY_334_DATA 0x00081020\r
-#define DDRSS_PHY_335_DATA 0x04010000\r
-#define DDRSS_PHY_336_DATA 0x00000000\r
-#define DDRSS_PHY_337_DATA 0x00000000\r
-#define DDRSS_PHY_338_DATA 0x00000000\r
-#define DDRSS_PHY_339_DATA 0x00000100\r
-#define DDRSS_PHY_340_DATA 0x01CC0C01\r
-#define DDRSS_PHY_341_DATA 0x0003CC0C\r
-#define DDRSS_PHY_342_DATA 0x20000140\r
-#define DDRSS_PHY_343_DATA 0x07FF0200\r
-#define DDRSS_PHY_344_DATA 0x0000DD01\r
-#define DDRSS_PHY_345_DATA 0x10100303\r
-#define DDRSS_PHY_346_DATA 0x10101010\r
-#define DDRSS_PHY_347_DATA 0x10101010\r
-#define DDRSS_PHY_348_DATA 0x00041010\r
-#define DDRSS_PHY_349_DATA 0x00100010\r
-#define DDRSS_PHY_350_DATA 0x00100010\r
-#define DDRSS_PHY_351_DATA 0x00100010\r
-#define DDRSS_PHY_352_DATA 0x00100010\r
-#define DDRSS_PHY_353_DATA 0x00050010\r
-#define DDRSS_PHY_354_DATA 0x51517041\r
-#define DDRSS_PHY_355_DATA 0x31C06000\r
-#define DDRSS_PHY_356_DATA 0x07AB0340\r
-#define DDRSS_PHY_357_DATA 0x00C0C001\r
-#define DDRSS_PHY_358_DATA 0x0D0C0001\r
-#define DDRSS_PHY_359_DATA 0x10001000\r
-#define DDRSS_PHY_360_DATA 0x0C063E42\r
-#define DDRSS_PHY_361_DATA 0x0F0C3201\r
-#define DDRSS_PHY_362_DATA 0x01000140\r
-#define DDRSS_PHY_363_DATA 0x0C000420\r
-#define DDRSS_PHY_364_DATA 0x000002DD\r
-#define DDRSS_PHY_365_DATA 0x0A0000D0\r
-#define DDRSS_PHY_366_DATA 0x00030200\r
-#define DDRSS_PHY_367_DATA 0x02800000\r
-#define DDRSS_PHY_368_DATA 0x80800000\r
-#define DDRSS_PHY_369_DATA 0x000D2010\r
-#define DDRSS_PHY_370_DATA 0x76543210\r
-#define DDRSS_PHY_371_DATA 0x00000008\r
-#define DDRSS_PHY_372_DATA 0x02800280\r
-#define DDRSS_PHY_373_DATA 0x02800280\r
-#define DDRSS_PHY_374_DATA 0x02800280\r
-#define DDRSS_PHY_375_DATA 0x02800280\r
-#define DDRSS_PHY_376_DATA 0x00000280\r
-#define DDRSS_PHY_377_DATA 0x0000A000\r
-#define DDRSS_PHY_378_DATA 0x00A000A0\r
-#define DDRSS_PHY_379_DATA 0x00A000A0\r
-#define DDRSS_PHY_380_DATA 0x00A000A0\r
-#define DDRSS_PHY_381_DATA 0x00A000A0\r
-#define DDRSS_PHY_382_DATA 0x00A000A0\r
-#define DDRSS_PHY_383_DATA 0x00A000A0\r
-#define DDRSS_PHY_384_DATA 0x00A000A0\r
-#define DDRSS_PHY_385_DATA 0x00A000A0\r
-#define DDRSS_PHY_386_DATA 0x006D00A0\r
-#define DDRSS_PHY_387_DATA 0x01A00005\r
-#define DDRSS_PHY_388_DATA 0x00000000\r
-#define DDRSS_PHY_389_DATA 0x00000000\r
-#define DDRSS_PHY_390_DATA 0x00080200\r
-#define DDRSS_PHY_391_DATA 0x00000000\r
-#define DDRSS_PHY_392_DATA 0x20202020\r
-#define DDRSS_PHY_393_DATA 0x20202020\r
-#define DDRSS_PHY_394_DATA 0xF0F02020\r
-#define DDRSS_PHY_395_DATA 0x00000000\r
-#define DDRSS_PHY_396_DATA 0x00000000\r
-#define DDRSS_PHY_397_DATA 0x00000000\r
-#define DDRSS_PHY_398_DATA 0x00000000\r
-#define DDRSS_PHY_399_DATA 0x00000000\r
-#define DDRSS_PHY_400_DATA 0x00000000\r
-#define DDRSS_PHY_401_DATA 0x00000000\r
-#define DDRSS_PHY_402_DATA 0x00000000\r
-#define DDRSS_PHY_403_DATA 0x00000000\r
-#define DDRSS_PHY_404_DATA 0x00000000\r
-#define DDRSS_PHY_405_DATA 0x00000000\r
-#define DDRSS_PHY_406_DATA 0x00000000\r
-#define DDRSS_PHY_407_DATA 0x00000000\r
-#define DDRSS_PHY_408_DATA 0x00000000\r
-#define DDRSS_PHY_409_DATA 0x00000000\r
-#define DDRSS_PHY_410_DATA 0x00000000\r
-#define DDRSS_PHY_411_DATA 0x00000000\r
-#define DDRSS_PHY_412_DATA 0x00000000\r
-#define DDRSS_PHY_413_DATA 0x00000000\r
-#define DDRSS_PHY_414_DATA 0x00000000\r
-#define DDRSS_PHY_415_DATA 0x00000000\r
-#define DDRSS_PHY_416_DATA 0x00000000\r
-#define DDRSS_PHY_417_DATA 0x00000000\r
-#define DDRSS_PHY_418_DATA 0x00000000\r
-#define DDRSS_PHY_419_DATA 0x00000000\r
-#define DDRSS_PHY_420_DATA 0x00000000\r
-#define DDRSS_PHY_421_DATA 0x00000000\r
-#define DDRSS_PHY_422_DATA 0x00000000\r
-#define DDRSS_PHY_423_DATA 0x00000000\r
-#define DDRSS_PHY_424_DATA 0x00000000\r
-#define DDRSS_PHY_425_DATA 0x00000000\r
-#define DDRSS_PHY_426_DATA 0x00000000\r
-#define DDRSS_PHY_427_DATA 0x00000000\r
-#define DDRSS_PHY_428_DATA 0x00000000\r
-#define DDRSS_PHY_429_DATA 0x00000000\r
-#define DDRSS_PHY_430_DATA 0x00000000\r
-#define DDRSS_PHY_431_DATA 0x00000000\r
-#define DDRSS_PHY_432_DATA 0x00000000\r
-#define DDRSS_PHY_433_DATA 0x00000000\r
-#define DDRSS_PHY_434_DATA 0x00000000\r
-#define DDRSS_PHY_435_DATA 0x00000000\r
-#define DDRSS_PHY_436_DATA 0x00000000\r
-#define DDRSS_PHY_437_DATA 0x00000000\r
-#define DDRSS_PHY_438_DATA 0x00000000\r
-#define DDRSS_PHY_439_DATA 0x00000000\r
-#define DDRSS_PHY_440_DATA 0x00000000\r
-#define DDRSS_PHY_441_DATA 0x00000000\r
-#define DDRSS_PHY_442_DATA 0x00000000\r
-#define DDRSS_PHY_443_DATA 0x00000000\r
-#define DDRSS_PHY_444_DATA 0x00000000\r
-#define DDRSS_PHY_445_DATA 0x00000000\r
-#define DDRSS_PHY_446_DATA 0x00000000\r
-#define DDRSS_PHY_447_DATA 0x00000000\r
-#define DDRSS_PHY_448_DATA 0x00000000\r
-#define DDRSS_PHY_449_DATA 0x00000000\r
-#define DDRSS_PHY_450_DATA 0x00000000\r
-#define DDRSS_PHY_451_DATA 0x00000000\r
-#define DDRSS_PHY_452_DATA 0x00000000\r
-#define DDRSS_PHY_453_DATA 0x00000000\r
-#define DDRSS_PHY_454_DATA 0x00000000\r
-#define DDRSS_PHY_455_DATA 0x00000000\r
-#define DDRSS_PHY_456_DATA 0x00000000\r
-#define DDRSS_PHY_457_DATA 0x00000000\r
-#define DDRSS_PHY_458_DATA 0x00000000\r
-#define DDRSS_PHY_459_DATA 0x00000000\r
-#define DDRSS_PHY_460_DATA 0x00000000\r
-#define DDRSS_PHY_461_DATA 0x00000000\r
-#define DDRSS_PHY_462_DATA 0x00000000\r
-#define DDRSS_PHY_463_DATA 0x00000000\r
-#define DDRSS_PHY_464_DATA 0x00000000\r
-#define DDRSS_PHY_465_DATA 0x00000000\r
-#define DDRSS_PHY_466_DATA 0x00000000\r
-#define DDRSS_PHY_467_DATA 0x00000000\r
-#define DDRSS_PHY_468_DATA 0x00000000\r
-#define DDRSS_PHY_469_DATA 0x00000000\r
-#define DDRSS_PHY_470_DATA 0x00000000\r
-#define DDRSS_PHY_471_DATA 0x00000000\r
-#define DDRSS_PHY_472_DATA 0x00000000\r
-#define DDRSS_PHY_473_DATA 0x00000000\r
-#define DDRSS_PHY_474_DATA 0x00000000\r
-#define DDRSS_PHY_475_DATA 0x00000000\r
-#define DDRSS_PHY_476_DATA 0x00000000\r
-#define DDRSS_PHY_477_DATA 0x00000000\r
-#define DDRSS_PHY_478_DATA 0x00000000\r
-#define DDRSS_PHY_479_DATA 0x00000000\r
-#define DDRSS_PHY_480_DATA 0x00000000\r
-#define DDRSS_PHY_481_DATA 0x00000000\r
-#define DDRSS_PHY_482_DATA 0x00000000\r
-#define DDRSS_PHY_483_DATA 0x00000000\r
-#define DDRSS_PHY_484_DATA 0x00000000\r
-#define DDRSS_PHY_485_DATA 0x00000000\r
-#define DDRSS_PHY_486_DATA 0x00000000\r
-#define DDRSS_PHY_487_DATA 0x00000000\r
-#define DDRSS_PHY_488_DATA 0x00000000\r
-#define DDRSS_PHY_489_DATA 0x00000000\r
-#define DDRSS_PHY_490_DATA 0x00000000\r
-#define DDRSS_PHY_491_DATA 0x00000000\r
-#define DDRSS_PHY_492_DATA 0x00000000\r
-#define DDRSS_PHY_493_DATA 0x00000000\r
-#define DDRSS_PHY_494_DATA 0x00000000\r
-#define DDRSS_PHY_495_DATA 0x00000000\r
-#define DDRSS_PHY_496_DATA 0x00000000\r
-#define DDRSS_PHY_497_DATA 0x00000000\r
-#define DDRSS_PHY_498_DATA 0x00000000\r
-#define DDRSS_PHY_499_DATA 0x00000000\r
-#define DDRSS_PHY_500_DATA 0x00000000\r
-#define DDRSS_PHY_501_DATA 0x00000000\r
-#define DDRSS_PHY_502_DATA 0x00000000\r
-#define DDRSS_PHY_503_DATA 0x00000000\r
-#define DDRSS_PHY_504_DATA 0x00000000\r
-#define DDRSS_PHY_505_DATA 0x00000000\r
-#define DDRSS_PHY_506_DATA 0x00000000\r
-#define DDRSS_PHY_507_DATA 0x00000000\r
-#define DDRSS_PHY_508_DATA 0x00000000\r
-#define DDRSS_PHY_509_DATA 0x00000000\r
-#define DDRSS_PHY_510_DATA 0x00000000\r
-#define DDRSS_PHY_511_DATA 0x00000000\r
-#define DDRSS_PHY_512_DATA 0x000004F0\r
-#define DDRSS_PHY_513_DATA 0x00000000\r
-#define DDRSS_PHY_514_DATA 0x00030200\r
-#define DDRSS_PHY_515_DATA 0x00000000\r
-#define DDRSS_PHY_516_DATA 0x00000000\r
-#define DDRSS_PHY_517_DATA 0x01030000\r
-#define DDRSS_PHY_518_DATA 0x00010000\r
-#define DDRSS_PHY_519_DATA 0x01030004\r
-#define DDRSS_PHY_520_DATA 0x01000000\r
-#define DDRSS_PHY_521_DATA 0x00000000\r
-#define DDRSS_PHY_522_DATA 0x00000000\r
-#define DDRSS_PHY_523_DATA 0x01000001\r
-#define DDRSS_PHY_524_DATA 0x00000100\r
-#define DDRSS_PHY_525_DATA 0x000800C0\r
-#define DDRSS_PHY_526_DATA 0x060100CC\r
-#define DDRSS_PHY_527_DATA 0x00030066\r
-#define DDRSS_PHY_528_DATA 0x00000000\r
-#define DDRSS_PHY_529_DATA 0x00000001\r
-#define DDRSS_PHY_530_DATA 0x0000AAAA\r
-#define DDRSS_PHY_531_DATA 0x00005555\r
-#define DDRSS_PHY_532_DATA 0x0000B5B5\r
-#define DDRSS_PHY_533_DATA 0x00004A4A\r
-#define DDRSS_PHY_534_DATA 0x00005656\r
-#define DDRSS_PHY_535_DATA 0x0000A9A9\r
-#define DDRSS_PHY_536_DATA 0x0000A9A9\r
-#define DDRSS_PHY_537_DATA 0x0000B5B5\r
-#define DDRSS_PHY_538_DATA 0x00000000\r
-#define DDRSS_PHY_539_DATA 0x00000000\r
-#define DDRSS_PHY_540_DATA 0x2A000000\r
-#define DDRSS_PHY_541_DATA 0x00000808\r
-#define DDRSS_PHY_542_DATA 0x0F000000\r
-#define DDRSS_PHY_543_DATA 0x00000F0F\r
-#define DDRSS_PHY_544_DATA 0x10200000\r
-#define DDRSS_PHY_545_DATA 0x0C002004\r
-#define DDRSS_PHY_546_DATA 0x00000000\r
-#define DDRSS_PHY_547_DATA 0x00000000\r
-#define DDRSS_PHY_548_DATA 0x55555555\r
-#define DDRSS_PHY_549_DATA 0xAAAAAAAA\r
-#define DDRSS_PHY_550_DATA 0x55555555\r
-#define DDRSS_PHY_551_DATA 0xAAAAAAAA\r
-#define DDRSS_PHY_552_DATA 0x00005555\r
-#define DDRSS_PHY_553_DATA 0x01000100\r
-#define DDRSS_PHY_554_DATA 0x00800180\r
-#define DDRSS_PHY_555_DATA 0x00000001\r
-#define DDRSS_PHY_556_DATA 0x00000000\r
-#define DDRSS_PHY_557_DATA 0x00000000\r
-#define DDRSS_PHY_558_DATA 0x00000000\r
-#define DDRSS_PHY_559_DATA 0x00000000\r
-#define DDRSS_PHY_560_DATA 0x00000000\r
-#define DDRSS_PHY_561_DATA 0x00000000\r
-#define DDRSS_PHY_562_DATA 0x00000000\r
-#define DDRSS_PHY_563_DATA 0x00000000\r
-#define DDRSS_PHY_564_DATA 0x00000000\r
-#define DDRSS_PHY_565_DATA 0x00000000\r
-#define DDRSS_PHY_566_DATA 0x00000000\r
-#define DDRSS_PHY_567_DATA 0x00000000\r
-#define DDRSS_PHY_568_DATA 0x00000000\r
-#define DDRSS_PHY_569_DATA 0x00000000\r
-#define DDRSS_PHY_570_DATA 0x00000000\r
-#define DDRSS_PHY_571_DATA 0x00000000\r
-#define DDRSS_PHY_572_DATA 0x00000000\r
-#define DDRSS_PHY_573_DATA 0x00000000\r
-#define DDRSS_PHY_574_DATA 0x00000000\r
-#define DDRSS_PHY_575_DATA 0x00000000\r
-#define DDRSS_PHY_576_DATA 0x00000000\r
-#define DDRSS_PHY_577_DATA 0x00000000\r
-#define DDRSS_PHY_578_DATA 0x00000104\r
-#define DDRSS_PHY_579_DATA 0x00000120\r
-#define DDRSS_PHY_580_DATA 0x00000000\r
-#define DDRSS_PHY_581_DATA 0x00000000\r
-#define DDRSS_PHY_582_DATA 0x00000000\r
-#define DDRSS_PHY_583_DATA 0x00000000\r
-#define DDRSS_PHY_584_DATA 0x00000000\r
-#define DDRSS_PHY_585_DATA 0x00000000\r
-#define DDRSS_PHY_586_DATA 0x00000000\r
-#define DDRSS_PHY_587_DATA 0x00000001\r
-#define DDRSS_PHY_588_DATA 0x07FF0000\r
-#define DDRSS_PHY_589_DATA 0x0080081F\r
-#define DDRSS_PHY_590_DATA 0x00081020\r
-#define DDRSS_PHY_591_DATA 0x04010000\r
-#define DDRSS_PHY_592_DATA 0x00000000\r
-#define DDRSS_PHY_593_DATA 0x00000000\r
-#define DDRSS_PHY_594_DATA 0x00000000\r
-#define DDRSS_PHY_595_DATA 0x00000100\r
-#define DDRSS_PHY_596_DATA 0x01CC0C01\r
-#define DDRSS_PHY_597_DATA 0x0003CC0C\r
-#define DDRSS_PHY_598_DATA 0x20000140\r
-#define DDRSS_PHY_599_DATA 0x07FF0200\r
-#define DDRSS_PHY_600_DATA 0x0000DD01\r
-#define DDRSS_PHY_601_DATA 0x10100303\r
-#define DDRSS_PHY_602_DATA 0x10101010\r
-#define DDRSS_PHY_603_DATA 0x10101010\r
-#define DDRSS_PHY_604_DATA 0x00041010\r
-#define DDRSS_PHY_605_DATA 0x00100010\r
-#define DDRSS_PHY_606_DATA 0x00100010\r
-#define DDRSS_PHY_607_DATA 0x00100010\r
-#define DDRSS_PHY_608_DATA 0x00100010\r
-#define DDRSS_PHY_609_DATA 0x00050010\r
-#define DDRSS_PHY_610_DATA 0x51517041\r
-#define DDRSS_PHY_611_DATA 0x31C06000\r
-#define DDRSS_PHY_612_DATA 0x07AB0340\r
-#define DDRSS_PHY_613_DATA 0x00C0C001\r
-#define DDRSS_PHY_614_DATA 0x0D0C0001\r
-#define DDRSS_PHY_615_DATA 0x10001000\r
-#define DDRSS_PHY_616_DATA 0x0C063E42\r
-#define DDRSS_PHY_617_DATA 0x0F0C3201\r
-#define DDRSS_PHY_618_DATA 0x01000140\r
-#define DDRSS_PHY_619_DATA 0x0C000420\r
-#define DDRSS_PHY_620_DATA 0x000002DD\r
-#define DDRSS_PHY_621_DATA 0x0A0000D0\r
-#define DDRSS_PHY_622_DATA 0x00030200\r
-#define DDRSS_PHY_623_DATA 0x02800000\r
-#define DDRSS_PHY_624_DATA 0x80800000\r
-#define DDRSS_PHY_625_DATA 0x000D2010\r
-#define DDRSS_PHY_626_DATA 0x76543210\r
-#define DDRSS_PHY_627_DATA 0x00000008\r
-#define DDRSS_PHY_628_DATA 0x02800280\r
-#define DDRSS_PHY_629_DATA 0x02800280\r
-#define DDRSS_PHY_630_DATA 0x02800280\r
-#define DDRSS_PHY_631_DATA 0x02800280\r
-#define DDRSS_PHY_632_DATA 0x00000280\r
-#define DDRSS_PHY_633_DATA 0x0000A000\r
-#define DDRSS_PHY_634_DATA 0x00A000A0\r
-#define DDRSS_PHY_635_DATA 0x00A000A0\r
-#define DDRSS_PHY_636_DATA 0x00A000A0\r
-#define DDRSS_PHY_637_DATA 0x00A000A0\r
-#define DDRSS_PHY_638_DATA 0x00A000A0\r
-#define DDRSS_PHY_639_DATA 0x00A000A0\r
-#define DDRSS_PHY_640_DATA 0x00A000A0\r
-#define DDRSS_PHY_641_DATA 0x00A000A0\r
-#define DDRSS_PHY_642_DATA 0x006D00A0\r
-#define DDRSS_PHY_643_DATA 0x01A00005\r
-#define DDRSS_PHY_644_DATA 0x00000000\r
-#define DDRSS_PHY_645_DATA 0x00000000\r
-#define DDRSS_PHY_646_DATA 0x00080200\r
-#define DDRSS_PHY_647_DATA 0x00000000\r
-#define DDRSS_PHY_648_DATA 0x20202020\r
-#define DDRSS_PHY_649_DATA 0x20202020\r
-#define DDRSS_PHY_650_DATA 0xF0F02020\r
-#define DDRSS_PHY_651_DATA 0x00000000\r
-#define DDRSS_PHY_652_DATA 0x00000000\r
-#define DDRSS_PHY_653_DATA 0x00000000\r
-#define DDRSS_PHY_654_DATA 0x00000000\r
-#define DDRSS_PHY_655_DATA 0x00000000\r
-#define DDRSS_PHY_656_DATA 0x00000000\r
-#define DDRSS_PHY_657_DATA 0x00000000\r
-#define DDRSS_PHY_658_DATA 0x00000000\r
-#define DDRSS_PHY_659_DATA 0x00000000\r
-#define DDRSS_PHY_660_DATA 0x00000000\r
-#define DDRSS_PHY_661_DATA 0x00000000\r
-#define DDRSS_PHY_662_DATA 0x00000000\r
-#define DDRSS_PHY_663_DATA 0x00000000\r
-#define DDRSS_PHY_664_DATA 0x00000000\r
-#define DDRSS_PHY_665_DATA 0x00000000\r
-#define DDRSS_PHY_666_DATA 0x00000000\r
-#define DDRSS_PHY_667_DATA 0x00000000\r
-#define DDRSS_PHY_668_DATA 0x00000000\r
-#define DDRSS_PHY_669_DATA 0x00000000\r
-#define DDRSS_PHY_670_DATA 0x00000000\r
-#define DDRSS_PHY_671_DATA 0x00000000\r
-#define DDRSS_PHY_672_DATA 0x00000000\r
-#define DDRSS_PHY_673_DATA 0x00000000\r
-#define DDRSS_PHY_674_DATA 0x00000000\r
-#define DDRSS_PHY_675_DATA 0x00000000\r
-#define DDRSS_PHY_676_DATA 0x00000000\r
-#define DDRSS_PHY_677_DATA 0x00000000\r
-#define DDRSS_PHY_678_DATA 0x00000000\r
-#define DDRSS_PHY_679_DATA 0x00000000\r
-#define DDRSS_PHY_680_DATA 0x00000000\r
-#define DDRSS_PHY_681_DATA 0x00000000\r
-#define DDRSS_PHY_682_DATA 0x00000000\r
-#define DDRSS_PHY_683_DATA 0x00000000\r
-#define DDRSS_PHY_684_DATA 0x00000000\r
-#define DDRSS_PHY_685_DATA 0x00000000\r
-#define DDRSS_PHY_686_DATA 0x00000000\r
-#define DDRSS_PHY_687_DATA 0x00000000\r
-#define DDRSS_PHY_688_DATA 0x00000000\r
-#define DDRSS_PHY_689_DATA 0x00000000\r
-#define DDRSS_PHY_690_DATA 0x00000000\r
-#define DDRSS_PHY_691_DATA 0x00000000\r
-#define DDRSS_PHY_692_DATA 0x00000000\r
-#define DDRSS_PHY_693_DATA 0x00000000\r
-#define DDRSS_PHY_694_DATA 0x00000000\r
-#define DDRSS_PHY_695_DATA 0x00000000\r
-#define DDRSS_PHY_696_DATA 0x00000000\r
-#define DDRSS_PHY_697_DATA 0x00000000\r
-#define DDRSS_PHY_698_DATA 0x00000000\r
-#define DDRSS_PHY_699_DATA 0x00000000\r
-#define DDRSS_PHY_700_DATA 0x00000000\r
-#define DDRSS_PHY_701_DATA 0x00000000\r
-#define DDRSS_PHY_702_DATA 0x00000000\r
-#define DDRSS_PHY_703_DATA 0x00000000\r
-#define DDRSS_PHY_704_DATA 0x00000000\r
-#define DDRSS_PHY_705_DATA 0x00000000\r
-#define DDRSS_PHY_706_DATA 0x00000000\r
-#define DDRSS_PHY_707_DATA 0x00000000\r
-#define DDRSS_PHY_708_DATA 0x00000000\r
-#define DDRSS_PHY_709_DATA 0x00000000\r
-#define DDRSS_PHY_710_DATA 0x00000000\r
-#define DDRSS_PHY_711_DATA 0x00000000\r
-#define DDRSS_PHY_712_DATA 0x00000000\r
-#define DDRSS_PHY_713_DATA 0x00000000\r
-#define DDRSS_PHY_714_DATA 0x00000000\r
-#define DDRSS_PHY_715_DATA 0x00000000\r
-#define DDRSS_PHY_716_DATA 0x00000000\r
-#define DDRSS_PHY_717_DATA 0x00000000\r
-#define DDRSS_PHY_718_DATA 0x00000000\r
-#define DDRSS_PHY_719_DATA 0x00000000\r
-#define DDRSS_PHY_720_DATA 0x00000000\r
-#define DDRSS_PHY_721_DATA 0x00000000\r
-#define DDRSS_PHY_722_DATA 0x00000000\r
-#define DDRSS_PHY_723_DATA 0x00000000\r
-#define DDRSS_PHY_724_DATA 0x00000000\r
-#define DDRSS_PHY_725_DATA 0x00000000\r
-#define DDRSS_PHY_726_DATA 0x00000000\r
-#define DDRSS_PHY_727_DATA 0x00000000\r
-#define DDRSS_PHY_728_DATA 0x00000000\r
-#define DDRSS_PHY_729_DATA 0x00000000\r
-#define DDRSS_PHY_730_DATA 0x00000000\r
-#define DDRSS_PHY_731_DATA 0x00000000\r
-#define DDRSS_PHY_732_DATA 0x00000000\r
-#define DDRSS_PHY_733_DATA 0x00000000\r
-#define DDRSS_PHY_734_DATA 0x00000000\r
-#define DDRSS_PHY_735_DATA 0x00000000\r
-#define DDRSS_PHY_736_DATA 0x00000000\r
-#define DDRSS_PHY_737_DATA 0x00000000\r
-#define DDRSS_PHY_738_DATA 0x00000000\r
-#define DDRSS_PHY_739_DATA 0x00000000\r
-#define DDRSS_PHY_740_DATA 0x00000000\r
-#define DDRSS_PHY_741_DATA 0x00000000\r
-#define DDRSS_PHY_742_DATA 0x00000000\r
-#define DDRSS_PHY_743_DATA 0x00000000\r
-#define DDRSS_PHY_744_DATA 0x00000000\r
-#define DDRSS_PHY_745_DATA 0x00000000\r
-#define DDRSS_PHY_746_DATA 0x00000000\r
-#define DDRSS_PHY_747_DATA 0x00000000\r
-#define DDRSS_PHY_748_DATA 0x00000000\r
-#define DDRSS_PHY_749_DATA 0x00000000\r
-#define DDRSS_PHY_750_DATA 0x00000000\r
-#define DDRSS_PHY_751_DATA 0x00000000\r
-#define DDRSS_PHY_752_DATA 0x00000000\r
-#define DDRSS_PHY_753_DATA 0x00000000\r
-#define DDRSS_PHY_754_DATA 0x00000000\r
-#define DDRSS_PHY_755_DATA 0x00000000\r
-#define DDRSS_PHY_756_DATA 0x00000000\r
-#define DDRSS_PHY_757_DATA 0x00000000\r
-#define DDRSS_PHY_758_DATA 0x00000000\r
-#define DDRSS_PHY_759_DATA 0x00000000\r
-#define DDRSS_PHY_760_DATA 0x00000000\r
-#define DDRSS_PHY_761_DATA 0x00000000\r
-#define DDRSS_PHY_762_DATA 0x00000000\r
-#define DDRSS_PHY_763_DATA 0x00000000\r
-#define DDRSS_PHY_764_DATA 0x00000000\r
-#define DDRSS_PHY_765_DATA 0x00000000\r
-#define DDRSS_PHY_766_DATA 0x00000000\r
-#define DDRSS_PHY_767_DATA 0x00000000\r
-#define DDRSS_PHY_768_DATA 0x000004F0\r
-#define DDRSS_PHY_769_DATA 0x00000000\r
-#define DDRSS_PHY_770_DATA 0x00030200\r
-#define DDRSS_PHY_771_DATA 0x00000000\r
-#define DDRSS_PHY_772_DATA 0x00000000\r
-#define DDRSS_PHY_773_DATA 0x01030000\r
-#define DDRSS_PHY_774_DATA 0x00010000\r
-#define DDRSS_PHY_775_DATA 0x01030004\r
-#define DDRSS_PHY_776_DATA 0x01000000\r
-#define DDRSS_PHY_777_DATA 0x00000000\r
-#define DDRSS_PHY_778_DATA 0x00000000\r
-#define DDRSS_PHY_779_DATA 0x01000001\r
-#define DDRSS_PHY_780_DATA 0x00000100\r
-#define DDRSS_PHY_781_DATA 0x000800C0\r
-#define DDRSS_PHY_782_DATA 0x060100CC\r
-#define DDRSS_PHY_783_DATA 0x00030066\r
-#define DDRSS_PHY_784_DATA 0x00000000\r
-#define DDRSS_PHY_785_DATA 0x00000001\r
-#define DDRSS_PHY_786_DATA 0x0000AAAA\r
-#define DDRSS_PHY_787_DATA 0x00005555\r
-#define DDRSS_PHY_788_DATA 0x0000B5B5\r
-#define DDRSS_PHY_789_DATA 0x00004A4A\r
-#define DDRSS_PHY_790_DATA 0x00005656\r
-#define DDRSS_PHY_791_DATA 0x0000A9A9\r
-#define DDRSS_PHY_792_DATA 0x0000A9A9\r
-#define DDRSS_PHY_793_DATA 0x0000B5B5\r
-#define DDRSS_PHY_794_DATA 0x00000000\r
-#define DDRSS_PHY_795_DATA 0x00000000\r
-#define DDRSS_PHY_796_DATA 0x2A000000\r
-#define DDRSS_PHY_797_DATA 0x00000808\r
-#define DDRSS_PHY_798_DATA 0x0F000000\r
-#define DDRSS_PHY_799_DATA 0x00000F0F\r
-#define DDRSS_PHY_800_DATA 0x10200000\r
-#define DDRSS_PHY_801_DATA 0x0C002004\r
-#define DDRSS_PHY_802_DATA 0x00000000\r
-#define DDRSS_PHY_803_DATA 0x00000000\r
-#define DDRSS_PHY_804_DATA 0x55555555\r
-#define DDRSS_PHY_805_DATA 0xAAAAAAAA\r
-#define DDRSS_PHY_806_DATA 0x55555555\r
-#define DDRSS_PHY_807_DATA 0xAAAAAAAA\r
-#define DDRSS_PHY_808_DATA 0x00005555\r
-#define DDRSS_PHY_809_DATA 0x01000100\r
-#define DDRSS_PHY_810_DATA 0x00800180\r
-#define DDRSS_PHY_811_DATA 0x00000000\r
-#define DDRSS_PHY_812_DATA 0x00000000\r
-#define DDRSS_PHY_813_DATA 0x00000000\r
-#define DDRSS_PHY_814_DATA 0x00000000\r
-#define DDRSS_PHY_815_DATA 0x00000000\r
-#define DDRSS_PHY_816_DATA 0x00000000\r
-#define DDRSS_PHY_817_DATA 0x00000000\r
-#define DDRSS_PHY_818_DATA 0x00000000\r
-#define DDRSS_PHY_819_DATA 0x00000000\r
-#define DDRSS_PHY_820_DATA 0x00000000\r
-#define DDRSS_PHY_821_DATA 0x00000000\r
-#define DDRSS_PHY_822_DATA 0x00000000\r
-#define DDRSS_PHY_823_DATA 0x00000000\r
-#define DDRSS_PHY_824_DATA 0x00000000\r
-#define DDRSS_PHY_825_DATA 0x00000000\r
-#define DDRSS_PHY_826_DATA 0x00000000\r
-#define DDRSS_PHY_827_DATA 0x00000000\r
-#define DDRSS_PHY_828_DATA 0x00000000\r
-#define DDRSS_PHY_829_DATA 0x00000000\r
-#define DDRSS_PHY_830_DATA 0x00000000\r
-#define DDRSS_PHY_831_DATA 0x00000000\r
-#define DDRSS_PHY_832_DATA 0x00000000\r
-#define DDRSS_PHY_833_DATA 0x00000000\r
-#define DDRSS_PHY_834_DATA 0x00000104\r
-#define DDRSS_PHY_835_DATA 0x00000120\r
-#define DDRSS_PHY_836_DATA 0x00000000\r
-#define DDRSS_PHY_837_DATA 0x00000000\r
-#define DDRSS_PHY_838_DATA 0x00000000\r
-#define DDRSS_PHY_839_DATA 0x00000000\r
-#define DDRSS_PHY_840_DATA 0x00000000\r
-#define DDRSS_PHY_841_DATA 0x00000000\r
-#define DDRSS_PHY_842_DATA 0x00000000\r
-#define DDRSS_PHY_843_DATA 0x00000001\r
-#define DDRSS_PHY_844_DATA 0x07FF0000\r
-#define DDRSS_PHY_845_DATA 0x0080081F\r
-#define DDRSS_PHY_846_DATA 0x00081020\r
-#define DDRSS_PHY_847_DATA 0x04010000\r
-#define DDRSS_PHY_848_DATA 0x00000000\r
-#define DDRSS_PHY_849_DATA 0x00000000\r
-#define DDRSS_PHY_850_DATA 0x00000000\r
-#define DDRSS_PHY_851_DATA 0x00000100\r
-#define DDRSS_PHY_852_DATA 0x01CC0C01\r
-#define DDRSS_PHY_853_DATA 0x0003CC0C\r
-#define DDRSS_PHY_854_DATA 0x20000140\r
-#define DDRSS_PHY_855_DATA 0x07FF0200\r
-#define DDRSS_PHY_856_DATA 0x0000DD01\r
-#define DDRSS_PHY_857_DATA 0x10100303\r
-#define DDRSS_PHY_858_DATA 0x10101010\r
-#define DDRSS_PHY_859_DATA 0x10101010\r
-#define DDRSS_PHY_860_DATA 0x00041010\r
-#define DDRSS_PHY_861_DATA 0x00100010\r
-#define DDRSS_PHY_862_DATA 0x00100010\r
-#define DDRSS_PHY_863_DATA 0x00100010\r
-#define DDRSS_PHY_864_DATA 0x00100010\r
-#define DDRSS_PHY_865_DATA 0x00050010\r
-#define DDRSS_PHY_866_DATA 0x51517041\r
-#define DDRSS_PHY_867_DATA 0x31C06000\r
-#define DDRSS_PHY_868_DATA 0x07AB0340\r
-#define DDRSS_PHY_869_DATA 0x00C0C001\r
-#define DDRSS_PHY_870_DATA 0x0D0C0001\r
-#define DDRSS_PHY_871_DATA 0x10001000\r
-#define DDRSS_PHY_872_DATA 0x0C063E42\r
-#define DDRSS_PHY_873_DATA 0x0F0C3201\r
-#define DDRSS_PHY_874_DATA 0x01000140\r
-#define DDRSS_PHY_875_DATA 0x0C000420\r
-#define DDRSS_PHY_876_DATA 0x000002DD\r
-#define DDRSS_PHY_877_DATA 0x0A0000D0\r
-#define DDRSS_PHY_878_DATA 0x00030200\r
-#define DDRSS_PHY_879_DATA 0x02800000\r
-#define DDRSS_PHY_880_DATA 0x80800000\r
-#define DDRSS_PHY_881_DATA 0x000D2010\r
-#define DDRSS_PHY_882_DATA 0x76543210\r
-#define DDRSS_PHY_883_DATA 0x00000008\r
-#define DDRSS_PHY_884_DATA 0x02800280\r
-#define DDRSS_PHY_885_DATA 0x02800280\r
-#define DDRSS_PHY_886_DATA 0x02800280\r
-#define DDRSS_PHY_887_DATA 0x02800280\r
-#define DDRSS_PHY_888_DATA 0x00000280\r
-#define DDRSS_PHY_889_DATA 0x0000A000\r
-#define DDRSS_PHY_890_DATA 0x00A000A0\r
-#define DDRSS_PHY_891_DATA 0x00A000A0\r
-#define DDRSS_PHY_892_DATA 0x00A000A0\r
-#define DDRSS_PHY_893_DATA 0x00A000A0\r
-#define DDRSS_PHY_894_DATA 0x00A000A0\r
-#define DDRSS_PHY_895_DATA 0x00A000A0\r
-#define DDRSS_PHY_896_DATA 0x00A000A0\r
-#define DDRSS_PHY_897_DATA 0x00A000A0\r
-#define DDRSS_PHY_898_DATA 0x006D00A0\r
-#define DDRSS_PHY_899_DATA 0x01A00005\r
-#define DDRSS_PHY_900_DATA 0x00000000\r
-#define DDRSS_PHY_901_DATA 0x00000000\r
-#define DDRSS_PHY_902_DATA 0x00080200\r
-#define DDRSS_PHY_903_DATA 0x00000000\r
-#define DDRSS_PHY_904_DATA 0x20202020\r
-#define DDRSS_PHY_905_DATA 0x20202020\r
-#define DDRSS_PHY_906_DATA 0xF0F02020\r
-#define DDRSS_PHY_907_DATA 0x00000000\r
-#define DDRSS_PHY_908_DATA 0x00000000\r
-#define DDRSS_PHY_909_DATA 0x00000000\r
-#define DDRSS_PHY_910_DATA 0x00000000\r
-#define DDRSS_PHY_911_DATA 0x00000000\r
-#define DDRSS_PHY_912_DATA 0x00000000\r
-#define DDRSS_PHY_913_DATA 0x00000000\r
-#define DDRSS_PHY_914_DATA 0x00000000\r
-#define DDRSS_PHY_915_DATA 0x00000000\r
-#define DDRSS_PHY_916_DATA 0x00000000\r
-#define DDRSS_PHY_917_DATA 0x00000000\r
-#define DDRSS_PHY_918_DATA 0x00000000\r
-#define DDRSS_PHY_919_DATA 0x00000000\r
-#define DDRSS_PHY_920_DATA 0x00000000\r
-#define DDRSS_PHY_921_DATA 0x00000000\r
-#define DDRSS_PHY_922_DATA 0x00000000\r
-#define DDRSS_PHY_923_DATA 0x00000000\r
-#define DDRSS_PHY_924_DATA 0x00000000\r
-#define DDRSS_PHY_925_DATA 0x00000000\r
-#define DDRSS_PHY_926_DATA 0x00000000\r
-#define DDRSS_PHY_927_DATA 0x00000000\r
-#define DDRSS_PHY_928_DATA 0x00000000\r
-#define DDRSS_PHY_929_DATA 0x00000000\r
-#define DDRSS_PHY_930_DATA 0x00000000\r
-#define DDRSS_PHY_931_DATA 0x00000000\r
-#define DDRSS_PHY_932_DATA 0x00000000\r
-#define DDRSS_PHY_933_DATA 0x00000000\r
-#define DDRSS_PHY_934_DATA 0x00000000\r
-#define DDRSS_PHY_935_DATA 0x00000000\r
-#define DDRSS_PHY_936_DATA 0x00000000\r
-#define DDRSS_PHY_937_DATA 0x00000000\r
-#define DDRSS_PHY_938_DATA 0x00000000\r
-#define DDRSS_PHY_939_DATA 0x00000000\r
-#define DDRSS_PHY_940_DATA 0x00000000\r
-#define DDRSS_PHY_941_DATA 0x00000000\r
-#define DDRSS_PHY_942_DATA 0x00000000\r
-#define DDRSS_PHY_943_DATA 0x00000000\r
-#define DDRSS_PHY_944_DATA 0x00000000\r
-#define DDRSS_PHY_945_DATA 0x00000000\r
-#define DDRSS_PHY_946_DATA 0x00000000\r
-#define DDRSS_PHY_947_DATA 0x00000000\r
-#define DDRSS_PHY_948_DATA 0x00000000\r
-#define DDRSS_PHY_949_DATA 0x00000000\r
-#define DDRSS_PHY_950_DATA 0x00000000\r
-#define DDRSS_PHY_951_DATA 0x00000000\r
-#define DDRSS_PHY_952_DATA 0x00000000\r
-#define DDRSS_PHY_953_DATA 0x00000000\r
-#define DDRSS_PHY_954_DATA 0x00000000\r
-#define DDRSS_PHY_955_DATA 0x00000000\r
-#define DDRSS_PHY_956_DATA 0x00000000\r
-#define DDRSS_PHY_957_DATA 0x00000000\r
-#define DDRSS_PHY_958_DATA 0x00000000\r
-#define DDRSS_PHY_959_DATA 0x00000000\r
-#define DDRSS_PHY_960_DATA 0x00000000\r
-#define DDRSS_PHY_961_DATA 0x00000000\r
-#define DDRSS_PHY_962_DATA 0x00000000\r
-#define DDRSS_PHY_963_DATA 0x00000000\r
-#define DDRSS_PHY_964_DATA 0x00000000\r
-#define DDRSS_PHY_965_DATA 0x00000000\r
-#define DDRSS_PHY_966_DATA 0x00000000\r
-#define DDRSS_PHY_967_DATA 0x00000000\r
-#define DDRSS_PHY_968_DATA 0x00000000\r
-#define DDRSS_PHY_969_DATA 0x00000000\r
-#define DDRSS_PHY_970_DATA 0x00000000\r
-#define DDRSS_PHY_971_DATA 0x00000000\r
-#define DDRSS_PHY_972_DATA 0x00000000\r
-#define DDRSS_PHY_973_DATA 0x00000000\r
-#define DDRSS_PHY_974_DATA 0x00000000\r
-#define DDRSS_PHY_975_DATA 0x00000000\r
-#define DDRSS_PHY_976_DATA 0x00000000\r
-#define DDRSS_PHY_977_DATA 0x00000000\r
-#define DDRSS_PHY_978_DATA 0x00000000\r
-#define DDRSS_PHY_979_DATA 0x00000000\r
-#define DDRSS_PHY_980_DATA 0x00000000\r
-#define DDRSS_PHY_981_DATA 0x00000000\r
-#define DDRSS_PHY_982_DATA 0x00000000\r
-#define DDRSS_PHY_983_DATA 0x00000000\r
-#define DDRSS_PHY_984_DATA 0x00000000\r
-#define DDRSS_PHY_985_DATA 0x00000000\r
-#define DDRSS_PHY_986_DATA 0x00000000\r
-#define DDRSS_PHY_987_DATA 0x00000000\r
-#define DDRSS_PHY_988_DATA 0x00000000\r
-#define DDRSS_PHY_989_DATA 0x00000000\r
-#define DDRSS_PHY_990_DATA 0x00000000\r
-#define DDRSS_PHY_991_DATA 0x00000000\r
-#define DDRSS_PHY_992_DATA 0x00000000\r
-#define DDRSS_PHY_993_DATA 0x00000000\r
-#define DDRSS_PHY_994_DATA 0x00000000\r
-#define DDRSS_PHY_995_DATA 0x00000000\r
-#define DDRSS_PHY_996_DATA 0x00000000\r
-#define DDRSS_PHY_997_DATA 0x00000000\r
-#define DDRSS_PHY_998_DATA 0x00000000\r
-#define DDRSS_PHY_999_DATA 0x00000000\r
-#define DDRSS_PHY_1000_DATA 0x00000000\r
-#define DDRSS_PHY_1001_DATA 0x00000000\r
-#define DDRSS_PHY_1002_DATA 0x00000000\r
-#define DDRSS_PHY_1003_DATA 0x00000000\r
-#define DDRSS_PHY_1004_DATA 0x00000000\r
-#define DDRSS_PHY_1005_DATA 0x00000000\r
-#define DDRSS_PHY_1006_DATA 0x00000000\r
-#define DDRSS_PHY_1007_DATA 0x00000000\r
-#define DDRSS_PHY_1008_DATA 0x00000000\r
-#define DDRSS_PHY_1009_DATA 0x00000000\r
-#define DDRSS_PHY_1010_DATA 0x00000000\r
-#define DDRSS_PHY_1011_DATA 0x00000000\r
-#define DDRSS_PHY_1012_DATA 0x00000000\r
-#define DDRSS_PHY_1013_DATA 0x00000000\r
-#define DDRSS_PHY_1014_DATA 0x00000000\r
-#define DDRSS_PHY_1015_DATA 0x00000000\r
-#define DDRSS_PHY_1016_DATA 0x00000000\r
-#define DDRSS_PHY_1017_DATA 0x00000000\r
-#define DDRSS_PHY_1018_DATA 0x00000000\r
-#define DDRSS_PHY_1019_DATA 0x00000000\r
-#define DDRSS_PHY_1020_DATA 0x00000000\r
-#define DDRSS_PHY_1021_DATA 0x00000000\r
-#define DDRSS_PHY_1022_DATA 0x00000000\r
-#define DDRSS_PHY_1023_DATA 0x00000000\r
-#define DDRSS_PHY_1024_DATA 0x00000000\r
-#define DDRSS_PHY_1025_DATA 0x00000000\r
-#define DDRSS_PHY_1026_DATA 0x00000000\r
-#define DDRSS_PHY_1027_DATA 0x00000000\r
-#define DDRSS_PHY_1028_DATA 0x00000000\r
-#define DDRSS_PHY_1029_DATA 0x00000100\r
-#define DDRSS_PHY_1030_DATA 0x00000200\r
-#define DDRSS_PHY_1031_DATA 0x00000000\r
-#define DDRSS_PHY_1032_DATA 0x00000000\r
-#define DDRSS_PHY_1033_DATA 0x00000000\r
-#define DDRSS_PHY_1034_DATA 0x00000000\r
-#define DDRSS_PHY_1035_DATA 0x00400000\r
-#define DDRSS_PHY_1036_DATA 0x00000080\r
-#define DDRSS_PHY_1037_DATA 0x00DCBA98\r
-#define DDRSS_PHY_1038_DATA 0x03000000\r
-#define DDRSS_PHY_1039_DATA 0x00200000\r
-#define DDRSS_PHY_1040_DATA 0x00000000\r
-#define DDRSS_PHY_1041_DATA 0x00000000\r
-#define DDRSS_PHY_1042_DATA 0x00000000\r
-#define DDRSS_PHY_1043_DATA 0x00000000\r
-#define DDRSS_PHY_1044_DATA 0x00000000\r
-#define DDRSS_PHY_1045_DATA 0x0000002A\r
-#define DDRSS_PHY_1046_DATA 0x00000015\r
-#define DDRSS_PHY_1047_DATA 0x00000015\r
-#define DDRSS_PHY_1048_DATA 0x0000002A\r
-#define DDRSS_PHY_1049_DATA 0x00000033\r
-#define DDRSS_PHY_1050_DATA 0x0000000C\r
-#define DDRSS_PHY_1051_DATA 0x0000000C\r
-#define DDRSS_PHY_1052_DATA 0x00000033\r
-#define DDRSS_PHY_1053_DATA 0x00543210\r
-#define DDRSS_PHY_1054_DATA 0x003F0000\r
-#define DDRSS_PHY_1055_DATA 0x000F013F\r
-#define DDRSS_PHY_1056_DATA 0x20202003\r
-#define DDRSS_PHY_1057_DATA 0x00202020\r
-#define DDRSS_PHY_1058_DATA 0x20008008\r
-#define DDRSS_PHY_1059_DATA 0x00000810\r
-#define DDRSS_PHY_1060_DATA 0x00000F00\r
-#define DDRSS_PHY_1061_DATA 0x00000000\r
-#define DDRSS_PHY_1062_DATA 0x00000000\r
-#define DDRSS_PHY_1063_DATA 0x00000000\r
-#define DDRSS_PHY_1064_DATA 0x000505FF\r
-#define DDRSS_PHY_1065_DATA 0x00030000\r
-#define DDRSS_PHY_1066_DATA 0x00000300\r
-#define DDRSS_PHY_1067_DATA 0x00000300\r
-#define DDRSS_PHY_1068_DATA 0x00000300\r
-#define DDRSS_PHY_1069_DATA 0x00000300\r
-#define DDRSS_PHY_1070_DATA 0x00000300\r
-#define DDRSS_PHY_1071_DATA 0x42080010\r
-#define DDRSS_PHY_1072_DATA 0x0000803E\r
-#define DDRSS_PHY_1073_DATA 0x00000001\r
-#define DDRSS_PHY_1074_DATA 0x01000102\r
-#define DDRSS_PHY_1075_DATA 0x00008000\r
-#define DDRSS_PHY_1076_DATA 0x00000000\r
-#define DDRSS_PHY_1077_DATA 0x00000000\r
-#define DDRSS_PHY_1078_DATA 0x00000000\r
-#define DDRSS_PHY_1079_DATA 0x00000000\r
-#define DDRSS_PHY_1080_DATA 0x00000000\r
-#define DDRSS_PHY_1081_DATA 0x00000000\r
-#define DDRSS_PHY_1082_DATA 0x00000000\r
-#define DDRSS_PHY_1083_DATA 0x00000000\r
-#define DDRSS_PHY_1084_DATA 0x00000000\r
-#define DDRSS_PHY_1085_DATA 0x00000000\r
-#define DDRSS_PHY_1086_DATA 0x00000000\r
-#define DDRSS_PHY_1087_DATA 0x00000000\r
-#define DDRSS_PHY_1088_DATA 0x00000000\r
-#define DDRSS_PHY_1089_DATA 0x00000000\r
-#define DDRSS_PHY_1090_DATA 0x00000000\r
-#define DDRSS_PHY_1091_DATA 0x00000000\r
-#define DDRSS_PHY_1092_DATA 0x00000000\r
-#define DDRSS_PHY_1093_DATA 0x00000000\r
-#define DDRSS_PHY_1094_DATA 0x00000000\r
-#define DDRSS_PHY_1095_DATA 0x00000000\r
-#define DDRSS_PHY_1096_DATA 0x00000000\r
-#define DDRSS_PHY_1097_DATA 0x00000000\r
-#define DDRSS_PHY_1098_DATA 0x00000000\r
-#define DDRSS_PHY_1099_DATA 0x00000000\r
-#define DDRSS_PHY_1100_DATA 0x00000000\r
-#define DDRSS_PHY_1101_DATA 0x00000000\r
-#define DDRSS_PHY_1102_DATA 0x00000000\r
-#define DDRSS_PHY_1103_DATA 0x00000000\r
-#define DDRSS_PHY_1104_DATA 0x00000000\r
-#define DDRSS_PHY_1105_DATA 0x00000000\r
-#define DDRSS_PHY_1106_DATA 0x00000000\r
-#define DDRSS_PHY_1107_DATA 0x00000000\r
-#define DDRSS_PHY_1108_DATA 0x00000000\r
-#define DDRSS_PHY_1109_DATA 0x00000000\r
-#define DDRSS_PHY_1110_DATA 0x00000000\r
-#define DDRSS_PHY_1111_DATA 0x00000000\r
-#define DDRSS_PHY_1112_DATA 0x00000000\r
-#define DDRSS_PHY_1113_DATA 0x00000000\r
-#define DDRSS_PHY_1114_DATA 0x00000000\r
-#define DDRSS_PHY_1115_DATA 0x00000000\r
-#define DDRSS_PHY_1116_DATA 0x00000000\r
-#define DDRSS_PHY_1117_DATA 0x00000000\r
-#define DDRSS_PHY_1118_DATA 0x00000000\r
-#define DDRSS_PHY_1119_DATA 0x00000000\r
-#define DDRSS_PHY_1120_DATA 0x00000000\r
-#define DDRSS_PHY_1121_DATA 0x00000000\r
-#define DDRSS_PHY_1122_DATA 0x00000000\r
-#define DDRSS_PHY_1123_DATA 0x00000000\r
-#define DDRSS_PHY_1124_DATA 0x00000000\r
-#define DDRSS_PHY_1125_DATA 0x00000000\r
-#define DDRSS_PHY_1126_DATA 0x00000000\r
-#define DDRSS_PHY_1127_DATA 0x00000000\r
-#define DDRSS_PHY_1128_DATA 0x00000000\r
-#define DDRSS_PHY_1129_DATA 0x00000000\r
-#define DDRSS_PHY_1130_DATA 0x00000000\r
-#define DDRSS_PHY_1131_DATA 0x00000000\r
-#define DDRSS_PHY_1132_DATA 0x00000000\r
-#define DDRSS_PHY_1133_DATA 0x00000000\r
-#define DDRSS_PHY_1134_DATA 0x00000000\r
-#define DDRSS_PHY_1135_DATA 0x00000000\r
-#define DDRSS_PHY_1136_DATA 0x00000000\r
-#define DDRSS_PHY_1137_DATA 0x00000000\r
-#define DDRSS_PHY_1138_DATA 0x00000000\r
-#define DDRSS_PHY_1139_DATA 0x00000000\r
-#define DDRSS_PHY_1140_DATA 0x00000000\r
-#define DDRSS_PHY_1141_DATA 0x00000000\r
-#define DDRSS_PHY_1142_DATA 0x00000000\r
-#define DDRSS_PHY_1143_DATA 0x00000000\r
-#define DDRSS_PHY_1144_DATA 0x00000000\r
-#define DDRSS_PHY_1145_DATA 0x00000000\r
-#define DDRSS_PHY_1146_DATA 0x00000000\r
-#define DDRSS_PHY_1147_DATA 0x00000000\r
-#define DDRSS_PHY_1148_DATA 0x00000000\r
-#define DDRSS_PHY_1149_DATA 0x00000000\r
-#define DDRSS_PHY_1150_DATA 0x00000000\r
-#define DDRSS_PHY_1151_DATA 0x00000000\r
-#define DDRSS_PHY_1152_DATA 0x00000000\r
-#define DDRSS_PHY_1153_DATA 0x00000000\r
-#define DDRSS_PHY_1154_DATA 0x00000000\r
-#define DDRSS_PHY_1155_DATA 0x00000000\r
-#define DDRSS_PHY_1156_DATA 0x00000000\r
-#define DDRSS_PHY_1157_DATA 0x00000000\r
-#define DDRSS_PHY_1158_DATA 0x00000000\r
-#define DDRSS_PHY_1159_DATA 0x00000000\r
-#define DDRSS_PHY_1160_DATA 0x00000000\r
-#define DDRSS_PHY_1161_DATA 0x00000000\r
-#define DDRSS_PHY_1162_DATA 0x00000000\r
-#define DDRSS_PHY_1163_DATA 0x00000000\r
-#define DDRSS_PHY_1164_DATA 0x00000000\r
-#define DDRSS_PHY_1165_DATA 0x00000000\r
-#define DDRSS_PHY_1166_DATA 0x00000000\r
-#define DDRSS_PHY_1167_DATA 0x00000000\r
-#define DDRSS_PHY_1168_DATA 0x00000000\r
-#define DDRSS_PHY_1169_DATA 0x00000000\r
-#define DDRSS_PHY_1170_DATA 0x00000000\r
-#define DDRSS_PHY_1171_DATA 0x00000000\r
-#define DDRSS_PHY_1172_DATA 0x00000000\r
-#define DDRSS_PHY_1173_DATA 0x00000000\r
-#define DDRSS_PHY_1174_DATA 0x00000000\r
-#define DDRSS_PHY_1175_DATA 0x00000000\r
-#define DDRSS_PHY_1176_DATA 0x00000000\r
-#define DDRSS_PHY_1177_DATA 0x00000000\r
-#define DDRSS_PHY_1178_DATA 0x00000000\r
-#define DDRSS_PHY_1179_DATA 0x00000000\r
-#define DDRSS_PHY_1180_DATA 0x00000000\r
-#define DDRSS_PHY_1181_DATA 0x00000000\r
-#define DDRSS_PHY_1182_DATA 0x00000000\r
-#define DDRSS_PHY_1183_DATA 0x00000000\r
-#define DDRSS_PHY_1184_DATA 0x00000000\r
-#define DDRSS_PHY_1185_DATA 0x00000000\r
-#define DDRSS_PHY_1186_DATA 0x00000000\r
-#define DDRSS_PHY_1187_DATA 0x00000000\r
-#define DDRSS_PHY_1188_DATA 0x00000000\r
-#define DDRSS_PHY_1189_DATA 0x00000000\r
-#define DDRSS_PHY_1190_DATA 0x00000000\r
-#define DDRSS_PHY_1191_DATA 0x00000000\r
-#define DDRSS_PHY_1192_DATA 0x00000000\r
-#define DDRSS_PHY_1193_DATA 0x00000000\r
-#define DDRSS_PHY_1194_DATA 0x00000000\r
-#define DDRSS_PHY_1195_DATA 0x00000000\r
-#define DDRSS_PHY_1196_DATA 0x00000000\r
-#define DDRSS_PHY_1197_DATA 0x00000000\r
-#define DDRSS_PHY_1198_DATA 0x00000000\r
-#define DDRSS_PHY_1199_DATA 0x00000000\r
-#define DDRSS_PHY_1200_DATA 0x00000000\r
-#define DDRSS_PHY_1201_DATA 0x00000000\r
-#define DDRSS_PHY_1202_DATA 0x00000000\r
-#define DDRSS_PHY_1203_DATA 0x00000000\r
-#define DDRSS_PHY_1204_DATA 0x00000000\r
-#define DDRSS_PHY_1205_DATA 0x00000000\r
-#define DDRSS_PHY_1206_DATA 0x00000000\r
-#define DDRSS_PHY_1207_DATA 0x00000000\r
-#define DDRSS_PHY_1208_DATA 0x00000000\r
-#define DDRSS_PHY_1209_DATA 0x00000000\r
-#define DDRSS_PHY_1210_DATA 0x00000000\r
-#define DDRSS_PHY_1211_DATA 0x00000000\r
-#define DDRSS_PHY_1212_DATA 0x00000000\r
-#define DDRSS_PHY_1213_DATA 0x00000000\r
-#define DDRSS_PHY_1214_DATA 0x00000000\r
-#define DDRSS_PHY_1215_DATA 0x00000000\r
-#define DDRSS_PHY_1216_DATA 0x00000000\r
-#define DDRSS_PHY_1217_DATA 0x00000000\r
-#define DDRSS_PHY_1218_DATA 0x00000000\r
-#define DDRSS_PHY_1219_DATA 0x00000000\r
-#define DDRSS_PHY_1220_DATA 0x00000000\r
-#define DDRSS_PHY_1221_DATA 0x00000000\r
-#define DDRSS_PHY_1222_DATA 0x00000000\r
-#define DDRSS_PHY_1223_DATA 0x00000000\r
-#define DDRSS_PHY_1224_DATA 0x00000000\r
-#define DDRSS_PHY_1225_DATA 0x00000000\r
-#define DDRSS_PHY_1226_DATA 0x00000000\r
-#define DDRSS_PHY_1227_DATA 0x00000000\r
-#define DDRSS_PHY_1228_DATA 0x00000000\r
-#define DDRSS_PHY_1229_DATA 0x00000000\r
-#define DDRSS_PHY_1230_DATA 0x00000000\r
-#define DDRSS_PHY_1231_DATA 0x00000000\r
-#define DDRSS_PHY_1232_DATA 0x00000000\r
-#define DDRSS_PHY_1233_DATA 0x00000000\r
-#define DDRSS_PHY_1234_DATA 0x00000000\r
-#define DDRSS_PHY_1235_DATA 0x00000000\r
-#define DDRSS_PHY_1236_DATA 0x00000000\r
-#define DDRSS_PHY_1237_DATA 0x00000000\r
-#define DDRSS_PHY_1238_DATA 0x00000000\r
-#define DDRSS_PHY_1239_DATA 0x00000000\r
-#define DDRSS_PHY_1240_DATA 0x00000000\r
-#define DDRSS_PHY_1241_DATA 0x00000000\r
-#define DDRSS_PHY_1242_DATA 0x00000000\r
-#define DDRSS_PHY_1243_DATA 0x00000000\r
-#define DDRSS_PHY_1244_DATA 0x00000000\r
-#define DDRSS_PHY_1245_DATA 0x00000000\r
-#define DDRSS_PHY_1246_DATA 0x00000000\r
-#define DDRSS_PHY_1247_DATA 0x00000000\r
-#define DDRSS_PHY_1248_DATA 0x00000000\r
-#define DDRSS_PHY_1249_DATA 0x00000000\r
-#define DDRSS_PHY_1250_DATA 0x00000000\r
-#define DDRSS_PHY_1251_DATA 0x00000000\r
-#define DDRSS_PHY_1252_DATA 0x00000000\r
-#define DDRSS_PHY_1253_DATA 0x00000000\r
-#define DDRSS_PHY_1254_DATA 0x00000000\r
-#define DDRSS_PHY_1255_DATA 0x00000000\r
-#define DDRSS_PHY_1256_DATA 0x00000000\r
-#define DDRSS_PHY_1257_DATA 0x00000000\r
-#define DDRSS_PHY_1258_DATA 0x00000000\r
-#define DDRSS_PHY_1259_DATA 0x00000000\r
-#define DDRSS_PHY_1260_DATA 0x00000000\r
-#define DDRSS_PHY_1261_DATA 0x00000000\r
-#define DDRSS_PHY_1262_DATA 0x00000000\r
-#define DDRSS_PHY_1263_DATA 0x00000000\r
-#define DDRSS_PHY_1264_DATA 0x00000000\r
-#define DDRSS_PHY_1265_DATA 0x00000000\r
-#define DDRSS_PHY_1266_DATA 0x00000000\r
-#define DDRSS_PHY_1267_DATA 0x00000000\r
-#define DDRSS_PHY_1268_DATA 0x00000000\r
-#define DDRSS_PHY_1269_DATA 0x00000000\r
-#define DDRSS_PHY_1270_DATA 0x00000000\r
-#define DDRSS_PHY_1271_DATA 0x00000000\r
-#define DDRSS_PHY_1272_DATA 0x00000000\r
-#define DDRSS_PHY_1273_DATA 0x00000000\r
-#define DDRSS_PHY_1274_DATA 0x00000000\r
-#define DDRSS_PHY_1275_DATA 0x00000000\r
-#define DDRSS_PHY_1276_DATA 0x00000000\r
-#define DDRSS_PHY_1277_DATA 0x00000000\r
-#define DDRSS_PHY_1278_DATA 0x00000000\r
-#define DDRSS_PHY_1279_DATA 0x00000000\r
-#define DDRSS_PHY_1280_DATA 0x00000000\r
-#define DDRSS_PHY_1281_DATA 0x00010100\r
-#define DDRSS_PHY_1282_DATA 0x00000000\r
-#define DDRSS_PHY_1283_DATA 0x00000000\r
-#define DDRSS_PHY_1284_DATA 0x00050000\r
-#define DDRSS_PHY_1285_DATA 0x04000000\r
-#define DDRSS_PHY_1286_DATA 0x00000055\r
-#define DDRSS_PHY_1287_DATA 0x00000000\r
-#define DDRSS_PHY_1288_DATA 0x00000000\r
-#define DDRSS_PHY_1289_DATA 0x00000000\r
-#define DDRSS_PHY_1290_DATA 0x00000000\r
-#define DDRSS_PHY_1291_DATA 0x00002001\r
-#define DDRSS_PHY_1292_DATA 0x0000400F\r
-#define DDRSS_PHY_1293_DATA 0x50020028\r
-#define DDRSS_PHY_1294_DATA 0x01010000\r
-#define DDRSS_PHY_1295_DATA 0x80080001\r
-#define DDRSS_PHY_1296_DATA 0x10200000\r
-#define DDRSS_PHY_1297_DATA 0x00000008\r
-#define DDRSS_PHY_1298_DATA 0x00000000\r
-#define DDRSS_PHY_1299_DATA 0x01090E00\r
-#define DDRSS_PHY_1300_DATA 0x00040101\r
-#define DDRSS_PHY_1301_DATA 0x0000010F\r
-#define DDRSS_PHY_1302_DATA 0x00000000\r
-#define DDRSS_PHY_1303_DATA 0x0000FFFF\r
-#define DDRSS_PHY_1304_DATA 0x00000000\r
-#define DDRSS_PHY_1305_DATA 0x01010000\r
-#define DDRSS_PHY_1306_DATA 0x01080402\r
-#define DDRSS_PHY_1307_DATA 0x01200F02\r
-#define DDRSS_PHY_1308_DATA 0x00194280\r
-#define DDRSS_PHY_1309_DATA 0x00000004\r
-#define DDRSS_PHY_1310_DATA 0x00050000\r
-#define DDRSS_PHY_1311_DATA 0x00000000\r
-#define DDRSS_PHY_1312_DATA 0x00000000\r
-#define DDRSS_PHY_1313_DATA 0x00000000\r
-#define DDRSS_PHY_1314_DATA 0x00000000\r
-#define DDRSS_PHY_1315_DATA 0x00000000\r
-#define DDRSS_PHY_1316_DATA 0x00000000\r
-#define DDRSS_PHY_1317_DATA 0x01000000\r
-#define DDRSS_PHY_1318_DATA 0x00000705\r
-#define DDRSS_PHY_1319_DATA 0x00000054\r
-#define DDRSS_PHY_1320_DATA 0x00030820\r
-#define DDRSS_PHY_1321_DATA 0x00010820\r
-#define DDRSS_PHY_1322_DATA 0x00010820\r
-#define DDRSS_PHY_1323_DATA 0x00010820\r
-#define DDRSS_PHY_1324_DATA 0x00010820\r
-#define DDRSS_PHY_1325_DATA 0x00010820\r
-#define DDRSS_PHY_1326_DATA 0x00010820\r
-#define DDRSS_PHY_1327_DATA 0x00010820\r
-#define DDRSS_PHY_1328_DATA 0x00010820\r
-#define DDRSS_PHY_1329_DATA 0x00000000\r
-#define DDRSS_PHY_1330_DATA 0x00000074\r
-#define DDRSS_PHY_1331_DATA 0x00000400\r
-#define DDRSS_PHY_1332_DATA 0x00000108\r
-#define DDRSS_PHY_1333_DATA 0x00000000\r
-#define DDRSS_PHY_1334_DATA 0x00000000\r
-#define DDRSS_PHY_1335_DATA 0x00000000\r
-#define DDRSS_PHY_1336_DATA 0x00000000\r
-#define DDRSS_PHY_1337_DATA 0x00000000\r
-#define DDRSS_PHY_1338_DATA 0x03000000\r
-#define DDRSS_PHY_1339_DATA 0x00000000\r
-#define DDRSS_PHY_1340_DATA 0x00000000\r
-#define DDRSS_PHY_1341_DATA 0x00000000\r
-#define DDRSS_PHY_1342_DATA 0x04102006\r
-#define DDRSS_PHY_1343_DATA 0x00041020\r
-#define DDRSS_PHY_1344_DATA 0x01C98C98\r
-#define DDRSS_PHY_1345_DATA 0x3F400000\r
-#define DDRSS_PHY_1346_DATA 0x3F3F1F3F\r
-#define DDRSS_PHY_1347_DATA 0x0000001F\r
-#define DDRSS_PHY_1348_DATA 0x00000000\r
-#define DDRSS_PHY_1349_DATA 0x00000000\r
-#define DDRSS_PHY_1350_DATA 0x00000000\r
-#define DDRSS_PHY_1351_DATA 0x00010000\r
-#define DDRSS_PHY_1352_DATA 0x00000000\r
-#define DDRSS_PHY_1353_DATA 0x00000000\r
-#define DDRSS_PHY_1354_DATA 0x00000000\r
-#define DDRSS_PHY_1355_DATA 0x00000000\r
-#define DDRSS_PHY_1356_DATA 0x76543210\r
-#define DDRSS_PHY_1357_DATA 0x00010198\r
-#define DDRSS_PHY_1358_DATA 0x00000000\r
-#define DDRSS_PHY_1359_DATA 0x00000000\r
-#define DDRSS_PHY_1360_DATA 0x00000000\r
-#define DDRSS_PHY_1361_DATA 0x00040700\r
-#define DDRSS_PHY_1362_DATA 0x00000000\r
-#define DDRSS_PHY_1363_DATA 0x00000000\r
-#define DDRSS_PHY_1364_DATA 0x00000000\r
-#define DDRSS_PHY_1365_DATA 0x00000000\r
-#define DDRSS_PHY_1366_DATA 0x00000000\r
-#define DDRSS_PHY_1367_DATA 0x00000002\r
-#define DDRSS_PHY_1368_DATA 0x00000000\r
-#define DDRSS_PHY_1369_DATA 0x00000000\r
-#define DDRSS_PHY_1370_DATA 0x00000000\r
-#define DDRSS_PHY_1371_DATA 0x00000000\r
-#define DDRSS_PHY_1372_DATA 0x00000000\r
-#define DDRSS_PHY_1373_DATA 0x00000000\r
-#define DDRSS_PHY_1374_DATA 0x00080000\r
-#define DDRSS_PHY_1375_DATA 0x000007FF\r
-#define DDRSS_PHY_1376_DATA 0x00000000\r
-#define DDRSS_PHY_1377_DATA 0x00000000\r
-#define DDRSS_PHY_1378_DATA 0x00000000\r
-#define DDRSS_PHY_1379_DATA 0x00000000\r
-#define DDRSS_PHY_1380_DATA 0x00000000\r
-#define DDRSS_PHY_1381_DATA 0x00000000\r
-#define DDRSS_PHY_1382_DATA 0x000FFFFF\r
-#define DDRSS_PHY_1383_DATA 0x000FFFFF\r
-#define DDRSS_PHY_1384_DATA 0x0000FFFF\r
-#define DDRSS_PHY_1385_DATA 0xFFFFFFF0\r
-#define DDRSS_PHY_1386_DATA 0x030FFFFF\r
-#define DDRSS_PHY_1387_DATA 0x01FFFFFF\r
-#define DDRSS_PHY_1388_DATA 0x0000FFFF\r
-#define DDRSS_PHY_1389_DATA 0x00000000\r
-#define DDRSS_PHY_1390_DATA 0x00000000\r
-#define DDRSS_PHY_1391_DATA 0x00000000\r
-#define DDRSS_PHY_1392_DATA 0x00000000\r
-#define DDRSS_PHY_1393_DATA 0x0001F7C5\r
-#define DDRSS_PHY_1394_DATA 0x00000005\r
-#define DDRSS_PHY_1395_DATA 0x00000000\r
-#define DDRSS_PHY_1396_DATA 0x00001142\r
-#define DDRSS_PHY_1397_DATA 0x010207AB\r
-#define DDRSS_PHY_1398_DATA 0x01000080\r
-#define DDRSS_PHY_1399_DATA 0x03900390\r
-#define DDRSS_PHY_1400_DATA 0x03900390\r
-#define DDRSS_PHY_1401_DATA 0x00000390\r
-#define DDRSS_PHY_1402_DATA 0x00000390\r
-#define DDRSS_PHY_1403_DATA 0x00000390\r
-#define DDRSS_PHY_1404_DATA 0x00000390\r
-#define DDRSS_PHY_1405_DATA 0x00000005\r
-#define DDRSS_PHY_1406_DATA 0x01813FFF\r
-#define DDRSS_PHY_1407_DATA 0x000000FF\r
-#define DDRSS_PHY_1408_DATA 0x0C000DFF\r
-#define DDRSS_PHY_1409_DATA 0x30000DFF\r
-#define DDRSS_PHY_1410_DATA 0x3F0DFF11\r
-#define DDRSS_PHY_1411_DATA 0x000100F0\r
-#define DDRSS_PHY_1412_DATA 0x780DFFFF\r
-#define DDRSS_PHY_1413_DATA 0x00007E31\r
-#define DDRSS_PHY_1414_DATA 0x000CBF11\r
-#define DDRSS_PHY_1415_DATA 0x01FF0010\r
-#define DDRSS_PHY_1416_DATA 0x000CBF11\r
-#define DDRSS_PHY_1417_DATA 0x01FF0010\r
-#define DDRSS_PHY_1418_DATA 0x3F0DFF11\r
-#define DDRSS_PHY_1419_DATA 0x01FF00F0\r
-#define DDRSS_PHY_1420_DATA 0x3F0DFF11\r
-#define DDRSS_PHY_1421_DATA 0x01FF00F0\r
-#define DDRSS_PHY_1422_DATA 0x20040006\r
+#define TH_FLD_MASK(fld) TH_MACRO_EXP(fld, _MASK)\r
+#define TH_FLD_SHIFT(fld) TH_MACRO_EXP(fld, _SHIFT)\r
+#define TH_FLD_WIDTH(fld) TH_MACRO_EXP(fld, _WIDTH)\r
+#define TH_FLD_WOCLR(fld) TH_MACRO_EXP(fld, _WOCLR)\r
+#define TH_FLD_WOSET(fld) TH_MACRO_EXP(fld, _WOSET)\r
\r
+#define str(s) #s\r
\r
+#define BOARD_DDR_CTL_REG_OFFSET (0)\r
\r
#ifdef __cplusplus\r
}\r
diff --git a/packages/ti/board/src/j721e_evm/include/board_ddrRegInit.h b/packages/ti/board/src/j721e_evm/include/board_ddrRegInit.h
--- /dev/null
@@ -0,0 +1,4424 @@
+/* Copyright (c) 2019, Texas Instruments Incorporated\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the distribution.\r
+ *\r
+ * * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,\r
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR\r
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR\r
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,\r
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\r
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\r
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\r
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,\r
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */\r
+\r
+#define DDRSS_PLL_FHS_CNT 10\r
+#define DDRSS_PLL_FREQUENCY_1 933000000\r
+#define DDRSS_PLL_FREQUENCY_2 933000000\r
+\r
+#define DDRSS_CTL_REG_INIT_COUNT (459U)\r
+#define DDRSS_PHY_INDEP_REG_INIT_COUNT (300U)\r
+#define DDRSS_PHY_REG_INIT_COUNT (1423U)\r
+\r
+\r
+uint32_t DDRSS_ctlReg[] = {\r
+ 0x00000B00U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00002710U,\r
+ 0x000186A0U,\r
+ 0x00000005U,\r
+ 0x00000064U,\r
+ 0x0005B18FU,\r
+ 0x0038EF90U,\r
+ 0x00000005U,\r
+ 0x00000E94U,\r
+ 0x0005B18FU,\r
+ 0x0038EF90U,\r
+ 0x00000005U,\r
+ 0x00000E94U,\r
+ 0x01010000U,\r
+ 0x02011001U,\r
+ 0x02010000U,\r
+ 0x00020100U,\r
+ 0x0000000AU,\r
+ 0x00000019U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x02020200U,\r
+ 0x00004B4BU,\r
+ 0x00100000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x040C0000U,\r
+ 0x10401040U,\r
+ 0x00050804U,\r
+ 0x09040008U,\r
+ 0x12000204U,\r
+ 0x1854007AU,\r
+ 0x12003A26U,\r
+ 0x1854007AU,\r
+ 0x20003A26U,\r
+ 0x000A0A09U,\r
+ 0x040006DBU,\r
+ 0x1B130F04U,\r
+ 0x0E00FFCDU,\r
+ 0x1B130F0EU,\r
+ 0x0E00FFCDU,\r
+ 0x0203040EU,\r
+ 0x26040500U,\r
+ 0x08282628U,\r
+ 0x14000D0AU,\r
+ 0x03010A0AU,\r
+ 0x01010003U,\r
+ 0x044E4E08U,\r
+ 0x042B2B04U,\r
+ 0x00002B2BU,\r
+ 0x00010100U,\r
+ 0x03010000U,\r
+ 0x00000E08U,\r
+ 0x000000BBU,\r
+ 0x0000020BU,\r
+ 0x00001C64U,\r
+ 0x0000020BU,\r
+ 0x00001C64U,\r
+ 0x00000005U,\r
+ 0x00030000U,\r
+ 0x00830010U,\r
+ 0x00830386U,\r
+ 0x00400386U,\r
+ 0x00120103U,\r
+ 0x000E0005U,\r
+ 0x2908000EU,\r
+ 0x05050129U,\r
+ 0x0401030AU,\r
+ 0x041B0E0AU,\r
+ 0x0E0A0401U,\r
+ 0x0001041BU,\r
+ 0x000F000FU,\r
+ 0x02190219U,\r
+ 0x02190219U,\r
+ 0x03050505U,\r
+ 0x03010303U,\r
+ 0x1C0A0E0AU,\r
+ 0x04040E04U,\r
+ 0x1C0A0E0AU,\r
+ 0x04040E04U,\r
+ 0x03010000U,\r
+ 0x00010000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x01000000U,\r
+ 0x80104002U,\r
+ 0x00000000U,\r
+ 0x00040005U,\r
+ 0x00000000U,\r
+ 0x00050000U,\r
+ 0x00000004U,\r
+ 0x00000000U,\r
+ 0x00040005U,\r
+ 0x00000000U,\r
+ 0x00002EC0U,\r
+ 0x00002EC0U,\r
+ 0x00002EC0U,\r
+ 0x00002EC0U,\r
+ 0x00002EC0U,\r
+ 0x00000000U,\r
+ 0x0000051DU,\r
+ 0x00071900U,\r
+ 0x00071900U,\r
+ 0x00071900U,\r
+ 0x00071900U,\r
+ 0x00071900U,\r
+ 0x00000000U,\r
+ 0x0000C6BCU,\r
+ 0x00071900U,\r
+ 0x00071900U,\r
+ 0x00071900U,\r
+ 0x00071900U,\r
+ 0x00071900U,\r
+ 0x00000000U,\r
+ 0x0000C6BCU,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x0A030500U,\r
+ 0x00040A04U,\r
+ 0x0A090000U,\r
+ 0x0A090701U,\r
+ 0x0900000EU,\r
+ 0x0907010AU,\r
+ 0x00000E0AU,\r
+ 0x07010A09U,\r
+ 0x000E0A09U,\r
+ 0x07000401U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x08080000U,\r
+ 0x01000000U,\r
+ 0x800000C0U,\r
+ 0x800000C0U,\r
+ 0x800000C0U,\r
+ 0x00000000U,\r
+ 0x00001500U,\r
+ 0x00000000U,\r
+ 0x00000001U,\r
+ 0x00000002U,\r
+ 0x0000100EU,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x000A0000U,\r
+ 0x000D0005U,\r
+ 0x000D0404U,\r
+ 0x00BB0176U,\r
+ 0x0E0E01D3U,\r
+ 0x017601D3U,\r
+ 0x01D300BBU,\r
+ 0x01D30E0EU,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x36E40084U,\r
+ 0x330036E4U,\r
+ 0x00003333U,\r
+ 0x56000000U,\r
+ 0x27270056U,\r
+ 0x0F0F0000U,\r
+ 0x00000000U,\r
+ 0x00840606U,\r
+ 0x36E436E4U,\r
+ 0x33333300U,\r
+ 0x00000000U,\r
+ 0x00565600U,\r
+ 0x00002727U,\r
+ 0x00000F0FU,\r
+ 0x06060000U,\r
+ 0x00000020U,\r
+ 0x00000000U,\r
+ 0x00000001U,\r
+ 0x00000000U,\r
+ 0x01000000U,\r
+ 0x00000001U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x02000000U,\r
+ 0x01080101U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00001000U,\r
+ 0x006403E8U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x15110000U,\r
+ 0x00040C18U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00030000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x01000200U,\r
+ 0x00320040U,\r
+ 0x00020008U,\r
+ 0x00400100U,\r
+ 0x0038074AU,\r
+ 0x01000200U,\r
+ 0x074A0040U,\r
+ 0x00000038U,\r
+ 0x005E0003U,\r
+ 0x0100005EU,\r
+ 0x00000000U,\r
+ 0x01010000U,\r
+ 0x00000202U,\r
+ 0x00000FFFU,\r
+ 0x1FFF1000U,\r
+ 0x01FF0000U,\r
+ 0x000101FFU,\r
+ 0xFFFF0B00U,\r
+ 0x01010001U,\r
+ 0x01010101U,\r
+ 0x01180101U,\r
+ 0x00030000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00040101U,\r
+ 0x04010100U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x03030300U,\r
+ 0x00000001U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x01000000U,\r
+ 0x00020201U,\r
+ 0x01000101U,\r
+ 0x01010001U,\r
+ 0x00010101U,\r
+ 0x05090903U,\r
+ 0x0E081B1BU,\r
+ 0x0009030EU,\r
+ 0x0A0D030FU,\r
+ 0x0A0D0306U,\r
+ 0x0D090006U,\r
+ 0x0100000DU,\r
+ 0x07030701U,\r
+ 0x00000003U,\r
+ 0x00000000U,\r
+ 0x00010000U,\r
+ 0x00280D00U,\r
+ 0x00000001U,\r
+ 0x00030001U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x01000000U,\r
+ 0x00000001U,\r
+ 0x00010100U,\r
+ 0x03030000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x000556AAU,\r
+ 0x000AAAAAU,\r
+ 0x000AA955U,\r
+ 0x00055555U,\r
+ 0x000B3133U,\r
+ 0x0004CD33U,\r
+ 0x0004CECCU,\r
+ 0x000B32CCU,\r
+ 0x00010300U,\r
+ 0x03000100U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00010000U,\r
+ 0x00000404U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x37371B00U,\r
+ 0x000A0000U,\r
+ 0x00000176U,\r
+ 0x00000200U,\r
+ 0x00000200U,\r
+ 0x00000200U,\r
+ 0x00000200U,\r
+ 0x00000462U,\r
+ 0x00000E9CU,\r
+ 0x00000204U,\r
+ 0x000038C8U,\r
+ 0x00000200U,\r
+ 0x00000200U,\r
+ 0x00000200U,\r
+ 0x00000200U,\r
+ 0x0000AA58U,\r
+ 0x000237D0U,\r
+ 0x00000C12U,\r
+ 0x000038C8U,\r
+ 0x00000200U,\r
+ 0x00000200U,\r
+ 0x00000200U,\r
+ 0x00000200U,\r
+ 0x0000AA58U,\r
+ 0x000237D0U,\r
+ 0x02020C12U,\r
+ 0x03030202U,\r
+ 0x00000022U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00001403U,\r
+ 0x000007D0U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00030000U,\r
+ 0x0006001EU,\r
+ 0x00190031U,\r
+ 0x00190031U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x02000000U,\r
+ 0x01000404U,\r
+ 0x091A091AU,\r
+ 0x00000105U,\r
+ 0x00010101U,\r
+ 0x00010101U,\r
+ 0x00010001U,\r
+ 0x00000101U,\r
+ 0x02000201U,\r
+ 0x02010000U,\r
+ 0x00000200U,\r
+ 0x22060000U,\r
+ 0x00000122U,\r
+ 0xFFFFFFFFU,\r
+ 0xFFFFFFFFU,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+};\r
+\r
+uint32_t DDRSS_phyIndepReg[] = {\r
+ 0x00000B00U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000101U,\r
+ 0x00640000U,\r
+ 0x00000001U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000007U,\r
+ 0x00010002U,\r
+ 0x0800000FU,\r
+ 0x00000103U,\r
+ 0x00000005U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00010100U,\r
+ 0x00280A00U,\r
+ 0x00000000U,\r
+ 0x0F000000U,\r
+ 0x00003200U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x01010102U,\r
+ 0x00000000U,\r
+ 0x000000AAU,\r
+ 0x00000055U,\r
+ 0x000000B5U,\r
+ 0x0000004AU,\r
+ 0x00000056U,\r
+ 0x000000A9U,\r
+ 0x000000A9U,\r
+ 0x000000B5U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x000F0F00U,\r
+ 0x00000019U,\r
+ 0x000007D0U,\r
+ 0x00000300U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x01000000U,\r
+ 0x00010101U,\r
+ 0x00000000U,\r
+ 0x00030000U,\r
+ 0x0F000000U,\r
+ 0x00000017U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x0A0A140AU,\r
+ 0x10020101U,\r
+ 0x00020805U,\r
+ 0x01000404U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000101U,\r
+ 0x0001010FU,\r
+ 0x00340000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x01000000U,\r
+ 0x00080100U,\r
+ 0x02000200U,\r
+ 0x01000100U,\r
+ 0x01000000U,\r
+ 0x02000200U,\r
+ 0x00000200U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000400U,\r
+ 0x02010000U,\r
+ 0x00080003U,\r
+ 0x00080000U,\r
+ 0x00000001U,\r
+ 0x00000000U,\r
+ 0x0000AA00U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00010000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000008U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000002U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x0000000AU,\r
+ 0x00000019U,\r
+ 0x00000100U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x01000000U,\r
+ 0x00010003U,\r
+ 0x02000101U,\r
+ 0x01030001U,\r
+ 0x00010400U,\r
+ 0x06000105U,\r
+ 0x01070001U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00010001U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000401U,\r
+ 0x00000000U,\r
+ 0x00010000U,\r
+ 0x00000000U,\r
+ 0x26260100U,\r
+ 0x00000034U,\r
+ 0x0000005EU,\r
+ 0x0002005EU,\r
+ 0x02000200U,\r
+ 0x40100C04U,\r
+ 0x000E4010U,\r
+ 0x000000BBU,\r
+ 0x0000020BU,\r
+ 0x00001C64U,\r
+ 0x0000020BU,\r
+ 0x04001C64U,\r
+ 0x01010404U,\r
+ 0x00001501U,\r
+ 0x00150015U,\r
+ 0x01000100U,\r
+ 0x00000100U,\r
+ 0x00000000U,\r
+ 0x01010101U,\r
+ 0x00000101U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x12040000U,\r
+ 0x0C0C0212U,\r
+ 0x00040402U,\r
+ 0x000C8034U,\r
+ 0x001F0047U,\r
+ 0x001F0047U,\r
+ 0x01010101U,\r
+ 0x0003000DU,\r
+ 0x000301D3U,\r
+ 0x010001D3U,\r
+ 0x000E000EU,\r
+ 0x01D40100U,\r
+ 0x010001D4U,\r
+ 0x01D401D4U,\r
+ 0x32103200U,\r
+ 0x01013210U,\r
+ 0x0A070601U,\r
+ 0x1C11090DU,\r
+ 0x1C110913U,\r
+ 0x0000C013U,\r
+ 0x00C01000U,\r
+ 0x00C01000U,\r
+ 0x00021000U,\r
+ 0x0021000DU,\r
+ 0x002101D3U,\r
+ 0x001101D3U,\r
+ 0x32000056U,\r
+ 0x00000101U,\r
+ 0x005A0035U,\r
+ 0x01013212U,\r
+ 0x00003500U,\r
+ 0x3212005AU,\r
+ 0x09000101U,\r
+ 0x04010504U,\r
+ 0x0400062BU,\r
+ 0x0A032001U,\r
+ 0x262B0F0AU,\r
+ 0x00002819U,\r
+ 0x5400E638U,\r
+ 0x1B1C2007U,\r
+ 0x262B0F13U,\r
+ 0x00002819U,\r
+ 0x5400E638U,\r
+ 0x1B1C2007U,\r
+ 0x00017613U,\r
+ 0x00000E9CU,\r
+ 0x000038C8U,\r
+ 0x000237D0U,\r
+ 0x000038C8U,\r
+ 0x000237D0U,\r
+ 0x0219000FU,\r
+ 0x03030219U,\r
+ 0x00271003U,\r
+ 0x000186A0U,\r
+ 0x00000005U,\r
+ 0x00000064U,\r
+ 0x0000000FU,\r
+ 0x0005B18FU,\r
+ 0x000186A0U,\r
+ 0x00000005U,\r
+ 0x00000E94U,\r
+ 0x00000219U,\r
+ 0x0005B18FU,\r
+ 0x000186A0U,\r
+ 0x00000005U,\r
+ 0x00000E94U,\r
+ 0x01000219U,\r
+ 0x00320040U,\r
+ 0x00010008U,\r
+ 0x074A0040U,\r
+ 0x00010038U,\r
+ 0x074A0040U,\r
+ 0x00000338U,\r
+ 0x005E005EU,\r
+ 0x00040404U,\r
+ 0x00000055U,\r
+ 0x55003C5AU,\r
+ 0x5A000000U,\r
+ 0x0055003CU,\r
+ 0x3C5A0000U,\r
+ 0x00005500U,\r
+ 0x0C3C5A00U,\r
+ 0x080F0E0DU,\r
+ 0x000B0A09U,\r
+ 0x00030201U,\r
+ 0x01000000U,\r
+ 0x04020201U,\r
+ 0x00080804U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00330084U,\r
+ 0x00160000U,\r
+ 0x563336E4U,\r
+ 0x00160F27U,\r
+ 0x563336E4U,\r
+ 0x00160F27U,\r
+ 0x00330084U,\r
+ 0x00160000U,\r
+ 0x563336E4U,\r
+ 0x00160F27U,\r
+ 0x563336E4U,\r
+ 0x00160F27U,\r
+ 0x00330084U,\r
+ 0x00160000U,\r
+ 0x563336E4U,\r
+ 0x00160F27U,\r
+ 0x563336E4U,\r
+ 0x00160F27U,\r
+ 0x00330084U,\r
+ 0x00160000U,\r
+ 0x563336E4U,\r
+ 0x00160F27U,\r
+ 0x563336E4U,\r
+ 0x00160F27U,\r
+ 0x00000000U,\r
+};\r
+\r
+uint32_t DDRSS_phyReg[] = \r
+{\r
+ 0x000004F0U,\r
+ 0x00000000U,\r
+ 0x00030200U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x01030000U,\r
+ 0x00010000U,\r
+ 0x01030004U,\r
+ 0x01000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x01000001U,\r
+ 0x00000100U,\r
+ 0x000800C0U,\r
+ 0x060100CCU,\r
+ 0x00030066U,\r
+ 0x00000000U,\r
+ 0x00000001U,\r
+ 0x0000AAAAU,\r
+ 0x00005555U,\r
+ 0x0000B5B5U,\r
+ 0x00004A4AU,\r
+ 0x00005656U,\r
+ 0x0000A9A9U,\r
+ 0x0000A9A9U,\r
+ 0x0000B5B5U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x2A000000U,\r
+ 0x00000808U,\r
+ 0x0F000000U,\r
+ 0x00000F0FU,\r
+ 0x10200000U,\r
+ 0x0C002004U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x55555555U,\r
+ 0xAAAAAAAAU,\r
+ 0x55555555U,\r
+ 0xAAAAAAAAU,\r
+ 0x00005555U,\r
+ 0x01000100U,\r
+ 0x00800180U,\r
+ 0x00000001U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000104U,\r
+ 0x00000120U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000001U,\r
+ 0x07FF0000U,\r
+ 0x0080081FU,\r
+ 0x00081020U,\r
+ 0x04010000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000100U,\r
+ 0x01CC0C01U,\r
+ 0x0003CC0CU,\r
+ 0x20000140U,\r
+ 0x07FF0200U,\r
+ 0x0000DD01U,\r
+ 0x10100303U,\r
+ 0x10101010U,\r
+ 0x10101010U,\r
+ 0x00041010U,\r
+ 0x00100010U,\r
+ 0x00100010U,\r
+ 0x00100010U,\r
+ 0x00100010U,\r
+ 0x00050010U,\r
+ 0x51517041U,\r
+ 0x31C06000U,\r
+ 0x07AB0340U,\r
+ 0x00C0C001U,\r
+ 0x0D0C0001U,\r
+ 0x10001000U,\r
+ 0x0C063E42U,\r
+ 0x0F0C3201U,\r
+ 0x01000140U,\r
+ 0x0C000420U,\r
+ 0x000002DDU,\r
+ 0x0A0000D0U,\r
+ 0x00030200U,\r
+ 0x02800000U,\r
+ 0x80800000U,\r
+ 0x000D2010U,\r
+ 0x76543210U,\r
+ 0x00000008U,\r
+ 0x02800280U,\r
+ 0x02800280U,\r
+ 0x02800280U,\r
+ 0x02800280U,\r
+ 0x00000280U,\r
+ 0x0000A000U,\r
+ 0x00A000A0U,\r
+ 0x00A000A0U,\r
+ 0x00A000A0U,\r
+ 0x00A000A0U,\r
+ 0x00A000A0U,\r
+ 0x00A000A0U,\r
+ 0x00A000A0U,\r
+ 0x00A000A0U,\r
+ 0x006D00A0U,\r
+ 0x01A00005U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00080200U,\r
+ 0x00000000U,\r
+ 0x20202020U,\r
+ 0x20202020U,\r
+ 0xF0F02020U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
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+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
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+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
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+ 0x00000000U,\r
+ 0x00000000U,\r
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+ 0x00000000U,\r
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+ 0x00000000U,\r
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+ 0x00000000U,\r
+ 0x00000000U,\r
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+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x000004F0U,\r
+ 0x00000000U,\r
+ 0x00030200U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x01030000U,\r
+ 0x00010000U,\r
+ 0x01030004U,\r
+ 0x01000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x01000001U,\r
+ 0x00000100U,\r
+ 0x000800C0U,\r
+ 0x060100CCU,\r
+ 0x00030066U,\r
+ 0x00000000U,\r
+ 0x00000001U,\r
+ 0x0000AAAAU,\r
+ 0x00005555U,\r
+ 0x0000B5B5U,\r
+ 0x00004A4AU,\r
+ 0x00005656U,\r
+ 0x0000A9A9U,\r
+ 0x0000A9A9U,\r
+ 0x0000B5B5U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x2A000000U,\r
+ 0x00000808U,\r
+ 0x0F000000U,\r
+ 0x00000F0FU,\r
+ 0x10200000U,\r
+ 0x0C002004U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x55555555U,\r
+ 0xAAAAAAAAU,\r
+ 0x55555555U,\r
+ 0xAAAAAAAAU,\r
+ 0x00005555U,\r
+ 0x01000100U,\r
+ 0x00800180U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000104U,\r
+ 0x00000120U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000001U,\r
+ 0x07FF0000U,\r
+ 0x0080081FU,\r
+ 0x00081020U,\r
+ 0x04010000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000100U,\r
+ 0x01CC0C01U,\r
+ 0x0003CC0CU,\r
+ 0x20000140U,\r
+ 0x07FF0200U,\r
+ 0x0000DD01U,\r
+ 0x10100303U,\r
+ 0x10101010U,\r
+ 0x10101010U,\r
+ 0x00041010U,\r
+ 0x00100010U,\r
+ 0x00100010U,\r
+ 0x00100010U,\r
+ 0x00100010U,\r
+ 0x00050010U,\r
+ 0x51517041U,\r
+ 0x31C06000U,\r
+ 0x07AB0340U,\r
+ 0x00C0C001U,\r
+ 0x0D0C0001U,\r
+ 0x10001000U,\r
+ 0x0C063E42U,\r
+ 0x0F0C3201U,\r
+ 0x01000140U,\r
+ 0x0C000420U,\r
+ 0x000002DDU,\r
+ 0x0A0000D0U,\r
+ 0x00030200U,\r
+ 0x02800000U,\r
+ 0x80800000U,\r
+ 0x000D2010U,\r
+ 0x76543210U,\r
+ 0x00000008U,\r
+ 0x02800280U,\r
+ 0x02800280U,\r
+ 0x02800280U,\r
+ 0x02800280U,\r
+ 0x00000280U,\r
+ 0x0000A000U,\r
+ 0x00A000A0U,\r
+ 0x00A000A0U,\r
+ 0x00A000A0U,\r
+ 0x00A000A0U,\r
+ 0x00A000A0U,\r
+ 0x00A000A0U,\r
+ 0x00A000A0U,\r
+ 0x00A000A0U,\r
+ 0x006D00A0U,\r
+ 0x01A00005U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00080200U,\r
+ 0x00000000U,\r
+ 0x20202020U,\r
+ 0x20202020U,\r
+ 0xF0F02020U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
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+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
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+ 0x00000000U,\r
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+ 0x00000000U,\r
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+ 0x00000000U,\r
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+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
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+ 0x00000000U,\r
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+ 0x00000000U,\r
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+ 0x00000000U,\r
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+ 0x00000000U,\r
+ 0x00000000U,\r
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+ 0x00000000U,\r
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+ 0x00000000U,\r
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+ 0x00000000U,\r
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+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x000004F0U,\r
+ 0x00000000U,\r
+ 0x00030200U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x01030000U,\r
+ 0x00010000U,\r
+ 0x01030004U,\r
+ 0x01000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x01000001U,\r
+ 0x00000100U,\r
+ 0x000800C0U,\r
+ 0x060100CCU,\r
+ 0x00030066U,\r
+ 0x00000000U,\r
+ 0x00000001U,\r
+ 0x0000AAAAU,\r
+ 0x00005555U,\r
+ 0x0000B5B5U,\r
+ 0x00004A4AU,\r
+ 0x00005656U,\r
+ 0x0000A9A9U,\r
+ 0x0000A9A9U,\r
+ 0x0000B5B5U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x2A000000U,\r
+ 0x00000808U,\r
+ 0x0F000000U,\r
+ 0x00000F0FU,\r
+ 0x10200000U,\r
+ 0x0C002004U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x55555555U,\r
+ 0xAAAAAAAAU,\r
+ 0x55555555U,\r
+ 0xAAAAAAAAU,\r
+ 0x00005555U,\r
+ 0x01000100U,\r
+ 0x00800180U,\r
+ 0x00000001U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
+ 0x00000000U,\r
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+ 0x3F0DFF11U,\r
+ 0x01FF00F0U,\r
+ 0x20040006U,\r
+};\r
+\r
+uint16_t DDRSS_ctlRegNum[] =\r
+{\r
+ 0,\r
+ 1,\r
+ 2,\r
+ 3,\r
+ 4,\r
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+};\r
+\r
+uint16_t DDRSS_phyIndepRegNum[] =\r
+{\r
+ 0,\r
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+ 299,\r
+};\r
+\r
+uint16_t DDRSS_phyRegNum[] =\r
+{\r
+ 0,\r
+ 1,\r
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+ 4,\r
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+};\r
+\r
diff --git a/packages/ti/drv/emac/firmware/icss_dualmac/src/pa_stat.h b/packages/ti/drv/emac/firmware/icss_dualmac/src/pa_stat.h
index 3a2acc8a416a722c195b8e647ae8e7e1d2306c52..ce6e96f4e0d77a3a39b57e49a938308331af53b8 100644 (file)
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
; EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ .if $defined("SLICE0")
TX_COL_RETRIES .set 80
TX_COL_DROPPED .set 81
+TX_QUEUE_CNT .set 16 ; 8 counters 16-23
+RX2HOST .set 48 ; 4 counters 48-51
+ .else
+TX_COL_RETRIES .set 80 + 128
+TX_COL_DROPPED .set 81 + 128
+TX_QUEUE_CNT .set 16 + 128 ; 8 counters 16-23
+RX2HOST .set 48 + 128; 4 counters 48-51
+ .endif
-; index is just a number but not an offset.
-m_inc_stat .macro reg, index
.if $defined("PRU0")
- ldi reg, index
- sbco ®, c9, 0x40, 1
+PA_STAT_R .set 0x40
.endif
.if $defined("PRU1")
- ldi reg, (index + 128)
- sbco ®, c9, 0x44, 1
+PA_STAT_R .set 0x44
.endif
.if $defined("RTU0")
- ldi reg, index
- sbco ®, c9, 0x48, 1
+PA_STAT_R .set 0x48
.endif
.if $defined("RTU1")
- ldi reg, (index + 128)
- sbco ®, c9, 0x4c, 1
+PA_STAT_R .set 0x4c
.endif
+
+; index is just a number but not an offset.
+m_inc_stat .macro reg, index
+ ldi reg, index
+ sbco ®, c9, PA_STAT_R, 1
.endm
diff --git a/packages/ti/drv/emac/firmware/icss_dualmac/src/rtu_psi.h b/packages/ti/drv/emac/firmware/icss_dualmac/src/rtu_psi.h
index f48b0d343aa53507b944da4acd4323029d450cf3..236366d359cb96ca5e3364d1138344f91bfc9aa5 100644 (file)
add r2, Ctx.ippc_res, MQ_SLOT0_RTU ;queue
TM_DISABLE
MQ_PUSH r2, r7, fail?
+ add r2, Ctx.ippc_res, TX_QUEUE_CNT
+ sbco &r2, c9, PA_STAT_R, 1
set GRrtu.pqmap, GRrtu.pqmap, Ctx.ippc_res
TM_ENABLE
jmp done?
diff --git a/packages/ti/drv/emac/firmware/icss_dualmac/src/rtu_v2.asm b/packages/ti/drv/emac/firmware/icss_dualmac/src/rtu_v2.asm
index 8ad95931f7758b87cf22ea7ddf2b527bce0222a5..3e82510c97adb95915f20073e59240bb682b8dd3 100644 (file)
.include "txrate.h"
.include "rtu_psi.h"
.include "iep.h"
+ .include "pa_stat.h"
loop_here .macro
here?: jmp here?
diff --git a/packages/ti/drv/emac/firmware/icss_dualmac/src/rxl2_txl2.asm b/packages/ti/drv/emac/firmware/icss_dualmac/src/rxl2_txl2.asm
index 6abf0708cfb03911f7a03d40d1a968ab26e002c0..bf34536d3dc92f310d4cb895dadf020f5af27796 100644 (file)
TM_DISABLE
PSIQ_POP
TM_ENABLE
+ m_inc_stat r19, RX2HOST
;r2 = flow | len r3 = starting read index
PSISANDF_TX_INIT2 r2, r3
index b8787950751e0cd7dd50299cc6855554d842b4b2..28e7d9999fe7982805df0f10e659f9eac2f1d0d4 100644 (file)
*/
static void GPIO_v1_hwiFxn(uintptr_t portIdx)
{
- uint32_t gpioPins;
- uint32_t gpioBase;
- uint32_t gpioIndex;
- uint32_t bitNum;
- uint32_t portNo = (uint32_t)portIdx;
+ uint32_t gpioPins;
+ uint32_t gpioBase;
+ uint32_t gpioIndex;
+ uint32_t bitNum;
+ uint32_t portNo = (uint32_t)portIdx;
GPIO_PortCallbackInfo *portCallbackInfo;
- GPIO_v1_HwAttrs *hwAttrs = (GPIO_v1_HwAttrs *)&GPIO_v1_hwAttrs[portNo - 1U];
- uint32_t intrLineNum = GPIO_INT_LINE_1;
+ GPIO_v1_HwAttrs *hwAttrs = (GPIO_v1_HwAttrs *)&GPIO_v1_hwAttrs[portNo - 1U];
+ uint32_t intrLineNum = GPIO_INT_LINE_1;
+ uint32_t gpioPinsClear;
+
portCallbackInfo = &gpioCallbackInfo[portNo -1U];
- gpioBase = hwAttrs->baseAddr;
+ gpioBase = hwAttrs->baseAddr;
/* Find out which pins have their interrupt flags set */
- gpioPins = GPIORawIntStatus(gpioBase, intrLineNum, GPIO_PIN_MASK_ALL);
-
- /* Clear all the set bits at once */
- GPIOIntrClearMask(gpioBase, intrLineNum, gpioPins);
+ gpioPins = GPIORawIntStatus(gpioBase, intrLineNum, GPIO_PIN_MASK_ALL);
+ gpioPinsClear = gpioPins;
/* Match each set bit to its corresponding callback function */
while (gpioPins) {
}
gpioPins &= ~(((uint32_t)1U) << bitNum);
}
+
+ /* Clear all the set bits at once */
+ GPIOIntrClearMask(gpioBase, intrLineNum, gpioPinsClear);
}
/*
diff --git a/packages/ti/drv/udma/examples/udma_apputils/udma_apputils.c b/packages/ti/drv/udma/examples/udma_apputils/udma_apputils.c
index 819df2676a08432de33f5c67267f006d60220487..31ac39ba212e9a3776c700f4aed9798c7313c658 100755 (executable)
cfgClec.extEvtNum = 0;
cfgClec.c7xEvtNum = 14;
CSL_clecConfigEvent(clecBaseAddr, i, &cfgClec);
-
- /* Switch now */
- CSL_c7xSecSupv2NonSecSupv();
#endif
return;
{
uint32_t isCacheCoherent;
-#if defined (BUILD_MPU1_0) || defined (BUILD_C7X_1)
+#if defined (BUILD_MPU1_0)
isCacheCoherent = TRUE;
#else
isCacheCoherent = FALSE;
diff --git a/packages/ti/drv/udma/unit_test/udma_ut/baremetal/am65xx/linker_a53.lds b/packages/ti/drv/udma/unit_test/udma_ut/baremetal/am65xx/linker_a53.lds
--- /dev/null
@@ -0,0 +1,210 @@
+/* File: linker_a53.lds
+ * Semihosting supported gcc Linker script for AM65XX A53 for QT
+ * Purpose: single core A53 C app
+*/
+__STACK_SIZE = 0x10000;
+__TI_STACK_SIZE = __STACK_SIZE;
+
+MEMORY
+{
+ MCU_RESVD : ORIGIN = 0x000041C00000, LENGTH = 0x00060000 /* MCUSS-OCMC RAM RESERVED FOR MCUSS & SOC Boot - 384KB */
+ OCMCRAM : ORIGIN = 0x000041C60000, LENGTH = 0x00020000 /* MCUSS-OCMC RAM - 128KB */
+ BOOTVECTOR : ORIGIN = 0x000070000100, LENGTH = 0x00001000 - 0x100 /* MSMC RAM INIT CODE (4 KB) */
+ MSMC_SRAM : ORIGIN = 0x000070001000, LENGTH = 0xEF000 /* MSMC RAM GENERAL USE */
+ MSMC_SRAM_H : ORIGIN = 0x000070100000, LENGTH = 0xE2000 /* MSMC RAM GENERAL USE - High memory */
+ MSMC_DMSC : ORIGIN = 0x0000701F0000, LENGTH = 0x10000 /* Reserved for DMSC */
+
+ DDR_0 (RWX) : ORIGIN = 0x80000000, LENGTH = 0x10000000
+ DDR_1 (RWX) : ORIGIN = 0x90000000, LENGTH = 0x10000000
+ DDR_2 (RWX) : ORIGIN = 0xA0000000, LENGTH = 0x60000000
+}
+
+REGION_ALIAS("REGION_TEXT", MSMC_SRAM);
+REGION_ALIAS("REGION_BSS", MSMC_SRAM);
+REGION_ALIAS("REGION_DATA", MSMC_SRAM);
+REGION_ALIAS("REGION_STACK", MSMC_SRAM);
+REGION_ALIAS("REGION_HEAP", MSMC_SRAM);
+REGION_ALIAS("REGION_ARM_EXIDX", MSMC_SRAM);
+REGION_ALIAS("REGION_ARM_EXTAB", MSMC_SRAM);
+REGION_ALIAS("REGION_TEXT_STARTUP", MSMC_SRAM);
+REGION_ALIAS("REGION_DATA_BUFFER", DDR_0);
+REGION_ALIAS("REGION_FAR", DDR_0);
+REGION_ALIAS("REGION_UDMA_BUFFER_MSMC", MSMC_SRAM_H);
+REGION_ALIAS("REGION_UDMA_BUFFER_DDR", DDR_0);
+REGION_ALIAS("REGION_UDMA_BUFFER_OSPI", DDR_0);
+REGION_ALIAS("REGION_UDMA_BUFFER_INTERNAL", DDR_0);
+
+SECTIONS {
+
+ .vecs : {
+ *(.vecs)
+ } > BOOTVECTOR AT> BOOTVECTOR
+
+ .text.csl_a53_startup : {
+ *(.text.csl_a53_startup)
+ *(.Entry)
+ } > REGION_TEXT_STARTUP AT> REGION_TEXT_STARTUP
+
+ .text : {
+ CREATE_OBJECT_SYMBOLS
+ *(.text)
+ *(.text.*)
+ . = ALIGN(0x8);
+ KEEP (*(.ctors))
+ . = ALIGN(0x4);
+ KEEP (*(.dtors))
+ . = ALIGN(0x8);
+ __init_array_start = .;
+ KEEP (*(.init_array*))
+ __init_array_end = .;
+ *(.init)
+ *(.fini*)
+ } > REGION_TEXT AT> REGION_TEXT
+
+ PROVIDE (__etext = .);
+ PROVIDE (_etext = .);
+ PROVIDE (etext = .);
+
+ .rodata : {
+ *(.rodata)
+ *(.rodata*)
+ } > REGION_TEXT AT> REGION_TEXT
+
+ .data_buffer : ALIGN (8) {
+ __data_buffer_load__ = LOADADDR (.data_buffer);
+ __data_buffer_start__ = .;
+ *(.data_buffer)
+ *(.data_buffer*)
+ . = ALIGN (8);
+ __data_buffer_end__ = .;
+ } > REGION_DATA_BUFFER AT> REGION_DATA_BUFFER
+
+ .data : ALIGN (8) {
+ __data_load__ = LOADADDR (.data);
+ __data_start__ = .;
+ *(.data)
+ *(.data*)
+ . = ALIGN (8);
+ __data_end__ = .;
+ } > REGION_DATA AT> REGION_TEXT
+
+ .ARM.exidx : {
+ __exidx_start = .;
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ __exidx_end = .;
+ } > REGION_ARM_EXIDX AT> REGION_ARM_EXIDX
+
+ .ARM.extab : {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > REGION_ARM_EXTAB AT> REGION_ARM_EXTAB
+
+ /* usb application ramdisk buffer */
+ .bss:extMemCache:ramdisk (NOLOAD) : ALIGN (32) {
+ } > DDR_0
+
+ /* For NDK packet memory, we need to map this sections before .bss*/
+ .bss:NDK_PACKETMEM (NOLOAD) : ALIGN (128) {} > DDR_0
+ .bss:NDK_MMBUFFER (NOLOAD) : ALIGN (128) {} > DDR_0
+
+ /* USB or any other LLD buffer for benchmarking */
+ .benchmark_buffer (NOLOAD) : ALIGN (32) {
+ } > DDR_0
+
+ /* cal's application buffer */
+ .bss:frameBuffer (NOLOAD) : ALIGN (32) {
+ } > DDR_0
+
+ .udma_buffer_msmc (NOLOAD) : ALIGN (128) {
+ } > REGION_UDMA_BUFFER_MSMC
+
+ .udma_buffer_ddr (NOLOAD) : ALIGN (128) {
+ } > REGION_UDMA_BUFFER_DDR
+
+ .udma_buffer_internal (NOLOAD) : ALIGN (128) {
+ } > REGION_UDMA_BUFFER_INTERNAL
+
+ .udma_buffer_ospi (NOLOAD) : ALIGN (128) {
+ } > REGION_UDMA_BUFFER_OSPI
+
+ .bss : {
+ __bss_start__ = .;
+ *(.shbss)
+ *(.bss)
+ *(.bss.*)
+ . = ALIGN (8);
+ __bss_end__ = .;
+ . = ALIGN (8);
+ *(COMMON)
+ } > REGION_BSS AT> REGION_BSS
+
+ .far : {
+ __far_start__ = .;
+ *(.far)
+ *(.far:*)
+ *(.far.*)
+ . = ALIGN (8);
+ __far_end__ = .;
+ . = ALIGN (8);
+ } > REGION_FAR AT> REGION_FAR
+
+ .heap : {
+ __heap_start__ = .;
+ end = __heap_start__;
+ _end = end;
+ __end = end;
+ KEEP(*(.heap))
+ __heap_end__ = .;
+ __HeapLimit = __heap_end__;
+ } > REGION_HEAP AT> REGION_HEAP
+
+ .stack (NOLOAD) : ALIGN(16) {
+ _stack = .;
+ __stack = .;
+ KEEP(*(.stack))
+ } > REGION_STACK AT> REGION_STACK
+
+ __TI_STACK_BASE = __stack;
+
+ /* Stabs debugging sections. */
+ .stab 0 : { *(.stab) }
+ .stabstr 0 : { *(.stabstr) }
+ .stab.excl 0 : { *(.stab.excl) }
+ .stab.exclstr 0 : { *(.stab.exclstr) }
+ .stab.index 0 : { *(.stab.index) }
+ .stab.indexstr 0 : { *(.stab.indexstr) }
+ .comment 0 : { *(.comment) }
+ /*
+ * DWARF debug sections.
+ * Symbols in the DWARF debugging sections are relative to the beginning
+ * of the section so we begin them at 0.
+ */
+ /* DWARF 1 */
+ .debug 0 : { *(.debug) }
+ .line 0 : { *(.line) }
+ /* GNU DWARF 1 extensions */
+ .debug_srcinfo 0 : { *(.debug_srcinfo) }
+ .debug_sfnames 0 : { *(.debug_sfnames) }
+ /* DWARF 1.1 and DWARF 2 */
+ .debug_aranges 0 : { *(.debug_aranges) }
+ .debug_pubnames 0 : { *(.debug_pubnames) }
+ /* DWARF 2 */
+ .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
+ .debug_abbrev 0 : { *(.debug_abbrev) }
+ .debug_line 0 : { *(.debug_line .debug_line.* .debug_line_end ) }
+ .debug_frame 0 : { *(.debug_frame) }
+ .debug_str 0 : { *(.debug_str) }
+ .debug_loc 0 : { *(.debug_loc) }
+ .debug_macinfo 0 : { *(.debug_macinfo) }
+ /* SGI/MIPS DWARF 2 extensions */
+ .debug_weaknames 0 : { *(.debug_weaknames) }
+ .debug_funcnames 0 : { *(.debug_funcnames) }
+ .debug_typenames 0 : { *(.debug_typenames) }
+ .debug_varnames 0 : { *(.debug_varnames) }
+ /* DWARF 3 */
+ .debug_pubtypes 0 : { *(.debug_pubtypes) }
+ .debug_ranges 0 : { *(.debug_ranges) }
+ /* DWARF Extension. */
+ .debug_macro 0 : { *(.debug_macro) }
+ .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }
+ /DISCARD/ : { *(.note.GNU-stack) *(.gnu_debuglink) *(.gnu.lto_*) }
+}
diff --git a/packages/ti/drv/udma/unit_test/udma_ut/baremetal/am65xx/linker_r5f.lds b/packages/ti/drv/udma/unit_test/udma_ut/baremetal/am65xx/linker_r5f.lds
--- /dev/null
@@ -0,0 +1,138 @@
+/*----------------------------------------------------------------------------*/
+/* File: k3m4_r5f_linker.cmd */
+/* Description: */
+/* Link command file for AM65XX M4 MCU 0 view */
+/* TI ARM Compiler version 15.12.3 LTS or later */
+/* */
+/* Platform: QT */
+/* (c) Texas Instruments 2017, All rights reserved. */
+/*----------------------------------------------------------------------------*/
+/* History: *'
+/* Aug 26th, 2016 Original version .......................... Loc Truong */
+/* Aug 01th, 2017 new TCM mem map .......................... Loc Truong */
+/* Nov 07th, 2017 Changes for R5F Init Code.................. Vivek Dhande */
+/*----------------------------------------------------------------------------*/
+/* Linker Settings */
+/* Standard linker options */
+--retain="*(.intvecs)"
+--retain="*(.intc_text)"
+--retain="*(.rstvectors)"
+--retain="*(.irqStack)"
+--retain="*(.fiqStack)"
+--retain="*(.abortStack)"
+--retain="*(.undStack)"
+--retain="*(.svcStack)"
+--fill_value=0
+--stack_size=0x2000
+--heap_size=0x1000
+--entry_point=_resetvectors /* Default C RTS boot.asm */
+
+-stack 0x2000 /* SOFTWARE STACK SIZE */
+-heap 0x2000 /* HEAP AREA SIZE */
+
+/* Stack Sizes for various modes */
+__IRQ_STACK_SIZE = 0x1000;
+__FIQ_STACK_SIZE = 0x1000;
+__ABORT_STACK_SIZE = 0x1000;
+__UND_STACK_SIZE = 0x1000;
+__SVC_STACK_SIZE = 0x1000;
+
+/*----------------------------------------------------------------------------*/
+/* Memory Map */
+MEMORY
+{
+ VECTORS (X) : origin=0x41C7F000 length=0x1000
+ /* Reset Vectors base address(RESET_VECTORS) should be 64 bytes aligned */
+ RESET_VECTORS (X) : origin=0x41C00000 length=0x100
+ /* MCU0_R5F_0 local view */
+ MCU0_R5F_TCMA_SBL_RSVD (X) : origin=0x0 length=0x100
+ MCU0_R5F_TCMA (X) : origin=0x100 length=0x8000 - 0x100
+ MCU0_R5F_TCMB0 (RWIX) : origin=0x41010000 length=0x8000
+
+ /* MCU0_R5F_1 SoC view */
+ MCU0_R5F1_ATCM (RWIX) : origin=0x41400000 length=0x8000
+ MCU0_R5F1_BTCM (RWIX) : origin=0x41410000 length=0x8000
+
+ /* Fully avaialble for apps. Used by SBL to load SYSFW */
+ OCMRAM_LOW (RWIX) : origin=0x41C00100 length=0x40600 - 0x100 /* ~257KB */
+
+ /* MCU0 memory used for SBL. Avaiable after boot for app starts for dynamic use */
+ SBL_RESERVED (RWIX) : origin=0x41C40600 length=0x60000 - 0x40600 /* ~126KB */
+
+ /* MCU0 share locations */
+ OCMRAM (RWIX) : origin=0x41C60000 length=0x20000 - 0x1000 /* ~124KB */
+
+
+ /* AM65XX M4 locations */
+ MSMC3 (RWIX) : origin=0x70000000 length=0xF0000 /* 1MB - 64K */
+ MSMC3_H (RWIX) : origin=0x70100000 length=0xE2000 /* 1MB -56K */
+
+ /* Reserved for DMSC */
+ MSMC3_DMSC (RWIX) : origin=0x701F0000 length=0x10000 /* 64K */
+
+ DDR0 (RWIX) : origin=0x80000000 length=0x80000000 /* 2GB */
+
+/* Additional memory settings */
+
+} /* end of MEMORY */
+
+/*----------------------------------------------------------------------------*/
+/* Section Configuration */
+
+SECTIONS
+{
+/* 'intvecs' and 'intc_text' sections shall be placed within */
+/* a range of +\- 16 MB */
+ .intvecs : {} palign(8) > VECTORS
+ .intc_text : {} palign(8) > VECTORS
+ .rstvectors : {} palign(8) > RESET_VECTORS
+ .bootCode : {} palign(8) > MSMC3
+ .startupCode : {} palign(8) > MSMC3
+ .startupData : {} palign(8) > MSMC3, type = NOINIT
+ .text : {} palign(8) > MSMC3
+ .const : {} palign(8) > MSMC3
+ .cinit : {} palign(8) > MSMC3
+ .pinit : {} palign(8) > MSMC3
+ .bss : {} align(4) > MSMC3
+ .far : {} align(4) > DDR0
+ .data : {} palign(128) > MSMC3
+ .boardcfg_data : {} palign(128) > MSMC3
+ .sysmem : {} > MSMC3
+
+ .udma_buffer_ddr : {} palign(128) > DDR0
+ .udma_buffer_ospi : {} palign(128) > DDR0
+ .udma_buffer_msmc : {} palign(128) > MSMC3
+ .udma_buffer_internal : {} palign(128) > OCMRAM
+
+ /* USB ram disk dev-msc example */
+ .bss:extMemCache:ramdisk : {} align (32) > DDR0
+
+ /* USB or any other LLD buffer for benchmarking */
+ .benchmark_buffer (NOLOAD) {} ALIGN (8) > DDR0
+
+ .stack : {} align(4) > MSMC3 (HIGH)
+ .irqStack : {. = . + __IRQ_STACK_SIZE;} align(4) > MSMC3 (HIGH)
+ RUN_START(__IRQ_STACK_START)
+ RUN_END(__IRQ_STACK_END)
+ .fiqStack : {. = . + __FIQ_STACK_SIZE;} align(4) > MSMC3 (HIGH)
+ RUN_START(__FIQ_STACK_START)
+ RUN_END(__FIQ_STACK_END)
+ .abortStack : {. = . + __ABORT_STACK_SIZE;} align(4) > MSMC3 (HIGH)
+ RUN_START(__ABORT_STACK_START)
+ RUN_END(__ABORT_STACK_END)
+ .undStack : {. = . + __UND_STACK_SIZE;} align(4) > MSMC3 (HIGH)
+ RUN_START(__UND_STACK_START)
+ RUN_END(__UND_STACK_END)
+ .svcStack : {. = . + __SVC_STACK_SIZE;} align(4) > MSMC3 (HIGH)
+ RUN_START(__SVC_STACK_START)
+ RUN_END(__SVC_STACK_END)
+
+/* Additional sections settings */
+
+} /* end of SECTIONS */
+
+/*----------------------------------------------------------------------------*/
+/* Misc linker settings */
+
+
+/*-------------------------------- END ---------------------------------------*/
diff --git a/packages/ti/drv/udma/unit_test/udma_ut/baremetal/j721e/linker_a72.lds b/packages/ti/drv/udma/unit_test/udma_ut/baremetal/j721e/linker_a72.lds
--- /dev/null
@@ -0,0 +1,214 @@
+__STACK_SIZE = 0x20000;
+__TI_STACK_SIZE = __STACK_SIZE;
+
+MEMORY
+{
+ OCMCRAM : ORIGIN = 0x000041C00000, LENGTH = 0x00080000 /* MCUSS-OCMC RAM - 512KB */
+
+
+ DDR_MPU1 (RWX) : ORIGIN = 0x80000000, LENGTH = 0x08000000
+ DDR_IPC (RWX) : ORIGIN = 0x90000000, LENGTH = 0x02000000
+
+ /* j721e MCMS3 locations */
+ /* j721e Reserved Memory for ARM Trusted Firmware */
+ MSMC3_ARM_FW (RWIX) : ORIGIN = 0x000070000000, LENGTH = 0x40000 /* 256KB */
+ BOOTVECTOR : ORIGIN = 0x000070040000, LENGTH = 0x1000 /* 4KB */
+ BOOTVECTOR_EL3 : ORIGIN = 0x000070041000, LENGTH = 0x1000 /* 4KB */
+ MSMC_MPU1 (RWX) : ORIGIN = 0x000070042000, LENGTH = 0x7AE000 /* 7864KB */
+ /* j721e Reserved Memory for DMSC Firmware */
+ MSMC3_DMSC_FW (RWIX) : ORIGIN = 0x0000707F0000, LENGTH = 0x10000 /* 64KB */
+}
+REGION_ALIAS("REGION_TEXT_EL3", DDR_MPU1);
+REGION_ALIAS("REGION_TEXT", DDR_MPU1);
+REGION_ALIAS("REGION_BSS", DDR_MPU1);
+REGION_ALIAS("REGION_DATA", DDR_MPU1);
+REGION_ALIAS("REGION_STACK", DDR_MPU1);
+REGION_ALIAS("REGION_HEAP", DDR_MPU1);
+REGION_ALIAS("REGION_ARM_EXIDX", DDR_MPU1);
+REGION_ALIAS("REGION_ARM_EXTAB", DDR_MPU1);
+REGION_ALIAS("REGION_TEXT_STARTUP", DDR_MPU1);
+REGION_ALIAS("REGION_DATA_BUFFER", DDR_MPU1);
+REGION_ALIAS("IPC_DATA_BUFFER_1", DDR_MPU1);
+REGION_ALIAS("REGION_UDMA_BUFFER_MSMC", MSMC_MPU1);
+REGION_ALIAS("REGION_UDMA_BUFFER_DDR", DDR_MPU1);
+REGION_ALIAS("REGION_UDMA_BUFFER_OSPI", DDR_MPU1);
+REGION_ALIAS("REGION_UDMA_BUFFER_INTERNAL", DDR_MPU1);
+
+
+SECTIONS {
+
+ .vecs : {
+ *(.vecs)
+ } > BOOTVECTOR AT> BOOTVECTOR
+
+ .vectors : {
+ *(.vectors)
+ } > BOOTVECTOR_EL3 AT> BOOTVECTOR_EL3
+ .text.el3 : {
+ *(.text.el3)
+ /* Ensure 8-byte alignment for descriptors and ensure inclusion */
+ . = ALIGN(8);
+ __RT_SVC_DESCS_START__ = .;
+ KEEP(*(rt_svc_descs))
+ __RT_SVC_DESCS_END__ = .;
+ } > REGION_TEXT_EL3 AT> REGION_TEXT_EL3
+
+ .text.csl_a72_startup : {
+ *(.text.csl_a72_startup)
+ *(.Entry)
+ } > REGION_TEXT_STARTUP AT> REGION_TEXT_STARTUP
+
+ .text : {
+ CREATE_OBJECT_SYMBOLS
+ *(.text)
+ *(.text.*)
+ . = ALIGN(0x8);
+ KEEP (*(.ctors))
+ . = ALIGN(0x4);
+ KEEP (*(.dtors))
+ . = ALIGN(0x8);
+ __init_array_start = .;
+ KEEP (*(.init_array*))
+ __init_array_end = .;
+ *(.init)
+ *(.fini*)
+ } > REGION_TEXT AT> REGION_TEXT
+
+ PROVIDE (__etext = .);
+ PROVIDE (_etext = .);
+ PROVIDE (etext = .);
+
+ .rodata : {
+ *(.rodata)
+ *(.rodata*)
+ } > REGION_TEXT AT> REGION_TEXT
+
+ .data_buffer : ALIGN (8) {
+ __data_buffer_load__ = LOADADDR (.data_buffer);
+ __data_buffer_start__ = .;
+ *(.data_buffer)
+ *(.data_buffer*)
+ . = ALIGN (8);
+ __data_buffer_end__ = .;
+ } > REGION_DATA_BUFFER AT> REGION_DATA_BUFFER
+
+ .data : ALIGN (8) {
+ __data_load__ = LOADADDR (.data);
+ __data_start__ = .;
+ *(.data)
+ *(.data*)
+ . = ALIGN (8);
+ __data_end__ = .;
+ } > REGION_DATA AT> REGION_TEXT
+
+ .ARM.exidx : {
+ __exidx_start = .;
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ __exidx_end = .;
+ } > REGION_ARM_EXIDX AT> REGION_ARM_EXIDX
+
+ .ARM.extab : {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > REGION_ARM_EXTAB AT> REGION_ARM_EXTAB
+
+ .bss:extMemCache:ramdisk : {
+ } > DDR_MPU1 /* MSMC_MPU1 */
+
+ /* USB or any other LLD buffer for benchmarking */
+ .benchmark_buffer (NOLOAD) : ALIGN (32) {
+ } > DDR_MPU1
+
+ .bss:frameBuffer (NOLOAD) : ALIGN (32) {
+ } > DDR_MPU1
+
+ .udma_buffer_msmc (NOLOAD) : ALIGN (128) {
+ } > REGION_UDMA_BUFFER_MSMC
+
+ .udma_buffer_ddr (NOLOAD) : ALIGN (128) {
+ } > REGION_UDMA_BUFFER_DDR
+
+ .udma_buffer_internal (NOLOAD) : ALIGN (128) {
+ } > REGION_UDMA_BUFFER_INTERNAL
+
+ .udma_buffer_ospi (NOLOAD) : ALIGN (128) {
+ } > REGION_UDMA_BUFFER_OSPI
+
+ ipc_data_buffer (NOLOAD) : ALIGN (32) {
+ } > IPC_DATA_BUFFER_1
+
+ /* For NDK packet memory, we need to map this sections before .bss*/
+ .bss:NDK_PACKETMEM (NOLOAD) : ALIGN (128) {} > DDR_MPU1
+ .bss:NDK_MMBUFFER (NOLOAD) : ALIGN (128) {} > DDR_MPU1
+
+ .bss : {
+ __bss_start__ = .;
+ *(.shbss)
+ *(.bss)
+ *(.bss.*)
+ . = ALIGN (8);
+ __bss_end__ = .;
+ . = ALIGN (8);
+ *(COMMON)
+ } > REGION_BSS AT> REGION_BSS
+
+ .heap : {
+ __heap_start__ = .;
+ end = __heap_start__;
+ _end = end;
+ __end = end;
+ KEEP(*(.heap))
+ __heap_end__ = .;
+ __HeapLimit = __heap_end__;
+ } > REGION_HEAP AT> REGION_HEAP
+
+ .stack (NOLOAD) : ALIGN(16) {
+ _stack = .;
+ __stack = .;
+ KEEP(*(.stack))
+ } > REGION_STACK AT> REGION_STACK
+
+ __TI_STACK_BASE = __stack;
+
+ /* Stabs debugging sections. */
+ .stab 0 : { *(.stab) }
+ .stabstr 0 : { *(.stabstr) }
+ .stab.excl 0 : { *(.stab.excl) }
+ .stab.exclstr 0 : { *(.stab.exclstr) }
+ .stab.index 0 : { *(.stab.index) }
+ .stab.indexstr 0 : { *(.stab.indexstr) }
+ .comment 0 : { *(.comment) }
+ /*
+ * DWARF debug sections.
+ * Symbols in the DWARF debugging sections are relative to the beginning
+ * of the section so we begin them at 0.
+ */
+ /* DWARF 1 */
+ .debug 0 : { *(.debug) }
+ .line 0 : { *(.line) }
+ /* GNU DWARF 1 extensions */
+ .debug_srcinfo 0 : { *(.debug_srcinfo) }
+ .debug_sfnames 0 : { *(.debug_sfnames) }
+ /* DWARF 1.1 and DWARF 2 */
+ .debug_aranges 0 : { *(.debug_aranges) }
+ .debug_pubnames 0 : { *(.debug_pubnames) }
+ /* DWARF 2 */
+ .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
+ .debug_abbrev 0 : { *(.debug_abbrev) }
+ .debug_line 0 : { *(.debug_line .debug_line.* .debug_line_end ) }
+ .debug_frame 0 : { *(.debug_frame) }
+ .debug_str 0 : { *(.debug_str) }
+ .debug_loc 0 : { *(.debug_loc) }
+ .debug_macinfo 0 : { *(.debug_macinfo) }
+ /* SGI/MIPS DWARF 2 extensions */
+ .debug_weaknames 0 : { *(.debug_weaknames) }
+ .debug_funcnames 0 : { *(.debug_funcnames) }
+ .debug_typenames 0 : { *(.debug_typenames) }
+ .debug_varnames 0 : { *(.debug_varnames) }
+ /* DWARF 3 */
+ .debug_pubtypes 0 : { *(.debug_pubtypes) }
+ .debug_ranges 0 : { *(.debug_ranges) }
+ /* DWARF Extension. */
+ .debug_macro 0 : { *(.debug_macro) }
+ .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }
+ /DISCARD/ : { *(.note.GNU-stack) *(.gnu_debuglink) *(.gnu.lto_*) }
+}
diff --git a/packages/ti/drv/udma/unit_test/udma_ut/baremetal/j721e/linker_c66.cmd b/packages/ti/drv/udma/unit_test/udma_ut/baremetal/j721e/linker_c66.cmd
--- /dev/null
@@ -0,0 +1,102 @@
+/*
+ * Copyright (c) 2018, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* This file is a copied and modified version of the J7ES.cmd provided from
+ * bios_6_73_00_12/packages/ti/sysbios/platforms/c6x/include/
+ *
+ * Default linker command file places all sections into L2SRAM which causes
+ * linker failures in the event of an entire program being larger than 288KB.
+ *
+ * Eventually this file should be deleted when J7ES platform is fully supported
+ * by the BIOS package.
+ */
+
+MEMORY
+{
+ L2SRAM: o = 0x00800000 l = 0x00048000 /* 288KB LOCAL L2/SRAM */
+ L1PSRAM: o = 0x00E00000 l = 0x00008000 /* 32KB LOCAL L1P/SRAM */
+ L1DSRAM: o = 0x00F00000 l = 0x00008000 /* 32KB LOCAL L1D/SRAM */
+ DDR0: o = 0x80000000 l = 0x20000000 /* 512MB DDR0 NAVSS */
+ /* j721e MSMC3 Memory */
+ /* j721e Reserved Memory for ARM Trusted Firmware */
+ MSMC3_ARM_FW (RWIX) : o = 0x70000000, l = 0x40000 /* 256KB */
+ MSMC3 (RWIX) : o = 0x70040000 l = 0x7B0000 /* 8MB - 320KB */
+ /* j721e Reserved Memory for DMSC Firmware */
+ MSMC3_DMSC_FW (RWIX) : o = 0x707F0000, l = 0x10000 /* 64KB */
+}
+
+-stack 0x2000 /* SOFTWARE STACK SIZE */
+-heap 0x2000 /* HEAP AREA SIZE */
+
+/* Set L1D, L1P and L2 Cache Sizes */
+ti_sysbios_family_c66_Cache_l1dSize = 32768;
+ti_sysbios_family_c66_Cache_l1pSize = 32768;
+ti_sysbios_family_c66_Cache_l2Size = 32768;
+
+SECTIONS
+{
+ .vecs: load > DDR0 ALIGN(0x10000)
+ .text:_c_int00 load > DDR0 ALIGN(0x10000)
+ .text: load > DDR0
+ .stack: load > DDR0
+ GROUP: load > DDR0
+ {
+ .bss:
+ .neardata:
+ .rodata:
+ }
+ .cio: load > DDR0
+ .const: load > DDR0
+ .data: load > DDR0
+ .switch: load > DDR0
+ .sysmem: load > DDR0
+ .far: load > DDR0
+ .args: load > DDR0
+
+ /* COFF sections */
+ .pinit: load > DDR0
+ .cinit: load > DDR0
+
+ /* EABI sections */
+ .binit: load > DDR0
+ .init_array: load > DDR0
+ .fardata: load > DDR0
+ .c6xabi.exidx: load > DDR0
+ .c6xabi.extab: load > DDR0
+
+ .csl_vect: load > L2SRAM
+
+ .udma_buffer_ddr load > DDR0
+ .udma_buffer_ospi load > DDR0
+ .udma_buffer_msmc load > MSMC3
+ .udma_buffer_internal load > L2SRAM
+}
diff --git a/packages/ti/drv/udma/unit_test/udma_ut/baremetal/j721e/linker_c7x.lds b/packages/ti/drv/udma/unit_test/udma_ut/baremetal/j721e/linker_c7x.lds
--- /dev/null
@@ -0,0 +1,115 @@
+/*
+ *
+ * Copyright (c) 2018 Texas Instruments Incorporated
+ *
+ * All rights reserved not granted herein.
+ *
+ * Limited License.
+ *
+ * Texas Instruments Incorporated grants a world-wide, royalty-free, non-exclusive
+ * license under copyrights and patents it now or hereafter owns or controls to make,
+ * have made, use, import, offer to sell and sell ("Utilize") this software subject to the
+ * terms herein. With respect to the foregoing patent license, such license is granted
+ * solely to the extent that any such patent is necessary to Utilize the software alone.
+ * The patent license shall not apply to any combinations which include this software,
+ * other than combinations with devices manufactured by or for TI ("TI Devices").
+ * No hardware patent is licensed hereunder.
+ *
+ * Redistributions must preserve existing copyright notices and reproduce this license
+ * (including the above copyright notice and the disclaimer and (if applicable) source
+ * code license limitations below) in the documentation and/or other materials provided
+ * with the distribution
+ *
+ * Redistribution and use in binary form, without modification, are permitted provided
+ * that the following conditions are met:
+ *
+ * * No reverse engineering, decompilation, or disassembly of this software is
+ * permitted with respect to any software provided in binary form.
+ *
+ * * any redistribution and use are licensed by TI for use only with TI Devices.
+ *
+ * * Nothing shall obligate TI to provide you with source code for the software
+ * licensed and provided to you in object code.
+ *
+ * If software source code is provided to you, modification and redistribution of the
+ * source code are permitted provided that the following conditions are met:
+ *
+ * * any redistribution and use of the source code, including any resulting derivative
+ * works, are licensed by TI for use only with TI Devices.
+ *
+ * * any redistribution and use of any object code compiled from the source code
+ * and any resulting derivative works, are licensed by TI for use only with TI Devices.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of its suppliers
+ *
+ * may be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * DISCLAIMER.
+ *
+ * THIS SOFTWARE IS PROVIDED BY TI AND TI'S LICENSORS "AS IS" AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL TI AND TI'S LICENSORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+-c
+-heap 0x20000
+-stack 0x20000
+--args 0x1000
+--diag_suppress=10068 /* "no matching section" */
+--cinit_compression=off
+--retain="*(xdc.meta)"
+
+MEMORY
+{
+ L2SRAM (RWX): org = 0x64800000, len = 0x00070000
+ DDR0 (RWIX) : ORIGIN = 0xA8000000, LENGTH = 0x08000000 /* 128 MB per core */
+ MSMC3 (RWIX) : ORIGIN = 0x70400000, LENGTH = 0x00080000 /* 512 KB per core */
+}
+
+SECTIONS
+{
+ xdc.meta (COPY): { } > DDR0
+ boot:
+ {
+ boot.*<boot.oe71>(.text)
+ } load > DDR0 ALIGN(0x200000)
+ .vecs > DDR0 ALIGN(0x400000)
+ .text > DDR0 ALIGN(0x200000)
+
+ .bss > DDR0 /* Zero-initialized data */
+ .data > DDR0 /* Initialized data */
+
+ .cinit > DDR0 /* could be part of const */
+ .init_array > DDR0 /* C++ initializations */
+ .stack > DDR0 ALIGN(0x2000)
+ .args > DDR0
+ .cio > DDR0
+ .const > DDR0
+ .switch > DDR0 /* For exception handling. */
+ .sysmem > DDR0 /* heap */
+
+ GROUP: > DDR0
+ {
+ .data.ti_sysbios_family_c7x_Mmu_tableArray : type=NOINIT
+ .data.ti_sysbios_family_c7x_Mmu_tableArraySlot : type=NOINIT
+ .data.ti_sysbios_family_c7x_Mmu_level1Table : type=NOINIT
+ }
+
+ ipc_data_buffer: > DDR0
+ .resource_table: { __RESOURCE_TABLE = .;} > DDR0
+
+ .udma_buffer_msmc > MSMC3
+ .udma_buffer_ddr > DDR0
+ .udma_buffer_internal > L2SRAM
+ .udma_buffer_ospi > DDR0
+
+}
diff --git a/packages/ti/drv/udma/unit_test/udma_ut/baremetal/j721e/linker_r5f.lds b/packages/ti/drv/udma/unit_test/udma_ut/baremetal/j721e/linker_r5f.lds
--- /dev/null
@@ -0,0 +1,102 @@
+/* Linker Settings */
+--retain="*(.bootCode)"
+--retain="*(.startupCode)"
+--retain="*(.startupData)"
+--retain="*(.intvecs)"
+--retain="*(.intc_text)"
+--retain="*(.rstvectors)"
+--retain="*(.irqStack)"
+--retain="*(.fiqStack)"
+--retain="*(.abortStack)"
+--retain="*(.undStack)"
+--retain="*(.svcStack)"
+--fill_value=0
+--stack_size=0x2000
+--heap_size=0x1000
+--entry_point=_resetvectors /* Default C RTS boot.asm */
+
+-stack 0x2000 /* SOFTWARE STACK SIZE */
+-heap 0x2000 /* HEAP AREA SIZE */
+
+/* Stack Sizes for various modes */
+__IRQ_STACK_SIZE = 0x1000;
+__FIQ_STACK_SIZE = 0x1000;
+__ABORT_STACK_SIZE = 0x1000;
+__UND_STACK_SIZE = 0x1000;
+__SVC_STACK_SIZE = 0x1000;
+
+/* Memory Map */
+MEMORY
+{
+ VECTORS (X) : origin=0x41C7F000 length=0x1000
+ /* Reset Vectors base address(RESET_VECTORS) should be 64 bytes aligned */
+ RESET_VECTORS (X) : origin=0x41C00000 length=0x100
+ /* MCU0_R5F_0 local view */
+ MCU0_R5F_TCMA_SBL_RSVD (X) : origin=0x0 length=0x100
+ MCU0_R5F_TCMA (X) : origin=0x100 length=0x8000 - 0x100
+ MCU0_R5F_TCMB0 (RWIX) : origin=0x41010000 length=0x8000
+
+ /* MCU0_R5F_1 SoC view */
+ MCU0_R5F1_ATCM (RWIX) : origin=0x41400000 length=0x8000
+ MCU0_R5F1_BTCM (RWIX) : origin=0x41410000 length=0x8000
+
+ /* MCU0 share locations */
+ OCMRAM (RWIX) : origin=0x41C00100 length=0x80000 - 0x1100 /* ~510KB */
+
+ /* j721e MCMS3 locations */
+ /* j721e Reserved Memory for ARM Trusted Firmware */
+ MSMC3_ARM_FW (RWIX) : origin=0x70000000 length=0x40000 /* 256KB */
+ MSMC3 (RWIX) : origin=0x70040000 length=0x7B0000 /* 8MB - 320KB */
+ /* j721e Reserved Memory for DMSC Firmware */
+ MSMC3_DMSC_FW (RWIX) : origin=0x707F0000 length=0x10000 /* 64KB */
+
+ DDR0 (RWIX) : origin=0x80000000 length=0x80000000 /* 2GB */
+}
+
+/* Section Configuration */
+SECTIONS
+{
+ /* 'intvecs' and 'intc_text' sections shall be placed within */
+ /* a range of +\- 16 MB */
+ .intvecs : {} palign(8) > VECTORS
+ .intc_text : {} palign(8) > VECTORS
+ .rstvectors : {} palign(8) > RESET_VECTORS
+ .bootCode : {} palign(8) > MSMC3
+ .startupCode : {} palign(8) > MSMC3
+ .startupData : {} palign(8) > MSMC3, type = NOINIT
+ .text : {} palign(8) > DDR0
+ .const : {} palign(8) > DDR0
+ .cinit : {} palign(8) > DDR0
+ .pinit : {} palign(8) > DDR0
+ .bss : {} align(4) > DDR0
+ .far : {} align(4) > DDR0
+ .data : {} palign(128) > DDR0
+ .boardcfg_data : {} palign(128) > MSMC3
+ .sysmem : {} > DDR0
+ .data_buffer : {} palign(128) > DDR0
+
+ .udma_buffer_ddr : {} palign(128) > DDR0
+ .udma_buffer_ospi : {} palign(128) > DDR0
+ .udma_buffer_msmc : {} palign(128) > MSMC3
+ .udma_buffer_internal : {} palign(128) > OCMRAM
+
+ /* USB or any other LLD buffer for benchmarking */
+ .benchmark_buffer (NOLOAD) {} ALIGN (8) > DDR0
+
+ .stack : {} align(4) > DDR0 (HIGH)
+ .irqStack : {. = . + __IRQ_STACK_SIZE;} align(4) > DDR0 (HIGH)
+ RUN_START(__IRQ_STACK_START)
+ RUN_END(__IRQ_STACK_END)
+ .fiqStack : {. = . + __FIQ_STACK_SIZE;} align(4) > DDR0 (HIGH)
+ RUN_START(__FIQ_STACK_START)
+ RUN_END(__FIQ_STACK_END)
+ .abortStack : {. = . + __ABORT_STACK_SIZE;} align(4) > DDR0 (HIGH)
+ RUN_START(__ABORT_STACK_START)
+ RUN_END(__ABORT_STACK_END)
+ .undStack : {. = . + __UND_STACK_SIZE;} align(4) > DDR0 (HIGH)
+ RUN_START(__UND_STACK_START)
+ RUN_END(__UND_STACK_END)
+ .svcStack : {. = . + __SVC_STACK_SIZE;} align(4) > DDR0 (HIGH)
+ RUN_START(__SVC_STACK_START)
+ RUN_END(__SVC_STACK_END)
+}
diff --git a/packages/ti/drv/udma/unit_test/udma_ut/baremetal/main_baremetal.c b/packages/ti/drv/udma/unit_test/udma_ut/baremetal/main_baremetal.c
--- /dev/null
@@ -0,0 +1,73 @@
+/*
+ * Copyright (c) Texas Instruments Incorporated 2018
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * \file main_tirtos.c
+ *
+ * \brief Main file for TI-RTOS build
+ */
+
+/* ========================================================================== */
+/* Include Files */
+/* ========================================================================== */
+#include <stdio.h>
+#include <udma_test.h>
+
+/* ========================================================================== */
+/* Macros & Typedefs */
+/* ========================================================================== */
+
+/* ========================================================================== */
+/* Structure Declarations */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/* Function Declarations */
+/* ========================================================================== */
+
+void taskFxn(void *a0, void *a1);
+
+/* ========================================================================== */
+/* Global Variables */
+/* ========================================================================== */
+
+/* ========================================================================== */
+/* Function Definitions */
+/* ========================================================================== */
+
+int main(void)
+{
+ taskFxn(NULL, NULL);
+ return(0);
+}
diff --git a/packages/ti/drv/udma/unit_test/udma_ut/main_common.c b/packages/ti/drv/udma/unit_test/udma_ut/main_common.c
--- /dev/null
@@ -0,0 +1,100 @@
+/*
+ * Copyright (c) Texas Instruments Incorporated 2018
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * \file main_common.c
+ *
+ * \brief Main file for TI-RTOS build
+ */
+
+/* ========================================================================== */
+/* Include Files */
+/* ========================================================================== */
+
+#include <stdio.h>
+#include <ti/board/board.h>
+#include <udma_test.h>
+
+/* ========================================================================== */
+/* Macros & Typedefs */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/* Structure Declarations */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/* Function Declarations */
+/* ========================================================================== */
+
+void taskFxn(void *a0, void *a1);
+
+/* ========================================================================== */
+/* Global Variables */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/* Function Definitions */
+/* ========================================================================== */
+
+void taskFxn(void *a0, void *a1)
+{
+ int32_t testPassed;
+ Board_initCfg boardCfg;
+ Fvid2_InitPrms fvid2InitPrms;
+
+ boardCfg = BOARD_INIT_PINMUX_CONFIG |
+ BOARD_INIT_UART_STDIO;
+ Board_init(boardCfg);
+
+ Udma_appC66xIntrConfig();
+
+ Fvid2InitPrms_init(&fvid2InitPrms);
+ fvid2InitPrms.printFxn = &udmaTestPrint;
+ Fvid2_init(&fvid2InitPrms);
+
+ testPassed = udmaTestParser();
+ if (UDMA_SOK != testPassed)
+ {
+ GT_0trace(UdmaUtTrace, GT_INFO1, " UDMA Unit Test Failed!!!\n");
+ }
+
+ Fvid2_deInit(NULL);
+
+ return;
+}
diff --git a/packages/ti/drv/udma/unit_test/udma_ut/rtos/makefile b/packages/ti/drv/udma/unit_test/udma_ut/makefile
similarity index 68%
rename from packages/ti/drv/udma/unit_test/udma_ut/rtos/makefile
rename to packages/ti/drv/udma/unit_test/udma_ut/makefile
index db915c4430f804e88305911f245a5d37b78e4ef5..ff54b6c2c0bfee64bb012997aac634e358701c2b 100755 (executable)
rename from packages/ti/drv/udma/unit_test/udma_ut/rtos/makefile
rename to packages/ti/drv/udma/unit_test/udma_ut/makefile
index db915c4430f804e88305911f245a5d37b78e4ef5..ff54b6c2c0bfee64bb012997aac634e358701c2b 100755 (executable)
#
include $(PDK_INSTALL_PATH)/ti/build/Rules.make
+APP_NAME = udma_unit_testapp
ifeq ($(UDMA_UT_MANUAL_ENTRY), yes)
APP_NAME = udma_user_input_unit_testapp
-else
-APP_NAME = udma_unit_testapp
+endif
+ifeq ($(UDMA_UT_BAREMETAL), yes)
+APP_NAME = udma_baremetal_unit_testapp
+BUILD_OS_TYPE=baremetal
+endif
+ifeq ($(UDMA_UT_DYNAMIC_ANALYSIS), yes)
+APP_NAME = udma_dynamic_unit_testapp
+BUILD_OS_TYPE=baremetal
endif
#
# This file is common makefile for building UDMA unit test app for both TI-RTOS/baremetal
#
-SRCDIR = . ../src ../src/soc/$(SOC)
-INCDIR = . ../src ../src/soc/$(SOC)
+SRCDIR = . ./src ./src/soc/$(SOC) ./rtos ./baremetal
+INCDIR = . ./src ./src/soc/$(SOC) ./rtos ./baremetal
# List all the external components/interfaces, whose interface header files
# need to be included for this component
XDC_CFG_UPDATE_$(CORE) = udma_ut.cfg
# Common source files and CFLAGS across all platforms and cores
-PACKAGE_SRCS_COMMON = . ../src ../../udma_ut_component.mk
+PACKAGE_SRCS_COMMON = . ./src ../udma_ut_component.mk
+SRCS_COMMON += main_common.c
SRCS_COMMON += udma_test_parser.c udma_test_blkcpy.c udma_test_common.c
SRCS_COMMON += udma_test_ring.c udma_test_proxy.c udma_test_ring_monitor.c
SRCS_COMMON += udma_test_event.c udma_test_flow.c
SRCS_COMMON += udma_test_bug.c udma_test_misc.c
-SRCS_COMMON += utils_mem.c utils_prf.c
SRCS_COMMON += udma_test_soc.c
+ifeq ($(BUILD_OS_TYPE), baremetal)
+SRCS_COMMON += utils_prf_baremetal.c utils_mem_baremetal.c
+else
+SRCS_COMMON += utils_prf.c utils_mem.c
+endif
CFLAGS_LOCAL_COMMON = $(PDK_CFLAGS) $(UDMA_CFLAGS) $(FVID2_CFLAGS)
ifeq ($(UDMA_UT_MANUAL_ENTRY), yes)
CFLAGS_LOCAL_COMMON += -DUDMA_UT_ENABLE_MANUAL_ENTRY
endif
-EXTERNAL_LNKCMD_FILE_LOCAL = $(SOC)/linker_$(CORE).lds
+ifeq ($(UDMA_UT_BAREMETAL), yes)
+ CFLAGS_LOCAL_COMMON += -DUDMA_UT_BAREMETAL
+endif
+ifeq ($(UDMA_UT_DYNAMIC_ANALYSIS), yes)
+ CFLAGS_LOCAL_COMMON += -DUDMA_UT_DYNAMIC_ANALYSIS -DUDMA_UT_BAREMETAL
+endif
+ifeq ($(BUILD_OS_TYPE), baremetal)
+ ifeq ($(ISA), c66)
+ EXTERNAL_LNKCMD_FILE_LOCAL = baremetal/$(SOC)/linker_$(ISA).cmd
+ else
+ EXTERNAL_LNKCMD_FILE_LOCAL = baremetal/$(SOC)/linker_$(ISA).lds
+ endif
+else
+EXTERNAL_LNKCMD_FILE_LOCAL = rtos/$(SOC)/linker_$(CORE).lds
+endif
# Core/SoC/platform specific source files and CFLAGS
# Example:
diff --git a/packages/ti/drv/udma/unit_test/udma_ut/rtos/main_tirtos.c b/packages/ti/drv/udma/unit_test/udma_ut/rtos/main_tirtos.c
index 02b9d45bf06d2cd5af303bd393b978ed74dabd1c..4794d0ac054bfa69ede87e632aed8e0d85d53209 100755 (executable)
/* Function Declarations */
/* ========================================================================== */
-static Void taskFxn(UArg a0, UArg a1);
+void taskFxn(void *a0, void *a1);
/* ========================================================================== */
/* Global Variables */
taskParams.stack = gAppTskStackMain;
taskParams.stackSize = sizeof (gAppTskStackMain);
- task = Task_create(taskFxn, &taskParams, &eb);
+ task = Task_create((Task_FuncPtr) taskFxn, &taskParams, &eb);
if(NULL == task)
{
BIOS_exit(0);
return(0);
}
-static Void taskFxn(UArg a0, UArg a1)
-{
- int32_t testPassed;
- Board_initCfg boardCfg;
- Fvid2_InitPrms fvid2InitPrms;
-
- boardCfg = BOARD_INIT_PINMUX_CONFIG |
- BOARD_INIT_UART_STDIO;
- Board_init(boardCfg);
-
- Udma_appC66xIntrConfig();
-
- Fvid2InitPrms_init(&fvid2InitPrms);
- fvid2InitPrms.printFxn = &udmaTestPrint;
- Fvid2_init(&fvid2InitPrms);
-
- testPassed = udmaTestParser();
- if (UDMA_SOK != testPassed)
- {
- GT_0trace(UdmaUtTrace, GT_INFO1, " UDMA Unit Test Failed!!!\n");
- }
-
- Fvid2_deInit(NULL);
-
- return;
-}
-
#if defined(BUILD_MPU) || defined (__C7100__)
extern void Osal_initMmuDefault(void);
void InitMmu(void)
diff --git a/packages/ti/drv/udma/unit_test/udma_ut/src/soc/am65xx/udma_test_soc.h b/packages/ti/drv/udma/unit_test/udma_ut/src/soc/am65xx/udma_test_soc.h
index 45d2104c78bf441dd95cd530735b56ecfbe2b2ce..f69196e452e304e47d6162e2f41e79be2efe0039 100644 (file)
#define UDMA_TEST_RF_SOC (UDMA_TEST_RF_SOC_AM65XX)
-#define UDMA_TEST_RF_MAIN_BC_HC (UDMA_TEST_RF_SOC | UDMA_TEST_RF_CORE_ALL | UDMA_TEST_RF_CFG_ALL)
-#define UDMA_TEST_RF_MAIN_BC (UDMA_TEST_RF_SOC | UDMA_TEST_RF_CORE_ALL | UDMA_TEST_RF_CFG_ALL)
-#define UDMA_TEST_RF_MCU_BC_HC (UDMA_TEST_RF_SOC | UDMA_TEST_RF_CORE_MCU1_0 | UDMA_TEST_RF_CFG_ALL)
-#define UDMA_TEST_RF_MCU_BC (UDMA_TEST_RF_SOC | UDMA_TEST_RF_CORE_ALL | UDMA_TEST_RF_CFG_ALL)
-#define UDMA_TEST_RF_DRU (UDMA_TEST_RF_SOC | UDMA_TEST_RF_CORE_ALL | UDMA_TEST_RF_CFG_ALL)
+#define UDMA_TEST_RF_MAIN_BC_HC (UDMA_TEST_RF_SOC | UDMA_TEST_RF_CORE_ALL | UDMA_TEST_RF_CFG_DEF)
+#define UDMA_TEST_RF_MAIN_BC (UDMA_TEST_RF_SOC | UDMA_TEST_RF_CORE_ALL | UDMA_TEST_RF_CFG_DEF)
+#define UDMA_TEST_RF_MCU_BC_HC (UDMA_TEST_RF_SOC | UDMA_TEST_RF_CORE_MCU1_0 | UDMA_TEST_RF_CFG_DEF)
+#define UDMA_TEST_RF_MCU_BC (UDMA_TEST_RF_SOC | UDMA_TEST_RF_CORE_ALL | UDMA_TEST_RF_CFG_DEF)
+#define UDMA_TEST_RF_DRU (UDMA_TEST_RF_SOC | UDMA_TEST_RF_CORE_ALL | UDMA_TEST_RF_CFG_DEF)
/* Multipe task testcases - some have only one instance. Doesn't make sense to run from 1 task */
-#define UDMA_TEST_RF_MAIN_BC_HC_MT (UDMA_TEST_RF_SOC | UDMA_TEST_RF_CORE_MPU1_0 | UDMA_TEST_RF_CFG_ALL)
+#define UDMA_TEST_RF_MAIN_BC_HC_MT (UDMA_TEST_RF_SOC | UDMA_TEST_RF_CORE_MPU1_0 | UDMA_TEST_RF_CFG_DEF)
#define UDMA_TEST_RF_MAIN_BC_MT (UDMA_TEST_RF_MAIN_BC)
#define UDMA_TEST_RF_MCU_BC_HC_MT (UDMA_TEST_RF_MCU_BC_HC)
#define UDMA_TEST_RF_MCU_BC_MT (UDMA_TEST_RF_MCU_BC)
#define UDMA_TEST_RF_MAIN_BC_PACING (UDMA_TEST_RF_MAIN_BC)
#define UDMA_TEST_RF_MAIN_BC_PAUSE (UDMA_TEST_RF_MAIN_BC)
-#define UDMA_TEST_RF_FLOW (UDMA_TEST_RF_SOC | UDMA_TEST_RF_CORE_ALL | UDMA_TEST_RF_CFG_ALL)
+#define UDMA_TEST_RF_FLOW (UDMA_TEST_RF_SOC | UDMA_TEST_RF_CORE_ALL | UDMA_TEST_RF_CFG_DEF)
#define UDMA_TEST_MAIN_UHC_START (0U)
#define UDMA_TEST_MCU_UHC_START (0U)
diff --git a/packages/ti/drv/udma/unit_test/udma_ut/src/soc/j721e/udma_test_soc.h b/packages/ti/drv/udma/unit_test/udma_ut/src/soc/j721e/udma_test_soc.h
index 175321570fe999b1c34ba3f7fe4f1ddb5a3e0d3d..91d55500998c2d5ba3b34b6ab025583b04b578d5 100644 (file)
UDMA_TEST_RF_CORE_MPU1_0 | \
UDMA_TEST_RF_CORE_MCU2_0 | \
UDMA_TEST_RF_CORE_MCU2_1 | \
- UDMA_TEST_RF_CFG_ALL)
-#define UDMA_TEST_RF_MAIN_BC (UDMA_TEST_RF_SOC | UDMA_TEST_RF_CORE_ALL | UDMA_TEST_RF_CFG_ALL)
+ UDMA_TEST_RF_CFG_DEF)
+#define UDMA_TEST_RF_MAIN_BC (UDMA_TEST_RF_SOC | UDMA_TEST_RF_CORE_ALL | UDMA_TEST_RF_CFG_DEF)
#define UDMA_TEST_RF_MCU_BC_HC (UDMA_TEST_RF_SOC | \
UDMA_TEST_RF_CORE_MCU1_0 | \
- UDMA_TEST_RF_CFG_ALL)
+ UDMA_TEST_RF_CFG_DEF)
#define UDMA_TEST_RF_MCU_BC (UDMA_TEST_RF_SOC | \
UDMA_TEST_RF_CORE_MPU1_0 | \
UDMA_TEST_RF_CORE_MCU2_0 | \
UDMA_TEST_RF_CORE_C66X_1 | \
UDMA_TEST_RF_CORE_C66X_2 | \
UDMA_TEST_RF_CORE_MCU1_0 | \
- UDMA_TEST_RF_CFG_ALL)
+ UDMA_TEST_RF_CFG_DEF)
#define UDMA_TEST_RF_DRU (UDMA_TEST_RF_SOC | \
UDMA_TEST_RF_CORE_MCU2_1 | \
UDMA_TEST_RF_CORE_C7X_1 | \
UDMA_TEST_RF_CORE_C66X_1 | \
UDMA_TEST_RF_CORE_C66X_2 | \
- UDMA_TEST_RF_CFG_ALL)
+ UDMA_TEST_RF_CFG_DEF)
/* Multipe task testcases - some have only one instance. Doesn't make sense to run from 1 task */
#define UDMA_TEST_RF_MAIN_BC_HC_MT (UDMA_TEST_RF_MAIN_BC_HC)
UDMA_TEST_RF_CORE_MPU1_0 | \
UDMA_TEST_RF_CORE_MCU2_0 | \
UDMA_TEST_RF_CORE_MCU2_1 | \
- UDMA_TEST_RF_CFG_ALL)
+ UDMA_TEST_RF_CFG_DEF)
#define UDMA_TEST_RF_MAIN_BC_PACING (UDMA_TEST_RF_MAIN_BC)
#define UDMA_TEST_RF_MAIN_BC_PAUSE (UDMA_TEST_RF_MAIN_BC)
diff --git a/packages/ti/drv/udma/unit_test/udma_ut/src/udma_test.h b/packages/ti/drv/udma/unit_test/udma_ut/src/udma_test.h
index e2753c9b942f29bb863d1eda0134c2cfb97bd7ba..65613c3eccaf6859bb29beb25920d025c23fbd00 100644 (file)
#include "utils_mem.h"
#include "utils_prf.h"
-#include "udma_test_soc.h"
+#if defined (SOC_AM65XX)
+#include "soc/am65xx/udma_test_soc.h"
+#else
+#include "soc/j721e/udma_test_soc.h"
+#endif
#ifdef __cplusplus
extern "C" {
UDMA_TEST_RF_CORE_MCU3_0 | UDMA_TEST_RF_CORE_MCU3_1)
/* For future when we have dynamic coverage testcases */
-#define UDMA_TEST_RF_CFG_ALL ((uint64_t)(((uint64_t) 0xFFFFU) << 48U))
+#define UDMA_TEST_RF_CFG_DEF ((uint64_t)(((uint64_t) 0x00001U) << 48U))
+#define UDMA_TEST_RF_CFG_DYN ((uint64_t)(((uint64_t) 0x00002U) << 48U))
/**
* \brief Test types - based on this the different application flow will be
diff --git a/packages/ti/drv/udma/unit_test/udma_ut/src/udma_test_blkcpy.c b/packages/ti/drv/udma/unit_test/udma_ut/src/udma_test_blkcpy.c
@@ -193,7 +193,11 @@ static int32_t udmaTestBlkcpyTestLoop(UdmaTestTaskObj *taskObj, uint32_t pauseTe
{
break;
}
+ #if defined (UDMA_UT_BAREMETAL)
+ Osal_delay(expectedTime - elapsedTime);
+ #else
TaskP_sleep(expectedTime - elapsedTime);
+ #endif
}
}
}
CSL_REG64_WR(chObj->trEventPrms.intrClearReg, chObj->trEventPrms.intrMask);
break;
}
+ #if !defined (UDMA_UT_BAREMETAL)
TaskP_yield();
+ #endif
}
}
}
@@ -330,7 +336,11 @@ static int32_t udmaTestBlkcpyTest(UdmaTestTaskObj *taskObj, uint32_t pauseTest)
{
/* Sleep for sometime and check if the transfer has completed;
* if so then it is an error */
+ #if defined (UDMA_UT_BAREMETAL)
+ Osal_delay(1);
+ #else
TaskP_sleep(1000); /* 1 sec sleep */
+ #endif
for(chCnt = 0U ; chCnt < taskObj->numCh; chCnt++)
{
chObj = taskObj->chObj[chCnt];
break;
}
+ #if !defined (UDMA_UT_BAREMETAL)
TaskP_yield();
+ #endif
}
}
break;
}
+ #if !defined (UDMA_UT_BAREMETAL)
TaskP_yield();
+ #endif
}
/* Unregister master event at the end - CQ is the master event */
diff --git a/packages/ti/drv/udma/unit_test/udma_ut/src/udma_test_common.c b/packages/ti/drv/udma/unit_test/udma_ut/src/udma_test_common.c
uint32_t AppUtils_getCurTimeInMsec(void)
{
- uint64_t curTimeMsec, curTimeUsec;
+ uint64_t curTimeMsec = 0, curTimeUsec = 0;
+#if defined (UDMA_UT_BAREMETAL) && defined (BUILD_C7X_1)
+ /* C7x baremetal doesnot support getting time timestamp */
+#else
curTimeUsec = TimerP_getTimeInUsecs();
+#endif
curTimeMsec = (curTimeUsec / 1000U);
return ((uint32_t) curTimeMsec);
diff --git a/packages/ti/drv/udma/unit_test/udma_ut/src/udma_test_parser.c b/packages/ti/drv/udma/unit_test/udma_ut/src/udma_test_parser.c
/* Global Variables */
/* ========================================================================== */
+#if !defined (UDMA_UT_BAREMETAL)
/* Task stack */
static uint8_t gUdmaParserTskStack[UDMA_TEST_MAX_TASKS][APP_TSK_STACK_MAIN] __attribute__((aligned(32)));;
+#endif
/* UDMA UT object. */
UdmaTestObj gUdmaTestUtObj =
return (retVal);
}
+#if defined (UDMA_UT_BAREMETAL)
+int32_t udmaTestCreateTestTasks(UdmaTestObj *testObj, UdmaTestParams *testPrms)
+{
+ int32_t retVal = UDMA_SOK;
+ uint32_t taskCnt;
+ UdmaTestTaskObj *taskObj;
+
+ for(taskCnt = 0U; taskCnt < testPrms->numTasks; taskCnt++)
+ {
+ taskObj = &testObj->taskObj[taskCnt];
+ udmaTestTask(taskObj, NULL);
+ }
+
+ for(taskCnt = 0u; taskCnt < testPrms->numTasks; taskCnt++)
+ {
+ retVal += testObj->taskObj[taskCnt].testResult;
+ }
+
+ return (retVal);
+}
+static int32_t udmaTestDeleteTestTasks(UdmaTestObj *testObj)
+{
+ return UDMA_SOK;
+}
+
+#else
int32_t udmaTestCreateTestTasks(UdmaTestObj *testObj, UdmaTestParams *testPrms)
{
int32_t retVal = UDMA_SOK;
return (retVal);
}
+#endif
static void udmaTestTask(void *arg0, void *arg1)
{
taskObj->testResult = retVal;
+#if !defined (UDMA_UT_BAREMETAL)
/* Test complete. Signal it */
SemaphoreP_post(testObj->taskCompleteSem);
+#endif
return;
}
testObj->traceMask = (GT_INFO1 | GT_TraceState_Enable);
testObj->sysCtrl.loopCnt = UDMA_TEST_DEF_LOOP_CNT;
testObj->sysCtrl.qdepth = UDMA_TEST_DEF_QDEPTH;
+#if defined (UDMA_UT_DYNAMIC_ANALYSIS)
+ testObj->sysCtrl.loopCnt = 1U;
+ testObj->sysCtrl.qdepth = 1U;
+#endif
testObj->sysCtrl.rtPrintEnable = FALSE;
/* Set run flag */
testObj->runFlag = 0U;
testObj->runFlag |= UDMA_TEST_RF_SOC;
testObj->runFlag |= UDMA_TEST_RF_CORE;
+ testObj->runFlag |= UDMA_TEST_RF_CFG_DEF;
+#if defined (UDMA_UT_DYNAMIC_ANALYSIS)
+ testObj->runFlag |= UDMA_TEST_RF_CFG_DYN;
+#endif
/* Mark all test cases as not run and set result to PASS */
for(testCnt = 0U; testCnt < UDMA_TEST_NUM_TESTCASES; testCnt++)
diff --git a/packages/ti/drv/udma/unit_test/udma_ut/src/udma_test_ring.c b/packages/ti/drv/udma/unit_test/udma_ut/src/udma_test_ring.c
CSL_REG64_WR(eventPrms.intrClearReg, eventPrms.intrMask);
break;
}
+ #if !defined (UDMA_UT_BAREMETAL)
TaskP_yield();
+ #endif
}
}
}
diff --git a/packages/ti/drv/udma/unit_test/udma_ut/src/udma_testcases.h b/packages/ti/drv/udma/unit_test/udma_ut/src/udma_testcases.h
index b27d8115eed252dcf8f2bc14638480c5a6634b66..b3ca6a2c0b10e11465a92aa5d0a6a72e319965c6 100644 (file)
.heapIdDest = {DEF_HEAP_ID},
.srcBufSize = {UDMA_TEST_DEF_ICNT0},
.destBufSize= {UDMA_TEST_DEF_DICNT0},
- .runFlag = (UDMA_TEST_RF_MAIN_BC),
+ .runFlag = (UDMA_TEST_RF_MAIN_BC | UDMA_TEST_RF_CFG_DYN),
.ringPrmId = UDMA_TEST_RING_PRMID_INVALID,
},
{
.heapIdDest = {DEF_HEAP_ID},
.srcBufSize = {UDMA_TEST_DEF_ICNT0},
.destBufSize= {UDMA_TEST_DEF_DICNT0},
- .runFlag = (UDMA_TEST_RF_MAIN_BC),
+ .runFlag = (UDMA_TEST_RF_MAIN_BC | UDMA_TEST_RF_CFG_DYN),
.ringPrmId = UDMA_TEST_RING_PRMID_INVALID,
},
{
.heapIdDest = {DEF_HEAP_ID},
.srcBufSize = {UDMA_TEST_DEF_ICNT0},
.destBufSize= {UDMA_TEST_DEF_DICNT0},
- .runFlag = (UDMA_TEST_RF_MCU_BC),
+ .runFlag = (UDMA_TEST_RF_MCU_BC | UDMA_TEST_RF_CFG_DYN),
.ringPrmId = UDMA_TEST_RING_PRMID_INVALID,
},
{
.heapIdDest = {DEF_HEAP_ID},
.srcBufSize = {UDMA_TEST_DEF_ICNT0},
.destBufSize= {UDMA_TEST_DEF_DICNT0},
- .runFlag = (UDMA_TEST_RF_MCU_BC),
+ .runFlag = (UDMA_TEST_RF_MCU_BC | UDMA_TEST_RF_CFG_DYN),
.ringPrmId = UDMA_TEST_RING_PRMID_INVALID,
},
{
.heapIdDest = {DEF_HEAP_ID},
.srcBufSize = {UDMA_TEST_DEF_ICNT0},
.destBufSize= {UDMA_TEST_DEF_DICNT0},
- .runFlag = (UDMA_TEST_RF_MAIN_BC),
+ .runFlag = (UDMA_TEST_RF_MAIN_BC | UDMA_TEST_RF_CFG_DYN),
.ringPrmId = UDMA_TEST_RING_PRMID_INVALID,
},
{
.heapIdDest = {DEF_HEAP_ID},
.srcBufSize = {UDMA_TEST_DEF_ICNT0},
.destBufSize= {UDMA_TEST_DEF_DICNT0},
- .runFlag = (UDMA_TEST_RF_DRU),
+ .runFlag = (UDMA_TEST_RF_DRU | UDMA_TEST_RF_CFG_DYN),
.ringPrmId = UDMA_TEST_RING_PRMID_INVALID,
},
{
.heapIdDest = {DEF_HEAP_ID},
.srcBufSize = {UDMA_TEST_DEF_ICNT0},
.destBufSize= {UDMA_TEST_DEF_DICNT0},
- .runFlag = (UDMA_TEST_RF_DRU),
+ .runFlag = (UDMA_TEST_RF_DRU | UDMA_TEST_RF_CFG_DYN),
.ringPrmId = UDMA_TEST_RING_PRMID_INVALID,
},
{
.heapIdDest = {DEF_HEAP_ID},
.srcBufSize = {UDMA_TEST_DEF_ICNT0},
.destBufSize= {UDMA_TEST_DEF_DICNT0},
- .runFlag = (UDMA_TEST_RF_SOC_ALL | UDMA_TEST_RF_CORE_ALL | UDMA_TEST_RF_CFG_ALL),
+ .runFlag = (UDMA_TEST_RF_SOC_ALL | UDMA_TEST_RF_CORE_ALL | UDMA_TEST_RF_CFG_DEF | UDMA_TEST_RF_CFG_DYN),
.ringPrmId = UDMA_TEST_RING_PRMID_EVENT_NONE,
},
{
.heapIdDest = {DEF_HEAP_ID},
.srcBufSize = {UDMA_TEST_DEF_ICNT0},
.destBufSize= {UDMA_TEST_DEF_DICNT0},
- .runFlag = (UDMA_TEST_RF_SOC_ALL | UDMA_TEST_RF_CORE_ALL | UDMA_TEST_RF_CFG_ALL),
+ .runFlag = (UDMA_TEST_RF_SOC_ALL | UDMA_TEST_RF_CORE_ALL | UDMA_TEST_RF_CFG_DEF | UDMA_TEST_RF_CFG_DYN),
.ringPrmId = UDMA_TEST_RING_PRMID_EVENT_NONE,
},
{
.heapIdDest = {DEF_HEAP_ID},
.srcBufSize = {UDMA_TEST_DEF_ICNT0},
.destBufSize= {UDMA_TEST_DEF_DICNT0},
- .runFlag = (UDMA_TEST_RF_SOC_ALL | UDMA_TEST_RF_CORE_ALL | UDMA_TEST_RF_CFG_ALL),
+ .runFlag = (UDMA_TEST_RF_SOC_ALL | UDMA_TEST_RF_CORE_ALL | UDMA_TEST_RF_CFG_DEF | UDMA_TEST_RF_CFG_DYN),
.ringPrmId = UDMA_TEST_RING_PRMID_EVENT_INTR,
},
{
.heapIdDest = {DEF_HEAP_ID},
.srcBufSize = {UDMA_TEST_DEF_ICNT0},
.destBufSize= {UDMA_TEST_DEF_DICNT0},
- .runFlag = (UDMA_TEST_RF_SOC_ALL | UDMA_TEST_RF_CORE_ALL | UDMA_TEST_RF_CFG_ALL),
+ .runFlag = (UDMA_TEST_RF_SOC_ALL | UDMA_TEST_RF_CORE_ALL | UDMA_TEST_RF_CFG_DEF | UDMA_TEST_RF_CFG_DYN),
.ringPrmId = UDMA_TEST_RING_PRMID_EVENT_POLLED,
},
{
.heapIdDest = {DEF_HEAP_ID},
.srcBufSize = {UDMA_TEST_DEF_ICNT0},
.destBufSize= {UDMA_TEST_DEF_DICNT0},
- .runFlag = (UDMA_TEST_RF_SOC_ALL | UDMA_TEST_RF_CORE_ALL | UDMA_TEST_RF_CFG_ALL),
+ .runFlag = (UDMA_TEST_RF_SOC_ALL | UDMA_TEST_RF_CORE_ALL | UDMA_TEST_RF_CFG_DEF | UDMA_TEST_RF_CFG_DYN),
.ringPrmId = UDMA_TEST_RING_PRMID_EVENT_POLLED,
},
{
.heapIdDest = {DEF_HEAP_ID},
.srcBufSize = {UDMA_TEST_DEF_ICNT0},
.destBufSize= {UDMA_TEST_DEF_DICNT0},
- .runFlag = (UDMA_TEST_RF_SOC_ALL | UDMA_TEST_RF_CORE_ALL | UDMA_TEST_RF_CFG_ALL),
+ .runFlag = (UDMA_TEST_RF_SOC_ALL | UDMA_TEST_RF_CORE_ALL | UDMA_TEST_RF_CFG_DEF | UDMA_TEST_RF_CFG_DYN),
.ringPrmId = UDMA_TEST_RING_PRMID_EVENT_POLLED,
},
{
.heapIdDest = {DEF_HEAP_ID},
.srcBufSize = {UDMA_TEST_DEF_ICNT0},
.destBufSize= {UDMA_TEST_DEF_DICNT0},
- .runFlag = (UDMA_TEST_RF_SOC_ALL | UDMA_TEST_RF_CORE_ALL | UDMA_TEST_RF_CFG_ALL),
+ .runFlag = (UDMA_TEST_RF_SOC_ALL | UDMA_TEST_RF_CORE_ALL | UDMA_TEST_RF_CFG_DEF | UDMA_TEST_RF_CFG_DYN),
.ringPrmId = UDMA_TEST_RING_PRMID_EVENT_POLLED,
},
{
.heapIdDest = {DEF_HEAP_ID},
.srcBufSize = {UDMA_TEST_DEF_ICNT0},
.destBufSize= {UDMA_TEST_DEF_DICNT0},
- .runFlag = (UDMA_TEST_RF_SOC_ALL | UDMA_TEST_RF_CORE_ALL | UDMA_TEST_RF_CFG_ALL),
+ .runFlag = (UDMA_TEST_RF_SOC_ALL | UDMA_TEST_RF_CORE_ALL | UDMA_TEST_RF_CFG_DEF | UDMA_TEST_RF_CFG_DYN),
.ringPrmId = UDMA_TEST_RING_PRMID_EVENT_NONE,
},
{
.heapIdDest = {DEF_HEAP_ID},
.srcBufSize = {UDMA_TEST_DEF_ICNT0},
.destBufSize= {UDMA_TEST_DEF_DICNT0},
- .runFlag = (UDMA_TEST_RF_SOC_AM65XX | UDMA_TEST_RF_CORE_ALL | UDMA_TEST_RF_CFG_ALL),
+ .runFlag = (UDMA_TEST_RF_SOC_AM65XX | UDMA_TEST_RF_CORE_ALL | UDMA_TEST_RF_CFG_DEF | UDMA_TEST_RF_CFG_DYN),
.ringPrmId = UDMA_TEST_RING_PRMID_EVENT_NONE,
},
{
.heapIdDest = {DEF_HEAP_ID},
.srcBufSize = {UDMA_TEST_DEF_ICNT0},
.destBufSize= {UDMA_TEST_DEF_DICNT0},
- .runFlag = (UDMA_TEST_RF_SOC_ALL | UDMA_TEST_RF_CORE_ALL | UDMA_TEST_RF_CFG_ALL),
+ .runFlag = (UDMA_TEST_RF_SOC_ALL | UDMA_TEST_RF_CORE_ALL | UDMA_TEST_RF_CFG_DEF | UDMA_TEST_RF_CFG_DYN),
.ringPrmId = UDMA_TEST_RING_PRMID_EVENT_NONE,
},
{
.heapIdDest = {DEF_HEAP_ID},
.srcBufSize = {UDMA_TEST_DEF_ICNT0},
.destBufSize= {UDMA_TEST_DEF_DICNT0},
- .runFlag = (UDMA_TEST_RF_SOC_J721E | UDMA_TEST_RF_CORE_ALL | UDMA_TEST_RF_CFG_ALL),
+ .runFlag = (UDMA_TEST_RF_SOC_J721E | UDMA_TEST_RF_CORE_ALL | UDMA_TEST_RF_CFG_DEF | UDMA_TEST_RF_CFG_DYN),
.ringPrmId = UDMA_TEST_RING_PRMID_EVENT_NONE,
},
{
.heapIdDest = {DEF_HEAP_ID},
.srcBufSize = {UDMA_TEST_DEF_ICNT0},
.destBufSize= {UDMA_TEST_DEF_DICNT0},
- .runFlag = (UDMA_TEST_RF_SOC_J721E | UDMA_TEST_RF_CORE_ALL | UDMA_TEST_RF_CFG_ALL),
+ .runFlag = (UDMA_TEST_RF_SOC_J721E | UDMA_TEST_RF_CORE_ALL | UDMA_TEST_RF_CFG_DEF | UDMA_TEST_RF_CFG_DYN),
.ringPrmId = UDMA_TEST_RING_PRMID_EVENT_NONE,
},
{
.heapIdDest = {DEF_HEAP_ID},
.srcBufSize = {UDMA_TEST_DEF_ICNT0},
.destBufSize= {UDMA_TEST_DEF_DICNT0},
- .runFlag = (UDMA_TEST_RF_SOC_J721E | UDMA_TEST_RF_CORE_ALL | UDMA_TEST_RF_CFG_ALL),
+ .runFlag = (UDMA_TEST_RF_SOC_J721E | UDMA_TEST_RF_CORE_ALL | UDMA_TEST_RF_CFG_DEF | UDMA_TEST_RF_CFG_DYN),
.ringPrmId = UDMA_TEST_RING_PRMID_EVENT_NONE,
},
{
.heapIdDest = {DEF_HEAP_ID},
.srcBufSize = {UDMA_TEST_DEF_ICNT0},
.destBufSize= {UDMA_TEST_DEF_DICNT0},
- .runFlag = (UDMA_TEST_RF_SOC_ALL | UDMA_TEST_RF_CORE_ALL | UDMA_TEST_RF_CFG_ALL),
+ .runFlag = (UDMA_TEST_RF_SOC_ALL | UDMA_TEST_RF_CORE_ALL | UDMA_TEST_RF_CFG_DEF | UDMA_TEST_RF_CFG_DYN),
.ringPrmId = UDMA_TEST_RING_PRMID_EVENT_NONE,
},
{
.heapIdDest = {DEF_HEAP_ID},
.srcBufSize = {UDMA_TEST_DEF_ICNT0},
.destBufSize= {UDMA_TEST_DEF_DICNT0},
- .runFlag = (UDMA_TEST_RF_FLOW),
+ .runFlag = (UDMA_TEST_RF_FLOW | UDMA_TEST_RF_CFG_DYN),
.ringPrmId = UDMA_TEST_RING_PRMID_EVENT_NONE,
},
{
.heapIdDest = {DEF_HEAP_ID},
.srcBufSize = {UDMA_TEST_DEF_ICNT0},
.destBufSize= {UDMA_TEST_DEF_DICNT0},
- .runFlag = (UDMA_TEST_RF_FLOW),
+ .runFlag = (UDMA_TEST_RF_FLOW | UDMA_TEST_RF_CFG_DYN),
.ringPrmId = UDMA_TEST_RING_PRMID_EVENT_NONE,
},
{
.heapIdDest = {DEF_HEAP_ID},
.srcBufSize = {UDMA_TEST_DEF_ICNT0},
.destBufSize= {UDMA_TEST_DEF_DICNT0},
- .runFlag = (UDMA_TEST_RF_SOC_ALL | UDMA_TEST_RF_CORE_ALL | UDMA_TEST_RF_CFG_ALL),
+ .runFlag = (UDMA_TEST_RF_SOC_ALL | UDMA_TEST_RF_CORE_ALL | UDMA_TEST_RF_CFG_DEF),
.ringPrmId = UDMA_TEST_RING_PRMID_INVALID,
},
{
.heapIdDest = {DEF_HEAP_ID},
.srcBufSize = {UDMA_TEST_DEF_ICNT0},
.destBufSize= {UDMA_TEST_DEF_DICNT0},
- .runFlag = (UDMA_TEST_RF_SOC_ALL | UDMA_TEST_RF_CORE_ALL | UDMA_TEST_RF_CFG_ALL),
+ .runFlag = (UDMA_TEST_RF_SOC_ALL | UDMA_TEST_RF_CORE_ALL | UDMA_TEST_RF_CFG_DEF | UDMA_TEST_RF_CFG_DYN),
.ringPrmId = UDMA_TEST_RING_PRMID_INVALID,
},
{
.heapIdDest = {DEF_HEAP_ID},
.srcBufSize = {UDMA_TEST_DEF_ICNT0},
.destBufSize= {UDMA_TEST_DEF_DICNT0},
- .runFlag = (UDMA_TEST_RF_SOC_ALL | UDMA_TEST_RF_CORE_ALL | UDMA_TEST_RF_CFG_ALL),
+ .runFlag = (UDMA_TEST_RF_SOC_ALL | UDMA_TEST_RF_CORE_ALL | UDMA_TEST_RF_CFG_DEF | UDMA_TEST_RF_CFG_DYN),
.ringPrmId = UDMA_TEST_RING_PRMID_INVALID,
},
{
.heapIdDest = {DEF_HEAP_ID},
.srcBufSize = {UDMA_TEST_DEF_ICNT0},
.destBufSize= {UDMA_TEST_DEF_DICNT0},
- .runFlag = (UDMA_TEST_RF_SOC_ALL | UDMA_TEST_RF_CORE_ALL | UDMA_TEST_RF_CFG_ALL),
+ .runFlag = (UDMA_TEST_RF_SOC_ALL | UDMA_TEST_RF_CORE_ALL | UDMA_TEST_RF_CFG_DEF),
.ringPrmId = UDMA_TEST_RING_PRMID_INVALID,
},
{
.heapIdDest = {DEF_HEAP_ID},
.srcBufSize = {UDMA_TEST_DEF_ICNT0},
.destBufSize= {UDMA_TEST_DEF_DICNT0},
- .runFlag = (UDMA_TEST_RF_SOC_ALL | UDMA_TEST_RF_CORE_ALL | UDMA_TEST_RF_CFG_ALL),
+ .runFlag = (UDMA_TEST_RF_SOC_ALL | UDMA_TEST_RF_CORE_ALL | UDMA_TEST_RF_CFG_DEF | UDMA_TEST_RF_CFG_DYN),
.ringPrmId = UDMA_TEST_RING_PRMID_EVENT_NONE,
},
{
.heapIdDest = {DEF_HEAP_ID},
.srcBufSize = {UDMA_TEST_DEF_ICNT0},
.destBufSize= {UDMA_TEST_DEF_DICNT0},
- .runFlag = (UDMA_TEST_RF_SOC_ALL | UDMA_TEST_RF_CORE_ALL | UDMA_TEST_RF_CFG_ALL),
+ .runFlag = (UDMA_TEST_RF_SOC_ALL | UDMA_TEST_RF_CORE_ALL | UDMA_TEST_RF_CFG_DEF | UDMA_TEST_RF_CFG_DYN),
.ringPrmId = UDMA_TEST_RING_PRMID_INVALID,
},
{
.heapIdDest = {DEF_HEAP_ID},
.srcBufSize = {UDMA_TEST_DEF_ICNT0},
.destBufSize= {UDMA_TEST_DEF_DICNT0},
- .runFlag = (UDMA_TEST_RF_MAIN_BC_PAUSE),
+ .runFlag = (UDMA_TEST_RF_MAIN_BC_PAUSE | UDMA_TEST_RF_CFG_DYN),
.ringPrmId = UDMA_TEST_RING_PRMID_INVALID,
},
{
.heapIdDest = {DEF_HEAP_ID},
.srcBufSize = {UDMA_TEST_DEF_ICNT0},
.destBufSize= {UDMA_TEST_DEF_DICNT0},
- .runFlag = (UDMA_TEST_RF_SOC_ALL | UDMA_TEST_RF_CORE_ALL | UDMA_TEST_RF_CFG_ALL),
+ .runFlag = (UDMA_TEST_RF_SOC_ALL | UDMA_TEST_RF_CORE_ALL | UDMA_TEST_RF_CFG_DEF | UDMA_TEST_RF_CFG_DYN),
.ringPrmId = UDMA_TEST_RING_PRMID_INVALID,
},
};
diff --git a/packages/ti/drv/udma/unit_test/udma_ut/src/utils_mem.c b/packages/ti/drv/udma/unit_test/udma_ut/src/utils_mem.c
gUtilsHeapMemHandle[UTILS_MEM_HEAP_ID_INTERNAL] = NULL;
HeapMem_destruct(&gUtilsHeapMemStruct[UTILS_MEM_HEAP_ID_OSPI]);
gUtilsHeapMemHandle[UTILS_MEM_HEAP_ID_OSPI] = NULL;
-
return (UDMA_SOK);
}
}
/* allocate memory */
- addr = HeapMem_alloc(gUtilsHeapMemHandle[heapId], size, align, NULL);
+ addr = HeapMem_alloc(gUtilsHeapMemHandle[heapId], size, align, NULL);
if((addr != NULL) && (TRUE == gUtilsMemClearBuf))
{
memset(addr, 0U, size);
HeapMem_getStats(gUtilsHeapMemHandle[heapId], &stats);
totalFreeSize = (uint32_t) stats.totalFreeSize;
}
-
return (totalFreeSize);
}
diff --git a/packages/ti/drv/udma/unit_test/udma_ut/src/utils_mem_baremetal.c b/packages/ti/drv/udma/unit_test/udma_ut/src/utils_mem_baremetal.c
--- /dev/null
@@ -0,0 +1,267 @@
+/*
+ * Copyright (c) Texas Instruments Incorporated 2018
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * \file utils_mem.c
+ *
+ * \brief Memory allocator API.
+ *
+ */
+
+/* ========================================================================== */
+/* Include Files */
+/* ========================================================================== */
+
+#include <string.h>
+#include <stdlib.h>
+#include "udma_test.h"
+
+/* ========================================================================== */
+/* Macros & Typedefs */
+/* ========================================================================== */
+
+/** \brief Utility define for Kilobyte, i.e 1024 bytes */
+#ifndef KB
+#define KB ((uint32_t) 1024U)
+#endif
+
+/** \brief Utility define for Megabyte, i.e 1024*1024 bytes */
+#ifndef MB
+#define MB (KB * KB)
+#endif
+
+#define UTILS_MEM_HEAP_SIZE_MSMC (300U * KB)
+#define UTILS_MEM_HEAP_SIZE_DDR (64U * MB)
+#if defined (__TI_ARM_V7R4__)
+/* R5 OCMC (MSRAM) */
+#define UTILS_MEM_HEAP_SIZE_INTERNAL (32U * KB)
+#else
+#define UTILS_MEM_HEAP_SIZE_INTERNAL (100U * KB)
+#endif
+#define UTILS_MEM_HEAP_SIZE_OSPI (16U * MB)
+
+/* Macro to align x to y */
+#define align(x,y) ((x + y - 1) & (~(y - 1)))
+
+/* ========================================================================== */
+/* Structure Declarations */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/* Function Declarations */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/* Global Variables */
+/* ========================================================================== */
+
+static uint8_t gUtilsHeapMemMsmc[UTILS_MEM_HEAP_SIZE_MSMC] __attribute__(( aligned(128), section(".udma_buffer_msmc") ));
+static uint8_t gUtilsHeapMemDdr[UTILS_MEM_HEAP_SIZE_DDR] __attribute__(( aligned(128), section(".udma_buffer_ddr") ));
+static uint8_t gUtilsHeapMemInternal[UTILS_MEM_HEAP_SIZE_INTERNAL] __attribute__(( aligned(128), section(".udma_buffer_internal") ));
+static uint8_t gUtilsHeapMemOspi[UTILS_MEM_HEAP_SIZE_OSPI] __attribute__(( aligned(128), section(".udma_buffer_ospi") ));
+
+uint8_t *fw_mem_start[UTILS_MEM_HEAP_NUM];
+uint8_t *fw_mem_end[UTILS_MEM_HEAP_NUM];
+uint8_t *fw_mem_alloc_ptr[UTILS_MEM_HEAP_NUM];
+uint8_t fw_mem_wraparound[UTILS_MEM_HEAP_NUM];
+
+static uint32_t gUtilsMemClearBuf = FALSE;
+
+/* ========================================================================== */
+/* Function Definitions */
+/* ========================================================================== */
+
+int32_t Utils_memInit(void)
+{
+ fw_mem_start[0] = (uint8_t*) gUtilsHeapMemMsmc;
+ fw_mem_end[0] = (uint8_t*)(&gUtilsHeapMemMsmc[UTILS_MEM_HEAP_SIZE_MSMC-1U]);
+ fw_mem_alloc_ptr[0] = (uint8_t*) gUtilsHeapMemMsmc;
+ fw_mem_wraparound[0]= FALSE;
+ fw_mem_start[1] = (uint8_t*) gUtilsHeapMemDdr;
+ fw_mem_end[1] = (uint8_t*)(&gUtilsHeapMemDdr[UTILS_MEM_HEAP_SIZE_DDR-1U]);
+ fw_mem_alloc_ptr[1] = (uint8_t*) gUtilsHeapMemDdr;
+ fw_mem_wraparound[1]= FALSE;
+ fw_mem_start[2] = (uint8_t*) gUtilsHeapMemInternal;
+ fw_mem_end[2] = (uint8_t*)(&gUtilsHeapMemInternal[UTILS_MEM_HEAP_SIZE_INTERNAL-1U]);
+ fw_mem_alloc_ptr[2] = (uint8_t*) gUtilsHeapMemInternal;
+ fw_mem_wraparound[2]= FALSE;
+ fw_mem_start[3] = (uint8_t*) gUtilsHeapMemOspi;
+ fw_mem_end[3] = (uint8_t*)(&gUtilsHeapMemOspi[UTILS_MEM_HEAP_SIZE_OSPI-1U]);
+ fw_mem_alloc_ptr[3] = (uint8_t*) gUtilsHeapMemOspi;
+ fw_mem_wraparound[3]= FALSE;
+
+ gUtilsMemClearBuf = TRUE;
+
+ return (UDMA_SOK);
+}
+
+int32_t Utils_memDeInit(void)
+{
+ return (UDMA_SOK);
+}
+
+void *Utils_alignedMalloc(uint32_t heapId, uint32_t size, uint32_t alignment)
+{
+ uint8_t *alloc_ptr;
+ void *p_block = (void *) NULL;
+
+ alloc_ptr = (uint8_t*)align((uintptr_t)fw_mem_alloc_ptr[heapId], alignment);
+
+ if ((alloc_ptr + size) < fw_mem_end[heapId])
+ {
+ p_block =(void *)alloc_ptr;
+ fw_mem_alloc_ptr[heapId] = alloc_ptr + size;
+ }
+ else
+ {
+ /* wraparound happened. */
+ fw_mem_wraparound[heapId] = TRUE;
+ fw_mem_alloc_ptr[heapId] = fw_mem_start[heapId];
+ alloc_ptr = (uint8_t*)align((uintptr_t)fw_mem_alloc_ptr[heapId], alignment);
+ p_block =(void *)alloc_ptr;
+ fw_mem_alloc_ptr[heapId] = alloc_ptr + size;
+ }
+
+ return p_block;
+}
+
+void Utils_alignedFree(void *p, uint32_t size )
+{
+ /* Nothing to be done here */
+}
+
+void *Utils_memAlloc(uint32_t heapId, uint32_t size, uint32_t align)
+{
+ void *addr;
+
+ GT_assert(UdmaUtTrace, heapId < UTILS_MEM_HEAP_NUM);
+
+ /* Heap alloc need some minimum allocation size */
+ if(size < UDMA_CACHELINE_ALIGNMENT)
+ {
+ size = UDMA_CACHELINE_ALIGNMENT;
+ }
+
+ /* allocate memory */
+ addr = Utils_alignedMalloc(heapId, size, align);
+ if((addr != NULL) && (TRUE == gUtilsMemClearBuf))
+ {
+ memset(addr, 0U, size);
+ /* Flush and invalidate the CPU write */
+ Udma_appUtilsCacheWbInv(addr, size);
+ }
+
+ return (addr);
+}
+
+int32_t Utils_memFree(uint32_t heapId, void *addr, uint32_t size)
+{
+ GT_assert(UdmaUtTrace, heapId < UTILS_MEM_HEAP_NUM);
+
+ /* Heap alloc need some minimum allocation size */
+ if(size < UDMA_CACHELINE_ALIGNMENT)
+ {
+ size = UDMA_CACHELINE_ALIGNMENT;
+ }
+ /* free previously allocated memory */
+ Utils_alignedFree(addr, size);
+ return (UDMA_SOK);
+}
+
+int32_t Utils_memClearOnAlloc(Bool enable)
+{
+ gUtilsMemClearBuf = enable;
+
+ return (UDMA_SOK);
+}
+
+void Utils_memGetHeapStat(Utils_MemHeapStatus *heapStat)
+{
+ uint32_t idx;
+
+ /* NULL pointer check */
+ GT_assert(UdmaUtTrace, NULL != heapStat);
+
+ heapStat->freeSysHeapSize = Utils_memGetSystemHeapFreeSpace();
+ for(idx = 0U; idx < UTILS_MEM_HEAP_NUM; idx++)
+ {
+ heapStat->freeBufHeapSize[idx] = Utils_memGetBufferHeapFreeSpace(idx);
+ }
+
+ return;
+}
+
+int32_t Utils_memCheckHeapStat(const Utils_MemHeapStatus *heapStat)
+{
+ int32_t retVal = UDMA_SOK;
+ uint32_t idx;
+ Utils_MemHeapStatus curStat;
+
+ /* NULL pointer check */
+ GT_assert(UdmaUtTrace, NULL != heapStat);
+
+ Utils_memGetHeapStat(&curStat);
+
+ if(heapStat->freeSysHeapSize != curStat.freeSysHeapSize)
+ {
+ GT_1trace(UdmaUtTrace, GT_CRIT,
+ "Warning: Memory leak (%d bytes) in System Heap!!\r\n",
+ (heapStat->freeSysHeapSize - curStat.freeSysHeapSize));
+ retVal = UDMA_EFAIL;
+ }
+ for(idx = 0U; idx < UTILS_MEM_HEAP_NUM; idx++)
+ {
+ if(heapStat->freeBufHeapSize[idx] != curStat.freeBufHeapSize[idx])
+ {
+ GT_1trace(UdmaUtTrace, GT_CRIT,
+ "Warning: Memory leak (%d bytes) in Buffer Heap!!\r\n",
+ (heapStat->freeBufHeapSize[idx] - curStat.freeBufHeapSize[idx]));
+ retVal = UDMA_EFAIL;
+ }
+ }
+
+ return (retVal);
+}
+
+uint32_t Utils_memGetSystemHeapFreeSpace(void)
+{
+ return ((UInt32) 1U);
+}
+
+uint32_t Utils_memGetBufferHeapFreeSpace(uint32_t heapId)
+{
+ return ((UInt32) 0U);
+}
diff --git a/packages/ti/drv/udma/unit_test/udma_ut/src/utils_prf_baremetal.c b/packages/ti/drv/udma/unit_test/udma_ut/src/utils_prf_baremetal.c
--- /dev/null
@@ -0,0 +1,407 @@
+/* =============================================================================
+ * Copyright (c) Texas Instruments Incorporated 2012-2017
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * \file utils_prf_baremetal.c
+ *
+ * \brief Profiling API utility file for baremetal.
+ *
+ */
+
+/* ========================================================================== */
+/* Include Files */
+/* ========================================================================== */
+
+#include <string.h>
+#include <ti/osal/osal.h>
+#include "udma_test.h"
+
+/* ========================================================================== */
+/* Macros & Typedefs */
+/* ========================================================================== */
+/* None */
+
+/* ========================================================================== */
+/* Structure Declarations */
+/* ========================================================================== */
+
+typedef struct
+{
+ Bool isAlloc;
+ Char name[32];
+ TaskP_Handle pTsk;
+ UInt64 totalTskThreadTime;
+} Utils_PrfLoadObj;
+
+typedef struct
+{
+ Utils_PrfTsHndl tsObj[UTILS_PRF_MAX_HNDL];
+ Utils_PrfLoadObj loadObj[UTILS_PRF_MAX_HNDL];
+} Utils_PrfObj;
+
+typedef struct
+{
+ UInt64 totalSwiThreadTime;
+ UInt64 totalHwiThreadTime;
+ UInt64 totalTime;
+ UInt64 totalIdlTskTime;
+} Utils_AccPrfLoadObj;
+
+/* ========================================================================== */
+/* Function Declarations */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/* Global Variables */
+/* ========================================================================== */
+
+static Utils_PrfObj gUtils_prfObj;
+static Utils_AccPrfLoadObj gUtils_accPrfLoadObj;
+
+/* ========================================================================== */
+/* Function Definitions */
+/* ========================================================================== */
+
+Int32 Utils_prfInit(void)
+{
+ memset(&gUtils_prfObj, 0, sizeof (gUtils_prfObj));
+ memset(&gUtils_accPrfLoadObj, 0, sizeof (Utils_AccPrfLoadObj));
+
+ return (0);
+}
+
+Int32 Utils_prfDeInit(void)
+{
+ return (0);
+}
+
+Utils_PrfTsHndl *Utils_prfTsCreate(const Char *name)
+{
+ UInt32 hndlId;
+ UInt32 cookie;
+ Utils_PrfTsHndl *pHndl = NULL;
+
+ cookie = HwiP_disable();
+
+ for (hndlId = 0; hndlId < UTILS_PRF_MAX_HNDL; hndlId++)
+ {
+ pHndl = &gUtils_prfObj.tsObj[hndlId];
+
+ if (FALSE == pHndl->isAlloc)
+ {
+ /* One less for NULL character */
+ strncpy(pHndl->name, name, ((UInt32) sizeof (pHndl->name) - 1U));
+ pHndl->name[sizeof (pHndl->name) - 1U] = (UInt8) '\0';
+ pHndl->isAlloc = (Bool) TRUE;
+ Utils_prfTsReset(pHndl);
+ break;
+ }
+ }
+
+ HwiP_restore(cookie);
+
+ return (pHndl);
+}
+
+Int32 Utils_prfTsDelete(Utils_PrfTsHndl *pHndl)
+{
+ pHndl->isAlloc = (Bool) FALSE;
+ return (0);
+}
+
+UInt64 Utils_prfTsBegin(Utils_PrfTsHndl *pHndl)
+{
+ pHndl->startTs = Utils_prfTsGet64();
+
+ return (pHndl->startTs);
+}
+
+UInt64 Utils_prfTsEnd(Utils_PrfTsHndl *pHndl, UInt32 numFrames)
+{
+ return (Utils_prfTsDelta(pHndl, pHndl->startTs, numFrames));
+}
+
+UInt64 Utils_prfTsDelta(Utils_PrfTsHndl *pHndl,
+ UInt64 startTime,
+ UInt32 numFrames)
+{
+ UInt64 endTs;
+ UInt32 cookie;
+
+ endTs = Utils_prfTsGet64();
+
+ cookie = HwiP_disable();
+
+ pHndl->totalTs += (endTs - pHndl->startTs);
+ pHndl->count++;
+ pHndl->numFrames += numFrames;
+
+ HwiP_restore(cookie);
+
+ return (endTs);
+}
+
+Int32 Utils_prfTsReset(Utils_PrfTsHndl *pHndl)
+{
+ UInt32 cookie;
+
+ cookie = HwiP_disable();
+
+ pHndl->totalTs = 0;
+ pHndl->count = 0;
+ pHndl->numFrames = 0;
+
+ HwiP_restore(cookie);
+
+ return (0);
+}
+
+UInt64 Utils_prfTsGet64(void)
+{
+ UInt64 curTs = (UInt64) 0U;
+ return (curTs);
+}
+
+Int32 Utils_prfTsPrint(Utils_PrfTsHndl *pHndl, uint32_t resetAfterPrint, uint32_t trace)
+{
+ UInt32 cpuKhz;
+ UInt32 timeMs, fps, fpc;
+ cpuKhz = 24000U;
+
+
+ timeMs = pHndl->totalTs / cpuKhz;
+
+ if(0U == timeMs)
+ {
+ fps = 0U;
+ }
+ else
+ {
+ fps = (pHndl->numFrames * (UInt32) 1000U) / timeMs;
+ }
+ if(0U == pHndl->count)
+ {
+ fpc = 0U;
+ }
+ else
+ {
+ fpc = pHndl->numFrames / pHndl->count;
+ }
+
+ GT_7trace(
+ trace, GT_INFO,
+ " %d: PRF : %s : t: %d ms, count: %d, frames: %d, fps: %d, fpc: %d \r\n",
+ AppUtils_getCurTimeInMsec(),
+ pHndl->name,
+ timeMs, /* in msecs */
+ pHndl->count,
+ pHndl->numFrames,
+ fps, /* frames per second */
+ fpc /* frames per count */
+ );
+
+ if (resetAfterPrint)
+ {
+ Utils_prfTsReset(pHndl);
+ }
+
+ return (0);
+}
+
+Int32 Utils_prfTsPrintAll(uint32_t resetAfterPrint, uint32_t trace)
+{
+ UInt32 hndlId;
+ Utils_PrfTsHndl *pHndl;
+
+ GT_0trace(trace, GT_INFO, "\r\n");
+
+ for (hndlId = 0; hndlId < UTILS_PRF_MAX_HNDL; hndlId++)
+ {
+ pHndl = &gUtils_prfObj.tsObj[hndlId];
+
+ if (TRUE == pHndl->isAlloc)
+ {
+ Utils_prfTsPrint(pHndl, resetAfterPrint, trace);
+ }
+ }
+
+ GT_0trace(trace, GT_INFO, "\r\n");
+
+ return (0);
+}
+
+Int32 Utils_prfLoadRegister(TaskP_Handle pTsk, const Char *name)
+{
+ UInt32 hndlId;
+ UInt32 cookie;
+ Int32 status = CSL_EFAIL;
+ Utils_PrfLoadObj *pHndl;
+
+ cookie = HwiP_disable();
+
+ for (hndlId = 0; hndlId < UTILS_PRF_MAX_HNDL; hndlId++)
+ {
+ pHndl = &gUtils_prfObj.loadObj[hndlId];
+
+ if (FALSE == pHndl->isAlloc)
+ {
+ pHndl->isAlloc = (Bool) TRUE;
+ pHndl->pTsk = pTsk;
+ /* One less for NULL character */
+ strncpy(pHndl->name, name, ((UInt32) sizeof (pHndl->name) - 1U));
+ pHndl->name[sizeof (pHndl->name) - 1U] = (UInt8) '\0';
+ status = CSL_SOK;
+ break;
+ }
+ }
+
+ HwiP_restore(cookie);
+
+ return (status);
+}
+
+Int32 Utils_prfLoadUnRegister(TaskP_Handle pTsk)
+{
+ UInt32 hndlId;
+ UInt32 cookie;
+ Int32 status = CSL_EFAIL;
+ Utils_PrfLoadObj *pHndl;
+
+ cookie = HwiP_disable();
+
+ for (hndlId = 0; hndlId < UTILS_PRF_MAX_HNDL; hndlId++)
+ {
+ pHndl = &gUtils_prfObj.loadObj[hndlId];
+
+ if ((TRUE == pHndl->isAlloc) && (pHndl->pTsk == pTsk))
+ {
+ pHndl->isAlloc = (Bool) FALSE;
+ status = CSL_SOK;
+ break;
+ }
+ }
+
+ HwiP_restore(cookie);
+
+ return (status);
+}
+
+Int32 Utils_prfLoadPrintAll(uint32_t printTskLoad, uint32_t trace)
+{
+ UInt32 hwiLoad, swiLoad, tskLoad, hndlId, cpuLoad;
+ Utils_PrfLoadObj *pHndl;
+
+ hwiLoad = (UInt32) ((gUtils_accPrfLoadObj.totalHwiThreadTime *
+ (UInt64) 100U) / gUtils_accPrfLoadObj.totalTime);
+ swiLoad = (UInt32) ((gUtils_accPrfLoadObj.totalSwiThreadTime *
+ (UInt64) 100U) / gUtils_accPrfLoadObj.totalTime);
+ cpuLoad = (UInt32) 100U -
+ (UInt32) ((gUtils_accPrfLoadObj.totalIdlTskTime *
+ (UInt64) 100U) /
+ gUtils_accPrfLoadObj.totalTime);
+
+ GT_0trace(trace, GT_INFO, "\r\n");
+ GT_4trace(trace, GT_INFO,
+ " %d: LOAD: CPU: %d%%, HWI: %d%%, SWI:%d%% \r\n",
+ AppUtils_getCurTimeInMsec(),
+ cpuLoad,
+ hwiLoad,
+ swiLoad);
+
+ if (((Bool) TRUE) == printTskLoad)
+ {
+ for (hndlId = 0; hndlId < UTILS_PRF_MAX_HNDL; hndlId++)
+ {
+ pHndl = &gUtils_prfObj.loadObj[hndlId];
+
+ if (TRUE == pHndl->isAlloc)
+ {
+ tskLoad = (UInt32) ((pHndl->totalTskThreadTime *
+ (UInt64) 100U) /
+ gUtils_accPrfLoadObj.totalTime);
+
+ GT_3trace(trace, GT_INFO,
+ " %d: LOAD: TSK: %s: %d%% \r\n",
+ AppUtils_getCurTimeInMsec(),
+ pHndl->name,
+ tskLoad);
+ }
+ }
+ }
+
+ GT_0trace(trace, GT_INFO, "\r\n");
+
+ return (0);
+}
+
+void Utils_prfLoadCalcStart(void)
+{
+ return;
+}
+
+void Utils_prfLoadCalcStop(void)
+{
+ return;
+}
+
+void Utils_prfLoadCalcReset(void)
+{
+ UInt32 hndlId;
+ Utils_PrfLoadObj *pHndl;
+
+ gUtils_accPrfLoadObj.totalHwiThreadTime = 0;
+ gUtils_accPrfLoadObj.totalSwiThreadTime = 0;
+ gUtils_accPrfLoadObj.totalTime = 0;
+ gUtils_accPrfLoadObj.totalIdlTskTime = 0;
+
+ /* Reset the performace loads accumulator */
+ for (hndlId = 0; hndlId < UTILS_PRF_MAX_HNDL; hndlId++)
+ {
+ pHndl = &gUtils_prfObj.loadObj[hndlId];
+
+ if (((Bool) TRUE == pHndl->isAlloc) &&
+ (pHndl->pTsk != NULL))
+ {
+ pHndl->totalTskThreadTime = 0;
+ }
+ }
+
+ return;
+}
+
+/* Function called by Loadupdate for each update cycle */
+void Utils_prfLoadUpdate(void)
+{
+ return;
+}
diff --git a/packages/ti/drv/udma/unit_test/udma_ut_component.mk b/packages/ti/drv/udma/unit_test/udma_ut_component.mk
# udma unit test app
export udma_unit_testapp_COMP_LIST = udma_unit_testapp
-udma_unit_testapp_RELPATH = ti/drv/udma/unit_test/udma_ut/rtos
-udma_unit_testapp_PATH = $(PDK_UDMA_COMP_PATH)/unit_test/udma_ut/rtos
+udma_unit_testapp_RELPATH = ti/drv/udma/unit_test/udma_ut
+udma_unit_testapp_PATH = $(PDK_UDMA_COMP_PATH)/unit_test/udma_ut
export udma_unit_testapp_MAKEFILE = -fmakefile
export udma_unit_testapp_BOARD_DEPENDENCY = yes
export udma_unit_testapp_CORE_DEPENDENCY = yes
# udma unit test app - with user input
export udma_user_input_unit_testapp_COMP_LIST = udma_user_input_unit_testapp
-udma_user_input_unit_testapp_RELPATH = ti/drv/udma/unit_test/udma_ut/rtos
-udma_user_input_unit_testapp_PATH = $(PDK_UDMA_COMP_PATH)/unit_test/udma_ut/rtos
+udma_user_input_unit_testapp_RELPATH = ti/drv/udma/unit_test/udma_ut
+udma_user_input_unit_testapp_PATH = $(PDK_UDMA_COMP_PATH)/unit_test/udma_ut
export udma_user_input_unit_testapp_MAKEFILE = -fmakefile UDMA_UT_MANUAL_ENTRY=yes
export udma_user_input_unit_testapp_BOARD_DEPENDENCY = yes
export udma_user_input_unit_testapp_CORE_DEPENDENCY = yes
export udma_user_input_unit_testapp_SBL_APPIMAGEGEN = yes
udma_ut_EXAMPLE_LIST += udma_user_input_unit_testapp
+# udma unit test app
+export udma_baremetal_unit_testapp_COMP_LIST = udma_baremetal_unit_testapp
+udma_baremetal_unit_testapp_RELPATH = ti/drv/udma/unit_test/udma_ut
+udma_baremetal_unit_testapp_PATH = $(PDK_UDMA_COMP_PATH)/unit_test/udma_ut
+export udma_baremetal_unit_testapp_MAKEFILE = -fmakefile UDMA_UT_BAREMETAL=yes
+export udma_baremetal_unit_testapp_BOARD_DEPENDENCY = yes
+export udma_baremetal_unit_testapp_CORE_DEPENDENCY = yes
+export udma_baremetal_unit_testapp_XDC_CONFIGURO = no
+udma_baremetal_unit_testapp_PKG_LIST = udma_baremetal_unit_testapp
+udma_baremetal_unit_testapp_INCLUDE = $(udma_baremetal_unit_testapp_PATH)
+export udma_baremetal_unit_testapp_BOARDLIST = $(drvudma_BOARDLIST)
+ifeq ($(SOC),$(filter $(SOC), j721e))
+export udma_baremetal_unit_testapp_$(SOC)_CORELIST = mpu1_0 mcu1_0 mcu2_0 mcu2_1 mcu3_0 mcu3_1 c66xdsp_1 c66xdsp_2 c7x_1
+else
+export udma_baremetal_unit_testapp_$(SOC)_CORELIST = mpu1_0 mcu1_0
+endif
+export udma_baremetal_unit_testapp_SBL_APPIMAGEGEN = yes
+udma_ut_EXAMPLE_LIST += udma_baremetal_unit_testapp
+
+# udma unit test app - for dynamic analysis
+export udma_dynamic_unit_testapp_COMP_LIST = udma_dynamic_unit_testapp
+udma_dynamic_unit_testapp_RELPATH = ti/drv/udma/unit_test/udma_ut
+udma_dynamic_unit_testapp_PATH = $(PDK_UDMA_COMP_PATH)/unit_test/udma_ut
+export udma_dynamic_unit_testapp_MAKEFILE = -fmakefile UDMA_UT_DYNAMIC_ANALYSIS=yes
+export udma_dynamic_unit_testapp_BOARD_DEPENDENCY = yes
+export udma_dynamic_unit_testapp_CORE_DEPENDENCY = yes
+export udma_dynamic_unit_testapp_XDC_CONFIGURO = no
+udma_dynamic_unit_testapp_PKG_LIST = udma_dynamic_unit_testapp
+udma_dynamic_unit_testapp_INCLUDE = $(udma_dynamic_unit_testapp_PATH)
+export udma_dynamic_unit_testapp_BOARDLIST = $(drvudma_BOARDLIST)
+ifeq ($(SOC),$(filter $(SOC), j721e))
+export udma_dynamic_unit_testapp_$(SOC)_CORELIST = mcu1_0 mcu2_1
+else
+export udma_dynamic_unit_testapp_$(SOC)_CORELIST = mcu1_0
+endif
+export udma_dynamic_unit_testapp_SBL_APPIMAGEGEN = yes
+udma_ut_EXAMPLE_LIST += udma_dynamic_unit_testapp
+
export udma_ut_LIB_LIST
export udma_ut_EXAMPLE_LIST
index 0031e0bc875655a997eb396d0b76f0e49de422fd..cc38d141c60eba4bf56e826cc3ab9075c35184d1 100644 (file)
#include <stdbool.h>
#include <stddef.h>
+/**
+ * @brief This enumerator defines the cache coherent or not
+ *
+ *
+ */
+typedef uint32_t Osal_CacheP_isCoherent;
+ /** Cache is coherent on this CPU */
+#define OSAL_CACHEP_COHERENT ((uint32_t) 0U)
+ /**Cache is not coherent on this CPU */
+#define OSAL_CACHEP_NOT_COHERENT ((uint32_t) 1U)
/*!
* @brief Function to write back cache lines
*/
extern void CacheP_wbInv(const void * addr, int32_t size);
+/*!
+ * @brief Function to call before handing over the memory buffer to DMA from CPU
+ *
+ * @param addr Start address of the cache line/s
+ *
+ * @param size size (in bytes) of the memory to be written back and invalidate
+ *
+ * @param isCoherent if the cache is coherent on that CPU or not
+ *
+ */
+void CacheP_fenceCpu2Dma(uintptr_t addr, uint32_t size, Osal_CacheP_isCoherent isCoherent);
+
+/*!
+ * @brief Function to call before reading the memory to CPU after DMA operations
+ *
+ * @param addr Start address of the cache line/s
+ *
+ * @param size size (in bytes) of the memory to be written back and invalidate
+ *
+ * @param isCoherent if the cache is coherent on that CPU or not @ref Osal_CacheP_isCoherent
+ *
+ */
+void CacheP_fenceDma2Cpu(uintptr_t addr, uint32_t size, Osal_CacheP_isCoherent isCoherent);
+
#ifdef __cplusplus
}
#endif
index ad27a3c0aec2aba8807cae9b8823c52e3cc77da3..206d13337dd1843b1c4a80ebb0375fb9d880d4c6 100644 (file)
#include <stdbool.h>
#include <stdlib.h>
#include <string.h>
-#include <xdc/std.h>
#include <ti/osal/osal.h>
#if defined(gnu_targets_arm_A15F)
return ((int32_t)CSL_a15ReadCoreId());
#else
- return 0;
+ return (osal_UNSUPPORTED);
#endif
}
+
+void CacheP_fenceCpu2Dma(uintptr_t addr, uint32_t size, Osal_CacheP_isCoherent isCoherent)
+{
+ /* CPU to DMA would be to do Wb call if it is not coherent */
+ if (isCoherent == OSAL_CACHEP_NOT_COHERENT)
+ {
+ CacheP_wb( (const void *) addr, size);
+ }
+}
+
+void CacheP_fenceDma2Cpu(uintptr_t addr, uint32_t size, Osal_CacheP_isCoherent isCoherent)
+{
+ /* DMA to CPU would be to do Cache inv call if it is not coherent */
+ if (isCoherent == OSAL_CACHEP_NOT_COHERENT)
+ {
+ CacheP_Inv( (const void *) addr, size);
+ }
+}
+/* Nothing past this point */
index 6a6303f9d3bf9795a6fd4d1bec941385f30bd387..548ce4295205c18a0d8b1d0d0bffb5cc679c9399 100644 (file)
-SRCDIR = . src/nonos
-INCDIR = . src/nonos
+SRCDIR = . src/nonos arch/core
+INCDIR = . src/nonos arch/core
-SRCS_COMMON += HwiP_nonos.c SwiP_nonos.c Utils_nonos.c SemaphoreP_nonos.c RegisterIntr_nonos.c
+SRCS_COMMON += HwiP_nonos.c SwiP_nonos.c Utils_nonos.c SemaphoreP_nonos.c RegisterIntr_nonos.c Core_utils.c
ifeq ($(SOC),$(filter $(SOC),am571x am572x am574x am335x am437x k2h k2k k2e k2l k2g c6678 c6657 omapl137 omapl138 am65xx j721e j7200))
SRCDIR += soc/$(SOC)