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raw | patch | inline | side by side (parent: 14c26e8)
raw | patch | inline | side by side (parent: 14c26e8)
| author | Jacob Stiffler <j-stiffler@ti.com> | |
| Fri, 1 Nov 2019 18:54:41 +0000 (14:54 -0400) | ||
| committer | Jacob Stiffler <j-stiffler@ti.com> | |
| Fri, 1 Nov 2019 18:54:41 +0000 (14:54 -0400) |
Development of gpio-lld has been relocated here from:
* Repo: https://git.ti.com/keystone-rtos/gpio-lld
* Branch: master
* Commit ID: c20a852ccdcfe127bdf9ce453dcd2edf2f709105
Signed-off-by: Jacob Stiffler <j-stiffler@ti.com>
* Repo: https://git.ti.com/keystone-rtos/gpio-lld
* Branch: master
* Commit ID: c20a852ccdcfe127bdf9ce453dcd2edf2f709105
Signed-off-by: Jacob Stiffler <j-stiffler@ti.com>
167 files changed:
diff --git a/packages/ti/drv/gpio/.gitignore b/packages/ti/drv/gpio/.gitignore
--- /dev/null
@@ -0,0 +1,27 @@
+*.swp
+*~
+.dlls
+.executables
+.interfaces
+.libraries
+.xdcenv.mak
+Settings.h
+Settings.xdc
+build/c66/
+build/k2[heklg]/
+build/am57*/
+build/am335x/
+build/am437x/
+build/m4/
+build/armv7/
+docs/Doxyfile
+docs/doxygen/
+example/led_blink/*/*/bios/src
+test/led_blink/*/*/bios/src
+gpiover.h
+lib/
+package.mak
+package/
+packages/
+*.o
+*.dep
diff --git a/packages/ti/drv/gpio/GPIO.h b/packages/ti/drv/gpio/GPIO.h
--- /dev/null
@@ -0,0 +1,391 @@
+/*
+ * Copyright (c) 2014-2015, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * \defgroup DRV_GPIO_MODULE GPIO Driver
+ *
+ * @{
+ */
+/* @} */
+
+/**
+ * \ingroup DRV_GPIO_MODULE
+ * \defgroup DRV_GPIO_API_MODULE GPIO Driver API
+ * GPIO driver interface
+ *
+ * @{
+ */
+
+/** ============================================================================
+ * @file GPIO.h
+ *
+ * @brief GPIO driver
+ *
+ * The GPIO header file should be included in an application as follows:
+ * @code
+ * #include <ti/drv/gpio/GPIO.h>
+ * @endcode
+ *
+ * # Operation #
+ *
+ * The GPIO module allows you to manage General Purpose I/O pins via
+ * simple and portable APIs. GPIO pin behaviour can be configured completely
+ * statically, or dynamically defined at runtime.
+ *
+ * The application is required to supply a device
+ * specific GPIOXXX_Config structure to the module. This structure
+ * communicates to the GPIO module how to configure the pins that will be used
+ * by the application (See the description of GPIO_PinConfig).
+ *
+ * The application is required to call GPIO_init(). This function will
+ * initialize all the GPIO pins defined in the GPIO_PinConfig table to the
+ * configurations specified. Once that is completed the other APIs can be
+ * used to access the pins.
+ *
+ * Asserts are used to verify that the driver has been initialized and
+ * to validate pin indexes within the various APIs.
+ *
+ * See the device specific GPIO header file for configuration details.
+ *
+ * ============================================================================
+ */
+
+#ifndef GPIO__H
+#define GPIO__H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/*!
+ * @brief GPIO pin configuration settings
+ *
+ * The upper 16 bits of the 32 bit PinConfig is reserved
+ * for pin configuration settings.
+ *
+ * The lower 16 bits are reserved for device-specific
+ * port/pin identifications
+ */
+typedef uint32_t GPIO_PinConfig;
+
+/*!
+ * @cond NODOC
+ * Internally used configuration bit access macros.
+ */
+#define GPIO_CFG_IO_MASK 0x00ff0000U
+#define GPIO_CFG_IO_LSB 16U
+#define GPIO_CFG_OUT_TYPE_MASK 0x00060000U
+#define GPIO_CFG_OUT_TYPE_LSB 17U
+#define GPIO_CFG_IN_TYPE_MASK 0x00060000U
+#define GPIO_CFG_IN_TYPE_LSB 17U
+#define GPIO_CFG_OUT_STRENGTH_MASK 0x00f00000U
+#define GPIO_CFG_OUT_STRENGTH_LSB 20U
+#define GPIO_CFG_INT_MASK 0x07000000U
+#define GPIO_CFG_INT_LSB 24U
+#define GPIO_CFG_OUT_BIT 19U
+
+
+
+/*! @endcond */
+
+/** @name GPIO_PinConfig pin direction configuration macros
+ * @{
+ */
+#define GPIO_CFG_OUTPUT (((uint32_t) 0) << GPIO_CFG_IO_LSB) /*! Pin is an output. */
+#define GPIO_CFG_OUT_STD (((uint32_t) 0) << GPIO_CFG_IO_LSB) /*! Output pin is not Open Drain */
+#define GPIO_CFG_OUT_OD_NOPULL (((uint32_t) 2) << GPIO_CFG_IO_LSB) /*! Output pin is Open Drain */
+#define GPIO_CFG_OUT_OD_PU (((uint32_t) 4) << GPIO_CFG_IO_LSB) /*! Output pin is Open Drain w/ pull up */
+#define GPIO_CFG_OUT_OD_PD (((uint32_t) 6) << GPIO_CFG_IO_LSB) /*! Output pin is Open Drain w/ pull dn */
+
+#define GPIO_CFG_OUT_HIGH (((uint32_t) 1) << GPIO_CFG_OUT_BIT) /*! Set pin's output to 1. */
+#define GPIO_CFG_OUT_LOW (((uint32_t) 0) << GPIO_CFG_OUT_BIT) /*! Set pin's output to 0. */
+
+#define GPIO_CFG_OUT_STR_LOW (((uint32_t) 0) << GPIO_CFG_OUT_STRENGTH_LSB)
+#define GPIO_CFG_OUT_STR_MED (((uint32_t) 1) << GPIO_CFG_OUT_STRENGTH_LSB)
+#define GPIO_CFG_OUT_STR_HIGH (((uint32_t) 2) << GPIO_CFG_OUT_STRENGTH_LSB)
+
+#define GPIO_CFG_INPUT (((uint32_t) 1) << GPIO_CFG_IO_LSB) /*! Pin is an input. */
+#define GPIO_CFG_IN_NOPULL (((uint32_t) 1) << GPIO_CFG_IO_LSB) /*! Input pin has no PU/PD */
+#define GPIO_CFG_IN_PU (((uint32_t) 3) << GPIO_CFG_IO_LSB) /*! Input pin has Pullup */
+#define GPIO_CFG_IN_PD (((uint32_t) 5) << GPIO_CFG_IO_LSB) /*! Input pin has Pulldown */
+/** @} */
+
+/** @name GPIO_PinConfig pin interrupt configuration macros
+ * @{
+ */
+#define GPIO_CFG_IN_INT_NONE (((uint32_t) 0) << GPIO_CFG_INT_LSB) /*! No Interrupt */
+#define GPIO_CFG_IN_INT_FALLING (((uint32_t) 1) << GPIO_CFG_INT_LSB) /*! Interrupt on falling edge */
+#define GPIO_CFG_IN_INT_RISING (((uint32_t) 2) << GPIO_CFG_INT_LSB) /*! Interrupt on rising edge */
+#define GPIO_CFG_IN_INT_BOTH_EDGES (((uint32_t) 3) << GPIO_CFG_INT_LSB) /*! Interrupt on both edges */
+#define GPIO_CFG_IN_INT_LOW (((uint32_t) 4) << GPIO_CFG_INT_LSB) /*! Interrupt on low level */
+#define GPIO_CFG_IN_INT_HIGH (((uint32_t) 5) << GPIO_CFG_INT_LSB) /*! Interrupt on high level */
+/** @} */
+
+/** @name Special GPIO_PinConfig configuration macros
+ * @{
+ */
+
+/*!
+ * \brief 'Or' in this GPIO_PinConfig definition to inform GPIO_setConfig()
+ * to only configure the interrupt attributes of a GPIO input pin.
+ */
+#define GPIO_CFG_IN_INT_ONLY (((uint32_t) 1) << 27) /*! configure interrupt only */
+
+/*!
+ * \brief Use this GPIO_PinConfig definition to inform GPIO_init()
+ * NOT to configure the corresponding pin
+ */
+#define GPIO_DO_NOT_CONFIG 0x7fff0001U /*! Do not configure this Pin */
+
+/** @} */
+
+/*!
+ * @brief GPIO callback function type
+ */
+typedef void (*GPIO_CallbackFxn)(void);
+
+/*!
+ * @brief Initializes the GPIO module
+ */
+typedef void (*GPIO_InitFxn) (void);
+
+/*!
+ * @brief Reads the value of a GPIO pin
+ */
+typedef uint32_t (*GPIO_ReadFxn) (uint32_t idx);
+
+/*!
+ * @brief Writes the value to a GPIO pin
+ */
+typedef void (*GPIO_WriteFxn) (uint32_t idx,
+ uint32_t value);
+
+/*!
+ * @brief Clear a GPIO pin interrupt flag
+ */
+typedef void (*GPIO_clearIntFxn) (uint32_t idx);
+
+/*!
+ * @brief Disable a GPIO pin interrupt
+ */
+typedef void (*GPIO_disableIntFxn) (uint32_t idx);
+
+/*!
+ * @brief Enable a GPIO pin interrupt
+ */
+typedef void (*GPIO_enableIntFxn) (uint32_t idx);
+
+/*!
+ * @brief Bind a callback function to a GPIO pin interrupt
+ */
+typedef void (*GPIO_setCallbackFxn) (uint32_t idx,
+ GPIO_CallbackFxn callback);
+
+/*!
+ * @brief Configure the gpio pin
+ */
+typedef void (*GPIO_setConfigFxn) (uint32_t idx,
+ GPIO_PinConfig pinConfig);
+/*!
+ * @brief Toggles the current state of a GPIO
+ *
+ * @param idx GPIO index
+ */
+typedef void (*GPIO_toggleFxn) (uint32_t idx);
+
+/*!
+ * @brief The definition of a GPIO function table that contains the
+ * required set of functions to control a specific GPIO driver
+ * implementation.
+ */
+ typedef struct GPIO_FxnTable_s {
+ /*! Function to initialize the given data object */
+ GPIO_InitFxn initFxn;
+ /*! Function to read from the specified peripheral */
+ GPIO_ReadFxn readFxn;
+ /*! Function to write from the specified peripheral */
+ GPIO_WriteFxn writeFxn;
+ /*! Function to clear a GPIO pin interrupt flag */
+ GPIO_clearIntFxn clearIntFxn;
+ /*! Function to disable a GPIO pin interrupt flag */
+ GPIO_disableIntFxn disableIntFxn;
+ /*! Function to enable a GPIO pin interrupt flag */
+ GPIO_enableIntFxn enableIntFxn;
+ /*! Function to bind a callback function to a GPIO pin interrupt */
+ GPIO_setCallbackFxn setCallbackFxn;
+ /*! Function to configure the gpio pin */
+ GPIO_setConfigFxn setConfigFxn;
+ /*! Function to toggles the current state of a GPIO */
+ GPIO_toggleFxn toggleFxn;
+
+} GPIO_FxnTable;
+
+
+/*! @brief GPIO Global configuration */
+typedef struct GPIO_Config_s {
+ /*! Pointer to a table of a driver-specific implementation of GPIO functions */
+ GPIO_FxnTable const *fxnTablePtr;
+
+ /*! Pointer to a driver specific data object */
+ void *object;
+
+ /*! Pointer to a driver specific hardware attributes structure */
+ void const *hwAttrs;
+} GPIO_Config;
+
+/* Avoid Misra warning "MISRA.DECL.ARRAY_SIZE" by pairing config array type
+ * with its array size to avoid externs with [] (no size) */
+#define GPIO_MAX_CONFIG_CNT (3U)
+typedef GPIO_Config GPIOConfigList[GPIO_MAX_CONFIG_CNT];
+
+/*!
+ * @brief Clear a GPIO pin interrupt flag
+ *
+ * Clears the GPIO interrupt for the specified index.
+ *
+ * Note: It is not necessary to call this API within a
+ * callback assigned to a pin.
+ *
+ * @param idx GPIO index
+ */
+extern void GPIO_clearInt(uint32_t idx);
+
+/*!
+ * @brief Disable a GPIO pin interrupt
+ *
+ * Disables interrupts for the specified GPIO index.
+ *
+ * @param idx GPIO index
+ */
+extern void GPIO_disableInt(uint32_t idx);
+
+/*!
+ * @brief Enable a GPIO pin interrupt
+ *
+ * Enables GPIO interrupts for the selected index to occur.
+ *
+ * Note: Prior to enabling a GPIO pin interrupt, make sure
+ * that a corresponding callback function has been provided.
+ * Use the GPIO_setCallback() API for this purpose at runtime.
+ * Alternatively, the callback function can be statically
+ * configured in the GPIO_CallbackFxn array provided.
+ *
+ * @param idx GPIO index
+ */
+extern void GPIO_enableInt(uint32_t idx);
+
+/*!
+ * @brief Initializes the GPIO module
+ *
+ * The pins defined in the application-provided *GPIOXXX_config* structure
+ * are initialized accordingly.
+ *
+ * @pre The GPIO_config structure must exist and be persistent before this
+ * function can be called. This function must also be called before
+ * any other GPIO driver APIs.
+ */
+extern void GPIO_init(void);
+
+/*!
+ * @brief Reads the value of a GPIO pin
+ *
+ * The value returned will either be zero or one depending on the
+ * state of the pin.
+ *
+ * @param idx GPIO index
+ *
+ * @return 0 or 1, depending on the state of the pin.
+ */
+extern uint32_t GPIO_read(uint32_t idx);
+
+/*!
+ * @brief Bind a callback function to a GPIO pin interrupt
+ *
+ * Associate a callback function with a particular GPIO pin interrupt.
+ *
+ * Callbacks can be changed at any time, making it easy to switch between
+ * efficient, state-specific interrupt handlers.
+ *
+ * Note: The callback function is called within the context of an interrupt
+ * handler.
+ *
+ * Note: This API does not enable the GPIO pin interrupt.
+ * Use GPIO_enableInt() and GPIO_disableInt() to enable
+ * and disable the pin interrupt as necessary.
+ *
+ * Note: it is not necessary to call GPIO_clearInt() within a callback.
+ * That operation is performed internally before the callback is invoked.
+ *
+ * @param idx GPIO index
+ * @param callback address of the callback function
+ */
+extern void GPIO_setCallback(uint32_t idx, GPIO_CallbackFxn callback);
+
+/*!
+ * @brief Configure the gpio pin
+ *
+ * Dynamically configure a gpio pin to a device specific setting.
+ * For many applications, the pin configurations provided in the static
+ * GPIO_PinConfig array is sufficient.
+ *
+ * For input pins with interrupt configurations, a corresponding interrupt
+ * object will be created as needed.
+ *
+ * @param idx GPIO index
+ * @param pinConfig device specific pin configuration settings
+ */
+extern void GPIO_setConfig(uint32_t idx, GPIO_PinConfig pinConfig);
+
+/*!
+ * @brief Toggles the current state of a GPIO
+ *
+ * @param idx GPIO index
+ */
+extern void GPIO_toggle(uint32_t idx);
+
+/*!
+ * @brief Writes the value to a GPIO pin
+ *
+ * @param idx GPIO index
+ * @param value must be either 0 or 1
+ */
+extern void GPIO_write(uint32_t idx, uint32_t value);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _GPIO_H */
+
+/* @} */
diff --git a/packages/ti/drv/gpio/GPIOver.h b/packages/ti/drv/gpio/GPIOver.h
--- /dev/null
@@ -0,0 +1,68 @@
+#ifndef _GPIOVER_H
+#define _GPIOVER_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* ============================================================= */
+/**
+ * @file GPIOver.h
+ *
+ * path ti/drv/gpio/GPIOver.h
+ *
+ * @brief gpio Driver Version Definitions
+ *
+ * ============================================================
+ * Copyright (c) Texas Instruments Incorporated 2009-2019
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+/**
+ * @brief This is the gpio Driver Version. Versions numbers are encoded in the
+ * following format:
+ * 0xAABBCCDD -> Arch (AA); API Changes (BB); Major (CC); Minor (DD)
+ */
+#define GPIO_DRV_VERSION_ID (0x01000010)
+
+/**
+ * @brief This is the version string which describes the GPIO driver along with
+ * the date and build information.
+ */
+#define GPIO_DRV_VERSION_STR "GPIO Driver Revision: 01.00.00.16"
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* _GPIOVER_H */
diff --git a/packages/ti/drv/gpio/GPIOver.h.xdt b/packages/ti/drv/gpio/GPIOver.h.xdt
--- /dev/null
@@ -0,0 +1,100 @@
+%%{\r
+/*!\r
+ * This template implements the GPIOver.h\r
+ */ \r
+ /* Versioning */\r
+ var ver = this;\r
+ var ver1 = [00,00,00,00];\r
+ var ver2 = [00,00,00,00];\r
+ \r
+ for each(i=0;i<ver.length;i++)\r
+ {\r
+ if(String(ver[i]).length < 2)\r
+ {\r
+ ver1[i]="0"+ver[i];\r
+ }\r
+ else\r
+ {\r
+ ver1[i] = ver[i];\r
+ }\r
+ \r
+ ver2[i] = Number(ver[i]).toString(16).toUpperCase();\r
+ \r
+ if(String(ver2[i]).length < 2)\r
+ {\r
+ ver2[i]="0"+ver2[i];\r
+ }\r
+ }\r
+ \r
+ var versionStr = "\""+"GPIO Driver Revision: "+ver1[0]+"."+ver1[1]+"."+ver1[2]+"."+ver1[3]+"\"";\r
+ var versionID = "(0x"+ver2[0]+ver2[1]+ver2[2]+ver2[3]+")";\r
+\r
+%%}\r
+#ifndef _GPIOVER_H\r
+#define _GPIOVER_H\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/* ============================================================= */\r
+/**\r
+ * @file GPIOver.h\r
+ *\r
+ * path ti/drv/gpio/GPIOver.h\r
+ *\r
+ * @brief gpio Driver Version Definitions\r
+ *\r
+ * ============================================================\r
+ * Copyright (c) Texas Instruments Incorporated 2009-2017\r
+ * \r
+ * Redistribution and use in source and binary forms, with or without \r
+ * modification, are permitted provided that the following conditions \r
+ * are met:\r
+ *\r
+ * Redistributions of source code must retain the above copyright \r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the \r
+ * documentation and/or other materials provided with the \r
+ * distribution.\r
+ *\r
+ * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \r
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT \r
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT \r
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \r
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT \r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT \r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE \r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+*/\r
+\r
+/**\r
+ * @brief This is the gpio Driver Version. Versions numbers are encoded in the \r
+ * following format:\r
+ * 0xAABBCCDD -> Arch (AA); API Changes (BB); Major (CC); Minor (DD)\r
+ */\r
+#define GPIO_DRV_VERSION_ID `versionID`\r
+\r
+/**\r
+ * @brief This is the version string which describes the GPIO driver along with\r
+ * the date and build information.\r
+ */\r
+#define GPIO_DRV_VERSION_STR `versionStr`\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+ \r
+\r
+#endif /* _GPIOVER_H */\r
diff --git a/packages/ti/drv/gpio/Settings.xdc.xdt b/packages/ti/drv/gpio/Settings.xdc.xdt
--- /dev/null
@@ -0,0 +1,55 @@
+\r
+%%{\r
+/*!\r
+ * This template implements the Settings.xdc\r
+ */ \r
+ /* Versioning */\r
+ var ver = this;\r
+ for each(i=0;i<ver.length;i++)\r
+ {\r
+ if(String(ver[i]).length < 2)\r
+ {\r
+ ver[i]="0"+ver[i];\r
+ }\r
+ }\r
+ \r
+ var packageVersion = "\""+ver[0]+"."+ver[1]+"."+ver[2]+"."+ver[3]+"\"";\r
+\r
+%%}\r
+\r
+module Settings\r
+{\r
+ config string gpioVersionString = `packageVersion`;\r
+ /*! This variable is to control the SoC type selection.\r
+ * By default this variable is set to NULL.\r
+ * \r
+ * To use LLD for the selected device, add the following lines to config\r
+ * file and set the deviceType correctly:\r
+ *\r
+ * var gpioSettings = xdc.useModule ('ti.drv.gpio.Settings');\r
+ * gpioSettings.socType = "am572x";\r
+ * \r
+ */\r
+ metaonly config string socType = "";\r
+\r
+ /*! This flag is used to indicate whether or not the benchmarking code\r
+ * (defined in the profilingHooks class) will be used in the project.\r
+ * Note that a separate library has been compiled and will be used\r
+ * ($NAME).profiling.a($SUFFIX). This is set in the *.cfg file.\r
+ */\r
+ config Bool enableProfiling = false;\r
+ \r
+ /*! This variable is to control the device library type selection.\r
+ * By default this variable is set to release.\r
+ * \r
+ * To use CSL to use the debug/release library, add the following lines to config\r
+ * file and set the library profile accordingly:\r
+ * \r
+ * var Uart Settings = xdc.useModule ('ti.Uart.Settings');\r
+ * UartSettings.libProfile = "debug";\r
+ * \r
+ */\r
+ metaonly config string libProfile = "release"; \r
+\r
+}\r
+\r
diff --git a/packages/ti/drv/gpio/build/buildlib.xs b/packages/ti/drv/gpio/build/buildlib.xs
--- /dev/null
@@ -0,0 +1,645 @@
+/******************************************************************************\r
+ * FILE PURPOSE: Build Library Utilities\r
+ ******************************************************************************\r
+ * FILE NAME: buildlib.xs\r
+ *\r
+ * DESCRIPTION: \r
+ * This file contains common routines that are used by the various LLD\r
+ * components.\r
+ *\r
+ * Copyright (C) 2014-2015, Texas Instruments, Inc.\r
+ *****************************************************************************/\r
+\r
+/**************************************************************************\r
+ * FUNCTION NAME : listAllFiles\r
+ **************************************************************************\r
+ * DESCRIPTION :\r
+ * Utility function which lists all files with a specific extension \r
+ * present in a directory and any directory inside it.\r
+ **************************************************************************/\r
+function listAllFiles(ext, dir, recurse)\r
+{ \r
+ var srcFile = [];\r
+ var d;\r
+\r
+ /* If recurse parameter is not specified we default to recursive search. */\r
+ if (recurse == null)\r
+ recurse = true;\r
+\r
+ if (dir == undefined) \r
+ d = ".";\r
+ else \r
+ d = dir;\r
+\r
+ /* Get access to the current directory. */\r
+ var file = new java.io.File(d);\r
+\r
+ /* Check if the file exists and it is a directory. */\r
+ if (file.exists() && file.isDirectory()) \r
+ {\r
+ /* Get a list of all files in the specific directory. */\r
+ var fileList = file.listFiles();\r
+ for (var i = 0; i < fileList.length; i++) \r
+ {\r
+ /* Dont add the generated directory 'package' and any of its files \r
+ * to the list here. */\r
+ if (fileList[i].getName().matches("package") == false)\r
+ {\r
+ /* Check if the detected file is a directory */\r
+ if (fileList[i].isDirectory())\r
+ {\r
+ /* We will recurse into the subdirectory only if required to do so. */\r
+ if (recurse == true)\r
+ {\r
+ /* Generate the directory Name in which we will recurse. */ \r
+ var directoryName = d + "/" + fileList[i].getName();\r
+\r
+ /* Get a list of all files in this directory */\r
+ var fileListing = listAllFiles (ext, directoryName, recurse);\r
+ if (fileListing != null)\r
+ {\r
+ /* Return a list of all file names in the directory. */\r
+ for (var j = 0 ; j < fileListing.length; j++) \r
+ srcFile[srcFile.length++] = fileListing[j];\r
+ }\r
+ }\r
+ }\r
+ else\r
+ {\r
+ /* This was a file. Check if the file name matches the extension */\r
+ if (fileList[i].getName().endsWith(ext) == true)\r
+ srcFile[srcFile.length++] = d + "/" + fileList[i].getName();\r
+ }\r
+ }\r
+ }\r
+\r
+ return srcFile;\r
+ }\r
+ return null;\r
+}\r
+\r
+\r
+function createMake(makefile)\r
+{\r
+ /* Create the main make file */\r
+ var fileModule = xdc.module('xdc.services.io.File');\r
+ if(makefile==undefined)\r
+ {\r
+ try{\r
+ makefile = fileModule.open("makefile", "w");\r
+ } catch (ex)\r
+ {\r
+ print("makefile cannot be written to. Please check Writing Permissions.");\r
+ java.lang.System.exit(1);\r
+ } \r
+ \r
+ Pkg.makePrologue += "\ninclude makefile\n"; \r
+ \r
+ Pkg.makeEpilogue += "\nclean::\n\t-$(RM) makefile\n";\r
+ makefile.writeLine("#*******************************************************************************");\r
+ makefile.writeLine("#* FILE PURPOSE: Top level makefile for Creating Component Libraries");\r
+ makefile.writeLine("#*******************************************************************************");\r
+ makefile.writeLine("#* FILE NAME: makefile");\r
+ makefile.writeLine("#*");\r
+ makefile.writeLine("#* DESCRIPTION: Defines Compiler tools paths, libraries , Build Options ");\r
+ makefile.writeLine("#*");\r
+ makefile.writeLine("#*");\r
+ makefile.writeLine("#*******************************************************************************");\r
+ makefile.writeLine("#*");\r
+ makefile.writeLine("# (Mandatory) Specify where various tools are installed.");\r
+\r
+ var file = xdc.module('xdc.services.io.File');\r
+ \r
+ \r
+ makefile.writeLine("\n# Output for prebuilt generated libraries");\r
+ makefile.writeLine("export LIBDIR ?= ./lib");\r
+ /* use sectti.exe from path */\r
+ makefile.writeLine("export SECTTI ?= sectti");\r
+\r
+ /* Create INCDIR from XDCPATH */\r
+ \r
+ /* copy the environment array from the current environment */\r
+ var env = java.lang.System.getenv();\r
+ var getxdcpath=String(java.lang.System.getenv("XDCPATH"));\r
+ getxdcpath= getxdcpath.replace(/\\/g,"/");\r
+ var keys = env.keySet().toArray();\r
+ var key;\r
+ var stat={};\r
+ var env_j=[];\r
+ var listxdcpath = new Array();\r
+ for (var i = 0; i < keys.length; i++) {\r
+ key = String(keys[i]);\r
+ if((key.match("INSTALL_PATH")) || (key.match("INSTALLDIR")))\r
+ {\r
+ var keyPath=String(env.get(key));\r
+ keyPath=keyPath.replace(/\\/g,"/");\r
+ var file = xdc.module('xdc.services.io.File');\r
+ keyPath=file.getDOSPath(keyPath);\r
+ if(getxdcpath.toString().match(keyPath))\r
+ {\r
+ listxdcpath.push({keyname: key,keypath: keyPath});\r
+ while(getxdcpath.toString().match(keyPath))\r
+ {\r
+ getxdcpath=getxdcpath.toString().replace(keyPath,"$("+key+")");\r
+ }\r
+ }\r
+ }\r
+ \r
+ }\r
+ var pkgroot="..";\r
+ for (var i = Pkg.name.split('.').length; i > 1; i--) {\r
+ pkgroot+="/..";\r
+ }\r
+ \r
+ makefile.writeLine("\n# ROOT Directory"); \r
+ makefile.writeLine("export ROOTDIR := "+pkgroot);\r
+ \r
+ makefile.writeLine("\n# INCLUDE Directory");\r
+ makefile.writeLine("export INCDIR := "+getxdcpath+";$(ROOTDIR)"); \r
+ \r
+ makefile.writeLine("\n# Common Macros used in make"); \r
+ makefile.writeLine("\nifndef RM"); \r
+ makefile.writeLine("export RM = rm -f");\r
+ makefile.writeLine("endif"); \r
+ \r
+ makefile.writeLine("\nifndef CP"); \r
+ makefile.writeLine("export CP = cp -p"); \r
+ makefile.writeLine("endif"); \r
+ \r
+ makefile.writeLine("\nexport MKDIR = mkdir -p");\r
+ \r
+ makefile.writeLine("\nifndef RMDIR"); \r
+ makefile.writeLine("export RMDIR = rm -rf");\r
+ makefile.writeLine("endif"); \r
+ \r
+ makefile.writeLine("\nifndef SED"); \r
+ makefile.writeLine("export SED = sed"); \r
+ makefile.writeLine("endif"); \r
+ \r
+ makefile.writeLine("\nifndef MAKE"); \r
+ makefile.writeLine("export MAKE = make"); \r
+ makefile.writeLine("endif"); \r
+\r
+ makefile.writeLine("\n# PHONY Targets"); \r
+ makefile.writeLine(".PHONY: all clean cleanall "); \r
+ \r
+ makefile.writeLine("\n# FORCE Targets"); \r
+ makefile.writeLine("FORCE: "); \r
+ \r
+ makefile.writeLine("\n# all rule"); \r
+ makefile.writeLine("all: .executables"); \r
+ makefile.writeLine(".executables: .libraries");\r
+ makefile.writeLine(".libraries:");\r
+ \r
+ makefile.writeLine("\n# Clean Rule"); \r
+ makefile.writeLine("clean:: clean_package"); \r
+ makefile.writeLine("# Clean Top Level Object Directory "); \r
+ makefile.writeLine("clean_package :\n\t$(RMDIR) $(LIBDIR)/*/"); \r
+ makefile.writeLine("\t$(RMDIR) package/cfg"); \r
+ }\r
+ else\r
+ {\r
+ try{\r
+ makefile = fileModule.open("makefile", "a");\r
+ } catch (ex)\r
+ {\r
+ print("makefile cannot be written to. Please check Writing Permissions.");\r
+ java.lang.System.exit(1);\r
+ } \r
+ \r
+ }\r
+\r
+ return makefile;\r
+}\r
+\r
+function createLibMake(device, objExtDir, makelibname,targetname, objectPath, useProfiling)\r
+{\r
+ var tooldir;\r
+ var cmdprefix;\r
+ var targetDir;\r
+ var stringname=String(targetname).replace("(xdc.bld.ITarget.Module)","");\r
+ var benchSuffix = "";\r
+\r
+ if (useProfiling == true) {\r
+ benchSuffix = "_bench";\r
+ }\r
+\r
+ switch(stringname)\r
+ {\r
+ case String(C66LE):\r
+ tooldir="C6X_GEN_INSTALL_PATH";\r
+ cmdprefix="";\r
+ targetDir="c66/release";\r
+ targetname=C66LE;\r
+ break;\r
+ case String(C66BE):\r
+ tooldir="C6X_GEN_INSTALL_PATH";\r
+ cmdprefix="";\r
+ targetDir="c66/release";\r
+ targetname=C66BE;\r
+ break;\r
+ case String(C674LE):\r
+ tooldir="C6X_GEN_INSTALL_PATH";\r
+ cmdprefix="";\r
+ targetDir="c674/release";\r
+ targetname=C674LE;\r
+ break;\r
+ case String(A15LE):\r
+ tooldir="TOOLCHAIN_PATH_A15"; \r
+ cmdprefix="CROSS_TOOL_PRFX";\r
+ targetDir="a15/release";\r
+ targetname=A15LE;\r
+ break;\r
+ case String(A9LE):\r
+ tooldir="TOOLCHAIN_PATH_A9";\r
+ cmdprefix="CROSS_TOOL_PRFX";\r
+ targetDir="a9/release";\r
+ targetname=A9LE;\r
+ break;\r
+ case String(A8LE):\r
+ tooldir="TOOLCHAIN_PATH_A8";\r
+ cmdprefix="CROSS_TOOL_PRFX";\r
+ targetDir="a8/release";\r
+ targetname=A8LE;\r
+ break;\r
+ case String(ARM9LE):\r
+ tooldir="TOOLCHAIN_PATH_ARM9";\r
+ cmdprefix="CROSS_TOOL_PRFX";\r
+ targetDir="arm9/release";\r
+ targetname=ARM9LE;\r
+ break;\r
+ case String(M4LE):\r
+ tooldir="TOOLCHAIN_PATH_M4";\r
+ cmdprefix="";\r
+ targetDir="m4/release";\r
+ targetname=M4LE;\r
+ break;\r
+ }\r
+ \r
+ var fileModule = xdc.module('xdc.services.io.File');\r
+ try{\r
+ var dstFile = new java.io.File(makelibname);\r
+ dstFile.getParentFile().mkdirs(); \r
+ libmakefile = fileModule.open(makelibname, "w");\r
+ /* Add to Archive list */\r
+ } catch (ex)\r
+ {\r
+ print(makelibname+" cannot be written to. Please check Writing Permissions.");\r
+ java.lang.System.exit(1);\r
+ } \r
+ libmakefile.writeLine("#*******************************************************************************");\r
+ libmakefile.writeLine("#* FILE PURPOSE: Lower level makefile for Creating Component Libraries");\r
+ libmakefile.writeLine("#*******************************************************************************");\r
+ libmakefile.writeLine("#* FILE NAME: "+makelibname);\r
+ libmakefile.writeLine("#*");\r
+ libmakefile.writeLine("#* DESCRIPTION: Defines Source Files, Compilers flags and build rules");\r
+ libmakefile.writeLine("#*");\r
+ libmakefile.writeLine("#*");\r
+ libmakefile.writeLine("#*******************************************************************************");\r
+ libmakefile.writeLine("#");\r
+ libmakefile.writeLine("");\r
+ libmakefile.writeLine("#");\r
+ libmakefile.writeLine("# Macro definitions referenced below");\r
+ libmakefile.writeLine("#");\r
+ libmakefile.writeLine("empty =");\r
+ libmakefile.writeLine("space =$(empty) $(empty)");\r
+ \r
+ if ((targetname.name == "A15F") || (targetname.name == "A9F") || (targetname.name == "A8F"))\r
+ {\r
+ \r
+ if(stringname.match("gnu.targets"))\r
+ {\r
+ libmakefile.writeLine("CC = $("+tooldir+")/bin/$("+cmdprefix+")gcc");\r
+ libmakefile.writeLine("AC = $("+tooldir+")/bin/$("+cmdprefix+")as"); \r
+ libmakefile.writeLine("ARIN = $("+tooldir+")/bin/$("+cmdprefix+")ar"); \r
+ libmakefile.writeLine("LD = $("+tooldir+")/bin/$("+cmdprefix+")gcc"); \r
+ }\r
+ else\r
+ {\r
+ print("Error: Non-GNU targets are not currently supported ");\r
+ java.lang.System.exit(1);\r
+\r
+ }\r
+ \r
+ libmakefile.writeLine("INCS = -I. -I$(strip $(subst ;, -I,$(subst $(space),\\$(space),$(INCDIR)))) -I$("+tooldir+")/include");\r
+ libmakefile.writeLine("OBJEXT = o"+targetname.suffix); \r
+ libmakefile.writeLine("AOBJEXT = s"+targetname.suffix); \r
+ if (useProfiling == true){\r
+ libmakefile.writeLine("CFLAGS_INTERNAL = " +targetname.ccOpts.prefix+" "+targetname.cc.opts+" -finstrument-functions -gdwarf-3 -g -D_ENABLE_BM");\r
+ }else{\r
+ libmakefile.writeLine("CFLAGS_INTERNAL = " +targetname.ccOpts.prefix+" "+targetname.cc.opts);\r
+ }\r
+ libmakefile.writeLine("ASFLAGS_INTERNAL = " +targetname.asmOpts.prefix+" "+targetname.asm.opts);\r
+ libmakefile.writeLine("ARFLAGS_INTERNAL = " +targetname.ar.opts);\r
+ libmakefile.writeLine("LNKFLAGS_INTERNAL = " +targetname.lnk.opts);\r
+ libmakefile.writeLine("INTERNALDEFS = -MD -MF $@.dep");\r
+ libmakefile.writeLine("INTERNALLINKDEFS = -o $@ -m $@.map"); /* TBD */\r
+ libmakefile.writeLine("OBJDIR = ./obj/obj_" +targetname.suffix +"/" + device.toString() + "/" + targetDir +"/obj" + "/" + objExtDir + benchSuffix); \r
+ \r
+ }\r
+ else\r
+ {\r
+ \r
+ if(stringname.match("ti.targets"))\r
+ {\r
+\r
+ var rtslibtemp = targetname.lnkOpts.suffix.toString().split("/");\r
+ var rtslib;\r
+ for(n=0;n<rtslibtemp.length;n++)\r
+ {\r
+ if(rtslibtemp[n].match(".lib"))\r
+ { \r
+ rtslib=rtslibtemp[n];\r
+ }\r
+ }\r
+\r
+ libmakefile.writeLine("CC = $("+tooldir+")/bin/"+targetname.cc.cmd);\r
+ libmakefile.writeLine("AC = $("+tooldir+")/bin/"+targetname.asm.cmd); \r
+ libmakefile.writeLine("ARIN = $("+tooldir+")/bin/"+targetname.ar.cmd); \r
+ libmakefile.writeLine("LD = $("+tooldir+")/bin/"+targetname.lnk.cmd); \r
+ libmakefile.writeLine("RTSLIB = -l $("+tooldir+")/lib/"+rtslib); \r
+ }\r
+ else\r
+ {\r
+ print("Error: Non-TI targets are not currently supported ");\r
+ java.lang.System.exit(1);\r
+\r
+ }\r
+ \r
+ libmakefile.writeLine("INCS = -I. -I$(strip $(subst ;, -I,$(subst $(space),\\$(space),$(INCDIR)))) -I$("+tooldir+")/include");\r
+ libmakefile.writeLine("OBJEXT = o"+targetname.suffix); \r
+ libmakefile.writeLine("AOBJEXT = s"+targetname.suffix); \r
+ if (useProfiling == true){\r
+ libmakefile.writeLine("CFLAGS_INTERNAL = " +targetname.ccOpts.prefix+" "+targetname.cc.opts+" --entry_parm=address --exit_hook=ti_utils_exit --exit_parm=address --entry_hook=ti_utils_entry -g -D_ENABLE_BM");\r
+ }else{\r
+ libmakefile.writeLine("CFLAGS_INTERNAL = " +targetname.ccOpts.prefix+" "+targetname.cc.opts);\r
+ }\r
+ libmakefile.writeLine("ASFLAGS_INTERNAL = " +targetname.asmOpts.prefix+" "+targetname.asm.opts);\r
+ libmakefile.writeLine("ARFLAGS_INTERNAL = " +targetname.ar.opts);\r
+ libmakefile.writeLine("LNKFLAGS_INTERNAL = " +targetname.lnk.opts);\r
+ /* libmakefile.writeLine("INTERNALDEFS = -D"+stringname.replace(/\./g,"_")+" -Dxdc_target_types__=ti/targets/std.h -DMAKEFILE_BUILD -eo.$(OBJEXT) -ea.$(AOBJEXT) -fr=$(@D) -fs=$(@D) -ppa -ppd=$@.dep");*/\r
+ libmakefile.writeLine("INTERNALDEFS = -D"+stringname.replace(/\./g,"_")+" -DMAKEFILE_BUILD -eo.$(OBJEXT) -ea.$(AOBJEXT) -fr=$(@D) -fs=$(@D) -ppa -ppd=$@.dep");\r
+ libmakefile.writeLine("INTERNALLINKDEFS = -o $@ -m $@.map");\r
+ libmakefile.writeLine("OBJDIR = ./obj/obj_" +targetname.suffix +"/" + device.toString() + "/" + targetDir +"/obj" + "/" + objExtDir + benchSuffix); \r
+ }\r
+ \r
+ return libmakefile;\r
+\r
+}\r
+\r
+function makeAddObjects(srcString, makefilename, srcfiles, flags,fileExt, targetName, objDir)\r
+{\r
+ var sourcestring = (srcString + fileExt).toString().toUpperCase();\r
+ var compileflagstring = sourcestring + "FLAGS";\r
+ var objectliststring = sourcestring + "OBJS";\r
+ /* List all the source files */\r
+ makefilename.writeLine("\n#List the "+srcString+" Files"); \r
+ makefilename.writeLine(sourcestring + "= \\");\r
+ for(var i=0;i<srcfiles.length-1;i++)\r
+ {\r
+ makefilename.writeLine(" "+srcfiles[i]+"\\");\r
+ }\r
+ makefilename.writeLine(" "+srcfiles[i]+"\n");\r
+ \r
+ /* Flags for the source files */\r
+ makefilename.writeLine("# FLAGS for the "+srcString+" Files"); \r
+ var compileflags="";\r
+ if(fileExt == "asm" && flags.aopts != undefined)\r
+ {\r
+ compileflags+=" "+flags.aopts;\r
+ }\r
+ else if((fileExt == "c" || fileExt == "sa")&& flags.copts != undefined)\r
+ {\r
+ compileflags+=" "+flags.copts;\r
+ } \r
+\r
+ if(flags.incs != undefined)\r
+ {\r
+ compileflags+=" "+flags.incs;\r
+ }\r
+\r
+\r
+ makefilename.writeLine(compileflagstring+" = "+compileflags +" \n"); \r
+ makefilename.writeLine("# Make Rule for the "+srcString+" Files"); \r
+ \r
+ makefilename.writeLine(objectliststring +" = $(patsubst %."+fileExt+", "+objDir+"/%.$(OBJEXT), $(" + sourcestring + "))"); \r
+ makefilename.writeLine("\n$("+objectliststring+"): "+objDir+"/%.$(OBJEXT): %."+fileExt); \r
+ if(fileExt == "c")\r
+ { \r
+ makefilename.writeLine("\t-@echo cl"+targetName.suffix +" $< ..."); \r
+ }\r
+ else\r
+ {\r
+ makefilename.writeLine("\t-@echo asm"+targetName.suffix +" $< ..."); \r
+ }\r
+ makefilename.writeLine("\tif [ ! -d $(@D) ]; then $(MKDIR) $(@D) ; fi;"); \r
+ \r
+ if(fileExt == "c")\r
+ {\r
+ if ((targetName.name == "A15F") || (targetName.name == "A9F") || (targetName.name == "A8F"))\r
+ {\r
+ makefilename.writeLine("\t$(RM) $@.dep");\r
+ makefilename.writeLine("\t$(CC) $(CFLAGS_INTERNAL) $("+compileflagstring+") $(INTERNALDEFS) $(INCS) $< -o $@");\r
+ /* \r
+ TBD\r
+ */\r
+ }\r
+ else\r
+ {\r
+ makefilename.writeLine("\t$(RM) $@.dep");\r
+ makefilename.writeLine("\t$(CC) $(CFLAGS_INTERNAL) $("+compileflagstring+") $(INTERNALDEFS) $(INCS) -fc $< ");\r
+ makefilename.writeLine("\t-@$(CP) $@.dep $@.pp; \\");\r
+ makefilename.writeLine(" $(SED) -e 's/#.*//' -e 's/^[^:]*: *//' -e 's/ *\\\\$$//' \\");\r
+ makefilename.writeLine(" -e '/^$$/ d' -e 's/$$/ :/' < $@.pp >> $@.dep; \\");\r
+ makefilename.writeLine(" $(RM) $@.pp ");\r
+ }\r
+ }\r
+ else if(fileExt == "asm")\r
+ {\r
+ makefilename.writeLine("\t$(AC) $(ASFLAGS_INTERNAL) $("+compileflagstring+") $(INTERNALDEFS) $(INCS) -fa $< ");\r
+ }\r
+ else if(fileExt == "sa")\r
+ {\r
+ makefilename.writeLine("\t$(AC) $(ASFLAGS_INTERNAL) $("+compileflagstring+") $(INTERNALDEFS) $(INCS) $< ");\r
+ }\r
+ \r
+ makefilename.writeLine("\n#Create Empty rule for dependency");\r
+ makefilename.writeLine("$("+objectliststring+"):"+makefilename.$private.fd);\r
+ makefilename.writeLine(makefilename.$private.fd+":");\r
+ makefilename.writeLine("\n#Include Depedency for "+srcString+" Files");\r
+ makefilename.writeLine("ifneq (clean,$(MAKECMDGOALS))");\r
+ makefilename.writeLine(" -include $("+objectliststring+":%.$(OBJEXT)=%.$(OBJEXT).dep)");\r
+ makefilename.writeLine("endif");\r
+ \r
+}\r
+\r
+/**************************************************************************\r
+ * FUNCTION NAME : buildLibrary\r
+ **************************************************************************\r
+ * DESCRIPTION :\r
+ * Utility function which will build a specific library\r
+ **************************************************************************/\r
+var makefilelocal;\r
+function buildLibrary (socName, isDmaSoc, isSoc, libOptions, libName, target, libFiles, useProfiling) \r
+{\r
+ var targetDir;\r
+ var objExtDir;\r
+ \r
+ if (useProfiling == true)\r
+ {\r
+ libName += ".profiling"\r
+ }\r
+\r
+ if (target.name == "A15F")\r
+ {\r
+ targetDir = "a15/release";\r
+ }\r
+ else if (target.name == "A9F")\r
+ {\r
+ targetDir = "a9/release";\r
+ }\r
+ else if (target.name == "A8F")\r
+ {\r
+ targetDir = "a8/release";\r
+ }\r
+ else if (target.name == "ARM9")\r
+ {\r
+ targetDir = "arm9/release";\r
+ }\r
+ else if (target.name == "C674")\r
+ {\r
+ targetDir = "c674/release";\r
+ }\r
+ else if (target.name == "M4")\r
+ {\r
+ targetDir = "m4/release";\r
+ }\r
+ else\r
+ {\r
+ targetDir = "c66/release";\r
+ }\r
+ \r
+ /* Derive the operating system and soc names */\r
+ if (isSoc == "true") {\r
+ var libNameExp = libName;\r
+ targetDir = socName+"/"+targetDir;\r
+ objExtDir = "soc";\r
+ }\r
+ else {\r
+ var libNameExp = libName;\r
+ objExtDir = "all";\r
+ }\r
+\r
+ var lldFullLibraryPath = "./lib/" + targetDir +"/" + libNameExp;\r
+ var lldFullBuildPath = "./build/" + targetDir +"/" + libNameExp;\r
+ var lldFullLibraryPathMake = "$(LIBDIR)/" + targetDir +"/" + libNameExp;\r
+\r
+ /* Create Main make file in the root of package folder */\r
+ makefilelocal = createMake(makefilelocal);\r
+\r
+ /* Write the rule to make library in main makefile */\r
+ lib = lldFullBuildPath+".a"+target.suffix;\r
+ libMake = lldFullLibraryPathMake+".a"+target.suffix;\r
+ var objectPath= "./package/"+lldFullBuildPath;\r
+ \r
+ makefilelocal.writeLine("\n\n# Make rule to create "+libMake+" library");\r
+ makefilelocal.writeLine(".libraries: "+ libMake);\r
+ makefilelocal.writeLine(libMake+": FORCE\n\t$(MAKE) -f "+lib+".mk $@"); \r
+\r
+ /* Create Library make file in the lib folder */\r
+ var makefilelib= createLibMake(socName, objExtDir, lib+".mk",target,objectPath,useProfiling); \r
+\r
+ /* Rule to clean library in main makefile */\r
+ makefilelocal.writeLine("# Rule to clean "+libMake+" library"); \r
+ makefilelocal.writeLine("clean ::\n\t$(RM) "+ libMake); \r
+ librule="\n\n"+libMake+" :";\r
+\r
+ /* Add files to be compiled */\r
+ /* Separate out the C and assembly files */\r
+ var cfiles= new Array();\r
+ var afiles= new Array();\r
+ var safiles= new Array();\r
+ for each(var srcFile in libFiles)\r
+ {\r
+ var srcFile=String(srcFile);\r
+ var dot = srcFile.lastIndexOf(".");\r
+ var extension = srcFile.substr(dot,srcFile.length); \r
+ if(extension == ".c")\r
+ {\r
+ cfiles.push(srcFile);\r
+ }\r
+ else if(extension == ".sa")\r
+ {\r
+ safiles.push(srcFile);\r
+ }\r
+ else if(extension == ".asm")\r
+ {\r
+ afiles.push(srcFile);\r
+ }\r
+ else\r
+ {\r
+ print("ERROR: Unsupported file extension");\r
+ java.lang.System.exit(1);\r
+ }\r
+ }\r
+ if(cfiles.length > 0)\r
+ { \r
+ makeAddObjects("COMMONSRC",makefilelib,cfiles,libOptions,"c",target, "$(OBJDIR)");\r
+ librule += " $(COMMONSRCCOBJS)"; \r
+ }\r
+ if(afiles.length > 0)\r
+ { \r
+ makeAddObjects("COMMONSRC",makefilelib,afiles,libOptions,"asm",target, "$(OBJDIR)");\r
+ librule += " $(COMMONSRCASMOBJS)"; \r
+ }\r
+ if(safiles.length > 0)\r
+ { \r
+ makeAddObjects("COMMONSRC",makefilelib,safiles,libOptions,"sa",target, "$(OBJDIR)");\r
+ librule += " $(COMMONSRCSAOBJS)"; \r
+ }\r
+\r
+ makefilelib.writeLine(librule);\r
+ makefilelib.writeLine("\t@echo archiving $? into $@ ...");\r
+ makefilelib.writeLine("\tif [ ! -d $(LIBDIR)/"+targetDir+" ]; then $(MKDIR) $(LIBDIR)/"+targetDir+" ; fi;"); \r
+ makefilelib.writeLine("\t$(ARIN) $(ARFLAGS_INTERNAL) $@ $?");\r
+ makefilelib.close(); \r
+\r
+ /* Create the Epilogue; which executes after all the builds are completed. \r
+ * This is used to generate the benchmark information for the built library. \r
+ * Also add the benchmarking information file to the package. */\r
+ /* Put the temp file in object directory since javascript doesn't have a built in tmpname, \r
+ * and don't want --jobs=# with # > 1 to result in collisions */\r
+ var libFullName = lldFullLibraryPath + ".a" + target.suffix;\r
+ var tempFile = libFullName + ".xml";\r
+ Pkg.makeEpilogue += ".libraries: " + libFullName + "_size.txt\n";\r
+ Pkg.makeEpilogue += libFullName + "_size.txt: " + libFullName + "\n";\r
+ if ( java.lang.String(target.name).contains('66') )\r
+ { \r
+ Pkg.makeEpilogue += "\n\t $(C6X_GEN_INSTALL_PATH)/bin/ofd6x -x " + libFullName + " > " + tempFile;\r
+ Pkg.makeEpilogue += "\n\t $(SECTTI) " + tempFile + " > " + libFullName + "_size.txt";\r
+ Pkg.makeEpilogue += "\n\t $(RM) " + tempFile + "\n\n";\r
+ } \r
+ else if (target.name == "M4")\r
+ {\r
+ Pkg.makeEpilogue += "\n\t $(TOOLCHAIN_PATH_M4)/bin/armofd -x " + libFullName + " > " + tempFile;\r
+ Pkg.makeEpilogue += "\n\t $(SECTTI) " + tempFile + " > " + libFullName + "_size.txt";\r
+ Pkg.makeEpilogue += "\n\t $(RM) " + tempFile + "\n\n";\r
+ }\r
+ else\r
+ {\r
+ Pkg.makeEpilogue += "\n\t $(TOOLCHAIN_PATH_A15)/bin/$(CROSS_TOOL_PRFX)size " + libFullName + " > " + libFullName + "_size.txt";\r
+ } \r
+ Pkg.otherFiles[Pkg.otherFiles.length++] = lldFullLibraryPath + ".a" + target.suffix + "_size.txt";\r
+ Pkg.otherFiles[Pkg.otherFiles.length++] = lldFullBuildPath + ".a" + target.suffix + ".mk";\r
+ Pkg.otherFiles[Pkg.otherFiles.length++] = lldFullLibraryPath + ".a" + target.suffix;\r
+\r
+ /* We need to clean after ourselves; extend the 'clean' target to take care of this. */\r
+ Pkg.makeEpilogue += "\nclean::\n";\r
+ Pkg.makeEpilogue += "\t$(RM) " + lldFullBuildPath + ".a" + target.suffix + "_size.txt\n"; \r
+ Pkg.makeEpilogue += "\t$(RMDIR) " + "$(LIBDIR)/" + targetDir + "/ \n\n";\r
+\r
+ return lib;\r
+}\r
+\r
+\r
+\r
diff --git a/packages/ti/drv/gpio/build/makefile.mk b/packages/ti/drv/gpio/build/makefile.mk
--- /dev/null
@@ -0,0 +1,63 @@
+#
+# Copyright (c) 2016 - 2018, Texas Instruments Incorporated
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# * Redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer.
+#
+# * Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution.
+#
+# * Neither the name of Texas Instruments Incorporated nor the names of
+# its contributors may be used to endorse or promote products derived
+# from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+# OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+# EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+
+include $(PDK_INSTALL_PATH)/ti/build/Rules.make
+include $(PDK_GPIO_COMP_PATH)/src/src_files_common.mk
+
+MODULE_NAME = gpio
+
+ifeq ($(SOC),$(filter $(SOC), am571x am572x am574x dra72x dra75x dra78x k2h k2k k2l k2e k2g c6678 c6657 am437x am335x omapl137 omapl138 am65xx j721e))
+SRCDIR += soc/$(SOC)
+INCDIR += soc
+# Common source files across all platforms and cores
+ SRCS_COMMON += GPIO_soc.c
+endif
+
+# List all the external components/interfaces, whose interface header files
+# need to be included for this component
+INCLUDE_EXTERNAL_INTERFACES = pdk edma
+
+ifeq ($(SOC),$(filter $(SOC), am571x am572x am574x dra72x dra75x dra78x k2h k2k k2l k2e k2g c6678 c6657 am437x am335x omapl137 omapl138 am65xx j721e))
+ PACKAGE_SRCS_COMMON += soc/$(SOC)/GPIO_soc.c soc/GPIO_soc.h
+endif
+
+CFLAGS_LOCAL_COMMON = $(PDK_CFLAGS)
+
+# Include common make files
+ifeq ($(MAKERULEDIR), )
+#Makerule path not defined, define this and assume relative path from ROOTDIR
+ MAKERULEDIR := $(ROOTDIR)/ti/build/makerules
+ export MAKERULEDIR
+endif
+include $(MAKERULEDIR)/common.mk
+
+# Nothing beyond this point
diff --git a/packages/ti/drv/gpio/build/makefile_indp.mk b/packages/ti/drv/gpio/build/makefile_indp.mk
--- /dev/null
@@ -0,0 +1,52 @@
+#
+# Copyright (c) 2016, Texas Instruments Incorporated
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# * Redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer.
+#
+# * Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution.
+#
+# * Neither the name of Texas Instruments Incorporated nor the names of
+# its contributors may be used to endorse or promote products derived
+# from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+# OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+# EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+
+include $(PDK_INSTALL_PATH)/ti/build/Rules.make
+include $(PDK_GPIO_COMP_PATH)/src/src_files_common.mk
+
+MODULE_NAME = gpio_indp
+
+# List all the external components/interfaces, whose interface header files
+# need to be included for this component
+INCLUDE_EXTERNAL_INTERFACES = pdk edma
+
+CFLAGS_LOCAL_COMMON = $(PDK_CFLAGS)
+
+# Include common make files
+ifeq ($(MAKERULEDIR), )
+#Makerule path not defined, define this and assume relative path from ROOTDIR
+ MAKERULEDIR := $(ROOTDIR)/ti/build/makerules
+ export MAKERULEDIR
+endif
+include $(MAKERULEDIR)/common.mk
+
+# Nothing beyond this point
diff --git a/packages/ti/drv/gpio/build/makefile_profile.mk b/packages/ti/drv/gpio/build/makefile_profile.mk
--- /dev/null
@@ -0,0 +1,69 @@
+#
+# Copyright (c) 2016, Texas Instruments Incorporated
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# * Redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer.
+#
+# * Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution.
+#
+# * Neither the name of Texas Instruments Incorporated nor the names of
+# its contributors may be used to endorse or promote products derived
+# from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+# OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+# EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+
+include $(PDK_INSTALL_PATH)/ti/build/Rules.make
+include $(PDK_GPIO_COMP_PATH)/src/src_files_common.mk
+
+MODULE_NAME = gpio_profile
+
+ifeq ($(SOC),$(filter $(SOC), am571x am572x am574x dra72x dra75x dra78x k2h k2k k2l k2e k2g c6678 c6657 am437x am335x omapl137 omapl138 am65xx j721e))
+SRCDIR += soc/$(SOC)
+INCDIR += soc
+# Common source files across all platforms and cores
+ SRCS_COMMON += GPIO_soc.c
+endif
+
+# List all the external components/interfaces, whose interface header files
+# need to be included for this component
+INCLUDE_EXTERNAL_INTERFACES = pdk edma
+
+ifeq ($(SOC),$(filter $(SOC), am571x am572x am574x dra72x dra75x dra78x k2h k2k k2l k2e k2g c6678 c6657 am437x am335x omapl137 omapl138 am65xx j721e))
+PACKAGE_SRCS_COMMON += soc/$(SOC) soc/$(SOC)/GPIO_soc.c soc/GPIO_soc.h
+endif
+
+ifeq ($(BUILDTYPE),$(filter $(BUILDTYPE), profile profiledma))
+ ifeq ($(CORE),$(filter $(CORE), a15_0 a9host a8host))
+ CFLAGS_LOCAL_COMMON = $(PDK_CFLAGS) -finstrument-functions -gdwarf-3 -g -D_ENABLE_BM
+ else
+ CFLAGS_LOCAL_COMMON = $(PDK_CFLAGS) --entry_parm=address --exit_hook=ti_utils_exit --exit_parm=address --entry_hook=ti_utils_entry -g -D_ENABLE_BM
+ endif
+endif
+
+# Include common make files
+ifeq ($(MAKERULEDIR), )
+#Makerule path not defined, define this and assume relative path from ROOTDIR
+ MAKERULEDIR := $(ROOTDIR)/ti/build/makerules
+ export MAKERULEDIR
+endif
+include $(MAKERULEDIR)/common.mk
+
+# Nothing beyond this point
diff --git a/packages/ti/drv/gpio/build/makefile_profile_indp.mk b/packages/ti/drv/gpio/build/makefile_profile_indp.mk
--- /dev/null
@@ -0,0 +1,58 @@
+#
+# Copyright (c) 2016, Texas Instruments Incorporated
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# * Redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer.
+#
+# * Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution.
+#
+# * Neither the name of Texas Instruments Incorporated nor the names of
+# its contributors may be used to endorse or promote products derived
+# from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+# OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+# EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+
+include $(PDK_INSTALL_PATH)/ti/build/Rules.make
+include $(PDK_GPIO_COMP_PATH)/src/src_files_common.mk
+
+MODULE_NAME = gpio_profile_indp
+
+# List all the external components/interfaces, whose interface header files
+# need to be included for this component
+INCLUDE_EXTERNAL_INTERFACES = pdk edma
+
+ifeq ($(BUILDTYPE),$(filter $(BUILDTYPE), profile profiledma))
+ ifeq ($(CORE),$(filter $(CORE), a15_0 a9host a8host))
+ CFLAGS_LOCAL_COMMON = $(PDK_CFLAGS) -finstrument-functions -gdwarf-3 -g -D_ENABLE_BM
+ else
+ CFLAGS_LOCAL_COMMON = $(PDK_CFLAGS) --entry_parm=address --exit_hook=ti_utils_exit --exit_parm=address --entry_hook=ti_utils_entry -g -D_ENABLE_BM
+ endif
+endif
+
+# Include common make files
+ifeq ($(MAKERULEDIR), )
+#Makerule path not defined, define this and assume relative path from ROOTDIR
+ MAKERULEDIR := $(ROOTDIR)/ti/build/makerules
+ export MAKERULEDIR
+endif
+include $(MAKERULEDIR)/common.mk
+
+# Nothing beyond this point
diff --git a/packages/ti/drv/gpio/config.bld b/packages/ti/drv/gpio/config.bld
--- /dev/null
@@ -0,0 +1,373 @@
+/******************************************************************************\r
+ * FILE PURPOSE: Build configuration Script for the gpio Driver\r
+ ******************************************************************************\r
+ * FILE NAME: config.bld\r
+ *\r
+ * DESCRIPTION: \r
+ * This file contains the build configuration script for the gpio driver\r
+ * and is responsible for configuration of the paths for the various \r
+ * tools required to build the driver.\r
+ *\r
+ * Copyright (C) 2014-2015, Texas Instruments, Inc.\r
+ *****************************************************************************/\r
+\r
+/* Get the Tools Base directory from the Environment Variable. */\r
+var c66ToolsBaseDir = java.lang.System.getenv("C6X_GEN_INSTALL_PATH");\r
+var c674ToolsBaseDir = java.lang.System.getenv("C6X_GEN_INSTALL_PATH");\r
+var m4ToolsBaseDir = java.lang.System.getenv("TOOLCHAIN_PATH_M4");\r
+var a15ToolsBaseDir = java.lang.System.getenv("TOOLCHAIN_PATH_A15");\r
+var a9ToolsBaseDir = java.lang.System.getenv("TOOLCHAIN_PATH_A9");\r
+var a8ToolsBaseDir = java.lang.System.getenv("TOOLCHAIN_PATH_A8");\r
+var arm9ToolsBaseDir = java.lang.System.getenv("TOOLCHAIN_PATH_ARM9");\r
+\r
+/* Get the extended debug flags for C66x, \r
+ * did not change the name for backwards compatibilty */\r
+var extDbgFlags = java.lang.System.getenv("EXTDBGFLAGS");\r
+\r
+/* Get the extended debug flags for A15 */\r
+var extDbgFlags_a15 = java.lang.System.getenv("EXTDBGFLAGS_A15");\r
+\r
+/* Get the extended debug flags for A8 */\r
+var extDbgFlags_a8 = java.lang.System.getenv("EXTDBGFLAGS_A8");\r
+\r
+/* Get the extended debug flags for A9 */\r
+var extDbgFlags_a9 = java.lang.System.getenv("EXTDBGFLAGS_A9");\r
+\r
+/* Get the extended debug flags for ARM9 */\r
+var extDbgFlags_arm9 = java.lang.System.getenv("EXTDBGFLAGS_ARM9");\r
+\r
+/* Get the extended debug flags for M4 */\r
+var extDbgFlags_m4 = java.lang.System.getenv("EXTDBGFLAGS_M4");\r
+\r
+/* Get the base directory for the uart Socket Driver Package */\r
+var driverPath = new java.io.File(".//").getPath();\r
+\r
+/* Include Path */\r
+var lldIncludePath = " -I" + driverPath + "/src" + " -I" + driverPath;\r
+\r
+/* Configure the gpio Socket Release Version Information */\r
+/* 3 steps: remove SPACE and TAB, convert to string and split to make array */\r
+var driverReleaseVersion = (""+Pkg.version.replace(/\s/g, "")).split(',');\r
+\r
+/* Print the Compiler Options */\r
+var pOpts = 1;\r
+\r
+/* C66 ELF compiler configuration for Little Endian Mode. */\r
+var C66LE = xdc.useModule('ti.targets.elf.C66');\r
+C66LE.rootDir = c66ToolsBaseDir;\r
+C66LE.ccOpts.prefix = "-mo -o3 -q -k -eo.o";\r
+if(extDbgFlags)\r
+ C66LE.ccOpts.prefix = C66LE.ccOpts.prefix + " " + extDbgFlags; \r
+\r
+/* C66 ELF compiler configuration for Big Endian Mode. */\r
+var C66BE = xdc.useModule('ti.targets.elf.C66_big_endian');\r
+C66BE.rootDir = c66ToolsBaseDir;\r
+C66BE.ccOpts.prefix = "-mo -o3 -q -k -eo.o -DBIGENDIAN";\r
+if(extDbgFlags) \r
+ C66BE.ccOpts.prefix = C66BE.ccOpts.prefix + " " + extDbgFlags;\r
+\r
+/* C674 ELF compiler configuration for Little Endian Mode. */\r
+var C674LE = xdc.useModule('ti.targets.elf.C674');\r
+C674LE.rootDir = c674ToolsBaseDir;\r
+C674LE.asmOpts.prefix = "--strip_coff_underscore";\r
+C674LE.ccOpts.prefix = "--strip_coff_underscore -mo -o3 -q -k -eo.o " + "-D" + cslPartNumber;\r
+if(extDbgFlags)\r
+ C674LE.ccOpts.prefix = C674LE.ccOpts.prefix + " " + extDbgFlags\r
+\r
+/* ARMv7 A15 compiler configuration */\r
+var A15LE = xdc.useModule('gnu.targets.arm.A15F');\r
+A15LE.rootDir = a15ToolsBaseDir;\r
+A15LE.ccOpts.prefix = "-mno-unaligned-access -c -mtune=cortex-a15 -marm -DDRA7xx -gstrict-dwarf -Wall -D__ARMv7 -D_LITTLE_ENDIAN=1";\r
+if(extDbgFlags_a15) \r
+ A15LE.ccOpts.prefix = A15LE.ccOpts.prefix + " " + extDbgFlags_a15; \r
+ \r
+/* ARMv7 A9 compiler configuration */\r
+var A9LE = xdc.useModule('gnu.targets.arm.A9F');\r
+A9LE.rootDir = a9ToolsBaseDir;\r
+A9LE.ccOpts.prefix = "-mno-unaligned-access -c -mtune=cortex-a9 -marm -DDRA7xx -gstrict-dwarf -Wall -D__ARMv7 -D_LITTLE_ENDIAN=1";\r
+if(extDbgFlags_a9) \r
+ A9LE.ccOpts.prefix = A9LE.ccOpts.prefix + " " + extDbgFlags_a9; \r
+\r
+/* ARMv7 A8 compiler configuration */\r
+var A8LE = xdc.useModule('gnu.targets.arm.A8F');\r
+A8LE.rootDir = a8ToolsBaseDir;\r
+A8LE.ccOpts.prefix = "-mno-unaligned-access -c -mtune=cortex-a8 -marm -DDRA7xx -gstrict-dwarf -Wall -D__ARMv7 -D_LITTLE_ENDIAN=1";\r
+if(extDbgFlags_a8) \r
+ A8LE.ccOpts.prefix = A8LE.ccOpts.prefix + " " + extDbgFlags_a8; \r
+\r
+/* ARMv5 ARM9 compiler configuration */\r
+var ARM9LE = xdc.useModule('ti.targets.arm.elf.Arm9');\r
+ARM9LE.rootDir = arm9ToolsBaseDir;\r
+ARM9LE.ccOpts.prefix = "-mno-unaligned-access -c -marm Dxdc_target_types__=gnu/targets/arm/std.h -Dxdc_target_name__=Arm9 -gstrict-dwarf -Wall -D__ARMv5 -D_LITTLE_ENDIAN=1";\r
+if(extDbgFlags_arm9)\r
+ ARM9LE.ccOpts.prefix = ARM9LE.ccOpts.prefix + " " + extDbgFlags_arm9;\r
+\r
+/* M4 ELF compiler configuration for Little Endian Mode. */\r
+var M4LE = xdc.useModule('ti.targets.arm.elf.M4');\r
+M4LE.rootDir = m4ToolsBaseDir;\r
+M4LE.ccOpts.prefix = "-o4 -qq -pdsw255 -DMAKEFILE_BUILD";\r
+if(extDbgFlags_m4)\r
+ M4LE.ccOpts.prefix = M4LE.ccOpts.prefix + " " + extDbgFlags_m4; \r
+\r
+/* soc name (am?) is inserted between first an second element of this\r
+ list to construct device file name for each device */\r
+var deviceConstruct = [ "soc/", "/GPIO_soc.c" ];\r
+\r
+\r
+/* Create the SoC List */\r
+var socs = { \r
+ /* device independent libraries */\r
+ all :\r
+ {\r
+ /* Build this library */\r
+ build: "true",\r
+ /* SoC lib enabled */\r
+ socDevLib: "false",\r
+ /* Library options */\r
+ copts: "",\r
+ /* target lists, kept blank now, would be updated based on argument lists */\r
+ targets: []\r
+ },\r
+ am335x :\r
+ {\r
+ /* this variable would be reinitialized to true, if XDCARGS contains am335x */\r
+ build: "false",\r
+ /* SoC lib enabled */\r
+ socDevLib: "true",\r
+ /* Library options */\r
+ copts: " -DSOC_AM335x",\r
+ /* target list */\r
+ targets: [ A8LE ]\r
+ },\r
+ am437x :\r
+ {\r
+ /* this variable would be reinitialized to true, if XDCARGS contains am437x */\r
+ build: "false", \r
+ /* SoC lib enabled */\r
+ socDevLib: "true",\r
+ /* Library options */\r
+ copts: " -DSOC_AM437x",\r
+ /* target list */\r
+ targets: [ A9LE ]\r
+ },\r
+ am572x :\r
+ {\r
+ /* this variable would be reinitialized to true, if XDCARGS contains am572x */\r
+ build: "false", \r
+ /* SoC lib enabled */\r
+ socDevLib: "true",\r
+ /* Library options */\r
+ copts: " -DSOC_AM572x",\r
+ /* target list */\r
+ targets: [ C66LE, M4LE, A15LE]\r
+ },\r
+ am574x :\r
+ {\r
+ /* this variable would be reinitialized to true, if XDCARGS contains am574x */\r
+ build: "false",\r
+ /* SoC lib enabled */\r
+ socDevLib: "true",\r
+ /* Library options */\r
+ copts: " -DSOC_AM574x",\r
+ /* target list */\r
+ targets: [ C66LE, M4LE, A15LE]\r
+ },\r
+ am571x :\r
+ {\r
+ /* this variable would be reinitialized to true, if XDCARGS contains am571x */\r
+ build: "false", \r
+ /* SoC lib enabled */\r
+ socDevLib: "true",\r
+ /* Library options */\r
+ copts: " -DSOC_AM571x",\r
+ /* target list */\r
+ targets: [ C66LE, M4LE, A15LE]\r
+ }, \r
+ dra75x :\r
+ {\r
+ /* this variable would be reinitialized to true, if XDCARGS contains dra75x */\r
+ build: "false",\r
+ /* SoC lib enabled */\r
+ socDevLib: "true",\r
+ /* Library options */\r
+ copts: " -DSOC_DRA75x",\r
+ /* target list */\r
+ targets: [ C66LE, M4LE, A15LE]\r
+ },\r
+ dra78x :\r
+ {\r
+ /* this variable would be reinitialized to true, if XDCARGS contains dra75x */\r
+ build: "false",\r
+ /* SoC lib enabled */\r
+ socDevLib: "true",\r
+ /* Library options */\r
+ copts: " -DSOC_DRA75x",\r
+ /* target list */\r
+ targets: [ C66LE, M4LE]\r
+ },\r
+ k2h :\r
+ {\r
+ /* this variable would be reinitialized to true, if XDCARGS contains k2h */\r
+ build: "false", \r
+ /* SoC lib enabled */\r
+ socDevLib: "true",\r
+ /* Library options */\r
+ copts: " -DSOC_K2H",\r
+ /* target list */\r
+ targets: [ C66LE, C66BE, A15LE]\r
+ }, \r
+ k2k :\r
+ {\r
+ /* this variable would be reinitialized to true, if XDCARGS contains k2k */\r
+ build: "false", \r
+ /* SoC lib enabled */\r
+ socDevLib: "true",\r
+ /* Library options */\r
+ copts: " -DSOC_K2H",\r
+ /* target list */\r
+ targets: [ C66LE, C66BE, A15LE]\r
+ }, \r
+ k2e :\r
+ {\r
+ /* this variable would be reinitialized to true, if XDCARGS contains k2e */\r
+ build: "false", \r
+ /* SoC lib enabled */\r
+ socDevLib: "true",\r
+ /* Library options */\r
+ copts: " -DSOC_K2E",\r
+ /* target list */\r
+ targets: [ C66LE, C66BE, A15LE]\r
+ }, \r
+ k2l :\r
+ {\r
+ /* this variable would be reinitialized to true, if XDCARGS contains k2l */\r
+ build: "false", \r
+ /* SoC lib enabled */\r
+ socDevLib: "true",\r
+ /* Library options */\r
+ copts: " -DSOC_K2L",\r
+ /* target list */\r
+ targets: [ C66LE, C66BE, A15LE]\r
+ },\r
+ k2g :\r
+ {\r
+ /* this variable would be reinitialized to true, if XDCARGS contains k2g */\r
+ build: "false", \r
+ /* SoC lib enabled */\r
+ socDevLib: "true",\r
+ /* Library options */\r
+ copts: " -DSOC_K2G",\r
+ /* target list */\r
+ targets: [ C66LE, C66BE, A15LE]\r
+ },\r
+ omapl137 :\r
+ {\r
+ /* this variable would be reinitialized to true, if XDCARGS contains omapl137 */\r
+ build: "false",\r
+ /* SoC lib enabled */\r
+ socDevLib: "true",\r
+ /* Library options */\r
+ copts: " -DSOC_OMAPL137",\r
+ /* target list */\r
+ targets: [ C674LE, ARM9LE]\r
+ },\r
+ omapl138 :\r
+ {\r
+ /* this variable would be reinitialized to true, if XDCARGS contains omapl138 */\r
+ build: "false",\r
+ /* SoC lib enabled */\r
+ socDevLib: "true",\r
+ /* Library options */\r
+ copts: " -DSOC_OMAPL138",\r
+ /* target list */\r
+ targets: [ C674LE, ARM9LE]\r
+ },\r
+ c6678 :\r
+ {\r
+ /* this variable would be reinitialized to true, if XDCARGS contains c6678 */\r
+ build: "false", \r
+ /* SoC lib enabled */\r
+ socDevLib: "true",\r
+ /* Library options */\r
+ copts: " -DSOC_C6678",\r
+ /* target list */\r
+ targets: [ C66LE, C66BE]\r
+ },\r
+ c6657 :\r
+ {\r
+ /* this variable would be reinitialized to true, if XDCARGS contains c6657 */\r
+ build: "false", \r
+ /* SoC lib enabled */\r
+ socDevLib: "true",\r
+ /* Library options */\r
+ copts: " -DSOC_C6657",\r
+ /* target list */\r
+ targets: [ C66LE, C66BE]\r
+ }\r
+};\r
+\r
+/**************************************************************************\r
+ * FUNCTION NAME : merge\r
+ **************************************************************************\r
+ * DESCRIPTION :\r
+ * The function is used to merge two arrarys\r
+ **************************************************************************/\r
+function merge() {\r
+ var args = arguments;\r
+ var hash = {};\r
+ var arr = [];\r
+ for (var i = 0; i < args.length; i++) {\r
+ for (var j = 0; j < args[i].length; j++) {\r
+ if (hash[args[i][j]] !== true) {\r
+ arr[arr.length] = args[i][j];\r
+ hash[args[i][j]] = true;\r
+ }\r
+ }\r
+ }\r
+ return arr;\r
+}\r
+\r
+/* Grab input from XDCARGS */\r
+var buildArguments = [];\r
+\r
+/* Construct the build arguments */\r
+for (var tmp=0; arguments[tmp] != undefined; tmp++)\r
+{\r
+\r
+ /* If no arguments are provided, override for building all */\r
+ if ( ( arguments.length == 1) && (arguments[tmp].equals("./config.bld")) )\r
+ buildArguments[buildArguments.length++] = "all";\r
+ else\r
+ buildArguments[buildArguments.length++] = arguments[tmp];\r
+}\r
+\r
+/* Build targets on this build */\r
+var build_targets = [];\r
+var soc_names = Object.keys(socs);\r
+\r
+for (var i=0; i < buildArguments.length; i++ ) {\r
+ /* Build it for all targets */\r
+ if (buildArguments[i] == "all") {\r
+ for (var j = 0; j < soc_names.length; j++) {\r
+ build_targets = merge (build_targets.slice(0), socs[soc_names[j]].targets.slice(0));\r
+ /* Set build to "true" for that SoC */\r
+ socs[soc_names[j]].build = "true";\r
+ }\r
+ }\r
+ else {\r
+ /* Skip the first argument, which is ./config.bld to get to next SoCs */\r
+ if (i == 0) continue; \r
+ /* Set that build to true if it is found in supported build socs */\r
+ for (j = 0; j < soc_names.length; j++) {\r
+ if (buildArguments[i] == soc_names[j]) {\r
+ socs[buildArguments[i]].build = "true";\r
+ build_targets = merge (build_targets.slice(0), socs[buildArguments[i]].targets.slice(0));\r
+ break;\r
+ }\r
+ }\r
+ } \r
+}\r
+\r
+/* Update the Build target generated list */\r
+socs["all"].targets = build_targets; \r
+Build.targets = build_targets;\r
diff --git a/packages/ti/drv/gpio/config_mk.bld b/packages/ti/drv/gpio/config_mk.bld
--- /dev/null
@@ -0,0 +1,44 @@
+/******************************************************************************
+ * FILE PURPOSE: Build configuration Script for the gpio Driver
+ ******************************************************************************
+ * FILE NAME: config_mk.bld
+ *
+ * DESCRIPTION:
+ * This file contains the build configuration script for the gpio driver
+ * and is responsible for configuration of the paths for the various
+ * tools required to build the driver.
+ *
+ * Copyright (C) 2014-2016, Texas Instruments, Inc.
+ *****************************************************************************/
+
+/* Get the Tools Base directory from the Environment Variable. */
+var c66ToolsBaseDir = java.lang.System.getenv("C6X_GEN_INSTALL_PATH");
+var c674ToolsBaseDir = java.lang.System.getenv("C6X_GEN_INSTALL_PATH");
+var m4ToolsBaseDir = java.lang.System.getenv("TOOLCHAIN_PATH_M4");
+var a15ToolsBaseDir = java.lang.System.getenv("TOOLCHAIN_PATH_A15");
+var a9ToolsBaseDir = java.lang.System.getenv("TOOLCHAIN_PATH_A9");
+var arm9ToolsBaseDir = java.lang.System.getenv("TOOLCHAIN_PATH_ARM9");
+var a8ToolsBaseDir = java.lang.System.getenv("TOOLCHAIN_PATH_A8");
+
+/* Get the base directory for the uart Socket Driver Package */
+var driverPath = new java.io.File(".//").getPath();
+
+/* Include Path */
+var lldIncludePath = " -I" + driverPath + "/src" + " -I" + driverPath;
+
+/* Configure the gpio Socket Release Version Information */
+/* 3 steps: remove SPACE and TAB, convert to string and split to make array */
+var driverReleaseVersion = (""+Pkg.version.replace(/\s/g, "")).split(',');
+
+/* Do not Print the Compiler Options */
+var pOpts = 0;
+
+/* List of all devices that needs to be build via XDC
+ * As the build happens through makefile, there is nothing to build via XDC
+ * using the below for packaging infrastructure
+ */
+var socs = [];
+var devices = [];
+var build_devices = [];
+Build.targets = []
+
diff --git a/packages/ti/drv/gpio/docs/GPIO_LLD_SoftwareManifest.html b/packages/ti/drv/gpio/docs/GPIO_LLD_SoftwareManifest.html
--- /dev/null
@@ -0,0 +1,328 @@
+<!--\r\r
+Texas Instruments Manifest Format 2.0\r\r
+-->\r\r
+\r\r
+<!DOCTYPE html PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">\r\r
+<html>\r\r
+\r\r
+<head>\r\r
+<meta http-equiv="Content-Type" content="text/html; charset=ISO-8859-1" />\r\r
+<!-- @Start Style -->\r\r
+<!-- Default style in case someone doesnt have Internet Access -->\r\r
+<style type="text/css" id="internalStyle">\r\r
+ body, div, p {\r\r
+ font-family: Lucida Grande, Verdana, Geneva, Arial, sans-serif;\r\r
+ font-size: 13px;\r\r
+ line-height: 1.3;\r\r
+ }\r\r
+ body {\r\r
+ margin: 20px; \r\r
+ }\r\r
+ h1 {\r\r
+ font-size: 150%;\r\r
+ }\r\r
+ h2 {\r\r
+ font-size: 120%;\r\r
+ }\r\r
+ h3 {\r\r
+ font-size: 100%;\r\r
+ }\r\r
+ img {\r\r
+ border: 0px;\r\r
+ vertical-align: middle;\r\r
+ }\r\r
+ table, th, td, tr {\r\r
+ border: 1px solid black; \r\r
+ font-family: Lucida Grande, Verdana, Geneva, Arial, sans-serif;\r\r
+ font-size: 13px;\r\r
+ line-height: 1.3;\r\r
+ empty-cells: show; \r\r
+ padding: 5px;\r\r
+ }\r\r
+ table {\r\r
+ border-collapse: collapse; \r\r
+ width: 100%;\r\r
+ }\r\r
+ tr {\r\r
+ page-break-inside: avoid;\r\r
+ }\r\r
+ #TIlogoLeft {\r\r
+ background-color: black; \r\r
+ padding: 0;\r\r
+ width: 20%;\r\r
+ }\r\r
+ #TIlogoRight {\r\r
+ background-color: red; \r\r
+ padding: 0;\r\r
+ }\r\r
+ #ProductName {\r\r
+ text-align: center;\r\r
+ }\r\r
+ #ReleaseDate {\r\r
+ text-align: center;\r\r
+ }\r\r
+ .LogoSection {\r\r
+ margin: 0;\r\r
+ padding: 0;\r\r
+ }\r\r
+ .HeaderSection {\r\r
+ margin: 25px 0 25px 0;\r\r
+ padding: 0;\r\r
+ }\r\r
+ .LegendSection {\r\r
+ margin: 25px 0 25px 0;\r\r
+ }\r\r
+ .ExportSection {\r\r
+ margin: 25px 0 25px 0;\r\r
+ }\r\r
+ .DisclaimerSection {\r\r
+ margin: 25px 0 25px 0; \r\r
+ }\r\r
+ .CreditSection {\r\r
+ margin: 25px 0 25px 0; \r\r
+ }\r\r
+ .LicenseSection {\r\r
+ margin: 25px 0 25px 0; \r\r
+ }\r\r
+ .ManifestTable {\r\r
+ margin: 25px 0 25px 0; \r\r
+ }\r\r
+</style> \r\r
+<!-- Override style from TI if they have Internet Access -->\r\r
+<link type="text/css" rel="stylesheet" href="timanifeststyle.css">\r\r
+<!-- @End Style -->\r\r
+<title>Texas Instruments Manifest</title>\r\r
+</head>\r\r
+\r\r
+<body><!-- Logo display, will need to fix up the URLs, this is just for testing.. Image alternate display not wporking well yet -->\r\r
+<div class="LogoSection">\r\r
+<table>\r\r
+ <tbody>\r\r
+ <tr>\r\r
+ <td id="TIlogoLeft">\r\r
+ <a href="http://www.ti.com/">\r\r
+ <!-- img src="tilogo.gif" alt="Texas Instruments Incorporated" -->\r\r
+ <img alt="" src="data:image/gif;base64,R0lGODlh3gA2AKIAAAAAAP///7u7u29vbz8/PwYGBujo6BgYGCH5BAAAAAAALAAAAADeADYAAAP/CLrc/jDKSau9OOvNu/9gKI5kaZ5oqq5s675wLM90bd94ru987//AoHBILBqPyKRyyWw6n9CodHorDALYLIHKJVqz2q44eAUHtoDB4DBu48rgLQErcNtnX7NhMDcICIB3gix5ZmtqAAZZew8EAo+QkQIDNVZqiIM1cHGKZ4YPAmaiAWw0c1gFmZqjB3SbZ6kNe6WhsAeOlDV0qjSFAXUAp7lwuREFtVsFgMvLB7fNAM+BCs+lDLd8BNYOuxfV22PL0RiWlwO1u3kDqejAEsjR6GB86FsHoYwA6gxWnVgGEegUuIelWJk6jswAGlXQ36J1xBSoQwfulIEDr/6l+VeK/+AehrAGOHRnAWRBbbWegckXAV6wk4AeRQtDQBEaBYsYlMl2hUCsBt0iKgilT9EfAlfO7SmzdKkrkQUT/fqZSECqLCSlntH375IAA1tqGUilLIBSNVnU+NmJNBRVChlF1QwAdlRWBy5P3QymwCLBYhs73cTHYBq3X33nDQ2wcWuBgef0FRD4GK3jU3VCZZUJAIw1OGg0P+4bFiubOWoOsEP1+KvZn3wurDbZ6lfcuw3yYkFjRSeYzRe7ARAbW0K3PmGIMi0OFDG1Mmha+RnufAHn3xL9ha6uTZ/rXagZ1GKAtTsHeWb+FEQvHILuX4+mLzj2j2r4TrFesTwMbE5Cuv8JzbTSGuRV1xgfUJFC3WbA0JWFalcItpgf8YU2yT/qATaedent5cBb8zk0DzIitgfKbonRFV9Wp2xl3UXq5Ccibp05598BnRigiAIJmrZAexkJQIuBwzX4CB3SQbeYQkPVAUco63DI2HzsAdYAiAvEZdYlaVQ5wXs3+bQAjovEUoBRR9LVAFLaPXCcY/KMqVRasQB5kiJgLcYgTkJiuCWKC2ZpIY/z/LRhYefkBAGW1HTyRy2UjObLHxSAOZ948EUVGCSC3SLZbB7iZKOLc2GRRgMH/VhdHnJwFCgD8iEGx0VKvpqbO+hoaCppEg3UiTES1CTkhNaQ+Qs4LQGql07/lET4mIQ6SvTSVGZ9Bmhz/bkYzK+PFKtpje6wumRm1wrLZzSdQASoZvyswdmSuk7p616HfkjBTxZBQucFgqXCFKdn1NpiUlQJhs8kteBWG0AbATbXS2tBlaeoVkmJRova4KkGPmhMFdiSYmq8cbTRYhrlkiHaNufJ9mIgVqEXnAOJM5JE4sgjudQ8bF82x+cKBP4Iiedecyjgx2/WtMNjjhcL9h+S4xq9RYJgsbeeUbmdrPTSQbPccsyijEXOfI8xyuinVJH1wdkS/MQ2Bc5Iq08DyHYwGglvPyCilbz0fa8GLV7r9+Btb7CJ14Qnzg8HpdKoOOF5Py752JNXvrblNphzEHnmnF/a+ecTbA465qKPXnnppkuOeuqKr8465K+z7nrsfc9Ouyq23z5I7rrfwXvvbhSQAAA7" />\r\r
+ </a>\r\r
+ </td>\r\r
+ <td id="TILogoRight">\r\r
+ <!-- img src="titagline.gif" alt="Technology for Innovators(tm)"-->\r\r
+ <img alt="" src="data:image/gif;base64,R0lGODlhOgEaALMAAP8AAP////92dv+3t/+Njf/W1v/t7f8hIf/19f+jo//Hx/8/P/9cXP/j4//6+v/+/iH5BAAAAAAALAAAAAA6ARoAAAT/EMhJq7046827/2AojmRpnmiqrmzrvnAsz3Rt33iu73zv/8CgcEgsGo/IpHLJbDqft0NDMCBQodis1jcADBKE7nYcCpjPgU5AQBKkVYOHAeRudqtXsh60/vRHdSoBBCGBNAkLe4o4f2psgG8pjR6GM5OLmDB/DA0GBoQADAgICRIBBQUOYgwGCg2kEgudBgUHAIGcBg0MsZ0NCnMGYgsBtqEGAbCynrW3AQONgcIFBgiErK6wAAfUtLbCscWiowoAyLDczLZu0AIJCAYOoJn0G38ObAwPEvLEts/O1vUhsA8AAjGonEmA9W6hGAVpEjiQoKBAhT8HJSRkVyEQQAAJ//a5YeMPQIFyACqCnJjSIgFCB4oB+HOSokWOAB6wIWCxnk8MfYh5QsYg5sVHfQLVMSqhztJIxWIaC6QzJy8KfZgqrNT0zR+nUNl8fSMvZ6IDwJCJRfoI7IR4Cub9nDsha6RwR02xUZpGq1utUWUq9FKgYV6/abgOHjt45tquEgY0SDDHoJg+fxhXolKNrmfH/EoR5EdAKmjQfB1qvPmGIQIJ3g4gC2egVF7LqxtP8Ng2cViTKFUCIGbNFKEEmB/VbDlYdqLRn+du8oTg6jjbmfe+CbTM2+BcuySgbQVtQoOCt7s3U8wbsqGs3ZppZLnylwFe8Uql825ogANPckUnYDoOCogxQGXADajggjcw4AA8DSSyTQASMmjhhTQscBWGHHbo4YcghijiiCSWaOKJKKao4oostugiFBEAADs=" />\r\r
+ </td>\r\r
+ </tr>\r\r
+ </tbody>\r\r
+</table>\r\r
+</div><div class="HeaderSection">\r\r
+<h1 id="ProductName">\r\r
+<!-- @Start Product -->\r\r
+GPIO LLD Manifest\r\r
+<!-- @End Product -->\r\r
+</h1>\r\r
+\r\r
+<h2 id="ReleaseDate">\r\r
+<!-- @Start Date -->\r\r
+02-25-2016\r\r
+<!-- @End Date -->\r\r
+</h2>\r\r
+\r\r
+\r\r
+<h2 id="SRASID">\r\r
+<!-- @Start Date -->\r\r
+Manifest ID - SRAS00002588\r\r
+<!-- @End Date -->\r\r
+</h2>\r\r
+</div><div class="LegendSection">\r\r
+<h2>Legend</h2>\r\r
+<p>(explanation of the fields in the Manifest Table below)</p>\r\r
+<table>\r\r
+<tbody>\r\r
+<tr>\r\r
+<td>\r\r
+<b>Software Name </b>\r\r
+</td>\r\r
+<td>\r\r
+The name of the application or file\r\r
+</td>\r\r
+</tr>\r\r
+<tr>\r\r
+<td>\r\r
+<b>Version</b>\r\r
+</td>\r\r
+<td>\r\r
+Version of the application or file\r\r
+</td>\r\r
+</tr>\r\r
+<tr>\r\r
+<td>\r\r
+<b>License Type</b>\r\r
+</td>\r\r
+<td>\r\r
+Type of license(s) under which TI will be providing\r\r
+software to the licensee (e.g. BSD-3-Clause, GPL-2.0, TI TSPA License, TI\r\r
+Commercial License). The license could be under Commercial terms or Open Source. See Open Source Reference License Disclaimer in\r\r
+the Disclaimers Section. Whenever possible, TI will use an <a href="http://spdx.org/licenses/"> SPDX Short Identifier </a> for an Open Source\r\r
+License. TI Commercial license terms are not usually included in the manifest and are conveyed through a variety \r\r
+of means such as a clickwrap license upon install, \r\r
+a signed license agreement and so forth.\r\r
+</td>\r\r
+</tr>\r\r
+<tr>\r\r
+<td>\r\r
+<b>Location</b>\r\r
+</td>\r\r
+<td>\r\r
+The directory name and path on the media or a specific file where the Software is located. Typically fully qualified path names \r\r
+are not used and instead the relevant top level directory of the application is given. \r\r
+A notation often used in the manifests is [as installed]/directory/*. Note that the asterisk implies that all\r\r
+files under that directory are licensed as the License Type field denotes. Any exceptions to this will \r\r
+generally be denoted as [as installed]/directory/* except as noted below which means as shown in subsequent rows of \r\r
+the manifest.\r\r
+</td>\r\r
+</tr>\r\r
+<tr>\r\r
+<td>\r\r
+<b>Delivered As</b>\r\r
+</td>\r\r
+<td>\r\r
+This field will either be “Source”, “Binary” or “Source\r\r
+and Binary” and is the primary form the content of the Software is delivered\r\r
+in. If the Software is delivered in an archive format, this field\r\r
+applies to the contents of the archive. If the word Limited is used\r\r
+with Source, as in “Limited Source” or “Limited Source and Binary” then\r\r
+only portions of the Source for the application are provided.\r\r
+</td>\r\r
+</tr>\r\r
+<tr>\r\r
+<td>\r\r
+<b>Modified by TI</b>\r\r
+</td>\r\r
+<td>\r\r
+This field will either be “Yes” or “No”. A “Yes” means\r\r
+TI has made changes to the Software. A “No” means TI has not made any\r\r
+changes. Note: This field is not applicable for Software “Obtained\r\r
+from” TI.\r\r
+</td>\r\r
+</tr>\r\r
+<tr>\r\r
+<td>\r\r
+<b>Obtained from</b>\r\r
+</td>\r\r
+<td>\r\r
+This field specifies from where or from whom TI obtained\r\r
+the Software. It may be a URL to an Open Source site, a 3<sup>rd</sup>\r\r
+party licensor, or TI. See Links Disclaimer in the Disclaimers\r\r
+Section.\r\r
+</td>\r\r
+</tr>\r\r
+</tbody>\r\r
+</table>\r\r
+</div><div class="DisclaimerSection">\r\r
+<h2>Disclaimers</h2>\r\r
+<h3>Export Control Classification Number (ECCN)</h3>\r\r
+<p>Any use of ECCNs listed in the Manifest is at the user’s risk\r\r
+and without recourse to TI. Your\r\r
+company, as the exporter of record, is responsible for determining the\r\r
+correct classification of any item at\r\r
+the time of export. Any export classification by TI of Software is for\r\r
+TI’s internal use only and shall not be construed as a representation\r\r
+or warranty\r\r
+regarding the proper export classification for such Software or whether\r\r
+an export\r\r
+license or other documentation is required for exporting such Software</p>\r\r
+<h3>Links in the Manifest</h3>\r\r
+<p>Any\r\r
+links appearing on this Manifest\r\r
+(for example in the “Obtained from” field) were verified at the time\r\r
+the Manifest was created. TI makes no guarantee that any listed links\r\r
+will\r\r
+remain active in the future.</p>\r\r
+<h3>Open Source License References</h3>\r\r
+<p>Your company is responsible for confirming the\r\r
+applicable license terms for any open source Software\r\r
+listed in this Manifest that was not “Obtained from” TI. Any open\r\r
+source license\r\r
+specified in this Manifest for Software that was\r\r
+not “Obtained from” TI is for TI’s internal use only and shall not be\r\r
+construed as a representation or warranty regarding the proper open\r\r
+source license terms\r\r
+for such Software.</p>\r\r
+</div><div class="ExportSection">\r\r
+<h2>Export Information</h2>\r\r
+<p>ECCN for Software included in this release:</p>\r\r
+Publicly Available - Open Source or TI TSPA License\r\r
+</div><div class="ManifestTable">\r\r
+<!-- h2>Manifest Table</h2 -->\r\r
+ \r
+ <table> \r
+ <tbody> \r
+ \r
+ <h2> \r
+ GPIO LLD Manifest Table \r
+ </h2> \r
+ \r
+ \r
+ <p> \r
+ \r
+ See the Legend above for a description of these columns. \r
+ \r
+ </p> \r
+ \r
+ <table id="targetpackages" name="targetpackages"> \r
+ <thead> \r
+ <tr> \r
+ <td><b>Software Name</b></td> \r
+ <td><b>Version</b></td> \r
+ <td><b>License Type</b></td> \r
+ <td><b>Delivered As</b></td> \r
+ <td><b>Modified by TI</b></td> \r
+ <td></td> \r
+ <td></td> \r
+ </tr> \r
+ </thead> \r
+ \r
+ \r
+ <tbody> \r
+ <tr> \r
+ <td id="name" name="name" rowspan="2"> \r
+ GPIO LLD \r
+ </td> \r
+ <td id="version" name="version" rowspan="2"> \r
+ 01.00.00 \r
+ </td> \r
+ <td id="license" name="license" rowspan="2"> \r
+ BSD-3-Clause \r
+ </td> \r
+ <td id="delivered" name="delivered" rowspan="2"> \r
+ Source and Binary \r
+ </td> \r
+ <td id="modified" name="modified" rowspan="2"> \r
+ N/A \r
+ </td> \r
+ <td><b>Location</b></td> \r
+ <td id="location" name="location"> \r
+ packages/ti/drv/gpio \r
+ </td> \r
+ </tr> \r
+ <tr> \r
+ <td><b>Obtained from</b></td> \r
+ <td id="obtained" name="obtained"> \r
+ Texas Instruments Incorporated \r
+ </td> \r
+ </tr> \r
+ \r
+ </tbody> \r
+ </table> \r
+ \r
+ </p> \r
+ </p> \r
+ <p> \r
+\r\r
+</div><div class="CreditSection">\r\r
+<h2>Credits</h2>\r\r
+<BR> <BR><BR><BR><BR>\r\r
+</div><div class="LicenseSection">\r\r
+<h2>Licenses</h2>\r\r
+<BR><h3><b> GPIO LLD Licenses </b></h3><BR> <BR><BR>/* Copyright (c) 2013 Texas Instruments Inc - http://www.ti.com */<BR><BR>/*<BR>*Â Redistribution and use in source and binary forms, with or without<BR>*Â modification, are permitted provided that the following conditions<BR>*Â are met:<BR>*<BR>*Â Â Â Redistributions of source code must retain the above copyright<BR>*Â Â Â notice, this list of conditions and the following disclaimer.<BR>*<BR>*Â Â Â Redistributions in binary form must reproduce the above copyright<BR>*Â Â Â notice, this list of conditions and the following disclaimer in the<BR>*Â Â Â documentation and/or other materials provided with the<BR>*Â Â Â distribution.<BR>*<BR>*Â Â Â Neither the name of Texas Instruments Incorporated nor the names of<BR>*Â Â Â its contributors may be used to endorse or promote products derived<BR>*Â Â Â from this software without specific prior written permission.<BR>*<BR>*Â THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS<BR>*Â "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT<BR>*Â LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR<BR>*Â A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT<BR>*Â OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,<BR>*Â SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT<BR>*Â LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,<BR>*Â DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY<BR>*Â THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT<BR>*Â (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE<BR>*Â OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.<BR>*<BR>*/<BR><BR><BR>\r\r
+</div>\r\r
+\r\r
+</body></html>
\ No newline at end of file
diff --git a/packages/ti/drv/gpio/docs/GPIO_LLD_UserGuide.pdf b/packages/ti/drv/gpio/docs/GPIO_LLD_UserGuide.pdf
new file mode 100755 (executable)
index 0000000..72bb50e
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index 0000000..72bb50e
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diff --git a/packages/ti/drv/gpio/docs/Module.xs b/packages/ti/drv/gpio/docs/Module.xs
--- /dev/null
@@ -0,0 +1,63 @@
+/******************************************************************************\r
+ * FILE PURPOSE: GPIO Driver DOCS Module specification file.\r
+ ******************************************************************************\r
+ * FILE NAME: module.xs\r
+ *\r
+ * DESCRIPTION: \r
+ * This file contains the module specification for the GPIO Driver Documentation .\r
+ *\r
+ * Copyright (C) 2008, Texas Instruments, Inc.\r
+ *****************************************************************************/\r
+\r
+/* Load the library utility. */\r
+var libUtility = xdc.loadCapsule ("../build/buildlib.xs");\r
+\r
+/**************************************************************************\r
+ * FUNCTION NAME : modBuild\r
+ **************************************************************************\r
+ * DESCRIPTION :\r
+ * The function is used to build the LLD documentation and add it to the\r
+ * package.\r
+ **************************************************************************/\r
+function modBuild() \r
+{\r
+ /* Create the actual PROLOGUE Section for the Documentation.*/\r
+ Pkg.makePrologue += "release: gpio_document_generation\n";\r
+ Pkg.makePrologue += "gpio_document_generation:\n";\r
+ Pkg.makePrologue += "\t @echo ----------------------------\n";\r
+ Pkg.makePrologue += "\t @echo Generating GPIO Driver Documentation\n";\r
+ Pkg.makePrologue += "\t doxygen docs/Doxyfile\n";\r
+ Pkg.makePrologue += "\t @echo GPIO Driver Documentation Generated \n";\r
+ Pkg.makePrologue += "\t @echo ----------------------------\n";\r
+\r
+ /* Add the documentation file to the package. */\r
+ Pkg.otherFiles[Pkg.otherFiles.length++] = "docs/tifooter.htm";\r
+ Pkg.otherFiles[Pkg.otherFiles.length++] = "docs/tiheader.htm";\r
+ Pkg.otherFiles[Pkg.otherFiles.length++] = "docs/tilogo.gif";\r
+ Pkg.otherFiles[Pkg.otherFiles.length++] = "docs/titagline.gif";\r
+\r
+ /* Add the GPIO Design Document to the package */\r
+ /* Pkg.otherFiles[Pkg.otherFiles.length++] = "docs/GPIO_LLD_UserGuide.pdf"; */\r
+\r
+ /* Add the GPIO Software Manifest to the package */\r
+ Pkg.otherFiles[Pkg.otherFiles.length++] = "docs/GPIO_LLD_SoftwareManifest.html";\r
+\r
+ /* Add the HTML documentation to the package */\r
+ Pkg.otherFiles[Pkg.otherFiles.length++] = "docs/doxygen";\r
+\r
+ /* Add the release notes to the package */\r
+ Pkg.otherFiles[Pkg.otherFiles.length++] = "docs/ReleaseNotes_GPIO_LLD.pdf";\r
+\r
+ /* Generate the ECLIPSE Plugin Generation: Only for SETUP Releases. */\r
+ if (driverInstallType == "SETUP")\r
+ {\r
+ Pkg.makePrologue += "all: eclipse_plugin_generation\n";\r
+ Pkg.makePrologue += "eclipse_plugin_generation:\n";\r
+ Pkg.makePrologue += "\t @echo ----------------------------\n";\r
+ Pkg.makePrologue += "\t @echo GPIO Eclipse Plugin Generation\n";\r
+ Pkg.makePrologue += "\t xs xdc.tools.eclipsePluginGen -o . -x ./eclipseDocs/sample.xml -c ./eclipseDocs/toc_cdoc_sample.xml\n";\r
+ Pkg.makePrologue += "\t @echo GPIO Eclipse Plugin Generated \n";\r
+ Pkg.makePrologue += "\t @echo ----------------------------\n";\r
+ }\r
+}\r
+\r
diff --git a/packages/ti/drv/gpio/docs/ReleaseNotes_GPIO_LLD.doc b/packages/ti/drv/gpio/docs/ReleaseNotes_GPIO_LLD.doc
new file mode 100755 (executable)
index 0000000..4ad9353
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diff --git a/packages/ti/drv/gpio/docs/ReleaseNotes_GPIO_LLD.pdf b/packages/ti/drv/gpio/docs/ReleaseNotes_GPIO_LLD.pdf
new file mode 100755 (executable)
index 0000000..c119a92
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index 0000000..c119a92
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diff --git a/packages/ti/drv/gpio/docs/doxyfile.xdt b/packages/ti/drv/gpio/docs/doxyfile.xdt
--- /dev/null
@@ -0,0 +1,298 @@
+%%{\r
+/*!\r
+ * This template implements the Doxyfile\r
+ */ \r
+ /* Versioning */\r
+ var ver = this;\r
+ var packageVersion = ver[0]+"."+ver[1]+"."+ver[2]+"."+ver[3];\r
+\r
+%%}\r
+\r
+# Doxyfile 1.5.6\r
+\r
+#---------------------------------------------------------------------------\r
+# Project related configuration options\r
+#---------------------------------------------------------------------------\r
+DOXYFILE_ENCODING = UTF-8\r
+PROJECT_NAME = "GPIO Low Level Driver"\r
+PROJECT_NUMBER = `packageVersion`\r
+OUTPUT_DIRECTORY = ./docs/doxygen\r
+CREATE_SUBDIRS = NO\r
+OUTPUT_LANGUAGE = English\r
+BRIEF_MEMBER_DESC = YES\r
+REPEAT_BRIEF = YES\r
+ABBREVIATE_BRIEF = "The $name class" \\r
+ "The $name widget" \\r
+ "The $name file" \\r
+ is \\r
+ provides \\r
+ specifies \\r
+ contains \\r
+ represents \\r
+ a \\r
+ an \\r
+ the\r
+ALWAYS_DETAILED_SEC = NO\r
+INLINE_INHERITED_MEMB = NO\r
+FULL_PATH_NAMES = NO\r
+STRIP_FROM_PATH = \r
+STRIP_FROM_INC_PATH = \r
+SHORT_NAMES = NO\r
+JAVADOC_AUTOBRIEF = NO\r
+QT_AUTOBRIEF = NO\r
+MULTILINE_CPP_IS_BRIEF = NO\r
+INHERIT_DOCS = YES\r
+SEPARATE_MEMBER_PAGES = NO\r
+TAB_SIZE = 8\r
+ALIASES = \r
+OPTIMIZE_OUTPUT_FOR_C = YES\r
+OPTIMIZE_OUTPUT_JAVA = NO\r
+OPTIMIZE_FOR_FORTRAN = NO\r
+OPTIMIZE_OUTPUT_VHDL = NO\r
+BUILTIN_STL_SUPPORT = NO\r
+CPP_CLI_SUPPORT = NO\r
+SIP_SUPPORT = NO\r
+IDL_PROPERTY_SUPPORT = YES\r
+DISTRIBUTE_GROUP_DOC = NO\r
+SUBGROUPING = YES\r
+TYPEDEF_HIDES_STRUCT = NO\r
+#---------------------------------------------------------------------------\r
+# Build related configuration options\r
+#---------------------------------------------------------------------------\r
+EXTRACT_ALL = NO\r
+EXTRACT_PRIVATE = NO\r
+EXTRACT_STATIC = YES\r
+EXTRACT_LOCAL_CLASSES = YES\r
+EXTRACT_LOCAL_METHODS = NO\r
+EXTRACT_ANON_NSPACES = NO\r
+HIDE_UNDOC_MEMBERS = YES\r
+HIDE_UNDOC_CLASSES = YES\r
+HIDE_FRIEND_COMPOUNDS = NO\r
+HIDE_IN_BODY_DOCS = NO\r
+INTERNAL_DOCS = NO\r
+CASE_SENSE_NAMES = NO\r
+HIDE_SCOPE_NAMES = NO\r
+SHOW_INCLUDE_FILES = YES\r
+INLINE_INFO = YES\r
+SORT_MEMBER_DOCS = YES\r
+SORT_BRIEF_DOCS = NO\r
+SORT_GROUP_NAMES = NO\r
+SORT_BY_SCOPE_NAME = NO\r
+GENERATE_TODOLIST = YES\r
+GENERATE_TESTLIST = YES\r
+GENERATE_BUGLIST = YES\r
+GENERATE_DEPRECATEDLIST= YES\r
+ENABLED_SECTIONS = \r
+MAX_INITIALIZER_LINES = 30\r
+SHOW_USED_FILES = YES\r
+SHOW_FILES = YES\r
+SHOW_NAMESPACES = YES\r
+FILE_VERSION_FILTER = \r
+#---------------------------------------------------------------------------\r
+# configuration options related to warning and progress messages\r
+#---------------------------------------------------------------------------\r
+QUIET = NO\r
+WARNINGS = YES\r
+WARN_IF_UNDOCUMENTED = YES\r
+WARN_IF_DOC_ERROR = YES\r
+WARN_NO_PARAMDOC = NO\r
+WARN_FORMAT = "$file:$line: $text"\r
+WARN_LOGFILE = \r
+#---------------------------------------------------------------------------\r
+# configuration options related to the input files\r
+#---------------------------------------------------------------------------\r
+INPUT = \r
+INPUT_ENCODING = UTF-8\r
+FILE_PATTERNS = *.c \\r
+ *.cc \\r
+ *.cxx \\r
+ *.cpp \\r
+ *.c++ \\r
+ *.d \\r
+ *.java \\r
+ *.ii \\r
+ *.ixx \\r
+ *.ipp \\r
+ *.i++ \\r
+ *.inl \\r
+ *.h \\r
+ *.hh \\r
+ *.hxx \\r
+ *.hpp \\r
+ *.h++ \\r
+ *.idl \\r
+ *.odl \\r
+ *.cs \\r
+ *.php \\r
+ *.php3 \\r
+ *.inc \\r
+ *.m \\r
+ *.mm \\r
+ *.dox \\r
+ *.py \\r
+ *.f90 \\r
+ *.f \\r
+ *.vhd \\r
+ *.vhdl\r
+RECURSIVE = YES\r
+EXCLUDE = YES \\r
+ ./example \\r
+ ./test \\r
+ ./package \\r
+ ./packages\r
+EXCLUDE_SYMLINKS = NO\r
+EXCLUDE_PATTERNS = cslr_*.h\r
+EXCLUDE_SYMBOLS = \r
+EXAMPLE_PATH = \r
+EXAMPLE_PATTERNS = *\r
+EXAMPLE_RECURSIVE = NO\r
+IMAGE_PATH = \r
+INPUT_FILTER = \r
+FILTER_PATTERNS = \r
+FILTER_SOURCE_FILES = NO\r
+#---------------------------------------------------------------------------\r
+# configuration options related to source browsing\r
+#---------------------------------------------------------------------------\r
+SOURCE_BROWSER = NO\r
+INLINE_SOURCES = NO\r
+STRIP_CODE_COMMENTS = YES\r
+REFERENCED_BY_RELATION = NO\r
+REFERENCES_RELATION = NO\r
+REFERENCES_LINK_SOURCE = YES\r
+USE_HTAGS = NO\r
+VERBATIM_HEADERS = NO\r
+#---------------------------------------------------------------------------\r
+# configuration options related to the alphabetical class index\r
+#---------------------------------------------------------------------------\r
+ALPHABETICAL_INDEX = NO\r
+COLS_IN_ALPHA_INDEX = 5\r
+IGNORE_PREFIX = \r
+#---------------------------------------------------------------------------\r
+# configuration options related to the HTML output\r
+#---------------------------------------------------------------------------\r
+GENERATE_HTML = YES\r
+HTML_OUTPUT = html\r
+HTML_FILE_EXTENSION = .html\r
+HTML_HEADER = ./docs/tiheader.htm\r
+HTML_FOOTER = ./docs/tifooter.htm\r
+HTML_STYLESHEET = \r
+GENERATE_HTMLHELP = YES\r
+GENERATE_DOCSET = NO\r
+DOCSET_FEEDNAME = "Doxygen generated docs"\r
+DOCSET_BUNDLE_ID = org.doxygen.Project\r
+HTML_DYNAMIC_SECTIONS = NO\r
+CHM_FILE = ..\..\gpiolldDocs.chm\r
+HHC_LOCATION = hhc.exe\r
+GENERATE_CHI = NO\r
+CHM_INDEX_ENCODING = \r
+BINARY_TOC = NO\r
+TOC_EXPAND = NO\r
+DISABLE_INDEX = NO\r
+ENUM_VALUES_PER_LINE = 4\r
+GENERATE_TREEVIEW = NONE\r
+TREEVIEW_WIDTH = 250\r
+FORMULA_FONTSIZE = 10\r
+#---------------------------------------------------------------------------\r
+# configuration options related to the LaTeX output\r
+#---------------------------------------------------------------------------\r
+GENERATE_LATEX = NO\r
+LATEX_OUTPUT = latex\r
+LATEX_CMD_NAME = latex\r
+MAKEINDEX_CMD_NAME = makeindex\r
+COMPACT_LATEX = NO\r
+PAPER_TYPE = a4wide\r
+EXTRA_PACKAGES = \r
+LATEX_HEADER = \r
+PDF_HYPERLINKS = YES\r
+USE_PDFLATEX = YES\r
+LATEX_BATCHMODE = NO\r
+LATEX_HIDE_INDICES = NO\r
+#---------------------------------------------------------------------------\r
+# configuration options related to the RTF output\r
+#---------------------------------------------------------------------------\r
+GENERATE_RTF = NO\r
+RTF_OUTPUT = rtf\r
+COMPACT_RTF = NO\r
+RTF_HYPERLINKS = NO\r
+RTF_STYLESHEET_FILE = \r
+RTF_EXTENSIONS_FILE = \r
+#---------------------------------------------------------------------------\r
+# configuration options related to the man page output\r
+#---------------------------------------------------------------------------\r
+GENERATE_MAN = NO\r
+MAN_OUTPUT = man\r
+MAN_EXTENSION = .3\r
+MAN_LINKS = NO\r
+#---------------------------------------------------------------------------\r
+# configuration options related to the XML output\r
+#---------------------------------------------------------------------------\r
+GENERATE_XML = NO\r
+XML_OUTPUT = xml\r
+XML_SCHEMA = \r
+XML_DTD = \r
+XML_PROGRAMLISTING = YES\r
+#---------------------------------------------------------------------------\r
+# configuration options for the AutoGen Definitions output\r
+#---------------------------------------------------------------------------\r
+GENERATE_AUTOGEN_DEF = NO\r
+#---------------------------------------------------------------------------\r
+# configuration options related to the Perl module output\r
+#---------------------------------------------------------------------------\r
+GENERATE_PERLMOD = NO\r
+PERLMOD_LATEX = NO\r
+PERLMOD_PRETTY = YES\r
+PERLMOD_MAKEVAR_PREFIX = \r
+#---------------------------------------------------------------------------\r
+# Configuration options related to the preprocessor \r
+#---------------------------------------------------------------------------\r
+ENABLE_PREPROCESSING = YES\r
+MACRO_EXPANSION = NO\r
+EXPAND_ONLY_PREDEF = NO\r
+SEARCH_INCLUDES = YES\r
+INCLUDE_PATH = \r
+INCLUDE_FILE_PATTERNS = \r
+PREDEFINED = \r
+EXPAND_AS_DEFINED = \r
+SKIP_FUNCTION_MACROS = YES\r
+#---------------------------------------------------------------------------\r
+# Configuration::additions related to external references \r
+#---------------------------------------------------------------------------\r
+TAGFILES = \r
+GENERATE_TAGFILE = \r
+ALLEXTERNALS = NO\r
+EXTERNAL_GROUPS = YES\r
+PERL_PATH = /usr/bin/perl\r
+#---------------------------------------------------------------------------\r
+# Configuration options related to the dot tool \r
+#---------------------------------------------------------------------------\r
+CLASS_DIAGRAMS = NO\r
+MSCGEN_PATH = \r
+HIDE_UNDOC_RELATIONS = YES\r
+HAVE_DOT = NO\r
+DOT_FONTPATH = \r
+CLASS_GRAPH = YES\r
+COLLABORATION_GRAPH = YES\r
+GROUP_GRAPHS = YES\r
+UML_LOOK = NO\r
+TEMPLATE_RELATIONS = NO\r
+INCLUDE_GRAPH = YES\r
+INCLUDED_BY_GRAPH = YES\r
+CALL_GRAPH = NO\r
+CALLER_GRAPH = NO\r
+GRAPHICAL_HIERARCHY = YES\r
+DIRECTORY_GRAPH = YES\r
+DOT_IMAGE_FORMAT = png\r
+DOT_PATH = \r
+DOTFILE_DIRS = \r
+DOT_GRAPH_MAX_NODES = 50\r
+MAX_DOT_GRAPH_DEPTH = 1000\r
+DOT_TRANSPARENT = YES\r
+DOT_MULTI_TARGETS = NO\r
+GENERATE_LEGEND = YES\r
+DOT_CLEANUP = YES\r
+#---------------------------------------------------------------------------\r
+# Configuration::additions related to the search engine \r
+#---------------------------------------------------------------------------\r
+SEARCHENGINE = NO\r
+\r
+\r
diff --git a/packages/ti/drv/gpio/docs/tifooter.htm b/packages/ti/drv/gpio/docs/tifooter.htm
--- /dev/null
@@ -0,0 +1,4 @@
+<hr size="1"><small>\r
+Copyright $year, Texas Instruments Incorporated</small>\r
+</body>\r
+</html>\r
diff --git a/packages/ti/drv/gpio/docs/tiheader.htm b/packages/ti/drv/gpio/docs/tiheader.htm
--- /dev/null
@@ -0,0 +1,12 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">\r
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">\r
+<title>$title</title>\r
+<link href="$relpath$doxygen.css" rel="stylesheet" type="text/css">\r
+<link href="$relpath$tabs.css" rel="stylesheet" type="text/css">\r
+</head><body>\r
+<table width=100%>\r
+<tr>\r
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../../tilogo.gif"></a></td>\r
+ <td bgcolor="red"><img src="../../titagline.gif"></td>\r
+</tr>\r
+</table>\r
diff --git a/packages/ti/drv/gpio/docs/tilogo.gif b/packages/ti/drv/gpio/docs/tilogo.gif
new file mode 100755 (executable)
index 0000000..f2fab2d
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index 0000000..f2fab2d
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diff --git a/packages/ti/drv/gpio/docs/titagline.gif b/packages/ti/drv/gpio/docs/titagline.gif
new file mode 100755 (executable)
index 0000000..743a024
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index 0000000..743a024
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diff --git a/packages/ti/drv/gpio/example/Module.xs b/packages/ti/drv/gpio/example/Module.xs
--- /dev/null
@@ -0,0 +1,57 @@
+/******************************************************************************\r
+ * FILE PURPOSE: GPIO LLD example files.\r
+ ******************************************************************************\r
+ * FILE NAME: module.xs\r
+ *\r
+ * DESCRIPTION: \r
+ * This file contains the module specification for GPIO LLD example files.\r
+ *\r
+ * Copyright (C) 2009, Texas Instruments, Inc.\r
+ *****************************************************************************/\r
+\r
+/* Load the library utility. */\r
+var libUtility = xdc.loadCapsule ("../build/buildlib.xs");\r
+\r
+/**************************************************************************\r
+ * FUNCTION NAME : modBuild\r
+ **************************************************************************\r
+ * DESCRIPTION :\r
+ * The function is used to add all the source files in the example \r
+ * directory into the package.\r
+ **************************************************************************/\r
+function modBuild() \r
+{\r
+ /* Add all the .c files to the release package. */\r
+ var exampleFiles = libUtility.listAllFiles (".c", "example", true);\r
+ for (var k = 0 ; k < exampleFiles.length; k++)\r
+ Pkg.otherFiles[Pkg.otherFiles.length++] = exampleFiles[k];\r
+\r
+ /* Add all the .h files to the release package. */\r
+ var exampleFiles = libUtility.listAllFiles (".h", "example", true);\r
+ for (var k = 0 ; k < exampleFiles.length; k++)\r
+ Pkg.otherFiles[Pkg.otherFiles.length++] = exampleFiles[k];\r
+\r
+ /* Add all the .cmd files to the release package. */\r
+ var exampleFiles = libUtility.listAllFiles (".cmd", "example", true);\r
+ for (var k = 0 ; k < exampleFiles.length; k++)\r
+ Pkg.otherFiles[Pkg.otherFiles.length++] = exampleFiles[k];\r
+\r
+ /* Add all the .cfg files to the release package. */\r
+ var exampleFiles = libUtility.listAllFiles (".cfg", "example", true);\r
+ for (var k = 0 ; k < exampleFiles.length; k++)\r
+ Pkg.otherFiles[Pkg.otherFiles.length++] = exampleFiles[k];\r
+\r
+ /* Add all the make files to the release package. */\r
+ var exampleFiles = libUtility.listAllFiles ("makefile", "example", true);\r
+ for (var k = 0 ; k < exampleFiles.length; k++)\r
+ Pkg.otherFiles[Pkg.otherFiles.length++] = exampleFiles[k];\r
+ /* Add the .txt to the package */\r
+ var exampleFiles = libUtility.listAllFiles (".txt", "example", true);\r
+ for (var k = 0 ; k < exampleFiles.length; k++)\r
+ Pkg.otherFiles[Pkg.otherFiles.length++] = exampleFiles[k];\r
+ /* Add all the .mk files to the release package. */\r
+ var mkFiles = libUtility.listAllFiles (".mk", "example", true);\r
+ for (var k = 0 ; k < mkFiles.length; k++)\r
+ Pkg.otherFiles[Pkg.otherFiles.length++] = mkFiles[k];\r
+\r
+}\r
diff --git a/packages/ti/drv/gpio/gpio_component.mk b/packages/ti/drv/gpio/gpio_component.mk
--- /dev/null
@@ -0,0 +1,281 @@
+#
+# Copyright (c) 2016-2018, Texas Instruments Incorporated
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# * Redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer.
+#
+# * Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution.
+#
+# * Neither the name of Texas Instruments Incorporated nor the names of
+# its contributors may be used to endorse or promote products derived
+# from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+# OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+# EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+
+# File: gpio_component.mk
+# This file is component include make file of GPIO rtosrary.
+# List of variables set in this file and their purpose:
+# <mod>_RELPATH - This is the relative path of the module, typically from
+# top-level directory of the package
+# <mod>_PATH - This is the absolute path of the module. It derives from
+# absolute path of the top-level directory (set in env.mk)
+# and relative path set above
+# <mod>_INCLUDE - This is the path that has interface header files of the
+# module. This can be multiple directories (space separated)
+# <mod>_PKG_LIST - Names of the modules (and sub-modules) that are a part
+# part of this module, including itself.
+# <mod>_BOARD_DEPENDENCY - "yes": means the code for this module depends on
+# board and the compiled obj/lib has to be kept
+# under <board> directory
+# "no" or "" or if this variable is not defined: means
+# this module has no board dependent code and hence
+# the obj/libs are not kept under <board> dir.
+# <mod>_CORE_DEPENDENCY - "yes": means the code for this module depends on
+# core and the compiled obj/rtos has to be kept
+# under <core> directory
+# "no" or "" or if this variable is not defined: means
+# this module has no core dependent code and hence
+# the obj/rtoss are not kept under <core> dir.
+# <mod>_APP_STAGE_FILES - List of source files that belongs to the module
+# <mod>, but that needs to be compiled at application
+# build stage (in the context of the app). This is
+# primarily for link time configurations or if the
+# source file is dependent on options/defines that are
+# application dependent. This can be left blank or
+# not defined at all, in which case, it means there
+# no source files in the module <mod> that are required
+# to be compiled in the application build stage.
+#
+ifeq ($(gpio_component_make_include), )
+
+# under other list
+drvgpio_BOARDLIST = am65xx_evm am65xx_idk j721e_sim j721e_evm
+drvgpio_SOCLIST = am574x am572x am571x dra72x dra75x dra78x k2h k2k k2l k2e k2g c6678 c6657 am437x am335x omapl137 omapl138 am65xx j721e
+drvgpio_SOCPROFILELIST = am574x am572x am571x dra72x dra75x dra78x k2h k2k k2l k2e k2g c6678 c6657 am437x am335x omapl137 omapl138
+drvgpio_am574x_CORELIST = c66x a15_0 ipu1_0
+drvgpio_am572x_CORELIST = c66x a15_0 ipu1_0
+drvgpio_am571x_CORELIST = c66x a15_0 ipu1_0
+drvgpio_dra72x_CORELIST = c66x a15_0 ipu1_0
+drvgpio_dra75x_CORELIST = c66x a15_0 ipu1_0
+drvgpio_dra78x_CORELIST = c66x ipu1_0
+drvgpio_k2h_CORELIST = c66x a15_0
+drvgpio_k2k_CORELIST = c66x a15_0
+drvgpio_k2l_CORELIST = c66x a15_0
+drvgpio_k2e_CORELIST = c66x a15_0
+drvgpio_k2g_CORELIST = c66x a15_0
+drvgpio_c6678_CORELIST = c66x
+drvgpio_c6657_CORELIST = c66x
+drvgpio_omapl137_CORELIST = c674x arm9_0
+drvgpio_omapl138_CORELIST = c674x arm9_0
+drvgpio_am437x_CORELIST = a9host
+drvgpio_am335x_CORELIST = a8host
+drvgpio_am65xx_CORELIST = mpu1_0 mcu1_0
+drvgpio_j721e_CORELIST = $(DEFAULT_j721e_CORELIST)
+drvgpio_j721e_CORELISTARM = mpu1_0 mcu1_0 mcu1_1 mcu2_0 mcu2_1 mcu3_0 mcu3_1
+############################
+# gpio package
+# List of components included under gpio rtos
+# The components included here are built and will be part of gpio rtos
+############################
+gpio_LIB_LIST = gpio gpio_indp gpio_profile gpio_profile_indp
+drvgpio_LIB_LIST = $(gpio_LIB_LIST)
+
+############################
+# gpio examples
+# List of examples under gpio
+# All the tests mentioned in list are built when test target is called
+# List below all examples for allowed values
+############################
+gpio_EXAMPLE_LIST = GPIO_Baremetal_LedBlink_TestApp GPIO_LedBlink_TestApp
+drvgpio_EXAMPLE_LIST = $(gpio_EXAMPLE_LIST)
+
+#
+# GPIO Modules
+#
+
+# GPIO LIB
+gpio_COMP_LIST = gpio
+gpio_RELPATH = ti/drv/gpio
+gpio_PATH = $(PDK_GPIO_COMP_PATH)
+gpio_LIBNAME = ti.drv.gpio
+export gpio_LIBNAME
+gpio_LIBPATH = $(gpio_PATH)/lib
+export gpio_LIBPATH
+gpio_OBJPATH = $(gpio_RELPATH)/gpio
+export gpio_OBJPATH
+gpio_MAKEFILE = -f build/makefile.mk
+export gpio_MAKEFILE
+gpio_BOARD_DEPENDENCY = no
+gpio_CORE_DEPENDENCY = no
+gpio_SOC_DEPENDENCY = yes
+export gpio_COMP_LIST
+export gpio_BOARD_DEPENDENCY
+export gpio_CORE_DEPENDENCY
+export gpio_SOC_DEPENDENCY
+gpio_PKG_LIST = gpio
+export gpio_PKG_LIST
+gpio_INCLUDE = $(gpio_PATH)
+gpio_SOCLIST = $(drvgpio_SOCLIST)
+export gpio_SOCLIST
+gpio_$(SOC)_CORELIST = $(drvgpio_$(SOC)_CORELIST)
+export gpio_$(SOC)_CORELIST
+
+# GPIO INDEPENDENT LIB
+gpio_indp_COMP_LIST = gpio_indp
+gpio_indp_RELPATH = ti/drv/gpio
+gpio_indp_PATH = $(PDK_GPIO_COMP_PATH)
+gpio_indp_LIBNAME = ti.drv.gpio
+export gpio_indp_LIBNAME
+gpio_indp_LIBPATH = $(gpio_indp_PATH)/lib
+export gpio_indp_LIBPATH
+gpio_indp_OBJPATH = $(gpio_indp_RELPATH)/gpio_indp
+export gpio_indp_OBJPATH
+gpio_indp_MAKEFILE = -f build/makefile_indp.mk
+export gpio_indp_MAKEFILE
+gpio_indp_BOARD_DEPENDENCY = no
+gpio_indp_CORE_DEPENDENCY = no
+gpio_indp_SOC_DEPENDENCY = no
+export gpio_indp_COMP_LIST
+export gpio_indp_BOARD_DEPENDENCY
+export gpio_indp_CORE_DEPENDENCY
+export gpio_indp_SOC_DEPENDENCY
+gpio_indp_PKG_LIST = gpio_indp
+export gpio_indp_PKG_LIST
+gpio_indp_INCLUDE = $(gpio_indp_PATH)
+gpio_indp_SOCLIST = $(drvgpio_SOCLIST)
+export gpio_indp_SOCLIST
+gpio_indp_$(SOC)_CORELIST = $(drvgpio_$(SOC)_CORELIST)
+export gpio_indp_$(SOC)_CORELIST
+
+# GPIO PROFILE LIB
+gpio_profile_COMP_LIST = gpio_profile
+gpio_profile_RELPATH = ti/drv/gpio
+gpio_profile_PATH = $(PDK_GPIO_COMP_PATH)
+gpio_profile_LIBNAME = ti.drv.gpio.profiling
+export gpio_profile_LIBNAME
+gpio_profile_LIBPATH = $(gpio_profile_PATH)/lib
+export gpio_profile_LIBPATH
+gpio_profile_OBJPATH = $(gpio_profile_RELPATH)/gpio_profile
+export gpio_profile_OBJPATH
+gpio_profile_MAKEFILE = -f build/makefile_profile.mk
+export gpio_profile_MAKEFILE
+gpio_profile_BOARD_DEPENDENCY = no
+gpio_profile_CORE_DEPENDENCY = no
+gpio_profile_SOC_DEPENDENCY = yes
+export gpio_profile_COMP_LIST
+export gpio_profile_BOARD_DEPENDENCY
+export gpio_profile_CORE_DEPENDENCY
+export gpio_profile_SOC_DEPENDENCY
+gpio_profile_PKG_LIST = gpio_profile
+export gpio_profile_PKG_LIST
+gpio_profile_INCLUDE = $(gpio_profile_PATH)
+gpio_profile_SOCLIST = $(drvgpio_SOCPROFILELIST)
+export gpio_profile_SOCLIST
+gpio_profile_$(SOC)_CORELIST = $(drvgpio_$(SOC)_CORELIST)
+export gpio_profile_$(SOC)_CORELIST
+
+# GPIO PROFILE INDEPENDENT LIB
+gpio_profile_indp_COMP_LIST = gpio_profile_indp
+gpio_profile_indp_RELPATH = ti/drv/gpio
+gpio_profile_indp_PATH = $(PDK_GPIO_COMP_PATH)
+gpio_profile_indp_LIBNAME = ti.drv.gpio.profiling
+export gpio_profile_indp_LIBNAME
+gpio_profile_indp_LIBPATH = $(gpio_profile_indp_PATH)/lib
+export gpio_profile_indp_LIBPATH
+gpio_profile_indp_OBJPATH = $(gpio_profile_indp_RELPATH)/gpio_profile_indp
+export gpio_profile_indp_OBJPATH
+gpio_profile_indp_MAKEFILE = -f build/makefile_profile_indp.mk
+export gpio_profile_indp_MAKEFILE
+gpio_profile_indp_BOARD_DEPENDENCY = no
+gpio_profile_indp_CORE_DEPENDENCY = no
+gpio_profile_indp_SOC_DEPENDENCY = no
+export gpio_profile_indp_COMP_LIST
+export gpio_profile_indp_BOARD_DEPENDENCY
+export gpio_profile_indp_CORE_DEPENDENCY
+export gpio_profile_indp_SOC_DEPENDENCY
+gpio_profile_indp_PKG_LIST = gpio_profile_indp
+export gpio_profile_indp_PKG_LIST
+gpio_profile_indp_INCLUDE = $(gpio_profile_indp_PATH)
+gpio_profile_indp_SOCLIST = $(drvgpio_SOCPROFILELIST)
+export gpio_profile_indp_SOCLIST
+gpio_profile_indp_$(SOC)_CORELIST = $(drvgpio_$(SOC)_CORELIST)
+export gpio_profile_indp_$(SOC)_CORELIST
+
+#
+# GPIO Examples
+#
+
+# GPIO baremetal Example led blink
+GPIO_Baremetal_LedBlink_TestApp_COMP_LIST = GPIO_Baremetal_LedBlink_TestApp
+GPIO_Baremetal_LedBlink_TestApp_RELPATH = ti/drv/gpio/test/led_blink
+GPIO_Baremetal_LedBlink_TestApp_PATH = $(PDK_GPIO_COMP_PATH)/test/led_blink
+GPIO_Baremetal_LedBlink_TestApp_BOARD_DEPENDENCY = yes
+GPIO_Baremetal_LedBlink_TestApp_CORE_DEPENDENCY = no
+GPIO_Baremetal_LedBlink_TestApp_MAKEFILE = -f makefile IS_BAREMETAL=yes
+export GPIO_Baremetal_LedBlink_TestApp_COMP_LIST
+export GPIO_Baremetal_LedBlink_TestApp_BOARD_DEPENDENCY
+export GPIO_Baremetal_LedBlink_TestApp_CORE_DEPENDENCY
+export GPIO_Baremetal_LedBlink_TestApp_MAKEFILE
+GPIO_Baremetal_LedBlink_TestApp_PKG_LIST = GPIO_Baremetal_LedBlink_TestApp
+GPIO_Baremetal_LedBlink_TestApp_INCLUDE = $(GPIO_Baremetal_LedBlink_TestApp_PATH)
+GPIO_Baremetal_LedBlink_TestApp_BOARDLIST = $(drvgpio_BOARDLIST)
+export GPIO_Baremetal_LedBlink_TestApp_BOARDLIST
+ifeq ($(SOC),$(filter $(SOC), j721e))
+GPIO_Baremetal_LedBlink_TestApp_$(SOC)_CORELIST = $(drvgpio_$(SOC)_CORELISTARM)
+else
+GPIO_Baremetal_LedBlink_TestApp_$(SOC)_CORELIST = $(drvgpio_$(SOC)_CORELIST)
+endif
+export GPIO_Baremetal_LedBlink_TestApp_$(SOC)_CORELIST
+ifeq ($(SOC),$(filter $(SOC), am65xx j721e))
+GPIO_Baremetal_LedBlink_TestApp_SBL_APPIMAGEGEN = yes
+export GPIO_Baremetal_LedBlink_TestApp_SBL_APPIMAGEGEN
+endif
+
+# GPIO rtos Example led blink
+GPIO_LedBlink_TestApp_COMP_LIST = GPIO_LedBlink_TestApp
+GPIO_LedBlink_TestApp_RELPATH = ti/drv/gpio/test/led_blink
+GPIO_LedBlink_TestApp_PATH = $(PDK_GPIO_COMP_PATH)/test/led_blink
+GPIO_LedBlink_TestApp_BOARD_DEPENDENCY = yes
+GPIO_LedBlink_TestApp_CORE_DEPENDENCY = no
+GPIO_LedBlink_TestApp_MAKEFILE = -f makefile
+GPIO_LedBlink_TestApp_XDC_CONFIGURO = yes
+export GPIO_LedBlink_TestApp_COMP_LIST
+export GPIO_LedBlink_TestApp_BOARD_DEPENDENCY
+export GPIO_LedBlink_TestApp_CORE_DEPENDENCY
+export GPIO_LedBlink_TestApp_XDC_CONFIGURO
+GPIO_LedBlink_TestApp_PKG_LIST = GPIO_LedBlink_TestApp
+GPIO_LedBlink_TestApp_INCLUDE = $(GPIO_LedBlink_TestApp_PATH)
+GPIO_LedBlink_TestApp_BOARDLIST = $(drvgpio_BOARDLIST)
+export GPIO_LedBlink_TestApp_BOARDLIST
+GPIO_LedBlink_TestApp_$(SOC)_CORELIST = $(gpio_$(SOC)_CORELIST)
+export GPIO_LedBlink_TestApp_$(SOC)_CORELIST
+ifeq ($(SOC),$(filter $(SOC), am65xx j721e))
+GPIO_LedBlink_TestApp_SBL_APPIMAGEGEN = yes
+export GPIO_LedBlink_TestApp_SBL_APPIMAGEGEN
+endif
+
+export drvgpio_LIB_LIST
+export drvgpio_EXAMPLE_LIST
+export gpio_LIB_LIST
+export gpio_EXAMPLE_LIST
+
+gpio_component_make_include := 1
+endif
diff --git a/packages/ti/drv/gpio/makefile b/packages/ti/drv/gpio/makefile
--- /dev/null
@@ -0,0 +1,46 @@
+#
+# Copyright (c) 2016, Texas Instruments Incorporated
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# * Redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer.
+#
+# * Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution.
+#
+# * Neither the name of Texas Instruments Incorporated nor the names of
+# its contributors may be used to endorse or promote products derived
+# from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+# OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+# EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+
+ifeq ($(RULES_MAKE), )
+include $(PDK_INSTALL_PATH)/ti/build/Rules.make
+else
+include $(RULES_MAKE)
+endif
+
+COMP = drvgpio
+
+lib_$(COMP)_BUILD_DEPENDENCY = soc
+
+$(COMP)_DOXYGEN_SUPPORT = yes
+
+include $(PDK_INSTALL_PATH)/ti/build/comp_top.mk
+
diff --git a/packages/ti/drv/gpio/package.bld b/packages/ti/drv/gpio/package.bld
--- /dev/null
@@ -0,0 +1,127 @@
+/******************************************************************************\r
+ * FILE PURPOSE: Build description for the gpio Driver\r
+ ******************************************************************************\r
+ * FILE NAME: package.bld\r
+ *\r
+ * DESCRIPTION: \r
+ * This file contains the build specification and description for the gpio driver\r
+ * \r
+ * The file takes the following parameters from the command line through the\r
+ * XDCARGS variable.\r
+ * XDCARGS[0] = Driver Install Type \r
+ * Valid Values are "TAR" or "SETUP"\r
+ * DEFAULT is "SETUP"\r
+ *\r
+ * Example for a valid command:\r
+ * xdc XDCARGS="SETUP" release \r
+ *\r
+ * Copyright (C) 2014-2015, Texas Instruments, Inc.\r
+ *****************************************************************************/\r
+\r
+/* List of all subdirectories that combine to make the gpio Socket Driver Package. */\r
+var subDirectories = [ "src", "docs", "test", "example", "soc" ];\r
+\r
+var driverInstallType;\r
+\r
+/* Determine if we need to create the InstallJammer Application or not? \r
+ * gpio LLD Deliverables be either of the following formats:\r
+ * - TAR Ball Package\r
+ * - Setup Executable \r
+ * DEFAULT is a SETUP Executable. */\r
+\r
+if ((arguments[0] != "TAR") && (arguments[0] != "SETUP"))\r
+ driverInstallType = "TAR";\r
+else\r
+ driverInstallType = arguments[0];\r
+\r
+/* Irrespective of the InstallType we always create a TAR Ball Package as a part\r
+ * of the RTSC Build. Here we determine the name of the TAR Ball Package\r
+ * Format is as follows:\r
+ * gpio_<version> */\r
+var gpioRTSCFileName = "gpio" + "_" + \r
+ driverReleaseVersion[0] + "_" + driverReleaseVersion[1] + "_" + \r
+ driverReleaseVersion[2] + "_" + driverReleaseVersion[3];\r
+\r
+/******************************************************************\r
+ ************************ Release Banner **************************\r
+ ******************************************************************/\r
+\r
+print ("************* gpio Socket Driver Build Information *************");\r
+print ("gpio Socket Driver Install : " + driverInstallType);\r
+print ("gpio Socket Driver LLD Version : " + driverReleaseVersion);\r
+print ("RTSC File Name : " + gpioRTSCFileName);\r
+print ("gpio Socket Driver LLD Path : " + driverPath);\r
+print ("C66 Tools Directory : " + c66ToolsBaseDir);\r
+print ("M4 Tools Directory : " + m4ToolsBaseDir);\r
+print ("A15 Tools Directory : " + a15ToolsBaseDir);\r
+if (pOpts == 1) \r
+{ \r
+ print ("CC LE opts : " + C66LE.ccOpts.prefix);\r
+ print ("CC BE opts : " + C66BE.ccOpts.prefix);\r
+ print ("M4 LE opts : " + M4LE.ccOpts.prefix);\r
+ print ("A15 basic opts : " + A15LE.ccOpts.prefix);\r
+}\r
+print ("****************************************************************");\r
+\r
+/* Create the release package for the gpio LLD */\r
+Pkg.defaultRelease = Pkg.addRelease (gpioRTSCFileName, {prefix: "./packages/"});\r
+\r
+/* Moving forward we need to set the Archiver of the package to be ZIP. This is currently\r
+ * not supported in the XDC tools being used. Currenly builds need to be done with the \r
+ * following options:-\r
+ * xdc MK_FIXLISTOPTS=-t release \r
+ * ZIP is a better option as it works natively with INSTALL Jammer and we can remove the\r
+ * uncompression into a temporary directory. XDC Tools with xdc-rXX support the ZIP archiver. */\r
+//Pkg.attrs = {archiver : "zip"};\r
+\r
+/* Cycle through all the sub-directories and build all the files */\r
+for (var i = 0; i < subDirectories.length; i++) \r
+{\r
+ /* Load the capsule in the sub directory. */\r
+ var caps = xdc.loadCapsule (subDirectories[i]+"/Module.xs");\r
+\r
+ print ("Building directory " + subDirectories[i]);\r
+\r
+ /* Build the capsule. */\r
+ caps.modBuild();\r
+\r
+ /* Package the module.xs files for building via package */\r
+ Pkg.otherFiles[Pkg.otherFiles.length++] = subDirectories[i]+"/Module.xs";\r
+}\r
+\r
+/* Package the remaining files */\r
+Pkg.otherFiles[Pkg.otherFiles.length++] = "config.bld";\r
+Pkg.otherFiles[Pkg.otherFiles.length++] = "config_mk.bld";\r
+Pkg.otherFiles[Pkg.otherFiles.length++] = "package.bld";\r
+Pkg.otherFiles[Pkg.otherFiles.length++] = "package.xdc";\r
+Pkg.otherFiles[Pkg.otherFiles.length++] = "package.xs";\r
+Pkg.otherFiles[Pkg.otherFiles.length++] = "Settings.xdc";\r
+Pkg.otherFiles[Pkg.otherFiles.length++] = "Settings.xdc.xdt";\r
+Pkg.otherFiles[Pkg.otherFiles.length++] = "GPIO.h";\r
+Pkg.otherFiles[Pkg.otherFiles.length++] = "GPIOver.h";\r
+Pkg.otherFiles[Pkg.otherFiles.length++] = "GPIOver.h.xdt";\r
+Pkg.otherFiles[Pkg.otherFiles.length++] = "docs/Doxyfile";\r
+Pkg.otherFiles[Pkg.otherFiles.length++] = "docs/doxyfile.xdt";\r
+Pkg.otherFiles[Pkg.otherFiles.length++] = "build/buildlib.xs";\r
+Pkg.otherFiles[Pkg.otherFiles.length++] = "makefile";\r
+Pkg.otherFiles[Pkg.otherFiles.length++] = "build/makefile.mk";\r
+Pkg.otherFiles[Pkg.otherFiles.length++] = "build/makefile_indp.mk";\r
+Pkg.otherFiles[Pkg.otherFiles.length++] = "build/makefile_profile_indp.mk";\r
+Pkg.otherFiles[Pkg.otherFiles.length++] = "build/makefile_profile.mk";\r
+Pkg.otherFiles[Pkg.otherFiles.length++] = "src/src_files_common.mk";\r
+Pkg.otherFiles[Pkg.otherFiles.length++] = "gpio_component.mk";\r
+Pkg.otherFiles[Pkg.otherFiles.length++] = "./lib";\r
+\r
+/* Generate Users Manual Doxyfile */\r
+var tplt = xdc.loadTemplate("./docs/doxyfile.xdt");\r
+tplt.genFile("./docs/Doxyfile",driverReleaseVersion); \r
+\r
+/* Generate Settings.xdc */\r
+var tplt = xdc.loadTemplate("./Settings.xdc.xdt");\r
+tplt.genFile("./Settings.xdc",driverReleaseVersion); \r
+\r
+/* Generate paver.h */\r
+var tplt = xdc.loadTemplate("./GPIOver.h.xdt");\r
+tplt.genFile("./GPIOver.h",driverReleaseVersion); \r
+\r
+ \r
diff --git a/packages/ti/drv/gpio/package.xdc b/packages/ti/drv/gpio/package.xdc
--- /dev/null
@@ -0,0 +1,16 @@
+/******************************************************************************\r
+ * FILE PURPOSE: Package specification file \r
+ ******************************************************************************\r
+ * FILE NAME: package.xdc\r
+ *\r
+ * DESCRIPTION: \r
+ * This file contains the package specification for the gpio Driver\r
+ *\r
+ * Copyright (C) 2015 - 2019, Texas Instruments, Inc.\r
+ *****************************************************************************/\r
+\r
+\r
+package ti.drv.gpio[1, 0, 0, 16] {\r
+ module Settings;\r
+}\r
+\r
diff --git a/packages/ti/drv/gpio/package.xs b/packages/ti/drv/gpio/package.xs
--- /dev/null
@@ -0,0 +1,137 @@
+/*\r
+ * ======== package.xs ========\r
+ *\r
+ */\r
+\r
+\r
+/*\r
+ * ======== Package.getLibs ========\r
+ * This function is called when a program's configuration files are\r
+ * being generated and it returns the name of a library appropriate\r
+ * for the program's configuration.\r
+ */\r
+\r
+function getLibs(prog)\r
+{\r
+ var suffix = prog.build.target.suffix;\r
+ var name = "";\r
+ var socType = this.Settings.socType;\r
+ var profilingTag = "";\r
+\r
+ socType = socType.toLowerCase();\r
+ /* Replace the last charecter in SoC am#### to am###x */\r
+ if (socType.substring(0, 2) == "am")\r
+ {\r
+ socType = socType.substring(0, socType.length - 1);\r
+ socType = socType.concat("x");\r
+ }\r
+\r
+ if (this.Settings.enableProfiling == true)\r
+ {\r
+ profilingTag = ".profiling"\r
+ }\r
+ name = this.$name + profilingTag + ".a" + suffix;\r
+ \r
+ /* Read LIBDIR variable */\r
+ var lib = java.lang.System.getenv("LIBDIR");\r
+\r
+ /* If NULL, default to "lib" folder */\r
+ if (lib == null)\r
+ {\r
+ lib = "./lib";\r
+ } else {\r
+ print ("\tSystem environment LIBDIR variable defined : " + lib);\r
+ }\r
+ \r
+ var socTypes = [ \r
+ 'am571x',\r
+ 'am572x',\r
+ 'am574x',\r
+ 'am335x',\r
+ 'am437x',\r
+ 'dra72x',\r
+ 'dra75x',\r
+ 'dra78x',\r
+ 'k2h',\r
+ 'k2k',\r
+ 'k2e',\r
+ 'k2l',\r
+ 'k2g',\r
+ 'omapl137',\r
+ 'omapl138',\r
+ 'c6678',\r
+ 'c6657',\r
+ 'c6747',\r
+ 'am65xx',\r
+ 'j721e'\r
+ ];\r
+\r
+ /* Get the SOC */\r
+ for each (var soc in socTypes)\r
+ {\r
+ if (socType.equals(soc))\r
+ {\r
+ lib = lib + "/" + soc;\r
+ name = this.$name + profilingTag + ".a" + suffix; \r
+ break;\r
+ }\r
+ }\r
+\r
+ /* Get target folder, if applicable */\r
+ if ( java.lang.String(suffix).contains('66') )\r
+ lib = lib + "/c66";\r
+ else if (java.lang.String(suffix).contains('674') )\r
+ lib = lib + "/c674";\r
+ else if (java.lang.String(suffix).contains('a15') )\r
+ lib = lib + "/a15";\r
+ else if (java.lang.String(suffix).contains('m4') )\r
+ lib = lib + "/m4";\r
+ else if (java.lang.String(suffix).contains('a9') )\r
+ lib = lib + "/a9";\r
+ else if (java.lang.String(suffix).contains('a8') )\r
+ lib = lib + "/a8"; \r
+ else if (java.lang.String(suffix).contains('e9') )\r
+ lib = lib + "/arm9";\r
+ else if (java.lang.String(suffix).contains('a53'))\r
+ lib = lib + "/a53";\r
+ else if (java.lang.String(suffix).contains('r5f'))\r
+ lib = lib + "/r5f";\r
+ else\r
+ throw new Error("\tUnknown target for: " + this.packageBase + lib);\r
+\r
+ var libProfiles = ["debug", "release"];\r
+ /* get the configured library profile */\r
+ for each(var profile in libProfiles)\r
+ {\r
+ if (this.Settings.libProfile.equals(profile))\r
+ {\r
+ lib = lib + "/" + profile;\r
+ break;\r
+ }\r
+ } \r
+\r
+ /* Get library name with path */\r
+ lib = lib + "/" + name;\r
+ if (java.io.File(this.packageBase + lib).exists()) {\r
+ print ("\tLinking with library " + this.$name + ":" + lib);\r
+ return lib;\r
+ }\r
+\r
+ /* Could not find any library, throw exception */\r
+ throw new Error("\tLibrary not found: " + this.packageBase + lib);\r
+}\r
+\r
+function init() {\r
+xdc.loadPackage("ti.osal");\r
+xdc.loadPackage("ti.csl");\r
+}\r
+\r
+/*\r
+ * ======== package.close ========\r
+ */\r
+function close()\r
+{ \r
+ if (xdc.om.$name != 'cfg') {\r
+ return;\r
+ }\r
+}\r
diff --git a/packages/ti/drv/gpio/soc/GPIO_soc.h b/packages/ti/drv/gpio/soc/GPIO_soc.h
--- /dev/null
@@ -0,0 +1,75 @@
+/**
+ * @file GPIO_soc.h
+ *
+ * @brief GPIO SoC level driver
+ */
+/*
+ * Copyright (c) 2015 - 2018, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef GPIO__SOC__H
+#define GPIO__SOC__H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <ti/drv/gpio/GPIO.h>
+#include <ti/osal/osal.h>
+#if defined(SOC_K2H) || defined(SOC_K2K) || defined(SOC_K2L) || defined(SOC_K2E) || defined(SOC_K2G) || defined(SOC_C6678) || defined(SOC_C6657) || defined(SOC_OMAPL137) || defined(SOC_OMAPL138) || defined(SOC_AM65XX) || defined(SOC_J721E)
+#include <ti/drv/gpio/src/v0/GPIO_v0.h>
+#endif
+
+#if defined(SOC_AM574x) || defined(SOC_AM572x) || defined(SOC_AM571x) || defined(SOC_AM335x) || defined(SOC_AM437x) || defined(SOC_DRA72x) || defined(SOC_DRA75x) || defined(SOC_DRA78x)
+#include <ti/drv/gpio/soc/GPIO_v1.h>
+#include <ti/csl/src/ip/gpio/V1/gpio_v2.h>
+#endif
+
+/* GPIO SoC level API */
+#if defined(SOC_K2H) || defined(SOC_K2K) || defined(SOC_K2L) || defined(SOC_K2E) || defined(SOC_K2G) || defined(SOC_C6678) || defined(SOC_C6657) || defined(SOC_OMAPL137) || defined(SOC_OMAPL138) || defined(SOC_AM65XX) || defined(SOC_J721E)
+extern int32_t GPIO_socGetInitCfg(uint32_t idx, GPIO_v0_HwAttrs *cfg);
+extern int32_t GPIO_socSetInitCfg(uint32_t idx, const GPIO_v0_HwAttrs *cfg);
+extern void GPIO_socGetNumPinsPorts(uint32_t *numPins, uint32_t *numPorts);
+#endif
+
+#if defined(SOC_K2G)
+extern int32_t GPIO_socSetIntMux(uint32_t index, uint32_t pinNum, const GPIO_IntCfg *cfg, uint32_t muxEvtSel);
+#endif
+
+#if defined(SOC_OMAPL137) || defined(SOC_OMAPL138)
+extern int32_t GPIO_socSetBankInt(uint32_t index, uint32_t pinNum, const GPIO_IntCfg *cfg);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* GPIO__SOC__H */
diff --git a/packages/ti/drv/gpio/soc/GPIO_v1.h b/packages/ti/drv/gpio/soc/GPIO_v1.h
--- /dev/null
@@ -0,0 +1,213 @@
+/*
+ * Copyright (c) 2014-2015, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/** ============================================================================
+ * @file GPIO_v1.h
+ *
+ * @brief GPIO driver
+ *
+ * The GPIO header file should be included in an application as follows:
+ * @code
+ * #include <ti/drv/gpio/soc/GPIO_v1.h>
+ * @endcode
+ *
+ * # Operation #
+ *
+ * The GPIO module allows you to manage General Purpose I/O pins via simple
+ * and portable APIs. The application is required to supply a GPIO_v1_Config
+ * structure to the module (see example below). This structure communicates to
+ * the GPIO module how to configure the pins used by the application (See the
+ * description of GPIO_PinConfig in the GPIO.h file).
+ *
+ * The application is required to call GPIO_init(). This function will
+ * initialize all the GPIO pins defined in the GPIO_PinConfig table to the
+ * configurations specified. Once completed the other APIs can be used to
+ * access the pins.
+ *
+ * Asserts are used to verify that the driver has been initialized, and is
+ * reading/writing a valid index.
+ *
+ * The following is an example of the code required to use 2 LEDs on an
+ * AM57X IDK board.
+ *
+ * Board header file:
+ * @code
+ * // Enum of GPIO names on the AM57X IDK EVM dev board
+ * typedef enum AM57X_IDK_EVM_GPIOName {
+ * AM57X_IDK_EVM_GRN_LED = 0,
+ * AM57X_IDK_EVM_YEL_LED,
+ * } AM57X_IDK_EVM_GPIOName;
+ * @endcode
+ *
+ * Board initialization code:
+ * @code
+ * #include <ti/drv/GPIO.h>
+ * #include <ti/drv/gpio/soc/GPIO_v1.h>
+ *
+ * // Array of pin configurations
+ * // NOTE: The order of the pin configurations must coincide with what was
+ * // defined in header file.
+ * // NOTE: Pins not used for interrupts should be placed at the end of the
+ * array. Callback entries can be omitted from callbacks array to
+ * reduce memory usage.
+ * const GPIO_PinConfig gpioPinConfigs[] = {
+ * // Input pins
+ * // AM57X_IDK_LED_GRN
+ * AM57X_IDK_GPIO_GRN_PIN | GPIO_CFG_IN_INT_RISING | GPIO_CFG_INPUT,
+ *
+ * // Output pins
+ * // AM57X_IDK_LED_YEL
+ * AM57X_IDK_GPIO_YEL_PIN | GPIO_CFG_OUTPUT,
+ * };
+ *
+ * // Array of callback function pointers
+ * // NOTE: The order of the pin configurations must coincide with what was
+ * // defined in header file.
+ * // NOTE: Pins not used for interrupts can be omitted from callbacks array to
+ * reduce memory usage (if placed at end of gpioPinConfigs array).
+ * const GPIO_callbackFxn gpioCallbackFunctions[] = {
+ * NULL, // AM57X_IDK_LED_GRN
+ * NULL
+ * };
+ *
+ * // The device-specific GPIO_config structure
+ * const GPIO_v1_Config GPIO_v1_config = {
+ * .pinConfigs = (GPIO_PinConfig *) gpioPinConfigs,
+ * .callbacks = (GPIO_CallbackFxn *) gpioCallbackFunctions,
+ * .numberOfPinConfigs = sizeof(gpioPinConfigs) / sizeof(GPIO_PinConfig),
+ * .numberOfCallbacks = sizeof(gpioCallbackFunctions) / sizeof(GPIO_CallbackFxn),
+ * .intPriority = (~0)
+ * };
+ *
+ * // Initialize peripheral and pins using the following init API.
+ *
+ * GPIO_init();
+ *
+ * @endcode
+ *
+ * Keep in mind that the callback functions will be called in the context of
+ * an interrupt service routine and should be designed accordingly. When an
+ * interrupt is triggered, the interrupt status of all (interrupt enabled) pins
+ * on a port will be read, cleared, and the respective callbacks will be
+ * executed. Callbacks will be called in order from least significant bit to
+ * most significant bit.
+ *
+ * ============================================================================
+ */
+
+#ifndef GPIO__V1__H
+#define GPIO__V1__H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+#include <ti/drv/gpio/GPIO.h>
+
+/* Mask for GPIO pin number */
+#define GPIO_CFG_PIN_NUM_MASK (0x000000FFU)
+
+/* Shift for GPIO pin number */
+#define GPIO_CFG_PIN_NUM_SHIFT (0x00U)
+
+/* Mask for GPIO port number */
+#define GPIO_CFG_PORT_NUM_MASK (0x0000FF00U)
+
+/* Shift for GPIO port number */
+#define GPIO_CFG_PORT_NUM_SHIFT (0x8U)
+
+/* Macro to formulated device specific port pin configuration */
+#define GPIO_DEVICE_CONFIG(port, pin) \
+ ((((port) << GPIO_CFG_PORT_NUM_SHIFT) &(GPIO_CFG_PORT_NUM_MASK)) | \
+ (((pin) << GPIO_CFG_PIN_NUM_SHIFT) & (GPIO_CFG_PIN_NUM_MASK)))
+
+
+/*!
+ * @brief GPIO Am57x Hardware attributes
+ */
+typedef struct GPIO_v1_HwAttrs_s {
+ /*! GPIO Peripheral base address */
+ uint32_t baseAddr;
+ /*! GPIO Peripheral interrupt vector */
+ uint32_t line1IntNum;
+ /*! GPIO Peripheral interrupt vector */
+ uint32_t line2IntNum;
+ /*! GPIO Peripheral interrupt vector */
+ uint32_t line1EventId;
+ /*! GPIO Peripheral interrupt vector */
+ uint32_t line2EventId;
+} GPIO_v1_HwAttrs;
+
+/* Avoid Misra warning "MISRA.DECL.ARRAY_SIZE" by pairing config array type
+ * with its array size to avoid externs with [] (no size) */
+#define GPIO_MAX_HWATTRS_CNT (8U)
+typedef GPIO_v1_HwAttrs GPIO_v1_hwAttrs_list[GPIO_MAX_HWATTRS_CNT];
+
+/*!
+ * @brief GPIO device specific driver configuration structure
+ */
+typedef struct GPIO_v1_Config_s {
+ /*! Pointer to the board's PinConfig array */
+ GPIO_PinConfig *pinConfigs;
+
+ /*! Pointer to the board's callback array */
+ GPIO_CallbackFxn *callbacks;
+
+ /*! Number of pin configs defined */
+ uint32_t numberOfPinConfigs;
+
+ /*! Number of callbacks defined */
+ uint32_t numberOfCallbacks;
+
+ /*! Interrupt priority used for call back interrupts. Setting ~0 will
+ * configure the lowest possible priority
+ */
+ uint32_t intPriority;
+} GPIO_v1_Config;
+
+/*!
+ * @brief Device specific port/pin definition macros
+ *
+ * Below are the port/pin definitions to be used within the board's pin
+ * configuration table. These macros should be OR'd in with the respective pin
+ * configuration settings.
+ */
+#define GPIO_v1_EMPTY_PIN 0x0000
+
+extern const GPIO_FxnTable GPIO_FxnTable_v1;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _GPIO_V1_H */
diff --git a/packages/ti/drv/gpio/soc/Module.xs b/packages/ti/drv/gpio/soc/Module.xs
--- /dev/null
@@ -0,0 +1,38 @@
+/******************************************************************************\r
+ * FILE PURPOSE: gpio LLD soc files.\r
+ ******************************************************************************\r
+ * FILE NAME: module.xs\r
+ *\r
+ * DESCRIPTION: \r
+ * This file contains the module specification for gpio LLD soc files.\r
+ *\r
+ * Copyright (C) 2009, Texas Instruments, Inc.\r
+ *****************************************************************************/\r
+\r
+/* Load the library utility. */\r
+var libUtility = xdc.loadCapsule ("../build/buildlib.xs");\r
+\r
+/**************************************************************************\r
+ * FUNCTION NAME : modBuild\r
+ **************************************************************************\r
+ * DESCRIPTION :\r
+ * The function is used to add all the source files in the soc \r
+ * directory into the package.\r
+ **************************************************************************/\r
+function modBuild() \r
+{\r
+ /* Add all the .c files to the release package. */\r
+ var configFiles = libUtility.listAllFiles (".c", "soc", true);\r
+ for (var k = 0 ; k < configFiles.length; k++)\r
+ Pkg.otherFiles[Pkg.otherFiles.length++] = configFiles[k];\r
+\r
+ /* Add all the .h files to the release package. */\r
+ var configFiles = libUtility.listAllFiles (".h", "soc", true);\r
+ for (var k = 0 ; k < configFiles.length; k++)\r
+ Pkg.otherFiles[Pkg.otherFiles.length++] = configFiles[k];\r
+ /* Add all the .mk files to the release package. */\r
+ var mkFiles = libUtility.listAllFiles (".mk", "soc", true);\r
+ for (var k = 0 ; k < mkFiles.length; k++)\r
+ Pkg.otherFiles[Pkg.otherFiles.length++] = mkFiles[k];\r
+\r
+}\r
diff --git a/packages/ti/drv/gpio/soc/am335x/GPIO_soc.c b/packages/ti/drv/gpio/soc/am335x/GPIO_soc.c
--- /dev/null
@@ -0,0 +1,108 @@
+/**
+ * \file am335x/GPIO_soc.c
+ *
+ * \brief AM335x SOC specific GPIO hardware attributes.
+ *
+ * This file contains the GPIO hardware attributes like base address and
+ * interrupt ids.
+ */
+
+/*
+ * Copyright (C) 2014-2015 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+#include <ti/csl/csl_utils.h>
+#include <ti/drv/gpio/GPIO.h>
+#include <ti/starterware/include/hw/soc_am335x.h>
+#include <ti/csl/csl_types.h>
+#include <ti/drv/gpio/soc/GPIO_soc.h>
+
+/* Number of GPIO ports */
+#define CSL_GPIO_PER_CNT 4U
+
+/* GPIO Driver hardware attributes */
+GPIO_v1_hwAttrs_list GPIO_v1_hwAttrs = {
+ {
+ SOC_GPIO_0_REGS,
+ 96,
+ 97,
+ 0,
+ 0
+ },
+ {
+ SOC_GPIO_1_REGS,
+ 98,
+ 99,
+ 0,
+ 0
+ },
+ {
+ SOC_GPIO_2_REGS,
+ 32,
+ 33,
+ 0,
+ 0
+ },
+ {
+ SOC_GPIO_3_REGS,
+ 62,
+ 63,
+ 0,
+ 0
+ },
+ /* "pad to full predefined length of array" */
+ { 0,0,0,0,0 },
+ { 0,0,0,0,0 },
+ { 0,0,0,0,0 },
+ { 0,0,0,0,0 },
+};
+
+/* GPIO configuration structure */
+CSL_PUBLIC_CONST GPIOConfigList GPIO_config =
+{
+ {
+ &GPIO_FxnTable_v1,
+ NULL,
+ NULL
+ },
+ /* "pad to full predefined length of array" */
+ {
+ NULL,
+ NULL,
+ NULL
+ },
+ {
+ NULL,
+ NULL,
+ NULL
+ }
+};
+
diff --git a/packages/ti/drv/gpio/soc/am437x/GPIO_soc.c b/packages/ti/drv/gpio/soc/am437x/GPIO_soc.c
--- /dev/null
@@ -0,0 +1,125 @@
+/**
+ * \file am437x/GPIO_soc.c
+ *
+ * \brief AM437x SOC specific GPIO hardware attributes.
+ *
+ * This file contains the GPIO hardware attributes like base address and
+ * interrupt ids.
+ */
+
+/*
+ * Copyright (C) 2014-2015 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+#include <ti/csl/csl_utils.h>
+#include <ti/drv/gpio/GPIO.h>
+#include <ti/starterware/include/hw/am437x.h>
+#include <ti/csl/csl_types.h>
+#include <ti/drv/gpio/soc/GPIO_soc.h>
+
+/* Number of GPIO ports */
+#define CSL_GPIO_PER_CNT 6U
+
+/* GPIO Driver hardware attributes */
+GPIO_v1_hwAttrs_list GPIO_v1_hwAttrs = {
+ {
+ SOC_GPIO0_REG,
+ 128,
+ 129,
+ 0,
+ 0
+ },
+ {
+ /* GPIO 1*/
+ SOC_GPIO1_REG,
+ 130,
+ 131,
+ 0,
+ 0
+ },
+ {
+ /* GPIO 2*/
+ SOC_GPIO2_REG,
+ 64,
+ 65,
+ 0,
+ 0
+ },
+ {
+ /* GPIO 3*/
+ SOC_GPIO3_REG,
+ 94,
+ 95,
+ 0,
+ 0
+ },
+ {
+ /* GPIO 4*/
+ SOC_GPIO4_REG,
+ 138,
+ 139,
+ 0,
+ 0
+ },
+ {
+ /* GPIO 5*/
+ SOC_GPIO5_REG,
+ 180,
+ 181,
+ 0,
+ 0
+ },
+ /* "pad to full predefined length of array" */
+ { 0,0,0,0,0 },
+ { 0,0,0,0,0 },
+};
+
+/* GPIO configuration structure */
+CSL_PUBLIC_CONST GPIOConfigList GPIO_config =
+{
+ {
+ &GPIO_FxnTable_v1,
+ NULL,
+ NULL
+ },
+ /* "pad to full predefined length of array" */
+ {
+ NULL,
+ NULL,
+ NULL
+ },
+ {
+ NULL,
+ NULL,
+ NULL
+ }
+};
+
diff --git a/packages/ti/drv/gpio/soc/am571x/GPIO_soc.c b/packages/ti/drv/gpio/soc/am571x/GPIO_soc.c
--- /dev/null
@@ -0,0 +1,196 @@
+/**
+ * \file am571x/GPIO_soc.c
+ *
+ * \brief AM571x SOC specific GPIO hardware attributes.
+ *
+ * This file contains the GPIO hardware attributes like base address and
+ * interrupt ids.
+ */
+
+/*
+ * Copyright (C) 2014-2015 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include <ti/csl/csl_utils.h>
+#include <ti/csl/soc/am571x/src/cslr_soc.h>
+#include <ti/csl/csl_types.h>
+#include <ti/drv/gpio/GPIO.h>
+#include <ti/drv/gpio/soc/GPIO_soc.h>
+
+/* Number of GPIO ports */
+#define CSL_GPIO_PER_CNT 8U
+
+/* GPIO Driver hardware attributes */
+GPIO_v1_hwAttrs_list GPIO_v1_hwAttrs = {
+ {
+#ifdef _TMS320C6X
+ CSL_DSP_GPIO1_REGS,
+ OSAL_REGINT_INTVEC_EVENT_COMBINER,
+#elif defined(__ARM_ARCH_7A__)
+ CSL_MPU_GPIO1_REGS,
+ 61,
+#else
+ CSL_IPU_GPIO1_REGS,
+ 51,
+#endif
+ 0,
+ 55,
+ 0
+ },
+ {
+#ifdef _TMS320C6X
+ CSL_DSP_GPIO2_REGS,
+ OSAL_REGINT_INTVEC_EVENT_COMBINER,
+#elif defined(__ARM_ARCH_7A__)
+ CSL_MPU_GPIO2_REGS,
+ 62,
+#else
+ CSL_IPU_GPIO2_REGS,
+ 52,
+#endif
+ 0,
+ 56,
+ 0
+ },
+ {
+#ifdef _TMS320C6X
+ CSL_DSP_GPIO3_REGS,
+ OSAL_REGINT_INTVEC_EVENT_COMBINER,
+#elif defined(__ARM_ARCH_7A__)
+ CSL_MPU_GPIO3_REGS,
+ 63,
+#else
+ CSL_IPU_GPIO3_REGS,
+ 49,
+#endif
+ 0,
+ 57,
+ 0
+ },
+ {
+#ifdef _TMS320C6X
+ CSL_DSP_GPIO4_REGS,
+ OSAL_REGINT_INTVEC_EVENT_COMBINER,
+#elif defined(__ARM_ARCH_7A__)
+ CSL_MPU_GPIO4_REGS,
+ 64,
+#else
+ CSL_IPU_GPIO4_REGS,
+ 49,
+#endif
+ 0,
+ 58,
+ 0
+ },
+ {
+#ifdef _TMS320C6X
+ CSL_DSP_GPIO5_REGS,
+ OSAL_REGINT_INTVEC_EVENT_COMBINER,
+#elif defined(__ARM_ARCH_7A__)
+ CSL_MPU_GPIO5_REGS,
+ 65,
+#else
+ CSL_IPU_GPIO5_REGS,
+ 49,
+#endif
+ 0,
+ 59,
+ 0
+ },
+ {
+#ifdef _TMS320C6X
+ CSL_DSP_GPIO6_REGS,
+ OSAL_REGINT_INTVEC_EVENT_COMBINER,
+#elif defined(__ARM_ARCH_7A__)
+ CSL_MPU_GPIO6_REGS,
+ 66,
+#else
+ CSL_IPU_GPIO6_REGS,
+ 49,
+#endif
+ 0,
+ 60,
+ 0
+ },
+ {
+#ifdef _TMS320C6X
+ CSL_DSP_GPIO7_REGS,
+ OSAL_REGINT_INTVEC_EVENT_COMBINER,
+#elif defined(__ARM_ARCH_7A__)
+ CSL_MPU_GPIO7_REGS,
+ 67,
+#else
+ CSL_IPU_GPIO7_REGS,
+ 49,
+#endif
+ 0,
+ 61,
+ 0
+ },
+ {
+#ifdef _TMS320C6X
+ CSL_DSP_GPIO8_REGS,
+ OSAL_REGINT_INTVEC_EVENT_COMBINER,
+#elif defined(__ARM_ARCH_7A__)
+ CSL_MPU_GPIO8_REGS,
+ 153,
+#else
+ CSL_IPU_GPIO8_REGS,
+ 49,
+#endif
+ 0,
+ 0,
+ 0
+ },
+};
+
+/* GPIO configuration structure */
+CSL_PUBLIC_CONST GPIOConfigList GPIO_config =
+{
+ {
+ &GPIO_FxnTable_v1,
+ NULL,
+ NULL
+ },
+ /* "pad to full predefined length of array" */
+ {
+ NULL,
+ NULL,
+ NULL
+ },
+ {
+ NULL,
+ NULL,
+ NULL
+ }
+};
+
diff --git a/packages/ti/drv/gpio/soc/am572x/GPIO_soc.c b/packages/ti/drv/gpio/soc/am572x/GPIO_soc.c
--- /dev/null
@@ -0,0 +1,195 @@
+/**
+ * \file am572x/GPIO_soc.c
+ *
+ * \brief AM572x SOC specific GPIO hardware attributes.
+ *
+ * This file contains the GPIO hardware attributes like base address and
+ * interrupt ids.
+ */
+
+/*
+ * Copyright (C) 2014-2015 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include <ti/csl/csl_utils.h>
+#include <ti/csl/soc/am572x/src/cslr_soc.h>
+#include <ti/csl/csl_types.h>
+#include <ti/drv/gpio/GPIO.h>
+#include <ti/drv/gpio/soc/GPIO_soc.h>
+
+/* Number of GPIO ports */
+#define CSL_GPIO_PER_CNT 8U
+
+/* GPIO Driver hardware attributes */
+GPIO_v1_hwAttrs_list GPIO_v1_hwAttrs = {
+ {
+#ifdef _TMS320C6X
+ CSL_DSP_GPIO1_REGS,
+ OSAL_REGINT_INTVEC_EVENT_COMBINER,
+#elif defined(__ARM_ARCH_7A__)
+ CSL_MPU_GPIO1_REGS,
+ 61,
+#else
+ CSL_IPU_GPIO1_REGS,
+ 51,
+#endif
+ 0,
+ 55,
+ 0
+ },
+ {
+#ifdef _TMS320C6X
+ CSL_DSP_GPIO2_REGS,
+ OSAL_REGINT_INTVEC_EVENT_COMBINER,
+#elif defined(__ARM_ARCH_7A__)
+ CSL_MPU_GPIO2_REGS,
+ 62,
+#else
+ CSL_IPU_GPIO2_REGS,
+ 52,
+#endif
+ 0,
+ 56,
+ 0
+ },
+ {
+#ifdef _TMS320C6X
+ CSL_DSP_GPIO3_REGS,
+ OSAL_REGINT_INTVEC_EVENT_COMBINER,
+#elif defined(__ARM_ARCH_7A__)
+ CSL_MPU_GPIO3_REGS,
+ 63,
+#else
+ CSL_IPU_GPIO3_REGS,
+ 49,
+#endif
+ 0,
+ 57,
+ 0
+ },
+ {
+#ifdef _TMS320C6X
+ CSL_DSP_GPIO4_REGS,
+ OSAL_REGINT_INTVEC_EVENT_COMBINER,
+#elif defined(__ARM_ARCH_7A__)
+ CSL_MPU_GPIO4_REGS,
+ 64,
+#else
+ CSL_IPU_GPIO4_REGS,
+ 49,
+#endif
+ 0,
+ 58,
+ 0
+ },
+ {
+#ifdef _TMS320C6X
+ CSL_DSP_GPIO5_REGS,
+ OSAL_REGINT_INTVEC_EVENT_COMBINER,
+#elif defined(__ARM_ARCH_7A__)
+ CSL_MPU_GPIO5_REGS,
+ 65,
+#else
+ CSL_IPU_GPIO5_REGS,
+ 49,
+#endif
+ 0,
+ 59,
+ 0
+ },
+ {
+#ifdef _TMS320C6X
+ CSL_DSP_GPIO6_REGS,
+ OSAL_REGINT_INTVEC_EVENT_COMBINER,
+#elif defined(__ARM_ARCH_7A__)
+ CSL_MPU_GPIO6_REGS,
+ 66,
+#else
+ CSL_IPU_GPIO6_REGS,
+ 49,
+#endif
+ 0,
+ 60,
+ 0
+ },
+ {
+#ifdef _TMS320C6X
+ CSL_DSP_GPIO7_REGS,
+ OSAL_REGINT_INTVEC_EVENT_COMBINER,
+#elif defined(__ARM_ARCH_7A__)
+ CSL_MPU_GPIO7_REGS,
+ 67,
+#else
+ CSL_IPU_GPIO7_REGS,
+ 49,
+#endif
+ 0,
+ 61,
+ 0
+ },
+ {
+#ifdef _TMS320C6X
+ CSL_DSP_GPIO8_REGS,
+ OSAL_REGINT_INTVEC_EVENT_COMBINER,
+#elif defined(__ARM_ARCH_7A__)
+ CSL_MPU_GPIO8_REGS,
+ 153,
+#else
+ CSL_IPU_GPIO8_REGS,
+ 49,
+#endif
+ 0,
+ 0,
+ 0
+ },
+};
+
+/* GPIO configuration structure */
+CSL_PUBLIC_CONST GPIOConfigList GPIO_config =
+{
+ {
+ &GPIO_FxnTable_v1,
+ NULL,
+ NULL
+ },
+ /* "pad to full predefined length of array" */
+ {
+ NULL,
+ NULL,
+ NULL
+ },
+ {
+ NULL,
+ NULL,
+ NULL
+ }
+};
diff --git a/packages/ti/drv/gpio/soc/am574x/GPIO_soc.c b/packages/ti/drv/gpio/soc/am574x/GPIO_soc.c
--- /dev/null
@@ -0,0 +1,195 @@
+/**
+ * \file am574x/GPIO_soc.c
+ *
+ * \brief AM574x SOC specific GPIO hardware attributes.
+ *
+ * This file contains the GPIO hardware attributes like base address and
+ * interrupt ids.
+ */
+
+/*
+ * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include <ti/csl/csl_utils.h>
+#include <ti/csl/soc/am574x/src/cslr_soc.h>
+#include <ti/csl/csl_types.h>
+#include <ti/drv/gpio/GPIO.h>
+#include <ti/drv/gpio/soc/GPIO_soc.h>
+
+/* Number of GPIO ports */
+#define CSL_GPIO_PER_CNT 8U
+
+/* GPIO Driver hardware attributes */
+GPIO_v1_hwAttrs_list GPIO_v1_hwAttrs = {
+ {
+#ifdef _TMS320C6X
+ CSL_DSP_GPIO1_REGS,
+ OSAL_REGINT_INTVEC_EVENT_COMBINER,
+#elif defined(__ARM_ARCH_7A__)
+ CSL_MPU_GPIO1_REGS,
+ 61,
+#else
+ CSL_IPU_GPIO1_REGS,
+ 51,
+#endif
+ 0,
+ 55,
+ 0
+ },
+ {
+#ifdef _TMS320C6X
+ CSL_DSP_GPIO2_REGS,
+ OSAL_REGINT_INTVEC_EVENT_COMBINER,
+#elif defined(__ARM_ARCH_7A__)
+ CSL_MPU_GPIO2_REGS,
+ 62,
+#else
+ CSL_IPU_GPIO2_REGS,
+ 52,
+#endif
+ 0,
+ 56,
+ 0
+ },
+ {
+#ifdef _TMS320C6X
+ CSL_DSP_GPIO3_REGS,
+ OSAL_REGINT_INTVEC_EVENT_COMBINER,
+#elif defined(__ARM_ARCH_7A__)
+ CSL_MPU_GPIO3_REGS,
+ 63,
+#else
+ CSL_IPU_GPIO3_REGS,
+ 49,
+#endif
+ 0,
+ 57,
+ 0
+ },
+ {
+#ifdef _TMS320C6X
+ CSL_DSP_GPIO4_REGS,
+ OSAL_REGINT_INTVEC_EVENT_COMBINER,
+#elif defined(__ARM_ARCH_7A__)
+ CSL_MPU_GPIO4_REGS,
+ 64,
+#else
+ CSL_IPU_GPIO4_REGS,
+ 49,
+#endif
+ 0,
+ 58,
+ 0
+ },
+ {
+#ifdef _TMS320C6X
+ CSL_DSP_GPIO5_REGS,
+ OSAL_REGINT_INTVEC_EVENT_COMBINER,
+#elif defined(__ARM_ARCH_7A__)
+ CSL_MPU_GPIO5_REGS,
+ 65,
+#else
+ CSL_IPU_GPIO5_REGS,
+ 49,
+#endif
+ 0,
+ 59,
+ 0
+ },
+ {
+#ifdef _TMS320C6X
+ CSL_DSP_GPIO6_REGS,
+ OSAL_REGINT_INTVEC_EVENT_COMBINER,
+#elif defined(__ARM_ARCH_7A__)
+ CSL_MPU_GPIO6_REGS,
+ 66,
+#else
+ CSL_IPU_GPIO6_REGS,
+ 49,
+#endif
+ 0,
+ 60,
+ 0
+ },
+ {
+#ifdef _TMS320C6X
+ CSL_DSP_GPIO7_REGS,
+ OSAL_REGINT_INTVEC_EVENT_COMBINER,
+#elif defined(__ARM_ARCH_7A__)
+ CSL_MPU_GPIO7_REGS,
+ 67,
+#else
+ CSL_IPU_GPIO7_REGS,
+ 49,
+#endif
+ 0,
+ 61,
+ 0
+ },
+ {
+#ifdef _TMS320C6X
+ CSL_DSP_GPIO8_REGS,
+ OSAL_REGINT_INTVEC_EVENT_COMBINER,
+#elif defined(__ARM_ARCH_7A__)
+ CSL_MPU_GPIO8_REGS,
+ 153,
+#else
+ CSL_IPU_GPIO8_REGS,
+ 49,
+#endif
+ 0,
+ 0,
+ 0
+ },
+};
+
+/* GPIO configuration structure */
+CSL_PUBLIC_CONST GPIOConfigList GPIO_config =
+{
+ {
+ &GPIO_FxnTable_v1,
+ NULL,
+ NULL
+ },
+ /* "pad to full predefined length of array" */
+ {
+ NULL,
+ NULL,
+ NULL
+ },
+ {
+ NULL,
+ NULL,
+ NULL
+ }
+};
diff --git a/packages/ti/drv/gpio/soc/am65xx/GPIO_soc.c b/packages/ti/drv/gpio/soc/am65xx/GPIO_soc.c
--- /dev/null
@@ -0,0 +1,521 @@
+/**
+ * \file am65xx/GPIO_soc.c
+ *
+ * \brief AM65XX SOC specific GPIO hardware attributes.
+ *
+ * This file contains the GPIO hardware attributes like base address and
+ * interrupt ids.
+ */
+
+/*
+ * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include <string.h>
+#include <ti/csl/csl_utils.h>
+#include <ti/csl/soc/am65xx/src/cslr_soc.h>
+#include <ti/csl/csl_types.h>
+#include <ti/csl/hw_types.h>
+#include <ti/csl/soc.h>
+#include <ti/csl/arch/csl_arch.h>
+#include <ti/drv/gpio/soc/GPIO_soc.h>
+#if defined (__aarch64__)
+#include <ti/csl/soc/am65xx/src/cslr_intr_gic0.h>
+#else
+#include <ti/csl/soc/am65xx/src/cslr_intr_mcu0.h>
+#endif
+#include <ti/drv/sciclient/sciclient.h>
+
+
+/** \brief Number of gpio pins for each port */
+#define GPIO_NUM_PINS_PER_PORT (96U)
+
+/** \brief Number of gpio ports present in the soc */
+#define GPIO_NUM_PORTS (2)
+
+/* GPIO Pin interrupt configurations */
+GPIO_IntCfg GPIO_intCfgs[GPIO_NUM_PORTS][GPIO_NUM_PINS_PER_PORT] =
+{
+ {
+ /* GPIO port 0 pin 0 */
+ {
+#if defined (__aarch64__)
+ /* main domain */
+ CSL_GIC0_INTR_MAIN_GPIOMUX_INTROUTER_MAIN_GPIOMUX_INTROUTER_MAIN_0_BUS_OUTP_0, /* main int router output interrupt number */
+ 0, /* GPIO pin interrupt event */
+#else
+ /* mcu domain */
+ CSL_MCU0_INTR_MAIN2MCU_PULSE_INTR0_OUTP_0, /* main 2 mcu int router output interrupt number */
+ 0, /* GPIO pin interrupt event */
+#endif
+ INVALID_INTC_MUX_NUM, /* CIC not used for GPIO pin 0 */
+ 0,
+ 0
+ },
+ /* GPIO port 0 pin 1 */
+ {
+#if defined (__aarch64__)
+ CSL_GIC0_INTR_MAIN_GPIOMUX_INTROUTER_MAIN_GPIOMUX_INTROUTER_MAIN_0_BUS_OUTP_0,
+ 0,
+#else
+ CSL_MCU0_INTR_MAIN2MCU_PULSE_INTR0_OUTP_0,
+ 0,
+#endif
+ INVALID_INTC_MUX_NUM,
+ 0,
+ 0
+ },
+ /* GPIO port 0 pin 2 */
+ {
+#if defined (__aarch64__)
+ CSL_GIC0_INTR_MAIN_GPIOMUX_INTROUTER_MAIN_GPIOMUX_INTROUTER_MAIN_0_BUS_OUTP_0,
+ 0,
+#else
+ CSL_MCU0_INTR_MAIN2MCU_PULSE_INTR0_OUTP_0,
+ 0,
+#endif
+ INVALID_INTC_MUX_NUM,
+ 0,
+ 0
+ },
+ /* GPIO port 0 pin 3 */
+ {
+#if defined (__aarch64__)
+ CSL_GIC0_INTR_MAIN_GPIOMUX_INTROUTER_MAIN_GPIOMUX_INTROUTER_MAIN_0_BUS_OUTP_0,
+ 0,
+#else
+ CSL_MCU0_INTR_MAIN2MCU_PULSE_INTR0_OUTP_0,
+ 0,
+#endif
+ INVALID_INTC_MUX_NUM,
+ 0,
+ 0
+ },
+ /* GPIO port 0 pin 4 */
+ {
+#if defined (__aarch64__)
+ CSL_GIC0_INTR_MAIN_GPIOMUX_INTROUTER_MAIN_GPIOMUX_INTROUTER_MAIN_0_BUS_OUTP_0,
+ 0,
+#else
+ CSL_MCU0_INTR_MAIN2MCU_PULSE_INTR0_OUTP_0,
+ 0,
+#endif
+ INVALID_INTC_MUX_NUM,
+ 0,
+ 0
+ },
+ /* GPIO port 0 pin 5 */
+ {
+#if defined (__aarch64__)
+ CSL_GIC0_INTR_MAIN_GPIOMUX_INTROUTER_MAIN_GPIOMUX_INTROUTER_MAIN_0_BUS_OUTP_0,
+ 0,
+#else
+ CSL_MCU0_INTR_MAIN2MCU_PULSE_INTR0_OUTP_0,
+ 0,
+#endif
+ INVALID_INTC_MUX_NUM,
+ 0,
+ 0
+ },
+ /* GPIO port 0 pin 6 */
+ {
+#if defined (__aarch64__)
+ CSL_GIC0_INTR_MAIN_GPIOMUX_INTROUTER_MAIN_GPIOMUX_INTROUTER_MAIN_0_BUS_OUTP_0,
+ 0,
+#else
+ CSL_MCU0_INTR_MAIN2MCU_PULSE_INTR0_OUTP_0,
+ 0,
+#endif
+ INVALID_INTC_MUX_NUM,
+ 0,
+ 0
+ },
+ /* GPIO port 0 pin 7 */
+ {
+#if defined (__aarch64__)
+ CSL_GIC0_INTR_MAIN_GPIOMUX_INTROUTER_MAIN_GPIOMUX_INTROUTER_MAIN_0_BUS_OUTP_0,
+ 0,
+#else
+ CSL_MCU0_INTR_MAIN2MCU_PULSE_INTR0_OUTP_0,
+ 0,
+#endif
+ INVALID_INTC_MUX_NUM,
+ 0,
+ 0
+ },
+ /* GPIO port 0 pin 8 */
+ {
+#if defined (__aarch64__)
+ CSL_GIC0_INTR_MAIN_GPIOMUX_INTROUTER_MAIN_GPIOMUX_INTROUTER_MAIN_0_BUS_OUTP_0,
+ 0,
+#else
+ CSL_MCU0_INTR_MAIN2MCU_PULSE_INTR0_OUTP_0,
+ 0,
+#endif
+ INVALID_INTC_MUX_NUM,
+ 0,
+ 0
+ },
+ /* GPIO port 0 pin 9 */
+ {
+#if defined (__aarch64__)
+ CSL_GIC0_INTR_MAIN_GPIOMUX_INTROUTER_MAIN_GPIOMUX_INTROUTER_MAIN_0_BUS_OUTP_0,
+ 0,
+#else
+ CSL_MCU0_INTR_MAIN2MCU_PULSE_INTR0_OUTP_0,
+ 0,
+#endif
+ INVALID_INTC_MUX_NUM,
+ 0,
+ 0
+ },
+ /* GPIO port 0 pin 10 */
+ {
+#if defined (__aarch64__)
+ CSL_GIC0_INTR_MAIN_GPIOMUX_INTROUTER_MAIN_GPIOMUX_INTROUTER_MAIN_0_BUS_OUTP_0,
+ 0,
+#else
+ CSL_MCU0_INTR_MAIN2MCU_PULSE_INTR0_OUTP_0,
+ 0,
+#endif
+ INVALID_INTC_MUX_NUM,
+ 0,
+ 0
+ },
+ /* GPIO port 0 pin 11 */
+ {
+#if defined (__aarch64__)
+ CSL_GIC0_INTR_MAIN_GPIOMUX_INTROUTER_MAIN_GPIOMUX_INTROUTER_MAIN_0_BUS_OUTP_0,
+ 0,
+#else
+ CSL_MCU0_INTR_MAIN2MCU_PULSE_INTR0_OUTP_0,
+ 0,
+#endif
+ INVALID_INTC_MUX_NUM,
+ 0,
+ 0
+ },
+ /* GPIO port 0 pin 12 */
+ {
+#if defined (__aarch64__)
+ CSL_GIC0_INTR_MAIN_GPIOMUX_INTROUTER_MAIN_GPIOMUX_INTROUTER_MAIN_0_BUS_OUTP_0,
+ 0,
+#else
+ CSL_MCU0_INTR_MAIN2MCU_PULSE_INTR0_OUTP_0,
+ 0,
+#endif
+ INVALID_INTC_MUX_NUM,
+ 0,
+ 0
+ },
+ /* GPIO port 0 pin 13 */
+ {
+#if defined (__aarch64__)
+ CSL_GIC0_INTR_MAIN_GPIOMUX_INTROUTER_MAIN_GPIOMUX_INTROUTER_MAIN_0_BUS_OUTP_0,
+ 0,
+#else
+ CSL_MCU0_INTR_MAIN2MCU_PULSE_INTR0_OUTP_0,
+ 0,
+#endif
+ INVALID_INTC_MUX_NUM,
+ 0,
+ 0
+ },
+ /* GPIO port 0 pin 14 */
+ {
+#if defined (__aarch64__)
+ CSL_GIC0_INTR_MAIN_GPIOMUX_INTROUTER_MAIN_GPIOMUX_INTROUTER_MAIN_0_BUS_OUTP_0,
+ 0,
+#else
+ CSL_MCU0_INTR_MAIN2MCU_PULSE_INTR0_OUTP_0,
+ 0,
+#endif
+ INVALID_INTC_MUX_NUM,
+ 0,
+ 0
+ },
+ /* GPIO port 0 pin 15 */
+ {
+#if defined (__aarch64__)
+ CSL_GIC0_INTR_MAIN_GPIOMUX_INTROUTER_MAIN_GPIOMUX_INTROUTER_MAIN_0_BUS_OUTP_0,
+ 0,
+#else
+ CSL_MCU0_INTR_MAIN2MCU_PULSE_INTR0_OUTP_0,
+ 0,
+#endif
+ INVALID_INTC_MUX_NUM,
+ 0,
+ 0
+ },
+ },
+};
+
+/* GPIO Driver hardware attributes */
+GPIO_v0_hwAttrsList GPIO_v0_hwAttrs =
+{
+ {
+ CSL_GPIO0_BASE,
+ &GPIO_intCfgs[0][0],
+ &GPIO_socConfigIntrPath,
+ },
+
+ {
+ CSL_GPIO1_BASE,
+ &GPIO_intCfgs[1][0],
+ &GPIO_socConfigIntrPath,
+ }
+};
+
+/* GPIO configuration structure */
+CSL_PUBLIC_CONST GPIOConfigList GPIO_config =
+{
+ {
+ &GPIO_FxnTable_v0,
+ NULL,
+ &GPIO_v0_hwAttrs[0]
+ },
+
+ {
+ &GPIO_FxnTable_v0,
+ NULL,
+ &GPIO_v0_hwAttrs[1]
+ },
+
+ {
+ NULL,
+ NULL,
+ NULL
+ }
+};
+
+/**
+ * \brief This API gets the SoC level of GPIO intial configuration
+ *
+ * \param index GPIO instance index.
+ * \param cfg Pointer to GPIO SOC initial config.
+ *
+ * \return 0 success: -1: error
+ *
+ */
+int32_t GPIO_socGetInitCfg(uint32_t index, GPIO_v0_HwAttrs *cfg)
+{
+ int32_t ret = 0;
+
+ if (index < GPIO_NUM_PORTS)
+ {
+ *cfg = GPIO_v0_hwAttrs[index];
+ }
+ else
+ {
+ ret = -1;
+ }
+
+ return ret;
+}
+
+/**
+ * \brief This API sets the SoC level of GPIO intial configuration
+ *
+ * \param index GPIO instance index.
+ * \param cfg Pointer to GPIO SOC initial config.
+ *
+ * \return 0 success: -1: error
+ *
+ */
+int32_t GPIO_socSetInitCfg(uint32_t index, const GPIO_v0_HwAttrs *cfg)
+{
+ int32_t ret = 0;
+
+ if (index < GPIO_NUM_PORTS)
+ {
+ GPIO_v0_hwAttrs[index] = *cfg;
+ }
+ else
+ {
+ ret = -1;
+ }
+
+ return ret;
+}
+
+/**
+ * \brief This API gets the number of GPIO pins per port
+ * and GPIO number of ports
+ *
+ * \param numPins pointer to numPins variable.
+ * \param numPorts pointer to numPorts variable.
+ *
+ * \return none
+ *
+ */
+void GPIO_socGetNumPinsPorts(uint32_t *numPins, uint32_t *numPorts)
+{
+ *numPins = GPIO_NUM_PINS_PER_PORT;
+ *numPorts = GPIO_NUM_PORTS;
+}
+
+void MuxIntcP_clearInEvent(int32_t muxNum, int32_t muxInEvent)
+{
+ return;
+}
+
+
+MuxIntcP_Status MuxIntcP_create(MuxIntcP_inParams *inParams, MuxIntcP_outParams *outParams)
+{
+ return (MuxIntcP_OK);
+}
+
+/* A count kept for each bank usage/ 16 pins share a bank */
+#define GPIO_NUM_BANKS ((GPIO_NUM_PINS_PER_PORT+15)/16)
+int32_t GPIO_PinBankUsageCount[GPIO_NUM_PORTS][GPIO_NUM_BANKS] ={0};
+
+/**
+ * \brief This function sets/clears the soc interrupt path including the \n
+ * interrupt routers (GPIO_RTR,MAIN2MCU_RTR) etc and GPIO number of ports
+ *
+ * \param portNum The GPIO port number to configure the interrupt path.
+ * \param pinNum The GPIO pin number to configure the interrupt path.
+ * \param hwAttrs The GPIO_v0_HwAttrs for this SOC
+ * \param setIntrPath TRUE - set the interrupt path, FALSE - clear the interrupt path
+ * \return CSL_PASS if successful, CSL_FAIL if failed
+ *
+ */
+int32_t GPIO_socConfigIntrPath(uint32_t portNum, uint32_t pinNum,void *hwAttrs,bool setIntrPath)
+{
+
+ GPIO_v0_HwAttrs *cfg = (GPIO_v0_HwAttrs *)hwAttrs;
+ GPIO_IntCfg *intCfg;
+ uint32_t bankNum;
+ int32_t retVal=CSL_PASS;
+#if defined(BUILD_MCU1_0) || defined(BUILD_MCU1_1)
+ CSL_ArmR5CPUInfo r5CpuInfo;
+#endif
+ struct tisci_msg_rm_irq_set_req rmIrqReq;
+ struct tisci_msg_rm_irq_set_resp rmIrqResp;
+ struct tisci_msg_rm_irq_release_req rmIrqRelease;
+ int32_t src_id,src_index,dst_id,dst_host_irq;
+
+ intCfg = cfg->intCfg;
+ cfg->baseAddr = CSL_WKUP_GPIO0_BASE; /* For AM65x GP EVM */
+
+#if defined(BUILD_MCU1_0) || defined(BUILD_MCU1_1)
+ CSL_armR5GetCpuID(&r5CpuInfo);
+#endif
+ /* Input parameter validation */
+ bankNum = pinNum/16; /* Each GPIO bank has 16 pins */
+
+ /* We route bank interrupts to the cpu interrupts */
+ if(cfg->baseAddr == CSL_WKUP_GPIO0_BASE) {
+ src_id = TISCI_DEV_WKUP_GPIO0;
+ src_index = 128 + bankNum; /* This is the bus_gpio_bank (128-131) mentioned in DMSC firmware guide for AM6_DEV_WKUP_GPIO0 */
+ } else if(cfg->baseAddr == CSL_GPIO0_BASE) {
+ src_id = TISCI_DEV_GPIO0;
+ src_index = 256 + bankNum; /* This is the bus_gpio_bank (256-261) mentioned in DMSC firmware guide for AM6_DEV_GPIO0 */
+ } else {
+ src_id = TISCI_DEV_GPIO1;
+ src_index = 256 + bankNum; /* This is the bus_gpio_bank (256-261) mentioned in DMSC firmware guide for AM6_DEV_GPIO1 */
+ }
+
+ /* GPIO uses bank interrupts. So choose the bank interrupts from bus_gpio_bank with valid values from
+ * the DMSC firmware user guide */
+#if defined(BUILD_MCU1_0) || defined(BUILD_MCU1_1)
+ if(r5CpuInfo.cpuID == 0) {
+ dst_id = TISCI_DEV_MCU_ARMSS0_CPU0;
+ } else {
+ dst_id = TISCI_DEV_MCU_ARMSS0_CPU1;
+ }
+#elif defined(BUILD_MPU1_0) || defined(BUILD_MPU1_1)
+ dst_id = TISCI_DEV_GIC0;
+#endif
+
+ dst_host_irq = intCfg[pinNum].intNum;
+
+ if(setIntrPath) {
+ memset (&rmIrqReq,0,sizeof(rmIrqReq));
+
+ rmIrqReq.secondary_host = TISCI_MSG_VALUE_RM_UNUSED_SECONDARY_HOST;
+ rmIrqReq.src_id = src_id;
+ rmIrqReq.src_index = src_index; /* This is the event coming out of
+ the peripheral */
+
+ /* Set the destination interrupt */
+ rmIrqReq.valid_params |= TISCI_MSG_VALUE_RM_DST_ID_VALID;
+ rmIrqReq.valid_params |= TISCI_MSG_VALUE_RM_DST_HOST_IRQ_VALID;
+
+ /* Set the destination based on the core */
+ rmIrqReq.dst_id = dst_id;
+ rmIrqReq.dst_host_irq = dst_host_irq;
+ } else {
+ memset (&rmIrqRelease,0,sizeof(rmIrqRelease));
+
+ rmIrqRelease.secondary_host = TISCI_MSG_VALUE_RM_UNUSED_SECONDARY_HOST;
+ rmIrqRelease.src_id = src_id;
+ rmIrqRelease.src_index = src_index; /* This is the event coming out of the peripheral */
+
+ /* Set the destination interrupt */
+ rmIrqRelease.valid_params |= TISCI_MSG_VALUE_RM_DST_ID_VALID;
+ rmIrqRelease.valid_params |= TISCI_MSG_VALUE_RM_DST_HOST_IRQ_VALID;
+
+ /* Set the destination based on the core */
+ rmIrqRelease.dst_id = dst_id;
+ rmIrqRelease.dst_host_irq = dst_host_irq;
+ }
+
+ /* Config event */
+ if(setIntrPath) {
+ if(GPIO_PinBankUsageCount[portNum][bankNum]==0) {
+ retVal = Sciclient_rmIrqSet(
+ (const struct tisci_msg_rm_irq_set_req *)&rmIrqReq,
+ &rmIrqResp,
+ SCICLIENT_SERVICE_WAIT_FOREVER);
+
+ if(retVal==CSL_PASS) {
+ /* Increase the bank usage count for this port */
+ GPIO_PinBankUsageCount[portNum][bankNum]++;
+ }
+ } else {
+ /* The interrupt path is already allocated, no need to re-allocate it */
+ retVal = CSL_PASS;
+ }
+ } else {
+ retVal = Sciclient_rmIrqRelease(
+ (const struct tisci_msg_rm_irq_release_req *)&rmIrqRelease,
+ SCICLIENT_SERVICE_WAIT_FOREVER);
+
+ if(retVal==CSL_PASS) {
+ /* Increase the bank usage count for this port */
+ GPIO_PinBankUsageCount[portNum][bankNum]--;
+ }
+ }
+
+ return(retVal);
+}
diff --git a/packages/ti/drv/gpio/soc/c6657/GPIO_soc.c b/packages/ti/drv/gpio/soc/c6657/GPIO_soc.c
--- /dev/null
@@ -0,0 +1,387 @@
+/**
+ * \file c6657/GPIO_soc.c
+ *
+ * \brief C6657 SOC specific GPIO hardware attributes.
+ *
+ * This file contains the GPIO hardware attributes like base address and
+ * interrupt ids.
+ */
+
+/*
+ * Copyright (C) 2015 - 2016 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+#include <ti/csl/csl_utils.h>
+#include <ti/csl/soc.h>
+#include <ti/csl/csl_types.h>
+#include <ti/csl/csl_chipAux.h>
+#include <ti/drv/gpio/GPIO.h>
+#include <ti/drv/gpio/soc/GPIO_soc.h>
+
+/** \brief Number of gpio pins for each port */
+#define GPIO_NUM_PINS_PER_PORT (32U)
+
+/** \brief Number of gpio ports present in the soc */
+#define GPIO_NUM_PORTS (CSL_GPIO_PER_CNT)
+
+/* GPIO Pin interrupt configurations */
+GPIO_IntCfg GPIO_intCfgs[GPIO_NUM_PINS_PER_PORT] =
+{
+ /* GPIO port 0 pin 0 */
+ {
+ 10, /* default DSP Interrupt vector number, can be set in GPIO_socSetInitCfg() API */
+ CSL_GEM_GPINTN, /* DSP corePac GPIO pin 0 interrupt event for Core 0 */
+ INVALID_INTC_MUX_NUM, /* CIC not used for GPIO pin 0 */
+ },
+ /* GPIO port 0 pin 1 */
+ {
+ 10,
+ CSL_GEM_GPINTN, /* DSP corePac GPIO pin 1 interrupt event for Core 1 */
+ INVALID_INTC_MUX_NUM,
+ },
+ /* GPIO port 0 pin 2 */
+ {
+ 10,
+ CSL_GEM_GPINT2, /* DSP corePac GPIO pin 2 interrupt event*/
+ INVALID_INTC_MUX_NUM,
+ },
+ /* GPIO port 0 pin 3 */
+ {
+ 10,
+ CSL_GEM_GPINT3, /* DSP corePac GPIO pin 3 interrupt event*/
+ INVALID_INTC_MUX_NUM,
+ },
+ /* GPIO port 0 pin 4 */
+ {
+ 10,
+ CSL_GEM_GPINT4, /* DSP corePac GPIO pin 4 interrupt event*/
+ INVALID_INTC_MUX_NUM,
+ },
+ /* GPIO port 0 pin 5 */
+ {
+ 10,
+ CSL_GEM_GPINT5, /* DSP corePac GPIO pin 5 interrupt event*/
+ INVALID_INTC_MUX_NUM,
+ },
+ /* GPIO port 0 pin 6 */
+ {
+ 10,
+ CSL_GEM_GPINT6, /* DSP corePac GPIO pin 6 interrupt event*/
+ INVALID_INTC_MUX_NUM,
+ },
+ /* GPIO port 0 pin 7 */
+ {
+ 10,
+ CSL_GEM_GPINT7, /* DSP corePac GPIO pin 7 interrupt event*/
+ INVALID_INTC_MUX_NUM,
+ },
+ /* GPIO port 0 pin 8 */
+ {
+ 10,
+ CSL_GEM_GPINT8, /* DSP corePac GPIO pin 8 interrupt event*/
+ INVALID_INTC_MUX_NUM,
+ },
+ /* GPIO port 0 pin 9 */
+ {
+ 10,
+ CSL_GEM_GPINT9, /* DSP corePac GPIO pin 9 interrupt event*/
+ INVALID_INTC_MUX_NUM,
+ },
+ /* GPIO port 0 pin 10 */
+ {
+ 10,
+ CSL_GEM_GPINT10, /* DSP corePac GPIO pin 10 interrupt event*/
+ INVALID_INTC_MUX_NUM,
+ },
+ /* GPIO port 0 pin 11 */
+ {
+ 10,
+ CSL_GEM_GPINT11, /* DSP corePac GPIO pin 11 interrupt event*/
+ INVALID_INTC_MUX_NUM,
+ },
+ /* GPIO port 0 pin 12 */
+ {
+ 10,
+ CSL_GEM_GPINT12, /* DSP corePac GPIO pin 12 interrupt event*/
+ INVALID_INTC_MUX_NUM,
+ },
+ /* GPIO port 0 pin 13 */
+ {
+ 10,
+ CSL_GEM_GPINT13, /* DSP corePac GPIO pin 13 interrupt event*/
+ INVALID_INTC_MUX_NUM,
+ },
+ /* GPIO port 0 pin 14 */
+ {
+ 10,
+ CSL_GEM_GPINT14, /* DSP corePac GPIO pin 14 interrupt event*/
+ INVALID_INTC_MUX_NUM,
+ },
+ /* GPIO port 0 pin 15 */
+ {
+ 10,
+ CSL_GEM_GPINT15, /* DSP corePac GPIO pin 15 interrupt event*/
+ INVALID_INTC_MUX_NUM,
+ },
+ /* GPIO port 0 pin 16 */
+ {
+ 10,
+ 25, /* default DSP INTC GPIO Event ID, can be set in GPIO_socSetInitCfg() API */
+ 0, /* CIC number 0 */
+ CSL_INTC0_GPINT16, /* CIC GPIO Event ID */
+ 3 /* default CIC Host Interrupt, map to CIC0_OUT(3+20*n) event */
+ },
+ /* GPIO port 0 pin 17 */
+ {
+ 10,
+ 25,
+ 0,
+ CSL_INTC0_GPINT17,
+ 3
+ },
+ /* GPIO port 0 pin 18 */
+ {
+ 10,
+ 25,
+ 0,
+ CSL_INTC0_GPINT18,
+ 3
+ },
+ /* GPIO port 0 pin 19 */
+ {
+ 10,
+ 25,
+ 0,
+ CSL_INTC0_GPINT19,
+ 3
+ },
+ /* GPIO port 0 pin 20 */
+ {
+ 10,
+ 25,
+ 0,
+ CSL_INTC0_GPINT20,
+ 3
+ },
+ /* GPIO port 0 pin 21 */
+ {
+ 10,
+ 25,
+ 0,
+ CSL_INTC0_GPINT21,
+ 3
+ },
+ /* GPIO port 0 pin 22 */
+ {
+ 10,
+ 25,
+ 0,
+ CSL_INTC0_GPINT22,
+ 3
+ },
+ /* GPIO port 0 pin 23 */
+ {
+ 10,
+ 25,
+ 0,
+ CSL_INTC0_GPINT23,
+ 3
+ },
+ /* GPIO port 0 pin 24 */
+ {
+ 10,
+ 25,
+ 0,
+ CSL_INTC0_GPINT24,
+ 3
+ },
+ /* GPIO port 0 pin 25 */
+ {
+ 10,
+ 25,
+ 0,
+ CSL_INTC0_GPINT25,
+ 3
+ },
+ /* GPIO port 0 pin 26 */
+ {
+ 10,
+ 25,
+ 0,
+ CSL_INTC0_GPINT26,
+ 3
+ },
+ /* GPIO port 0 pin 27 */
+ {
+ 10,
+ 25,
+ 0,
+ CSL_INTC0_GPINT27,
+ 3
+ },
+ /* GPIO port 0 pin 28 */
+ {
+ 10,
+ 25,
+ 0,
+ CSL_INTC0_GPINT28,
+ 3
+ },
+ /* GPIO port 0 pin 29 */
+ {
+ 10,
+ 25,
+ 0,
+ CSL_INTC0_GPINT29,
+ 3
+ },
+ /* GPIO port 0 pin 30 */
+ {
+ 10,
+ 25,
+ 0,
+ CSL_INTC0_GPINT30,
+ 3
+ },
+ /* GPIO port 0 pin 31 */
+ {
+ 10,
+ 25,
+ 0,
+ CSL_INTC0_GPINT31,
+ 3
+ }
+};
+
+/* GPIO Driver hardware attributes */
+GPIO_v0_hwAttrsList GPIO_v0_hwAttrs =
+{
+ {
+ CSL_GPIO_REGS,
+ &GPIO_intCfgs[0],
+ NULL
+ },
+
+ {
+ 0,
+ NULL,
+ NULL
+ }
+};
+
+/* GPIO configuration structure */
+CSL_PUBLIC_CONST GPIOConfigList GPIO_config =
+{
+ {
+ &GPIO_FxnTable_v0,
+ NULL,
+ &GPIO_v0_hwAttrs[0]
+ },
+
+ {
+ NULL,
+ NULL,
+ NULL
+ },
+ /* "pad to full predefined length of array" */
+ {
+ NULL,
+ NULL,
+ NULL
+ }
+};
+
+/**
+ * \brief This API gets the SoC level of GPIO intial configuration
+ *
+ * \param index GPIO instance index.
+ * \param cfg Pointer to GPIO SOC initial config.
+ *
+ * \return 0 success: -1: error
+ *
+ */
+int32_t GPIO_socGetInitCfg(uint32_t index, GPIO_v0_HwAttrs *cfg)
+{
+ int32_t ret = 0;
+
+ if (index < GPIO_NUM_PORTS)
+ {
+ *cfg = GPIO_v0_hwAttrs[index];
+ }
+ else
+ {
+ ret = -1;
+ }
+
+ return ret;
+}
+
+/**
+ * \brief This API sets the SoC level of GPIO intial configuration
+ *
+ * \param index GPIO instance index.
+ * \param cfg Pointer to GPIO SOC initial config.
+ *
+ * \return 0 success: -1: error
+ *
+ */
+int32_t GPIO_socSetInitCfg(uint32_t index, const GPIO_v0_HwAttrs *cfg)
+{
+ int32_t ret = 0;
+
+ if (index < GPIO_NUM_PORTS)
+ {
+ GPIO_v0_hwAttrs[index] = *cfg;
+ }
+ else
+ {
+ ret = -1;
+ }
+
+ return ret;
+}
+
+/**
+ * \brief This API gets the number of GPIO pins per port
+ * and GPIO number of ports
+ *
+ * \param numPins pointer to numPins variable.
+ * \param numPorts pointer to numPorts variable.
+ *
+ * \return none
+ *
+ */
+void GPIO_socGetNumPinsPorts(uint32_t *numPins, uint32_t *numPorts)
+{
+ *numPins = GPIO_NUM_PINS_PER_PORT;
+ *numPorts = GPIO_NUM_PORTS;
+}
+
diff --git a/packages/ti/drv/gpio/soc/c6678/GPIO_soc.c b/packages/ti/drv/gpio/soc/c6678/GPIO_soc.c
--- /dev/null
@@ -0,0 +1,276 @@
+/**
+ * \file c6678/GPIO_soc.c
+ *
+ * \brief C6678 SOC specific GPIO hardware attributes.
+ *
+ * This file contains the GPIO hardware attributes like base address and
+ * interrupt ids.
+ */
+
+/*
+ * Copyright (C) 2015 - 2016 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+#include <ti/csl/csl_utils.h>
+#include <ti/csl/soc.h>
+#include <ti/csl/csl_types.h>
+#include <ti/csl/csl_chipAux.h>
+#include <ti/drv/gpio/GPIO.h>
+#include <ti/drv/gpio/soc/GPIO_soc.h>
+
+/** \brief Number of gpio pins for each port */
+#define GPIO_NUM_PINS_PER_PORT (32U)
+
+/** \brief Number of gpio ports present in the soc */
+#define GPIO_NUM_PORTS (CSL_GPIO_PER_CNT)
+
+/* GPIO Pin interrupt configurations */
+GPIO_IntCfg GPIO_intCfgs[GPIO_NUM_PINS_PER_PORT] =
+{
+ /* GPIO port 0 pin 0 */
+ {
+ 10, /* default DSP Interrupt vector number, can be set in GPIO_socSetInitCfg() API */
+ CSL_GEM_GPINTN, /* DSP corePac GPIO pin 0 interrupt event for Core 0 */
+ INVALID_INTC_MUX_NUM, /* CIC not used for GPIO pin 0 */
+ },
+ /* GPIO port 0 pin 1 */
+ {
+ 10,
+ CSL_GEM_GPINTN, /* DSP corePac GPIO pin 1 interrupt event for Core 1 */
+ INVALID_INTC_MUX_NUM,
+ },
+ /* GPIO port 0 pin 2 */
+ {
+ 10,
+ CSL_GEM_GPINTN, /* DSP corePac GPIO pin 2 interrupt event for Core 2 */
+ INVALID_INTC_MUX_NUM,
+ },
+ /* GPIO port 0 pin 3 */
+ {
+ 10,
+ CSL_GEM_GPINTN, /* DSP corePac GPIO pin 3 interrupt event for Core 3 */
+ INVALID_INTC_MUX_NUM,
+ },
+ /* GPIO port 0 pin 4 */
+ {
+ 10,
+ CSL_GEM_GPINTN, /* DSP corePac GPIO pin 4 interrupt event for Core 4 */
+ INVALID_INTC_MUX_NUM,
+ },
+ /* GPIO port 0 pin 5 */
+ {
+ 10,
+ CSL_GEM_GPINTN, /* DSP corePac GPIO pin 5 interrupt event for Core 5 */
+ INVALID_INTC_MUX_NUM,
+ },
+ /* GPIO port 0 pin 6 */
+ {
+ 10,
+ CSL_GEM_GPINTN, /* DSP corePac GPIO pin 6 interrupt event for Core 6 */
+ INVALID_INTC_MUX_NUM,
+ },
+ /* GPIO port 0 pin 7 */
+ {
+ 10,
+ CSL_GEM_GPINTN, /* DSP corePac GPIO pin 7 interrupt event for Core 7 */
+ INVALID_INTC_MUX_NUM,
+ },
+ /* GPIO port 0 pin 8 */
+ {
+ 10,
+ CSL_GEM_GPINT8, /* DSP corePac GPIO pin 8 interrupt event */
+ INVALID_INTC_MUX_NUM,
+ },
+ /* GPIO port 0 pin 9 */
+ {
+ 10,
+ CSL_GEM_GPINT9, /* DSP corePac GPIO pin 9 interrupt event*/
+ INVALID_INTC_MUX_NUM,
+ },
+ /* GPIO port 0 pin 10 */
+ {
+ 10,
+ CSL_GEM_GPINT10, /* DSP corePac GPIO pin 10 interrupt event*/
+ INVALID_INTC_MUX_NUM,
+ },
+ /* GPIO port 0 pin 11 */
+ {
+ 10,
+ CSL_GEM_GPINT11, /* DSP corePac GPIO pin 11 interrupt event*/
+ INVALID_INTC_MUX_NUM,
+ },
+ /* GPIO port 0 pin 12 */
+ {
+ 10,
+ CSL_GEM_GPINT12, /* DSP corePac GPIO pin 12 interrupt event*/
+ INVALID_INTC_MUX_NUM,
+ },
+ /* GPIO port 0 pin 13 */
+ {
+ 10,
+ CSL_GEM_GPINT13, /* DSP corePac GPIO pin 13 interrupt event*/
+ INVALID_INTC_MUX_NUM,
+ },
+ /* GPIO port 0 pin 14 */
+ {
+ 10,
+ CSL_GEM_GPINT14, /* DSP corePac GPIO pin 14 interrupt event*/
+ INVALID_INTC_MUX_NUM,
+ },
+ /* GPIO port 0 pin 15 */
+ {
+ 10,
+ CSL_GEM_GPINT15, /* DSP corePac GPIO pin 15 interrupt event*/
+ INVALID_INTC_MUX_NUM,
+ },
+ /* GPIO port 0 pin 16-31 */
+ {0,0,0},
+ {0,0,0},
+ {0,0,0},
+ {0,0,0},
+ {0,0,0},
+ {0,0,0},
+ {0,0,0},
+ {0,0,0},
+ {0,0,0},
+ {0,0,0},
+ {0,0,0},
+ {0,0,0},
+ {0,0,0},
+ {0,0,0},
+ {0,0,0},
+ {0,0,0}
+};
+
+/* GPIO Driver hardware attributes */
+GPIO_v0_hwAttrsList GPIO_v0_hwAttrs =
+{
+ {
+ CSL_GPIO_REGS,
+ &GPIO_intCfgs[0],
+ NULL
+ },
+
+ {
+ 0,
+ NULL,
+ NULL
+ }
+};
+
+/* GPIO configuration structure */
+CSL_PUBLIC_CONST GPIOConfigList GPIO_config =
+{
+ {
+ &GPIO_FxnTable_v0,
+ NULL,
+ &GPIO_v0_hwAttrs[0]
+ },
+
+ {
+ NULL,
+ NULL,
+ NULL
+ },
+ /* "pad to full predefined length of array" */
+ {
+ NULL,
+ NULL,
+ NULL
+ }
+};
+
+/**
+ * \brief This API gets the SoC level of GPIO intial configuration
+ *
+ * \param index GPIO instance index.
+ * \param cfg Pointer to GPIO SOC initial config.
+ *
+ * \return 0 success: -1: error
+ *
+ */
+int32_t GPIO_socGetInitCfg(uint32_t index, GPIO_v0_HwAttrs *cfg)
+{
+ int32_t ret = 0;
+
+ if (index < GPIO_NUM_PORTS)
+ {
+ *cfg = GPIO_v0_hwAttrs[index];
+ }
+ else
+ {
+ ret = -1;
+ }
+
+ return ret;
+}
+
+/**
+ * \brief This API sets the SoC level of GPIO intial configuration
+ *
+ * \param index GPIO instance index.
+ * \param cfg Pointer to GPIO SOC initial config.
+ *
+ * \return 0 success: -1: error
+ *
+ */
+int32_t GPIO_socSetInitCfg(uint32_t index, const GPIO_v0_HwAttrs *cfg)
+{
+ int32_t ret = 0;
+
+ if (index < GPIO_NUM_PORTS)
+ {
+ GPIO_v0_hwAttrs[index] = *cfg;
+ }
+ else
+ {
+ ret = -1;
+ }
+
+ return ret;
+}
+
+/**
+ * \brief This API gets the number of GPIO pins per port
+ * and GPIO number of ports
+ *
+ * \param numPins pointer to numPins variable.
+ * \param numPorts pointer to numPorts variable.
+ *
+ * \return none
+ *
+ */
+void GPIO_socGetNumPinsPorts(uint32_t *numPins, uint32_t *numPorts)
+{
+ *numPins = GPIO_NUM_PINS_PER_PORT;
+ *numPorts = GPIO_NUM_PORTS;
+}
+
diff --git a/packages/ti/drv/gpio/soc/dra72x/GPIO_soc.c b/packages/ti/drv/gpio/soc/dra72x/GPIO_soc.c
--- /dev/null
@@ -0,0 +1,178 @@
+/**
+ * \file dra72x/GPIO_soc.c
+ *
+ * \brief DRA72x SOC specific GPIO hardware attributes.
+ *
+ * This file contains the GPIO hardware attributes like base address and
+ * interrupt ids.
+ */
+
+/*
+ * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+#include <ti/csl/csl_utils.h>
+#include <ti/csl/soc.h>
+#include <ti/csl/csl_types.h>
+#include <ti/drv/gpio/GPIO.h>
+#include <ti/drv/gpio/soc/GPIO_soc.h>
+
+/* Number of GPIO ports */
+#define CSL_GPIO_PER_CNT 8U
+
+/* GPIO Driver hardware attributes */
+GPIO_v1_hwAttrs_list GPIO_v1_hwAttrs = {
+ {
+ SOC_GPIO1_BASE,
+#ifdef _TMS320C6X
+ OSAL_REGINT_INTVEC_EVENT_COMBINER,
+#elif defined(__ARM_ARCH_7A__)
+ 61,
+#else
+ 51,
+#endif
+ 0,
+ 55,
+ 0
+ },
+ {
+ SOC_GPIO2_BASE,
+#ifdef _TMS320C6X
+ OSAL_REGINT_INTVEC_EVENT_COMBINER,
+#elif defined(__ARM_ARCH_7A__)
+ 62,
+#else
+ 52,
+#endif
+ 0,
+ 56,
+ 0
+ },
+ {
+ SOC_GPIO3_BASE,
+#ifdef _TMS320C6X
+ OSAL_REGINT_INTVEC_EVENT_COMBINER,
+#elif defined(__ARM_ARCH_7A__)
+ 63,
+#else
+ 49,
+#endif
+ 0,
+ 57,
+ 0
+ },
+ {
+ SOC_GPIO4_BASE,
+#ifdef _TMS320C6X
+ OSAL_REGINT_INTVEC_EVENT_COMBINER,
+#elif defined(__ARM_ARCH_7A__)
+ 64,
+#else
+ 49,
+#endif
+ 0,
+ 58,
+ 0
+ },
+ {
+ SOC_GPIO5_BASE,
+#ifdef _TMS320C6X
+ OSAL_REGINT_INTVEC_EVENT_COMBINER,
+#elif defined(__ARM_ARCH_7A__)
+ 65,
+#else
+ 49,
+#endif
+ 0,
+ 59,
+ 0
+ },
+ {
+ SOC_GPIO6_BASE,
+#ifdef _TMS320C6X
+ OSAL_REGINT_INTVEC_EVENT_COMBINER,
+#elif defined(__ARM_ARCH_7A__)
+ 66,
+#else
+ 49,
+#endif
+ 0,
+ 60,
+ 0
+ },
+ {
+ SOC_GPIO7_BASE,
+#ifdef _TMS320C6X
+ OSAL_REGINT_INTVEC_EVENT_COMBINER,
+#elif defined(__ARM_ARCH_7A__)
+ 67,
+#else
+ 49,
+#endif
+ 0,
+ 61,
+ 0
+ },
+ {
+ SOC_GPIO8_BASE,
+#ifdef _TMS320C6X
+ OSAL_REGINT_INTVEC_EVENT_COMBINER,
+#elif defined(__ARM_ARCH_7A__)
+ 153,
+#else
+ 49,
+#endif
+ 0,
+ 0,
+ 0
+ },
+};
+
+/* GPIO configuration structure */
+CSL_PUBLIC_CONST GPIOConfigList GPIO_config =
+{
+ {
+ &GPIO_FxnTable_v1,
+ NULL,
+ NULL
+ },
+ /* "pad to full predefined length of array" */
+ {
+ NULL,
+ NULL,
+ NULL
+ },
+ {
+ NULL,
+ NULL,
+ NULL
+ }
+};
diff --git a/packages/ti/drv/gpio/soc/dra75x/GPIO_soc.c b/packages/ti/drv/gpio/soc/dra75x/GPIO_soc.c
--- /dev/null
@@ -0,0 +1,194 @@
+/**
+ * \file dra75x/GPIO_soc.c
+ *
+ * \brief DRA75x SOC specific GPIO hardware attributes.
+ *
+ * This file contains the GPIO hardware attributes like base address and
+ * interrupt ids.
+ */
+
+/*
+ * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+#include <ti/csl/csl_utils.h>
+#include <ti/csl/soc.h>
+#include <ti/csl/csl_types.h>
+#include <ti/drv/gpio/GPIO.h>
+#include <ti/drv/gpio/soc/GPIO_soc.h>
+
+/* Number of GPIO ports */
+#define CSL_GPIO_PER_CNT 8U
+
+/* GPIO Driver hardware attributes */
+GPIO_v1_hwAttrs_list GPIO_v1_hwAttrs = {
+ {
+#ifdef _TMS320C6X
+ SOC_GPIO1_BASE,
+ OSAL_REGINT_INTVEC_EVENT_COMBINER,
+#elif defined(__ARM_ARCH_7A__)
+ SOC_GPIO1_BASE,
+ 61,
+#else
+ SOC_GPIO1_BASE,
+ 51,
+#endif
+ 0,
+ 55,
+ 0
+ },
+ {
+#ifdef _TMS320C6X
+ SOC_GPIO2_BASE,
+ OSAL_REGINT_INTVEC_EVENT_COMBINER,
+#elif defined(__ARM_ARCH_7A__)
+ SOC_GPIO2_BASE,
+ 62,
+#else
+ SOC_GPIO2_BASE,
+ 52,
+#endif
+ 0,
+ 56,
+ 0
+ },
+ {
+#ifdef _TMS320C6X
+ SOC_GPIO3_BASE,
+ OSAL_REGINT_INTVEC_EVENT_COMBINER,
+#elif defined(__ARM_ARCH_7A__)
+ SOC_GPIO3_BASE,
+ 63,
+#else
+ SOC_GPIO3_BASE,
+ 49,
+#endif
+ 0,
+ 57,
+ 0
+ },
+ {
+#ifdef _TMS320C6X
+ SOC_GPIO4_BASE,
+ OSAL_REGINT_INTVEC_EVENT_COMBINER,
+#elif defined(__ARM_ARCH_7A__)
+ SOC_GPIO4_BASE,
+ 64,
+#else
+ SOC_GPIO4_BASE,
+ 49,
+#endif
+ 0,
+ 58,
+ 0
+ },
+ {
+#ifdef _TMS320C6X
+ SOC_GPIO5_BASE,
+ OSAL_REGINT_INTVEC_EVENT_COMBINER,
+#elif defined(__ARM_ARCH_7A__)
+ SOC_GPIO5_BASE,
+ 65,
+#else
+ SOC_GPIO5_BASE,
+ 49,
+#endif
+ 0,
+ 59,
+ 0
+ },
+ {
+#ifdef _TMS320C6X
+ SOC_GPIO6_BASE,
+ OSAL_REGINT_INTVEC_EVENT_COMBINER,
+#elif defined(__ARM_ARCH_7A__)
+ SOC_GPIO6_BASE,
+ 66,
+#else
+ SOC_GPIO6_BASE,
+ 49,
+#endif
+ 0,
+ 60,
+ 0
+ },
+ {
+#ifdef _TMS320C6X
+ SOC_GPIO7_BASE,
+ OSAL_REGINT_INTVEC_EVENT_COMBINER,
+#elif defined(__ARM_ARCH_7A__)
+ SOC_GPIO7_BASE,
+ 67,
+#else
+ SOC_GPIO7_BASE,
+ 49,
+#endif
+ 0,
+ 61,
+ 0
+ },
+ {
+#ifdef _TMS320C6X
+ SOC_GPIO8_BASE,
+ OSAL_REGINT_INTVEC_EVENT_COMBINER,
+#elif defined(__ARM_ARCH_7A__)
+ SOC_GPIO8_BASE,
+ 153,
+#else
+ SOC_GPIO8_BASE,
+ 49,
+#endif
+ 0,
+ 0,
+ 0
+ },
+};
+
+/* GPIO configuration structure */
+CSL_PUBLIC_CONST GPIOConfigList GPIO_config =
+{
+ {
+ &GPIO_FxnTable_v1,
+ NULL,
+ NULL
+ },
+ /* "pad to full predefined length of array" */
+ {
+ NULL,
+ NULL,
+ NULL
+ },
+ {
+ NULL,
+ NULL,
+ NULL
+ }
+};
diff --git a/packages/ti/drv/gpio/soc/dra78x/GPIO_soc.c b/packages/ti/drv/gpio/soc/dra78x/GPIO_soc.c
--- /dev/null
@@ -0,0 +1,122 @@
+/**
+ * \file dra78x/GPIO_soc.c
+ *
+ * \brief DRA78X SOC specific GPIO hardware attributes.
+ *
+ * This file contains the GPIO hardware attributes like base address and
+ * interrupt ids.
+ */
+
+/*
+ * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+#include <ti/csl/csl_utils.h>
+#include <ti/csl/soc.h>
+#include <ti/csl/csl_types.h>
+#include <ti/drv/gpio/GPIO.h>
+#include <ti/drv/gpio/soc/GPIO_soc.h>
+
+/* Number of GPIO ports */
+#define CSL_GPIO_PER_CNT 4U
+
+/* GPIO Driver hardware attributes */
+GPIO_v1_hwAttrs_list GPIO_v1_hwAttrs = {
+ {
+#ifdef _TMS320C6X
+ SOC_GPIO1_BASE,
+ OSAL_REGINT_INTVEC_EVENT_COMBINER,
+#else
+ SOC_GPIO1_BASE,
+ 51,
+#endif
+ 0,
+ 55,
+ 0
+ },
+ {
+#ifdef _TMS320C6X
+ SOC_GPIO2_BASE,
+ OSAL_REGINT_INTVEC_EVENT_COMBINER,
+#else
+ SOC_GPIO2_BASE,
+ 52,
+#endif
+ 0,
+ 56,
+ 0
+ },
+ {
+#ifdef _TMS320C6X
+ SOC_GPIO3_BASE,
+ OSAL_REGINT_INTVEC_EVENT_COMBINER,
+#else
+ SOC_GPIO3_BASE,
+ 55,
+#endif
+ 0,
+ 57,
+ 0
+ },
+ {
+#ifdef _TMS320C6X
+ SOC_GPIO4_BASE,
+ OSAL_REGINT_INTVEC_EVENT_COMBINER,
+#else
+ SOC_GPIO4_BASE,
+ 56,
+#endif
+ 0,
+ 58,
+ 0
+ },
+};
+
+/* GPIO configuration structure */
+CSL_PUBLIC_CONST GPIOConfigList GPIO_config =
+{
+ {
+ &GPIO_FxnTable_v1,
+ NULL,
+ NULL
+ },
+ /* "pad to full predefined length of array" */
+ {
+ NULL,
+ NULL,
+ NULL
+ },
+ {
+ NULL,
+ NULL,
+ NULL
+ }
+};
diff --git a/packages/ti/drv/gpio/soc/j721e/GPIO_soc.c b/packages/ti/drv/gpio/soc/j721e/GPIO_soc.c
--- /dev/null
@@ -0,0 +1,854 @@
+/**
+ * \file j721e/GPIO_soc.c
+ *
+ * \brief J721E SOC specific GPIO hardware attributes.
+ *
+ * This file contains the GPIO hardware attributes like base address and
+ * interrupt ids.
+ */
+
+/*
+ * Copyright (C) 2018 - 2019 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include <string.h>
+#include <ti/csl/csl_utils.h>
+#include <ti/csl/soc/j721e/src/cslr_soc.h>
+#include <ti/csl/csl_types.h>
+#include <ti/csl/hw_types.h>
+#include <ti/csl/soc.h>
+#include <ti/csl/arch/csl_arch.h>
+#include <ti/drv/gpio/soc/GPIO_soc.h>
+#include <ti/drv/sciclient/sciclient.h>
+#include <ti/csl/csl_clec.h>
+#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
+#include <ti/csl/csl_chipAux.h>
+#endif
+
+/** \brief Number of gpio pins for each port */
+#define GPIO_NUM_PINS_PER_PORT (128U)
+
+/** \brief Number of gpio ports present in the soc */
+#define GPIO_NUM_PORTS (8U)
+
+/* define the interrupt start number for GPIO on C66x */
+#define GPIO_TISCI_C66X_DST_HOST_IRQ0 (70U)
+
+/* define the interrupt start number for GPIO on C7x */
+#define GPIO_C7X_IRQ0 (40U)
+
+/* CLEC input event # offset for GIC SPI */
+#define GPIO_CLEC_GIC_SPI_IN_EVT_OFFSET (1024U - 32U)
+
+/* GPIO Pin interrupt configurations */
+GPIO_IntCfg GPIO_intCfgs[GPIO_NUM_PORTS][GPIO_NUM_PINS_PER_PORT] =
+{
+ {
+ /* GPIO port 0 pin 0 */
+ {
+#if defined (BUILD_MPU)
+ /* main domain */
+ CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_GPIOMUX_INTRTR0_OUTP_8, /* main int router output interrupt number */
+ 0, /* GPIO pin interrupt event */
+#endif
+#if defined (BUILD_MCU)
+ /* mcu domain */
+ CSLR_MCU_R5FSS0_CORE0_INTR_MAIN2MCU_LVL_INTRTR0_OUTL_0, /* main 2 mcu int router output interrupt number */
+ 0, /* GPIO pin interrupt event */
+#endif
+#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
+ /* main domain */
+ OSAL_REGINT_INTVEC_EVENT_COMBINER, /* main 2 c66x int router output interrupt number */
+ GPIO_TISCI_C66X_DST_HOST_IRQ0, /* GPIO pin interrupt event */
+#endif
+#if defined (BUILD_C7X_1)
+ /* main domain */
+ GPIO_C7X_IRQ0, /* main 2 c7x CLEC output interrupt number */
+ CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_GPIOMUX_INTRTR0_OUTP_8 + GPIO_CLEC_GIC_SPI_IN_EVT_OFFSET, /* GPIO pin interrupt event */
+#endif
+ INVALID_INTC_MUX_NUM, /* CIC not used for GPIO pin 0 */
+ 0,
+ 0
+ },
+ /* GPIO port 0 pin 1 */
+ {
+#if defined (BUILD_MPU)
+ /* main domain */
+ CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_GPIOMUX_INTRTR0_OUTP_8, /* main int router output interrupt number */
+ 0, /* GPIO pin interrupt event */
+#endif
+#if defined (BUILD_MCU)
+ /* mcu domain */
+ CSLR_MCU_R5FSS0_CORE0_INTR_MAIN2MCU_LVL_INTRTR0_OUTL_0, /* main 2 mcu int router output interrupt number */
+ 0, /* GPIO pin interrupt event */
+#endif
+#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
+ /* main domain */
+ OSAL_REGINT_INTVEC_EVENT_COMBINER, /* main 2 c66x int router output interrupt number */
+ GPIO_TISCI_C66X_DST_HOST_IRQ0, /* GPIO pin interrupt event */
+#endif
+#if defined (BUILD_C7X_1)
+ /* main domain */
+ GPIO_C7X_IRQ0, /* main 2 c7x CLEC output interrupt number */
+ CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_GPIOMUX_INTRTR0_OUTP_8 + GPIO_CLEC_GIC_SPI_IN_EVT_OFFSET, /* GPIO pin interrupt event */
+#endif
+ INVALID_INTC_MUX_NUM,
+ 0,
+ 0
+ },
+ /* GPIO port 0 pin 2 */
+ {
+#if defined (BUILD_MPU)
+ /* main domain */
+ CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_GPIOMUX_INTRTR0_OUTP_8, /* main int router output interrupt number */
+ 0, /* GPIO pin interrupt event */
+#endif
+#if defined (BUILD_MCU)
+ /* mcu domain */
+ CSLR_MCU_R5FSS0_CORE0_INTR_MAIN2MCU_LVL_INTRTR0_OUTL_0, /* main 2 mcu int router output interrupt number */
+ 0, /* GPIO pin interrupt event */
+#endif
+#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
+ /* main domain */
+ OSAL_REGINT_INTVEC_EVENT_COMBINER, /* main 2 c66x int router output interrupt number */
+ GPIO_TISCI_C66X_DST_HOST_IRQ0, /* GPIO pin interrupt event */
+#endif
+#if defined (BUILD_C7X_1)
+ /* main domain */
+ GPIO_C7X_IRQ0, /* main 2 c7x CLEC output interrupt number */
+ CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_GPIOMUX_INTRTR0_OUTP_8 + GPIO_CLEC_GIC_SPI_IN_EVT_OFFSET, /* GPIO pin interrupt event */
+#endif
+ INVALID_INTC_MUX_NUM,
+ 0,
+ 0
+ },
+ /* GPIO port 0 pin 3 */
+ {
+#if defined (BUILD_MPU)
+ /* main domain */
+ CSLR_MCU_R5FSS0_CORE0_INTR_MAIN2MCU_LVL_INTRTR0_OUTL_0, /* main int router output interrupt number */
+ 0, /* GPIO pin interrupt event */
+#endif
+#if defined (BUILD_MCU)
+ /* mcu domain */
+ CSLR_MCU_R5FSS0_CORE0_INTR_MAIN2MCU_LVL_INTRTR0_OUTL_0, /* main 2 mcu int router output interrupt number */
+ 0, /* GPIO pin interrupt event */
+#endif
+#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
+ /* main domain */
+ OSAL_REGINT_INTVEC_EVENT_COMBINER, /* main 2 c66x int router output interrupt number */
+ GPIO_TISCI_C66X_DST_HOST_IRQ0, /* GPIO pin interrupt event */
+#endif
+#if defined (BUILD_C7X_1)
+ /* main domain */
+ GPIO_C7X_IRQ0, /* main 2 c7x CLEC output interrupt number */
+ CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_GPIOMUX_INTRTR0_OUTP_8 + GPIO_CLEC_GIC_SPI_IN_EVT_OFFSET, /* GPIO pin interrupt event */
+#endif
+ INVALID_INTC_MUX_NUM,
+ 0,
+ 0
+ },
+ /* GPIO port 0 pin 4 */
+ {
+#if defined (BUILD_MPU)
+ /* main domain */
+ CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_GPIOMUX_INTRTR0_OUTP_8, /* main int router output interrupt number */
+ 0, /* GPIO pin interrupt event */
+#endif
+#if defined (BUILD_MCU)
+ /* mcu domain */
+ CSLR_MCU_R5FSS0_CORE0_INTR_MAIN2MCU_LVL_INTRTR0_OUTL_0, /* main 2 mcu int router output interrupt number */
+ 0, /* GPIO pin interrupt event */
+#endif
+#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
+ /* main domain */
+ OSAL_REGINT_INTVEC_EVENT_COMBINER, /* main 2 c66x int router output interrupt number */
+ GPIO_TISCI_C66X_DST_HOST_IRQ0, /* GPIO pin interrupt event */
+#endif
+#if defined (BUILD_C7X_1)
+ /* main domain */
+ GPIO_C7X_IRQ0, /* main 2 c7x CLEC output interrupt number */
+ CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_GPIOMUX_INTRTR0_OUTP_8 + GPIO_CLEC_GIC_SPI_IN_EVT_OFFSET, /* GPIO pin interrupt event */
+#endif
+ INVALID_INTC_MUX_NUM,
+ 0,
+ 0
+ },
+ /* GPIO port 0 pin 5 */
+ {
+#if defined (BUILD_MPU)
+ /* main domain */
+ CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_GPIOMUX_INTRTR0_OUTP_8, /* main int router output interrupt number */
+ 0, /* GPIO pin interrupt event */
+#endif
+#if defined (BUILD_MCU)
+ /* mcu domain */
+ CSLR_MCU_R5FSS0_CORE0_INTR_MAIN2MCU_LVL_INTRTR0_OUTL_0, /* main 2 mcu int router output interrupt number */
+ 0, /* GPIO pin interrupt event */
+#endif
+#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
+ /* main domain */
+ OSAL_REGINT_INTVEC_EVENT_COMBINER, /* main 2 c66x int router output interrupt number */
+ GPIO_TISCI_C66X_DST_HOST_IRQ0, /* GPIO pin interrupt event */
+#endif
+#if defined (BUILD_C7X_1)
+ /* main domain */
+ GPIO_C7X_IRQ0, /* main 2 c7x CLEC output interrupt number */
+ CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_GPIOMUX_INTRTR0_OUTP_8 + GPIO_CLEC_GIC_SPI_IN_EVT_OFFSET, /* GPIO pin interrupt event */
+#endif
+ INVALID_INTC_MUX_NUM,
+ 0,
+ 0
+ },
+ /* GPIO port 0 pin 6 */
+ {
+#if defined (BUILD_MPU)
+ /* main domain */
+ CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_GPIOMUX_INTRTR0_OUTP_8, /* main int router output interrupt number */
+ 0, /* GPIO pin interrupt event */
+#endif
+#if defined (BUILD_MCU)
+ /* mcu domain */
+ CSLR_MCU_R5FSS0_CORE0_INTR_MAIN2MCU_LVL_INTRTR0_OUTL_0, /* main 2 mcu int router output interrupt number */
+ 0, /* GPIO pin interrupt event */
+#endif
+#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
+ /* main domain */
+ OSAL_REGINT_INTVEC_EVENT_COMBINER, /* main 2 c66x int router output interrupt number */
+ GPIO_TISCI_C66X_DST_HOST_IRQ0, /* GPIO pin interrupt event */
+#endif
+#if defined (BUILD_C7X_1)
+ /* main domain */
+ GPIO_C7X_IRQ0, /* main 2 c7x CLEC output interrupt number */
+ CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_GPIOMUX_INTRTR0_OUTP_8 + GPIO_CLEC_GIC_SPI_IN_EVT_OFFSET, /* GPIO pin interrupt event */
+#endif
+ INVALID_INTC_MUX_NUM,
+ 0,
+ 0
+ },
+ /* GPIO port 0 pin 7 */
+ {
+#if defined (BUILD_MPU)
+ /* main domain */
+ CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_GPIOMUX_INTRTR0_OUTP_8, /* main int router output interrupt number */
+ 0, /* GPIO pin interrupt event */
+#endif
+#if defined (BUILD_MCU)
+ /* mcu domain */
+ CSLR_MCU_R5FSS0_CORE0_INTR_MAIN2MCU_LVL_INTRTR0_OUTL_0, /* main 2 mcu int router output interrupt number */
+ 0, /* GPIO pin interrupt event */
+#endif
+#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
+ /* main domain */
+ OSAL_REGINT_INTVEC_EVENT_COMBINER, /* main 2 c66x int router output interrupt number */
+ GPIO_TISCI_C66X_DST_HOST_IRQ0, /* GPIO pin interrupt event */
+#endif
+#if defined (BUILD_C7X_1)
+ /* main domain */
+ GPIO_C7X_IRQ0, /* main 2 c7x CLEC output interrupt number */
+ CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_GPIOMUX_INTRTR0_OUTP_8 + GPIO_CLEC_GIC_SPI_IN_EVT_OFFSET, /* GPIO pin interrupt event */
+#endif
+ INVALID_INTC_MUX_NUM,
+ 0,
+ 0
+ },
+ /* GPIO port 0 pin 8 */
+ {
+#if defined (BUILD_MPU)
+ /* main domain */
+ CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_GPIOMUX_INTRTR0_OUTP_8, /* main int router output interrupt number */
+ 0, /* GPIO pin interrupt event */
+#endif
+#if defined (BUILD_MCU)
+ /* mcu domain */
+ CSLR_MCU_R5FSS0_CORE0_INTR_MAIN2MCU_LVL_INTRTR0_OUTL_0, /* main 2 mcu int router output interrupt number */
+ 0, /* GPIO pin interrupt event */
+#endif
+#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
+ /* main domain */
+ OSAL_REGINT_INTVEC_EVENT_COMBINER, /* main 2 c66x int router output interrupt number */
+ GPIO_TISCI_C66X_DST_HOST_IRQ0, /* GPIO pin interrupt event */
+#endif
+#if defined (BUILD_C7X_1)
+ /* main domain */
+ GPIO_C7X_IRQ0, /* main 2 c7x CLEC output interrupt number */
+ CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_GPIOMUX_INTRTR0_OUTP_8 + GPIO_CLEC_GIC_SPI_IN_EVT_OFFSET, /* GPIO pin interrupt event */
+#endif
+ INVALID_INTC_MUX_NUM,
+ 0,
+ 0
+ },
+ /* GPIO port 0 pin 9 */
+ {
+#if defined (BUILD_MPU)
+ /* main domain */
+ CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_GPIOMUX_INTRTR0_OUTP_8, /* main int router output interrupt number */
+ 0, /* GPIO pin interrupt event */
+#endif
+#if defined (BUILD_MCU)
+ /* mcu domain */
+ CSLR_MCU_R5FSS0_CORE0_INTR_MAIN2MCU_LVL_INTRTR0_OUTL_0, /* main 2 mcu int router output interrupt number */
+ 0, /* GPIO pin interrupt event */
+#endif
+#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
+ /* main domain */
+ OSAL_REGINT_INTVEC_EVENT_COMBINER, /* main 2 c66x int router output interrupt number */
+ GPIO_TISCI_C66X_DST_HOST_IRQ0, /* GPIO pin interrupt event */
+#endif
+#if defined (BUILD_C7X_1)
+ /* main domain */
+ GPIO_C7X_IRQ0, /* main 2 c7x CLEC output interrupt number */
+ CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_GPIOMUX_INTRTR0_OUTP_8 + GPIO_CLEC_GIC_SPI_IN_EVT_OFFSET, /* GPIO pin interrupt event */
+#endif
+ INVALID_INTC_MUX_NUM,
+ 0,
+ 0
+ },
+ /* GPIO port 0 pin 10 */
+ {
+#if defined (BUILD_MPU)
+ /* main domain */
+ CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_GPIOMUX_INTRTR0_OUTP_8, /* main int router output interrupt number */
+ 0, /* GPIO pin interrupt event */
+#endif
+#if defined (BUILD_MCU)
+ /* mcu domain */
+ CSLR_MCU_R5FSS0_CORE0_INTR_MAIN2MCU_LVL_INTRTR0_OUTL_0, /* main 2 mcu int router output interrupt number */
+ 0, /* GPIO pin interrupt event */
+#endif
+#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
+ /* main domain */
+ OSAL_REGINT_INTVEC_EVENT_COMBINER, /* main 2 c66x int router output interrupt number */
+ GPIO_TISCI_C66X_DST_HOST_IRQ0, /* GPIO pin interrupt event */
+#endif
+#if defined (BUILD_C7X_1)
+ /* main domain */
+ GPIO_C7X_IRQ0, /* main 2 c7x CLEC output interrupt number */
+ CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_GPIOMUX_INTRTR0_OUTP_8 + GPIO_CLEC_GIC_SPI_IN_EVT_OFFSET, /* GPIO pin interrupt event */
+#endif
+ INVALID_INTC_MUX_NUM,
+ 0,
+ 0
+ },
+ /* GPIO port 0 pin 11 */
+ {
+#if defined (BUILD_MPU)
+ /* main domain */
+ CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_GPIOMUX_INTRTR0_OUTP_8, /* main int router output interrupt number */
+ 0, /* GPIO pin interrupt event */
+#endif
+#if defined (BUILD_MCU)
+ /* mcu domain */
+ CSLR_MCU_R5FSS0_CORE0_INTR_MAIN2MCU_LVL_INTRTR0_OUTL_0, /* main 2 mcu int router output interrupt number */
+ 0, /* GPIO pin interrupt event */
+#endif
+#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
+ /* main domain */
+ OSAL_REGINT_INTVEC_EVENT_COMBINER, /* main 2 c66x int router output interrupt number */
+ GPIO_TISCI_C66X_DST_HOST_IRQ0, /* GPIO pin interrupt event */
+#endif
+#if defined (BUILD_C7X_1)
+ /* main domain */
+ GPIO_C7X_IRQ0, /* main 2 c7x CLEC output interrupt number */
+ CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_GPIOMUX_INTRTR0_OUTP_8 + GPIO_CLEC_GIC_SPI_IN_EVT_OFFSET, /* GPIO pin interrupt event */
+#endif
+ INVALID_INTC_MUX_NUM,
+ 0,
+ 0
+ },
+ /* GPIO port 0 pin 12 */
+ {
+#if defined (BUILD_MPU)
+ /* main domain */
+ CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_GPIOMUX_INTRTR0_OUTP_8, /* main int router output interrupt number */
+ 0, /* GPIO pin interrupt event */
+#endif
+#if defined (BUILD_MCU)
+ /* mcu domain */
+ CSLR_MCU_R5FSS0_CORE0_INTR_MAIN2MCU_LVL_INTRTR0_OUTL_0, /* main 2 mcu int router output interrupt number */
+ 0, /* GPIO pin interrupt event */
+#endif
+#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
+ /* main domain */
+ OSAL_REGINT_INTVEC_EVENT_COMBINER, /* main 2 c66x int router output interrupt number */
+ GPIO_TISCI_C66X_DST_HOST_IRQ0, /* GPIO pin interrupt event */
+#endif
+#if defined (BUILD_C7X_1)
+ /* main domain */
+ GPIO_C7X_IRQ0, /* main 2 c7x CLEC output interrupt number */
+ CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_GPIOMUX_INTRTR0_OUTP_8 + GPIO_CLEC_GIC_SPI_IN_EVT_OFFSET, /* GPIO pin interrupt event */
+#endif
+ INVALID_INTC_MUX_NUM,
+ 0,
+ 0
+ },
+ /* GPIO port 0 pin 13 */
+ {
+#if defined (BUILD_MPU)
+ /* main domain */
+ CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_GPIOMUX_INTRTR0_OUTP_8, /* main int router output interrupt number */
+ 0, /* GPIO pin interrupt event */
+#endif
+#if defined (BUILD_MCU)
+ /* mcu domain */
+ CSLR_MCU_R5FSS0_CORE0_INTR_MAIN2MCU_LVL_INTRTR0_OUTL_0, /* main 2 mcu int router output interrupt number */
+ 0, /* GPIO pin interrupt event */
+#endif
+#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
+ /* main domain */
+ OSAL_REGINT_INTVEC_EVENT_COMBINER, /* main 2 c66x int router output interrupt number */
+ GPIO_TISCI_C66X_DST_HOST_IRQ0, /* GPIO pin interrupt event */
+#endif
+#if defined (BUILD_C7X_1)
+ /* main domain */
+ GPIO_C7X_IRQ0, /* main 2 c7x CLEC output interrupt number */
+ CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_GPIOMUX_INTRTR0_OUTP_8 + GPIO_CLEC_GIC_SPI_IN_EVT_OFFSET, /* GPIO pin interrupt event */
+#endif
+ INVALID_INTC_MUX_NUM,
+ 0,
+ 0
+ },
+ /* GPIO port 0 pin 14 */
+ {
+#if defined (BUILD_MPU)
+ /* main domain */
+ CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_GPIOMUX_INTRTR0_OUTP_8, /* main int router output interrupt number */
+ 0, /* GPIO pin interrupt event */
+#endif
+#if defined (BUILD_MCU)
+ /* mcu domain */
+ CSLR_MCU_R5FSS0_CORE0_INTR_MAIN2MCU_LVL_INTRTR0_OUTL_0, /* main 2 mcu int router output interrupt number */
+ 0, /* GPIO pin interrupt event */
+#endif
+#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
+ /* main domain */
+ OSAL_REGINT_INTVEC_EVENT_COMBINER, /* main 2 c66x int router output interrupt number */
+ GPIO_TISCI_C66X_DST_HOST_IRQ0, /* GPIO pin interrupt event */
+#endif
+#if defined (BUILD_C7X_1)
+ /* main domain */
+ GPIO_C7X_IRQ0, /* main 2 c7x CLEC output interrupt number */
+ CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_GPIOMUX_INTRTR0_OUTP_8 + GPIO_CLEC_GIC_SPI_IN_EVT_OFFSET, /* GPIO pin interrupt event */
+#endif
+ INVALID_INTC_MUX_NUM,
+ 0,
+ 0
+ },
+ /* GPIO port 0 pin 15 */
+ {
+#if defined (BUILD_MPU)
+ /* main domain */
+ CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_GPIOMUX_INTRTR0_OUTP_8, /* main int router output interrupt number */
+ 0, /* GPIO pin interrupt event */
+#endif
+#if defined (BUILD_MCU)
+ /* mcu domain */
+ CSLR_MCU_R5FSS0_CORE0_INTR_MAIN2MCU_LVL_INTRTR0_OUTL_0, /* main 2 mcu int router output interrupt number */
+ 0, /* GPIO pin interrupt event */
+#endif
+#if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
+ /* main domain */
+ OSAL_REGINT_INTVEC_EVENT_COMBINER, /* main 2 c66x int router output interrupt number */
+ GPIO_TISCI_C66X_DST_HOST_IRQ0, /* GPIO pin interrupt event */
+#endif
+#if defined (BUILD_C7X_1)
+ /* main domain */
+ GPIO_C7X_IRQ0, /* main 2 c7x CLEC output interrupt number */
+ CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_GPIOMUX_INTRTR0_OUTP_8 + GPIO_CLEC_GIC_SPI_IN_EVT_OFFSET, /* GPIO pin interrupt event */
+#endif
+ INVALID_INTC_MUX_NUM,
+ 0,
+ 0
+ },
+ },
+};
+
+/* GPIO Driver hardware attributes */
+GPIO_v0_hwAttrsList GPIO_v0_hwAttrs =
+{
+ {
+ (uint32_t)CSL_GPIO0_BASE,
+ &GPIO_intCfgs[0][0],
+ &GPIO_socConfigIntrPath,
+ },
+ {
+ (uint32_t)CSL_GPIO1_BASE,
+ &GPIO_intCfgs[1][0],
+ &GPIO_socConfigIntrPath,
+ },
+ {
+ (uint32_t)CSL_GPIO2_BASE,
+ &GPIO_intCfgs[2][0],
+ &GPIO_socConfigIntrPath,
+ },
+ {
+ (uint32_t)CSL_GPIO3_BASE,
+ &GPIO_intCfgs[3][0],
+ &GPIO_socConfigIntrPath,
+ },
+ {
+ (uint32_t)CSL_GPIO4_BASE,
+ &GPIO_intCfgs[4][0],
+ &GPIO_socConfigIntrPath,
+ },
+ {
+ (uint32_t)CSL_GPIO5_BASE,
+ &GPIO_intCfgs[5][0],
+ &GPIO_socConfigIntrPath,
+ },
+ {
+ (uint32_t)CSL_GPIO6_BASE,
+ &GPIO_intCfgs[6][0],
+ &GPIO_socConfigIntrPath,
+ },
+ {
+ (uint32_t)CSL_GPIO7_BASE,
+ &GPIO_intCfgs[7][0],
+ &GPIO_socConfigIntrPath,
+ }
+};
+
+/* GPIO configuration structure */
+CSL_PUBLIC_CONST GPIOConfigList GPIO_config =
+{
+ {
+ &GPIO_FxnTable_v0,
+ NULL,
+ &GPIO_v0_hwAttrs[0]
+ },
+
+ {
+ &GPIO_FxnTable_v0,
+ NULL,
+ &GPIO_v0_hwAttrs[1]
+ },
+
+ {
+ NULL,
+ NULL,
+ NULL
+ }
+};
+
+/**
+ * \brief This API gets the SoC level of GPIO intial configuration
+ *
+ * \param idx GPIO instance index.
+ * \param cfg Pointer to GPIO SOC initial config.
+ *
+ * \return 0 success: -1: error
+ *
+ */
+int32_t GPIO_socGetInitCfg(uint32_t idx, GPIO_v0_HwAttrs *cfg)
+{
+ int32_t ret = 0;
+
+ if (idx < GPIO_NUM_PORTS)
+ {
+ *cfg = GPIO_v0_hwAttrs[idx];
+ }
+ else
+ {
+ ret = -1;
+ }
+
+ return ret;
+}
+
+/**
+ * \brief This API sets the SoC level of GPIO intial configuration
+ *
+ * \param idx GPIO instance index.
+ * \param cfg Pointer to GPIO SOC initial config.
+ *
+ * \return 0 success: -1: error
+ *
+ */
+int32_t GPIO_socSetInitCfg(uint32_t idx, const GPIO_v0_HwAttrs *cfg)
+{
+ int32_t ret = 0;
+
+ if (idx < GPIO_NUM_PORTS)
+ {
+ GPIO_v0_hwAttrs[idx] = *cfg;
+ }
+ else
+ {
+ ret = -1;
+ }
+
+ return ret;
+}
+
+/**
+ * \brief This API gets the number of GPIO pins per port
+ * and GPIO number of ports
+ *
+ * \param numPins pointer to numPins variable.
+ * \param numPorts pointer to numPorts variable.
+ *
+ * \return none
+ *
+ */
+void GPIO_socGetNumPinsPorts(uint32_t *numPins, uint32_t *numPorts)
+{
+ *numPins = GPIO_NUM_PINS_PER_PORT;
+ *numPorts = GPIO_NUM_PORTS;
+}
+
+void MuxIntcP_clearInEvent(int32_t muxNum, int32_t muxInEvent)
+{
+ (void)muxNum;
+ (void)muxInEvent;
+
+ return;
+}
+
+
+MuxIntcP_Status MuxIntcP_create(MuxIntcP_inParams *inParams, MuxIntcP_outParams *outParams)
+{
+ inParams = inParams;
+ outParams = outParams;
+
+ return (MuxIntcP_OK);
+}
+
+/* A count kept for each bank usage/ 16 pins share a bank */
+#define GPIO_NUM_BANKS ((GPIO_NUM_PINS_PER_PORT + 15U) / 16U)
+uint32_t GPIO_PinBankUsageCount[GPIO_NUM_PORTS][GPIO_NUM_BANKS] = {0U, };
+
+/**
+ * \brief This function sets/clears the soc interrupt path including the \n
+ * interrupt routers (GPIO_RTR,MAIN2MCU_RTR) etc and GPIO number of ports
+ *
+ * \param portNum The GPIO port number to configure the interrupt path.
+ * \param pinNum The GPIO pin number to configure the interrupt path.
+ * \param hwAttrs The GPIO_v0_HwAttrs for this SOC
+ * \param setIntrPath TRUE - set the interrupt path, FALSE - clear the interrupt path
+ * \return CSL_PASS if successful, CSL_FAIL if failed
+ *
+ */
+int32_t GPIO_socConfigIntrPath(uint32_t portNum, uint32_t pinNum,void *hwAttrs,bool setIntrPath)
+{
+
+ GPIO_v0_HwAttrs *cfg = (GPIO_v0_HwAttrs *)hwAttrs;
+ GPIO_IntCfg *intCfg;
+ uint32_t bankNum;
+ int32_t retVal=CSL_PASS;
+#if defined(BUILD_MCU1_0) || defined(BUILD_MCU1_1) || defined(BUILD_MCU2_0) || defined(BUILD_MCU2_1) || defined(BUILD_MCU3_0) || defined(BUILD_MCU3_1)
+ CSL_ArmR5CPUInfo r5CpuInfo;
+#endif
+ struct tisci_msg_rm_irq_set_req rmIrqReq;
+ struct tisci_msg_rm_irq_set_resp rmIrqResp;
+ struct tisci_msg_rm_irq_release_req rmIrqRelease;
+ uint16_t src_id,src_index,dst_id,dst_host_irq;
+
+ intCfg = cfg->intCfg;
+ cfg->baseAddr = (uint32_t)CSL_WKUP_GPIO0_BASE; /* For AM65x GP EVM */
+
+#if defined(BUILD_MCU1_0) || defined(BUILD_MCU1_1) || defined(BUILD_MCU2_0) || defined(BUILD_MCU2_1) || defined(BUILD_MCU3_0) || defined(BUILD_MCU3_1)
+ CSL_armR5GetCpuID(&r5CpuInfo);
+#endif
+ /* Input parameter validation */
+ bankNum = pinNum/16U; /* Each GPIO bank has 16 pins */
+
+ /* We route bank interrupts to the cpu interrupts */
+ switch (cfg->baseAddr)
+ {
+ case (uint32_t)CSL_WKUP_GPIO0_BASE:
+ src_id = TISCI_DEV_WKUP_GPIO0;
+ src_index = (uint16_t)bankNum; /* This is the bus_gpio_bank (0-5) mentioned in DMSC firmware guide for J721E_DEV_WKUP_GPIO0 */
+ break;
+ case (uint32_t)CSL_WKUP_GPIO1_BASE:
+ src_id = TISCI_DEV_WKUP_GPIO1;
+ src_index = (uint16_t)bankNum; /* This is the bus_gpio_bank (0-5) mentioned in DMSC firmware guide for J721E_DEV_WKUP_GPIO1 */
+ break;
+ case (uint32_t)CSL_GPIO0_BASE:
+ src_id = TISCI_DEV_GPIO0;
+ src_index = (uint16_t)bankNum; /* This is the bus_gpio_bank (0-7) mentioned in DMSC firmware guide for J721E_DEV_GPIO0 */
+ break;
+ case (uint32_t)CSL_GPIO2_BASE:
+ src_id = TISCI_DEV_GPIO2;
+ src_index = (uint16_t)bankNum; /* This is the bus_gpio_bank (0-7) mentioned in DMSC firmware guide for J721E_DEV_GPIO2 */
+ break;
+ case (uint32_t)CSL_GPIO4_BASE:
+ src_id = TISCI_DEV_GPIO4;
+ src_index = (uint16_t)bankNum; /* This is the bus_gpio_bank (0-7) mentioned in DMSC firmware guide for J721E_DEV_GPIO4 */
+ break;
+ case (uint32_t)CSL_GPIO6_BASE:
+ src_id = TISCI_DEV_GPIO6;
+ src_index = (uint16_t)bankNum; /* This is the bus_gpio_bank (0-7) mentioned in DMSC firmware guide for J721E_DEV_GPIO6 */
+ break;
+ case (uint32_t)CSL_GPIO1_BASE:
+ src_id = TISCI_DEV_GPIO1;
+ src_index = (uint16_t)bankNum; /* This is the bus_gpio_bank (0-2) mentioned in DMSC firmware guide for J721E_DEV_GPIO1 */
+ break;
+ case (uint32_t)CSL_GPIO3_BASE:
+ src_id = TISCI_DEV_GPIO3;
+ src_index = (uint16_t)bankNum; /* This is the bus_gpio_bank (0-2) mentioned in DMSC firmware guide for J721E_DEV_GPIO3 */
+ break;
+ case (uint32_t)CSL_GPIO5_BASE:
+ src_id = TISCI_DEV_GPIO5;
+ src_index = (uint16_t)bankNum; /* This is the bus_gpio_bank (0-2) mentioned in DMSC firmware guide for J721E_DEV_GPIO5 */
+ break;
+ case (uint32_t)CSL_GPIO7_BASE:
+ src_id = TISCI_DEV_GPIO7;
+ src_index = (uint16_t)bankNum; /* This is the bus_gpio_bank (0-2) mentioned in DMSC firmware guide for J721E_DEV_GPIO7 */
+ break;
+ default:
+ break;
+ }
+
+ /* GPIO uses bank interrupts. So choose the bank interrupts from bus_gpio_bank with valid values from
+ * the DMSC firmware user guide */
+#if defined(BUILD_MCU1_0) || defined(BUILD_MCU1_1)
+ if(r5CpuInfo.cpuID == 0U) {
+ dst_id = TISCI_DEV_MCU_R5FSS0_CORE0;
+ dst_host_irq = (uint16_t)intCfg[pinNum].intNum;
+ } else {
+ dst_id = TISCI_DEV_MCU_R5FSS0_CORE1;
+ dst_host_irq = (uint16_t)intCfg[pinNum].intNum;
+ }
+#elif defined(BUILD_MCU2_0) || defined(BUILD_MCU2_1)
+ if(r5CpuInfo.cpuID == 0U) {
+ dst_id = TISCI_DEV_R5FSS0_CORE0;
+ dst_host_irq = (uint16_t)intCfg[pinNum].intNum;
+ } else {
+ dst_id = TISCI_DEV_R5FSS0_CORE1;
+ dst_host_irq = (uint16_t)intCfg[pinNum].intNum;
+ }
+#elif defined(BUILD_MCU3_0) || defined(BUILD_MCU3_1)
+ if(r5CpuInfo.cpuID == 0U) {
+ dst_id = TISCI_DEV_R5FSS1_CORE0;
+ dst_host_irq = (uint16_t)intCfg[pinNum].intNum;
+ } else {
+ dst_id = TISCI_DEV_R5FSS1_CORE1;
+ dst_host_irq = (uint16_t)intCfg[pinNum].intNum;
+ }
+#elif defined(BUILD_MPU1_0) || defined(BUILD_MPU1_1)
+ dst_id = TISCI_DEV_COMPUTE_CLUSTER0_GIC500SS;
+ dst_host_irq = (uint16_t)intCfg[pinNum].intNum;
+#elif defined(BUILD_DSP_1) || defined(BUILD_DSP_2)
+ if (CSL_chipReadDNUM() == 0U)
+ {
+ /* Set the destination for core0 */
+ dst_id = TISCI_DEV_C66SS0_CORE0;
+ }
+ else
+ {
+ /* Set the destination for core1 */
+ dst_id = TISCI_DEV_C66SS1_CORE0;
+ }
+ dst_host_irq = (uint16_t)intCfg[pinNum].eventId;
+#elif defined(BUILD_C7X_1)
+ dst_id = TISCI_DEV_COMPUTE_CLUSTER0_CLEC;
+ dst_host_irq = (uint16_t)(CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_WKUP_GPIOMUX_INTRTR0_OUTP_16 + bankNum);
+#endif
+
+ if(setIntrPath) {
+ (void)memset (&rmIrqReq,0,sizeof(rmIrqReq));
+
+ rmIrqReq.secondary_host = TISCI_MSG_VALUE_RM_UNUSED_SECONDARY_HOST;
+ rmIrqReq.src_id = src_id;
+ rmIrqReq.src_index = src_index; /* This is the event coming out of
+ the peripheral */
+
+ /* Set the destination interrupt */
+ rmIrqReq.valid_params |= TISCI_MSG_VALUE_RM_DST_ID_VALID;
+ rmIrqReq.valid_params |= TISCI_MSG_VALUE_RM_DST_HOST_IRQ_VALID;
+
+ /* Set the destination based on the core */
+ rmIrqReq.dst_id = dst_id;
+ rmIrqReq.dst_host_irq = dst_host_irq;
+ } else {
+ (void)memset (&rmIrqRelease,0,sizeof(rmIrqRelease));
+
+ rmIrqRelease.secondary_host = TISCI_MSG_VALUE_RM_UNUSED_SECONDARY_HOST;
+ rmIrqRelease.src_id = src_id;
+ rmIrqRelease.src_index = src_index; /* This is the event coming out of the peripheral */
+
+ /* Set the destination interrupt */
+ rmIrqRelease.valid_params |= TISCI_MSG_VALUE_RM_DST_ID_VALID;
+ rmIrqRelease.valid_params |= TISCI_MSG_VALUE_RM_DST_HOST_IRQ_VALID;
+
+ /* Set the destination based on the core */
+ rmIrqRelease.dst_id = dst_id;
+ rmIrqRelease.dst_host_irq = dst_host_irq;
+ }
+
+ /* Config event */
+ if(setIntrPath) {
+ if(GPIO_PinBankUsageCount[portNum][bankNum] == 0U) {
+ retVal = Sciclient_rmIrqSet(
+ (const struct tisci_msg_rm_irq_set_req *)&rmIrqReq,
+ &rmIrqResp,
+ SCICLIENT_SERVICE_WAIT_FOREVER);
+
+ if(retVal==CSL_PASS) {
+ /* Increase the bank usage count for this port */
+ GPIO_PinBankUsageCount[portNum][bankNum]++;
+ }
+ } else {
+ /* The interrupt path is already allocated, no need to re-allocate it */
+ retVal = CSL_PASS;
+ }
+ } else {
+ retVal = Sciclient_rmIrqRelease(
+ (const struct tisci_msg_rm_irq_release_req *)&rmIrqRelease,
+ SCICLIENT_SERVICE_WAIT_FOREVER);
+
+ if(retVal==CSL_PASS) {
+ /* Increase the bank usage count for this port */
+ GPIO_PinBankUsageCount[portNum][bankNum]--;
+ }
+ }
+
+#if defined (BUILD_C7X_1)
+ int32_t ret;
+ CSL_ClecEventConfig cfgClec;
+ CSL_CLEC_EVTRegs *clecBaseAddr = (CSL_CLEC_EVTRegs *)CSL_COMPUTE_CLUSTER0_CLEC_REGS_BASE;
+
+ /* Configure CLEC for GPIO */
+ cfgClec.secureClaimEnable = FALSE;
+ cfgClec.evtSendEnable = TRUE;
+ cfgClec.rtMap = CSL_CLEC_RTMAP_CPU_ALL;
+ cfgClec.extEvtNum = 0;
+ cfgClec.c7xEvtNum = intCfg[pinNum].intNum;
+ ret = CSL_clecConfigEvent(clecBaseAddr, intCfg[pinNum].eventId, &cfgClec);
+ if (ret == CSL_EFAIL)
+ {
+ retVal = CSL_EFAIL;
+ }
+#endif
+
+ return(retVal);
+}
diff --git a/packages/ti/drv/gpio/soc/k2e/GPIO_soc.c b/packages/ti/drv/gpio/soc/k2e/GPIO_soc.c
--- /dev/null
@@ -0,0 +1,652 @@
+/**
+ * \file k2e/GPIO_soc.c
+ *
+ * \brief K2E SOC specific GPIO hardware attributes.
+ *
+ * This file contains the GPIO hardware attributes like base address and
+ * interrupt ids.
+ */
+
+/*
+ * Copyright (C) 2015 - 2016 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include <ti/csl/csl_utils.h>
+#include <ti/csl/soc.h>
+#include <ti/csl/csl_types.h>
+#include <ti/csl/csl_device_interrupt.h>
+#include <ti/drv/gpio/GPIO.h>
+#include <ti/drv/gpio/soc/GPIO_soc.h>
+
+/** \brief Number of gpio pins for each port */
+#define GPIO_NUM_PINS_PER_PORT (32U)
+
+/** \brief Number of gpio ports present in the soc */
+#define GPIO_NUM_PORTS (CSL_GPIO_PER_CNT)
+
+/* GPIO Pin interrupt configurations */
+GPIO_IntCfg GPIO_intCfgs[GPIO_NUM_PINS_PER_PORT] =
+{
+ /* GPIO port 0 pin 0 */
+ {
+#ifdef _TMS320C6X
+ OSAL_REGINT_INTVEC_EVENT_COMBINER, /* DSP interrupt vector */
+ 34, /* default DSP INTC GPIO Event ID, can be set in GPIO_socSetInitCfg() API */
+ 0, /* Chip Interrupt Controller number 0 */
+ CSL_CIC0_GPIO_INT0, /* CIC0 GPIO Event ID */
+ 18 /* default CIC0 Host Interrupt, map to CIC_0_OUT18 event */
+#else
+ CSL_ARM_GIC_GPIO_INT0 + 32, /* GPIO pin interrupt event for ARM GIC */
+ 0,
+ INVALID_INTC_MUX_NUM, /* CIC not used for GPIO pin 0 */
+ 0,
+ 0
+#endif
+ },
+ /* GPIO port 0 pin 1 */
+ {
+#ifdef _TMS320C6X
+ OSAL_REGINT_INTVEC_EVENT_COMBINER,
+ 34,
+ 0,
+ CSL_CIC0_GPIO_INT1,
+ 18
+#else
+ CSL_ARM_GIC_GPIO_INT1 + 32,
+ 0,
+ INVALID_INTC_MUX_NUM,
+ 0,
+ 0
+#endif
+ },
+ /* GPIO port 0 pin 2 */
+ {
+#ifdef _TMS320C6X
+ OSAL_REGINT_INTVEC_EVENT_COMBINER,
+ 34,
+ 0,
+ CSL_CIC0_GPIO_INT2,
+ 18
+#else
+ CSL_ARM_GIC_GPIO_INT2 + 32,
+ 0,
+ INVALID_INTC_MUX_NUM,
+ 0,
+ 0
+#endif
+ },
+ /* GPIO port 0 pin 3 */
+ {
+#ifdef _TMS320C6X
+ OSAL_REGINT_INTVEC_EVENT_COMBINER,
+ 34,
+ 0,
+ CSL_CIC0_GPIO_INT3,
+ 18
+#else
+ CSL_ARM_GIC_GPIO_INT3 + 32,
+ 0,
+ INVALID_INTC_MUX_NUM,
+ 0,
+ 0
+#endif
+ },
+ /* GPIO port 0 pin 4 */
+ {
+#ifdef _TMS320C6X
+ OSAL_REGINT_INTVEC_EVENT_COMBINER,
+ 34,
+ 0,
+ CSL_CIC0_GPIO_INT4,
+ 18
+#else
+ CSL_ARM_GIC_GPIO_INT4 + 32,
+ 0,
+ INVALID_INTC_MUX_NUM,
+ 0,
+ 0
+#endif
+ },
+ /* GPIO port 0 pin 5 */
+ {
+#ifdef _TMS320C6X
+ OSAL_REGINT_INTVEC_EVENT_COMBINER,
+ 34,
+ 0,
+ CSL_CIC0_GPIO_INT5,
+ 18
+#else
+ CSL_ARM_GIC_GPIO_INT5 + 32,
+ 0,
+ INVALID_INTC_MUX_NUM,
+ 0,
+ 0
+#endif
+ },
+ /* GPIO port 0 pin 6 */
+ {
+#ifdef _TMS320C6X
+ OSAL_REGINT_INTVEC_EVENT_COMBINER,
+ 34,
+ 0,
+ CSL_CIC0_GPIO_INT6,
+ 18
+#else
+ CSL_ARM_GIC_GPIO_INT6 + 32,
+ 0,
+ INVALID_INTC_MUX_NUM,
+ 0,
+ 0
+#endif
+ },
+ /* GPIO port 0 pin 7 */
+ {
+#ifdef _TMS320C6X
+ OSAL_REGINT_INTVEC_EVENT_COMBINER,
+ 34,
+ 0,
+ CSL_CIC0_GPIO_INT7,
+ 18
+#else
+ CSL_ARM_GIC_GPIO_INT7 + 32,
+ 0,
+ INVALID_INTC_MUX_NUM,
+ 0,
+ 0
+#endif
+ },
+ /* GPIO port 0 pin 8 */
+ {
+#ifdef _TMS320C6X
+ OSAL_REGINT_INTVEC_EVENT_COMBINER,
+ CSL_C66X_COREPAC_GPIO_INT8,
+#else
+ CSL_ARM_GIC_GPIO_INT8 + 32,
+ 0,
+#endif
+ INVALID_INTC_MUX_NUM,
+ 0,
+ 0
+ },
+ /* GPIO port 0 pin 9 */
+ {
+#ifdef _TMS320C6X
+ OSAL_REGINT_INTVEC_EVENT_COMBINER,
+ CSL_C66X_COREPAC_GPIO_INT9,
+#else
+ CSL_ARM_GIC_GPIO_INT9 + 32,
+ 0,
+#endif
+ INVALID_INTC_MUX_NUM,
+ 0,
+ 0
+ },
+ /* GPIO port 0 pin 10 */
+ {
+#ifdef _TMS320C6X
+ OSAL_REGINT_INTVEC_EVENT_COMBINER,
+ CSL_C66X_COREPAC_GPIO_INT10,
+#else
+ CSL_ARM_GIC_GPIO_INT10 + 32,
+ 0,
+#endif
+ INVALID_INTC_MUX_NUM,
+ 0,
+ 0
+ },
+ /* GPIO port 0 pin 11 */
+ {
+#ifdef _TMS320C6X
+ OSAL_REGINT_INTVEC_EVENT_COMBINER,
+ CSL_C66X_COREPAC_GPIO_INT11,
+#else
+ CSL_ARM_GIC_GPIO_INT11 + 32,
+ 0,
+#endif
+ INVALID_INTC_MUX_NUM,
+ 0,
+ 0
+ },
+ /* GPIO port 0 pin 12 */
+ {
+#ifdef _TMS320C6X
+ OSAL_REGINT_INTVEC_EVENT_COMBINER,
+ CSL_C66X_COREPAC_GPIO_INT12,
+#else
+ CSL_ARM_GIC_GPIO_INT12 + 32,
+ 0,
+#endif
+ INVALID_INTC_MUX_NUM,
+ 0,
+ 0
+ },
+ /* GPIO port 0 pin 13 */
+ {
+#ifdef _TMS320C6X
+ OSAL_REGINT_INTVEC_EVENT_COMBINER,
+ CSL_C66X_COREPAC_GPIO_INT13,
+#else
+ CSL_ARM_GIC_GPIO_INT13 + 32,
+ 0,
+#endif
+ INVALID_INTC_MUX_NUM,
+ 0,
+ 0
+ },
+ /* GPIO port 0 pin 14 */
+ {
+#ifdef _TMS320C6X
+ OSAL_REGINT_INTVEC_EVENT_COMBINER,
+ CSL_C66X_COREPAC_GPIO_INT14,
+#else
+ CSL_ARM_GIC_GPIO_INT14 + 32,
+ 0,
+#endif
+ INVALID_INTC_MUX_NUM,
+ 0,
+ 0
+ },
+ /* GPIO port 0 pin 15 */
+ {
+#ifdef _TMS320C6X
+ OSAL_REGINT_INTVEC_EVENT_COMBINER,
+ CSL_C66X_COREPAC_GPIO_INT15,
+#else
+ CSL_ARM_GIC_GPIO_INT15 + 32,
+ 0,
+#endif
+ INVALID_INTC_MUX_NUM,
+ 0,
+ 0
+ },
+ /* GPIO port 0 pin 16 */
+ {
+#ifdef _TMS320C6X
+ OSAL_REGINT_INTVEC_EVENT_COMBINER,
+ 35,
+ 0,
+ CSL_CIC0_GPIO_INT16,
+ 19
+#else
+ CSL_ARM_GIC_GPIO_INT16 + 32,
+ 0,
+ INVALID_INTC_MUX_NUM,
+ 0,
+ 0
+#endif
+ },
+ /* GPIO port 0 pin 17 */
+ {
+#ifdef _TMS320C6X
+ OSAL_REGINT_INTVEC_EVENT_COMBINER,
+ 35,
+ 0,
+ CSL_CIC0_GPIO_INT17,
+ 19
+#else
+ CSL_ARM_GIC_GPIO_INT17 + 32,
+ 0,
+ INVALID_INTC_MUX_NUM,
+ 0,
+ 0
+#endif
+ },
+ /* GPIO port 0 pin 18 */
+ {
+#ifdef _TMS320C6X
+ OSAL_REGINT_INTVEC_EVENT_COMBINER,
+ 35,
+ 0,
+ CSL_CIC0_GPIO_INT18,
+ 19
+#else
+ CSL_ARM_GIC_GPIO_INT18 + 32,
+ 0,
+ INVALID_INTC_MUX_NUM,
+ 0,
+ 0
+#endif
+ },
+ /* GPIO port 0 pin 19 */
+ {
+#ifdef _TMS320C6X
+ OSAL_REGINT_INTVEC_EVENT_COMBINER,
+ 35,
+ 0,
+ CSL_CIC0_GPIO_INT19,
+ 19
+#else
+ CSL_ARM_GIC_GPIO_INT19 + 32,
+ 0,
+ INVALID_INTC_MUX_NUM,
+ 0,
+ 0
+#endif
+ },
+ /* GPIO port 0 pin 20 */
+ {
+#ifdef _TMS320C6X
+ OSAL_REGINT_INTVEC_EVENT_COMBINER,
+ 35,
+ 0,
+ CSL_CIC0_GPIO_INT20,
+ 19
+#else
+ CSL_ARM_GIC_GPIO_INT20 + 32,
+ 0,
+ INVALID_INTC_MUX_NUM,
+ 0,
+ 0
+#endif
+ },
+ /* GPIO port 0 pin 21 */
+ {
+#ifdef _TMS320C6X
+ OSAL_REGINT_INTVEC_EVENT_COMBINER,
+ 35,
+ 0,
+ CSL_CIC0_GPIO_INT21,
+ 19
+#else
+ CSL_ARM_GIC_GPIO_INT21 + 32,
+ 0,
+ INVALID_INTC_MUX_NUM,
+ 0,
+ 0
+#endif
+ },
+ /* GPIO port 0 pin 22 */
+ {
+#ifdef _TMS320C6X
+ OSAL_REGINT_INTVEC_EVENT_COMBINER,
+ 35,
+ 0,
+ CSL_CIC0_GPIO_INT22,
+ 19
+#else
+ CSL_ARM_GIC_GPIO_INT22 + 32,
+ 0,
+ INVALID_INTC_MUX_NUM,
+ 0,
+ 0
+#endif
+ },
+ /* GPIO port 0 pin 23 */
+ {
+#ifdef _TMS320C6X
+ OSAL_REGINT_INTVEC_EVENT_COMBINER,
+ 35,
+ 0,
+ CSL_CIC0_GPIO_INT23,
+ 19
+#else
+ CSL_ARM_GIC_GPIO_INT23 + 32,
+ 0,
+ INVALID_INTC_MUX_NUM,
+ 0,
+ 0
+#endif
+ },
+ /* GPIO port 0 pin 24 */
+ {
+#ifdef _TMS320C6X
+ OSAL_REGINT_INTVEC_EVENT_COMBINER,
+ 35,
+ 0,
+ CSL_CIC0_GPIO_INT24,
+ 19
+#else
+ CSL_ARM_GIC_GPIO_INT24 + 32,
+ 0,
+ INVALID_INTC_MUX_NUM,
+ 0,
+ 0
+#endif
+ },
+ /* GPIO port 0 pin 25 */
+ {
+#ifdef _TMS320C6X
+ OSAL_REGINT_INTVEC_EVENT_COMBINER,
+ 35,
+ 0,
+ CSL_CIC0_GPIO_INT25,
+ 19
+#else
+ CSL_ARM_GIC_GPIO_INT25 + 32,
+ 0,
+ INVALID_INTC_MUX_NUM,
+ 0,
+ 0
+#endif
+ },
+ /* GPIO port 0 pin 26 */
+ {
+#ifdef _TMS320C6X
+ OSAL_REGINT_INTVEC_EVENT_COMBINER,
+ 35,
+ 0,
+ CSL_CIC0_GPIO_INT26,
+ 19
+#else
+ CSL_ARM_GIC_GPIO_INT26 + 32,
+ 0,
+ INVALID_INTC_MUX_NUM,
+ 0,
+ 0
+#endif
+ },
+ /* GPIO port 0 pin 27 */
+ {
+#ifdef _TMS320C6X
+ OSAL_REGINT_INTVEC_EVENT_COMBINER,
+ 35,
+ 0,
+ CSL_CIC0_GPIO_INT27,
+ 19
+#else
+ CSL_ARM_GIC_GPIO_INT27 + 32,
+ 0,
+ INVALID_INTC_MUX_NUM,
+ 0,
+ 0
+#endif
+ },
+ /* GPIO port 0 pin 28 */
+ {
+#ifdef _TMS320C6X
+ OSAL_REGINT_INTVEC_EVENT_COMBINER,
+ 35,
+ 0,
+ CSL_CIC0_GPIO_INT28,
+ 19
+#else
+ CSL_ARM_GIC_GPIO_INT28 + 32,
+ 0,
+ INVALID_INTC_MUX_NUM,
+ 0,
+ 0
+#endif
+ },
+ /* GPIO port 0 pin 29 */
+ {
+#ifdef _TMS320C6X
+ OSAL_REGINT_INTVEC_EVENT_COMBINER,
+ 35,
+ 0,
+ CSL_CIC0_GPIO_INT29,
+ 19
+#else
+ CSL_ARM_GIC_GPIO_INT29 + 32,
+ 0,
+ INVALID_INTC_MUX_NUM,
+ 0,
+ 0
+#endif
+ },
+ /* GPIO port 0 pin 30 */
+ {
+#ifdef _TMS320C6X
+ OSAL_REGINT_INTVEC_EVENT_COMBINER,
+ 35,
+ 0,
+ CSL_CIC0_GPIO_INT30,
+ 19
+#else
+ CSL_ARM_GIC_GPIO_INT30 + 32,
+ 0,
+ INVALID_INTC_MUX_NUM,
+ 0,
+ 0
+#endif
+ },
+ /* GPIO port 0 pin 31 */
+ {
+#ifdef _TMS320C6X
+ OSAL_REGINT_INTVEC_EVENT_COMBINER,
+ 35,
+ 0,
+ CSL_CIC0_GPIO_INT31,
+ 19
+#else
+ CSL_ARM_GIC_GPIO_INT31 + 32,
+ 0,
+ INVALID_INTC_MUX_NUM,
+ 0,
+ 0
+#endif
+ }
+};
+
+/* GPIO Driver hardware attributes */
+GPIO_v0_hwAttrsList GPIO_v0_hwAttrs =
+{
+ {
+ CSL_GPIO_CFG_REGS,
+ &GPIO_intCfgs[0],
+ NULL
+ },
+
+ {
+ 0,
+ NULL,
+ NULL
+ }
+};
+
+/* GPIO configuration structure */
+CSL_PUBLIC_CONST GPIOConfigList GPIO_config =
+{
+ {
+ &GPIO_FxnTable_v0,
+ NULL,
+ &GPIO_v0_hwAttrs[0]
+ },
+
+ {
+ NULL,
+ NULL,
+ NULL
+ },
+ /* "pad to full predefined length of array" */
+ {
+ NULL,
+ NULL,
+ NULL
+ }
+};
+
+/**
+ * \brief This API gets the SoC level of GPIO intial configuration
+ *
+ * \param index GPIO instance index.
+ * \param cfg Pointer to GPIO SOC initial config.
+ *
+ * \return 0 success: -1: error
+ *
+ */
+int32_t GPIO_socGetInitCfg(uint32_t index, GPIO_v0_HwAttrs *cfg)
+{
+ int32_t ret = 0;
+
+ if (index < GPIO_NUM_PORTS)
+ {
+ *cfg = GPIO_v0_hwAttrs[index];
+ }
+ else
+ {
+ ret = -1;
+ }
+
+ return ret;
+}
+
+/**
+ * \brief This API sets the SoC level of GPIO intial configuration
+ *
+ * \param index GPIO instance index.
+ * \param cfg Pointer to GPIO SOC initial config.
+ *
+ * \return 0 success: -1: error
+ *
+ */
+int32_t GPIO_socSetInitCfg(uint32_t index, const GPIO_v0_HwAttrs *cfg)
+{
+ int32_t ret = 0;
+
+ if (index < GPIO_NUM_PORTS)
+ {
+ GPIO_v0_hwAttrs[index] = *cfg;
+ }
+ else
+ {
+ ret = -1;
+ }
+
+ return ret;
+}
+
+/**
+ * \brief This API gets the number of GPIO pins per port
+ * and GPIO number of ports
+ *
+ * \param numPins pointer to numPins variable.
+ * \param numPorts pointer to numPorts variable.
+ *
+ * \return none
+ *
+ */
+void GPIO_socGetNumPinsPorts(uint32_t *numPins, uint32_t *numPorts)
+{
+ *numPins = GPIO_NUM_PINS_PER_PORT;
+ *numPorts = GPIO_NUM_PORTS;
+}
+
diff --git a/packages/ti/drv/gpio/soc/k2g/GPIO_soc.c b/packages/ti/drv/gpio/soc/k2g/GPIO_soc.c
--- /dev/null
@@ -0,0 +1,251 @@
+/**
+ * \file k2g/GPIO_soc.c
+ *
+ * \brief K2G SOC specific GPIO hardware attributes.
+ *
+ * This file contains the GPIO hardware attributes like base address and
+ * interrupt ids.
+ */
+
+/*
+ * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include <ti/csl/csl_utils.h>
+#include <ti/csl/soc.h>
+#include <ti/csl/csl_types.h>
+#include <ti/csl/csl_device_interrupt.h>
+#include <ti/csl/cslr_bootcfg.h>
+#include <ti/csl/hw_types.h>
+#include <ti/drv/gpio/GPIO.h>
+#include <ti/drv/gpio/soc/GPIO_soc.h>
+
+/** \brief Number of gpio pins for each port */
+#define GPIO_NUM_PINS_PER_PORT (144U)
+
+/** \brief Number of gpio ports present in the soc */
+#define GPIO_NUM_PORTS (CSL_GPIO_CNT)
+
+GPIO_IntCfg GPIO_defaultIntCfg[GPIO_NUM_PORTS] =
+{
+ /* GPIO port 0 pins */
+ {
+#ifdef _TMS320C6X
+ OSAL_REGINT_INTVEC_EVENT_COMBINER, /* default DSP Interrupt vector number, can be set in GPIO_socSetInitCfg() API */
+ CSL_C66X_COREPAC_GPIOMUX_INT16, /* GPIO pin int mapped to GPIOMUX event sel 16 */
+#else
+ CSL_ARM_GIC_GPIOMUX_INT0 + 32, /* GPIO pin int mapped to GPIOMUX event sel 0 */
+ 0,
+#endif
+ INVALID_INTC_MUX_NUM, /* CIC not used for GPIO pin 0 */
+ 0,
+ 0
+ },
+ /* GPIO port 1 pins */
+ {
+#ifdef _TMS320C6X
+ OSAL_REGINT_INTVEC_EVENT_COMBINER,
+ CSL_C66X_COREPAC_GPIOMUX_INT17,
+#else
+ CSL_ARM_GIC_GPIOMUX_INT1 + 32,
+ 0,
+#endif
+ INVALID_INTC_MUX_NUM,
+ 0,
+ 0
+ }
+};
+
+/* GPIO Pin interrupt configurations */
+GPIO_IntCfg GPIO_intCfgs[GPIO_NUM_PORTS][GPIO_NUM_PINS_PER_PORT];
+
+/* GPIO Driver hardware attributes */
+GPIO_v0_hwAttrsList GPIO_v0_hwAttrs =
+{
+ {
+ CSL_GPIO_0_REGS,
+ &GPIO_intCfgs[0][0],
+ NULL
+ },
+
+ {
+ CSL_GPIO_1_REGS,
+ &GPIO_intCfgs[1][0],
+ NULL
+ }
+};
+
+/* GPIO configuration structure */
+CSL_PUBLIC_CONST GPIOConfigList GPIO_config =
+{
+ {
+ &GPIO_FxnTable_v0,
+ NULL,
+ &GPIO_v0_hwAttrs[0]
+ },
+
+ {
+ &GPIO_FxnTable_v0,
+ NULL,
+ &GPIO_v0_hwAttrs[1]
+ },
+
+ {
+ NULL,
+ NULL,
+ NULL
+ }
+};
+
+/**
+ * \brief This API gets the SoC level of GPIO intial configuration
+ *
+ * \param index GPIO instance index.
+ * \param cfg Pointer to GPIO SOC initial config.
+ *
+ * \return 0 success: -1: error
+ *
+ */
+int32_t GPIO_socGetInitCfg(uint32_t index, GPIO_v0_HwAttrs *cfg)
+{
+ int32_t ret = 0;
+
+ if (index < GPIO_NUM_PORTS)
+ {
+ *cfg = GPIO_v0_hwAttrs[index];
+ }
+ else
+ {
+ ret = -1;
+ }
+
+ return ret;
+}
+
+/**
+ * \brief This API sets the SoC level of GPIO intial configuration
+ *
+ * \param index GPIO instance index.
+ * \param cfg Pointer to GPIO SOC initial config.
+ *
+ * \return 0 success: -1: error
+ *
+ */
+int32_t GPIO_socSetInitCfg(uint32_t index, const GPIO_v0_HwAttrs *cfg)
+{
+ int32_t ret = 0;
+
+ if (index < GPIO_NUM_PORTS)
+ {
+ GPIO_v0_hwAttrs[index] = *cfg;
+ }
+ else
+ {
+ ret = -1;
+ }
+
+ return ret;
+}
+
+/**
+ * \brief This API gets the number of GPIO pins per port
+ * and GPIO number of ports
+ *
+ * \param numPins pointer to numPins variable.
+ * \param numPorts pointer to numPorts variable.
+ *
+ * \return none
+ *
+ */
+void GPIO_socGetNumPinsPorts(uint32_t *numPins, uint32_t *numPorts)
+{
+ *numPins = GPIO_NUM_PINS_PER_PORT;
+ *numPorts = GPIO_NUM_PORTS;
+}
+
+/**
+ * \brief This API sets the GPIO MUX for GPIO interrupts
+ *
+ * \param index GPIO instance index.
+ * \param pinNum Pin number of the GPIO instance.
+ * \param cfg pointer to GPIO interrupt configuration data
+ * if NULL use the default configurations.
+ * \param muxEvtSel Event slect number for ARM GPIOMUX interrupt.
+ *
+ * \return 0 success: -1: error
+ *
+ */
+int32_t GPIO_socSetIntMux(uint32_t index, uint32_t pinNum, const GPIO_IntCfg *cfg, uint32_t muxEvtSel)
+{
+ uint32_t intNum;
+ uint32_t addr;
+ GPIO_IntCfg *intCfg;
+ int32_t retVal = 0;
+
+ /* Get the GPIO pin interrupt number */
+ if (index == 0)
+ {
+ intNum = pinNum;
+ }
+ else if (index == 1U)
+ {
+ intNum = pinNum + GPIO_NUM_PINS_PER_PORT;
+ if (intNum > 255U)
+ {
+ retVal = -1;
+ }
+ }
+ else
+ {
+ retVal = -1;
+ }
+
+ if(retVal == 0)
+ {
+ /* Setup GPIO pin interrupt configurations */
+ intCfg = GPIO_v0_hwAttrs[index].intCfg + pinNum;
+ if (cfg == NULL)
+ {
+ *intCfg = GPIO_defaultIntCfg[index];
+ }
+ else
+ {
+ *intCfg = *cfg;
+ }
+
+ /* Setup GPIO interrupt event mux Control */
+ addr = CSL_BOOT_CFG_REGS + CSL_BOOTCFG_EVENT_MUXCTL0 + muxEvtSel;
+ HW_WR_REG8(addr, intNum);
+ }
+
+ return (retVal);
+}
diff --git a/packages/ti/drv/gpio/soc/k2h/GPIO_soc.c b/packages/ti/drv/gpio/soc/k2h/GPIO_soc.c
--- /dev/null
@@ -0,0 +1,626 @@
+/**
+ * \file k2h/GPIO_soc.c
+ *
+ * \brief K2H SOC specific GPIO hardware attributes.
+ *
+ * This file contains the GPIO hardware attributes like base address and
+ * interrupt ids.
+ */
+
+/*
+ * Copyright (C) 2015 - 2016 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include <ti/csl/csl_utils.h>
+#include <ti/csl/soc.h>
+#include <ti/csl/csl_types.h>
+#include <ti/csl/csl_device_interrupt.h>
+#include <ti/drv/gpio/GPIO.h>
+#include <ti/drv/gpio/soc/GPIO_soc.h>
+
+/** \brief Number of gpio pins for each port */
+#define GPIO_NUM_PINS_PER_PORT (32U)
+
+/** \brief Number of gpio ports present in the soc */
+#define GPIO_NUM_PORTS (CSL_GPIO_PER_CNT)
+
+/* GPIO Pin interrupt configurations */
+GPIO_IntCfg GPIO_intCfgs[GPIO_NUM_PINS_PER_PORT] =
+{
+ /* GPIO port 0 pin 0 */
+ {
+#ifdef _TMS320C6X
+ OSAL_REGINT_INTVEC_EVENT_COMBINER, /* default DSP Interrupt vector number, can be set in GPIO_socSetInitCfg() API */
+ CSL_C66X_COREPAC_GPIO_INTN, /* DSP corePac GPIO pin 0 interrupt event for Core 0 */
+#else
+ CSL_ARM_GIC_GPIO_INT0 + 32,
+ 0,
+#endif
+ INVALID_INTC_MUX_NUM, /* CIC not used for GPIO pin 0 */
+ },
+ /* GPIO port 0 pin 1 */
+ {
+#ifdef _TMS320C6X
+ OSAL_REGINT_INTVEC_EVENT_COMBINER,
+ CSL_C66X_COREPAC_GPIO_INTN, /* DSP corePac GPIO pin 1 interrupt event for Core 1 */
+#else
+ CSL_ARM_GIC_GPIO_INT1 + 32,
+ 0,
+#endif
+ INVALID_INTC_MUX_NUM,
+ 0,
+ 0
+ },
+ /* GPIO port 0 pin 2 */
+ {
+#ifdef _TMS320C6X
+ OSAL_REGINT_INTVEC_EVENT_COMBINER,
+ CSL_C66X_COREPAC_GPIO_INTN, /* DSP corePac GPIO pin 2 interrupt event for Core 2 */
+#else
+ CSL_ARM_GIC_GPIO_INT2 + 32,
+ 0,
+#endif
+ INVALID_INTC_MUX_NUM,
+ 0,
+ 0
+ },
+ /* GPIO port 0 pin 3 */
+ {
+#ifdef _TMS320C6X
+ OSAL_REGINT_INTVEC_EVENT_COMBINER,
+ CSL_C66X_COREPAC_GPIO_INTN, /* DSP corePac GPIO pin 3 interrupt event for Core 3 */
+#else
+ CSL_ARM_GIC_GPIO_INT3 + 32,
+ 0,
+#endif
+ INVALID_INTC_MUX_NUM,
+ 0,
+ 0
+ },
+ /* GPIO port 0 pin 4 */
+ {
+#ifdef _TMS320C6X
+ OSAL_REGINT_INTVEC_EVENT_COMBINER,
+ CSL_C66X_COREPAC_GPIO_INTN, /* DSP corePac GPIO pin 4 interrupt event for Core 4 */
+#else
+ CSL_ARM_GIC_GPIO_INT4 + 32,
+ 0,
+#endif
+ INVALID_INTC_MUX_NUM,
+ 0,
+ 0
+ },
+ /* GPIO port 0 pin 5 */
+ {
+#ifdef _TMS320C6X
+ OSAL_REGINT_INTVEC_EVENT_COMBINER,
+ CSL_C66X_COREPAC_GPIO_INTN, /* DSP corePac GPIO pin 5 interrupt event for Core 5 */
+#else
+ CSL_ARM_GIC_GPIO_INT5 + 32,
+ 0,
+#endif
+ INVALID_INTC_MUX_NUM,
+ 0,
+ 0
+ },
+ /* GPIO port 0 pin 6 */
+ {
+#ifdef _TMS320C6X
+ OSAL_REGINT_INTVEC_EVENT_COMBINER,
+ CSL_C66X_COREPAC_GPIO_INTN, /* DSP corePac GPIO pin 6 interrupt event for Core 6 */
+#else
+ CSL_ARM_GIC_GPIO_INT6 + 32,
+ 0,
+#endif
+ INVALID_INTC_MUX_NUM,
+ 0,
+ 0
+ },
+ /* GPIO port 0 pin 7 */
+ {
+#ifdef _TMS320C6X
+ OSAL_REGINT_INTVEC_EVENT_COMBINER,
+ CSL_C66X