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raw | patch | inline | side by side (parent: baadd73)
raw | patch | inline | side by side (parent: baadd73)
author | Badri S <badri@ti.com> | |
Fri, 16 Oct 2020 11:02:02 +0000 (16:32 +0530) | ||
committer | Sivaraj R <sivaraj@ti.com> | |
Sat, 31 Oct 2020 04:09:47 +0000 (23:09 -0500) |
misc fixes for issues found when enabling SBL QSPI mode
on TPR12 EVM
Signed-off-by: Badri S <badri@ti.com>
on TPR12 EVM
Signed-off-by: Badri S <badri@ti.com>
index b2b49ed9e3f8596bfb7bca8f2cb3bd1f479c9d99..94ee5b9fcd248d9624038016e038f92c403ec73a 100644 (file)
* code should setup the MPU to allow L2 execution permissions
***********************************************************************************/
#define SBL_INIT_CODE_SIZE 640
+#define SBL_TEST_CCS_LOAD 1
/*----------------------------------------------------------------------------*/
/* Memory Map */
{
*(.rstvectors) /* IVT is put at the beginning of the section */
. = align(8);
- *(.bootCode)
- . = align(8);
- }load=L2_RESVD, run=INIT_CODE
+ *(.bootCode)
+ . = align(8);
+#if (SBL_TEST_CCS_LOAD == 1)
+ } > INIT_CODE
+#else
+ } load=L2_RESVD, run=INIT_CODE
+#endif
+
+ .bootCode : {} palign(8) > L2_RAM_SBL
+ .startupCode : {} palign(8) > L2_RAM_SBL
+ .startupData : {} palign(8) > L2_RAM_SBL
.sblScratch : {} palign(8) > SBL_SCRATCH, type = NOINIT
- .startupCode : {} palign(8) > L2_RAM_SBL
- .startupData : {} palign(8) > L2_RAM_SBL
.sbl_profile_info : {} palign(8) > L2_RAM_SBL
.text : {} palign(8) > L2_RAM_SBL
.const : {} palign(8) > L2_RAM_SBL
index 1a3c4882ce5d7854b671322ff0a021daa247f517..95e5fcd85125e7d6018b8b4bb57a805e49356c68 100644 (file)
* @details
* Mapping Array between Clock mode and Clock Mode Value for RTI and WDG
*/
-static uint16_t gRtiClkSrcValMap[] =
+static const uint16_t gRtiClkSrcValMap[] =
{
[Rcm_PeripheralClockSource_XTAL_CLK] = 0x000U, /* XTAL_CLK */
[Rcm_PeripheralClockSource_SYS_CLK] = 0x222U, /* SYS_CLK */
* @details
* Mapping Array between Clock mode and Clock Mode Value for SPI
*/
-static uint16_t gSpiClkSrcValMap[] =
+static const uint16_t gSpiClkSrcValMap[] =
{
[Rcm_PeripheralClockSource_XTAL_CLK] = 0x111U, /* XTAL_CLK */
[Rcm_PeripheralClockSource_SYS_CLK] = 0x222U, /* SYS_CLK */
[Rcm_PeripheralClockSource_DPLL_PER_HSDIV0_CLKOUT3] = 0x888U, /* Set unsupported clock source to 0x888 which indicates invalid value */
};
-static uint16_t gI2CClkSrcValMap[] =
+static const uint16_t gI2CClkSrcValMap[] =
{
[Rcm_PeripheralClockSource_XTAL_CLK] = 0x111U,
[Rcm_PeripheralClockSource_SYS_CLK] = 0x222U,
* @details
* Mapping Array between Clock mode and Clock Mode Value for QSPI
*/
-static uint16_t gQspiClkSrcValMap[] =
+static const uint16_t gQspiClkSrcValMap[] =
{
[Rcm_PeripheralClockSource_XTAL_CLK] = 0x000U, /* XTAL_CLK */
[Rcm_PeripheralClockSource_SYS_CLK] = 0x222U, /* SYS_CLK */
* @details
* Mapping Array between Clock mode and Clock Mode Value for SCI
*/
-static uint16_t gSciClkSrcValMap[] =
+static const uint16_t gSciClkSrcValMap[] =
{
[Rcm_PeripheralClockSource_XTAL_CLK] = 0x111U, /* XTAL_CLK */
[Rcm_PeripheralClockSource_SYS_CLK] = 0x222U, /* SYS_CLK */
};
-static uint16_t gMcanClkSrcValMap[] =
+static const uint16_t gMcanClkSrcValMap[] =
{
[Rcm_PeripheralClockSource_XTAL_CLK] = 0x888U, /* XTAL clock source not supported for MCANA */
[Rcm_PeripheralClockSource_SYS_CLK] = 0x222U,
};
-static uint16_t gCsiRxClkSrcValMap[] =
+static const uint16_t gCsiRxClkSrcValMap[] =
{
[Rcm_PeripheralClockSource_XTAL_CLK] = 0x666U, /* XTAL clock source not supported for MCANA */
[Rcm_PeripheralClockSource_SYS_CLK] = 0x888U,
[Rcm_PeripheralClockSource_DPLL_PER_HSDIV0_CLKOUT3] = 0x888U, /* Set unsupported clock source to 0x888 which indicates invalid value */
};
-static uint16_t gDssRtiClkSrcValMap[] =
+static const uint16_t gDssRtiClkSrcValMap[] =
{
[Rcm_PeripheralClockSource_XTAL_CLK] = 0x111U,
[Rcm_PeripheralClockSource_SYS_CLK] = 0x222U,
[Rcm_PeripheralClockSource_DPLL_PER_HSDIV0_CLKOUT3] = 0x888U, /* Set unsupported clock source to 0x888 which indicates invalid value */
};
-static uint16_t gDssSciClkSrcValMap[] =
+static const uint16_t gDssSciClkSrcValMap[] =
{
[Rcm_PeripheralClockSource_XTAL_CLK] = 0x111U,
[Rcm_PeripheralClockSource_SYS_CLK] = 0x222U,
[Rcm_PeripheralClockSource_DPLL_PER_HSDIV0_CLKOUT3] = 0x888U, /* Set unsupported clock source to 0x888 which indicates invalid value */
};
-static uint16_t gRcssSciClkSrcValMap[] =
+static const uint16_t gRcssSciClkSrcValMap[] =
{
[Rcm_PeripheralClockSource_XTAL_CLK] = 0x111U,
[Rcm_PeripheralClockSource_SYS_CLK] = 0x222U,
[Rcm_PeripheralClockSource_DPLL_PER_HSDIV0_CLKOUT3] = 0x888U, /* Set unsupported clock source to 0x888 which indicates invalid value */
};
-static uint16_t gRcssSpiClkSrcValMap[] =
+static const uint16_t gRcssSpiClkSrcValMap[] =
{
[Rcm_PeripheralClockSource_XTAL_CLK] = 0x111U,
[Rcm_PeripheralClockSource_SYS_CLK] = 0x222U,
[Rcm_PeripheralClockSource_DPLL_PER_HSDIV0_CLKOUT3] = 0x888U, /* Set unsupported clock source to 0x888 which indicates invalid value */
};
-static uint16_t gRcssI2CClkSrcValMap[] =
+static const uint16_t gRcssI2CClkSrcValMap[] =
{
[Rcm_PeripheralClockSource_XTAL_CLK] = 0x111U,
[Rcm_PeripheralClockSource_SYS_CLK] = 0x222U,
[Rcm_PeripheralClockSource_DPLL_PER_HSDIV0_CLKOUT3] = 0x888U, /* Set unsupported clock source to 0x888 which indicates invalid value */
};
-static uint16_t gRcssATLClkSrcValMap[] =
+static const uint16_t gRcssATLClkSrcValMap[] =
{
[Rcm_PeripheralClockSource_XTAL_CLK] = 0x111U,
[Rcm_PeripheralClockSource_SYS_CLK] = 0x222U,
[Rcm_PeripheralClockSource_DPLL_CORE_HSDIV0_CLKOUT2] = 0x888U,
};
-static uint16_t gRcssMCASPAuxClkSrcValMap[] =
+static const uint16_t gRcssMCASPAuxClkSrcValMap[] =
{
[Rcm_PeripheralClockSource_XTAL_CLK] = 0x888U,
[Rcm_PeripheralClockSource_SYS_CLK] = 0x888U,
[Rcm_PeripheralClockSource_DPLL_PER_HSDIV0_CLKOUT3] = 0x444U,
};
-static uint16_t gCptsClkSrcValMap[] =
+static const uint16_t gCptsClkSrcValMap[] =
{
[Rcm_PeripheralClockSource_XTAL_CLK] = 0x111U,
[Rcm_PeripheralClockSource_SYS_CLK] = 0x222U,
[Rcm_PeripheralClockSource_DPLL_PER_HSDIV0_CLKOUT3] = 0x888U, /* Set unsupported clock source to 0x888 which indicates invalid value */
};
-static uint16_t gCpswClkSrcValMap[] =
+static const uint16_t gCpswClkSrcValMap[] =
{
[Rcm_PeripheralClockSource_XTAL_CLK] = 0x111U,
[Rcm_PeripheralClockSource_SYS_CLK] = 0x222U,
[Rcm_PeripheralClockSource_DPLL_PER_HSDIV0_CLKOUT3] = 0x888U, /* Set unsupported clock source to 0x888 which indicates invalid value */
};
-static uint16_t gDspcoreClkSrcValMap[] =
+static const uint16_t gDspcoreClkSrcValMap[] =
{
[Rcm_DSPClockSource_XTAL_CLK] = 0x111,
[Rcm_DSPClockSource_DPLL_DSP_HSDIV0_CLKOUT1] = 0x222,
[Rcm_DSPClockSource_DPLL_CORE_HSDIV0_CLKOUT1] = 0x444
};
-static uint16_t gCR5ClkSrcValMap[] =
+static const uint16_t gCR5ClkSrcValMap[] =
{
[Rcm_CR5ClockSource_DPLL_CORE_HSDIV0_CLKOUT2] = 0x222U,
};
* @details
* Mapping Array between Reset Cause Bit and Reset Cause
*/
-static Rcm_ResetCause gResetBitToResetCause[11U] =
+static const Rcm_ResetCause gResetBitToResetCause[11U] =
{
Rcm_ResetCause_POWER_ON_RESET,
Rcm_ResetCause_WARM_RESET,
************************** RCM Functions *****************************
**************************************************************************/
-static uint32_t getClkSrcFromClkSelVal(uint16_t *clkSelTbl, uint32_t numEntries, uint32_t clkSelMatchVal)
+static uint32_t getClkSrcFromClkSelVal(const uint16_t *clkSelTbl, uint32_t numEntries, uint32_t clkSelMatchVal)
{
uint32_t i;
uint32_t clkSource;
interruptRegParams.corepacConfig.arg = (uintptr_t)(instIndex);
interruptRegParams.corepacConfig.corepacEventNum = gpioHwAttr->highInterruptNum;
+#if defined(SOC_TPR12) /* All TPR12 interrupts are pulse and not level */
+ interruptRegParams.corepacConfig.triggerSensitivity = OSAL_ARM_GIC_TRIG_TYPE_EDGE;
+#endif
#if defined(_TMS320C6X)
interruptRegParams.corepacConfig.intVecNum = OSAL_REGINT_INTVEC_EVENT_COMBINER;
#else
interruptRegParams.corepacConfig.arg = (uintptr_t)(instIndex);
interruptRegParams.corepacConfig.corepacEventNum = gpioHwAttr->lowInterruptNum;
+#if defined(SOC_TPR12) /* All TPR12 interrupts are pulse and not level */
+ interruptRegParams.corepacConfig.triggerSensitivity = OSAL_ARM_GIC_TRIG_TYPE_EDGE;
+#endif
#if defined(_TMS320C6X)
interruptRegParams.corepacConfig.intVecNum = OSAL_REGINT_INTVEC_EVENT_COMBINER;
#else
diff --git a/packages/ti/drv/mailbox/examples/mailbox_msg_testapp/main_dss.c b/packages/ti/drv/mailbox/examples/mailbox_msg_testapp/main_dss.c
index 4be2e5919be8e5115205fe1f75eb024a9cb754b9..895e58e4ad9c7aa6c2f543ce7ba07b85d5622122 100644 (file)
{
uint32_t retVal = 0;
- printf("DSS: App Sync\n");
+ System_printf("DSS: App Sync\n");
App_setDssState(1U);
while (retVal == 0)
Task_sleep(1);
}
- printf("DSS: App Sync Done.\n");
+ System_printf("DSS: App Sync Done.\n");
App_setMssState (0U);
}
openParam.remoteEndpoint = MAILBOX_INST_MSS_CR5A;
openParam.cfg.readMode = MAILBOX_MODE_CALLBACK;
openParam.cfg.readCallback = Test_appCallbackFunction;
- openParam.cfg.writeTimeout = 1000U;
+ //openParam.cfg.writeTimeout = 1000U;
/* Open the Instance */
handle = Mailbox_open(&openParam, &errCode);
openParam.cfg.readMode = MAILBOX_MODE_CALLBACK;
openParam.cfg.readCallback = Test_appCallbackFunction3;
openParam.cfg.writeMode = MAILBOX_MODE_BLOCKING;
- openParam.cfg.writeTimeout = 1000U;
+ //openParam.cfg.writeTimeout = 1000U;
handleArray[3] = Mailbox_open(&openParam, &errCode);
if (handleArray[3] == NULL)
openParam.cfg.chId = MAILBOX_CH_ID_4;
openParam.cfg.readMode = MAILBOX_MODE_BLOCKING;
openParam.cfg.writeMode = MAILBOX_MODE_BLOCKING;
- openParam.cfg.writeTimeout = 1000U;
+ //openParam.cfg.writeTimeout = 1000U;
handleArray[4] = Mailbox_open(&openParam, &errCode);
if (handleArray[4] == NULL)
openParam.cfg.chId = MAILBOX_CH_ID_7;
openParam.cfg.readMode = MAILBOX_MODE_BLOCKING;
openParam.cfg.writeMode = MAILBOX_MODE_BLOCKING;
- openParam.cfg.writeTimeout = 1000U;
+ //openParam.cfg.writeTimeout = 1000U;
handleArray[7] = Mailbox_open(&openParam, &errCode);
if (handleArray[7] == NULL)
diff --git a/packages/ti/drv/mailbox/examples/mailbox_msg_testapp/main_mss.c b/packages/ti/drv/mailbox/examples/mailbox_msg_testapp/main_mss.c
index e903068e9dbc34f662940d087d5b8118d07b672c..c745d0018b907d3e675852c5898fee2fd2129934 100644 (file)
{
uint32_t retVal = 0;
- printf("MSS: App Sync\n");
+ System_printf("MSS: App Sync\n");
App_setMssState(1U);
while (retVal == 0)
Task_sleep(1);
}
- printf("MSS: App Sync Done.\n");
+ System_printf("MSS: App Sync Done.\n");
App_setDssState (0U);
}
openParam.remoteEndpoint = MAILBOX_INST_DSP;
openParam.cfg.readMode = MAILBOX_MODE_CALLBACK;
openParam.cfg.readCallback = Test_appCallbackFunction;
- openParam.cfg.writeTimeout = 1000U;
+ //openParam.cfg.writeTimeout = 1000U;
/* Open the Instance to DSS */
handleDss = Mailbox_open(&openParam, &errCode);
openParam.cfg.readMode = MAILBOX_MODE_CALLBACK;
openParam.cfg.readCallback = Test_appCallbackFunction3;
openParam.cfg.writeMode = MAILBOX_MODE_BLOCKING;
- openParam.cfg.writeTimeout = 1000U;
+ //openParam.cfg.writeTimeout = 1000U;
handleArray[3] = Mailbox_open(&openParam, &errCode);
if (handleArray[3] == NULL)
openParam.cfg.chId = MAILBOX_CH_ID_4;
openParam.cfg.readMode = MAILBOX_MODE_BLOCKING;
openParam.cfg.writeMode = MAILBOX_MODE_BLOCKING;
- openParam.cfg.writeTimeout = 1000U;
+ //openParam.cfg.writeTimeout = 1000U;
handleArray[4] = Mailbox_open(&openParam, &errCode);
if (handleArray[4] == NULL)
openParam.cfg.chId = MAILBOX_CH_ID_7;
openParam.cfg.readMode = MAILBOX_MODE_BLOCKING;
openParam.cfg.writeMode = MAILBOX_MODE_BLOCKING;
- openParam.cfg.writeTimeout = 1000U;
+ //openParam.cfg.writeTimeout = 1000U;
handleArray[7] = Mailbox_open(&openParam, &errCode);
if (handleArray[7] == NULL)
diff --git a/packages/ti/drv/spi/test/qspi_flash/src/main_qspi_flash_test.c b/packages/ti/drv/spi/test/qspi_flash/src/main_qspi_flash_test.c
index a87ec6a2db89fee02294515799333a65c9e8eace..f410d89034d9d7de32a78dc7253600d05d387373 100644 (file)
@@ -723,7 +723,7 @@ int32_t QSPI_test_readInputFile(S25FL_Handle flashHandle, QSPI_Tests *test, bool
}
fclose(fp);
- return 0;
+ return true;
}
static bool QSPI_test_func_file_write (void *arg)