PRSDK-8021: PDK: Fix J7VCL build error
authorSivaraj R <sivaraj@ti.com>
Sat, 7 Mar 2020 07:46:50 +0000 (13:16 +0530)
committerMahesh Radhakrishnan <a0875154@ti.com>
Mon, 9 Mar 2020 14:43:48 +0000 (09:43 -0500)
- Protected UTC and DRU configuration properly so that no access/call
can happen through user
- Also ported the PSIL and PDMA testcases to match J7VCL soc data
- Also fixed OSAL, I2C and MMCSD and UART build issues

Signed-off-by: Sivaraj R <sivaraj@ti.com>
28 files changed:
packages/ti/drv/i2c/test/eeprom_read/makefile
packages/ti/drv/mmcsd/test/src/MMCSD_log.h
packages/ti/drv/mmcsd/test/src/main.c
packages/ti/drv/mmcsd/test/src/main_emmc.c
packages/ti/drv/uart/uart_component.mk
packages/ti/drv/udma/include/udma_cfg.h
packages/ti/drv/udma/include/udma_ch.h
packages/ti/drv/udma/soc/V2/udma_soc.c
packages/ti/drv/udma/soc/V2/udma_soc.h
packages/ti/drv/udma/src/udma_ch.c
packages/ti/drv/udma/src/udma_event.c
packages/ti/drv/udma/src/udma_priv.h
packages/ti/drv/udma/src/udma_rm.c
packages/ti/drv/udma/udma.h
packages/ti/drv/udma/udma_component.mk
packages/ti/drv/udma/unit_test/udma_ut/baremetal/j7200/linker_a72.lds [new file with mode: 0755]
packages/ti/drv/udma/unit_test/udma_ut/baremetal/j7200/linker_r5f.lds [new file with mode: 0644]
packages/ti/drv/udma/unit_test/udma_ut/rtos/j7200/linker_mcu1_0.lds [new file with mode: 0644]
packages/ti/drv/udma/unit_test/udma_ut/rtos/j7200/linker_mcu1_1.lds [new file with mode: 0644]
packages/ti/drv/udma/unit_test/udma_ut/rtos/j7200/linker_mcu2_0.lds [new file with mode: 0644]
packages/ti/drv/udma/unit_test/udma_ut/rtos/j7200/linker_mcu2_1.lds [new file with mode: 0644]
packages/ti/drv/udma/unit_test/udma_ut/rtos/j7200/linker_mpu1_0.lds [new file with mode: 0644]
packages/ti/drv/udma/unit_test/udma_ut/src/soc/j7200/udma_test_soc.c
packages/ti/drv/udma/unit_test/udma_ut/src/udma_test_parser.c
packages/ti/drv/udma/unit_test/udma_ut/src/udma_testcases.h
packages/ti/drv/udma/unit_test/udma_ut/src/udma_testconfig.h
packages/ti/drv/udma/unit_test/udma_ut_component.mk
packages/ti/osal/test/sysbios_unit_test/makefile

index 15beec0d30b05de895c00e7ea499de26d2079588..9cb3b06bf7672f9ea37e53761a8e9f8e94693b32 100644 (file)
@@ -66,11 +66,14 @@ endif
 
 CFLAGS_I2C_UT =
 
-PACKAGE_SRCS_COMMON = src makefile $(SOC)
+PACKAGE_SRCS_COMMON = src makefile
+ifeq ($(SOC),$(filter $(SOC), am65xx))
+  PACKAGE_SRCS_COMMON += $(SOC)
+endif
 CFLAGS_LOCAL_COMMON = $(PDK_CFLAGS) $(CFLAGS_I2C_UT) $(CFLAGS_OS_DEFINES)
 
 ifeq ($(SOC),$(filter $(SOC), j721e j7200))
-CFLAGS_LOCAL_COMMON += -DUNITY_INCLUDE_CONFIG_H 
+CFLAGS_LOCAL_COMMON += -DUNITY_INCLUDE_CONFIG_H
 endif
 # Core/SoC/platform specific source files and CFLAGS
 # Example:
index ddcf82abb8db2a7dd374d22d5703ab0b9a464c29..c9dd99027b22778e2e2583fe33f86d829d4da617 100644 (file)
@@ -51,7 +51,7 @@ extern "C" {
 /* UART Header files */
 #include <ti/drv/uart/UART.h>
 #include <ti/drv/uart/UART_stdio.h>
-#if !defined(SOC_AM65XX) && !defined(SOC_J721E)
+#if !defined(SOC_AM65XX) && !defined(SOC_J721E) && !defined(SOC_J7200)
 #include <ti/csl/soc/am572x/src/cslr_control_core_pad_io.h>
 #endif
 
index f823eb117f9a9764b01a65a0f6d9950ca42a9b6f..4c0ab1298d880253e70dd34442c574c2c41b7b21 100644 (file)
@@ -171,7 +171,7 @@ const FATFSConfigList FATFS_config = {
 #endif
 #include "profiling.h"
 
-#if defined(SOC_AM65XX) || defined(SOC_J721E)
+#if defined(SOC_AM65XX) || defined(SOC_J721E) || defined(SOC_J7200)
 #include <ti/csl/src/ip/intr_router/V0/csl_intr_router.h>
 #endif
 /**********************************************************************
@@ -394,7 +394,7 @@ Void InitMmu()
         goto mmu_exit;
     }
 
-#if defined(SOC_J721E) || defined(SOC_J7200)   
+#if defined(SOC_J721E) || defined(SOC_J7200)
     ret=Mmu_map(0x01800000, 0x01800000, 0x00200000, &attrs); /* gicv3       */
     if(ret==false) {
                goto mmu_exit;
@@ -454,7 +454,7 @@ Void InitMmu()
 
                goto mmu_exit;
        }
-           
+
        ret=Mmu_map(0x42120000, 0x42120000, 0x00001000, &attrs); /* mmcsd        */
 
     if(ret==false) {
@@ -873,7 +873,7 @@ mmcsdTestSDProfile_t * mmcsdTestProfiles[] = {
        &SDProfiles_1p8V_SDR25,
        &SDProfiles_1p8V_SDR50,
        &SDProfiles_1p8V_DDR50,
-       
+
 #if !defined(SOC_J721E) && !defined(SOC_J7200)
        &SDProfiles_1p8V_SDR104,
 #endif
@@ -1070,7 +1070,7 @@ void mmcsd_test(UArg arg0, UArg arg1)
         hwAttrsConfigDefault.cardType=MMCSD_CARD_SD;
         hwAttrsConfig.supportedBusWidth= (MMCSD_BUS_WIDTH_1BIT | MMCSD_BUS_WIDTH_4BIT);
 #endif
+
      readWriteTestFlag = 1;
 
 
@@ -1103,8 +1103,8 @@ void mmcsd_test(UArg arg0, UArg arg1)
 #ifdef MMCSD_DMA_ENABLED
      /* EDMA / ADMA2 / SDMA */
      hwAttrsConfig.enableDma=1;
-     
-     
+
+
 #ifdef MMCSD_EDMA_ENABLED
       hwAttrsConfig.edmaHandle = gEdmaHandle;
 #endif
@@ -1295,7 +1295,7 @@ int32_t fillMmcPageData(uint8_t *buf, int32_t length, uint8_t flag,uint32_t *ram
              *rampBase = *rampBase+1;
          }
 
-    } 
+    }
     else {
      for(i =0; i < length; i++)  {
         *(buf+i) = data;
@@ -1396,7 +1396,7 @@ int32_t HSMMCSDReadWriteTest_RAW(mmcsdTestSDProfile_t *testProfilePtr)
           goto raw_test_exit;
         }
      }
+
 #ifdef MEASURE_TIME
      profile_end_point(PROFILE_MMCSD_WRITE);
 #endif
@@ -1417,7 +1417,7 @@ int32_t HSMMCSDReadWriteTest_RAW(mmcsdTestSDProfile_t *testProfilePtr)
           goto raw_test_exit;
         }
     }
-    
+
 
 #ifdef MEASURE_TIME
      profile_end_point(PROFILE_MMCSD_READ);
index ac0e8d07c28ac82f146abfa1d986986fe2587e17..55a733aa5ac605b59b4940be6c5c837a6097dd4b 100644 (file)
 
 #include "profiling.h"
 
-#if defined(SOC_AM65XX) || defined(SOC_J721E)
+#if defined(SOC_AM65XX) || defined(SOC_J721E) || defined(SOC_J7200)
 #include <ti/csl/src/ip/intr_router/V0/csl_intr_router.h>
 #endif
 /**********************************************************************
@@ -1216,7 +1216,7 @@ int32_t HSMMCSDReadWriteTest_RAW(mmcsdTestMMCProfile_t *testProfilePtr)
      goto raw_test_exit;
   } else {
      MMCSD_log ("\nMMCSD_Open() completed successfully\n");
-  }      
+  }
   mmcStartSector=MMCSTARTSECTOR;
 
   /* Fill up the data pattern once */
index b8c27ef13a66b2af9bd7876e9781fd6207a14686..2ab17820fb248e60d1018777ae305d713795ec13 100644 (file)
@@ -150,10 +150,9 @@ uart_PKG_LIST = uart
 uart_INCLUDE = $(uart_PATH)
 uart_SOCLIST = tda2xx tda2px tda2ex tda3xx dra78x am574x am572x am571x dra72x dra75x k2h k2k k2l k2e k2g c6678 c6657 am437x am335x omapl137 omapl138 am65xx j721e j7200
 export uart_SOCLIST
-ifeq ($(SOC),$(filter $(SOC), j721e j7200))
-uart_$(SOC)_CORELIST = $(drvuart_$(SOC)_CORELIST) c7x_1
-else
 uart_$(SOC)_CORELIST = $(drvuart_$(SOC)_CORELIST)
+ifeq ($(SOC),$(filter $(SOC), j721e))
+uart_$(SOC)_CORELIST += c7x_1
 endif
 export uart_$(SOC)_CORELIST
 
index f6574dba8327be73a3d55913026219ff9b4b5b79..425926a505423d9c33be12d22f88c0c79810eb77 100644 (file)
@@ -146,8 +146,10 @@ extern "C" {
 /** \brief Default RX channel bus order ID */
 #define UDMA_DEFAULT_UTC_CH_BUS_ORDERID     (0U)
 
+#if (UDMA_NUM_UTC_INSTANCE > 0)
 /** \brief Default DRU queue ID */
 #define UDMA_DEFAULT_UTC_DRU_QUEUE_ID       (CSL_DRU_QUEUE_ID_3)
+#endif
 
 /** \brief UDMA print buffer length */
 #define UDMA_CFG_PRINT_BUF_LEN              ((uint32_t) 1024U)
index 572ed3380d499c72a8aeaa26f1c2d1af83dff08a..5ca047bd3602ece2fd3ece47e821cba3117b02a5 100644 (file)
@@ -428,6 +428,7 @@ typedef struct
      *      TRUE = Suppress sending TD packet
      *   TODO: Should we allocate tdCq based on this flag?
      */
+#if (UDMA_NUM_UTC_INSTANCE > 0)
     /* Below fields are applicable only for DRU UTC */
     uint64_t                druOwner;
     /**< [IN] This field controls how the TR is received by the DRU.
@@ -445,6 +446,7 @@ typedef struct
      *        The priority queue is queue 0 the round robin
      *        queues are queues 1 - 4.
      */
+#endif
 } Udma_ChUtcPrms;
 
 /**
@@ -948,6 +950,7 @@ int32_t Udma_chGetStats(Udma_ChHandle chHandle, Udma_ChStats *chStats);
 /*                  Internal/Private Structure Declarations                   */
 /* ========================================================================== */
 
+#if (UDMA_NUM_UTC_INSTANCE > 0)
 /**
  *  \brief UDMA UTC instance information.
  *
@@ -977,6 +980,7 @@ typedef struct
     uint32_t                numQueue;
     /**< Number of queues present in a DRU*/
 } Udma_UtcInstInfo;
+#endif
 
 /**
  *  \brief UDMA channel object.
@@ -992,8 +996,10 @@ struct Udma_ChObj
     /**< Object to store the channel params. */
     Udma_DrvHandle          drvHandle;
     /**< Pointer to global driver handle. */
+#if (UDMA_NUM_UTC_INSTANCE > 0)
     const Udma_UtcInstInfo *utcInfo;
     /**< Pointer to global UTC instance info. */
+#endif
 
     uint32_t                txChNum;
     /**< Allocated TX channel number - this is relative channel number from
@@ -1056,10 +1062,12 @@ struct Udma_ChObj
     /**< Pointer to UDMAP External config register overlay */
     volatile CSL_udmap_txcrtRegs_chan   *pExtRtRegs;
     /**< Pointer to UDMAP External RT config register overlay */
+#if (UDMA_NUM_UTC_INSTANCE > 0)
     volatile CSL_DRU_CHNRTRegs_CHNRT    *pDruNrtRegs;
     /**< Pointer to DRU Non RT config register overlay */
     volatile CSL_DRU_CHRTRegs_CHRT      *pDruRtRegs;
     /**< Pointer to DRU RT config register overlay */
+#endif
 
     uint32_t                chInitDone;
     /**< Flag to set the channel object is init. */
index d64e4696dc29e0062bf341aade403fce08707464..a317aa7f82876edd25f204ae01db9d645bf36188 100644 (file)
@@ -208,10 +208,8 @@ void Udma_initDrvHandle(Udma_DrvHandle drvHandle)
     drvHandle->devIdIa      = TISCI_DEV_MCU_NAVSS0_INTAGGR_0;
 #if defined (BUILD_MCU1_0)
     drvHandle->devIdCore    = TISCI_DEV_MCU_R5FSS0_CORE0;
-    drvHandle->druCoreId    = UDMA_DRU_CORE_ID_MCU1_0;
 #else
     drvHandle->devIdCore    = TISCI_DEV_MCU_R5FSS0_CORE1;
-    drvHandle->druCoreId    = UDMA_DRU_CORE_ID_MCU1_1;
 #endif
 #else
     /* IA config init */
@@ -231,15 +229,12 @@ void Udma_initDrvHandle(Udma_DrvHandle drvHandle)
     drvHandle->clecOffset   = 0U;
 #if defined (BUILD_MPU1_0)
     drvHandle->devIdCore    = TISCI_DEV_COMPUTE_CLUSTER0_GIC500SS;
-    drvHandle->druCoreId    = UDMA_DRU_CORE_ID_MPU1_0;
 #endif
 #if defined (BUILD_MCU2_0)
     drvHandle->devIdCore    = TISCI_DEV_R5FSS0_CORE0;
-    drvHandle->druCoreId    = UDMA_DRU_CORE_ID_MCU2_0;
 #endif
 #if defined (BUILD_MCU2_1)
     drvHandle->devIdCore    = TISCI_DEV_R5FSS0_CORE1;
-    drvHandle->druCoreId    = UDMA_DRU_CORE_ID_MCU2_1;
 #endif
 #endif
 
index 392e141827734c39a2adacbd9882d86df982d850..48962d5777ad0af03123966a004fd8a53fb755af 100644 (file)
@@ -110,29 +110,6 @@ extern "C" {
 #define UDMA_NUM_CORE                   (UDMA_NUM_MAIN_CORE + UDMA_NUM_MCU_CORE)
 /* @} */
 
-/**
- *  \anchor Udma_DruSubmitCoreId
- *  \name DRU core ID register to use for direct TR submission.
- *   Each CPU should have a unique submit register to avoid corrupting
- *   submit word when SW is running from multiple CPU at the same time.
- *
- *   Note: Since only 3 submit register set is present, we need to share some
- *   of them across cores. This means that Direct TR from these cores can't
- *   run simultaneously.
- *   In this case C7x and C66x are provided unique ID which are more likely to
- *   use direct TR mode and other cores share the same core ID.
- *
- *  List of all DRU cores ID to use for all the CPUs present in the SOC.
- *
- *  @{
- */
-#define UDMA_DRU_CORE_ID_MPU1_0         (CSL_DRU_CORE_ID_2)
-#define UDMA_DRU_CORE_ID_MCU2_0         (CSL_DRU_CORE_ID_2)
-#define UDMA_DRU_CORE_ID_MCU2_1         (CSL_DRU_CORE_ID_2)
-#define UDMA_DRU_CORE_ID_MCU1_0         (CSL_DRU_CORE_ID_2)
-#define UDMA_DRU_CORE_ID_MCU1_1         (CSL_DRU_CORE_ID_2)
-/* @} */
-
 /**
  *  \anchor Udma_PsilCh
  *  \name PSIL Channels
@@ -150,25 +127,10 @@ extern "C" {
  *
  *  @{
  */
-#define UDMA_PSIL_CH_MAIN_SAUL0_TX          (CSL_PSILCFG_NAVSS_MAIN_SAUL0_PSILD_THREAD_OFFSET)
-#define UDMA_PSIL_CH_MAIN_ICSS_G0_TX        (CSL_PSILCFG_NAVSS_MAIN_ICSS_G0_PSILD_THREAD_OFFSET)
-#define UDMA_PSIL_CH_MAIN_ICSS_G1_TX        (CSL_PSILCFG_NAVSS_MAIN_ICSS_G1_PSILD_THREAD_OFFSET)
-#define UDMA_PSIL_CH_MAIN_CPSW9_TX          (CSL_PSILCFG_NAVSS_MAIN_CPSW9_PSILD_THREAD_OFFSET)
-
-#define UDMA_PSIL_CH_MAIN_SAUL0_RX          (CSL_PSILCFG_NAVSS_MAIN_SAUL0_PSILS_THREAD_OFFSET)
-#define UDMA_PSIL_CH_MAIN_ICSS_G0_RX        (CSL_PSILCFG_NAVSS_MAIN_ICSS_G0_PSILS_THREAD_OFFSET)
-#define UDMA_PSIL_CH_MAIN_ICSS_G1_RX        (CSL_PSILCFG_NAVSS_MAIN_ICSS_G1_PSILS_THREAD_OFFSET)
-#define UDMA_PSIL_CH_MAIN_CPSW9_RX          (CSL_PSILCFG_NAVSS_MAIN_CPSW9_PSILS_THREAD_OFFSET)
-
-#define UDMA_PSIL_CH_MAIN_SAUL0_TX_CNT      (CSL_PSILCFG_NAVSS_MAIN_SAUL0_PSILD_THREAD_CNT)
-#define UDMA_PSIL_CH_MAIN_ICSS_G0_TX_CNT    (CSL_PSILCFG_NAVSS_MAIN_ICSS_G0_PSILD_THREAD_CNT)
-#define UDMA_PSIL_CH_MAIN_ICSS_G1_TX_CNT    (CSL_PSILCFG_NAVSS_MAIN_ICSS_G1_PSILD_THREAD_CNT)
-
-#define UDMA_PSIL_CH_MAIN_SAUL0_RX_CNT      (CSL_PSILCFG_NAVSS_MAIN_SAUL0_PSILS_THREAD_CNT)
-#define UDMA_PSIL_CH_MAIN_ICSS_G0_RX_CNT    (CSL_PSILCFG_NAVSS_MAIN_ICSS_G0_PSILS_THREAD_CNT)
-#define UDMA_PSIL_CH_MAIN_ICSS_G1_RX_CNT    (CSL_PSILCFG_NAVSS_MAIN_ICSS_G1_PSILS_THREAD_CNT)
-#define UDMA_PSIL_CH_MAIN_CPSW9_TX_CNT      (CSL_PSILCFG_NAVSS_MAIN_CPSW9_PSILD_THREAD_CNT)
-#define UDMA_PSIL_CH_MAIN_CPSW9_RX_CNT      (CSL_PSILCFG_NAVSS_MAIN_CPSW9_PSILS_THREAD_CNT)
+#define UDMA_PSIL_CH_MAIN_CPSW5_TX          (CSL_PSILCFG_NAVSS_MAIN_CPSW5_PSILD_THREAD_OFFSET)
+#define UDMA_PSIL_CH_MAIN_CPSW5_RX          (CSL_PSILCFG_NAVSS_MAIN_CPSW5_PSILS_THREAD_OFFSET)
+#define UDMA_PSIL_CH_MAIN_CPSW5_TX_CNT      (CSL_PSILCFG_NAVSS_MAIN_CPSW5_PSILD_THREAD_CNT)
+#define UDMA_PSIL_CH_MAIN_CPSW5_RX_CNT      (CSL_PSILCFG_NAVSS_MAIN_CPSW5_PSILS_THREAD_CNT)
 /* @} */
 
 /**
@@ -217,26 +179,6 @@ extern "C" {
 #define UDMA_PDMA_CH_MAIN_MCASP0_TX     (CSL_PDMA_CH_MAIN_MCASP0_CH0_TX)
 #define UDMA_PDMA_CH_MAIN_MCASP1_TX     (CSL_PDMA_CH_MAIN_MCASP1_CH0_TX)
 #define UDMA_PDMA_CH_MAIN_MCASP2_TX     (CSL_PDMA_CH_MAIN_MCASP2_CH0_TX)
-#define UDMA_PDMA_CH_MAIN_MCASP3_TX     (CSL_PDMA_CH_MAIN_MCASP3_CH0_TX)
-#define UDMA_PDMA_CH_MAIN_MCASP4_TX     (CSL_PDMA_CH_MAIN_MCASP4_CH0_TX)
-#define UDMA_PDMA_CH_MAIN_MCASP5_TX     (CSL_PDMA_CH_MAIN_MCASP5_CH0_TX)
-#define UDMA_PDMA_CH_MAIN_MCASP6_TX     (CSL_PDMA_CH_MAIN_MCASP6_CH0_TX)
-#define UDMA_PDMA_CH_MAIN_MCASP7_TX     (CSL_PDMA_CH_MAIN_MCASP7_CH0_TX)
-#define UDMA_PDMA_CH_MAIN_MCASP8_TX     (CSL_PDMA_CH_MAIN_MCASP8_CH0_TX)
-#define UDMA_PDMA_CH_MAIN_MCASP9_TX     (CSL_PDMA_CH_MAIN_MCASP9_CH0_TX)
-#define UDMA_PDMA_CH_MAIN_MCASP10_TX    (CSL_PDMA_CH_MAIN_MCASP10_CH0_TX)
-#define UDMA_PDMA_CH_MAIN_MCASP11_TX    (CSL_PDMA_CH_MAIN_MCASP11_CH0_TX)
-/*
- * PDMA Main AASRC TX Channels
- */
-#define UDMA_PDMA_CH_MAIN_AASRC0_CH0_TX (CSL_PDMA_CH_MAIN_AASRC0_CH0_TX)
-#define UDMA_PDMA_CH_MAIN_AASRC0_CH1_TX (CSL_PDMA_CH_MAIN_AASRC0_CH1_TX)
-#define UDMA_PDMA_CH_MAIN_AASRC0_CH2_TX (CSL_PDMA_CH_MAIN_AASRC0_CH2_TX)
-#define UDMA_PDMA_CH_MAIN_AASRC0_CH3_TX (CSL_PDMA_CH_MAIN_AASRC0_CH3_TX)
-#define UDMA_PDMA_CH_MAIN_AASRC0_CH4_TX (CSL_PDMA_CH_MAIN_AASRC0_CH4_TX)
-#define UDMA_PDMA_CH_MAIN_AASRC0_CH5_TX (CSL_PDMA_CH_MAIN_AASRC0_CH5_TX)
-#define UDMA_PDMA_CH_MAIN_AASRC0_CH6_TX (CSL_PDMA_CH_MAIN_AASRC0_CH6_TX)
-#define UDMA_PDMA_CH_MAIN_AASRC0_CH7_TX (CSL_PDMA_CH_MAIN_AASRC0_CH7_TX)
 /*
  * PDMA Main UART TX Channels
  */
@@ -330,6 +272,18 @@ extern "C" {
 #define UDMA_PDMA_CH_MAIN_MCAN13_CH0_TX (CSL_PDMA_CH_MAIN_MCAN13_CH0_TX)
 #define UDMA_PDMA_CH_MAIN_MCAN13_CH1_TX (CSL_PDMA_CH_MAIN_MCAN13_CH1_TX)
 #define UDMA_PDMA_CH_MAIN_MCAN13_CH2_TX (CSL_PDMA_CH_MAIN_MCAN13_CH2_TX)
+#define UDMA_PDMA_CH_MAIN_MCAN14_CH0_TX (CSL_PDMA_CH_MAIN_MCAN14_CH0_TX)
+#define UDMA_PDMA_CH_MAIN_MCAN14_CH1_TX (CSL_PDMA_CH_MAIN_MCAN14_CH1_TX)
+#define UDMA_PDMA_CH_MAIN_MCAN14_CH2_TX (CSL_PDMA_CH_MAIN_MCAN14_CH2_TX)
+#define UDMA_PDMA_CH_MAIN_MCAN15_CH0_TX (CSL_PDMA_CH_MAIN_MCAN15_CH0_TX)
+#define UDMA_PDMA_CH_MAIN_MCAN15_CH1_TX (CSL_PDMA_CH_MAIN_MCAN15_CH1_TX)
+#define UDMA_PDMA_CH_MAIN_MCAN15_CH2_TX (CSL_PDMA_CH_MAIN_MCAN15_CH2_TX)
+#define UDMA_PDMA_CH_MAIN_MCAN16_CH0_TX (CSL_PDMA_CH_MAIN_MCAN16_CH0_TX)
+#define UDMA_PDMA_CH_MAIN_MCAN16_CH1_TX (CSL_PDMA_CH_MAIN_MCAN16_CH1_TX)
+#define UDMA_PDMA_CH_MAIN_MCAN16_CH2_TX (CSL_PDMA_CH_MAIN_MCAN16_CH2_TX)
+#define UDMA_PDMA_CH_MAIN_MCAN17_CH0_TX (CSL_PDMA_CH_MAIN_MCAN17_CH0_TX)
+#define UDMA_PDMA_CH_MAIN_MCAN17_CH1_TX (CSL_PDMA_CH_MAIN_MCAN17_CH1_TX)
+#define UDMA_PDMA_CH_MAIN_MCAN17_CH2_TX (CSL_PDMA_CH_MAIN_MCAN17_CH2_TX)
 /* @} */
 
 /**
@@ -384,26 +338,6 @@ extern "C" {
 #define UDMA_PDMA_CH_MAIN_MCASP0_RX     (CSL_PDMA_CH_MAIN_MCASP0_CH0_RX)
 #define UDMA_PDMA_CH_MAIN_MCASP1_RX     (CSL_PDMA_CH_MAIN_MCASP1_CH0_RX)
 #define UDMA_PDMA_CH_MAIN_MCASP2_RX     (CSL_PDMA_CH_MAIN_MCASP2_CH0_RX)
-#define UDMA_PDMA_CH_MAIN_MCASP3_RX     (CSL_PDMA_CH_MAIN_MCASP3_CH0_RX)
-#define UDMA_PDMA_CH_MAIN_MCASP4_RX     (CSL_PDMA_CH_MAIN_MCASP4_CH0_RX)
-#define UDMA_PDMA_CH_MAIN_MCASP5_RX     (CSL_PDMA_CH_MAIN_MCASP5_CH0_RX)
-#define UDMA_PDMA_CH_MAIN_MCASP6_RX     (CSL_PDMA_CH_MAIN_MCASP6_CH0_RX)
-#define UDMA_PDMA_CH_MAIN_MCASP7_RX     (CSL_PDMA_CH_MAIN_MCASP7_CH0_RX)
-#define UDMA_PDMA_CH_MAIN_MCASP8_RX     (CSL_PDMA_CH_MAIN_MCASP8_CH0_RX)
-#define UDMA_PDMA_CH_MAIN_MCASP9_RX     (CSL_PDMA_CH_MAIN_MCASP9_CH0_RX)
-#define UDMA_PDMA_CH_MAIN_MCASP10_RX    (CSL_PDMA_CH_MAIN_MCASP10_CH0_RX)
-#define UDMA_PDMA_CH_MAIN_MCASP11_RX    (CSL_PDMA_CH_MAIN_MCASP11_CH0_RX)
-/*
- * PDMA Main AASRC RX Channels
- */
-#define UDMA_PDMA_CH_MAIN_AASRC0_CH0_RX (CSL_PDMA_CH_MAIN_AASRC0_CH0_RX)
-#define UDMA_PDMA_CH_MAIN_AASRC0_CH1_RX (CSL_PDMA_CH_MAIN_AASRC0_CH1_RX)
-#define UDMA_PDMA_CH_MAIN_AASRC0_CH2_RX (CSL_PDMA_CH_MAIN_AASRC0_CH2_RX)
-#define UDMA_PDMA_CH_MAIN_AASRC0_CH3_RX (CSL_PDMA_CH_MAIN_AASRC0_CH3_RX)
-#define UDMA_PDMA_CH_MAIN_AASRC0_CH4_RX (CSL_PDMA_CH_MAIN_AASRC0_CH4_RX)
-#define UDMA_PDMA_CH_MAIN_AASRC0_CH5_RX (CSL_PDMA_CH_MAIN_AASRC0_CH5_RX)
-#define UDMA_PDMA_CH_MAIN_AASRC0_CH6_RX (CSL_PDMA_CH_MAIN_AASRC0_CH6_RX)
-#define UDMA_PDMA_CH_MAIN_AASRC0_CH7_RX (CSL_PDMA_CH_MAIN_AASRC0_CH7_RX)
 /*
  * PDMA Main UART RX Channels
  */
@@ -497,6 +431,18 @@ extern "C" {
 #define UDMA_PDMA_CH_MAIN_MCAN13_CH0_RX (CSL_PDMA_CH_MAIN_MCAN13_CH0_RX)
 #define UDMA_PDMA_CH_MAIN_MCAN13_CH1_RX (CSL_PDMA_CH_MAIN_MCAN13_CH1_RX)
 #define UDMA_PDMA_CH_MAIN_MCAN13_CH2_RX (CSL_PDMA_CH_MAIN_MCAN13_CH2_RX)
+#define UDMA_PDMA_CH_MAIN_MCAN14_CH0_RX (CSL_PDMA_CH_MAIN_MCAN14_CH0_RX)
+#define UDMA_PDMA_CH_MAIN_MCAN14_CH1_RX (CSL_PDMA_CH_MAIN_MCAN14_CH1_RX)
+#define UDMA_PDMA_CH_MAIN_MCAN14_CH2_RX (CSL_PDMA_CH_MAIN_MCAN14_CH2_RX)
+#define UDMA_PDMA_CH_MAIN_MCAN15_CH0_RX (CSL_PDMA_CH_MAIN_MCAN15_CH0_RX)
+#define UDMA_PDMA_CH_MAIN_MCAN15_CH1_RX (CSL_PDMA_CH_MAIN_MCAN15_CH1_RX)
+#define UDMA_PDMA_CH_MAIN_MCAN15_CH2_RX (CSL_PDMA_CH_MAIN_MCAN15_CH2_RX)
+#define UDMA_PDMA_CH_MAIN_MCAN16_CH0_RX (CSL_PDMA_CH_MAIN_MCAN16_CH0_RX)
+#define UDMA_PDMA_CH_MAIN_MCAN16_CH1_RX (CSL_PDMA_CH_MAIN_MCAN16_CH1_RX)
+#define UDMA_PDMA_CH_MAIN_MCAN16_CH2_RX (CSL_PDMA_CH_MAIN_MCAN16_CH2_RX)
+#define UDMA_PDMA_CH_MAIN_MCAN17_CH0_RX (CSL_PDMA_CH_MAIN_MCAN17_CH0_RX)
+#define UDMA_PDMA_CH_MAIN_MCAN17_CH1_RX (CSL_PDMA_CH_MAIN_MCAN17_CH1_RX)
+#define UDMA_PDMA_CH_MAIN_MCAN17_CH2_RX (CSL_PDMA_CH_MAIN_MCAN17_CH2_RX)
 /* @} */
 
 /**
index 06000cc2331197736f17ec9def2a81acbdd08839..7b3b8daf30a5ec8046657eb3c19498f533fed144 100755 (executable)
@@ -70,11 +70,13 @@ static int32_t Udma_chEnableLocal(Udma_ChHandle chHandle);
 static int32_t Udma_chDisableBlkCpyChan(Udma_ChHandle chHandle, uint32_t timeout);
 static int32_t Udma_chDisableTxChan(Udma_ChHandle chHandle, uint32_t timeout);
 static int32_t Udma_chDisableRxChan(Udma_ChHandle chHandle, uint32_t timeout);
+#if (UDMA_NUM_UTC_INSTANCE > 0)
 static int32_t Udma_chDisableExtChan(Udma_ChHandle chHandle, uint32_t timeout);
+#endif
 static uint32_t Udma_chGetTriggerEvent(Udma_DrvHandle drvHandle,
                                        Udma_ChHandle chHandle,
                                        uint32_t trigger);
-
+#if (UDMA_NUM_UTC_INSTANCE > 0)
 static int32_t Udma_psilcfgSetRtEnable(Udma_DrvHandle drvHandle,
                                        uint32_t threadId,
                                        uint32_t bEnable);
@@ -89,6 +91,7 @@ static int32_t Udma_psilcfgRead(Udma_DrvHandle drvHandle,
                                 uint32_t threadId,
                                 uint32_t regId,
                                 uint32_t *pData);
+#endif
 
 /* ========================================================================== */
 /*                            Global Variables                                */
@@ -133,7 +136,9 @@ int32_t Udma_chOpen(Udma_DrvHandle drvHandle,
         (void) memcpy(&chHandle->chPrms, chPrms, sizeof(Udma_ChPrms));
         chHandle->chType            = chType;
         chHandle->drvHandle         = drvHandle;
+#if (UDMA_NUM_UTC_INSTANCE > 0)
         chHandle->utcInfo           = (const Udma_UtcInstInfo *) NULL_PTR;
+#endif
         chHandle->txChNum           = UDMA_DMA_CH_INVALID;
         chHandle->rxChNum           = UDMA_DMA_CH_INVALID;
         chHandle->extChNum          = UDMA_DMA_CH_INVALID;
@@ -151,13 +156,16 @@ int32_t Udma_chOpen(Udma_DrvHandle drvHandle,
         chHandle->pRxRtRegs         = (volatile CSL_udmap_rxcrtRegs_chan *) NULL_PTR;
         chHandle->pExtCfgRegs       = (volatile CSL_udmap_txccfgRegs_chan *) NULL_PTR;
         chHandle->pExtRtRegs        = (volatile CSL_udmap_txcrtRegs_chan *) NULL_PTR;
+#if (UDMA_NUM_UTC_INSTANCE > 0)
         chHandle->pDruNrtRegs       = (volatile CSL_DRU_CHNRTRegs_CHNRT *) NULL_PTR;
         chHandle->pDruRtRegs        = (volatile CSL_DRU_CHRTRegs_CHRT *) NULL_PTR;
+#endif
         chHandle->chOesAllocDone    = FALSE;
         chHandle->trigger           = CSL_UDMAP_TR_FLAGS_TRIGGER_NONE;
 
         if((chHandle->chType & UDMA_CH_FLAG_UTC) == UDMA_CH_FLAG_UTC)
         {
+#if (UDMA_NUM_UTC_INSTANCE > 0)
             /* Get UTC instance object pointer */
             chHandle->utcInfo = Udma_chGetUtcInst(drvHandle, chPrms->utcId);
             if(NULL_PTR == chHandle->utcInfo)
@@ -165,6 +173,10 @@ int32_t Udma_chOpen(Udma_DrvHandle drvHandle,
                 retVal = UDMA_EINVALID_PARAMS;
                 Udma_printf(drvHandle, "[Error] Invalid UTC ID!!\n");
             }
+#else
+            retVal = UDMA_EFAIL;
+            Udma_printf(drvHandle, "[Error] UTC Not supported!!!\n");
+#endif
         }
     }
 
@@ -491,6 +503,7 @@ int32_t Udma_chConfigRx(Udma_ChHandle chHandle, const Udma_ChRxPrms *rxPrms)
 
 int32_t Udma_chConfigUtc(Udma_ChHandle chHandle, const Udma_ChUtcPrms *utcPrms)
 {
+#if (UDMA_NUM_UTC_INSTANCE > 0)
     int32_t                 retVal = UDMA_SOK;
     uint32_t                utcChNum;
     Udma_DrvHandle          drvHandle;
@@ -636,6 +649,9 @@ int32_t Udma_chConfigUtc(Udma_ChHandle chHandle, const Udma_ChUtcPrms *utcPrms)
         /* Copy the config */
         (void) memcpy(&chHandle->utcPrms, utcPrms, sizeof(chHandle->utcPrms));
     }
+#else
+    int32_t     retVal = UDMA_EFAIL;
+#endif
 
     return (retVal);
 }
@@ -759,10 +775,12 @@ int32_t Udma_chDisable(Udma_ChHandle chHandle, uint32_t timeout)
         {
             retVal = Udma_chDisableBlkCpyChan(chHandle, timeout);
         }
+#if (UDMA_NUM_UTC_INSTANCE > 0)
         else if((chHandle->chType & UDMA_CH_FLAG_UTC) == UDMA_CH_FLAG_UTC)
         {
             retVal = Udma_chDisableExtChan(chHandle, timeout);
         }
+#endif
         else
         {
             if((chHandle->chType & UDMA_CH_FLAG_TX) == UDMA_CH_FLAG_TX)
@@ -783,8 +801,10 @@ int32_t Udma_chPause(Udma_ChHandle chHandle)
 {
     int32_t                 retVal = UDMA_SOK;
     Udma_DrvHandle          drvHandle;
+#if (UDMA_NUM_UTC_INSTANCE > 0)
     uint32_t                utcChNum;
     const Udma_UtcInstInfo *utcInfo;
+#endif
 
     /* Error check */
     if((NULL_PTR == chHandle) || (chHandle->chInitDone != UDMA_INIT_DONE))
@@ -815,6 +835,7 @@ int32_t Udma_chPause(Udma_ChHandle chHandle)
             (void) CSL_udmapPauseRxChan(&drvHandle->udmapRegs, chHandle->rxChNum);
         }
 
+#if (UDMA_NUM_UTC_INSTANCE > 0)
         if((chHandle->chType & UDMA_CH_FLAG_UTC) == UDMA_CH_FLAG_UTC)
         {
             utcInfo = chHandle->utcInfo;
@@ -848,6 +869,7 @@ int32_t Udma_chPause(Udma_ChHandle chHandle)
                 }
             }
         }
+#endif
     }
 
     return (retVal);
@@ -857,8 +879,10 @@ int32_t Udma_chResume(Udma_ChHandle chHandle)
 {
     int32_t                 retVal = UDMA_SOK;
     Udma_DrvHandle          drvHandle;
+#if (UDMA_NUM_UTC_INSTANCE > 0)
     uint32_t                utcChNum;
     const Udma_UtcInstInfo *utcInfo;
+#endif
 
     /* Error check */
     if((NULL_PTR == chHandle) || (chHandle->chInitDone != UDMA_INIT_DONE))
@@ -889,6 +913,7 @@ int32_t Udma_chResume(Udma_ChHandle chHandle)
             (void) CSL_udmapUnpauseRxChan(&drvHandle->udmapRegs, chHandle->rxChNum);
         }
 
+#if (UDMA_NUM_UTC_INSTANCE > 0)
         if((chHandle->chType & UDMA_CH_FLAG_UTC) == UDMA_CH_FLAG_UTC)
         {
             utcInfo = chHandle->utcInfo;
@@ -922,6 +947,7 @@ int32_t Udma_chResume(Udma_ChHandle chHandle)
                 }
             }
         }
+#endif
     }
 
     return (retVal);
@@ -951,11 +977,13 @@ uint32_t Udma_chGetNum(Udma_ChHandle chHandle)
     {
         if((chHandle->chType & UDMA_CH_FLAG_UTC) == UDMA_CH_FLAG_UTC)
         {
+#if (UDMA_NUM_UTC_INSTANCE > 0)
             Udma_assert(drvHandle, chHandle->utcInfo != NULL_PTR);
             Udma_assert(drvHandle, chHandle->extChNum != UDMA_DMA_CH_INVALID);
             Udma_assert(drvHandle, chHandle->extChNum >= chHandle->utcInfo->startCh);
             /* Provide the channel offset within a UTC */
             chNum = chHandle->extChNum - chHandle->utcInfo->startCh;
+#endif
         }
         else
         {
@@ -1151,7 +1179,9 @@ int32_t Udma_chSetSwTrigger(Udma_ChHandle chHandle, uint32_t trigger)
 {
     int32_t                 retVal = UDMA_SOK;
     Udma_DrvHandle          drvHandle;
+#if (UDMA_NUM_UTC_INSTANCE > 0)
     const Udma_UtcInstInfo *utcInfo;
+#endif
 
     /* Error check */
     if((NULL_PTR == chHandle) ||
@@ -1187,6 +1217,7 @@ int32_t Udma_chSetSwTrigger(Udma_ChHandle chHandle, uint32_t trigger)
         }
         else
         {
+#if (UDMA_NUM_UTC_INSTANCE > 0)
             utcInfo = chHandle->utcInfo;
             Udma_assert(drvHandle, utcInfo != NULL_PTR);
             if(UDMA_UTC_TYPE_DRU == utcInfo->utcType)
@@ -1202,6 +1233,10 @@ int32_t Udma_chSetSwTrigger(Udma_ChHandle chHandle, uint32_t trigger)
                 Udma_printf(drvHandle,
                             "[Error] SW trigger not supported for other UTCs !!!\n");
             }
+#else
+            retVal = UDMA_EFAIL;
+            Udma_printf(drvHandle, "[Error] UTC Not supported!!!\n");
+#endif
         }
     }
 
@@ -1534,8 +1569,10 @@ void UdmaChUtcPrms_init(Udma_ChUtcPrms *utcPrms)
         utcPrms->dmaPriority    = UDMA_DEFAULT_UTC_CH_DMA_PRIORITY;
         utcPrms->burstSize      = TISCI_MSG_VALUE_RM_UDMAP_CH_BURST_SIZE_128_BYTES;
         utcPrms->supressTdCqPkt = TISCI_MSG_VALUE_RM_UDMAP_TX_CH_SUPPRESS_TD_DISABLED;
+#if (UDMA_NUM_UTC_INSTANCE > 0)
         utcPrms->druOwner       = CSL_DRU_OWNER_UDMAC_TR;
         utcPrms->druQueueId     = UDMA_DEFAULT_UTC_DRU_QUEUE_ID;
+#endif
     }
 
     return;
@@ -1553,12 +1590,12 @@ void UdmaChPdmaPrms_init(Udma_ChPdmaPrms *pdmaPrms)
     return;
 }
 
+#if (UDMA_NUM_UTC_INSTANCE > 0)
 const Udma_UtcInstInfo *Udma_chGetUtcInst(Udma_DrvHandle drvHandle,
                                           uint32_t utcId)
 
 {
     const Udma_UtcInstInfo *utcInfo = (const Udma_UtcInstInfo *) NULL_PTR;
-#if (UDMA_NUM_UTC_INSTANCE > 0)
     uint32_t                i;
 
     for(i = 0U; i < UDMA_NUM_UTC_INSTANCE; i++)
@@ -1569,10 +1606,10 @@ const Udma_UtcInstInfo *Udma_chGetUtcInst(Udma_DrvHandle drvHandle,
             break;
         }
     }
-#endif
 
     return (utcInfo);
 }
+#endif
 
 int32_t Udma_chGetStats(Udma_ChHandle chHandle, Udma_ChStats *chStats)
 {
@@ -1662,9 +1699,11 @@ static int32_t Udma_chAllocResource(Udma_ChHandle chHandle)
 {
     int32_t                 retVal = UDMA_SOK, tempRetVal;
     Udma_DrvHandle          drvHandle;
-    uint32_t                utcChNum;
     uint16_t                ringNum;
+#if (UDMA_NUM_UTC_INSTANCE > 0)
+    uint32_t                utcChNum;
     const Udma_UtcInstInfo *utcInfo;
+#endif
 
     drvHandle = chHandle->drvHandle;
 
@@ -1702,6 +1741,7 @@ static int32_t Udma_chAllocResource(Udma_ChHandle chHandle)
                 chHandle->rxChNum + drvHandle->udmapDestThreadOffset;
         }
     }
+#if (UDMA_NUM_UTC_INSTANCE > 0)
     else if((chHandle->chType & UDMA_CH_FLAG_UTC) == UDMA_CH_FLAG_UTC)
     {
         utcInfo = chHandle->utcInfo;
@@ -1729,6 +1769,7 @@ static int32_t Udma_chAllocResource(Udma_ChHandle chHandle)
             }
         }
     }
+#endif
     else
     {
         /* Allocate UDMAP for PDMA channels */
@@ -2013,12 +2054,14 @@ static int32_t Udma_chFreeResource(Udma_ChHandle chHandle)
         chHandle->defaultFlowObj.flowInitDone = UDMA_DEINIT_DONE;
         chHandle->defaultFlow                 = (Udma_FlowHandle) NULL_PTR;
     }
+#if (UDMA_NUM_UTC_INSTANCE > 0)
     if(UDMA_DMA_CH_INVALID != chHandle->extChNum)
     {
         /* External channel free */
         Udma_rmFreeExtCh(chHandle->extChNum, drvHandle, chHandle->utcInfo);
         chHandle->extChNum = UDMA_DMA_CH_INVALID;
     }
+#endif
     chHandle->pdmaChNum = UDMA_DMA_CH_INVALID;
     chHandle->peerThreadId = UDMA_THREAD_ID_INVALID;
 
@@ -2101,13 +2144,14 @@ static int32_t Udma_chUnpair(Udma_ChHandle chHandle)
 {
     int32_t         retVal = UDMA_SOK;
     Udma_DrvHandle  drvHandle;
-    uint32_t        dstThreadId;
     struct tisci_msg_rm_psil_unpair_req rmUnpairReq;
 
     drvHandle = chHandle->drvHandle;
 
     if((chHandle->chType & UDMA_CH_FLAG_UTC) == UDMA_CH_FLAG_UTC)
     {
+#if (UDMA_NUM_UTC_INSTANCE > 0)
+        uint32_t        dstThreadId;
         if(CSL_DRU_OWNER_UDMAC_TR == chHandle->utcPrms.druOwner)
         {
             /* For UTC, destination thread disable should be done */
@@ -2125,6 +2169,10 @@ static int32_t Udma_chUnpair(Udma_ChHandle chHandle)
                     "[Error] PSI UTC destination thread disable failed!!!\n");
             }
         }
+#else
+        retVal = UDMA_EFAIL;
+        Udma_printf(drvHandle, "[Error] UTC Not supported!!!\n");
+#endif
     }
     else
     {
@@ -2162,11 +2210,13 @@ static int32_t Udma_chEnableLocal(Udma_ChHandle chHandle)
 {
     int32_t                 retVal = UDMA_SOK;
     uint32_t                regVal;
-    uint32_t                utcChNum;
     Udma_DrvHandle          drvHandle;
-    const Udma_UtcInstInfo *utcInfo;
     CSL_UdmapRT             rtEnable;
+#if (UDMA_NUM_UTC_INSTANCE > 0)
+    uint32_t                utcChNum;
     uint32_t                srcThreadId;
+    const Udma_UtcInstInfo *utcInfo;
+#endif
 
     drvHandle = chHandle->drvHandle;
 
@@ -2209,6 +2259,7 @@ static int32_t Udma_chEnableLocal(Udma_ChHandle chHandle)
         CSL_REG32_WR(&chHandle->pRxRtRegs->PEER8, regVal);
     }
 
+#if (UDMA_NUM_UTC_INSTANCE > 0)
     if((chHandle->chType & UDMA_CH_FLAG_UTC) == UDMA_CH_FLAG_UTC)
     {
         utcInfo = chHandle->utcInfo;
@@ -2260,6 +2311,7 @@ static int32_t Udma_chEnableLocal(Udma_ChHandle chHandle)
                 &rtEnable);
         }
     }
+#endif
 
     return (retVal);
 }
@@ -2563,6 +2615,7 @@ static int32_t Udma_chDisableRxChan(Udma_ChHandle chHandle, uint32_t timeout)
     return (retVal);
 }
 
+#if (UDMA_NUM_UTC_INSTANCE > 0)
 static int32_t Udma_chDisableExtChan(Udma_ChHandle chHandle, uint32_t timeout)
 {
     int32_t                 retVal = UDMA_SOK;
@@ -2702,6 +2755,7 @@ static int32_t Udma_chDisableExtChan(Udma_ChHandle chHandle, uint32_t timeout)
 
     return (retVal);
 }
+#endif
 
 static uint32_t Udma_chGetTriggerEvent(Udma_DrvHandle drvHandle,
                                        Udma_ChHandle chHandle,
@@ -2749,6 +2803,7 @@ static uint32_t Udma_chGetTriggerEvent(Udma_DrvHandle drvHandle,
     return (triggerEvent);
 }
 
+#if (UDMA_NUM_UTC_INSTANCE > 0)
 static int32_t Udma_psilcfgSetRtEnable(Udma_DrvHandle drvHandle,
                                        uint32_t threadId,
                                        uint32_t bEnable)
@@ -2856,3 +2911,4 @@ static int32_t Udma_psilcfgRead(Udma_DrvHandle drvHandle,
 
     return (retVal);
 }
+#endif
index 34a42e9fe6b114170d1da5c38cc44eb94dd50a61..88392d129e84fa93080c680a4ea5aaaf703e1789 100755 (executable)
@@ -1169,11 +1169,8 @@ static int32_t Udma_eventProgramSteering(Udma_DrvHandle drvHandle,
                                          Udma_EventHandle eventHandle)
 {
     int32_t                 retVal = UDMA_SOK;
-    uint32_t                evtNum;
     Udma_ChHandle           chHandle;
     Udma_EventPrms         *eventPrms;
-    uint32_t                utcChNum;
-    const Udma_UtcInstInfo *utcInfo;
 
     Udma_assert(drvHandle, eventHandle != NULL_PTR);
     eventPrms = &eventHandle->eventPrms;
@@ -1183,7 +1180,6 @@ static int32_t Udma_eventProgramSteering(Udma_DrvHandle drvHandle,
         Udma_assert(drvHandle, eventPrms->chHandle != NULL_PTR);
         chHandle = eventPrms->chHandle;
 
-        evtNum = Udma_eventGetId(eventHandle);
         if(((chHandle->chType & UDMA_CH_FLAG_BLK_COPY) == UDMA_CH_FLAG_BLK_COPY) ||
             ((chHandle->chType & UDMA_CH_FLAG_RX) == UDMA_CH_FLAG_RX))
         {
@@ -1195,6 +1191,12 @@ static int32_t Udma_eventProgramSteering(Udma_DrvHandle drvHandle,
         }
         else
         {
+#if (UDMA_NUM_UTC_INSTANCE > 0)
+            uint32_t                evtNum;
+            uint32_t                utcChNum;
+            const Udma_UtcInstInfo *utcInfo;
+
+            evtNum = Udma_eventGetId(eventHandle);
             utcInfo = chHandle->utcInfo;
             Udma_assert(drvHandle, utcInfo != NULL_PTR);
             if(UDMA_UTC_TYPE_DRU == utcInfo->utcType)
@@ -1216,6 +1218,7 @@ static int32_t Udma_eventProgramSteering(Udma_DrvHandle drvHandle,
                 Udma_printf(drvHandle,
                     "[Error] TR events not possible in other external channels!!\n");
             }
+#endif
         }
 
         if(UDMA_SOK == retVal)
@@ -1232,11 +1235,8 @@ static void Udma_eventResetSteering(Udma_DrvHandle drvHandle,
                                     Udma_EventHandle eventHandle)
 {
     int32_t                 retVal = UDMA_SOK;
-    uint32_t                evtNum;
     Udma_ChHandle           chHandle;
     Udma_EventPrms         *eventPrms;
-    uint32_t                utcChNum;
-    const Udma_UtcInstInfo *utcInfo;
 
     Udma_assert(drvHandle, eventHandle != NULL_PTR);
     eventPrms = &eventHandle->eventPrms;
@@ -1246,7 +1246,6 @@ static void Udma_eventResetSteering(Udma_DrvHandle drvHandle,
         Udma_assert(drvHandle, eventPrms->chHandle != NULL_PTR);
         chHandle = eventPrms->chHandle;
 
-        evtNum = UDMA_EVENT_INVALID;
         if(((chHandle->chType & UDMA_CH_FLAG_BLK_COPY) == UDMA_CH_FLAG_BLK_COPY) ||
             ((chHandle->chType & UDMA_CH_FLAG_RX) == UDMA_CH_FLAG_RX))
         {
@@ -1258,6 +1257,12 @@ static void Udma_eventResetSteering(Udma_DrvHandle drvHandle,
         }
         else
         {
+#if (UDMA_NUM_UTC_INSTANCE > 0)
+            uint32_t                evtNum;
+            uint32_t                utcChNum;
+            const Udma_UtcInstInfo *utcInfo;
+
+            evtNum = UDMA_EVENT_INVALID;
             utcInfo = chHandle->utcInfo;
             Udma_assert(drvHandle, utcInfo != NULL_PTR);
             if(UDMA_UTC_TYPE_DRU == utcInfo->utcType)
@@ -1279,6 +1284,7 @@ static void Udma_eventResetSteering(Udma_DrvHandle drvHandle,
                 Udma_printf(drvHandle,
                     "[Error] TR events not possible in other external channels!!\n");
             }
+#endif
         }
 
         if(UDMA_SOK == retVal)
index 7c29d1f581036c8872ba6e5cb0e17bc393d977ee..40cee19f12c6a8c80de164d8e4edfdfa0b5c12bc 100644 (file)
@@ -90,8 +90,10 @@ void Udma_initDrvHandle(Udma_DrvHandle drvHandle);
 void UdmaRmInitPrms_init(uint32_t instId, Udma_RmInitPrms *rmInitPrms);
 
 /* Private APIs */
+#if (UDMA_NUM_UTC_INSTANCE > 0)
 const Udma_UtcInstInfo *Udma_chGetUtcInst(Udma_DrvHandle drvHandle,
                                           uint32_t utcId);
+#endif
 
 /**
  *  \brief Default RA memory fence API used for CSL-FL to perform cache ops
@@ -126,12 +128,14 @@ uint32_t Udma_rmAllocTxUhcCh(uint32_t preferredChNum, Udma_DrvHandle drvHandle);
 void Udma_rmFreeTxUhcCh(uint32_t chNum, Udma_DrvHandle drvHandle);
 uint32_t Udma_rmAllocRxUhcCh(uint32_t preferredChNum, Udma_DrvHandle drvHandle);
 void Udma_rmFreeRxUhcCh(uint32_t chNum, Udma_DrvHandle drvHandle);
+#if (UDMA_NUM_UTC_INSTANCE > 0)
 uint32_t Udma_rmAllocExtCh(uint32_t preferredChNum,
                            Udma_DrvHandle drvHandle,
                            const Udma_UtcInstInfo *utcInfo);
 void Udma_rmFreeExtCh(uint32_t chNum,
                       Udma_DrvHandle drvHandle,
                       const Udma_UtcInstInfo *utcInfo);
+#endif
 /* Ring RM APIs */
 uint16_t Udma_rmAllocFreeRing(Udma_DrvHandle drvHandle);
 void Udma_rmFreeFreeRing(uint16_t ringNum, Udma_DrvHandle drvHandle);
index c5e8d4cff8d97b064115144e9928da88c94ffa64..8f248c46081251d8c5a7be66ce038fa9079609a8 100755 (executable)
@@ -1043,12 +1043,12 @@ void Udma_rmFreeRxUhcCh(uint32_t chNum, Udma_DrvHandle drvHandle)
     return;
 }
 
+#if (UDMA_NUM_UTC_INSTANCE > 0)
 uint32_t Udma_rmAllocExtCh(uint32_t preferredChNum,
                            Udma_DrvHandle drvHandle,
                            const Udma_UtcInstInfo *utcInfo)
 {
     uint32_t            chNum = UDMA_DMA_CH_INVALID;
-#if (UDMA_NUM_UTC_INSTANCE > 0)
     uint32_t            i, offset, bitPos, bitMask;
     uint32_t            utcId;
     Udma_RmInitPrms    *rmInitPrms = &drvHandle->initPrms.rmInitPrms;
@@ -1103,7 +1103,6 @@ uint32_t Udma_rmAllocExtCh(uint32_t preferredChNum,
 
     Udma_assert(drvHandle, drvHandle->initPrms.osalPrms.unlockMutex != (Udma_OsalMutexUnlockFxn) NULL_PTR);
     drvHandle->initPrms.osalPrms.unlockMutex(drvHandle->rmLock);
-#endif
 
     return (chNum);
 }
@@ -1112,7 +1111,6 @@ void Udma_rmFreeExtCh(uint32_t chNum,
                       Udma_DrvHandle drvHandle,
                       const Udma_UtcInstInfo *utcInfo)
 {
-#if (UDMA_NUM_UTC_INSTANCE > 0)
     uint32_t            i, offset, bitPos, bitMask;
     uint32_t            utcId;
     Udma_RmInitPrms    *rmInitPrms = &drvHandle->initPrms.rmInitPrms;
@@ -1136,10 +1134,10 @@ void Udma_rmFreeExtCh(uint32_t chNum,
 
     Udma_assert(drvHandle, drvHandle->initPrms.osalPrms.unlockMutex != (Udma_OsalMutexUnlockFxn) NULL_PTR);
     drvHandle->initPrms.osalPrms.unlockMutex(drvHandle->rmLock);
-#endif
 
     return;
 }
+#endif
 
 uint16_t Udma_rmAllocFreeRing(Udma_DrvHandle drvHandle)
 {
index 224e3d82c5619b5728391fcade368940aa4d9b2f..b6cba2186c3f8fa1178a340947dd365f8a2605b2 100755 (executable)
@@ -76,9 +76,9 @@
 #include <ti/osal/osal.h>
 #include <ti/drv/sciclient/sciclient.h>
 
+#include <ti/drv/udma/soc/udma_soc.h>
 #include <ti/drv/udma/include/udma_cfg.h>
 #include <ti/drv/udma/include/udma_types.h>
-#include <ti/drv/udma/soc/udma_soc.h>
 #include <ti/drv/udma/include/udma_osal.h>
 #include <ti/drv/udma/include/udma_ring.h>
 #include <ti/drv/udma/include/udma_proxy.h>
@@ -86,7 +86,9 @@
 #include <ti/drv/udma/include/udma_event.h>
 #include <ti/drv/udma/include/udma_rm.h>
 #include <ti/drv/udma/include/udma_ch.h>
+#if (UDMA_NUM_UTC_INSTANCE > 0)
 #include <ti/drv/udma/include/udma_dru.h>
+#endif
 #include <ti/drv/udma/include/udma_utils.h>
 
 #ifdef __cplusplus
@@ -380,11 +382,13 @@ struct Udma_DrvObj
     /**< Proxy RM ID */
     uint16_t                devIdCore;
     /**< Core RM ID */
+#if (UDMA_NUM_UTC_INSTANCE > 0)
     uint32_t                druCoreId;
     /**< DRU core ID register to use for direct TR submission.
      *   Each CPU should have a unique submit register to avoid corrupting
      *   submit word when SW is running from multiple CPU at the same time.
      *   Refer \ref Udma_DruSubmitCoreId */
+#endif
 
     uint32_t                txChOffset;
     /**< TX channel offset. */
index 9d40827b434201a476cff7ca5f8dc3d323c556a9..9a753a264e66ec6d1659162c9c0912985c27823d 100644 (file)
@@ -95,7 +95,7 @@ endif
 export dmautils_CORE_DEPENDENCY = yes
 dmautils_PKG_LIST = dmautils
 dmautils_INCLUDE = $(dmautils_PATH)
-export dmautils_SOCLIST = $(drvudma_SOCLIST)
+export dmautils_SOCLIST = j721e
 export dmautils_$(SOC)_CORELIST = c7x_1 c7x-hostemu
 udma_LIB_LIST += dmautils
 
diff --git a/packages/ti/drv/udma/unit_test/udma_ut/baremetal/j7200/linker_a72.lds b/packages/ti/drv/udma/unit_test/udma_ut/baremetal/j7200/linker_a72.lds
new file mode 100755 (executable)
index 0000000..19f4ad2
--- /dev/null
@@ -0,0 +1,214 @@
+__STACK_SIZE = 0x20000;
+__TI_STACK_SIZE = __STACK_SIZE;
+
+MEMORY
+{
+    OCMCRAM     : ORIGIN = 0x000041C00000, LENGTH = 0x00080000                         /* MCUSS-OCMC RAM - 512KB                                       */
+
+
+    DDR_MPU1   (RWX)   : ORIGIN = 0x80000000, LENGTH = 0x08000000
+    DDR_IPC     (RWX)          : ORIGIN = 0x90000000, LENGTH = 0x02000000
+
+    /* j721e MCMS3 locations                                                  */
+    /* j721e Reserved Memory for ARM Trusted Firmware                        */
+    MSMC3_ARM_FW   (RWIX)   : ORIGIN = 0x000070000000, LENGTH = 0x40000         /* 256KB */
+    BOOTVECTOR              : ORIGIN = 0x000070040000, LENGTH = 0x1000          /* 4KB */
+    BOOTVECTOR_EL3          : ORIGIN = 0x000070041000, LENGTH = 0x1000          /* 4KB */
+    MSMC_MPU1  (RWX)       : ORIGIN = 0x000070042000, LENGTH = 0x7AE000        /* 7864KB */
+    /* j721e Reserved Memory for DMSC Firmware                                */
+    MSMC3_DMSC_FW  (RWIX)   : ORIGIN = 0x0000707F0000, LENGTH = 0x10000         /* 64KB */
+}
+REGION_ALIAS("REGION_TEXT_EL3", DDR_MPU1);
+REGION_ALIAS("REGION_TEXT", DDR_MPU1);
+REGION_ALIAS("REGION_BSS", DDR_MPU1);
+REGION_ALIAS("REGION_DATA", DDR_MPU1);
+REGION_ALIAS("REGION_STACK", DDR_MPU1);
+REGION_ALIAS("REGION_HEAP", DDR_MPU1);
+REGION_ALIAS("REGION_ARM_EXIDX", DDR_MPU1);
+REGION_ALIAS("REGION_ARM_EXTAB", DDR_MPU1);
+REGION_ALIAS("REGION_TEXT_STARTUP", DDR_MPU1);
+REGION_ALIAS("REGION_DATA_BUFFER", DDR_MPU1);
+REGION_ALIAS("IPC_DATA_BUFFER_1", DDR_MPU1);
+REGION_ALIAS("REGION_UDMA_BUFFER_MSMC", MSMC_MPU1);
+REGION_ALIAS("REGION_UDMA_BUFFER_DDR", DDR_MPU1);
+REGION_ALIAS("REGION_UDMA_BUFFER_OSPI", DDR_MPU1);
+REGION_ALIAS("REGION_UDMA_BUFFER_INTERNAL", DDR_MPU1);
+
+
+SECTIONS {
+
+    .vecs : {
+        *(.vecs)
+    } > BOOTVECTOR AT> BOOTVECTOR
+
+    .vectors : {
+        *(.vectors)
+    } > BOOTVECTOR_EL3 AT> BOOTVECTOR_EL3
+       .text.el3 : {
+           *(.text.el3)
+                /* Ensure 8-byte alignment for descriptors and ensure inclusion */
+        . = ALIGN(8);
+        __RT_SVC_DESCS_START__ = .;
+        KEEP(*(rt_svc_descs))
+        __RT_SVC_DESCS_END__ = .;
+    } > REGION_TEXT_EL3 AT> REGION_TEXT_EL3
+
+    .text.csl_a72_startup : {
+        *(.text.csl_a72_startup)
+               *(.Entry)
+    } > REGION_TEXT_STARTUP AT> REGION_TEXT_STARTUP
+
+    .text : {
+        CREATE_OBJECT_SYMBOLS
+        *(.text)
+        *(.text.*)
+        . = ALIGN(0x8);
+        KEEP (*(.ctors))
+        . = ALIGN(0x4);
+        KEEP (*(.dtors))
+        . = ALIGN(0x8);
+        __init_array_start = .;
+        KEEP (*(.init_array*))
+        __init_array_end = .;
+        *(.init)
+        *(.fini*)
+    } > REGION_TEXT AT> REGION_TEXT
+
+    PROVIDE (__etext = .);
+    PROVIDE (_etext = .);
+    PROVIDE (etext = .);
+
+    .rodata : {
+        *(.rodata)
+        *(.rodata*)
+    } > REGION_TEXT AT> REGION_TEXT
+
+    .data_buffer : ALIGN (8) {
+        __data_buffer_load__ = LOADADDR (.data_buffer);
+        __data_buffer_start__ = .;
+        *(.data_buffer)
+        *(.data_buffer*)
+        . = ALIGN (8);
+        __data_buffer_end__ = .;
+    } > REGION_DATA_BUFFER AT> REGION_DATA_BUFFER
+
+    .data : ALIGN (8) {
+        __data_load__ = LOADADDR (.data);
+        __data_start__ = .;
+        *(.data)
+        *(.data*)
+        . = ALIGN (8);
+        __data_end__ = .;
+    } > REGION_DATA AT> REGION_TEXT
+
+    .ARM.exidx : {
+        __exidx_start = .;
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+        __exidx_end = .;
+    } > REGION_ARM_EXIDX AT> REGION_ARM_EXIDX
+
+    .ARM.extab : {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    } > REGION_ARM_EXTAB AT> REGION_ARM_EXTAB
+
+    .bss:extMemCache:ramdisk : {
+    } > DDR_MPU1  /* MSMC_MPU1 */
+
+    /* USB or any other LLD buffer for benchmarking */
+    .benchmark_buffer (NOLOAD) : ALIGN (32) {
+    } > DDR_MPU1
+
+    .bss:frameBuffer (NOLOAD) : ALIGN (32) {
+    } > DDR_MPU1
+
+    .udma_buffer_msmc (NOLOAD) : ALIGN (128) {
+    } > REGION_UDMA_BUFFER_MSMC
+
+    .udma_buffer_ddr (NOLOAD) : ALIGN (128) {
+    } > REGION_UDMA_BUFFER_DDR
+
+    .udma_buffer_internal (NOLOAD) : ALIGN (128) {
+    } > REGION_UDMA_BUFFER_INTERNAL
+
+    .udma_buffer_ospi (NOLOAD) : ALIGN (128) {
+    } > REGION_UDMA_BUFFER_OSPI
+
+    ipc_data_buffer (NOLOAD) : ALIGN (32) {
+    } > IPC_DATA_BUFFER_1
+
+    /* For NDK packet memory, we need to map this sections before .bss*/
+    .bss:NDK_PACKETMEM (NOLOAD) : ALIGN (128) {} > DDR_MPU1
+    .bss:NDK_MMBUFFER  (NOLOAD) : ALIGN (128) {} > DDR_MPU1
+
+    .bss : {
+        __bss_start__ = .;
+        *(.shbss)
+        *(.bss)
+        *(.bss.*)
+        . = ALIGN (8);
+        __bss_end__ = .;
+        . = ALIGN (8);
+        *(COMMON)
+    } > REGION_BSS AT> REGION_BSS
+
+    .heap : {
+        __heap_start__ = .;
+        end = __heap_start__;
+        _end = end;
+        __end = end;
+        KEEP(*(.heap))
+        __heap_end__ = .;
+        __HeapLimit = __heap_end__;
+    } > REGION_HEAP AT> REGION_HEAP
+
+    .stack (NOLOAD) : ALIGN(16) {
+        _stack = .;
+        __stack = .;
+        KEEP(*(.stack))
+    } > REGION_STACK AT> REGION_STACK
+
+       __TI_STACK_BASE = __stack;
+
+    /* Stabs debugging sections.  */
+    .stab          0 : { *(.stab) }
+    .stabstr       0 : { *(.stabstr) }
+    .stab.excl     0 : { *(.stab.excl) }
+    .stab.exclstr  0 : { *(.stab.exclstr) }
+    .stab.index    0 : { *(.stab.index) }
+    .stab.indexstr 0 : { *(.stab.indexstr) }
+    .comment       0 : { *(.comment) }
+    /*
+     * DWARF debug sections.
+     * Symbols in the DWARF debugging sections are relative to the beginning
+     * of the section so we begin them at 0.
+     */
+    /* DWARF 1 */
+    .debug         0 : { *(.debug) }
+    .line          0 : { *(.line) }
+    /* GNU DWARF 1 extensions */
+    .debug_srcinfo  0 : { *(.debug_srcinfo) }
+    .debug_sfnames  0 : { *(.debug_sfnames) }
+    /* DWARF 1.1 and DWARF 2 */
+    .debug_aranges  0 : { *(.debug_aranges) }
+    .debug_pubnames 0 : { *(.debug_pubnames) }
+    /* DWARF 2 */
+    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+    .debug_abbrev   0 : { *(.debug_abbrev) }
+    .debug_line     0 : { *(.debug_line .debug_line.* .debug_line_end ) }
+    .debug_frame    0 : { *(.debug_frame) }
+    .debug_str      0 : { *(.debug_str) }
+    .debug_loc      0 : { *(.debug_loc) }
+    .debug_macinfo  0 : { *(.debug_macinfo) }
+    /* SGI/MIPS DWARF 2 extensions */
+    .debug_weaknames 0 : { *(.debug_weaknames) }
+    .debug_funcnames 0 : { *(.debug_funcnames) }
+    .debug_typenames 0 : { *(.debug_typenames) }
+    .debug_varnames  0 : { *(.debug_varnames) }
+    /* DWARF 3 */
+    .debug_pubtypes 0 : { *(.debug_pubtypes) }
+    .debug_ranges   0 : { *(.debug_ranges) }
+    /* DWARF Extension.  */
+    .debug_macro    0 : { *(.debug_macro) }
+    .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }
+    /DISCARD/ : { *(.note.GNU-stack) *(.gnu_debuglink) *(.gnu.lto_*) }
+}
diff --git a/packages/ti/drv/udma/unit_test/udma_ut/baremetal/j7200/linker_r5f.lds b/packages/ti/drv/udma/unit_test/udma_ut/baremetal/j7200/linker_r5f.lds
new file mode 100644 (file)
index 0000000..fea3c2f
--- /dev/null
@@ -0,0 +1,102 @@
+/* Linker Settings */
+--retain="*(.bootCode)"
+--retain="*(.startupCode)"
+--retain="*(.startupData)"
+--retain="*(.intvecs)"
+--retain="*(.intc_text)"
+--retain="*(.rstvectors)"
+--retain="*(.irqStack)"
+--retain="*(.fiqStack)"
+--retain="*(.abortStack)"
+--retain="*(.undStack)"
+--retain="*(.svcStack)"
+--fill_value=0
+--stack_size=0x2000
+--heap_size=0x1000
+--entry_point=_resetvectors     /* Default C RTS boot.asm   */
+
+-stack  0x2000                              /* SOFTWARE STACK SIZE           */
+-heap   0x2000                              /* HEAP AREA SIZE                */
+
+/* Stack Sizes for various modes */
+__IRQ_STACK_SIZE = 0x1000;
+__FIQ_STACK_SIZE = 0x1000;
+__ABORT_STACK_SIZE = 0x1000;
+__UND_STACK_SIZE = 0x1000;
+__SVC_STACK_SIZE = 0x1000;
+
+/* Memory Map */
+MEMORY
+{
+    VECTORS (X)             : origin=0x41C7F000 length=0x1000
+    /*  Reset Vectors base address(RESET_VECTORS) should be 64 bytes aligned  */
+    RESET_VECTORS (X)       : origin=0x41C00000 length=0x100
+    /* MCU0_R5F_0 local view */
+    MCU0_R5F_TCMA_SBL_RSVD (X)  : origin=0x0        length=0x100
+    MCU0_R5F_TCMA (X)       : origin=0x100      length=0x8000 - 0x100
+    MCU0_R5F_TCMB0 (RWIX)   : origin=0x41010000 length=0x8000
+
+    /* MCU0_R5F_1 SoC view */
+    MCU0_R5F1_ATCM (RWIX)   : origin=0x41400000 length=0x8000
+    MCU0_R5F1_BTCM (RWIX)   : origin=0x41410000 length=0x8000
+
+    /* MCU0 share locations */
+    OCMRAM  (RWIX)          : origin=0x41C00100 length=0x80000 - 0x1100      /* ~510KB */
+
+    /* j721e MCMS3 locations */
+    /* j721e Reserved Memory for ARM Trusted Firmware */
+    MSMC3_ARM_FW   (RWIX)   : origin=0x70000000 length=0x40000         /* 256KB */
+    MSMC3   (RWIX)          : origin=0x70040000 length=0x7B0000        /* 8MB - 320KB */
+    /* j721e Reserved Memory for DMSC Firmware */
+    MSMC3_DMSC_FW  (RWIX)   : origin=0x707F0000 length=0x10000         /* 64KB */
+
+    DDR0    (RWIX)          : origin=0x80000000 length=0x80000000      /* 2GB */
+}
+
+/* Section Configuration */
+SECTIONS
+{
+    /* 'intvecs' and 'intc_text' sections shall be placed within */
+    /* a range of +\- 16 MB */
+    .intvecs       : {} palign(8)      > VECTORS
+    .intc_text     : {} palign(8)      > VECTORS
+    .rstvectors    : {} palign(8)      > RESET_VECTORS
+    .bootCode      : {} palign(8)      > MSMC3
+    .startupCode   : {} palign(8)      > MSMC3
+    .startupData   : {} palign(8)      > MSMC3, type = NOINIT
+    .text          : {} palign(8)      > DDR0
+    .const         : {} palign(8)      > DDR0
+    .cinit         : {} palign(8)      > DDR0
+    .pinit         : {} palign(8)      > DDR0
+    .bss           : {} align(4)       > DDR0
+    .far           : {} align(4)       > DDR0
+    .data          : {} palign(128)    > DDR0
+    .boardcfg_data : {} palign(128)    > MSMC3
+    .sysmem        : {}                > DDR0
+    .data_buffer   : {} palign(128)    > DDR0
+
+    .udma_buffer_ddr                        : {} palign(128) > DDR0
+    .udma_buffer_ospi                       : {} palign(128) > DDR0
+    .udma_buffer_msmc                       : {} palign(128) > MSMC3
+    .udma_buffer_internal                   : {} palign(128) > OCMRAM
+
+    /* USB or any other LLD buffer for benchmarking */
+    .benchmark_buffer (NOLOAD) {} ALIGN (8) > DDR0
+
+    .stack      : {} align(4)       > DDR0  (HIGH)
+    .irqStack   : {. = . + __IRQ_STACK_SIZE;} align(4)      > DDR0  (HIGH)
+    RUN_START(__IRQ_STACK_START)
+    RUN_END(__IRQ_STACK_END)
+    .fiqStack   : {. = . + __FIQ_STACK_SIZE;} align(4)      > DDR0  (HIGH)
+    RUN_START(__FIQ_STACK_START)
+    RUN_END(__FIQ_STACK_END)
+    .abortStack : {. = . + __ABORT_STACK_SIZE;} align(4)    > DDR0  (HIGH)
+    RUN_START(__ABORT_STACK_START)
+    RUN_END(__ABORT_STACK_END)
+    .undStack   : {. = . + __UND_STACK_SIZE;} align(4)      > DDR0  (HIGH)
+    RUN_START(__UND_STACK_START)
+    RUN_END(__UND_STACK_END)
+    .svcStack   : {. = . + __SVC_STACK_SIZE;} align(4)      > DDR0  (HIGH)
+    RUN_START(__SVC_STACK_START)
+    RUN_END(__SVC_STACK_END)
+}
diff --git a/packages/ti/drv/udma/unit_test/udma_ut/rtos/j7200/linker_mcu1_0.lds b/packages/ti/drv/udma/unit_test/udma_ut/rtos/j7200/linker_mcu1_0.lds
new file mode 100644 (file)
index 0000000..7992268
--- /dev/null
@@ -0,0 +1,43 @@
+/* linker options */
+--fill_value=0
+--stack_size=0x2000
+--heap_size=0x1000
+
+-e __VECS_ENTRY_POINT
+
+MEMORY
+{
+    R5F_TCMA_SBL_RSVD(X): ORIGIN = 0x00000000, LENGTH = 0x100
+    RESET_VECTORS(X)    : ORIGIN = 0x41C40000, LENGTH = 0x100
+    R5F_TCMB0   (RWIX)  : ORIGIN = 0x41010000, LENGTH = 0x00008000  /*  32 KB */
+    DDR0        (RWIX)  : ORIGIN = 0xA0000000, LENGTH = 0x08000000  /* 128 MB per core */
+    OCMRAM      (RWIX)  : ORIGIN = 0x41C10000, LENGTH = 0x00008000  /*  32 KB per core */
+    MSMC3       (RWIX)  : ORIGIN = 0x70100000, LENGTH = 0x00080000  /* 512 KB per core */
+}
+
+SECTIONS
+{
+    .vecs       : {
+        __VECS_ENTRY_POINT = .;
+    }                                            palign(8)   > RESET_VECTORS
+    .text_boot {
+        *boot.aer5f*<*boot.o*>(.text)
+     }                                           palign(8)   > R5F_TCMB0
+    .text:xdc_runtime_Startup_reset__I      : {} palign(8)   > R5F_TCMB0
+    .text:ti_sysbios_family_arm_v7r_Cache*  : {} palign(8)   > R5F_TCMB0
+    .text:ti_sysbios_family_arm_MPU*        : {} palign(8)   > R5F_TCMB0
+
+    .text                                   : {} palign(8)   > DDR0
+    .cinit                                  : {} palign(8)   > DDR0
+    .bss                                    : {} align(8)    > DDR0
+    .const                                  : {} palign(8)   > DDR0
+    .data                                   : {} palign(128) > DDR0
+    .sysmem                                 : {} align(8)    > DDR0
+    .stack                                  : {} align(4)    > DDR0
+    .data_buffer                            : {} palign(128) > DDR0
+
+    .udma_buffer_ddr                        : {} palign(128) > DDR0
+    .udma_buffer_ospi                       : {} palign(128) > DDR0
+    .udma_buffer_msmc                       : {} palign(128) > MSMC3
+    .udma_buffer_internal                   : {} palign(128) > OCMRAM
+}
diff --git a/packages/ti/drv/udma/unit_test/udma_ut/rtos/j7200/linker_mcu1_1.lds b/packages/ti/drv/udma/unit_test/udma_ut/rtos/j7200/linker_mcu1_1.lds
new file mode 100644 (file)
index 0000000..ee03e05
--- /dev/null
@@ -0,0 +1,43 @@
+/* linker options */
+--fill_value=0
+--stack_size=0x2000
+--heap_size=0x1000
+
+-e __VECS_ENTRY_POINT
+
+MEMORY
+{
+    R5F_TCMA_SBL_RSVD(X): ORIGIN = 0x00000000, LENGTH = 0x100
+    RESET_VECTORS(X)    : ORIGIN = 0x41C41000, LENGTH = 0x100
+    R5F_TCMB0   (RWIX)  : ORIGIN = 0x41010000, LENGTH = 0x00008000  /*  32 KB */
+    DDR0        (RWIX)  : ORIGIN = 0xD0000000, LENGTH = 0x08000000  /* 128 MB per core */
+    OCMRAM      (RWIX)  : ORIGIN = 0x41C18000, LENGTH = 0x00008000  /*  32 KB per core */
+    MSMC3       (RWIX)  : ORIGIN = 0x70180000, LENGTH = 0x00080000  /* 512 KB per core */
+}
+
+SECTIONS
+{
+    .vecs       : {
+        __VECS_ENTRY_POINT = .;
+    }                                            palign(8)   > RESET_VECTORS
+    .text_boot {
+        *boot.aer5f*<*boot.o*>(.text)
+     }                                           palign(8)   > R5F_TCMB0
+    .text:xdc_runtime_Startup_reset__I      : {} palign(8)   > R5F_TCMB0
+    .text:ti_sysbios_family_arm_v7r_Cache*  : {} palign(8)   > R5F_TCMB0
+    .text:ti_sysbios_family_arm_MPU*        : {} palign(8)   > R5F_TCMB0
+
+    .text                                   : {} palign(8)   > DDR0
+    .cinit                                  : {} palign(8)   > DDR0
+    .bss                                    : {} align(8)    > DDR0
+    .const                                  : {} palign(8)   > DDR0
+    .data                                   : {} palign(128) > DDR0
+    .sysmem                                 : {} align(8)    > DDR0
+    .stack                                  : {} align(4)    > DDR0
+    .data_buffer                            : {} palign(128) > DDR0
+
+    .udma_buffer_ddr                        : {} palign(128) > DDR0
+    .udma_buffer_ospi                       : {} palign(128) > DDR0
+    .udma_buffer_msmc                       : {} palign(128) > MSMC3
+    .udma_buffer_internal                   : {} palign(128) > OCMRAM
+}
diff --git a/packages/ti/drv/udma/unit_test/udma_ut/rtos/j7200/linker_mcu2_0.lds b/packages/ti/drv/udma/unit_test/udma_ut/rtos/j7200/linker_mcu2_0.lds
new file mode 100644 (file)
index 0000000..ed49586
--- /dev/null
@@ -0,0 +1,43 @@
+/* linker options */
+--fill_value=0
+--stack_size=0x2000
+--heap_size=0x1000
+
+-e __VECS_ENTRY_POINT
+
+MEMORY
+{
+    R5F_TCMA_SBL_RSVD(X): ORIGIN = 0x00000000, LENGTH = 0x100
+    RESET_VECTORS(X)    : ORIGIN = 0x41C42000, LENGTH = 0x100
+    R5F_TCMB0   (RWIX)  : ORIGIN = 0x41010000, LENGTH = 0x00008000  /*  32 KB */
+    DDR0        (RWIX)  : ORIGIN = 0xB0000000, LENGTH = 0x08000000  /* 128 MB per core */
+    OCMRAM      (RWIX)  : ORIGIN = 0x41C20000, LENGTH = 0x00008000  /*  32 KB per core */
+    MSMC3       (RWIX)  : ORIGIN = 0x70200000, LENGTH = 0x00080000  /* 512 KB per core */
+}
+
+SECTIONS
+{
+    .vecs       : {
+        __VECS_ENTRY_POINT = .;
+    }                                            palign(8)   > RESET_VECTORS
+    .text_boot {
+        *boot.aer5f*<*boot.o*>(.text)
+     }                                           palign(8)   > R5F_TCMB0
+    .text:xdc_runtime_Startup_reset__I      : {} palign(8)   > R5F_TCMB0
+    .text:ti_sysbios_family_arm_v7r_Cache*  : {} palign(8)   > R5F_TCMB0
+    .text:ti_sysbios_family_arm_MPU*        : {} palign(8)   > R5F_TCMB0
+
+    .text                                   : {} palign(8)   > DDR0
+    .cinit                                  : {} palign(8)   > DDR0
+    .bss                                    : {} align(8)    > DDR0
+    .const                                  : {} palign(8)   > DDR0
+    .data                                   : {} palign(128) > DDR0
+    .sysmem                                 : {} align(8)    > DDR0
+    .stack                                  : {} align(4)    > DDR0
+    .data_buffer                            : {} palign(128) > DDR0
+
+    .udma_buffer_ddr                        : {} palign(128) > DDR0
+    .udma_buffer_ospi                       : {} palign(128) > DDR0
+    .udma_buffer_msmc                       : {} palign(128) > MSMC3
+    .udma_buffer_internal                   : {} palign(128) > OCMRAM
+}
diff --git a/packages/ti/drv/udma/unit_test/udma_ut/rtos/j7200/linker_mcu2_1.lds b/packages/ti/drv/udma/unit_test/udma_ut/rtos/j7200/linker_mcu2_1.lds
new file mode 100644 (file)
index 0000000..fc9b252
--- /dev/null
@@ -0,0 +1,43 @@
+/* linker options */
+--fill_value=0
+--stack_size=0x2000
+--heap_size=0x1000
+
+-e __VECS_ENTRY_POINT
+
+MEMORY
+{
+    R5F_TCMA_SBL_RSVD(X): ORIGIN = 0x00000000, LENGTH = 0x100
+    RESET_VECTORS(X)    : ORIGIN = 0x41C43000, LENGTH = 0x100
+    R5F_TCMB0   (RWIX)  : ORIGIN = 0x41010000, LENGTH = 0x00008000  /*  32 KB */
+    DDR0        (RWIX)  : ORIGIN = 0xB8000000, LENGTH = 0x08000000  /* 128 MB per core */
+    OCMRAM      (RWIX)  : ORIGIN = 0x41C28000, LENGTH = 0x00008000  /*  32 KB per core */
+    MSMC3       (RWIX)  : ORIGIN = 0x70280000, LENGTH = 0x00080000  /* 512 KB per core */
+}
+
+SECTIONS
+{
+    .vecs       : {
+        __VECS_ENTRY_POINT = .;
+    }                                            palign(8)   > RESET_VECTORS
+    .text_boot {
+        *boot.aer5f*<*boot.o*>(.text)
+     }                                           palign(8)   > R5F_TCMB0
+    .text:xdc_runtime_Startup_reset__I      : {} palign(8)   > R5F_TCMB0
+    .text:ti_sysbios_family_arm_v7r_Cache*  : {} palign(8)   > R5F_TCMB0
+    .text:ti_sysbios_family_arm_MPU*        : {} palign(8)   > R5F_TCMB0
+
+    .text                                   : {} palign(8)   > DDR0
+    .cinit                                  : {} palign(8)   > DDR0
+    .bss                                    : {} align(8)    > DDR0
+    .const                                  : {} palign(8)   > DDR0
+    .data                                   : {} palign(128) > DDR0
+    .sysmem                                 : {} align(8)    > DDR0
+    .stack                                  : {} align(4)    > DDR0
+    .data_buffer                            : {} palign(128) > DDR0
+
+    .udma_buffer_ddr                        : {} palign(128) > DDR0
+    .udma_buffer_ospi                       : {} palign(128) > DDR0
+    .udma_buffer_msmc                       : {} palign(128) > MSMC3
+    .udma_buffer_internal                   : {} palign(128) > OCMRAM
+}
diff --git a/packages/ti/drv/udma/unit_test/udma_ut/rtos/j7200/linker_mpu1_0.lds b/packages/ti/drv/udma/unit_test/udma_ut/rtos/j7200/linker_mpu1_0.lds
new file mode 100644 (file)
index 0000000..33ad05d
--- /dev/null
@@ -0,0 +1,203 @@
+__STACK_SIZE = 0x20000;
+__TI_STACK_SIZE = __STACK_SIZE;
+
+MEMORY
+{
+    DDR_MPU1   (RWX)    : ORIGIN = 0x80000000, LENGTH = 0x08000000  /* 128 MB per core */
+    BOOTVECTOR          : ORIGIN = 0x70040000, LENGTH = 0x1000      /*   4 KB */
+    BOOTVECTOR_EL3      : ORIGIN = 0x70041000, LENGTH = 0x1000      /*   4 KB */
+    MSMC3       (RWIX)  : ORIGIN = 0x70080000, LENGTH = 0x00080000  /* 512 KB per core */
+}
+
+REGION_ALIAS("REGION_TEXT_EL3", DDR_MPU1);
+REGION_ALIAS("REGION_TEXT", DDR_MPU1);
+REGION_ALIAS("REGION_BSS", DDR_MPU1);
+REGION_ALIAS("REGION_DATA", DDR_MPU1);
+REGION_ALIAS("REGION_STACK", DDR_MPU1);
+REGION_ALIAS("REGION_HEAP", DDR_MPU1);
+REGION_ALIAS("REGION_ARM_EXIDX", DDR_MPU1);
+REGION_ALIAS("REGION_ARM_EXTAB", DDR_MPU1);
+REGION_ALIAS("REGION_TEXT_STARTUP", DDR_MPU1);
+REGION_ALIAS("REGION_DATA_BUFFER", DDR_MPU1);
+REGION_ALIAS("IPC_DATA_BUFFER_1", DDR_MPU1);
+REGION_ALIAS("REGION_UDMA_BUFFER_MSMC", MSMC3);
+REGION_ALIAS("REGION_UDMA_BUFFER_DDR", DDR_MPU1);
+REGION_ALIAS("REGION_UDMA_BUFFER_OSPI", DDR_MPU1);
+REGION_ALIAS("REGION_UDMA_BUFFER_INTERNAL", DDR_MPU1);
+
+SECTIONS {
+    .vecs : {
+        *(.vecs)
+    } > BOOTVECTOR AT> BOOTVECTOR
+
+    .vectors : {
+        *(.vectors)
+    } > BOOTVECTOR_EL3 AT> BOOTVECTOR_EL3
+    .text.el3 : {
+    *(.text.el3)
+    /* Ensure 8-byte alignment for descriptors and ensure inclusion */
+        . = ALIGN(8);
+        __RT_SVC_DESCS_START__ = .;
+        KEEP(*(rt_svc_descs))
+        __RT_SVC_DESCS_END__ = .;
+    } > REGION_TEXT_EL3 AT> REGION_TEXT_EL3
+
+    .text.csl_a72_startup : {
+        *(.text.csl_a72_startup)
+    *(.Entry)
+    } > REGION_TEXT_STARTUP AT> REGION_TEXT_STARTUP
+
+    .text : {
+        CREATE_OBJECT_SYMBOLS
+        *(.text)
+        *(.text.*)
+        . = ALIGN(0x8);
+        KEEP (*(.ctors))
+        . = ALIGN(0x4);
+        KEEP (*(.dtors))
+        . = ALIGN(0x8);
+        __init_array_start = .;
+        KEEP (*(.init_array*))
+        __init_array_end = .;
+        *(.init)
+        *(.fini*)
+    } > REGION_TEXT AT> REGION_TEXT
+
+    PROVIDE (__etext = .);
+    PROVIDE (_etext = .);
+    PROVIDE (etext = .);
+
+    .rodata : {
+        *(.rodata)
+        *(.rodata*)
+    } > REGION_TEXT AT> REGION_TEXT
+
+    .data_buffer : ALIGN (8) {
+        __data_buffer_load__ = LOADADDR (.data_buffer);
+        __data_buffer_start__ = .;
+        *(.data_buffer)
+        *(.data_buffer*)
+        . = ALIGN (8);
+        __data_buffer_end__ = .;
+    } > REGION_DATA_BUFFER AT> REGION_DATA_BUFFER
+
+    .data : ALIGN (8) {
+        __data_load__ = LOADADDR (.data);
+        __data_start__ = .;
+        *(.data)
+        *(.data*)
+        . = ALIGN (8);
+        __data_end__ = .;
+    } > REGION_DATA AT> REGION_TEXT
+
+    .ARM.exidx : {
+        __exidx_start = .;
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+        __exidx_end = .;
+    } > REGION_ARM_EXIDX AT> REGION_ARM_EXIDX
+
+    .ARM.extab : {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    } > REGION_ARM_EXTAB AT> REGION_ARM_EXTAB
+
+    .bss:extMemCache:ramdisk : {
+    } > DDR_MPU1
+
+    /* USB or any other LLD buffer for benchmarking */
+    .benchmark_buffer (NOLOAD) : ALIGN (32) {
+    } > DDR_MPU1
+
+    .bss:frameBuffer (NOLOAD) : ALIGN (32) {
+    } > DDR_MPU1
+
+    .udma_buffer_msmc (NOLOAD) : ALIGN (128) {
+    } > REGION_UDMA_BUFFER_MSMC
+
+    .udma_buffer_ddr (NOLOAD) : ALIGN (128) {
+    } > REGION_UDMA_BUFFER_DDR
+
+    .udma_buffer_internal (NOLOAD) : ALIGN (128) {
+    } > REGION_UDMA_BUFFER_INTERNAL
+
+    .udma_buffer_ospi (NOLOAD) : ALIGN (128) {
+    } > REGION_UDMA_BUFFER_OSPI
+
+    ipc_data_buffer (NOLOAD) : ALIGN (32) {
+    } > IPC_DATA_BUFFER_1
+
+    /* For NDK packet memory, we need to map this sections before .bss*/
+    .bss:NDK_PACKETMEM (NOLOAD) : ALIGN (128) {} > DDR_MPU1
+    .bss:NDK_MMBUFFER  (NOLOAD) : ALIGN (128) {} > DDR_MPU1
+
+    .bss : {
+        __bss_start__ = .;
+        *(.shbss)
+        *(.bss)
+        *(.bss.*)
+        . = ALIGN (8);
+        __bss_end__ = .;
+        . = ALIGN (8);
+        *(COMMON)
+    } > REGION_BSS AT> REGION_BSS
+
+    .heap : {
+        __heap_start__ = .;
+        end = __heap_start__;
+        _end = end;
+        __end = end;
+        KEEP(*(.heap))
+        __heap_end__ = .;
+        __HeapLimit = __heap_end__;
+    } > REGION_HEAP AT> REGION_HEAP
+
+    .stack (NOLOAD) : ALIGN(16) {
+        _stack = .;
+        __stack = .;
+        KEEP(*(.stack))
+    } > REGION_STACK AT> REGION_STACK
+
+    __TI_STACK_BASE = __stack;
+
+    /* Stabs debugging sections.  */
+    .stab          0 : { *(.stab) }
+    .stabstr       0 : { *(.stabstr) }
+    .stab.excl     0 : { *(.stab.excl) }
+    .stab.exclstr  0 : { *(.stab.exclstr) }
+    .stab.index    0 : { *(.stab.index) }
+    .stab.indexstr 0 : { *(.stab.indexstr) }
+    .comment       0 : { *(.comment) }
+    /*
+     * DWARF debug sections.
+     * Symbols in the DWARF debugging sections are relative to the beginning
+     * of the section so we begin them at 0.
+     */
+    /* DWARF 1 */
+    .debug         0 : { *(.debug) }
+    .line          0 : { *(.line) }
+    /* GNU DWARF 1 extensions */
+    .debug_srcinfo  0 : { *(.debug_srcinfo) }
+    .debug_sfnames  0 : { *(.debug_sfnames) }
+    /* DWARF 1.1 and DWARF 2 */
+    .debug_aranges  0 : { *(.debug_aranges) }
+    .debug_pubnames 0 : { *(.debug_pubnames) }
+    /* DWARF 2 */
+    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+    .debug_abbrev   0 : { *(.debug_abbrev) }
+    .debug_line     0 : { *(.debug_line .debug_line.* .debug_line_end ) }
+    .debug_frame    0 : { *(.debug_frame) }
+    .debug_str      0 : { *(.debug_str) }
+    .debug_loc      0 : { *(.debug_loc) }
+    .debug_macinfo  0 : { *(.debug_macinfo) }
+    /* SGI/MIPS DWARF 2 extensions */
+    .debug_weaknames 0 : { *(.debug_weaknames) }
+    .debug_funcnames 0 : { *(.debug_funcnames) }
+    .debug_typenames 0 : { *(.debug_typenames) }
+    .debug_varnames  0 : { *(.debug_varnames) }
+    /* DWARF 3 */
+    .debug_pubtypes 0 : { *(.debug_pubtypes) }
+    .debug_ranges   0 : { *(.debug_ranges) }
+    /* DWARF Extension.  */
+    .debug_macro    0 : { *(.debug_macro) }
+    .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }
+    /DISCARD/ : { *(.note.GNU-stack) *(.gnu_debuglink) *(.gnu.lto_*) }
+}
index fb4b8e135552a4d06e95f940d3a327c529d7a760..02b09ef3d09905332c184fe24e1e7e3c455b04f5 100644 (file)
@@ -82,29 +82,8 @@ int32_t udmaTestPrintPsilMacro(UdmaTestTaskObj *taskObj)
               " ------------------------------------\r\n");
 
     GT_2trace(taskObj->traceMask, GT_INFO1,
-              " MAIN_SAUL0_TX       : Thread Offset: 0x%0.4X, Thread Count: %d\r\n",
-              UDMA_PSIL_CH_MAIN_SAUL0_TX, UDMA_PSIL_CH_MAIN_SAUL0_TX_CNT);
-    GT_2trace(taskObj->traceMask, GT_INFO1,
-              " MAIN_ICSS_G0_TX     : Thread Offset: 0x%0.4X, Thread Count: %d\r\n",
-              UDMA_PSIL_CH_MAIN_ICSS_G0_TX, UDMA_PSIL_CH_MAIN_ICSS_G0_TX_CNT);
-    GT_2trace(taskObj->traceMask, GT_INFO1,
-              " MAIN_ICSS_G1_TX     : Thread Offset: 0x%0.4X, Thread Count: %d\r\n",
-              UDMA_PSIL_CH_MAIN_ICSS_G1_TX, UDMA_PSIL_CH_MAIN_ICSS_G1_TX_CNT);
-    GT_2trace(taskObj->traceMask, GT_INFO1,
-              " MAIN_VPAC_TC0_TX    : Thread Offset: 0x%0.4X, Thread Count: %d\r\n",
-              UDMA_PSIL_CH_MAIN_VPAC_TC0_TX, UDMA_PSIL_CH_MAIN_VPAC_TC0_TX_CNT);
-    GT_2trace(taskObj->traceMask, GT_INFO1,
-              " MAIN_VPAC_TC1_TX    : Thread Offset: 0x%0.4X, Thread Count: %d\r\n",
-              UDMA_PSIL_CH_MAIN_VPAC_TC1_TX, UDMA_PSIL_CH_MAIN_VPAC_TC1_TX_CNT);
-    GT_2trace(taskObj->traceMask, GT_INFO1,
-              " MAIN_DMPAC_TC0_TX   : Thread Offset: 0x%0.4X, Thread Count: %d\r\n",
-              UDMA_PSIL_CH_MAIN_DMPAC_TC0_TX, UDMA_PSIL_CH_MAIN_DMPAC_TC0_TX_CNT);
-    GT_2trace(taskObj->traceMask, GT_INFO1,
-              " MAIN_CSI_TX         : Thread Offset: 0x%0.4X, Thread Count: %d\r\n",
-              UDMA_PSIL_CH_MAIN_CSI_TX, UDMA_PSIL_CH_MAIN_CSI_TX_CNT);
-    GT_2trace(taskObj->traceMask, GT_INFO1,
-              " MAIN_CPSW9_TX       : Thread Offset: 0x%0.4X, Thread Count: %d\r\n",
-              UDMA_PSIL_CH_MAIN_CPSW9_TX, UDMA_PSIL_CH_MAIN_CPSW9_TX_CNT);
+              " MAIN_CPSW5_TX       : Thread Offset: 0x%0.4X, Thread Count: %d\r\n",
+              UDMA_PSIL_CH_MAIN_CPSW5_TX, UDMA_PSIL_CH_MAIN_CPSW5_TX_CNT);
     GT_2trace(taskObj->traceMask, GT_INFO1,
               " MCU_CPSW0_TX        : Thread Offset: 0x%0.4X, Thread Count: %d\r\n",
               UDMA_PSIL_CH_MCU_CPSW0_TX, UDMA_PSIL_CH_MCU_CPSW0_TX_CNT);
@@ -114,29 +93,8 @@ int32_t udmaTestPrintPsilMacro(UdmaTestTaskObj *taskObj)
     GT_0trace(taskObj->traceMask, GT_INFO1, " \r\n");
 
     GT_2trace(taskObj->traceMask, GT_INFO1,
-              " MAIN_SAUL0_RX       : Thread Offset: 0x%0.4X, Thread Count: %d\r\n",
-              UDMA_PSIL_CH_MAIN_SAUL0_RX, UDMA_PSIL_CH_MAIN_SAUL0_RX_CNT);
-    GT_2trace(taskObj->traceMask, GT_INFO1,
-              " MAIN_ICSS_G0_RX     : Thread Offset: 0x%0.4X, Thread Count: %d\r\n",
-              UDMA_PSIL_CH_MAIN_ICSS_G0_RX, UDMA_PSIL_CH_MAIN_ICSS_G0_RX_CNT);
-    GT_2trace(taskObj->traceMask, GT_INFO1,
-              " MAIN_ICSS_G1_RX     : Thread Offset: 0x%0.4X, Thread Count: %d\r\n",
-              UDMA_PSIL_CH_MAIN_ICSS_G1_RX, UDMA_PSIL_CH_MAIN_ICSS_G1_RX_CNT);
-    GT_2trace(taskObj->traceMask, GT_INFO1,
-              " MAIN_VPAC_TC0_RX    : Thread Offset: 0x%0.4X, Thread Count: %d\r\n",
-              UDMA_PSIL_CH_MAIN_VPAC_TC0_RX, UDMA_PSIL_CH_MAIN_VPAC_TC0_RX_CNT);
-    GT_2trace(taskObj->traceMask, GT_INFO1,
-              " MAIN_VPAC_TC1_RX    : Thread Offset: 0x%0.4X, Thread Count: %d\r\n",
-              UDMA_PSIL_CH_MAIN_VPAC_TC1_RX, UDMA_PSIL_CH_MAIN_VPAC_TC1_RX_CNT);
-    GT_2trace(taskObj->traceMask, GT_INFO1,
-              " MAIN_DMPAC_TC0_RX   : Thread Offset: 0x%0.4X, Thread Count: %d\r\n",
-              UDMA_PSIL_CH_MAIN_DMPAC_TC0_RX, UDMA_PSIL_CH_MAIN_DMPAC_TC0_RX_CNT);
-    GT_2trace(taskObj->traceMask, GT_INFO1,
-              " MAIN_CSI_RX         : Thread Offset: 0x%0.4X, Thread Count: %d\r\n",
-              UDMA_PSIL_CH_MAIN_CSI_RX, UDMA_PSIL_CH_MAIN_CSI_RX_CNT);
-    GT_2trace(taskObj->traceMask, GT_INFO1,
-              " MAIN_CPSW9_RX       : Thread Offset: 0x%0.4X, Thread Count: %d\r\n",
-              UDMA_PSIL_CH_MAIN_CPSW9_RX, UDMA_PSIL_CH_MAIN_CPSW9_RX_CNT);
+              " MAIN_CPSW5_RX       : Thread Offset: 0x%0.4X, Thread Count: %d\r\n",
+              UDMA_PSIL_CH_MAIN_CPSW5_RX, UDMA_PSIL_CH_MAIN_CPSW5_RX_CNT);
     GT_2trace(taskObj->traceMask, GT_INFO1,
               " MCU_CPSW0_RX        : Thread Offset: 0x%0.4X, Thread Count: %d\r\n",
               UDMA_PSIL_CH_MCU_CPSW0_RX, UDMA_PSIL_CH_MCU_CPSW0_RX_CNT);
@@ -166,57 +124,6 @@ int32_t udmaTestPrintPdmaMacro(UdmaTestTaskObj *taskObj)
     GT_1trace(taskObj->traceMask, GT_INFO1,
               " MAIN_MCASP2_TX              : Thread ID: 0x%0.4X\r\n",
               UDMA_PDMA_CH_MAIN_MCASP2_TX);
-    GT_1trace(taskObj->traceMask, GT_INFO1,
-              " MAIN_MCASP3_TX              : Thread ID: 0x%0.4X\r\n",
-              UDMA_PDMA_CH_MAIN_MCASP3_TX);
-    GT_1trace(taskObj->traceMask, GT_INFO1,
-              " MAIN_MCASP4_TX              : Thread ID: 0x%0.4X\r\n",
-              UDMA_PDMA_CH_MAIN_MCASP4_TX);
-    GT_1trace(taskObj->traceMask, GT_INFO1,
-              " MAIN_MCASP5_TX              : Thread ID: 0x%0.4X\r\n",
-              UDMA_PDMA_CH_MAIN_MCASP5_TX);
-    GT_1trace(taskObj->traceMask, GT_INFO1,
-              " MAIN_MCASP6_TX              : Thread ID: 0x%0.4X\r\n",
-              UDMA_PDMA_CH_MAIN_MCASP6_TX);
-    GT_1trace(taskObj->traceMask, GT_INFO1,
-              " MAIN_MCASP7_TX              : Thread ID: 0x%0.4X\r\n",
-              UDMA_PDMA_CH_MAIN_MCASP7_TX);
-    GT_1trace(taskObj->traceMask, GT_INFO1,
-              " MAIN_MCASP8_TX              : Thread ID: 0x%0.4X\r\n",
-              UDMA_PDMA_CH_MAIN_MCASP8_TX);
-    GT_1trace(taskObj->traceMask, GT_INFO1,
-              " MAIN_MCASP9_TX              : Thread ID: 0x%0.4X\r\n",
-              UDMA_PDMA_CH_MAIN_MCASP9_TX);
-    GT_1trace(taskObj->traceMask, GT_INFO1,
-              " MAIN_MCASP10_TX             : Thread ID: 0x%0.4X\r\n",
-              UDMA_PDMA_CH_MAIN_MCASP10_TX);
-    GT_1trace(taskObj->traceMask, GT_INFO1,
-              " MAIN_MCASP11_TX             : Thread ID: 0x%0.4X\r\n",
-              UDMA_PDMA_CH_MAIN_MCASP11_TX);
-    GT_1trace(taskObj->traceMask, GT_INFO1,
-              " MAIN_AASRC0_CH0_TX          : Thread ID: 0x%0.4X\r\n",
-              UDMA_PDMA_CH_MAIN_AASRC0_CH0_TX);
-    GT_1trace(taskObj->traceMask, GT_INFO1,
-              " MAIN_AASRC0_CH1_TX          : Thread ID: 0x%0.4X\r\n",
-              UDMA_PDMA_CH_MAIN_AASRC0_CH1_TX);
-    GT_1trace(taskObj->traceMask, GT_INFO1,
-              " MAIN_AASRC0_CH2_TX          : Thread ID: 0x%0.4X\r\n",
-              UDMA_PDMA_CH_MAIN_AASRC0_CH2_TX);
-    GT_1trace(taskObj->traceMask, GT_INFO1,
-              " MAIN_AASRC0_CH3_TX          : Thread ID: 0x%0.4X\r\n",
-              UDMA_PDMA_CH_MAIN_AASRC0_CH3_TX);
-    GT_1trace(taskObj->traceMask, GT_INFO1,
-              " MAIN_AASRC0_CH4_TX          : Thread ID: 0x%0.4X\r\n",
-              UDMA_PDMA_CH_MAIN_AASRC0_CH4_TX);
-    GT_1trace(taskObj->traceMask, GT_INFO1,
-              " MAIN_AASRC0_CH5_TX          : Thread ID: 0x%0.4X\r\n",
-              UDMA_PDMA_CH_MAIN_AASRC0_CH5_TX);
-    GT_1trace(taskObj->traceMask, GT_INFO1,
-              " MAIN_AASRC0_CH6_TX          : Thread ID: 0x%0.4X\r\n",
-              UDMA_PDMA_CH_MAIN_AASRC0_CH6_TX);
-    GT_1trace(taskObj->traceMask, GT_INFO1,
-              " MAIN_AASRC0_CH7_TX          : Thread ID: 0x%0.4X\r\n",
-              UDMA_PDMA_CH_MAIN_AASRC0_CH7_TX);
     GT_1trace(taskObj->traceMask, GT_INFO1,
               " MAIN_UART0_TX               : Thread ID: 0x%0.4X\r\n",
               UDMA_PDMA_CH_MAIN_UART0_TX);
@@ -469,6 +376,42 @@ int32_t udmaTestPrintPdmaMacro(UdmaTestTaskObj *taskObj)
     GT_1trace(taskObj->traceMask, GT_INFO1,
               " MAIN_MCAN13_CH2_TX          : Thread ID: 0x%0.4X\r\n",
               UDMA_PDMA_CH_MAIN_MCAN13_CH2_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN14_CH0_TX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN14_CH0_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN14_CH1_TX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN14_CH1_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN14_CH2_TX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN14_CH2_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN15_CH0_TX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN15_CH0_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN15_CH1_TX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN15_CH1_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN15_CH2_TX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN15_CH2_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN16_CH0_TX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN16_CH0_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN16_CH1_TX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN16_CH1_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN16_CH2_TX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN16_CH2_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN17_CH0_TX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN17_CH0_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN17_CH1_TX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN17_CH1_TX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN17_CH2_TX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN17_CH2_TX);
     GT_1trace(taskObj->traceMask, GT_INFO1,
               " MCU_MCSPI0_CH0_TX           : Thread ID: 0x%0.4X\r\n",
               UDMA_PDMA_CH_MCU_MCSPI0_CH0_TX);
@@ -535,57 +478,6 @@ int32_t udmaTestPrintPdmaMacro(UdmaTestTaskObj *taskObj)
     GT_1trace(taskObj->traceMask, GT_INFO1,
               " MAIN_MCASP2_RX              : Thread ID: 0x%0.4X\r\n",
               UDMA_PDMA_CH_MAIN_MCASP2_RX);
-    GT_1trace(taskObj->traceMask, GT_INFO1,
-              " MAIN_MCASP3_RX              : Thread ID: 0x%0.4X\r\n",
-              UDMA_PDMA_CH_MAIN_MCASP3_RX);
-    GT_1trace(taskObj->traceMask, GT_INFO1,
-              " MAIN_MCASP4_RX              : Thread ID: 0x%0.4X\r\n",
-              UDMA_PDMA_CH_MAIN_MCASP4_RX);
-    GT_1trace(taskObj->traceMask, GT_INFO1,
-              " MAIN_MCASP5_RX              : Thread ID: 0x%0.4X\r\n",
-              UDMA_PDMA_CH_MAIN_MCASP5_RX);
-    GT_1trace(taskObj->traceMask, GT_INFO1,
-              " MAIN_MCASP6_RX              : Thread ID: 0x%0.4X\r\n",
-              UDMA_PDMA_CH_MAIN_MCASP6_RX);
-    GT_1trace(taskObj->traceMask, GT_INFO1,
-              " MAIN_MCASP7_RX              : Thread ID: 0x%0.4X\r\n",
-              UDMA_PDMA_CH_MAIN_MCASP7_RX);
-    GT_1trace(taskObj->traceMask, GT_INFO1,
-              " MAIN_MCASP8_RX              : Thread ID: 0x%0.4X\r\n",
-              UDMA_PDMA_CH_MAIN_MCASP8_RX);
-    GT_1trace(taskObj->traceMask, GT_INFO1,
-              " MAIN_MCASP9_RX              : Thread ID: 0x%0.4X\r\n",
-              UDMA_PDMA_CH_MAIN_MCASP9_RX);
-    GT_1trace(taskObj->traceMask, GT_INFO1,
-              " MAIN_MCASP10_RX             : Thread ID: 0x%0.4X\r\n",
-              UDMA_PDMA_CH_MAIN_MCASP10_RX);
-    GT_1trace(taskObj->traceMask, GT_INFO1,
-              " MAIN_MCASP11_RX             : Thread ID: 0x%0.4X\r\n",
-              UDMA_PDMA_CH_MAIN_MCASP11_RX);
-    GT_1trace(taskObj->traceMask, GT_INFO1,
-              " MAIN_AASRC0_CH0_RX          : Thread ID: 0x%0.4X\r\n",
-              UDMA_PDMA_CH_MAIN_AASRC0_CH0_RX);
-    GT_1trace(taskObj->traceMask, GT_INFO1,
-              " MAIN_AASRC0_CH1_RX          : Thread ID: 0x%0.4X\r\n",
-              UDMA_PDMA_CH_MAIN_AASRC0_CH1_RX);
-    GT_1trace(taskObj->traceMask, GT_INFO1,
-              " MAIN_AASRC0_CH2_RX          : Thread ID: 0x%0.4X\r\n",
-              UDMA_PDMA_CH_MAIN_AASRC0_CH2_RX);
-    GT_1trace(taskObj->traceMask, GT_INFO1,
-              " MAIN_AASRC0_CH3_RX          : Thread ID: 0x%0.4X\r\n",
-              UDMA_PDMA_CH_MAIN_AASRC0_CH3_RX);
-    GT_1trace(taskObj->traceMask, GT_INFO1,
-              " MAIN_AASRC0_CH4_RX          : Thread ID: 0x%0.4X\r\n",
-              UDMA_PDMA_CH_MAIN_AASRC0_CH4_RX);
-    GT_1trace(taskObj->traceMask, GT_INFO1,
-              " MAIN_AASRC0_CH5_RX          : Thread ID: 0x%0.4X\r\n",
-              UDMA_PDMA_CH_MAIN_AASRC0_CH5_RX);
-    GT_1trace(taskObj->traceMask, GT_INFO1,
-              " MAIN_AASRC0_CH6_RX          : Thread ID: 0x%0.4X\r\n",
-              UDMA_PDMA_CH_MAIN_AASRC0_CH6_RX);
-    GT_1trace(taskObj->traceMask, GT_INFO1,
-              " MAIN_AASRC0_CH7_RX          : Thread ID: 0x%0.4X\r\n",
-              UDMA_PDMA_CH_MAIN_AASRC0_CH7_RX);
     GT_1trace(taskObj->traceMask, GT_INFO1,
               " MAIN_UART0_RX               : Thread ID: 0x%0.4X\r\n",
               UDMA_PDMA_CH_MAIN_UART0_RX);
@@ -838,6 +730,42 @@ int32_t udmaTestPrintPdmaMacro(UdmaTestTaskObj *taskObj)
     GT_1trace(taskObj->traceMask, GT_INFO1,
               " MAIN_MCAN13_CH2_RX          : Thread ID: 0x%0.4X\r\n",
               UDMA_PDMA_CH_MAIN_MCAN13_CH2_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN14_CH0_RX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN14_CH0_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN14_CH1_RX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN14_CH1_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN14_CH2_RX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN14_CH2_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN15_CH0_RX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN15_CH0_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN15_CH1_RX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN15_CH1_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN15_CH2_RX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN15_CH2_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN16_CH0_RX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN16_CH0_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN16_CH1_RX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN16_CH1_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN16_CH2_RX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN16_CH2_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN17_CH0_RX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN17_CH0_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN17_CH1_RX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN17_CH1_RX);
+    GT_1trace(taskObj->traceMask, GT_INFO1,
+              " MAIN_MCAN17_CH2_RX          : Thread ID: 0x%0.4X\r\n",
+              UDMA_PDMA_CH_MAIN_MCAN17_CH2_RX);
     GT_1trace(taskObj->traceMask, GT_INFO1,
               " MCU_ADC0_CH0_RX             : Thread ID: 0x%0.4X\r\n",
               UDMA_PDMA_CH_MCU_ADC0_CH0_RX);
index e039763b4c39fbf5022bb4fc2c6eb9d7738a20c2..5531adc29e6d708c152703320281f0252e8d0bc9 100755 (executable)
@@ -639,11 +639,13 @@ static void udmaTestTask(void *arg0, void *arg1)
 static int32_t udmaTestInit(UdmaTestObj *testObj)
 {
     int32_t             retVal = UDMA_SOK;
-    Udma_DrvHandle      drvHandle;
     SemaphoreP_Params   semPrms;
+#if defined (UDMA_UTC_ID_MSMC_DRU0)
+    Udma_DrvHandle      drvHandle;
     uint32_t            utcId;
     uint32_t            numQueue, queId;
     CSL_DruQueueConfig  queueCfg;
+#endif
 
     SemaphoreP_Params_init(&semPrms);
     semPrms.mode = SemaphoreP_Mode_BINARY;
@@ -656,6 +658,7 @@ static int32_t udmaTestInit(UdmaTestObj *testObj)
     retVal += Utils_memInit();
     retVal += udmaTestInitDriver(testObj);
 
+#if defined (UDMA_UTC_ID_MSMC_DRU0)
     if(UDMA_SOK == retVal)
     {
         /* Init all DRU queue */
@@ -680,6 +683,7 @@ static int32_t udmaTestInit(UdmaTestObj *testObj)
             }
         }
     }
+#endif
 
     return (retVal);
 }
index dc2898b75beecc797e1374f8bfd3d8ebaf620bd3..be4665ddc399584b3c91c9488a5f4716a0b63af1 100755 (executable)
@@ -1161,6 +1161,7 @@ static UdmaTestParams gUdmaTestCases[] =
         .runFlag    = (UDMA_TEST_RF_MAIN_BC_PACING),
         .ringPrmId  = UDMA_TEST_RING_PRMID_INVALID,
     },
+#if defined (UDMA_UTC_ID_MSMC_DRU0)
     {
         .enableTest = TEST_ENABLE,
         .tcId       = 3499U,
@@ -1481,6 +1482,7 @@ static UdmaTestParams gUdmaTestCases[] =
         .runFlag    = (UDMA_TEST_RF_DRU_MT),
         .ringPrmId  = UDMA_TEST_RING_PRMID_INVALID,
     },
+#endif  /* #if defined (UDMA_UTC_ID_MSMC_DRU0) */
     {
         .enableTest = TEST_ENABLE,
         .tcId       = 3507U,
index 4379e416ee270e2148102fe097607252339c16e5..89794e9dd6de93e5a314d93a98d88d62f7204e6e 100644 (file)
@@ -172,8 +172,10 @@ static const UdmaTestUtcChPrm gUdmaTestUtcChPrm[] =
             .dmaPriority    = UDMA_DEFAULT_UTC_CH_DMA_PRIORITY,
             .burstSize      = TISCI_MSG_VALUE_RM_UDMAP_CH_BURST_SIZE_128_BYTES,
             .supressTdCqPkt = TISCI_MSG_VALUE_RM_UDMAP_TX_CH_SUPPRESS_TD_DISABLED,
+#if (UDMA_NUM_UTC_INSTANCE > 0)
             .druOwner       = CSL_DRU_OWNER_UDMAC_TR,
             .druQueueId     = CSL_DRU_QUEUE_ID_3,
+#endif
         }
     },
     {
@@ -190,8 +192,10 @@ static const UdmaTestUtcChPrm gUdmaTestUtcChPrm[] =
             .dmaPriority    = TISCI_MSG_VALUE_RM_UDMAP_CH_SCHED_PRIOR_HIGH,
             .burstSize      = TISCI_MSG_VALUE_RM_UDMAP_CH_BURST_SIZE_128_BYTES,
             .supressTdCqPkt = TISCI_MSG_VALUE_RM_UDMAP_TX_CH_SUPPRESS_TD_DISABLED,
+#if (UDMA_NUM_UTC_INSTANCE > 0)
             .druOwner       = CSL_DRU_OWNER_UDMAC_TR,
             .druQueueId     = CSL_DRU_QUEUE_ID_3,
+#endif
         }
     },
 };
@@ -317,6 +321,7 @@ static const UdmaTestChPrm gUdmaTestChPrm[] =
         .utcPrmId       = UDMA_TEST_UTCCH_PRMID_INVALID,
         .pdmaPrmId      = UDMA_TEST_PDMACH_PRMID_INVALID,
     },
+#if defined (UDMA_UTC_ID_MSMC_DRU0)
     {
         .chPrmId        = UDMA_TEST_CH_PRMID_DRU_DEF,
         .chType         = UDMA_CH_TYPE_UTC,
@@ -343,6 +348,7 @@ static const UdmaTestChPrm gUdmaTestChPrm[] =
         .utcPrmId       = UDMA_TEST_UTCCH_PRMID_DEF,
         .pdmaPrmId      = UDMA_TEST_PDMACH_PRMID_INVALID,
     },
+#endif
     {
         .chPrmId        = UDMA_TEST_CH_PRMID_BLKCPY_HC_DEF,
         .chType         = UDMA_CH_TYPE_TR_BLK_COPY_HC,
index 6baade4dcd8d07763340c71f4ad33160b457dfd6..79033ede3625d87fbddd2ac8a54c950323125143 100755 (executable)
 #
 ifeq ($(udma_ut_component_make_include), )
 
+drvudma_ut_am65xx_CORELIST = mpu1_0 mcu1_0
+drvudma_ut_j721e_CORELIST  = mpu1_0 mcu1_0 mcu2_0 mcu2_1 mcu3_0 mcu3_1 c66xdsp_1 c66xdsp_2 c7x_1
+drvudma_ut_j7200_CORELIST  = mpu1_0 mcu1_0 mcu2_0 mcu2_1
+
+drvudma_dynamic_ut_am65xx_CORELIST = mcu1_0
+drvudma_dynamic_ut_j721e_CORELIST  = mcu1_0 mcu2_1
+drvudma_dynamic_ut_j7200_CORELIST  = mcu1_0 mcu2_1
+
 ############################
 # udma_ut package
 # List of components included under udma_ut
@@ -53,11 +61,7 @@ export udma_unit_testapp_XDC_CONFIGURO = yes
 udma_unit_testapp_PKG_LIST = udma_unit_testapp
 udma_unit_testapp_INCLUDE = $(udma_unit_testapp_PATH)
 export udma_unit_testapp_BOARDLIST = $(drvudma_BOARDLIST)
-ifeq ($(SOC),$(filter $(SOC), j721e))
-export udma_unit_testapp_$(SOC)_CORELIST = mpu1_0 mcu1_0 mcu2_0 mcu2_1 mcu3_0 mcu3_1 c66xdsp_1 c66xdsp_2 c7x_1
-else
-export udma_unit_testapp_$(SOC)_CORELIST = mpu1_0 mcu1_0
-endif
+export udma_unit_testapp_$(SOC)_CORELIST = $(drvudma_ut_$(SOC)_CORELIST)
 export udma_unit_testapp_SBL_APPIMAGEGEN = yes
 udma_ut_EXAMPLE_LIST += udma_unit_testapp
 
@@ -72,11 +76,7 @@ export udma_user_input_unit_testapp_XDC_CONFIGURO = yes
 udma_user_input_unit_testapp_PKG_LIST = udma_user_input_unit_testapp
 udma_user_input_unit_testapp_INCLUDE = $(udma_user_input_unit_testapp_PATH)
 export udma_user_input_unit_testapp_BOARDLIST = $(drvudma_BOARDLIST)
-ifeq ($(SOC),$(filter $(SOC), j721e))
-export udma_user_input_unit_testapp_$(SOC)_CORELIST = mpu1_0 mcu1_0 mcu2_0 mcu2_1 mcu3_0 mcu3_1 c66xdsp_1 c66xdsp_2 c7x_1
-else
-export udma_user_input_unit_testapp_$(SOC)_CORELIST = mpu1_0 mcu1_0
-endif
+export udma_user_input_unit_testapp_$(SOC)_CORELIST = $(drvudma_ut_$(SOC)_CORELIST)
 export udma_user_input_unit_testapp_SBL_APPIMAGEGEN = yes
 udma_ut_EXAMPLE_LIST += udma_user_input_unit_testapp
 
@@ -91,11 +91,7 @@ export udma_baremetal_unit_testapp_XDC_CONFIGURO = no
 udma_baremetal_unit_testapp_PKG_LIST = udma_baremetal_unit_testapp
 udma_baremetal_unit_testapp_INCLUDE = $(udma_baremetal_unit_testapp_PATH)
 export udma_baremetal_unit_testapp_BOARDLIST = $(drvudma_BOARDLIST)
-ifeq ($(SOC),$(filter $(SOC), j721e))
-export udma_baremetal_unit_testapp_$(SOC)_CORELIST = mpu1_0 mcu1_0 mcu2_0 mcu2_1 mcu3_0 mcu3_1 c66xdsp_1 c66xdsp_2 c7x_1
-else
-export udma_baremetal_unit_testapp_$(SOC)_CORELIST = mpu1_0 mcu1_0
-endif
+export udma_baremetal_unit_testapp_$(SOC)_CORELIST = $(drvudma_ut_$(SOC)_CORELIST)
 export udma_baremetal_unit_testapp_SBL_APPIMAGEGEN = yes
 udma_ut_EXAMPLE_LIST += udma_baremetal_unit_testapp
 
@@ -110,11 +106,7 @@ export udma_dynamic_unit_testapp_XDC_CONFIGURO = no
 udma_dynamic_unit_testapp_PKG_LIST = udma_dynamic_unit_testapp
 udma_dynamic_unit_testapp_INCLUDE = $(udma_dynamic_unit_testapp_PATH)
 export udma_dynamic_unit_testapp_BOARDLIST = $(drvudma_BOARDLIST)
-ifeq ($(SOC),$(filter $(SOC), j721e))
-export udma_dynamic_unit_testapp_$(SOC)_CORELIST = mcu1_0 mcu2_1
-else
-export udma_dynamic_unit_testapp_$(SOC)_CORELIST = mcu1_0
-endif
+export udma_dynamic_unit_testapp_$(SOC)_CORELIST = $(drvudma_dynamic_ut_$(SOC)_CORELIST)
 export udma_dynamic_unit_testapp_SBL_APPIMAGEGEN = yes
 udma_ut_EXAMPLE_LIST += udma_dynamic_unit_testapp
 
index 156906470c45bede3d8ecfe172b3d7e85c05318a..7ffcaec473b6a31f3851448e5b81b93482693cc5 100644 (file)
@@ -7,7 +7,7 @@ APP_NAME = OSAL_TestApp
 # Name of the binary if different from the default (APP_NAME)_$(BOARD_$(CORE)_<build_profile>
 LOCAL_APP_NAME =  OSAL_$(BOARD)_$(CORE)TestApp
 
-ifeq ($(SOC),$(filter $(SOC), am65xx j721e j7200, tpr12))
+ifeq ($(SOC),$(filter $(SOC), am65xx j721e j7200 tpr12))
 SRCDIR = . ../src ../
 INCDIR = . ../src ../
 # Common source files across all platforms and cores