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raw | patch | inline | side by side (parent: 8a14186)
| author | Jacob Stiffler <j-stiffler@ti.com> | |
| Fri, 1 Nov 2019 18:57:47 +0000 (14:57 -0400) | ||
| committer | Jacob Stiffler <j-stiffler@ti.com> | |
| Fri, 1 Nov 2019 18:57:47 +0000 (14:57 -0400) |
Development of dss-lld has been relocated here from:
* Repo: https://git.ti.com/keystone-rtos/dss-lld
* Branch: master
* Commit ID: c28a39a174fe2df880b5fbaa57b246df057ba9fb
Signed-off-by: Jacob Stiffler <j-stiffler@ti.com>
* Repo: https://git.ti.com/keystone-rtos/dss-lld
* Branch: master
* Commit ID: c28a39a174fe2df880b5fbaa57b246df057ba9fb
Signed-off-by: Jacob Stiffler <j-stiffler@ti.com>
360 files changed:
diff --git a/packages/ti/drv/dss/.gitignore b/packages/ti/drv/dss/.gitignore
--- /dev/null
@@ -0,0 +1,10 @@
+lib/*\r
+.dlls\r
+.executables\r
+.xdcenv.mak\r
+*.mak\r
+.interfaces\r
+.libraries\r
+package/*\r
+Settings.h\r
+Settings.xdc
\ No newline at end of file
diff --git a/packages/ti/drv/dss/Settings.xdc.xdt b/packages/ti/drv/dss/Settings.xdc.xdt
--- /dev/null
@@ -0,0 +1,59 @@
+
+%%{
+/*!
+ * This template implements the Settings.xdc
+ */
+ /* Versioning */
+ var ver = this;
+ for each(i=0;i<ver.length;i++)
+ {
+ if(String(ver[i]).length < 2)
+ {
+ ver[i]="0"+ver[i];
+ }
+ }
+
+ var packageVersion = "\""+ver[0]+"."+ver[1]+"."+ver[2]+"."+ver[3]+"\"";
+
+%%}
+
+module Settings
+{
+ config string dssVersionString = `packageVersion`;
+
+ /*! This variable is to control the SoC type selection.
+ * By default this variable is set to NULL.
+ *
+ * To use DSS for the selected device, add the following lines to config
+ * file and set the deviceType correctly:
+ *
+ * var dssSettings = xdc.useModule ('ti.drv.dss.Settings');
+ * dssSettings.socType = "am65xx";
+ *
+ */
+ metaonly config string socType = "";
+
+ /*! This variable is to control the Board type selection.
+ * By default this variable is set to NULL.
+ *
+ * To use DSS for the selected device, add the following lines to config
+ * file and set the deviceType correctly:
+ *
+ * var dssSettings = xdc.useModule ('ti.drv.dss.Settings');
+ * dssSettings.boardType = "am65xx_evm";
+ *
+ */
+ metaonly config string boardType = "";
+
+ /*! This variable is to control the device library type selection.
+ * By default this variable is set to release.
+ *
+ * To use the debug/release library, add the following lines to config
+ * file and set the library profile accordingly:
+ *
+ * var dssSettings = xdc.useModule ('ti.drv.dss.Settings');
+ * dssSettings.libProfile = "debug";
+ *
+ */
+ metaonly config string libProfile = "release";
+}
diff --git a/packages/ti/drv/dss/config_mk.bld b/packages/ti/drv/dss/config_mk.bld
--- /dev/null
@@ -0,0 +1,19 @@
+/******************************************************************************
+ * FILE PURPOSE: Build configuration Script for the DSS
+ ******************************************************************************
+ * FILE NAME: config.bld
+ *
+ * DESCRIPTION:
+ * This file contains the build configuration script for the DSS
+ * and is responsible for configuration of the paths for the various
+ * tools required to build the driver.
+ *
+ * Copyright (C) 2018, Texas Instruments, Inc.
+ *****************************************************************************/
+
+/* Configure the DSS Release Version Information */
+var dssDriverReleaseVersion = (""+Pkg.version.replace(/\s/g, "")).split(',');
+
+var Build = xdc.useModule('xdc.bld.BuildEnvironment');
+Build.useTargets=null;
+
diff --git a/packages/ti/drv/dss/docs/Doxyfile b/packages/ti/drv/dss/docs/Doxyfile
--- /dev/null
@@ -0,0 +1,240 @@
+# Doxyfile 1.5.1-p1
+
+#---------------------------------------------------------------------------
+# Project related configuration options
+#---------------------------------------------------------------------------
+PROJECT_NAME = "DSS Driver"
+PROJECT_NUMBER = 3.03.00
+OUTPUT_DIRECTORY = ./docs/doxygen
+CREATE_SUBDIRS = NO
+OUTPUT_LANGUAGE = English
+BRIEF_MEMBER_DESC = YES
+REPEAT_BRIEF = YES
+ABBREVIATE_BRIEF = "The $name class" \
+ "The $name widget" \
+ "The $name file" \
+ is \
+ provides \
+ specifies \
+ contains \
+ represents \
+ a \
+ an \
+ the
+ALWAYS_DETAILED_SEC = NO
+INLINE_INHERITED_MEMB = NO
+FULL_PATH_NAMES = NO
+STRIP_FROM_PATH =
+STRIP_FROM_INC_PATH =
+SHORT_NAMES = NO
+JAVADOC_AUTOBRIEF = NO
+MULTILINE_CPP_IS_BRIEF = NO
+INHERIT_DOCS = YES
+SEPARATE_MEMBER_PAGES = NO
+TAB_SIZE = 8
+ALIASES =
+OPTIMIZE_OUTPUT_FOR_C = YES
+OPTIMIZE_OUTPUT_JAVA = NO
+BUILTIN_STL_SUPPORT = NO
+DISTRIBUTE_GROUP_DOC = YES
+SUBGROUPING = YES
+#---------------------------------------------------------------------------
+# Build related configuration options
+#---------------------------------------------------------------------------
+EXTRACT_ALL = NO
+EXTRACT_PRIVATE = NO
+EXTRACT_STATIC = YES
+EXTRACT_LOCAL_CLASSES = YES
+EXTRACT_LOCAL_METHODS = NO
+HIDE_UNDOC_MEMBERS = NO
+HIDE_UNDOC_CLASSES = YES
+HIDE_FRIEND_COMPOUNDS = NO
+HIDE_IN_BODY_DOCS = NO
+INTERNAL_DOCS = NO
+CASE_SENSE_NAMES = NO
+HIDE_SCOPE_NAMES = NO
+SHOW_INCLUDE_FILES = YES
+INLINE_INFO = YES
+SORT_MEMBER_DOCS = YES
+SORT_BRIEF_DOCS = NO
+SORT_BY_SCOPE_NAME = NO
+GENERATE_TODOLIST = YES
+GENERATE_TESTLIST = YES
+GENERATE_BUGLIST = YES
+GENERATE_DEPRECATEDLIST= YES
+ENABLED_SECTIONS =
+MAX_INITIALIZER_LINES = 30
+SHOW_USED_FILES = YES
+FILE_VERSION_FILTER =
+#---------------------------------------------------------------------------
+# configuration options related to warning and progress messages
+#---------------------------------------------------------------------------
+QUIET = NO
+WARNINGS = YES
+WARN_IF_UNDOCUMENTED = YES
+WARN_IF_DOC_ERROR = YES
+WARN_NO_PARAMDOC = NO
+WARN_FORMAT = "$file:$line: $text"
+WARN_LOGFILE =
+#---------------------------------------------------------------------------
+# configuration options related to the input files
+#---------------------------------------------------------------------------
+INPUT = ../../csl/csl_dss.h \
+ ../../csl/csl_fvid2_dataTypes.h \
+ ../../csl/src/ip/dss/V4/csl_dssCommon.h \
+ ../../csl/src/ip/dss/V4/csl_dssOverlay.h \
+ ../../csl/src/ip/dss/V4/csl_dssTop.h \
+ ../../csl/src/ip/dss/V4/csl_dssVideoPipe.h \
+ ../../csl/src/ip/dss/V4/csl_dssVideoPort.h \
+ ./dss.h \
+ ./include/dss_cfg.h \
+ ./include/dss_disp.h \
+ ./include/dss_dctrl.h \
+ ./soc/V0/dss_soc.h
+
+FILE_PATTERNS = *.h
+
+RECURSIVE = NO
+EXCLUDE = NO
+EXCLUDE_SYMLINKS = NO
+EXCLUDE_PATTERNS =
+EXAMPLE_PATH = ./docs/doxygen
+EXAMPLE_PATTERNS = *
+EXAMPLE_RECURSIVE = NO
+IMAGE_PATH =
+INPUT_FILTER =
+FILTER_PATTERNS =
+FILTER_SOURCE_FILES = NO
+#---------------------------------------------------------------------------
+# configuration options related to source browsing
+#---------------------------------------------------------------------------
+SOURCE_BROWSER = NO
+INLINE_SOURCES = NO
+STRIP_CODE_COMMENTS = YES
+REFERENCED_BY_RELATION = NO
+REFERENCES_RELATION = NO
+REFERENCES_LINK_SOURCE = YES
+USE_HTAGS = NO
+VERBATIM_HEADERS = NO
+#---------------------------------------------------------------------------
+# configuration options related to the alphabetical class index
+#---------------------------------------------------------------------------
+ALPHABETICAL_INDEX = NO
+COLS_IN_ALPHA_INDEX = 5
+IGNORE_PREFIX =
+#---------------------------------------------------------------------------
+# configuration options related to the HTML output
+#---------------------------------------------------------------------------
+GENERATE_HTML = YES
+HTML_OUTPUT = html
+HTML_FILE_EXTENSION = .html
+HTML_HEADER = ./docs/doxygen/tiheader.htm
+HTML_FOOTER = ./docs/doxygen/tifooter.htm
+HTML_STYLESHEET =
+GENERATE_HTMLHELP = NO
+CHM_FILE = ..\..\dss.chm
+HHC_LOCATION = hhc.exe
+GENERATE_CHI = NO
+BINARY_TOC = NO
+TOC_EXPAND = NO
+DISABLE_INDEX = NO
+ENUM_VALUES_PER_LINE = 4
+GENERATE_TREEVIEW = NO
+TREEVIEW_WIDTH = 250
+#---------------------------------------------------------------------------
+# configuration options related to the LaTeX output
+#---------------------------------------------------------------------------
+GENERATE_LATEX = NO
+LATEX_OUTPUT = latex
+LATEX_CMD_NAME = latex
+MAKEINDEX_CMD_NAME = makeindex
+COMPACT_LATEX = NO
+PAPER_TYPE = a4wide
+EXTRA_PACKAGES =
+LATEX_HEADER =
+PDF_HYPERLINKS = YES
+USE_PDFLATEX = YES
+LATEX_BATCHMODE = NO
+LATEX_HIDE_INDICES = NO
+#---------------------------------------------------------------------------
+# configuration options related to the RTF output
+#---------------------------------------------------------------------------
+GENERATE_RTF = NO
+RTF_OUTPUT = rtf
+COMPACT_RTF = NO
+RTF_HYPERLINKS = NO
+RTF_STYLESHEET_FILE =
+RTF_EXTENSIONS_FILE =
+#---------------------------------------------------------------------------
+# configuration options related to the man page output
+#---------------------------------------------------------------------------
+GENERATE_MAN = NO
+MAN_OUTPUT = man
+MAN_EXTENSION = .3
+MAN_LINKS = NO
+#---------------------------------------------------------------------------
+# configuration options related to the XML output
+#---------------------------------------------------------------------------
+GENERATE_XML = NO
+XML_OUTPUT = xml
+XML_PROGRAMLISTING = YES
+#---------------------------------------------------------------------------
+# configuration options for the AutoGen Definitions output
+#---------------------------------------------------------------------------
+GENERATE_AUTOGEN_DEF = NO
+#---------------------------------------------------------------------------
+# configuration options related to the Perl module output
+#---------------------------------------------------------------------------
+GENERATE_PERLMOD = NO
+PERLMOD_LATEX = NO
+PERLMOD_PRETTY = YES
+PERLMOD_MAKEVAR_PREFIX =
+#---------------------------------------------------------------------------
+# Configuration options related to the preprocessor
+#---------------------------------------------------------------------------
+ENABLE_PREPROCESSING = YES
+MACRO_EXPANSION = NO
+EXPAND_ONLY_PREDEF = NO
+SEARCH_INCLUDES = YES
+INCLUDE_PATH =
+INCLUDE_FILE_PATTERNS =
+PREDEFINED =
+EXPAND_AS_DEFINED =
+SKIP_FUNCTION_MACROS = YES
+#---------------------------------------------------------------------------
+# Configuration::additions related to external references
+#---------------------------------------------------------------------------
+TAGFILES =
+GENERATE_TAGFILE =
+ALLEXTERNALS = NO
+EXTERNAL_GROUPS = YES
+PERL_PATH = /usr/bin/perl
+#---------------------------------------------------------------------------
+# Configuration options related to the dot tool
+#---------------------------------------------------------------------------
+CLASS_DIAGRAMS = NO
+HIDE_UNDOC_RELATIONS = YES
+HAVE_DOT = NO
+CLASS_GRAPH = YES
+COLLABORATION_GRAPH = YES
+GROUP_GRAPHS = YES
+UML_LOOK = NO
+TEMPLATE_RELATIONS = NO
+INCLUDE_GRAPH = YES
+INCLUDED_BY_GRAPH = YES
+CALL_GRAPH = NO
+CALLER_GRAPH = NO
+GRAPHICAL_HIERARCHY = YES
+DIRECTORY_GRAPH = YES
+DOT_IMAGE_FORMAT = png
+DOT_PATH =
+DOTFILE_DIRS =
+MAX_DOT_GRAPH_DEPTH = 1000
+DOT_TRANSPARENT = YES
+DOT_MULTI_TARGETS = NO
+GENERATE_LEGEND = YES
+DOT_CLEANUP = YES
+#---------------------------------------------------------------------------
+# Configuration::additions related to the search engine
+#---------------------------------------------------------------------------
+SEARCHENGINE = NO
diff --git a/packages/ti/drv/dss/docs/doxygen/html/annotated.html b/packages/ti/drv/dss/docs/doxygen/html/annotated.html
--- /dev/null
@@ -0,0 +1,98 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Data Structures</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li class="current"><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="files.html"><span>Files</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow2" class="tabs2">
+ <ul class="tablist">
+ <li class="current"><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="functions.html"><span>Data Fields</span></a></li>
+ </ul>
+ </div>
+</div><!-- top -->
+<div class="header">
+ <div class="headertitle">
+<div class="title">Data Structures</div> </div>
+</div><!--header-->
+<div class="contents">
+<div class="textblock">Here are the data structures with brief descriptions:</div><div class="directory">
+<table class="directory">
+<tr id="row_0_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="struct_c_s_l___dss_cba_cfg.html" target="_self">CSL_DssCbaCfg</a></td><td class="desc">DSS CBA Config parameters </td></tr>
+<tr id="row_1_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="struct_c_s_l___dss_csc_coeff.html" target="_self">CSL_DssCscCoeff</a></td><td class="desc">Structure containing coefficients for Color Space Conversion </td></tr>
+<tr id="row_2_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="struct_c_s_l___dss_global_m_flag_cfg.html" target="_self">CSL_DssGlobalMFlagCfg</a></td><td class="desc">DSS Global MFLAG Config parameters </td></tr>
+<tr id="row_3_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="struct_c_s_l___dss_overlay_cfg.html" target="_self">CSL_DssOverlayCfg</a></td><td class="desc">Configuration for DSS Overlay </td></tr>
+<tr id="row_4_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="struct_c_s_l___dss_overlay_layer_cfg.html" target="_self">CSL_DssOverlayLayerCfg</a></td><td class="desc">Configuration for selecting overlay input layers </td></tr>
+<tr id="row_5_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="struct_c_s_l___dss_overlay_pipe_pos_cfg.html" target="_self">CSL_DssOverlayPipePosCfg</a></td><td class="desc">Video Pipe Position Configuration in Overlay </td></tr>
+<tr id="row_6_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="struct_c_s_l___dss_safety_chk_cfg.html" target="_self">CSL_DssSafetyChkCfg</a></td><td class="desc">Configuration for doing safety checks </td></tr>
+<tr id="row_7_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="struct_c_s_l___dss_vid_pipe_alpha_cfg.html" target="_self">CSL_DssVidPipeAlphaCfg</a></td><td class="desc">DSS Video Pipe Alpha Config parameters </td></tr>
+<tr id="row_8_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="struct_c_s_l___dss_vid_pipe_cfg.html" target="_self">CSL_DssVidPipeCfg</a></td><td class="desc">Configuration for DSS Video Pipe </td></tr>
+<tr id="row_9_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="struct_c_s_l___dss_vid_pipe_dma_cfg.html" target="_self">CSL_DssVidPipeDmaCfg</a></td><td class="desc">DSS Video Pipe DMA related Config parameters </td></tr>
+<tr id="row_10_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="struct_c_s_l___dss_vid_pipe_luma_cfg.html" target="_self">CSL_DssVidPipeLumaCfg</a></td><td class="desc">DSS Video Pipe Luma Key Config parameters </td></tr>
+<tr id="row_11_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="struct_c_s_l___dss_vid_pipe_m_flag_cfg.html" target="_self">CSL_DssVidPipeMFlagCfg</a></td><td class="desc">DSS Video Pipe MFLAG Config parameters </td></tr>
+<tr id="row_12_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="struct_c_s_l___dss_vid_pipe_v_c1_cfg.html" target="_self">CSL_DssVidPipeVC1Cfg</a></td><td class="desc">DSS Video Pipe VC1 configuration </td></tr>
+<tr id="row_13_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="struct_c_s_l___dss_vp_gamma_cfg.html" target="_self">CSL_DssVpGammaCfg</a></td><td class="desc">Gamma Correction configuration for DSS Video Port Output </td></tr>
+<tr id="row_14_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="struct_c_s_l___dss_vp_lcd_adv_signal_cfg.html" target="_self">CSL_DssVpLcdAdvSignalCfg</a></td><td class="desc">Advance Signal Configuration for the LCD </td></tr>
+<tr id="row_15_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="struct_c_s_l___dss_vp_lcd_blank_timing_cfg.html" target="_self">CSL_DssVpLcdBlankTimingCfg</a></td><td class="desc">Blanking Timing parameters for the LCD </td></tr>
+<tr id="row_16_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="struct_c_s_l___dss_vp_lcd_op_timing_cfg.html" target="_self">CSL_DssVpLcdOpTimingCfg</a></td><td class="desc">Timing configuration for the LCD output </td></tr>
+<tr id="row_17_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="struct_c_s_l___dss_vp_lcd_signal_polarity_cfg.html" target="_self">CSL_DssVpLcdSignalPolarityCfg</a></td><td class="desc">Polarity of Active Video, Pixel Clock, HSync and VSync signals for the LCD </td></tr>
+<tr id="row_18_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="struct_c_s_l___dss_vp_lcd_tdm_cfg.html" target="_self">CSL_DssVpLcdTdmCfg</a></td><td class="desc">LCD Configuration for Time Division Multiplexing </td></tr>
+<tr id="row_19_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="struct_dss___dctrl_adv_vp_params.html" target="_self">Dss_DctrlAdvVpParams</a></td><td class="desc">Structure containing advance Video Port information. This structure is used as an argument to IOCTL_DSS_DCTRL_SET_ADV_VP_PARAMS </td></tr>
+<tr id="row_20_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="struct_dss___dctrl_global_dss_params.html" target="_self">Dss_DctrlGlobalDssParams</a></td><td class="desc">Structure containing global DSS Configuration. This structure is used as an argument to IOCTL_DSS_DCTRL_SET_GLOBAL_DSS_PARAMS </td></tr>
+<tr id="row_21_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="struct_dss___dctrl_lcd_blank_timing_params.html" target="_self">Dss_DctrlLcdBlankTimingParams</a></td><td class="desc">Structure containing LCD Blank Timing Configuration. This structure is used as an argument to IOCTL_DSS_DCTRL_SET_LCD_BLANK_TIMING_PARAMS </td></tr>
+<tr id="row_22_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="struct_dss___dctrl_oldi_params.html" target="_self">Dss_DctrlOldiParams</a></td><td class="desc">Structure containing OLDI configuration. This structure is used as an argument to IOCTL_DSS_DCTRL_SET_OLDI_PARAMS </td></tr>
+<tr id="row_23_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="struct_dss___dctrl_overlay_layer_params.html" target="_self">Dss_DctrlOverlayLayerParams</a></td><td class="desc">Structure containing Overlay layer information. This structure is used as an argument to IOCTL_DSS_DCTRL_SET_LAYER_PARAMS </td></tr>
+<tr id="row_24_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="struct_dss___dctrl_overlay_params.html" target="_self">Dss_DctrlOverlayParams</a></td><td class="desc">Structure containing Overlay information. This structure is used as an argument to IOCTL_DSS_DCTRL_SET_OVERLAY_PARAMS </td></tr>
+<tr id="row_25_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="struct_dss___dctrl_path_info.html" target="_self">Dss_DctrlPathInfo</a></td><td class="desc">Structure containing DSS path information. This structure is used as an argument to IOCTL_DSS_DCTRL_SET_PATH. This IOCTL takes the array of edges connected between nodes </td></tr>
+<tr id="row_26_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="struct_dss___dctrl_region_safety_chk_cfg.html" target="_self">Dss_DctrlRegionSafetyChkCfg</a></td><td class="desc">Structure containing Safety Check configuration for a particular region </td></tr>
+<tr id="row_27_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="struct_dss___dctrl_sync_lost_cb_params.html" target="_self">Dss_DctrlSyncLostCbParams</a></td><td class="desc">Structure containing Sync Lost callback parameters. This structure is used as an argument to IOCTL_DSS_DCTRL_REGISTER_SYNCLOST_CB </td></tr>
+<tr id="row_28_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="struct_dss___dctrl_vp_csc_coeff.html" target="_self">Dss_DctrlVpCscCoeff</a></td><td class="desc">Structure containing Video Port CSC information. This structure is used as an argument to IOCTL_DSS_DCTRL_SET_VP_CSC_COEFF </td></tr>
+<tr id="row_29_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="struct_dss___dctrl_vp_error_stats.html" target="_self">Dss_DctrlVpErrorStats</a></td><td class="desc">Structure containing Error Stats of Video Port. This structure is used as an argument to IOCTL_DSS_DCTRL_GET_VP_ERROR_STATS </td></tr>
+<tr id="row_30_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="struct_dss___dctrl_vp_params.html" target="_self">Dss_DctrlVpParams</a></td><td class="desc">Structure containing Video Port information. This structure is used as an argument to IOCTL_DSS_DCTRL_SET_VP_PARAMS </td></tr>
+<tr id="row_31_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="struct_dss___dctrl_vp_safety_chk_params.html" target="_self">Dss_DctrlVpSafetyChkParams</a></td><td class="desc">Structure containing Safety Check configuration of Video Port. This structure is used as an argument to IOCTL_DSS_DCTRL_SET_VP_SAFETY_CHK_PARAMS </td></tr>
+<tr id="row_32_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="struct_dss___disp_buf_prgm_cb_params.html" target="_self">Dss_DispBufPrgmCbParams</a></td><td class="desc">Structure containing display buffer program callback parameters. This structure is used as an argument to IOCTL_DSS_DISP_REGISTER_BUF_PRGM_CB </td></tr>
+<tr id="row_33_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="struct_dss___disp_create_params.html" target="_self">Dss_DispCreateParams</a></td><td class="desc">Structure containing display driver create arguments, used when calling Fvid2_create() </td></tr>
+<tr id="row_34_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="struct_dss___disp_create_status.html" target="_self">Dss_DispCreateStatus</a></td><td class="desc">Structure containing create status for the display driver. This should be passed as a status argument while creating the driver </td></tr>
+<tr id="row_35_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="struct_dss___disp_current_status.html" target="_self">Dss_DispCurrentStatus</a></td><td class="desc">Structure containing current status of the display driver. This structure is used as an argument to IOCTL_DSS_DISP_GET_CURRENT_STATUS </td></tr>
+<tr id="row_36_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="struct_dss___disp_params.html" target="_self">Dss_DispParams</a></td><td class="desc">Structure containing DSS parameters. This structure is used as an argument to IOCTL_DSS_DISP_SET_DSS_PARAMS </td></tr>
+<tr id="row_37_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="struct_dss___disp_pipe_mflag_params.html" target="_self">Dss_DispPipeMflagParams</a></td><td class="desc">Structure containing Video Pipe Mflag Information. This structure is used as an argument to IOCTL_DSS_DISP_SET_PIPE_MFLAG_PARAMS </td></tr>
+<tr id="row_38_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="struct_dss___disp_pipe_prgm_cb_params.html" target="_self">Dss_DispPipePrgmCbParams</a></td><td class="desc">Structure containing video pipe program callback parameters. This structure is used as an argument to IOCTL_DSS_DISP_REGISTER_PIPE_PRGM_CB </td></tr>
+<tr id="row_39_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="struct_dss___disp_pipe_safety_chk_params.html" target="_self">Dss_DispPipeSafetyChkParams</a></td><td class="desc">Structure containing Safety Check configuration of Video Port. This structure is used as an argument to IOCTL_DSS_DISP_SET_PIPE_SAFETY_CHK_PARAMS </td></tr>
+<tr id="row_40_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="struct_dss___disp_rt_params.html" target="_self">Dss_DispRtParams</a></td><td class="desc">Structure containing run time configuration of the display driver. This needs to be passed along with frame list to update any supported run time parameters </td></tr>
+<tr id="row_41_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="struct_dss___disp_under_flow_cb_params.html" target="_self">Dss_DispUnderFlowCbParams</a></td><td class="desc">Structure containing pipe under flow callback parameters. This structure is used as an argument to IOCTL_DSS_DISP_REGISTER_PIPE_UNDERFLOW_CB </td></tr>
+<tr id="row_42_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="struct_dss___frame_rt_params.html" target="_self">Dss_FrameRtParams</a></td><td class="desc">Structure containing run time configuration per frame </td></tr>
+<tr id="row_43_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="struct_dss___init_params.html" target="_self">Dss_InitParams</a></td><td class="desc">DSS initialization parameters </td></tr>
+<tr id="row_44_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="struct_dss___irq_params.html" target="_self">Dss_IrqParams</a></td><td class="desc">Structure containing DSS interrupt information. Events should be enabled only for available Video Ports and Video Pipes </td></tr>
+<tr id="row_45_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="struct_dss___rm_info.html" target="_self">Dss_RmInfo</a></td><td class="desc">Structure containing resources manager information. This enables display sharing between two different softwares </td></tr>
+<tr id="row_46_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="struct_dss___sc_rt_params.html" target="_self">Dss_ScRtParams</a></td><td class="desc">Structure containing run time scaler configuration </td></tr>
+<tr id="row_47_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="struct_dss___soc_params.html" target="_self">Dss_SocParams</a></td><td class="desc">DSS SOC parameters </td></tr>
+<tr id="row_48_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="struct_fvid2___crop_config.html" target="_self">Fvid2_CropConfig</a></td><td class="desc">Structure containing crop configuration - used in Scaler and VCOMP </td></tr>
+<tr id="row_49_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="struct_fvid2___format.html" target="_self">Fvid2_Format</a></td><td class="desc">FVID2 video buffer format specification </td></tr>
+<tr id="row_50_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="struct_fvid2___frame.html" target="_self">Fvid2_Frame</a></td><td class="desc">FVID2 frame buffer structure </td></tr>
+<tr id="row_51_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="struct_fvid2___frame_list.html" target="_self">Fvid2_FrameList</a></td><td class="desc">FVID2 frame buffer list used to exchange multiple FVID2 frames in a single driver call </td></tr>
+<tr id="row_52_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="struct_fvid2___mode_info.html" target="_self">Fvid2_ModeInfo</a></td><td class="desc">FVID2 Mode information structure </td></tr>
+<tr id="row_53_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="struct_fvid2___pos_config.html" target="_self">Fvid2_PosConfig</a></td><td class="desc">Structure containing position configuration - used in VCOMP and CIG </td></tr>
+<tr id="row_54_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="struct_fvid2___size_config.html" target="_self">Fvid2_SizeConfig</a></td><td class="desc">Structure containing size configuration </td></tr>
+<tr id="row_55_"><td class="entry"><img src="ftv2lastnode.png" alt="\" width="16" height="22" /><img src="ftv2cl.png" alt="C" width="24" height="22" /><a class="el" href="struct_fvid2___sub_frame_info.html" target="_self">Fvid2_SubFrameInfo</a></td><td class="desc">Sub-Frame information </td></tr>
+</table>
+</div><!-- directory -->
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
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+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Data Structure Index</title>
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+<link href="tabs.css" rel="stylesheet" type="text/css">
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+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
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+ <li><a href="index.html"><span>Main Page</span></a></li>
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+<div class="title">Data Structure Index</div> </div>
+</div><!--header-->
+<div class="contents">
+<div class="qindex"><a class="qindex" href="#letter_C">C</a> | <a class="qindex" href="#letter_D">D</a> | <a class="qindex" href="#letter_F">F</a></div>
+<table style="margin: 10px; white-space: nowrap;" align="center" width="95%" border="0" cellspacing="0" cellpadding="0">
+<tr><td rowspan="2" valign="bottom"><a name="letter_C"></a><table border="0" cellspacing="0" cellpadding="0"><tr><td><div class="ah">  C  </div></td></tr></table>
+</td><td valign="top"><a class="el" href="struct_c_s_l___dss_vid_pipe_m_flag_cfg.html">CSL_DssVidPipeMFlagCfg</a>   </td><td valign="top"><a class="el" href="struct_dss___dctrl_oldi_params.html">Dss_DctrlOldiParams</a>   </td><td valign="top"><a class="el" href="struct_dss___disp_current_status.html">Dss_DispCurrentStatus</a>   </td><td rowspan="2" valign="bottom"><a name="letter_F"></a><table border="0" cellspacing="0" cellpadding="0"><tr><td><div class="ah">  F  </div></td></tr></table>
+</td></tr>
+<tr><td valign="top"><a class="el" href="struct_c_s_l___dss_vid_pipe_v_c1_cfg.html">CSL_DssVidPipeVC1Cfg</a>   </td><td valign="top"><a class="el" href="struct_dss___dctrl_overlay_layer_params.html">Dss_DctrlOverlayLayerParams</a>   </td><td valign="top"><a class="el" href="struct_dss___disp_params.html">Dss_DispParams</a>   </td></tr>
+<tr><td valign="top"><a class="el" href="struct_c_s_l___dss_cba_cfg.html">CSL_DssCbaCfg</a>   </td><td valign="top"><a class="el" href="struct_c_s_l___dss_vp_gamma_cfg.html">CSL_DssVpGammaCfg</a>   </td><td valign="top"><a class="el" href="struct_dss___dctrl_overlay_params.html">Dss_DctrlOverlayParams</a>   </td><td valign="top"><a class="el" href="struct_dss___disp_pipe_mflag_params.html">Dss_DispPipeMflagParams</a>   </td><td valign="top"><a class="el" href="struct_fvid2___crop_config.html">Fvid2_CropConfig</a>   </td></tr>
+<tr><td valign="top"><a class="el" href="struct_c_s_l___dss_csc_coeff.html">CSL_DssCscCoeff</a>   </td><td valign="top"><a class="el" href="struct_c_s_l___dss_vp_lcd_adv_signal_cfg.html">CSL_DssVpLcdAdvSignalCfg</a>   </td><td valign="top"><a class="el" href="struct_dss___dctrl_path_info.html">Dss_DctrlPathInfo</a>   </td><td valign="top"><a class="el" href="struct_dss___disp_pipe_prgm_cb_params.html">Dss_DispPipePrgmCbParams</a>   </td><td valign="top"><a class="el" href="struct_fvid2___format.html">Fvid2_Format</a>   </td></tr>
+<tr><td valign="top"><a class="el" href="struct_c_s_l___dss_global_m_flag_cfg.html">CSL_DssGlobalMFlagCfg</a>   </td><td valign="top"><a class="el" href="struct_c_s_l___dss_vp_lcd_blank_timing_cfg.html">CSL_DssVpLcdBlankTimingCfg</a>   </td><td valign="top"><a class="el" href="struct_dss___dctrl_region_safety_chk_cfg.html">Dss_DctrlRegionSafetyChkCfg</a>   </td><td valign="top"><a class="el" href="struct_dss___disp_pipe_safety_chk_params.html">Dss_DispPipeSafetyChkParams</a>   </td><td valign="top"><a class="el" href="struct_fvid2___frame.html">Fvid2_Frame</a>   </td></tr>
+<tr><td valign="top"><a class="el" href="struct_c_s_l___dss_overlay_cfg.html">CSL_DssOverlayCfg</a>   </td><td valign="top"><a class="el" href="struct_c_s_l___dss_vp_lcd_op_timing_cfg.html">CSL_DssVpLcdOpTimingCfg</a>   </td><td valign="top"><a class="el" href="struct_dss___dctrl_sync_lost_cb_params.html">Dss_DctrlSyncLostCbParams</a>   </td><td valign="top"><a class="el" href="struct_dss___disp_rt_params.html">Dss_DispRtParams</a>   </td><td valign="top"><a class="el" href="struct_fvid2___frame_list.html">Fvid2_FrameList</a>   </td></tr>
+<tr><td valign="top"><a class="el" href="struct_c_s_l___dss_overlay_layer_cfg.html">CSL_DssOverlayLayerCfg</a>   </td><td valign="top"><a class="el" href="struct_c_s_l___dss_vp_lcd_signal_polarity_cfg.html">CSL_DssVpLcdSignalPolarityCfg</a>   </td><td valign="top"><a class="el" href="struct_dss___dctrl_vp_csc_coeff.html">Dss_DctrlVpCscCoeff</a>   </td><td valign="top"><a class="el" href="struct_dss___disp_under_flow_cb_params.html">Dss_DispUnderFlowCbParams</a>   </td><td valign="top"><a class="el" href="struct_fvid2___mode_info.html">Fvid2_ModeInfo</a>   </td></tr>
+<tr><td valign="top"><a class="el" href="struct_c_s_l___dss_overlay_pipe_pos_cfg.html">CSL_DssOverlayPipePosCfg</a>   </td><td valign="top"><a class="el" href="struct_c_s_l___dss_vp_lcd_tdm_cfg.html">CSL_DssVpLcdTdmCfg</a>   </td><td valign="top"><a class="el" href="struct_dss___dctrl_vp_error_stats.html">Dss_DctrlVpErrorStats</a>   </td><td valign="top"><a class="el" href="struct_dss___frame_rt_params.html">Dss_FrameRtParams</a>   </td><td valign="top"><a class="el" href="struct_fvid2___pos_config.html">Fvid2_PosConfig</a>   </td></tr>
+<tr><td valign="top"><a class="el" href="struct_c_s_l___dss_safety_chk_cfg.html">CSL_DssSafetyChkCfg</a>   </td><td rowspan="2" valign="bottom"><a name="letter_D"></a><table border="0" cellspacing="0" cellpadding="0"><tr><td><div class="ah">  D  </div></td></tr></table>
+</td><td valign="top"><a class="el" href="struct_dss___dctrl_vp_params.html">Dss_DctrlVpParams</a>   </td><td valign="top"><a class="el" href="struct_dss___init_params.html">Dss_InitParams</a>   </td><td valign="top"><a class="el" href="struct_fvid2___size_config.html">Fvid2_SizeConfig</a>   </td></tr>
+<tr><td valign="top"><a class="el" href="struct_c_s_l___dss_vid_pipe_alpha_cfg.html">CSL_DssVidPipeAlphaCfg</a>   </td><td valign="top"><a class="el" href="struct_dss___dctrl_vp_safety_chk_params.html">Dss_DctrlVpSafetyChkParams</a>   </td><td valign="top"><a class="el" href="struct_dss___irq_params.html">Dss_IrqParams</a>   </td><td valign="top"><a class="el" href="struct_fvid2___sub_frame_info.html">Fvid2_SubFrameInfo</a>   </td></tr>
+<tr><td valign="top"><a class="el" href="struct_c_s_l___dss_vid_pipe_cfg.html">CSL_DssVidPipeCfg</a>   </td><td valign="top"><a class="el" href="struct_dss___dctrl_adv_vp_params.html">Dss_DctrlAdvVpParams</a>   </td><td valign="top"><a class="el" href="struct_dss___disp_buf_prgm_cb_params.html">Dss_DispBufPrgmCbParams</a>   </td><td valign="top"><a class="el" href="struct_dss___rm_info.html">Dss_RmInfo</a>   </td><td></td></tr>
+<tr><td valign="top"><a class="el" href="struct_c_s_l___dss_vid_pipe_dma_cfg.html">CSL_DssVidPipeDmaCfg</a>   </td><td valign="top"><a class="el" href="struct_dss___dctrl_global_dss_params.html">Dss_DctrlGlobalDssParams</a>   </td><td valign="top"><a class="el" href="struct_dss___disp_create_params.html">Dss_DispCreateParams</a>   </td><td valign="top"><a class="el" href="struct_dss___sc_rt_params.html">Dss_ScRtParams</a>   </td><td></td></tr>
+<tr><td valign="top"><a class="el" href="struct_c_s_l___dss_vid_pipe_luma_cfg.html">CSL_DssVidPipeLumaCfg</a>   </td><td valign="top"><a class="el" href="struct_dss___dctrl_lcd_blank_timing_params.html">Dss_DctrlLcdBlankTimingParams</a>   </td><td valign="top"><a class="el" href="struct_dss___disp_create_status.html">Dss_DispCreateStatus</a>   </td><td valign="top"><a class="el" href="struct_dss___soc_params.html">Dss_SocParams</a>   </td><td></td></tr>
+<tr><td></td><td></td><td></td><td></td><td></td></tr>
+</table>
+<div class="qindex"><a class="qindex" href="#letter_C">C</a> | <a class="qindex" href="#letter_D">D</a> | <a class="qindex" href="#letter_F">F</a></div>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/closed.png b/packages/ti/drv/dss/docs/doxygen/html/closed.png
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--- /dev/null
@@ -0,0 +1,52 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>csl_dss.h File Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li class="current"><a href="files.html"><span>Files</span></a></li>
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+ <div id="navrow2" class="tabs2">
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+ <li><a href="files.html"><span>File List</span></a></li>
+ <li><a href="globals.html"><span>Globals</span></a></li>
+ </ul>
+ </div>
+<div id="nav-path" class="navpath">
+ <ul>
+<li class="navelem"><a class="el" href="dir_f5943f6d28c724c9867ac930658f5901.html">csl</a></li> </ul>
+</div>
+</div><!-- top -->
+<div class="header">
+ <div class="headertitle">
+<div class="title">csl_dss.h File Reference</div> </div>
+</div><!--header-->
+<div class="contents">
+
+<p><h1>This file contains the CSL-FL API's for DSS </h1>
+
+<a href="#details">More...</a></p>
+<div class="textblock"><code>#include <ti/csl/csl.h></code><br/>
+<code>#include <ti/csl/cslr.h></code><br/>
+<code>#include <ti/csl/cslr_dss.h></code><br/>
+</div><a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
+<div class="textblock"><h1>This file contains the CSL-FL API's for DSS </h1>
+<p>============================================================================ </p>
+</div></div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/csl__dss_common_8h.html b/packages/ti/drv/dss/docs/doxygen/html/csl__dss_common_8h.html
--- /dev/null
@@ -0,0 +1,311 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>csl_dssCommon.h File Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li class="current"><a href="files.html"><span>Files</span></a></li>
+ </ul>
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+ <ul class="tablist">
+ <li><a href="files.html"><span>File List</span></a></li>
+ <li><a href="globals.html"><span>Globals</span></a></li>
+ </ul>
+ </div>
+<div id="nav-path" class="navpath">
+ <ul>
+<li class="navelem"><a class="el" href="dir_f5943f6d28c724c9867ac930658f5901.html">csl</a></li><li class="navelem"><a class="el" href="dir_2c013fc7e98dc8ade314eba46bcbb0d6.html">src</a></li><li class="navelem"><a class="el" href="dir_063bd5b357e44d632c140cb38e979030.html">ip</a></li><li class="navelem"><a class="el" href="dir_9601e7bd9bffb8db00e0c1272827daa6.html">dss</a></li><li class="navelem"><a class="el" href="dir_61ed5367bdc2fa7807323d7b06750347.html">V4</a></li> </ul>
+</div>
+</div><!-- top -->
+<div class="header">
+ <div class="summary">
+<a href="#nested-classes">Data Structures</a> |
+<a href="#typedef-members">Typedefs</a> |
+<a href="#func-members">Functions</a> </div>
+ <div class="headertitle">
+<div class="title">csl_dssCommon.h File Reference<div class="ingroups"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html">DSS Common CSL FL</a></div></div> </div>
+</div><!--header-->
+<div class="contents">
+
+<p>DSS Common CSL FL interface file.
+<a href="#details">More...</a></p>
+<table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="nested-classes"></a>
+Data Structures</h2></td></tr>
+<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_global_m_flag_cfg.html">CSL_DssGlobalMFlagCfg</a></td></tr>
+<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">DSS Global MFLAG Config parameters. <a href="struct_c_s_l___dss_global_m_flag_cfg.html#details">More...</a><br/></td></tr>
+<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_cba_cfg.html">CSL_DssCbaCfg</a></td></tr>
+<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">DSS CBA Config parameters. <a href="struct_c_s_l___dss_cba_cfg.html#details">More...</a><br/></td></tr>
+<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
+Macros</h2></td></tr>
+<tr><td colspan="2"><div class="groupHeader">DISPC Interrupt Mask</div></td></tr>
+<tr><td colspan="2"><div class="groupText"><p><a class="anchor" id="CSL_DssDispcIntrMask"></a></p>
+</div></td></tr>
+<tr class="memitem:ga1c3a6a248c34ffb2b8183155f96107c9"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga1c3a6a248c34ffb2b8183155f96107c9"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1c3a6a248c34ffb2b8183155f96107c9">CSL_DSS_DISPC_INTR_WB_MASK</a>   ((uint32_t) 0x4000U)</td></tr>
+<tr class="memdesc:ga1c3a6a248c34ffb2b8183155f96107c9"><td class="mdescLeft"> </td><td class="mdescRight">Write Back Pipeline Interrupt. <br/></td></tr>
+<tr class="separator:ga1c3a6a248c34ffb2b8183155f96107c9"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gaca4d1f25e688c3c257df26fbed1bf0b0"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaca4d1f25e688c3c257df26fbed1bf0b0"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gaca4d1f25e688c3c257df26fbed1bf0b0">CSL_DSS_DISPC_INTR_VIDL2_MASK</a>   ((uint32_t) 0x80U)</td></tr>
+<tr class="memdesc:gaca4d1f25e688c3c257df26fbed1bf0b0"><td class="mdescLeft"> </td><td class="mdescRight">Video Lite Pipeline 2 Interrupt. <br/></td></tr>
+<tr class="separator:gaca4d1f25e688c3c257df26fbed1bf0b0"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga3e9bb13013658677983d41d243db6530"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga3e9bb13013658677983d41d243db6530"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga3e9bb13013658677983d41d243db6530">CSL_DSS_DISPC_INTR_VID2_MASK</a>   ((uint32_t) 0x40U)</td></tr>
+<tr class="memdesc:ga3e9bb13013658677983d41d243db6530"><td class="mdescLeft"> </td><td class="mdescRight">Video PipeLine 2 Interrupt. <br/></td></tr>
+<tr class="separator:ga3e9bb13013658677983d41d243db6530"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gabee1d0a280ee911c3f3863343167c034"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gabee1d0a280ee911c3f3863343167c034"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gabee1d0a280ee911c3f3863343167c034">CSL_DSS_DISPC_INTR_VIDL1_MASK</a>   ((uint32_t) 0x20U)</td></tr>
+<tr class="memdesc:gabee1d0a280ee911c3f3863343167c034"><td class="mdescLeft"> </td><td class="mdescRight">Video Lite Pipeline 1 Interrupt. <br/></td></tr>
+<tr class="separator:gabee1d0a280ee911c3f3863343167c034"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga06e5097b8fb8b1581b289d1e4c5f8b1d"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga06e5097b8fb8b1581b289d1e4c5f8b1d"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga06e5097b8fb8b1581b289d1e4c5f8b1d">CSL_DSS_DISPC_INTR_VID1_MASK</a>   ((uint32_t) 0x10U)</td></tr>
+<tr class="memdesc:ga06e5097b8fb8b1581b289d1e4c5f8b1d"><td class="mdescLeft"> </td><td class="mdescRight">Video PipeLine 1 Interrupt. <br/></td></tr>
+<tr class="separator:ga06e5097b8fb8b1581b289d1e4c5f8b1d"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga4663d2526dbf5150b3173715ee5bf049"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga4663d2526dbf5150b3173715ee5bf049"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga4663d2526dbf5150b3173715ee5bf049">CSL_DSS_DISPC_INTR_VP4_MASK</a>   ((uint32_t) 0x08U)</td></tr>
+<tr class="memdesc:ga4663d2526dbf5150b3173715ee5bf049"><td class="mdescLeft"> </td><td class="mdescRight">Video Port 4 Interrupt. <br/></td></tr>
+<tr class="separator:ga4663d2526dbf5150b3173715ee5bf049"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga72e1189718d84be73378a1c7243668d0"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga72e1189718d84be73378a1c7243668d0"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga72e1189718d84be73378a1c7243668d0">CSL_DSS_DISPC_INTR_VP3_MASK</a>   ((uint32_t) 0x04U)</td></tr>
+<tr class="memdesc:ga72e1189718d84be73378a1c7243668d0"><td class="mdescLeft"> </td><td class="mdescRight">Video Port 3 Interrupt. <br/></td></tr>
+<tr class="separator:ga72e1189718d84be73378a1c7243668d0"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga7c9437915888ed76ced5942c24acf8e7"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga7c9437915888ed76ced5942c24acf8e7"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga7c9437915888ed76ced5942c24acf8e7">CSL_DSS_DISPC_INTR_VP2_MASK</a>   ((uint32_t) 0x02U)</td></tr>
+<tr class="memdesc:ga7c9437915888ed76ced5942c24acf8e7"><td class="mdescLeft"> </td><td class="mdescRight">Video Port 2 Interrupt. <br/></td></tr>
+<tr class="separator:ga7c9437915888ed76ced5942c24acf8e7"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga9c7a9966f4f00cf84f8522ae35009f6f"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga9c7a9966f4f00cf84f8522ae35009f6f"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga9c7a9966f4f00cf84f8522ae35009f6f">CSL_DSS_DISPC_INTR_VP1_MASK</a>   ((uint32_t) 0x01U)</td></tr>
+<tr class="memdesc:ga9c7a9966f4f00cf84f8522ae35009f6f"><td class="mdescLeft"> </td><td class="mdescRight">Video Port 1 Interrupt. <br/></td></tr>
+<tr class="separator:ga9c7a9966f4f00cf84f8522ae35009f6f"><td class="memSeparator" colspan="2"> </td></tr>
+<tr><td colspan="2"><div class="groupHeader">Video Pipeline Interrupt Mask</div></td></tr>
+<tr><td colspan="2"><div class="groupText"><p><a class="anchor" id="CSL_DssVidPipeIntrMask"></a></p>
+</div></td></tr>
+<tr class="memitem:gac01c7ef875638b7ac0110c9306e97e03"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gac01c7ef875638b7ac0110c9306e97e03"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gac01c7ef875638b7ac0110c9306e97e03">CSL_DSS_VID_PIPE_INTR_FBDC_ILLEGALTILE_MASK</a>   ((uint32_t) CSL_DSS_COMMON_M_VID_IRQENABLE_0_FBDC_ILLEGALTILEREQ_EN_MASK)</td></tr>
+<tr class="memdesc:gac01c7ef875638b7ac0110c9306e97e03"><td class="mdescLeft"> </td><td class="mdescRight">Interrupt due to FBDC illegal tile request. <br/></td></tr>
+<tr class="separator:gac01c7ef875638b7ac0110c9306e97e03"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gaeb0df43d6aa106d64cbae9879d850ab2"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaeb0df43d6aa106d64cbae9879d850ab2"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gaeb0df43d6aa106d64cbae9879d850ab2">CSL_DSS_VID_PIPE_INTR_FBDC_CORRUPTTILE_MASK</a>   ((uint32_t) CSL_DSS_COMMON_M_VID_IRQENABLE_0_FBDC_CORRUPTTILE_EN_MASK)</td></tr>
+<tr class="memdesc:gaeb0df43d6aa106d64cbae9879d850ab2"><td class="mdescLeft"> </td><td class="mdescRight">Interrupt due to FBDC corrupted tile detection. <br/></td></tr>
+<tr class="separator:gaeb0df43d6aa106d64cbae9879d850ab2"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga5a394bb4a7b00f928e9287c7838a1a7d"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga5a394bb4a7b00f928e9287c7838a1a7d"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga5a394bb4a7b00f928e9287c7838a1a7d">CSL_DSS_VID_PIPE_INTR_SAFETYVIOLATION_MASK</a>   ((uint32_t) CSL_DSS_COMMON_M_VID_IRQENABLE_0_SAFETYREGION_EN_MASK)</td></tr>
+<tr class="memdesc:ga5a394bb4a7b00f928e9287c7838a1a7d"><td class="mdescLeft"> </td><td class="mdescRight">Interrupt due to safety violation. <br/></td></tr>
+<tr class="separator:ga5a394bb4a7b00f928e9287c7838a1a7d"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gaf2e001a112ba432cac5fec625eede116"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaf2e001a112ba432cac5fec625eede116"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gaf2e001a112ba432cac5fec625eede116">CSL_DSS_VID_PIPE_INTR_WINDOWEND_MASK</a>   ((uint32_t) CSL_DSS_COMMON_M_VID_IRQENABLE_0_VIDENDWINDOW_EN_MASK)</td></tr>
+<tr class="memdesc:gaf2e001a112ba432cac5fec625eede116"><td class="mdescLeft"> </td><td class="mdescRight">Interrupt due to video window end. <br/></td></tr>
+<tr class="separator:gaf2e001a112ba432cac5fec625eede116"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gac87f5c5a2d6fea0b3be605ef429fa7fa"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gac87f5c5a2d6fea0b3be605ef429fa7fa"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gac87f5c5a2d6fea0b3be605ef429fa7fa">CSL_DSS_VID_PIPE_INTR_BUFUNDERFLOW_MASK</a>   ((uint32_t) CSL_DSS_COMMON_M_VID_IRQENABLE_0_VIDBUFFERUNDERFLOW_EN_MASK)</td></tr>
+<tr class="memdesc:gac87f5c5a2d6fea0b3be605ef429fa7fa"><td class="mdescLeft"> </td><td class="mdescRight">Interrupt due to buffer underflow. <br/></td></tr>
+<tr class="separator:gac87f5c5a2d6fea0b3be605ef429fa7fa"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gab333a63a9c79c3af6e7b439ad23f6ee7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gab333a63a9c79c3af6e7b439ad23f6ee7">CSL_DSS_VID_PIPE_INTR_ALL_MASK</a></td></tr>
+<tr class="memdesc:gab333a63a9c79c3af6e7b439ad23f6ee7"><td class="mdescLeft"> </td><td class="mdescRight">All Video Pipe interrupts. <a href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gab333a63a9c79c3af6e7b439ad23f6ee7">More...</a><br/></td></tr>
+<tr class="separator:gab333a63a9c79c3af6e7b439ad23f6ee7"><td class="memSeparator" colspan="2"> </td></tr>
+<tr><td colspan="2"><div class="groupHeader">Video Port Interrupt Mask</div></td></tr>
+<tr><td colspan="2"><div class="groupText"><p><a class="anchor" id="CSL_DssVpIntrMask"></a></p>
+</div></td></tr>
+<tr class="memitem:ga17a731c79f013dff8a68313609310a14"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga17a731c79f013dff8a68313609310a14"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga17a731c79f013dff8a68313609310a14">CSL_DSS_VP_INTR_FRAMEDONE_MASK</a>   ((uint32_t) CSL_DSS_COMMON_M_VP_IRQENABLE_0_VPFRAMEDONE_EN_MASK)</td></tr>
+<tr class="memdesc:ga17a731c79f013dff8a68313609310a14"><td class="mdescLeft"> </td><td class="mdescRight">Frame Done for Video Port. <br/></td></tr>
+<tr class="separator:ga17a731c79f013dff8a68313609310a14"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga1ddaba61f8fa43456fb3d8549f69815f"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga1ddaba61f8fa43456fb3d8549f69815f"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1ddaba61f8fa43456fb3d8549f69815f">CSL_DSS_VP_INTR_VSYNC_MASK</a>   ((uint32_t) CSL_DSS_COMMON_M_VP_IRQENABLE_0_VPVSYNC_EN_MASK)</td></tr>
+<tr class="memdesc:ga1ddaba61f8fa43456fb3d8549f69815f"><td class="mdescLeft"> </td><td class="mdescRight">Vertical Synchronization for Video Port. <br/></td></tr>
+<tr class="separator:ga1ddaba61f8fa43456fb3d8549f69815f"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga323ac381f7d2dacaa7d710894740d796"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga323ac381f7d2dacaa7d710894740d796"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga323ac381f7d2dacaa7d710894740d796">CSL_DSS_VP_INTR_ODDVSYNC_MASK</a>   ((uint32_t) CSL_DSS_COMMON_M_VP_IRQENABLE_0_VPVSYNC_ODD_EN_MASK)</td></tr>
+<tr class="memdesc:ga323ac381f7d2dacaa7d710894740d796"><td class="mdescLeft"> </td><td class="mdescRight">VSYNC for odd field from interlace mode only. <br/></td></tr>
+<tr class="separator:ga323ac381f7d2dacaa7d710894740d796"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gab542da635c1710ea24c5a29e3e6f150c"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gab542da635c1710ea24c5a29e3e6f150c"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gab542da635c1710ea24c5a29e3e6f150c">CSL_DSS_VP_INTR_PROGLINENUM_MASK</a>   ((uint32_t) CSL_DSS_COMMON_M_VP_IRQENABLE_0_VPPROGRAMMEDLINENUMBER_EN_MASK)</td></tr>
+<tr class="memdesc:gab542da635c1710ea24c5a29e3e6f150c"><td class="mdescLeft"> </td><td class="mdescRight">Display scan has reached the programmed user line number. <br/></td></tr>
+<tr class="separator:gab542da635c1710ea24c5a29e3e6f150c"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga92903c6e1b355ed60ca8a15c1673c3b9"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga92903c6e1b355ed60ca8a15c1673c3b9"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga92903c6e1b355ed60ca8a15c1673c3b9">CSL_DSS_VP_INTR_SYNCLOST_MASK</a>   ((uint32_t) CSL_DSS_COMMON_M_VP_IRQENABLE_0_VPSYNCLOST_EN_MASK)</td></tr>
+<tr class="memdesc:ga92903c6e1b355ed60ca8a15c1673c3b9"><td class="mdescLeft"> </td><td class="mdescRight">Synchronization Lost for Video Port. <br/></td></tr>
+<tr class="separator:ga92903c6e1b355ed60ca8a15c1673c3b9"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gaa57aa7b8fc4736ff9598a0b8c5b308c6"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaa57aa7b8fc4736ff9598a0b8c5b308c6"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gaa57aa7b8fc4736ff9598a0b8c5b308c6">CSL_DSS_VP_INTR_ACBIASCOUNT_MASK</a>   ((uint32_t) CSL_DSS_COMMON_M_VP_IRQENABLE_0_ACBIASCOUNTSTATUS_EN_MASK)</td></tr>
+<tr class="memdesc:gaa57aa7b8fc4736ff9598a0b8c5b308c6"><td class="mdescLeft"> </td><td class="mdescRight">AC Bias transition counter has decremented to zero. <br/></td></tr>
+<tr class="separator:gaa57aa7b8fc4736ff9598a0b8c5b308c6"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gaf396f3733114c9eb5478a5a7852fb09e"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaf396f3733114c9eb5478a5a7852fb09e"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gaf396f3733114c9eb5478a5a7852fb09e">CSL_DSS_VP_INTR_SAFETYVIOLATION_REGION1_MASK</a>   ((uint32_t) 0x40U)</td></tr>
+<tr class="memdesc:gaf396f3733114c9eb5478a5a7852fb09e"><td class="mdescLeft"> </td><td class="mdescRight">Interrupt due to region 1 safety violation. <br/></td></tr>
+<tr class="separator:gaf396f3733114c9eb5478a5a7852fb09e"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gab1798bd63882f1a7da07264aa665a06e"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gab1798bd63882f1a7da07264aa665a06e"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gab1798bd63882f1a7da07264aa665a06e">CSL_DSS_VP_INTR_SAFETYVIOLATION_REGION2_MASK</a>   ((uint32_t) 0x80U)</td></tr>
+<tr class="memdesc:gab1798bd63882f1a7da07264aa665a06e"><td class="mdescLeft"> </td><td class="mdescRight">Interrupt due to region 2 safety violation. <br/></td></tr>
+<tr class="separator:gab1798bd63882f1a7da07264aa665a06e"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gaf436eb889d4490f9e0fb4b79ebeea6cb"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaf436eb889d4490f9e0fb4b79ebeea6cb"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gaf436eb889d4490f9e0fb4b79ebeea6cb">CSL_DSS_VP_INTR_SAFETYVIOLATION_REGION3_MASK</a>   ((uint32_t) 0x100U)</td></tr>
+<tr class="memdesc:gaf436eb889d4490f9e0fb4b79ebeea6cb"><td class="mdescLeft"> </td><td class="mdescRight">Interrupt due to region 3 safety violation. <br/></td></tr>
+<tr class="separator:gaf436eb889d4490f9e0fb4b79ebeea6cb"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga84dc6d8ce16d3bc5fd19fb1008f53998"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga84dc6d8ce16d3bc5fd19fb1008f53998"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga84dc6d8ce16d3bc5fd19fb1008f53998">CSL_DSS_VP_INTR_SAFETYVIOLATION_REGION4_MASK</a>   ((uint32_t) 0x200U)</td></tr>
+<tr class="memdesc:ga84dc6d8ce16d3bc5fd19fb1008f53998"><td class="mdescLeft"> </td><td class="mdescRight">Interrupt due to region 4 safety violation. <br/></td></tr>
+<tr class="separator:ga84dc6d8ce16d3bc5fd19fb1008f53998"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga2287bdc0f1a6bb8d7c25590cc580d26a"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga2287bdc0f1a6bb8d7c25590cc580d26a"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga2287bdc0f1a6bb8d7c25590cc580d26a">CSL_DSS_VP_INTR_SECURITYVIOLATION_MASK</a>   ((uint32_t) CSL_DSS_COMMON_M_VP_IRQENABLE_0_SECURITYVIOLATION_EN_MASK)</td></tr>
+<tr class="memdesc:ga2287bdc0f1a6bb8d7c25590cc580d26a"><td class="mdescLeft"> </td><td class="mdescRight">Interrupt due to security violation. <br/></td></tr>
+<tr class="separator:ga2287bdc0f1a6bb8d7c25590cc580d26a"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga4b7fe7d3fbf537386925b2118337517d"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga4b7fe7d3fbf537386925b2118337517d"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga4b7fe7d3fbf537386925b2118337517d">CSL_DSS_VP_INTR_GOBITCLEAR_MASK</a>   ((uint32_t) CSL_DSS_COMMON_M_VP_IRQENABLE_0_VPSYNC_EN_MASK)</td></tr>
+<tr class="memdesc:ga4b7fe7d3fbf537386925b2118337517d"><td class="mdescLeft"> </td><td class="mdescRight">Go bit clear interrupt for VP. <br/></td></tr>
+<tr class="separator:ga4b7fe7d3fbf537386925b2118337517d"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga07b59cbeb37e6d5337a4117ecf688973"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga07b59cbeb37e6d5337a4117ecf688973"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga07b59cbeb37e6d5337a4117ecf688973">CSL_DSS_VP_INTR_SAFETYVIOLATION_REGION5_MASK</a>   ((uint32_t) 0x2000U)</td></tr>
+<tr class="memdesc:ga07b59cbeb37e6d5337a4117ecf688973"><td class="mdescLeft"> </td><td class="mdescRight">Interrupt due to region 5 safety violation. <br/></td></tr>
+<tr class="separator:ga07b59cbeb37e6d5337a4117ecf688973"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gab854dd38750979bf152c0bb7d39f10f9"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gab854dd38750979bf152c0bb7d39f10f9"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gab854dd38750979bf152c0bb7d39f10f9">CSL_DSS_VP_INTR_SAFETYVIOLATION_REGION6_MASK</a>   ((uint32_t) 0x4000U)</td></tr>
+<tr class="memdesc:gab854dd38750979bf152c0bb7d39f10f9"><td class="mdescLeft"> </td><td class="mdescRight">Interrupt due to region 6 safety violation. <br/></td></tr>
+<tr class="separator:gab854dd38750979bf152c0bb7d39f10f9"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gafd2c9bb5bce5224951f713e6a67951cb"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gafd2c9bb5bce5224951f713e6a67951cb"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gafd2c9bb5bce5224951f713e6a67951cb">CSL_DSS_VP_INTR_SAFETYVIOLATION_REGION7_MASK</a>   ((uint32_t) 0x8000U)</td></tr>
+<tr class="memdesc:gafd2c9bb5bce5224951f713e6a67951cb"><td class="mdescLeft"> </td><td class="mdescRight">Interrupt due to region 7 safety violation. <br/></td></tr>
+<tr class="separator:gafd2c9bb5bce5224951f713e6a67951cb"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gafee920aa4503ff1c8ec7d91a028802ba"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gafee920aa4503ff1c8ec7d91a028802ba"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gafee920aa4503ff1c8ec7d91a028802ba">CSL_DSS_VP_INTR_SAFETYVIOLATION_REGION8_MASK</a>   ((uint32_t) 0x10000U)</td></tr>
+<tr class="memdesc:gafee920aa4503ff1c8ec7d91a028802ba"><td class="mdescLeft"> </td><td class="mdescRight">Interrupt due to region 8 safety violation. <br/></td></tr>
+<tr class="separator:gafee920aa4503ff1c8ec7d91a028802ba"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga062132a334862eff31df843867a5a9c1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga062132a334862eff31df843867a5a9c1">CSL_DSS_VP_INTR_ALL_MASK</a></td></tr>
+<tr class="memdesc:ga062132a334862eff31df843867a5a9c1"><td class="mdescLeft"> </td><td class="mdescRight">All Video Port interrupts. <a href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga062132a334862eff31df843867a5a9c1">More...</a><br/></td></tr>
+<tr class="separator:ga062132a334862eff31df843867a5a9c1"><td class="memSeparator" colspan="2"> </td></tr>
+<tr><td colspan="2"><div class="groupHeader">Write back Pipeline Interrupt Mask</div></td></tr>
+<tr><td colspan="2"><div class="groupText"><p><a class="anchor" id="CSL_DssWBPipeIntrMask"></a></p>
+</div></td></tr>
+<tr class="memitem:ga7956cca4dac339f72e3bfd028cef8aea"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga7956cca4dac339f72e3bfd028cef8aea"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga7956cca4dac339f72e3bfd028cef8aea">CSL_DSS_WB_PIPE_INTR_WBSYNC_MASK</a>   ((uint32_t) CSL_DSS_COMMON_M_WB_IRQENABLE_WBSYNC_EN_MASK)</td></tr>
+<tr class="memdesc:ga7956cca4dac339f72e3bfd028cef8aea"><td class="mdescLeft"> </td><td class="mdescRight">Interrupt due to completion of write back sync. <br/></td></tr>
+<tr class="separator:ga7956cca4dac339f72e3bfd028cef8aea"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga1fcec556feabbf38743c1ff5ece580de"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga1fcec556feabbf38743c1ff5ece580de"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1fcec556feabbf38743c1ff5ece580de">CSL_DSS_WB_PIPE_INTR_SECURITYVIOLATION_MASK</a>   ((uint32_t) CSL_DSS_COMMON_M_WB_IRQENABLE_SECURITYVIOLATION_EN_MASK)</td></tr>
+<tr class="memdesc:ga1fcec556feabbf38743c1ff5ece580de"><td class="mdescLeft"> </td><td class="mdescRight">Interrupt due to security violation. <br/></td></tr>
+<tr class="separator:ga1fcec556feabbf38743c1ff5ece580de"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga21c87fbab481fb6ea24b202b12610a35"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga21c87fbab481fb6ea24b202b12610a35"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga21c87fbab481fb6ea24b202b12610a35">CSL_DSS_WB_PIPE_INTR_FRAMEDONE_MASK</a>   ((uint32_t) CSL_DSS_COMMON_M_WB_IRQENABLE_WBFRAMEDONE_EN_MASK)</td></tr>
+<tr class="memdesc:ga21c87fbab481fb6ea24b202b12610a35"><td class="mdescLeft"> </td><td class="mdescRight">Interrupt due to write back frame completion. <br/></td></tr>
+<tr class="separator:ga21c87fbab481fb6ea24b202b12610a35"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga49798f6dd7f9930bcde282c21197c739"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga49798f6dd7f9930bcde282c21197c739"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga49798f6dd7f9930bcde282c21197c739">CSL_DSS_WB_PIPE_INTR_UNCOMPLETE_MASK</a>   ((uint32_t) CSL_DSS_COMMON_M_WB_IRQENABLE_WBUNCOMPLETEERROR_EN_MASK)</td></tr>
+<tr class="memdesc:ga49798f6dd7f9930bcde282c21197c739"><td class="mdescLeft"> </td><td class="mdescRight">Interrupt due to buffer flush before full drain (Only Capture WB) <br/></td></tr>
+<tr class="separator:ga49798f6dd7f9930bcde282c21197c739"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga9a426ebaaf7f08452b96825dff7dd6ea"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga9a426ebaaf7f08452b96825dff7dd6ea"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga9a426ebaaf7f08452b96825dff7dd6ea">CSL_DSS_WB_PIPE_INTR_OVERFLOW_MASK</a>   ((uint32_t) CSL_DSS_COMMON_M_WB_IRQENABLE_WBBUFFEROVERFLOW_EN_MASK)</td></tr>
+<tr class="memdesc:ga9a426ebaaf7f08452b96825dff7dd6ea"><td class="mdescLeft"> </td><td class="mdescRight">Interrupt due to buffer overflow. <br/></td></tr>
+<tr class="separator:ga9a426ebaaf7f08452b96825dff7dd6ea"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gaa87662a09ae286e277da4b5ee2243b71"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gaa87662a09ae286e277da4b5ee2243b71">CSL_DSS_WB_PIPE_INTR_ALL_MASK</a></td></tr>
+<tr class="memdesc:gaa87662a09ae286e277da4b5ee2243b71"><td class="mdescLeft"> </td><td class="mdescRight">All Write Back Pipe interrupts. <a href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gaa87662a09ae286e277da4b5ee2243b71">More...</a><br/></td></tr>
+<tr class="separator:gaa87662a09ae286e277da4b5ee2243b71"><td class="memSeparator" colspan="2"> </td></tr>
+<tr><td colspan="2"><div class="groupHeader">Mflag Start Mode</div></td></tr>
+<tr><td colspan="2"><div class="groupText"><p><a class="anchor" id="CSL_DssMflagStartMode"></a></p>
+</div></td></tr>
+<tr class="memitem:ga8463a9a268552ec6233a928947813a7d"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga8463a9a268552ec6233a928947813a7d"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga8463a9a268552ec6233a928947813a7d">CSL_DSS_MFLAG_START_NORMAL</a>   ((uint32_t) CSL_DSS_COMMON_M_DISPC_GLOBAL_MFLAG_ATTRIBUTE_MFLAG_START_VAL_MFLAGNORMALSTARTMODE)</td></tr>
+<tr class="memdesc:ga8463a9a268552ec6233a928947813a7d"><td class="mdescLeft"> </td><td class="mdescRight">Mflag of each pipe is kept at 0 until preload is reached. <br/></td></tr>
+<tr class="separator:ga8463a9a268552ec6233a928947813a7d"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga25a7a13a5ed7fa79de52587991cd6e8c"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga25a7a13a5ed7fa79de52587991cd6e8c"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga25a7a13a5ed7fa79de52587991cd6e8c">CSL_DSS_MFLAG_START_FORCED</a>   ((uint32_t) CSL_DSS_COMMON_M_DISPC_GLOBAL_MFLAG_ATTRIBUTE_MFLAG_START_VAL_MFLAGFORCESTARTMODE)</td></tr>
+<tr class="memdesc:ga25a7a13a5ed7fa79de52587991cd6e8c"><td class="mdescLeft"> </td><td class="mdescRight">Mflag is driven as per Mflag Ctrl. <br/></td></tr>
+<tr class="separator:ga25a7a13a5ed7fa79de52587991cd6e8c"><td class="memSeparator" colspan="2"> </td></tr>
+<tr><td colspan="2"><div class="groupHeader">Mflag Control</div></td></tr>
+<tr><td colspan="2"><div class="groupText"><p><a class="anchor" id="CSL_DssMflagCtrl"></a></p>
+</div></td></tr>
+<tr class="memitem:ga8a1fdde2ee44a5d4f758add66d1e531a"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga8a1fdde2ee44a5d4f758add66d1e531a"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga8a1fdde2ee44a5d4f758add66d1e531a">CSL_DSS_MFLAG_CTRL_DISABLED</a>   ((uint32_t) CSL_DSS_COMMON_M_DISPC_GLOBAL_MFLAG_ATTRIBUTE_MFLAG_CTRL_VAL_MFLAGDIS)</td></tr>
+<tr class="memdesc:ga8a1fdde2ee44a5d4f758add66d1e531a"><td class="mdescLeft"> </td><td class="mdescRight">Mflag is disabled. <br/></td></tr>
+<tr class="separator:ga8a1fdde2ee44a5d4f758add66d1e531a"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gae33f049f22cfce779d267a22ba79d1e3"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gae33f049f22cfce779d267a22ba79d1e3"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gae33f049f22cfce779d267a22ba79d1e3">CSL_DSS_MFLAG_CTRL_FORCE_ENABLE</a>   ((uint32_t) CSL_DSS_COMMON_M_DISPC_GLOBAL_MFLAG_ATTRIBUTE_MFLAG_CTRL_VAL_MFLAGFORCE)</td></tr>
+<tr class="memdesc:gae33f049f22cfce779d267a22ba79d1e3"><td class="mdescLeft"> </td><td class="mdescRight">Mflag is force enabled. <br/></td></tr>
+<tr class="separator:gae33f049f22cfce779d267a22ba79d1e3"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gafd85bc61dad64ede428e21526edd470a"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gafd85bc61dad64ede428e21526edd470a"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gafd85bc61dad64ede428e21526edd470a">CSL_DSS_MFLAG_CTRL_DYNAMIC</a>   ((uint32_t) CSL_DSS_COMMON_M_DISPC_GLOBAL_MFLAG_ATTRIBUTE_MFLAG_CTRL_VAL_MFLAGEN)</td></tr>
+<tr class="memdesc:gafd85bc61dad64ede428e21526edd470a"><td class="mdescLeft"> </td><td class="mdescRight">Mflag signal is set dynamically as per rules. <br/></td></tr>
+<tr class="separator:gafd85bc61dad64ede428e21526edd470a"><td class="memSeparator" colspan="2"> </td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="typedef-members"></a>
+Typedefs</h2></td></tr>
+<tr class="memitem:ga1b5d2dc642484dd5b5af1cd7db50ef74"><td class="memItemLeft" align="right" valign="top">typedef CSL_dss_common_mRegs </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1b5d2dc642484dd5b5af1cd7db50ef74">CSL_dss_commRegs</a></td></tr>
+<tr class="memdesc:ga1b5d2dc642484dd5b5af1cd7db50ef74"><td class="mdescLeft"> </td><td class="mdescRight">DSS Common Registers. <a href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1b5d2dc642484dd5b5af1cd7db50ef74">More...</a><br/></td></tr>
+<tr class="separator:ga1b5d2dc642484dd5b5af1cd7db50ef74"><td class="memSeparator" colspan="2"> </td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a>
+Functions</h2></td></tr>
+<tr class="memitem:ga567b2f823b70e843ceb9c4ca8c501cae"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga567b2f823b70e843ceb9c4ca8c501cae">CSL_dssModuleReset</a> (<a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1b5d2dc642484dd5b5af1cd7db50ef74">CSL_dss_commRegs</a> *commRegs)</td></tr>
+<tr class="memdesc:ga567b2f823b70e843ceb9c4ca8c501cae"><td class="mdescLeft"> </td><td class="mdescRight">Reset the DSS Module. Application should make sure Video Ports are disabled before calling this API. <a href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga567b2f823b70e843ceb9c4ca8c501cae">More...</a><br/></td></tr>
+<tr class="separator:ga567b2f823b70e843ceb9c4ca8c501cae"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga78ae8cafecdf61459530ae0ecaee1312"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga78ae8cafecdf61459530ae0ecaee1312">CSL_dssEnableDispcIntr</a> (<a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1b5d2dc642484dd5b5af1cd7db50ef74">CSL_dss_commRegs</a> *commRegs, uint32_t intrMask, uint32_t intrEnable)</td></tr>
+<tr class="memdesc:ga78ae8cafecdf61459530ae0ecaee1312"><td class="mdescLeft"> </td><td class="mdescRight">Enable/disable the interrupts at DSS top level. <a href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga78ae8cafecdf61459530ae0ecaee1312">More...</a><br/></td></tr>
+<tr class="separator:ga78ae8cafecdf61459530ae0ecaee1312"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga1d1f5ed599418de87535e92ff113dbae"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1d1f5ed599418de87535e92ff113dbae">CSL_dssEnablePipeIntr</a> (<a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1b5d2dc642484dd5b5af1cd7db50ef74">CSL_dss_commRegs</a> *commRegs, uint32_t vidPipeId, uint32_t intrMask, uint32_t intrEnable)</td></tr>
+<tr class="memdesc:ga1d1f5ed599418de87535e92ff113dbae"><td class="mdescLeft"> </td><td class="mdescRight">Enable/disable the interrupts for Video Pipe. <a href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1d1f5ed599418de87535e92ff113dbae">More...</a><br/></td></tr>
+<tr class="separator:ga1d1f5ed599418de87535e92ff113dbae"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gabc7928512f14f647d32d899a9850b4ad"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gabc7928512f14f647d32d899a9850b4ad">CSL_dssEnableVpIntr</a> (<a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1b5d2dc642484dd5b5af1cd7db50ef74">CSL_dss_commRegs</a> *commRegs, uint32_t portId, uint32_t intrMask, uint32_t intrEnable)</td></tr>
+<tr class="memdesc:gabc7928512f14f647d32d899a9850b4ad"><td class="mdescLeft"> </td><td class="mdescRight">Enable/disable the interrupts for Video Port. <a href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gabc7928512f14f647d32d899a9850b4ad">More...</a><br/></td></tr>
+<tr class="separator:gabc7928512f14f647d32d899a9850b4ad"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga2f59e10e9d38932af384543d274dc90c"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga2f59e10e9d38932af384543d274dc90c">CSL_dssClearDispcIntr</a> (<a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1b5d2dc642484dd5b5af1cd7db50ef74">CSL_dss_commRegs</a> *commRegs, uint32_t intrMask)</td></tr>
+<tr class="memdesc:ga2f59e10e9d38932af384543d274dc90c"><td class="mdescLeft"> </td><td class="mdescRight">Clear the interrupts at DSS top level. <a href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga2f59e10e9d38932af384543d274dc90c">More...</a><br/></td></tr>
+<tr class="separator:ga2f59e10e9d38932af384543d274dc90c"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga1c2b89748e481bf4651cf4b87805177d"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1c2b89748e481bf4651cf4b87805177d">CSL_dssClearPipeIntr</a> (<a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1b5d2dc642484dd5b5af1cd7db50ef74">CSL_dss_commRegs</a> *commRegs, uint32_t vidPipeId, uint32_t intrMask)</td></tr>
+<tr class="memdesc:ga1c2b89748e481bf4651cf4b87805177d"><td class="mdescLeft"> </td><td class="mdescRight">Clear the interrupts for Video Pipe. <a href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1c2b89748e481bf4651cf4b87805177d">More...</a><br/></td></tr>
+<tr class="separator:ga1c2b89748e481bf4651cf4b87805177d"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga086ca7d14c9f2a75305035c512972c18"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga086ca7d14c9f2a75305035c512972c18">CSL_dssClearVpIntr</a> (<a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1b5d2dc642484dd5b5af1cd7db50ef74">CSL_dss_commRegs</a> *commRegs, uint32_t portId, uint32_t intrMask)</td></tr>
+<tr class="memdesc:ga086ca7d14c9f2a75305035c512972c18"><td class="mdescLeft"> </td><td class="mdescRight">Clear the interrupts for Video Port. <a href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga086ca7d14c9f2a75305035c512972c18">More...</a><br/></td></tr>
+<tr class="separator:ga086ca7d14c9f2a75305035c512972c18"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga196052d031e6e46bc99f4631218d2da7"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga196052d031e6e46bc99f4631218d2da7">CSL_dssGetDispcIntrStatus</a> (const <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1b5d2dc642484dd5b5af1cd7db50ef74">CSL_dss_commRegs</a> *commRegs)</td></tr>
+<tr class="memdesc:ga196052d031e6e46bc99f4631218d2da7"><td class="mdescLeft"> </td><td class="mdescRight">Get the top level interrupt status of DSS. <a href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga196052d031e6e46bc99f4631218d2da7">More...</a><br/></td></tr>
+<tr class="separator:ga196052d031e6e46bc99f4631218d2da7"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gab25aea830bb6567a67be6018fbce58e2"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gab25aea830bb6567a67be6018fbce58e2">CSL_dssGetPipeIntrStatus</a> (const <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1b5d2dc642484dd5b5af1cd7db50ef74">CSL_dss_commRegs</a> *commRegs, uint32_t vidPipeId)</td></tr>
+<tr class="memdesc:gab25aea830bb6567a67be6018fbce58e2"><td class="mdescLeft"> </td><td class="mdescRight">Get the interrupt status of Video Pipe. <a href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gab25aea830bb6567a67be6018fbce58e2">More...</a><br/></td></tr>
+<tr class="separator:gab25aea830bb6567a67be6018fbce58e2"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga7202424e4a3404aaf894e294be0a1f7d"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga7202424e4a3404aaf894e294be0a1f7d">CSL_dssGetVpIntrStatus</a> (const <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1b5d2dc642484dd5b5af1cd7db50ef74">CSL_dss_commRegs</a> *commRegs, uint32_t portId)</td></tr>
+<tr class="memdesc:ga7202424e4a3404aaf894e294be0a1f7d"><td class="mdescLeft"> </td><td class="mdescRight">Get the interrupt status of Video Port. <a href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga7202424e4a3404aaf894e294be0a1f7d">More...</a><br/></td></tr>
+<tr class="separator:ga7202424e4a3404aaf894e294be0a1f7d"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga51649681f3f478ab1c44d97aa3ed8323"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga51649681f3f478ab1c44d97aa3ed8323">CSL_dssSetGlobalMflagConfig</a> (<a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1b5d2dc642484dd5b5af1cd7db50ef74">CSL_dss_commRegs</a> *commRegs, const <a class="el" href="struct_c_s_l___dss_global_m_flag_cfg.html">CSL_DssGlobalMFlagCfg</a> *mflagCfg)</td></tr>
+<tr class="memdesc:ga51649681f3f478ab1c44d97aa3ed8323"><td class="mdescLeft"> </td><td class="mdescRight">Set the global MFLAG configuration. <a href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga51649681f3f478ab1c44d97aa3ed8323">More...</a><br/></td></tr>
+<tr class="separator:ga51649681f3f478ab1c44d97aa3ed8323"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gad3490bc78c9441400a4a77c933006f6c"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gad3490bc78c9441400a4a77c933006f6c">CSL_dssGlobalVpEnable</a> (<a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1b5d2dc642484dd5b5af1cd7db50ef74">CSL_dss_commRegs</a> *commRegs, uint32_t portIdMask)</td></tr>
+<tr class="memdesc:gad3490bc78c9441400a4a77c933006f6c"><td class="mdescLeft"> </td><td class="mdescRight">Enable the global VP enable bit. This allows setting multiple outputs synchronously. The 'OR' result of different masks can be used as input parameter. <a href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gad3490bc78c9441400a4a77c933006f6c">More...</a><br/></td></tr>
+<tr class="separator:gad3490bc78c9441400a4a77c933006f6c"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga6c62a23a768c0ce357db64365ebdc0b0"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga6c62a23a768c0ce357db64365ebdc0b0">CSL_dssGlobalVpGoBitEnable</a> (<a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1b5d2dc642484dd5b5af1cd7db50ef74">CSL_dss_commRegs</a> *commRegs, uint32_t portIdMask)</td></tr>
+<tr class="memdesc:ga6c62a23a768c0ce357db64365ebdc0b0"><td class="mdescLeft"> </td><td class="mdescRight">Enable the global VP go bit. This allows setting multiple outputs synchronously. The 'OR' result of different masks can be used as input parameter. <a href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga6c62a23a768c0ce357db64365ebdc0b0">More...</a><br/></td></tr>
+<tr class="separator:ga6c62a23a768c0ce357db64365ebdc0b0"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga1ce4591b123f52bf6e6cc00a485fcd38"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1ce4591b123f52bf6e6cc00a485fcd38">CSL_dssSetCbaConfig</a> (<a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1b5d2dc642484dd5b5af1cd7db50ef74">CSL_dss_commRegs</a> *commRegs, const <a class="el" href="struct_c_s_l___dss_cba_cfg.html">CSL_DssCbaCfg</a> *cbaCfg)</td></tr>
+<tr class="memdesc:ga1ce4591b123f52bf6e6cc00a485fcd38"><td class="mdescLeft"> </td><td class="mdescRight">Set the CBA configuration. <a href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1ce4591b123f52bf6e6cc00a485fcd38">More...</a><br/></td></tr>
+<tr class="separator:ga1ce4591b123f52bf6e6cc00a485fcd38"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga1c215888b011a5cca5880679ea560f74"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1c215888b011a5cca5880679ea560f74">CSL_dssConnectVpToDpi</a> (<a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1b5d2dc642484dd5b5af1cd7db50ef74">CSL_dss_commRegs</a> *commRegs, uint32_t portId, uint32_t dpiId)</td></tr>
+<tr class="memdesc:ga1c215888b011a5cca5880679ea560f74"><td class="mdescLeft"> </td><td class="mdescRight">This API can be used to select the VP connection to DPI. <a href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1c215888b011a5cca5880679ea560f74">More...</a><br/></td></tr>
+<tr class="separator:ga1c215888b011a5cca5880679ea560f74"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga67eb3b87f230f3d3598ff1ea3c8ccbbe"><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga67eb3b87f230f3d3598ff1ea3c8ccbbe">CSL_dssGlobalMFlagCfgInit</a> (<a class="el" href="struct_c_s_l___dss_global_m_flag_cfg.html">CSL_DssGlobalMFlagCfg</a> *mflagCfg)</td></tr>
+<tr class="memdesc:ga67eb3b87f230f3d3598ff1ea3c8ccbbe"><td class="mdescLeft"> </td><td class="mdescRight"><a class="el" href="struct_c_s_l___dss_global_m_flag_cfg.html" title="DSS Global MFLAG Config parameters. ">CSL_DssGlobalMFlagCfg</a> structure init function. <a href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga67eb3b87f230f3d3598ff1ea3c8ccbbe">More...</a><br/></td></tr>
+<tr class="separator:ga67eb3b87f230f3d3598ff1ea3c8ccbbe"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gafa9009a2a94ae2222dfaaa166de1f33d"><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gafa9009a2a94ae2222dfaaa166de1f33d">CSL_dssCbaCfgInit</a> (<a class="el" href="struct_c_s_l___dss_cba_cfg.html">CSL_DssCbaCfg</a> *cbaCfg)</td></tr>
+<tr class="memdesc:gafa9009a2a94ae2222dfaaa166de1f33d"><td class="mdescLeft"> </td><td class="mdescRight"><a class="el" href="struct_c_s_l___dss_cba_cfg.html" title="DSS CBA Config parameters. ">CSL_DssCbaCfg</a> structure init function. <a href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gafa9009a2a94ae2222dfaaa166de1f33d">More...</a><br/></td></tr>
+<tr class="separator:gafa9009a2a94ae2222dfaaa166de1f33d"><td class="memSeparator" colspan="2"> </td></tr>
+</table>
+<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
+<div class="textblock"><p>DSS Common CSL FL interface file. </p>
+</div></div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/csl__dss_overlay_8h.html b/packages/ti/drv/dss/docs/doxygen/html/csl__dss_overlay_8h.html
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+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
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+<title>csl_dssOverlay.h File Reference</title>
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+<div id="nav-path" class="navpath">
+ <ul>
+<li class="navelem"><a class="el" href="dir_f5943f6d28c724c9867ac930658f5901.html">csl</a></li><li class="navelem"><a class="el" href="dir_2c013fc7e98dc8ade314eba46bcbb0d6.html">src</a></li><li class="navelem"><a class="el" href="dir_063bd5b357e44d632c140cb38e979030.html">ip</a></li><li class="navelem"><a class="el" href="dir_9601e7bd9bffb8db00e0c1272827daa6.html">dss</a></li><li class="navelem"><a class="el" href="dir_61ed5367bdc2fa7807323d7b06750347.html">V4</a></li> </ul>
+</div>
+</div><!-- top -->
+<div class="header">
+ <div class="summary">
+<a href="#nested-classes">Data Structures</a> |
+<a href="#typedef-members">Typedefs</a> |
+<a href="#func-members">Functions</a> </div>
+ <div class="headertitle">
+<div class="title">csl_dssOverlay.h File Reference<div class="ingroups"><a class="el" href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html">DSS Overlay CSL FL</a></div></div> </div>
+</div><!--header-->
+<div class="contents">
+
+<p>DSS Overlay CSL FL interface file.
+<a href="#details">More...</a></p>
+<table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="nested-classes"></a>
+Data Structures</h2></td></tr>
+<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_overlay_cfg.html">CSL_DssOverlayCfg</a></td></tr>
+<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">Configuration for DSS Overlay. <a href="struct_c_s_l___dss_overlay_cfg.html#details">More...</a><br/></td></tr>
+<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_overlay_layer_cfg.html">CSL_DssOverlayLayerCfg</a></td></tr>
+<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">Configuration for selecting overlay input layers. <a href="struct_c_s_l___dss_overlay_layer_cfg.html#details">More...</a><br/></td></tr>
+<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_overlay_pipe_pos_cfg.html">CSL_DssOverlayPipePosCfg</a></td></tr>
+<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">Video Pipe Position Configuration in Overlay. <a href="struct_c_s_l___dss_overlay_pipe_pos_cfg.html#details">More...</a><br/></td></tr>
+<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
+Macros</h2></td></tr>
+<tr><td colspan="2"><div class="groupHeader">DSS Overlay Transparency Color Key Selection</div></td></tr>
+<tr><td colspan="2"><div class="groupText"><p><a class="anchor" id="CSL_DssOverlayTransColor"></a></p>
+</div></td></tr>
+<tr class="memitem:ga340c7a53b58c9fed267c3164ec0a03c9"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga340c7a53b58c9fed267c3164ec0a03c9"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#ga340c7a53b58c9fed267c3164ec0a03c9">CSL_DSS_OVERLAY_TRANS_COLOR_DEST</a>   ((uint32_t) CSL_DSS_OVR1_CONFIG_TCKLCDSELECTION_VAL_GDTK)</td></tr>
+<tr class="memdesc:ga340c7a53b58c9fed267c3164ec0a03c9"><td class="mdescLeft"> </td><td class="mdescRight">Destination transparency color key selected. <br/></td></tr>
+<tr class="separator:ga340c7a53b58c9fed267c3164ec0a03c9"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga164f53537368dff35827675dfda8cf12"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga164f53537368dff35827675dfda8cf12"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#ga164f53537368dff35827675dfda8cf12">CSL_DSS_OVERLAY_TRANS_COLOR_SRC</a>   ((uint32_t) CSL_DSS_OVR1_CONFIG_TCKLCDSELECTION_VAL_VSTK)</td></tr>
+<tr class="memdesc:ga164f53537368dff35827675dfda8cf12"><td class="mdescLeft"> </td><td class="mdescRight">Source transparency color key selected. <br/></td></tr>
+<tr class="separator:ga164f53537368dff35827675dfda8cf12"><td class="memSeparator" colspan="2"> </td></tr>
+<tr><td colspan="2"><div class="groupHeader">DSS Overlay Layer Number</div></td></tr>
+<tr><td colspan="2"><div class="groupText"><p><a class="anchor" id="CSL_DssOverlayLayerNum"></a></p>
+</div></td></tr>
+<tr class="memitem:ga2488889aa0b927be4a00ec57b8b75f70"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga2488889aa0b927be4a00ec57b8b75f70"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#ga2488889aa0b927be4a00ec57b8b75f70">CSL_DSS_OVERLAY_LAYER_NUM_0</a>   ((uint32_t) 0x0U)</td></tr>
+<tr class="memdesc:ga2488889aa0b927be4a00ec57b8b75f70"><td class="mdescLeft"> </td><td class="mdescRight">Overlay Layer 0. <br/></td></tr>
+<tr class="separator:ga2488889aa0b927be4a00ec57b8b75f70"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gabe9d38d2a4ef636da3b3a261cbb94f71"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gabe9d38d2a4ef636da3b3a261cbb94f71"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#gabe9d38d2a4ef636da3b3a261cbb94f71">CSL_DSS_OVERLAY_LAYER_NUM_1</a>   ((uint32_t) 0x1U)</td></tr>
+<tr class="memdesc:gabe9d38d2a4ef636da3b3a261cbb94f71"><td class="mdescLeft"> </td><td class="mdescRight">Overlay Layer 1. <br/></td></tr>
+<tr class="separator:gabe9d38d2a4ef636da3b3a261cbb94f71"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga97d71d9f152602cd81c45e7cdfa3a92d"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga97d71d9f152602cd81c45e7cdfa3a92d"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#ga97d71d9f152602cd81c45e7cdfa3a92d">CSL_DSS_OVERLAY_LAYER_NUM_2</a>   ((uint32_t) 0x2U)</td></tr>
+<tr class="memdesc:ga97d71d9f152602cd81c45e7cdfa3a92d"><td class="mdescLeft"> </td><td class="mdescRight">Overlay Layer 2. <br/></td></tr>
+<tr class="separator:ga97d71d9f152602cd81c45e7cdfa3a92d"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga4f0066fbe34c973483392a7128eb598a"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga4f0066fbe34c973483392a7128eb598a"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#ga4f0066fbe34c973483392a7128eb598a">CSL_DSS_OVERLAY_LAYER_NUM_3</a>   ((uint32_t) 0x3U)</td></tr>
+<tr class="memdesc:ga4f0066fbe34c973483392a7128eb598a"><td class="mdescLeft"> </td><td class="mdescRight">Overlay Layer 3. <br/></td></tr>
+<tr class="separator:ga4f0066fbe34c973483392a7128eb598a"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga2a682ed470d58605922ee2106033a5f8"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga2a682ed470d58605922ee2106033a5f8"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#ga2a682ed470d58605922ee2106033a5f8">CSL_DSS_OVERLAY_LAYER_MAX</a>   ((uint32_t) 0x4U)</td></tr>
+<tr class="memdesc:ga2a682ed470d58605922ee2106033a5f8"><td class="mdescLeft"> </td><td class="mdescRight">Maximum overlay layers. <br/></td></tr>
+<tr class="separator:ga2a682ed470d58605922ee2106033a5f8"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gae0d0be4608934fba2afa072b6716220a"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gae0d0be4608934fba2afa072b6716220a"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#gae0d0be4608934fba2afa072b6716220a">CSL_DSS_OVERLAY_LAYER_INVALID</a>   ((uint32_t) 0xFFU)</td></tr>
+<tr class="memdesc:gae0d0be4608934fba2afa072b6716220a"><td class="mdescLeft"> </td><td class="mdescRight">Invalid Overlay Layer. <br/></td></tr>
+<tr class="separator:gae0d0be4608934fba2afa072b6716220a"><td class="memSeparator" colspan="2"> </td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="typedef-members"></a>
+Typedefs</h2></td></tr>
+<tr class="memitem:ga835adb8a42f16beefbfb5440b9dede63"><td class="memItemLeft" align="right" valign="top">typedef CSL_dss_ovr1Regs </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#ga835adb8a42f16beefbfb5440b9dede63">CSL_dss_overlayRegs</a></td></tr>
+<tr class="memdesc:ga835adb8a42f16beefbfb5440b9dede63"><td class="mdescLeft"> </td><td class="mdescRight">DSS Overlay Registers. <a href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#ga835adb8a42f16beefbfb5440b9dede63">More...</a><br/></td></tr>
+<tr class="separator:ga835adb8a42f16beefbfb5440b9dede63"><td class="memSeparator" colspan="2"> </td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a>
+Functions</h2></td></tr>
+<tr class="memitem:ga03a77e67fa911acc5e905faafe06a7cc"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#ga03a77e67fa911acc5e905faafe06a7cc">CSL_dssOverlaySetConfig</a> (<a class="el" href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#ga835adb8a42f16beefbfb5440b9dede63">CSL_dss_overlayRegs</a> *overlayRegs, const <a class="el" href="struct_c_s_l___dss_overlay_cfg.html">CSL_DssOverlayCfg</a> *overlayCfg)</td></tr>
+<tr class="memdesc:ga03a77e67fa911acc5e905faafe06a7cc"><td class="mdescLeft"> </td><td class="mdescRight">Configure the Overlay Params. <a href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#ga03a77e67fa911acc5e905faafe06a7cc">More...</a><br/></td></tr>
+<tr class="separator:ga03a77e67fa911acc5e905faafe06a7cc"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gad36724322f426d4022c944b5fc53f3fd"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#gad36724322f426d4022c944b5fc53f3fd">CSL_dssOverlayColorBarEnable</a> (<a class="el" href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#ga835adb8a42f16beefbfb5440b9dede63">CSL_dss_overlayRegs</a> *overlayRegs, uint32_t enable)</td></tr>
+<tr class="memdesc:gad36724322f426d4022c944b5fc53f3fd"><td class="mdescLeft"> </td><td class="mdescRight">Enable the Color Bar in DSS Overlay. <a href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#gad36724322f426d4022c944b5fc53f3fd">More...</a><br/></td></tr>
+<tr class="separator:gad36724322f426d4022c944b5fc53f3fd"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga0854ef7eebe8ec3dabd739cda8a0a87b"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#ga0854ef7eebe8ec3dabd739cda8a0a87b">CSL_dssOverlaySetLayerConfig</a> (<a class="el" href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#ga835adb8a42f16beefbfb5440b9dede63">CSL_dss_overlayRegs</a> *overlayRegs, const <a class="el" href="struct_c_s_l___dss_overlay_layer_cfg.html">CSL_DssOverlayLayerCfg</a> *layerCfg)</td></tr>
+<tr class="memdesc:ga0854ef7eebe8ec3dabd739cda8a0a87b"><td class="mdescLeft"> </td><td class="mdescRight">Configure the Overlay input selection. <a href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#ga0854ef7eebe8ec3dabd739cda8a0a87b">More...</a><br/></td></tr>
+<tr class="separator:ga0854ef7eebe8ec3dabd739cda8a0a87b"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga04705e269d2be5aa01508e3f5dafdf7c"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#ga04705e269d2be5aa01508e3f5dafdf7c">CSL_dssOverlaySetPipePosConfig</a> (<a class="el" href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#ga835adb8a42f16beefbfb5440b9dede63">CSL_dss_overlayRegs</a> *overlayRegs, const <a class="el" href="struct_c_s_l___dss_overlay_pipe_pos_cfg.html">CSL_DssOverlayPipePosCfg</a> *pipePosCfg, uint32_t layerNum)</td></tr>
+<tr class="memdesc:ga04705e269d2be5aa01508e3f5dafdf7c"><td class="mdescLeft"> </td><td class="mdescRight">Configure the Video Pipe Position in Overlay. <a href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#ga04705e269d2be5aa01508e3f5dafdf7c">More...</a><br/></td></tr>
+<tr class="separator:ga04705e269d2be5aa01508e3f5dafdf7c"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gae88aaba46e12dfb2f72c93691ea14c99"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#gae88aaba46e12dfb2f72c93691ea14c99">CSL_dssOverlayGetEnabledPipeLayerNum</a> (const <a class="el" href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#ga835adb8a42f16beefbfb5440b9dede63">CSL_dss_overlayRegs</a> *overlayRegs, uint32_t pipeId)</td></tr>
+<tr class="memdesc:gae88aaba46e12dfb2f72c93691ea14c99"><td class="mdescLeft"> </td><td class="mdescRight">Get the layer number where a particular Video Pipe is connected. <a href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#gae88aaba46e12dfb2f72c93691ea14c99">More...</a><br/></td></tr>
+<tr class="separator:gae88aaba46e12dfb2f72c93691ea14c99"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga5f9f1191f5d62fa0747616ae87e3cc65"><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#ga5f9f1191f5d62fa0747616ae87e3cc65">CSL_dssOverlayCfgInit</a> (<a class="el" href="struct_c_s_l___dss_overlay_cfg.html">CSL_DssOverlayCfg</a> *overlayCfg)</td></tr>
+<tr class="memdesc:ga5f9f1191f5d62fa0747616ae87e3cc65"><td class="mdescLeft"> </td><td class="mdescRight"><a class="el" href="struct_c_s_l___dss_overlay_cfg.html" title="Configuration for DSS Overlay. ">CSL_DssOverlayCfg</a> structure init function. <a href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#ga5f9f1191f5d62fa0747616ae87e3cc65">More...</a><br/></td></tr>
+<tr class="separator:ga5f9f1191f5d62fa0747616ae87e3cc65"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gae7481e9db942be0537425939b6387a22"><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#gae7481e9db942be0537425939b6387a22">CSL_dssOverlayLayerCfgInit</a> (<a class="el" href="struct_c_s_l___dss_overlay_layer_cfg.html">CSL_DssOverlayLayerCfg</a> *layerCfg)</td></tr>
+<tr class="memdesc:gae7481e9db942be0537425939b6387a22"><td class="mdescLeft"> </td><td class="mdescRight"><a class="el" href="struct_c_s_l___dss_overlay_layer_cfg.html" title="Configuration for selecting overlay input layers. ">CSL_DssOverlayLayerCfg</a> structure init function. <a href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#gae7481e9db942be0537425939b6387a22">More...</a><br/></td></tr>
+<tr class="separator:gae7481e9db942be0537425939b6387a22"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga1c8500dcdd91d052cfc9c01d4bed6e30"><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#ga1c8500dcdd91d052cfc9c01d4bed6e30">CSL_dssOverlayPipePosCfgInit</a> (<a class="el" href="struct_c_s_l___dss_overlay_pipe_pos_cfg.html">CSL_DssOverlayPipePosCfg</a> *pipePosCfg)</td></tr>
+<tr class="memdesc:ga1c8500dcdd91d052cfc9c01d4bed6e30"><td class="mdescLeft"> </td><td class="mdescRight"><a class="el" href="struct_c_s_l___dss_overlay_pipe_pos_cfg.html" title="Video Pipe Position Configuration in Overlay. ">CSL_DssOverlayPipePosCfg</a> structure init function. <a href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#ga1c8500dcdd91d052cfc9c01d4bed6e30">More...</a><br/></td></tr>
+<tr class="separator:ga1c8500dcdd91d052cfc9c01d4bed6e30"><td class="memSeparator" colspan="2"> </td></tr>
+</table>
+<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
+<div class="textblock"><p>DSS Overlay CSL FL interface file. </p>
+</div></div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/csl__dss_top_8h.html b/packages/ti/drv/dss/docs/doxygen/html/csl__dss_top_8h.html
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+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
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+<title>csl_dssTop.h File Reference</title>
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+ </div>
+<div id="nav-path" class="navpath">
+ <ul>
+<li class="navelem"><a class="el" href="dir_f5943f6d28c724c9867ac930658f5901.html">csl</a></li><li class="navelem"><a class="el" href="dir_2c013fc7e98dc8ade314eba46bcbb0d6.html">src</a></li><li class="navelem"><a class="el" href="dir_063bd5b357e44d632c140cb38e979030.html">ip</a></li><li class="navelem"><a class="el" href="dir_9601e7bd9bffb8db00e0c1272827daa6.html">dss</a></li><li class="navelem"><a class="el" href="dir_61ed5367bdc2fa7807323d7b06750347.html">V4</a></li> </ul>
+</div>
+</div><!-- top -->
+<div class="header">
+ <div class="summary">
+<a href="#nested-classes">Data Structures</a> |
+<a href="#define-members">Macros</a> |
+<a href="#func-members">Functions</a> </div>
+ <div class="headertitle">
+<div class="title">csl_dssTop.h File Reference<div class="ingroups"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html">Top Level CSL FL</a></div></div> </div>
+</div><!--header-->
+<div class="contents">
+
+<p>DSS Top CSL FL interface file.
+<a href="#details">More...</a></p>
+<div class="textblock"><code>#include <ti/csl/soc.h></code><br/>
+<code>#include <<a class="el" href="csl__fvid2__data_types_8h.html">ti/csl/csl_fvid2_dataTypes.h</a>></code><br/>
+<code>#include <ti/csl/cslr_dss.h></code><br/>
+</div><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="nested-classes"></a>
+Data Structures</h2></td></tr>
+<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_csc_coeff.html">CSL_DssCscCoeff</a></td></tr>
+<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">Structure containing coefficients for Color Space Conversion. <a href="struct_c_s_l___dss_csc_coeff.html#details">More...</a><br/></td></tr>
+<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_safety_chk_cfg.html">CSL_DssSafetyChkCfg</a></td></tr>
+<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">Configuration for doing safety checks. <a href="struct_c_s_l___dss_safety_chk_cfg.html#details">More...</a><br/></td></tr>
+<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
+Macros</h2></td></tr>
+<tr class="memitem:gac8a30c5680379b12128e75859e9f2312"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gac8a30c5680379b12128e75859e9f2312"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gac8a30c5680379b12128e75859e9f2312">CSL_DSS_NUM_LUT_ENTRIES</a>   ((uint32_t) 256U)</td></tr>
+<tr class="memdesc:gac8a30c5680379b12128e75859e9f2312"><td class="mdescLeft"> </td><td class="mdescRight">Number of entries for CLUT/Gamma Correction. <br/></td></tr>
+<tr class="separator:gac8a30c5680379b12128e75859e9f2312"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gaa7973f4d3301c7360cdbcc6f60c6e8fb"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaa7973f4d3301c7360cdbcc6f60c6e8fb"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gaa7973f4d3301c7360cdbcc6f60c6e8fb">CSL_DSS_MODULE_INVALID</a>   ((uint32_t) 0xFFU)</td></tr>
+<tr class="memdesc:gaa7973f4d3301c7360cdbcc6f60c6e8fb"><td class="mdescLeft"> </td><td class="mdescRight">Invalid Module Id for DSS modules. <br/></td></tr>
+<tr class="separator:gaa7973f4d3301c7360cdbcc6f60c6e8fb"><td class="memSeparator" colspan="2"> </td></tr>
+<tr><td colspan="2"><div class="groupHeader">DSS Video Pipeline Type</div></td></tr>
+<tr><td colspan="2"><div class="groupText"><p>To distinguish between VID (with scaler) and VIDL (without scaler)</p>
+<p><a class="anchor" id="CSL_DssVidPipeType"></a></p>
+</div></td></tr>
+<tr class="memitem:gae0a57704e2a39702c1d1ac1a861ead86"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gae0a57704e2a39702c1d1ac1a861ead86"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gae0a57704e2a39702c1d1ac1a861ead86">CSL_DSS_VID_PIPE_TYPE_VID</a>   ((uint32_t) 0x0)</td></tr>
+<tr class="memdesc:gae0a57704e2a39702c1d1ac1a861ead86"><td class="mdescLeft"> </td><td class="mdescRight">Video Pipe is of type VID. <br/></td></tr>
+<tr class="separator:gae0a57704e2a39702c1d1ac1a861ead86"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gab3801fb3aa15ef1b184da3fc2f9ea9ad"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gab3801fb3aa15ef1b184da3fc2f9ea9ad"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gab3801fb3aa15ef1b184da3fc2f9ea9ad">CSL_DSS_VID_PIPE_TYPE_VIDL</a>   ((uint32_t) 0x1)</td></tr>
+<tr class="memdesc:gab3801fb3aa15ef1b184da3fc2f9ea9ad"><td class="mdescLeft"> </td><td class="mdescRight">Video Pipe is of type VIDL. <br/></td></tr>
+<tr class="separator:gab3801fb3aa15ef1b184da3fc2f9ea9ad"><td class="memSeparator" colspan="2"> </td></tr>
+<tr><td colspan="2"><div class="groupHeader">DSS Common Region Id</div></td></tr>
+<tr><td colspan="2"><div class="groupText"><p>Id for different Common Regions</p>
+<p><a class="anchor" id="CSL_DssCommRegId"></a></p>
+</div></td></tr>
+<tr class="memitem:gaba6b3367cbe7db1f57b4693234fbcd86"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaba6b3367cbe7db1f57b4693234fbcd86"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gaba6b3367cbe7db1f57b4693234fbcd86">CSL_DSS_COMM_REG_ID_0</a>   ((uint32_t) 0x0U)</td></tr>
+<tr class="memdesc:gaba6b3367cbe7db1f57b4693234fbcd86"><td class="mdescLeft"> </td><td class="mdescRight">Common Region 0 i.e. M region. <br/></td></tr>
+<tr class="separator:gaba6b3367cbe7db1f57b4693234fbcd86"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga961c35c051c33b4e92691db8a5ee749d"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga961c35c051c33b4e92691db8a5ee749d"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga961c35c051c33b4e92691db8a5ee749d">CSL_DSS_COMM_REG_ID_1</a>   ((uint32_t) 0x1U)</td></tr>
+<tr class="memdesc:ga961c35c051c33b4e92691db8a5ee749d"><td class="mdescLeft"> </td><td class="mdescRight">Common Region 1 i.e. S0 region. <br/></td></tr>
+<tr class="separator:ga961c35c051c33b4e92691db8a5ee749d"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gafaece2043fd351a5f7f8b5b1628921c7"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gafaece2043fd351a5f7f8b5b1628921c7"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gafaece2043fd351a5f7f8b5b1628921c7">CSL_DSS_COMM_REG_ID_2</a>   ((uint32_t) 0x2U)</td></tr>
+<tr class="memdesc:gafaece2043fd351a5f7f8b5b1628921c7"><td class="mdescLeft"> </td><td class="mdescRight">Common Region 2 i.e. S1 region. <br/></td></tr>
+<tr class="separator:gafaece2043fd351a5f7f8b5b1628921c7"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga22dc72847784f75cad78a4c2a3b3f217"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga22dc72847784f75cad78a4c2a3b3f217"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga22dc72847784f75cad78a4c2a3b3f217">CSL_DSS_COMM_REG_ID_3</a>   ((uint32_t) 0x3U)</td></tr>
+<tr class="memdesc:ga22dc72847784f75cad78a4c2a3b3f217"><td class="mdescLeft"> </td><td class="mdescRight">Common Region 3 i.e. S2 region. <br/></td></tr>
+<tr class="separator:ga22dc72847784f75cad78a4c2a3b3f217"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gab1b9457684eda680598c1bc8a574e20c"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gab1b9457684eda680598c1bc8a574e20c"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gab1b9457684eda680598c1bc8a574e20c">CSL_DSS_COMM_REG_ID_MAX</a>   ((uint32_t) 0x4U)</td></tr>
+<tr class="memdesc:gab1b9457684eda680598c1bc8a574e20c"><td class="mdescLeft"> </td><td class="mdescRight">Common Region Max Id. <br/></td></tr>
+<tr class="separator:gab1b9457684eda680598c1bc8a574e20c"><td class="memSeparator" colspan="2"> </td></tr>
+<tr><td colspan="2"><div class="groupHeader">DSS Common Region Id Mask</div></td></tr>
+<tr><td colspan="2"><div class="groupText"><p>Mask for different Common Regions</p>
+<p><a class="anchor" id="CSL_DssCommRegIdMask"></a></p>
+</div></td></tr>
+<tr class="memitem:ga8e4fccb97063f3a1a8ae7a0a45f7de7b"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga8e4fccb97063f3a1a8ae7a0a45f7de7b"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga8e4fccb97063f3a1a8ae7a0a45f7de7b">CSL_DSS_COMM_REG_ID_0_MASK</a>   ((uint32_t) 0x1U)</td></tr>
+<tr class="memdesc:ga8e4fccb97063f3a1a8ae7a0a45f7de7b"><td class="mdescLeft"> </td><td class="mdescRight">Common Region 0 Mask. <br/></td></tr>
+<tr class="separator:ga8e4fccb97063f3a1a8ae7a0a45f7de7b"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga4b279b40e6fa88217af7df5242fdd007"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga4b279b40e6fa88217af7df5242fdd007"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga4b279b40e6fa88217af7df5242fdd007">CSL_DSS_COMM_REG_ID_1_MASK</a>   ((uint32_t) 0x2U)</td></tr>
+<tr class="memdesc:ga4b279b40e6fa88217af7df5242fdd007"><td class="mdescLeft"> </td><td class="mdescRight">Common Region 1 Mask. <br/></td></tr>
+<tr class="separator:ga4b279b40e6fa88217af7df5242fdd007"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gafdceb9e1230dd80ea4e7da1689f9ffba"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gafdceb9e1230dd80ea4e7da1689f9ffba"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gafdceb9e1230dd80ea4e7da1689f9ffba">CSL_DSS_COMM_REG_ID_2_MASK</a>   ((uint32_t) 0x4U)</td></tr>
+<tr class="memdesc:gafdceb9e1230dd80ea4e7da1689f9ffba"><td class="mdescLeft"> </td><td class="mdescRight">Common Region 2 Mask. <br/></td></tr>
+<tr class="separator:gafdceb9e1230dd80ea4e7da1689f9ffba"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga6ae3cbe4e7f4e35054a0f8f1d739ed83"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga6ae3cbe4e7f4e35054a0f8f1d739ed83"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga6ae3cbe4e7f4e35054a0f8f1d739ed83">CSL_DSS_COMM_REG_ID_3_MASK</a>   ((uint32_t) 0x8U)</td></tr>
+<tr class="memdesc:ga6ae3cbe4e7f4e35054a0f8f1d739ed83"><td class="mdescLeft"> </td><td class="mdescRight">Common Region 3 Mask. <br/></td></tr>
+<tr class="separator:ga6ae3cbe4e7f4e35054a0f8f1d739ed83"><td class="memSeparator" colspan="2"> </td></tr>
+<tr><td colspan="2"><div class="groupHeader">DSS Video Pipeline Id</div></td></tr>
+<tr><td colspan="2"><div class="groupText"><p>Id for different Video Pipelines</p>
+<p><a class="anchor" id="CSL_DssVidPipeId"></a></p>
+</div></td></tr>
+<tr class="memitem:gab861a5295a9cd21b01897e1026aa2b79"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gab861a5295a9cd21b01897e1026aa2b79"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gab861a5295a9cd21b01897e1026aa2b79">CSL_DSS_VID_PIPE_ID_VID1</a>   ((uint32_t) 0x0U)</td></tr>
+<tr class="memdesc:gab861a5295a9cd21b01897e1026aa2b79"><td class="mdescLeft"> </td><td class="mdescRight">Video Pipeline 1. <br/></td></tr>
+<tr class="separator:gab861a5295a9cd21b01897e1026aa2b79"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga73aee3bb97f91dafe4f9adfd0a0d3bac"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga73aee3bb97f91dafe4f9adfd0a0d3bac"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga73aee3bb97f91dafe4f9adfd0a0d3bac">CSL_DSS_VID_PIPE_ID_VIDL1</a>   ((uint32_t) 0x1U)</td></tr>
+<tr class="memdesc:ga73aee3bb97f91dafe4f9adfd0a0d3bac"><td class="mdescLeft"> </td><td class="mdescRight">Video Lite Pipeline 1. <br/></td></tr>
+<tr class="separator:ga73aee3bb97f91dafe4f9adfd0a0d3bac"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gadd35014f4f1e166a6b95a0e80970f9e8"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gadd35014f4f1e166a6b95a0e80970f9e8"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gadd35014f4f1e166a6b95a0e80970f9e8">CSL_DSS_VID_PIPE_ID_VID2</a>   ((uint32_t) 0x2U)</td></tr>
+<tr class="memdesc:gadd35014f4f1e166a6b95a0e80970f9e8"><td class="mdescLeft"> </td><td class="mdescRight">Video Pipeline 2. <br/></td></tr>
+<tr class="separator:gadd35014f4f1e166a6b95a0e80970f9e8"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga9692470b1ffe05c0bf39af6cce81b3dd"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga9692470b1ffe05c0bf39af6cce81b3dd"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga9692470b1ffe05c0bf39af6cce81b3dd">CSL_DSS_VID_PIPE_ID_VIDL2</a>   ((uint32_t) 0x3U)</td></tr>
+<tr class="memdesc:ga9692470b1ffe05c0bf39af6cce81b3dd"><td class="mdescLeft"> </td><td class="mdescRight">Video Lite Pipeline 2. <br/></td></tr>
+<tr class="separator:ga9692470b1ffe05c0bf39af6cce81b3dd"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gafbbd94228f58df3124b2bc9780379cea"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gafbbd94228f58df3124b2bc9780379cea"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gafbbd94228f58df3124b2bc9780379cea">CSL_DSS_VID_PIPE_ID_MAX</a>   ((uint32_t) 0x4U)</td></tr>
+<tr class="memdesc:gafbbd94228f58df3124b2bc9780379cea"><td class="mdescLeft"> </td><td class="mdescRight">Video Pipeline Max Id. <br/></td></tr>
+<tr class="separator:gafbbd94228f58df3124b2bc9780379cea"><td class="memSeparator" colspan="2"> </td></tr>
+<tr><td colspan="2"><div class="groupHeader">DSS Video Pipeline Id Mask</div></td></tr>
+<tr><td colspan="2"><div class="groupText"><p>Mask for different Video Pipelines</p>
+<p><a class="anchor" id="CSL_DssVidPipeIdMask"></a></p>
+</div></td></tr>
+<tr class="memitem:gaada71522489dcbd519415f3f81e490d0"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaada71522489dcbd519415f3f81e490d0"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gaada71522489dcbd519415f3f81e490d0">CSL_DSS_VID_PIPE_ID_VID1_MASK</a>   ((uint32_t) 0x1U)</td></tr>
+<tr class="memdesc:gaada71522489dcbd519415f3f81e490d0"><td class="mdescLeft"> </td><td class="mdescRight">Video Pipeline 1 Mask. <br/></td></tr>
+<tr class="separator:gaada71522489dcbd519415f3f81e490d0"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga86337ef6c0f0e8ac50c07638c91104c6"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga86337ef6c0f0e8ac50c07638c91104c6"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga86337ef6c0f0e8ac50c07638c91104c6">CSL_DSS_VID_PIPE_ID_VIDL1_MASK</a>   ((uint32_t) 0x2U)</td></tr>
+<tr class="memdesc:ga86337ef6c0f0e8ac50c07638c91104c6"><td class="mdescLeft"> </td><td class="mdescRight">Video Lite Pipeline 1 Mask. <br/></td></tr>
+<tr class="separator:ga86337ef6c0f0e8ac50c07638c91104c6"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga1d978b06983e4f19a666abd322a70293"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga1d978b06983e4f19a666abd322a70293"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga1d978b06983e4f19a666abd322a70293">CSL_DSS_VID_PIPE_ID_VID2_MASK</a>   ((uint32_t) 0x4U)</td></tr>
+<tr class="memdesc:ga1d978b06983e4f19a666abd322a70293"><td class="mdescLeft"> </td><td class="mdescRight">Video Pipeline 2 Mask. <br/></td></tr>
+<tr class="separator:ga1d978b06983e4f19a666abd322a70293"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga69abb0b78149e8c8880f5ce9f1d7d508"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga69abb0b78149e8c8880f5ce9f1d7d508"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga69abb0b78149e8c8880f5ce9f1d7d508">CSL_DSS_VID_PIPE_ID_VIDL2_MASK</a>   ((uint32_t) 0x8U)</td></tr>
+<tr class="memdesc:ga69abb0b78149e8c8880f5ce9f1d7d508"><td class="mdescLeft"> </td><td class="mdescRight">Video Lite Pipeline 1 Mask. <br/></td></tr>
+<tr class="separator:ga69abb0b78149e8c8880f5ce9f1d7d508"><td class="memSeparator" colspan="2"> </td></tr>
+<tr><td colspan="2"><div class="groupHeader">DSS Overlay Id</div></td></tr>
+<tr><td colspan="2"><div class="groupText"><p>Id for DSS Overlays</p>
+<p><a class="anchor" id="CSL_DssOverlayId"></a></p>
+</div></td></tr>
+<tr class="memitem:ga5acb54b8623189d18b4211a24a0ddb8c"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga5acb54b8623189d18b4211a24a0ddb8c"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga5acb54b8623189d18b4211a24a0ddb8c">CSL_DSS_OVERLAY_ID_1</a>   ((uint32_t) 0x0U)</td></tr>
+<tr class="memdesc:ga5acb54b8623189d18b4211a24a0ddb8c"><td class="mdescLeft"> </td><td class="mdescRight">Overlay 1. <br/></td></tr>
+<tr class="separator:ga5acb54b8623189d18b4211a24a0ddb8c"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga37edd061f4545fb5bcaf98fb0e29f49c"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga37edd061f4545fb5bcaf98fb0e29f49c"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga37edd061f4545fb5bcaf98fb0e29f49c">CSL_DSS_OVERLAY_ID_2</a>   ((uint32_t) 0x1U)</td></tr>
+<tr class="memdesc:ga37edd061f4545fb5bcaf98fb0e29f49c"><td class="mdescLeft"> </td><td class="mdescRight">Overlay 2. <br/></td></tr>
+<tr class="separator:ga37edd061f4545fb5bcaf98fb0e29f49c"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga4cc372289cf4841713a3fff407e519ec"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga4cc372289cf4841713a3fff407e519ec"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga4cc372289cf4841713a3fff407e519ec">CSL_DSS_OVERLAY_ID_3</a>   ((uint32_t) 0x2U)</td></tr>
+<tr class="memdesc:ga4cc372289cf4841713a3fff407e519ec"><td class="mdescLeft"> </td><td class="mdescRight">Overlay 3. <br/></td></tr>
+<tr class="separator:ga4cc372289cf4841713a3fff407e519ec"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gae8da1ca2c825364e430e6bb94a11c8de"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gae8da1ca2c825364e430e6bb94a11c8de"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gae8da1ca2c825364e430e6bb94a11c8de">CSL_DSS_OVERLAY_ID_4</a>   ((uint32_t) 0x3U)</td></tr>
+<tr class="memdesc:gae8da1ca2c825364e430e6bb94a11c8de"><td class="mdescLeft"> </td><td class="mdescRight">Overlay 4. <br/></td></tr>
+<tr class="separator:gae8da1ca2c825364e430e6bb94a11c8de"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga41df77f605b2d5c6e107fd4b0df61220"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga41df77f605b2d5c6e107fd4b0df61220"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga41df77f605b2d5c6e107fd4b0df61220">CSL_DSS_OVERLAY_ID_MAX</a>   ((uint32_t) 0x4U)</td></tr>
+<tr class="memdesc:ga41df77f605b2d5c6e107fd4b0df61220"><td class="mdescLeft"> </td><td class="mdescRight">Overlay Max Id. <br/></td></tr>
+<tr class="separator:ga41df77f605b2d5c6e107fd4b0df61220"><td class="memSeparator" colspan="2"> </td></tr>
+<tr><td colspan="2"><div class="groupHeader">DSS Overlay Id Mask</div></td></tr>
+<tr><td colspan="2"><div class="groupText"><p>Mask for DSS Overlays</p>
+<p><a class="anchor" id="CSL_DssOverlayIdMask"></a></p>
+</div></td></tr>
+<tr class="memitem:gab66410f4f933b9c077e3f9d294436073"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gab66410f4f933b9c077e3f9d294436073"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gab66410f4f933b9c077e3f9d294436073">CSL_DSS_OVERLAY_ID_1_MASK</a>   ((uint32_t) 0x1U)</td></tr>
+<tr class="memdesc:gab66410f4f933b9c077e3f9d294436073"><td class="mdescLeft"> </td><td class="mdescRight">Overlay 1 Mask. <br/></td></tr>
+<tr class="separator:gab66410f4f933b9c077e3f9d294436073"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gac474fcd4a03b4204c8cf584ba7b105e2"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gac474fcd4a03b4204c8cf584ba7b105e2"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gac474fcd4a03b4204c8cf584ba7b105e2">CSL_DSS_OVERLAY_ID_2_MASK</a>   ((uint32_t) 0x2U)</td></tr>
+<tr class="memdesc:gac474fcd4a03b4204c8cf584ba7b105e2"><td class="mdescLeft"> </td><td class="mdescRight">Overlay 2 Mask. <br/></td></tr>
+<tr class="separator:gac474fcd4a03b4204c8cf584ba7b105e2"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gaa3f86a021fef86c1bdf2d94e122143c2"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaa3f86a021fef86c1bdf2d94e122143c2"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gaa3f86a021fef86c1bdf2d94e122143c2">CSL_DSS_OVERLAY_ID_3_MASK</a>   ((uint32_t) 0x4U)</td></tr>
+<tr class="memdesc:gaa3f86a021fef86c1bdf2d94e122143c2"><td class="mdescLeft"> </td><td class="mdescRight">Overlay 3 Mask. <br/></td></tr>
+<tr class="separator:gaa3f86a021fef86c1bdf2d94e122143c2"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga80bbc7f730eed3ab5d593b450858375e"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga80bbc7f730eed3ab5d593b450858375e"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga80bbc7f730eed3ab5d593b450858375e">CSL_DSS_OVERLAY_ID_4_MASK</a>   ((uint32_t) 0x8U)</td></tr>
+<tr class="memdesc:ga80bbc7f730eed3ab5d593b450858375e"><td class="mdescLeft"> </td><td class="mdescRight">Overlay 4 Mask. <br/></td></tr>
+<tr class="separator:ga80bbc7f730eed3ab5d593b450858375e"><td class="memSeparator" colspan="2"> </td></tr>
+<tr><td colspan="2"><div class="groupHeader">DSS Video Port Id</div></td></tr>
+<tr><td colspan="2"><div class="groupText"><p>Id for DSS Video Ports</p>
+<p><a class="anchor" id="CSL_DssVpId"></a></p>
+</div></td></tr>
+<tr class="memitem:gafbe058ac640cf42ad08afa3b32fb29d1"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gafbe058ac640cf42ad08afa3b32fb29d1"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gafbe058ac640cf42ad08afa3b32fb29d1">CSL_DSS_VP_ID_1</a>   ((uint32_t) 0x0U)</td></tr>
+<tr class="memdesc:gafbe058ac640cf42ad08afa3b32fb29d1"><td class="mdescLeft"> </td><td class="mdescRight">Video Port 1. <br/></td></tr>
+<tr class="separator:gafbe058ac640cf42ad08afa3b32fb29d1"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga34118161f4c12f89689b79f5ce09696c"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga34118161f4c12f89689b79f5ce09696c"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga34118161f4c12f89689b79f5ce09696c">CSL_DSS_VP_ID_2</a>   ((uint32_t) 0x1U)</td></tr>
+<tr class="memdesc:ga34118161f4c12f89689b79f5ce09696c"><td class="mdescLeft"> </td><td class="mdescRight">Video Port 2. <br/></td></tr>
+<tr class="separator:ga34118161f4c12f89689b79f5ce09696c"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga657e4b1ceb6955c961961d5c0af3e9b7"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga657e4b1ceb6955c961961d5c0af3e9b7"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga657e4b1ceb6955c961961d5c0af3e9b7">CSL_DSS_VP_ID_3</a>   ((uint32_t) 0x2U)</td></tr>
+<tr class="memdesc:ga657e4b1ceb6955c961961d5c0af3e9b7"><td class="mdescLeft"> </td><td class="mdescRight">Video Port 3. <br/></td></tr>
+<tr class="separator:ga657e4b1ceb6955c961961d5c0af3e9b7"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga961d6492d4afd198139770cb4b93a5ab"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga961d6492d4afd198139770cb4b93a5ab"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga961d6492d4afd198139770cb4b93a5ab">CSL_DSS_VP_ID_4</a>   ((uint32_t) 0x3U)</td></tr>
+<tr class="memdesc:ga961d6492d4afd198139770cb4b93a5ab"><td class="mdescLeft"> </td><td class="mdescRight">Video Port 4. <br/></td></tr>
+<tr class="separator:ga961d6492d4afd198139770cb4b93a5ab"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga0a203752c6295d20389b36d6c2e0de0c"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga0a203752c6295d20389b36d6c2e0de0c"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga0a203752c6295d20389b36d6c2e0de0c">CSL_DSS_VP_ID_MAX</a>   ((uint32_t) 0x4U)</td></tr>
+<tr class="memdesc:ga0a203752c6295d20389b36d6c2e0de0c"><td class="mdescLeft"> </td><td class="mdescRight">Video Port Max Id. <br/></td></tr>
+<tr class="separator:ga0a203752c6295d20389b36d6c2e0de0c"><td class="memSeparator" colspan="2"> </td></tr>
+<tr><td colspan="2"><div class="groupHeader">DSS Video Port Id Mask</div></td></tr>
+<tr><td colspan="2"><div class="groupText"><p>Mask for DSS Video Ports</p>
+<p><a class="anchor" id="CSL_DssVpIdMask"></a></p>
+</div></td></tr>
+<tr class="memitem:ga2b8bb0130844b328ae5711f9f4b5487b"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga2b8bb0130844b328ae5711f9f4b5487b"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga2b8bb0130844b328ae5711f9f4b5487b">CSL_DSS_VP_ID_1_MASK</a>   ((uint32_t) 0x1U)</td></tr>
+<tr class="memdesc:ga2b8bb0130844b328ae5711f9f4b5487b"><td class="mdescLeft"> </td><td class="mdescRight">Video Port 1. <br/></td></tr>
+<tr class="separator:ga2b8bb0130844b328ae5711f9f4b5487b"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga40b42315f64e4f7290af3f3f2c1f6fb4"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga40b42315f64e4f7290af3f3f2c1f6fb4"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga40b42315f64e4f7290af3f3f2c1f6fb4">CSL_DSS_VP_ID_2_MASK</a>   ((uint32_t) 0x2U)</td></tr>
+<tr class="memdesc:ga40b42315f64e4f7290af3f3f2c1f6fb4"><td class="mdescLeft"> </td><td class="mdescRight">Video Port 2. <br/></td></tr>
+<tr class="separator:ga40b42315f64e4f7290af3f3f2c1f6fb4"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gac5818d5d83b12514d8a01d62d6743306"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gac5818d5d83b12514d8a01d62d6743306"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gac5818d5d83b12514d8a01d62d6743306">CSL_DSS_VP_ID_3_MASK</a>   ((uint32_t) 0x4U)</td></tr>
+<tr class="memdesc:gac5818d5d83b12514d8a01d62d6743306"><td class="mdescLeft"> </td><td class="mdescRight">Video Port 3. <br/></td></tr>
+<tr class="separator:gac5818d5d83b12514d8a01d62d6743306"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gacabf7b4969d7515d967d243e2e67dd2a"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gacabf7b4969d7515d967d243e2e67dd2a"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gacabf7b4969d7515d967d243e2e67dd2a">CSL_DSS_VP_ID_4_MASK</a>   ((uint32_t) 0x8U)</td></tr>
+<tr class="memdesc:gacabf7b4969d7515d967d243e2e67dd2a"><td class="mdescLeft"> </td><td class="mdescRight">Video Port 4. <br/></td></tr>
+<tr class="separator:gacabf7b4969d7515d967d243e2e67dd2a"><td class="memSeparator" colspan="2"> </td></tr>
+<tr><td colspan="2"><div class="groupHeader">DSS CSC Range</div></td></tr>
+<tr><td colspan="2"><div class="groupText"><p>DSS Color Space Conversion range setting</p>
+<p><a class="anchor" id="CSL_DssCscRange"></a></p>
+</div></td></tr>
+<tr class="memitem:ga3041c8743595f7ce5d8ebb59cf32bcc4"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga3041c8743595f7ce5d8ebb59cf32bcc4"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga3041c8743595f7ce5d8ebb59cf32bcc4">CSL_DSS_CSC_RANGE_LIMITED</a>   ((uint32_t) 0x0U)</td></tr>
+<tr class="memdesc:ga3041c8743595f7ce5d8ebb59cf32bcc4"><td class="mdescLeft"> </td><td class="mdescRight">Limited range selected. <br/></td></tr>
+<tr class="separator:ga3041c8743595f7ce5d8ebb59cf32bcc4"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga2b1f7a9fccfe834266cc61dbab22a7f2"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga2b1f7a9fccfe834266cc61dbab22a7f2"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga2b1f7a9fccfe834266cc61dbab22a7f2">CSL_DSS_CSC_RANGE_FULL</a>   ((uint32_t) 0x1U)</td></tr>
+<tr class="memdesc:ga2b1f7a9fccfe834266cc61dbab22a7f2"><td class="mdescLeft"> </td><td class="mdescRight">Full range selected. <br/></td></tr>
+<tr class="separator:ga2b1f7a9fccfe834266cc61dbab22a7f2"><td class="memSeparator" colspan="2"> </td></tr>
+<tr><td colspan="2"><div class="groupHeader">DSS Safety Region Id</div></td></tr>
+<tr><td colspan="2"><div class="groupText"><p><a class="anchor" id="CSL_DssSafetyRegionId"></a></p>
+</div></td></tr>
+<tr class="memitem:gaa3a861b982382bd7387783bf1019576c"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaa3a861b982382bd7387783bf1019576c"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gaa3a861b982382bd7387783bf1019576c">CSL_DSS_SAFETY_REGION_0</a>   ((uint32_t) 0x0U)</td></tr>
+<tr class="memdesc:gaa3a861b982382bd7387783bf1019576c"><td class="mdescLeft"> </td><td class="mdescRight">Safety Region 0. <br/></td></tr>
+<tr class="separator:gaa3a861b982382bd7387783bf1019576c"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gaa104154d768c72acac19f2545460038c"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaa104154d768c72acac19f2545460038c"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gaa104154d768c72acac19f2545460038c">CSL_DSS_SAFETY_REGION_1</a>   ((uint32_t) 0x1U)</td></tr>
+<tr class="memdesc:gaa104154d768c72acac19f2545460038c"><td class="mdescLeft"> </td><td class="mdescRight">Safety Region 1. <br/></td></tr>
+<tr class="separator:gaa104154d768c72acac19f2545460038c"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga3ca88d86a0c19685b48ce935c86821bd"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga3ca88d86a0c19685b48ce935c86821bd"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga3ca88d86a0c19685b48ce935c86821bd">CSL_DSS_SAFETY_REGION_2</a>   ((uint32_t) 0x2U)</td></tr>
+<tr class="memdesc:ga3ca88d86a0c19685b48ce935c86821bd"><td class="mdescLeft"> </td><td class="mdescRight">Safety Region 2. <br/></td></tr>
+<tr class="separator:ga3ca88d86a0c19685b48ce935c86821bd"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga7fecc5cd051151b901deb0dbd6c36201"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga7fecc5cd051151b901deb0dbd6c36201"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga7fecc5cd051151b901deb0dbd6c36201">CSL_DSS_SAFETY_REGION_3</a>   ((uint32_t) 0x3U)</td></tr>
+<tr class="memdesc:ga7fecc5cd051151b901deb0dbd6c36201"><td class="mdescLeft"> </td><td class="mdescRight">Safety Region 3. <br/></td></tr>
+<tr class="separator:ga7fecc5cd051151b901deb0dbd6c36201"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gabfb09986c4139d4093308e6f708fd582"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gabfb09986c4139d4093308e6f708fd582"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gabfb09986c4139d4093308e6f708fd582">CSL_DSS_SAFETY_REGION_4</a>   ((uint32_t) 0x4U)</td></tr>
+<tr class="memdesc:gabfb09986c4139d4093308e6f708fd582"><td class="mdescLeft"> </td><td class="mdescRight">Safety Region 4. <br/></td></tr>
+<tr class="separator:gabfb09986c4139d4093308e6f708fd582"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga83b9053e2bc53689cf537ae19102ff9f"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga83b9053e2bc53689cf537ae19102ff9f"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga83b9053e2bc53689cf537ae19102ff9f">CSL_DSS_SAFETY_REGION_5</a>   ((uint32_t) 0x5U)</td></tr>
+<tr class="memdesc:ga83b9053e2bc53689cf537ae19102ff9f"><td class="mdescLeft"> </td><td class="mdescRight">Safety Region 5. <br/></td></tr>
+<tr class="separator:ga83b9053e2bc53689cf537ae19102ff9f"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga0e75b3f63a3ad9488a287d1cfe5ff9a5"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga0e75b3f63a3ad9488a287d1cfe5ff9a5"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga0e75b3f63a3ad9488a287d1cfe5ff9a5">CSL_DSS_SAFETY_REGION_6</a>   ((uint32_t) 0x6U)</td></tr>
+<tr class="memdesc:ga0e75b3f63a3ad9488a287d1cfe5ff9a5"><td class="mdescLeft"> </td><td class="mdescRight">Safety Region 6. <br/></td></tr>
+<tr class="separator:ga0e75b3f63a3ad9488a287d1cfe5ff9a5"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga20d089acf2d69bd7f86a05eea0093bfa"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga20d089acf2d69bd7f86a05eea0093bfa"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga20d089acf2d69bd7f86a05eea0093bfa">CSL_DSS_SAFETY_REGION_7</a>   ((uint32_t) 0x7U)</td></tr>
+<tr class="memdesc:ga20d089acf2d69bd7f86a05eea0093bfa"><td class="mdescLeft"> </td><td class="mdescRight">Safety Region 7. <br/></td></tr>
+<tr class="separator:ga20d089acf2d69bd7f86a05eea0093bfa"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga514efc84b40d7147969434b2d5cff2fe"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga514efc84b40d7147969434b2d5cff2fe"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga514efc84b40d7147969434b2d5cff2fe">CSL_DSS_SAFETY_REGION_MAX</a>   ((uint32_t) 0x8U)</td></tr>
+<tr class="memdesc:ga514efc84b40d7147969434b2d5cff2fe"><td class="mdescLeft"> </td><td class="mdescRight">Safety Region Max. <br/></td></tr>
+<tr class="separator:ga514efc84b40d7147969434b2d5cff2fe"><td class="memSeparator" colspan="2"> </td></tr>
+<tr><td colspan="2"><div class="groupHeader">DSS Safety Check Mode</div></td></tr>
+<tr><td colspan="2"><div class="groupText"><p>Mode of operation of the safety check module</p>
+<p><a class="anchor" id="CSL_DssSafetyChkMode"></a></p>
+</div></td></tr>
+<tr class="memitem:ga87bc16f17eb07c0e42f1e00f9ed1ef3e"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga87bc16f17eb07c0e42f1e00f9ed1ef3e"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga87bc16f17eb07c0e42f1e00f9ed1ef3e">CSL_DSS_SAFETY_CHK_FRAME_FREEZE_DETECT</a>   ((uint32_t) CSL_DSS_VID1_SAFETY_ATTRIBUTES_CAPTUREMODE_VAL_FRAMEFREEZE)</td></tr>
+<tr class="memdesc:ga87bc16f17eb07c0e42f1e00f9ed1ef3e"><td class="mdescLeft"> </td><td class="mdescRight">Frame freeze detect enabled. <br/></td></tr>
+<tr class="separator:ga87bc16f17eb07c0e42f1e00f9ed1ef3e"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gabc2f69f2dfaab74b675a923fb14c3489"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gabc2f69f2dfaab74b675a923fb14c3489"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gabc2f69f2dfaab74b675a923fb14c3489">CSL_DSS_SAFETY_CHK_DATA_INTEGRITY</a>   ((uint32_t) CSL_DSS_VID1_SAFETY_ATTRIBUTES_CAPTUREMODE_VAL_DATACHECK)</td></tr>
+<tr class="memdesc:gabc2f69f2dfaab74b675a923fb14c3489"><td class="mdescLeft"> </td><td class="mdescRight">Data correctness check enabled. <br/></td></tr>
+<tr class="separator:gabc2f69f2dfaab74b675a923fb14c3489"><td class="memSeparator" colspan="2"> </td></tr>
+<tr><td colspan="2"><div class="groupHeader">DSS Safety Check Frame Skip</div></td></tr>
+<tr><td colspan="2"><div class="groupText"><p>Indicates which frames to be skipped while doing safety check</p>
+<p><a class="anchor" id="CSL_DssSafetyChkFrameSkip"></a></p>
+</div></td></tr>
+<tr class="memitem:ga3b3b3a0ec326781390a727d437cd3e59"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga3b3b3a0ec326781390a727d437cd3e59"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga3b3b3a0ec326781390a727d437cd3e59">CSL_DSS_SAFETY_CHK_FRAME_SKIP_NO</a>   ((uint32_t) CSL_DSS_VID1_SAFETY_ATTRIBUTES_FRAMESKIP_VAL_DISABLE)</td></tr>
+<tr class="memdesc:ga3b3b3a0ec326781390a727d437cd3e59"><td class="mdescLeft"> </td><td class="mdescRight">No frames are skipped. <br/></td></tr>
+<tr class="separator:ga3b3b3a0ec326781390a727d437cd3e59"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga663277190152e9b070a32830bdfab30d"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga663277190152e9b070a32830bdfab30d"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga663277190152e9b070a32830bdfab30d">CSL_DSS_SAFETY_CHK_FRAME_SKIP_EVEN</a>   ((uint32_t) CSL_DSS_VID1_SAFETY_ATTRIBUTES_FRAMESKIP_VAL_EVEN)</td></tr>
+<tr class="memdesc:ga663277190152e9b070a32830bdfab30d"><td class="mdescLeft"> </td><td class="mdescRight">Even Frames are skipped starting from second frame after enable. <br/></td></tr>
+<tr class="separator:ga663277190152e9b070a32830bdfab30d"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gafca0e84bf97ed23528e1bc15af0a4e98"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gafca0e84bf97ed23528e1bc15af0a4e98"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gafca0e84bf97ed23528e1bc15af0a4e98">CSL_DSS_SAFETY_CHK_FRAME_SKIP_ODD</a>   ((uint32_t) CSL_DSS_VID1_SAFETY_ATTRIBUTES_FRAMESKIP_VAL_ODD)</td></tr>
+<tr class="memdesc:gafca0e84bf97ed23528e1bc15af0a4e98"><td class="mdescLeft"> </td><td class="mdescRight">Odd Frames are skipped starting from first frame after enable. <br/></td></tr>
+<tr class="separator:gafca0e84bf97ed23528e1bc15af0a4e98"><td class="memSeparator" colspan="2"> </td></tr>
+<tr><td colspan="2"><div class="groupHeader">DSS DPI Id</div></td></tr>
+<tr><td colspan="2"><div class="groupText"><p><a class="anchor" id="CSL_DssDpiId"></a></p>
+</div></td></tr>
+<tr class="memitem:ga9679d96bb4a54cf7e8ce0a22bf034ce3"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga9679d96bb4a54cf7e8ce0a22bf034ce3"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga9679d96bb4a54cf7e8ce0a22bf034ce3">CSL_DSS_DPI_ID_0</a>   ((uint32_t) 0x0U)</td></tr>
+<tr class="memdesc:ga9679d96bb4a54cf7e8ce0a22bf034ce3"><td class="mdescLeft"> </td><td class="mdescRight">DPI Id 0. <br/></td></tr>
+<tr class="separator:ga9679d96bb4a54cf7e8ce0a22bf034ce3"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga2ef99175d7ba50686f9d3b55484099d3"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga2ef99175d7ba50686f9d3b55484099d3"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga2ef99175d7ba50686f9d3b55484099d3">CSL_DSS_DPI_ID_1</a>   ((uint32_t) 0x1U)</td></tr>
+<tr class="memdesc:ga2ef99175d7ba50686f9d3b55484099d3"><td class="mdescLeft"> </td><td class="mdescRight">DPI Id 1. <br/></td></tr>
+<tr class="separator:ga2ef99175d7ba50686f9d3b55484099d3"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga2fcf2f843406ec0ff1ee6ec29156576e"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga2fcf2f843406ec0ff1ee6ec29156576e"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga2fcf2f843406ec0ff1ee6ec29156576e">CSL_DSS_DPI_ID_2</a>   ((uint32_t) 0x2U)</td></tr>
+<tr class="memdesc:ga2fcf2f843406ec0ff1ee6ec29156576e"><td class="mdescLeft"> </td><td class="mdescRight">DPI Id 2. <br/></td></tr>
+<tr class="separator:ga2fcf2f843406ec0ff1ee6ec29156576e"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga3e2b38794f954faea2bf1769d25c2bd3"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga3e2b38794f954faea2bf1769d25c2bd3"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga3e2b38794f954faea2bf1769d25c2bd3">CSL_DSS_DPI_ID_3</a>   ((uint32_t) 0x3U)</td></tr>
+<tr class="memdesc:ga3e2b38794f954faea2bf1769d25c2bd3"><td class="mdescLeft"> </td><td class="mdescRight">DPI Id 3. <br/></td></tr>
+<tr class="separator:ga3e2b38794f954faea2bf1769d25c2bd3"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga92854e551ae60a5d40c9c5c1c8326092"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga92854e551ae60a5d40c9c5c1c8326092"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga92854e551ae60a5d40c9c5c1c8326092">CSL_DSS_DPI_ID_4</a>   ((uint32_t) 0x4U)</td></tr>
+<tr class="memdesc:ga92854e551ae60a5d40c9c5c1c8326092"><td class="mdescLeft"> </td><td class="mdescRight">DPI Id 4. <br/></td></tr>
+<tr class="separator:ga92854e551ae60a5d40c9c5c1c8326092"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gad22d8422668bd5e965c0611d4c80ca36"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gad22d8422668bd5e965c0611d4c80ca36"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gad22d8422668bd5e965c0611d4c80ca36">CSL_DSS_DPI_ID_5</a>   ((uint32_t) 0x5U)</td></tr>
+<tr class="memdesc:gad22d8422668bd5e965c0611d4c80ca36"><td class="mdescLeft"> </td><td class="mdescRight">DPI Id 5. <br/></td></tr>
+<tr class="separator:gad22d8422668bd5e965c0611d4c80ca36"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga53c1ac5fbf207e8f973902051404e51e"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga53c1ac5fbf207e8f973902051404e51e"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga53c1ac5fbf207e8f973902051404e51e">CSL_DSS_DPI_ID_MAX</a>   ((uint32_t) 0x6U)</td></tr>
+<tr class="memdesc:ga53c1ac5fbf207e8f973902051404e51e"><td class="mdescLeft"> </td><td class="mdescRight">DPI Id Max. <br/></td></tr>
+<tr class="separator:ga53c1ac5fbf207e8f973902051404e51e"><td class="memSeparator" colspan="2"> </td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a>
+Functions</h2></td></tr>
+<tr class="memitem:ga09a24eab792b00629e4b510d36a326a8"><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga09a24eab792b00629e4b510d36a326a8">CSL_dssCscCoeffInit</a> (<a class="el" href="struct_c_s_l___dss_csc_coeff.html">CSL_DssCscCoeff</a> *cscCoeff)</td></tr>
+<tr class="memdesc:ga09a24eab792b00629e4b510d36a326a8"><td class="mdescLeft"> </td><td class="mdescRight"><a class="el" href="struct_c_s_l___dss_csc_coeff.html" title="Structure containing coefficients for Color Space Conversion. ">CSL_DssCscCoeff</a> structure init function. <a href="group___c_s_l___d_s_s_t_o_p.html#ga09a24eab792b00629e4b510d36a326a8">More...</a><br/></td></tr>
+<tr class="separator:ga09a24eab792b00629e4b510d36a326a8"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga0eba2c12170b846778eecb3eeb5a9a46"><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga0eba2c12170b846778eecb3eeb5a9a46">CSL_dssSafetyChkCfgInit</a> (<a class="el" href="struct_c_s_l___dss_safety_chk_cfg.html">CSL_DssSafetyChkCfg</a> *safetyCfg)</td></tr>
+<tr class="memdesc:ga0eba2c12170b846778eecb3eeb5a9a46"><td class="mdescLeft"> </td><td class="mdescRight"><a class="el" href="struct_c_s_l___dss_safety_chk_cfg.html" title="Configuration for doing safety checks. ">CSL_DssSafetyChkCfg</a> structure init function. <a href="group___c_s_l___d_s_s_t_o_p.html#ga0eba2c12170b846778eecb3eeb5a9a46">More...</a><br/></td></tr>
+<tr class="separator:ga0eba2c12170b846778eecb3eeb5a9a46"><td class="memSeparator" colspan="2"> </td></tr>
+</table>
+<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
+<div class="textblock"><p>DSS Top CSL FL interface file. </p>
+</div></div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/csl__dss_video_pipe_8h.html b/packages/ti/drv/dss/docs/doxygen/html/csl__dss_video_pipe_8h.html
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+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
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+<title>csl_dssVideoPipe.h File Reference</title>
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+</table>
+<!-- Generated by Doxygen 1.8.6 -->
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+ <li><a href="index.html"><span>Main Page</span></a></li>
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+<li class="navelem"><a class="el" href="dir_f5943f6d28c724c9867ac930658f5901.html">csl</a></li><li class="navelem"><a class="el" href="dir_2c013fc7e98dc8ade314eba46bcbb0d6.html">src</a></li><li class="navelem"><a class="el" href="dir_063bd5b357e44d632c140cb38e979030.html">ip</a></li><li class="navelem"><a class="el" href="dir_9601e7bd9bffb8db00e0c1272827daa6.html">dss</a></li><li class="navelem"><a class="el" href="dir_61ed5367bdc2fa7807323d7b06750347.html">V4</a></li> </ul>
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+ <div class="summary">
+<a href="#nested-classes">Data Structures</a> |
+<a href="#typedef-members">Typedefs</a> |
+<a href="#func-members">Functions</a> </div>
+ <div class="headertitle">
+<div class="title">csl_dssVideoPipe.h File Reference<div class="ingroups"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html">DSS Video Pipe CSL FL</a></div></div> </div>
+</div><!--header-->
+<div class="contents">
+
+<p>DSS Video Pipe CSL FL interface file.
+<a href="#details">More...</a></p>
+<table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="nested-classes"></a>
+Data Structures</h2></td></tr>
+<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_vid_pipe_cfg.html">CSL_DssVidPipeCfg</a></td></tr>
+<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">Configuration for DSS Video Pipe. <a href="struct_c_s_l___dss_vid_pipe_cfg.html#details">More...</a><br/></td></tr>
+<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_vid_pipe_dma_cfg.html">CSL_DssVidPipeDmaCfg</a></td></tr>
+<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">DSS Video Pipe DMA related Config parameters. <a href="struct_c_s_l___dss_vid_pipe_dma_cfg.html#details">More...</a><br/></td></tr>
+<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_vid_pipe_luma_cfg.html">CSL_DssVidPipeLumaCfg</a></td></tr>
+<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">DSS Video Pipe Luma Key Config parameters. <a href="struct_c_s_l___dss_vid_pipe_luma_cfg.html#details">More...</a><br/></td></tr>
+<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_vid_pipe_alpha_cfg.html">CSL_DssVidPipeAlphaCfg</a></td></tr>
+<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">DSS Video Pipe Alpha Config parameters. <a href="struct_c_s_l___dss_vid_pipe_alpha_cfg.html#details">More...</a><br/></td></tr>
+<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_vid_pipe_v_c1_cfg.html">CSL_DssVidPipeVC1Cfg</a></td></tr>
+<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">DSS Video Pipe VC1 configuration. <a href="struct_c_s_l___dss_vid_pipe_v_c1_cfg.html#details">More...</a><br/></td></tr>
+<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_vid_pipe_m_flag_cfg.html">CSL_DssVidPipeMFlagCfg</a></td></tr>
+<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">DSS Video Pipe MFLAG Config parameters. <a href="struct_c_s_l___dss_vid_pipe_m_flag_cfg.html#details">More...</a><br/></td></tr>
+<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
+Macros</h2></td></tr>
+<tr><td colspan="2"><div class="groupHeader">DSS Video Pipe YUV Alignment</div></td></tr>
+<tr><td colspan="2"><div class="groupText"><p>DSS Video Pipe alignment for unpacked YUV data</p>
+<p><a class="anchor" id="CSL_DssVidPipeYuvAlign"></a></p>
+</div></td></tr>
+<tr class="memitem:ga39ea4aaf120f874835b851ed1a0d84af"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga39ea4aaf120f874835b851ed1a0d84af"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#ga39ea4aaf120f874835b851ed1a0d84af">CSL_DSS_VID_PIPE_YUV_ALIGN_LSB</a>   ((uint32_t) CSL_DSS_VID1_ATTRIBUTES2_YUV_ALIGN_VAL_LSB)</td></tr>
+<tr class="memdesc:ga39ea4aaf120f874835b851ed1a0d84af"><td class="mdescLeft"> </td><td class="mdescRight">Data is LSB aligned (MSB unused) <br/></td></tr>
+<tr class="separator:ga39ea4aaf120f874835b851ed1a0d84af"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gaed342608ce368c3c538c10e808a60eef"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaed342608ce368c3c538c10e808a60eef"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gaed342608ce368c3c538c10e808a60eef">CSL_DSS_VID_PIPE_YUV_ALIGN_MSB</a>   ((uint32_t) CSL_DSS_VID1_ATTRIBUTES2_YUV_ALIGN_VAL_MSB)</td></tr>
+<tr class="memdesc:gaed342608ce368c3c538c10e808a60eef"><td class="mdescLeft"> </td><td class="mdescRight">Data is MSB aligned (LSB unused) <br/></td></tr>
+<tr class="separator:gaed342608ce368c3c538c10e808a60eef"><td class="memSeparator" colspan="2"> </td></tr>
+<tr><td colspan="2"><div class="groupHeader">DSS Video Pipe Scaler Value</div></td></tr>
+<tr><td colspan="2"><div class="groupText"><p><a class="anchor" id="CSL_DssVidPipeScVal"></a></p>
+</div></td></tr>
+<tr class="memitem:gabeae764db02ef759820ebc878da5abc7"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gabeae764db02ef759820ebc878da5abc7"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gabeae764db02ef759820ebc878da5abc7">CSL_DSS_VID_PIPE_SC_DISABLED</a>   ((uint32_t) CSL_DSS_VID1_ATTRIBUTES_RESIZEENABLE_VAL_RESIZEPROC)</td></tr>
+<tr class="memdesc:gabeae764db02ef759820ebc878da5abc7"><td class="mdescLeft"> </td><td class="mdescRight">Scaler is disabled. <br/></td></tr>
+<tr class="separator:gabeae764db02ef759820ebc878da5abc7"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gae5bb5538c01dcbf3f8b9d1fc52dc385a"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gae5bb5538c01dcbf3f8b9d1fc52dc385a"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gae5bb5538c01dcbf3f8b9d1fc52dc385a">CSL_DSS_VID_PIPE_SC_ENABLED_H</a>   ((uint32_t) CSL_DSS_VID1_ATTRIBUTES_RESIZEENABLE_VAL_HRESIZE)</td></tr>
+<tr class="memdesc:gae5bb5538c01dcbf3f8b9d1fc52dc385a"><td class="mdescLeft"> </td><td class="mdescRight">Horizontal scaling is enabled. <br/></td></tr>
+<tr class="separator:gae5bb5538c01dcbf3f8b9d1fc52dc385a"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga0add9ab4761fdd4bd2a09c4e140a35c0"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga0add9ab4761fdd4bd2a09c4e140a35c0"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#ga0add9ab4761fdd4bd2a09c4e140a35c0">CSL_DSS_VID_PIPE_SC_ENABLED_V</a>   ((uint32_t) CSL_DSS_VID1_ATTRIBUTES_RESIZEENABLE_VAL_VRESIZE)</td></tr>
+<tr class="memdesc:ga0add9ab4761fdd4bd2a09c4e140a35c0"><td class="mdescLeft"> </td><td class="mdescRight">Vertical scaling is enabled. <br/></td></tr>
+<tr class="separator:ga0add9ab4761fdd4bd2a09c4e140a35c0"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga00799c61e0313dc87418c766f836a958"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga00799c61e0313dc87418c766f836a958"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#ga00799c61e0313dc87418c766f836a958">CSL_DSS_VID_PIPE_SC_ENABLED_HV</a>   ((uint32_t) CSL_DSS_VID1_ATTRIBUTES_RESIZEENABLE_VAL_HVRESIZE)</td></tr>
+<tr class="memdesc:ga00799c61e0313dc87418c766f836a958"><td class="mdescLeft"> </td><td class="mdescRight">Both horizontal and vertical scaling is enabled. <br/></td></tr>
+<tr class="separator:ga00799c61e0313dc87418c766f836a958"><td class="memSeparator" colspan="2"> </td></tr>
+<tr><td colspan="2"><div class="groupHeader">DSS Video Pipe Preload Control Value</div></td></tr>
+<tr><td colspan="2"><div class="groupText"><p>DSS Video Pipe Preload Value can be fixed HW value or SW determined</p>
+<p><a class="anchor" id="CSL_DssVidPipePreloadControl"></a></p>
+</div></td></tr>
+<tr class="memitem:ga9920a3ec2d8c5a8707be21d19df2cdca"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga9920a3ec2d8c5a8707be21d19df2cdca"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#ga9920a3ec2d8c5a8707be21d19df2cdca">CSL_DSS_VID_PIPE_PRELOAD_CONTROL_SW</a>   ((uint32_t) CSL_DSS_VID1_ATTRIBUTES_BUFPRELOAD_VAL_DEFVAL)</td></tr>
+<tr class="memdesc:ga9920a3ec2d8c5a8707be21d19df2cdca"><td class="mdescLeft"> </td><td class="mdescRight">Value is defined by preload register. <br/></td></tr>
+<tr class="separator:ga9920a3ec2d8c5a8707be21d19df2cdca"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gaddf7744bff3546d7cf3dfcd5f50578e0"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaddf7744bff3546d7cf3dfcd5f50578e0"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gaddf7744bff3546d7cf3dfcd5f50578e0">CSL_DSS_VID_PIPE_PRELOAD_CONTROL_HW</a>   ((uint32_t) CSL_DSS_VID1_ATTRIBUTES_BUFPRELOAD_VAL_HIGHTHRES)</td></tr>
+<tr class="memdesc:gaddf7744bff3546d7cf3dfcd5f50578e0"><td class="mdescLeft"> </td><td class="mdescRight">HW pre-fetches pixels up to high threshold value. <br/></td></tr>
+<tr class="separator:gaddf7744bff3546d7cf3dfcd5f50578e0"><td class="memSeparator" colspan="2"> </td></tr>
+<tr><td colspan="2"><div class="groupHeader">DSS Video Pipe Priority Value</div></td></tr>
+<tr><td colspan="2"><div class="groupText"><p><a class="anchor" id="CSL_DssVidPipePriorityVal"></a></p>
+</div></td></tr>
+<tr class="memitem:ga8d4e4c078fa0fed3f7d3d3739d5ff7cd"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga8d4e4c078fa0fed3f7d3d3739d5ff7cd"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#ga8d4e4c078fa0fed3f7d3d3739d5ff7cd">CSL_DSS_VID_PIPE_PRIORITY_NORMAL</a>   ((uint32_t) CSL_DSS_VID1_ATTRIBUTES_ARBITRATION_VAL_NORMALPRIO)</td></tr>
+<tr class="memdesc:ga8d4e4c078fa0fed3f7d3d3739d5ff7cd"><td class="mdescLeft"> </td><td class="mdescRight">Priority of video pipeline is normal. <br/></td></tr>
+<tr class="separator:ga8d4e4c078fa0fed3f7d3d3739d5ff7cd"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gab90746bec79505e7a733d0f2bd72f5c4"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gab90746bec79505e7a733d0f2bd72f5c4"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gab90746bec79505e7a733d0f2bd72f5c4">CSL_DSS_VID_PIPE_PRIORITY_HIGH</a>   ((uint32_t) CSL_DSS_VID1_ATTRIBUTES_ARBITRATION_VAL_HIGHPRIO)</td></tr>
+<tr class="memdesc:gab90746bec79505e7a733d0f2bd72f5c4"><td class="mdescLeft"> </td><td class="mdescRight">Priority of video pipeline is high. <br/></td></tr>
+<tr class="separator:gab90746bec79505e7a733d0f2bd72f5c4"><td class="memSeparator" colspan="2"> </td></tr>
+<tr><td colspan="2"><div class="groupHeader">DSS Video Pipe Self Refresh Mode Control</div></td></tr>
+<tr><td colspan="2"><div class="groupText"><p><a class="anchor" id="CSL_DssVidPipeRefreshControl"></a></p>
+</div></td></tr>
+<tr class="memitem:gacb4282f5d79fd4252da0e6dfc0a6e124"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gacb4282f5d79fd4252da0e6dfc0a6e124"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gacb4282f5d79fd4252da0e6dfc0a6e124">CSL_DSS_VID_PIPE_REFRESH_CONTROL_SW</a>   ((uint32_t) CSL_DSS_VID1_ATTRIBUTES_SELFREFRESHAUTO_VAL_SELFREFRESHAUTODIS)</td></tr>
+<tr class="memdesc:gacb4282f5d79fd4252da0e6dfc0a6e124"><td class="mdescLeft"> </td><td class="mdescRight">Transition is controlled by SW. <br/></td></tr>
+<tr class="separator:gacb4282f5d79fd4252da0e6dfc0a6e124"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gaa791b8ccb4cccc15ca17524094cfb280"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaa791b8ccb4cccc15ca17524094cfb280"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gaa791b8ccb4cccc15ca17524094cfb280">CSL_DSS_VID_PIPE_REFRESH_CONTROL_HW</a>   ((uint32_t) CSL_DSS_VID1_ATTRIBUTES_SELFREFRESHAUTO_VAL_SELFREFRESHAUTOEN)</td></tr>
+<tr class="memdesc:gaa791b8ccb4cccc15ca17524094cfb280"><td class="mdescLeft"> </td><td class="mdescRight">Transition is controlled by HW. <br/></td></tr>
+<tr class="separator:gaa791b8ccb4cccc15ca17524094cfb280"><td class="memSeparator" colspan="2"> </td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="typedef-members"></a>
+Typedefs</h2></td></tr>
+<tr class="memitem:gafdca0345c9254a9bdbcd6e4a2ee000f6"><td class="memItemLeft" align="right" valign="top">typedef CSL_dss_vid1Regs </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gafdca0345c9254a9bdbcd6e4a2ee000f6">CSL_dss_pipeRegs</a></td></tr>
+<tr class="memdesc:gafdca0345c9254a9bdbcd6e4a2ee000f6"><td class="mdescLeft"> </td><td class="mdescRight">DSS Video Pipe Registers. <a href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gafdca0345c9254a9bdbcd6e4a2ee000f6">More...</a><br/></td></tr>
+<tr class="separator:gafdca0345c9254a9bdbcd6e4a2ee000f6"><td class="memSeparator" colspan="2"> </td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a>
+Functions</h2></td></tr>
+<tr class="memitem:ga6d983ffe721b5a1b602bfa53995f1c76"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#ga6d983ffe721b5a1b602bfa53995f1c76">CSL_dssVidPipeSetConfig</a> (<a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gafdca0345c9254a9bdbcd6e4a2ee000f6">CSL_dss_pipeRegs</a> *pipeRegs, const <a class="el" href="struct_c_s_l___dss_vid_pipe_cfg.html">CSL_DssVidPipeCfg</a> *pipeCfg, const <a class="el" href="struct_c_s_l___dss_vid_pipe_v_c1_cfg.html">CSL_DssVidPipeVC1Cfg</a> *vc1Cfg)</td></tr>
+<tr class="memdesc:ga6d983ffe721b5a1b602bfa53995f1c76"><td class="mdescLeft"> </td><td class="mdescRight">Configure the Video Pipe. <a href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#ga6d983ffe721b5a1b602bfa53995f1c76">More...</a><br/></td></tr>
+<tr class="separator:ga6d983ffe721b5a1b602bfa53995f1c76"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gaf3bd47c49aa8edd65bfd202779cdd0a2"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gaf3bd47c49aa8edd65bfd202779cdd0a2">CSL_dssVidPipeSetDmaConfig</a> (<a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gafdca0345c9254a9bdbcd6e4a2ee000f6">CSL_dss_pipeRegs</a> *pipeRegs, const <a class="el" href="struct_c_s_l___dss_vid_pipe_dma_cfg.html">CSL_DssVidPipeDmaCfg</a> *dmaCfg)</td></tr>
+<tr class="memdesc:gaf3bd47c49aa8edd65bfd202779cdd0a2"><td class="mdescLeft"> </td><td class="mdescRight">Configure the Video Pipe DMA parameters. <a href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gaf3bd47c49aa8edd65bfd202779cdd0a2">More...</a><br/></td></tr>
+<tr class="separator:gaf3bd47c49aa8edd65bfd202779cdd0a2"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga0b9cbe7775795bca5b9a8904ec9fc4b1"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#ga0b9cbe7775795bca5b9a8904ec9fc4b1">CSL_dssVidPipeEnableTransparency</a> (<a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gafdca0345c9254a9bdbcd6e4a2ee000f6">CSL_dss_pipeRegs</a> *pipeRegs, const <a class="el" href="struct_c_s_l___dss_vid_pipe_luma_cfg.html">CSL_DssVidPipeLumaCfg</a> *lumaCfg)</td></tr>
+<tr class="memdesc:ga0b9cbe7775795bca5b9a8904ec9fc4b1"><td class="mdescLeft"> </td><td class="mdescRight">Enable the Luma Key transparency matching and set luma params. <a href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#ga0b9cbe7775795bca5b9a8904ec9fc4b1">More...</a><br/></td></tr>
+<tr class="separator:ga0b9cbe7775795bca5b9a8904ec9fc4b1"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga3646182313235e92362cd843fdc6c2e6"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#ga3646182313235e92362cd843fdc6c2e6">CSL_dssVidPipeSetAlphaConfig</a> (<a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gafdca0345c9254a9bdbcd6e4a2ee000f6">CSL_dss_pipeRegs</a> *pipeRegs, const <a class="el" href="struct_c_s_l___dss_vid_pipe_alpha_cfg.html">CSL_DssVidPipeAlphaCfg</a> *alphaCfg)</td></tr>
+<tr class="memdesc:ga3646182313235e92362cd843fdc6c2e6"><td class="mdescLeft"> </td><td class="mdescRight">Set DSS Video Pipe Alpha parameters. <a href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#ga3646182313235e92362cd843fdc6c2e6">More...</a><br/></td></tr>
+<tr class="separator:ga3646182313235e92362cd843fdc6c2e6"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gacebfcb0b4ae57fa7a1ce3c73f6b552e8"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gacebfcb0b4ae57fa7a1ce3c73f6b552e8">CSL_dssVidPipeSetCSCCoeff</a> (<a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gafdca0345c9254a9bdbcd6e4a2ee000f6">CSL_dss_pipeRegs</a> *pipeRegs, const <a class="el" href="struct_c_s_l___dss_csc_coeff.html">CSL_DssCscCoeff</a> *coeff)</td></tr>
+<tr class="memdesc:gacebfcb0b4ae57fa7a1ce3c73f6b552e8"><td class="mdescLeft"> </td><td class="mdescRight">Configure the coefficients for Color Space Conversion. <a href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gacebfcb0b4ae57fa7a1ce3c73f6b552e8">More...</a><br/></td></tr>
+<tr class="separator:gacebfcb0b4ae57fa7a1ce3c73f6b552e8"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga11ed49990e9b63ecbf167cff5f6a9755"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#ga11ed49990e9b63ecbf167cff5f6a9755">CSL_dssVidPipeSetBuffAddr</a> (<a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gafdca0345c9254a9bdbcd6e4a2ee000f6">CSL_dss_pipeRegs</a> *pipeRegs, uint32_t field, uint64_t baseAddrRGBY, uint64_t baseAddrUV)</td></tr>
+<tr class="memdesc:ga11ed49990e9b63ecbf167cff5f6a9755"><td class="mdescLeft"> </td><td class="mdescRight">Configure the coefficients for Color Space Conversion. <a href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#ga11ed49990e9b63ecbf167cff5f6a9755">More...</a><br/></td></tr>
+<tr class="separator:ga11ed49990e9b63ecbf167cff5f6a9755"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gac037fe8b1ea6f506c6b0d00fd4a84491"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gac037fe8b1ea6f506c6b0d00fd4a84491">CSL_dssVidPipeEnable</a> (<a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gafdca0345c9254a9bdbcd6e4a2ee000f6">CSL_dss_pipeRegs</a> *pipeRegs, uint32_t enable)</td></tr>
+<tr class="memdesc:gac037fe8b1ea6f506c6b0d00fd4a84491"><td class="mdescLeft"> </td><td class="mdescRight">Enable the DSS Video Pipe. <a href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gac037fe8b1ea6f506c6b0d00fd4a84491">More...</a><br/></td></tr>
+<tr class="separator:gac037fe8b1ea6f506c6b0d00fd4a84491"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga70f77613b5b22a937388f5b072a7f74d"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#ga70f77613b5b22a937388f5b072a7f74d">CSL_dssVidPipeSetSafetySignSeedVal</a> (<a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gafdca0345c9254a9bdbcd6e4a2ee000f6">CSL_dss_pipeRegs</a> *pipeRegs, uint32_t signSeedVal)</td></tr>
+<tr class="memdesc:ga70f77613b5b22a937388f5b072a7f74d"><td class="mdescLeft"> </td><td class="mdescRight">Set the seed value for the signature calculation. <a href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#ga70f77613b5b22a937388f5b072a7f74d">More...</a><br/></td></tr>
+<tr class="separator:ga70f77613b5b22a937388f5b072a7f74d"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga37238e9b68bd88742eb54cca7c3cd7a8"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#ga37238e9b68bd88742eb54cca7c3cd7a8">CSL_dssVidPipeSetSafetyReferenceSign</a> (<a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gafdca0345c9254a9bdbcd6e4a2ee000f6">CSL_dss_pipeRegs</a> *pipeRegs, uint32_t referenceSign)</td></tr>
+<tr class="memdesc:ga37238e9b68bd88742eb54cca7c3cd7a8"><td class="mdescLeft"> </td><td class="mdescRight">Set the reference safety signature for data correctness check. <a href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#ga37238e9b68bd88742eb54cca7c3cd7a8">More...</a><br/></td></tr>
+<tr class="separator:ga37238e9b68bd88742eb54cca7c3cd7a8"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gae5dc5282a40648fd2f69165e7a373265"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gae5dc5282a40648fd2f69165e7a373265">CSL_dssVidPipeSetSafetyChkConfig</a> (<a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gafdca0345c9254a9bdbcd6e4a2ee000f6">CSL_dss_pipeRegs</a> *pipeRegs, const <a class="el" href="struct_c_s_l___dss_safety_chk_cfg.html">CSL_DssSafetyChkCfg</a> *safetyCfg)</td></tr>
+<tr class="memdesc:gae5dc5282a40648fd2f69165e7a373265"><td class="mdescLeft"> </td><td class="mdescRight">Configure the Safety Check Params. <a href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gae5dc5282a40648fd2f69165e7a373265">More...</a><br/></td></tr>
+<tr class="separator:gae5dc5282a40648fd2f69165e7a373265"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gaf51512cbab443cebde3013bc6bf212aa"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gaf51512cbab443cebde3013bc6bf212aa">CSL_dssVidPipeGetSafetySign</a> (const <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gafdca0345c9254a9bdbcd6e4a2ee000f6">CSL_dss_pipeRegs</a> *pipeRegs)</td></tr>
+<tr class="memdesc:gaf51512cbab443cebde3013bc6bf212aa"><td class="mdescLeft"> </td><td class="mdescRight">Get the Safety Signature. <a href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gaf51512cbab443cebde3013bc6bf212aa">More...</a><br/></td></tr>
+<tr class="separator:gaf51512cbab443cebde3013bc6bf212aa"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga3095d9a0f35cd85fba7c2be6b14d798d"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#ga3095d9a0f35cd85fba7c2be6b14d798d">CSL_dssVidPipeSetMflagConfig</a> (<a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gafdca0345c9254a9bdbcd6e4a2ee000f6">CSL_dss_pipeRegs</a> *pipeRegs, const <a class="el" href="struct_c_s_l___dss_vid_pipe_m_flag_cfg.html">CSL_DssVidPipeMFlagCfg</a> *mflagCfg)</td></tr>
+<tr class="memdesc:ga3095d9a0f35cd85fba7c2be6b14d798d"><td class="mdescLeft"> </td><td class="mdescRight">Set the MFLAG configuration. <a href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#ga3095d9a0f35cd85fba7c2be6b14d798d">More...</a><br/></td></tr>
+<tr class="separator:ga3095d9a0f35cd85fba7c2be6b14d798d"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gaf4dc4e4142893b328dd75906147dde8f"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gaf4dc4e4142893b328dd75906147dde8f">CSL_dssVidPipeCropEnable</a> (<a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gafdca0345c9254a9bdbcd6e4a2ee000f6">CSL_dss_pipeRegs</a> *pipeRegs, uint32_t enable)</td></tr>
+<tr class="memdesc:gaf4dc4e4142893b328dd75906147dde8f"><td class="mdescLeft"> </td><td class="mdescRight">Enable the crop in DSS Video Pipe. <a href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gaf4dc4e4142893b328dd75906147dde8f">More...</a><br/></td></tr>
+<tr class="separator:gaf4dc4e4142893b328dd75906147dde8f"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gae2ea4d9e0e2d9662d1bda20ec77567dc"><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gae2ea4d9e0e2d9662d1bda20ec77567dc">CSL_dssVidPipeCfgInit</a> (<a class="el" href="struct_c_s_l___dss_vid_pipe_cfg.html">CSL_DssVidPipeCfg</a> *pipeCfg)</td></tr>
+<tr class="memdesc:gae2ea4d9e0e2d9662d1bda20ec77567dc"><td class="mdescLeft"> </td><td class="mdescRight"><a class="el" href="struct_c_s_l___dss_vid_pipe_cfg.html" title="Configuration for DSS Video Pipe. ">CSL_DssVidPipeCfg</a> structure init function. <a href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gae2ea4d9e0e2d9662d1bda20ec77567dc">More...</a><br/></td></tr>
+<tr class="separator:gae2ea4d9e0e2d9662d1bda20ec77567dc"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga53cc07dd9deeeec69be494c89fd12812"><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#ga53cc07dd9deeeec69be494c89fd12812">CSL_dssVidPipeDmaCfgInit</a> (<a class="el" href="struct_c_s_l___dss_vid_pipe_dma_cfg.html">CSL_DssVidPipeDmaCfg</a> *dmaCfg)</td></tr>
+<tr class="memdesc:ga53cc07dd9deeeec69be494c89fd12812"><td class="mdescLeft"> </td><td class="mdescRight"><a class="el" href="struct_c_s_l___dss_vid_pipe_dma_cfg.html" title="DSS Video Pipe DMA related Config parameters. ">CSL_DssVidPipeDmaCfg</a> structure init function. <a href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#ga53cc07dd9deeeec69be494c89fd12812">More...</a><br/></td></tr>
+<tr class="separator:ga53cc07dd9deeeec69be494c89fd12812"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gaeec644be0c0f1f62da19eca5c1e9b877"><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gaeec644be0c0f1f62da19eca5c1e9b877">CSL_dssVidPipeLumaCfgInit</a> (<a class="el" href="struct_c_s_l___dss_vid_pipe_luma_cfg.html">CSL_DssVidPipeLumaCfg</a> *lumaCfg)</td></tr>
+<tr class="memdesc:gaeec644be0c0f1f62da19eca5c1e9b877"><td class="mdescLeft"> </td><td class="mdescRight"><a class="el" href="struct_c_s_l___dss_vid_pipe_luma_cfg.html" title="DSS Video Pipe Luma Key Config parameters. ">CSL_DssVidPipeLumaCfg</a> structure init function. <a href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gaeec644be0c0f1f62da19eca5c1e9b877">More...</a><br/></td></tr>
+<tr class="separator:gaeec644be0c0f1f62da19eca5c1e9b877"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga8a3d5286ff2be3f2056f554f1d5c92d7"><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#ga8a3d5286ff2be3f2056f554f1d5c92d7">CSL_dssVidPipeAlphaCfgInit</a> (<a class="el" href="struct_c_s_l___dss_vid_pipe_alpha_cfg.html">CSL_DssVidPipeAlphaCfg</a> *alphaCfg)</td></tr>
+<tr class="memdesc:ga8a3d5286ff2be3f2056f554f1d5c92d7"><td class="mdescLeft"> </td><td class="mdescRight"><a class="el" href="struct_c_s_l___dss_vid_pipe_alpha_cfg.html" title="DSS Video Pipe Alpha Config parameters. ">CSL_DssVidPipeAlphaCfg</a> structure init function. <a href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#ga8a3d5286ff2be3f2056f554f1d5c92d7">More...</a><br/></td></tr>
+<tr class="separator:ga8a3d5286ff2be3f2056f554f1d5c92d7"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gaf11746b1003b15855996b817cfe3d38a"><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gaf11746b1003b15855996b817cfe3d38a">CSL_dssVidPipeVC1CfgInit</a> (<a class="el" href="struct_c_s_l___dss_vid_pipe_v_c1_cfg.html">CSL_DssVidPipeVC1Cfg</a> *vc1Cfg)</td></tr>
+<tr class="memdesc:gaf11746b1003b15855996b817cfe3d38a"><td class="mdescLeft"> </td><td class="mdescRight"><a class="el" href="struct_c_s_l___dss_vid_pipe_v_c1_cfg.html" title="DSS Video Pipe VC1 configuration. ">CSL_DssVidPipeVC1Cfg</a> structure init function. <a href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gaf11746b1003b15855996b817cfe3d38a">More...</a><br/></td></tr>
+<tr class="separator:gaf11746b1003b15855996b817cfe3d38a"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga5d27f327524e3016a74de471e5eb38a1"><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#ga5d27f327524e3016a74de471e5eb38a1">CSL_dssVidPipeMFlagCfgInit</a> (<a class="el" href="struct_c_s_l___dss_vid_pipe_m_flag_cfg.html">CSL_DssVidPipeMFlagCfg</a> *mflagCfg)</td></tr>
+<tr class="memdesc:ga5d27f327524e3016a74de471e5eb38a1"><td class="mdescLeft"> </td><td class="mdescRight"><a class="el" href="struct_c_s_l___dss_vid_pipe_m_flag_cfg.html" title="DSS Video Pipe MFLAG Config parameters. ">CSL_DssVidPipeMFlagCfg</a> structure init function. <a href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#ga5d27f327524e3016a74de471e5eb38a1">More...</a><br/></td></tr>
+<tr class="separator:ga5d27f327524e3016a74de471e5eb38a1"><td class="memSeparator" colspan="2"> </td></tr>
+</table>
+<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
+<div class="textblock"><p>DSS Video Pipe CSL FL interface file. </p>
+</div></div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/csl__dss_video_port_8h.html b/packages/ti/drv/dss/docs/doxygen/html/csl__dss_video_port_8h.html
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+<li class="navelem"><a class="el" href="dir_f5943f6d28c724c9867ac930658f5901.html">csl</a></li><li class="navelem"><a class="el" href="dir_2c013fc7e98dc8ade314eba46bcbb0d6.html">src</a></li><li class="navelem"><a class="el" href="dir_063bd5b357e44d632c140cb38e979030.html">ip</a></li><li class="navelem"><a class="el" href="dir_9601e7bd9bffb8db00e0c1272827daa6.html">dss</a></li><li class="navelem"><a class="el" href="dir_61ed5367bdc2fa7807323d7b06750347.html">V4</a></li> </ul>
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+ <div class="headertitle">
+<div class="title">csl_dssVideoPort.h File Reference<div class="ingroups"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html">DSS Video Port CSL FL</a></div></div> </div>
+</div><!--header-->
+<div class="contents">
+
+<p>DSS Video Port CSL FL interface file.
+<a href="#details">More...</a></p>
+<table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="nested-classes"></a>
+Data Structures</h2></td></tr>
+<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_vp_gamma_cfg.html">CSL_DssVpGammaCfg</a></td></tr>
+<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">Gamma Correction configuration for DSS Video Port Output. <a href="struct_c_s_l___dss_vp_gamma_cfg.html#details">More...</a><br/></td></tr>
+<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_vp_lcd_tdm_cfg.html">CSL_DssVpLcdTdmCfg</a></td></tr>
+<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">LCD Configuration for Time Division Multiplexing. <a href="struct_c_s_l___dss_vp_lcd_tdm_cfg.html#details">More...</a><br/></td></tr>
+<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_vp_lcd_signal_polarity_cfg.html">CSL_DssVpLcdSignalPolarityCfg</a></td></tr>
+<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">Polarity of Active Video, Pixel Clock, HSync and VSync signals for the LCD. <a href="struct_c_s_l___dss_vp_lcd_signal_polarity_cfg.html#details">More...</a><br/></td></tr>
+<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_vp_lcd_adv_signal_cfg.html">CSL_DssVpLcdAdvSignalCfg</a></td></tr>
+<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">Advance Signal Configuration for the LCD. <a href="struct_c_s_l___dss_vp_lcd_adv_signal_cfg.html#details">More...</a><br/></td></tr>
+<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_vp_lcd_op_timing_cfg.html">CSL_DssVpLcdOpTimingCfg</a></td></tr>
+<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">Timing configuration for the LCD output. <a href="struct_c_s_l___dss_vp_lcd_op_timing_cfg.html#details">More...</a><br/></td></tr>
+<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_vp_lcd_blank_timing_cfg.html">CSL_DssVpLcdBlankTimingCfg</a></td></tr>
+<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">Blanking Timing parameters for the LCD. <a href="struct_c_s_l___dss_vp_lcd_blank_timing_cfg.html#details">More...</a><br/></td></tr>
+<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
+Macros</h2></td></tr>
+<tr><td colspan="2"><div class="groupHeader">Video Port CSC Position</div></td></tr>
+<tr><td colspan="2"><div class="groupText"><p>DSS Video Port Color Space Conversion block position wrt Gamma block</p>
+<p><a class="anchor" id="CSL_DssVpCscPos"></a></p>
+</div></td></tr>
+<tr class="memitem:ga9d8db056eb5e4a6dc1972200c70acf09"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga9d8db056eb5e4a6dc1972200c70acf09"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga9d8db056eb5e4a6dc1972200c70acf09">CSL_DSS_VP_CSC_POS_AFTER_GAMMA</a>   ((uint32_t) CSL_DSS_VP1_CONFIG_COLORCONVPOS_VAL_AFTERGAMMA)</td></tr>
+<tr class="memdesc:ga9d8db056eb5e4a6dc1972200c70acf09"><td class="mdescLeft"> </td><td class="mdescRight">CSC block is after GAMMA correction. <br/></td></tr>
+<tr class="separator:ga9d8db056eb5e4a6dc1972200c70acf09"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga7adc25e7daeddfff398a028a6f7af0b8"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga7adc25e7daeddfff398a028a6f7af0b8"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga7adc25e7daeddfff398a028a6f7af0b8">CSL_DSS_VP_CSC_POS_BEFORE_GAMMA</a>   ((uint32_t) CSL_DSS_VP1_CONFIG_COLORCONVPOS_VAL_BEFOREGAMMA)</td></tr>
+<tr class="memdesc:ga7adc25e7daeddfff398a028a6f7af0b8"><td class="mdescLeft"> </td><td class="mdescRight">CSC block is before GAMMA correction. <br/></td></tr>
+<tr class="separator:ga7adc25e7daeddfff398a028a6f7af0b8"><td class="memSeparator" colspan="2"> </td></tr>
+<tr><td colspan="2"><div class="groupHeader">TDM Mode Unused Bits Level</div></td></tr>
+<tr><td colspan="2"><div class="groupText"><p>State of unused bits in TDM mode for the VP output</p>
+<p><a class="anchor" id="CSL_DssVpTdmUnusedBitsLevel"></a></p>
+</div></td></tr>
+<tr class="memitem:gab2d941b89a9b42c988e72d4500379661"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gab2d941b89a9b42c988e72d4500379661"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gab2d941b89a9b42c988e72d4500379661">CSL_DSS_VP_TDM_UNUSED_BITS_LEVEL_LOW</a>   ((uint32_t) CSL_DSS_VP1_CONTROL_TDMUNUSEDBITS_VAL_LOWLEVEL)</td></tr>
+<tr class="memdesc:gab2d941b89a9b42c988e72d4500379661"><td class="mdescLeft"> </td><td class="mdescRight">Low level. <br/></td></tr>
+<tr class="separator:gab2d941b89a9b42c988e72d4500379661"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gac426f8586cc7293b20148c1dfd1cec3a"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gac426f8586cc7293b20148c1dfd1cec3a"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gac426f8586cc7293b20148c1dfd1cec3a">CSL_DSS_VP_TDM_UNUSED_BITS_LEVEL_HIGH</a>   ((uint32_t) CSL_DSS_VP1_CONTROL_TDMUNUSEDBITS_VAL_HIGHLEVEL)</td></tr>
+<tr class="memdesc:gac426f8586cc7293b20148c1dfd1cec3a"><td class="mdescLeft"> </td><td class="mdescRight">High level. <br/></td></tr>
+<tr class="separator:gac426f8586cc7293b20148c1dfd1cec3a"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga58a52d1ec3bd962fe6ec5996d788cbe5"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga58a52d1ec3bd962fe6ec5996d788cbe5"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga58a52d1ec3bd962fe6ec5996d788cbe5">CSL_DSS_VP_TDM_UNUSED_BITS_LEVEL_UNCHANGED</a>   ((uint32_t) CSL_DSS_VP1_CONTROL_TDMUNUSEDBITS_VAL_UNCHANGED)</td></tr>
+<tr class="memdesc:ga58a52d1ec3bd962fe6ec5996d788cbe5"><td class="mdescLeft"> </td><td class="mdescRight">Unchanged level. <br/></td></tr>
+<tr class="separator:ga58a52d1ec3bd962fe6ec5996d788cbe5"><td class="memSeparator" colspan="2"> </td></tr>
+<tr><td colspan="2"><div class="groupHeader">TDM Cycle format</div></td></tr>
+<tr><td colspan="2"><div class="groupText"><p><a class="anchor" id="CSL_DssVpTdmCycleFormat"></a></p>
+</div></td></tr>
+<tr class="memitem:ga5b4659b24eb81a27c27f0d409fd51460"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga5b4659b24eb81a27c27f0d409fd51460"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga5b4659b24eb81a27c27f0d409fd51460">CSL_DSS_VP_TDM_CYCLE_1PERPIXEL</a>   ((uint32_t) CSL_DSS_VP1_CONTROL_TDMCYCLEFORMAT_VAL_1CYCPERPIX)</td></tr>
+<tr class="memdesc:ga5b4659b24eb81a27c27f0d409fd51460"><td class="mdescLeft"> </td><td class="mdescRight">1 cycle per pixel <br/></td></tr>
+<tr class="separator:ga5b4659b24eb81a27c27f0d409fd51460"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga5c6498fbbc637492bee5fec53327d8d2"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga5c6498fbbc637492bee5fec53327d8d2"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga5c6498fbbc637492bee5fec53327d8d2">CSL_DSS_VP_TDM_CYCLE_2PERPIXEL</a>   ((uint32_t) CSL_DSS_VP1_CONTROL_TDMCYCLEFORMAT_VAL_2CYCPERPIX)</td></tr>
+<tr class="memdesc:ga5c6498fbbc637492bee5fec53327d8d2"><td class="mdescLeft"> </td><td class="mdescRight">2 cycles per pixel <br/></td></tr>
+<tr class="separator:ga5c6498fbbc637492bee5fec53327d8d2"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga9f47ee0306de87ccadf8e16a57276cf0"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga9f47ee0306de87ccadf8e16a57276cf0"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga9f47ee0306de87ccadf8e16a57276cf0">CSL_DSS_VP_TDM_CYCLE_3PERPIXEL</a>   ((uint32_t) CSL_DSS_VP1_CONTROL_TDMCYCLEFORMAT_VAL_3CYCPERPIX)</td></tr>
+<tr class="memdesc:ga9f47ee0306de87ccadf8e16a57276cf0"><td class="mdescLeft"> </td><td class="mdescRight">3 cycles per pixel <br/></td></tr>
+<tr class="separator:ga9f47ee0306de87ccadf8e16a57276cf0"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga81528f8f4538347b9f0b9e5b1c47374a"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga81528f8f4538347b9f0b9e5b1c47374a"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga81528f8f4538347b9f0b9e5b1c47374a">CSL_DSS_VP_TDM_CYCLE_3PER2PIXEL</a>   ((uint32_t) CSL_DSS_VP1_CONTROL_TDMCYCLEFORMAT_VAL_3CYCPER2PIX)</td></tr>
+<tr class="memdesc:ga81528f8f4538347b9f0b9e5b1c47374a"><td class="mdescLeft"> </td><td class="mdescRight">3 cycles per 2 pixels <br/></td></tr>
+<tr class="separator:ga81528f8f4538347b9f0b9e5b1c47374a"><td class="memSeparator" colspan="2"> </td></tr>
+<tr><td colspan="2"><div class="groupHeader">Output interface width in TDM mode</div></td></tr>
+<tr><td colspan="2"><div class="groupText"><p><a class="anchor" id="CSL_DssVpTdmParallelMode"></a></p>
+</div></td></tr>
+<tr class="memitem:gacd33fff8fc6d940d149b39ca4dd2f032"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gacd33fff8fc6d940d149b39ca4dd2f032"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gacd33fff8fc6d940d149b39ca4dd2f032">CSL_DSS_VP_TDM_PARALLEL_OUTPUT_8BIT</a>   ((uint32_t) CSL_DSS_VP1_CONTROL_TDMPARALLELMODE_VAL_8BPARAINT)</td></tr>
+<tr class="memdesc:gacd33fff8fc6d940d149b39ca4dd2f032"><td class="mdescLeft"> </td><td class="mdescRight">8-bit parallel output interface selected <br/></td></tr>
+<tr class="separator:gacd33fff8fc6d940d149b39ca4dd2f032"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gabf1ad83065c73fc074ed85876c5e505e"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gabf1ad83065c73fc074ed85876c5e505e"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gabf1ad83065c73fc074ed85876c5e505e">CSL_DSS_VP_TDM_PARALLEL_OUTPUT_9BIT</a>   ((uint32_t) CSL_DSS_VP1_CONTROL_TDMPARALLELMODE_VAL_9BPARAINT)</td></tr>
+<tr class="memdesc:gabf1ad83065c73fc074ed85876c5e505e"><td class="mdescLeft"> </td><td class="mdescRight">9-bit parallel output interface selected <br/></td></tr>
+<tr class="separator:gabf1ad83065c73fc074ed85876c5e505e"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gac83301ee887a6562c3ec89a921c4b74f"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gac83301ee887a6562c3ec89a921c4b74f"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gac83301ee887a6562c3ec89a921c4b74f">CSL_DSS_VP_TDM_PARALLEL_OUTPUT_12BIT</a>   ((uint32_t) CSL_DSS_VP1_CONTROL_TDMPARALLELMODE_VAL_12BPARAINT)</td></tr>
+<tr class="memdesc:gac83301ee887a6562c3ec89a921c4b74f"><td class="mdescLeft"> </td><td class="mdescRight">12-bit parallel output interface selected <br/></td></tr>
+<tr class="separator:gac83301ee887a6562c3ec89a921c4b74f"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga8715d15d4ee5eebd9ea7b15adcf22394"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga8715d15d4ee5eebd9ea7b15adcf22394"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga8715d15d4ee5eebd9ea7b15adcf22394">CSL_DSS_VP_TDM_PARALLEL_OUTPUT_16BIT</a>   ((uint32_t) CSL_DSS_VP1_CONTROL_TDMPARALLELMODE_VAL_16BPARAINT)</td></tr>
+<tr class="memdesc:ga8715d15d4ee5eebd9ea7b15adcf22394"><td class="mdescLeft"> </td><td class="mdescRight">16-bit parallel output interface selected <br/></td></tr>
+<tr class="separator:ga8715d15d4ee5eebd9ea7b15adcf22394"><td class="memSeparator" colspan="2"> </td></tr>
+<tr><td colspan="2"><div class="groupHeader">LCD HSync VSync Alignment</div></td></tr>
+<tr><td colspan="2"><div class="groupText"><p><a class="anchor" id="CSL_DssVpLcdHVSyncAlign"></a></p>
+</div></td></tr>
+<tr class="memitem:gab6a57958037687c92ae5d39ef7e4633f"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gab6a57958037687c92ae5d39ef7e4633f"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gab6a57958037687c92ae5d39ef7e4633f">CSL_DSS_VP_HVSYNC_NOT_ALIGNED</a>   ((uint32_t) CSL_DSS_VP1_POL_FREQ_ALIGN_VAL_NOTALIGNED)</td></tr>
+<tr class="memdesc:gab6a57958037687c92ae5d39ef7e4633f"><td class="mdescLeft"> </td><td class="mdescRight">HSYNC and VSYNC are not aligned. <br/></td></tr>
+<tr class="separator:gab6a57958037687c92ae5d39ef7e4633f"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga744ce9e2dba4875d10456de204cdf564"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga744ce9e2dba4875d10456de204cdf564"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga744ce9e2dba4875d10456de204cdf564">CSL_DSS_VP_HVSYNC_ALIGNED</a>   ((uint32_t) CSL_DSS_VP1_POL_FREQ_ALIGN_VAL_ALIGNED)</td></tr>
+<tr class="memdesc:ga744ce9e2dba4875d10456de204cdf564"><td class="mdescLeft"> </td><td class="mdescRight">HSYNC and VSYNC assertions are aligned. <br/></td></tr>
+<tr class="separator:ga744ce9e2dba4875d10456de204cdf564"><td class="memSeparator" colspan="2"> </td></tr>
+<tr><td colspan="2"><div class="groupHeader">LCD HSYNC/VSYNC pixel clock control</div></td></tr>
+<tr><td colspan="2"><div class="groupText"><p><a class="anchor" id="CSL_DssVpLcdHVClkControl"></a></p>
+</div></td></tr>
+<tr class="memitem:ga2b87767e34b62775d52ef6022789bdd0"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga2b87767e34b62775d52ef6022789bdd0"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga2b87767e34b62775d52ef6022789bdd0">CSL_DSS_VP_HVCLK_CONTROL_OFF</a>   ((uint32_t) CSL_DSS_VP1_POL_FREQ_ONOFF_VAL_DOPEDPCK)</td></tr>
+<tr class="memdesc:ga2b87767e34b62775d52ef6022789bdd0"><td class="mdescLeft"> </td><td class="mdescRight">HSYNC and VSYNC are driven on opposite edges of the pixel clock than pixel data. <br/></td></tr>
+<tr class="separator:ga2b87767e34b62775d52ef6022789bdd0"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gac3a10008ac4fbc32ef1869c751602925"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gac3a10008ac4fbc32ef1869c751602925"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gac3a10008ac4fbc32ef1869c751602925">CSL_DSS_VP_HVCLK_CONTROL_ON</a>   ((uint32_t) CSL_DSS_VP1_POL_FREQ_ONOFF_VAL_DBIT16)</td></tr>
+<tr class="memdesc:gac3a10008ac4fbc32ef1869c751602925"><td class="mdescLeft"> </td><td class="mdescRight">HSYNC and VSYNC are driven according to hVClkRiseFall value. <br/></td></tr>
+<tr class="separator:gac3a10008ac4fbc32ef1869c751602925"><td class="memSeparator" colspan="2"> </td></tr>
+<tr><td colspan="2"><div class="groupHeader">Delta Lines Per Panel</div></td></tr>
+<tr><td colspan="2"><div class="groupText"><p>Delta size value of the odd field compared to the even field</p>
+<p><a class="anchor" id="CSL_DssVpDeltaLpp"></a></p>
+</div></td></tr>
+<tr class="memitem:ga0d0f13dd26e92dba642f40387e517b6a"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga0d0f13dd26e92dba642f40387e517b6a"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga0d0f13dd26e92dba642f40387e517b6a">CSL_DSS_VP_LPP_DELTA_ZERO</a>   ((uint32_t) CSL_DSS_VP1_SIZE_SCREEN_DELTA_LPP_VAL_SAME)</td></tr>
+<tr class="memdesc:ga0d0f13dd26e92dba642f40387e517b6a"><td class="mdescLeft"> </td><td class="mdescRight">Odd field has same size as even. <br/></td></tr>
+<tr class="separator:ga0d0f13dd26e92dba642f40387e517b6a"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga219596f8e8c8b043dde6c1f05c36f570"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga219596f8e8c8b043dde6c1f05c36f570"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga219596f8e8c8b043dde6c1f05c36f570">CSL_DSS_VP_LPP_DELTA_PLUSONE</a>   ((uint32_t) CSL_DSS_VP1_SIZE_SCREEN_DELTA_LPP_VAL_PLUSONE)</td></tr>
+<tr class="memdesc:ga219596f8e8c8b043dde6c1f05c36f570"><td class="mdescLeft"> </td><td class="mdescRight">Odd field is equal to even field + 1. <br/></td></tr>
+<tr class="separator:ga219596f8e8c8b043dde6c1f05c36f570"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga1a9e8a871ac9b403dfe0f0d208b3c29f"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga1a9e8a871ac9b403dfe0f0d208b3c29f"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga1a9e8a871ac9b403dfe0f0d208b3c29f">CSL_DSS_VP_LPP_DELTA_MINUSONE</a>   ((uint32_t) CSL_DSS_VP1_SIZE_SCREEN_DELTA_LPP_VAL_MINUSONE)</td></tr>
+<tr class="memdesc:ga1a9e8a871ac9b403dfe0f0d208b3c29f"><td class="mdescLeft"> </td><td class="mdescRight">Odd field is equal to even field - 1. <br/></td></tr>
+<tr class="separator:ga1a9e8a871ac9b403dfe0f0d208b3c29f"><td class="memSeparator" colspan="2"> </td></tr>
+<tr><td colspan="2"><div class="groupHeader">Video Port First Field</div></td></tr>
+<tr><td colspan="2"><div class="groupText"><p>First Field to Video Port output in case of interlace mode</p>
+<p><a class="anchor" id="CSL_DssVpFidFirstVal"></a></p>
+</div></td></tr>
+<tr class="memitem:gab6a1a6b67d60bff5578cc42bc2bc0114"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gab6a1a6b67d60bff5578cc42bc2bc0114"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gab6a1a6b67d60bff5578cc42bc2bc0114">CSL_DSS_VP_FID_FIRST_EVEN</a>   ((uint32_t) CSL_DSS_VP1_CONFIG_FIDFIRST_VAL_EVEN)</td></tr>
+<tr class="memdesc:gab6a1a6b67d60bff5578cc42bc2bc0114"><td class="mdescLeft"> </td><td class="mdescRight">First field is even. <br/></td></tr>
+<tr class="separator:gab6a1a6b67d60bff5578cc42bc2bc0114"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga62dd57b2769fa39f4459379b8f432465"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga62dd57b2769fa39f4459379b8f432465"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga62dd57b2769fa39f4459379b8f432465">CSL_DSS_VP_FID_FIRST_ODD</a>   ((uint32_t) CSL_DSS_VP1_CONFIG_FIDFIRST_VAL_ODD)</td></tr>
+<tr class="memdesc:ga62dd57b2769fa39f4459379b8f432465"><td class="mdescLeft"> </td><td class="mdescRight">First field is odd. <br/></td></tr>
+<tr class="separator:ga62dd57b2769fa39f4459379b8f432465"><td class="memSeparator" colspan="2"> </td></tr>
+<tr><td colspan="2"><div class="groupHeader">Video Port Stall Mode</div></td></tr>
+<tr><td colspan="2"><div class="groupText"><p>The type of transfer in Stall mode</p>
+<p><a class="anchor" id="CSL_DssVpStallMode"></a></p>
+</div></td></tr>
+<tr class="memitem:gabd8aa22176d523bf6927f02922e6a965"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gabd8aa22176d523bf6927f02922e6a965"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gabd8aa22176d523bf6927f02922e6a965">CSL_DSS_VP_STALL_MODE_COMMAND</a>   ((uint32_t) CSL_DSS_VP1_CONTROL_STALLMODETYPE_VAL_COMMANDMODE)</td></tr>
+<tr class="memdesc:gabd8aa22176d523bf6927f02922e6a965"><td class="mdescLeft"> </td><td class="mdescRight">Stall mode is command. <br/></td></tr>
+<tr class="separator:gabd8aa22176d523bf6927f02922e6a965"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga1ae77b1f37ae1fafa15adc649b49f309"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga1ae77b1f37ae1fafa15adc649b49f309"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga1ae77b1f37ae1fafa15adc649b49f309">CSL_DSS_VP_STALL_MODE_VIDEO</a>   ((uint32_t) CSL_DSS_VP1_CONTROL_STALLMODETYPE_VAL_VIDEOMODE)</td></tr>
+<tr class="memdesc:ga1ae77b1f37ae1fafa15adc649b49f309"><td class="mdescLeft"> </td><td class="mdescRight">Stall mode is video. <br/></td></tr>
+<tr class="separator:ga1ae77b1f37ae1fafa15adc649b49f309"><td class="memSeparator" colspan="2"> </td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="typedef-members"></a>
+Typedefs</h2></td></tr>
+<tr class="memitem:gaaaf231996a0d81bd23a1460d729dad23"><td class="memItemLeft" align="right" valign="top">typedef CSL_dss_vp1Regs </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gaaaf231996a0d81bd23a1460d729dad23">CSL_dss_vpRegs</a></td></tr>
+<tr class="memdesc:gaaaf231996a0d81bd23a1460d729dad23"><td class="mdescLeft"> </td><td class="mdescRight">DSS Video Port Registers. <a href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gaaaf231996a0d81bd23a1460d729dad23">More...</a><br/></td></tr>
+<tr class="separator:gaaaf231996a0d81bd23a1460d729dad23"><td class="memSeparator" colspan="2"> </td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a>
+Functions</h2></td></tr>
+<tr class="memitem:ga9c61092eddfa87bcba87cc116fb8bd1d"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga9c61092eddfa87bcba87cc116fb8bd1d">CSL_dssVpEnable</a> (<a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gaaaf231996a0d81bd23a1460d729dad23">CSL_dss_vpRegs</a> *vpRegs, uint32_t enable)</td></tr>
+<tr class="memdesc:ga9c61092eddfa87bcba87cc116fb8bd1d"><td class="mdescLeft"> </td><td class="mdescRight">Enable the DSS Video Port. <a href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga9c61092eddfa87bcba87cc116fb8bd1d">More...</a><br/></td></tr>
+<tr class="separator:ga9c61092eddfa87bcba87cc116fb8bd1d"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga0ba989884315a28b21a62a722574865d"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga0ba989884315a28b21a62a722574865d">CSL_dssVpSetGoBit</a> (<a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gaaaf231996a0d81bd23a1460d729dad23">CSL_dss_vpRegs</a> *vpRegs)</td></tr>
+<tr class="memdesc:ga0ba989884315a28b21a62a722574865d"><td class="mdescLeft"> </td><td class="mdescRight">GO Command for the VP output. It is used to synchronize the pipelines associated with the VP output. <a href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga0ba989884315a28b21a62a722574865d">More...</a><br/></td></tr>
+<tr class="separator:ga0ba989884315a28b21a62a722574865d"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga48c44cb30d94ee22ddd885998830d852"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga48c44cb30d94ee22ddd885998830d852">CSL_dssVpSetLcdTdmConfig</a> (<a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gaaaf231996a0d81bd23a1460d729dad23">CSL_dss_vpRegs</a> *vpRegs, const <a class="el" href="struct_c_s_l___dss_vp_lcd_tdm_cfg.html">CSL_DssVpLcdTdmCfg</a> *lcdTdmCfg)</td></tr>
+<tr class="memdesc:ga48c44cb30d94ee22ddd885998830d852"><td class="mdescLeft"> </td><td class="mdescRight">Configure the LCD TDM(Time division multiplexing) parameters. <a href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga48c44cb30d94ee22ddd885998830d852">More...</a><br/></td></tr>
+<tr class="separator:ga48c44cb30d94ee22ddd885998830d852"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga1a4f05443f8ba7bffea84d63b43788ab"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga1a4f05443f8ba7bffea84d63b43788ab">CSL_dssVpSetLcdLineNum</a> (<a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gaaaf231996a0d81bd23a1460d729dad23">CSL_dss_vpRegs</a> *vpRegs, uint32_t lineNum)</td></tr>
+<tr class="memdesc:ga1a4f05443f8ba7bffea84d63b43788ab"><td class="mdescLeft"> </td><td class="mdescRight">Set the Line Number at which the interrupt should be generated. <a href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga1a4f05443f8ba7bffea84d63b43788ab">More...</a><br/></td></tr>
+<tr class="separator:ga1a4f05443f8ba7bffea84d63b43788ab"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga447444c64439d7b1210a9b696dd8a673"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga447444c64439d7b1210a9b696dd8a673">CSL_dssVpGetLcdLineNum</a> (const <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gaaaf231996a0d81bd23a1460d729dad23">CSL_dss_vpRegs</a> *vpRegs)</td></tr>
+<tr class="memdesc:ga447444c64439d7b1210a9b696dd8a673"><td class="mdescLeft"> </td><td class="mdescRight">Get the number of line currently displayed. <a href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga447444c64439d7b1210a9b696dd8a673">More...</a><br/></td></tr>
+<tr class="separator:ga447444c64439d7b1210a9b696dd8a673"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga0225f72557517955d94f1a6ce815ed14"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga0225f72557517955d94f1a6ce815ed14">CSL_dssVpSetLcdOpTimingConfig</a> (<a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gaaaf231996a0d81bd23a1460d729dad23">CSL_dss_vpRegs</a> *vpRegs, const <a class="el" href="struct_c_s_l___dss_vp_lcd_op_timing_cfg.html">CSL_DssVpLcdOpTimingCfg</a> *lcdCfg)</td></tr>
+<tr class="memdesc:ga0225f72557517955d94f1a6ce815ed14"><td class="mdescLeft"> </td><td class="mdescRight">Configure the LCD Timing parameters. <a href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga0225f72557517955d94f1a6ce815ed14">More...</a><br/></td></tr>
+<tr class="separator:ga0225f72557517955d94f1a6ce815ed14"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga5f52bab6e5e9242d6f77faf995a4de6e"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga5f52bab6e5e9242d6f77faf995a4de6e">CSL_dssVpSetLcdBlankTiming</a> (<a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gaaaf231996a0d81bd23a1460d729dad23">CSL_dss_vpRegs</a> *vpRegs, const <a class="el" href="struct_c_s_l___dss_vp_lcd_blank_timing_cfg.html">CSL_DssVpLcdBlankTimingCfg</a> *blankCfg, uint32_t dvoFormat, uint32_t scanFormat, uint32_t isCustomTiming)</td></tr>
+<tr class="memdesc:ga5f52bab6e5e9242d6f77faf995a4de6e"><td class="mdescLeft"> </td><td class="mdescRight">Configure the LCD Blank Timing parameters. <a href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga5f52bab6e5e9242d6f77faf995a4de6e">More...</a><br/></td></tr>
+<tr class="separator:ga5f52bab6e5e9242d6f77faf995a4de6e"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga45dfca83a394f21328886b7ad7d89056"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga45dfca83a394f21328886b7ad7d89056">CSL_dssVpSetLcdAdvSignalConfig</a> (<a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gaaaf231996a0d81bd23a1460d729dad23">CSL_dss_vpRegs</a> *vpRegs, const <a class="el" href="struct_c_s_l___dss_vp_lcd_adv_signal_cfg.html">CSL_DssVpLcdAdvSignalCfg</a> *advSignalCfg)</td></tr>
+<tr class="memdesc:ga45dfca83a394f21328886b7ad7d89056"><td class="mdescLeft"> </td><td class="mdescRight">Configure the advance LCD Signal parameters. <a href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga45dfca83a394f21328886b7ad7d89056">More...</a><br/></td></tr>
+<tr class="separator:ga45dfca83a394f21328886b7ad7d89056"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga75453549b6c9c05da750b55cdb2a8ad3"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga75453549b6c9c05da750b55cdb2a8ad3">CSL_dssVpSetLcdSignalPolarityConfig</a> (<a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gaaaf231996a0d81bd23a1460d729dad23">CSL_dss_vpRegs</a> *vpRegs, const <a class="el" href="struct_c_s_l___dss_vp_lcd_signal_polarity_cfg.html">CSL_DssVpLcdSignalPolarityCfg</a> *polarityCfg)</td></tr>
+<tr class="memdesc:ga75453549b6c9c05da750b55cdb2a8ad3"><td class="mdescLeft"> </td><td class="mdescRight">Configure the Polarity of LCD signals(HSYNC, VSYNC, PCLK, Data) <a href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga75453549b6c9c05da750b55cdb2a8ad3">More...</a><br/></td></tr>
+<tr class="separator:ga75453549b6c9c05da750b55cdb2a8ad3"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga253c3416c174352edcda17c4ca271013"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga253c3416c174352edcda17c4ca271013">CSL_dssVpEnableTvGamma</a> (<a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gaaaf231996a0d81bd23a1460d729dad23">CSL_dss_vpRegs</a> *vpRegs, const <a class="el" href="struct_c_s_l___dss_vp_gamma_cfg.html">CSL_DssVpGammaCfg</a> *gammaCfg)</td></tr>
+<tr class="memdesc:ga253c3416c174352edcda17c4ca271013"><td class="mdescLeft"> </td><td class="mdescRight">Enable/Bypass TV Gamma Table. <a href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga253c3416c174352edcda17c4ca271013">More...</a><br/></td></tr>
+<tr class="separator:ga253c3416c174352edcda17c4ca271013"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga7d36af9cdba47ad2622758fd632980ce"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga7d36af9cdba47ad2622758fd632980ce">CSL_dssVpSetCSCCoeff</a> (<a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gaaaf231996a0d81bd23a1460d729dad23">CSL_dss_vpRegs</a> *vpRegs, const <a class="el" href="struct_c_s_l___dss_csc_coeff.html">CSL_DssCscCoeff</a> *cscCoeff, uint32_t cscPos, uint32_t cscEnable)</td></tr>
+<tr class="memdesc:ga7d36af9cdba47ad2622758fd632980ce"><td class="mdescLeft"> </td><td class="mdescRight">Configure the coefficients for Color Space Conversion. <a href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga7d36af9cdba47ad2622758fd632980ce">More...</a><br/></td></tr>
+<tr class="separator:ga7d36af9cdba47ad2622758fd632980ce"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga1bc9995f9958912a188ae2a98351aec5"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga1bc9995f9958912a188ae2a98351aec5">CSL_dssVpSetSafetySignSeedVal</a> (<a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gaaaf231996a0d81bd23a1460d729dad23">CSL_dss_vpRegs</a> *vpRegs, uint32_t signSeedVal)</td></tr>
+<tr class="memdesc:ga1bc9995f9958912a188ae2a98351aec5"><td class="mdescLeft"> </td><td class="mdescRight">Set the seed value for the signature calculation. <a href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga1bc9995f9958912a188ae2a98351aec5">More...</a><br/></td></tr>
+<tr class="separator:ga1bc9995f9958912a188ae2a98351aec5"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga20bfb7e29029c7256d6766b9b05f5f23"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga20bfb7e29029c7256d6766b9b05f5f23">CSL_dssVpSetSafetyReferenceSign</a> (<a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gaaaf231996a0d81bd23a1460d729dad23">CSL_dss_vpRegs</a> *vpRegs, uint32_t referenceSign, uint32_t regionId)</td></tr>
+<tr class="memdesc:ga20bfb7e29029c7256d6766b9b05f5f23"><td class="mdescLeft"> </td><td class="mdescRight">Set the reference safety signature for data correctness check. <a href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga20bfb7e29029c7256d6766b9b05f5f23">More...</a><br/></td></tr>
+<tr class="separator:ga20bfb7e29029c7256d6766b9b05f5f23"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gad2853dae9324aa61cbb332d14b308da6"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gad2853dae9324aa61cbb332d14b308da6">CSL_dssVpSetSafetyChkConfig</a> (<a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gaaaf231996a0d81bd23a1460d729dad23">CSL_dss_vpRegs</a> *vpRegs, const <a class="el" href="struct_c_s_l___dss_safety_chk_cfg.html">CSL_DssSafetyChkCfg</a> *safetyCfg, uint32_t regionId)</td></tr>
+<tr class="memdesc:gad2853dae9324aa61cbb332d14b308da6"><td class="mdescLeft"> </td><td class="mdescRight">Configure the Safety Check parameters. <a href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gad2853dae9324aa61cbb332d14b308da6">More...</a><br/></td></tr>
+<tr class="separator:gad2853dae9324aa61cbb332d14b308da6"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga7f7b411493687d0d758ff8b047a23712"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga7f7b411493687d0d758ff8b047a23712">CSL_dssVpGetSafetySign</a> (const <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gaaaf231996a0d81bd23a1460d729dad23">CSL_dss_vpRegs</a> *vpRegs, uint32_t regionId)</td></tr>
+<tr class="memdesc:ga7f7b411493687d0d758ff8b047a23712"><td class="mdescLeft"> </td><td class="mdescRight">Get the Safety Signature of the sub region. <a href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga7f7b411493687d0d758ff8b047a23712">More...</a><br/></td></tr>
+<tr class="separator:ga7f7b411493687d0d758ff8b047a23712"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga08a68b5de9d2c6646b0654ccad3b9600"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga08a68b5de9d2c6646b0654ccad3b9600">CSL_dssVpStallModeEnable</a> (<a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gaaaf231996a0d81bd23a1460d729dad23">CSL_dss_vpRegs</a> *vpRegs, uint32_t enable, uint32_t stallModeType)</td></tr>
+<tr class="memdesc:ga08a68b5de9d2c6646b0654ccad3b9600"><td class="mdescLeft"> </td><td class="mdescRight">Enable/disable the Video Port stall mode. <a href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga08a68b5de9d2c6646b0654ccad3b9600">More...</a><br/></td></tr>
+<tr class="separator:ga08a68b5de9d2c6646b0654ccad3b9600"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga709fdcc02c1f82d9a3b595ad67b9f086"><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga709fdcc02c1f82d9a3b595ad67b9f086">CSL_dssVpGammaCfgInit</a> (<a class="el" href="struct_c_s_l___dss_vp_gamma_cfg.html">CSL_DssVpGammaCfg</a> *gammaCfg)</td></tr>
+<tr class="memdesc:ga709fdcc02c1f82d9a3b595ad67b9f086"><td class="mdescLeft"> </td><td class="mdescRight"><a class="el" href="struct_c_s_l___dss_vp_gamma_cfg.html" title="Gamma Correction configuration for DSS Video Port Output. ">CSL_DssVpGammaCfg</a> structure init function. <a href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga709fdcc02c1f82d9a3b595ad67b9f086">More...</a><br/></td></tr>
+<tr class="separator:ga709fdcc02c1f82d9a3b595ad67b9f086"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gaf276b6af542ab92fa03bf0af6d1af1cb"><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gaf276b6af542ab92fa03bf0af6d1af1cb">CSL_dssVpLcdTdmCfgInit</a> (<a class="el" href="struct_c_s_l___dss_vp_lcd_tdm_cfg.html">CSL_DssVpLcdTdmCfg</a> *tdmCfg)</td></tr>
+<tr class="memdesc:gaf276b6af542ab92fa03bf0af6d1af1cb"><td class="mdescLeft"> </td><td class="mdescRight"><a class="el" href="struct_c_s_l___dss_vp_lcd_tdm_cfg.html" title="LCD Configuration for Time Division Multiplexing. ">CSL_DssVpLcdTdmCfg</a> structure init function. <a href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gaf276b6af542ab92fa03bf0af6d1af1cb">More...</a><br/></td></tr>
+<tr class="separator:gaf276b6af542ab92fa03bf0af6d1af1cb"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga158b9aed148e3a14e1bff1cb8613bc67"><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga158b9aed148e3a14e1bff1cb8613bc67">CSL_dssVpLcdSignalPolarityCfgInit</a> (<a class="el" href="struct_c_s_l___dss_vp_lcd_signal_polarity_cfg.html">CSL_DssVpLcdSignalPolarityCfg</a> *polarityCfg)</td></tr>
+<tr class="memdesc:ga158b9aed148e3a14e1bff1cb8613bc67"><td class="mdescLeft"> </td><td class="mdescRight"><a class="el" href="struct_c_s_l___dss_vp_lcd_signal_polarity_cfg.html" title="Polarity of Active Video, Pixel Clock, HSync and VSync signals for the LCD. ">CSL_DssVpLcdSignalPolarityCfg</a> structure init function. <a href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga158b9aed148e3a14e1bff1cb8613bc67">More...</a><br/></td></tr>
+<tr class="separator:ga158b9aed148e3a14e1bff1cb8613bc67"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga50f5efd31f31736019ee265e3078d4ef"><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga50f5efd31f31736019ee265e3078d4ef">CSL_dssVpLcdAdvSignalCfgInit</a> (<a class="el" href="struct_c_s_l___dss_vp_lcd_adv_signal_cfg.html">CSL_DssVpLcdAdvSignalCfg</a> *advSignalCfg)</td></tr>
+<tr class="memdesc:ga50f5efd31f31736019ee265e3078d4ef"><td class="mdescLeft"> </td><td class="mdescRight"><a class="el" href="struct_c_s_l___dss_vp_lcd_adv_signal_cfg.html" title="Advance Signal Configuration for the LCD. ">CSL_DssVpLcdAdvSignalCfg</a> structure init function. <a href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga50f5efd31f31736019ee265e3078d4ef">More...</a><br/></td></tr>
+<tr class="separator:ga50f5efd31f31736019ee265e3078d4ef"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga2be9daed03e91c1706a4075be86a7054"><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga2be9daed03e91c1706a4075be86a7054">CSL_dssVpLcdOpTimingCfgInit</a> (<a class="el" href="struct_c_s_l___dss_vp_lcd_op_timing_cfg.html">CSL_DssVpLcdOpTimingCfg</a> *lcdCfg)</td></tr>
+<tr class="memdesc:ga2be9daed03e91c1706a4075be86a7054"><td class="mdescLeft"> </td><td class="mdescRight"><a class="el" href="struct_c_s_l___dss_vp_lcd_op_timing_cfg.html" title="Timing configuration for the LCD output. ">CSL_DssVpLcdOpTimingCfg</a> structure init function. <a href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga2be9daed03e91c1706a4075be86a7054">More...</a><br/></td></tr>
+<tr class="separator:ga2be9daed03e91c1706a4075be86a7054"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gadd1a815002453481cce4f9dbf8da864a"><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gadd1a815002453481cce4f9dbf8da864a">CSL_dssVpLcdBlankTimingCfgInit</a> (<a class="el" href="struct_c_s_l___dss_vp_lcd_blank_timing_cfg.html">CSL_DssVpLcdBlankTimingCfg</a> *blankCfg)</td></tr>
+<tr class="memdesc:gadd1a815002453481cce4f9dbf8da864a"><td class="mdescLeft"> </td><td class="mdescRight"><a class="el" href="struct_c_s_l___dss_vp_lcd_blank_timing_cfg.html" title="Blanking Timing parameters for the LCD. ">CSL_DssVpLcdBlankTimingCfg</a> structure init function. <a href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gadd1a815002453481cce4f9dbf8da864a">More...</a><br/></td></tr>
+<tr class="separator:gadd1a815002453481cce4f9dbf8da864a"><td class="memSeparator" colspan="2"> </td></tr>
+</table>
+<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
+<div class="textblock"><p>DSS Video Port CSL FL interface file. </p>
+</div></div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/csl__fvid2__data_types_8h.html b/packages/ti/drv/dss/docs/doxygen/html/csl__fvid2__data_types_8h.html
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+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
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+<title>csl_fvid2_dataTypes.h File Reference</title>
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+<li class="navelem"><a class="el" href="dir_f5943f6d28c724c9867ac930658f5901.html">csl</a></li> </ul>
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+<a href="#nested-classes">Data Structures</a> |
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+<a href="#func-members">Functions</a> </div>
+ <div class="headertitle">
+<div class="title">csl_fvid2_dataTypes.h File Reference</div> </div>
+</div><!--header-->
+<div class="contents">
+
+<p>CSL FVID2 Datatypes.
+<a href="#details">More...</a></p>
+<div class="textblock"><code>#include <ti/csl/tistdtypes.h></code><br/>
+</div><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="nested-classes"></a>
+Data Structures</h2></td></tr>
+<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_fvid2___format.html">Fvid2_Format</a></td></tr>
+<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">FVID2 video buffer format specification. <a href="struct_fvid2___format.html#details">More...</a><br/></td></tr>
+<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_fvid2___sub_frame_info.html">Fvid2_SubFrameInfo</a></td></tr>
+<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">Sub-Frame information. <a href="struct_fvid2___sub_frame_info.html#details">More...</a><br/></td></tr>
+<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_fvid2___frame.html">Fvid2_Frame</a></td></tr>
+<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">FVID2 frame buffer structure. <a href="struct_fvid2___frame.html#details">More...</a><br/></td></tr>
+<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_fvid2___frame_list.html">Fvid2_FrameList</a></td></tr>
+<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">FVID2 frame buffer list used to exchange multiple FVID2 frames in a single driver call. <a href="struct_fvid2___frame_list.html#details">More...</a><br/></td></tr>
+<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_fvid2___mode_info.html">Fvid2_ModeInfo</a></td></tr>
+<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">FVID2 Mode information structure. <a href="struct_fvid2___mode_info.html#details">More...</a><br/></td></tr>
+<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_fvid2___crop_config.html">Fvid2_CropConfig</a></td></tr>
+<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">Structure containing crop configuration - used in Scaler and VCOMP. <a href="struct_fvid2___crop_config.html#details">More...</a><br/></td></tr>
+<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_fvid2___pos_config.html">Fvid2_PosConfig</a></td></tr>
+<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">Structure containing position configuration - used in VCOMP and CIG. <a href="struct_fvid2___pos_config.html#details">More...</a><br/></td></tr>
+<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_fvid2___size_config.html">Fvid2_SizeConfig</a></td></tr>
+<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">Structure containing size configuration. <a href="struct_fvid2___size_config.html#details">More...</a><br/></td></tr>
+<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
+Macros</h2></td></tr>
+<tr class="memitem:a88e886eb47cb269040fb5bc7fda3f82c"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a88e886eb47cb269040fb5bc7fda3f82c"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a88e886eb47cb269040fb5bc7fda3f82c">FVID2_TIMEOUT_NONE</a>   (0U)</td></tr>
+<tr class="memdesc:a88e886eb47cb269040fb5bc7fda3f82c"><td class="mdescLeft"> </td><td class="mdescRight">No Timeout. <br/></td></tr>
+<tr class="separator:a88e886eb47cb269040fb5bc7fda3f82c"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ac39a381aee86801c727735f635719cef"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ac39a381aee86801c727735f635719cef"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#ac39a381aee86801c727735f635719cef">FVID2_TIMEOUT_FOREVER</a>   (~((uint32_t) 0U))</td></tr>
+<tr class="memdesc:ac39a381aee86801c727735f635719cef"><td class="mdescLeft"> </td><td class="mdescRight">Timeout wait forever. <br/></td></tr>
+<tr class="separator:ac39a381aee86801c727735f635719cef"><td class="memSeparator" colspan="2"> </td></tr>
+<tr><td colspan="2"><div class="groupHeader">FVID2 Error Codes</div></td></tr>
+<tr><td colspan="2"><div class="groupText"><p>Error codes returned by FVID2 APIs </p>
+</div></td></tr>
+<tr class="memitem:a8395476cbd9d01e0aaa219814515d5c9"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a8395476cbd9d01e0aaa219814515d5c9"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a8395476cbd9d01e0aaa219814515d5c9">FVID2_SOK</a>   ((int32_t) 0)</td></tr>
+<tr class="memdesc:a8395476cbd9d01e0aaa219814515d5c9"><td class="mdescLeft"> </td><td class="mdescRight">FVID2 API call successful. <br/></td></tr>
+<tr class="separator:a8395476cbd9d01e0aaa219814515d5c9"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:acb9d973050d110982065b52b0e6b364b"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="acb9d973050d110982065b52b0e6b364b"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#acb9d973050d110982065b52b0e6b364b">FVID2_EFAIL</a>   (-(int32_t) 1)</td></tr>
+<tr class="memdesc:acb9d973050d110982065b52b0e6b364b"><td class="mdescLeft"> </td><td class="mdescRight">FVID2 API call returned with error as failed. Used for generic error. It may be some hardware failure and/or software failure. <br/></td></tr>
+<tr class="separator:acb9d973050d110982065b52b0e6b364b"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a885f0ef7c82a7d48a4b8c9331061d59d"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a885f0ef7c82a7d48a4b8c9331061d59d"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a885f0ef7c82a7d48a4b8c9331061d59d">FVID2_EBADARGS</a>   (-(int32_t) 2)</td></tr>
+<tr class="memdesc:a885f0ef7c82a7d48a4b8c9331061d59d"><td class="mdescLeft"> </td><td class="mdescRight">FVID2 API call returned with error as bad arguments. Typically, NULL pointer passed to the FVID2 API where its not expected. <br/></td></tr>
+<tr class="separator:a885f0ef7c82a7d48a4b8c9331061d59d"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a45bbc830a10292026a3a520024180c4e"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a45bbc830a10292026a3a520024180c4e"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a45bbc830a10292026a3a520024180c4e">FVID2_EINVALID_PARAMS</a>   (-(int32_t) 3)</td></tr>
+<tr class="memdesc:a45bbc830a10292026a3a520024180c4e"><td class="mdescLeft"> </td><td class="mdescRight">FVID2 API call returned with error as invalid parameters. Typically when parameters passed are not valid or out of range. <br/></td></tr>
+<tr class="separator:a45bbc830a10292026a3a520024180c4e"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ac7f5a0ff683c19787dd7bba1b3df9d2d"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ac7f5a0ff683c19787dd7bba1b3df9d2d"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#ac7f5a0ff683c19787dd7bba1b3df9d2d">FVID2_EDEVICE_INUSE</a>   (-(int32_t) 4)</td></tr>
+<tr class="memdesc:ac7f5a0ff683c19787dd7bba1b3df9d2d"><td class="mdescLeft"> </td><td class="mdescRight">FVID2 API call returned with error as device already in use. Example, tried to open the driver maximum + 1 times. Display and Capture driver supports single open only, while M2M driver supports multiple open. <br/></td></tr>
+<tr class="separator:ac7f5a0ff683c19787dd7bba1b3df9d2d"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a5eed0289096959f2b2584734326fcb0b"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a5eed0289096959f2b2584734326fcb0b"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a5eed0289096959f2b2584734326fcb0b">FVID2_ETIMEOUT</a>   (-(int32_t) 5)</td></tr>
+<tr class="memdesc:a5eed0289096959f2b2584734326fcb0b"><td class="mdescLeft"> </td><td class="mdescRight">FVID2 API call returned with error as timed out. Typically API is waiting for some condition and returned as condition not happened in the timeout period. <br/></td></tr>
+<tr class="separator:a5eed0289096959f2b2584734326fcb0b"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a9b874ab5f96bd5a7c6e020088028cd40"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a9b874ab5f96bd5a7c6e020088028cd40"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a9b874ab5f96bd5a7c6e020088028cd40">FVID2_EALLOC</a>   (-(int32_t) 6)</td></tr>
+<tr class="memdesc:a9b874ab5f96bd5a7c6e020088028cd40"><td class="mdescLeft"> </td><td class="mdescRight">FVID2 API call returned with error as allocation failure. Typically memory or resource allocation failure. <br/></td></tr>
+<tr class="separator:a9b874ab5f96bd5a7c6e020088028cd40"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a55f2570c77c466749bb58a73bec2ff8f"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a55f2570c77c466749bb58a73bec2ff8f"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a55f2570c77c466749bb58a73bec2ff8f">FVID2_EOUT_OF_RANGE</a>   (-(int32_t) 7)</td></tr>
+<tr class="memdesc:a55f2570c77c466749bb58a73bec2ff8f"><td class="mdescLeft"> </td><td class="mdescRight">FVID2 API call returned with error as out of range. Typically when API is called with some argument that is out of range for that API like array index etc. <br/></td></tr>
+<tr class="separator:a55f2570c77c466749bb58a73bec2ff8f"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ae64399f94932c999861f44619d747893"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ae64399f94932c999861f44619d747893"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#ae64399f94932c999861f44619d747893">FVID2_EAGAIN</a>   (-(int32_t) 8)</td></tr>
+<tr class="memdesc:ae64399f94932c999861f44619d747893"><td class="mdescLeft"> </td><td class="mdescRight">FVID2 API call returned with error as try again. Momentarily API is not able to service request because of queue full or any other temporary reason. <br/></td></tr>
+<tr class="separator:ae64399f94932c999861f44619d747893"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a3d1ed7fccba01dcd0fbd32517ce547f2"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a3d1ed7fccba01dcd0fbd32517ce547f2"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a3d1ed7fccba01dcd0fbd32517ce547f2">FVID2_EUNSUPPORTED_CMD</a>   (-(int32_t) 9)</td></tr>
+<tr class="memdesc:a3d1ed7fccba01dcd0fbd32517ce547f2"><td class="mdescLeft"> </td><td class="mdescRight">FVID2 API call returned with unsupported command. Typically when command is not supported by control API. <br/></td></tr>
+<tr class="separator:a3d1ed7fccba01dcd0fbd32517ce547f2"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:af7b2f760851f8a9643a455628ad1f8bb"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="af7b2f760851f8a9643a455628ad1f8bb"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#af7b2f760851f8a9643a455628ad1f8bb">FVID2_ENO_MORE_BUFFERS</a>   (-(int32_t) 10)</td></tr>
+<tr class="memdesc:af7b2f760851f8a9643a455628ad1f8bb"><td class="mdescLeft"> </td><td class="mdescRight">FVID2 API call returned with error as no more buffers available. Typically when no buffers are available. <br/></td></tr>
+<tr class="separator:af7b2f760851f8a9643a455628ad1f8bb"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a7ca3b42172e03868ca9d87b34524cb8d"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a7ca3b42172e03868ca9d87b34524cb8d"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a7ca3b42172e03868ca9d87b34524cb8d">FVID2_EUNSUPPORTED_OPS</a>   (-(int32_t) 11)</td></tr>
+<tr class="memdesc:a7ca3b42172e03868ca9d87b34524cb8d"><td class="mdescLeft"> </td><td class="mdescRight">FVID2 API call returned with error as unsupported operation. Typically when the specific operation is not supported by that API such as IOCTL not supporting some specific functions. <br/></td></tr>
+<tr class="separator:a7ca3b42172e03868ca9d87b34524cb8d"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a15e3b6063db48b059651aa4056acb482"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a15e3b6063db48b059651aa4056acb482"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a15e3b6063db48b059651aa4056acb482">FVID2_EDRIVER_INUSE</a>   (-(int32_t) 12)</td></tr>
+<tr class="memdesc:a15e3b6063db48b059651aa4056acb482"><td class="mdescLeft"> </td><td class="mdescRight">FVID2 API call returned with error as driver already in use. <br/></td></tr>
+<tr class="separator:a15e3b6063db48b059651aa4056acb482"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:aedcb86d5a2e3ec73847eca004e037535"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aedcb86d5a2e3ec73847eca004e037535"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#aedcb86d5a2e3ec73847eca004e037535">FVID2_WNON_RECOMMENDED_PARAMS</a>   (-(int32_t) 13)</td></tr>
+<tr class="memdesc:aedcb86d5a2e3ec73847eca004e037535"><td class="mdescLeft"> </td><td class="mdescRight">FVID2 API call returned with warning for non-recommended parameter settings sent by application. Application may choose to ignore this. <br/></td></tr>
+<tr class="separator:aedcb86d5a2e3ec73847eca004e037535"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a947146551dd317bd5a6923633ab663b1"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a947146551dd317bd5a6923633ab663b1"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a947146551dd317bd5a6923633ab663b1">FVID2_ENO_DEVICE</a>   (-(int32_t) 14)</td></tr>
+<tr class="memdesc:a947146551dd317bd5a6923633ab663b1"><td class="mdescLeft"> </td><td class="mdescRight">FVID2 API call returned with error as no device present for the given command and API. <br/></td></tr>
+<tr class="separator:a947146551dd317bd5a6923633ab663b1"><td class="memSeparator" colspan="2"> </td></tr>
+<tr><td colspan="2"><div class="groupHeader">FVID2 Max limits</div></td></tr>
+<tr class="memitem:adcf85da7b48cf6db3cce2efb2d86c92f"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="adcf85da7b48cf6db3cce2efb2d86c92f"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#adcf85da7b48cf6db3cce2efb2d86c92f">FVID2_MAX_FRAME_PTR</a>   (64U)</td></tr>
+<tr class="memdesc:adcf85da7b48cf6db3cce2efb2d86c92f"><td class="mdescLeft"> </td><td class="mdescRight">This macro determines the maximum number of FVID2 frame pointers that can be passed per frame list. <br/></td></tr>
+<tr class="separator:adcf85da7b48cf6db3cce2efb2d86c92f"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a6fc0d1953df344af3840c1fa516ec270"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a6fc0d1953df344af3840c1fa516ec270"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a6fc0d1953df344af3840c1fa516ec270">FVID2_MAX_FIELDS</a>   (2U)</td></tr>
+<tr class="memdesc:a6fc0d1953df344af3840c1fa516ec270"><td class="mdescLeft"> </td><td class="mdescRight">Number of fields - top and bottom. Used for allocating address pointers for both the fields. <br/></td></tr>
+<tr class="separator:a6fc0d1953df344af3840c1fa516ec270"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a19b6ef6e426b64e15bc08ce46c644aef"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a19b6ef6e426b64e15bc08ce46c644aef"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a19b6ef6e426b64e15bc08ce46c644aef">FVID2_MAX_PLANES_PER_FIELD</a>   (3U)</td></tr>
+<tr class="memdesc:a19b6ef6e426b64e15bc08ce46c644aef"><td class="mdescLeft"> </td><td class="mdescRight">This macro determines the maximum number of planes/address used to represent a video buffer per field. Currently this is set to 3 to support the maximum pointers required for YUV/RGB planar format - Y, Cb and Cr or R, G and B. <br/></td></tr>
+<tr class="separator:a19b6ef6e426b64e15bc08ce46c644aef"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:aef0d63f7f96514278ebda30f1c0bec74"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#aef0d63f7f96514278ebda30f1c0bec74">FVID2_MAX_PLANES</a></td></tr>
+<tr class="memdesc:aef0d63f7f96514278ebda30f1c0bec74"><td class="mdescLeft"> </td><td class="mdescRight">This macro determines the maximum number of planes/address used to represent a video buffer. Currently this is set to 6 to support the maximum pointers required for two fields of YUV/RGB planar format - Y, Cb and Cr or R, G and B. <a href="#aef0d63f7f96514278ebda30f1c0bec74">More...</a><br/></td></tr>
+<tr class="separator:aef0d63f7f96514278ebda30f1c0bec74"><td class="memSeparator" colspan="2"> </td></tr>
+<tr><td colspan="2"><div class="groupHeader">FVID2 Frame Address Index</div></td></tr>
+<tr><td colspan="2"><div class="groupText"><p><a class="el" href="struct_fvid2___frame.html#ad9e33643cd628e7432da408ad6565305">Fvid2_Frame.addr</a> structure is array of pointers. The below indices are used to identify the correct buffer address corresponding to the field and buffer formats. </p>
+</div></td></tr>
+<tr class="memitem:a9ff732b464eedfe4640b4169970765c8"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a9ff732b464eedfe4640b4169970765c8"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a9ff732b464eedfe4640b4169970765c8">FVID2_YUV_PL_Y_ADDR_IDX</a>   (0U)</td></tr>
+<tr class="memdesc:a9ff732b464eedfe4640b4169970765c8"><td class="mdescLeft"> </td><td class="mdescRight">Y Index for YUV444/YUV422/YUV420 planar formats. <br/></td></tr>
+<tr class="separator:a9ff732b464eedfe4640b4169970765c8"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ada7ebea730d1889e88c13b17c5b2d053"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ada7ebea730d1889e88c13b17c5b2d053"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#ada7ebea730d1889e88c13b17c5b2d053">FVID2_YUV_PL_CB_ADDR_IDX</a>   (1U)</td></tr>
+<tr class="memdesc:ada7ebea730d1889e88c13b17c5b2d053"><td class="mdescLeft"> </td><td class="mdescRight">CB Index for YUV444/YUV422/YUV420 planar formats. <br/></td></tr>
+<tr class="separator:ada7ebea730d1889e88c13b17c5b2d053"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a0bbd3a8627de6776fc92458a8b3c6a4a"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a0bbd3a8627de6776fc92458a8b3c6a4a"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a0bbd3a8627de6776fc92458a8b3c6a4a">FVID2_YUV_PL_CR_ADDR_IDX</a>   (2U)</td></tr>
+<tr class="memdesc:a0bbd3a8627de6776fc92458a8b3c6a4a"><td class="mdescLeft"> </td><td class="mdescRight">CR Index for YUV444/YUV422/YUV420 planar formats. <br/></td></tr>
+<tr class="separator:a0bbd3a8627de6776fc92458a8b3c6a4a"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a9a79f5ef34a964258855d87b738cc19f"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a9a79f5ef34a964258855d87b738cc19f"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a9a79f5ef34a964258855d87b738cc19f">FVID2_YUV_SP_Y_ADDR_IDX</a>   (0U)</td></tr>
+<tr class="memdesc:a9a79f5ef34a964258855d87b738cc19f"><td class="mdescLeft"> </td><td class="mdescRight">Y Index for YUV semi planar formats. <br/></td></tr>
+<tr class="separator:a9a79f5ef34a964258855d87b738cc19f"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a12c8a4aa7624a1d6e007cb29331f1119"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a12c8a4aa7624a1d6e007cb29331f1119"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a12c8a4aa7624a1d6e007cb29331f1119">FVID2_YUV_SP_CBCR_ADDR_IDX</a>   (1U)</td></tr>
+<tr class="memdesc:a12c8a4aa7624a1d6e007cb29331f1119"><td class="mdescLeft"> </td><td class="mdescRight">CB Index for semi planar formats. <br/></td></tr>
+<tr class="separator:a12c8a4aa7624a1d6e007cb29331f1119"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:aa817e06beb7398bb897b0ca37fd65c89"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aa817e06beb7398bb897b0ca37fd65c89"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#aa817e06beb7398bb897b0ca37fd65c89">FVID2_RGB_ADDR_IDX</a>   (0U)</td></tr>
+<tr class="memdesc:aa817e06beb7398bb897b0ca37fd65c89"><td class="mdescLeft"> </td><td class="mdescRight">Index for RGB888/RGB565/ARGB32 formats. <br/></td></tr>
+<tr class="separator:aa817e06beb7398bb897b0ca37fd65c89"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a964627052348693970b6b8078a622a11"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a964627052348693970b6b8078a622a11"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a964627052348693970b6b8078a622a11">FVID2_YUV_INT_ADDR_IDX</a>   (0U)</td></tr>
+<tr class="memdesc:a964627052348693970b6b8078a622a11"><td class="mdescLeft"> </td><td class="mdescRight">Index for YUV444/YUV422 interleaved formats. <br/></td></tr>
+<tr class="separator:a964627052348693970b6b8078a622a11"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a16d75a000e95e205d6ef10eb5a6a7005"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a16d75a000e95e205d6ef10eb5a6a7005"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a16d75a000e95e205d6ef10eb5a6a7005">FVID2_YUV_PL_Y_FID2_ADDR_IDX</a>   (<a class="el" href="csl__fvid2__data_types_8h.html#a9ff732b464eedfe4640b4169970765c8">FVID2_YUV_PL_Y_ADDR_IDX</a> + 3U)</td></tr>
+<tr class="memdesc:a16d75a000e95e205d6ef10eb5a6a7005"><td class="mdescLeft"> </td><td class="mdescRight">Y Index for YUV444/YUV422/YUV420 planar formats for field 2. <br/></td></tr>
+<tr class="separator:a16d75a000e95e205d6ef10eb5a6a7005"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a8af505377d5f361ec078e9181336d42e"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a8af505377d5f361ec078e9181336d42e"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a8af505377d5f361ec078e9181336d42e">FVID2_YUV_PL_CB_FID2_ADDR_IDX</a>   (<a class="el" href="csl__fvid2__data_types_8h.html#ada7ebea730d1889e88c13b17c5b2d053">FVID2_YUV_PL_CB_ADDR_IDX</a> + 3U)</td></tr>
+<tr class="memdesc:a8af505377d5f361ec078e9181336d42e"><td class="mdescLeft"> </td><td class="mdescRight">CB Index for YUV444/YUV422/YUV420 planar formats for field 2. <br/></td></tr>
+<tr class="separator:a8af505377d5f361ec078e9181336d42e"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a74bcea671e6e8833edbd978fd0dd27be"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a74bcea671e6e8833edbd978fd0dd27be"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a74bcea671e6e8833edbd978fd0dd27be">FVID2_YUV_PL_CR_FID2_ADDR_IDX</a>   (<a class="el" href="csl__fvid2__data_types_8h.html#a0bbd3a8627de6776fc92458a8b3c6a4a">FVID2_YUV_PL_CR_ADDR_IDX</a> + 3U)</td></tr>
+<tr class="memdesc:a74bcea671e6e8833edbd978fd0dd27be"><td class="mdescLeft"> </td><td class="mdescRight">CR Index for YUV444/YUV422/YUV420 planar formats for field 2. <br/></td></tr>
+<tr class="separator:a74bcea671e6e8833edbd978fd0dd27be"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:acebcf1dfbbc29d3e139e95b4f4c5ed6d"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="acebcf1dfbbc29d3e139e95b4f4c5ed6d"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#acebcf1dfbbc29d3e139e95b4f4c5ed6d">FVID2_YUV_SP_Y_FID2_ADDR_IDX</a>   (<a class="el" href="csl__fvid2__data_types_8h.html#a9a79f5ef34a964258855d87b738cc19f">FVID2_YUV_SP_Y_ADDR_IDX</a> + 3U)</td></tr>
+<tr class="memdesc:acebcf1dfbbc29d3e139e95b4f4c5ed6d"><td class="mdescLeft"> </td><td class="mdescRight">Y Index for YUV semi planar formats for field 2. <br/></td></tr>
+<tr class="separator:acebcf1dfbbc29d3e139e95b4f4c5ed6d"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a32797001f230161fdd9b1a26755061ee"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a32797001f230161fdd9b1a26755061ee"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a32797001f230161fdd9b1a26755061ee">FVID2_YUV_SP_CBCR_FID2_ADDR_IDX</a>   (<a class="el" href="csl__fvid2__data_types_8h.html#a12c8a4aa7624a1d6e007cb29331f1119">FVID2_YUV_SP_CBCR_ADDR_IDX</a> + 3U)</td></tr>
+<tr class="memdesc:a32797001f230161fdd9b1a26755061ee"><td class="mdescLeft"> </td><td class="mdescRight">CB Index for semi planar formats for field 2. <br/></td></tr>
+<tr class="separator:a32797001f230161fdd9b1a26755061ee"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a31e867f5964f35c3554a204beb07601e"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a31e867f5964f35c3554a204beb07601e"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a31e867f5964f35c3554a204beb07601e">FVID2_RGB_FID2_ADDR_IDX</a>   (<a class="el" href="csl__fvid2__data_types_8h.html#aa817e06beb7398bb897b0ca37fd65c89">FVID2_RGB_ADDR_IDX</a> + 3U)</td></tr>
+<tr class="memdesc:a31e867f5964f35c3554a204beb07601e"><td class="mdescLeft"> </td><td class="mdescRight">Index for RGB888/RGB565/ARGB32 formats for field 2. <br/></td></tr>
+<tr class="separator:a31e867f5964f35c3554a204beb07601e"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a909f592eabc1bf70b9a3dab15e468713"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a909f592eabc1bf70b9a3dab15e468713"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a909f592eabc1bf70b9a3dab15e468713">FVID2_YUV_INT_FID2_ADDR_IDX</a>   (<a class="el" href="csl__fvid2__data_types_8h.html#a964627052348693970b6b8078a622a11">FVID2_YUV_INT_ADDR_IDX</a> + 3U)</td></tr>
+<tr class="memdesc:a909f592eabc1bf70b9a3dab15e468713"><td class="mdescLeft"> </td><td class="mdescRight">Index for YUV444/YUV422 interleaved formats for field 2. <br/></td></tr>
+<tr class="separator:a909f592eabc1bf70b9a3dab15e468713"><td class="memSeparator" colspan="2"> </td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="enum-members"></a>
+Enumerations</h2></td></tr>
+<tr class="memitem:a4e1d4b630095a3e5f9d560b839603a8e"><td class="memItemLeft" align="right" valign="top">enum  </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a4e1d4b630095a3e5f9d560b839603a8e">Fvid2_VideoIfMode</a> { <br/>
+  <a class="el" href="csl__fvid2__data_types_8h.html#a4e1d4b630095a3e5f9d560b839603a8ea0c1ebff799492bc87e0947ea5b4af1e6">FVID2_VIFM_SCH_ES</a> = 0,
+<a class="el" href="csl__fvid2__data_types_8h.html#a4e1d4b630095a3e5f9d560b839603a8ea7e22126a15add08aeabce4216492c88b">FVID2_VIFM_MCH_LINE_MUX_ES</a>,
+<a class="el" href="csl__fvid2__data_types_8h.html#a4e1d4b630095a3e5f9d560b839603a8ea07b6e18e02112c367d6bd3b380d2d9d3">FVID2_VIFM_MCH_PIXEL_MUX_ES</a>,
+<a class="el" href="csl__fvid2__data_types_8h.html#a4e1d4b630095a3e5f9d560b839603a8ea7ffc6821187a28919e2ee5f8723199b1">FVID2_VIFM_SCH_DS_HSYNC_VBLK</a>,
+<br/>
+  <a class="el" href="csl__fvid2__data_types_8h.html#a4e1d4b630095a3e5f9d560b839603a8ea41dea0d5f63dd2ea51de8030460f6527">FVID2_VIFM_SCH_DS_HSYNC_VSYNC</a>,
+<a class="el" href="csl__fvid2__data_types_8h.html#a4e1d4b630095a3e5f9d560b839603a8ea2fa8c574decaca5d94b93a6c8aa2ae64">FVID2_VIFM_SCH_DS_AVID_VBLK</a>,
+<a class="el" href="csl__fvid2__data_types_8h.html#a4e1d4b630095a3e5f9d560b839603a8ea901482ffa323be1fb48302f7404930a6">FVID2_VIFM_SCH_DS_AVID_VSYNC</a>,
+<a class="el" href="csl__fvid2__data_types_8h.html#a4e1d4b630095a3e5f9d560b839603a8eac7aceedd75323567a399f68742d54ccb">FVID2_VIFM_MCH_LINE_MUX_SPLIT_LINE_ES</a>,
+<br/>
+  <a class="el" href="csl__fvid2__data_types_8h.html#a4e1d4b630095a3e5f9d560b839603a8ea0caef0a1234afe67eed22370729d04f8">FVID2_VIFM_SCH_CSI2</a>,
+<a class="el" href="csl__fvid2__data_types_8h.html#a4e1d4b630095a3e5f9d560b839603a8ea83e693e66bda0561fb9c4cc81733fa87">FVID2_VIFM_SCH_LVDS</a>,
+<a class="el" href="csl__fvid2__data_types_8h.html#a4e1d4b630095a3e5f9d560b839603a8ea03c1d8ab4e4325886e9c8553f0c6708f">FVID2_VIFM_SCH_CPI</a>,
+<a class="el" href="csl__fvid2__data_types_8h.html#a4e1d4b630095a3e5f9d560b839603a8ea06e8f99dd0b137efcc6ca8e2e2f15527">FVID2_VIFM_MAX</a>
+<br/>
+ }</td></tr>
+<tr class="memdesc:a4e1d4b630095a3e5f9d560b839603a8e"><td class="mdescLeft"> </td><td class="mdescRight">Video interface mode. <a href="csl__fvid2__data_types_8h.html#a4e1d4b630095a3e5f9d560b839603a8e">More...</a><br/></td></tr>
+<tr class="separator:a4e1d4b630095a3e5f9d560b839603a8e"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a6372ae9694a790a94e2da8e06d76b540"><td class="memItemLeft" align="right" valign="top">enum  </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a6372ae9694a790a94e2da8e06d76b540">Fvid2_ChromaPos</a> { <a class="el" href="csl__fvid2__data_types_8h.html#a6372ae9694a790a94e2da8e06d76b540a2d0e94bc80160340b9f3ea5ef2df480a">FVID2_CHROMA_POS_COSITED</a>,
+<a class="el" href="csl__fvid2__data_types_8h.html#a6372ae9694a790a94e2da8e06d76b540a354971423ce04887bfb431e05790568c">FVID2_CHROMA_POS_CENTERED</a>
+ }</td></tr>
+<tr class="memdesc:a6372ae9694a790a94e2da8e06d76b540"><td class="mdescLeft"> </td><td class="mdescRight">Enum for selecting chroma position in chroma up or down sampler. <a href="csl__fvid2__data_types_8h.html#a6372ae9694a790a94e2da8e06d76b540">More...</a><br/></td></tr>
+<tr class="separator:a6372ae9694a790a94e2da8e06d76b540"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ac5d9776b0da6459f3f9cfbcbce8eec18"><td class="memItemLeft" align="right" valign="top">enum  </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#ac5d9776b0da6459f3f9cfbcbce8eec18">Fvid2_BayerColorComp</a> { <br/>
+  <a class="el" href="csl__fvid2__data_types_8h.html#ac5d9776b0da6459f3f9cfbcbce8eec18ae8725e59cc3be75abc7b2211be865db3">FVID2_BAYER_COLOR_COMP_R</a>,
+<a class="el" href="csl__fvid2__data_types_8h.html#ac5d9776b0da6459f3f9cfbcbce8eec18a8a20bb44d83f09c3216382a281468f10">FVID2_BAYER_COLOR_COMP_GR</a>,
+<a class="el" href="csl__fvid2__data_types_8h.html#ac5d9776b0da6459f3f9cfbcbce8eec18af8760d6393d606fa75b0948835d026f8">FVID2_BAYER_COLOR_COMP_GB</a>,
+<a class="el" href="csl__fvid2__data_types_8h.html#ac5d9776b0da6459f3f9cfbcbce8eec18aab7a458ffc41a81da35d21b7160745d0">FVID2_BAYER_COLOR_COMP_B</a>,
+<br/>
+  <a class="el" href="csl__fvid2__data_types_8h.html#ac5d9776b0da6459f3f9cfbcbce8eec18ae4b13df43936976b20342bcfe77957a3">FVID2_BAYER_COLOR_COMP_MAX</a>
+<br/>
+ }</td></tr>
+<tr class="memdesc:ac5d9776b0da6459f3f9cfbcbce8eec18"><td class="mdescLeft"> </td><td class="mdescRight">Enum for selecting bayer color components for odd/even pixel position on odd/even lines, Also used for specifying gain and offset in White balance config for each color component. <a href="csl__fvid2__data_types_8h.html#ac5d9776b0da6459f3f9cfbcbce8eec18">More...</a><br/></td></tr>
+<tr class="separator:ac5d9776b0da6459f3f9cfbcbce8eec18"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a248e190fab40aca929969c432068a099"><td class="memItemLeft" align="right" valign="top">enum  </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a248e190fab40aca929969c432068a099">Fvid2_FrameStatus</a> { <br/>
+  <a class="el" href="csl__fvid2__data_types_8h.html#a248e190fab40aca929969c432068a099adf9e647770fecfbd9ace849d2db8f988">FVID2_FRAME_STATUS_INIT</a> = 0,
+<a class="el" href="csl__fvid2__data_types_8h.html#a248e190fab40aca929969c432068a099a696c6a4cbd00246b5c1e4370fa302055">FVID2_FRAME_STATUS_COMPLETED</a>,
+<a class="el" href="csl__fvid2__data_types_8h.html#a248e190fab40aca929969c432068a099aeefebb0a00827e6d2362df182c6e0709">FVID2_FRAME_STATUS_PENDING</a>,
+<a class="el" href="csl__fvid2__data_types_8h.html#a248e190fab40aca929969c432068a099afb0044f14c3f1d87d92611b1b13c3a02">FVID2_FRAME_STATUS_SUBMITTED</a>,
+<br/>
+  <a class="el" href="csl__fvid2__data_types_8h.html#a248e190fab40aca929969c432068a099ac9611a6508b8e02547b4706cc38ad89d">FVID2_FRAME_STATUS_ERROR</a>,
+<a class="el" href="csl__fvid2__data_types_8h.html#a248e190fab40aca929969c432068a099a43d4d377646d7279138602a7aeac3f72">FVID2_FRAME_STATUS_ABORTED</a>,
+<a class="el" href="csl__fvid2__data_types_8h.html#a248e190fab40aca929969c432068a099abebee14dd307042e25082acf1b1270f5">FVID2_FRAME_STATUS_OVERFLOW</a>,
+<a class="el" href="csl__fvid2__data_types_8h.html#a248e190fab40aca929969c432068a099a475443372b2fb2763923f7d58b5f467a">FVID2_FRAME_STATUS_ECC_CORRECTED</a>,
+<br/>
+  <a class="el" href="csl__fvid2__data_types_8h.html#a248e190fab40aca929969c432068a099a84c41401ba6a29d9ca60b93a48803202">FVID2_FRAME_STATUS_CRC_ERROR</a>,
+<a class="el" href="csl__fvid2__data_types_8h.html#a248e190fab40aca929969c432068a099a38f88ca4ff3a06f88914c71a5c1b7c0e">FVID2_FRAME_STATUS_ECC_ERROR</a>,
+<a class="el" href="csl__fvid2__data_types_8h.html#a248e190fab40aca929969c432068a099ae0e4d1baff68faaadda86f76db875869">FVID2_FRAME_STATUS_MAX</a>
+<br/>
+ }</td></tr>
+<tr class="memdesc:a248e190fab40aca929969c432068a099"><td class="mdescLeft"> </td><td class="mdescRight">Enum for state of the FVID2 frame. Typically used for marking FVID2_frame as either SUBMITTED, Completed/Done, Errorneous at the time of flush/abort when driver returns back all the frames. <a href="csl__fvid2__data_types_8h.html#a248e190fab40aca929969c432068a099">More...</a><br/></td></tr>
+<tr class="separator:a248e190fab40aca929969c432068a099"><td class="memSeparator" colspan="2"> </td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a>
+Functions</h2></td></tr>
+<tr class="memitem:a0ff414941310bac0f142807d5ce4992d"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a0ff414941310bac0f142807d5ce4992d">Fvid2_getModeInfo</a> (<a class="el" href="struct_fvid2___mode_info.html">Fvid2_ModeInfo</a> *modeInfo)</td></tr>
+<tr class="memdesc:a0ff414941310bac0f142807d5ce4992d"><td class="mdescLeft"> </td><td class="mdescRight">Function to get the information about various FVID2 modes/standards. <a href="#a0ff414941310bac0f142807d5ce4992d">More...</a><br/></td></tr>
+<tr class="separator:a0ff414941310bac0f142807d5ce4992d"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ac486d696661acd7c496e032ee598a9c4"><td class="memItemLeft" align="right" valign="top">const Char * </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#ac486d696661acd7c496e032ee598a9c4">Fvid2_getDataFmtString</a> (uint32_t dataFmt)</td></tr>
+<tr class="memdesc:ac486d696661acd7c496e032ee598a9c4"><td class="mdescLeft"> </td><td class="mdescRight">Function to get the name of the data format in printable string. <a href="#ac486d696661acd7c496e032ee598a9c4">More...</a><br/></td></tr>
+<tr class="separator:ac486d696661acd7c496e032ee598a9c4"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a5bb999e03ac1bac7da6b62f004f17bf9"><td class="memItemLeft" align="right" valign="top">const Char * </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a5bb999e03ac1bac7da6b62f004f17bf9">Fvid2_getStandardString</a> (uint32_t standard)</td></tr>
+<tr class="memdesc:a5bb999e03ac1bac7da6b62f004f17bf9"><td class="mdescLeft"> </td><td class="mdescRight">Function to get the name of the standard in printable string. <a href="#a5bb999e03ac1bac7da6b62f004f17bf9">More...</a><br/></td></tr>
+<tr class="separator:a5bb999e03ac1bac7da6b62f004f17bf9"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ab54967003a826f9becaf1fb346609658"><td class="memItemLeft" align="right" valign="top">static int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#ab54967003a826f9becaf1fb346609658">Fvid2_isDataFmtYuv422</a> (uint32_t dataFmt)</td></tr>
+<tr class="memdesc:ab54967003a826f9becaf1fb346609658"><td class="mdescLeft"> </td><td class="mdescRight">Function to check whether a data format is YUV422. <a href="#ab54967003a826f9becaf1fb346609658">More...</a><br/></td></tr>
+<tr class="separator:ab54967003a826f9becaf1fb346609658"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:af103bb1d4a91a5112e2418d06ed9c6ad"><td class="memItemLeft" align="right" valign="top">static int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#af103bb1d4a91a5112e2418d06ed9c6ad">Fvid2_isDataFmtYuv420</a> (uint32_t dataFmt)</td></tr>
+<tr class="memdesc:af103bb1d4a91a5112e2418d06ed9c6ad"><td class="mdescLeft"> </td><td class="mdescRight">Function to check whether a data format is YUV420. <a href="#af103bb1d4a91a5112e2418d06ed9c6ad">More...</a><br/></td></tr>
+<tr class="separator:af103bb1d4a91a5112e2418d06ed9c6ad"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a453391f7467c4aeec2968c29b77d5e99"><td class="memItemLeft" align="right" valign="top">static int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a453391f7467c4aeec2968c29b77d5e99">Fvid2_isDataFmtYuv420Sp</a> (uint32_t dataFmt)</td></tr>
+<tr class="memdesc:a453391f7467c4aeec2968c29b77d5e99"><td class="mdescLeft"> </td><td class="mdescRight">Function to check whether a data format is YUV420SP. <a href="#a453391f7467c4aeec2968c29b77d5e99">More...</a><br/></td></tr>
+<tr class="separator:a453391f7467c4aeec2968c29b77d5e99"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a8ac3f62f103515fa9ccc940448d4ebf5"><td class="memItemLeft" align="right" valign="top">static int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a8ac3f62f103515fa9ccc940448d4ebf5">Fvid2_isDataFmtYuv422Sp</a> (uint32_t dataFmt)</td></tr>
+<tr class="memdesc:a8ac3f62f103515fa9ccc940448d4ebf5"><td class="mdescLeft"> </td><td class="mdescRight">Function to check whether a data format is YUV422SP. <a href="#a8ac3f62f103515fa9ccc940448d4ebf5">More...</a><br/></td></tr>
+<tr class="separator:a8ac3f62f103515fa9ccc940448d4ebf5"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a233fa36d9cfcde59468c7ddc8a8990e2"><td class="memItemLeft" align="right" valign="top">static int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a233fa36d9cfcde59468c7ddc8a8990e2">Fvid2_isDataFmtSemiPlanar</a> (uint32_t dataFmt)</td></tr>
+<tr class="memdesc:a233fa36d9cfcde59468c7ddc8a8990e2"><td class="mdescLeft"> </td><td class="mdescRight">Function to check whether a data format is semi-planar. <a href="#a233fa36d9cfcde59468c7ddc8a8990e2">More...</a><br/></td></tr>
+<tr class="separator:a233fa36d9cfcde59468c7ddc8a8990e2"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ab5751442713ba8a70dbaa097be64a891"><td class="memItemLeft" align="right" valign="top">static int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#ab5751442713ba8a70dbaa097be64a891">Fvid2_isDataFmtYuv422I</a> (uint32_t dataFmt)</td></tr>
+<tr class="memdesc:ab5751442713ba8a70dbaa097be64a891"><td class="mdescLeft"> </td><td class="mdescRight">Function to check whether a data format is YUV422 interleaved. <a href="#ab5751442713ba8a70dbaa097be64a891">More...</a><br/></td></tr>
+<tr class="separator:ab5751442713ba8a70dbaa097be64a891"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a906531b9be45f2bd528e1fac44b00340"><td class="memItemLeft" align="right" valign="top">static int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a906531b9be45f2bd528e1fac44b00340">Fvid2_isDataFmtYuv444</a> (uint32_t dataFmt)</td></tr>
+<tr class="memdesc:a906531b9be45f2bd528e1fac44b00340"><td class="mdescLeft"> </td><td class="mdescRight">Function to check whether a data format is YUV444 . <a href="#a906531b9be45f2bd528e1fac44b00340">More...</a><br/></td></tr>
+<tr class="separator:a906531b9be45f2bd528e1fac44b00340"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:abcb80b193d95790e23d51f7a04e232ed"><td class="memItemLeft" align="right" valign="top">static int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#abcb80b193d95790e23d51f7a04e232ed">Fvid2_isDataFmtYuv</a> (uint32_t dataFmt)</td></tr>
+<tr class="memdesc:abcb80b193d95790e23d51f7a04e232ed"><td class="mdescLeft"> </td><td class="mdescRight">Function to check whether a data format is YUV. <a href="#abcb80b193d95790e23d51f7a04e232ed">More...</a><br/></td></tr>
+<tr class="separator:abcb80b193d95790e23d51f7a04e232ed"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a7b92c32c5cd073fd09ca32a655065048"><td class="memItemLeft" align="right" valign="top">static int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a7b92c32c5cd073fd09ca32a655065048">Fvid2_isDataFmtBayer</a> (uint32_t dataFmt)</td></tr>
+<tr class="memdesc:a7b92c32c5cd073fd09ca32a655065048"><td class="mdescLeft"> </td><td class="mdescRight">Function to check whether a data format is Bayer with MosaicPattern. <a href="#a7b92c32c5cd073fd09ca32a655065048">More...</a><br/></td></tr>
+<tr class="separator:a7b92c32c5cd073fd09ca32a655065048"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:adc25f711515d08d8cb9cb5752135f969"><td class="memItemLeft" align="right" valign="top">static int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#adc25f711515d08d8cb9cb5752135f969">Fvid2_isDataFmtRgb16bit</a> (uint32_t dataFmt)</td></tr>
+<tr class="memdesc:adc25f711515d08d8cb9cb5752135f969"><td class="mdescLeft"> </td><td class="mdescRight">Function to check whether a data format is RGB 16-bit. <a href="#adc25f711515d08d8cb9cb5752135f969">More...</a><br/></td></tr>
+<tr class="separator:adc25f711515d08d8cb9cb5752135f969"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a7a17697bd4677e5c0e4611c91821c5b2"><td class="memItemLeft" align="right" valign="top">static int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a7a17697bd4677e5c0e4611c91821c5b2">Fvid2_isDataFmtRgb</a> (uint32_t dataFmt)</td></tr>
+<tr class="memdesc:a7a17697bd4677e5c0e4611c91821c5b2"><td class="mdescLeft"> </td><td class="mdescRight">Function to check whether a data format is RGB . <a href="#a7a17697bd4677e5c0e4611c91821c5b2">More...</a><br/></td></tr>
+<tr class="separator:a7a17697bd4677e5c0e4611c91821c5b2"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a933b005f12a4845f842d978718560099"><td class="memItemLeft" align="right" valign="top">static int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a933b005f12a4845f842d978718560099">Fvid2_isDataFmtRgb24bit</a> (uint32_t dataFmt)</td></tr>
+<tr class="memdesc:a933b005f12a4845f842d978718560099"><td class="mdescLeft"> </td><td class="mdescRight">Function to check whether a data format is RGB 24-bit. <a href="#a933b005f12a4845f842d978718560099">More...</a><br/></td></tr>
+<tr class="separator:a933b005f12a4845f842d978718560099"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a83e52e7870da61828fccff98d4985f77"><td class="memItemLeft" align="right" valign="top">static int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a83e52e7870da61828fccff98d4985f77">Fvid2_isDataFmtRgb32bit</a> (uint32_t dataFmt)</td></tr>
+<tr class="memdesc:a83e52e7870da61828fccff98d4985f77"><td class="mdescLeft"> </td><td class="mdescRight">Function to check whether a data format is RGB 32-bit. <a href="#a83e52e7870da61828fccff98d4985f77">More...</a><br/></td></tr>
+<tr class="separator:a83e52e7870da61828fccff98d4985f77"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:addaf6c10b34dbfbe5b9e892c4e08a90f"><td class="memItemLeft" align="right" valign="top">static int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#addaf6c10b34dbfbe5b9e892c4e08a90f">Fvid2_isDataFmtRgb64bit</a> (uint32_t dataFmt)</td></tr>
+<tr class="memdesc:addaf6c10b34dbfbe5b9e892c4e08a90f"><td class="mdescLeft"> </td><td class="mdescRight">Function to check whether a data format is RGB 64 bit. <a href="#addaf6c10b34dbfbe5b9e892c4e08a90f">More...</a><br/></td></tr>
+<tr class="separator:addaf6c10b34dbfbe5b9e892c4e08a90f"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a8938f5c1b9a0655d7dbb4aabb11a6c16"><td class="memItemLeft" align="right" valign="top">static uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a8938f5c1b9a0655d7dbb4aabb11a6c16">Fvid2_BayerColorIndex</a> (uint32_t dataFmt, uint32_t color)</td></tr>
+<tr class="memdesc:a8938f5c1b9a0655d7dbb4aabb11a6c16"><td class="mdescLeft"> </td><td class="mdescRight">Function to get the index of the color for bayer data format. <a href="#a8938f5c1b9a0655d7dbb4aabb11a6c16">More...</a><br/></td></tr>
+<tr class="separator:a8938f5c1b9a0655d7dbb4aabb11a6c16"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a8996b9bd71f65f97abf2ee422611529b"><td class="memItemLeft" align="right" valign="top">static int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a8996b9bd71f65f97abf2ee422611529b">Fvid2_isStandardVesa</a> (uint32_t standard)</td></tr>
+<tr class="memdesc:a8996b9bd71f65f97abf2ee422611529b"><td class="mdescLeft"> </td><td class="mdescRight">Function to check whether a standard is VESA mode or not. <a href="#a8996b9bd71f65f97abf2ee422611529b">More...</a><br/></td></tr>
+<tr class="separator:a8996b9bd71f65f97abf2ee422611529b"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a3c57266e7a813692eee72e3624f22fdf"><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a3c57266e7a813692eee72e3624f22fdf">Fvid2Format_init</a> (<a class="el" href="struct_fvid2___format.html">Fvid2_Format</a> *fmt)</td></tr>
+<tr class="memdesc:a3c57266e7a813692eee72e3624f22fdf"><td class="mdescLeft"> </td><td class="mdescRight"><a class="el" href="struct_fvid2___format.html" title="FVID2 video buffer format specification. ">Fvid2_Format</a> structure init function. <a href="#a3c57266e7a813692eee72e3624f22fdf">More...</a><br/></td></tr>
+<tr class="separator:a3c57266e7a813692eee72e3624f22fdf"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a699a19f64a958b0e023264d2626df860"><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a699a19f64a958b0e023264d2626df860">Fvid2SubFrameInfo_init</a> (<a class="el" href="struct_fvid2___sub_frame_info.html">Fvid2_SubFrameInfo</a> *sfInfo)</td></tr>
+<tr class="memdesc:a699a19f64a958b0e023264d2626df860"><td class="mdescLeft"> </td><td class="mdescRight"><a class="el" href="struct_fvid2___sub_frame_info.html" title="Sub-Frame information. ">Fvid2_SubFrameInfo</a> structure init function. <a href="#a699a19f64a958b0e023264d2626df860">More...</a><br/></td></tr>
+<tr class="separator:a699a19f64a958b0e023264d2626df860"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a519f857d75a4b946c99e0a8cfa0da148"><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a519f857d75a4b946c99e0a8cfa0da148">Fvid2Frame_init</a> (<a class="el" href="struct_fvid2___frame.html">Fvid2_Frame</a> *frm)</td></tr>
+<tr class="memdesc:a519f857d75a4b946c99e0a8cfa0da148"><td class="mdescLeft"> </td><td class="mdescRight"><a class="el" href="struct_fvid2___frame.html" title="FVID2 frame buffer structure. ">Fvid2_Frame</a> structure init function. <a href="#a519f857d75a4b946c99e0a8cfa0da148">More...</a><br/></td></tr>
+<tr class="separator:a519f857d75a4b946c99e0a8cfa0da148"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a835800489d2c42aed71f30941b9f2fd2"><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a835800489d2c42aed71f30941b9f2fd2">Fvid2FrameList_init</a> (<a class="el" href="struct_fvid2___frame_list.html">Fvid2_FrameList</a> *fList)</td></tr>
+<tr class="memdesc:a835800489d2c42aed71f30941b9f2fd2"><td class="mdescLeft"> </td><td class="mdescRight"><a class="el" href="struct_fvid2___frame_list.html" title="FVID2 frame buffer list used to exchange multiple FVID2 frames in a single driver call...">Fvid2_FrameList</a> structure init function. <a href="#a835800489d2c42aed71f30941b9f2fd2">More...</a><br/></td></tr>
+<tr class="separator:a835800489d2c42aed71f30941b9f2fd2"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a7fd1ec90c192cdc87f2e51819ad6b6fa"><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a7fd1ec90c192cdc87f2e51819ad6b6fa">Fvid2ModeInfo_init</a> (<a class="el" href="struct_fvid2___mode_info.html">Fvid2_ModeInfo</a> *modeInfo)</td></tr>
+<tr class="memdesc:a7fd1ec90c192cdc87f2e51819ad6b6fa"><td class="mdescLeft"> </td><td class="mdescRight"><a class="el" href="struct_fvid2___mode_info.html" title="FVID2 Mode information structure. ">Fvid2_ModeInfo</a> structure init function. This defaults to 1080p60. <a href="#a7fd1ec90c192cdc87f2e51819ad6b6fa">More...</a><br/></td></tr>
+<tr class="separator:a7fd1ec90c192cdc87f2e51819ad6b6fa"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a7f76750350b75947c9bfa26b76798c92"><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a7f76750350b75947c9bfa26b76798c92">Fvid2CropConfig_init</a> (<a class="el" href="struct_fvid2___crop_config.html">Fvid2_CropConfig</a> *cropCfg)</td></tr>
+<tr class="memdesc:a7f76750350b75947c9bfa26b76798c92"><td class="mdescLeft"> </td><td class="mdescRight"><a class="el" href="struct_fvid2___crop_config.html" title="Structure containing crop configuration - used in Scaler and VCOMP. ">Fvid2_CropConfig</a> structure init function. <a href="#a7f76750350b75947c9bfa26b76798c92">More...</a><br/></td></tr>
+<tr class="separator:a7f76750350b75947c9bfa26b76798c92"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:acde86e2766599bb25a7126f364e78c4e"><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#acde86e2766599bb25a7126f364e78c4e">Fvid2PosConfig_init</a> (<a class="el" href="struct_fvid2___pos_config.html">Fvid2_PosConfig</a> *posCfg)</td></tr>
+<tr class="memdesc:acde86e2766599bb25a7126f364e78c4e"><td class="mdescLeft"> </td><td class="mdescRight"><a class="el" href="struct_fvid2___pos_config.html" title="Structure containing position configuration - used in VCOMP and CIG. ">Fvid2_PosConfig</a> structure init function. <a href="#acde86e2766599bb25a7126f364e78c4e">More...</a><br/></td></tr>
+<tr class="separator:acde86e2766599bb25a7126f364e78c4e"><td class="memSeparator" colspan="2"> </td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
+Digital Video Format</h2></td></tr>
+<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrpe225defff55bffecf06aba9e2bc90cd3"></a><a class="anchor" id="Fvid2_DVFormat"></a></p>
+</td></tr>
+<tr class="memitem:a684efc69ec215474fc66994999213ce9"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a684efc69ec215474fc66994999213ce9"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a684efc69ec215474fc66994999213ce9">FVID2_DV_BT656_EMBSYNC</a>   ((uint32_t) 0x00U)</td></tr>
+<tr class="memdesc:a684efc69ec215474fc66994999213ce9"><td class="mdescLeft"> </td><td class="mdescRight">Video format is BT656 with embedded sync. <br/></td></tr>
+<tr class="separator:a684efc69ec215474fc66994999213ce9"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ac69252ca09459e02c7a290db6eeba988"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ac69252ca09459e02c7a290db6eeba988"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#ac69252ca09459e02c7a290db6eeba988">FVID2_DV_BT1120_EMBSYNC</a>   ((uint32_t) 0x01U)</td></tr>
+<tr class="memdesc:ac69252ca09459e02c7a290db6eeba988"><td class="mdescLeft"> </td><td class="mdescRight">Video format is BT1120 with embedded sync. <br/></td></tr>
+<tr class="separator:ac69252ca09459e02c7a290db6eeba988"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a492d3c9a26a007b2d24bac7e3b2e34d2"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a492d3c9a26a007b2d24bac7e3b2e34d2"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a492d3c9a26a007b2d24bac7e3b2e34d2">FVID2_DV_GENERIC_DISCSYNC</a>   ((uint32_t) 0x02U)</td></tr>
+<tr class="memdesc:a492d3c9a26a007b2d24bac7e3b2e34d2"><td class="mdescLeft"> </td><td class="mdescRight">Video format is for any discrete sync. <br/></td></tr>
+<tr class="separator:a492d3c9a26a007b2d24bac7e3b2e34d2"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:adb4edd1db6ff8f90a668f7d9d568b77e"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="adb4edd1db6ff8f90a668f7d9d568b77e"></a>
+typedef uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#adb4edd1db6ff8f90a668f7d9d568b77e">Fvid2_DVFormat</a></td></tr>
+<tr class="memdesc:adb4edd1db6ff8f90a668f7d9d568b77e"><td class="mdescLeft"> </td><td class="mdescRight">Video format is BT656 with embedded sync. <br/></td></tr>
+<tr class="separator:adb4edd1db6ff8f90a668f7d9d568b77e"><td class="memSeparator" colspan="2"> </td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
+Video Buffer Flip Type</h2></td></tr>
+<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrp794f808db04cd771462007cb7182ace9"></a><a class="anchor" id="Fvid2_FlipType"></a></p>
+</td></tr>
+<tr class="memitem:aab734c88ee2494bf6eb6b1e0c01c41d1"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aab734c88ee2494bf6eb6b1e0c01c41d1"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#aab734c88ee2494bf6eb6b1e0c01c41d1">FVID2_FLIP_TYPE_NONE</a>   ((uint32_t) 0x00U)</td></tr>
+<tr class="memdesc:aab734c88ee2494bf6eb6b1e0c01c41d1"><td class="mdescLeft"> </td><td class="mdescRight">Flip Type is None. <br/></td></tr>
+<tr class="separator:aab734c88ee2494bf6eb6b1e0c01c41d1"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:aa12baa65ad86757aafa36c5f22a93de2"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aa12baa65ad86757aafa36c5f22a93de2"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#aa12baa65ad86757aafa36c5f22a93de2">FVID2_FLIP_TYPE_H</a>   ((uint32_t) 0x01U)</td></tr>
+<tr class="memdesc:aa12baa65ad86757aafa36c5f22a93de2"><td class="mdescLeft"> </td><td class="mdescRight">Flip Type is Horizontal i.e. along Y axis. <br/></td></tr>
+<tr class="separator:aa12baa65ad86757aafa36c5f22a93de2"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:acb0e70768a82732cb712c9010be02610"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="acb0e70768a82732cb712c9010be02610"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#acb0e70768a82732cb712c9010be02610">FVID2_FLIP_TYPE_V</a>   ((uint32_t) 0x02U)</td></tr>
+<tr class="memdesc:acb0e70768a82732cb712c9010be02610"><td class="mdescLeft"> </td><td class="mdescRight">Flip Type is Vertical i.e. along X axis. <br/></td></tr>
+<tr class="separator:acb0e70768a82732cb712c9010be02610"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a346b3fc00efbc0e4d14e73e63aaea40d"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a346b3fc00efbc0e4d14e73e63aaea40d"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a346b3fc00efbc0e4d14e73e63aaea40d">FVID2_FLIP_TYPE_HV</a>   ((uint32_t) 0x03U)</td></tr>
+<tr class="memdesc:a346b3fc00efbc0e4d14e73e63aaea40d"><td class="mdescLeft"> </td><td class="mdescRight">Flip Type is Horizontal + Vertical. <br/></td></tr>
+<tr class="separator:a346b3fc00efbc0e4d14e73e63aaea40d"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a936d3064b224ce1fb3e7204b044e1013"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a936d3064b224ce1fb3e7204b044e1013"></a>
+typedef uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a936d3064b224ce1fb3e7204b044e1013">Fvid2_FlipType</a></td></tr>
+<tr class="memdesc:a936d3064b224ce1fb3e7204b044e1013"><td class="mdescLeft"> </td><td class="mdescRight">Flip Type is None. <br/></td></tr>
+<tr class="separator:a936d3064b224ce1fb3e7204b044e1013"><td class="memSeparator" colspan="2"> </td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
+Video Data format</h2></td></tr>
+<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrp029ef7ee9df6ee72e2fdac2a23c1c80a"></a>Naming convention followed FVID2_DF_ARGB32_8888 In 8-bit byte memory </p>
+<h1>B0 B1 B2 B3 B4 B5 B6 B7 </h1>
+<h1>| A | R | G | B | A | R | G | B | </h1>
+<p><a class="anchor" id="Fvid2_DataFormat"></a> FVID2_DF_YUV422I_UYVY </p>
+<h1>B0 B1 B2 B3 B4 B5 B6 B7 </h1>
+<h1>| U | Y | V | Y | U | Y | V | Y | </h1>
+<p>FVID2_DF_ARGB16_4444 </p>
+<h1>B0 B1 B2 B3 B4 B5 B6 B7 </h1>
+<h1>| AR | GB | AR | GB | AR | GB | AR | GB | </h1>
+</td></tr>
+<tr class="memitem:a448a369807ae9869026c20d2dcc6418a"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a448a369807ae9869026c20d2dcc6418a"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a448a369807ae9869026c20d2dcc6418a">FVID2_DF_YUV422I_UYVY</a>   ((uint32_t) 0x0000U)</td></tr>
+<tr class="memdesc:a448a369807ae9869026c20d2dcc6418a"><td class="mdescLeft"> </td><td class="mdescRight">YUV 422 Interleaved format - UYVY. <br/></td></tr>
+<tr class="separator:a448a369807ae9869026c20d2dcc6418a"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a3e813c4bd94d89da0895513982484244"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a3e813c4bd94d89da0895513982484244"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a3e813c4bd94d89da0895513982484244">FVID2_DF_YUV422I_YUYV</a>   ((uint32_t) 0x0001U)</td></tr>
+<tr class="memdesc:a3e813c4bd94d89da0895513982484244"><td class="mdescLeft"> </td><td class="mdescRight">YUV 422 Interleaved format - YUYV. <br/></td></tr>
+<tr class="separator:a3e813c4bd94d89da0895513982484244"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ad36f836a5191c1fc3e8438010f93034b"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ad36f836a5191c1fc3e8438010f93034b"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#ad36f836a5191c1fc3e8438010f93034b">FVID2_DF_YUV422I_YVYU</a>   ((uint32_t) 0x0002U)</td></tr>
+<tr class="memdesc:ad36f836a5191c1fc3e8438010f93034b"><td class="mdescLeft"> </td><td class="mdescRight">YUV 422 Interleaved format - YVYU. <br/></td></tr>
+<tr class="separator:ad36f836a5191c1fc3e8438010f93034b"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:aa240e8708764e2963827afbe8c124af6"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aa240e8708764e2963827afbe8c124af6"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#aa240e8708764e2963827afbe8c124af6">FVID2_DF_YUV422I_VYUY</a>   ((uint32_t) 0x0003U)</td></tr>
+<tr class="memdesc:aa240e8708764e2963827afbe8c124af6"><td class="mdescLeft"> </td><td class="mdescRight">YUV 422 Interleaved format - VYUY. <br/></td></tr>
+<tr class="separator:aa240e8708764e2963827afbe8c124af6"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a2aaccb6bfe08e0fc445e15445ad79c22"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a2aaccb6bfe08e0fc445e15445ad79c22"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a2aaccb6bfe08e0fc445e15445ad79c22">FVID2_DF_YUV422SP_UV</a>   ((uint32_t) 0x0004U)</td></tr>
+<tr class="memdesc:a2aaccb6bfe08e0fc445e15445ad79c22"><td class="mdescLeft"> </td><td class="mdescRight">YUV 422 Semi-Planar - Y separate, UV interleaved. <br/></td></tr>
+<tr class="separator:a2aaccb6bfe08e0fc445e15445ad79c22"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a631723f6c512f2e90d9cacfdbcbfa573"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a631723f6c512f2e90d9cacfdbcbfa573"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a631723f6c512f2e90d9cacfdbcbfa573">FVID2_DF_YUV422SP_VU</a>   ((uint32_t) 0x0005U)</td></tr>
+<tr class="memdesc:a631723f6c512f2e90d9cacfdbcbfa573"><td class="mdescLeft"> </td><td class="mdescRight">YUV 422 Semi-Planar - Y separate, VU interleaved. <br/></td></tr>
+<tr class="separator:a631723f6c512f2e90d9cacfdbcbfa573"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ad90f4b08909fc4f5deded1bde7c6edd2"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ad90f4b08909fc4f5deded1bde7c6edd2"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#ad90f4b08909fc4f5deded1bde7c6edd2">FVID2_DF_YUV422P</a>   ((uint32_t) 0x0006U)</td></tr>
+<tr class="memdesc:ad90f4b08909fc4f5deded1bde7c6edd2"><td class="mdescLeft"> </td><td class="mdescRight">YUV 422 Planar - Y, U and V separate. <br/></td></tr>
+<tr class="separator:ad90f4b08909fc4f5deded1bde7c6edd2"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ab63b38caf7ca24ce594c85b3dfbb8759"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ab63b38caf7ca24ce594c85b3dfbb8759"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#ab63b38caf7ca24ce594c85b3dfbb8759">FVID2_DF_YUV420SP_UV</a>   ((uint32_t) 0x0007U)</td></tr>
+<tr class="memdesc:ab63b38caf7ca24ce594c85b3dfbb8759"><td class="mdescLeft"> </td><td class="mdescRight">YUV 420 Semi-Planar - Y separate, UV interleaved. <br/></td></tr>
+<tr class="separator:ab63b38caf7ca24ce594c85b3dfbb8759"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ad6889d3b8017a064be486267bb3630a4"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ad6889d3b8017a064be486267bb3630a4"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#ad6889d3b8017a064be486267bb3630a4">FVID2_DF_YUV420SP_VU</a>   ((uint32_t) 0x0008U)</td></tr>
+<tr class="memdesc:ad6889d3b8017a064be486267bb3630a4"><td class="mdescLeft"> </td><td class="mdescRight">YUV 420 Semi-Planar - Y separate, VU interleaved. <br/></td></tr>
+<tr class="separator:ad6889d3b8017a064be486267bb3630a4"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a1128242a44b82fb22b204f53f84280e8"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a1128242a44b82fb22b204f53f84280e8"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a1128242a44b82fb22b204f53f84280e8">FVID2_DF_YUV420P</a>   ((uint32_t) 0x0009U)</td></tr>
+<tr class="memdesc:a1128242a44b82fb22b204f53f84280e8"><td class="mdescLeft"> </td><td class="mdescRight">YUV 420 Planar - Y, U and V separate. <br/></td></tr>
+<tr class="separator:a1128242a44b82fb22b204f53f84280e8"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:acac24fc0e004eaac9745a0b147fbecc8"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="acac24fc0e004eaac9745a0b147fbecc8"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#acac24fc0e004eaac9745a0b147fbecc8">FVID2_DF_YUV444P</a>   ((uint32_t) 0x000AU)</td></tr>
+<tr class="memdesc:acac24fc0e004eaac9745a0b147fbecc8"><td class="mdescLeft"> </td><td class="mdescRight">YUV 444 Planar - Y, U and V separate. <br/></td></tr>
+<tr class="separator:acac24fc0e004eaac9745a0b147fbecc8"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:af2787196b36deee7af96a2c3e9daa1d1"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="af2787196b36deee7af96a2c3e9daa1d1"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#af2787196b36deee7af96a2c3e9daa1d1">FVID2_DF_YUV444I</a>   ((uint32_t) 0x000BU)</td></tr>
+<tr class="memdesc:af2787196b36deee7af96a2c3e9daa1d1"><td class="mdescLeft"> </td><td class="mdescRight">YUV 444 interleaved - YUVYUV... <br/></td></tr>
+<tr class="separator:af2787196b36deee7af96a2c3e9daa1d1"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a32ae6edbeded76ac2c45277cec3b339c"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a32ae6edbeded76ac2c45277cec3b339c"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a32ae6edbeded76ac2c45277cec3b339c">FVID2_DF_RGB16_565</a>   ((uint32_t) 0x000CU)</td></tr>
+<tr class="memdesc:a32ae6edbeded76ac2c45277cec3b339c"><td class="mdescLeft"> </td><td class="mdescRight">RGB565 16-bit - 5-bits R, 6-bits G, 5-bits B. <br/></td></tr>
+<tr class="separator:a32ae6edbeded76ac2c45277cec3b339c"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a01421f2c9f5ed4e7e140d4aa53e96018"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a01421f2c9f5ed4e7e140d4aa53e96018"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a01421f2c9f5ed4e7e140d4aa53e96018">FVID2_DF_ARGB16_1555</a>   ((uint32_t) 0x000DU)</td></tr>
+<tr class="memdesc:a01421f2c9f5ed4e7e140d4aa53e96018"><td class="mdescLeft"> </td><td class="mdescRight">ARGB1555 16-bit - 5-bits R, 5-bits G, 5-bits B, 1-bit Alpha . <br/></td></tr>
+<tr class="separator:a01421f2c9f5ed4e7e140d4aa53e96018"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a4bdfe77d3077368a41b4a97addaa6440"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a4bdfe77d3077368a41b4a97addaa6440"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a4bdfe77d3077368a41b4a97addaa6440">FVID2_DF_RGBA16_5551</a>   ((uint32_t) 0x000EU)</td></tr>
+<tr class="memdesc:a4bdfe77d3077368a41b4a97addaa6440"><td class="mdescLeft"> </td><td class="mdescRight">RGBA5551 16-bit - 5-bits R, 5-bits G, 5-bits B, 1-bit Alpha . <br/></td></tr>
+<tr class="separator:a4bdfe77d3077368a41b4a97addaa6440"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a158a6625cc1a572a0faa171e0cc8177c"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a158a6625cc1a572a0faa171e0cc8177c"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a158a6625cc1a572a0faa171e0cc8177c">FVID2_DF_ARGB16_4444</a>   ((uint32_t) 0x000FU)</td></tr>
+<tr class="memdesc:a158a6625cc1a572a0faa171e0cc8177c"><td class="mdescLeft"> </td><td class="mdescRight">ARGB4444 16-bit - 4-bits R, 4-bits G, 4-bits B, 4-bit Alpha . <br/></td></tr>
+<tr class="separator:a158a6625cc1a572a0faa171e0cc8177c"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a0b3ae71bf4eeab7f5ebe6ca0711cf16a"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a0b3ae71bf4eeab7f5ebe6ca0711cf16a"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a0b3ae71bf4eeab7f5ebe6ca0711cf16a">FVID2_DF_RGBA16_4444</a>   ((uint32_t) 0x0010U)</td></tr>
+<tr class="memdesc:a0b3ae71bf4eeab7f5ebe6ca0711cf16a"><td class="mdescLeft"> </td><td class="mdescRight">RGBA4444 16-bit - 4-bits R, 4-bits G, 4-bits B, 4-bit Alpha . <br/></td></tr>
+<tr class="separator:a0b3ae71bf4eeab7f5ebe6ca0711cf16a"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a5b7c873e84f994c0ca6ec5a2e8728fe0"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a5b7c873e84f994c0ca6ec5a2e8728fe0"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a5b7c873e84f994c0ca6ec5a2e8728fe0">FVID2_DF_RGBX16_4444</a>   ((uint32_t) 0x0011U)</td></tr>
+<tr class="memdesc:a5b7c873e84f994c0ca6ec5a2e8728fe0"><td class="mdescLeft"> </td><td class="mdescRight">RGBX4444 16-bit - 4-bits R, 4-bits G, 4-bits B, 4-bit Unused . <br/></td></tr>
+<tr class="separator:a5b7c873e84f994c0ca6ec5a2e8728fe0"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a8254787491a05dd9d5473f3cd3e6bf8b"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a8254787491a05dd9d5473f3cd3e6bf8b"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a8254787491a05dd9d5473f3cd3e6bf8b">FVID2_DF_ARGB24_6666</a>   ((uint32_t) 0x0012U)</td></tr>
+<tr class="memdesc:a8254787491a05dd9d5473f3cd3e6bf8b"><td class="mdescLeft"> </td><td class="mdescRight">ARGB6666 24-bit - 6-bits R, 6-bits G, 6-bits B, 6-bit Alpha . <br/></td></tr>
+<tr class="separator:a8254787491a05dd9d5473f3cd3e6bf8b"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a19d91f4e19785c48b3b66296889681b5"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a19d91f4e19785c48b3b66296889681b5"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a19d91f4e19785c48b3b66296889681b5">FVID2_DF_RGBA24_6666</a>   ((uint32_t) 0x0013U)</td></tr>
+<tr class="memdesc:a19d91f4e19785c48b3b66296889681b5"><td class="mdescLeft"> </td><td class="mdescRight">RGBA6666 24-bit - 6-bits R, 6-bits G, 6-bits B, 6-bit Alpha . <br/></td></tr>
+<tr class="separator:a19d91f4e19785c48b3b66296889681b5"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a64e90ed408291967281eb6705d23d89a"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a64e90ed408291967281eb6705d23d89a"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a64e90ed408291967281eb6705d23d89a">FVID2_DF_RGB24_888</a>   ((uint32_t) 0x0014U)</td></tr>
+<tr class="memdesc:a64e90ed408291967281eb6705d23d89a"><td class="mdescLeft"> </td><td class="mdescRight">RGB24 24-bit - 8-bits R, 8-bits G, 8-bits B. <br/></td></tr>
+<tr class="separator:a64e90ed408291967281eb6705d23d89a"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ad2bc7fe03beb6e72d2ca72e586f04d7c"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ad2bc7fe03beb6e72d2ca72e586f04d7c"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#ad2bc7fe03beb6e72d2ca72e586f04d7c">FVID2_DF_BGRX_4444</a>   ((uint32_t) 0x0015U)</td></tr>
+<tr class="memdesc:ad2bc7fe03beb6e72d2ca72e586f04d7c"><td class="mdescLeft"> </td><td class="mdescRight">RGBx12-16bit- 4-bits R, 4-bits G, 4-bits B, 4-bits unused . <br/></td></tr>
+<tr class="separator:ad2bc7fe03beb6e72d2ca72e586f04d7c"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a8d277b7f056d59b6c83265f0cc67e0d4"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a8d277b7f056d59b6c83265f0cc67e0d4"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a8d277b7f056d59b6c83265f0cc67e0d4">FVID2_DF_XBGR_4444</a>   ((uint32_t) 0x0016U)</td></tr>
+<tr class="memdesc:a8d277b7f056d59b6c83265f0cc67e0d4"><td class="mdescLeft"> </td><td class="mdescRight">xRGB12-16bit- 4-bits R, 4-bits G, 4-bits B, 4-bits unused. <br/></td></tr>
+<tr class="separator:a8d277b7f056d59b6c83265f0cc67e0d4"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a1dc4c2f912fc9ba8b5fb69e8b6150508"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a1dc4c2f912fc9ba8b5fb69e8b6150508"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a1dc4c2f912fc9ba8b5fb69e8b6150508">FVID2_DF_ARGB32_8888</a>   ((uint32_t) 0x0017U)</td></tr>
+<tr class="memdesc:a1dc4c2f912fc9ba8b5fb69e8b6150508"><td class="mdescLeft"> </td><td class="mdescRight">ARGB32 32-bit - 8-bits R, 8-bits G, 8-bits B, 8-bit Alpha . <br/></td></tr>
+<tr class="separator:a1dc4c2f912fc9ba8b5fb69e8b6150508"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a239a986a0538e87169a3a93c6f930659"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a239a986a0538e87169a3a93c6f930659"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a239a986a0538e87169a3a93c6f930659">FVID2_DF_XRGB32_8888</a>   ((uint32_t) 0x0018U)</td></tr>
+<tr class="memdesc:a239a986a0538e87169a3a93c6f930659"><td class="mdescLeft"> </td><td class="mdescRight">XRGB32 32-bit - 8-bits R, 8-bits G, 8-bits B, 8-bit unused . <br/></td></tr>
+<tr class="separator:a239a986a0538e87169a3a93c6f930659"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ae4d69b5f89d0cada72e9ddce76bafdcd"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ae4d69b5f89d0cada72e9ddce76bafdcd"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#ae4d69b5f89d0cada72e9ddce76bafdcd">FVID2_DF_RGBA32_8888</a>   ((uint32_t) 0x0019U)</td></tr>
+<tr class="memdesc:ae4d69b5f89d0cada72e9ddce76bafdcd"><td class="mdescLeft"> </td><td class="mdescRight">RGBA32 32-bit - 8-bits R, 8-bits G, 8-bits B, 8-bit Alpha . <br/></td></tr>
+<tr class="separator:ae4d69b5f89d0cada72e9ddce76bafdcd"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a18ba1f57934c0a1253c6e3dffeb259c0"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a18ba1f57934c0a1253c6e3dffeb259c0"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a18ba1f57934c0a1253c6e3dffeb259c0">FVID2_DF_BGR16_565</a>   ((uint32_t) 0x001AU)</td></tr>
+<tr class="memdesc:a18ba1f57934c0a1253c6e3dffeb259c0"><td class="mdescLeft"> </td><td class="mdescRight">BGR565 16-bit - 5-bits B, 6-bits G, 5-bits R. <br/></td></tr>
+<tr class="separator:a18ba1f57934c0a1253c6e3dffeb259c0"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a00daf662fcdcb2597982219fb65acc10"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a00daf662fcdcb2597982219fb65acc10"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a00daf662fcdcb2597982219fb65acc10">FVID2_DF_ABGR16_1555</a>   ((uint32_t) 0x001BU)</td></tr>
+<tr class="memdesc:a00daf662fcdcb2597982219fb65acc10"><td class="mdescLeft"> </td><td class="mdescRight">ABGR1555 16-bit - 5-bits B, 5-bits G, 5-bits R, 1-bit Alpha . <br/></td></tr>
+<tr class="separator:a00daf662fcdcb2597982219fb65acc10"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a6072fd045d93236b07e78c370c10a34c"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a6072fd045d93236b07e78c370c10a34c"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a6072fd045d93236b07e78c370c10a34c">FVID2_DF_ABGR16_4444</a>   ((uint32_t) 0x001CU)</td></tr>
+<tr class="memdesc:a6072fd045d93236b07e78c370c10a34c"><td class="mdescLeft"> </td><td class="mdescRight">ABGR4444 16-bit - 4-bits B, 4-bits G, 4-bits R, 4-bit Alpha . <br/></td></tr>
+<tr class="separator:a6072fd045d93236b07e78c370c10a34c"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a1791763d70b2a9ef4ce3c0d58713353b"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a1791763d70b2a9ef4ce3c0d58713353b"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a1791763d70b2a9ef4ce3c0d58713353b">FVID2_DF_BGRA16_5551</a>   ((uint32_t) 0x001DU)</td></tr>
+<tr class="memdesc:a1791763d70b2a9ef4ce3c0d58713353b"><td class="mdescLeft"> </td><td class="mdescRight">BGRA5551 16-bit - 5-bits B, 5-bits G, 5-bits R, 1-bit Alpha . <br/></td></tr>
+<tr class="separator:a1791763d70b2a9ef4ce3c0d58713353b"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a89624affc2cf501c93a0ee1a5bbf15ea"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a89624affc2cf501c93a0ee1a5bbf15ea"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a89624affc2cf501c93a0ee1a5bbf15ea">FVID2_DF_BGRA16_4444</a>   ((uint32_t) 0x001EU)</td></tr>
+<tr class="memdesc:a89624affc2cf501c93a0ee1a5bbf15ea"><td class="mdescLeft"> </td><td class="mdescRight">BGRA4444 16-bit - 4-bits B, 4-bits G, 4-bits R, 4-bit Alpha . <br/></td></tr>
+<tr class="separator:a89624affc2cf501c93a0ee1a5bbf15ea"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a94d16fe4ce7013be49163a6766acc4b5"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a94d16fe4ce7013be49163a6766acc4b5"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a94d16fe4ce7013be49163a6766acc4b5">FVID2_DF_AGBR16_1555</a>   ((uint32_t) 0x001FU)</td></tr>
+<tr class="memdesc:a94d16fe4ce7013be49163a6766acc4b5"><td class="mdescLeft"> </td><td class="mdescRight">ABGR1555 16-bit - 5-bits G, 5-bits B, 5-bits R, 1-bit Alpha . <br/></td></tr>
+<tr class="separator:a94d16fe4ce7013be49163a6766acc4b5"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:af06b2c482186670cf233856fd352ee4e"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="af06b2c482186670cf233856fd352ee4e"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#af06b2c482186670cf233856fd352ee4e">FVID2_DF_AGBR16_4444</a>   ((uint32_t) 0x0020U)</td></tr>
+<tr class="memdesc:af06b2c482186670cf233856fd352ee4e"><td class="mdescLeft"> </td><td class="mdescRight">ABGR4444 16-bit - 4-bits G, 4-bits B, 4-bits R, 4-bit Alpha . <br/></td></tr>
+<tr class="separator:af06b2c482186670cf233856fd352ee4e"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a56456b051414f24f15e54f8047ed2e24"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a56456b051414f24f15e54f8047ed2e24"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a56456b051414f24f15e54f8047ed2e24">FVID2_DF_XGBR16_1555</a>   ((uint32_t) 0x0021U)</td></tr>
+<tr class="memdesc:a56456b051414f24f15e54f8047ed2e24"><td class="mdescLeft"> </td><td class="mdescRight">XGBR1555 16-bit - 5-bits G, 5-bits B, 5-bits R, 1-bit unused . <br/></td></tr>
+<tr class="separator:a56456b051414f24f15e54f8047ed2e24"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:aacb134c845672f1d4c36d8ef7c90640b"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aacb134c845672f1d4c36d8ef7c90640b"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#aacb134c845672f1d4c36d8ef7c90640b">FVID2_DF_BGRX16_5551</a>   ((uint32_t) 0x0022U)</td></tr>
+<tr class="memdesc:aacb134c845672f1d4c36d8ef7c90640b"><td class="mdescLeft"> </td><td class="mdescRight">BGRX5551 16-bit - 5-bits B, 5-bits G, 5-bits R, 1-bit unused . <br/></td></tr>
+<tr class="separator:aacb134c845672f1d4c36d8ef7c90640b"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a67826657e1c94c81a777ce2a3df6c9ec"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a67826657e1c94c81a777ce2a3df6c9ec"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a67826657e1c94c81a777ce2a3df6c9ec">FVID2_DF_ABGR24_6666</a>   ((uint32_t) 0x0023U)</td></tr>
+<tr class="memdesc:a67826657e1c94c81a777ce2a3df6c9ec"><td class="mdescLeft"> </td><td class="mdescRight">ABGR6666 24-bit - 6-bits B, 6-bits G, 6-bits R, 6-bit Alpha . <br/></td></tr>
+<tr class="separator:a67826657e1c94c81a777ce2a3df6c9ec"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:aec71eda457b0df82372226edfc45f735"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aec71eda457b0df82372226edfc45f735"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#aec71eda457b0df82372226edfc45f735">FVID2_DF_BGR24_888</a>   ((uint32_t) 0x0024U)</td></tr>
+<tr class="memdesc:aec71eda457b0df82372226edfc45f735"><td class="mdescLeft"> </td><td class="mdescRight">BGR888 24-bit - 8-bits B, 8-bits G, 8-bits R. <br/></td></tr>
+<tr class="separator:aec71eda457b0df82372226edfc45f735"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:afc2be7884a0beb3294c6bae7fbb88078"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="afc2be7884a0beb3294c6bae7fbb88078"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#afc2be7884a0beb3294c6bae7fbb88078">FVID2_DF_XBGR24_8888</a>   ((uint32_t) 0x0025U)</td></tr>
+<tr class="memdesc:afc2be7884a0beb3294c6bae7fbb88078"><td class="mdescLeft"> </td><td class="mdescRight">xBGR888 24-bit - 8-bits B, 8-bits G, 8-bits R, 8-bit unused <br/></td></tr>
+<tr class="separator:afc2be7884a0beb3294c6bae7fbb88078"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a7f4968f909516c395b60621f6cf2347d"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a7f4968f909516c395b60621f6cf2347d"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a7f4968f909516c395b60621f6cf2347d">FVID2_DF_RGBX24_8888</a>   ((uint32_t) 0x0026U)</td></tr>
+<tr class="memdesc:a7f4968f909516c395b60621f6cf2347d"><td class="mdescLeft"> </td><td class="mdescRight">xBGR888 24-bit - 8-bits B, 8-bits G, 8-bits R, 8-bit unused <br/></td></tr>
+<tr class="separator:a7f4968f909516c395b60621f6cf2347d"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a75dc549b652933589bdc74ca7c558722"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a75dc549b652933589bdc74ca7c558722"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a75dc549b652933589bdc74ca7c558722">FVID2_DF_BGRX24_8888</a>   ((uint32_t) 0x0027U)</td></tr>
+<tr class="memdesc:a75dc549b652933589bdc74ca7c558722"><td class="mdescLeft"> </td><td class="mdescRight">xBGR888 24-bit - 8-bits B, 8-bits G, 8-bits R, 8-bit unused <br/></td></tr>
+<tr class="separator:a75dc549b652933589bdc74ca7c558722"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a3a3d5548cb11ed83586d2c69706216b2"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a3a3d5548cb11ed83586d2c69706216b2"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a3a3d5548cb11ed83586d2c69706216b2">FVID2_DF_ABGR32_8888</a>   ((uint32_t) 0x0028U)</td></tr>
+<tr class="memdesc:a3a3d5548cb11ed83586d2c69706216b2"><td class="mdescLeft"> </td><td class="mdescRight">ABGR8888 32-bit - 8-bits B, 8-bits G, 8-bits R, 8-bit Alpha . <br/></td></tr>
+<tr class="separator:a3a3d5548cb11ed83586d2c69706216b2"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a51a66504c3dfa081dd0a73d4ed9e127c"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a51a66504c3dfa081dd0a73d4ed9e127c"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a51a66504c3dfa081dd0a73d4ed9e127c">FVID2_DF_BGRA24_6666</a>   ((uint32_t) 0x0029U)</td></tr>
+<tr class="memdesc:a51a66504c3dfa081dd0a73d4ed9e127c"><td class="mdescLeft"> </td><td class="mdescRight">BGRA6666 24-bit - 6-bits B, 6-bits G, 6-bits R, 6-bit Alpha . <br/></td></tr>
+<tr class="separator:a51a66504c3dfa081dd0a73d4ed9e127c"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:aca5dd6e1728f52bbb03a9b3bf43e8a6d"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aca5dd6e1728f52bbb03a9b3bf43e8a6d"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#aca5dd6e1728f52bbb03a9b3bf43e8a6d">FVID2_DF_BGRA32_8888</a>   ((uint32_t) 0x002AU)</td></tr>
+<tr class="memdesc:aca5dd6e1728f52bbb03a9b3bf43e8a6d"><td class="mdescLeft"> </td><td class="mdescRight">BGRA8888 32-bit - 8-bits B, 8-bits G, 8-bits R, 8-bit Alpha . <br/></td></tr>
+<tr class="separator:aca5dd6e1728f52bbb03a9b3bf43e8a6d"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ae619d5684dd5fa3e87d940a509a17849"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ae619d5684dd5fa3e87d940a509a17849"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#ae619d5684dd5fa3e87d940a509a17849">FVID2_DF_BGRX32_8888</a>   ((uint32_t) 0x002BU)</td></tr>
+<tr class="memdesc:ae619d5684dd5fa3e87d940a509a17849"><td class="mdescLeft"> </td><td class="mdescRight">BGRX8888 32-bit - 8-bits B, 8-bits G, 8-bits R, 8-bit unused. <br/></td></tr>
+<tr class="separator:ae619d5684dd5fa3e87d940a509a17849"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a85f2cb500f5f931089021bb0e0ac3081"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a85f2cb500f5f931089021bb0e0ac3081"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a85f2cb500f5f931089021bb0e0ac3081">FVID2_DF_BGRA16_1555</a>   ((uint32_t) 0x002CU)</td></tr>
+<tr class="memdesc:a85f2cb500f5f931089021bb0e0ac3081"><td class="mdescLeft"> </td><td class="mdescRight">BGRA1555 16-bit - 5-bits B, 5-bits G, 5-bits R, 1-bit Alpha. <br/></td></tr>
+<tr class="separator:a85f2cb500f5f931089021bb0e0ac3081"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a2b5bec3bf23075002232ec86cf447eeb"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a2b5bec3bf23075002232ec86cf447eeb"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a2b5bec3bf23075002232ec86cf447eeb">FVID2_DF_BGRX16_1555</a>   ((uint32_t) 0x002DU)</td></tr>
+<tr class="memdesc:a2b5bec3bf23075002232ec86cf447eeb"><td class="mdescLeft"> </td><td class="mdescRight">BGRX1555 16-bit - 5-bits B, 5-bits G, 5-bits R, 1-bit unused. <br/></td></tr>
+<tr class="separator:a2b5bec3bf23075002232ec86cf447eeb"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:acdb1b99d22676ff072abe4109855df41"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="acdb1b99d22676ff072abe4109855df41"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#acdb1b99d22676ff072abe4109855df41">FVID2_DF_BGRA32_1010102</a>   ((uint32_t) 0x002EU)</td></tr>
+<tr class="memdesc:acdb1b99d22676ff072abe4109855df41"><td class="mdescLeft"> </td><td class="mdescRight">BGRA1010102 32-bit - 10-bits B, 10-bits G, 10-bits R, 2-bit Alpha. <br/></td></tr>
+<tr class="separator:acdb1b99d22676ff072abe4109855df41"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a17947044a5e1e05729b7d362e3a1eb96"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a17947044a5e1e05729b7d362e3a1eb96"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a17947044a5e1e05729b7d362e3a1eb96">FVID2_DF_BGRX32_1010102</a>   ((uint32_t) 0x002FU)</td></tr>
+<tr class="memdesc:a17947044a5e1e05729b7d362e3a1eb96"><td class="mdescLeft"> </td><td class="mdescRight">BGRX1010102 32-bit - 10-bits B, 10-bits G, 10-bits R, 2-bit unused. <br/></td></tr>
+<tr class="separator:a17947044a5e1e05729b7d362e3a1eb96"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a2a52d935ebb62b4080d77c71925f0647"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a2a52d935ebb62b4080d77c71925f0647"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a2a52d935ebb62b4080d77c71925f0647">FVID2_DF_RGBA32_1010102</a>   ((uint32_t) 0x0030U)</td></tr>
+<tr class="memdesc:a2a52d935ebb62b4080d77c71925f0647"><td class="mdescLeft"> </td><td class="mdescRight">RGBA1010102 32-bit - 10-bits B, 10-bits G, 10-bits R, 2-bit Alpha. <br/></td></tr>
+<tr class="separator:a2a52d935ebb62b4080d77c71925f0647"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a1eb85f4435bf7c1c056dd24493d3db70"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a1eb85f4435bf7c1c056dd24493d3db70"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a1eb85f4435bf7c1c056dd24493d3db70">FVID2_DF_RGBX32_1010102</a>   ((uint32_t) 0x0031U)</td></tr>
+<tr class="memdesc:a1eb85f4435bf7c1c056dd24493d3db70"><td class="mdescLeft"> </td><td class="mdescRight">RGBX1010102 32-bit - 10-bits B, 10-bits G, 10-bits R, 2-bit unused. <br/></td></tr>
+<tr class="separator:a1eb85f4435bf7c1c056dd24493d3db70"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a2f536f26da1c058f07bc094b15250050"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a2f536f26da1c058f07bc094b15250050"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a2f536f26da1c058f07bc094b15250050">FVID2_DF_BGRA64_16161616</a>   ((uint32_t) 0x0032U)</td></tr>
+<tr class="memdesc:a2f536f26da1c058f07bc094b15250050"><td class="mdescLeft"> </td><td class="mdescRight">RGBA16161616 64-bit - 16-bits B, 16-bits G, 16-bits R, 16-bit Alpha. <br/></td></tr>
+<tr class="separator:a2f536f26da1c058f07bc094b15250050"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:aee0eb933b042e4164b905743faed7fa9"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aee0eb933b042e4164b905743faed7fa9"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#aee0eb933b042e4164b905743faed7fa9">FVID2_DF_BGRX64_16161616</a>   ((uint32_t) 0x0033U)</td></tr>
+<tr class="memdesc:aee0eb933b042e4164b905743faed7fa9"><td class="mdescLeft"> </td><td class="mdescRight">BGRX16161616 64-bit - 16-bits B, 16-bits G, 16-bits R, 16-bit unused. <br/></td></tr>
+<tr class="separator:aee0eb933b042e4164b905743faed7fa9"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ac193792fc6715e083fa52deaec27b811"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ac193792fc6715e083fa52deaec27b811"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#ac193792fc6715e083fa52deaec27b811">FVID2_DF_ABGR64_16161616</a>   ((uint32_t) 0x0034U)</td></tr>
+<tr class="memdesc:ac193792fc6715e083fa52deaec27b811"><td class="mdescLeft"> </td><td class="mdescRight">ABGR16161616 64-bit - 16-bits B, 16-bits G, 16-bits R, 16-bit Alpha. <br/></td></tr>
+<tr class="separator:ac193792fc6715e083fa52deaec27b811"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a4935a7e3cfe990c9e4f24b8103084997"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a4935a7e3cfe990c9e4f24b8103084997"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a4935a7e3cfe990c9e4f24b8103084997">FVID2_DF_XBGR64_16161616</a>   ((uint32_t) 0x0035U)</td></tr>
+<tr class="memdesc:a4935a7e3cfe990c9e4f24b8103084997"><td class="mdescLeft"> </td><td class="mdescRight">XBGR16161616 64-bit - 16-bits B, 16-bits G, 16-bits R, 16-bit unused. <br/></td></tr>
+<tr class="separator:a4935a7e3cfe990c9e4f24b8103084997"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a04fa2124c8580bc7a4885df5891b7f05"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a04fa2124c8580bc7a4885df5891b7f05"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a04fa2124c8580bc7a4885df5891b7f05">FVID2_DF_BITMAP8</a>   ((uint32_t) 0x0036U)</td></tr>
+<tr class="memdesc:a04fa2124c8580bc7a4885df5891b7f05"><td class="mdescLeft"> </td><td class="mdescRight">BITMAP 8bpp. <br/></td></tr>
+<tr class="separator:a04fa2124c8580bc7a4885df5891b7f05"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a562ec66b68f6b50cdac78220daaa71c8"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a562ec66b68f6b50cdac78220daaa71c8"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a562ec66b68f6b50cdac78220daaa71c8">FVID2_DF_BITMAP4_LOWER</a>   ((uint32_t) 0x0037U)</td></tr>
+<tr class="memdesc:a562ec66b68f6b50cdac78220daaa71c8"><td class="mdescLeft"> </td><td class="mdescRight">BITMAP 4bpp lower address in CLUT. <br/></td></tr>
+<tr class="separator:a562ec66b68f6b50cdac78220daaa71c8"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a5954451e7c2dfe448e008f82a566a033"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a5954451e7c2dfe448e008f82a566a033"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a5954451e7c2dfe448e008f82a566a033">FVID2_DF_BITMAP4_UPPER</a>   ((uint32_t) 0x0038U)</td></tr>
+<tr class="memdesc:a5954451e7c2dfe448e008f82a566a033"><td class="mdescLeft"> </td><td class="mdescRight">BITMAP 4bpp upper address in CLUT. <br/></td></tr>
+<tr class="separator:a5954451e7c2dfe448e008f82a566a033"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ae5066c9514b1fe3e37ef14a2a2f15900"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ae5066c9514b1fe3e37ef14a2a2f15900"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#ae5066c9514b1fe3e37ef14a2a2f15900">FVID2_DF_BITMAP2_OFFSET0</a>   ((uint32_t) 0x0039U)</td></tr>
+<tr class="memdesc:ae5066c9514b1fe3e37ef14a2a2f15900"><td class="mdescLeft"> </td><td class="mdescRight">BITMAP 2bpp offset 0 in CLUT. <br/></td></tr>
+<tr class="separator:ae5066c9514b1fe3e37ef14a2a2f15900"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a94a59c233a6956e42313c59efb33a97a"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a94a59c233a6956e42313c59efb33a97a"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a94a59c233a6956e42313c59efb33a97a">FVID2_DF_BITMAP2_OFFSET1</a>   ((uint32_t) 0x003AU)</td></tr>
+<tr class="memdesc:a94a59c233a6956e42313c59efb33a97a"><td class="mdescLeft"> </td><td class="mdescRight">BITMAP 2bpp offset 1 in CLUT. <br/></td></tr>
+<tr class="separator:a94a59c233a6956e42313c59efb33a97a"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:aeab63d2e4c48b48bc1dc6d3067a32dd7"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aeab63d2e4c48b48bc1dc6d3067a32dd7"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#aeab63d2e4c48b48bc1dc6d3067a32dd7">FVID2_DF_BITMAP2_OFFSET2</a>   ((uint32_t) 0x003BU)</td></tr>
+<tr class="memdesc:aeab63d2e4c48b48bc1dc6d3067a32dd7"><td class="mdescLeft"> </td><td class="mdescRight">BITMAP 2bpp offset 2 in CLUT. <br/></td></tr>
+<tr class="separator:aeab63d2e4c48b48bc1dc6d3067a32dd7"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ad0516ca037fedc24412cdddf968cc350"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ad0516ca037fedc24412cdddf968cc350"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#ad0516ca037fedc24412cdddf968cc350">FVID2_DF_BITMAP2_OFFSET3</a>   ((uint32_t) 0x003CU)</td></tr>
+<tr class="memdesc:ad0516ca037fedc24412cdddf968cc350"><td class="mdescLeft"> </td><td class="mdescRight">BITMAP 2bpp offset 3 in CLUT. <br/></td></tr>
+<tr class="separator:ad0516ca037fedc24412cdddf968cc350"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a10760a07c8cf03ca9a72d02cb17113c1"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a10760a07c8cf03ca9a72d02cb17113c1"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a10760a07c8cf03ca9a72d02cb17113c1">FVID2_DF_BITMAP1_OFFSET0</a>   ((uint32_t) 0x003DU)</td></tr>
+<tr class="memdesc:a10760a07c8cf03ca9a72d02cb17113c1"><td class="mdescLeft"> </td><td class="mdescRight">BITMAP 1bpp offset 0 in CLUT. <br/></td></tr>
+<tr class="separator:a10760a07c8cf03ca9a72d02cb17113c1"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a517f2431a437bc0770fb8cf5e0cc545d"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a517f2431a437bc0770fb8cf5e0cc545d"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a517f2431a437bc0770fb8cf5e0cc545d">FVID2_DF_BITMAP1_OFFSET1</a>   ((uint32_t) 0x003EU)</td></tr>
+<tr class="memdesc:a517f2431a437bc0770fb8cf5e0cc545d"><td class="mdescLeft"> </td><td class="mdescRight">BITMAP 1bpp offset 1 in CLUT. <br/></td></tr>
+<tr class="separator:a517f2431a437bc0770fb8cf5e0cc545d"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a1f9122ed261ceb5e368d8be6781d2061"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a1f9122ed261ceb5e368d8be6781d2061"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a1f9122ed261ceb5e368d8be6781d2061">FVID2_DF_BITMAP1_OFFSET2</a>   ((uint32_t) 0x003FU)</td></tr>
+<tr class="memdesc:a1f9122ed261ceb5e368d8be6781d2061"><td class="mdescLeft"> </td><td class="mdescRight">BITMAP 1bpp offset 2 in CLUT. <br/></td></tr>
+<tr class="separator:a1f9122ed261ceb5e368d8be6781d2061"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ab85aa8ce8cbe8eb318d3446424fcac5e"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ab85aa8ce8cbe8eb318d3446424fcac5e"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#ab85aa8ce8cbe8eb318d3446424fcac5e">FVID2_DF_BITMAP1_OFFSET3</a>   ((uint32_t) 0x0040U)</td></tr>
+<tr class="memdesc:ab85aa8ce8cbe8eb318d3446424fcac5e"><td class="mdescLeft"> </td><td class="mdescRight">BITMAP 1bpp offset 3 in CLUT. <br/></td></tr>
+<tr class="separator:ab85aa8ce8cbe8eb318d3446424fcac5e"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a83d3b53838565b24257e88d2be4f3553"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a83d3b53838565b24257e88d2be4f3553"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a83d3b53838565b24257e88d2be4f3553">FVID2_DF_BITMAP1_OFFSET4</a>   ((uint32_t) 0x0041U)</td></tr>
+<tr class="memdesc:a83d3b53838565b24257e88d2be4f3553"><td class="mdescLeft"> </td><td class="mdescRight">BITMAP 1bpp offset 4 in CLUT. <br/></td></tr>
+<tr class="separator:a83d3b53838565b24257e88d2be4f3553"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ae4438daff144c2dde771ca155bd81919"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ae4438daff144c2dde771ca155bd81919"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#ae4438daff144c2dde771ca155bd81919">FVID2_DF_BITMAP1_OFFSET5</a>   ((uint32_t) 0x0042U)</td></tr>
+<tr class="memdesc:ae4438daff144c2dde771ca155bd81919"><td class="mdescLeft"> </td><td class="mdescRight">BITMAP 1bpp offset 5 in CLUT. <br/></td></tr>
+<tr class="separator:ae4438daff144c2dde771ca155bd81919"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a5f983c913420e553af0ea0bf1f258148"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a5f983c913420e553af0ea0bf1f258148"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a5f983c913420e553af0ea0bf1f258148">FVID2_DF_BITMAP1_OFFSET6</a>   ((uint32_t) 0x0043U)</td></tr>
+<tr class="memdesc:a5f983c913420e553af0ea0bf1f258148"><td class="mdescLeft"> </td><td class="mdescRight">BITMAP 1bpp offset 6 in CLUT. <br/></td></tr>
+<tr class="separator:a5f983c913420e553af0ea0bf1f258148"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a08702a9b950303fb9417a0bb30d48d13"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a08702a9b950303fb9417a0bb30d48d13"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a08702a9b950303fb9417a0bb30d48d13">FVID2_DF_BITMAP1_OFFSET7</a>   ((uint32_t) 0x0044U)</td></tr>
+<tr class="memdesc:a08702a9b950303fb9417a0bb30d48d13"><td class="mdescLeft"> </td><td class="mdescRight">BITMAP 1bpp offset 7 in CLUT. <br/></td></tr>
+<tr class="separator:a08702a9b950303fb9417a0bb30d48d13"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a234aecba82d3233c8ebf5cbb08ab4f45"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a234aecba82d3233c8ebf5cbb08ab4f45"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a234aecba82d3233c8ebf5cbb08ab4f45">FVID2_DF_BITMAP8_BGRA32</a>   ((uint32_t) 0x0045U)</td></tr>
+<tr class="memdesc:a234aecba82d3233c8ebf5cbb08ab4f45"><td class="mdescLeft"> </td><td class="mdescRight">BITMAP 8bpp BGRA32. <br/></td></tr>
+<tr class="separator:a234aecba82d3233c8ebf5cbb08ab4f45"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:abb07e628c687364e8f825ed46a1340a2"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="abb07e628c687364e8f825ed46a1340a2"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#abb07e628c687364e8f825ed46a1340a2">FVID2_DF_BITMAP4_BGRA32_LOWER</a>   ((uint32_t) 0x0046U)</td></tr>
+<tr class="memdesc:abb07e628c687364e8f825ed46a1340a2"><td class="mdescLeft"> </td><td class="mdescRight">BITMAP 4bpp BGRA32 lower address in CLUT. <br/></td></tr>
+<tr class="separator:abb07e628c687364e8f825ed46a1340a2"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:aa385922e446358686fcb9531368a2e07"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aa385922e446358686fcb9531368a2e07"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#aa385922e446358686fcb9531368a2e07">FVID2_DF_BITMAP4_BGRA32_UPPER</a>   ((uint32_t) 0x0047U)</td></tr>
+<tr class="memdesc:aa385922e446358686fcb9531368a2e07"><td class="mdescLeft"> </td><td class="mdescRight">BITMAP 4bpp BGRA32 upper address in CLUT. <br/></td></tr>
+<tr class="separator:aa385922e446358686fcb9531368a2e07"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ac0c627a8e4c7061b6699f03790ee3cf9"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ac0c627a8e4c7061b6699f03790ee3cf9"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#ac0c627a8e4c7061b6699f03790ee3cf9">FVID2_DF_BITMAP2_BGRA32_OFFSET0</a>   ((uint32_t) 0x0048U)</td></tr>
+<tr class="memdesc:ac0c627a8e4c7061b6699f03790ee3cf9"><td class="mdescLeft"> </td><td class="mdescRight">BITMAP 2bpp BGRA32 offset 0 in CLUT. <br/></td></tr>
+<tr class="separator:ac0c627a8e4c7061b6699f03790ee3cf9"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:abce9ccfc02e04c6de616bb6b0727f665"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="abce9ccfc02e04c6de616bb6b0727f665"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#abce9ccfc02e04c6de616bb6b0727f665">FVID2_DF_BITMAP2_BGRA32_OFFSET1</a>   ((uint32_t) 0x0049U)</td></tr>
+<tr class="memdesc:abce9ccfc02e04c6de616bb6b0727f665"><td class="mdescLeft"> </td><td class="mdescRight">BITMAP 2bpp BGRA32 offset 1 in CLUT. <br/></td></tr>
+<tr class="separator:abce9ccfc02e04c6de616bb6b0727f665"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a5455f16c5fb3966fc34763dc47ad235c"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a5455f16c5fb3966fc34763dc47ad235c"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a5455f16c5fb3966fc34763dc47ad235c">FVID2_DF_BITMAP2_BGRA32_OFFSET2</a>   ((uint32_t) 0x004AU)</td></tr>
+<tr class="memdesc:a5455f16c5fb3966fc34763dc47ad235c"><td class="mdescLeft"> </td><td class="mdescRight">BITMAP 2bpp BGRA32 offset 2 in CLUT. <br/></td></tr>
+<tr class="separator:a5455f16c5fb3966fc34763dc47ad235c"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a913b43554331ac260a0126874614c286"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a913b43554331ac260a0126874614c286"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a913b43554331ac260a0126874614c286">FVID2_DF_BITMAP2_BGRA32_OFFSET3</a>   ((uint32_t) 0x004BU)</td></tr>
+<tr class="memdesc:a913b43554331ac260a0126874614c286"><td class="mdescLeft"> </td><td class="mdescRight">BITMAP 2bpp BGRA32 offset 3 in CLUT. <br/></td></tr>
+<tr class="separator:a913b43554331ac260a0126874614c286"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a16db1c27d1ce932d2f040afc0d17bbdf"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a16db1c27d1ce932d2f040afc0d17bbdf"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a16db1c27d1ce932d2f040afc0d17bbdf">FVID2_DF_BITMAP1_BGRA32_OFFSET0</a>   ((uint32_t) 0x004CU)</td></tr>
+<tr class="memdesc:a16db1c27d1ce932d2f040afc0d17bbdf"><td class="mdescLeft"> </td><td class="mdescRight">BITMAP 1bpp BGRA32 offset 0 in CLUT. <br/></td></tr>
+<tr class="separator:a16db1c27d1ce932d2f040afc0d17bbdf"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a9a6b2d58b22b3fa7db0f8dffc48fe2ee"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a9a6b2d58b22b3fa7db0f8dffc48fe2ee"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a9a6b2d58b22b3fa7db0f8dffc48fe2ee">FVID2_DF_BITMAP1_BGRA32_OFFSET1</a>   ((uint32_t) 0x004DU)</td></tr>
+<tr class="memdesc:a9a6b2d58b22b3fa7db0f8dffc48fe2ee"><td class="mdescLeft"> </td><td class="mdescRight">BITMAP 1bpp BGRA32 offset 1 in CLUT. <br/></td></tr>
+<tr class="separator:a9a6b2d58b22b3fa7db0f8dffc48fe2ee"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a5364c08f0778a36a5c7ea05f0c15a793"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a5364c08f0778a36a5c7ea05f0c15a793"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a5364c08f0778a36a5c7ea05f0c15a793">FVID2_DF_BITMAP1_BGRA32_OFFSET2</a>   ((uint32_t) 0x004EU)</td></tr>
+<tr class="memdesc:a5364c08f0778a36a5c7ea05f0c15a793"><td class="mdescLeft"> </td><td class="mdescRight">BITMAP 1bpp BGRA32 offset 2 in CLUT. <br/></td></tr>
+<tr class="separator:a5364c08f0778a36a5c7ea05f0c15a793"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:aece03427fdb8c77dbc63a515c4b64698"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aece03427fdb8c77dbc63a515c4b64698"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#aece03427fdb8c77dbc63a515c4b64698">FVID2_DF_BITMAP1_BGRA32_OFFSET3</a>   ((uint32_t) 0x004FU)</td></tr>
+<tr class="memdesc:aece03427fdb8c77dbc63a515c4b64698"><td class="mdescLeft"> </td><td class="mdescRight">BITMAP 1bpp BGRA32 offset 3 in CLUT. <br/></td></tr>
+<tr class="separator:aece03427fdb8c77dbc63a515c4b64698"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a44918b4b286a3edc045e5ad30cd7670c"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a44918b4b286a3edc045e5ad30cd7670c"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a44918b4b286a3edc045e5ad30cd7670c">FVID2_DF_BITMAP1_BGRA32_OFFSET4</a>   ((uint32_t) 0x0050U)</td></tr>
+<tr class="memdesc:a44918b4b286a3edc045e5ad30cd7670c"><td class="mdescLeft"> </td><td class="mdescRight">BITMAP 1bpp BGRA32 offset 4 in CLUT. <br/></td></tr>
+<tr class="separator:a44918b4b286a3edc045e5ad30cd7670c"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a2d3c0c4bdd622258b14b03dca8d8b549"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a2d3c0c4bdd622258b14b03dca8d8b549"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a2d3c0c4bdd622258b14b03dca8d8b549">FVID2_DF_BITMAP1_BGRA32_OFFSET5</a>   ((uint32_t) 0x0051U)</td></tr>
+<tr class="memdesc:a2d3c0c4bdd622258b14b03dca8d8b549"><td class="mdescLeft"> </td><td class="mdescRight">BITMAP 1bpp BGRA32 offset 5 in CLUT. <br/></td></tr>
+<tr class="separator:a2d3c0c4bdd622258b14b03dca8d8b549"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:af069f3d015b1729f8844290c18da3e5f"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="af069f3d015b1729f8844290c18da3e5f"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#af069f3d015b1729f8844290c18da3e5f">FVID2_DF_BITMAP1_BGRA32_OFFSET6</a>   ((uint32_t) 0x0052U)</td></tr>
+<tr class="memdesc:af069f3d015b1729f8844290c18da3e5f"><td class="mdescLeft"> </td><td class="mdescRight">BITMAP 1bpp BGRA32 offset 6 in CLUT. <br/></td></tr>
+<tr class="separator:af069f3d015b1729f8844290c18da3e5f"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a69e192ccb29f33b09aecd8135d6f5842"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a69e192ccb29f33b09aecd8135d6f5842"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a69e192ccb29f33b09aecd8135d6f5842">FVID2_DF_BITMAP1_BGRA32_OFFSET7</a>   ((uint32_t) 0x0053U)</td></tr>
+<tr class="memdesc:a69e192ccb29f33b09aecd8135d6f5842"><td class="mdescLeft"> </td><td class="mdescRight">BITMAP 1bpp BGRA32 offset 7 in CLUT. <br/></td></tr>
+<tr class="separator:a69e192ccb29f33b09aecd8135d6f5842"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a18d65e217800bff159d5d1b3c98181a9"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a18d65e217800bff159d5d1b3c98181a9"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a18d65e217800bff159d5d1b3c98181a9">FVID2_DF_BAYER_RAW</a>   ((uint32_t) 0x0054U)</td></tr>
+<tr class="memdesc:a18d65e217800bff159d5d1b3c98181a9"><td class="mdescLeft"> </td><td class="mdescRight">Bayer pattern. <br/></td></tr>
+<tr class="separator:a18d65e217800bff159d5d1b3c98181a9"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:acbdc73f8daeb86579c39393467757490"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="acbdc73f8daeb86579c39393467757490"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#acbdc73f8daeb86579c39393467757490">FVID2_DF_BAYER_GRBG</a>   ((uint32_t) 0x0055U)</td></tr>
+<tr class="memdesc:acbdc73f8daeb86579c39393467757490"><td class="mdescLeft"> </td><td class="mdescRight">Raw bayer data color pattern G R G R ... B G B G ... <br/></td></tr>
+<tr class="separator:acbdc73f8daeb86579c39393467757490"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a0dbdb7ed0808e6aff08211ef0232d313"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a0dbdb7ed0808e6aff08211ef0232d313"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a0dbdb7ed0808e6aff08211ef0232d313">FVID2_DF_BAYER_RGGB</a>   ((uint32_t) 0x0056U)</td></tr>
+<tr class="memdesc:a0dbdb7ed0808e6aff08211ef0232d313"><td class="mdescLeft"> </td><td class="mdescRight">Raw bayer data color pattern R G G R ... G B G B ... <br/></td></tr>
+<tr class="separator:a0dbdb7ed0808e6aff08211ef0232d313"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a48195789c241dc8820128785eea7c445"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a48195789c241dc8820128785eea7c445"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a48195789c241dc8820128785eea7c445">FVID2_DF_BAYER_BGGR</a>   ((uint32_t) 0x0057U)</td></tr>
+<tr class="memdesc:a48195789c241dc8820128785eea7c445"><td class="mdescLeft"> </td><td class="mdescRight">Raw bayer data color pattern B G B G ... G B G B ... <br/></td></tr>
+<tr class="separator:a48195789c241dc8820128785eea7c445"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a5447b8962dc20cd0d4ab6edcb93f25b5"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a5447b8962dc20cd0d4ab6edcb93f25b5"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a5447b8962dc20cd0d4ab6edcb93f25b5">FVID2_DF_BAYER_GBRG</a>   ((uint32_t) 0x0058U)</td></tr>
+<tr class="memdesc:a5447b8962dc20cd0d4ab6edcb93f25b5"><td class="mdescLeft"> </td><td class="mdescRight">Raw bayer data color pattern G B G B ... R R R G ... <br/></td></tr>
+<tr class="separator:a5447b8962dc20cd0d4ab6edcb93f25b5"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a8d14ca09f0d0ccf2eb21590178007020"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a8d14ca09f0d0ccf2eb21590178007020"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a8d14ca09f0d0ccf2eb21590178007020">FVID2_DF_RAW_VBI</a>   ((uint32_t) 0x0059U)</td></tr>
+<tr class="memdesc:a8d14ca09f0d0ccf2eb21590178007020"><td class="mdescLeft"> </td><td class="mdescRight">Raw VBI data. <br/></td></tr>
+<tr class="separator:a8d14ca09f0d0ccf2eb21590178007020"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a62f6e76115ac0629eafb3349f1acbef9"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a62f6e76115ac0629eafb3349f1acbef9"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a62f6e76115ac0629eafb3349f1acbef9">FVID2_DF_RAW24</a>   ((uint32_t) 0x005AU)</td></tr>
+<tr class="memdesc:a62f6e76115ac0629eafb3349f1acbef9"><td class="mdescLeft"> </td><td class="mdescRight">24 bit raw-data. <br/></td></tr>
+<tr class="separator:a62f6e76115ac0629eafb3349f1acbef9"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:abfe70502360c9fb38239cbfc95a002d2"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="abfe70502360c9fb38239cbfc95a002d2"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#abfe70502360c9fb38239cbfc95a002d2">FVID2_DF_RAW16</a>   ((uint32_t) 0x005BU)</td></tr>
+<tr class="memdesc:abfe70502360c9fb38239cbfc95a002d2"><td class="mdescLeft"> </td><td class="mdescRight">16 bit raw-data. <br/></td></tr>
+<tr class="separator:abfe70502360c9fb38239cbfc95a002d2"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a7cf29dde337e998d8cfb19e9a0859144"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a7cf29dde337e998d8cfb19e9a0859144"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a7cf29dde337e998d8cfb19e9a0859144">FVID2_DF_RAW08</a>   ((uint32_t) 0x005CU)</td></tr>
+<tr class="memdesc:a7cf29dde337e998d8cfb19e9a0859144"><td class="mdescLeft"> </td><td class="mdescRight">8 bit raw-data. <br/></td></tr>
+<tr class="separator:a7cf29dde337e998d8cfb19e9a0859144"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:abaac151f338559b161ab644940a3c026"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="abaac151f338559b161ab644940a3c026"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#abaac151f338559b161ab644940a3c026">FVID2_DF_MISC</a>   ((uint32_t) 0x005DU)</td></tr>
+<tr class="memdesc:abaac151f338559b161ab644940a3c026"><td class="mdescLeft"> </td><td class="mdescRight">For future purpose. <br/></td></tr>
+<tr class="separator:abaac151f338559b161ab644940a3c026"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a467d4182b255081bba531e681e2f3e73"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a467d4182b255081bba531e681e2f3e73"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a467d4182b255081bba531e681e2f3e73">FVID2_DF_BITMAP4</a>   ((uint32_t) <a class="el" href="csl__fvid2__data_types_8h.html#a562ec66b68f6b50cdac78220daaa71c8">FVID2_DF_BITMAP4_LOWER</a>)</td></tr>
+<tr class="memdesc:a467d4182b255081bba531e681e2f3e73"><td class="mdescLeft"> </td><td class="mdescRight">BITMAP 4bpp. <br/></td></tr>
+<tr class="separator:a467d4182b255081bba531e681e2f3e73"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a7977b000d6a911c5629fca8f9fa27f2b"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a7977b000d6a911c5629fca8f9fa27f2b"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a7977b000d6a911c5629fca8f9fa27f2b">FVID2_DF_BITMAP2</a>   ((uint32_t) <a class="el" href="csl__fvid2__data_types_8h.html#ae5066c9514b1fe3e37ef14a2a2f15900">FVID2_DF_BITMAP2_OFFSET0</a>)</td></tr>
+<tr class="memdesc:a7977b000d6a911c5629fca8f9fa27f2b"><td class="mdescLeft"> </td><td class="mdescRight">BITMAP 2bpp. <br/></td></tr>
+<tr class="separator:a7977b000d6a911c5629fca8f9fa27f2b"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:aeed99cb6e59342810b3cdfeb8e6d3c39"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aeed99cb6e59342810b3cdfeb8e6d3c39"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#aeed99cb6e59342810b3cdfeb8e6d3c39">FVID2_DF_BITMAP1</a>   ((uint32_t) <a class="el" href="csl__fvid2__data_types_8h.html#a10760a07c8cf03ca9a72d02cb17113c1">FVID2_DF_BITMAP1_OFFSET0</a>)</td></tr>
+<tr class="memdesc:aeed99cb6e59342810b3cdfeb8e6d3c39"><td class="mdescLeft"> </td><td class="mdescRight">BITMAP 1bpp. <br/></td></tr>
+<tr class="separator:aeed99cb6e59342810b3cdfeb8e6d3c39"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a8eadae0ebd94292739fe9c0d11c9f517"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a8eadae0ebd94292739fe9c0d11c9f517"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a8eadae0ebd94292739fe9c0d11c9f517">FVID2_DF_RAW06</a>   ((uint32_t) 0x5EU)</td></tr>
+<tr class="memdesc:a8eadae0ebd94292739fe9c0d11c9f517"><td class="mdescLeft"> </td><td class="mdescRight">6 bit raw-data. <br/></td></tr>
+<tr class="separator:a8eadae0ebd94292739fe9c0d11c9f517"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a0d265f5ce87c772a825aa20eaded3bf4"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a0d265f5ce87c772a825aa20eaded3bf4"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a0d265f5ce87c772a825aa20eaded3bf4">FVID2_DF_RAW07</a>   ((uint32_t) 0x5FU)</td></tr>
+<tr class="memdesc:a0d265f5ce87c772a825aa20eaded3bf4"><td class="mdescLeft"> </td><td class="mdescRight">7 bit raw-data. <br/></td></tr>
+<tr class="separator:a0d265f5ce87c772a825aa20eaded3bf4"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a27de8f0b14e945415c1a5fe93d9e9c04"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a27de8f0b14e945415c1a5fe93d9e9c04"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a27de8f0b14e945415c1a5fe93d9e9c04">FVID2_DF_RAW10</a>   ((uint32_t) 0x60U)</td></tr>
+<tr class="memdesc:a27de8f0b14e945415c1a5fe93d9e9c04"><td class="mdescLeft"> </td><td class="mdescRight">10 bit raw-data. <br/></td></tr>
+<tr class="separator:a27de8f0b14e945415c1a5fe93d9e9c04"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:af1dd36366abbb08498954d1ed9fd43d6"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="af1dd36366abbb08498954d1ed9fd43d6"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#af1dd36366abbb08498954d1ed9fd43d6">FVID2_DF_RAW12</a>   ((uint32_t) 0x61U)</td></tr>
+<tr class="memdesc:af1dd36366abbb08498954d1ed9fd43d6"><td class="mdescLeft"> </td><td class="mdescRight">12 bit raw-data. <br/></td></tr>
+<tr class="separator:af1dd36366abbb08498954d1ed9fd43d6"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:aebb3c3edf491f97c1778bff2816de59a"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aebb3c3edf491f97c1778bff2816de59a"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#aebb3c3edf491f97c1778bff2816de59a">FVID2_DF_RAW14</a>   ((uint32_t) 0x62U)</td></tr>
+<tr class="memdesc:aebb3c3edf491f97c1778bff2816de59a"><td class="mdescLeft"> </td><td class="mdescRight">14 bit raw-data. <br/></td></tr>
+<tr class="separator:aebb3c3edf491f97c1778bff2816de59a"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ac1759a5faefa88199521570e8a59b5cb"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ac1759a5faefa88199521570e8a59b5cb"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#ac1759a5faefa88199521570e8a59b5cb">FVID2_DF_JPEG1_INTERCHANGE</a>   ((uint32_t) 0x63U)</td></tr>
+<tr class="memdesc:ac1759a5faefa88199521570e8a59b5cb"><td class="mdescLeft"> </td><td class="mdescRight">JPEG INTERCHANGE data. <br/></td></tr>
+<tr class="separator:ac1759a5faefa88199521570e8a59b5cb"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a8d85099bf344b7ea9620745de131ecf7"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a8d85099bf344b7ea9620745de131ecf7"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a8d85099bf344b7ea9620745de131ecf7">FVID2_DF_JPEG2_JFIF</a>   ((uint32_t) 0x64U)</td></tr>
+<tr class="memdesc:a8d85099bf344b7ea9620745de131ecf7"><td class="mdescLeft"> </td><td class="mdescRight">JPEG2 JFIF data. <br/></td></tr>
+<tr class="separator:a8d85099bf344b7ea9620745de131ecf7"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a4cbe264631c47691ac45d60960ed76e1"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a4cbe264631c47691ac45d60960ed76e1"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a4cbe264631c47691ac45d60960ed76e1">FVID2_DF_JPEG3_EXIF</a>   ((uint32_t) 0x65U)</td></tr>
+<tr class="memdesc:a4cbe264631c47691ac45d60960ed76e1"><td class="mdescLeft"> </td><td class="mdescRight">JPEG3 EXIF data. <br/></td></tr>
+<tr class="separator:a4cbe264631c47691ac45d60960ed76e1"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a221e61fc3bb6e12776da02c4119130bf"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a221e61fc3bb6e12776da02c4119130bf"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a221e61fc3bb6e12776da02c4119130bf">FVID2_DF_DPCM_10_8_10_PRED1</a>   ((uint32_t) 0x66U)</td></tr>
+<tr class="memdesc:a221e61fc3bb6e12776da02c4119130bf"><td class="mdescLeft"> </td><td class="mdescRight">DPCM 10-8-10 PRED1 data. <br/></td></tr>
+<tr class="separator:a221e61fc3bb6e12776da02c4119130bf"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a287d72df32d2425f8d8ef71c50331652"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a287d72df32d2425f8d8ef71c50331652"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a287d72df32d2425f8d8ef71c50331652">FVID2_DF_DPCM_10_8_10_PRED2</a>   ((uint32_t) 0x67U)</td></tr>
+<tr class="memdesc:a287d72df32d2425f8d8ef71c50331652"><td class="mdescLeft"> </td><td class="mdescRight">DPCM 10-8-10 PRED2 data. <br/></td></tr>
+<tr class="separator:a287d72df32d2425f8d8ef71c50331652"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a3bcee12fd066fdd9b17808b1a28e8d4f"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a3bcee12fd066fdd9b17808b1a28e8d4f"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a3bcee12fd066fdd9b17808b1a28e8d4f">FVID2_DF_DPCM_10_7_10_PRED1</a>   ((uint32_t) 0x68U)</td></tr>
+<tr class="memdesc:a3bcee12fd066fdd9b17808b1a28e8d4f"><td class="mdescLeft"> </td><td class="mdescRight">DPCM 10-7-10 PRED1 data. <br/></td></tr>
+<tr class="separator:a3bcee12fd066fdd9b17808b1a28e8d4f"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a68873b46ba5da2eddd59fbf27be21173"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a68873b46ba5da2eddd59fbf27be21173"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a68873b46ba5da2eddd59fbf27be21173">FVID2_DF_DPCM_10_7_10_PRED2</a>   ((uint32_t) 0x69U)</td></tr>
+<tr class="memdesc:a68873b46ba5da2eddd59fbf27be21173"><td class="mdescLeft"> </td><td class="mdescRight">DPCM 10-7-10 PRED2 data. <br/></td></tr>
+<tr class="separator:a68873b46ba5da2eddd59fbf27be21173"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:aa69a34c5646c43e68db8bfdf0702b576"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aa69a34c5646c43e68db8bfdf0702b576"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#aa69a34c5646c43e68db8bfdf0702b576">FVID2_DF_DPCM_10_6_10_PRED1</a>   ((uint32_t) 0x6AU)</td></tr>
+<tr class="memdesc:aa69a34c5646c43e68db8bfdf0702b576"><td class="mdescLeft"> </td><td class="mdescRight">DPCM 10-6-10 PRED1 data. <br/></td></tr>
+<tr class="separator:aa69a34c5646c43e68db8bfdf0702b576"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ad48229056835fd87fa9bc35110f8dcc3"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ad48229056835fd87fa9bc35110f8dcc3"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#ad48229056835fd87fa9bc35110f8dcc3">FVID2_DF_DPCM_10_6_10_PRED2</a>   ((uint32_t) 0x6BU)</td></tr>
+<tr class="memdesc:ad48229056835fd87fa9bc35110f8dcc3"><td class="mdescLeft"> </td><td class="mdescRight">DPCM 10-6-10 PRED2 data. <br/></td></tr>
+<tr class="separator:ad48229056835fd87fa9bc35110f8dcc3"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ac7fced6538f6fcfbcccee27d61ab20c6"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ac7fced6538f6fcfbcccee27d61ab20c6"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#ac7fced6538f6fcfbcccee27d61ab20c6">FVID2_DF_DPCM_12_8_10_PRED1</a>   ((uint32_t) 0x6CU)</td></tr>
+<tr class="memdesc:ac7fced6538f6fcfbcccee27d61ab20c6"><td class="mdescLeft"> </td><td class="mdescRight">DPCM 12-8-10 PRED1 data. <br/></td></tr>
+<tr class="separator:ac7fced6538f6fcfbcccee27d61ab20c6"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a60a0b29846c75560d63df548611fa306"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a60a0b29846c75560d63df548611fa306"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a60a0b29846c75560d63df548611fa306">FVID2_DF_DPCM_12_8_10_PRED2</a>   ((uint32_t) 0x6DU)</td></tr>
+<tr class="memdesc:a60a0b29846c75560d63df548611fa306"><td class="mdescLeft"> </td><td class="mdescRight">DPCM 12-8-10 PRED2 data. <br/></td></tr>
+<tr class="separator:a60a0b29846c75560d63df548611fa306"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ad00ef97dfa923119ae7a79e8df71286f"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ad00ef97dfa923119ae7a79e8df71286f"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#ad00ef97dfa923119ae7a79e8df71286f">FVID2_DF_DPCM_12_7_10_PRED1</a>   ((uint32_t) 0x6EU)</td></tr>
+<tr class="memdesc:ad00ef97dfa923119ae7a79e8df71286f"><td class="mdescLeft"> </td><td class="mdescRight">DPCM 12-7-10 PRED1 data. <br/></td></tr>
+<tr class="separator:ad00ef97dfa923119ae7a79e8df71286f"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:aca742efce1f8753b8a0ac553d072c321"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aca742efce1f8753b8a0ac553d072c321"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#aca742efce1f8753b8a0ac553d072c321">FVID2_DF_DPCM_12_7_10_PRED2</a>   ((uint32_t) 0x6FU)</td></tr>
+<tr class="memdesc:aca742efce1f8753b8a0ac553d072c321"><td class="mdescLeft"> </td><td class="mdescRight">DPCM 12-7-10 PRED2 data. <br/></td></tr>
+<tr class="separator:aca742efce1f8753b8a0ac553d072c321"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ac59e7c2a55726e4f70d8b4a3887591bc"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ac59e7c2a55726e4f70d8b4a3887591bc"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#ac59e7c2a55726e4f70d8b4a3887591bc">FVID2_DF_DPCM_12_6_10_PRED1</a>   ((uint32_t) 0x70U)</td></tr>
+<tr class="memdesc:ac59e7c2a55726e4f70d8b4a3887591bc"><td class="mdescLeft"> </td><td class="mdescRight">DPCM 12-6-10 PRED1 data. <br/></td></tr>
+<tr class="separator:ac59e7c2a55726e4f70d8b4a3887591bc"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a5efa0312778106da777f0f87d346be8c"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a5efa0312778106da777f0f87d346be8c"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a5efa0312778106da777f0f87d346be8c">FVID2_DF_DPCM_12_6_10_PRED2</a>   ((uint32_t) 0x71U)</td></tr>
+<tr class="memdesc:a5efa0312778106da777f0f87d346be8c"><td class="mdescLeft"> </td><td class="mdescRight">DPCM 12-6-10 PRED2 data. <br/></td></tr>
+<tr class="separator:a5efa0312778106da777f0f87d346be8c"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a9d95da374dde11173aacdd49bf572d2d"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a9d95da374dde11173aacdd49bf572d2d"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a9d95da374dde11173aacdd49bf572d2d">FVID2_DF_BGR16_565_A8</a>   ((uint32_t) 0x72U)</td></tr>
+<tr class="memdesc:a9d95da374dde11173aacdd49bf572d2d"><td class="mdescLeft"> </td><td class="mdescRight">BGR565 16-bit - 5-bits B, 6-bits G, 5-bits R. Alpha 8-bits another plane. <br/></td></tr>
+<tr class="separator:a9d95da374dde11173aacdd49bf572d2d"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ac890be0c77887f47a9ee672a0e2c3b68"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ac890be0c77887f47a9ee672a0e2c3b68"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#ac890be0c77887f47a9ee672a0e2c3b68">FVID2_DF_RGB16_565_A8</a>   ((uint32_t) 0x73U)</td></tr>
+<tr class="memdesc:ac890be0c77887f47a9ee672a0e2c3b68"><td class="mdescLeft"> </td><td class="mdescRight">RGB565 16-bit - 5-bits R, 6-bits G, 5-bits B. Alpha 8-bits another plane. <br/></td></tr>
+<tr class="separator:ac890be0c77887f47a9ee672a0e2c3b68"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a5ea6a8aa70091892dd2d8dfc4eb87509"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a5ea6a8aa70091892dd2d8dfc4eb87509"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a5ea6a8aa70091892dd2d8dfc4eb87509">FVID2_DF_LUMA_ONLY</a>   ((uint32_t) 0x74U)</td></tr>
+<tr class="memdesc:a5ea6a8aa70091892dd2d8dfc4eb87509"><td class="mdescLeft"> </td><td class="mdescRight">Luma only data for YUV data format. <br/></td></tr>
+<tr class="separator:a5ea6a8aa70091892dd2d8dfc4eb87509"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a2ecc2ac5f7ca93fb4459fec68ac628b7"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a2ecc2ac5f7ca93fb4459fec68ac628b7"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a2ecc2ac5f7ca93fb4459fec68ac628b7">FVID2_DF_CHROMA_ONLY</a>   ((uint32_t) 0x75U)</td></tr>
+<tr class="memdesc:a2ecc2ac5f7ca93fb4459fec68ac628b7"><td class="mdescLeft"> </td><td class="mdescRight">Chroma only data for YUV data format. <br/></td></tr>
+<tr class="separator:a2ecc2ac5f7ca93fb4459fec68ac628b7"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a70edee686b7e231560048424e7d48ffa"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a70edee686b7e231560048424e7d48ffa"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a70edee686b7e231560048424e7d48ffa">FVID2_DF_RGB24_888_PLANAR</a>   ((uint32_t) 0x76U)</td></tr>
+<tr class="memdesc:a70edee686b7e231560048424e7d48ffa"><td class="mdescLeft"> </td><td class="mdescRight">RGB888 planar format data format. <br/></td></tr>
+<tr class="separator:a70edee686b7e231560048424e7d48ffa"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a6d1db62d4c8a945fa2c2f1c1ff54b71c"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a6d1db62d4c8a945fa2c2f1c1ff54b71c"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a6d1db62d4c8a945fa2c2f1c1ff54b71c">FVID2_DF_INVALID</a>   ((uint32_t) 0x00FFU)</td></tr>
+<tr class="memdesc:a6d1db62d4c8a945fa2c2f1c1ff54b71c"><td class="mdescLeft"> </td><td class="mdescRight">Invalid data format. Could be used to initialize variables. <br/></td></tr>
+<tr class="separator:a6d1db62d4c8a945fa2c2f1c1ff54b71c"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a9f5096b017d15ffecdcc0990fd1b031a"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a9f5096b017d15ffecdcc0990fd1b031a"></a>
+typedef uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a9f5096b017d15ffecdcc0990fd1b031a">Fvid2_DataFormat</a></td></tr>
+<tr class="memdesc:a9f5096b017d15ffecdcc0990fd1b031a"><td class="mdescLeft"> </td><td class="mdescRight">YUV 422 Interleaved format - UYVY. <br/></td></tr>
+<tr class="separator:a9f5096b017d15ffecdcc0990fd1b031a"><td class="memSeparator" colspan="2"> </td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
+Scan format</h2></td></tr>
+<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrp6498bace51374185ac239d2570b977ff"></a><a class="anchor" id="Fvid2_ScanFormat"></a></p>
+</td></tr>
+<tr class="memitem:ad10493ed6f290f7fa0675a265b2c07b2"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ad10493ed6f290f7fa0675a265b2c07b2"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#ad10493ed6f290f7fa0675a265b2c07b2">FVID2_SF_INTERLACED</a>   ((uint32_t) 0x00U)</td></tr>
+<tr class="memdesc:ad10493ed6f290f7fa0675a265b2c07b2"><td class="mdescLeft"> </td><td class="mdescRight">Interlaced mode. <br/></td></tr>
+<tr class="separator:ad10493ed6f290f7fa0675a265b2c07b2"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ad0541a876e164776093a922da96e0439"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ad0541a876e164776093a922da96e0439"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#ad0541a876e164776093a922da96e0439">FVID2_SF_PROGRESSIVE</a>   ((uint32_t) 0x01U)</td></tr>
+<tr class="memdesc:ad0541a876e164776093a922da96e0439"><td class="mdescLeft"> </td><td class="mdescRight">Progressive mode. <br/></td></tr>
+<tr class="separator:ad0541a876e164776093a922da96e0439"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a5cc4a5eb1a0fdd03b5fe97f14ba39965"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a5cc4a5eb1a0fdd03b5fe97f14ba39965"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a5cc4a5eb1a0fdd03b5fe97f14ba39965">FVID2_SF_MAX</a>   ((uint32_t) 0x02U)</td></tr>
+<tr class="memdesc:a5cc4a5eb1a0fdd03b5fe97f14ba39965"><td class="mdescLeft"> </td><td class="mdescRight">Used by driver for validating the input parameters. <br/></td></tr>
+<tr class="separator:a5cc4a5eb1a0fdd03b5fe97f14ba39965"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:af5dfad95adb11f1220c13a37564b706e"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="af5dfad95adb11f1220c13a37564b706e"></a>
+typedef uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#af5dfad95adb11f1220c13a37564b706e">Fvid2_ScanFormat</a></td></tr>
+<tr class="memdesc:af5dfad95adb11f1220c13a37564b706e"><td class="mdescLeft"> </td><td class="mdescRight">Interlaced mode. <br/></td></tr>
+<tr class="separator:af5dfad95adb11f1220c13a37564b706e"><td class="memSeparator" colspan="2"> </td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
+Video standards</h2></td></tr>
+<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrp28cea0893d6996ccacc298cbe3cd62b7"></a><a class="anchor" id="Fvid2_Standard"></a></p>
+</td></tr>
+<tr class="memitem:a508515b25947ede0cb5c03afc572f56d"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a508515b25947ede0cb5c03afc572f56d"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a508515b25947ede0cb5c03afc572f56d">FVID2_STD_NTSC</a>   ((uint32_t) 0x00U)</td></tr>
+<tr class="memdesc:a508515b25947ede0cb5c03afc572f56d"><td class="mdescLeft"> </td><td class="mdescRight">720x480 30FPS interlaced NTSC standard. <br/></td></tr>
+<tr class="separator:a508515b25947ede0cb5c03afc572f56d"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a7bd496bf85b4038f0fd0c841b741e968"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a7bd496bf85b4038f0fd0c841b741e968"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a7bd496bf85b4038f0fd0c841b741e968">FVID2_STD_PAL</a>   ((uint32_t) 0x01U)</td></tr>
+<tr class="memdesc:a7bd496bf85b4038f0fd0c841b741e968"><td class="mdescLeft"> </td><td class="mdescRight">720x576 30FPS interlaced PAL standard. <br/></td></tr>
+<tr class="separator:a7bd496bf85b4038f0fd0c841b741e968"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:af725d5147e849a32f0b1eb27d9c769e6"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="af725d5147e849a32f0b1eb27d9c769e6"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#af725d5147e849a32f0b1eb27d9c769e6">FVID2_STD_480I</a>   ((uint32_t) 0x02U)</td></tr>
+<tr class="memdesc:af725d5147e849a32f0b1eb27d9c769e6"><td class="mdescLeft"> </td><td class="mdescRight">720x480 30FPS interlaced SD standard. <br/></td></tr>
+<tr class="separator:af725d5147e849a32f0b1eb27d9c769e6"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a7f961f37c4aa079e0ca408d1d421437a"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a7f961f37c4aa079e0ca408d1d421437a"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a7f961f37c4aa079e0ca408d1d421437a">FVID2_STD_576I</a>   ((uint32_t) 0x03U)</td></tr>
+<tr class="memdesc:a7f961f37c4aa079e0ca408d1d421437a"><td class="mdescLeft"> </td><td class="mdescRight">720x576 30FPS interlaced SD standard. <br/></td></tr>
+<tr class="separator:a7f961f37c4aa079e0ca408d1d421437a"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:acd4ae0f475e71e394e924b8b6f213e52"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="acd4ae0f475e71e394e924b8b6f213e52"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#acd4ae0f475e71e394e924b8b6f213e52">FVID2_STD_CIF</a>   ((uint32_t) 0x04U)</td></tr>
+<tr class="memdesc:acd4ae0f475e71e394e924b8b6f213e52"><td class="mdescLeft"> </td><td class="mdescRight">Interlaced, 360x120 per field NTSC, 360x144 per field PAL. <br/></td></tr>
+<tr class="separator:acd4ae0f475e71e394e924b8b6f213e52"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a2b7bdf54fd82989b7c6e0461b945efdc"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a2b7bdf54fd82989b7c6e0461b945efdc"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a2b7bdf54fd82989b7c6e0461b945efdc">FVID2_STD_HALF_D1</a>   ((uint32_t) 0x05U)</td></tr>
+<tr class="memdesc:a2b7bdf54fd82989b7c6e0461b945efdc"><td class="mdescLeft"> </td><td class="mdescRight">Interlaced, 360x240 per field NTSC, 360x288 per field PAL. <br/></td></tr>
+<tr class="separator:a2b7bdf54fd82989b7c6e0461b945efdc"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a29d79e852429936a25f9282cf335d48c"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a29d79e852429936a25f9282cf335d48c"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a29d79e852429936a25f9282cf335d48c">FVID2_STD_D1</a>   ((uint32_t) 0x06U)</td></tr>
+<tr class="memdesc:a29d79e852429936a25f9282cf335d48c"><td class="mdescLeft"> </td><td class="mdescRight">Interlaced, 720x240 per field NTSC, 720x288 per field PAL. <br/></td></tr>
+<tr class="separator:a29d79e852429936a25f9282cf335d48c"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:abad8059c7e559059445a38172ef12fdc"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="abad8059c7e559059445a38172ef12fdc"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#abad8059c7e559059445a38172ef12fdc">FVID2_STD_480P</a>   ((uint32_t) 0x07U)</td></tr>
+<tr class="memdesc:abad8059c7e559059445a38172ef12fdc"><td class="mdescLeft"> </td><td class="mdescRight">720x480 60FPS progressive ED standard. <br/></td></tr>
+<tr class="separator:abad8059c7e559059445a38172ef12fdc"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a6d55a81370bd468d1fad62c7b34f35f9"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a6d55a81370bd468d1fad62c7b34f35f9"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a6d55a81370bd468d1fad62c7b34f35f9">FVID2_STD_576P</a>   ((uint32_t) 0x08U)</td></tr>
+<tr class="memdesc:a6d55a81370bd468d1fad62c7b34f35f9"><td class="mdescLeft"> </td><td class="mdescRight">720x576 60FPS progressive ED standard. <br/></td></tr>
+<tr class="separator:a6d55a81370bd468d1fad62c7b34f35f9"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a6bb35a8b1ceb84436db49019d7572df1"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a6bb35a8b1ceb84436db49019d7572df1"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a6bb35a8b1ceb84436db49019d7572df1">FVID2_STD_720P_60</a>   ((uint32_t) 0x09U)</td></tr>
+<tr class="memdesc:a6bb35a8b1ceb84436db49019d7572df1"><td class="mdescLeft"> </td><td class="mdescRight">1280x720 60FPS progressive HD standard. <br/></td></tr>
+<tr class="separator:a6bb35a8b1ceb84436db49019d7572df1"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a9b394349cded10b8af057ff5940646eb"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a9b394349cded10b8af057ff5940646eb"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a9b394349cded10b8af057ff5940646eb">FVID2_STD_720P_50</a>   ((uint32_t) 0x0AU)</td></tr>
+<tr class="memdesc:a9b394349cded10b8af057ff5940646eb"><td class="mdescLeft"> </td><td class="mdescRight">1280x720 50FPS progressive HD standard. <br/></td></tr>
+<tr class="separator:a9b394349cded10b8af057ff5940646eb"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:aa26f238860774149d2588be37d7bc59d"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aa26f238860774149d2588be37d7bc59d"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#aa26f238860774149d2588be37d7bc59d">FVID2_STD_1080I_60</a>   ((uint32_t) 0x0BU)</td></tr>
+<tr class="memdesc:aa26f238860774149d2588be37d7bc59d"><td class="mdescLeft"> </td><td class="mdescRight">1920x1080 30FPS interlaced HD standard. <br/></td></tr>
+<tr class="separator:aa26f238860774149d2588be37d7bc59d"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ad03201d7eaefc365e9669e563c8943b9"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ad03201d7eaefc365e9669e563c8943b9"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#ad03201d7eaefc365e9669e563c8943b9">FVID2_STD_1080I_50</a>   ((uint32_t) 0x0CU)</td></tr>
+<tr class="memdesc:ad03201d7eaefc365e9669e563c8943b9"><td class="mdescLeft"> </td><td class="mdescRight">1920x1080 50FPS interlaced HD standard. <br/></td></tr>
+<tr class="separator:ad03201d7eaefc365e9669e563c8943b9"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a68e822d86ea54f7bc4b4cbf7f61e5245"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a68e822d86ea54f7bc4b4cbf7f61e5245"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a68e822d86ea54f7bc4b4cbf7f61e5245">FVID2_STD_1080P_60</a>   ((uint32_t) 0x0DU)</td></tr>
+<tr class="memdesc:a68e822d86ea54f7bc4b4cbf7f61e5245"><td class="mdescLeft"> </td><td class="mdescRight">1920x1080 60FPS progressive HD standard. <br/></td></tr>
+<tr class="separator:a68e822d86ea54f7bc4b4cbf7f61e5245"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:aea1694ce11428345dfe3aa40830c45f9"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aea1694ce11428345dfe3aa40830c45f9"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#aea1694ce11428345dfe3aa40830c45f9">FVID2_STD_1080P_50</a>   ((uint32_t) 0x0EU)</td></tr>
+<tr class="memdesc:aea1694ce11428345dfe3aa40830c45f9"><td class="mdescLeft"> </td><td class="mdescRight">1920x1080 50FPS progressive HD standard. <br/></td></tr>
+<tr class="separator:aea1694ce11428345dfe3aa40830c45f9"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ae7f99f1670fd74f6f9980df3bb8d5e21"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ae7f99f1670fd74f6f9980df3bb8d5e21"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#ae7f99f1670fd74f6f9980df3bb8d5e21">FVID2_STD_1080P_24</a>   ((uint32_t) 0x0FU)</td></tr>
+<tr class="memdesc:ae7f99f1670fd74f6f9980df3bb8d5e21"><td class="mdescLeft"> </td><td class="mdescRight">1920x1080 24FPS progressive HD standard. <br/></td></tr>
+<tr class="separator:ae7f99f1670fd74f6f9980df3bb8d5e21"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a677029e5d4746ab0ab19753710eaf8fc"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a677029e5d4746ab0ab19753710eaf8fc"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a677029e5d4746ab0ab19753710eaf8fc">FVID2_STD_1080P_30</a>   ((uint32_t) 0x10U)</td></tr>
+<tr class="memdesc:a677029e5d4746ab0ab19753710eaf8fc"><td class="mdescLeft"> </td><td class="mdescRight">1920x1080 30FPS progressive HD standard. <br/></td></tr>
+<tr class="separator:a677029e5d4746ab0ab19753710eaf8fc"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a539104247aec67a1e9a02e99c5dcf644"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a539104247aec67a1e9a02e99c5dcf644"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a539104247aec67a1e9a02e99c5dcf644">FVID2_STD_VGA_60</a>   ((uint32_t) 0x11U)</td></tr>
+<tr class="memdesc:a539104247aec67a1e9a02e99c5dcf644"><td class="mdescLeft"> </td><td class="mdescRight">640x480 60FPS VESA standard. <br/></td></tr>
+<tr class="separator:a539104247aec67a1e9a02e99c5dcf644"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a071ae5ffed3b0dae002efb8bed4a6ff0"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a071ae5ffed3b0dae002efb8bed4a6ff0"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a071ae5ffed3b0dae002efb8bed4a6ff0">FVID2_STD_VGA_72</a>   ((uint32_t) 0x12U)</td></tr>
+<tr class="memdesc:a071ae5ffed3b0dae002efb8bed4a6ff0"><td class="mdescLeft"> </td><td class="mdescRight">640x480 72FPS VESA standard. <br/></td></tr>
+<tr class="separator:a071ae5ffed3b0dae002efb8bed4a6ff0"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ab3dcebfeb086005fc35de1dd08922cf6"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ab3dcebfeb086005fc35de1dd08922cf6"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#ab3dcebfeb086005fc35de1dd08922cf6">FVID2_STD_VGA_75</a>   ((uint32_t) 0x13U)</td></tr>
+<tr class="memdesc:ab3dcebfeb086005fc35de1dd08922cf6"><td class="mdescLeft"> </td><td class="mdescRight">640x480 75FPS VESA standard. <br/></td></tr>
+<tr class="separator:ab3dcebfeb086005fc35de1dd08922cf6"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a331cf0ca858d87e3c005a3441a9bb723"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a331cf0ca858d87e3c005a3441a9bb723"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a331cf0ca858d87e3c005a3441a9bb723">FVID2_STD_VGA_85</a>   ((uint32_t) 0x14U)</td></tr>
+<tr class="memdesc:a331cf0ca858d87e3c005a3441a9bb723"><td class="mdescLeft"> </td><td class="mdescRight">640x480 85FPS VESA standard. <br/></td></tr>
+<tr class="separator:a331cf0ca858d87e3c005a3441a9bb723"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ac23e7e176ae9d5ac95f5a89abce32520"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ac23e7e176ae9d5ac95f5a89abce32520"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#ac23e7e176ae9d5ac95f5a89abce32520">FVID2_STD_WVGA_60</a>   ((uint32_t) 0x15U)</td></tr>
+<tr class="memdesc:ac23e7e176ae9d5ac95f5a89abce32520"><td class="mdescLeft"> </td><td class="mdescRight">800x480 60PFS WVGA <br/></td></tr>
+<tr class="separator:ac23e7e176ae9d5ac95f5a89abce32520"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ac326c1d1653379357aa624d639c811c7"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ac326c1d1653379357aa624d639c811c7"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#ac326c1d1653379357aa624d639c811c7">FVID2_STD_SVGA_60</a>   ((uint32_t) 0x16U)</td></tr>
+<tr class="memdesc:ac326c1d1653379357aa624d639c811c7"><td class="mdescLeft"> </td><td class="mdescRight">800x600 60FPS VESA standard. <br/></td></tr>
+<tr class="separator:ac326c1d1653379357aa624d639c811c7"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a37351c4d4096383e2d5d72316af3f4f0"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a37351c4d4096383e2d5d72316af3f4f0"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a37351c4d4096383e2d5d72316af3f4f0">FVID2_STD_SVGA_72</a>   ((uint32_t) 0x17U)</td></tr>
+<tr class="memdesc:a37351c4d4096383e2d5d72316af3f4f0"><td class="mdescLeft"> </td><td class="mdescRight">800x600 72FPS VESA standard. <br/></td></tr>
+<tr class="separator:a37351c4d4096383e2d5d72316af3f4f0"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a36e85a9212920839f4cdea2f97774d00"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a36e85a9212920839f4cdea2f97774d00"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a36e85a9212920839f4cdea2f97774d00">FVID2_STD_SVGA_75</a>   ((uint32_t) 0x18U)</td></tr>
+<tr class="memdesc:a36e85a9212920839f4cdea2f97774d00"><td class="mdescLeft"> </td><td class="mdescRight">800x600 75FPS VESA standard. <br/></td></tr>
+<tr class="separator:a36e85a9212920839f4cdea2f97774d00"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:abe1e836c388da56174b6fba2a98fec2d"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="abe1e836c388da56174b6fba2a98fec2d"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#abe1e836c388da56174b6fba2a98fec2d">FVID2_STD_SVGA_85</a>   ((uint32_t) 0x19U)</td></tr>
+<tr class="memdesc:abe1e836c388da56174b6fba2a98fec2d"><td class="mdescLeft"> </td><td class="mdescRight">800x600 85FPS VESA standard. <br/></td></tr>
+<tr class="separator:abe1e836c388da56174b6fba2a98fec2d"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ab49cbaf2b57c299a579e3c97eb72f37b"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ab49cbaf2b57c299a579e3c97eb72f37b"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#ab49cbaf2b57c299a579e3c97eb72f37b">FVID2_STD_WSVGA_70</a>   ((uint32_t) 0x1AU)</td></tr>
+<tr class="memdesc:ab49cbaf2b57c299a579e3c97eb72f37b"><td class="mdescLeft"> </td><td class="mdescRight">1024x600 70FPS standard. <br/></td></tr>
+<tr class="separator:ab49cbaf2b57c299a579e3c97eb72f37b"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a2a3be1bf860b622d3561bb1b795fc414"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a2a3be1bf860b622d3561bb1b795fc414"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a2a3be1bf860b622d3561bb1b795fc414">FVID2_STD_XGA_60</a>   ((uint32_t) 0x1BU)</td></tr>
+<tr class="memdesc:a2a3be1bf860b622d3561bb1b795fc414"><td class="mdescLeft"> </td><td class="mdescRight">1024x768 60FPS VESA standard. <br/></td></tr>
+<tr class="separator:a2a3be1bf860b622d3561bb1b795fc414"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ae303cf581ad8069ed5bd6862003fdc83"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ae303cf581ad8069ed5bd6862003fdc83"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#ae303cf581ad8069ed5bd6862003fdc83">FVID2_STD_XGA_DSS_TDM_60</a>   ((uint32_t) 0x1CU)</td></tr>
+<tr class="memdesc:ae303cf581ad8069ed5bd6862003fdc83"><td class="mdescLeft"> </td><td class="mdescRight">1024x768 60FPS VESA standard. Applicable for DSS in 8-bit TDM mode. <br/></td></tr>
+<tr class="separator:ae303cf581ad8069ed5bd6862003fdc83"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a351fd686457f2bb276ffc6f5064cbd9e"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a351fd686457f2bb276ffc6f5064cbd9e"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a351fd686457f2bb276ffc6f5064cbd9e">FVID2_STD_XGA_70</a>   ((uint32_t) 0x1DU)</td></tr>
+<tr class="memdesc:a351fd686457f2bb276ffc6f5064cbd9e"><td class="mdescLeft"> </td><td class="mdescRight">1024x768 72FPS VESA standard. <br/></td></tr>
+<tr class="separator:a351fd686457f2bb276ffc6f5064cbd9e"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:aae15675f7a5d749ee8acfa542e05d8a9"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aae15675f7a5d749ee8acfa542e05d8a9"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#aae15675f7a5d749ee8acfa542e05d8a9">FVID2_STD_XGA_75</a>   ((uint32_t) 0x1EU)</td></tr>
+<tr class="memdesc:aae15675f7a5d749ee8acfa542e05d8a9"><td class="mdescLeft"> </td><td class="mdescRight">1024x768 75FPS VESA standard. <br/></td></tr>
+<tr class="separator:aae15675f7a5d749ee8acfa542e05d8a9"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a351e7a94e0446f709932fd8505ca8402"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a351e7a94e0446f709932fd8505ca8402"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a351e7a94e0446f709932fd8505ca8402">FVID2_STD_XGA_85</a>   ((uint32_t) 0x1FU)</td></tr>
+<tr class="memdesc:a351e7a94e0446f709932fd8505ca8402"><td class="mdescLeft"> </td><td class="mdescRight">1024x768 85FPS VESA standard. <br/></td></tr>
+<tr class="separator:a351e7a94e0446f709932fd8505ca8402"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a93b0af8925015d4614799ba16ad6b654"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a93b0af8925015d4614799ba16ad6b654"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a93b0af8925015d4614799ba16ad6b654">FVID2_STD_1368_768_60</a>   ((uint32_t) 0x20U)</td></tr>
+<tr class="memdesc:a93b0af8925015d4614799ba16ad6b654"><td class="mdescLeft"> </td><td class="mdescRight">1368x768 60 PFS VESA. <br/></td></tr>
+<tr class="separator:a93b0af8925015d4614799ba16ad6b654"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:aeaa514ed3d728d5f625d9e0ad0eb5be8"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aeaa514ed3d728d5f625d9e0ad0eb5be8"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#aeaa514ed3d728d5f625d9e0ad0eb5be8">FVID2_STD_1366_768_60</a>   ((uint32_t) 0x21U)</td></tr>
+<tr class="memdesc:aeaa514ed3d728d5f625d9e0ad0eb5be8"><td class="mdescLeft"> </td><td class="mdescRight">1366x768 60 PFS VESA. <br/></td></tr>
+<tr class="separator:aeaa514ed3d728d5f625d9e0ad0eb5be8"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:aa41941d7e409af4939202e9cb4630efb"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aa41941d7e409af4939202e9cb4630efb"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#aa41941d7e409af4939202e9cb4630efb">FVID2_STD_1360_768_60</a>   ((uint32_t) 0x22U)</td></tr>
+<tr class="memdesc:aa41941d7e409af4939202e9cb4630efb"><td class="mdescLeft"> </td><td class="mdescRight">1360x768 60 PFS VESA. <br/></td></tr>
+<tr class="separator:aa41941d7e409af4939202e9cb4630efb"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a576daaef9c5b1c823b3107c9bb96d114"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a576daaef9c5b1c823b3107c9bb96d114"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a576daaef9c5b1c823b3107c9bb96d114">FVID2_STD_WXGA_30</a>   ((uint32_t) 0x23U)</td></tr>
+<tr class="memdesc:a576daaef9c5b1c823b3107c9bb96d114"><td class="mdescLeft"> </td><td class="mdescRight">1280x800 30FPS VESA standard. <br/></td></tr>
+<tr class="separator:a576daaef9c5b1c823b3107c9bb96d114"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a014e933fc51a2bd62139614d022c9b26"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a014e933fc51a2bd62139614d022c9b26"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a014e933fc51a2bd62139614d022c9b26">FVID2_STD_WXGA_60</a>   ((uint32_t) 0x24U)</td></tr>
+<tr class="memdesc:a014e933fc51a2bd62139614d022c9b26"><td class="mdescLeft"> </td><td class="mdescRight">1280x800 60FPS VESA standard. <br/></td></tr>
+<tr class="separator:a014e933fc51a2bd62139614d022c9b26"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a16436c69aafd74ca687088aaae15ba76"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a16436c69aafd74ca687088aaae15ba76"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a16436c69aafd74ca687088aaae15ba76">FVID2_STD_WXGA_75</a>   ((uint32_t) 0x25U)</td></tr>
+<tr class="memdesc:a16436c69aafd74ca687088aaae15ba76"><td class="mdescLeft"> </td><td class="mdescRight">1280x800 75FPS VESA standard. <br/></td></tr>
+<tr class="separator:a16436c69aafd74ca687088aaae15ba76"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:af3565ee49136c5a00d8c07f68ebd453e"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="af3565ee49136c5a00d8c07f68ebd453e"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#af3565ee49136c5a00d8c07f68ebd453e">FVID2_STD_WXGA_85</a>   ((uint32_t) 0x26U)</td></tr>
+<tr class="memdesc:af3565ee49136c5a00d8c07f68ebd453e"><td class="mdescLeft"> </td><td class="mdescRight">1280x800 85FPS VESA standard. <br/></td></tr>
+<tr class="separator:af3565ee49136c5a00d8c07f68ebd453e"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a2b167ba856bcb092c2abf0af556e2da1"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a2b167ba856bcb092c2abf0af556e2da1"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a2b167ba856bcb092c2abf0af556e2da1">FVID2_STD_1440_900_60</a>   ((uint32_t) 0x27U)</td></tr>
+<tr class="memdesc:a2b167ba856bcb092c2abf0af556e2da1"><td class="mdescLeft"> </td><td class="mdescRight">1440x900 60 PFS VESA standard. <br/></td></tr>
+<tr class="separator:a2b167ba856bcb092c2abf0af556e2da1"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a5f2b699f67df490f4922f0cf80e12a17"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a5f2b699f67df490f4922f0cf80e12a17"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a5f2b699f67df490f4922f0cf80e12a17">FVID2_STD_SXGA_60</a>   ((uint32_t) 0x28U)</td></tr>
+<tr class="memdesc:a5f2b699f67df490f4922f0cf80e12a17"><td class="mdescLeft"> </td><td class="mdescRight">1280x1024 60FPS VESA standard. <br/></td></tr>
+<tr class="separator:a5f2b699f67df490f4922f0cf80e12a17"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a3240f384b90e33105de53c735ac24ab8"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a3240f384b90e33105de53c735ac24ab8"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a3240f384b90e33105de53c735ac24ab8">FVID2_STD_SXGA_75</a>   ((uint32_t) 0x29U)</td></tr>
+<tr class="memdesc:a3240f384b90e33105de53c735ac24ab8"><td class="mdescLeft"> </td><td class="mdescRight">1280x1024 75FPS VESA standard. <br/></td></tr>
+<tr class="separator:a3240f384b90e33105de53c735ac24ab8"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a89f1f4cd2d6c4ba37f143a804e09e56d"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a89f1f4cd2d6c4ba37f143a804e09e56d"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a89f1f4cd2d6c4ba37f143a804e09e56d">FVID2_STD_SXGA_85</a>   ((uint32_t) 0x2AU)</td></tr>
+<tr class="memdesc:a89f1f4cd2d6c4ba37f143a804e09e56d"><td class="mdescLeft"> </td><td class="mdescRight">1280x1024 85FPS VESA standard. <br/></td></tr>
+<tr class="separator:a89f1f4cd2d6c4ba37f143a804e09e56d"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a7a77706faae342689c3e8dd2f31a442a"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a7a77706faae342689c3e8dd2f31a442a"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a7a77706faae342689c3e8dd2f31a442a">FVID2_STD_WSXGAP_60</a>   ((uint32_t) 0x2BU)</td></tr>
+<tr class="memdesc:a7a77706faae342689c3e8dd2f31a442a"><td class="mdescLeft"> </td><td class="mdescRight">1680x1050 60 PFS VESA standard. <br/></td></tr>
+<tr class="separator:a7a77706faae342689c3e8dd2f31a442a"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ac57de538e6e7c03b518f40b576b78e54"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ac57de538e6e7c03b518f40b576b78e54"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#ac57de538e6e7c03b518f40b576b78e54">FVID2_STD_SXGAP_60</a>   ((uint32_t) 0x2CU)</td></tr>
+<tr class="memdesc:ac57de538e6e7c03b518f40b576b78e54"><td class="mdescLeft"> </td><td class="mdescRight">1400x1050 60FPS VESA standard. <br/></td></tr>
+<tr class="separator:ac57de538e6e7c03b518f40b576b78e54"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ab8bb357f5290805dae7cb93e59207ca6"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ab8bb357f5290805dae7cb93e59207ca6"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#ab8bb357f5290805dae7cb93e59207ca6">FVID2_STD_SXGAP_75</a>   ((uint32_t) 0x2DU)</td></tr>
+<tr class="memdesc:ab8bb357f5290805dae7cb93e59207ca6"><td class="mdescLeft"> </td><td class="mdescRight">1400x1050 75FPS VESA standard. <br/></td></tr>
+<tr class="separator:ab8bb357f5290805dae7cb93e59207ca6"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a857b7d7d1443a364f5642fcd8f9fcad0"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a857b7d7d1443a364f5642fcd8f9fcad0"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a857b7d7d1443a364f5642fcd8f9fcad0">FVID2_STD_UXGA_60</a>   ((uint32_t) 0x2EU)</td></tr>
+<tr class="memdesc:a857b7d7d1443a364f5642fcd8f9fcad0"><td class="mdescLeft"> </td><td class="mdescRight">1600x1200 60FPS VESA standard. <br/></td></tr>
+<tr class="separator:a857b7d7d1443a364f5642fcd8f9fcad0"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a0abdf3aefeccfe5a6e2bf8fc2f0b1356"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a0abdf3aefeccfe5a6e2bf8fc2f0b1356"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a0abdf3aefeccfe5a6e2bf8fc2f0b1356">FVID2_STD_MUX_2CH_D1</a>   ((uint32_t) 0x2FU)</td></tr>
+<tr class="memdesc:a0abdf3aefeccfe5a6e2bf8fc2f0b1356"><td class="mdescLeft"> </td><td class="mdescRight">Interlaced, 2Ch D1, NTSC or PAL. <br/></td></tr>
+<tr class="separator:a0abdf3aefeccfe5a6e2bf8fc2f0b1356"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ad757a9ccea31d5a94c0ec1c6322f9271"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ad757a9ccea31d5a94c0ec1c6322f9271"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#ad757a9ccea31d5a94c0ec1c6322f9271">FVID2_STD_MUX_2CH_HALF_D1</a>   ((uint32_t) 0x30U)</td></tr>
+<tr class="memdesc:ad757a9ccea31d5a94c0ec1c6322f9271"><td class="mdescLeft"> </td><td class="mdescRight">Interlaced, 2ch half D1, NTSC or PAL. <br/></td></tr>
+<tr class="separator:ad757a9ccea31d5a94c0ec1c6322f9271"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:af5a5f9c53ab6634cb288c00808129639"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="af5a5f9c53ab6634cb288c00808129639"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#af5a5f9c53ab6634cb288c00808129639">FVID2_STD_MUX_2CH_CIF</a>   ((uint32_t) 0x31U)</td></tr>
+<tr class="memdesc:af5a5f9c53ab6634cb288c00808129639"><td class="mdescLeft"> </td><td class="mdescRight">Interlaced, 2ch CIF, NTSC or PAL. <br/></td></tr>
+<tr class="separator:af5a5f9c53ab6634cb288c00808129639"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a1a68a709c1a760d4ee6f8c70b7a4f14b"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a1a68a709c1a760d4ee6f8c70b7a4f14b"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a1a68a709c1a760d4ee6f8c70b7a4f14b">FVID2_STD_MUX_4CH_D1</a>   ((uint32_t) 0x32U)</td></tr>
+<tr class="memdesc:a1a68a709c1a760d4ee6f8c70b7a4f14b"><td class="mdescLeft"> </td><td class="mdescRight">Interlaced, 4Ch D1, NTSC or PAL. <br/></td></tr>
+<tr class="separator:a1a68a709c1a760d4ee6f8c70b7a4f14b"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a8d2347b9179f8bda62f4ca0ae337ed22"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a8d2347b9179f8bda62f4ca0ae337ed22"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a8d2347b9179f8bda62f4ca0ae337ed22">FVID2_STD_MUX_4CH_CIF</a>   ((uint32_t) 0x33U)</td></tr>
+<tr class="memdesc:a8d2347b9179f8bda62f4ca0ae337ed22"><td class="mdescLeft"> </td><td class="mdescRight">Interlaced, 4Ch CIF, NTSC or PAL. <br/></td></tr>
+<tr class="separator:a8d2347b9179f8bda62f4ca0ae337ed22"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a5afbbf47084865e341f0870ee30cc739"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a5afbbf47084865e341f0870ee30cc739"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a5afbbf47084865e341f0870ee30cc739">FVID2_STD_MUX_4CH_HALF_D1</a>   ((uint32_t) 0x34U)</td></tr>
+<tr class="memdesc:a5afbbf47084865e341f0870ee30cc739"><td class="mdescLeft"> </td><td class="mdescRight">Interlaced, 4Ch Half-D1, NTSC or PAL. <br/></td></tr>
+<tr class="separator:a5afbbf47084865e341f0870ee30cc739"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a1d96d34832944c554b3b7adb6ebad4d9"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a1d96d34832944c554b3b7adb6ebad4d9"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a1d96d34832944c554b3b7adb6ebad4d9">FVID2_STD_MUX_8CH_CIF</a>   ((uint32_t) 0x35U)</td></tr>
+<tr class="memdesc:a1d96d34832944c554b3b7adb6ebad4d9"><td class="mdescLeft"> </td><td class="mdescRight">Interlaced, 8Ch CIF, NTSC or PAL. <br/></td></tr>
+<tr class="separator:a1d96d34832944c554b3b7adb6ebad4d9"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a3829733b32609b9a5f9f6f0bbd6714e5"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a3829733b32609b9a5f9f6f0bbd6714e5"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a3829733b32609b9a5f9f6f0bbd6714e5">FVID2_STD_MUX_8CH_HALF_D1</a>   ((uint32_t) 0x36U)</td></tr>
+<tr class="memdesc:a3829733b32609b9a5f9f6f0bbd6714e5"><td class="mdescLeft"> </td><td class="mdescRight">Interlaced, 8Ch Half-D1, NTSC or PAL. <br/></td></tr>
+<tr class="separator:a3829733b32609b9a5f9f6f0bbd6714e5"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:aaab0c4817ec5e9f10f0c13d5375e1d30"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aaab0c4817ec5e9f10f0c13d5375e1d30"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#aaab0c4817ec5e9f10f0c13d5375e1d30">FVID2_STD_WXGA_5x3_30</a>   ((uint32_t) 0x37U)</td></tr>
+<tr class="memdesc:aaab0c4817ec5e9f10f0c13d5375e1d30"><td class="mdescLeft"> </td><td class="mdescRight">WXGA standard (1280x768) with the aspect ratio 5:3 at 30FPS. <br/></td></tr>
+<tr class="separator:aaab0c4817ec5e9f10f0c13d5375e1d30"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ad69ca1aed51329f28c87873b2544dd0e"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ad69ca1aed51329f28c87873b2544dd0e"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#ad69ca1aed51329f28c87873b2544dd0e">FVID2_STD_WXGA_5x3_60</a>   ((uint32_t) 0x38U)</td></tr>
+<tr class="memdesc:ad69ca1aed51329f28c87873b2544dd0e"><td class="mdescLeft"> </td><td class="mdescRight">WXGA resolution (1280x768) with the aspect ratio 5:3 at 60FPS. <br/></td></tr>
+<tr class="separator:ad69ca1aed51329f28c87873b2544dd0e"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a42448ed6ed591d189584a9d6751c2edf"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a42448ed6ed591d189584a9d6751c2edf"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a42448ed6ed591d189584a9d6751c2edf">FVID2_STD_WXGA_5x3_75</a>   ((uint32_t) 0x39U)</td></tr>
+<tr class="memdesc:a42448ed6ed591d189584a9d6751c2edf"><td class="mdescLeft"> </td><td class="mdescRight">WXGA resolution (1280x768) with the aspect ratio 5:3 at 75FPS. <br/></td></tr>
+<tr class="separator:a42448ed6ed591d189584a9d6751c2edf"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:aaea4cb84fc06503d103416a5d7c064bf"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aaea4cb84fc06503d103416a5d7c064bf"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#aaea4cb84fc06503d103416a5d7c064bf">FVID2_STD_AUTO_DETECT</a>   ((uint32_t) 0x3AU)</td></tr>
+<tr class="memdesc:aaea4cb84fc06503d103416a5d7c064bf"><td class="mdescLeft"> </td><td class="mdescRight">Auto-detect standard. Used in capture mode. <br/></td></tr>
+<tr class="separator:aaea4cb84fc06503d103416a5d7c064bf"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a3be5517c8a5b384f525120a6473b9aa8"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a3be5517c8a5b384f525120a6473b9aa8"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a3be5517c8a5b384f525120a6473b9aa8">FVID2_STD_CUSTOM</a>   ((uint32_t) 0x3BU)</td></tr>
+<tr class="memdesc:a3be5517c8a5b384f525120a6473b9aa8"><td class="mdescLeft"> </td><td class="mdescRight">Custom standard used when connecting to external LCD etc... The video timing is provided by the application. Used in display mode. <br/></td></tr>
+<tr class="separator:a3be5517c8a5b384f525120a6473b9aa8"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:aaa2667d105d557f254c20b87534ed4b6"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aaa2667d105d557f254c20b87534ed4b6"></a>
+typedef uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#aaa2667d105d557f254c20b87534ed4b6">Fvid2_Standard</a></td></tr>
+<tr class="memdesc:aaa2667d105d557f254c20b87534ed4b6"><td class="mdescLeft"> </td><td class="mdescRight">720x480 30FPS interlaced NTSC standard. <br/></td></tr>
+<tr class="separator:aaa2667d105d557f254c20b87534ed4b6"><td class="memSeparator" colspan="2"> </td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
+Field type</h2></td></tr>
+<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrpd742cb277ac01a0fc2738a3394b0b33b"></a><a class="anchor" id="Fvid2_Fid"></a></p>
+</td></tr>
+<tr class="memitem:af32c74c0915f13dab2d7e120ef005abc"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="af32c74c0915f13dab2d7e120ef005abc"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#af32c74c0915f13dab2d7e120ef005abc">FVID2_FID_TOP</a>   ((uint32_t) 0U)</td></tr>
+<tr class="memdesc:af32c74c0915f13dab2d7e120ef005abc"><td class="mdescLeft"> </td><td class="mdescRight">Top field. <br/></td></tr>
+<tr class="separator:af32c74c0915f13dab2d7e120ef005abc"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a23d309e6dd15b8d12631e929fff9e339"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a23d309e6dd15b8d12631e929fff9e339"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a23d309e6dd15b8d12631e929fff9e339">FVID2_FID_BOTTOM</a>   ((uint32_t) 1U)</td></tr>
+<tr class="memdesc:a23d309e6dd15b8d12631e929fff9e339"><td class="mdescLeft"> </td><td class="mdescRight">Bottom field. <br/></td></tr>
+<tr class="separator:a23d309e6dd15b8d12631e929fff9e339"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ab5843717d261368283fd1618d1a26efa"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ab5843717d261368283fd1618d1a26efa"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#ab5843717d261368283fd1618d1a26efa">FVID2_FID_FRAME</a>   ((uint32_t) 2U)</td></tr>
+<tr class="memdesc:ab5843717d261368283fd1618d1a26efa"><td class="mdescLeft"> </td><td class="mdescRight">Frame mode - Contains both the fields or a progressive frame. <br/></td></tr>
+<tr class="separator:ab5843717d261368283fd1618d1a26efa"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a922a79fd009af8bf7cca0539cf326f8f"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a922a79fd009af8bf7cca0539cf326f8f"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a922a79fd009af8bf7cca0539cf326f8f">FVID2_FID_MAX</a>   ((uint32_t) 3U)</td></tr>
+<tr class="memdesc:a922a79fd009af8bf7cca0539cf326f8f"><td class="mdescLeft"> </td><td class="mdescRight">Used by driver for validating the input parameters. <br/></td></tr>
+<tr class="separator:a922a79fd009af8bf7cca0539cf326f8f"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a46dbb7460c568075f1cd6959282d87cb"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a46dbb7460c568075f1cd6959282d87cb"></a>
+typedef uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a46dbb7460c568075f1cd6959282d87cb">Fvid2_Fid</a></td></tr>
+<tr class="memdesc:a46dbb7460c568075f1cd6959282d87cb"><td class="mdescLeft"> </td><td class="mdescRight">Top field. <br/></td></tr>
+<tr class="separator:a46dbb7460c568075f1cd6959282d87cb"><td class="memSeparator" colspan="2"> </td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
+Polarity type</h2></td></tr>
+<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrpf16739124b637d0de5e3b0735fa9f77b"></a><a class="anchor" id="Fvid2_Polarity"></a></p>
+</td></tr>
+<tr class="memitem:a7039fcba297528e798b709348d086ae0"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a7039fcba297528e798b709348d086ae0"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a7039fcba297528e798b709348d086ae0">FVID2_POL_LOW</a>   ((uint32_t) 0U)</td></tr>
+<tr class="memdesc:a7039fcba297528e798b709348d086ae0"><td class="mdescLeft"> </td><td class="mdescRight">Low Polarity. <br/></td></tr>
+<tr class="separator:a7039fcba297528e798b709348d086ae0"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a1ec7e5d8259b4f4d17b46f530c0d131c"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a1ec7e5d8259b4f4d17b46f530c0d131c"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a1ec7e5d8259b4f4d17b46f530c0d131c">FVID2_POL_HIGH</a>   ((uint32_t) 1U)</td></tr>
+<tr class="memdesc:a1ec7e5d8259b4f4d17b46f530c0d131c"><td class="mdescLeft"> </td><td class="mdescRight">High Polarity. <br/></td></tr>
+<tr class="separator:a1ec7e5d8259b4f4d17b46f530c0d131c"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a6a962d56487d54dcae253875c5f5b507"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a6a962d56487d54dcae253875c5f5b507"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a6a962d56487d54dcae253875c5f5b507">FVID2_POL_MAX</a>   ((uint32_t) 2U)</td></tr>
+<tr class="memdesc:a6a962d56487d54dcae253875c5f5b507"><td class="mdescLeft"> </td><td class="mdescRight">Used by driver for validating the input parameters. <br/></td></tr>
+<tr class="separator:a6a962d56487d54dcae253875c5f5b507"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a9e9754a80a4e33aebaf391204a570723"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a9e9754a80a4e33aebaf391204a570723"></a>
+typedef uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a9e9754a80a4e33aebaf391204a570723">Fvid2_Polarity</a></td></tr>
+<tr class="memdesc:a9e9754a80a4e33aebaf391204a570723"><td class="mdescLeft"> </td><td class="mdescRight">Low Polarity. <br/></td></tr>
+<tr class="separator:a9e9754a80a4e33aebaf391204a570723"><td class="memSeparator" colspan="2"> </td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
+Edge Polarity type</h2></td></tr>
+<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrpe928658f43c5a0250023ead3e510a737"></a><a class="anchor" id="Fvid2_EdgePolarity"></a></p>
+</td></tr>
+<tr class="memitem:af1bb38fbf056952fa9c28bd85ac2508f"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="af1bb38fbf056952fa9c28bd85ac2508f"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#af1bb38fbf056952fa9c28bd85ac2508f">FVID2_EDGE_POL_RISING</a>   ((uint32_t) 0U)</td></tr>
+<tr class="memdesc:af1bb38fbf056952fa9c28bd85ac2508f"><td class="mdescLeft"> </td><td class="mdescRight">Rising Edge. <br/></td></tr>
+<tr class="separator:af1bb38fbf056952fa9c28bd85ac2508f"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a16d3b52243aa2b0e0bf6a07ae5d24104"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a16d3b52243aa2b0e0bf6a07ae5d24104"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a16d3b52243aa2b0e0bf6a07ae5d24104">FVID2_EDGE_POL_FALLING</a>   ((uint32_t) 1U)</td></tr>
+<tr class="memdesc:a16d3b52243aa2b0e0bf6a07ae5d24104"><td class="mdescLeft"> </td><td class="mdescRight">Falling Edge. <br/></td></tr>
+<tr class="separator:a16d3b52243aa2b0e0bf6a07ae5d24104"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a37ba0f81682b573fdd22c909c5064f12"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a37ba0f81682b573fdd22c909c5064f12"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a37ba0f81682b573fdd22c909c5064f12">FVID2_EDGE_POL_MAX</a>   ((uint32_t) 2U)</td></tr>
+<tr class="memdesc:a37ba0f81682b573fdd22c909c5064f12"><td class="mdescLeft"> </td><td class="mdescRight">Used by driver for validating the input parameters. <br/></td></tr>
+<tr class="separator:a37ba0f81682b573fdd22c909c5064f12"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:acfe95315f6c3bfd70f38bb2d4486bd19"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="acfe95315f6c3bfd70f38bb2d4486bd19"></a>
+typedef uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#acfe95315f6c3bfd70f38bb2d4486bd19">Fvid2_EdgePolarity</a></td></tr>
+<tr class="memdesc:acfe95315f6c3bfd70f38bb2d4486bd19"><td class="mdescLeft"> </td><td class="mdescRight">Rising Edge. <br/></td></tr>
+<tr class="separator:acfe95315f6c3bfd70f38bb2d4486bd19"><td class="memSeparator" colspan="2"> </td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
+Field ID polarity</h2></td></tr>
+<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrpd2306dfa1ff6338021277eb9dbe3ccaf"></a><a class="anchor" id="Fvid2_FidPol"></a></p>
+</td></tr>
+<tr class="memitem:ab5b7377e57466d1708b4f4ec8393b7bd"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ab5b7377e57466d1708b4f4ec8393b7bd"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#ab5b7377e57466d1708b4f4ec8393b7bd">FVID2_FIDPOL_NORMAL</a>   ((uint32_t) 0U)</td></tr>
+<tr class="memdesc:ab5b7377e57466d1708b4f4ec8393b7bd"><td class="mdescLeft"> </td><td class="mdescRight">FID = 0, top field. <br/></td></tr>
+<tr class="separator:ab5b7377e57466d1708b4f4ec8393b7bd"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:acabe3506962c40666e10696224cfbfb0"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="acabe3506962c40666e10696224cfbfb0"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#acabe3506962c40666e10696224cfbfb0">FVID2_FIDPOL_INVERT</a>   ((uint32_t) 1U)</td></tr>
+<tr class="memdesc:acabe3506962c40666e10696224cfbfb0"><td class="mdescLeft"> </td><td class="mdescRight">FID = 1, bottom field. <br/></td></tr>
+<tr class="separator:acabe3506962c40666e10696224cfbfb0"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a771282d54cb8fd1a47a32f2210786a3a"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a771282d54cb8fd1a47a32f2210786a3a"></a>
+typedef uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a771282d54cb8fd1a47a32f2210786a3a">Fvid2_FidPol</a></td></tr>
+<tr class="memdesc:a771282d54cb8fd1a47a32f2210786a3a"><td class="mdescLeft"> </td><td class="mdescRight">FID = 0, top field. <br/></td></tr>
+<tr class="separator:a771282d54cb8fd1a47a32f2210786a3a"><td class="memSeparator" colspan="2"> </td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
+Buffer storage format</h2></td></tr>
+<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrpe52859ea50fc78d92b76e2a686e29342"></a><a class="anchor" id="Fvid2_BufferFormat"></a></p>
+</td></tr>
+<tr class="memitem:afa226435f563ae5b91e94e8e0728a12c"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="afa226435f563ae5b91e94e8e0728a12c"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#afa226435f563ae5b91e94e8e0728a12c">FVID2_BUF_FMT_FIELD</a>   ((uint32_t) 0U)</td></tr>
+<tr class="memdesc:afa226435f563ae5b91e94e8e0728a12c"><td class="mdescLeft"> </td><td class="mdescRight">Buffers are captured/displayed as fields instead of frames. <br/></td></tr>
+<tr class="separator:afa226435f563ae5b91e94e8e0728a12c"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:aac021d82bbc20a8ce5ea9a88a2cd8dd0"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aac021d82bbc20a8ce5ea9a88a2cd8dd0"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#aac021d82bbc20a8ce5ea9a88a2cd8dd0">FVID2_BUF_FMT_FRAME</a>   ((uint32_t) 1U)</td></tr>
+<tr class="memdesc:aac021d82bbc20a8ce5ea9a88a2cd8dd0"><td class="mdescLeft"> </td><td class="mdescRight">Buffers are captured/displayed as frames. <br/></td></tr>
+<tr class="separator:aac021d82bbc20a8ce5ea9a88a2cd8dd0"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a46ba9c505db41c885e5614571f680707"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a46ba9c505db41c885e5614571f680707"></a>
+typedef uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a46ba9c505db41c885e5614571f680707">Fvid2_BufferFormat</a></td></tr>
+<tr class="memdesc:a46ba9c505db41c885e5614571f680707"><td class="mdescLeft"> </td><td class="mdescRight">Buffers are captured/displayed as fields instead of frames. <br/></td></tr>
+<tr class="separator:a46ba9c505db41c885e5614571f680707"><td class="memSeparator" colspan="2"> </td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
+Storage Format for each color component in pixel</h2></td></tr>
+<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrp59c36f01287a714175f00341cd4203f1"></a><a class="anchor" id="Fvid2_ColorCompStorageFmt"></a></p>
+</td></tr>
+<tr class="memitem:ab926a2bd1d85a43a6cd118b522c36da9"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ab926a2bd1d85a43a6cd118b522c36da9"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#ab926a2bd1d85a43a6cd118b522c36da9">FVID2_CCSF_BITS1_PACKED</a>   ((uint32_t) 0x00U)</td></tr>
+<tr class="memdesc:ab926a2bd1d85a43a6cd118b522c36da9"><td class="mdescLeft"> </td><td class="mdescRight">1 Bits per Pixel packed. <br/></td></tr>
+<tr class="separator:ab926a2bd1d85a43a6cd118b522c36da9"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a594de86d607039309992132021df72c1"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a594de86d607039309992132021df72c1"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a594de86d607039309992132021df72c1">FVID2_CCSF_BITS2_PACKED</a>   ((uint32_t) 0x01U)</td></tr>
+<tr class="memdesc:a594de86d607039309992132021df72c1"><td class="mdescLeft"> </td><td class="mdescRight">2 Bits per Pixel packed. <br/></td></tr>
+<tr class="separator:a594de86d607039309992132021df72c1"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a9707de69ccc80d650d2adc52fbf3b410"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a9707de69ccc80d650d2adc52fbf3b410"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a9707de69ccc80d650d2adc52fbf3b410">FVID2_CCSF_BITS4_PACKED</a>   ((uint32_t) 0x02U)</td></tr>
+<tr class="memdesc:a9707de69ccc80d650d2adc52fbf3b410"><td class="mdescLeft"> </td><td class="mdescRight">4 Bits per Pixel packed. <br/></td></tr>
+<tr class="separator:a9707de69ccc80d650d2adc52fbf3b410"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a3a142fe37655cbd712f9e01c91d5db4d"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a3a142fe37655cbd712f9e01c91d5db4d"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a3a142fe37655cbd712f9e01c91d5db4d">FVID2_CCSF_BITS8_PACKED</a>   ((uint32_t) 0x03U)</td></tr>
+<tr class="memdesc:a3a142fe37655cbd712f9e01c91d5db4d"><td class="mdescLeft"> </td><td class="mdescRight">8 Bits per Pixel packed. <br/></td></tr>
+<tr class="separator:a3a142fe37655cbd712f9e01c91d5db4d"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:af3ac23834ffbf9aa575aa1aa1ba5f5dd"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="af3ac23834ffbf9aa575aa1aa1ba5f5dd"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#af3ac23834ffbf9aa575aa1aa1ba5f5dd">FVID2_CCSF_BITS10_PACKED</a>   ((uint32_t) 0x04U)</td></tr>
+<tr class="memdesc:af3ac23834ffbf9aa575aa1aa1ba5f5dd"><td class="mdescLeft"> </td><td class="mdescRight">12 Bits per Pixel packed. <br/></td></tr>
+<tr class="separator:af3ac23834ffbf9aa575aa1aa1ba5f5dd"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:aaca4732e06c1a91049170d81747e54ef"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aaca4732e06c1a91049170d81747e54ef"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#aaca4732e06c1a91049170d81747e54ef">FVID2_CCSF_BITS12_PACKED</a>   ((uint32_t) 0x05U)</td></tr>
+<tr class="memdesc:aaca4732e06c1a91049170d81747e54ef"><td class="mdescLeft"> </td><td class="mdescRight">12 Bits per Pixel packed. <br/></td></tr>
+<tr class="separator:aaca4732e06c1a91049170d81747e54ef"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a83bbd32f9354c1456bb2483aea4e1f9c"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a83bbd32f9354c1456bb2483aea4e1f9c"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a83bbd32f9354c1456bb2483aea4e1f9c">FVID2_CCSF_BITS14_PACKED</a>   ((uint32_t) 0x06U)</td></tr>
+<tr class="memdesc:a83bbd32f9354c1456bb2483aea4e1f9c"><td class="mdescLeft"> </td><td class="mdescRight">14 Bits per Pixel packed. <br/></td></tr>
+<tr class="separator:a83bbd32f9354c1456bb2483aea4e1f9c"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a04ecc76a7481ee23eb31ee72d373f67f"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a04ecc76a7481ee23eb31ee72d373f67f"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a04ecc76a7481ee23eb31ee72d373f67f">FVID2_CCSF_BITS16_PACKED</a>   ((uint32_t) 0x07U)</td></tr>
+<tr class="memdesc:a04ecc76a7481ee23eb31ee72d373f67f"><td class="mdescLeft"> </td><td class="mdescRight">16 Bits per Pixel packed. <br/></td></tr>
+<tr class="separator:a04ecc76a7481ee23eb31ee72d373f67f"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a785fa5e01bef9af1c292209f5cccf5cd"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a785fa5e01bef9af1c292209f5cccf5cd"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a785fa5e01bef9af1c292209f5cccf5cd">FVID2_CCSF_BITS24_PACKED</a>   ((uint32_t) 0x08U)</td></tr>
+<tr class="memdesc:a785fa5e01bef9af1c292209f5cccf5cd"><td class="mdescLeft"> </td><td class="mdescRight">24 Bits per Pixel packed. <br/></td></tr>
+<tr class="separator:a785fa5e01bef9af1c292209f5cccf5cd"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a54169847d76c66ad23f937e1b39b9f67"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a54169847d76c66ad23f937e1b39b9f67"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a54169847d76c66ad23f937e1b39b9f67">FVID2_CCSF_BITS32_PACKED</a>   ((uint32_t) 0x09U)</td></tr>
+<tr class="memdesc:a54169847d76c66ad23f937e1b39b9f67"><td class="mdescLeft"> </td><td class="mdescRight">32 Bits per Pixel packed. <br/></td></tr>
+<tr class="separator:a54169847d76c66ad23f937e1b39b9f67"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ac2fb823eb58d916b329917b1eb61e11b"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ac2fb823eb58d916b329917b1eb61e11b"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#ac2fb823eb58d916b329917b1eb61e11b">FVID2_CCSF_BITS6_UNPACKED8</a>   ((uint32_t) 0x0AU)</td></tr>
+<tr class="memdesc:ac2fb823eb58d916b329917b1eb61e11b"><td class="mdescLeft"> </td><td class="mdescRight">6 Bits per Pixel unpacked in 8bit container. <br/></td></tr>
+<tr class="separator:ac2fb823eb58d916b329917b1eb61e11b"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a07455c28c2c98f6b2d421a99aa6c4f9a"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a07455c28c2c98f6b2d421a99aa6c4f9a"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a07455c28c2c98f6b2d421a99aa6c4f9a">FVID2_CCSF_BITS7_UNPACKED8</a>   ((uint32_t) 0x0BU)</td></tr>
+<tr class="memdesc:a07455c28c2c98f6b2d421a99aa6c4f9a"><td class="mdescLeft"> </td><td class="mdescRight">7 Bits per Pixel unpacked in 8bit container. <br/></td></tr>
+<tr class="separator:a07455c28c2c98f6b2d421a99aa6c4f9a"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a00417ee1982d86db35983a405a0ec036"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a00417ee1982d86db35983a405a0ec036"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a00417ee1982d86db35983a405a0ec036">FVID2_CCSF_BITS8_UNPACKED12</a>   ((uint32_t) 0x0CU)</td></tr>
+<tr class="memdesc:a00417ee1982d86db35983a405a0ec036"><td class="mdescLeft"> </td><td class="mdescRight">8 Bits per Pixel unpacked in 12bit container. <br/></td></tr>
+<tr class="separator:a00417ee1982d86db35983a405a0ec036"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:afd8b6daeed620a8114ed0486cab137a1"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="afd8b6daeed620a8114ed0486cab137a1"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#afd8b6daeed620a8114ed0486cab137a1">FVID2_CCSF_BITS8_UNPACKED16</a>   ((uint32_t) 0x0DU)</td></tr>
+<tr class="memdesc:afd8b6daeed620a8114ed0486cab137a1"><td class="mdescLeft"> </td><td class="mdescRight">8 Bits per Pixel unpacked in 12bit container. <br/></td></tr>
+<tr class="separator:afd8b6daeed620a8114ed0486cab137a1"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a299dac024c0d2cc79833a7b8f464fcf8"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a299dac024c0d2cc79833a7b8f464fcf8"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a299dac024c0d2cc79833a7b8f464fcf8">FVID2_CCSF_BITS9_UNPACKED16</a>   ((uint32_t) 0x0EU)</td></tr>
+<tr class="memdesc:a299dac024c0d2cc79833a7b8f464fcf8"><td class="mdescLeft"> </td><td class="mdescRight">9 Bits per Pixel unpacked in 16bit container. <br/></td></tr>
+<tr class="separator:a299dac024c0d2cc79833a7b8f464fcf8"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:aac7eaa1f4b68b84dca644e7b3a4a02a8"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aac7eaa1f4b68b84dca644e7b3a4a02a8"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#aac7eaa1f4b68b84dca644e7b3a4a02a8">FVID2_CCSF_BITS10_UNPACKED16</a>   ((uint32_t) 0x0FU)</td></tr>
+<tr class="memdesc:aac7eaa1f4b68b84dca644e7b3a4a02a8"><td class="mdescLeft"> </td><td class="mdescRight">10 Bits per Pixel unpacked in 16bit container <br/></td></tr>
+<tr class="separator:aac7eaa1f4b68b84dca644e7b3a4a02a8"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a4f53868e86fd933d7e8998fc78dd835b"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a4f53868e86fd933d7e8998fc78dd835b"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a4f53868e86fd933d7e8998fc78dd835b">FVID2_CCSF_BITS11_UNPACKED16</a>   ((uint32_t) 0x10U)</td></tr>
+<tr class="memdesc:a4f53868e86fd933d7e8998fc78dd835b"><td class="mdescLeft"> </td><td class="mdescRight">11 Bits per Pixel unpacked in 16bit container. <br/></td></tr>
+<tr class="separator:a4f53868e86fd933d7e8998fc78dd835b"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a8b42effc244c7f41159f640a4843ec17"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a8b42effc244c7f41159f640a4843ec17"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a8b42effc244c7f41159f640a4843ec17">FVID2_CCSF_BITS12_UNPACKED16</a>   ((uint32_t) 0x11U)</td></tr>
+<tr class="memdesc:a8b42effc244c7f41159f640a4843ec17"><td class="mdescLeft"> </td><td class="mdescRight">12 Bits per Pixel, unpacked in 16bit container <br/></td></tr>
+<tr class="separator:a8b42effc244c7f41159f640a4843ec17"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a00f1d329f88f72cf5ac0b12306c71637"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a00f1d329f88f72cf5ac0b12306c71637"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a00f1d329f88f72cf5ac0b12306c71637">FVID2_CCSF_BITS13_UNPACKED16</a>   ((uint32_t) 0x12U)</td></tr>
+<tr class="memdesc:a00f1d329f88f72cf5ac0b12306c71637"><td class="mdescLeft"> </td><td class="mdescRight">13 Bits per Pixel unpacked in 16bit container. <br/></td></tr>
+<tr class="separator:a00f1d329f88f72cf5ac0b12306c71637"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a97e208768c0a77614e9add93dfeb53c4"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a97e208768c0a77614e9add93dfeb53c4"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a97e208768c0a77614e9add93dfeb53c4">FVID2_CCSF_BITS14_UNPACKED16</a>   ((uint32_t) 0x13U)</td></tr>
+<tr class="memdesc:a97e208768c0a77614e9add93dfeb53c4"><td class="mdescLeft"> </td><td class="mdescRight">14 Bits per Pixel unpacked in 16bit container. <br/></td></tr>
+<tr class="separator:a97e208768c0a77614e9add93dfeb53c4"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a6c2b17f6ec2ac3f348d422ac7a7d4433"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a6c2b17f6ec2ac3f348d422ac7a7d4433"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a6c2b17f6ec2ac3f348d422ac7a7d4433">FVID2_CCSF_BITS15_UNPACKED16</a>   ((uint32_t) 0x14U)</td></tr>
+<tr class="memdesc:a6c2b17f6ec2ac3f348d422ac7a7d4433"><td class="mdescLeft"> </td><td class="mdescRight">15 Bits per Pixel unpacked in 16bit container. <br/></td></tr>
+<tr class="separator:a6c2b17f6ec2ac3f348d422ac7a7d4433"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a988e90d38af500d421c021a047abf722"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a988e90d38af500d421c021a047abf722"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a988e90d38af500d421c021a047abf722">FVID2_CCSF_BITS20_UNPACKED24</a>   ((uint32_t) 0x15U)</td></tr>
+<tr class="memdesc:a988e90d38af500d421c021a047abf722"><td class="mdescLeft"> </td><td class="mdescRight">20 Bits per Pixel unpacked in 24bit container. <br/></td></tr>
+<tr class="separator:a988e90d38af500d421c021a047abf722"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a61dddf1df3cf8174f8d3917ae3773694"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a61dddf1df3cf8174f8d3917ae3773694"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a61dddf1df3cf8174f8d3917ae3773694">FVID2_CCSF_BITS6_UNPACKED8_MSB_ALIGNED</a>   ((uint32_t) 0x16U)</td></tr>
+<tr class="memdesc:a61dddf1df3cf8174f8d3917ae3773694"><td class="mdescLeft"> </td><td class="mdescRight">6 Bits per Pixel unpacked in 8bit container. <br/></td></tr>
+<tr class="separator:a61dddf1df3cf8174f8d3917ae3773694"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a51b1da78a40589438bc13185782b319d"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a51b1da78a40589438bc13185782b319d"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a51b1da78a40589438bc13185782b319d">FVID2_CCSF_BITS7_UNPACKED8_MSB_ALIGNED</a>   ((uint32_t) 0x17U)</td></tr>
+<tr class="memdesc:a51b1da78a40589438bc13185782b319d"><td class="mdescLeft"> </td><td class="mdescRight">7 Bits per Pixel unpacked in 8bit container. <br/></td></tr>
+<tr class="separator:a51b1da78a40589438bc13185782b319d"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a813c1e0799dccb563604154a11881e6a"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a813c1e0799dccb563604154a11881e6a"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a813c1e0799dccb563604154a11881e6a">FVID2_CCSF_BITS8_UNPACKED12_MSB_ALIGNED</a>   ((uint32_t) 0x18U)</td></tr>
+<tr class="memdesc:a813c1e0799dccb563604154a11881e6a"><td class="mdescLeft"> </td><td class="mdescRight">8 Bits per Pixel unpacked in 12bit container. <br/></td></tr>
+<tr class="separator:a813c1e0799dccb563604154a11881e6a"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a1b8537b0791ad34722a02f0b8b4c304d"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a1b8537b0791ad34722a02f0b8b4c304d"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a1b8537b0791ad34722a02f0b8b4c304d">FVID2_CCSF_BITS8_UNPACKED16_MSB_ALIGNED</a>   ((uint32_t) 0x19U)</td></tr>
+<tr class="memdesc:a1b8537b0791ad34722a02f0b8b4c304d"><td class="mdescLeft"> </td><td class="mdescRight">8 Bits per Pixel unpacked in 12bit container. <br/></td></tr>
+<tr class="separator:a1b8537b0791ad34722a02f0b8b4c304d"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:af2178a61154ebb9c186a253a65409583"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="af2178a61154ebb9c186a253a65409583"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#af2178a61154ebb9c186a253a65409583">FVID2_CCSF_BITS9_UNPACKED16_MSB_ALIGNED</a>   ((uint32_t) 0x1AU)</td></tr>
+<tr class="memdesc:af2178a61154ebb9c186a253a65409583"><td class="mdescLeft"> </td><td class="mdescRight">9 Bits per Pixel unpacked in 16bit container. <br/></td></tr>
+<tr class="separator:af2178a61154ebb9c186a253a65409583"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a9085719b19b28a5cbad6a65d79d297f6"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a9085719b19b28a5cbad6a65d79d297f6"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a9085719b19b28a5cbad6a65d79d297f6">FVID2_CCSF_BITS10_UNPACKED16_MSB_ALIGNED</a>   ((uint32_t) 0x1BU)</td></tr>
+<tr class="memdesc:a9085719b19b28a5cbad6a65d79d297f6"><td class="mdescLeft"> </td><td class="mdescRight">10 Bits per Pixel unpacked in 16bit container <br/></td></tr>
+<tr class="separator:a9085719b19b28a5cbad6a65d79d297f6"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a8917b7740656c6d3832d67df9881ab8e"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a8917b7740656c6d3832d67df9881ab8e"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a8917b7740656c6d3832d67df9881ab8e">FVID2_CCSF_BITS11_UNPACKED16_MSB_ALIGNED</a>   ((uint32_t) 0x1CU)</td></tr>
+<tr class="memdesc:a8917b7740656c6d3832d67df9881ab8e"><td class="mdescLeft"> </td><td class="mdescRight">11 Bits per Pixel unpacked in 16bit container. <br/></td></tr>
+<tr class="separator:a8917b7740656c6d3832d67df9881ab8e"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a303e8ae9078fddebfaaa00ccbc8326fc"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a303e8ae9078fddebfaaa00ccbc8326fc"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a303e8ae9078fddebfaaa00ccbc8326fc">FVID2_CCSF_BITS12_UNPACKED16_MSB_ALIGNED</a>   ((uint32_t) 0x1DU)</td></tr>
+<tr class="memdesc:a303e8ae9078fddebfaaa00ccbc8326fc"><td class="mdescLeft"> </td><td class="mdescRight">12 Bits per Pixel, unpacked in 16bit container <br/></td></tr>
+<tr class="separator:a303e8ae9078fddebfaaa00ccbc8326fc"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a7bf5cca0a682a0b00276a425f1b8291b"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a7bf5cca0a682a0b00276a425f1b8291b"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a7bf5cca0a682a0b00276a425f1b8291b">FVID2_CCSF_BITS13_UNPACKED16_MSB_ALIGNED</a>   ((uint32_t) 0x1EU)</td></tr>
+<tr class="memdesc:a7bf5cca0a682a0b00276a425f1b8291b"><td class="mdescLeft"> </td><td class="mdescRight">13 Bits per Pixel unpacked in 16bit container. <br/></td></tr>
+<tr class="separator:a7bf5cca0a682a0b00276a425f1b8291b"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a76a2d25e1dc39f445ff81ecb1966ca18"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a76a2d25e1dc39f445ff81ecb1966ca18"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a76a2d25e1dc39f445ff81ecb1966ca18">FVID2_CCSF_BITS14_UNPACKED16_MSB_ALIGNED</a>   ((uint32_t) 0x1FU)</td></tr>
+<tr class="memdesc:a76a2d25e1dc39f445ff81ecb1966ca18"><td class="mdescLeft"> </td><td class="mdescRight">14 Bits per Pixel unpacked in 16bit container. <br/></td></tr>
+<tr class="separator:a76a2d25e1dc39f445ff81ecb1966ca18"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a56e845ec6128209b54547e4615bac029"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a56e845ec6128209b54547e4615bac029"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a56e845ec6128209b54547e4615bac029">FVID2_CCSF_BITS15_UNPACKED16_MSB_ALIGNED</a>   ((uint32_t) 0x20U)</td></tr>
+<tr class="memdesc:a56e845ec6128209b54547e4615bac029"><td class="mdescLeft"> </td><td class="mdescRight">15 Bits per Pixel unpacked in 16bit container. <br/></td></tr>
+<tr class="separator:a56e845ec6128209b54547e4615bac029"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:aa464f94a49c7e913fb48d3ad212b3063"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aa464f94a49c7e913fb48d3ad212b3063"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#aa464f94a49c7e913fb48d3ad212b3063">FVID2_CCSF_BITS20_UNPACKED24_MSB_ALIGNED</a>   ((uint32_t) 0x21U)</td></tr>
+<tr class="memdesc:aa464f94a49c7e913fb48d3ad212b3063"><td class="mdescLeft"> </td><td class="mdescRight">20 Bits per Pixel unpacked in 24bit container. <br/></td></tr>
+<tr class="separator:aa464f94a49c7e913fb48d3ad212b3063"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a5c9edcc22a7b1b990efc98af43912f49"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a5c9edcc22a7b1b990efc98af43912f49"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a5c9edcc22a7b1b990efc98af43912f49">FVID2_CCSF_MAX</a>   ((uint32_t) 0x22U)</td></tr>
+<tr class="memdesc:a5c9edcc22a7b1b990efc98af43912f49"><td class="mdescLeft"> </td><td class="mdescRight">Used by driver for validating the input parameters. <br/></td></tr>
+<tr class="separator:a5c9edcc22a7b1b990efc98af43912f49"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a82c2f41780c5f44ed27f7ebadf18a21d"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a82c2f41780c5f44ed27f7ebadf18a21d"></a>
+typedef uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a82c2f41780c5f44ed27f7ebadf18a21d">Fvid2_ColorCompStorageFmt</a></td></tr>
+<tr class="memdesc:a82c2f41780c5f44ed27f7ebadf18a21d"><td class="mdescLeft"> </td><td class="mdescRight">1 Bits per Pixel packed. <br/></td></tr>
+<tr class="separator:a82c2f41780c5f44ed27f7ebadf18a21d"><td class="memSeparator" colspan="2"> </td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
+Digital video interface width</h2></td></tr>
+<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrp3c1b13754a4f48db3bf8bcbc8a0b5d08"></a><a class="anchor" id="Fvid2_VideoIfWidth"></a></p>
+</td></tr>
+<tr class="memitem:a2dcc786e9b4d47f2408761a012f5760a"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a2dcc786e9b4d47f2408761a012f5760a"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a2dcc786e9b4d47f2408761a012f5760a">FVID2_VIFW_8BIT</a>   ((uint32_t) 0x00U)</td></tr>
+<tr class="memdesc:a2dcc786e9b4d47f2408761a012f5760a"><td class="mdescLeft"> </td><td class="mdescRight">8-bit interface. <br/></td></tr>
+<tr class="separator:a2dcc786e9b4d47f2408761a012f5760a"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ac3a717fe05ad4965118af833cf59e344"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ac3a717fe05ad4965118af833cf59e344"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#ac3a717fe05ad4965118af833cf59e344">FVID2_VIFW_10BIT</a>   ((uint32_t) 0x01U)</td></tr>
+<tr class="memdesc:ac3a717fe05ad4965118af833cf59e344"><td class="mdescLeft"> </td><td class="mdescRight">10-bit interface. <br/></td></tr>
+<tr class="separator:ac3a717fe05ad4965118af833cf59e344"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:aa4f84d19ce06a5392a81a6f377eca451"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aa4f84d19ce06a5392a81a6f377eca451"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#aa4f84d19ce06a5392a81a6f377eca451">FVID2_VIFW_12BIT</a>   ((uint32_t) 0x02U)</td></tr>
+<tr class="memdesc:aa4f84d19ce06a5392a81a6f377eca451"><td class="mdescLeft"> </td><td class="mdescRight">12-bit interface. <br/></td></tr>
+<tr class="separator:aa4f84d19ce06a5392a81a6f377eca451"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a231633928ad65ad5c614fd4c99e02f63"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a231633928ad65ad5c614fd4c99e02f63"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a231633928ad65ad5c614fd4c99e02f63">FVID2_VIFW_14BIT</a>   ((uint32_t) 0x03U)</td></tr>
+<tr class="memdesc:a231633928ad65ad5c614fd4c99e02f63"><td class="mdescLeft"> </td><td class="mdescRight">14-bit interface. <br/></td></tr>
+<tr class="separator:a231633928ad65ad5c614fd4c99e02f63"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a1e9c51d0e52003c568876305d8b5ac4a"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a1e9c51d0e52003c568876305d8b5ac4a"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a1e9c51d0e52003c568876305d8b5ac4a">FVID2_VIFW_16BIT</a>   ((uint32_t) 0x04U)</td></tr>
+<tr class="memdesc:a1e9c51d0e52003c568876305d8b5ac4a"><td class="mdescLeft"> </td><td class="mdescRight">16-bit interface. <br/></td></tr>
+<tr class="separator:a1e9c51d0e52003c568876305d8b5ac4a"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a5f82958aa532079ce0d121b6abfa6290"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a5f82958aa532079ce0d121b6abfa6290"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a5f82958aa532079ce0d121b6abfa6290">FVID2_VIFW_18BIT</a>   ((uint32_t) 0x05U)</td></tr>
+<tr class="memdesc:a5f82958aa532079ce0d121b6abfa6290"><td class="mdescLeft"> </td><td class="mdescRight">18-bit interface. <br/></td></tr>
+<tr class="separator:a5f82958aa532079ce0d121b6abfa6290"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a737fba3bfb51d5a0db8d273dc62c6f55"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a737fba3bfb51d5a0db8d273dc62c6f55"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a737fba3bfb51d5a0db8d273dc62c6f55">FVID2_VIFW_20BIT</a>   ((uint32_t) 0x06U)</td></tr>
+<tr class="memdesc:a737fba3bfb51d5a0db8d273dc62c6f55"><td class="mdescLeft"> </td><td class="mdescRight">20-bit interface. <br/></td></tr>
+<tr class="separator:a737fba3bfb51d5a0db8d273dc62c6f55"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:af0ca9fef4970890bdb6c3294e3488dd2"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="af0ca9fef4970890bdb6c3294e3488dd2"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#af0ca9fef4970890bdb6c3294e3488dd2">FVID2_VIFW_24BIT</a>   ((uint32_t) 0x07U)</td></tr>
+<tr class="memdesc:af0ca9fef4970890bdb6c3294e3488dd2"><td class="mdescLeft"> </td><td class="mdescRight">24-bit interface. <br/></td></tr>
+<tr class="separator:af0ca9fef4970890bdb6c3294e3488dd2"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ab662f4e73161ba1c2b0def811521f144"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ab662f4e73161ba1c2b0def811521f144"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#ab662f4e73161ba1c2b0def811521f144">FVID2_VIFW_30BIT</a>   ((uint32_t) 0x08U)</td></tr>
+<tr class="memdesc:ab662f4e73161ba1c2b0def811521f144"><td class="mdescLeft"> </td><td class="mdescRight">30-bit interface. <br/></td></tr>
+<tr class="separator:ab662f4e73161ba1c2b0def811521f144"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a3bbc392f936b3fc101d207b191832032"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a3bbc392f936b3fc101d207b191832032"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a3bbc392f936b3fc101d207b191832032">FVID2_VIFW_36BIT</a>   ((uint32_t) 0x09U)</td></tr>
+<tr class="memdesc:a3bbc392f936b3fc101d207b191832032"><td class="mdescLeft"> </td><td class="mdescRight">36-bit interface. <br/></td></tr>
+<tr class="separator:a3bbc392f936b3fc101d207b191832032"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ac0f2644123a9cfad25d5d1394cd83b07"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ac0f2644123a9cfad25d5d1394cd83b07"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#ac0f2644123a9cfad25d5d1394cd83b07">FVID2_VIFW_1LANES</a>   ((uint32_t) 0x0AU)</td></tr>
+<tr class="memdesc:ac0f2644123a9cfad25d5d1394cd83b07"><td class="mdescLeft"> </td><td class="mdescRight">CSI2 specific - 1 data lanes. <br/></td></tr>
+<tr class="separator:ac0f2644123a9cfad25d5d1394cd83b07"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a0bf298ec713b45e4412921b840700b21"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a0bf298ec713b45e4412921b840700b21"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a0bf298ec713b45e4412921b840700b21">FVID2_VIFW_2LANES</a>   ((uint32_t) 0x0BU)</td></tr>
+<tr class="memdesc:a0bf298ec713b45e4412921b840700b21"><td class="mdescLeft"> </td><td class="mdescRight">CSI2 specific - 2 data lanes. <br/></td></tr>
+<tr class="separator:a0bf298ec713b45e4412921b840700b21"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ab6c39f963bb8d0873cd040f80df74528"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ab6c39f963bb8d0873cd040f80df74528"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#ab6c39f963bb8d0873cd040f80df74528">FVID2_VIFW_3LANES</a>   ((uint32_t) 0x0CU)</td></tr>
+<tr class="memdesc:ab6c39f963bb8d0873cd040f80df74528"><td class="mdescLeft"> </td><td class="mdescRight">CSI2 specific - 3 data lanes. <br/></td></tr>
+<tr class="separator:ab6c39f963bb8d0873cd040f80df74528"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a855c0790a50e48407a58b4e6682005d8"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a855c0790a50e48407a58b4e6682005d8"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a855c0790a50e48407a58b4e6682005d8">FVID2_VIFW_4LANES</a>   ((uint32_t) 0x0DU)</td></tr>
+<tr class="memdesc:a855c0790a50e48407a58b4e6682005d8"><td class="mdescLeft"> </td><td class="mdescRight">CSI2 / LVDS specific - 4 data lanes. <br/></td></tr>
+<tr class="separator:a855c0790a50e48407a58b4e6682005d8"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a3fc89d365c319b7999dfab0a24269105"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a3fc89d365c319b7999dfab0a24269105"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a3fc89d365c319b7999dfab0a24269105">FVID2_VIFW_MAX</a>   ((uint32_t) 0x0EU)</td></tr>
+<tr class="memdesc:a3fc89d365c319b7999dfab0a24269105"><td class="mdescLeft"> </td><td class="mdescRight">Maximum modes. <br/></td></tr>
+<tr class="separator:a3fc89d365c319b7999dfab0a24269105"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a3644341e8e51f60794fb15f219f0a5f7"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a3644341e8e51f60794fb15f219f0a5f7"></a>
+typedef uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html#a3644341e8e51f60794fb15f219f0a5f7">Fvid2_VideoIfWidth</a></td></tr>
+<tr class="memdesc:a3644341e8e51f60794fb15f219f0a5f7"><td class="mdescLeft"> </td><td class="mdescRight">8-bit interface. <br/></td></tr>
+<tr class="separator:a3644341e8e51f60794fb15f219f0a5f7"><td class="memSeparator" colspan="2"> </td></tr>
+</table>
+<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
+<div class="textblock"><p>CSL FVID2 Datatypes. </p>
+</div><h2 class="groupheader">Macro Definition Documentation</h2>
+<a class="anchor" id="aef0d63f7f96514278ebda30f1c0bec74"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">#define FVID2_MAX_PLANES</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<b>Value:</b><div class="fragment"><div class="line">(<a class="code" href="csl__fvid2__data_types_8h.html#a6fc0d1953df344af3840c1fa516ec270">FVID2_MAX_FIELDS</a> * <a class="code" href="csl__fvid2__data_types_8h.html#a19b6ef6e426b64e15bc08ce46c644aef">\</a></div>
+<div class="line"><a class="code" href="csl__fvid2__data_types_8h.html#a19b6ef6e426b64e15bc08ce46c644aef"> FVID2_MAX_PLANES_PER_FIELD</a>)</div>
+<div class="ttc" id="csl__fvid2__data_types_8h_html_a19b6ef6e426b64e15bc08ce46c644aef"><div class="ttname"><a href="csl__fvid2__data_types_8h.html#a19b6ef6e426b64e15bc08ce46c644aef">FVID2_MAX_PLANES_PER_FIELD</a></div><div class="ttdeci">#define FVID2_MAX_PLANES_PER_FIELD</div><div class="ttdoc">This macro determines the maximum number of planes/address used to represent a video buffer per field...</div><div class="ttdef"><b>Definition:</b> csl_fvid2_dataTypes.h:152</div></div>
+<div class="ttc" id="csl__fvid2__data_types_8h_html_a6fc0d1953df344af3840c1fa516ec270"><div class="ttname"><a href="csl__fvid2__data_types_8h.html#a6fc0d1953df344af3840c1fa516ec270">FVID2_MAX_FIELDS</a></div><div class="ttdeci">#define FVID2_MAX_FIELDS</div><div class="ttdoc">Number of fields - top and bottom. Used for allocating address pointers for both the fields...</div><div class="ttdef"><b>Definition:</b> csl_fvid2_dataTypes.h:144</div></div>
+</div><!-- fragment -->
+<p>This macro determines the maximum number of planes/address used to represent a video buffer. Currently this is set to 6 to support the maximum pointers required for two fields of YUV/RGB planar format - Y, Cb and Cr or R, G and B. </p>
+
+</div>
+</div>
+<h2 class="groupheader">Enumeration Type Documentation</h2>
+<a class="anchor" id="ac5d9776b0da6459f3f9cfbcbce8eec18"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">enum <a class="el" href="csl__fvid2__data_types_8h.html#ac5d9776b0da6459f3f9cfbcbce8eec18">Fvid2_BayerColorComp</a></td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+
+<p>Enum for selecting bayer color components for odd/even pixel position on odd/even lines, Also used for specifying gain and offset in White balance config for each color component. </p>
+<table class="fieldtable">
+<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><em><a class="anchor" id="ac5d9776b0da6459f3f9cfbcbce8eec18ae8725e59cc3be75abc7b2211be865db3"></a>FVID2_BAYER_COLOR_COMP_R</em> </td><td class="fielddoc">
+<p>Red Color Component in Bayer image </p>
+</td></tr>
+<tr><td class="fieldname"><em><a class="anchor" id="ac5d9776b0da6459f3f9cfbcbce8eec18a8a20bb44d83f09c3216382a281468f10"></a>FVID2_BAYER_COLOR_COMP_GR</em> </td><td class="fielddoc">
+<p>GreenR Color Component in Bayer image </p>
+</td></tr>
+<tr><td class="fieldname"><em><a class="anchor" id="ac5d9776b0da6459f3f9cfbcbce8eec18af8760d6393d606fa75b0948835d026f8"></a>FVID2_BAYER_COLOR_COMP_GB</em> </td><td class="fielddoc">
+<p>GreenB Color Component in Bayer image </p>
+</td></tr>
+<tr><td class="fieldname"><em><a class="anchor" id="ac5d9776b0da6459f3f9cfbcbce8eec18aab7a458ffc41a81da35d21b7160745d0"></a>FVID2_BAYER_COLOR_COMP_B</em> </td><td class="fielddoc">
+<p>Blue Color Component in Bayer image </p>
+</td></tr>
+<tr><td class="fieldname"><em><a class="anchor" id="ac5d9776b0da6459f3f9cfbcbce8eec18ae4b13df43936976b20342bcfe77957a3"></a>FVID2_BAYER_COLOR_COMP_MAX</em> </td><td class="fielddoc">
+<p>This should be the last number, used in specifying array size </p>
+</td></tr>
+</table>
+
+</div>
+</div>
+<a class="anchor" id="a6372ae9694a790a94e2da8e06d76b540"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">enum <a class="el" href="csl__fvid2__data_types_8h.html#a6372ae9694a790a94e2da8e06d76b540">Fvid2_ChromaPos</a></td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+
+<p>Enum for selecting chroma position in chroma up or down sampler. </p>
+<table class="fieldtable">
+<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><em><a class="anchor" id="a6372ae9694a790a94e2da8e06d76b540a2d0e94bc80160340b9f3ea5ef2df480a"></a>FVID2_CHROMA_POS_COSITED</em> </td><td class="fielddoc">
+<p>Chroma is cosited </p>
+</td></tr>
+<tr><td class="fieldname"><em><a class="anchor" id="a6372ae9694a790a94e2da8e06d76b540a354971423ce04887bfb431e05790568c"></a>FVID2_CHROMA_POS_CENTERED</em> </td><td class="fielddoc">
+<p>Chroma is Centered </p>
+</td></tr>
+</table>
+
+</div>
+</div>
+<a class="anchor" id="a248e190fab40aca929969c432068a099"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">enum <a class="el" href="csl__fvid2__data_types_8h.html#a248e190fab40aca929969c432068a099">Fvid2_FrameStatus</a></td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+
+<p>Enum for state of the FVID2 frame. Typically used for marking FVID2_frame as either SUBMITTED, Completed/Done, Errorneous at the time of flush/abort when driver returns back all the frames. </p>
+<table class="fieldtable">
+<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><em><a class="anchor" id="a248e190fab40aca929969c432068a099adf9e647770fecfbd9ace849d2db8f988"></a>FVID2_FRAME_STATUS_INIT</em> </td><td class="fielddoc">
+<p>FVID2 Frame is initialized using init function </p>
+</td></tr>
+<tr><td class="fieldname"><em><a class="anchor" id="a248e190fab40aca929969c432068a099a696c6a4cbd00246b5c1e4370fa302055"></a>FVID2_FRAME_STATUS_COMPLETED</em> </td><td class="fielddoc">
+<p>Frame processing is completed and can be used in the application </p>
+</td></tr>
+<tr><td class="fieldname"><em><a class="anchor" id="a248e190fab40aca929969c432068a099aeefebb0a00827e6d2362df182c6e0709"></a>FVID2_FRAME_STATUS_PENDING</em> </td><td class="fielddoc">
+<p>Frame processing is still pending, used for the frames which are dequeued before being processed </p>
+</td></tr>
+<tr><td class="fieldname"><em><a class="anchor" id="a248e190fab40aca929969c432068a099afb0044f14c3f1d87d92611b1b13c3a02"></a>FVID2_FRAME_STATUS_SUBMITTED</em> </td><td class="fielddoc">
+<p>Frame is just submitted to the driver </p>
+</td></tr>
+<tr><td class="fieldname"><em><a class="anchor" id="a248e190fab40aca929969c432068a099ac9611a6508b8e02547b4706cc38ad89d"></a>FVID2_FRAME_STATUS_ERROR</em> </td><td class="fielddoc">
+<p>Frame has error </p>
+</td></tr>
+<tr><td class="fieldname"><em><a class="anchor" id="a248e190fab40aca929969c432068a099a43d4d377646d7279138602a7aeac3f72"></a>FVID2_FRAME_STATUS_ABORTED</em> </td><td class="fielddoc">
+<p>Frame processing is aborted, used for the frames which are force moved to output queue </p>
+</td></tr>
+<tr><td class="fieldname"><em><a class="anchor" id="a248e190fab40aca929969c432068a099abebee14dd307042e25082acf1b1270f5"></a>FVID2_FRAME_STATUS_OVERFLOW</em> </td><td class="fielddoc">
+<p>The IP processing this frame experienced and overflow of its internal buffers. Indicates severe error </p>
+</td></tr>
+<tr><td class="fieldname"><em><a class="anchor" id="a248e190fab40aca929969c432068a099a475443372b2fb2763923f7d58b5f467a"></a>FVID2_FRAME_STATUS_ECC_CORRECTED</em> </td><td class="fielddoc">
+<p>There was 1 bit ECC error, which was corrected. Provided the hardware and/or protocol used to process this frame supports ECC </p>
+</td></tr>
+<tr><td class="fieldname"><em><a class="anchor" id="a248e190fab40aca929969c432068a099a84c41401ba6a29d9ca60b93a48803202"></a>FVID2_FRAME_STATUS_CRC_ERROR</em> </td><td class="fielddoc">
+<p>CRC errors were detected, the integrity of the data is not guaranteed. Provided the hardware and/or protocol used to process this frame supports CRC </p>
+</td></tr>
+<tr><td class="fieldname"><em><a class="anchor" id="a248e190fab40aca929969c432068a099a38f88ca4ff3a06f88914c71a5c1b7c0e"></a>FVID2_FRAME_STATUS_ECC_ERROR</em> </td><td class="fielddoc">
+<p>There were multiple bit ECC error, which was could not be corrected. Provided the hardware and/or protocol used to process this frame supports ECC </p>
+</td></tr>
+<tr><td class="fieldname"><em><a class="anchor" id="a248e190fab40aca929969c432068a099ae0e4d1baff68faaadda86f76db875869"></a>FVID2_FRAME_STATUS_MAX</em> </td><td class="fielddoc">
+<p>This should be the last number, </p>
+</td></tr>
+</table>
+
+</div>
+</div>
+<a class="anchor" id="a4e1d4b630095a3e5f9d560b839603a8e"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">enum <a class="el" href="csl__fvid2__data_types_8h.html#a4e1d4b630095a3e5f9d560b839603a8e">Fvid2_VideoIfMode</a></td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+
+<p>Video interface mode. </p>
+<table class="fieldtable">
+<tr><th colspan="2">Enumerator</th></tr><tr><td class="fieldname"><em><a class="anchor" id="a4e1d4b630095a3e5f9d560b839603a8ea0c1ebff799492bc87e0947ea5b4af1e6"></a>FVID2_VIFM_SCH_ES</em> </td><td class="fielddoc">
+<p>Single Channel non multiplexed mode. </p>
+</td></tr>
+<tr><td class="fieldname"><em><a class="anchor" id="a4e1d4b630095a3e5f9d560b839603a8ea7e22126a15add08aeabce4216492c88b"></a>FVID2_VIFM_MCH_LINE_MUX_ES</em> </td><td class="fielddoc">
+<p>Multi-channel line-multiplexed mode. </p>
+</td></tr>
+<tr><td class="fieldname"><em><a class="anchor" id="a4e1d4b630095a3e5f9d560b839603a8ea07b6e18e02112c367d6bd3b380d2d9d3"></a>FVID2_VIFM_MCH_PIXEL_MUX_ES</em> </td><td class="fielddoc">
+<p>Multi-channel pixel muxed. </p>
+</td></tr>
+<tr><td class="fieldname"><em><a class="anchor" id="a4e1d4b630095a3e5f9d560b839603a8ea7ffc6821187a28919e2ee5f8723199b1"></a>FVID2_VIFM_SCH_DS_HSYNC_VBLK</em> </td><td class="fielddoc">
+<p>Single Channel non multiplexed discrete sync mode with HSYNC and VBLK as control signals. </p>
+</td></tr>
+<tr><td class="fieldname"><em><a class="anchor" id="a4e1d4b630095a3e5f9d560b839603a8ea41dea0d5f63dd2ea51de8030460f6527"></a>FVID2_VIFM_SCH_DS_HSYNC_VSYNC</em> </td><td class="fielddoc">
+<p>Single Channel non multiplexed discrete sync mode with HSYNC and VSYNC as control signals. </p>
+</td></tr>
+<tr><td class="fieldname"><em><a class="anchor" id="a4e1d4b630095a3e5f9d560b839603a8ea2fa8c574decaca5d94b93a6c8aa2ae64"></a>FVID2_VIFM_SCH_DS_AVID_VBLK</em> </td><td class="fielddoc">
+<p>Single Channel non multiplexed discrete sync mode with AVID and VBLK as control signals. </p>
+</td></tr>
+<tr><td class="fieldname"><em><a class="anchor" id="a4e1d4b630095a3e5f9d560b839603a8ea901482ffa323be1fb48302f7404930a6"></a>FVID2_VIFM_SCH_DS_AVID_VSYNC</em> </td><td class="fielddoc">
+<p>Single Channel non multiplexed discrete sync mode with AVID and VBLK as control signals. </p>
+</td></tr>
+<tr><td class="fieldname"><em><a class="anchor" id="a4e1d4b630095a3e5f9d560b839603a8eac7aceedd75323567a399f68742d54ccb"></a>FVID2_VIFM_MCH_LINE_MUX_SPLIT_LINE_ES</em> </td><td class="fielddoc">
+<p>Multi-channel line-multiplexed mode - split line mode. </p>
+</td></tr>
+<tr><td class="fieldname"><em><a class="anchor" id="a4e1d4b630095a3e5f9d560b839603a8ea0caef0a1234afe67eed22370729d04f8"></a>FVID2_VIFM_SCH_CSI2</em> </td><td class="fielddoc">
+<p>Single channel capture via CSI2 interface </p>
+</td></tr>
+<tr><td class="fieldname"><em><a class="anchor" id="a4e1d4b630095a3e5f9d560b839603a8ea83e693e66bda0561fb9c4cc81733fa87"></a>FVID2_VIFM_SCH_LVDS</em> </td><td class="fielddoc">
+<p>Single channel capture via LVDS interface </p>
+</td></tr>
+<tr><td class="fieldname"><em><a class="anchor" id="a4e1d4b630095a3e5f9d560b839603a8ea03c1d8ab4e4325886e9c8553f0c6708f"></a>FVID2_VIFM_SCH_CPI</em> </td><td class="fielddoc">
+<p>Single channel capture via Parallel interface </p>
+</td></tr>
+<tr><td class="fieldname"><em><a class="anchor" id="a4e1d4b630095a3e5f9d560b839603a8ea06e8f99dd0b137efcc6ca8e2e2f15527"></a>FVID2_VIFM_MAX</em> </td><td class="fielddoc">
+<p>Should be the last value of this enumeration. Will be used by driver for validating the input parameters. </p>
+</td></tr>
+</table>
+
+</div>
+</div>
+<h2 class="groupheader">Function Documentation</h2>
+<a class="anchor" id="a8938f5c1b9a0655d7dbb4aabb11a6c16"></a>
+<div class="memitem">
+<div class="memproto">
+<table class="mlabels">
+ <tr>
+ <td class="mlabels-left">
+ <table class="memname">
+ <tr>
+ <td class="memname">static uint32_t Fvid2_BayerColorIndex </td>
+ <td>(</td>
+ <td class="paramtype">uint32_t </td>
+ <td class="paramname"><em>dataFmt</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">uint32_t </td>
+ <td class="paramname"><em>color</em> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td></td>
+ </tr>
+ </table>
+ </td>
+ <td class="mlabels-right">
+<span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span> </td>
+ </tr>
+</table>
+</div><div class="memdoc">
+
+<p>Function to get the index of the color for bayer data format. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">dataFmt</td><td>[IN] Bayer Data Format For valid values see <a class="el" href="csl__fvid2__data_types_8h.html#a9f5096b017d15ffecdcc0990fd1b031a" title="YUV 422 Interleaved format - UYVY. ">Fvid2_DataFormat</a>. </td></tr>
+ <tr><td class="paramname">color</td><td>[IN] Bayer Color Component For valid values see <a class="el" href="csl__fvid2__data_types_8h.html#ac5d9776b0da6459f3f9cfbcbce8eec18" title="Enum for selecting bayer color components for odd/even pixel position on odd/even lines...">Fvid2_BayerColorComp</a></td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>Returns index of the color component. </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ac486d696661acd7c496e032ee598a9c4"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">const Char* Fvid2_getDataFmtString </td>
+ <td>(</td>
+ <td class="paramtype">uint32_t </td>
+ <td class="paramname"><em>dataFmt</em></td><td>)</td>
+ <td></td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+
+<p>Function to get the name of the data format in printable string. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">dataFmt</td><td>[IN] Data format to get the name. For valid values see <a class="el" href="csl__fvid2__data_types_8h.html#a9f5096b017d15ffecdcc0990fd1b031a" title="YUV 422 Interleaved format - UYVY. ">Fvid2_DataFormat</a>.</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>Returns a const pointer to the string. If the data format is not known, then it return the string as "UNKNOWN". </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="a0ff414941310bac0f142807d5ce4992d"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">int32_t Fvid2_getModeInfo </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="struct_fvid2___mode_info.html">Fvid2_ModeInfo</a> * </td>
+ <td class="paramname"><em>modeInfo</em></td><td>)</td>
+ <td></td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+
+<p>Function to get the information about various FVID2 modes/standards. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">modeInfo</td><td>[OUT] Pointer to <a class="el" href="struct_fvid2___mode_info.html" title="FVID2 Mode information structure. ">Fvid2_ModeInfo</a> structure where the information is filled.</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>FVID2_SOK on success, else appropriate FVID2 error code on failure. </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="a5bb999e03ac1bac7da6b62f004f17bf9"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">const Char* Fvid2_getStandardString </td>
+ <td>(</td>
+ <td class="paramtype">uint32_t </td>
+ <td class="paramname"><em>standard</em></td><td>)</td>
+ <td></td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+
+<p>Function to get the name of the standard in printable string. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">standard</td><td>[IN] Standard to get the name. For valid values see <a class="el" href="csl__fvid2__data_types_8h.html#aaa2667d105d557f254c20b87534ed4b6" title="720x480 30FPS interlaced NTSC standard. ">Fvid2_Standard</a>.</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>Returns a const pointer to the string. If the standard is not known, then it return the string as "UNKNOWN". </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="a7b92c32c5cd073fd09ca32a655065048"></a>
+<div class="memitem">
+<div class="memproto">
+<table class="mlabels">
+ <tr>
+ <td class="mlabels-left">
+ <table class="memname">
+ <tr>
+ <td class="memname">static int32_t Fvid2_isDataFmtBayer </td>
+ <td>(</td>
+ <td class="paramtype">uint32_t </td>
+ <td class="paramname"><em>dataFmt</em></td><td>)</td>
+ <td></td>
+ </tr>
+ </table>
+ </td>
+ <td class="mlabels-right">
+<span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span> </td>
+ </tr>
+</table>
+</div><div class="memdoc">
+
+<p>Function to check whether a data format is Bayer with MosaicPattern. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">dataFmt</td><td>[IN] Data format to check. For valid values see <a class="el" href="csl__fvid2__data_types_8h.html#a9f5096b017d15ffecdcc0990fd1b031a" title="YUV 422 Interleaved format - UYVY. ">Fvid2_DataFormat</a>.</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>Returns TRUE if data format is Bayer, FALSE otherwise. </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="a7a17697bd4677e5c0e4611c91821c5b2"></a>
+<div class="memitem">
+<div class="memproto">
+<table class="mlabels">
+ <tr>
+ <td class="mlabels-left">
+ <table class="memname">
+ <tr>
+ <td class="memname">static int32_t Fvid2_isDataFmtRgb </td>
+ <td>(</td>
+ <td class="paramtype">uint32_t </td>
+ <td class="paramname"><em>dataFmt</em></td><td>)</td>
+ <td></td>
+ </tr>
+ </table>
+ </td>
+ <td class="mlabels-right">
+<span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span> </td>
+ </tr>
+</table>
+</div><div class="memdoc">
+
+<p>Function to check whether a data format is RGB . </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">dataFmt</td><td>[IN] Data format to check. For valid values see <a class="el" href="csl__fvid2__data_types_8h.html#a9f5096b017d15ffecdcc0990fd1b031a" title="YUV 422 Interleaved format - UYVY. ">Fvid2_DataFormat</a>.</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>Returns TRUE if data format is RGB , FALSE otherwise. </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="adc25f711515d08d8cb9cb5752135f969"></a>
+<div class="memitem">
+<div class="memproto">
+<table class="mlabels">
+ <tr>
+ <td class="mlabels-left">
+ <table class="memname">
+ <tr>
+ <td class="memname">static int32_t Fvid2_isDataFmtRgb16bit </td>
+ <td>(</td>
+ <td class="paramtype">uint32_t </td>
+ <td class="paramname"><em>dataFmt</em></td><td>)</td>
+ <td></td>
+ </tr>
+ </table>
+ </td>
+ <td class="mlabels-right">
+<span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span> </td>
+ </tr>
+</table>
+</div><div class="memdoc">
+
+<p>Function to check whether a data format is RGB 16-bit. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">dataFmt</td><td>[IN] Data format to check. For valid values see <a class="el" href="csl__fvid2__data_types_8h.html#a9f5096b017d15ffecdcc0990fd1b031a" title="YUV 422 Interleaved format - UYVY. ">Fvid2_DataFormat</a>.</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>Returns TRUE if data format is RGB 16-bit, FALSE otherwise. </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="a933b005f12a4845f842d978718560099"></a>
+<div class="memitem">
+<div class="memproto">
+<table class="mlabels">
+ <tr>
+ <td class="mlabels-left">
+ <table class="memname">
+ <tr>
+ <td class="memname">static int32_t Fvid2_isDataFmtRgb24bit </td>
+ <td>(</td>
+ <td class="paramtype">uint32_t </td>
+ <td class="paramname"><em>dataFmt</em></td><td>)</td>
+ <td></td>
+ </tr>
+ </table>
+ </td>
+ <td class="mlabels-right">
+<span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span> </td>
+ </tr>
+</table>
+</div><div class="memdoc">
+
+<p>Function to check whether a data format is RGB 24-bit. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">dataFmt</td><td>[IN] Data format to check. For valid values see <a class="el" href="csl__fvid2__data_types_8h.html#a9f5096b017d15ffecdcc0990fd1b031a" title="YUV 422 Interleaved format - UYVY. ">Fvid2_DataFormat</a>.</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>Returns TRUE if data format is RGB 24-bit, FALSE otherwise. </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="a83e52e7870da61828fccff98d4985f77"></a>
+<div class="memitem">
+<div class="memproto">
+<table class="mlabels">
+ <tr>
+ <td class="mlabels-left">
+ <table class="memname">
+ <tr>
+ <td class="memname">static int32_t Fvid2_isDataFmtRgb32bit </td>
+ <td>(</td>
+ <td class="paramtype">uint32_t </td>
+ <td class="paramname"><em>dataFmt</em></td><td>)</td>
+ <td></td>
+ </tr>
+ </table>
+ </td>
+ <td class="mlabels-right">
+<span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span> </td>
+ </tr>
+</table>
+</div><div class="memdoc">
+
+<p>Function to check whether a data format is RGB 32-bit. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">dataFmt</td><td>[IN] Data format to check. For valid values see <a class="el" href="csl__fvid2__data_types_8h.html#a9f5096b017d15ffecdcc0990fd1b031a" title="YUV 422 Interleaved format - UYVY. ">Fvid2_DataFormat</a>.</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>Returns TRUE if data format is RGB 32-bit, FALSE otherwise. </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="addaf6c10b34dbfbe5b9e892c4e08a90f"></a>
+<div class="memitem">
+<div class="memproto">
+<table class="mlabels">
+ <tr>
+ <td class="mlabels-left">
+ <table class="memname">
+ <tr>
+ <td class="memname">static int32_t Fvid2_isDataFmtRgb64bit </td>
+ <td>(</td>
+ <td class="paramtype">uint32_t </td>
+ <td class="paramname"><em>dataFmt</em></td><td>)</td>
+ <td></td>
+ </tr>
+ </table>
+ </td>
+ <td class="mlabels-right">
+<span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span> </td>
+ </tr>
+</table>
+</div><div class="memdoc">
+
+<p>Function to check whether a data format is RGB 64 bit. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">dataFmt</td><td>[IN] Data format to check. For valid values see <a class="el" href="csl__fvid2__data_types_8h.html#a9f5096b017d15ffecdcc0990fd1b031a" title="YUV 422 Interleaved format - UYVY. ">Fvid2_DataFormat</a>.</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>Returns TRUE if data format is RGB 64-bit, FALSE otherwise. </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="a233fa36d9cfcde59468c7ddc8a8990e2"></a>
+<div class="memitem">
+<div class="memproto">
+<table class="mlabels">
+ <tr>
+ <td class="mlabels-left">
+ <table class="memname">
+ <tr>
+ <td class="memname">static int32_t Fvid2_isDataFmtSemiPlanar </td>
+ <td>(</td>
+ <td class="paramtype">uint32_t </td>
+ <td class="paramname"><em>dataFmt</em></td><td>)</td>
+ <td></td>
+ </tr>
+ </table>
+ </td>
+ <td class="mlabels-right">
+<span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span> </td>
+ </tr>
+</table>
+</div><div class="memdoc">
+
+<p>Function to check whether a data format is semi-planar. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">dataFmt</td><td>[IN] Data format to check. For valid values see <a class="el" href="csl__fvid2__data_types_8h.html#a9f5096b017d15ffecdcc0990fd1b031a" title="YUV 422 Interleaved format - UYVY. ">Fvid2_DataFormat</a>.</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>Returns TRUE if data format is semi-planar, FALSE otherwise. </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="abcb80b193d95790e23d51f7a04e232ed"></a>
+<div class="memitem">
+<div class="memproto">
+<table class="mlabels">
+ <tr>
+ <td class="mlabels-left">
+ <table class="memname">
+ <tr>
+ <td class="memname">static int32_t Fvid2_isDataFmtYuv </td>
+ <td>(</td>
+ <td class="paramtype">uint32_t </td>
+ <td class="paramname"><em>dataFmt</em></td><td>)</td>
+ <td></td>
+ </tr>
+ </table>
+ </td>
+ <td class="mlabels-right">
+<span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span> </td>
+ </tr>
+</table>
+</div><div class="memdoc">
+
+<p>Function to check whether a data format is YUV. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">dataFmt</td><td>[IN] Data format to check. For valid values see <a class="el" href="csl__fvid2__data_types_8h.html#a9f5096b017d15ffecdcc0990fd1b031a" title="YUV 422 Interleaved format - UYVY. ">Fvid2_DataFormat</a>.</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>Returns TRUE if data format is YUV, FALSE otherwise. </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="af103bb1d4a91a5112e2418d06ed9c6ad"></a>
+<div class="memitem">
+<div class="memproto">
+<table class="mlabels">
+ <tr>
+ <td class="mlabels-left">
+ <table class="memname">
+ <tr>
+ <td class="memname">static int32_t Fvid2_isDataFmtYuv420 </td>
+ <td>(</td>
+ <td class="paramtype">uint32_t </td>
+ <td class="paramname"><em>dataFmt</em></td><td>)</td>
+ <td></td>
+ </tr>
+ </table>
+ </td>
+ <td class="mlabels-right">
+<span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span> </td>
+ </tr>
+</table>
+</div><div class="memdoc">
+
+<p>Function to check whether a data format is YUV420. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">dataFmt</td><td>[IN] Data format to check. For valid values see <a class="el" href="csl__fvid2__data_types_8h.html#a9f5096b017d15ffecdcc0990fd1b031a" title="YUV 422 Interleaved format - UYVY. ">Fvid2_DataFormat</a>.</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>Returns TRUE if data format is YUV420, FALSE otherwise. </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="a453391f7467c4aeec2968c29b77d5e99"></a>
+<div class="memitem">
+<div class="memproto">
+<table class="mlabels">
+ <tr>
+ <td class="mlabels-left">
+ <table class="memname">
+ <tr>
+ <td class="memname">static int32_t Fvid2_isDataFmtYuv420Sp </td>
+ <td>(</td>
+ <td class="paramtype">uint32_t </td>
+ <td class="paramname"><em>dataFmt</em></td><td>)</td>
+ <td></td>
+ </tr>
+ </table>
+ </td>
+ <td class="mlabels-right">
+<span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span> </td>
+ </tr>
+</table>
+</div><div class="memdoc">
+
+<p>Function to check whether a data format is YUV420SP. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">dataFmt</td><td>[IN] Data format to check. For valid values see <a class="el" href="csl__fvid2__data_types_8h.html#a9f5096b017d15ffecdcc0990fd1b031a" title="YUV 422 Interleaved format - UYVY. ">Fvid2_DataFormat</a>.</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>Returns TRUE if data format is YUV420SP, FALSE otherwise. </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ab54967003a826f9becaf1fb346609658"></a>
+<div class="memitem">
+<div class="memproto">
+<table class="mlabels">
+ <tr>
+ <td class="mlabels-left">
+ <table class="memname">
+ <tr>
+ <td class="memname">static int32_t Fvid2_isDataFmtYuv422 </td>
+ <td>(</td>
+ <td class="paramtype">uint32_t </td>
+ <td class="paramname"><em>dataFmt</em></td><td>)</td>
+ <td></td>
+ </tr>
+ </table>
+ </td>
+ <td class="mlabels-right">
+<span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span> </td>
+ </tr>
+</table>
+</div><div class="memdoc">
+
+<p>Function to check whether a data format is YUV422. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">dataFmt</td><td>[IN] Data format to check. For valid values see <a class="el" href="csl__fvid2__data_types_8h.html#a9f5096b017d15ffecdcc0990fd1b031a" title="YUV 422 Interleaved format - UYVY. ">Fvid2_DataFormat</a>.</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>Returns TRUE if data format is YUV422, FALSE otherwise. </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ab5751442713ba8a70dbaa097be64a891"></a>
+<div class="memitem">
+<div class="memproto">
+<table class="mlabels">
+ <tr>
+ <td class="mlabels-left">
+ <table class="memname">
+ <tr>
+ <td class="memname">static int32_t Fvid2_isDataFmtYuv422I </td>
+ <td>(</td>
+ <td class="paramtype">uint32_t </td>
+ <td class="paramname"><em>dataFmt</em></td><td>)</td>
+ <td></td>
+ </tr>
+ </table>
+ </td>
+ <td class="mlabels-right">
+<span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span> </td>
+ </tr>
+</table>
+</div><div class="memdoc">
+
+<p>Function to check whether a data format is YUV422 interleaved. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">dataFmt</td><td>[IN] Data format to check. For valid values see <a class="el" href="csl__fvid2__data_types_8h.html#a9f5096b017d15ffecdcc0990fd1b031a" title="YUV 422 Interleaved format - UYVY. ">Fvid2_DataFormat</a>.</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>Returns TRUE if data format is YUV422 interleaved, FALSE otherwise. </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="a8ac3f62f103515fa9ccc940448d4ebf5"></a>
+<div class="memitem">
+<div class="memproto">
+<table class="mlabels">
+ <tr>
+ <td class="mlabels-left">
+ <table class="memname">
+ <tr>
+ <td class="memname">static int32_t Fvid2_isDataFmtYuv422Sp </td>
+ <td>(</td>
+ <td class="paramtype">uint32_t </td>
+ <td class="paramname"><em>dataFmt</em></td><td>)</td>
+ <td></td>
+ </tr>
+ </table>
+ </td>
+ <td class="mlabels-right">
+<span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span> </td>
+ </tr>
+</table>
+</div><div class="memdoc">
+
+<p>Function to check whether a data format is YUV422SP. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">dataFmt</td><td>[IN] Data format to check. For valid values see <a class="el" href="csl__fvid2__data_types_8h.html#a9f5096b017d15ffecdcc0990fd1b031a" title="YUV 422 Interleaved format - UYVY. ">Fvid2_DataFormat</a>.</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>Returns TRUE if data format is YUV422SP, FALSE otherwise. </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="a906531b9be45f2bd528e1fac44b00340"></a>
+<div class="memitem">
+<div class="memproto">
+<table class="mlabels">
+ <tr>
+ <td class="mlabels-left">
+ <table class="memname">
+ <tr>
+ <td class="memname">static int32_t Fvid2_isDataFmtYuv444 </td>
+ <td>(</td>
+ <td class="paramtype">uint32_t </td>
+ <td class="paramname"><em>dataFmt</em></td><td>)</td>
+ <td></td>
+ </tr>
+ </table>
+ </td>
+ <td class="mlabels-right">
+<span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span> </td>
+ </tr>
+</table>
+</div><div class="memdoc">
+
+<p>Function to check whether a data format is YUV444 . </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">dataFmt</td><td>[IN] Data format to check. For valid values see <a class="el" href="csl__fvid2__data_types_8h.html#a9f5096b017d15ffecdcc0990fd1b031a" title="YUV 422 Interleaved format - UYVY. ">Fvid2_DataFormat</a>.</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>Returns TRUE if data format is YUV444 , FALSE otherwise. </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="a8996b9bd71f65f97abf2ee422611529b"></a>
+<div class="memitem">
+<div class="memproto">
+<table class="mlabels">
+ <tr>
+ <td class="mlabels-left">
+ <table class="memname">
+ <tr>
+ <td class="memname">static int32_t Fvid2_isStandardVesa </td>
+ <td>(</td>
+ <td class="paramtype">uint32_t </td>
+ <td class="paramname"><em>standard</em></td><td>)</td>
+ <td></td>
+ </tr>
+ </table>
+ </td>
+ <td class="mlabels-right">
+<span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span> </td>
+ </tr>
+</table>
+</div><div class="memdoc">
+
+<p>Function to check whether a standard is VESA mode or not. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">standard</td><td>[IN] Standard to check. For valid values see <a class="el" href="csl__fvid2__data_types_8h.html#aaa2667d105d557f254c20b87534ed4b6" title="720x480 30FPS interlaced NTSC standard. ">Fvid2_Standard</a>.</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>Returns TRUE if standard is VESA, FALSE otherwise. </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="a7f76750350b75947c9bfa26b76798c92"></a>
+<div class="memitem">
+<div class="memproto">
+<table class="mlabels">
+ <tr>
+ <td class="mlabels-left">
+ <table class="memname">
+ <tr>
+ <td class="memname">static void Fvid2CropConfig_init </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="struct_fvid2___crop_config.html">Fvid2_CropConfig</a> * </td>
+ <td class="paramname"><em>cropCfg</em></td><td>)</td>
+ <td></td>
+ </tr>
+ </table>
+ </td>
+ <td class="mlabels-right">
+<span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span> </td>
+ </tr>
+</table>
+</div><div class="memdoc">
+
+<p><a class="el" href="struct_fvid2___crop_config.html" title="Structure containing crop configuration - used in Scaler and VCOMP. ">Fvid2_CropConfig</a> structure init function. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">cropCfg</td><td>[IN] Pointer to <a class="el" href="struct_fvid2___crop_config.html" title="Structure containing crop configuration - used in Scaler and VCOMP. ">Fvid2_CropConfig</a> structure. </td></tr>
+ </table>
+ </dd>
+</dl>
+
+</div>
+</div>
+<a class="anchor" id="a3c57266e7a813692eee72e3624f22fdf"></a>
+<div class="memitem">
+<div class="memproto">
+<table class="mlabels">
+ <tr>
+ <td class="mlabels-left">
+ <table class="memname">
+ <tr>
+ <td class="memname">static void Fvid2Format_init </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="struct_fvid2___format.html">Fvid2_Format</a> * </td>
+ <td class="paramname"><em>fmt</em></td><td>)</td>
+ <td></td>
+ </tr>
+ </table>
+ </td>
+ <td class="mlabels-right">
+<span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span> </td>
+ </tr>
+</table>
+</div><div class="memdoc">
+
+<p><a class="el" href="struct_fvid2___format.html" title="FVID2 video buffer format specification. ">Fvid2_Format</a> structure init function. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">fmt</td><td>[IN] Pointer to <a class="el" href="struct_fvid2___format.html" title="FVID2 video buffer format specification. ">Fvid2_Format</a> structure. </td></tr>
+ </table>
+ </dd>
+</dl>
+
+</div>
+</div>
+<a class="anchor" id="a519f857d75a4b946c99e0a8cfa0da148"></a>
+<div class="memitem">
+<div class="memproto">
+<table class="mlabels">
+ <tr>
+ <td class="mlabels-left">
+ <table class="memname">
+ <tr>
+ <td class="memname">static void Fvid2Frame_init </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="struct_fvid2___frame.html">Fvid2_Frame</a> * </td>
+ <td class="paramname"><em>frm</em></td><td>)</td>
+ <td></td>
+ </tr>
+ </table>
+ </td>
+ <td class="mlabels-right">
+<span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span> </td>
+ </tr>
+</table>
+</div><div class="memdoc">
+
+<p><a class="el" href="struct_fvid2___frame.html" title="FVID2 frame buffer structure. ">Fvid2_Frame</a> structure init function. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">frm</td><td>[IN] Pointer to <a class="el" href="struct_fvid2___frame.html" title="FVID2 frame buffer structure. ">Fvid2_Frame</a> structure. </td></tr>
+ </table>
+ </dd>
+</dl>
+
+</div>
+</div>
+<a class="anchor" id="a835800489d2c42aed71f30941b9f2fd2"></a>
+<div class="memitem">
+<div class="memproto">
+<table class="mlabels">
+ <tr>
+ <td class="mlabels-left">
+ <table class="memname">
+ <tr>
+ <td class="memname">static void Fvid2FrameList_init </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="struct_fvid2___frame_list.html">Fvid2_FrameList</a> * </td>
+ <td class="paramname"><em>fList</em></td><td>)</td>
+ <td></td>
+ </tr>
+ </table>
+ </td>
+ <td class="mlabels-right">
+<span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span> </td>
+ </tr>
+</table>
+</div><div class="memdoc">
+
+<p><a class="el" href="struct_fvid2___frame_list.html" title="FVID2 frame buffer list used to exchange multiple FVID2 frames in a single driver call...">Fvid2_FrameList</a> structure init function. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">fList</td><td>[IN] Pointer to <a class="el" href="struct_fvid2___frame_list.html" title="FVID2 frame buffer list used to exchange multiple FVID2 frames in a single driver call...">Fvid2_FrameList</a> structure. </td></tr>
+ </table>
+ </dd>
+</dl>
+
+</div>
+</div>
+<a class="anchor" id="a7fd1ec90c192cdc87f2e51819ad6b6fa"></a>
+<div class="memitem">
+<div class="memproto">
+<table class="mlabels">
+ <tr>
+ <td class="mlabels-left">
+ <table class="memname">
+ <tr>
+ <td class="memname">static void Fvid2ModeInfo_init </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="struct_fvid2___mode_info.html">Fvid2_ModeInfo</a> * </td>
+ <td class="paramname"><em>modeInfo</em></td><td>)</td>
+ <td></td>
+ </tr>
+ </table>
+ </td>
+ <td class="mlabels-right">
+<span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span> </td>
+ </tr>
+</table>
+</div><div class="memdoc">
+
+<p><a class="el" href="struct_fvid2___mode_info.html" title="FVID2 Mode information structure. ">Fvid2_ModeInfo</a> structure init function. This defaults to 1080p60. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">modeInfo</td><td>[IN] Pointer to <a class="el" href="struct_fvid2___mode_info.html" title="FVID2 Mode information structure. ">Fvid2_ModeInfo</a> structure. </td></tr>
+ </table>
+ </dd>
+</dl>
+
+</div>
+</div>
+<a class="anchor" id="acde86e2766599bb25a7126f364e78c4e"></a>
+<div class="memitem">
+<div class="memproto">
+<table class="mlabels">
+ <tr>
+ <td class="mlabels-left">
+ <table class="memname">
+ <tr>
+ <td class="memname">static void Fvid2PosConfig_init </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="struct_fvid2___pos_config.html">Fvid2_PosConfig</a> * </td>
+ <td class="paramname"><em>posCfg</em></td><td>)</td>
+ <td></td>
+ </tr>
+ </table>
+ </td>
+ <td class="mlabels-right">
+<span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span> </td>
+ </tr>
+</table>
+</div><div class="memdoc">
+
+<p><a class="el" href="struct_fvid2___pos_config.html" title="Structure containing position configuration - used in VCOMP and CIG. ">Fvid2_PosConfig</a> structure init function. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">posCfg</td><td>[IN] Pointer to <a class="el" href="struct_fvid2___pos_config.html" title="Structure containing position configuration - used in VCOMP and CIG. ">Fvid2_PosConfig</a> structure. </td></tr>
+ </table>
+ </dd>
+</dl>
+
+</div>
+</div>
+<a class="anchor" id="a699a19f64a958b0e023264d2626df860"></a>
+<div class="memitem">
+<div class="memproto">
+<table class="mlabels">
+ <tr>
+ <td class="mlabels-left">
+ <table class="memname">
+ <tr>
+ <td class="memname">static void Fvid2SubFrameInfo_init </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="struct_fvid2___sub_frame_info.html">Fvid2_SubFrameInfo</a> * </td>
+ <td class="paramname"><em>sfInfo</em></td><td>)</td>
+ <td></td>
+ </tr>
+ </table>
+ </td>
+ <td class="mlabels-right">
+<span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span> </td>
+ </tr>
+</table>
+</div><div class="memdoc">
+
+<p><a class="el" href="struct_fvid2___sub_frame_info.html" title="Sub-Frame information. ">Fvid2_SubFrameInfo</a> structure init function. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">sfInfo</td><td>[IN] Pointer to <a class="el" href="struct_fvid2___sub_frame_info.html" title="Sub-Frame information. ">Fvid2_SubFrameInfo</a> structure. </td></tr>
+ </table>
+ </dd>
+</dl>
+
+</div>
+</div>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
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+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
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+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
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+<tr class="memitem:dir_2c013fc7e98dc8ade314eba46bcbb0d6"><td class="memItemLeft" align="right" valign="top">directory  </td><td class="memItemRight" valign="bottom"><a class="el" href="dir_2c013fc7e98dc8ade314eba46bcbb0d6.html">src</a></td></tr>
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+<tr class="memdesc:csl__dss_8h"><td class="mdescLeft"> </td><td class="mdescRight"><h1>This file contains the CSL-FL API's for DSS </h1>
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+<tr class="memitem:csl__fvid2__data_types_8h"><td class="memItemLeft" align="right" valign="top">file  </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__fvid2__data_types_8h.html">csl_fvid2_dataTypes.h</a></td></tr>
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+</table>
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+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
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diff --git a/packages/ti/drv/dss/docs/doxygen/html/doxygen.png b/packages/ti/drv/dss/docs/doxygen/html/doxygen.png
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diff --git a/packages/ti/drv/dss/docs/doxygen/html/dss_8h.html b/packages/ti/drv/dss/docs/doxygen/html/dss_8h.html
--- /dev/null
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+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>dss.h File Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
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+<!-- Generated by Doxygen 1.8.6 -->
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+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li class="current"><a href="files.html"><span>Files</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow2" class="tabs2">
+ <ul class="tablist">
+ <li><a href="files.html"><span>File List</span></a></li>
+ <li><a href="globals.html"><span>Globals</span></a></li>
+ </ul>
+ </div>
+</div><!-- top -->
+<div class="header">
+ <div class="summary">
+<a href="#nested-classes">Data Structures</a> |
+<a href="#define-members">Macros</a> |
+<a href="#func-members">Functions</a> </div>
+ <div class="headertitle">
+<div class="title">dss.h File Reference<div class="ingroups"><a class="el" href="group___d_s_s.html">DSS Driver</a></div></div> </div>
+</div><!--header-->
+<div class="contents">
+
+<p>DSS Driver API/interface file.
+<a href="#details">More...</a></p>
+<div class="textblock"><code>#include <stdint.h></code><br/>
+<code>#include <ti/csl/soc.h></code><br/>
+<code>#include <<a class="el" href="csl__dss_8h.html">ti/csl/csl_dss.h</a>></code><br/>
+<code>#include <ti/drv/fvid2/fvid2.h></code><br/>
+<code>#include <<a class="el" href="dss__cfg_8h.html">ti/drv/dss/include/dss_cfg.h</a>></code><br/>
+<code>#include <ti/drv/dss/soc/dss_soc.h></code><br/>
+<code>#include <<a class="el" href="dss__disp_8h.html">ti/drv/dss/include/dss_disp.h</a>></code><br/>
+<code>#include <<a class="el" href="dss__dctrl_8h.html">ti/drv/dss/include/dss_dctrl.h</a>></code><br/>
+</div><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="nested-classes"></a>
+Data Structures</h2></td></tr>
+<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___init_params.html">Dss_InitParams</a></td></tr>
+<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">DSS initialization parameters. <a href="struct_dss___init_params.html#details">More...</a><br/></td></tr>
+<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
+Macros</h2></td></tr>
+<tr class="memitem:ga87b702c7777640534d677104a7697d35"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga87b702c7777640534d677104a7697d35"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___d_s_s.html#ga87b702c7777640534d677104a7697d35">DSS_DISP_DRV_ID</a>   (FVID2_DSS_DRV_BASE + 0x00U)</td></tr>
+<tr class="memdesc:ga87b702c7777640534d677104a7697d35"><td class="mdescLeft"> </td><td class="mdescRight">Display driver ID used at the time of FVID2 create. <br/></td></tr>
+<tr class="separator:ga87b702c7777640534d677104a7697d35"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga0a02adbaa0f72fbfba37dbca39c7ab1d"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga0a02adbaa0f72fbfba37dbca39c7ab1d"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___d_s_s.html#ga0a02adbaa0f72fbfba37dbca39c7ab1d">DSS_DCTRL_DRV_ID</a>   (FVID2_DSS_DRV_BASE + 0x01U)</td></tr>
+<tr class="memdesc:ga0a02adbaa0f72fbfba37dbca39c7ab1d"><td class="mdescLeft"> </td><td class="mdescRight">Display controller driver ID used at the time of FVID2 create. <br/></td></tr>
+<tr class="separator:ga0a02adbaa0f72fbfba37dbca39c7ab1d"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gaf8566eb291e6ce8c67bf5158426d42b9"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaf8566eb291e6ce8c67bf5158426d42b9"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___d_s_s.html#gaf8566eb291e6ce8c67bf5158426d42b9">DSS_DISP_IOCTL_BASE</a>   (FVID2_DSS_DRV_IOCTL_BASE + 0x000U)</td></tr>
+<tr class="memdesc:gaf8566eb291e6ce8c67bf5158426d42b9"><td class="mdescLeft"> </td><td class="mdescRight">IOCTL base address for the display driver IOCTLs. <br/></td></tr>
+<tr class="separator:gaf8566eb291e6ce8c67bf5158426d42b9"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga9f2d978d01f7c34d373f956e5e5862d1"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga9f2d978d01f7c34d373f956e5e5862d1"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___d_s_s.html#ga9f2d978d01f7c34d373f956e5e5862d1">DSS_DCTRL_IOCTL_BASE</a>   (FVID2_DSS_DRV_IOCTL_BASE + 0x100U)</td></tr>
+<tr class="memdesc:ga9f2d978d01f7c34d373f956e5e5862d1"><td class="mdescLeft"> </td><td class="mdescRight">IOCTL base address for the display controller driver IOCTLs. <br/></td></tr>
+<tr class="separator:ga9f2d978d01f7c34d373f956e5e5862d1"><td class="memSeparator" colspan="2"> </td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a>
+Functions</h2></td></tr>
+<tr class="memitem:ga148ec5eeed6ef017fddce29adee32e90"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___d_s_s.html#ga148ec5eeed6ef017fddce29adee32e90">Dss_initParamsInit</a> (<a class="el" href="struct_dss___init_params.html">Dss_InitParams</a> *dssParams)</td></tr>
+<tr class="memdesc:ga148ec5eeed6ef017fddce29adee32e90"><td class="mdescLeft"> </td><td class="mdescRight"><a class="el" href="struct_dss___init_params.html" title="DSS initialization parameters. ">Dss_InitParams</a> structure init function. <a href="group___d_s_s.html#ga148ec5eeed6ef017fddce29adee32e90">More...</a><br/></td></tr>
+<tr class="separator:ga148ec5eeed6ef017fddce29adee32e90"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga9a7600eb912fe78c81a4e5fd88b495f6"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group___d_s_s.html#ga9a7600eb912fe78c81a4e5fd88b495f6">Dss_init</a> (const <a class="el" href="struct_dss___init_params.html">Dss_InitParams</a> *initParams)</td></tr>
+<tr class="memdesc:ga9a7600eb912fe78c81a4e5fd88b495f6"><td class="mdescLeft"> </td><td class="mdescRight">DSS initialization function. This function initializes the DSS hardware and drivers. This function should be called before calling any driver APIs and only once. <a href="group___d_s_s.html#ga9a7600eb912fe78c81a4e5fd88b495f6">More...</a><br/></td></tr>
+<tr class="separator:ga9a7600eb912fe78c81a4e5fd88b495f6"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga8da153ec94fd77b1238623030aedd76e"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group___d_s_s.html#ga8da153ec94fd77b1238623030aedd76e">Dss_deInit</a> (void)</td></tr>
+<tr class="memdesc:ga8da153ec94fd77b1238623030aedd76e"><td class="mdescLeft"> </td><td class="mdescRight">DSS de-initialization function. This function un-initializes the DSS hardware and drivers. This function should be called during system shutdown if <a class="el" href="group___d_s_s.html#ga9a7600eb912fe78c81a4e5fd88b495f6" title="DSS initialization function. This function initializes the DSS hardware and drivers. This function should be called before calling any driver APIs and only once. ">Dss_init()</a> was called by the application. <a href="group___d_s_s.html#ga8da153ec94fd77b1238623030aedd76e">More...</a><br/></td></tr>
+<tr class="separator:ga8da153ec94fd77b1238623030aedd76e"><td class="memSeparator" colspan="2"> </td></tr>
+</table>
+<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
+<div class="textblock"><p>DSS Driver API/interface file. </p>
+</div></div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/dss__cfg_8h.html b/packages/ti/drv/dss/docs/doxygen/html/dss__cfg_8h.html
--- /dev/null
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+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
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+<title>dss_cfg.h File Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
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+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
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+ <li><a href="index.html"><span>Main Page</span></a></li>
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+ </div>
+<div id="nav-path" class="navpath">
+ <ul>
+<li class="navelem"><a class="el" href="dir_0fa78962abed40d3d8df26bacdfc9ada.html">include</a></li> </ul>
+</div>
+</div><!-- top -->
+<div class="header">
+ <div class="summary">
+<a href="#define-members">Macros</a> </div>
+ <div class="headertitle">
+<div class="title">dss_cfg.h File Reference</div> </div>
+</div><!--header-->
+<div class="contents">
+
+<p>DSS Driver configuration file.
+<a href="#details">More...</a></p>
+<table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
+Macros</h2></td></tr>
+<tr class="memitem:aba4c70e5063467ebeb1cd820b1e4f808"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aba4c70e5063467ebeb1cd820b1e4f808"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="dss__cfg_8h.html#aba4c70e5063467ebeb1cd820b1e4f808">DSS_DEF_QUEUE_LEN_PER_INST</a>   (16U)</td></tr>
+<tr class="memdesc:aba4c70e5063467ebeb1cd820b1e4f808"><td class="mdescLeft"> </td><td class="mdescRight">Default max number of frames that can be queued per display driver instance. <br/></td></tr>
+<tr class="separator:aba4c70e5063467ebeb1cd820b1e4f808"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a76ace3e354893fc499603be1fbe3d1b2"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="dss__cfg_8h.html#a76ace3e354893fc499603be1fbe3d1b2">DssTrace</a></td></tr>
+<tr class="memdesc:a76ace3e354893fc499603be1fbe3d1b2"><td class="mdescLeft"> </td><td class="mdescRight">Log enable for DSS module. <a href="#a76ace3e354893fc499603be1fbe3d1b2">More...</a><br/></td></tr>
+<tr class="separator:a76ace3e354893fc499603be1fbe3d1b2"><td class="memSeparator" colspan="2"> </td></tr>
+</table>
+<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
+<div class="textblock"><p>DSS Driver configuration file. </p>
+</div><h2 class="groupheader">Macro Definition Documentation</h2>
+<a class="anchor" id="a76ace3e354893fc499603be1fbe3d1b2"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">#define DssTrace</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<b>Value:</b><div class="fragment"><div class="line">((uint32_t) GT_ERR | \</div>
+<div class="line"> (uint32_t) GT_TraceState_Enable)</div>
+</div><!-- fragment -->
+<p>Log enable for DSS module. </p>
+
+</div>
+</div>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/dss__dctrl_8h.html b/packages/ti/drv/dss/docs/doxygen/html/dss__dctrl_8h.html
--- /dev/null
@@ -0,0 +1,565 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>dss_dctrl.h File Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li class="current"><a href="files.html"><span>Files</span></a></li>
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+ </div>
+<div id="nav-path" class="navpath">
+ <ul>
+<li class="navelem"><a class="el" href="dir_0fa78962abed40d3d8df26bacdfc9ada.html">include</a></li> </ul>
+</div>
+</div><!-- top -->
+<div class="header">
+ <div class="summary">
+<a href="#nested-classes">Data Structures</a> |
+<a href="#define-members">Macros</a> |
+<a href="#typedef-members">Typedefs</a> |
+<a href="#func-members">Functions</a> </div>
+ <div class="headertitle">
+<div class="title">dss_dctrl.h File Reference</div> </div>
+</div><!--header-->
+<div class="contents">
+
+<p>DSS Controller Driver API/interface file.
+<a href="#details">More...</a></p>
+<table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="nested-classes"></a>
+Data Structures</h2></td></tr>
+<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___dctrl_path_info.html">Dss_DctrlPathInfo</a></td></tr>
+<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">Structure containing DSS path information. This structure is used as an argument to IOCTL_DSS_DCTRL_SET_PATH. This IOCTL takes the array of edges connected between nodes. <a href="struct_dss___dctrl_path_info.html#details">More...</a><br/></td></tr>
+<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___dctrl_vp_params.html">Dss_DctrlVpParams</a></td></tr>
+<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">Structure containing Video Port information. This structure is used as an argument to IOCTL_DSS_DCTRL_SET_VP_PARAMS. <a href="struct_dss___dctrl_vp_params.html#details">More...</a><br/></td></tr>
+<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___dctrl_overlay_params.html">Dss_DctrlOverlayParams</a></td></tr>
+<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">Structure containing Overlay information. This structure is used as an argument to IOCTL_DSS_DCTRL_SET_OVERLAY_PARAMS. <a href="struct_dss___dctrl_overlay_params.html#details">More...</a><br/></td></tr>
+<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___dctrl_overlay_layer_params.html">Dss_DctrlOverlayLayerParams</a></td></tr>
+<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">Structure containing Overlay layer information. This structure is used as an argument to IOCTL_DSS_DCTRL_SET_LAYER_PARAMS. <a href="struct_dss___dctrl_overlay_layer_params.html#details">More...</a><br/></td></tr>
+<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___dctrl_vp_csc_coeff.html">Dss_DctrlVpCscCoeff</a></td></tr>
+<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">Structure containing Video Port CSC information. This structure is used as an argument to IOCTL_DSS_DCTRL_SET_VP_CSC_COEFF. <a href="struct_dss___dctrl_vp_csc_coeff.html#details">More...</a><br/></td></tr>
+<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___dctrl_adv_vp_params.html">Dss_DctrlAdvVpParams</a></td></tr>
+<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">Structure containing advance Video Port information. This structure is used as an argument to IOCTL_DSS_DCTRL_SET_ADV_VP_PARAMS. <a href="struct_dss___dctrl_adv_vp_params.html#details">More...</a><br/></td></tr>
+<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___dctrl_lcd_blank_timing_params.html">Dss_DctrlLcdBlankTimingParams</a></td></tr>
+<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">Structure containing LCD Blank Timing Configuration. This structure is used as an argument to IOCTL_DSS_DCTRL_SET_LCD_BLANK_TIMING_PARAMS. <a href="struct_dss___dctrl_lcd_blank_timing_params.html#details">More...</a><br/></td></tr>
+<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___dctrl_region_safety_chk_cfg.html">Dss_DctrlRegionSafetyChkCfg</a></td></tr>
+<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">Structure containing Safety Check configuration for a particular region. <a href="struct_dss___dctrl_region_safety_chk_cfg.html#details">More...</a><br/></td></tr>
+<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___dctrl_vp_safety_chk_params.html">Dss_DctrlVpSafetyChkParams</a></td></tr>
+<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">Structure containing Safety Check configuration of Video Port. This structure is used as an argument to IOCTL_DSS_DCTRL_SET_VP_SAFETY_CHK_PARAMS. <a href="struct_dss___dctrl_vp_safety_chk_params.html#details">More...</a><br/></td></tr>
+<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___dctrl_vp_error_stats.html">Dss_DctrlVpErrorStats</a></td></tr>
+<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">Structure containing Error Stats of Video Port. This structure is used as an argument to IOCTL_DSS_DCTRL_GET_VP_ERROR_STATS. <a href="struct_dss___dctrl_vp_error_stats.html#details">More...</a><br/></td></tr>
+<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___dctrl_global_dss_params.html">Dss_DctrlGlobalDssParams</a></td></tr>
+<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">Structure containing global DSS Configuration. This structure is used as an argument to IOCTL_DSS_DCTRL_SET_GLOBAL_DSS_PARAMS. <a href="struct_dss___dctrl_global_dss_params.html#details">More...</a><br/></td></tr>
+<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___dctrl_sync_lost_cb_params.html">Dss_DctrlSyncLostCbParams</a></td></tr>
+<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">Structure containing Sync Lost callback parameters. This structure is used as an argument to IOCTL_DSS_DCTRL_REGISTER_SYNCLOST_CB. <a href="struct_dss___dctrl_sync_lost_cb_params.html#details">More...</a><br/></td></tr>
+<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
+Macros</h2></td></tr>
+<tr class="memitem:gae55f1184bc13a50a4e113e95835a5d0c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___d_s_s___d_c_t_r_l___i_o_c_t_l.html#gae55f1184bc13a50a4e113e95835a5d0c">IOCTL_DSS_DCTRL_SET_PATH</a>   (<a class="el" href="group___d_s_s.html#ga9f2d978d01f7c34d373f956e5e5862d1">DSS_DCTRL_IOCTL_BASE</a> + 0x01U)</td></tr>
+<tr class="memdesc:gae55f1184bc13a50a4e113e95835a5d0c"><td class="mdescLeft"> </td><td class="mdescRight">Command to set the DSS display path configuration. <a href="group___d_s_s___d_c_t_r_l___i_o_c_t_l.html#gae55f1184bc13a50a4e113e95835a5d0c">More...</a><br/></td></tr>
+<tr class="separator:gae55f1184bc13a50a4e113e95835a5d0c"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga4b16831ed360d38789d105376246c41a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___d_s_s___d_c_t_r_l___i_o_c_t_l.html#ga4b16831ed360d38789d105376246c41a">IOCTL_DSS_DCTRL_CLEAR_PATH</a>   (<a class="el" href="group___d_s_s.html#ga9f2d978d01f7c34d373f956e5e5862d1">DSS_DCTRL_IOCTL_BASE</a> + 0x02U)</td></tr>
+<tr class="memdesc:ga4b16831ed360d38789d105376246c41a"><td class="mdescLeft"> </td><td class="mdescRight">Command to clear the DSS display path configuration. <a href="group___d_s_s___d_c_t_r_l___i_o_c_t_l.html#ga4b16831ed360d38789d105376246c41a">More...</a><br/></td></tr>
+<tr class="separator:ga4b16831ed360d38789d105376246c41a"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gad9d06c559d83e6b0cd1fb72dfeca55c0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___d_s_s___d_c_t_r_l___i_o_c_t_l.html#gad9d06c559d83e6b0cd1fb72dfeca55c0">IOCTL_DSS_DCTRL_SET_VP_PARAMS</a>   (<a class="el" href="group___d_s_s.html#ga9f2d978d01f7c34d373f956e5e5862d1">DSS_DCTRL_IOCTL_BASE</a> + 0x03U)</td></tr>
+<tr class="memdesc:gad9d06c559d83e6b0cd1fb72dfeca55c0"><td class="mdescLeft"> </td><td class="mdescRight">Command to set Video Port configuration. <a href="group___d_s_s___d_c_t_r_l___i_o_c_t_l.html#gad9d06c559d83e6b0cd1fb72dfeca55c0">More...</a><br/></td></tr>
+<tr class="separator:gad9d06c559d83e6b0cd1fb72dfeca55c0"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga076d70564e492c0780bc4c747ca7ee82"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___d_s_s___d_c_t_r_l___i_o_c_t_l.html#ga076d70564e492c0780bc4c747ca7ee82">IOCTL_DSS_DCTRL_SET_OVERLAY_PARAMS</a>   (<a class="el" href="group___d_s_s.html#ga9f2d978d01f7c34d373f956e5e5862d1">DSS_DCTRL_IOCTL_BASE</a> + 0x04U)</td></tr>
+<tr class="memdesc:ga076d70564e492c0780bc4c747ca7ee82"><td class="mdescLeft"> </td><td class="mdescRight">Command to set configuration of the given overlay. <a href="group___d_s_s___d_c_t_r_l___i_o_c_t_l.html#ga076d70564e492c0780bc4c747ca7ee82">More...</a><br/></td></tr>
+<tr class="separator:ga076d70564e492c0780bc4c747ca7ee82"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga824609e625e41769f9042b8879a73861"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___d_s_s___d_c_t_r_l___i_o_c_t_l.html#ga824609e625e41769f9042b8879a73861">IOCTL_DSS_DCTRL_SET_LAYER_PARAMS</a>   (<a class="el" href="group___d_s_s.html#ga9f2d978d01f7c34d373f956e5e5862d1">DSS_DCTRL_IOCTL_BASE</a> + 0x05U)</td></tr>
+<tr class="memdesc:ga824609e625e41769f9042b8879a73861"><td class="mdescLeft"> </td><td class="mdescRight">Command to set layer/Z-order configuration of the given overlay. <a href="group___d_s_s___d_c_t_r_l___i_o_c_t_l.html#ga824609e625e41769f9042b8879a73861">More...</a><br/></td></tr>
+<tr class="separator:ga824609e625e41769f9042b8879a73861"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gad01ce1c58a3a6966395f29a6d61d7684"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___d_s_s___d_c_t_r_l___i_o_c_t_l.html#gad01ce1c58a3a6966395f29a6d61d7684">IOCTL_DSS_DCTRL_SET_VP_CSC_COEFF</a>   (<a class="el" href="group___d_s_s.html#ga9f2d978d01f7c34d373f956e5e5862d1">DSS_DCTRL_IOCTL_BASE</a> + 0x06U)</td></tr>
+<tr class="memdesc:gad01ce1c58a3a6966395f29a6d61d7684"><td class="mdescLeft"> </td><td class="mdescRight">Command to program the CSC coefficients for Video Port. By default BT 601 coefficients are set. <a href="group___d_s_s___d_c_t_r_l___i_o_c_t_l.html#gad01ce1c58a3a6966395f29a6d61d7684">More...</a><br/></td></tr>
+<tr class="separator:gad01ce1c58a3a6966395f29a6d61d7684"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga41ce0b6adeb9b7e098ce3b84113bf48f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___d_s_s___d_c_t_r_l___i_o_c_t_l.html#ga41ce0b6adeb9b7e098ce3b84113bf48f">IOCTL_DSS_DCTRL_SET_ADV_VP_PARAMS</a>   (<a class="el" href="group___d_s_s.html#ga9f2d978d01f7c34d373f956e5e5862d1">DSS_DCTRL_IOCTL_BASE</a> + 0x07U)</td></tr>
+<tr class="memdesc:ga41ce0b6adeb9b7e098ce3b84113bf48f"><td class="mdescLeft"> </td><td class="mdescRight">Command to set advance Video Port configuration. <a href="group___d_s_s___d_c_t_r_l___i_o_c_t_l.html#ga41ce0b6adeb9b7e098ce3b84113bf48f">More...</a><br/></td></tr>
+<tr class="separator:ga41ce0b6adeb9b7e098ce3b84113bf48f"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga381f6aa554cc69e7fdb6dc6022086cee"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___d_s_s___d_c_t_r_l___i_o_c_t_l.html#ga381f6aa554cc69e7fdb6dc6022086cee">IOCTL_DSS_DCTRL_SET_LCD_BLANK_TIMING_PARAMS</a>   (<a class="el" href="group___d_s_s.html#ga9f2d978d01f7c34d373f956e5e5862d1">DSS_DCTRL_IOCTL_BASE</a> + 0x08U)</td></tr>
+<tr class="memdesc:ga381f6aa554cc69e7fdb6dc6022086cee"><td class="mdescLeft"> </td><td class="mdescRight">Command to program blank timing parameters of given LCD. <a href="group___d_s_s___d_c_t_r_l___i_o_c_t_l.html#ga381f6aa554cc69e7fdb6dc6022086cee">More...</a><br/></td></tr>
+<tr class="separator:ga381f6aa554cc69e7fdb6dc6022086cee"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gabcaa1961abdf4145c9db4cedffe58259"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___d_s_s___d_c_t_r_l___i_o_c_t_l.html#gabcaa1961abdf4145c9db4cedffe58259">IOCTL_DSS_DCTRL_SET_VP_SAFETY_CHK_PARAMS</a>   (<a class="el" href="group___d_s_s.html#ga9f2d978d01f7c34d373f956e5e5862d1">DSS_DCTRL_IOCTL_BASE</a> + 0x09U)</td></tr>
+<tr class="memdesc:gabcaa1961abdf4145c9db4cedffe58259"><td class="mdescLeft"> </td><td class="mdescRight">Command to program Safety Check configuration at Video Port Output. <a href="group___d_s_s___d_c_t_r_l___i_o_c_t_l.html#gabcaa1961abdf4145c9db4cedffe58259">More...</a><br/></td></tr>
+<tr class="separator:gabcaa1961abdf4145c9db4cedffe58259"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga3d29253c153bdec7275527bd0b8fe4dc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___d_s_s___d_c_t_r_l___i_o_c_t_l.html#ga3d29253c153bdec7275527bd0b8fe4dc">IOCTL_DSS_DCTRL_GET_VP_ERROR_STATS</a>   (<a class="el" href="group___d_s_s.html#ga9f2d978d01f7c34d373f956e5e5862d1">DSS_DCTRL_IOCTL_BASE</a> + 0x0AU)</td></tr>
+<tr class="memdesc:ga3d29253c153bdec7275527bd0b8fe4dc"><td class="mdescLeft"> </td><td class="mdescRight">IOCTL to get the number of errors for a given Video Port. <a href="group___d_s_s___d_c_t_r_l___i_o_c_t_l.html#ga3d29253c153bdec7275527bd0b8fe4dc">More...</a><br/></td></tr>
+<tr class="separator:ga3d29253c153bdec7275527bd0b8fe4dc"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga48fd0f5f1e1476ef03b203ae9b1ccfaa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___d_s_s___d_c_t_r_l___i_o_c_t_l.html#ga48fd0f5f1e1476ef03b203ae9b1ccfaa">IOCTL_DSS_DCTRL_SET_GLOBAL_DSS_PARAMS</a>   (<a class="el" href="group___d_s_s.html#ga9f2d978d01f7c34d373f956e5e5862d1">DSS_DCTRL_IOCTL_BASE</a> + 0x0BU)</td></tr>
+<tr class="memdesc:ga48fd0f5f1e1476ef03b203ae9b1ccfaa"><td class="mdescLeft"> </td><td class="mdescRight">IOCTL to set the global DSS parameters. <a href="group___d_s_s___d_c_t_r_l___i_o_c_t_l.html#ga48fd0f5f1e1476ef03b203ae9b1ccfaa">More...</a><br/></td></tr>
+<tr class="separator:ga48fd0f5f1e1476ef03b203ae9b1ccfaa"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga626c83cf4afb58295e807b710e10c5b0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___d_s_s___d_c_t_r_l___i_o_c_t_l.html#ga626c83cf4afb58295e807b710e10c5b0">IOCTL_DSS_DCTRL_STOP_VP</a>   (<a class="el" href="group___d_s_s.html#ga9f2d978d01f7c34d373f956e5e5862d1">DSS_DCTRL_IOCTL_BASE</a> + 0x0CU)</td></tr>
+<tr class="memdesc:ga626c83cf4afb58295e807b710e10c5b0"><td class="mdescLeft"> </td><td class="mdescRight">Command to disable Video Port. <a href="group___d_s_s___d_c_t_r_l___i_o_c_t_l.html#ga626c83cf4afb58295e807b710e10c5b0">More...</a><br/></td></tr>
+<tr class="separator:ga626c83cf4afb58295e807b710e10c5b0"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga0605d3de6b43d543ab11a8ba54a5fdbc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___d_s_s___d_c_t_r_l___i_o_c_t_l.html#ga0605d3de6b43d543ab11a8ba54a5fdbc">IOCTL_DSS_DCTRL_SET_OLDI_PARAMS</a>   (<a class="el" href="group___d_s_s.html#ga9f2d978d01f7c34d373f956e5e5862d1">DSS_DCTRL_IOCTL_BASE</a> + 0x0DU)</td></tr>
+<tr class="memdesc:ga0605d3de6b43d543ab11a8ba54a5fdbc"><td class="mdescLeft"> </td><td class="mdescRight">IOCTL to set the OLDI configuration of given video port. <a href="group___d_s_s___d_c_t_r_l___i_o_c_t_l.html#ga0605d3de6b43d543ab11a8ba54a5fdbc">More...</a><br/></td></tr>
+<tr class="separator:ga0605d3de6b43d543ab11a8ba54a5fdbc"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gae4ab29ac71849b0ad7810e5fecaf2b00"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___d_s_s___d_c_t_r_l___i_o_c_t_l.html#gae4ab29ac71849b0ad7810e5fecaf2b00">IOCTL_DSS_DCTRL_REGISTER_SYNCLOST_CB</a>   (<a class="el" href="group___d_s_s.html#ga9f2d978d01f7c34d373f956e5e5862d1">DSS_DCTRL_IOCTL_BASE</a> + 0x0EU)</td></tr>
+<tr class="memdesc:gae4ab29ac71849b0ad7810e5fecaf2b00"><td class="mdescLeft"> </td><td class="mdescRight">Command to register Video Port sync lost callback function. <a href="group___d_s_s___d_c_t_r_l___i_o_c_t_l.html#gae4ab29ac71849b0ad7810e5fecaf2b00">More...</a><br/></td></tr>
+<tr class="separator:gae4ab29ac71849b0ad7810e5fecaf2b00"><td class="memSeparator" colspan="2"> </td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="typedef-members"></a>
+Typedefs</h2></td></tr>
+<tr class="memitem:adc02df6de7a3d5940da55838ee464701"><td class="memItemLeft" align="right" valign="top">typedef void(* </td><td class="memItemRight" valign="bottom"><a class="el" href="dss__dctrl_8h.html#adc02df6de7a3d5940da55838ee464701">Dss_DctrlSyncLostCbFxn</a> )(uint32_t vpId, void *appData)</td></tr>
+<tr class="memdesc:adc02df6de7a3d5940da55838ee464701"><td class="mdescLeft"> </td><td class="mdescRight">Video Port sync loss callback function prototype. <a href="#adc02df6de7a3d5940da55838ee464701">More...</a><br/></td></tr>
+<tr class="separator:adc02df6de7a3d5940da55838ee464701"><td class="memSeparator" colspan="2"> </td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a>
+Functions</h2></td></tr>
+<tr class="memitem:a123a4e064a3dd6ae0de052f3668bcc82"><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="dss__dctrl_8h.html#a123a4e064a3dd6ae0de052f3668bcc82">Dss_dctrlPathInfoInit</a> (<a class="el" href="struct_dss___dctrl_path_info.html">Dss_DctrlPathInfo</a> *pathInfo)</td></tr>
+<tr class="memdesc:a123a4e064a3dd6ae0de052f3668bcc82"><td class="mdescLeft"> </td><td class="mdescRight"><a class="el" href="struct_dss___dctrl_path_info.html" title="Structure containing DSS path information. This structure is used as an argument to IOCTL_DSS_DCTRL_S...">Dss_DctrlPathInfo</a> structure init function. <a href="#a123a4e064a3dd6ae0de052f3668bcc82">More...</a><br/></td></tr>
+<tr class="separator:a123a4e064a3dd6ae0de052f3668bcc82"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:aff73397092899b064dc00d8a813286a4"><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="dss__dctrl_8h.html#aff73397092899b064dc00d8a813286a4">Dss_dctrlVpParamsInit</a> (<a class="el" href="struct_dss___dctrl_vp_params.html">Dss_DctrlVpParams</a> *vpParams)</td></tr>
+<tr class="memdesc:aff73397092899b064dc00d8a813286a4"><td class="mdescLeft"> </td><td class="mdescRight"><a class="el" href="struct_dss___dctrl_vp_params.html" title="Structure containing Video Port information. This structure is used as an argument to IOCTL_DSS_DCTRL...">Dss_DctrlVpParams</a> structure init function. <a href="#aff73397092899b064dc00d8a813286a4">More...</a><br/></td></tr>
+<tr class="separator:aff73397092899b064dc00d8a813286a4"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:aeb3a05c6b9e915a29bfa94784b427f75"><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="dss__dctrl_8h.html#aeb3a05c6b9e915a29bfa94784b427f75">Dss_dctrlOverlayParamsInit</a> (<a class="el" href="struct_dss___dctrl_overlay_params.html">Dss_DctrlOverlayParams</a> *overlayParams)</td></tr>
+<tr class="memdesc:aeb3a05c6b9e915a29bfa94784b427f75"><td class="mdescLeft"> </td><td class="mdescRight"><a class="el" href="struct_dss___dctrl_overlay_params.html" title="Structure containing Overlay information. This structure is used as an argument to IOCTL_DSS_DCTRL_SE...">Dss_DctrlOverlayParams</a> structure init function. <a href="#aeb3a05c6b9e915a29bfa94784b427f75">More...</a><br/></td></tr>
+<tr class="separator:aeb3a05c6b9e915a29bfa94784b427f75"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a5a26a0b5b1059cb2dc79b0f7ec932cb6"><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="dss__dctrl_8h.html#a5a26a0b5b1059cb2dc79b0f7ec932cb6">Dss_dctrlOverlayLayerParamsInit</a> (<a class="el" href="struct_dss___dctrl_overlay_layer_params.html">Dss_DctrlOverlayLayerParams</a> *layerParams)</td></tr>
+<tr class="memdesc:a5a26a0b5b1059cb2dc79b0f7ec932cb6"><td class="mdescLeft"> </td><td class="mdescRight"><a class="el" href="struct_dss___dctrl_overlay_layer_params.html" title="Structure containing Overlay layer information. This structure is used as an argument to IOCTL_DSS_DC...">Dss_DctrlOverlayLayerParams</a> structure init function. <a href="#a5a26a0b5b1059cb2dc79b0f7ec932cb6">More...</a><br/></td></tr>
+<tr class="separator:a5a26a0b5b1059cb2dc79b0f7ec932cb6"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a8ef2fd5c8a1f3760dc6bd0d3f41cf782"><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="dss__dctrl_8h.html#a8ef2fd5c8a1f3760dc6bd0d3f41cf782">Dss_dctrlAdvVpParamsInit</a> (<a class="el" href="struct_dss___dctrl_adv_vp_params.html">Dss_DctrlAdvVpParams</a> *advVpParams)</td></tr>
+<tr class="memdesc:a8ef2fd5c8a1f3760dc6bd0d3f41cf782"><td class="mdescLeft"> </td><td class="mdescRight"><a class="el" href="struct_dss___dctrl_adv_vp_params.html" title="Structure containing advance Video Port information. This structure is used as an argument to IOCTL_D...">Dss_DctrlAdvVpParams</a> structure init function. <a href="#a8ef2fd5c8a1f3760dc6bd0d3f41cf782">More...</a><br/></td></tr>
+<tr class="separator:a8ef2fd5c8a1f3760dc6bd0d3f41cf782"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a1bee4f99058e9860ea9e0d8c46713d17"><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="dss__dctrl_8h.html#a1bee4f99058e9860ea9e0d8c46713d17">Dss_dctrlLcdBlankTimingParamsInit</a> (<a class="el" href="struct_dss___dctrl_lcd_blank_timing_params.html">Dss_DctrlLcdBlankTimingParams</a> *lcdBlankTimingParams)</td></tr>
+<tr class="memdesc:a1bee4f99058e9860ea9e0d8c46713d17"><td class="mdescLeft"> </td><td class="mdescRight"><a class="el" href="struct_dss___dctrl_lcd_blank_timing_params.html" title="Structure containing LCD Blank Timing Configuration. This structure is used as an argument to IOCTL_D...">Dss_DctrlLcdBlankTimingParams</a> structure init function. <a href="#a1bee4f99058e9860ea9e0d8c46713d17">More...</a><br/></td></tr>
+<tr class="separator:a1bee4f99058e9860ea9e0d8c46713d17"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a128f0b2a1da8e24d1e87993efc59a049"><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="dss__dctrl_8h.html#a128f0b2a1da8e24d1e87993efc59a049">Dss_dctrlRegionSafetyChkCfgInit</a> (<a class="el" href="struct_dss___dctrl_region_safety_chk_cfg.html">Dss_DctrlRegionSafetyChkCfg</a> *regionSafetyChkCfg)</td></tr>
+<tr class="memdesc:a128f0b2a1da8e24d1e87993efc59a049"><td class="mdescLeft"> </td><td class="mdescRight"><a class="el" href="struct_dss___dctrl_region_safety_chk_cfg.html" title="Structure containing Safety Check configuration for a particular region. ">Dss_DctrlRegionSafetyChkCfg</a> structure init function. <a href="#a128f0b2a1da8e24d1e87993efc59a049">More...</a><br/></td></tr>
+<tr class="separator:a128f0b2a1da8e24d1e87993efc59a049"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a3434c36ddde97b9077bb2b055cf0a4b0"><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="dss__dctrl_8h.html#a3434c36ddde97b9077bb2b055cf0a4b0">Dss_dctrlVpSafetyChkParamsInit</a> (<a class="el" href="struct_dss___dctrl_vp_safety_chk_params.html">Dss_DctrlVpSafetyChkParams</a> *vpSafetyChkParams)</td></tr>
+<tr class="memdesc:a3434c36ddde97b9077bb2b055cf0a4b0"><td class="mdescLeft"> </td><td class="mdescRight"><a class="el" href="struct_dss___dctrl_vp_safety_chk_params.html" title="Structure containing Safety Check configuration of Video Port. This structure is used as an argument ...">Dss_DctrlVpSafetyChkParams</a> structure init function. <a href="#a3434c36ddde97b9077bb2b055cf0a4b0">More...</a><br/></td></tr>
+<tr class="separator:a3434c36ddde97b9077bb2b055cf0a4b0"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ab7d6c323f77101a8d6f6ec0b36fcd092"><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="dss__dctrl_8h.html#ab7d6c323f77101a8d6f6ec0b36fcd092">Dss_dctrlVpErrorStatsInit</a> (<a class="el" href="struct_dss___dctrl_vp_error_stats.html">Dss_DctrlVpErrorStats</a> *vpErrorStats)</td></tr>
+<tr class="memdesc:ab7d6c323f77101a8d6f6ec0b36fcd092"><td class="mdescLeft"> </td><td class="mdescRight"><a class="el" href="struct_dss___dctrl_vp_error_stats.html" title="Structure containing Error Stats of Video Port. This structure is used as an argument to IOCTL_DSS_DC...">Dss_DctrlVpErrorStats</a> structure init function. <a href="#ab7d6c323f77101a8d6f6ec0b36fcd092">More...</a><br/></td></tr>
+<tr class="separator:ab7d6c323f77101a8d6f6ec0b36fcd092"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a9245be86f5b0aa58fd825ddac59b15de"><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="dss__dctrl_8h.html#a9245be86f5b0aa58fd825ddac59b15de">Dss_dctrlGlobalDssParamsInit</a> (<a class="el" href="struct_dss___dctrl_global_dss_params.html">Dss_DctrlGlobalDssParams</a> *globalDssParams)</td></tr>
+<tr class="memdesc:a9245be86f5b0aa58fd825ddac59b15de"><td class="mdescLeft"> </td><td class="mdescRight"><a class="el" href="struct_dss___dctrl_global_dss_params.html" title="Structure containing global DSS Configuration. This structure is used as an argument to IOCTL_DSS_DCT...">Dss_DctrlGlobalDssParams</a> structure init function. <a href="#a9245be86f5b0aa58fd825ddac59b15de">More...</a><br/></td></tr>
+<tr class="separator:a9245be86f5b0aa58fd825ddac59b15de"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:aa6b7e9e12da3c697e83d78d8909bfdb9"><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="dss__dctrl_8h.html#aa6b7e9e12da3c697e83d78d8909bfdb9">Dss_dctrlSyncLostCbParamsInit</a> (<a class="el" href="struct_dss___dctrl_sync_lost_cb_params.html">Dss_DctrlSyncLostCbParams</a> *syncLostCbParams)</td></tr>
+<tr class="memdesc:aa6b7e9e12da3c697e83d78d8909bfdb9"><td class="mdescLeft"> </td><td class="mdescRight"><a class="el" href="struct_dss___dctrl_sync_lost_cb_params.html" title="Structure containing Sync Lost callback parameters. This structure is used as an argument to IOCTL_DS...">Dss_DctrlSyncLostCbParams</a> structure init function. <a href="#aa6b7e9e12da3c697e83d78d8909bfdb9">More...</a><br/></td></tr>
+<tr class="separator:aa6b7e9e12da3c697e83d78d8909bfdb9"><td class="memSeparator" colspan="2"> </td></tr>
+</table>
+<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
+<div class="textblock"><p>DSS Controller Driver API/interface file. </p>
+</div><h2 class="groupheader">Typedef Documentation</h2>
+<a class="anchor" id="adc02df6de7a3d5940da55838ee464701"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">typedef void(* Dss_DctrlSyncLostCbFxn)(uint32_t vpId, void *appData)</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+
+<p>Video Port sync loss callback function prototype. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">appData</td><td>[OUT] Application's private data.</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None. </dd></dl>
+
+</div>
+</div>
+<h2 class="groupheader">Function Documentation</h2>
+<a class="anchor" id="a8ef2fd5c8a1f3760dc6bd0d3f41cf782"></a>
+<div class="memitem">
+<div class="memproto">
+<table class="mlabels">
+ <tr>
+ <td class="mlabels-left">
+ <table class="memname">
+ <tr>
+ <td class="memname">static void Dss_dctrlAdvVpParamsInit </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="struct_dss___dctrl_adv_vp_params.html">Dss_DctrlAdvVpParams</a> * </td>
+ <td class="paramname"><em>advVpParams</em></td><td>)</td>
+ <td></td>
+ </tr>
+ </table>
+ </td>
+ <td class="mlabels-right">
+<span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span> </td>
+ </tr>
+</table>
+</div><div class="memdoc">
+
+<p><a class="el" href="struct_dss___dctrl_adv_vp_params.html" title="Structure containing advance Video Port information. This structure is used as an argument to IOCTL_D...">Dss_DctrlAdvVpParams</a> structure init function. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">advVpParams</td><td>[IN]Pointer to <a class="el" href="struct_dss___dctrl_adv_vp_params.html" title="Structure containing advance Video Port information. This structure is used as an argument to IOCTL_D...">Dss_DctrlAdvVpParams</a> structure.</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="a9245be86f5b0aa58fd825ddac59b15de"></a>
+<div class="memitem">
+<div class="memproto">
+<table class="mlabels">
+ <tr>
+ <td class="mlabels-left">
+ <table class="memname">
+ <tr>
+ <td class="memname">static void Dss_dctrlGlobalDssParamsInit </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="struct_dss___dctrl_global_dss_params.html">Dss_DctrlGlobalDssParams</a> * </td>
+ <td class="paramname"><em>globalDssParams</em></td><td>)</td>
+ <td></td>
+ </tr>
+ </table>
+ </td>
+ <td class="mlabels-right">
+<span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span> </td>
+ </tr>
+</table>
+</div><div class="memdoc">
+
+<p><a class="el" href="struct_dss___dctrl_global_dss_params.html" title="Structure containing global DSS Configuration. This structure is used as an argument to IOCTL_DSS_DCT...">Dss_DctrlGlobalDssParams</a> structure init function. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">globalDssParams</td><td>[IN]Pointer to <a class="el" href="struct_dss___dctrl_global_dss_params.html" title="Structure containing global DSS Configuration. This structure is used as an argument to IOCTL_DSS_DCT...">Dss_DctrlGlobalDssParams</a> structure.</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="a1bee4f99058e9860ea9e0d8c46713d17"></a>
+<div class="memitem">
+<div class="memproto">
+<table class="mlabels">
+ <tr>
+ <td class="mlabels-left">
+ <table class="memname">
+ <tr>
+ <td class="memname">static void Dss_dctrlLcdBlankTimingParamsInit </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="struct_dss___dctrl_lcd_blank_timing_params.html">Dss_DctrlLcdBlankTimingParams</a> * </td>
+ <td class="paramname"><em>lcdBlankTimingParams</em></td><td>)</td>
+ <td></td>
+ </tr>
+ </table>
+ </td>
+ <td class="mlabels-right">
+<span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span> </td>
+ </tr>
+</table>
+</div><div class="memdoc">
+
+<p><a class="el" href="struct_dss___dctrl_lcd_blank_timing_params.html" title="Structure containing LCD Blank Timing Configuration. This structure is used as an argument to IOCTL_D...">Dss_DctrlLcdBlankTimingParams</a> structure init function. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">lcdBlankTimingParams</td><td>[IN]Pointer to <a class="el" href="struct_dss___dctrl_lcd_blank_timing_params.html" title="Structure containing LCD Blank Timing Configuration. This structure is used as an argument to IOCTL_D...">Dss_DctrlLcdBlankTimingParams</a> structure.</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="a5a26a0b5b1059cb2dc79b0f7ec932cb6"></a>
+<div class="memitem">
+<div class="memproto">
+<table class="mlabels">
+ <tr>
+ <td class="mlabels-left">
+ <table class="memname">
+ <tr>
+ <td class="memname">static void Dss_dctrlOverlayLayerParamsInit </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="struct_dss___dctrl_overlay_layer_params.html">Dss_DctrlOverlayLayerParams</a> * </td>
+ <td class="paramname"><em>layerParams</em></td><td>)</td>
+ <td></td>
+ </tr>
+ </table>
+ </td>
+ <td class="mlabels-right">
+<span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span> </td>
+ </tr>
+</table>
+</div><div class="memdoc">
+
+<p><a class="el" href="struct_dss___dctrl_overlay_layer_params.html" title="Structure containing Overlay layer information. This structure is used as an argument to IOCTL_DSS_DC...">Dss_DctrlOverlayLayerParams</a> structure init function. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">layerParams</td><td>[IN]Pointer to <a class="el" href="struct_dss___dctrl_overlay_layer_params.html" title="Structure containing Overlay layer information. This structure is used as an argument to IOCTL_DSS_DC...">Dss_DctrlOverlayLayerParams</a> structure.</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="aeb3a05c6b9e915a29bfa94784b427f75"></a>
+<div class="memitem">
+<div class="memproto">
+<table class="mlabels">
+ <tr>
+ <td class="mlabels-left">
+ <table class="memname">
+ <tr>
+ <td class="memname">static void Dss_dctrlOverlayParamsInit </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="struct_dss___dctrl_overlay_params.html">Dss_DctrlOverlayParams</a> * </td>
+ <td class="paramname"><em>overlayParams</em></td><td>)</td>
+ <td></td>
+ </tr>
+ </table>
+ </td>
+ <td class="mlabels-right">
+<span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span> </td>
+ </tr>
+</table>
+</div><div class="memdoc">
+
+<p><a class="el" href="struct_dss___dctrl_overlay_params.html" title="Structure containing Overlay information. This structure is used as an argument to IOCTL_DSS_DCTRL_SE...">Dss_DctrlOverlayParams</a> structure init function. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">overlayParams</td><td>[IN]Pointer to <a class="el" href="struct_dss___dctrl_overlay_params.html" title="Structure containing Overlay information. This structure is used as an argument to IOCTL_DSS_DCTRL_SE...">Dss_DctrlOverlayParams</a> structure.</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="a123a4e064a3dd6ae0de052f3668bcc82"></a>
+<div class="memitem">
+<div class="memproto">
+<table class="mlabels">
+ <tr>
+ <td class="mlabels-left">
+ <table class="memname">
+ <tr>
+ <td class="memname">static void Dss_dctrlPathInfoInit </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="struct_dss___dctrl_path_info.html">Dss_DctrlPathInfo</a> * </td>
+ <td class="paramname"><em>pathInfo</em></td><td>)</td>
+ <td></td>
+ </tr>
+ </table>
+ </td>
+ <td class="mlabels-right">
+<span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span> </td>
+ </tr>
+</table>
+</div><div class="memdoc">
+
+<p><a class="el" href="struct_dss___dctrl_path_info.html" title="Structure containing DSS path information. This structure is used as an argument to IOCTL_DSS_DCTRL_S...">Dss_DctrlPathInfo</a> structure init function. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">pathInfo</td><td>[IN]Pointer to <a class="el" href="struct_dss___dctrl_path_info.html" title="Structure containing DSS path information. This structure is used as an argument to IOCTL_DSS_DCTRL_S...">Dss_DctrlPathInfo</a> structure.</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="a128f0b2a1da8e24d1e87993efc59a049"></a>
+<div class="memitem">
+<div class="memproto">
+<table class="mlabels">
+ <tr>
+ <td class="mlabels-left">
+ <table class="memname">
+ <tr>
+ <td class="memname">static void Dss_dctrlRegionSafetyChkCfgInit </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="struct_dss___dctrl_region_safety_chk_cfg.html">Dss_DctrlRegionSafetyChkCfg</a> * </td>
+ <td class="paramname"><em>regionSafetyChkCfg</em></td><td>)</td>
+ <td></td>
+ </tr>
+ </table>
+ </td>
+ <td class="mlabels-right">
+<span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span> </td>
+ </tr>
+</table>
+</div><div class="memdoc">
+
+<p><a class="el" href="struct_dss___dctrl_region_safety_chk_cfg.html" title="Structure containing Safety Check configuration for a particular region. ">Dss_DctrlRegionSafetyChkCfg</a> structure init function. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">regionSafetyChkCfg</td><td>[IN]Pointer to <a class="el" href="struct_dss___dctrl_region_safety_chk_cfg.html" title="Structure containing Safety Check configuration for a particular region. ">Dss_DctrlRegionSafetyChkCfg</a> structure.</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="aa6b7e9e12da3c697e83d78d8909bfdb9"></a>
+<div class="memitem">
+<div class="memproto">
+<table class="mlabels">
+ <tr>
+ <td class="mlabels-left">
+ <table class="memname">
+ <tr>
+ <td class="memname">static void Dss_dctrlSyncLostCbParamsInit </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="struct_dss___dctrl_sync_lost_cb_params.html">Dss_DctrlSyncLostCbParams</a> * </td>
+ <td class="paramname"><em>syncLostCbParams</em></td><td>)</td>
+ <td></td>
+ </tr>
+ </table>
+ </td>
+ <td class="mlabels-right">
+<span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span> </td>
+ </tr>
+</table>
+</div><div class="memdoc">
+
+<p><a class="el" href="struct_dss___dctrl_sync_lost_cb_params.html" title="Structure containing Sync Lost callback parameters. This structure is used as an argument to IOCTL_DS...">Dss_DctrlSyncLostCbParams</a> structure init function. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">syncLostCbParams</td><td>[IN]Pointer to <a class="el" href="struct_dss___dctrl_sync_lost_cb_params.html" title="Structure containing Sync Lost callback parameters. This structure is used as an argument to IOCTL_DS...">Dss_DctrlSyncLostCbParams</a> structure.</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ab7d6c323f77101a8d6f6ec0b36fcd092"></a>
+<div class="memitem">
+<div class="memproto">
+<table class="mlabels">
+ <tr>
+ <td class="mlabels-left">
+ <table class="memname">
+ <tr>
+ <td class="memname">static void Dss_dctrlVpErrorStatsInit </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="struct_dss___dctrl_vp_error_stats.html">Dss_DctrlVpErrorStats</a> * </td>
+ <td class="paramname"><em>vpErrorStats</em></td><td>)</td>
+ <td></td>
+ </tr>
+ </table>
+ </td>
+ <td class="mlabels-right">
+<span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span> </td>
+ </tr>
+</table>
+</div><div class="memdoc">
+
+<p><a class="el" href="struct_dss___dctrl_vp_error_stats.html" title="Structure containing Error Stats of Video Port. This structure is used as an argument to IOCTL_DSS_DC...">Dss_DctrlVpErrorStats</a> structure init function. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">vpErrorStats</td><td>[IN]Pointer to <a class="el" href="struct_dss___dctrl_vp_error_stats.html" title="Structure containing Error Stats of Video Port. This structure is used as an argument to IOCTL_DSS_DC...">Dss_DctrlVpErrorStats</a> structure.</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="aff73397092899b064dc00d8a813286a4"></a>
+<div class="memitem">
+<div class="memproto">
+<table class="mlabels">
+ <tr>
+ <td class="mlabels-left">
+ <table class="memname">
+ <tr>
+ <td class="memname">static void Dss_dctrlVpParamsInit </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="struct_dss___dctrl_vp_params.html">Dss_DctrlVpParams</a> * </td>
+ <td class="paramname"><em>vpParams</em></td><td>)</td>
+ <td></td>
+ </tr>
+ </table>
+ </td>
+ <td class="mlabels-right">
+<span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span> </td>
+ </tr>
+</table>
+</div><div class="memdoc">
+
+<p><a class="el" href="struct_dss___dctrl_vp_params.html" title="Structure containing Video Port information. This structure is used as an argument to IOCTL_DSS_DCTRL...">Dss_DctrlVpParams</a> structure init function. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">vpParams</td><td>[IN]Pointer to <a class="el" href="struct_dss___dctrl_vp_params.html" title="Structure containing Video Port information. This structure is used as an argument to IOCTL_DSS_DCTRL...">Dss_DctrlVpParams</a> structure.</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="a3434c36ddde97b9077bb2b055cf0a4b0"></a>
+<div class="memitem">
+<div class="memproto">
+<table class="mlabels">
+ <tr>
+ <td class="mlabels-left">
+ <table class="memname">
+ <tr>
+ <td class="memname">static void Dss_dctrlVpSafetyChkParamsInit </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="struct_dss___dctrl_vp_safety_chk_params.html">Dss_DctrlVpSafetyChkParams</a> * </td>
+ <td class="paramname"><em>vpSafetyChkParams</em></td><td>)</td>
+ <td></td>
+ </tr>
+ </table>
+ </td>
+ <td class="mlabels-right">
+<span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span> </td>
+ </tr>
+</table>
+</div><div class="memdoc">
+
+<p><a class="el" href="struct_dss___dctrl_vp_safety_chk_params.html" title="Structure containing Safety Check configuration of Video Port. This structure is used as an argument ...">Dss_DctrlVpSafetyChkParams</a> structure init function. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">vpSafetyChkParams</td><td>[IN]Pointer to <a class="el" href="struct_dss___dctrl_vp_safety_chk_params.html" title="Structure containing Safety Check configuration of Video Port. This structure is used as an argument ...">Dss_DctrlVpSafetyChkParams</a> structure.</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None </dd></dl>
+
+</div>
+</div>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/dss__disp_8h.html b/packages/ti/drv/dss/docs/doxygen/html/dss__disp_8h.html
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+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>dss_disp.h File Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
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+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
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+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
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+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li class="current"><a href="files.html"><span>Files</span></a></li>
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+ <ul class="tablist">
+ <li><a href="files.html"><span>File List</span></a></li>
+ <li><a href="globals.html"><span>Globals</span></a></li>
+ </ul>
+ </div>
+<div id="nav-path" class="navpath">
+ <ul>
+<li class="navelem"><a class="el" href="dir_0fa78962abed40d3d8df26bacdfc9ada.html">include</a></li> </ul>
+</div>
+</div><!-- top -->
+<div class="header">
+ <div class="summary">
+<a href="#nested-classes">Data Structures</a> |
+<a href="#define-members">Macros</a> |
+<a href="#typedef-members">Typedefs</a> |
+<a href="#func-members">Functions</a> </div>
+ <div class="headertitle">
+<div class="title">dss_disp.h File Reference</div> </div>
+</div><!--header-->
+<div class="contents">
+
+<p>DSS Display Driver interface file.
+<a href="#details">More...</a></p>
+<table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="nested-classes"></a>
+Data Structures</h2></td></tr>
+<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___disp_create_params.html">Dss_DispCreateParams</a></td></tr>
+<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">Structure containing display driver create arguments, used when calling Fvid2_create(). <a href="struct_dss___disp_create_params.html#details">More...</a><br/></td></tr>
+<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___disp_create_status.html">Dss_DispCreateStatus</a></td></tr>
+<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">Structure containing create status for the display driver. This should be passed as a status argument while creating the driver. <a href="struct_dss___disp_create_status.html#details">More...</a><br/></td></tr>
+<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___disp_params.html">Dss_DispParams</a></td></tr>
+<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">Structure containing DSS parameters. This structure is used as an argument to IOCTL_DSS_DISP_SET_DSS_PARAMS. <a href="struct_dss___disp_params.html#details">More...</a><br/></td></tr>
+<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___disp_pipe_mflag_params.html">Dss_DispPipeMflagParams</a></td></tr>
+<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">Structure containing Video Pipe Mflag Information. This structure is used as an argument to IOCTL_DSS_DISP_SET_PIPE_MFLAG_PARAMS. <a href="struct_dss___disp_pipe_mflag_params.html#details">More...</a><br/></td></tr>
+<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___disp_current_status.html">Dss_DispCurrentStatus</a></td></tr>
+<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">Structure containing current status of the display driver. This structure is used as an argument to IOCTL_DSS_DISP_GET_CURRENT_STATUS. <a href="struct_dss___disp_current_status.html#details">More...</a><br/></td></tr>
+<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___disp_pipe_safety_chk_params.html">Dss_DispPipeSafetyChkParams</a></td></tr>
+<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">Structure containing Safety Check configuration of Video Port. This structure is used as an argument to IOCTL_DSS_DISP_SET_PIPE_SAFETY_CHK_PARAMS. <a href="struct_dss___disp_pipe_safety_chk_params.html#details">More...</a><br/></td></tr>
+<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___disp_buf_prgm_cb_params.html">Dss_DispBufPrgmCbParams</a></td></tr>
+<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">Structure containing display buffer program callback parameters. This structure is used as an argument to IOCTL_DSS_DISP_REGISTER_BUF_PRGM_CB. <a href="struct_dss___disp_buf_prgm_cb_params.html#details">More...</a><br/></td></tr>
+<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___disp_pipe_prgm_cb_params.html">Dss_DispPipePrgmCbParams</a></td></tr>
+<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">Structure containing video pipe program callback parameters. This structure is used as an argument to IOCTL_DSS_DISP_REGISTER_PIPE_PRGM_CB. <a href="struct_dss___disp_pipe_prgm_cb_params.html#details">More...</a><br/></td></tr>
+<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___disp_under_flow_cb_params.html">Dss_DispUnderFlowCbParams</a></td></tr>
+<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">Structure containing pipe under flow callback parameters. This structure is used as an argument to IOCTL_DSS_DISP_REGISTER_PIPE_UNDERFLOW_CB. <a href="struct_dss___disp_under_flow_cb_params.html#details">More...</a><br/></td></tr>
+<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___sc_rt_params.html">Dss_ScRtParams</a></td></tr>
+<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">Structure containing run time scaler configuration. <a href="struct_dss___sc_rt_params.html#details">More...</a><br/></td></tr>
+<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___frame_rt_params.html">Dss_FrameRtParams</a></td></tr>
+<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">Structure containing run time configuration per frame. <a href="struct_dss___frame_rt_params.html#details">More...</a><br/></td></tr>
+<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___disp_rt_params.html">Dss_DispRtParams</a></td></tr>
+<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">Structure containing run time configuration of the display driver. This needs to be passed along with frame list to update any supported run time parameters. <a href="struct_dss___disp_rt_params.html#details">More...</a><br/></td></tr>
+<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
+Macros</h2></td></tr>
+<tr class="memitem:a8e15b63c9ad0534336ab8b75c714c873"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a8e15b63c9ad0534336ab8b75c714c873"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="dss__disp_8h.html#a8e15b63c9ad0534336ab8b75c714c873">DSS_BUFFER_ALIGNMENT</a>   (16U)</td></tr>
+<tr class="memdesc:a8e15b63c9ad0534336ab8b75c714c873"><td class="mdescLeft"> </td><td class="mdescRight">DSS video buffer alignment. All application buffer address and line pitch should be aligned to this byte boundary. <br/></td></tr>
+<tr class="separator:a8e15b63c9ad0534336ab8b75c714c873"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga4bd8cea3f070081f575996cc7fe3571f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___d_s_s___d_i_s_p___i_o_c_t_l.html#ga4bd8cea3f070081f575996cc7fe3571f">IOCTL_DSS_DISP_SET_DSS_PARAMS</a>   (<a class="el" href="group___d_s_s.html#gaf8566eb291e6ce8c67bf5158426d42b9">DSS_DISP_IOCTL_BASE</a> + 0x0001U)</td></tr>
+<tr class="memdesc:ga4bd8cea3f070081f575996cc7fe3571f"><td class="mdescLeft"> </td><td class="mdescRight">Command to set DSS display parameters. <a href="group___d_s_s___d_i_s_p___i_o_c_t_l.html#ga4bd8cea3f070081f575996cc7fe3571f">More...</a><br/></td></tr>
+<tr class="separator:ga4bd8cea3f070081f575996cc7fe3571f"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga9643f8f73bbe0006d0c56d0bcedccef5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___d_s_s___d_i_s_p___i_o_c_t_l.html#ga9643f8f73bbe0006d0c56d0bcedccef5">IOCTL_DSS_DISP_SET_PIPE_MFLAG_PARAMS</a>   (<a class="el" href="group___d_s_s.html#gaf8566eb291e6ce8c67bf5158426d42b9">DSS_DISP_IOCTL_BASE</a> + 0x0002U)</td></tr>
+<tr class="memdesc:ga9643f8f73bbe0006d0c56d0bcedccef5"><td class="mdescLeft"> </td><td class="mdescRight">Command to set MFLAG parameters for video pipe. <a href="group___d_s_s___d_i_s_p___i_o_c_t_l.html#ga9643f8f73bbe0006d0c56d0bcedccef5">More...</a><br/></td></tr>
+<tr class="separator:ga9643f8f73bbe0006d0c56d0bcedccef5"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga0b629ede4d23a166a0d61a8a467cf2a7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___d_s_s___d_i_s_p___i_o_c_t_l.html#ga0b629ede4d23a166a0d61a8a467cf2a7">IOCTL_DSS_DISP_GET_CURRENT_STATUS</a>   (<a class="el" href="group___d_s_s.html#gaf8566eb291e6ce8c67bf5158426d42b9">DSS_DISP_IOCTL_BASE</a> + 0x0003U)</td></tr>
+<tr class="memdesc:ga0b629ede4d23a166a0d61a8a467cf2a7"><td class="mdescLeft"> </td><td class="mdescRight">Command to get the display status. <a href="group___d_s_s___d_i_s_p___i_o_c_t_l.html#ga0b629ede4d23a166a0d61a8a467cf2a7">More...</a><br/></td></tr>
+<tr class="separator:ga0b629ede4d23a166a0d61a8a467cf2a7"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga71325651456731ff972f3f976632f817"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___d_s_s___d_i_s_p___i_o_c_t_l.html#ga71325651456731ff972f3f976632f817">IOCTL_DSS_DISP_SET_PIPE_SAFETY_CHK_PARAMS</a>   (<a class="el" href="group___d_s_s.html#gaf8566eb291e6ce8c67bf5158426d42b9">DSS_DISP_IOCTL_BASE</a> + 0x0004U)</td></tr>
+<tr class="memdesc:ga71325651456731ff972f3f976632f817"><td class="mdescLeft"> </td><td class="mdescRight">Command to program Safety Check configuration at Video Pipe Output. <a href="group___d_s_s___d_i_s_p___i_o_c_t_l.html#ga71325651456731ff972f3f976632f817">More...</a><br/></td></tr>
+<tr class="separator:ga71325651456731ff972f3f976632f817"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gaa06196d5ebeb859291214d2d54b6858b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___d_s_s___d_i_s_p___i_o_c_t_l.html#gaa06196d5ebeb859291214d2d54b6858b">IOCTL_DSS_DISP_SET_PIPE_CSC_COEFF</a>   (<a class="el" href="group___d_s_s.html#gaf8566eb291e6ce8c67bf5158426d42b9">DSS_DISP_IOCTL_BASE</a> + 0x0005U)</td></tr>
+<tr class="memdesc:gaa06196d5ebeb859291214d2d54b6858b"><td class="mdescLeft"> </td><td class="mdescRight">Command to program the CSC coefficients for Video Pipe. By default BT 601 coefficients are set. <a href="group___d_s_s___d_i_s_p___i_o_c_t_l.html#gaa06196d5ebeb859291214d2d54b6858b">More...</a><br/></td></tr>
+<tr class="separator:gaa06196d5ebeb859291214d2d54b6858b"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga273f588861739dcf0a3e69409cb86946"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___d_s_s___d_i_s_p___i_o_c_t_l.html#ga273f588861739dcf0a3e69409cb86946">IOCTL_DSS_DISP_REGISTER_BUF_PRGM_CB</a>   (<a class="el" href="group___d_s_s.html#gaf8566eb291e6ce8c67bf5158426d42b9">DSS_DISP_IOCTL_BASE</a> + 0x0006U)</td></tr>
+<tr class="memdesc:ga273f588861739dcf0a3e69409cb86946"><td class="mdescLeft"> </td><td class="mdescRight">Command to register buffer program callback function. <a href="group___d_s_s___d_i_s_p___i_o_c_t_l.html#ga273f588861739dcf0a3e69409cb86946">More...</a><br/></td></tr>
+<tr class="separator:ga273f588861739dcf0a3e69409cb86946"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga0cb126061bb1b12410ac877e1f8ba1eb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___d_s_s___d_i_s_p___i_o_c_t_l.html#ga0cb126061bb1b12410ac877e1f8ba1eb">IOCTL_DSS_DISP_REGISTER_PIPE_PRGM_CB</a>   (<a class="el" href="group___d_s_s.html#gaf8566eb291e6ce8c67bf5158426d42b9">DSS_DISP_IOCTL_BASE</a> + 0x0007U)</td></tr>
+<tr class="memdesc:ga0cb126061bb1b12410ac877e1f8ba1eb"><td class="mdescLeft"> </td><td class="mdescRight">Command to register video pipe program callback function. <a href="group___d_s_s___d_i_s_p___i_o_c_t_l.html#ga0cb126061bb1b12410ac877e1f8ba1eb">More...</a><br/></td></tr>
+<tr class="separator:ga0cb126061bb1b12410ac877e1f8ba1eb"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga50c39b909c3e819d5662285112bbca59"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___d_s_s___d_i_s_p___i_o_c_t_l.html#ga50c39b909c3e819d5662285112bbca59">IOCTL_DSS_DISP_REGISTER_PIPE_UNDERFLOW_CB</a>   (<a class="el" href="group___d_s_s.html#gaf8566eb291e6ce8c67bf5158426d42b9">DSS_DISP_IOCTL_BASE</a> + 0x0008U)</td></tr>
+<tr class="memdesc:ga50c39b909c3e819d5662285112bbca59"><td class="mdescLeft"> </td><td class="mdescRight">Command to register video pipe underflow callback function. <a href="group___d_s_s___d_i_s_p___i_o_c_t_l.html#ga50c39b909c3e819d5662285112bbca59">More...</a><br/></td></tr>
+<tr class="separator:ga50c39b909c3e819d5662285112bbca59"><td class="memSeparator" colspan="2"> </td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="typedef-members"></a>
+Typedefs</h2></td></tr>
+<tr class="memitem:a3f3415894bf0e54f2d06f24ea22c602e"><td class="memItemLeft" align="right" valign="top">typedef <a class="el" href="struct_fvid2___frame.html">Fvid2_Frame</a> *(* </td><td class="memItemRight" valign="bottom"><a class="el" href="dss__disp_8h.html#a3f3415894bf0e54f2d06f24ea22c602e">Dss_DispBufPrgmCbFxn</a> )(Fvid2_Handle handle, <a class="el" href="struct_fvid2___frame.html">Fvid2_Frame</a> *curFrm, uint32_t isFrmRepeat, uint32_t frmRepeatCnt)</td></tr>
+<tr class="memdesc:a3f3415894bf0e54f2d06f24ea22c602e"><td class="mdescLeft"> </td><td class="mdescRight">Display driver buffer program callback function prototype. <a href="#a3f3415894bf0e54f2d06f24ea22c602e">More...</a><br/></td></tr>
+<tr class="separator:a3f3415894bf0e54f2d06f24ea22c602e"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a4ccdd634499058281998bcc9a7af0555"><td class="memItemLeft" align="right" valign="top">typedef int32_t(* </td><td class="memItemRight" valign="bottom"><a class="el" href="dss__disp_8h.html#a4ccdd634499058281998bcc9a7af0555">Dss_DispPipePrgmCbFxn</a> )(<a class="el" href="struct_fvid2___frame.html">Fvid2_Frame</a> *progFrm, void *appData)</td></tr>
+<tr class="memdesc:a4ccdd634499058281998bcc9a7af0555"><td class="mdescLeft"> </td><td class="mdescRight">Display driver video pipe program callback function prototype. <a href="#a4ccdd634499058281998bcc9a7af0555">More...</a><br/></td></tr>
+<tr class="separator:a4ccdd634499058281998bcc9a7af0555"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a14c7b8d97214b5c092eb8702e24522a1"><td class="memItemLeft" align="right" valign="top">typedef void(* </td><td class="memItemRight" valign="bottom"><a class="el" href="dss__disp_8h.html#a14c7b8d97214b5c092eb8702e24522a1">Dss_DispUnderFlowCbFxn</a> )(void *appData)</td></tr>
+<tr class="memdesc:a14c7b8d97214b5c092eb8702e24522a1"><td class="mdescLeft"> </td><td class="mdescRight">Video pipe underflow callback function prototype. <a href="#a14c7b8d97214b5c092eb8702e24522a1">More...</a><br/></td></tr>
+<tr class="separator:a14c7b8d97214b5c092eb8702e24522a1"><td class="memSeparator" colspan="2"> </td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a>
+Functions</h2></td></tr>
+<tr class="memitem:a0b1e08d5de369b9d9bfeaf4ab7841884"><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="dss__disp_8h.html#a0b1e08d5de369b9d9bfeaf4ab7841884">Dss_dispCreateParamsInit</a> (<a class="el" href="struct_dss___disp_create_params.html">Dss_DispCreateParams</a> *createParams)</td></tr>
+<tr class="memdesc:a0b1e08d5de369b9d9bfeaf4ab7841884"><td class="mdescLeft"> </td><td class="mdescRight"><a class="el" href="struct_dss___disp_create_params.html" title="Structure containing display driver create arguments, used when calling Fvid2_create(). ">Dss_DispCreateParams</a> structure init function. <a href="#a0b1e08d5de369b9d9bfeaf4ab7841884">More...</a><br/></td></tr>
+<tr class="separator:a0b1e08d5de369b9d9bfeaf4ab7841884"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ade1761a8d085738b03f4a2d3a4af24b3"><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="dss__disp_8h.html#ade1761a8d085738b03f4a2d3a4af24b3">Dss_dispParamsInit</a> (<a class="el" href="struct_dss___disp_params.html">Dss_DispParams</a> *dssParams)</td></tr>
+<tr class="memdesc:ade1761a8d085738b03f4a2d3a4af24b3"><td class="mdescLeft"> </td><td class="mdescRight"><a class="el" href="struct_dss___disp_params.html" title="Structure containing DSS parameters. This structure is used as an argument to IOCTL_DSS_DISP_SET_DSS_...">Dss_DispParams</a> structure init function. <a href="#ade1761a8d085738b03f4a2d3a4af24b3">More...</a><br/></td></tr>
+<tr class="separator:ade1761a8d085738b03f4a2d3a4af24b3"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a870942fd13c4ea685c1e03b4fe51da4c"><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="dss__disp_8h.html#a870942fd13c4ea685c1e03b4fe51da4c">Dss_dispPipeMflagParamsInit</a> (<a class="el" href="struct_dss___disp_pipe_mflag_params.html">Dss_DispPipeMflagParams</a> *pipeMflagParams)</td></tr>
+<tr class="memdesc:a870942fd13c4ea685c1e03b4fe51da4c"><td class="mdescLeft"> </td><td class="mdescRight"><a class="el" href="struct_dss___disp_pipe_mflag_params.html" title="Structure containing Video Pipe Mflag Information. This structure is used as an argument to IOCTL_DSS...">Dss_DispPipeMflagParams</a> structure init function. <a href="#a870942fd13c4ea685c1e03b4fe51da4c">More...</a><br/></td></tr>
+<tr class="separator:a870942fd13c4ea685c1e03b4fe51da4c"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:aa658322ec9e4dff9106f95f92439aa16"><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="dss__disp_8h.html#aa658322ec9e4dff9106f95f92439aa16">Dss_dispPipeSafetyChkParamsInit</a> (<a class="el" href="struct_dss___disp_pipe_safety_chk_params.html">Dss_DispPipeSafetyChkParams</a> *pipeSafetyChkParams)</td></tr>
+<tr class="memdesc:aa658322ec9e4dff9106f95f92439aa16"><td class="mdescLeft"> </td><td class="mdescRight"><a class="el" href="struct_dss___disp_pipe_safety_chk_params.html" title="Structure containing Safety Check configuration of Video Port. This structure is used as an argument ...">Dss_DispPipeSafetyChkParams</a> structure init function. <a href="#aa658322ec9e4dff9106f95f92439aa16">More...</a><br/></td></tr>
+<tr class="separator:aa658322ec9e4dff9106f95f92439aa16"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a5d7c65146501cb5e2e4bfeee924afe1c"><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="dss__disp_8h.html#a5d7c65146501cb5e2e4bfeee924afe1c">Dss_dispBufPrgmCbParamsInit</a> (<a class="el" href="struct_dss___disp_buf_prgm_cb_params.html">Dss_DispBufPrgmCbParams</a> *bufPrgmCbParams)</td></tr>
+<tr class="memdesc:a5d7c65146501cb5e2e4bfeee924afe1c"><td class="mdescLeft"> </td><td class="mdescRight"><a class="el" href="struct_dss___disp_buf_prgm_cb_params.html" title="Structure containing display buffer program callback parameters. This structure is used as an argumen...">Dss_DispBufPrgmCbParams</a> structure init function. <a href="#a5d7c65146501cb5e2e4bfeee924afe1c">More...</a><br/></td></tr>
+<tr class="separator:a5d7c65146501cb5e2e4bfeee924afe1c"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a6c10a27c661e431f53014ed39b8335ec"><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="dss__disp_8h.html#a6c10a27c661e431f53014ed39b8335ec">Dss_dispPipePrgmCbParamsInit</a> (<a class="el" href="struct_dss___disp_pipe_prgm_cb_params.html">Dss_DispPipePrgmCbParams</a> *pipePrgmCbParams)</td></tr>
+<tr class="memdesc:a6c10a27c661e431f53014ed39b8335ec"><td class="mdescLeft"> </td><td class="mdescRight"><a class="el" href="struct_dss___disp_pipe_prgm_cb_params.html" title="Structure containing video pipe program callback parameters. This structure is used as an argument to...">Dss_DispPipePrgmCbParams</a> structure init function. <a href="#a6c10a27c661e431f53014ed39b8335ec">More...</a><br/></td></tr>
+<tr class="separator:a6c10a27c661e431f53014ed39b8335ec"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a076a2c0095da75002988e147c8f9991c"><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="dss__disp_8h.html#a076a2c0095da75002988e147c8f9991c">Dss_dispUnderFlowCbParamsInit</a> (<a class="el" href="struct_dss___disp_under_flow_cb_params.html">Dss_DispUnderFlowCbParams</a> *underFlowCbParams)</td></tr>
+<tr class="memdesc:a076a2c0095da75002988e147c8f9991c"><td class="mdescLeft"> </td><td class="mdescRight"><a class="el" href="struct_dss___disp_under_flow_cb_params.html" title="Structure containing pipe under flow callback parameters. This structure is used as an argument to IO...">Dss_DispUnderFlowCbParams</a> structure init function. <a href="#a076a2c0095da75002988e147c8f9991c">More...</a><br/></td></tr>
+<tr class="separator:a076a2c0095da75002988e147c8f9991c"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a9f3129c4857d08aec6387867cc2e778c"><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="dss__disp_8h.html#a9f3129c4857d08aec6387867cc2e778c">Dss_scRtParamsInit</a> (<a class="el" href="struct_dss___sc_rt_params.html">Dss_ScRtParams</a> *scRtParams)</td></tr>
+<tr class="memdesc:a9f3129c4857d08aec6387867cc2e778c"><td class="mdescLeft"> </td><td class="mdescRight"><a class="el" href="struct_dss___sc_rt_params.html" title="Structure containing run time scaler configuration. ">Dss_ScRtParams</a> structure init function. <a href="#a9f3129c4857d08aec6387867cc2e778c">More...</a><br/></td></tr>
+<tr class="separator:a9f3129c4857d08aec6387867cc2e778c"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a20946243c0b2d8b3c5b317098abfba69"><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="dss__disp_8h.html#a20946243c0b2d8b3c5b317098abfba69">Dss_frameRtParamsInit</a> (<a class="el" href="struct_dss___frame_rt_params.html">Dss_FrameRtParams</a> *frameRtParams)</td></tr>
+<tr class="memdesc:a20946243c0b2d8b3c5b317098abfba69"><td class="mdescLeft"> </td><td class="mdescRight"><a class="el" href="struct_dss___frame_rt_params.html" title="Structure containing run time configuration per frame. ">Dss_FrameRtParams</a> structure init function. <a href="#a20946243c0b2d8b3c5b317098abfba69">More...</a><br/></td></tr>
+<tr class="separator:a20946243c0b2d8b3c5b317098abfba69"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ae1a443826f5f5c55bb40417fcb689bcd"><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="dss__disp_8h.html#ae1a443826f5f5c55bb40417fcb689bcd">Dss_dispRtParamsInit</a> (<a class="el" href="struct_dss___disp_rt_params.html">Dss_DispRtParams</a> *rtParams)</td></tr>
+<tr class="memdesc:ae1a443826f5f5c55bb40417fcb689bcd"><td class="mdescLeft"> </td><td class="mdescRight"><a class="el" href="struct_dss___disp_rt_params.html" title="Structure containing run time configuration of the display driver. This needs to be passed along with...">Dss_DispRtParams</a> structure init function. <a href="#ae1a443826f5f5c55bb40417fcb689bcd">More...</a><br/></td></tr>
+<tr class="separator:ae1a443826f5f5c55bb40417fcb689bcd"><td class="memSeparator" colspan="2"> </td></tr>
+</table>
+<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
+<div class="textblock"><p>DSS Display Driver interface file. </p>
+</div><h2 class="groupheader">Typedef Documentation</h2>
+<a class="anchor" id="a3f3415894bf0e54f2d06f24ea22c602e"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">typedef <a class="el" href="struct_fvid2___frame.html">Fvid2_Frame</a>*(* Dss_DispBufPrgmCbFxn)(Fvid2_Handle handle, <a class="el" href="struct_fvid2___frame.html">Fvid2_Frame</a> *curFrm, uint32_t isFrmRepeat, uint32_t frmRepeatCnt)</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+
+<p>Display driver buffer program callback function prototype. </p>
+<p>This callback is called by the driver when it is about to program the already queued buffer to the hardware. The driver returns the current frame pointer and the application can use this information to check if the buffer to be programmed is too old to display. If it decides so, the application can give a new frame buffer (blank frame) in the return parameter. Then the driver swaps this FVID2 frame pointer in its internal queue and program the new frame provided.</p>
+<p>Note: Once the frame is swapped with the driver, the driver will not have any reference to the old frame. The ownership of the old frame is transferred to application and will not be returned in the driver dequeue operation.</p>
+<p>User should assume that callbacks happen in ISR context and hence should apply rules relevant to ISR context when implementing callback functions, i.e. blocking APIs should not be called from callback. Users should also assume that interrupts are enabled when in callback context, i.e. other interrupt / callbacks can occur when a callback is under execution. User callback implementation should not be very long, since callback execution may block other drivers from executing. Typically it is recommended to set a semaphore or flag when callback happens and do the more involved callback handling in task context.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">handle</td><td>[OUT] FVID2 handle for which the callback has occurred. </td></tr>
+ <tr><td class="paramname">curFrm</td><td>[OUT] Current FVID2 frame about to be programmed. </td></tr>
+ <tr><td class="paramname">isFrmRepeat</td><td>[OUT] Flag to indicate whether the current frame is already programmed in the hardware. </td></tr>
+ <tr><td class="paramname">frmRepeatCnt</td><td>[OUT] This variable indicates the frame repeat count reflecting the hardware queue depth. In case of DSS, we have actual register and shadow register. Hence this value could be 1 or 2 for most of the cases. 1 means normal operating mode without frame repeat. 2 means both the shadow and current register have the same buffer i.e. the frame is getting repeated. There is a special case when this value is 0. This means the driver is trying to program the register in low latency mode in task context. But the success of the buffer getting accepted depends on when the queue is called with respect to VSYNC. If the Queue call is very near the VSYNC say 10 lines before VSYNC, the buffer programming will not be accepted. And the application should assume that the buffer will gets programmed in the next VSYNC only.</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>The application can return the new FVID2 frame to be used for programming the hardware. If the application returns NULL no action is taken and the driver will go ahead and program the current frame to hardware. </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="a4ccdd634499058281998bcc9a7af0555"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">typedef int32_t(* Dss_DispPipePrgmCbFxn)(<a class="el" href="struct_fvid2___frame.html">Fvid2_Frame</a> *progFrm, void *appData)</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+
+<p>Display driver video pipe program callback function prototype. </p>
+<p>This callback is called by the driver after it has programmed the already queued buffer to the hardware. The application can use this callback to simulate a VSYNC. The driver returns the programmed frame pointer to the application.</p>
+<p>User should assume that callbacks happen in ISR context and hence should apply rules relevant to ISR context when implementing callback functions, i.e. blocking APIs should not be called from callback. User callback implementation should not be very long, since callback execution may block other drivers from executing. Typically it is recommended to set a semaphore or flag when callback happens and do the more involved callback handling in task context.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">progFrm</td><td>[OUT] Current FVID2 frame that has been programmed. </td></tr>
+ <tr><td class="paramname">appData</td><td>[OUT] Application's private data.</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>Status </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="a14c7b8d97214b5c092eb8702e24522a1"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">typedef void(* Dss_DispUnderFlowCbFxn)(void *appData)</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+
+<p>Video pipe underflow callback function prototype. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">appData</td><td>[OUT] Application's private data.</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None. </dd></dl>
+
+</div>
+</div>
+<h2 class="groupheader">Function Documentation</h2>
+<a class="anchor" id="a5d7c65146501cb5e2e4bfeee924afe1c"></a>
+<div class="memitem">
+<div class="memproto">
+<table class="mlabels">
+ <tr>
+ <td class="mlabels-left">
+ <table class="memname">
+ <tr>
+ <td class="memname">static void Dss_dispBufPrgmCbParamsInit </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="struct_dss___disp_buf_prgm_cb_params.html">Dss_DispBufPrgmCbParams</a> * </td>
+ <td class="paramname"><em>bufPrgmCbParams</em></td><td>)</td>
+ <td></td>
+ </tr>
+ </table>
+ </td>
+ <td class="mlabels-right">
+<span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span> </td>
+ </tr>
+</table>
+</div><div class="memdoc">
+
+<p><a class="el" href="struct_dss___disp_buf_prgm_cb_params.html" title="Structure containing display buffer program callback parameters. This structure is used as an argumen...">Dss_DispBufPrgmCbParams</a> structure init function. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">bufPrgmCbParams</td><td>[IN]Pointer to <a class="el" href="struct_dss___disp_buf_prgm_cb_params.html" title="Structure containing display buffer program callback parameters. This structure is used as an argumen...">Dss_DispBufPrgmCbParams</a> structure.</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="a0b1e08d5de369b9d9bfeaf4ab7841884"></a>
+<div class="memitem">
+<div class="memproto">
+<table class="mlabels">
+ <tr>
+ <td class="mlabels-left">
+ <table class="memname">
+ <tr>
+ <td class="memname">static void Dss_dispCreateParamsInit </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="struct_dss___disp_create_params.html">Dss_DispCreateParams</a> * </td>
+ <td class="paramname"><em>createParams</em></td><td>)</td>
+ <td></td>
+ </tr>
+ </table>
+ </td>
+ <td class="mlabels-right">
+<span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span> </td>
+ </tr>
+</table>
+</div><div class="memdoc">
+
+<p><a class="el" href="struct_dss___disp_create_params.html" title="Structure containing display driver create arguments, used when calling Fvid2_create(). ">Dss_DispCreateParams</a> structure init function. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">createParams</td><td>[IN]Pointer to <a class="el" href="struct_dss___disp_create_params.html" title="Structure containing display driver create arguments, used when calling Fvid2_create(). ">Dss_DispCreateParams</a> structure.</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ade1761a8d085738b03f4a2d3a4af24b3"></a>
+<div class="memitem">
+<div class="memproto">
+<table class="mlabels">
+ <tr>
+ <td class="mlabels-left">
+ <table class="memname">
+ <tr>
+ <td class="memname">static void Dss_dispParamsInit </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="struct_dss___disp_params.html">Dss_DispParams</a> * </td>
+ <td class="paramname"><em>dssParams</em></td><td>)</td>
+ <td></td>
+ </tr>
+ </table>
+ </td>
+ <td class="mlabels-right">
+<span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span> </td>
+ </tr>
+</table>
+</div><div class="memdoc">
+
+<p><a class="el" href="struct_dss___disp_params.html" title="Structure containing DSS parameters. This structure is used as an argument to IOCTL_DSS_DISP_SET_DSS_...">Dss_DispParams</a> structure init function. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">dssParams</td><td>[IN]Pointer to <a class="el" href="struct_dss___disp_params.html" title="Structure containing DSS parameters. This structure is used as an argument to IOCTL_DSS_DISP_SET_DSS_...">Dss_DispParams</a> structure.</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="a870942fd13c4ea685c1e03b4fe51da4c"></a>
+<div class="memitem">
+<div class="memproto">
+<table class="mlabels">
+ <tr>
+ <td class="mlabels-left">
+ <table class="memname">
+ <tr>
+ <td class="memname">static void Dss_dispPipeMflagParamsInit </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="struct_dss___disp_pipe_mflag_params.html">Dss_DispPipeMflagParams</a> * </td>
+ <td class="paramname"><em>pipeMflagParams</em></td><td>)</td>
+ <td></td>
+ </tr>
+ </table>
+ </td>
+ <td class="mlabels-right">
+<span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span> </td>
+ </tr>
+</table>
+</div><div class="memdoc">
+
+<p><a class="el" href="struct_dss___disp_pipe_mflag_params.html" title="Structure containing Video Pipe Mflag Information. This structure is used as an argument to IOCTL_DSS...">Dss_DispPipeMflagParams</a> structure init function. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">pipeMflagParams</td><td>[IN]Pointer to <a class="el" href="struct_dss___disp_pipe_mflag_params.html" title="Structure containing Video Pipe Mflag Information. This structure is used as an argument to IOCTL_DSS...">Dss_DispPipeMflagParams</a> structure.</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="a6c10a27c661e431f53014ed39b8335ec"></a>
+<div class="memitem">
+<div class="memproto">
+<table class="mlabels">
+ <tr>
+ <td class="mlabels-left">
+ <table class="memname">
+ <tr>
+ <td class="memname">static void Dss_dispPipePrgmCbParamsInit </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="struct_dss___disp_pipe_prgm_cb_params.html">Dss_DispPipePrgmCbParams</a> * </td>
+ <td class="paramname"><em>pipePrgmCbParams</em></td><td>)</td>
+ <td></td>
+ </tr>
+ </table>
+ </td>
+ <td class="mlabels-right">
+<span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span> </td>
+ </tr>
+</table>
+</div><div class="memdoc">
+
+<p><a class="el" href="struct_dss___disp_pipe_prgm_cb_params.html" title="Structure containing video pipe program callback parameters. This structure is used as an argument to...">Dss_DispPipePrgmCbParams</a> structure init function. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">pipePrgmCbParams</td><td>[IN]Pointer to <a class="el" href="struct_dss___disp_pipe_prgm_cb_params.html" title="Structure containing video pipe program callback parameters. This structure is used as an argument to...">Dss_DispPipePrgmCbParams</a> structure.</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="aa658322ec9e4dff9106f95f92439aa16"></a>
+<div class="memitem">
+<div class="memproto">
+<table class="mlabels">
+ <tr>
+ <td class="mlabels-left">
+ <table class="memname">
+ <tr>
+ <td class="memname">static void Dss_dispPipeSafetyChkParamsInit </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="struct_dss___disp_pipe_safety_chk_params.html">Dss_DispPipeSafetyChkParams</a> * </td>
+ <td class="paramname"><em>pipeSafetyChkParams</em></td><td>)</td>
+ <td></td>
+ </tr>
+ </table>
+ </td>
+ <td class="mlabels-right">
+<span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span> </td>
+ </tr>
+</table>
+</div><div class="memdoc">
+
+<p><a class="el" href="struct_dss___disp_pipe_safety_chk_params.html" title="Structure containing Safety Check configuration of Video Port. This structure is used as an argument ...">Dss_DispPipeSafetyChkParams</a> structure init function. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">pipeSafetyChkParams</td><td>[IN]Pointer to <a class="el" href="struct_dss___disp_pipe_safety_chk_params.html" title="Structure containing Safety Check configuration of Video Port. This structure is used as an argument ...">Dss_DispPipeSafetyChkParams</a> structure.</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ae1a443826f5f5c55bb40417fcb689bcd"></a>
+<div class="memitem">
+<div class="memproto">
+<table class="mlabels">
+ <tr>
+ <td class="mlabels-left">
+ <table class="memname">
+ <tr>
+ <td class="memname">static void Dss_dispRtParamsInit </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="struct_dss___disp_rt_params.html">Dss_DispRtParams</a> * </td>
+ <td class="paramname"><em>rtParams</em></td><td>)</td>
+ <td></td>
+ </tr>
+ </table>
+ </td>
+ <td class="mlabels-right">
+<span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span> </td>
+ </tr>
+</table>
+</div><div class="memdoc">
+
+<p><a class="el" href="struct_dss___disp_rt_params.html" title="Structure containing run time configuration of the display driver. This needs to be passed along with...">Dss_DispRtParams</a> structure init function. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">rtParams</td><td>[IN]Pointer to <a class="el" href="struct_dss___disp_rt_params.html" title="Structure containing run time configuration of the display driver. This needs to be passed along with...">Dss_DispRtParams</a> structure.</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="a076a2c0095da75002988e147c8f9991c"></a>
+<div class="memitem">
+<div class="memproto">
+<table class="mlabels">
+ <tr>
+ <td class="mlabels-left">
+ <table class="memname">
+ <tr>
+ <td class="memname">static void Dss_dispUnderFlowCbParamsInit </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="struct_dss___disp_under_flow_cb_params.html">Dss_DispUnderFlowCbParams</a> * </td>
+ <td class="paramname"><em>underFlowCbParams</em></td><td>)</td>
+ <td></td>
+ </tr>
+ </table>
+ </td>
+ <td class="mlabels-right">
+<span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span> </td>
+ </tr>
+</table>
+</div><div class="memdoc">
+
+<p><a class="el" href="struct_dss___disp_under_flow_cb_params.html" title="Structure containing pipe under flow callback parameters. This structure is used as an argument to IO...">Dss_DispUnderFlowCbParams</a> structure init function. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">underFlowCbParams</td><td>[IN]Pointer to <a class="el" href="struct_dss___disp_under_flow_cb_params.html" title="Structure containing pipe under flow callback parameters. This structure is used as an argument to IO...">Dss_DispUnderFlowCbParams</a> structure.</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="a20946243c0b2d8b3c5b317098abfba69"></a>
+<div class="memitem">
+<div class="memproto">
+<table class="mlabels">
+ <tr>
+ <td class="mlabels-left">
+ <table class="memname">
+ <tr>
+ <td class="memname">static void Dss_frameRtParamsInit </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="struct_dss___frame_rt_params.html">Dss_FrameRtParams</a> * </td>
+ <td class="paramname"><em>frameRtParams</em></td><td>)</td>
+ <td></td>
+ </tr>
+ </table>
+ </td>
+ <td class="mlabels-right">
+<span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span> </td>
+ </tr>
+</table>
+</div><div class="memdoc">
+
+<p><a class="el" href="struct_dss___frame_rt_params.html" title="Structure containing run time configuration per frame. ">Dss_FrameRtParams</a> structure init function. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">frameRtParams</td><td>[IN]Pointer to <a class="el" href="struct_dss___frame_rt_params.html" title="Structure containing run time configuration per frame. ">Dss_FrameRtParams</a> structure.</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="a9f3129c4857d08aec6387867cc2e778c"></a>
+<div class="memitem">
+<div class="memproto">
+<table class="mlabels">
+ <tr>
+ <td class="mlabels-left">
+ <table class="memname">
+ <tr>
+ <td class="memname">static void Dss_scRtParamsInit </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="struct_dss___sc_rt_params.html">Dss_ScRtParams</a> * </td>
+ <td class="paramname"><em>scRtParams</em></td><td>)</td>
+ <td></td>
+ </tr>
+ </table>
+ </td>
+ <td class="mlabels-right">
+<span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span> </td>
+ </tr>
+</table>
+</div><div class="memdoc">
+
+<p><a class="el" href="struct_dss___sc_rt_params.html" title="Structure containing run time scaler configuration. ">Dss_ScRtParams</a> structure init function. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">scRtParams</td><td>[IN]Pointer to <a class="el" href="struct_dss___sc_rt_params.html" title="Structure containing run time scaler configuration. ">Dss_ScRtParams</a> structure.</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None </dd></dl>
+
+</div>
+</div>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/dss__soc_8h.html b/packages/ti/drv/dss/docs/doxygen/html/dss__soc_8h.html
--- /dev/null
@@ -0,0 +1,421 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>dss_soc.h File Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li class="current"><a href="files.html"><span>Files</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow2" class="tabs2">
+ <ul class="tablist">
+ <li><a href="files.html"><span>File List</span></a></li>
+ <li><a href="globals.html"><span>Globals</span></a></li>
+ </ul>
+ </div>
+<div id="nav-path" class="navpath">
+ <ul>
+<li class="navelem"><a class="el" href="dir_2448ef93368455da4d6fef1a2979cd30.html">soc</a></li><li class="navelem"><a class="el" href="dir_e430b0b3b71064fbce69d7c00dd3cfd0.html">V0</a></li> </ul>
+</div>
+</div><!-- top -->
+<div class="header">
+ <div class="summary">
+<a href="#nested-classes">Data Structures</a> |
+<a href="#func-members">Functions</a> </div>
+ <div class="headertitle">
+<div class="title">dss_soc.h File Reference</div> </div>
+</div><!--header-->
+<div class="contents">
+
+<p>DSS Driver AM65xx SOC specific file.
+<a href="#details">More...</a></p>
+<table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="nested-classes"></a>
+Data Structures</h2></td></tr>
+<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___irq_params.html">Dss_IrqParams</a></td></tr>
+<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">Structure containing DSS interrupt information. Events should be enabled only for available Video Ports and Video Pipes. <a href="struct_dss___irq_params.html#details">More...</a><br/></td></tr>
+<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___rm_info.html">Dss_RmInfo</a></td></tr>
+<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">Structure containing resources manager information. This enables display sharing between two different softwares. <a href="struct_dss___rm_info.html#details">More...</a><br/></td></tr>
+<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___soc_params.html">Dss_SocParams</a></td></tr>
+<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">DSS SOC parameters. <a href="struct_dss___soc_params.html#details">More...</a><br/></td></tr>
+<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___dctrl_oldi_params.html">Dss_DctrlOldiParams</a></td></tr>
+<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">Structure containing OLDI configuration. This structure is used as an argument to IOCTL_DSS_DCTRL_SET_OLDI_PARAMS. <a href="struct_dss___dctrl_oldi_params.html#details">More...</a><br/></td></tr>
+<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
+Macros</h2></td></tr>
+<tr><td colspan="2"><div class="groupHeader">DSS DCTRL Instance IDs</div></td></tr>
+<tr class="memitem:a9f12541fdf035815233db52d23727911"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a9f12541fdf035815233db52d23727911"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="dss__soc_8h.html#a9f12541fdf035815233db52d23727911">DSS_DCTRL_INST_0</a>   (0U)</td></tr>
+<tr class="memdesc:a9f12541fdf035815233db52d23727911"><td class="mdescLeft"> </td><td class="mdescRight">Display controller instance 0. <br/></td></tr>
+<tr class="separator:a9f12541fdf035815233db52d23727911"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ac66ebc6e5c2f1a6c7f7dd129acb02ebd"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ac66ebc6e5c2f1a6c7f7dd129acb02ebd"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="dss__soc_8h.html#ac66ebc6e5c2f1a6c7f7dd129acb02ebd">DSS_DCTRL_INST_MAX</a>   (1U)</td></tr>
+<tr class="memdesc:ac66ebc6e5c2f1a6c7f7dd129acb02ebd"><td class="mdescLeft"> </td><td class="mdescRight">Maximum number of display driver instances. <br/></td></tr>
+<tr class="separator:ac66ebc6e5c2f1a6c7f7dd129acb02ebd"><td class="memSeparator" colspan="2"> </td></tr>
+<tr><td colspan="2"><div class="groupHeader">DSS Display Instance IDs</div></td></tr>
+<tr class="memitem:a9b73eea7de83a9a39a1f200ec4096e4d"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a9b73eea7de83a9a39a1f200ec4096e4d"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="dss__soc_8h.html#a9b73eea7de83a9a39a1f200ec4096e4d">DSS_DISP_INST_VID1</a>   (<a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gab861a5295a9cd21b01897e1026aa2b79">CSL_DSS_VID_PIPE_ID_VID1</a>)</td></tr>
+<tr class="memdesc:a9b73eea7de83a9a39a1f200ec4096e4d"><td class="mdescLeft"> </td><td class="mdescRight">Video 1 Pipeline display driver instance number. <br/></td></tr>
+<tr class="separator:a9b73eea7de83a9a39a1f200ec4096e4d"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ad56ec47be5d8455998b861548c38ceec"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ad56ec47be5d8455998b861548c38ceec"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="dss__soc_8h.html#ad56ec47be5d8455998b861548c38ceec">DSS_DISP_INST_VIDL1</a>   (<a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga73aee3bb97f91dafe4f9adfd0a0d3bac">CSL_DSS_VID_PIPE_ID_VIDL1</a>)</td></tr>
+<tr class="memdesc:ad56ec47be5d8455998b861548c38ceec"><td class="mdescLeft"> </td><td class="mdescRight">Video Lite 1 Pipeline display driver instance number. <br/></td></tr>
+<tr class="separator:ad56ec47be5d8455998b861548c38ceec"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a240f22c4499be957a1f78dc24d13d587"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a240f22c4499be957a1f78dc24d13d587"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="dss__soc_8h.html#a240f22c4499be957a1f78dc24d13d587">DSS_DISP_INST_MAX</a>   (<a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gafbbd94228f58df3124b2bc9780379cea">CSL_DSS_VID_PIPE_ID_MAX</a>)</td></tr>
+<tr class="memdesc:a240f22c4499be957a1f78dc24d13d587"><td class="mdescLeft"> </td><td class="mdescRight">Maximum number of display driver instances. <br/></td></tr>
+<tr class="separator:a240f22c4499be957a1f78dc24d13d587"><td class="memSeparator" colspan="2"> </td></tr>
+<tr><td colspan="2"><div class="groupHeader">DSS DCTRL Node Id</div></td></tr>
+<tr><td colspan="2"><div class="groupText"><p><a class="anchor" id="Dss_DctrlNodeId"></a></p>
+<p>Node ids that are used by the set config to connect different modules and create a graph </p>
+</div></td></tr>
+<tr class="memitem:addcf6826238296d5d0cf3f46fb668380"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="addcf6826238296d5d0cf3f46fb668380"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="dss__soc_8h.html#addcf6826238296d5d0cf3f46fb668380">DSS_DCTRL_NODE_INVALID</a>   ((uint32_t) 0x0U)</td></tr>
+<tr class="memdesc:addcf6826238296d5d0cf3f46fb668380"><td class="mdescLeft"> </td><td class="mdescRight">Defines maximum number of nodes for allocation including invalid node. <br/></td></tr>
+<tr class="separator:addcf6826238296d5d0cf3f46fb668380"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a1ca57513d77bd5f52e431690ec5b2b0f"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a1ca57513d77bd5f52e431690ec5b2b0f"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="dss__soc_8h.html#a1ca57513d77bd5f52e431690ec5b2b0f">DSS_DCTRL_NODE_VID1</a>   ((uint32_t) 0x1U)</td></tr>
+<tr class="memdesc:a1ca57513d77bd5f52e431690ec5b2b0f"><td class="mdescLeft"> </td><td class="mdescRight">Defines maximum number of nodes for allocation including invalid node. <br/></td></tr>
+<tr class="separator:a1ca57513d77bd5f52e431690ec5b2b0f"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a38e52fb43b4d2792d67953bf92641c8e"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a38e52fb43b4d2792d67953bf92641c8e"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="dss__soc_8h.html#a38e52fb43b4d2792d67953bf92641c8e">DSS_DCTRL_NODE_VIDL1</a>   ((uint32_t) 0x2U)</td></tr>
+<tr class="memdesc:a38e52fb43b4d2792d67953bf92641c8e"><td class="mdescLeft"> </td><td class="mdescRight">Defines maximum number of nodes for allocation including invalid node. <br/></td></tr>
+<tr class="separator:a38e52fb43b4d2792d67953bf92641c8e"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a6ac0743ded9082870f782c1deb9fee05"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a6ac0743ded9082870f782c1deb9fee05"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="dss__soc_8h.html#a6ac0743ded9082870f782c1deb9fee05">DSS_DCTRL_NODE_OVERLAY1</a>   ((uint32_t) 0x3U)</td></tr>
+<tr class="memdesc:a6ac0743ded9082870f782c1deb9fee05"><td class="mdescLeft"> </td><td class="mdescRight">Defines maximum number of nodes for allocation including invalid node. <br/></td></tr>
+<tr class="separator:a6ac0743ded9082870f782c1deb9fee05"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a99e2d8a40fd3ea1bd492dd227021761e"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a99e2d8a40fd3ea1bd492dd227021761e"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="dss__soc_8h.html#a99e2d8a40fd3ea1bd492dd227021761e">DSS_DCTRL_NODE_OVERLAY2</a>   ((uint32_t) 0x4U)</td></tr>
+<tr class="memdesc:a99e2d8a40fd3ea1bd492dd227021761e"><td class="mdescLeft"> </td><td class="mdescRight">Defines maximum number of nodes for allocation including invalid node. <br/></td></tr>
+<tr class="separator:a99e2d8a40fd3ea1bd492dd227021761e"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ab05e2fb7e5ae5efefc38b10735025bfd"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ab05e2fb7e5ae5efefc38b10735025bfd"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="dss__soc_8h.html#ab05e2fb7e5ae5efefc38b10735025bfd">DSS_DCTRL_NODE_VP1</a>   ((uint32_t) 0x5U)</td></tr>
+<tr class="memdesc:ab05e2fb7e5ae5efefc38b10735025bfd"><td class="mdescLeft"> </td><td class="mdescRight">Defines maximum number of nodes for allocation including invalid node. <br/></td></tr>
+<tr class="separator:ab05e2fb7e5ae5efefc38b10735025bfd"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:aba4b126180d74b834ff45412d2c98062"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aba4b126180d74b834ff45412d2c98062"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="dss__soc_8h.html#aba4b126180d74b834ff45412d2c98062">DSS_DCTRL_NODE_VP2</a>   ((uint32_t) 0x6U)</td></tr>
+<tr class="memdesc:aba4b126180d74b834ff45412d2c98062"><td class="mdescLeft"> </td><td class="mdescRight">Defines maximum number of nodes for allocation including invalid node. <br/></td></tr>
+<tr class="separator:aba4b126180d74b834ff45412d2c98062"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ae42fb0de4238cbff83100dd6af2777df"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ae42fb0de4238cbff83100dd6af2777df"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="dss__soc_8h.html#ae42fb0de4238cbff83100dd6af2777df">DSS_DCTRL_NODE_OLDI</a>   ((uint32_t) 0x7U)</td></tr>
+<tr class="memdesc:ae42fb0de4238cbff83100dd6af2777df"><td class="mdescLeft"> </td><td class="mdescRight">Defines maximum number of nodes for allocation including invalid node. <br/></td></tr>
+<tr class="separator:ae42fb0de4238cbff83100dd6af2777df"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:adcc5563c51855a3f4b8f1b53f8b26672"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="adcc5563c51855a3f4b8f1b53f8b26672"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="dss__soc_8h.html#adcc5563c51855a3f4b8f1b53f8b26672">DSS_DCTRL_NODE_DPI1</a>   ((uint32_t) 0x8U)</td></tr>
+<tr class="memdesc:adcc5563c51855a3f4b8f1b53f8b26672"><td class="mdescLeft"> </td><td class="mdescRight">Defines maximum number of nodes for allocation including invalid node. <br/></td></tr>
+<tr class="separator:adcc5563c51855a3f4b8f1b53f8b26672"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ad68744191253ed0e140808365e78d315"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ad68744191253ed0e140808365e78d315"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="dss__soc_8h.html#ad68744191253ed0e140808365e78d315">DSS_DCTRL_MAX_NODES</a>   ((uint32_t) 9U)</td></tr>
+<tr class="memdesc:ad68744191253ed0e140808365e78d315"><td class="mdescLeft"> </td><td class="mdescRight">Defines maximum number of nodes for allocation including invalid node. <br/></td></tr>
+<tr class="separator:ad68744191253ed0e140808365e78d315"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a8dbb4dd2e4cfdb12f6d01c6ddcd923e0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="dss__soc_8h.html#a8dbb4dd2e4cfdb12f6d01c6ddcd923e0">DSS_DCTRL_MAX_EDGES</a>   ((uint32_t) 8U)</td></tr>
+<tr class="memdesc:a8dbb4dd2e4cfdb12f6d01c6ddcd923e0"><td class="mdescLeft"> </td><td class="mdescRight">Defines maximum number of edges for allocation. This is derived by looking at all possible DSS connections in the SoC. <a href="#a8dbb4dd2e4cfdb12f6d01c6ddcd923e0">More...</a><br/></td></tr>
+<tr class="separator:a8dbb4dd2e4cfdb12f6d01c6ddcd923e0"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:aa7ac2fb77b879354f19126b346099294"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aa7ac2fb77b879354f19126b346099294"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="dss__soc_8h.html#aa7ac2fb77b879354f19126b346099294">DSS_FUNC_IRQ_DEFAULT_NUM</a>   (CSL_GIC0_INTR_DSS0_BUS_DISPC_INTR_REQ_0)</td></tr>
+<tr class="memdesc:aa7ac2fb77b879354f19126b346099294"><td class="mdescLeft"> </td><td class="mdescRight">Defines maximum number of nodes for allocation including invalid node. <br/></td></tr>
+<tr class="separator:aa7ac2fb77b879354f19126b346099294"><td class="memSeparator" colspan="2"> </td></tr>
+<tr><td colspan="2"><div class="groupHeader">Instance Ids for DSS Event Manager.</div></td></tr>
+<tr><td colspan="2"><div class="groupText"><p><a class="anchor" id="Dss_EvtMgrInstId"></a></p>
+</div></td></tr>
+<tr class="memitem:a2d58a192f10fab6608c8f1cde2489aa5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="dss__soc_8h.html#a2d58a192f10fab6608c8f1cde2489aa5">DSS_EVT_MGR_INST_ID_FUNC</a>   ((uint32_t) 0x00U)</td></tr>
+<tr class="memdesc:a2d58a192f10fab6608c8f1cde2489aa5"><td class="mdescLeft"> </td><td class="mdescRight">Instance Id for functional interrupts. <a href="#a2d58a192f10fab6608c8f1cde2489aa5">More...</a><br/></td></tr>
+<tr class="separator:a2d58a192f10fab6608c8f1cde2489aa5"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a655e39bd46b2a70609bd7d6c878f394f"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a655e39bd46b2a70609bd7d6c878f394f"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="dss__soc_8h.html#a655e39bd46b2a70609bd7d6c878f394f">DSS_EVT_MGR_INST_ID_MAX</a>   ((uint32_t) 0x01U)</td></tr>
+<tr class="memdesc:a655e39bd46b2a70609bd7d6c878f394f"><td class="mdescLeft"> </td><td class="mdescRight">Invalid Instance Id. <br/></td></tr>
+<tr class="separator:a655e39bd46b2a70609bd7d6c878f394f"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:aa6df7d5f82c9928bd28c3031bef4adbc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="dss__soc_8h.html#aa6df7d5f82c9928bd28c3031bef4adbc">DSS_EVT_MGR_INST_ID_INVALID</a>   ((uint32_t) 0xFFU)</td></tr>
+<tr class="memdesc:aa6df7d5f82c9928bd28c3031bef4adbc"><td class="mdescLeft"> </td><td class="mdescRight">Instance Id for functional interrupts. <a href="#aa6df7d5f82c9928bd28c3031bef4adbc">More...</a><br/></td></tr>
+<tr class="separator:aa6df7d5f82c9928bd28c3031bef4adbc"><td class="memSeparator" colspan="2"> </td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a>
+Functions</h2></td></tr>
+<tr class="memitem:ac5552efbddfba904ce91dbcd5d0bd455"><td class="memItemLeft" align="right" valign="top">static uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="dss__soc_8h.html#ac5552efbddfba904ce91dbcd5d0bd455">Dss_dispIsVidInst</a> (uint32_t instId)</td></tr>
+<tr class="memdesc:ac5552efbddfba904ce91dbcd5d0bd455"><td class="mdescLeft"> </td><td class="mdescRight">Check if the display driver instance is of type Video pipeline. <a href="#ac5552efbddfba904ce91dbcd5d0bd455">More...</a><br/></td></tr>
+<tr class="separator:ac5552efbddfba904ce91dbcd5d0bd455"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:afe01ba05886b4fec75e6bc8414cf2582"><td class="memItemLeft" align="right" valign="top">static uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="dss__soc_8h.html#afe01ba05886b4fec75e6bc8414cf2582">Dss_dispIsVidLInst</a> (uint32_t instId)</td></tr>
+<tr class="memdesc:afe01ba05886b4fec75e6bc8414cf2582"><td class="mdescLeft"> </td><td class="mdescRight">Check if the display driver instance is of type Video lite pipeline. <a href="#afe01ba05886b4fec75e6bc8414cf2582">More...</a><br/></td></tr>
+<tr class="separator:afe01ba05886b4fec75e6bc8414cf2582"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ae9111504fb718b4ac86e9a13ebf0b1d8"><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="dss__soc_8h.html#ae9111504fb718b4ac86e9a13ebf0b1d8">Dss_irqParamsInit</a> (<a class="el" href="struct_dss___irq_params.html">Dss_IrqParams</a> *irqParams)</td></tr>
+<tr class="memdesc:ae9111504fb718b4ac86e9a13ebf0b1d8"><td class="mdescLeft"> </td><td class="mdescRight"><a class="el" href="struct_dss___irq_params.html" title="Structure containing DSS interrupt information. Events should be enabled only for available Video Por...">Dss_IrqParams</a> structure init function. <a href="#ae9111504fb718b4ac86e9a13ebf0b1d8">More...</a><br/></td></tr>
+<tr class="separator:ae9111504fb718b4ac86e9a13ebf0b1d8"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a24089c231dd46a8856c109008a2ac5b4"><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="dss__soc_8h.html#a24089c231dd46a8856c109008a2ac5b4">Dss_rmInfoInit</a> (<a class="el" href="struct_dss___rm_info.html">Dss_RmInfo</a> *rmInfo)</td></tr>
+<tr class="memdesc:a24089c231dd46a8856c109008a2ac5b4"><td class="mdescLeft"> </td><td class="mdescRight"><a class="el" href="struct_dss___rm_info.html" title="Structure containing resources manager information. This enables display sharing between two differen...">Dss_RmInfo</a> structure init function. <a href="#a24089c231dd46a8856c109008a2ac5b4">More...</a><br/></td></tr>
+<tr class="separator:a24089c231dd46a8856c109008a2ac5b4"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ab0090cdbb416c7e5ebe089d50914b70a"><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="dss__soc_8h.html#ab0090cdbb416c7e5ebe089d50914b70a">Dss_socParamsInit</a> (<a class="el" href="struct_dss___soc_params.html">Dss_SocParams</a> *socParams)</td></tr>
+<tr class="memdesc:ab0090cdbb416c7e5ebe089d50914b70a"><td class="mdescLeft"> </td><td class="mdescRight"><a class="el" href="struct_dss___soc_params.html" title="DSS SOC parameters. ">Dss_SocParams</a> structure init function. <a href="#ab0090cdbb416c7e5ebe089d50914b70a">More...</a><br/></td></tr>
+<tr class="separator:ab0090cdbb416c7e5ebe089d50914b70a"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a6b12a5aecc6d9248f665d838abbad924"><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="dss__soc_8h.html#a6b12a5aecc6d9248f665d838abbad924">Dss_dctrlOldiParamsInit</a> (<a class="el" href="struct_dss___dctrl_oldi_params.html">Dss_DctrlOldiParams</a> *oldiParams)</td></tr>
+<tr class="memdesc:a6b12a5aecc6d9248f665d838abbad924"><td class="mdescLeft"> </td><td class="mdescRight"><a class="el" href="struct_dss___dctrl_oldi_params.html" title="Structure containing OLDI configuration. This structure is used as an argument to IOCTL_DSS_DCTRL_SET...">Dss_DctrlOldiParams</a> structure init function. <a href="#a6b12a5aecc6d9248f665d838abbad924">More...</a><br/></td></tr>
+<tr class="separator:a6b12a5aecc6d9248f665d838abbad924"><td class="memSeparator" colspan="2"> </td></tr>
+</table>
+<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
+<div class="textblock"><p>DSS Driver AM65xx SOC specific file. </p>
+</div><h2 class="groupheader">Macro Definition Documentation</h2>
+<a class="anchor" id="a8dbb4dd2e4cfdb12f6d01c6ddcd923e0"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">#define DSS_DCTRL_MAX_EDGES   ((uint32_t) 8U)</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+
+<p>Defines maximum number of edges for allocation. This is derived by looking at all possible DSS connections in the SoC. </p>
+<p>DSS Functional Interrupt Number for A53 </p>
+
+</div>
+</div>
+<a class="anchor" id="a2d58a192f10fab6608c8f1cde2489aa5"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">#define DSS_EVT_MGR_INST_ID_FUNC   ((uint32_t) 0x00U)</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+
+<p>Instance Id for functional interrupts. </p>
+<p><Max Instance Id </p>
+
+</div>
+</div>
+<a class="anchor" id="aa6df7d5f82c9928bd28c3031bef4adbc"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">#define DSS_EVT_MGR_INST_ID_INVALID   ((uint32_t) 0xFFU)</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+
+<p>Instance Id for functional interrupts. </p>
+<p><Max Instance Id </p>
+
+</div>
+</div>
+<h2 class="groupheader">Function Documentation</h2>
+<a class="anchor" id="a6b12a5aecc6d9248f665d838abbad924"></a>
+<div class="memitem">
+<div class="memproto">
+<table class="mlabels">
+ <tr>
+ <td class="mlabels-left">
+ <table class="memname">
+ <tr>
+ <td class="memname">static void Dss_dctrlOldiParamsInit </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="struct_dss___dctrl_oldi_params.html">Dss_DctrlOldiParams</a> * </td>
+ <td class="paramname"><em>oldiParams</em></td><td>)</td>
+ <td></td>
+ </tr>
+ </table>
+ </td>
+ <td class="mlabels-right">
+<span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span> </td>
+ </tr>
+</table>
+</div><div class="memdoc">
+
+<p><a class="el" href="struct_dss___dctrl_oldi_params.html" title="Structure containing OLDI configuration. This structure is used as an argument to IOCTL_DSS_DCTRL_SET...">Dss_DctrlOldiParams</a> structure init function. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">oldiParams</td><td>[IN]Pointer to <a class="el" href="struct_dss___dctrl_oldi_params.html" title="Structure containing OLDI configuration. This structure is used as an argument to IOCTL_DSS_DCTRL_SET...">Dss_DctrlOldiParams</a> structure.</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ac5552efbddfba904ce91dbcd5d0bd455"></a>
+<div class="memitem">
+<div class="memproto">
+<table class="mlabels">
+ <tr>
+ <td class="mlabels-left">
+ <table class="memname">
+ <tr>
+ <td class="memname">static uint32_t Dss_dispIsVidInst </td>
+ <td>(</td>
+ <td class="paramtype">uint32_t </td>
+ <td class="paramname"><em>instId</em></td><td>)</td>
+ <td></td>
+ </tr>
+ </table>
+ </td>
+ <td class="mlabels-right">
+<span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span> </td>
+ </tr>
+</table>
+</div><div class="memdoc">
+
+<p>Check if the display driver instance is of type Video pipeline. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">instId</td><td>[IN]Driver Instance Id.</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>TRUE if instance is Video pipeline else returns FALSE. </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="afe01ba05886b4fec75e6bc8414cf2582"></a>
+<div class="memitem">
+<div class="memproto">
+<table class="mlabels">
+ <tr>
+ <td class="mlabels-left">
+ <table class="memname">
+ <tr>
+ <td class="memname">static uint32_t Dss_dispIsVidLInst </td>
+ <td>(</td>
+ <td class="paramtype">uint32_t </td>
+ <td class="paramname"><em>instId</em></td><td>)</td>
+ <td></td>
+ </tr>
+ </table>
+ </td>
+ <td class="mlabels-right">
+<span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span> </td>
+ </tr>
+</table>
+</div><div class="memdoc">
+
+<p>Check if the display driver instance is of type Video lite pipeline. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">instId</td><td>[IN]Driver Instance Id.</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>TRUE if instance is Video lite pipeline else returns FALSE. </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ae9111504fb718b4ac86e9a13ebf0b1d8"></a>
+<div class="memitem">
+<div class="memproto">
+<table class="mlabels">
+ <tr>
+ <td class="mlabels-left">
+ <table class="memname">
+ <tr>
+ <td class="memname">static void Dss_irqParamsInit </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="struct_dss___irq_params.html">Dss_IrqParams</a> * </td>
+ <td class="paramname"><em>irqParams</em></td><td>)</td>
+ <td></td>
+ </tr>
+ </table>
+ </td>
+ <td class="mlabels-right">
+<span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span> </td>
+ </tr>
+</table>
+</div><div class="memdoc">
+
+<p><a class="el" href="struct_dss___irq_params.html" title="Structure containing DSS interrupt information. Events should be enabled only for available Video Por...">Dss_IrqParams</a> structure init function. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">irqParams</td><td>Pointer to <a class="el" href="struct_dss___irq_params.html" title="Structure containing DSS interrupt information. Events should be enabled only for available Video Por...">Dss_IrqParams</a> structure.</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="a24089c231dd46a8856c109008a2ac5b4"></a>
+<div class="memitem">
+<div class="memproto">
+<table class="mlabels">
+ <tr>
+ <td class="mlabels-left">
+ <table class="memname">
+ <tr>
+ <td class="memname">static void Dss_rmInfoInit </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="struct_dss___rm_info.html">Dss_RmInfo</a> * </td>
+ <td class="paramname"><em>rmInfo</em></td><td>)</td>
+ <td></td>
+ </tr>
+ </table>
+ </td>
+ <td class="mlabels-right">
+<span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span> </td>
+ </tr>
+</table>
+</div><div class="memdoc">
+
+<p><a class="el" href="struct_dss___rm_info.html" title="Structure containing resources manager information. This enables display sharing between two differen...">Dss_RmInfo</a> structure init function. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">rmInfo</td><td>Pointer to <a class="el" href="struct_dss___rm_info.html" title="Structure containing resources manager information. This enables display sharing between two differen...">Dss_RmInfo</a> structure.</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ab0090cdbb416c7e5ebe089d50914b70a"></a>
+<div class="memitem">
+<div class="memproto">
+<table class="mlabels">
+ <tr>
+ <td class="mlabels-left">
+ <table class="memname">
+ <tr>
+ <td class="memname">static void Dss_socParamsInit </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="struct_dss___soc_params.html">Dss_SocParams</a> * </td>
+ <td class="paramname"><em>socParams</em></td><td>)</td>
+ <td></td>
+ </tr>
+ </table>
+ </td>
+ <td class="mlabels-right">
+<span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span> </td>
+ </tr>
+</table>
+</div><div class="memdoc">
+
+<p><a class="el" href="struct_dss___soc_params.html" title="DSS SOC parameters. ">Dss_SocParams</a> structure init function. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">socParams</td><td>Pointer to <a class="el" href="struct_dss___soc_params.html" title="DSS SOC parameters. ">Dss_SocParams</a> structure.</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None </dd></dl>
+
+</div>
+</div>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/dynsections.js b/packages/ti/drv/dss/docs/doxygen/html/dynsections.js
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+ content.hide();
+ summary.show();
+ $(linkObj).addClass('closed').removeClass('opened');
+ $(trigger).attr('src',src.substring(0,src.length-8)+'closed.png');
+ } else {
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+ summary.hide();
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+ return false;
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+ $('table.directory tr').
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+ rows.filter("[id^=row_"+id+"]").hide();
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+ //All sub images
+ var childImages = childRows.find("img");
+ var childImg = childImages.filter("[id^=img]");
+ var childArr = childImages.filter("[id^=arr]");
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+ rows.css('display','none');
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+ } else {
+ rows.css('display','table-row'); // using show() causes jump in firefox
+ $(img).attr('src',src.substring(0,src.length-10)+'open.png');
+ }
+}
+
diff --git a/packages/ti/drv/dss/docs/doxygen/html/files.html b/packages/ti/drv/dss/docs/doxygen/html/files.html
--- /dev/null
@@ -0,0 +1,55 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>File List</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li class="current"><a href="files.html"><span>Files</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow2" class="tabs2">
+ <ul class="tablist">
+ <li class="current"><a href="files.html"><span>File List</span></a></li>
+ <li><a href="globals.html"><span>Globals</span></a></li>
+ </ul>
+ </div>
+</div><!-- top -->
+<div class="header">
+ <div class="headertitle">
+<div class="title">File List</div> </div>
+</div><!--header-->
+<div class="contents">
+<div class="textblock">Here is a list of all documented files with brief descriptions:</div><div class="directory">
+<table class="directory">
+<tr id="row_0_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2doc.png" alt="*" width="24" height="22" /><a class="el" href="csl__dss_8h.html" target="_self">csl_dss.h</a></td><td class="desc"><h1>This file contains the CSL-FL API's for DSS </h1>
+</td></tr>
+<tr id="row_1_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2doc.png" alt="*" width="24" height="22" /><a class="el" href="csl__dss_common_8h.html" target="_self">csl_dssCommon.h</a></td><td class="desc">DSS Common CSL FL interface file </td></tr>
+<tr id="row_2_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2doc.png" alt="*" width="24" height="22" /><a class="el" href="csl__dss_overlay_8h.html" target="_self">csl_dssOverlay.h</a></td><td class="desc">DSS Overlay CSL FL interface file </td></tr>
+<tr id="row_3_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2doc.png" alt="*" width="24" height="22" /><a class="el" href="csl__dss_top_8h.html" target="_self">csl_dssTop.h</a></td><td class="desc">DSS Top CSL FL interface file </td></tr>
+<tr id="row_4_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2doc.png" alt="*" width="24" height="22" /><a class="el" href="csl__dss_video_pipe_8h.html" target="_self">csl_dssVideoPipe.h</a></td><td class="desc">DSS Video Pipe CSL FL interface file </td></tr>
+<tr id="row_5_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2doc.png" alt="*" width="24" height="22" /><a class="el" href="csl__dss_video_port_8h.html" target="_self">csl_dssVideoPort.h</a></td><td class="desc">DSS Video Port CSL FL interface file </td></tr>
+<tr id="row_6_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2doc.png" alt="*" width="24" height="22" /><a class="el" href="csl__fvid2__data_types_8h.html" target="_self">csl_fvid2_dataTypes.h</a></td><td class="desc">CSL FVID2 Datatypes </td></tr>
+<tr id="row_7_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2doc.png" alt="*" width="24" height="22" /><a class="el" href="dss_8h.html" target="_self">dss.h</a></td><td class="desc">DSS Driver API/interface file </td></tr>
+<tr id="row_8_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2doc.png" alt="*" width="24" height="22" /><a class="el" href="dss__cfg_8h.html" target="_self">dss_cfg.h</a></td><td class="desc">DSS Driver configuration file </td></tr>
+<tr id="row_9_"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2doc.png" alt="*" width="24" height="22" /><a class="el" href="dss__dctrl_8h.html" target="_self">dss_dctrl.h</a></td><td class="desc">DSS Controller Driver API/interface file </td></tr>
+<tr id="row_10_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><img src="ftv2doc.png" alt="*" width="24" height="22" /><a class="el" href="dss__disp_8h.html" target="_self">dss_disp.h</a></td><td class="desc">DSS Display Driver interface file </td></tr>
+<tr id="row_11_"><td class="entry"><img src="ftv2lastnode.png" alt="\" width="16" height="22" /><img src="ftv2doc.png" alt="*" width="24" height="22" /><a class="el" href="dss__soc_8h.html" target="_self">dss_soc.h</a></td><td class="desc">DSS Driver AM65xx SOC specific file </td></tr>
+</table>
+</div><!-- directory -->
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
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diff --git a/packages/ti/drv/dss/docs/doxygen/html/functions.html b/packages/ti/drv/dss/docs/doxygen/html/functions.html
--- /dev/null
@@ -0,0 +1,93 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li class="current"><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="files.html"><span>Files</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow2" class="tabs2">
+ <ul class="tablist">
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li class="current"><a href="functions.html"><span>Data Fields</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow3" class="tabs2">
+ <ul class="tablist">
+ <li class="current"><a href="functions.html"><span>All</span></a></li>
+ <li><a href="functions_vars.html"><span>Variables</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow4" class="tabs3">
+ <ul class="tablist">
+ <li class="current"><a href="functions.html#index_a"><span>a</span></a></li>
+ <li><a href="functions_b.html#index_b"><span>b</span></a></li>
+ <li><a href="functions_c.html#index_c"><span>c</span></a></li>
+ <li><a href="functions_d.html#index_d"><span>d</span></a></li>
+ <li><a href="functions_e.html#index_e"><span>e</span></a></li>
+ <li><a href="functions_f.html#index_f"><span>f</span></a></li>
+ <li><a href="functions_g.html#index_g"><span>g</span></a></li>
+ <li><a href="functions_h.html#index_h"><span>h</span></a></li>
+ <li><a href="functions_i.html#index_i"><span>i</span></a></li>
+ <li><a href="functions_l.html#index_l"><span>l</span></a></li>
+ <li><a href="functions_m.html#index_m"><span>m</span></a></li>
+ <li><a href="functions_n.html#index_n"><span>n</span></a></li>
+ <li><a href="functions_o.html#index_o"><span>o</span></a></li>
+ <li><a href="functions_p.html#index_p"><span>p</span></a></li>
+ <li><a href="functions_q.html#index_q"><span>q</span></a></li>
+ <li><a href="functions_r.html#index_r"><span>r</span></a></li>
+ <li><a href="functions_s.html#index_s"><span>s</span></a></li>
+ <li><a href="functions_t.html#index_t"><span>t</span></a></li>
+ <li><a href="functions_u.html#index_u"><span>u</span></a></li>
+ <li><a href="functions_v.html#index_v"><span>v</span></a></li>
+ <li><a href="functions_w.html#index_w"><span>w</span></a></li>
+ <li><a href="functions_y.html#index_y"><span>y</span></a></li>
+ </ul>
+ </div>
+</div><!-- top -->
+<div class="contents">
+<div class="textblock">Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:</div>
+
+<h3><a class="anchor" id="index_a"></a>- a -</h3><ul>
+<li>acB
+: <a class="el" href="struct_c_s_l___dss_vp_lcd_adv_signal_cfg.html#acff326382d610c9f1680dae1e897d1c2">CSL_DssVpLcdAdvSignalCfg</a>
+</li>
+<li>acBI
+: <a class="el" href="struct_c_s_l___dss_vp_lcd_adv_signal_cfg.html#a19de0b442f322232367aeb005332693a">CSL_DssVpLcdAdvSignalCfg</a>
+</li>
+<li>actVidPolarity
+: <a class="el" href="struct_c_s_l___dss_vp_lcd_signal_polarity_cfg.html#aba814560abdf027968da571705fe6873">CSL_DssVpLcdSignalPolarityCfg</a>
+</li>
+<li>addr
+: <a class="el" href="struct_fvid2___frame.html#ad9e33643cd628e7432da408ad6565305">Fvid2_Frame</a>
+</li>
+<li>alphaCfg
+: <a class="el" href="struct_dss___disp_params.html#a3a34d97aedf973f3eeaca5d9469667ca">Dss_DispParams</a>
+</li>
+<li>appData
+: <a class="el" href="struct_dss___dctrl_sync_lost_cb_params.html#a018ed0ef2544b8f52207dc5799238854">Dss_DctrlSyncLostCbParams</a>
+, <a class="el" href="struct_fvid2___frame.html#a071f9e8c68e831b029a17a342da7bce8">Fvid2_Frame</a>
+, <a class="el" href="struct_fvid2___frame_list.html#a3d40464eb4d1129eae2c8a95d65a5ec5">Fvid2_FrameList</a>
+</li>
+<li>arbitration
+: <a class="el" href="struct_c_s_l___dss_vid_pipe_dma_cfg.html#ae13f5377c727660f54f27d1061a4020b">CSL_DssVidPipeDmaCfg</a>
+</li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/functions_b.html b/packages/ti/drv/dss/docs/doxygen/html/functions_b.html
--- /dev/null
@@ -0,0 +1,103 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li class="current"><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="files.html"><span>Files</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow2" class="tabs2">
+ <ul class="tablist">
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li class="current"><a href="functions.html"><span>Data Fields</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow3" class="tabs2">
+ <ul class="tablist">
+ <li class="current"><a href="functions.html"><span>All</span></a></li>
+ <li><a href="functions_vars.html"><span>Variables</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow4" class="tabs3">
+ <ul class="tablist">
+ <li><a href="functions.html#index_a"><span>a</span></a></li>
+ <li class="current"><a href="functions_b.html#index_b"><span>b</span></a></li>
+ <li><a href="functions_c.html#index_c"><span>c</span></a></li>
+ <li><a href="functions_d.html#index_d"><span>d</span></a></li>
+ <li><a href="functions_e.html#index_e"><span>e</span></a></li>
+ <li><a href="functions_f.html#index_f"><span>f</span></a></li>
+ <li><a href="functions_g.html#index_g"><span>g</span></a></li>
+ <li><a href="functions_h.html#index_h"><span>h</span></a></li>
+ <li><a href="functions_i.html#index_i"><span>i</span></a></li>
+ <li><a href="functions_l.html#index_l"><span>l</span></a></li>
+ <li><a href="functions_m.html#index_m"><span>m</span></a></li>
+ <li><a href="functions_n.html#index_n"><span>n</span></a></li>
+ <li><a href="functions_o.html#index_o"><span>o</span></a></li>
+ <li><a href="functions_p.html#index_p"><span>p</span></a></li>
+ <li><a href="functions_q.html#index_q"><span>q</span></a></li>
+ <li><a href="functions_r.html#index_r"><span>r</span></a></li>
+ <li><a href="functions_s.html#index_s"><span>s</span></a></li>
+ <li><a href="functions_t.html#index_t"><span>t</span></a></li>
+ <li><a href="functions_u.html#index_u"><span>u</span></a></li>
+ <li><a href="functions_v.html#index_v"><span>v</span></a></li>
+ <li><a href="functions_w.html#index_w"><span>w</span></a></li>
+ <li><a href="functions_y.html#index_y"><span>y</span></a></li>
+ </ul>
+ </div>
+</div><!-- top -->
+<div class="contents">
+<div class="textblock">Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:</div>
+
+<h3><a class="anchor" id="index_b"></a>- b -</h3><ul>
+<li>backGroundColor
+: <a class="el" href="struct_c_s_l___dss_overlay_cfg.html#a6cd0a80d721ebd8316233c7d1a0eff8a">CSL_DssOverlayCfg</a>
+</li>
+<li>bitAlignPixel1Cycle0
+: <a class="el" href="struct_c_s_l___dss_vp_lcd_tdm_cfg.html#abab9fab501255acd87c1ab71e02df53a">CSL_DssVpLcdTdmCfg</a>
+</li>
+<li>bitAlignPixel1Cycle1
+: <a class="el" href="struct_c_s_l___dss_vp_lcd_tdm_cfg.html#a62a5d33c4b5cdaf4a1837a9062319b8d">CSL_DssVpLcdTdmCfg</a>
+</li>
+<li>bitAlignPixel1Cycle2
+: <a class="el" href="struct_c_s_l___dss_vp_lcd_tdm_cfg.html#a1fa26016fc933f54738aebc327fa8cac">CSL_DssVpLcdTdmCfg</a>
+</li>
+<li>bitAlignPixel2Cycle0
+: <a class="el" href="struct_c_s_l___dss_vp_lcd_tdm_cfg.html#aa23d4e0d384e3af3988eab00332b626f">CSL_DssVpLcdTdmCfg</a>
+</li>
+<li>bitAlignPixel2Cycle1
+: <a class="el" href="struct_c_s_l___dss_vp_lcd_tdm_cfg.html#a14eac5468c7e383536d68992ccbdbf69">CSL_DssVpLcdTdmCfg</a>
+</li>
+<li>bitAlignPixel2Cycle2
+: <a class="el" href="struct_c_s_l___dss_vp_lcd_tdm_cfg.html#ada6dacedb1a801fe5f91396b7252a719">CSL_DssVpLcdTdmCfg</a>
+</li>
+<li>bufHighThreshold
+: <a class="el" href="struct_c_s_l___dss_vid_pipe_dma_cfg.html#ac65a5085dbe2dd974d91cca54b9bfca7">CSL_DssVidPipeDmaCfg</a>
+</li>
+<li>bufLowThreshold
+: <a class="el" href="struct_c_s_l___dss_vid_pipe_dma_cfg.html#ab6f24c128746dac326d90a96a87bb220">CSL_DssVidPipeDmaCfg</a>
+</li>
+<li>bufPreloadControl
+: <a class="el" href="struct_c_s_l___dss_vid_pipe_dma_cfg.html#af7f5f21d2d1b24e927fcdb3e8f05c945">CSL_DssVidPipeDmaCfg</a>
+</li>
+<li>bufPrgmCbFxn
+: <a class="el" href="struct_dss___disp_buf_prgm_cb_params.html#a44001b7a082865cef75594b3cb8853b6">Dss_DispBufPrgmCbParams</a>
+</li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/functions_c.html b/packages/ti/drv/dss/docs/doxygen/html/functions_c.html
--- /dev/null
@@ -0,0 +1,142 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li class="current"><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="files.html"><span>Files</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow2" class="tabs2">
+ <ul class="tablist">
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li class="current"><a href="functions.html"><span>Data Fields</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow3" class="tabs2">
+ <ul class="tablist">
+ <li class="current"><a href="functions.html"><span>All</span></a></li>
+ <li><a href="functions_vars.html"><span>Variables</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow4" class="tabs3">
+ <ul class="tablist">
+ <li><a href="functions.html#index_a"><span>a</span></a></li>
+ <li><a href="functions_b.html#index_b"><span>b</span></a></li>
+ <li class="current"><a href="functions_c.html#index_c"><span>c</span></a></li>
+ <li><a href="functions_d.html#index_d"><span>d</span></a></li>
+ <li><a href="functions_e.html#index_e"><span>e</span></a></li>
+ <li><a href="functions_f.html#index_f"><span>f</span></a></li>
+ <li><a href="functions_g.html#index_g"><span>g</span></a></li>
+ <li><a href="functions_h.html#index_h"><span>h</span></a></li>
+ <li><a href="functions_i.html#index_i"><span>i</span></a></li>
+ <li><a href="functions_l.html#index_l"><span>l</span></a></li>
+ <li><a href="functions_m.html#index_m"><span>m</span></a></li>
+ <li><a href="functions_n.html#index_n"><span>n</span></a></li>
+ <li><a href="functions_o.html#index_o"><span>o</span></a></li>
+ <li><a href="functions_p.html#index_p"><span>p</span></a></li>
+ <li><a href="functions_q.html#index_q"><span>q</span></a></li>
+ <li><a href="functions_r.html#index_r"><span>r</span></a></li>
+ <li><a href="functions_s.html#index_s"><span>s</span></a></li>
+ <li><a href="functions_t.html#index_t"><span>t</span></a></li>
+ <li><a href="functions_u.html#index_u"><span>u</span></a></li>
+ <li><a href="functions_v.html#index_v"><span>v</span></a></li>
+ <li><a href="functions_w.html#index_w"><span>w</span></a></li>
+ <li><a href="functions_y.html#index_y"><span>y</span></a></li>
+ </ul>
+ </div>
+</div><!-- top -->
+<div class="contents">
+<div class="textblock">Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:</div>
+
+<h3><a class="anchor" id="index_c"></a>- c -</h3><ul>
+<li>c00
+: <a class="el" href="struct_c_s_l___dss_csc_coeff.html#ac7b7297b4e02573287df1f9f35d8aca2">CSL_DssCscCoeff</a>
+</li>
+<li>c01
+: <a class="el" href="struct_c_s_l___dss_csc_coeff.html#a5a75499dfeeb44b76d415bb9bbe98d8d">CSL_DssCscCoeff</a>
+</li>
+<li>c02
+: <a class="el" href="struct_c_s_l___dss_csc_coeff.html#a19b693b93d0cf75adb2fb68117695d8a">CSL_DssCscCoeff</a>
+</li>
+<li>c10
+: <a class="el" href="struct_c_s_l___dss_csc_coeff.html#aa669cc1212525291737f9bc74d0153ce">CSL_DssCscCoeff</a>
+</li>
+<li>c11
+: <a class="el" href="struct_c_s_l___dss_csc_coeff.html#a83ecbca550770735501789f7afcdf58e">CSL_DssCscCoeff</a>
+</li>
+<li>c12
+: <a class="el" href="struct_c_s_l___dss_csc_coeff.html#a8e8879c108c96cfb3ddaddc04920e09e">CSL_DssCscCoeff</a>
+</li>
+<li>c20
+: <a class="el" href="struct_c_s_l___dss_csc_coeff.html#ae191fedd2933af25a14134968c36cc4e">CSL_DssCscCoeff</a>
+</li>
+<li>c21
+: <a class="el" href="struct_c_s_l___dss_csc_coeff.html#a254195b0c504a070d1f3965b252a11f3">CSL_DssCscCoeff</a>
+</li>
+<li>c22
+: <a class="el" href="struct_c_s_l___dss_csc_coeff.html#ab4f1a6d7535f7b7c3cd9318a8d4147a4">CSL_DssCscCoeff</a>
+</li>
+<li>cbaCfg
+: <a class="el" href="struct_dss___dctrl_global_dss_params.html#a28fb2f34eb97b5d4d8980bcbb6135f8c">Dss_DctrlGlobalDssParams</a>
+</li>
+<li>ccsFormat
+: <a class="el" href="struct_fvid2___format.html#aff43b4f3b6ebdc15e84c1a0c4e55fd14">Fvid2_Format</a>
+</li>
+<li>chNum
+: <a class="el" href="struct_fvid2___format.html#a1f5ea464b31c5f7e77323e8f82c4d5e8">Fvid2_Format</a>
+, <a class="el" href="struct_fvid2___frame.html#a550ee00873923f1cc53905dfa0911918">Fvid2_Frame</a>
+</li>
+<li>clutdata
+: <a class="el" href="struct_c_s_l___dss_vid_pipe_cfg.html#a7ce9ca51a30b95aa4542c412a06f3fe8">CSL_DssVidPipeCfg</a>
+</li>
+<li>colorbarEnable
+: <a class="el" href="struct_dss___dctrl_overlay_params.html#afad2eae0981ea3cbf8438264247c01b1">Dss_DctrlOverlayParams</a>
+</li>
+<li>colorKeyEnable
+: <a class="el" href="struct_c_s_l___dss_overlay_cfg.html#aaeb04d69fcf39faa7ac2e8dff0dd57be">CSL_DssOverlayCfg</a>
+</li>
+<li>colorKeySel
+: <a class="el" href="struct_c_s_l___dss_overlay_cfg.html#a04994324fc3e3290d5a2384b1643abc4">CSL_DssOverlayCfg</a>
+</li>
+<li>cropHeight
+: <a class="el" href="struct_fvid2___crop_config.html#a81496ac240b08840f12474d0c53958cd">Fvid2_CropConfig</a>
+</li>
+<li>cropStartX
+: <a class="el" href="struct_fvid2___crop_config.html#a0312b61252f23269919008c8c2a15450">Fvid2_CropConfig</a>
+</li>
+<li>cropStartY
+: <a class="el" href="struct_fvid2___crop_config.html#a35cc1e45b5914ed02374fc1b0400b740">Fvid2_CropConfig</a>
+</li>
+<li>cropWidth
+: <a class="el" href="struct_fvid2___crop_config.html#a45cf01dd1c4d0f9e069432d3ea467c03">Fvid2_CropConfig</a>
+</li>
+<li>cscCoeff
+: <a class="el" href="struct_dss___dctrl_vp_csc_coeff.html#ae178eec62d495ae8ec2e0e5cc5e70e65">Dss_DctrlVpCscCoeff</a>
+</li>
+<li>cscPos
+: <a class="el" href="struct_dss___dctrl_vp_csc_coeff.html#ae353e0bd890dee8e7a8eeddf408ffc64">Dss_DctrlVpCscCoeff</a>
+</li>
+<li>cscRange
+: <a class="el" href="struct_c_s_l___dss_csc_coeff.html#aaa6a45f2e780f4d62f57fd3c5e3b73ee">CSL_DssCscCoeff</a>
+, <a class="el" href="struct_c_s_l___dss_vid_pipe_cfg.html#a69fdfed089bd4ee2daea72c8e40a98f2">CSL_DssVidPipeCfg</a>
+, <a class="el" href="struct_c_s_l___dss_vp_lcd_op_timing_cfg.html#a1e927fefea2d081753712d11f440731d">CSL_DssVpLcdOpTimingCfg</a>
+</li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/functions_d.html b/packages/ti/drv/dss/docs/doxygen/html/functions_d.html
--- /dev/null
@@ -0,0 +1,103 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li class="current"><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="files.html"><span>Files</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow2" class="tabs2">
+ <ul class="tablist">
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li class="current"><a href="functions.html"><span>Data Fields</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow3" class="tabs2">
+ <ul class="tablist">
+ <li class="current"><a href="functions.html"><span>All</span></a></li>
+ <li><a href="functions_vars.html"><span>Variables</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow4" class="tabs3">
+ <ul class="tablist">
+ <li><a href="functions.html#index_a"><span>a</span></a></li>
+ <li><a href="functions_b.html#index_b"><span>b</span></a></li>
+ <li><a href="functions_c.html#index_c"><span>c</span></a></li>
+ <li class="current"><a href="functions_d.html#index_d"><span>d</span></a></li>
+ <li><a href="functions_e.html#index_e"><span>e</span></a></li>
+ <li><a href="functions_f.html#index_f"><span>f</span></a></li>
+ <li><a href="functions_g.html#index_g"><span>g</span></a></li>
+ <li><a href="functions_h.html#index_h"><span>h</span></a></li>
+ <li><a href="functions_i.html#index_i"><span>i</span></a></li>
+ <li><a href="functions_l.html#index_l"><span>l</span></a></li>
+ <li><a href="functions_m.html#index_m"><span>m</span></a></li>
+ <li><a href="functions_n.html#index_n"><span>n</span></a></li>
+ <li><a href="functions_o.html#index_o"><span>o</span></a></li>
+ <li><a href="functions_p.html#index_p"><span>p</span></a></li>
+ <li><a href="functions_q.html#index_q"><span>q</span></a></li>
+ <li><a href="functions_r.html#index_r"><span>r</span></a></li>
+ <li><a href="functions_s.html#index_s"><span>s</span></a></li>
+ <li><a href="functions_t.html#index_t"><span>t</span></a></li>
+ <li><a href="functions_u.html#index_u"><span>u</span></a></li>
+ <li><a href="functions_v.html#index_v"><span>v</span></a></li>
+ <li><a href="functions_w.html#index_w"><span>w</span></a></li>
+ <li><a href="functions_y.html#index_y"><span>y</span></a></li>
+ </ul>
+ </div>
+</div><!-- top -->
+<div class="contents">
+<div class="textblock">Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:</div>
+
+<h3><a class="anchor" id="index_d"></a>- d -</h3><ul>
+<li>dataFormat
+: <a class="el" href="struct_dss___frame_rt_params.html#ae6280dd0f1eabe05ba89d7f81d9c2975">Dss_FrameRtParams</a>
+, <a class="el" href="struct_fvid2___format.html#abb9f60d4fcdab6fbfda7a2c92cbfce53">Fvid2_Format</a>
+</li>
+<li>deltaLinesPerPanel
+: <a class="el" href="struct_c_s_l___dss_vp_lcd_op_timing_cfg.html#a4d8eec6b33ff2de5a769235aee2a2acb">CSL_DssVpLcdOpTimingCfg</a>
+</li>
+<li>dequeueCount
+: <a class="el" href="struct_dss___disp_current_status.html#ab165778deecd58c934909dcf35571b03">Dss_DispCurrentStatus</a>
+</li>
+<li>dispFrmCount
+: <a class="el" href="struct_dss___disp_current_status.html#ad530ba229be8e4fab5d0dcdfcfdffc75">Dss_DispCurrentStatus</a>
+</li>
+<li>dispHeight
+: <a class="el" href="struct_dss___disp_create_status.html#a077cf565fe573dff029d69cf3d7e9bea">Dss_DispCreateStatus</a>
+</li>
+<li>dispWidth
+: <a class="el" href="struct_dss___disp_create_status.html#aee56647a1d80812a6b4e6ceb62bcf568">Dss_DispCreateStatus</a>
+</li>
+<li>dmaCfg
+: <a class="el" href="struct_dss___disp_params.html#a80d78d43a05b928cf2b6bd7c009f4ae6">Dss_DispParams</a>
+</li>
+<li>drvData
+: <a class="el" href="struct_fvid2___frame.html#a5e23564dddc24970d5a08ec7f91ac387">Fvid2_Frame</a>
+, <a class="el" href="struct_fvid2___frame_list.html#ae92f871d92e87591634aa6fbf2db7a9c">Fvid2_FrameList</a>
+</li>
+<li>dssCommonRegionId
+: <a class="el" href="struct_dss___irq_params.html#ad0b38c26a215ee1ef19d7a7dd31fdc59">Dss_IrqParams</a>
+</li>
+<li>dvoFormat
+: <a class="el" href="struct_c_s_l___dss_vp_lcd_op_timing_cfg.html#aaeadccfcb9ea48ce2989afa051909b2e">CSL_DssVpLcdOpTimingCfg</a>
+, <a class="el" href="struct_dss___dctrl_lcd_blank_timing_params.html#a7d98e8797f58bb69e6a0f639e749bb97">Dss_DctrlLcdBlankTimingParams</a>
+</li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/functions_e.html b/packages/ti/drv/dss/docs/doxygen/html/functions_e.html
--- /dev/null
@@ -0,0 +1,73 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li class="current"><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="files.html"><span>Files</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow2" class="tabs2">
+ <ul class="tablist">
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li class="current"><a href="functions.html"><span>Data Fields</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow3" class="tabs2">
+ <ul class="tablist">
+ <li class="current"><a href="functions.html"><span>All</span></a></li>
+ <li><a href="functions_vars.html"><span>Variables</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow4" class="tabs3">
+ <ul class="tablist">
+ <li><a href="functions.html#index_a"><span>a</span></a></li>
+ <li><a href="functions_b.html#index_b"><span>b</span></a></li>
+ <li><a href="functions_c.html#index_c"><span>c</span></a></li>
+ <li><a href="functions_d.html#index_d"><span>d</span></a></li>
+ <li class="current"><a href="functions_e.html#index_e"><span>e</span></a></li>
+ <li><a href="functions_f.html#index_f"><span>f</span></a></li>
+ <li><a href="functions_g.html#index_g"><span>g</span></a></li>
+ <li><a href="functions_h.html#index_h"><span>h</span></a></li>
+ <li><a href="functions_i.html#index_i"><span>i</span></a></li>
+ <li><a href="functions_l.html#index_l"><span>l</span></a></li>
+ <li><a href="functions_m.html#index_m"><span>m</span></a></li>
+ <li><a href="functions_n.html#index_n"><span>n</span></a></li>
+ <li><a href="functions_o.html#index_o"><span>o</span></a></li>
+ <li><a href="functions_p.html#index_p"><span>p</span></a></li>
+ <li><a href="functions_q.html#index_q"><span>q</span></a></li>
+ <li><a href="functions_r.html#index_r"><span>r</span></a></li>
+ <li><a href="functions_s.html#index_s"><span>s</span></a></li>
+ <li><a href="functions_t.html#index_t"><span>t</span></a></li>
+ <li><a href="functions_u.html#index_u"><span>u</span></a></li>
+ <li><a href="functions_v.html#index_v"><span>v</span></a></li>
+ <li><a href="functions_w.html#index_w"><span>w</span></a></li>
+ <li><a href="functions_y.html#index_y"><span>y</span></a></li>
+ </ul>
+ </div>
+</div><!-- top -->
+<div class="contents">
+<div class="textblock">Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:</div>
+
+<h3><a class="anchor" id="index_e"></a>- e -</h3><ul>
+<li>edgeInfo
+: <a class="el" href="struct_dss___dctrl_path_info.html#a8f2ebc06f24bf439b9b82bed9c70b8fd">Dss_DctrlPathInfo</a>
+</li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/functions_f.html b/packages/ti/drv/dss/docs/doxygen/html/functions_f.html
--- /dev/null
@@ -0,0 +1,91 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li class="current"><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="files.html"><span>Files</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow2" class="tabs2">
+ <ul class="tablist">
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li class="current"><a href="functions.html"><span>Data Fields</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow3" class="tabs2">
+ <ul class="tablist">
+ <li class="current"><a href="functions.html"><span>All</span></a></li>
+ <li><a href="functions_vars.html"><span>Variables</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow4" class="tabs3">
+ <ul class="tablist">
+ <li><a href="functions.html#index_a"><span>a</span></a></li>
+ <li><a href="functions_b.html#index_b"><span>b</span></a></li>
+ <li><a href="functions_c.html#index_c"><span>c</span></a></li>
+ <li><a href="functions_d.html#index_d"><span>d</span></a></li>
+ <li><a href="functions_e.html#index_e"><span>e</span></a></li>
+ <li class="current"><a href="functions_f.html#index_f"><span>f</span></a></li>
+ <li><a href="functions_g.html#index_g"><span>g</span></a></li>
+ <li><a href="functions_h.html#index_h"><span>h</span></a></li>
+ <li><a href="functions_i.html#index_i"><span>i</span></a></li>
+ <li><a href="functions_l.html#index_l"><span>l</span></a></li>
+ <li><a href="functions_m.html#index_m"><span>m</span></a></li>
+ <li><a href="functions_n.html#index_n"><span>n</span></a></li>
+ <li><a href="functions_o.html#index_o"><span>o</span></a></li>
+ <li><a href="functions_p.html#index_p"><span>p</span></a></li>
+ <li><a href="functions_q.html#index_q"><span>q</span></a></li>
+ <li><a href="functions_r.html#index_r"><span>r</span></a></li>
+ <li><a href="functions_s.html#index_s"><span>s</span></a></li>
+ <li><a href="functions_t.html#index_t"><span>t</span></a></li>
+ <li><a href="functions_u.html#index_u"><span>u</span></a></li>
+ <li><a href="functions_v.html#index_v"><span>v</span></a></li>
+ <li><a href="functions_w.html#index_w"><span>w</span></a></li>
+ <li><a href="functions_y.html#index_y"><span>y</span></a></li>
+ </ul>
+ </div>
+</div><!-- top -->
+<div class="contents">
+<div class="textblock">Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:</div>
+
+<h3><a class="anchor" id="index_f"></a>- f -</h3><ul>
+<li>fid
+: <a class="el" href="struct_fvid2___frame.html#a953491d1babc17d72cb892ae22b0b2a0">Fvid2_Frame</a>
+</li>
+<li>fidFirst
+: <a class="el" href="struct_c_s_l___dss_vp_lcd_op_timing_cfg.html#a5348fe79a6dc369023b8f569b36d731b">CSL_DssVpLcdOpTimingCfg</a>
+</li>
+<li>fieldMerged
+: <a class="el" href="struct_fvid2___format.html#a58cee5e76605bdd4a691c8094f719f8d">Fvid2_Format</a>
+</li>
+<li>flipType
+: <a class="el" href="struct_c_s_l___dss_vid_pipe_cfg.html#abebbaaf4c35c0d96cdcc9fdc9300de28">CSL_DssVidPipeCfg</a>
+</li>
+<li>fps
+: <a class="el" href="struct_fvid2___mode_info.html#ad507776704ccbdc7380978d8979777f9">Fvid2_ModeInfo</a>
+</li>
+<li>frames
+: <a class="el" href="struct_fvid2___frame_list.html#ae772ff66598716fe46b8aa687240414c">Fvid2_FrameList</a>
+</li>
+<li>frameSkip
+: <a class="el" href="struct_c_s_l___dss_safety_chk_cfg.html#a6ed2ecbafc577cc70efdb2ba75f93142">CSL_DssSafetyChkCfg</a>
+</li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/functions_g.html b/packages/ti/drv/dss/docs/doxygen/html/functions_g.html
--- /dev/null
@@ -0,0 +1,89 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li class="current"><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="files.html"><span>Files</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow2" class="tabs2">
+ <ul class="tablist">
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li class="current"><a href="functions.html"><span>Data Fields</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow3" class="tabs2">
+ <ul class="tablist">
+ <li class="current"><a href="functions.html"><span>All</span></a></li>
+ <li><a href="functions_vars.html"><span>Variables</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow4" class="tabs3">
+ <ul class="tablist">
+ <li><a href="functions.html#index_a"><span>a</span></a></li>
+ <li><a href="functions_b.html#index_b"><span>b</span></a></li>
+ <li><a href="functions_c.html#index_c"><span>c</span></a></li>
+ <li><a href="functions_d.html#index_d"><span>d</span></a></li>
+ <li><a href="functions_e.html#index_e"><span>e</span></a></li>
+ <li><a href="functions_f.html#index_f"><span>f</span></a></li>
+ <li class="current"><a href="functions_g.html#index_g"><span>g</span></a></li>
+ <li><a href="functions_h.html#index_h"><span>h</span></a></li>
+ <li><a href="functions_i.html#index_i"><span>i</span></a></li>
+ <li><a href="functions_l.html#index_l"><span>l</span></a></li>
+ <li><a href="functions_m.html#index_m"><span>m</span></a></li>
+ <li><a href="functions_n.html#index_n"><span>n</span></a></li>
+ <li><a href="functions_o.html#index_o"><span>o</span></a></li>
+ <li><a href="functions_p.html#index_p"><span>p</span></a></li>
+ <li><a href="functions_q.html#index_q"><span>q</span></a></li>
+ <li><a href="functions_r.html#index_r"><span>r</span></a></li>
+ <li><a href="functions_s.html#index_s"><span>s</span></a></li>
+ <li><a href="functions_t.html#index_t"><span>t</span></a></li>
+ <li><a href="functions_u.html#index_u"><span>u</span></a></li>
+ <li><a href="functions_v.html#index_v"><span>v</span></a></li>
+ <li><a href="functions_w.html#index_w"><span>w</span></a></li>
+ <li><a href="functions_y.html#index_y"><span>y</span></a></li>
+ </ul>
+ </div>
+</div><!-- top -->
+<div class="contents">
+<div class="textblock">Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:</div>
+
+<h3><a class="anchor" id="index_g"></a>- g -</h3><ul>
+<li>gammaData
+: <a class="el" href="struct_c_s_l___dss_vp_gamma_cfg.html#abe6f3edc0a2132f4c12e7a879069bca5">CSL_DssVpGammaCfg</a>
+</li>
+<li>gammaEnable
+: <a class="el" href="struct_c_s_l___dss_vid_pipe_cfg.html#a5e9c6107d03fb837bc74a71538c5ed3e">CSL_DssVidPipeCfg</a>
+, <a class="el" href="struct_c_s_l___dss_vp_gamma_cfg.html#a64733ec49dec684d60ce3fe608323e90">CSL_DssVpGammaCfg</a>
+</li>
+<li>globalAlpha
+: <a class="el" href="struct_c_s_l___dss_vid_pipe_alpha_cfg.html#af1657cd739f1bde94ae85e504c3e5af6">CSL_DssVidPipeAlphaCfg</a>
+</li>
+<li>globalMflagCfg
+: <a class="el" href="struct_dss___dctrl_global_dss_params.html#af07803690960e450435f1d962bd6e82a">Dss_DctrlGlobalDssParams</a>
+</li>
+<li>globalMflagCtrl
+: <a class="el" href="struct_c_s_l___dss_global_m_flag_cfg.html#a476453835fc320b9268d47a22b23dbc8">CSL_DssGlobalMFlagCfg</a>
+</li>
+<li>globalMflagStart
+: <a class="el" href="struct_c_s_l___dss_global_m_flag_cfg.html#ab59aea1dc07f654fc07e0710421923f2">CSL_DssGlobalMFlagCfg</a>
+</li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/functions_h.html b/packages/ti/drv/dss/docs/doxygen/html/functions_h.html
--- /dev/null
@@ -0,0 +1,103 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li class="current"><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="files.html"><span>Files</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow2" class="tabs2">
+ <ul class="tablist">
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li class="current"><a href="functions.html"><span>Data Fields</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow3" class="tabs2">
+ <ul class="tablist">
+ <li class="current"><a href="functions.html"><span>All</span></a></li>
+ <li><a href="functions_vars.html"><span>Variables</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow4" class="tabs3">
+ <ul class="tablist">
+ <li><a href="functions.html#index_a"><span>a</span></a></li>
+ <li><a href="functions_b.html#index_b"><span>b</span></a></li>
+ <li><a href="functions_c.html#index_c"><span>c</span></a></li>
+ <li><a href="functions_d.html#index_d"><span>d</span></a></li>
+ <li><a href="functions_e.html#index_e"><span>e</span></a></li>
+ <li><a href="functions_f.html#index_f"><span>f</span></a></li>
+ <li><a href="functions_g.html#index_g"><span>g</span></a></li>
+ <li class="current"><a href="functions_h.html#index_h"><span>h</span></a></li>
+ <li><a href="functions_i.html#index_i"><span>i</span></a></li>
+ <li><a href="functions_l.html#index_l"><span>l</span></a></li>
+ <li><a href="functions_m.html#index_m"><span>m</span></a></li>
+ <li><a href="functions_n.html#index_n"><span>n</span></a></li>
+ <li><a href="functions_o.html#index_o"><span>o</span></a></li>
+ <li><a href="functions_p.html#index_p"><span>p</span></a></li>
+ <li><a href="functions_q.html#index_q"><span>q</span></a></li>
+ <li><a href="functions_r.html#index_r"><span>r</span></a></li>
+ <li><a href="functions_s.html#index_s"><span>s</span></a></li>
+ <li><a href="functions_t.html#index_t"><span>t</span></a></li>
+ <li><a href="functions_u.html#index_u"><span>u</span></a></li>
+ <li><a href="functions_v.html#index_v"><span>v</span></a></li>
+ <li><a href="functions_w.html#index_w"><span>w</span></a></li>
+ <li><a href="functions_y.html#index_y"><span>y</span></a></li>
+ </ul>
+ </div>
+</div><!-- top -->
+<div class="contents">
+<div class="textblock">Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:</div>
+
+<h3><a class="anchor" id="index_h"></a>- h -</h3><ul>
+<li>hBackPorch
+: <a class="el" href="struct_c_s_l___dss_vp_lcd_blank_timing_cfg.html#afea7b5341ea83edbb5d067c5bc8a152b">CSL_DssVpLcdBlankTimingCfg</a>
+, <a class="el" href="struct_fvid2___mode_info.html#a0d8d9e15366412921d1b1cb083924236">Fvid2_ModeInfo</a>
+</li>
+<li>height
+: <a class="el" href="struct_dss___frame_rt_params.html#ab174627123752cb63bbd8450275ccc5c">Dss_FrameRtParams</a>
+, <a class="el" href="struct_fvid2___format.html#a4585d49a857883721f2664f4a0826849">Fvid2_Format</a>
+, <a class="el" href="struct_fvid2___mode_info.html#a086db39a44f2c72f78a9016263d56123">Fvid2_ModeInfo</a>
+, <a class="el" href="struct_fvid2___size_config.html#ae111168986dd4c3e73a9ffeed987cb3c">Fvid2_SizeConfig</a>
+</li>
+<li>hFrontPorch
+: <a class="el" href="struct_c_s_l___dss_vp_lcd_blank_timing_cfg.html#acdf92ed15c2e9ee31271fb9d611665b5">CSL_DssVpLcdBlankTimingCfg</a>
+, <a class="el" href="struct_fvid2___mode_info.html#a9c7400f345023ef6ebbf384d9d4f5a0c">Fvid2_ModeInfo</a>
+</li>
+<li>hsPolarity
+: <a class="el" href="struct_c_s_l___dss_vp_lcd_signal_polarity_cfg.html#a07d10e32b5c69a73ab69eb18f0e3e1e7">CSL_DssVpLcdSignalPolarityCfg</a>
+</li>
+<li>hSyncGated
+: <a class="el" href="struct_c_s_l___dss_vp_lcd_adv_signal_cfg.html#aa9d9f9160213e99b0018acb25aad2873">CSL_DssVpLcdAdvSignalCfg</a>
+</li>
+<li>hSyncLen
+: <a class="el" href="struct_c_s_l___dss_vp_lcd_blank_timing_cfg.html#ad79981ec3f4a8df8ee12b1dd96e7c667">CSL_DssVpLcdBlankTimingCfg</a>
+, <a class="el" href="struct_fvid2___mode_info.html#ac30f9a789796a753ee22fd56d837b0dc">Fvid2_ModeInfo</a>
+</li>
+<li>hVAlign
+: <a class="el" href="struct_c_s_l___dss_vp_lcd_adv_signal_cfg.html#a2e82a5ae83cd53e3b4f0608a8058c69b">CSL_DssVpLcdAdvSignalCfg</a>
+</li>
+<li>hVClkControl
+: <a class="el" href="struct_c_s_l___dss_vp_lcd_adv_signal_cfg.html#a5794fc2d4b1012397f05e36b64e98809">CSL_DssVpLcdAdvSignalCfg</a>
+</li>
+<li>hVClkRiseFall
+: <a class="el" href="struct_c_s_l___dss_vp_lcd_adv_signal_cfg.html#ad021ce573a1521cf305a2f2080db9589">CSL_DssVpLcdAdvSignalCfg</a>
+</li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/functions_i.html b/packages/ti/drv/dss/docs/doxygen/html/functions_i.html
--- /dev/null
@@ -0,0 +1,97 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li class="current"><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="files.html"><span>Files</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow2" class="tabs2">
+ <ul class="tablist">
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li class="current"><a href="functions.html"><span>Data Fields</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow3" class="tabs2">
+ <ul class="tablist">
+ <li class="current"><a href="functions.html"><span>All</span></a></li>
+ <li><a href="functions_vars.html"><span>Variables</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow4" class="tabs3">
+ <ul class="tablist">
+ <li><a href="functions.html#index_a"><span>a</span></a></li>
+ <li><a href="functions_b.html#index_b"><span>b</span></a></li>
+ <li><a href="functions_c.html#index_c"><span>c</span></a></li>
+ <li><a href="functions_d.html#index_d"><span>d</span></a></li>
+ <li><a href="functions_e.html#index_e"><span>e</span></a></li>
+ <li><a href="functions_f.html#index_f"><span>f</span></a></li>
+ <li><a href="functions_g.html#index_g"><span>g</span></a></li>
+ <li><a href="functions_h.html#index_h"><span>h</span></a></li>
+ <li class="current"><a href="functions_i.html#index_i"><span>i</span></a></li>
+ <li><a href="functions_l.html#index_l"><span>l</span></a></li>
+ <li><a href="functions_m.html#index_m"><span>m</span></a></li>
+ <li><a href="functions_n.html#index_n"><span>n</span></a></li>
+ <li><a href="functions_o.html#index_o"><span>o</span></a></li>
+ <li><a href="functions_p.html#index_p"><span>p</span></a></li>
+ <li><a href="functions_q.html#index_q"><span>q</span></a></li>
+ <li><a href="functions_r.html#index_r"><span>r</span></a></li>
+ <li><a href="functions_s.html#index_s"><span>s</span></a></li>
+ <li><a href="functions_t.html#index_t"><span>t</span></a></li>
+ <li><a href="functions_u.html#index_u"><span>u</span></a></li>
+ <li><a href="functions_v.html#index_v"><span>v</span></a></li>
+ <li><a href="functions_w.html#index_w"><span>w</span></a></li>
+ <li><a href="functions_y.html#index_y"><span>y</span></a></li>
+ </ul>
+ </div>
+</div><!-- top -->
+<div class="contents">
+<div class="textblock">Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:</div>
+
+<h3><a class="anchor" id="index_i"></a>- i -</h3><ul>
+<li>inFmt
+: <a class="el" href="struct_c_s_l___dss_vid_pipe_cfg.html#ad746f01b386f5f8b836ae76193641be0">CSL_DssVidPipeCfg</a>
+</li>
+<li>inFrmParams
+: <a class="el" href="struct_dss___disp_rt_params.html#a6cc436c9916749a865525d66388c7133">Dss_DispRtParams</a>
+</li>
+<li>inputPipe
+: <a class="el" href="struct_c_s_l___dss_overlay_layer_cfg.html#a9fa2884d228ae00ba4694fcb04c76bf9">CSL_DssOverlayLayerCfg</a>
+</li>
+<li>irqNum
+: <a class="el" href="struct_dss___irq_params.html#aa3ef349676a4f3e5ff139616501c4a25">Dss_IrqParams</a>
+</li>
+<li>irqParams
+: <a class="el" href="struct_dss___soc_params.html#a8323d29f1f228a29162b29d1ab487b5a">Dss_SocParams</a>
+</li>
+<li>isCommRegAvailable
+: <a class="el" href="struct_dss___rm_info.html#aba3fc693c174a47dd1d73a9e58d97b00">Dss_RmInfo</a>
+</li>
+<li>isOverlayAvailable
+: <a class="el" href="struct_dss___rm_info.html#ac9add0a21cbc5d3a4b0f893e766e593e">Dss_RmInfo</a>
+</li>
+<li>isPipeAvailable
+: <a class="el" href="struct_dss___rm_info.html#a4b8a53db450d230a652cd8cc38d9cd5a">Dss_RmInfo</a>
+</li>
+<li>isPortAvailable
+: <a class="el" href="struct_dss___rm_info.html#a72fbf32ce584379f198783a281f00130">Dss_RmInfo</a>
+</li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/functions_l.html b/packages/ti/drv/dss/docs/doxygen/html/functions_l.html
--- /dev/null
@@ -0,0 +1,104 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li class="current"><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="files.html"><span>Files</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow2" class="tabs2">
+ <ul class="tablist">
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li class="current"><a href="functions.html"><span>Data Fields</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow3" class="tabs2">
+ <ul class="tablist">
+ <li class="current"><a href="functions.html"><span>All</span></a></li>
+ <li><a href="functions_vars.html"><span>Variables</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow4" class="tabs3">
+ <ul class="tablist">
+ <li><a href="functions.html#index_a"><span>a</span></a></li>
+ <li><a href="functions_b.html#index_b"><span>b</span></a></li>
+ <li><a href="functions_c.html#index_c"><span>c</span></a></li>
+ <li><a href="functions_d.html#index_d"><span>d</span></a></li>
+ <li><a href="functions_e.html#index_e"><span>e</span></a></li>
+ <li><a href="functions_f.html#index_f"><span>f</span></a></li>
+ <li><a href="functions_g.html#index_g"><span>g</span></a></li>
+ <li><a href="functions_h.html#index_h"><span>h</span></a></li>
+ <li><a href="functions_i.html#index_i"><span>i</span></a></li>
+ <li class="current"><a href="functions_l.html#index_l"><span>l</span></a></li>
+ <li><a href="functions_m.html#index_m"><span>m</span></a></li>
+ <li><a href="functions_n.html#index_n"><span>n</span></a></li>
+ <li><a href="functions_o.html#index_o"><span>o</span></a></li>
+ <li><a href="functions_p.html#index_p"><span>p</span></a></li>
+ <li><a href="functions_q.html#index_q"><span>q</span></a></li>
+ <li><a href="functions_r.html#index_r"><span>r</span></a></li>
+ <li><a href="functions_s.html#index_s"><span>s</span></a></li>
+ <li><a href="functions_t.html#index_t"><span>t</span></a></li>
+ <li><a href="functions_u.html#index_u"><span>u</span></a></li>
+ <li><a href="functions_v.html#index_v"><span>v</span></a></li>
+ <li><a href="functions_w.html#index_w"><span>w</span></a></li>
+ <li><a href="functions_y.html#index_y"><span>y</span></a></li>
+ </ul>
+ </div>
+</div><!-- top -->
+<div class="contents">
+<div class="textblock">Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:</div>
+
+<h3><a class="anchor" id="index_l"></a>- l -</h3><ul>
+<li>layerEnable
+: <a class="el" href="struct_c_s_l___dss_overlay_layer_cfg.html#a83dcc8dccd51c4dd38f5c8de44226596">CSL_DssOverlayLayerCfg</a>
+</li>
+<li>layerNum
+: <a class="el" href="struct_c_s_l___dss_overlay_layer_cfg.html#a79b077926e883044363d2fe27a986196">CSL_DssOverlayLayerCfg</a>
+</li>
+<li>layerPos
+: <a class="el" href="struct_c_s_l___dss_overlay_pipe_pos_cfg.html#af609b8a3d9d62d0dd1ac4756c3add323">CSL_DssOverlayPipePosCfg</a>
+, <a class="el" href="struct_dss___disp_params.html#ac26e2dd60bc2eb1f9a1ef92f5b8374c8">Dss_DispParams</a>
+</li>
+<li>lcdAdvSignalCfg
+: <a class="el" href="struct_dss___dctrl_adv_vp_params.html#a6f8a69ef5d888ab0efac61cd952b84e4">Dss_DctrlAdvVpParams</a>
+</li>
+<li>lcdBlankTimingCfg
+: <a class="el" href="struct_dss___dctrl_lcd_blank_timing_params.html#ab210add6d59769281c95f6d1bc8b9d76">Dss_DctrlLcdBlankTimingParams</a>
+</li>
+<li>lcdOpTimingCfg
+: <a class="el" href="struct_dss___dctrl_vp_params.html#ab85222c9535dd65a0148c5df4ebf4d2f">Dss_DctrlVpParams</a>
+</li>
+<li>lcdPolarityCfg
+: <a class="el" href="struct_dss___dctrl_vp_params.html#a40f589e08e3d00ac44640cc27ffd20dd">Dss_DctrlVpParams</a>
+</li>
+<li>lcdTdmCfg
+: <a class="el" href="struct_dss___dctrl_vp_params.html#a705586424b3d0c7af64f8bae7d95fcba">Dss_DctrlVpParams</a>
+</li>
+<li>lumaKeyEnable
+: <a class="el" href="struct_c_s_l___dss_vid_pipe_luma_cfg.html#a963fa503522975f7e78da0e7085ac209">CSL_DssVidPipeLumaCfg</a>
+</li>
+<li>lumaKeyMaxVal
+: <a class="el" href="struct_c_s_l___dss_vid_pipe_luma_cfg.html#af695a93a94cb7e1981719483d56feda5">CSL_DssVidPipeLumaCfg</a>
+</li>
+<li>lumaKeyMinVal
+: <a class="el" href="struct_c_s_l___dss_vid_pipe_luma_cfg.html#af92d3bdda59367a1120e40316b8469b5">CSL_DssVidPipeLumaCfg</a>
+</li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/functions_m.html b/packages/ti/drv/dss/docs/doxygen/html/functions_m.html
--- /dev/null
@@ -0,0 +1,79 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li class="current"><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="files.html"><span>Files</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow2" class="tabs2">
+ <ul class="tablist">
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li class="current"><a href="functions.html"><span>Data Fields</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow3" class="tabs2">
+ <ul class="tablist">
+ <li class="current"><a href="functions.html"><span>All</span></a></li>
+ <li><a href="functions_vars.html"><span>Variables</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow4" class="tabs3">
+ <ul class="tablist">
+ <li><a href="functions.html#index_a"><span>a</span></a></li>
+ <li><a href="functions_b.html#index_b"><span>b</span></a></li>
+ <li><a href="functions_c.html#index_c"><span>c</span></a></li>
+ <li><a href="functions_d.html#index_d"><span>d</span></a></li>
+ <li><a href="functions_e.html#index_e"><span>e</span></a></li>
+ <li><a href="functions_f.html#index_f"><span>f</span></a></li>
+ <li><a href="functions_g.html#index_g"><span>g</span></a></li>
+ <li><a href="functions_h.html#index_h"><span>h</span></a></li>
+ <li><a href="functions_i.html#index_i"><span>i</span></a></li>
+ <li><a href="functions_l.html#index_l"><span>l</span></a></li>
+ <li class="current"><a href="functions_m.html#index_m"><span>m</span></a></li>
+ <li><a href="functions_n.html#index_n"><span>n</span></a></li>
+ <li><a href="functions_o.html#index_o"><span>o</span></a></li>
+ <li><a href="functions_p.html#index_p"><span>p</span></a></li>
+ <li><a href="functions_q.html#index_q"><span>q</span></a></li>
+ <li><a href="functions_r.html#index_r"><span>r</span></a></li>
+ <li><a href="functions_s.html#index_s"><span>s</span></a></li>
+ <li><a href="functions_t.html#index_t"><span>t</span></a></li>
+ <li><a href="functions_u.html#index_u"><span>u</span></a></li>
+ <li><a href="functions_v.html#index_v"><span>v</span></a></li>
+ <li><a href="functions_w.html#index_w"><span>w</span></a></li>
+ <li><a href="functions_y.html#index_y"><span>y</span></a></li>
+ </ul>
+ </div>
+</div><!-- top -->
+<div class="contents">
+<div class="textblock">Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:</div>
+
+<h3><a class="anchor" id="index_m"></a>- m -</h3><ul>
+<li>mflagCfg
+: <a class="el" href="struct_dss___disp_pipe_mflag_params.html#a006a172bac6001d494ac6f1901d56f1e">Dss_DispPipeMflagParams</a>
+</li>
+<li>mInfo
+: <a class="el" href="struct_c_s_l___dss_vp_lcd_op_timing_cfg.html#a19292617b2fdd63c9d9d85a1ea41d97a">CSL_DssVpLcdOpTimingCfg</a>
+</li>
+<li>minNumPrimeBuf
+: <a class="el" href="struct_dss___disp_create_status.html#a12b0ad905934ec8007bcd821cf0deff7">Dss_DispCreateStatus</a>
+</li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/functions_n.html b/packages/ti/drv/dss/docs/doxygen/html/functions_n.html
--- /dev/null
@@ -0,0 +1,106 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li class="current"><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="files.html"><span>Files</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow2" class="tabs2">
+ <ul class="tablist">
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li class="current"><a href="functions.html"><span>Data Fields</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow3" class="tabs2">
+ <ul class="tablist">
+ <li class="current"><a href="functions.html"><span>All</span></a></li>
+ <li><a href="functions_vars.html"><span>Variables</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow4" class="tabs3">
+ <ul class="tablist">
+ <li><a href="functions.html#index_a"><span>a</span></a></li>
+ <li><a href="functions_b.html#index_b"><span>b</span></a></li>
+ <li><a href="functions_c.html#index_c"><span>c</span></a></li>
+ <li><a href="functions_d.html#index_d"><span>d</span></a></li>
+ <li><a href="functions_e.html#index_e"><span>e</span></a></li>
+ <li><a href="functions_f.html#index_f"><span>f</span></a></li>
+ <li><a href="functions_g.html#index_g"><span>g</span></a></li>
+ <li><a href="functions_h.html#index_h"><span>h</span></a></li>
+ <li><a href="functions_i.html#index_i"><span>i</span></a></li>
+ <li><a href="functions_l.html#index_l"><span>l</span></a></li>
+ <li><a href="functions_m.html#index_m"><span>m</span></a></li>
+ <li class="current"><a href="functions_n.html#index_n"><span>n</span></a></li>
+ <li><a href="functions_o.html#index_o"><span>o</span></a></li>
+ <li><a href="functions_p.html#index_p"><span>p</span></a></li>
+ <li><a href="functions_q.html#index_q"><span>q</span></a></li>
+ <li><a href="functions_r.html#index_r"><span>r</span></a></li>
+ <li><a href="functions_s.html#index_s"><span>s</span></a></li>
+ <li><a href="functions_t.html#index_t"><span>t</span></a></li>
+ <li><a href="functions_u.html#index_u"><span>u</span></a></li>
+ <li><a href="functions_v.html#index_v"><span>v</span></a></li>
+ <li><a href="functions_w.html#index_w"><span>w</span></a></li>
+ <li><a href="functions_y.html#index_y"><span>y</span></a></li>
+ </ul>
+ </div>
+</div><!-- top -->
+<div class="contents">
+<div class="textblock">Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:</div>
+
+<h3><a class="anchor" id="index_n"></a>- n -</h3><ul>
+<li>nibblemodeEnable
+: <a class="el" href="struct_c_s_l___dss_vid_pipe_cfg.html#a3c4e8eb4baaf50467b94c025b7f9831f">CSL_DssVidPipeCfg</a>
+</li>
+<li>numBitsPixel1Cycle0
+: <a class="el" href="struct_c_s_l___dss_vp_lcd_tdm_cfg.html#a0d9325def55c887e1e6d6b240c66e290">CSL_DssVpLcdTdmCfg</a>
+</li>
+<li>numBitsPixel1Cycle1
+: <a class="el" href="struct_c_s_l___dss_vp_lcd_tdm_cfg.html#acdc280739512994d6cc71dd1125e12fb">CSL_DssVpLcdTdmCfg</a>
+</li>
+<li>numBitsPixel1Cycle2
+: <a class="el" href="struct_c_s_l___dss_vp_lcd_tdm_cfg.html#ae83d325c5b05f1db8045509f5de15269">CSL_DssVpLcdTdmCfg</a>
+</li>
+<li>numBitsPixel2Cycle0
+: <a class="el" href="struct_c_s_l___dss_vp_lcd_tdm_cfg.html#a24039fc18531e5abf5f24eae912385d4">CSL_DssVpLcdTdmCfg</a>
+</li>
+<li>numBitsPixel2Cycle1
+: <a class="el" href="struct_c_s_l___dss_vp_lcd_tdm_cfg.html#adc86e977d445f895132a246b494ae240">CSL_DssVpLcdTdmCfg</a>
+</li>
+<li>numBitsPixel2Cycle2
+: <a class="el" href="struct_c_s_l___dss_vp_lcd_tdm_cfg.html#ad1b25370dd21ced32c4a9a3abb5e50f0">CSL_DssVpLcdTdmCfg</a>
+</li>
+<li>numEdges
+: <a class="el" href="struct_dss___dctrl_path_info.html#a86805ff6cd957de13ee114445fc2a316">Dss_DctrlPathInfo</a>
+</li>
+<li>numFrames
+: <a class="el" href="struct_fvid2___frame_list.html#af516451b916cad435d827c96669e2825">Fvid2_FrameList</a>
+</li>
+<li>numInLines
+: <a class="el" href="struct_fvid2___sub_frame_info.html#a813a5659d1d56a49b0d1b6d8d600ae74">Fvid2_SubFrameInfo</a>
+</li>
+<li>numOutLines
+: <a class="el" href="struct_fvid2___sub_frame_info.html#aad0a2f3475b4f409b956a359b31a0960">Fvid2_SubFrameInfo</a>
+</li>
+<li>numValidIrq
+: <a class="el" href="struct_dss___irq_params.html#aa506ef07fa2b7d3396f82dc52e46c2bd">Dss_IrqParams</a>
+</li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/functions_o.html b/packages/ti/drv/dss/docs/doxygen/html/functions_o.html
--- /dev/null
@@ -0,0 +1,89 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li class="current"><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="files.html"><span>Files</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow2" class="tabs2">
+ <ul class="tablist">
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li class="current"><a href="functions.html"><span>Data Fields</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow3" class="tabs2">
+ <ul class="tablist">
+ <li class="current"><a href="functions.html"><span>All</span></a></li>
+ <li><a href="functions_vars.html"><span>Variables</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow4" class="tabs3">
+ <ul class="tablist">
+ <li><a href="functions.html#index_a"><span>a</span></a></li>
+ <li><a href="functions_b.html#index_b"><span>b</span></a></li>
+ <li><a href="functions_c.html#index_c"><span>c</span></a></li>
+ <li><a href="functions_d.html#index_d"><span>d</span></a></li>
+ <li><a href="functions_e.html#index_e"><span>e</span></a></li>
+ <li><a href="functions_f.html#index_f"><span>f</span></a></li>
+ <li><a href="functions_g.html#index_g"><span>g</span></a></li>
+ <li><a href="functions_h.html#index_h"><span>h</span></a></li>
+ <li><a href="functions_i.html#index_i"><span>i</span></a></li>
+ <li><a href="functions_l.html#index_l"><span>l</span></a></li>
+ <li><a href="functions_m.html#index_m"><span>m</span></a></li>
+ <li><a href="functions_n.html#index_n"><span>n</span></a></li>
+ <li class="current"><a href="functions_o.html#index_o"><span>o</span></a></li>
+ <li><a href="functions_p.html#index_p"><span>p</span></a></li>
+ <li><a href="functions_q.html#index_q"><span>q</span></a></li>
+ <li><a href="functions_r.html#index_r"><span>r</span></a></li>
+ <li><a href="functions_s.html#index_s"><span>s</span></a></li>
+ <li><a href="functions_t.html#index_t"><span>t</span></a></li>
+ <li><a href="functions_u.html#index_u"><span>u</span></a></li>
+ <li><a href="functions_v.html#index_v"><span>v</span></a></li>
+ <li><a href="functions_w.html#index_w"><span>w</span></a></li>
+ <li><a href="functions_y.html#index_y"><span>y</span></a></li>
+ </ul>
+ </div>
+</div><!-- top -->
+<div class="contents">
+<div class="textblock">Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:</div>
+
+<h3><a class="anchor" id="index_o"></a>- o -</h3><ul>
+<li>oldiCfg
+: <a class="el" href="struct_dss___dctrl_oldi_params.html#adad012c98bd5cf3ce7cb164f57ba38cb">Dss_DctrlOldiParams</a>
+</li>
+<li>outFrmParams
+: <a class="el" href="struct_dss___disp_rt_params.html#a8190a88390e7d3d6327d53c73381a997">Dss_DispRtParams</a>
+</li>
+<li>outHeight
+: <a class="el" href="struct_c_s_l___dss_vid_pipe_cfg.html#a1d3a19f6cf680aba0505a2abd670140e">CSL_DssVidPipeCfg</a>
+</li>
+<li>outWidth
+: <a class="el" href="struct_c_s_l___dss_vid_pipe_cfg.html#aee9fafc3374aa44e5d8aa0ade330de5c">CSL_DssVidPipeCfg</a>
+</li>
+<li>overlayCfg
+: <a class="el" href="struct_dss___dctrl_overlay_params.html#acaee7b8d01578e10237919957527a046">Dss_DctrlOverlayParams</a>
+</li>
+<li>overlayId
+: <a class="el" href="struct_dss___dctrl_overlay_layer_params.html#af8e6714702ff114368a6b0fd566e3e65">Dss_DctrlOverlayLayerParams</a>
+, <a class="el" href="struct_dss___dctrl_overlay_params.html#a2883c49b828e361ecc83312668ef535d">Dss_DctrlOverlayParams</a>
+</li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/functions_p.html b/packages/ti/drv/dss/docs/doxygen/html/functions_p.html
--- /dev/null
@@ -0,0 +1,153 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li class="current"><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="files.html"><span>Files</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow2" class="tabs2">
+ <ul class="tablist">
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li class="current"><a href="functions.html"><span>Data Fields</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow3" class="tabs2">
+ <ul class="tablist">
+ <li class="current"><a href="functions.html"><span>All</span></a></li>
+ <li><a href="functions_vars.html"><span>Variables</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow4" class="tabs3">
+ <ul class="tablist">
+ <li><a href="functions.html#index_a"><span>a</span></a></li>
+ <li><a href="functions_b.html#index_b"><span>b</span></a></li>
+ <li><a href="functions_c.html#index_c"><span>c</span></a></li>
+ <li><a href="functions_d.html#index_d"><span>d</span></a></li>
+ <li><a href="functions_e.html#index_e"><span>e</span></a></li>
+ <li><a href="functions_f.html#index_f"><span>f</span></a></li>
+ <li><a href="functions_g.html#index_g"><span>g</span></a></li>
+ <li><a href="functions_h.html#index_h"><span>h</span></a></li>
+ <li><a href="functions_i.html#index_i"><span>i</span></a></li>
+ <li><a href="functions_l.html#index_l"><span>l</span></a></li>
+ <li><a href="functions_m.html#index_m"><span>m</span></a></li>
+ <li><a href="functions_n.html#index_n"><span>n</span></a></li>
+ <li><a href="functions_o.html#index_o"><span>o</span></a></li>
+ <li class="current"><a href="functions_p.html#index_p"><span>p</span></a></li>
+ <li><a href="functions_q.html#index_q"><span>q</span></a></li>
+ <li><a href="functions_r.html#index_r"><span>r</span></a></li>
+ <li><a href="functions_s.html#index_s"><span>s</span></a></li>
+ <li><a href="functions_t.html#index_t"><span>t</span></a></li>
+ <li><a href="functions_u.html#index_u"><span>u</span></a></li>
+ <li><a href="functions_v.html#index_v"><span>v</span></a></li>
+ <li><a href="functions_w.html#index_w"><span>w</span></a></li>
+ <li><a href="functions_y.html#index_y"><span>y</span></a></li>
+ </ul>
+ </div>
+</div><!-- top -->
+<div class="contents">
+<div class="textblock">Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:</div>
+
+<h3><a class="anchor" id="index_p"></a>- p -</h3><ul>
+<li>perFrameCfg
+: <a class="el" href="struct_fvid2___frame.html#ab70ec59f98e2fa3bac85f5fe25645bcc">Fvid2_Frame</a>
+</li>
+<li>periodicCbEnable
+: <a class="el" href="struct_dss___disp_create_params.html#ab8366600abad325065cdf8fac4de2a77">Dss_DispCreateParams</a>
+</li>
+<li>perListCfg
+: <a class="el" href="struct_fvid2___frame_list.html#ab6dbd19e34bebec6941fbde314fcfb4f">Fvid2_FrameList</a>
+</li>
+<li>pipeCfg
+: <a class="el" href="struct_dss___disp_params.html#a48165b146fa02698a76b378930ad9a3f">Dss_DispParams</a>
+</li>
+<li>pipeLayerNum
+: <a class="el" href="struct_dss___dctrl_overlay_layer_params.html#a8c4c1af551a7aa49f3e5eab31c7f3d26">Dss_DctrlOverlayLayerParams</a>
+</li>
+<li>pipePrgmCbFxn
+: <a class="el" href="struct_dss___disp_pipe_prgm_cb_params.html#a3665e053d0ee61b9555b4640f4e1325f">Dss_DispPipePrgmCbParams</a>
+</li>
+<li>pipeSafetyChkCfg
+: <a class="el" href="struct_dss___disp_pipe_safety_chk_params.html#a1d2da23596678e366eddaad75e2382c3">Dss_DispPipeSafetyChkParams</a>
+</li>
+<li>pipeType
+: <a class="el" href="struct_c_s_l___dss_vid_pipe_cfg.html#a85e0ba7c97b71003b61e862ebc3fbe40">CSL_DssVidPipeCfg</a>
+</li>
+<li>pitch
+: <a class="el" href="struct_dss___frame_rt_params.html#a4dab0431dffbdbcb94b06e5cb27c7f06">Dss_FrameRtParams</a>
+, <a class="el" href="struct_fvid2___format.html#a3721a977887cae78aa15398c8214145b">Fvid2_Format</a>
+</li>
+<li>pixelClkPolarity
+: <a class="el" href="struct_c_s_l___dss_vp_lcd_signal_polarity_cfg.html#a097ae617d62555043fe4edd375a6963c">CSL_DssVpLcdSignalPolarityCfg</a>
+</li>
+<li>pixelClock
+: <a class="el" href="struct_fvid2___mode_info.html#ac65ac9af809220a1a6445bfa1111ca05">Fvid2_ModeInfo</a>
+</li>
+<li>pixelClockGated
+: <a class="el" href="struct_c_s_l___dss_vp_lcd_adv_signal_cfg.html#a071dfbc56f4de8d9818e824d03a9662c">CSL_DssVpLcdAdvSignalCfg</a>
+</li>
+<li>pixelDataGated
+: <a class="el" href="struct_c_s_l___dss_vp_lcd_adv_signal_cfg.html#a32ff2b36d117b98e574214336a68616e">CSL_DssVpLcdAdvSignalCfg</a>
+</li>
+<li>pixelGated
+: <a class="el" href="struct_c_s_l___dss_vp_lcd_adv_signal_cfg.html#a3111150c26bb26812762ef8de4ba03d6">CSL_DssVpLcdAdvSignalCfg</a>
+</li>
+<li>pixelInc
+: <a class="el" href="struct_c_s_l___dss_vid_pipe_cfg.html#a026189ab1fe6ad7ab75606a70cbc6136">CSL_DssVidPipeCfg</a>
+, <a class="el" href="struct_dss___sc_rt_params.html#a91ae75c8f0ebf3f0cc30b8b97a2024c6">Dss_ScRtParams</a>
+</li>
+<li>posCfg
+: <a class="el" href="struct_dss___disp_rt_params.html#a29259476cb78ef269ef5827d5c59e11e">Dss_DispRtParams</a>
+</li>
+<li>postOffset1
+: <a class="el" href="struct_c_s_l___dss_csc_coeff.html#ab0784bdfae37f766f4ad327bc5e597c6">CSL_DssCscCoeff</a>
+</li>
+<li>postOffset2
+: <a class="el" href="struct_c_s_l___dss_csc_coeff.html#aead82d70ab275933b820a7e87abb05c8">CSL_DssCscCoeff</a>
+</li>
+<li>postOffset3
+: <a class="el" href="struct_c_s_l___dss_csc_coeff.html#a3877e738385c127011a7c14b00c38ddf">CSL_DssCscCoeff</a>
+</li>
+<li>preloadVal
+: <a class="el" href="struct_c_s_l___dss_vid_pipe_dma_cfg.html#a168a8a5323eacf1349b91ff84a28290e">CSL_DssVidPipeDmaCfg</a>
+</li>
+<li>preMultiplyAlpha
+: <a class="el" href="struct_c_s_l___dss_vid_pipe_alpha_cfg.html#a592febc9d395769c45a294b1b2725136">CSL_DssVidPipeAlphaCfg</a>
+</li>
+<li>preOffset1
+: <a class="el" href="struct_c_s_l___dss_csc_coeff.html#ac7220e1ec74749d1223be58334fec6bd">CSL_DssCscCoeff</a>
+</li>
+<li>preOffset2
+: <a class="el" href="struct_c_s_l___dss_csc_coeff.html#ad68c0c52100a22abdc7e7f32726d9070">CSL_DssCscCoeff</a>
+</li>
+<li>preOffset3
+: <a class="el" href="struct_c_s_l___dss_csc_coeff.html#a347ff46868f7d6adfd877071a9fcc899">CSL_DssCscCoeff</a>
+</li>
+<li>priHigh
+: <a class="el" href="struct_c_s_l___dss_cba_cfg.html#a6f7af7472d1da8ba301750414e88640f">CSL_DssCbaCfg</a>
+</li>
+<li>priLow
+: <a class="el" href="struct_c_s_l___dss_cba_cfg.html#a6d3f899c4e19cf0e52d33d01295f75e7">CSL_DssCbaCfg</a>
+</li>
+<li>progPipeVsyncEnable
+: <a class="el" href="struct_dss___disp_create_params.html#a1b1d68b7e5feb7f8c40fb925db6a2ce9">Dss_DispCreateParams</a>
+</li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/functions_q.html b/packages/ti/drv/dss/docs/doxygen/html/functions_q.html
--- /dev/null
@@ -0,0 +1,73 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li class="current"><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="files.html"><span>Files</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow2" class="tabs2">
+ <ul class="tablist">
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li class="current"><a href="functions.html"><span>Data Fields</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow3" class="tabs2">
+ <ul class="tablist">
+ <li class="current"><a href="functions.html"><span>All</span></a></li>
+ <li><a href="functions_vars.html"><span>Variables</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow4" class="tabs3">
+ <ul class="tablist">
+ <li><a href="functions.html#index_a"><span>a</span></a></li>
+ <li><a href="functions_b.html#index_b"><span>b</span></a></li>
+ <li><a href="functions_c.html#index_c"><span>c</span></a></li>
+ <li><a href="functions_d.html#index_d"><span>d</span></a></li>
+ <li><a href="functions_e.html#index_e"><span>e</span></a></li>
+ <li><a href="functions_f.html#index_f"><span>f</span></a></li>
+ <li><a href="functions_g.html#index_g"><span>g</span></a></li>
+ <li><a href="functions_h.html#index_h"><span>h</span></a></li>
+ <li><a href="functions_i.html#index_i"><span>i</span></a></li>
+ <li><a href="functions_l.html#index_l"><span>l</span></a></li>
+ <li><a href="functions_m.html#index_m"><span>m</span></a></li>
+ <li><a href="functions_n.html#index_n"><span>n</span></a></li>
+ <li><a href="functions_o.html#index_o"><span>o</span></a></li>
+ <li><a href="functions_p.html#index_p"><span>p</span></a></li>
+ <li class="current"><a href="functions_q.html#index_q"><span>q</span></a></li>
+ <li><a href="functions_r.html#index_r"><span>r</span></a></li>
+ <li><a href="functions_s.html#index_s"><span>s</span></a></li>
+ <li><a href="functions_t.html#index_t"><span>t</span></a></li>
+ <li><a href="functions_u.html#index_u"><span>u</span></a></li>
+ <li><a href="functions_v.html#index_v"><span>v</span></a></li>
+ <li><a href="functions_w.html#index_w"><span>w</span></a></li>
+ <li><a href="functions_y.html#index_y"><span>y</span></a></li>
+ </ul>
+ </div>
+</div><!-- top -->
+<div class="contents">
+<div class="textblock">Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:</div>
+
+<h3><a class="anchor" id="index_q"></a>- q -</h3><ul>
+<li>queueCount
+: <a class="el" href="struct_dss___disp_current_status.html#a92cf9e8cc3729ad69f5e7240d3598d01">Dss_DispCurrentStatus</a>
+</li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/functions_r.html b/packages/ti/drv/dss/docs/doxygen/html/functions_r.html
--- /dev/null
@@ -0,0 +1,95 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li class="current"><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="files.html"><span>Files</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow2" class="tabs2">
+ <ul class="tablist">
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li class="current"><a href="functions.html"><span>Data Fields</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow3" class="tabs2">
+ <ul class="tablist">
+ <li class="current"><a href="functions.html"><span>All</span></a></li>
+ <li><a href="functions_vars.html"><span>Variables</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow4" class="tabs3">
+ <ul class="tablist">
+ <li><a href="functions.html#index_a"><span>a</span></a></li>
+ <li><a href="functions_b.html#index_b"><span>b</span></a></li>
+ <li><a href="functions_c.html#index_c"><span>c</span></a></li>
+ <li><a href="functions_d.html#index_d"><span>d</span></a></li>
+ <li><a href="functions_e.html#index_e"><span>e</span></a></li>
+ <li><a href="functions_f.html#index_f"><span>f</span></a></li>
+ <li><a href="functions_g.html#index_g"><span>g</span></a></li>
+ <li><a href="functions_h.html#index_h"><span>h</span></a></li>
+ <li><a href="functions_i.html#index_i"><span>i</span></a></li>
+ <li><a href="functions_l.html#index_l"><span>l</span></a></li>
+ <li><a href="functions_m.html#index_m"><span>m</span></a></li>
+ <li><a href="functions_n.html#index_n"><span>n</span></a></li>
+ <li><a href="functions_o.html#index_o"><span>o</span></a></li>
+ <li><a href="functions_p.html#index_p"><span>p</span></a></li>
+ <li><a href="functions_q.html#index_q"><span>q</span></a></li>
+ <li class="current"><a href="functions_r.html#index_r"><span>r</span></a></li>
+ <li><a href="functions_s.html#index_s"><span>s</span></a></li>
+ <li><a href="functions_t.html#index_t"><span>t</span></a></li>
+ <li><a href="functions_u.html#index_u"><span>u</span></a></li>
+ <li><a href="functions_v.html#index_v"><span>v</span></a></li>
+ <li><a href="functions_w.html#index_w"><span>w</span></a></li>
+ <li><a href="functions_y.html#index_y"><span>y</span></a></li>
+ </ul>
+ </div>
+</div><!-- top -->
+<div class="contents">
+<div class="textblock">Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:</div>
+
+<h3><a class="anchor" id="index_r"></a>- r -</h3><ul>
+<li>rangeUV
+: <a class="el" href="struct_c_s_l___dss_vid_pipe_v_c1_cfg.html#ae6ccf08aef3dd34a7470fc3f266f045c">CSL_DssVidPipeVC1Cfg</a>
+</li>
+<li>rangeY
+: <a class="el" href="struct_c_s_l___dss_vid_pipe_v_c1_cfg.html#ad5abb3e5a9aefd67f460c6c806d9d60a">CSL_DssVidPipeVC1Cfg</a>
+</li>
+<li>referenceSign
+: <a class="el" href="struct_dss___dctrl_region_safety_chk_cfg.html#a33766617818233c722d23b49daf3a1b1">Dss_DctrlRegionSafetyChkCfg</a>
+, <a class="el" href="struct_dss___disp_pipe_safety_chk_params.html#a959fe56578ad3537011559f97fbd4661">Dss_DispPipeSafetyChkParams</a>
+</li>
+<li>regionPos
+: <a class="el" href="struct_c_s_l___dss_safety_chk_cfg.html#acd23c9535ba779805df7c92946522de1">CSL_DssSafetyChkCfg</a>
+</li>
+<li>regionSize
+: <a class="el" href="struct_c_s_l___dss_safety_chk_cfg.html#adfe6989e81985735685e9dc1a3cc2fc3">CSL_DssSafetyChkCfg</a>
+</li>
+<li>repeatFrmCount
+: <a class="el" href="struct_dss___disp_current_status.html#af4c9a477ce0debeae4dbcd653e1d3c18">Dss_DispCurrentStatus</a>
+</li>
+<li>retVal
+: <a class="el" href="struct_dss___disp_create_status.html#a46416dc8db8540d785740d4b3c41f052">Dss_DispCreateStatus</a>
+</li>
+<li>rmInfo
+: <a class="el" href="struct_dss___soc_params.html#aafaaca6953b19d37aa273c25a3a5ada8">Dss_SocParams</a>
+</li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/functions_s.html b/packages/ti/drv/dss/docs/doxygen/html/functions_s.html
--- /dev/null
@@ -0,0 +1,142 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li class="current"><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="files.html"><span>Files</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow2" class="tabs2">
+ <ul class="tablist">
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li class="current"><a href="functions.html"><span>Data Fields</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow3" class="tabs2">
+ <ul class="tablist">
+ <li class="current"><a href="functions.html"><span>All</span></a></li>
+ <li><a href="functions_vars.html"><span>Variables</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow4" class="tabs3">
+ <ul class="tablist">
+ <li><a href="functions.html#index_a"><span>a</span></a></li>
+ <li><a href="functions_b.html#index_b"><span>b</span></a></li>
+ <li><a href="functions_c.html#index_c"><span>c</span></a></li>
+ <li><a href="functions_d.html#index_d"><span>d</span></a></li>
+ <li><a href="functions_e.html#index_e"><span>e</span></a></li>
+ <li><a href="functions_f.html#index_f"><span>f</span></a></li>
+ <li><a href="functions_g.html#index_g"><span>g</span></a></li>
+ <li><a href="functions_h.html#index_h"><span>h</span></a></li>
+ <li><a href="functions_i.html#index_i"><span>i</span></a></li>
+ <li><a href="functions_l.html#index_l"><span>l</span></a></li>
+ <li><a href="functions_m.html#index_m"><span>m</span></a></li>
+ <li><a href="functions_n.html#index_n"><span>n</span></a></li>
+ <li><a href="functions_o.html#index_o"><span>o</span></a></li>
+ <li><a href="functions_p.html#index_p"><span>p</span></a></li>
+ <li><a href="functions_q.html#index_q"><span>q</span></a></li>
+ <li><a href="functions_r.html#index_r"><span>r</span></a></li>
+ <li class="current"><a href="functions_s.html#index_s"><span>s</span></a></li>
+ <li><a href="functions_t.html#index_t"><span>t</span></a></li>
+ <li><a href="functions_u.html#index_u"><span>u</span></a></li>
+ <li><a href="functions_v.html#index_v"><span>v</span></a></li>
+ <li><a href="functions_w.html#index_w"><span>w</span></a></li>
+ <li><a href="functions_y.html#index_y"><span>y</span></a></li>
+ </ul>
+ </div>
+</div><!-- top -->
+<div class="contents">
+<div class="textblock">Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:</div>
+
+<h3><a class="anchor" id="index_s"></a>- s -</h3><ul>
+<li>safetyChkCfg
+: <a class="el" href="struct_dss___dctrl_region_safety_chk_cfg.html#aba94499a93c5fcbcf17aac03978b7692">Dss_DctrlRegionSafetyChkCfg</a>
+</li>
+<li>safetyChkEnable
+: <a class="el" href="struct_c_s_l___dss_safety_chk_cfg.html#aa0b0d70dc3629906f279027fe788d52f">CSL_DssSafetyChkCfg</a>
+</li>
+<li>safetyChkMode
+: <a class="el" href="struct_c_s_l___dss_safety_chk_cfg.html#ae4777be78384a09ac1e76eaa5ef925f6">CSL_DssSafetyChkCfg</a>
+</li>
+<li>safetyRegionEnable
+: <a class="el" href="struct_dss___dctrl_region_safety_chk_cfg.html#a1fce7a9f3745d77fc11cac0b45bd7ae0">Dss_DctrlRegionSafetyChkCfg</a>
+</li>
+<li>safetySignSeedVal
+: <a class="el" href="struct_dss___dctrl_vp_safety_chk_params.html#a673816f47183a4e18606ec70a01292ec">Dss_DctrlVpSafetyChkParams</a>
+, <a class="el" href="struct_dss___disp_pipe_safety_chk_params.html#a806bdd67b98f5ad01597e70ea7c2ce9c">Dss_DispPipeSafetyChkParams</a>
+</li>
+<li>safetyViolation
+: <a class="el" href="struct_dss___dctrl_vp_error_stats.html#a9a3c57243d5e6622e5bd4fff8ab95cd4">Dss_DctrlVpErrorStats</a>
+</li>
+<li>safetyViolationCount
+: <a class="el" href="struct_dss___disp_current_status.html#a2de8eed6f459af208ad159c02ebfbab0">Dss_DispCurrentStatus</a>
+</li>
+<li>scanFormat
+: <a class="el" href="struct_fvid2___format.html#a8caf0c6c3ab4f84dfcbfdc23958cc2fa">Fvid2_Format</a>
+, <a class="el" href="struct_fvid2___mode_info.html#a9f9211f1783dadb46fe4f24fe44bf205">Fvid2_ModeInfo</a>
+</li>
+<li>scEnable
+: <a class="el" href="struct_c_s_l___dss_vid_pipe_cfg.html#a558ff6d8e56438ce6f4e573a4e28cbc5">CSL_DssVidPipeCfg</a>
+</li>
+<li>scParams
+: <a class="el" href="struct_dss___disp_rt_params.html#ac3d56cce7d4cae6e8baee8e4784b77b6">Dss_DispRtParams</a>
+</li>
+<li>securityViolation
+: <a class="el" href="struct_dss___dctrl_vp_error_stats.html#a54b7302e5365b28c21f1678322860d3f">Dss_DctrlVpErrorStats</a>
+</li>
+<li>seedSelectEnable
+: <a class="el" href="struct_c_s_l___dss_safety_chk_cfg.html#a125d8cffdb194601754cf97d2a56c00b">CSL_DssSafetyChkCfg</a>
+</li>
+<li>selfRefreshControl
+: <a class="el" href="struct_c_s_l___dss_vid_pipe_dma_cfg.html#a59b2e750c7a9bb8ae5141829f98ccaed">CSL_DssVidPipeDmaCfg</a>
+</li>
+<li>selfRefreshEnable
+: <a class="el" href="struct_c_s_l___dss_vid_pipe_dma_cfg.html#aea2c8225738ca8620eb2af07690db604">CSL_DssVidPipeDmaCfg</a>
+</li>
+<li>socParams
+: <a class="el" href="struct_dss___init_params.html#aa8b798f4f03fcfb8bd59b04999d448a8">Dss_InitParams</a>
+</li>
+<li>standard
+: <a class="el" href="struct_dss___disp_create_status.html#ae7ddd0a663c8bcbaf6ddb9339f3257cf">Dss_DispCreateStatus</a>
+, <a class="el" href="struct_fvid2___mode_info.html#a8c27c6fb4272816c4708e23e66ea4c40">Fvid2_ModeInfo</a>
+</li>
+<li>startX
+: <a class="el" href="struct_fvid2___pos_config.html#a162f7d3ab12a8e049147ba10b1743b4f">Fvid2_PosConfig</a>
+</li>
+<li>startY
+: <a class="el" href="struct_fvid2___pos_config.html#a0bdff26f19f3571e6a76db9134644d38">Fvid2_PosConfig</a>
+</li>
+<li>status
+: <a class="el" href="struct_fvid2___frame.html#a16ee5088306c5a6bbf0126549ec005e1">Fvid2_Frame</a>
+</li>
+<li>subFrameInfo
+: <a class="el" href="struct_fvid2___frame.html#a97a3b5dcf677d9e81113358d18d45ffd">Fvid2_Frame</a>
+</li>
+<li>subFrameNum
+: <a class="el" href="struct_fvid2___sub_frame_info.html#a6139adfc91c58651f0344f79781319a4">Fvid2_SubFrameInfo</a>
+</li>
+<li>syncLost
+: <a class="el" href="struct_dss___dctrl_vp_error_stats.html#af272b85724ab489cac4f6ae36797dd15">Dss_DctrlVpErrorStats</a>
+</li>
+<li>syncLostCbFxn
+: <a class="el" href="struct_dss___dctrl_sync_lost_cb_params.html#a5c2ae7356eec440301d5ae9015e0f33a">Dss_DctrlSyncLostCbParams</a>
+</li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/functions_t.html b/packages/ti/drv/dss/docs/doxygen/html/functions_t.html
--- /dev/null
@@ -0,0 +1,100 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li class="current"><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="files.html"><span>Files</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow2" class="tabs2">
+ <ul class="tablist">
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li class="current"><a href="functions.html"><span>Data Fields</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow3" class="tabs2">
+ <ul class="tablist">
+ <li class="current"><a href="functions.html"><span>All</span></a></li>
+ <li><a href="functions_vars.html"><span>Variables</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow4" class="tabs3">
+ <ul class="tablist">
+ <li><a href="functions.html#index_a"><span>a</span></a></li>
+ <li><a href="functions_b.html#index_b"><span>b</span></a></li>
+ <li><a href="functions_c.html#index_c"><span>c</span></a></li>
+ <li><a href="functions_d.html#index_d"><span>d</span></a></li>
+ <li><a href="functions_e.html#index_e"><span>e</span></a></li>
+ <li><a href="functions_f.html#index_f"><span>f</span></a></li>
+ <li><a href="functions_g.html#index_g"><span>g</span></a></li>
+ <li><a href="functions_h.html#index_h"><span>h</span></a></li>
+ <li><a href="functions_i.html#index_i"><span>i</span></a></li>
+ <li><a href="functions_l.html#index_l"><span>l</span></a></li>
+ <li><a href="functions_m.html#index_m"><span>m</span></a></li>
+ <li><a href="functions_n.html#index_n"><span>n</span></a></li>
+ <li><a href="functions_o.html#index_o"><span>o</span></a></li>
+ <li><a href="functions_p.html#index_p"><span>p</span></a></li>
+ <li><a href="functions_q.html#index_q"><span>q</span></a></li>
+ <li><a href="functions_r.html#index_r"><span>r</span></a></li>
+ <li><a href="functions_s.html#index_s"><span>s</span></a></li>
+ <li class="current"><a href="functions_t.html#index_t"><span>t</span></a></li>
+ <li><a href="functions_u.html#index_u"><span>u</span></a></li>
+ <li><a href="functions_v.html#index_v"><span>v</span></a></li>
+ <li><a href="functions_w.html#index_w"><span>w</span></a></li>
+ <li><a href="functions_y.html#index_y"><span>y</span></a></li>
+ </ul>
+ </div>
+</div><!-- top -->
+<div class="contents">
+<div class="textblock">Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:</div>
+
+<h3><a class="anchor" id="index_t"></a>- t -</h3><ul>
+<li>tdmCycleFormat
+: <a class="el" href="struct_c_s_l___dss_vp_lcd_tdm_cfg.html#ae96d7a4d10f0aba11ae1fe050bbb4bae">CSL_DssVpLcdTdmCfg</a>
+</li>
+<li>tdmEnable
+: <a class="el" href="struct_c_s_l___dss_vp_lcd_tdm_cfg.html#abb0166aec4ae051ab0dd636877340902">CSL_DssVpLcdTdmCfg</a>
+</li>
+<li>tdmParallelMode
+: <a class="el" href="struct_c_s_l___dss_vp_lcd_tdm_cfg.html#aba88a2bb1746761f7406f66d04f5412a">CSL_DssVpLcdTdmCfg</a>
+</li>
+<li>tdmUnusedBitsLevel
+: <a class="el" href="struct_c_s_l___dss_vp_lcd_tdm_cfg.html#aa36d89a896199beac0c818f878730876">CSL_DssVpLcdTdmCfg</a>
+</li>
+<li>thresholdHigh
+: <a class="el" href="struct_c_s_l___dss_vid_pipe_m_flag_cfg.html#a9457e4916f1490c14f3b1bda1b56db8a">CSL_DssVidPipeMFlagCfg</a>
+</li>
+<li>thresholdLow
+: <a class="el" href="struct_c_s_l___dss_vid_pipe_m_flag_cfg.html#a10d1d9efb5a2b9c52b87f74b73c3b7ae">CSL_DssVidPipeMFlagCfg</a>
+</li>
+<li>thresholdValue
+: <a class="el" href="struct_c_s_l___dss_safety_chk_cfg.html#a2ab0df15747d286392ad903768bd82c1">CSL_DssSafetyChkCfg</a>
+</li>
+<li>timeStamp64
+: <a class="el" href="struct_fvid2___frame.html#a4563054a2f01febf65268dafa538f70c">Fvid2_Frame</a>
+</li>
+<li>transColorKeyMax
+: <a class="el" href="struct_c_s_l___dss_overlay_cfg.html#a30d4c1ba3e4ac96fd6618a450b95ee37">CSL_DssOverlayCfg</a>
+</li>
+<li>transColorKeyMin
+: <a class="el" href="struct_c_s_l___dss_overlay_cfg.html#a25f45603756892cc7bc3f43d840d94bb">CSL_DssOverlayCfg</a>
+</li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/functions_u.html b/packages/ti/drv/dss/docs/doxygen/html/functions_u.html
--- /dev/null
@@ -0,0 +1,76 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li class="current"><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="files.html"><span>Files</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow2" class="tabs2">
+ <ul class="tablist">
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li class="current"><a href="functions.html"><span>Data Fields</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow3" class="tabs2">
+ <ul class="tablist">
+ <li class="current"><a href="functions.html"><span>All</span></a></li>
+ <li><a href="functions_vars.html"><span>Variables</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow4" class="tabs3">
+ <ul class="tablist">
+ <li><a href="functions.html#index_a"><span>a</span></a></li>
+ <li><a href="functions_b.html#index_b"><span>b</span></a></li>
+ <li><a href="functions_c.html#index_c"><span>c</span></a></li>
+ <li><a href="functions_d.html#index_d"><span>d</span></a></li>
+ <li><a href="functions_e.html#index_e"><span>e</span></a></li>
+ <li><a href="functions_f.html#index_f"><span>f</span></a></li>
+ <li><a href="functions_g.html#index_g"><span>g</span></a></li>
+ <li><a href="functions_h.html#index_h"><span>h</span></a></li>
+ <li><a href="functions_i.html#index_i"><span>i</span></a></li>
+ <li><a href="functions_l.html#index_l"><span>l</span></a></li>
+ <li><a href="functions_m.html#index_m"><span>m</span></a></li>
+ <li><a href="functions_n.html#index_n"><span>n</span></a></li>
+ <li><a href="functions_o.html#index_o"><span>o</span></a></li>
+ <li><a href="functions_p.html#index_p"><span>p</span></a></li>
+ <li><a href="functions_q.html#index_q"><span>q</span></a></li>
+ <li><a href="functions_r.html#index_r"><span>r</span></a></li>
+ <li><a href="functions_s.html#index_s"><span>s</span></a></li>
+ <li><a href="functions_t.html#index_t"><span>t</span></a></li>
+ <li class="current"><a href="functions_u.html#index_u"><span>u</span></a></li>
+ <li><a href="functions_v.html#index_v"><span>v</span></a></li>
+ <li><a href="functions_w.html#index_w"><span>w</span></a></li>
+ <li><a href="functions_y.html#index_y"><span>y</span></a></li>
+ </ul>
+ </div>
+</div><!-- top -->
+<div class="contents">
+<div class="textblock">Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:</div>
+
+<h3><a class="anchor" id="index_u"></a>- u -</h3><ul>
+<li>underFlowCbFxn
+: <a class="el" href="struct_dss___disp_under_flow_cb_params.html#a60686aad091a413400037ab52ee52c5a">Dss_DispUnderFlowCbParams</a>
+</li>
+<li>underflowCount
+: <a class="el" href="struct_dss___disp_current_status.html#abe96e5d704939af373e8a533790d5875">Dss_DispCurrentStatus</a>
+</li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/functions_v.html b/packages/ti/drv/dss/docs/doxygen/html/functions_v.html
--- /dev/null
@@ -0,0 +1,110 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li class="current"><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="files.html"><span>Files</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow2" class="tabs2">
+ <ul class="tablist">
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li class="current"><a href="functions.html"><span>Data Fields</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow3" class="tabs2">
+ <ul class="tablist">
+ <li class="current"><a href="functions.html"><span>All</span></a></li>
+ <li><a href="functions_vars.html"><span>Variables</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow4" class="tabs3">
+ <ul class="tablist">
+ <li><a href="functions.html#index_a"><span>a</span></a></li>
+ <li><a href="functions_b.html#index_b"><span>b</span></a></li>
+ <li><a href="functions_c.html#index_c"><span>c</span></a></li>
+ <li><a href="functions_d.html#index_d"><span>d</span></a></li>
+ <li><a href="functions_e.html#index_e"><span>e</span></a></li>
+ <li><a href="functions_f.html#index_f"><span>f</span></a></li>
+ <li><a href="functions_g.html#index_g"><span>g</span></a></li>
+ <li><a href="functions_h.html#index_h"><span>h</span></a></li>
+ <li><a href="functions_i.html#index_i"><span>i</span></a></li>
+ <li><a href="functions_l.html#index_l"><span>l</span></a></li>
+ <li><a href="functions_m.html#index_m"><span>m</span></a></li>
+ <li><a href="functions_n.html#index_n"><span>n</span></a></li>
+ <li><a href="functions_o.html#index_o"><span>o</span></a></li>
+ <li><a href="functions_p.html#index_p"><span>p</span></a></li>
+ <li><a href="functions_q.html#index_q"><span>q</span></a></li>
+ <li><a href="functions_r.html#index_r"><span>r</span></a></li>
+ <li><a href="functions_s.html#index_s"><span>s</span></a></li>
+ <li><a href="functions_t.html#index_t"><span>t</span></a></li>
+ <li><a href="functions_u.html#index_u"><span>u</span></a></li>
+ <li class="current"><a href="functions_v.html#index_v"><span>v</span></a></li>
+ <li><a href="functions_w.html#index_w"><span>w</span></a></li>
+ <li><a href="functions_y.html#index_y"><span>y</span></a></li>
+ </ul>
+ </div>
+</div><!-- top -->
+<div class="contents">
+<div class="textblock">Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:</div>
+
+<h3><a class="anchor" id="index_v"></a>- v -</h3><ul>
+<li>vBackPorch
+: <a class="el" href="struct_c_s_l___dss_vp_lcd_blank_timing_cfg.html#aa47f7bea5a1b26d347984a25769e5424">CSL_DssVpLcdBlankTimingCfg</a>
+, <a class="el" href="struct_fvid2___mode_info.html#a9ade9b5bd46517cb5cfd0590585cbc33">Fvid2_ModeInfo</a>
+</li>
+<li>vc1Cfg
+: <a class="el" href="struct_dss___disp_params.html#a706397a3b18a877996fbf8f8276ab2e4">Dss_DispParams</a>
+</li>
+<li>vc1Enable
+: <a class="el" href="struct_c_s_l___dss_vid_pipe_v_c1_cfg.html#afd21865a4ea9a111674749d13e2aeec1">CSL_DssVidPipeVC1Cfg</a>
+</li>
+<li>vFrontPorch
+: <a class="el" href="struct_c_s_l___dss_vp_lcd_blank_timing_cfg.html#a0155b917c75ee07e575746a3e3e431d3">CSL_DssVpLcdBlankTimingCfg</a>
+, <a class="el" href="struct_fvid2___mode_info.html#a806ac4325f4edcaf2b7dca12a5051149">Fvid2_ModeInfo</a>
+</li>
+<li>videoIfWidth
+: <a class="el" href="struct_c_s_l___dss_vp_lcd_op_timing_cfg.html#a9967666ac6fea7f27b7fcfd6e4da55a6">CSL_DssVpLcdOpTimingCfg</a>
+</li>
+<li>vpId
+: <a class="el" href="struct_dss___dctrl_adv_vp_params.html#afd01ce9227b77bec352c157f1105b622">Dss_DctrlAdvVpParams</a>
+, <a class="el" href="struct_dss___dctrl_lcd_blank_timing_params.html#ae1b052eccedf552786588d1c7ae16172">Dss_DctrlLcdBlankTimingParams</a>
+, <a class="el" href="struct_dss___dctrl_oldi_params.html#a05de5db50e555596e3ec6402b2342bb4">Dss_DctrlOldiParams</a>
+, <a class="el" href="struct_dss___dctrl_sync_lost_cb_params.html#a61ef10a6d3eba7bc313a97aa0030a235">Dss_DctrlSyncLostCbParams</a>
+, <a class="el" href="struct_dss___dctrl_vp_csc_coeff.html#a203077028ae50d9ca4db3c325d40dc1b">Dss_DctrlVpCscCoeff</a>
+, <a class="el" href="struct_dss___dctrl_vp_error_stats.html#a557f21aa6cf21d93cbb30621de72ecb0">Dss_DctrlVpErrorStats</a>
+, <a class="el" href="struct_dss___dctrl_vp_params.html#aa76e94e775ed4a9146ebc8fc937c904e">Dss_DctrlVpParams</a>
+, <a class="el" href="struct_dss___dctrl_vp_safety_chk_params.html#a034f526bd2e786a118ebb9a84e5c5cb8">Dss_DctrlVpSafetyChkParams</a>
+</li>
+<li>vpSafetyChkCfg
+: <a class="el" href="struct_dss___dctrl_vp_safety_chk_params.html#a79a3554cac97f602e452fc5ae125288e">Dss_DctrlVpSafetyChkParams</a>
+</li>
+<li>vsPolarity
+: <a class="el" href="struct_c_s_l___dss_vp_lcd_signal_polarity_cfg.html#af04cf78189cce9f85c441bf4e22f23d7">CSL_DssVpLcdSignalPolarityCfg</a>
+</li>
+<li>vSyncGated
+: <a class="el" href="struct_c_s_l___dss_vp_lcd_adv_signal_cfg.html#a8ff089c8259760a24199389c68519338">CSL_DssVpLcdAdvSignalCfg</a>
+</li>
+<li>vSyncLen
+: <a class="el" href="struct_c_s_l___dss_vp_lcd_blank_timing_cfg.html#aac23b4702301fa2aa6a64ac5299fd2ba">CSL_DssVpLcdBlankTimingCfg</a>
+, <a class="el" href="struct_fvid2___mode_info.html#a2b756eece94e9a720028ece8d50991b3">Fvid2_ModeInfo</a>
+</li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/functions_vars.html b/packages/ti/drv/dss/docs/doxygen/html/functions_vars.html
--- /dev/null
@@ -0,0 +1,93 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Data Fields - Variables</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li class="current"><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="files.html"><span>Files</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow2" class="tabs2">
+ <ul class="tablist">
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li class="current"><a href="functions.html"><span>Data Fields</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow3" class="tabs2">
+ <ul class="tablist">
+ <li><a href="functions.html"><span>All</span></a></li>
+ <li class="current"><a href="functions_vars.html"><span>Variables</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow4" class="tabs3">
+ <ul class="tablist">
+ <li class="current"><a href="functions_vars.html#index_a"><span>a</span></a></li>
+ <li><a href="functions_vars_b.html#index_b"><span>b</span></a></li>
+ <li><a href="functions_vars_c.html#index_c"><span>c</span></a></li>
+ <li><a href="functions_vars_d.html#index_d"><span>d</span></a></li>
+ <li><a href="functions_vars_e.html#index_e"><span>e</span></a></li>
+ <li><a href="functions_vars_f.html#index_f"><span>f</span></a></li>
+ <li><a href="functions_vars_g.html#index_g"><span>g</span></a></li>
+ <li><a href="functions_vars_h.html#index_h"><span>h</span></a></li>
+ <li><a href="functions_vars_i.html#index_i"><span>i</span></a></li>
+ <li><a href="functions_vars_l.html#index_l"><span>l</span></a></li>
+ <li><a href="functions_vars_m.html#index_m"><span>m</span></a></li>
+ <li><a href="functions_vars_n.html#index_n"><span>n</span></a></li>
+ <li><a href="functions_vars_o.html#index_o"><span>o</span></a></li>
+ <li><a href="functions_vars_p.html#index_p"><span>p</span></a></li>
+ <li><a href="functions_vars_q.html#index_q"><span>q</span></a></li>
+ <li><a href="functions_vars_r.html#index_r"><span>r</span></a></li>
+ <li><a href="functions_vars_s.html#index_s"><span>s</span></a></li>
+ <li><a href="functions_vars_t.html#index_t"><span>t</span></a></li>
+ <li><a href="functions_vars_u.html#index_u"><span>u</span></a></li>
+ <li><a href="functions_vars_v.html#index_v"><span>v</span></a></li>
+ <li><a href="functions_vars_w.html#index_w"><span>w</span></a></li>
+ <li><a href="functions_vars_y.html#index_y"><span>y</span></a></li>
+ </ul>
+ </div>
+</div><!-- top -->
+<div class="contents">
+ 
+
+<h3><a class="anchor" id="index_a"></a>- a -</h3><ul>
+<li>acB
+: <a class="el" href="struct_c_s_l___dss_vp_lcd_adv_signal_cfg.html#acff326382d610c9f1680dae1e897d1c2">CSL_DssVpLcdAdvSignalCfg</a>
+</li>
+<li>acBI
+: <a class="el" href="struct_c_s_l___dss_vp_lcd_adv_signal_cfg.html#a19de0b442f322232367aeb005332693a">CSL_DssVpLcdAdvSignalCfg</a>
+</li>
+<li>actVidPolarity
+: <a class="el" href="struct_c_s_l___dss_vp_lcd_signal_polarity_cfg.html#aba814560abdf027968da571705fe6873">CSL_DssVpLcdSignalPolarityCfg</a>
+</li>
+<li>addr
+: <a class="el" href="struct_fvid2___frame.html#ad9e33643cd628e7432da408ad6565305">Fvid2_Frame</a>
+</li>
+<li>alphaCfg
+: <a class="el" href="struct_dss___disp_params.html#a3a34d97aedf973f3eeaca5d9469667ca">Dss_DispParams</a>
+</li>
+<li>appData
+: <a class="el" href="struct_dss___dctrl_sync_lost_cb_params.html#a018ed0ef2544b8f52207dc5799238854">Dss_DctrlSyncLostCbParams</a>
+, <a class="el" href="struct_fvid2___frame.html#a071f9e8c68e831b029a17a342da7bce8">Fvid2_Frame</a>
+, <a class="el" href="struct_fvid2___frame_list.html#a3d40464eb4d1129eae2c8a95d65a5ec5">Fvid2_FrameList</a>
+</li>
+<li>arbitration
+: <a class="el" href="struct_c_s_l___dss_vid_pipe_dma_cfg.html#ae13f5377c727660f54f27d1061a4020b">CSL_DssVidPipeDmaCfg</a>
+</li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/functions_vars_b.html b/packages/ti/drv/dss/docs/doxygen/html/functions_vars_b.html
--- /dev/null
@@ -0,0 +1,103 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Data Fields - Variables</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li class="current"><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="files.html"><span>Files</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow2" class="tabs2">
+ <ul class="tablist">
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li class="current"><a href="functions.html"><span>Data Fields</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow3" class="tabs2">
+ <ul class="tablist">
+ <li><a href="functions.html"><span>All</span></a></li>
+ <li class="current"><a href="functions_vars.html"><span>Variables</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow4" class="tabs3">
+ <ul class="tablist">
+ <li><a href="functions_vars.html#index_a"><span>a</span></a></li>
+ <li class="current"><a href="functions_vars_b.html#index_b"><span>b</span></a></li>
+ <li><a href="functions_vars_c.html#index_c"><span>c</span></a></li>
+ <li><a href="functions_vars_d.html#index_d"><span>d</span></a></li>
+ <li><a href="functions_vars_e.html#index_e"><span>e</span></a></li>
+ <li><a href="functions_vars_f.html#index_f"><span>f</span></a></li>
+ <li><a href="functions_vars_g.html#index_g"><span>g</span></a></li>
+ <li><a href="functions_vars_h.html#index_h"><span>h</span></a></li>
+ <li><a href="functions_vars_i.html#index_i"><span>i</span></a></li>
+ <li><a href="functions_vars_l.html#index_l"><span>l</span></a></li>
+ <li><a href="functions_vars_m.html#index_m"><span>m</span></a></li>
+ <li><a href="functions_vars_n.html#index_n"><span>n</span></a></li>
+ <li><a href="functions_vars_o.html#index_o"><span>o</span></a></li>
+ <li><a href="functions_vars_p.html#index_p"><span>p</span></a></li>
+ <li><a href="functions_vars_q.html#index_q"><span>q</span></a></li>
+ <li><a href="functions_vars_r.html#index_r"><span>r</span></a></li>
+ <li><a href="functions_vars_s.html#index_s"><span>s</span></a></li>
+ <li><a href="functions_vars_t.html#index_t"><span>t</span></a></li>
+ <li><a href="functions_vars_u.html#index_u"><span>u</span></a></li>
+ <li><a href="functions_vars_v.html#index_v"><span>v</span></a></li>
+ <li><a href="functions_vars_w.html#index_w"><span>w</span></a></li>
+ <li><a href="functions_vars_y.html#index_y"><span>y</span></a></li>
+ </ul>
+ </div>
+</div><!-- top -->
+<div class="contents">
+ 
+
+<h3><a class="anchor" id="index_b"></a>- b -</h3><ul>
+<li>backGroundColor
+: <a class="el" href="struct_c_s_l___dss_overlay_cfg.html#a6cd0a80d721ebd8316233c7d1a0eff8a">CSL_DssOverlayCfg</a>
+</li>
+<li>bitAlignPixel1Cycle0
+: <a class="el" href="struct_c_s_l___dss_vp_lcd_tdm_cfg.html#abab9fab501255acd87c1ab71e02df53a">CSL_DssVpLcdTdmCfg</a>
+</li>
+<li>bitAlignPixel1Cycle1
+: <a class="el" href="struct_c_s_l___dss_vp_lcd_tdm_cfg.html#a62a5d33c4b5cdaf4a1837a9062319b8d">CSL_DssVpLcdTdmCfg</a>
+</li>
+<li>bitAlignPixel1Cycle2
+: <a class="el" href="struct_c_s_l___dss_vp_lcd_tdm_cfg.html#a1fa26016fc933f54738aebc327fa8cac">CSL_DssVpLcdTdmCfg</a>
+</li>
+<li>bitAlignPixel2Cycle0
+: <a class="el" href="struct_c_s_l___dss_vp_lcd_tdm_cfg.html#aa23d4e0d384e3af3988eab00332b626f">CSL_DssVpLcdTdmCfg</a>
+</li>
+<li>bitAlignPixel2Cycle1
+: <a class="el" href="struct_c_s_l___dss_vp_lcd_tdm_cfg.html#a14eac5468c7e383536d68992ccbdbf69">CSL_DssVpLcdTdmCfg</a>
+</li>
+<li>bitAlignPixel2Cycle2
+: <a class="el" href="struct_c_s_l___dss_vp_lcd_tdm_cfg.html#ada6dacedb1a801fe5f91396b7252a719">CSL_DssVpLcdTdmCfg</a>
+</li>
+<li>bufHighThreshold
+: <a class="el" href="struct_c_s_l___dss_vid_pipe_dma_cfg.html#ac65a5085dbe2dd974d91cca54b9bfca7">CSL_DssVidPipeDmaCfg</a>
+</li>
+<li>bufLowThreshold
+: <a class="el" href="struct_c_s_l___dss_vid_pipe_dma_cfg.html#ab6f24c128746dac326d90a96a87bb220">CSL_DssVidPipeDmaCfg</a>
+</li>
+<li>bufPreloadControl
+: <a class="el" href="struct_c_s_l___dss_vid_pipe_dma_cfg.html#af7f5f21d2d1b24e927fcdb3e8f05c945">CSL_DssVidPipeDmaCfg</a>
+</li>
+<li>bufPrgmCbFxn
+: <a class="el" href="struct_dss___disp_buf_prgm_cb_params.html#a44001b7a082865cef75594b3cb8853b6">Dss_DispBufPrgmCbParams</a>
+</li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/functions_vars_c.html b/packages/ti/drv/dss/docs/doxygen/html/functions_vars_c.html
--- /dev/null
@@ -0,0 +1,142 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Data Fields - Variables</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li class="current"><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="files.html"><span>Files</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow2" class="tabs2">
+ <ul class="tablist">
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li class="current"><a href="functions.html"><span>Data Fields</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow3" class="tabs2">
+ <ul class="tablist">
+ <li><a href="functions.html"><span>All</span></a></li>
+ <li class="current"><a href="functions_vars.html"><span>Variables</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow4" class="tabs3">
+ <ul class="tablist">
+ <li><a href="functions_vars.html#index_a"><span>a</span></a></li>
+ <li><a href="functions_vars_b.html#index_b"><span>b</span></a></li>
+ <li class="current"><a href="functions_vars_c.html#index_c"><span>c</span></a></li>
+ <li><a href="functions_vars_d.html#index_d"><span>d</span></a></li>
+ <li><a href="functions_vars_e.html#index_e"><span>e</span></a></li>
+ <li><a href="functions_vars_f.html#index_f"><span>f</span></a></li>
+ <li><a href="functions_vars_g.html#index_g"><span>g</span></a></li>
+ <li><a href="functions_vars_h.html#index_h"><span>h</span></a></li>
+ <li><a href="functions_vars_i.html#index_i"><span>i</span></a></li>
+ <li><a href="functions_vars_l.html#index_l"><span>l</span></a></li>
+ <li><a href="functions_vars_m.html#index_m"><span>m</span></a></li>
+ <li><a href="functions_vars_n.html#index_n"><span>n</span></a></li>
+ <li><a href="functions_vars_o.html#index_o"><span>o</span></a></li>
+ <li><a href="functions_vars_p.html#index_p"><span>p</span></a></li>
+ <li><a href="functions_vars_q.html#index_q"><span>q</span></a></li>
+ <li><a href="functions_vars_r.html#index_r"><span>r</span></a></li>
+ <li><a href="functions_vars_s.html#index_s"><span>s</span></a></li>
+ <li><a href="functions_vars_t.html#index_t"><span>t</span></a></li>
+ <li><a href="functions_vars_u.html#index_u"><span>u</span></a></li>
+ <li><a href="functions_vars_v.html#index_v"><span>v</span></a></li>
+ <li><a href="functions_vars_w.html#index_w"><span>w</span></a></li>
+ <li><a href="functions_vars_y.html#index_y"><span>y</span></a></li>
+ </ul>
+ </div>
+</div><!-- top -->
+<div class="contents">
+ 
+
+<h3><a class="anchor" id="index_c"></a>- c -</h3><ul>
+<li>c00
+: <a class="el" href="struct_c_s_l___dss_csc_coeff.html#ac7b7297b4e02573287df1f9f35d8aca2">CSL_DssCscCoeff</a>
+</li>
+<li>c01
+: <a class="el" href="struct_c_s_l___dss_csc_coeff.html#a5a75499dfeeb44b76d415bb9bbe98d8d">CSL_DssCscCoeff</a>
+</li>
+<li>c02
+: <a class="el" href="struct_c_s_l___dss_csc_coeff.html#a19b693b93d0cf75adb2fb68117695d8a">CSL_DssCscCoeff</a>
+</li>
+<li>c10
+: <a class="el" href="struct_c_s_l___dss_csc_coeff.html#aa669cc1212525291737f9bc74d0153ce">CSL_DssCscCoeff</a>
+</li>
+<li>c11
+: <a class="el" href="struct_c_s_l___dss_csc_coeff.html#a83ecbca550770735501789f7afcdf58e">CSL_DssCscCoeff</a>
+</li>
+<li>c12
+: <a class="el" href="struct_c_s_l___dss_csc_coeff.html#a8e8879c108c96cfb3ddaddc04920e09e">CSL_DssCscCoeff</a>
+</li>
+<li>c20
+: <a class="el" href="struct_c_s_l___dss_csc_coeff.html#ae191fedd2933af25a14134968c36cc4e">CSL_DssCscCoeff</a>
+</li>
+<li>c21
+: <a class="el" href="struct_c_s_l___dss_csc_coeff.html#a254195b0c504a070d1f3965b252a11f3">CSL_DssCscCoeff</a>
+</li>
+<li>c22
+: <a class="el" href="struct_c_s_l___dss_csc_coeff.html#ab4f1a6d7535f7b7c3cd9318a8d4147a4">CSL_DssCscCoeff</a>
+</li>
+<li>cbaCfg
+: <a class="el" href="struct_dss___dctrl_global_dss_params.html#a28fb2f34eb97b5d4d8980bcbb6135f8c">Dss_DctrlGlobalDssParams</a>
+</li>
+<li>ccsFormat
+: <a class="el" href="struct_fvid2___format.html#aff43b4f3b6ebdc15e84c1a0c4e55fd14">Fvid2_Format</a>
+</li>
+<li>chNum
+: <a class="el" href="struct_fvid2___format.html#a1f5ea464b31c5f7e77323e8f82c4d5e8">Fvid2_Format</a>
+, <a class="el" href="struct_fvid2___frame.html#a550ee00873923f1cc53905dfa0911918">Fvid2_Frame</a>
+</li>
+<li>clutdata
+: <a class="el" href="struct_c_s_l___dss_vid_pipe_cfg.html#a7ce9ca51a30b95aa4542c412a06f3fe8">CSL_DssVidPipeCfg</a>
+</li>
+<li>colorbarEnable
+: <a class="el" href="struct_dss___dctrl_overlay_params.html#afad2eae0981ea3cbf8438264247c01b1">Dss_DctrlOverlayParams</a>
+</li>
+<li>colorKeyEnable
+: <a class="el" href="struct_c_s_l___dss_overlay_cfg.html#aaeb04d69fcf39faa7ac2e8dff0dd57be">CSL_DssOverlayCfg</a>
+</li>
+<li>colorKeySel
+: <a class="el" href="struct_c_s_l___dss_overlay_cfg.html#a04994324fc3e3290d5a2384b1643abc4">CSL_DssOverlayCfg</a>
+</li>
+<li>cropHeight
+: <a class="el" href="struct_fvid2___crop_config.html#a81496ac240b08840f12474d0c53958cd">Fvid2_CropConfig</a>
+</li>
+<li>cropStartX
+: <a class="el" href="struct_fvid2___crop_config.html#a0312b61252f23269919008c8c2a15450">Fvid2_CropConfig</a>
+</li>
+<li>cropStartY
+: <a class="el" href="struct_fvid2___crop_config.html#a35cc1e45b5914ed02374fc1b0400b740">Fvid2_CropConfig</a>
+</li>
+<li>cropWidth
+: <a class="el" href="struct_fvid2___crop_config.html#a45cf01dd1c4d0f9e069432d3ea467c03">Fvid2_CropConfig</a>
+</li>
+<li>cscCoeff
+: <a class="el" href="struct_dss___dctrl_vp_csc_coeff.html#ae178eec62d495ae8ec2e0e5cc5e70e65">Dss_DctrlVpCscCoeff</a>
+</li>
+<li>cscPos
+: <a class="el" href="struct_dss___dctrl_vp_csc_coeff.html#ae353e0bd890dee8e7a8eeddf408ffc64">Dss_DctrlVpCscCoeff</a>
+</li>
+<li>cscRange
+: <a class="el" href="struct_c_s_l___dss_csc_coeff.html#aaa6a45f2e780f4d62f57fd3c5e3b73ee">CSL_DssCscCoeff</a>
+, <a class="el" href="struct_c_s_l___dss_vid_pipe_cfg.html#a69fdfed089bd4ee2daea72c8e40a98f2">CSL_DssVidPipeCfg</a>
+, <a class="el" href="struct_c_s_l___dss_vp_lcd_op_timing_cfg.html#a1e927fefea2d081753712d11f440731d">CSL_DssVpLcdOpTimingCfg</a>
+</li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/functions_vars_d.html b/packages/ti/drv/dss/docs/doxygen/html/functions_vars_d.html
--- /dev/null
@@ -0,0 +1,103 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Data Fields - Variables</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li class="current"><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="files.html"><span>Files</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow2" class="tabs2">
+ <ul class="tablist">
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li class="current"><a href="functions.html"><span>Data Fields</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow3" class="tabs2">
+ <ul class="tablist">
+ <li><a href="functions.html"><span>All</span></a></li>
+ <li class="current"><a href="functions_vars.html"><span>Variables</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow4" class="tabs3">
+ <ul class="tablist">
+ <li><a href="functions_vars.html#index_a"><span>a</span></a></li>
+ <li><a href="functions_vars_b.html#index_b"><span>b</span></a></li>
+ <li><a href="functions_vars_c.html#index_c"><span>c</span></a></li>
+ <li class="current"><a href="functions_vars_d.html#index_d"><span>d</span></a></li>
+ <li><a href="functions_vars_e.html#index_e"><span>e</span></a></li>
+ <li><a href="functions_vars_f.html#index_f"><span>f</span></a></li>
+ <li><a href="functions_vars_g.html#index_g"><span>g</span></a></li>
+ <li><a href="functions_vars_h.html#index_h"><span>h</span></a></li>
+ <li><a href="functions_vars_i.html#index_i"><span>i</span></a></li>
+ <li><a href="functions_vars_l.html#index_l"><span>l</span></a></li>
+ <li><a href="functions_vars_m.html#index_m"><span>m</span></a></li>
+ <li><a href="functions_vars_n.html#index_n"><span>n</span></a></li>
+ <li><a href="functions_vars_o.html#index_o"><span>o</span></a></li>
+ <li><a href="functions_vars_p.html#index_p"><span>p</span></a></li>
+ <li><a href="functions_vars_q.html#index_q"><span>q</span></a></li>
+ <li><a href="functions_vars_r.html#index_r"><span>r</span></a></li>
+ <li><a href="functions_vars_s.html#index_s"><span>s</span></a></li>
+ <li><a href="functions_vars_t.html#index_t"><span>t</span></a></li>
+ <li><a href="functions_vars_u.html#index_u"><span>u</span></a></li>
+ <li><a href="functions_vars_v.html#index_v"><span>v</span></a></li>
+ <li><a href="functions_vars_w.html#index_w"><span>w</span></a></li>
+ <li><a href="functions_vars_y.html#index_y"><span>y</span></a></li>
+ </ul>
+ </div>
+</div><!-- top -->
+<div class="contents">
+ 
+
+<h3><a class="anchor" id="index_d"></a>- d -</h3><ul>
+<li>dataFormat
+: <a class="el" href="struct_dss___frame_rt_params.html#ae6280dd0f1eabe05ba89d7f81d9c2975">Dss_FrameRtParams</a>
+, <a class="el" href="struct_fvid2___format.html#abb9f60d4fcdab6fbfda7a2c92cbfce53">Fvid2_Format</a>
+</li>
+<li>deltaLinesPerPanel
+: <a class="el" href="struct_c_s_l___dss_vp_lcd_op_timing_cfg.html#a4d8eec6b33ff2de5a769235aee2a2acb">CSL_DssVpLcdOpTimingCfg</a>
+</li>
+<li>dequeueCount
+: <a class="el" href="struct_dss___disp_current_status.html#ab165778deecd58c934909dcf35571b03">Dss_DispCurrentStatus</a>
+</li>
+<li>dispFrmCount
+: <a class="el" href="struct_dss___disp_current_status.html#ad530ba229be8e4fab5d0dcdfcfdffc75">Dss_DispCurrentStatus</a>
+</li>
+<li>dispHeight
+: <a class="el" href="struct_dss___disp_create_status.html#a077cf565fe573dff029d69cf3d7e9bea">Dss_DispCreateStatus</a>
+</li>
+<li>dispWidth
+: <a class="el" href="struct_dss___disp_create_status.html#aee56647a1d80812a6b4e6ceb62bcf568">Dss_DispCreateStatus</a>
+</li>
+<li>dmaCfg
+: <a class="el" href="struct_dss___disp_params.html#a80d78d43a05b928cf2b6bd7c009f4ae6">Dss_DispParams</a>
+</li>
+<li>drvData
+: <a class="el" href="struct_fvid2___frame.html#a5e23564dddc24970d5a08ec7f91ac387">Fvid2_Frame</a>
+, <a class="el" href="struct_fvid2___frame_list.html#ae92f871d92e87591634aa6fbf2db7a9c">Fvid2_FrameList</a>
+</li>
+<li>dssCommonRegionId
+: <a class="el" href="struct_dss___irq_params.html#ad0b38c26a215ee1ef19d7a7dd31fdc59">Dss_IrqParams</a>
+</li>
+<li>dvoFormat
+: <a class="el" href="struct_c_s_l___dss_vp_lcd_op_timing_cfg.html#aaeadccfcb9ea48ce2989afa051909b2e">CSL_DssVpLcdOpTimingCfg</a>
+, <a class="el" href="struct_dss___dctrl_lcd_blank_timing_params.html#a7d98e8797f58bb69e6a0f639e749bb97">Dss_DctrlLcdBlankTimingParams</a>
+</li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/functions_vars_e.html b/packages/ti/drv/dss/docs/doxygen/html/functions_vars_e.html
--- /dev/null
@@ -0,0 +1,73 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Data Fields - Variables</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li class="current"><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="files.html"><span>Files</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow2" class="tabs2">
+ <ul class="tablist">
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li class="current"><a href="functions.html"><span>Data Fields</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow3" class="tabs2">
+ <ul class="tablist">
+ <li><a href="functions.html"><span>All</span></a></li>
+ <li class="current"><a href="functions_vars.html"><span>Variables</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow4" class="tabs3">
+ <ul class="tablist">
+ <li><a href="functions_vars.html#index_a"><span>a</span></a></li>
+ <li><a href="functions_vars_b.html#index_b"><span>b</span></a></li>
+ <li><a href="functions_vars_c.html#index_c"><span>c</span></a></li>
+ <li><a href="functions_vars_d.html#index_d"><span>d</span></a></li>
+ <li class="current"><a href="functions_vars_e.html#index_e"><span>e</span></a></li>
+ <li><a href="functions_vars_f.html#index_f"><span>f</span></a></li>
+ <li><a href="functions_vars_g.html#index_g"><span>g</span></a></li>
+ <li><a href="functions_vars_h.html#index_h"><span>h</span></a></li>
+ <li><a href="functions_vars_i.html#index_i"><span>i</span></a></li>
+ <li><a href="functions_vars_l.html#index_l"><span>l</span></a></li>
+ <li><a href="functions_vars_m.html#index_m"><span>m</span></a></li>
+ <li><a href="functions_vars_n.html#index_n"><span>n</span></a></li>
+ <li><a href="functions_vars_o.html#index_o"><span>o</span></a></li>
+ <li><a href="functions_vars_p.html#index_p"><span>p</span></a></li>
+ <li><a href="functions_vars_q.html#index_q"><span>q</span></a></li>
+ <li><a href="functions_vars_r.html#index_r"><span>r</span></a></li>
+ <li><a href="functions_vars_s.html#index_s"><span>s</span></a></li>
+ <li><a href="functions_vars_t.html#index_t"><span>t</span></a></li>
+ <li><a href="functions_vars_u.html#index_u"><span>u</span></a></li>
+ <li><a href="functions_vars_v.html#index_v"><span>v</span></a></li>
+ <li><a href="functions_vars_w.html#index_w"><span>w</span></a></li>
+ <li><a href="functions_vars_y.html#index_y"><span>y</span></a></li>
+ </ul>
+ </div>
+</div><!-- top -->
+<div class="contents">
+ 
+
+<h3><a class="anchor" id="index_e"></a>- e -</h3><ul>
+<li>edgeInfo
+: <a class="el" href="struct_dss___dctrl_path_info.html#a8f2ebc06f24bf439b9b82bed9c70b8fd">Dss_DctrlPathInfo</a>
+</li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/functions_vars_f.html b/packages/ti/drv/dss/docs/doxygen/html/functions_vars_f.html
--- /dev/null
@@ -0,0 +1,91 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Data Fields - Variables</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li class="current"><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="files.html"><span>Files</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow2" class="tabs2">
+ <ul class="tablist">
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li class="current"><a href="functions.html"><span>Data Fields</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow3" class="tabs2">
+ <ul class="tablist">
+ <li><a href="functions.html"><span>All</span></a></li>
+ <li class="current"><a href="functions_vars.html"><span>Variables</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow4" class="tabs3">
+ <ul class="tablist">
+ <li><a href="functions_vars.html#index_a"><span>a</span></a></li>
+ <li><a href="functions_vars_b.html#index_b"><span>b</span></a></li>
+ <li><a href="functions_vars_c.html#index_c"><span>c</span></a></li>
+ <li><a href="functions_vars_d.html#index_d"><span>d</span></a></li>
+ <li><a href="functions_vars_e.html#index_e"><span>e</span></a></li>
+ <li class="current"><a href="functions_vars_f.html#index_f"><span>f</span></a></li>
+ <li><a href="functions_vars_g.html#index_g"><span>g</span></a></li>
+ <li><a href="functions_vars_h.html#index_h"><span>h</span></a></li>
+ <li><a href="functions_vars_i.html#index_i"><span>i</span></a></li>
+ <li><a href="functions_vars_l.html#index_l"><span>l</span></a></li>
+ <li><a href="functions_vars_m.html#index_m"><span>m</span></a></li>
+ <li><a href="functions_vars_n.html#index_n"><span>n</span></a></li>
+ <li><a href="functions_vars_o.html#index_o"><span>o</span></a></li>
+ <li><a href="functions_vars_p.html#index_p"><span>p</span></a></li>
+ <li><a href="functions_vars_q.html#index_q"><span>q</span></a></li>
+ <li><a href="functions_vars_r.html#index_r"><span>r</span></a></li>
+ <li><a href="functions_vars_s.html#index_s"><span>s</span></a></li>
+ <li><a href="functions_vars_t.html#index_t"><span>t</span></a></li>
+ <li><a href="functions_vars_u.html#index_u"><span>u</span></a></li>
+ <li><a href="functions_vars_v.html#index_v"><span>v</span></a></li>
+ <li><a href="functions_vars_w.html#index_w"><span>w</span></a></li>
+ <li><a href="functions_vars_y.html#index_y"><span>y</span></a></li>
+ </ul>
+ </div>
+</div><!-- top -->
+<div class="contents">
+ 
+
+<h3><a class="anchor" id="index_f"></a>- f -</h3><ul>
+<li>fid
+: <a class="el" href="struct_fvid2___frame.html#a953491d1babc17d72cb892ae22b0b2a0">Fvid2_Frame</a>
+</li>
+<li>fidFirst
+: <a class="el" href="struct_c_s_l___dss_vp_lcd_op_timing_cfg.html#a5348fe79a6dc369023b8f569b36d731b">CSL_DssVpLcdOpTimingCfg</a>
+</li>
+<li>fieldMerged
+: <a class="el" href="struct_fvid2___format.html#a58cee5e76605bdd4a691c8094f719f8d">Fvid2_Format</a>
+</li>
+<li>flipType
+: <a class="el" href="struct_c_s_l___dss_vid_pipe_cfg.html#abebbaaf4c35c0d96cdcc9fdc9300de28">CSL_DssVidPipeCfg</a>
+</li>
+<li>fps
+: <a class="el" href="struct_fvid2___mode_info.html#ad507776704ccbdc7380978d8979777f9">Fvid2_ModeInfo</a>
+</li>
+<li>frames
+: <a class="el" href="struct_fvid2___frame_list.html#ae772ff66598716fe46b8aa687240414c">Fvid2_FrameList</a>
+</li>
+<li>frameSkip
+: <a class="el" href="struct_c_s_l___dss_safety_chk_cfg.html#a6ed2ecbafc577cc70efdb2ba75f93142">CSL_DssSafetyChkCfg</a>
+</li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/functions_vars_g.html b/packages/ti/drv/dss/docs/doxygen/html/functions_vars_g.html
--- /dev/null
@@ -0,0 +1,89 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Data Fields - Variables</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li class="current"><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="files.html"><span>Files</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow2" class="tabs2">
+ <ul class="tablist">
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li class="current"><a href="functions.html"><span>Data Fields</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow3" class="tabs2">
+ <ul class="tablist">
+ <li><a href="functions.html"><span>All</span></a></li>
+ <li class="current"><a href="functions_vars.html"><span>Variables</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow4" class="tabs3">
+ <ul class="tablist">
+ <li><a href="functions_vars.html#index_a"><span>a</span></a></li>
+ <li><a href="functions_vars_b.html#index_b"><span>b</span></a></li>
+ <li><a href="functions_vars_c.html#index_c"><span>c</span></a></li>
+ <li><a href="functions_vars_d.html#index_d"><span>d</span></a></li>
+ <li><a href="functions_vars_e.html#index_e"><span>e</span></a></li>
+ <li><a href="functions_vars_f.html#index_f"><span>f</span></a></li>
+ <li class="current"><a href="functions_vars_g.html#index_g"><span>g</span></a></li>
+ <li><a href="functions_vars_h.html#index_h"><span>h</span></a></li>
+ <li><a href="functions_vars_i.html#index_i"><span>i</span></a></li>
+ <li><a href="functions_vars_l.html#index_l"><span>l</span></a></li>
+ <li><a href="functions_vars_m.html#index_m"><span>m</span></a></li>
+ <li><a href="functions_vars_n.html#index_n"><span>n</span></a></li>
+ <li><a href="functions_vars_o.html#index_o"><span>o</span></a></li>
+ <li><a href="functions_vars_p.html#index_p"><span>p</span></a></li>
+ <li><a href="functions_vars_q.html#index_q"><span>q</span></a></li>
+ <li><a href="functions_vars_r.html#index_r"><span>r</span></a></li>
+ <li><a href="functions_vars_s.html#index_s"><span>s</span></a></li>
+ <li><a href="functions_vars_t.html#index_t"><span>t</span></a></li>
+ <li><a href="functions_vars_u.html#index_u"><span>u</span></a></li>
+ <li><a href="functions_vars_v.html#index_v"><span>v</span></a></li>
+ <li><a href="functions_vars_w.html#index_w"><span>w</span></a></li>
+ <li><a href="functions_vars_y.html#index_y"><span>y</span></a></li>
+ </ul>
+ </div>
+</div><!-- top -->
+<div class="contents">
+ 
+
+<h3><a class="anchor" id="index_g"></a>- g -</h3><ul>
+<li>gammaData
+: <a class="el" href="struct_c_s_l___dss_vp_gamma_cfg.html#abe6f3edc0a2132f4c12e7a879069bca5">CSL_DssVpGammaCfg</a>
+</li>
+<li>gammaEnable
+: <a class="el" href="struct_c_s_l___dss_vid_pipe_cfg.html#a5e9c6107d03fb837bc74a71538c5ed3e">CSL_DssVidPipeCfg</a>
+, <a class="el" href="struct_c_s_l___dss_vp_gamma_cfg.html#a64733ec49dec684d60ce3fe608323e90">CSL_DssVpGammaCfg</a>
+</li>
+<li>globalAlpha
+: <a class="el" href="struct_c_s_l___dss_vid_pipe_alpha_cfg.html#af1657cd739f1bde94ae85e504c3e5af6">CSL_DssVidPipeAlphaCfg</a>
+</li>
+<li>globalMflagCfg
+: <a class="el" href="struct_dss___dctrl_global_dss_params.html#af07803690960e450435f1d962bd6e82a">Dss_DctrlGlobalDssParams</a>
+</li>
+<li>globalMflagCtrl
+: <a class="el" href="struct_c_s_l___dss_global_m_flag_cfg.html#a476453835fc320b9268d47a22b23dbc8">CSL_DssGlobalMFlagCfg</a>
+</li>
+<li>globalMflagStart
+: <a class="el" href="struct_c_s_l___dss_global_m_flag_cfg.html#ab59aea1dc07f654fc07e0710421923f2">CSL_DssGlobalMFlagCfg</a>
+</li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/functions_vars_h.html b/packages/ti/drv/dss/docs/doxygen/html/functions_vars_h.html
--- /dev/null
@@ -0,0 +1,103 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Data Fields - Variables</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li class="current"><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="files.html"><span>Files</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow2" class="tabs2">
+ <ul class="tablist">
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li class="current"><a href="functions.html"><span>Data Fields</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow3" class="tabs2">
+ <ul class="tablist">
+ <li><a href="functions.html"><span>All</span></a></li>
+ <li class="current"><a href="functions_vars.html"><span>Variables</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow4" class="tabs3">
+ <ul class="tablist">
+ <li><a href="functions_vars.html#index_a"><span>a</span></a></li>
+ <li><a href="functions_vars_b.html#index_b"><span>b</span></a></li>
+ <li><a href="functions_vars_c.html#index_c"><span>c</span></a></li>
+ <li><a href="functions_vars_d.html#index_d"><span>d</span></a></li>
+ <li><a href="functions_vars_e.html#index_e"><span>e</span></a></li>
+ <li><a href="functions_vars_f.html#index_f"><span>f</span></a></li>
+ <li><a href="functions_vars_g.html#index_g"><span>g</span></a></li>
+ <li class="current"><a href="functions_vars_h.html#index_h"><span>h</span></a></li>
+ <li><a href="functions_vars_i.html#index_i"><span>i</span></a></li>
+ <li><a href="functions_vars_l.html#index_l"><span>l</span></a></li>
+ <li><a href="functions_vars_m.html#index_m"><span>m</span></a></li>
+ <li><a href="functions_vars_n.html#index_n"><span>n</span></a></li>
+ <li><a href="functions_vars_o.html#index_o"><span>o</span></a></li>
+ <li><a href="functions_vars_p.html#index_p"><span>p</span></a></li>
+ <li><a href="functions_vars_q.html#index_q"><span>q</span></a></li>
+ <li><a href="functions_vars_r.html#index_r"><span>r</span></a></li>
+ <li><a href="functions_vars_s.html#index_s"><span>s</span></a></li>
+ <li><a href="functions_vars_t.html#index_t"><span>t</span></a></li>
+ <li><a href="functions_vars_u.html#index_u"><span>u</span></a></li>
+ <li><a href="functions_vars_v.html#index_v"><span>v</span></a></li>
+ <li><a href="functions_vars_w.html#index_w"><span>w</span></a></li>
+ <li><a href="functions_vars_y.html#index_y"><span>y</span></a></li>
+ </ul>
+ </div>
+</div><!-- top -->
+<div class="contents">
+ 
+
+<h3><a class="anchor" id="index_h"></a>- h -</h3><ul>
+<li>hBackPorch
+: <a class="el" href="struct_c_s_l___dss_vp_lcd_blank_timing_cfg.html#afea7b5341ea83edbb5d067c5bc8a152b">CSL_DssVpLcdBlankTimingCfg</a>
+, <a class="el" href="struct_fvid2___mode_info.html#a0d8d9e15366412921d1b1cb083924236">Fvid2_ModeInfo</a>
+</li>
+<li>height
+: <a class="el" href="struct_dss___frame_rt_params.html#ab174627123752cb63bbd8450275ccc5c">Dss_FrameRtParams</a>
+, <a class="el" href="struct_fvid2___format.html#a4585d49a857883721f2664f4a0826849">Fvid2_Format</a>
+, <a class="el" href="struct_fvid2___mode_info.html#a086db39a44f2c72f78a9016263d56123">Fvid2_ModeInfo</a>
+, <a class="el" href="struct_fvid2___size_config.html#ae111168986dd4c3e73a9ffeed987cb3c">Fvid2_SizeConfig</a>
+</li>
+<li>hFrontPorch
+: <a class="el" href="struct_c_s_l___dss_vp_lcd_blank_timing_cfg.html#acdf92ed15c2e9ee31271fb9d611665b5">CSL_DssVpLcdBlankTimingCfg</a>
+, <a class="el" href="struct_fvid2___mode_info.html#a9c7400f345023ef6ebbf384d9d4f5a0c">Fvid2_ModeInfo</a>
+</li>
+<li>hsPolarity
+: <a class="el" href="struct_c_s_l___dss_vp_lcd_signal_polarity_cfg.html#a07d10e32b5c69a73ab69eb18f0e3e1e7">CSL_DssVpLcdSignalPolarityCfg</a>
+</li>
+<li>hSyncGated
+: <a class="el" href="struct_c_s_l___dss_vp_lcd_adv_signal_cfg.html#aa9d9f9160213e99b0018acb25aad2873">CSL_DssVpLcdAdvSignalCfg</a>
+</li>
+<li>hSyncLen
+: <a class="el" href="struct_c_s_l___dss_vp_lcd_blank_timing_cfg.html#ad79981ec3f4a8df8ee12b1dd96e7c667">CSL_DssVpLcdBlankTimingCfg</a>
+, <a class="el" href="struct_fvid2___mode_info.html#ac30f9a789796a753ee22fd56d837b0dc">Fvid2_ModeInfo</a>
+</li>
+<li>hVAlign
+: <a class="el" href="struct_c_s_l___dss_vp_lcd_adv_signal_cfg.html#a2e82a5ae83cd53e3b4f0608a8058c69b">CSL_DssVpLcdAdvSignalCfg</a>
+</li>
+<li>hVClkControl
+: <a class="el" href="struct_c_s_l___dss_vp_lcd_adv_signal_cfg.html#a5794fc2d4b1012397f05e36b64e98809">CSL_DssVpLcdAdvSignalCfg</a>
+</li>
+<li>hVClkRiseFall
+: <a class="el" href="struct_c_s_l___dss_vp_lcd_adv_signal_cfg.html#ad021ce573a1521cf305a2f2080db9589">CSL_DssVpLcdAdvSignalCfg</a>
+</li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/functions_vars_i.html b/packages/ti/drv/dss/docs/doxygen/html/functions_vars_i.html
--- /dev/null
@@ -0,0 +1,97 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Data Fields - Variables</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li class="current"><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="files.html"><span>Files</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow2" class="tabs2">
+ <ul class="tablist">
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li class="current"><a href="functions.html"><span>Data Fields</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow3" class="tabs2">
+ <ul class="tablist">
+ <li><a href="functions.html"><span>All</span></a></li>
+ <li class="current"><a href="functions_vars.html"><span>Variables</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow4" class="tabs3">
+ <ul class="tablist">
+ <li><a href="functions_vars.html#index_a"><span>a</span></a></li>
+ <li><a href="functions_vars_b.html#index_b"><span>b</span></a></li>
+ <li><a href="functions_vars_c.html#index_c"><span>c</span></a></li>
+ <li><a href="functions_vars_d.html#index_d"><span>d</span></a></li>
+ <li><a href="functions_vars_e.html#index_e"><span>e</span></a></li>
+ <li><a href="functions_vars_f.html#index_f"><span>f</span></a></li>
+ <li><a href="functions_vars_g.html#index_g"><span>g</span></a></li>
+ <li><a href="functions_vars_h.html#index_h"><span>h</span></a></li>
+ <li class="current"><a href="functions_vars_i.html#index_i"><span>i</span></a></li>
+ <li><a href="functions_vars_l.html#index_l"><span>l</span></a></li>
+ <li><a href="functions_vars_m.html#index_m"><span>m</span></a></li>
+ <li><a href="functions_vars_n.html#index_n"><span>n</span></a></li>
+ <li><a href="functions_vars_o.html#index_o"><span>o</span></a></li>
+ <li><a href="functions_vars_p.html#index_p"><span>p</span></a></li>
+ <li><a href="functions_vars_q.html#index_q"><span>q</span></a></li>
+ <li><a href="functions_vars_r.html#index_r"><span>r</span></a></li>
+ <li><a href="functions_vars_s.html#index_s"><span>s</span></a></li>
+ <li><a href="functions_vars_t.html#index_t"><span>t</span></a></li>
+ <li><a href="functions_vars_u.html#index_u"><span>u</span></a></li>
+ <li><a href="functions_vars_v.html#index_v"><span>v</span></a></li>
+ <li><a href="functions_vars_w.html#index_w"><span>w</span></a></li>
+ <li><a href="functions_vars_y.html#index_y"><span>y</span></a></li>
+ </ul>
+ </div>
+</div><!-- top -->
+<div class="contents">
+ 
+
+<h3><a class="anchor" id="index_i"></a>- i -</h3><ul>
+<li>inFmt
+: <a class="el" href="struct_c_s_l___dss_vid_pipe_cfg.html#ad746f01b386f5f8b836ae76193641be0">CSL_DssVidPipeCfg</a>
+</li>
+<li>inFrmParams
+: <a class="el" href="struct_dss___disp_rt_params.html#a6cc436c9916749a865525d66388c7133">Dss_DispRtParams</a>
+</li>
+<li>inputPipe
+: <a class="el" href="struct_c_s_l___dss_overlay_layer_cfg.html#a9fa2884d228ae00ba4694fcb04c76bf9">CSL_DssOverlayLayerCfg</a>
+</li>
+<li>irqNum
+: <a class="el" href="struct_dss___irq_params.html#aa3ef349676a4f3e5ff139616501c4a25">Dss_IrqParams</a>
+</li>
+<li>irqParams
+: <a class="el" href="struct_dss___soc_params.html#a8323d29f1f228a29162b29d1ab487b5a">Dss_SocParams</a>
+</li>
+<li>isCommRegAvailable
+: <a class="el" href="struct_dss___rm_info.html#aba3fc693c174a47dd1d73a9e58d97b00">Dss_RmInfo</a>
+</li>
+<li>isOverlayAvailable
+: <a class="el" href="struct_dss___rm_info.html#ac9add0a21cbc5d3a4b0f893e766e593e">Dss_RmInfo</a>
+</li>
+<li>isPipeAvailable
+: <a class="el" href="struct_dss___rm_info.html#a4b8a53db450d230a652cd8cc38d9cd5a">Dss_RmInfo</a>
+</li>
+<li>isPortAvailable
+: <a class="el" href="struct_dss___rm_info.html#a72fbf32ce584379f198783a281f00130">Dss_RmInfo</a>
+</li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/functions_vars_l.html b/packages/ti/drv/dss/docs/doxygen/html/functions_vars_l.html
--- /dev/null
@@ -0,0 +1,104 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Data Fields - Variables</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li class="current"><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="files.html"><span>Files</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow2" class="tabs2">
+ <ul class="tablist">
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li class="current"><a href="functions.html"><span>Data Fields</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow3" class="tabs2">
+ <ul class="tablist">
+ <li><a href="functions.html"><span>All</span></a></li>
+ <li class="current"><a href="functions_vars.html"><span>Variables</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow4" class="tabs3">
+ <ul class="tablist">
+ <li><a href="functions_vars.html#index_a"><span>a</span></a></li>
+ <li><a href="functions_vars_b.html#index_b"><span>b</span></a></li>
+ <li><a href="functions_vars_c.html#index_c"><span>c</span></a></li>
+ <li><a href="functions_vars_d.html#index_d"><span>d</span></a></li>
+ <li><a href="functions_vars_e.html#index_e"><span>e</span></a></li>
+ <li><a href="functions_vars_f.html#index_f"><span>f</span></a></li>
+ <li><a href="functions_vars_g.html#index_g"><span>g</span></a></li>
+ <li><a href="functions_vars_h.html#index_h"><span>h</span></a></li>
+ <li><a href="functions_vars_i.html#index_i"><span>i</span></a></li>
+ <li class="current"><a href="functions_vars_l.html#index_l"><span>l</span></a></li>
+ <li><a href="functions_vars_m.html#index_m"><span>m</span></a></li>
+ <li><a href="functions_vars_n.html#index_n"><span>n</span></a></li>
+ <li><a href="functions_vars_o.html#index_o"><span>o</span></a></li>
+ <li><a href="functions_vars_p.html#index_p"><span>p</span></a></li>
+ <li><a href="functions_vars_q.html#index_q"><span>q</span></a></li>
+ <li><a href="functions_vars_r.html#index_r"><span>r</span></a></li>
+ <li><a href="functions_vars_s.html#index_s"><span>s</span></a></li>
+ <li><a href="functions_vars_t.html#index_t"><span>t</span></a></li>
+ <li><a href="functions_vars_u.html#index_u"><span>u</span></a></li>
+ <li><a href="functions_vars_v.html#index_v"><span>v</span></a></li>
+ <li><a href="functions_vars_w.html#index_w"><span>w</span></a></li>
+ <li><a href="functions_vars_y.html#index_y"><span>y</span></a></li>
+ </ul>
+ </div>
+</div><!-- top -->
+<div class="contents">
+ 
+
+<h3><a class="anchor" id="index_l"></a>- l -</h3><ul>
+<li>layerEnable
+: <a class="el" href="struct_c_s_l___dss_overlay_layer_cfg.html#a83dcc8dccd51c4dd38f5c8de44226596">CSL_DssOverlayLayerCfg</a>
+</li>
+<li>layerNum
+: <a class="el" href="struct_c_s_l___dss_overlay_layer_cfg.html#a79b077926e883044363d2fe27a986196">CSL_DssOverlayLayerCfg</a>
+</li>
+<li>layerPos
+: <a class="el" href="struct_c_s_l___dss_overlay_pipe_pos_cfg.html#af609b8a3d9d62d0dd1ac4756c3add323">CSL_DssOverlayPipePosCfg</a>
+, <a class="el" href="struct_dss___disp_params.html#ac26e2dd60bc2eb1f9a1ef92f5b8374c8">Dss_DispParams</a>
+</li>
+<li>lcdAdvSignalCfg
+: <a class="el" href="struct_dss___dctrl_adv_vp_params.html#a6f8a69ef5d888ab0efac61cd952b84e4">Dss_DctrlAdvVpParams</a>
+</li>
+<li>lcdBlankTimingCfg
+: <a class="el" href="struct_dss___dctrl_lcd_blank_timing_params.html#ab210add6d59769281c95f6d1bc8b9d76">Dss_DctrlLcdBlankTimingParams</a>
+</li>
+<li>lcdOpTimingCfg
+: <a class="el" href="struct_dss___dctrl_vp_params.html#ab85222c9535dd65a0148c5df4ebf4d2f">Dss_DctrlVpParams</a>
+</li>
+<li>lcdPolarityCfg
+: <a class="el" href="struct_dss___dctrl_vp_params.html#a40f589e08e3d00ac44640cc27ffd20dd">Dss_DctrlVpParams</a>
+</li>
+<li>lcdTdmCfg
+: <a class="el" href="struct_dss___dctrl_vp_params.html#a705586424b3d0c7af64f8bae7d95fcba">Dss_DctrlVpParams</a>
+</li>
+<li>lumaKeyEnable
+: <a class="el" href="struct_c_s_l___dss_vid_pipe_luma_cfg.html#a963fa503522975f7e78da0e7085ac209">CSL_DssVidPipeLumaCfg</a>
+</li>
+<li>lumaKeyMaxVal
+: <a class="el" href="struct_c_s_l___dss_vid_pipe_luma_cfg.html#af695a93a94cb7e1981719483d56feda5">CSL_DssVidPipeLumaCfg</a>
+</li>
+<li>lumaKeyMinVal
+: <a class="el" href="struct_c_s_l___dss_vid_pipe_luma_cfg.html#af92d3bdda59367a1120e40316b8469b5">CSL_DssVidPipeLumaCfg</a>
+</li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/functions_vars_m.html b/packages/ti/drv/dss/docs/doxygen/html/functions_vars_m.html
--- /dev/null
@@ -0,0 +1,79 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Data Fields - Variables</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li class="current"><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="files.html"><span>Files</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow2" class="tabs2">
+ <ul class="tablist">
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li class="current"><a href="functions.html"><span>Data Fields</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow3" class="tabs2">
+ <ul class="tablist">
+ <li><a href="functions.html"><span>All</span></a></li>
+ <li class="current"><a href="functions_vars.html"><span>Variables</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow4" class="tabs3">
+ <ul class="tablist">
+ <li><a href="functions_vars.html#index_a"><span>a</span></a></li>
+ <li><a href="functions_vars_b.html#index_b"><span>b</span></a></li>
+ <li><a href="functions_vars_c.html#index_c"><span>c</span></a></li>
+ <li><a href="functions_vars_d.html#index_d"><span>d</span></a></li>
+ <li><a href="functions_vars_e.html#index_e"><span>e</span></a></li>
+ <li><a href="functions_vars_f.html#index_f"><span>f</span></a></li>
+ <li><a href="functions_vars_g.html#index_g"><span>g</span></a></li>
+ <li><a href="functions_vars_h.html#index_h"><span>h</span></a></li>
+ <li><a href="functions_vars_i.html#index_i"><span>i</span></a></li>
+ <li><a href="functions_vars_l.html#index_l"><span>l</span></a></li>
+ <li class="current"><a href="functions_vars_m.html#index_m"><span>m</span></a></li>
+ <li><a href="functions_vars_n.html#index_n"><span>n</span></a></li>
+ <li><a href="functions_vars_o.html#index_o"><span>o</span></a></li>
+ <li><a href="functions_vars_p.html#index_p"><span>p</span></a></li>
+ <li><a href="functions_vars_q.html#index_q"><span>q</span></a></li>
+ <li><a href="functions_vars_r.html#index_r"><span>r</span></a></li>
+ <li><a href="functions_vars_s.html#index_s"><span>s</span></a></li>
+ <li><a href="functions_vars_t.html#index_t"><span>t</span></a></li>
+ <li><a href="functions_vars_u.html#index_u"><span>u</span></a></li>
+ <li><a href="functions_vars_v.html#index_v"><span>v</span></a></li>
+ <li><a href="functions_vars_w.html#index_w"><span>w</span></a></li>
+ <li><a href="functions_vars_y.html#index_y"><span>y</span></a></li>
+ </ul>
+ </div>
+</div><!-- top -->
+<div class="contents">
+ 
+
+<h3><a class="anchor" id="index_m"></a>- m -</h3><ul>
+<li>mflagCfg
+: <a class="el" href="struct_dss___disp_pipe_mflag_params.html#a006a172bac6001d494ac6f1901d56f1e">Dss_DispPipeMflagParams</a>
+</li>
+<li>mInfo
+: <a class="el" href="struct_c_s_l___dss_vp_lcd_op_timing_cfg.html#a19292617b2fdd63c9d9d85a1ea41d97a">CSL_DssVpLcdOpTimingCfg</a>
+</li>
+<li>minNumPrimeBuf
+: <a class="el" href="struct_dss___disp_create_status.html#a12b0ad905934ec8007bcd821cf0deff7">Dss_DispCreateStatus</a>
+</li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/functions_vars_n.html b/packages/ti/drv/dss/docs/doxygen/html/functions_vars_n.html
--- /dev/null
@@ -0,0 +1,106 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Data Fields - Variables</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li class="current"><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="files.html"><span>Files</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow2" class="tabs2">
+ <ul class="tablist">
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li class="current"><a href="functions.html"><span>Data Fields</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow3" class="tabs2">
+ <ul class="tablist">
+ <li><a href="functions.html"><span>All</span></a></li>
+ <li class="current"><a href="functions_vars.html"><span>Variables</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow4" class="tabs3">
+ <ul class="tablist">
+ <li><a href="functions_vars.html#index_a"><span>a</span></a></li>
+ <li><a href="functions_vars_b.html#index_b"><span>b</span></a></li>
+ <li><a href="functions_vars_c.html#index_c"><span>c</span></a></li>
+ <li><a href="functions_vars_d.html#index_d"><span>d</span></a></li>
+ <li><a href="functions_vars_e.html#index_e"><span>e</span></a></li>
+ <li><a href="functions_vars_f.html#index_f"><span>f</span></a></li>
+ <li><a href="functions_vars_g.html#index_g"><span>g</span></a></li>
+ <li><a href="functions_vars_h.html#index_h"><span>h</span></a></li>
+ <li><a href="functions_vars_i.html#index_i"><span>i</span></a></li>
+ <li><a href="functions_vars_l.html#index_l"><span>l</span></a></li>
+ <li><a href="functions_vars_m.html#index_m"><span>m</span></a></li>
+ <li class="current"><a href="functions_vars_n.html#index_n"><span>n</span></a></li>
+ <li><a href="functions_vars_o.html#index_o"><span>o</span></a></li>
+ <li><a href="functions_vars_p.html#index_p"><span>p</span></a></li>
+ <li><a href="functions_vars_q.html#index_q"><span>q</span></a></li>
+ <li><a href="functions_vars_r.html#index_r"><span>r</span></a></li>
+ <li><a href="functions_vars_s.html#index_s"><span>s</span></a></li>
+ <li><a href="functions_vars_t.html#index_t"><span>t</span></a></li>
+ <li><a href="functions_vars_u.html#index_u"><span>u</span></a></li>
+ <li><a href="functions_vars_v.html#index_v"><span>v</span></a></li>
+ <li><a href="functions_vars_w.html#index_w"><span>w</span></a></li>
+ <li><a href="functions_vars_y.html#index_y"><span>y</span></a></li>
+ </ul>
+ </div>
+</div><!-- top -->
+<div class="contents">
+ 
+
+<h3><a class="anchor" id="index_n"></a>- n -</h3><ul>
+<li>nibblemodeEnable
+: <a class="el" href="struct_c_s_l___dss_vid_pipe_cfg.html#a3c4e8eb4baaf50467b94c025b7f9831f">CSL_DssVidPipeCfg</a>
+</li>
+<li>numBitsPixel1Cycle0
+: <a class="el" href="struct_c_s_l___dss_vp_lcd_tdm_cfg.html#a0d9325def55c887e1e6d6b240c66e290">CSL_DssVpLcdTdmCfg</a>
+</li>
+<li>numBitsPixel1Cycle1
+: <a class="el" href="struct_c_s_l___dss_vp_lcd_tdm_cfg.html#acdc280739512994d6cc71dd1125e12fb">CSL_DssVpLcdTdmCfg</a>
+</li>
+<li>numBitsPixel1Cycle2
+: <a class="el" href="struct_c_s_l___dss_vp_lcd_tdm_cfg.html#ae83d325c5b05f1db8045509f5de15269">CSL_DssVpLcdTdmCfg</a>
+</li>
+<li>numBitsPixel2Cycle0
+: <a class="el" href="struct_c_s_l___dss_vp_lcd_tdm_cfg.html#a24039fc18531e5abf5f24eae912385d4">CSL_DssVpLcdTdmCfg</a>
+</li>
+<li>numBitsPixel2Cycle1
+: <a class="el" href="struct_c_s_l___dss_vp_lcd_tdm_cfg.html#adc86e977d445f895132a246b494ae240">CSL_DssVpLcdTdmCfg</a>
+</li>
+<li>numBitsPixel2Cycle2
+: <a class="el" href="struct_c_s_l___dss_vp_lcd_tdm_cfg.html#ad1b25370dd21ced32c4a9a3abb5e50f0">CSL_DssVpLcdTdmCfg</a>
+</li>
+<li>numEdges
+: <a class="el" href="struct_dss___dctrl_path_info.html#a86805ff6cd957de13ee114445fc2a316">Dss_DctrlPathInfo</a>
+</li>
+<li>numFrames
+: <a class="el" href="struct_fvid2___frame_list.html#af516451b916cad435d827c96669e2825">Fvid2_FrameList</a>
+</li>
+<li>numInLines
+: <a class="el" href="struct_fvid2___sub_frame_info.html#a813a5659d1d56a49b0d1b6d8d600ae74">Fvid2_SubFrameInfo</a>
+</li>
+<li>numOutLines
+: <a class="el" href="struct_fvid2___sub_frame_info.html#aad0a2f3475b4f409b956a359b31a0960">Fvid2_SubFrameInfo</a>
+</li>
+<li>numValidIrq
+: <a class="el" href="struct_dss___irq_params.html#aa506ef07fa2b7d3396f82dc52e46c2bd">Dss_IrqParams</a>
+</li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/functions_vars_o.html b/packages/ti/drv/dss/docs/doxygen/html/functions_vars_o.html
--- /dev/null
@@ -0,0 +1,89 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Data Fields - Variables</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li class="current"><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="files.html"><span>Files</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow2" class="tabs2">
+ <ul class="tablist">
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li class="current"><a href="functions.html"><span>Data Fields</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow3" class="tabs2">
+ <ul class="tablist">
+ <li><a href="functions.html"><span>All</span></a></li>
+ <li class="current"><a href="functions_vars.html"><span>Variables</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow4" class="tabs3">
+ <ul class="tablist">
+ <li><a href="functions_vars.html#index_a"><span>a</span></a></li>
+ <li><a href="functions_vars_b.html#index_b"><span>b</span></a></li>
+ <li><a href="functions_vars_c.html#index_c"><span>c</span></a></li>
+ <li><a href="functions_vars_d.html#index_d"><span>d</span></a></li>
+ <li><a href="functions_vars_e.html#index_e"><span>e</span></a></li>
+ <li><a href="functions_vars_f.html#index_f"><span>f</span></a></li>
+ <li><a href="functions_vars_g.html#index_g"><span>g</span></a></li>
+ <li><a href="functions_vars_h.html#index_h"><span>h</span></a></li>
+ <li><a href="functions_vars_i.html#index_i"><span>i</span></a></li>
+ <li><a href="functions_vars_l.html#index_l"><span>l</span></a></li>
+ <li><a href="functions_vars_m.html#index_m"><span>m</span></a></li>
+ <li><a href="functions_vars_n.html#index_n"><span>n</span></a></li>
+ <li class="current"><a href="functions_vars_o.html#index_o"><span>o</span></a></li>
+ <li><a href="functions_vars_p.html#index_p"><span>p</span></a></li>
+ <li><a href="functions_vars_q.html#index_q"><span>q</span></a></li>
+ <li><a href="functions_vars_r.html#index_r"><span>r</span></a></li>
+ <li><a href="functions_vars_s.html#index_s"><span>s</span></a></li>
+ <li><a href="functions_vars_t.html#index_t"><span>t</span></a></li>
+ <li><a href="functions_vars_u.html#index_u"><span>u</span></a></li>
+ <li><a href="functions_vars_v.html#index_v"><span>v</span></a></li>
+ <li><a href="functions_vars_w.html#index_w"><span>w</span></a></li>
+ <li><a href="functions_vars_y.html#index_y"><span>y</span></a></li>
+ </ul>
+ </div>
+</div><!-- top -->
+<div class="contents">
+ 
+
+<h3><a class="anchor" id="index_o"></a>- o -</h3><ul>
+<li>oldiCfg
+: <a class="el" href="struct_dss___dctrl_oldi_params.html#adad012c98bd5cf3ce7cb164f57ba38cb">Dss_DctrlOldiParams</a>
+</li>
+<li>outFrmParams
+: <a class="el" href="struct_dss___disp_rt_params.html#a8190a88390e7d3d6327d53c73381a997">Dss_DispRtParams</a>
+</li>
+<li>outHeight
+: <a class="el" href="struct_c_s_l___dss_vid_pipe_cfg.html#a1d3a19f6cf680aba0505a2abd670140e">CSL_DssVidPipeCfg</a>
+</li>
+<li>outWidth
+: <a class="el" href="struct_c_s_l___dss_vid_pipe_cfg.html#aee9fafc3374aa44e5d8aa0ade330de5c">CSL_DssVidPipeCfg</a>
+</li>
+<li>overlayCfg
+: <a class="el" href="struct_dss___dctrl_overlay_params.html#acaee7b8d01578e10237919957527a046">Dss_DctrlOverlayParams</a>
+</li>
+<li>overlayId
+: <a class="el" href="struct_dss___dctrl_overlay_layer_params.html#af8e6714702ff114368a6b0fd566e3e65">Dss_DctrlOverlayLayerParams</a>
+, <a class="el" href="struct_dss___dctrl_overlay_params.html#a2883c49b828e361ecc83312668ef535d">Dss_DctrlOverlayParams</a>
+</li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/functions_vars_p.html b/packages/ti/drv/dss/docs/doxygen/html/functions_vars_p.html
--- /dev/null
@@ -0,0 +1,153 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Data Fields - Variables</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li class="current"><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="files.html"><span>Files</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow2" class="tabs2">
+ <ul class="tablist">
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li class="current"><a href="functions.html"><span>Data Fields</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow3" class="tabs2">
+ <ul class="tablist">
+ <li><a href="functions.html"><span>All</span></a></li>
+ <li class="current"><a href="functions_vars.html"><span>Variables</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow4" class="tabs3">
+ <ul class="tablist">
+ <li><a href="functions_vars.html#index_a"><span>a</span></a></li>
+ <li><a href="functions_vars_b.html#index_b"><span>b</span></a></li>
+ <li><a href="functions_vars_c.html#index_c"><span>c</span></a></li>
+ <li><a href="functions_vars_d.html#index_d"><span>d</span></a></li>
+ <li><a href="functions_vars_e.html#index_e"><span>e</span></a></li>
+ <li><a href="functions_vars_f.html#index_f"><span>f</span></a></li>
+ <li><a href="functions_vars_g.html#index_g"><span>g</span></a></li>
+ <li><a href="functions_vars_h.html#index_h"><span>h</span></a></li>
+ <li><a href="functions_vars_i.html#index_i"><span>i</span></a></li>
+ <li><a href="functions_vars_l.html#index_l"><span>l</span></a></li>
+ <li><a href="functions_vars_m.html#index_m"><span>m</span></a></li>
+ <li><a href="functions_vars_n.html#index_n"><span>n</span></a></li>
+ <li><a href="functions_vars_o.html#index_o"><span>o</span></a></li>
+ <li class="current"><a href="functions_vars_p.html#index_p"><span>p</span></a></li>
+ <li><a href="functions_vars_q.html#index_q"><span>q</span></a></li>
+ <li><a href="functions_vars_r.html#index_r"><span>r</span></a></li>
+ <li><a href="functions_vars_s.html#index_s"><span>s</span></a></li>
+ <li><a href="functions_vars_t.html#index_t"><span>t</span></a></li>
+ <li><a href="functions_vars_u.html#index_u"><span>u</span></a></li>
+ <li><a href="functions_vars_v.html#index_v"><span>v</span></a></li>
+ <li><a href="functions_vars_w.html#index_w"><span>w</span></a></li>
+ <li><a href="functions_vars_y.html#index_y"><span>y</span></a></li>
+ </ul>
+ </div>
+</div><!-- top -->
+<div class="contents">
+ 
+
+<h3><a class="anchor" id="index_p"></a>- p -</h3><ul>
+<li>perFrameCfg
+: <a class="el" href="struct_fvid2___frame.html#ab70ec59f98e2fa3bac85f5fe25645bcc">Fvid2_Frame</a>
+</li>
+<li>periodicCbEnable
+: <a class="el" href="struct_dss___disp_create_params.html#ab8366600abad325065cdf8fac4de2a77">Dss_DispCreateParams</a>
+</li>
+<li>perListCfg
+: <a class="el" href="struct_fvid2___frame_list.html#ab6dbd19e34bebec6941fbde314fcfb4f">Fvid2_FrameList</a>
+</li>
+<li>pipeCfg
+: <a class="el" href="struct_dss___disp_params.html#a48165b146fa02698a76b378930ad9a3f">Dss_DispParams</a>
+</li>
+<li>pipeLayerNum
+: <a class="el" href="struct_dss___dctrl_overlay_layer_params.html#a8c4c1af551a7aa49f3e5eab31c7f3d26">Dss_DctrlOverlayLayerParams</a>
+</li>
+<li>pipePrgmCbFxn
+: <a class="el" href="struct_dss___disp_pipe_prgm_cb_params.html#a3665e053d0ee61b9555b4640f4e1325f">Dss_DispPipePrgmCbParams</a>
+</li>
+<li>pipeSafetyChkCfg
+: <a class="el" href="struct_dss___disp_pipe_safety_chk_params.html#a1d2da23596678e366eddaad75e2382c3">Dss_DispPipeSafetyChkParams</a>
+</li>
+<li>pipeType
+: <a class="el" href="struct_c_s_l___dss_vid_pipe_cfg.html#a85e0ba7c97b71003b61e862ebc3fbe40">CSL_DssVidPipeCfg</a>
+</li>
+<li>pitch
+: <a class="el" href="struct_dss___frame_rt_params.html#a4dab0431dffbdbcb94b06e5cb27c7f06">Dss_FrameRtParams</a>
+, <a class="el" href="struct_fvid2___format.html#a3721a977887cae78aa15398c8214145b">Fvid2_Format</a>
+</li>
+<li>pixelClkPolarity
+: <a class="el" href="struct_c_s_l___dss_vp_lcd_signal_polarity_cfg.html#a097ae617d62555043fe4edd375a6963c">CSL_DssVpLcdSignalPolarityCfg</a>
+</li>
+<li>pixelClock
+: <a class="el" href="struct_fvid2___mode_info.html#ac65ac9af809220a1a6445bfa1111ca05">Fvid2_ModeInfo</a>
+</li>
+<li>pixelClockGated
+: <a class="el" href="struct_c_s_l___dss_vp_lcd_adv_signal_cfg.html#a071dfbc56f4de8d9818e824d03a9662c">CSL_DssVpLcdAdvSignalCfg</a>
+</li>
+<li>pixelDataGated
+: <a class="el" href="struct_c_s_l___dss_vp_lcd_adv_signal_cfg.html#a32ff2b36d117b98e574214336a68616e">CSL_DssVpLcdAdvSignalCfg</a>
+</li>
+<li>pixelGated
+: <a class="el" href="struct_c_s_l___dss_vp_lcd_adv_signal_cfg.html#a3111150c26bb26812762ef8de4ba03d6">CSL_DssVpLcdAdvSignalCfg</a>
+</li>
+<li>pixelInc
+: <a class="el" href="struct_c_s_l___dss_vid_pipe_cfg.html#a026189ab1fe6ad7ab75606a70cbc6136">CSL_DssVidPipeCfg</a>
+, <a class="el" href="struct_dss___sc_rt_params.html#a91ae75c8f0ebf3f0cc30b8b97a2024c6">Dss_ScRtParams</a>
+</li>
+<li>posCfg
+: <a class="el" href="struct_dss___disp_rt_params.html#a29259476cb78ef269ef5827d5c59e11e">Dss_DispRtParams</a>
+</li>
+<li>postOffset1
+: <a class="el" href="struct_c_s_l___dss_csc_coeff.html#ab0784bdfae37f766f4ad327bc5e597c6">CSL_DssCscCoeff</a>
+</li>
+<li>postOffset2
+: <a class="el" href="struct_c_s_l___dss_csc_coeff.html#aead82d70ab275933b820a7e87abb05c8">CSL_DssCscCoeff</a>
+</li>
+<li>postOffset3
+: <a class="el" href="struct_c_s_l___dss_csc_coeff.html#a3877e738385c127011a7c14b00c38ddf">CSL_DssCscCoeff</a>
+</li>
+<li>preloadVal
+: <a class="el" href="struct_c_s_l___dss_vid_pipe_dma_cfg.html#a168a8a5323eacf1349b91ff84a28290e">CSL_DssVidPipeDmaCfg</a>
+</li>
+<li>preMultiplyAlpha
+: <a class="el" href="struct_c_s_l___dss_vid_pipe_alpha_cfg.html#a592febc9d395769c45a294b1b2725136">CSL_DssVidPipeAlphaCfg</a>
+</li>
+<li>preOffset1
+: <a class="el" href="struct_c_s_l___dss_csc_coeff.html#ac7220e1ec74749d1223be58334fec6bd">CSL_DssCscCoeff</a>
+</li>
+<li>preOffset2
+: <a class="el" href="struct_c_s_l___dss_csc_coeff.html#ad68c0c52100a22abdc7e7f32726d9070">CSL_DssCscCoeff</a>
+</li>
+<li>preOffset3
+: <a class="el" href="struct_c_s_l___dss_csc_coeff.html#a347ff46868f7d6adfd877071a9fcc899">CSL_DssCscCoeff</a>
+</li>
+<li>priHigh
+: <a class="el" href="struct_c_s_l___dss_cba_cfg.html#a6f7af7472d1da8ba301750414e88640f">CSL_DssCbaCfg</a>
+</li>
+<li>priLow
+: <a class="el" href="struct_c_s_l___dss_cba_cfg.html#a6d3f899c4e19cf0e52d33d01295f75e7">CSL_DssCbaCfg</a>
+</li>
+<li>progPipeVsyncEnable
+: <a class="el" href="struct_dss___disp_create_params.html#a1b1d68b7e5feb7f8c40fb925db6a2ce9">Dss_DispCreateParams</a>
+</li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/functions_vars_q.html b/packages/ti/drv/dss/docs/doxygen/html/functions_vars_q.html
--- /dev/null
@@ -0,0 +1,73 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Data Fields - Variables</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li class="current"><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="files.html"><span>Files</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow2" class="tabs2">
+ <ul class="tablist">
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li class="current"><a href="functions.html"><span>Data Fields</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow3" class="tabs2">
+ <ul class="tablist">
+ <li><a href="functions.html"><span>All</span></a></li>
+ <li class="current"><a href="functions_vars.html"><span>Variables</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow4" class="tabs3">
+ <ul class="tablist">
+ <li><a href="functions_vars.html#index_a"><span>a</span></a></li>
+ <li><a href="functions_vars_b.html#index_b"><span>b</span></a></li>
+ <li><a href="functions_vars_c.html#index_c"><span>c</span></a></li>
+ <li><a href="functions_vars_d.html#index_d"><span>d</span></a></li>
+ <li><a href="functions_vars_e.html#index_e"><span>e</span></a></li>
+ <li><a href="functions_vars_f.html#index_f"><span>f</span></a></li>
+ <li><a href="functions_vars_g.html#index_g"><span>g</span></a></li>
+ <li><a href="functions_vars_h.html#index_h"><span>h</span></a></li>
+ <li><a href="functions_vars_i.html#index_i"><span>i</span></a></li>
+ <li><a href="functions_vars_l.html#index_l"><span>l</span></a></li>
+ <li><a href="functions_vars_m.html#index_m"><span>m</span></a></li>
+ <li><a href="functions_vars_n.html#index_n"><span>n</span></a></li>
+ <li><a href="functions_vars_o.html#index_o"><span>o</span></a></li>
+ <li><a href="functions_vars_p.html#index_p"><span>p</span></a></li>
+ <li class="current"><a href="functions_vars_q.html#index_q"><span>q</span></a></li>
+ <li><a href="functions_vars_r.html#index_r"><span>r</span></a></li>
+ <li><a href="functions_vars_s.html#index_s"><span>s</span></a></li>
+ <li><a href="functions_vars_t.html#index_t"><span>t</span></a></li>
+ <li><a href="functions_vars_u.html#index_u"><span>u</span></a></li>
+ <li><a href="functions_vars_v.html#index_v"><span>v</span></a></li>
+ <li><a href="functions_vars_w.html#index_w"><span>w</span></a></li>
+ <li><a href="functions_vars_y.html#index_y"><span>y</span></a></li>
+ </ul>
+ </div>
+</div><!-- top -->
+<div class="contents">
+ 
+
+<h3><a class="anchor" id="index_q"></a>- q -</h3><ul>
+<li>queueCount
+: <a class="el" href="struct_dss___disp_current_status.html#a92cf9e8cc3729ad69f5e7240d3598d01">Dss_DispCurrentStatus</a>
+</li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/functions_vars_r.html b/packages/ti/drv/dss/docs/doxygen/html/functions_vars_r.html
--- /dev/null
@@ -0,0 +1,95 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Data Fields - Variables</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li class="current"><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="files.html"><span>Files</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow2" class="tabs2">
+ <ul class="tablist">
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li class="current"><a href="functions.html"><span>Data Fields</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow3" class="tabs2">
+ <ul class="tablist">
+ <li><a href="functions.html"><span>All</span></a></li>
+ <li class="current"><a href="functions_vars.html"><span>Variables</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow4" class="tabs3">
+ <ul class="tablist">
+ <li><a href="functions_vars.html#index_a"><span>a</span></a></li>
+ <li><a href="functions_vars_b.html#index_b"><span>b</span></a></li>
+ <li><a href="functions_vars_c.html#index_c"><span>c</span></a></li>
+ <li><a href="functions_vars_d.html#index_d"><span>d</span></a></li>
+ <li><a href="functions_vars_e.html#index_e"><span>e</span></a></li>
+ <li><a href="functions_vars_f.html#index_f"><span>f</span></a></li>
+ <li><a href="functions_vars_g.html#index_g"><span>g</span></a></li>
+ <li><a href="functions_vars_h.html#index_h"><span>h</span></a></li>
+ <li><a href="functions_vars_i.html#index_i"><span>i</span></a></li>
+ <li><a href="functions_vars_l.html#index_l"><span>l</span></a></li>
+ <li><a href="functions_vars_m.html#index_m"><span>m</span></a></li>
+ <li><a href="functions_vars_n.html#index_n"><span>n</span></a></li>
+ <li><a href="functions_vars_o.html#index_o"><span>o</span></a></li>
+ <li><a href="functions_vars_p.html#index_p"><span>p</span></a></li>
+ <li><a href="functions_vars_q.html#index_q"><span>q</span></a></li>
+ <li class="current"><a href="functions_vars_r.html#index_r"><span>r</span></a></li>
+ <li><a href="functions_vars_s.html#index_s"><span>s</span></a></li>
+ <li><a href="functions_vars_t.html#index_t"><span>t</span></a></li>
+ <li><a href="functions_vars_u.html#index_u"><span>u</span></a></li>
+ <li><a href="functions_vars_v.html#index_v"><span>v</span></a></li>
+ <li><a href="functions_vars_w.html#index_w"><span>w</span></a></li>
+ <li><a href="functions_vars_y.html#index_y"><span>y</span></a></li>
+ </ul>
+ </div>
+</div><!-- top -->
+<div class="contents">
+ 
+
+<h3><a class="anchor" id="index_r"></a>- r -</h3><ul>
+<li>rangeUV
+: <a class="el" href="struct_c_s_l___dss_vid_pipe_v_c1_cfg.html#ae6ccf08aef3dd34a7470fc3f266f045c">CSL_DssVidPipeVC1Cfg</a>
+</li>
+<li>rangeY
+: <a class="el" href="struct_c_s_l___dss_vid_pipe_v_c1_cfg.html#ad5abb3e5a9aefd67f460c6c806d9d60a">CSL_DssVidPipeVC1Cfg</a>
+</li>
+<li>referenceSign
+: <a class="el" href="struct_dss___dctrl_region_safety_chk_cfg.html#a33766617818233c722d23b49daf3a1b1">Dss_DctrlRegionSafetyChkCfg</a>
+, <a class="el" href="struct_dss___disp_pipe_safety_chk_params.html#a959fe56578ad3537011559f97fbd4661">Dss_DispPipeSafetyChkParams</a>
+</li>
+<li>regionPos
+: <a class="el" href="struct_c_s_l___dss_safety_chk_cfg.html#acd23c9535ba779805df7c92946522de1">CSL_DssSafetyChkCfg</a>
+</li>
+<li>regionSize
+: <a class="el" href="struct_c_s_l___dss_safety_chk_cfg.html#adfe6989e81985735685e9dc1a3cc2fc3">CSL_DssSafetyChkCfg</a>
+</li>
+<li>repeatFrmCount
+: <a class="el" href="struct_dss___disp_current_status.html#af4c9a477ce0debeae4dbcd653e1d3c18">Dss_DispCurrentStatus</a>
+</li>
+<li>retVal
+: <a class="el" href="struct_dss___disp_create_status.html#a46416dc8db8540d785740d4b3c41f052">Dss_DispCreateStatus</a>
+</li>
+<li>rmInfo
+: <a class="el" href="struct_dss___soc_params.html#aafaaca6953b19d37aa273c25a3a5ada8">Dss_SocParams</a>
+</li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/functions_vars_s.html b/packages/ti/drv/dss/docs/doxygen/html/functions_vars_s.html
--- /dev/null
@@ -0,0 +1,142 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Data Fields - Variables</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li class="current"><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="files.html"><span>Files</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow2" class="tabs2">
+ <ul class="tablist">
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li class="current"><a href="functions.html"><span>Data Fields</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow3" class="tabs2">
+ <ul class="tablist">
+ <li><a href="functions.html"><span>All</span></a></li>
+ <li class="current"><a href="functions_vars.html"><span>Variables</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow4" class="tabs3">
+ <ul class="tablist">
+ <li><a href="functions_vars.html#index_a"><span>a</span></a></li>
+ <li><a href="functions_vars_b.html#index_b"><span>b</span></a></li>
+ <li><a href="functions_vars_c.html#index_c"><span>c</span></a></li>
+ <li><a href="functions_vars_d.html#index_d"><span>d</span></a></li>
+ <li><a href="functions_vars_e.html#index_e"><span>e</span></a></li>
+ <li><a href="functions_vars_f.html#index_f"><span>f</span></a></li>
+ <li><a href="functions_vars_g.html#index_g"><span>g</span></a></li>
+ <li><a href="functions_vars_h.html#index_h"><span>h</span></a></li>
+ <li><a href="functions_vars_i.html#index_i"><span>i</span></a></li>
+ <li><a href="functions_vars_l.html#index_l"><span>l</span></a></li>
+ <li><a href="functions_vars_m.html#index_m"><span>m</span></a></li>
+ <li><a href="functions_vars_n.html#index_n"><span>n</span></a></li>
+ <li><a href="functions_vars_o.html#index_o"><span>o</span></a></li>
+ <li><a href="functions_vars_p.html#index_p"><span>p</span></a></li>
+ <li><a href="functions_vars_q.html#index_q"><span>q</span></a></li>
+ <li><a href="functions_vars_r.html#index_r"><span>r</span></a></li>
+ <li class="current"><a href="functions_vars_s.html#index_s"><span>s</span></a></li>
+ <li><a href="functions_vars_t.html#index_t"><span>t</span></a></li>
+ <li><a href="functions_vars_u.html#index_u"><span>u</span></a></li>
+ <li><a href="functions_vars_v.html#index_v"><span>v</span></a></li>
+ <li><a href="functions_vars_w.html#index_w"><span>w</span></a></li>
+ <li><a href="functions_vars_y.html#index_y"><span>y</span></a></li>
+ </ul>
+ </div>
+</div><!-- top -->
+<div class="contents">
+ 
+
+<h3><a class="anchor" id="index_s"></a>- s -</h3><ul>
+<li>safetyChkCfg
+: <a class="el" href="struct_dss___dctrl_region_safety_chk_cfg.html#aba94499a93c5fcbcf17aac03978b7692">Dss_DctrlRegionSafetyChkCfg</a>
+</li>
+<li>safetyChkEnable
+: <a class="el" href="struct_c_s_l___dss_safety_chk_cfg.html#aa0b0d70dc3629906f279027fe788d52f">CSL_DssSafetyChkCfg</a>
+</li>
+<li>safetyChkMode
+: <a class="el" href="struct_c_s_l___dss_safety_chk_cfg.html#ae4777be78384a09ac1e76eaa5ef925f6">CSL_DssSafetyChkCfg</a>
+</li>
+<li>safetyRegionEnable
+: <a class="el" href="struct_dss___dctrl_region_safety_chk_cfg.html#a1fce7a9f3745d77fc11cac0b45bd7ae0">Dss_DctrlRegionSafetyChkCfg</a>
+</li>
+<li>safetySignSeedVal
+: <a class="el" href="struct_dss___dctrl_vp_safety_chk_params.html#a673816f47183a4e18606ec70a01292ec">Dss_DctrlVpSafetyChkParams</a>
+, <a class="el" href="struct_dss___disp_pipe_safety_chk_params.html#a806bdd67b98f5ad01597e70ea7c2ce9c">Dss_DispPipeSafetyChkParams</a>
+</li>
+<li>safetyViolation
+: <a class="el" href="struct_dss___dctrl_vp_error_stats.html#a9a3c57243d5e6622e5bd4fff8ab95cd4">Dss_DctrlVpErrorStats</a>
+</li>
+<li>safetyViolationCount
+: <a class="el" href="struct_dss___disp_current_status.html#a2de8eed6f459af208ad159c02ebfbab0">Dss_DispCurrentStatus</a>
+</li>
+<li>scanFormat
+: <a class="el" href="struct_fvid2___format.html#a8caf0c6c3ab4f84dfcbfdc23958cc2fa">Fvid2_Format</a>
+, <a class="el" href="struct_fvid2___mode_info.html#a9f9211f1783dadb46fe4f24fe44bf205">Fvid2_ModeInfo</a>
+</li>
+<li>scEnable
+: <a class="el" href="struct_c_s_l___dss_vid_pipe_cfg.html#a558ff6d8e56438ce6f4e573a4e28cbc5">CSL_DssVidPipeCfg</a>
+</li>
+<li>scParams
+: <a class="el" href="struct_dss___disp_rt_params.html#ac3d56cce7d4cae6e8baee8e4784b77b6">Dss_DispRtParams</a>
+</li>
+<li>securityViolation
+: <a class="el" href="struct_dss___dctrl_vp_error_stats.html#a54b7302e5365b28c21f1678322860d3f">Dss_DctrlVpErrorStats</a>
+</li>
+<li>seedSelectEnable
+: <a class="el" href="struct_c_s_l___dss_safety_chk_cfg.html#a125d8cffdb194601754cf97d2a56c00b">CSL_DssSafetyChkCfg</a>
+</li>
+<li>selfRefreshControl
+: <a class="el" href="struct_c_s_l___dss_vid_pipe_dma_cfg.html#a59b2e750c7a9bb8ae5141829f98ccaed">CSL_DssVidPipeDmaCfg</a>
+</li>
+<li>selfRefreshEnable
+: <a class="el" href="struct_c_s_l___dss_vid_pipe_dma_cfg.html#aea2c8225738ca8620eb2af07690db604">CSL_DssVidPipeDmaCfg</a>
+</li>
+<li>socParams
+: <a class="el" href="struct_dss___init_params.html#aa8b798f4f03fcfb8bd59b04999d448a8">Dss_InitParams</a>
+</li>
+<li>standard
+: <a class="el" href="struct_dss___disp_create_status.html#ae7ddd0a663c8bcbaf6ddb9339f3257cf">Dss_DispCreateStatus</a>
+, <a class="el" href="struct_fvid2___mode_info.html#a8c27c6fb4272816c4708e23e66ea4c40">Fvid2_ModeInfo</a>
+</li>
+<li>startX
+: <a class="el" href="struct_fvid2___pos_config.html#a162f7d3ab12a8e049147ba10b1743b4f">Fvid2_PosConfig</a>
+</li>
+<li>startY
+: <a class="el" href="struct_fvid2___pos_config.html#a0bdff26f19f3571e6a76db9134644d38">Fvid2_PosConfig</a>
+</li>
+<li>status
+: <a class="el" href="struct_fvid2___frame.html#a16ee5088306c5a6bbf0126549ec005e1">Fvid2_Frame</a>
+</li>
+<li>subFrameInfo
+: <a class="el" href="struct_fvid2___frame.html#a97a3b5dcf677d9e81113358d18d45ffd">Fvid2_Frame</a>
+</li>
+<li>subFrameNum
+: <a class="el" href="struct_fvid2___sub_frame_info.html#a6139adfc91c58651f0344f79781319a4">Fvid2_SubFrameInfo</a>
+</li>
+<li>syncLost
+: <a class="el" href="struct_dss___dctrl_vp_error_stats.html#af272b85724ab489cac4f6ae36797dd15">Dss_DctrlVpErrorStats</a>
+</li>
+<li>syncLostCbFxn
+: <a class="el" href="struct_dss___dctrl_sync_lost_cb_params.html#a5c2ae7356eec440301d5ae9015e0f33a">Dss_DctrlSyncLostCbParams</a>
+</li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/functions_vars_t.html b/packages/ti/drv/dss/docs/doxygen/html/functions_vars_t.html
--- /dev/null
@@ -0,0 +1,100 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Data Fields - Variables</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li class="current"><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="files.html"><span>Files</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow2" class="tabs2">
+ <ul class="tablist">
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li class="current"><a href="functions.html"><span>Data Fields</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow3" class="tabs2">
+ <ul class="tablist">
+ <li><a href="functions.html"><span>All</span></a></li>
+ <li class="current"><a href="functions_vars.html"><span>Variables</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow4" class="tabs3">
+ <ul class="tablist">
+ <li><a href="functions_vars.html#index_a"><span>a</span></a></li>
+ <li><a href="functions_vars_b.html#index_b"><span>b</span></a></li>
+ <li><a href="functions_vars_c.html#index_c"><span>c</span></a></li>
+ <li><a href="functions_vars_d.html#index_d"><span>d</span></a></li>
+ <li><a href="functions_vars_e.html#index_e"><span>e</span></a></li>
+ <li><a href="functions_vars_f.html#index_f"><span>f</span></a></li>
+ <li><a href="functions_vars_g.html#index_g"><span>g</span></a></li>
+ <li><a href="functions_vars_h.html#index_h"><span>h</span></a></li>
+ <li><a href="functions_vars_i.html#index_i"><span>i</span></a></li>
+ <li><a href="functions_vars_l.html#index_l"><span>l</span></a></li>
+ <li><a href="functions_vars_m.html#index_m"><span>m</span></a></li>
+ <li><a href="functions_vars_n.html#index_n"><span>n</span></a></li>
+ <li><a href="functions_vars_o.html#index_o"><span>o</span></a></li>
+ <li><a href="functions_vars_p.html#index_p"><span>p</span></a></li>
+ <li><a href="functions_vars_q.html#index_q"><span>q</span></a></li>
+ <li><a href="functions_vars_r.html#index_r"><span>r</span></a></li>
+ <li><a href="functions_vars_s.html#index_s"><span>s</span></a></li>
+ <li class="current"><a href="functions_vars_t.html#index_t"><span>t</span></a></li>
+ <li><a href="functions_vars_u.html#index_u"><span>u</span></a></li>
+ <li><a href="functions_vars_v.html#index_v"><span>v</span></a></li>
+ <li><a href="functions_vars_w.html#index_w"><span>w</span></a></li>
+ <li><a href="functions_vars_y.html#index_y"><span>y</span></a></li>
+ </ul>
+ </div>
+</div><!-- top -->
+<div class="contents">
+ 
+
+<h3><a class="anchor" id="index_t"></a>- t -</h3><ul>
+<li>tdmCycleFormat
+: <a class="el" href="struct_c_s_l___dss_vp_lcd_tdm_cfg.html#ae96d7a4d10f0aba11ae1fe050bbb4bae">CSL_DssVpLcdTdmCfg</a>
+</li>
+<li>tdmEnable
+: <a class="el" href="struct_c_s_l___dss_vp_lcd_tdm_cfg.html#abb0166aec4ae051ab0dd636877340902">CSL_DssVpLcdTdmCfg</a>
+</li>
+<li>tdmParallelMode
+: <a class="el" href="struct_c_s_l___dss_vp_lcd_tdm_cfg.html#aba88a2bb1746761f7406f66d04f5412a">CSL_DssVpLcdTdmCfg</a>
+</li>
+<li>tdmUnusedBitsLevel
+: <a class="el" href="struct_c_s_l___dss_vp_lcd_tdm_cfg.html#aa36d89a896199beac0c818f878730876">CSL_DssVpLcdTdmCfg</a>
+</li>
+<li>thresholdHigh
+: <a class="el" href="struct_c_s_l___dss_vid_pipe_m_flag_cfg.html#a9457e4916f1490c14f3b1bda1b56db8a">CSL_DssVidPipeMFlagCfg</a>
+</li>
+<li>thresholdLow
+: <a class="el" href="struct_c_s_l___dss_vid_pipe_m_flag_cfg.html#a10d1d9efb5a2b9c52b87f74b73c3b7ae">CSL_DssVidPipeMFlagCfg</a>
+</li>
+<li>thresholdValue
+: <a class="el" href="struct_c_s_l___dss_safety_chk_cfg.html#a2ab0df15747d286392ad903768bd82c1">CSL_DssSafetyChkCfg</a>
+</li>
+<li>timeStamp64
+: <a class="el" href="struct_fvid2___frame.html#a4563054a2f01febf65268dafa538f70c">Fvid2_Frame</a>
+</li>
+<li>transColorKeyMax
+: <a class="el" href="struct_c_s_l___dss_overlay_cfg.html#a30d4c1ba3e4ac96fd6618a450b95ee37">CSL_DssOverlayCfg</a>
+</li>
+<li>transColorKeyMin
+: <a class="el" href="struct_c_s_l___dss_overlay_cfg.html#a25f45603756892cc7bc3f43d840d94bb">CSL_DssOverlayCfg</a>
+</li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/functions_vars_u.html b/packages/ti/drv/dss/docs/doxygen/html/functions_vars_u.html
--- /dev/null
@@ -0,0 +1,76 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Data Fields - Variables</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li class="current"><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="files.html"><span>Files</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow2" class="tabs2">
+ <ul class="tablist">
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li class="current"><a href="functions.html"><span>Data Fields</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow3" class="tabs2">
+ <ul class="tablist">
+ <li><a href="functions.html"><span>All</span></a></li>
+ <li class="current"><a href="functions_vars.html"><span>Variables</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow4" class="tabs3">
+ <ul class="tablist">
+ <li><a href="functions_vars.html#index_a"><span>a</span></a></li>
+ <li><a href="functions_vars_b.html#index_b"><span>b</span></a></li>
+ <li><a href="functions_vars_c.html#index_c"><span>c</span></a></li>
+ <li><a href="functions_vars_d.html#index_d"><span>d</span></a></li>
+ <li><a href="functions_vars_e.html#index_e"><span>e</span></a></li>
+ <li><a href="functions_vars_f.html#index_f"><span>f</span></a></li>
+ <li><a href="functions_vars_g.html#index_g"><span>g</span></a></li>
+ <li><a href="functions_vars_h.html#index_h"><span>h</span></a></li>
+ <li><a href="functions_vars_i.html#index_i"><span>i</span></a></li>
+ <li><a href="functions_vars_l.html#index_l"><span>l</span></a></li>
+ <li><a href="functions_vars_m.html#index_m"><span>m</span></a></li>
+ <li><a href="functions_vars_n.html#index_n"><span>n</span></a></li>
+ <li><a href="functions_vars_o.html#index_o"><span>o</span></a></li>
+ <li><a href="functions_vars_p.html#index_p"><span>p</span></a></li>
+ <li><a href="functions_vars_q.html#index_q"><span>q</span></a></li>
+ <li><a href="functions_vars_r.html#index_r"><span>r</span></a></li>
+ <li><a href="functions_vars_s.html#index_s"><span>s</span></a></li>
+ <li><a href="functions_vars_t.html#index_t"><span>t</span></a></li>
+ <li class="current"><a href="functions_vars_u.html#index_u"><span>u</span></a></li>
+ <li><a href="functions_vars_v.html#index_v"><span>v</span></a></li>
+ <li><a href="functions_vars_w.html#index_w"><span>w</span></a></li>
+ <li><a href="functions_vars_y.html#index_y"><span>y</span></a></li>
+ </ul>
+ </div>
+</div><!-- top -->
+<div class="contents">
+ 
+
+<h3><a class="anchor" id="index_u"></a>- u -</h3><ul>
+<li>underFlowCbFxn
+: <a class="el" href="struct_dss___disp_under_flow_cb_params.html#a60686aad091a413400037ab52ee52c5a">Dss_DispUnderFlowCbParams</a>
+</li>
+<li>underflowCount
+: <a class="el" href="struct_dss___disp_current_status.html#abe96e5d704939af373e8a533790d5875">Dss_DispCurrentStatus</a>
+</li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/functions_vars_v.html b/packages/ti/drv/dss/docs/doxygen/html/functions_vars_v.html
--- /dev/null
@@ -0,0 +1,110 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Data Fields - Variables</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li class="current"><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="files.html"><span>Files</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow2" class="tabs2">
+ <ul class="tablist">
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li class="current"><a href="functions.html"><span>Data Fields</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow3" class="tabs2">
+ <ul class="tablist">
+ <li><a href="functions.html"><span>All</span></a></li>
+ <li class="current"><a href="functions_vars.html"><span>Variables</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow4" class="tabs3">
+ <ul class="tablist">
+ <li><a href="functions_vars.html#index_a"><span>a</span></a></li>
+ <li><a href="functions_vars_b.html#index_b"><span>b</span></a></li>
+ <li><a href="functions_vars_c.html#index_c"><span>c</span></a></li>
+ <li><a href="functions_vars_d.html#index_d"><span>d</span></a></li>
+ <li><a href="functions_vars_e.html#index_e"><span>e</span></a></li>
+ <li><a href="functions_vars_f.html#index_f"><span>f</span></a></li>
+ <li><a href="functions_vars_g.html#index_g"><span>g</span></a></li>
+ <li><a href="functions_vars_h.html#index_h"><span>h</span></a></li>
+ <li><a href="functions_vars_i.html#index_i"><span>i</span></a></li>
+ <li><a href="functions_vars_l.html#index_l"><span>l</span></a></li>
+ <li><a href="functions_vars_m.html#index_m"><span>m</span></a></li>
+ <li><a href="functions_vars_n.html#index_n"><span>n</span></a></li>
+ <li><a href="functions_vars_o.html#index_o"><span>o</span></a></li>
+ <li><a href="functions_vars_p.html#index_p"><span>p</span></a></li>
+ <li><a href="functions_vars_q.html#index_q"><span>q</span></a></li>
+ <li><a href="functions_vars_r.html#index_r"><span>r</span></a></li>
+ <li><a href="functions_vars_s.html#index_s"><span>s</span></a></li>
+ <li><a href="functions_vars_t.html#index_t"><span>t</span></a></li>
+ <li><a href="functions_vars_u.html#index_u"><span>u</span></a></li>
+ <li class="current"><a href="functions_vars_v.html#index_v"><span>v</span></a></li>
+ <li><a href="functions_vars_w.html#index_w"><span>w</span></a></li>
+ <li><a href="functions_vars_y.html#index_y"><span>y</span></a></li>
+ </ul>
+ </div>
+</div><!-- top -->
+<div class="contents">
+ 
+
+<h3><a class="anchor" id="index_v"></a>- v -</h3><ul>
+<li>vBackPorch
+: <a class="el" href="struct_c_s_l___dss_vp_lcd_blank_timing_cfg.html#aa47f7bea5a1b26d347984a25769e5424">CSL_DssVpLcdBlankTimingCfg</a>
+, <a class="el" href="struct_fvid2___mode_info.html#a9ade9b5bd46517cb5cfd0590585cbc33">Fvid2_ModeInfo</a>
+</li>
+<li>vc1Cfg
+: <a class="el" href="struct_dss___disp_params.html#a706397a3b18a877996fbf8f8276ab2e4">Dss_DispParams</a>
+</li>
+<li>vc1Enable
+: <a class="el" href="struct_c_s_l___dss_vid_pipe_v_c1_cfg.html#afd21865a4ea9a111674749d13e2aeec1">CSL_DssVidPipeVC1Cfg</a>
+</li>
+<li>vFrontPorch
+: <a class="el" href="struct_c_s_l___dss_vp_lcd_blank_timing_cfg.html#a0155b917c75ee07e575746a3e3e431d3">CSL_DssVpLcdBlankTimingCfg</a>
+, <a class="el" href="struct_fvid2___mode_info.html#a806ac4325f4edcaf2b7dca12a5051149">Fvid2_ModeInfo</a>
+</li>
+<li>videoIfWidth
+: <a class="el" href="struct_c_s_l___dss_vp_lcd_op_timing_cfg.html#a9967666ac6fea7f27b7fcfd6e4da55a6">CSL_DssVpLcdOpTimingCfg</a>
+</li>
+<li>vpId
+: <a class="el" href="struct_dss___dctrl_adv_vp_params.html#afd01ce9227b77bec352c157f1105b622">Dss_DctrlAdvVpParams</a>
+, <a class="el" href="struct_dss___dctrl_lcd_blank_timing_params.html#ae1b052eccedf552786588d1c7ae16172">Dss_DctrlLcdBlankTimingParams</a>
+, <a class="el" href="struct_dss___dctrl_oldi_params.html#a05de5db50e555596e3ec6402b2342bb4">Dss_DctrlOldiParams</a>
+, <a class="el" href="struct_dss___dctrl_sync_lost_cb_params.html#a61ef10a6d3eba7bc313a97aa0030a235">Dss_DctrlSyncLostCbParams</a>
+, <a class="el" href="struct_dss___dctrl_vp_csc_coeff.html#a203077028ae50d9ca4db3c325d40dc1b">Dss_DctrlVpCscCoeff</a>
+, <a class="el" href="struct_dss___dctrl_vp_error_stats.html#a557f21aa6cf21d93cbb30621de72ecb0">Dss_DctrlVpErrorStats</a>
+, <a class="el" href="struct_dss___dctrl_vp_params.html#aa76e94e775ed4a9146ebc8fc937c904e">Dss_DctrlVpParams</a>
+, <a class="el" href="struct_dss___dctrl_vp_safety_chk_params.html#a034f526bd2e786a118ebb9a84e5c5cb8">Dss_DctrlVpSafetyChkParams</a>
+</li>
+<li>vpSafetyChkCfg
+: <a class="el" href="struct_dss___dctrl_vp_safety_chk_params.html#a79a3554cac97f602e452fc5ae125288e">Dss_DctrlVpSafetyChkParams</a>
+</li>
+<li>vsPolarity
+: <a class="el" href="struct_c_s_l___dss_vp_lcd_signal_polarity_cfg.html#af04cf78189cce9f85c441bf4e22f23d7">CSL_DssVpLcdSignalPolarityCfg</a>
+</li>
+<li>vSyncGated
+: <a class="el" href="struct_c_s_l___dss_vp_lcd_adv_signal_cfg.html#a8ff089c8259760a24199389c68519338">CSL_DssVpLcdAdvSignalCfg</a>
+</li>
+<li>vSyncLen
+: <a class="el" href="struct_c_s_l___dss_vp_lcd_blank_timing_cfg.html#aac23b4702301fa2aa6a64ac5299fd2ba">CSL_DssVpLcdBlankTimingCfg</a>
+, <a class="el" href="struct_fvid2___mode_info.html#a2b756eece94e9a720028ece8d50991b3">Fvid2_ModeInfo</a>
+</li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/functions_vars_w.html b/packages/ti/drv/dss/docs/doxygen/html/functions_vars_w.html
--- /dev/null
@@ -0,0 +1,76 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Data Fields - Variables</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li class="current"><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="files.html"><span>Files</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow2" class="tabs2">
+ <ul class="tablist">
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li class="current"><a href="functions.html"><span>Data Fields</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow3" class="tabs2">
+ <ul class="tablist">
+ <li><a href="functions.html"><span>All</span></a></li>
+ <li class="current"><a href="functions_vars.html"><span>Variables</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow4" class="tabs3">
+ <ul class="tablist">
+ <li><a href="functions_vars.html#index_a"><span>a</span></a></li>
+ <li><a href="functions_vars_b.html#index_b"><span>b</span></a></li>
+ <li><a href="functions_vars_c.html#index_c"><span>c</span></a></li>
+ <li><a href="functions_vars_d.html#index_d"><span>d</span></a></li>
+ <li><a href="functions_vars_e.html#index_e"><span>e</span></a></li>
+ <li><a href="functions_vars_f.html#index_f"><span>f</span></a></li>
+ <li><a href="functions_vars_g.html#index_g"><span>g</span></a></li>
+ <li><a href="functions_vars_h.html#index_h"><span>h</span></a></li>
+ <li><a href="functions_vars_i.html#index_i"><span>i</span></a></li>
+ <li><a href="functions_vars_l.html#index_l"><span>l</span></a></li>
+ <li><a href="functions_vars_m.html#index_m"><span>m</span></a></li>
+ <li><a href="functions_vars_n.html#index_n"><span>n</span></a></li>
+ <li><a href="functions_vars_o.html#index_o"><span>o</span></a></li>
+ <li><a href="functions_vars_p.html#index_p"><span>p</span></a></li>
+ <li><a href="functions_vars_q.html#index_q"><span>q</span></a></li>
+ <li><a href="functions_vars_r.html#index_r"><span>r</span></a></li>
+ <li><a href="functions_vars_s.html#index_s"><span>s</span></a></li>
+ <li><a href="functions_vars_t.html#index_t"><span>t</span></a></li>
+ <li><a href="functions_vars_u.html#index_u"><span>u</span></a></li>
+ <li><a href="functions_vars_v.html#index_v"><span>v</span></a></li>
+ <li class="current"><a href="functions_vars_w.html#index_w"><span>w</span></a></li>
+ <li><a href="functions_vars_y.html#index_y"><span>y</span></a></li>
+ </ul>
+ </div>
+</div><!-- top -->
+<div class="contents">
+ 
+
+<h3><a class="anchor" id="index_w"></a>- w -</h3><ul>
+<li>width
+: <a class="el" href="struct_dss___frame_rt_params.html#a12e945cb05d7fb6f7732c22b7a5f314c">Dss_FrameRtParams</a>
+, <a class="el" href="struct_fvid2___format.html#ae8fa2690ac1bef44b56d546a6b0cce6f">Fvid2_Format</a>
+, <a class="el" href="struct_fvid2___mode_info.html#a65e201988503365e459cd3464c3a8b8d">Fvid2_ModeInfo</a>
+, <a class="el" href="struct_fvid2___size_config.html#a53d5200a448e56564f80fcd92863596d">Fvid2_SizeConfig</a>
+</li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/functions_vars_y.html b/packages/ti/drv/dss/docs/doxygen/html/functions_vars_y.html
--- /dev/null
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+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Data Fields - Variables</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li class="current"><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="files.html"><span>Files</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow2" class="tabs2">
+ <ul class="tablist">
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li class="current"><a href="functions.html"><span>Data Fields</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow3" class="tabs2">
+ <ul class="tablist">
+ <li><a href="functions.html"><span>All</span></a></li>
+ <li class="current"><a href="functions_vars.html"><span>Variables</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow4" class="tabs3">
+ <ul class="tablist">
+ <li><a href="functions_vars.html#index_a"><span>a</span></a></li>
+ <li><a href="functions_vars_b.html#index_b"><span>b</span></a></li>
+ <li><a href="functions_vars_c.html#index_c"><span>c</span></a></li>
+ <li><a href="functions_vars_d.html#index_d"><span>d</span></a></li>
+ <li><a href="functions_vars_e.html#index_e"><span>e</span></a></li>
+ <li><a href="functions_vars_f.html#index_f"><span>f</span></a></li>
+ <li><a href="functions_vars_g.html#index_g"><span>g</span></a></li>
+ <li><a href="functions_vars_h.html#index_h"><span>h</span></a></li>
+ <li><a href="functions_vars_i.html#index_i"><span>i</span></a></li>
+ <li><a href="functions_vars_l.html#index_l"><span>l</span></a></li>
+ <li><a href="functions_vars_m.html#index_m"><span>m</span></a></li>
+ <li><a href="functions_vars_n.html#index_n"><span>n</span></a></li>
+ <li><a href="functions_vars_o.html#index_o"><span>o</span></a></li>
+ <li><a href="functions_vars_p.html#index_p"><span>p</span></a></li>
+ <li><a href="functions_vars_q.html#index_q"><span>q</span></a></li>
+ <li><a href="functions_vars_r.html#index_r"><span>r</span></a></li>
+ <li><a href="functions_vars_s.html#index_s"><span>s</span></a></li>
+ <li><a href="functions_vars_t.html#index_t"><span>t</span></a></li>
+ <li><a href="functions_vars_u.html#index_u"><span>u</span></a></li>
+ <li><a href="functions_vars_v.html#index_v"><span>v</span></a></li>
+ <li><a href="functions_vars_w.html#index_w"><span>w</span></a></li>
+ <li class="current"><a href="functions_vars_y.html#index_y"><span>y</span></a></li>
+ </ul>
+ </div>
+</div><!-- top -->
+<div class="contents">
+ 
+
+<h3><a class="anchor" id="index_y"></a>- y -</h3><ul>
+<li>yuvAlign
+: <a class="el" href="struct_c_s_l___dss_vid_pipe_cfg.html#a3926c260e814c53179d80058a595935c">CSL_DssVidPipeCfg</a>
+</li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/functions_w.html b/packages/ti/drv/dss/docs/doxygen/html/functions_w.html
--- /dev/null
@@ -0,0 +1,76 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li class="current"><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="files.html"><span>Files</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow2" class="tabs2">
+ <ul class="tablist">
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li class="current"><a href="functions.html"><span>Data Fields</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow3" class="tabs2">
+ <ul class="tablist">
+ <li class="current"><a href="functions.html"><span>All</span></a></li>
+ <li><a href="functions_vars.html"><span>Variables</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow4" class="tabs3">
+ <ul class="tablist">
+ <li><a href="functions.html#index_a"><span>a</span></a></li>
+ <li><a href="functions_b.html#index_b"><span>b</span></a></li>
+ <li><a href="functions_c.html#index_c"><span>c</span></a></li>
+ <li><a href="functions_d.html#index_d"><span>d</span></a></li>
+ <li><a href="functions_e.html#index_e"><span>e</span></a></li>
+ <li><a href="functions_f.html#index_f"><span>f</span></a></li>
+ <li><a href="functions_g.html#index_g"><span>g</span></a></li>
+ <li><a href="functions_h.html#index_h"><span>h</span></a></li>
+ <li><a href="functions_i.html#index_i"><span>i</span></a></li>
+ <li><a href="functions_l.html#index_l"><span>l</span></a></li>
+ <li><a href="functions_m.html#index_m"><span>m</span></a></li>
+ <li><a href="functions_n.html#index_n"><span>n</span></a></li>
+ <li><a href="functions_o.html#index_o"><span>o</span></a></li>
+ <li><a href="functions_p.html#index_p"><span>p</span></a></li>
+ <li><a href="functions_q.html#index_q"><span>q</span></a></li>
+ <li><a href="functions_r.html#index_r"><span>r</span></a></li>
+ <li><a href="functions_s.html#index_s"><span>s</span></a></li>
+ <li><a href="functions_t.html#index_t"><span>t</span></a></li>
+ <li><a href="functions_u.html#index_u"><span>u</span></a></li>
+ <li><a href="functions_v.html#index_v"><span>v</span></a></li>
+ <li class="current"><a href="functions_w.html#index_w"><span>w</span></a></li>
+ <li><a href="functions_y.html#index_y"><span>y</span></a></li>
+ </ul>
+ </div>
+</div><!-- top -->
+<div class="contents">
+<div class="textblock">Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:</div>
+
+<h3><a class="anchor" id="index_w"></a>- w -</h3><ul>
+<li>width
+: <a class="el" href="struct_dss___frame_rt_params.html#a12e945cb05d7fb6f7732c22b7a5f314c">Dss_FrameRtParams</a>
+, <a class="el" href="struct_fvid2___format.html#ae8fa2690ac1bef44b56d546a6b0cce6f">Fvid2_Format</a>
+, <a class="el" href="struct_fvid2___mode_info.html#a65e201988503365e459cd3464c3a8b8d">Fvid2_ModeInfo</a>
+, <a class="el" href="struct_fvid2___size_config.html#a53d5200a448e56564f80fcd92863596d">Fvid2_SizeConfig</a>
+</li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/functions_y.html b/packages/ti/drv/dss/docs/doxygen/html/functions_y.html
--- /dev/null
@@ -0,0 +1,73 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Data Fields</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li class="current"><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="files.html"><span>Files</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow2" class="tabs2">
+ <ul class="tablist">
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li class="current"><a href="functions.html"><span>Data Fields</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow3" class="tabs2">
+ <ul class="tablist">
+ <li class="current"><a href="functions.html"><span>All</span></a></li>
+ <li><a href="functions_vars.html"><span>Variables</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow4" class="tabs3">
+ <ul class="tablist">
+ <li><a href="functions.html#index_a"><span>a</span></a></li>
+ <li><a href="functions_b.html#index_b"><span>b</span></a></li>
+ <li><a href="functions_c.html#index_c"><span>c</span></a></li>
+ <li><a href="functions_d.html#index_d"><span>d</span></a></li>
+ <li><a href="functions_e.html#index_e"><span>e</span></a></li>
+ <li><a href="functions_f.html#index_f"><span>f</span></a></li>
+ <li><a href="functions_g.html#index_g"><span>g</span></a></li>
+ <li><a href="functions_h.html#index_h"><span>h</span></a></li>
+ <li><a href="functions_i.html#index_i"><span>i</span></a></li>
+ <li><a href="functions_l.html#index_l"><span>l</span></a></li>
+ <li><a href="functions_m.html#index_m"><span>m</span></a></li>
+ <li><a href="functions_n.html#index_n"><span>n</span></a></li>
+ <li><a href="functions_o.html#index_o"><span>o</span></a></li>
+ <li><a href="functions_p.html#index_p"><span>p</span></a></li>
+ <li><a href="functions_q.html#index_q"><span>q</span></a></li>
+ <li><a href="functions_r.html#index_r"><span>r</span></a></li>
+ <li><a href="functions_s.html#index_s"><span>s</span></a></li>
+ <li><a href="functions_t.html#index_t"><span>t</span></a></li>
+ <li><a href="functions_u.html#index_u"><span>u</span></a></li>
+ <li><a href="functions_v.html#index_v"><span>v</span></a></li>
+ <li><a href="functions_w.html#index_w"><span>w</span></a></li>
+ <li class="current"><a href="functions_y.html#index_y"><span>y</span></a></li>
+ </ul>
+ </div>
+</div><!-- top -->
+<div class="contents">
+<div class="textblock">Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:</div>
+
+<h3><a class="anchor" id="index_y"></a>- y -</h3><ul>
+<li>yuvAlign
+: <a class="el" href="struct_c_s_l___dss_vid_pipe_cfg.html#a3926c260e814c53179d80058a595935c">CSL_DssVidPipeCfg</a>
+</li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/globals.html b/packages/ti/drv/dss/docs/doxygen/html/globals.html
--- /dev/null
@@ -0,0 +1,722 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Globals</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li class="current"><a href="files.html"><span>Files</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow2" class="tabs2">
+ <ul class="tablist">
+ <li><a href="files.html"><span>File List</span></a></li>
+ <li class="current"><a href="globals.html"><span>Globals</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow3" class="tabs2">
+ <ul class="tablist">
+ <li class="current"><a href="globals.html"><span>All</span></a></li>
+ <li><a href="globals_func.html"><span>Functions</span></a></li>
+ <li><a href="globals_type.html"><span>Typedefs</span></a></li>
+ <li><a href="globals_enum.html"><span>Enumerations</span></a></li>
+ <li><a href="globals_eval.html"><span>Enumerator</span></a></li>
+ <li><a href="globals_defs.html"><span>Macros</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow4" class="tabs3">
+ <ul class="tablist">
+ <li class="current"><a href="globals.html#index_c"><span>c</span></a></li>
+ <li><a href="globals_d.html#index_d"><span>d</span></a></li>
+ <li><a href="globals_f.html#index_f"><span>f</span></a></li>
+ <li><a href="globals_i.html#index_i"><span>i</span></a></li>
+ </ul>
+ </div>
+</div><!-- top -->
+<div class="contents">
+<div class="textblock">Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation:</div>
+
+<h3><a class="anchor" id="index_c"></a>- c -</h3><ul>
+<li>CSL_DSS_COMM_REG_ID_0
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gaba6b3367cbe7db1f57b4693234fbcd86">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_COMM_REG_ID_0_MASK
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga8e4fccb97063f3a1a8ae7a0a45f7de7b">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_COMM_REG_ID_1
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga961c35c051c33b4e92691db8a5ee749d">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_COMM_REG_ID_1_MASK
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga4b279b40e6fa88217af7df5242fdd007">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_COMM_REG_ID_2
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gafaece2043fd351a5f7f8b5b1628921c7">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_COMM_REG_ID_2_MASK
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gafdceb9e1230dd80ea4e7da1689f9ffba">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_COMM_REG_ID_3
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga22dc72847784f75cad78a4c2a3b3f217">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_COMM_REG_ID_3_MASK
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga6ae3cbe4e7f4e35054a0f8f1d739ed83">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_COMM_REG_ID_MAX
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gab1b9457684eda680598c1bc8a574e20c">csl_dssTop.h</a>
+</li>
+<li>CSL_dss_commRegs
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1b5d2dc642484dd5b5af1cd7db50ef74">csl_dssCommon.h</a>
+</li>
+<li>CSL_DSS_CSC_RANGE_FULL
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga2b1f7a9fccfe834266cc61dbab22a7f2">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_CSC_RANGE_LIMITED
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga3041c8743595f7ce5d8ebb59cf32bcc4">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_DISPC_INTR_VID1_MASK
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga06e5097b8fb8b1581b289d1e4c5f8b1d">csl_dssCommon.h</a>
+</li>
+<li>CSL_DSS_DISPC_INTR_VID2_MASK
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga3e9bb13013658677983d41d243db6530">csl_dssCommon.h</a>
+</li>
+<li>CSL_DSS_DISPC_INTR_VIDL1_MASK
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gabee1d0a280ee911c3f3863343167c034">csl_dssCommon.h</a>
+</li>
+<li>CSL_DSS_DISPC_INTR_VIDL2_MASK
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gaca4d1f25e688c3c257df26fbed1bf0b0">csl_dssCommon.h</a>
+</li>
+<li>CSL_DSS_DISPC_INTR_VP1_MASK
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga9c7a9966f4f00cf84f8522ae35009f6f">csl_dssCommon.h</a>
+</li>
+<li>CSL_DSS_DISPC_INTR_VP2_MASK
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga7c9437915888ed76ced5942c24acf8e7">csl_dssCommon.h</a>
+</li>
+<li>CSL_DSS_DISPC_INTR_VP3_MASK
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga72e1189718d84be73378a1c7243668d0">csl_dssCommon.h</a>
+</li>
+<li>CSL_DSS_DISPC_INTR_VP4_MASK
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga4663d2526dbf5150b3173715ee5bf049">csl_dssCommon.h</a>
+</li>
+<li>CSL_DSS_DISPC_INTR_WB_MASK
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1c3a6a248c34ffb2b8183155f96107c9">csl_dssCommon.h</a>
+</li>
+<li>CSL_DSS_DPI_ID_0
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga9679d96bb4a54cf7e8ce0a22bf034ce3">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_DPI_ID_1
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga2ef99175d7ba50686f9d3b55484099d3">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_DPI_ID_2
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga2fcf2f843406ec0ff1ee6ec29156576e">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_DPI_ID_3
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga3e2b38794f954faea2bf1769d25c2bd3">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_DPI_ID_4
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga92854e551ae60a5d40c9c5c1c8326092">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_DPI_ID_5
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gad22d8422668bd5e965c0611d4c80ca36">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_DPI_ID_MAX
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga53c1ac5fbf207e8f973902051404e51e">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_MFLAG_CTRL_DISABLED
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga8a1fdde2ee44a5d4f758add66d1e531a">csl_dssCommon.h</a>
+</li>
+<li>CSL_DSS_MFLAG_CTRL_DYNAMIC
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gafd85bc61dad64ede428e21526edd470a">csl_dssCommon.h</a>
+</li>
+<li>CSL_DSS_MFLAG_CTRL_FORCE_ENABLE
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gae33f049f22cfce779d267a22ba79d1e3">csl_dssCommon.h</a>
+</li>
+<li>CSL_DSS_MFLAG_START_FORCED
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga25a7a13a5ed7fa79de52587991cd6e8c">csl_dssCommon.h</a>
+</li>
+<li>CSL_DSS_MFLAG_START_NORMAL
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga8463a9a268552ec6233a928947813a7d">csl_dssCommon.h</a>
+</li>
+<li>CSL_DSS_MODULE_INVALID
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gaa7973f4d3301c7360cdbcc6f60c6e8fb">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_NUM_LUT_ENTRIES
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gac8a30c5680379b12128e75859e9f2312">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_OVERLAY_ID_1
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga5acb54b8623189d18b4211a24a0ddb8c">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_OVERLAY_ID_1_MASK
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gab66410f4f933b9c077e3f9d294436073">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_OVERLAY_ID_2
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga37edd061f4545fb5bcaf98fb0e29f49c">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_OVERLAY_ID_2_MASK
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gac474fcd4a03b4204c8cf584ba7b105e2">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_OVERLAY_ID_3
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga4cc372289cf4841713a3fff407e519ec">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_OVERLAY_ID_3_MASK
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gaa3f86a021fef86c1bdf2d94e122143c2">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_OVERLAY_ID_4
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gae8da1ca2c825364e430e6bb94a11c8de">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_OVERLAY_ID_4_MASK
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga80bbc7f730eed3ab5d593b450858375e">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_OVERLAY_ID_MAX
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga41df77f605b2d5c6e107fd4b0df61220">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_OVERLAY_LAYER_INVALID
+: <a class="el" href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#gae0d0be4608934fba2afa072b6716220a">csl_dssOverlay.h</a>
+</li>
+<li>CSL_DSS_OVERLAY_LAYER_MAX
+: <a class="el" href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#ga2a682ed470d58605922ee2106033a5f8">csl_dssOverlay.h</a>
+</li>
+<li>CSL_DSS_OVERLAY_LAYER_NUM_0
+: <a class="el" href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#ga2488889aa0b927be4a00ec57b8b75f70">csl_dssOverlay.h</a>
+</li>
+<li>CSL_DSS_OVERLAY_LAYER_NUM_1
+: <a class="el" href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#gabe9d38d2a4ef636da3b3a261cbb94f71">csl_dssOverlay.h</a>
+</li>
+<li>CSL_DSS_OVERLAY_LAYER_NUM_2
+: <a class="el" href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#ga97d71d9f152602cd81c45e7cdfa3a92d">csl_dssOverlay.h</a>
+</li>
+<li>CSL_DSS_OVERLAY_LAYER_NUM_3
+: <a class="el" href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#ga4f0066fbe34c973483392a7128eb598a">csl_dssOverlay.h</a>
+</li>
+<li>CSL_DSS_OVERLAY_TRANS_COLOR_DEST
+: <a class="el" href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#ga340c7a53b58c9fed267c3164ec0a03c9">csl_dssOverlay.h</a>
+</li>
+<li>CSL_DSS_OVERLAY_TRANS_COLOR_SRC
+: <a class="el" href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#ga164f53537368dff35827675dfda8cf12">csl_dssOverlay.h</a>
+</li>
+<li>CSL_dss_overlayRegs
+: <a class="el" href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#ga835adb8a42f16beefbfb5440b9dede63">csl_dssOverlay.h</a>
+</li>
+<li>CSL_dss_pipeRegs
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gafdca0345c9254a9bdbcd6e4a2ee000f6">csl_dssVideoPipe.h</a>
+</li>
+<li>CSL_DSS_SAFETY_CHK_DATA_INTEGRITY
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gabc2f69f2dfaab74b675a923fb14c3489">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_SAFETY_CHK_FRAME_FREEZE_DETECT
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga87bc16f17eb07c0e42f1e00f9ed1ef3e">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_SAFETY_CHK_FRAME_SKIP_EVEN
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga663277190152e9b070a32830bdfab30d">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_SAFETY_CHK_FRAME_SKIP_NO
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga3b3b3a0ec326781390a727d437cd3e59">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_SAFETY_CHK_FRAME_SKIP_ODD
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gafca0e84bf97ed23528e1bc15af0a4e98">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_SAFETY_REGION_0
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gaa3a861b982382bd7387783bf1019576c">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_SAFETY_REGION_1
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gaa104154d768c72acac19f2545460038c">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_SAFETY_REGION_2
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga3ca88d86a0c19685b48ce935c86821bd">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_SAFETY_REGION_3
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga7fecc5cd051151b901deb0dbd6c36201">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_SAFETY_REGION_4
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gabfb09986c4139d4093308e6f708fd582">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_SAFETY_REGION_5
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga83b9053e2bc53689cf537ae19102ff9f">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_SAFETY_REGION_6
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga0e75b3f63a3ad9488a287d1cfe5ff9a5">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_SAFETY_REGION_7
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga20d089acf2d69bd7f86a05eea0093bfa">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_SAFETY_REGION_MAX
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga514efc84b40d7147969434b2d5cff2fe">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_VID_PIPE_ID_MAX
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gafbbd94228f58df3124b2bc9780379cea">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_VID_PIPE_ID_VID1
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gab861a5295a9cd21b01897e1026aa2b79">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_VID_PIPE_ID_VID1_MASK
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gaada71522489dcbd519415f3f81e490d0">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_VID_PIPE_ID_VID2
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gadd35014f4f1e166a6b95a0e80970f9e8">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_VID_PIPE_ID_VID2_MASK
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga1d978b06983e4f19a666abd322a70293">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_VID_PIPE_ID_VIDL1
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga73aee3bb97f91dafe4f9adfd0a0d3bac">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_VID_PIPE_ID_VIDL1_MASK
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga86337ef6c0f0e8ac50c07638c91104c6">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_VID_PIPE_ID_VIDL2
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga9692470b1ffe05c0bf39af6cce81b3dd">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_VID_PIPE_ID_VIDL2_MASK
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga69abb0b78149e8c8880f5ce9f1d7d508">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_VID_PIPE_INTR_ALL_MASK
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gab333a63a9c79c3af6e7b439ad23f6ee7">csl_dssCommon.h</a>
+</li>
+<li>CSL_DSS_VID_PIPE_INTR_BUFUNDERFLOW_MASK
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gac87f5c5a2d6fea0b3be605ef429fa7fa">csl_dssCommon.h</a>
+</li>
+<li>CSL_DSS_VID_PIPE_INTR_FBDC_CORRUPTTILE_MASK
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gaeb0df43d6aa106d64cbae9879d850ab2">csl_dssCommon.h</a>
+</li>
+<li>CSL_DSS_VID_PIPE_INTR_FBDC_ILLEGALTILE_MASK
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gac01c7ef875638b7ac0110c9306e97e03">csl_dssCommon.h</a>
+</li>
+<li>CSL_DSS_VID_PIPE_INTR_SAFETYVIOLATION_MASK
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga5a394bb4a7b00f928e9287c7838a1a7d">csl_dssCommon.h</a>
+</li>
+<li>CSL_DSS_VID_PIPE_INTR_WINDOWEND_MASK
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gaf2e001a112ba432cac5fec625eede116">csl_dssCommon.h</a>
+</li>
+<li>CSL_DSS_VID_PIPE_PRELOAD_CONTROL_HW
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gaddf7744bff3546d7cf3dfcd5f50578e0">csl_dssVideoPipe.h</a>
+</li>
+<li>CSL_DSS_VID_PIPE_PRELOAD_CONTROL_SW
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#ga9920a3ec2d8c5a8707be21d19df2cdca">csl_dssVideoPipe.h</a>
+</li>
+<li>CSL_DSS_VID_PIPE_PRIORITY_HIGH
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gab90746bec79505e7a733d0f2bd72f5c4">csl_dssVideoPipe.h</a>
+</li>
+<li>CSL_DSS_VID_PIPE_PRIORITY_NORMAL
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#ga8d4e4c078fa0fed3f7d3d3739d5ff7cd">csl_dssVideoPipe.h</a>
+</li>
+<li>CSL_DSS_VID_PIPE_REFRESH_CONTROL_HW
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gaa791b8ccb4cccc15ca17524094cfb280">csl_dssVideoPipe.h</a>
+</li>
+<li>CSL_DSS_VID_PIPE_REFRESH_CONTROL_SW
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gacb4282f5d79fd4252da0e6dfc0a6e124">csl_dssVideoPipe.h</a>
+</li>
+<li>CSL_DSS_VID_PIPE_SC_DISABLED
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gabeae764db02ef759820ebc878da5abc7">csl_dssVideoPipe.h</a>
+</li>
+<li>CSL_DSS_VID_PIPE_SC_ENABLED_H
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gae5bb5538c01dcbf3f8b9d1fc52dc385a">csl_dssVideoPipe.h</a>
+</li>
+<li>CSL_DSS_VID_PIPE_SC_ENABLED_HV
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#ga00799c61e0313dc87418c766f836a958">csl_dssVideoPipe.h</a>
+</li>
+<li>CSL_DSS_VID_PIPE_SC_ENABLED_V
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#ga0add9ab4761fdd4bd2a09c4e140a35c0">csl_dssVideoPipe.h</a>
+</li>
+<li>CSL_DSS_VID_PIPE_TYPE_VID
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gae0a57704e2a39702c1d1ac1a861ead86">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_VID_PIPE_TYPE_VIDL
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gab3801fb3aa15ef1b184da3fc2f9ea9ad">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_VID_PIPE_YUV_ALIGN_LSB
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#ga39ea4aaf120f874835b851ed1a0d84af">csl_dssVideoPipe.h</a>
+</li>
+<li>CSL_DSS_VID_PIPE_YUV_ALIGN_MSB
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gaed342608ce368c3c538c10e808a60eef">csl_dssVideoPipe.h</a>
+</li>
+<li>CSL_DSS_VP_CSC_POS_AFTER_GAMMA
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga9d8db056eb5e4a6dc1972200c70acf09">csl_dssVideoPort.h</a>
+</li>
+<li>CSL_DSS_VP_CSC_POS_BEFORE_GAMMA
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga7adc25e7daeddfff398a028a6f7af0b8">csl_dssVideoPort.h</a>
+</li>
+<li>CSL_DSS_VP_FID_FIRST_EVEN
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gab6a1a6b67d60bff5578cc42bc2bc0114">csl_dssVideoPort.h</a>
+</li>
+<li>CSL_DSS_VP_FID_FIRST_ODD
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga62dd57b2769fa39f4459379b8f432465">csl_dssVideoPort.h</a>
+</li>
+<li>CSL_DSS_VP_HVCLK_CONTROL_OFF
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga2b87767e34b62775d52ef6022789bdd0">csl_dssVideoPort.h</a>
+</li>
+<li>CSL_DSS_VP_HVCLK_CONTROL_ON
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gac3a10008ac4fbc32ef1869c751602925">csl_dssVideoPort.h</a>
+</li>
+<li>CSL_DSS_VP_HVSYNC_ALIGNED
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga744ce9e2dba4875d10456de204cdf564">csl_dssVideoPort.h</a>
+</li>
+<li>CSL_DSS_VP_HVSYNC_NOT_ALIGNED
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gab6a57958037687c92ae5d39ef7e4633f">csl_dssVideoPort.h</a>
+</li>
+<li>CSL_DSS_VP_ID_1
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gafbe058ac640cf42ad08afa3b32fb29d1">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_VP_ID_1_MASK
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga2b8bb0130844b328ae5711f9f4b5487b">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_VP_ID_2
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga34118161f4c12f89689b79f5ce09696c">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_VP_ID_2_MASK
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga40b42315f64e4f7290af3f3f2c1f6fb4">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_VP_ID_3
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga657e4b1ceb6955c961961d5c0af3e9b7">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_VP_ID_3_MASK
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gac5818d5d83b12514d8a01d62d6743306">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_VP_ID_4
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga961d6492d4afd198139770cb4b93a5ab">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_VP_ID_4_MASK
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gacabf7b4969d7515d967d243e2e67dd2a">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_VP_ID_MAX
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga0a203752c6295d20389b36d6c2e0de0c">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_VP_INTR_ACBIASCOUNT_MASK
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gaa57aa7b8fc4736ff9598a0b8c5b308c6">csl_dssCommon.h</a>
+</li>
+<li>CSL_DSS_VP_INTR_ALL_MASK
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga062132a334862eff31df843867a5a9c1">csl_dssCommon.h</a>
+</li>
+<li>CSL_DSS_VP_INTR_FRAMEDONE_MASK
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga17a731c79f013dff8a68313609310a14">csl_dssCommon.h</a>
+</li>
+<li>CSL_DSS_VP_INTR_GOBITCLEAR_MASK
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga4b7fe7d3fbf537386925b2118337517d">csl_dssCommon.h</a>
+</li>
+<li>CSL_DSS_VP_INTR_ODDVSYNC_MASK
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga323ac381f7d2dacaa7d710894740d796">csl_dssCommon.h</a>
+</li>
+<li>CSL_DSS_VP_INTR_PROGLINENUM_MASK
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gab542da635c1710ea24c5a29e3e6f150c">csl_dssCommon.h</a>
+</li>
+<li>CSL_DSS_VP_INTR_SAFETYVIOLATION_REGION1_MASK
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gaf396f3733114c9eb5478a5a7852fb09e">csl_dssCommon.h</a>
+</li>
+<li>CSL_DSS_VP_INTR_SAFETYVIOLATION_REGION2_MASK
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gab1798bd63882f1a7da07264aa665a06e">csl_dssCommon.h</a>
+</li>
+<li>CSL_DSS_VP_INTR_SAFETYVIOLATION_REGION3_MASK
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gaf436eb889d4490f9e0fb4b79ebeea6cb">csl_dssCommon.h</a>
+</li>
+<li>CSL_DSS_VP_INTR_SAFETYVIOLATION_REGION4_MASK
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga84dc6d8ce16d3bc5fd19fb1008f53998">csl_dssCommon.h</a>
+</li>
+<li>CSL_DSS_VP_INTR_SAFETYVIOLATION_REGION5_MASK
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga07b59cbeb37e6d5337a4117ecf688973">csl_dssCommon.h</a>
+</li>
+<li>CSL_DSS_VP_INTR_SAFETYVIOLATION_REGION6_MASK
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gab854dd38750979bf152c0bb7d39f10f9">csl_dssCommon.h</a>
+</li>
+<li>CSL_DSS_VP_INTR_SAFETYVIOLATION_REGION7_MASK
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gafd2c9bb5bce5224951f713e6a67951cb">csl_dssCommon.h</a>
+</li>
+<li>CSL_DSS_VP_INTR_SAFETYVIOLATION_REGION8_MASK
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gafee920aa4503ff1c8ec7d91a028802ba">csl_dssCommon.h</a>
+</li>
+<li>CSL_DSS_VP_INTR_SECURITYVIOLATION_MASK
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga2287bdc0f1a6bb8d7c25590cc580d26a">csl_dssCommon.h</a>
+</li>
+<li>CSL_DSS_VP_INTR_SYNCLOST_MASK
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga92903c6e1b355ed60ca8a15c1673c3b9">csl_dssCommon.h</a>
+</li>
+<li>CSL_DSS_VP_INTR_VSYNC_MASK
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1ddaba61f8fa43456fb3d8549f69815f">csl_dssCommon.h</a>
+</li>
+<li>CSL_DSS_VP_LPP_DELTA_MINUSONE
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga1a9e8a871ac9b403dfe0f0d208b3c29f">csl_dssVideoPort.h</a>
+</li>
+<li>CSL_DSS_VP_LPP_DELTA_PLUSONE
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga219596f8e8c8b043dde6c1f05c36f570">csl_dssVideoPort.h</a>
+</li>
+<li>CSL_DSS_VP_LPP_DELTA_ZERO
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga0d0f13dd26e92dba642f40387e517b6a">csl_dssVideoPort.h</a>
+</li>
+<li>CSL_DSS_VP_STALL_MODE_COMMAND
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gabd8aa22176d523bf6927f02922e6a965">csl_dssVideoPort.h</a>
+</li>
+<li>CSL_DSS_VP_STALL_MODE_VIDEO
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga1ae77b1f37ae1fafa15adc649b49f309">csl_dssVideoPort.h</a>
+</li>
+<li>CSL_DSS_VP_TDM_CYCLE_1PERPIXEL
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga5b4659b24eb81a27c27f0d409fd51460">csl_dssVideoPort.h</a>
+</li>
+<li>CSL_DSS_VP_TDM_CYCLE_2PERPIXEL
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga5c6498fbbc637492bee5fec53327d8d2">csl_dssVideoPort.h</a>
+</li>
+<li>CSL_DSS_VP_TDM_CYCLE_3PER2PIXEL
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga81528f8f4538347b9f0b9e5b1c47374a">csl_dssVideoPort.h</a>
+</li>
+<li>CSL_DSS_VP_TDM_CYCLE_3PERPIXEL
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga9f47ee0306de87ccadf8e16a57276cf0">csl_dssVideoPort.h</a>
+</li>
+<li>CSL_DSS_VP_TDM_PARALLEL_OUTPUT_12BIT
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gac83301ee887a6562c3ec89a921c4b74f">csl_dssVideoPort.h</a>
+</li>
+<li>CSL_DSS_VP_TDM_PARALLEL_OUTPUT_16BIT
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga8715d15d4ee5eebd9ea7b15adcf22394">csl_dssVideoPort.h</a>
+</li>
+<li>CSL_DSS_VP_TDM_PARALLEL_OUTPUT_8BIT
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gacd33fff8fc6d940d149b39ca4dd2f032">csl_dssVideoPort.h</a>
+</li>
+<li>CSL_DSS_VP_TDM_PARALLEL_OUTPUT_9BIT
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gabf1ad83065c73fc074ed85876c5e505e">csl_dssVideoPort.h</a>
+</li>
+<li>CSL_DSS_VP_TDM_UNUSED_BITS_LEVEL_HIGH
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gac426f8586cc7293b20148c1dfd1cec3a">csl_dssVideoPort.h</a>
+</li>
+<li>CSL_DSS_VP_TDM_UNUSED_BITS_LEVEL_LOW
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gab2d941b89a9b42c988e72d4500379661">csl_dssVideoPort.h</a>
+</li>
+<li>CSL_DSS_VP_TDM_UNUSED_BITS_LEVEL_UNCHANGED
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga58a52d1ec3bd962fe6ec5996d788cbe5">csl_dssVideoPort.h</a>
+</li>
+<li>CSL_dss_vpRegs
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gaaaf231996a0d81bd23a1460d729dad23">csl_dssVideoPort.h</a>
+</li>
+<li>CSL_DSS_WB_PIPE_INTR_ALL_MASK
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gaa87662a09ae286e277da4b5ee2243b71">csl_dssCommon.h</a>
+</li>
+<li>CSL_DSS_WB_PIPE_INTR_FRAMEDONE_MASK
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga21c87fbab481fb6ea24b202b12610a35">csl_dssCommon.h</a>
+</li>
+<li>CSL_DSS_WB_PIPE_INTR_OVERFLOW_MASK
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga9a426ebaaf7f08452b96825dff7dd6ea">csl_dssCommon.h</a>
+</li>
+<li>CSL_DSS_WB_PIPE_INTR_SECURITYVIOLATION_MASK
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1fcec556feabbf38743c1ff5ece580de">csl_dssCommon.h</a>
+</li>
+<li>CSL_DSS_WB_PIPE_INTR_UNCOMPLETE_MASK
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga49798f6dd7f9930bcde282c21197c739">csl_dssCommon.h</a>
+</li>
+<li>CSL_DSS_WB_PIPE_INTR_WBSYNC_MASK
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga7956cca4dac339f72e3bfd028cef8aea">csl_dssCommon.h</a>
+</li>
+<li>CSL_dssCbaCfgInit()
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gafa9009a2a94ae2222dfaaa166de1f33d">csl_dssCommon.h</a>
+</li>
+<li>CSL_dssClearDispcIntr()
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga2f59e10e9d38932af384543d274dc90c">csl_dssCommon.h</a>
+</li>
+<li>CSL_dssClearPipeIntr()
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1c2b89748e481bf4651cf4b87805177d">csl_dssCommon.h</a>
+</li>
+<li>CSL_dssClearVpIntr()
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga086ca7d14c9f2a75305035c512972c18">csl_dssCommon.h</a>
+</li>
+<li>CSL_dssConnectVpToDpi()
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1c215888b011a5cca5880679ea560f74">csl_dssCommon.h</a>
+</li>
+<li>CSL_dssCscCoeffInit()
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga09a24eab792b00629e4b510d36a326a8">csl_dssTop.h</a>
+</li>
+<li>CSL_dssEnableDispcIntr()
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga78ae8cafecdf61459530ae0ecaee1312">csl_dssCommon.h</a>
+</li>
+<li>CSL_dssEnablePipeIntr()
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1d1f5ed599418de87535e92ff113dbae">csl_dssCommon.h</a>
+</li>
+<li>CSL_dssEnableVpIntr()
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gabc7928512f14f647d32d899a9850b4ad">csl_dssCommon.h</a>
+</li>
+<li>CSL_dssGetDispcIntrStatus()
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga196052d031e6e46bc99f4631218d2da7">csl_dssCommon.h</a>
+</li>
+<li>CSL_dssGetPipeIntrStatus()
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gab25aea830bb6567a67be6018fbce58e2">csl_dssCommon.h</a>
+</li>
+<li>CSL_dssGetVpIntrStatus()
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga7202424e4a3404aaf894e294be0a1f7d">csl_dssCommon.h</a>
+</li>
+<li>CSL_dssGlobalMFlagCfgInit()
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga67eb3b87f230f3d3598ff1ea3c8ccbbe">csl_dssCommon.h</a>
+</li>
+<li>CSL_dssGlobalVpEnable()
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gad3490bc78c9441400a4a77c933006f6c">csl_dssCommon.h</a>
+</li>
+<li>CSL_dssGlobalVpGoBitEnable()
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga6c62a23a768c0ce357db64365ebdc0b0">csl_dssCommon.h</a>
+</li>
+<li>CSL_dssModuleReset()
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga567b2f823b70e843ceb9c4ca8c501cae">csl_dssCommon.h</a>
+</li>
+<li>CSL_dssOverlayCfgInit()
+: <a class="el" href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#ga5f9f1191f5d62fa0747616ae87e3cc65">csl_dssOverlay.h</a>
+</li>
+<li>CSL_dssOverlayColorBarEnable()
+: <a class="el" href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#gad36724322f426d4022c944b5fc53f3fd">csl_dssOverlay.h</a>
+</li>
+<li>CSL_dssOverlayGetEnabledPipeLayerNum()
+: <a class="el" href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#gae88aaba46e12dfb2f72c93691ea14c99">csl_dssOverlay.h</a>
+</li>
+<li>CSL_dssOverlayLayerCfgInit()
+: <a class="el" href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#gae7481e9db942be0537425939b6387a22">csl_dssOverlay.h</a>
+</li>
+<li>CSL_dssOverlayPipePosCfgInit()
+: <a class="el" href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#ga1c8500dcdd91d052cfc9c01d4bed6e30">csl_dssOverlay.h</a>
+</li>
+<li>CSL_dssOverlaySetConfig()
+: <a class="el" href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#ga03a77e67fa911acc5e905faafe06a7cc">csl_dssOverlay.h</a>
+</li>
+<li>CSL_dssOverlaySetLayerConfig()
+: <a class="el" href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#ga0854ef7eebe8ec3dabd739cda8a0a87b">csl_dssOverlay.h</a>
+</li>
+<li>CSL_dssOverlaySetPipePosConfig()
+: <a class="el" href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#ga04705e269d2be5aa01508e3f5dafdf7c">csl_dssOverlay.h</a>
+</li>
+<li>CSL_dssSafetyChkCfgInit()
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga0eba2c12170b846778eecb3eeb5a9a46">csl_dssTop.h</a>
+</li>
+<li>CSL_dssSetCbaConfig()
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1ce4591b123f52bf6e6cc00a485fcd38">csl_dssCommon.h</a>
+</li>
+<li>CSL_dssSetGlobalMflagConfig()
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga51649681f3f478ab1c44d97aa3ed8323">csl_dssCommon.h</a>
+</li>
+<li>CSL_dssVidPipeAlphaCfgInit()
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#ga8a3d5286ff2be3f2056f554f1d5c92d7">csl_dssVideoPipe.h</a>
+</li>
+<li>CSL_dssVidPipeCfgInit()
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gae2ea4d9e0e2d9662d1bda20ec77567dc">csl_dssVideoPipe.h</a>
+</li>
+<li>CSL_dssVidPipeCropEnable()
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gaf4dc4e4142893b328dd75906147dde8f">csl_dssVideoPipe.h</a>
+</li>
+<li>CSL_dssVidPipeDmaCfgInit()
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#ga53cc07dd9deeeec69be494c89fd12812">csl_dssVideoPipe.h</a>
+</li>
+<li>CSL_dssVidPipeEnable()
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gac037fe8b1ea6f506c6b0d00fd4a84491">csl_dssVideoPipe.h</a>
+</li>
+<li>CSL_dssVidPipeEnableTransparency()
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#ga0b9cbe7775795bca5b9a8904ec9fc4b1">csl_dssVideoPipe.h</a>
+</li>
+<li>CSL_dssVidPipeGetSafetySign()
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gaf51512cbab443cebde3013bc6bf212aa">csl_dssVideoPipe.h</a>
+</li>
+<li>CSL_dssVidPipeLumaCfgInit()
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gaeec644be0c0f1f62da19eca5c1e9b877">csl_dssVideoPipe.h</a>
+</li>
+<li>CSL_dssVidPipeMFlagCfgInit()
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#ga5d27f327524e3016a74de471e5eb38a1">csl_dssVideoPipe.h</a>
+</li>
+<li>CSL_dssVidPipeSetAlphaConfig()
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#ga3646182313235e92362cd843fdc6c2e6">csl_dssVideoPipe.h</a>
+</li>
+<li>CSL_dssVidPipeSetBuffAddr()
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#ga11ed49990e9b63ecbf167cff5f6a9755">csl_dssVideoPipe.h</a>
+</li>
+<li>CSL_dssVidPipeSetConfig()
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#ga6d983ffe721b5a1b602bfa53995f1c76">csl_dssVideoPipe.h</a>
+</li>
+<li>CSL_dssVidPipeSetCSCCoeff()
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gacebfcb0b4ae57fa7a1ce3c73f6b552e8">csl_dssVideoPipe.h</a>
+</li>
+<li>CSL_dssVidPipeSetDmaConfig()
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gaf3bd47c49aa8edd65bfd202779cdd0a2">csl_dssVideoPipe.h</a>
+</li>
+<li>CSL_dssVidPipeSetMflagConfig()
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#ga3095d9a0f35cd85fba7c2be6b14d798d">csl_dssVideoPipe.h</a>
+</li>
+<li>CSL_dssVidPipeSetSafetyChkConfig()
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gae5dc5282a40648fd2f69165e7a373265">csl_dssVideoPipe.h</a>
+</li>
+<li>CSL_dssVidPipeSetSafetyReferenceSign()
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#ga37238e9b68bd88742eb54cca7c3cd7a8">csl_dssVideoPipe.h</a>
+</li>
+<li>CSL_dssVidPipeSetSafetySignSeedVal()
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#ga70f77613b5b22a937388f5b072a7f74d">csl_dssVideoPipe.h</a>
+</li>
+<li>CSL_dssVidPipeVC1CfgInit()
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gaf11746b1003b15855996b817cfe3d38a">csl_dssVideoPipe.h</a>
+</li>
+<li>CSL_dssVpEnable()
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga9c61092eddfa87bcba87cc116fb8bd1d">csl_dssVideoPort.h</a>
+</li>
+<li>CSL_dssVpEnableTvGamma()
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga253c3416c174352edcda17c4ca271013">csl_dssVideoPort.h</a>
+</li>
+<li>CSL_dssVpGammaCfgInit()
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga709fdcc02c1f82d9a3b595ad67b9f086">csl_dssVideoPort.h</a>
+</li>
+<li>CSL_dssVpGetLcdLineNum()
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga447444c64439d7b1210a9b696dd8a673">csl_dssVideoPort.h</a>
+</li>
+<li>CSL_dssVpGetSafetySign()
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga7f7b411493687d0d758ff8b047a23712">csl_dssVideoPort.h</a>
+</li>
+<li>CSL_dssVpLcdAdvSignalCfgInit()
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga50f5efd31f31736019ee265e3078d4ef">csl_dssVideoPort.h</a>
+</li>
+<li>CSL_dssVpLcdBlankTimingCfgInit()
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gadd1a815002453481cce4f9dbf8da864a">csl_dssVideoPort.h</a>
+</li>
+<li>CSL_dssVpLcdOpTimingCfgInit()
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga2be9daed03e91c1706a4075be86a7054">csl_dssVideoPort.h</a>
+</li>
+<li>CSL_dssVpLcdSignalPolarityCfgInit()
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga158b9aed148e3a14e1bff1cb8613bc67">csl_dssVideoPort.h</a>
+</li>
+<li>CSL_dssVpLcdTdmCfgInit()
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gaf276b6af542ab92fa03bf0af6d1af1cb">csl_dssVideoPort.h</a>
+</li>
+<li>CSL_dssVpSetCSCCoeff()
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga7d36af9cdba47ad2622758fd632980ce">csl_dssVideoPort.h</a>
+</li>
+<li>CSL_dssVpSetGoBit()
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga0ba989884315a28b21a62a722574865d">csl_dssVideoPort.h</a>
+</li>
+<li>CSL_dssVpSetLcdAdvSignalConfig()
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga45dfca83a394f21328886b7ad7d89056">csl_dssVideoPort.h</a>
+</li>
+<li>CSL_dssVpSetLcdBlankTiming()
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga5f52bab6e5e9242d6f77faf995a4de6e">csl_dssVideoPort.h</a>
+</li>
+<li>CSL_dssVpSetLcdLineNum()
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga1a4f05443f8ba7bffea84d63b43788ab">csl_dssVideoPort.h</a>
+</li>
+<li>CSL_dssVpSetLcdOpTimingConfig()
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga0225f72557517955d94f1a6ce815ed14">csl_dssVideoPort.h</a>
+</li>
+<li>CSL_dssVpSetLcdSignalPolarityConfig()
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga75453549b6c9c05da750b55cdb2a8ad3">csl_dssVideoPort.h</a>
+</li>
+<li>CSL_dssVpSetLcdTdmConfig()
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga48c44cb30d94ee22ddd885998830d852">csl_dssVideoPort.h</a>
+</li>
+<li>CSL_dssVpSetSafetyChkConfig()
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gad2853dae9324aa61cbb332d14b308da6">csl_dssVideoPort.h</a>
+</li>
+<li>CSL_dssVpSetSafetyReferenceSign()
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga20bfb7e29029c7256d6766b9b05f5f23">csl_dssVideoPort.h</a>
+</li>
+<li>CSL_dssVpSetSafetySignSeedVal()
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga1bc9995f9958912a188ae2a98351aec5">csl_dssVideoPort.h</a>
+</li>
+<li>CSL_dssVpStallModeEnable()
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga08a68b5de9d2c6646b0654ccad3b9600">csl_dssVideoPort.h</a>
+</li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/globals_d.html b/packages/ti/drv/dss/docs/doxygen/html/globals_d.html
--- /dev/null
@@ -0,0 +1,239 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Globals</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li class="current"><a href="files.html"><span>Files</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow2" class="tabs2">
+ <ul class="tablist">
+ <li><a href="files.html"><span>File List</span></a></li>
+ <li class="current"><a href="globals.html"><span>Globals</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow3" class="tabs2">
+ <ul class="tablist">
+ <li class="current"><a href="globals.html"><span>All</span></a></li>
+ <li><a href="globals_func.html"><span>Functions</span></a></li>
+ <li><a href="globals_type.html"><span>Typedefs</span></a></li>
+ <li><a href="globals_enum.html"><span>Enumerations</span></a></li>
+ <li><a href="globals_eval.html"><span>Enumerator</span></a></li>
+ <li><a href="globals_defs.html"><span>Macros</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow4" class="tabs3">
+ <ul class="tablist">
+ <li><a href="globals.html#index_c"><span>c</span></a></li>
+ <li class="current"><a href="globals_d.html#index_d"><span>d</span></a></li>
+ <li><a href="globals_f.html#index_f"><span>f</span></a></li>
+ <li><a href="globals_i.html#index_i"><span>i</span></a></li>
+ </ul>
+ </div>
+</div><!-- top -->
+<div class="contents">
+<div class="textblock">Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation:</div>
+
+<h3><a class="anchor" id="index_d"></a>- d -</h3><ul>
+<li>DSS_BUFFER_ALIGNMENT
+: <a class="el" href="dss__disp_8h.html#a8e15b63c9ad0534336ab8b75c714c873">dss_disp.h</a>
+</li>
+<li>DSS_DCTRL_DRV_ID
+: <a class="el" href="group___d_s_s.html#ga0a02adbaa0f72fbfba37dbca39c7ab1d">dss.h</a>
+</li>
+<li>DSS_DCTRL_INST_0
+: <a class="el" href="dss__soc_8h.html#a9f12541fdf035815233db52d23727911">dss_soc.h</a>
+</li>
+<li>DSS_DCTRL_INST_MAX
+: <a class="el" href="dss__soc_8h.html#ac66ebc6e5c2f1a6c7f7dd129acb02ebd">dss_soc.h</a>
+</li>
+<li>DSS_DCTRL_IOCTL_BASE
+: <a class="el" href="group___d_s_s.html#ga9f2d978d01f7c34d373f956e5e5862d1">dss.h</a>
+</li>
+<li>DSS_DCTRL_MAX_EDGES
+: <a class="el" href="dss__soc_8h.html#a8dbb4dd2e4cfdb12f6d01c6ddcd923e0">dss_soc.h</a>
+</li>
+<li>DSS_DCTRL_MAX_NODES
+: <a class="el" href="dss__soc_8h.html#ad68744191253ed0e140808365e78d315">dss_soc.h</a>
+</li>
+<li>DSS_DCTRL_NODE_DPI1
+: <a class="el" href="dss__soc_8h.html#adcc5563c51855a3f4b8f1b53f8b26672">dss_soc.h</a>
+</li>
+<li>DSS_DCTRL_NODE_INVALID
+: <a class="el" href="dss__soc_8h.html#addcf6826238296d5d0cf3f46fb668380">dss_soc.h</a>
+</li>
+<li>DSS_DCTRL_NODE_OLDI
+: <a class="el" href="dss__soc_8h.html#ae42fb0de4238cbff83100dd6af2777df">dss_soc.h</a>
+</li>
+<li>DSS_DCTRL_NODE_OVERLAY1
+: <a class="el" href="dss__soc_8h.html#a6ac0743ded9082870f782c1deb9fee05">dss_soc.h</a>
+</li>
+<li>DSS_DCTRL_NODE_OVERLAY2
+: <a class="el" href="dss__soc_8h.html#a99e2d8a40fd3ea1bd492dd227021761e">dss_soc.h</a>
+</li>
+<li>DSS_DCTRL_NODE_VID1
+: <a class="el" href="dss__soc_8h.html#a1ca57513d77bd5f52e431690ec5b2b0f">dss_soc.h</a>
+</li>
+<li>DSS_DCTRL_NODE_VIDL1
+: <a class="el" href="dss__soc_8h.html#a38e52fb43b4d2792d67953bf92641c8e">dss_soc.h</a>
+</li>
+<li>DSS_DCTRL_NODE_VP1
+: <a class="el" href="dss__soc_8h.html#ab05e2fb7e5ae5efefc38b10735025bfd">dss_soc.h</a>
+</li>
+<li>DSS_DCTRL_NODE_VP2
+: <a class="el" href="dss__soc_8h.html#aba4b126180d74b834ff45412d2c98062">dss_soc.h</a>
+</li>
+<li>Dss_dctrlAdvVpParamsInit()
+: <a class="el" href="dss__dctrl_8h.html#a8ef2fd5c8a1f3760dc6bd0d3f41cf782">dss_dctrl.h</a>
+</li>
+<li>Dss_dctrlGlobalDssParamsInit()
+: <a class="el" href="dss__dctrl_8h.html#a9245be86f5b0aa58fd825ddac59b15de">dss_dctrl.h</a>
+</li>
+<li>Dss_dctrlLcdBlankTimingParamsInit()
+: <a class="el" href="dss__dctrl_8h.html#a1bee4f99058e9860ea9e0d8c46713d17">dss_dctrl.h</a>
+</li>
+<li>Dss_dctrlOldiParamsInit()
+: <a class="el" href="dss__soc_8h.html#a6b12a5aecc6d9248f665d838abbad924">dss_soc.h</a>
+</li>
+<li>Dss_dctrlOverlayLayerParamsInit()
+: <a class="el" href="dss__dctrl_8h.html#a5a26a0b5b1059cb2dc79b0f7ec932cb6">dss_dctrl.h</a>
+</li>
+<li>Dss_dctrlOverlayParamsInit()
+: <a class="el" href="dss__dctrl_8h.html#aeb3a05c6b9e915a29bfa94784b427f75">dss_dctrl.h</a>
+</li>
+<li>Dss_dctrlPathInfoInit()
+: <a class="el" href="dss__dctrl_8h.html#a123a4e064a3dd6ae0de052f3668bcc82">dss_dctrl.h</a>
+</li>
+<li>Dss_dctrlRegionSafetyChkCfgInit()
+: <a class="el" href="dss__dctrl_8h.html#a128f0b2a1da8e24d1e87993efc59a049">dss_dctrl.h</a>
+</li>
+<li>Dss_DctrlSyncLostCbFxn
+: <a class="el" href="dss__dctrl_8h.html#adc02df6de7a3d5940da55838ee464701">dss_dctrl.h</a>
+</li>
+<li>Dss_dctrlSyncLostCbParamsInit()
+: <a class="el" href="dss__dctrl_8h.html#aa6b7e9e12da3c697e83d78d8909bfdb9">dss_dctrl.h</a>
+</li>
+<li>Dss_dctrlVpErrorStatsInit()
+: <a class="el" href="dss__dctrl_8h.html#ab7d6c323f77101a8d6f6ec0b36fcd092">dss_dctrl.h</a>
+</li>
+<li>Dss_dctrlVpParamsInit()
+: <a class="el" href="dss__dctrl_8h.html#aff73397092899b064dc00d8a813286a4">dss_dctrl.h</a>
+</li>
+<li>Dss_dctrlVpSafetyChkParamsInit()
+: <a class="el" href="dss__dctrl_8h.html#a3434c36ddde97b9077bb2b055cf0a4b0">dss_dctrl.h</a>
+</li>
+<li>DSS_DEF_QUEUE_LEN_PER_INST
+: <a class="el" href="dss__cfg_8h.html#aba4c70e5063467ebeb1cd820b1e4f808">dss_cfg.h</a>
+</li>
+<li>Dss_deInit()
+: <a class="el" href="group___d_s_s.html#ga8da153ec94fd77b1238623030aedd76e">dss.h</a>
+</li>
+<li>DSS_DISP_DRV_ID
+: <a class="el" href="group___d_s_s.html#ga87b702c7777640534d677104a7697d35">dss.h</a>
+</li>
+<li>DSS_DISP_INST_MAX
+: <a class="el" href="dss__soc_8h.html#a240f22c4499be957a1f78dc24d13d587">dss_soc.h</a>
+</li>
+<li>DSS_DISP_INST_VID1
+: <a class="el" href="dss__soc_8h.html#a9b73eea7de83a9a39a1f200ec4096e4d">dss_soc.h</a>
+</li>
+<li>DSS_DISP_INST_VIDL1
+: <a class="el" href="dss__soc_8h.html#ad56ec47be5d8455998b861548c38ceec">dss_soc.h</a>
+</li>
+<li>DSS_DISP_IOCTL_BASE
+: <a class="el" href="group___d_s_s.html#gaf8566eb291e6ce8c67bf5158426d42b9">dss.h</a>
+</li>
+<li>Dss_DispBufPrgmCbFxn
+: <a class="el" href="dss__disp_8h.html#a3f3415894bf0e54f2d06f24ea22c602e">dss_disp.h</a>
+</li>
+<li>Dss_dispBufPrgmCbParamsInit()
+: <a class="el" href="dss__disp_8h.html#a5d7c65146501cb5e2e4bfeee924afe1c">dss_disp.h</a>
+</li>
+<li>Dss_dispCreateParamsInit()
+: <a class="el" href="dss__disp_8h.html#a0b1e08d5de369b9d9bfeaf4ab7841884">dss_disp.h</a>
+</li>
+<li>Dss_dispIsVidInst()
+: <a class="el" href="dss__soc_8h.html#ac5552efbddfba904ce91dbcd5d0bd455">dss_soc.h</a>
+</li>
+<li>Dss_dispIsVidLInst()
+: <a class="el" href="dss__soc_8h.html#afe01ba05886b4fec75e6bc8414cf2582">dss_soc.h</a>
+</li>
+<li>Dss_dispParamsInit()
+: <a class="el" href="dss__disp_8h.html#ade1761a8d085738b03f4a2d3a4af24b3">dss_disp.h</a>
+</li>
+<li>Dss_dispPipeMflagParamsInit()
+: <a class="el" href="dss__disp_8h.html#a870942fd13c4ea685c1e03b4fe51da4c">dss_disp.h</a>
+</li>
+<li>Dss_DispPipePrgmCbFxn
+: <a class="el" href="dss__disp_8h.html#a4ccdd634499058281998bcc9a7af0555">dss_disp.h</a>
+</li>
+<li>Dss_dispPipePrgmCbParamsInit()
+: <a class="el" href="dss__disp_8h.html#a6c10a27c661e431f53014ed39b8335ec">dss_disp.h</a>
+</li>
+<li>Dss_dispPipeSafetyChkParamsInit()
+: <a class="el" href="dss__disp_8h.html#aa658322ec9e4dff9106f95f92439aa16">dss_disp.h</a>
+</li>
+<li>Dss_dispRtParamsInit()
+: <a class="el" href="dss__disp_8h.html#ae1a443826f5f5c55bb40417fcb689bcd">dss_disp.h</a>
+</li>
+<li>Dss_DispUnderFlowCbFxn
+: <a class="el" href="dss__disp_8h.html#a14c7b8d97214b5c092eb8702e24522a1">dss_disp.h</a>
+</li>
+<li>Dss_dispUnderFlowCbParamsInit()
+: <a class="el" href="dss__disp_8h.html#a076a2c0095da75002988e147c8f9991c">dss_disp.h</a>
+</li>
+<li>DSS_EVT_MGR_INST_ID_FUNC
+: <a class="el" href="dss__soc_8h.html#a2d58a192f10fab6608c8f1cde2489aa5">dss_soc.h</a>
+</li>
+<li>DSS_EVT_MGR_INST_ID_INVALID
+: <a class="el" href="dss__soc_8h.html#aa6df7d5f82c9928bd28c3031bef4adbc">dss_soc.h</a>
+</li>
+<li>DSS_EVT_MGR_INST_ID_MAX
+: <a class="el" href="dss__soc_8h.html#a655e39bd46b2a70609bd7d6c878f394f">dss_soc.h</a>
+</li>
+<li>Dss_frameRtParamsInit()
+: <a class="el" href="dss__disp_8h.html#a20946243c0b2d8b3c5b317098abfba69">dss_disp.h</a>
+</li>
+<li>DSS_FUNC_IRQ_DEFAULT_NUM
+: <a class="el" href="dss__soc_8h.html#aa7ac2fb77b879354f19126b346099294">dss_soc.h</a>
+</li>
+<li>Dss_init()
+: <a class="el" href="group___d_s_s.html#ga9a7600eb912fe78c81a4e5fd88b495f6">dss.h</a>
+</li>
+<li>Dss_initParamsInit()
+: <a class="el" href="group___d_s_s.html#ga148ec5eeed6ef017fddce29adee32e90">dss.h</a>
+</li>
+<li>Dss_irqParamsInit()
+: <a class="el" href="dss__soc_8h.html#ae9111504fb718b4ac86e9a13ebf0b1d8">dss_soc.h</a>
+</li>
+<li>Dss_rmInfoInit()
+: <a class="el" href="dss__soc_8h.html#a24089c231dd46a8856c109008a2ac5b4">dss_soc.h</a>
+</li>
+<li>Dss_scRtParamsInit()
+: <a class="el" href="dss__disp_8h.html#a9f3129c4857d08aec6387867cc2e778c">dss_disp.h</a>
+</li>
+<li>Dss_socParamsInit()
+: <a class="el" href="dss__soc_8h.html#ab0090cdbb416c7e5ebe089d50914b70a">dss_soc.h</a>
+</li>
+<li>DssTrace
+: <a class="el" href="dss__cfg_8h.html#a76ace3e354893fc499603be1fbe3d1b2">dss_cfg.h</a>
+</li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/globals_defs.html b/packages/ti/drv/dss/docs/doxygen/html/globals_defs.html
--- /dev/null
@@ -0,0 +1,506 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Globals</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li class="current"><a href="files.html"><span>Files</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow2" class="tabs2">
+ <ul class="tablist">
+ <li><a href="files.html"><span>File List</span></a></li>
+ <li class="current"><a href="globals.html"><span>Globals</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow3" class="tabs2">
+ <ul class="tablist">
+ <li><a href="globals.html"><span>All</span></a></li>
+ <li><a href="globals_func.html"><span>Functions</span></a></li>
+ <li><a href="globals_type.html"><span>Typedefs</span></a></li>
+ <li><a href="globals_enum.html"><span>Enumerations</span></a></li>
+ <li><a href="globals_eval.html"><span>Enumerator</span></a></li>
+ <li class="current"><a href="globals_defs.html"><span>Macros</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow4" class="tabs3">
+ <ul class="tablist">
+ <li class="current"><a href="globals_defs.html#index_c"><span>c</span></a></li>
+ <li><a href="globals_defs_d.html#index_d"><span>d</span></a></li>
+ <li><a href="globals_defs_f.html#index_f"><span>f</span></a></li>
+ <li><a href="globals_defs_i.html#index_i"><span>i</span></a></li>
+ </ul>
+ </div>
+</div><!-- top -->
+<div class="contents">
+ 
+
+<h3><a class="anchor" id="index_c"></a>- c -</h3><ul>
+<li>CSL_DSS_COMM_REG_ID_0
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gaba6b3367cbe7db1f57b4693234fbcd86">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_COMM_REG_ID_0_MASK
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga8e4fccb97063f3a1a8ae7a0a45f7de7b">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_COMM_REG_ID_1
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga961c35c051c33b4e92691db8a5ee749d">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_COMM_REG_ID_1_MASK
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga4b279b40e6fa88217af7df5242fdd007">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_COMM_REG_ID_2
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gafaece2043fd351a5f7f8b5b1628921c7">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_COMM_REG_ID_2_MASK
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gafdceb9e1230dd80ea4e7da1689f9ffba">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_COMM_REG_ID_3
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga22dc72847784f75cad78a4c2a3b3f217">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_COMM_REG_ID_3_MASK
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga6ae3cbe4e7f4e35054a0f8f1d739ed83">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_COMM_REG_ID_MAX
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gab1b9457684eda680598c1bc8a574e20c">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_CSC_RANGE_FULL
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga2b1f7a9fccfe834266cc61dbab22a7f2">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_CSC_RANGE_LIMITED
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga3041c8743595f7ce5d8ebb59cf32bcc4">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_DISPC_INTR_VID1_MASK
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga06e5097b8fb8b1581b289d1e4c5f8b1d">csl_dssCommon.h</a>
+</li>
+<li>CSL_DSS_DISPC_INTR_VID2_MASK
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga3e9bb13013658677983d41d243db6530">csl_dssCommon.h</a>
+</li>
+<li>CSL_DSS_DISPC_INTR_VIDL1_MASK
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gabee1d0a280ee911c3f3863343167c034">csl_dssCommon.h</a>
+</li>
+<li>CSL_DSS_DISPC_INTR_VIDL2_MASK
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gaca4d1f25e688c3c257df26fbed1bf0b0">csl_dssCommon.h</a>
+</li>
+<li>CSL_DSS_DISPC_INTR_VP1_MASK
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga9c7a9966f4f00cf84f8522ae35009f6f">csl_dssCommon.h</a>
+</li>
+<li>CSL_DSS_DISPC_INTR_VP2_MASK
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga7c9437915888ed76ced5942c24acf8e7">csl_dssCommon.h</a>
+</li>
+<li>CSL_DSS_DISPC_INTR_VP3_MASK
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga72e1189718d84be73378a1c7243668d0">csl_dssCommon.h</a>
+</li>
+<li>CSL_DSS_DISPC_INTR_VP4_MASK
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga4663d2526dbf5150b3173715ee5bf049">csl_dssCommon.h</a>
+</li>
+<li>CSL_DSS_DISPC_INTR_WB_MASK
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1c3a6a248c34ffb2b8183155f96107c9">csl_dssCommon.h</a>
+</li>
+<li>CSL_DSS_DPI_ID_0
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga9679d96bb4a54cf7e8ce0a22bf034ce3">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_DPI_ID_1
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga2ef99175d7ba50686f9d3b55484099d3">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_DPI_ID_2
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga2fcf2f843406ec0ff1ee6ec29156576e">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_DPI_ID_3
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga3e2b38794f954faea2bf1769d25c2bd3">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_DPI_ID_4
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga92854e551ae60a5d40c9c5c1c8326092">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_DPI_ID_5
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gad22d8422668bd5e965c0611d4c80ca36">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_DPI_ID_MAX
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga53c1ac5fbf207e8f973902051404e51e">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_MFLAG_CTRL_DISABLED
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga8a1fdde2ee44a5d4f758add66d1e531a">csl_dssCommon.h</a>
+</li>
+<li>CSL_DSS_MFLAG_CTRL_DYNAMIC
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gafd85bc61dad64ede428e21526edd470a">csl_dssCommon.h</a>
+</li>
+<li>CSL_DSS_MFLAG_CTRL_FORCE_ENABLE
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gae33f049f22cfce779d267a22ba79d1e3">csl_dssCommon.h</a>
+</li>
+<li>CSL_DSS_MFLAG_START_FORCED
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga25a7a13a5ed7fa79de52587991cd6e8c">csl_dssCommon.h</a>
+</li>
+<li>CSL_DSS_MFLAG_START_NORMAL
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga8463a9a268552ec6233a928947813a7d">csl_dssCommon.h</a>
+</li>
+<li>CSL_DSS_MODULE_INVALID
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gaa7973f4d3301c7360cdbcc6f60c6e8fb">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_NUM_LUT_ENTRIES
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gac8a30c5680379b12128e75859e9f2312">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_OVERLAY_ID_1
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga5acb54b8623189d18b4211a24a0ddb8c">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_OVERLAY_ID_1_MASK
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gab66410f4f933b9c077e3f9d294436073">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_OVERLAY_ID_2
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga37edd061f4545fb5bcaf98fb0e29f49c">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_OVERLAY_ID_2_MASK
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gac474fcd4a03b4204c8cf584ba7b105e2">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_OVERLAY_ID_3
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga4cc372289cf4841713a3fff407e519ec">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_OVERLAY_ID_3_MASK
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gaa3f86a021fef86c1bdf2d94e122143c2">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_OVERLAY_ID_4
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gae8da1ca2c825364e430e6bb94a11c8de">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_OVERLAY_ID_4_MASK
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga80bbc7f730eed3ab5d593b450858375e">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_OVERLAY_ID_MAX
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga41df77f605b2d5c6e107fd4b0df61220">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_OVERLAY_LAYER_INVALID
+: <a class="el" href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#gae0d0be4608934fba2afa072b6716220a">csl_dssOverlay.h</a>
+</li>
+<li>CSL_DSS_OVERLAY_LAYER_MAX
+: <a class="el" href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#ga2a682ed470d58605922ee2106033a5f8">csl_dssOverlay.h</a>
+</li>
+<li>CSL_DSS_OVERLAY_LAYER_NUM_0
+: <a class="el" href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#ga2488889aa0b927be4a00ec57b8b75f70">csl_dssOverlay.h</a>
+</li>
+<li>CSL_DSS_OVERLAY_LAYER_NUM_1
+: <a class="el" href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#gabe9d38d2a4ef636da3b3a261cbb94f71">csl_dssOverlay.h</a>
+</li>
+<li>CSL_DSS_OVERLAY_LAYER_NUM_2
+: <a class="el" href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#ga97d71d9f152602cd81c45e7cdfa3a92d">csl_dssOverlay.h</a>
+</li>
+<li>CSL_DSS_OVERLAY_LAYER_NUM_3
+: <a class="el" href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#ga4f0066fbe34c973483392a7128eb598a">csl_dssOverlay.h</a>
+</li>
+<li>CSL_DSS_OVERLAY_TRANS_COLOR_DEST
+: <a class="el" href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#ga340c7a53b58c9fed267c3164ec0a03c9">csl_dssOverlay.h</a>
+</li>
+<li>CSL_DSS_OVERLAY_TRANS_COLOR_SRC
+: <a class="el" href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#ga164f53537368dff35827675dfda8cf12">csl_dssOverlay.h</a>
+</li>
+<li>CSL_DSS_SAFETY_CHK_DATA_INTEGRITY
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gabc2f69f2dfaab74b675a923fb14c3489">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_SAFETY_CHK_FRAME_FREEZE_DETECT
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga87bc16f17eb07c0e42f1e00f9ed1ef3e">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_SAFETY_CHK_FRAME_SKIP_EVEN
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga663277190152e9b070a32830bdfab30d">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_SAFETY_CHK_FRAME_SKIP_NO
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga3b3b3a0ec326781390a727d437cd3e59">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_SAFETY_CHK_FRAME_SKIP_ODD
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gafca0e84bf97ed23528e1bc15af0a4e98">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_SAFETY_REGION_0
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gaa3a861b982382bd7387783bf1019576c">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_SAFETY_REGION_1
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gaa104154d768c72acac19f2545460038c">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_SAFETY_REGION_2
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga3ca88d86a0c19685b48ce935c86821bd">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_SAFETY_REGION_3
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga7fecc5cd051151b901deb0dbd6c36201">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_SAFETY_REGION_4
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gabfb09986c4139d4093308e6f708fd582">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_SAFETY_REGION_5
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga83b9053e2bc53689cf537ae19102ff9f">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_SAFETY_REGION_6
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga0e75b3f63a3ad9488a287d1cfe5ff9a5">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_SAFETY_REGION_7
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga20d089acf2d69bd7f86a05eea0093bfa">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_SAFETY_REGION_MAX
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga514efc84b40d7147969434b2d5cff2fe">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_VID_PIPE_ID_MAX
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gafbbd94228f58df3124b2bc9780379cea">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_VID_PIPE_ID_VID1
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gab861a5295a9cd21b01897e1026aa2b79">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_VID_PIPE_ID_VID1_MASK
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gaada71522489dcbd519415f3f81e490d0">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_VID_PIPE_ID_VID2
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gadd35014f4f1e166a6b95a0e80970f9e8">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_VID_PIPE_ID_VID2_MASK
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga1d978b06983e4f19a666abd322a70293">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_VID_PIPE_ID_VIDL1
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga73aee3bb97f91dafe4f9adfd0a0d3bac">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_VID_PIPE_ID_VIDL1_MASK
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga86337ef6c0f0e8ac50c07638c91104c6">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_VID_PIPE_ID_VIDL2
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga9692470b1ffe05c0bf39af6cce81b3dd">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_VID_PIPE_ID_VIDL2_MASK
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga69abb0b78149e8c8880f5ce9f1d7d508">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_VID_PIPE_INTR_ALL_MASK
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gab333a63a9c79c3af6e7b439ad23f6ee7">csl_dssCommon.h</a>
+</li>
+<li>CSL_DSS_VID_PIPE_INTR_BUFUNDERFLOW_MASK
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gac87f5c5a2d6fea0b3be605ef429fa7fa">csl_dssCommon.h</a>
+</li>
+<li>CSL_DSS_VID_PIPE_INTR_FBDC_CORRUPTTILE_MASK
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gaeb0df43d6aa106d64cbae9879d850ab2">csl_dssCommon.h</a>
+</li>
+<li>CSL_DSS_VID_PIPE_INTR_FBDC_ILLEGALTILE_MASK
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gac01c7ef875638b7ac0110c9306e97e03">csl_dssCommon.h</a>
+</li>
+<li>CSL_DSS_VID_PIPE_INTR_SAFETYVIOLATION_MASK
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga5a394bb4a7b00f928e9287c7838a1a7d">csl_dssCommon.h</a>
+</li>
+<li>CSL_DSS_VID_PIPE_INTR_WINDOWEND_MASK
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gaf2e001a112ba432cac5fec625eede116">csl_dssCommon.h</a>
+</li>
+<li>CSL_DSS_VID_PIPE_PRELOAD_CONTROL_HW
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gaddf7744bff3546d7cf3dfcd5f50578e0">csl_dssVideoPipe.h</a>
+</li>
+<li>CSL_DSS_VID_PIPE_PRELOAD_CONTROL_SW
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#ga9920a3ec2d8c5a8707be21d19df2cdca">csl_dssVideoPipe.h</a>
+</li>
+<li>CSL_DSS_VID_PIPE_PRIORITY_HIGH
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gab90746bec79505e7a733d0f2bd72f5c4">csl_dssVideoPipe.h</a>
+</li>
+<li>CSL_DSS_VID_PIPE_PRIORITY_NORMAL
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#ga8d4e4c078fa0fed3f7d3d3739d5ff7cd">csl_dssVideoPipe.h</a>
+</li>
+<li>CSL_DSS_VID_PIPE_REFRESH_CONTROL_HW
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gaa791b8ccb4cccc15ca17524094cfb280">csl_dssVideoPipe.h</a>
+</li>
+<li>CSL_DSS_VID_PIPE_REFRESH_CONTROL_SW
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gacb4282f5d79fd4252da0e6dfc0a6e124">csl_dssVideoPipe.h</a>
+</li>
+<li>CSL_DSS_VID_PIPE_SC_DISABLED
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gabeae764db02ef759820ebc878da5abc7">csl_dssVideoPipe.h</a>
+</li>
+<li>CSL_DSS_VID_PIPE_SC_ENABLED_H
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gae5bb5538c01dcbf3f8b9d1fc52dc385a">csl_dssVideoPipe.h</a>
+</li>
+<li>CSL_DSS_VID_PIPE_SC_ENABLED_HV
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#ga00799c61e0313dc87418c766f836a958">csl_dssVideoPipe.h</a>
+</li>
+<li>CSL_DSS_VID_PIPE_SC_ENABLED_V
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#ga0add9ab4761fdd4bd2a09c4e140a35c0">csl_dssVideoPipe.h</a>
+</li>
+<li>CSL_DSS_VID_PIPE_TYPE_VID
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gae0a57704e2a39702c1d1ac1a861ead86">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_VID_PIPE_TYPE_VIDL
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gab3801fb3aa15ef1b184da3fc2f9ea9ad">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_VID_PIPE_YUV_ALIGN_LSB
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#ga39ea4aaf120f874835b851ed1a0d84af">csl_dssVideoPipe.h</a>
+</li>
+<li>CSL_DSS_VID_PIPE_YUV_ALIGN_MSB
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gaed342608ce368c3c538c10e808a60eef">csl_dssVideoPipe.h</a>
+</li>
+<li>CSL_DSS_VP_CSC_POS_AFTER_GAMMA
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga9d8db056eb5e4a6dc1972200c70acf09">csl_dssVideoPort.h</a>
+</li>
+<li>CSL_DSS_VP_CSC_POS_BEFORE_GAMMA
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga7adc25e7daeddfff398a028a6f7af0b8">csl_dssVideoPort.h</a>
+</li>
+<li>CSL_DSS_VP_FID_FIRST_EVEN
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gab6a1a6b67d60bff5578cc42bc2bc0114">csl_dssVideoPort.h</a>
+</li>
+<li>CSL_DSS_VP_FID_FIRST_ODD
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga62dd57b2769fa39f4459379b8f432465">csl_dssVideoPort.h</a>
+</li>
+<li>CSL_DSS_VP_HVCLK_CONTROL_OFF
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga2b87767e34b62775d52ef6022789bdd0">csl_dssVideoPort.h</a>
+</li>
+<li>CSL_DSS_VP_HVCLK_CONTROL_ON
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gac3a10008ac4fbc32ef1869c751602925">csl_dssVideoPort.h</a>
+</li>
+<li>CSL_DSS_VP_HVSYNC_ALIGNED
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga744ce9e2dba4875d10456de204cdf564">csl_dssVideoPort.h</a>
+</li>
+<li>CSL_DSS_VP_HVSYNC_NOT_ALIGNED
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gab6a57958037687c92ae5d39ef7e4633f">csl_dssVideoPort.h</a>
+</li>
+<li>CSL_DSS_VP_ID_1
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gafbe058ac640cf42ad08afa3b32fb29d1">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_VP_ID_1_MASK
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga2b8bb0130844b328ae5711f9f4b5487b">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_VP_ID_2
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga34118161f4c12f89689b79f5ce09696c">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_VP_ID_2_MASK
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga40b42315f64e4f7290af3f3f2c1f6fb4">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_VP_ID_3
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga657e4b1ceb6955c961961d5c0af3e9b7">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_VP_ID_3_MASK
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gac5818d5d83b12514d8a01d62d6743306">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_VP_ID_4
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga961d6492d4afd198139770cb4b93a5ab">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_VP_ID_4_MASK
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gacabf7b4969d7515d967d243e2e67dd2a">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_VP_ID_MAX
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga0a203752c6295d20389b36d6c2e0de0c">csl_dssTop.h</a>
+</li>
+<li>CSL_DSS_VP_INTR_ACBIASCOUNT_MASK
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gaa57aa7b8fc4736ff9598a0b8c5b308c6">csl_dssCommon.h</a>
+</li>
+<li>CSL_DSS_VP_INTR_ALL_MASK
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga062132a334862eff31df843867a5a9c1">csl_dssCommon.h</a>
+</li>
+<li>CSL_DSS_VP_INTR_FRAMEDONE_MASK
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga17a731c79f013dff8a68313609310a14">csl_dssCommon.h</a>
+</li>
+<li>CSL_DSS_VP_INTR_GOBITCLEAR_MASK
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga4b7fe7d3fbf537386925b2118337517d">csl_dssCommon.h</a>
+</li>
+<li>CSL_DSS_VP_INTR_ODDVSYNC_MASK
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga323ac381f7d2dacaa7d710894740d796">csl_dssCommon.h</a>
+</li>
+<li>CSL_DSS_VP_INTR_PROGLINENUM_MASK
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gab542da635c1710ea24c5a29e3e6f150c">csl_dssCommon.h</a>
+</li>
+<li>CSL_DSS_VP_INTR_SAFETYVIOLATION_REGION1_MASK
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gaf396f3733114c9eb5478a5a7852fb09e">csl_dssCommon.h</a>
+</li>
+<li>CSL_DSS_VP_INTR_SAFETYVIOLATION_REGION2_MASK
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gab1798bd63882f1a7da07264aa665a06e">csl_dssCommon.h</a>
+</li>
+<li>CSL_DSS_VP_INTR_SAFETYVIOLATION_REGION3_MASK
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gaf436eb889d4490f9e0fb4b79ebeea6cb">csl_dssCommon.h</a>
+</li>
+<li>CSL_DSS_VP_INTR_SAFETYVIOLATION_REGION4_MASK
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga84dc6d8ce16d3bc5fd19fb1008f53998">csl_dssCommon.h</a>
+</li>
+<li>CSL_DSS_VP_INTR_SAFETYVIOLATION_REGION5_MASK
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga07b59cbeb37e6d5337a4117ecf688973">csl_dssCommon.h</a>
+</li>
+<li>CSL_DSS_VP_INTR_SAFETYVIOLATION_REGION6_MASK
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gab854dd38750979bf152c0bb7d39f10f9">csl_dssCommon.h</a>
+</li>
+<li>CSL_DSS_VP_INTR_SAFETYVIOLATION_REGION7_MASK
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gafd2c9bb5bce5224951f713e6a67951cb">csl_dssCommon.h</a>
+</li>
+<li>CSL_DSS_VP_INTR_SAFETYVIOLATION_REGION8_MASK
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gafee920aa4503ff1c8ec7d91a028802ba">csl_dssCommon.h</a>
+</li>
+<li>CSL_DSS_VP_INTR_SECURITYVIOLATION_MASK
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga2287bdc0f1a6bb8d7c25590cc580d26a">csl_dssCommon.h</a>
+</li>
+<li>CSL_DSS_VP_INTR_SYNCLOST_MASK
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga92903c6e1b355ed60ca8a15c1673c3b9">csl_dssCommon.h</a>
+</li>
+<li>CSL_DSS_VP_INTR_VSYNC_MASK
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1ddaba61f8fa43456fb3d8549f69815f">csl_dssCommon.h</a>
+</li>
+<li>CSL_DSS_VP_LPP_DELTA_MINUSONE
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga1a9e8a871ac9b403dfe0f0d208b3c29f">csl_dssVideoPort.h</a>
+</li>
+<li>CSL_DSS_VP_LPP_DELTA_PLUSONE
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga219596f8e8c8b043dde6c1f05c36f570">csl_dssVideoPort.h</a>
+</li>
+<li>CSL_DSS_VP_LPP_DELTA_ZERO
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga0d0f13dd26e92dba642f40387e517b6a">csl_dssVideoPort.h</a>
+</li>
+<li>CSL_DSS_VP_STALL_MODE_COMMAND
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gabd8aa22176d523bf6927f02922e6a965">csl_dssVideoPort.h</a>
+</li>
+<li>CSL_DSS_VP_STALL_MODE_VIDEO
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga1ae77b1f37ae1fafa15adc649b49f309">csl_dssVideoPort.h</a>
+</li>
+<li>CSL_DSS_VP_TDM_CYCLE_1PERPIXEL
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga5b4659b24eb81a27c27f0d409fd51460">csl_dssVideoPort.h</a>
+</li>
+<li>CSL_DSS_VP_TDM_CYCLE_2PERPIXEL
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga5c6498fbbc637492bee5fec53327d8d2">csl_dssVideoPort.h</a>
+</li>
+<li>CSL_DSS_VP_TDM_CYCLE_3PER2PIXEL
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga81528f8f4538347b9f0b9e5b1c47374a">csl_dssVideoPort.h</a>
+</li>
+<li>CSL_DSS_VP_TDM_CYCLE_3PERPIXEL
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga9f47ee0306de87ccadf8e16a57276cf0">csl_dssVideoPort.h</a>
+</li>
+<li>CSL_DSS_VP_TDM_PARALLEL_OUTPUT_12BIT
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gac83301ee887a6562c3ec89a921c4b74f">csl_dssVideoPort.h</a>
+</li>
+<li>CSL_DSS_VP_TDM_PARALLEL_OUTPUT_16BIT
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga8715d15d4ee5eebd9ea7b15adcf22394">csl_dssVideoPort.h</a>
+</li>
+<li>CSL_DSS_VP_TDM_PARALLEL_OUTPUT_8BIT
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gacd33fff8fc6d940d149b39ca4dd2f032">csl_dssVideoPort.h</a>
+</li>
+<li>CSL_DSS_VP_TDM_PARALLEL_OUTPUT_9BIT
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gabf1ad83065c73fc074ed85876c5e505e">csl_dssVideoPort.h</a>
+</li>
+<li>CSL_DSS_VP_TDM_UNUSED_BITS_LEVEL_HIGH
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gac426f8586cc7293b20148c1dfd1cec3a">csl_dssVideoPort.h</a>
+</li>
+<li>CSL_DSS_VP_TDM_UNUSED_BITS_LEVEL_LOW
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gab2d941b89a9b42c988e72d4500379661">csl_dssVideoPort.h</a>
+</li>
+<li>CSL_DSS_VP_TDM_UNUSED_BITS_LEVEL_UNCHANGED
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga58a52d1ec3bd962fe6ec5996d788cbe5">csl_dssVideoPort.h</a>
+</li>
+<li>CSL_DSS_WB_PIPE_INTR_ALL_MASK
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gaa87662a09ae286e277da4b5ee2243b71">csl_dssCommon.h</a>
+</li>
+<li>CSL_DSS_WB_PIPE_INTR_FRAMEDONE_MASK
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga21c87fbab481fb6ea24b202b12610a35">csl_dssCommon.h</a>
+</li>
+<li>CSL_DSS_WB_PIPE_INTR_OVERFLOW_MASK
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga9a426ebaaf7f08452b96825dff7dd6ea">csl_dssCommon.h</a>
+</li>
+<li>CSL_DSS_WB_PIPE_INTR_SECURITYVIOLATION_MASK
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1fcec556feabbf38743c1ff5ece580de">csl_dssCommon.h</a>
+</li>
+<li>CSL_DSS_WB_PIPE_INTR_UNCOMPLETE_MASK
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga49798f6dd7f9930bcde282c21197c739">csl_dssCommon.h</a>
+</li>
+<li>CSL_DSS_WB_PIPE_INTR_WBSYNC_MASK
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga7956cca4dac339f72e3bfd028cef8aea">csl_dssCommon.h</a>
+</li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/globals_defs_d.html b/packages/ti/drv/dss/docs/doxygen/html/globals_defs_d.html
--- /dev/null
@@ -0,0 +1,137 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Globals</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li class="current"><a href="files.html"><span>Files</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow2" class="tabs2">
+ <ul class="tablist">
+ <li><a href="files.html"><span>File List</span></a></li>
+ <li class="current"><a href="globals.html"><span>Globals</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow3" class="tabs2">
+ <ul class="tablist">
+ <li><a href="globals.html"><span>All</span></a></li>
+ <li><a href="globals_func.html"><span>Functions</span></a></li>
+ <li><a href="globals_type.html"><span>Typedefs</span></a></li>
+ <li><a href="globals_enum.html"><span>Enumerations</span></a></li>
+ <li><a href="globals_eval.html"><span>Enumerator</span></a></li>
+ <li class="current"><a href="globals_defs.html"><span>Macros</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow4" class="tabs3">
+ <ul class="tablist">
+ <li><a href="globals_defs.html#index_c"><span>c</span></a></li>
+ <li class="current"><a href="globals_defs_d.html#index_d"><span>d</span></a></li>
+ <li><a href="globals_defs_f.html#index_f"><span>f</span></a></li>
+ <li><a href="globals_defs_i.html#index_i"><span>i</span></a></li>
+ </ul>
+ </div>
+</div><!-- top -->
+<div class="contents">
+ 
+
+<h3><a class="anchor" id="index_d"></a>- d -</h3><ul>
+<li>DSS_BUFFER_ALIGNMENT
+: <a class="el" href="dss__disp_8h.html#a8e15b63c9ad0534336ab8b75c714c873">dss_disp.h</a>
+</li>
+<li>DSS_DCTRL_DRV_ID
+: <a class="el" href="group___d_s_s.html#ga0a02adbaa0f72fbfba37dbca39c7ab1d">dss.h</a>
+</li>
+<li>DSS_DCTRL_INST_0
+: <a class="el" href="dss__soc_8h.html#a9f12541fdf035815233db52d23727911">dss_soc.h</a>
+</li>
+<li>DSS_DCTRL_INST_MAX
+: <a class="el" href="dss__soc_8h.html#ac66ebc6e5c2f1a6c7f7dd129acb02ebd">dss_soc.h</a>
+</li>
+<li>DSS_DCTRL_IOCTL_BASE
+: <a class="el" href="group___d_s_s.html#ga9f2d978d01f7c34d373f956e5e5862d1">dss.h</a>
+</li>
+<li>DSS_DCTRL_MAX_EDGES
+: <a class="el" href="dss__soc_8h.html#a8dbb4dd2e4cfdb12f6d01c6ddcd923e0">dss_soc.h</a>
+</li>
+<li>DSS_DCTRL_MAX_NODES
+: <a class="el" href="dss__soc_8h.html#ad68744191253ed0e140808365e78d315">dss_soc.h</a>
+</li>
+<li>DSS_DCTRL_NODE_DPI1
+: <a class="el" href="dss__soc_8h.html#adcc5563c51855a3f4b8f1b53f8b26672">dss_soc.h</a>
+</li>
+<li>DSS_DCTRL_NODE_INVALID
+: <a class="el" href="dss__soc_8h.html#addcf6826238296d5d0cf3f46fb668380">dss_soc.h</a>
+</li>
+<li>DSS_DCTRL_NODE_OLDI
+: <a class="el" href="dss__soc_8h.html#ae42fb0de4238cbff83100dd6af2777df">dss_soc.h</a>
+</li>
+<li>DSS_DCTRL_NODE_OVERLAY1
+: <a class="el" href="dss__soc_8h.html#a6ac0743ded9082870f782c1deb9fee05">dss_soc.h</a>
+</li>
+<li>DSS_DCTRL_NODE_OVERLAY2
+: <a class="el" href="dss__soc_8h.html#a99e2d8a40fd3ea1bd492dd227021761e">dss_soc.h</a>
+</li>
+<li>DSS_DCTRL_NODE_VID1
+: <a class="el" href="dss__soc_8h.html#a1ca57513d77bd5f52e431690ec5b2b0f">dss_soc.h</a>
+</li>
+<li>DSS_DCTRL_NODE_VIDL1
+: <a class="el" href="dss__soc_8h.html#a38e52fb43b4d2792d67953bf92641c8e">dss_soc.h</a>
+</li>
+<li>DSS_DCTRL_NODE_VP1
+: <a class="el" href="dss__soc_8h.html#ab05e2fb7e5ae5efefc38b10735025bfd">dss_soc.h</a>
+</li>
+<li>DSS_DCTRL_NODE_VP2
+: <a class="el" href="dss__soc_8h.html#aba4b126180d74b834ff45412d2c98062">dss_soc.h</a>
+</li>
+<li>DSS_DEF_QUEUE_LEN_PER_INST
+: <a class="el" href="dss__cfg_8h.html#aba4c70e5063467ebeb1cd820b1e4f808">dss_cfg.h</a>
+</li>
+<li>DSS_DISP_DRV_ID
+: <a class="el" href="group___d_s_s.html#ga87b702c7777640534d677104a7697d35">dss.h</a>
+</li>
+<li>DSS_DISP_INST_MAX
+: <a class="el" href="dss__soc_8h.html#a240f22c4499be957a1f78dc24d13d587">dss_soc.h</a>
+</li>
+<li>DSS_DISP_INST_VID1
+: <a class="el" href="dss__soc_8h.html#a9b73eea7de83a9a39a1f200ec4096e4d">dss_soc.h</a>
+</li>
+<li>DSS_DISP_INST_VIDL1
+: <a class="el" href="dss__soc_8h.html#ad56ec47be5d8455998b861548c38ceec">dss_soc.h</a>
+</li>
+<li>DSS_DISP_IOCTL_BASE
+: <a class="el" href="group___d_s_s.html#gaf8566eb291e6ce8c67bf5158426d42b9">dss.h</a>
+</li>
+<li>DSS_EVT_MGR_INST_ID_FUNC
+: <a class="el" href="dss__soc_8h.html#a2d58a192f10fab6608c8f1cde2489aa5">dss_soc.h</a>
+</li>
+<li>DSS_EVT_MGR_INST_ID_INVALID
+: <a class="el" href="dss__soc_8h.html#aa6df7d5f82c9928bd28c3031bef4adbc">dss_soc.h</a>
+</li>
+<li>DSS_EVT_MGR_INST_ID_MAX
+: <a class="el" href="dss__soc_8h.html#a655e39bd46b2a70609bd7d6c878f394f">dss_soc.h</a>
+</li>
+<li>DSS_FUNC_IRQ_DEFAULT_NUM
+: <a class="el" href="dss__soc_8h.html#aa7ac2fb77b879354f19126b346099294">dss_soc.h</a>
+</li>
+<li>DssTrace
+: <a class="el" href="dss__cfg_8h.html#a76ace3e354893fc499603be1fbe3d1b2">dss_cfg.h</a>
+</li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/globals_defs_f.html b/packages/ti/drv/dss/docs/doxygen/html/globals_defs_f.html
--- /dev/null
@@ -0,0 +1,932 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Globals</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li class="current"><a href="files.html"><span>Files</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow2" class="tabs2">
+ <ul class="tablist">
+ <li><a href="files.html"><span>File List</span></a></li>
+ <li class="current"><a href="globals.html"><span>Globals</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow3" class="tabs2">
+ <ul class="tablist">
+ <li><a href="globals.html"><span>All</span></a></li>
+ <li><a href="globals_func.html"><span>Functions</span></a></li>
+ <li><a href="globals_type.html"><span>Typedefs</span></a></li>
+ <li><a href="globals_enum.html"><span>Enumerations</span></a></li>
+ <li><a href="globals_eval.html"><span>Enumerator</span></a></li>
+ <li class="current"><a href="globals_defs.html"><span>Macros</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow4" class="tabs3">
+ <ul class="tablist">
+ <li><a href="globals_defs.html#index_c"><span>c</span></a></li>
+ <li><a href="globals_defs_d.html#index_d"><span>d</span></a></li>
+ <li class="current"><a href="globals_defs_f.html#index_f"><span>f</span></a></li>
+ <li><a href="globals_defs_i.html#index_i"><span>i</span></a></li>
+ </ul>
+ </div>
+</div><!-- top -->
+<div class="contents">
+ 
+
+<h3><a class="anchor" id="index_f"></a>- f -</h3><ul>
+<li>FVID2_BUF_FMT_FIELD
+: <a class="el" href="csl__fvid2__data_types_8h.html#afa226435f563ae5b91e94e8e0728a12c">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_BUF_FMT_FRAME
+: <a class="el" href="csl__fvid2__data_types_8h.html#aac021d82bbc20a8ce5ea9a88a2cd8dd0">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_CCSF_BITS10_PACKED
+: <a class="el" href="csl__fvid2__data_types_8h.html#af3ac23834ffbf9aa575aa1aa1ba5f5dd">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_CCSF_BITS10_UNPACKED16
+: <a class="el" href="csl__fvid2__data_types_8h.html#aac7eaa1f4b68b84dca644e7b3a4a02a8">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_CCSF_BITS10_UNPACKED16_MSB_ALIGNED
+: <a class="el" href="csl__fvid2__data_types_8h.html#a9085719b19b28a5cbad6a65d79d297f6">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_CCSF_BITS11_UNPACKED16
+: <a class="el" href="csl__fvid2__data_types_8h.html#a4f53868e86fd933d7e8998fc78dd835b">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_CCSF_BITS11_UNPACKED16_MSB_ALIGNED
+: <a class="el" href="csl__fvid2__data_types_8h.html#a8917b7740656c6d3832d67df9881ab8e">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_CCSF_BITS12_PACKED
+: <a class="el" href="csl__fvid2__data_types_8h.html#aaca4732e06c1a91049170d81747e54ef">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_CCSF_BITS12_UNPACKED16
+: <a class="el" href="csl__fvid2__data_types_8h.html#a8b42effc244c7f41159f640a4843ec17">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_CCSF_BITS12_UNPACKED16_MSB_ALIGNED
+: <a class="el" href="csl__fvid2__data_types_8h.html#a303e8ae9078fddebfaaa00ccbc8326fc">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_CCSF_BITS13_UNPACKED16
+: <a class="el" href="csl__fvid2__data_types_8h.html#a00f1d329f88f72cf5ac0b12306c71637">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_CCSF_BITS13_UNPACKED16_MSB_ALIGNED
+: <a class="el" href="csl__fvid2__data_types_8h.html#a7bf5cca0a682a0b00276a425f1b8291b">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_CCSF_BITS14_PACKED
+: <a class="el" href="csl__fvid2__data_types_8h.html#a83bbd32f9354c1456bb2483aea4e1f9c">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_CCSF_BITS14_UNPACKED16
+: <a class="el" href="csl__fvid2__data_types_8h.html#a97e208768c0a77614e9add93dfeb53c4">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_CCSF_BITS14_UNPACKED16_MSB_ALIGNED
+: <a class="el" href="csl__fvid2__data_types_8h.html#a76a2d25e1dc39f445ff81ecb1966ca18">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_CCSF_BITS15_UNPACKED16
+: <a class="el" href="csl__fvid2__data_types_8h.html#a6c2b17f6ec2ac3f348d422ac7a7d4433">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_CCSF_BITS15_UNPACKED16_MSB_ALIGNED
+: <a class="el" href="csl__fvid2__data_types_8h.html#a56e845ec6128209b54547e4615bac029">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_CCSF_BITS16_PACKED
+: <a class="el" href="csl__fvid2__data_types_8h.html#a04ecc76a7481ee23eb31ee72d373f67f">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_CCSF_BITS1_PACKED
+: <a class="el" href="csl__fvid2__data_types_8h.html#ab926a2bd1d85a43a6cd118b522c36da9">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_CCSF_BITS20_UNPACKED24
+: <a class="el" href="csl__fvid2__data_types_8h.html#a988e90d38af500d421c021a047abf722">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_CCSF_BITS20_UNPACKED24_MSB_ALIGNED
+: <a class="el" href="csl__fvid2__data_types_8h.html#aa464f94a49c7e913fb48d3ad212b3063">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_CCSF_BITS24_PACKED
+: <a class="el" href="csl__fvid2__data_types_8h.html#a785fa5e01bef9af1c292209f5cccf5cd">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_CCSF_BITS2_PACKED
+: <a class="el" href="csl__fvid2__data_types_8h.html#a594de86d607039309992132021df72c1">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_CCSF_BITS32_PACKED
+: <a class="el" href="csl__fvid2__data_types_8h.html#a54169847d76c66ad23f937e1b39b9f67">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_CCSF_BITS4_PACKED
+: <a class="el" href="csl__fvid2__data_types_8h.html#a9707de69ccc80d650d2adc52fbf3b410">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_CCSF_BITS6_UNPACKED8
+: <a class="el" href="csl__fvid2__data_types_8h.html#ac2fb823eb58d916b329917b1eb61e11b">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_CCSF_BITS6_UNPACKED8_MSB_ALIGNED
+: <a class="el" href="csl__fvid2__data_types_8h.html#a61dddf1df3cf8174f8d3917ae3773694">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_CCSF_BITS7_UNPACKED8
+: <a class="el" href="csl__fvid2__data_types_8h.html#a07455c28c2c98f6b2d421a99aa6c4f9a">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_CCSF_BITS7_UNPACKED8_MSB_ALIGNED
+: <a class="el" href="csl__fvid2__data_types_8h.html#a51b1da78a40589438bc13185782b319d">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_CCSF_BITS8_PACKED
+: <a class="el" href="csl__fvid2__data_types_8h.html#a3a142fe37655cbd712f9e01c91d5db4d">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_CCSF_BITS8_UNPACKED12
+: <a class="el" href="csl__fvid2__data_types_8h.html#a00417ee1982d86db35983a405a0ec036">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_CCSF_BITS8_UNPACKED12_MSB_ALIGNED
+: <a class="el" href="csl__fvid2__data_types_8h.html#a813c1e0799dccb563604154a11881e6a">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_CCSF_BITS8_UNPACKED16
+: <a class="el" href="csl__fvid2__data_types_8h.html#afd8b6daeed620a8114ed0486cab137a1">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_CCSF_BITS8_UNPACKED16_MSB_ALIGNED
+: <a class="el" href="csl__fvid2__data_types_8h.html#a1b8537b0791ad34722a02f0b8b4c304d">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_CCSF_BITS9_UNPACKED16
+: <a class="el" href="csl__fvid2__data_types_8h.html#a299dac024c0d2cc79833a7b8f464fcf8">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_CCSF_BITS9_UNPACKED16_MSB_ALIGNED
+: <a class="el" href="csl__fvid2__data_types_8h.html#af2178a61154ebb9c186a253a65409583">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_CCSF_MAX
+: <a class="el" href="csl__fvid2__data_types_8h.html#a5c9edcc22a7b1b990efc98af43912f49">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_DF_ABGR16_1555
+: <a class="el" href="csl__fvid2__data_types_8h.html#a00daf662fcdcb2597982219fb65acc10">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_DF_ABGR16_4444
+: <a class="el" href="csl__fvid2__data_types_8h.html#a6072fd045d93236b07e78c370c10a34c">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_DF_ABGR24_6666
+: <a class="el" href="csl__fvid2__data_types_8h.html#a67826657e1c94c81a777ce2a3df6c9ec">csl_fvid2_dataTypes.h</a>
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+</li>
+<li>FVID2_STD_MUX_4CH_HALF_D1
+: <a class="el" href="csl__fvid2__data_types_8h.html#a5afbbf47084865e341f0870ee30cc739">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_STD_MUX_8CH_CIF
+: <a class="el" href="csl__fvid2__data_types_8h.html#a1d96d34832944c554b3b7adb6ebad4d9">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_STD_MUX_8CH_HALF_D1
+: <a class="el" href="csl__fvid2__data_types_8h.html#a3829733b32609b9a5f9f6f0bbd6714e5">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_STD_NTSC
+: <a class="el" href="csl__fvid2__data_types_8h.html#a508515b25947ede0cb5c03afc572f56d">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_STD_PAL
+: <a class="el" href="csl__fvid2__data_types_8h.html#a7bd496bf85b4038f0fd0c841b741e968">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_STD_SVGA_60
+: <a class="el" href="csl__fvid2__data_types_8h.html#ac326c1d1653379357aa624d639c811c7">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_STD_SVGA_72
+: <a class="el" href="csl__fvid2__data_types_8h.html#a37351c4d4096383e2d5d72316af3f4f0">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_STD_SVGA_75
+: <a class="el" href="csl__fvid2__data_types_8h.html#a36e85a9212920839f4cdea2f97774d00">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_STD_SVGA_85
+: <a class="el" href="csl__fvid2__data_types_8h.html#abe1e836c388da56174b6fba2a98fec2d">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_STD_SXGA_60
+: <a class="el" href="csl__fvid2__data_types_8h.html#a5f2b699f67df490f4922f0cf80e12a17">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_STD_SXGA_75
+: <a class="el" href="csl__fvid2__data_types_8h.html#a3240f384b90e33105de53c735ac24ab8">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_STD_SXGA_85
+: <a class="el" href="csl__fvid2__data_types_8h.html#a89f1f4cd2d6c4ba37f143a804e09e56d">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_STD_SXGAP_60
+: <a class="el" href="csl__fvid2__data_types_8h.html#ac57de538e6e7c03b518f40b576b78e54">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_STD_SXGAP_75
+: <a class="el" href="csl__fvid2__data_types_8h.html#ab8bb357f5290805dae7cb93e59207ca6">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_STD_UXGA_60
+: <a class="el" href="csl__fvid2__data_types_8h.html#a857b7d7d1443a364f5642fcd8f9fcad0">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_STD_VGA_60
+: <a class="el" href="csl__fvid2__data_types_8h.html#a539104247aec67a1e9a02e99c5dcf644">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_STD_VGA_72
+: <a class="el" href="csl__fvid2__data_types_8h.html#a071ae5ffed3b0dae002efb8bed4a6ff0">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_STD_VGA_75
+: <a class="el" href="csl__fvid2__data_types_8h.html#ab3dcebfeb086005fc35de1dd08922cf6">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_STD_VGA_85
+: <a class="el" href="csl__fvid2__data_types_8h.html#a331cf0ca858d87e3c005a3441a9bb723">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_STD_WSVGA_70
+: <a class="el" href="csl__fvid2__data_types_8h.html#ab49cbaf2b57c299a579e3c97eb72f37b">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_STD_WSXGAP_60
+: <a class="el" href="csl__fvid2__data_types_8h.html#a7a77706faae342689c3e8dd2f31a442a">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_STD_WVGA_60
+: <a class="el" href="csl__fvid2__data_types_8h.html#ac23e7e176ae9d5ac95f5a89abce32520">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_STD_WXGA_30
+: <a class="el" href="csl__fvid2__data_types_8h.html#a576daaef9c5b1c823b3107c9bb96d114">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_STD_WXGA_5x3_30
+: <a class="el" href="csl__fvid2__data_types_8h.html#aaab0c4817ec5e9f10f0c13d5375e1d30">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_STD_WXGA_5x3_60
+: <a class="el" href="csl__fvid2__data_types_8h.html#ad69ca1aed51329f28c87873b2544dd0e">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_STD_WXGA_5x3_75
+: <a class="el" href="csl__fvid2__data_types_8h.html#a42448ed6ed591d189584a9d6751c2edf">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_STD_WXGA_60
+: <a class="el" href="csl__fvid2__data_types_8h.html#a014e933fc51a2bd62139614d022c9b26">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_STD_WXGA_75
+: <a class="el" href="csl__fvid2__data_types_8h.html#a16436c69aafd74ca687088aaae15ba76">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_STD_WXGA_85
+: <a class="el" href="csl__fvid2__data_types_8h.html#af3565ee49136c5a00d8c07f68ebd453e">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_STD_XGA_60
+: <a class="el" href="csl__fvid2__data_types_8h.html#a2a3be1bf860b622d3561bb1b795fc414">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_STD_XGA_70
+: <a class="el" href="csl__fvid2__data_types_8h.html#a351fd686457f2bb276ffc6f5064cbd9e">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_STD_XGA_75
+: <a class="el" href="csl__fvid2__data_types_8h.html#aae15675f7a5d749ee8acfa542e05d8a9">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_STD_XGA_85
+: <a class="el" href="csl__fvid2__data_types_8h.html#a351e7a94e0446f709932fd8505ca8402">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_STD_XGA_DSS_TDM_60
+: <a class="el" href="csl__fvid2__data_types_8h.html#ae303cf581ad8069ed5bd6862003fdc83">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_TIMEOUT_FOREVER
+: <a class="el" href="csl__fvid2__data_types_8h.html#ac39a381aee86801c727735f635719cef">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_TIMEOUT_NONE
+: <a class="el" href="csl__fvid2__data_types_8h.html#a88e886eb47cb269040fb5bc7fda3f82c">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_VIFW_10BIT
+: <a class="el" href="csl__fvid2__data_types_8h.html#ac3a717fe05ad4965118af833cf59e344">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_VIFW_12BIT
+: <a class="el" href="csl__fvid2__data_types_8h.html#aa4f84d19ce06a5392a81a6f377eca451">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_VIFW_14BIT
+: <a class="el" href="csl__fvid2__data_types_8h.html#a231633928ad65ad5c614fd4c99e02f63">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_VIFW_16BIT
+: <a class="el" href="csl__fvid2__data_types_8h.html#a1e9c51d0e52003c568876305d8b5ac4a">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_VIFW_18BIT
+: <a class="el" href="csl__fvid2__data_types_8h.html#a5f82958aa532079ce0d121b6abfa6290">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_VIFW_1LANES
+: <a class="el" href="csl__fvid2__data_types_8h.html#ac0f2644123a9cfad25d5d1394cd83b07">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_VIFW_20BIT
+: <a class="el" href="csl__fvid2__data_types_8h.html#a737fba3bfb51d5a0db8d273dc62c6f55">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_VIFW_24BIT
+: <a class="el" href="csl__fvid2__data_types_8h.html#af0ca9fef4970890bdb6c3294e3488dd2">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_VIFW_2LANES
+: <a class="el" href="csl__fvid2__data_types_8h.html#a0bf298ec713b45e4412921b840700b21">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_VIFW_30BIT
+: <a class="el" href="csl__fvid2__data_types_8h.html#ab662f4e73161ba1c2b0def811521f144">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_VIFW_36BIT
+: <a class="el" href="csl__fvid2__data_types_8h.html#a3bbc392f936b3fc101d207b191832032">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_VIFW_3LANES
+: <a class="el" href="csl__fvid2__data_types_8h.html#ab6c39f963bb8d0873cd040f80df74528">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_VIFW_4LANES
+: <a class="el" href="csl__fvid2__data_types_8h.html#a855c0790a50e48407a58b4e6682005d8">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_VIFW_8BIT
+: <a class="el" href="csl__fvid2__data_types_8h.html#a2dcc786e9b4d47f2408761a012f5760a">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_VIFW_MAX
+: <a class="el" href="csl__fvid2__data_types_8h.html#a3fc89d365c319b7999dfab0a24269105">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_WNON_RECOMMENDED_PARAMS
+: <a class="el" href="csl__fvid2__data_types_8h.html#aedcb86d5a2e3ec73847eca004e037535">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_YUV_INT_ADDR_IDX
+: <a class="el" href="csl__fvid2__data_types_8h.html#a964627052348693970b6b8078a622a11">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_YUV_INT_FID2_ADDR_IDX
+: <a class="el" href="csl__fvid2__data_types_8h.html#a909f592eabc1bf70b9a3dab15e468713">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_YUV_PL_CB_ADDR_IDX
+: <a class="el" href="csl__fvid2__data_types_8h.html#ada7ebea730d1889e88c13b17c5b2d053">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_YUV_PL_CB_FID2_ADDR_IDX
+: <a class="el" href="csl__fvid2__data_types_8h.html#a8af505377d5f361ec078e9181336d42e">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_YUV_PL_CR_ADDR_IDX
+: <a class="el" href="csl__fvid2__data_types_8h.html#a0bbd3a8627de6776fc92458a8b3c6a4a">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_YUV_PL_CR_FID2_ADDR_IDX
+: <a class="el" href="csl__fvid2__data_types_8h.html#a74bcea671e6e8833edbd978fd0dd27be">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_YUV_PL_Y_ADDR_IDX
+: <a class="el" href="csl__fvid2__data_types_8h.html#a9ff732b464eedfe4640b4169970765c8">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_YUV_PL_Y_FID2_ADDR_IDX
+: <a class="el" href="csl__fvid2__data_types_8h.html#a16d75a000e95e205d6ef10eb5a6a7005">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_YUV_SP_CBCR_ADDR_IDX
+: <a class="el" href="csl__fvid2__data_types_8h.html#a12c8a4aa7624a1d6e007cb29331f1119">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_YUV_SP_CBCR_FID2_ADDR_IDX
+: <a class="el" href="csl__fvid2__data_types_8h.html#a32797001f230161fdd9b1a26755061ee">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_YUV_SP_Y_ADDR_IDX
+: <a class="el" href="csl__fvid2__data_types_8h.html#a9a79f5ef34a964258855d87b738cc19f">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_YUV_SP_Y_FID2_ADDR_IDX
+: <a class="el" href="csl__fvid2__data_types_8h.html#acebcf1dfbbc29d3e139e95b4f4c5ed6d">csl_fvid2_dataTypes.h</a>
+</li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/globals_defs_i.html b/packages/ti/drv/dss/docs/doxygen/html/globals_defs_i.html
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+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Globals</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li class="current"><a href="files.html"><span>Files</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow2" class="tabs2">
+ <ul class="tablist">
+ <li><a href="files.html"><span>File List</span></a></li>
+ <li class="current"><a href="globals.html"><span>Globals</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow3" class="tabs2">
+ <ul class="tablist">
+ <li><a href="globals.html"><span>All</span></a></li>
+ <li><a href="globals_func.html"><span>Functions</span></a></li>
+ <li><a href="globals_type.html"><span>Typedefs</span></a></li>
+ <li><a href="globals_enum.html"><span>Enumerations</span></a></li>
+ <li><a href="globals_eval.html"><span>Enumerator</span></a></li>
+ <li class="current"><a href="globals_defs.html"><span>Macros</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow4" class="tabs3">
+ <ul class="tablist">
+ <li><a href="globals_defs.html#index_c"><span>c</span></a></li>
+ <li><a href="globals_defs_d.html#index_d"><span>d</span></a></li>
+ <li><a href="globals_defs_f.html#index_f"><span>f</span></a></li>
+ <li class="current"><a href="globals_defs_i.html#index_i"><span>i</span></a></li>
+ </ul>
+ </div>
+</div><!-- top -->
+<div class="contents">
+ 
+
+<h3><a class="anchor" id="index_i"></a>- i -</h3><ul>
+<li>IOCTL_DSS_DCTRL_CLEAR_PATH
+: <a class="el" href="group___d_s_s___d_c_t_r_l___i_o_c_t_l.html#ga4b16831ed360d38789d105376246c41a">dss_dctrl.h</a>
+</li>
+<li>IOCTL_DSS_DCTRL_GET_VP_ERROR_STATS
+: <a class="el" href="group___d_s_s___d_c_t_r_l___i_o_c_t_l.html#ga3d29253c153bdec7275527bd0b8fe4dc">dss_dctrl.h</a>
+</li>
+<li>IOCTL_DSS_DCTRL_REGISTER_SYNCLOST_CB
+: <a class="el" href="group___d_s_s___d_c_t_r_l___i_o_c_t_l.html#gae4ab29ac71849b0ad7810e5fecaf2b00">dss_dctrl.h</a>
+</li>
+<li>IOCTL_DSS_DCTRL_SET_ADV_VP_PARAMS
+: <a class="el" href="group___d_s_s___d_c_t_r_l___i_o_c_t_l.html#ga41ce0b6adeb9b7e098ce3b84113bf48f">dss_dctrl.h</a>
+</li>
+<li>IOCTL_DSS_DCTRL_SET_GLOBAL_DSS_PARAMS
+: <a class="el" href="group___d_s_s___d_c_t_r_l___i_o_c_t_l.html#ga48fd0f5f1e1476ef03b203ae9b1ccfaa">dss_dctrl.h</a>
+</li>
+<li>IOCTL_DSS_DCTRL_SET_LAYER_PARAMS
+: <a class="el" href="group___d_s_s___d_c_t_r_l___i_o_c_t_l.html#ga824609e625e41769f9042b8879a73861">dss_dctrl.h</a>
+</li>
+<li>IOCTL_DSS_DCTRL_SET_LCD_BLANK_TIMING_PARAMS
+: <a class="el" href="group___d_s_s___d_c_t_r_l___i_o_c_t_l.html#ga381f6aa554cc69e7fdb6dc6022086cee">dss_dctrl.h</a>
+</li>
+<li>IOCTL_DSS_DCTRL_SET_OLDI_PARAMS
+: <a class="el" href="group___d_s_s___d_c_t_r_l___i_o_c_t_l.html#ga0605d3de6b43d543ab11a8ba54a5fdbc">dss_dctrl.h</a>
+</li>
+<li>IOCTL_DSS_DCTRL_SET_OVERLAY_PARAMS
+: <a class="el" href="group___d_s_s___d_c_t_r_l___i_o_c_t_l.html#ga076d70564e492c0780bc4c747ca7ee82">dss_dctrl.h</a>
+</li>
+<li>IOCTL_DSS_DCTRL_SET_PATH
+: <a class="el" href="group___d_s_s___d_c_t_r_l___i_o_c_t_l.html#gae55f1184bc13a50a4e113e95835a5d0c">dss_dctrl.h</a>
+</li>
+<li>IOCTL_DSS_DCTRL_SET_VP_CSC_COEFF
+: <a class="el" href="group___d_s_s___d_c_t_r_l___i_o_c_t_l.html#gad01ce1c58a3a6966395f29a6d61d7684">dss_dctrl.h</a>
+</li>
+<li>IOCTL_DSS_DCTRL_SET_VP_PARAMS
+: <a class="el" href="group___d_s_s___d_c_t_r_l___i_o_c_t_l.html#gad9d06c559d83e6b0cd1fb72dfeca55c0">dss_dctrl.h</a>
+</li>
+<li>IOCTL_DSS_DCTRL_SET_VP_SAFETY_CHK_PARAMS
+: <a class="el" href="group___d_s_s___d_c_t_r_l___i_o_c_t_l.html#gabcaa1961abdf4145c9db4cedffe58259">dss_dctrl.h</a>
+</li>
+<li>IOCTL_DSS_DCTRL_STOP_VP
+: <a class="el" href="group___d_s_s___d_c_t_r_l___i_o_c_t_l.html#ga626c83cf4afb58295e807b710e10c5b0">dss_dctrl.h</a>
+</li>
+<li>IOCTL_DSS_DISP_GET_CURRENT_STATUS
+: <a class="el" href="group___d_s_s___d_i_s_p___i_o_c_t_l.html#ga0b629ede4d23a166a0d61a8a467cf2a7">dss_disp.h</a>
+</li>
+<li>IOCTL_DSS_DISP_REGISTER_BUF_PRGM_CB
+: <a class="el" href="group___d_s_s___d_i_s_p___i_o_c_t_l.html#ga273f588861739dcf0a3e69409cb86946">dss_disp.h</a>
+</li>
+<li>IOCTL_DSS_DISP_REGISTER_PIPE_PRGM_CB
+: <a class="el" href="group___d_s_s___d_i_s_p___i_o_c_t_l.html#ga0cb126061bb1b12410ac877e1f8ba1eb">dss_disp.h</a>
+</li>
+<li>IOCTL_DSS_DISP_REGISTER_PIPE_UNDERFLOW_CB
+: <a class="el" href="group___d_s_s___d_i_s_p___i_o_c_t_l.html#ga50c39b909c3e819d5662285112bbca59">dss_disp.h</a>
+</li>
+<li>IOCTL_DSS_DISP_SET_DSS_PARAMS
+: <a class="el" href="group___d_s_s___d_i_s_p___i_o_c_t_l.html#ga4bd8cea3f070081f575996cc7fe3571f">dss_disp.h</a>
+</li>
+<li>IOCTL_DSS_DISP_SET_PIPE_CSC_COEFF
+: <a class="el" href="group___d_s_s___d_i_s_p___i_o_c_t_l.html#gaa06196d5ebeb859291214d2d54b6858b">dss_disp.h</a>
+</li>
+<li>IOCTL_DSS_DISP_SET_PIPE_MFLAG_PARAMS
+: <a class="el" href="group___d_s_s___d_i_s_p___i_o_c_t_l.html#ga9643f8f73bbe0006d0c56d0bcedccef5">dss_disp.h</a>
+</li>
+<li>IOCTL_DSS_DISP_SET_PIPE_SAFETY_CHK_PARAMS
+: <a class="el" href="group___d_s_s___d_i_s_p___i_o_c_t_l.html#ga71325651456731ff972f3f976632f817">dss_disp.h</a>
+</li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/globals_enum.html b/packages/ti/drv/dss/docs/doxygen/html/globals_enum.html
--- /dev/null
@@ -0,0 +1,58 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Globals</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li class="current"><a href="files.html"><span>Files</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow2" class="tabs2">
+ <ul class="tablist">
+ <li><a href="files.html"><span>File List</span></a></li>
+ <li class="current"><a href="globals.html"><span>Globals</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow3" class="tabs2">
+ <ul class="tablist">
+ <li><a href="globals.html"><span>All</span></a></li>
+ <li><a href="globals_func.html"><span>Functions</span></a></li>
+ <li><a href="globals_type.html"><span>Typedefs</span></a></li>
+ <li class="current"><a href="globals_enum.html"><span>Enumerations</span></a></li>
+ <li><a href="globals_eval.html"><span>Enumerator</span></a></li>
+ <li><a href="globals_defs.html"><span>Macros</span></a></li>
+ </ul>
+ </div>
+</div><!-- top -->
+<div class="contents">
+ <ul>
+<li>Fvid2_BayerColorComp
+: <a class="el" href="csl__fvid2__data_types_8h.html#ac5d9776b0da6459f3f9cfbcbce8eec18">csl_fvid2_dataTypes.h</a>
+</li>
+<li>Fvid2_ChromaPos
+: <a class="el" href="csl__fvid2__data_types_8h.html#a6372ae9694a790a94e2da8e06d76b540">csl_fvid2_dataTypes.h</a>
+</li>
+<li>Fvid2_FrameStatus
+: <a class="el" href="csl__fvid2__data_types_8h.html#a248e190fab40aca929969c432068a099">csl_fvid2_dataTypes.h</a>
+</li>
+<li>Fvid2_VideoIfMode
+: <a class="el" href="csl__fvid2__data_types_8h.html#a4e1d4b630095a3e5f9d560b839603a8e">csl_fvid2_dataTypes.h</a>
+</li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/globals_eval.html b/packages/ti/drv/dss/docs/doxygen/html/globals_eval.html
--- /dev/null
@@ -0,0 +1,136 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Globals</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li class="current"><a href="files.html"><span>Files</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow2" class="tabs2">
+ <ul class="tablist">
+ <li><a href="files.html"><span>File List</span></a></li>
+ <li class="current"><a href="globals.html"><span>Globals</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow3" class="tabs2">
+ <ul class="tablist">
+ <li><a href="globals.html"><span>All</span></a></li>
+ <li><a href="globals_func.html"><span>Functions</span></a></li>
+ <li><a href="globals_type.html"><span>Typedefs</span></a></li>
+ <li><a href="globals_enum.html"><span>Enumerations</span></a></li>
+ <li class="current"><a href="globals_eval.html"><span>Enumerator</span></a></li>
+ <li><a href="globals_defs.html"><span>Macros</span></a></li>
+ </ul>
+ </div>
+</div><!-- top -->
+<div class="contents">
+ <ul>
+<li>FVID2_BAYER_COLOR_COMP_B
+: <a class="el" href="csl__fvid2__data_types_8h.html#ac5d9776b0da6459f3f9cfbcbce8eec18aab7a458ffc41a81da35d21b7160745d0">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_BAYER_COLOR_COMP_GB
+: <a class="el" href="csl__fvid2__data_types_8h.html#ac5d9776b0da6459f3f9cfbcbce8eec18af8760d6393d606fa75b0948835d026f8">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_BAYER_COLOR_COMP_GR
+: <a class="el" href="csl__fvid2__data_types_8h.html#ac5d9776b0da6459f3f9cfbcbce8eec18a8a20bb44d83f09c3216382a281468f10">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_BAYER_COLOR_COMP_MAX
+: <a class="el" href="csl__fvid2__data_types_8h.html#ac5d9776b0da6459f3f9cfbcbce8eec18ae4b13df43936976b20342bcfe77957a3">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_BAYER_COLOR_COMP_R
+: <a class="el" href="csl__fvid2__data_types_8h.html#ac5d9776b0da6459f3f9cfbcbce8eec18ae8725e59cc3be75abc7b2211be865db3">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_CHROMA_POS_CENTERED
+: <a class="el" href="csl__fvid2__data_types_8h.html#a6372ae9694a790a94e2da8e06d76b540a354971423ce04887bfb431e05790568c">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_CHROMA_POS_COSITED
+: <a class="el" href="csl__fvid2__data_types_8h.html#a6372ae9694a790a94e2da8e06d76b540a2d0e94bc80160340b9f3ea5ef2df480a">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_FRAME_STATUS_ABORTED
+: <a class="el" href="csl__fvid2__data_types_8h.html#a248e190fab40aca929969c432068a099a43d4d377646d7279138602a7aeac3f72">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_FRAME_STATUS_COMPLETED
+: <a class="el" href="csl__fvid2__data_types_8h.html#a248e190fab40aca929969c432068a099a696c6a4cbd00246b5c1e4370fa302055">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_FRAME_STATUS_CRC_ERROR
+: <a class="el" href="csl__fvid2__data_types_8h.html#a248e190fab40aca929969c432068a099a84c41401ba6a29d9ca60b93a48803202">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_FRAME_STATUS_ECC_CORRECTED
+: <a class="el" href="csl__fvid2__data_types_8h.html#a248e190fab40aca929969c432068a099a475443372b2fb2763923f7d58b5f467a">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_FRAME_STATUS_ECC_ERROR
+: <a class="el" href="csl__fvid2__data_types_8h.html#a248e190fab40aca929969c432068a099a38f88ca4ff3a06f88914c71a5c1b7c0e">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_FRAME_STATUS_ERROR
+: <a class="el" href="csl__fvid2__data_types_8h.html#a248e190fab40aca929969c432068a099ac9611a6508b8e02547b4706cc38ad89d">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_FRAME_STATUS_INIT
+: <a class="el" href="csl__fvid2__data_types_8h.html#a248e190fab40aca929969c432068a099adf9e647770fecfbd9ace849d2db8f988">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_FRAME_STATUS_MAX
+: <a class="el" href="csl__fvid2__data_types_8h.html#a248e190fab40aca929969c432068a099ae0e4d1baff68faaadda86f76db875869">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_FRAME_STATUS_OVERFLOW
+: <a class="el" href="csl__fvid2__data_types_8h.html#a248e190fab40aca929969c432068a099abebee14dd307042e25082acf1b1270f5">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_FRAME_STATUS_PENDING
+: <a class="el" href="csl__fvid2__data_types_8h.html#a248e190fab40aca929969c432068a099aeefebb0a00827e6d2362df182c6e0709">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_FRAME_STATUS_SUBMITTED
+: <a class="el" href="csl__fvid2__data_types_8h.html#a248e190fab40aca929969c432068a099afb0044f14c3f1d87d92611b1b13c3a02">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_VIFM_MAX
+: <a class="el" href="csl__fvid2__data_types_8h.html#a4e1d4b630095a3e5f9d560b839603a8ea06e8f99dd0b137efcc6ca8e2e2f15527">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_VIFM_MCH_LINE_MUX_ES
+: <a class="el" href="csl__fvid2__data_types_8h.html#a4e1d4b630095a3e5f9d560b839603a8ea7e22126a15add08aeabce4216492c88b">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_VIFM_MCH_LINE_MUX_SPLIT_LINE_ES
+: <a class="el" href="csl__fvid2__data_types_8h.html#a4e1d4b630095a3e5f9d560b839603a8eac7aceedd75323567a399f68742d54ccb">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_VIFM_MCH_PIXEL_MUX_ES
+: <a class="el" href="csl__fvid2__data_types_8h.html#a4e1d4b630095a3e5f9d560b839603a8ea07b6e18e02112c367d6bd3b380d2d9d3">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_VIFM_SCH_CPI
+: <a class="el" href="csl__fvid2__data_types_8h.html#a4e1d4b630095a3e5f9d560b839603a8ea03c1d8ab4e4325886e9c8553f0c6708f">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_VIFM_SCH_CSI2
+: <a class="el" href="csl__fvid2__data_types_8h.html#a4e1d4b630095a3e5f9d560b839603a8ea0caef0a1234afe67eed22370729d04f8">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_VIFM_SCH_DS_AVID_VBLK
+: <a class="el" href="csl__fvid2__data_types_8h.html#a4e1d4b630095a3e5f9d560b839603a8ea2fa8c574decaca5d94b93a6c8aa2ae64">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_VIFM_SCH_DS_AVID_VSYNC
+: <a class="el" href="csl__fvid2__data_types_8h.html#a4e1d4b630095a3e5f9d560b839603a8ea901482ffa323be1fb48302f7404930a6">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_VIFM_SCH_DS_HSYNC_VBLK
+: <a class="el" href="csl__fvid2__data_types_8h.html#a4e1d4b630095a3e5f9d560b839603a8ea7ffc6821187a28919e2ee5f8723199b1">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_VIFM_SCH_DS_HSYNC_VSYNC
+: <a class="el" href="csl__fvid2__data_types_8h.html#a4e1d4b630095a3e5f9d560b839603a8ea41dea0d5f63dd2ea51de8030460f6527">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_VIFM_SCH_ES
+: <a class="el" href="csl__fvid2__data_types_8h.html#a4e1d4b630095a3e5f9d560b839603a8ea0c1ebff799492bc87e0947ea5b4af1e6">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_VIFM_SCH_LVDS
+: <a class="el" href="csl__fvid2__data_types_8h.html#a4e1d4b630095a3e5f9d560b839603a8ea83e693e66bda0561fb9c4cc81733fa87">csl_fvid2_dataTypes.h</a>
+</li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/globals_f.html b/packages/ti/drv/dss/docs/doxygen/html/globals_f.html
--- /dev/null
@@ -0,0 +1,1148 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Globals</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li class="current"><a href="files.html"><span>Files</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow2" class="tabs2">
+ <ul class="tablist">
+ <li><a href="files.html"><span>File List</span></a></li>
+ <li class="current"><a href="globals.html"><span>Globals</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow3" class="tabs2">
+ <ul class="tablist">
+ <li class="current"><a href="globals.html"><span>All</span></a></li>
+ <li><a href="globals_func.html"><span>Functions</span></a></li>
+ <li><a href="globals_type.html"><span>Typedefs</span></a></li>
+ <li><a href="globals_enum.html"><span>Enumerations</span></a></li>
+ <li><a href="globals_eval.html"><span>Enumerator</span></a></li>
+ <li><a href="globals_defs.html"><span>Macros</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow4" class="tabs3">
+ <ul class="tablist">
+ <li><a href="globals.html#index_c"><span>c</span></a></li>
+ <li><a href="globals_d.html#index_d"><span>d</span></a></li>
+ <li class="current"><a href="globals_f.html#index_f"><span>f</span></a></li>
+ <li><a href="globals_i.html#index_i"><span>i</span></a></li>
+ </ul>
+ </div>
+</div><!-- top -->
+<div class="contents">
+<div class="textblock">Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation:</div>
+
+<h3><a class="anchor" id="index_f"></a>- f -</h3><ul>
+<li>FVID2_BAYER_COLOR_COMP_B
+: <a class="el" href="csl__fvid2__data_types_8h.html#ac5d9776b0da6459f3f9cfbcbce8eec18aab7a458ffc41a81da35d21b7160745d0">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_BAYER_COLOR_COMP_GB
+: <a class="el" href="csl__fvid2__data_types_8h.html#ac5d9776b0da6459f3f9cfbcbce8eec18af8760d6393d606fa75b0948835d026f8">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_BAYER_COLOR_COMP_GR
+: <a class="el" href="csl__fvid2__data_types_8h.html#ac5d9776b0da6459f3f9cfbcbce8eec18a8a20bb44d83f09c3216382a281468f10">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_BAYER_COLOR_COMP_MAX
+: <a class="el" href="csl__fvid2__data_types_8h.html#ac5d9776b0da6459f3f9cfbcbce8eec18ae4b13df43936976b20342bcfe77957a3">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_BAYER_COLOR_COMP_R
+: <a class="el" href="csl__fvid2__data_types_8h.html#ac5d9776b0da6459f3f9cfbcbce8eec18ae8725e59cc3be75abc7b2211be865db3">csl_fvid2_dataTypes.h</a>
+</li>
+<li>Fvid2_BayerColorComp
+: <a class="el" href="csl__fvid2__data_types_8h.html#ac5d9776b0da6459f3f9cfbcbce8eec18">csl_fvid2_dataTypes.h</a>
+</li>
+<li>Fvid2_BayerColorIndex()
+: <a class="el" href="csl__fvid2__data_types_8h.html#a8938f5c1b9a0655d7dbb4aabb11a6c16">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_BUF_FMT_FIELD
+: <a class="el" href="csl__fvid2__data_types_8h.html#afa226435f563ae5b91e94e8e0728a12c">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_BUF_FMT_FRAME
+: <a class="el" href="csl__fvid2__data_types_8h.html#aac021d82bbc20a8ce5ea9a88a2cd8dd0">csl_fvid2_dataTypes.h</a>
+</li>
+<li>Fvid2_BufferFormat
+: <a class="el" href="csl__fvid2__data_types_8h.html#a46ba9c505db41c885e5614571f680707">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_CCSF_BITS10_PACKED
+: <a class="el" href="csl__fvid2__data_types_8h.html#af3ac23834ffbf9aa575aa1aa1ba5f5dd">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_CCSF_BITS10_UNPACKED16
+: <a class="el" href="csl__fvid2__data_types_8h.html#aac7eaa1f4b68b84dca644e7b3a4a02a8">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_CCSF_BITS10_UNPACKED16_MSB_ALIGNED
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+: <a class="el" href="csl__fvid2__data_types_8h.html#af32c74c0915f13dab2d7e120ef005abc">csl_fvid2_dataTypes.h</a>
+</li>
+<li>Fvid2_FidPol
+: <a class="el" href="csl__fvid2__data_types_8h.html#a771282d54cb8fd1a47a32f2210786a3a">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_FIDPOL_INVERT
+: <a class="el" href="csl__fvid2__data_types_8h.html#acabe3506962c40666e10696224cfbfb0">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_FIDPOL_NORMAL
+: <a class="el" href="csl__fvid2__data_types_8h.html#ab5b7377e57466d1708b4f4ec8393b7bd">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_FLIP_TYPE_H
+: <a class="el" href="csl__fvid2__data_types_8h.html#aa12baa65ad86757aafa36c5f22a93de2">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_FLIP_TYPE_HV
+: <a class="el" href="csl__fvid2__data_types_8h.html#a346b3fc00efbc0e4d14e73e63aaea40d">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_FLIP_TYPE_NONE
+: <a class="el" href="csl__fvid2__data_types_8h.html#aab734c88ee2494bf6eb6b1e0c01c41d1">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_FLIP_TYPE_V
+: <a class="el" href="csl__fvid2__data_types_8h.html#acb0e70768a82732cb712c9010be02610">csl_fvid2_dataTypes.h</a>
+</li>
+<li>Fvid2_FlipType
+: <a class="el" href="csl__fvid2__data_types_8h.html#a936d3064b224ce1fb3e7204b044e1013">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_FRAME_STATUS_ABORTED
+: <a class="el" href="csl__fvid2__data_types_8h.html#a248e190fab40aca929969c432068a099a43d4d377646d7279138602a7aeac3f72">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_FRAME_STATUS_COMPLETED
+: <a class="el" href="csl__fvid2__data_types_8h.html#a248e190fab40aca929969c432068a099a696c6a4cbd00246b5c1e4370fa302055">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_FRAME_STATUS_CRC_ERROR
+: <a class="el" href="csl__fvid2__data_types_8h.html#a248e190fab40aca929969c432068a099a84c41401ba6a29d9ca60b93a48803202">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_FRAME_STATUS_ECC_CORRECTED
+: <a class="el" href="csl__fvid2__data_types_8h.html#a248e190fab40aca929969c432068a099a475443372b2fb2763923f7d58b5f467a">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_FRAME_STATUS_ECC_ERROR
+: <a class="el" href="csl__fvid2__data_types_8h.html#a248e190fab40aca929969c432068a099a38f88ca4ff3a06f88914c71a5c1b7c0e">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_FRAME_STATUS_ERROR
+: <a class="el" href="csl__fvid2__data_types_8h.html#a248e190fab40aca929969c432068a099ac9611a6508b8e02547b4706cc38ad89d">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_FRAME_STATUS_INIT
+: <a class="el" href="csl__fvid2__data_types_8h.html#a248e190fab40aca929969c432068a099adf9e647770fecfbd9ace849d2db8f988">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_FRAME_STATUS_MAX
+: <a class="el" href="csl__fvid2__data_types_8h.html#a248e190fab40aca929969c432068a099ae0e4d1baff68faaadda86f76db875869">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_FRAME_STATUS_OVERFLOW
+: <a class="el" href="csl__fvid2__data_types_8h.html#a248e190fab40aca929969c432068a099abebee14dd307042e25082acf1b1270f5">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_FRAME_STATUS_PENDING
+: <a class="el" href="csl__fvid2__data_types_8h.html#a248e190fab40aca929969c432068a099aeefebb0a00827e6d2362df182c6e0709">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_FRAME_STATUS_SUBMITTED
+: <a class="el" href="csl__fvid2__data_types_8h.html#a248e190fab40aca929969c432068a099afb0044f14c3f1d87d92611b1b13c3a02">csl_fvid2_dataTypes.h</a>
+</li>
+<li>Fvid2_FrameStatus
+: <a class="el" href="csl__fvid2__data_types_8h.html#a248e190fab40aca929969c432068a099">csl_fvid2_dataTypes.h</a>
+</li>
+<li>Fvid2_getDataFmtString()
+: <a class="el" href="csl__fvid2__data_types_8h.html#ac486d696661acd7c496e032ee598a9c4">csl_fvid2_dataTypes.h</a>
+</li>
+<li>Fvid2_getModeInfo()
+: <a class="el" href="csl__fvid2__data_types_8h.html#a0ff414941310bac0f142807d5ce4992d">csl_fvid2_dataTypes.h</a>
+</li>
+<li>Fvid2_getStandardString()
+: <a class="el" href="csl__fvid2__data_types_8h.html#a5bb999e03ac1bac7da6b62f004f17bf9">csl_fvid2_dataTypes.h</a>
+</li>
+<li>Fvid2_isDataFmtBayer()
+: <a class="el" href="csl__fvid2__data_types_8h.html#a7b92c32c5cd073fd09ca32a655065048">csl_fvid2_dataTypes.h</a>
+</li>
+<li>Fvid2_isDataFmtRgb()
+: <a class="el" href="csl__fvid2__data_types_8h.html#a7a17697bd4677e5c0e4611c91821c5b2">csl_fvid2_dataTypes.h</a>
+</li>
+<li>Fvid2_isDataFmtRgb16bit()
+: <a class="el" href="csl__fvid2__data_types_8h.html#adc25f711515d08d8cb9cb5752135f969">csl_fvid2_dataTypes.h</a>
+</li>
+<li>Fvid2_isDataFmtRgb24bit()
+: <a class="el" href="csl__fvid2__data_types_8h.html#a933b005f12a4845f842d978718560099">csl_fvid2_dataTypes.h</a>
+</li>
+<li>Fvid2_isDataFmtRgb32bit()
+: <a class="el" href="csl__fvid2__data_types_8h.html#a83e52e7870da61828fccff98d4985f77">csl_fvid2_dataTypes.h</a>
+</li>
+<li>Fvid2_isDataFmtRgb64bit()
+: <a class="el" href="csl__fvid2__data_types_8h.html#addaf6c10b34dbfbe5b9e892c4e08a90f">csl_fvid2_dataTypes.h</a>
+</li>
+<li>Fvid2_isDataFmtSemiPlanar()
+: <a class="el" href="csl__fvid2__data_types_8h.html#a233fa36d9cfcde59468c7ddc8a8990e2">csl_fvid2_dataTypes.h</a>
+</li>
+<li>Fvid2_isDataFmtYuv()
+: <a class="el" href="csl__fvid2__data_types_8h.html#abcb80b193d95790e23d51f7a04e232ed">csl_fvid2_dataTypes.h</a>
+</li>
+<li>Fvid2_isDataFmtYuv420()
+: <a class="el" href="csl__fvid2__data_types_8h.html#af103bb1d4a91a5112e2418d06ed9c6ad">csl_fvid2_dataTypes.h</a>
+</li>
+<li>Fvid2_isDataFmtYuv420Sp()
+: <a class="el" href="csl__fvid2__data_types_8h.html#a453391f7467c4aeec2968c29b77d5e99">csl_fvid2_dataTypes.h</a>
+</li>
+<li>Fvid2_isDataFmtYuv422()
+: <a class="el" href="csl__fvid2__data_types_8h.html#ab54967003a826f9becaf1fb346609658">csl_fvid2_dataTypes.h</a>
+</li>
+<li>Fvid2_isDataFmtYuv422I()
+: <a class="el" href="csl__fvid2__data_types_8h.html#ab5751442713ba8a70dbaa097be64a891">csl_fvid2_dataTypes.h</a>
+</li>
+<li>Fvid2_isDataFmtYuv422Sp()
+: <a class="el" href="csl__fvid2__data_types_8h.html#a8ac3f62f103515fa9ccc940448d4ebf5">csl_fvid2_dataTypes.h</a>
+</li>
+<li>Fvid2_isDataFmtYuv444()
+: <a class="el" href="csl__fvid2__data_types_8h.html#a906531b9be45f2bd528e1fac44b00340">csl_fvid2_dataTypes.h</a>
+</li>
+<li>Fvid2_isStandardVesa()
+: <a class="el" href="csl__fvid2__data_types_8h.html#a8996b9bd71f65f97abf2ee422611529b">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_MAX_FIELDS
+: <a class="el" href="csl__fvid2__data_types_8h.html#a6fc0d1953df344af3840c1fa516ec270">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_MAX_FRAME_PTR
+: <a class="el" href="csl__fvid2__data_types_8h.html#adcf85da7b48cf6db3cce2efb2d86c92f">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_MAX_PLANES
+: <a class="el" href="csl__fvid2__data_types_8h.html#aef0d63f7f96514278ebda30f1c0bec74">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_MAX_PLANES_PER_FIELD
+: <a class="el" href="csl__fvid2__data_types_8h.html#a19b6ef6e426b64e15bc08ce46c644aef">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_POL_HIGH
+: <a class="el" href="csl__fvid2__data_types_8h.html#a1ec7e5d8259b4f4d17b46f530c0d131c">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_POL_LOW
+: <a class="el" href="csl__fvid2__data_types_8h.html#a7039fcba297528e798b709348d086ae0">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_POL_MAX
+: <a class="el" href="csl__fvid2__data_types_8h.html#a6a962d56487d54dcae253875c5f5b507">csl_fvid2_dataTypes.h</a>
+</li>
+<li>Fvid2_Polarity
+: <a class="el" href="csl__fvid2__data_types_8h.html#a9e9754a80a4e33aebaf391204a570723">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_RGB_ADDR_IDX
+: <a class="el" href="csl__fvid2__data_types_8h.html#aa817e06beb7398bb897b0ca37fd65c89">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_RGB_FID2_ADDR_IDX
+: <a class="el" href="csl__fvid2__data_types_8h.html#a31e867f5964f35c3554a204beb07601e">csl_fvid2_dataTypes.h</a>
+</li>
+<li>Fvid2_ScanFormat
+: <a class="el" href="csl__fvid2__data_types_8h.html#af5dfad95adb11f1220c13a37564b706e">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_SF_INTERLACED
+: <a class="el" href="csl__fvid2__data_types_8h.html#ad10493ed6f290f7fa0675a265b2c07b2">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_SF_MAX
+: <a class="el" href="csl__fvid2__data_types_8h.html#a5cc4a5eb1a0fdd03b5fe97f14ba39965">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_SF_PROGRESSIVE
+: <a class="el" href="csl__fvid2__data_types_8h.html#ad0541a876e164776093a922da96e0439">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_SOK
+: <a class="el" href="csl__fvid2__data_types_8h.html#a8395476cbd9d01e0aaa219814515d5c9">csl_fvid2_dataTypes.h</a>
+</li>
+<li>Fvid2_Standard
+: <a class="el" href="csl__fvid2__data_types_8h.html#aaa2667d105d557f254c20b87534ed4b6">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_STD_1080I_50
+: <a class="el" href="csl__fvid2__data_types_8h.html#ad03201d7eaefc365e9669e563c8943b9">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_STD_1080I_60
+: <a class="el" href="csl__fvid2__data_types_8h.html#aa26f238860774149d2588be37d7bc59d">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_STD_1080P_24
+: <a class="el" href="csl__fvid2__data_types_8h.html#ae7f99f1670fd74f6f9980df3bb8d5e21">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_STD_1080P_30
+: <a class="el" href="csl__fvid2__data_types_8h.html#a677029e5d4746ab0ab19753710eaf8fc">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_STD_1080P_50
+: <a class="el" href="csl__fvid2__data_types_8h.html#aea1694ce11428345dfe3aa40830c45f9">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_STD_1080P_60
+: <a class="el" href="csl__fvid2__data_types_8h.html#a68e822d86ea54f7bc4b4cbf7f61e5245">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_STD_1360_768_60
+: <a class="el" href="csl__fvid2__data_types_8h.html#aa41941d7e409af4939202e9cb4630efb">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_STD_1366_768_60
+: <a class="el" href="csl__fvid2__data_types_8h.html#aeaa514ed3d728d5f625d9e0ad0eb5be8">csl_fvid2_dataTypes.h</a>
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+<li>FVID2_STD_1368_768_60
+: <a class="el" href="csl__fvid2__data_types_8h.html#a93b0af8925015d4614799ba16ad6b654">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_STD_1440_900_60
+: <a class="el" href="csl__fvid2__data_types_8h.html#a2b167ba856bcb092c2abf0af556e2da1">csl_fvid2_dataTypes.h</a>
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+<li>FVID2_STD_480I
+: <a class="el" href="csl__fvid2__data_types_8h.html#af725d5147e849a32f0b1eb27d9c769e6">csl_fvid2_dataTypes.h</a>
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+<li>FVID2_STD_480P
+: <a class="el" href="csl__fvid2__data_types_8h.html#abad8059c7e559059445a38172ef12fdc">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_STD_576I
+: <a class="el" href="csl__fvid2__data_types_8h.html#a7f961f37c4aa079e0ca408d1d421437a">csl_fvid2_dataTypes.h</a>
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+<li>FVID2_STD_576P
+: <a class="el" href="csl__fvid2__data_types_8h.html#a6d55a81370bd468d1fad62c7b34f35f9">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_STD_720P_50
+: <a class="el" href="csl__fvid2__data_types_8h.html#a9b394349cded10b8af057ff5940646eb">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_STD_720P_60
+: <a class="el" href="csl__fvid2__data_types_8h.html#a6bb35a8b1ceb84436db49019d7572df1">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_STD_AUTO_DETECT
+: <a class="el" href="csl__fvid2__data_types_8h.html#aaea4cb84fc06503d103416a5d7c064bf">csl_fvid2_dataTypes.h</a>
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+<li>FVID2_STD_CIF
+: <a class="el" href="csl__fvid2__data_types_8h.html#acd4ae0f475e71e394e924b8b6f213e52">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_STD_CUSTOM
+: <a class="el" href="csl__fvid2__data_types_8h.html#a3be5517c8a5b384f525120a6473b9aa8">csl_fvid2_dataTypes.h</a>
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+<li>FVID2_STD_D1
+: <a class="el" href="csl__fvid2__data_types_8h.html#a29d79e852429936a25f9282cf335d48c">csl_fvid2_dataTypes.h</a>
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+<li>FVID2_STD_HALF_D1
+: <a class="el" href="csl__fvid2__data_types_8h.html#a2b7bdf54fd82989b7c6e0461b945efdc">csl_fvid2_dataTypes.h</a>
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+<li>FVID2_STD_MUX_2CH_CIF
+: <a class="el" href="csl__fvid2__data_types_8h.html#af5a5f9c53ab6634cb288c00808129639">csl_fvid2_dataTypes.h</a>
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+<li>FVID2_STD_MUX_2CH_D1
+: <a class="el" href="csl__fvid2__data_types_8h.html#a0abdf3aefeccfe5a6e2bf8fc2f0b1356">csl_fvid2_dataTypes.h</a>
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+<li>FVID2_STD_MUX_2CH_HALF_D1
+: <a class="el" href="csl__fvid2__data_types_8h.html#ad757a9ccea31d5a94c0ec1c6322f9271">csl_fvid2_dataTypes.h</a>
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+<li>FVID2_STD_MUX_4CH_CIF
+: <a class="el" href="csl__fvid2__data_types_8h.html#a8d2347b9179f8bda62f4ca0ae337ed22">csl_fvid2_dataTypes.h</a>
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+<li>FVID2_STD_MUX_4CH_D1
+: <a class="el" href="csl__fvid2__data_types_8h.html#a1a68a709c1a760d4ee6f8c70b7a4f14b">csl_fvid2_dataTypes.h</a>
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+<li>FVID2_STD_MUX_4CH_HALF_D1
+: <a class="el" href="csl__fvid2__data_types_8h.html#a5afbbf47084865e341f0870ee30cc739">csl_fvid2_dataTypes.h</a>
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+<li>FVID2_STD_MUX_8CH_CIF
+: <a class="el" href="csl__fvid2__data_types_8h.html#a1d96d34832944c554b3b7adb6ebad4d9">csl_fvid2_dataTypes.h</a>
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+<li>FVID2_STD_MUX_8CH_HALF_D1
+: <a class="el" href="csl__fvid2__data_types_8h.html#a3829733b32609b9a5f9f6f0bbd6714e5">csl_fvid2_dataTypes.h</a>
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+<li>FVID2_STD_NTSC
+: <a class="el" href="csl__fvid2__data_types_8h.html#a508515b25947ede0cb5c03afc572f56d">csl_fvid2_dataTypes.h</a>
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+<li>FVID2_STD_PAL
+: <a class="el" href="csl__fvid2__data_types_8h.html#a7bd496bf85b4038f0fd0c841b741e968">csl_fvid2_dataTypes.h</a>
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+<li>FVID2_STD_SVGA_60
+: <a class="el" href="csl__fvid2__data_types_8h.html#ac326c1d1653379357aa624d639c811c7">csl_fvid2_dataTypes.h</a>
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+<li>FVID2_STD_SVGA_72
+: <a class="el" href="csl__fvid2__data_types_8h.html#a37351c4d4096383e2d5d72316af3f4f0">csl_fvid2_dataTypes.h</a>
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+<li>FVID2_STD_SVGA_75
+: <a class="el" href="csl__fvid2__data_types_8h.html#a36e85a9212920839f4cdea2f97774d00">csl_fvid2_dataTypes.h</a>
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+<li>FVID2_STD_SVGA_85
+: <a class="el" href="csl__fvid2__data_types_8h.html#abe1e836c388da56174b6fba2a98fec2d">csl_fvid2_dataTypes.h</a>
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+<li>FVID2_STD_SXGA_60
+: <a class="el" href="csl__fvid2__data_types_8h.html#a5f2b699f67df490f4922f0cf80e12a17">csl_fvid2_dataTypes.h</a>
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+<li>FVID2_STD_SXGA_75
+: <a class="el" href="csl__fvid2__data_types_8h.html#a3240f384b90e33105de53c735ac24ab8">csl_fvid2_dataTypes.h</a>
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+<li>FVID2_STD_SXGA_85
+: <a class="el" href="csl__fvid2__data_types_8h.html#a89f1f4cd2d6c4ba37f143a804e09e56d">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_STD_SXGAP_60
+: <a class="el" href="csl__fvid2__data_types_8h.html#ac57de538e6e7c03b518f40b576b78e54">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_STD_SXGAP_75
+: <a class="el" href="csl__fvid2__data_types_8h.html#ab8bb357f5290805dae7cb93e59207ca6">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_STD_UXGA_60
+: <a class="el" href="csl__fvid2__data_types_8h.html#a857b7d7d1443a364f5642fcd8f9fcad0">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_STD_VGA_60
+: <a class="el" href="csl__fvid2__data_types_8h.html#a539104247aec67a1e9a02e99c5dcf644">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_STD_VGA_72
+: <a class="el" href="csl__fvid2__data_types_8h.html#a071ae5ffed3b0dae002efb8bed4a6ff0">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_STD_VGA_75
+: <a class="el" href="csl__fvid2__data_types_8h.html#ab3dcebfeb086005fc35de1dd08922cf6">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_STD_VGA_85
+: <a class="el" href="csl__fvid2__data_types_8h.html#a331cf0ca858d87e3c005a3441a9bb723">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_STD_WSVGA_70
+: <a class="el" href="csl__fvid2__data_types_8h.html#ab49cbaf2b57c299a579e3c97eb72f37b">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_STD_WSXGAP_60
+: <a class="el" href="csl__fvid2__data_types_8h.html#a7a77706faae342689c3e8dd2f31a442a">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_STD_WVGA_60
+: <a class="el" href="csl__fvid2__data_types_8h.html#ac23e7e176ae9d5ac95f5a89abce32520">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_STD_WXGA_30
+: <a class="el" href="csl__fvid2__data_types_8h.html#a576daaef9c5b1c823b3107c9bb96d114">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_STD_WXGA_5x3_30
+: <a class="el" href="csl__fvid2__data_types_8h.html#aaab0c4817ec5e9f10f0c13d5375e1d30">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_STD_WXGA_5x3_60
+: <a class="el" href="csl__fvid2__data_types_8h.html#ad69ca1aed51329f28c87873b2544dd0e">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_STD_WXGA_5x3_75
+: <a class="el" href="csl__fvid2__data_types_8h.html#a42448ed6ed591d189584a9d6751c2edf">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_STD_WXGA_60
+: <a class="el" href="csl__fvid2__data_types_8h.html#a014e933fc51a2bd62139614d022c9b26">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_STD_WXGA_75
+: <a class="el" href="csl__fvid2__data_types_8h.html#a16436c69aafd74ca687088aaae15ba76">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_STD_WXGA_85
+: <a class="el" href="csl__fvid2__data_types_8h.html#af3565ee49136c5a00d8c07f68ebd453e">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_STD_XGA_60
+: <a class="el" href="csl__fvid2__data_types_8h.html#a2a3be1bf860b622d3561bb1b795fc414">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_STD_XGA_70
+: <a class="el" href="csl__fvid2__data_types_8h.html#a351fd686457f2bb276ffc6f5064cbd9e">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_STD_XGA_75
+: <a class="el" href="csl__fvid2__data_types_8h.html#aae15675f7a5d749ee8acfa542e05d8a9">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_STD_XGA_85
+: <a class="el" href="csl__fvid2__data_types_8h.html#a351e7a94e0446f709932fd8505ca8402">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_STD_XGA_DSS_TDM_60
+: <a class="el" href="csl__fvid2__data_types_8h.html#ae303cf581ad8069ed5bd6862003fdc83">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_TIMEOUT_FOREVER
+: <a class="el" href="csl__fvid2__data_types_8h.html#ac39a381aee86801c727735f635719cef">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_TIMEOUT_NONE
+: <a class="el" href="csl__fvid2__data_types_8h.html#a88e886eb47cb269040fb5bc7fda3f82c">csl_fvid2_dataTypes.h</a>
+</li>
+<li>Fvid2_VideoIfMode
+: <a class="el" href="csl__fvid2__data_types_8h.html#a4e1d4b630095a3e5f9d560b839603a8e">csl_fvid2_dataTypes.h</a>
+</li>
+<li>Fvid2_VideoIfWidth
+: <a class="el" href="csl__fvid2__data_types_8h.html#a3644341e8e51f60794fb15f219f0a5f7">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_VIFM_MAX
+: <a class="el" href="csl__fvid2__data_types_8h.html#a4e1d4b630095a3e5f9d560b839603a8ea06e8f99dd0b137efcc6ca8e2e2f15527">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_VIFM_MCH_LINE_MUX_ES
+: <a class="el" href="csl__fvid2__data_types_8h.html#a4e1d4b630095a3e5f9d560b839603a8ea7e22126a15add08aeabce4216492c88b">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_VIFM_MCH_LINE_MUX_SPLIT_LINE_ES
+: <a class="el" href="csl__fvid2__data_types_8h.html#a4e1d4b630095a3e5f9d560b839603a8eac7aceedd75323567a399f68742d54ccb">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_VIFM_MCH_PIXEL_MUX_ES
+: <a class="el" href="csl__fvid2__data_types_8h.html#a4e1d4b630095a3e5f9d560b839603a8ea07b6e18e02112c367d6bd3b380d2d9d3">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_VIFM_SCH_CPI
+: <a class="el" href="csl__fvid2__data_types_8h.html#a4e1d4b630095a3e5f9d560b839603a8ea03c1d8ab4e4325886e9c8553f0c6708f">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_VIFM_SCH_CSI2
+: <a class="el" href="csl__fvid2__data_types_8h.html#a4e1d4b630095a3e5f9d560b839603a8ea0caef0a1234afe67eed22370729d04f8">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_VIFM_SCH_DS_AVID_VBLK
+: <a class="el" href="csl__fvid2__data_types_8h.html#a4e1d4b630095a3e5f9d560b839603a8ea2fa8c574decaca5d94b93a6c8aa2ae64">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_VIFM_SCH_DS_AVID_VSYNC
+: <a class="el" href="csl__fvid2__data_types_8h.html#a4e1d4b630095a3e5f9d560b839603a8ea901482ffa323be1fb48302f7404930a6">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_VIFM_SCH_DS_HSYNC_VBLK
+: <a class="el" href="csl__fvid2__data_types_8h.html#a4e1d4b630095a3e5f9d560b839603a8ea7ffc6821187a28919e2ee5f8723199b1">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_VIFM_SCH_DS_HSYNC_VSYNC
+: <a class="el" href="csl__fvid2__data_types_8h.html#a4e1d4b630095a3e5f9d560b839603a8ea41dea0d5f63dd2ea51de8030460f6527">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_VIFM_SCH_ES
+: <a class="el" href="csl__fvid2__data_types_8h.html#a4e1d4b630095a3e5f9d560b839603a8ea0c1ebff799492bc87e0947ea5b4af1e6">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_VIFM_SCH_LVDS
+: <a class="el" href="csl__fvid2__data_types_8h.html#a4e1d4b630095a3e5f9d560b839603a8ea83e693e66bda0561fb9c4cc81733fa87">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_VIFW_10BIT
+: <a class="el" href="csl__fvid2__data_types_8h.html#ac3a717fe05ad4965118af833cf59e344">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_VIFW_12BIT
+: <a class="el" href="csl__fvid2__data_types_8h.html#aa4f84d19ce06a5392a81a6f377eca451">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_VIFW_14BIT
+: <a class="el" href="csl__fvid2__data_types_8h.html#a231633928ad65ad5c614fd4c99e02f63">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_VIFW_16BIT
+: <a class="el" href="csl__fvid2__data_types_8h.html#a1e9c51d0e52003c568876305d8b5ac4a">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_VIFW_18BIT
+: <a class="el" href="csl__fvid2__data_types_8h.html#a5f82958aa532079ce0d121b6abfa6290">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_VIFW_1LANES
+: <a class="el" href="csl__fvid2__data_types_8h.html#ac0f2644123a9cfad25d5d1394cd83b07">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_VIFW_20BIT
+: <a class="el" href="csl__fvid2__data_types_8h.html#a737fba3bfb51d5a0db8d273dc62c6f55">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_VIFW_24BIT
+: <a class="el" href="csl__fvid2__data_types_8h.html#af0ca9fef4970890bdb6c3294e3488dd2">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_VIFW_2LANES
+: <a class="el" href="csl__fvid2__data_types_8h.html#a0bf298ec713b45e4412921b840700b21">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_VIFW_30BIT
+: <a class="el" href="csl__fvid2__data_types_8h.html#ab662f4e73161ba1c2b0def811521f144">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_VIFW_36BIT
+: <a class="el" href="csl__fvid2__data_types_8h.html#a3bbc392f936b3fc101d207b191832032">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_VIFW_3LANES
+: <a class="el" href="csl__fvid2__data_types_8h.html#ab6c39f963bb8d0873cd040f80df74528">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_VIFW_4LANES
+: <a class="el" href="csl__fvid2__data_types_8h.html#a855c0790a50e48407a58b4e6682005d8">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_VIFW_8BIT
+: <a class="el" href="csl__fvid2__data_types_8h.html#a2dcc786e9b4d47f2408761a012f5760a">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_VIFW_MAX
+: <a class="el" href="csl__fvid2__data_types_8h.html#a3fc89d365c319b7999dfab0a24269105">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_WNON_RECOMMENDED_PARAMS
+: <a class="el" href="csl__fvid2__data_types_8h.html#aedcb86d5a2e3ec73847eca004e037535">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_YUV_INT_ADDR_IDX
+: <a class="el" href="csl__fvid2__data_types_8h.html#a964627052348693970b6b8078a622a11">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_YUV_INT_FID2_ADDR_IDX
+: <a class="el" href="csl__fvid2__data_types_8h.html#a909f592eabc1bf70b9a3dab15e468713">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_YUV_PL_CB_ADDR_IDX
+: <a class="el" href="csl__fvid2__data_types_8h.html#ada7ebea730d1889e88c13b17c5b2d053">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_YUV_PL_CB_FID2_ADDR_IDX
+: <a class="el" href="csl__fvid2__data_types_8h.html#a8af505377d5f361ec078e9181336d42e">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_YUV_PL_CR_ADDR_IDX
+: <a class="el" href="csl__fvid2__data_types_8h.html#a0bbd3a8627de6776fc92458a8b3c6a4a">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_YUV_PL_CR_FID2_ADDR_IDX
+: <a class="el" href="csl__fvid2__data_types_8h.html#a74bcea671e6e8833edbd978fd0dd27be">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_YUV_PL_Y_ADDR_IDX
+: <a class="el" href="csl__fvid2__data_types_8h.html#a9ff732b464eedfe4640b4169970765c8">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_YUV_PL_Y_FID2_ADDR_IDX
+: <a class="el" href="csl__fvid2__data_types_8h.html#a16d75a000e95e205d6ef10eb5a6a7005">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_YUV_SP_CBCR_ADDR_IDX
+: <a class="el" href="csl__fvid2__data_types_8h.html#a12c8a4aa7624a1d6e007cb29331f1119">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_YUV_SP_CBCR_FID2_ADDR_IDX
+: <a class="el" href="csl__fvid2__data_types_8h.html#a32797001f230161fdd9b1a26755061ee">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_YUV_SP_Y_ADDR_IDX
+: <a class="el" href="csl__fvid2__data_types_8h.html#a9a79f5ef34a964258855d87b738cc19f">csl_fvid2_dataTypes.h</a>
+</li>
+<li>FVID2_YUV_SP_Y_FID2_ADDR_IDX
+: <a class="el" href="csl__fvid2__data_types_8h.html#acebcf1dfbbc29d3e139e95b4f4c5ed6d">csl_fvid2_dataTypes.h</a>
+</li>
+<li>Fvid2CropConfig_init()
+: <a class="el" href="csl__fvid2__data_types_8h.html#a7f76750350b75947c9bfa26b76798c92">csl_fvid2_dataTypes.h</a>
+</li>
+<li>Fvid2Format_init()
+: <a class="el" href="csl__fvid2__data_types_8h.html#a3c57266e7a813692eee72e3624f22fdf">csl_fvid2_dataTypes.h</a>
+</li>
+<li>Fvid2Frame_init()
+: <a class="el" href="csl__fvid2__data_types_8h.html#a519f857d75a4b946c99e0a8cfa0da148">csl_fvid2_dataTypes.h</a>
+</li>
+<li>Fvid2FrameList_init()
+: <a class="el" href="csl__fvid2__data_types_8h.html#a835800489d2c42aed71f30941b9f2fd2">csl_fvid2_dataTypes.h</a>
+</li>
+<li>Fvid2ModeInfo_init()
+: <a class="el" href="csl__fvid2__data_types_8h.html#a7fd1ec90c192cdc87f2e51819ad6b6fa">csl_fvid2_dataTypes.h</a>
+</li>
+<li>Fvid2PosConfig_init()
+: <a class="el" href="csl__fvid2__data_types_8h.html#acde86e2766599bb25a7126f364e78c4e">csl_fvid2_dataTypes.h</a>
+</li>
+<li>Fvid2SubFrameInfo_init()
+: <a class="el" href="csl__fvid2__data_types_8h.html#a699a19f64a958b0e023264d2626df860">csl_fvid2_dataTypes.h</a>
+</li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/globals_func.html b/packages/ti/drv/dss/docs/doxygen/html/globals_func.html
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+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Globals</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li class="current"><a href="files.html"><span>Files</span></a></li>
+ </ul>
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+ <div id="navrow2" class="tabs2">
+ <ul class="tablist">
+ <li><a href="files.html"><span>File List</span></a></li>
+ <li class="current"><a href="globals.html"><span>Globals</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow3" class="tabs2">
+ <ul class="tablist">
+ <li><a href="globals.html"><span>All</span></a></li>
+ <li class="current"><a href="globals_func.html"><span>Functions</span></a></li>
+ <li><a href="globals_type.html"><span>Typedefs</span></a></li>
+ <li><a href="globals_enum.html"><span>Enumerations</span></a></li>
+ <li><a href="globals_eval.html"><span>Enumerator</span></a></li>
+ <li><a href="globals_defs.html"><span>Macros</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow4" class="tabs3">
+ <ul class="tablist">
+ <li><a href="#index_c"><span>c</span></a></li>
+ <li><a href="#index_d"><span>d</span></a></li>
+ <li class="current"><a href="#index_f"><span>f</span></a></li>
+ </ul>
+ </div>
+</div><!-- top -->
+<div class="contents">
+ 
+
+<h3><a class="anchor" id="index_c"></a>- c -</h3><ul>
+<li>CSL_dssCbaCfgInit()
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gafa9009a2a94ae2222dfaaa166de1f33d">csl_dssCommon.h</a>
+</li>
+<li>CSL_dssClearDispcIntr()
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga2f59e10e9d38932af384543d274dc90c">csl_dssCommon.h</a>
+</li>
+<li>CSL_dssClearPipeIntr()
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1c2b89748e481bf4651cf4b87805177d">csl_dssCommon.h</a>
+</li>
+<li>CSL_dssClearVpIntr()
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga086ca7d14c9f2a75305035c512972c18">csl_dssCommon.h</a>
+</li>
+<li>CSL_dssConnectVpToDpi()
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1c215888b011a5cca5880679ea560f74">csl_dssCommon.h</a>
+</li>
+<li>CSL_dssCscCoeffInit()
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga09a24eab792b00629e4b510d36a326a8">csl_dssTop.h</a>
+</li>
+<li>CSL_dssEnableDispcIntr()
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga78ae8cafecdf61459530ae0ecaee1312">csl_dssCommon.h</a>
+</li>
+<li>CSL_dssEnablePipeIntr()
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1d1f5ed599418de87535e92ff113dbae">csl_dssCommon.h</a>
+</li>
+<li>CSL_dssEnableVpIntr()
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gabc7928512f14f647d32d899a9850b4ad">csl_dssCommon.h</a>
+</li>
+<li>CSL_dssGetDispcIntrStatus()
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga196052d031e6e46bc99f4631218d2da7">csl_dssCommon.h</a>
+</li>
+<li>CSL_dssGetPipeIntrStatus()
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gab25aea830bb6567a67be6018fbce58e2">csl_dssCommon.h</a>
+</li>
+<li>CSL_dssGetVpIntrStatus()
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga7202424e4a3404aaf894e294be0a1f7d">csl_dssCommon.h</a>
+</li>
+<li>CSL_dssGlobalMFlagCfgInit()
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga67eb3b87f230f3d3598ff1ea3c8ccbbe">csl_dssCommon.h</a>
+</li>
+<li>CSL_dssGlobalVpEnable()
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gad3490bc78c9441400a4a77c933006f6c">csl_dssCommon.h</a>
+</li>
+<li>CSL_dssGlobalVpGoBitEnable()
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga6c62a23a768c0ce357db64365ebdc0b0">csl_dssCommon.h</a>
+</li>
+<li>CSL_dssModuleReset()
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga567b2f823b70e843ceb9c4ca8c501cae">csl_dssCommon.h</a>
+</li>
+<li>CSL_dssOverlayCfgInit()
+: <a class="el" href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#ga5f9f1191f5d62fa0747616ae87e3cc65">csl_dssOverlay.h</a>
+</li>
+<li>CSL_dssOverlayColorBarEnable()
+: <a class="el" href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#gad36724322f426d4022c944b5fc53f3fd">csl_dssOverlay.h</a>
+</li>
+<li>CSL_dssOverlayGetEnabledPipeLayerNum()
+: <a class="el" href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#gae88aaba46e12dfb2f72c93691ea14c99">csl_dssOverlay.h</a>
+</li>
+<li>CSL_dssOverlayLayerCfgInit()
+: <a class="el" href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#gae7481e9db942be0537425939b6387a22">csl_dssOverlay.h</a>
+</li>
+<li>CSL_dssOverlayPipePosCfgInit()
+: <a class="el" href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#ga1c8500dcdd91d052cfc9c01d4bed6e30">csl_dssOverlay.h</a>
+</li>
+<li>CSL_dssOverlaySetConfig()
+: <a class="el" href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#ga03a77e67fa911acc5e905faafe06a7cc">csl_dssOverlay.h</a>
+</li>
+<li>CSL_dssOverlaySetLayerConfig()
+: <a class="el" href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#ga0854ef7eebe8ec3dabd739cda8a0a87b">csl_dssOverlay.h</a>
+</li>
+<li>CSL_dssOverlaySetPipePosConfig()
+: <a class="el" href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#ga04705e269d2be5aa01508e3f5dafdf7c">csl_dssOverlay.h</a>
+</li>
+<li>CSL_dssSafetyChkCfgInit()
+: <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga0eba2c12170b846778eecb3eeb5a9a46">csl_dssTop.h</a>
+</li>
+<li>CSL_dssSetCbaConfig()
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1ce4591b123f52bf6e6cc00a485fcd38">csl_dssCommon.h</a>
+</li>
+<li>CSL_dssSetGlobalMflagConfig()
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga51649681f3f478ab1c44d97aa3ed8323">csl_dssCommon.h</a>
+</li>
+<li>CSL_dssVidPipeAlphaCfgInit()
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#ga8a3d5286ff2be3f2056f554f1d5c92d7">csl_dssVideoPipe.h</a>
+</li>
+<li>CSL_dssVidPipeCfgInit()
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gae2ea4d9e0e2d9662d1bda20ec77567dc">csl_dssVideoPipe.h</a>
+</li>
+<li>CSL_dssVidPipeCropEnable()
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gaf4dc4e4142893b328dd75906147dde8f">csl_dssVideoPipe.h</a>
+</li>
+<li>CSL_dssVidPipeDmaCfgInit()
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#ga53cc07dd9deeeec69be494c89fd12812">csl_dssVideoPipe.h</a>
+</li>
+<li>CSL_dssVidPipeEnable()
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gac037fe8b1ea6f506c6b0d00fd4a84491">csl_dssVideoPipe.h</a>
+</li>
+<li>CSL_dssVidPipeEnableTransparency()
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#ga0b9cbe7775795bca5b9a8904ec9fc4b1">csl_dssVideoPipe.h</a>
+</li>
+<li>CSL_dssVidPipeGetSafetySign()
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gaf51512cbab443cebde3013bc6bf212aa">csl_dssVideoPipe.h</a>
+</li>
+<li>CSL_dssVidPipeLumaCfgInit()
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gaeec644be0c0f1f62da19eca5c1e9b877">csl_dssVideoPipe.h</a>
+</li>
+<li>CSL_dssVidPipeMFlagCfgInit()
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#ga5d27f327524e3016a74de471e5eb38a1">csl_dssVideoPipe.h</a>
+</li>
+<li>CSL_dssVidPipeSetAlphaConfig()
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#ga3646182313235e92362cd843fdc6c2e6">csl_dssVideoPipe.h</a>
+</li>
+<li>CSL_dssVidPipeSetBuffAddr()
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#ga11ed49990e9b63ecbf167cff5f6a9755">csl_dssVideoPipe.h</a>
+</li>
+<li>CSL_dssVidPipeSetConfig()
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#ga6d983ffe721b5a1b602bfa53995f1c76">csl_dssVideoPipe.h</a>
+</li>
+<li>CSL_dssVidPipeSetCSCCoeff()
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gacebfcb0b4ae57fa7a1ce3c73f6b552e8">csl_dssVideoPipe.h</a>
+</li>
+<li>CSL_dssVidPipeSetDmaConfig()
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gaf3bd47c49aa8edd65bfd202779cdd0a2">csl_dssVideoPipe.h</a>
+</li>
+<li>CSL_dssVidPipeSetMflagConfig()
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#ga3095d9a0f35cd85fba7c2be6b14d798d">csl_dssVideoPipe.h</a>
+</li>
+<li>CSL_dssVidPipeSetSafetyChkConfig()
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gae5dc5282a40648fd2f69165e7a373265">csl_dssVideoPipe.h</a>
+</li>
+<li>CSL_dssVidPipeSetSafetyReferenceSign()
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#ga37238e9b68bd88742eb54cca7c3cd7a8">csl_dssVideoPipe.h</a>
+</li>
+<li>CSL_dssVidPipeSetSafetySignSeedVal()
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#ga70f77613b5b22a937388f5b072a7f74d">csl_dssVideoPipe.h</a>
+</li>
+<li>CSL_dssVidPipeVC1CfgInit()
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gaf11746b1003b15855996b817cfe3d38a">csl_dssVideoPipe.h</a>
+</li>
+<li>CSL_dssVpEnable()
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga9c61092eddfa87bcba87cc116fb8bd1d">csl_dssVideoPort.h</a>
+</li>
+<li>CSL_dssVpEnableTvGamma()
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga253c3416c174352edcda17c4ca271013">csl_dssVideoPort.h</a>
+</li>
+<li>CSL_dssVpGammaCfgInit()
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga709fdcc02c1f82d9a3b595ad67b9f086">csl_dssVideoPort.h</a>
+</li>
+<li>CSL_dssVpGetLcdLineNum()
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga447444c64439d7b1210a9b696dd8a673">csl_dssVideoPort.h</a>
+</li>
+<li>CSL_dssVpGetSafetySign()
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga7f7b411493687d0d758ff8b047a23712">csl_dssVideoPort.h</a>
+</li>
+<li>CSL_dssVpLcdAdvSignalCfgInit()
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga50f5efd31f31736019ee265e3078d4ef">csl_dssVideoPort.h</a>
+</li>
+<li>CSL_dssVpLcdBlankTimingCfgInit()
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gadd1a815002453481cce4f9dbf8da864a">csl_dssVideoPort.h</a>
+</li>
+<li>CSL_dssVpLcdOpTimingCfgInit()
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga2be9daed03e91c1706a4075be86a7054">csl_dssVideoPort.h</a>
+</li>
+<li>CSL_dssVpLcdSignalPolarityCfgInit()
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga158b9aed148e3a14e1bff1cb8613bc67">csl_dssVideoPort.h</a>
+</li>
+<li>CSL_dssVpLcdTdmCfgInit()
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gaf276b6af542ab92fa03bf0af6d1af1cb">csl_dssVideoPort.h</a>
+</li>
+<li>CSL_dssVpSetCSCCoeff()
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga7d36af9cdba47ad2622758fd632980ce">csl_dssVideoPort.h</a>
+</li>
+<li>CSL_dssVpSetGoBit()
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga0ba989884315a28b21a62a722574865d">csl_dssVideoPort.h</a>
+</li>
+<li>CSL_dssVpSetLcdAdvSignalConfig()
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga45dfca83a394f21328886b7ad7d89056">csl_dssVideoPort.h</a>
+</li>
+<li>CSL_dssVpSetLcdBlankTiming()
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga5f52bab6e5e9242d6f77faf995a4de6e">csl_dssVideoPort.h</a>
+</li>
+<li>CSL_dssVpSetLcdLineNum()
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga1a4f05443f8ba7bffea84d63b43788ab">csl_dssVideoPort.h</a>
+</li>
+<li>CSL_dssVpSetLcdOpTimingConfig()
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga0225f72557517955d94f1a6ce815ed14">csl_dssVideoPort.h</a>
+</li>
+<li>CSL_dssVpSetLcdSignalPolarityConfig()
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga75453549b6c9c05da750b55cdb2a8ad3">csl_dssVideoPort.h</a>
+</li>
+<li>CSL_dssVpSetLcdTdmConfig()
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga48c44cb30d94ee22ddd885998830d852">csl_dssVideoPort.h</a>
+</li>
+<li>CSL_dssVpSetSafetyChkConfig()
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gad2853dae9324aa61cbb332d14b308da6">csl_dssVideoPort.h</a>
+</li>
+<li>CSL_dssVpSetSafetyReferenceSign()
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga20bfb7e29029c7256d6766b9b05f5f23">csl_dssVideoPort.h</a>
+</li>
+<li>CSL_dssVpSetSafetySignSeedVal()
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga1bc9995f9958912a188ae2a98351aec5">csl_dssVideoPort.h</a>
+</li>
+<li>CSL_dssVpStallModeEnable()
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga08a68b5de9d2c6646b0654ccad3b9600">csl_dssVideoPort.h</a>
+</li>
+</ul>
+
+
+<h3><a class="anchor" id="index_d"></a>- d -</h3><ul>
+<li>Dss_dctrlAdvVpParamsInit()
+: <a class="el" href="dss__dctrl_8h.html#a8ef2fd5c8a1f3760dc6bd0d3f41cf782">dss_dctrl.h</a>
+</li>
+<li>Dss_dctrlGlobalDssParamsInit()
+: <a class="el" href="dss__dctrl_8h.html#a9245be86f5b0aa58fd825ddac59b15de">dss_dctrl.h</a>
+</li>
+<li>Dss_dctrlLcdBlankTimingParamsInit()
+: <a class="el" href="dss__dctrl_8h.html#a1bee4f99058e9860ea9e0d8c46713d17">dss_dctrl.h</a>
+</li>
+<li>Dss_dctrlOldiParamsInit()
+: <a class="el" href="dss__soc_8h.html#a6b12a5aecc6d9248f665d838abbad924">dss_soc.h</a>
+</li>
+<li>Dss_dctrlOverlayLayerParamsInit()
+: <a class="el" href="dss__dctrl_8h.html#a5a26a0b5b1059cb2dc79b0f7ec932cb6">dss_dctrl.h</a>
+</li>
+<li>Dss_dctrlOverlayParamsInit()
+: <a class="el" href="dss__dctrl_8h.html#aeb3a05c6b9e915a29bfa94784b427f75">dss_dctrl.h</a>
+</li>
+<li>Dss_dctrlPathInfoInit()
+: <a class="el" href="dss__dctrl_8h.html#a123a4e064a3dd6ae0de052f3668bcc82">dss_dctrl.h</a>
+</li>
+<li>Dss_dctrlRegionSafetyChkCfgInit()
+: <a class="el" href="dss__dctrl_8h.html#a128f0b2a1da8e24d1e87993efc59a049">dss_dctrl.h</a>
+</li>
+<li>Dss_dctrlSyncLostCbParamsInit()
+: <a class="el" href="dss__dctrl_8h.html#aa6b7e9e12da3c697e83d78d8909bfdb9">dss_dctrl.h</a>
+</li>
+<li>Dss_dctrlVpErrorStatsInit()
+: <a class="el" href="dss__dctrl_8h.html#ab7d6c323f77101a8d6f6ec0b36fcd092">dss_dctrl.h</a>
+</li>
+<li>Dss_dctrlVpParamsInit()
+: <a class="el" href="dss__dctrl_8h.html#aff73397092899b064dc00d8a813286a4">dss_dctrl.h</a>
+</li>
+<li>Dss_dctrlVpSafetyChkParamsInit()
+: <a class="el" href="dss__dctrl_8h.html#a3434c36ddde97b9077bb2b055cf0a4b0">dss_dctrl.h</a>
+</li>
+<li>Dss_deInit()
+: <a class="el" href="group___d_s_s.html#ga8da153ec94fd77b1238623030aedd76e">dss.h</a>
+</li>
+<li>Dss_dispBufPrgmCbParamsInit()
+: <a class="el" href="dss__disp_8h.html#a5d7c65146501cb5e2e4bfeee924afe1c">dss_disp.h</a>
+</li>
+<li>Dss_dispCreateParamsInit()
+: <a class="el" href="dss__disp_8h.html#a0b1e08d5de369b9d9bfeaf4ab7841884">dss_disp.h</a>
+</li>
+<li>Dss_dispIsVidInst()
+: <a class="el" href="dss__soc_8h.html#ac5552efbddfba904ce91dbcd5d0bd455">dss_soc.h</a>
+</li>
+<li>Dss_dispIsVidLInst()
+: <a class="el" href="dss__soc_8h.html#afe01ba05886b4fec75e6bc8414cf2582">dss_soc.h</a>
+</li>
+<li>Dss_dispParamsInit()
+: <a class="el" href="dss__disp_8h.html#ade1761a8d085738b03f4a2d3a4af24b3">dss_disp.h</a>
+</li>
+<li>Dss_dispPipeMflagParamsInit()
+: <a class="el" href="dss__disp_8h.html#a870942fd13c4ea685c1e03b4fe51da4c">dss_disp.h</a>
+</li>
+<li>Dss_dispPipePrgmCbParamsInit()
+: <a class="el" href="dss__disp_8h.html#a6c10a27c661e431f53014ed39b8335ec">dss_disp.h</a>
+</li>
+<li>Dss_dispPipeSafetyChkParamsInit()
+: <a class="el" href="dss__disp_8h.html#aa658322ec9e4dff9106f95f92439aa16">dss_disp.h</a>
+</li>
+<li>Dss_dispRtParamsInit()
+: <a class="el" href="dss__disp_8h.html#ae1a443826f5f5c55bb40417fcb689bcd">dss_disp.h</a>
+</li>
+<li>Dss_dispUnderFlowCbParamsInit()
+: <a class="el" href="dss__disp_8h.html#a076a2c0095da75002988e147c8f9991c">dss_disp.h</a>
+</li>
+<li>Dss_frameRtParamsInit()
+: <a class="el" href="dss__disp_8h.html#a20946243c0b2d8b3c5b317098abfba69">dss_disp.h</a>
+</li>
+<li>Dss_init()
+: <a class="el" href="group___d_s_s.html#ga9a7600eb912fe78c81a4e5fd88b495f6">dss.h</a>
+</li>
+<li>Dss_initParamsInit()
+: <a class="el" href="group___d_s_s.html#ga148ec5eeed6ef017fddce29adee32e90">dss.h</a>
+</li>
+<li>Dss_irqParamsInit()
+: <a class="el" href="dss__soc_8h.html#ae9111504fb718b4ac86e9a13ebf0b1d8">dss_soc.h</a>
+</li>
+<li>Dss_rmInfoInit()
+: <a class="el" href="dss__soc_8h.html#a24089c231dd46a8856c109008a2ac5b4">dss_soc.h</a>
+</li>
+<li>Dss_scRtParamsInit()
+: <a class="el" href="dss__disp_8h.html#a9f3129c4857d08aec6387867cc2e778c">dss_disp.h</a>
+</li>
+<li>Dss_socParamsInit()
+: <a class="el" href="dss__soc_8h.html#ab0090cdbb416c7e5ebe089d50914b70a">dss_soc.h</a>
+</li>
+</ul>
+
+
+<h3><a class="anchor" id="index_f"></a>- f -</h3><ul>
+<li>Fvid2_BayerColorIndex()
+: <a class="el" href="csl__fvid2__data_types_8h.html#a8938f5c1b9a0655d7dbb4aabb11a6c16">csl_fvid2_dataTypes.h</a>
+</li>
+<li>Fvid2_getDataFmtString()
+: <a class="el" href="csl__fvid2__data_types_8h.html#ac486d696661acd7c496e032ee598a9c4">csl_fvid2_dataTypes.h</a>
+</li>
+<li>Fvid2_getModeInfo()
+: <a class="el" href="csl__fvid2__data_types_8h.html#a0ff414941310bac0f142807d5ce4992d">csl_fvid2_dataTypes.h</a>
+</li>
+<li>Fvid2_getStandardString()
+: <a class="el" href="csl__fvid2__data_types_8h.html#a5bb999e03ac1bac7da6b62f004f17bf9">csl_fvid2_dataTypes.h</a>
+</li>
+<li>Fvid2_isDataFmtBayer()
+: <a class="el" href="csl__fvid2__data_types_8h.html#a7b92c32c5cd073fd09ca32a655065048">csl_fvid2_dataTypes.h</a>
+</li>
+<li>Fvid2_isDataFmtRgb()
+: <a class="el" href="csl__fvid2__data_types_8h.html#a7a17697bd4677e5c0e4611c91821c5b2">csl_fvid2_dataTypes.h</a>
+</li>
+<li>Fvid2_isDataFmtRgb16bit()
+: <a class="el" href="csl__fvid2__data_types_8h.html#adc25f711515d08d8cb9cb5752135f969">csl_fvid2_dataTypes.h</a>
+</li>
+<li>Fvid2_isDataFmtRgb24bit()
+: <a class="el" href="csl__fvid2__data_types_8h.html#a933b005f12a4845f842d978718560099">csl_fvid2_dataTypes.h</a>
+</li>
+<li>Fvid2_isDataFmtRgb32bit()
+: <a class="el" href="csl__fvid2__data_types_8h.html#a83e52e7870da61828fccff98d4985f77">csl_fvid2_dataTypes.h</a>
+</li>
+<li>Fvid2_isDataFmtRgb64bit()
+: <a class="el" href="csl__fvid2__data_types_8h.html#addaf6c10b34dbfbe5b9e892c4e08a90f">csl_fvid2_dataTypes.h</a>
+</li>
+<li>Fvid2_isDataFmtSemiPlanar()
+: <a class="el" href="csl__fvid2__data_types_8h.html#a233fa36d9cfcde59468c7ddc8a8990e2">csl_fvid2_dataTypes.h</a>
+</li>
+<li>Fvid2_isDataFmtYuv()
+: <a class="el" href="csl__fvid2__data_types_8h.html#abcb80b193d95790e23d51f7a04e232ed">csl_fvid2_dataTypes.h</a>
+</li>
+<li>Fvid2_isDataFmtYuv420()
+: <a class="el" href="csl__fvid2__data_types_8h.html#af103bb1d4a91a5112e2418d06ed9c6ad">csl_fvid2_dataTypes.h</a>
+</li>
+<li>Fvid2_isDataFmtYuv420Sp()
+: <a class="el" href="csl__fvid2__data_types_8h.html#a453391f7467c4aeec2968c29b77d5e99">csl_fvid2_dataTypes.h</a>
+</li>
+<li>Fvid2_isDataFmtYuv422()
+: <a class="el" href="csl__fvid2__data_types_8h.html#ab54967003a826f9becaf1fb346609658">csl_fvid2_dataTypes.h</a>
+</li>
+<li>Fvid2_isDataFmtYuv422I()
+: <a class="el" href="csl__fvid2__data_types_8h.html#ab5751442713ba8a70dbaa097be64a891">csl_fvid2_dataTypes.h</a>
+</li>
+<li>Fvid2_isDataFmtYuv422Sp()
+: <a class="el" href="csl__fvid2__data_types_8h.html#a8ac3f62f103515fa9ccc940448d4ebf5">csl_fvid2_dataTypes.h</a>
+</li>
+<li>Fvid2_isDataFmtYuv444()
+: <a class="el" href="csl__fvid2__data_types_8h.html#a906531b9be45f2bd528e1fac44b00340">csl_fvid2_dataTypes.h</a>
+</li>
+<li>Fvid2_isStandardVesa()
+: <a class="el" href="csl__fvid2__data_types_8h.html#a8996b9bd71f65f97abf2ee422611529b">csl_fvid2_dataTypes.h</a>
+</li>
+<li>Fvid2CropConfig_init()
+: <a class="el" href="csl__fvid2__data_types_8h.html#a7f76750350b75947c9bfa26b76798c92">csl_fvid2_dataTypes.h</a>
+</li>
+<li>Fvid2Format_init()
+: <a class="el" href="csl__fvid2__data_types_8h.html#a3c57266e7a813692eee72e3624f22fdf">csl_fvid2_dataTypes.h</a>
+</li>
+<li>Fvid2Frame_init()
+: <a class="el" href="csl__fvid2__data_types_8h.html#a519f857d75a4b946c99e0a8cfa0da148">csl_fvid2_dataTypes.h</a>
+</li>
+<li>Fvid2FrameList_init()
+: <a class="el" href="csl__fvid2__data_types_8h.html#a835800489d2c42aed71f30941b9f2fd2">csl_fvid2_dataTypes.h</a>
+</li>
+<li>Fvid2ModeInfo_init()
+: <a class="el" href="csl__fvid2__data_types_8h.html#a7fd1ec90c192cdc87f2e51819ad6b6fa">csl_fvid2_dataTypes.h</a>
+</li>
+<li>Fvid2PosConfig_init()
+: <a class="el" href="csl__fvid2__data_types_8h.html#acde86e2766599bb25a7126f364e78c4e">csl_fvid2_dataTypes.h</a>
+</li>
+<li>Fvid2SubFrameInfo_init()
+: <a class="el" href="csl__fvid2__data_types_8h.html#a699a19f64a958b0e023264d2626df860">csl_fvid2_dataTypes.h</a>
+</li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/globals_i.html b/packages/ti/drv/dss/docs/doxygen/html/globals_i.html
--- /dev/null
@@ -0,0 +1,122 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Globals</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li class="current"><a href="files.html"><span>Files</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow2" class="tabs2">
+ <ul class="tablist">
+ <li><a href="files.html"><span>File List</span></a></li>
+ <li class="current"><a href="globals.html"><span>Globals</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow3" class="tabs2">
+ <ul class="tablist">
+ <li class="current"><a href="globals.html"><span>All</span></a></li>
+ <li><a href="globals_func.html"><span>Functions</span></a></li>
+ <li><a href="globals_type.html"><span>Typedefs</span></a></li>
+ <li><a href="globals_enum.html"><span>Enumerations</span></a></li>
+ <li><a href="globals_eval.html"><span>Enumerator</span></a></li>
+ <li><a href="globals_defs.html"><span>Macros</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow4" class="tabs3">
+ <ul class="tablist">
+ <li><a href="globals.html#index_c"><span>c</span></a></li>
+ <li><a href="globals_d.html#index_d"><span>d</span></a></li>
+ <li><a href="globals_f.html#index_f"><span>f</span></a></li>
+ <li class="current"><a href="globals_i.html#index_i"><span>i</span></a></li>
+ </ul>
+ </div>
+</div><!-- top -->
+<div class="contents">
+<div class="textblock">Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation:</div>
+
+<h3><a class="anchor" id="index_i"></a>- i -</h3><ul>
+<li>IOCTL_DSS_DCTRL_CLEAR_PATH
+: <a class="el" href="group___d_s_s___d_c_t_r_l___i_o_c_t_l.html#ga4b16831ed360d38789d105376246c41a">dss_dctrl.h</a>
+</li>
+<li>IOCTL_DSS_DCTRL_GET_VP_ERROR_STATS
+: <a class="el" href="group___d_s_s___d_c_t_r_l___i_o_c_t_l.html#ga3d29253c153bdec7275527bd0b8fe4dc">dss_dctrl.h</a>
+</li>
+<li>IOCTL_DSS_DCTRL_REGISTER_SYNCLOST_CB
+: <a class="el" href="group___d_s_s___d_c_t_r_l___i_o_c_t_l.html#gae4ab29ac71849b0ad7810e5fecaf2b00">dss_dctrl.h</a>
+</li>
+<li>IOCTL_DSS_DCTRL_SET_ADV_VP_PARAMS
+: <a class="el" href="group___d_s_s___d_c_t_r_l___i_o_c_t_l.html#ga41ce0b6adeb9b7e098ce3b84113bf48f">dss_dctrl.h</a>
+</li>
+<li>IOCTL_DSS_DCTRL_SET_GLOBAL_DSS_PARAMS
+: <a class="el" href="group___d_s_s___d_c_t_r_l___i_o_c_t_l.html#ga48fd0f5f1e1476ef03b203ae9b1ccfaa">dss_dctrl.h</a>
+</li>
+<li>IOCTL_DSS_DCTRL_SET_LAYER_PARAMS
+: <a class="el" href="group___d_s_s___d_c_t_r_l___i_o_c_t_l.html#ga824609e625e41769f9042b8879a73861">dss_dctrl.h</a>
+</li>
+<li>IOCTL_DSS_DCTRL_SET_LCD_BLANK_TIMING_PARAMS
+: <a class="el" href="group___d_s_s___d_c_t_r_l___i_o_c_t_l.html#ga381f6aa554cc69e7fdb6dc6022086cee">dss_dctrl.h</a>
+</li>
+<li>IOCTL_DSS_DCTRL_SET_OLDI_PARAMS
+: <a class="el" href="group___d_s_s___d_c_t_r_l___i_o_c_t_l.html#ga0605d3de6b43d543ab11a8ba54a5fdbc">dss_dctrl.h</a>
+</li>
+<li>IOCTL_DSS_DCTRL_SET_OVERLAY_PARAMS
+: <a class="el" href="group___d_s_s___d_c_t_r_l___i_o_c_t_l.html#ga076d70564e492c0780bc4c747ca7ee82">dss_dctrl.h</a>
+</li>
+<li>IOCTL_DSS_DCTRL_SET_PATH
+: <a class="el" href="group___d_s_s___d_c_t_r_l___i_o_c_t_l.html#gae55f1184bc13a50a4e113e95835a5d0c">dss_dctrl.h</a>
+</li>
+<li>IOCTL_DSS_DCTRL_SET_VP_CSC_COEFF
+: <a class="el" href="group___d_s_s___d_c_t_r_l___i_o_c_t_l.html#gad01ce1c58a3a6966395f29a6d61d7684">dss_dctrl.h</a>
+</li>
+<li>IOCTL_DSS_DCTRL_SET_VP_PARAMS
+: <a class="el" href="group___d_s_s___d_c_t_r_l___i_o_c_t_l.html#gad9d06c559d83e6b0cd1fb72dfeca55c0">dss_dctrl.h</a>
+</li>
+<li>IOCTL_DSS_DCTRL_SET_VP_SAFETY_CHK_PARAMS
+: <a class="el" href="group___d_s_s___d_c_t_r_l___i_o_c_t_l.html#gabcaa1961abdf4145c9db4cedffe58259">dss_dctrl.h</a>
+</li>
+<li>IOCTL_DSS_DCTRL_STOP_VP
+: <a class="el" href="group___d_s_s___d_c_t_r_l___i_o_c_t_l.html#ga626c83cf4afb58295e807b710e10c5b0">dss_dctrl.h</a>
+</li>
+<li>IOCTL_DSS_DISP_GET_CURRENT_STATUS
+: <a class="el" href="group___d_s_s___d_i_s_p___i_o_c_t_l.html#ga0b629ede4d23a166a0d61a8a467cf2a7">dss_disp.h</a>
+</li>
+<li>IOCTL_DSS_DISP_REGISTER_BUF_PRGM_CB
+: <a class="el" href="group___d_s_s___d_i_s_p___i_o_c_t_l.html#ga273f588861739dcf0a3e69409cb86946">dss_disp.h</a>
+</li>
+<li>IOCTL_DSS_DISP_REGISTER_PIPE_PRGM_CB
+: <a class="el" href="group___d_s_s___d_i_s_p___i_o_c_t_l.html#ga0cb126061bb1b12410ac877e1f8ba1eb">dss_disp.h</a>
+</li>
+<li>IOCTL_DSS_DISP_REGISTER_PIPE_UNDERFLOW_CB
+: <a class="el" href="group___d_s_s___d_i_s_p___i_o_c_t_l.html#ga50c39b909c3e819d5662285112bbca59">dss_disp.h</a>
+</li>
+<li>IOCTL_DSS_DISP_SET_DSS_PARAMS
+: <a class="el" href="group___d_s_s___d_i_s_p___i_o_c_t_l.html#ga4bd8cea3f070081f575996cc7fe3571f">dss_disp.h</a>
+</li>
+<li>IOCTL_DSS_DISP_SET_PIPE_CSC_COEFF
+: <a class="el" href="group___d_s_s___d_i_s_p___i_o_c_t_l.html#gaa06196d5ebeb859291214d2d54b6858b">dss_disp.h</a>
+</li>
+<li>IOCTL_DSS_DISP_SET_PIPE_MFLAG_PARAMS
+: <a class="el" href="group___d_s_s___d_i_s_p___i_o_c_t_l.html#ga9643f8f73bbe0006d0c56d0bcedccef5">dss_disp.h</a>
+</li>
+<li>IOCTL_DSS_DISP_SET_PIPE_SAFETY_CHK_PARAMS
+: <a class="el" href="group___d_s_s___d_i_s_p___i_o_c_t_l.html#ga71325651456731ff972f3f976632f817">dss_disp.h</a>
+</li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/globals_type.html b/packages/ti/drv/dss/docs/doxygen/html/globals_type.html
--- /dev/null
@@ -0,0 +1,106 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Globals</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li class="current"><a href="files.html"><span>Files</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow2" class="tabs2">
+ <ul class="tablist">
+ <li><a href="files.html"><span>File List</span></a></li>
+ <li class="current"><a href="globals.html"><span>Globals</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow3" class="tabs2">
+ <ul class="tablist">
+ <li><a href="globals.html"><span>All</span></a></li>
+ <li><a href="globals_func.html"><span>Functions</span></a></li>
+ <li class="current"><a href="globals_type.html"><span>Typedefs</span></a></li>
+ <li><a href="globals_enum.html"><span>Enumerations</span></a></li>
+ <li><a href="globals_eval.html"><span>Enumerator</span></a></li>
+ <li><a href="globals_defs.html"><span>Macros</span></a></li>
+ </ul>
+ </div>
+</div><!-- top -->
+<div class="contents">
+ <ul>
+<li>CSL_dss_commRegs
+: <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1b5d2dc642484dd5b5af1cd7db50ef74">csl_dssCommon.h</a>
+</li>
+<li>CSL_dss_overlayRegs
+: <a class="el" href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#ga835adb8a42f16beefbfb5440b9dede63">csl_dssOverlay.h</a>
+</li>
+<li>CSL_dss_pipeRegs
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gafdca0345c9254a9bdbcd6e4a2ee000f6">csl_dssVideoPipe.h</a>
+</li>
+<li>CSL_dss_vpRegs
+: <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gaaaf231996a0d81bd23a1460d729dad23">csl_dssVideoPort.h</a>
+</li>
+<li>Dss_DctrlSyncLostCbFxn
+: <a class="el" href="dss__dctrl_8h.html#adc02df6de7a3d5940da55838ee464701">dss_dctrl.h</a>
+</li>
+<li>Dss_DispBufPrgmCbFxn
+: <a class="el" href="dss__disp_8h.html#a3f3415894bf0e54f2d06f24ea22c602e">dss_disp.h</a>
+</li>
+<li>Dss_DispPipePrgmCbFxn
+: <a class="el" href="dss__disp_8h.html#a4ccdd634499058281998bcc9a7af0555">dss_disp.h</a>
+</li>
+<li>Dss_DispUnderFlowCbFxn
+: <a class="el" href="dss__disp_8h.html#a14c7b8d97214b5c092eb8702e24522a1">dss_disp.h</a>
+</li>
+<li>Fvid2_BufferFormat
+: <a class="el" href="csl__fvid2__data_types_8h.html#a46ba9c505db41c885e5614571f680707">csl_fvid2_dataTypes.h</a>
+</li>
+<li>Fvid2_ColorCompStorageFmt
+: <a class="el" href="csl__fvid2__data_types_8h.html#a82c2f41780c5f44ed27f7ebadf18a21d">csl_fvid2_dataTypes.h</a>
+</li>
+<li>Fvid2_DataFormat
+: <a class="el" href="csl__fvid2__data_types_8h.html#a9f5096b017d15ffecdcc0990fd1b031a">csl_fvid2_dataTypes.h</a>
+</li>
+<li>Fvid2_DVFormat
+: <a class="el" href="csl__fvid2__data_types_8h.html#adb4edd1db6ff8f90a668f7d9d568b77e">csl_fvid2_dataTypes.h</a>
+</li>
+<li>Fvid2_EdgePolarity
+: <a class="el" href="csl__fvid2__data_types_8h.html#acfe95315f6c3bfd70f38bb2d4486bd19">csl_fvid2_dataTypes.h</a>
+</li>
+<li>Fvid2_Fid
+: <a class="el" href="csl__fvid2__data_types_8h.html#a46dbb7460c568075f1cd6959282d87cb">csl_fvid2_dataTypes.h</a>
+</li>
+<li>Fvid2_FidPol
+: <a class="el" href="csl__fvid2__data_types_8h.html#a771282d54cb8fd1a47a32f2210786a3a">csl_fvid2_dataTypes.h</a>
+</li>
+<li>Fvid2_FlipType
+: <a class="el" href="csl__fvid2__data_types_8h.html#a936d3064b224ce1fb3e7204b044e1013">csl_fvid2_dataTypes.h</a>
+</li>
+<li>Fvid2_Polarity
+: <a class="el" href="csl__fvid2__data_types_8h.html#a9e9754a80a4e33aebaf391204a570723">csl_fvid2_dataTypes.h</a>
+</li>
+<li>Fvid2_ScanFormat
+: <a class="el" href="csl__fvid2__data_types_8h.html#af5dfad95adb11f1220c13a37564b706e">csl_fvid2_dataTypes.h</a>
+</li>
+<li>Fvid2_Standard
+: <a class="el" href="csl__fvid2__data_types_8h.html#aaa2667d105d557f254c20b87534ed4b6">csl_fvid2_dataTypes.h</a>
+</li>
+<li>Fvid2_VideoIfWidth
+: <a class="el" href="csl__fvid2__data_types_8h.html#a3644341e8e51f60794fb15f219f0a5f7">csl_fvid2_dataTypes.h</a>
+</li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/group___c_s_l___d_s_s.html b/packages/ti/drv/dss/docs/doxygen/html/group___c_s_l___d_s_s.html
--- /dev/null
@@ -0,0 +1,62 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DSS</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="files.html"><span>Files</span></a></li>
+ </ul>
+ </div>
+</div><!-- top -->
+<div class="header">
+ <div class="summary">
+<a href="#groups">Modules</a> </div>
+ <div class="headertitle">
+<div class="title">DSS</div> </div>
+</div><!--header-->
+<div class="contents">
+<table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="groups"></a>
+Modules</h2></td></tr>
+<tr class="memitem:group___c_s_l___d_s_s_c_o_m_m_o_n"><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html">DSS Common CSL FL</a></td></tr>
+<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:group___c_s_l___d_s_s_o_v_e_r_l_a_y"><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html">DSS Overlay CSL FL</a></td></tr>
+<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:group___c_s_l___d_s_s_t_o_p"><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html">Top Level CSL FL</a></td></tr>
+<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e"><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html">DSS Video Pipe CSL FL</a></td></tr>
+<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t"><td class="memItemLeft" align="right" valign="top"> </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html">DSS Video Port CSL FL</a></td></tr>
+<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
+</table>
+<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
+<p>The Display Subsystem (DSS) provides the logic to interface display peripherals. DSS has multiple hardware blocks and in order to simplify DSS programming, DSS CSL FL driver has been logically divided into following modules:</p>
+<ul>
+<li><b> DSS Top </b> (See <a class="el" href="group___c_s_l___d_s_s_t_o_p.html">Top Level CSL FL</a>) <br/>
+</li>
+<li><b> DSS Common </b> (See <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html">DSS Common CSL FL</a>) <br/>
+</li>
+<li><b> DSS Video Pipe </b> (See <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html">DSS Video Pipe CSL FL</a>) <br/>
+</li>
+<li><b> DSS Overlay </b> (See <a class="el" href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html">DSS Overlay CSL FL</a>) <br/>
+</li>
+<li><b> DSS Video Port </b> (See <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html">DSS Video Port CSL FL</a>) <br/>
+ </li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/group___c_s_l___d_s_s_c_o_m_m_o_n.html b/packages/ti/drv/dss/docs/doxygen/html/group___c_s_l___d_s_s_c_o_m_m_o_n.html
--- /dev/null
@@ -0,0 +1,1065 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DSS Common CSL FL</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="files.html"><span>Files</span></a></li>
+ </ul>
+ </div>
+</div><!-- top -->
+<div class="header">
+ <div class="summary">
+<a href="#files">Files</a> |
+<a href="#nested-classes">Data Structures</a> |
+<a href="#typedef-members">Typedefs</a> |
+<a href="#func-members">Functions</a> </div>
+ <div class="headertitle">
+<div class="title">DSS Common CSL FL<div class="ingroups"><a class="el" href="group___c_s_l___d_s_s.html">DSS</a></div></div> </div>
+</div><!--header-->
+<div class="contents">
+<table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="files"></a>
+Files</h2></td></tr>
+<tr class="memitem:csl__dss_common_8h"><td class="memItemLeft" align="right" valign="top">file  </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__dss_common_8h.html">csl_dssCommon.h</a></td></tr>
+<tr class="memdesc:csl__dss_common_8h"><td class="mdescLeft"> </td><td class="mdescRight">DSS Common CSL FL interface file. <br/></td></tr>
+<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="nested-classes"></a>
+Data Structures</h2></td></tr>
+<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_global_m_flag_cfg.html">CSL_DssGlobalMFlagCfg</a></td></tr>
+<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">DSS Global MFLAG Config parameters. <a href="struct_c_s_l___dss_global_m_flag_cfg.html#details">More...</a><br/></td></tr>
+<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_cba_cfg.html">CSL_DssCbaCfg</a></td></tr>
+<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">DSS CBA Config parameters. <a href="struct_c_s_l___dss_cba_cfg.html#details">More...</a><br/></td></tr>
+<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="typedef-members"></a>
+Typedefs</h2></td></tr>
+<tr class="memitem:ga1b5d2dc642484dd5b5af1cd7db50ef74"><td class="memItemLeft" align="right" valign="top">typedef CSL_dss_common_mRegs </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1b5d2dc642484dd5b5af1cd7db50ef74">CSL_dss_commRegs</a></td></tr>
+<tr class="memdesc:ga1b5d2dc642484dd5b5af1cd7db50ef74"><td class="mdescLeft"> </td><td class="mdescRight">DSS Common Registers. <a href="#ga1b5d2dc642484dd5b5af1cd7db50ef74">More...</a><br/></td></tr>
+<tr class="separator:ga1b5d2dc642484dd5b5af1cd7db50ef74"><td class="memSeparator" colspan="2"> </td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a>
+Functions</h2></td></tr>
+<tr class="memitem:ga567b2f823b70e843ceb9c4ca8c501cae"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga567b2f823b70e843ceb9c4ca8c501cae">CSL_dssModuleReset</a> (<a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1b5d2dc642484dd5b5af1cd7db50ef74">CSL_dss_commRegs</a> *commRegs)</td></tr>
+<tr class="memdesc:ga567b2f823b70e843ceb9c4ca8c501cae"><td class="mdescLeft"> </td><td class="mdescRight">Reset the DSS Module. Application should make sure Video Ports are disabled before calling this API. <a href="#ga567b2f823b70e843ceb9c4ca8c501cae">More...</a><br/></td></tr>
+<tr class="separator:ga567b2f823b70e843ceb9c4ca8c501cae"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga78ae8cafecdf61459530ae0ecaee1312"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga78ae8cafecdf61459530ae0ecaee1312">CSL_dssEnableDispcIntr</a> (<a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1b5d2dc642484dd5b5af1cd7db50ef74">CSL_dss_commRegs</a> *commRegs, uint32_t intrMask, uint32_t intrEnable)</td></tr>
+<tr class="memdesc:ga78ae8cafecdf61459530ae0ecaee1312"><td class="mdescLeft"> </td><td class="mdescRight">Enable/disable the interrupts at DSS top level. <a href="#ga78ae8cafecdf61459530ae0ecaee1312">More...</a><br/></td></tr>
+<tr class="separator:ga78ae8cafecdf61459530ae0ecaee1312"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga1d1f5ed599418de87535e92ff113dbae"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1d1f5ed599418de87535e92ff113dbae">CSL_dssEnablePipeIntr</a> (<a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1b5d2dc642484dd5b5af1cd7db50ef74">CSL_dss_commRegs</a> *commRegs, uint32_t vidPipeId, uint32_t intrMask, uint32_t intrEnable)</td></tr>
+<tr class="memdesc:ga1d1f5ed599418de87535e92ff113dbae"><td class="mdescLeft"> </td><td class="mdescRight">Enable/disable the interrupts for Video Pipe. <a href="#ga1d1f5ed599418de87535e92ff113dbae">More...</a><br/></td></tr>
+<tr class="separator:ga1d1f5ed599418de87535e92ff113dbae"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gabc7928512f14f647d32d899a9850b4ad"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gabc7928512f14f647d32d899a9850b4ad">CSL_dssEnableVpIntr</a> (<a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1b5d2dc642484dd5b5af1cd7db50ef74">CSL_dss_commRegs</a> *commRegs, uint32_t portId, uint32_t intrMask, uint32_t intrEnable)</td></tr>
+<tr class="memdesc:gabc7928512f14f647d32d899a9850b4ad"><td class="mdescLeft"> </td><td class="mdescRight">Enable/disable the interrupts for Video Port. <a href="#gabc7928512f14f647d32d899a9850b4ad">More...</a><br/></td></tr>
+<tr class="separator:gabc7928512f14f647d32d899a9850b4ad"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga2f59e10e9d38932af384543d274dc90c"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga2f59e10e9d38932af384543d274dc90c">CSL_dssClearDispcIntr</a> (<a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1b5d2dc642484dd5b5af1cd7db50ef74">CSL_dss_commRegs</a> *commRegs, uint32_t intrMask)</td></tr>
+<tr class="memdesc:ga2f59e10e9d38932af384543d274dc90c"><td class="mdescLeft"> </td><td class="mdescRight">Clear the interrupts at DSS top level. <a href="#ga2f59e10e9d38932af384543d274dc90c">More...</a><br/></td></tr>
+<tr class="separator:ga2f59e10e9d38932af384543d274dc90c"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga1c2b89748e481bf4651cf4b87805177d"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1c2b89748e481bf4651cf4b87805177d">CSL_dssClearPipeIntr</a> (<a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1b5d2dc642484dd5b5af1cd7db50ef74">CSL_dss_commRegs</a> *commRegs, uint32_t vidPipeId, uint32_t intrMask)</td></tr>
+<tr class="memdesc:ga1c2b89748e481bf4651cf4b87805177d"><td class="mdescLeft"> </td><td class="mdescRight">Clear the interrupts for Video Pipe. <a href="#ga1c2b89748e481bf4651cf4b87805177d">More...</a><br/></td></tr>
+<tr class="separator:ga1c2b89748e481bf4651cf4b87805177d"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga086ca7d14c9f2a75305035c512972c18"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga086ca7d14c9f2a75305035c512972c18">CSL_dssClearVpIntr</a> (<a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1b5d2dc642484dd5b5af1cd7db50ef74">CSL_dss_commRegs</a> *commRegs, uint32_t portId, uint32_t intrMask)</td></tr>
+<tr class="memdesc:ga086ca7d14c9f2a75305035c512972c18"><td class="mdescLeft"> </td><td class="mdescRight">Clear the interrupts for Video Port. <a href="#ga086ca7d14c9f2a75305035c512972c18">More...</a><br/></td></tr>
+<tr class="separator:ga086ca7d14c9f2a75305035c512972c18"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga196052d031e6e46bc99f4631218d2da7"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga196052d031e6e46bc99f4631218d2da7">CSL_dssGetDispcIntrStatus</a> (const <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1b5d2dc642484dd5b5af1cd7db50ef74">CSL_dss_commRegs</a> *commRegs)</td></tr>
+<tr class="memdesc:ga196052d031e6e46bc99f4631218d2da7"><td class="mdescLeft"> </td><td class="mdescRight">Get the top level interrupt status of DSS. <a href="#ga196052d031e6e46bc99f4631218d2da7">More...</a><br/></td></tr>
+<tr class="separator:ga196052d031e6e46bc99f4631218d2da7"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gab25aea830bb6567a67be6018fbce58e2"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gab25aea830bb6567a67be6018fbce58e2">CSL_dssGetPipeIntrStatus</a> (const <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1b5d2dc642484dd5b5af1cd7db50ef74">CSL_dss_commRegs</a> *commRegs, uint32_t vidPipeId)</td></tr>
+<tr class="memdesc:gab25aea830bb6567a67be6018fbce58e2"><td class="mdescLeft"> </td><td class="mdescRight">Get the interrupt status of Video Pipe. <a href="#gab25aea830bb6567a67be6018fbce58e2">More...</a><br/></td></tr>
+<tr class="separator:gab25aea830bb6567a67be6018fbce58e2"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga7202424e4a3404aaf894e294be0a1f7d"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga7202424e4a3404aaf894e294be0a1f7d">CSL_dssGetVpIntrStatus</a> (const <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1b5d2dc642484dd5b5af1cd7db50ef74">CSL_dss_commRegs</a> *commRegs, uint32_t portId)</td></tr>
+<tr class="memdesc:ga7202424e4a3404aaf894e294be0a1f7d"><td class="mdescLeft"> </td><td class="mdescRight">Get the interrupt status of Video Port. <a href="#ga7202424e4a3404aaf894e294be0a1f7d">More...</a><br/></td></tr>
+<tr class="separator:ga7202424e4a3404aaf894e294be0a1f7d"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga51649681f3f478ab1c44d97aa3ed8323"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga51649681f3f478ab1c44d97aa3ed8323">CSL_dssSetGlobalMflagConfig</a> (<a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1b5d2dc642484dd5b5af1cd7db50ef74">CSL_dss_commRegs</a> *commRegs, const <a class="el" href="struct_c_s_l___dss_global_m_flag_cfg.html">CSL_DssGlobalMFlagCfg</a> *mflagCfg)</td></tr>
+<tr class="memdesc:ga51649681f3f478ab1c44d97aa3ed8323"><td class="mdescLeft"> </td><td class="mdescRight">Set the global MFLAG configuration. <a href="#ga51649681f3f478ab1c44d97aa3ed8323">More...</a><br/></td></tr>
+<tr class="separator:ga51649681f3f478ab1c44d97aa3ed8323"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gad3490bc78c9441400a4a77c933006f6c"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gad3490bc78c9441400a4a77c933006f6c">CSL_dssGlobalVpEnable</a> (<a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1b5d2dc642484dd5b5af1cd7db50ef74">CSL_dss_commRegs</a> *commRegs, uint32_t portIdMask)</td></tr>
+<tr class="memdesc:gad3490bc78c9441400a4a77c933006f6c"><td class="mdescLeft"> </td><td class="mdescRight">Enable the global VP enable bit. This allows setting multiple outputs synchronously. The 'OR' result of different masks can be used as input parameter. <a href="#gad3490bc78c9441400a4a77c933006f6c">More...</a><br/></td></tr>
+<tr class="separator:gad3490bc78c9441400a4a77c933006f6c"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga6c62a23a768c0ce357db64365ebdc0b0"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga6c62a23a768c0ce357db64365ebdc0b0">CSL_dssGlobalVpGoBitEnable</a> (<a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1b5d2dc642484dd5b5af1cd7db50ef74">CSL_dss_commRegs</a> *commRegs, uint32_t portIdMask)</td></tr>
+<tr class="memdesc:ga6c62a23a768c0ce357db64365ebdc0b0"><td class="mdescLeft"> </td><td class="mdescRight">Enable the global VP go bit. This allows setting multiple outputs synchronously. The 'OR' result of different masks can be used as input parameter. <a href="#ga6c62a23a768c0ce357db64365ebdc0b0">More...</a><br/></td></tr>
+<tr class="separator:ga6c62a23a768c0ce357db64365ebdc0b0"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga1ce4591b123f52bf6e6cc00a485fcd38"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1ce4591b123f52bf6e6cc00a485fcd38">CSL_dssSetCbaConfig</a> (<a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1b5d2dc642484dd5b5af1cd7db50ef74">CSL_dss_commRegs</a> *commRegs, const <a class="el" href="struct_c_s_l___dss_cba_cfg.html">CSL_DssCbaCfg</a> *cbaCfg)</td></tr>
+<tr class="memdesc:ga1ce4591b123f52bf6e6cc00a485fcd38"><td class="mdescLeft"> </td><td class="mdescRight">Set the CBA configuration. <a href="#ga1ce4591b123f52bf6e6cc00a485fcd38">More...</a><br/></td></tr>
+<tr class="separator:ga1ce4591b123f52bf6e6cc00a485fcd38"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga1c215888b011a5cca5880679ea560f74"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1c215888b011a5cca5880679ea560f74">CSL_dssConnectVpToDpi</a> (<a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1b5d2dc642484dd5b5af1cd7db50ef74">CSL_dss_commRegs</a> *commRegs, uint32_t portId, uint32_t dpiId)</td></tr>
+<tr class="memdesc:ga1c215888b011a5cca5880679ea560f74"><td class="mdescLeft"> </td><td class="mdescRight">This API can be used to select the VP connection to DPI. <a href="#ga1c215888b011a5cca5880679ea560f74">More...</a><br/></td></tr>
+<tr class="separator:ga1c215888b011a5cca5880679ea560f74"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga67eb3b87f230f3d3598ff1ea3c8ccbbe"><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga67eb3b87f230f3d3598ff1ea3c8ccbbe">CSL_dssGlobalMFlagCfgInit</a> (<a class="el" href="struct_c_s_l___dss_global_m_flag_cfg.html">CSL_DssGlobalMFlagCfg</a> *mflagCfg)</td></tr>
+<tr class="memdesc:ga67eb3b87f230f3d3598ff1ea3c8ccbbe"><td class="mdescLeft"> </td><td class="mdescRight"><a class="el" href="struct_c_s_l___dss_global_m_flag_cfg.html" title="DSS Global MFLAG Config parameters. ">CSL_DssGlobalMFlagCfg</a> structure init function. <a href="#ga67eb3b87f230f3d3598ff1ea3c8ccbbe">More...</a><br/></td></tr>
+<tr class="separator:ga67eb3b87f230f3d3598ff1ea3c8ccbbe"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gafa9009a2a94ae2222dfaaa166de1f33d"><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gafa9009a2a94ae2222dfaaa166de1f33d">CSL_dssCbaCfgInit</a> (<a class="el" href="struct_c_s_l___dss_cba_cfg.html">CSL_DssCbaCfg</a> *cbaCfg)</td></tr>
+<tr class="memdesc:gafa9009a2a94ae2222dfaaa166de1f33d"><td class="mdescLeft"> </td><td class="mdescRight"><a class="el" href="struct_c_s_l___dss_cba_cfg.html" title="DSS CBA Config parameters. ">CSL_DssCbaCfg</a> structure init function. <a href="#gafa9009a2a94ae2222dfaaa166de1f33d">More...</a><br/></td></tr>
+<tr class="separator:gafa9009a2a94ae2222dfaaa166de1f33d"><td class="memSeparator" colspan="2"> </td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
+DISPC Interrupt Mask</h2></td></tr>
+<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrp81aee38fb12043535df496932756a39e"></a><a class="anchor" id="CSL_DssDispcIntrMask"></a></p>
+</td></tr>
+<tr class="memitem:ga1c3a6a248c34ffb2b8183155f96107c9"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga1c3a6a248c34ffb2b8183155f96107c9"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1c3a6a248c34ffb2b8183155f96107c9">CSL_DSS_DISPC_INTR_WB_MASK</a>   ((uint32_t) 0x4000U)</td></tr>
+<tr class="memdesc:ga1c3a6a248c34ffb2b8183155f96107c9"><td class="mdescLeft"> </td><td class="mdescRight">Write Back Pipeline Interrupt. <br/></td></tr>
+<tr class="separator:ga1c3a6a248c34ffb2b8183155f96107c9"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gaca4d1f25e688c3c257df26fbed1bf0b0"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaca4d1f25e688c3c257df26fbed1bf0b0"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gaca4d1f25e688c3c257df26fbed1bf0b0">CSL_DSS_DISPC_INTR_VIDL2_MASK</a>   ((uint32_t) 0x80U)</td></tr>
+<tr class="memdesc:gaca4d1f25e688c3c257df26fbed1bf0b0"><td class="mdescLeft"> </td><td class="mdescRight">Video Lite Pipeline 2 Interrupt. <br/></td></tr>
+<tr class="separator:gaca4d1f25e688c3c257df26fbed1bf0b0"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga3e9bb13013658677983d41d243db6530"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga3e9bb13013658677983d41d243db6530"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga3e9bb13013658677983d41d243db6530">CSL_DSS_DISPC_INTR_VID2_MASK</a>   ((uint32_t) 0x40U)</td></tr>
+<tr class="memdesc:ga3e9bb13013658677983d41d243db6530"><td class="mdescLeft"> </td><td class="mdescRight">Video PipeLine 2 Interrupt. <br/></td></tr>
+<tr class="separator:ga3e9bb13013658677983d41d243db6530"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gabee1d0a280ee911c3f3863343167c034"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gabee1d0a280ee911c3f3863343167c034"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gabee1d0a280ee911c3f3863343167c034">CSL_DSS_DISPC_INTR_VIDL1_MASK</a>   ((uint32_t) 0x20U)</td></tr>
+<tr class="memdesc:gabee1d0a280ee911c3f3863343167c034"><td class="mdescLeft"> </td><td class="mdescRight">Video Lite Pipeline 1 Interrupt. <br/></td></tr>
+<tr class="separator:gabee1d0a280ee911c3f3863343167c034"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga06e5097b8fb8b1581b289d1e4c5f8b1d"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga06e5097b8fb8b1581b289d1e4c5f8b1d"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga06e5097b8fb8b1581b289d1e4c5f8b1d">CSL_DSS_DISPC_INTR_VID1_MASK</a>   ((uint32_t) 0x10U)</td></tr>
+<tr class="memdesc:ga06e5097b8fb8b1581b289d1e4c5f8b1d"><td class="mdescLeft"> </td><td class="mdescRight">Video PipeLine 1 Interrupt. <br/></td></tr>
+<tr class="separator:ga06e5097b8fb8b1581b289d1e4c5f8b1d"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga4663d2526dbf5150b3173715ee5bf049"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga4663d2526dbf5150b3173715ee5bf049"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga4663d2526dbf5150b3173715ee5bf049">CSL_DSS_DISPC_INTR_VP4_MASK</a>   ((uint32_t) 0x08U)</td></tr>
+<tr class="memdesc:ga4663d2526dbf5150b3173715ee5bf049"><td class="mdescLeft"> </td><td class="mdescRight">Video Port 4 Interrupt. <br/></td></tr>
+<tr class="separator:ga4663d2526dbf5150b3173715ee5bf049"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga72e1189718d84be73378a1c7243668d0"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga72e1189718d84be73378a1c7243668d0"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga72e1189718d84be73378a1c7243668d0">CSL_DSS_DISPC_INTR_VP3_MASK</a>   ((uint32_t) 0x04U)</td></tr>
+<tr class="memdesc:ga72e1189718d84be73378a1c7243668d0"><td class="mdescLeft"> </td><td class="mdescRight">Video Port 3 Interrupt. <br/></td></tr>
+<tr class="separator:ga72e1189718d84be73378a1c7243668d0"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga7c9437915888ed76ced5942c24acf8e7"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga7c9437915888ed76ced5942c24acf8e7"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga7c9437915888ed76ced5942c24acf8e7">CSL_DSS_DISPC_INTR_VP2_MASK</a>   ((uint32_t) 0x02U)</td></tr>
+<tr class="memdesc:ga7c9437915888ed76ced5942c24acf8e7"><td class="mdescLeft"> </td><td class="mdescRight">Video Port 2 Interrupt. <br/></td></tr>
+<tr class="separator:ga7c9437915888ed76ced5942c24acf8e7"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga9c7a9966f4f00cf84f8522ae35009f6f"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga9c7a9966f4f00cf84f8522ae35009f6f"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga9c7a9966f4f00cf84f8522ae35009f6f">CSL_DSS_DISPC_INTR_VP1_MASK</a>   ((uint32_t) 0x01U)</td></tr>
+<tr class="memdesc:ga9c7a9966f4f00cf84f8522ae35009f6f"><td class="mdescLeft"> </td><td class="mdescRight">Video Port 1 Interrupt. <br/></td></tr>
+<tr class="separator:ga9c7a9966f4f00cf84f8522ae35009f6f"><td class="memSeparator" colspan="2"> </td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
+Video Pipeline Interrupt Mask</h2></td></tr>
+<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrp6657c55ef569fadde81547e254373d35"></a><a class="anchor" id="CSL_DssVidPipeIntrMask"></a></p>
+</td></tr>
+<tr class="memitem:gac01c7ef875638b7ac0110c9306e97e03"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gac01c7ef875638b7ac0110c9306e97e03"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gac01c7ef875638b7ac0110c9306e97e03">CSL_DSS_VID_PIPE_INTR_FBDC_ILLEGALTILE_MASK</a>   ((uint32_t) CSL_DSS_COMMON_M_VID_IRQENABLE_0_FBDC_ILLEGALTILEREQ_EN_MASK)</td></tr>
+<tr class="memdesc:gac01c7ef875638b7ac0110c9306e97e03"><td class="mdescLeft"> </td><td class="mdescRight">Interrupt due to FBDC illegal tile request. <br/></td></tr>
+<tr class="separator:gac01c7ef875638b7ac0110c9306e97e03"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gaeb0df43d6aa106d64cbae9879d850ab2"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaeb0df43d6aa106d64cbae9879d850ab2"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gaeb0df43d6aa106d64cbae9879d850ab2">CSL_DSS_VID_PIPE_INTR_FBDC_CORRUPTTILE_MASK</a>   ((uint32_t) CSL_DSS_COMMON_M_VID_IRQENABLE_0_FBDC_CORRUPTTILE_EN_MASK)</td></tr>
+<tr class="memdesc:gaeb0df43d6aa106d64cbae9879d850ab2"><td class="mdescLeft"> </td><td class="mdescRight">Interrupt due to FBDC corrupted tile detection. <br/></td></tr>
+<tr class="separator:gaeb0df43d6aa106d64cbae9879d850ab2"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga5a394bb4a7b00f928e9287c7838a1a7d"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga5a394bb4a7b00f928e9287c7838a1a7d"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga5a394bb4a7b00f928e9287c7838a1a7d">CSL_DSS_VID_PIPE_INTR_SAFETYVIOLATION_MASK</a>   ((uint32_t) CSL_DSS_COMMON_M_VID_IRQENABLE_0_SAFETYREGION_EN_MASK)</td></tr>
+<tr class="memdesc:ga5a394bb4a7b00f928e9287c7838a1a7d"><td class="mdescLeft"> </td><td class="mdescRight">Interrupt due to safety violation. <br/></td></tr>
+<tr class="separator:ga5a394bb4a7b00f928e9287c7838a1a7d"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gaf2e001a112ba432cac5fec625eede116"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaf2e001a112ba432cac5fec625eede116"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gaf2e001a112ba432cac5fec625eede116">CSL_DSS_VID_PIPE_INTR_WINDOWEND_MASK</a>   ((uint32_t) CSL_DSS_COMMON_M_VID_IRQENABLE_0_VIDENDWINDOW_EN_MASK)</td></tr>
+<tr class="memdesc:gaf2e001a112ba432cac5fec625eede116"><td class="mdescLeft"> </td><td class="mdescRight">Interrupt due to video window end. <br/></td></tr>
+<tr class="separator:gaf2e001a112ba432cac5fec625eede116"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gac87f5c5a2d6fea0b3be605ef429fa7fa"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gac87f5c5a2d6fea0b3be605ef429fa7fa"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gac87f5c5a2d6fea0b3be605ef429fa7fa">CSL_DSS_VID_PIPE_INTR_BUFUNDERFLOW_MASK</a>   ((uint32_t) CSL_DSS_COMMON_M_VID_IRQENABLE_0_VIDBUFFERUNDERFLOW_EN_MASK)</td></tr>
+<tr class="memdesc:gac87f5c5a2d6fea0b3be605ef429fa7fa"><td class="mdescLeft"> </td><td class="mdescRight">Interrupt due to buffer underflow. <br/></td></tr>
+<tr class="separator:gac87f5c5a2d6fea0b3be605ef429fa7fa"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gab333a63a9c79c3af6e7b439ad23f6ee7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gab333a63a9c79c3af6e7b439ad23f6ee7">CSL_DSS_VID_PIPE_INTR_ALL_MASK</a></td></tr>
+<tr class="memdesc:gab333a63a9c79c3af6e7b439ad23f6ee7"><td class="mdescLeft"> </td><td class="mdescRight">All Video Pipe interrupts. <a href="#gab333a63a9c79c3af6e7b439ad23f6ee7">More...</a><br/></td></tr>
+<tr class="separator:gab333a63a9c79c3af6e7b439ad23f6ee7"><td class="memSeparator" colspan="2"> </td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
+Video Port Interrupt Mask</h2></td></tr>
+<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrpae2eaddb475336066eb1416be87fa275"></a><a class="anchor" id="CSL_DssVpIntrMask"></a></p>
+</td></tr>
+<tr class="memitem:ga17a731c79f013dff8a68313609310a14"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga17a731c79f013dff8a68313609310a14"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga17a731c79f013dff8a68313609310a14">CSL_DSS_VP_INTR_FRAMEDONE_MASK</a>   ((uint32_t) CSL_DSS_COMMON_M_VP_IRQENABLE_0_VPFRAMEDONE_EN_MASK)</td></tr>
+<tr class="memdesc:ga17a731c79f013dff8a68313609310a14"><td class="mdescLeft"> </td><td class="mdescRight">Frame Done for Video Port. <br/></td></tr>
+<tr class="separator:ga17a731c79f013dff8a68313609310a14"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga1ddaba61f8fa43456fb3d8549f69815f"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga1ddaba61f8fa43456fb3d8549f69815f"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1ddaba61f8fa43456fb3d8549f69815f">CSL_DSS_VP_INTR_VSYNC_MASK</a>   ((uint32_t) CSL_DSS_COMMON_M_VP_IRQENABLE_0_VPVSYNC_EN_MASK)</td></tr>
+<tr class="memdesc:ga1ddaba61f8fa43456fb3d8549f69815f"><td class="mdescLeft"> </td><td class="mdescRight">Vertical Synchronization for Video Port. <br/></td></tr>
+<tr class="separator:ga1ddaba61f8fa43456fb3d8549f69815f"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga323ac381f7d2dacaa7d710894740d796"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga323ac381f7d2dacaa7d710894740d796"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga323ac381f7d2dacaa7d710894740d796">CSL_DSS_VP_INTR_ODDVSYNC_MASK</a>   ((uint32_t) CSL_DSS_COMMON_M_VP_IRQENABLE_0_VPVSYNC_ODD_EN_MASK)</td></tr>
+<tr class="memdesc:ga323ac381f7d2dacaa7d710894740d796"><td class="mdescLeft"> </td><td class="mdescRight">VSYNC for odd field from interlace mode only. <br/></td></tr>
+<tr class="separator:ga323ac381f7d2dacaa7d710894740d796"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gab542da635c1710ea24c5a29e3e6f150c"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gab542da635c1710ea24c5a29e3e6f150c"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gab542da635c1710ea24c5a29e3e6f150c">CSL_DSS_VP_INTR_PROGLINENUM_MASK</a>   ((uint32_t) CSL_DSS_COMMON_M_VP_IRQENABLE_0_VPPROGRAMMEDLINENUMBER_EN_MASK)</td></tr>
+<tr class="memdesc:gab542da635c1710ea24c5a29e3e6f150c"><td class="mdescLeft"> </td><td class="mdescRight">Display scan has reached the programmed user line number. <br/></td></tr>
+<tr class="separator:gab542da635c1710ea24c5a29e3e6f150c"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga92903c6e1b355ed60ca8a15c1673c3b9"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga92903c6e1b355ed60ca8a15c1673c3b9"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga92903c6e1b355ed60ca8a15c1673c3b9">CSL_DSS_VP_INTR_SYNCLOST_MASK</a>   ((uint32_t) CSL_DSS_COMMON_M_VP_IRQENABLE_0_VPSYNCLOST_EN_MASK)</td></tr>
+<tr class="memdesc:ga92903c6e1b355ed60ca8a15c1673c3b9"><td class="mdescLeft"> </td><td class="mdescRight">Synchronization Lost for Video Port. <br/></td></tr>
+<tr class="separator:ga92903c6e1b355ed60ca8a15c1673c3b9"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gaa57aa7b8fc4736ff9598a0b8c5b308c6"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaa57aa7b8fc4736ff9598a0b8c5b308c6"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gaa57aa7b8fc4736ff9598a0b8c5b308c6">CSL_DSS_VP_INTR_ACBIASCOUNT_MASK</a>   ((uint32_t) CSL_DSS_COMMON_M_VP_IRQENABLE_0_ACBIASCOUNTSTATUS_EN_MASK)</td></tr>
+<tr class="memdesc:gaa57aa7b8fc4736ff9598a0b8c5b308c6"><td class="mdescLeft"> </td><td class="mdescRight">AC Bias transition counter has decremented to zero. <br/></td></tr>
+<tr class="separator:gaa57aa7b8fc4736ff9598a0b8c5b308c6"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gaf396f3733114c9eb5478a5a7852fb09e"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaf396f3733114c9eb5478a5a7852fb09e"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gaf396f3733114c9eb5478a5a7852fb09e">CSL_DSS_VP_INTR_SAFETYVIOLATION_REGION1_MASK</a>   ((uint32_t) 0x40U)</td></tr>
+<tr class="memdesc:gaf396f3733114c9eb5478a5a7852fb09e"><td class="mdescLeft"> </td><td class="mdescRight">Interrupt due to region 1 safety violation. <br/></td></tr>
+<tr class="separator:gaf396f3733114c9eb5478a5a7852fb09e"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gab1798bd63882f1a7da07264aa665a06e"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gab1798bd63882f1a7da07264aa665a06e"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gab1798bd63882f1a7da07264aa665a06e">CSL_DSS_VP_INTR_SAFETYVIOLATION_REGION2_MASK</a>   ((uint32_t) 0x80U)</td></tr>
+<tr class="memdesc:gab1798bd63882f1a7da07264aa665a06e"><td class="mdescLeft"> </td><td class="mdescRight">Interrupt due to region 2 safety violation. <br/></td></tr>
+<tr class="separator:gab1798bd63882f1a7da07264aa665a06e"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gaf436eb889d4490f9e0fb4b79ebeea6cb"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaf436eb889d4490f9e0fb4b79ebeea6cb"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gaf436eb889d4490f9e0fb4b79ebeea6cb">CSL_DSS_VP_INTR_SAFETYVIOLATION_REGION3_MASK</a>   ((uint32_t) 0x100U)</td></tr>
+<tr class="memdesc:gaf436eb889d4490f9e0fb4b79ebeea6cb"><td class="mdescLeft"> </td><td class="mdescRight">Interrupt due to region 3 safety violation. <br/></td></tr>
+<tr class="separator:gaf436eb889d4490f9e0fb4b79ebeea6cb"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga84dc6d8ce16d3bc5fd19fb1008f53998"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga84dc6d8ce16d3bc5fd19fb1008f53998"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga84dc6d8ce16d3bc5fd19fb1008f53998">CSL_DSS_VP_INTR_SAFETYVIOLATION_REGION4_MASK</a>   ((uint32_t) 0x200U)</td></tr>
+<tr class="memdesc:ga84dc6d8ce16d3bc5fd19fb1008f53998"><td class="mdescLeft"> </td><td class="mdescRight">Interrupt due to region 4 safety violation. <br/></td></tr>
+<tr class="separator:ga84dc6d8ce16d3bc5fd19fb1008f53998"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga2287bdc0f1a6bb8d7c25590cc580d26a"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga2287bdc0f1a6bb8d7c25590cc580d26a"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga2287bdc0f1a6bb8d7c25590cc580d26a">CSL_DSS_VP_INTR_SECURITYVIOLATION_MASK</a>   ((uint32_t) CSL_DSS_COMMON_M_VP_IRQENABLE_0_SECURITYVIOLATION_EN_MASK)</td></tr>
+<tr class="memdesc:ga2287bdc0f1a6bb8d7c25590cc580d26a"><td class="mdescLeft"> </td><td class="mdescRight">Interrupt due to security violation. <br/></td></tr>
+<tr class="separator:ga2287bdc0f1a6bb8d7c25590cc580d26a"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga4b7fe7d3fbf537386925b2118337517d"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga4b7fe7d3fbf537386925b2118337517d"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga4b7fe7d3fbf537386925b2118337517d">CSL_DSS_VP_INTR_GOBITCLEAR_MASK</a>   ((uint32_t) CSL_DSS_COMMON_M_VP_IRQENABLE_0_VPSYNC_EN_MASK)</td></tr>
+<tr class="memdesc:ga4b7fe7d3fbf537386925b2118337517d"><td class="mdescLeft"> </td><td class="mdescRight">Go bit clear interrupt for VP. <br/></td></tr>
+<tr class="separator:ga4b7fe7d3fbf537386925b2118337517d"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga07b59cbeb37e6d5337a4117ecf688973"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga07b59cbeb37e6d5337a4117ecf688973"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga07b59cbeb37e6d5337a4117ecf688973">CSL_DSS_VP_INTR_SAFETYVIOLATION_REGION5_MASK</a>   ((uint32_t) 0x2000U)</td></tr>
+<tr class="memdesc:ga07b59cbeb37e6d5337a4117ecf688973"><td class="mdescLeft"> </td><td class="mdescRight">Interrupt due to region 5 safety violation. <br/></td></tr>
+<tr class="separator:ga07b59cbeb37e6d5337a4117ecf688973"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gab854dd38750979bf152c0bb7d39f10f9"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gab854dd38750979bf152c0bb7d39f10f9"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gab854dd38750979bf152c0bb7d39f10f9">CSL_DSS_VP_INTR_SAFETYVIOLATION_REGION6_MASK</a>   ((uint32_t) 0x4000U)</td></tr>
+<tr class="memdesc:gab854dd38750979bf152c0bb7d39f10f9"><td class="mdescLeft"> </td><td class="mdescRight">Interrupt due to region 6 safety violation. <br/></td></tr>
+<tr class="separator:gab854dd38750979bf152c0bb7d39f10f9"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gafd2c9bb5bce5224951f713e6a67951cb"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gafd2c9bb5bce5224951f713e6a67951cb"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gafd2c9bb5bce5224951f713e6a67951cb">CSL_DSS_VP_INTR_SAFETYVIOLATION_REGION7_MASK</a>   ((uint32_t) 0x8000U)</td></tr>
+<tr class="memdesc:gafd2c9bb5bce5224951f713e6a67951cb"><td class="mdescLeft"> </td><td class="mdescRight">Interrupt due to region 7 safety violation. <br/></td></tr>
+<tr class="separator:gafd2c9bb5bce5224951f713e6a67951cb"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gafee920aa4503ff1c8ec7d91a028802ba"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gafee920aa4503ff1c8ec7d91a028802ba"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gafee920aa4503ff1c8ec7d91a028802ba">CSL_DSS_VP_INTR_SAFETYVIOLATION_REGION8_MASK</a>   ((uint32_t) 0x10000U)</td></tr>
+<tr class="memdesc:gafee920aa4503ff1c8ec7d91a028802ba"><td class="mdescLeft"> </td><td class="mdescRight">Interrupt due to region 8 safety violation. <br/></td></tr>
+<tr class="separator:gafee920aa4503ff1c8ec7d91a028802ba"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga062132a334862eff31df843867a5a9c1"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga062132a334862eff31df843867a5a9c1">CSL_DSS_VP_INTR_ALL_MASK</a></td></tr>
+<tr class="memdesc:ga062132a334862eff31df843867a5a9c1"><td class="mdescLeft"> </td><td class="mdescRight">All Video Port interrupts. <a href="#ga062132a334862eff31df843867a5a9c1">More...</a><br/></td></tr>
+<tr class="separator:ga062132a334862eff31df843867a5a9c1"><td class="memSeparator" colspan="2"> </td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
+Write back Pipeline Interrupt Mask</h2></td></tr>
+<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrp9ed42cc2459afd6c0d31ba56b77b7d29"></a><a class="anchor" id="CSL_DssWBPipeIntrMask"></a></p>
+</td></tr>
+<tr class="memitem:ga7956cca4dac339f72e3bfd028cef8aea"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga7956cca4dac339f72e3bfd028cef8aea"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga7956cca4dac339f72e3bfd028cef8aea">CSL_DSS_WB_PIPE_INTR_WBSYNC_MASK</a>   ((uint32_t) CSL_DSS_COMMON_M_WB_IRQENABLE_WBSYNC_EN_MASK)</td></tr>
+<tr class="memdesc:ga7956cca4dac339f72e3bfd028cef8aea"><td class="mdescLeft"> </td><td class="mdescRight">Interrupt due to completion of write back sync. <br/></td></tr>
+<tr class="separator:ga7956cca4dac339f72e3bfd028cef8aea"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga1fcec556feabbf38743c1ff5ece580de"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga1fcec556feabbf38743c1ff5ece580de"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1fcec556feabbf38743c1ff5ece580de">CSL_DSS_WB_PIPE_INTR_SECURITYVIOLATION_MASK</a>   ((uint32_t) CSL_DSS_COMMON_M_WB_IRQENABLE_SECURITYVIOLATION_EN_MASK)</td></tr>
+<tr class="memdesc:ga1fcec556feabbf38743c1ff5ece580de"><td class="mdescLeft"> </td><td class="mdescRight">Interrupt due to security violation. <br/></td></tr>
+<tr class="separator:ga1fcec556feabbf38743c1ff5ece580de"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga21c87fbab481fb6ea24b202b12610a35"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga21c87fbab481fb6ea24b202b12610a35"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga21c87fbab481fb6ea24b202b12610a35">CSL_DSS_WB_PIPE_INTR_FRAMEDONE_MASK</a>   ((uint32_t) CSL_DSS_COMMON_M_WB_IRQENABLE_WBFRAMEDONE_EN_MASK)</td></tr>
+<tr class="memdesc:ga21c87fbab481fb6ea24b202b12610a35"><td class="mdescLeft"> </td><td class="mdescRight">Interrupt due to write back frame completion. <br/></td></tr>
+<tr class="separator:ga21c87fbab481fb6ea24b202b12610a35"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga49798f6dd7f9930bcde282c21197c739"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga49798f6dd7f9930bcde282c21197c739"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga49798f6dd7f9930bcde282c21197c739">CSL_DSS_WB_PIPE_INTR_UNCOMPLETE_MASK</a>   ((uint32_t) CSL_DSS_COMMON_M_WB_IRQENABLE_WBUNCOMPLETEERROR_EN_MASK)</td></tr>
+<tr class="memdesc:ga49798f6dd7f9930bcde282c21197c739"><td class="mdescLeft"> </td><td class="mdescRight">Interrupt due to buffer flush before full drain (Only Capture WB) <br/></td></tr>
+<tr class="separator:ga49798f6dd7f9930bcde282c21197c739"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga9a426ebaaf7f08452b96825dff7dd6ea"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga9a426ebaaf7f08452b96825dff7dd6ea"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga9a426ebaaf7f08452b96825dff7dd6ea">CSL_DSS_WB_PIPE_INTR_OVERFLOW_MASK</a>   ((uint32_t) CSL_DSS_COMMON_M_WB_IRQENABLE_WBBUFFEROVERFLOW_EN_MASK)</td></tr>
+<tr class="memdesc:ga9a426ebaaf7f08452b96825dff7dd6ea"><td class="mdescLeft"> </td><td class="mdescRight">Interrupt due to buffer overflow. <br/></td></tr>
+<tr class="separator:ga9a426ebaaf7f08452b96825dff7dd6ea"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gaa87662a09ae286e277da4b5ee2243b71"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gaa87662a09ae286e277da4b5ee2243b71">CSL_DSS_WB_PIPE_INTR_ALL_MASK</a></td></tr>
+<tr class="memdesc:gaa87662a09ae286e277da4b5ee2243b71"><td class="mdescLeft"> </td><td class="mdescRight">All Write Back Pipe interrupts. <a href="#gaa87662a09ae286e277da4b5ee2243b71">More...</a><br/></td></tr>
+<tr class="separator:gaa87662a09ae286e277da4b5ee2243b71"><td class="memSeparator" colspan="2"> </td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
+Mflag Start Mode</h2></td></tr>
+<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrp08193763171ec700721d0abcc38b400a"></a><a class="anchor" id="CSL_DssMflagStartMode"></a></p>
+</td></tr>
+<tr class="memitem:ga8463a9a268552ec6233a928947813a7d"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga8463a9a268552ec6233a928947813a7d"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga8463a9a268552ec6233a928947813a7d">CSL_DSS_MFLAG_START_NORMAL</a>   ((uint32_t) CSL_DSS_COMMON_M_DISPC_GLOBAL_MFLAG_ATTRIBUTE_MFLAG_START_VAL_MFLAGNORMALSTARTMODE)</td></tr>
+<tr class="memdesc:ga8463a9a268552ec6233a928947813a7d"><td class="mdescLeft"> </td><td class="mdescRight">Mflag of each pipe is kept at 0 until preload is reached. <br/></td></tr>
+<tr class="separator:ga8463a9a268552ec6233a928947813a7d"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga25a7a13a5ed7fa79de52587991cd6e8c"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga25a7a13a5ed7fa79de52587991cd6e8c"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga25a7a13a5ed7fa79de52587991cd6e8c">CSL_DSS_MFLAG_START_FORCED</a>   ((uint32_t) CSL_DSS_COMMON_M_DISPC_GLOBAL_MFLAG_ATTRIBUTE_MFLAG_START_VAL_MFLAGFORCESTARTMODE)</td></tr>
+<tr class="memdesc:ga25a7a13a5ed7fa79de52587991cd6e8c"><td class="mdescLeft"> </td><td class="mdescRight">Mflag is driven as per Mflag Ctrl. <br/></td></tr>
+<tr class="separator:ga25a7a13a5ed7fa79de52587991cd6e8c"><td class="memSeparator" colspan="2"> </td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
+Mflag Control</h2></td></tr>
+<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrp7926dc16bf39d1966e3506efc485c4d6"></a><a class="anchor" id="CSL_DssMflagCtrl"></a></p>
+</td></tr>
+<tr class="memitem:ga8a1fdde2ee44a5d4f758add66d1e531a"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga8a1fdde2ee44a5d4f758add66d1e531a"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga8a1fdde2ee44a5d4f758add66d1e531a">CSL_DSS_MFLAG_CTRL_DISABLED</a>   ((uint32_t) CSL_DSS_COMMON_M_DISPC_GLOBAL_MFLAG_ATTRIBUTE_MFLAG_CTRL_VAL_MFLAGDIS)</td></tr>
+<tr class="memdesc:ga8a1fdde2ee44a5d4f758add66d1e531a"><td class="mdescLeft"> </td><td class="mdescRight">Mflag is disabled. <br/></td></tr>
+<tr class="separator:ga8a1fdde2ee44a5d4f758add66d1e531a"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gae33f049f22cfce779d267a22ba79d1e3"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gae33f049f22cfce779d267a22ba79d1e3"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gae33f049f22cfce779d267a22ba79d1e3">CSL_DSS_MFLAG_CTRL_FORCE_ENABLE</a>   ((uint32_t) CSL_DSS_COMMON_M_DISPC_GLOBAL_MFLAG_ATTRIBUTE_MFLAG_CTRL_VAL_MFLAGFORCE)</td></tr>
+<tr class="memdesc:gae33f049f22cfce779d267a22ba79d1e3"><td class="mdescLeft"> </td><td class="mdescRight">Mflag is force enabled. <br/></td></tr>
+<tr class="separator:gae33f049f22cfce779d267a22ba79d1e3"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gafd85bc61dad64ede428e21526edd470a"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gafd85bc61dad64ede428e21526edd470a"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gafd85bc61dad64ede428e21526edd470a">CSL_DSS_MFLAG_CTRL_DYNAMIC</a>   ((uint32_t) CSL_DSS_COMMON_M_DISPC_GLOBAL_MFLAG_ATTRIBUTE_MFLAG_CTRL_VAL_MFLAGEN)</td></tr>
+<tr class="memdesc:gafd85bc61dad64ede428e21526edd470a"><td class="mdescLeft"> </td><td class="mdescRight">Mflag signal is set dynamically as per rules. <br/></td></tr>
+<tr class="separator:gafd85bc61dad64ede428e21526edd470a"><td class="memSeparator" colspan="2"> </td></tr>
+</table>
+<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
+<h2 class="groupheader">Macro Definition Documentation</h2>
+<a class="anchor" id="gab333a63a9c79c3af6e7b439ad23f6ee7"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">#define CSL_DSS_VID_PIPE_INTR_ALL_MASK</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<b>Value:</b><div class="fragment"><div class="line">(<a class="code" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gac01c7ef875638b7ac0110c9306e97e03">CSL_DSS_VID_PIPE_INTR_FBDC_ILLEGALTILE_MASK</a> | <a class="code" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gaeb0df43d6aa106d64cbae9879d850ab2">\</a></div>
+<div class="line"><a class="code" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gaeb0df43d6aa106d64cbae9879d850ab2"> CSL_DSS_VID_PIPE_INTR_FBDC_CORRUPTTILE_MASK</a> | <a class="code" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga5a394bb4a7b00f928e9287c7838a1a7d">\</a></div>
+<div class="line"><a class="code" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga5a394bb4a7b00f928e9287c7838a1a7d"> CSL_DSS_VID_PIPE_INTR_SAFETYVIOLATION_MASK</a> | <a class="code" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gaf2e001a112ba432cac5fec625eede116">\</a></div>
+<div class="line"><a class="code" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gaf2e001a112ba432cac5fec625eede116"> CSL_DSS_VID_PIPE_INTR_WINDOWEND_MASK</a> | <a class="code" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gac87f5c5a2d6fea0b3be605ef429fa7fa">\</a></div>
+<div class="line"><a class="code" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gac87f5c5a2d6fea0b3be605ef429fa7fa"> CSL_DSS_VID_PIPE_INTR_BUFUNDERFLOW_MASK</a>)</div>
+<div class="ttc" id="group___c_s_l___d_s_s_c_o_m_m_o_n_html_gac87f5c5a2d6fea0b3be605ef429fa7fa"><div class="ttname"><a href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gac87f5c5a2d6fea0b3be605ef429fa7fa">CSL_DSS_VID_PIPE_INTR_BUFUNDERFLOW_MASK</a></div><div class="ttdeci">#define CSL_DSS_VID_PIPE_INTR_BUFUNDERFLOW_MASK</div><div class="ttdoc">Interrupt due to buffer underflow. </div><div class="ttdef"><b>Definition:</b> csl_dssCommon.h:115</div></div>
+<div class="ttc" id="group___c_s_l___d_s_s_c_o_m_m_o_n_html_ga5a394bb4a7b00f928e9287c7838a1a7d"><div class="ttname"><a href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga5a394bb4a7b00f928e9287c7838a1a7d">CSL_DSS_VID_PIPE_INTR_SAFETYVIOLATION_MASK</a></div><div class="ttdeci">#define CSL_DSS_VID_PIPE_INTR_SAFETYVIOLATION_MASK</div><div class="ttdoc">Interrupt due to safety violation. </div><div class="ttdef"><b>Definition:</b> csl_dssCommon.h:109</div></div>
+<div class="ttc" id="group___c_s_l___d_s_s_c_o_m_m_o_n_html_gaeb0df43d6aa106d64cbae9879d850ab2"><div class="ttname"><a href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gaeb0df43d6aa106d64cbae9879d850ab2">CSL_DSS_VID_PIPE_INTR_FBDC_CORRUPTTILE_MASK</a></div><div class="ttdeci">#define CSL_DSS_VID_PIPE_INTR_FBDC_CORRUPTTILE_MASK</div><div class="ttdoc">Interrupt due to FBDC corrupted tile detection. </div><div class="ttdef"><b>Definition:</b> csl_dssCommon.h:106</div></div>
+<div class="ttc" id="group___c_s_l___d_s_s_c_o_m_m_o_n_html_gac01c7ef875638b7ac0110c9306e97e03"><div class="ttname"><a href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gac01c7ef875638b7ac0110c9306e97e03">CSL_DSS_VID_PIPE_INTR_FBDC_ILLEGALTILE_MASK</a></div><div class="ttdeci">#define CSL_DSS_VID_PIPE_INTR_FBDC_ILLEGALTILE_MASK</div><div class="ttdoc">Interrupt due to FBDC illegal tile request. </div><div class="ttdef"><b>Definition:</b> csl_dssCommon.h:103</div></div>
+<div class="ttc" id="group___c_s_l___d_s_s_c_o_m_m_o_n_html_gaf2e001a112ba432cac5fec625eede116"><div class="ttname"><a href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gaf2e001a112ba432cac5fec625eede116">CSL_DSS_VID_PIPE_INTR_WINDOWEND_MASK</a></div><div class="ttdeci">#define CSL_DSS_VID_PIPE_INTR_WINDOWEND_MASK</div><div class="ttdoc">Interrupt due to video window end. </div><div class="ttdef"><b>Definition:</b> csl_dssCommon.h:112</div></div>
+</div><!-- fragment -->
+<p>All Video Pipe interrupts. </p>
+
+</div>
+</div>
+<a class="anchor" id="ga062132a334862eff31df843867a5a9c1"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">#define CSL_DSS_VP_INTR_ALL_MASK</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<b>Value:</b><div class="fragment"><div class="line">(<a class="code" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga17a731c79f013dff8a68313609310a14">CSL_DSS_VP_INTR_FRAMEDONE_MASK</a> | <a class="code" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1ddaba61f8fa43456fb3d8549f69815f">\</a></div>
+<div class="line"><a class="code" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1ddaba61f8fa43456fb3d8549f69815f"> CSL_DSS_VP_INTR_VSYNC_MASK</a> | <a class="code" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga323ac381f7d2dacaa7d710894740d796">\</a></div>
+<div class="line"><a class="code" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga323ac381f7d2dacaa7d710894740d796"> CSL_DSS_VP_INTR_ODDVSYNC_MASK</a> | <a class="code" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gab542da635c1710ea24c5a29e3e6f150c">\</a></div>
+<div class="line"><a class="code" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gab542da635c1710ea24c5a29e3e6f150c"> CSL_DSS_VP_INTR_PROGLINENUM_MASK</a> | <a class="code" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga92903c6e1b355ed60ca8a15c1673c3b9">\</a></div>
+<div class="line"><a class="code" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga92903c6e1b355ed60ca8a15c1673c3b9"> CSL_DSS_VP_INTR_SYNCLOST_MASK</a> | <a class="code" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gaa57aa7b8fc4736ff9598a0b8c5b308c6">\</a></div>
+<div class="line"><a class="code" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gaa57aa7b8fc4736ff9598a0b8c5b308c6"> CSL_DSS_VP_INTR_ACBIASCOUNT_MASK</a> | <a class="code" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gaf396f3733114c9eb5478a5a7852fb09e">\</a></div>
+<div class="line"><a class="code" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gaf396f3733114c9eb5478a5a7852fb09e"> CSL_DSS_VP_INTR_SAFETYVIOLATION_REGION1_MASK</a> | <a class="code" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gab1798bd63882f1a7da07264aa665a06e">\</a></div>
+<div class="line"><a class="code" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gab1798bd63882f1a7da07264aa665a06e"> CSL_DSS_VP_INTR_SAFETYVIOLATION_REGION2_MASK</a> | <a class="code" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gaf436eb889d4490f9e0fb4b79ebeea6cb">\</a></div>
+<div class="line"><a class="code" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gaf436eb889d4490f9e0fb4b79ebeea6cb"> CSL_DSS_VP_INTR_SAFETYVIOLATION_REGION3_MASK</a> | <a class="code" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga84dc6d8ce16d3bc5fd19fb1008f53998">\</a></div>
+<div class="line"><a class="code" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga84dc6d8ce16d3bc5fd19fb1008f53998"> CSL_DSS_VP_INTR_SAFETYVIOLATION_REGION4_MASK</a> | <a class="code" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga2287bdc0f1a6bb8d7c25590cc580d26a">\</a></div>
+<div class="line"><a class="code" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga2287bdc0f1a6bb8d7c25590cc580d26a"> CSL_DSS_VP_INTR_SECURITYVIOLATION_MASK</a> | <a class="code" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga4b7fe7d3fbf537386925b2118337517d">\</a></div>
+<div class="line"><a class="code" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga4b7fe7d3fbf537386925b2118337517d"> CSL_DSS_VP_INTR_GOBITCLEAR_MASK</a> | <a class="code" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga07b59cbeb37e6d5337a4117ecf688973">\</a></div>
+<div class="line"><a class="code" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga07b59cbeb37e6d5337a4117ecf688973"> CSL_DSS_VP_INTR_SAFETYVIOLATION_REGION5_MASK</a> | <a class="code" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gab854dd38750979bf152c0bb7d39f10f9">\</a></div>
+<div class="line"><a class="code" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gab854dd38750979bf152c0bb7d39f10f9"> CSL_DSS_VP_INTR_SAFETYVIOLATION_REGION6_MASK</a> | <a class="code" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gafd2c9bb5bce5224951f713e6a67951cb">\</a></div>
+<div class="line"><a class="code" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gafd2c9bb5bce5224951f713e6a67951cb"> CSL_DSS_VP_INTR_SAFETYVIOLATION_REGION7_MASK</a> | <a class="code" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gafee920aa4503ff1c8ec7d91a028802ba">\</a></div>
+<div class="line"><a class="code" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gafee920aa4503ff1c8ec7d91a028802ba"> CSL_DSS_VP_INTR_SAFETYVIOLATION_REGION8_MASK</a>)</div>
+<div class="ttc" id="group___c_s_l___d_s_s_c_o_m_m_o_n_html_gab1798bd63882f1a7da07264aa665a06e"><div class="ttname"><a href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gab1798bd63882f1a7da07264aa665a06e">CSL_DSS_VP_INTR_SAFETYVIOLATION_REGION2_MASK</a></div><div class="ttdeci">#define CSL_DSS_VP_INTR_SAFETYVIOLATION_REGION2_MASK</div><div class="ttdoc">Interrupt due to region 2 safety violation. </div><div class="ttdef"><b>Definition:</b> csl_dssCommon.h:154</div></div>
+<div class="ttc" id="group___c_s_l___d_s_s_c_o_m_m_o_n_html_gafee920aa4503ff1c8ec7d91a028802ba"><div class="ttname"><a href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gafee920aa4503ff1c8ec7d91a028802ba">CSL_DSS_VP_INTR_SAFETYVIOLATION_REGION8_MASK</a></div><div class="ttdeci">#define CSL_DSS_VP_INTR_SAFETYVIOLATION_REGION8_MASK</div><div class="ttdoc">Interrupt due to region 8 safety violation. </div><div class="ttdef"><b>Definition:</b> csl_dssCommon.h:178</div></div>
+<div class="ttc" id="group___c_s_l___d_s_s_c_o_m_m_o_n_html_ga323ac381f7d2dacaa7d710894740d796"><div class="ttname"><a href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga323ac381f7d2dacaa7d710894740d796">CSL_DSS_VP_INTR_ODDVSYNC_MASK</a></div><div class="ttdeci">#define CSL_DSS_VP_INTR_ODDVSYNC_MASK</div><div class="ttdoc">VSYNC for odd field from interlace mode only. </div><div class="ttdef"><b>Definition:</b> csl_dssCommon.h:139</div></div>
+<div class="ttc" id="group___c_s_l___d_s_s_c_o_m_m_o_n_html_ga92903c6e1b355ed60ca8a15c1673c3b9"><div class="ttname"><a href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga92903c6e1b355ed60ca8a15c1673c3b9">CSL_DSS_VP_INTR_SYNCLOST_MASK</a></div><div class="ttdeci">#define CSL_DSS_VP_INTR_SYNCLOST_MASK</div><div class="ttdoc">Synchronization Lost for Video Port. </div><div class="ttdef"><b>Definition:</b> csl_dssCommon.h:145</div></div>
+<div class="ttc" id="group___c_s_l___d_s_s_c_o_m_m_o_n_html_ga1ddaba61f8fa43456fb3d8549f69815f"><div class="ttname"><a href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1ddaba61f8fa43456fb3d8549f69815f">CSL_DSS_VP_INTR_VSYNC_MASK</a></div><div class="ttdeci">#define CSL_DSS_VP_INTR_VSYNC_MASK</div><div class="ttdoc">Vertical Synchronization for Video Port. </div><div class="ttdef"><b>Definition:</b> csl_dssCommon.h:136</div></div>
+<div class="ttc" id="group___c_s_l___d_s_s_c_o_m_m_o_n_html_ga84dc6d8ce16d3bc5fd19fb1008f53998"><div class="ttname"><a href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga84dc6d8ce16d3bc5fd19fb1008f53998">CSL_DSS_VP_INTR_SAFETYVIOLATION_REGION4_MASK</a></div><div class="ttdeci">#define CSL_DSS_VP_INTR_SAFETYVIOLATION_REGION4_MASK</div><div class="ttdoc">Interrupt due to region 4 safety violation. </div><div class="ttdef"><b>Definition:</b> csl_dssCommon.h:160</div></div>
+<div class="ttc" id="group___c_s_l___d_s_s_c_o_m_m_o_n_html_ga17a731c79f013dff8a68313609310a14"><div class="ttname"><a href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga17a731c79f013dff8a68313609310a14">CSL_DSS_VP_INTR_FRAMEDONE_MASK</a></div><div class="ttdeci">#define CSL_DSS_VP_INTR_FRAMEDONE_MASK</div><div class="ttdoc">Frame Done for Video Port. </div><div class="ttdef"><b>Definition:</b> csl_dssCommon.h:133</div></div>
+<div class="ttc" id="group___c_s_l___d_s_s_c_o_m_m_o_n_html_gab854dd38750979bf152c0bb7d39f10f9"><div class="ttname"><a href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gab854dd38750979bf152c0bb7d39f10f9">CSL_DSS_VP_INTR_SAFETYVIOLATION_REGION6_MASK</a></div><div class="ttdeci">#define CSL_DSS_VP_INTR_SAFETYVIOLATION_REGION6_MASK</div><div class="ttdoc">Interrupt due to region 6 safety violation. </div><div class="ttdef"><b>Definition:</b> csl_dssCommon.h:172</div></div>
+<div class="ttc" id="group___c_s_l___d_s_s_c_o_m_m_o_n_html_ga07b59cbeb37e6d5337a4117ecf688973"><div class="ttname"><a href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga07b59cbeb37e6d5337a4117ecf688973">CSL_DSS_VP_INTR_SAFETYVIOLATION_REGION5_MASK</a></div><div class="ttdeci">#define CSL_DSS_VP_INTR_SAFETYVIOLATION_REGION5_MASK</div><div class="ttdoc">Interrupt due to region 5 safety violation. </div><div class="ttdef"><b>Definition:</b> csl_dssCommon.h:169</div></div>
+<div class="ttc" id="group___c_s_l___d_s_s_c_o_m_m_o_n_html_gab542da635c1710ea24c5a29e3e6f150c"><div class="ttname"><a href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gab542da635c1710ea24c5a29e3e6f150c">CSL_DSS_VP_INTR_PROGLINENUM_MASK</a></div><div class="ttdeci">#define CSL_DSS_VP_INTR_PROGLINENUM_MASK</div><div class="ttdoc">Display scan has reached the programmed user line number. </div><div class="ttdef"><b>Definition:</b> csl_dssCommon.h:142</div></div>
+<div class="ttc" id="group___c_s_l___d_s_s_c_o_m_m_o_n_html_ga2287bdc0f1a6bb8d7c25590cc580d26a"><div class="ttname"><a href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga2287bdc0f1a6bb8d7c25590cc580d26a">CSL_DSS_VP_INTR_SECURITYVIOLATION_MASK</a></div><div class="ttdeci">#define CSL_DSS_VP_INTR_SECURITYVIOLATION_MASK</div><div class="ttdoc">Interrupt due to security violation. </div><div class="ttdef"><b>Definition:</b> csl_dssCommon.h:163</div></div>
+<div class="ttc" id="group___c_s_l___d_s_s_c_o_m_m_o_n_html_gaa57aa7b8fc4736ff9598a0b8c5b308c6"><div class="ttname"><a href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gaa57aa7b8fc4736ff9598a0b8c5b308c6">CSL_DSS_VP_INTR_ACBIASCOUNT_MASK</a></div><div class="ttdeci">#define CSL_DSS_VP_INTR_ACBIASCOUNT_MASK</div><div class="ttdoc">AC Bias transition counter has decremented to zero. </div><div class="ttdef"><b>Definition:</b> csl_dssCommon.h:148</div></div>
+<div class="ttc" id="group___c_s_l___d_s_s_c_o_m_m_o_n_html_gaf436eb889d4490f9e0fb4b79ebeea6cb"><div class="ttname"><a href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gaf436eb889d4490f9e0fb4b79ebeea6cb">CSL_DSS_VP_INTR_SAFETYVIOLATION_REGION3_MASK</a></div><div class="ttdeci">#define CSL_DSS_VP_INTR_SAFETYVIOLATION_REGION3_MASK</div><div class="ttdoc">Interrupt due to region 3 safety violation. </div><div class="ttdef"><b>Definition:</b> csl_dssCommon.h:157</div></div>
+<div class="ttc" id="group___c_s_l___d_s_s_c_o_m_m_o_n_html_gaf396f3733114c9eb5478a5a7852fb09e"><div class="ttname"><a href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gaf396f3733114c9eb5478a5a7852fb09e">CSL_DSS_VP_INTR_SAFETYVIOLATION_REGION1_MASK</a></div><div class="ttdeci">#define CSL_DSS_VP_INTR_SAFETYVIOLATION_REGION1_MASK</div><div class="ttdoc">Interrupt due to region 1 safety violation. </div><div class="ttdef"><b>Definition:</b> csl_dssCommon.h:151</div></div>
+<div class="ttc" id="group___c_s_l___d_s_s_c_o_m_m_o_n_html_ga4b7fe7d3fbf537386925b2118337517d"><div class="ttname"><a href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga4b7fe7d3fbf537386925b2118337517d">CSL_DSS_VP_INTR_GOBITCLEAR_MASK</a></div><div class="ttdeci">#define CSL_DSS_VP_INTR_GOBITCLEAR_MASK</div><div class="ttdoc">Go bit clear interrupt for VP. </div><div class="ttdef"><b>Definition:</b> csl_dssCommon.h:166</div></div>
+<div class="ttc" id="group___c_s_l___d_s_s_c_o_m_m_o_n_html_gafd2c9bb5bce5224951f713e6a67951cb"><div class="ttname"><a href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#gafd2c9bb5bce5224951f713e6a67951cb">CSL_DSS_VP_INTR_SAFETYVIOLATION_REGION7_MASK</a></div><div class="ttdeci">#define CSL_DSS_VP_INTR_SAFETYVIOLATION_REGION7_MASK</div><div class="ttdoc">Interrupt due to region 7 safety violation. </div><div class="ttdef"><b>Definition:</b> csl_dssCommon.h:175</div></div>
+</div><!-- fragment -->
+<p>All Video Port interrupts. </p>
+
+</div>
+</div>
+<a class="anchor" id="gaa87662a09ae286e277da4b5ee2243b71"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">#define CSL_DSS_WB_PIPE_INTR_ALL_MASK</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<b>Value:</b><div class="fragment"><div class="line">(<a class="code" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga7956cca4dac339f72e3bfd028cef8aea">CSL_DSS_WB_PIPE_INTR_WBSYNC_MASK</a> | <a class="code" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1fcec556feabbf38743c1ff5ece580de">\</a></div>
+<div class="line"><a class="code" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1fcec556feabbf38743c1ff5ece580de"> CSL_DSS_WB_PIPE_INTR_SECURITYVIOLATION_MASK</a> | <a class="code" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga21c87fbab481fb6ea24b202b12610a35">\</a></div>
+<div class="line"><a class="code" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga21c87fbab481fb6ea24b202b12610a35"> CSL_DSS_WB_PIPE_INTR_FRAMEDONE_MASK</a> | <a class="code" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga49798f6dd7f9930bcde282c21197c739">\</a></div>
+<div class="line"><a class="code" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga49798f6dd7f9930bcde282c21197c739"> CSL_DSS_WB_PIPE_INTR_UNCOMPLETE_MASK</a> | <a class="code" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga9a426ebaaf7f08452b96825dff7dd6ea">\</a></div>
+<div class="line"><a class="code" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga9a426ebaaf7f08452b96825dff7dd6ea"> CSL_DSS_WB_PIPE_INTR_OVERFLOW_MASK</a>)</div>
+<div class="ttc" id="group___c_s_l___d_s_s_c_o_m_m_o_n_html_ga1fcec556feabbf38743c1ff5ece580de"><div class="ttname"><a href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1fcec556feabbf38743c1ff5ece580de">CSL_DSS_WB_PIPE_INTR_SECURITYVIOLATION_MASK</a></div><div class="ttdeci">#define CSL_DSS_WB_PIPE_INTR_SECURITYVIOLATION_MASK</div><div class="ttdoc">Interrupt due to security violation. </div><div class="ttdef"><b>Definition:</b> csl_dssCommon.h:210</div></div>
+<div class="ttc" id="group___c_s_l___d_s_s_c_o_m_m_o_n_html_ga21c87fbab481fb6ea24b202b12610a35"><div class="ttname"><a href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga21c87fbab481fb6ea24b202b12610a35">CSL_DSS_WB_PIPE_INTR_FRAMEDONE_MASK</a></div><div class="ttdeci">#define CSL_DSS_WB_PIPE_INTR_FRAMEDONE_MASK</div><div class="ttdoc">Interrupt due to write back frame completion. </div><div class="ttdef"><b>Definition:</b> csl_dssCommon.h:213</div></div>
+<div class="ttc" id="group___c_s_l___d_s_s_c_o_m_m_o_n_html_ga9a426ebaaf7f08452b96825dff7dd6ea"><div class="ttname"><a href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga9a426ebaaf7f08452b96825dff7dd6ea">CSL_DSS_WB_PIPE_INTR_OVERFLOW_MASK</a></div><div class="ttdeci">#define CSL_DSS_WB_PIPE_INTR_OVERFLOW_MASK</div><div class="ttdoc">Interrupt due to buffer overflow. </div><div class="ttdef"><b>Definition:</b> csl_dssCommon.h:219</div></div>
+<div class="ttc" id="group___c_s_l___d_s_s_c_o_m_m_o_n_html_ga49798f6dd7f9930bcde282c21197c739"><div class="ttname"><a href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga49798f6dd7f9930bcde282c21197c739">CSL_DSS_WB_PIPE_INTR_UNCOMPLETE_MASK</a></div><div class="ttdeci">#define CSL_DSS_WB_PIPE_INTR_UNCOMPLETE_MASK</div><div class="ttdoc">Interrupt due to buffer flush before full drain (Only Capture WB) </div><div class="ttdef"><b>Definition:</b> csl_dssCommon.h:216</div></div>
+<div class="ttc" id="group___c_s_l___d_s_s_c_o_m_m_o_n_html_ga7956cca4dac339f72e3bfd028cef8aea"><div class="ttname"><a href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga7956cca4dac339f72e3bfd028cef8aea">CSL_DSS_WB_PIPE_INTR_WBSYNC_MASK</a></div><div class="ttdeci">#define CSL_DSS_WB_PIPE_INTR_WBSYNC_MASK</div><div class="ttdoc">Interrupt due to completion of write back sync. </div><div class="ttdef"><b>Definition:</b> csl_dssCommon.h:207</div></div>
+</div><!-- fragment -->
+<p>All Write Back Pipe interrupts. </p>
+
+</div>
+</div>
+<h2 class="groupheader">Typedef Documentation</h2>
+<a class="anchor" id="ga1b5d2dc642484dd5b5af1cd7db50ef74"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">typedef CSL_dss_common_mRegs <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1b5d2dc642484dd5b5af1cd7db50ef74">CSL_dss_commRegs</a></td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+
+<p>DSS Common Registers. </p>
+<p>DSS7 has two identical Common blocks, hence define a generic structure to have common APIs </p>
+
+</div>
+</div>
+<h2 class="groupheader">Function Documentation</h2>
+<a class="anchor" id="gafa9009a2a94ae2222dfaaa166de1f33d"></a>
+<div class="memitem">
+<div class="memproto">
+<table class="mlabels">
+ <tr>
+ <td class="mlabels-left">
+ <table class="memname">
+ <tr>
+ <td class="memname">static void CSL_dssCbaCfgInit </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="struct_c_s_l___dss_cba_cfg.html">CSL_DssCbaCfg</a> * </td>
+ <td class="paramname"><em>cbaCfg</em></td><td>)</td>
+ <td></td>
+ </tr>
+ </table>
+ </td>
+ <td class="mlabels-right">
+<span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span> </td>
+ </tr>
+</table>
+</div><div class="memdoc">
+
+<p><a class="el" href="struct_c_s_l___dss_cba_cfg.html" title="DSS CBA Config parameters. ">CSL_DssCbaCfg</a> structure init function. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">cbaCfg</td><td>Pointer to <a class="el" href="struct_c_s_l___dss_cba_cfg.html" title="DSS CBA Config parameters. ">CSL_DssCbaCfg</a> structure</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga2f59e10e9d38932af384543d274dc90c"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">void CSL_dssClearDispcIntr </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1b5d2dc642484dd5b5af1cd7db50ef74">CSL_dss_commRegs</a> * </td>
+ <td class="paramname"><em>commRegs</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">uint32_t </td>
+ <td class="paramname"><em>intrMask</em> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td></td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+
+<p>Clear the interrupts at DSS top level. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">commRegs</td><td>Pointer to a <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1b5d2dc642484dd5b5af1cd7db50ef74" title="DSS Common Registers. ">CSL_dss_commRegs</a> structure containing the common configuration </td></tr>
+ <tr><td class="paramname">intrMask</td><td>Interrupt Mask. Refer <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#CSL_DssDispcIntrMask">CSL_DssDispcIntrMask</a> for values</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga1c2b89748e481bf4651cf4b87805177d"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">void CSL_dssClearPipeIntr </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1b5d2dc642484dd5b5af1cd7db50ef74">CSL_dss_commRegs</a> * </td>
+ <td class="paramname"><em>commRegs</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">uint32_t </td>
+ <td class="paramname"><em>vidPipeId</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">uint32_t </td>
+ <td class="paramname"><em>intrMask</em> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td></td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+
+<p>Clear the interrupts for Video Pipe. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">commRegs</td><td>Pointer to a <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1b5d2dc642484dd5b5af1cd7db50ef74" title="DSS Common Registers. ">CSL_dss_commRegs</a> structure containing the common configuration </td></tr>
+ <tr><td class="paramname">vidPipeId</td><td>Video Pipe for which interrupt should be cleared. Valid Values: CSL_DSS_VID_PIPE_ID_VID1 CSL_DSS_VID_PIPE_ID_VIDL1 CSL_DSS_VID_PIPE_ID_VID2 CSL_DSS_VID_PIPE_ID_VIDL2 </td></tr>
+ <tr><td class="paramname">intrMask</td><td>Interrupt Mask. Refer <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#CSL_DssVidPipeIntrMask">CSL_DssVidPipeIntrMask</a> for values</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga086ca7d14c9f2a75305035c512972c18"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">void CSL_dssClearVpIntr </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1b5d2dc642484dd5b5af1cd7db50ef74">CSL_dss_commRegs</a> * </td>
+ <td class="paramname"><em>commRegs</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">uint32_t </td>
+ <td class="paramname"><em>portId</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">uint32_t </td>
+ <td class="paramname"><em>intrMask</em> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td></td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+
+<p>Clear the interrupts for Video Port. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">commRegs</td><td>Pointer to a <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1b5d2dc642484dd5b5af1cd7db50ef74" title="DSS Common Registers. ">CSL_dss_commRegs</a> structure containing the common configuration </td></tr>
+ <tr><td class="paramname">portId</td><td>Video Port for which interrupt should be cleared. Valid Values: CSL_DSS_VP_ID_1 CSL_DSS_VP_ID_2 CSL_DSS_VP_ID_3 CSL_DSS_VP_ID_4 </td></tr>
+ <tr><td class="paramname">intrMask</td><td>Interrupt Mask. Refer <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#CSL_DssVpIntrMask">CSL_DssVpIntrMask</a> for values</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga1c215888b011a5cca5880679ea560f74"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">int32_t CSL_dssConnectVpToDpi </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1b5d2dc642484dd5b5af1cd7db50ef74">CSL_dss_commRegs</a> * </td>
+ <td class="paramname"><em>commRegs</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">uint32_t </td>
+ <td class="paramname"><em>portId</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">uint32_t </td>
+ <td class="paramname"><em>dpiId</em> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td></td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+
+<p>This API can be used to select the VP connection to DPI. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">commRegs</td><td>Pointer to a <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1b5d2dc642484dd5b5af1cd7db50ef74" title="DSS Common Registers. ">CSL_dss_commRegs</a> structure containing the common configuration </td></tr>
+ <tr><td class="paramname">portId</td><td>Video Port Id. Possible values are: CSL_DSS_VP_ID_2 or CSL_DSS_VP_ID_4 </td></tr>
+ <tr><td class="paramname">dpiId</td><td>DPI Id. Possible values are: CSL_DSS_DPI_ID_0 or CSL_DSS_DPI_ID_1</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>CSL_ErrType_t </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga78ae8cafecdf61459530ae0ecaee1312"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">void CSL_dssEnableDispcIntr </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1b5d2dc642484dd5b5af1cd7db50ef74">CSL_dss_commRegs</a> * </td>
+ <td class="paramname"><em>commRegs</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">uint32_t </td>
+ <td class="paramname"><em>intrMask</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">uint32_t </td>
+ <td class="paramname"><em>intrEnable</em> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td></td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+
+<p>Enable/disable the interrupts at DSS top level. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">commRegs</td><td>Pointer to a <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1b5d2dc642484dd5b5af1cd7db50ef74" title="DSS Common Registers. ">CSL_dss_commRegs</a> structure containing the common configuration </td></tr>
+ <tr><td class="paramname">intrMask</td><td>Interrupt Mask. Refer <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#CSL_DssDispcIntrMask">CSL_DssDispcIntrMask</a> for values </td></tr>
+ <tr><td class="paramname">intrEnable</td><td>Enable/Disable the interrupt TRUE: Enable interrupt FALSE: Disable interrupt</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga1d1f5ed599418de87535e92ff113dbae"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">void CSL_dssEnablePipeIntr </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1b5d2dc642484dd5b5af1cd7db50ef74">CSL_dss_commRegs</a> * </td>
+ <td class="paramname"><em>commRegs</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">uint32_t </td>
+ <td class="paramname"><em>vidPipeId</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">uint32_t </td>
+ <td class="paramname"><em>intrMask</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">uint32_t </td>
+ <td class="paramname"><em>intrEnable</em> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td></td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+
+<p>Enable/disable the interrupts for Video Pipe. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">commRegs</td><td>Pointer to a <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1b5d2dc642484dd5b5af1cd7db50ef74" title="DSS Common Registers. ">CSL_dss_commRegs</a> structure containing the common configuration </td></tr>
+ <tr><td class="paramname">vidPipeId</td><td>Video Pipe for which interrupt should be configured. Valid Values: CSL_DSS_VID_PIPE_ID_VID1 CSL_DSS_VID_PIPE_ID_VIDL1 CSL_DSS_VID_PIPE_ID_VID2 CSL_DSS_VID_PIPE_ID_VIDL2 </td></tr>
+ <tr><td class="paramname">intrMask</td><td>Interrupt Mask. Refer <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#CSL_DssVidPipeIntrMask">CSL_DssVidPipeIntrMask</a> for values </td></tr>
+ <tr><td class="paramname">intrEnable</td><td>Enable/Disable the interrupt TRUE: Enable interrupt FALSE: Disable interrupt</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="gabc7928512f14f647d32d899a9850b4ad"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">void CSL_dssEnableVpIntr </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1b5d2dc642484dd5b5af1cd7db50ef74">CSL_dss_commRegs</a> * </td>
+ <td class="paramname"><em>commRegs</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">uint32_t </td>
+ <td class="paramname"><em>portId</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">uint32_t </td>
+ <td class="paramname"><em>intrMask</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">uint32_t </td>
+ <td class="paramname"><em>intrEnable</em> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td></td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+
+<p>Enable/disable the interrupts for Video Port. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">commRegs</td><td>Pointer to a <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1b5d2dc642484dd5b5af1cd7db50ef74" title="DSS Common Registers. ">CSL_dss_commRegs</a> structure containing the common configuration </td></tr>
+ <tr><td class="paramname">portId</td><td>Video Port for which interrupt should be configured. Valid Values: CSL_DSS_VP_ID_1 CSL_DSS_VP_ID_2 CSL_DSS_VP_ID_3 CSL_DSS_VP_ID_4 </td></tr>
+ <tr><td class="paramname">intrMask</td><td>Interrupt Mask. Refer <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#CSL_DssVpIntrMask">CSL_DssVpIntrMask</a> for values </td></tr>
+ <tr><td class="paramname">intrEnable</td><td>Enable/Disable the interrupt TRUE: Enable interrupt FALSE: Disable interrupt</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga196052d031e6e46bc99f4631218d2da7"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t CSL_dssGetDispcIntrStatus </td>
+ <td>(</td>
+ <td class="paramtype">const <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1b5d2dc642484dd5b5af1cd7db50ef74">CSL_dss_commRegs</a> * </td>
+ <td class="paramname"><em>commRegs</em></td><td>)</td>
+ <td></td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+
+<p>Get the top level interrupt status of DSS. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">commRegs</td><td>Pointer to a <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1b5d2dc642484dd5b5af1cd7db50ef74" title="DSS Common Registers. ">CSL_dss_commRegs</a> structure containing the common configuration</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>Interrupt status </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="gab25aea830bb6567a67be6018fbce58e2"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t CSL_dssGetPipeIntrStatus </td>
+ <td>(</td>
+ <td class="paramtype">const <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1b5d2dc642484dd5b5af1cd7db50ef74">CSL_dss_commRegs</a> * </td>
+ <td class="paramname"><em>commRegs</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">uint32_t </td>
+ <td class="paramname"><em>vidPipeId</em> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td></td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+
+<p>Get the interrupt status of Video Pipe. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">commRegs</td><td>Pointer to a <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1b5d2dc642484dd5b5af1cd7db50ef74" title="DSS Common Registers. ">CSL_dss_commRegs</a> structure containing the common configuration </td></tr>
+ <tr><td class="paramname">vidPipeId</td><td>Video Pipe for which interrupt should be cleared. Valid Values: CSL_DSS_VID_PIPE_ID_VID1 CSL_DSS_VID_PIPE_ID_VIDL1 CSL_DSS_VID_PIPE_ID_VID2 CSL_DSS_VID_PIPE_ID_VIDL2 </td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>Interrupt status </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga7202424e4a3404aaf894e294be0a1f7d"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t CSL_dssGetVpIntrStatus </td>
+ <td>(</td>
+ <td class="paramtype">const <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1b5d2dc642484dd5b5af1cd7db50ef74">CSL_dss_commRegs</a> * </td>
+ <td class="paramname"><em>commRegs</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">uint32_t </td>
+ <td class="paramname"><em>portId</em> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td></td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+
+<p>Get the interrupt status of Video Port. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">commRegs</td><td>Pointer to a <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1b5d2dc642484dd5b5af1cd7db50ef74" title="DSS Common Registers. ">CSL_dss_commRegs</a> structure containing the common configuration </td></tr>
+ <tr><td class="paramname">portId</td><td>Video Port for which interrupt should be cleared. Valid Values: CSL_DSS_VP_ID_1 CSL_DSS_VP_ID_2 CSL_DSS_VP_ID_3 CSL_DSS_VP_ID_4 </td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>Interrupt status </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga67eb3b87f230f3d3598ff1ea3c8ccbbe"></a>
+<div class="memitem">
+<div class="memproto">
+<table class="mlabels">
+ <tr>
+ <td class="mlabels-left">
+ <table class="memname">
+ <tr>
+ <td class="memname">static void CSL_dssGlobalMFlagCfgInit </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="struct_c_s_l___dss_global_m_flag_cfg.html">CSL_DssGlobalMFlagCfg</a> * </td>
+ <td class="paramname"><em>mflagCfg</em></td><td>)</td>
+ <td></td>
+ </tr>
+ </table>
+ </td>
+ <td class="mlabels-right">
+<span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span> </td>
+ </tr>
+</table>
+</div><div class="memdoc">
+
+<p><a class="el" href="struct_c_s_l___dss_global_m_flag_cfg.html" title="DSS Global MFLAG Config parameters. ">CSL_DssGlobalMFlagCfg</a> structure init function. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">mflagCfg</td><td>Pointer to <a class="el" href="struct_c_s_l___dss_global_m_flag_cfg.html" title="DSS Global MFLAG Config parameters. ">CSL_DssGlobalMFlagCfg</a> structure</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="gad3490bc78c9441400a4a77c933006f6c"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">void CSL_dssGlobalVpEnable </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1b5d2dc642484dd5b5af1cd7db50ef74">CSL_dss_commRegs</a> * </td>
+ <td class="paramname"><em>commRegs</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">uint32_t </td>
+ <td class="paramname"><em>portIdMask</em> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td></td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+
+<p>Enable the global VP enable bit. This allows setting multiple outputs synchronously. The 'OR' result of different masks can be used as input parameter. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">commRegs</td><td>Pointer to a <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1b5d2dc642484dd5b5af1cd7db50ef74" title="DSS Common Registers. ">CSL_dss_commRegs</a> structure containing the common configuration </td></tr>
+ <tr><td class="paramname">portIdMask</td><td>Video Port for which enable bit should be set. Refer <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#CSL_DssVpIdMask">CSL_DssVpIdMask</a> for details.</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga6c62a23a768c0ce357db64365ebdc0b0"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">void CSL_dssGlobalVpGoBitEnable </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1b5d2dc642484dd5b5af1cd7db50ef74">CSL_dss_commRegs</a> * </td>
+ <td class="paramname"><em>commRegs</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">uint32_t </td>
+ <td class="paramname"><em>portIdMask</em> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td></td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+
+<p>Enable the global VP go bit. This allows setting multiple outputs synchronously. The 'OR' result of different masks can be used as input parameter. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">commRegs</td><td>Pointer to a <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1b5d2dc642484dd5b5af1cd7db50ef74" title="DSS Common Registers. ">CSL_dss_commRegs</a> structure containing the common configuration </td></tr>
+ <tr><td class="paramname">portIdMask</td><td>Video Port for which go bit should be set. Refer <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#CSL_DssVpIdMask">CSL_DssVpIdMask</a> for details.</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga567b2f823b70e843ceb9c4ca8c501cae"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">void CSL_dssModuleReset </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1b5d2dc642484dd5b5af1cd7db50ef74">CSL_dss_commRegs</a> * </td>
+ <td class="paramname"><em>commRegs</em></td><td>)</td>
+ <td></td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+
+<p>Reset the DSS Module. Application should make sure Video Ports are disabled before calling this API. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">commRegs</td><td>Pointer to a <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1b5d2dc642484dd5b5af1cd7db50ef74" title="DSS Common Registers. ">CSL_dss_commRegs</a> structure containing the common configuration</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga1ce4591b123f52bf6e6cc00a485fcd38"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">void CSL_dssSetCbaConfig </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1b5d2dc642484dd5b5af1cd7db50ef74">CSL_dss_commRegs</a> * </td>
+ <td class="paramname"><em>commRegs</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">const <a class="el" href="struct_c_s_l___dss_cba_cfg.html">CSL_DssCbaCfg</a> * </td>
+ <td class="paramname"><em>cbaCfg</em> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td></td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+
+<p>Set the CBA configuration. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">commRegs</td><td>Pointer to a <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1b5d2dc642484dd5b5af1cd7db50ef74" title="DSS Common Registers. ">CSL_dss_commRegs</a> structure containing the common configuration </td></tr>
+ <tr><td class="paramname">cbaCfg</td><td>Pointer to <a class="el" href="struct_c_s_l___dss_cba_cfg.html" title="DSS CBA Config parameters. ">CSL_DssCbaCfg</a> structure. This parameter should not be NULL</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga51649681f3f478ab1c44d97aa3ed8323"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">void CSL_dssSetGlobalMflagConfig </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1b5d2dc642484dd5b5af1cd7db50ef74">CSL_dss_commRegs</a> * </td>
+ <td class="paramname"><em>commRegs</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">const <a class="el" href="struct_c_s_l___dss_global_m_flag_cfg.html">CSL_DssGlobalMFlagCfg</a> * </td>
+ <td class="paramname"><em>mflagCfg</em> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td></td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+
+<p>Set the global MFLAG configuration. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">commRegs</td><td>Pointer to a <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#ga1b5d2dc642484dd5b5af1cd7db50ef74" title="DSS Common Registers. ">CSL_dss_commRegs</a> structure containing the common configuration </td></tr>
+ <tr><td class="paramname">mflagCfg</td><td>Pointer to <a class="el" href="struct_c_s_l___dss_global_m_flag_cfg.html" title="DSS Global MFLAG Config parameters. ">CSL_DssGlobalMFlagCfg</a> structure. This parameter should not be NULL</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None </dd></dl>
+
+</div>
+</div>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
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+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="nested-classes"></a>
+Data Structures</h2></td></tr>
+<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_overlay_cfg.html">CSL_DssOverlayCfg</a></td></tr>
+<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">Configuration for DSS Overlay. <a href="struct_c_s_l___dss_overlay_cfg.html#details">More...</a><br/></td></tr>
+<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_overlay_layer_cfg.html">CSL_DssOverlayLayerCfg</a></td></tr>
+<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">Configuration for selecting overlay input layers. <a href="struct_c_s_l___dss_overlay_layer_cfg.html#details">More...</a><br/></td></tr>
+<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_overlay_pipe_pos_cfg.html">CSL_DssOverlayPipePosCfg</a></td></tr>
+<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">Video Pipe Position Configuration in Overlay. <a href="struct_c_s_l___dss_overlay_pipe_pos_cfg.html#details">More...</a><br/></td></tr>
+<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="typedef-members"></a>
+Typedefs</h2></td></tr>
+<tr class="memitem:ga835adb8a42f16beefbfb5440b9dede63"><td class="memItemLeft" align="right" valign="top">typedef CSL_dss_ovr1Regs </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#ga835adb8a42f16beefbfb5440b9dede63">CSL_dss_overlayRegs</a></td></tr>
+<tr class="memdesc:ga835adb8a42f16beefbfb5440b9dede63"><td class="mdescLeft"> </td><td class="mdescRight">DSS Overlay Registers. <a href="#ga835adb8a42f16beefbfb5440b9dede63">More...</a><br/></td></tr>
+<tr class="separator:ga835adb8a42f16beefbfb5440b9dede63"><td class="memSeparator" colspan="2"> </td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a>
+Functions</h2></td></tr>
+<tr class="memitem:ga03a77e67fa911acc5e905faafe06a7cc"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#ga03a77e67fa911acc5e905faafe06a7cc">CSL_dssOverlaySetConfig</a> (<a class="el" href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#ga835adb8a42f16beefbfb5440b9dede63">CSL_dss_overlayRegs</a> *overlayRegs, const <a class="el" href="struct_c_s_l___dss_overlay_cfg.html">CSL_DssOverlayCfg</a> *overlayCfg)</td></tr>
+<tr class="memdesc:ga03a77e67fa911acc5e905faafe06a7cc"><td class="mdescLeft"> </td><td class="mdescRight">Configure the Overlay Params. <a href="#ga03a77e67fa911acc5e905faafe06a7cc">More...</a><br/></td></tr>
+<tr class="separator:ga03a77e67fa911acc5e905faafe06a7cc"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gad36724322f426d4022c944b5fc53f3fd"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#gad36724322f426d4022c944b5fc53f3fd">CSL_dssOverlayColorBarEnable</a> (<a class="el" href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#ga835adb8a42f16beefbfb5440b9dede63">CSL_dss_overlayRegs</a> *overlayRegs, uint32_t enable)</td></tr>
+<tr class="memdesc:gad36724322f426d4022c944b5fc53f3fd"><td class="mdescLeft"> </td><td class="mdescRight">Enable the Color Bar in DSS Overlay. <a href="#gad36724322f426d4022c944b5fc53f3fd">More...</a><br/></td></tr>
+<tr class="separator:gad36724322f426d4022c944b5fc53f3fd"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga0854ef7eebe8ec3dabd739cda8a0a87b"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#ga0854ef7eebe8ec3dabd739cda8a0a87b">CSL_dssOverlaySetLayerConfig</a> (<a class="el" href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#ga835adb8a42f16beefbfb5440b9dede63">CSL_dss_overlayRegs</a> *overlayRegs, const <a class="el" href="struct_c_s_l___dss_overlay_layer_cfg.html">CSL_DssOverlayLayerCfg</a> *layerCfg)</td></tr>
+<tr class="memdesc:ga0854ef7eebe8ec3dabd739cda8a0a87b"><td class="mdescLeft"> </td><td class="mdescRight">Configure the Overlay input selection. <a href="#ga0854ef7eebe8ec3dabd739cda8a0a87b">More...</a><br/></td></tr>
+<tr class="separator:ga0854ef7eebe8ec3dabd739cda8a0a87b"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga04705e269d2be5aa01508e3f5dafdf7c"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#ga04705e269d2be5aa01508e3f5dafdf7c">CSL_dssOverlaySetPipePosConfig</a> (<a class="el" href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#ga835adb8a42f16beefbfb5440b9dede63">CSL_dss_overlayRegs</a> *overlayRegs, const <a class="el" href="struct_c_s_l___dss_overlay_pipe_pos_cfg.html">CSL_DssOverlayPipePosCfg</a> *pipePosCfg, uint32_t layerNum)</td></tr>
+<tr class="memdesc:ga04705e269d2be5aa01508e3f5dafdf7c"><td class="mdescLeft"> </td><td class="mdescRight">Configure the Video Pipe Position in Overlay. <a href="#ga04705e269d2be5aa01508e3f5dafdf7c">More...</a><br/></td></tr>
+<tr class="separator:ga04705e269d2be5aa01508e3f5dafdf7c"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gae88aaba46e12dfb2f72c93691ea14c99"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#gae88aaba46e12dfb2f72c93691ea14c99">CSL_dssOverlayGetEnabledPipeLayerNum</a> (const <a class="el" href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#ga835adb8a42f16beefbfb5440b9dede63">CSL_dss_overlayRegs</a> *overlayRegs, uint32_t pipeId)</td></tr>
+<tr class="memdesc:gae88aaba46e12dfb2f72c93691ea14c99"><td class="mdescLeft"> </td><td class="mdescRight">Get the layer number where a particular Video Pipe is connected. <a href="#gae88aaba46e12dfb2f72c93691ea14c99">More...</a><br/></td></tr>
+<tr class="separator:gae88aaba46e12dfb2f72c93691ea14c99"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga5f9f1191f5d62fa0747616ae87e3cc65"><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#ga5f9f1191f5d62fa0747616ae87e3cc65">CSL_dssOverlayCfgInit</a> (<a class="el" href="struct_c_s_l___dss_overlay_cfg.html">CSL_DssOverlayCfg</a> *overlayCfg)</td></tr>
+<tr class="memdesc:ga5f9f1191f5d62fa0747616ae87e3cc65"><td class="mdescLeft"> </td><td class="mdescRight"><a class="el" href="struct_c_s_l___dss_overlay_cfg.html" title="Configuration for DSS Overlay. ">CSL_DssOverlayCfg</a> structure init function. <a href="#ga5f9f1191f5d62fa0747616ae87e3cc65">More...</a><br/></td></tr>
+<tr class="separator:ga5f9f1191f5d62fa0747616ae87e3cc65"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gae7481e9db942be0537425939b6387a22"><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#gae7481e9db942be0537425939b6387a22">CSL_dssOverlayLayerCfgInit</a> (<a class="el" href="struct_c_s_l___dss_overlay_layer_cfg.html">CSL_DssOverlayLayerCfg</a> *layerCfg)</td></tr>
+<tr class="memdesc:gae7481e9db942be0537425939b6387a22"><td class="mdescLeft"> </td><td class="mdescRight"><a class="el" href="struct_c_s_l___dss_overlay_layer_cfg.html" title="Configuration for selecting overlay input layers. ">CSL_DssOverlayLayerCfg</a> structure init function. <a href="#gae7481e9db942be0537425939b6387a22">More...</a><br/></td></tr>
+<tr class="separator:gae7481e9db942be0537425939b6387a22"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga1c8500dcdd91d052cfc9c01d4bed6e30"><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#ga1c8500dcdd91d052cfc9c01d4bed6e30">CSL_dssOverlayPipePosCfgInit</a> (<a class="el" href="struct_c_s_l___dss_overlay_pipe_pos_cfg.html">CSL_DssOverlayPipePosCfg</a> *pipePosCfg)</td></tr>
+<tr class="memdesc:ga1c8500dcdd91d052cfc9c01d4bed6e30"><td class="mdescLeft"> </td><td class="mdescRight"><a class="el" href="struct_c_s_l___dss_overlay_pipe_pos_cfg.html" title="Video Pipe Position Configuration in Overlay. ">CSL_DssOverlayPipePosCfg</a> structure init function. <a href="#ga1c8500dcdd91d052cfc9c01d4bed6e30">More...</a><br/></td></tr>
+<tr class="separator:ga1c8500dcdd91d052cfc9c01d4bed6e30"><td class="memSeparator" colspan="2"> </td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
+DSS Overlay Transparency Color Key Selection</h2></td></tr>
+<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrpb8f6a68a5488f323fc033454d576f6de"></a><a class="anchor" id="CSL_DssOverlayTransColor"></a></p>
+</td></tr>
+<tr class="memitem:ga340c7a53b58c9fed267c3164ec0a03c9"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga340c7a53b58c9fed267c3164ec0a03c9"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#ga340c7a53b58c9fed267c3164ec0a03c9">CSL_DSS_OVERLAY_TRANS_COLOR_DEST</a>   ((uint32_t) CSL_DSS_OVR1_CONFIG_TCKLCDSELECTION_VAL_GDTK)</td></tr>
+<tr class="memdesc:ga340c7a53b58c9fed267c3164ec0a03c9"><td class="mdescLeft"> </td><td class="mdescRight">Destination transparency color key selected. <br/></td></tr>
+<tr class="separator:ga340c7a53b58c9fed267c3164ec0a03c9"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga164f53537368dff35827675dfda8cf12"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga164f53537368dff35827675dfda8cf12"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#ga164f53537368dff35827675dfda8cf12">CSL_DSS_OVERLAY_TRANS_COLOR_SRC</a>   ((uint32_t) CSL_DSS_OVR1_CONFIG_TCKLCDSELECTION_VAL_VSTK)</td></tr>
+<tr class="memdesc:ga164f53537368dff35827675dfda8cf12"><td class="mdescLeft"> </td><td class="mdescRight">Source transparency color key selected. <br/></td></tr>
+<tr class="separator:ga164f53537368dff35827675dfda8cf12"><td class="memSeparator" colspan="2"> </td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
+DSS Overlay Layer Number</h2></td></tr>
+<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrp518944b3fcab2db6c80b235c81d7efc6"></a><a class="anchor" id="CSL_DssOverlayLayerNum"></a></p>
+</td></tr>
+<tr class="memitem:ga2488889aa0b927be4a00ec57b8b75f70"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga2488889aa0b927be4a00ec57b8b75f70"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#ga2488889aa0b927be4a00ec57b8b75f70">CSL_DSS_OVERLAY_LAYER_NUM_0</a>   ((uint32_t) 0x0U)</td></tr>
+<tr class="memdesc:ga2488889aa0b927be4a00ec57b8b75f70"><td class="mdescLeft"> </td><td class="mdescRight">Overlay Layer 0. <br/></td></tr>
+<tr class="separator:ga2488889aa0b927be4a00ec57b8b75f70"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gabe9d38d2a4ef636da3b3a261cbb94f71"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gabe9d38d2a4ef636da3b3a261cbb94f71"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#gabe9d38d2a4ef636da3b3a261cbb94f71">CSL_DSS_OVERLAY_LAYER_NUM_1</a>   ((uint32_t) 0x1U)</td></tr>
+<tr class="memdesc:gabe9d38d2a4ef636da3b3a261cbb94f71"><td class="mdescLeft"> </td><td class="mdescRight">Overlay Layer 1. <br/></td></tr>
+<tr class="separator:gabe9d38d2a4ef636da3b3a261cbb94f71"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga97d71d9f152602cd81c45e7cdfa3a92d"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga97d71d9f152602cd81c45e7cdfa3a92d"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#ga97d71d9f152602cd81c45e7cdfa3a92d">CSL_DSS_OVERLAY_LAYER_NUM_2</a>   ((uint32_t) 0x2U)</td></tr>
+<tr class="memdesc:ga97d71d9f152602cd81c45e7cdfa3a92d"><td class="mdescLeft"> </td><td class="mdescRight">Overlay Layer 2. <br/></td></tr>
+<tr class="separator:ga97d71d9f152602cd81c45e7cdfa3a92d"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga4f0066fbe34c973483392a7128eb598a"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga4f0066fbe34c973483392a7128eb598a"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#ga4f0066fbe34c973483392a7128eb598a">CSL_DSS_OVERLAY_LAYER_NUM_3</a>   ((uint32_t) 0x3U)</td></tr>
+<tr class="memdesc:ga4f0066fbe34c973483392a7128eb598a"><td class="mdescLeft"> </td><td class="mdescRight">Overlay Layer 3. <br/></td></tr>
+<tr class="separator:ga4f0066fbe34c973483392a7128eb598a"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga2a682ed470d58605922ee2106033a5f8"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga2a682ed470d58605922ee2106033a5f8"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#ga2a682ed470d58605922ee2106033a5f8">CSL_DSS_OVERLAY_LAYER_MAX</a>   ((uint32_t) 0x4U)</td></tr>
+<tr class="memdesc:ga2a682ed470d58605922ee2106033a5f8"><td class="mdescLeft"> </td><td class="mdescRight">Maximum overlay layers. <br/></td></tr>
+<tr class="separator:ga2a682ed470d58605922ee2106033a5f8"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gae0d0be4608934fba2afa072b6716220a"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gae0d0be4608934fba2afa072b6716220a"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#gae0d0be4608934fba2afa072b6716220a">CSL_DSS_OVERLAY_LAYER_INVALID</a>   ((uint32_t) 0xFFU)</td></tr>
+<tr class="memdesc:gae0d0be4608934fba2afa072b6716220a"><td class="mdescLeft"> </td><td class="mdescRight">Invalid Overlay Layer. <br/></td></tr>
+<tr class="separator:gae0d0be4608934fba2afa072b6716220a"><td class="memSeparator" colspan="2"> </td></tr>
+</table>
+<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
+<h2 class="groupheader">Typedef Documentation</h2>
+<a class="anchor" id="ga835adb8a42f16beefbfb5440b9dede63"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">typedef CSL_dss_ovr1Regs <a class="el" href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#ga835adb8a42f16beefbfb5440b9dede63">CSL_dss_overlayRegs</a></td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+
+<p>DSS Overlay Registers. </p>
+<p>DSS7 UL has two identical Overlay blocks, hence define a generic structure to have common APIs </p>
+
+</div>
+</div>
+<h2 class="groupheader">Function Documentation</h2>
+<a class="anchor" id="ga5f9f1191f5d62fa0747616ae87e3cc65"></a>
+<div class="memitem">
+<div class="memproto">
+<table class="mlabels">
+ <tr>
+ <td class="mlabels-left">
+ <table class="memname">
+ <tr>
+ <td class="memname">static void CSL_dssOverlayCfgInit </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="struct_c_s_l___dss_overlay_cfg.html">CSL_DssOverlayCfg</a> * </td>
+ <td class="paramname"><em>overlayCfg</em></td><td>)</td>
+ <td></td>
+ </tr>
+ </table>
+ </td>
+ <td class="mlabels-right">
+<span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span> </td>
+ </tr>
+</table>
+</div><div class="memdoc">
+
+<p><a class="el" href="struct_c_s_l___dss_overlay_cfg.html" title="Configuration for DSS Overlay. ">CSL_DssOverlayCfg</a> structure init function. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">overlayCfg</td><td>Pointer to <a class="el" href="struct_c_s_l___dss_overlay_cfg.html" title="Configuration for DSS Overlay. ">CSL_DssOverlayCfg</a> structure</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="gad36724322f426d4022c944b5fc53f3fd"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">void CSL_dssOverlayColorBarEnable </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#ga835adb8a42f16beefbfb5440b9dede63">CSL_dss_overlayRegs</a> * </td>
+ <td class="paramname"><em>overlayRegs</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">uint32_t </td>
+ <td class="paramname"><em>enable</em> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td></td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+
+<p>Enable the Color Bar in DSS Overlay. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">overlayRegs</td><td>Pointer to a <a class="el" href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#ga835adb8a42f16beefbfb5440b9dede63" title="DSS Overlay Registers. ">CSL_dss_overlayRegs</a> structure containing the overlay configuration </td></tr>
+ <tr><td class="paramname">enable</td><td>Enable or disable the color bar</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="gae88aaba46e12dfb2f72c93691ea14c99"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t CSL_dssOverlayGetEnabledPipeLayerNum </td>
+ <td>(</td>
+ <td class="paramtype">const <a class="el" href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#ga835adb8a42f16beefbfb5440b9dede63">CSL_dss_overlayRegs</a> * </td>
+ <td class="paramname"><em>overlayRegs</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">uint32_t </td>
+ <td class="paramname"><em>pipeId</em> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td></td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+
+<p>Get the layer number where a particular Video Pipe is connected. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">overlayRegs</td><td>Pointer to a <a class="el" href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#ga835adb8a42f16beefbfb5440b9dede63" title="DSS Overlay Registers. ">CSL_dss_overlayRegs</a> structure containing the overlay configuration </td></tr>
+ <tr><td class="paramname">pipeId</td><td>Pipe Id. Refer to <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#CSL_DssVidPipeId">CSL_DssVidPipeId</a> for values</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd><a class="el" href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#CSL_DssOverlayLayerNum">CSL_DssOverlayLayerNum</a> Layer Number to which pipe is connected. API returns CSL_DSS_OVERLAY_LAYER_INVALID if pipe is not connected to any overlay layer </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="gae7481e9db942be0537425939b6387a22"></a>
+<div class="memitem">
+<div class="memproto">
+<table class="mlabels">
+ <tr>
+ <td class="mlabels-left">
+ <table class="memname">
+ <tr>
+ <td class="memname">static void CSL_dssOverlayLayerCfgInit </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="struct_c_s_l___dss_overlay_layer_cfg.html">CSL_DssOverlayLayerCfg</a> * </td>
+ <td class="paramname"><em>layerCfg</em></td><td>)</td>
+ <td></td>
+ </tr>
+ </table>
+ </td>
+ <td class="mlabels-right">
+<span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span> </td>
+ </tr>
+</table>
+</div><div class="memdoc">
+
+<p><a class="el" href="struct_c_s_l___dss_overlay_layer_cfg.html" title="Configuration for selecting overlay input layers. ">CSL_DssOverlayLayerCfg</a> structure init function. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">layerCfg</td><td>Pointer to <a class="el" href="struct_c_s_l___dss_overlay_layer_cfg.html" title="Configuration for selecting overlay input layers. ">CSL_DssOverlayLayerCfg</a> structure</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga1c8500dcdd91d052cfc9c01d4bed6e30"></a>
+<div class="memitem">
+<div class="memproto">
+<table class="mlabels">
+ <tr>
+ <td class="mlabels-left">
+ <table class="memname">
+ <tr>
+ <td class="memname">static void CSL_dssOverlayPipePosCfgInit </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="struct_c_s_l___dss_overlay_pipe_pos_cfg.html">CSL_DssOverlayPipePosCfg</a> * </td>
+ <td class="paramname"><em>pipePosCfg</em></td><td>)</td>
+ <td></td>
+ </tr>
+ </table>
+ </td>
+ <td class="mlabels-right">
+<span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span> </td>
+ </tr>
+</table>
+</div><div class="memdoc">
+
+<p><a class="el" href="struct_c_s_l___dss_overlay_pipe_pos_cfg.html" title="Video Pipe Position Configuration in Overlay. ">CSL_DssOverlayPipePosCfg</a> structure init function. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">pipePosCfg</td><td>Pointer to <a class="el" href="struct_c_s_l___dss_overlay_pipe_pos_cfg.html" title="Video Pipe Position Configuration in Overlay. ">CSL_DssOverlayPipePosCfg</a> structure</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga03a77e67fa911acc5e905faafe06a7cc"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">void CSL_dssOverlaySetConfig </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#ga835adb8a42f16beefbfb5440b9dede63">CSL_dss_overlayRegs</a> * </td>
+ <td class="paramname"><em>overlayRegs</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">const <a class="el" href="struct_c_s_l___dss_overlay_cfg.html">CSL_DssOverlayCfg</a> * </td>
+ <td class="paramname"><em>overlayCfg</em> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td></td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+
+<p>Configure the Overlay Params. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">overlayRegs</td><td>Pointer to a <a class="el" href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#ga835adb8a42f16beefbfb5440b9dede63" title="DSS Overlay Registers. ">CSL_dss_overlayRegs</a> structure containing the overlay configuration </td></tr>
+ <tr><td class="paramname">overlayCfg</td><td>Pointer to the <a class="el" href="struct_c_s_l___dss_overlay_cfg.html" title="Configuration for DSS Overlay. ">CSL_DssOverlayCfg</a> structure. This parameter should not be NULL</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga0854ef7eebe8ec3dabd739cda8a0a87b"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">void CSL_dssOverlaySetLayerConfig </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#ga835adb8a42f16beefbfb5440b9dede63">CSL_dss_overlayRegs</a> * </td>
+ <td class="paramname"><em>overlayRegs</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">const <a class="el" href="struct_c_s_l___dss_overlay_layer_cfg.html">CSL_DssOverlayLayerCfg</a> * </td>
+ <td class="paramname"><em>layerCfg</em> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td></td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+
+<p>Configure the Overlay input selection. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">overlayRegs</td><td>Pointer to a <a class="el" href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#ga835adb8a42f16beefbfb5440b9dede63" title="DSS Overlay Registers. ">CSL_dss_overlayRegs</a> structure containing the overlay configuration </td></tr>
+ <tr><td class="paramname">layerCfg</td><td>Pointer to <a class="el" href="struct_c_s_l___dss_overlay_layer_cfg.html" title="Configuration for selecting overlay input layers. ">CSL_DssOverlayLayerCfg</a> structure. This parameter should not be NULL</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga04705e269d2be5aa01508e3f5dafdf7c"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">void CSL_dssOverlaySetPipePosConfig </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#ga835adb8a42f16beefbfb5440b9dede63">CSL_dss_overlayRegs</a> * </td>
+ <td class="paramname"><em>overlayRegs</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">const <a class="el" href="struct_c_s_l___dss_overlay_pipe_pos_cfg.html">CSL_DssOverlayPipePosCfg</a> * </td>
+ <td class="paramname"><em>pipePosCfg</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">uint32_t </td>
+ <td class="paramname"><em>layerNum</em> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td></td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+
+<p>Configure the Video Pipe Position in Overlay. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">overlayRegs</td><td>Pointer to a <a class="el" href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#ga835adb8a42f16beefbfb5440b9dede63" title="DSS Overlay Registers. ">CSL_dss_overlayRegs</a> structure containing the overlay configuration </td></tr>
+ <tr><td class="paramname">pipePosCfg</td><td>Pointer to <a class="el" href="struct_c_s_l___dss_overlay_pipe_pos_cfg.html" title="Video Pipe Position Configuration in Overlay. ">CSL_DssOverlayPipePosCfg</a> structure. This parameter should not be NULL </td></tr>
+ <tr><td class="paramname">layerNum</td><td>Layer Number</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None </dd></dl>
+
+</div>
+</div>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/group___c_s_l___d_s_s_t_o_p.html b/packages/ti/drv/dss/docs/doxygen/html/group___c_s_l___d_s_s_t_o_p.html
--- /dev/null
@@ -0,0 +1,468 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Top Level CSL FL</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
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+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="files.html"><span>Files</span></a></li>
+ </ul>
+ </div>
+</div><!-- top -->
+<div class="header">
+ <div class="summary">
+<a href="#files">Files</a> |
+<a href="#nested-classes">Data Structures</a> |
+<a href="#define-members">Macros</a> |
+<a href="#func-members">Functions</a> </div>
+ <div class="headertitle">
+<div class="title">Top Level CSL FL<div class="ingroups"><a class="el" href="group___c_s_l___d_s_s.html">DSS</a></div></div> </div>
+</div><!--header-->
+<div class="contents">
+<table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="files"></a>
+Files</h2></td></tr>
+<tr class="memitem:csl__dss_top_8h"><td class="memItemLeft" align="right" valign="top">file  </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__dss_top_8h.html">csl_dssTop.h</a></td></tr>
+<tr class="memdesc:csl__dss_top_8h"><td class="mdescLeft"> </td><td class="mdescRight">DSS Top CSL FL interface file. <br/></td></tr>
+<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="nested-classes"></a>
+Data Structures</h2></td></tr>
+<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_csc_coeff.html">CSL_DssCscCoeff</a></td></tr>
+<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">Structure containing coefficients for Color Space Conversion. <a href="struct_c_s_l___dss_csc_coeff.html#details">More...</a><br/></td></tr>
+<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_safety_chk_cfg.html">CSL_DssSafetyChkCfg</a></td></tr>
+<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">Configuration for doing safety checks. <a href="struct_c_s_l___dss_safety_chk_cfg.html#details">More...</a><br/></td></tr>
+<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
+Macros</h2></td></tr>
+<tr class="memitem:gac8a30c5680379b12128e75859e9f2312"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gac8a30c5680379b12128e75859e9f2312"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gac8a30c5680379b12128e75859e9f2312">CSL_DSS_NUM_LUT_ENTRIES</a>   ((uint32_t) 256U)</td></tr>
+<tr class="memdesc:gac8a30c5680379b12128e75859e9f2312"><td class="mdescLeft"> </td><td class="mdescRight">Number of entries for CLUT/Gamma Correction. <br/></td></tr>
+<tr class="separator:gac8a30c5680379b12128e75859e9f2312"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gaa7973f4d3301c7360cdbcc6f60c6e8fb"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaa7973f4d3301c7360cdbcc6f60c6e8fb"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gaa7973f4d3301c7360cdbcc6f60c6e8fb">CSL_DSS_MODULE_INVALID</a>   ((uint32_t) 0xFFU)</td></tr>
+<tr class="memdesc:gaa7973f4d3301c7360cdbcc6f60c6e8fb"><td class="mdescLeft"> </td><td class="mdescRight">Invalid Module Id for DSS modules. <br/></td></tr>
+<tr class="separator:gaa7973f4d3301c7360cdbcc6f60c6e8fb"><td class="memSeparator" colspan="2"> </td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a>
+Functions</h2></td></tr>
+<tr class="memitem:ga09a24eab792b00629e4b510d36a326a8"><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga09a24eab792b00629e4b510d36a326a8">CSL_dssCscCoeffInit</a> (<a class="el" href="struct_c_s_l___dss_csc_coeff.html">CSL_DssCscCoeff</a> *cscCoeff)</td></tr>
+<tr class="memdesc:ga09a24eab792b00629e4b510d36a326a8"><td class="mdescLeft"> </td><td class="mdescRight"><a class="el" href="struct_c_s_l___dss_csc_coeff.html" title="Structure containing coefficients for Color Space Conversion. ">CSL_DssCscCoeff</a> structure init function. <a href="#ga09a24eab792b00629e4b510d36a326a8">More...</a><br/></td></tr>
+<tr class="separator:ga09a24eab792b00629e4b510d36a326a8"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga0eba2c12170b846778eecb3eeb5a9a46"><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga0eba2c12170b846778eecb3eeb5a9a46">CSL_dssSafetyChkCfgInit</a> (<a class="el" href="struct_c_s_l___dss_safety_chk_cfg.html">CSL_DssSafetyChkCfg</a> *safetyCfg)</td></tr>
+<tr class="memdesc:ga0eba2c12170b846778eecb3eeb5a9a46"><td class="mdescLeft"> </td><td class="mdescRight"><a class="el" href="struct_c_s_l___dss_safety_chk_cfg.html" title="Configuration for doing safety checks. ">CSL_DssSafetyChkCfg</a> structure init function. <a href="#ga0eba2c12170b846778eecb3eeb5a9a46">More...</a><br/></td></tr>
+<tr class="separator:ga0eba2c12170b846778eecb3eeb5a9a46"><td class="memSeparator" colspan="2"> </td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
+DSS Video Pipeline Type</h2></td></tr>
+<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrp43c87426969e26d23a5da78eae1d6dc3"></a>To distinguish between VID (with scaler) and VIDL (without scaler)</p>
+<p><a class="anchor" id="CSL_DssVidPipeType"></a></p>
+</td></tr>
+<tr class="memitem:gae0a57704e2a39702c1d1ac1a861ead86"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gae0a57704e2a39702c1d1ac1a861ead86"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gae0a57704e2a39702c1d1ac1a861ead86">CSL_DSS_VID_PIPE_TYPE_VID</a>   ((uint32_t) 0x0)</td></tr>
+<tr class="memdesc:gae0a57704e2a39702c1d1ac1a861ead86"><td class="mdescLeft"> </td><td class="mdescRight">Video Pipe is of type VID. <br/></td></tr>
+<tr class="separator:gae0a57704e2a39702c1d1ac1a861ead86"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gab3801fb3aa15ef1b184da3fc2f9ea9ad"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gab3801fb3aa15ef1b184da3fc2f9ea9ad"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gab3801fb3aa15ef1b184da3fc2f9ea9ad">CSL_DSS_VID_PIPE_TYPE_VIDL</a>   ((uint32_t) 0x1)</td></tr>
+<tr class="memdesc:gab3801fb3aa15ef1b184da3fc2f9ea9ad"><td class="mdescLeft"> </td><td class="mdescRight">Video Pipe is of type VIDL. <br/></td></tr>
+<tr class="separator:gab3801fb3aa15ef1b184da3fc2f9ea9ad"><td class="memSeparator" colspan="2"> </td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
+DSS Common Region Id</h2></td></tr>
+<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrpe14c18786796e6e151589afd6f03bb3c"></a>Id for different Common Regions</p>
+<p><a class="anchor" id="CSL_DssCommRegId"></a></p>
+</td></tr>
+<tr class="memitem:gaba6b3367cbe7db1f57b4693234fbcd86"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaba6b3367cbe7db1f57b4693234fbcd86"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gaba6b3367cbe7db1f57b4693234fbcd86">CSL_DSS_COMM_REG_ID_0</a>   ((uint32_t) 0x0U)</td></tr>
+<tr class="memdesc:gaba6b3367cbe7db1f57b4693234fbcd86"><td class="mdescLeft"> </td><td class="mdescRight">Common Region 0 i.e. M region. <br/></td></tr>
+<tr class="separator:gaba6b3367cbe7db1f57b4693234fbcd86"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga961c35c051c33b4e92691db8a5ee749d"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga961c35c051c33b4e92691db8a5ee749d"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga961c35c051c33b4e92691db8a5ee749d">CSL_DSS_COMM_REG_ID_1</a>   ((uint32_t) 0x1U)</td></tr>
+<tr class="memdesc:ga961c35c051c33b4e92691db8a5ee749d"><td class="mdescLeft"> </td><td class="mdescRight">Common Region 1 i.e. S0 region. <br/></td></tr>
+<tr class="separator:ga961c35c051c33b4e92691db8a5ee749d"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gafaece2043fd351a5f7f8b5b1628921c7"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gafaece2043fd351a5f7f8b5b1628921c7"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gafaece2043fd351a5f7f8b5b1628921c7">CSL_DSS_COMM_REG_ID_2</a>   ((uint32_t) 0x2U)</td></tr>
+<tr class="memdesc:gafaece2043fd351a5f7f8b5b1628921c7"><td class="mdescLeft"> </td><td class="mdescRight">Common Region 2 i.e. S1 region. <br/></td></tr>
+<tr class="separator:gafaece2043fd351a5f7f8b5b1628921c7"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga22dc72847784f75cad78a4c2a3b3f217"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga22dc72847784f75cad78a4c2a3b3f217"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga22dc72847784f75cad78a4c2a3b3f217">CSL_DSS_COMM_REG_ID_3</a>   ((uint32_t) 0x3U)</td></tr>
+<tr class="memdesc:ga22dc72847784f75cad78a4c2a3b3f217"><td class="mdescLeft"> </td><td class="mdescRight">Common Region 3 i.e. S2 region. <br/></td></tr>
+<tr class="separator:ga22dc72847784f75cad78a4c2a3b3f217"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gab1b9457684eda680598c1bc8a574e20c"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gab1b9457684eda680598c1bc8a574e20c"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gab1b9457684eda680598c1bc8a574e20c">CSL_DSS_COMM_REG_ID_MAX</a>   ((uint32_t) 0x4U)</td></tr>
+<tr class="memdesc:gab1b9457684eda680598c1bc8a574e20c"><td class="mdescLeft"> </td><td class="mdescRight">Common Region Max Id. <br/></td></tr>
+<tr class="separator:gab1b9457684eda680598c1bc8a574e20c"><td class="memSeparator" colspan="2"> </td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
+DSS Common Region Id Mask</h2></td></tr>
+<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrp463a1b4194c629b7d229502009d25347"></a>Mask for different Common Regions</p>
+<p><a class="anchor" id="CSL_DssCommRegIdMask"></a></p>
+</td></tr>
+<tr class="memitem:ga8e4fccb97063f3a1a8ae7a0a45f7de7b"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga8e4fccb97063f3a1a8ae7a0a45f7de7b"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga8e4fccb97063f3a1a8ae7a0a45f7de7b">CSL_DSS_COMM_REG_ID_0_MASK</a>   ((uint32_t) 0x1U)</td></tr>
+<tr class="memdesc:ga8e4fccb97063f3a1a8ae7a0a45f7de7b"><td class="mdescLeft"> </td><td class="mdescRight">Common Region 0 Mask. <br/></td></tr>
+<tr class="separator:ga8e4fccb97063f3a1a8ae7a0a45f7de7b"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga4b279b40e6fa88217af7df5242fdd007"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga4b279b40e6fa88217af7df5242fdd007"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga4b279b40e6fa88217af7df5242fdd007">CSL_DSS_COMM_REG_ID_1_MASK</a>   ((uint32_t) 0x2U)</td></tr>
+<tr class="memdesc:ga4b279b40e6fa88217af7df5242fdd007"><td class="mdescLeft"> </td><td class="mdescRight">Common Region 1 Mask. <br/></td></tr>
+<tr class="separator:ga4b279b40e6fa88217af7df5242fdd007"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gafdceb9e1230dd80ea4e7da1689f9ffba"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gafdceb9e1230dd80ea4e7da1689f9ffba"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gafdceb9e1230dd80ea4e7da1689f9ffba">CSL_DSS_COMM_REG_ID_2_MASK</a>   ((uint32_t) 0x4U)</td></tr>
+<tr class="memdesc:gafdceb9e1230dd80ea4e7da1689f9ffba"><td class="mdescLeft"> </td><td class="mdescRight">Common Region 2 Mask. <br/></td></tr>
+<tr class="separator:gafdceb9e1230dd80ea4e7da1689f9ffba"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga6ae3cbe4e7f4e35054a0f8f1d739ed83"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga6ae3cbe4e7f4e35054a0f8f1d739ed83"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga6ae3cbe4e7f4e35054a0f8f1d739ed83">CSL_DSS_COMM_REG_ID_3_MASK</a>   ((uint32_t) 0x8U)</td></tr>
+<tr class="memdesc:ga6ae3cbe4e7f4e35054a0f8f1d739ed83"><td class="mdescLeft"> </td><td class="mdescRight">Common Region 3 Mask. <br/></td></tr>
+<tr class="separator:ga6ae3cbe4e7f4e35054a0f8f1d739ed83"><td class="memSeparator" colspan="2"> </td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
+DSS Video Pipeline Id</h2></td></tr>
+<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrp4b589ffcca2426061519164c8a417d26"></a>Id for different Video Pipelines</p>
+<p><a class="anchor" id="CSL_DssVidPipeId"></a></p>
+</td></tr>
+<tr class="memitem:gab861a5295a9cd21b01897e1026aa2b79"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gab861a5295a9cd21b01897e1026aa2b79"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gab861a5295a9cd21b01897e1026aa2b79">CSL_DSS_VID_PIPE_ID_VID1</a>   ((uint32_t) 0x0U)</td></tr>
+<tr class="memdesc:gab861a5295a9cd21b01897e1026aa2b79"><td class="mdescLeft"> </td><td class="mdescRight">Video Pipeline 1. <br/></td></tr>
+<tr class="separator:gab861a5295a9cd21b01897e1026aa2b79"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga73aee3bb97f91dafe4f9adfd0a0d3bac"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga73aee3bb97f91dafe4f9adfd0a0d3bac"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga73aee3bb97f91dafe4f9adfd0a0d3bac">CSL_DSS_VID_PIPE_ID_VIDL1</a>   ((uint32_t) 0x1U)</td></tr>
+<tr class="memdesc:ga73aee3bb97f91dafe4f9adfd0a0d3bac"><td class="mdescLeft"> </td><td class="mdescRight">Video Lite Pipeline 1. <br/></td></tr>
+<tr class="separator:ga73aee3bb97f91dafe4f9adfd0a0d3bac"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gadd35014f4f1e166a6b95a0e80970f9e8"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gadd35014f4f1e166a6b95a0e80970f9e8"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gadd35014f4f1e166a6b95a0e80970f9e8">CSL_DSS_VID_PIPE_ID_VID2</a>   ((uint32_t) 0x2U)</td></tr>
+<tr class="memdesc:gadd35014f4f1e166a6b95a0e80970f9e8"><td class="mdescLeft"> </td><td class="mdescRight">Video Pipeline 2. <br/></td></tr>
+<tr class="separator:gadd35014f4f1e166a6b95a0e80970f9e8"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga9692470b1ffe05c0bf39af6cce81b3dd"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga9692470b1ffe05c0bf39af6cce81b3dd"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga9692470b1ffe05c0bf39af6cce81b3dd">CSL_DSS_VID_PIPE_ID_VIDL2</a>   ((uint32_t) 0x3U)</td></tr>
+<tr class="memdesc:ga9692470b1ffe05c0bf39af6cce81b3dd"><td class="mdescLeft"> </td><td class="mdescRight">Video Lite Pipeline 2. <br/></td></tr>
+<tr class="separator:ga9692470b1ffe05c0bf39af6cce81b3dd"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gafbbd94228f58df3124b2bc9780379cea"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gafbbd94228f58df3124b2bc9780379cea"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gafbbd94228f58df3124b2bc9780379cea">CSL_DSS_VID_PIPE_ID_MAX</a>   ((uint32_t) 0x4U)</td></tr>
+<tr class="memdesc:gafbbd94228f58df3124b2bc9780379cea"><td class="mdescLeft"> </td><td class="mdescRight">Video Pipeline Max Id. <br/></td></tr>
+<tr class="separator:gafbbd94228f58df3124b2bc9780379cea"><td class="memSeparator" colspan="2"> </td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
+DSS Video Pipeline Id Mask</h2></td></tr>
+<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrpeb4f1adda29b365a747b3831c9d25219"></a>Mask for different Video Pipelines</p>
+<p><a class="anchor" id="CSL_DssVidPipeIdMask"></a></p>
+</td></tr>
+<tr class="memitem:gaada71522489dcbd519415f3f81e490d0"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaada71522489dcbd519415f3f81e490d0"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gaada71522489dcbd519415f3f81e490d0">CSL_DSS_VID_PIPE_ID_VID1_MASK</a>   ((uint32_t) 0x1U)</td></tr>
+<tr class="memdesc:gaada71522489dcbd519415f3f81e490d0"><td class="mdescLeft"> </td><td class="mdescRight">Video Pipeline 1 Mask. <br/></td></tr>
+<tr class="separator:gaada71522489dcbd519415f3f81e490d0"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga86337ef6c0f0e8ac50c07638c91104c6"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga86337ef6c0f0e8ac50c07638c91104c6"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga86337ef6c0f0e8ac50c07638c91104c6">CSL_DSS_VID_PIPE_ID_VIDL1_MASK</a>   ((uint32_t) 0x2U)</td></tr>
+<tr class="memdesc:ga86337ef6c0f0e8ac50c07638c91104c6"><td class="mdescLeft"> </td><td class="mdescRight">Video Lite Pipeline 1 Mask. <br/></td></tr>
+<tr class="separator:ga86337ef6c0f0e8ac50c07638c91104c6"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga1d978b06983e4f19a666abd322a70293"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga1d978b06983e4f19a666abd322a70293"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga1d978b06983e4f19a666abd322a70293">CSL_DSS_VID_PIPE_ID_VID2_MASK</a>   ((uint32_t) 0x4U)</td></tr>
+<tr class="memdesc:ga1d978b06983e4f19a666abd322a70293"><td class="mdescLeft"> </td><td class="mdescRight">Video Pipeline 2 Mask. <br/></td></tr>
+<tr class="separator:ga1d978b06983e4f19a666abd322a70293"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga69abb0b78149e8c8880f5ce9f1d7d508"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga69abb0b78149e8c8880f5ce9f1d7d508"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga69abb0b78149e8c8880f5ce9f1d7d508">CSL_DSS_VID_PIPE_ID_VIDL2_MASK</a>   ((uint32_t) 0x8U)</td></tr>
+<tr class="memdesc:ga69abb0b78149e8c8880f5ce9f1d7d508"><td class="mdescLeft"> </td><td class="mdescRight">Video Lite Pipeline 1 Mask. <br/></td></tr>
+<tr class="separator:ga69abb0b78149e8c8880f5ce9f1d7d508"><td class="memSeparator" colspan="2"> </td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
+DSS Overlay Id</h2></td></tr>
+<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrpcfb0a9f68d3237eaaf05f7f77f257a18"></a>Id for DSS Overlays</p>
+<p><a class="anchor" id="CSL_DssOverlayId"></a></p>
+</td></tr>
+<tr class="memitem:ga5acb54b8623189d18b4211a24a0ddb8c"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga5acb54b8623189d18b4211a24a0ddb8c"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga5acb54b8623189d18b4211a24a0ddb8c">CSL_DSS_OVERLAY_ID_1</a>   ((uint32_t) 0x0U)</td></tr>
+<tr class="memdesc:ga5acb54b8623189d18b4211a24a0ddb8c"><td class="mdescLeft"> </td><td class="mdescRight">Overlay 1. <br/></td></tr>
+<tr class="separator:ga5acb54b8623189d18b4211a24a0ddb8c"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga37edd061f4545fb5bcaf98fb0e29f49c"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga37edd061f4545fb5bcaf98fb0e29f49c"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga37edd061f4545fb5bcaf98fb0e29f49c">CSL_DSS_OVERLAY_ID_2</a>   ((uint32_t) 0x1U)</td></tr>
+<tr class="memdesc:ga37edd061f4545fb5bcaf98fb0e29f49c"><td class="mdescLeft"> </td><td class="mdescRight">Overlay 2. <br/></td></tr>
+<tr class="separator:ga37edd061f4545fb5bcaf98fb0e29f49c"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga4cc372289cf4841713a3fff407e519ec"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga4cc372289cf4841713a3fff407e519ec"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga4cc372289cf4841713a3fff407e519ec">CSL_DSS_OVERLAY_ID_3</a>   ((uint32_t) 0x2U)</td></tr>
+<tr class="memdesc:ga4cc372289cf4841713a3fff407e519ec"><td class="mdescLeft"> </td><td class="mdescRight">Overlay 3. <br/></td></tr>
+<tr class="separator:ga4cc372289cf4841713a3fff407e519ec"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gae8da1ca2c825364e430e6bb94a11c8de"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gae8da1ca2c825364e430e6bb94a11c8de"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gae8da1ca2c825364e430e6bb94a11c8de">CSL_DSS_OVERLAY_ID_4</a>   ((uint32_t) 0x3U)</td></tr>
+<tr class="memdesc:gae8da1ca2c825364e430e6bb94a11c8de"><td class="mdescLeft"> </td><td class="mdescRight">Overlay 4. <br/></td></tr>
+<tr class="separator:gae8da1ca2c825364e430e6bb94a11c8de"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga41df77f605b2d5c6e107fd4b0df61220"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga41df77f605b2d5c6e107fd4b0df61220"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga41df77f605b2d5c6e107fd4b0df61220">CSL_DSS_OVERLAY_ID_MAX</a>   ((uint32_t) 0x4U)</td></tr>
+<tr class="memdesc:ga41df77f605b2d5c6e107fd4b0df61220"><td class="mdescLeft"> </td><td class="mdescRight">Overlay Max Id. <br/></td></tr>
+<tr class="separator:ga41df77f605b2d5c6e107fd4b0df61220"><td class="memSeparator" colspan="2"> </td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
+DSS Overlay Id Mask</h2></td></tr>
+<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrpaa3ecb068fdfa3c7f57c2c1db2f7da87"></a>Mask for DSS Overlays</p>
+<p><a class="anchor" id="CSL_DssOverlayIdMask"></a></p>
+</td></tr>
+<tr class="memitem:gab66410f4f933b9c077e3f9d294436073"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gab66410f4f933b9c077e3f9d294436073"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gab66410f4f933b9c077e3f9d294436073">CSL_DSS_OVERLAY_ID_1_MASK</a>   ((uint32_t) 0x1U)</td></tr>
+<tr class="memdesc:gab66410f4f933b9c077e3f9d294436073"><td class="mdescLeft"> </td><td class="mdescRight">Overlay 1 Mask. <br/></td></tr>
+<tr class="separator:gab66410f4f933b9c077e3f9d294436073"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gac474fcd4a03b4204c8cf584ba7b105e2"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gac474fcd4a03b4204c8cf584ba7b105e2"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gac474fcd4a03b4204c8cf584ba7b105e2">CSL_DSS_OVERLAY_ID_2_MASK</a>   ((uint32_t) 0x2U)</td></tr>
+<tr class="memdesc:gac474fcd4a03b4204c8cf584ba7b105e2"><td class="mdescLeft"> </td><td class="mdescRight">Overlay 2 Mask. <br/></td></tr>
+<tr class="separator:gac474fcd4a03b4204c8cf584ba7b105e2"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gaa3f86a021fef86c1bdf2d94e122143c2"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaa3f86a021fef86c1bdf2d94e122143c2"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gaa3f86a021fef86c1bdf2d94e122143c2">CSL_DSS_OVERLAY_ID_3_MASK</a>   ((uint32_t) 0x4U)</td></tr>
+<tr class="memdesc:gaa3f86a021fef86c1bdf2d94e122143c2"><td class="mdescLeft"> </td><td class="mdescRight">Overlay 3 Mask. <br/></td></tr>
+<tr class="separator:gaa3f86a021fef86c1bdf2d94e122143c2"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga80bbc7f730eed3ab5d593b450858375e"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga80bbc7f730eed3ab5d593b450858375e"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga80bbc7f730eed3ab5d593b450858375e">CSL_DSS_OVERLAY_ID_4_MASK</a>   ((uint32_t) 0x8U)</td></tr>
+<tr class="memdesc:ga80bbc7f730eed3ab5d593b450858375e"><td class="mdescLeft"> </td><td class="mdescRight">Overlay 4 Mask. <br/></td></tr>
+<tr class="separator:ga80bbc7f730eed3ab5d593b450858375e"><td class="memSeparator" colspan="2"> </td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
+DSS Video Port Id</h2></td></tr>
+<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrp8e7e2734143bce0b1d9361d2b28f72cd"></a>Id for DSS Video Ports</p>
+<p><a class="anchor" id="CSL_DssVpId"></a></p>
+</td></tr>
+<tr class="memitem:gafbe058ac640cf42ad08afa3b32fb29d1"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gafbe058ac640cf42ad08afa3b32fb29d1"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gafbe058ac640cf42ad08afa3b32fb29d1">CSL_DSS_VP_ID_1</a>   ((uint32_t) 0x0U)</td></tr>
+<tr class="memdesc:gafbe058ac640cf42ad08afa3b32fb29d1"><td class="mdescLeft"> </td><td class="mdescRight">Video Port 1. <br/></td></tr>
+<tr class="separator:gafbe058ac640cf42ad08afa3b32fb29d1"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga34118161f4c12f89689b79f5ce09696c"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga34118161f4c12f89689b79f5ce09696c"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga34118161f4c12f89689b79f5ce09696c">CSL_DSS_VP_ID_2</a>   ((uint32_t) 0x1U)</td></tr>
+<tr class="memdesc:ga34118161f4c12f89689b79f5ce09696c"><td class="mdescLeft"> </td><td class="mdescRight">Video Port 2. <br/></td></tr>
+<tr class="separator:ga34118161f4c12f89689b79f5ce09696c"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga657e4b1ceb6955c961961d5c0af3e9b7"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga657e4b1ceb6955c961961d5c0af3e9b7"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga657e4b1ceb6955c961961d5c0af3e9b7">CSL_DSS_VP_ID_3</a>   ((uint32_t) 0x2U)</td></tr>
+<tr class="memdesc:ga657e4b1ceb6955c961961d5c0af3e9b7"><td class="mdescLeft"> </td><td class="mdescRight">Video Port 3. <br/></td></tr>
+<tr class="separator:ga657e4b1ceb6955c961961d5c0af3e9b7"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga961d6492d4afd198139770cb4b93a5ab"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga961d6492d4afd198139770cb4b93a5ab"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga961d6492d4afd198139770cb4b93a5ab">CSL_DSS_VP_ID_4</a>   ((uint32_t) 0x3U)</td></tr>
+<tr class="memdesc:ga961d6492d4afd198139770cb4b93a5ab"><td class="mdescLeft"> </td><td class="mdescRight">Video Port 4. <br/></td></tr>
+<tr class="separator:ga961d6492d4afd198139770cb4b93a5ab"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga0a203752c6295d20389b36d6c2e0de0c"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga0a203752c6295d20389b36d6c2e0de0c"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga0a203752c6295d20389b36d6c2e0de0c">CSL_DSS_VP_ID_MAX</a>   ((uint32_t) 0x4U)</td></tr>
+<tr class="memdesc:ga0a203752c6295d20389b36d6c2e0de0c"><td class="mdescLeft"> </td><td class="mdescRight">Video Port Max Id. <br/></td></tr>
+<tr class="separator:ga0a203752c6295d20389b36d6c2e0de0c"><td class="memSeparator" colspan="2"> </td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
+DSS Video Port Id Mask</h2></td></tr>
+<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrp1fb3a130098965c6681a70b50146e92b"></a>Mask for DSS Video Ports</p>
+<p><a class="anchor" id="CSL_DssVpIdMask"></a></p>
+</td></tr>
+<tr class="memitem:ga2b8bb0130844b328ae5711f9f4b5487b"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga2b8bb0130844b328ae5711f9f4b5487b"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga2b8bb0130844b328ae5711f9f4b5487b">CSL_DSS_VP_ID_1_MASK</a>   ((uint32_t) 0x1U)</td></tr>
+<tr class="memdesc:ga2b8bb0130844b328ae5711f9f4b5487b"><td class="mdescLeft"> </td><td class="mdescRight">Video Port 1. <br/></td></tr>
+<tr class="separator:ga2b8bb0130844b328ae5711f9f4b5487b"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga40b42315f64e4f7290af3f3f2c1f6fb4"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga40b42315f64e4f7290af3f3f2c1f6fb4"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga40b42315f64e4f7290af3f3f2c1f6fb4">CSL_DSS_VP_ID_2_MASK</a>   ((uint32_t) 0x2U)</td></tr>
+<tr class="memdesc:ga40b42315f64e4f7290af3f3f2c1f6fb4"><td class="mdescLeft"> </td><td class="mdescRight">Video Port 2. <br/></td></tr>
+<tr class="separator:ga40b42315f64e4f7290af3f3f2c1f6fb4"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gac5818d5d83b12514d8a01d62d6743306"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gac5818d5d83b12514d8a01d62d6743306"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gac5818d5d83b12514d8a01d62d6743306">CSL_DSS_VP_ID_3_MASK</a>   ((uint32_t) 0x4U)</td></tr>
+<tr class="memdesc:gac5818d5d83b12514d8a01d62d6743306"><td class="mdescLeft"> </td><td class="mdescRight">Video Port 3. <br/></td></tr>
+<tr class="separator:gac5818d5d83b12514d8a01d62d6743306"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gacabf7b4969d7515d967d243e2e67dd2a"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gacabf7b4969d7515d967d243e2e67dd2a"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gacabf7b4969d7515d967d243e2e67dd2a">CSL_DSS_VP_ID_4_MASK</a>   ((uint32_t) 0x8U)</td></tr>
+<tr class="memdesc:gacabf7b4969d7515d967d243e2e67dd2a"><td class="mdescLeft"> </td><td class="mdescRight">Video Port 4. <br/></td></tr>
+<tr class="separator:gacabf7b4969d7515d967d243e2e67dd2a"><td class="memSeparator" colspan="2"> </td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
+DSS CSC Range</h2></td></tr>
+<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrpd4a3662b1126c41fa8b992e665baac9d"></a>DSS Color Space Conversion range setting</p>
+<p><a class="anchor" id="CSL_DssCscRange"></a></p>
+</td></tr>
+<tr class="memitem:ga3041c8743595f7ce5d8ebb59cf32bcc4"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga3041c8743595f7ce5d8ebb59cf32bcc4"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga3041c8743595f7ce5d8ebb59cf32bcc4">CSL_DSS_CSC_RANGE_LIMITED</a>   ((uint32_t) 0x0U)</td></tr>
+<tr class="memdesc:ga3041c8743595f7ce5d8ebb59cf32bcc4"><td class="mdescLeft"> </td><td class="mdescRight">Limited range selected. <br/></td></tr>
+<tr class="separator:ga3041c8743595f7ce5d8ebb59cf32bcc4"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga2b1f7a9fccfe834266cc61dbab22a7f2"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga2b1f7a9fccfe834266cc61dbab22a7f2"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga2b1f7a9fccfe834266cc61dbab22a7f2">CSL_DSS_CSC_RANGE_FULL</a>   ((uint32_t) 0x1U)</td></tr>
+<tr class="memdesc:ga2b1f7a9fccfe834266cc61dbab22a7f2"><td class="mdescLeft"> </td><td class="mdescRight">Full range selected. <br/></td></tr>
+<tr class="separator:ga2b1f7a9fccfe834266cc61dbab22a7f2"><td class="memSeparator" colspan="2"> </td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
+DSS Safety Region Id</h2></td></tr>
+<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrp97068651d2c78fc46e17a55960fbb300"></a><a class="anchor" id="CSL_DssSafetyRegionId"></a></p>
+</td></tr>
+<tr class="memitem:gaa3a861b982382bd7387783bf1019576c"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaa3a861b982382bd7387783bf1019576c"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gaa3a861b982382bd7387783bf1019576c">CSL_DSS_SAFETY_REGION_0</a>   ((uint32_t) 0x0U)</td></tr>
+<tr class="memdesc:gaa3a861b982382bd7387783bf1019576c"><td class="mdescLeft"> </td><td class="mdescRight">Safety Region 0. <br/></td></tr>
+<tr class="separator:gaa3a861b982382bd7387783bf1019576c"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gaa104154d768c72acac19f2545460038c"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaa104154d768c72acac19f2545460038c"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gaa104154d768c72acac19f2545460038c">CSL_DSS_SAFETY_REGION_1</a>   ((uint32_t) 0x1U)</td></tr>
+<tr class="memdesc:gaa104154d768c72acac19f2545460038c"><td class="mdescLeft"> </td><td class="mdescRight">Safety Region 1. <br/></td></tr>
+<tr class="separator:gaa104154d768c72acac19f2545460038c"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga3ca88d86a0c19685b48ce935c86821bd"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga3ca88d86a0c19685b48ce935c86821bd"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga3ca88d86a0c19685b48ce935c86821bd">CSL_DSS_SAFETY_REGION_2</a>   ((uint32_t) 0x2U)</td></tr>
+<tr class="memdesc:ga3ca88d86a0c19685b48ce935c86821bd"><td class="mdescLeft"> </td><td class="mdescRight">Safety Region 2. <br/></td></tr>
+<tr class="separator:ga3ca88d86a0c19685b48ce935c86821bd"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga7fecc5cd051151b901deb0dbd6c36201"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga7fecc5cd051151b901deb0dbd6c36201"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga7fecc5cd051151b901deb0dbd6c36201">CSL_DSS_SAFETY_REGION_3</a>   ((uint32_t) 0x3U)</td></tr>
+<tr class="memdesc:ga7fecc5cd051151b901deb0dbd6c36201"><td class="mdescLeft"> </td><td class="mdescRight">Safety Region 3. <br/></td></tr>
+<tr class="separator:ga7fecc5cd051151b901deb0dbd6c36201"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gabfb09986c4139d4093308e6f708fd582"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gabfb09986c4139d4093308e6f708fd582"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gabfb09986c4139d4093308e6f708fd582">CSL_DSS_SAFETY_REGION_4</a>   ((uint32_t) 0x4U)</td></tr>
+<tr class="memdesc:gabfb09986c4139d4093308e6f708fd582"><td class="mdescLeft"> </td><td class="mdescRight">Safety Region 4. <br/></td></tr>
+<tr class="separator:gabfb09986c4139d4093308e6f708fd582"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga83b9053e2bc53689cf537ae19102ff9f"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga83b9053e2bc53689cf537ae19102ff9f"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga83b9053e2bc53689cf537ae19102ff9f">CSL_DSS_SAFETY_REGION_5</a>   ((uint32_t) 0x5U)</td></tr>
+<tr class="memdesc:ga83b9053e2bc53689cf537ae19102ff9f"><td class="mdescLeft"> </td><td class="mdescRight">Safety Region 5. <br/></td></tr>
+<tr class="separator:ga83b9053e2bc53689cf537ae19102ff9f"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga0e75b3f63a3ad9488a287d1cfe5ff9a5"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga0e75b3f63a3ad9488a287d1cfe5ff9a5"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga0e75b3f63a3ad9488a287d1cfe5ff9a5">CSL_DSS_SAFETY_REGION_6</a>   ((uint32_t) 0x6U)</td></tr>
+<tr class="memdesc:ga0e75b3f63a3ad9488a287d1cfe5ff9a5"><td class="mdescLeft"> </td><td class="mdescRight">Safety Region 6. <br/></td></tr>
+<tr class="separator:ga0e75b3f63a3ad9488a287d1cfe5ff9a5"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga20d089acf2d69bd7f86a05eea0093bfa"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga20d089acf2d69bd7f86a05eea0093bfa"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga20d089acf2d69bd7f86a05eea0093bfa">CSL_DSS_SAFETY_REGION_7</a>   ((uint32_t) 0x7U)</td></tr>
+<tr class="memdesc:ga20d089acf2d69bd7f86a05eea0093bfa"><td class="mdescLeft"> </td><td class="mdescRight">Safety Region 7. <br/></td></tr>
+<tr class="separator:ga20d089acf2d69bd7f86a05eea0093bfa"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga514efc84b40d7147969434b2d5cff2fe"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga514efc84b40d7147969434b2d5cff2fe"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga514efc84b40d7147969434b2d5cff2fe">CSL_DSS_SAFETY_REGION_MAX</a>   ((uint32_t) 0x8U)</td></tr>
+<tr class="memdesc:ga514efc84b40d7147969434b2d5cff2fe"><td class="mdescLeft"> </td><td class="mdescRight">Safety Region Max. <br/></td></tr>
+<tr class="separator:ga514efc84b40d7147969434b2d5cff2fe"><td class="memSeparator" colspan="2"> </td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
+DSS Safety Check Mode</h2></td></tr>
+<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrpcbedaa0bb877b8cddda7f9e53b926807"></a>Mode of operation of the safety check module</p>
+<p><a class="anchor" id="CSL_DssSafetyChkMode"></a></p>
+</td></tr>
+<tr class="memitem:ga87bc16f17eb07c0e42f1e00f9ed1ef3e"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga87bc16f17eb07c0e42f1e00f9ed1ef3e"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga87bc16f17eb07c0e42f1e00f9ed1ef3e">CSL_DSS_SAFETY_CHK_FRAME_FREEZE_DETECT</a>   ((uint32_t) CSL_DSS_VID1_SAFETY_ATTRIBUTES_CAPTUREMODE_VAL_FRAMEFREEZE)</td></tr>
+<tr class="memdesc:ga87bc16f17eb07c0e42f1e00f9ed1ef3e"><td class="mdescLeft"> </td><td class="mdescRight">Frame freeze detect enabled. <br/></td></tr>
+<tr class="separator:ga87bc16f17eb07c0e42f1e00f9ed1ef3e"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gabc2f69f2dfaab74b675a923fb14c3489"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gabc2f69f2dfaab74b675a923fb14c3489"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gabc2f69f2dfaab74b675a923fb14c3489">CSL_DSS_SAFETY_CHK_DATA_INTEGRITY</a>   ((uint32_t) CSL_DSS_VID1_SAFETY_ATTRIBUTES_CAPTUREMODE_VAL_DATACHECK)</td></tr>
+<tr class="memdesc:gabc2f69f2dfaab74b675a923fb14c3489"><td class="mdescLeft"> </td><td class="mdescRight">Data correctness check enabled. <br/></td></tr>
+<tr class="separator:gabc2f69f2dfaab74b675a923fb14c3489"><td class="memSeparator" colspan="2"> </td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
+DSS Safety Check Frame Skip</h2></td></tr>
+<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrp4f25b42e171e1e65f90829cd462804ff"></a>Indicates which frames to be skipped while doing safety check</p>
+<p><a class="anchor" id="CSL_DssSafetyChkFrameSkip"></a></p>
+</td></tr>
+<tr class="memitem:ga3b3b3a0ec326781390a727d437cd3e59"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga3b3b3a0ec326781390a727d437cd3e59"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga3b3b3a0ec326781390a727d437cd3e59">CSL_DSS_SAFETY_CHK_FRAME_SKIP_NO</a>   ((uint32_t) CSL_DSS_VID1_SAFETY_ATTRIBUTES_FRAMESKIP_VAL_DISABLE)</td></tr>
+<tr class="memdesc:ga3b3b3a0ec326781390a727d437cd3e59"><td class="mdescLeft"> </td><td class="mdescRight">No frames are skipped. <br/></td></tr>
+<tr class="separator:ga3b3b3a0ec326781390a727d437cd3e59"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga663277190152e9b070a32830bdfab30d"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga663277190152e9b070a32830bdfab30d"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga663277190152e9b070a32830bdfab30d">CSL_DSS_SAFETY_CHK_FRAME_SKIP_EVEN</a>   ((uint32_t) CSL_DSS_VID1_SAFETY_ATTRIBUTES_FRAMESKIP_VAL_EVEN)</td></tr>
+<tr class="memdesc:ga663277190152e9b070a32830bdfab30d"><td class="mdescLeft"> </td><td class="mdescRight">Even Frames are skipped starting from second frame after enable. <br/></td></tr>
+<tr class="separator:ga663277190152e9b070a32830bdfab30d"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gafca0e84bf97ed23528e1bc15af0a4e98"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gafca0e84bf97ed23528e1bc15af0a4e98"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gafca0e84bf97ed23528e1bc15af0a4e98">CSL_DSS_SAFETY_CHK_FRAME_SKIP_ODD</a>   ((uint32_t) CSL_DSS_VID1_SAFETY_ATTRIBUTES_FRAMESKIP_VAL_ODD)</td></tr>
+<tr class="memdesc:gafca0e84bf97ed23528e1bc15af0a4e98"><td class="mdescLeft"> </td><td class="mdescRight">Odd Frames are skipped starting from first frame after enable. <br/></td></tr>
+<tr class="separator:gafca0e84bf97ed23528e1bc15af0a4e98"><td class="memSeparator" colspan="2"> </td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
+DSS DPI Id</h2></td></tr>
+<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrp631d209402e40260289711a0549407bf"></a><a class="anchor" id="CSL_DssDpiId"></a></p>
+</td></tr>
+<tr class="memitem:ga9679d96bb4a54cf7e8ce0a22bf034ce3"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga9679d96bb4a54cf7e8ce0a22bf034ce3"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga9679d96bb4a54cf7e8ce0a22bf034ce3">CSL_DSS_DPI_ID_0</a>   ((uint32_t) 0x0U)</td></tr>
+<tr class="memdesc:ga9679d96bb4a54cf7e8ce0a22bf034ce3"><td class="mdescLeft"> </td><td class="mdescRight">DPI Id 0. <br/></td></tr>
+<tr class="separator:ga9679d96bb4a54cf7e8ce0a22bf034ce3"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga2ef99175d7ba50686f9d3b55484099d3"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga2ef99175d7ba50686f9d3b55484099d3"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga2ef99175d7ba50686f9d3b55484099d3">CSL_DSS_DPI_ID_1</a>   ((uint32_t) 0x1U)</td></tr>
+<tr class="memdesc:ga2ef99175d7ba50686f9d3b55484099d3"><td class="mdescLeft"> </td><td class="mdescRight">DPI Id 1. <br/></td></tr>
+<tr class="separator:ga2ef99175d7ba50686f9d3b55484099d3"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga2fcf2f843406ec0ff1ee6ec29156576e"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga2fcf2f843406ec0ff1ee6ec29156576e"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga2fcf2f843406ec0ff1ee6ec29156576e">CSL_DSS_DPI_ID_2</a>   ((uint32_t) 0x2U)</td></tr>
+<tr class="memdesc:ga2fcf2f843406ec0ff1ee6ec29156576e"><td class="mdescLeft"> </td><td class="mdescRight">DPI Id 2. <br/></td></tr>
+<tr class="separator:ga2fcf2f843406ec0ff1ee6ec29156576e"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga3e2b38794f954faea2bf1769d25c2bd3"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga3e2b38794f954faea2bf1769d25c2bd3"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga3e2b38794f954faea2bf1769d25c2bd3">CSL_DSS_DPI_ID_3</a>   ((uint32_t) 0x3U)</td></tr>
+<tr class="memdesc:ga3e2b38794f954faea2bf1769d25c2bd3"><td class="mdescLeft"> </td><td class="mdescRight">DPI Id 3. <br/></td></tr>
+<tr class="separator:ga3e2b38794f954faea2bf1769d25c2bd3"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga92854e551ae60a5d40c9c5c1c8326092"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga92854e551ae60a5d40c9c5c1c8326092"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga92854e551ae60a5d40c9c5c1c8326092">CSL_DSS_DPI_ID_4</a>   ((uint32_t) 0x4U)</td></tr>
+<tr class="memdesc:ga92854e551ae60a5d40c9c5c1c8326092"><td class="mdescLeft"> </td><td class="mdescRight">DPI Id 4. <br/></td></tr>
+<tr class="separator:ga92854e551ae60a5d40c9c5c1c8326092"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gad22d8422668bd5e965c0611d4c80ca36"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gad22d8422668bd5e965c0611d4c80ca36"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gad22d8422668bd5e965c0611d4c80ca36">CSL_DSS_DPI_ID_5</a>   ((uint32_t) 0x5U)</td></tr>
+<tr class="memdesc:gad22d8422668bd5e965c0611d4c80ca36"><td class="mdescLeft"> </td><td class="mdescRight">DPI Id 5. <br/></td></tr>
+<tr class="separator:gad22d8422668bd5e965c0611d4c80ca36"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga53c1ac5fbf207e8f973902051404e51e"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga53c1ac5fbf207e8f973902051404e51e"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga53c1ac5fbf207e8f973902051404e51e">CSL_DSS_DPI_ID_MAX</a>   ((uint32_t) 0x6U)</td></tr>
+<tr class="memdesc:ga53c1ac5fbf207e8f973902051404e51e"><td class="mdescLeft"> </td><td class="mdescRight">DPI Id Max. <br/></td></tr>
+<tr class="separator:ga53c1ac5fbf207e8f973902051404e51e"><td class="memSeparator" colspan="2"> </td></tr>
+</table>
+<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
+<p>This can be used across sub component CSL FLs of DSS </p>
+<h2 class="groupheader">Function Documentation</h2>
+<a class="anchor" id="ga09a24eab792b00629e4b510d36a326a8"></a>
+<div class="memitem">
+<div class="memproto">
+<table class="mlabels">
+ <tr>
+ <td class="mlabels-left">
+ <table class="memname">
+ <tr>
+ <td class="memname">static void CSL_dssCscCoeffInit </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="struct_c_s_l___dss_csc_coeff.html">CSL_DssCscCoeff</a> * </td>
+ <td class="paramname"><em>cscCoeff</em></td><td>)</td>
+ <td></td>
+ </tr>
+ </table>
+ </td>
+ <td class="mlabels-right">
+<span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span> </td>
+ </tr>
+</table>
+</div><div class="memdoc">
+
+<p><a class="el" href="struct_c_s_l___dss_csc_coeff.html" title="Structure containing coefficients for Color Space Conversion. ">CSL_DssCscCoeff</a> structure init function. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">cscCoeff</td><td>Pointer to <a class="el" href="struct_c_s_l___dss_csc_coeff.html" title="Structure containing coefficients for Color Space Conversion. ">CSL_DssCscCoeff</a> structure</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga0eba2c12170b846778eecb3eeb5a9a46"></a>
+<div class="memitem">
+<div class="memproto">
+<table class="mlabels">
+ <tr>
+ <td class="mlabels-left">
+ <table class="memname">
+ <tr>
+ <td class="memname">static void CSL_dssSafetyChkCfgInit </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="struct_c_s_l___dss_safety_chk_cfg.html">CSL_DssSafetyChkCfg</a> * </td>
+ <td class="paramname"><em>safetyCfg</em></td><td>)</td>
+ <td></td>
+ </tr>
+ </table>
+ </td>
+ <td class="mlabels-right">
+<span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span> </td>
+ </tr>
+</table>
+</div><div class="memdoc">
+
+<p><a class="el" href="struct_c_s_l___dss_safety_chk_cfg.html" title="Configuration for doing safety checks. ">CSL_DssSafetyChkCfg</a> structure init function. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">safetyCfg</td><td>Pointer to <a class="el" href="struct_c_s_l___dss_safety_chk_cfg.html" title="Configuration for doing safety checks. ">CSL_DssSafetyChkCfg</a> structure</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None </dd></dl>
+
+</div>
+</div>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html b/packages/ti/drv/dss/docs/doxygen/html/group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html
--- /dev/null
@@ -0,0 +1,900 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DSS Video Pipe CSL FL</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="files.html"><span>Files</span></a></li>
+ </ul>
+ </div>
+</div><!-- top -->
+<div class="header">
+ <div class="summary">
+<a href="#files">Files</a> |
+<a href="#nested-classes">Data Structures</a> |
+<a href="#typedef-members">Typedefs</a> |
+<a href="#func-members">Functions</a> </div>
+ <div class="headertitle">
+<div class="title">DSS Video Pipe CSL FL<div class="ingroups"><a class="el" href="group___c_s_l___d_s_s.html">DSS</a></div></div> </div>
+</div><!--header-->
+<div class="contents">
+<table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="files"></a>
+Files</h2></td></tr>
+<tr class="memitem:csl__dss_video_pipe_8h"><td class="memItemLeft" align="right" valign="top">file  </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__dss_video_pipe_8h.html">csl_dssVideoPipe.h</a></td></tr>
+<tr class="memdesc:csl__dss_video_pipe_8h"><td class="mdescLeft"> </td><td class="mdescRight">DSS Video Pipe CSL FL interface file. <br/></td></tr>
+<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="nested-classes"></a>
+Data Structures</h2></td></tr>
+<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_vid_pipe_cfg.html">CSL_DssVidPipeCfg</a></td></tr>
+<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">Configuration for DSS Video Pipe. <a href="struct_c_s_l___dss_vid_pipe_cfg.html#details">More...</a><br/></td></tr>
+<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_vid_pipe_dma_cfg.html">CSL_DssVidPipeDmaCfg</a></td></tr>
+<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">DSS Video Pipe DMA related Config parameters. <a href="struct_c_s_l___dss_vid_pipe_dma_cfg.html#details">More...</a><br/></td></tr>
+<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_vid_pipe_luma_cfg.html">CSL_DssVidPipeLumaCfg</a></td></tr>
+<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">DSS Video Pipe Luma Key Config parameters. <a href="struct_c_s_l___dss_vid_pipe_luma_cfg.html#details">More...</a><br/></td></tr>
+<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_vid_pipe_alpha_cfg.html">CSL_DssVidPipeAlphaCfg</a></td></tr>
+<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">DSS Video Pipe Alpha Config parameters. <a href="struct_c_s_l___dss_vid_pipe_alpha_cfg.html#details">More...</a><br/></td></tr>
+<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_vid_pipe_v_c1_cfg.html">CSL_DssVidPipeVC1Cfg</a></td></tr>
+<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">DSS Video Pipe VC1 configuration. <a href="struct_c_s_l___dss_vid_pipe_v_c1_cfg.html#details">More...</a><br/></td></tr>
+<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_vid_pipe_m_flag_cfg.html">CSL_DssVidPipeMFlagCfg</a></td></tr>
+<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">DSS Video Pipe MFLAG Config parameters. <a href="struct_c_s_l___dss_vid_pipe_m_flag_cfg.html#details">More...</a><br/></td></tr>
+<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="typedef-members"></a>
+Typedefs</h2></td></tr>
+<tr class="memitem:gafdca0345c9254a9bdbcd6e4a2ee000f6"><td class="memItemLeft" align="right" valign="top">typedef CSL_dss_vid1Regs </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gafdca0345c9254a9bdbcd6e4a2ee000f6">CSL_dss_pipeRegs</a></td></tr>
+<tr class="memdesc:gafdca0345c9254a9bdbcd6e4a2ee000f6"><td class="mdescLeft"> </td><td class="mdescRight">DSS Video Pipe Registers. <a href="#gafdca0345c9254a9bdbcd6e4a2ee000f6">More...</a><br/></td></tr>
+<tr class="separator:gafdca0345c9254a9bdbcd6e4a2ee000f6"><td class="memSeparator" colspan="2"> </td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a>
+Functions</h2></td></tr>
+<tr class="memitem:ga6d983ffe721b5a1b602bfa53995f1c76"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#ga6d983ffe721b5a1b602bfa53995f1c76">CSL_dssVidPipeSetConfig</a> (<a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gafdca0345c9254a9bdbcd6e4a2ee000f6">CSL_dss_pipeRegs</a> *pipeRegs, const <a class="el" href="struct_c_s_l___dss_vid_pipe_cfg.html">CSL_DssVidPipeCfg</a> *pipeCfg, const <a class="el" href="struct_c_s_l___dss_vid_pipe_v_c1_cfg.html">CSL_DssVidPipeVC1Cfg</a> *vc1Cfg)</td></tr>
+<tr class="memdesc:ga6d983ffe721b5a1b602bfa53995f1c76"><td class="mdescLeft"> </td><td class="mdescRight">Configure the Video Pipe. <a href="#ga6d983ffe721b5a1b602bfa53995f1c76">More...</a><br/></td></tr>
+<tr class="separator:ga6d983ffe721b5a1b602bfa53995f1c76"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gaf3bd47c49aa8edd65bfd202779cdd0a2"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gaf3bd47c49aa8edd65bfd202779cdd0a2">CSL_dssVidPipeSetDmaConfig</a> (<a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gafdca0345c9254a9bdbcd6e4a2ee000f6">CSL_dss_pipeRegs</a> *pipeRegs, const <a class="el" href="struct_c_s_l___dss_vid_pipe_dma_cfg.html">CSL_DssVidPipeDmaCfg</a> *dmaCfg)</td></tr>
+<tr class="memdesc:gaf3bd47c49aa8edd65bfd202779cdd0a2"><td class="mdescLeft"> </td><td class="mdescRight">Configure the Video Pipe DMA parameters. <a href="#gaf3bd47c49aa8edd65bfd202779cdd0a2">More...</a><br/></td></tr>
+<tr class="separator:gaf3bd47c49aa8edd65bfd202779cdd0a2"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga0b9cbe7775795bca5b9a8904ec9fc4b1"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#ga0b9cbe7775795bca5b9a8904ec9fc4b1">CSL_dssVidPipeEnableTransparency</a> (<a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gafdca0345c9254a9bdbcd6e4a2ee000f6">CSL_dss_pipeRegs</a> *pipeRegs, const <a class="el" href="struct_c_s_l___dss_vid_pipe_luma_cfg.html">CSL_DssVidPipeLumaCfg</a> *lumaCfg)</td></tr>
+<tr class="memdesc:ga0b9cbe7775795bca5b9a8904ec9fc4b1"><td class="mdescLeft"> </td><td class="mdescRight">Enable the Luma Key transparency matching and set luma params. <a href="#ga0b9cbe7775795bca5b9a8904ec9fc4b1">More...</a><br/></td></tr>
+<tr class="separator:ga0b9cbe7775795bca5b9a8904ec9fc4b1"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga3646182313235e92362cd843fdc6c2e6"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#ga3646182313235e92362cd843fdc6c2e6">CSL_dssVidPipeSetAlphaConfig</a> (<a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gafdca0345c9254a9bdbcd6e4a2ee000f6">CSL_dss_pipeRegs</a> *pipeRegs, const <a class="el" href="struct_c_s_l___dss_vid_pipe_alpha_cfg.html">CSL_DssVidPipeAlphaCfg</a> *alphaCfg)</td></tr>
+<tr class="memdesc:ga3646182313235e92362cd843fdc6c2e6"><td class="mdescLeft"> </td><td class="mdescRight">Set DSS Video Pipe Alpha parameters. <a href="#ga3646182313235e92362cd843fdc6c2e6">More...</a><br/></td></tr>
+<tr class="separator:ga3646182313235e92362cd843fdc6c2e6"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gacebfcb0b4ae57fa7a1ce3c73f6b552e8"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gacebfcb0b4ae57fa7a1ce3c73f6b552e8">CSL_dssVidPipeSetCSCCoeff</a> (<a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gafdca0345c9254a9bdbcd6e4a2ee000f6">CSL_dss_pipeRegs</a> *pipeRegs, const <a class="el" href="struct_c_s_l___dss_csc_coeff.html">CSL_DssCscCoeff</a> *coeff)</td></tr>
+<tr class="memdesc:gacebfcb0b4ae57fa7a1ce3c73f6b552e8"><td class="mdescLeft"> </td><td class="mdescRight">Configure the coefficients for Color Space Conversion. <a href="#gacebfcb0b4ae57fa7a1ce3c73f6b552e8">More...</a><br/></td></tr>
+<tr class="separator:gacebfcb0b4ae57fa7a1ce3c73f6b552e8"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga11ed49990e9b63ecbf167cff5f6a9755"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#ga11ed49990e9b63ecbf167cff5f6a9755">CSL_dssVidPipeSetBuffAddr</a> (<a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gafdca0345c9254a9bdbcd6e4a2ee000f6">CSL_dss_pipeRegs</a> *pipeRegs, uint32_t field, uint64_t baseAddrRGBY, uint64_t baseAddrUV)</td></tr>
+<tr class="memdesc:ga11ed49990e9b63ecbf167cff5f6a9755"><td class="mdescLeft"> </td><td class="mdescRight">Configure the coefficients for Color Space Conversion. <a href="#ga11ed49990e9b63ecbf167cff5f6a9755">More...</a><br/></td></tr>
+<tr class="separator:ga11ed49990e9b63ecbf167cff5f6a9755"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gac037fe8b1ea6f506c6b0d00fd4a84491"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gac037fe8b1ea6f506c6b0d00fd4a84491">CSL_dssVidPipeEnable</a> (<a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gafdca0345c9254a9bdbcd6e4a2ee000f6">CSL_dss_pipeRegs</a> *pipeRegs, uint32_t enable)</td></tr>
+<tr class="memdesc:gac037fe8b1ea6f506c6b0d00fd4a84491"><td class="mdescLeft"> </td><td class="mdescRight">Enable the DSS Video Pipe. <a href="#gac037fe8b1ea6f506c6b0d00fd4a84491">More...</a><br/></td></tr>
+<tr class="separator:gac037fe8b1ea6f506c6b0d00fd4a84491"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga70f77613b5b22a937388f5b072a7f74d"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#ga70f77613b5b22a937388f5b072a7f74d">CSL_dssVidPipeSetSafetySignSeedVal</a> (<a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gafdca0345c9254a9bdbcd6e4a2ee000f6">CSL_dss_pipeRegs</a> *pipeRegs, uint32_t signSeedVal)</td></tr>
+<tr class="memdesc:ga70f77613b5b22a937388f5b072a7f74d"><td class="mdescLeft"> </td><td class="mdescRight">Set the seed value for the signature calculation. <a href="#ga70f77613b5b22a937388f5b072a7f74d">More...</a><br/></td></tr>
+<tr class="separator:ga70f77613b5b22a937388f5b072a7f74d"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga37238e9b68bd88742eb54cca7c3cd7a8"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#ga37238e9b68bd88742eb54cca7c3cd7a8">CSL_dssVidPipeSetSafetyReferenceSign</a> (<a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gafdca0345c9254a9bdbcd6e4a2ee000f6">CSL_dss_pipeRegs</a> *pipeRegs, uint32_t referenceSign)</td></tr>
+<tr class="memdesc:ga37238e9b68bd88742eb54cca7c3cd7a8"><td class="mdescLeft"> </td><td class="mdescRight">Set the reference safety signature for data correctness check. <a href="#ga37238e9b68bd88742eb54cca7c3cd7a8">More...</a><br/></td></tr>
+<tr class="separator:ga37238e9b68bd88742eb54cca7c3cd7a8"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gae5dc5282a40648fd2f69165e7a373265"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gae5dc5282a40648fd2f69165e7a373265">CSL_dssVidPipeSetSafetyChkConfig</a> (<a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gafdca0345c9254a9bdbcd6e4a2ee000f6">CSL_dss_pipeRegs</a> *pipeRegs, const <a class="el" href="struct_c_s_l___dss_safety_chk_cfg.html">CSL_DssSafetyChkCfg</a> *safetyCfg)</td></tr>
+<tr class="memdesc:gae5dc5282a40648fd2f69165e7a373265"><td class="mdescLeft"> </td><td class="mdescRight">Configure the Safety Check Params. <a href="#gae5dc5282a40648fd2f69165e7a373265">More...</a><br/></td></tr>
+<tr class="separator:gae5dc5282a40648fd2f69165e7a373265"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gaf51512cbab443cebde3013bc6bf212aa"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gaf51512cbab443cebde3013bc6bf212aa">CSL_dssVidPipeGetSafetySign</a> (const <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gafdca0345c9254a9bdbcd6e4a2ee000f6">CSL_dss_pipeRegs</a> *pipeRegs)</td></tr>
+<tr class="memdesc:gaf51512cbab443cebde3013bc6bf212aa"><td class="mdescLeft"> </td><td class="mdescRight">Get the Safety Signature. <a href="#gaf51512cbab443cebde3013bc6bf212aa">More...</a><br/></td></tr>
+<tr class="separator:gaf51512cbab443cebde3013bc6bf212aa"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga3095d9a0f35cd85fba7c2be6b14d798d"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#ga3095d9a0f35cd85fba7c2be6b14d798d">CSL_dssVidPipeSetMflagConfig</a> (<a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gafdca0345c9254a9bdbcd6e4a2ee000f6">CSL_dss_pipeRegs</a> *pipeRegs, const <a class="el" href="struct_c_s_l___dss_vid_pipe_m_flag_cfg.html">CSL_DssVidPipeMFlagCfg</a> *mflagCfg)</td></tr>
+<tr class="memdesc:ga3095d9a0f35cd85fba7c2be6b14d798d"><td class="mdescLeft"> </td><td class="mdescRight">Set the MFLAG configuration. <a href="#ga3095d9a0f35cd85fba7c2be6b14d798d">More...</a><br/></td></tr>
+<tr class="separator:ga3095d9a0f35cd85fba7c2be6b14d798d"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gaf4dc4e4142893b328dd75906147dde8f"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gaf4dc4e4142893b328dd75906147dde8f">CSL_dssVidPipeCropEnable</a> (<a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gafdca0345c9254a9bdbcd6e4a2ee000f6">CSL_dss_pipeRegs</a> *pipeRegs, uint32_t enable)</td></tr>
+<tr class="memdesc:gaf4dc4e4142893b328dd75906147dde8f"><td class="mdescLeft"> </td><td class="mdescRight">Enable the crop in DSS Video Pipe. <a href="#gaf4dc4e4142893b328dd75906147dde8f">More...</a><br/></td></tr>
+<tr class="separator:gaf4dc4e4142893b328dd75906147dde8f"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gae2ea4d9e0e2d9662d1bda20ec77567dc"><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gae2ea4d9e0e2d9662d1bda20ec77567dc">CSL_dssVidPipeCfgInit</a> (<a class="el" href="struct_c_s_l___dss_vid_pipe_cfg.html">CSL_DssVidPipeCfg</a> *pipeCfg)</td></tr>
+<tr class="memdesc:gae2ea4d9e0e2d9662d1bda20ec77567dc"><td class="mdescLeft"> </td><td class="mdescRight"><a class="el" href="struct_c_s_l___dss_vid_pipe_cfg.html" title="Configuration for DSS Video Pipe. ">CSL_DssVidPipeCfg</a> structure init function. <a href="#gae2ea4d9e0e2d9662d1bda20ec77567dc">More...</a><br/></td></tr>
+<tr class="separator:gae2ea4d9e0e2d9662d1bda20ec77567dc"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga53cc07dd9deeeec69be494c89fd12812"><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#ga53cc07dd9deeeec69be494c89fd12812">CSL_dssVidPipeDmaCfgInit</a> (<a class="el" href="struct_c_s_l___dss_vid_pipe_dma_cfg.html">CSL_DssVidPipeDmaCfg</a> *dmaCfg)</td></tr>
+<tr class="memdesc:ga53cc07dd9deeeec69be494c89fd12812"><td class="mdescLeft"> </td><td class="mdescRight"><a class="el" href="struct_c_s_l___dss_vid_pipe_dma_cfg.html" title="DSS Video Pipe DMA related Config parameters. ">CSL_DssVidPipeDmaCfg</a> structure init function. <a href="#ga53cc07dd9deeeec69be494c89fd12812">More...</a><br/></td></tr>
+<tr class="separator:ga53cc07dd9deeeec69be494c89fd12812"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gaeec644be0c0f1f62da19eca5c1e9b877"><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gaeec644be0c0f1f62da19eca5c1e9b877">CSL_dssVidPipeLumaCfgInit</a> (<a class="el" href="struct_c_s_l___dss_vid_pipe_luma_cfg.html">CSL_DssVidPipeLumaCfg</a> *lumaCfg)</td></tr>
+<tr class="memdesc:gaeec644be0c0f1f62da19eca5c1e9b877"><td class="mdescLeft"> </td><td class="mdescRight"><a class="el" href="struct_c_s_l___dss_vid_pipe_luma_cfg.html" title="DSS Video Pipe Luma Key Config parameters. ">CSL_DssVidPipeLumaCfg</a> structure init function. <a href="#gaeec644be0c0f1f62da19eca5c1e9b877">More...</a><br/></td></tr>
+<tr class="separator:gaeec644be0c0f1f62da19eca5c1e9b877"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga8a3d5286ff2be3f2056f554f1d5c92d7"><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#ga8a3d5286ff2be3f2056f554f1d5c92d7">CSL_dssVidPipeAlphaCfgInit</a> (<a class="el" href="struct_c_s_l___dss_vid_pipe_alpha_cfg.html">CSL_DssVidPipeAlphaCfg</a> *alphaCfg)</td></tr>
+<tr class="memdesc:ga8a3d5286ff2be3f2056f554f1d5c92d7"><td class="mdescLeft"> </td><td class="mdescRight"><a class="el" href="struct_c_s_l___dss_vid_pipe_alpha_cfg.html" title="DSS Video Pipe Alpha Config parameters. ">CSL_DssVidPipeAlphaCfg</a> structure init function. <a href="#ga8a3d5286ff2be3f2056f554f1d5c92d7">More...</a><br/></td></tr>
+<tr class="separator:ga8a3d5286ff2be3f2056f554f1d5c92d7"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gaf11746b1003b15855996b817cfe3d38a"><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gaf11746b1003b15855996b817cfe3d38a">CSL_dssVidPipeVC1CfgInit</a> (<a class="el" href="struct_c_s_l___dss_vid_pipe_v_c1_cfg.html">CSL_DssVidPipeVC1Cfg</a> *vc1Cfg)</td></tr>
+<tr class="memdesc:gaf11746b1003b15855996b817cfe3d38a"><td class="mdescLeft"> </td><td class="mdescRight"><a class="el" href="struct_c_s_l___dss_vid_pipe_v_c1_cfg.html" title="DSS Video Pipe VC1 configuration. ">CSL_DssVidPipeVC1Cfg</a> structure init function. <a href="#gaf11746b1003b15855996b817cfe3d38a">More...</a><br/></td></tr>
+<tr class="separator:gaf11746b1003b15855996b817cfe3d38a"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga5d27f327524e3016a74de471e5eb38a1"><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#ga5d27f327524e3016a74de471e5eb38a1">CSL_dssVidPipeMFlagCfgInit</a> (<a class="el" href="struct_c_s_l___dss_vid_pipe_m_flag_cfg.html">CSL_DssVidPipeMFlagCfg</a> *mflagCfg)</td></tr>
+<tr class="memdesc:ga5d27f327524e3016a74de471e5eb38a1"><td class="mdescLeft"> </td><td class="mdescRight"><a class="el" href="struct_c_s_l___dss_vid_pipe_m_flag_cfg.html" title="DSS Video Pipe MFLAG Config parameters. ">CSL_DssVidPipeMFlagCfg</a> structure init function. <a href="#ga5d27f327524e3016a74de471e5eb38a1">More...</a><br/></td></tr>
+<tr class="separator:ga5d27f327524e3016a74de471e5eb38a1"><td class="memSeparator" colspan="2"> </td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
+DSS Video Pipe YUV Alignment</h2></td></tr>
+<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrp86b2331e6a2db01a2dc084ec0330b77d"></a>DSS Video Pipe alignment for unpacked YUV data</p>
+<p><a class="anchor" id="CSL_DssVidPipeYuvAlign"></a></p>
+</td></tr>
+<tr class="memitem:ga39ea4aaf120f874835b851ed1a0d84af"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga39ea4aaf120f874835b851ed1a0d84af"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#ga39ea4aaf120f874835b851ed1a0d84af">CSL_DSS_VID_PIPE_YUV_ALIGN_LSB</a>   ((uint32_t) CSL_DSS_VID1_ATTRIBUTES2_YUV_ALIGN_VAL_LSB)</td></tr>
+<tr class="memdesc:ga39ea4aaf120f874835b851ed1a0d84af"><td class="mdescLeft"> </td><td class="mdescRight">Data is LSB aligned (MSB unused) <br/></td></tr>
+<tr class="separator:ga39ea4aaf120f874835b851ed1a0d84af"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gaed342608ce368c3c538c10e808a60eef"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaed342608ce368c3c538c10e808a60eef"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gaed342608ce368c3c538c10e808a60eef">CSL_DSS_VID_PIPE_YUV_ALIGN_MSB</a>   ((uint32_t) CSL_DSS_VID1_ATTRIBUTES2_YUV_ALIGN_VAL_MSB)</td></tr>
+<tr class="memdesc:gaed342608ce368c3c538c10e808a60eef"><td class="mdescLeft"> </td><td class="mdescRight">Data is MSB aligned (LSB unused) <br/></td></tr>
+<tr class="separator:gaed342608ce368c3c538c10e808a60eef"><td class="memSeparator" colspan="2"> </td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
+DSS Video Pipe Scaler Value</h2></td></tr>
+<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrp83154959129b95a62ce8d13e8b314eab"></a><a class="anchor" id="CSL_DssVidPipeScVal"></a></p>
+</td></tr>
+<tr class="memitem:gabeae764db02ef759820ebc878da5abc7"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gabeae764db02ef759820ebc878da5abc7"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gabeae764db02ef759820ebc878da5abc7">CSL_DSS_VID_PIPE_SC_DISABLED</a>   ((uint32_t) CSL_DSS_VID1_ATTRIBUTES_RESIZEENABLE_VAL_RESIZEPROC)</td></tr>
+<tr class="memdesc:gabeae764db02ef759820ebc878da5abc7"><td class="mdescLeft"> </td><td class="mdescRight">Scaler is disabled. <br/></td></tr>
+<tr class="separator:gabeae764db02ef759820ebc878da5abc7"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gae5bb5538c01dcbf3f8b9d1fc52dc385a"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gae5bb5538c01dcbf3f8b9d1fc52dc385a"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gae5bb5538c01dcbf3f8b9d1fc52dc385a">CSL_DSS_VID_PIPE_SC_ENABLED_H</a>   ((uint32_t) CSL_DSS_VID1_ATTRIBUTES_RESIZEENABLE_VAL_HRESIZE)</td></tr>
+<tr class="memdesc:gae5bb5538c01dcbf3f8b9d1fc52dc385a"><td class="mdescLeft"> </td><td class="mdescRight">Horizontal scaling is enabled. <br/></td></tr>
+<tr class="separator:gae5bb5538c01dcbf3f8b9d1fc52dc385a"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga0add9ab4761fdd4bd2a09c4e140a35c0"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga0add9ab4761fdd4bd2a09c4e140a35c0"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#ga0add9ab4761fdd4bd2a09c4e140a35c0">CSL_DSS_VID_PIPE_SC_ENABLED_V</a>   ((uint32_t) CSL_DSS_VID1_ATTRIBUTES_RESIZEENABLE_VAL_VRESIZE)</td></tr>
+<tr class="memdesc:ga0add9ab4761fdd4bd2a09c4e140a35c0"><td class="mdescLeft"> </td><td class="mdescRight">Vertical scaling is enabled. <br/></td></tr>
+<tr class="separator:ga0add9ab4761fdd4bd2a09c4e140a35c0"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga00799c61e0313dc87418c766f836a958"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga00799c61e0313dc87418c766f836a958"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#ga00799c61e0313dc87418c766f836a958">CSL_DSS_VID_PIPE_SC_ENABLED_HV</a>   ((uint32_t) CSL_DSS_VID1_ATTRIBUTES_RESIZEENABLE_VAL_HVRESIZE)</td></tr>
+<tr class="memdesc:ga00799c61e0313dc87418c766f836a958"><td class="mdescLeft"> </td><td class="mdescRight">Both horizontal and vertical scaling is enabled. <br/></td></tr>
+<tr class="separator:ga00799c61e0313dc87418c766f836a958"><td class="memSeparator" colspan="2"> </td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
+DSS Video Pipe Preload Control Value</h2></td></tr>
+<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrp3f0530b4e9aa3b05bdb641cec287c44f"></a>DSS Video Pipe Preload Value can be fixed HW value or SW determined</p>
+<p><a class="anchor" id="CSL_DssVidPipePreloadControl"></a></p>
+</td></tr>
+<tr class="memitem:ga9920a3ec2d8c5a8707be21d19df2cdca"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga9920a3ec2d8c5a8707be21d19df2cdca"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#ga9920a3ec2d8c5a8707be21d19df2cdca">CSL_DSS_VID_PIPE_PRELOAD_CONTROL_SW</a>   ((uint32_t) CSL_DSS_VID1_ATTRIBUTES_BUFPRELOAD_VAL_DEFVAL)</td></tr>
+<tr class="memdesc:ga9920a3ec2d8c5a8707be21d19df2cdca"><td class="mdescLeft"> </td><td class="mdescRight">Value is defined by preload register. <br/></td></tr>
+<tr class="separator:ga9920a3ec2d8c5a8707be21d19df2cdca"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gaddf7744bff3546d7cf3dfcd5f50578e0"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaddf7744bff3546d7cf3dfcd5f50578e0"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gaddf7744bff3546d7cf3dfcd5f50578e0">CSL_DSS_VID_PIPE_PRELOAD_CONTROL_HW</a>   ((uint32_t) CSL_DSS_VID1_ATTRIBUTES_BUFPRELOAD_VAL_HIGHTHRES)</td></tr>
+<tr class="memdesc:gaddf7744bff3546d7cf3dfcd5f50578e0"><td class="mdescLeft"> </td><td class="mdescRight">HW pre-fetches pixels up to high threshold value. <br/></td></tr>
+<tr class="separator:gaddf7744bff3546d7cf3dfcd5f50578e0"><td class="memSeparator" colspan="2"> </td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
+DSS Video Pipe Priority Value</h2></td></tr>
+<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrp02664cab5bf857c6d0d7db873b13fa6d"></a><a class="anchor" id="CSL_DssVidPipePriorityVal"></a></p>
+</td></tr>
+<tr class="memitem:ga8d4e4c078fa0fed3f7d3d3739d5ff7cd"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga8d4e4c078fa0fed3f7d3d3739d5ff7cd"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#ga8d4e4c078fa0fed3f7d3d3739d5ff7cd">CSL_DSS_VID_PIPE_PRIORITY_NORMAL</a>   ((uint32_t) CSL_DSS_VID1_ATTRIBUTES_ARBITRATION_VAL_NORMALPRIO)</td></tr>
+<tr class="memdesc:ga8d4e4c078fa0fed3f7d3d3739d5ff7cd"><td class="mdescLeft"> </td><td class="mdescRight">Priority of video pipeline is normal. <br/></td></tr>
+<tr class="separator:ga8d4e4c078fa0fed3f7d3d3739d5ff7cd"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gab90746bec79505e7a733d0f2bd72f5c4"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gab90746bec79505e7a733d0f2bd72f5c4"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gab90746bec79505e7a733d0f2bd72f5c4">CSL_DSS_VID_PIPE_PRIORITY_HIGH</a>   ((uint32_t) CSL_DSS_VID1_ATTRIBUTES_ARBITRATION_VAL_HIGHPRIO)</td></tr>
+<tr class="memdesc:gab90746bec79505e7a733d0f2bd72f5c4"><td class="mdescLeft"> </td><td class="mdescRight">Priority of video pipeline is high. <br/></td></tr>
+<tr class="separator:gab90746bec79505e7a733d0f2bd72f5c4"><td class="memSeparator" colspan="2"> </td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
+DSS Video Pipe Self Refresh Mode Control</h2></td></tr>
+<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrp6bbf78e2cd2fffd2777670f1dc32f539"></a><a class="anchor" id="CSL_DssVidPipeRefreshControl"></a></p>
+</td></tr>
+<tr class="memitem:gacb4282f5d79fd4252da0e6dfc0a6e124"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gacb4282f5d79fd4252da0e6dfc0a6e124"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gacb4282f5d79fd4252da0e6dfc0a6e124">CSL_DSS_VID_PIPE_REFRESH_CONTROL_SW</a>   ((uint32_t) CSL_DSS_VID1_ATTRIBUTES_SELFREFRESHAUTO_VAL_SELFREFRESHAUTODIS)</td></tr>
+<tr class="memdesc:gacb4282f5d79fd4252da0e6dfc0a6e124"><td class="mdescLeft"> </td><td class="mdescRight">Transition is controlled by SW. <br/></td></tr>
+<tr class="separator:gacb4282f5d79fd4252da0e6dfc0a6e124"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gaa791b8ccb4cccc15ca17524094cfb280"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaa791b8ccb4cccc15ca17524094cfb280"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gaa791b8ccb4cccc15ca17524094cfb280">CSL_DSS_VID_PIPE_REFRESH_CONTROL_HW</a>   ((uint32_t) CSL_DSS_VID1_ATTRIBUTES_SELFREFRESHAUTO_VAL_SELFREFRESHAUTOEN)</td></tr>
+<tr class="memdesc:gaa791b8ccb4cccc15ca17524094cfb280"><td class="mdescLeft"> </td><td class="mdescRight">Transition is controlled by HW. <br/></td></tr>
+<tr class="separator:gaa791b8ccb4cccc15ca17524094cfb280"><td class="memSeparator" colspan="2"> </td></tr>
+</table>
+<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
+<h2 class="groupheader">Typedef Documentation</h2>
+<a class="anchor" id="gafdca0345c9254a9bdbcd6e4a2ee000f6"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">typedef CSL_dss_vid1Regs <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gafdca0345c9254a9bdbcd6e4a2ee000f6">CSL_dss_pipeRegs</a></td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+
+<p>DSS Video Pipe Registers. </p>
+<p>DSS7 UL has two Video Pipes: VID and VIDL1. VIDL1 registers are a subset of VID registers. Hence using VID register structure as a generic structure to have common APIs. Caller should not configure VID pipe specific functionality for VIDL1 pipe </p>
+
+</div>
+</div>
+<h2 class="groupheader">Function Documentation</h2>
+<a class="anchor" id="ga8a3d5286ff2be3f2056f554f1d5c92d7"></a>
+<div class="memitem">
+<div class="memproto">
+<table class="mlabels">
+ <tr>
+ <td class="mlabels-left">
+ <table class="memname">
+ <tr>
+ <td class="memname">static void CSL_dssVidPipeAlphaCfgInit </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="struct_c_s_l___dss_vid_pipe_alpha_cfg.html">CSL_DssVidPipeAlphaCfg</a> * </td>
+ <td class="paramname"><em>alphaCfg</em></td><td>)</td>
+ <td></td>
+ </tr>
+ </table>
+ </td>
+ <td class="mlabels-right">
+<span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span> </td>
+ </tr>
+</table>
+</div><div class="memdoc">
+
+<p><a class="el" href="struct_c_s_l___dss_vid_pipe_alpha_cfg.html" title="DSS Video Pipe Alpha Config parameters. ">CSL_DssVidPipeAlphaCfg</a> structure init function. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">alphaCfg</td><td>Pointer to <a class="el" href="struct_c_s_l___dss_vid_pipe_alpha_cfg.html" title="DSS Video Pipe Alpha Config parameters. ">CSL_DssVidPipeAlphaCfg</a> structure</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="gae2ea4d9e0e2d9662d1bda20ec77567dc"></a>
+<div class="memitem">
+<div class="memproto">
+<table class="mlabels">
+ <tr>
+ <td class="mlabels-left">
+ <table class="memname">
+ <tr>
+ <td class="memname">static void CSL_dssVidPipeCfgInit </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="struct_c_s_l___dss_vid_pipe_cfg.html">CSL_DssVidPipeCfg</a> * </td>
+ <td class="paramname"><em>pipeCfg</em></td><td>)</td>
+ <td></td>
+ </tr>
+ </table>
+ </td>
+ <td class="mlabels-right">
+<span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span> </td>
+ </tr>
+</table>
+</div><div class="memdoc">
+
+<p><a class="el" href="struct_c_s_l___dss_vid_pipe_cfg.html" title="Configuration for DSS Video Pipe. ">CSL_DssVidPipeCfg</a> structure init function. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">pipeCfg</td><td>Pointer to <a class="el" href="struct_c_s_l___dss_vid_pipe_cfg.html" title="Configuration for DSS Video Pipe. ">CSL_DssVidPipeCfg</a> structure</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="gaf4dc4e4142893b328dd75906147dde8f"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">void CSL_dssVidPipeCropEnable </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gafdca0345c9254a9bdbcd6e4a2ee000f6">CSL_dss_pipeRegs</a> * </td>
+ <td class="paramname"><em>pipeRegs</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">uint32_t </td>
+ <td class="paramname"><em>enable</em> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td></td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+
+<p>Enable the crop in DSS Video Pipe. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">pipeRegs</td><td>Pointer to a <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gafdca0345c9254a9bdbcd6e4a2ee000f6" title="DSS Video Pipe Registers. ">CSL_dss_pipeRegs</a> structure containing the Video Pipe configuration </td></tr>
+ <tr><td class="paramname">enable</td><td>Enable or disable the Video Pipe TRUE: Enable FALSE: Disable</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga53cc07dd9deeeec69be494c89fd12812"></a>
+<div class="memitem">
+<div class="memproto">
+<table class="mlabels">
+ <tr>
+ <td class="mlabels-left">
+ <table class="memname">
+ <tr>
+ <td class="memname">static void CSL_dssVidPipeDmaCfgInit </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="struct_c_s_l___dss_vid_pipe_dma_cfg.html">CSL_DssVidPipeDmaCfg</a> * </td>
+ <td class="paramname"><em>dmaCfg</em></td><td>)</td>
+ <td></td>
+ </tr>
+ </table>
+ </td>
+ <td class="mlabels-right">
+<span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span> </td>
+ </tr>
+</table>
+</div><div class="memdoc">
+
+<p><a class="el" href="struct_c_s_l___dss_vid_pipe_dma_cfg.html" title="DSS Video Pipe DMA related Config parameters. ">CSL_DssVidPipeDmaCfg</a> structure init function. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">dmaCfg</td><td>Pointer to <a class="el" href="struct_c_s_l___dss_vid_pipe_dma_cfg.html" title="DSS Video Pipe DMA related Config parameters. ">CSL_DssVidPipeDmaCfg</a> structure</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="gac037fe8b1ea6f506c6b0d00fd4a84491"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">void CSL_dssVidPipeEnable </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gafdca0345c9254a9bdbcd6e4a2ee000f6">CSL_dss_pipeRegs</a> * </td>
+ <td class="paramname"><em>pipeRegs</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">uint32_t </td>
+ <td class="paramname"><em>enable</em> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td></td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+
+<p>Enable the DSS Video Pipe. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">pipeRegs</td><td>Pointer to a <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gafdca0345c9254a9bdbcd6e4a2ee000f6" title="DSS Video Pipe Registers. ">CSL_dss_pipeRegs</a> structure containing the Video Pipe configuration </td></tr>
+ <tr><td class="paramname">enable</td><td>Enable or disable the Video Pipe TRUE: Enable FALSE: Disable</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga0b9cbe7775795bca5b9a8904ec9fc4b1"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">void CSL_dssVidPipeEnableTransparency </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gafdca0345c9254a9bdbcd6e4a2ee000f6">CSL_dss_pipeRegs</a> * </td>
+ <td class="paramname"><em>pipeRegs</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">const <a class="el" href="struct_c_s_l___dss_vid_pipe_luma_cfg.html">CSL_DssVidPipeLumaCfg</a> * </td>
+ <td class="paramname"><em>lumaCfg</em> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td></td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+
+<p>Enable the Luma Key transparency matching and set luma params. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">pipeRegs</td><td>Pointer to a <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gafdca0345c9254a9bdbcd6e4a2ee000f6" title="DSS Video Pipe Registers. ">CSL_dss_pipeRegs</a> structure containing the Video Pipe configuration </td></tr>
+ <tr><td class="paramname">lumaCfg</td><td>Pointer to the <a class="el" href="struct_c_s_l___dss_vid_pipe_luma_cfg.html" title="DSS Video Pipe Luma Key Config parameters. ">CSL_DssVidPipeLumaCfg</a> structure. This parameter should not be NULL</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="gaf51512cbab443cebde3013bc6bf212aa"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t CSL_dssVidPipeGetSafetySign </td>
+ <td>(</td>
+ <td class="paramtype">const <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gafdca0345c9254a9bdbcd6e4a2ee000f6">CSL_dss_pipeRegs</a> * </td>
+ <td class="paramname"><em>pipeRegs</em></td><td>)</td>
+ <td></td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+
+<p>Get the Safety Signature. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">pipeRegs</td><td>Pointer to a <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gafdca0345c9254a9bdbcd6e4a2ee000f6" title="DSS Video Pipe Registers. ">CSL_dss_pipeRegs</a> structure containing the Video Pipe configuration</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>Signature Value </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="gaeec644be0c0f1f62da19eca5c1e9b877"></a>
+<div class="memitem">
+<div class="memproto">
+<table class="mlabels">
+ <tr>
+ <td class="mlabels-left">
+ <table class="memname">
+ <tr>
+ <td class="memname">static void CSL_dssVidPipeLumaCfgInit </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="struct_c_s_l___dss_vid_pipe_luma_cfg.html">CSL_DssVidPipeLumaCfg</a> * </td>
+ <td class="paramname"><em>lumaCfg</em></td><td>)</td>
+ <td></td>
+ </tr>
+ </table>
+ </td>
+ <td class="mlabels-right">
+<span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span> </td>
+ </tr>
+</table>
+</div><div class="memdoc">
+
+<p><a class="el" href="struct_c_s_l___dss_vid_pipe_luma_cfg.html" title="DSS Video Pipe Luma Key Config parameters. ">CSL_DssVidPipeLumaCfg</a> structure init function. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">lumaCfg</td><td>Pointer to <a class="el" href="struct_c_s_l___dss_vid_pipe_luma_cfg.html" title="DSS Video Pipe Luma Key Config parameters. ">CSL_DssVidPipeLumaCfg</a> structure</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga5d27f327524e3016a74de471e5eb38a1"></a>
+<div class="memitem">
+<div class="memproto">
+<table class="mlabels">
+ <tr>
+ <td class="mlabels-left">
+ <table class="memname">
+ <tr>
+ <td class="memname">static void CSL_dssVidPipeMFlagCfgInit </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="struct_c_s_l___dss_vid_pipe_m_flag_cfg.html">CSL_DssVidPipeMFlagCfg</a> * </td>
+ <td class="paramname"><em>mflagCfg</em></td><td>)</td>
+ <td></td>
+ </tr>
+ </table>
+ </td>
+ <td class="mlabels-right">
+<span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span> </td>
+ </tr>
+</table>
+</div><div class="memdoc">
+
+<p><a class="el" href="struct_c_s_l___dss_vid_pipe_m_flag_cfg.html" title="DSS Video Pipe MFLAG Config parameters. ">CSL_DssVidPipeMFlagCfg</a> structure init function. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">mflagCfg</td><td>Pointer to <a class="el" href="struct_c_s_l___dss_vid_pipe_m_flag_cfg.html" title="DSS Video Pipe MFLAG Config parameters. ">CSL_DssVidPipeMFlagCfg</a> structure</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga3646182313235e92362cd843fdc6c2e6"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">void CSL_dssVidPipeSetAlphaConfig </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gafdca0345c9254a9bdbcd6e4a2ee000f6">CSL_dss_pipeRegs</a> * </td>
+ <td class="paramname"><em>pipeRegs</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">const <a class="el" href="struct_c_s_l___dss_vid_pipe_alpha_cfg.html">CSL_DssVidPipeAlphaCfg</a> * </td>
+ <td class="paramname"><em>alphaCfg</em> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td></td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+
+<p>Set DSS Video Pipe Alpha parameters. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">pipeRegs</td><td>Pointer to a <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gafdca0345c9254a9bdbcd6e4a2ee000f6" title="DSS Video Pipe Registers. ">CSL_dss_pipeRegs</a> structure containing the Video Pipe configuration </td></tr>
+ <tr><td class="paramname">alphaCfg</td><td>Pointer to the <a class="el" href="struct_c_s_l___dss_vid_pipe_alpha_cfg.html" title="DSS Video Pipe Alpha Config parameters. ">CSL_DssVidPipeAlphaCfg</a> structure. This parameter should not be NULL</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga11ed49990e9b63ecbf167cff5f6a9755"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">void CSL_dssVidPipeSetBuffAddr </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gafdca0345c9254a9bdbcd6e4a2ee000f6">CSL_dss_pipeRegs</a> * </td>
+ <td class="paramname"><em>pipeRegs</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">uint32_t </td>
+ <td class="paramname"><em>field</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">uint64_t </td>
+ <td class="paramname"><em>baseAddrRGBY</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">uint64_t </td>
+ <td class="paramname"><em>baseAddrUV</em> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td></td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+
+<p>Configure the coefficients for Color Space Conversion. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">pipeRegs</td><td>Pointer to a <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gafdca0345c9254a9bdbcd6e4a2ee000f6" title="DSS Video Pipe Registers. ">CSL_dss_pipeRegs</a> structure containing the Video Pipe configuration </td></tr>
+ <tr><td class="paramname">field</td><td>Top or bottom field. Refer <a class="el" href="csl__fvid2__data_types_8h.html#a46dbb7460c568075f1cd6959282d87cb" title="Top field. ">Fvid2_Fid</a> for values. Top is even field and Bottom is odd </td></tr>
+ <tr><td class="paramname">baseAddrRGBY</td><td>Base address of RGB or Y plane depending on format </td></tr>
+ <tr><td class="paramname">baseAddrUV</td><td>UV base address valid only for YUV420-NV12/NV21</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga6d983ffe721b5a1b602bfa53995f1c76"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">int32_t CSL_dssVidPipeSetConfig </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gafdca0345c9254a9bdbcd6e4a2ee000f6">CSL_dss_pipeRegs</a> * </td>
+ <td class="paramname"><em>pipeRegs</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">const <a class="el" href="struct_c_s_l___dss_vid_pipe_cfg.html">CSL_DssVidPipeCfg</a> * </td>
+ <td class="paramname"><em>pipeCfg</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">const <a class="el" href="struct_c_s_l___dss_vid_pipe_v_c1_cfg.html">CSL_DssVidPipeVC1Cfg</a> * </td>
+ <td class="paramname"><em>vc1Cfg</em> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td></td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+
+<p>Configure the Video Pipe. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">pipeRegs</td><td>Pointer to a <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gafdca0345c9254a9bdbcd6e4a2ee000f6" title="DSS Video Pipe Registers. ">CSL_dss_pipeRegs</a> structure containing the Video Pipe configuration </td></tr>
+ <tr><td class="paramname">pipeCfg</td><td>Pointer to the <a class="el" href="struct_c_s_l___dss_vid_pipe_cfg.html" title="Configuration for DSS Video Pipe. ">CSL_DssVidPipeCfg</a> structure. This parameter should not be NULL </td></tr>
+ <tr><td class="paramname">vc1Cfg</td><td>Pointer to the <a class="el" href="struct_c_s_l___dss_vid_pipe_v_c1_cfg.html" title="DSS Video Pipe VC1 configuration. ">CSL_DssVidPipeVC1Cfg</a> structure. This parameter should not be NULL</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>CSL_ErrType_t </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="gacebfcb0b4ae57fa7a1ce3c73f6b552e8"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">void CSL_dssVidPipeSetCSCCoeff </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gafdca0345c9254a9bdbcd6e4a2ee000f6">CSL_dss_pipeRegs</a> * </td>
+ <td class="paramname"><em>pipeRegs</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">const <a class="el" href="struct_c_s_l___dss_csc_coeff.html">CSL_DssCscCoeff</a> * </td>
+ <td class="paramname"><em>coeff</em> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td></td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+
+<p>Configure the coefficients for Color Space Conversion. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">pipeRegs</td><td>Pointer to a <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gafdca0345c9254a9bdbcd6e4a2ee000f6" title="DSS Video Pipe Registers. ">CSL_dss_pipeRegs</a> structure containing the Video Pipe configuration </td></tr>
+ <tr><td class="paramname">coeff</td><td>Pointer to <a class="el" href="struct_c_s_l___dss_csc_coeff.html" title="Structure containing coefficients for Color Space Conversion. ">CSL_DssCscCoeff</a> structure. This parameter should not be NULL</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="gaf3bd47c49aa8edd65bfd202779cdd0a2"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">void CSL_dssVidPipeSetDmaConfig </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gafdca0345c9254a9bdbcd6e4a2ee000f6">CSL_dss_pipeRegs</a> * </td>
+ <td class="paramname"><em>pipeRegs</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">const <a class="el" href="struct_c_s_l___dss_vid_pipe_dma_cfg.html">CSL_DssVidPipeDmaCfg</a> * </td>
+ <td class="paramname"><em>dmaCfg</em> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td></td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+
+<p>Configure the Video Pipe DMA parameters. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">pipeRegs</td><td>Pointer to a <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gafdca0345c9254a9bdbcd6e4a2ee000f6" title="DSS Video Pipe Registers. ">CSL_dss_pipeRegs</a> structure containing the Video Pipe configuration </td></tr>
+ <tr><td class="paramname">dmaCfg</td><td>Pointer to the <a class="el" href="struct_c_s_l___dss_vid_pipe_dma_cfg.html" title="DSS Video Pipe DMA related Config parameters. ">CSL_DssVidPipeDmaCfg</a> structure. This parameter should not be NULL</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga3095d9a0f35cd85fba7c2be6b14d798d"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">void CSL_dssVidPipeSetMflagConfig </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gafdca0345c9254a9bdbcd6e4a2ee000f6">CSL_dss_pipeRegs</a> * </td>
+ <td class="paramname"><em>pipeRegs</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">const <a class="el" href="struct_c_s_l___dss_vid_pipe_m_flag_cfg.html">CSL_DssVidPipeMFlagCfg</a> * </td>
+ <td class="paramname"><em>mflagCfg</em> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td></td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+
+<p>Set the MFLAG configuration. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">pipeRegs</td><td>Pointer to a <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gafdca0345c9254a9bdbcd6e4a2ee000f6" title="DSS Video Pipe Registers. ">CSL_dss_pipeRegs</a> structure containing the Video Pipe configuration </td></tr>
+ <tr><td class="paramname">mflagCfg</td><td>Pointer to <a class="el" href="struct_c_s_l___dss_vid_pipe_m_flag_cfg.html" title="DSS Video Pipe MFLAG Config parameters. ">CSL_DssVidPipeMFlagCfg</a> structure. This parameter should not be NULL</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="gae5dc5282a40648fd2f69165e7a373265"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">void CSL_dssVidPipeSetSafetyChkConfig </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gafdca0345c9254a9bdbcd6e4a2ee000f6">CSL_dss_pipeRegs</a> * </td>
+ <td class="paramname"><em>pipeRegs</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">const <a class="el" href="struct_c_s_l___dss_safety_chk_cfg.html">CSL_DssSafetyChkCfg</a> * </td>
+ <td class="paramname"><em>safetyCfg</em> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td></td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+
+<p>Configure the Safety Check Params. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">pipeRegs</td><td>Pointer to a <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gafdca0345c9254a9bdbcd6e4a2ee000f6" title="DSS Video Pipe Registers. ">CSL_dss_pipeRegs</a> structure containing the Video Pipe configuration </td></tr>
+ <tr><td class="paramname">safetyCfg</td><td>Pointer to <a class="el" href="struct_c_s_l___dss_safety_chk_cfg.html" title="Configuration for doing safety checks. ">CSL_DssSafetyChkCfg</a> structure. This parameter should not be NULL</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga37238e9b68bd88742eb54cca7c3cd7a8"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">void CSL_dssVidPipeSetSafetyReferenceSign </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gafdca0345c9254a9bdbcd6e4a2ee000f6">CSL_dss_pipeRegs</a> * </td>
+ <td class="paramname"><em>pipeRegs</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">uint32_t </td>
+ <td class="paramname"><em>referenceSign</em> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td></td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+
+<p>Set the reference safety signature for data correctness check. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">pipeRegs</td><td>Pointer to a <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gafdca0345c9254a9bdbcd6e4a2ee000f6" title="DSS Video Pipe Registers. ">CSL_dss_pipeRegs</a> structure containing the Video Pipe configuration </td></tr>
+ <tr><td class="paramname">referenceSign</td><td>Reference Safety Signature</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga70f77613b5b22a937388f5b072a7f74d"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">void CSL_dssVidPipeSetSafetySignSeedVal </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gafdca0345c9254a9bdbcd6e4a2ee000f6">CSL_dss_pipeRegs</a> * </td>
+ <td class="paramname"><em>pipeRegs</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">uint32_t </td>
+ <td class="paramname"><em>signSeedVal</em> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td></td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+
+<p>Set the seed value for the signature calculation. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">pipeRegs</td><td>Pointer to a <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#gafdca0345c9254a9bdbcd6e4a2ee000f6" title="DSS Video Pipe Registers. ">CSL_dss_pipeRegs</a> structure containing the Video Pipe configuration </td></tr>
+ <tr><td class="paramname">signSeedVal</td><td>Signature Seed Value to be Set</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="gaf11746b1003b15855996b817cfe3d38a"></a>
+<div class="memitem">
+<div class="memproto">
+<table class="mlabels">
+ <tr>
+ <td class="mlabels-left">
+ <table class="memname">
+ <tr>
+ <td class="memname">static void CSL_dssVidPipeVC1CfgInit </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="struct_c_s_l___dss_vid_pipe_v_c1_cfg.html">CSL_DssVidPipeVC1Cfg</a> * </td>
+ <td class="paramname"><em>vc1Cfg</em></td><td>)</td>
+ <td></td>
+ </tr>
+ </table>
+ </td>
+ <td class="mlabels-right">
+<span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span> </td>
+ </tr>
+</table>
+</div><div class="memdoc">
+
+<p><a class="el" href="struct_c_s_l___dss_vid_pipe_v_c1_cfg.html" title="DSS Video Pipe VC1 configuration. ">CSL_DssVidPipeVC1Cfg</a> structure init function. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">vc1Cfg</td><td>Pointer to <a class="el" href="struct_c_s_l___dss_vid_pipe_v_c1_cfg.html" title="DSS Video Pipe VC1 configuration. ">CSL_DssVidPipeVC1Cfg</a> structure</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None </dd></dl>
+
+</div>
+</div>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html b/packages/ti/drv/dss/docs/doxygen/html/group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html
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+<a href="#func-members">Functions</a> </div>
+ <div class="headertitle">
+<div class="title">DSS Video Port CSL FL<div class="ingroups"><a class="el" href="group___c_s_l___d_s_s.html">DSS</a></div></div> </div>
+</div><!--header-->
+<div class="contents">
+<table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="files"></a>
+Files</h2></td></tr>
+<tr class="memitem:csl__dss_video_port_8h"><td class="memItemLeft" align="right" valign="top">file  </td><td class="memItemRight" valign="bottom"><a class="el" href="csl__dss_video_port_8h.html">csl_dssVideoPort.h</a></td></tr>
+<tr class="memdesc:csl__dss_video_port_8h"><td class="mdescLeft"> </td><td class="mdescRight">DSS Video Port CSL FL interface file. <br/></td></tr>
+<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="nested-classes"></a>
+Data Structures</h2></td></tr>
+<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_vp_gamma_cfg.html">CSL_DssVpGammaCfg</a></td></tr>
+<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">Gamma Correction configuration for DSS Video Port Output. <a href="struct_c_s_l___dss_vp_gamma_cfg.html#details">More...</a><br/></td></tr>
+<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_vp_lcd_tdm_cfg.html">CSL_DssVpLcdTdmCfg</a></td></tr>
+<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">LCD Configuration for Time Division Multiplexing. <a href="struct_c_s_l___dss_vp_lcd_tdm_cfg.html#details">More...</a><br/></td></tr>
+<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_vp_lcd_signal_polarity_cfg.html">CSL_DssVpLcdSignalPolarityCfg</a></td></tr>
+<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">Polarity of Active Video, Pixel Clock, HSync and VSync signals for the LCD. <a href="struct_c_s_l___dss_vp_lcd_signal_polarity_cfg.html#details">More...</a><br/></td></tr>
+<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_vp_lcd_adv_signal_cfg.html">CSL_DssVpLcdAdvSignalCfg</a></td></tr>
+<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">Advance Signal Configuration for the LCD. <a href="struct_c_s_l___dss_vp_lcd_adv_signal_cfg.html#details">More...</a><br/></td></tr>
+<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_vp_lcd_op_timing_cfg.html">CSL_DssVpLcdOpTimingCfg</a></td></tr>
+<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">Timing configuration for the LCD output. <a href="struct_c_s_l___dss_vp_lcd_op_timing_cfg.html#details">More...</a><br/></td></tr>
+<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_vp_lcd_blank_timing_cfg.html">CSL_DssVpLcdBlankTimingCfg</a></td></tr>
+<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">Blanking Timing parameters for the LCD. <a href="struct_c_s_l___dss_vp_lcd_blank_timing_cfg.html#details">More...</a><br/></td></tr>
+<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="typedef-members"></a>
+Typedefs</h2></td></tr>
+<tr class="memitem:gaaaf231996a0d81bd23a1460d729dad23"><td class="memItemLeft" align="right" valign="top">typedef CSL_dss_vp1Regs </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gaaaf231996a0d81bd23a1460d729dad23">CSL_dss_vpRegs</a></td></tr>
+<tr class="memdesc:gaaaf231996a0d81bd23a1460d729dad23"><td class="mdescLeft"> </td><td class="mdescRight">DSS Video Port Registers. <a href="#gaaaf231996a0d81bd23a1460d729dad23">More...</a><br/></td></tr>
+<tr class="separator:gaaaf231996a0d81bd23a1460d729dad23"><td class="memSeparator" colspan="2"> </td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a>
+Functions</h2></td></tr>
+<tr class="memitem:ga9c61092eddfa87bcba87cc116fb8bd1d"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga9c61092eddfa87bcba87cc116fb8bd1d">CSL_dssVpEnable</a> (<a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gaaaf231996a0d81bd23a1460d729dad23">CSL_dss_vpRegs</a> *vpRegs, uint32_t enable)</td></tr>
+<tr class="memdesc:ga9c61092eddfa87bcba87cc116fb8bd1d"><td class="mdescLeft"> </td><td class="mdescRight">Enable the DSS Video Port. <a href="#ga9c61092eddfa87bcba87cc116fb8bd1d">More...</a><br/></td></tr>
+<tr class="separator:ga9c61092eddfa87bcba87cc116fb8bd1d"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga0ba989884315a28b21a62a722574865d"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga0ba989884315a28b21a62a722574865d">CSL_dssVpSetGoBit</a> (<a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gaaaf231996a0d81bd23a1460d729dad23">CSL_dss_vpRegs</a> *vpRegs)</td></tr>
+<tr class="memdesc:ga0ba989884315a28b21a62a722574865d"><td class="mdescLeft"> </td><td class="mdescRight">GO Command for the VP output. It is used to synchronize the pipelines associated with the VP output. <a href="#ga0ba989884315a28b21a62a722574865d">More...</a><br/></td></tr>
+<tr class="separator:ga0ba989884315a28b21a62a722574865d"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga48c44cb30d94ee22ddd885998830d852"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga48c44cb30d94ee22ddd885998830d852">CSL_dssVpSetLcdTdmConfig</a> (<a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gaaaf231996a0d81bd23a1460d729dad23">CSL_dss_vpRegs</a> *vpRegs, const <a class="el" href="struct_c_s_l___dss_vp_lcd_tdm_cfg.html">CSL_DssVpLcdTdmCfg</a> *lcdTdmCfg)</td></tr>
+<tr class="memdesc:ga48c44cb30d94ee22ddd885998830d852"><td class="mdescLeft"> </td><td class="mdescRight">Configure the LCD TDM(Time division multiplexing) parameters. <a href="#ga48c44cb30d94ee22ddd885998830d852">More...</a><br/></td></tr>
+<tr class="separator:ga48c44cb30d94ee22ddd885998830d852"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga1a4f05443f8ba7bffea84d63b43788ab"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga1a4f05443f8ba7bffea84d63b43788ab">CSL_dssVpSetLcdLineNum</a> (<a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gaaaf231996a0d81bd23a1460d729dad23">CSL_dss_vpRegs</a> *vpRegs, uint32_t lineNum)</td></tr>
+<tr class="memdesc:ga1a4f05443f8ba7bffea84d63b43788ab"><td class="mdescLeft"> </td><td class="mdescRight">Set the Line Number at which the interrupt should be generated. <a href="#ga1a4f05443f8ba7bffea84d63b43788ab">More...</a><br/></td></tr>
+<tr class="separator:ga1a4f05443f8ba7bffea84d63b43788ab"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga447444c64439d7b1210a9b696dd8a673"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga447444c64439d7b1210a9b696dd8a673">CSL_dssVpGetLcdLineNum</a> (const <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gaaaf231996a0d81bd23a1460d729dad23">CSL_dss_vpRegs</a> *vpRegs)</td></tr>
+<tr class="memdesc:ga447444c64439d7b1210a9b696dd8a673"><td class="mdescLeft"> </td><td class="mdescRight">Get the number of line currently displayed. <a href="#ga447444c64439d7b1210a9b696dd8a673">More...</a><br/></td></tr>
+<tr class="separator:ga447444c64439d7b1210a9b696dd8a673"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga0225f72557517955d94f1a6ce815ed14"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga0225f72557517955d94f1a6ce815ed14">CSL_dssVpSetLcdOpTimingConfig</a> (<a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gaaaf231996a0d81bd23a1460d729dad23">CSL_dss_vpRegs</a> *vpRegs, const <a class="el" href="struct_c_s_l___dss_vp_lcd_op_timing_cfg.html">CSL_DssVpLcdOpTimingCfg</a> *lcdCfg)</td></tr>
+<tr class="memdesc:ga0225f72557517955d94f1a6ce815ed14"><td class="mdescLeft"> </td><td class="mdescRight">Configure the LCD Timing parameters. <a href="#ga0225f72557517955d94f1a6ce815ed14">More...</a><br/></td></tr>
+<tr class="separator:ga0225f72557517955d94f1a6ce815ed14"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga5f52bab6e5e9242d6f77faf995a4de6e"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga5f52bab6e5e9242d6f77faf995a4de6e">CSL_dssVpSetLcdBlankTiming</a> (<a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gaaaf231996a0d81bd23a1460d729dad23">CSL_dss_vpRegs</a> *vpRegs, const <a class="el" href="struct_c_s_l___dss_vp_lcd_blank_timing_cfg.html">CSL_DssVpLcdBlankTimingCfg</a> *blankCfg, uint32_t dvoFormat, uint32_t scanFormat, uint32_t isCustomTiming)</td></tr>
+<tr class="memdesc:ga5f52bab6e5e9242d6f77faf995a4de6e"><td class="mdescLeft"> </td><td class="mdescRight">Configure the LCD Blank Timing parameters. <a href="#ga5f52bab6e5e9242d6f77faf995a4de6e">More...</a><br/></td></tr>
+<tr class="separator:ga5f52bab6e5e9242d6f77faf995a4de6e"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga45dfca83a394f21328886b7ad7d89056"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga45dfca83a394f21328886b7ad7d89056">CSL_dssVpSetLcdAdvSignalConfig</a> (<a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gaaaf231996a0d81bd23a1460d729dad23">CSL_dss_vpRegs</a> *vpRegs, const <a class="el" href="struct_c_s_l___dss_vp_lcd_adv_signal_cfg.html">CSL_DssVpLcdAdvSignalCfg</a> *advSignalCfg)</td></tr>
+<tr class="memdesc:ga45dfca83a394f21328886b7ad7d89056"><td class="mdescLeft"> </td><td class="mdescRight">Configure the advance LCD Signal parameters. <a href="#ga45dfca83a394f21328886b7ad7d89056">More...</a><br/></td></tr>
+<tr class="separator:ga45dfca83a394f21328886b7ad7d89056"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga75453549b6c9c05da750b55cdb2a8ad3"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga75453549b6c9c05da750b55cdb2a8ad3">CSL_dssVpSetLcdSignalPolarityConfig</a> (<a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gaaaf231996a0d81bd23a1460d729dad23">CSL_dss_vpRegs</a> *vpRegs, const <a class="el" href="struct_c_s_l___dss_vp_lcd_signal_polarity_cfg.html">CSL_DssVpLcdSignalPolarityCfg</a> *polarityCfg)</td></tr>
+<tr class="memdesc:ga75453549b6c9c05da750b55cdb2a8ad3"><td class="mdescLeft"> </td><td class="mdescRight">Configure the Polarity of LCD signals(HSYNC, VSYNC, PCLK, Data) <a href="#ga75453549b6c9c05da750b55cdb2a8ad3">More...</a><br/></td></tr>
+<tr class="separator:ga75453549b6c9c05da750b55cdb2a8ad3"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga253c3416c174352edcda17c4ca271013"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga253c3416c174352edcda17c4ca271013">CSL_dssVpEnableTvGamma</a> (<a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gaaaf231996a0d81bd23a1460d729dad23">CSL_dss_vpRegs</a> *vpRegs, const <a class="el" href="struct_c_s_l___dss_vp_gamma_cfg.html">CSL_DssVpGammaCfg</a> *gammaCfg)</td></tr>
+<tr class="memdesc:ga253c3416c174352edcda17c4ca271013"><td class="mdescLeft"> </td><td class="mdescRight">Enable/Bypass TV Gamma Table. <a href="#ga253c3416c174352edcda17c4ca271013">More...</a><br/></td></tr>
+<tr class="separator:ga253c3416c174352edcda17c4ca271013"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga7d36af9cdba47ad2622758fd632980ce"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga7d36af9cdba47ad2622758fd632980ce">CSL_dssVpSetCSCCoeff</a> (<a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gaaaf231996a0d81bd23a1460d729dad23">CSL_dss_vpRegs</a> *vpRegs, const <a class="el" href="struct_c_s_l___dss_csc_coeff.html">CSL_DssCscCoeff</a> *cscCoeff, uint32_t cscPos, uint32_t cscEnable)</td></tr>
+<tr class="memdesc:ga7d36af9cdba47ad2622758fd632980ce"><td class="mdescLeft"> </td><td class="mdescRight">Configure the coefficients for Color Space Conversion. <a href="#ga7d36af9cdba47ad2622758fd632980ce">More...</a><br/></td></tr>
+<tr class="separator:ga7d36af9cdba47ad2622758fd632980ce"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga1bc9995f9958912a188ae2a98351aec5"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga1bc9995f9958912a188ae2a98351aec5">CSL_dssVpSetSafetySignSeedVal</a> (<a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gaaaf231996a0d81bd23a1460d729dad23">CSL_dss_vpRegs</a> *vpRegs, uint32_t signSeedVal)</td></tr>
+<tr class="memdesc:ga1bc9995f9958912a188ae2a98351aec5"><td class="mdescLeft"> </td><td class="mdescRight">Set the seed value for the signature calculation. <a href="#ga1bc9995f9958912a188ae2a98351aec5">More...</a><br/></td></tr>
+<tr class="separator:ga1bc9995f9958912a188ae2a98351aec5"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga20bfb7e29029c7256d6766b9b05f5f23"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga20bfb7e29029c7256d6766b9b05f5f23">CSL_dssVpSetSafetyReferenceSign</a> (<a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gaaaf231996a0d81bd23a1460d729dad23">CSL_dss_vpRegs</a> *vpRegs, uint32_t referenceSign, uint32_t regionId)</td></tr>
+<tr class="memdesc:ga20bfb7e29029c7256d6766b9b05f5f23"><td class="mdescLeft"> </td><td class="mdescRight">Set the reference safety signature for data correctness check. <a href="#ga20bfb7e29029c7256d6766b9b05f5f23">More...</a><br/></td></tr>
+<tr class="separator:ga20bfb7e29029c7256d6766b9b05f5f23"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gad2853dae9324aa61cbb332d14b308da6"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gad2853dae9324aa61cbb332d14b308da6">CSL_dssVpSetSafetyChkConfig</a> (<a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gaaaf231996a0d81bd23a1460d729dad23">CSL_dss_vpRegs</a> *vpRegs, const <a class="el" href="struct_c_s_l___dss_safety_chk_cfg.html">CSL_DssSafetyChkCfg</a> *safetyCfg, uint32_t regionId)</td></tr>
+<tr class="memdesc:gad2853dae9324aa61cbb332d14b308da6"><td class="mdescLeft"> </td><td class="mdescRight">Configure the Safety Check parameters. <a href="#gad2853dae9324aa61cbb332d14b308da6">More...</a><br/></td></tr>
+<tr class="separator:gad2853dae9324aa61cbb332d14b308da6"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga7f7b411493687d0d758ff8b047a23712"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga7f7b411493687d0d758ff8b047a23712">CSL_dssVpGetSafetySign</a> (const <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gaaaf231996a0d81bd23a1460d729dad23">CSL_dss_vpRegs</a> *vpRegs, uint32_t regionId)</td></tr>
+<tr class="memdesc:ga7f7b411493687d0d758ff8b047a23712"><td class="mdescLeft"> </td><td class="mdescRight">Get the Safety Signature of the sub region. <a href="#ga7f7b411493687d0d758ff8b047a23712">More...</a><br/></td></tr>
+<tr class="separator:ga7f7b411493687d0d758ff8b047a23712"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga08a68b5de9d2c6646b0654ccad3b9600"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga08a68b5de9d2c6646b0654ccad3b9600">CSL_dssVpStallModeEnable</a> (<a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gaaaf231996a0d81bd23a1460d729dad23">CSL_dss_vpRegs</a> *vpRegs, uint32_t enable, uint32_t stallModeType)</td></tr>
+<tr class="memdesc:ga08a68b5de9d2c6646b0654ccad3b9600"><td class="mdescLeft"> </td><td class="mdescRight">Enable/disable the Video Port stall mode. <a href="#ga08a68b5de9d2c6646b0654ccad3b9600">More...</a><br/></td></tr>
+<tr class="separator:ga08a68b5de9d2c6646b0654ccad3b9600"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga709fdcc02c1f82d9a3b595ad67b9f086"><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga709fdcc02c1f82d9a3b595ad67b9f086">CSL_dssVpGammaCfgInit</a> (<a class="el" href="struct_c_s_l___dss_vp_gamma_cfg.html">CSL_DssVpGammaCfg</a> *gammaCfg)</td></tr>
+<tr class="memdesc:ga709fdcc02c1f82d9a3b595ad67b9f086"><td class="mdescLeft"> </td><td class="mdescRight"><a class="el" href="struct_c_s_l___dss_vp_gamma_cfg.html" title="Gamma Correction configuration for DSS Video Port Output. ">CSL_DssVpGammaCfg</a> structure init function. <a href="#ga709fdcc02c1f82d9a3b595ad67b9f086">More...</a><br/></td></tr>
+<tr class="separator:ga709fdcc02c1f82d9a3b595ad67b9f086"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gaf276b6af542ab92fa03bf0af6d1af1cb"><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gaf276b6af542ab92fa03bf0af6d1af1cb">CSL_dssVpLcdTdmCfgInit</a> (<a class="el" href="struct_c_s_l___dss_vp_lcd_tdm_cfg.html">CSL_DssVpLcdTdmCfg</a> *tdmCfg)</td></tr>
+<tr class="memdesc:gaf276b6af542ab92fa03bf0af6d1af1cb"><td class="mdescLeft"> </td><td class="mdescRight"><a class="el" href="struct_c_s_l___dss_vp_lcd_tdm_cfg.html" title="LCD Configuration for Time Division Multiplexing. ">CSL_DssVpLcdTdmCfg</a> structure init function. <a href="#gaf276b6af542ab92fa03bf0af6d1af1cb">More...</a><br/></td></tr>
+<tr class="separator:gaf276b6af542ab92fa03bf0af6d1af1cb"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga158b9aed148e3a14e1bff1cb8613bc67"><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga158b9aed148e3a14e1bff1cb8613bc67">CSL_dssVpLcdSignalPolarityCfgInit</a> (<a class="el" href="struct_c_s_l___dss_vp_lcd_signal_polarity_cfg.html">CSL_DssVpLcdSignalPolarityCfg</a> *polarityCfg)</td></tr>
+<tr class="memdesc:ga158b9aed148e3a14e1bff1cb8613bc67"><td class="mdescLeft"> </td><td class="mdescRight"><a class="el" href="struct_c_s_l___dss_vp_lcd_signal_polarity_cfg.html" title="Polarity of Active Video, Pixel Clock, HSync and VSync signals for the LCD. ">CSL_DssVpLcdSignalPolarityCfg</a> structure init function. <a href="#ga158b9aed148e3a14e1bff1cb8613bc67">More...</a><br/></td></tr>
+<tr class="separator:ga158b9aed148e3a14e1bff1cb8613bc67"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga50f5efd31f31736019ee265e3078d4ef"><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga50f5efd31f31736019ee265e3078d4ef">CSL_dssVpLcdAdvSignalCfgInit</a> (<a class="el" href="struct_c_s_l___dss_vp_lcd_adv_signal_cfg.html">CSL_DssVpLcdAdvSignalCfg</a> *advSignalCfg)</td></tr>
+<tr class="memdesc:ga50f5efd31f31736019ee265e3078d4ef"><td class="mdescLeft"> </td><td class="mdescRight"><a class="el" href="struct_c_s_l___dss_vp_lcd_adv_signal_cfg.html" title="Advance Signal Configuration for the LCD. ">CSL_DssVpLcdAdvSignalCfg</a> structure init function. <a href="#ga50f5efd31f31736019ee265e3078d4ef">More...</a><br/></td></tr>
+<tr class="separator:ga50f5efd31f31736019ee265e3078d4ef"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga2be9daed03e91c1706a4075be86a7054"><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga2be9daed03e91c1706a4075be86a7054">CSL_dssVpLcdOpTimingCfgInit</a> (<a class="el" href="struct_c_s_l___dss_vp_lcd_op_timing_cfg.html">CSL_DssVpLcdOpTimingCfg</a> *lcdCfg)</td></tr>
+<tr class="memdesc:ga2be9daed03e91c1706a4075be86a7054"><td class="mdescLeft"> </td><td class="mdescRight"><a class="el" href="struct_c_s_l___dss_vp_lcd_op_timing_cfg.html" title="Timing configuration for the LCD output. ">CSL_DssVpLcdOpTimingCfg</a> structure init function. <a href="#ga2be9daed03e91c1706a4075be86a7054">More...</a><br/></td></tr>
+<tr class="separator:ga2be9daed03e91c1706a4075be86a7054"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gadd1a815002453481cce4f9dbf8da864a"><td class="memItemLeft" align="right" valign="top">static void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gadd1a815002453481cce4f9dbf8da864a">CSL_dssVpLcdBlankTimingCfgInit</a> (<a class="el" href="struct_c_s_l___dss_vp_lcd_blank_timing_cfg.html">CSL_DssVpLcdBlankTimingCfg</a> *blankCfg)</td></tr>
+<tr class="memdesc:gadd1a815002453481cce4f9dbf8da864a"><td class="mdescLeft"> </td><td class="mdescRight"><a class="el" href="struct_c_s_l___dss_vp_lcd_blank_timing_cfg.html" title="Blanking Timing parameters for the LCD. ">CSL_DssVpLcdBlankTimingCfg</a> structure init function. <a href="#gadd1a815002453481cce4f9dbf8da864a">More...</a><br/></td></tr>
+<tr class="separator:gadd1a815002453481cce4f9dbf8da864a"><td class="memSeparator" colspan="2"> </td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
+Video Port CSC Position</h2></td></tr>
+<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrp5c98f183d6d614428e30591f620cee49"></a>DSS Video Port Color Space Conversion block position wrt Gamma block</p>
+<p><a class="anchor" id="CSL_DssVpCscPos"></a></p>
+</td></tr>
+<tr class="memitem:ga9d8db056eb5e4a6dc1972200c70acf09"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga9d8db056eb5e4a6dc1972200c70acf09"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga9d8db056eb5e4a6dc1972200c70acf09">CSL_DSS_VP_CSC_POS_AFTER_GAMMA</a>   ((uint32_t) CSL_DSS_VP1_CONFIG_COLORCONVPOS_VAL_AFTERGAMMA)</td></tr>
+<tr class="memdesc:ga9d8db056eb5e4a6dc1972200c70acf09"><td class="mdescLeft"> </td><td class="mdescRight">CSC block is after GAMMA correction. <br/></td></tr>
+<tr class="separator:ga9d8db056eb5e4a6dc1972200c70acf09"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga7adc25e7daeddfff398a028a6f7af0b8"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga7adc25e7daeddfff398a028a6f7af0b8"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga7adc25e7daeddfff398a028a6f7af0b8">CSL_DSS_VP_CSC_POS_BEFORE_GAMMA</a>   ((uint32_t) CSL_DSS_VP1_CONFIG_COLORCONVPOS_VAL_BEFOREGAMMA)</td></tr>
+<tr class="memdesc:ga7adc25e7daeddfff398a028a6f7af0b8"><td class="mdescLeft"> </td><td class="mdescRight">CSC block is before GAMMA correction. <br/></td></tr>
+<tr class="separator:ga7adc25e7daeddfff398a028a6f7af0b8"><td class="memSeparator" colspan="2"> </td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
+TDM Mode Unused Bits Level</h2></td></tr>
+<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrpe503bc1271fa1044b5d90a1140b221c2"></a>State of unused bits in TDM mode for the VP output</p>
+<p><a class="anchor" id="CSL_DssVpTdmUnusedBitsLevel"></a></p>
+</td></tr>
+<tr class="memitem:gab2d941b89a9b42c988e72d4500379661"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gab2d941b89a9b42c988e72d4500379661"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gab2d941b89a9b42c988e72d4500379661">CSL_DSS_VP_TDM_UNUSED_BITS_LEVEL_LOW</a>   ((uint32_t) CSL_DSS_VP1_CONTROL_TDMUNUSEDBITS_VAL_LOWLEVEL)</td></tr>
+<tr class="memdesc:gab2d941b89a9b42c988e72d4500379661"><td class="mdescLeft"> </td><td class="mdescRight">Low level. <br/></td></tr>
+<tr class="separator:gab2d941b89a9b42c988e72d4500379661"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gac426f8586cc7293b20148c1dfd1cec3a"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gac426f8586cc7293b20148c1dfd1cec3a"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gac426f8586cc7293b20148c1dfd1cec3a">CSL_DSS_VP_TDM_UNUSED_BITS_LEVEL_HIGH</a>   ((uint32_t) CSL_DSS_VP1_CONTROL_TDMUNUSEDBITS_VAL_HIGHLEVEL)</td></tr>
+<tr class="memdesc:gac426f8586cc7293b20148c1dfd1cec3a"><td class="mdescLeft"> </td><td class="mdescRight">High level. <br/></td></tr>
+<tr class="separator:gac426f8586cc7293b20148c1dfd1cec3a"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga58a52d1ec3bd962fe6ec5996d788cbe5"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga58a52d1ec3bd962fe6ec5996d788cbe5"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga58a52d1ec3bd962fe6ec5996d788cbe5">CSL_DSS_VP_TDM_UNUSED_BITS_LEVEL_UNCHANGED</a>   ((uint32_t) CSL_DSS_VP1_CONTROL_TDMUNUSEDBITS_VAL_UNCHANGED)</td></tr>
+<tr class="memdesc:ga58a52d1ec3bd962fe6ec5996d788cbe5"><td class="mdescLeft"> </td><td class="mdescRight">Unchanged level. <br/></td></tr>
+<tr class="separator:ga58a52d1ec3bd962fe6ec5996d788cbe5"><td class="memSeparator" colspan="2"> </td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
+TDM Cycle format</h2></td></tr>
+<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrp88d40159c6c0ee98c67bb6ebb9f20e1e"></a><a class="anchor" id="CSL_DssVpTdmCycleFormat"></a></p>
+</td></tr>
+<tr class="memitem:ga5b4659b24eb81a27c27f0d409fd51460"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga5b4659b24eb81a27c27f0d409fd51460"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga5b4659b24eb81a27c27f0d409fd51460">CSL_DSS_VP_TDM_CYCLE_1PERPIXEL</a>   ((uint32_t) CSL_DSS_VP1_CONTROL_TDMCYCLEFORMAT_VAL_1CYCPERPIX)</td></tr>
+<tr class="memdesc:ga5b4659b24eb81a27c27f0d409fd51460"><td class="mdescLeft"> </td><td class="mdescRight">1 cycle per pixel <br/></td></tr>
+<tr class="separator:ga5b4659b24eb81a27c27f0d409fd51460"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga5c6498fbbc637492bee5fec53327d8d2"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga5c6498fbbc637492bee5fec53327d8d2"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga5c6498fbbc637492bee5fec53327d8d2">CSL_DSS_VP_TDM_CYCLE_2PERPIXEL</a>   ((uint32_t) CSL_DSS_VP1_CONTROL_TDMCYCLEFORMAT_VAL_2CYCPERPIX)</td></tr>
+<tr class="memdesc:ga5c6498fbbc637492bee5fec53327d8d2"><td class="mdescLeft"> </td><td class="mdescRight">2 cycles per pixel <br/></td></tr>
+<tr class="separator:ga5c6498fbbc637492bee5fec53327d8d2"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga9f47ee0306de87ccadf8e16a57276cf0"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga9f47ee0306de87ccadf8e16a57276cf0"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga9f47ee0306de87ccadf8e16a57276cf0">CSL_DSS_VP_TDM_CYCLE_3PERPIXEL</a>   ((uint32_t) CSL_DSS_VP1_CONTROL_TDMCYCLEFORMAT_VAL_3CYCPERPIX)</td></tr>
+<tr class="memdesc:ga9f47ee0306de87ccadf8e16a57276cf0"><td class="mdescLeft"> </td><td class="mdescRight">3 cycles per pixel <br/></td></tr>
+<tr class="separator:ga9f47ee0306de87ccadf8e16a57276cf0"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga81528f8f4538347b9f0b9e5b1c47374a"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga81528f8f4538347b9f0b9e5b1c47374a"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga81528f8f4538347b9f0b9e5b1c47374a">CSL_DSS_VP_TDM_CYCLE_3PER2PIXEL</a>   ((uint32_t) CSL_DSS_VP1_CONTROL_TDMCYCLEFORMAT_VAL_3CYCPER2PIX)</td></tr>
+<tr class="memdesc:ga81528f8f4538347b9f0b9e5b1c47374a"><td class="mdescLeft"> </td><td class="mdescRight">3 cycles per 2 pixels <br/></td></tr>
+<tr class="separator:ga81528f8f4538347b9f0b9e5b1c47374a"><td class="memSeparator" colspan="2"> </td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
+Output interface width in TDM mode</h2></td></tr>
+<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrpf5d5d871fa0d98d3dc2172a28d142e8c"></a><a class="anchor" id="CSL_DssVpTdmParallelMode"></a></p>
+</td></tr>
+<tr class="memitem:gacd33fff8fc6d940d149b39ca4dd2f032"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gacd33fff8fc6d940d149b39ca4dd2f032"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gacd33fff8fc6d940d149b39ca4dd2f032">CSL_DSS_VP_TDM_PARALLEL_OUTPUT_8BIT</a>   ((uint32_t) CSL_DSS_VP1_CONTROL_TDMPARALLELMODE_VAL_8BPARAINT)</td></tr>
+<tr class="memdesc:gacd33fff8fc6d940d149b39ca4dd2f032"><td class="mdescLeft"> </td><td class="mdescRight">8-bit parallel output interface selected <br/></td></tr>
+<tr class="separator:gacd33fff8fc6d940d149b39ca4dd2f032"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gabf1ad83065c73fc074ed85876c5e505e"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gabf1ad83065c73fc074ed85876c5e505e"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gabf1ad83065c73fc074ed85876c5e505e">CSL_DSS_VP_TDM_PARALLEL_OUTPUT_9BIT</a>   ((uint32_t) CSL_DSS_VP1_CONTROL_TDMPARALLELMODE_VAL_9BPARAINT)</td></tr>
+<tr class="memdesc:gabf1ad83065c73fc074ed85876c5e505e"><td class="mdescLeft"> </td><td class="mdescRight">9-bit parallel output interface selected <br/></td></tr>
+<tr class="separator:gabf1ad83065c73fc074ed85876c5e505e"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gac83301ee887a6562c3ec89a921c4b74f"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gac83301ee887a6562c3ec89a921c4b74f"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gac83301ee887a6562c3ec89a921c4b74f">CSL_DSS_VP_TDM_PARALLEL_OUTPUT_12BIT</a>   ((uint32_t) CSL_DSS_VP1_CONTROL_TDMPARALLELMODE_VAL_12BPARAINT)</td></tr>
+<tr class="memdesc:gac83301ee887a6562c3ec89a921c4b74f"><td class="mdescLeft"> </td><td class="mdescRight">12-bit parallel output interface selected <br/></td></tr>
+<tr class="separator:gac83301ee887a6562c3ec89a921c4b74f"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga8715d15d4ee5eebd9ea7b15adcf22394"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga8715d15d4ee5eebd9ea7b15adcf22394"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga8715d15d4ee5eebd9ea7b15adcf22394">CSL_DSS_VP_TDM_PARALLEL_OUTPUT_16BIT</a>   ((uint32_t) CSL_DSS_VP1_CONTROL_TDMPARALLELMODE_VAL_16BPARAINT)</td></tr>
+<tr class="memdesc:ga8715d15d4ee5eebd9ea7b15adcf22394"><td class="mdescLeft"> </td><td class="mdescRight">16-bit parallel output interface selected <br/></td></tr>
+<tr class="separator:ga8715d15d4ee5eebd9ea7b15adcf22394"><td class="memSeparator" colspan="2"> </td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
+LCD HSync VSync Alignment</h2></td></tr>
+<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrpf1a71de7f0edfcc2ed1890c94b9c241d"></a><a class="anchor" id="CSL_DssVpLcdHVSyncAlign"></a></p>
+</td></tr>
+<tr class="memitem:gab6a57958037687c92ae5d39ef7e4633f"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gab6a57958037687c92ae5d39ef7e4633f"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gab6a57958037687c92ae5d39ef7e4633f">CSL_DSS_VP_HVSYNC_NOT_ALIGNED</a>   ((uint32_t) CSL_DSS_VP1_POL_FREQ_ALIGN_VAL_NOTALIGNED)</td></tr>
+<tr class="memdesc:gab6a57958037687c92ae5d39ef7e4633f"><td class="mdescLeft"> </td><td class="mdescRight">HSYNC and VSYNC are not aligned. <br/></td></tr>
+<tr class="separator:gab6a57958037687c92ae5d39ef7e4633f"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga744ce9e2dba4875d10456de204cdf564"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga744ce9e2dba4875d10456de204cdf564"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga744ce9e2dba4875d10456de204cdf564">CSL_DSS_VP_HVSYNC_ALIGNED</a>   ((uint32_t) CSL_DSS_VP1_POL_FREQ_ALIGN_VAL_ALIGNED)</td></tr>
+<tr class="memdesc:ga744ce9e2dba4875d10456de204cdf564"><td class="mdescLeft"> </td><td class="mdescRight">HSYNC and VSYNC assertions are aligned. <br/></td></tr>
+<tr class="separator:ga744ce9e2dba4875d10456de204cdf564"><td class="memSeparator" colspan="2"> </td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
+LCD HSYNC/VSYNC pixel clock control</h2></td></tr>
+<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrp45a1f72e3944ee9c0aec7219b5e19f81"></a><a class="anchor" id="CSL_DssVpLcdHVClkControl"></a></p>
+</td></tr>
+<tr class="memitem:ga2b87767e34b62775d52ef6022789bdd0"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga2b87767e34b62775d52ef6022789bdd0"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga2b87767e34b62775d52ef6022789bdd0">CSL_DSS_VP_HVCLK_CONTROL_OFF</a>   ((uint32_t) CSL_DSS_VP1_POL_FREQ_ONOFF_VAL_DOPEDPCK)</td></tr>
+<tr class="memdesc:ga2b87767e34b62775d52ef6022789bdd0"><td class="mdescLeft"> </td><td class="mdescRight">HSYNC and VSYNC are driven on opposite edges of the pixel clock than pixel data. <br/></td></tr>
+<tr class="separator:ga2b87767e34b62775d52ef6022789bdd0"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gac3a10008ac4fbc32ef1869c751602925"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gac3a10008ac4fbc32ef1869c751602925"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gac3a10008ac4fbc32ef1869c751602925">CSL_DSS_VP_HVCLK_CONTROL_ON</a>   ((uint32_t) CSL_DSS_VP1_POL_FREQ_ONOFF_VAL_DBIT16)</td></tr>
+<tr class="memdesc:gac3a10008ac4fbc32ef1869c751602925"><td class="mdescLeft"> </td><td class="mdescRight">HSYNC and VSYNC are driven according to hVClkRiseFall value. <br/></td></tr>
+<tr class="separator:gac3a10008ac4fbc32ef1869c751602925"><td class="memSeparator" colspan="2"> </td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
+Delta Lines Per Panel</h2></td></tr>
+<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrp90b8550e21c3bf345294413554165b31"></a>Delta size value of the odd field compared to the even field</p>
+<p><a class="anchor" id="CSL_DssVpDeltaLpp"></a></p>
+</td></tr>
+<tr class="memitem:ga0d0f13dd26e92dba642f40387e517b6a"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga0d0f13dd26e92dba642f40387e517b6a"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga0d0f13dd26e92dba642f40387e517b6a">CSL_DSS_VP_LPP_DELTA_ZERO</a>   ((uint32_t) CSL_DSS_VP1_SIZE_SCREEN_DELTA_LPP_VAL_SAME)</td></tr>
+<tr class="memdesc:ga0d0f13dd26e92dba642f40387e517b6a"><td class="mdescLeft"> </td><td class="mdescRight">Odd field has same size as even. <br/></td></tr>
+<tr class="separator:ga0d0f13dd26e92dba642f40387e517b6a"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga219596f8e8c8b043dde6c1f05c36f570"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga219596f8e8c8b043dde6c1f05c36f570"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga219596f8e8c8b043dde6c1f05c36f570">CSL_DSS_VP_LPP_DELTA_PLUSONE</a>   ((uint32_t) CSL_DSS_VP1_SIZE_SCREEN_DELTA_LPP_VAL_PLUSONE)</td></tr>
+<tr class="memdesc:ga219596f8e8c8b043dde6c1f05c36f570"><td class="mdescLeft"> </td><td class="mdescRight">Odd field is equal to even field + 1. <br/></td></tr>
+<tr class="separator:ga219596f8e8c8b043dde6c1f05c36f570"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga1a9e8a871ac9b403dfe0f0d208b3c29f"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga1a9e8a871ac9b403dfe0f0d208b3c29f"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga1a9e8a871ac9b403dfe0f0d208b3c29f">CSL_DSS_VP_LPP_DELTA_MINUSONE</a>   ((uint32_t) CSL_DSS_VP1_SIZE_SCREEN_DELTA_LPP_VAL_MINUSONE)</td></tr>
+<tr class="memdesc:ga1a9e8a871ac9b403dfe0f0d208b3c29f"><td class="mdescLeft"> </td><td class="mdescRight">Odd field is equal to even field - 1. <br/></td></tr>
+<tr class="separator:ga1a9e8a871ac9b403dfe0f0d208b3c29f"><td class="memSeparator" colspan="2"> </td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
+Video Port First Field</h2></td></tr>
+<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrpe42210cbbdad4f63a05258af52d3aa38"></a>First Field to Video Port output in case of interlace mode</p>
+<p><a class="anchor" id="CSL_DssVpFidFirstVal"></a></p>
+</td></tr>
+<tr class="memitem:gab6a1a6b67d60bff5578cc42bc2bc0114"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gab6a1a6b67d60bff5578cc42bc2bc0114"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gab6a1a6b67d60bff5578cc42bc2bc0114">CSL_DSS_VP_FID_FIRST_EVEN</a>   ((uint32_t) CSL_DSS_VP1_CONFIG_FIDFIRST_VAL_EVEN)</td></tr>
+<tr class="memdesc:gab6a1a6b67d60bff5578cc42bc2bc0114"><td class="mdescLeft"> </td><td class="mdescRight">First field is even. <br/></td></tr>
+<tr class="separator:gab6a1a6b67d60bff5578cc42bc2bc0114"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga62dd57b2769fa39f4459379b8f432465"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga62dd57b2769fa39f4459379b8f432465"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga62dd57b2769fa39f4459379b8f432465">CSL_DSS_VP_FID_FIRST_ODD</a>   ((uint32_t) CSL_DSS_VP1_CONFIG_FIDFIRST_VAL_ODD)</td></tr>
+<tr class="memdesc:ga62dd57b2769fa39f4459379b8f432465"><td class="mdescLeft"> </td><td class="mdescRight">First field is odd. <br/></td></tr>
+<tr class="separator:ga62dd57b2769fa39f4459379b8f432465"><td class="memSeparator" colspan="2"> </td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
+Video Port Stall Mode</h2></td></tr>
+<tr><td class="ititle" colspan="2"><p><a class="anchor" id="amgrpac8a57f03e131fbaeed6053da5842fc6"></a>The type of transfer in Stall mode</p>
+<p><a class="anchor" id="CSL_DssVpStallMode"></a></p>
+</td></tr>
+<tr class="memitem:gabd8aa22176d523bf6927f02922e6a965"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gabd8aa22176d523bf6927f02922e6a965"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gabd8aa22176d523bf6927f02922e6a965">CSL_DSS_VP_STALL_MODE_COMMAND</a>   ((uint32_t) CSL_DSS_VP1_CONTROL_STALLMODETYPE_VAL_COMMANDMODE)</td></tr>
+<tr class="memdesc:gabd8aa22176d523bf6927f02922e6a965"><td class="mdescLeft"> </td><td class="mdescRight">Stall mode is command. <br/></td></tr>
+<tr class="separator:gabd8aa22176d523bf6927f02922e6a965"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga1ae77b1f37ae1fafa15adc649b49f309"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga1ae77b1f37ae1fafa15adc649b49f309"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#ga1ae77b1f37ae1fafa15adc649b49f309">CSL_DSS_VP_STALL_MODE_VIDEO</a>   ((uint32_t) CSL_DSS_VP1_CONTROL_STALLMODETYPE_VAL_VIDEOMODE)</td></tr>
+<tr class="memdesc:ga1ae77b1f37ae1fafa15adc649b49f309"><td class="mdescLeft"> </td><td class="mdescRight">Stall mode is video. <br/></td></tr>
+<tr class="separator:ga1ae77b1f37ae1fafa15adc649b49f309"><td class="memSeparator" colspan="2"> </td></tr>
+</table>
+<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
+<h2 class="groupheader">Typedef Documentation</h2>
+<a class="anchor" id="gaaaf231996a0d81bd23a1460d729dad23"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">typedef CSL_dss_vp1Regs <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gaaaf231996a0d81bd23a1460d729dad23">CSL_dss_vpRegs</a></td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+
+<p>DSS Video Port Registers. </p>
+<p>DSS7 UL has two identical VP blocks, hence define a generic structure to have common APIs </p>
+
+</div>
+</div>
+<h2 class="groupheader">Function Documentation</h2>
+<a class="anchor" id="ga9c61092eddfa87bcba87cc116fb8bd1d"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">void CSL_dssVpEnable </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gaaaf231996a0d81bd23a1460d729dad23">CSL_dss_vpRegs</a> * </td>
+ <td class="paramname"><em>vpRegs</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">uint32_t </td>
+ <td class="paramname"><em>enable</em> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td></td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+
+<p>Enable the DSS Video Port. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">vpRegs</td><td>Pointer to a <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gaaaf231996a0d81bd23a1460d729dad23" title="DSS Video Port Registers. ">CSL_dss_vpRegs</a> structure containing the video port configuration </td></tr>
+ <tr><td class="paramname">enable</td><td>Enable or disable the Video Port TRUE: Enable FALSE: Disable</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga253c3416c174352edcda17c4ca271013"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">void CSL_dssVpEnableTvGamma </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gaaaf231996a0d81bd23a1460d729dad23">CSL_dss_vpRegs</a> * </td>
+ <td class="paramname"><em>vpRegs</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">const <a class="el" href="struct_c_s_l___dss_vp_gamma_cfg.html">CSL_DssVpGammaCfg</a> * </td>
+ <td class="paramname"><em>gammaCfg</em> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td></td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+
+<p>Enable/Bypass TV Gamma Table. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">vpRegs</td><td>Pointer to a <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gaaaf231996a0d81bd23a1460d729dad23" title="DSS Video Port Registers. ">CSL_dss_vpRegs</a> structure containing the video port configuration </td></tr>
+ <tr><td class="paramname">gammaCfg</td><td>Pointer to <a class="el" href="struct_c_s_l___dss_vp_gamma_cfg.html" title="Gamma Correction configuration for DSS Video Port Output. ">CSL_DssVpGammaCfg</a> structure. This parameter should not be NULL</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga709fdcc02c1f82d9a3b595ad67b9f086"></a>
+<div class="memitem">
+<div class="memproto">
+<table class="mlabels">
+ <tr>
+ <td class="mlabels-left">
+ <table class="memname">
+ <tr>
+ <td class="memname">static void CSL_dssVpGammaCfgInit </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="struct_c_s_l___dss_vp_gamma_cfg.html">CSL_DssVpGammaCfg</a> * </td>
+ <td class="paramname"><em>gammaCfg</em></td><td>)</td>
+ <td></td>
+ </tr>
+ </table>
+ </td>
+ <td class="mlabels-right">
+<span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span> </td>
+ </tr>
+</table>
+</div><div class="memdoc">
+
+<p><a class="el" href="struct_c_s_l___dss_vp_gamma_cfg.html" title="Gamma Correction configuration for DSS Video Port Output. ">CSL_DssVpGammaCfg</a> structure init function. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">gammaCfg</td><td>Pointer to <a class="el" href="struct_c_s_l___dss_vp_gamma_cfg.html" title="Gamma Correction configuration for DSS Video Port Output. ">CSL_DssVpGammaCfg</a> structure</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga447444c64439d7b1210a9b696dd8a673"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t CSL_dssVpGetLcdLineNum </td>
+ <td>(</td>
+ <td class="paramtype">const <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gaaaf231996a0d81bd23a1460d729dad23">CSL_dss_vpRegs</a> * </td>
+ <td class="paramname"><em>vpRegs</em></td><td>)</td>
+ <td></td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+
+<p>Get the number of line currently displayed. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">vpRegs</td><td>Pointer to a <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gaaaf231996a0d81bd23a1460d729dad23" title="DSS Video Port Registers. ">CSL_dss_vpRegs</a> structure containing the video port configuration</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>Current line number </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga7f7b411493687d0d758ff8b047a23712"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t CSL_dssVpGetSafetySign </td>
+ <td>(</td>
+ <td class="paramtype">const <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gaaaf231996a0d81bd23a1460d729dad23">CSL_dss_vpRegs</a> * </td>
+ <td class="paramname"><em>vpRegs</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">uint32_t </td>
+ <td class="paramname"><em>regionId</em> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td></td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+
+<p>Get the Safety Signature of the sub region. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">vpRegs</td><td>Pointer to a <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gaaaf231996a0d81bd23a1460d729dad23" title="DSS Video Port Registers. ">CSL_dss_vpRegs</a> structure containing the video port configuration </td></tr>
+ <tr><td class="paramname">regionId</td><td>Region for which safety check should be done. Refer <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#CSL_DssSafetyRegionId">CSL_DssSafetyRegionId</a> for values</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>Signature Value </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga50f5efd31f31736019ee265e3078d4ef"></a>
+<div class="memitem">
+<div class="memproto">
+<table class="mlabels">
+ <tr>
+ <td class="mlabels-left">
+ <table class="memname">
+ <tr>
+ <td class="memname">static void CSL_dssVpLcdAdvSignalCfgInit </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="struct_c_s_l___dss_vp_lcd_adv_signal_cfg.html">CSL_DssVpLcdAdvSignalCfg</a> * </td>
+ <td class="paramname"><em>advSignalCfg</em></td><td>)</td>
+ <td></td>
+ </tr>
+ </table>
+ </td>
+ <td class="mlabels-right">
+<span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span> </td>
+ </tr>
+</table>
+</div><div class="memdoc">
+
+<p><a class="el" href="struct_c_s_l___dss_vp_lcd_adv_signal_cfg.html" title="Advance Signal Configuration for the LCD. ">CSL_DssVpLcdAdvSignalCfg</a> structure init function. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">advSignalCfg</td><td>Pointer to <a class="el" href="struct_c_s_l___dss_vp_lcd_adv_signal_cfg.html" title="Advance Signal Configuration for the LCD. ">CSL_DssVpLcdAdvSignalCfg</a> structure</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="gadd1a815002453481cce4f9dbf8da864a"></a>
+<div class="memitem">
+<div class="memproto">
+<table class="mlabels">
+ <tr>
+ <td class="mlabels-left">
+ <table class="memname">
+ <tr>
+ <td class="memname">static void CSL_dssVpLcdBlankTimingCfgInit </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="struct_c_s_l___dss_vp_lcd_blank_timing_cfg.html">CSL_DssVpLcdBlankTimingCfg</a> * </td>
+ <td class="paramname"><em>blankCfg</em></td><td>)</td>
+ <td></td>
+ </tr>
+ </table>
+ </td>
+ <td class="mlabels-right">
+<span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span> </td>
+ </tr>
+</table>
+</div><div class="memdoc">
+
+<p><a class="el" href="struct_c_s_l___dss_vp_lcd_blank_timing_cfg.html" title="Blanking Timing parameters for the LCD. ">CSL_DssVpLcdBlankTimingCfg</a> structure init function. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">blankCfg</td><td>Pointer to <a class="el" href="struct_c_s_l___dss_vp_lcd_blank_timing_cfg.html" title="Blanking Timing parameters for the LCD. ">CSL_DssVpLcdBlankTimingCfg</a> structure</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga2be9daed03e91c1706a4075be86a7054"></a>
+<div class="memitem">
+<div class="memproto">
+<table class="mlabels">
+ <tr>
+ <td class="mlabels-left">
+ <table class="memname">
+ <tr>
+ <td class="memname">static void CSL_dssVpLcdOpTimingCfgInit </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="struct_c_s_l___dss_vp_lcd_op_timing_cfg.html">CSL_DssVpLcdOpTimingCfg</a> * </td>
+ <td class="paramname"><em>lcdCfg</em></td><td>)</td>
+ <td></td>
+ </tr>
+ </table>
+ </td>
+ <td class="mlabels-right">
+<span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span> </td>
+ </tr>
+</table>
+</div><div class="memdoc">
+
+<p><a class="el" href="struct_c_s_l___dss_vp_lcd_op_timing_cfg.html" title="Timing configuration for the LCD output. ">CSL_DssVpLcdOpTimingCfg</a> structure init function. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">lcdCfg</td><td>Pointer to <a class="el" href="struct_c_s_l___dss_vp_lcd_op_timing_cfg.html" title="Timing configuration for the LCD output. ">CSL_DssVpLcdOpTimingCfg</a> structure</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga158b9aed148e3a14e1bff1cb8613bc67"></a>
+<div class="memitem">
+<div class="memproto">
+<table class="mlabels">
+ <tr>
+ <td class="mlabels-left">
+ <table class="memname">
+ <tr>
+ <td class="memname">static void CSL_dssVpLcdSignalPolarityCfgInit </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="struct_c_s_l___dss_vp_lcd_signal_polarity_cfg.html">CSL_DssVpLcdSignalPolarityCfg</a> * </td>
+ <td class="paramname"><em>polarityCfg</em></td><td>)</td>
+ <td></td>
+ </tr>
+ </table>
+ </td>
+ <td class="mlabels-right">
+<span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span> </td>
+ </tr>
+</table>
+</div><div class="memdoc">
+
+<p><a class="el" href="struct_c_s_l___dss_vp_lcd_signal_polarity_cfg.html" title="Polarity of Active Video, Pixel Clock, HSync and VSync signals for the LCD. ">CSL_DssVpLcdSignalPolarityCfg</a> structure init function. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">polarityCfg</td><td>Pointer to <a class="el" href="struct_c_s_l___dss_vp_lcd_signal_polarity_cfg.html" title="Polarity of Active Video, Pixel Clock, HSync and VSync signals for the LCD. ">CSL_DssVpLcdSignalPolarityCfg</a> structure</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="gaf276b6af542ab92fa03bf0af6d1af1cb"></a>
+<div class="memitem">
+<div class="memproto">
+<table class="mlabels">
+ <tr>
+ <td class="mlabels-left">
+ <table class="memname">
+ <tr>
+ <td class="memname">static void CSL_dssVpLcdTdmCfgInit </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="struct_c_s_l___dss_vp_lcd_tdm_cfg.html">CSL_DssVpLcdTdmCfg</a> * </td>
+ <td class="paramname"><em>tdmCfg</em></td><td>)</td>
+ <td></td>
+ </tr>
+ </table>
+ </td>
+ <td class="mlabels-right">
+<span class="mlabels"><span class="mlabel">inline</span><span class="mlabel">static</span></span> </td>
+ </tr>
+</table>
+</div><div class="memdoc">
+
+<p><a class="el" href="struct_c_s_l___dss_vp_lcd_tdm_cfg.html" title="LCD Configuration for Time Division Multiplexing. ">CSL_DssVpLcdTdmCfg</a> structure init function. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">tdmCfg</td><td>Pointer to <a class="el" href="struct_c_s_l___dss_vp_lcd_tdm_cfg.html" title="LCD Configuration for Time Division Multiplexing. ">CSL_DssVpLcdTdmCfg</a> structure</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga7d36af9cdba47ad2622758fd632980ce"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">void CSL_dssVpSetCSCCoeff </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gaaaf231996a0d81bd23a1460d729dad23">CSL_dss_vpRegs</a> * </td>
+ <td class="paramname"><em>vpRegs</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">const <a class="el" href="struct_c_s_l___dss_csc_coeff.html">CSL_DssCscCoeff</a> * </td>
+ <td class="paramname"><em>cscCoeff</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">uint32_t </td>
+ <td class="paramname"><em>cscPos</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">uint32_t </td>
+ <td class="paramname"><em>cscEnable</em> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td></td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+
+<p>Configure the coefficients for Color Space Conversion. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">vpRegs</td><td>Pointer to a <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gaaaf231996a0d81bd23a1460d729dad23" title="DSS Video Port Registers. ">CSL_dss_vpRegs</a> structure containing the video port configuration </td></tr>
+ <tr><td class="paramname">cscCoeff</td><td>Pointer to <a class="el" href="struct_c_s_l___dss_csc_coeff.html" title="Structure containing coefficients for Color Space Conversion. ">CSL_DssCscCoeff</a> structure. This parameter should not be NULL </td></tr>
+ <tr><td class="paramname">cscPos</td><td>Position of CSC block wrt GAMMA module. Refer <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#CSL_DssVpCscPos">CSL_DssVpCscPos</a> for values </td></tr>
+ <tr><td class="paramname">cscEnable</td><td>CSC Enable TRUE: Enable CSC FALSE: Disable CSC</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga0ba989884315a28b21a62a722574865d"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">void CSL_dssVpSetGoBit </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gaaaf231996a0d81bd23a1460d729dad23">CSL_dss_vpRegs</a> * </td>
+ <td class="paramname"><em>vpRegs</em></td><td>)</td>
+ <td></td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+
+<p>GO Command for the VP output. It is used to synchronize the pipelines associated with the VP output. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">vpRegs</td><td>Pointer to a <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gaaaf231996a0d81bd23a1460d729dad23" title="DSS Video Port Registers. ">CSL_dss_vpRegs</a> structure containing the video port configuration</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga45dfca83a394f21328886b7ad7d89056"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">void CSL_dssVpSetLcdAdvSignalConfig </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gaaaf231996a0d81bd23a1460d729dad23">CSL_dss_vpRegs</a> * </td>
+ <td class="paramname"><em>vpRegs</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">const <a class="el" href="struct_c_s_l___dss_vp_lcd_adv_signal_cfg.html">CSL_DssVpLcdAdvSignalCfg</a> * </td>
+ <td class="paramname"><em>advSignalCfg</em> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td></td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+
+<p>Configure the advance LCD Signal parameters. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">vpRegs</td><td>Pointer to a <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gaaaf231996a0d81bd23a1460d729dad23" title="DSS Video Port Registers. ">CSL_dss_vpRegs</a> structure containing the video port configuration </td></tr>
+ <tr><td class="paramname">advSignalCfg</td><td>Pointer to <a class="el" href="struct_c_s_l___dss_vp_lcd_adv_signal_cfg.html" title="Advance Signal Configuration for the LCD. ">CSL_DssVpLcdAdvSignalCfg</a> structure. This parameter should not be NULL</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga5f52bab6e5e9242d6f77faf995a4de6e"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">int32_t CSL_dssVpSetLcdBlankTiming </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gaaaf231996a0d81bd23a1460d729dad23">CSL_dss_vpRegs</a> * </td>
+ <td class="paramname"><em>vpRegs</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">const <a class="el" href="struct_c_s_l___dss_vp_lcd_blank_timing_cfg.html">CSL_DssVpLcdBlankTimingCfg</a> * </td>
+ <td class="paramname"><em>blankCfg</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">uint32_t </td>
+ <td class="paramname"><em>dvoFormat</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">uint32_t </td>
+ <td class="paramname"><em>scanFormat</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">uint32_t </td>
+ <td class="paramname"><em>isCustomTiming</em> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td></td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+
+<p>Configure the LCD Blank Timing parameters. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">vpRegs</td><td>Pointer to a <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gaaaf231996a0d81bd23a1460d729dad23" title="DSS Video Port Registers. ">CSL_dss_vpRegs</a> structure containing the video port configuration </td></tr>
+ <tr><td class="paramname">blankCfg</td><td>Pointer to the <a class="el" href="struct_c_s_l___dss_vp_lcd_blank_timing_cfg.html" title="Blanking Timing parameters for the LCD. ">CSL_DssVpLcdBlankTimingCfg</a> structure. This parameter should not be NULL </td></tr>
+ <tr><td class="paramname">dvoFormat</td><td>Digital output format. For valid values see <a class="el" href="csl__fvid2__data_types_8h.html#Fvid2_DVFormat">Fvid2_DVFormat</a> </td></tr>
+ <tr><td class="paramname">scanFormat</td><td>Scan format. For valid values see <a class="el" href="csl__fvid2__data_types_8h.html#af5dfad95adb11f1220c13a37564b706e" title="Interlaced mode. ">Fvid2_ScanFormat</a> </td></tr>
+ <tr><td class="paramname">isCustomTiming</td><td>Variable to determine whether custom timing is used. It should always be set to TRUE when this API is called by application.</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>CSL_ErrType_t </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga1a4f05443f8ba7bffea84d63b43788ab"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">void CSL_dssVpSetLcdLineNum </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gaaaf231996a0d81bd23a1460d729dad23">CSL_dss_vpRegs</a> * </td>
+ <td class="paramname"><em>vpRegs</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">uint32_t </td>
+ <td class="paramname"><em>lineNum</em> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td></td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+
+<p>Set the Line Number at which the interrupt should be generated. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">vpRegs</td><td>Pointer to a <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gaaaf231996a0d81bd23a1460d729dad23" title="DSS Video Port Registers. ">CSL_dss_vpRegs</a> structure containing the video port configuration </td></tr>
+ <tr><td class="paramname">lineNum</td><td>Line Number that should be programmed in the register</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga0225f72557517955d94f1a6ce815ed14"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">int32_t CSL_dssVpSetLcdOpTimingConfig </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gaaaf231996a0d81bd23a1460d729dad23">CSL_dss_vpRegs</a> * </td>
+ <td class="paramname"><em>vpRegs</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">const <a class="el" href="struct_c_s_l___dss_vp_lcd_op_timing_cfg.html">CSL_DssVpLcdOpTimingCfg</a> * </td>
+ <td class="paramname"><em>lcdCfg</em> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td></td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+
+<p>Configure the LCD Timing parameters. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">vpRegs</td><td>Pointer to a <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gaaaf231996a0d81bd23a1460d729dad23" title="DSS Video Port Registers. ">CSL_dss_vpRegs</a> structure containing the video port configuration </td></tr>
+ <tr><td class="paramname">lcdCfg</td><td>Pointer to the <a class="el" href="struct_c_s_l___dss_vp_lcd_op_timing_cfg.html" title="Timing configuration for the LCD output. ">CSL_DssVpLcdOpTimingCfg</a> structure. This parameter should not be NULL</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>CSL_ErrType_t </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga75453549b6c9c05da750b55cdb2a8ad3"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">void CSL_dssVpSetLcdSignalPolarityConfig </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gaaaf231996a0d81bd23a1460d729dad23">CSL_dss_vpRegs</a> * </td>
+ <td class="paramname"><em>vpRegs</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">const <a class="el" href="struct_c_s_l___dss_vp_lcd_signal_polarity_cfg.html">CSL_DssVpLcdSignalPolarityCfg</a> * </td>
+ <td class="paramname"><em>polarityCfg</em> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td></td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+
+<p>Configure the Polarity of LCD signals(HSYNC, VSYNC, PCLK, Data) </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">vpRegs</td><td>Pointer to a <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gaaaf231996a0d81bd23a1460d729dad23" title="DSS Video Port Registers. ">CSL_dss_vpRegs</a> structure containing the video port configuration </td></tr>
+ <tr><td class="paramname">polarityCfg</td><td>Pointer to <a class="el" href="struct_c_s_l___dss_vp_lcd_signal_polarity_cfg.html" title="Polarity of Active Video, Pixel Clock, HSync and VSync signals for the LCD. ">CSL_DssVpLcdSignalPolarityCfg</a> structure. This parameter should not be NULL</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga48c44cb30d94ee22ddd885998830d852"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">void CSL_dssVpSetLcdTdmConfig </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gaaaf231996a0d81bd23a1460d729dad23">CSL_dss_vpRegs</a> * </td>
+ <td class="paramname"><em>vpRegs</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">const <a class="el" href="struct_c_s_l___dss_vp_lcd_tdm_cfg.html">CSL_DssVpLcdTdmCfg</a> * </td>
+ <td class="paramname"><em>lcdTdmCfg</em> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td></td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+
+<p>Configure the LCD TDM(Time division multiplexing) parameters. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">vpRegs</td><td>Pointer to a <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gaaaf231996a0d81bd23a1460d729dad23" title="DSS Video Port Registers. ">CSL_dss_vpRegs</a> structure containing the video port configuration </td></tr>
+ <tr><td class="paramname">lcdTdmCfg</td><td>Pointer to the <a class="el" href="struct_c_s_l___dss_vp_lcd_tdm_cfg.html" title="LCD Configuration for Time Division Multiplexing. ">CSL_DssVpLcdTdmCfg</a> structure. This parameter should not be NULL</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="gad2853dae9324aa61cbb332d14b308da6"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">void CSL_dssVpSetSafetyChkConfig </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gaaaf231996a0d81bd23a1460d729dad23">CSL_dss_vpRegs</a> * </td>
+ <td class="paramname"><em>vpRegs</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">const <a class="el" href="struct_c_s_l___dss_safety_chk_cfg.html">CSL_DssSafetyChkCfg</a> * </td>
+ <td class="paramname"><em>safetyCfg</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">uint32_t </td>
+ <td class="paramname"><em>regionId</em> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td></td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+
+<p>Configure the Safety Check parameters. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">vpRegs</td><td>Pointer to a <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gaaaf231996a0d81bd23a1460d729dad23" title="DSS Video Port Registers. ">CSL_dss_vpRegs</a> structure containing the video port configuration </td></tr>
+ <tr><td class="paramname">safetyCfg</td><td>Pointer to <a class="el" href="struct_c_s_l___dss_safety_chk_cfg.html" title="Configuration for doing safety checks. ">CSL_DssSafetyChkCfg</a> structure. This parameter should not be NULL </td></tr>
+ <tr><td class="paramname">regionId</td><td>Region for which safety check should be done. Refer <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#CSL_DssSafetyRegionId">CSL_DssSafetyRegionId</a> for values</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga20bfb7e29029c7256d6766b9b05f5f23"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">void CSL_dssVpSetSafetyReferenceSign </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gaaaf231996a0d81bd23a1460d729dad23">CSL_dss_vpRegs</a> * </td>
+ <td class="paramname"><em>vpRegs</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">uint32_t </td>
+ <td class="paramname"><em>referenceSign</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">uint32_t </td>
+ <td class="paramname"><em>regionId</em> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td></td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+
+<p>Set the reference safety signature for data correctness check. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">vpRegs</td><td>Pointer to a <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gaaaf231996a0d81bd23a1460d729dad23" title="DSS Video Port Registers. ">CSL_dss_vpRegs</a> structure containing the video port configuration </td></tr>
+ <tr><td class="paramname">referenceSign</td><td>Reference Safety Signature </td></tr>
+ <tr><td class="paramname">regionId</td><td>Region for which safety check should be done. Refer <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#CSL_DssSafetyRegionId">CSL_DssSafetyRegionId</a> for values</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga1bc9995f9958912a188ae2a98351aec5"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">void CSL_dssVpSetSafetySignSeedVal </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gaaaf231996a0d81bd23a1460d729dad23">CSL_dss_vpRegs</a> * </td>
+ <td class="paramname"><em>vpRegs</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">uint32_t </td>
+ <td class="paramname"><em>signSeedVal</em> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td></td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+
+<p>Set the seed value for the signature calculation. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">vpRegs</td><td>Pointer to a <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gaaaf231996a0d81bd23a1460d729dad23" title="DSS Video Port Registers. ">CSL_dss_vpRegs</a> structure containing the video port configuration </td></tr>
+ <tr><td class="paramname">signSeedVal</td><td>Signature Seed Value to be Set</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga08a68b5de9d2c6646b0654ccad3b9600"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">void CSL_dssVpStallModeEnable </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gaaaf231996a0d81bd23a1460d729dad23">CSL_dss_vpRegs</a> * </td>
+ <td class="paramname"><em>vpRegs</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">uint32_t </td>
+ <td class="paramname"><em>enable</em>, </td>
+ </tr>
+ <tr>
+ <td class="paramkey"></td>
+ <td></td>
+ <td class="paramtype">uint32_t </td>
+ <td class="paramname"><em>stallModeType</em> </td>
+ </tr>
+ <tr>
+ <td></td>
+ <td>)</td>
+ <td></td><td></td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+
+<p>Enable/disable the Video Port stall mode. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">vpRegs</td><td>Pointer to a <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#gaaaf231996a0d81bd23a1460d729dad23" title="DSS Video Port Registers. ">CSL_dss_vpRegs</a> structure containing the video port configuration </td></tr>
+ <tr><td class="paramname">enable</td><td>Enable or disable the stall mode of Video Port TRUE: Enable FALSE: Disable </td></tr>
+ <tr><td class="paramname">stallModeType</td><td>Stall Mode Type Refer <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#CSL_DssVpStallMode">CSL_DssVpStallMode</a> for values</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None </dd></dl>
+
+</div>
+</div>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/group___d_s_s.html b/packages/ti/drv/dss/docs/doxygen/html/group___d_s_s.html
--- /dev/null
@@ -0,0 +1,152 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>DSS Driver</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="files.html"><span>Files</span></a></li>
+ </ul>
+ </div>
+</div><!-- top -->
+<div class="header">
+ <div class="summary">
+<a href="#files">Files</a> |
+<a href="#nested-classes">Data Structures</a> |
+<a href="#define-members">Macros</a> |
+<a href="#func-members">Functions</a> </div>
+ <div class="headertitle">
+<div class="title">DSS Driver</div> </div>
+</div><!--header-->
+<div class="contents">
+<table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="files"></a>
+Files</h2></td></tr>
+<tr class="memitem:dss_8h"><td class="memItemLeft" align="right" valign="top">file  </td><td class="memItemRight" valign="bottom"><a class="el" href="dss_8h.html">dss.h</a></td></tr>
+<tr class="memdesc:dss_8h"><td class="mdescLeft"> </td><td class="mdescRight">DSS Driver API/interface file. <br/></td></tr>
+<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="nested-classes"></a>
+Data Structures</h2></td></tr>
+<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___init_params.html">Dss_InitParams</a></td></tr>
+<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">DSS initialization parameters. <a href="struct_dss___init_params.html#details">More...</a><br/></td></tr>
+<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
+Macros</h2></td></tr>
+<tr class="memitem:ga87b702c7777640534d677104a7697d35"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga87b702c7777640534d677104a7697d35"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___d_s_s.html#ga87b702c7777640534d677104a7697d35">DSS_DISP_DRV_ID</a>   (FVID2_DSS_DRV_BASE + 0x00U)</td></tr>
+<tr class="memdesc:ga87b702c7777640534d677104a7697d35"><td class="mdescLeft"> </td><td class="mdescRight">Display driver ID used at the time of FVID2 create. <br/></td></tr>
+<tr class="separator:ga87b702c7777640534d677104a7697d35"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga0a02adbaa0f72fbfba37dbca39c7ab1d"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga0a02adbaa0f72fbfba37dbca39c7ab1d"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___d_s_s.html#ga0a02adbaa0f72fbfba37dbca39c7ab1d">DSS_DCTRL_DRV_ID</a>   (FVID2_DSS_DRV_BASE + 0x01U)</td></tr>
+<tr class="memdesc:ga0a02adbaa0f72fbfba37dbca39c7ab1d"><td class="mdescLeft"> </td><td class="mdescRight">Display controller driver ID used at the time of FVID2 create. <br/></td></tr>
+<tr class="separator:ga0a02adbaa0f72fbfba37dbca39c7ab1d"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gaf8566eb291e6ce8c67bf5158426d42b9"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaf8566eb291e6ce8c67bf5158426d42b9"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___d_s_s.html#gaf8566eb291e6ce8c67bf5158426d42b9">DSS_DISP_IOCTL_BASE</a>   (FVID2_DSS_DRV_IOCTL_BASE + 0x000U)</td></tr>
+<tr class="memdesc:gaf8566eb291e6ce8c67bf5158426d42b9"><td class="mdescLeft"> </td><td class="mdescRight">IOCTL base address for the display driver IOCTLs. <br/></td></tr>
+<tr class="separator:gaf8566eb291e6ce8c67bf5158426d42b9"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga9f2d978d01f7c34d373f956e5e5862d1"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga9f2d978d01f7c34d373f956e5e5862d1"></a>
+#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___d_s_s.html#ga9f2d978d01f7c34d373f956e5e5862d1">DSS_DCTRL_IOCTL_BASE</a>   (FVID2_DSS_DRV_IOCTL_BASE + 0x100U)</td></tr>
+<tr class="memdesc:ga9f2d978d01f7c34d373f956e5e5862d1"><td class="mdescLeft"> </td><td class="mdescRight">IOCTL base address for the display controller driver IOCTLs. <br/></td></tr>
+<tr class="separator:ga9f2d978d01f7c34d373f956e5e5862d1"><td class="memSeparator" colspan="2"> </td></tr>
+</table><table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a>
+Functions</h2></td></tr>
+<tr class="memitem:ga148ec5eeed6ef017fddce29adee32e90"><td class="memItemLeft" align="right" valign="top">void </td><td class="memItemRight" valign="bottom"><a class="el" href="group___d_s_s.html#ga148ec5eeed6ef017fddce29adee32e90">Dss_initParamsInit</a> (<a class="el" href="struct_dss___init_params.html">Dss_InitParams</a> *dssParams)</td></tr>
+<tr class="memdesc:ga148ec5eeed6ef017fddce29adee32e90"><td class="mdescLeft"> </td><td class="mdescRight"><a class="el" href="struct_dss___init_params.html" title="DSS initialization parameters. ">Dss_InitParams</a> structure init function. <a href="#ga148ec5eeed6ef017fddce29adee32e90">More...</a><br/></td></tr>
+<tr class="separator:ga148ec5eeed6ef017fddce29adee32e90"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga9a7600eb912fe78c81a4e5fd88b495f6"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group___d_s_s.html#ga9a7600eb912fe78c81a4e5fd88b495f6">Dss_init</a> (const <a class="el" href="struct_dss___init_params.html">Dss_InitParams</a> *initParams)</td></tr>
+<tr class="memdesc:ga9a7600eb912fe78c81a4e5fd88b495f6"><td class="mdescLeft"> </td><td class="mdescRight">DSS initialization function. This function initializes the DSS hardware and drivers. This function should be called before calling any driver APIs and only once. <a href="#ga9a7600eb912fe78c81a4e5fd88b495f6">More...</a><br/></td></tr>
+<tr class="separator:ga9a7600eb912fe78c81a4e5fd88b495f6"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga8da153ec94fd77b1238623030aedd76e"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="group___d_s_s.html#ga8da153ec94fd77b1238623030aedd76e">Dss_deInit</a> (void)</td></tr>
+<tr class="memdesc:ga8da153ec94fd77b1238623030aedd76e"><td class="mdescLeft"> </td><td class="mdescRight">DSS de-initialization function. This function un-initializes the DSS hardware and drivers. This function should be called during system shutdown if <a class="el" href="group___d_s_s.html#ga9a7600eb912fe78c81a4e5fd88b495f6" title="DSS initialization function. This function initializes the DSS hardware and drivers. This function should be called before calling any driver APIs and only once. ">Dss_init()</a> was called by the application. <a href="#ga8da153ec94fd77b1238623030aedd76e">More...</a><br/></td></tr>
+<tr class="separator:ga8da153ec94fd77b1238623030aedd76e"><td class="memSeparator" colspan="2"> </td></tr>
+</table>
+<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
+<h2 class="groupheader">Function Documentation</h2>
+<a class="anchor" id="ga8da153ec94fd77b1238623030aedd76e"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">int32_t Dss_deInit </td>
+ <td>(</td>
+ <td class="paramtype">void </td>
+ <td class="paramname"></td><td>)</td>
+ <td></td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+
+<p>DSS de-initialization function. This function un-initializes the DSS hardware and drivers. This function should be called during system shutdown if <a class="el" href="group___d_s_s.html#ga9a7600eb912fe78c81a4e5fd88b495f6" title="DSS initialization function. This function initializes the DSS hardware and drivers. This function should be called before calling any driver APIs and only once. ">Dss_init()</a> was called by the application. </p>
+<dl class="section return"><dt>Returns</dt><dd>FVID2_SOK if successful, else suitable error code </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga9a7600eb912fe78c81a4e5fd88b495f6"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">int32_t Dss_init </td>
+ <td>(</td>
+ <td class="paramtype">const <a class="el" href="struct_dss___init_params.html">Dss_InitParams</a> * </td>
+ <td class="paramname"><em>initParams</em></td><td>)</td>
+ <td></td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+
+<p>DSS initialization function. This function initializes the DSS hardware and drivers. This function should be called before calling any driver APIs and only once. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">initParams</td><td>Pointer to a <a class="el" href="struct_dss___init_params.html" title="DSS initialization parameters. ">Dss_InitParams</a> structure containing the DSS configuration</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>FVID2_SOK if successful, else suitable error code </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga148ec5eeed6ef017fddce29adee32e90"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">void Dss_initParamsInit </td>
+ <td>(</td>
+ <td class="paramtype"><a class="el" href="struct_dss___init_params.html">Dss_InitParams</a> * </td>
+ <td class="paramname"><em>dssParams</em></td><td>)</td>
+ <td></td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+
+<p><a class="el" href="struct_dss___init_params.html" title="DSS initialization parameters. ">Dss_InitParams</a> structure init function. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">dssParams</td><td>Pointer to <a class="el" href="struct_dss___init_params.html" title="DSS initialization parameters. ">Dss_InitParams</a> structure.</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>None </dd></dl>
+
+</div>
+</div>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
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+<div class="title">DSS_DCTRL_IOCTL</div> </div>
+</div><!--header-->
+<div class="contents">
+<table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
+Macros</h2></td></tr>
+<tr class="memitem:gae55f1184bc13a50a4e113e95835a5d0c"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___d_s_s___d_c_t_r_l___i_o_c_t_l.html#gae55f1184bc13a50a4e113e95835a5d0c">IOCTL_DSS_DCTRL_SET_PATH</a>   (<a class="el" href="group___d_s_s.html#ga9f2d978d01f7c34d373f956e5e5862d1">DSS_DCTRL_IOCTL_BASE</a> + 0x01U)</td></tr>
+<tr class="memdesc:gae55f1184bc13a50a4e113e95835a5d0c"><td class="mdescLeft"> </td><td class="mdescRight">Command to set the DSS display path configuration. <a href="#gae55f1184bc13a50a4e113e95835a5d0c">More...</a><br/></td></tr>
+<tr class="separator:gae55f1184bc13a50a4e113e95835a5d0c"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga4b16831ed360d38789d105376246c41a"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___d_s_s___d_c_t_r_l___i_o_c_t_l.html#ga4b16831ed360d38789d105376246c41a">IOCTL_DSS_DCTRL_CLEAR_PATH</a>   (<a class="el" href="group___d_s_s.html#ga9f2d978d01f7c34d373f956e5e5862d1">DSS_DCTRL_IOCTL_BASE</a> + 0x02U)</td></tr>
+<tr class="memdesc:ga4b16831ed360d38789d105376246c41a"><td class="mdescLeft"> </td><td class="mdescRight">Command to clear the DSS display path configuration. <a href="#ga4b16831ed360d38789d105376246c41a">More...</a><br/></td></tr>
+<tr class="separator:ga4b16831ed360d38789d105376246c41a"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gad9d06c559d83e6b0cd1fb72dfeca55c0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___d_s_s___d_c_t_r_l___i_o_c_t_l.html#gad9d06c559d83e6b0cd1fb72dfeca55c0">IOCTL_DSS_DCTRL_SET_VP_PARAMS</a>   (<a class="el" href="group___d_s_s.html#ga9f2d978d01f7c34d373f956e5e5862d1">DSS_DCTRL_IOCTL_BASE</a> + 0x03U)</td></tr>
+<tr class="memdesc:gad9d06c559d83e6b0cd1fb72dfeca55c0"><td class="mdescLeft"> </td><td class="mdescRight">Command to set Video Port configuration. <a href="#gad9d06c559d83e6b0cd1fb72dfeca55c0">More...</a><br/></td></tr>
+<tr class="separator:gad9d06c559d83e6b0cd1fb72dfeca55c0"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga076d70564e492c0780bc4c747ca7ee82"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___d_s_s___d_c_t_r_l___i_o_c_t_l.html#ga076d70564e492c0780bc4c747ca7ee82">IOCTL_DSS_DCTRL_SET_OVERLAY_PARAMS</a>   (<a class="el" href="group___d_s_s.html#ga9f2d978d01f7c34d373f956e5e5862d1">DSS_DCTRL_IOCTL_BASE</a> + 0x04U)</td></tr>
+<tr class="memdesc:ga076d70564e492c0780bc4c747ca7ee82"><td class="mdescLeft"> </td><td class="mdescRight">Command to set configuration of the given overlay. <a href="#ga076d70564e492c0780bc4c747ca7ee82">More...</a><br/></td></tr>
+<tr class="separator:ga076d70564e492c0780bc4c747ca7ee82"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga824609e625e41769f9042b8879a73861"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___d_s_s___d_c_t_r_l___i_o_c_t_l.html#ga824609e625e41769f9042b8879a73861">IOCTL_DSS_DCTRL_SET_LAYER_PARAMS</a>   (<a class="el" href="group___d_s_s.html#ga9f2d978d01f7c34d373f956e5e5862d1">DSS_DCTRL_IOCTL_BASE</a> + 0x05U)</td></tr>
+<tr class="memdesc:ga824609e625e41769f9042b8879a73861"><td class="mdescLeft"> </td><td class="mdescRight">Command to set layer/Z-order configuration of the given overlay. <a href="#ga824609e625e41769f9042b8879a73861">More...</a><br/></td></tr>
+<tr class="separator:ga824609e625e41769f9042b8879a73861"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gad01ce1c58a3a6966395f29a6d61d7684"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___d_s_s___d_c_t_r_l___i_o_c_t_l.html#gad01ce1c58a3a6966395f29a6d61d7684">IOCTL_DSS_DCTRL_SET_VP_CSC_COEFF</a>   (<a class="el" href="group___d_s_s.html#ga9f2d978d01f7c34d373f956e5e5862d1">DSS_DCTRL_IOCTL_BASE</a> + 0x06U)</td></tr>
+<tr class="memdesc:gad01ce1c58a3a6966395f29a6d61d7684"><td class="mdescLeft"> </td><td class="mdescRight">Command to program the CSC coefficients for Video Port. By default BT 601 coefficients are set. <a href="#gad01ce1c58a3a6966395f29a6d61d7684">More...</a><br/></td></tr>
+<tr class="separator:gad01ce1c58a3a6966395f29a6d61d7684"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga41ce0b6adeb9b7e098ce3b84113bf48f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___d_s_s___d_c_t_r_l___i_o_c_t_l.html#ga41ce0b6adeb9b7e098ce3b84113bf48f">IOCTL_DSS_DCTRL_SET_ADV_VP_PARAMS</a>   (<a class="el" href="group___d_s_s.html#ga9f2d978d01f7c34d373f956e5e5862d1">DSS_DCTRL_IOCTL_BASE</a> + 0x07U)</td></tr>
+<tr class="memdesc:ga41ce0b6adeb9b7e098ce3b84113bf48f"><td class="mdescLeft"> </td><td class="mdescRight">Command to set advance Video Port configuration. <a href="#ga41ce0b6adeb9b7e098ce3b84113bf48f">More...</a><br/></td></tr>
+<tr class="separator:ga41ce0b6adeb9b7e098ce3b84113bf48f"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga381f6aa554cc69e7fdb6dc6022086cee"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___d_s_s___d_c_t_r_l___i_o_c_t_l.html#ga381f6aa554cc69e7fdb6dc6022086cee">IOCTL_DSS_DCTRL_SET_LCD_BLANK_TIMING_PARAMS</a>   (<a class="el" href="group___d_s_s.html#ga9f2d978d01f7c34d373f956e5e5862d1">DSS_DCTRL_IOCTL_BASE</a> + 0x08U)</td></tr>
+<tr class="memdesc:ga381f6aa554cc69e7fdb6dc6022086cee"><td class="mdescLeft"> </td><td class="mdescRight">Command to program blank timing parameters of given LCD. <a href="#ga381f6aa554cc69e7fdb6dc6022086cee">More...</a><br/></td></tr>
+<tr class="separator:ga381f6aa554cc69e7fdb6dc6022086cee"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gabcaa1961abdf4145c9db4cedffe58259"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___d_s_s___d_c_t_r_l___i_o_c_t_l.html#gabcaa1961abdf4145c9db4cedffe58259">IOCTL_DSS_DCTRL_SET_VP_SAFETY_CHK_PARAMS</a>   (<a class="el" href="group___d_s_s.html#ga9f2d978d01f7c34d373f956e5e5862d1">DSS_DCTRL_IOCTL_BASE</a> + 0x09U)</td></tr>
+<tr class="memdesc:gabcaa1961abdf4145c9db4cedffe58259"><td class="mdescLeft"> </td><td class="mdescRight">Command to program Safety Check configuration at Video Port Output. <a href="#gabcaa1961abdf4145c9db4cedffe58259">More...</a><br/></td></tr>
+<tr class="separator:gabcaa1961abdf4145c9db4cedffe58259"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga3d29253c153bdec7275527bd0b8fe4dc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___d_s_s___d_c_t_r_l___i_o_c_t_l.html#ga3d29253c153bdec7275527bd0b8fe4dc">IOCTL_DSS_DCTRL_GET_VP_ERROR_STATS</a>   (<a class="el" href="group___d_s_s.html#ga9f2d978d01f7c34d373f956e5e5862d1">DSS_DCTRL_IOCTL_BASE</a> + 0x0AU)</td></tr>
+<tr class="memdesc:ga3d29253c153bdec7275527bd0b8fe4dc"><td class="mdescLeft"> </td><td class="mdescRight">IOCTL to get the number of errors for a given Video Port. <a href="#ga3d29253c153bdec7275527bd0b8fe4dc">More...</a><br/></td></tr>
+<tr class="separator:ga3d29253c153bdec7275527bd0b8fe4dc"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga48fd0f5f1e1476ef03b203ae9b1ccfaa"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___d_s_s___d_c_t_r_l___i_o_c_t_l.html#ga48fd0f5f1e1476ef03b203ae9b1ccfaa">IOCTL_DSS_DCTRL_SET_GLOBAL_DSS_PARAMS</a>   (<a class="el" href="group___d_s_s.html#ga9f2d978d01f7c34d373f956e5e5862d1">DSS_DCTRL_IOCTL_BASE</a> + 0x0BU)</td></tr>
+<tr class="memdesc:ga48fd0f5f1e1476ef03b203ae9b1ccfaa"><td class="mdescLeft"> </td><td class="mdescRight">IOCTL to set the global DSS parameters. <a href="#ga48fd0f5f1e1476ef03b203ae9b1ccfaa">More...</a><br/></td></tr>
+<tr class="separator:ga48fd0f5f1e1476ef03b203ae9b1ccfaa"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga626c83cf4afb58295e807b710e10c5b0"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___d_s_s___d_c_t_r_l___i_o_c_t_l.html#ga626c83cf4afb58295e807b710e10c5b0">IOCTL_DSS_DCTRL_STOP_VP</a>   (<a class="el" href="group___d_s_s.html#ga9f2d978d01f7c34d373f956e5e5862d1">DSS_DCTRL_IOCTL_BASE</a> + 0x0CU)</td></tr>
+<tr class="memdesc:ga626c83cf4afb58295e807b710e10c5b0"><td class="mdescLeft"> </td><td class="mdescRight">Command to disable Video Port. <a href="#ga626c83cf4afb58295e807b710e10c5b0">More...</a><br/></td></tr>
+<tr class="separator:ga626c83cf4afb58295e807b710e10c5b0"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga0605d3de6b43d543ab11a8ba54a5fdbc"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___d_s_s___d_c_t_r_l___i_o_c_t_l.html#ga0605d3de6b43d543ab11a8ba54a5fdbc">IOCTL_DSS_DCTRL_SET_OLDI_PARAMS</a>   (<a class="el" href="group___d_s_s.html#ga9f2d978d01f7c34d373f956e5e5862d1">DSS_DCTRL_IOCTL_BASE</a> + 0x0DU)</td></tr>
+<tr class="memdesc:ga0605d3de6b43d543ab11a8ba54a5fdbc"><td class="mdescLeft"> </td><td class="mdescRight">IOCTL to set the OLDI configuration of given video port. <a href="#ga0605d3de6b43d543ab11a8ba54a5fdbc">More...</a><br/></td></tr>
+<tr class="separator:ga0605d3de6b43d543ab11a8ba54a5fdbc"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gae4ab29ac71849b0ad7810e5fecaf2b00"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___d_s_s___d_c_t_r_l___i_o_c_t_l.html#gae4ab29ac71849b0ad7810e5fecaf2b00">IOCTL_DSS_DCTRL_REGISTER_SYNCLOST_CB</a>   (<a class="el" href="group___d_s_s.html#ga9f2d978d01f7c34d373f956e5e5862d1">DSS_DCTRL_IOCTL_BASE</a> + 0x0EU)</td></tr>
+<tr class="memdesc:gae4ab29ac71849b0ad7810e5fecaf2b00"><td class="mdescLeft"> </td><td class="mdescRight">Command to register Video Port sync lost callback function. <a href="#gae4ab29ac71849b0ad7810e5fecaf2b00">More...</a><br/></td></tr>
+<tr class="separator:gae4ab29ac71849b0ad7810e5fecaf2b00"><td class="memSeparator" colspan="2"> </td></tr>
+</table>
+<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
+<h2 class="groupheader">Macro Definition Documentation</h2>
+<a class="anchor" id="ga4b16831ed360d38789d105376246c41a"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">#define IOCTL_DSS_DCTRL_CLEAR_PATH   (<a class="el" href="group___d_s_s.html#ga9f2d978d01f7c34d373f956e5e5862d1">DSS_DCTRL_IOCTL_BASE</a> + 0x02U)</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+
+<p>Command to clear the DSS display path configuration. </p>
+<p>This IOCTL takes list of edges connecting nodes and clears the configuration. It also stops Video Ports.</p>
+<p>It does not validates the edge list. It simply disables the edge connecting nodes. For the Video Ports, it checks for the validity and then disables the video port if there are no errors. Use macros defined in <<a class="el" href="dss__soc_8h.html" title="DSS Driver AM65xx SOC specific file. ">dss_soc.h</a>> for different node ids.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">cmdArgs</td><td>[IN] Pointer of type <a class="el" href="struct_dss___dctrl_path_info.html" title="Structure containing DSS path information. This structure is used as an argument to IOCTL_DSS_DCTRL_S...">Dss_DctrlPathInfo</a> </td></tr>
+ <tr><td class="paramname">cmdArgsStatus</td><td>[OUT] NULL</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>FVID2_SOK if successful, else suitable error code </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga3d29253c153bdec7275527bd0b8fe4dc"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">#define IOCTL_DSS_DCTRL_GET_VP_ERROR_STATS   (<a class="el" href="group___d_s_s.html#ga9f2d978d01f7c34d373f956e5e5862d1">DSS_DCTRL_IOCTL_BASE</a> + 0x0AU)</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+
+<p>IOCTL to get the number of errors for a given Video Port. </p>
+<p>This IOCTL is used to get the count of sync lost errors, security violations and safety check errors for a given video port.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">cmdArgs</td><td>[IN] Pointer of type <a class="el" href="struct_dss___dctrl_vp_error_stats.html" title="Structure containing Error Stats of Video Port. This structure is used as an argument to IOCTL_DSS_DC...">Dss_DctrlVpErrorStats</a> </td></tr>
+ <tr><td class="paramname">cmdArgsStatus</td><td>[OUT] NULL</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>FVID2_SOK if successful, else suitable error code </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="gae4ab29ac71849b0ad7810e5fecaf2b00"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">#define IOCTL_DSS_DCTRL_REGISTER_SYNCLOST_CB   (<a class="el" href="group___d_s_s.html#ga9f2d978d01f7c34d373f956e5e5862d1">DSS_DCTRL_IOCTL_BASE</a> + 0x0EU)</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+
+<p>Command to register Video Port sync lost callback function. </p>
+<p>This IOCTL can be used to register a callback when there is a sync loss for a particular video port. See <a class="el" href="dss__dctrl_8h.html#adc02df6de7a3d5940da55838ee464701" title="Video Port sync loss callback function prototype. ">Dss_DctrlSyncLostCbFxn</a> for details. This IOCTL is per Video Port and hence should be called separately for each port. Note: syncLostCbFxn should be set to NULL in order to unregister the callback.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">cmdArgs</td><td>[IN] Pointer of type <a class="el" href="struct_dss___dctrl_sync_lost_cb_params.html" title="Structure containing Sync Lost callback parameters. This structure is used as an argument to IOCTL_DS...">Dss_DctrlSyncLostCbParams</a> </td></tr>
+ <tr><td class="paramname">cmdArgsStatus</td><td>[OUT] NULL</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>FVID2_SOK if successful, else suitable error code </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga41ce0b6adeb9b7e098ce3b84113bf48f"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">#define IOCTL_DSS_DCTRL_SET_ADV_VP_PARAMS   (<a class="el" href="group___d_s_s.html#ga9f2d978d01f7c34d373f956e5e5862d1">DSS_DCTRL_IOCTL_BASE</a> + 0x07U)</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+
+<p>Command to set advance Video Port configuration. </p>
+<p>This IOCTL is used to program the advance Video Port configuration. Refer <a class="el" href="struct_dss___dctrl_adv_vp_params.html" title="Structure containing advance Video Port information. This structure is used as an argument to IOCTL_D...">Dss_DctrlAdvVpParams</a> for configuration details.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">cmdArgs</td><td>[IN] Pointer of type <a class="el" href="struct_dss___dctrl_adv_vp_params.html" title="Structure containing advance Video Port information. This structure is used as an argument to IOCTL_D...">Dss_DctrlAdvVpParams</a> </td></tr>
+ <tr><td class="paramname">cmdArgsStatus</td><td>[OUT] NULL</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>FVID2_SOK if successful, else suitable error code </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga48fd0f5f1e1476ef03b203ae9b1ccfaa"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">#define IOCTL_DSS_DCTRL_SET_GLOBAL_DSS_PARAMS   (<a class="el" href="group___d_s_s.html#ga9f2d978d01f7c34d373f956e5e5862d1">DSS_DCTRL_IOCTL_BASE</a> + 0x0BU)</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+
+<p>IOCTL to set the global DSS parameters. </p>
+<p>This IOCTL can be used to set the global mflag and CBA configuration.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">cmdArgs</td><td>[IN] Pointer of type <a class="el" href="struct_dss___dctrl_global_dss_params.html" title="Structure containing global DSS Configuration. This structure is used as an argument to IOCTL_DSS_DCT...">Dss_DctrlGlobalDssParams</a> </td></tr>
+ <tr><td class="paramname">cmdArgsStatus</td><td>[OUT] NULL</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>FVID2_SOK if successful, else suitable error code </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga824609e625e41769f9042b8879a73861"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">#define IOCTL_DSS_DCTRL_SET_LAYER_PARAMS   (<a class="el" href="group___d_s_s.html#ga9f2d978d01f7c34d373f956e5e5862d1">DSS_DCTRL_IOCTL_BASE</a> + 0x05U)</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+
+<p>Command to set layer/Z-order configuration of the given overlay. </p>
+<p>This IOCTL is used to set the layer/Z-order configuration. Refer <a class="el" href="struct_dss___dctrl_overlay_layer_params.html" title="Structure containing Overlay layer information. This structure is used as an argument to IOCTL_DSS_DC...">Dss_DctrlOverlayLayerParams</a> for details. Note: User should pass the layer configuration for all the video pipes which are present in the DSS in order to set/change the Z order. In case a particular pipe is disabled, layerNum should be set to CSL_DSS_OVERLAY_LAYER_INVALID.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">cmdArgs</td><td>[IN] Pointer of type <a class="el" href="struct_dss___dctrl_overlay_layer_params.html" title="Structure containing Overlay layer information. This structure is used as an argument to IOCTL_DSS_DC...">Dss_DctrlOverlayLayerParams</a> </td></tr>
+ <tr><td class="paramname">cmdArgsStatus</td><td>[OUT] NULL</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>FVID2_SOK if successful, else suitable error code </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga381f6aa554cc69e7fdb6dc6022086cee"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">#define IOCTL_DSS_DCTRL_SET_LCD_BLANK_TIMING_PARAMS   (<a class="el" href="group___d_s_s.html#ga9f2d978d01f7c34d373f956e5e5862d1">DSS_DCTRL_IOCTL_BASE</a> + 0x08U)</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+
+<p>Command to program blank timing parameters of given LCD. </p>
+<p>This IOCTL is used to program the blank timing parameters for the LCD. This IOCTL can be called dynamically at runtime. Note: The change in timing will take effect from the next vsync. This API should be called in the vsync callback to the application in the ISR context or immediately after that in task/swi context. Calling this IOCTL near the vsync should be avoided as the shadow to work copy could happens while we are changing the timing parameters and could result in taking only a part of this configuration for next one frame or delaying the timing change by next one frame. Subsequent frames will have proper timing.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">cmdArgs</td><td>[IN] Pointer of type <a class="el" href="struct_dss___dctrl_lcd_blank_timing_params.html" title="Structure containing LCD Blank Timing Configuration. This structure is used as an argument to IOCTL_D...">Dss_DctrlLcdBlankTimingParams</a> </td></tr>
+ <tr><td class="paramname">cmdArgsStatus</td><td>[OUT] NULL</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>FVID2_SOK if successful, else suitable error code </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga0605d3de6b43d543ab11a8ba54a5fdbc"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">#define IOCTL_DSS_DCTRL_SET_OLDI_PARAMS   (<a class="el" href="group___d_s_s.html#ga9f2d978d01f7c34d373f956e5e5862d1">DSS_DCTRL_IOCTL_BASE</a> + 0x0DU)</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+
+<p>IOCTL to set the OLDI configuration of given video port. </p>
+<p>This IOCTL can be used to set the OLDI parameters. Refer <a class="el" href="struct_dss___dctrl_oldi_params.html" title="Structure containing OLDI configuration. This structure is used as an argument to IOCTL_DSS_DCTRL_SET...">Dss_DctrlOldiParams</a> for configuration details. Note: This IOCTL is supported only for AM65xx SoC.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">cmdArgs</td><td>[IN] Pointer of type <a class="el" href="struct_dss___dctrl_oldi_params.html" title="Structure containing OLDI configuration. This structure is used as an argument to IOCTL_DSS_DCTRL_SET...">Dss_DctrlOldiParams</a> </td></tr>
+ <tr><td class="paramname">cmdArgsStatus</td><td>[OUT] NULL</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>FVID2_SOK if successful, else suitable error code </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga076d70564e492c0780bc4c747ca7ee82"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">#define IOCTL_DSS_DCTRL_SET_OVERLAY_PARAMS   (<a class="el" href="group___d_s_s.html#ga9f2d978d01f7c34d373f956e5e5862d1">DSS_DCTRL_IOCTL_BASE</a> + 0x04U)</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+
+<p>Command to set configuration of the given overlay. </p>
+<p>This IOCTL is used to set the different Overlay parameters. Refer <a class="el" href="struct_dss___dctrl_overlay_params.html" title="Structure containing Overlay information. This structure is used as an argument to IOCTL_DSS_DCTRL_SE...">Dss_DctrlOverlayParams</a> for configuration details. Note: In case color bar enable is TRUE then this IOCTL should be called at the end after doing all other display controller configuration.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">cmdArgs</td><td>[IN] Pointer of type <a class="el" href="struct_dss___dctrl_overlay_params.html" title="Structure containing Overlay information. This structure is used as an argument to IOCTL_DSS_DCTRL_SE...">Dss_DctrlOverlayParams</a> </td></tr>
+ <tr><td class="paramname">cmdArgsStatus</td><td>[OUT] NULL</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>FVID2_SOK if successful, else suitable error code </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="gae55f1184bc13a50a4e113e95835a5d0c"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">#define IOCTL_DSS_DCTRL_SET_PATH   (<a class="el" href="group___d_s_s.html#ga9f2d978d01f7c34d373f956e5e5862d1">DSS_DCTRL_IOCTL_BASE</a> + 0x01U)</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+
+<p>Command to set the DSS display path configuration. </p>
+<p>All the DSS modules handled by the Display Controller can be represented by a graph, where node represents a module like video port, overlay etc. and edge is present between two nodes if they are connected. All DSS paths can be configured by this IOCTL in one shot. Use macros defined in <<a class="el" href="dss__soc_8h.html" title="DSS Driver AM65xx SOC specific file. ">dss_soc.h</a>> for different node ids.</p>
+<p>This IOCTL takes list of edges connecting nodes and configures display paths. It first validates these paths and then configures DSS for the display paths. It configures all the modules present in the path.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">cmdArgs</td><td>[IN] Pointer of type <a class="el" href="struct_dss___dctrl_path_info.html" title="Structure containing DSS path information. This structure is used as an argument to IOCTL_DSS_DCTRL_S...">Dss_DctrlPathInfo</a> </td></tr>
+ <tr><td class="paramname">cmdArgsStatus</td><td>[OUT] NULL</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>FVID2_SOK if successful, else suitable error code </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="gad01ce1c58a3a6966395f29a6d61d7684"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">#define IOCTL_DSS_DCTRL_SET_VP_CSC_COEFF   (<a class="el" href="group___d_s_s.html#ga9f2d978d01f7c34d373f956e5e5862d1">DSS_DCTRL_IOCTL_BASE</a> + 0x06U)</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+
+<p>Command to program the CSC coefficients for Video Port. By default BT 601 coefficients are set. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">cmdArgs</td><td>[IN] Pointer of type <a class="el" href="struct_dss___dctrl_vp_csc_coeff.html" title="Structure containing Video Port CSC information. This structure is used as an argument to IOCTL_DSS_D...">Dss_DctrlVpCscCoeff</a> </td></tr>
+ <tr><td class="paramname">cmdArgsStatus</td><td>[OUT] NULL</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>FVID2_SOK if successful, else suitable error code </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="gad9d06c559d83e6b0cd1fb72dfeca55c0"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">#define IOCTL_DSS_DCTRL_SET_VP_PARAMS   (<a class="el" href="group___d_s_s.html#ga9f2d978d01f7c34d373f956e5e5862d1">DSS_DCTRL_IOCTL_BASE</a> + 0x03U)</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+
+<p>Command to set Video Port configuration. </p>
+<p>This IOCTL is used to set the Video Port configuration if Video Port is not on. For the enabled Video Port, port has to be stopped first, then configuration can can be changed. Refer <a class="el" href="struct_dss___dctrl_vp_params.html" title="Structure containing Video Port information. This structure is used as an argument to IOCTL_DSS_DCTRL...">Dss_DctrlVpParams</a> for configuration details. This IOCTL should be called before IOCTL_DSS_DCTRL_SET_PATH.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">cmdArgs</td><td>[IN] Pointer of type <a class="el" href="struct_dss___dctrl_vp_params.html" title="Structure containing Video Port information. This structure is used as an argument to IOCTL_DSS_DCTRL...">Dss_DctrlVpParams</a> </td></tr>
+ <tr><td class="paramname">cmdArgsStatus</td><td>[OUT] NULL</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>FVID2_SOK if successful, else suitable error code </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="gabcaa1961abdf4145c9db4cedffe58259"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">#define IOCTL_DSS_DCTRL_SET_VP_SAFETY_CHK_PARAMS   (<a class="el" href="group___d_s_s.html#ga9f2d978d01f7c34d373f956e5e5862d1">DSS_DCTRL_IOCTL_BASE</a> + 0x09U)</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+
+<p>Command to program Safety Check configuration at Video Port Output. </p>
+<p>This IOCTL is used to program the safety check configuration parameters. Note: There are up to four sub-regions within the active video output in which safety check can be enabled. This IOCTL should be called separately for each region.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">cmdArgs</td><td>[IN] Pointer of type <a class="el" href="struct_dss___dctrl_vp_safety_chk_params.html" title="Structure containing Safety Check configuration of Video Port. This structure is used as an argument ...">Dss_DctrlVpSafetyChkParams</a> </td></tr>
+ <tr><td class="paramname">cmdArgsStatus</td><td>[OUT] NULL</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>FVID2_SOK if successful, else suitable error code </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga626c83cf4afb58295e807b710e10c5b0"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">#define IOCTL_DSS_DCTRL_STOP_VP   (<a class="el" href="group___d_s_s.html#ga9f2d978d01f7c34d373f956e5e5862d1">DSS_DCTRL_IOCTL_BASE</a> + 0x0CU)</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+
+<p>Command to disable Video Port. </p>
+<p>This IOCTL is used to disable the Video Port. Refer <a class="el" href="struct_dss___dctrl_vp_params.html" title="Structure containing Video Port information. This structure is used as an argument to IOCTL_DSS_DCTRL...">Dss_DctrlVpParams</a> for configuration details.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">cmdArgs</td><td>[IN] Pointer of type <a class="el" href="struct_dss___dctrl_vp_params.html" title="Structure containing Video Port information. This structure is used as an argument to IOCTL_DSS_DCTRL...">Dss_DctrlVpParams</a> </td></tr>
+ <tr><td class="paramname">cmdArgsStatus</td><td>[OUT] NULL</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>FVID2_SOK if successful, else suitable error code </dd></dl>
+
+</div>
+</div>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
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+<div class="title">DSS_DISP_IOCTL</div> </div>
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+<div class="contents">
+<table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
+Macros</h2></td></tr>
+<tr class="memitem:ga4bd8cea3f070081f575996cc7fe3571f"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___d_s_s___d_i_s_p___i_o_c_t_l.html#ga4bd8cea3f070081f575996cc7fe3571f">IOCTL_DSS_DISP_SET_DSS_PARAMS</a>   (<a class="el" href="group___d_s_s.html#gaf8566eb291e6ce8c67bf5158426d42b9">DSS_DISP_IOCTL_BASE</a> + 0x0001U)</td></tr>
+<tr class="memdesc:ga4bd8cea3f070081f575996cc7fe3571f"><td class="mdescLeft"> </td><td class="mdescRight">Command to set DSS display parameters. <a href="#ga4bd8cea3f070081f575996cc7fe3571f">More...</a><br/></td></tr>
+<tr class="separator:ga4bd8cea3f070081f575996cc7fe3571f"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga9643f8f73bbe0006d0c56d0bcedccef5"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___d_s_s___d_i_s_p___i_o_c_t_l.html#ga9643f8f73bbe0006d0c56d0bcedccef5">IOCTL_DSS_DISP_SET_PIPE_MFLAG_PARAMS</a>   (<a class="el" href="group___d_s_s.html#gaf8566eb291e6ce8c67bf5158426d42b9">DSS_DISP_IOCTL_BASE</a> + 0x0002U)</td></tr>
+<tr class="memdesc:ga9643f8f73bbe0006d0c56d0bcedccef5"><td class="mdescLeft"> </td><td class="mdescRight">Command to set MFLAG parameters for video pipe. <a href="#ga9643f8f73bbe0006d0c56d0bcedccef5">More...</a><br/></td></tr>
+<tr class="separator:ga9643f8f73bbe0006d0c56d0bcedccef5"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga0b629ede4d23a166a0d61a8a467cf2a7"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___d_s_s___d_i_s_p___i_o_c_t_l.html#ga0b629ede4d23a166a0d61a8a467cf2a7">IOCTL_DSS_DISP_GET_CURRENT_STATUS</a>   (<a class="el" href="group___d_s_s.html#gaf8566eb291e6ce8c67bf5158426d42b9">DSS_DISP_IOCTL_BASE</a> + 0x0003U)</td></tr>
+<tr class="memdesc:ga0b629ede4d23a166a0d61a8a467cf2a7"><td class="mdescLeft"> </td><td class="mdescRight">Command to get the display status. <a href="#ga0b629ede4d23a166a0d61a8a467cf2a7">More...</a><br/></td></tr>
+<tr class="separator:ga0b629ede4d23a166a0d61a8a467cf2a7"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga71325651456731ff972f3f976632f817"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___d_s_s___d_i_s_p___i_o_c_t_l.html#ga71325651456731ff972f3f976632f817">IOCTL_DSS_DISP_SET_PIPE_SAFETY_CHK_PARAMS</a>   (<a class="el" href="group___d_s_s.html#gaf8566eb291e6ce8c67bf5158426d42b9">DSS_DISP_IOCTL_BASE</a> + 0x0004U)</td></tr>
+<tr class="memdesc:ga71325651456731ff972f3f976632f817"><td class="mdescLeft"> </td><td class="mdescRight">Command to program Safety Check configuration at Video Pipe Output. <a href="#ga71325651456731ff972f3f976632f817">More...</a><br/></td></tr>
+<tr class="separator:ga71325651456731ff972f3f976632f817"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:gaa06196d5ebeb859291214d2d54b6858b"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___d_s_s___d_i_s_p___i_o_c_t_l.html#gaa06196d5ebeb859291214d2d54b6858b">IOCTL_DSS_DISP_SET_PIPE_CSC_COEFF</a>   (<a class="el" href="group___d_s_s.html#gaf8566eb291e6ce8c67bf5158426d42b9">DSS_DISP_IOCTL_BASE</a> + 0x0005U)</td></tr>
+<tr class="memdesc:gaa06196d5ebeb859291214d2d54b6858b"><td class="mdescLeft"> </td><td class="mdescRight">Command to program the CSC coefficients for Video Pipe. By default BT 601 coefficients are set. <a href="#gaa06196d5ebeb859291214d2d54b6858b">More...</a><br/></td></tr>
+<tr class="separator:gaa06196d5ebeb859291214d2d54b6858b"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga273f588861739dcf0a3e69409cb86946"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___d_s_s___d_i_s_p___i_o_c_t_l.html#ga273f588861739dcf0a3e69409cb86946">IOCTL_DSS_DISP_REGISTER_BUF_PRGM_CB</a>   (<a class="el" href="group___d_s_s.html#gaf8566eb291e6ce8c67bf5158426d42b9">DSS_DISP_IOCTL_BASE</a> + 0x0006U)</td></tr>
+<tr class="memdesc:ga273f588861739dcf0a3e69409cb86946"><td class="mdescLeft"> </td><td class="mdescRight">Command to register buffer program callback function. <a href="#ga273f588861739dcf0a3e69409cb86946">More...</a><br/></td></tr>
+<tr class="separator:ga273f588861739dcf0a3e69409cb86946"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga0cb126061bb1b12410ac877e1f8ba1eb"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___d_s_s___d_i_s_p___i_o_c_t_l.html#ga0cb126061bb1b12410ac877e1f8ba1eb">IOCTL_DSS_DISP_REGISTER_PIPE_PRGM_CB</a>   (<a class="el" href="group___d_s_s.html#gaf8566eb291e6ce8c67bf5158426d42b9">DSS_DISP_IOCTL_BASE</a> + 0x0007U)</td></tr>
+<tr class="memdesc:ga0cb126061bb1b12410ac877e1f8ba1eb"><td class="mdescLeft"> </td><td class="mdescRight">Command to register video pipe program callback function. <a href="#ga0cb126061bb1b12410ac877e1f8ba1eb">More...</a><br/></td></tr>
+<tr class="separator:ga0cb126061bb1b12410ac877e1f8ba1eb"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ga50c39b909c3e819d5662285112bbca59"><td class="memItemLeft" align="right" valign="top">#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group___d_s_s___d_i_s_p___i_o_c_t_l.html#ga50c39b909c3e819d5662285112bbca59">IOCTL_DSS_DISP_REGISTER_PIPE_UNDERFLOW_CB</a>   (<a class="el" href="group___d_s_s.html#gaf8566eb291e6ce8c67bf5158426d42b9">DSS_DISP_IOCTL_BASE</a> + 0x0008U)</td></tr>
+<tr class="memdesc:ga50c39b909c3e819d5662285112bbca59"><td class="mdescLeft"> </td><td class="mdescRight">Command to register video pipe underflow callback function. <a href="#ga50c39b909c3e819d5662285112bbca59">More...</a><br/></td></tr>
+<tr class="separator:ga50c39b909c3e819d5662285112bbca59"><td class="memSeparator" colspan="2"> </td></tr>
+</table>
+<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
+<h2 class="groupheader">Macro Definition Documentation</h2>
+<a class="anchor" id="ga0b629ede4d23a166a0d61a8a467cf2a7"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">#define IOCTL_DSS_DISP_GET_CURRENT_STATUS   (<a class="el" href="group___d_s_s.html#gaf8566eb291e6ce8c67bf5158426d42b9">DSS_DISP_IOCTL_BASE</a> + 0x0003U)</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+
+<p>Command to get the display status. </p>
+<p>This IOCTL can be used to get the display status like number of frames displayed, repeated, queued. dequeued, etc. Note: These counters will be reset either at the time of driver create or while starting the display operation. See respective counter comments for details.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">cmdArgs</td><td>[IN] Pointer of type <a class="el" href="struct_dss___disp_current_status.html" title="Structure containing current status of the display driver. This structure is used as an argument to I...">Dss_DispCurrentStatus</a> </td></tr>
+ <tr><td class="paramname">cmdArgsStatus</td><td>[OUT] NULL</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>FVID2_SOK if successful, else suitable error code </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga273f588861739dcf0a3e69409cb86946"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">#define IOCTL_DSS_DISP_REGISTER_BUF_PRGM_CB   (<a class="el" href="group___d_s_s.html#gaf8566eb291e6ce8c67bf5158426d42b9">DSS_DISP_IOCTL_BASE</a> + 0x0006U)</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+
+<p>Command to register buffer program callback function. </p>
+<p>This IOCTL can be used to register a callback when the actual buffer is getting programmed to the hardware. See <a class="el" href="dss__disp_8h.html#a3f3415894bf0e54f2d06f24ea22c602e" title="Display driver buffer program callback function prototype. ">Dss_DispBufPrgmCbFxn</a> for details. This IOCTL is per display driver instance and hence should be called separately for each display pipeline. Also this IOCTL should be called before starting the display. Note: bufPrgmCbFxn should be set to NULL in order to unregister the callback.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">cmdArgs</td><td>[IN] Pointer of type <a class="el" href="struct_dss___disp_buf_prgm_cb_params.html" title="Structure containing display buffer program callback parameters. This structure is used as an argumen...">Dss_DispBufPrgmCbParams</a> </td></tr>
+ <tr><td class="paramname">cmdArgsStatus</td><td>[OUT] NULL</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>FVID2_SOK if successful, else suitable error code </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga0cb126061bb1b12410ac877e1f8ba1eb"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">#define IOCTL_DSS_DISP_REGISTER_PIPE_PRGM_CB   (<a class="el" href="group___d_s_s.html#gaf8566eb291e6ce8c67bf5158426d42b9">DSS_DISP_IOCTL_BASE</a> + 0x0007U)</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+
+<p>Command to register video pipe program callback function. </p>
+<p>This IOCTL can be used to register a callback when the actual buffer has been programmed to the hardware. See <a class="el" href="dss__disp_8h.html#a4ccdd634499058281998bcc9a7af0555" title="Display driver video pipe program callback function prototype. ">Dss_DispPipePrgmCbFxn</a> for details. This IOCTL is per display driver instance and hence should be called separately for each display pipeline. Also this IOCTL should be called before starting the display. Note: pipePrgmCbFxn should be set to NULL in order to unregister the callback.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">cmdArgs</td><td>[IN] Pointer of type <a class="el" href="struct_dss___disp_pipe_prgm_cb_params.html" title="Structure containing video pipe program callback parameters. This structure is used as an argument to...">Dss_DispPipePrgmCbParams</a> </td></tr>
+ <tr><td class="paramname">cmdArgsStatus</td><td>[OUT] NULL</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>FVID2_SOK if successful, else suitable error code </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga50c39b909c3e819d5662285112bbca59"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">#define IOCTL_DSS_DISP_REGISTER_PIPE_UNDERFLOW_CB   (<a class="el" href="group___d_s_s.html#gaf8566eb291e6ce8c67bf5158426d42b9">DSS_DISP_IOCTL_BASE</a> + 0x0008U)</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+
+<p>Command to register video pipe underflow callback function. </p>
+<p>This IOCTL can be used to register a callback when there is a underflow for a particular video pipe. See <a class="el" href="dss__disp_8h.html#a14c7b8d97214b5c092eb8702e24522a1" title="Video pipe underflow callback function prototype. ">Dss_DispUnderFlowCbFxn</a> for details. This IOCTL is per display driver instance and hence should be called separately for each display pipeline. Also this IOCTL should be called before starting the display. Note: underFlowCbFxn should be set to NULL in order to unregister the callback.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">cmdArgs</td><td>[IN] Pointer of type <a class="el" href="struct_dss___disp_under_flow_cb_params.html" title="Structure containing pipe under flow callback parameters. This structure is used as an argument to IO...">Dss_DispUnderFlowCbParams</a> </td></tr>
+ <tr><td class="paramname">cmdArgsStatus</td><td>[OUT] NULL</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>FVID2_SOK if successful, else suitable error code </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga4bd8cea3f070081f575996cc7fe3571f"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">#define IOCTL_DSS_DISP_SET_DSS_PARAMS   (<a class="el" href="group___d_s_s.html#gaf8566eb291e6ce8c67bf5158426d42b9">DSS_DISP_IOCTL_BASE</a> + 0x0001U)</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+
+<p>Command to set DSS display parameters. </p>
+<p>This IOCTL is used to program the DSS display parameters. Refer to structure <a class="el" href="struct_dss___disp_params.html" title="Structure containing DSS parameters. This structure is used as an argument to IOCTL_DSS_DISP_SET_DSS_...">Dss_DispParams</a> for details on DSS parameters.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">cmdArgs</td><td>[IN] Pointer of type <a class="el" href="struct_dss___disp_params.html" title="Structure containing DSS parameters. This structure is used as an argument to IOCTL_DSS_DISP_SET_DSS_...">Dss_DispParams</a> </td></tr>
+ <tr><td class="paramname">cmdArgsStatus</td><td>[OUT] NULL</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>FVID2_SOK if successful, else suitable error code </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="gaa06196d5ebeb859291214d2d54b6858b"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">#define IOCTL_DSS_DISP_SET_PIPE_CSC_COEFF   (<a class="el" href="group___d_s_s.html#gaf8566eb291e6ce8c67bf5158426d42b9">DSS_DISP_IOCTL_BASE</a> + 0x0005U)</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+
+<p>Command to program the CSC coefficients for Video Pipe. By default BT 601 coefficients are set. </p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">cmdArgs</td><td>[IN] Pointer of type <a class="el" href="struct_c_s_l___dss_csc_coeff.html" title="Structure containing coefficients for Color Space Conversion. ">CSL_DssCscCoeff</a> </td></tr>
+ <tr><td class="paramname">cmdArgsStatus</td><td>[OUT] NULL</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>FVID2_SOK if successful, else suitable error code </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga9643f8f73bbe0006d0c56d0bcedccef5"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">#define IOCTL_DSS_DISP_SET_PIPE_MFLAG_PARAMS   (<a class="el" href="group___d_s_s.html#gaf8566eb291e6ce8c67bf5158426d42b9">DSS_DISP_IOCTL_BASE</a> + 0x0002U)</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+
+<p>Command to set MFLAG parameters for video pipe. </p>
+<p>This IOCTL can be used to set the MFLAG parameters for the given video pipe.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">cmdArgs</td><td>[IN] Pointer of type <a class="el" href="struct_dss___disp_pipe_mflag_params.html" title="Structure containing Video Pipe Mflag Information. This structure is used as an argument to IOCTL_DSS...">Dss_DispPipeMflagParams</a> </td></tr>
+ <tr><td class="paramname">cmdArgsStatus</td><td>[OUT] NULL</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>FVID2_SOK if successful, else suitable error code </dd></dl>
+
+</div>
+</div>
+<a class="anchor" id="ga71325651456731ff972f3f976632f817"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">#define IOCTL_DSS_DISP_SET_PIPE_SAFETY_CHK_PARAMS   (<a class="el" href="group___d_s_s.html#gaf8566eb291e6ce8c67bf5158426d42b9">DSS_DISP_IOCTL_BASE</a> + 0x0004U)</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+
+<p>Command to program Safety Check configuration at Video Pipe Output. </p>
+<p>This IOCTL is used to program the safety check configuration parameters.</p>
+<dl class="params"><dt>Parameters</dt><dd>
+ <table class="params">
+ <tr><td class="paramname">cmdArgs</td><td>[IN] Pointer of type <a class="el" href="struct_dss___disp_pipe_safety_chk_params.html" title="Structure containing Safety Check configuration of Video Port. This structure is used as an argument ...">Dss_DispPipeSafetyChkParams</a> </td></tr>
+ <tr><td class="paramname">cmdArgsStatus</td><td>[OUT] NULL</td></tr>
+ </table>
+ </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd>FVID2_SOK if successful, else suitable error code </dd></dl>
+
+</div>
+</div>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
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+<div class="levels">[detail level <span onclick="javascript:toggleLevel(1);">1</span><span onclick="javascript:toggleLevel(2);">2</span>]</div><table class="directory">
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+<tr id="row_0_3_" class="even"><td class="entry"><img src="ftv2vertline.png" alt="|" width="16" height="22" /><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html" target="_self">DSS Video Pipe CSL FL</a></td><td class="desc"></td></tr>
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+<tr id="row_1_" class="even"><td class="entry"><img src="ftv2node.png" alt="o" width="16" height="22" /><a class="el" href="group___d_s_s.html" target="_self">DSS Driver</a></td><td class="desc"></td></tr>
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+<a href="#pub-attribs">Data Fields</a> </div>
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+<div class="title">CSL_DssCbaCfg Struct Reference<div class="ingroups"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html">DSS Common CSL FL</a></div></div> </div>
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+<div class="contents">
+
+<p>DSS CBA Config parameters.
+ <a href="struct_c_s_l___dss_cba_cfg.html#details">More...</a></p>
+
+<p><code>#include <csl_dssCommon.h></code></p>
+<table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
+Data Fields</h2></td></tr>
+<tr class="memitem:a6f7af7472d1da8ba301750414e88640f"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_cba_cfg.html#a6f7af7472d1da8ba301750414e88640f">priHigh</a></td></tr>
+<tr class="separator:a6f7af7472d1da8ba301750414e88640f"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a6d3f899c4e19cf0e52d33d01295f75e7"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_cba_cfg.html#a6d3f899c4e19cf0e52d33d01295f75e7">priLow</a></td></tr>
+<tr class="separator:a6d3f899c4e19cf0e52d33d01295f75e7"><td class="memSeparator" colspan="2"> </td></tr>
+</table>
+<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
+<div class="textblock"><p>DSS CBA Config parameters. </p>
+</div><h2 class="groupheader">Field Documentation</h2>
+<a class="anchor" id="a6f7af7472d1da8ba301750414e88640f"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t CSL_DssCbaCfg::priHigh</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Priority level for high priority mflag transactions. Value of 0x0 indicates highest priority & value of 0x7 indicates lowest priority </p>
+
+</div>
+</div>
+<a class="anchor" id="a6d3f899c4e19cf0e52d33d01295f75e7"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t CSL_DssCbaCfg::priLow</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Priority level for normal non-mflag transactions. Value of 0x0 indicates highest priority & value of 0x7 indicates lowest priority </p>
+
+</div>
+</div>
+<hr/>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="csl__dss_common_8h.html">csl_dssCommon.h</a></li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/struct_c_s_l___dss_csc_coeff.html b/packages/ti/drv/dss/docs/doxygen/html/struct_c_s_l___dss_csc_coeff.html
--- /dev/null
@@ -0,0 +1,295 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>CSL_DssCscCoeff Struct Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li class="current"><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="files.html"><span>Files</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow2" class="tabs2">
+ <ul class="tablist">
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="functions.html"><span>Data Fields</span></a></li>
+ </ul>
+ </div>
+</div><!-- top -->
+<div class="header">
+ <div class="summary">
+<a href="#pub-attribs">Data Fields</a> </div>
+ <div class="headertitle">
+<div class="title">CSL_DssCscCoeff Struct Reference<div class="ingroups"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html">Top Level CSL FL</a></div></div> </div>
+</div><!--header-->
+<div class="contents">
+
+<p>Structure containing coefficients for Color Space Conversion.
+ <a href="struct_c_s_l___dss_csc_coeff.html#details">More...</a></p>
+
+<p><code>#include <csl_dssTop.h></code></p>
+<table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
+Data Fields</h2></td></tr>
+<tr class="memitem:aaa6a45f2e780f4d62f57fd3c5e3b73ee"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_csc_coeff.html#aaa6a45f2e780f4d62f57fd3c5e3b73ee">cscRange</a></td></tr>
+<tr class="separator:aaa6a45f2e780f4d62f57fd3c5e3b73ee"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ac7b7297b4e02573287df1f9f35d8aca2"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_csc_coeff.html#ac7b7297b4e02573287df1f9f35d8aca2">c00</a></td></tr>
+<tr class="separator:ac7b7297b4e02573287df1f9f35d8aca2"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a5a75499dfeeb44b76d415bb9bbe98d8d"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_csc_coeff.html#a5a75499dfeeb44b76d415bb9bbe98d8d">c01</a></td></tr>
+<tr class="separator:a5a75499dfeeb44b76d415bb9bbe98d8d"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a19b693b93d0cf75adb2fb68117695d8a"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_csc_coeff.html#a19b693b93d0cf75adb2fb68117695d8a">c02</a></td></tr>
+<tr class="separator:a19b693b93d0cf75adb2fb68117695d8a"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:aa669cc1212525291737f9bc74d0153ce"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_csc_coeff.html#aa669cc1212525291737f9bc74d0153ce">c10</a></td></tr>
+<tr class="separator:aa669cc1212525291737f9bc74d0153ce"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a83ecbca550770735501789f7afcdf58e"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_csc_coeff.html#a83ecbca550770735501789f7afcdf58e">c11</a></td></tr>
+<tr class="separator:a83ecbca550770735501789f7afcdf58e"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a8e8879c108c96cfb3ddaddc04920e09e"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_csc_coeff.html#a8e8879c108c96cfb3ddaddc04920e09e">c12</a></td></tr>
+<tr class="separator:a8e8879c108c96cfb3ddaddc04920e09e"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ae191fedd2933af25a14134968c36cc4e"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_csc_coeff.html#ae191fedd2933af25a14134968c36cc4e">c20</a></td></tr>
+<tr class="separator:ae191fedd2933af25a14134968c36cc4e"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a254195b0c504a070d1f3965b252a11f3"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_csc_coeff.html#a254195b0c504a070d1f3965b252a11f3">c21</a></td></tr>
+<tr class="separator:a254195b0c504a070d1f3965b252a11f3"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ab4f1a6d7535f7b7c3cd9318a8d4147a4"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_csc_coeff.html#ab4f1a6d7535f7b7c3cd9318a8d4147a4">c22</a></td></tr>
+<tr class="separator:ab4f1a6d7535f7b7c3cd9318a8d4147a4"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ac7220e1ec74749d1223be58334fec6bd"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_csc_coeff.html#ac7220e1ec74749d1223be58334fec6bd">preOffset1</a></td></tr>
+<tr class="separator:ac7220e1ec74749d1223be58334fec6bd"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ad68c0c52100a22abdc7e7f32726d9070"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_csc_coeff.html#ad68c0c52100a22abdc7e7f32726d9070">preOffset2</a></td></tr>
+<tr class="separator:ad68c0c52100a22abdc7e7f32726d9070"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a347ff46868f7d6adfd877071a9fcc899"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_csc_coeff.html#a347ff46868f7d6adfd877071a9fcc899">preOffset3</a></td></tr>
+<tr class="separator:a347ff46868f7d6adfd877071a9fcc899"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ab0784bdfae37f766f4ad327bc5e597c6"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_csc_coeff.html#ab0784bdfae37f766f4ad327bc5e597c6">postOffset1</a></td></tr>
+<tr class="separator:ab0784bdfae37f766f4ad327bc5e597c6"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:aead82d70ab275933b820a7e87abb05c8"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_csc_coeff.html#aead82d70ab275933b820a7e87abb05c8">postOffset2</a></td></tr>
+<tr class="separator:aead82d70ab275933b820a7e87abb05c8"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a3877e738385c127011a7c14b00c38ddf"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_csc_coeff.html#a3877e738385c127011a7c14b00c38ddf">postOffset3</a></td></tr>
+<tr class="separator:a3877e738385c127011a7c14b00c38ddf"><td class="memSeparator" colspan="2"> </td></tr>
+</table>
+<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
+<div class="textblock"><p>Structure containing coefficients for Color Space Conversion. </p>
+</div><h2 class="groupheader">Field Documentation</h2>
+<a class="anchor" id="ac7b7297b4e02573287df1f9f35d8aca2"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">int32_t CSL_DssCscCoeff::c00</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>C00 Coefficient Encoded signed value </p>
+
+</div>
+</div>
+<a class="anchor" id="a5a75499dfeeb44b76d415bb9bbe98d8d"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">int32_t CSL_DssCscCoeff::c01</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>C01 Coefficient Encoded signed value </p>
+
+</div>
+</div>
+<a class="anchor" id="a19b693b93d0cf75adb2fb68117695d8a"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">int32_t CSL_DssCscCoeff::c02</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>C02 Coefficient Encoded signed value </p>
+
+</div>
+</div>
+<a class="anchor" id="aa669cc1212525291737f9bc74d0153ce"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">int32_t CSL_DssCscCoeff::c10</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>C10 Coefficient Encoded signed value </p>
+
+</div>
+</div>
+<a class="anchor" id="a83ecbca550770735501789f7afcdf58e"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">int32_t CSL_DssCscCoeff::c11</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>C11 Coefficient Encoded signed value </p>
+
+</div>
+</div>
+<a class="anchor" id="a8e8879c108c96cfb3ddaddc04920e09e"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">int32_t CSL_DssCscCoeff::c12</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>C12 Coefficient Encoded signed value </p>
+
+</div>
+</div>
+<a class="anchor" id="ae191fedd2933af25a14134968c36cc4e"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">int32_t CSL_DssCscCoeff::c20</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>C20 Coefficient Encoded signed value </p>
+
+</div>
+</div>
+<a class="anchor" id="a254195b0c504a070d1f3965b252a11f3"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">int32_t CSL_DssCscCoeff::c21</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>C21 Coefficient Encoded signed value </p>
+
+</div>
+</div>
+<a class="anchor" id="ab4f1a6d7535f7b7c3cd9318a8d4147a4"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">int32_t CSL_DssCscCoeff::c22</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>C22 Coefficient Encoded signed value </p>
+
+</div>
+</div>
+<a class="anchor" id="aaa6a45f2e780f4d62f57fd3c5e3b73ee"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t CSL_DssCscCoeff::cscRange</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Color Space Conversion range setting For valid values see <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#CSL_DssCscRange">CSL_DssCscRange</a> </p>
+
+</div>
+</div>
+<a class="anchor" id="ab0784bdfae37f766f4ad327bc5e597c6"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">int32_t CSL_DssCscCoeff::postOffset1</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Post Offset1 Coefficient Encoded signed value </p>
+
+</div>
+</div>
+<a class="anchor" id="aead82d70ab275933b820a7e87abb05c8"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">int32_t CSL_DssCscCoeff::postOffset2</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Post Offset2 Coefficient Encoded signed value </p>
+
+</div>
+</div>
+<a class="anchor" id="a3877e738385c127011a7c14b00c38ddf"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">int32_t CSL_DssCscCoeff::postOffset3</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Post Offset3 Coefficient Encoded signed value </p>
+
+</div>
+</div>
+<a class="anchor" id="ac7220e1ec74749d1223be58334fec6bd"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">int32_t CSL_DssCscCoeff::preOffset1</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Pre Offset1 Coefficient Encoded signed value </p>
+
+</div>
+</div>
+<a class="anchor" id="ad68c0c52100a22abdc7e7f32726d9070"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">int32_t CSL_DssCscCoeff::preOffset2</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Pre Offset2 Coefficient Encoded signed value </p>
+
+</div>
+</div>
+<a class="anchor" id="a347ff46868f7d6adfd877071a9fcc899"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">int32_t CSL_DssCscCoeff::preOffset3</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Pre Offset3 Coefficient Encoded signed value </p>
+
+</div>
+</div>
+<hr/>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="csl__dss_top_8h.html">csl_dssTop.h</a></li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/struct_c_s_l___dss_global_m_flag_cfg.html b/packages/ti/drv/dss/docs/doxygen/html/struct_c_s_l___dss_global_m_flag_cfg.html
--- /dev/null
@@ -0,0 +1,85 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>CSL_DssGlobalMFlagCfg Struct Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li class="current"><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="files.html"><span>Files</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow2" class="tabs2">
+ <ul class="tablist">
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="functions.html"><span>Data Fields</span></a></li>
+ </ul>
+ </div>
+</div><!-- top -->
+<div class="header">
+ <div class="summary">
+<a href="#pub-attribs">Data Fields</a> </div>
+ <div class="headertitle">
+<div class="title">CSL_DssGlobalMFlagCfg Struct Reference<div class="ingroups"><a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html">DSS Common CSL FL</a></div></div> </div>
+</div><!--header-->
+<div class="contents">
+
+<p>DSS Global MFLAG Config parameters.
+ <a href="struct_c_s_l___dss_global_m_flag_cfg.html#details">More...</a></p>
+
+<p><code>#include <csl_dssCommon.h></code></p>
+<table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
+Data Fields</h2></td></tr>
+<tr class="memitem:ab59aea1dc07f654fc07e0710421923f2"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_global_m_flag_cfg.html#ab59aea1dc07f654fc07e0710421923f2">globalMflagStart</a></td></tr>
+<tr class="separator:ab59aea1dc07f654fc07e0710421923f2"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a476453835fc320b9268d47a22b23dbc8"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_global_m_flag_cfg.html#a476453835fc320b9268d47a22b23dbc8">globalMflagCtrl</a></td></tr>
+<tr class="separator:a476453835fc320b9268d47a22b23dbc8"><td class="memSeparator" colspan="2"> </td></tr>
+</table>
+<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
+<div class="textblock"><p>DSS Global MFLAG Config parameters. </p>
+</div><h2 class="groupheader">Field Documentation</h2>
+<a class="anchor" id="a476453835fc320b9268d47a22b23dbc8"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t CSL_DssGlobalMFlagCfg::globalMflagCtrl</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Mflag Control Signal. Refer <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#CSL_DssMflagCtrl">CSL_DssMflagCtrl</a> for values </p>
+
+</div>
+</div>
+<a class="anchor" id="ab59aea1dc07f654fc07e0710421923f2"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t CSL_DssGlobalMFlagCfg::globalMflagStart</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Mflag start for DMA master port, used to drive mflag signal when DMA buffer is empty at the beginning of pipeline. Refer <a class="el" href="group___c_s_l___d_s_s_c_o_m_m_o_n.html#CSL_DssMflagStartMode">CSL_DssMflagStartMode</a> for values </p>
+
+</div>
+</div>
+<hr/>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="csl__dss_common_8h.html">csl_dssCommon.h</a></li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/struct_c_s_l___dss_overlay_cfg.html b/packages/ti/drv/dss/docs/doxygen/html/struct_c_s_l___dss_overlay_cfg.html
--- /dev/null
@@ -0,0 +1,130 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>CSL_DssOverlayCfg Struct Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li class="current"><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="files.html"><span>Files</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow2" class="tabs2">
+ <ul class="tablist">
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="functions.html"><span>Data Fields</span></a></li>
+ </ul>
+ </div>
+</div><!-- top -->
+<div class="header">
+ <div class="summary">
+<a href="#pub-attribs">Data Fields</a> </div>
+ <div class="headertitle">
+<div class="title">CSL_DssOverlayCfg Struct Reference<div class="ingroups"><a class="el" href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html">DSS Overlay CSL FL</a></div></div> </div>
+</div><!--header-->
+<div class="contents">
+
+<p>Configuration for DSS Overlay.
+ <a href="struct_c_s_l___dss_overlay_cfg.html#details">More...</a></p>
+
+<p><code>#include <csl_dssOverlay.h></code></p>
+<table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
+Data Fields</h2></td></tr>
+<tr class="memitem:aaeb04d69fcf39faa7ac2e8dff0dd57be"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_overlay_cfg.html#aaeb04d69fcf39faa7ac2e8dff0dd57be">colorKeyEnable</a></td></tr>
+<tr class="separator:aaeb04d69fcf39faa7ac2e8dff0dd57be"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a04994324fc3e3290d5a2384b1643abc4"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_overlay_cfg.html#a04994324fc3e3290d5a2384b1643abc4">colorKeySel</a></td></tr>
+<tr class="separator:a04994324fc3e3290d5a2384b1643abc4"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a25f45603756892cc7bc3f43d840d94bb"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_overlay_cfg.html#a25f45603756892cc7bc3f43d840d94bb">transColorKeyMin</a></td></tr>
+<tr class="separator:a25f45603756892cc7bc3f43d840d94bb"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a30d4c1ba3e4ac96fd6618a450b95ee37"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_overlay_cfg.html#a30d4c1ba3e4ac96fd6618a450b95ee37">transColorKeyMax</a></td></tr>
+<tr class="separator:a30d4c1ba3e4ac96fd6618a450b95ee37"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a6cd0a80d721ebd8316233c7d1a0eff8a"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_overlay_cfg.html#a6cd0a80d721ebd8316233c7d1a0eff8a">backGroundColor</a></td></tr>
+<tr class="separator:a6cd0a80d721ebd8316233c7d1a0eff8a"><td class="memSeparator" colspan="2"> </td></tr>
+</table>
+<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
+<div class="textblock"><p>Configuration for DSS Overlay. </p>
+</div><h2 class="groupheader">Field Documentation</h2>
+<a class="anchor" id="a6cd0a80d721ebd8316233c7d1a0eff8a"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t CSL_DssOverlayCfg::backGroundColor</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Background color value in 24 bit RGB format 31--—24 23--—16 15---—8 7----—0 Unused R G B </p>
+
+</div>
+</div>
+<a class="anchor" id="aaeb04d69fcf39faa7ac2e8dff0dd57be"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t CSL_DssOverlayCfg::colorKeyEnable</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Enable Transparency Color Key FALSE: Disable Color Key TRUE: Enable Color Key </p>
+
+</div>
+</div>
+<a class="anchor" id="a04994324fc3e3290d5a2384b1643abc4"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t CSL_DssOverlayCfg::colorKeySel</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Transparency Color Key Selection. For valid values see <a class="el" href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#CSL_DssOverlayTransColor">CSL_DssOverlayTransColor</a> </p>
+
+</div>
+</div>
+<a class="anchor" id="a30d4c1ba3e4ac96fd6618a450b95ee37"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t CSL_DssOverlayCfg::transColorKeyMax</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Maximum Transparency color key value in 24 bit RGB format 31--—24 23--—16 15---—8 7----—0 Unused R G B </p>
+
+</div>
+</div>
+<a class="anchor" id="a25f45603756892cc7bc3f43d840d94bb"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t CSL_DssOverlayCfg::transColorKeyMin</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Minimum Transparency color key value in 24 bit RGB format 31--—24 23--—16 15---—8 7----—0 Unused R G B </p>
+
+</div>
+</div>
+<hr/>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="csl__dss_overlay_8h.html">csl_dssOverlay.h</a></li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/struct_c_s_l___dss_overlay_layer_cfg.html b/packages/ti/drv/dss/docs/doxygen/html/struct_c_s_l___dss_overlay_layer_cfg.html
--- /dev/null
@@ -0,0 +1,100 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>CSL_DssOverlayLayerCfg Struct Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li class="current"><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="files.html"><span>Files</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow2" class="tabs2">
+ <ul class="tablist">
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="functions.html"><span>Data Fields</span></a></li>
+ </ul>
+ </div>
+</div><!-- top -->
+<div class="header">
+ <div class="summary">
+<a href="#pub-attribs">Data Fields</a> </div>
+ <div class="headertitle">
+<div class="title">CSL_DssOverlayLayerCfg Struct Reference<div class="ingroups"><a class="el" href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html">DSS Overlay CSL FL</a></div></div> </div>
+</div><!--header-->
+<div class="contents">
+
+<p>Configuration for selecting overlay input layers.
+ <a href="struct_c_s_l___dss_overlay_layer_cfg.html#details">More...</a></p>
+
+<p><code>#include <csl_dssOverlay.h></code></p>
+<table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
+Data Fields</h2></td></tr>
+<tr class="memitem:a83dcc8dccd51c4dd38f5c8de44226596"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_overlay_layer_cfg.html#a83dcc8dccd51c4dd38f5c8de44226596">layerEnable</a></td></tr>
+<tr class="separator:a83dcc8dccd51c4dd38f5c8de44226596"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a79b077926e883044363d2fe27a986196"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_overlay_layer_cfg.html#a79b077926e883044363d2fe27a986196">layerNum</a></td></tr>
+<tr class="separator:a79b077926e883044363d2fe27a986196"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a9fa2884d228ae00ba4694fcb04c76bf9"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_overlay_layer_cfg.html#a9fa2884d228ae00ba4694fcb04c76bf9">inputPipe</a></td></tr>
+<tr class="separator:a9fa2884d228ae00ba4694fcb04c76bf9"><td class="memSeparator" colspan="2"> </td></tr>
+</table>
+<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
+<div class="textblock"><p>Configuration for selecting overlay input layers. </p>
+</div><h2 class="groupheader">Field Documentation</h2>
+<a class="anchor" id="a9fa2884d228ae00ba4694fcb04c76bf9"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t CSL_DssOverlayLayerCfg::inputPipe</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Video Pipe Id connected to Overlay. For valid values see <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#CSL_DssVidPipeId">CSL_DssVidPipeId</a> </p>
+
+</div>
+</div>
+<a class="anchor" id="a83dcc8dccd51c4dd38f5c8de44226596"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t CSL_DssOverlayLayerCfg::layerEnable</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Overlay Layer Enable FALSE: Disable Overlay Layer TRUE: Enable Overlay Layer </p>
+
+</div>
+</div>
+<a class="anchor" id="a79b077926e883044363d2fe27a986196"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t CSL_DssOverlayLayerCfg::layerNum</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Overlay Layer Number. Refer <a class="el" href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#CSL_DssOverlayLayerNum">CSL_DssOverlayLayerNum</a> for valid values </p>
+
+</div>
+</div>
+<hr/>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="csl__dss_overlay_8h.html">csl_dssOverlay.h</a></li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/struct_c_s_l___dss_overlay_pipe_pos_cfg.html b/packages/ti/drv/dss/docs/doxygen/html/struct_c_s_l___dss_overlay_pipe_pos_cfg.html
--- /dev/null
@@ -0,0 +1,76 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>CSL_DssOverlayPipePosCfg Struct Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li class="current"><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="files.html"><span>Files</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow2" class="tabs2">
+ <ul class="tablist">
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="functions.html"><span>Data Fields</span></a></li>
+ </ul>
+ </div>
+</div><!-- top -->
+<div class="header">
+ <div class="summary">
+<a href="#pub-attribs">Data Fields</a> </div>
+ <div class="headertitle">
+<div class="title">CSL_DssOverlayPipePosCfg Struct Reference<div class="ingroups"><a class="el" href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html">DSS Overlay CSL FL</a></div></div> </div>
+</div><!--header-->
+<div class="contents">
+
+<p>Video Pipe Position Configuration in Overlay.
+ <a href="struct_c_s_l___dss_overlay_pipe_pos_cfg.html#details">More...</a></p>
+
+<p><code>#include <csl_dssOverlay.h></code></p>
+<table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
+Data Fields</h2></td></tr>
+<tr class="memitem:af609b8a3d9d62d0dd1ac4756c3add323"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_fvid2___pos_config.html">Fvid2_PosConfig</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_overlay_pipe_pos_cfg.html#af609b8a3d9d62d0dd1ac4756c3add323">layerPos</a></td></tr>
+<tr class="separator:af609b8a3d9d62d0dd1ac4756c3add323"><td class="memSeparator" colspan="2"> </td></tr>
+</table>
+<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
+<div class="textblock"><p>Video Pipe Position Configuration in Overlay. </p>
+</div><h2 class="groupheader">Field Documentation</h2>
+<a class="anchor" id="af609b8a3d9d62d0dd1ac4756c3add323"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname"><a class="el" href="struct_fvid2___pos_config.html">Fvid2_PosConfig</a> CSL_DssOverlayPipePosCfg::layerPos</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Position of the layer described using <a class="el" href="struct_fvid2___pos_config.html" title="Structure containing position configuration - used in VCOMP and CIG. ">Fvid2_PosConfig</a></p>
+<p><b>startX</b>:<br/>
+ X position of the layer The first pixel on the left of the screen has the X-position 0 <br/>
+</p>
+<p><b>startY</b>:<br/>
+ Y position of the layer The line at the top has the Y-position 0 <br/>
+ </p>
+
+</div>
+</div>
+<hr/>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="csl__dss_overlay_8h.html">csl_dssOverlay.h</a></li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/struct_c_s_l___dss_safety_chk_cfg.html b/packages/ti/drv/dss/docs/doxygen/html/struct_c_s_l___dss_safety_chk_cfg.html
--- /dev/null
@@ -0,0 +1,172 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>CSL_DssSafetyChkCfg Struct Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
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+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
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+ </ul>
+ </div>
+</div><!-- top -->
+<div class="header">
+ <div class="summary">
+<a href="#pub-attribs">Data Fields</a> </div>
+ <div class="headertitle">
+<div class="title">CSL_DssSafetyChkCfg Struct Reference<div class="ingroups"><a class="el" href="group___c_s_l___d_s_s_t_o_p.html">Top Level CSL FL</a></div></div> </div>
+</div><!--header-->
+<div class="contents">
+
+<p>Configuration for doing safety checks.
+ <a href="struct_c_s_l___dss_safety_chk_cfg.html#details">More...</a></p>
+
+<p><code>#include <csl_dssTop.h></code></p>
+<table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
+Data Fields</h2></td></tr>
+<tr class="memitem:aa0b0d70dc3629906f279027fe788d52f"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_safety_chk_cfg.html#aa0b0d70dc3629906f279027fe788d52f">safetyChkEnable</a></td></tr>
+<tr class="separator:aa0b0d70dc3629906f279027fe788d52f"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ae4777be78384a09ac1e76eaa5ef925f6"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_safety_chk_cfg.html#ae4777be78384a09ac1e76eaa5ef925f6">safetyChkMode</a></td></tr>
+<tr class="separator:ae4777be78384a09ac1e76eaa5ef925f6"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a125d8cffdb194601754cf97d2a56c00b"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_safety_chk_cfg.html#a125d8cffdb194601754cf97d2a56c00b">seedSelectEnable</a></td></tr>
+<tr class="separator:a125d8cffdb194601754cf97d2a56c00b"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a2ab0df15747d286392ad903768bd82c1"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_safety_chk_cfg.html#a2ab0df15747d286392ad903768bd82c1">thresholdValue</a></td></tr>
+<tr class="separator:a2ab0df15747d286392ad903768bd82c1"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a6ed2ecbafc577cc70efdb2ba75f93142"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_safety_chk_cfg.html#a6ed2ecbafc577cc70efdb2ba75f93142">frameSkip</a></td></tr>
+<tr class="separator:a6ed2ecbafc577cc70efdb2ba75f93142"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:acd23c9535ba779805df7c92946522de1"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_fvid2___pos_config.html">Fvid2_PosConfig</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_safety_chk_cfg.html#acd23c9535ba779805df7c92946522de1">regionPos</a></td></tr>
+<tr class="separator:acd23c9535ba779805df7c92946522de1"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:adfe6989e81985735685e9dc1a3cc2fc3"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_fvid2___size_config.html">Fvid2_SizeConfig</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_safety_chk_cfg.html#adfe6989e81985735685e9dc1a3cc2fc3">regionSize</a></td></tr>
+<tr class="separator:adfe6989e81985735685e9dc1a3cc2fc3"><td class="memSeparator" colspan="2"> </td></tr>
+</table>
+<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
+<div class="textblock"><p>Configuration for doing safety checks. </p>
+</div><h2 class="groupheader">Field Documentation</h2>
+<a class="anchor" id="a6ed2ecbafc577cc70efdb2ba75f93142"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t CSL_DssSafetyChkCfg::frameSkip</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Indicates which frames to be skipped while doing safety checks For valid values see <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#CSL_DssSafetyChkFrameSkip">CSL_DssSafetyChkFrameSkip</a> </p>
+
+</div>
+</div>
+<a class="anchor" id="acd23c9535ba779805df7c92946522de1"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname"><a class="el" href="struct_fvid2___pos_config.html">Fvid2_PosConfig</a> CSL_DssSafetyChkCfg::regionPos</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Position of the safety region described using <a class="el" href="struct_fvid2___pos_config.html" title="Structure containing position configuration - used in VCOMP and CIG. ">Fvid2_PosConfig</a></p>
+<p><b>startX</b>:<br/>
+ X position of the layer The first pixel on the left of the screen has the X-position 0 <br/>
+</p>
+<p><b>startY</b>:<br/>
+ Y position of the layer The first pixel at the top has the Y-position 0 <br/>
+ </p>
+
+</div>
+</div>
+<a class="anchor" id="adfe6989e81985735685e9dc1a3cc2fc3"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname"><a class="el" href="struct_fvid2___size_config.html">Fvid2_SizeConfig</a> CSL_DssSafetyChkCfg::regionSize</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Size of the safety region described using <a class="el" href="struct_fvid2___size_config.html" title="Structure containing size configuration. ">Fvid2_SizeConfig</a></p>
+<p><b>width</b>:<br/>
+ Width of the safety region One pixel wide region has value of 0 <br/>
+</p>
+<p><b>height</b>:<br/>
+ Height of the safety region One pixel height region has value of 0 <br/>
+ </p>
+
+</div>
+</div>
+<a class="anchor" id="aa0b0d70dc3629906f279027fe788d52f"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t CSL_DssSafetyChkCfg::safetyChkEnable</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Safety check Enable for the region FALSE: Disable Safety Check TRUE: Enable Safety Check </p>
+
+</div>
+</div>
+<a class="anchor" id="ae4777be78384a09ac1e76eaa5ef925f6"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t CSL_DssSafetyChkCfg::safetyChkMode</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Mode of operation of the safety check module For valid values see <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#CSL_DssSafetyChkMode">CSL_DssSafetyChkMode</a> </p>
+
+</div>
+</div>
+<a class="anchor" id="a125d8cffdb194601754cf97d2a56c00b"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t CSL_DssSafetyChkCfg::seedSelectEnable</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Initial seed selection control FALSE: Initial seed is always 0xFFFFFFFF TRUE: Initial seed is defined by SAFETY_LFSR_SEED </p>
+
+</div>
+</div>
+<a class="anchor" id="a2ab0df15747d286392ad903768bd82c1"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t CSL_DssSafetyChkCfg::thresholdValue</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Allowed maximum number of frames with the same frame signature. When the freeze frame counter reaches thresholdValue+1, a freeze frame detection will occur </p>
+
+</div>
+</div>
+<hr/>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="csl__dss_top_8h.html">csl_dssTop.h</a></li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/struct_c_s_l___dss_vid_pipe_alpha_cfg.html b/packages/ti/drv/dss/docs/doxygen/html/struct_c_s_l___dss_vid_pipe_alpha_cfg.html
--- /dev/null
@@ -0,0 +1,85 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>CSL_DssVidPipeAlphaCfg Struct Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li class="current"><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="files.html"><span>Files</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow2" class="tabs2">
+ <ul class="tablist">
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="functions.html"><span>Data Fields</span></a></li>
+ </ul>
+ </div>
+</div><!-- top -->
+<div class="header">
+ <div class="summary">
+<a href="#pub-attribs">Data Fields</a> </div>
+ <div class="headertitle">
+<div class="title">CSL_DssVidPipeAlphaCfg Struct Reference<div class="ingroups"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html">DSS Video Pipe CSL FL</a></div></div> </div>
+</div><!--header-->
+<div class="contents">
+
+<p>DSS Video Pipe Alpha Config parameters.
+ <a href="struct_c_s_l___dss_vid_pipe_alpha_cfg.html#details">More...</a></p>
+
+<p><code>#include <csl_dssVideoPipe.h></code></p>
+<table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
+Data Fields</h2></td></tr>
+<tr class="memitem:af1657cd739f1bde94ae85e504c3e5af6"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_vid_pipe_alpha_cfg.html#af1657cd739f1bde94ae85e504c3e5af6">globalAlpha</a></td></tr>
+<tr class="separator:af1657cd739f1bde94ae85e504c3e5af6"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a592febc9d395769c45a294b1b2725136"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_vid_pipe_alpha_cfg.html#a592febc9d395769c45a294b1b2725136">preMultiplyAlpha</a></td></tr>
+<tr class="separator:a592febc9d395769c45a294b1b2725136"><td class="memSeparator" colspan="2"> </td></tr>
+</table>
+<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
+<div class="textblock"><p>DSS Video Pipe Alpha Config parameters. </p>
+</div><h2 class="groupheader">Field Documentation</h2>
+<a class="anchor" id="af1657cd739f1bde94ae85e504c3e5af6"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t CSL_DssVidPipeAlphaCfg::globalAlpha</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Global alpha value from 0 to 255. 0 corresponds to fully transparent and 255 to fully opaque </p>
+
+</div>
+</div>
+<a class="anchor" id="a592febc9d395769c45a294b1b2725136"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t CSL_DssVidPipeAlphaCfg::preMultiplyAlpha</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>The field configures the pipe to process incoming data as pre multiplied alpha data. FALSE: Non pre multiplied alpha data TRUE: Pre multiplied alpha data </p>
+
+</div>
+</div>
+<hr/>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="csl__dss_video_pipe_8h.html">csl_dssVideoPipe.h</a></li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/struct_c_s_l___dss_vid_pipe_cfg.html b/packages/ti/drv/dss/docs/doxygen/html/struct_c_s_l___dss_vid_pipe_cfg.html
--- /dev/null
@@ -0,0 +1,308 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>CSL_DssVidPipeCfg Struct Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li class="current"><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="files.html"><span>Files</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow2" class="tabs2">
+ <ul class="tablist">
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="functions.html"><span>Data Fields</span></a></li>
+ </ul>
+ </div>
+</div><!-- top -->
+<div class="header">
+ <div class="summary">
+<a href="#pub-attribs">Data Fields</a> </div>
+ <div class="headertitle">
+<div class="title">CSL_DssVidPipeCfg Struct Reference<div class="ingroups"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html">DSS Video Pipe CSL FL</a></div></div> </div>
+</div><!--header-->
+<div class="contents">
+
+<p>Configuration for DSS Video Pipe.
+ <a href="struct_c_s_l___dss_vid_pipe_cfg.html#details">More...</a></p>
+
+<p><code>#include <csl_dssVideoPipe.h></code></p>
+<table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
+Data Fields</h2></td></tr>
+<tr class="memitem:a85e0ba7c97b71003b61e862ebc3fbe40"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_vid_pipe_cfg.html#a85e0ba7c97b71003b61e862ebc3fbe40">pipeType</a></td></tr>
+<tr class="separator:a85e0ba7c97b71003b61e862ebc3fbe40"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ad746f01b386f5f8b836ae76193641be0"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_fvid2___format.html">Fvid2_Format</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_vid_pipe_cfg.html#ad746f01b386f5f8b836ae76193641be0">inFmt</a></td></tr>
+<tr class="separator:ad746f01b386f5f8b836ae76193641be0"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a026189ab1fe6ad7ab75606a70cbc6136"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_vid_pipe_cfg.html#a026189ab1fe6ad7ab75606a70cbc6136">pixelInc</a></td></tr>
+<tr class="separator:a026189ab1fe6ad7ab75606a70cbc6136"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a3926c260e814c53179d80058a595935c"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_vid_pipe_cfg.html#a3926c260e814c53179d80058a595935c">yuvAlign</a></td></tr>
+<tr class="separator:a3926c260e814c53179d80058a595935c"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:aee9fafc3374aa44e5d8aa0ade330de5c"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_vid_pipe_cfg.html#aee9fafc3374aa44e5d8aa0ade330de5c">outWidth</a></td></tr>
+<tr class="separator:aee9fafc3374aa44e5d8aa0ade330de5c"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a1d3a19f6cf680aba0505a2abd670140e"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_vid_pipe_cfg.html#a1d3a19f6cf680aba0505a2abd670140e">outHeight</a></td></tr>
+<tr class="separator:a1d3a19f6cf680aba0505a2abd670140e"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a558ff6d8e56438ce6f4e573a4e28cbc5"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_vid_pipe_cfg.html#a558ff6d8e56438ce6f4e573a4e28cbc5">scEnable</a></td></tr>
+<tr class="separator:a558ff6d8e56438ce6f4e573a4e28cbc5"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a69fdfed089bd4ee2daea72c8e40a98f2"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_vid_pipe_cfg.html#a69fdfed089bd4ee2daea72c8e40a98f2">cscRange</a></td></tr>
+<tr class="separator:a69fdfed089bd4ee2daea72c8e40a98f2"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:abebbaaf4c35c0d96cdcc9fdc9300de28"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_vid_pipe_cfg.html#abebbaaf4c35c0d96cdcc9fdc9300de28">flipType</a></td></tr>
+<tr class="separator:abebbaaf4c35c0d96cdcc9fdc9300de28"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a7ce9ca51a30b95aa4542c412a06f3fe8"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_vid_pipe_cfg.html#a7ce9ca51a30b95aa4542c412a06f3fe8">clutdata</a> [<a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gac8a30c5680379b12128e75859e9f2312">CSL_DSS_NUM_LUT_ENTRIES</a>]</td></tr>
+<tr class="separator:a7ce9ca51a30b95aa4542c412a06f3fe8"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a3c4e8eb4baaf50467b94c025b7f9831f"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_vid_pipe_cfg.html#a3c4e8eb4baaf50467b94c025b7f9831f">nibblemodeEnable</a></td></tr>
+<tr class="separator:a3c4e8eb4baaf50467b94c025b7f9831f"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a5e9c6107d03fb837bc74a71538c5ed3e"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_vid_pipe_cfg.html#a5e9c6107d03fb837bc74a71538c5ed3e">gammaEnable</a></td></tr>
+<tr class="separator:a5e9c6107d03fb837bc74a71538c5ed3e"><td class="memSeparator" colspan="2"> </td></tr>
+</table>
+<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
+<div class="textblock"><p>Configuration for DSS Video Pipe. </p>
+</div><h2 class="groupheader">Field Documentation</h2>
+<a class="anchor" id="a7ce9ca51a30b95aa4542c412a06f3fe8"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t CSL_DssVidPipeCfg::clutdata[<a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gac8a30c5680379b12128e75859e9f2312">CSL_DSS_NUM_LUT_ENTRIES</a>]</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Color Look-up Table for the bitmap formats </p>
+
+</div>
+</div>
+<a class="anchor" id="a69fdfed089bd4ee2daea72c8e40a98f2"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t CSL_DssVidPipeCfg::cscRange</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Color Space Conversion range setting For valid values see <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#CSL_DssCscRange">CSL_DssCscRange</a> </p>
+
+</div>
+</div>
+<a class="anchor" id="abebbaaf4c35c0d96cdcc9fdc9300de28"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t CSL_DssVidPipeCfg::flipType</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Video Buffer Flip Type For valid values see <a class="el" href="csl__fvid2__data_types_8h.html#Fvid2_FlipType">Fvid2_FlipType</a> </p>
+
+</div>
+</div>
+<a class="anchor" id="a5e9c6107d03fb837bc74a71538c5ed3e"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t CSL_DssVidPipeCfg::gammaEnable</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Inverse Gamma Support (using CLUT) FALSE: Gamma support is disabled TRUE: Gamma support is enabled </p>
+
+</div>
+</div>
+<a class="anchor" id="ad746f01b386f5f8b836ae76193641be0"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname"><a class="el" href="struct_fvid2___format.html">Fvid2_Format</a> CSL_DssVidPipeCfg::inFmt</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Input format described using FVID2 frame format <a class="el" href="struct_fvid2___format.html" title="FVID2 video buffer format specification. ">Fvid2_Format</a></p>
+<p><b>width</b>:<br/>
+ Input width, in pixels This represents the input width to be programmed <br/>
+</p>
+<p><b>height</b>:<br/>
+ Input height, in lines This represents the input height to be programmed <br/>
+</p>
+<p><b>pitch</b>:<br/>
+ Pitch in bytes between two lines Pitch can be specified separately for every plane <br/>
+</p>
+<p><b>dataFormat</b>:<br/>
+ Input Data format, valid options are<br/>
+ FVID2_DF_YUV422I_UYVY,<br/>
+ FVID2_DF_YUV422I_YUYV,<br/>
+ FVID2_DF_YUV420SP_UV,<br/>
+ FVID2_DF_XBGR64_16161616,<br/>
+ FVID2_DF_BGRX64_16161616,<br/>
+ FVID2_DF_RGBX32_1010102,<br/>
+ FVID2_DF_BGRX32_1010102,<br/>
+ FVID2_DF_XRGB32_8888,<br/>
+ FVID2_DF_XBGR24_8888,<br/>
+ FVID2_DF_BGRX32_8888,<br/>
+ FVID2_DF_BGRX24_8888,<br/>
+ FVID2_DF_BGRX16_1555,<br/>
+ FVID2_DF_BGRX16_5551,<br/>
+ FVID2_DF_XBGR_4444,<br/>
+ FVID2_DF_RGBX16_4444,<br/>
+ FVID2_DF_BGRX_4444,<br/>
+ FVID2_DF_RGB16_565_A8,<br/>
+ FVID2_DF_BGR16_565_A8,<br/>
+ FVID2_DF_BITMAP8,<br/>
+ FVID2_DF_BITMAP4,<br/>
+ FVID2_DF_BITMAP2,<br/>
+ FVID2_DF_BITMAP1,<br/>
+ FVID2_DF_ABGR64_16161616,<br/>
+ FVID2_DF_BGRA64_16161616,<br/>
+ FVID2_DF_RGBA32_1010102,<br/>
+ FVID2_DF_BGRA32_1010102,<br/>
+ FVID2_DF_RGB24_888,<br/>
+ FVID2_DF_BGR24_888,<br/>
+ FVID2_DF_ARGB32_8888,<br/>
+ FVID2_DF_ABGR32_8888,<br/>
+ FVID2_DF_RGBA32_8888,<br/>
+ FVID2_DF_BGRA32_8888,<br/>
+ FVID2_DF_BGRA16_1555,<br/>
+ FVID2_DF_BGRA16_5551,<br/>
+ FVID2_DF_RGB16_565,<br/>
+ FVID2_DF_BGR16_565,<br/>
+ FVID2_DF_ABGR16_4444,<br/>
+ FVID2_DF_RGBA16_4444,<br/>
+ FVID2_DF_BGRA16_4444<br/>
+ For valid values see <a class="el" href="csl__fvid2__data_types_8h.html#a9f5096b017d15ffecdcc0990fd1b031a" title="YUV 422 Interleaved format - UYVY. ">Fvid2_DataFormat</a><br/>
+</p>
+<p><b>scanFormat</b>:<br/>
+ Scan format, valid options are<br/>
+ FVID2_SF_INTERLACED,<br/>
+ FVID2_SF_PROGRESSIVE<br/>
+ For valid values see <a class="el" href="csl__fvid2__data_types_8h.html#af5dfad95adb11f1220c13a37564b706e" title="Interlaced mode. ">Fvid2_ScanFormat</a><br/>
+</p>
+<p><b>ccsFormat</b>:<br/>
+ Color component storage format, used only in case of YUV data Valid options are<br/>
+ FVID2_CCSF_BITS8_PACKED,<br/>
+ FVID2_CCSF_BITS10_PACKED,<br/>
+ FVID2_CCSF_BITS12_PACKED,<br/>
+ FVID2_CCSF_BITS10_UNPACKED16,<br/>
+ FVID2_CCSF_BITS12_UNPACKED16<br/>
+ For valid values see <a class="el" href="csl__fvid2__data_types_8h.html#a82c2f41780c5f44ed27f7ebadf18a21d" title="1 Bits per Pixel packed. ">Fvid2_ColorCompStorageFmt</a><br/>
+</p>
+<p><b>fieldMerged</b>:<br/>
+ Field Merged Flag for interlaced buffers, valid options are<br/>
+ TRUE,<br/>
+ FALSE<br/>
+</p>
+<p><b>chNum</b>: Not used, set to 0 or default </p>
+
+</div>
+</div>
+<a class="anchor" id="a3c4e8eb4baaf50467b94c025b7f9831f"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t CSL_DssVidPipeCfg::nibblemodeEnable</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Nibble mode for bitmap formats FALSE: Disable Nibble Mode TRUE: Enable Nibble Mode </p>
+
+</div>
+</div>
+<a class="anchor" id="a1d3a19f6cf680aba0505a2abd670140e"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t CSL_DssVidPipeCfg::outHeight</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Vertical Size of picture at output of video pipeline </p>
+
+</div>
+</div>
+<a class="anchor" id="aee9fafc3374aa44e5d8aa0ade330de5c"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t CSL_DssVidPipeCfg::outWidth</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Horizontal Size of picture at output of video pipeline </p>
+
+</div>
+</div>
+<a class="anchor" id="a85e0ba7c97b71003b61e862ebc3fbe40"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t CSL_DssVidPipeCfg::pipeType</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Video Pipe Type. For valid values see <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#CSL_DssVidPipeType">CSL_DssVidPipeType</a> </p>
+
+</div>
+</div>
+<a class="anchor" id="a026189ab1fe6ad7ab75606a70cbc6136"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t CSL_DssVidPipeCfg::pixelInc</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Number of bytes to increment between two pixels. Encoded unsigned value (from 1 to 255) to specify the number of bytes between two pixels in the video buffer. The value 0 is invalid. The value 1 means next pixel. The value 1 + n *(ccsFormat/8) means increment of n pixels. For YUV4:2:0, maximum supported value is 128 </p>
+
+</div>
+</div>
+<a class="anchor" id="a558ff6d8e56438ce6f4e573a4e28cbc5"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t CSL_DssVidPipeCfg::scEnable</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Enable the scaler, valid only if input and output size are different FALSE: Disable Scaler TRUE: Enable Scaler </p>
+
+</div>
+</div>
+<a class="anchor" id="a3926c260e814c53179d80058a595935c"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t CSL_DssVidPipeCfg::yuvAlign</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Alignment for unpacked YUV data For valid values see <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#CSL_DssVidPipeYuvAlign">CSL_DssVidPipeYuvAlign</a> </p>
+
+</div>
+</div>
+<hr/>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="csl__dss_video_pipe_8h.html">csl_dssVideoPipe.h</a></li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/struct_c_s_l___dss_vid_pipe_dma_cfg.html b/packages/ti/drv/dss/docs/doxygen/html/struct_c_s_l___dss_vid_pipe_dma_cfg.html
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+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
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+ </ul>
+ </div>
+</div><!-- top -->
+<div class="header">
+ <div class="summary">
+<a href="#pub-attribs">Data Fields</a> </div>
+ <div class="headertitle">
+<div class="title">CSL_DssVidPipeDmaCfg Struct Reference<div class="ingroups"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html">DSS Video Pipe CSL FL</a></div></div> </div>
+</div><!--header-->
+<div class="contents">
+
+<p>DSS Video Pipe DMA related Config parameters.
+ <a href="struct_c_s_l___dss_vid_pipe_dma_cfg.html#details">More...</a></p>
+
+<p><code>#include <csl_dssVideoPipe.h></code></p>
+<table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
+Data Fields</h2></td></tr>
+<tr class="memitem:af7f5f21d2d1b24e927fcdb3e8f05c945"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_vid_pipe_dma_cfg.html#af7f5f21d2d1b24e927fcdb3e8f05c945">bufPreloadControl</a></td></tr>
+<tr class="separator:af7f5f21d2d1b24e927fcdb3e8f05c945"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a168a8a5323eacf1349b91ff84a28290e"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_vid_pipe_dma_cfg.html#a168a8a5323eacf1349b91ff84a28290e">preloadVal</a></td></tr>
+<tr class="separator:a168a8a5323eacf1349b91ff84a28290e"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ab6f24c128746dac326d90a96a87bb220"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_vid_pipe_dma_cfg.html#ab6f24c128746dac326d90a96a87bb220">bufLowThreshold</a></td></tr>
+<tr class="separator:ab6f24c128746dac326d90a96a87bb220"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ac65a5085dbe2dd974d91cca54b9bfca7"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_vid_pipe_dma_cfg.html#ac65a5085dbe2dd974d91cca54b9bfca7">bufHighThreshold</a></td></tr>
+<tr class="separator:ac65a5085dbe2dd974d91cca54b9bfca7"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a59b2e750c7a9bb8ae5141829f98ccaed"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_vid_pipe_dma_cfg.html#a59b2e750c7a9bb8ae5141829f98ccaed">selfRefreshControl</a></td></tr>
+<tr class="separator:a59b2e750c7a9bb8ae5141829f98ccaed"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:aea2c8225738ca8620eb2af07690db604"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_vid_pipe_dma_cfg.html#aea2c8225738ca8620eb2af07690db604">selfRefreshEnable</a></td></tr>
+<tr class="separator:aea2c8225738ca8620eb2af07690db604"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ae13f5377c727660f54f27d1061a4020b"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_vid_pipe_dma_cfg.html#ae13f5377c727660f54f27d1061a4020b">arbitration</a></td></tr>
+<tr class="separator:ae13f5377c727660f54f27d1061a4020b"><td class="memSeparator" colspan="2"> </td></tr>
+</table>
+<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
+<div class="textblock"><p>DSS Video Pipe DMA related Config parameters. </p>
+</div><h2 class="groupheader">Field Documentation</h2>
+<a class="anchor" id="ae13f5377c727660f54f27d1061a4020b"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t CSL_DssVidPipeDmaCfg::arbitration</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Determines the priority of the video pipeline. For valid values see <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#CSL_DssVidPipePriorityVal">CSL_DssVidPipePriorityVal</a> </p>
+
+</div>
+</div>
+<a class="anchor" id="ac65a5085dbe2dd974d91cca54b9bfca7"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t CSL_DssVidPipeDmaCfg::bufHighThreshold</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Video DMA buffer high threshold. Number of 128 bits defining the Threshold value </p>
+
+</div>
+</div>
+<a class="anchor" id="ab6f24c128746dac326d90a96a87bb220"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t CSL_DssVidPipeDmaCfg::bufLowThreshold</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>DMA buffer low threshold. Number of 128 bits defining the threshold value </p>
+
+</div>
+</div>
+<a class="anchor" id="af7f5f21d2d1b24e927fcdb3e8f05c945"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t CSL_DssVidPipeDmaCfg::bufPreloadControl</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Buffer Preload Value can be either pre fixed(set by HW) or as programmed by SW. For valid values see <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#CSL_DssVidPipePreloadControl">CSL_DssVidPipePreloadControl</a> </p>
+
+</div>
+</div>
+<a class="anchor" id="a168a8a5323eacf1349b91ff84a28290e"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t CSL_DssVidPipeDmaCfg::preloadVal</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Buffer Preload Value when preload is SW controlled </p>
+
+</div>
+</div>
+<a class="anchor" id="a59b2e750c7a9bb8ae5141829f98ccaed"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t CSL_DssVidPipeDmaCfg::selfRefreshControl</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Self Refresh transition from disabled to enabled can be controlled by either SW or HW. For valid values see <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html#CSL_DssVidPipeRefreshControl">CSL_DssVidPipeRefreshControl</a> </p>
+
+</div>
+</div>
+<a class="anchor" id="aea2c8225738ca8620eb2af07690db604"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t CSL_DssVidPipeDmaCfg::selfRefreshEnable</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Enable the self refresh of the video window from its own DMA buffer FALSE: Disable self refresh TRUE: Enable self refresh </p>
+
+</div>
+</div>
+<hr/>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="csl__dss_video_pipe_8h.html">csl_dssVideoPipe.h</a></li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/struct_c_s_l___dss_vid_pipe_luma_cfg.html b/packages/ti/drv/dss/docs/doxygen/html/struct_c_s_l___dss_vid_pipe_luma_cfg.html
--- /dev/null
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+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>CSL_DssVidPipeLumaCfg Struct Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
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+<!-- Generated by Doxygen 1.8.6 -->
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+<a href="#pub-attribs">Data Fields</a> </div>
+ <div class="headertitle">
+<div class="title">CSL_DssVidPipeLumaCfg Struct Reference<div class="ingroups"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html">DSS Video Pipe CSL FL</a></div></div> </div>
+</div><!--header-->
+<div class="contents">
+
+<p>DSS Video Pipe Luma Key Config parameters.
+ <a href="struct_c_s_l___dss_vid_pipe_luma_cfg.html#details">More...</a></p>
+
+<p><code>#include <csl_dssVideoPipe.h></code></p>
+<table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
+Data Fields</h2></td></tr>
+<tr class="memitem:a963fa503522975f7e78da0e7085ac209"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_vid_pipe_luma_cfg.html#a963fa503522975f7e78da0e7085ac209">lumaKeyEnable</a></td></tr>
+<tr class="separator:a963fa503522975f7e78da0e7085ac209"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:af92d3bdda59367a1120e40316b8469b5"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_vid_pipe_luma_cfg.html#af92d3bdda59367a1120e40316b8469b5">lumaKeyMinVal</a></td></tr>
+<tr class="separator:af92d3bdda59367a1120e40316b8469b5"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:af695a93a94cb7e1981719483d56feda5"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_vid_pipe_luma_cfg.html#af695a93a94cb7e1981719483d56feda5">lumaKeyMaxVal</a></td></tr>
+<tr class="separator:af695a93a94cb7e1981719483d56feda5"><td class="memSeparator" colspan="2"> </td></tr>
+</table>
+<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
+<div class="textblock"><p>DSS Video Pipe Luma Key Config parameters. </p>
+</div><h2 class="groupheader">Field Documentation</h2>
+<a class="anchor" id="a963fa503522975f7e78da0e7085ac209"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t CSL_DssVidPipeLumaCfg::lumaKeyEnable</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Enable Luma Key transparency matching FALSE: Disable luma key operation TRUE: Enable luma key operation </p>
+
+</div>
+</div>
+<a class="anchor" id="af695a93a94cb7e1981719483d56feda5"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t CSL_DssVidPipeLumaCfg::lumaKeyMaxVal</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>12 bit Luma Key Max Value. luma_key_min <= Pixel's y <= luma_key_max. If condition is true alpha value will be forced to ZERO </p>
+
+</div>
+</div>
+<a class="anchor" id="af92d3bdda59367a1120e40316b8469b5"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t CSL_DssVidPipeLumaCfg::lumaKeyMinVal</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>12 bit Luma Key Min Value. luma_key_min <= Pixel's y <= luma_key_max. If condition is true alpha value will be forced to ZERO </p>
+
+</div>
+</div>
+<hr/>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="csl__dss_video_pipe_8h.html">csl_dssVideoPipe.h</a></li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/struct_c_s_l___dss_vid_pipe_m_flag_cfg.html b/packages/ti/drv/dss/docs/doxygen/html/struct_c_s_l___dss_vid_pipe_m_flag_cfg.html
--- /dev/null
@@ -0,0 +1,85 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>CSL_DssVidPipeMFlagCfg Struct Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li class="current"><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="files.html"><span>Files</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow2" class="tabs2">
+ <ul class="tablist">
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="functions.html"><span>Data Fields</span></a></li>
+ </ul>
+ </div>
+</div><!-- top -->
+<div class="header">
+ <div class="summary">
+<a href="#pub-attribs">Data Fields</a> </div>
+ <div class="headertitle">
+<div class="title">CSL_DssVidPipeMFlagCfg Struct Reference<div class="ingroups"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html">DSS Video Pipe CSL FL</a></div></div> </div>
+</div><!--header-->
+<div class="contents">
+
+<p>DSS Video Pipe MFLAG Config parameters.
+ <a href="struct_c_s_l___dss_vid_pipe_m_flag_cfg.html#details">More...</a></p>
+
+<p><code>#include <csl_dssVideoPipe.h></code></p>
+<table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
+Data Fields</h2></td></tr>
+<tr class="memitem:a10d1d9efb5a2b9c52b87f74b73c3b7ae"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_vid_pipe_m_flag_cfg.html#a10d1d9efb5a2b9c52b87f74b73c3b7ae">thresholdLow</a></td></tr>
+<tr class="separator:a10d1d9efb5a2b9c52b87f74b73c3b7ae"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a9457e4916f1490c14f3b1bda1b56db8a"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_vid_pipe_m_flag_cfg.html#a9457e4916f1490c14f3b1bda1b56db8a">thresholdHigh</a></td></tr>
+<tr class="separator:a9457e4916f1490c14f3b1bda1b56db8a"><td class="memSeparator" colspan="2"> </td></tr>
+</table>
+<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
+<div class="textblock"><p>DSS Video Pipe MFLAG Config parameters. </p>
+</div><h2 class="groupheader">Field Documentation</h2>
+<a class="anchor" id="a9457e4916f1490c14f3b1bda1b56db8a"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t CSL_DssVidPipeMFlagCfg::thresholdHigh</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>High threshold for mflag generation </p>
+
+</div>
+</div>
+<a class="anchor" id="a10d1d9efb5a2b9c52b87f74b73c3b7ae"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t CSL_DssVidPipeMFlagCfg::thresholdLow</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Low threshold for mflag generation </p>
+
+</div>
+</div>
+<hr/>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="csl__dss_video_pipe_8h.html">csl_dssVideoPipe.h</a></li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/struct_c_s_l___dss_vid_pipe_v_c1_cfg.html b/packages/ti/drv/dss/docs/doxygen/html/struct_c_s_l___dss_vid_pipe_v_c1_cfg.html
--- /dev/null
@@ -0,0 +1,100 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>CSL_DssVidPipeVC1Cfg Struct Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li class="current"><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="files.html"><span>Files</span></a></li>
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+ </div>
+ <div id="navrow2" class="tabs2">
+ <ul class="tablist">
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="functions.html"><span>Data Fields</span></a></li>
+ </ul>
+ </div>
+</div><!-- top -->
+<div class="header">
+ <div class="summary">
+<a href="#pub-attribs">Data Fields</a> </div>
+ <div class="headertitle">
+<div class="title">CSL_DssVidPipeVC1Cfg Struct Reference<div class="ingroups"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_i_p_e.html">DSS Video Pipe CSL FL</a></div></div> </div>
+</div><!--header-->
+<div class="contents">
+
+<p>DSS Video Pipe VC1 configuration.
+ <a href="struct_c_s_l___dss_vid_pipe_v_c1_cfg.html#details">More...</a></p>
+
+<p><code>#include <csl_dssVideoPipe.h></code></p>
+<table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
+Data Fields</h2></td></tr>
+<tr class="memitem:afd21865a4ea9a111674749d13e2aeec1"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_vid_pipe_v_c1_cfg.html#afd21865a4ea9a111674749d13e2aeec1">vc1Enable</a></td></tr>
+<tr class="separator:afd21865a4ea9a111674749d13e2aeec1"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ad5abb3e5a9aefd67f460c6c806d9d60a"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_vid_pipe_v_c1_cfg.html#ad5abb3e5a9aefd67f460c6c806d9d60a">rangeY</a></td></tr>
+<tr class="separator:ad5abb3e5a9aefd67f460c6c806d9d60a"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ae6ccf08aef3dd34a7470fc3f266f045c"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_vid_pipe_v_c1_cfg.html#ae6ccf08aef3dd34a7470fc3f266f045c">rangeUV</a></td></tr>
+<tr class="separator:ae6ccf08aef3dd34a7470fc3f266f045c"><td class="memSeparator" colspan="2"> </td></tr>
+</table>
+<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
+<div class="textblock"><p>DSS Video Pipe VC1 configuration. </p>
+</div><h2 class="groupheader">Field Documentation</h2>
+<a class="anchor" id="ae6ccf08aef3dd34a7470fc3f266f045c"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t CSL_DssVidPipeVC1Cfg::rangeUV</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>VC1 Range Value for UV(CbCr) Component, valid values 0-7 </p>
+
+</div>
+</div>
+<a class="anchor" id="ad5abb3e5a9aefd67f460c6c806d9d60a"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t CSL_DssVidPipeVC1Cfg::rangeY</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>VC1 Range Value for Y Component, valid values 0-7 </p>
+
+</div>
+</div>
+<a class="anchor" id="afd21865a4ea9a111674749d13e2aeec1"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t CSL_DssVidPipeVC1Cfg::vc1Enable</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Enable/disable VC1 mapping, should be enabled only for YUV formats </p>
+
+</div>
+</div>
+<hr/>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="csl__dss_video_pipe_8h.html">csl_dssVideoPipe.h</a></li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/struct_c_s_l___dss_vp_gamma_cfg.html b/packages/ti/drv/dss/docs/doxygen/html/struct_c_s_l___dss_vp_gamma_cfg.html
--- /dev/null
@@ -0,0 +1,85 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>CSL_DssVpGammaCfg Struct Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li class="current"><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="files.html"><span>Files</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow2" class="tabs2">
+ <ul class="tablist">
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="functions.html"><span>Data Fields</span></a></li>
+ </ul>
+ </div>
+</div><!-- top -->
+<div class="header">
+ <div class="summary">
+<a href="#pub-attribs">Data Fields</a> </div>
+ <div class="headertitle">
+<div class="title">CSL_DssVpGammaCfg Struct Reference<div class="ingroups"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html">DSS Video Port CSL FL</a></div></div> </div>
+</div><!--header-->
+<div class="contents">
+
+<p>Gamma Correction configuration for DSS Video Port Output.
+ <a href="struct_c_s_l___dss_vp_gamma_cfg.html#details">More...</a></p>
+
+<p><code>#include <csl_dssVideoPort.h></code></p>
+<table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
+Data Fields</h2></td></tr>
+<tr class="memitem:a64733ec49dec684d60ce3fe608323e90"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_vp_gamma_cfg.html#a64733ec49dec684d60ce3fe608323e90">gammaEnable</a></td></tr>
+<tr class="separator:a64733ec49dec684d60ce3fe608323e90"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:abe6f3edc0a2132f4c12e7a879069bca5"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_vp_gamma_cfg.html#abe6f3edc0a2132f4c12e7a879069bca5">gammaData</a> [<a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gac8a30c5680379b12128e75859e9f2312">CSL_DSS_NUM_LUT_ENTRIES</a>]</td></tr>
+<tr class="separator:abe6f3edc0a2132f4c12e7a879069bca5"><td class="memSeparator" colspan="2"> </td></tr>
+</table>
+<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
+<div class="textblock"><p>Gamma Correction configuration for DSS Video Port Output. </p>
+</div><h2 class="groupheader">Field Documentation</h2>
+<a class="anchor" id="abe6f3edc0a2132f4c12e7a879069bca5"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t CSL_DssVpGammaCfg::gammaData[<a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gac8a30c5680379b12128e75859e9f2312">CSL_DSS_NUM_LUT_ENTRIES</a>]</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Value to be stored in Gamma Table </p>
+
+</div>
+</div>
+<a class="anchor" id="a64733ec49dec684d60ce3fe608323e90"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t CSL_DssVpGammaCfg::gammaEnable</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Enable Gamma Correction FALSE: Disable Gamma TRUE: Enable Gamma </p>
+
+</div>
+</div>
+<hr/>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="csl__dss_video_port_8h.html">csl_dssVideoPort.h</a></li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/struct_c_s_l___dss_vp_lcd_adv_signal_cfg.html b/packages/ti/drv/dss/docs/doxygen/html/struct_c_s_l___dss_vp_lcd_adv_signal_cfg.html
--- /dev/null
@@ -0,0 +1,205 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>CSL_DssVpLcdAdvSignalCfg Struct Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li class="current"><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="files.html"><span>Files</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow2" class="tabs2">
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+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
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+ </ul>
+ </div>
+</div><!-- top -->
+<div class="header">
+ <div class="summary">
+<a href="#pub-attribs">Data Fields</a> </div>
+ <div class="headertitle">
+<div class="title">CSL_DssVpLcdAdvSignalCfg Struct Reference<div class="ingroups"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html">DSS Video Port CSL FL</a></div></div> </div>
+</div><!--header-->
+<div class="contents">
+
+<p>Advance Signal Configuration for the LCD.
+ <a href="struct_c_s_l___dss_vp_lcd_adv_signal_cfg.html#details">More...</a></p>
+
+<p><code>#include <csl_dssVideoPort.h></code></p>
+<table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
+Data Fields</h2></td></tr>
+<tr class="memitem:a2e82a5ae83cd53e3b4f0608a8058c69b"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_vp_lcd_adv_signal_cfg.html#a2e82a5ae83cd53e3b4f0608a8058c69b">hVAlign</a></td></tr>
+<tr class="separator:a2e82a5ae83cd53e3b4f0608a8058c69b"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a5794fc2d4b1012397f05e36b64e98809"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_vp_lcd_adv_signal_cfg.html#a5794fc2d4b1012397f05e36b64e98809">hVClkControl</a></td></tr>
+<tr class="separator:a5794fc2d4b1012397f05e36b64e98809"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ad021ce573a1521cf305a2f2080db9589"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_vp_lcd_adv_signal_cfg.html#ad021ce573a1521cf305a2f2080db9589">hVClkRiseFall</a></td></tr>
+<tr class="separator:ad021ce573a1521cf305a2f2080db9589"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a19de0b442f322232367aeb005332693a"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_vp_lcd_adv_signal_cfg.html#a19de0b442f322232367aeb005332693a">acBI</a></td></tr>
+<tr class="separator:a19de0b442f322232367aeb005332693a"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:acff326382d610c9f1680dae1e897d1c2"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_vp_lcd_adv_signal_cfg.html#acff326382d610c9f1680dae1e897d1c2">acB</a></td></tr>
+<tr class="separator:acff326382d610c9f1680dae1e897d1c2"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a8ff089c8259760a24199389c68519338"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_vp_lcd_adv_signal_cfg.html#a8ff089c8259760a24199389c68519338">vSyncGated</a></td></tr>
+<tr class="separator:a8ff089c8259760a24199389c68519338"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:aa9d9f9160213e99b0018acb25aad2873"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_vp_lcd_adv_signal_cfg.html#aa9d9f9160213e99b0018acb25aad2873">hSyncGated</a></td></tr>
+<tr class="separator:aa9d9f9160213e99b0018acb25aad2873"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a071dfbc56f4de8d9818e824d03a9662c"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_vp_lcd_adv_signal_cfg.html#a071dfbc56f4de8d9818e824d03a9662c">pixelClockGated</a></td></tr>
+<tr class="separator:a071dfbc56f4de8d9818e824d03a9662c"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a32ff2b36d117b98e574214336a68616e"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_vp_lcd_adv_signal_cfg.html#a32ff2b36d117b98e574214336a68616e">pixelDataGated</a></td></tr>
+<tr class="separator:a32ff2b36d117b98e574214336a68616e"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a3111150c26bb26812762ef8de4ba03d6"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_vp_lcd_adv_signal_cfg.html#a3111150c26bb26812762ef8de4ba03d6">pixelGated</a></td></tr>
+<tr class="separator:a3111150c26bb26812762ef8de4ba03d6"><td class="memSeparator" colspan="2"> </td></tr>
+</table>
+<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
+<div class="textblock"><p>Advance Signal Configuration for the LCD. </p>
+</div><h2 class="groupheader">Field Documentation</h2>
+<a class="anchor" id="acff326382d610c9f1680dae1e897d1c2"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t CSL_DssVpLcdAdvSignalCfg::acB</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>AC bias pin frequency RW 0x00 Value (from 0 to 255) used to specify the number of line clocks to count before transitioning the AC bias pin. This pin is used to periodically invert the polarity of the power supply to prevent DC charge buildup within the display </p>
+
+</div>
+</div>
+<a class="anchor" id="a19de0b442f322232367aeb005332693a"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t CSL_DssVpLcdAdvSignalCfg::acBI</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>AC bias pin transitions per interrupt. Value (from 0 to 15) used to specify the number of AC bias pin transitions </p>
+
+</div>
+</div>
+<a class="anchor" id="aa9d9f9160213e99b0018acb25aad2873"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t CSL_DssVpLcdAdvSignalCfg::hSyncGated</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>HSYNC gated enabled FALSE: HSYNC gated disabled TRUE: HSYNC gated enabled </p>
+
+</div>
+</div>
+<a class="anchor" id="a2e82a5ae83cd53e3b4f0608a8058c69b"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t CSL_DssVpLcdAdvSignalCfg::hVAlign</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Defines the alignment between HSYNC and VSYNC assertion. For valid values see <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#CSL_DssVpLcdHVSyncAlign">CSL_DssVpLcdHVSyncAlign</a> </p>
+
+</div>
+</div>
+<a class="anchor" id="a5794fc2d4b1012397f05e36b64e98809"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t CSL_DssVpLcdAdvSignalCfg::hVClkControl</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>HSYNC/VSYNC pixel clock control on/off. For valid values see <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#CSL_DssVpLcdHVClkControl">CSL_DssVpLcdHVClkControl</a> </p>
+
+</div>
+</div>
+<a class="anchor" id="ad021ce573a1521cf305a2f2080db9589"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t CSL_DssVpLcdAdvSignalCfg::hVClkRiseFall</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Program HSYNC/VSYNC rise or fall For valid values see <a class="el" href="csl__fvid2__data_types_8h.html#acfe95315f6c3bfd70f38bb2d4486bd19" title="Rising Edge. ">Fvid2_EdgePolarity</a> </p>
+
+</div>
+</div>
+<a class="anchor" id="a071dfbc56f4de8d9818e824d03a9662c"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t CSL_DssVpLcdAdvSignalCfg::pixelClockGated</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Pixel clock gated enabled FALSE: Pixel clock gated disabled TRUE: Pixel clock gated enabled </p>
+
+</div>
+</div>
+<a class="anchor" id="a32ff2b36d117b98e574214336a68616e"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t CSL_DssVpLcdAdvSignalCfg::pixelDataGated</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Pixel data gated enabled FALSE: Pixel data gated disabled TRUE: Pixel data gated enabled </p>
+
+</div>
+</div>
+<a class="anchor" id="a3111150c26bb26812762ef8de4ba03d6"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t CSL_DssVpLcdAdvSignalCfg::pixelGated</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Pixel gated enable (only for TFT) FALSE: Pixel clock always toggles (only in TFT mode) TRUE: Pixel clock toggles only when there is valid data to display (only in TFT mode) </p>
+
+</div>
+</div>
+<a class="anchor" id="a8ff089c8259760a24199389c68519338"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t CSL_DssVpLcdAdvSignalCfg::vSyncGated</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>VSYNC gated enabled FALSE: VSYNC gated disabled TRUE: VSYNC gated enabled </p>
+
+</div>
+</div>
+<hr/>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="csl__dss_video_port_8h.html">csl_dssVideoPort.h</a></li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/struct_c_s_l___dss_vp_lcd_blank_timing_cfg.html b/packages/ti/drv/dss/docs/doxygen/html/struct_c_s_l___dss_vp_lcd_blank_timing_cfg.html
--- /dev/null
@@ -0,0 +1,145 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>CSL_DssVpLcdBlankTimingCfg Struct Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li class="current"><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="files.html"><span>Files</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow2" class="tabs2">
+ <ul class="tablist">
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="functions.html"><span>Data Fields</span></a></li>
+ </ul>
+ </div>
+</div><!-- top -->
+<div class="header">
+ <div class="summary">
+<a href="#pub-attribs">Data Fields</a> </div>
+ <div class="headertitle">
+<div class="title">CSL_DssVpLcdBlankTimingCfg Struct Reference<div class="ingroups"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html">DSS Video Port CSL FL</a></div></div> </div>
+</div><!--header-->
+<div class="contents">
+
+<p>Blanking Timing parameters for the LCD.
+ <a href="struct_c_s_l___dss_vp_lcd_blank_timing_cfg.html#details">More...</a></p>
+
+<p><code>#include <csl_dssVideoPort.h></code></p>
+<table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
+Data Fields</h2></td></tr>
+<tr class="memitem:acdf92ed15c2e9ee31271fb9d611665b5"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_vp_lcd_blank_timing_cfg.html#acdf92ed15c2e9ee31271fb9d611665b5">hFrontPorch</a></td></tr>
+<tr class="separator:acdf92ed15c2e9ee31271fb9d611665b5"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:afea7b5341ea83edbb5d067c5bc8a152b"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_vp_lcd_blank_timing_cfg.html#afea7b5341ea83edbb5d067c5bc8a152b">hBackPorch</a></td></tr>
+<tr class="separator:afea7b5341ea83edbb5d067c5bc8a152b"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ad79981ec3f4a8df8ee12b1dd96e7c667"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_vp_lcd_blank_timing_cfg.html#ad79981ec3f4a8df8ee12b1dd96e7c667">hSyncLen</a></td></tr>
+<tr class="separator:ad79981ec3f4a8df8ee12b1dd96e7c667"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a0155b917c75ee07e575746a3e3e431d3"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_vp_lcd_blank_timing_cfg.html#a0155b917c75ee07e575746a3e3e431d3">vFrontPorch</a></td></tr>
+<tr class="separator:a0155b917c75ee07e575746a3e3e431d3"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:aa47f7bea5a1b26d347984a25769e5424"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_vp_lcd_blank_timing_cfg.html#aa47f7bea5a1b26d347984a25769e5424">vBackPorch</a></td></tr>
+<tr class="separator:aa47f7bea5a1b26d347984a25769e5424"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:aac23b4702301fa2aa6a64ac5299fd2ba"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_vp_lcd_blank_timing_cfg.html#aac23b4702301fa2aa6a64ac5299fd2ba">vSyncLen</a></td></tr>
+<tr class="separator:aac23b4702301fa2aa6a64ac5299fd2ba"><td class="memSeparator" colspan="2"> </td></tr>
+</table>
+<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
+<div class="textblock"><p>Blanking Timing parameters for the LCD. </p>
+</div><h2 class="groupheader">Field Documentation</h2>
+<a class="anchor" id="afea7b5341ea83edbb5d067c5bc8a152b"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t CSL_DssVpLcdBlankTimingCfg::hBackPorch</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Horizontal Back Porch, specifies the number of pixel clock periods to add to the beginning of a line transmission before the first set of pixels is output to the display. In BT mode and interlaced, this field corresponds to the vertical field blanking No 2 for Even Field. In case of BT progressive mode this field is unused </p>
+
+</div>
+</div>
+<a class="anchor" id="acdf92ed15c2e9ee31271fb9d611665b5"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t CSL_DssVpLcdBlankTimingCfg::hFrontPorch</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Horizontal Front Porch, specifies the number of pixel clock periods to add to the end of a line transmission before line clock is asserted. In BT mode and interlaced, this field corresponds to the vertical field blanking No 1 for Even Field. In case of BT progressive mode this field is unused </p>
+
+</div>
+</div>
+<a class="anchor" id="ad79981ec3f4a8df8ee12b1dd96e7c667"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t CSL_DssVpLcdBlankTimingCfg::hSyncLen</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Horizontal synchronization pulse width, Encoded Value(from 1 to 256)to specify the number of pixel clock periods to pulse the line clock at the end of each line. In BT mode, this field corresponds to 12-bit horizontal blanking </p>
+
+</div>
+</div>
+<a class="anchor" id="aa47f7bea5a1b26d347984a25769e5424"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t CSL_DssVpLcdBlankTimingCfg::vBackPorch</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Vertical back porch encoded value (from 0 to 4095) to specify the number of line clock periods to add to the beginning of a frame. In BT mode and interlaced, this field corresponds to the vertical field blanking No 2 for Odd Field. In case of BT progressive mode this field corresponds to the Vertical frame blanking No 2 before the first set of pixels is output to the display </p>
+
+</div>
+</div>
+<a class="anchor" id="a0155b917c75ee07e575746a3e3e431d3"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t CSL_DssVpLcdBlankTimingCfg::vFrontPorch</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Vertical front porch encoded value (from 0 to 4095) to specify the number of line clock periods to add to the end of each frame. When in BT mode and interlaced, this field corresponds to the vertical field blanking No 1 for Odd Field. In case of BT progressive mode this field corresponds to the Vertical frame blanking No 2 </p>
+
+</div>
+</div>
+<a class="anchor" id="aac23b4702301fa2aa6a64ac5299fd2ba"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t CSL_DssVpLcdBlankTimingCfg::vSyncLen</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Vertical synchronization pulse width In active mode, RW 0x00 encoded value (from 1 to 256) to specify the number of line clock periods (program to value minus 1) to pulse the frame clock (VSYNC) pin at the end of each frame after the end of frame wait (VFP) period elapses. Frame clock uses as VSYNC signal in active mode. In BT mode, this field is not used </p>
+
+</div>
+</div>
+<hr/>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="csl__dss_video_port_8h.html">csl_dssVideoPort.h</a></li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/struct_c_s_l___dss_vp_lcd_op_timing_cfg.html b/packages/ti/drv/dss/docs/doxygen/html/struct_c_s_l___dss_vp_lcd_op_timing_cfg.html
--- /dev/null
@@ -0,0 +1,184 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>CSL_DssVpLcdOpTimingCfg Struct Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li class="current"><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="files.html"><span>Files</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow2" class="tabs2">
+ <ul class="tablist">
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="functions.html"><span>Data Fields</span></a></li>
+ </ul>
+ </div>
+</div><!-- top -->
+<div class="header">
+ <div class="summary">
+<a href="#pub-attribs">Data Fields</a> </div>
+ <div class="headertitle">
+<div class="title">CSL_DssVpLcdOpTimingCfg Struct Reference<div class="ingroups"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html">DSS Video Port CSL FL</a></div></div> </div>
+</div><!--header-->
+<div class="contents">
+
+<p>Timing configuration for the LCD output.
+ <a href="struct_c_s_l___dss_vp_lcd_op_timing_cfg.html#details">More...</a></p>
+
+<p><code>#include <csl_dssVideoPort.h></code></p>
+<table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
+Data Fields</h2></td></tr>
+<tr class="memitem:a19292617b2fdd63c9d9d85a1ea41d97a"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_fvid2___mode_info.html">Fvid2_ModeInfo</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_vp_lcd_op_timing_cfg.html#a19292617b2fdd63c9d9d85a1ea41d97a">mInfo</a></td></tr>
+<tr class="separator:a19292617b2fdd63c9d9d85a1ea41d97a"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:aaeadccfcb9ea48ce2989afa051909b2e"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_vp_lcd_op_timing_cfg.html#aaeadccfcb9ea48ce2989afa051909b2e">dvoFormat</a></td></tr>
+<tr class="separator:aaeadccfcb9ea48ce2989afa051909b2e"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a1e927fefea2d081753712d11f440731d"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_vp_lcd_op_timing_cfg.html#a1e927fefea2d081753712d11f440731d">cscRange</a></td></tr>
+<tr class="separator:a1e927fefea2d081753712d11f440731d"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a9967666ac6fea7f27b7fcfd6e4da55a6"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_vp_lcd_op_timing_cfg.html#a9967666ac6fea7f27b7fcfd6e4da55a6">videoIfWidth</a></td></tr>
+<tr class="separator:a9967666ac6fea7f27b7fcfd6e4da55a6"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a4d8eec6b33ff2de5a769235aee2a2acb"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_vp_lcd_op_timing_cfg.html#a4d8eec6b33ff2de5a769235aee2a2acb">deltaLinesPerPanel</a></td></tr>
+<tr class="separator:a4d8eec6b33ff2de5a769235aee2a2acb"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a5348fe79a6dc369023b8f569b36d731b"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_vp_lcd_op_timing_cfg.html#a5348fe79a6dc369023b8f569b36d731b">fidFirst</a></td></tr>
+<tr class="separator:a5348fe79a6dc369023b8f569b36d731b"><td class="memSeparator" colspan="2"> </td></tr>
+</table>
+<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
+<div class="textblock"><p>Timing configuration for the LCD output. </p>
+</div><h2 class="groupheader">Field Documentation</h2>
+<a class="anchor" id="a1e927fefea2d081753712d11f440731d"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t CSL_DssVpLcdOpTimingCfg::cscRange</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>CSC Range. For valid values see <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#CSL_DssCscRange">CSL_DssCscRange</a> </p>
+
+</div>
+</div>
+<a class="anchor" id="a4d8eec6b33ff2de5a769235aee2a2acb"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t CSL_DssVpLcdOpTimingCfg::deltaLinesPerPanel</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Delta size of the odd field compared to the even field. For valid values see <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#CSL_DssVpDeltaLpp">CSL_DssVpDeltaLpp</a> </p>
+
+</div>
+</div>
+<a class="anchor" id="aaeadccfcb9ea48ce2989afa051909b2e"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t CSL_DssVpLcdOpTimingCfg::dvoFormat</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Digital output format. For valid values see <a class="el" href="csl__fvid2__data_types_8h.html#Fvid2_DVFormat">Fvid2_DVFormat</a> </p>
+
+</div>
+</div>
+<a class="anchor" id="a5348fe79a6dc369023b8f569b36d731b"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t CSL_DssVpLcdOpTimingCfg::fidFirst</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Selects the first field to output in case of interlace mode. In case of progressive mode, the value is not used. For valid values see <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#CSL_DssVpFidFirstVal">CSL_DssVpFidFirstVal</a> </p>
+
+</div>
+</div>
+<a class="anchor" id="a19292617b2fdd63c9d9d85a1ea41d97a"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname"><a class="el" href="struct_fvid2___mode_info.html">Fvid2_ModeInfo</a> CSL_DssVpLcdOpTimingCfg::mInfo</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>FVID2 mode information <a class="el" href="struct_fvid2___mode_info.html" title="FVID2 Mode information structure. ">Fvid2_ModeInfo</a></p>
+<p><b>standard</b>:<br/>
+ Standard for which to get the info. For valid values see <a class="el" href="csl__fvid2__data_types_8h.html#aaa2667d105d557f254c20b87534ed4b6" title="720x480 30FPS interlaced NTSC standard. ">Fvid2_Standard</a>. In case of <b>BT output</b> this should always be FVID2_STD_CUSTOM<br/>
+</p>
+<p><b>width</b>:<br/>
+ Active video frame width in pixels <br/>
+</p>
+<p><b>height</b>:<br/>
+ Active video frame height in lines <br/>
+</p>
+<p><b>scanFormat</b>:<br/>
+ Scan format of standard. For valid values see <a class="el" href="csl__fvid2__data_types_8h.html#af5dfad95adb11f1220c13a37564b706e" title="Interlaced mode. ">Fvid2_ScanFormat</a><br/>
+</p>
+<p><b>hFrontPorch</b>:<br/>
+ Horizontal Front Porch. Specifies the number of pixel clock periods to add to the end of a line transmission before line clock is asserted. In BT mode and interlaced, this field corresponds to the vertical field blanking No 1 for Even Field. In case of BT progressive mode this field is unused<br/>
+</p>
+<p><b>hBackPorch</b>:<br/>
+ Horizontal Back Porch. Specifies the number of pixel clock periods to add to the beginning of a line transmission before the first set of pixels is output to the display. In BT mode and interlaced, this field corresponds to the vertical field blanking No 2 for Even Field. In case of BT progressive mode this field is unused<br/>
+</p>
+<p><b>hSyncLen</b>:<br/>
+ Horizontal synchronization pulse width. Encoded Value(from 1 to 256)to specify the number of pixel clock periods to pulse the line clock at the end of each line. In BT mode, this field corresponds to 12-bit horizontal blanking<br/>
+</p>
+<p><b>vFrontPorch</b>:<br/>
+ Vertical front porch. Encoded value (from 0 to 4095) to specify the number of line clock periods to add to the end of each frame. When in BT mode and interlaced, this field corresponds to the vertical field blanking No 1 for Odd Field. In case of BT progressive mode this field corresponds to the Vertical frame blanking No 2<br/>
+</p>
+<p><b>vBackPorch</b>:<br/>
+ Vertical back porch. Encoded value (from 0 to 4095) to specify the number of line clock periods to add to the beginning of a frame. In BT mode and interlaced, this field corresponds to the vertical field blanking No 2 for Odd Field. In case of BT progressive mode this field corresponds to the Vertical frame blanking No 2 before the first set of pixels is output to the display<br/>
+</p>
+<p><b>vSyncLen</b>:<br/>
+ Vertical synchronization pulse width. In active mode, RW 0x00 encoded value (from 1 to 256) to specify the number of line clock periods (program to value minus 1) to pulse the frame clock (VSYNC) pin at the end of each frame after the end of frame wait (VFP) period elapses. In BT mode, this field is not used<br/>
+</p>
+<p><b>pixelClock, fps</b>: Not used, set to 0 or default </p>
+
+</div>
+</div>
+<a class="anchor" id="a9967666ac6fea7f27b7fcfd6e4da55a6"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t CSL_DssVpLcdOpTimingCfg::videoIfWidth</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Video interface Width, Valid options are<br/>
+ FVID2_VIFW_12BIT,<br/>
+ FVID2_VIFW_16BIT,<br/>
+ FVID2_VIFW_18BIT,<br/>
+ FVID2_VIFW_24BIT,<br/>
+ FVID2_VIFW_30BIT,<br/>
+ FVID2_VIFW_36BIT<br/>
+ For more details see <a class="el" href="csl__fvid2__data_types_8h.html#a3644341e8e51f60794fb15f219f0a5f7" title="8-bit interface. ">Fvid2_VideoIfWidth</a><br/>
+ </p>
+
+</div>
+</div>
+<hr/>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="csl__dss_video_port_8h.html">csl_dssVideoPort.h</a></li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/struct_c_s_l___dss_vp_lcd_signal_polarity_cfg.html b/packages/ti/drv/dss/docs/doxygen/html/struct_c_s_l___dss_vp_lcd_signal_polarity_cfg.html
--- /dev/null
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+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>CSL_DssVpLcdSignalPolarityCfg Struct Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li class="current"><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="files.html"><span>Files</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow2" class="tabs2">
+ <ul class="tablist">
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="functions.html"><span>Data Fields</span></a></li>
+ </ul>
+ </div>
+</div><!-- top -->
+<div class="header">
+ <div class="summary">
+<a href="#pub-attribs">Data Fields</a> </div>
+ <div class="headertitle">
+<div class="title">CSL_DssVpLcdSignalPolarityCfg Struct Reference<div class="ingroups"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html">DSS Video Port CSL FL</a></div></div> </div>
+</div><!--header-->
+<div class="contents">
+
+<p>Polarity of Active Video, Pixel Clock, HSync and VSync signals for the LCD.
+ <a href="struct_c_s_l___dss_vp_lcd_signal_polarity_cfg.html#details">More...</a></p>
+
+<p><code>#include <csl_dssVideoPort.h></code></p>
+<table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
+Data Fields</h2></td></tr>
+<tr class="memitem:aba814560abdf027968da571705fe6873"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_vp_lcd_signal_polarity_cfg.html#aba814560abdf027968da571705fe6873">actVidPolarity</a></td></tr>
+<tr class="separator:aba814560abdf027968da571705fe6873"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a097ae617d62555043fe4edd375a6963c"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_vp_lcd_signal_polarity_cfg.html#a097ae617d62555043fe4edd375a6963c">pixelClkPolarity</a></td></tr>
+<tr class="separator:a097ae617d62555043fe4edd375a6963c"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a07d10e32b5c69a73ab69eb18f0e3e1e7"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_vp_lcd_signal_polarity_cfg.html#a07d10e32b5c69a73ab69eb18f0e3e1e7">hsPolarity</a></td></tr>
+<tr class="separator:a07d10e32b5c69a73ab69eb18f0e3e1e7"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:af04cf78189cce9f85c441bf4e22f23d7"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_vp_lcd_signal_polarity_cfg.html#af04cf78189cce9f85c441bf4e22f23d7">vsPolarity</a></td></tr>
+<tr class="separator:af04cf78189cce9f85c441bf4e22f23d7"><td class="memSeparator" colspan="2"> </td></tr>
+</table>
+<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
+<div class="textblock"><p>Polarity of Active Video, Pixel Clock, HSync and VSync signals for the LCD. </p>
+</div><h2 class="groupheader">Field Documentation</h2>
+<a class="anchor" id="aba814560abdf027968da571705fe6873"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t CSL_DssVpLcdSignalPolarityCfg::actVidPolarity</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Invert output enable For valid values see <a class="el" href="csl__fvid2__data_types_8h.html#a9e9754a80a4e33aebaf391204a570723" title="Low Polarity. ">Fvid2_Polarity</a> </p>
+
+</div>
+</div>
+<a class="anchor" id="a07d10e32b5c69a73ab69eb18f0e3e1e7"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t CSL_DssVpLcdSignalPolarityCfg::hsPolarity</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>HSYNC Polarity For valid values see <a class="el" href="csl__fvid2__data_types_8h.html#a9e9754a80a4e33aebaf391204a570723" title="Low Polarity. ">Fvid2_Polarity</a> </p>
+
+</div>
+</div>
+<a class="anchor" id="a097ae617d62555043fe4edd375a6963c"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t CSL_DssVpLcdSignalPolarityCfg::pixelClkPolarity</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Invert pixel clock For valid values see <a class="el" href="csl__fvid2__data_types_8h.html#acfe95315f6c3bfd70f38bb2d4486bd19" title="Rising Edge. ">Fvid2_EdgePolarity</a> </p>
+
+</div>
+</div>
+<a class="anchor" id="af04cf78189cce9f85c441bf4e22f23d7"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t CSL_DssVpLcdSignalPolarityCfg::vsPolarity</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>VSYNC Polarity For valid values see <a class="el" href="csl__fvid2__data_types_8h.html#a9e9754a80a4e33aebaf391204a570723" title="Low Polarity. ">Fvid2_Polarity</a> </p>
+
+</div>
+</div>
+<hr/>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="csl__dss_video_port_8h.html">csl_dssVideoPort.h</a></li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/struct_c_s_l___dss_vp_lcd_tdm_cfg.html b/packages/ti/drv/dss/docs/doxygen/html/struct_c_s_l___dss_vp_lcd_tdm_cfg.html
--- /dev/null
@@ -0,0 +1,295 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>CSL_DssVpLcdTdmCfg Struct Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li class="current"><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="files.html"><span>Files</span></a></li>
+ </ul>
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+ <div id="navrow2" class="tabs2">
+ <ul class="tablist">
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="functions.html"><span>Data Fields</span></a></li>
+ </ul>
+ </div>
+</div><!-- top -->
+<div class="header">
+ <div class="summary">
+<a href="#pub-attribs">Data Fields</a> </div>
+ <div class="headertitle">
+<div class="title">CSL_DssVpLcdTdmCfg Struct Reference<div class="ingroups"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html">DSS Video Port CSL FL</a></div></div> </div>
+</div><!--header-->
+<div class="contents">
+
+<p>LCD Configuration for Time Division Multiplexing.
+ <a href="struct_c_s_l___dss_vp_lcd_tdm_cfg.html#details">More...</a></p>
+
+<p><code>#include <csl_dssVideoPort.h></code></p>
+<table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
+Data Fields</h2></td></tr>
+<tr class="memitem:abb0166aec4ae051ab0dd636877340902"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_vp_lcd_tdm_cfg.html#abb0166aec4ae051ab0dd636877340902">tdmEnable</a></td></tr>
+<tr class="separator:abb0166aec4ae051ab0dd636877340902"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:aa36d89a896199beac0c818f878730876"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_vp_lcd_tdm_cfg.html#aa36d89a896199beac0c818f878730876">tdmUnusedBitsLevel</a></td></tr>
+<tr class="separator:aa36d89a896199beac0c818f878730876"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ae96d7a4d10f0aba11ae1fe050bbb4bae"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_vp_lcd_tdm_cfg.html#ae96d7a4d10f0aba11ae1fe050bbb4bae">tdmCycleFormat</a></td></tr>
+<tr class="separator:ae96d7a4d10f0aba11ae1fe050bbb4bae"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:aba88a2bb1746761f7406f66d04f5412a"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_vp_lcd_tdm_cfg.html#aba88a2bb1746761f7406f66d04f5412a">tdmParallelMode</a></td></tr>
+<tr class="separator:aba88a2bb1746761f7406f66d04f5412a"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a0d9325def55c887e1e6d6b240c66e290"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_vp_lcd_tdm_cfg.html#a0d9325def55c887e1e6d6b240c66e290">numBitsPixel1Cycle0</a></td></tr>
+<tr class="separator:a0d9325def55c887e1e6d6b240c66e290"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:acdc280739512994d6cc71dd1125e12fb"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_vp_lcd_tdm_cfg.html#acdc280739512994d6cc71dd1125e12fb">numBitsPixel1Cycle1</a></td></tr>
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+<tr class="memitem:ae83d325c5b05f1db8045509f5de15269"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_vp_lcd_tdm_cfg.html#ae83d325c5b05f1db8045509f5de15269">numBitsPixel1Cycle2</a></td></tr>
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+<tr class="memitem:abab9fab501255acd87c1ab71e02df53a"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_vp_lcd_tdm_cfg.html#abab9fab501255acd87c1ab71e02df53a">bitAlignPixel1Cycle0</a></td></tr>
+<tr class="separator:abab9fab501255acd87c1ab71e02df53a"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a62a5d33c4b5cdaf4a1837a9062319b8d"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_vp_lcd_tdm_cfg.html#a62a5d33c4b5cdaf4a1837a9062319b8d">bitAlignPixel1Cycle1</a></td></tr>
+<tr class="separator:a62a5d33c4b5cdaf4a1837a9062319b8d"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a1fa26016fc933f54738aebc327fa8cac"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_vp_lcd_tdm_cfg.html#a1fa26016fc933f54738aebc327fa8cac">bitAlignPixel1Cycle2</a></td></tr>
+<tr class="separator:a1fa26016fc933f54738aebc327fa8cac"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a24039fc18531e5abf5f24eae912385d4"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_vp_lcd_tdm_cfg.html#a24039fc18531e5abf5f24eae912385d4">numBitsPixel2Cycle0</a></td></tr>
+<tr class="separator:a24039fc18531e5abf5f24eae912385d4"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:adc86e977d445f895132a246b494ae240"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_vp_lcd_tdm_cfg.html#adc86e977d445f895132a246b494ae240">numBitsPixel2Cycle1</a></td></tr>
+<tr class="separator:adc86e977d445f895132a246b494ae240"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ad1b25370dd21ced32c4a9a3abb5e50f0"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_vp_lcd_tdm_cfg.html#ad1b25370dd21ced32c4a9a3abb5e50f0">numBitsPixel2Cycle2</a></td></tr>
+<tr class="separator:ad1b25370dd21ced32c4a9a3abb5e50f0"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:aa23d4e0d384e3af3988eab00332b626f"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_vp_lcd_tdm_cfg.html#aa23d4e0d384e3af3988eab00332b626f">bitAlignPixel2Cycle0</a></td></tr>
+<tr class="separator:aa23d4e0d384e3af3988eab00332b626f"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a14eac5468c7e383536d68992ccbdbf69"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_vp_lcd_tdm_cfg.html#a14eac5468c7e383536d68992ccbdbf69">bitAlignPixel2Cycle1</a></td></tr>
+<tr class="separator:a14eac5468c7e383536d68992ccbdbf69"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ada6dacedb1a801fe5f91396b7252a719"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_vp_lcd_tdm_cfg.html#ada6dacedb1a801fe5f91396b7252a719">bitAlignPixel2Cycle2</a></td></tr>
+<tr class="separator:ada6dacedb1a801fe5f91396b7252a719"><td class="memSeparator" colspan="2"> </td></tr>
+</table>
+<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
+<div class="textblock"><p>LCD Configuration for Time Division Multiplexing. </p>
+</div><h2 class="groupheader">Field Documentation</h2>
+<a class="anchor" id="abab9fab501255acd87c1ab71e02df53a"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t CSL_DssVpLcdTdmCfg::bitAlignPixel1Cycle0</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Alignment of the bits from pixel 1 for cycle0 on the output interface </p>
+
+</div>
+</div>
+<a class="anchor" id="a62a5d33c4b5cdaf4a1837a9062319b8d"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t CSL_DssVpLcdTdmCfg::bitAlignPixel1Cycle1</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Alignment of the bits from pixel 1 for cycle1 on the output interface </p>
+
+</div>
+</div>
+<a class="anchor" id="a1fa26016fc933f54738aebc327fa8cac"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t CSL_DssVpLcdTdmCfg::bitAlignPixel1Cycle2</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Alignment of the bits from pixel 1 for cycle2 on the output interface </p>
+
+</div>
+</div>
+<a class="anchor" id="aa23d4e0d384e3af3988eab00332b626f"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t CSL_DssVpLcdTdmCfg::bitAlignPixel2Cycle0</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Alignment of the bits from pixel 2 for cycle 0 on the output interface </p>
+
+</div>
+</div>
+<a class="anchor" id="a14eac5468c7e383536d68992ccbdbf69"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t CSL_DssVpLcdTdmCfg::bitAlignPixel2Cycle1</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Alignment of the bits from pixel 2 for cycle 1 on the output interface </p>
+
+</div>
+</div>
+<a class="anchor" id="ada6dacedb1a801fe5f91396b7252a719"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t CSL_DssVpLcdTdmCfg::bitAlignPixel2Cycle2</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Alignment of the bits from pixel 2 for cycle 2 on the output interface </p>
+
+</div>
+</div>
+<a class="anchor" id="a0d9325def55c887e1e6d6b240c66e290"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t CSL_DssVpLcdTdmCfg::numBitsPixel1Cycle0</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Number of bits from the pixel 1 for cycle 0(value from 0 to 16 bits). The values from 17 to 31 are invalid </p>
+
+</div>
+</div>
+<a class="anchor" id="acdc280739512994d6cc71dd1125e12fb"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t CSL_DssVpLcdTdmCfg::numBitsPixel1Cycle1</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Number of bits from the pixel 1 for cycle 1(value from 0 to 16 bits). The values from 17 to 31 are invalid </p>
+
+</div>
+</div>
+<a class="anchor" id="ae83d325c5b05f1db8045509f5de15269"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t CSL_DssVpLcdTdmCfg::numBitsPixel1Cycle2</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Number of bits from the pixel 1 for cycle 2(value from 0 to 16 bits). The values from 17 to 31 are invalid </p>
+
+</div>
+</div>
+<a class="anchor" id="a24039fc18531e5abf5f24eae912385d4"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t CSL_DssVpLcdTdmCfg::numBitsPixel2Cycle0</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Number of bits from the pixel 2 for cycle 0(value from 0 to 16 bits). The values from 17 to 31 are invalid </p>
+
+</div>
+</div>
+<a class="anchor" id="adc86e977d445f895132a246b494ae240"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t CSL_DssVpLcdTdmCfg::numBitsPixel2Cycle1</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Number of bits from the pixel 2 for cycle 1(value from 0 to 16 bits). The values from 17 to 31 are invalid </p>
+
+</div>
+</div>
+<a class="anchor" id="ad1b25370dd21ced32c4a9a3abb5e50f0"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t CSL_DssVpLcdTdmCfg::numBitsPixel2Cycle2</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Number of bits from the pixel 2 for cycle 2(value from 0 to 16 bits). The values from 17 to 31 are invalid </p>
+
+</div>
+</div>
+<a class="anchor" id="ae96d7a4d10f0aba11ae1fe050bbb4bae"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t CSL_DssVpLcdTdmCfg::tdmCycleFormat</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Cycle format (TDM mode only) for the VP output. For valid values see <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#CSL_DssVpTdmCycleFormat">CSL_DssVpTdmCycleFormat</a> </p>
+
+</div>
+</div>
+<a class="anchor" id="abb0166aec4ae051ab0dd636877340902"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t CSL_DssVpLcdTdmCfg::tdmEnable</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Enable the multiple cycle format for the VP output FALSE: Disable TDM TRUE: Enable TDM </p>
+
+</div>
+</div>
+<a class="anchor" id="aba88a2bb1746761f7406f66d04f5412a"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t CSL_DssVpLcdTdmCfg::tdmParallelMode</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Output interface width (TDM mode only) for the VP output. For valid values see <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#CSL_DssVpTdmParallelMode">CSL_DssVpTdmParallelMode</a> </p>
+
+</div>
+</div>
+<a class="anchor" id="aa36d89a896199beac0c818f878730876"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t CSL_DssVpLcdTdmCfg::tdmUnusedBitsLevel</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>State of unused bits (TDM mode only) for the VP output. For valid values see <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#CSL_DssVpTdmUnusedBitsLevel">CSL_DssVpTdmUnusedBitsLevel</a> </p>
+
+</div>
+</div>
+<hr/>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="csl__dss_video_port_8h.html">csl_dssVideoPort.h</a></li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/struct_c_s_l___dss_vp_oldi_cfg.html b/packages/ti/drv/dss/docs/doxygen/html/struct_c_s_l___dss_vp_oldi_cfg.html
--- /dev/null
@@ -0,0 +1,100 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>CSL_DssVpOldiCfg Struct Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li class="current"><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="files.html"><span>Files</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow2" class="tabs2">
+ <ul class="tablist">
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="functions.html"><span>Data Fields</span></a></li>
+ </ul>
+ </div>
+</div><!-- top -->
+<div class="header">
+ <div class="summary">
+<a href="#pub-attribs">Data Fields</a> </div>
+ <div class="headertitle">
+<div class="title">CSL_DssVpOldiCfg Struct Reference<div class="ingroups"><a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html">DSS Video Port CSL FL</a></div></div> </div>
+</div><!--header-->
+<div class="contents">
+
+<p>OLDI Configuration.
+ <a href="struct_c_s_l___dss_vp_oldi_cfg.html#details">More...</a></p>
+
+<p><code>#include <csl_dssVideoPort.h></code></p>
+<table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
+Data Fields</h2></td></tr>
+<tr class="memitem:a52a9e531691e023b7634991e3096fc1e"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_vp_oldi_cfg.html#a52a9e531691e023b7634991e3096fc1e">oldiMapType</a></td></tr>
+<tr class="separator:a52a9e531691e023b7634991e3096fc1e"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a94f5f9c85756db0b4dc7bc0b19c7440c"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_vp_oldi_cfg.html#a94f5f9c85756db0b4dc7bc0b19c7440c">dataEnablePolarity</a></td></tr>
+<tr class="separator:a94f5f9c85756db0b4dc7bc0b19c7440c"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a0a2827a2b6a0402e988bc0aabf2d04f0"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_c_s_l___dss_vp_oldi_cfg.html#a0a2827a2b6a0402e988bc0aabf2d04f0">dssBitDepth</a></td></tr>
+<tr class="separator:a0a2827a2b6a0402e988bc0aabf2d04f0"><td class="memSeparator" colspan="2"> </td></tr>
+</table>
+<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
+<div class="textblock"><p>OLDI Configuration. </p>
+</div><h2 class="groupheader">Field Documentation</h2>
+<a class="anchor" id="a94f5f9c85756db0b4dc7bc0b19c7440c"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t CSL_DssVpOldiCfg::dataEnablePolarity</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Data Enable Polarity For valid values see <a class="el" href="csl__fvid2__data_types_8h.html#a9e9754a80a4e33aebaf391204a570723" title="Low Polarity. ">Fvid2_Polarity</a> </p>
+
+</div>
+</div>
+<a class="anchor" id="a0a2827a2b6a0402e988bc0aabf2d04f0"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t CSL_DssVpOldiCfg::dssBitDepth</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>DSS Bit Depth. This is used only in case of CSL_DSS_VP_OLDI_MAP_TYPE_A See <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#CSL_DssVpOldiBitDepth">CSL_DssVpOldiBitDepth</a> for valid values </p>
+
+</div>
+</div>
+<a class="anchor" id="a52a9e531691e023b7634991e3096fc1e"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t CSL_DssVpOldiCfg::oldiMapType</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>OLDI Map Type. See <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#CSL_DssVpOldiMapType">CSL_DssVpOldiMapType</a> for valid values </p>
+
+</div>
+</div>
+<hr/>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="csl__dss_video_port_8h.html">csl_dssVideoPort.h</a></li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/struct_dss___dctrl_adv_vp_params.html b/packages/ti/drv/dss/docs/doxygen/html/struct_dss___dctrl_adv_vp_params.html
--- /dev/null
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+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Dss_DctrlAdvVpParams Struct Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li class="current"><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="files.html"><span>Files</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow2" class="tabs2">
+ <ul class="tablist">
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="functions.html"><span>Data Fields</span></a></li>
+ </ul>
+ </div>
+</div><!-- top -->
+<div class="header">
+ <div class="summary">
+<a href="#pub-attribs">Data Fields</a> </div>
+ <div class="headertitle">
+<div class="title">Dss_DctrlAdvVpParams Struct Reference</div> </div>
+</div><!--header-->
+<div class="contents">
+
+<p>Structure containing advance Video Port information. This structure is used as an argument to IOCTL_DSS_DCTRL_SET_ADV_VP_PARAMS.
+ <a href="struct_dss___dctrl_adv_vp_params.html#details">More...</a></p>
+
+<p><code>#include <dss_dctrl.h></code></p>
+<table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
+Data Fields</h2></td></tr>
+<tr class="memitem:afd01ce9227b77bec352c157f1105b622"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___dctrl_adv_vp_params.html#afd01ce9227b77bec352c157f1105b622">vpId</a></td></tr>
+<tr class="separator:afd01ce9227b77bec352c157f1105b622"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a6f8a69ef5d888ab0efac61cd952b84e4"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_c_s_l___dss_vp_lcd_adv_signal_cfg.html">CSL_DssVpLcdAdvSignalCfg</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___dctrl_adv_vp_params.html#a6f8a69ef5d888ab0efac61cd952b84e4">lcdAdvSignalCfg</a></td></tr>
+<tr class="separator:a6f8a69ef5d888ab0efac61cd952b84e4"><td class="memSeparator" colspan="2"> </td></tr>
+</table>
+<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
+<div class="textblock"><p>Structure containing advance Video Port information. This structure is used as an argument to IOCTL_DSS_DCTRL_SET_ADV_VP_PARAMS. </p>
+</div><h2 class="groupheader">Field Documentation</h2>
+<a class="anchor" id="a6f8a69ef5d888ab0efac61cd952b84e4"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname"><a class="el" href="struct_c_s_l___dss_vp_lcd_adv_signal_cfg.html">CSL_DssVpLcdAdvSignalCfg</a> Dss_DctrlAdvVpParams::lcdAdvSignalCfg</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Advance Signal Configuration for the LCD. See <a class="el" href="struct_c_s_l___dss_vp_lcd_adv_signal_cfg.html">CSL_DssVpLcdAdvSignalCfg</a> for details </p>
+
+</div>
+</div>
+<a class="anchor" id="afd01ce9227b77bec352c157f1105b622"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t Dss_DctrlAdvVpParams::vpId</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Video Port Id. See <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#CSL_DssVpId">CSL_DssVpId</a> for values </p>
+
+</div>
+</div>
+<hr/>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="dss__dctrl_8h.html">dss_dctrl.h</a></li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/struct_dss___dctrl_global_dss_params.html b/packages/ti/drv/dss/docs/doxygen/html/struct_dss___dctrl_global_dss_params.html
--- /dev/null
@@ -0,0 +1,85 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Dss_DctrlGlobalDssParams Struct Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li class="current"><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="files.html"><span>Files</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow2" class="tabs2">
+ <ul class="tablist">
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="functions.html"><span>Data Fields</span></a></li>
+ </ul>
+ </div>
+</div><!-- top -->
+<div class="header">
+ <div class="summary">
+<a href="#pub-attribs">Data Fields</a> </div>
+ <div class="headertitle">
+<div class="title">Dss_DctrlGlobalDssParams Struct Reference</div> </div>
+</div><!--header-->
+<div class="contents">
+
+<p>Structure containing global DSS Configuration. This structure is used as an argument to IOCTL_DSS_DCTRL_SET_GLOBAL_DSS_PARAMS.
+ <a href="struct_dss___dctrl_global_dss_params.html#details">More...</a></p>
+
+<p><code>#include <dss_dctrl.h></code></p>
+<table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
+Data Fields</h2></td></tr>
+<tr class="memitem:af07803690960e450435f1d962bd6e82a"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_c_s_l___dss_global_m_flag_cfg.html">CSL_DssGlobalMFlagCfg</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___dctrl_global_dss_params.html#af07803690960e450435f1d962bd6e82a">globalMflagCfg</a></td></tr>
+<tr class="separator:af07803690960e450435f1d962bd6e82a"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a28fb2f34eb97b5d4d8980bcbb6135f8c"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_c_s_l___dss_cba_cfg.html">CSL_DssCbaCfg</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___dctrl_global_dss_params.html#a28fb2f34eb97b5d4d8980bcbb6135f8c">cbaCfg</a></td></tr>
+<tr class="separator:a28fb2f34eb97b5d4d8980bcbb6135f8c"><td class="memSeparator" colspan="2"> </td></tr>
+</table>
+<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
+<div class="textblock"><p>Structure containing global DSS Configuration. This structure is used as an argument to IOCTL_DSS_DCTRL_SET_GLOBAL_DSS_PARAMS. </p>
+</div><h2 class="groupheader">Field Documentation</h2>
+<a class="anchor" id="a28fb2f34eb97b5d4d8980bcbb6135f8c"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname"><a class="el" href="struct_c_s_l___dss_cba_cfg.html">CSL_DssCbaCfg</a> Dss_DctrlGlobalDssParams::cbaCfg</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>CBA Priority Configuration. See <a class="el" href="struct_c_s_l___dss_cba_cfg.html">CSL_DssCbaCfg</a> for details </p>
+
+</div>
+</div>
+<a class="anchor" id="af07803690960e450435f1d962bd6e82a"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname"><a class="el" href="struct_c_s_l___dss_global_m_flag_cfg.html">CSL_DssGlobalMFlagCfg</a> Dss_DctrlGlobalDssParams::globalMflagCfg</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Global Mflag Configuration. See <a class="el" href="struct_c_s_l___dss_global_m_flag_cfg.html">CSL_DssGlobalMFlagCfg</a> for details </p>
+
+</div>
+</div>
+<hr/>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="dss__dctrl_8h.html">dss_dctrl.h</a></li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/struct_dss___dctrl_lcd_blank_timing_params.html b/packages/ti/drv/dss/docs/doxygen/html/struct_dss___dctrl_lcd_blank_timing_params.html
--- /dev/null
@@ -0,0 +1,100 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Dss_DctrlLcdBlankTimingParams Struct Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li class="current"><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="files.html"><span>Files</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow2" class="tabs2">
+ <ul class="tablist">
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="functions.html"><span>Data Fields</span></a></li>
+ </ul>
+ </div>
+</div><!-- top -->
+<div class="header">
+ <div class="summary">
+<a href="#pub-attribs">Data Fields</a> </div>
+ <div class="headertitle">
+<div class="title">Dss_DctrlLcdBlankTimingParams Struct Reference</div> </div>
+</div><!--header-->
+<div class="contents">
+
+<p>Structure containing LCD Blank Timing Configuration. This structure is used as an argument to IOCTL_DSS_DCTRL_SET_LCD_BLANK_TIMING_PARAMS.
+ <a href="struct_dss___dctrl_lcd_blank_timing_params.html#details">More...</a></p>
+
+<p><code>#include <dss_dctrl.h></code></p>
+<table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
+Data Fields</h2></td></tr>
+<tr class="memitem:ae1b052eccedf552786588d1c7ae16172"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___dctrl_lcd_blank_timing_params.html#ae1b052eccedf552786588d1c7ae16172">vpId</a></td></tr>
+<tr class="separator:ae1b052eccedf552786588d1c7ae16172"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a7d98e8797f58bb69e6a0f639e749bb97"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___dctrl_lcd_blank_timing_params.html#a7d98e8797f58bb69e6a0f639e749bb97">dvoFormat</a></td></tr>
+<tr class="separator:a7d98e8797f58bb69e6a0f639e749bb97"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ab210add6d59769281c95f6d1bc8b9d76"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_c_s_l___dss_vp_lcd_blank_timing_cfg.html">CSL_DssVpLcdBlankTimingCfg</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___dctrl_lcd_blank_timing_params.html#ab210add6d59769281c95f6d1bc8b9d76">lcdBlankTimingCfg</a></td></tr>
+<tr class="separator:ab210add6d59769281c95f6d1bc8b9d76"><td class="memSeparator" colspan="2"> </td></tr>
+</table>
+<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
+<div class="textblock"><p>Structure containing LCD Blank Timing Configuration. This structure is used as an argument to IOCTL_DSS_DCTRL_SET_LCD_BLANK_TIMING_PARAMS. </p>
+</div><h2 class="groupheader">Field Documentation</h2>
+<a class="anchor" id="a7d98e8797f58bb69e6a0f639e749bb97"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t Dss_DctrlLcdBlankTimingParams::dvoFormat</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Digital output format. For valid values see <a class="el" href="csl__fvid2__data_types_8h.html#Fvid2_DVFormat">Fvid2_DVFormat</a> </p>
+
+</div>
+</div>
+<a class="anchor" id="ab210add6d59769281c95f6d1bc8b9d76"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname"><a class="el" href="struct_c_s_l___dss_vp_lcd_blank_timing_cfg.html">CSL_DssVpLcdBlankTimingCfg</a> Dss_DctrlLcdBlankTimingParams::lcdBlankTimingCfg</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Timing configuration for the LCD. See <a class="el" href="struct_c_s_l___dss_vp_lcd_blank_timing_cfg.html">CSL_DssVpLcdBlankTimingCfg</a> for details </p>
+
+</div>
+</div>
+<a class="anchor" id="ae1b052eccedf552786588d1c7ae16172"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t Dss_DctrlLcdBlankTimingParams::vpId</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Video Port Id. See <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#CSL_DssVpId">CSL_DssVpId</a> for values </p>
+
+</div>
+</div>
+<hr/>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="dss__dctrl_8h.html">dss_dctrl.h</a></li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/struct_dss___dctrl_oldi_params.html b/packages/ti/drv/dss/docs/doxygen/html/struct_dss___dctrl_oldi_params.html
--- /dev/null
@@ -0,0 +1,85 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Dss_DctrlOldiParams Struct Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li class="current"><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="files.html"><span>Files</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow2" class="tabs2">
+ <ul class="tablist">
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="functions.html"><span>Data Fields</span></a></li>
+ </ul>
+ </div>
+</div><!-- top -->
+<div class="header">
+ <div class="summary">
+<a href="#pub-attribs">Data Fields</a> </div>
+ <div class="headertitle">
+<div class="title">Dss_DctrlOldiParams Struct Reference</div> </div>
+</div><!--header-->
+<div class="contents">
+
+<p>Structure containing OLDI configuration. This structure is used as an argument to IOCTL_DSS_DCTRL_SET_OLDI_PARAMS.
+ <a href="struct_dss___dctrl_oldi_params.html#details">More...</a></p>
+
+<p><code>#include <dss_soc.h></code></p>
+<table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
+Data Fields</h2></td></tr>
+<tr class="memitem:a05de5db50e555596e3ec6402b2342bb4"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___dctrl_oldi_params.html#a05de5db50e555596e3ec6402b2342bb4">vpId</a></td></tr>
+<tr class="separator:a05de5db50e555596e3ec6402b2342bb4"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:adad012c98bd5cf3ce7cb164f57ba38cb"><td class="memItemLeft" align="right" valign="top">CSL_DssVpOldiCfg </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___dctrl_oldi_params.html#adad012c98bd5cf3ce7cb164f57ba38cb">oldiCfg</a></td></tr>
+<tr class="separator:adad012c98bd5cf3ce7cb164f57ba38cb"><td class="memSeparator" colspan="2"> </td></tr>
+</table>
+<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
+<div class="textblock"><p>Structure containing OLDI configuration. This structure is used as an argument to IOCTL_DSS_DCTRL_SET_OLDI_PARAMS. </p>
+</div><h2 class="groupheader">Field Documentation</h2>
+<a class="anchor" id="adad012c98bd5cf3ce7cb164f57ba38cb"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">CSL_DssVpOldiCfg Dss_DctrlOldiParams::oldiCfg</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>OLDI configuration. See CSL_DssVpOldiCfg for details </p>
+
+</div>
+</div>
+<a class="anchor" id="a05de5db50e555596e3ec6402b2342bb4"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t Dss_DctrlOldiParams::vpId</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Video Port Id. See <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#CSL_DssVpId">CSL_DssVpId</a> for values </p>
+
+</div>
+</div>
+<hr/>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="dss__soc_8h.html">dss_soc.h</a></li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/struct_dss___dctrl_overlay_layer_params.html b/packages/ti/drv/dss/docs/doxygen/html/struct_dss___dctrl_overlay_layer_params.html
--- /dev/null
@@ -0,0 +1,85 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Dss_DctrlOverlayLayerParams Struct Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li class="current"><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="files.html"><span>Files</span></a></li>
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+ </ul>
+ </div>
+</div><!-- top -->
+<div class="header">
+ <div class="summary">
+<a href="#pub-attribs">Data Fields</a> </div>
+ <div class="headertitle">
+<div class="title">Dss_DctrlOverlayLayerParams Struct Reference</div> </div>
+</div><!--header-->
+<div class="contents">
+
+<p>Structure containing Overlay layer information. This structure is used as an argument to IOCTL_DSS_DCTRL_SET_LAYER_PARAMS.
+ <a href="struct_dss___dctrl_overlay_layer_params.html#details">More...</a></p>
+
+<p><code>#include <dss_dctrl.h></code></p>
+<table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
+Data Fields</h2></td></tr>
+<tr class="memitem:af8e6714702ff114368a6b0fd566e3e65"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___dctrl_overlay_layer_params.html#af8e6714702ff114368a6b0fd566e3e65">overlayId</a></td></tr>
+<tr class="separator:af8e6714702ff114368a6b0fd566e3e65"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a8c4c1af551a7aa49f3e5eab31c7f3d26"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___dctrl_overlay_layer_params.html#a8c4c1af551a7aa49f3e5eab31c7f3d26">pipeLayerNum</a> [<a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gafbbd94228f58df3124b2bc9780379cea">CSL_DSS_VID_PIPE_ID_MAX</a>]</td></tr>
+<tr class="separator:a8c4c1af551a7aa49f3e5eab31c7f3d26"><td class="memSeparator" colspan="2"> </td></tr>
+</table>
+<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
+<div class="textblock"><p>Structure containing Overlay layer information. This structure is used as an argument to IOCTL_DSS_DCTRL_SET_LAYER_PARAMS. </p>
+</div><h2 class="groupheader">Field Documentation</h2>
+<a class="anchor" id="af8e6714702ff114368a6b0fd566e3e65"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t Dss_DctrlOverlayLayerParams::overlayId</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Overlay Id. See <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#CSL_DssOverlayId">CSL_DssOverlayId</a> for values </p>
+
+</div>
+</div>
+<a class="anchor" id="a8c4c1af551a7aa49f3e5eab31c7f3d26"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t Dss_DctrlOverlayLayerParams::pipeLayerNum[<a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gafbbd94228f58df3124b2bc9780379cea">CSL_DSS_VID_PIPE_ID_MAX</a>]</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Layer to which a particular Video Pipe Id is connected. For valid values see <a class="el" href="group___c_s_l___d_s_s_o_v_e_r_l_a_y.html#CSL_DssOverlayLayerNum">CSL_DssOverlayLayerNum</a> </p>
+
+</div>
+</div>
+<hr/>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="dss__dctrl_8h.html">dss_dctrl.h</a></li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/struct_dss___dctrl_overlay_params.html b/packages/ti/drv/dss/docs/doxygen/html/struct_dss___dctrl_overlay_params.html
--- /dev/null
@@ -0,0 +1,100 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Dss_DctrlOverlayParams Struct Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li class="current"><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="files.html"><span>Files</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow2" class="tabs2">
+ <ul class="tablist">
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="functions.html"><span>Data Fields</span></a></li>
+ </ul>
+ </div>
+</div><!-- top -->
+<div class="header">
+ <div class="summary">
+<a href="#pub-attribs">Data Fields</a> </div>
+ <div class="headertitle">
+<div class="title">Dss_DctrlOverlayParams Struct Reference</div> </div>
+</div><!--header-->
+<div class="contents">
+
+<p>Structure containing Overlay information. This structure is used as an argument to IOCTL_DSS_DCTRL_SET_OVERLAY_PARAMS.
+ <a href="struct_dss___dctrl_overlay_params.html#details">More...</a></p>
+
+<p><code>#include <dss_dctrl.h></code></p>
+<table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
+Data Fields</h2></td></tr>
+<tr class="memitem:a2883c49b828e361ecc83312668ef535d"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___dctrl_overlay_params.html#a2883c49b828e361ecc83312668ef535d">overlayId</a></td></tr>
+<tr class="separator:a2883c49b828e361ecc83312668ef535d"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:afad2eae0981ea3cbf8438264247c01b1"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___dctrl_overlay_params.html#afad2eae0981ea3cbf8438264247c01b1">colorbarEnable</a></td></tr>
+<tr class="separator:afad2eae0981ea3cbf8438264247c01b1"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:acaee7b8d01578e10237919957527a046"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_c_s_l___dss_overlay_cfg.html">CSL_DssOverlayCfg</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___dctrl_overlay_params.html#acaee7b8d01578e10237919957527a046">overlayCfg</a></td></tr>
+<tr class="separator:acaee7b8d01578e10237919957527a046"><td class="memSeparator" colspan="2"> </td></tr>
+</table>
+<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
+<div class="textblock"><p>Structure containing Overlay information. This structure is used as an argument to IOCTL_DSS_DCTRL_SET_OVERLAY_PARAMS. </p>
+</div><h2 class="groupheader">Field Documentation</h2>
+<a class="anchor" id="afad2eae0981ea3cbf8438264247c01b1"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t Dss_DctrlOverlayParams::colorbarEnable</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Overlay Color bar Enable. TRUE: Enable FALSE: Disable </p>
+
+</div>
+</div>
+<a class="anchor" id="acaee7b8d01578e10237919957527a046"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname"><a class="el" href="struct_c_s_l___dss_overlay_cfg.html">CSL_DssOverlayCfg</a> Dss_DctrlOverlayParams::overlayCfg</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Overlay Configuration. See <a class="el" href="struct_c_s_l___dss_overlay_cfg.html">CSL_DssOverlayCfg</a> for details </p>
+
+</div>
+</div>
+<a class="anchor" id="a2883c49b828e361ecc83312668ef535d"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t Dss_DctrlOverlayParams::overlayId</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Overlay Id. See <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#CSL_DssOverlayId">CSL_DssOverlayId</a> for values </p>
+
+</div>
+</div>
+<hr/>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="dss__dctrl_8h.html">dss_dctrl.h</a></li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/struct_dss___dctrl_path_info.html b/packages/ti/drv/dss/docs/doxygen/html/struct_dss___dctrl_path_info.html
--- /dev/null
@@ -0,0 +1,85 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Dss_DctrlPathInfo Struct Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li class="current"><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="files.html"><span>Files</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow2" class="tabs2">
+ <ul class="tablist">
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="functions.html"><span>Data Fields</span></a></li>
+ </ul>
+ </div>
+</div><!-- top -->
+<div class="header">
+ <div class="summary">
+<a href="#pub-attribs">Data Fields</a> </div>
+ <div class="headertitle">
+<div class="title">Dss_DctrlPathInfo Struct Reference</div> </div>
+</div><!--header-->
+<div class="contents">
+
+<p>Structure containing DSS path information. This structure is used as an argument to IOCTL_DSS_DCTRL_SET_PATH. This IOCTL takes the array of edges connected between nodes.
+ <a href="struct_dss___dctrl_path_info.html#details">More...</a></p>
+
+<p><code>#include <dss_dctrl.h></code></p>
+<table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
+Data Fields</h2></td></tr>
+<tr class="memitem:a86805ff6cd957de13ee114445fc2a316"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___dctrl_path_info.html#a86805ff6cd957de13ee114445fc2a316">numEdges</a></td></tr>
+<tr class="separator:a86805ff6cd957de13ee114445fc2a316"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a8f2ebc06f24bf439b9b82bed9c70b8fd"><td class="memItemLeft" align="right" valign="top">Fvid2_GraphEdgeInfo </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___dctrl_path_info.html#a8f2ebc06f24bf439b9b82bed9c70b8fd">edgeInfo</a> [<a class="el" href="dss__soc_8h.html#a8dbb4dd2e4cfdb12f6d01c6ddcd923e0">DSS_DCTRL_MAX_EDGES</a>]</td></tr>
+<tr class="separator:a8f2ebc06f24bf439b9b82bed9c70b8fd"><td class="memSeparator" colspan="2"> </td></tr>
+</table>
+<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
+<div class="textblock"><p>Structure containing DSS path information. This structure is used as an argument to IOCTL_DSS_DCTRL_SET_PATH. This IOCTL takes the array of edges connected between nodes. </p>
+</div><h2 class="groupheader">Field Documentation</h2>
+<a class="anchor" id="a8f2ebc06f24bf439b9b82bed9c70b8fd"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">Fvid2_GraphEdgeInfo Dss_DctrlPathInfo::edgeInfo[<a class="el" href="dss__soc_8h.html#a8dbb4dd2e4cfdb12f6d01c6ddcd923e0">DSS_DCTRL_MAX_EDGES</a>]</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>List of edges connecting DSS modules. Display controller parse these edges and enables/disables input/output path in the appropriate DSS module. This edge tells which module is connected to which module enabling output in edge start module and input in edge end module. </p>
+
+</div>
+</div>
+<a class="anchor" id="a86805ff6cd957de13ee114445fc2a316"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t Dss_DctrlPathInfo::numEdges</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Number edge in the edgeInfo array </p>
+
+</div>
+</div>
+<hr/>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="dss__dctrl_8h.html">dss_dctrl.h</a></li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/struct_dss___dctrl_region_safety_chk_cfg.html b/packages/ti/drv/dss/docs/doxygen/html/struct_dss___dctrl_region_safety_chk_cfg.html
--- /dev/null
@@ -0,0 +1,100 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Dss_DctrlRegionSafetyChkCfg Struct Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li class="current"><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="files.html"><span>Files</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow2" class="tabs2">
+ <ul class="tablist">
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="functions.html"><span>Data Fields</span></a></li>
+ </ul>
+ </div>
+</div><!-- top -->
+<div class="header">
+ <div class="summary">
+<a href="#pub-attribs">Data Fields</a> </div>
+ <div class="headertitle">
+<div class="title">Dss_DctrlRegionSafetyChkCfg Struct Reference</div> </div>
+</div><!--header-->
+<div class="contents">
+
+<p>Structure containing Safety Check configuration for a particular region.
+ <a href="struct_dss___dctrl_region_safety_chk_cfg.html#details">More...</a></p>
+
+<p><code>#include <dss_dctrl.h></code></p>
+<table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
+Data Fields</h2></td></tr>
+<tr class="memitem:a1fce7a9f3745d77fc11cac0b45bd7ae0"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___dctrl_region_safety_chk_cfg.html#a1fce7a9f3745d77fc11cac0b45bd7ae0">safetyRegionEnable</a></td></tr>
+<tr class="separator:a1fce7a9f3745d77fc11cac0b45bd7ae0"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a33766617818233c722d23b49daf3a1b1"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___dctrl_region_safety_chk_cfg.html#a33766617818233c722d23b49daf3a1b1">referenceSign</a></td></tr>
+<tr class="separator:a33766617818233c722d23b49daf3a1b1"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:aba94499a93c5fcbcf17aac03978b7692"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_c_s_l___dss_safety_chk_cfg.html">CSL_DssSafetyChkCfg</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___dctrl_region_safety_chk_cfg.html#aba94499a93c5fcbcf17aac03978b7692">safetyChkCfg</a></td></tr>
+<tr class="separator:aba94499a93c5fcbcf17aac03978b7692"><td class="memSeparator" colspan="2"> </td></tr>
+</table>
+<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
+<div class="textblock"><p>Structure containing Safety Check configuration for a particular region. </p>
+</div><h2 class="groupheader">Field Documentation</h2>
+<a class="anchor" id="a33766617818233c722d23b49daf3a1b1"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t Dss_DctrlRegionSafetyChkCfg::referenceSign</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Reference Safety Signature for Data Correctness Check </p>
+
+</div>
+</div>
+<a class="anchor" id="aba94499a93c5fcbcf17aac03978b7692"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname"><a class="el" href="struct_c_s_l___dss_safety_chk_cfg.html">CSL_DssSafetyChkCfg</a> Dss_DctrlRegionSafetyChkCfg::safetyChkCfg</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Safety Check Configuration. See <a class="el" href="struct_c_s_l___dss_safety_chk_cfg.html">CSL_DssSafetyChkCfg</a> for details </p>
+
+</div>
+</div>
+<a class="anchor" id="a1fce7a9f3745d77fc11cac0b45bd7ae0"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t Dss_DctrlRegionSafetyChkCfg::safetyRegionEnable</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Whether to enable region or not </p>
+
+</div>
+</div>
+<hr/>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="dss__dctrl_8h.html">dss_dctrl.h</a></li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/struct_dss___dctrl_sync_lost_cb_params.html b/packages/ti/drv/dss/docs/doxygen/html/struct_dss___dctrl_sync_lost_cb_params.html
--- /dev/null
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+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Dss_DctrlSyncLostCbParams Struct Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li class="current"><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="files.html"><span>Files</span></a></li>
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+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
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+ </ul>
+ </div>
+</div><!-- top -->
+<div class="header">
+ <div class="summary">
+<a href="#pub-attribs">Data Fields</a> </div>
+ <div class="headertitle">
+<div class="title">Dss_DctrlSyncLostCbParams Struct Reference</div> </div>
+</div><!--header-->
+<div class="contents">
+
+<p>Structure containing Sync Lost callback parameters. This structure is used as an argument to IOCTL_DSS_DCTRL_REGISTER_SYNCLOST_CB.
+ <a href="struct_dss___dctrl_sync_lost_cb_params.html#details">More...</a></p>
+
+<p><code>#include <dss_dctrl.h></code></p>
+<table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
+Data Fields</h2></td></tr>
+<tr class="memitem:a61ef10a6d3eba7bc313a97aa0030a235"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___dctrl_sync_lost_cb_params.html#a61ef10a6d3eba7bc313a97aa0030a235">vpId</a></td></tr>
+<tr class="separator:a61ef10a6d3eba7bc313a97aa0030a235"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a5c2ae7356eec440301d5ae9015e0f33a"><td class="memItemLeft" align="right" valign="top"><a class="el" href="dss__dctrl_8h.html#adc02df6de7a3d5940da55838ee464701">Dss_DctrlSyncLostCbFxn</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___dctrl_sync_lost_cb_params.html#a5c2ae7356eec440301d5ae9015e0f33a">syncLostCbFxn</a></td></tr>
+<tr class="separator:a5c2ae7356eec440301d5ae9015e0f33a"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a018ed0ef2544b8f52207dc5799238854"><td class="memItemLeft" align="right" valign="top">void * </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___dctrl_sync_lost_cb_params.html#a018ed0ef2544b8f52207dc5799238854">appData</a></td></tr>
+<tr class="separator:a018ed0ef2544b8f52207dc5799238854"><td class="memSeparator" colspan="2"> </td></tr>
+</table>
+<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
+<div class="textblock"><p>Structure containing Sync Lost callback parameters. This structure is used as an argument to IOCTL_DSS_DCTRL_REGISTER_SYNCLOST_CB. </p>
+</div><h2 class="groupheader">Field Documentation</h2>
+<a class="anchor" id="a018ed0ef2544b8f52207dc5799238854"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">void* Dss_DctrlSyncLostCbParams::appData</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Private data of application </p>
+
+</div>
+</div>
+<a class="anchor" id="a5c2ae7356eec440301d5ae9015e0f33a"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname"><a class="el" href="dss__dctrl_8h.html#adc02df6de7a3d5940da55838ee464701">Dss_DctrlSyncLostCbFxn</a> Dss_DctrlSyncLostCbParams::syncLostCbFxn</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Sync lost callback function </p>
+
+</div>
+</div>
+<a class="anchor" id="a61ef10a6d3eba7bc313a97aa0030a235"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t Dss_DctrlSyncLostCbParams::vpId</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Video Port Id. See <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#CSL_DssVpId">CSL_DssVpId</a> for values </p>
+
+</div>
+</div>
+<hr/>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="dss__dctrl_8h.html">dss_dctrl.h</a></li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/struct_dss___dctrl_vp_csc_coeff.html b/packages/ti/drv/dss/docs/doxygen/html/struct_dss___dctrl_vp_csc_coeff.html
--- /dev/null
@@ -0,0 +1,100 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Dss_DctrlVpCscCoeff Struct Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li class="current"><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="files.html"><span>Files</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow2" class="tabs2">
+ <ul class="tablist">
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="functions.html"><span>Data Fields</span></a></li>
+ </ul>
+ </div>
+</div><!-- top -->
+<div class="header">
+ <div class="summary">
+<a href="#pub-attribs">Data Fields</a> </div>
+ <div class="headertitle">
+<div class="title">Dss_DctrlVpCscCoeff Struct Reference</div> </div>
+</div><!--header-->
+<div class="contents">
+
+<p>Structure containing Video Port CSC information. This structure is used as an argument to IOCTL_DSS_DCTRL_SET_VP_CSC_COEFF.
+ <a href="struct_dss___dctrl_vp_csc_coeff.html#details">More...</a></p>
+
+<p><code>#include <dss_dctrl.h></code></p>
+<table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
+Data Fields</h2></td></tr>
+<tr class="memitem:a203077028ae50d9ca4db3c325d40dc1b"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___dctrl_vp_csc_coeff.html#a203077028ae50d9ca4db3c325d40dc1b">vpId</a></td></tr>
+<tr class="separator:a203077028ae50d9ca4db3c325d40dc1b"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ae353e0bd890dee8e7a8eeddf408ffc64"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___dctrl_vp_csc_coeff.html#ae353e0bd890dee8e7a8eeddf408ffc64">cscPos</a></td></tr>
+<tr class="separator:ae353e0bd890dee8e7a8eeddf408ffc64"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ae178eec62d495ae8ec2e0e5cc5e70e65"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_c_s_l___dss_csc_coeff.html">CSL_DssCscCoeff</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___dctrl_vp_csc_coeff.html#ae178eec62d495ae8ec2e0e5cc5e70e65">cscCoeff</a></td></tr>
+<tr class="separator:ae178eec62d495ae8ec2e0e5cc5e70e65"><td class="memSeparator" colspan="2"> </td></tr>
+</table>
+<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
+<div class="textblock"><p>Structure containing Video Port CSC information. This structure is used as an argument to IOCTL_DSS_DCTRL_SET_VP_CSC_COEFF. </p>
+</div><h2 class="groupheader">Field Documentation</h2>
+<a class="anchor" id="ae178eec62d495ae8ec2e0e5cc5e70e65"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname"><a class="el" href="struct_c_s_l___dss_csc_coeff.html">CSL_DssCscCoeff</a> Dss_DctrlVpCscCoeff::cscCoeff</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Video Port CSC coefficients. See <a class="el" href="struct_c_s_l___dss_csc_coeff.html">CSL_DssCscCoeff</a> for details </p>
+
+</div>
+</div>
+<a class="anchor" id="ae353e0bd890dee8e7a8eeddf408ffc64"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t Dss_DctrlVpCscCoeff::cscPos</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Position of CSC block wrt GAMMA module. Refer <a class="el" href="group___c_s_l___d_s_s_v_i_d_e_o_p_o_r_t.html#CSL_DssVpCscPos">CSL_DssVpCscPos</a> for values </p>
+
+</div>
+</div>
+<a class="anchor" id="a203077028ae50d9ca4db3c325d40dc1b"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t Dss_DctrlVpCscCoeff::vpId</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Video Port Id. See <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#CSL_DssVpId">CSL_DssVpId</a> for values </p>
+
+</div>
+</div>
+<hr/>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="dss__dctrl_8h.html">dss_dctrl.h</a></li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/struct_dss___dctrl_vp_error_stats.html b/packages/ti/drv/dss/docs/doxygen/html/struct_dss___dctrl_vp_error_stats.html
--- /dev/null
@@ -0,0 +1,115 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Dss_DctrlVpErrorStats Struct Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li class="current"><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="files.html"><span>Files</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow2" class="tabs2">
+ <ul class="tablist">
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="functions.html"><span>Data Fields</span></a></li>
+ </ul>
+ </div>
+</div><!-- top -->
+<div class="header">
+ <div class="summary">
+<a href="#pub-attribs">Data Fields</a> </div>
+ <div class="headertitle">
+<div class="title">Dss_DctrlVpErrorStats Struct Reference</div> </div>
+</div><!--header-->
+<div class="contents">
+
+<p>Structure containing Error Stats of Video Port. This structure is used as an argument to IOCTL_DSS_DCTRL_GET_VP_ERROR_STATS.
+ <a href="struct_dss___dctrl_vp_error_stats.html#details">More...</a></p>
+
+<p><code>#include <dss_dctrl.h></code></p>
+<table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
+Data Fields</h2></td></tr>
+<tr class="memitem:a557f21aa6cf21d93cbb30621de72ecb0"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___dctrl_vp_error_stats.html#a557f21aa6cf21d93cbb30621de72ecb0">vpId</a></td></tr>
+<tr class="separator:a557f21aa6cf21d93cbb30621de72ecb0"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:af272b85724ab489cac4f6ae36797dd15"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___dctrl_vp_error_stats.html#af272b85724ab489cac4f6ae36797dd15">syncLost</a></td></tr>
+<tr class="separator:af272b85724ab489cac4f6ae36797dd15"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a9a3c57243d5e6622e5bd4fff8ab95cd4"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___dctrl_vp_error_stats.html#a9a3c57243d5e6622e5bd4fff8ab95cd4">safetyViolation</a> [<a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga514efc84b40d7147969434b2d5cff2fe">CSL_DSS_SAFETY_REGION_MAX</a>]</td></tr>
+<tr class="separator:a9a3c57243d5e6622e5bd4fff8ab95cd4"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a54b7302e5365b28c21f1678322860d3f"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___dctrl_vp_error_stats.html#a54b7302e5365b28c21f1678322860d3f">securityViolation</a></td></tr>
+<tr class="separator:a54b7302e5365b28c21f1678322860d3f"><td class="memSeparator" colspan="2"> </td></tr>
+</table>
+<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
+<div class="textblock"><p>Structure containing Error Stats of Video Port. This structure is used as an argument to IOCTL_DSS_DCTRL_GET_VP_ERROR_STATS. </p>
+</div><h2 class="groupheader">Field Documentation</h2>
+<a class="anchor" id="a9a3c57243d5e6622e5bd4fff8ab95cd4"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t Dss_DctrlVpErrorStats::safetyViolation[<a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga514efc84b40d7147969434b2d5cff2fe">CSL_DSS_SAFETY_REGION_MAX</a>]</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Safety Violation Count </p>
+
+</div>
+</div>
+<a class="anchor" id="a54b7302e5365b28c21f1678322860d3f"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t Dss_DctrlVpErrorStats::securityViolation</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Security Violation Count </p>
+
+</div>
+</div>
+<a class="anchor" id="af272b85724ab489cac4f6ae36797dd15"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t Dss_DctrlVpErrorStats::syncLost</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>SyncLost Error Count of the LCD </p>
+
+</div>
+</div>
+<a class="anchor" id="a557f21aa6cf21d93cbb30621de72ecb0"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t Dss_DctrlVpErrorStats::vpId</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Video Port Id. See <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#CSL_DssVpId">CSL_DssVpId</a> for values </p>
+
+</div>
+</div>
+<hr/>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="dss__dctrl_8h.html">dss_dctrl.h</a></li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/struct_dss___dctrl_vp_params.html b/packages/ti/drv/dss/docs/doxygen/html/struct_dss___dctrl_vp_params.html
--- /dev/null
@@ -0,0 +1,115 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Dss_DctrlVpParams Struct Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li class="current"><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="files.html"><span>Files</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow2" class="tabs2">
+ <ul class="tablist">
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="functions.html"><span>Data Fields</span></a></li>
+ </ul>
+ </div>
+</div><!-- top -->
+<div class="header">
+ <div class="summary">
+<a href="#pub-attribs">Data Fields</a> </div>
+ <div class="headertitle">
+<div class="title">Dss_DctrlVpParams Struct Reference</div> </div>
+</div><!--header-->
+<div class="contents">
+
+<p>Structure containing Video Port information. This structure is used as an argument to IOCTL_DSS_DCTRL_SET_VP_PARAMS.
+ <a href="struct_dss___dctrl_vp_params.html#details">More...</a></p>
+
+<p><code>#include <dss_dctrl.h></code></p>
+<table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
+Data Fields</h2></td></tr>
+<tr class="memitem:aa76e94e775ed4a9146ebc8fc937c904e"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___dctrl_vp_params.html#aa76e94e775ed4a9146ebc8fc937c904e">vpId</a></td></tr>
+<tr class="separator:aa76e94e775ed4a9146ebc8fc937c904e"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ab85222c9535dd65a0148c5df4ebf4d2f"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_c_s_l___dss_vp_lcd_op_timing_cfg.html">CSL_DssVpLcdOpTimingCfg</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___dctrl_vp_params.html#ab85222c9535dd65a0148c5df4ebf4d2f">lcdOpTimingCfg</a></td></tr>
+<tr class="separator:ab85222c9535dd65a0148c5df4ebf4d2f"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a40f589e08e3d00ac44640cc27ffd20dd"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_c_s_l___dss_vp_lcd_signal_polarity_cfg.html">CSL_DssVpLcdSignalPolarityCfg</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___dctrl_vp_params.html#a40f589e08e3d00ac44640cc27ffd20dd">lcdPolarityCfg</a></td></tr>
+<tr class="separator:a40f589e08e3d00ac44640cc27ffd20dd"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a705586424b3d0c7af64f8bae7d95fcba"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_c_s_l___dss_vp_lcd_tdm_cfg.html">CSL_DssVpLcdTdmCfg</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___dctrl_vp_params.html#a705586424b3d0c7af64f8bae7d95fcba">lcdTdmCfg</a></td></tr>
+<tr class="separator:a705586424b3d0c7af64f8bae7d95fcba"><td class="memSeparator" colspan="2"> </td></tr>
+</table>
+<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
+<div class="textblock"><p>Structure containing Video Port information. This structure is used as an argument to IOCTL_DSS_DCTRL_SET_VP_PARAMS. </p>
+</div><h2 class="groupheader">Field Documentation</h2>
+<a class="anchor" id="ab85222c9535dd65a0148c5df4ebf4d2f"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname"><a class="el" href="struct_c_s_l___dss_vp_lcd_op_timing_cfg.html">CSL_DssVpLcdOpTimingCfg</a> Dss_DctrlVpParams::lcdOpTimingCfg</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Timing configuration for the LCD output. See <a class="el" href="struct_c_s_l___dss_vp_lcd_op_timing_cfg.html">CSL_DssVpLcdOpTimingCfg</a> for details </p>
+
+</div>
+</div>
+<a class="anchor" id="a40f589e08e3d00ac44640cc27ffd20dd"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname"><a class="el" href="struct_c_s_l___dss_vp_lcd_signal_polarity_cfg.html">CSL_DssVpLcdSignalPolarityCfg</a> Dss_DctrlVpParams::lcdPolarityCfg</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>LCD Polarity Configuration. See <a class="el" href="struct_c_s_l___dss_vp_lcd_signal_polarity_cfg.html">CSL_DssVpLcdSignalPolarityCfg</a> for details </p>
+
+</div>
+</div>
+<a class="anchor" id="a705586424b3d0c7af64f8bae7d95fcba"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname"><a class="el" href="struct_c_s_l___dss_vp_lcd_tdm_cfg.html">CSL_DssVpLcdTdmCfg</a> Dss_DctrlVpParams::lcdTdmCfg</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>LCD TDM Configuration. See <a class="el" href="struct_c_s_l___dss_vp_lcd_tdm_cfg.html">CSL_DssVpLcdTdmCfg</a> for details </p>
+
+</div>
+</div>
+<a class="anchor" id="aa76e94e775ed4a9146ebc8fc937c904e"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t Dss_DctrlVpParams::vpId</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Video Port Id. See <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#CSL_DssVpId">CSL_DssVpId</a> for values </p>
+
+</div>
+</div>
+<hr/>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="dss__dctrl_8h.html">dss_dctrl.h</a></li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/struct_dss___dctrl_vp_safety_chk_params.html b/packages/ti/drv/dss/docs/doxygen/html/struct_dss___dctrl_vp_safety_chk_params.html
--- /dev/null
@@ -0,0 +1,100 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Dss_DctrlVpSafetyChkParams Struct Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li class="current"><a href="annotated.html"><span>Data Structures</span></a></li>
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+</div><!-- top -->
+<div class="header">
+ <div class="summary">
+<a href="#pub-attribs">Data Fields</a> </div>
+ <div class="headertitle">
+<div class="title">Dss_DctrlVpSafetyChkParams Struct Reference</div> </div>
+</div><!--header-->
+<div class="contents">
+
+<p>Structure containing Safety Check configuration of Video Port. This structure is used as an argument to IOCTL_DSS_DCTRL_SET_VP_SAFETY_CHK_PARAMS.
+ <a href="struct_dss___dctrl_vp_safety_chk_params.html#details">More...</a></p>
+
+<p><code>#include <dss_dctrl.h></code></p>
+<table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
+Data Fields</h2></td></tr>
+<tr class="memitem:a034f526bd2e786a118ebb9a84e5c5cb8"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___dctrl_vp_safety_chk_params.html#a034f526bd2e786a118ebb9a84e5c5cb8">vpId</a></td></tr>
+<tr class="separator:a034f526bd2e786a118ebb9a84e5c5cb8"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a673816f47183a4e18606ec70a01292ec"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___dctrl_vp_safety_chk_params.html#a673816f47183a4e18606ec70a01292ec">safetySignSeedVal</a></td></tr>
+<tr class="separator:a673816f47183a4e18606ec70a01292ec"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a79a3554cac97f602e452fc5ae125288e"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_dss___dctrl_region_safety_chk_cfg.html">Dss_DctrlRegionSafetyChkCfg</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___dctrl_vp_safety_chk_params.html#a79a3554cac97f602e452fc5ae125288e">vpSafetyChkCfg</a> [<a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga514efc84b40d7147969434b2d5cff2fe">CSL_DSS_SAFETY_REGION_MAX</a>]</td></tr>
+<tr class="separator:a79a3554cac97f602e452fc5ae125288e"><td class="memSeparator" colspan="2"> </td></tr>
+</table>
+<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
+<div class="textblock"><p>Structure containing Safety Check configuration of Video Port. This structure is used as an argument to IOCTL_DSS_DCTRL_SET_VP_SAFETY_CHK_PARAMS. </p>
+</div><h2 class="groupheader">Field Documentation</h2>
+<a class="anchor" id="a673816f47183a4e18606ec70a01292ec"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t Dss_DctrlVpSafetyChkParams::safetySignSeedVal</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Safety Signature Seed Value </p>
+
+</div>
+</div>
+<a class="anchor" id="a034f526bd2e786a118ebb9a84e5c5cb8"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t Dss_DctrlVpSafetyChkParams::vpId</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Video Port Id. See <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#CSL_DssVpId">CSL_DssVpId</a> for values </p>
+
+</div>
+</div>
+<a class="anchor" id="a79a3554cac97f602e452fc5ae125288e"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname"><a class="el" href="struct_dss___dctrl_region_safety_chk_cfg.html">Dss_DctrlRegionSafetyChkCfg</a> Dss_DctrlVpSafetyChkParams::vpSafetyChkCfg[<a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga514efc84b40d7147969434b2d5cff2fe">CSL_DSS_SAFETY_REGION_MAX</a>]</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Safety Check Configuration. See <a class="el" href="struct_dss___dctrl_region_safety_chk_cfg.html">Dss_DctrlRegionSafetyChkCfg</a> for details </p>
+
+</div>
+</div>
+<hr/>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="dss__dctrl_8h.html">dss_dctrl.h</a></li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/struct_dss___disp_buf_prgm_cb_params.html b/packages/ti/drv/dss/docs/doxygen/html/struct_dss___disp_buf_prgm_cb_params.html
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+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Dss_DispBufPrgmCbParams Struct Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
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+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
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+ <ul class="tablist">
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+</div><!-- top -->
+<div class="header">
+ <div class="summary">
+<a href="#pub-attribs">Data Fields</a> </div>
+ <div class="headertitle">
+<div class="title">Dss_DispBufPrgmCbParams Struct Reference</div> </div>
+</div><!--header-->
+<div class="contents">
+
+<p>Structure containing display buffer program callback parameters. This structure is used as an argument to IOCTL_DSS_DISP_REGISTER_BUF_PRGM_CB.
+ <a href="struct_dss___disp_buf_prgm_cb_params.html#details">More...</a></p>
+
+<p><code>#include <dss_disp.h></code></p>
+<table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
+Data Fields</h2></td></tr>
+<tr class="memitem:a44001b7a082865cef75594b3cb8853b6"><td class="memItemLeft" align="right" valign="top"><a class="el" href="dss__disp_8h.html#a3f3415894bf0e54f2d06f24ea22c602e">Dss_DispBufPrgmCbFxn</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___disp_buf_prgm_cb_params.html#a44001b7a082865cef75594b3cb8853b6">bufPrgmCbFxn</a></td></tr>
+<tr class="separator:a44001b7a082865cef75594b3cb8853b6"><td class="memSeparator" colspan="2"> </td></tr>
+</table>
+<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
+<div class="textblock"><p>Structure containing display buffer program callback parameters. This structure is used as an argument to IOCTL_DSS_DISP_REGISTER_BUF_PRGM_CB. </p>
+</div><h2 class="groupheader">Field Documentation</h2>
+<a class="anchor" id="a44001b7a082865cef75594b3cb8853b6"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname"><a class="el" href="dss__disp_8h.html#a3f3415894bf0e54f2d06f24ea22c602e">Dss_DispBufPrgmCbFxn</a> Dss_DispBufPrgmCbParams::bufPrgmCbFxn</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Application callback function to be called just before programming the hardware. A value of NULL will un-register the callback. </p>
+
+</div>
+</div>
+<hr/>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="dss__disp_8h.html">dss_disp.h</a></li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/struct_dss___disp_create_params.html b/packages/ti/drv/dss/docs/doxygen/html/struct_dss___disp_create_params.html
--- /dev/null
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+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Dss_DispCreateParams Struct Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
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+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
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+ <ul class="tablist">
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+ </ul>
+ </div>
+</div><!-- top -->
+<div class="header">
+ <div class="summary">
+<a href="#pub-attribs">Data Fields</a> </div>
+ <div class="headertitle">
+<div class="title">Dss_DispCreateParams Struct Reference</div> </div>
+</div><!--header-->
+<div class="contents">
+
+<p>Structure containing display driver create arguments, used when calling Fvid2_create().
+ <a href="struct_dss___disp_create_params.html#details">More...</a></p>
+
+<p><code>#include <dss_disp.h></code></p>
+<table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
+Data Fields</h2></td></tr>
+<tr class="memitem:ab8366600abad325065cdf8fac4de2a77"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___disp_create_params.html#ab8366600abad325065cdf8fac4de2a77">periodicCbEnable</a></td></tr>
+<tr class="separator:ab8366600abad325065cdf8fac4de2a77"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a1b1d68b7e5feb7f8c40fb925db6a2ce9"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___disp_create_params.html#a1b1d68b7e5feb7f8c40fb925db6a2ce9">progPipeVsyncEnable</a></td></tr>
+<tr class="separator:a1b1d68b7e5feb7f8c40fb925db6a2ce9"><td class="memSeparator" colspan="2"> </td></tr>
+</table>
+<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
+<div class="textblock"><p>Structure containing display driver create arguments, used when calling Fvid2_create(). </p>
+</div><h2 class="groupheader">Field Documentation</h2>
+<a class="anchor" id="ab8366600abad325065cdf8fac4de2a77"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t Dss_DispCreateParams::periodicCbEnable</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Periodic Callback Enable. Possible values are TRUE or FALSE. TRUE: User callback passed during FVID2 create is called periodically. For progressive display, this interval is equal to VSYNC interval. For interlaced display, this interval is equal to twice the VSYNC interval as frames (two fields) are queued to the driver FALSE: User callback passed during FVID2 create is called only if one or more frames (requests) are available in the driver output queue for the application to dequeue </p>
+
+</div>
+</div>
+<a class="anchor" id="a1b1d68b7e5feb7f8c40fb925db6a2ce9"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t Dss_DispCreateParams::progPipeVsyncEnable</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Program Pipe at Vsync Enable. Possible values are TRUE or FALSE. TRUE: Pipe Registers will be updated only during VSYNC context. This essentially implies that start and stop will be dummy. The actual buffer programming will happen at next VSYNC and hence there will be one frame delay. In case of queue operation the frame will always be pushed to request queue. This means buffer will not be updated immediately even when driver is repeating frames in safe to push context. FALSE: This is the default behavior. Start and stop will be agnostic to Vsync and happen immediately. In case of queue operation, driver will display the new frame if there was frame repeat and queue is done during safe to push period. </p>
+
+</div>
+</div>
+<hr/>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="dss__disp_8h.html">dss_disp.h</a></li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/struct_dss___disp_create_status.html b/packages/ti/drv/dss/docs/doxygen/html/struct_dss___disp_create_status.html
--- /dev/null
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+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Dss_DispCreateStatus Struct Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li class="current"><a href="annotated.html"><span>Data Structures</span></a></li>
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+ </ul>
+ </div>
+</div><!-- top -->
+<div class="header">
+ <div class="summary">
+<a href="#pub-attribs">Data Fields</a> </div>
+ <div class="headertitle">
+<div class="title">Dss_DispCreateStatus Struct Reference</div> </div>
+</div><!--header-->
+<div class="contents">
+
+<p>Structure containing create status for the display driver. This should be passed as a status argument while creating the driver.
+ <a href="struct_dss___disp_create_status.html#details">More...</a></p>
+
+<p><code>#include <dss_disp.h></code></p>
+<table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
+Data Fields</h2></td></tr>
+<tr class="memitem:a46416dc8db8540d785740d4b3c41f052"><td class="memItemLeft" align="right" valign="top">int32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___disp_create_status.html#a46416dc8db8540d785740d4b3c41f052">retVal</a></td></tr>
+<tr class="separator:a46416dc8db8540d785740d4b3c41f052"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ae7ddd0a663c8bcbaf6ddb9339f3257cf"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___disp_create_status.html#ae7ddd0a663c8bcbaf6ddb9339f3257cf">standard</a></td></tr>
+<tr class="separator:ae7ddd0a663c8bcbaf6ddb9339f3257cf"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:aee56647a1d80812a6b4e6ceb62bcf568"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___disp_create_status.html#aee56647a1d80812a6b4e6ceb62bcf568">dispWidth</a></td></tr>
+<tr class="separator:aee56647a1d80812a6b4e6ceb62bcf568"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a077cf565fe573dff029d69cf3d7e9bea"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___disp_create_status.html#a077cf565fe573dff029d69cf3d7e9bea">dispHeight</a></td></tr>
+<tr class="separator:a077cf565fe573dff029d69cf3d7e9bea"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a12b0ad905934ec8007bcd821cf0deff7"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___disp_create_status.html#a12b0ad905934ec8007bcd821cf0deff7">minNumPrimeBuf</a></td></tr>
+<tr class="separator:a12b0ad905934ec8007bcd821cf0deff7"><td class="memSeparator" colspan="2"> </td></tr>
+</table>
+<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
+<div class="textblock"><p>Structure containing create status for the display driver. This should be passed as a status argument while creating the driver. </p>
+</div><h2 class="groupheader">Field Documentation</h2>
+<a class="anchor" id="a077cf565fe573dff029d69cf3d7e9bea"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t Dss_DispCreateStatus::dispHeight</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Height of the display at the Video Port in lines </p>
+
+</div>
+</div>
+<a class="anchor" id="aee56647a1d80812a6b4e6ceb62bcf568"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t Dss_DispCreateStatus::dispWidth</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Width of the display at the Video Port in pixels </p>
+
+</div>
+</div>
+<a class="anchor" id="a12b0ad905934ec8007bcd821cf0deff7"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t Dss_DispCreateStatus::minNumPrimeBuf</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Minimum number of buffers to prime before starting display operation </p>
+
+</div>
+</div>
+<a class="anchor" id="a46416dc8db8540d785740d4b3c41f052"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">int32_t Dss_DispCreateStatus::retVal</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Return status of create call </p>
+
+</div>
+</div>
+<a class="anchor" id="ae7ddd0a663c8bcbaf6ddb9339f3257cf"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t Dss_DispCreateStatus::standard</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Video Port standard like 1080p, 720p, etc. to which the video pipe is connected. For valid values see <a class="el" href="csl__fvid2__data_types_8h.html#aaa2667d105d557f254c20b87534ed4b6" title="720x480 30FPS interlaced NTSC standard. ">Fvid2_Standard</a> </p>
+
+</div>
+</div>
+<hr/>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="dss__disp_8h.html">dss_disp.h</a></li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/struct_dss___disp_current_status.html b/packages/ti/drv/dss/docs/doxygen/html/struct_dss___disp_current_status.html
--- /dev/null
@@ -0,0 +1,145 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Dss_DispCurrentStatus Struct Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li class="current"><a href="annotated.html"><span>Data Structures</span></a></li>
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+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
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+ </ul>
+ </div>
+</div><!-- top -->
+<div class="header">
+ <div class="summary">
+<a href="#pub-attribs">Data Fields</a> </div>
+ <div class="headertitle">
+<div class="title">Dss_DispCurrentStatus Struct Reference</div> </div>
+</div><!--header-->
+<div class="contents">
+
+<p>Structure containing current status of the display driver. This structure is used as an argument to IOCTL_DSS_DISP_GET_CURRENT_STATUS.
+ <a href="struct_dss___disp_current_status.html#details">More...</a></p>
+
+<p><code>#include <dss_disp.h></code></p>
+<table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
+Data Fields</h2></td></tr>
+<tr class="memitem:a92cf9e8cc3729ad69f5e7240d3598d01"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___disp_current_status.html#a92cf9e8cc3729ad69f5e7240d3598d01">queueCount</a></td></tr>
+<tr class="separator:a92cf9e8cc3729ad69f5e7240d3598d01"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ab165778deecd58c934909dcf35571b03"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___disp_current_status.html#ab165778deecd58c934909dcf35571b03">dequeueCount</a></td></tr>
+<tr class="separator:ab165778deecd58c934909dcf35571b03"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ad530ba229be8e4fab5d0dcdfcfdffc75"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___disp_current_status.html#ad530ba229be8e4fab5d0dcdfcfdffc75">dispFrmCount</a></td></tr>
+<tr class="separator:ad530ba229be8e4fab5d0dcdfcfdffc75"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:af4c9a477ce0debeae4dbcd653e1d3c18"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___disp_current_status.html#af4c9a477ce0debeae4dbcd653e1d3c18">repeatFrmCount</a></td></tr>
+<tr class="separator:af4c9a477ce0debeae4dbcd653e1d3c18"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:abe96e5d704939af373e8a533790d5875"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___disp_current_status.html#abe96e5d704939af373e8a533790d5875">underflowCount</a></td></tr>
+<tr class="separator:abe96e5d704939af373e8a533790d5875"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a2de8eed6f459af208ad159c02ebfbab0"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___disp_current_status.html#a2de8eed6f459af208ad159c02ebfbab0">safetyViolationCount</a></td></tr>
+<tr class="separator:a2de8eed6f459af208ad159c02ebfbab0"><td class="memSeparator" colspan="2"> </td></tr>
+</table>
+<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
+<div class="textblock"><p>Structure containing current status of the display driver. This structure is used as an argument to IOCTL_DSS_DISP_GET_CURRENT_STATUS. </p>
+</div><h2 class="groupheader">Field Documentation</h2>
+<a class="anchor" id="ab165778deecd58c934909dcf35571b03"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t Dss_DispCurrentStatus::dequeueCount</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Counter to keep track of how many requests are dequeued from the driver. Note: This counter will be reset at the time of driver create </p>
+
+</div>
+</div>
+<a class="anchor" id="ad530ba229be8e4fab5d0dcdfcfdffc75"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t Dss_DispCurrentStatus::dispFrmCount</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Counter to keep track of how many frames are displayed. For interlaced display, this is half of the actual field display. Note: This counter will be reset at the time of display start </p>
+
+</div>
+</div>
+<a class="anchor" id="a92cf9e8cc3729ad69f5e7240d3598d01"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t Dss_DispCurrentStatus::queueCount</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Counter to keep track of how many requests are queued to the driver. Note: This counter will be reset at the time of driver create </p>
+
+</div>
+</div>
+<a class="anchor" id="af4c9a477ce0debeae4dbcd653e1d3c18"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t Dss_DispCurrentStatus::repeatFrmCount</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Counter to keep track of how many frames are repeated when the application fails to queue buffer at the display rate. Note: This counter will be reset at the time of display start </p>
+
+</div>
+</div>
+<a class="anchor" id="a2de8eed6f459af208ad159c02ebfbab0"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t Dss_DispCurrentStatus::safetyViolationCount</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Counter to keep track of number of safety violations Note: This counter will be reset at the time of driver create </p>
+
+</div>
+</div>
+<a class="anchor" id="abe96e5d704939af373e8a533790d5875"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t Dss_DispCurrentStatus::underflowCount</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Counter to keep track of number of underflows Note: This counter will be reset at the time of driver create </p>
+
+</div>
+</div>
+<hr/>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="dss__disp_8h.html">dss_disp.h</a></li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/struct_dss___disp_params.html b/packages/ti/drv/dss/docs/doxygen/html/struct_dss___disp_params.html
--- /dev/null
@@ -0,0 +1,136 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Dss_DispParams Struct Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li class="current"><a href="annotated.html"><span>Data Structures</span></a></li>
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+ <div id="navrow2" class="tabs2">
+ <ul class="tablist">
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="functions.html"><span>Data Fields</span></a></li>
+ </ul>
+ </div>
+</div><!-- top -->
+<div class="header">
+ <div class="summary">
+<a href="#pub-attribs">Data Fields</a> </div>
+ <div class="headertitle">
+<div class="title">Dss_DispParams Struct Reference</div> </div>
+</div><!--header-->
+<div class="contents">
+
+<p>Structure containing DSS parameters. This structure is used as an argument to IOCTL_DSS_DISP_SET_DSS_PARAMS.
+ <a href="struct_dss___disp_params.html#details">More...</a></p>
+
+<p><code>#include <dss_disp.h></code></p>
+<table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
+Data Fields</h2></td></tr>
+<tr class="memitem:a48165b146fa02698a76b378930ad9a3f"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_c_s_l___dss_vid_pipe_cfg.html">CSL_DssVidPipeCfg</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___disp_params.html#a48165b146fa02698a76b378930ad9a3f">pipeCfg</a></td></tr>
+<tr class="separator:a48165b146fa02698a76b378930ad9a3f"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a80d78d43a05b928cf2b6bd7c009f4ae6"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_c_s_l___dss_vid_pipe_dma_cfg.html">CSL_DssVidPipeDmaCfg</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___disp_params.html#a80d78d43a05b928cf2b6bd7c009f4ae6">dmaCfg</a></td></tr>
+<tr class="separator:a80d78d43a05b928cf2b6bd7c009f4ae6"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a3a34d97aedf973f3eeaca5d9469667ca"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_c_s_l___dss_vid_pipe_alpha_cfg.html">CSL_DssVidPipeAlphaCfg</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___disp_params.html#a3a34d97aedf973f3eeaca5d9469667ca">alphaCfg</a></td></tr>
+<tr class="separator:a3a34d97aedf973f3eeaca5d9469667ca"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a706397a3b18a877996fbf8f8276ab2e4"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_c_s_l___dss_vid_pipe_v_c1_cfg.html">CSL_DssVidPipeVC1Cfg</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___disp_params.html#a706397a3b18a877996fbf8f8276ab2e4">vc1Cfg</a></td></tr>
+<tr class="separator:a706397a3b18a877996fbf8f8276ab2e4"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ac26e2dd60bc2eb1f9a1ef92f5b8374c8"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_fvid2___pos_config.html">Fvid2_PosConfig</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___disp_params.html#ac26e2dd60bc2eb1f9a1ef92f5b8374c8">layerPos</a></td></tr>
+<tr class="separator:ac26e2dd60bc2eb1f9a1ef92f5b8374c8"><td class="memSeparator" colspan="2"> </td></tr>
+</table>
+<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
+<div class="textblock"><p>Structure containing DSS parameters. This structure is used as an argument to IOCTL_DSS_DISP_SET_DSS_PARAMS. </p>
+</div><h2 class="groupheader">Field Documentation</h2>
+<a class="anchor" id="a3a34d97aedf973f3eeaca5d9469667ca"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname"><a class="el" href="struct_c_s_l___dss_vid_pipe_alpha_cfg.html">CSL_DssVidPipeAlphaCfg</a> Dss_DispParams::alphaCfg</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Video pipeline alpha configuration </p>
+
+</div>
+</div>
+<a class="anchor" id="a80d78d43a05b928cf2b6bd7c009f4ae6"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname"><a class="el" href="struct_c_s_l___dss_vid_pipe_dma_cfg.html">CSL_DssVidPipeDmaCfg</a> Dss_DispParams::dmaCfg</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Video pipeline DMA configuration </p>
+
+</div>
+</div>
+<a class="anchor" id="ac26e2dd60bc2eb1f9a1ef92f5b8374c8"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname"><a class="el" href="struct_fvid2___pos_config.html">Fvid2_PosConfig</a> Dss_DispParams::layerPos</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Position of the video buffer described using <a class="el" href="struct_fvid2___pos_config.html" title="Structure containing position configuration - used in VCOMP and CIG. ">Fvid2_PosConfig</a></p>
+<p><b>startX</b>:<br/>
+ X position of the video buffer The first pixel on the left of the screen has the X-position 0 <br/>
+</p>
+<p><b>startY</b>:<br/>
+ Y position of the video buffer The line at the top has the Y-position 0 <br/>
+ </p>
+
+</div>
+</div>
+<a class="anchor" id="a48165b146fa02698a76b378930ad9a3f"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname"><a class="el" href="struct_c_s_l___dss_vid_pipe_cfg.html">CSL_DssVidPipeCfg</a> Dss_DispParams::pipeCfg</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Video pipeline configuration </p>
+
+</div>
+</div>
+<a class="anchor" id="a706397a3b18a877996fbf8f8276ab2e4"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname"><a class="el" href="struct_c_s_l___dss_vid_pipe_v_c1_cfg.html">CSL_DssVidPipeVC1Cfg</a> Dss_DispParams::vc1Cfg</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Video pipeline VC1 configuration </p>
+
+</div>
+</div>
+<hr/>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="dss__disp_8h.html">dss_disp.h</a></li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/struct_dss___disp_pipe_mflag_params.html b/packages/ti/drv/dss/docs/doxygen/html/struct_dss___disp_pipe_mflag_params.html
--- /dev/null
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+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Dss_DispPipeMflagParams Struct Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li class="current"><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="files.html"><span>Files</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow2" class="tabs2">
+ <ul class="tablist">
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="functions.html"><span>Data Fields</span></a></li>
+ </ul>
+ </div>
+</div><!-- top -->
+<div class="header">
+ <div class="summary">
+<a href="#pub-attribs">Data Fields</a> </div>
+ <div class="headertitle">
+<div class="title">Dss_DispPipeMflagParams Struct Reference</div> </div>
+</div><!--header-->
+<div class="contents">
+
+<p>Structure containing Video Pipe Mflag Information. This structure is used as an argument to IOCTL_DSS_DISP_SET_PIPE_MFLAG_PARAMS.
+ <a href="struct_dss___disp_pipe_mflag_params.html#details">More...</a></p>
+
+<p><code>#include <dss_disp.h></code></p>
+<table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
+Data Fields</h2></td></tr>
+<tr class="memitem:a006a172bac6001d494ac6f1901d56f1e"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_c_s_l___dss_vid_pipe_m_flag_cfg.html">CSL_DssVidPipeMFlagCfg</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___disp_pipe_mflag_params.html#a006a172bac6001d494ac6f1901d56f1e">mflagCfg</a></td></tr>
+<tr class="separator:a006a172bac6001d494ac6f1901d56f1e"><td class="memSeparator" colspan="2"> </td></tr>
+</table>
+<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
+<div class="textblock"><p>Structure containing Video Pipe Mflag Information. This structure is used as an argument to IOCTL_DSS_DISP_SET_PIPE_MFLAG_PARAMS. </p>
+</div><h2 class="groupheader">Field Documentation</h2>
+<a class="anchor" id="a006a172bac6001d494ac6f1901d56f1e"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname"><a class="el" href="struct_c_s_l___dss_vid_pipe_m_flag_cfg.html">CSL_DssVidPipeMFlagCfg</a> Dss_DispPipeMflagParams::mflagCfg</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Video pipeline mflag configuration. See <a class="el" href="struct_c_s_l___dss_vid_pipe_m_flag_cfg.html" title="DSS Video Pipe MFLAG Config parameters. ">CSL_DssVidPipeMFlagCfg</a> for details </p>
+
+</div>
+</div>
+<hr/>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="dss__disp_8h.html">dss_disp.h</a></li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/struct_dss___disp_pipe_prgm_cb_params.html b/packages/ti/drv/dss/docs/doxygen/html/struct_dss___disp_pipe_prgm_cb_params.html
--- /dev/null
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+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Dss_DispPipePrgmCbParams Struct Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
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+ <td bgcolor="red"><img src="../titagline.gif"></td>
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+<!-- Generated by Doxygen 1.8.6 -->
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+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
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+ </ul>
+ </div>
+</div><!-- top -->
+<div class="header">
+ <div class="summary">
+<a href="#pub-attribs">Data Fields</a> </div>
+ <div class="headertitle">
+<div class="title">Dss_DispPipePrgmCbParams Struct Reference</div> </div>
+</div><!--header-->
+<div class="contents">
+
+<p>Structure containing video pipe program callback parameters. This structure is used as an argument to IOCTL_DSS_DISP_REGISTER_PIPE_PRGM_CB.
+ <a href="struct_dss___disp_pipe_prgm_cb_params.html#details">More...</a></p>
+
+<p><code>#include <dss_disp.h></code></p>
+<table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
+Data Fields</h2></td></tr>
+<tr class="memitem:a3665e053d0ee61b9555b4640f4e1325f"><td class="memItemLeft" align="right" valign="top"><a class="el" href="dss__disp_8h.html#a4ccdd634499058281998bcc9a7af0555">Dss_DispPipePrgmCbFxn</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___disp_pipe_prgm_cb_params.html#a3665e053d0ee61b9555b4640f4e1325f">pipePrgmCbFxn</a></td></tr>
+<tr class="separator:a3665e053d0ee61b9555b4640f4e1325f"><td class="memSeparator" colspan="2"> </td></tr>
+</table>
+<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
+<div class="textblock"><p>Structure containing video pipe program callback parameters. This structure is used as an argument to IOCTL_DSS_DISP_REGISTER_PIPE_PRGM_CB. </p>
+</div><h2 class="groupheader">Field Documentation</h2>
+<a class="anchor" id="a3665e053d0ee61b9555b4640f4e1325f"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname"><a class="el" href="dss__disp_8h.html#a4ccdd634499058281998bcc9a7af0555">Dss_DispPipePrgmCbFxn</a> Dss_DispPipePrgmCbParams::pipePrgmCbFxn</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Application callback function to be called just after programming the hardware. A value of NULL will un-register the callback. </p>
+
+</div>
+</div>
+<hr/>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="dss__disp_8h.html">dss_disp.h</a></li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/struct_dss___disp_pipe_safety_chk_params.html b/packages/ti/drv/dss/docs/doxygen/html/struct_dss___disp_pipe_safety_chk_params.html
--- /dev/null
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+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Dss_DispPipeSafetyChkParams Struct Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
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+ <ul class="tablist">
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+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
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+ </ul>
+ </div>
+</div><!-- top -->
+<div class="header">
+ <div class="summary">
+<a href="#pub-attribs">Data Fields</a> </div>
+ <div class="headertitle">
+<div class="title">Dss_DispPipeSafetyChkParams Struct Reference</div> </div>
+</div><!--header-->
+<div class="contents">
+
+<p>Structure containing Safety Check configuration of Video Port. This structure is used as an argument to IOCTL_DSS_DISP_SET_PIPE_SAFETY_CHK_PARAMS.
+ <a href="struct_dss___disp_pipe_safety_chk_params.html#details">More...</a></p>
+
+<p><code>#include <dss_disp.h></code></p>
+<table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
+Data Fields</h2></td></tr>
+<tr class="memitem:a806bdd67b98f5ad01597e70ea7c2ce9c"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___disp_pipe_safety_chk_params.html#a806bdd67b98f5ad01597e70ea7c2ce9c">safetySignSeedVal</a></td></tr>
+<tr class="separator:a806bdd67b98f5ad01597e70ea7c2ce9c"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a959fe56578ad3537011559f97fbd4661"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___disp_pipe_safety_chk_params.html#a959fe56578ad3537011559f97fbd4661">referenceSign</a></td></tr>
+<tr class="separator:a959fe56578ad3537011559f97fbd4661"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a1d2da23596678e366eddaad75e2382c3"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_c_s_l___dss_safety_chk_cfg.html">CSL_DssSafetyChkCfg</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___disp_pipe_safety_chk_params.html#a1d2da23596678e366eddaad75e2382c3">pipeSafetyChkCfg</a></td></tr>
+<tr class="separator:a1d2da23596678e366eddaad75e2382c3"><td class="memSeparator" colspan="2"> </td></tr>
+</table>
+<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
+<div class="textblock"><p>Structure containing Safety Check configuration of Video Port. This structure is used as an argument to IOCTL_DSS_DISP_SET_PIPE_SAFETY_CHK_PARAMS. </p>
+</div><h2 class="groupheader">Field Documentation</h2>
+<a class="anchor" id="a1d2da23596678e366eddaad75e2382c3"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname"><a class="el" href="struct_c_s_l___dss_safety_chk_cfg.html">CSL_DssSafetyChkCfg</a> Dss_DispPipeSafetyChkParams::pipeSafetyChkCfg</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Safety Check Configuration. See <a class="el" href="struct_c_s_l___dss_safety_chk_cfg.html">CSL_DssSafetyChkCfg</a> for details </p>
+
+</div>
+</div>
+<a class="anchor" id="a959fe56578ad3537011559f97fbd4661"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t Dss_DispPipeSafetyChkParams::referenceSign</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Reference Safety Signature for Data Correctness Check </p>
+
+</div>
+</div>
+<a class="anchor" id="a806bdd67b98f5ad01597e70ea7c2ce9c"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t Dss_DispPipeSafetyChkParams::safetySignSeedVal</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Safety Signature Seed Value </p>
+
+</div>
+</div>
+<hr/>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="dss__disp_8h.html">dss_disp.h</a></li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/struct_dss___disp_rt_params.html b/packages/ti/drv/dss/docs/doxygen/html/struct_dss___disp_rt_params.html
--- /dev/null
@@ -0,0 +1,115 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Dss_DispRtParams Struct Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
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+ </ul>
+ </div>
+</div><!-- top -->
+<div class="header">
+ <div class="summary">
+<a href="#pub-attribs">Data Fields</a> </div>
+ <div class="headertitle">
+<div class="title">Dss_DispRtParams Struct Reference</div> </div>
+</div><!--header-->
+<div class="contents">
+
+<p>Structure containing run time configuration of the display driver. This needs to be passed along with frame list to update any supported run time parameters.
+ <a href="struct_dss___disp_rt_params.html#details">More...</a></p>
+
+<p><code>#include <dss_disp.h></code></p>
+<table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
+Data Fields</h2></td></tr>
+<tr class="memitem:a29259476cb78ef269ef5827d5c59e11e"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_fvid2___pos_config.html">Fvid2_PosConfig</a> * </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___disp_rt_params.html#a29259476cb78ef269ef5827d5c59e11e">posCfg</a></td></tr>
+<tr class="separator:a29259476cb78ef269ef5827d5c59e11e"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a6cc436c9916749a865525d66388c7133"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_dss___frame_rt_params.html">Dss_FrameRtParams</a> * </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___disp_rt_params.html#a6cc436c9916749a865525d66388c7133">inFrmParams</a></td></tr>
+<tr class="separator:a6cc436c9916749a865525d66388c7133"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a8190a88390e7d3d6327d53c73381a997"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_dss___frame_rt_params.html">Dss_FrameRtParams</a> * </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___disp_rt_params.html#a8190a88390e7d3d6327d53c73381a997">outFrmParams</a></td></tr>
+<tr class="separator:a8190a88390e7d3d6327d53c73381a997"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ac3d56cce7d4cae6e8baee8e4784b77b6"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_dss___sc_rt_params.html">Dss_ScRtParams</a> * </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___disp_rt_params.html#ac3d56cce7d4cae6e8baee8e4784b77b6">scParams</a></td></tr>
+<tr class="separator:ac3d56cce7d4cae6e8baee8e4784b77b6"><td class="memSeparator" colspan="2"> </td></tr>
+</table>
+<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
+<div class="textblock"><p>Structure containing run time configuration of the display driver. This needs to be passed along with frame list to update any supported run time parameters. </p>
+</div><h2 class="groupheader">Field Documentation</h2>
+<a class="anchor" id="a6cc436c9916749a865525d66388c7133"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname"><a class="el" href="struct_dss___frame_rt_params.html">Dss_FrameRtParams</a>* Dss_DispRtParams::inFrmParams</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>RT Params for input frame. This parameter is used to change the frame width and height at runtime. Note that this is used only when the buffer dimension is smaller than the LCD size. When changing the size, the application should ensure that the startX/startY + frame size doesn't exceed the display resolution. Refer to <a class="el" href="struct_dss___frame_rt_params.html" title="Structure containing run time configuration per frame. ">Dss_FrameRtParams</a> for details. Note: Pass NULL if no change is required </p>
+
+</div>
+</div>
+<a class="anchor" id="a8190a88390e7d3d6327d53c73381a997"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname"><a class="el" href="struct_dss___frame_rt_params.html">Dss_FrameRtParams</a>* Dss_DispRtParams::outFrmParams</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>RT Params for output frame i.e. output of video pipeline. Only Width and height is valid in this structure. Refer to <a class="el" href="struct_dss___frame_rt_params.html" title="Structure containing run time configuration per frame. ">Dss_FrameRtParams</a> for details. Note: Pass NULL if no change is required </p>
+
+</div>
+</div>
+<a class="anchor" id="a29259476cb78ef269ef5827d5c59e11e"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname"><a class="el" href="struct_fvid2___pos_config.html">Fvid2_PosConfig</a>* Dss_DispRtParams::posCfg</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Position Configuration used to position the Frame in the Overlay. Refer to <a class="el" href="struct_fvid2___pos_config.html" title="Structure containing position configuration - used in VCOMP and CIG. ">Fvid2_PosConfig</a> for details. Note: Pass NULL if no change is required </p>
+
+</div>
+</div>
+<a class="anchor" id="ac3d56cce7d4cae6e8baee8e4784b77b6"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname"><a class="el" href="struct_dss___sc_rt_params.html">Dss_ScRtParams</a>* Dss_DispRtParams::scParams</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>RT Params for scaler. Refer to <a class="el" href="struct_dss___sc_rt_params.html" title="Structure containing run time scaler configuration. ">Dss_ScRtParams</a> for details. Note: Pass NULL if no change is required </p>
+
+</div>
+</div>
+<hr/>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="dss__disp_8h.html">dss_disp.h</a></li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/struct_dss___disp_under_flow_cb_params.html b/packages/ti/drv/dss/docs/doxygen/html/struct_dss___disp_under_flow_cb_params.html
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+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Dss_DispUnderFlowCbParams Struct Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li class="current"><a href="annotated.html"><span>Data Structures</span></a></li>
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+ <ul class="tablist">
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
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+ </ul>
+ </div>
+</div><!-- top -->
+<div class="header">
+ <div class="summary">
+<a href="#pub-attribs">Data Fields</a> </div>
+ <div class="headertitle">
+<div class="title">Dss_DispUnderFlowCbParams Struct Reference</div> </div>
+</div><!--header-->
+<div class="contents">
+
+<p>Structure containing pipe under flow callback parameters. This structure is used as an argument to IOCTL_DSS_DISP_REGISTER_PIPE_UNDERFLOW_CB.
+ <a href="struct_dss___disp_under_flow_cb_params.html#details">More...</a></p>
+
+<p><code>#include <dss_disp.h></code></p>
+<table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
+Data Fields</h2></td></tr>
+<tr class="memitem:a60686aad091a413400037ab52ee52c5a"><td class="memItemLeft" align="right" valign="top"><a class="el" href="dss__disp_8h.html#a14c7b8d97214b5c092eb8702e24522a1">Dss_DispUnderFlowCbFxn</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___disp_under_flow_cb_params.html#a60686aad091a413400037ab52ee52c5a">underFlowCbFxn</a></td></tr>
+<tr class="separator:a60686aad091a413400037ab52ee52c5a"><td class="memSeparator" colspan="2"> </td></tr>
+</table>
+<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
+<div class="textblock"><p>Structure containing pipe under flow callback parameters. This structure is used as an argument to IOCTL_DSS_DISP_REGISTER_PIPE_UNDERFLOW_CB. </p>
+</div><h2 class="groupheader">Field Documentation</h2>
+<a class="anchor" id="a60686aad091a413400037ab52ee52c5a"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname"><a class="el" href="dss__disp_8h.html#a14c7b8d97214b5c092eb8702e24522a1">Dss_DispUnderFlowCbFxn</a> Dss_DispUnderFlowCbParams::underFlowCbFxn</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Sync lost callback function </p>
+
+</div>
+</div>
+<hr/>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="dss__disp_8h.html">dss_disp.h</a></li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/struct_dss___frame_rt_params.html b/packages/ti/drv/dss/docs/doxygen/html/struct_dss___frame_rt_params.html
--- /dev/null
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+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
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+<title>Dss_FrameRtParams Struct Reference</title>
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+<div class="header">
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+<a href="#pub-attribs">Data Fields</a> </div>
+ <div class="headertitle">
+<div class="title">Dss_FrameRtParams Struct Reference</div> </div>
+</div><!--header-->
+<div class="contents">
+
+<p>Structure containing run time configuration per frame.
+ <a href="struct_dss___frame_rt_params.html#details">More...</a></p>
+
+<p><code>#include <dss_disp.h></code></p>
+<table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
+Data Fields</h2></td></tr>
+<tr class="memitem:a12e945cb05d7fb6f7732c22b7a5f314c"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___frame_rt_params.html#a12e945cb05d7fb6f7732c22b7a5f314c">width</a></td></tr>
+<tr class="separator:a12e945cb05d7fb6f7732c22b7a5f314c"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ab174627123752cb63bbd8450275ccc5c"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___frame_rt_params.html#ab174627123752cb63bbd8450275ccc5c">height</a></td></tr>
+<tr class="separator:ab174627123752cb63bbd8450275ccc5c"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a4dab0431dffbdbcb94b06e5cb27c7f06"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___frame_rt_params.html#a4dab0431dffbdbcb94b06e5cb27c7f06">pitch</a> [<a class="el" href="csl__fvid2__data_types_8h.html#aef0d63f7f96514278ebda30f1c0bec74">FVID2_MAX_PLANES</a>]</td></tr>
+<tr class="separator:a4dab0431dffbdbcb94b06e5cb27c7f06"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ae6280dd0f1eabe05ba89d7f81d9c2975"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___frame_rt_params.html#ae6280dd0f1eabe05ba89d7f81d9c2975">dataFormat</a></td></tr>
+<tr class="separator:ae6280dd0f1eabe05ba89d7f81d9c2975"><td class="memSeparator" colspan="2"> </td></tr>
+</table>
+<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
+<div class="textblock"><p>Structure containing run time configuration per frame. </p>
+</div><h2 class="groupheader">Field Documentation</h2>
+<a class="anchor" id="ae6280dd0f1eabe05ba89d7f81d9c2975"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t Dss_FrameRtParams::dataFormat</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Frame data Format. For valid values see <a class="el" href="csl__fvid2__data_types_8h.html#a9f5096b017d15ffecdcc0990fd1b031a" title="YUV 422 Interleaved format - UYVY. ">Fvid2_DataFormat</a>. </p>
+
+</div>
+</div>
+<a class="anchor" id="ab174627123752cb63bbd8450275ccc5c"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t Dss_FrameRtParams::height</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Height of the video frame or field in lines. </p>
+
+</div>
+</div>
+<a class="anchor" id="a4dab0431dffbdbcb94b06e5cb27c7f06"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t Dss_FrameRtParams::pitch[<a class="el" href="csl__fvid2__data_types_8h.html#aef0d63f7f96514278ebda30f1c0bec74">FVID2_MAX_PLANES</a>]</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Pitch in bytes for each of the sub-buffers. This represents the difference between two consecutive line addresses in bytes. This is irrespective of whether the video is interlaced or progressive and whether the fields are merged or separated for interlaced video. </p>
+
+</div>
+</div>
+<a class="anchor" id="a12e945cb05d7fb6f7732c22b7a5f314c"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t Dss_FrameRtParams::width</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Width of the video frame or field in pixels. </p>
+
+</div>
+</div>
+<hr/>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="dss__disp_8h.html">dss_disp.h</a></li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/struct_dss___init_params.html b/packages/ti/drv/dss/docs/doxygen/html/struct_dss___init_params.html
--- /dev/null
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+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Dss_InitParams Struct Reference</title>
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+<link href="tabs.css" rel="stylesheet" type="text/css">
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+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
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+</div><!-- top -->
+<div class="header">
+ <div class="summary">
+<a href="#pub-attribs">Data Fields</a> </div>
+ <div class="headertitle">
+<div class="title">Dss_InitParams Struct Reference<div class="ingroups"><a class="el" href="group___d_s_s.html">DSS Driver</a></div></div> </div>
+</div><!--header-->
+<div class="contents">
+
+<p>DSS initialization parameters.
+ <a href="struct_dss___init_params.html#details">More...</a></p>
+
+<p><code>#include <dss.h></code></p>
+<table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
+Data Fields</h2></td></tr>
+<tr class="memitem:aa8b798f4f03fcfb8bd59b04999d448a8"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_dss___soc_params.html">Dss_SocParams</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___init_params.html#aa8b798f4f03fcfb8bd59b04999d448a8">socParams</a></td></tr>
+<tr class="separator:aa8b798f4f03fcfb8bd59b04999d448a8"><td class="memSeparator" colspan="2"> </td></tr>
+</table>
+<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
+<div class="textblock"><p>DSS initialization parameters. </p>
+</div><h2 class="groupheader">Field Documentation</h2>
+<a class="anchor" id="aa8b798f4f03fcfb8bd59b04999d448a8"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname"><a class="el" href="struct_dss___soc_params.html">Dss_SocParams</a> Dss_InitParams::socParams</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>SoC parameters. Refer <a class="el" href="struct_dss___soc_params.html" title="DSS SOC parameters. ">Dss_SocParams</a> for details </p>
+
+</div>
+</div>
+<hr/>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="dss_8h.html">dss.h</a></li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/struct_dss___irq_params.html b/packages/ti/drv/dss/docs/doxygen/html/struct_dss___irq_params.html
--- /dev/null
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+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Dss_IrqParams Struct Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
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+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
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+ </ul>
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+</div><!-- top -->
+<div class="header">
+ <div class="summary">
+<a href="#pub-attribs">Data Fields</a> </div>
+ <div class="headertitle">
+<div class="title">Dss_IrqParams Struct Reference</div> </div>
+</div><!--header-->
+<div class="contents">
+
+<p>Structure containing DSS interrupt information. Events should be enabled only for available Video Ports and Video Pipes.
+ <a href="struct_dss___irq_params.html#details">More...</a></p>
+
+<p><code>#include <dss_soc.h></code></p>
+<table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
+Data Fields</h2></td></tr>
+<tr class="memitem:ad0b38c26a215ee1ef19d7a7dd31fdc59"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___irq_params.html#ad0b38c26a215ee1ef19d7a7dd31fdc59">dssCommonRegionId</a></td></tr>
+<tr class="separator:ad0b38c26a215ee1ef19d7a7dd31fdc59"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:aa506ef07fa2b7d3396f82dc52e46c2bd"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___irq_params.html#aa506ef07fa2b7d3396f82dc52e46c2bd">numValidIrq</a></td></tr>
+<tr class="separator:aa506ef07fa2b7d3396f82dc52e46c2bd"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:aa3ef349676a4f3e5ff139616501c4a25"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___irq_params.html#aa3ef349676a4f3e5ff139616501c4a25">irqNum</a> [<a class="el" href="dss__soc_8h.html#a655e39bd46b2a70609bd7d6c878f394f">DSS_EVT_MGR_INST_ID_MAX</a>]</td></tr>
+<tr class="separator:aa3ef349676a4f3e5ff139616501c4a25"><td class="memSeparator" colspan="2"> </td></tr>
+</table>
+<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
+<div class="textblock"><p>Structure containing DSS interrupt information. Events should be enabled only for available Video Ports and Video Pipes. </p>
+</div><h2 class="groupheader">Field Documentation</h2>
+<a class="anchor" id="ad0b38c26a215ee1ef19d7a7dd31fdc59"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t Dss_IrqParams::dssCommonRegionId</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>DSS Common Region Id. There are multiple common regions in DSS hardware each having IRQ aggregation registers and IRQ generator. This enables fully independent monitoring/control of the interrupt events by different hosts. User can decide which common region to use. By default region 0 will be used. Refer <a class="el" href="group___c_s_l___d_s_s_t_o_p.html#CSL_DssCommRegId">CSL_DssCommRegId</a> for values </p>
+
+</div>
+</div>
+<a class="anchor" id="aa3ef349676a4f3e5ff139616501c4a25"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t Dss_IrqParams::irqNum[<a class="el" href="dss__soc_8h.html#a655e39bd46b2a70609bd7d6c878f394f">DSS_EVT_MGR_INST_ID_MAX</a>]</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>DSS interrupt numbers. This will enable to configure different interrupt numbers. This will be initialized to default values as specified in the DssInitParams_init function. User may override these values if allowed.</p>
+<p>Note: Driver will only register for the specified interrupt numbers. If needed the corresponding crossbar mapping for the device interrupt should be done by the application. </p>
+
+</div>
+</div>
+<a class="anchor" id="aa506ef07fa2b7d3396f82dc52e46c2bd"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t Dss_IrqParams::numValidIrq</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Number of valid DSS interrupts. There can be multiple interrupts in DSS hardware. This specifies number of valid IRQs in below array. </p>
+
+</div>
+</div>
+<hr/>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="dss__soc_8h.html">dss_soc.h</a></li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/struct_dss___rm_info.html b/packages/ti/drv/dss/docs/doxygen/html/struct_dss___rm_info.html
--- /dev/null
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+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Dss_RmInfo Struct Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
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+ <li class="current"><a href="annotated.html"><span>Data Structures</span></a></li>
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+ </ul>
+ </div>
+</div><!-- top -->
+<div class="header">
+ <div class="summary">
+<a href="#pub-attribs">Data Fields</a> </div>
+ <div class="headertitle">
+<div class="title">Dss_RmInfo Struct Reference</div> </div>
+</div><!--header-->
+<div class="contents">
+
+<p>Structure containing resources manager information. This enables display sharing between two different softwares.
+ <a href="struct_dss___rm_info.html#details">More...</a></p>
+
+<p><code>#include <dss_soc.h></code></p>
+<table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
+Data Fields</h2></td></tr>
+<tr class="memitem:aba3fc693c174a47dd1d73a9e58d97b00"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___rm_info.html#aba3fc693c174a47dd1d73a9e58d97b00">isCommRegAvailable</a> [<a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gab1b9457684eda680598c1bc8a574e20c">CSL_DSS_COMM_REG_ID_MAX</a>]</td></tr>
+<tr class="separator:aba3fc693c174a47dd1d73a9e58d97b00"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a4b8a53db450d230a652cd8cc38d9cd5a"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___rm_info.html#a4b8a53db450d230a652cd8cc38d9cd5a">isPipeAvailable</a> [<a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gafbbd94228f58df3124b2bc9780379cea">CSL_DSS_VID_PIPE_ID_MAX</a>]</td></tr>
+<tr class="separator:a4b8a53db450d230a652cd8cc38d9cd5a"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ac9add0a21cbc5d3a4b0f893e766e593e"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___rm_info.html#ac9add0a21cbc5d3a4b0f893e766e593e">isOverlayAvailable</a> [<a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga41df77f605b2d5c6e107fd4b0df61220">CSL_DSS_OVERLAY_ID_MAX</a>]</td></tr>
+<tr class="separator:ac9add0a21cbc5d3a4b0f893e766e593e"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a72fbf32ce584379f198783a281f00130"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___rm_info.html#a72fbf32ce584379f198783a281f00130">isPortAvailable</a> [<a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga0a203752c6295d20389b36d6c2e0de0c">CSL_DSS_VP_ID_MAX</a>]</td></tr>
+<tr class="separator:a72fbf32ce584379f198783a281f00130"><td class="memSeparator" colspan="2"> </td></tr>
+</table>
+<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
+<div class="textblock"><p>Structure containing resources manager information. This enables display sharing between two different softwares. </p>
+</div><h2 class="groupheader">Field Documentation</h2>
+<a class="anchor" id="aba3fc693c174a47dd1d73a9e58d97b00"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t Dss_RmInfo::isCommRegAvailable[<a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gab1b9457684eda680598c1bc8a574e20c">CSL_DSS_COMM_REG_ID_MAX</a>]</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Ids for available common regions </p>
+
+</div>
+</div>
+<a class="anchor" id="ac9add0a21cbc5d3a4b0f893e766e593e"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t Dss_RmInfo::isOverlayAvailable[<a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga41df77f605b2d5c6e107fd4b0df61220">CSL_DSS_OVERLAY_ID_MAX</a>]</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Ids for available overlays </p>
+
+</div>
+</div>
+<a class="anchor" id="a4b8a53db450d230a652cd8cc38d9cd5a"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t Dss_RmInfo::isPipeAvailable[<a class="el" href="group___c_s_l___d_s_s_t_o_p.html#gafbbd94228f58df3124b2bc9780379cea">CSL_DSS_VID_PIPE_ID_MAX</a>]</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Ids for available video pipes </p>
+
+</div>
+</div>
+<a class="anchor" id="a72fbf32ce584379f198783a281f00130"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t Dss_RmInfo::isPortAvailable[<a class="el" href="group___c_s_l___d_s_s_t_o_p.html#ga0a203752c6295d20389b36d6c2e0de0c">CSL_DSS_VP_ID_MAX</a>]</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Ids for available video ports </p>
+
+</div>
+</div>
+<hr/>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="dss__soc_8h.html">dss_soc.h</a></li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/struct_dss___sc_rt_params.html b/packages/ti/drv/dss/docs/doxygen/html/struct_dss___sc_rt_params.html
--- /dev/null
@@ -0,0 +1,70 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Dss_ScRtParams Struct Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li class="current"><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="files.html"><span>Files</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow2" class="tabs2">
+ <ul class="tablist">
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="functions.html"><span>Data Fields</span></a></li>
+ </ul>
+ </div>
+</div><!-- top -->
+<div class="header">
+ <div class="summary">
+<a href="#pub-attribs">Data Fields</a> </div>
+ <div class="headertitle">
+<div class="title">Dss_ScRtParams Struct Reference</div> </div>
+</div><!--header-->
+<div class="contents">
+
+<p>Structure containing run time scaler configuration.
+ <a href="struct_dss___sc_rt_params.html#details">More...</a></p>
+
+<p><code>#include <dss_disp.h></code></p>
+<table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
+Data Fields</h2></td></tr>
+<tr class="memitem:a91ae75c8f0ebf3f0cc30b8b97a2024c6"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___sc_rt_params.html#a91ae75c8f0ebf3f0cc30b8b97a2024c6">pixelInc</a></td></tr>
+<tr class="separator:a91ae75c8f0ebf3f0cc30b8b97a2024c6"><td class="memSeparator" colspan="2"> </td></tr>
+</table>
+<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
+<div class="textblock"><p>Structure containing run time scaler configuration. </p>
+</div><h2 class="groupheader">Field Documentation</h2>
+<a class="anchor" id="a91ae75c8f0ebf3f0cc30b8b97a2024c6"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t Dss_ScRtParams::pixelInc</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Pixel increment in terms of pixels. </p>
+
+</div>
+</div>
+<hr/>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="dss__disp_8h.html">dss_disp.h</a></li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/struct_dss___soc_params.html b/packages/ti/drv/dss/docs/doxygen/html/struct_dss___soc_params.html
--- /dev/null
@@ -0,0 +1,85 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Dss_SocParams Struct Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li class="current"><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="files.html"><span>Files</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow2" class="tabs2">
+ <ul class="tablist">
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="functions.html"><span>Data Fields</span></a></li>
+ </ul>
+ </div>
+</div><!-- top -->
+<div class="header">
+ <div class="summary">
+<a href="#pub-attribs">Data Fields</a> </div>
+ <div class="headertitle">
+<div class="title">Dss_SocParams Struct Reference</div> </div>
+</div><!--header-->
+<div class="contents">
+
+<p>DSS SOC parameters.
+ <a href="struct_dss___soc_params.html#details">More...</a></p>
+
+<p><code>#include <dss_soc.h></code></p>
+<table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
+Data Fields</h2></td></tr>
+<tr class="memitem:a8323d29f1f228a29162b29d1ab487b5a"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_dss___irq_params.html">Dss_IrqParams</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___soc_params.html#a8323d29f1f228a29162b29d1ab487b5a">irqParams</a></td></tr>
+<tr class="separator:a8323d29f1f228a29162b29d1ab487b5a"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:aafaaca6953b19d37aa273c25a3a5ada8"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_dss___rm_info.html">Dss_RmInfo</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_dss___soc_params.html#aafaaca6953b19d37aa273c25a3a5ada8">rmInfo</a></td></tr>
+<tr class="separator:aafaaca6953b19d37aa273c25a3a5ada8"><td class="memSeparator" colspan="2"> </td></tr>
+</table>
+<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
+<div class="textblock"><p>DSS SOC parameters. </p>
+</div><h2 class="groupheader">Field Documentation</h2>
+<a class="anchor" id="a8323d29f1f228a29162b29d1ab487b5a"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname"><a class="el" href="struct_dss___irq_params.html">Dss_IrqParams</a> Dss_SocParams::irqParams</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>DSS interrupt information </p>
+
+</div>
+</div>
+<a class="anchor" id="aafaaca6953b19d37aa273c25a3a5ada8"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname"><a class="el" href="struct_dss___rm_info.html">Dss_RmInfo</a> Dss_SocParams::rmInfo</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>DSS resource information </p>
+
+</div>
+</div>
+<hr/>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="dss__soc_8h.html">dss_soc.h</a></li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/struct_fvid2___crop_config.html b/packages/ti/drv/dss/docs/doxygen/html/struct_fvid2___crop_config.html
--- /dev/null
@@ -0,0 +1,116 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Fvid2_CropConfig Struct Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li class="current"><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="files.html"><span>Files</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow2" class="tabs2">
+ <ul class="tablist">
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="functions.html"><span>Data Fields</span></a></li>
+ </ul>
+ </div>
+</div><!-- top -->
+<div class="header">
+ <div class="summary">
+<a href="#pub-attribs">Data Fields</a> </div>
+ <div class="headertitle">
+<div class="title">Fvid2_CropConfig Struct Reference</div> </div>
+</div><!--header-->
+<div class="contents">
+
+<p>Structure containing crop configuration - used in Scaler and VCOMP.
+ <a href="struct_fvid2___crop_config.html#details">More...</a></p>
+
+<p><code>#include <csl_fvid2_dataTypes.h></code></p>
+<table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
+Data Fields</h2></td></tr>
+<tr class="memitem:a0312b61252f23269919008c8c2a15450"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_fvid2___crop_config.html#a0312b61252f23269919008c8c2a15450">cropStartX</a></td></tr>
+<tr class="separator:a0312b61252f23269919008c8c2a15450"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a35cc1e45b5914ed02374fc1b0400b740"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_fvid2___crop_config.html#a35cc1e45b5914ed02374fc1b0400b740">cropStartY</a></td></tr>
+<tr class="separator:a35cc1e45b5914ed02374fc1b0400b740"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a45cf01dd1c4d0f9e069432d3ea467c03"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_fvid2___crop_config.html#a45cf01dd1c4d0f9e069432d3ea467c03">cropWidth</a></td></tr>
+<tr class="separator:a45cf01dd1c4d0f9e069432d3ea467c03"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a81496ac240b08840f12474d0c53958cd"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_fvid2___crop_config.html#a81496ac240b08840f12474d0c53958cd">cropHeight</a></td></tr>
+<tr class="separator:a81496ac240b08840f12474d0c53958cd"><td class="memSeparator" colspan="2"> </td></tr>
+</table>
+<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
+<div class="textblock"><p>Structure containing crop configuration - used in Scaler and VCOMP. </p>
+<p>struct <a class="el" href="struct_fvid2___crop_config.html" title="Structure containing crop configuration - used in Scaler and VCOMP. ">Fvid2_CropConfig</a> </p>
+</div><h2 class="groupheader">Field Documentation</h2>
+<a class="anchor" id="a81496ac240b08840f12474d0c53958cd"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t Fvid2_CropConfig::cropHeight</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Height of the picture to be cropped. </p>
+
+</div>
+</div>
+<a class="anchor" id="a0312b61252f23269919008c8c2a15450"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t Fvid2_CropConfig::cropStartX</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Horizontal offset from which picture needs to be cropped. </p>
+
+</div>
+</div>
+<a class="anchor" id="a35cc1e45b5914ed02374fc1b0400b740"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t Fvid2_CropConfig::cropStartY</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Vertical offset from which picture needs to be cropped. </p>
+
+</div>
+</div>
+<a class="anchor" id="a45cf01dd1c4d0f9e069432d3ea467c03"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t Fvid2_CropConfig::cropWidth</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Width of the picture to be cropped. </p>
+
+</div>
+</div>
+<hr/>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="csl__fvid2__data_types_8h.html">csl_fvid2_dataTypes.h</a></li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/struct_fvid2___format.html b/packages/ti/drv/dss/docs/doxygen/html/struct_fvid2___format.html
--- /dev/null
@@ -0,0 +1,176 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Fvid2_Format Struct Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li class="current"><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="files.html"><span>Files</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow2" class="tabs2">
+ <ul class="tablist">
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="functions.html"><span>Data Fields</span></a></li>
+ </ul>
+ </div>
+</div><!-- top -->
+<div class="header">
+ <div class="summary">
+<a href="#pub-attribs">Data Fields</a> </div>
+ <div class="headertitle">
+<div class="title">Fvid2_Format Struct Reference</div> </div>
+</div><!--header-->
+<div class="contents">
+
+<p>FVID2 video buffer format specification.
+ <a href="struct_fvid2___format.html#details">More...</a></p>
+
+<p><code>#include <csl_fvid2_dataTypes.h></code></p>
+<table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
+Data Fields</h2></td></tr>
+<tr class="memitem:a1f5ea464b31c5f7e77323e8f82c4d5e8"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_fvid2___format.html#a1f5ea464b31c5f7e77323e8f82c4d5e8">chNum</a></td></tr>
+<tr class="separator:a1f5ea464b31c5f7e77323e8f82c4d5e8"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ae8fa2690ac1bef44b56d546a6b0cce6f"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_fvid2___format.html#ae8fa2690ac1bef44b56d546a6b0cce6f">width</a></td></tr>
+<tr class="separator:ae8fa2690ac1bef44b56d546a6b0cce6f"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a4585d49a857883721f2664f4a0826849"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_fvid2___format.html#a4585d49a857883721f2664f4a0826849">height</a></td></tr>
+<tr class="separator:a4585d49a857883721f2664f4a0826849"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a3721a977887cae78aa15398c8214145b"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_fvid2___format.html#a3721a977887cae78aa15398c8214145b">pitch</a> [<a class="el" href="csl__fvid2__data_types_8h.html#aef0d63f7f96514278ebda30f1c0bec74">FVID2_MAX_PLANES</a>]</td></tr>
+<tr class="separator:a3721a977887cae78aa15398c8214145b"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a58cee5e76605bdd4a691c8094f719f8d"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_fvid2___format.html#a58cee5e76605bdd4a691c8094f719f8d">fieldMerged</a> [<a class="el" href="csl__fvid2__data_types_8h.html#a19b6ef6e426b64e15bc08ce46c644aef">FVID2_MAX_PLANES_PER_FIELD</a>]</td></tr>
+<tr class="separator:a58cee5e76605bdd4a691c8094f719f8d"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:abb9f60d4fcdab6fbfda7a2c92cbfce53"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_fvid2___format.html#abb9f60d4fcdab6fbfda7a2c92cbfce53">dataFormat</a></td></tr>
+<tr class="separator:abb9f60d4fcdab6fbfda7a2c92cbfce53"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a8caf0c6c3ab4f84dfcbfdc23958cc2fa"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_fvid2___format.html#a8caf0c6c3ab4f84dfcbfdc23958cc2fa">scanFormat</a></td></tr>
+<tr class="separator:a8caf0c6c3ab4f84dfcbfdc23958cc2fa"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:aff43b4f3b6ebdc15e84c1a0c4e55fd14"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_fvid2___format.html#aff43b4f3b6ebdc15e84c1a0c4e55fd14">ccsFormat</a></td></tr>
+<tr class="separator:aff43b4f3b6ebdc15e84c1a0c4e55fd14"><td class="memSeparator" colspan="2"> </td></tr>
+</table>
+<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
+<div class="textblock"><p>FVID2 video buffer format specification. </p>
+<p>Used during Fvid2_create() by some drivers. Used as parameter to Fvid2_setFormat(), Fvid2_getFormat() by some drivers. </p>
+</div><h2 class="groupheader">Field Documentation</h2>
+<a class="anchor" id="aff43b4f3b6ebdc15e84c1a0c4e55fd14"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t Fvid2_Format::ccsFormat</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Color Component Storage format. For valid values see <a class="el" href="csl__fvid2__data_types_8h.html#a82c2f41780c5f44ed27f7ebadf18a21d" title="1 Bits per Pixel packed. ">Fvid2_ColorCompStorageFmt</a>. </p>
+
+</div>
+</div>
+<a class="anchor" id="a1f5ea464b31c5f7e77323e8f82c4d5e8"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t Fvid2_Format::chNum</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Channel Number to which this format belongs to. </p>
+
+</div>
+</div>
+<a class="anchor" id="abb9f60d4fcdab6fbfda7a2c92cbfce53"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t Fvid2_Format::dataFormat</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Frame data Format. For valid values see <a class="el" href="csl__fvid2__data_types_8h.html#a9f5096b017d15ffecdcc0990fd1b031a" title="YUV 422 Interleaved format - UYVY. ">Fvid2_DataFormat</a>. </p>
+
+</div>
+</div>
+<a class="anchor" id="a58cee5e76605bdd4a691c8094f719f8d"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t Fvid2_Format::fieldMerged[<a class="el" href="csl__fvid2__data_types_8h.html#a19b6ef6e426b64e15bc08ce46c644aef">FVID2_MAX_PLANES_PER_FIELD</a>]</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>This field tells whether both the fields have to be merged, i.e line interleaved or not. Used only for interlaced format. The effective pitch is calculated based on this information along with pitch parameter. If fields are merged, effective pitch = pitch * 2 else effective pitch = pitch. </p>
+
+</div>
+</div>
+<a class="anchor" id="a4585d49a857883721f2664f4a0826849"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t Fvid2_Format::height</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Height of the video frame or field in lines. </p>
+
+</div>
+</div>
+<a class="anchor" id="a3721a977887cae78aa15398c8214145b"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t Fvid2_Format::pitch[<a class="el" href="csl__fvid2__data_types_8h.html#aef0d63f7f96514278ebda30f1c0bec74">FVID2_MAX_PLANES</a>]</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Pitch in bytes for each of the sub-buffers. This represents the difference between two consecutive line addresses in bytes. This is irrespective of whether the video is interlaced or progressive and whether the fields are merged or separated for interlaced video. </p>
+
+</div>
+</div>
+<a class="anchor" id="a8caf0c6c3ab4f84dfcbfdc23958cc2fa"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t Fvid2_Format::scanFormat</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Scan Format. For valid values see <a class="el" href="csl__fvid2__data_types_8h.html#af5dfad95adb11f1220c13a37564b706e" title="Interlaced mode. ">Fvid2_ScanFormat</a>. </p>
+
+</div>
+</div>
+<a class="anchor" id="ae8fa2690ac1bef44b56d546a6b0cce6f"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t Fvid2_Format::width</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Width of the video frame or field in pixels. </p>
+
+</div>
+</div>
+<hr/>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="csl__fvid2__data_types_8h.html">csl_fvid2_dataTypes.h</a></li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/struct_fvid2___frame.html b/packages/ti/drv/dss/docs/doxygen/html/struct_fvid2___frame.html
--- /dev/null
@@ -0,0 +1,200 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Fvid2_Frame Struct Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li class="current"><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="files.html"><span>Files</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow2" class="tabs2">
+ <ul class="tablist">
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="functions.html"><span>Data Fields</span></a></li>
+ </ul>
+ </div>
+</div><!-- top -->
+<div class="header">
+ <div class="summary">
+<a href="#pub-attribs">Data Fields</a> </div>
+ <div class="headertitle">
+<div class="title">Fvid2_Frame Struct Reference</div> </div>
+</div><!--header-->
+<div class="contents">
+
+<p>FVID2 frame buffer structure.
+ <a href="struct_fvid2___frame.html#details">More...</a></p>
+
+<p><code>#include <csl_fvid2_dataTypes.h></code></p>
+<table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
+Data Fields</h2></td></tr>
+<tr class="memitem:ad9e33643cd628e7432da408ad6565305"><td class="memItemLeft" align="right" valign="top">void * </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_fvid2___frame.html#ad9e33643cd628e7432da408ad6565305">addr</a> [<a class="el" href="csl__fvid2__data_types_8h.html#aef0d63f7f96514278ebda30f1c0bec74">FVID2_MAX_PLANES</a>]</td></tr>
+<tr class="separator:ad9e33643cd628e7432da408ad6565305"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a953491d1babc17d72cb892ae22b0b2a0"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_fvid2___frame.html#a953491d1babc17d72cb892ae22b0b2a0">fid</a></td></tr>
+<tr class="separator:a953491d1babc17d72cb892ae22b0b2a0"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a550ee00873923f1cc53905dfa0911918"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_fvid2___frame.html#a550ee00873923f1cc53905dfa0911918">chNum</a></td></tr>
+<tr class="separator:a550ee00873923f1cc53905dfa0911918"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a4563054a2f01febf65268dafa538f70c"><td class="memItemLeft" align="right" valign="top">uint64_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_fvid2___frame.html#a4563054a2f01febf65268dafa538f70c">timeStamp64</a></td></tr>
+<tr class="separator:a4563054a2f01febf65268dafa538f70c"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a071f9e8c68e831b029a17a342da7bce8"><td class="memItemLeft" align="right" valign="top">void * </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_fvid2___frame.html#a071f9e8c68e831b029a17a342da7bce8">appData</a></td></tr>
+<tr class="separator:a071f9e8c68e831b029a17a342da7bce8"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ab70ec59f98e2fa3bac85f5fe25645bcc"><td class="memItemLeft" align="right" valign="top">void * </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_fvid2___frame.html#ab70ec59f98e2fa3bac85f5fe25645bcc">perFrameCfg</a></td></tr>
+<tr class="separator:ab70ec59f98e2fa3bac85f5fe25645bcc"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a5e23564dddc24970d5a08ec7f91ac387"><td class="memItemLeft" align="right" valign="top">void * </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_fvid2___frame.html#a5e23564dddc24970d5a08ec7f91ac387">drvData</a></td></tr>
+<tr class="separator:a5e23564dddc24970d5a08ec7f91ac387"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a97a3b5dcf677d9e81113358d18d45ffd"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_fvid2___sub_frame_info.html">Fvid2_SubFrameInfo</a> * </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_fvid2___frame.html#a97a3b5dcf677d9e81113358d18d45ffd">subFrameInfo</a></td></tr>
+<tr class="separator:a97a3b5dcf677d9e81113358d18d45ffd"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a16ee5088306c5a6bbf0126549ec005e1"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_fvid2___frame.html#a16ee5088306c5a6bbf0126549ec005e1">status</a></td></tr>
+<tr class="separator:a16ee5088306c5a6bbf0126549ec005e1"><td class="memSeparator" colspan="2"> </td></tr>
+</table>
+<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
+<div class="textblock"><p>FVID2 frame buffer structure. </p>
+<p>Unless specified otherwise, all fields in this structure are</p>
+<p>[IN] for Fvid2_queue(), Fvid2_processFrames() operation. [OUT] for Fvid2_dequeue(), Fvid2_getProcessedFrames() operation. </p>
+</div><h2 class="groupheader">Field Documentation</h2>
+<a class="anchor" id="ad9e33643cd628e7432da408ad6565305"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">void* Fvid2_Frame::addr[<a class="el" href="csl__fvid2__data_types_8h.html#aef0d63f7f96514278ebda30f1c0bec74">FVID2_MAX_PLANES</a>]</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>FVID2 buffer pointers for supporting multiple addresses like Y, U, V etc for a given frame. The interpretation of these pointers depend on the format configured for the driver. Not all pointers are valid for a given format.</p>
+<p>Representation of YUV422 Interlaced Planar Buffer: Field 0 Y -> addr[0], Field 1 Y -> addr[3] Field 0 U -> addr[1], Field 1 U -> addr[4] Field 0 V -> addr[2], Field 1 V -> addr[5] Representation of YUV422 Progressive Planar Buffer: Y -> addr[0] U -> addr[1] V -> addr[2] Other pointers are not valid.</p>
+<p>Representation of Interlaced YUV422 Interleaved Buffer: Field 0 YUV -> addr[0], Field 1 YUV -> addr[3] Representation of Progressive YUV422 Interleaved Buffer: YUV -> addr[0] Other pointers are not valid.</p>
+<p>Representation of Interlaced YUV420SP or YUV422SP Buffer: Field 0 Y -> addr[0], Field 1 Y -> addr[3] Field 0 UV -> addr[1], Field 1 UV -> addr[4] Representation of Progressive YUV420SP or YUV422SP Buffer: Y -> addr[0] UV -> addr[1] Other pointers are not valid.</p>
+<p>Representation of Interlaced RGB888 Buffer Field 0 RGB -> addr[0], Field 1 RGB -> addr[3], Representation of Progressive RGB888 Buffer RGB -> addr[0] Other pointers are not valid. </p>
+
+</div>
+</div>
+<a class="anchor" id="a071f9e8c68e831b029a17a342da7bce8"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">void* Fvid2_Frame::appData</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Additional application parameter per frame. This is not modified by driver. </p>
+
+</div>
+</div>
+<a class="anchor" id="a550ee00873923f1cc53905dfa0911918"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t Fvid2_Frame::chNum</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Channel number to which this FVID2 frame belongs to. </p>
+
+</div>
+</div>
+<a class="anchor" id="a5e23564dddc24970d5a08ec7f91ac387"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">void* Fvid2_Frame::drvData</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Used by driver. Application should not modify this. </p>
+
+</div>
+</div>
+<a class="anchor" id="a953491d1babc17d72cb892ae22b0b2a0"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t Fvid2_Frame::fid</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Indicates whether this frame belong to top or bottom field. For valid values see <a class="el" href="csl__fvid2__data_types_8h.html#a46dbb7460c568075f1cd6959282d87cb" title="Top field. ">Fvid2_Fid</a>. </p>
+
+</div>
+</div>
+<a class="anchor" id="ab70ec59f98e2fa3bac85f5fe25645bcc"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">void* Fvid2_Frame::perFrameCfg</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Per frame configuration parameters like scaling ratio, positioning, cropping etc... This should be set to NULL if not used.</p>
+<p>This can be used by application to control driver behaviour on a per frame basis, example changing scaling ratio for scaler driver.</p>
+<p>This can be used by application to get per frame status, example detected frame width, height from capture driver.</p>
+<p>This could be set to NULL if not used. In this case, the driver will use the last supplied configuration.</p>
+<p>The exact structure type that is passed is driver specific. </p>
+
+</div>
+</div>
+<a class="anchor" id="a16ee5088306c5a6bbf0126549ec005e1"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t Fvid2_Frame::status</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Status of the Frame, see <a class="el" href="csl__fvid2__data_types_8h.html#a248e190fab40aca929969c432068a099" title="Enum for state of the FVID2 frame. Typically used for marking FVID2_frame as either SUBMITTED...">Fvid2_FrameStatus</a> for the valid values Updated by the driver </p>
+
+</div>
+</div>
+<a class="anchor" id="a97a3b5dcf677d9e81113358d18d45ffd"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname"><a class="el" href="struct_fvid2___sub_frame_info.html">Fvid2_SubFrameInfo</a>* Fvid2_Frame::subFrameInfo</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Used for SubFrame level processing information exchange between application and driver. This could be set to NULL if sub-frame level processing is not used. </p>
+
+</div>
+</div>
+<a class="anchor" id="a4563054a2f01febf65268dafa538f70c"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint64_t Fvid2_Frame::timeStamp64</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>64-bit Time stamp returned by the driver. The value and the unit is driver implementation dependent. But in general the time stamp stored is in micro-seconds. Refer to each driver implementation for the meaning and unit of the time stamp value. Only valid for frames received using Fvid2_dequeue(). </p>
+
+</div>
+</div>
+<hr/>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="csl__fvid2__data_types_8h.html">csl_fvid2_dataTypes.h</a></li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/struct_fvid2___frame_list.html b/packages/ti/drv/dss/docs/doxygen/html/struct_fvid2___frame_list.html
--- /dev/null
@@ -0,0 +1,134 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Fvid2_FrameList Struct Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li class="current"><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="files.html"><span>Files</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow2" class="tabs2">
+ <ul class="tablist">
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="functions.html"><span>Data Fields</span></a></li>
+ </ul>
+ </div>
+</div><!-- top -->
+<div class="header">
+ <div class="summary">
+<a href="#pub-attribs">Data Fields</a> </div>
+ <div class="headertitle">
+<div class="title">Fvid2_FrameList Struct Reference</div> </div>
+</div><!--header-->
+<div class="contents">
+
+<p>FVID2 frame buffer list used to exchange multiple FVID2 frames in a single driver call.
+ <a href="struct_fvid2___frame_list.html#details">More...</a></p>
+
+<p><code>#include <csl_fvid2_dataTypes.h></code></p>
+<table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
+Data Fields</h2></td></tr>
+<tr class="memitem:ae772ff66598716fe46b8aa687240414c"><td class="memItemLeft" align="right" valign="top"><a class="el" href="struct_fvid2___frame.html">Fvid2_Frame</a> * </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_fvid2___frame_list.html#ae772ff66598716fe46b8aa687240414c">frames</a> [<a class="el" href="csl__fvid2__data_types_8h.html#adcf85da7b48cf6db3cce2efb2d86c92f">FVID2_MAX_FRAME_PTR</a>]</td></tr>
+<tr class="separator:ae772ff66598716fe46b8aa687240414c"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:af516451b916cad435d827c96669e2825"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_fvid2___frame_list.html#af516451b916cad435d827c96669e2825">numFrames</a></td></tr>
+<tr class="separator:af516451b916cad435d827c96669e2825"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ae92f871d92e87591634aa6fbf2db7a9c"><td class="memItemLeft" align="right" valign="top">void * </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_fvid2___frame_list.html#ae92f871d92e87591634aa6fbf2db7a9c">drvData</a></td></tr>
+<tr class="separator:ae92f871d92e87591634aa6fbf2db7a9c"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a3d40464eb4d1129eae2c8a95d65a5ec5"><td class="memItemLeft" align="right" valign="top">void * </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_fvid2___frame_list.html#a3d40464eb4d1129eae2c8a95d65a5ec5">appData</a></td></tr>
+<tr class="separator:a3d40464eb4d1129eae2c8a95d65a5ec5"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ab6dbd19e34bebec6941fbde314fcfb4f"><td class="memItemLeft" align="right" valign="top">void * </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_fvid2___frame_list.html#ab6dbd19e34bebec6941fbde314fcfb4f">perListCfg</a></td></tr>
+<tr class="separator:ab6dbd19e34bebec6941fbde314fcfb4f"><td class="memSeparator" colspan="2"> </td></tr>
+</table>
+<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
+<div class="textblock"><p>FVID2 frame buffer list used to exchange multiple FVID2 frames in a single driver call. </p>
+<p>Unless specified otherwise, all fields in this structure are</p>
+<p>[IN] for Fvid2_queue(), Fvid2_processFrames() operation. [OUT] for Fvid2_dequeue(), Fvid2_getProcessedFrames() operation. </p>
+</div><h2 class="groupheader">Field Documentation</h2>
+<a class="anchor" id="a3d40464eb4d1129eae2c8a95d65a5ec5"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">void* Fvid2_FrameList::appData</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Additional application parameter per frame. This is not modified by driver. </p>
+
+</div>
+</div>
+<a class="anchor" id="ae92f871d92e87591634aa6fbf2db7a9c"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">void* Fvid2_FrameList::drvData</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Used by driver. Application should not modify this. </p>
+
+</div>
+</div>
+<a class="anchor" id="ae772ff66598716fe46b8aa687240414c"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname"><a class="el" href="struct_fvid2___frame.html">Fvid2_Frame</a>* Fvid2_FrameList::frames[<a class="el" href="csl__fvid2__data_types_8h.html#adcf85da7b48cf6db3cce2efb2d86c92f">FVID2_MAX_FRAME_PTR</a>]</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Array of <a class="el" href="struct_fvid2___frame.html" title="FVID2 frame buffer structure. ">Fvid2_Frame</a> pointers that are to given or received from the driver. </p>
+
+</div>
+</div>
+<a class="anchor" id="af516451b916cad435d827c96669e2825"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t Fvid2_FrameList::numFrames</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Number of frames that are given or received from the driver i.e number of valid pointers in the array containing <a class="el" href="struct_fvid2___frame.html" title="FVID2 frame buffer structure. ">Fvid2_Frame</a> pointers. </p>
+
+</div>
+</div>
+<a class="anchor" id="ab6dbd19e34bebec6941fbde314fcfb4f"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">void* Fvid2_FrameList::perListCfg</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Per list configuration parameters like scaling ratio, positioning, cropping etc which are applicable for the frames together.</p>
+<p>This could be set to NULL if not used. In this case, the driver will use the last supplied configuration.</p>
+<p>The exact structure type that is passed is driver specific. </p>
+
+</div>
+</div>
+<hr/>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="csl__fvid2__data_types_8h.html">csl_fvid2_dataTypes.h</a></li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/struct_fvid2___mode_info.html b/packages/ti/drv/dss/docs/doxygen/html/struct_fvid2___mode_info.html
--- /dev/null
@@ -0,0 +1,235 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Fvid2_ModeInfo Struct Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li class="current"><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="files.html"><span>Files</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow2" class="tabs2">
+ <ul class="tablist">
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="functions.html"><span>Data Fields</span></a></li>
+ </ul>
+ </div>
+</div><!-- top -->
+<div class="header">
+ <div class="summary">
+<a href="#pub-attribs">Data Fields</a> </div>
+ <div class="headertitle">
+<div class="title">Fvid2_ModeInfo Struct Reference</div> </div>
+</div><!--header-->
+<div class="contents">
+
+<p>FVID2 Mode information structure.
+ <a href="struct_fvid2___mode_info.html#details">More...</a></p>
+
+<p><code>#include <csl_fvid2_dataTypes.h></code></p>
+<table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
+Data Fields</h2></td></tr>
+<tr class="memitem:a8c27c6fb4272816c4708e23e66ea4c40"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_fvid2___mode_info.html#a8c27c6fb4272816c4708e23e66ea4c40">standard</a></td></tr>
+<tr class="separator:a8c27c6fb4272816c4708e23e66ea4c40"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a65e201988503365e459cd3464c3a8b8d"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_fvid2___mode_info.html#a65e201988503365e459cd3464c3a8b8d">width</a></td></tr>
+<tr class="separator:a65e201988503365e459cd3464c3a8b8d"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a086db39a44f2c72f78a9016263d56123"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_fvid2___mode_info.html#a086db39a44f2c72f78a9016263d56123">height</a></td></tr>
+<tr class="separator:a086db39a44f2c72f78a9016263d56123"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a9f9211f1783dadb46fe4f24fe44bf205"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_fvid2___mode_info.html#a9f9211f1783dadb46fe4f24fe44bf205">scanFormat</a></td></tr>
+<tr class="separator:a9f9211f1783dadb46fe4f24fe44bf205"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ac65ac9af809220a1a6445bfa1111ca05"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_fvid2___mode_info.html#ac65ac9af809220a1a6445bfa1111ca05">pixelClock</a></td></tr>
+<tr class="separator:ac65ac9af809220a1a6445bfa1111ca05"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ad507776704ccbdc7380978d8979777f9"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_fvid2___mode_info.html#ad507776704ccbdc7380978d8979777f9">fps</a></td></tr>
+<tr class="separator:ad507776704ccbdc7380978d8979777f9"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a9c7400f345023ef6ebbf384d9d4f5a0c"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_fvid2___mode_info.html#a9c7400f345023ef6ebbf384d9d4f5a0c">hFrontPorch</a></td></tr>
+<tr class="separator:a9c7400f345023ef6ebbf384d9d4f5a0c"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a0d8d9e15366412921d1b1cb083924236"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_fvid2___mode_info.html#a0d8d9e15366412921d1b1cb083924236">hBackPorch</a></td></tr>
+<tr class="separator:a0d8d9e15366412921d1b1cb083924236"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ac30f9a789796a753ee22fd56d837b0dc"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_fvid2___mode_info.html#ac30f9a789796a753ee22fd56d837b0dc">hSyncLen</a></td></tr>
+<tr class="separator:ac30f9a789796a753ee22fd56d837b0dc"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a806ac4325f4edcaf2b7dca12a5051149"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_fvid2___mode_info.html#a806ac4325f4edcaf2b7dca12a5051149">vFrontPorch</a></td></tr>
+<tr class="separator:a806ac4325f4edcaf2b7dca12a5051149"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a9ade9b5bd46517cb5cfd0590585cbc33"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_fvid2___mode_info.html#a9ade9b5bd46517cb5cfd0590585cbc33">vBackPorch</a></td></tr>
+<tr class="separator:a9ade9b5bd46517cb5cfd0590585cbc33"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a2b756eece94e9a720028ece8d50991b3"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_fvid2___mode_info.html#a2b756eece94e9a720028ece8d50991b3">vSyncLen</a></td></tr>
+<tr class="separator:a2b756eece94e9a720028ece8d50991b3"><td class="memSeparator" colspan="2"> </td></tr>
+</table>
+<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
+<div class="textblock"><p>FVID2 Mode information structure. </p>
+</div><h2 class="groupheader">Field Documentation</h2>
+<a class="anchor" id="ad507776704ccbdc7380978d8979777f9"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t Fvid2_ModeInfo::fps</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Frames per second. </p>
+
+</div>
+</div>
+<a class="anchor" id="a0d8d9e15366412921d1b1cb083924236"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t Fvid2_ModeInfo::hBackPorch</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Horizontal back porch. </p>
+
+</div>
+</div>
+<a class="anchor" id="a086db39a44f2c72f78a9016263d56123"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t Fvid2_ModeInfo::height</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Active video frame height in lines. </p>
+
+</div>
+</div>
+<a class="anchor" id="a9c7400f345023ef6ebbf384d9d4f5a0c"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t Fvid2_ModeInfo::hFrontPorch</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Horizontal front porch. Same for both fields in case of interlaced display. </p>
+
+</div>
+</div>
+<a class="anchor" id="ac30f9a789796a753ee22fd56d837b0dc"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t Fvid2_ModeInfo::hSyncLen</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Horizontal sync length. Same for both fields in case of interlaced display. </p>
+
+</div>
+</div>
+<a class="anchor" id="ac65ac9af809220a1a6445bfa1111ca05"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t Fvid2_ModeInfo::pixelClock</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Pixel clock of standard in KHz. This assumes 8-bit interface for NTSC/PAL/480I/576I resolutions and 16/24-bit interface for other resolutions including 480P and 576P. </p>
+
+</div>
+</div>
+<a class="anchor" id="a9f9211f1783dadb46fe4f24fe44bf205"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t Fvid2_ModeInfo::scanFormat</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Scan format of standard. For valid values see <a class="el" href="csl__fvid2__data_types_8h.html#af5dfad95adb11f1220c13a37564b706e" title="Interlaced mode. ">Fvid2_ScanFormat</a>. </p>
+
+</div>
+</div>
+<a class="anchor" id="a8c27c6fb4272816c4708e23e66ea4c40"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t Fvid2_ModeInfo::standard</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>[IN] Standard for which to get the info. For valid values see <a class="el" href="csl__fvid2__data_types_8h.html#aaa2667d105d557f254c20b87534ed4b6" title="720x480 30FPS interlaced NTSC standard. ">Fvid2_Standard</a>. </p>
+
+</div>
+</div>
+<a class="anchor" id="a9ade9b5bd46517cb5cfd0590585cbc33"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t Fvid2_ModeInfo::vBackPorch</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Vertical back porch for each field or frame. </p>
+
+</div>
+</div>
+<a class="anchor" id="a806ac4325f4edcaf2b7dca12a5051149"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t Fvid2_ModeInfo::vFrontPorch</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Vertical front porch for each field or frame. </p>
+
+</div>
+</div>
+<a class="anchor" id="a2b756eece94e9a720028ece8d50991b3"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t Fvid2_ModeInfo::vSyncLen</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Vertical sync length for each field. </p>
+
+</div>
+</div>
+<a class="anchor" id="a65e201988503365e459cd3464c3a8b8d"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t Fvid2_ModeInfo::width</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Active video frame width in pixels. </p>
+
+</div>
+</div>
+<hr/>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="csl__fvid2__data_types_8h.html">csl_fvid2_dataTypes.h</a></li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/struct_fvid2___pos_config.html b/packages/ti/drv/dss/docs/doxygen/html/struct_fvid2___pos_config.html
--- /dev/null
@@ -0,0 +1,86 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Fvid2_PosConfig Struct Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li class="current"><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="files.html"><span>Files</span></a></li>
+ </ul>
+ </div>
+ <div id="navrow2" class="tabs2">
+ <ul class="tablist">
+ <li><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="functions.html"><span>Data Fields</span></a></li>
+ </ul>
+ </div>
+</div><!-- top -->
+<div class="header">
+ <div class="summary">
+<a href="#pub-attribs">Data Fields</a> </div>
+ <div class="headertitle">
+<div class="title">Fvid2_PosConfig Struct Reference</div> </div>
+</div><!--header-->
+<div class="contents">
+
+<p>Structure containing position configuration - used in VCOMP and CIG.
+ <a href="struct_fvid2___pos_config.html#details">More...</a></p>
+
+<p><code>#include <csl_fvid2_dataTypes.h></code></p>
+<table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
+Data Fields</h2></td></tr>
+<tr class="memitem:a162f7d3ab12a8e049147ba10b1743b4f"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_fvid2___pos_config.html#a162f7d3ab12a8e049147ba10b1743b4f">startX</a></td></tr>
+<tr class="separator:a162f7d3ab12a8e049147ba10b1743b4f"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a0bdff26f19f3571e6a76db9134644d38"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_fvid2___pos_config.html#a0bdff26f19f3571e6a76db9134644d38">startY</a></td></tr>
+<tr class="separator:a0bdff26f19f3571e6a76db9134644d38"><td class="memSeparator" colspan="2"> </td></tr>
+</table>
+<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
+<div class="textblock"><p>Structure containing position configuration - used in VCOMP and CIG. </p>
+<p>struct <a class="el" href="struct_fvid2___pos_config.html" title="Structure containing position configuration - used in VCOMP and CIG. ">Fvid2_PosConfig</a> </p>
+</div><h2 class="groupheader">Field Documentation</h2>
+<a class="anchor" id="a162f7d3ab12a8e049147ba10b1743b4f"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t Fvid2_PosConfig::startX</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Horizontal offset from which picture needs to be positioned. </p>
+
+</div>
+</div>
+<a class="anchor" id="a0bdff26f19f3571e6a76db9134644d38"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t Fvid2_PosConfig::startY</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Vertical offset from which picture needs to be positioned. </p>
+
+</div>
+</div>
+<hr/>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="csl__fvid2__data_types_8h.html">csl_fvid2_dataTypes.h</a></li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/html/struct_fvid2___size_config.html b/packages/ti/drv/dss/docs/doxygen/html/struct_fvid2___size_config.html
--- /dev/null
@@ -0,0 +1,86 @@
+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
+<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
+<title>Fvid2_SizeConfig Struct Reference</title>
+<link href="doxygen.css" rel="stylesheet" type="text/css">
+<link href="tabs.css" rel="stylesheet" type="text/css">
+</head><body>
+<table width=100%>
+<tr>
+ <td bgcolor="black" width="1"><a href="http://www.ti.com"><img border=0 src="../tilogo.gif"></a></td>
+ <td bgcolor="red"><img src="../titagline.gif"></td>
+</tr>
+</table>
+<!-- Generated by Doxygen 1.8.6 -->
+ <div id="navrow1" class="tabs">
+ <ul class="tablist">
+ <li><a href="index.html"><span>Main Page</span></a></li>
+ <li><a href="modules.html"><span>Modules</span></a></li>
+ <li class="current"><a href="annotated.html"><span>Data Structures</span></a></li>
+ <li><a href="files.html"><span>Files</span></a></li>
+ </ul>
+ </div>
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+ </div>
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+<div class="header">
+ <div class="summary">
+<a href="#pub-attribs">Data Fields</a> </div>
+ <div class="headertitle">
+<div class="title">Fvid2_SizeConfig Struct Reference</div> </div>
+</div><!--header-->
+<div class="contents">
+
+<p>Structure containing size configuration.
+ <a href="struct_fvid2___size_config.html#details">More...</a></p>
+
+<p><code>#include <csl_fvid2_dataTypes.h></code></p>
+<table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
+Data Fields</h2></td></tr>
+<tr class="memitem:a53d5200a448e56564f80fcd92863596d"><td class="memItemLeft" align="right" valign="top">UInt32 </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_fvid2___size_config.html#a53d5200a448e56564f80fcd92863596d">width</a></td></tr>
+<tr class="separator:a53d5200a448e56564f80fcd92863596d"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:ae111168986dd4c3e73a9ffeed987cb3c"><td class="memItemLeft" align="right" valign="top">UInt32 </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_fvid2___size_config.html#ae111168986dd4c3e73a9ffeed987cb3c">height</a></td></tr>
+<tr class="separator:ae111168986dd4c3e73a9ffeed987cb3c"><td class="memSeparator" colspan="2"> </td></tr>
+</table>
+<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
+<div class="textblock"><p>Structure containing size configuration. </p>
+<p>struct <a class="el" href="struct_fvid2___size_config.html" title="Structure containing size configuration. ">Fvid2_SizeConfig</a> </p>
+</div><h2 class="groupheader">Field Documentation</h2>
+<a class="anchor" id="ae111168986dd4c3e73a9ffeed987cb3c"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">UInt32 Fvid2_SizeConfig::height</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Height of the picture. </p>
+
+</div>
+</div>
+<a class="anchor" id="a53d5200a448e56564f80fcd92863596d"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">UInt32 Fvid2_SizeConfig::width</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>Width of the picture. </p>
+
+</div>
+</div>
+<hr/>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="csl__fvid2__data_types_8h.html">csl_fvid2_dataTypes.h</a></li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
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+<div class="title">Fvid2_SubFrameInfo Struct Reference</div> </div>
+</div><!--header-->
+<div class="contents">
+
+<p>Sub-Frame information.
+ <a href="struct_fvid2___sub_frame_info.html#details">More...</a></p>
+
+<p><code>#include <csl_fvid2_dataTypes.h></code></p>
+<table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
+Data Fields</h2></td></tr>
+<tr class="memitem:a6139adfc91c58651f0344f79781319a4"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_fvid2___sub_frame_info.html#a6139adfc91c58651f0344f79781319a4">subFrameNum</a></td></tr>
+<tr class="separator:a6139adfc91c58651f0344f79781319a4"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:a813a5659d1d56a49b0d1b6d8d600ae74"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_fvid2___sub_frame_info.html#a813a5659d1d56a49b0d1b6d8d600ae74">numInLines</a></td></tr>
+<tr class="separator:a813a5659d1d56a49b0d1b6d8d600ae74"><td class="memSeparator" colspan="2"> </td></tr>
+<tr class="memitem:aad0a2f3475b4f409b956a359b31a0960"><td class="memItemLeft" align="right" valign="top">uint32_t </td><td class="memItemRight" valign="bottom"><a class="el" href="struct_fvid2___sub_frame_info.html#aad0a2f3475b4f409b956a359b31a0960">numOutLines</a></td></tr>
+<tr class="separator:aad0a2f3475b4f409b956a359b31a0960"><td class="memSeparator" colspan="2"> </td></tr>
+</table>
+<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
+<div class="textblock"><p>Sub-Frame information. </p>
+<p>This is used in drivers supporting sub-frame level processing, for application and driver interaction </p>
+</div><h2 class="groupheader">Field Documentation</h2>
+<a class="anchor" id="a813a5659d1d56a49b0d1b6d8d600ae74"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t Fvid2_SubFrameInfo::numInLines</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>[IN] Number of lines available in input frame at the end of this sub-frame. Used only in M2M mode. Not used in capture mode. </p>
+
+</div>
+</div>
+<a class="anchor" id="aad0a2f3475b4f409b956a359b31a0960"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t Fvid2_SubFrameInfo::numOutLines</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>[OUT] Number of lines generated in output buffer after processing current sub-frame. Set by driver and used by application. </p>
+
+</div>
+</div>
+<a class="anchor" id="a6139adfc91c58651f0344f79781319a4"></a>
+<div class="memitem">
+<div class="memproto">
+ <table class="memname">
+ <tr>
+ <td class="memname">uint32_t Fvid2_SubFrameInfo::subFrameNum</td>
+ </tr>
+ </table>
+</div><div class="memdoc">
+<p>[IN]/[OUT] Current sub-frame number in this frame, range is from 0 to (number of sub-frames in frame - 1). Set by application and used by driver in case of M2M mode. Set by driver and used by application in case of capture mode. </p>
+
+</div>
+</div>
+<hr/>The documentation for this struct was generated from the following file:<ul>
+<li><a class="el" href="csl__fvid2__data_types_8h.html">csl_fvid2_dataTypes.h</a></li>
+</ul>
+</div><!-- contents -->
+<hr size="1"><small>
+Copyright 2018, Texas Instruments Incorporated</small>
+</body>
+</html>
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+<!--[if gte mso 9]><xml>
+ <o:shapedefaults v:ext="edit" spidmax="5122"/>
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+ <o:idmap v:ext="edit" data="1"/>
+ </o:shapelayout></xml><![endif]-->
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diff --git a/packages/ti/drv/dss/docs/doxygen/tifooter.htm b/packages/ti/drv/dss/docs/doxygen/tifooter.htm
--- /dev/null
@@ -0,0 +1,4 @@
+<hr size="1"><small>
+Copyright $year, Texas Instruments Incorporated</small>
+</body>
+</html>
diff --git a/packages/ti/drv/dss/docs/doxygen/tiheader.htm b/packages/ti/drv/dss/docs/doxygen/tiheader.htm
--- /dev/null
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+<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
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diff --git a/packages/ti/drv/dss/dss.h b/packages/ti/drv/dss/dss.h
--- /dev/null
@@ -0,0 +1,168 @@
+/*
+ * Copyright (c) Texas Instruments Incorporated 2018
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * \defgroup DRV_DSS_MODULE DSS Driver
+ *
+ * @{
+ *
+ * The Display Subsystem (DSS) provides the logic to interface display
+ * peripherals. This is DSS FVID2 driver documentation.
+ */
+/* @} */
+
+/**
+ * \ingroup DRV_DSS_MODULE
+ * \defgroup DSS_TOP_LEVEL DSS Driver Header
+ * This is DSS's top level include for applications
+ *
+ * @{
+ */
+
+/**
+ * \file dss.h
+ *
+ * \brief DSS Driver API/interface file.
+ */
+
+#ifndef DSS_H_
+#define DSS_H_
+
+/* ========================================================================== */
+/* Include Files */
+/* ========================================================================== */
+
+#include <stdint.h>
+#include <ti/csl/soc.h>
+#include <ti/csl/csl_dss.h>
+#include <ti/drv/fvid2/fvid2.h>
+#include <ti/drv/dss/include/dss_cfg.h>
+#include <ti/drv/dss/soc/dss_soc.h>
+#include <ti/drv/dss/include/dss_disp.h>
+#include <ti/drv/dss/include/dss_dctrl.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* ========================================================================== */
+/* Macros & Typedefs */
+/* ========================================================================== */
+
+/** \brief Display driver ID used at the time of FVID2 create. */
+#define DSS_DISP_DRV_ID (FVID2_DSS_DRV_BASE + 0x00U)
+
+/** \brief Display controller driver ID used at the time of FVID2 create. */
+#define DSS_DCTRL_DRV_ID (FVID2_DSS_DRV_BASE + 0x01U)
+
+/*
+ * IOCTLs Base address.
+ */
+/** \brief IOCTL base address for the display driver IOCTLs. */
+#define DSS_DISP_IOCTL_BASE (FVID2_DSS_DRV_IOCTL_BASE + 0x000U)
+/** \brief IOCTL base address for the display controller driver IOCTLs. */
+#define DSS_DCTRL_IOCTL_BASE (FVID2_DSS_DRV_IOCTL_BASE + 0x100U)
+/** \brief IOCTL base address for the SOC specific display driver IOCTLs. */
+#define DSS_DISP_SOC_IOCTL_BASE (DSS_DISP_IOCTL_BASE + 0x40U)
+/** \brief IOCTL base address for the SOC specific display controller driver
+ * IOCTLs. */
+#define DSS_DCTRL_SOC_IOCTL_BASE (DSS_DCTRL_IOCTL_BASE + 0x40U)
+
+/* ========================================================================== */
+/* Structure Declarations */
+/* ========================================================================== */
+
+/**
+ * \brief DSS initialization parameters.
+ */
+typedef struct
+{
+ Dss_SocParams socParams;
+ /**< SoC parameters. Refer #Dss_SocParams for details */
+} Dss_InitParams;
+
+/* ========================================================================== */
+/* Internal/Private Function Declarations */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/* Function Declarations */
+/* ========================================================================== */
+
+/**
+ * \brief Dss_InitParams structure init function.
+ *
+ * \param dssParams Pointer to #Dss_InitParams structure.
+ *
+ * \return None
+ */
+void Dss_initParamsInit(Dss_InitParams *dssParams);
+
+/**
+ * \brief DSS initialization function.
+ * This function initializes the DSS hardware and drivers.
+ * This function should be called before calling any driver APIs and
+ * only once.
+ *
+ * \param initParams Pointer to a #Dss_InitParams structure
+ * containing the DSS configuration
+ *
+ * \return FVID2_SOK if successful, else suitable error code
+ */
+int32_t Dss_init(const Dss_InitParams *initParams);
+
+/**
+ * \brief DSS de-initialization function.
+ * This function un-initializes the DSS hardware and drivers.
+ * This function should be called during system shutdown if Dss_init()
+ * was called by the application.
+ *
+ * \return FVID2_SOK if successful, else suitable error code
+ */
+int32_t Dss_deInit(void);
+
+/* ========================================================================== */
+/* Static Function Definitions */
+/* ========================================================================== */
+
+/* None */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #ifndef DSS_H_ */
+
+/* @} */
diff --git a/packages/ti/drv/dss/dss_component.mk b/packages/ti/drv/dss/dss_component.mk
--- /dev/null
@@ -0,0 +1,224 @@
+# File: dss_component.mk
+# This file is component include make file of DSS driver library.
+# List of variables set in this file and their purpose:
+# <mod>_RELPATH - This is the relative path of the module, typically from
+# top-level directory of the package
+# <mod>_PATH - This is the absolute path of the module. It derives from
+# absolute path of the top-level directory (set in env.mk)
+# and relative path set above
+# <mod>_INCLUDE - This is the path that has interface header files of the
+# module. This can be multiple directories (space separated)
+# <mod>_PKG_LIST - Names of the modules (and sub-modules) that are a part
+# part of this module, including itself.
+# <mod>_BOARD_DEPENDENCY - "yes": means the code for this module depends on
+# platform and the compiled obj/lib has to be kept
+# under <platform> directory
+# "no" or "" or if this variable is not defined: means
+# this module has no platform dependent code and hence
+# the obj/libs are not kept under <platform> dir.
+# <mod>_CORE_DEPENDENCY - "yes": means the code for this module depends on
+# core and the compiled obj/lib has to be kept
+# under <core> directory
+# "no" or "" or if this variable is not defined: means
+# this module has no core dependent code and hence
+# the obj/libs are not kept under <core> dir.
+# <mod>_APP_STAGE_FILES - List of source files that belongs to the module
+# <mod>, but that needs to be compiled at application
+# build stage (in the context of the app). This is
+# primarily for link time configurations or if the
+# source file is dependent on options/defines that are
+# application dependent. This can be left blank or
+# not defined at all, in which case, it means there
+# no source files in the module <mod> that are required
+# to be compiled in the application build stage.
+#
+ifeq ($(dss_component_make_include), )
+
+drvdss_SOCLIST = am65xx j721e
+drvdss_BOARDLIST = am65xx_evm j721e_evm
+drvdss_am65xx_CORELIST = mpu1_0
+drvdss_j721e_CORELIST = mcu2_1
+
+############################
+# DSS package
+# List of components included under DSS lib
+# The components included here are built and will be part of DSS lib
+############################
+dss_LIB_LIST =
+
+############################
+# DSS app lib package
+# List of components included under DSS app lib
+# The components included here are built and will be part of DSS app lib
+############################
+dss_APP_LIB_LIST =
+
+############################
+# DSS examples
+# List of examples under DSS (+= is used at each example definition)
+# All the tests mentioned in list are built when test target is called
+# List below all examples for allowed values
+############################
+dss_EXAMPLE_LIST =
+
+#
+# DSS Modules
+#
+
+# DSS library
+dss_COMP_LIST = dss
+dss_RELPATH = ti/drv/dss
+dss_PATH = $(PDK_DSS_COMP_PATH)
+dss_LIBNAME = dss
+dss_LIBPATH = $(PDK_DSS_COMP_PATH)/lib
+dss_MAKEFILE = -fsrc/makefile
+export dss_MAKEFILE
+export dss_LIBNAME
+export dss_LIBPATH
+dss_BOARD_DEPENDENCY = no
+dss_CORE_DEPENDENCY = yes
+export dss_COMP_LIST
+export dss_BOARD_DEPENDENCY
+export dss_CORE_DEPENDENCY
+dss_PKG_LIST = dss
+dss_INCLUDE = $(dss_PATH)
+dss_SOCLIST = $(drvdss_SOCLIST)
+export dss_SOCLIST
+dss_$(SOC)_CORELIST = $(drvdss_$(SOC)_CORELIST)
+export dss_$(SOC)_CORELIST
+dss_LIB_LIST += dss
+
+dss_app_utils_COMP_LIST = dss_app_utils
+dss_app_utils_RELPATH = ti/drv/dss/examples/utils
+dss_app_utils_PATH = $(PDK_DSS_COMP_PATH)/examples/utils
+dss_app_utils_LIBNAME = dss_app_utils
+dss_app_utils_LIBPATH = $(PDK_DSS_COMP_PATH)/lib
+dss_app_utils_OBJPATH = $(dss_app_utils_RELPATH)/app_utils_nonos
+dss_app_utils_MAKEFILE = -fmakefile
+export dss_app_utils_LIBNAME
+export dss_app_utils_LIBPATH
+export dss_app_utils_MAKEFILE
+export dss_app_utils_OBJPATH
+dss_app_utils_BOARD_DEPENDENCY = yes
+dss_app_utils_CORE_DEPENDENCY = yes
+export dss_app_utils_COMP_LIST
+export dss_app_utils_BOARD_DEPENDENCY
+export dss_app_utils_CORE_DEPENDENCY
+dss_app_utils_PKG_LIST = dss_app_utils
+dss_app_utils_INCLUDE = $(dss_app_utils_PATH)
+dss_app_utils_SOCLIST = $(drvdss_SOCLIST)
+export dss_app_utils_SOCLIST
+dss_app_utils_$(SOC)_CORELIST = $(drvdss_$(SOC)_CORELIST)
+export dss_app_utils_$(SOC)_CORELIST
+
+dss_app_utils_sysbios_COMP_LIST = dss_app_utils_sysbios
+dss_app_utils_sysbios_RELPATH = ti/drv/dss/examples/utils
+dss_app_utils_sysbios_PATH = $(PDK_DSS_COMP_PATH)/examples/utils
+dss_app_utils_sysbios_LIBNAME = dss_app_utils_sysbios
+dss_app_utils_sysbios_LIBPATH = $(PDK_DSS_COMP_PATH)/lib
+dss_app_utils_sysbios_OBJPATH = $(dss_app_utils_sysbios_RELPATH)/app_utils_sysbios
+dss_app_utils_sysbios_MAKEFILE = -fmakefile_sysbios
+export dss_app_utils_sysbios_LIBNAME
+export dss_app_utils_sysbios_LIBPATH
+export dss_app_utils_sysbios_MAKEFILE
+export dss_app_utils_sysbios_OBJPATH
+dss_app_utils_sysbios_BOARD_DEPENDENCY = yes
+dss_app_utils_sysbios_CORE_DEPENDENCY = yes
+export dss_app_utils_sysbios_COMP_LIST
+export dss_app_utils_sysbios_BOARD_DEPENDENCY
+export dss_app_utils_sysbios_CORE_DEPENDENCY
+dss_app_utils_sysbios_PKG_LIST = dss_app_utils_sysbios
+dss_app_utils_sysbios_INCLUDE = $(dss_app_utils_sysbios_PATH)
+dss_app_utils_sysbios_SOCLIST = $(drvdss_SOCLIST)
+export dss_app_utils_sysbios_SOCLIST
+dss_app_utils_sysbios_$(SOC)_CORELIST = $(drvdss_$(SOC)_CORELIST)
+export dss_app_utils_sysbios_$(SOC)_CORELIST
+
+dss_APP_LIB_LIST += dss_app_utils dss_app_utils_sysbios
+
+#
+# DSS Examples
+#
+
+# DSS colorbar test app
+dss_colorbar_testapp_COMP_LIST = dss_colorbar_testapp
+dss_colorbar_testapp_RELPATH = ti/drv/dss/examples/dss_colorbar_test
+dss_colorbar_testapp_PATH = $(PDK_DSS_COMP_PATH)/examples/dss_colorbar_test
+dss_colorbar_testapp_BOARD_DEPENDENCY = yes
+dss_colorbar_testapp_CORE_DEPENDENCY = yes
+dss_colorbar_testapp_XDC_CONFIGURO = yes
+export dss_colorbar_testapp_COMP_LIST
+export dss_colorbar_testapp_BOARD_DEPENDENCY
+export dss_colorbar_testapp_CORE_DEPENDENCY
+export dss_colorbar_testapp_XDC_CONFIGURO
+dss_colorbar_testapp_PKG_LIST = dss_colorbar_testapp
+dss_colorbar_testapp_INCLUDE = $(dss_colorbar_testapp_PATH)
+dss_colorbar_testapp_BOARDLIST = $(drvdss_BOARDLIST)
+export dss_colorbar_testapp_BOARDLIST
+dss_colorbar_testapp_$(SOC)_CORELIST = $(drvdss_$(SOC)_CORELIST)
+export dss_colorbar_testapp_$(SOC)_CORELIST
+dss_EXAMPLE_LIST += dss_colorbar_testapp
+ifeq ($(SOC),$(filter $(SOC), am65xx j721e))
+dss_colorbar_testapp_SBL_APPIMAGEGEN = yes
+export dss_colorbar_testapp_SBL_APPIMAGEGEN
+endif
+
+# DSS display test app
+dss_display_testapp_COMP_LIST = dss_display_testapp
+dss_display_testapp_RELPATH = ti/drv/dss/examples/dss_display_test
+dss_display_testapp_PATH = $(PDK_DSS_COMP_PATH)/examples/dss_display_test
+dss_display_testapp_BOARD_DEPENDENCY = yes
+dss_display_testapp_CORE_DEPENDENCY = yes
+dss_display_testapp_XDC_CONFIGURO = yes
+export dss_display_testapp_COMP_LIST
+export dss_display_testapp_BOARD_DEPENDENCY
+export dss_display_testapp_CORE_DEPENDENCY
+export dss_display_testapp_XDC_CONFIGURO
+dss_display_testapp_PKG_LIST = dss_display_testapp
+dss_display_testapp_INCLUDE = $(dss_display_testapp_PATH)
+dss_display_testapp_BOARDLIST = $(drvdss_BOARDLIST)
+export dss_display_testapp_BOARDLIST
+dss_display_testapp_$(SOC)_CORELIST = $(drvdss_$(SOC)_CORELIST)
+export dss_display_testapp_$(SOC)_CORELIST
+dss_EXAMPLE_LIST += dss_display_testapp
+ifeq ($(SOC),$(filter $(SOC), am65xx j721e))
+dss_display_testapp_SBL_APPIMAGEGEN = yes
+export dss_display_testapp_SBL_APPIMAGEGEN
+endif
+
+# DSS display baremetal test app
+dss_baremetal_display_testapp_COMP_LIST = dss_baremetal_display_testapp
+dss_baremetal_display_testapp_RELPATH = ti/drv/dss/examples/dss_display_test
+dss_baremetal_display_testapp_PATH = $(PDK_DSS_COMP_PATH)/examples/dss_display_test
+dss_baremetal_display_testapp_MAKEFILE = -fmakefile_baremetal
+export dss_baremetal_display_testapp_MAKEFILE
+dss_baremetal_display_testapp_BOARD_DEPENDENCY = yes
+dss_baremetal_display_testapp_CORE_DEPENDENCY = yes
+export dss_baremetal_display_testapp_COMP_LIST
+export dss_baremetal_display_testapp_BOARD_DEPENDENCY
+export dss_baremetal_display_testapp_CORE_DEPENDENCY
+dss_baremetal_display_testapp_PKG_LIST = dss_baremetal_display_testapp
+dss_baremetal_display_testapp_INCLUDE = $(dss_baremetal_display_testapp_PATH)
+dss_baremetal_display_testapp_BOARDLIST = $(drvdss_BOARDLIST)
+export dss_baremetal_display_testapp_BOARDLIST
+dss_baremetal_display_testapp_$(SOC)_CORELIST = $(drvdss_$(SOC)_CORELIST)
+export dss_baremetal_display_testapp_$(SOC)_CORELIST
+dss_EXAMPLE_LIST += dss_baremetal_display_testapp
+ifeq ($(SOC),$(filter $(SOC), am65xx j721e))
+dss_baremetal_display_testapp_SBL_APPIMAGEGEN = yes
+export dss_baremetal_display_testapp_SBL_APPIMAGEGEN
+endif
+
+export dss_LIB_LIST
+export dss_APP_LIB_LIST
+export dss_EXAMPLE_LIST
+export drvdss_LIB_LIST = $(dss_LIB_LIST)
+export drvdss_APP_LIB_LIST = $(dss_APP_LIB_LIST)
+export drvdss_EXAMPLE_LIST = $(dss_EXAMPLE_LIST)
+
+DSS_CFLAGS = $(FVID2_CFLAGS)
+
+export DSS_CFLAGS
+
+dss_component_make_include := 1
+endif
diff --git a/packages/ti/drv/dss/dssver.h b/packages/ti/drv/dss/dssver.h
--- /dev/null
@@ -0,0 +1,69 @@
+#ifndef DSSVER_H_
+#define DSSVER_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* ============================================================= */
+/**
+ * @file dssver.h
+ *
+ * path ti/drv/dss/dssver.h
+ *
+ * @brief DSS Version Definitions
+ *
+ * ============================================================
+ * Copyright (c) Texas Instruments Incorporated 2019
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+/**
+ * @brief This is the DSS Version. Versions numbers are encoded in the following
+ * format:
+ * 0xAABBCCDD -> Arch (AA); API Changes (BB); Major (CC); Minor (DD)
+ */
+#define DSS_VERSION_ID (0x01000004)
+
+/**
+ * @brief This is the version string which describes the DSS along with the
+ * date and build information.
+ */
+#define DSS_VERSION_STR "Dss Revision: 01.00.00.03"
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* DSSVER_H_ */
diff --git a/packages/ti/drv/dss/dssver.h.xdt b/packages/ti/drv/dss/dssver.h.xdt
--- /dev/null
@@ -0,0 +1,101 @@
+%%{
+/*!
+ * This template implements the dssver.h
+ */
+ /* Versioning */
+ var ver = this;
+ var ver1 = [00,00,00,00];
+ var ver2 = [00,00,00,00];
+
+ for each(i=0;i<ver.length;i++)
+ {
+ if(String(ver[i]).length < 2)
+ {
+ ver1[i]="0"+ver[i];
+ }
+ else
+ {
+ ver1[i] = ver[i];
+ }
+
+ ver2[i] = Number(ver[i]).toString(16).toUpperCase();
+
+ if(String(ver2[i]).length < 2)
+ {
+ ver2[i]="0"+ver2[i];
+ }
+ }
+
+ var versionStr = "\""+"Dss Revision: "+ver1[0]+"."+ver1[1]+"."+ver1[2]+"."+ver1[3]+"\"";
+ var versionID = "(0x"+ver2[0]+ver2[1]+ver2[2]+ver2[3]+")";
+
+%%}
+#ifndef DSSVER_H_
+#define DSSVER_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* ============================================================= */
+/**
+ * @file dssver.h
+ *
+ * path ti/drv/dss/dssver.h
+ *
+ * @brief DSS Version Definitions
+ *
+ * ============================================================
+ * Copyright (c) Texas Instruments Incorporated 2019
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+/**
+ * @brief This is the DSS Version. Versions numbers are encoded in the following
+ * format:
+ * 0xAABBCCDD -> Arch (AA); API Changes (BB); Major (CC); Minor (DD)
+ */
+#define DSS_VERSION_ID (0x01000003)
+
+/**
+ * @brief This is the version string which describes the DSS along with the
+ * date and build information.
+ */
+#define DSS_VERSION_STR "Dss Revision: 01.00.00.03"
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* DSSVER_H_ */
diff --git a/packages/ti/drv/dss/examples/dss_colorbar_test/dss_colorbar_test.c b/packages/ti/drv/dss/examples/dss_colorbar_test/dss_colorbar_test.c
--- /dev/null
@@ -0,0 +1,340 @@
+/*
+ * Copyright (c) Texas Instruments Incorporated 2018
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * \file dss_colorbar_test.c
+ *
+ * \brief DSS colorbar application that display colorbar present in the DSS.
+ */
+
+/* ========================================================================== */
+/* Include Files */
+/* ========================================================================== */
+
+#include <stdio.h>
+#include <dss_colorbar_test.h>
+#include <ti/drv/uart/UART.h>
+#include <ti/drv/uart/UART_stdio.h>
+
+/* ========================================================================== */
+/* Macros & Typedefs */
+/* ========================================================================== */
+
+#if defined (SOC_AM65XX)
+#define TEST_VP_ID (CSL_DSS_VP_ID_1)
+#define TEST_OVERLAY_ID (CSL_DSS_OVERLAY_ID_1)
+#else
+#define TEST_VP_ID (CSL_DSS_VP_ID_2)
+#define TEST_OVERLAY_ID (CSL_DSS_OVERLAY_ID_2)
+#endif
+
+/* ========================================================================== */
+/* Structure Declarations */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/* Function Declarations */
+/* ========================================================================== */
+
+static void DispApp_init(DispApp_Obj *appObj);
+static void DispApp_deInit(DispApp_Obj *appObj);
+static void DispApp_create(DispApp_Obj *appObj);
+static void DispApp_delete(DispApp_Obj *appObj);
+static int32_t DispApp_configDctrl(DispApp_Obj *appObj);
+static int32_t DispApp_runTest(DispApp_Obj *appObj);
+
+/* ========================================================================== */
+/* Global Variables */
+/* ========================================================================== */
+
+DispApp_Obj gDispApp_Obj;
+
+/* ========================================================================== */
+/* Function Definitions */
+/* ========================================================================== */
+
+/*
+ * DSS colorbar test
+ */
+int32_t Dss_colorbarTest(void)
+{
+ int32_t retVal = FVID2_SOK;
+
+ DispApp_init(&gDispApp_Obj);
+
+ App_print("DSS colorbar application started...\r\n");
+
+ retVal = DispApp_runTest(&gDispApp_Obj);
+
+ DispApp_deInit(&gDispApp_Obj);
+
+ if(FVID2_SOK == retVal)
+ {
+ App_print("DSS colorbar test Passed!!\r\n");
+ }
+ else
+ {
+ App_print("DSS colorbar test Failed!!\r\n");
+ }
+
+ return (0);
+}
+
+static void DispApp_init(DispApp_Obj *appObj)
+{
+ int32_t retVal = FVID2_SOK;
+ Fvid2_InitPrms initPrms;
+
+ Fvid2InitPrms_init(&initPrms);
+ initPrms.printFxn = &App_print;
+ retVal = Fvid2_init(&initPrms);
+ if(retVal != FVID2_SOK)
+ {
+ App_print("Fvid2 Init Failed!!!\r\n");
+ }
+
+ Dss_initParamsInit(&appObj->initParams);
+ Dss_init(&appObj->initParams);
+
+ if(FVID2_SOK == retVal)
+ {
+ /* Create DCTRL handle, used for common driver configuration */
+ appObj->dctrlHandle = Fvid2_create(
+ DSS_DCTRL_DRV_ID,
+ DSS_DCTRL_INST_0,
+ NULL,
+ NULL,
+ NULL);
+ if(NULL == appObj->dctrlHandle)
+ {
+ App_print("DCTRL Create Failed!!!\r\n");
+ }
+ }
+
+ if(FVID2_SOK == retVal)
+ {
+ App_print("DispApp_init() - DONE !!!\r\n");
+ }
+
+ return;
+}
+
+static void DispApp_deInit(DispApp_Obj *appObj)
+{
+ int32_t retVal = FVID2_SOK;
+
+ /* Delete DCTRL handle */
+ retVal = Fvid2_delete(appObj->dctrlHandle, NULL);
+ retVal += Dss_deInit();
+ retVal += Fvid2_deInit(NULL);
+ if(retVal != FVID2_SOK)
+ {
+ App_print("DCTRL handle delete failed!!!\r\n");
+ }
+ else
+ {
+ App_print("DispApp_deInit() - DONE !!!\r\n");
+ }
+
+ return;
+}
+
+static int32_t DispApp_runTest(DispApp_Obj *appObj)
+{
+ int32_t retVal = FVID2_SOK;
+
+ /* Create driver */
+ DispApp_create(appObj);
+
+ App_print("Starting display ... !!!\r\n");
+ App_print("Display in progress ... DO NOT HALT !!!\r\n");
+
+#if defined (SIMULATOR)
+ volatile uint32_t loop = 0xffffffU;
+ while (0U != loop--);
+#else
+ Osal_delay(OSAL_DELAY_COUNT);
+#endif
+
+ if(FVID2_SOK == retVal)
+ {
+ /* Delete driver */
+ DispApp_delete(appObj);
+ }
+
+ return retVal;
+}
+
+static void DispApp_create(DispApp_Obj *appObj)
+{
+ int32_t retVal = FVID2_SOK;
+ Dss_DctrlVpParams *vpParams;
+
+ vpParams = &appObj->vpParams;
+ Dss_dctrlVpParamsInit(vpParams);
+
+ vpParams->vpId = TEST_VP_ID;
+#if defined (SOC_AM65XX)
+ vpParams->lcdOpTimingCfg.mInfo.standard = FVID2_STD_CUSTOM;
+ vpParams->lcdOpTimingCfg.mInfo.width = DISP_APP_LCD_WIDTH;
+ vpParams->lcdOpTimingCfg.mInfo.height = DISP_APP_LCD_HEIGHT;
+ vpParams->lcdOpTimingCfg.mInfo.hFrontPorch = 48U;
+ vpParams->lcdOpTimingCfg.mInfo.hBackPorch = 80U;
+ vpParams->lcdOpTimingCfg.mInfo.hSyncLen = 32U;
+ vpParams->lcdOpTimingCfg.mInfo.vFrontPorch = 3U;
+ vpParams->lcdOpTimingCfg.mInfo.vBackPorch = 14U;
+ vpParams->lcdOpTimingCfg.mInfo.vSyncLen = 6U;
+#else
+ vpParams->lcdOpTimingCfg.mInfo.standard = FVID2_STD_1080P_60;
+#endif
+ vpParams->lcdOpTimingCfg.dvoFormat = FVID2_DV_GENERIC_DISCSYNC;
+ vpParams->lcdOpTimingCfg.videoIfWidth = FVID2_VIFW_24BIT;
+
+ vpParams->lcdPolarityCfg.actVidPolarity = FVID2_POL_HIGH;
+ vpParams->lcdPolarityCfg.pixelClkPolarity = FVID2_EDGE_POL_FALLING;
+ vpParams->lcdPolarityCfg.hsPolarity = FVID2_POL_HIGH;
+ vpParams->lcdPolarityCfg.vsPolarity = FVID2_POL_HIGH;
+
+ DispApp_configDctrl(appObj);
+
+ if(FVID2_SOK == retVal)
+ {
+ App_print("Display create complete!!\r\n");
+ }
+
+ return;
+}
+
+static void DispApp_delete(DispApp_Obj *appObj)
+{
+ int32_t retVal;
+ Dss_DctrlVpParams *vpParams;
+
+ vpParams = &appObj->vpParams;
+
+ retVal = Fvid2_control(
+ appObj->dctrlHandle,
+ IOCTL_DSS_DCTRL_STOP_VP,
+ vpParams,
+ NULL);
+ if(FVID2_SOK != retVal)
+ {
+ App_print("VP Stop Failed!!!\r\n");
+ }
+
+ if(FVID2_SOK == retVal)
+ {
+ App_print("Display delete complete!!\r\n");
+ }
+
+ return;
+}
+
+static int32_t DispApp_configDctrl(DispApp_Obj *appObj)
+{
+ int32_t retVal = FVID2_SOK;
+ Dss_DctrlVpParams *vpParams;
+ Dss_DctrlOverlayParams *overlayParams;
+#if defined (SOC_AM65XX)
+ Dss_DctrlOldiParams *oldiParams;
+ oldiParams = &appObj->oldiParams;
+ Dss_dctrlOldiParamsInit(oldiParams);
+#endif
+
+ vpParams = &appObj->vpParams;
+ overlayParams = &appObj->overlayParams;
+ Dss_dctrlOverlayParamsInit(overlayParams);
+
+ retVal = Fvid2_control(
+ appObj->dctrlHandle,
+ IOCTL_DSS_DCTRL_SET_VP_PARAMS,
+ vpParams,
+ NULL);
+ if(retVal != FVID2_SOK)
+ {
+ App_print("Dctrl Set VP Params IOCTL Failed!!!\r\n");
+ }
+
+#if defined (SOC_AM65XX)
+ retVal = Fvid2_control(
+ appObj->dctrlHandle,
+ IOCTL_DSS_DCTRL_SET_OLDI_PARAMS,
+ oldiParams,
+ NULL);
+ if(retVal != FVID2_SOK)
+ {
+ App_print("DCTRL Set OLDI Params IOCTL Failed!!!\r\n");
+ }
+#endif
+
+#if defined (SOC_J721E)
+ uint32_t regVal2;
+
+ /* Select DPI0 connection */
+ regVal2 = CSL_REG32_RD(CSL_DSS0_DISPC_0_COMMON_M_BASE +
+ CSL_DSS_COMMON_M_DISPC_CONNECTIONS);
+ CSL_FINS(regVal2,
+ DSS_COMMON_M_DISPC_CONNECTIONS_DPI_0_CONN,
+ CSL_DSS_COMMON_M_DISPC_CONNECTIONS_DPI_0_CONN_VAL_VP2);
+ CSL_REG32_WR(CSL_DSS0_DISPC_0_COMMON_M_BASE +
+ CSL_DSS_COMMON_M_DISPC_CONNECTIONS, regVal2);
+#endif
+
+ overlayParams->overlayId = TEST_OVERLAY_ID;
+ overlayParams->colorbarEnable = TRUE;
+
+ retVal = Fvid2_control(
+ appObj->dctrlHandle,
+ IOCTL_DSS_DCTRL_SET_OVERLAY_PARAMS,
+ overlayParams,
+ NULL);
+ if(retVal != FVID2_SOK)
+ {
+ App_print("DCTRL Set Overlay Params IOCTL Failed!!!\r\n");
+ }
+
+ return (retVal);
+}
+
+void App_print(const char *format, ...)
+{
+ va_list vaArgPtr;
+ va_start(vaArgPtr, format);
+
+ DSS_log(format, vaArgPtr);
+ va_end(vaArgPtr);
+
+ return;
+}
diff --git a/packages/ti/drv/dss/examples/dss_colorbar_test/dss_colorbar_test.h b/packages/ti/drv/dss/examples/dss_colorbar_test/dss_colorbar_test.h
--- /dev/null
@@ -0,0 +1,134 @@
+/*
+ * Copyright (c) Texas Instruments Incorporated 2018
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * \file dss_colorbar_test.h
+ *
+ * \brief DSS Colorbar Test Header file.
+ */
+
+#ifndef DSS_COLORBAR_TEST_H_
+#define DSS_COLORBAR_TEST_H_
+
+/* ========================================================================== */
+/* Include Files */
+/* ========================================================================== */
+
+#include <ti/drv/dss/dss.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* ========================================================================== */
+/* Macros & Typedefs */
+/* ========================================================================== */
+
+#if defined (SIMULATOR)
+#define OSAL_DELAY_COUNT (10U)
+#else
+#define OSAL_DELAY_COUNT (1000U)
+#endif
+
+#define DISP_APP_LCD_WIDTH (1280U)
+#define DISP_APP_LCD_HEIGHT (800U)
+
+/* Enable the below macro to have prints on the IO Console */
+#undef CIO_CONSOLE
+
+#ifndef CIO_CONSOLE
+#define DSS_log UART_printf
+#else
+#define DSS_log printf
+#endif
+
+/* ========================================================================== */
+/* Structure Declarations */
+/* ========================================================================== */
+
+/**
+ * \brief Test application data structure.
+ */
+typedef struct
+{
+ Fvid2_Handle dctrlHandle;
+ /**< DCTRL handle */
+ Dss_InitParams initParams;
+ /**< DSS Initialization Parameters */
+ Dss_DctrlVpParams vpParams;
+ /**< VP Params */
+ Dss_DctrlOverlayParams overlayParams;
+ /**< Overlay Params */
+#if defined (SOC_AM65XX)
+ Dss_DctrlOldiParams oldiParams;
+ /**< OLDI Params */
+#endif
+} DispApp_Obj;
+
+/* ========================================================================== */
+/* Internal/Private Function Declarations */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/* Function Declarations */
+/* ========================================================================== */
+
+void App_print(const char *format, ...);
+
+/* ========================================================================== */
+/* Global Variables */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/* Internal Function Declarations (Needed for other static inlines) */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/* Static Function Definitions */
+/* ========================================================================== */
+
+/* None */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #ifndef DSS_COLORBAR_TEST_H_ */
+
+/* @} */
diff --git a/packages/ti/drv/dss/examples/dss_colorbar_test/main_tirtos.c b/packages/ti/drv/dss/examples/dss_colorbar_test/main_tirtos.c
--- /dev/null
@@ -0,0 +1,143 @@
+/*
+ * Copyright (c) Texas Instruments Incorporated 2018
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * \file main_tirtos.c
+ *
+ * \brief Main file for TI-RTOS build
+ */
+
+/* ========================================================================== */
+/* Include Files */
+/* ========================================================================== */
+
+#include <stdio.h>
+/* XDCtools Header files */
+#include <xdc/std.h>
+#include <xdc/runtime/Error.h>
+#include <xdc/runtime/System.h>
+/* BIOS Header files */
+#include <ti/sysbios/BIOS.h>
+#include <ti/sysbios/knl/Task.h>
+#include <ti/board/board.h>
+#include <ti/drv/dss/examples/utils/app_utils.h>
+#include "dss_colorbar_test.h"
+
+/* ========================================================================== */
+/* Macros & Typedefs */
+/* ========================================================================== */
+
+/* Test application stack size */
+#define DISP_APP_TSK_STACK_MAIN (10U * 1024U)
+
+/* ========================================================================== */
+/* Structure Declarations */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/* Function Declarations */
+/* ========================================================================== */
+
+static Void taskFxn(UArg a0, UArg a1);
+extern int32_t Dss_colorbarTest(void);
+
+/* ========================================================================== */
+/* Global Variables */
+/* ========================================================================== */
+
+/* Test application stack */
+static uint8_t gDispAppTskStackMain[DISP_APP_TSK_STACK_MAIN];
+
+/* ========================================================================== */
+/* Function Definitions */
+/* ========================================================================== */
+
+int main(void)
+{
+ Task_Handle task;
+ Error_Block eb;
+ Task_Params taskParams;
+
+ Error_init(&eb);
+
+ /* Initialize the task params */
+ Task_Params_init(&taskParams);
+ /* Set the task priority higher than the default priority (1) */
+ taskParams.priority = 2;
+ taskParams.stack = gDispAppTskStackMain;
+ taskParams.stackSize = sizeof(gDispAppTskStackMain);
+
+ task = Task_create(taskFxn, &taskParams, &eb);
+ if(NULL == task)
+ {
+ BIOS_exit(0);
+ }
+ BIOS_start(); /* does not return */
+
+ return(0);
+}
+
+static Void taskFxn(UArg a0, UArg a1)
+{
+ Board_initCfg boardCfg;
+
+ boardCfg = BOARD_INIT_PINMUX_CONFIG |
+ BOARD_INIT_UNLOCK_MMR |
+ BOARD_INIT_UART_STDIO;
+ Board_init(boardCfg);
+
+#if defined (SOC_AM65XX)
+ App_configureLCD(APP_OUTPUT_OLDI);
+#else
+#if (1U == DISP_APP_TEST_EDP)
+ App_configureLCD(APP_OUTPUT_EDP);
+#else
+ App_configureLCD(APP_OUTPUT_HDMI);
+#endif
+#endif
+ App_configureSoC();
+
+ Dss_colorbarTest();
+
+ return;
+}
+
+#if defined(BUILD_MPU) || defined (__C7100__)
+extern void Osal_initMmuDefault(void);
+void InitMmu(void)
+{
+ Osal_initMmuDefault();
+}
+#endif
diff --git a/packages/ti/drv/dss/examples/dss_colorbar_test/makefile b/packages/ti/drv/dss/examples/dss_colorbar_test/makefile
--- /dev/null
@@ -0,0 +1,50 @@
+#
+# This file is the makefile for building DSS colorbar test app for TI RTOS
+#
+ifeq ($(RULES_MAKE), )
+include $(PDK_INSTALL_PATH)/ti/build/Rules.make
+else
+include $(RULES_MAKE)
+endif
+
+APP_NAME = dss_colorbar_testapp
+
+SRCDIR = .
+INCDIR = .
+
+# List all the external components/interfaces, whose interface header files
+# need to be included for this component
+INCLUDE_EXTERNAL_INTERFACES = pdk
+
+# List all the components required by the application
+COMP_LIST_COMMON = csl fvid2 dss dss_app_utils
+COMP_LIST_COMMON += board uart sciclient pm_lib i2c
+
+INCLUDE_EXTERNAL_INTERFACES += xdc bios
+COMP_LIST_COMMON += osal_tirtos
+SRCS_COMMON = main_tirtos.c
+# Enable XDC build for application by providing XDC CFG File per core
+XDC_CFG_FILE_$(CORE) = $(PDK_INSTALL_PATH)/ti/build/$(SOC)/sysbios_$(ISA).cfg
+
+# Common source files and CFLAGS across all platforms and cores
+PACKAGE_SRCS_COMMON = .
+SRCS_COMMON += dss_colorbar_test.c
+CFLAGS_LOCAL_COMMON += $(PDK_CFLAGS) $(DSS_CFLAGS)
+
+# Core/SoC/platform specific source files and CFLAGS
+# Example:
+# SRCS_<core/SoC/platform-name> =
+# CFLAGS_LOCAL_<core/SoC/platform-name> =
+
+# Include common make files
+ifeq ($(MAKERULEDIR), )
+#Makerule path not defined, define this and assume relative path from ROOTDIR
+ MAKERULEDIR := $(ROOTDIR)/ti/build/makerules
+ export MAKERULEDIR
+endif
+include $(MAKERULEDIR)/common.mk
+
+# OBJs and libraries are built by using rule defined in rules_<target>.mk
+# and need not be explicitly specified here
+
+# Nothing beyond this point
diff --git a/packages/ti/drv/dss/examples/dss_display_test/dss_display_buffer1.h b/packages/ti/drv/dss/examples/dss_display_test/dss_display_buffer1.h
--- /dev/null
@@ -0,0 +1,172899 @@
+/*
+ * Copyright (c) Texas Instruments Incorporated 2018
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * \file dss_display_buffer1.h
+ *
+ * \brief DSS Display buffer size 480x360 BGRA8888 format
+ */
+
+#ifndef DSS_DISPLAY_BUFFER1_H_
+#define DSS_DISPLAY_BUFFER1_H_
+
+/* ========================================================================== */
+/* Include Files */
+/* ========================================================================== */
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* ========================================================================== */
+/* Macros & Typedefs */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/* Structure Declarations */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/* Function Declarations */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/* Static Function Declarations */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/* Global Variables */
+/* ========================================================================== */
+
+const uint32_t gDispArray1[] __attribute__((section(".data_buffer")));
+const uint32_t gDispArray1[] __attribute__((aligned (4096)));
+const uint32_t gDispArray1[] = {
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
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+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6
+};
+
+
+/* ========================================================================== */
+/* Static Function Definitions */
+/* ========================================================================== */
+
+/* None */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #ifndef DSS_DISPLAY_BUFFER1_H_ */
+
+/* @} */
diff --git a/packages/ti/drv/dss/examples/dss_display_test/dss_display_buffer2.h b/packages/ti/drv/dss/examples/dss_display_test/dss_display_buffer2.h
--- /dev/null
@@ -0,0 +1,172898 @@
+/*
+ * Copyright (c) Texas Instruments Incorporated 2018
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * \file dss_display_buffer2.h
+ *
+ * \brief DSS Display buffer size 480x360 BGRA8888 format
+ */
+
+#ifndef DSS_DISPLAY_BUFFER2_H_
+#define DSS_DISPLAY_BUFFER2_H_
+
+/* ========================================================================== */
+/* Include Files */
+/* ========================================================================== */
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* ========================================================================== */
+/* Macros & Typedefs */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/* Structure Declarations */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/* Function Declarations */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/* Static Function Declarations */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/* Global Variables */
+/* ========================================================================== */
+
+const uint32_t gDispArray2[] __attribute__((section(".data_buffer")));
+const uint32_t gDispArray2[] __attribute__((aligned (4096)));
+const uint32_t gDispArray2[] = {
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
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+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
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+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
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+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
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+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6,
+ 0xFFB6B5B6
+};
+
+/* ========================================================================== */
+/* Static Function Definitions */
+/* ========================================================================== */
+
+/* None */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #ifndef DSS_DISPLAY_BUFFER2_H_ */
+
+/* @} */
diff --git a/packages/ti/drv/dss/examples/dss_display_test/dss_display_test.c b/packages/ti/drv/dss/examples/dss_display_test/dss_display_test.c
--- /dev/null
@@ -0,0 +1,1015 @@
+/*
+ * Copyright (c) Texas Instruments Incorporated 2018
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * \file dss_display_test.c
+ *
+ * \brief DSS sample application that displays two ARGB32 buffers.
+ */
+
+/* ========================================================================== */
+/* Include Files */
+/* ========================================================================== */
+
+#include <stdio.h>
+#include <string.h>
+#include <dss_display_test.h>
+#include <dss_display_buffer1.h>
+#include <dss_display_buffer2.h>
+#include <ti/drv/uart/UART.h>
+#include <ti/drv/uart/UART_stdio.h>
+
+#if !defined(DSS_TESTAPP_BAREMETAL)
+#include <ti/drv/dss/examples/utils/app_utils_prf.h>
+#endif
+
+
+/* ========================================================================== */
+/* Macros & Typedefs */
+/* ========================================================================== */
+
+#if defined (SOC_AM65XX)
+#define TEST_VP_ID (CSL_DSS_VP_ID_1)
+#define TEST_OVERLAY_ID (CSL_DSS_OVERLAY_ID_1)
+#define TEST_DCTRL_OVERLAY_NODE_ID (DSS_DCTRL_NODE_OVERLAY1)
+#define TEST_DCTRL_VP_NODE_ID (DSS_DCTRL_NODE_VP1)
+#define TEST_DCTRL_OUT_NODE_ID (DSS_DCTRL_NODE_OLDI)
+#else
+#if(1U == DISP_APP_TEST_EDP)
+#define TEST_VP_ID (CSL_DSS_VP_ID_1)
+#define TEST_OVERLAY_ID (CSL_DSS_OVERLAY_ID_1)
+#define TEST_DCTRL_OVERLAY_NODE_ID (DSS_DCTRL_NODE_OVERLAY1)
+#define TEST_DCTRL_VP_NODE_ID (DSS_DCTRL_NODE_VP1)
+#define TEST_DCTRL_OUT_NODE_ID (DSS_DCTRL_NODE_EDP_DPI0)
+#elif(1U == DISP_APP_TEST_OVERLAY_VP_4)
+#define TEST_VP_ID (CSL_DSS_VP_ID_4)
+#define TEST_OVERLAY_ID (CSL_DSS_OVERLAY_ID_4)
+#define TEST_DCTRL_OVERLAY_NODE_ID (DSS_DCTRL_NODE_OVERLAY4)
+#define TEST_DCTRL_VP_NODE_ID (DSS_DCTRL_NODE_VP4)
+#define TEST_DCTRL_OUT_NODE_ID (DSS_DCTRL_NODE_DPI_DPI0)
+#else
+#define TEST_VP_ID (CSL_DSS_VP_ID_2)
+#define TEST_OVERLAY_ID (CSL_DSS_OVERLAY_ID_2)
+#define TEST_DCTRL_OVERLAY_NODE_ID (DSS_DCTRL_NODE_OVERLAY2)
+#define TEST_DCTRL_VP_NODE_ID (DSS_DCTRL_NODE_VP2)
+#define TEST_DCTRL_OUT_NODE_ID (DSS_DCTRL_NODE_DPI_DPI0)
+#if(1U == DISP_APP_TEST_MULTISYNC)
+#define TEST_SYNC_VP_ID (CSL_DSS_VP_ID_1)
+#define TEST_DCTRL_SYNC_VP_NODE_ID (DSS_DCTRL_NODE_VP1)
+#define TEST_DCTRL_SYNC_OUT_NODE_ID (DSS_DCTRL_NODE_DISCSYNC0)
+#endif
+#endif
+#endif
+
+/* ========================================================================== */
+/* Structure Declarations */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/* Function Declarations */
+/* ========================================================================== */
+
+static void DispApp_init(DispApp_Obj *appObj);
+static void DispApp_deInit(DispApp_Obj *appObj);
+static void DispApp_create(DispApp_Obj *appObj);
+static void DispApp_delete(DispApp_Obj *appObj);
+static int32_t DispApp_configDctrl(DispApp_Obj *appObj);
+static int32_t DispApp_runTest(DispApp_Obj *appObj);
+static void DispApp_initParams(DispApp_Obj *appObj);
+static int32_t DispApp_allocAndQueueFrames(const DispApp_Obj *appObj,
+ DispApp_InstObj *instObj);
+static int32_t DispApp_pipeCbFxn(Fvid2_Handle handle, void *appData);
+
+/* ========================================================================== */
+/* Global Variables */
+/* ========================================================================== */
+
+DispApp_Obj gDispApp_Obj;
+#if !defined(DSS_TESTAPP_BAREMETAL)
+uint32_t gTestStopTime, gTestStartTime;
+#endif
+
+/* ========================================================================== */
+/* Function Definitions */
+/* ========================================================================== */
+
+/*
+ * DSS display test
+ */
+int32_t Dss_displayTest(void)
+{
+ int32_t retVal = FVID2_SOK;
+ DispApp_init(&gDispApp_Obj);
+
+ App_print("DSS display application started...\r\n");
+
+#if !defined(DSS_TESTAPP_BAREMETAL)
+ Utils_prfLoadCalcStart();
+ Utils_prfLoadRegister(TaskP_self(), "Display_testapp");
+#endif
+
+ retVal = DispApp_runTest(&gDispApp_Obj);
+
+#if !defined(DSS_TESTAPP_BAREMETAL)
+ Utils_prfLoadCalcStop();
+ Utils_prfLoadPrintAll(TRUE, 0);
+ Utils_prfLoadCalcReset();
+ Utils_prfLoadUnRegister(TaskP_self());
+ App_print("Number of frames = %d, elapsed msec = %d, fps = %d\n",
+ DISP_APP_RUN_COUNT,
+ gTestStopTime - gTestStartTime,
+ (uint32_t)((float)DISP_APP_RUN_COUNT / ((gTestStopTime - gTestStartTime)/1000.0)));
+
+#endif
+
+ DispApp_deInit(&gDispApp_Obj);
+
+ if(FVID2_SOK == retVal)
+ {
+ App_print("DSS display test Passed!!\r\n");
+ }
+ else
+ {
+ App_print("DSS display test Failed!!\r\n");
+ }
+
+ return (0);
+}
+
+static void DispApp_init(DispApp_Obj *appObj)
+{
+ int32_t retVal = FVID2_SOK;
+ Fvid2_InitPrms initPrms;
+
+ Fvid2InitPrms_init(&initPrms);
+ initPrms.printFxn = &App_print;
+ retVal = Fvid2_init(&initPrms);
+ if(retVal != FVID2_SOK)
+ {
+ App_print("Fvid2 Init Failed!!!\r\n");
+ }
+
+ Dss_initParamsInit(&appObj->initParams);
+#if(1U == DISP_APP_ENABLE_COMMON1_REGION)
+ appObj->initParams.socParams.irqParams.dssCommonRegionId = CSL_DSS_COMM_REG_ID_1;
+ appObj->initParams.socParams.irqParams.numValidIrq = DSS_EVT_MGR_INST_ID_MAX;
+ appObj->initParams.socParams.irqParams.irqNum[DSS_EVT_MGR_INST_ID_FUNC] = 53U;
+ appObj->initParams.socParams.irqParams.irqNum[DSS_EVT_MGR_INST_ID_SAFETY] = 55U;
+ appObj->initParams.socParams.irqParams.irqNum[DSS_EVT_MGR_INST_ID_SECURITY] = 57U;
+#endif
+#if defined (SOC_J721E)
+ appObj->initParams.socParams.dpInitParams.isHpdSupported = FALSE;
+#endif
+ Dss_init(&appObj->initParams);
+
+ if(FVID2_SOK == retVal)
+ {
+ /* Create DCTRL handle, used for common driver configuration */
+ appObj->dctrlHandle = Fvid2_create(
+ DSS_DCTRL_DRV_ID,
+ DSS_DCTRL_INST_0,
+ NULL,
+ NULL,
+ NULL);
+ if(NULL == appObj->dctrlHandle)
+ {
+ App_print("DCTRL Create Failed!!!\r\n");
+ }
+ }
+
+ if(FVID2_SOK == retVal)
+ {
+ App_print("DispApp_init() - DONE !!!\r\n");
+ }
+
+ return;
+}
+
+static void DispApp_deInit(DispApp_Obj *appObj)
+{
+ int32_t retVal = FVID2_SOK;
+
+ /* Delete DCTRL handle */
+ retVal = Fvid2_delete(appObj->dctrlHandle, NULL);
+ retVal += Dss_deInit();
+ retVal += Fvid2_deInit(NULL);
+ if(retVal != FVID2_SOK)
+ {
+ App_print("DCTRL handle delete failed!!!\r\n");
+ }
+ else
+ {
+ App_print("DispApp_deInit() - DONE !!!\r\n");
+ }
+
+ return;
+}
+
+static int32_t DispApp_runTest(DispApp_Obj *appObj)
+{
+ int32_t retVal = FVID2_SOK;
+ uint32_t instCnt = 0U;
+ volatile uint32_t loopCount = 0U;
+ DispApp_InstObj *instObj;
+ Fvid2_FrameList frmList;
+
+ /* Create driver */
+ DispApp_create(appObj);
+
+ App_print("Starting display ... !!!\r\n");
+ App_print("Display in progress ... DO NOT HALT !!!\r\n");
+
+ /* Start driver */
+ for(instCnt=0U; instCnt<gDispAppTestParams.numTestPipes; instCnt++)
+ {
+ instObj = &appObj->instObj[instCnt];
+
+ retVal = Fvid2_start(instObj->drvHandle, NULL);
+ if(retVal != FVID2_SOK)
+ {
+ App_print("Display Start Failed!!!\r\n");
+ break;
+ }
+ }
+
+#if !defined(DSS_TESTAPP_BAREMETAL)
+ gTestStartTime = AppUtils_getCurTimeInMsec();
+#endif
+
+ while(loopCount++ < DISP_APP_RUN_COUNT)
+ {
+ for(instCnt=0U; instCnt<gDispAppTestParams.numTestPipes; instCnt++)
+ {
+ instObj = &appObj->instObj[instCnt];
+ (void) SemaphoreP_pend(instObj->syncSem, SemaphoreP_WAIT_FOREVER);
+ retVal = Fvid2_dequeue(instObj->drvHandle,
+ &frmList,
+ 0U,
+ FVID2_TIMEOUT_NONE);
+
+ if(FVID2_SOK == retVal)
+ {
+ retVal = Fvid2_queue(instObj->drvHandle, &frmList, 0U);
+ if(FVID2_SOK != retVal)
+ {
+ App_print("Display Queue Failed!!!\r\n");
+ break;
+ }
+ }
+ else if (FVID2_EAGAIN == retVal)
+ {
+ /* Do nothing as this is first callback */
+ }
+ else
+ {
+ /* Error */
+ App_print("Display Dequeue Failed!!!\r\n");
+ break;
+ }
+ }
+ }
+
+ for(instCnt=0U; instCnt<gDispAppTestParams.numTestPipes; instCnt++)
+ {
+ instObj = &appObj->instObj[instCnt];
+ retVal = Fvid2_stop(instObj->drvHandle, NULL);
+ if(retVal != FVID2_SOK)
+ {
+ App_print("Display Stop Failed!!!\r\n");
+ break;
+ }
+ }
+
+#if !defined(DSS_TESTAPP_BAREMETAL)
+ gTestStopTime = AppUtils_getCurTimeInMsec();
+#endif
+
+ if(FVID2_SOK == retVal)
+ {
+ /* Delete driver */
+ DispApp_delete(appObj);
+ }
+
+ return retVal;
+}
+
+static void DispApp_create(DispApp_Obj *appObj)
+{
+ int32_t retVal = FVID2_SOK;
+ uint32_t instCnt = 0U;
+ SemaphoreP_Params semParams;
+ Dss_DctrlVpParams *vpParams;
+ Dss_DctrlAdvVpParams *advVpParams;
+ DispApp_InstObj *instObj;
+
+ DispApp_initParams(appObj);
+ vpParams = &appObj->vpParams;
+ advVpParams = &appObj->advVpParams;
+ Dss_dctrlVpParamsInit(vpParams);
+ Dss_dctrlAdvVpParamsInit(advVpParams);
+
+ vpParams->vpId = TEST_VP_ID;
+ advVpParams->vpId = TEST_VP_ID;
+
+#if defined (SOC_AM65XX)
+ vpParams->lcdOpTimingCfg.mInfo.standard = FVID2_STD_CUSTOM;
+ vpParams->lcdOpTimingCfg.mInfo.width = DISP_APP_LCD_WIDTH;
+ vpParams->lcdOpTimingCfg.mInfo.height = DISP_APP_LCD_HEIGHT;
+ vpParams->lcdOpTimingCfg.mInfo.hFrontPorch = 48U;
+ vpParams->lcdOpTimingCfg.mInfo.hBackPorch = 80U;
+ vpParams->lcdOpTimingCfg.mInfo.hSyncLen = 32U;
+ vpParams->lcdOpTimingCfg.mInfo.vFrontPorch = 3U;
+ vpParams->lcdOpTimingCfg.mInfo.vBackPorch = 14U;
+ vpParams->lcdOpTimingCfg.mInfo.vSyncLen = 6U;
+#else
+#if(1U == DISP_APP_TEST_MULTISYNC)
+ vpParams->syncOpCfg.enabled = TRUE;
+ vpParams->syncOpCfg.isPrimary = TRUE;
+ vpParams->syncOpCfg.numSyncVpIds = 1U;
+ vpParams->syncOpCfg.syncVpIds[0] = TEST_SYNC_VP_ID;
+#endif
+#if(DISP_APP_BGR24 == DISP_APP_USE_TEST_PARAMS)
+#if(1U == DISP_APP_TEST_EDP)
+ vpParams->lcdOpTimingCfg.mInfo.standard = FVID2_STD_CUSTOM;
+ vpParams->lcdOpTimingCfg.mInfo.width = 1280U;
+ vpParams->lcdOpTimingCfg.mInfo.height = 720U;
+ vpParams->lcdOpTimingCfg.mInfo.pixelClock = 74250U;
+ vpParams->lcdOpTimingCfg.mInfo.hFrontPorch = 110U;
+ vpParams->lcdOpTimingCfg.mInfo.hBackPorch = 220U;
+ vpParams->lcdOpTimingCfg.mInfo.hSyncLen = 40U;
+ vpParams->lcdOpTimingCfg.mInfo.vFrontPorch = 5U;
+ vpParams->lcdOpTimingCfg.mInfo.vBackPorch = 20U;
+ vpParams->lcdOpTimingCfg.mInfo.vSyncLen = 5U;
+#else
+ vpParams->lcdOpTimingCfg.mInfo.standard = FVID2_STD_720P_60;
+#endif
+#else
+#if(1U == DISP_APP_TEST_EDP)
+ vpParams->lcdOpTimingCfg.mInfo.standard = FVID2_STD_CUSTOM;
+ vpParams->lcdOpTimingCfg.mInfo.width = 1920U;
+ vpParams->lcdOpTimingCfg.mInfo.height = 1080U;
+ vpParams->lcdOpTimingCfg.mInfo.pixelClock = 148500U;
+ vpParams->lcdOpTimingCfg.mInfo.hFrontPorch = 88U;
+ vpParams->lcdOpTimingCfg.mInfo.hBackPorch = 148U;
+ vpParams->lcdOpTimingCfg.mInfo.hSyncLen = 44U;
+ vpParams->lcdOpTimingCfg.mInfo.vFrontPorch = 4U;
+ vpParams->lcdOpTimingCfg.mInfo.vBackPorch = 36U;
+ vpParams->lcdOpTimingCfg.mInfo.vSyncLen = 5U;
+#else
+ vpParams->lcdOpTimingCfg.mInfo.standard = FVID2_STD_1080P_60;
+#endif
+#endif
+#endif
+
+ vpParams->lcdOpTimingCfg.dvoFormat = FVID2_DV_GENERIC_DISCSYNC;
+#if(1U == DISP_APP_TEST_EDP)
+ vpParams->lcdOpTimingCfg.videoIfWidth = FVID2_VIFW_36BIT;
+#else
+ vpParams->lcdOpTimingCfg.videoIfWidth = FVID2_VIFW_24BIT;
+#endif
+ vpParams->lcdPolarityCfg.actVidPolarity = FVID2_POL_HIGH;
+ vpParams->lcdPolarityCfg.hsPolarity = FVID2_POL_HIGH;
+ vpParams->lcdPolarityCfg.vsPolarity = FVID2_POL_HIGH;
+#if(1U == DISP_APP_TEST_EDP)
+ vpParams->lcdPolarityCfg.pixelClkPolarity = FVID2_EDGE_POL_RISING;
+
+ advVpParams->lcdAdvSignalCfg.hVAlign = CSL_DSS_VP_HVSYNC_ALIGNED;
+ advVpParams->lcdAdvSignalCfg.hVClkControl = CSL_DSS_VP_HVCLK_CONTROL_ON;
+ advVpParams->lcdAdvSignalCfg.hVClkRiseFall = FVID2_EDGE_POL_RISING;
+#else
+ vpParams->lcdPolarityCfg.pixelClkPolarity = FVID2_EDGE_POL_FALLING;
+#endif
+
+#if(1U == DISP_APP_TEST_MULTISYNC)
+ vpParams = &appObj->syncVpParams;
+ advVpParams = &appObj->syncAdvVpParams;
+ Dss_dctrlVpParamsInit(vpParams);
+ Dss_dctrlAdvVpParamsInit(advVpParams);
+
+ vpParams->vpId = TEST_SYNC_VP_ID;
+ advVpParams->vpId = TEST_SYNC_VP_ID;
+
+ vpParams->syncOpCfg.enabled = TRUE;
+ vpParams->syncOpCfg.isPrimary = FALSE;
+ vpParams->syncOpCfg.numSyncVpIds = 0U;
+
+#if(DISP_APP_BGR24 == DISP_APP_USE_TEST_PARAMS)
+ vpParams->lcdOpTimingCfg.mInfo.standard = FVID2_STD_720P_60;
+#else
+ vpParams->lcdOpTimingCfg.mInfo.standard = FVID2_STD_1080P_60;
+#endif
+
+ vpParams->lcdOpTimingCfg.dvoFormat = FVID2_DV_GENERIC_DISCSYNC;
+ vpParams->lcdOpTimingCfg.videoIfWidth = FVID2_VIFW_24BIT;
+ vpParams->lcdPolarityCfg.actVidPolarity = FVID2_POL_HIGH;
+ vpParams->lcdPolarityCfg.hsPolarity = FVID2_POL_HIGH;
+ vpParams->lcdPolarityCfg.vsPolarity = FVID2_POL_HIGH;
+ vpParams->lcdPolarityCfg.pixelClkPolarity = FVID2_EDGE_POL_FALLING;
+#endif
+
+ DispApp_configDctrl(appObj);
+
+ for(instCnt=0U; instCnt<gDispAppTestParams.numTestPipes; instCnt++)
+ {
+ instObj = &appObj->instObj[instCnt];
+ SemaphoreP_Params_init(&semParams);
+ semParams.mode = SemaphoreP_Mode_BINARY;
+ instObj->syncSem = SemaphoreP_create(0U, &semParams);
+ instObj->drvHandle = Fvid2_create(
+ DSS_DISP_DRV_ID,
+ instObj->instId,
+ &instObj->createParams,
+ &instObj->createStatus,
+ &instObj->cbParams);
+ if((NULL == instObj->drvHandle) ||
+ (instObj->createStatus.retVal != FVID2_SOK))
+ {
+ App_print("Display Create Failed!!!\r\n");
+ retVal = instObj->createStatus.retVal;
+ }
+
+ if(FVID2_SOK == retVal)
+ {
+ retVal = Fvid2_control(
+ instObj->drvHandle,
+ IOCTL_DSS_DISP_SET_DSS_PARAMS,
+ &instObj->dispParams,
+ NULL);
+ if(retVal != FVID2_SOK)
+ {
+ App_print("DSS Set Params IOCTL Failed!!!\r\n");
+ }
+ }
+ if(FVID2_SOK == retVal)
+ {
+ retVal = Fvid2_control(
+ instObj->drvHandle,
+ IOCTL_DSS_DISP_SET_PIPE_MFLAG_PARAMS,
+ &instObj->mflagParams,
+ NULL);
+ if(retVal != FVID2_SOK)
+ {
+ App_print("DSS Set Mflag Params IOCTL Failed!!!\r\n");
+ }
+ }
+ if(FVID2_SOK == retVal)
+ {
+ retVal = DispApp_allocAndQueueFrames(appObj, instObj);
+ if(retVal != FVID2_SOK)
+ {
+ App_print("Display Alloc and Queue Failed!!!\r\n");
+ }
+ }
+
+ if(FVID2_SOK != retVal)
+ {
+ break;
+ }
+ }
+
+ if(FVID2_SOK == retVal)
+ {
+ App_print("Display create complete!!\r\n");
+ }
+
+ return;
+}
+
+static void DispApp_delete(DispApp_Obj *appObj)
+{
+ int32_t retVal;
+ uint32_t instCnt;
+ Dss_DctrlVpParams *vpParams;
+#if(1U == DISP_APP_TEST_MULTISYNC)
+ Dss_DctrlVpParams *syncVpParams;
+#endif
+ Dss_DctrlPathInfo *pathInfo;
+ Dss_DctrlVpErrorStats *pErrorStats;
+ DispApp_InstObj *instObj;
+ Dss_DispCurrentStatus currStatus;
+ Fvid2_FrameList frmList;
+
+ vpParams = &appObj->vpParams;
+#if(1U == DISP_APP_TEST_MULTISYNC)
+ syncVpParams = &appObj->syncVpParams;
+#endif
+ pathInfo = &appObj->dctrlPathInfo;
+ pErrorStats = &appObj->errorStats;
+
+ for(instCnt=0U; instCnt<gDispAppTestParams.numTestPipes; instCnt++)
+ {
+ instObj = &appObj->instObj[instCnt];
+
+ /* Check for DSS underflow errors */
+ retVal = Fvid2_control(
+ instObj->drvHandle,
+ IOCTL_DSS_DISP_GET_CURRENT_STATUS,
+ &currStatus,
+ NULL);
+ if(FVID2_SOK != retVal)
+ {
+ App_print("Failed to get Display Stats!!!\r\n");
+ }
+
+ /* Print Synclost errors */
+ if(0U != currStatus.underflowCount)
+ {
+ GT_2trace(DssTrace, GT_ERR, "No of Underflows for Inst %d: %d\r\n", instCnt, currStatus.underflowCount);
+ }
+ else
+ {
+ App_print("Underflow did not occur\r\n");
+ }
+
+ /* Dequeue all the request from the driver */
+ while (1U)
+ {
+ retVal = Fvid2_dequeue(
+ instObj->drvHandle,
+ &frmList,
+ 0U,
+ FVID2_TIMEOUT_NONE);
+ if(FVID2_SOK != retVal)
+ {
+ break;
+ }
+ }
+
+ retVal = Fvid2_delete(instObj->drvHandle, NULL);
+ if(FVID2_SOK != retVal)
+ {
+ App_print("Display Delete Failed!!!\r\n");
+ break;
+ }
+ }
+
+ /* Check for DSS synclost errors */
+ retVal = Fvid2_control(
+ appObj->dctrlHandle,
+ IOCTL_DSS_DCTRL_GET_VP_ERROR_STATS,
+ pErrorStats,
+ NULL);
+ if(FVID2_SOK != retVal)
+ {
+ App_print("Failed to get VP Stats!!!\r\n");
+ }
+
+ /* Print Synclost errors */
+ if(0U != pErrorStats->syncLost)
+ {
+ GT_1trace(DssTrace, GT_ERR, "No of Sync Lost: %d\r\n", pErrorStats->syncLost);
+ }
+ else
+ {
+ App_print("Sync Lost did not occur\r\n");
+ }
+
+ retVal = Fvid2_control(
+ appObj->dctrlHandle,
+ IOCTL_DSS_DCTRL_CLEAR_PATH,
+ pathInfo,
+ NULL);
+ if(FVID2_SOK != retVal)
+ {
+ App_print("Clear Path Failed!!!\r\n");
+ }
+
+#if(1U == DISP_APP_TEST_MULTISYNC)
+ retVal = Fvid2_control(
+ appObj->dctrlHandle,
+ IOCTL_DSS_DCTRL_STOP_VP,
+ syncVpParams,
+ NULL);
+ if(FVID2_SOK != retVal)
+ {
+ App_print("VP Stop Failed!!!\r\n");
+ }
+#endif
+
+ retVal = Fvid2_control(
+ appObj->dctrlHandle,
+ IOCTL_DSS_DCTRL_STOP_VP,
+ vpParams,
+ NULL);
+ if(FVID2_SOK != retVal)
+ {
+ App_print("VP Stop Failed!!!\r\n");
+ }
+
+ if(FVID2_SOK == retVal)
+ {
+ App_print("Display delete complete!!\r\n");
+ }
+
+ return;
+}
+
+static int32_t DispApp_allocAndQueueFrames(const DispApp_Obj *appObj,
+ DispApp_InstObj *instObj)
+{
+ int32_t retVal = FVID2_SOK;
+ uint32_t frmId, numFrames;
+ Fvid2_Frame *frm;
+ Fvid2_FrameList frmList;
+
+#if(1U == DISP_APP_LOAD_BUFFERS_RUNTIME)
+ uint32_t height=1080U, width=1920U;
+ char uartInput = '0';
+ App_print("Load Image using loadRaw command and then press '1'\n");
+ App_print("Command is:\n");
+ App_print("loadRaw(0x82000000, 0, \"C:\\\\display_bgr888_prog_packed_1920_1080.tigf\", 32, false);\n");
+ do
+ {
+ scanf("%c", &uartInput);
+ } while ('1' != uartInput);
+#endif
+
+ Fvid2FrameList_init(&frmList);
+ frm = &instObj->frames[0U];
+ numFrames = DISP_APP_MAX_FRAMES_PER_HANDLE;
+ /* init memory pointer for 'numFrames' */
+ for(frmId=0U; frmId<numFrames; frmId++)
+ {
+ /* init Fvid2_Frame to 0's */
+ Fvid2Frame_init(&frm[frmId]);
+#if(1U == DISP_APP_LOAD_BUFFERS_RUNTIME)
+ #if(DISP_APP_YUV420 == DISP_APP_USE_TEST_PARAMS)
+ frm[frmId].addr[0U] =
+ (uint64_t)(DISP_APP_DDR_LOAD_ADDRESS +
+ frmId*height*width*3U/2U);
+ frm[frmId].addr[1U] =
+ (uint64_t)(DISP_APP_DDR_LOAD_ADDRESS +
+ frmId*height*width*3U/2U +
+ height*width);
+ #elif(DISP_APP_YUV420_12 == DISP_APP_USE_TEST_PARAMS)
+ frm[frmId].addr[0U] =
+ (uint64_t)(DISP_APP_DDR_LOAD_ADDRESS);
+ frm[frmId].addr[1U] =
+ (uint64_t)(DISP_APP_DDR_LOAD_ADDRESS +
+ height*width*2U);
+ #if(1U == DISP_APP_RAW_DATA_INPUT)
+ /* For raw image , treat vid buffer as Luma and initialize chroma */
+ uint32_t temp_addr = frm[frmId].addr[1U];
+ int32_t j;
+ for(j=0;j<518400;j++)
+ {
+ CSL_REG32_WR(temp_addr + 4*j, 0x08000800U);
+ }
+ #endif
+ #else
+ frm[frmId].addr[0U] =
+ (uint64_t)(DISP_APP_DDR_LOAD_ADDRESS +
+ frmId*height*width*gDispAppTestParams.bpp);
+
+ #endif
+#else
+ if(instObj->instId == gDispAppTestParams.instId[0U])
+ {
+ if(0U == frmId)
+ {
+ frm[frmId].addr[0U] = (uint64_t) gDispArray1;
+ }
+ else
+ {
+ frm[frmId].addr[0U] = (uint64_t)gDispArray2;
+ }
+ }
+ else
+ {
+ if(0U == frmId)
+ {
+ frm[frmId].addr[0U] = (uint64_t)gDispArray1;
+ }
+ else
+ {
+ frm[frmId].addr[0U] = (uint64_t)gDispArray2;
+ }
+ }
+#endif
+ frm[frmId].fid = FVID2_FID_FRAME;
+ frm[frmId].appData = instObj;
+
+ /* Set number of frame in frame list - one at a time */
+ frmList.numFrames = 1U;
+ frmList.frames[0U] = &frm[frmId];
+
+ /*
+ * queue the frames in frmList
+ * All allocate frames are queued here as an example.
+ * In general atleast 2 frames per channel need to queued
+ * before starting display,
+ * else frame will get dropped until frames are queued
+ */
+ retVal = Fvid2_queue(instObj->drvHandle, &frmList, 0U);
+ if(FVID2_SOK != retVal)
+ {
+ App_print("Display Queue Failed!!!\r\n");
+ break;
+ }
+ }
+
+ return (retVal);
+}
+
+static void DispApp_initParams(DispApp_Obj *appObj)
+{
+ uint32_t instCnt = 0U, numPipes = 0U, i;
+ Dss_DispParams *dispParams;
+ DispApp_InstObj *instObj;
+
+ numPipes = gDispAppTestParams.numTestPipes;
+
+ for(instCnt=0U; instCnt<numPipes; instCnt++)
+ {
+ /* Initialize video pipes */
+ instObj = &appObj->instObj[instCnt];
+ instObj->instId = gDispAppTestParams.instId[instCnt];
+ Dss_dispCreateParamsInit(&instObj->createParams);
+ Fvid2CbParams_init(&instObj->cbParams);
+ instObj->cbParams.cbFxn = &DispApp_pipeCbFxn;
+ instObj->cbParams.appData = instObj;
+
+ dispParams = &instObj->dispParams;
+ Dss_dispParamsInit(dispParams);
+ dispParams->pipeCfg.pipeType = gDispAppTestParams.pipeType[instCnt];
+ dispParams->pipeCfg.inFmt.width = gDispAppTestParams.inWidth[instCnt];
+ dispParams->pipeCfg.inFmt.height = gDispAppTestParams.inHeight[instCnt];
+ for(i=0U; i<FVID2_MAX_PLANES; i++)
+ {
+ dispParams->pipeCfg.inFmt.pitch[i] =
+ gDispAppTestParams.pitch[instCnt][i];
+ }
+ dispParams->pipeCfg.inFmt.dataFormat =
+ gDispAppTestParams.inDataFmt[instCnt];
+ dispParams->pipeCfg.inFmt.scanFormat =
+ gDispAppTestParams.inScanFmt[instCnt];
+ dispParams->pipeCfg.outWidth = gDispAppTestParams.outWidth[instCnt];
+ dispParams->pipeCfg.outHeight = gDispAppTestParams.outHeight[instCnt];
+ dispParams->pipeCfg.scEnable = gDispAppTestParams.scEnable[instCnt];
+#if(DISP_APP_YUV420_12 == DISP_APP_USE_TEST_PARAMS)
+ dispParams->pipeCfg.inFmt.ccsFormat = FVID2_CCSF_BITS12_UNPACKED16;
+ dispParams->pipeCfg.yuvAlign = CSL_DSS_VID_PIPE_YUV_ALIGN_LSB;
+#endif
+#if(1U==DISP_APP_ENABLE_FLIP)
+ dispParams->pipeCfg.flipType = FVID2_FLIP_TYPE_V;
+#endif
+ dispParams->alphaCfg.globalAlpha =
+ gDispAppTestParams.globalAlpha[instCnt];
+ dispParams->alphaCfg.preMultiplyAlpha =
+ gDispAppTestParams.preMultiplyAlpha[instCnt];
+ dispParams->layerPos.startX = gDispAppTestParams.posx[instCnt];
+ dispParams->layerPos.startY = gDispAppTestParams.posy[instCnt];
+#if(1U == DISP_APP_ENBALE_PIPE_CROP)
+ dispParams->cropParams.cropEnable = TRUE;
+ dispParams->cropParams.cropCfg.cropTop = 31;
+ dispParams->cropParams.cropCfg.cropBottom = 31;
+ dispParams->cropParams.cropCfg.cropLeft = 31;
+ dispParams->cropParams.cropCfg.cropRight = 31;
+#endif
+ Dss_dispPipeMflagParamsInit(&instObj->mflagParams);
+ }
+}
+
+static int32_t DispApp_configDctrl(DispApp_Obj *appObj)
+{
+ int32_t retVal = FVID2_SOK;
+ uint32_t i = 0U, j=0U;
+ Dss_DctrlVpParams *vpParams;
+#if(1U == DISP_APP_TEST_MULTISYNC)
+ Dss_DctrlVpParams *syncVpParams;
+#endif
+ Dss_DctrlOverlayParams *overlayParams;
+ Dss_DctrlOverlayLayerParams *layerParams;
+ Dss_DctrlPathInfo *pathInfo;
+ Dss_DctrlAdvVpParams *advVpParams;
+#if(1U == DISP_APP_TEST_MULTISYNC)
+ Dss_DctrlAdvVpParams *syncAdvVpParams;
+#endif
+ Dss_DctrlGlobalDssParams *globalDssParams;
+#if defined (SOC_AM65XX)
+ Dss_DctrlOldiParams *oldiParams;
+ oldiParams = &appObj->oldiParams;
+ Dss_dctrlOldiParamsInit(oldiParams);
+#endif
+ vpParams = &appObj->vpParams;
+#if(1U == DISP_APP_TEST_MULTISYNC)
+ syncVpParams = &appObj->syncVpParams;
+#endif
+ overlayParams = &appObj->overlayParams;
+ layerParams = &appObj->layerParams;
+ pathInfo = &appObj->dctrlPathInfo;
+ advVpParams = &appObj->advVpParams;
+#if(1U == DISP_APP_TEST_MULTISYNC)
+ syncAdvVpParams = &appObj->syncAdvVpParams;
+#endif
+ globalDssParams= &appObj->globalDssParams;
+
+ Dss_dctrlOverlayParamsInit(overlayParams);
+ Dss_dctrlOverlayLayerParamsInit(layerParams);
+ Dss_dctrlPathInfoInit(pathInfo);
+ Dss_dctrlGlobalDssParamsInit(globalDssParams);
+
+ pathInfo->edgeInfo[pathInfo->numEdges].startNode = gDispAppTestParams.pipeNodeId[0U];
+ pathInfo->edgeInfo[pathInfo->numEdges].endNode = TEST_DCTRL_OVERLAY_NODE_ID;
+ pathInfo->numEdges++;
+ pathInfo->edgeInfo[pathInfo->numEdges].startNode = TEST_DCTRL_OVERLAY_NODE_ID;
+ pathInfo->edgeInfo[pathInfo->numEdges].endNode = TEST_DCTRL_VP_NODE_ID;
+ pathInfo->numEdges++;
+ pathInfo->edgeInfo[pathInfo->numEdges].startNode = TEST_DCTRL_VP_NODE_ID;
+ pathInfo->edgeInfo[pathInfo->numEdges].endNode = TEST_DCTRL_OUT_NODE_ID;
+ pathInfo->numEdges++;
+ if(gDispAppTestParams.numTestPipes > 1U)
+ {
+ for(i=1U; i<gDispAppTestParams.numTestPipes; i++)
+ {
+ pathInfo->edgeInfo[pathInfo->numEdges].startNode =
+ gDispAppTestParams.pipeNodeId[i];
+ pathInfo->edgeInfo[pathInfo->numEdges].endNode =
+ TEST_DCTRL_OVERLAY_NODE_ID;
+ pathInfo->numEdges++;
+ }
+ }
+#if(1U == DISP_APP_TEST_MULTISYNC)
+ pathInfo->edgeInfo[pathInfo->numEdges].startNode = TEST_DCTRL_SYNC_VP_NODE_ID;
+ pathInfo->edgeInfo[pathInfo->numEdges].endNode = TEST_DCTRL_SYNC_OUT_NODE_ID;
+ pathInfo->numEdges++;
+#endif
+
+ retVal = Fvid2_control(
+ appObj->dctrlHandle,
+ IOCTL_DSS_DCTRL_SET_PATH,
+ pathInfo,
+ NULL);
+ if(retVal != FVID2_SOK)
+ {
+ App_print("Dctrl Set Path IOCTL Failed!!!\r\n");
+ }
+
+#if(1U == DISP_APP_TEST_MULTISYNC)
+ retVal = Fvid2_control(
+ appObj->dctrlHandle,
+ IOCTL_DSS_DCTRL_SET_VP_PARAMS,
+ syncVpParams,
+ NULL);
+ if(retVal != FVID2_SOK)
+ {
+ App_print("Dctrl Set VP Params IOCTL Failed!!!\r\n");
+ }
+
+ retVal = Fvid2_control(
+ appObj->dctrlHandle,
+ IOCTL_DSS_DCTRL_SET_ADV_VP_PARAMS,
+ syncAdvVpParams,
+ NULL);
+ if(retVal != FVID2_SOK)
+ {
+ App_print("DCTRL Set Advance VP Params IOCTL Failed!!!\r\n");
+ }
+#endif
+
+ retVal = Fvid2_control(
+ appObj->dctrlHandle,
+ IOCTL_DSS_DCTRL_SET_VP_PARAMS,
+ vpParams,
+ NULL);
+ if(retVal != FVID2_SOK)
+ {
+ App_print("Dctrl Set VP Params IOCTL Failed!!!\r\n");
+ }
+
+ retVal = Fvid2_control(
+ appObj->dctrlHandle,
+ IOCTL_DSS_DCTRL_SET_ADV_VP_PARAMS,
+ advVpParams,
+ NULL);
+ if(retVal != FVID2_SOK)
+ {
+ App_print("DCTRL Set Advance VP Params IOCTL Failed!!!\r\n");
+ }
+
+
+#if defined (SOC_AM65XX)
+ retVal = Fvid2_control(
+ appObj->dctrlHandle,
+ IOCTL_DSS_DCTRL_SET_OLDI_PARAMS,
+ oldiParams,
+ NULL);
+ if(retVal != FVID2_SOK)
+ {
+ App_print("DCTRL Set OLDI Params IOCTL Failed!!!\r\n");
+ }
+#endif
+
+ overlayParams->overlayId = TEST_OVERLAY_ID;
+ overlayParams->colorbarEnable = FALSE;
+ overlayParams->overlayCfg.colorKeyEnable = TRUE;
+ overlayParams->overlayCfg.colorKeySel = CSL_DSS_OVERLAY_TRANS_COLOR_DEST;
+#if(DISP_APP_YUV420 == DISP_APP_USE_TEST_PARAMS)
+ overlayParams->overlayCfg.colorKeySel = CSL_DSS_OVERLAY_TRANS_COLOR_SRC;
+#endif
+ overlayParams->overlayCfg.backGroundColor = 0xc8c800U;
+ retVal = Fvid2_control(
+ appObj->dctrlHandle,
+ IOCTL_DSS_DCTRL_SET_OVERLAY_PARAMS,
+ overlayParams,
+ NULL);
+ if(retVal != FVID2_SOK)
+ {
+ App_print("DCTRL Set Overlay Params IOCTL Failed!!!\r\n");
+ }
+
+ layerParams->overlayId = TEST_OVERLAY_ID;
+ layerParams->pipeLayerNum[gDispAppTestParams.pipeId[0U]] =
+ CSL_DSS_OVERLAY_LAYER_NUM_0;
+ if(gDispAppTestParams.numTestPipes > 1U)
+ {
+ for(i=1U; i<gDispAppTestParams.numTestPipes;i++)
+ {
+ layerParams->pipeLayerNum[gDispAppTestParams.pipeId[i]] = i;
+ }
+ }
+
+ if(gDispAppTestParams.numTestPipes < CSL_DSS_VID_PIPE_ID_MAX)
+ {
+ for(i=gDispAppTestParams.numTestPipes; i<CSL_DSS_VID_PIPE_ID_MAX; i++)
+ {
+ layerParams->pipeLayerNum[gDispAppTestParams.invalidPipeId[j++]] =
+ CSL_DSS_OVERLAY_LAYER_INVALID;
+ }
+ }
+
+ retVal = Fvid2_control(
+ appObj->dctrlHandle,
+ IOCTL_DSS_DCTRL_SET_LAYER_PARAMS,
+ layerParams,
+ NULL);
+ if(retVal != FVID2_SOK)
+ {
+ App_print("DCTRL Set Layer Params IOCTL Failed!!!\r\n");
+ }
+
+ retVal = Fvid2_control(
+ appObj->dctrlHandle,
+ IOCTL_DSS_DCTRL_SET_GLOBAL_DSS_PARAMS,
+ globalDssParams,
+ NULL);
+ if(retVal != FVID2_SOK)
+ {
+ App_print("DCTRL Set Global DSS Params IOCTL Failed!!!\r\n");
+ }
+
+ return (retVal);
+}
+
+static int32_t DispApp_pipeCbFxn(Fvid2_Handle handle, void *appData)
+{
+ int32_t retVal = FVID2_SOK;
+ DispApp_InstObj *instObj = (DispApp_InstObj *) appData;
+ GT_assert (DssTrace, (NULL != instObj));
+ (void) SemaphoreP_post(instObj->syncSem);
+
+ return (retVal);
+}
+
+void App_print(const char *format, ...)
+{
+ va_list vaArgPtr;
+ va_start(vaArgPtr, format);
+
+ DSS_log(format, vaArgPtr);
+ va_end(vaArgPtr);
+
+ return;
+}
diff --git a/packages/ti/drv/dss/examples/dss_display_test/dss_display_test.h b/packages/ti/drv/dss/examples/dss_display_test/dss_display_test.h
--- /dev/null
@@ -0,0 +1,1318 @@
+/*
+ * Copyright (c) Texas Instruments Incorporated 2018
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * \file dss_display_test.h
+ *
+ * \brief DSS display Test Header file.
+ */
+
+#ifndef DSS_DISPLAY_TEST_H_
+#define DSS_DISPLAY_TEST_H_
+
+/* ========================================================================== */
+/* Include Files */
+/* ========================================================================== */
+
+#include <ti/drv/dss/dss.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* ========================================================================== */
+/* Macros & Typedefs */
+/* ========================================================================== */
+#if defined (SIMULATOR)
+#define DISP_APP_RUN_COUNT (0x10U)
+#else
+#define DISP_APP_RUN_COUNT (0x1000U)
+#endif
+
+#if defined (SOC_AM65XX)
+#define DISP_APP_LCD_WIDTH (1280U)
+#define DISP_APP_LCD_HEIGHT (800U)
+#else
+#define DISP_APP_LCD_WIDTH (1920U)
+#define DISP_APP_LCD_HEIGHT (1080U)
+#endif
+/* Worst case frames per handle */
+#define DISP_APP_MAX_FRAMES_PER_HANDLE (2U)
+
+/* Test Params */
+#define DISP_APP_BGRA32_1 (1U)
+#define DISP_APP_BGRA32_2 (2U)
+#define DISP_APP_ARGB32 (3U)
+#define DISP_APP_RGB24 (4U)
+#define DISP_APP_BGR24 (5U)
+#define DISP_APP_YUV2 (6U)
+#define DISP_APP_UVVY (7U)
+#define DISP_APP_YUV420 (8U)
+#define DISP_APP_YUV420_12 (9U)
+#define DISP_APP_RGB565 (10U)
+#define DISP_APP_BGR565 (11U)
+#define DISP_APP_BGRA32 (12U)
+
+/* Test Params to be used. Possible values:
+ * 1U: Test VID1 and VIDL1
+ * 2U: Test VID2 and VIDL2 (only for J7)
+ * 3U: Test VID1 ARGB32
+ * 4U: Test VID1 RGB24
+ * 5U: Test VID1 BGR24
+ * 6U: Test VID1 YUV422I-YUYV (only for J7)
+ * 7U: Test VID1 YUV422I-UYVY (only for J7)
+ * 8U: Test VID1 YUV420 (only for J7)
+ * 9U: Test VID1 YUV420 12 bit (Only for J7)
+ * 10U: Test VID1 RGB565 (Only for J7)
+ * 11U: Test VID1 BGR565 (Only for J7)
+ * 12U: Test VID1 BGRA32 (Only for J7, eDP)
+ */
+#define DISP_APP_USE_TEST_PARAMS (DISP_APP_BGRA32_1)
+
+/* Load buffers runtime for RGB24 and YUV formats */
+#define DISP_APP_LOAD_BUFFERS_RUNTIME (0U)
+
+#define DISP_APP_DDR_LOAD_ADDRESS (0x82000000U)
+
+#define DISP_APP_ENBALE_PIPE_CROP (0U)
+
+#define DISP_APP_ENABLE_COMMON1_REGION (0U)
+
+#define DISP_APP_TEST_OVERLAY_VP_4 (0U)
+
+#define DISP_APP_ENABLE_FLIP (0U)
+
+#define DISP_APP_RAW_DATA_INPUT (0U)
+
+#define DISP_APP_TEST_EDP (0U)
+
+#define DISP_APP_TEST_MULTISYNC (0U)
+
+/* Enable the below macro to have prints on the IO Console */
+#undef CIO_CONSOLE
+
+#ifndef CIO_CONSOLE
+#define DSS_log UART_printf
+#else
+#define DSS_log printf
+#endif
+
+/* ========================================================================== */
+/* Structure Declarations */
+/* ========================================================================== */
+
+/**
+ * \brief Display application test parameters.
+ * The test case execution happens based on values of this structure
+ */
+typedef struct
+{
+ uint32_t numTestPipes;
+ /**< Number of pipes in test params */
+ uint32_t bpp;
+ /**< Number of bytes per pixel */
+ uint32_t instId[CSL_DSS_VID_PIPE_ID_MAX];
+ /**< Driver instance id */
+ uint32_t pipeId[CSL_DSS_VID_PIPE_ID_MAX];
+ /**< Pipe id */
+ uint32_t pipeNodeId[CSL_DSS_VID_PIPE_ID_MAX];
+ /**< Pipe Node id */
+ uint32_t pipeType[CSL_DSS_VID_PIPE_ID_MAX];
+ /**< Video pipe type */
+ uint32_t inDataFmt[CSL_DSS_VID_PIPE_ID_MAX];
+ /**< Data format */
+ uint32_t inWidth[CSL_DSS_VID_PIPE_ID_MAX];
+ /**< Input buffer resolution width in pixels */
+ uint32_t inHeight[CSL_DSS_VID_PIPE_ID_MAX];
+ /**< Input buffer resolution height in lines */
+ uint32_t pitch[CSL_DSS_VID_PIPE_ID_MAX][FVID2_MAX_PLANES];
+ /**< Pitch of input buffer */
+ uint32_t inScanFmt[CSL_DSS_VID_PIPE_ID_MAX];
+ /**< Scan format */
+ uint32_t outWidth[CSL_DSS_VID_PIPE_ID_MAX];
+ /**< Output buffer resolution width in pixels */
+ uint32_t outHeight[CSL_DSS_VID_PIPE_ID_MAX];
+ /**< Output buffer resolution height in lines */
+ uint32_t scEnable[CSL_DSS_VID_PIPE_ID_MAX];
+ /**< Scaler enable */
+ uint32_t globalAlpha[CSL_DSS_VID_PIPE_ID_MAX];
+ /**< Global Alpha value */
+ uint32_t preMultiplyAlpha[CSL_DSS_VID_PIPE_ID_MAX];
+ /**< Pre-multiply Alpha value */
+ uint32_t posx[CSL_DSS_VID_PIPE_ID_MAX];
+ /**< Input buffer position x. */
+ uint32_t posy[CSL_DSS_VID_PIPE_ID_MAX];
+ /**< Input buffer position y. */
+ uint32_t invalidPipeId[CSL_DSS_VID_PIPE_ID_MAX];
+ /**< Pipe id */
+} DispApp_TestParams;
+
+/**
+ * \brief Driver instance information.
+ */
+typedef struct
+{
+ uint32_t instId;
+ /**< Instance ID */
+ Dss_DispCreateParams createParams;
+ /**< Create time parameters */
+ Dss_DispCreateStatus createStatus;
+ /**< Create status returned by driver during Fvid2_create() */
+ Dss_DispParams dispParams;
+ /**< DSS display parameters */
+ Dss_DispPipeMflagParams mflagParams;
+ /**< DSS mflag parameters */
+ Fvid2_Handle drvHandle;
+ /**< FVID2 display driver handle */
+ Fvid2_CbParams cbParams;
+ /**< Callback parameters */
+ Fvid2_Frame frames[DISP_APP_MAX_FRAMES_PER_HANDLE];
+ /**< FVID2 Frames that will be used for display */
+ SemaphoreP_Handle syncSem;
+ /**< Semaphore for ISR */
+} DispApp_InstObj;
+
+/**
+ * \brief Test application data structure.
+ */
+typedef struct
+{
+ DispApp_InstObj instObj[CSL_DSS_VID_PIPE_ID_MAX];
+ /**< Display driver instance objects */
+ Fvid2_Handle dctrlHandle;
+ /**< DCTRL handle */
+ Dss_InitParams initParams;
+ /**< DSS Initialization Parameters */
+ Dss_DctrlPathInfo dctrlPathInfo;
+ /**< DSS Path Information */
+ Dss_DctrlVpParams vpParams;
+ /**< VP Params */
+ Dss_DctrlVpParams syncVpParams;
+ /**< VP Params for synchronised VP */
+ Dss_DctrlOverlayParams overlayParams;
+ /**< Overlay Params */
+ Dss_DctrlOverlayLayerParams layerParams;
+ /**< Layer Params */
+ Dss_DctrlVpErrorStats errorStats;
+ /**< Error Stats */
+ Dss_DctrlAdvVpParams advVpParams;
+ /**< Advance VP Params */
+ Dss_DctrlAdvVpParams syncAdvVpParams;
+ /**< Advance VP Params for Synchronised VP */
+ Dss_DctrlGlobalDssParams globalDssParams;
+ /**< Global DSS Params */
+#if defined (SOC_AM65XX)
+ Dss_DctrlOldiParams oldiParams;
+ /**< OLDI Params */
+#endif
+} DispApp_Obj;
+
+/* ========================================================================== */
+/* Internal/Private Function Declarations */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/* Function Declarations */
+/* ========================================================================== */
+
+void App_print(const char *format, ...);
+
+/* ========================================================================== */
+/* Global Variables */
+/* ========================================================================== */
+
+#if (DISP_APP_BGRA32 == DISP_APP_USE_TEST_PARAMS)
+static const DispApp_TestParams gDispAppTestParams=
+{
+ /* Number of Pipes */
+ 1U,
+ /* bpp */
+ 4U,
+ /* Instance Id */
+ {
+ DSS_DISP_INST_VID1
+ },
+ /* Pipe Id */
+ {
+ CSL_DSS_VID_PIPE_ID_VID1
+ },
+ /* Pipe Node Id */
+ {
+ DSS_DCTRL_NODE_VID1
+ },
+ /* Pipe Type */
+ {
+ CSL_DSS_VID_PIPE_TYPE_VID
+ },
+ /* Data format */
+ {
+ FVID2_DF_BGRA32_8888
+ },
+ /* Input buffer width */
+ {
+ 1920U
+ },
+ /* Input buffer height */
+ {
+ 1080U
+ },
+ /* Pitch */
+ {
+ {
+ 1920U*4U, 0U, 0U, 0U, 0U, 0U
+ }
+ },
+ /* Scan format */
+ {
+ FVID2_SF_PROGRESSIVE
+ },
+ /* Output buffer width */
+ {
+ DISP_APP_LCD_WIDTH
+ },
+ /* Output buffer height */
+ {
+ DISP_APP_LCD_HEIGHT
+ },
+ /* Scaler enable */
+ {
+ TRUE
+ },
+ /* Global Alpha */
+ {
+ 0xFFU
+ },
+ /* Pre-multiply alpha */
+ {
+ FALSE
+ },
+ /* X Position */
+ {
+ 0U
+ },
+ /* Y position */
+ {
+ 0U
+ },
+ /* Invalid Pipe Id */
+ {
+ CSL_DSS_VID_PIPE_ID_VIDL1,
+#if defined (SOC_J721E)
+ CSL_DSS_VID_PIPE_ID_VID2,
+ CSL_DSS_VID_PIPE_ID_VIDL2
+#endif
+ }
+};
+#elif (DISP_APP_BGR565 == DISP_APP_USE_TEST_PARAMS)
+static const DispApp_TestParams gDispAppTestParams=
+{
+ /* Number of Pipes */
+ 1U,
+ /* bpp */
+ 2U,
+ /* Instance Id */
+ {
+ DSS_DISP_INST_VID1
+ },
+ /* Pipe Id */
+ {
+ CSL_DSS_VID_PIPE_ID_VID1
+ },
+ /* Pipe Node Id */
+ {
+ DSS_DCTRL_NODE_VID1
+ },
+ /* Pipe Type */
+ {
+ CSL_DSS_VID_PIPE_TYPE_VID
+ },
+ /* Data format */
+ {
+ FVID2_DF_BGR16_565
+ },
+ /* Input buffer width */
+ {
+ 1920U
+ },
+ /* Input buffer height */
+ {
+ 1080U
+ },
+ /* Pitch */
+ {
+ {
+ 1920U*2U, 0U, 0U, 0U, 0U, 0U
+ }
+ },
+ /* Scan format */
+ {
+ FVID2_SF_PROGRESSIVE
+ },
+ /* Output buffer width */
+ {
+ DISP_APP_LCD_WIDTH
+ },
+ /* Output buffer height */
+ {
+ DISP_APP_LCD_HEIGHT
+ },
+ /* Scaler enable */
+ {
+ TRUE
+ },
+ /* Global Alpha */
+ {
+ 0xFFU
+ },
+ /* Pre-multiply alpha */
+ {
+ FALSE
+ },
+ /* X Position */
+ {
+ 0U
+ },
+ /* Y position */
+ {
+ 0U
+ },
+ /* Invalid Pipe Id */
+ {
+ CSL_DSS_VID_PIPE_ID_VIDL1,
+#if defined (SOC_J721E)
+ CSL_DSS_VID_PIPE_ID_VID2,
+ CSL_DSS_VID_PIPE_ID_VIDL2
+#endif
+ }
+};
+#elif (DISP_APP_RGB565 == DISP_APP_USE_TEST_PARAMS)
+static const DispApp_TestParams gDispAppTestParams=
+{
+ /* Number of Pipes */
+ 1U,
+ /* bpp */
+ 2U,
+ /* Instance Id */
+ {
+ DSS_DISP_INST_VID1
+ },
+ /* Pipe Id */
+ {
+ CSL_DSS_VID_PIPE_ID_VID1
+ },
+ /* Pipe Node Id */
+ {
+ DSS_DCTRL_NODE_VID1
+ },
+ /* Pipe Type */
+ {
+ CSL_DSS_VID_PIPE_TYPE_VID
+ },
+ /* Data format */
+ {
+ FVID2_DF_RGB16_565
+ },
+ /* Input buffer width */
+ {
+ 1920U
+ },
+ /* Input buffer height */
+ {
+ 1080U
+ },
+ /* Pitch */
+ {
+ {
+ 1920U*2U, 0U, 0U, 0U, 0U, 0U
+ }
+ },
+ /* Scan format */
+ {
+ FVID2_SF_PROGRESSIVE
+ },
+ /* Output buffer width */
+ {
+ DISP_APP_LCD_WIDTH
+ },
+ /* Output buffer height */
+ {
+ DISP_APP_LCD_HEIGHT
+ },
+ /* Scaler enable */
+ {
+ TRUE
+ },
+ /* Global Alpha */
+ {
+ 0xFFU
+ },
+ /* Pre-multiply alpha */
+ {
+ FALSE
+ },
+ /* X Position */
+ {
+ 0U
+ },
+ /* Y position */
+ {
+ 0U
+ },
+ /* Invalid Pipe Id */
+ {
+ CSL_DSS_VID_PIPE_ID_VIDL1,
+#if defined (SOC_J721E)
+ CSL_DSS_VID_PIPE_ID_VID2,
+ CSL_DSS_VID_PIPE_ID_VIDL2
+#endif
+ }
+};
+#elif (DISP_APP_YUV420_12 == DISP_APP_USE_TEST_PARAMS)
+static const DispApp_TestParams gDispAppTestParams=
+{
+ /* Number of Pipes */
+ 1U,
+ /* bpp, not used in this case */
+ 3U,
+ /* Instance Id */
+ {
+ DSS_DISP_INST_VID1
+ },
+ /* Pipe Id */
+ {
+ CSL_DSS_VID_PIPE_ID_VID1
+ },
+ /* Pipe Node Id */
+ {
+ DSS_DCTRL_NODE_VID1
+ },
+ /* Pipe Type */
+ {
+ CSL_DSS_VID_PIPE_TYPE_VID
+ },
+ /* Data format */
+ {
+ FVID2_DF_YUV420SP_UV
+ },
+ /* Input buffer width */
+ {
+ 1920U
+ },
+ /* Input buffer height */
+ {
+ 1080U
+ },
+ /* Pitch */
+ {
+ {
+ 1920U*2U, 1920U*2U, 0U, 0U, 0U, 0U
+ }
+ },
+ /* Scan format */
+ {
+ FVID2_SF_PROGRESSIVE
+ },
+ /* Output buffer width */
+ {
+ DISP_APP_LCD_WIDTH
+ },
+ /* Output buffer height */
+ {
+ DISP_APP_LCD_HEIGHT
+ },
+ /* Scaler enable */
+ {
+ TRUE
+ },
+ /* Global Alpha */
+ {
+ 0xFFU
+ },
+ /* Pre-multiply alpha */
+ {
+ FALSE
+ },
+ /* X Position */
+ {
+ 0U
+ },
+ /* Y position */
+ {
+ 0U
+ },
+ /* Invalid Pipe Id */
+ {
+ CSL_DSS_VID_PIPE_ID_VIDL1,
+#if defined (SOC_J721E)
+ CSL_DSS_VID_PIPE_ID_VID2,
+ CSL_DSS_VID_PIPE_ID_VIDL2
+#endif
+ }
+};
+#elif (DISP_APP_YUV420 == DISP_APP_USE_TEST_PARAMS)
+static const DispApp_TestParams gDispAppTestParams=
+{
+ /* Number of Pipes */
+ 1U,
+ /* bpp, not used in this case */
+ 3U/2U,
+ /* Instance Id */
+ {
+ DSS_DISP_INST_VID1
+ },
+ /* Pipe Id */
+ {
+ CSL_DSS_VID_PIPE_ID_VID1
+ },
+ /* Pipe Node Id */
+ {
+ DSS_DCTRL_NODE_VID1
+ },
+ /* Pipe Type */
+ {
+ CSL_DSS_VID_PIPE_TYPE_VID
+ },
+ /* Data format */
+ {
+ FVID2_DF_YUV420SP_UV
+ },
+ /* Input buffer width */
+ {
+ 1920U
+ },
+ /* Input buffer height */
+ {
+ 1080U
+ },
+ /* Pitch */
+ {
+ {
+ 1920U, 1920U, 0U, 0U, 0U, 0U
+ }
+ },
+ /* Scan format */
+ {
+ FVID2_SF_PROGRESSIVE
+ },
+ /* Output buffer width */
+ {
+ DISP_APP_LCD_WIDTH
+ },
+ /* Output buffer height */
+ {
+ DISP_APP_LCD_HEIGHT
+ },
+ /* Scaler enable */
+ {
+ TRUE
+ },
+ /* Global Alpha */
+ {
+ 0xFFU
+ },
+ /* Pre-multiply alpha */
+ {
+ FALSE
+ },
+ /* X Position */
+ {
+ 0U
+ },
+ /* Y position */
+ {
+ 0U
+ },
+ /* Invalid Pipe Id */
+ {
+ CSL_DSS_VID_PIPE_ID_VIDL1,
+#if defined (SOC_J721E)
+ CSL_DSS_VID_PIPE_ID_VID2,
+ CSL_DSS_VID_PIPE_ID_VIDL2
+#endif
+ }
+};
+#elif (DISP_APP_UVVY == DISP_APP_USE_TEST_PARAMS)
+static const DispApp_TestParams gDispAppTestParams=
+{
+ /* Number of Pipes */
+ 1U,
+ /* bpp */
+ 2U,
+ /* Instance Id */
+ {
+ DSS_DISP_INST_VID1
+ },
+ /* Pipe Id */
+ {
+ CSL_DSS_VID_PIPE_ID_VID1
+ },
+ /* Pipe Node Id */
+ {
+ DSS_DCTRL_NODE_VID1
+ },
+ /* Pipe Type */
+ {
+ CSL_DSS_VID_PIPE_TYPE_VID
+ },
+ /* Data format */
+ {
+ FVID2_DF_YUV422I_UYVY
+ },
+ /* Input buffer width */
+ {
+ 1920U
+ },
+ /* Input buffer height */
+ {
+ 1080U
+ },
+ /* Pitch */
+ {
+ {
+ 1920U*2U, 0U, 0U, 0U, 0U, 0U
+ }
+ },
+ /* Scan format */
+ {
+ FVID2_SF_PROGRESSIVE
+ },
+ /* Output buffer width */
+ {
+ DISP_APP_LCD_WIDTH
+ },
+ /* Output buffer height */
+ {
+ DISP_APP_LCD_HEIGHT
+ },
+ /* Scaler enable */
+ {
+ TRUE
+ },
+ /* Global Alpha */
+ {
+ 0xFFU
+ },
+ /* Pre-multiply alpha */
+ {
+ FALSE
+ },
+ /* X Position */
+ {
+ 0U
+ },
+ /* Y position */
+ {
+ 0U
+ },
+ /* Invalid Pipe Id */
+ {
+ CSL_DSS_VID_PIPE_ID_VIDL1,
+#if defined (SOC_J721E)
+ CSL_DSS_VID_PIPE_ID_VID2,
+ CSL_DSS_VID_PIPE_ID_VIDL2
+#endif
+ }
+};
+#elif (DISP_APP_YUV2 == DISP_APP_USE_TEST_PARAMS)
+static const DispApp_TestParams gDispAppTestParams=
+{
+ /* Number of Pipes */
+ 1U,
+ /* bpp */
+ 2U,
+ /* Instance Id */
+ {
+ DSS_DISP_INST_VID1
+ },
+ /* Pipe Id */
+ {
+ CSL_DSS_VID_PIPE_ID_VID1
+ },
+ /* Pipe Node Id */
+ {
+ DSS_DCTRL_NODE_VID1
+ },
+ /* Pipe Type */
+ {
+ CSL_DSS_VID_PIPE_TYPE_VID
+ },
+ /* Data format */
+ {
+ FVID2_DF_YUV422I_YUYV
+ },
+ /* Input buffer width */
+ {
+ 1920U
+ },
+ /* Input buffer height */
+ {
+ 1080U
+ },
+ /* Pitch */
+ {
+ {
+ 1920U*2U, 0U, 0U, 0U, 0U, 0U
+ }
+ },
+ /* Scan format */
+ {
+ FVID2_SF_PROGRESSIVE
+ },
+ /* Output buffer width */
+ {
+ DISP_APP_LCD_WIDTH
+ },
+ /* Output buffer height */
+ {
+ DISP_APP_LCD_HEIGHT
+ },
+ /* Scaler enable */
+ {
+ TRUE
+ },
+ /* Global Alpha */
+ {
+ 0xFFU
+ },
+ /* Pre-multiply alpha */
+ {
+ FALSE
+ },
+ /* X Position */
+ {
+ 0U
+ },
+ /* Y position */
+ {
+ 0U
+ },
+ /* Invalid Pipe Id */
+ {
+ CSL_DSS_VID_PIPE_ID_VIDL1,
+#if defined (SOC_J721E)
+ CSL_DSS_VID_PIPE_ID_VID2,
+ CSL_DSS_VID_PIPE_ID_VIDL2
+#endif
+ }
+};
+#elif (DISP_APP_BGR24 == DISP_APP_USE_TEST_PARAMS)
+static const DispApp_TestParams gDispAppTestParams=
+{
+ /* Number of Pipes */
+ 1U,
+ /* bpp */
+ 3U,
+ /* Instance Id */
+ {
+ DSS_DISP_INST_VID1
+ },
+ /* Pipe Id */
+ {
+ CSL_DSS_VID_PIPE_ID_VID1
+ },
+ /* Pipe Node Id */
+ {
+ DSS_DCTRL_NODE_VID1
+ },
+ /* Pipe Type */
+ {
+ CSL_DSS_VID_PIPE_TYPE_VID
+ },
+ /* Data format */
+ {
+ FVID2_DF_BGR24_888
+ },
+ /* Input buffer width */
+ {
+ 1920U
+ },
+ /* Input buffer height */
+ {
+ 1080U
+ },
+ /* Pitch */
+ {
+ {
+ 1920U*3U, 0U, 0U, 0U, 0U, 0U
+ }
+ },
+ /* Scan format */
+ {
+ FVID2_SF_PROGRESSIVE
+ },
+ /* Output buffer width */
+ {
+ DISP_APP_LCD_WIDTH
+ },
+ /* Output buffer height */
+ {
+ DISP_APP_LCD_HEIGHT
+ },
+ /* Scaler enable */
+ {
+ TRUE
+ },
+ /* Global Alpha */
+ {
+ 0xFFU
+ },
+ /* Pre-multiply alpha */
+ {
+ FALSE
+ },
+ /* X Position */
+ {
+ 0U
+ },
+ /* Y position */
+ {
+ 0U
+ },
+ /* Invalid Pipe Id */
+ {
+ CSL_DSS_VID_PIPE_ID_VIDL1,
+#if defined (SOC_J721E)
+ CSL_DSS_VID_PIPE_ID_VID2,
+ CSL_DSS_VID_PIPE_ID_VIDL2
+#endif
+ }
+};
+#elif (DISP_APP_RGB24 == DISP_APP_USE_TEST_PARAMS)
+static const DispApp_TestParams gDispAppTestParams=
+{
+ /* Number of Pipes */
+ 1U,
+ /* bpp */
+ 3U,
+ /* Instance Id */
+ {
+ DSS_DISP_INST_VID1
+ },
+ /* Pipe Id */
+ {
+ CSL_DSS_VID_PIPE_ID_VID1
+ },
+ /* Pipe Node Id */
+ {
+ DSS_DCTRL_NODE_VID1
+ },
+ /* Pipe Type */
+ {
+ CSL_DSS_VID_PIPE_TYPE_VID
+ },
+ /* Data format */
+ {
+ FVID2_DF_RGB24_888
+ },
+ /* Input buffer width */
+ {
+ 1920U
+ },
+ /* Input buffer height */
+ {
+ 1080U
+ },
+ /* Pitch */
+ {
+ {
+ 1920U*3U, 0U, 0U, 0U, 0U, 0U
+ }
+ },
+ /* Scan format */
+ {
+ FVID2_SF_PROGRESSIVE
+ },
+ /* Output buffer width */
+ {
+ DISP_APP_LCD_WIDTH
+ },
+ /* Output buffer height */
+ {
+ DISP_APP_LCD_HEIGHT
+ },
+ /* Scaler enable */
+ {
+ TRUE
+ },
+ /* Global Alpha */
+ {
+ 0xFFU
+ },
+ /* Pre-multiply alpha */
+ {
+ FALSE
+ },
+ /* X Position */
+ {
+ 0U
+ },
+ /* Y position */
+ {
+ 0U
+ },
+ /* Invalid Pipe Id */
+ {
+ CSL_DSS_VID_PIPE_ID_VIDL1,
+#if defined (SOC_J721E)
+ CSL_DSS_VID_PIPE_ID_VID2,
+ CSL_DSS_VID_PIPE_ID_VIDL2
+#endif
+ }
+};
+#elif (DISP_APP_ARGB32 == DISP_APP_USE_TEST_PARAMS)
+static const DispApp_TestParams gDispAppTestParams=
+{
+ /* Number of Pipes */
+ 1U,
+ /* bpp */
+ 4U,
+ /* Instance Id */
+ {
+ DSS_DISP_INST_VID1
+ },
+ /* Pipe Id */
+ {
+ CSL_DSS_VID_PIPE_ID_VID1
+ },
+ /* Pipe Node Id */
+ {
+ DSS_DCTRL_NODE_VID1
+ },
+ /* Pipe Type */
+ {
+ CSL_DSS_VID_PIPE_TYPE_VID
+ },
+ /* Data format */
+ {
+ FVID2_DF_ARGB32_8888
+ },
+ /* Input buffer width */
+ {
+ 1920U
+ },
+ /* Input buffer height */
+ {
+ 1080U
+ },
+ /* Pitch */
+ {
+ {
+ 1920U*4U, 0U, 0U, 0U, 0U, 0U
+ }
+ },
+ /* Scan format */
+ {
+ FVID2_SF_PROGRESSIVE
+ },
+ /* Output buffer width */
+ {
+ DISP_APP_LCD_WIDTH
+ },
+ /* Output buffer height */
+ {
+ DISP_APP_LCD_HEIGHT
+ },
+ /* Scaler enable */
+ {
+ TRUE
+ },
+ /* Global Alpha */
+ {
+ 0xFFU
+ },
+ /* Pre-multiply alpha */
+ {
+ FALSE
+ },
+ /* X Position */
+ {
+ 0U
+ },
+ /* Y position */
+ {
+ 0U
+ },
+ /* Invalid Pipe Id */
+ {
+ CSL_DSS_VID_PIPE_ID_VIDL1,
+#if defined (SOC_J721E)
+ CSL_DSS_VID_PIPE_ID_VID2,
+ CSL_DSS_VID_PIPE_ID_VIDL2
+#endif
+ }
+};
+#elif (DISP_APP_BGRA32_2 == DISP_APP_USE_TEST_PARAMS)
+static const DispApp_TestParams gDispAppTestParams=
+{
+ /* Number of Pipes */
+ 2U,
+ /* bpp */
+ 4U,
+ /* Instance Id */
+ {
+ DSS_DISP_INST_VID2,
+ DSS_DISP_INST_VIDL2
+ },
+ /* Pipe Id */
+ {
+ CSL_DSS_VID_PIPE_ID_VID2,
+ CSL_DSS_VID_PIPE_ID_VIDL2
+ },
+ /* Pipe Node Id */
+ {
+ DSS_DCTRL_NODE_VID2,
+ DSS_DCTRL_NODE_VIDL2
+ },
+ /* Pipe Type */
+ {
+ CSL_DSS_VID_PIPE_TYPE_VID,
+ CSL_DSS_VID_PIPE_TYPE_VIDL
+ },
+ /* Data format */
+ {
+ FVID2_DF_BGRA32_8888,
+ FVID2_DF_BGRA32_8888
+ },
+ /* Input buffer width */
+ {
+ 480U,
+ 480U
+ },
+ /* Input buffer height */
+ {
+ 360U,
+ 360U
+ },
+ /* Pitch */
+ {
+ {
+ 480U*4U, 0U, 0U, 0U, 0U, 0U
+ },
+ {
+ 480U*4U, 0U, 0U, 0U, 0U, 0U
+ }
+ },
+ /* Scan format */
+ {
+ FVID2_SF_PROGRESSIVE,
+ FVID2_SF_PROGRESSIVE
+ },
+ /* Output buffer width */
+ {
+ 360U,
+ 480U
+ },
+ /* Output buffer height */
+ {
+ 240U,
+ 360U
+ },
+ /* Scaler enable */
+ {
+ TRUE,
+ FALSE
+ },
+ /* Global Alpha */
+ {
+ 0xFFU,
+ 0xFFU
+ },
+ /* Pre-multiply alpha */
+ {
+ FALSE,
+ FALSE
+ },
+#if defined (SOC_AM65XX)
+ /* X Position */
+ {
+ 0U,
+ 800U
+ },
+ /* Y position */
+ {
+ 0U,
+ 440U
+ },
+#else
+ /* X Position */
+ {
+ 0U,
+ 1440U
+ },
+ /* Y position */
+ {
+ 0U,
+ 720U
+ },
+#endif
+ /* Invalid Pipe Id */
+ {
+ CSL_DSS_VID_PIPE_ID_VID1,
+ CSL_DSS_VID_PIPE_ID_VIDL1
+ }
+};
+#else
+static const DispApp_TestParams gDispAppTestParams=
+{
+ /* Number of Pipes */
+ 2U,
+ /* bpp */
+ 4U,
+ /* Instance Id */
+ {
+ DSS_DISP_INST_VID1,
+ DSS_DISP_INST_VIDL1
+ },
+ /* Pipe Id */
+ {
+ CSL_DSS_VID_PIPE_ID_VID1,
+ CSL_DSS_VID_PIPE_ID_VIDL1
+ },
+ /* Pipe Node Id */
+ {
+ DSS_DCTRL_NODE_VID1,
+ DSS_DCTRL_NODE_VIDL1
+ },
+ /* Pipe Type */
+ {
+ CSL_DSS_VID_PIPE_TYPE_VID,
+ CSL_DSS_VID_PIPE_TYPE_VIDL
+ },
+ /* Data format */
+ {
+ FVID2_DF_BGRA32_8888,
+ FVID2_DF_BGRA32_8888
+ },
+ /* Input buffer width */
+ {
+ 480U,
+ 480U
+ },
+ /* Input buffer height */
+ {
+ 360U,
+ 360U
+ },
+ /* Pitch */
+ {
+ {
+ 480U*4U, 0U, 0U, 0U, 0U, 0U
+ },
+ {
+ 480U*4U, 0U, 0U, 0U, 0U, 0U
+ }
+ },
+ /* Scan format */
+ {
+ FVID2_SF_PROGRESSIVE,
+ FVID2_SF_PROGRESSIVE
+ },
+ /* Output buffer width */
+ {
+ 720U,
+ 480U
+ },
+ /* Output buffer height */
+ {
+ 540U,
+ 360U
+ },
+ /* Scaler enable */
+ {
+ TRUE,
+ FALSE
+ },
+ /* Global Alpha */
+ {
+ 0xFFU,
+ 0xFFU
+ },
+ /* Pre-multiply alpha */
+ {
+ FALSE,
+ FALSE
+ },
+#if defined (SOC_AM65XX)
+ /* X Position */
+ {
+ 0U,
+ 800U
+ },
+ /* Y position */
+ {
+ 0U,
+ 440U
+ },
+#else
+ /* X Position */
+ {
+ 0U,
+ 1440U
+ },
+ /* Y position */
+ {
+ 0U,
+ 720U
+ },
+#endif
+#if defined (SOC_J721E)
+ /* Invalid Pipe Id */
+ {
+ CSL_DSS_VID_PIPE_ID_VID2,
+ CSL_DSS_VID_PIPE_ID_VIDL2
+ }
+#endif
+};
+#endif
+
+/* ========================================================================== */
+/* Internal Function Declarations (Needed for other static inlines) */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/* Static Function Definitions */
+/* ========================================================================== */
+
+/* None */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #ifndef DSS_DISPLAY_TEST_H_ */
+
+/* @} */
diff --git a/packages/ti/drv/dss/examples/dss_display_test/dss_display_test_prf.cfg b/packages/ti/drv/dss/examples/dss_display_test/dss_display_test_prf.cfg
--- /dev/null
@@ -0,0 +1,9 @@
+var Load = xdc.useModule('ti.sysbios.utils.Load');
+
+/* load calculation related settings */
+Load.swiEnabled = true;
+Load.hwiEnabled = true;
+Load.taskEnabled = true;
+Load.updateInIdle = true;
+Load.windowInMs = 500;
+Load.postUpdate = '&Utils_prfLoadUpdate';
diff --git a/packages/ti/drv/dss/examples/dss_display_test/main_baremetal.c b/packages/ti/drv/dss/examples/dss_display_test/main_baremetal.c
--- /dev/null
@@ -0,0 +1,102 @@
+/*
+ * Copyright (c) Texas Instruments Incorporated 2018
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * \file main_baremetal.c
+ *
+ * \brief Main file for baremetal build
+ */
+
+/* ========================================================================== */
+/* Include Files */
+/* ========================================================================== */
+
+#include <stdio.h>
+#include <stdint.h>
+#include <ti/board/board.h>
+#include <ti/drv/dss/examples/utils/app_utils.h>
+#include "dss_display_test.h"
+
+/* ========================================================================== */
+/* Macros & Typedefs */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/* Structure Declarations */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/* Function Declarations */
+/* ========================================================================== */
+
+extern int32_t Dss_displayTest(void);
+
+/* ========================================================================== */
+/* Global Variables */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/* Function Definitions */
+/* ========================================================================== */
+
+int main(void)
+{
+ Board_initCfg boardCfg;
+
+ boardCfg = BOARD_INIT_PINMUX_CONFIG |
+ BOARD_INIT_UNLOCK_MMR |
+ BOARD_INIT_UART_STDIO;
+ Board_init(boardCfg);
+
+#if defined (SOC_AM65XX)
+ App_configureLCD(APP_OUTPUT_OLDI);
+#else
+#if (1U == DISP_APP_TEST_EDP)
+ App_configureLCD(APP_OUTPUT_EDP);
+#else
+ App_configureLCD(APP_OUTPUT_HDMI);
+#endif
+#endif
+
+ App_configureSoC();
+
+ Dss_displayTest();
+
+ return(0);
+}
diff --git a/packages/ti/drv/dss/examples/dss_display_test/main_tirtos.c b/packages/ti/drv/dss/examples/dss_display_test/main_tirtos.c
--- /dev/null
@@ -0,0 +1,183 @@
+/*
+ * Copyright (c) Texas Instruments Incorporated 2018
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * \file main_tirtos.c
+ *
+ * \brief Main file for TI-RTOS build
+ */
+
+/* ========================================================================== */
+/* Include Files */
+/* ========================================================================== */
+
+#include <stdio.h>
+/* XDCtools Header files */
+#include <xdc/std.h>
+#include <xdc/runtime/Error.h>
+#include <xdc/runtime/System.h>
+/* BIOS Header files */
+#include <ti/sysbios/BIOS.h>
+#include <ti/sysbios/knl/Task.h>
+#include <ti/board/board.h>
+#include <ti/drv/dss/examples/utils/app_utils.h>
+#include "dss_display_test.h"
+
+/* ========================================================================== */
+/* Macros & Typedefs */
+/* ========================================================================== */
+
+/* Test application stack size */
+#define DISP_APP_TSK_STACK_MAIN (10U * 1024U)
+
+/* ========================================================================== */
+/* Structure Declarations */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/* Function Declarations */
+/* ========================================================================== */
+
+static Void taskFxn(UArg a0, UArg a1);
+extern int32_t Dss_displayTest(void);
+
+/* ========================================================================== */
+/* Global Variables */
+/* ========================================================================== */
+
+/* Test application stack */
+static uint8_t gDispAppTskStackMain[DISP_APP_TSK_STACK_MAIN];
+
+/* ========================================================================== */
+/* Function Definitions */
+/* ========================================================================== */
+
+int main(void)
+{
+ Task_Handle task;
+ Error_Block eb;
+ Task_Params taskParams;
+
+ Error_init(&eb);
+
+ /* Initialize the task params */
+ Task_Params_init(&taskParams);
+ /* Set the task priority higher than the default priority (1) */
+ taskParams.priority = 2;
+ taskParams.stack = gDispAppTskStackMain;
+ taskParams.stackSize = sizeof(gDispAppTskStackMain);
+
+ task = Task_create(taskFxn, &taskParams, &eb);
+ if(NULL == task)
+ {
+ BIOS_exit(0);
+ }
+ BIOS_start(); /* does not return */
+
+ return(0);
+}
+
+static Void taskFxn(UArg a0, UArg a1)
+{
+#if(1U == DISP_APP_TEST_MULTISYNC)
+ uint32_t regVal;
+#endif
+ Board_initCfg boardCfg;
+
+ boardCfg = BOARD_INIT_PINMUX_CONFIG |
+ BOARD_INIT_UNLOCK_MMR |
+ BOARD_INIT_UART_STDIO;
+ Board_init(boardCfg);
+
+#if defined (SOC_AM65XX)
+ App_configureLCD(APP_OUTPUT_OLDI);
+#else
+#if (1U == DISP_APP_TEST_EDP)
+ App_configureLCD(APP_OUTPUT_EDP);
+#else
+ App_configureLCD(APP_OUTPUT_HDMI);
+#if (1U == DISP_APP_TEST_MULTISYNC)
+ /* HSYNC mode 14 <- VP0 HSYNC */
+ regVal = CSL_REG32_RD(CSL_CTRL_MMR0_CFG0_BASE +
+ CSL_MAIN_CTRL_MMR_CFG0_PADCONFIG38);
+ CSL_FINS(regVal,
+ MAIN_CTRL_MMR_CFG0_PADCONFIG38_MUXMODE,
+ 0xEU);
+ CSL_REG32_WR(CSL_CTRL_MMR0_CFG0_BASE +
+ CSL_MAIN_CTRL_MMR_CFG0_PADCONFIG38, regVal);
+
+ /* DE MODE 14 <- VP0 DE */
+ regVal = CSL_REG32_RD(CSL_CTRL_MMR0_CFG0_BASE +
+ CSL_MAIN_CTRL_MMR_CFG0_PADCONFIG39);
+ CSL_FINS(regVal,
+ MAIN_CTRL_MMR_CFG0_PADCONFIG39_MUXMODE,
+ 0xEU);
+ CSL_REG32_WR(CSL_CTRL_MMR0_CFG0_BASE +
+ CSL_MAIN_CTRL_MMR_CFG0_PADCONFIG39, regVal);
+
+ /* VSYNC MODE 14 <- VP0 VSYNC */
+ regVal = CSL_REG32_RD(CSL_CTRL_MMR0_CFG0_BASE +
+ CSL_MAIN_CTRL_MMR_CFG0_PADCONFIG40);
+ CSL_FINS(regVal,
+ MAIN_CTRL_MMR_CFG0_PADCONFIG40_MUXMODE,
+ 0xEU);
+ CSL_REG32_WR(CSL_CTRL_MMR0_CFG0_BASE +
+ CSL_MAIN_CTRL_MMR_CFG0_PADCONFIG40, regVal);
+
+ /* DPI_0_PCLK <- DPI_1_PCLK */
+ regVal = CSL_REG32_RD(CSL_CTRL_MMR0_CFG0_BASE +
+ CSL_MAIN_CTRL_MMR_CFG0_DSS_DISPC0_CLKSEL3);
+ CSL_FINS(regVal,
+ MAIN_CTRL_MMR_CFG0_DSS_DISPC0_CLKSEL3_DPI3_PCLK,
+ 0x5U);
+ CSL_REG32_WR(CSL_CTRL_MMR0_CFG0_BASE +
+ CSL_MAIN_CTRL_MMR_CFG0_DSS_DISPC0_CLKSEL3, regVal);
+#endif
+#endif
+#endif
+ App_configureSoC();
+
+ Dss_displayTest();
+
+ return;
+}
+
+#if defined(BUILD_MPU) || defined (__C7100__)
+extern void Osal_initMmuDefault(void);
+void InitMmu(void)
+{
+ Osal_initMmuDefault();
+}
+#endif
diff --git a/packages/ti/drv/dss/examples/dss_display_test/makefile b/packages/ti/drv/dss/examples/dss_display_test/makefile
--- /dev/null
@@ -0,0 +1,12 @@
+#
+# This file is the makefile for building DSS display test app for TI RTOS
+#
+ifeq ($(RULES_MAKE), )
+include $(PDK_INSTALL_PATH)/ti/build/Rules.make
+else
+include $(RULES_MAKE)
+endif
+
+APP_NAME = dss_display_testapp
+
+include makefile.mk
diff --git a/packages/ti/drv/dss/examples/dss_display_test/makefile.mk b/packages/ti/drv/dss/examples/dss_display_test/makefile.mk
--- /dev/null
@@ -0,0 +1,54 @@
+#
+# This file is the makefile for building DSS display test app for both TI RTOS
+# and baremetal
+#
+
+SRCDIR = .
+INCDIR = .
+
+# List all the external components/interfaces, whose interface header files
+# need to be included for this component
+INCLUDE_EXTERNAL_INTERFACES = pdk
+
+# List all the components required by the application
+COMP_LIST_COMMON = csl fvid2 dss
+COMP_LIST_COMMON += board uart sciclient pm_lib i2c
+
+ifeq ($(BUILD_OS_TYPE), baremetal)
+ COMP_LIST_COMMON += osal_nonos csl_init dss_app_utils
+ SRCS_COMMON = main_baremetal.c
+ CFLAGS_LOCAL_COMMON += -DDSS_TESTAPP_BAREMETAL
+ ifeq ($(ISA),$(filter $(ISA), a53))
+ LNKFLAGS_LOCAL_$(CORE) += --entry Entry
+ endif
+else
+ INCLUDE_EXTERNAL_INTERFACES += xdc bios
+ COMP_LIST_COMMON += osal_tirtos dss_app_utils_sysbios
+ SRCS_COMMON = main_tirtos.c
+ # Enable XDC build for application by providing XDC CFG File per core
+ XDC_CFG_FILE_$(CORE) = $(PDK_INSTALL_PATH)/ti/build/$(SOC)/sysbios_$(ISA).cfg
+ XDC_CFG_UPDATE_$(CORE) = dss_display_test_prf.cfg
+endif
+
+# Common source files and CFLAGS across all platforms and cores
+PACKAGE_SRCS_COMMON = .
+SRCS_COMMON += dss_display_test.c
+CFLAGS_LOCAL_COMMON += $(PDK_CFLAGS) $(DSS_CFLAGS)
+
+# Core/SoC/platform specific source files and CFLAGS
+# Example:
+# SRCS_<core/SoC/platform-name> =
+# CFLAGS_LOCAL_<core/SoC/platform-name> =
+
+# Include common make files
+ifeq ($(MAKERULEDIR), )
+#Makerule path not defined, define this and assume relative path from ROOTDIR
+ MAKERULEDIR := $(ROOTDIR)/ti/build/makerules
+ export MAKERULEDIR
+endif
+include $(MAKERULEDIR)/common.mk
+
+# OBJs and libraries are built by using rule defined in rules_<target>.mk
+# and need not be explicitly specified here
+
+# Nothing beyond this point
diff --git a/packages/ti/drv/dss/examples/dss_display_test/makefile_baremetal b/packages/ti/drv/dss/examples/dss_display_test/makefile_baremetal
--- /dev/null
@@ -0,0 +1,14 @@
+#
+# This file is the makefile for building DSS display test app for baremetal
+#
+ifeq ($(RULES_MAKE), )
+include $(PDK_INSTALL_PATH)/ti/build/Rules.make
+else
+include $(RULES_MAKE)
+endif
+
+APP_NAME = dss_baremetal_display_testapp
+BUILD_OS_TYPE=baremetal
+CFLAGS_LOCAL_COMMON = -DDSS_APP_BAREMETAL
+
+include makefile.mk
diff --git a/packages/ti/drv/dss/examples/utils/app_utils.h b/packages/ti/drv/dss/examples/utils/app_utils.h
--- /dev/null
@@ -0,0 +1,107 @@
+/*
+ * Copyright (c) Texas Instruments Incorporated 2018
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * \file app_utils.h
+ *
+ * \brief DSS example utility header file.
+ */
+
+#ifndef APP_UTILS_H_
+#define APP_UTILS_H_
+
+/* ========================================================================== */
+/* Include Files */
+/* ========================================================================== */
+
+/* None */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* ========================================================================== */
+/* Macros & Typedefs */
+/* ========================================================================== */
+
+#if defined (SOC_AM65XX)
+#define APP_OUTPUT_OLDI (0)
+#else
+#define APP_OUTPUT_HDMI (0)
+#define APP_OUTPUT_EDP (1)
+#endif
+
+/* ========================================================================== */
+/* Structure Declarations */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/* Internal/Private Function Declarations */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/* Function Declarations */
+/* ========================================================================== */
+
+void App_configureLCD(uint32_t app_output);
+void App_configureSoC(void);
+
+/* ========================================================================== */
+/* Global Variables */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/* Internal Function Declarations (Needed for other static inlines) */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/* Static Function Definitions */
+/* ========================================================================== */
+
+/* None */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #ifndef APP_UTILS_H_ */
+
+/* @} */
diff --git a/packages/ti/drv/dss/examples/utils/app_utils_am65xx.c b/packages/ti/drv/dss/examples/utils/app_utils_am65xx.c
--- /dev/null
@@ -0,0 +1,155 @@
+/*
+ * Copyright (c) Texas Instruments Incorporated 2018
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * \file app_utils_am65xx.c
+ *
+ * \brief DSS example utility APIs for AM65xx
+ */
+
+/* ========================================================================== */
+/* Include Files */
+/* ========================================================================== */
+
+#include <stdio.h>
+#include <ti/csl/csl.h>
+#include <ti/board/board.h>
+#include <ti/csl/csl_gpio.h>
+#include <ti/board/src/evmKeystone3/include/board_i2c_io_exp.h>
+#include <ti/drv/sciclient/sciclient.h>
+#include <ti/drv/pm/pmlib.h>
+#include "app_utils.h"
+
+/* ========================================================================== */
+/* Macros & Typedefs */
+/* ========================================================================== */
+
+/* PWM pin number */
+#define PWM_GPIO_PIN (86U)
+
+/* ========================================================================== */
+/* Structure Declarations */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/* Function Declarations */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/* Global Variables */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/* Function Definitions */
+/* ========================================================================== */
+
+void App_configureSoC(void)
+{
+ /* Configure OLDI IOs */
+ uint32_t regVal;
+ regVal = CSL_REG32_RD(CSL_CTRL_MMR0_CFG0_BASE +
+ CSL_MAIN_CTRL_MMR_CFG0_OLDI_DAT0_IO_CTRL);
+ CSL_FINS(regVal,
+ MAIN_CTRL_MMR_CFG0_OLDI_DAT0_IO_CTRL_PWRDN_TX,
+ FALSE);
+ CSL_REG32_WR(CSL_CTRL_MMR0_CFG0_BASE +
+ CSL_MAIN_CTRL_MMR_CFG0_OLDI_DAT0_IO_CTRL, regVal);
+
+ regVal = CSL_REG32_RD(CSL_CTRL_MMR0_CFG0_BASE +
+ CSL_MAIN_CTRL_MMR_CFG0_OLDI_DAT1_IO_CTRL);
+ CSL_FINS(regVal,
+ MAIN_CTRL_MMR_CFG0_OLDI_DAT1_IO_CTRL_PWRDN_TX,
+ FALSE);
+ CSL_REG32_WR(CSL_CTRL_MMR0_CFG0_BASE +
+ CSL_MAIN_CTRL_MMR_CFG0_OLDI_DAT1_IO_CTRL, regVal);
+
+ regVal = CSL_REG32_RD(CSL_CTRL_MMR0_CFG0_BASE +
+ CSL_MAIN_CTRL_MMR_CFG0_OLDI_DAT2_IO_CTRL);
+ CSL_FINS(regVal,
+ MAIN_CTRL_MMR_CFG0_OLDI_DAT2_IO_CTRL_PWRDN_TX,
+ FALSE);
+ CSL_REG32_WR(CSL_CTRL_MMR0_CFG0_BASE +
+ CSL_MAIN_CTRL_MMR_CFG0_OLDI_DAT2_IO_CTRL, regVal);
+
+ regVal = CSL_REG32_RD(CSL_CTRL_MMR0_CFG0_BASE +
+ CSL_MAIN_CTRL_MMR_CFG0_OLDI_DAT3_IO_CTRL);
+ CSL_FINS(regVal,
+ MAIN_CTRL_MMR_CFG0_OLDI_DAT3_IO_CTRL_PWRDN_TX,
+ FALSE);
+ CSL_REG32_WR(CSL_CTRL_MMR0_CFG0_BASE +
+ CSL_MAIN_CTRL_MMR_CFG0_OLDI_DAT3_IO_CTRL, regVal);
+
+ regVal = CSL_REG32_RD(CSL_CTRL_MMR0_CFG0_BASE +
+ CSL_MAIN_CTRL_MMR_CFG0_OLDI_CLK_IO_CTRL);
+ CSL_FINS(regVal,
+ MAIN_CTRL_MMR_CFG0_OLDI_CLK_IO_CTRL_PWRDN_TX,
+ FALSE);
+ CSL_REG32_WR(CSL_CTRL_MMR0_CFG0_BASE +
+ CSL_MAIN_CTRL_MMR_CFG0_OLDI_CLK_IO_CTRL, regVal);
+}
+
+void App_configureLCD(uint32_t app_output)
+{
+ int32_t status = PM_SUCCESS;
+ Sciclient_init(NULL);
+ status = PMLIBClkRateSet(TISCI_DEV_OLDI_TX_CORE_MAIN_0,
+ TISCI_DEV_OLDI_TX_CORE_MAIN_0_BUS_OLDI_PLL_CLK,
+ 497500000);
+
+ if(PM_SUCCESS == status)
+ {
+ Board_i2cIoExpInit();
+ Board_i2cIoExpSetPinDirection(BOARD_I2C_IOEXP_DEVICE2_ADDR,
+ PORTNUM_1,
+ PIN_NUM_0,
+ PIN_DIRECTION_OUTPUT);
+
+ /* Pull the LCD enable to high */
+ Board_i2cIoExpPinLevelSet(BOARD_I2C_IOEXP_DEVICE2_ADDR,
+ PORTNUM_1,
+ PIN_NUM_0,
+ GPIO_SIGNAL_LEVEL_HIGH);
+
+ /* Set PWM pin as GPIO for max brightness */
+ GPIOSetDirMode_v0(CSL_GPIO1_BASE, PWM_GPIO_PIN, GPIO_DIRECTION_OUTPUT);
+ GPIOPinWrite_v0(CSL_GPIO1_BASE, PWM_GPIO_PIN, GPIO_PIN_LOW);
+ CSL_REG32_WR(CSL_CTRL_MMR0_CFG0_BASE +
+ CSL_MAIN_CTRL_MMR_CFG0_PADCONFIG190, 0x50007U);
+ }
+}
diff --git a/packages/ti/drv/dss/examples/utils/app_utils_j721e.c b/packages/ti/drv/dss/examples/utils/app_utils_j721e.c
--- /dev/null
@@ -0,0 +1,216 @@
+/*
+ * Copyright (c) Texas Instruments Incorporated 2018
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * \file app_utils.c
+ *
+ * \brief DSS example utility APIs for J7
+ */
+
+/* ========================================================================== */
+/* Include Files */
+/* ========================================================================== */
+
+#include <ti/board/src/j721e_evm/include/board_control.h>
+#include <ti/csl/soc/cslr_soc_ctrl_mmr.h>
+#include <ti/drv/sciclient/sciclient.h>
+#include <ti/drv/pm/pmlib.h>
+#include "app_utils.h"
+
+/* ========================================================================== */
+/* Macros & Typedefs */
+/* ========================================================================== */
+
+
+/* ========================================================================== */
+/* Structure Declarations */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/* Function Declarations */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/* Global Variables */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/* Function Definitions */
+/* ========================================================================== */
+
+void App_configureSoC(void)
+{
+ /* Set drive strength */
+ CSL_REG32_WR(CSL_WKUP_CTRL_MMR0_CFG0_BASE +
+ CSL_WKUP_CTRL_MMR_CFG0_H_IO_DRVSTRNGTH0_PROXY, 0xFU);
+
+ CSL_REG32_WR(CSL_WKUP_CTRL_MMR0_CFG0_BASE +
+ CSL_WKUP_CTRL_MMR_CFG0_V_IO_DRVSTRNGTH0_PROXY, 0xFU);
+}
+
+void App_configureLCD(uint32_t app_output)
+{
+ int32_t status = PM_SUCCESS;
+ uint32_t regVal;
+
+ if(APP_OUTPUT_HDMI == app_output)
+ {
+ if(PM_SUCCESS == status)
+ {
+ status = Sciclient_pmSetModuleClkParent(TISCI_DEV_DSS0,
+ TISCI_DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK,
+ TISCI_DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0,
+ SCICLIENT_SERVICE_WAIT_FOREVER);
+ }
+
+ if(PM_SUCCESS == status)
+ {
+ status = Sciclient_pmSetModuleState(TISCI_DEV_DSS0,
+ TISCI_MSG_VALUE_DEVICE_SW_STATE_ON,
+ TISCI_MSG_FLAG_AOP,
+ SCICLIENT_SERVICE_WAIT_FOREVER);
+ }
+
+ if(PM_SUCCESS == status)
+ {
+ status = Sciclient_pmModuleClkRequest(TISCI_DEV_DSS0,
+ TISCI_DEV_DSS0_DSS_FUNC_CLK,
+ TISCI_MSG_VALUE_CLOCK_SW_STATE_REQ,
+ 0,
+ SCICLIENT_SERVICE_WAIT_FOREVER);
+ }
+
+ if(PM_SUCCESS == status)
+ {
+ status = Sciclient_pmSetModuleClkFreq(TISCI_DEV_DSS0,
+ TISCI_DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK,
+ 148500000ULL,
+ 0,
+ SCICLIENT_SERVICE_WAIT_FOREVER);
+ }
+
+ if(PM_SUCCESS == status)
+ {
+ status = Sciclient_pmModuleClkRequest(TISCI_DEV_DSS0,
+ TISCI_DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK,
+ TISCI_MSG_VALUE_CLOCK_SW_STATE_REQ,
+ 0,
+ SCICLIENT_SERVICE_WAIT_FOREVER);
+ }
+ if(PM_SUCCESS == status)
+ {
+ Board_control(BOARD_CTRL_CMD_SET_HDMI_MUX, (void*) 0U);
+ Board_control(BOARD_CTRL_CMD_SET_HDMI_PD_HIGH, (void*) 0U);
+ }
+ }
+ else
+ {
+ if(PM_SUCCESS == status)
+ {
+ status = Sciclient_pmSetModuleState(TISCI_DEV_SERDES_10G0,
+ TISCI_MSG_VALUE_DEVICE_SW_STATE_ON,
+ TISCI_MSG_FLAG_AOP,
+ SCICLIENT_SERVICE_WAIT_FOREVER);
+ }
+
+ if(PM_SUCCESS == status)
+ {
+ status = Sciclient_pmSetModuleState(TISCI_DEV_DSS_EDP0,
+ TISCI_MSG_VALUE_DEVICE_SW_STATE_ON,
+ TISCI_MSG_FLAG_AOP,
+ SCICLIENT_SERVICE_WAIT_FOREVER);
+ }
+
+ /* Very Ugly Hack: Select DPI0 clk from DPI1_clk */
+ if(PM_SUCCESS == status)
+ {
+ status = Sciclient_pmSetModuleClkParent(TISCI_DEV_DSS0,
+ TISCI_DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK,
+ TISCI_DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK_PARENT_DPI0_EXT_CLKSEL_OUT0,
+ SCICLIENT_SERVICE_WAIT_FOREVER);
+ }
+
+ if(PM_SUCCESS == status)
+ {
+ status = Sciclient_pmSetModuleState(TISCI_DEV_DSS0,
+ TISCI_MSG_VALUE_DEVICE_SW_STATE_ON,
+ TISCI_MSG_FLAG_AOP,
+ SCICLIENT_SERVICE_WAIT_FOREVER);
+ }
+
+ if(PM_SUCCESS == status)
+ {
+ status = Sciclient_pmModuleClkRequest(TISCI_DEV_DSS0,
+ TISCI_DEV_DSS0_DSS_FUNC_CLK,
+ TISCI_MSG_VALUE_CLOCK_SW_STATE_REQ,
+ 0,
+ SCICLIENT_SERVICE_WAIT_FOREVER);
+ }
+
+ if(PM_SUCCESS == status)
+ {
+ status = Sciclient_pmSetModuleClkFreq(TISCI_DEV_DSS0,
+ TISCI_DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK,
+ 148500000ULL,
+ 0,
+ SCICLIENT_SERVICE_WAIT_FOREVER);
+ }
+
+ if(PM_SUCCESS == status)
+ {
+ status = Sciclient_pmModuleClkRequest(TISCI_DEV_DSS0,
+ TISCI_DEV_DSS0_DSS_INST0_DPI_1_IN_2X_CLK,
+ TISCI_MSG_VALUE_CLOCK_SW_STATE_REQ,
+ 0,
+ SCICLIENT_SERVICE_WAIT_FOREVER);
+ }
+
+ if(PM_SUCCESS == status)
+ {
+ regVal = CSL_REG32_RD(CSL_CTRL_MMR0_CFG0_BASE +
+ CSL_MAIN_CTRL_MMR_CFG0_DSS_DISPC0_CLKSEL3);
+ CSL_FINS(regVal,
+ MAIN_CTRL_MMR_CFG0_DSS_DISPC0_CLKSEL3_DPI3_PCLK,
+ 0x5U);
+ CSL_REG32_WR(CSL_CTRL_MMR0_CFG0_BASE +
+ CSL_MAIN_CTRL_MMR_CFG0_DSS_DISPC0_CLKSEL3, regVal);
+ }
+ }
+
+}
diff --git a/packages/ti/drv/dss/examples/utils/app_utils_prf.c b/packages/ti/drv/dss/examples/utils/app_utils_prf.c
--- /dev/null
@@ -0,0 +1,484 @@
+/*
+ * Copyright (c) Texas Instruments Incorporated 2018
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * \file utils_prf.c
+ *
+ * \brief Profiling API utility file.
+ *
+ */
+
+/* ========================================================================== */
+/* Include Files */
+/* ========================================================================== */
+
+#include <stdio.h>
+#include <string.h>
+#include <xdc/runtime/System.h>
+#include <xdc/runtime/Types.h>
+#include <xdc/runtime/Timestamp.h>
+#include <ti/sysbios/hal/Hwi.h>
+#include <ti/sysbios/utils/Load.h>
+#include <ti/sysbios/knl/Task.h>
+#include <ti/osal/SemaphoreP.h>
+#include <ti/osal/TaskP.h>
+#include <ti/csl/csl_types.h>
+#include <ti/csl/csl_error.h>
+#include "app_utils_prf.h"
+
+
+/* ========================================================================== */
+/* Macros & Typedefs */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/* Structure Declarations */
+/* ========================================================================== */
+
+typedef struct
+{
+ uint32_t isAlloc;
+ char name[32];
+ TaskP_Handle pTsk;
+ uint64_t totalTskThreadTime;
+} Utils_PrfLoadObj;
+
+typedef struct
+{
+ Utils_PrfTsHndl tsObj[UTILS_PRF_MAX_HNDL];
+ Utils_PrfLoadObj loadObj[UTILS_PRF_MAX_HNDL];
+} Utils_PrfObj;
+
+typedef struct
+{
+ uint64_t totalSwiThreadTime;
+ uint64_t totalHwiThreadTime;
+ uint64_t totalTime;
+ uint64_t totalIdlTskTime;
+} Utils_AccPrfLoadObj;
+
+/* ========================================================================== */
+/* Function Declarations */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/* Global Variables */
+/* ========================================================================== */
+
+static Utils_PrfObj gUtils_prfObj;
+static Utils_AccPrfLoadObj gUtils_accPrfLoadObj;
+static uint32_t gUtils_startLoadCalc = 0;
+
+/* ========================================================================== */
+/* Function Definitions */
+/* ========================================================================== */
+
+uint32_t AppUtils_getCurTimeInMsec(void)
+{
+ uint64_t curTimeMsec, curTimeUsec;
+
+ curTimeUsec = TimerP_getTimeInUsecs();
+ curTimeMsec = (curTimeUsec / 1000U);
+
+ return ((uint32_t) curTimeMsec);
+}
+
+int32_t Utils_prfInit(void)
+{
+ memset(&gUtils_prfObj, 0, sizeof (gUtils_prfObj));
+ memset(&gUtils_accPrfLoadObj, 0, sizeof (Utils_AccPrfLoadObj));
+
+ return (0);
+}
+
+int32_t Utils_prfDeInit(void)
+{
+ return (0);
+}
+
+Utils_PrfTsHndl *Utils_prfTsCreate(const char *name)
+{
+ uint32_t hndlId;
+ uint32_t cookie;
+ Utils_PrfTsHndl *pHndl = NULL;
+
+ cookie = Hwi_disable();
+
+ for (hndlId = 0; hndlId < UTILS_PRF_MAX_HNDL; hndlId++)
+ {
+ pHndl = &gUtils_prfObj.tsObj[hndlId];
+
+ if(FALSE == pHndl->isAlloc)
+ {
+ /* One less for NULL character */
+ strncpy(pHndl->name, name, ((uint32_t) sizeof (pHndl->name) - 1U));
+ pHndl->name[sizeof (pHndl->name) - 1U] = (UInt8) '\0';
+ pHndl->isAlloc = (uint32_t) TRUE;
+ Utils_prfTsReset(pHndl);
+ break;
+ }
+ }
+
+ Hwi_restore(cookie);
+
+ return (pHndl);
+}
+
+int32_t Utils_prfTsDelete(Utils_PrfTsHndl *pHndl)
+{
+ pHndl->isAlloc = (uint32_t) FALSE;
+ return (0);
+}
+
+uint64_t Utils_prfTsBegin(Utils_PrfTsHndl *pHndl)
+{
+ pHndl->startTs = Utils_prfTsGet64();
+
+ return (pHndl->startTs);
+}
+
+uint64_t Utils_prfTsEnd(Utils_PrfTsHndl *pHndl, uint32_t numFrames)
+{
+ return (Utils_prfTsDelta(pHndl, pHndl->startTs, numFrames));
+}
+
+uint64_t Utils_prfTsDelta(Utils_PrfTsHndl *pHndl,
+ uint64_t startTime,
+ uint32_t numFrames)
+{
+ uint64_t endTs;
+ uint32_t cookie;
+
+ endTs = Utils_prfTsGet64();
+
+ cookie = Hwi_disable();
+
+ pHndl->totalTs += (endTs - pHndl->startTs);
+ pHndl->count++;
+ pHndl->numFrames += numFrames;
+
+ Hwi_restore(cookie);
+
+ return (endTs);
+}
+
+int32_t Utils_prfTsReset(Utils_PrfTsHndl *pHndl)
+{
+ uint32_t cookie;
+
+ cookie = Hwi_disable();
+
+ pHndl->totalTs = 0;
+ pHndl->count = 0;
+ pHndl->numFrames = 0;
+
+ Hwi_restore(cookie);
+
+ return (0);
+}
+
+uint64_t Utils_prfTsGet64(void)
+{
+ uint64_t curTs;
+ Types_Timestamp64 ts64;
+
+ Timestamp_get64(&ts64);
+
+ curTs = ((uint64_t) ts64.hi << 32) | ts64.lo;
+
+ return (curTs);
+}
+
+int32_t Utils_prfTsPrint(Utils_PrfTsHndl *pHndl, uint32_t resetAfterPrint, uint32_t trace)
+{
+ uint32_t cpuKhz;
+ uint32_t timeMs, fps, fpc;
+ Types_FreqHz cpuHz;
+
+ Timestamp_getFreq(&cpuHz);
+
+ cpuKhz = cpuHz.lo / (uint32_t) 1000U; /* convert to Khz */
+
+ timeMs = pHndl->totalTs / cpuKhz;
+
+ if(0U == timeMs)
+ {
+ fps = 0U;
+ }
+ else
+ {
+ fps = (pHndl->numFrames * (uint32_t) 1000U) / timeMs;
+ }
+ if(0U == pHndl->count)
+ {
+ fpc = 0U;
+ }
+ else
+ {
+ fpc = pHndl->numFrames / pHndl->count;
+ }
+
+ printf(
+ " %d: PRF : %s : t: %d ms, count: %d, frames: %d, fps: %d, fpc: %d \r\n",
+ AppUtils_getCurTimeInMsec(),
+ pHndl->name,
+ timeMs, /* in msecs */
+ pHndl->count,
+ pHndl->numFrames,
+ fps, /* frames per second */
+ fpc /* frames per count */
+ );
+
+ if(resetAfterPrint)
+ {
+ Utils_prfTsReset(pHndl);
+ }
+
+ return (0);
+}
+
+int32_t Utils_prfTsPrintAll(uint32_t resetAfterPrint, uint32_t trace)
+{
+ uint32_t hndlId;
+ Utils_PrfTsHndl *pHndl;
+
+ printf("\r\n");
+
+ for (hndlId = 0; hndlId < UTILS_PRF_MAX_HNDL; hndlId++)
+ {
+ pHndl = &gUtils_prfObj.tsObj[hndlId];
+
+ if(TRUE == pHndl->isAlloc)
+ {
+ Utils_prfTsPrint(pHndl, resetAfterPrint, trace);
+ }
+ }
+
+ printf("\r\n");
+
+ return (0);
+}
+
+int32_t Utils_prfLoadRegister(TaskP_Handle pTsk, const char *name)
+{
+ uint32_t hndlId;
+ uint32_t cookie;
+ int32_t status = CSL_EFAIL;
+ Utils_PrfLoadObj *pHndl;
+
+ cookie = Hwi_disable();
+
+ for (hndlId = 0; hndlId < UTILS_PRF_MAX_HNDL; hndlId++)
+ {
+ pHndl = &gUtils_prfObj.loadObj[hndlId];
+
+ if(FALSE == pHndl->isAlloc)
+ {
+ pHndl->isAlloc = (uint32_t) TRUE;
+ pHndl->pTsk = pTsk;
+ /* One less for NULL character */
+ strncpy(pHndl->name, name, ((uint32_t) sizeof (pHndl->name) - 1U));
+ pHndl->name[sizeof (pHndl->name) - 1U] = (UInt8) '\0';
+ status = CSL_SOK;
+ break;
+ }
+ }
+
+ Hwi_restore(cookie);
+
+ return (status);
+}
+
+int32_t Utils_prfLoadUnRegister(TaskP_Handle pTsk)
+{
+ uint32_t hndlId;
+ uint32_t cookie;
+ int32_t status = CSL_EFAIL;
+ Utils_PrfLoadObj *pHndl;
+
+ cookie = Hwi_disable();
+
+ for (hndlId = 0; hndlId < UTILS_PRF_MAX_HNDL; hndlId++)
+ {
+ pHndl = &gUtils_prfObj.loadObj[hndlId];
+
+ if((TRUE == pHndl->isAlloc) && (pHndl->pTsk == pTsk))
+ {
+ pHndl->isAlloc = (uint32_t) FALSE;
+ status = CSL_SOK;
+ break;
+ }
+ }
+
+ Hwi_restore(cookie);
+
+ return (status);
+}
+
+int32_t Utils_prfLoadPrintAll(uint32_t printTskLoad, uint32_t trace)
+{
+ uint32_t hwiLoad, swiLoad, tskLoad, hndlId, cpuLoad;
+ Utils_PrfLoadObj *pHndl;
+
+ hwiLoad = (uint32_t) ((gUtils_accPrfLoadObj.totalHwiThreadTime *
+ (uint64_t) 100U) / gUtils_accPrfLoadObj.totalTime);
+ swiLoad = (uint32_t) ((gUtils_accPrfLoadObj.totalSwiThreadTime *
+ (uint64_t) 100U) / gUtils_accPrfLoadObj.totalTime);
+ cpuLoad = (uint32_t) 100U -
+ (uint32_t) ((gUtils_accPrfLoadObj.totalIdlTskTime *
+ (uint64_t) 100U) /
+ gUtils_accPrfLoadObj.totalTime);
+
+ printf("\r\n");
+ printf(
+ " %d: LOAD: CPU: %d%%, HWI: %d%%, SWI:%d%% \r\n",
+ AppUtils_getCurTimeInMsec(),
+ cpuLoad,
+ hwiLoad,
+ swiLoad);
+
+ if(((uint32_t) TRUE) == printTskLoad)
+ {
+ for (hndlId = 0; hndlId < UTILS_PRF_MAX_HNDL; hndlId++)
+ {
+ pHndl = &gUtils_prfObj.loadObj[hndlId];
+
+ if(TRUE == pHndl->isAlloc)
+ {
+ tskLoad = (uint32_t) ((pHndl->totalTskThreadTime *
+ (uint64_t) 100U) /
+ gUtils_accPrfLoadObj.totalTime);
+
+ printf(
+ " %d: LOAD: TSK: %s: %d%% \r\n",
+ AppUtils_getCurTimeInMsec(),
+ pHndl->name,
+ tskLoad);
+ }
+ }
+ }
+
+ printf("\r\n");
+
+ return (0);
+}
+
+void Utils_prfLoadCalcStart(void)
+{
+ uint32_t cookie;
+
+ cookie = Hwi_disable();
+ gUtils_startLoadCalc = (uint32_t) TRUE;
+ Hwi_restore(cookie);
+
+ return;
+}
+
+void Utils_prfLoadCalcStop(void)
+{
+ uint32_t cookie;
+
+ cookie = Hwi_disable();
+ gUtils_startLoadCalc = FALSE;
+ Hwi_restore(cookie);
+
+ return;
+}
+
+void Utils_prfLoadCalcReset(void)
+{
+ uint32_t hndlId;
+ Utils_PrfLoadObj *pHndl;
+
+ gUtils_accPrfLoadObj.totalHwiThreadTime = 0;
+ gUtils_accPrfLoadObj.totalSwiThreadTime = 0;
+ gUtils_accPrfLoadObj.totalTime = 0;
+ gUtils_accPrfLoadObj.totalIdlTskTime = 0;
+
+ /* Reset the performace loads accumulator */
+ for (hndlId = 0; hndlId < UTILS_PRF_MAX_HNDL; hndlId++)
+ {
+ pHndl = &gUtils_prfObj.loadObj[hndlId];
+
+ if(((uint32_t) TRUE == pHndl->isAlloc) &&
+ (pHndl->pTsk != NULL))
+ {
+ pHndl->totalTskThreadTime = 0;
+ }
+ }
+
+ return;
+}
+
+/* Function called by Loadupdate for each update cycle */
+void Utils_prfLoadUpdate(void)
+{
+ uint32_t hndlId;
+ Load_Stat hwiLoadStat, swiLoadStat, tskLoadStat, idlTskLoadStat;
+ TaskP_Handle idlTskHndl = NULL;
+ Utils_PrfLoadObj *pHndl;
+
+ if(((uint32_t) TRUE) == (uint32_t) gUtils_startLoadCalc)
+ {
+ idlTskHndl = Task_getIdleTask();
+
+ /* Get the all loads first */
+ Load_getGlobalHwiLoad(&hwiLoadStat);
+ Load_getGlobalSwiLoad(&swiLoadStat);
+ Load_getTaskLoad(idlTskHndl, &idlTskLoadStat);
+
+ gUtils_accPrfLoadObj.totalHwiThreadTime += hwiLoadStat.threadTime;
+ gUtils_accPrfLoadObj.totalSwiThreadTime += swiLoadStat.threadTime;
+ gUtils_accPrfLoadObj.totalTime += hwiLoadStat.totalTime;
+ gUtils_accPrfLoadObj.totalIdlTskTime += idlTskLoadStat.threadTime;
+
+ /* Call the load updated function of each registered task one by one
+ * along with the swiLoad, hwiLoad, and Task's own load */
+ for (hndlId = 0; hndlId < UTILS_PRF_MAX_HNDL; hndlId++)
+ {
+ pHndl = &gUtils_prfObj.loadObj[hndlId];
+
+ if(((uint32_t) TRUE == pHndl->isAlloc) &&
+ (pHndl->pTsk != NULL))
+ {
+ Load_getTaskLoad(pHndl->pTsk, &tskLoadStat);
+ pHndl->totalTskThreadTime += tskLoadStat.threadTime;
+ }
+ }
+ }
+
+ return;
+}
diff --git a/packages/ti/drv/dss/examples/utils/app_utils_prf.h b/packages/ti/drv/dss/examples/utils/app_utils_prf.h
--- /dev/null
@@ -0,0 +1,282 @@
+/*
+ * Copyright (c) Texas Instruments Incorporated 2018
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * \ingroup UTILS_API
+ * \defgroup UTILS_PRF_API Profiling API
+ * @{
+ */
+
+/**
+ * \file utils_prf.h
+ *
+ * \brief Profiling API.
+ *
+ * - APIs to measure and print elasped time @ 64-bit precision
+ * - Utils_prfTsXxxx
+ *
+ * - APIs to measure and print CPU load at task, HWI, SWI, global level
+ * - Utils_prfLoadXxxx
+ */
+
+#ifndef UTILS_PRF_H_
+#define UTILS_PRF_H_
+
+/* ========================================================================== */
+/* Include Files */
+/* ========================================================================== */
+
+#include <ti/osal/osal.h>
+#include <ti/osal/TaskP.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* ========================================================================== */
+/* Macros & Typedefs */
+/* ========================================================================== */
+
+/** \brief Maximum supported profiling objects */
+#define UTILS_PRF_MAX_HNDL (64U)
+
+/* ========================================================================== */
+/* Structure Declarations */
+/* ========================================================================== */
+
+/**
+ * \brief Profiling load object.
+ */
+typedef struct
+{
+ int32_t cpuLoad;
+ /**< CPU load. */
+ int32_t hwiLoad;
+ /**< HWI load. */
+ int32_t swiLoad;
+ /**< SWI load. */
+ int32_t tskLoad;
+ /**< TSK load. */
+} Utils_PrfLoad;
+
+/** \brief Typedef for the loadupdate function for the user. */
+typedef void (*Utils_loadUpdate)(Utils_PrfLoad *prfLoad);
+
+/**
+ * \brief Profiling time-stamp object.
+ */
+typedef struct
+{
+ char name[32];
+ /**< Name. */
+ uint32_t isAlloc;
+ /**< Indicates if the object is initialized (used). */
+ uint64_t startTs;
+ /**< Start time stamp value. */
+ uint64_t totalTs;
+ /**< Total time stamp value. */
+ uint32_t count;
+ /**< Number of times time stamp delta is calculated. */
+ uint32_t numFrames;
+ /**< Total number of frames being used for time-stamping. */
+} Utils_PrfTsHndl;
+
+/* ========================================================================== */
+/* Function Declarations */
+/* ========================================================================== */
+
+uint32_t AppUtils_getCurTimeInMsec(void);
+
+/**
+ * \brief Initializes the profiling utility.
+ *
+ * This function must be called before using any peformance or Timestamp utils
+ *
+ * \return 0 on success, else failure
+ */
+int32_t Utils_prfInit(void);
+
+/**
+ * \brief De-initializes the profiling utility.
+ *
+ * \return 0 on success, else failure
+ */
+int32_t Utils_prfDeInit(void);
+
+/**
+ * \brief Creates the handle for the time stamp taking.
+ *
+ * \param name [IN] Name of the time stamp object
+ *
+ * \return Valid handle on success, else NULL
+ */
+Utils_PrfTsHndl *Utils_prfTsCreate(const char *name);
+
+/**
+ * \brief Deletes the handle for the timestamp.
+ *
+ * \param pHndl [IN] Handle to be deleted
+ *
+ * \return 0 on success, else failure
+ */
+int32_t Utils_prfTsDelete(Utils_PrfTsHndl *pHndl);
+
+/**
+ * \brief Start taking the timestamp.
+ *
+ * \param pHndl [IN] Handle to be time stamp object
+ *
+ * \return Initial time stamp value on success
+ */
+uint64_t Utils_prfTsBegin(Utils_PrfTsHndl *pHndl);
+
+/**
+ * \brief Stop taking the timestamp.
+ *
+ * \param pHndl [IN] Handle to be time stamp object
+ * \param numFrames [IN] Number of associated with the time stamp
+ *
+ * \return Final time stamp value on success
+ */
+uint64_t Utils_prfTsEnd(Utils_PrfTsHndl *pHndl, uint32_t numFrames);
+
+/**
+ * \brief Update the CPU load information for all profile handles
+ */
+void Utils_prfLoadUpdate(void);
+
+/**
+ * \brief Calculates the difference between the timestamp.
+ *
+ * \param pHndl [IN] Handle to be time stamp object
+ * \param startTime [IN] Start time stamp value
+ * \param numFrames [IN] Number of associated with the time stamp
+ *
+ * \return Final time stamp value on success
+ */
+uint64_t Utils_prfTsDelta(Utils_PrfTsHndl *pHndl,
+ uint64_t startTime,
+ uint32_t numFrames);
+
+/**
+ * \brief Resets the timestamp counter for that handle.
+ *
+ * \param pHndl [IN] Handle to be time stamp object
+ *
+ * \return 0 on success, else failure
+ */
+int32_t Utils_prfTsReset(Utils_PrfTsHndl *pHndl);
+
+/**
+ * \brief Gets the 64-bit timer ticks
+ *
+ * \return Current 64-bit timer ticks value on success
+ */
+uint64_t Utils_prfTsGet64(void);
+
+/**
+ * \brief Prints the timestamp difference and resets the counter thereafter
+ * depending on specified resetAfterPrint parameter.
+ *
+ * \param pHndl [IN] Handle to be time stamp object
+ * \param resetAfterPrint [IN] Indicates whether time stamp values should be
+ * reset after printing
+ *
+ * \return 0 on success, else failure
+ */
+int32_t Utils_prfTsPrint(Utils_PrfTsHndl *pHndl, uint32_t resetAfterPrint, uint32_t trace);
+
+/**
+ * \brief Prints the timestamp difference for all registered handles and resets
+ * the counter thereafter depending on specified resetAfterPrint
+ * parameter.
+ *
+ * \param resetAfterPrint [IN] Indicates whether time stamp values should be
+ * reset after printing
+ *
+ * \return 0 on success, else failure
+ */
+int32_t Utils_prfTsPrintAll(uint32_t resetAfterPrint, uint32_t trace);
+
+/**
+ * \brief Registers a task for load calculation.
+ *
+ * \param pTsk [IN] Handle to task object to be registered for load
+ * calculation
+ * \param name [IN] Name to be associated with the registered handle
+ *
+ * \return 0 on success, else failure
+ */
+int32_t Utils_prfLoadRegister(TaskP_Handle pTsk, const char *name);
+/**
+ * \brief Un-registers a task for load calculation.
+ *
+ * \param pTsk [IN] Handle to task object to be unregistered for
+ * load calculation
+ *
+ * \return 0 on success, else failure
+ */
+int32_t Utils_prfLoadUnRegister(TaskP_Handle pTsk);
+
+/**
+ * \brief Prints loads for all the registered tasks. Also prints information
+ * for each task depending on the specified printTskLoad parameter.
+ *
+ * \param printTskLoad [IN] Indicates whether load information for each
+ * registered task should be printed.
+ *
+ * \return 0 on success, else failure
+ */
+int32_t Utils_prfLoadPrintAll(uint32_t printTskLoad, uint32_t trace);
+
+/**
+ * \brief Start taking the performance load for all the registered tasks.
+ */
+void Utils_prfLoadCalcStart(void);
+
+/**
+ * \brief Stop taking the load for all the registered tasks.
+ */
+void Utils_prfLoadCalcStop(void);
+
+/**
+ * \brief Reset the load calculation mainly for next cycle of run.
+ */
+void Utils_prfLoadCalcReset(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ifndef UTILS_PRF_H_ */
+
+/* @} */
diff --git a/packages/ti/drv/dss/examples/utils/makefile b/packages/ti/drv/dss/examples/utils/makefile
--- /dev/null
@@ -0,0 +1,17 @@
+#
+# This file is the makefile for building DSS app utils library.
+#
+ifeq ($(RULES_MAKE), )
+include $(PDK_INSTALL_PATH)/ti/build/Rules.make
+else
+include $(RULES_MAKE)
+endif
+
+MODULE_NAME = dss_app_utils
+
+INCLUDE_EXTERNAL_INTERFACES =
+
+SRCS_COMMON =
+
+include makefile.mk
+# Nothing beyond this point
diff --git a/packages/ti/drv/dss/examples/utils/makefile.mk b/packages/ti/drv/dss/examples/utils/makefile.mk
--- /dev/null
@@ -0,0 +1,36 @@
+#
+# This file is the makefile for building DSS app utils library.
+#
+
+SRCDIR = .
+INCDIR = .
+
+# List all the external components/interfaces, whose interface header files
+# need to be included for this component
+INCLUDE_EXTERNAL_INTERFACES += pdk
+INCLUDE_INTERNAL_INTERFACES = csl
+
+# Common source files and CFLAGS across all platforms and cores
+SRCS_COMMON += app_utils_$(SOC).c
+
+PACKAGE_SRCS_COMMON = .
+CFLAGS_LOCAL_COMMON = $(PDK_CFLAGS) $(DSS_CFLAGS)
+
+# Core/SoC/platform specific source files and CFLAGS
+# Example:
+# SRCS_<core/SoC/platform-name> =
+# CFLAGS_LOCAL_<core/SoC/platform-name> =
+
+# Include common make files
+ifeq ($(MAKERULEDIR), )
+#Makerule path not defined, define this and assume relative path from ROOTDIR
+ MAKERULEDIR := $(ROOTDIR)/ti/build/makerules
+ export MAKERULEDIR
+endif
+include $(MAKERULEDIR)/common.mk
+
+# OBJs and libraries are built by using rule defined in rules_<target>.mk
+# and need not be explicitly specified here
+
+# Nothing beyond this point
+
diff --git a/packages/ti/drv/dss/examples/utils/makefile_sysbios b/packages/ti/drv/dss/examples/utils/makefile_sysbios
--- /dev/null
@@ -0,0 +1,17 @@
+#
+# This file is the makefile for building DSS app utils library.
+#
+ifeq ($(RULES_MAKE), )
+include $(PDK_INSTALL_PATH)/ti/build/Rules.make
+else
+include $(RULES_MAKE)
+endif
+
+MODULE_NAME = dss_app_utils_sysbios
+
+INCLUDE_EXTERNAL_INTERFACES = xdc bios
+
+SRCS_COMMON = app_utils_prf.c
+
+include makefile.mk
+# Nothing beyond this point
diff --git a/packages/ti/drv/dss/include/dss_cfg.h b/packages/ti/drv/dss/include/dss_cfg.h
--- /dev/null
@@ -0,0 +1,103 @@
+/*
+ * Copyright (c) Texas Instruments Incorporated 2018
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * \ingroup DRV_DSS_MODULE
+ * \defgroup DRV_DSS_CFG_MODULE DSS Driver Configurations
+ * This is documentation for DSS driver configuration
+ *
+ * @{
+ */
+
+/**
+ * \file dss_cfg.h
+ *
+ * \brief DSS Driver configuration file.
+ */
+
+#ifndef DSS_CFG_H_
+#define DSS_CFG_H_
+
+/* ========================================================================== */
+/* Include Files */
+/* ========================================================================== */
+
+/* None */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* ========================================================================== */
+/* Macros & Typedefs */
+/* ========================================================================== */
+
+/** \brief Default max number of frames that can be queued per display driver
+ * instance */
+#define DSS_DEF_QUEUE_LEN_PER_INST (16U)
+
+/** \brief Log enable for DSS module */
+#define DssTrace ((uint32_t) GT_ERR | \
+ (uint32_t) GT_TraceState_Enable)
+
+/* ========================================================================== */
+/* Structure Declarations */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/* Internal/Private Function Declarations */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/* Function Declarations */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/* Static Function Definitions */
+/* ========================================================================== */
+
+/* None */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #ifndef DSS_CFG_H_ */
+
+/* @} */
diff --git a/packages/ti/drv/dss/include/dss_dctrl.h b/packages/ti/drv/dss/include/dss_dctrl.h
--- /dev/null
@@ -0,0 +1,902 @@
+/*
+ * Copyright (c) Texas Instruments Incorporated 2018
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * \ingroup DRV_DSS_MODULE
+ * \defgroup DRV_DSS_DCTRL_MODULE Display Controller Driver
+ * This is DSS Display Controller driver documentation
+ *
+ * @{
+ */
+
+/**
+ * \file dss_dctrl.h
+ *
+ * \brief DSS Controller Driver API/interface file.
+ */
+
+#ifndef DSS_DCTRL_H_
+#define DSS_DCTRL_H_
+
+/* ========================================================================== */
+/* Include Files */
+/* ========================================================================== */
+
+/* None */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* ========================================================================== */
+/* Macros & Typedefs */
+/* ========================================================================== */
+
+/**
+ * \brief Video Port sync loss callback function prototype.
+ *
+ * \param vpId [OUT] Video Port Id.
+ * \param appData [OUT] Application's private data.
+ *
+ * \return None.
+ */
+typedef void (*Dss_DctrlSyncLostCbFxn)(uint32_t vpId, void *appData);
+
+/** \brief Forward declaration for instance object. */
+typedef struct Dss_DctrlVpSafetyCbData_t Dss_DctrlVpSafetyCbData;
+
+/**
+ * \brief Video Port safety error callback function prototype.
+ *
+ * \param vpId [OUT] Video Port Id.
+ * \param safetyCbData [OUT] Safety Callback Data.
+ * Refer #Dss_DctrlVpSafetyCbData_t for details
+ * \param appData [OUT] Application's private data.
+ *
+ * \return None.
+ */
+typedef void (*Dss_DctrlSafetyErrCbFxn)(uint32_t vpId,
+ Dss_DctrlVpSafetyCbData safetyCbData,
+ void *appData);
+
+/**
+ * \brief Video Port line number callback function prototype.
+ *
+ * \param vpId [OUT] Video Port Id.
+ * \param appData [OUT] Application's private data.
+ *
+ * \return None.
+ */
+typedef void (*Dss_DctrlLineNumCbFxn)(uint32_t vpId, void *appData);
+
+/*
+ * Display controller driver IOCTLs.
+ */
+
+/**
+ * \ingroup DRV_DSS_DCTRL_MODULE
+ * \defgroup DRV_DSS_DCTRL_IOCTL Display Controller IOCTLs
+ * @{
+ *
+ * These are display controller FVID2 APIs that can be called by the
+ * application.
+ */
+
+/**
+ * \brief Command to set the DSS display path configuration.
+ *
+ * All the DSS modules handled by the Display Controller can be
+ * represented by a graph, where node represents a module like video port,
+ * overlay etc. and edge is present between two nodes if they are connected.
+ * All DSS paths can be configured by this IOCTL in one shot. Use macros
+ * defined in <dss_soc.h> for different node ids.
+ *
+ * This IOCTL takes list of edges connecting nodes and configures display
+ * paths. It first validates these paths and then configures DSS for the
+ * display paths. It configures all the modules present in the path.
+ *
+ * \param cmdArgs [IN] Pointer of type #Dss_DctrlPathInfo
+ * \param cmdArgsStatus [OUT] NULL
+ *
+ * \return FVID2_SOK if successful, else suitable error code
+ */
+#define IOCTL_DSS_DCTRL_SET_PATH (DSS_DCTRL_IOCTL_BASE + 0x01U)
+
+/**
+ * \brief Command to clear the DSS display path configuration.
+ *
+ * This IOCTL takes list of edges connecting nodes and clears the
+ * configuration. It also stops Video Ports.
+ *
+ * It does not validates the edge list. It simply disables the edge
+ * connecting nodes. For the Video Ports, it checks for the validity and
+ * then disables the video port if there are no errors.
+ * Use macros defined in <dss_soc.h> for different node ids.
+ *
+ * \param cmdArgs [IN] Pointer of type #Dss_DctrlPathInfo
+ * \param cmdArgsStatus [OUT] NULL
+ *
+ * \return FVID2_SOK if successful, else suitable error code
+ */
+#define IOCTL_DSS_DCTRL_CLEAR_PATH (DSS_DCTRL_IOCTL_BASE + 0x02U)
+
+/**
+ * \brief Command to set Video Port configuration.
+ *
+ * This IOCTL is used to set the Video Port configuration if Video Port
+ * is not on. For the enabled Video Port, port has to be stopped first,
+ * then configuration can can be changed. Refer #Dss_DctrlVpParams
+ * for configuration details.
+ * This IOCTL should be called before IOCTL_DSS_DCTRL_SET_PATH.
+ *
+ * \param cmdArgs [IN] Pointer of type #Dss_DctrlVpParams
+ * \param cmdArgsStatus [OUT] NULL
+ *
+ * \return FVID2_SOK if successful, else suitable error code
+ *
+ */
+#define IOCTL_DSS_DCTRL_SET_VP_PARAMS (DSS_DCTRL_IOCTL_BASE + 0x03U)
+
+/**
+ * \brief Command to set configuration of the given overlay.
+ *
+ * This IOCTL is used to set the different Overlay parameters. Refer
+ * #Dss_DctrlOverlayParams for configuration details.
+ * Note: In case color bar enable is TRUE then this IOCTL should be called at
+ * the end after doing all other display controller configuration.
+ *
+ * \param cmdArgs [IN] Pointer of type #Dss_DctrlOverlayParams
+ * \param cmdArgsStatus [OUT] NULL
+ *
+ * \return FVID2_SOK if successful, else suitable error code
+ *
+ */
+#define IOCTL_DSS_DCTRL_SET_OVERLAY_PARAMS (DSS_DCTRL_IOCTL_BASE + 0x04U)
+
+/**
+ * \brief Command to set layer/Z-order configuration of the given overlay.
+ *
+ * This IOCTL is used to set the layer/Z-order configuration. Refer
+ * #Dss_DctrlOverlayLayerParams for details.
+ * Note: User should pass the layer configuration for all the video pipes which
+ * are present in the DSS in order to set/change the Z order.
+ * In case a particular pipe is disabled, layerNum should be set to
+ * CSL_DSS_OVERLAY_LAYER_INVALID.
+ *
+ * \param cmdArgs [IN] Pointer of type #Dss_DctrlOverlayLayerParams
+ * \param cmdArgsStatus [OUT] NULL
+ *
+ * \return FVID2_SOK if successful, else suitable error code
+ *
+ */
+#define IOCTL_DSS_DCTRL_SET_LAYER_PARAMS (DSS_DCTRL_IOCTL_BASE + 0x05U)
+
+/**
+ * \brief Command to program the CSC coefficients for Video Port.
+ * By default BT 601 coefficients are set.
+ *
+ * \param cmdArgs [IN] Pointer of type #Dss_DctrlVpCscCoeff
+ * \param cmdArgsStatus [OUT] NULL
+ *
+ * \return FVID2_SOK if successful, else suitable error code
+ */
+#define IOCTL_DSS_DCTRL_SET_VP_CSC_COEFF (DSS_DCTRL_IOCTL_BASE + 0x06U)
+
+/**
+ * \brief Command to set advance Video Port configuration.
+ *
+ * This IOCTL is used to program the advance Video Port configuration.
+ * Refer #Dss_DctrlAdvVpParams for configuration details.
+ *
+ * \param cmdArgs [IN] Pointer of type #Dss_DctrlAdvVpParams
+ * \param cmdArgsStatus [OUT] NULL
+ *
+ * \return FVID2_SOK if successful, else suitable error code
+ */
+#define IOCTL_DSS_DCTRL_SET_ADV_VP_PARAMS (DSS_DCTRL_IOCTL_BASE + 0x07U)
+
+/**
+ * \brief Command to program blank timing parameters of given LCD.
+ *
+ * This IOCTL is used to program the blank timing parameters for the LCD.
+ * This IOCTL can be called dynamically at runtime.
+ * Note: The change in timing will take effect from the next vsync.
+ * This API should be called in the vsync callback to the application in the
+ * ISR context or immediately after that in task/swi context. Calling this
+ * IOCTL near the vsync should be avoided as the shadow to work copy could
+ * happens while we are changing the timing parameters and could result in
+ * taking only a part of this configuration for next one frame or delaying the
+ * timing change by next one frame. Subsequent frames will have proper timing.
+ *
+ * \param cmdArgs [IN] Pointer of type #Dss_DctrlLcdBlankTimingParams
+ * \param cmdArgsStatus [OUT] NULL
+ *
+ * \return FVID2_SOK if successful, else suitable error code
+ */
+#define IOCTL_DSS_DCTRL_SET_LCD_BLANK_TIMING_PARAMS \
+ (DSS_DCTRL_IOCTL_BASE + 0x08U)
+
+/**
+ * \brief Command to program Safety Check configuration at Video Port Output.
+ *
+ * This IOCTL is used to program the safety check configuration parameters.
+ * Note: There are up to four sub-regions within the active video output in
+ * which safety check can be enabled. This IOCTL should be called separately
+ * for each region.
+ *
+ * \param cmdArgs [IN] Pointer of type #Dss_DctrlVpSafetyChkParams
+ * \param cmdArgsStatus [OUT] NULL
+ *
+ * \return FVID2_SOK if successful, else suitable error code
+ */
+#define IOCTL_DSS_DCTRL_SET_VP_SAFETY_CHK_PARAMS \
+ (DSS_DCTRL_IOCTL_BASE + 0x09U)
+
+/**
+ * \brief IOCTL to get the number of errors for a given Video Port.
+ *
+ * This IOCTL is used to get the count of sync lost errors, security violations
+ * and safety check errors for a given video port.
+ *
+ * \param cmdArgs [IN] Pointer of type #Dss_DctrlVpErrorStats
+ * \param cmdArgsStatus [OUT] NULL
+ *
+ * \return FVID2_SOK if successful, else suitable error code
+ *
+ */
+#define IOCTL_DSS_DCTRL_GET_VP_ERROR_STATS (DSS_DCTRL_IOCTL_BASE + 0x0AU)
+
+/**
+ * \brief IOCTL to set the global DSS parameters.
+ *
+ * This IOCTL can be used to set the global mflag and CBA configuration.
+ *
+ * \param cmdArgs [IN] Pointer of type #Dss_DctrlGlobalDssParams
+ * \param cmdArgsStatus [OUT] NULL
+ *
+ * \return FVID2_SOK if successful, else suitable error code
+ *
+ */
+#define IOCTL_DSS_DCTRL_SET_GLOBAL_DSS_PARAMS (DSS_DCTRL_IOCTL_BASE + 0x0BU)
+
+/**
+ * \brief Command to disable Video Port.
+ *
+ * This IOCTL is used to disable the Video Port.
+ * Refer #Dss_DctrlVpParams for configuration details.
+ *
+ * \param cmdArgs [IN] Pointer of type #Dss_DctrlVpParams
+ * \param cmdArgsStatus [OUT] NULL
+ *
+ * \return FVID2_SOK if successful, else suitable error code
+ *
+ */
+#define IOCTL_DSS_DCTRL_STOP_VP (DSS_DCTRL_IOCTL_BASE + 0x0CU)
+
+/**
+ * \brief Command to register Video Port sync lost callback function.
+ *
+ * This IOCTL can be used to register a callback when there is a sync loss for
+ * a particular video port. See #Dss_DctrlSyncLostCbFxn for details. This IOCTL
+ * is per Video Port and hence should be called separately for each port.
+ * Note: syncLostCbFxn should be set to NULL in order to unregister
+ * the callback.
+ *
+ * \param cmdArgs [IN] Pointer of type #Dss_DctrlSyncLostCbParams
+ * \param cmdArgsStatus [OUT] NULL
+ *
+ * \return FVID2_SOK if successful, else suitable error code
+ */
+#define IOCTL_DSS_DCTRL_REGISTER_SYNCLOST_CB (DSS_DCTRL_IOCTL_BASE + 0x0DU)
+
+/**
+ * \brief Command to register Video Port line number callback function
+ *
+ * This IOCTL can be used to register a callback when there is a line number
+ * interrupt for a particular video port. See #Dss_DctrlLineNumCbFxn for
+ * details. This IOCTL is per Video Port and hence should be called separately
+ * for each port.
+ * Note: lineNumCbFxn should be set to NULL in order to unregister
+ * the callback.
+ *
+ * \param cmdArgs [IN] Pointer of type #Dss_DctrlLineNumCbParams
+ * \param cmdArgsStatus [OUT] NULL
+ *
+ * \return FVID2_SOK if successful, else suitable error code
+ */
+#define IOCTL_DSS_DCTRL_REGISTER_LINENUM_CB (DSS_DCTRL_IOCTL_BASE + 0x0EU)
+
+/* @} */
+
+/* ========================================================================== */
+/* Structure Declarations */
+/* ========================================================================== */
+
+/**
+ * \brief Structure containing DSS path information.
+ * This structure is used as an argument to IOCTL_DSS_DCTRL_SET_PATH.
+ * This IOCTL takes the array of edges connected between nodes.
+ */
+typedef struct
+{
+ uint32_t numEdges;
+ /**< Number edge in the edgeInfo array */
+ Fvid2_GraphEdgeInfo edgeInfo[DSS_DCTRL_MAX_EDGES];
+ /**< List of edges connecting DSS modules. Display controller parses these
+ * edges and enables/disables input/output path in the appropriate DSS
+ * module. This edge tells which module is connected to which module
+ * enabling output in edge start module and input in edge end module.*/
+} Dss_DctrlPathInfo;
+
+/**
+ * \brief Structure containing DSS sync operations configuration.
+ * This structure is used as a part of \ref Dss_DctrlVpParams.
+ */
+typedef struct
+{
+ uint32_t enabled;
+ /**< Enable sync operations configuration */
+ uint32_t isPrimary;
+ /**< Whether this VP is the primary output.
+ * Only operations on the primary VP results in H/W
+ * register operations.
+ * For secondary VPs, the enable / setGo operations
+ * pend on the corresponding operation on the primary VP */
+ uint32_t syncVpIds[CSL_DSS_VP_ID_MAX];
+ /**< Array of VP Ids for Sync operations */
+ uint32_t numSyncVpIds;
+ /**< Number of valid VP Ids in #syncVpIds */
+} Dss_DctrlSyncOpCfg;
+
+/**
+ * \brief Structure containing Video Port information.
+ * This structure is used as an argument to IOCTL_DSS_DCTRL_SET_VP_PARAMS.
+ */
+typedef struct
+{
+ uint32_t vpId;
+ /**< Video Port Id. See \ref CSL_DssVpId for values */
+ CSL_DssVpLcdOpTimingCfg lcdOpTimingCfg;
+ /**< Timing configuration for the LCD output.
+ * See \ref CSL_DssVpLcdOpTimingCfg for details */
+ CSL_DssVpLcdSignalPolarityCfg lcdPolarityCfg;
+ /**< LCD Polarity Configuration.
+ * See \ref CSL_DssVpLcdSignalPolarityCfg for details */
+ CSL_DssVpLcdTdmCfg lcdTdmCfg;
+ /**< LCD TDM Configuration. See \ref CSL_DssVpLcdTdmCfg for details */
+ Dss_DctrlSyncOpCfg syncOpCfg;
+ /**< Sync operation Configuration. See \ref Dss_DctrlSyncOpCfg for details */
+} Dss_DctrlVpParams;
+
+/**
+ * \brief Structure containing Overlay information.
+ * This structure is used as an argument to IOCTL_DSS_DCTRL_SET_OVERLAY_PARAMS.
+ */
+typedef struct
+{
+ uint32_t overlayId;
+ /**< Overlay Id. See \ref CSL_DssOverlayId for values */
+ uint32_t colorbarEnable;
+ /**< Overlay Color bar Enable. TRUE: Enable FALSE: Disable */
+ CSL_DssOverlayCfg overlayCfg;
+ /**< Overlay Configuration. See \ref CSL_DssOverlayCfg for details */
+} Dss_DctrlOverlayParams;
+
+/**
+ * \brief Structure containing Overlay layer information.
+ * This structure is used as an argument to IOCTL_DSS_DCTRL_SET_LAYER_PARAMS.
+ */
+typedef struct
+{
+ uint32_t overlayId;
+ /**< Overlay Id. See \ref CSL_DssOverlayId for values */
+ uint32_t pipeLayerNum[CSL_DSS_VID_PIPE_ID_MAX];
+ /**< Layer to which a particular Video Pipe Id is connected.
+ * For valid values see \ref CSL_DssOverlayLayerNum */
+} Dss_DctrlOverlayLayerParams;
+
+/**
+ * \brief Structure containing Video Port CSC information.
+ * This structure is used as an argument to IOCTL_DSS_DCTRL_SET_VP_CSC_COEFF.
+ */
+typedef struct
+{
+ uint32_t vpId;
+ /**< Video Port Id. See \ref CSL_DssVpId for values */
+ uint32_t cscPos;
+ /**< Position of CSC block wrt GAMMA module.
+ * Refer \ref CSL_DssVpCscPos for values */
+ CSL_DssCscCoeff cscCoeff;
+ /**< Video Port CSC coefficients.
+ * See \ref CSL_DssCscCoeff for details */
+} Dss_DctrlVpCscCoeff;
+
+/**
+ * \brief Structure containing advance Video Port information.
+ * This structure is used as an argument to IOCTL_DSS_DCTRL_SET_ADV_VP_PARAMS.
+ */
+typedef struct
+{
+ uint32_t vpId;
+ /**< Video Port Id. See \ref CSL_DssVpId for values */
+ CSL_DssVpLcdAdvSignalCfg lcdAdvSignalCfg;
+ /**< Advance Signal Configuration for the LCD.
+ * See \ref CSL_DssVpLcdAdvSignalCfg for details */
+} Dss_DctrlAdvVpParams;
+
+/**
+ * \brief Structure containing LCD Blank Timing Configuration.
+ * This structure is used as an argument to
+ * IOCTL_DSS_DCTRL_SET_LCD_BLANK_TIMING_PARAMS.
+ */
+typedef struct
+{
+ uint32_t vpId;
+ /**< Video Port Id. See \ref CSL_DssVpId for values */
+ uint32_t dvoFormat;
+ /**< Digital output format. For valid values see \ref Fvid2_DVFormat */
+ CSL_DssVpLcdBlankTimingCfg lcdBlankTimingCfg;
+ /**< Timing configuration for the LCD.
+ * See \ref CSL_DssVpLcdBlankTimingCfg for details */
+} Dss_DctrlLcdBlankTimingParams;
+
+/**
+ * \brief Structure containing Safety Check configuration for a particular
+ * region.
+ */
+typedef struct
+{
+ uint32_t regionId;
+ /**< Safety Region Id */
+ uint32_t referenceSign;
+ /**< Reference Safety Signature for Data Correctness Check */
+ CSL_DssSafetyChkCfg safetyChkCfg;
+ /**< Safety Check Configuration. See \ref CSL_DssSafetyChkCfg for details */
+} Dss_DctrlRegionSafetyChkCfg;
+
+/**
+ * \brief Structure containing safety error callback data.
+ * This structure is returned by the driver .
+ */
+struct Dss_DctrlVpSafetyCbData_t
+{
+ uint32_t regionId;
+ /**< Region Id for which interrupt has occurred */
+ uint32_t capturedSign;
+ /**< Captured Safety Signature by Data Correctness Check, set to 0x0 in case
+ * of frame freeze detect */
+};
+
+/**
+ * \brief Structure containing Safety Check configuration of Video Port.
+ * This structure is used as an argument to
+ * IOCTL_DSS_DCTRL_SET_VP_SAFETY_CHK_PARAMS.
+ */
+typedef struct
+{
+ uint32_t vpId;
+ /**< Video Port Id. See \ref CSL_DssVpId for values */
+ uint32_t safetySignSeedVal;
+ /**< Safety Signature Seed Value, only one non-zero value is possible in a
+ * particular context. In case user passes multiple non-zero values for
+ * different regions, previous value is overwritten. */
+ Dss_DctrlRegionSafetyChkCfg regionSafetyChkCfg;
+ /**< Safety Check Configuration for a particular region.
+ * See \ref Dss_DctrlRegionSafetyChkCfg for details */
+ Dss_DctrlSafetyErrCbFxn safetyErrCbFxn;
+ /**< Safety Error callback function */
+ Dss_DctrlVpSafetyCbData safetyCbData;
+ /**< Safety Error callback data to be returned to application */
+ void *appData;
+ /**< Private data of application */
+} Dss_DctrlVpSafetyChkParams;
+
+/**
+ * \brief Structure containing Error Stats of Video Port.
+ * This structure is used as an argument to IOCTL_DSS_DCTRL_GET_VP_ERROR_STATS.
+ */
+typedef struct
+{
+ uint32_t vpId;
+ /**< Video Port Id. See \ref CSL_DssVpId for values */
+ uint32_t syncLost;
+ /**< SyncLost Error Count of the LCD */
+ uint32_t safetyViolation[CSL_DSS_VP_SAFETY_REGION_MAX];
+ /**< Safety Violation Count */
+ uint32_t securityViolation;
+ /**< Security Violation Count */
+} Dss_DctrlVpErrorStats;
+
+/**
+ * \brief Structure containing global DSS Configuration.
+ * This structure is used as an argument to
+ * IOCTL_DSS_DCTRL_SET_GLOBAL_DSS_PARAMS.
+ */
+typedef struct
+{
+ CSL_DssGlobalMFlagCfg globalMflagCfg;
+ /**< Global Mflag Configuration.
+ * See \ref CSL_DssGlobalMFlagCfg for details */
+ CSL_DssCbaCfg cbaCfg;
+ /**< CBA Priority Configuration. See \ref CSL_DssCbaCfg for details */
+} Dss_DctrlGlobalDssParams;
+
+/**
+ * \brief Structure containing Sync Lost callback parameters.
+ * This structure is used as an argument to
+ * IOCTL_DSS_DCTRL_REGISTER_SYNCLOST_CB.
+ */
+typedef struct
+{
+ uint32_t vpId;
+ /**< Video Port Id. See \ref CSL_DssVpId for values */
+ Dss_DctrlSyncLostCbFxn syncLostCbFxn;
+ /**< Sync lost callback function */
+ void *appData;
+ /**< Private data of application */
+} Dss_DctrlSyncLostCbParams;
+
+/**
+ * \brief Structure containing line number interrupt callback parameters.
+ * This structure is used as an argument to
+ * IOCTL_DSS_DCTRL_REGISTER_LINENUM_CB.
+ */
+typedef struct
+{
+ uint32_t vpId;
+ /**< Video Port Id. See \ref CSL_DssVpId for values */
+ Dss_DctrlLineNumCbFxn lineNumCbFxn;
+ /**< Line number callback function */
+ void *appData;
+ /**< Private data of application */
+} Dss_DctrlLineNumCbParams;
+
+/* ========================================================================== */
+/* Internal/Private Function Declarations */
+/* ========================================================================== */
+
+/**
+ * \brief Dss_DctrlPathInfo structure init function.
+ *
+ * \param pathInfo [IN]Pointer to #Dss_DctrlPathInfo structure.
+ *
+ * \return None
+ */
+static inline void Dss_dctrlPathInfoInit(Dss_DctrlPathInfo *pathInfo);
+
+/**
+ * \brief Dss_DctrlVpParams structure init function.
+ *
+ * \param vpParams [IN]Pointer to #Dss_DctrlVpParams structure.
+ *
+ * \return None
+ */
+static inline void Dss_dctrlVpParamsInit(Dss_DctrlVpParams *vpParams);
+
+/**
+ * \brief Dss_DctrlOverlayParams structure init function.
+ *
+ * \param overlayParams [IN]Pointer to #Dss_DctrlOverlayParams structure.
+ *
+ * \return None
+ */
+static inline void Dss_dctrlOverlayParamsInit(
+ Dss_DctrlOverlayParams *overlayParams);
+
+/**
+ * \brief Dss_DctrlOverlayLayerParams structure init function.
+ *
+ * \param layerParams [IN]Pointer to #Dss_DctrlOverlayLayerParams structure.
+ *
+ * \return None
+ */
+static inline void Dss_dctrlOverlayLayerParamsInit(
+ Dss_DctrlOverlayLayerParams *layerParams);
+
+/**
+ * \brief Dss_DctrlAdvVpParams structure init function.
+ *
+ * \param advVpParams [IN]Pointer to #Dss_DctrlAdvVpParams structure.
+ *
+ * \return None
+ */
+static inline void Dss_dctrlAdvVpParamsInit(Dss_DctrlAdvVpParams *advVpParams);
+
+/**
+ * \brief Dss_DctrlLcdBlankTimingParams structure init function.
+ *
+ * \param lcdBlankTimingParams [IN]Pointer to #Dss_DctrlLcdBlankTimingParams
+ * structure.
+ *
+ * \return None
+ */
+static inline void Dss_dctrlLcdBlankTimingParamsInit(
+ Dss_DctrlLcdBlankTimingParams *lcdBlankTimingParams);
+
+/**
+ * \brief Dss_DctrlRegionSafetyChkCfg structure init function.
+ *
+ * \param regionSafetyChkCfg [IN]Pointer to #Dss_DctrlRegionSafetyChkCfg
+ * structure.
+ *
+ * \return None
+ */
+static inline void Dss_dctrlRegionSafetyChkCfgInit(
+ Dss_DctrlRegionSafetyChkCfg *regionSafetyChkCfg);
+
+/**
+ * \brief Dss_DctrlVpSafetyCbData structure init function.
+ *
+ * \param safetyCbData [IN]Pointer to #Dss_DctrlVpSafetyCbData_t structure.
+ *
+ * \return None
+ */
+static inline void Dss_dctrlVpSafetyCbDataInit(
+ Dss_DctrlVpSafetyCbData *safetyCbData);
+
+/**
+ * \brief Dss_DctrlVpSafetyChkParams structure init function.
+ *
+ * \param vpSafetyChkParams [IN]Pointer to #Dss_DctrlVpSafetyChkParams
+ * structure.
+ *
+ * \return None
+ */
+static inline void Dss_dctrlVpSafetyChkParamsInit(
+ Dss_DctrlVpSafetyChkParams *vpSafetyChkParams);
+
+/**
+ * \brief Dss_DctrlVpErrorStats structure init function.
+ *
+ * \param vpErrorStats [IN]Pointer to #Dss_DctrlVpErrorStats structure.
+ *
+ * \return None
+ */
+static inline void Dss_dctrlVpErrorStatsInit(
+ Dss_DctrlVpErrorStats *vpErrorStats);
+
+/**
+ * \brief Dss_DctrlGlobalDssParams structure init function.
+ *
+ * \param globalDssParams [IN]Pointer to #Dss_DctrlGlobalDssParams structure.
+ *
+ * \return None
+ */
+static inline void Dss_dctrlGlobalDssParamsInit(
+ Dss_DctrlGlobalDssParams *globalDssParams);
+
+/**
+ * \brief Dss_DctrlSyncLostCbParams structure init function.
+ *
+ * \param syncLostCbParams [IN]Pointer to #Dss_DctrlSyncLostCbParams structure.
+ *
+ * \return None
+ */
+static inline void Dss_dctrlSyncLostCbParamsInit(
+ Dss_DctrlSyncLostCbParams *syncLostCbParams);
+
+/**
+ * \brief Dss_DctrlLineNumCbParams structure init function.
+ *
+ * \param lineNumCbParams [IN]Pointer to #Dss_DctrlLineNumCbParams structure.
+ *
+ * \return None
+ */
+static inline void Dss_dctrlLineNumCbParamsInit(
+ Dss_DctrlLineNumCbParams *lineNumCbParams);
+
+/* ========================================================================== */
+/* Function Declarations */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/* Static Function Definitions */
+/* ========================================================================== */
+
+static inline void Dss_dctrlPathInfoInit(Dss_DctrlPathInfo *pathInfo)
+{
+ uint32_t i;
+ if(NULL != pathInfo)
+ {
+ pathInfo->numEdges = 0U;
+ for(i=0U; i<DSS_DCTRL_MAX_EDGES; i++)
+ {
+ pathInfo->edgeInfo[i].startNode = 0U;
+ pathInfo->edgeInfo[i].endNode = 0U;
+ }
+ }
+}
+
+static inline void Dss_DctrlSyncOpCfgInit(Dss_DctrlSyncOpCfg *syncOpCfg)
+{
+ uint32_t i;
+
+ if(NULL != syncOpCfg)
+ {
+ syncOpCfg->enabled = FALSE;
+ syncOpCfg->isPrimary = TRUE;
+ for(i = 0; i < CSL_DSS_VP_ID_MAX; i++)
+ {
+ syncOpCfg->syncVpIds[i] = CSL_DSS_VP_ID_1;
+ }
+ syncOpCfg->numSyncVpIds = 0;
+ }
+}
+
+static inline void Dss_dctrlVpParamsInit(Dss_DctrlVpParams *vpParams)
+{
+ if(NULL != vpParams)
+ {
+ vpParams->vpId = CSL_DSS_VP_ID_1;
+ CSL_dssVpLcdOpTimingCfgInit(&(vpParams->lcdOpTimingCfg));
+ CSL_dssVpLcdSignalPolarityCfgInit(&(vpParams->lcdPolarityCfg));
+ CSL_dssVpLcdTdmCfgInit(&(vpParams->lcdTdmCfg));
+ Dss_DctrlSyncOpCfgInit(&(vpParams->syncOpCfg));
+ }
+}
+
+static inline void Dss_dctrlOverlayParamsInit(
+ Dss_DctrlOverlayParams *overlayParams)
+{
+ if(NULL != overlayParams)
+ {
+ overlayParams->overlayId = CSL_DSS_OVERLAY_ID_1;
+ overlayParams->colorbarEnable = FALSE;
+ CSL_dssOverlayCfgInit(&(overlayParams->overlayCfg));
+ }
+}
+
+static inline void Dss_dctrlOverlayLayerParamsInit(
+ Dss_DctrlOverlayLayerParams *layerParams)
+{
+ uint32_t i;
+ if(NULL != layerParams)
+ {
+ layerParams->overlayId = CSL_DSS_OVERLAY_ID_1;
+ for(i=0U; i<CSL_DSS_VID_PIPE_ID_MAX; i++)
+ {
+ layerParams->pipeLayerNum[i] = CSL_DSS_OVERLAY_LAYER_INVALID;
+ }
+ }
+}
+
+static inline void Dss_dctrlAdvVpParamsInit(Dss_DctrlAdvVpParams *advVpParams)
+{
+ if(NULL != advVpParams)
+ {
+ advVpParams->vpId = CSL_DSS_VP_ID_1;
+ CSL_dssVpLcdAdvSignalCfgInit(&(advVpParams->lcdAdvSignalCfg));
+ }
+}
+
+static inline void Dss_dctrlLcdBlankTimingParamsInit(
+ Dss_DctrlLcdBlankTimingParams *lcdBlankTimingParams)
+{
+ if(NULL != lcdBlankTimingParams)
+ {
+ lcdBlankTimingParams->vpId = CSL_DSS_VP_ID_1;
+ CSL_dssVpLcdBlankTimingCfgInit(&(lcdBlankTimingParams->lcdBlankTimingCfg));
+ }
+}
+
+static inline void Dss_dctrlRegionSafetyChkCfgInit(
+ Dss_DctrlRegionSafetyChkCfg *regionSafetyChkCfg)
+{
+ if(NULL != regionSafetyChkCfg)
+ {
+ regionSafetyChkCfg->regionId = CSL_DSS_VP_SAFETY_REGION_0;
+ regionSafetyChkCfg->referenceSign = 0U;
+ CSL_dssSafetyChkCfgInit(&(regionSafetyChkCfg->safetyChkCfg));
+ }
+}
+
+static inline void Dss_dctrlVpSafetyCbDataInit(
+ Dss_DctrlVpSafetyCbData *safetyCbData)
+{
+ if(NULL != safetyCbData)
+ {
+ safetyCbData->regionId = CSL_DSS_VP_SAFETY_REGION_0;
+ safetyCbData->capturedSign = 0U;
+ }
+}
+
+static inline void Dss_dctrlVpSafetyChkParamsInit(
+ Dss_DctrlVpSafetyChkParams *vpSafetyChkParams)
+{
+ if(NULL != vpSafetyChkParams)
+ {
+ vpSafetyChkParams->vpId = CSL_DSS_VP_ID_1;
+ vpSafetyChkParams->safetySignSeedVal = 0U;
+ Dss_dctrlRegionSafetyChkCfgInit(&(vpSafetyChkParams->regionSafetyChkCfg));
+ vpSafetyChkParams->safetyErrCbFxn = NULL;
+ Dss_dctrlVpSafetyCbDataInit(&(vpSafetyChkParams->safetyCbData));
+ vpSafetyChkParams->appData = NULL;
+ }
+}
+
+static inline void Dss_dctrlVpErrorStatsInit(Dss_DctrlVpErrorStats *vpErrorStats)
+{
+ uint32_t i;
+ if(NULL != vpErrorStats)
+ {
+ vpErrorStats->vpId = CSL_DSS_VP_ID_1;
+ vpErrorStats->syncLost = 0U;
+ for(i=0U; i<CSL_DSS_VP_SAFETY_REGION_MAX; i++)
+ {
+ vpErrorStats->safetyViolation[i] = 0U;
+ }
+ vpErrorStats->securityViolation = 0U;
+ }
+}
+
+static inline void Dss_dctrlGlobalDssParamsInit(
+ Dss_DctrlGlobalDssParams *globalDssParams)
+{
+ if(NULL != globalDssParams)
+ {
+ CSL_dssGlobalMFlagCfgInit(&(globalDssParams->globalMflagCfg));
+ CSL_dssCbaCfgInit(&(globalDssParams->cbaCfg));
+ }
+}
+
+static inline void Dss_dctrlSyncLostCbParamsInit(
+ Dss_DctrlSyncLostCbParams *syncLostCbParams)
+{
+ if(NULL != syncLostCbParams)
+ {
+ syncLostCbParams->vpId = CSL_DSS_VP_ID_1;
+ syncLostCbParams->syncLostCbFxn = NULL;
+ syncLostCbParams->appData = NULL;
+ }
+}
+
+static inline void Dss_dctrlLineNumCbParamsInit(
+ Dss_DctrlLineNumCbParams *lineNumCbParams)
+{
+ if(NULL != lineNumCbParams)
+ {
+ lineNumCbParams->vpId = CSL_DSS_VP_ID_1;
+ lineNumCbParams->lineNumCbFxn = NULL;
+ lineNumCbParams->appData = NULL;
+ }
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #ifndef DSS_DCTRL_H_ */
+
+/* @} */
diff --git a/packages/ti/drv/dss/include/dss_disp.h b/packages/ti/drv/dss/include/dss_disp.h
--- /dev/null
@@ -0,0 +1,808 @@
+/*
+ * Copyright (c) Texas Instruments Incorporated 2018
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * \ingroup DRV_DSS_MODULE
+ * \defgroup DRV_DSS_DISP_MODULE Display Pipe Driver
+ * This is DSS Display driver documentation
+ *
+ * @{
+ */
+
+/**
+ * \file dss_disp.h
+ *
+ * \brief DSS Display Driver interface file.
+ */
+
+#ifndef DSS_DISP_H_
+#define DSS_DISP_H_
+
+/* ========================================================================== */
+/* Include Files */
+/* ========================================================================== */
+
+/* None */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* ========================================================================== */
+/* Macros & Typedefs */
+/* ========================================================================== */
+
+/**
+ * \brief Display driver buffer program callback function prototype.
+ *
+ * This callback is called by the driver when it is about to program the
+ * already queued buffer to the hardware. The driver returns the current
+ * frame pointer and the application can use this information to check if
+ * the buffer to be programmed is too old to display. If it decides so,
+ * the application can give a new frame buffer (blank frame) in the return
+ * parameter. Then the driver swaps this FVID2 frame pointer in its internal
+ * queue and program the new frame provided.
+ *
+ * Note: Once the frame is swapped with the driver, the driver will not have
+ * any reference to the old frame. The ownership of the old frame is
+ * transferred to application and will not be returned in the driver dequeue
+ * operation.
+ *
+ * User should assume that callbacks happen in ISR context and hence should
+ * apply rules relevant to ISR context when implementing callback functions,
+ * i.e. blocking APIs should not be called from callback. Users should also
+ * assume that interrupts are enabled when in callback context, i.e. other
+ * interrupt / callbacks can occur when a callback is under execution.
+ * User callback implementation should not be very long, since callback
+ * execution may block other drivers from executing. Typically it is
+ * recommended to set a semaphore or flag when callback happens and do the
+ * more involved callback handling in task context.
+ *
+ * \param handle [OUT] FVID2 handle for which the callback has occurred.
+ * \param curFrm [OUT] Current FVID2 frame about to be programmed.
+ * \param isFrmRepeat [OUT] Flag to indicate whether the current frame is
+ * already programmed in the hardware.
+ * \param frmRepeatCnt [OUT] This variable indicates the frame repeat
+ * count reflecting the hardware queue depth.
+ * In case of DSS, we have actual register and shadow
+ * register. Hence this value could be 1 or 2
+ * for most of the cases. 1 means normal operating
+ * mode without frame repeat. 2 means both the
+ * shadow and current register have the same buffer
+ * i.e. the frame is getting repeated.
+ * There is a special case when this value is 0.
+ * This means the driver is trying to program the
+ * register in low latency mode in task context.
+ * But the success of the buffer getting accepted
+ * depends on when the queue is called with respect
+ * to VSYNC. If the Queue call is very near the VSYNC
+ * say 10 lines before VSYNC, the buffer programming
+ * will not be accepted. And the application should
+ * assume that the buffer will gets programmed in
+ * the next VSYNC only.
+ *
+ * \return The application can return the new FVID2 frame to be used for
+ * programming the hardware. If the application returns NULL no action is
+ * taken and the driver will go ahead and program the current frame to
+ * hardware.
+ */
+typedef Fvid2_Frame *(*Dss_DispBufPrgmCbFxn)(Fvid2_Handle handle,
+ Fvid2_Frame *curFrm,
+ uint32_t isFrmRepeat,
+ uint32_t frmRepeatCnt);
+
+/**
+ * \brief Display driver video pipe program callback function prototype.
+ *
+ * This callback is called by the driver after it has programmed the already
+ * queued buffer to the hardware. The application can use this callback to
+ * simulate a VSYNC. The driver returns the programmed frame pointer to the
+ * application.
+ *
+ * User should assume that callbacks happen in ISR context and hence should
+ * apply rules relevant to ISR context when implementing callback functions,
+ * i.e. blocking APIs should not be called from callback. User callback
+ * implementation should not be very long, since callback execution may block
+ * other drivers from executing. Typically it is recommended to set a semaphore
+ * or flag when callback happens and do the more involved callback handling in
+ * task context.
+ *
+ * \param progFrm [OUT] Current FVID2 frame that has been programmed.
+ * \param appData [OUT] Application's private data.
+ *
+ * \return Status
+ */
+typedef int32_t (*Dss_DispPipePrgmCbFxn)(Fvid2_Frame *progFrm,
+ void *appData);
+
+/**
+ * \brief Video pipe underflow callback function prototype.
+ *
+ * \param appData [OUT] Application's private data.
+ *
+ * \return None.
+ */
+typedef void (*Dss_DispUnderFlowCbFxn)(void *appData);
+
+/**
+ * \brief Video Pipe safety error callback function prototype.
+ *
+ * \param capturedSign [OUT] Captured signature
+ * \param appData [OUT] Application's private data.
+ *
+ * \return None.
+ */
+typedef void (*Dss_DispSafetyErrCbFxn)(uint32_t capturedSign,
+ void *appData);
+
+/**
+ * \brief DSS video buffer alignment. All application buffer address and
+ * line pitch should be aligned to this byte boundary.
+ */
+#define DSS_BUFFER_ALIGNMENT (16U)
+
+/*
+ * Display driver IOCTLs.
+ */
+
+/**
+ * \ingroup DRV_DSS_DISP_MODULE
+ * \defgroup DRV_DSS_DISP_IOCTL Display IOCTLs
+ * @{
+ *
+ * These are display FVID2 APIs that can be called by the application.
+ */
+
+/**
+ * \brief Command to set DSS display parameters.
+ *
+ * This IOCTL is used to program the DSS display parameters. Refer to structure
+ * #Dss_DispParams for details on DSS parameters.
+ *
+ * \param cmdArgs [IN] Pointer of type #Dss_DispParams
+ * \param cmdArgsStatus [OUT] NULL
+ *
+ * \return FVID2_SOK if successful, else suitable error code
+ */
+#define IOCTL_DSS_DISP_SET_DSS_PARAMS (DSS_DISP_IOCTL_BASE + 0x0001U)
+
+/**
+ * \brief Command to set MFLAG parameters for video pipe.
+ *
+ * This IOCTL can be used to set the MFLAG parameters for the given video pipe.
+ *
+ * \param cmdArgs [IN] Pointer of type #Dss_DispPipeMflagParams
+ * \param cmdArgsStatus [OUT] NULL
+ *
+ * \return FVID2_SOK if successful, else suitable error code
+ *
+ */
+#define IOCTL_DSS_DISP_SET_PIPE_MFLAG_PARAMS (DSS_DISP_IOCTL_BASE + 0x0002U)
+
+/**
+ * \brief Command to get the display status.
+ *
+ * This IOCTL can be used to get the display status like number of frames
+ * displayed, repeated, queued. dequeued, etc.
+ * Note: These counters will be reset either at the time of driver create or
+ * while starting the display operation. See respective counter comments for
+ * details.
+ *
+ * \param cmdArgs [IN] Pointer of type #Dss_DispCurrentStatus
+ * \param cmdArgsStatus [OUT] NULL
+ *
+ * \return FVID2_SOK if successful, else suitable error code
+ *
+ */
+#define IOCTL_DSS_DISP_GET_CURRENT_STATUS (DSS_DISP_IOCTL_BASE + 0x0003U)
+
+/**
+ * \brief Command to program Safety Check configuration at Video Pipe Output.
+ *
+ * This IOCTL is used to program the safety check configuration parameters.
+ *
+ * \param cmdArgs [IN] Pointer of type #Dss_DispPipeSafetyChkParams
+ * \param cmdArgsStatus [OUT] NULL
+ *
+ * \return FVID2_SOK if successful, else suitable error code
+ */
+#define IOCTL_DSS_DISP_SET_PIPE_SAFETY_CHK_PARAMS \
+ (DSS_DISP_IOCTL_BASE + 0x0004U)
+
+/**
+ * \brief Command to program the CSC coefficients for Video Pipe.
+ * By default BT 601 coefficients are set.
+ *
+ * \param cmdArgs [IN] Pointer of type #CSL_DssCscCoeff
+ * \param cmdArgsStatus [OUT] NULL
+ *
+ * \return FVID2_SOK if successful, else suitable error code
+ */
+#define IOCTL_DSS_DISP_SET_PIPE_CSC_COEFF (DSS_DISP_IOCTL_BASE + 0x0005U)
+
+/**
+ * \brief Command to register buffer program callback function.
+ *
+ * This IOCTL can be used to register a callback when the actual buffer
+ * is getting programmed to the hardware. See #Dss_DispBufPrgmCbFxn for
+ * details. This IOCTL is per display driver instance and hence should be
+ * called separately for each display pipeline.
+ * Also this IOCTL should be called before starting the display.
+ * Note: bufPrgmCbFxn should be set to NULL in order to unregister
+ * the callback.
+ *
+ * \param cmdArgs [IN] Pointer of type #Dss_DispBufPrgmCbParams
+ * \param cmdArgsStatus [OUT] NULL
+ *
+ * \return FVID2_SOK if successful, else suitable error code
+ */
+#define IOCTL_DSS_DISP_REGISTER_BUF_PRGM_CB (DSS_DISP_IOCTL_BASE + 0x0006U)
+
+/**
+ * \brief Command to register video pipe program callback function.
+ *
+ * This IOCTL can be used to register a callback when the actual buffer
+ * has been programmed to the hardware. See #Dss_DispPipePrgmCbFxn for
+ * details. This IOCTL is per display driver instance and hence should be
+ * called separately for each display pipeline.
+ * Also this IOCTL should be called before starting the display.
+ * Note: pipePrgmCbFxn should be set to NULL in order to unregister
+ * the callback.
+ *
+ * \param cmdArgs [IN] Pointer of type #Dss_DispPipePrgmCbParams
+ * \param cmdArgsStatus [OUT] NULL
+ *
+ * \return FVID2_SOK if successful, else suitable error code
+ */
+#define IOCTL_DSS_DISP_REGISTER_PIPE_PRGM_CB (DSS_DISP_IOCTL_BASE + 0x0007U)
+
+/**
+ * \brief Command to register video pipe underflow callback function.
+ *
+ * This IOCTL can be used to register a callback when there is a underflow for
+ * a particular video pipe. See #Dss_DispUnderFlowCbFxn for details. This
+ * IOCTL is per display driver instance and hence should be called separately
+ * for each display pipeline.
+ * Also this IOCTL should be called before starting the display.
+ * Note: underFlowCbFxn should be set to NULL in order to unregister
+ * the callback.
+ *
+ * \param cmdArgs [IN] Pointer of type #Dss_DispUnderFlowCbParams
+ * \param cmdArgsStatus [OUT] NULL
+ *
+ * \return FVID2_SOK if successful, else suitable error code
+ */
+#define IOCTL_DSS_DISP_REGISTER_PIPE_UNDERFLOW_CB \
+ (DSS_DISP_IOCTL_BASE + 0x0008U)
+
+/* @} */
+
+/* ========================================================================== */
+/* Structure Declarations */
+/* ========================================================================== */
+
+/**
+ * \brief Structure containing display driver create arguments, used when
+ * calling Fvid2_create().
+ */
+typedef struct
+{
+ uint32_t periodicCbEnable;
+ /**< Periodic Callback Enable. Possible values are TRUE or FALSE.
+ * TRUE: User callback passed during FVID2 create is called periodically.
+ * For progressive display, this interval is equal to VSYNC interval.
+ * For interlaced display, this interval is equal to twice the VSYNC
+ * interval as frames (two fields) are queued to the driver
+ * FALSE: User callback passed during FVID2 create is called only
+ * if one or more frames (requests) are available in the driver output
+ * queue for the application to dequeue */
+ uint32_t progPipeVsyncEnable;
+ /**< Program Pipe at Vsync Enable. Possible values are TRUE or FALSE.
+ * TRUE: Pipe Registers will be updated only during VSYNC context. This
+ * essentially implies that start and stop will be dummy. The actual
+ * buffer programming will happen at next VSYNC and hence there
+ * will be one frame delay. In case of queue operation the frame will
+ * always be pushed to request queue. This means buffer will not be
+ * updated immediately even when driver is repeating frames in safe to
+ * push context.
+ * FALSE: This is the default behavior. Start and stop will be agnostic
+ * to Vsync and happen immediately. In case of queue operation, driver
+ * will display the new frame if there was frame repeat and queue is done
+ * during safe to push period.
+ */
+} Dss_DispCreateParams;
+
+/**
+ * \brief Structure containing create status for the display driver. This
+ * should be passed as a status argument while creating the driver.
+ */
+typedef struct
+{
+ int32_t retVal;
+ /**< Return status of create call */
+ uint32_t standard;
+ /**< Video Port standard like 1080p, 720p, etc. to which the video pipe
+ * is connected. For valid values see #Fvid2_Standard */
+ uint32_t dispWidth;
+ /**< Width of the display at the Video Port in pixels */
+ uint32_t dispHeight;
+ /**< Height of the display at the Video Port in lines */
+ uint32_t minNumPrimeBuf;
+ /**< Minimum number of buffers to prime before starting display
+ * operation */
+} Dss_DispCreateStatus;
+
+/**
+ * \brief Structure containing video pipeline crop configuration.
+ */
+typedef struct
+{
+ uint32_t cropEnable;
+ /**< Enable/disable the crop */
+ Fvid2_EdgeCropConfig cropCfg;
+ /**< Crop configuration described using FVID2 type #Fvid2_EdgeCropConfig
+ *
+ * <b>cropTop</b>:<br>
+ * Crop Top in lines, valid values are 0-31 <br>
+ *
+ * <b>cropBottom</b>:<br>
+ * Crop Bottom in lines, valid values are 0-31 <br>
+ *
+ * <b>cropLeft</b>:<br>
+ * Crop Left in pixels, valid values are 0-31 <br>
+ *
+ * <b>cropRight</b>:<br>
+ * Crop Right in pixels, valid values are 0-31 <br> */
+} Dss_DispPipeCropParams;
+
+/**
+ * \brief Structure containing DSS parameters.
+ * This structure is used as an argument to IOCTL_DSS_DISP_SET_DSS_PARAMS.
+ */
+typedef struct
+{
+ CSL_DssVidPipeCfg pipeCfg;
+ /**< Video pipeline configuration */
+ CSL_DssVidPipeDmaCfg dmaCfg;
+ /**< Video pipeline DMA configuration */
+ CSL_DssVidPipeAlphaCfg alphaCfg;
+ /**< Video pipeline alpha configuration */
+ CSL_DssVidPipeVC1Cfg vc1Cfg;
+ /**< Video pipeline VC1 configuration */
+ Dss_DispPipeCropParams cropParams;
+ /**< Video pipeline Crop parameters, used only for J7 platform */
+ Fvid2_PosConfig layerPos;
+ /**< Position of the video buffer described using #Fvid2_PosConfig
+ *
+ * <b>startX</b>:<br>
+ * X position of the video buffer
+ * The first pixel on the left of the screen has the X-position 0 <br>
+ *
+ * <b>startY</b>:<br>
+ * Y position of the video buffer
+ * The line at the top has the Y-position 0 <br>
+ */
+} Dss_DispParams;
+
+/**
+ * \brief Structure containing Video Pipe Mflag Information.
+ * This structure is used as an argument to
+ * IOCTL_DSS_DISP_SET_PIPE_MFLAG_PARAMS.
+ */
+typedef struct
+{
+ CSL_DssVidPipeMFlagCfg mflagCfg;
+ /**< Video pipeline mflag configuration. See #CSL_DssVidPipeMFlagCfg for
+ * details */
+} Dss_DispPipeMflagParams;
+
+/**
+ * \brief Structure containing current status of the display driver.
+ * This structure is used as an argument to IOCTL_DSS_DISP_GET_CURRENT_STATUS.
+ */
+typedef struct
+{
+ uint32_t queueCount;
+ /**< Counter to keep track of how many requests are queued to the driver.
+ * Note: This counter will be reset at the time of driver create */
+ uint32_t dequeueCount;
+ /**< Counter to keep track of how many requests are dequeued from the
+ * driver.
+ * Note: This counter will be reset at the time of driver create */
+ uint32_t dispFrmCount;
+ /**< Counter to keep track of how many frames are displayed.
+ * For interlaced display, this is half of the actual field display.
+ * Note: This counter will be reset at the time of display start */
+ uint32_t repeatFrmCount;
+ /**< Counter to keep track of how many frames are repeated when the
+ * application fails to queue buffer at the display rate.
+ * Note: This counter will be reset at the time of display start */
+ uint32_t underflowCount;
+ /**< Counter to keep track of number of underflows
+ * Note: This counter will be reset at the time of driver create */
+ uint32_t safetyViolationCount;
+ /**< Counter to keep track of number of safety violations
+ * Note: This counter will be reset at the time of driver create */
+} Dss_DispCurrentStatus;
+
+/**
+ * \brief Structure containing Safety Check configuration of Video Port.
+ * This structure is used as an argument to
+ * IOCTL_DSS_DISP_SET_PIPE_SAFETY_CHK_PARAMS.
+ */
+typedef struct
+{
+ uint32_t safetySignSeedVal;
+ /**< Safety Signature Seed Value */
+ uint32_t referenceSign;
+ /**< Reference Safety Signature for Data Correctness Check */
+ CSL_DssSafetyChkCfg safetyChkCfg;
+ /**< Safety Check Configuration. See \ref CSL_DssSafetyChkCfg for details */
+ Dss_DispSafetyErrCbFxn safetyErrCbFxn;
+ /**< Safety Error callback function */
+ uint32_t capturedSign;
+ /**< Captured Signature returned to the application */
+ void *appData;
+ /**< Private data of application */
+} Dss_DispPipeSafetyChkParams;
+
+/**
+ * \brief Structure containing display buffer program callback parameters.
+ * This structure is used as an argument to
+ * IOCTL_DSS_DISP_REGISTER_BUF_PRGM_CB.
+ */
+typedef struct
+{
+ Dss_DispBufPrgmCbFxn bufPrgmCbFxn;
+ /**< Application callback function to be called just before programming
+ * the hardware. A value of NULL will un-register the callback. */
+} Dss_DispBufPrgmCbParams;
+
+/**
+ * \brief Structure containing video pipe program callback parameters.
+ * This structure is used as an argument to
+ * IOCTL_DSS_DISP_REGISTER_PIPE_PRGM_CB.
+ */
+typedef struct
+{
+ Dss_DispPipePrgmCbFxn pipePrgmCbFxn;
+ /**< Application callback function to be called just after programming
+ * the hardware. A value of NULL will un-register the callback. */
+ void *appData;
+ /**< Private data of application */
+} Dss_DispPipePrgmCbParams;
+
+/**
+ * \brief Structure containing pipe under flow callback parameters.
+ * This structure is used as an argument to
+ * IOCTL_DSS_DISP_REGISTER_PIPE_UNDERFLOW_CB.
+ */
+typedef struct
+{
+ Dss_DispUnderFlowCbFxn underFlowCbFxn;
+ /**< Sync lost callback function */
+ void *appData;
+ /**< Private data of application */
+} Dss_DispUnderFlowCbParams;
+
+/**
+ * \brief Structure containing run time scaler configuration.
+ */
+typedef struct
+{
+ uint32_t pixelInc;
+ /**< Pixel increment in terms of pixels. */
+} Dss_ScRtParams;
+
+/**
+ * \brief Structure containing run time configuration per frame.
+ */
+typedef struct
+{
+ uint32_t width;
+ /**< Width of the video frame or field in pixels. */
+ uint32_t height;
+ /**< Height of the video frame or field in lines. */
+ uint32_t pitch[FVID2_MAX_PLANES];
+ /**< Pitch in bytes for each of the sub-buffers. This represents the
+ * difference between two consecutive line addresses in bytes.
+ * This is irrespective of whether the video is interlaced or
+ * progressive and whether the fields are merged or separated for
+ * interlaced video. */
+ uint32_t dataFormat;
+ /**< Frame data Format. For valid values see #Fvid2_DataFormat. */
+} Dss_FrameRtParams;
+
+/**
+ * \brief Structure containing run time configuration of the display driver.
+ * This needs to be passed along with frame list to update any supported
+ * run time parameters.
+ */
+typedef struct
+{
+ Fvid2_PosConfig *posCfg;
+ /**< Position Configuration used to position the Frame in the Overlay.
+ * Refer to #Fvid2_PosConfig for details.
+ * Note: Pass NULL if no change is required */
+ Dss_FrameRtParams *inFrmParams;
+ /**< RT Params for input frame. This parameter is used to change the
+ * frame width and height at runtime. Note that this is used only when
+ * the buffer dimension is smaller than the LCD size. When changing the
+ * size, the application should ensure that the startX/startY +
+ * frame size doesn't exceed the display resolution.
+ * Refer to #Dss_FrameRtParams for details.
+ * Note: Pass NULL if no change is required */
+ Dss_FrameRtParams *outFrmParams;
+ /**< RT Params for output frame i.e. output of video pipeline.
+ * Only Width and height is valid in this structure.
+ * Refer to #Dss_FrameRtParams for details.
+ * Note: Pass NULL if no change is required */
+ Dss_ScRtParams *scParams;
+ /**< RT Params for scaler.
+ * Refer to #Dss_ScRtParams for details.
+ * Note: Pass NULL if no change is required */
+} Dss_DispRtParams;
+
+/* ========================================================================== */
+/* Internal/Private Function Declarations */
+/* ========================================================================== */
+
+/**
+ * \brief Dss_DispCreateParams structure init function.
+ *
+ * \param createParams [IN]Pointer to #Dss_DispCreateParams structure.
+ *
+ * \return None
+ */
+static inline void Dss_dispCreateParamsInit(Dss_DispCreateParams *createParams);
+
+/**
+ * \brief Dss_DispParams structure init function.
+ *
+ * \param dssParams [IN]Pointer to #Dss_DispParams structure.
+ *
+ * \return None
+ */
+static inline void Dss_dispParamsInit(Dss_DispParams *dssParams);
+
+/**
+ * \brief Dss_DispPipeMflagParams structure init function.
+ *
+ * \param pipeMflagParams [IN]Pointer to #Dss_DispPipeMflagParams structure.
+ *
+ * \return None
+ */
+static inline void Dss_dispPipeMflagParamsInit(
+ Dss_DispPipeMflagParams *pipeMflagParams);
+
+/**
+ * \brief Dss_DispPipeSafetyChkParams structure init function.
+ *
+ * \param pipeSafetyChkParams [IN]Pointer to #Dss_DispPipeSafetyChkParams
+ * structure.
+ *
+ * \return None
+ */
+static inline void Dss_dispPipeSafetyChkParamsInit(
+ Dss_DispPipeSafetyChkParams *pipeSafetyChkParams);
+
+/**
+ * \brief Dss_DispBufPrgmCbParams structure init function.
+ *
+ * \param bufPrgmCbParams [IN]Pointer to #Dss_DispBufPrgmCbParams structure.
+ *
+ * \return None
+ */
+static inline void Dss_dispBufPrgmCbParamsInit(
+ Dss_DispBufPrgmCbParams *bufPrgmCbParams);
+
+/**
+ * \brief Dss_DispPipePrgmCbParams structure init function.
+ *
+ * \param pipePrgmCbParams [IN]Pointer to #Dss_DispPipePrgmCbParams structure.
+ *
+ * \return None
+ */
+static inline void Dss_dispPipePrgmCbParamsInit(
+ Dss_DispPipePrgmCbParams *pipePrgmCbParams);
+
+/**
+ * \brief Dss_DispUnderFlowCbParams structure init function.
+ *
+ * \param underFlowCbParams [IN]Pointer to #Dss_DispUnderFlowCbParams structure.
+ *
+ * \return None
+ */
+static inline void Dss_dispUnderFlowCbParamsInit(
+ Dss_DispUnderFlowCbParams *underFlowCbParams);
+
+/**
+ * \brief Dss_ScRtParams structure init function.
+ *
+ * \param scRtParams [IN]Pointer to #Dss_ScRtParams structure.
+ *
+ * \return None
+ */
+static inline void Dss_scRtParamsInit(Dss_ScRtParams *scRtParams);
+
+/**
+ * \brief Dss_FrameRtParams structure init function.
+ *
+ * \param frameRtParams [IN]Pointer to #Dss_FrameRtParams structure.
+ *
+ * \return None
+ */
+static inline void Dss_frameRtParamsInit(Dss_FrameRtParams *frameRtParams);
+
+/**
+ * \brief Dss_DispRtParams structure init function.
+ *
+ * \param rtParams [IN]Pointer to #Dss_DispRtParams structure.
+ *
+ * \return None
+ */
+static inline void Dss_dispRtParamsInit(Dss_DispRtParams *rtParams);
+
+/* ========================================================================== */
+/* Function Declarations */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/* Static Function Definitions */
+/* ========================================================================== */
+
+static inline void Dss_dispCreateParamsInit(Dss_DispCreateParams *createParams)
+{
+ if(NULL != createParams)
+ {
+ createParams->periodicCbEnable = TRUE;
+ createParams->progPipeVsyncEnable = FALSE;
+ }
+}
+
+static inline void Dss_dispPipeCropParamsInit(
+ Dss_DispPipeCropParams *cropParams)
+{
+ if(NULL != cropParams)
+ {
+ cropParams->cropEnable = FALSE;
+ Fvid2EdgeCropConfig_init(&(cropParams->cropCfg));
+ }
+}
+
+static inline void Dss_dispParamsInit(Dss_DispParams *dssParams)
+{
+ if(NULL != dssParams)
+ {
+ CSL_dssVidPipeCfgInit(&(dssParams->pipeCfg));
+ CSL_dssVidPipeDmaCfgInit(&(dssParams->dmaCfg));
+ CSL_dssVidPipeAlphaCfgInit(&(dssParams->alphaCfg));
+ CSL_dssVidPipeVC1CfgInit(&(dssParams->vc1Cfg));
+ Dss_dispPipeCropParamsInit(&(dssParams->cropParams));
+ Fvid2PosConfig_init(&(dssParams->layerPos));
+ }
+}
+
+static inline void Dss_dispPipeMflagParamsInit(
+ Dss_DispPipeMflagParams *pipeMflagParams)
+{
+ if(NULL != pipeMflagParams)
+ {
+ CSL_dssVidPipeMFlagCfgInit(&(pipeMflagParams->mflagCfg));
+ }
+}
+
+static inline void Dss_dispPipeSafetyChkParamsInit(
+ Dss_DispPipeSafetyChkParams *pipeSafetyChkParams)
+{
+ if(NULL != pipeSafetyChkParams)
+ {
+ pipeSafetyChkParams->safetySignSeedVal = 0U;
+ pipeSafetyChkParams->referenceSign = 0U;
+ CSL_dssSafetyChkCfgInit(&(pipeSafetyChkParams->safetyChkCfg));
+ pipeSafetyChkParams->safetyErrCbFxn = NULL;
+ pipeSafetyChkParams->capturedSign = 0U;
+ pipeSafetyChkParams->appData = NULL;
+ }
+}
+
+static inline void Dss_dispBufPrgmCbParamsInit(
+ Dss_DispBufPrgmCbParams *bufPrgmCbParams)
+{
+ if(NULL != bufPrgmCbParams)
+ {
+ bufPrgmCbParams->bufPrgmCbFxn = NULL;
+ }
+}
+
+static inline void Dss_dispPipePrgmCbParamsInit(
+ Dss_DispPipePrgmCbParams *pipePrgmCbParams)
+{
+ if(NULL != pipePrgmCbParams)
+ {
+ pipePrgmCbParams->pipePrgmCbFxn = NULL;
+ }
+}
+
+static inline void Dss_dispUnderFlowCbParamsInit(
+ Dss_DispUnderFlowCbParams *underFlowCbParams)
+{
+ if(NULL != underFlowCbParams)
+ {
+ underFlowCbParams->underFlowCbFxn = NULL;
+ }
+}
+
+static inline void Dss_scRtParamsInit(Dss_ScRtParams *scRtParams)
+{
+ if(NULL != scRtParams)
+ {
+ scRtParams->pixelInc = 1U;
+ }
+}
+
+static inline void Dss_frameRtParamsInit(Dss_FrameRtParams *frameRtParams)
+{
+ uint32_t i;
+ if(NULL != frameRtParams)
+ {
+ frameRtParams->width = 1920U;
+ frameRtParams->height = 1080U;
+ frameRtParams->dataFormat = FVID2_DF_YUV422I_YUYV;
+ for(i=0U; i<FVID2_MAX_PLANES; i++)
+ {
+ frameRtParams->pitch[i] = 1920U*3U;
+ }
+ }
+}
+
+static inline void Dss_dispRtParamsInit(Dss_DispRtParams *rtParams)
+{
+ if(NULL != rtParams)
+ {
+ rtParams->posCfg = NULL;
+ rtParams->inFrmParams = NULL;
+ rtParams->outFrmParams = NULL;
+ rtParams->scParams = NULL;
+ }
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #ifndef DSS_DISP_H_ */
+
+/* @} */
diff --git a/packages/ti/drv/dss/makefile b/packages/ti/drv/dss/makefile
--- /dev/null
@@ -0,0 +1,46 @@
+#
+# Copyright (c) 2018, Texas Instruments Incorporated
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# * Redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer.
+#
+# * Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution.
+#
+# * Neither the name of Texas Instruments Incorporated nor the names of
+# its contributors may be used to endorse or promote products derived
+# from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+# OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+# EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+
+ifeq ($(RULES_MAKE), )
+include $(PDK_INSTALL_PATH)/ti/build/Rules.make
+else
+include $(RULES_MAKE)
+endif
+
+COMP = drvdss
+
+lib_$(COMP)_BUILD_DEPENDENCY = soc
+
+$(COMP)_DOXYGEN_SUPPORT = yes
+
+include $(PDK_INSTALL_PATH)/ti/build/comp_top.mk
+
diff --git a/packages/ti/drv/dss/package.bld b/packages/ti/drv/dss/package.bld
--- /dev/null
@@ -0,0 +1,19 @@
+/******************************************************************************
+ * FILE PURPOSE: Build description for the DSS Package
+ ******************************************************************************
+ * FILE NAME: package.bld
+ *
+ * DESCRIPTION:
+ * This file contains the build specification and description for the DSS
+ *
+ *
+ * Copyright (C) 2018, Texas Instruments, Inc.
+ *****************************************************************************/
+
+/* Generate Settings.xdc */
+var tplt = xdc.loadTemplate("./Settings.xdc.xdt");
+tplt.genFile("./Settings.xdc",dssDriverReleaseVersion);
+
+/* Generate paver.h */
+var tplt = xdc.loadTemplate("./dssver.h.xdt");
+tplt.genFile("./dssver.h",dssDriverReleaseVersion);
\ No newline at end of file
diff --git a/packages/ti/drv/dss/package.xdc b/packages/ti/drv/dss/package.xdc
--- /dev/null
@@ -0,0 +1,13 @@
+/******************************************************************************
+ * FILE PURPOSE: Package specification file
+ ******************************************************************************
+ * FILE NAME: package.xdc
+ *
+ * DESCRIPTION:
+ * This file contains the package specification for the DSS Driver
+ *
+ * Copyright (C) 2019, Texas Instruments, Inc.
+ *****************************************************************************/
+package ti.drv.dss[1, 0, 0, 4] {
+ module Settings;
+}
diff --git a/packages/ti/drv/dss/package.xs b/packages/ti/drv/dss/package.xs
--- /dev/null
@@ -0,0 +1,121 @@
+/*
+ * ======== package.xs ========
+ *
+ */
+
+
+/*
+ * ======== Package.getLibs ========
+ * This function is called when a program's configuration files are
+ * being generated and it returns the name of a library appropriate
+ * for the program's configuration.
+ */
+
+function getLibs(prog)
+{
+ var suffix = prog.build.target.suffix;
+ var socType = this.Settings.socType;
+ var boardType = this.Settings.boardType;
+ var socTypes = [
+ 'am65xx',
+ ];
+ var boardTypes = [
+ 'am65xx_sim',
+ 'am65xx_evm'
+ ];
+ var libNames = [
+ 'dss'
+ ];
+
+ /* Read LIBDIR variable */
+ var lib = java.lang.System.getenv("LIBDIR");
+
+ /* If NULL, default to "lib" folder */
+ if (lib == null)
+ {
+ lib = "./lib";
+ } else {
+ print ("\tSystem environment LIBDIR variable defined : " + lib);
+ }
+
+ /* Get the Board */
+ for each (var board in boardTypes)
+ {
+ if (boardType.equals(board))
+ {
+ lib = lib + "/" + board;
+ name = this.$name + ".a" + suffix;
+ break;
+ }
+ }
+
+ /* Get target folder, if applicable */
+ if (java.lang.String(suffix).contains('mcu1_0'))
+ lib = lib + "/mcu1_0";
+ else if (java.lang.String(suffix).contains('mcu2_0'))
+ lib = lib + "/mcu2_0";
+ else if (java.lang.String(suffix).contains('mpu1_1'))
+ lib = lib + "/mpu1_1";
+ else if (java.lang.String(suffix).contains('mpu1_0'))
+ lib = lib + "/mpu1_0";
+ else if (java.lang.String(suffix).contains('a53'))
+ lib = lib + "/mpu1_0";
+ else if (java.lang.String(suffix).contains('r5f'))
+ lib = lib + "/mcu1_0";
+ else
+ throw new Error("\tUnknown target for: " + this.packageBase + lib);
+
+ var libProfiles = ["debug", "release"];
+ /* get the configured library profile */
+ for each(var profile in libProfiles)
+ {
+ if (this.Settings.libProfile.equals(profile))
+ {
+ lib = lib + "/" + profile;
+ break;
+ }
+ }
+
+ /* Update the lib names with the lib extension */
+ lib_dir = lib;
+ lib ="";
+ for each(var libName in libNames)
+ {
+ libName = libName + ".a" + suffix;
+ if ((java.io.File(this.packageBase + lib_dir + "/" + libName).exists()))
+ {
+ /* Get library name with path */
+ lib = lib + lib_dir +"/" + libName;
+ lib = lib + ";";
+ print ("\tLinking with library " + this.packageBase + lib_dir + "/" + libName );
+ }
+ else
+ {
+ /* Could not find any library, throw exception */
+ throw new Error("\tLibrary not found: " + this.packageBase + lib_dir + "/" + libName);
+ break;
+ }
+ }
+
+ /* Get library name with path */
+ return lib;
+}
+
+/*
+ * ======== package.init ========
+ */
+function init() {
+ xdc.loadPackage("ti.osal");
+ xdc.loadPackage("ti.csl");
+}
+
+
+/*
+ * ======== package.close ========
+ */
+function close()
+{
+ if (xdc.om.$name != 'cfg') {
+ return;
+ }
+}
diff --git a/packages/ti/drv/dss/soc/V0/dss_soc.c b/packages/ti/drv/dss/soc/V0/dss_soc.c
--- /dev/null
@@ -0,0 +1,555 @@
+/*
+ * Copyright (c) Texas Instruments Incorporated 2018
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * \file dss_soc.c
+ *
+ * \brief File containing the SOC related configuration functions for DSS.
+ *
+ */
+
+/* ========================================================================== */
+/* Include Files */
+/* ========================================================================== */
+
+#include <ti/drv/dss/dss.h>
+#include <dss_soc_priv.h>
+#include <ti/drv/dss/src/drv/common/dss_evtMgr.h>
+
+/* ========================================================================== */
+/* Macros & Typedefs */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/* Structure Declarations */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/* Function Declarations */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/* Global Variables */
+/* ========================================================================== */
+
+/** Module ids for display controller nodes. For nodes that are not part of DSS
+ * HW, module id is not defined
+ */
+static const Dss_DctrlNodeIdInfo gDss_DctrlNodeIdInfo[] = {
+ {DSS_DCTRL_NODE_VID1, CSL_DSS_VID_PIPE_ID_VID1, DSS_DCTRL_NODE_TYPE_PIPE},
+ {DSS_DCTRL_NODE_VIDL1, CSL_DSS_VID_PIPE_ID_VIDL1, DSS_DCTRL_NODE_TYPE_PIPE},
+ {DSS_DCTRL_NODE_OVERLAY1, CSL_DSS_OVERLAY_ID_1, DSS_DCTRL_NODE_TYPE_OVERLAY},
+ {DSS_DCTRL_NODE_OVERLAY2, CSL_DSS_OVERLAY_ID_2, DSS_DCTRL_NODE_TYPE_OVERLAY},
+ {DSS_DCTRL_NODE_VP1, CSL_DSS_VP_ID_1, DSS_DCTRL_NODE_TYPE_VP},
+ {DSS_DCTRL_NODE_VP2, CSL_DSS_VP_ID_2, DSS_DCTRL_NODE_TYPE_VP},
+ {DSS_DCTRL_NODE_OLDI, CSL_DSS_MODULE_INVALID, DSS_DCTRL_NODE_TYPE_OUTPUT}, /* Virtual Node */
+ {DSS_DCTRL_NODE_DPI1, CSL_DSS_MODULE_INVALID, DSS_DCTRL_NODE_TYPE_OUTPUT} /* Virtual Node */
+};
+
+static const Dss_CommRegInfo gDss_commRegInfo[] = {
+ {CSL_DSS_COMM_REG_ID_0, (void *)CSL_DSS0_COMMON_BASE},
+ {CSL_DSS_COMM_REG_ID_1, (void *)CSL_DSS0_COMMON1_BASE}
+};
+
+static const Dss_PipeRegInfo gDss_pipeRegInfo[] = {
+ {CSL_DSS_VID_PIPE_ID_VID1, (void *)CSL_DSS0_VID_BASE},
+ {CSL_DSS_VID_PIPE_ID_VIDL1, (void *)CSL_DSS0_VIDL1_BASE}
+};
+
+static const Dss_OverlayRegInfo gDss_overlayRegInfo[] = {
+ {CSL_DSS_OVERLAY_ID_1, (void *)CSL_DSS0_OVR1_BASE},
+ {CSL_DSS_OVERLAY_ID_2, (void *)CSL_DSS0_OVR2_BASE}
+};
+
+static const Dss_VpRegInfo gDss_vpRegInfo[] = {
+ {CSL_DSS_VP_ID_1, (void *)CSL_DSS0_VP1_BASE},
+ {CSL_DSS_VP_ID_2, (void *)CSL_DSS0_VP2_BASE}
+};
+
+static const Dss_OverlayConnInfo gDss_OverlayConnInfo[] = {
+ {CSL_DSS_OVERLAY_ID_1, CSL_DSS_VP_ID_1},
+ {CSL_DSS_OVERLAY_ID_2, CSL_DSS_VP_ID_2}
+};
+
+static const Dss_VpSafetyRegionIdInfo gDss_VpSafetyRegionIdInfo[] = {
+ {CSL_DSS_VP_SAFETY_REGION_0, DSS_VP_EVENT_SAFETY_VIOLATION_0},
+ {CSL_DSS_VP_SAFETY_REGION_1, DSS_VP_EVENT_SAFETY_VIOLATION_1},
+ {CSL_DSS_VP_SAFETY_REGION_2, DSS_VP_EVENT_SAFETY_VIOLATION_2},
+ {CSL_DSS_VP_SAFETY_REGION_3, DSS_VP_EVENT_SAFETY_VIOLATION_3}
+};
+
+static const Dss_EventGroupInfo gDss_EventGroupInfo[] = {
+ {DSS_EVENT_GROUP_VP1, CSL_DSS_VP_ID_1, DSS_EVENT_GROUP_TYPE_VP},
+ {DSS_EVENT_GROUP_VP2, CSL_DSS_VP_ID_2, DSS_EVENT_GROUP_TYPE_VP},
+ {DSS_EVENT_GROUP_VID1, CSL_DSS_VID_PIPE_ID_VID1, DSS_EVENT_GROUP_TYPE_PIPE},
+ {DSS_EVENT_GROUP_VIDL1, CSL_DSS_VID_PIPE_ID_VIDL1, DSS_EVENT_GROUP_TYPE_PIPE}
+};
+
+static const uint32_t gDss_PipeErrEvents[] = {
+ DSS_PIPE_EVENT_BUFF_UNDERFLOW
+};
+
+static const uint32_t gDss_VpFuncEvents[] = {
+ DSS_VP_EVENT_VSYNC,
+ DSS_VP_EVENT_LINE_NUM
+};
+
+static const uint32_t gDss_VpErrEvents[] = {
+ DSS_VP_EVENT_SYNC_LOST
+};
+
+/* Global containing SoC information. */
+static Dss_SocInfo gDss_SocInfo;
+
+/* ========================================================================== */
+/* Function Definitions */
+/* ========================================================================== */
+
+void Dss_fillSocInfo(Dss_RmInfo *rmInfo)
+{
+ uint32_t i = 0U;
+
+ for(i=CSL_DSS_COMM_REG_ID_0; i<CSL_DSS_COMM_REG_ID_MAX; i++)
+ {
+ if(TRUE == rmInfo->isCommRegAvailable[i])
+ {
+ gDss_SocInfo.commRegs[i] =
+ (CSL_dss_commRegs *)gDss_commRegInfo[i].commRegs;
+ }
+ }
+ for(i=CSL_DSS_VID_PIPE_ID_VID1; i<CSL_DSS_VID_PIPE_ID_MAX; i++)
+ {
+ if(TRUE == rmInfo->isPipeAvailable[i])
+ {
+ gDss_SocInfo.pipeRegs[i] =
+ (CSL_dss_pipeRegs *)gDss_pipeRegInfo[i].pipeRegs;
+ }
+ }
+ for(i=CSL_DSS_OVERLAY_ID_1; i<CSL_DSS_OVERLAY_ID_MAX; i++)
+ {
+ if(TRUE == rmInfo->isOverlayAvailable[i])
+ {
+ gDss_SocInfo.overlayRegs[i] =
+ (CSL_dss_overlayRegs *)gDss_overlayRegInfo[i].overlayRegs;
+ }
+ }
+ for(i=CSL_DSS_VP_ID_1; i<CSL_DSS_VP_ID_MAX; i++)
+ {
+ if(TRUE == rmInfo->isPortAvailable[i])
+ {
+ gDss_SocInfo.vpRegs[i] =
+ (CSL_dss_vpRegs *)gDss_vpRegInfo[i].vpRegs;
+ }
+ }
+}
+
+const Dss_SocInfo* Dss_getSocInfo(void)
+{
+ return (const Dss_SocInfo*)(&gDss_SocInfo);
+}
+
+int32_t Dss_convNodetoModule(uint32_t nodeId,
+ uint32_t *moduleId)
+{
+ int32_t retVal = FVID2_EFAIL;
+ uint32_t i;
+ *moduleId = CSL_DSS_MODULE_INVALID;
+
+ for(i=0U;
+ i<sizeof (gDss_DctrlNodeIdInfo) / sizeof (gDss_DctrlNodeIdInfo[0U]);
+ i++)
+ {
+ if(nodeId == gDss_DctrlNodeIdInfo[i].nodeId)
+ {
+ *moduleId = gDss_DctrlNodeIdInfo[i].moduleId;
+ retVal = FVID2_SOK;
+ break;
+ }
+ }
+
+ return (retVal);
+}
+
+int32_t Dss_convModuletoNode(uint32_t *nodeId,
+ uint32_t moduleId,
+ uint32_t nodeType)
+{
+ int32_t retVal = FVID2_EFAIL;
+ uint32_t i;
+ *nodeId = DSS_DCTRL_NODE_INVALID;
+
+ for(i=0U;
+ i<sizeof (gDss_DctrlNodeIdInfo) / sizeof (gDss_DctrlNodeIdInfo[0U]);
+ i++)
+ {
+ if((moduleId == gDss_DctrlNodeIdInfo[i].moduleId) &&
+ (nodeType == gDss_DctrlNodeIdInfo[i].nodeType))
+ {
+ *nodeId = gDss_DctrlNodeIdInfo[i].nodeId;
+ retVal = FVID2_SOK;
+ break;
+ }
+ }
+
+ return (retVal);
+}
+
+void Dss_convEventGrouptoModule(uint32_t eventGroup,
+ uint32_t *moduleId)
+{
+ uint32_t i;
+ *moduleId = CSL_DSS_MODULE_INVALID;
+
+ for(i=0U;
+ i<sizeof (gDss_EventGroupInfo) / sizeof (gDss_EventGroupInfo[0U]);
+ i++)
+ {
+ if(eventGroup == gDss_EventGroupInfo[i].eventGroup)
+ {
+ *moduleId = gDss_EventGroupInfo[i].moduleId;
+ break;
+ }
+ }
+}
+
+void Dss_convModuletoEventGroup(uint32_t *eventGroup,
+ uint32_t moduleId,
+ uint32_t eventGroupType)
+{
+ uint32_t i;
+ *eventGroup = DSS_EVENT_GROUP_INVALID;
+
+ for(i=0U;
+ i<sizeof (gDss_EventGroupInfo) / sizeof (gDss_EventGroupInfo[0U]);
+ i++)
+ {
+ if((moduleId == gDss_EventGroupInfo[i].moduleId) &&
+ (eventGroupType == gDss_EventGroupInfo[i].eventGroupType))
+ {
+ *eventGroup = gDss_EventGroupInfo[i].eventGroup;
+ break;
+ }
+ }
+}
+
+uint32_t Dss_getVpConnId(uint32_t overlayId)
+{
+ uint32_t vpId = CSL_DSS_MODULE_INVALID, i;
+
+ for(i=0U;
+ i<sizeof(gDss_OverlayConnInfo)/sizeof(gDss_OverlayConnInfo[0U]);
+ i++)
+ {
+ if(overlayId == gDss_OverlayConnInfo[i].overlayId)
+ {
+ vpId = gDss_OverlayConnInfo[i].vpId;
+ break;
+ }
+ }
+
+ return vpId;
+}
+
+int32_t Dss_enableL1Event(Dss_EvtMgrInfo *evtMgrInfo,
+ uint32_t dssCommonRegionId,
+ uint32_t eventGroup,
+ uint32_t event,
+ uint32_t eventCnt)
+{
+ int32_t retVal = FVID2_SOK;
+ uint32_t regVal;
+ CSL_dss_commRegs *commRegs;
+ const Dss_SocInfo *socInfo;
+
+ GT_assert(DssTrace, (NULL != evtMgrInfo));
+
+ /* Get common register space */
+ socInfo = Dss_getSocInfo();
+ commRegs = socInfo->commRegs[dssCommonRegionId];
+ GT_assert(DssTrace, (NULL != commRegs));
+
+ if(DSS_EVENT_GROUP_VP1 == eventGroup)
+ {
+ /* Clear the status of interrupt */
+ regVal = CSL_REG32_RD(&commRegs->VP_IRQSTATUS_0);
+ regVal |= eventGroup;
+ CSL_REG32_WR(&commRegs->VP_IRQSTATUS_0, regVal);
+
+ /* Enable the interrupts at the VP1 level */
+ regVal = CSL_REG32_RD(&commRegs->VP_IRQENABLE_0);
+ regVal |= event;
+ CSL_REG32_WR(&commRegs->VP_IRQENABLE_0, regVal);
+
+ /* Store the register address in evtMgrInfo instance */
+ evtMgrInfo->l1EnableReg[eventCnt] = &commRegs->VP_IRQENABLE_0;
+ evtMgrInfo->l1StatusReg[eventCnt] = &commRegs->VP_IRQSTATUS_0;
+ evtMgrInfo->l1Mask[eventCnt] = event;
+ evtMgrInfo->allEvents[eventCnt] = event;
+ }
+ else if(DSS_EVENT_GROUP_VP2 == eventGroup)
+ {
+ /* Clear the status of interrupt */
+ regVal = CSL_REG32_RD(&commRegs->VP_IRQSTATUS_1);
+ regVal |= eventGroup;
+ CSL_REG32_WR(&commRegs->VP_IRQSTATUS_1, regVal);
+
+ /* Enable the interrupts at the VP2 level */
+ regVal = CSL_REG32_RD(&commRegs->VP_IRQENABLE_1);
+ regVal |= event;
+ CSL_REG32_WR(&commRegs->VP_IRQENABLE_1, regVal);
+
+ /* Store the register address in evtMgrInfo instance */
+ evtMgrInfo->l1EnableReg[eventCnt] = &commRegs->VP_IRQENABLE_1;
+ evtMgrInfo->l1StatusReg[eventCnt] = &commRegs->VP_IRQSTATUS_1;
+ evtMgrInfo->l1Mask[eventCnt] = event;
+ evtMgrInfo->allEvents[eventCnt] = event;
+ }
+ else if(DSS_EVENT_GROUP_VID1 == eventGroup)
+ {
+ /* Clear the status of interrupt */
+ regVal = CSL_REG32_RD(&commRegs->VID_IRQSTATUS_0);
+ regVal |= eventGroup;
+ CSL_REG32_WR(&commRegs->VID_IRQSTATUS_0, regVal);
+
+ /* Enable the interrupts at the VID1 Pipe level */
+ regVal = CSL_REG32_RD(&commRegs->VID_IRQENABLE_0);
+ regVal |= event;
+ CSL_REG32_WR(&commRegs->VID_IRQENABLE_0, regVal);
+
+ /* Store the register address in evtMgrInfo instance */
+ evtMgrInfo->l1EnableReg[eventCnt] = &commRegs->VID_IRQENABLE_0;
+ evtMgrInfo->l1StatusReg[eventCnt] = &commRegs->VID_IRQSTATUS_0;
+ evtMgrInfo->l1Mask[eventCnt] = event;
+ evtMgrInfo->allEvents[eventCnt] = event;
+ }
+ else if(DSS_EVENT_GROUP_VIDL1 == eventGroup)
+ {
+ /* Clear the status of interrupt */
+ regVal = CSL_REG32_RD(&commRegs->VID_IRQSTATUS_1);
+ regVal |= eventGroup;
+ CSL_REG32_WR(&commRegs->VID_IRQSTATUS_1, regVal);
+
+ /* Enable the interrupts at the VIDL1 Pipe level */
+ regVal = CSL_REG32_RD(&commRegs->VID_IRQENABLE_1);
+ regVal |= event;
+ CSL_REG32_WR(&commRegs->VID_IRQENABLE_1, regVal);
+
+ /* Store the register address in evtMgrInfo instance */
+ evtMgrInfo->l1EnableReg[eventCnt] = &commRegs->VID_IRQENABLE_1;
+ evtMgrInfo->l1StatusReg[eventCnt] = &commRegs->VID_IRQSTATUS_1;
+ evtMgrInfo->l1Mask[eventCnt] = event;
+ evtMgrInfo->allEvents[eventCnt] = event;
+ }
+ else
+ {
+ GT_assert(DssTrace, FALSE);
+ retVal = FVID2_EBADARGS;
+ }
+
+ return retVal;
+}
+
+void Dss_getEnabledVpFuncEvents(uint32_t events[DSS_EVT_MGR_MAX_CLIENT_EVENTS],
+ uint32_t *numEvts)
+{
+ uint32_t i;
+ *numEvts = sizeof(gDss_VpFuncEvents)/sizeof(uint32_t);
+ for(i=0U; i<*numEvts; i++)
+ {
+ events[i] = gDss_VpFuncEvents[i];
+ }
+}
+
+void Dss_getEnabledVpErrEvents(uint32_t events[DSS_EVT_MGR_MAX_CLIENT_EVENTS],
+ uint32_t *numEvts)
+{
+ uint32_t i;
+ *numEvts = sizeof(gDss_VpErrEvents)/sizeof(uint32_t);
+ for(i=0U; i<*numEvts; i++)
+ {
+ events[i] = gDss_VpErrEvents[i];
+ }
+}
+
+void Dss_getEnabledPipeErrEvents(uint32_t events[DSS_EVT_MGR_MAX_CLIENT_EVENTS],
+ uint32_t *numEvts)
+{
+ uint32_t i;
+ *numEvts = sizeof(gDss_PipeErrEvents)/sizeof(uint32_t);
+ for(i=0U; i<*numEvts; i++)
+ {
+ events[i] = gDss_PipeErrEvents[i];
+ }
+}
+
+uint32_t Dss_dctrlIsPipeNode(uint32_t nodeId)
+{
+ uint32_t isPipeNode = FALSE;
+
+ if((DSS_DCTRL_NODE_VID1 == nodeId) ||
+ (DSS_DCTRL_NODE_VIDL1 == nodeId))
+ {
+ isPipeNode = TRUE;
+ }
+
+ return (isPipeNode);
+}
+
+uint32_t Dss_dctrlIsValidNode(uint32_t nodeId)
+{
+ uint32_t i, isValidNode = FALSE, graphNodeInfoSize = 0U;
+ const Fvid2_GraphNodeInfo *graphNodeInfo;
+
+ graphNodeInfo = Dss_dctrlGetDefaultNodeInfo(&graphNodeInfoSize);
+
+ for(i=1U; i<graphNodeInfoSize; i++)
+ {
+ if(nodeId == graphNodeInfo[i].nodeId)
+ {
+ isValidNode = TRUE;
+ break;
+ }
+ }
+
+ return (isValidNode);
+}
+
+uint32_t Dss_dctrlIsVideoMuxNeeded(uint32_t vpNodeId,
+ uint32_t outNodeId)
+{
+ return FALSE;
+}
+
+int32_t Dss_dctrlProgramVideoMux(uint32_t vpNodeId,
+ uint32_t outNodeId)
+{
+ return FVID2_SOK;
+}
+
+uint32_t Dss_getEvtMgrFuncIntrId(void)
+{
+ uint32_t evtMgrId;
+
+ evtMgrId = DSS_EVT_MGR_INST_ID_FUNC;
+
+ return evtMgrId;
+}
+
+uint32_t Dss_getEvtMgrSafetyIntrId(void)
+{
+ uint32_t evtMgrId;
+
+ evtMgrId = DSS_EVT_MGR_INST_ID_FUNC;
+
+ return evtMgrId;
+}
+
+uint32_t Dss_getEvtMgrSecurityIntrId(void)
+{
+ uint32_t evtMgrId;
+
+ evtMgrId = DSS_EVT_MGR_INST_ID_FUNC;
+
+ return evtMgrId;
+}
+
+int32_t Dss_fillEvtMgrInitInfo(Dss_EvtMgrInitParams *evtMgrParams,
+ Dss_IrqParams *irqParams)
+{
+ int32_t retVal = FVID2_SOK;
+
+ evtMgrParams->dssCommonRegionId = irqParams->dssCommonRegionId;
+ evtMgrParams->numIrq = irqParams->numValidIrq;
+ evtMgrParams->irqNum[0U] = irqParams->irqNum[DSS_EVT_MGR_INST_ID_FUNC];
+ evtMgrParams->instId[0U] = DSS_EVT_MGR_INST_ID_FUNC;
+
+ return retVal;
+}
+
+uint32_t Dss_dctrlGetVpSafetyRegionId(uint32_t evtId)
+{
+ uint32_t i;
+ uint32_t regionId = CSL_DSS_VP_SAFETY_REGION_INVALID;
+
+ for(i=0U;
+ i<sizeof (gDss_VpSafetyRegionIdInfo) /
+ sizeof (gDss_VpSafetyRegionIdInfo[0U]);
+ i++)
+ {
+ if(evtId == gDss_VpSafetyRegionIdInfo[i].regionErrEvt)
+ {
+ regionId = gDss_VpSafetyRegionIdInfo[i].regionId;
+ break;
+ }
+ }
+
+ return (regionId);
+}
+
+uint32_t Dss_dctrlIsSafetyEvent(uint32_t evtId)
+{
+ uint32_t retVal = FALSE;
+ if((evtId >= DSS_VP_EVENT_SAFETY_VIOLATION_0) &&
+ (evtId <= DSS_VP_EVENT_SAFETY_VIOLATION_3))
+ {
+ retVal = TRUE;
+ }
+ return retVal;
+}
+
+
+uint32_t Dss_dctrlGetVpSafetyEvtId(uint32_t regionId)
+{
+ uint32_t i;
+ uint32_t evtId = DSS_VP_EVENT_INVALID;
+
+ for(i=0U;
+ i<sizeof (gDss_VpSafetyRegionIdInfo) /
+ sizeof (gDss_VpSafetyRegionIdInfo[0U]);
+ i++)
+ {
+ if(regionId == gDss_VpSafetyRegionIdInfo[i].regionId)
+ {
+ evtId = gDss_VpSafetyRegionIdInfo[i].regionErrEvt;
+ break;
+ }
+ }
+
+ return (evtId);
+}
diff --git a/packages/ti/drv/dss/soc/V0/dss_soc.h b/packages/ti/drv/dss/soc/V0/dss_soc.h
--- /dev/null
@@ -0,0 +1,407 @@
+/*
+ * Copyright (c) Texas Instruments Incorporated 2018
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * \ingroup DRV_DSS_MODULE
+ * \defgroup DRV_DSS_SOC_MODULE DSS SoC Config
+ * This is DSS documentation specific to AM65xx SoC
+ *
+ * @{
+ */
+
+/**
+ * \file dss_soc.h
+ *
+ * \brief DSS Driver AM65xx SOC specific file.
+ */
+
+#ifndef DSS_SOC_H_
+#define DSS_SOC_H_
+
+/* ========================================================================== */
+/* Include Files */
+/* ========================================================================== */
+
+/* None */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* ========================================================================== */
+/* Macros & Typedefs */
+/* ========================================================================== */
+
+/*
+ * Macros for different driver instance numbers to be passed as instance ID
+ * at the time of driver create.
+ * Note: These are read only macros. Don't modify the value of these macros.
+ */
+
+/**
+ * \name DSS DCTRL Instance IDs
+ *
+ * @{
+ */
+
+/** \brief Display controller instance 0. */
+#define DSS_DCTRL_INST_0 (0U)
+
+/** \brief Maximum number of display driver instances */
+#define DSS_DCTRL_INST_MAX (1U)
+/* @} */
+
+/**
+ * \name DSS Display Instance IDs
+ *
+ * @{
+ */
+
+/** \brief Video 1 Pipeline display driver instance number. */
+#define DSS_DISP_INST_VID1 (CSL_DSS_VID_PIPE_ID_VID1)
+
+/** \brief Video Lite 1 Pipeline display driver instance number. */
+#define DSS_DISP_INST_VIDL1 (CSL_DSS_VID_PIPE_ID_VIDL1)
+
+/** \brief Maximum number of display driver instances */
+#define DSS_DISP_INST_MAX (CSL_DSS_VID_PIPE_ID_MAX)
+/* @} */
+
+/**
+ * \anchor Dss_DctrlNodeType
+ * \name DSS DCTRL Node type
+ *
+ * Node types that are used by the set path to connect different modules and
+ * create a graph
+ *
+ * @{
+ */
+#define DSS_DCTRL_NODE_TYPE_INVALID ((uint32_t) 0x0U)
+#define DSS_DCTRL_NODE_TYPE_PIPE ((uint32_t) 0x1U)
+#define DSS_DCTRL_NODE_TYPE_OVERLAY ((uint32_t) 0x2U)
+#define DSS_DCTRL_NODE_TYPE_VP ((uint32_t) 0x3U)
+#define DSS_DCTRL_NODE_TYPE_OUTPUT ((uint32_t) 0x4U)
+/* @} */
+
+/**
+ * \anchor Dss_DctrlNodeId
+ * \name DSS DCTRL Node Id
+ *
+ * Node ids that are used by the set path to connect different modules and
+ * create a graph
+ *
+ * @{
+ */
+#define DSS_DCTRL_NODE_INVALID ((uint32_t) 0x0U)
+#define DSS_DCTRL_NODE_VID1 ((uint32_t) 0x1U)
+#define DSS_DCTRL_NODE_VIDL1 ((uint32_t) 0x2U)
+#define DSS_DCTRL_NODE_OVERLAY1 ((uint32_t) 0x3U)
+#define DSS_DCTRL_NODE_OVERLAY2 ((uint32_t) 0x4U)
+#define DSS_DCTRL_NODE_VP1 ((uint32_t) 0x5U)
+#define DSS_DCTRL_NODE_VP2 ((uint32_t) 0x6U)
+#define DSS_DCTRL_NODE_OLDI ((uint32_t) 0x7U)
+#define DSS_DCTRL_NODE_DPI1 ((uint32_t) 0x8U)
+/* @} */
+
+/** \brief Defines maximum number of nodes for allocation including invalid node
+ */
+#define DSS_DCTRL_MAX_NODES ((uint32_t) 9U)
+
+/** \brief Defines maximum number of edges for allocation. This is derived by
+ * looking at all possible DSS connections in the SoC.
+ */
+#define DSS_DCTRL_MAX_EDGES ((uint32_t) 8U)
+
+/**< \brief DSS Functional Interrupt Number for A53 */
+#define DSS_FUNC_IRQ_DEFAULT_NUM (CSL_GIC0_INTR_DSS0_BUS_DISPC_INTR_REQ_0)
+
+/**
+ * \anchor Dss_EvtMgrInstId
+ * \name Instance Ids for DSS Event Manager.
+ *
+ * @{
+ */
+/**< \brief Instance Id for functional interrupts */
+#define DSS_EVT_MGR_INST_ID_FUNC ((uint32_t) 0x00U)
+/**< \brief Max Instance Id */
+#define DSS_EVT_MGR_INST_ID_MAX ((uint32_t) 0x01U)
+/**< \brief Invalid Instance Id */
+#define DSS_EVT_MGR_INST_ID_INVALID ((uint32_t) 0xFFU)
+/* @} */
+
+/*
+ * SOC specific IOCTLs.
+ */
+
+/**
+ * \addtogroup DRV_DSS_DCTRL_IOCTL
+ * @{
+ */
+/**
+ * \brief IOCTL to set the OLDI configuration of given video port.
+ *
+ * This IOCTL can be used to set the OLDI parameters. Refer
+ * #Dss_DctrlOldiParams for configuration details.
+ * Note: This IOCTL is supported only for AM65xx SoC.
+ *
+ * \param cmdArgs [IN] Pointer of type #Dss_DctrlOldiParams
+ * \param cmdArgsStatus [OUT] NULL
+ *
+ * \return FVID2_SOK if successful, else suitable error code
+ *
+ */
+#define IOCTL_DSS_DCTRL_SET_OLDI_PARAMS (DSS_DCTRL_SOC_IOCTL_BASE + 0x01U)
+/* @} */
+
+/* ========================================================================== */
+/* Structure Declarations */
+/* ========================================================================== */
+
+/**
+ * \brief Structure containing DSS interrupt information. Events should be
+ * enabled only for available Video Ports and Video Pipes
+ */
+typedef struct
+{
+ uint32_t dssCommonRegionId;
+ /**< DSS Common Region Id. There are multiple common regions in DSS hardware
+ * each having IRQ aggregation registers and IRQ generator. This enables
+ * fully independent monitoring/control of the interrupt events by
+ * different hosts. User can decide which common region to use. By default
+ * region 0 will be used. Refer \ref CSL_DssCommRegId for values
+ */
+ uint32_t numValidIrq;
+ /**< Number of valid DSS interrupts. There can be multiple interrupts in DSS
+ * hardware. This specifies number of valid IRQs in below array.
+ */
+ uint32_t irqNum[DSS_EVT_MGR_INST_ID_MAX];
+ /**< DSS interrupt numbers. This will enable to configure different interrupt
+ * numbers. This will be initialized to default values as specified in the
+ * DssInitParams_init function. User may override these values if allowed.
+ *
+ * Note: Driver will only register for the specified interrupt numbers.
+ * If needed the corresponding crossbar mapping for the device interrupt
+ * should be done by the application.
+ */
+} Dss_IrqParams;
+
+/**
+ * \brief Structure containing resources manager information. This enables
+ * display sharing between two different softwares.
+ */
+typedef struct
+{
+ uint32_t isCommRegAvailable[CSL_DSS_COMM_REG_ID_MAX];
+ /**< Ids for available common regions */
+ uint32_t isPipeAvailable[CSL_DSS_VID_PIPE_ID_MAX];
+ /**< Ids for available video pipes */
+ uint32_t isOverlayAvailable[CSL_DSS_OVERLAY_ID_MAX];
+ /**< Ids for available overlays */
+ uint32_t isPortAvailable[CSL_DSS_VP_ID_MAX];
+ /**< Ids for available video ports */
+} Dss_RmInfo;
+
+/**
+ * \brief DSS SOC parameters.
+ */
+typedef struct
+{
+ Dss_IrqParams irqParams;
+ /**< DSS interrupt information */
+ Dss_RmInfo rmInfo;
+ /**< DSS resource information */
+} Dss_SocParams;
+
+/**
+ * \brief Structure containing OLDI configuration. This structure is used
+ * as an argument to IOCTL_DSS_DCTRL_SET_OLDI_PARAMS.
+ */
+typedef struct
+{
+ uint32_t vpId;
+ /**< Video Port Id. See \ref CSL_DssVpId for values */
+ CSL_DssVpOldiCfg oldiCfg;
+ /**< OLDI configuration. See \ref CSL_DssVpOldiCfg for details */
+} Dss_DctrlOldiParams;
+
+/* ========================================================================== */
+/* Internal/Private Function Declarations */
+/* ========================================================================== */
+
+/**
+ * \brief Check if the display driver instance is of type Video pipeline.
+ *
+ * \param instId [IN]Driver Instance Id.
+ *
+ * \return TRUE if instance is Video pipeline else returns FALSE.
+ */
+static inline uint32_t Dss_dispIsVidInst(uint32_t instId);
+
+/**
+ * \brief Check if the display driver instance is of type Video lite pipeline.
+ *
+ * \param instId [IN]Driver Instance Id.
+ *
+ * \return TRUE if instance is Video lite pipeline else returns FALSE.
+ */
+static inline uint32_t Dss_dispIsVidLInst(uint32_t instId);
+
+/**
+ * \brief Dss_IrqParams structure init function.
+ *
+ * \param irqParams Pointer to #Dss_IrqParams structure.
+ *
+ * \return None
+ */
+static inline void Dss_irqParamsInit(Dss_IrqParams *irqParams);
+
+/**
+ * \brief Dss_RmInfo structure init function.
+ *
+ * \param rmInfo Pointer to #Dss_RmInfo structure.
+ *
+ * \return None
+ */
+static inline void Dss_rmInfoInit(Dss_RmInfo *rmInfo);
+
+/**
+ * \brief Dss_SocParams structure init function.
+ *
+ * \param socParams Pointer to #Dss_SocParams structure.
+ *
+ * \return None
+ */
+static inline void Dss_socParamsInit(Dss_SocParams *socParams);
+
+/**
+ * \brief Dss_DctrlOldiParams structure init function.
+ *
+ * \param oldiParams [IN]Pointer to #Dss_DctrlOldiParams structure.
+ *
+ * \return None
+ */
+static inline void Dss_dctrlOldiParamsInit(Dss_DctrlOldiParams *oldiParams);
+
+/* ========================================================================== */
+/* Function Declarations */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/* Static Function Definitions */
+/* ========================================================================== */
+
+static inline uint32_t Dss_dispIsVidInst(uint32_t instId)
+{
+ uint32_t isVidInst = FALSE;
+
+ if(DSS_DISP_INST_VID1 == instId)
+ {
+ isVidInst = TRUE;
+ }
+
+ return (isVidInst);
+}
+
+static inline uint32_t Dss_dispIsVidLInst(uint32_t instId)
+{
+ uint32_t isVidLInst = FALSE;
+
+ if(DSS_DISP_INST_VIDL1 == instId)
+ {
+ isVidLInst = TRUE;
+ }
+
+ return (isVidLInst);
+}
+
+static inline void Dss_irqParamsInit(Dss_IrqParams *irqParams)
+{
+ if(NULL != irqParams)
+ {
+ irqParams->dssCommonRegionId = CSL_DSS_COMM_REG_ID_0;
+ irqParams->numValidIrq = DSS_EVT_MGR_INST_ID_MAX;
+ irqParams->irqNum[DSS_EVT_MGR_INST_ID_FUNC] = DSS_FUNC_IRQ_DEFAULT_NUM;
+ }
+}
+
+static inline void Dss_rmInfoInit(Dss_RmInfo *rmInfo)
+{
+ uint32_t i = 0U;
+ if(NULL != rmInfo)
+ {
+ for(i=CSL_DSS_COMM_REG_ID_0; i<CSL_DSS_COMM_REG_ID_MAX; i++)
+ {
+ rmInfo->isCommRegAvailable[i] = TRUE;
+ }
+ for(i=CSL_DSS_VID_PIPE_ID_VID1; i<CSL_DSS_VID_PIPE_ID_MAX; i++)
+ {
+ rmInfo->isPipeAvailable[i] = TRUE;
+ }
+ for(i=CSL_DSS_OVERLAY_ID_1; i<CSL_DSS_OVERLAY_ID_MAX; i++)
+ {
+ rmInfo->isOverlayAvailable[i] = TRUE;
+ }
+ for(i=CSL_DSS_VP_ID_1; i<CSL_DSS_VP_ID_MAX; i++)
+ {
+ rmInfo->isPortAvailable[i] = TRUE;
+ }
+ }
+}
+
+static inline void Dss_socParamsInit(Dss_SocParams *socParams)
+{
+ if(NULL != socParams)
+ {
+ Dss_irqParamsInit(&(socParams->irqParams));
+ Dss_rmInfoInit(&(socParams->rmInfo));
+ }
+}
+
+static inline void Dss_dctrlOldiParamsInit(Dss_DctrlOldiParams *oldiParams)
+{
+ if(NULL != oldiParams)
+ {
+ oldiParams->vpId = CSL_DSS_VP_ID_1;
+ CSL_dssVpOldiCfgInit(&(oldiParams->oldiCfg));
+ }
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #ifndef DSS_SOC_VO_H_ */
+
+/* @} */
diff --git a/packages/ti/drv/dss/soc/V0/dss_soc_graph.c b/packages/ti/drv/dss/soc/V0/dss_soc_graph.c
--- /dev/null
@@ -0,0 +1,136 @@
+/*
+ * Copyright (c) Texas Instruments Incorporated 2018
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * \file dss_soc_graph.c
+ *
+ * \brief File containing the graph related configuration functions for DSS.
+ *
+ */
+
+/* ========================================================================== */
+/* Include Files */
+/* ========================================================================== */
+
+#include <ti/drv/dss/dss.h>
+#include "dss_soc_priv.h"
+
+/* ========================================================================== */
+/* Macros & Typedefs */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/* Structure Declarations */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/* Function Declarations */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/* Global Variables */
+/* ========================================================================== */
+
+static const Fvid2_GraphNodeInfo gDctrlGraphNodeInfoDefaults[DSS_DCTRL_MAX_NODES] =
+{
+ {DSS_DCTRL_NODE_INVALID,
+ FVID2_GRAPH_NODE_IN_NONE, FVID2_GRAPH_NODE_IN_NONE,
+ FVID2_GRAPH_NODE_TYPE_DUMMY,
+ 0U, 0U, {0U, {NULL}, {0}}, {0U, {NULL}, {0}}},
+ {DSS_DCTRL_NODE_VID1,
+ FVID2_GRAPH_NODE_IN_SINGLE, FVID2_GRAPH_NODE_OUT_MULTI,
+ FVID2_GRAPH_NODE_TYPE_DSS_PIPE,
+ 0U, 0U, {0U, {NULL}, {0}}, {0U, {NULL}, {0}}},
+ {DSS_DCTRL_NODE_VIDL1,
+ FVID2_GRAPH_NODE_IN_SINGLE, FVID2_GRAPH_NODE_OUT_MULTI,
+ FVID2_GRAPH_NODE_TYPE_DSS_PIPE,
+ 0U, 0U, {0U, {NULL}, {0}}, {0U, {NULL}, {0}}},
+ {DSS_DCTRL_NODE_OVERLAY1,
+ FVID2_GRAPH_NODE_IN_MULTI, FVID2_GRAPH_NODE_OUT_SINGLE,
+ FVID2_GRAPH_NODE_TYPE_DSS_OVERLAY,
+ 0U, 0U, {0U, {NULL}, {0}}, {0U, {NULL}, {0}}},
+ {DSS_DCTRL_NODE_OVERLAY2,
+ FVID2_GRAPH_NODE_IN_MULTI, FVID2_GRAPH_NODE_OUT_SINGLE,
+ FVID2_GRAPH_NODE_TYPE_DSS_OVERLAY,
+ 0U, 0U, {0U, {NULL}, {0}}, {0U, {NULL}, {0}}},
+ {DSS_DCTRL_NODE_VP1,
+ FVID2_GRAPH_NODE_IN_SINGLE, FVID2_GRAPH_NODE_OUT_SINGLE,
+ FVID2_GRAPH_NODE_TYPE_DSS_VP,
+ 0U, 0U, {0U, {NULL}, {0}}, {0U, {NULL}, {0}}},
+ {DSS_DCTRL_NODE_VP2,
+ FVID2_GRAPH_NODE_IN_SINGLE, FVID2_GRAPH_NODE_OUT_SINGLE,
+ FVID2_GRAPH_NODE_TYPE_DSS_VP,
+ 0U, 0U, {0U, {NULL}, {0}}, {0U, {NULL}, {0}}},
+ {DSS_DCTRL_NODE_OLDI,
+ FVID2_GRAPH_NODE_IN_SINGLE, FVID2_GRAPH_NODE_OUT_SINGLE,
+ FVID2_GRAPH_NODE_TYPE_DSS_OUT,
+ 0U, 0U, {0U, {NULL}, {0}}, {0U, {NULL}, {0}}},
+ {DSS_DCTRL_NODE_DPI1,
+ FVID2_GRAPH_NODE_IN_SINGLE, FVID2_GRAPH_NODE_OUT_SINGLE,
+ FVID2_GRAPH_NODE_TYPE_DSS_OUT,
+ 0U, 0U, {0U, {NULL}, {0}}, {0U, {NULL}, {0}}}
+};
+
+static const Fvid2_GraphEdgeInfo gDctrlGraphEdgeInfoDefaults[DSS_DCTRL_MAX_EDGES] =
+{
+ {DSS_DCTRL_NODE_VID1, DSS_DCTRL_NODE_OVERLAY1},
+ {DSS_DCTRL_NODE_VIDL1, DSS_DCTRL_NODE_OVERLAY1},
+ {DSS_DCTRL_NODE_VID1, DSS_DCTRL_NODE_OVERLAY2},
+ {DSS_DCTRL_NODE_VIDL1, DSS_DCTRL_NODE_OVERLAY2},
+ {DSS_DCTRL_NODE_OVERLAY1, DSS_DCTRL_NODE_VP1},
+ {DSS_DCTRL_NODE_OVERLAY2, DSS_DCTRL_NODE_VP2},
+ {DSS_DCTRL_NODE_VP1, DSS_DCTRL_NODE_OLDI},
+ {DSS_DCTRL_NODE_VP2, DSS_DCTRL_NODE_DPI1}
+};
+
+/* ========================================================================== */
+/* Function Definitions */
+/* ========================================================================== */
+
+const Fvid2_GraphEdgeInfo* Dss_dctrlGetDefaultEdgeInfo(uint32_t *edgeMemSize)
+{
+ *edgeMemSize = sizeof (gDctrlGraphEdgeInfoDefaults);
+ return &gDctrlGraphEdgeInfoDefaults[0U];
+}
+
+const Fvid2_GraphNodeInfo* Dss_dctrlGetDefaultNodeInfo(uint32_t *nodeMemSize)
+{
+ *nodeMemSize = sizeof (gDctrlGraphNodeInfoDefaults);
+ return &gDctrlGraphNodeInfoDefaults[0U];
+}
diff --git a/packages/ti/drv/dss/soc/V0/dss_soc_priv.h b/packages/ti/drv/dss/soc/V0/dss_soc_priv.h
--- /dev/null
@@ -0,0 +1,590 @@
+/*
+ * Copyright (c) Texas Instruments Incorporated 2018
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * \file dss_soc_priv.h
+ *
+ * \brief DSS Driver AM65xx SOC file containing private APIs used by display
+ * and display controller driver.
+ */
+
+#ifndef DSS_SOC_PRIV_H_
+#define DSS_SOC_PRIV_H_
+
+/* ========================================================================== */
+/* Include Files */
+/* ========================================================================== */
+
+/* None */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* ========================================================================== */
+/* Macros & Typedefs */
+/* ========================================================================== */
+
+/**
+ * \anchor Dss_EventGroup
+ * \name DSS Events are logically grouped under one of the following
+ * categories.
+ *
+ * @{
+ */
+/**< \brief Event Group for VP1 */
+#define DSS_EVENT_GROUP_VP1 CSL_DSS_DISPC_INTR_VP1_MASK
+/**< \brief Event Group for VP2 */
+#define DSS_EVENT_GROUP_VP2 CSL_DSS_DISPC_INTR_VP2_MASK
+/**< \brief Event Group for VID1 */
+#define DSS_EVENT_GROUP_VID1 CSL_DSS_DISPC_INTR_VID1_MASK
+/**< \brief Event Group for VIDL1 */
+#define DSS_EVENT_GROUP_VIDL1 CSL_DSS_DISPC_INTR_VIDL1_MASK
+/**< \brief Invalid Event Group */
+#define DSS_EVENT_GROUP_INVALID ((uint32_t) 0xFFU)
+/* @} */
+
+/**
+ * \anchor Dss_EventGroupType
+ * \name DSS Event Groups are logically grouped under one of the following
+ * categories.
+ *
+ * @{
+ */
+/**< \brief Event Group for VP */
+#define DSS_EVENT_GROUP_TYPE_VP ((uint32_t) 0x00U)
+/**< \brief Event Group for Pipe */
+#define DSS_EVENT_GROUP_TYPE_PIPE ((uint32_t) 0x01U)
+/**< \brief Invalid Event Group */
+#define DSS_EVENT_GROUP_TYPE_INVALID ((uint32_t) 0xFFU)
+/* @} */
+
+/**
+ * \anchor Dss_VpEvents
+ * \name List of Video Port Events.
+ *
+ * @{
+ */
+/**< \brief Frame done interrupt */
+#define DSS_VP_EVENT_FRAME_DONE \
+ CSL_DSS_VP_INTR_FRAMEDONE_MASK
+/**< \brief Vsync interrupt */
+#define DSS_VP_EVENT_VSYNC \
+ CSL_DSS_VP_INTR_VSYNC_MASK
+/**< \brief Odd Vsync interrupt in case of interlace display */
+#define DSS_VP_EVENT_ODD_VSYNC \
+ CSL_DSS_VP_INTR_ODDVSYNC_MASK
+/**< \brief Line number interrupt */
+#define DSS_VP_EVENT_LINE_NUM \
+ CSL_DSS_VP_INTR_PROGLINENUM_MASK
+/**< \brief Sync lost Interrupt */
+#define DSS_VP_EVENT_SYNC_LOST \
+ CSL_DSS_VP_INTR_SYNCLOST_MASK
+/**< \brief AC Bias transition counter 0 interrupt */
+#define DSS_VP_EVENT_ACBIAS_COUNT \
+ CSL_DSS_VP_INTR_ACBIASCOUNT_MASK
+/**< \brief Safety violation region 0 interrupt */
+#define DSS_VP_EVENT_SAFETY_VIOLATION_0 \
+ CSL_DSS_VP_INTR_SAFETYVIOLATION_REGION0_MASK
+/**< \brief Safety violation region 1 interrupt */
+#define DSS_VP_EVENT_SAFETY_VIOLATION_1 \
+ CSL_DSS_VP_INTR_SAFETYVIOLATION_REGION1_MASK
+/**< \brief Safety violation region 2 interrupt */
+#define DSS_VP_EVENT_SAFETY_VIOLATION_2 \
+ CSL_DSS_VP_INTR_SAFETYVIOLATION_REGION2_MASK
+/**< \brief Safety violation region 3 interrupt */
+#define DSS_VP_EVENT_SAFETY_VIOLATION_3 \
+ CSL_DSS_VP_INTR_SAFETYVIOLATION_REGION3_MASK
+/**< \brief Security violation Interrupt */
+#define DSS_VP_EVENT_SECURITY_VIOLATION \
+ CSL_DSS_VP_INTR_SECURITYVIOLATION_MASK
+/**< \brief Go bit clear interrupt */
+#define DSS_VP_EVENT_GO_BIT_CLEAR \
+ CSL_DSS_VP_INTR_GOBITCLEAR_MASK
+/**< \brief Invalid event Id */
+#define DSS_VP_EVENT_INVALID ((uint32_t) 0xFFU)
+/* @} */
+
+/**
+ * \anchor Dss_PipeEvents
+ * \name List of Video Pipe Events.
+ *
+ * @{
+ */
+/**< \brief Safety violation interrupt */
+#define DSS_PIPE_EVENT_SAFETY_VIOLATION \
+ CSL_DSS_VID_PIPE_INTR_SAFETYVIOLATION_MASK
+/**< \brief Window end Interrupt */
+#define DSS_PIPE_EVENT_WINDOW_END \
+ CSL_DSS_VID_PIPE_INTR_WINDOWEND_MASK
+/**< \brief Buffer underflow interrupt */
+#define DSS_PIPE_EVENT_BUFF_UNDERFLOW \
+ CSL_DSS_VID_PIPE_INTR_BUFUNDERFLOW_MASK
+/* @} */
+
+/** \brief Maximum number of clients for Event Manager */
+#define DSS_EVT_MGR_MAX_CLIENTS ((uint32_t) 12U)
+
+/** \brief Maximum number of client events */
+#define DSS_EVT_MGR_MAX_CLIENT_EVENTS ((uint32_t) 15U)
+
+/** \brief Maximum number of display clients for Event Manager */
+#define DSS_DISP_EVT_MGR_MAX_CLIENTS ((uint32_t) 4U)
+
+/** \brief Maximum number of display clients per instance for Event Manager */
+#define DSS_DISP_INST_EVT_MGR_MAX_CLIENTS ((uint32_t) 2U)
+
+/** \brief Maximum number of display controller clients for Event Manager */
+#define DSS_DCTRL_EVT_MGR_MAX_CLIENTS ((uint32_t) 8U)
+
+/* ========================================================================== */
+/* Structure Declarations */
+/* ========================================================================== */
+
+/** \brief Forward declaration of Event Manager information structure */
+typedef struct Dss_EvtMgrInfo_t Dss_EvtMgrInfo;
+
+/** \brief Forward declaration of Event Manager initialization structure */
+typedef struct Dss_EvtMgrInitParams_t Dss_EvtMgrInitParams;
+
+/**
+ * \brief This structure contains common region register information
+ */
+typedef struct
+{
+ uint32_t commRegId;
+ /**< Common region id. Refer #CSL_DssCommRegId for valid values */
+ void *commRegs;
+ /**< Common region registers */
+} Dss_CommRegInfo;
+
+/**
+ * \brief This structure contains video pipe register information
+ */
+typedef struct
+{
+ uint32_t pipeId;
+ /**< Video pipe id. Refer #CSL_DssVidPipeId for valid values */
+ void *pipeRegs;
+ /**< Video Pipe registers */
+} Dss_PipeRegInfo;
+
+/**
+ * \brief This structure contains overlay register information
+ */
+typedef struct
+{
+ uint32_t overlayId;
+ /**< Overlay id. Refer #CSL_DssOverlayId for valid values */
+ void *overlayRegs;
+ /**< Overlay registers */
+} Dss_OverlayRegInfo;
+
+/**
+ * \brief This structure contains video port register information
+ */
+typedef struct
+{
+ uint32_t vpId;
+ /**< Video port id. Refer #CSL_DssVpId for valid values */
+ void *vpRegs;
+ /**< Video port registers */
+} Dss_VpRegInfo;
+
+/**
+ * \brief This structure defines module id for a particular nodeId
+ */
+typedef struct
+{
+ uint32_t nodeId;
+ /**< Node Id. Refer #Dss_DctrlNodeId for valid values */
+ uint32_t moduleId;
+ /**< Module Id */
+ uint32_t nodeType;
+ /**< Node type. Refer #Dss_DctrlNodeType for valid values */
+} Dss_DctrlNodeIdInfo;
+
+/**
+ * \brief Structure containing information about DSS register space.
+ */
+typedef struct
+{
+ CSL_dss_commRegs *commRegs[CSL_DSS_COMM_REG_ID_MAX];
+ /**< Common region registers */
+ CSL_dss_pipeRegs *pipeRegs[CSL_DSS_VID_PIPE_ID_MAX];
+ /**< Pipe registers */
+ CSL_dss_overlayRegs *overlayRegs[CSL_DSS_OVERLAY_ID_MAX];
+ /**< Overlay registers */
+ CSL_dss_vpRegs *vpRegs[CSL_DSS_VP_ID_MAX];
+ /**< Video Port registers */
+} Dss_SocInfo;
+
+/**
+ * \brief This structure defines information about overlay connection
+ */
+typedef struct
+{
+ uint32_t overlayId;
+ /**< Overlay Id. Refer #CSL_DssOverlayId for valid values */
+ uint32_t vpId;
+ /**< Video Port Id. Refer #CSL_DssVpId for valid values */
+} Dss_OverlayConnInfo;
+
+/**
+ * \brief This structure contains event group information
+ */
+typedef struct
+{
+ uint32_t eventGroup;
+ /**< Event Group. Refer \ref Dss_EventGroup for valid values */
+ uint32_t moduleId;
+ /**< Event Group's module id */
+ uint32_t eventGroupType;
+ /**< Event Group's type. Refer \ref Dss_EventGroupType for values */
+} Dss_EventGroupInfo;
+
+/**
+ * \brief This structure contains safety region information
+ */
+typedef struct
+{
+ uint32_t regionId;
+ /**< Safety region Id */
+ uint32_t regionErrEvt;
+ /**< Safety region error event */
+} Dss_VpSafetyRegionIdInfo;
+
+/* ========================================================================== */
+/* Internal/Private Function Declarations */
+/* ========================================================================== */
+
+/**
+ * \brief Dss_SocInfo structure init function
+ *
+ * \param socInfo Pointer to #Dss_SocInfo structure
+ *
+ * \return None
+ */
+static inline void Dss_socInfoInit(Dss_SocInfo *socInfo);
+
+/* ========================================================================== */
+/* Function Declarations */
+/* ========================================================================== */
+
+/**
+ * \brief This API fills the SoC information depending on the resources
+ * available to the DSS driver.
+ *
+ * \param rmInfo Resource information. Refer #Dss_RmInfo for details
+ *
+ * \return None
+ */
+void Dss_fillSocInfo(Dss_RmInfo *rmInfo);
+
+/**
+ * \brief This API gets the SoC information depending on the resources
+ * available to the DSS driver.
+ *
+ * \param None
+ *
+ * \return Pointer to Dss_SocInfo object
+ */
+const Dss_SocInfo* Dss_getSocInfo(void);
+
+/**
+ * \brief Get the module id for a given graph node.
+ *
+ * \param nodeId Node Id. Refer \ref Dss_DctrlNodeId for valid values
+ * \param moduleId Module Id
+ *
+ * \return FVID2_SOK if successful, else failure
+ */
+int32_t Dss_convNodetoModule(uint32_t nodeId,
+ uint32_t *moduleId);
+
+/**
+ * \brief Get the graph node id for a given module.
+ *
+ * \param nodeId Node Id. Refer \ref Dss_DctrlNodeId for valid values
+ * \param moduleId Module Id
+ *
+ * \return FVID2_SOK if successful, else failure
+ */
+int32_t Dss_convModuletoNode(uint32_t *nodeId,
+ uint32_t moduleId,
+ uint32_t nodeType);
+
+/**
+ * \brief Get the module id for a given event group.
+ *
+ * \param eventGroup Event Group. Refer \ref Dss_EventGroup for valid values
+ * \param moduleId Module Id
+ *
+ * \return None
+ */
+void Dss_convEventGrouptoModule(uint32_t eventGroup,
+ uint32_t *moduleId);
+
+/**
+ * \brief Get the event group for a given module.
+ *
+ * \param eventGroup Event Group. Refer \ref Dss_EventGroup.
+ * \param moduleId Module Id
+ * \param eventGroupType Event group type
+ *
+ * \return None
+ */
+void Dss_convModuletoEventGroup(uint32_t *eventGroup,
+ uint32_t moduleId,
+ uint32_t eventGroupType);
+
+/**
+ * \brief This API gets the default edge information.
+ *
+ * \param edgeMemSize Graph edge memory size
+ *
+ * \return Pointer to Fvid2_GraphEdgeInfo object
+ */
+const Fvid2_GraphEdgeInfo* Dss_dctrlGetDefaultEdgeInfo(uint32_t *edgeMemSize);
+
+/**
+ * \brief This API gets the default node information.
+ *
+ * \param nodeMemSize Graph node memory size
+ *
+ * \return Pointer to Fvid2_GraphNodeInfo object
+ */
+const Fvid2_GraphNodeInfo* Dss_dctrlGetDefaultNodeInfo(uint32_t *nodeMemSize);
+
+/**
+ * \brief Get the Video Port connected to a particular overlay.
+ *
+ * \param overlayId Overlay id. Refer #CSL_DssOverlayId for valid values
+ *
+ * \return vpId Video Port Id
+ */
+uint32_t Dss_getVpConnId(uint32_t overlayId);
+
+/**
+ * \brief This API enables the DSS event in level 1 registers for a particular
+ * event group.
+ *
+ * \param evtMgrInfo Event manager information.
+ * Refer #Dss_EvtMgrInfo for details.
+ * \param dssCommonRegionId DSS common region id
+ * \param eventGroup Event group for which event should be enabled
+ * \param event Event id
+ * \param eventCnt Event Count
+ *
+ * \return FVID2_SOK if successful, else failure
+ */
+int32_t Dss_enableL1Event(Dss_EvtMgrInfo *evtMgrInfo,
+ uint32_t dssCommonRegionId,
+ uint32_t eventGroup,
+ uint32_t event,
+ uint32_t eventCnt);
+
+/**
+ * \brief This API returns the list of enabled VP functional events.
+ *
+ * \param events Array of events.
+ * \param numEvts Pointer to number of events.
+ *
+ * \return Pointer to VP functional events.
+ */
+void Dss_getEnabledVpFuncEvents(uint32_t events[DSS_EVT_MGR_MAX_CLIENT_EVENTS],
+ uint32_t *numEvts);
+
+/**
+ * \brief This API returns the list of enabled VP error events.
+ *
+ * \param events Array of events.
+ * \param numEvts Pointer to number of events.
+ *
+ * \return Pointer to VP error events.
+ */
+void Dss_getEnabledVpErrEvents(uint32_t events[DSS_EVT_MGR_MAX_CLIENT_EVENTS],
+ uint32_t *numEvts);
+
+/**
+ * \brief This API returns the list of enabled pipe error events.
+ *
+ * \param events Array of events.
+ * \param numEvts Pointer to number of events.
+ *
+ * \return Pointer to Pipe error events.
+ */
+void Dss_getEnabledPipeErrEvents(uint32_t events[DSS_EVT_MGR_MAX_CLIENT_EVENTS],
+ uint32_t *numEvts);
+
+/**
+ * \brief Check if the given node is video pipe node
+ *
+ * \param nodeId Node Id.
+ *
+ * \return TRUE if node is Video pipe node else returns FALSE.
+ */
+uint32_t Dss_dctrlIsPipeNode(uint32_t nodeId);
+
+/**
+ * \brief Check if the given node is valid
+ *
+ * \param nodeId Node Id.
+ *
+ * \return TRUE if given node is valid else returns FALSE.
+ */
+uint32_t Dss_dctrlIsValidNode(uint32_t nodeId);
+
+/**
+ * \brief Check if the Video Mux Programming is Needed
+ *
+ * \param vpNodeId Video Port Node Id.
+ * \param outNodeId Output Node Id.
+ *
+ * \return TRUE if programming is needed else returns FALSE.
+ */
+uint32_t Dss_dctrlIsVideoMuxNeeded(uint32_t vpNodeId,
+ uint32_t outNodeId);
+
+/**
+ * \brief This API does the required video mux programming.
+ *
+ * \param vpNodeId Video Port Node Id.
+ * \param outNodeId Output Node Id.
+ *
+ * \return FVID2_SOK if programming is successful else failure.
+ */
+int32_t Dss_dctrlProgramVideoMux(uint32_t vpNodeId,
+ uint32_t outNodeId);
+
+/**
+ * \brief Get the event manager id for functional interrupts.
+ *
+ * \param None
+ *
+ * \return evtMgrId Event Manager Id
+ */
+uint32_t Dss_getEvtMgrFuncIntrId(void);
+
+/**
+ * \brief Get the event manager id for safety interrupts.
+ *
+ * \param None
+ *
+ * \return evtMgrId Event Manager Id
+ */
+uint32_t Dss_getEvtMgrSafetyIntrId(void);
+
+/**
+ * \brief Get the event manager id for security interrupts.
+ *
+ * \param None
+ *
+ * \return evtMgrId Event Manager Id
+ */
+uint32_t Dss_getEvtMgrSecurityIntrId(void);
+
+/**
+ * \brief This API fills the event manager initialization information depending
+ * on interrupt parameters passed by application.
+ *
+ * \param evtMgrParams Event manager initialization parameters.
+ * Refer #Dss_EvtMgrInitParams for details.
+ * \param irqParams DSS IRQ initialization parameters.
+ * Refer #Dss_IrqParams for details.
+ *
+ * \return FVID2_SOK if programming is successful else failure.
+ */
+int32_t Dss_fillEvtMgrInitInfo(Dss_EvtMgrInitParams *evtMgrParams,
+ Dss_IrqParams *irqParams);
+
+/**
+ * \brief Get the Safety region id for a particular safety error event.
+ *
+ * \param evtId Safety error event id.
+ *
+ * \return Safety region id.
+ */
+uint32_t Dss_dctrlGetVpSafetyRegionId(uint32_t evtId);
+
+/**
+ * \brief Get if the particular event is Safety Event.
+ *
+ * \param evtId Event id.
+ *
+ * \return TRUE if event is safety event, else FALSE.
+ */
+uint32_t Dss_dctrlIsSafetyEvent(uint32_t evtId);
+
+/**
+ * \brief Get the Safety error event id for a particular region id.
+ *
+ * \param regionId Safety region id.
+ *
+ * \return Safety error event id.
+ */
+uint32_t Dss_dctrlGetVpSafetyEvtId(uint32_t regionId);
+
+/* ========================================================================== */
+/* Static Function Definitions */
+/* ========================================================================== */
+
+static inline void Dss_socInfoInit(Dss_SocInfo *socInfo)
+{
+ uint32_t i = 0U;
+ if(NULL != socInfo)
+ {
+ for(i=CSL_DSS_COMM_REG_ID_0; i<CSL_DSS_COMM_REG_ID_MAX; i++)
+ {
+ socInfo->commRegs[i]=NULL;
+ }
+ for(i=CSL_DSS_VID_PIPE_ID_VID1; i<CSL_DSS_VID_PIPE_ID_MAX; i++)
+ {
+ socInfo->pipeRegs[i]=NULL;
+ }
+ for(i=CSL_DSS_OVERLAY_ID_1; i<CSL_DSS_OVERLAY_ID_MAX; i++)
+ {
+ socInfo->overlayRegs[i]=NULL;
+ }
+ for(i=CSL_DSS_VP_ID_1; i<CSL_DSS_VP_ID_MAX; i++)
+ {
+ socInfo->vpRegs[i]=NULL;
+ }
+ }
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #ifndef DSS_SOC_PRIV_H_ */
diff --git a/packages/ti/drv/dss/soc/V1/dss_soc.c b/packages/ti/drv/dss/soc/V1/dss_soc.c
--- /dev/null
@@ -0,0 +1,689 @@
+/*
+ * Copyright (c) Texas Instruments Incorporated 2018
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * \file dss_soc.c
+ *
+ * \brief File containing the SOC related configuration functions for DSS.
+ *
+ */
+
+/* ========================================================================== */
+/* Include Files */
+/* ========================================================================== */
+
+#include <ti/drv/dss/dss.h>
+#include <dss_soc_priv.h>
+#include <ti/drv/dss/src/drv/common/dss_evtMgr.h>
+
+/* ========================================================================== */
+/* Macros & Typedefs */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/* Structure Declarations */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/* Function Declarations */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/* Global Variables */
+/* ========================================================================== */
+
+/** Module ids for display controller nodes. For nodes that are not part of DSS
+ * HW, module id is not defined
+ */
+static const Dss_DctrlNodeIdInfo gDss_DctrlNodeIdInfo[] = {
+ {DSS_DCTRL_NODE_VID1, CSL_DSS_VID_PIPE_ID_VID1, DSS_DCTRL_NODE_TYPE_PIPE},
+ {DSS_DCTRL_NODE_VIDL1, CSL_DSS_VID_PIPE_ID_VIDL1, DSS_DCTRL_NODE_TYPE_PIPE},
+ {DSS_DCTRL_NODE_VID2, CSL_DSS_VID_PIPE_ID_VID2, DSS_DCTRL_NODE_TYPE_PIPE},
+ {DSS_DCTRL_NODE_VIDL2, CSL_DSS_VID_PIPE_ID_VIDL2, DSS_DCTRL_NODE_TYPE_PIPE},
+ {DSS_DCTRL_NODE_OVERLAY1, CSL_DSS_OVERLAY_ID_1, DSS_DCTRL_NODE_TYPE_OVERLAY},
+ {DSS_DCTRL_NODE_OVERLAY2, CSL_DSS_OVERLAY_ID_2, DSS_DCTRL_NODE_TYPE_OVERLAY},
+ {DSS_DCTRL_NODE_OVERLAY3, CSL_DSS_OVERLAY_ID_3, DSS_DCTRL_NODE_TYPE_OVERLAY},
+ {DSS_DCTRL_NODE_OVERLAY4, CSL_DSS_OVERLAY_ID_4, DSS_DCTRL_NODE_TYPE_OVERLAY},
+ {DSS_DCTRL_NODE_VP1, CSL_DSS_VP_ID_1, DSS_DCTRL_NODE_TYPE_VP},
+ {DSS_DCTRL_NODE_VP2, CSL_DSS_VP_ID_2, DSS_DCTRL_NODE_TYPE_VP},
+ {DSS_DCTRL_NODE_VP3, CSL_DSS_VP_ID_3, DSS_DCTRL_NODE_TYPE_VP},
+ {DSS_DCTRL_NODE_VP4, CSL_DSS_VP_ID_4, DSS_DCTRL_NODE_TYPE_VP},
+ {DSS_DCTRL_NODE_DPI_DPI0, CSL_DSS_DPI_ID_DPI_0, DSS_DCTRL_NODE_TYPE_OUTPUT}, /* Virtual Node */
+ {DSS_DCTRL_NODE_DPI_DPI1, CSL_DSS_DPI_ID_DPI_1, DSS_DCTRL_NODE_TYPE_OUTPUT}, /* Virtual Node */
+ {DSS_DCTRL_NODE_EDP_DPI0, CSL_DSS_DPI_ID_EDP_0, DSS_DCTRL_NODE_TYPE_OUTPUT}, /* Virtual Node */
+ {DSS_DCTRL_NODE_EDP_DPI1, CSL_DSS_DPI_ID_EDP_1, DSS_DCTRL_NODE_TYPE_OUTPUT}, /* Virtual Node */
+ {DSS_DCTRL_NODE_EDP_DPI2, CSL_DSS_DPI_ID_EDP_2, DSS_DCTRL_NODE_TYPE_OUTPUT}, /* Virtual Node */
+ {DSS_DCTRL_NODE_EDP_DPI3, CSL_DSS_DPI_ID_EDP_3, DSS_DCTRL_NODE_TYPE_OUTPUT}, /* Virtual Node */
+ {DSS_DCTRL_NODE_DSI, CSL_DSS_DPI_ID_DSI, DSS_DCTRL_NODE_TYPE_OUTPUT} /* Virtual Node */
+};
+
+static const Dss_CommRegInfo gDss_commRegInfo[] = {
+ {CSL_DSS_COMM_REG_ID_0, (void *)CSL_DSS0_DISPC_0_COMMON_M_BASE},
+ {CSL_DSS_COMM_REG_ID_1, (void *)CSL_DSS0_DISPC_0_COMMON_S0_BASE},
+ {CSL_DSS_COMM_REG_ID_2, (void *)CSL_DSS0_DISPC_0_COMMON_S1_BASE},
+ {CSL_DSS_COMM_REG_ID_3, (void *)CSL_DSS0_DISPC_0_COMMON_S2_BASE}
+};
+
+static const Dss_PipeRegInfo gDss_pipeRegInfo[] = {
+ {CSL_DSS_VID_PIPE_ID_VID1, (void *)CSL_DSS0_VID1_BASE},
+ {CSL_DSS_VID_PIPE_ID_VIDL1, (void *)CSL_DSS0_VIDL1_BASE},
+ {CSL_DSS_VID_PIPE_ID_VID2, (void *)CSL_DSS0_VID2_BASE},
+ {CSL_DSS_VID_PIPE_ID_VIDL2, (void *)CSL_DSS0_VIDL2_BASE}
+};
+
+static const Dss_OverlayRegInfo gDss_overlayRegInfo[] = {
+ {CSL_DSS_OVERLAY_ID_1, (void *)CSL_DSS0_OVR1_BASE},
+ {CSL_DSS_OVERLAY_ID_2, (void *)CSL_DSS0_OVR2_BASE},
+ {CSL_DSS_OVERLAY_ID_3, (void *)CSL_DSS0_OVR3_BASE},
+ {CSL_DSS_OVERLAY_ID_4, (void *)CSL_DSS0_OVR4_BASE}
+};
+
+static const Dss_VpRegInfo gDss_vpRegInfo[] = {
+ {CSL_DSS_VP_ID_1, (void *)CSL_DSS0_VP1_BASE},
+ {CSL_DSS_VP_ID_2, (void *)CSL_DSS0_VP2_BASE},
+ {CSL_DSS_VP_ID_3, (void *)CSL_DSS0_VP3_BASE},
+ {CSL_DSS_VP_ID_4, (void *)CSL_DSS0_VP4_BASE}
+};
+
+static const Dss_OverlayConnInfo gDss_OverlayConnInfo[] = {
+ {CSL_DSS_OVERLAY_ID_1, CSL_DSS_VP_ID_1},
+ {CSL_DSS_OVERLAY_ID_2, CSL_DSS_VP_ID_2},
+ {CSL_DSS_OVERLAY_ID_3, CSL_DSS_VP_ID_3},
+ {CSL_DSS_OVERLAY_ID_4, CSL_DSS_VP_ID_4}
+};
+
+static const Dss_VpSafetyRegionIdInfo gDss_VpSafetyRegionIdInfo[] = {
+ {CSL_DSS_VP_SAFETY_REGION_0, DSS_VP_EVENT_SAFETY_VIOLATION_0},
+ {CSL_DSS_VP_SAFETY_REGION_1, DSS_VP_EVENT_SAFETY_VIOLATION_1},
+ {CSL_DSS_VP_SAFETY_REGION_2, DSS_VP_EVENT_SAFETY_VIOLATION_2},
+ {CSL_DSS_VP_SAFETY_REGION_3, DSS_VP_EVENT_SAFETY_VIOLATION_3},
+ {CSL_DSS_VP_SAFETY_REGION_4, DSS_VP_EVENT_SAFETY_VIOLATION_4},
+ {CSL_DSS_VP_SAFETY_REGION_5, DSS_VP_EVENT_SAFETY_VIOLATION_5},
+ {CSL_DSS_VP_SAFETY_REGION_6, DSS_VP_EVENT_SAFETY_VIOLATION_6},
+ {CSL_DSS_VP_SAFETY_REGION_7, DSS_VP_EVENT_SAFETY_VIOLATION_7}
+};
+
+static const Dss_EventGroupInfo gDss_EventGroupInfo[] = {
+ {DSS_EVENT_GROUP_VP1, CSL_DSS_VP_ID_1, DSS_EVENT_GROUP_TYPE_VP},
+ {DSS_EVENT_GROUP_VP2, CSL_DSS_VP_ID_2, DSS_EVENT_GROUP_TYPE_VP},
+ {DSS_EVENT_GROUP_VP3, CSL_DSS_VP_ID_3, DSS_EVENT_GROUP_TYPE_VP},
+ {DSS_EVENT_GROUP_VP4, CSL_DSS_VP_ID_4, DSS_EVENT_GROUP_TYPE_VP},
+ {DSS_EVENT_GROUP_VID1, CSL_DSS_VID_PIPE_ID_VID1, DSS_EVENT_GROUP_TYPE_PIPE},
+ {DSS_EVENT_GROUP_VIDL1, CSL_DSS_VID_PIPE_ID_VIDL1, DSS_EVENT_GROUP_TYPE_PIPE},
+ {DSS_EVENT_GROUP_VID2, CSL_DSS_VID_PIPE_ID_VID2, DSS_EVENT_GROUP_TYPE_PIPE},
+ {DSS_EVENT_GROUP_VIDL2, CSL_DSS_VID_PIPE_ID_VIDL2, DSS_EVENT_GROUP_TYPE_PIPE}
+};
+
+static const uint32_t gDss_PipeErrEvents[] = {
+ DSS_PIPE_EVENT_BUFF_UNDERFLOW
+};
+
+static const uint32_t gDss_VpFuncEvents[] = {
+ DSS_VP_EVENT_VSYNC,
+ DSS_VP_EVENT_LINE_NUM
+};
+
+static const uint32_t gDss_VpErrEvents[] = {
+ DSS_VP_EVENT_SYNC_LOST
+};
+
+/* Global containing SoC information. */
+static Dss_SocInfo gDss_SocInfo;
+
+/* ========================================================================== */
+/* Function Definitions */
+/* ========================================================================== */
+
+void Dss_fillSocInfo(Dss_RmInfo *rmInfo)
+{
+ uint32_t i = 0U;
+
+ for(i=CSL_DSS_COMM_REG_ID_0; i<CSL_DSS_COMM_REG_ID_MAX; i++)
+ {
+ if(TRUE == rmInfo->isCommRegAvailable[i])
+ {
+ gDss_SocInfo.commRegs[i] =
+ (CSL_dss_commRegs *)gDss_commRegInfo[i].commRegs;
+ }
+ }
+ for(i=CSL_DSS_VID_PIPE_ID_VID1; i<CSL_DSS_VID_PIPE_ID_MAX; i++)
+ {
+ if(TRUE == rmInfo->isPipeAvailable[i])
+ {
+ gDss_SocInfo.pipeRegs[i] =
+ (CSL_dss_pipeRegs *)gDss_pipeRegInfo[i].pipeRegs;
+ }
+ }
+ for(i=CSL_DSS_OVERLAY_ID_1; i<CSL_DSS_OVERLAY_ID_MAX; i++)
+ {
+ if(TRUE == rmInfo->isOverlayAvailable[i])
+ {
+ gDss_SocInfo.overlayRegs[i] =
+ (CSL_dss_overlayRegs *)gDss_overlayRegInfo[i].overlayRegs;
+ }
+ }
+ for(i=CSL_DSS_VP_ID_1; i<CSL_DSS_VP_ID_MAX; i++)
+ {
+ if(TRUE == rmInfo->isPortAvailable[i])
+ {
+ gDss_SocInfo.vpRegs[i] =
+ (CSL_dss_vpRegs *)gDss_vpRegInfo[i].vpRegs;
+ }
+ }
+}
+
+const Dss_SocInfo* Dss_getSocInfo(void)
+{
+ return (const Dss_SocInfo*)(&gDss_SocInfo);
+}
+
+int32_t Dss_convNodetoModule(uint32_t nodeId,
+ uint32_t *moduleId)
+{
+ int32_t retVal = FVID2_EFAIL;
+ uint32_t i;
+ *moduleId = CSL_DSS_MODULE_INVALID;
+
+ for(i=0U;
+ i<sizeof (gDss_DctrlNodeIdInfo) / sizeof (gDss_DctrlNodeIdInfo[0U]);
+ i++)
+ {
+ if(nodeId == gDss_DctrlNodeIdInfo[i].nodeId)
+ {
+ *moduleId = gDss_DctrlNodeIdInfo[i].moduleId;
+ retVal = FVID2_SOK;
+ break;
+ }
+ }
+
+ return (retVal);
+}
+
+int32_t Dss_convModuletoNode(uint32_t *nodeId,
+ uint32_t moduleId,
+ uint32_t nodeType)
+{
+ int32_t retVal = FVID2_EFAIL;
+ uint32_t i;
+ *nodeId = DSS_DCTRL_NODE_INVALID;
+
+ for(i=0U;
+ i<sizeof (gDss_DctrlNodeIdInfo) / sizeof (gDss_DctrlNodeIdInfo[0U]);
+ i++)
+ {
+ if((moduleId == gDss_DctrlNodeIdInfo[i].moduleId) &&
+ (nodeType == gDss_DctrlNodeIdInfo[i].nodeType))
+ {
+ *nodeId = gDss_DctrlNodeIdInfo[i].nodeId;
+ retVal = FVID2_SOK;
+ break;
+ }
+ }
+
+ return (retVal);
+}
+
+void Dss_convEventGrouptoModule(uint32_t eventGroup,
+ uint32_t *moduleId)
+{
+ uint32_t i;
+ *moduleId = CSL_DSS_MODULE_INVALID;
+
+ for(i=0U;
+ i<sizeof (gDss_EventGroupInfo) / sizeof (gDss_EventGroupInfo[0U]);
+ i++)
+ {
+ if(eventGroup == gDss_EventGroupInfo[i].eventGroup)
+ {
+ *moduleId = gDss_EventGroupInfo[i].moduleId;
+ break;
+ }
+ }
+}
+
+void Dss_convModuletoEventGroup(uint32_t *eventGroup,
+ uint32_t moduleId,
+ uint32_t eventGroupType)
+{
+ uint32_t i;
+ *eventGroup = DSS_EVENT_GROUP_INVALID;
+
+ for(i=0U;
+ i<sizeof (gDss_EventGroupInfo) / sizeof (gDss_EventGroupInfo[0U]);
+ i++)
+ {
+ if((moduleId == gDss_EventGroupInfo[i].moduleId) &&
+ (eventGroupType == gDss_EventGroupInfo[i].eventGroupType))
+ {
+ *eventGroup = gDss_EventGroupInfo[i].eventGroup;
+ break;
+ }
+ }
+}
+
+uint32_t Dss_getVpConnId(uint32_t overlayId)
+{
+ uint32_t vpId = CSL_DSS_MODULE_INVALID, i;
+
+ for(i=0U;
+ i<sizeof(gDss_OverlayConnInfo)/sizeof(gDss_OverlayConnInfo[0U]);
+ i++)
+ {
+ if(overlayId == gDss_OverlayConnInfo[i].overlayId)
+ {
+ vpId = gDss_OverlayConnInfo[i].vpId;
+ break;
+ }
+ }
+
+ return vpId;
+}
+
+int32_t Dss_enableL1Event(Dss_EvtMgrInfo *evtMgrInfo,
+ uint32_t dssCommonRegionId,
+ uint32_t eventGroup,
+ uint32_t event,
+ uint32_t eventCnt)
+{
+ int32_t retVal = FVID2_SOK;
+ uint32_t regVal;
+ CSL_dss_commRegs *commRegs;
+ const Dss_SocInfo *socInfo;
+
+ GT_assert(DssTrace, (NULL != evtMgrInfo));
+
+ /* Get common register space */
+ socInfo = Dss_getSocInfo();
+ commRegs = socInfo->commRegs[dssCommonRegionId];
+ GT_assert(DssTrace, (NULL != commRegs));
+
+ if(DSS_EVENT_GROUP_VP1 == eventGroup)
+ {
+ /* Clear the status of interrupt */
+ regVal = CSL_REG32_RD(&commRegs->VP_IRQSTATUS_0);
+ regVal |= eventGroup;
+ CSL_REG32_WR(&commRegs->VP_IRQSTATUS_0, regVal);
+
+ /* Enable the interrupts at the VP1 level */
+ regVal = CSL_REG32_RD(&commRegs->VP_IRQENABLE_0);
+ regVal |= event;
+ CSL_REG32_WR(&commRegs->VP_IRQENABLE_0, regVal);
+
+ /* Store the register address in evtMgrInfo instance */
+ evtMgrInfo->l1EnableReg[eventCnt] = &commRegs->VP_IRQENABLE_0;
+ evtMgrInfo->l1StatusReg[eventCnt] = &commRegs->VP_IRQSTATUS_0;
+ evtMgrInfo->l1Mask[eventCnt] = event;
+ evtMgrInfo->allEvents[eventCnt] = event;
+ }
+ else if(DSS_EVENT_GROUP_VP2 == eventGroup)
+ {
+ /* Clear the status of interrupt */
+ regVal = CSL_REG32_RD(&commRegs->VP_IRQSTATUS_1);
+ regVal |= eventGroup;
+ CSL_REG32_WR(&commRegs->VP_IRQSTATUS_1, regVal);
+
+ /* Enable the interrupts at the VP2 level */
+ regVal = CSL_REG32_RD(&commRegs->VP_IRQENABLE_1);
+ regVal |= event;
+ CSL_REG32_WR(&commRegs->VP_IRQENABLE_1, regVal);
+
+ /* Store the register address in evtMgrInfo instance */
+ evtMgrInfo->l1EnableReg[eventCnt] = &commRegs->VP_IRQENABLE_1;
+ evtMgrInfo->l1StatusReg[eventCnt] = &commRegs->VP_IRQSTATUS_1;
+ evtMgrInfo->l1Mask[eventCnt] = event;
+ evtMgrInfo->allEvents[eventCnt] = event;
+ }
+ else if(DSS_EVENT_GROUP_VP3 == eventGroup)
+ {
+ /* Clear the status of interrupt */
+ regVal = CSL_REG32_RD(&commRegs->VP_IRQSTATUS_2);
+ regVal |= eventGroup;
+ CSL_REG32_WR(&commRegs->VP_IRQSTATUS_2, regVal);
+
+ /* Enable the interrupts at the VP3 level */
+ regVal = CSL_REG32_RD(&commRegs->VP_IRQENABLE_2);
+ regVal |= event;
+ CSL_REG32_WR(&commRegs->VP_IRQENABLE_2, regVal);
+
+ /* Store the register address in evtMgrInfo instance */
+ evtMgrInfo->l1EnableReg[eventCnt] = &commRegs->VP_IRQENABLE_2;
+ evtMgrInfo->l1StatusReg[eventCnt] = &commRegs->VP_IRQSTATUS_2;
+ evtMgrInfo->l1Mask[eventCnt] = event;
+ evtMgrInfo->allEvents[eventCnt] = event;
+ }
+ else if(DSS_EVENT_GROUP_VP4 == eventGroup)
+ {
+ /* Clear the status of interrupt */
+ regVal = CSL_REG32_RD(&commRegs->VP_IRQSTATUS_3);
+ regVal |= eventGroup;
+ CSL_REG32_WR(&commRegs->VP_IRQSTATUS_3, regVal);
+
+ /* Enable the interrupts at the VP4 level */
+ regVal = CSL_REG32_RD(&commRegs->VP_IRQENABLE_3);
+ regVal |= event;
+ CSL_REG32_WR(&commRegs->VP_IRQENABLE_3, regVal);
+
+ /* Store the register address in evtMgrInfo instance */
+ evtMgrInfo->l1EnableReg[eventCnt] = &commRegs->VP_IRQENABLE_3;
+ evtMgrInfo->l1StatusReg[eventCnt] = &commRegs->VP_IRQSTATUS_3;
+ evtMgrInfo->l1Mask[eventCnt] = event;
+ evtMgrInfo->allEvents[eventCnt] = event;
+ }
+ else if(DSS_EVENT_GROUP_VID1 == eventGroup)
+ {
+ /* Clear the status of interrupt */
+ regVal = CSL_REG32_RD(&commRegs->VID_IRQSTATUS_0);
+ regVal |= eventGroup;
+ CSL_REG32_WR(&commRegs->VID_IRQSTATUS_0, regVal);
+
+ /* Enable the interrupts at the VID1 Pipe level */
+ regVal = CSL_REG32_RD(&commRegs->VID_IRQENABLE_0);
+ regVal |= event;
+ CSL_REG32_WR(&commRegs->VID_IRQENABLE_0, regVal);
+
+ /* Store the register address in evtMgrInfo instance */
+ evtMgrInfo->l1EnableReg[eventCnt] = &commRegs->VID_IRQENABLE_0;
+ evtMgrInfo->l1StatusReg[eventCnt] = &commRegs->VID_IRQSTATUS_0;
+ evtMgrInfo->l1Mask[eventCnt] = event;
+ evtMgrInfo->allEvents[eventCnt] = event;
+ }
+ else if(DSS_EVENT_GROUP_VIDL1 == eventGroup)
+ {
+ /* Clear the status of interrupt */
+ regVal = CSL_REG32_RD(&commRegs->VID_IRQSTATUS_1);
+ regVal |= eventGroup;
+ CSL_REG32_WR(&commRegs->VID_IRQSTATUS_1, regVal);
+
+ /* Enable the interrupts at the VIDL1 Pipe level */
+ regVal = CSL_REG32_RD(&commRegs->VID_IRQENABLE_1);
+ regVal |= event;
+ CSL_REG32_WR(&commRegs->VID_IRQENABLE_1, regVal);
+
+ /* Store the register address in evtMgrInfo instance */
+ evtMgrInfo->l1EnableReg[eventCnt] = &commRegs->VID_IRQENABLE_1;
+ evtMgrInfo->l1StatusReg[eventCnt] = &commRegs->VID_IRQSTATUS_1;
+ evtMgrInfo->l1Mask[eventCnt] = event;
+ evtMgrInfo->allEvents[eventCnt] = event;
+ }
+ else if(DSS_EVENT_GROUP_VID2 == eventGroup)
+ {
+ /* Clear the status of interrupt */
+ regVal = CSL_REG32_RD(&commRegs->VID_IRQSTATUS_2);
+ regVal |= eventGroup;
+ CSL_REG32_WR(&commRegs->VID_IRQSTATUS_2, regVal);
+
+ /* Enable the interrupts at the VID2 Pipe level */
+ regVal = CSL_REG32_RD(&commRegs->VID_IRQENABLE_2);
+ regVal |= event;
+ CSL_REG32_WR(&commRegs->VID_IRQENABLE_2, regVal);
+
+ /* Store the register address in evtMgrInfo instance */
+ evtMgrInfo->l1EnableReg[eventCnt] = &commRegs->VID_IRQENABLE_2;
+ evtMgrInfo->l1StatusReg[eventCnt] = &commRegs->VID_IRQSTATUS_2;
+ evtMgrInfo->l1Mask[eventCnt] = event;
+ evtMgrInfo->allEvents[eventCnt] = event;
+ }
+ else if(DSS_EVENT_GROUP_VIDL2 == eventGroup)
+ {
+ /* Clear the status of interrupt */
+ regVal = CSL_REG32_RD(&commRegs->VID_IRQSTATUS_3);
+ regVal |= eventGroup;
+ CSL_REG32_WR(&commRegs->VID_IRQSTATUS_3, regVal);
+
+ /* Enable the interrupts at the VIDL2 Pipe level */
+ regVal = CSL_REG32_RD(&commRegs->VID_IRQENABLE_3);
+ regVal |= event;
+ CSL_REG32_WR(&commRegs->VID_IRQENABLE_3, regVal);
+
+ /* Store the register address in evtMgrInfo instance */
+ evtMgrInfo->l1EnableReg[eventCnt] = &commRegs->VID_IRQENABLE_3;
+ evtMgrInfo->l1StatusReg[eventCnt] = &commRegs->VID_IRQSTATUS_3;
+ evtMgrInfo->l1Mask[eventCnt] = event;
+ evtMgrInfo->allEvents[eventCnt] = event;
+ }
+ else
+ {
+ GT_assert(DssTrace, FALSE);
+ retVal = FVID2_EBADARGS;
+ }
+
+ return retVal;
+}
+
+void Dss_getEnabledVpFuncEvents(uint32_t events[DSS_EVT_MGR_MAX_CLIENT_EVENTS],
+ uint32_t *numEvts)
+{
+ uint32_t i;
+ *numEvts = sizeof(gDss_VpFuncEvents)/sizeof(uint32_t);
+ for(i=0U; i<*numEvts; i++)
+ {
+ events[i] = gDss_VpFuncEvents[i];
+ }
+}
+
+void Dss_getEnabledVpErrEvents(uint32_t events[DSS_EVT_MGR_MAX_CLIENT_EVENTS],
+ uint32_t *numEvts)
+{
+ uint32_t i;
+ *numEvts = sizeof(gDss_VpErrEvents)/sizeof(uint32_t);
+ for(i=0U; i<*numEvts; i++)
+ {
+ events[i] = gDss_VpErrEvents[i];
+ }
+}
+
+void Dss_getEnabledPipeErrEvents(uint32_t events[DSS_EVT_MGR_MAX_CLIENT_EVENTS],
+ uint32_t *numEvts)
+{
+ uint32_t i;
+ *numEvts = sizeof(gDss_PipeErrEvents)/sizeof(uint32_t);
+ for(i=0U; i<*numEvts; i++)
+ {
+ events[i] = gDss_PipeErrEvents[i];
+ }
+}
+
+uint32_t Dss_dctrlIsPipeNode(uint32_t nodeId)
+{
+ uint32_t isPipeNode = FALSE;
+
+ if((DSS_DCTRL_NODE_VID1 == nodeId) ||
+ (DSS_DCTRL_NODE_VIDL1 == nodeId) ||
+ (DSS_DCTRL_NODE_VID2 == nodeId) ||
+ (DSS_DCTRL_NODE_VIDL2 == nodeId))
+ {
+ isPipeNode = TRUE;
+ }
+
+ return (isPipeNode);
+}
+
+uint32_t Dss_dctrlIsValidNode(uint32_t nodeId)
+{
+ uint32_t i, isValidNode = FALSE, graphNodeInfoSize = 0U;
+ const Fvid2_GraphNodeInfo *graphNodeInfo;
+
+ graphNodeInfo = Dss_dctrlGetDefaultNodeInfo(&graphNodeInfoSize);
+
+ for(i=1U; i<graphNodeInfoSize; i++)
+ {
+ if(nodeId == graphNodeInfo[i].nodeId)
+ {
+ isValidNode = TRUE;
+ break;
+ }
+ }
+
+ return (isValidNode);
+}
+
+uint32_t Dss_dctrlIsVideoMuxNeeded(uint32_t vpNodeId,
+ uint32_t outNodeId)
+{
+ uint32_t isMuxNeeded = FALSE;
+
+ if(((DSS_DCTRL_NODE_DPI_DPI0 == outNodeId) ||
+ (DSS_DCTRL_NODE_DPI_DPI1 == outNodeId)) &&
+ ((DSS_DCTRL_NODE_VP2 == vpNodeId) ||
+ (DSS_DCTRL_NODE_VP4 == vpNodeId)))
+ {
+ isMuxNeeded = TRUE;
+ }
+
+ return isMuxNeeded;
+}
+
+int32_t Dss_dctrlProgramVideoMux(uint32_t vpNodeId,
+ uint32_t outNodeId)
+{
+ int32_t retVal = FVID2_SOK;
+ uint32_t vpId, outId;
+ const Dss_SocInfo *socInfo;
+ CSL_dss_commRegs *commRegs;
+
+ /* Get common registers */
+ socInfo = Dss_getSocInfo();
+ commRegs = socInfo->commRegs[CSL_DSS_COMM_REG_ID_0];
+ GT_assert(DssTrace, (NULL != commRegs));
+ /* Get video port id */
+ retVal = Dss_convNodetoModule(vpNodeId, &vpId);
+ GT_assert(DssTrace, (CSL_DSS_MODULE_INVALID != vpId));
+ /* Get output module id */
+ retVal = Dss_convNodetoModule(outNodeId, &outId);
+ GT_assert(DssTrace, (CSL_DSS_MODULE_INVALID != outId));
+ retVal = CSL_dssConnectVpToDpi(commRegs, vpId, outId);
+
+ return (retVal);
+}
+
+uint32_t Dss_getEvtMgrFuncIntrId(void)
+{
+ uint32_t evtMgrId;
+
+ evtMgrId = DSS_EVT_MGR_INST_ID_FUNC;
+
+ return evtMgrId;
+}
+
+uint32_t Dss_getEvtMgrSafetyIntrId(void)
+{
+ uint32_t evtMgrId;
+
+ evtMgrId = DSS_EVT_MGR_INST_ID_SAFETY;
+
+ return evtMgrId;
+}
+
+uint32_t Dss_getEvtMgrSecurityIntrId(void)
+{
+ uint32_t evtMgrId;
+
+ evtMgrId = DSS_EVT_MGR_INST_ID_SECURITY;
+
+ return evtMgrId;
+}
+
+int32_t Dss_fillEvtMgrInitInfo(Dss_EvtMgrInitParams *evtMgrParams,
+ Dss_IrqParams *irqParams)
+{
+ int32_t retVal = FVID2_SOK;
+
+ evtMgrParams->dssCommonRegionId = irqParams->dssCommonRegionId;
+ evtMgrParams->numIrq = irqParams->numValidIrq;
+ evtMgrParams->irqNum[0U] = irqParams->irqNum[DSS_EVT_MGR_INST_ID_FUNC];
+ evtMgrParams->instId[0U] = DSS_EVT_MGR_INST_ID_FUNC;
+ evtMgrParams->irqNum[1U] = irqParams->irqNum[DSS_EVT_MGR_INST_ID_SAFETY];
+ evtMgrParams->instId[1U] = DSS_EVT_MGR_INST_ID_SAFETY;
+ evtMgrParams->irqNum[2U] = irqParams->irqNum[DSS_EVT_MGR_INST_ID_SECURITY];
+ evtMgrParams->instId[2U] = DSS_EVT_MGR_INST_ID_SECURITY;
+
+ return retVal;
+}
+
+uint32_t Dss_dctrlGetVpSafetyRegionId(uint32_t evtId)
+{
+ uint32_t i;
+ uint32_t regionId = CSL_DSS_VP_SAFETY_REGION_INVALID;
+
+ for(i=0U;
+ i<sizeof (gDss_VpSafetyRegionIdInfo) /
+ sizeof (gDss_VpSafetyRegionIdInfo[0U]);
+ i++)
+ {
+ if(evtId == gDss_VpSafetyRegionIdInfo[i].regionErrEvt)
+ {
+ regionId = gDss_VpSafetyRegionIdInfo[i].regionId;
+ break;
+ }
+ }
+
+ return (regionId);
+}
+
+uint32_t Dss_dctrlIsSafetyEvent(uint32_t evtId)
+{
+ uint32_t retVal = FALSE;
+ if((evtId >= DSS_VP_EVENT_SAFETY_VIOLATION_0) &&
+ (evtId <= DSS_VP_EVENT_SAFETY_VIOLATION_7))
+ {
+ retVal = TRUE;
+ }
+ return retVal;
+}
+
+
+uint32_t Dss_dctrlGetVpSafetyEvtId(uint32_t regionId)
+{
+ uint32_t i;
+ uint32_t evtId = DSS_VP_EVENT_INVALID;
+
+ for(i=0U;
+ i<sizeof (gDss_VpSafetyRegionIdInfo) /
+ sizeof (gDss_VpSafetyRegionIdInfo[0U]);
+ i++)
+ {
+ if(regionId == gDss_VpSafetyRegionIdInfo[i].regionId)
+ {
+ evtId = gDss_VpSafetyRegionIdInfo[i].regionErrEvt;
+ break;
+ }
+ }
+
+ return (evtId);
+}
diff --git a/packages/ti/drv/dss/soc/V1/dss_soc.h b/packages/ti/drv/dss/soc/V1/dss_soc.h
--- /dev/null
@@ -0,0 +1,501 @@
+/*
+ * Copyright (c) Texas Instruments Incorporated 2018
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * \ingroup DRV_DSS_MODULE
+ * \defgroup DRV_DSS_SOC_MODULE DSS SoC Config
+ * This is DSS documentation specific to J7 SoC
+ *
+ * @{
+ */
+
+/**
+ * \file dss_soc.h
+ *
+ * \brief DSS Driver J7 SOC specific file.
+ */
+
+#ifndef DSS_SOC_H_
+#define DSS_SOC_H_
+
+/* ========================================================================== */
+/* Include Files */
+/* ========================================================================== */
+
+/* None */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* ========================================================================== */
+/* Macros & Typedefs */
+/* ========================================================================== */
+
+/**
+ * \brief DP HPD callback function prototype.
+ *
+ * \param hpdState [OUT] HPD state TRUE / FALSE.
+ * \param appData [OUT] Application's private data.
+ *
+ * \return None.
+ */
+typedef void (*Dss_DctrlDpHpdCbFxn)(uint32_t hpdState, void *appData);
+
+/*
+ * Macros for different driver instance numbers to be passed as instance ID
+ * at the time of driver create.
+ * Note: These are read only macros. Don't modify the value of these macros.
+ */
+
+/**
+ * \name DSS DCTRL Instance IDs
+ *
+ * @{
+ */
+
+/** \brief Display controller instance 0. */
+#define DSS_DCTRL_INST_0 (0U)
+
+/** \brief Maximum number of display driver instances */
+#define DSS_DCTRL_INST_MAX (1U)
+/* @} */
+
+/**
+ * \name DSS Display Instance IDs
+ *
+ * @{
+ */
+
+/** \brief Video 1 Pipeline display driver instance number. */
+#define DSS_DISP_INST_VID1 (CSL_DSS_VID_PIPE_ID_VID1)
+
+/** \brief Video Lite 1 Pipeline display driver instance number. */
+#define DSS_DISP_INST_VIDL1 (CSL_DSS_VID_PIPE_ID_VIDL1)
+
+/** \brief Video 2 Pipeline display driver instance number. */
+#define DSS_DISP_INST_VID2 (CSL_DSS_VID_PIPE_ID_VID2)
+
+/** \brief Video Lite 2 Pipeline display driver instance number. */
+#define DSS_DISP_INST_VIDL2 (CSL_DSS_VID_PIPE_ID_VIDL2)
+
+/** \brief Maximum number of display driver instances */
+#define DSS_DISP_INST_MAX (CSL_DSS_VID_PIPE_ID_MAX)
+/* @} */
+
+/**
+ * \anchor Dss_DctrlNodeType
+ * \name DSS DCTRL Node type
+ *
+ * Node types that are used by the set path to connect different modules and
+ * create a graph
+ *
+ * @{
+ */
+#define DSS_DCTRL_NODE_TYPE_INVALID ((uint32_t) 0x0U)
+#define DSS_DCTRL_NODE_TYPE_PIPE ((uint32_t) 0x1U)
+#define DSS_DCTRL_NODE_TYPE_OVERLAY ((uint32_t) 0x2U)
+#define DSS_DCTRL_NODE_TYPE_VP ((uint32_t) 0x3U)
+#define DSS_DCTRL_NODE_TYPE_OUTPUT ((uint32_t) 0x4U)
+/* @} */
+
+/**
+ * \anchor Dss_DctrlNodeId
+ * \name DSS DCTRL Node Id
+ *
+ * Node ids that are used by the set path to connect different modules and
+ * create a graph
+ *
+ * @{
+ */
+#define DSS_DCTRL_NODE_INVALID (0x0U)
+#define DSS_DCTRL_NODE_VID1 (0x1U)
+#define DSS_DCTRL_NODE_VIDL1 (0x2U)
+#define DSS_DCTRL_NODE_VID2 (0x3U)
+#define DSS_DCTRL_NODE_VIDL2 (0x4U)
+#define DSS_DCTRL_NODE_OVERLAY1 (0x5U)
+#define DSS_DCTRL_NODE_OVERLAY2 (0x6U)
+#define DSS_DCTRL_NODE_OVERLAY3 (0x7U)
+#define DSS_DCTRL_NODE_OVERLAY4 (0x8U)
+#define DSS_DCTRL_NODE_VP1 (0x9U)
+#define DSS_DCTRL_NODE_VP2 (0xAU)
+#define DSS_DCTRL_NODE_VP3 (0xBU)
+#define DSS_DCTRL_NODE_VP4 (0xCU)
+#define DSS_DCTRL_NODE_DPI_DPI0 (0xDU)
+#define DSS_DCTRL_NODE_DPI_DPI1 (0xEU)
+#define DSS_DCTRL_NODE_EDP_DPI0 (0xFU)
+#define DSS_DCTRL_NODE_EDP_DPI1 (0x10U)
+#define DSS_DCTRL_NODE_EDP_DPI2 (0x11U)
+#define DSS_DCTRL_NODE_EDP_DPI3 (0x12U)
+#define DSS_DCTRL_NODE_DSI (0x13U)
+#define DSS_DCTRL_NODE_DISCSYNC0 (0x14U)
+#define DSS_DCTRL_NODE_DISCSYNC1 (0x15U)
+/* @} */
+
+/** \brief Defines maximum number of nodes for allocation including invalid node
+ */
+#define DSS_DCTRL_MAX_NODES (22U)
+
+/** \brief Defines maximum number of edges for allocation. This is derived by
+ * looking at all possible DSS connections in the SoC.
+ */
+#define DSS_DCTRL_MAX_EDGES (32U)
+
+/**< \brief DSS Functional Interrupt Number for R5 */
+#define DSS_FUNC_IRQ_DEFAULT_NUM (52U)
+
+/**< \brief DSS Safety Interrupt Number for R5 */
+#define DSS_SAFE_IRQ_DEFAULT_NUM (54U)
+
+/**< \brief DSS Functional Interrupt Number for R5 */
+#define DSS_SECURE_IRQ_DEFAULT_NUM (56U)
+
+/**
+ * \anchor Dss_EvtMgrInstId
+ * \name Instance Ids for DSS Event Manager.
+ *
+ * @{
+ */
+/**< \brief Instance Id for functional interrupts */
+#define DSS_EVT_MGR_INST_ID_FUNC ((uint32_t) 0x00U)
+/**< \brief Instance Id for safety interrupts */
+#define DSS_EVT_MGR_INST_ID_SAFETY ((uint32_t) 0x01U)
+/**< \brief Instance Id for security interrupts */
+#define DSS_EVT_MGR_INST_ID_SECURITY ((uint32_t) 0x02U)
+/**< \brief Max Instance Id */
+#define DSS_EVT_MGR_INST_ID_MAX ((uint32_t) 0x03U)
+/**< \brief Invalid Instance Id */
+#define DSS_EVT_MGR_INST_ID_INVALID ((uint32_t) 0xFFU)
+/* @} */
+
+/*
+ * SOC specific IOCTLs.
+ */
+
+/**
+ * \addtogroup DRV_DSS_DCTRL_IOCTL
+ * @{
+ */
+/**
+ * \brief IOCTL to process Display port HPD.
+ *
+ * This IOCTL can be used to process the display port HPD interrupt.
+ * Note: This IOCTL is supported only for J721E SoC.
+ *
+ * \param cmdArgs [IN] Pointer of type uint32_t.
+ * Supported values: TRUE/FALSE
+ * \param cmdArgsStatus [OUT] NULL
+ *
+ * \return FVID2_SOK if successful, else suitable error code
+ *
+ */
+#define IOCTL_DSS_DCTRL_PROCESS_DP_HPD (DSS_DCTRL_SOC_IOCTL_BASE + 0x01U)
+
+/**
+ * \brief IOCTL to register Display port HPD callback.
+ *
+ * This IOCTL can be used to register the callback for
+ * display port HPD interrupt. Refer #Dss_DctrlDpHpdCbParams
+ * for details.
+ * Note: This IOCTL is supported only for J721E SoC.
+ *
+ * \param cmdArgs [IN] Pointer of type #Dss_DctrlDpHpdCbParams.
+ * \param cmdArgsStatus [OUT] NULL
+ *
+ * \return FVID2_SOK if successful, else suitable error code
+ *
+ */
+#define IOCTL_DSS_DCTRL_REGISTER_DP_HPD_CB (DSS_DCTRL_SOC_IOCTL_BASE + 0x02U)
+/* @} */
+
+/* ========================================================================== */
+/* Structure Declarations */
+/* ========================================================================== */
+
+/**
+ * \brief Structure containing DSS interrupt information. Events should be
+ * enabled only for available Video Ports and Video Pipes
+ */
+typedef struct
+{
+ uint32_t dssCommonRegionId;
+ /**< DSS Common Region Id. There are multiple common regions in DSS hardware
+ * each having IRQ aggregation registers and IRQ generator. This enables
+ * fully independent monitoring/control of the interrupt events by
+ * different hosts. User can decide which common region to use. By default
+ * region 0 will be used. Refer \ref CSL_DssCommRegId for values
+ */
+ uint32_t numValidIrq;
+ /**< Number of valid DSS interrupts. There can be multiple interrupts in DSS
+ * hardware. This specifies number of valid IRQs in below array.
+ */
+ uint32_t irqNum[DSS_EVT_MGR_INST_ID_MAX];
+ /**< DSS interrupt numbers. This will enable to configure different interrupt
+ * numbers. This will be initialized to default values as specified in the
+ * DssInitParams_init function. User may override these values if allowed.
+ *
+ * Note: Driver will only register for the specified interrupt numbers.
+ * If needed the corresponding crossbar mapping for the device interrupt
+ * should be done by the application.
+ */
+} Dss_IrqParams;
+
+/**
+ * \brief Structure containing resources manager information. This enables
+ * display sharing between two different softwares.
+ */
+typedef struct
+{
+ uint32_t isCommRegAvailable[CSL_DSS_COMM_REG_ID_MAX];
+ /**< Ids for available common regions */
+ uint32_t isPipeAvailable[CSL_DSS_VID_PIPE_ID_MAX];
+ /**< Ids for available video pipes */
+ uint32_t isOverlayAvailable[CSL_DSS_OVERLAY_ID_MAX];
+ /**< Ids for available overlays */
+ uint32_t isPortAvailable[CSL_DSS_VP_ID_MAX];
+ /**< Ids for available video ports */
+} Dss_RmInfo;
+
+/**
+ * \brief Structure containing Display Port init parameters
+ */
+typedef struct
+{
+ uint32_t isAvailable;
+ /**< Flag to indicate whether eDP module is available */
+ uint32_t isHpdSupported;
+ /**< Flag to indicate whether driver should detect and
+ * handle hot-plug interrupts
+ */
+} Dss_DpInitParams;
+
+/**
+ * \brief DSS SOC parameters.
+ */
+typedef struct
+{
+ Dss_IrqParams irqParams;
+ /**< DSS interrupt information */
+ Dss_RmInfo rmInfo;
+ /**< DSS resource information */
+ Dss_DpInitParams dpInitParams;
+ /**< DSS DP init information */
+} Dss_SocParams;
+
+/**
+ * \brief DSS DP HPD Callback parameters
+ */
+typedef struct
+{
+ Dss_DctrlDpHpdCbFxn hpdCbFxn;
+ /**< HPD callback function. Refer #Dss_DctrlDpHpdCbFxn */
+ void *appData;
+ /**< Application data */
+} Dss_DctrlDpHpdCbParams;
+
+/* ========================================================================== */
+/* Internal/Private Function Declarations */
+/* ========================================================================== */
+
+/**
+ * \brief Check if the display driver instance is of type Video pipeline.
+ *
+ * \param instId [IN]Driver Instance Id.
+ *
+ * \return TRUE if instance is Video pipeline else returns FALSE.
+ */
+static inline uint32_t Dss_dispIsVidInst(uint32_t instId);
+
+/**
+ * \brief Check if the display driver instance is of type Video lite pipeline.
+ *
+ * \param instId [IN]Driver Instance Id.
+ *
+ * \return TRUE if instance is Video lite pipeline else returns FALSE.
+ */
+static inline uint32_t Dss_dispIsVidLInst(uint32_t instId);
+
+/**
+ * \brief Dss_IrqParams structure init function.
+ *
+ * \param irqParams Pointer to #Dss_IrqParams structure.
+ *
+ * \return None
+ */
+static inline void Dss_irqParamsInit(Dss_IrqParams *irqParams);
+
+/**
+ * \brief Dss_RmInfo structure init function.
+ *
+ * \param rmInfo Pointer to #Dss_RmInfo structure.
+ *
+ * \return None
+ */
+static inline void Dss_rmInfoInit(Dss_RmInfo *rmInfo);
+
+/**
+ * \brief Dss_DpInitParams structure init function.
+ *
+ * \param dpInitParams Pointer to #Dss_DpInitParams structure.
+ *
+ * \return None
+ */
+static inline void Dss_dpInitParamsInit(Dss_DpInitParams *dpInitParams);
+
+/**
+ * \brief Dss_SocParams structure init function.
+ *
+ * \param socParams Pointer to #Dss_SocParams structure.
+ *
+ * \return None
+ */
+static inline void Dss_socParamsInit(Dss_SocParams *socParams);
+
+/**
+ * \brief Dss_DctrlDpHpdCbParams structure init function.
+ *
+ * \param cbParams Pointer to #Dss_DctrlDpHpdCbParams structure.
+ *
+ * \return None
+ */
+static inline void Dss_dctrlDpHpdCbParamsInit(Dss_DctrlDpHpdCbParams *cbParams);
+
+/* ========================================================================== */
+/* Function Declarations */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/* Static Function Definitions */
+/* ========================================================================== */
+
+static inline uint32_t Dss_dispIsVidInst(uint32_t instId)
+{
+ uint32_t isVidInst = FALSE;
+
+ if((DSS_DISP_INST_VID1 == instId) ||
+ (DSS_DISP_INST_VID2 == instId))
+ {
+ isVidInst = TRUE;
+ }
+
+ return (isVidInst);
+}
+
+static inline uint32_t Dss_dispIsVidLInst(uint32_t instId)
+{
+ uint32_t isVidLInst = FALSE;
+
+ if((DSS_DISP_INST_VIDL1 == instId) ||
+ (DSS_DISP_INST_VIDL2 == instId))
+ {
+ isVidLInst = TRUE;
+ }
+
+ return (isVidLInst);
+}
+
+static inline void Dss_irqParamsInit(Dss_IrqParams *irqParams)
+{
+ if(NULL != irqParams)
+ {
+ irqParams->dssCommonRegionId = CSL_DSS_COMM_REG_ID_0;
+ irqParams->numValidIrq = DSS_EVT_MGR_INST_ID_MAX;
+ irqParams->irqNum[DSS_EVT_MGR_INST_ID_FUNC] = DSS_FUNC_IRQ_DEFAULT_NUM;
+ irqParams->irqNum[DSS_EVT_MGR_INST_ID_SAFETY] =
+ DSS_SAFE_IRQ_DEFAULT_NUM;
+ irqParams->irqNum[DSS_EVT_MGR_INST_ID_SECURITY] =
+ DSS_SECURE_IRQ_DEFAULT_NUM;
+ }
+}
+
+static inline void Dss_rmInfoInit(Dss_RmInfo *rmInfo)
+{
+ uint32_t i = 0U;
+ if(NULL != rmInfo)
+ {
+ for(i=CSL_DSS_COMM_REG_ID_0; i<CSL_DSS_COMM_REG_ID_MAX; i++)
+ {
+ rmInfo->isCommRegAvailable[i] = TRUE;
+ }
+ for(i=CSL_DSS_VID_PIPE_ID_VID1; i<CSL_DSS_VID_PIPE_ID_MAX; i++)
+ {
+ rmInfo->isPipeAvailable[i] = TRUE;
+ }
+ for(i=CSL_DSS_OVERLAY_ID_1; i<CSL_DSS_OVERLAY_ID_MAX; i++)
+ {
+ rmInfo->isOverlayAvailable[i] = TRUE;
+ }
+ for(i=CSL_DSS_VP_ID_1; i<CSL_DSS_VP_ID_MAX; i++)
+ {
+ rmInfo->isPortAvailable[i] = TRUE;
+ }
+ }
+}
+
+static inline void Dss_dpInitParamsInit(Dss_DpInitParams *dpInitParams)
+{
+ if(NULL != dpInitParams)
+ {
+ dpInitParams->isAvailable = TRUE;
+ dpInitParams->isHpdSupported = TRUE;
+ }
+}
+
+static inline void Dss_socParamsInit(Dss_SocParams *socParams)
+{
+ if(NULL != socParams)
+ {
+ Dss_irqParamsInit(&(socParams->irqParams));
+ Dss_rmInfoInit(&(socParams->rmInfo));
+ Dss_dpInitParamsInit(&(socParams->dpInitParams));
+ }
+}
+
+static inline void Dss_dctrlDpHpdCbParamsInit(Dss_DctrlDpHpdCbParams *cbParams)
+{
+ if(NULL != cbParams)
+ {
+ cbParams->hpdCbFxn = NULL;
+ cbParams->appData = NULL;
+ }
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #ifndef DSS_SOC_V1_H_ */
+
+/* @} */
diff --git a/packages/ti/drv/dss/soc/V1/dss_soc_fw.c b/packages/ti/drv/dss/soc/V1/dss_soc_fw.c
--- /dev/null
@@ -0,0 +1,32849 @@
+/*
+ * Copyright (c) Texas Instruments Incorporated 2018
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * \file dss_soc_fw.c
+ *
+ * \brief File containing the firmware for eDP.
+ *
+ */
+
+/* ========================================================================== */
+/* Include Files */
+/* ========================================================================== */
+
+#include <ti/drv/dss/dss.h>
+#include "dss_soc_priv.h"
+
+/* ========================================================================== */
+/* Macros & Typedefs */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/* Structure Declarations */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/* Function Declarations */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/* Global Variables */
+/* ========================================================================== */
+
+
+uint8_t gDctrlDpIram[DCTRL_DP_IMEM_SIZE] = {
+ 0x06, 0x07, 0x00, 0x00,
+ 0x21, 0x22, 0x22, 0x22,
+ 0x00, 0x00, 0x00, 0xe0,
+ 0x54, 0x00, 0x00, 0x30,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x3c, 0x98, 0x00, 0x30,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x0c, 0x00, 0x00, 0xe4,
+ 0x13, 0x1c, 0x53, 0x30,
+ 0x63, 0x13, 0x20, 0x61,
+ 0x00, 0x21, 0xf5, 0xff,
+ 0x51, 0xf6, 0xff, 0x61,
+ 0xf6, 0xff, 0x0c, 0x03,
+ 0x7d, 0x02, 0x50, 0x66,
+ 0x10, 0xc6, 0x04, 0x00,
+ 0x40, 0x63, 0x50, 0x00,
+ 0x20, 0x00, 0x3d, 0xf0,
+ 0xf0, 0x20, 0x00, 0x50,
+ 0x33, 0xc0, 0xb6, 0xb3,
+ 0x14, 0x70, 0x74, 0x41,
+ 0x70, 0x40, 0x34, 0x67,
+ 0x13, 0xe5, 0x40, 0x63,
+ 0x50, 0x50, 0x33, 0xc0,
+ 0xf6, 0xb3, 0xed, 0x00,
+ 0x20, 0x00, 0x51, 0xe8,
+ 0xff, 0x0c, 0x03, 0x7d,
+ 0x02, 0x70, 0x40, 0x34,
+ 0x40, 0xe3, 0x50, 0x50,
+ 0x33, 0xc0, 0x70, 0x74,
+ 0x41, 0xf6, 0xb3, 0xf0,
+ 0x30, 0x20, 0x00, 0x21,
+ 0xe4, 0xff, 0x16, 0x72,
+ 0x00, 0xc0, 0x02, 0x00,
+ 0x0c, 0x00, 0x56, 0xf2,
+ 0xff, 0x0c, 0x11, 0x10,
+ 0x49, 0x13, 0x00, 0x48,
+ 0x13, 0x10, 0x20, 0x00,
+ 0x0c, 0x00, 0x41, 0xde,
+ 0xff, 0x3d, 0xf0, 0x40,
+ 0x6c, 0x13, 0x85, 0xee,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x6c, 0x61, 0xa0,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
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+ 0x70, 0x54, 0xff, 0x3f,
+ 0x98, 0x0c, 0xff, 0x3f,
+ 0xf0, 0x55, 0xff, 0x3f,
+ 0x3c, 0x1d, 0xff, 0x3f,
+ 0x65, 0x58, 0xff, 0x3f,
+ 0xd8, 0x40, 0x00, 0x00,
+ 0xff, 0xff, 0xff, 0xef,
+ 0xe4, 0x40, 0x00, 0x00,
+ 0xa4, 0x40, 0x00, 0x00,
+ 0x00, 0x00, 0x02, 0x00,
+ 0xd0, 0x2e, 0xff, 0x3f,
+ 0xc4, 0x2c, 0xff, 0x3f,
+ 0xb0, 0x19, 0xff, 0x3f,
+ 0x38, 0x53, 0xff, 0x3f,
+ 0x50, 0x01, 0xff, 0x3f,
+ 0xe8, 0x40, 0x00, 0x00,
+ 0x04, 0x40, 0x00, 0x00,
+ 0x24, 0x51, 0xff, 0x3f,
+ 0xa0, 0x52, 0xff, 0x3f,
+ 0x70, 0x58, 0xff, 0x3f,
+ 0x50, 0x53, 0xff, 0x3f,
+ 0xa0, 0x40, 0x00, 0x00,
+ 0x9c, 0x52, 0xff, 0x3f,
+ 0xbc, 0x40, 0x00, 0x00,
+ 0x98, 0x52, 0xff, 0x3f,
+ 0xc0, 0x40, 0x00, 0x00,
+ 0xc4, 0x52, 0xff, 0x3f,
+ 0xdc, 0x40, 0x00, 0x00,
+ 0xc0, 0x52, 0xff, 0x3f,
+ 0xe0, 0x40, 0x00, 0x00,
+ 0xb4, 0x40, 0x00, 0x00,
+ 0xb8, 0x40, 0x00, 0x00,
+ 0xc4, 0x40, 0x00, 0x00,
+ 0x3c, 0x51, 0xff, 0x3f,
+ 0xc8, 0x40, 0x00, 0x00,
+ 0xac, 0x40, 0x00, 0x00,
+ 0xb0, 0x40, 0x00, 0x00,
+ 0xcc, 0x40, 0x00, 0x00,
+ 0x40, 0x53, 0xff, 0x3f,
+ 0x9c, 0x8b, 0x00, 0x30,
+ 0x74, 0x0d, 0xff, 0x3f,
+ 0x10, 0x53, 0xff, 0x3f,
+ 0x28, 0x80, 0x06, 0x00,
+ 0x29, 0x80, 0x06, 0x00,
+ 0x3a, 0x80, 0x06, 0x00,
+ 0x3b, 0x80, 0x06, 0x00,
+ 0xbf, 0x80, 0x06, 0x00,
+ 0xc0, 0x80, 0x06, 0x00,
+ 0x0b, 0x80, 0x06, 0x00,
+ 0x0c, 0x80, 0x06, 0x00,
+ 0x04, 0x80, 0x06, 0x00,
+ 0x05, 0x80, 0x06, 0x00,
+ 0x07, 0x80, 0x06, 0x00,
+ 0x00, 0x80, 0x06, 0x00,
+ 0x2b, 0x80, 0x06, 0x00,
+ 0x2c, 0x80, 0x06, 0x00,
+ 0x27, 0x80, 0x06, 0x00,
+ 0x14, 0x80, 0x06, 0x00,
+ 0x2a, 0x80, 0x06, 0x00,
+ 0x3c, 0x80, 0x06, 0x00,
+ 0xb4, 0x19, 0xff, 0x3f,
+ 0x0c, 0x2d, 0xff, 0x3f,
+ 0x91, 0x2e, 0xff, 0x3f,
+ 0xf4, 0x2f, 0xff, 0x3f,
+ 0x04, 0x2d, 0xff, 0x3f,
+ 0x3c, 0x19, 0xff, 0x3f,
+ 0x5c, 0x1a, 0xff, 0x3f,
+ 0x60, 0x18, 0xff, 0x3f,
+ 0x6c, 0x1a, 0xff, 0x3f,
+ 0x14, 0x4b, 0xff, 0x3f,
+ 0x10, 0x12, 0xff, 0x3f,
+ 0xff, 0xf7, 0xff, 0xff,
+ 0xff, 0xef, 0xff, 0xff,
+ 0xff, 0xff, 0xfe, 0xff,
+ 0xe8, 0x11, 0xff, 0x3f,
+ 0xa8, 0x18, 0xff, 0x3f,
+ 0xa0, 0x13, 0xff, 0x3f,
+ 0xad, 0x53, 0x00, 0x30,
+ 0x04, 0x24, 0x00, 0x00,
+ 0x00, 0x90, 0x06, 0x00,
+ 0x73, 0x94, 0x06, 0x00,
+ 0xa0, 0x86, 0x01, 0x00,
+ 0xbc, 0x1d, 0xff, 0x3f,
+ 0xe0, 0x93, 0x06, 0x00,
+ 0xff, 0xff, 0xff, 0x00,
+ 0xb8, 0x0b, 0x00, 0x00,
+ 0xd0, 0x13, 0xff, 0x3f,
+ 0x94, 0x94, 0x06, 0x00,
+ 0x40, 0x0d, 0x03, 0x00,
+ 0x74, 0x10, 0x00, 0x00,
+ 0x52, 0x09, 0x00, 0x00,
+ 0x20, 0x16, 0xff, 0x3f,
+ 0xc4, 0x1d, 0xff, 0x3f,
+ 0xa0, 0x92, 0x06, 0x00,
+ 0xb0, 0x92, 0x06, 0x00,
+ 0x08, 0x90, 0x06, 0x00,
+ 0x20, 0x92, 0x06, 0x00,
+ 0x88, 0x13, 0x00, 0x00,
+ 0x0b, 0x90, 0x06, 0x00,
+ 0x15, 0x92, 0x06, 0x00,
+ 0x1d, 0x92, 0x06, 0x00,
+ 0x18, 0x93, 0x06, 0x00,
+ 0x28, 0x93, 0x06, 0x00,
+ 0xf0, 0x92, 0x06, 0x00,
+ 0xc0, 0x92, 0x06, 0x00,
+ 0xe0, 0x92, 0x06, 0x00,
+ 0xf8, 0x92, 0x06, 0x00,
+ 0x30, 0x93, 0x06, 0x00,
+ 0x32, 0x93, 0x06, 0x00,
+ 0x35, 0x93, 0x06, 0x00,
+ 0x45, 0x93, 0x06, 0x00,
+ 0x93, 0x94, 0x06, 0x00,
+ 0xf0, 0x93, 0x06, 0x00,
+ 0xf3, 0x93, 0x06, 0x00,
+ 0xf5, 0x93, 0x06, 0x00,
+ 0x94, 0x1b, 0xff, 0x3f,
+ 0x6a, 0x5f, 0x00, 0x30,
+ 0xac, 0x18, 0xff, 0x3f,
+ 0x24, 0x52, 0xff, 0x3f,
+ 0x94, 0x13, 0xff, 0x3f,
+ 0xff, 0xbf, 0xff, 0xff,
+ 0xa8, 0x61, 0x00, 0x00,
+ 0xe0, 0x8b, 0x00, 0x30,
+ 0x27, 0x93, 0x06, 0x00,
+ 0xf2, 0x93, 0x06, 0x00,
+ 0x17, 0x95, 0x06, 0x00,
+ 0x18, 0x95, 0x06, 0x00,
+ 0x9f, 0x92, 0x06, 0x00,
+ 0xef, 0x92, 0x06, 0x00,
+ 0x17, 0x93, 0x06, 0x00,
+ 0x14, 0x92, 0x06, 0x00,
+ 0x1f, 0x92, 0x06, 0x00,
+ 0x44, 0x93, 0x06, 0x00,
+ 0x07, 0x90, 0x06, 0x00,
+ 0xef, 0x93, 0x06, 0x00,
+ 0x31, 0x93, 0x06, 0x00,
+ 0xbf, 0x92, 0x06, 0x00,
+ 0x72, 0x94, 0x06, 0x00,
+ 0x95, 0x94, 0x06, 0x00,
+ 0x00, 0x1b, 0xff, 0x3f,
+ 0x14, 0x13, 0xff, 0x3f,
+ 0x1f, 0xfe, 0x00, 0x00,
+ 0x00, 0x08, 0x00, 0x00,
+ 0xc0, 0x1d, 0xff, 0x3f,
+ 0xf0, 0x14, 0x00, 0x00,
+ 0x50, 0x22, 0xff, 0x3f,
+ 0x2d, 0x6a, 0x00, 0x30,
+ 0xec, 0x11, 0xff, 0x3f,
+ 0xff, 0xdf, 0xff, 0xff,
+ 0xff, 0x7f, 0xff, 0xff,
+ 0x00, 0x00, 0x01, 0x00,
+ 0xc0, 0x21, 0xff, 0x3f,
+ 0x24, 0x17, 0xff, 0x3f,
+ 0x38, 0x1d, 0xff, 0x3f,
+ 0x89, 0x10, 0x00, 0x00,
+ 0x98, 0x11, 0xff, 0x3f,
+ 0x00, 0x10, 0x00, 0x00,
+ 0xe4, 0x2c, 0xff, 0x3f,
+ 0xf0, 0x10, 0x00, 0x00,
+ 0x10, 0x1b, 0xff, 0x3f,
+ 0x00, 0x24, 0x00, 0x00,
+ 0xd4, 0x11, 0xff, 0x3f,
+ 0x58, 0x13, 0xff, 0x3f,
+ 0x04, 0x09, 0x00, 0x00,
+ 0x08, 0x09, 0x00, 0x00,
+ 0x18, 0x09, 0x00, 0x00,
+ 0x1c, 0x09, 0x00, 0x00,
+ 0x10, 0x09, 0x00, 0x00,
+ 0x20, 0x09, 0x00, 0x00,
+ 0x24, 0x09, 0x00, 0x00,
+ 0x38, 0x13, 0xff, 0x3f,
+ 0xfc, 0x0f, 0x00, 0x00,
+ 0x28, 0x17, 0xff, 0x3f,
+ 0x00, 0x1e, 0xff, 0x3f,
+ 0xec, 0x6e, 0x00, 0x30,
+ 0xbc, 0x70, 0x00, 0x30,
+ 0x04, 0x1c, 0xff, 0x3f,
+ 0x04, 0x53, 0x00, 0x30,
+ 0x18, 0x8b, 0x00, 0x30,
+ 0xdc, 0x8a, 0x00, 0x30,
+ 0xc4, 0x89, 0x00, 0x30,
+ 0xd4, 0x0d, 0xff, 0x3f,
+ 0xbc, 0x0e, 0xff, 0x3f,
+ 0x78, 0x85, 0x00, 0x30,
+ 0x54, 0x85, 0x00, 0x30,
+ 0xf4, 0x84, 0x00, 0x30,
+ 0x84, 0x82, 0x00, 0x30,
+ 0x60, 0x82, 0x00, 0x30,
+ 0x90, 0x7c, 0x00, 0x30,
+ 0x30, 0x13, 0xff, 0x3f,
+ 0x84, 0x74, 0x00, 0x30,
+ 0x40, 0x22, 0xff, 0x3f,
+ 0xd4, 0x25, 0xff, 0x3f,
+ 0xd0, 0x29, 0xff, 0x3f,
+ 0x58, 0x2a, 0xff, 0x3f,
+ 0x4c, 0x24, 0xff, 0x3f,
+ 0xd8, 0x29, 0xff, 0x3f,
+ 0xd0, 0x21, 0xff, 0x3f,
+ 0x80, 0x07, 0x00, 0x30,
+ 0x00, 0x08, 0x00, 0x30,
+ 0x38, 0x03, 0xff, 0x3f,
+ 0x58, 0x72, 0x00, 0x30,
+ 0x5c, 0x13, 0xff, 0x3f,
+ 0xbc, 0x21, 0xff, 0x3f,
+ 0x44, 0x24, 0xff, 0x3f,
+ 0x00, 0x28, 0x00, 0x00,
+ 0x48, 0x28, 0x00, 0x00,
+ 0x4c, 0x28, 0x00, 0x00,
+ 0xe8, 0x0e, 0xff, 0x3f,
+ 0x00, 0x13, 0xff, 0x3f,
+ 0x74, 0x0f, 0xff, 0x3f,
+ 0x1c, 0x83, 0x00, 0x30,
+ 0x00, 0x22, 0x00, 0x00,
+ 0x10, 0x00, 0xff, 0x3f,
+ 0x30, 0x00, 0xff, 0x3f,
+ 0x79, 0x0f, 0xff, 0x3f,
+ 0x6c, 0x83, 0x00, 0x30,
+ 0xf4, 0x0e, 0xff, 0x3f,
+ 0x80, 0x14, 0x00, 0x00,
+ 0x00, 0xc2, 0xeb, 0x0b,
+ 0x04, 0x13, 0xff, 0x3f,
+ 0xd0, 0x0e, 0xff, 0x3f,
+ 0xb4, 0x83, 0x00, 0x30,
+ 0x80, 0x84, 0x00, 0x30,
+ 0x78, 0x0f, 0xff, 0x3f,
+ 0xa0, 0x82, 0x00, 0x30,
+ 0x28, 0x84, 0x00, 0x30,
+ 0xdc, 0x82, 0x00, 0x30,
+ 0x77, 0x0f, 0xff, 0x3f,
+ 0x10, 0x13, 0xff, 0x3f,
+ 0xfc, 0x12, 0xff, 0x3f,
+ 0xe4, 0x0e, 0xff, 0x3f,
+ 0x04, 0x84, 0x00, 0x30,
+ 0x75, 0x0f, 0xff, 0x3f,
+ 0x76, 0x0f, 0xff, 0x3f,
+ 0x78, 0x11, 0xff, 0x3f,
+ 0x58, 0x84, 0x00, 0x30,
+ 0x24, 0x0e, 0xff, 0x3f,
+ 0x88, 0x85, 0x00, 0x30,
+ 0x08, 0x0e, 0xff, 0x3f,
+ 0x14, 0x28, 0x00, 0x00,
+ 0x18, 0x28, 0x00, 0x00,
+ 0x80, 0x96, 0x98, 0x00,
+ 0x28, 0x28, 0x00, 0x00,
+ 0x30, 0x28, 0x00, 0x00,
+ 0x34, 0x28, 0x00, 0x00,
+ 0x1c, 0x28, 0x00, 0x00,
+ 0x54, 0x3e, 0x00, 0x00,
+ 0x74, 0x3e, 0x00, 0x00,
+ 0x18, 0x40, 0x00, 0x00,
+ 0x14, 0x1b, 0xff, 0x3f,
+ 0x5a, 0x5a, 0xa5, 0xa5,
+ 0x70, 0x13, 0xff, 0x3f,
+ 0xc0, 0x79, 0x00, 0x30,
+ 0x9c, 0x79, 0x00, 0x30,
+ 0x18, 0x74, 0x00, 0x30,
+ 0x24, 0x13, 0x00, 0x30,
+ 0x80, 0x14, 0x00, 0x30,
+ 0xa4, 0x14, 0x00, 0x30,
+ 0x64, 0x2c, 0xff, 0x3f,
+ 0x60, 0x2e, 0xff, 0x3f,
+ 0x08, 0x23, 0x00, 0x00,
+ 0x1c, 0x21, 0x00, 0x00,
+ 0x08, 0x28, 0x00, 0x00,
+ 0xd8, 0x14, 0x00, 0x30,
+ 0x00, 0x21, 0x00, 0x00,
+ 0x04, 0x21, 0x00, 0x00,
+ 0x54, 0x13, 0xff, 0x3f,
+ 0x40, 0x03, 0xff, 0x3f,
+ 0x50, 0x03, 0xff, 0x3f,
+ 0x00, 0x09, 0x00, 0x00,
+ 0x0c, 0x09, 0x00, 0x00,
+ 0xb0, 0x71, 0x0b, 0x00,
+ 0x90, 0x01, 0xff, 0x3f,
+ 0x5c, 0x03, 0xff, 0x3f,
+ 0x90, 0x59, 0xff, 0x3f,
+ 0xa0, 0x59, 0xff, 0x3f,
+ 0xa0, 0x5a, 0xff, 0x3f,
+ 0xa4, 0x5a, 0xff, 0x3f,
+ 0x70, 0x03, 0xff, 0x3f,
+ 0xa0, 0x5c, 0xff, 0x3f,
+ 0xb0, 0x5a, 0xff, 0x3f,
+ 0x20, 0x5b, 0xff, 0x3f,
+ 0x10, 0x5b, 0xff, 0x3f,
+ 0xfc, 0x95, 0x00, 0x30,
+ 0xc0, 0x5a, 0xff, 0x3f,
+ 0x68, 0x03, 0xff, 0x3f,
+ 0x64, 0x03, 0xff, 0x3f,
+ 0x74, 0x03, 0xff, 0x3f,
+ 0x20, 0x5b, 0xff, 0x3f,
+ 0x78, 0x03, 0xff, 0x3f,
+ 0xe0, 0x02, 0xff, 0x3f,
+ 0x24, 0x5b, 0xff, 0x3f,
+ 0x20, 0x5c, 0xff, 0x3f,
+ 0xa8, 0x5c, 0xff, 0x3f,
+ 0xb8, 0x5c, 0xff, 0x3f,
+ 0x7c, 0x03, 0xff, 0x3f,
+ 0xac, 0x5c, 0xff, 0x3f,
+ 0xc0, 0x9a, 0x00, 0x30,
+ 0x3c, 0x98, 0x00, 0x30,
+ 0x00, 0x00, 0x00, 0x00,
+ 0xf0, 0x9a, 0x00, 0x30,
+ 0x21, 0x00, 0x05, 0x00,
+ 0x07, 0x00, 0x00, 0x80,
+ 0x05, 0x00, 0x00, 0x00,
+ 0x90, 0x02, 0xff, 0x3f,
+ 0x88, 0x04, 0xff, 0x3f,
+ 0x98, 0x9d, 0x00, 0x30,
+ 0x80, 0x04, 0xff, 0x3f,
+ 0x00, 0x0d, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0xc0,
+ 0xb0, 0x9d, 0x00, 0x30,
+ 0xec, 0x00, 0xff, 0x3f,
+ 0xe8, 0x02, 0xff, 0x3f,
+ 0x08, 0x10, 0x00, 0x30,
+ 0x36, 0x81, 0x00, 0x81,
+ 0x52, 0xfe, 0x3d, 0xf0,
+ 0xe0, 0x08, 0x00, 0x81,
+ 0x51, 0xfe, 0x3d, 0xf0,
+ 0xe0, 0x08, 0x00, 0x1d,
+ 0xf0, 0x00, 0x00, 0x00,
+ 0x02, 0xa0, 0x00, 0x11,
+ 0x4e, 0xfe, 0x31, 0x4e,
+ 0xfe, 0x30, 0xe6, 0x13,
+ 0x10, 0x20, 0x00, 0x41,
+ 0x4d, 0xfe, 0x16, 0x24,
+ 0x00, 0xd0, 0x04, 0x00,
+ 0x61, 0x4c, 0xfe, 0x71,
+ 0x4c, 0xfe, 0x77, 0xb6,
+ 0x32, 0x88, 0x06, 0x98,
+ 0x16, 0x8b, 0x66, 0x80,
+ 0xa9, 0xc0, 0x27, 0x6a,
+ 0x03, 0x09, 0x08, 0x4b,
+ 0x88, 0x37, 0x6a, 0x07,
+ 0x02, 0x68, 0x00, 0x09,
+ 0x18, 0x82, 0xc8, 0x08,
+ 0xa0, 0xa4, 0x41, 0x8c,
+ 0xea, 0x0b, 0xaa, 0x09,
+ 0x08, 0x09, 0x18, 0x09,
+ 0x28, 0x09, 0x38, 0x82,
+ 0xc8, 0x10, 0x56, 0xfa,
+ 0xfe, 0x77, 0x36, 0xcc,
+ 0x15, 0xd9, 0x08, 0x61,
+ 0x3e, 0xfe, 0x71, 0x3e,
+ 0xfe, 0x81, 0x3e, 0xfe,
+ 0x91, 0x3f, 0xfe, 0xa1,
+ 0x3f, 0xfe, 0x68, 0x06,
+ 0x15, 0x76, 0x08, 0x61,
+ 0x39, 0xfe, 0x71, 0x39,
+ 0xfe, 0x81, 0x39, 0xfe,
+ 0x68, 0x06, 0x55, 0x00,
+ 0x08, 0x95, 0x3d, 0x08,
+ 0x36, 0x41, 0x00, 0x31,
+ 0x39, 0xfe, 0x82, 0x03,
+ 0x00, 0xec, 0xf8, 0x21,
+ 0x38, 0xfe, 0xb8, 0x02,
+ 0xa2, 0x2b, 0x00, 0x16,
+ 0xda, 0x00, 0x4b, 0x9b,
+ 0x99, 0x02, 0xe0, 0x0a,
+ 0x00, 0xb8, 0x02, 0xa8,
+ 0x0b, 0x56, 0x1a, 0xff,
+ 0xa1, 0x33, 0xfe, 0x0c,
+ 0x0b, 0xb7, 0x1a, 0x08,
+ 0xa1, 0x32, 0xfe, 0x81,
+ 0x30, 0xfe, 0xe0, 0x08,
+ 0x00, 0x0c, 0x1c, 0xc2,
+ 0x43, 0x00, 0x1d, 0xf0,
+ 0x1d, 0xf0, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0x81,
+ 0x2d, 0xfe, 0x92, 0xa0,
+ 0x00, 0x97, 0x18, 0x0b,
+ 0xa1, 0x2a, 0xfe, 0xb1,
+ 0x2b, 0xfe, 0x81, 0x29,
+ 0xfe, 0xe0, 0x08, 0x00,
+ 0x1d, 0xf0, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0x0c,
+ 0x02, 0x8c, 0xa4, 0x0c,
+ 0x06, 0x62, 0x43, 0x00,
+ 0x1b, 0x33, 0x1b, 0x66,
+ 0x67, 0x94, 0xf5, 0x1d,
+ 0xf0, 0x00, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0xbd,
+ 0x03, 0xad, 0x02, 0xa5,
+ 0x0b, 0x00, 0x1d, 0xf0,
+ 0x36, 0x41, 0x00, 0xad,
+ 0x02, 0x65, 0xf4, 0x00,
+ 0x1d, 0xf0, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0xa2,
+ 0xa0, 0xcc, 0x25, 0xf6,
+ 0x00, 0x2d, 0x0a, 0x1d,
+ 0xf0, 0x00, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0xc0,
+ 0x20, 0x00, 0x39, 0x02,
+ 0x1d, 0xf0, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0xed,
+ 0x06, 0xdd, 0x05, 0xcd,
+ 0x04, 0xbd, 0x03, 0xad,
+ 0x02, 0x0c, 0x0f, 0x25,
+ 0xd3, 0x00, 0x1d, 0xf0,
+ 0x36, 0x41, 0x00, 0xad,
+ 0x02, 0x25, 0x10, 0x00,
+ 0x1d, 0xf0, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0xbd,
+ 0x03, 0xad, 0x02, 0xa5,
+ 0x11, 0x00, 0x1d, 0xf0,
+ 0x36, 0x41, 0x00, 0xcd,
+ 0x04, 0xbd, 0x03, 0xad,
+ 0x02, 0x65, 0xc1, 0x07,
+ 0x1d, 0xf0, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0xcd,
+ 0x04, 0xbd, 0x03, 0xad,
+ 0x02, 0x0c, 0x0d, 0xa5,
+ 0x15, 0x00, 0x1d, 0xf0,
+ 0x36, 0x41, 0x00, 0x21,
+ 0x02, 0xfe, 0x1d, 0xf0,
+ 0x36, 0x41, 0x00, 0xcd,
+ 0x04, 0xbd, 0x03, 0xad,
+ 0x02, 0x0c, 0x0d, 0x25,
+ 0xc1, 0x02, 0x1d, 0xf0,
+ 0x36, 0x41, 0x00, 0xbd,
+ 0x03, 0xad, 0x02, 0xe5,
+ 0xb4, 0x07, 0x1d, 0xf0,
+ 0x36, 0x41, 0x00, 0xcd,
+ 0x04, 0xbd, 0x03, 0xad,
+ 0x02, 0x25, 0xbd, 0x07,
+ 0x1d, 0xf0, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0xad,
+ 0x02, 0x0c, 0x0b, 0xe5,
+ 0xc4, 0x07, 0x1d, 0xf0,
+ 0x36, 0x61, 0x00, 0x22,
+ 0xc3, 0x40, 0xa2, 0x03,
+ 0x01, 0x92, 0x03, 0x02,
+ 0x82, 0x03, 0x03, 0x80,
+ 0x99, 0x11, 0x90, 0x88,
+ 0x20, 0x92, 0x03, 0x00,
+ 0x00, 0xaa, 0x11, 0x80,
+ 0x99, 0x01, 0xa0, 0x99,
+ 0x20, 0x90, 0x88, 0x20,
+ 0xc0, 0x20, 0x00, 0x89,
+ 0x01, 0xa1, 0xe9, 0xfd,
+ 0xc0, 0x20, 0x00, 0xb8,
+ 0x01, 0x65, 0xf3, 0xff,
+ 0x4b, 0x33, 0x27, 0x93,
+ 0xcc, 0xb2, 0xa1, 0x00,
+ 0xa1, 0xe6, 0xfd, 0xc0,
+ 0x20, 0x00, 0xc8, 0x0a,
+ 0x87, 0xec, 0x07, 0xc0,
+ 0x20, 0x00, 0xd8, 0x0a,
+ 0xb7, 0x0d, 0xf7, 0x1d,
+ 0xf0, 0x00, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0xbd,
+ 0x03, 0xad, 0x02, 0x65,
+ 0xfa, 0xff, 0x1d, 0xf0,
+ 0x36, 0x41, 0x00, 0xad,
+ 0x02, 0x25, 0xe3, 0x00,
+ 0x1d, 0xf0, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0xa2,
+ 0xa0, 0xcc, 0xe5, 0xe4,
+ 0x00, 0x2d, 0x0a, 0x1d,
+ 0xf0, 0x00, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0xed,
+ 0x06, 0xdd, 0x05, 0xcd,
+ 0x04, 0xbd, 0x03, 0xad,
+ 0x02, 0x0c, 0x1f, 0xa5,
+ 0xc2, 0x00, 0x1d, 0xf0,
+ 0x36, 0x41, 0x00, 0xad,
+ 0x02, 0xb2, 0x22, 0x32,
+ 0xe5, 0xba, 0x07, 0xad,
+ 0x02, 0xb2, 0xc2, 0x48,
+ 0x4c, 0x0c, 0xe5, 0xb1,
+ 0x07, 0x1d, 0xf0, 0x00,
+ 0x36, 0x41, 0x00, 0xad,
+ 0x02, 0x25, 0xfe, 0xff,
+ 0x1d, 0xf0, 0x00, 0x00,
+ 0x36, 0x81, 0x00, 0x42,
+ 0x22, 0x32, 0xad, 0x02,
+ 0xbd, 0x01, 0xe5, 0xa6,
+ 0x07, 0xad, 0x02, 0xbd,
+ 0x04, 0x25, 0xb8, 0x07,
+ 0xad, 0x02, 0x4c, 0x0c,
+ 0xb2, 0xd2, 0x01, 0xb2,
+ 0xcb, 0x88, 0xe5, 0xae,
+ 0x07, 0xad, 0x02, 0xbd,
+ 0x01, 0x2c, 0x08, 0x1c,
+ 0xcc, 0x40, 0xc8, 0x83,
+ 0xe5, 0xad, 0x07, 0xbd,
+ 0x03, 0xad, 0x02, 0x65,
+ 0xa4, 0x07, 0xad, 0x01,
+ 0x0c, 0x0b, 0x2c, 0x0c,
+ 0x25, 0xad, 0x08, 0x1d,
+ 0xf0, 0x00, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0xbd,
+ 0x03, 0xad, 0x02, 0x65,
+ 0xfb, 0xff, 0x1d, 0xf0,
+ 0x36, 0x41, 0x00, 0xcd,
+ 0x04, 0xbd, 0x03, 0xad,
+ 0x02, 0x25, 0xab, 0x07,
+ 0x1d, 0xf0, 0x00, 0x00,
+ 0x36, 0x81, 0x00, 0x4c,
+ 0x08, 0x47, 0xb8, 0x13,
+ 0xbd, 0x04, 0xad, 0x03,
+ 0xcd, 0x01, 0xdd, 0x05,
+ 0xe5, 0xab, 0x02, 0x3d,
+ 0x01, 0x1c, 0xc9, 0x2c,
+ 0x04, 0x50, 0x49, 0x93,
+ 0x3c, 0x6b, 0x4c, 0x0c,
+ 0x62, 0xc2, 0x48, 0xad,
+ 0x06, 0xa5, 0xa8, 0x08,
+ 0x5c, 0xcb, 0x4c, 0x0c,
+ 0xa2, 0xd2, 0x01, 0xa2,
+ 0xca, 0x88, 0xe5, 0xa7,
+ 0x08, 0xac, 0x14, 0xad,
+ 0x02, 0x3a, 0xc4, 0xe2,
+ 0x03, 0x00, 0xd2, 0x0a,
+ 0x88, 0xf2, 0x0a, 0x48,
+ 0x1b, 0xaa, 0xf0, 0xee,
+ 0x30, 0xe2, 0x4a, 0x47,
+ 0xb2, 0x03, 0x00, 0x1b,
+ 0x33, 0xd0, 0xbb, 0x30,
+ 0xb2, 0x4a, 0x87, 0xc7,
+ 0x93, 0xe0, 0xbd, 0x05,
+ 0xad, 0x02, 0x65, 0xad,
+ 0x07, 0xbd, 0x06, 0xad,
+ 0x02, 0x4c, 0x0c, 0x65,
+ 0xa4, 0x07, 0xad, 0x01,
+ 0x0c, 0x0b, 0x2c, 0x0c,
+ 0xe5, 0xa3, 0x08, 0x1d,
+ 0xf0, 0x00, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0xcd,
+ 0x04, 0xbd, 0x03, 0xad,
+ 0x02, 0x0c, 0x1d, 0xe5,
+ 0xf7, 0xff, 0x1d, 0xf0,
+ 0x36, 0x41, 0x00, 0x21,
+ 0x8b, 0xfd, 0x1d, 0xf0,
+ 0x36, 0x41, 0x00, 0xcd,
+ 0x04, 0xbd, 0x03, 0xad,
+ 0x02, 0x0c, 0x1d, 0x65,
+ 0xa3, 0x02, 0x1d, 0xf0,
+ 0x36, 0x41, 0x00, 0xbd,
+ 0x03, 0xad, 0x02, 0x25,
+ 0x97, 0x07, 0x1d, 0xf0,
+ 0x36, 0x41, 0x00, 0xcd,
+ 0x04, 0xbd, 0x03, 0xad,
+ 0x02, 0x65, 0x9f, 0x07,
+ 0x1d, 0xf0, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0xad,
+ 0x02, 0x0c, 0x1b, 0x25,
+ 0xa7, 0x07, 0x1d, 0xf0,
+ 0x36, 0x41, 0x00, 0xc0,
+ 0x20, 0x00, 0x28, 0x02,
+ 0x1d, 0xf0, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0x71,
+ 0x7b, 0xfd, 0x31, 0x7b,
+ 0xfd, 0x70, 0x72, 0xd1,
+ 0x3a, 0x37, 0x82, 0x03,
+ 0x80, 0x41, 0x79, 0xfd,
+ 0x16, 0xf8, 0x13, 0x82,
+ 0xa0, 0x80, 0x1c, 0x8a,
+ 0x20, 0xa8, 0x93, 0x65,
+ 0xfd, 0xff, 0x92, 0x03,
+ 0x80, 0x7c, 0xf6, 0x60,
+ 0xaa, 0x30, 0xa0, 0x99,
+ 0x10, 0x90, 0x90, 0x74,
+ 0x16, 0x39, 0x12, 0x4a,
+ 0x57, 0x41, 0x71, 0xfd,
+ 0xc2, 0x23, 0x1f, 0xf2,
+ 0xa0, 0x88, 0x2c, 0x0e,
+ 0x20, 0xef, 0x93, 0x5a,
+ 0xdc, 0x4a, 0xdd, 0xd2,
+ 0x0d, 0x80, 0xc0, 0x20,
+ 0x00, 0xd9, 0x0e, 0x1b,
+ 0xcc, 0xb2, 0x23, 0x1e,
+ 0xc2, 0x63, 0x1f, 0xc7,
+ 0x9b, 0x04, 0x0c, 0x08,
+ 0x82, 0x43, 0x80, 0x92,
+ 0xa0, 0x80, 0x1c, 0x8a,
+ 0x20, 0xa9, 0x93, 0xe5,
+ 0xf8, 0xff, 0xbd, 0x0a,
+ 0xa2, 0x03, 0x80, 0x60,
+ 0xbb, 0x30, 0xb0, 0xaa,
+ 0x10, 0xa0, 0xa0, 0x74,
+ 0x56, 0xca, 0xfb, 0xc2,
+ 0xa0, 0x84, 0x1c, 0xca,
+ 0x20, 0xac, 0x93, 0x25,
+ 0xf7, 0xff, 0x42, 0xa1,
+ 0x80, 0x0c, 0x56, 0x31,
+ 0x5d, 0xfd, 0xa0, 0x90,
+ 0x04, 0x3a, 0x37, 0x56,
+ 0xe9, 0x0b, 0x92, 0x23,
+ 0x7f, 0xc2, 0xc9, 0xfb,
+ 0x16, 0x5c, 0x0b, 0x16,
+ 0xd9, 0x09, 0x0b, 0xd9,
+ 0x16, 0x3d, 0x08, 0x26,
+ 0x29, 0x6b, 0x26, 0x39,
+ 0x2c, 0x66, 0x49, 0x54,
+ 0xe2, 0xa0, 0x8c, 0x2c,
+ 0x4a, 0x20, 0xae, 0x93,
+ 0xa5, 0xf3, 0xff, 0x92,
+ 0x23, 0x80, 0x5a, 0x99,
+ 0x92, 0xd9, 0x10, 0xa2,
+ 0x49, 0xf0, 0x82, 0x23,
+ 0x80, 0xf2, 0x23, 0x81,
+ 0x1b, 0x88, 0x82, 0x63,
+ 0x80, 0x87, 0x9f, 0x30,
+ 0x62, 0x63, 0x7f, 0x86,
+ 0x0a, 0x00, 0xb2, 0xa0,
+ 0x8c, 0x2c, 0x4a, 0x20,
+ 0xab, 0x93, 0x25, 0xf1,
+ 0xff, 0x4a, 0xc3, 0x0c,
+ 0x49, 0xa2, 0x4c, 0x8b,
+ 0xc2, 0x0c, 0x8a, 0xa0,
+ 0xd0, 0x74, 0x80, 0xcc,
+ 0x11, 0xda, 0xcc, 0xc2,
+ 0x63, 0x81, 0xc0, 0x96,
+ 0x83, 0x0c, 0x0d, 0xd2,
+ 0x63, 0x80, 0x92, 0x63,
+ 0x7f, 0xd2, 0xa0, 0x84,
+ 0x1c, 0xca, 0x20, 0xad,
+ 0x93, 0x65, 0xee, 0xff,
+ 0xa0, 0x90, 0x04, 0x06,
+ 0xdf, 0xff, 0xe2, 0xa0,
+ 0x8c, 0x2c, 0x4a, 0x20,
+ 0xae, 0x93, 0x65, 0xed,
+ 0xff, 0x0c, 0x39, 0x4a,
+ 0xf3, 0xa2, 0x4f, 0x8a,
+ 0x86, 0xf5, 0xff, 0x82,
+ 0xa0, 0x8c, 0x2c, 0x4a,
+ 0x20, 0xa8, 0x93, 0x25,
+ 0xec, 0xff, 0x4a, 0x93,
+ 0xa2, 0x49, 0x89, 0x0c,
+ 0x29, 0x46, 0xf0, 0xff,
+ 0xb2, 0xa0, 0x8c, 0x2c,
+ 0x4a, 0x20, 0xab, 0x93,
+ 0xa5, 0xea, 0xff, 0x0c,
+ 0x19, 0x4a, 0xc3, 0xa2,
+ 0x4c, 0x88, 0x06, 0xeb,
+ 0xff, 0x1d, 0xf0, 0x4a,
+ 0x57, 0x86, 0xc7, 0xff,
+ 0x36, 0x41, 0x00, 0x41,
+ 0x2a, 0xfd, 0x31, 0x28,
+ 0xfd, 0x0c, 0x18, 0x32,
+ 0x03, 0xc1, 0x40, 0x33,
+ 0xa0, 0x32, 0x23, 0x7f,
+ 0x0c, 0x02, 0x48, 0x83,
+ 0x29, 0x43, 0x80, 0x44,
+ 0x20, 0x49, 0x83, 0x1d,
+ 0xf0, 0x00, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0x0c,
+ 0x03, 0x41, 0x1b, 0xfd,
+ 0x51, 0x1a, 0xfd, 0x81,
+ 0x1d, 0xfd, 0x50, 0x52,
+ 0xd1, 0x4a, 0x45, 0x8a,
+ 0x55, 0x32, 0x65, 0x7f,
+ 0x32, 0x44, 0x80, 0x1d,
+ 0xf0, 0x00, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0x0c,
+ 0xca, 0xa5, 0x10, 0x07,
+ 0x91, 0x14, 0xfd, 0x0c,
+ 0x18, 0x82, 0x49, 0xb6,
+ 0x1d, 0xf0, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0x0c,
+ 0x14, 0x0c, 0x05, 0x31,
+ 0x0f, 0xfd, 0x81, 0x13,
+ 0xfd, 0xc0, 0x20, 0x00,
+ 0x88, 0x08, 0x91, 0x12,
+ 0xfd, 0x07, 0x68, 0x1f,
+ 0x21, 0x12, 0xfd, 0xc0,
+ 0x20, 0x00, 0x28, 0x02,
+ 0x27, 0x62, 0x05, 0x52,
+ 0x49, 0x80, 0x42, 0x43,
+ 0x76, 0x37, 0x62, 0x05,
+ 0x42, 0x49, 0x80, 0x42,
+ 0x43, 0x77, 0x07, 0x62,
+ 0x02, 0x65, 0xfb, 0xff,
+ 0x61, 0x07, 0xfd, 0x21,
+ 0x0a, 0xfd, 0xc0, 0x20,
+ 0x00, 0x28, 0x02, 0x17,
+ 0x62, 0x16, 0x0c, 0x4a,
+ 0xe5, 0xbb, 0x05, 0x60,
+ 0x9a, 0xa0, 0x92, 0x29,
+ 0x7f, 0x42, 0x43, 0x74,
+ 0x88, 0x89, 0x59, 0x49,
+ 0x40, 0x88, 0x20, 0x89,
+ 0x89, 0x37, 0x62, 0x16,
+ 0x0c, 0x4a, 0x65, 0xba,
+ 0x05, 0x60, 0xba, 0xa0,
+ 0xb2, 0x2b, 0x7f, 0x42,
+ 0x43, 0x75, 0xa8, 0x8b,
+ 0x59, 0x4b, 0x40, 0xaa,
+ 0x20, 0xa9, 0x8b, 0x1d,
+ 0xf0, 0x00, 0x00, 0x00,
+ 0x36, 0xa1, 0x00, 0x59,
+ 0x01, 0x88, 0x12, 0xe2,
+ 0x04, 0x08, 0x92, 0x04,
+ 0x00, 0xb2, 0x04, 0x01,
+ 0xf2, 0x04, 0x09, 0xc2,
+ 0x04, 0x0d, 0xd2, 0x04,
+ 0x05, 0x62, 0x04, 0x0f,
+ 0xad, 0x03, 0x72, 0x04,
+ 0x07, 0x32, 0x04, 0x0b,
+ 0x80, 0x77, 0x01, 0x80,
+ 0x66, 0x01, 0x80, 0xdd,
+ 0x11, 0x80, 0xcc, 0x11,
+ 0x80, 0xff, 0x11, 0x80,
+ 0xbb, 0x11, 0xb0, 0x99,
+ 0x20, 0x80, 0x33, 0x01,
+ 0xb2, 0x04, 0x0c, 0xf0,
+ 0xee, 0x20, 0xc0, 0xbb,
+ 0x20, 0xc2, 0x04, 0x04,
+ 0xf2, 0x04, 0x03, 0xd0,
+ 0xcc, 0x20, 0xd2, 0x04,
+ 0x02, 0x80, 0xff, 0x01,
+ 0x00, 0xdd, 0x11, 0xf0,
+ 0xdd, 0x20, 0xd0, 0x99,
+ 0x20, 0xf2, 0x04, 0x0a,
+ 0xd8, 0x28, 0x00, 0xff,
+ 0x11, 0x30, 0xff, 0x20,
+ 0x32, 0x04, 0x0e, 0xf0,
+ 0xee, 0x20, 0x00, 0x33,
+ 0x11, 0x60, 0x33, 0x20,
+ 0x30, 0xbb, 0x20, 0x62,
+ 0x04, 0x06, 0x38, 0x02,
+ 0xe0, 0x2d, 0x30, 0x00,
+ 0x66, 0x11, 0x70, 0x66,
+ 0x20, 0x30, 0x31, 0x21,
+ 0x78, 0x08, 0x0b, 0x33,
+ 0x90, 0x77, 0x30, 0x98,
+ 0x38, 0x60, 0xcc, 0x20,
+ 0xb0, 0x99, 0x30, 0xb8,
+ 0x18, 0x82, 0xc8, 0x10,
+ 0xc0, 0x4b, 0x30, 0x56,
+ 0xca, 0x3f, 0xf1, 0xd2,
+ 0xfc, 0x52, 0xdf, 0x08,
+ 0xf2, 0xdf, 0x0c, 0xe6,
+ 0x13, 0x02, 0x86, 0x74,
+ 0x00, 0x89, 0x31, 0x90,
+ 0x68, 0x74, 0x90, 0xd0,
+ 0x75, 0x20, 0xc8, 0x75,
+ 0x70, 0xe0, 0x75, 0x39,
+ 0x11, 0x90, 0xb8, 0x75,
+ 0x90, 0x30, 0x74, 0xf0,
+ 0xbb, 0xa0, 0x50, 0xee,
+ 0xa0, 0xf0, 0xcc, 0xa0,
+ 0x50, 0xdd, 0xa0, 0xd2,
+ 0x2d, 0x7f, 0xc2, 0x2c,
+ 0x7f, 0xe2, 0x2e, 0x7f,
+ 0xb2, 0x2b, 0x7f, 0x40,
+ 0x58, 0x75, 0x70, 0x90,
+ 0x74, 0xf0, 0x55, 0xa0,
+ 0x52, 0x25, 0x7f, 0xe0,
+ 0xbb, 0x30, 0xd0, 0xcc,
+ 0x30, 0xe8, 0x38, 0xd1,
+ 0xbe, 0xfc, 0x88, 0x08,
+ 0xa2, 0xdd, 0x04, 0xd0,
+ 0x33, 0xa0, 0xd0, 0x99,
+ 0xa0, 0x92, 0x29, 0x7f,
+ 0x32, 0x23, 0x7f, 0xa0,
+ 0x66, 0xa0, 0x62, 0x26,
+ 0x7f, 0x40, 0xd0, 0x75,
+ 0x30, 0xee, 0x30, 0x90,
+ 0x88, 0x30, 0x31, 0xb6,
+ 0xfc, 0x80, 0x66, 0x30,
+ 0x20, 0x98, 0x74, 0x70,
+ 0x88, 0x75, 0xa0, 0x99,
+ 0xa0, 0x92, 0x29, 0x7f,
+ 0x70, 0x78, 0x74, 0xf0,
+ 0x88, 0xa0, 0x30, 0xdd,
+ 0xa0, 0xd2, 0x2d, 0x7f,
+ 0x82, 0x28, 0x7f, 0xa0,
+ 0x77, 0xa0, 0xe0, 0x99,
+ 0x30, 0x72, 0x27, 0x7f,
+ 0xe2, 0xd3, 0xf8, 0xd0,
+ 0x88, 0x30, 0xd8, 0x31,
+ 0x90, 0x88, 0x30, 0x89,
+ 0x51, 0x40, 0x90, 0x74,
+ 0xe0, 0x99, 0xa0, 0x92,
+ 0x29, 0x7f, 0x88, 0x1d,
+ 0xd8, 0x2d, 0x90, 0x88,
+ 0x30, 0x80, 0x77, 0x30,
+ 0x9d, 0x03, 0x20, 0x80,
+ 0x75, 0x70, 0x7c, 0x30,
+ 0x70, 0x38, 0x74, 0x40,
+ 0xc8, 0x74, 0x90, 0x88,
+ 0xa0, 0x20, 0x20, 0x74,
+ 0x98, 0x51, 0x82, 0x28,
+ 0x7f, 0xe0, 0x22, 0xa0,
+ 0xa0, 0xcc, 0xa0, 0xa0,
+ 0x33, 0xa0, 0x32, 0x23,
+ 0x7f, 0xc2, 0x2c, 0x7f,
+ 0x22, 0x22, 0x7f, 0x80,
+ 0x55, 0x30, 0x90, 0x88,
+ 0x74, 0x20, 0xdd, 0x30,
+ 0x60, 0x55, 0x30, 0x28,
+ 0x51, 0x50, 0x48, 0x74,
+ 0xd0, 0xcc, 0x30, 0xa0,
+ 0x88, 0xa0, 0x82, 0x28,
+ 0x7f, 0xd1, 0x92, 0xfc,
+ 0xc0, 0xbb, 0x30, 0xa0,
+ 0x44, 0xa0, 0x20, 0x28,
+ 0x75, 0x49, 0x41, 0x90,
+ 0xc0, 0x74, 0xb0, 0x68,
+ 0x74, 0x90, 0x90, 0x75,
+ 0xa0, 0x66, 0xa0, 0xe0,
+ 0xcc, 0xa0, 0xc2, 0x2c,
+ 0x7f, 0x70, 0xa0, 0x74,
+ 0x69, 0x21, 0xb0, 0x48,
+ 0x75, 0xd0, 0x99, 0xa0,
+ 0x92, 0x29, 0x7f, 0x50,
+ 0xd0, 0x74, 0xf0, 0x44,
+ 0xa0, 0xb0, 0x60, 0x74,
+ 0xe0, 0xaa, 0xa0, 0xa2,
+ 0x2a, 0x7f, 0xb0, 0xb0,
+ 0x75, 0x42, 0x24, 0x7f,
+ 0xe0, 0xdd, 0xa0, 0xe0,
+ 0x66, 0xa0, 0x62, 0x26,
+ 0x7f, 0xd2, 0x2d, 0x7f,
+ 0x90, 0x44, 0x30, 0x70,
+ 0xe0, 0x75, 0x50, 0x98,
+ 0x75, 0x70, 0x78, 0x75,
+ 0xf0, 0x99, 0xa0, 0xf1,
+ 0x7b, 0xfc, 0x92, 0x29,
+ 0x7f, 0xf0, 0xee, 0xa0,
+ 0xe2, 0x2e, 0x7f, 0x50,
+ 0x50, 0x75, 0xe0, 0x99,
+ 0x30, 0xe2, 0xdf, 0x04,
+ 0xe0, 0x77, 0xa0, 0xe0,
+ 0x22, 0xa0, 0x22, 0x22,
+ 0x7f, 0x72, 0x27, 0x7f,
+ 0xed, 0x0f, 0xe0, 0xbb,
+ 0xa0, 0xb2, 0x2b, 0x7f,
+ 0xf2, 0xdf, 0x04, 0xb0,
+ 0x77, 0x30, 0xb8, 0x31,
+ 0xe0, 0x55, 0xa0, 0xb8,
+ 0x4b, 0x52, 0x25, 0x7f,
+ 0xd0, 0xbb, 0x30, 0xb0,
+ 0x88, 0x30, 0x80, 0x77,
+ 0x30, 0x88, 0x31, 0x50,
+ 0x22, 0x30, 0xb8, 0x78,
+ 0x58, 0x68, 0xc0, 0xbb,
+ 0x30, 0x60, 0x55, 0x30,
+ 0xc8, 0x11, 0x68, 0x58,
+ 0x50, 0x33, 0x30, 0x82,
+ 0xc8, 0x20, 0x58, 0x41,
+ 0x30, 0x22, 0x30, 0xa0,
+ 0x66, 0x30, 0x0b, 0xcc,
+ 0x3d, 0x0c, 0x52, 0x25,
+ 0x7f, 0xa8, 0x21, 0x60,
+ 0x55, 0x30, 0xa2, 0x2a,
+ 0x7f, 0x50, 0x44, 0x30,
+ 0x51, 0x5e, 0xfc, 0xb0,
+ 0xaa, 0x30, 0xa0, 0x99,
+ 0x30, 0x56, 0xcc, 0xe2,
+ 0x40, 0xa8, 0x74, 0x20,
+ 0xc8, 0x74, 0x90, 0xe8,
+ 0x74, 0x70, 0xd8, 0x74,
+ 0xb1, 0x59, 0xfc, 0x90,
+ 0x30, 0x74, 0x62, 0xdb,
+ 0xfc, 0x60, 0x33, 0xa0,
+ 0xb0, 0xdd, 0xa0, 0xb0,
+ 0xee, 0xa0, 0xb0, 0xcc,
+ 0xa0, 0xb0, 0xaa, 0xa0,
+ 0xa2, 0x2a, 0x7f, 0xc9,
+ 0x71, 0xe9, 0x51, 0xd9,
+ 0x41, 0x20, 0xe0, 0x74,
+ 0x90, 0xd0, 0x75, 0x70,
+ 0xc0, 0x74, 0x90, 0x98,
+ 0x75, 0x60, 0xcc, 0xa0,
+ 0x50, 0xdd, 0xa0, 0x60,
+ 0xee, 0xa0, 0xe2, 0x2e,
+ 0x7f, 0xd2, 0x2d, 0x7f,
+ 0xc9, 0x21, 0x40, 0xb0,
+ 0x74, 0xf0, 0x99, 0xa0,
+ 0x92, 0x29, 0x7f, 0x60,
+ 0xbb, 0xa0, 0x20, 0xc8,
+ 0x75, 0x40, 0x68, 0x75,
+ 0xb9, 0x61, 0xf0, 0xcc,
+ 0xa0, 0xc2, 0x2c, 0x7f,
+ 0x20, 0xb0, 0x75, 0xf0,
+ 0x66, 0xa0, 0x22, 0x23,
+ 0x7f, 0x62, 0x26, 0x7f,
+ 0x50, 0xbb, 0xa0, 0xd0,
+ 0xcc, 0x30, 0xb2, 0x2b,
+ 0x7f, 0x40, 0xd0, 0x75,
+ 0xb0, 0x66, 0x30, 0x50,
+ 0xdd, 0xa0, 0xd2, 0x2d,
+ 0x7f, 0x70, 0xb8, 0x75,
+ 0xf0, 0xbb, 0xa0, 0xb2,
+ 0x2b, 0x7f, 0x31, 0x39,
+ 0xfc, 0xd0, 0xbb, 0x30,
+ 0x70, 0xd0, 0x75, 0x50,
+ 0xdd, 0xa0, 0xd2, 0x2d,
+ 0x7f, 0x78, 0x51, 0xd0,
+ 0x99, 0x30, 0xd8, 0x28,
+ 0x72, 0x27, 0x7f, 0xe0,
+ 0xdd, 0x30, 0xd0, 0xaa,
+ 0x30, 0xe8, 0x38, 0xd8,
+ 0x71, 0xa0, 0x99, 0x30,
+ 0x20, 0xee, 0x30, 0xa8,
+ 0x08, 0x28, 0x61, 0xd2,
+ 0x2d, 0x7f, 0x22, 0x22,
+ 0x7f, 0xe0, 0xdd, 0x30,
+ 0xd0, 0xbb, 0x30, 0xe8,
+ 0x18, 0xd8, 0x41, 0x20,
+ 0xee, 0x30, 0xd2, 0x2d,
+ 0x7f, 0x90, 0x20, 0x74,
+ 0x2a, 0x23, 0xe0, 0xdd,
+ 0x30, 0x22, 0x02, 0x80,
+ 0xd0, 0xcc, 0x30, 0xd8,
+ 0x21, 0xc0, 0x40, 0x74,
+ 0xc0, 0xe8, 0x75, 0xea,
+ 0xe3, 0x4a, 0x43, 0x42,
+ 0x04, 0x80, 0xd2, 0x2d,
+ 0x7f, 0xe2, 0x0e, 0x80,
+ 0xd0, 0xaa, 0x30, 0x80,
+ 0xee, 0x01, 0xa0, 0x77,
+ 0x30, 0xa8, 0x48, 0x70,
+ 0x66, 0x30, 0x60, 0x70,
+ 0x74, 0x60, 0xd8, 0x75,
+ 0xda, 0xd3, 0x7a, 0x73,
+ 0x72, 0x07, 0x80, 0xd2,
+ 0x0d, 0x80, 0xa0, 0x77,
+ 0x30, 0xa8, 0x58, 0x80,
+ 0xdd, 0x01, 0xa0, 0x44,
+ 0x30, 0xc0, 0xa0, 0x75,
+ 0xaa, 0xa3, 0xa2, 0x0a,
+ 0x80, 0xc0, 0xc8, 0x74,
+ 0x00, 0xaa, 0x11, 0xd0,
+ 0xaa, 0x30, 0x60, 0xd8,
+ 0x74, 0x60, 0x60, 0x75,
+ 0xda, 0xd3, 0xd2, 0x0d,
+ 0x80, 0x6a, 0x63, 0x62,
+ 0x06, 0x80, 0x80, 0xdd,
+ 0x11, 0xd0, 0x44, 0x30,
+ 0xb0, 0xd8, 0x75, 0xda,
+ 0xd3, 0xd2, 0x0d, 0x80,
+ 0x00, 0x66, 0x11, 0x80,
+ 0xdd, 0x01, 0xd0, 0x66,
+ 0x30, 0xb0, 0xd8, 0x74,
+ 0xda, 0xd3, 0xd2, 0x0d,
+ 0x80, 0xca, 0xc3, 0x80,
+ 0xdd, 0x11, 0xd0, 0x77,
+ 0x30, 0x90, 0xd0, 0x75,
+ 0xda, 0xd3, 0xd2, 0x0d,
+ 0x80, 0xc2, 0x0c, 0x80,
+ 0x00, 0xdd, 0x11, 0xe0,
+ 0xdd, 0x30, 0xd0, 0x77,
+ 0x30, 0xd8, 0x68, 0x80,
+ 0xcc, 0x11, 0xd0, 0x22,
+ 0x30, 0xc0, 0x22, 0x30,
+ 0x60, 0x22, 0x30, 0x90,
+ 0xc8, 0x75, 0xb0, 0x60,
+ 0x75, 0xca, 0xc3, 0x90,
+ 0x98, 0x74, 0x9a, 0x93,
+ 0xc2, 0x0c, 0x80, 0x6a,
+ 0x63, 0x62, 0x06, 0x80,
+ 0x80, 0xcc, 0x01, 0x00,
+ 0x66, 0x11, 0xc0, 0x66,
+ 0x30, 0x60, 0x44, 0x30,
+ 0x70, 0xe8, 0x41, 0xc2,
+ 0x09, 0x80, 0xd8, 0x78,
+ 0xb0, 0xf0, 0x74, 0xfa,
+ 0xf3, 0xf2, 0x0f, 0x80,
+ 0x68, 0x01, 0xd0, 0xff,
+ 0x30, 0x72, 0x46, 0x00,
+ 0xe2, 0x46, 0x01, 0x42,
+ 0x46, 0x04, 0x70, 0xe0,
+ 0xf5, 0xe2, 0x46, 0x02,
+ 0x70, 0xe8, 0x75, 0xe2,
+ 0x46, 0x03, 0x22, 0x46,
+ 0x08, 0x40, 0xe8, 0x41,
+ 0xe2, 0x46, 0x05, 0x40,
+ 0xe0, 0xf5, 0xe2, 0x46,
+ 0x06, 0x40, 0xe8, 0x75,
+ 0xe2, 0x46, 0x07, 0x20,
+ 0xe8, 0x41, 0xe2, 0x46,
+ 0x09, 0x20, 0xe0, 0xf5,
+ 0xe2, 0x46, 0x0a, 0x20,
+ 0xe8, 0x75, 0xe2, 0x46,
+ 0x0b, 0x80, 0x2c, 0x11,
+ 0x20, 0xff, 0x30, 0xa0,
+ 0xff, 0x30, 0xf2, 0x46,
+ 0x0c, 0xf0, 0xc8, 0x41,
+ 0xf0, 0x20, 0xf5, 0x22,
+ 0x46, 0x0e, 0xc2, 0x46,
+ 0x0d, 0x0c, 0x02, 0xf0,
+ 0xf8, 0x75, 0xf2, 0x46,
+ 0x0f, 0x1d, 0xf0, 0xf1,
+ 0xd7, 0xfb, 0x52, 0xdf,
+ 0x08, 0xf2, 0xdf, 0x0c,
+ 0xe6, 0x13, 0x02, 0x46,
+ 0x74, 0x00, 0x0b, 0x33,
+ 0xe8, 0x38, 0xc8, 0x28,
+ 0x20, 0xd0, 0x74, 0x20,
+ 0xb0, 0x75, 0x90, 0xa0,
+ 0x75, 0x49, 0x81, 0x70,
+ 0x68, 0x75, 0xf0, 0x66,
+ 0xa0, 0x90, 0x48, 0x75,
+ 0x50, 0xaa, 0xa0, 0x50,
+ 0xbb, 0xa0, 0xb2, 0x2b,
+ 0x7f, 0xa2, 0x2a, 0x7f,
+ 0xf0, 0x44, 0xa0, 0x62,
+ 0x26, 0x7f, 0xf1, 0xc8,
+ 0xfb, 0x42, 0x24, 0x7f,
+ 0xa0, 0x66, 0x30, 0xb0,
+ 0x44, 0x30, 0xf0, 0xdd,
+ 0xa0, 0xd2, 0x2d, 0x7f,
+ 0x90, 0xb8, 0x74, 0xa2,
+ 0xdf, 0x04, 0x90, 0x90,
+ 0x74, 0xa0, 0xbb, 0xa0,
+ 0xd0, 0xcc, 0x30, 0xf0,
+ 0x99, 0xa0, 0xd8, 0x81,
+ 0x92, 0x29, 0x7f, 0xb2,
+ 0x2b, 0x7f, 0x90, 0xee,
+ 0x30, 0xc0, 0xbb, 0x30,
+ 0xd0, 0xd0, 0x75, 0xc2,
+ 0xdf, 0x0c, 0x50, 0xdd,
+ 0xa0, 0x20, 0x98, 0x75,
+ 0x58, 0x18, 0xd2, 0x2d,
+ 0x7f, 0x20, 0x28, 0x74,
+ 0xc0, 0x99, 0xa0, 0xa0,
+ 0x22, 0xa0, 0x22, 0x22,
+ 0x7f, 0x92, 0x29, 0x7f,
+ 0x70, 0xc8, 0x74, 0xa0,
+ 0xcc, 0xa0, 0xc2, 0x2c,
+ 0x7f, 0xd0, 0x99, 0x30,
+ 0xe0, 0xcc, 0x30, 0xe8,
+ 0x81, 0xc0, 0x99, 0x30,
+ 0xe0, 0xc0, 0x74, 0xf0,
+ 0xcc, 0xa0, 0xc2, 0x2c,
+ 0x7f, 0xe0, 0xe8, 0x75,
+ 0xc0, 0x55, 0x30, 0x50,
+ 0x22, 0x30, 0xc2, 0xdf,
+ 0x0c, 0x70, 0x50, 0x75,
+ 0x20, 0x26, 0x30, 0xc0,
+ 0xee, 0xa0, 0xe2, 0x2e,
+ 0x7f, 0x62, 0xdf, 0x08,
+ 0x60, 0x55, 0xa0, 0x52,
+ 0x25, 0x7f, 0x99, 0x41,
+ 0x50, 0xee, 0x30, 0xb0,
+ 0xee, 0x30, 0x58, 0x81,
+ 0x70, 0xb0, 0x74, 0xe0,
+ 0xd8, 0x74, 0x78, 0x08,
+ 0x50, 0x58, 0x74, 0xa0,
+ 0xdd, 0xa0, 0xf0, 0xbb,
+ 0xa0, 0xb2, 0x2b, 0x7f,
+ 0xd9, 0x61, 0xa0, 0x55,
+ 0xa0, 0x52, 0x25, 0x7f,
+ 0x90, 0xd0, 0x74, 0xb0,
+ 0x77, 0x30, 0xf0, 0xdd,
+ 0xa0, 0xd9, 0x21, 0x70,
+ 0x55, 0x30, 0x20, 0xb8,
+ 0x74, 0x90, 0x70, 0x75,
+ 0x50, 0x44, 0x30, 0xa0,
+ 0xbb, 0xa0, 0xb2, 0x2b,
+ 0x7f, 0x49, 0x51, 0x40,
+ 0x58, 0x74, 0x40, 0xd0,
+ 0x74, 0x60, 0x77, 0xa0,
+ 0x72, 0x27, 0x7f, 0xf0,
+ 0xdd, 0xa0, 0xa0, 0x55,
+ 0xa0, 0x59, 0x71, 0xd2,
+ 0x2d, 0x7f, 0x90, 0x58,
+ 0x74, 0x40, 0x48, 0x75,
+ 0xe0, 0x98, 0x75, 0xc0,
+ 0x44, 0xa0, 0xa0, 0x55,
+ 0xa0, 0x52, 0x25, 0x7f,
+ 0x42, 0x24, 0x7f, 0xe0,
+ 0xc0, 0x74, 0x20, 0xa0,
+ 0x74, 0xe0, 0xe0, 0x75,
+ 0xf0, 0xcc, 0xa0, 0xf0,
+ 0xaa, 0xa0, 0xa2, 0x2a,
+ 0x7f, 0x70, 0x44, 0x30,
+ 0xc2, 0x2c, 0x7f, 0x78,
+ 0x41, 0xf2, 0xdf, 0x0c,
+ 0xf0, 0x99, 0xa0, 0x70,
+ 0x78, 0x75, 0x20, 0xf0,
+ 0x75, 0x92, 0x29, 0x7f,
+ 0x20, 0x28, 0x75, 0x60,
+ 0xff, 0xa0, 0xf2, 0x2f,
+ 0x7f, 0x68, 0x51, 0xf0,
+ 0x99, 0x30, 0xf1, 0x7b,
+ 0xfb, 0x60, 0x60, 0x75,
+ 0xf0, 0x22, 0xa0, 0xf0,
+ 0x77, 0xa0, 0x72, 0x27,
+ 0x7f, 0x22, 0x22, 0x7f,
+ 0xf2, 0xdf, 0xfc, 0xf0,
+ 0x66, 0xa0, 0xf0, 0xee,
+ 0xa0, 0xe2, 0x2e, 0x7f,
+ 0x62, 0x26, 0x7f, 0xf2,
+ 0xdf, 0x04, 0x60, 0x22,
+ 0x30, 0x68, 0x68, 0xe0,
+ 0x77, 0x30, 0xc0, 0x66,
+ 0x30, 0xc8, 0x48, 0x60,
+ 0x55, 0x30, 0x50, 0x22,
+ 0x30, 0x68, 0x58, 0x58,
+ 0x61, 0xd0, 0xcc, 0x30,
+ 0xc0, 0xbb, 0x30, 0xa0,
+ 0x66, 0x30, 0xc8, 0x21,
+ 0x52, 0x25, 0x7f, 0xb0,
+ 0x77, 0x30, 0xa8, 0x71,
+ 0xb8, 0x78, 0x82, 0xc8,
+ 0x20, 0xa2, 0x2a, 0x7f,
+ 0x60, 0x55, 0x30, 0xc2,
+ 0x2c, 0x7f, 0x50, 0x44,
+ 0x30, 0x51, 0x64, 0xfb,
+ 0xc0, 0xbb, 0x30, 0xb0,
+ 0xaa, 0x30, 0xa0, 0x99,
+ 0x30, 0x56, 0xd3, 0xe2,
+ 0x40, 0xa8, 0x74, 0x70,
+ 0xc8, 0x74, 0x90, 0x60,
+ 0x74, 0x20, 0xe8, 0x74,
+ 0xb1, 0x5f, 0xfb, 0x90,
+ 0xd8, 0x74, 0x32, 0xdb,
+ 0xfc, 0xb0, 0xdd, 0xa0,
+ 0xb0, 0xee, 0xa0, 0x30,
+ 0x66, 0xa0, 0xb0, 0xcc,
+ 0xa0, 0xb0, 0xaa, 0xa0,
+ 0xa2, 0x2a, 0x7f, 0xc9,
+ 0x71, 0x69, 0x91, 0xe9,
+ 0x51, 0xd9, 0x41, 0x70,
+ 0xe0, 0x74, 0x70, 0xd8,
+ 0x75, 0x40, 0x68, 0x75,
+ 0x40, 0xc0, 0x74, 0x30,
+ 0xcc, 0xa0, 0xf0, 0x66,
+ 0xa0, 0xf0, 0xdd, 0xa0,
+ 0x30, 0xee, 0xa0, 0xe2,
+ 0x2e, 0x7f, 0xd2, 0x2d,
+ 0x7f, 0x62, 0x26, 0x7f,
+ 0x70, 0x70, 0x75, 0xc9,
+ 0x21, 0x20, 0xb0, 0x74,
+ 0x20, 0xc0, 0x75, 0x30,
+ 0xbb, 0xa0, 0x50, 0x77,
+ 0xa0, 0x72, 0x27, 0x7f,
+ 0x90, 0x30, 0x75, 0xb9,
+ 0x61, 0x50, 0xcc, 0xa0,
+ 0xc2, 0x2c, 0x7f, 0x20,
+ 0xb8, 0x75, 0x90, 0x98,
+ 0x75, 0x50, 0x33, 0xa0,
+ 0x32, 0x23, 0x7f, 0x70,
+ 0x66, 0x30, 0xf0, 0x99,
+ 0xa0, 0xf0, 0xbb, 0xa0,
+ 0xb2, 0x2b, 0x7f, 0x92,
+ 0x29, 0x7f, 0x78, 0x41,
+ 0x30, 0xdd, 0x30, 0x72,
+ 0x27, 0x7f, 0x40, 0x30,
+ 0x75, 0xc0, 0x99, 0x30,
+ 0x48, 0x68, 0xc8, 0x08,
+ 0x50, 0x33, 0xa0, 0x22,
+ 0x23, 0x7f, 0xe0, 0xcc,
+ 0x30, 0x38, 0x21, 0xe8,
+ 0x38, 0x20, 0xbb, 0x30,
+ 0xc0, 0xaa, 0x30, 0x32,
+ 0x23, 0x7f, 0xc8, 0x71,
+ 0xa0, 0x99, 0x30, 0x28,
+ 0x91, 0xa8, 0x28, 0x22,
+ 0x22, 0x7f, 0xc2, 0x2c,
+ 0x7f, 0x20, 0xee, 0x30,
+ 0xe0, 0xcc, 0x30, 0x28,
+ 0x18, 0xe8, 0x51, 0xc0,
+ 0xbb, 0x30, 0x30, 0x22,
+ 0x30, 0xc8, 0x61, 0x31,
+ 0x2e, 0xfb, 0xe2, 0x2e,
+ 0x7f, 0xc2, 0x2c, 0x7f,
+ 0x20, 0xee, 0x30, 0xe0,
+ 0xdd, 0x30, 0xc0, 0xaa,
+ 0x30, 0xb0, 0xe8, 0x75,
+ 0xa0, 0x77, 0x30, 0x70,
+ 0x66, 0x30, 0xea, 0xe3,
+ 0x78, 0x58, 0xe2, 0x0e,
+ 0x80, 0xd0, 0xa0, 0x75,
+ 0x60, 0xc8, 0x75, 0x60,
+ 0x20, 0x74, 0x2a, 0x23,
+ 0xca, 0xc3, 0xaa, 0xa3,
+ 0x80, 0xee, 0x01, 0xa2,
+ 0x0a, 0x80, 0xc2, 0x0c,
+ 0x80, 0x22, 0x02, 0x80,
+ 0x80, 0xcc, 0x01, 0x40,
+ 0x22, 0x30, 0x00, 0xaa,
+ 0x11, 0xd0, 0x40, 0x74,
+ 0xc0, 0xaa, 0x30, 0x4a,
+ 0x43, 0x60, 0xc0, 0x75,
+ 0x42, 0x04, 0x80, 0x60,
+ 0x68, 0x74, 0xca, 0xc3,
+ 0xc2, 0x0c, 0x80, 0x70,
+ 0x44, 0x30, 0x6a, 0x63,
+ 0x62, 0x06, 0x80, 0xd0,
+ 0x78, 0x75, 0x00, 0xcc,
+ 0x11, 0xd0, 0xd8, 0x74,
+ 0x7a, 0x73, 0x72, 0x07,
+ 0x80, 0xda, 0xd3, 0xe0,
+ 0xcc, 0x30, 0x80, 0x66,
+ 0x11, 0xe8, 0x48, 0x60,
+ 0x44, 0x30, 0xd2, 0x0d,
+ 0x80, 0xb0, 0x68, 0x74,
+ 0x6a, 0x63, 0x62, 0x06,
+ 0x80, 0x80, 0x77, 0x01,
+ 0x80, 0x66, 0x11, 0x60,
+ 0x22, 0x30, 0x90, 0x60,
+ 0x75, 0x6a, 0x63, 0x62,
+ 0x06, 0x80, 0x80, 0xdd,
+ 0x11, 0x00, 0x66, 0x11,
+ 0x70, 0x66, 0x30, 0x60,
+ 0x22, 0x30, 0x90, 0x70,
+ 0x74, 0xb0, 0x60, 0x75,
+ 0x7a, 0x73, 0x72, 0x07,
+ 0x80, 0x6a, 0x63, 0x62,
+ 0x06, 0x80, 0xe0, 0x77,
+ 0x30, 0xd0, 0x77, 0x30,
+ 0xc0, 0x77, 0x30, 0x00,
+ 0x66, 0x11, 0x90, 0xc8,
+ 0x75, 0x90, 0x98, 0x74,
+ 0xca, 0xc3, 0xc2, 0x0c,
+ 0x80, 0x9a, 0x93, 0x80,
+ 0xcc, 0x01, 0xc0, 0x66,
+ 0x30, 0x60, 0x44, 0x30,
+ 0x06, 0xff, 0xfe, 0x00,
+ 0x36, 0x61, 0x00, 0x0c,
+ 0x1b, 0xcd, 0x04, 0xdd,
+ 0x05, 0xa1, 0xf5, 0xfa,
+ 0xa9, 0x01, 0x25, 0x7c,
+ 0xff, 0x28, 0x03, 0xec,
+ 0x12, 0xa8, 0x01, 0x0c,
+ 0x1b, 0xcd, 0x04, 0xdd,
+ 0x05, 0x25, 0x7b, 0xff,
+ 0xa2, 0xc4, 0x90, 0xb2,
+ 0xc4, 0x80, 0x82, 0x0a,
+ 0x7f, 0x1b, 0x88, 0x80,
+ 0x80, 0x74, 0x82, 0x4a,
+ 0x7f, 0xcc, 0x38, 0x0b,
+ 0xaa, 0xb7, 0x9a, 0xed,
+ 0x92, 0x06, 0x00, 0x1b,
+ 0xb2, 0x5a, 0xa2, 0xa2,
+ 0x0a, 0x00, 0xb0, 0xb0,
+ 0x34, 0xb9, 0x03, 0x0c,
+ 0x02, 0xa0, 0x99, 0x30,
+ 0x92, 0x47, 0x0c, 0x1d,
+ 0xf0, 0x00, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0xc0,
+ 0x20, 0x00, 0x28, 0x02,
+ 0x1d, 0xf0, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0xc0,
+ 0x20, 0x00, 0x39, 0x02,
+ 0x1d, 0xf0, 0x00, 0x00,
+ 0x36, 0xe1, 0x01, 0xdd,
+ 0x07, 0xcd, 0x03, 0xbd,
+ 0x02, 0xad, 0x01, 0x65,
+ 0x45, 0xff, 0xcd, 0x05,
+ 0xbd, 0x04, 0xad, 0x01,
+ 0x65, 0xef, 0x06, 0xbd,
+ 0x06, 0xad, 0x01, 0x65,
+ 0x3e, 0xff, 0xad, 0x01,
+ 0x0c, 0x0b, 0xc2, 0xa0,
+ 0xcc, 0xa5, 0xee, 0x07,
+ 0x1d, 0xf0, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0xa1,
+ 0xd2, 0xfa, 0xd2, 0x02,
+ 0x01, 0xc2, 0x02, 0x02,
+ 0xb2, 0x02, 0x03, 0x80,
+ 0xcc, 0x11, 0xc0, 0xbb,
+ 0x20, 0xc2, 0x02, 0x00,
+ 0x00, 0xdd, 0x11, 0x80,
+ 0xcc, 0x01, 0xd0, 0xcc,
+ 0x20, 0xc0, 0xbb, 0x20,
+ 0x25, 0xfa, 0xff, 0xa1,
+ 0xc9, 0xfa, 0xd2, 0x02,
+ 0x05, 0xc2, 0x02, 0x06,
+ 0xb2, 0x02, 0x07, 0x80,
+ 0xcc, 0x11, 0xc0, 0xbb,
+ 0x20, 0xc2, 0x02, 0x04,
+ 0x00, 0xdd, 0x11, 0x80,
+ 0xcc, 0x01, 0xd0, 0xcc,
+ 0x20, 0xc0, 0xbb, 0x20,
+ 0xe5, 0xf7, 0xff, 0xa1,
+ 0xc0, 0xfa, 0xd2, 0x02,
+ 0x09, 0xc2, 0x02, 0x0a,
+ 0xb2, 0x02, 0x0b, 0x80,
+ 0xcc, 0x11, 0xc0, 0xbb,
+ 0x20, 0xc2, 0x02, 0x08,
+ 0x00, 0xdd, 0x11, 0x80,
+ 0xcc, 0x01, 0xd0, 0xcc,
+ 0x20, 0xc0, 0xbb, 0x20,
+ 0xa5, 0xf5, 0xff, 0xa1,
+ 0xb7, 0xfa, 0xd2, 0x02,
+ 0x0d, 0xc2, 0x02, 0x0e,
+ 0xb2, 0x02, 0x0f, 0x80,
+ 0xcc, 0x11, 0xc0, 0xbb,
+ 0x20, 0xc2, 0x02, 0x0c,
+ 0x00, 0xdd, 0x11, 0x80,
+ 0xcc, 0x01, 0xd0, 0xcc,
+ 0x20, 0xc0, 0xbb, 0x20,
+ 0x65, 0xf3, 0xff, 0xa1,
+ 0x98, 0xfa, 0x65, 0xf2,
+ 0xff, 0x22, 0xa2, 0x00,
+ 0x97, 0xea, 0x08, 0xa1,
+ 0x95, 0xfa, 0xa5, 0xf1,
+ 0xff, 0x27, 0x0a, 0xf6,
+ 0xa1, 0xaa, 0xfa, 0x25,
+ 0xf1, 0xff, 0xa2, 0x43,
+ 0x0f, 0xa0, 0xd8, 0x41,
+ 0xa0, 0xe0, 0xf5, 0xa0,
+ 0xf8, 0x75, 0xf2, 0x43,
+ 0x0c, 0xe2, 0x43, 0x0d,
+ 0xd2, 0x43, 0x0e, 0xa1,
+ 0xa4, 0xfa, 0x65, 0xef,
+ 0xff, 0xa2, 0x43, 0x0b,
+ 0xa0, 0x88, 0x41, 0xa0,
+ 0x90, 0xf5, 0xa0, 0xb8,
+ 0x75, 0xb2, 0x43, 0x08,
+ 0x92, 0x43, 0x09, 0x82,
+ 0x43, 0x0a, 0xa1, 0x9e,
+ 0xfa, 0xa5, 0xed, 0xff,
+ 0xa2, 0x43, 0x07, 0xa0,
+ 0xc8, 0x41, 0xa0, 0xd0,
+ 0xf5, 0xa0, 0xe8, 0x75,
+ 0xe2, 0x43, 0x04, 0xd2,
+ 0x43, 0x05, 0xc2, 0x43,
+ 0x06, 0xa1, 0x98, 0xfa,
+ 0xe5, 0xeb, 0xff, 0xa2,
+ 0x43, 0x03, 0xa0, 0xf8,
+ 0x41, 0xa0, 0x20, 0xf5,
+ 0xa0, 0x88, 0x75, 0x82,
+ 0x43, 0x00, 0x22, 0x43,
+ 0x01, 0xf2, 0x43, 0x02,
+ 0x0c, 0x02, 0x1d, 0xf0,
+ 0x36, 0x41, 0x00, 0xa1,
+ 0x91, 0xfa, 0xd2, 0x02,
+ 0x0d, 0xc2, 0x02, 0x0e,
+ 0xb2, 0x02, 0x0f, 0x80,
+ 0xcc, 0x11, 0xc0, 0xbb,
+ 0x20, 0xc2, 0x02, 0x0c,
+ 0x00, 0xdd, 0x11, 0x80,
+ 0xcc, 0x01, 0xd0, 0xcc,
+ 0x20, 0xc0, 0xbb, 0x20,
+ 0xa5, 0xe8, 0xff, 0xa1,
+ 0x89, 0xfa, 0xd2, 0x02,
+ 0x09, 0xc2, 0x02, 0x0a,
+ 0xb2, 0x02, 0x0b, 0x80,
+ 0xcc, 0x11, 0xc0, 0xbb,
+ 0x20, 0xc2, 0x02, 0x08,
+ 0x00, 0xdd, 0x11, 0x80,
+ 0xcc, 0x01, 0xd0, 0xcc,
+ 0x20, 0xc0, 0xbb, 0x20,
+ 0x65, 0xe6, 0xff, 0xa1,
+ 0x81, 0xfa, 0xd2, 0x02,
+ 0x05, 0xc2, 0x02, 0x06,
+ 0xb2, 0x02, 0x07, 0x80,
+ 0xcc, 0x11, 0xc0, 0xbb,
+ 0x20, 0xc2, 0x02, 0x04,
+ 0x00, 0xdd, 0x11, 0x80,
+ 0xcc, 0x01, 0xd0, 0xcc,
+ 0x20, 0xc0, 0xbb, 0x20,
+ 0x25, 0xe4, 0xff, 0xa1,
+ 0x79, 0xfa, 0xd2, 0x02,
+ 0x01, 0xc2, 0x02, 0x02,
+ 0xb2, 0x02, 0x03, 0x80,
+ 0xcc, 0x11, 0xc0, 0xbb,
+ 0x20, 0xc2, 0x02, 0x00,
+ 0x00, 0xdd, 0x11, 0x80,
+ 0xcc, 0x01, 0xd0, 0xcc,
+ 0x20, 0xc0, 0xbb, 0x20,
+ 0xe5, 0xe1, 0xff, 0xbd,
+ 0x02, 0xa1, 0x66, 0xfa,
+ 0xa5, 0xd0, 0x02, 0x1d,
+ 0xf0, 0x00, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0xb1,
+ 0x6e, 0xfa, 0x91, 0x6c,
+ 0xfa, 0xc2, 0xd2, 0xff,
+ 0xc2, 0x2c, 0x3f, 0x22,
+ 0xc2, 0xfc, 0x82, 0x29,
+ 0x7f, 0xad, 0x02, 0xc0,
+ 0x88, 0xc0, 0x82, 0x69,
+ 0x7f, 0xe5, 0xd0, 0x07,
+ 0xad, 0x02, 0x65, 0x44,
+ 0x07, 0x1d, 0xf0, 0x00,
+ 0x36, 0x41, 0x00, 0x4b,
+ 0xa2, 0x65, 0x4d, 0x07,
+ 0x91, 0x62, 0xfa, 0x29,
+ 0x0a, 0x82, 0x29, 0x7f,
+ 0xb2, 0x29, 0x80, 0x8a,
+ 0x82, 0x82, 0x69, 0x7f,
+ 0x4b, 0x2a, 0xb0, 0x88,
+ 0x73, 0x82, 0x69, 0x80,
+ 0x1d, 0xf0, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0xbd,
+ 0x03, 0x47, 0x92, 0x03,
+ 0x4d, 0x03, 0xbd, 0x02,
+ 0xb7, 0x12, 0x07, 0xad,
+ 0x02, 0x25, 0xc5, 0x00,
+ 0x56, 0x4a, 0x08, 0x0c,
+ 0x13, 0x39, 0x02, 0x38,
+ 0x14, 0xa8, 0x24, 0x9c,
+ 0x43, 0xb2, 0xda, 0xfe,
+ 0xa0, 0xa3, 0xa0, 0xa2,
+ 0xda, 0xfe, 0xc2, 0x2a,
+ 0x7f, 0xa2, 0xca, 0xfc,
+ 0xcc, 0x3c, 0x0b, 0x33,
+ 0xb7, 0x9a, 0xf2, 0xad,
+ 0x02, 0xbd, 0x03, 0x25,
+ 0xd4, 0x00, 0x56, 0xaa,
+ 0x05, 0xc8, 0x24, 0xb8,
+ 0x22, 0xac, 0x63, 0x0c,
+ 0x05, 0x0c, 0x04, 0xe8,
+ 0x0b, 0x1b, 0x44, 0x5a,
+ 0xee, 0xe9, 0x0b, 0xd8,
+ 0x0c, 0x50, 0x8e, 0x62,
+ 0xea, 0x5d, 0x59, 0x0b,
+ 0x4b, 0xbb, 0x98, 0x0c,
+ 0x4b, 0xcc, 0x90, 0x55,
+ 0x62, 0x8a, 0x55, 0x47,
+ 0x93, 0xe0, 0x4d, 0x03,
+ 0xc6, 0x00, 0x00, 0x0c,
+ 0x04, 0x0c, 0x05, 0xac,
+ 0x55, 0xe0, 0x34, 0x11,
+ 0xf8, 0x12, 0xf7, 0x34,
+ 0x0c, 0xad, 0x02, 0x1b,
+ 0xb4, 0xa5, 0xcf, 0x00,
+ 0xdc, 0x4a, 0xb8, 0x22,
+ 0x3a, 0xbb, 0x1b, 0x44,
+ 0xc8, 0x0b, 0x4b, 0x33,
+ 0x5a, 0xcc, 0xc9, 0x0b,
+ 0x50, 0x5c, 0x62, 0x4b,
+ 0xbb, 0x56, 0xb5, 0xfd,
+ 0x2d, 0x0a, 0x1d, 0xf0,
+ 0x36, 0x61, 0x00, 0xad,
+ 0x03, 0xbd, 0x04, 0x65,
+ 0x5c, 0x00, 0xd6, 0x4a,
+ 0x00, 0x3c, 0x25, 0xc6,
+ 0x14, 0x00, 0xad, 0x01,
+ 0xa5, 0x4a, 0x01, 0x47,
+ 0x92, 0x0c, 0xbd, 0x04,
+ 0xad, 0x01, 0x65, 0xba,
+ 0x00, 0x5d, 0x0a, 0xfc,
+ 0xaa, 0x4d, 0x01, 0x37,
+ 0x12, 0x0a, 0xbd, 0x03,
+ 0xad, 0x02, 0x65, 0xb9,
+ 0x00, 0x5d, 0x0a, 0xec,
+ 0xaa, 0x0c, 0x18, 0x89,
+ 0x02, 0xa8, 0x14, 0xb8,
+ 0x24, 0x9c, 0x7a, 0xd2,
+ 0xdb, 0xfe, 0xb0, 0xca,
+ 0xa0, 0xc2, 0xdc, 0xfe,
+ 0xe2, 0x2c, 0x7f, 0xc2,
+ 0xcc, 0xfc, 0xcc, 0x8e,
+ 0x0b, 0xaa, 0xd7, 0x9c,
+ 0xf2, 0x46, 0x00, 0x00,
+ 0xb8, 0x24, 0xc8, 0x22,
+ 0xe5, 0x33, 0x00, 0x0c,
+ 0x05, 0xad, 0x01, 0x25,
+ 0x47, 0x01, 0x2d, 0x05,
+ 0x1d, 0xf0, 0x00, 0x00,
+ 0x36, 0x01, 0x01, 0x5d,
+ 0x02, 0xad, 0x04, 0xe5,
+ 0xc1, 0x00, 0xcc, 0x2a,
+ 0x3c, 0xc2, 0x1d, 0xf0,
+ 0xad, 0x01, 0x25, 0x44,
+ 0x01, 0xcb, 0xa1, 0xe5,
+ 0x43, 0x01, 0xa2, 0xc1,
+ 0x18, 0x65, 0x43, 0x01,
+ 0xa2, 0xc1, 0x24, 0x25,
+ 0x43, 0x01, 0xa2, 0xc1,
+ 0x30, 0xa5, 0x42, 0x01,
+ 0xad, 0x03, 0xbd, 0x04,
+ 0xe5, 0x52, 0x00, 0xd6,
+ 0x2a, 0x05, 0x8c, 0x92,
+ 0xbd, 0x03, 0xad, 0x05,
+ 0xa5, 0xb1, 0x00, 0x2d,
+ 0x0a, 0xec, 0x6a, 0x0c,
+ 0x02, 0x1d, 0xf0, 0xad,
+ 0x01, 0xcb, 0xb1, 0xe5,
+ 0x36, 0x01, 0x96, 0x0a,
+ 0x0f, 0xad, 0x01, 0xc8,
+ 0xf1, 0x98, 0x81, 0xbd,
+ 0x01, 0xca, 0x99, 0x88,
+ 0x09, 0xcb, 0xc1, 0x1b,
+ 0x88, 0x89, 0x09, 0xa5,
+ 0xdc, 0x00, 0x2d, 0x0a,
+ 0x16, 0xba, 0xfd, 0xad,
+ 0x01, 0xa5, 0x3f, 0x01,
+ 0xcb, 0xa1, 0x65, 0x3f,
+ 0x01, 0xa2, 0xc1, 0x18,
+ 0xe5, 0x3e, 0x01, 0xa2,
+ 0xc1, 0x24, 0xa5, 0x3e,
+ 0x01, 0xa2, 0xc1, 0x30,
+ 0x25, 0x3e, 0x01, 0x1d,
+ 0xf0, 0xad, 0x01, 0xbd,
+ 0x03, 0xa5, 0xac, 0x00,
+ 0x2d, 0x0a, 0x56, 0x5a,
+ 0xfd, 0xbd, 0x04, 0xcb,
+ 0xa1, 0xe5, 0xab, 0x00,
+ 0x2d, 0x0a, 0x56, 0x9a,
+ 0xfc, 0x0c, 0x14, 0x49,
+ 0x01, 0x49, 0x31, 0xb8,
+ 0x13, 0xa2, 0xc1, 0x18,
+ 0x2b, 0xbb, 0x25, 0xbc,
+ 0x00, 0x2d, 0x0a, 0x56,
+ 0x4a, 0xfb, 0xa2, 0xc1,
+ 0x18, 0x0c, 0x0b, 0x65,
+ 0xb8, 0x00, 0x2d, 0x0a,
+ 0x56, 0x7a, 0xfa, 0xa2,
+ 0xc1, 0x24, 0x0c, 0x2b,
+ 0x65, 0xba, 0x00, 0x2d,
+ 0x0a, 0x56, 0xaa, 0xf9,
+ 0xa2, 0xc1, 0x30, 0x0c,
+ 0x3b, 0xa5, 0xb9, 0x00,
+ 0x2d, 0x0a, 0x56, 0xda,
+ 0xf8, 0xcb, 0xa1, 0xe5,
+ 0xac, 0x00, 0x1c, 0xfb,
+ 0xa0, 0xa0, 0x44, 0x1c,
+ 0xec, 0xa7, 0x3c, 0x1d,
+ 0xa0, 0x4b, 0xc0, 0xad,
+ 0x01, 0xbd, 0x04, 0xe5,
+ 0x9b, 0x00, 0x2d, 0x0a,
+ 0x56, 0xfa, 0xf6, 0xcb,
+ 0xa1, 0xbd, 0x04, 0x25,
+ 0x9b, 0x00, 0x2d, 0x0a,
+ 0x56, 0x3a, 0xf6, 0x46,
+ 0x00, 0x00, 0x0c, 0x04,
+ 0xcb, 0xa1, 0xb8, 0x11,
+ 0x78, 0x41, 0x0b, 0x6b,
+ 0x70, 0xbb, 0xc0, 0x0b,
+ 0x77, 0xb0, 0xbb, 0x11,
+ 0x25, 0x99, 0x00, 0x2d,
+ 0x0a, 0x56, 0x6a, 0xf4,
+ 0xad, 0x01, 0xcb, 0xb1,
+ 0xe5, 0x28, 0x01, 0x96,
+ 0xda, 0x00, 0x70, 0xc6,
+ 0xc0, 0xc2, 0x61, 0x14,
+ 0xe0, 0xcc, 0x11, 0xc9,
+ 0xf1, 0x06, 0xc5, 0xff,
+ 0x70, 0xd6, 0xc0, 0xd2,
+ 0x61, 0x14, 0xb2, 0x21,
+ 0x14, 0xcb, 0xa1, 0xb0,
+ 0xbb, 0x11, 0xb2, 0x61,
+ 0x13, 0xa5, 0x37, 0x00,
+ 0x2d, 0x0a, 0x56, 0x5a,
+ 0xf1, 0xdd, 0x06, 0x42,
+ 0x61, 0x12, 0x67, 0x37,
+ 0x02, 0x46, 0x67, 0x00,
+ 0x62, 0x21, 0x13, 0x42,
+ 0x21, 0x14, 0xe0, 0xf7,
+ 0x11, 0xf2, 0x61, 0x11,
+ 0xe0, 0x44, 0x11, 0x62,
+ 0xc6, 0xe0, 0x62, 0x61,
+ 0x15, 0xe0, 0x6d, 0x11,
+ 0xd2, 0x61, 0x10, 0xe2,
+ 0x21, 0x11, 0xc8, 0x51,
+ 0x28, 0x81, 0xa8, 0x21,
+ 0x4a, 0x22, 0x6a, 0xaa,
+ 0xb8, 0x0a, 0xea, 0xcc,
+ 0xc8, 0x0c, 0x22, 0xd2,
+ 0xfe, 0xc7, 0x3b, 0x07,
+ 0x7c, 0xf8, 0x82, 0x62,
+ 0x7f, 0x86, 0x06, 0x00,
+ 0x0c, 0x0d, 0xa2, 0xda,
+ 0xff, 0xa2, 0x2a, 0x3f,
+ 0xa5, 0xdd, 0x06, 0x7c,
+ 0xfe, 0xcd, 0x0e, 0xcc,
+ 0x5b, 0xcc, 0x1b, 0xa7,
+ 0x3e, 0x01, 0xcd, 0x0a,
+ 0xc2, 0x62, 0x7f, 0xc8,
+ 0x81, 0x4a, 0xcc, 0xc2,
+ 0xdc, 0xfe, 0xb2, 0x2c,
+ 0x7f, 0x1b, 0xbb, 0xb2,
+ 0x6c, 0x7f, 0xe8, 0x81,
+ 0xa2, 0xc1, 0x24, 0x4a,
+ 0xee, 0xe2, 0xde, 0xfe,
+ 0xd2, 0x2e, 0x7f, 0x0c,
+ 0x0b, 0x0b, 0xdd, 0xd2,
+ 0x6e, 0x7f, 0x65, 0xa6,
+ 0x00, 0x2d, 0x0a, 0x56,
+ 0x8a, 0xe8, 0xd2, 0x21,
+ 0x11, 0xcc, 0x37, 0x0c,
+ 0x0e, 0x46, 0x02, 0x00,
+ 0xe8, 0x51, 0xda, 0xee,
+ 0xe2, 0xde, 0xff, 0xe2,
+ 0x2e, 0x3f, 0x88, 0xb1,
+ 0xa2, 0xc1, 0x24, 0xe9,
+ 0x08, 0xf8, 0x51, 0xe8,
+ 0xb1, 0xda, 0xdf, 0xd8,
+ 0x0d, 0xd9, 0x1e, 0xc8,
+ 0x81, 0xbd, 0x0a, 0x4a,
+ 0xcc, 0xc2, 0xdc, 0xff,
+ 0xc2, 0x2c, 0x3f, 0xa5,
+ 0x29, 0x00, 0x2d, 0x0a,
+ 0x56, 0xfa, 0xe4, 0xa2,
+ 0xc1, 0x30, 0x0c, 0x0b,
+ 0xe5, 0xa1, 0x00, 0x2d,
+ 0x0a, 0x56, 0x2a, 0xe4,
+ 0x92, 0x21, 0x10, 0xb6,
+ 0x29, 0x0c, 0x98, 0x21,
+ 0x6a, 0x99, 0x92, 0xd9,
+ 0xff, 0x92, 0x29, 0x3e,
+ 0x46, 0x00, 0x00, 0x0c,
+ 0x09, 0xb8, 0xe1, 0xa2,
+ 0x21, 0x10, 0x99, 0x0b,
+ 0xcc, 0x3a, 0x0c, 0x0e,
+ 0x46, 0x02, 0x00, 0xe8,
+ 0x21, 0x6a, 0xee, 0xe2,
+ 0xde, 0xff, 0xe2, 0x2e,
+ 0x3f, 0xa2, 0xc1, 0x24,
+ 0x88, 0xe1, 0xb2, 0xc1,
+ 0x30, 0xe9, 0x18, 0xf8,
+ 0x21, 0x88, 0xe1, 0x6a,
+ 0xff, 0xf8, 0x0f, 0xf9,
+ 0x28, 0xe5, 0x14, 0x01,
+ 0xa6, 0x1a, 0x02, 0xc6,
+ 0xd4, 0xff, 0xa2, 0xc1,
+ 0x24, 0xc8, 0x81, 0xcb,
+ 0xb1, 0x4a, 0xcc, 0xc2,
+ 0xdc, 0xff, 0xc2, 0x2c,
+ 0x3f, 0xa5, 0x22, 0x00,
+ 0x2d, 0x0a, 0x56, 0x1a,
+ 0xde, 0xa2, 0xc1, 0x24,
+ 0xb2, 0x21, 0x15, 0x25,
+ 0x82, 0x00, 0x2d, 0x0a,
+ 0x56, 0x3a, 0xdd, 0xad,
+ 0x01, 0xbd, 0x01, 0xc2,
+ 0xc1, 0x24, 0xe5, 0xb8,
+ 0x00, 0x2d, 0x0a, 0x56,
+ 0x4a, 0xdc, 0xad, 0x01,
+ 0xa5, 0x97, 0x00, 0xd6,
+ 0x8a, 0x03, 0xa2, 0xc1,
+ 0x24, 0xcb, 0xb1, 0x65,
+ 0x8a, 0x00, 0x2d, 0x0a,
+ 0x56, 0xfa, 0xda, 0xa2,
+ 0xc1, 0x24, 0xb2, 0x21,
+ 0x15, 0xe5, 0x7e, 0x00,
+ 0x2d, 0x0a, 0x56, 0x1a,
+ 0xda, 0xad, 0x01, 0xbd,
+ 0x01, 0xc2, 0xc1, 0x24,
+ 0xe5, 0x9e, 0x00, 0x2d,
+ 0x0a, 0x56, 0x2a, 0xd9,
+ 0xf8, 0x81, 0x4a, 0xff,
+ 0xf2, 0xdf, 0xfe, 0xe2,
+ 0x2f, 0x7f, 0x0b, 0xee,
+ 0xe2, 0x6f, 0x7f, 0x62,
+ 0xc6, 0xfc, 0x42, 0xc4,
+ 0xfc, 0xd2, 0x21, 0x10,
+ 0x82, 0x21, 0x15, 0x0b,
+ 0xdd, 0x82, 0xc8, 0xe0,
+ 0x82, 0x61, 0x15, 0x56,
+ 0x94, 0xe7, 0x16, 0x95,
+ 0xd6, 0xad, 0x01, 0xb2,
+ 0x21, 0x12, 0x25, 0x1c,
+ 0x00, 0x2d, 0x0a, 0x56,
+ 0xca, 0xd5, 0xad, 0x05,
+ 0xbd, 0x01, 0x98, 0x03,
+ 0x99, 0x01, 0x25, 0x84,
+ 0x00, 0x2d, 0x0a, 0x56,
+ 0xca, 0xd4, 0xad, 0x05,
+ 0x25, 0x90, 0x00, 0x56,
+ 0x4a, 0xd4, 0x0c, 0x1a,
+ 0xa9, 0x05, 0x46, 0x4f,
+ 0xff, 0x00, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0x9c,
+ 0x72, 0x0c, 0x07, 0x0c,
+ 0x08, 0x1b, 0x88, 0x68,
+ 0x03, 0x58, 0x04, 0x4b,
+ 0x33, 0x50, 0x76, 0x06,
+ 0x59, 0x04, 0x4b, 0x44,
+ 0x87, 0x92, 0xed, 0x46,
+ 0x00, 0x00, 0x0c, 0x07,
+ 0x8c, 0xf7, 0x88, 0x04,
+ 0x70, 0x98, 0xc0, 0x99,
+ 0x04, 0x70, 0x88, 0x62,
+ 0x4b, 0x44, 0x7d, 0x08,
+ 0x56, 0xe8, 0xfe, 0x1d,
+ 0xf0, 0x00, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0x50,
+ 0x00, 0xf3, 0x7d, 0x02,
+ 0xf6, 0xb2, 0x02, 0x06,
+ 0x2b, 0x00, 0x0c, 0x05,
+ 0x20, 0xa4, 0x41, 0x72,
+ 0xc7, 0xf0, 0xb8, 0x04,
+ 0x98, 0x03, 0x88, 0x14,
+ 0xb4, 0x59, 0xb9, 0xb9,
+ 0x04, 0x68, 0x13, 0x58,
+ 0x24, 0x84, 0x96, 0x86,
+ 0x89, 0x14, 0xf8, 0x23,
+ 0xe8, 0x34, 0x54, 0x6f,
+ 0x5f, 0x59, 0x24, 0xd8,
+ 0x33, 0xc8, 0x44, 0xe4,
+ 0xfd, 0xed, 0xe9, 0x34,
+ 0xb8, 0x43, 0x98, 0x54,
+ 0xc4, 0xdb, 0xcb, 0xc9,
+ 0x44, 0x88, 0x53, 0x68,
+ 0x64, 0x94, 0xb8, 0x98,
+ 0x99, 0x54, 0x58, 0x63,
+ 0xf8, 0x74, 0x64, 0x85,
+ 0x65, 0x69, 0x64, 0xe8,
+ 0x73, 0xd8, 0x84, 0xf4,
+ 0x5e, 0xfe, 0xf9, 0x74,
+ 0xc8, 0x83, 0xb8, 0x94,
+ 0xd4, 0xec, 0xdc, 0xd9,
+ 0x84, 0x98, 0x93, 0x88,
+ 0xa4, 0xb4, 0xc9, 0xb9,
+ 0xb9, 0x94, 0x68, 0xa3,
+ 0x58, 0xb4, 0x84, 0x96,
+ 0x86, 0x89, 0xa4, 0xf8,
+ 0xb3, 0xe8, 0xc4, 0x54,
+ 0x6f, 0x5f, 0x59, 0xb4,
+ 0xd8, 0xc3, 0xc8, 0xd4,
+ 0xe4, 0xfd, 0xed, 0xe9,
+ 0xc4, 0xb8, 0xd3, 0x98,
+ 0xe4, 0xc4, 0xdb, 0xcb,
+ 0xc9, 0xd4, 0x88, 0xe3,
+ 0x68, 0xf4, 0x94, 0xb8,
+ 0x98, 0x99, 0xe4, 0x58,
+ 0xf3, 0x32, 0xc3, 0x40,
+ 0x64, 0x85, 0x65, 0x69,
+ 0xf4, 0x42, 0xc4, 0x40,
+ 0xb6, 0xb7, 0x02, 0x06,
+ 0xd8, 0xff, 0xc0, 0x7a,
+ 0x11, 0x70, 0x72, 0xc0,
+ 0x46, 0x00, 0x00, 0x0c,
+ 0x05, 0x9d, 0x07, 0xb6,
+ 0x87, 0x5c, 0x70, 0xa3,
+ 0x41, 0x72, 0xc7, 0xf8,
+ 0xe8, 0x04, 0xd8, 0x03,
+ 0xc8, 0x14, 0xe4, 0x5d,
+ 0xed, 0xe9, 0x04, 0xb8,
+ 0x13, 0x88, 0x24, 0xc4,
+ 0xdb, 0xcb, 0xc9, 0x14,
+ 0x68, 0x23, 0x58, 0x34,
+ 0x84, 0xb6, 0x86, 0x89,
+ 0x24, 0x28, 0x33, 0xf8,
+ 0x44, 0x54, 0x62, 0x52,
+ 0x59, 0x34, 0xe8, 0x43,
+ 0xd8, 0x54, 0xf4, 0x2e,
+ 0xfe, 0xf9, 0x44, 0xc8,
+ 0x53, 0xb8, 0x64, 0xd4,
+ 0xec, 0xdc, 0xd9, 0x54,
+ 0x88, 0x63, 0x68, 0x74,
+ 0xb4, 0xc8, 0xb8, 0xb9,
+ 0x64, 0x58, 0x73, 0x32,
+ 0xc3, 0x20, 0x64, 0x85,
+ 0x85, 0x89, 0x74, 0x42,
+ 0xc4, 0x20, 0xf6, 0x87,
+ 0xab, 0xd0, 0x7a, 0x11,
+ 0x70, 0x79, 0xc0, 0x9c,
+ 0x07, 0x0b, 0x77, 0x98,
+ 0x03, 0xa8, 0x04, 0x4b,
+ 0x33, 0xa4, 0x59, 0x85,
+ 0x89, 0x04, 0x4b, 0x44,
+ 0x56, 0xd7, 0xfe, 0xb8,
+ 0x04, 0x5a, 0xbb, 0xb9,
+ 0x04, 0x50, 0x5b, 0x62,
+ 0x4b, 0x44, 0x56, 0x15,
+ 0xff, 0x1d, 0xf0, 0x00,
+ 0x36, 0x61, 0x00, 0xbd,
+ 0x03, 0xad, 0x02, 0x49,
+ 0x31, 0xcd, 0x01, 0xcb,
+ 0x81, 0x0c, 0x19, 0x99,
+ 0x01, 0x99, 0x11, 0x89,
+ 0x21, 0x25, 0x8b, 0x00,
+ 0x2d, 0x0a, 0x1d, 0xf0,
+ 0x36, 0x41, 0x00, 0x48,
+ 0x12, 0x30, 0xa5, 0x41,
+ 0xa7, 0x34, 0x7f, 0x30,
+ 0xf0, 0x44, 0xa7, 0x94,
+ 0x02, 0x56, 0x6f, 0x07,
+ 0x16, 0xfa, 0x03, 0xa0,
+ 0x84, 0xc0, 0xac, 0x08,
+ 0xd8, 0x22, 0x0c, 0x0c,
+ 0xe0, 0xea, 0x11, 0x0c,
+ 0x0b, 0x1b, 0xcc, 0xba,
+ 0x8d, 0xea, 0x4d, 0x4b,
+ 0xee, 0x48, 0x04, 0x49,
+ 0x08, 0x48, 0x12, 0x4b,
+ 0xbb, 0xa0, 0x94, 0xc0,
+ 0x97, 0x3c, 0xe9, 0x46,
+ 0x00, 0x00, 0x0c, 0x0c,
+ 0x47, 0xbc, 0x13, 0x0c,
+ 0x0d, 0xe0, 0xbc, 0x11,
+ 0xa8, 0x22, 0x1b, 0xcc,
+ 0xba, 0x8a, 0xd9, 0x08,
+ 0x48, 0x12, 0x4b, 0xbb,
+ 0x47, 0x3c, 0xf2, 0xac,
+ 0xcf, 0xac, 0xa4, 0x0c,
+ 0x09, 0xe0, 0xb4, 0x11,
+ 0xd8, 0x22, 0x2c, 0x0e,
+ 0xf0, 0xee, 0xc0, 0x00,
+ 0x0f, 0x40, 0xba, 0xad,
+ 0xa2, 0xda, 0xfe, 0x82,
+ 0x2a, 0x7f, 0xb2, 0xcb,
+ 0xfc, 0x80, 0xc0, 0x91,
+ 0x90, 0x9c, 0x20, 0x00,
+ 0x1e, 0x40, 0x92, 0x6a,
+ 0x7f, 0x00, 0x98, 0xa1,
+ 0x56, 0xfb, 0xfd, 0x0c,
+ 0x02, 0x1d, 0xf0, 0xad,
+ 0x02, 0x0c, 0x0b, 0xa5,
+ 0x6e, 0x00, 0x2d, 0x0a,
+ 0x1d, 0xf0, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0x78,
+ 0x12, 0x9c, 0x67, 0x68,
+ 0x22, 0x82, 0xd6, 0xfe,
+ 0x60, 0x67, 0xa0, 0x62,
+ 0xd6, 0xfe, 0x92, 0x26,
+ 0x7f, 0x62, 0xc6, 0xfc,
+ 0xcc, 0x39, 0x0b, 0x77,
+ 0x87, 0x96, 0xf2, 0x88,
+ 0x13, 0x68, 0x23, 0x9c,
+ 0x48, 0x92, 0xd6, 0xfe,
+ 0x60, 0x68, 0xa0, 0x62,
+ 0xd6, 0xfe, 0xa2, 0x26,
+ 0x7f, 0x62, 0xc6, 0xfc,
+ 0xcc, 0x3a, 0x0b, 0x88,
+ 0x97, 0x96, 0xf2, 0xcc,
+ 0x07, 0xac, 0xe8, 0x77,
+ 0x38, 0x30, 0x87, 0x37,
+ 0x31, 0xac, 0x67, 0x88,
+ 0x22, 0x98, 0x23, 0x80,
+ 0x67, 0xa0, 0x82, 0xd8,
+ 0xfe, 0x62, 0xd6, 0xfe,
+ 0x90, 0x27, 0xa0, 0x22,
+ 0xd2, 0xfe, 0x72, 0x26,
+ 0x7f, 0x32, 0x22, 0x7f,
+ 0x77, 0x33, 0x0f, 0x37,
+ 0x37, 0x10, 0x22, 0xc2,
+ 0xfc, 0x62, 0xc6, 0xfc,
+ 0x87, 0x96, 0xea, 0x0c,
+ 0x02, 0x1d, 0xf0, 0x0c,
+ 0x12, 0x1d, 0xf0, 0x7c,
+ 0xf2, 0x1d, 0xf0, 0x00,
+ 0x36, 0x61, 0x00, 0x81,
+ 0xa3, 0xf8, 0x71, 0xa1,
+ 0xf8, 0x9d, 0x03, 0xad,
+ 0x04, 0xa9, 0x11, 0x99,
+ 0x01, 0x8b, 0x57, 0x62,
+ 0xc7, 0x30, 0x82, 0x08,
+ 0x7e, 0x32, 0xc7, 0x14,
+ 0x42, 0xc7, 0x3c, 0xcc,
+ 0x88, 0x65, 0x62, 0x00,
+ 0x56, 0x0a, 0x22, 0x3c,
+ 0xc2, 0x1d, 0xf0, 0xb8,
+ 0x07, 0xf8, 0x17, 0x88,
+ 0x77, 0xb7, 0x3f, 0x02,
+ 0xc6, 0x3e, 0x00, 0xc8,
+ 0xe7, 0xa8, 0x47, 0xf0,
+ 0x2b, 0xc0, 0xe0, 0xe2,
+ 0x11, 0xe9, 0x21, 0x80,
+ 0x22, 0xa0, 0xa0, 0xab,
+ 0xa0, 0xc0, 0xcf, 0xa0,
+ 0xc8, 0x0c, 0xb8, 0x0a,
+ 0x22, 0xd2, 0xfe, 0xc7,
+ 0xbb, 0x02, 0xc6, 0x4b,
+ 0x00, 0x7c, 0xfc, 0xc2,
+ 0x62, 0x7f, 0xa8, 0x23,
+ 0xea, 0xaa, 0xa2, 0xda,
+ 0xfe, 0x92, 0x2a, 0x7f,
+ 0x1b, 0x99, 0x92, 0x6a,
+ 0x7f, 0xad, 0x04, 0xf1,
+ 0x89, 0xf8, 0xd8, 0x07,
+ 0xf8, 0x0f, 0xe8, 0x23,
+ 0xf0, 0xdd, 0xc0, 0xe0,
+ 0xdd, 0xa0, 0xd2, 0xdd,
+ 0xfe, 0xc2, 0x2d, 0x7f,
+ 0x0c, 0x0b, 0x0b, 0xcc,
+ 0xc2, 0x6d, 0x7f, 0xa5,
+ 0x5d, 0x00, 0x2d, 0x0a,
+ 0x56, 0xfa, 0x0c, 0xf1,
+ 0x80, 0xf8, 0xf8, 0x0f,
+ 0xc8, 0x26, 0xe0, 0xef,
+ 0x11, 0xcc, 0x3f, 0x0c,
+ 0x0c, 0x06, 0x02, 0x00,
+ 0xc0, 0xcf, 0xa0, 0xc2,
+ 0xdc, 0xff, 0xc2, 0x2c,
+ 0x3f, 0xad, 0x04, 0xbd,
+ 0x04, 0xd8, 0x24, 0x88,
+ 0x07, 0xc9, 0x0d, 0x98,
+ 0x26, 0xc8, 0x24, 0xea,
+ 0x99, 0x98, 0x09, 0x99,
+ 0x1c, 0xd8, 0x23, 0xf0,
+ 0xc8, 0xc0, 0xd0, 0xcc,
+ 0xa0, 0xc2, 0xdc, 0xff,
+ 0xc2, 0x2c, 0x3f, 0x25,
+ 0xe0, 0xff, 0x2d, 0x0a,
+ 0x56, 0xba, 0x08, 0xa1,
+ 0x70, 0xf8, 0x0c, 0x0b,
+ 0x65, 0x58, 0x00, 0x2d,
+ 0x0a, 0x56, 0xea, 0x07,
+ 0xb8, 0x07, 0xa1, 0x6c,
+ 0xf8, 0xe0, 0xcb, 0x11,
+ 0xa8, 0x2a, 0xb6, 0x2b,
+ 0x0d, 0x98, 0x25, 0x90,
+ 0x9b, 0xa0, 0x92, 0xd9,
+ 0xff, 0x92, 0x29, 0x3e,
+ 0x46, 0x00, 0x00, 0x0c,
+ 0x09, 0x99, 0x0a, 0xcc,
+ 0x3b, 0x0c, 0x0e, 0x46,
+ 0x02, 0x00, 0xe8, 0x25,
+ 0xca, 0xee, 0xe2, 0xde,
+ 0xff, 0xe2, 0x2e, 0x3f,
+ 0xb1, 0x61, 0xf8, 0x88,
+ 0x2b, 0xad, 0x04, 0xe9,
+ 0x18, 0xf8, 0x25, 0x88,
+ 0x2b, 0xca, 0xff, 0xf8,
+ 0x0f, 0xf9, 0x28, 0x65,
+ 0xcb, 0x00, 0xa6, 0x1a,
+ 0x02, 0x06, 0xcf, 0xff,
+ 0x86, 0x1c, 0x00, 0xac,
+ 0xc2, 0xb8, 0xb7, 0xad,
+ 0x05, 0x29, 0x31, 0x25,
+ 0xdb, 0xff, 0x78, 0x31,
+ 0x2d, 0x0a, 0xdc, 0xda,
+ 0xad, 0x07, 0x98, 0x01,
+ 0xbd, 0x05, 0x98, 0x09,
+ 0x99, 0x05, 0xe5, 0x42,
+ 0x00, 0x2d, 0x0a, 0xcc,
+ 0xca, 0xad, 0x07, 0x25,
+ 0x4f, 0x00, 0xcc, 0x5a,
+ 0x0c, 0x1a, 0xa9, 0x07,
+ 0xc6, 0xff, 0xff, 0xad,
+ 0x05, 0x65, 0xd2, 0x00,
+ 0xad, 0x06, 0x25, 0xd2,
+ 0x00, 0xad, 0x03, 0xe5,
+ 0xd1, 0x00, 0x31, 0x49,
+ 0xf8, 0xad, 0x04, 0x65,
+ 0xd1, 0x00, 0x0c, 0x04,
+ 0xad, 0x03, 0xe5, 0xd0,
+ 0x00, 0xb1, 0x43, 0xf8,
+ 0x42, 0x4b, 0x7e, 0x1d,
+ 0xf0, 0x0c, 0x0d, 0xa2,
+ 0xda, 0xff, 0xa2, 0x2a,
+ 0x3f, 0x25, 0x81, 0x06,
+ 0xe8, 0x21, 0x7c, 0xfc,
+ 0x56, 0xfb, 0xeb, 0xa7,
+ 0xbc, 0x02, 0x46, 0xae,
+ 0xff, 0xcd, 0x0a, 0x06,
+ 0xad, 0xff, 0xad, 0x04,
+ 0xbd, 0x06, 0xe1, 0x3a,
+ 0xf8, 0xc8, 0x07, 0xe8,
+ 0x0e, 0xd8, 0x23, 0xe0,
+ 0xcc, 0xc0, 0xd0, 0xcc,
+ 0xa0, 0xc2, 0xdc, 0xff,
+ 0xc2, 0x2c, 0x3f, 0x25,
+ 0xd1, 0xff, 0x2d, 0x0a,
+ 0x56, 0xba, 0xf9, 0xc1,
+ 0x33, 0xf8, 0xb8, 0x07,
+ 0xc8, 0x0c, 0xad, 0x04,
+ 0xc0, 0xbb, 0xc0, 0xb0,
+ 0xbb, 0x11, 0xb2, 0xcb,
+ 0xe0, 0xa5, 0x2f, 0x00,
+ 0x2d, 0x0a, 0x56, 0x1a,
+ 0xf8, 0xad, 0x05, 0xbd,
+ 0x05, 0xcd, 0x04, 0xa5,
+ 0x66, 0x00, 0x2d, 0x0a,
+ 0x56, 0x3a, 0xf7, 0xad,
+ 0x05, 0x65, 0x45, 0x00,
+ 0xd6, 0x5a, 0x12, 0xad,
+ 0x04, 0xbd, 0x06, 0x25,
+ 0x38, 0x00, 0x2d, 0x0a,
+ 0x56, 0xfa, 0xf5, 0xc1,
+ 0x24, 0xf8, 0xb8, 0x07,
+ 0xc8, 0x0c, 0xad, 0x04,
+ 0xc0, 0xbb, 0xc0, 0xb0,
+ 0xbb, 0x11, 0xb2, 0xcb,
+ 0xe0, 0xe5, 0x2b, 0x00,
+ 0x2d, 0x0a, 0x56, 0x5a,
+ 0xf4, 0xad, 0x05, 0xbd,
+ 0x05, 0xcd, 0x04, 0x25,
+ 0x4c, 0x00, 0x2d, 0x0a,
+ 0x56, 0x7a, 0xf3, 0xe1,
+ 0x1a, 0xf8, 0xb8, 0x07,
+ 0xe8, 0x0e, 0xf8, 0x23,
+ 0xe0, 0xeb, 0xc0, 0xf0,
+ 0xee, 0xa0, 0xe2, 0xde,
+ 0xfe, 0xd2, 0x2e, 0x7f,
+ 0x0b, 0xdd, 0xd2, 0x6e,
+ 0x7f, 0x86, 0x35, 0x00,
+ 0xad, 0x05, 0x25, 0xc4,
+ 0x00, 0xad, 0x06, 0xe5,
+ 0xc3, 0x00, 0xad, 0x03,
+ 0x65, 0xc3, 0x00, 0xad,
+ 0x04, 0x25, 0xc3, 0x00,
+ 0xa1, 0x0f, 0xf8, 0xe5,
+ 0xc2, 0x00, 0xad, 0x05,
+ 0x25, 0xc1, 0x00, 0xad,
+ 0x06, 0xe5, 0xc0, 0x00,
+ 0xad, 0x03, 0xa5, 0xc0,
+ 0x00, 0xad, 0x04, 0x65,
+ 0xc0, 0x00, 0xa1, 0x08,
+ 0xf8, 0xe5, 0xbf, 0x00,
+ 0xa8, 0x01, 0xb8, 0x11,
+ 0x25, 0xd0, 0xff, 0xd6,
+ 0x1a, 0x01, 0x8c, 0xa2,
+ 0xad, 0x02, 0xb8, 0x01,
+ 0xe5, 0x2e, 0x00, 0x2d,
+ 0x0a, 0x56, 0xea, 0xec,
+ 0x0c, 0x02, 0x1d, 0xf0,
+ 0xad, 0x05, 0xb8, 0x01,
+ 0xe5, 0x2d, 0x00, 0x2d,
+ 0x0a, 0x56, 0xea, 0xeb,
+ 0xad, 0x06, 0xb8, 0x11,
+ 0x25, 0x2d, 0x00, 0x2d,
+ 0x0a, 0x56, 0x2a, 0xeb,
+ 0xb8, 0x01, 0x0c, 0x1c,
+ 0xc9, 0x05, 0xc9, 0x06,
+ 0xb8, 0x1b, 0xad, 0x03,
+ 0x2b, 0xbb, 0x65, 0x3d,
+ 0x00, 0x2d, 0x0a, 0x56,
+ 0xca, 0xe9, 0xad, 0x03,
+ 0x0c, 0x0b, 0xa5, 0x39,
+ 0x00, 0x2d, 0x0a, 0x56,
+ 0x0a, 0xe9, 0xad, 0x04,
+ 0x0c, 0x2b, 0xe5, 0x3b,
+ 0x00, 0x2d, 0x0a, 0x56,
+ 0x4a, 0xe8, 0xa1, 0xee,
+ 0xf7, 0x0c, 0x3b, 0x25,
+ 0x3b, 0x00, 0x2d, 0x0a,
+ 0x56, 0x7a, 0xe7, 0xad,
+ 0x06, 0x25, 0x2e, 0x00,
+ 0x1c, 0xfe, 0xa0, 0xc0,
+ 0x44, 0x1c, 0xed, 0xc7,
+ 0x3d, 0x29, 0xc0, 0xbe,
+ 0xc0, 0xe1, 0xe7, 0xf7,
+ 0xad, 0x05, 0xb9, 0x0e,
+ 0xe5, 0x1c, 0x00, 0x2d,
+ 0x0a, 0x56, 0x6a, 0xe5,
+ 0xb1, 0xe4, 0xf7, 0xad,
+ 0x06, 0xb8, 0x0b, 0x25,
+ 0x1c, 0x00, 0x2d, 0x0a,
+ 0x8c, 0xfa, 0x46, 0x91,
+ 0xff, 0xb8, 0x07, 0x0b,
+ 0x9b, 0xc6, 0x21, 0x00,
+ 0xd1, 0xde, 0xf7, 0x0c,
+ 0x0c, 0xc9, 0x0d, 0xad,
+ 0x06, 0xc8, 0x15, 0xb8,
+ 0x16, 0xe1, 0xd8, 0xf7,
+ 0x0b, 0xdb, 0xd9, 0x0e,
+ 0xb0, 0xbc, 0xc0, 0xb0,
+ 0xbb, 0x11, 0x0b, 0xcc,
+ 0xc2, 0x6e, 0x11, 0x25,
+ 0x19, 0x00, 0x2d, 0x0a,
+ 0x56, 0x7a, 0xe1, 0xad,
+ 0x05, 0xbd, 0x06, 0xe5,
+ 0xa8, 0x00, 0x96, 0xfa,
+ 0x02, 0xbd, 0x05, 0xcd,
+ 0x06, 0xa1, 0xce, 0xf7,
+ 0x81, 0xd1, 0xf7, 0xa8,
+ 0x0a, 0x88, 0x08, 0x98,
+ 0x23, 0xa0, 0x88, 0xc0,
+ 0x90, 0x88, 0xa0, 0xf8,
+ 0x08, 0xad, 0x05, 0x1b,
+ 0xff, 0xf9, 0x08, 0xe5,
+ 0x4d, 0x00, 0x2d, 0x0a,
+ 0x56, 0x7a, 0xde, 0xad,
+ 0x05, 0xbd, 0x06, 0xe5,
+ 0xa5, 0x00, 0xd6, 0xfa,
+ 0xfc, 0xc1, 0xc3, 0xf7,
+ 0xb1, 0xc6, 0xf7, 0xc8,
+ 0x0c, 0xb8, 0x0b, 0xad,
+ 0x06, 0xc0, 0xbb, 0xc0,
+ 0xb0, 0xbb, 0x11, 0x65,
+ 0xb5, 0xff, 0x2d, 0x0a,
+ 0x56, 0x3a, 0xdc, 0xb1,
+ 0xbc, 0xf7, 0x0c, 0x1a,
+ 0x91, 0xbf, 0xf7, 0xa2,
+ 0x4b, 0x7e, 0x98, 0x09,
+ 0x0c, 0xa2, 0x99, 0x07,
+ 0x1d, 0xf0, 0x00, 0x00,
+ 0x36, 0x81, 0x00, 0xa8,
+ 0x26, 0x0c, 0x0b, 0xc8,
+ 0x16, 0x29, 0x71, 0xdd,
+ 0x05, 0x2d, 0x04, 0xd9,
+ 0x41, 0x58, 0x71, 0xe0,
+ 0xcc, 0x11, 0xe5, 0x22,
+ 0x07, 0x29, 0x01, 0x39,
+ 0x31, 0x69, 0x61, 0x78,
+ 0x26, 0x98, 0x13, 0x68,
+ 0x12, 0x69, 0x11, 0x60,
+ 0x99, 0x63, 0xe0, 0xa6,
+ 0x11, 0xa9, 0x51, 0x16,
+ 0x96, 0x04, 0x70, 0x46,
+ 0xa0, 0x0c, 0x03, 0x69,
+ 0x11, 0x99, 0x21, 0x29,
+ 0x01, 0xa8, 0x21, 0xcd,
+ 0x07, 0x68, 0x41, 0xb8,
+ 0x31, 0x28, 0x25, 0xb8,
+ 0x2b, 0x3a, 0x22, 0x28,
+ 0x02, 0x98, 0x0b, 0x88,
+ 0x07, 0x20, 0x99, 0x82,
+ 0xdd, 0x02, 0x9a, 0x88,
+ 0x80, 0x66, 0x82, 0xe5,
+ 0x97, 0xff, 0xdd, 0x06,
+ 0xa8, 0x11, 0xb8, 0x01,
+ 0xcd, 0x07, 0xb8, 0x2b,
+ 0xe5, 0x96, 0xff, 0xc8,
+ 0x51, 0x4b, 0x33, 0x4b,
+ 0x44, 0x29, 0x07, 0x0c,
+ 0x0d, 0x4b, 0x77, 0xd9,
+ 0x14, 0xc7, 0x93, 0xc0,
+ 0xbd, 0x07, 0x28, 0x01,
+ 0x68, 0x11, 0x48, 0x61,
+ 0xc8, 0x51, 0xa8, 0x25,
+ 0x4b, 0xcc, 0x65, 0x08,
+ 0x07, 0xad, 0x05, 0xbd,
+ 0x02, 0xe5, 0xb3, 0xff,
+ 0xc8, 0x25, 0x96, 0x8a,
+ 0x00, 0xad, 0x06, 0xb8,
+ 0x22, 0x25, 0x90, 0xff,
+ 0x1d, 0xf0, 0xbd, 0x0c,
+ 0xad, 0x06, 0xc8, 0x24,
+ 0x65, 0x8f, 0xff, 0x1d,
+ 0xf0, 0x00, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0x81,
+ 0x8a, 0xf7, 0x82, 0x08,
+ 0x7e, 0xcc, 0xb8, 0xad,
+ 0x04, 0x65, 0x1d, 0x00,
+ 0xd6, 0x4a, 0x00, 0x3c,
+ 0x23, 0x06, 0x11, 0x00,
+ 0xbd, 0x03, 0xad, 0x02,
+ 0xcd, 0x04, 0xe5, 0xb7,
+ 0xff, 0x3d, 0x0a, 0xfc,
+ 0x6a, 0xad, 0x02, 0xe5,
+ 0x1b, 0x00, 0xd6, 0x3a,
+ 0x03, 0xad, 0x02, 0xbd,
+ 0x02, 0xcd, 0x04, 0xe5,
+ 0x24, 0x00, 0x3d, 0x0a,
+ 0xec, 0x1a, 0xad, 0x02,
+ 0x65, 0x1a, 0x00, 0x96,
+ 0xaa, 0xfe, 0xc6, 0x06,
+ 0x00, 0xad, 0x02, 0xbd,
+ 0x04, 0xe5, 0x92, 0x00,
+ 0x96, 0xda, 0x00, 0xad,
+ 0x02, 0xbd, 0x02, 0xcd,
+ 0x04, 0x65, 0x39, 0x00,
+ 0x3d, 0x0a, 0x16, 0x7a,
+ 0xfe, 0x2d, 0x03, 0x1d,
+ 0xf0, 0xad, 0x02, 0xbd,
+ 0x04, 0x25, 0x91, 0x00,
+ 0xd6, 0x3a, 0xfe, 0x86,
+ 0xfb, 0xff, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0xad,
+ 0x02, 0x65, 0x0f, 0x00,
+ 0x88, 0x12, 0x3a, 0xaa,
+ 0xb0, 0x88, 0x11, 0xa7,
+ 0xb8, 0x0d, 0xb2, 0xca,
+ 0x1f, 0xb0, 0xb5, 0x41,
+ 0xad, 0x02, 0x65, 0x1a,
+ 0x00, 0x56, 0x2a, 0x08,
+ 0x30, 0xe5, 0x41, 0x16,
+ 0x4e, 0x04, 0xb8, 0x12,
+ 0xe0, 0xde, 0x11, 0xb7,
+ 0xbe, 0x25, 0xc8, 0x22,
+ 0xe0, 0xab, 0x11, 0xe0,
+ 0xbb, 0xc0, 0xe0, 0xbb,
+ 0x11, 0xba, 0xfc, 0xaa,
+ 0x8c, 0xb2, 0xcb, 0xfc,
+ 0xa2, 0xca, 0xfc, 0x82,
+ 0xd8, 0xff, 0xf2, 0xdf,
+ 0xff, 0xf2, 0x2f, 0x3f,
+ 0xf2, 0x68, 0x3f, 0xd7,
+ 0x9a, 0xe6, 0xbd, 0x0e,
+ 0x9c, 0x3b, 0x98, 0x22,
+ 0xe0, 0xab, 0x11, 0x0c,
+ 0x0b, 0xaa, 0xc9, 0xa2,
+ 0xca, 0xfc, 0xc2, 0xdc,
+ 0xff, 0xb2, 0x6c, 0x3f,
+ 0x56, 0x1a, 0xff, 0x30,
+ 0xf0, 0x44, 0xac, 0xff,
+ 0xd8, 0x12, 0xbd, 0x0e,
+ 0xd7, 0xbe, 0x29, 0xc8,
+ 0x22, 0xe0, 0xae, 0x11,
+ 0x0c, 0x0d, 0x2c, 0x03,
+ 0xf0, 0x33, 0xc0, 0x1b,
+ 0xbb, 0x00, 0x1f, 0x40,
+ 0xaa, 0xec, 0x98, 0x0e,
+ 0x4b, 0xaa, 0x00, 0x89,
+ 0xa1, 0x00, 0x03, 0x40,
+ 0xd0, 0xd8, 0x20, 0xd9,
+ 0x0e, 0x88, 0x12, 0x90,
+ 0xd0, 0x91, 0x87, 0x3b,
+ 0xe1, 0x0c, 0x0a, 0x2d,
+ 0x0a, 0x1d, 0xf0, 0x00,
+ 0x36, 0x41, 0x00, 0x37,
+ 0x12, 0x0a, 0xb8, 0x23,
+ 0x48, 0x13, 0xcc, 0x7b,
+ 0xad, 0x02, 0x25, 0x90,
+ 0x00, 0x0c, 0x02, 0x1d,
+ 0xf0, 0x0b, 0x44, 0x8c,
+ 0xd4, 0xb0, 0xa4, 0xa0,
+ 0x88, 0x0a, 0xa2, 0xca,
+ 0xfc, 0xcc, 0x38, 0x0b,
+ 0x44, 0xa7, 0x9b, 0xf3,
+ 0xad, 0x02, 0x1b, 0xb4,
+ 0x98, 0x03, 0x99, 0x02,
+ 0x65, 0x0e, 0x00, 0x5d,
+ 0x0a, 0xdc, 0x6a, 0xa8,
+ 0x22, 0xc8, 0x12, 0x0c,
+ 0x0b, 0xe0, 0xcc, 0x11,
+ 0xa5, 0x03, 0x07, 0xa8,
+ 0x22, 0xb8, 0x23, 0x0c,
+ 0x4c, 0xc0, 0xc4, 0xa0,
+ 0xa5, 0xef, 0x06, 0x2d,
+ 0x05, 0x1d, 0xf0, 0x00,
+ 0x36, 0x41, 0x00, 0x58,
+ 0x12, 0x68, 0x22, 0x0b,
+ 0x55, 0x9c, 0x05, 0x60,
+ 0x25, 0xa0, 0x48, 0x02,
+ 0x22, 0xc2, 0xfc, 0xcc,
+ 0xd4, 0x0b, 0x55, 0x67,
+ 0x92, 0xf3, 0x46, 0x00,
+ 0x00, 0x68, 0x22, 0x60,
+ 0x45, 0xa0, 0x48, 0x04,
+ 0x1c, 0xf2, 0x2c, 0x06,
+ 0x00, 0x02, 0x40, 0x40,
+ 0x80, 0x91, 0x07, 0xe8,
+ 0x06, 0x0b, 0x22, 0x0b,
+ 0x66, 0x56, 0xf6, 0xfe,
+ 0xb0, 0x25, 0x11, 0x2a,
+ 0x26, 0x1d, 0xf0, 0x00,
+ 0x36, 0x41, 0x00, 0x68,
+ 0x23, 0x68, 0x06, 0x0c,
+ 0x45, 0x2b, 0x46, 0x50,
+ 0x44, 0x10, 0x60, 0x44,
+ 0x90, 0x60, 0x74, 0x82,
+ 0x0c, 0x25, 0x70, 0x75,
+ 0xc0, 0x70, 0x44, 0x82,
+ 0x60, 0x74, 0x82, 0x70,
+ 0x75, 0xc0, 0x70, 0x44,
+ 0x82, 0x60, 0x64, 0x82,
+ 0x60, 0x55, 0xc0, 0x50,
+ 0x44, 0x82, 0x40, 0x40,
+ 0x60, 0x49, 0x02, 0x1d,
+ 0xf0, 0x00, 0x00, 0x00,
+ 0x36, 0x61, 0x00, 0xad,
+ 0x02, 0x19, 0x31, 0x4b,
+ 0xb1, 0x0c, 0x08, 0x0c,
+ 0x19, 0x99, 0x11, 0x99,
+ 0x21, 0x89, 0x01, 0x25,
+ 0x78, 0x00, 0x2d, 0x0a,
+ 0x1d, 0xf0, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0xad,
+ 0x02, 0x0c, 0x1b, 0xa5,
+ 0x02, 0x00, 0x4d, 0x0a,
+ 0xdc, 0xaa, 0xa8, 0x22,
+ 0xc8, 0x12, 0x0c, 0x0b,
+ 0xe0, 0xcc, 0x11, 0xe5,
+ 0xf7, 0x06, 0x7c, 0xfe,
+ 0x0c, 0x1d, 0x88, 0x22,
+ 0x30, 0xf1, 0x60, 0xf9,
+ 0x08, 0x30, 0xde, 0xa3,
+ 0xd9, 0x02, 0x2d, 0x04,
+ 0x1d, 0xf0, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0x81,
+ 0x03, 0xf7, 0x37, 0x38,
+ 0x11, 0x98, 0x12, 0x37,
+ 0xb9, 0x3a, 0xe0, 0x53,
+ 0x11, 0x50, 0xa0, 0xf4,
+ 0xa5, 0x24, 0xff, 0x4d,
+ 0x0a, 0xcc, 0x2a, 0x5c,
+ 0x02, 0x1d, 0xf0, 0xcd,
+ 0x05, 0x0c, 0x0b, 0x25,
+ 0xf4, 0x06, 0xb8, 0x22,
+ 0x9c, 0x9b, 0xc8, 0x12,
+ 0xad, 0x04, 0xe0, 0xcc,
+ 0x11, 0xe5, 0xdf, 0x06,
+ 0xa8, 0x22, 0xc8, 0x12,
+ 0x0c, 0x0b, 0xe0, 0xcc,
+ 0x11, 0x65, 0xf2, 0x06,
+ 0xa8, 0x22, 0x65, 0x1f,
+ 0xff, 0x39, 0x12, 0x49,
+ 0x22, 0x0c, 0x02, 0x1d,
+ 0xf0, 0x00, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0x58,
+ 0x03, 0x88, 0x04, 0x50,
+ 0x88, 0x82, 0xd6, 0x98,
+ 0x01, 0xad, 0x03, 0xbd,
+ 0x04, 0xe5, 0x88, 0xff,
+ 0x96, 0xfa, 0x01, 0xcd,
+ 0x04, 0xbd, 0x03, 0xad,
+ 0x02, 0x65, 0x2b, 0xff,
+ 0xcc, 0xfa, 0x59, 0x02,
+ 0xc6, 0x02, 0x00, 0xcd,
+ 0x04, 0xbd, 0x03, 0xad,
+ 0x02, 0x65, 0x20, 0xff,
+ 0x16, 0xea, 0xfe, 0x2d,
+ 0x0a, 0x1d, 0xf0, 0xcd,
+ 0x03, 0xbd, 0x04, 0xad,
+ 0x02, 0x65, 0x29, 0xff,
+ 0x56, 0xfa, 0xfe, 0x50,
+ 0x50, 0x60, 0x06, 0xf6,
+ 0xff, 0x00, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0xad,
+ 0x04, 0x25, 0xf1, 0xff,
+ 0xd6, 0x3a, 0x00, 0x3c,
+ 0x22, 0x1d, 0xf0, 0xbd,
+ 0x03, 0xad, 0x02, 0xcd,
+ 0x04, 0xe5, 0x2d, 0xff,
+ 0x3d, 0x0a, 0xfc, 0x6a,
+ 0xad, 0x02, 0xa5, 0xef,
+ 0xff, 0xd6, 0x3a, 0x03,
+ 0xad, 0x02, 0xbd, 0x02,
+ 0xcd, 0x04, 0xa5, 0xf8,
+ 0xff, 0x3d, 0x0a, 0xec,
+ 0x1a, 0xad, 0x02, 0x65,
+ 0xee, 0xff, 0x96, 0xaa,
+ 0xfe, 0xc6, 0x06, 0x00,
+ 0xad, 0x02, 0xbd, 0x04,
+ 0xa5, 0x66, 0x00, 0x96,
+ 0xda, 0x00, 0xad, 0x02,
+ 0xbd, 0x02, 0xcd, 0x04,
+ 0x25, 0x0d, 0x00, 0x3d,
+ 0x0a, 0x16, 0x7a, 0xfe,
+ 0x2d, 0x03, 0x1d, 0xf0,
+ 0xad, 0x02, 0xbd, 0x04,
+ 0xe5, 0x64, 0x00, 0xd6,
+ 0x3a, 0xfe, 0x86, 0xfb,
+ 0xff, 0x00, 0x00, 0x00,
+ 0x36, 0x81, 0x00, 0xad,
+ 0x01, 0xa5, 0x6d, 0x00,
+ 0xcb, 0xa1, 0x65, 0x6d,
+ 0x00, 0x37, 0x92, 0x0d,
+ 0xbd, 0x03, 0xad, 0x01,
+ 0xe5, 0xdc, 0xff, 0x7d,
+ 0x0a, 0x56, 0xca, 0x08,
+ 0x3d, 0x01, 0x47, 0x92,
+ 0x0d, 0xbd, 0x04, 0xcb,
+ 0xa1, 0xe5, 0xdb, 0xff,
+ 0x7d, 0x0a, 0x56, 0xba,
+ 0x07, 0xcb, 0x41, 0x58,
+ 0x13, 0x68, 0x14, 0x9c,
+ 0x65, 0xa8, 0x23, 0xb2,
+ 0xda, 0xfe, 0xa0, 0xa5,
+ 0xa0, 0xa2, 0xda, 0xfe,
+ 0xc2, 0x2a, 0x7f, 0xa2,
+ 0xca, 0xfc, 0xcc, 0x3c,
+ 0x0b, 0x55, 0xb7, 0x9a,
+ 0xf2, 0x9c, 0x66, 0xa8,
+ 0x24, 0xb2, 0xda, 0xfe,
+ 0xa0, 0xa6, 0xa0, 0xa2,
+ 0xda, 0xfe, 0xc2, 0x2a,
+ 0x7f, 0xa2, 0xca, 0xfc,
+ 0xcc, 0x3c, 0x0b, 0x66,
+ 0xb7, 0x9a, 0xf2, 0xad,
+ 0x02, 0x6a, 0xb5, 0x25,
+ 0xe9, 0xff, 0x7d, 0x0a,
+ 0xfc, 0x5a, 0xad, 0x02,
+ 0x0c, 0x0b, 0x65, 0xe5,
+ 0xff, 0x7d, 0x0a, 0xec,
+ 0xaa, 0x9c, 0xf6, 0xe0,
+ 0x66, 0x11, 0xad, 0x05,
+ 0xb8, 0x23, 0xd8, 0x24,
+ 0xc8, 0x22, 0x6a, 0xdd,
+ 0x6a, 0xcc, 0xc2, 0xcc,
+ 0xfc, 0xd2, 0xdd, 0xff,
+ 0xd2, 0x2d, 0x3f, 0xe5,
+ 0x55, 0xff, 0x62, 0xc6,
+ 0xfc, 0x56, 0x16, 0xfe,
+ 0xf8, 0x03, 0xe8, 0x04,
+ 0xf0, 0xee, 0x82, 0xe9,
+ 0x02, 0xcb, 0xa1, 0xa5,
+ 0x64, 0x00, 0xad, 0x01,
+ 0x25, 0x64, 0x00, 0x2d,
+ 0x07, 0x1d, 0xf0, 0x00,
+ 0x36, 0x41, 0x00, 0x58,
+ 0x03, 0x88, 0x04, 0x50,
+ 0x88, 0x82, 0xa6, 0x18,
+ 0x19, 0xad, 0x03, 0xbd,
+ 0x04, 0x25, 0x72, 0xff,
+ 0x96, 0xfa, 0x01, 0xcd,
+ 0x04, 0xbd, 0x03, 0xad,
+ 0x02, 0xa5, 0x14, 0xff,
+ 0xcc, 0xfa, 0x59, 0x02,
+ 0xc6, 0x02, 0x00, 0xcd,
+ 0x04, 0xbd, 0x03, 0xad,
+ 0x02, 0xa5, 0x09, 0xff,
+ 0x16, 0xea, 0xfe, 0x2d,
+ 0x0a, 0x1d, 0xf0, 0xcd,
+ 0x03, 0xbd, 0x04, 0xad,
+ 0x02, 0xa5, 0x12, 0xff,
+ 0x56, 0xfa, 0xfe, 0x50,
+ 0x50, 0x60, 0x06, 0xf6,
+ 0xff, 0x00, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0xad,
+ 0x02, 0xe5, 0xd2, 0xff,
+ 0x7b, 0x5a, 0x50, 0x53,
+ 0x41, 0x57, 0xb4, 0x03,
+ 0x2c, 0x82, 0x1d, 0xf0,
+ 0xad, 0x03, 0x0c, 0x0b,
+ 0xcd, 0x04, 0x25, 0xd4,
+ 0x06, 0x0b, 0x94, 0xac,
+ 0x45, 0x9a, 0xa3, 0x0c,
+ 0x09, 0x0b, 0x55, 0xb8,
+ 0x22, 0x90, 0x82, 0x41,
+ 0xb0, 0x88, 0xa0, 0x88,
+ 0x08, 0x90, 0xb0, 0x14,
+ 0xd0, 0xbb, 0x11, 0x1b,
+ 0x99, 0x00, 0x0b, 0x40,
+ 0x80, 0x80, 0x91, 0x82,
+ 0x4a, 0x00, 0x0b, 0xaa,
+ 0x56, 0xd5, 0xfd, 0x0c,
+ 0x02, 0x1d, 0xf0, 0x00,
+ 0x36, 0xa1, 0x00, 0x0c,
+ 0x07, 0xbd, 0x03, 0xcd,
+ 0x02, 0xed, 0x06, 0x9d,
+ 0x04, 0x99, 0x41, 0x61,
+ 0x66, 0xf6, 0x4d, 0x05,
+ 0x21, 0x6b, 0xf6, 0x51,
+ 0x6b, 0xf6, 0x82, 0x02,
+ 0x00, 0x4b, 0x35, 0x9c,
+ 0x28, 0xf1, 0x69, 0xf6,
+ 0xdd, 0x03, 0x72, 0x42,
+ 0x00, 0x92, 0xa0, 0x80,
+ 0x79, 0x2d, 0xcb, 0xdd,
+ 0xf7, 0x9d, 0xf8, 0x99,
+ 0x05, 0x0c, 0x1d, 0x21,
+ 0x64, 0xf6, 0xf2, 0x06,
+ 0x7d, 0x4b, 0xa2, 0xdc,
+ 0xcf, 0xd2, 0x46, 0x7d,
+ 0xad, 0x04, 0xa5, 0xd1,
+ 0xff, 0x96, 0xea, 0x00,
+ 0x98, 0x24, 0x98, 0x09,
+ 0x07, 0x69, 0x07, 0xa8,
+ 0x41, 0xa5, 0xd0, 0xff,
+ 0xd6, 0x9a, 0x30, 0x1c,
+ 0x42, 0x1d, 0xf0, 0x82,
+ 0xc2, 0x34, 0x62, 0xc2,
+ 0x30, 0xb9, 0x51, 0xe9,
+ 0x61, 0xc9, 0x81, 0x0c,
+ 0x3d, 0xd9, 0x71, 0x66,
+ 0x1f, 0x3c, 0x22, 0xc2,
+ 0x1c, 0xa8, 0x41, 0x7d,
+ 0x08, 0xf1, 0x4b, 0xf6,
+ 0x0c, 0x2e, 0xe2, 0x4f,
+ 0x7d, 0x65, 0xc6, 0xff,
+ 0xa9, 0x05, 0x82, 0xa2,
+ 0x9f, 0xa7, 0xb8, 0x02,
+ 0xc6, 0x99, 0x00, 0x92,
+ 0xa0, 0xef, 0xa7, 0xb9,
+ 0x02, 0x86, 0xc6, 0x00,
+ 0x4c, 0xfb, 0xa7, 0xbb,
+ 0x02, 0x46, 0xc3, 0x00,
+ 0xc8, 0x71, 0x0c, 0x1d,
+ 0x1c, 0x7e, 0xa0, 0xee,
+ 0x62, 0xe0, 0xdc, 0x93,
+ 0x46, 0x92, 0x00, 0x66,
+ 0x2f, 0x13, 0x16, 0xfe,
+ 0x17, 0x88, 0x2e, 0x16,
+ 0xa8, 0x17, 0xbd, 0x0e,
+ 0x0c, 0xcc, 0xe5, 0xb1,
+ 0x06, 0x0c, 0x49, 0x46,
+ 0x64, 0x00, 0x66, 0x3f,
+ 0x2e, 0xcd, 0x04, 0xbd,
+ 0x0a, 0xe5, 0xaa, 0xff,
+ 0xb1, 0x3f, 0xf6, 0x92,
+ 0xca, 0xf6, 0xa9, 0x0b,
+ 0x16, 0x59, 0x15, 0x56,
+ 0x2a, 0x18, 0xe1, 0x32,
+ 0xf6, 0x0c, 0x4d, 0xc8,
+ 0x61, 0xd2, 0x4e, 0x7d,
+ 0x16, 0x5c, 0x14, 0xad,
+ 0x0c, 0xb2, 0xcb, 0xd8,
+ 0x0c, 0xcc, 0xa5, 0xae,
+ 0x06, 0x06, 0x4e, 0x00,
+ 0xb2, 0xc2, 0x48, 0xe2,
+ 0xc2, 0x40, 0xc2, 0xc2,
+ 0x38, 0x66, 0x4f, 0x2c,
+ 0xa8, 0x51, 0xbd, 0x04,
+ 0xd1, 0x28, 0xf6, 0x0c,
+ 0x5c, 0xc2, 0x4d, 0x7d,
+ 0x25, 0x3e, 0x00, 0xd8,
+ 0x51, 0xe1, 0x2e, 0xf6,
+ 0xe9, 0x91, 0x96, 0xaa,
+ 0x29, 0xbd, 0x0d, 0xad,
+ 0x0e, 0xcd, 0x04, 0x65,
+ 0xd2, 0xff, 0xf1, 0x29,
+ 0xf6, 0xa9, 0x0f, 0x56,
+ 0x7a, 0x13, 0x46, 0xa5,
+ 0x00, 0xd2, 0x22, 0x11,
+ 0x98, 0xf2, 0x56, 0x7d,
+ 0x05, 0x56, 0xe9, 0x04,
+ 0x79, 0x05, 0x91, 0x1a,
+ 0xf6, 0x82, 0x22, 0x10,
+ 0x72, 0x49, 0x7d, 0x16,
+ 0x28, 0x17, 0xa1, 0x21,
+ 0xf6, 0xa9, 0x91, 0xcd,
+ 0x04, 0xd8, 0x02, 0xb8,
+ 0x81, 0xe1, 0x1f, 0xf6,
+ 0xad, 0x0b, 0x25, 0x97,
+ 0xff, 0xd1, 0x1e, 0xf6,
+ 0xb8, 0x0d, 0xc8, 0x06,
+ 0xf0, 0xbb, 0x11, 0xb9,
+ 0x0d, 0xc7, 0x5b, 0x0d,
+ 0xa8, 0x81, 0xb8, 0x91,
+ 0xcd, 0x04, 0xd8, 0x02,
+ 0xe1, 0x18, 0xf6, 0x65,
+ 0x95, 0xff, 0xc8, 0x05,
+ 0xd1, 0x18, 0xf6, 0x1b,
+ 0xcc, 0xd8, 0x0d, 0xc9,
+ 0x05, 0xd7, 0x3c, 0xc6,
+ 0x86, 0x4d, 0x00, 0x2c,
+ 0x0d, 0x0b, 0x99, 0x99,
+ 0xf2, 0xf1, 0x13, 0xf6,
+ 0x88, 0x41, 0x0b, 0xad,
+ 0x00, 0x0a, 0x40, 0x88,
+ 0x28, 0xa9, 0x0f, 0x80,
+ 0x89, 0xa0, 0x88, 0x08,
+ 0x8b, 0xaf, 0x80, 0x80,
+ 0x91, 0x80, 0xf0, 0x04,
+ 0xf9, 0x0a, 0x07, 0xe8,
+ 0x04, 0x98, 0x0b, 0x16,
+ 0xa9, 0x07, 0xdc, 0x4f,
+ 0xa8, 0x0b, 0x66, 0x1a,
+ 0x10, 0xcd, 0x04, 0xd8,
+ 0x02, 0xb8, 0x81, 0xe1,
+ 0x04, 0xf6, 0xad, 0x0b,
+ 0x25, 0x90, 0xff, 0x86,
+ 0x18, 0x00, 0xd8, 0x06,
+ 0x88, 0x0e, 0x0c, 0x29,
+ 0x99, 0x0b, 0x1b, 0x88,
+ 0x89, 0x0e, 0x80, 0x9d,
+ 0xc0, 0x00, 0x19, 0x40,
+ 0x98, 0x0c, 0x00, 0xff,
+ 0xa1, 0xf0, 0xf9, 0x20,
+ 0xf9, 0x0c, 0x87, 0x9d,
+ 0x43, 0x79, 0x05, 0x9c,
+ 0xcd, 0xcd, 0x04, 0xd8,
+ 0x02, 0xb8, 0x81, 0xe1,
+ 0xf7, 0xf5, 0xad, 0x0b,
+ 0xe5, 0x8c, 0xff, 0xa8,
+ 0x05, 0xb8, 0x06, 0x1b,
+ 0xaa, 0xa9, 0x05, 0xb7,
+ 0x3a, 0xe6, 0xf1, 0xf3,
+ 0xf5, 0xf8, 0x0f, 0xa8,
+ 0x81, 0xcd, 0x04, 0xd8,
+ 0x02, 0xe1, 0xef, 0xf5,
+ 0xf0, 0xbf, 0x90, 0x30,
+ 0xbb, 0xa0, 0xe5, 0x8a,
+ 0xff, 0xf1, 0xee, 0xf5,
+ 0x79, 0x0f, 0xe2, 0xcf,
+ 0xf8, 0xc8, 0x2f, 0x79,
+ 0x0e, 0x0b, 0xcc, 0xc9,
+ 0x2f, 0x0c, 0xa2, 0x1d,
+ 0xf0, 0xa1, 0xeb, 0xf5,
+ 0x0c, 0x1b, 0x25, 0xb4,
+ 0xff, 0x81, 0xe3, 0xf5,
+ 0xa9, 0x08, 0xdc, 0xba,
+ 0xb8, 0x14, 0xa2, 0xc8,
+ 0xd8, 0xa0, 0xbb, 0x11,
+ 0xe5, 0x99, 0xff, 0xc1,
+ 0xdf, 0xf5, 0x98, 0x71,
+ 0xa9, 0x0c, 0xcc, 0x7a,
+ 0xd1, 0xd4, 0xf5, 0x92,
+ 0x4d, 0x7d, 0xc6, 0xf3,
+ 0xff, 0xe1, 0xdb, 0xf5,
+ 0xe9, 0x91, 0x88, 0x06,
+ 0x0c, 0x1f, 0x0b, 0x98,
+ 0x00, 0x19, 0x40, 0x00,
+ 0xcf, 0xa1, 0xc9, 0x05,
+ 0x00, 0x18, 0x40, 0x00,
+ 0xff, 0xa1, 0xf7, 0xbc,
+ 0x1b, 0x0c, 0x12, 0xc0,
+ 0xac, 0x90, 0x30, 0xaa,
+ 0xa0, 0xe5, 0x31, 0x00,
+ 0xd8, 0x06, 0xc8, 0x05,
+ 0x00, 0x1d, 0x40, 0x1b,
+ 0xcc, 0xc9, 0x05, 0x00,
+ 0xb2, 0xa1, 0xb7, 0x3c,
+ 0xe5, 0xa8, 0x91, 0xa5,
+ 0x30, 0x00, 0x21, 0xd2,
+ 0xf5, 0xa2, 0xc2, 0xf4,
+ 0xe5, 0x2f, 0x00, 0xad,
+ 0x02, 0x38, 0x61, 0xa5,
+ 0x2f, 0x00, 0xcc, 0x43,
+ 0xa1, 0xcd, 0xf5, 0x25,
+ 0x2f, 0x00, 0x21, 0xc5,
+ 0xf5, 0x28, 0x02, 0x1d,
+ 0xf0, 0x81, 0xc4, 0xf5,
+ 0x89, 0x91, 0x19, 0x31,
+ 0xd8, 0x02, 0xa8, 0x81,
+ 0x4b, 0xb1, 0xcd, 0x04,
+ 0x71, 0xc8, 0xf5, 0x0c,
+ 0x19, 0x99, 0x01, 0x99,
+ 0x11, 0x99, 0x21, 0xe2,
+ 0xc7, 0xe8, 0x25, 0x7f,
+ 0xff, 0xb8, 0x07, 0x16,
+ 0x3b, 0xf8, 0xbd, 0x04,
+ 0xc8, 0x81, 0x7c, 0xfd,
+ 0xd9, 0x0c, 0xad, 0x0c,
+ 0xe5, 0xb0, 0xff, 0xe1,
+ 0xb7, 0xf5, 0xa9, 0x0e,
+ 0x86, 0xdb, 0xff, 0x0c,
+ 0x6d, 0xa8, 0x81, 0xb8,
+ 0x14, 0x0c, 0x6f, 0xd0,
+ 0xff, 0x63, 0xf9, 0x06,
+ 0x1b, 0xbb, 0xb9, 0x07,
+ 0x25, 0xaa, 0xff, 0xc1,
+ 0xb0, 0xf5, 0xd1, 0xb0,
+ 0xf5, 0xd9, 0x91, 0xa9,
+ 0x0c, 0x56, 0xda, 0xf4,
+ 0xad, 0x0d, 0xb8, 0x07,
+ 0xe5, 0xa8, 0xff, 0xe1,
+ 0xab, 0xf5, 0xa9, 0x0e,
+ 0x56, 0xea, 0xf3, 0xb8,
+ 0x07, 0xa2, 0xce, 0xe4,
+ 0xf0, 0xbb, 0x11, 0xe5,
+ 0xa7, 0xff, 0xc1, 0xa6,
+ 0xf5, 0xa9, 0x0c, 0x56,
+ 0xba, 0xf2, 0xe2, 0xcc,
+ 0xfc, 0x88, 0x51, 0x0c,
+ 0x1f, 0x88, 0x08, 0x0c,
+ 0x0d, 0x1b, 0x88, 0x80,
+ 0xdf, 0x83, 0xd9, 0x0e,
+ 0x16, 0x1d, 0xee, 0xad,
+ 0x02, 0xb8, 0x51, 0x25,
+ 0x94, 0xff, 0x91, 0x9d,
+ 0xf5, 0xa9, 0x09, 0x56,
+ 0x7a, 0xf0, 0x0c, 0x1a,
+ 0xa9, 0x02, 0xc6, 0xb2,
+ 0xff, 0xad, 0x02, 0xbd,
+ 0x04, 0xe5, 0x9b, 0xff,
+ 0x21, 0x9f, 0xf5, 0x0c,
+ 0x0c, 0xc9, 0x05, 0xc0,
+ 0xac, 0x90, 0x30, 0xaa,
+ 0xa0, 0xa5, 0x22, 0x00,
+ 0xc8, 0x05, 0x1b, 0xcc,
+ 0xc9, 0x05, 0xb6, 0xec,
+ 0xed, 0xa1, 0x93, 0xf5,
+ 0xa5, 0x21, 0x00, 0xad,
+ 0x02, 0x65, 0x21, 0x00,
+ 0xa1, 0x95, 0xf5, 0xe5,
+ 0x1f, 0x00, 0xa1, 0x8f,
+ 0xf5, 0x65, 0x1f, 0x00,
+ 0xad, 0x02, 0x25, 0x1f,
+ 0x00, 0xad, 0x03, 0x0c,
+ 0x0b, 0xc2, 0xa6, 0x00,
+ 0x65, 0x96, 0x06, 0x86,
+ 0xa0, 0xff, 0x0c, 0x4d,
+ 0x46, 0xd1, 0xff, 0x0c,
+ 0x5d, 0x06, 0xd0, 0xff,
+ 0xbd, 0x0d, 0xad, 0x0e,
+ 0x65, 0x8d, 0xff, 0xd1,
+ 0x83, 0xf5, 0xa9, 0x0d,
+ 0x56, 0xea, 0xe9, 0xa8,
+ 0x91, 0xcd, 0x04, 0xb1,
+ 0x86, 0xf5, 0xd8, 0x02,
+ 0xcb, 0xeb, 0xa5, 0x6f,
+ 0xff, 0xa8, 0x81, 0xb1,
+ 0x83, 0xf5, 0xa5, 0x8b,
+ 0xff, 0xe1, 0x7b, 0xf5,
+ 0xa9, 0x0e, 0x56, 0x0a,
+ 0xe8, 0x19, 0x31, 0xa8,
+ 0x81, 0x4b, 0xb1, 0xcd,
+ 0x04, 0xd8, 0x02, 0xe2,
+ 0xce, 0xe4, 0x0c, 0x1f,
+ 0xf9, 0x01, 0xf9, 0x11,
+ 0xf9, 0x21, 0x25, 0x6d,
+ 0xff, 0xd8, 0x06, 0xb6,
+ 0x2d, 0x7a, 0x0b, 0xbd,
+ 0x0c, 0x1a, 0x00, 0x1b,
+ 0x40, 0xb1, 0x79, 0xf5,
+ 0x00, 0xaa, 0xa1, 0xa9,
+ 0x0b, 0xb8, 0x14, 0xa0,
+ 0xaa, 0x90, 0x30, 0xaa,
+ 0xa0, 0x1b, 0xbb, 0x25,
+ 0x99, 0xff, 0xc1, 0x6b,
+ 0xf5, 0xa9, 0x0c, 0x56,
+ 0xfa, 0xe3, 0xa8, 0x2c,
+ 0xb8, 0x91, 0xa0, 0xaa,
+ 0x90, 0x30, 0xaa, 0xa0,
+ 0x25, 0x86, 0xff, 0xb1,
+ 0x66, 0xf5, 0xa9, 0x0b,
+ 0x56, 0xaa, 0xe2, 0xd8,
+ 0x06, 0x0c, 0x0c, 0x0b,
+ 0xed, 0xac, 0x4e, 0xc9,
+ 0x05, 0xcd, 0x04, 0xb1,
+ 0x6a, 0xf5, 0xd8, 0x02,
+ 0xb8, 0x0b, 0xe1, 0x61,
+ 0xf5, 0xb0, 0xbb, 0x90,
+ 0x30, 0xbb, 0xa0, 0xad,
+ 0x0b, 0x25, 0x67, 0xff,
+ 0xd8, 0x06, 0xc8, 0x05,
+ 0x0b, 0xed, 0x1b, 0xcc,
+ 0xc9, 0x05, 0xe7, 0x3c,
+ 0xdb, 0x00, 0x1d, 0x40,
+ 0xc1, 0x61, 0xf5, 0x0c,
+ 0x1e, 0xc8, 0x0c, 0x00,
+ 0xee, 0xa1, 0x1b, 0xcc,
+ 0xc9, 0x05, 0xe7, 0x3c,
+ 0x1c, 0x91, 0x58, 0xf5,
+ 0xd8, 0x41, 0x79, 0x09,
+ 0x79, 0x19, 0xe2, 0xc9,
+ 0xf8, 0xd8, 0x1d, 0xf2,
+ 0xc9, 0xf4, 0x82, 0xc9,
+ 0xfc, 0x79, 0x08, 0x79,
+ 0x0f, 0xd9, 0x0e, 0x86,
+ 0x65, 0xff, 0xb8, 0x14,
+ 0xc0, 0xac, 0x90, 0x30,
+ 0xaa, 0xa0, 0x1b, 0xbb,
+ 0x65, 0x90, 0xff, 0xb1,
+ 0x49, 0xf5, 0xa9, 0x0b,
+ 0x56, 0x6a, 0xdb, 0xb8,
+ 0x05, 0xb0, 0xbb, 0x90,
+ 0x30, 0xbb, 0xa0, 0xad,
+ 0x0b, 0xb2, 0xcb, 0xf4,
+ 0x65, 0x7d, 0xff, 0xc1,
+ 0x43, 0xf5, 0xa9, 0x0c,
+ 0x56, 0xea, 0xd9, 0xb8,
+ 0x91, 0xcd, 0x04, 0xd8,
+ 0x02, 0xa8, 0x05, 0xe1,
+ 0x41, 0xf5, 0xa0, 0xaa,
+ 0x90, 0x30, 0xaa, 0xa0,
+ 0x25, 0x5f, 0xff, 0x0c,
+ 0x1b, 0xd8, 0x06, 0xc8,
+ 0x05, 0x00, 0x1d, 0x40,
+ 0x1b, 0xcc, 0xc9, 0x05,
+ 0x00, 0xbb, 0xa1, 0xb7,
+ 0x3c, 0xab, 0xc6, 0xe2,
+ 0xff, 0x00, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0x78,
+ 0x12, 0x9c, 0x67, 0x68,
+ 0x22, 0x82, 0xd6, 0xfe,
+ 0x60, 0x67, 0xa0, 0x62,
+ 0xd6, 0xfe, 0x92, 0x26,
+ 0x7f, 0x62, 0xc6, 0xfc,
+ 0xcc, 0x39, 0x0b, 0x77,
+ 0x87, 0x96, 0xf2, 0x88,
+ 0x13, 0x68, 0x23, 0x9c,
+ 0x48, 0x92, 0xd6, 0xfe,
+ 0x60, 0x68, 0xa0, 0x62,
+ 0xd6, 0xfe, 0xa2, 0x26,
+ 0x7f, 0x62, 0xc6, 0xfc,
+ 0xcc, 0x3a, 0x0b, 0x88,
+ 0x97, 0x96, 0xf2, 0xcc,
+ 0x17, 0x16, 0x28, 0x05,
+ 0x77, 0xb8, 0x03, 0x28,
+ 0x02, 0x1d, 0xf0, 0x68,
+ 0x03, 0x87, 0x37, 0x0f,
+ 0xa8, 0x02, 0x88, 0x22,
+ 0xa6, 0x1a, 0x0d, 0xd6,
+ 0xa6, 0x00, 0x0c, 0x12,
+ 0x1d, 0xf0, 0x6d, 0x0a,
+ 0x60, 0x20, 0x60, 0x1d,
+ 0xf0, 0xa6, 0x16, 0x06,
+ 0xd6, 0x3a, 0x00, 0x7c,
+ 0xf2, 0x1d, 0xf0, 0xac,
+ 0x47, 0x80, 0x67, 0xa0,
+ 0x38, 0x23, 0x82, 0xd8,
+ 0xfe, 0x62, 0xd6, 0xfe,
+ 0x30, 0x37, 0xa0, 0x32,
+ 0xd3, 0xfe, 0x92, 0x26,
+ 0x7f, 0x72, 0x23, 0x7f,
+ 0x97, 0x37, 0x0f, 0x77,
+ 0x39, 0xcf, 0x32, 0xc3,
+ 0xfc, 0x62, 0xc6, 0xfc,
+ 0x87, 0x96, 0xea, 0x0c,
+ 0x02, 0x1d, 0xf0, 0x2d,
+ 0x0a, 0x1d, 0xf0, 0x00,
+ 0x36, 0x41, 0x00, 0x8c,
+ 0x82, 0x0c, 0x13, 0x0c,
+ 0x08, 0x89, 0x12, 0x89,
+ 0x22, 0x39, 0x02, 0x1d,
+ 0xf0, 0x00, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0x9c,
+ 0xb2, 0xa8, 0x22, 0x8c,
+ 0xda, 0xc8, 0x12, 0x0c,
+ 0x0b, 0xe0, 0xcc, 0x11,
+ 0xa5, 0x75, 0x06, 0xa8,
+ 0x22, 0xa5, 0xa2, 0xfe,
+ 0x0c, 0x1d, 0x0c, 0x0e,
+ 0xe9, 0x12, 0xe9, 0x22,
+ 0xd9, 0x02, 0x1d, 0xf0,
+ 0x36, 0x41, 0x00, 0x9c,
+ 0x12, 0xc8, 0x02, 0x8c,
+ 0xdc, 0xa8, 0x12, 0xbd,
+ 0x03, 0x88, 0x4c, 0xcd,
+ 0x04, 0xe0, 0x08, 0x00,
+ 0x0c, 0x02, 0x1d, 0xf0,
+ 0x21, 0x05, 0xf5, 0x1d,
+ 0xf0, 0x00, 0x00, 0x00,
+ 0x36, 0xa1, 0x00, 0x7d,
+ 0x04, 0xad, 0x01, 0x0c,
+ 0x0b, 0x2c, 0x0c, 0xe5,
+ 0x71, 0x06, 0x92, 0xc1,
+ 0x20, 0x0c, 0x08, 0x89,
+ 0x09, 0x48, 0x06, 0x48,
+ 0x24, 0x16, 0xa3, 0x05,
+ 0x79, 0x91, 0x40, 0x73,
+ 0x63, 0x8c, 0x96, 0xa8,
+ 0x06, 0x8c, 0x5a, 0x88,
+ 0x3a, 0xa8, 0x16, 0xe0,
+ 0x08, 0x00, 0xcd, 0x05,
+ 0xad, 0x06, 0xb8, 0x91,
+ 0xa5, 0xfa, 0xff, 0xad,
+ 0x06, 0xb2, 0xc1, 0x20,
+ 0x0c, 0x4c, 0x25, 0xfa,
+ 0xff, 0x8c, 0xb6, 0xa8,
+ 0x06, 0x8c, 0x7a, 0xbd,
+ 0x01, 0x88, 0x5a, 0xa8,
+ 0x16, 0xe0, 0x08, 0x00,
+ 0x9c, 0x57, 0x1a, 0xd7,
+ 0xcd, 0x01, 0x92, 0x0c,
+ 0x00, 0xb2, 0x02, 0x00,
+ 0x1b, 0xcc, 0xb0, 0x99,
+ 0x30, 0x92, 0x42, 0x00,
+ 0x1b, 0x22, 0xd7, 0x9c,
+ 0xec, 0xc2, 0x01, 0x23,
+ 0x70, 0x33, 0xc0, 0x1b,
+ 0xcc, 0xc2, 0x41, 0x23,
+ 0x56, 0x63, 0xfa, 0x1d,
+ 0xf0, 0x00, 0x00, 0x00,
+ 0x36, 0x81, 0x00, 0x0c,
+ 0x0d, 0xb2, 0x22, 0x29,
+ 0xa1, 0xe3, 0xf4, 0x16,
+ 0x9b, 0x09, 0x26, 0x1b,
+ 0x5c, 0x0c, 0x22, 0x1d,
+ 0xf0, 0x16, 0xc6, 0x09,
+ 0x56, 0x9a, 0x09, 0x1b,
+ 0x55, 0x0b, 0x77, 0x66,
+ 0x07, 0x2e, 0x1b, 0xa5,
+ 0xbd, 0x04, 0x1c, 0x0c,
+ 0x0c, 0x08, 0x82, 0x45,
+ 0x00, 0xa5, 0x54, 0x06,
+ 0xc1, 0xd9, 0xf4, 0xad,
+ 0x02, 0xbd, 0x0c, 0xa5,
+ 0x3f, 0x00, 0x2d, 0x0a,
+ 0x1d, 0xf0, 0xd2, 0x4a,
+ 0x00, 0x72, 0xcb, 0xec,
+ 0x2b, 0x5a, 0x92, 0xcb,
+ 0xed, 0x0c, 0x2c, 0xc2,
+ 0x4a, 0x01, 0x16, 0x09,
+ 0xfd, 0x62, 0xa0, 0x64,
+ 0x0c, 0x0a, 0xbd, 0x05,
+ 0x0c, 0x1c, 0xe0, 0x03,
+ 0x00, 0xd2, 0x05, 0x00,
+ 0x56, 0x1d, 0xfb, 0x0b,
+ 0x66, 0x16, 0xc6, 0x04,
+ 0x16, 0x8a, 0xfe, 0x86,
+ 0xe9, 0xff, 0xe1, 0xca,
+ 0xf4, 0xe2, 0x0e, 0x7e,
+ 0xec, 0x1e, 0x66, 0x1b,
+ 0x1b, 0x9c, 0x83, 0xa2,
+ 0x22, 0x2a, 0xa5, 0x1e,
+ 0x00, 0x6d, 0x0a, 0x8c,
+ 0xea, 0x52, 0x0a, 0x08,
+ 0x78, 0x12, 0xf0, 0xf5,
+ 0x11, 0xf9, 0x31, 0xf2,
+ 0xcf, 0x12, 0xf7, 0xb7,
+ 0x23, 0x0c, 0x12, 0x1d,
+ 0xf0, 0x6d, 0x0a, 0xad,
+ 0x02, 0xbd, 0x06, 0xcd,
+ 0x06, 0xe5, 0x38, 0x00,
+ 0x2d, 0x0a, 0x1d, 0xf0,
+ 0x8c, 0x53, 0xb8, 0x12,
+ 0x1c, 0xa8, 0xb7, 0x38,
+ 0x8c, 0x0c, 0x12, 0x1d,
+ 0xf0, 0x9b, 0x2a, 0x1d,
+ 0xf0, 0x0c, 0x0b, 0xcd,
+ 0x07, 0xa1, 0xb5, 0xf4,
+ 0xa9, 0x21, 0xa5, 0x5e,
+ 0x06, 0xb1, 0xb5, 0xf4,
+ 0x0c, 0x0a, 0xcd, 0x05,
+ 0xa2, 0x4b, 0x80, 0x0c,
+ 0x0a, 0xb1, 0xb3, 0xf4,
+ 0xb9, 0x51, 0xe0, 0x03,
+ 0x00, 0x38, 0x51, 0x8c,
+ 0x2a, 0x9b, 0x2a, 0x1d,
+ 0xf0, 0x0c, 0x0a, 0x0c,
+ 0x0b, 0x3a, 0xc5, 0x88,
+ 0x66, 0xc9, 0x41, 0xe0,
+ 0x08, 0x00, 0xbd, 0x04,
+ 0xc8, 0x31, 0xa8, 0x41,
+ 0xc0, 0xc7, 0xc0, 0xaa,
+ 0xa5, 0xca, 0xaa, 0xd2,
+ 0xda, 0xff, 0x0c, 0x1c,
+ 0xa2, 0xca, 0xef, 0xc2,
+ 0x4d, 0xee, 0x1c, 0x0c,
+ 0xe5, 0x46, 0x06, 0x48,
+ 0x41, 0x0c, 0x09, 0x99,
+ 0x01, 0x99, 0x11, 0x88,
+ 0xd6, 0xad, 0x01, 0xe0,
+ 0x08, 0x00, 0xa9, 0x11,
+ 0x8c, 0x5a, 0x88, 0x36,
+ 0x69, 0x01, 0xe0, 0x08,
+ 0x00, 0x68, 0x21, 0xad,
+ 0x04, 0xcd, 0x03, 0xdd,
+ 0x05, 0xed, 0x01, 0x50,
+ 0x77, 0xc0, 0x0b, 0x77,
+ 0xbd, 0x07, 0xe5, 0xe4,
+ 0xff, 0xad, 0x03, 0xbd,
+ 0x05, 0xcd, 0x04, 0xdd,
+ 0x07, 0xed, 0x01, 0x25,
+ 0xe4, 0xff, 0xa8, 0x01,
+ 0x16, 0xfa, 0xf4, 0x88,
+ 0xea, 0xa8, 0x11, 0xe0,
+ 0x08, 0x00, 0x0c, 0x09,
+ 0x99, 0x11, 0x46, 0xd0,
+ 0xff, 0x00, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0x41,
+ 0x91, 0xf4, 0xa1, 0x91,
+ 0xf4, 0x82, 0xaf, 0x70,
+ 0x87, 0x1a, 0x20, 0x9c,
+ 0xd2, 0x92, 0x2a, 0x24,
+ 0x9c, 0x89, 0x58, 0x12,
+ 0xa8, 0x14, 0x57, 0x9a,
+ 0x0a, 0xa8, 0x04, 0xb8,
+ 0x22, 0xcd, 0x05, 0xe5,
+ 0x38, 0x06, 0x8c, 0x8a,
+ 0xb8, 0x54, 0x42, 0xc4,
+ 0x14, 0x56, 0x7b, 0xfe,
+ 0x0c, 0x04, 0x8c, 0x64,
+ 0x0c, 0x02, 0xc8, 0x44,
+ 0xc9, 0x03, 0x1d, 0xf0,
+ 0x22, 0xaf, 0xd2, 0x1d,
+ 0xf0, 0x00, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0x88,
+ 0x02, 0x80, 0x63, 0xc0,
+ 0xe6, 0x16, 0x04, 0x22,
+ 0xaf, 0xa0, 0x1d, 0xf0,
+ 0x72, 0x08, 0x00, 0x2b,
+ 0x98, 0x77, 0x15, 0x04,
+ 0x22, 0xaf, 0x9e, 0x1d,
+ 0xf0, 0x1b, 0x78, 0x79,
+ 0x02, 0x70, 0x73, 0xc0,
+ 0xe6, 0x17, 0x1a, 0x22,
+ 0xaf, 0xa0, 0x1d, 0xf0,
+ 0xa6, 0x27, 0xf7, 0x52,
+ 0x08, 0x02, 0x59, 0x04,
+ 0x3b, 0x88, 0x89, 0x02,
+ 0x80, 0x93, 0xc0, 0x57,
+ 0x39, 0xe8, 0x0c, 0x02,
+ 0x1d, 0xf0, 0x52, 0x08,
+ 0x01, 0x77, 0xe5, 0x08,
+ 0x99, 0x02, 0x59, 0x04,
+ 0x8d, 0x09, 0x86, 0xf9,
+ 0xff, 0x50, 0x50, 0x64,
+ 0x26, 0x15, 0xd4, 0x26,
+ 0x25, 0x0a, 0x26, 0x35,
+ 0x1f, 0x26, 0x45, 0x3d,
+ 0x22, 0xaf, 0x9c, 0x1d,
+ 0xf0, 0xa6, 0x37, 0xbe,
+ 0x62, 0x08, 0x02, 0x52,
+ 0x08, 0x03, 0x80, 0x66,
+ 0x11, 0x4b, 0x88, 0x89,
+ 0x02, 0x60, 0x55, 0x20,
+ 0x59, 0x04, 0x86, 0xee,
+ 0xff, 0xa6, 0x47, 0xa6,
+ 0x52, 0x08, 0x04, 0x72,
+ 0x08, 0x03, 0x62, 0x08,
+ 0x02, 0x80, 0x77, 0x11,
+ 0x00, 0x66, 0x11, 0x5b,
+ 0x88, 0x89, 0x02, 0x70,
+ 0x66, 0x20, 0x60, 0x55,
+ 0x20, 0x59, 0x04, 0x46,
+ 0xe6, 0xff, 0xa6, 0x57,
+ 0x85, 0x72, 0x08, 0x03,
+ 0x62, 0x08, 0x04, 0x52,
+ 0x08, 0x05, 0x80, 0x66,
+ 0x11, 0x60, 0x55, 0x20,
+ 0x00, 0x77, 0x11, 0x62,
+ 0x08, 0x02, 0x6b, 0x88,
+ 0x89, 0x02, 0x80, 0x66,
+ 0x01, 0x70, 0x66, 0x20,
+ 0x60, 0x55, 0x20, 0x59,
+ 0x04, 0xc6, 0xdb, 0xff,
+ 0x36, 0x41, 0x00, 0x26,
+ 0x22, 0x0c, 0x42, 0xc2,
+ 0xfd, 0x31, 0x4e, 0xf4,
+ 0x0c, 0x02, 0x40, 0x23,
+ 0x83, 0x1d, 0xf0, 0x21,
+ 0x4d, 0xf4, 0x1d, 0xf0,
+ 0x36, 0x61, 0x00, 0x0c,
+ 0xb8, 0xad, 0x05, 0xdd,
+ 0x03, 0x71, 0x4a, 0xf4,
+ 0xbd, 0x06, 0xe2, 0xd2,
+ 0x01, 0x61, 0x49, 0xf4,
+ 0x92, 0xce, 0x8c, 0xc2,
+ 0xce, 0x98, 0xc9, 0xb7,
+ 0x4b, 0x47, 0x99, 0xa7,
+ 0x32, 0xc7, 0x10, 0xf2,
+ 0x06, 0xde, 0x52, 0xc7,
+ 0x1c, 0x87, 0xbf, 0x3a,
+ 0xa9, 0x01, 0x91, 0x43,
+ 0xf4, 0xf0, 0x8f, 0x90,
+ 0x9a, 0x88, 0xa0, 0x08,
+ 0x00, 0xc6, 0x17, 0x00,
+ 0x86, 0x59, 0x00, 0x46,
+ 0x4f, 0x00, 0x06, 0x45,
+ 0x00, 0x46, 0x04, 0x00,
+ 0x06, 0x3f, 0x00, 0xc6,
+ 0x39, 0x00, 0xc6, 0x0b,
+ 0x00, 0x46, 0x33, 0x00,
+ 0xc6, 0x28, 0x00, 0xc6,
+ 0x21, 0x00, 0xad, 0x04,
+ 0xbd, 0x05, 0xcd, 0x03,
+ 0x25, 0x62, 0xff, 0xa9,
+ 0x07, 0xac, 0x7a, 0xad,
+ 0x04, 0x65, 0xc5, 0xff,
+ 0xad, 0x05, 0x25, 0xc5,
+ 0xff, 0xad, 0x03, 0xe5,
+ 0xc4, 0xff, 0xb8, 0x07,
+ 0x0c, 0x0a, 0x6b, 0x2b,
+ 0xb0, 0x2a, 0x83, 0x1d,
+ 0xf0, 0xc2, 0xc2, 0x38,
+ 0xad, 0x05, 0xbd, 0x04,
+ 0x25, 0x54, 0xff, 0xa9,
+ 0x07, 0x56, 0x6a, 0xfd,
+ 0xc2, 0x06, 0xde, 0x1b,
+ 0xcc, 0xc2, 0x46, 0xde,
+ 0x0c, 0xa2, 0x1d, 0xf0,
+ 0xad, 0x04, 0x1b, 0xdf,
+ 0xd2, 0x46, 0xde, 0xe5,
+ 0xc1, 0xff, 0xad, 0x05,
+ 0x65, 0xc1, 0xff, 0xad,
+ 0x03, 0x25, 0xc1, 0xff,
+ 0xad, 0x04, 0xa5, 0xbf,
+ 0xff, 0xad, 0x05, 0x65,
+ 0xbf, 0xff, 0xad, 0x03,
+ 0x68, 0x01, 0xe5, 0xbe,
+ 0xff, 0xbd, 0x06, 0xad,
+ 0x04, 0xc8, 0x12, 0xe5,
+ 0x2b, 0x00, 0xa9, 0x07,
+ 0x56, 0x7a, 0xf9, 0x8b,
+ 0xb2, 0xad, 0x04, 0xe5,
+ 0xb3, 0xff, 0x96, 0xea,
+ 0xfb, 0xad, 0x04, 0x65,
+ 0xbe, 0xff, 0x0c, 0x12,
+ 0x1d, 0xf0, 0xad, 0x04,
+ 0xc8, 0x12, 0xc9, 0xc7,
+ 0x65, 0x5e, 0xff, 0xa9,
+ 0x07, 0x56, 0x6a, 0xf7,
+ 0xe2, 0x06, 0xde, 0x1b,
+ 0xee, 0xe2, 0x46, 0xde,
+ 0x06, 0xe7, 0xff, 0x9c,
+ 0xbd, 0xad, 0x04, 0xbd,
+ 0x04, 0xa5, 0x4c, 0xff,
+ 0xa9, 0x07, 0x56, 0xda,
+ 0xf5, 0x8b, 0xc2, 0xad,
+ 0x04, 0xbd, 0x04, 0x65,
+ 0x45, 0xff, 0xa9, 0x07,
+ 0x56, 0xfa, 0xf4, 0xf2,
+ 0x06, 0xde, 0x1b, 0x8f,
+ 0x82, 0x46, 0xde, 0x46,
+ 0xdd, 0xff, 0xad, 0x04,
+ 0xbd, 0x03, 0xcd, 0x05,
+ 0xe5, 0x3e, 0xff, 0xa9,
+ 0x07, 0x56, 0x6a, 0xf3,
+ 0xf2, 0x06, 0xde, 0xc6,
+ 0xf8, 0xff, 0xc2, 0xc2,
+ 0x2c, 0xad, 0x04, 0xbd,
+ 0x05, 0x65, 0x42, 0xff,
+ 0xa9, 0x07, 0x56, 0x1a,
+ 0xf2, 0xc6, 0xd1, 0xff,
+ 0xc2, 0xc2, 0x5c, 0xad,
+ 0x05, 0xbd, 0x04, 0xe5,
+ 0x47, 0xff, 0xa9, 0x07,
+ 0x56, 0xfa, 0xf0, 0x46,
+ 0xcd, 0xff, 0xc2, 0xc2,
+ 0x50, 0xd2, 0xc2, 0x38,
+ 0xe2, 0xce, 0x80, 0xad,
+ 0x03, 0xbd, 0x04, 0x65,
+ 0x5b, 0xff, 0xa9, 0x07,
+ 0x92, 0xca, 0xf6, 0x16,
+ 0x59, 0xf2, 0xb2, 0x06,
+ 0xde, 0x1b, 0xbb, 0xb2,
+ 0x46, 0xde, 0x56, 0x9a,
+ 0xee, 0xc6, 0xc5, 0xff,
+ 0xc2, 0xc2, 0x44, 0xd2,
+ 0xc2, 0x2c, 0xe2, 0xc2,
+ 0x74, 0xad, 0x05, 0xbd,
+ 0x04, 0xe5, 0x58, 0xff,
+ 0xa9, 0x07, 0xc2, 0xca,
+ 0xf6, 0x16, 0xfc, 0xef,
+ 0xd2, 0x06, 0xde, 0x1b,
+ 0xdd, 0xd2, 0x46, 0xde,
+ 0x56, 0x3a, 0xec, 0x46,
+ 0xbc, 0xff, 0x1b, 0xef,
+ 0xe2, 0x46, 0xde, 0x46,
+ 0xba, 0xff, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0x61,
+ 0xe3, 0xf3, 0xb1, 0xd8,
+ 0xf3, 0x4b, 0x56, 0xa2,
+ 0x0b, 0x7e, 0x72, 0xc6,
+ 0x10, 0xec, 0xda, 0x1b,
+ 0x8a, 0xad, 0x05, 0x82,
+ 0x4b, 0x7e, 0x65, 0xaf,
+ 0xff, 0xad, 0x05, 0xe5,
+ 0xad, 0xff, 0xbd, 0x03,
+ 0xad, 0x05, 0xc8, 0x12,
+ 0xa5, 0x1a, 0x00, 0xa9,
+ 0x06, 0xfc, 0x0a, 0xad,
+ 0x05, 0x8b, 0xb2, 0xe5,
+ 0xa2, 0xff, 0x96, 0x7a,
+ 0x03, 0xad, 0x05, 0x65,
+ 0xad, 0xff, 0x0c, 0x12,
+ 0x1d, 0xf0, 0xc2, 0xc2,
+ 0x14, 0x8b, 0xd2, 0xe2,
+ 0xc2, 0x68, 0xad, 0x05,
+ 0xbd, 0x05, 0xe5, 0x51,
+ 0xff, 0xa9, 0x06, 0x26,
+ 0x9a, 0x1e, 0xbd, 0x04,
+ 0xc8, 0x07, 0xad, 0x05,
+ 0x25, 0x4c, 0xff, 0xa9,
+ 0x06, 0xad, 0x05, 0xe5,
+ 0xaa, 0xff, 0xa8, 0x06,
+ 0x0c, 0x09, 0x5b, 0x2a,
+ 0xa0, 0x29, 0x83, 0x1d,
+ 0xf0, 0xb8, 0x12, 0xb9,
+ 0x07, 0x0c, 0xa2, 0x1d,
+ 0xf0, 0x00, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0x82,
+ 0x22, 0x29, 0x8c, 0x88,
+ 0x0c, 0x22, 0x1d, 0xf0,
+ 0x0c, 0x02, 0x1d, 0xf0,
+ 0x1d, 0xf0, 0x91, 0xb6,
+ 0xf3, 0x51, 0xc0, 0xf3,
+ 0x92, 0x09, 0x7e, 0xb2,
+ 0xa1, 0xf1, 0xcc, 0x99,
+ 0xa8, 0x12, 0xa2, 0x65,
+ 0xc5, 0xa2, 0xca, 0xf0,
+ 0xb7, 0xba, 0x5b, 0xbd,
+ 0x04, 0xad, 0x02, 0xc1,
+ 0xbb, 0xf3, 0x25, 0xf5,
+ 0xff, 0x2d, 0x0a, 0x56,
+ 0x5a, 0xfd, 0x91, 0xb9,
+ 0xf3, 0x82, 0x09, 0x80,
+ 0xa1, 0xb9, 0xf3, 0x56,
+ 0xc8, 0x04, 0x46, 0x10,
+ 0x00, 0xb2, 0x0a, 0x00,
+ 0xc2, 0x25, 0xc5, 0x9c,
+ 0x4b, 0xe2, 0xa0, 0xff,
+ 0xd2, 0xc9, 0x7f, 0xda,
+ 0xdc, 0xd7, 0xba, 0x36,
+ 0xe7, 0x9b, 0x33, 0xb2,
+ 0x0a, 0x01, 0x1b, 0xaa,
+ 0x56, 0x1b, 0xff, 0xe1,
+ 0x6d, 0xf3, 0x1b, 0xfa,
+ 0xf2, 0x65, 0xc7, 0x0c,
+ 0x3a, 0xf0, 0xfc, 0xc0,
+ 0xfa, 0xee, 0xe2, 0xde,
+ 0x44, 0xe2, 0xce, 0xc0,
+ 0xe2, 0x65, 0xc4, 0xe5,
+ 0xd3, 0xff, 0xa2, 0x65,
+ 0xca, 0xdc, 0x1a, 0x0c,
+ 0x12, 0x1d, 0xf0, 0xb2,
+ 0x0a, 0x00, 0x1b, 0xaa,
+ 0x26, 0x1b, 0xb5, 0x0c,
+ 0x22, 0xa2, 0x65, 0xc7,
+ 0x1d, 0xf0, 0x3c, 0x0d,
+ 0xc2, 0x25, 0xc7, 0xb2,
+ 0x25, 0xc4, 0x21, 0xa1,
+ 0xf3, 0x62, 0x0a, 0x08,
+ 0x42, 0xc2, 0xfc, 0xad,
+ 0x02, 0xca, 0xbb, 0xb2,
+ 0x65, 0xc8, 0xcd, 0x04,
+ 0xe5, 0xc3, 0xff, 0x56,
+ 0x7a, 0x09, 0xe2, 0x25,
+ 0xc6, 0xd2, 0x25, 0xc4,
+ 0x2b, 0xee, 0xe0, 0xdd,
+ 0xc0, 0x56, 0x9d, 0x08,
+ 0xad, 0x02, 0xb2, 0x25,
+ 0xc8, 0xcd, 0x04, 0x3c,
+ 0x0d, 0x25, 0xc2, 0xff,
+ 0x56, 0xaa, 0x07, 0x82,
+ 0x25, 0xc6, 0xf2, 0x25,
+ 0xc4, 0x6a, 0x88, 0x6b,
+ 0x88, 0x87, 0x9f, 0x6d,
+ 0xad, 0x02, 0xb2, 0x25,
+ 0xc8, 0xc1, 0x90, 0xf3,
+ 0x0c, 0x6d, 0x65, 0xc0,
+ 0xff, 0x56, 0xda, 0x05,
+ 0x92, 0x25, 0xcc, 0xa2,
+ 0x25, 0xc7, 0xa2, 0x65,
+ 0xcd, 0xaa, 0x99, 0xa1,
+ 0x8c, 0xf3, 0x92, 0x65,
+ 0xc7, 0xb2, 0xca, 0xf8,
+ 0x65, 0xba, 0xff, 0x56,
+ 0x3a, 0x04, 0xb2, 0x25,
+ 0xc9, 0x66, 0x3b, 0x3d,
+ 0xad, 0x02, 0xb2, 0x25,
+ 0xc8, 0xcd, 0x04, 0x0c,
+ 0x5d, 0x65, 0xbd, 0xff,
+ 0xec, 0xea, 0xcd, 0x04,
+ 0xad, 0x02, 0xb2, 0x25,
+ 0xc8, 0x0c, 0x4d, 0xa5,
+ 0xbc, 0xff, 0xec, 0x0a,
+ 0xc2, 0x25, 0xc6, 0x67,
+ 0x9c, 0x1b, 0xbd, 0x03,
+ 0x22, 0x25, 0xc7, 0xcd,
+ 0x06, 0xad, 0x02, 0x25,
+ 0xf2, 0x05, 0xcc, 0xca,
+ 0x2a, 0xe6, 0xd2, 0x25,
+ 0xc8, 0xe2, 0x65, 0xc7,
+ 0xe0, 0xdd, 0xc0, 0x16,
+ 0x9d, 0xeb, 0x0c, 0x72,
+ 0x1d, 0xf0, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0x9c,
+ 0x34, 0x0c, 0x05, 0x4a,
+ 0xb3, 0xad, 0x03, 0x82,
+ 0x0a, 0x00, 0x1b, 0xaa,
+ 0xcc, 0x88, 0x1b, 0x55,
+ 0xb7, 0x9a, 0xf3, 0x46,
+ 0x00, 0x00, 0x0c, 0x05,
+ 0xad, 0x02, 0x50, 0xb4,
+ 0xc0, 0x3b, 0xbb, 0xb0,
+ 0xb2, 0x41, 0xe5, 0x11,
+ 0xff, 0xfc, 0xba, 0xad,
+ 0x02, 0x0c, 0x0b, 0x65,
+ 0x0e, 0xff, 0xfc, 0x2a,
+ 0x47, 0xb5, 0x30, 0x0c,
+ 0x0b, 0xe8, 0x22, 0x5a,
+ 0xf3, 0x4a, 0xc3, 0xc2,
+ 0xcc, 0x80, 0xf2, 0xcf,
+ 0x80, 0xb0, 0xd0, 0x14,
+ 0x92, 0x0c, 0x7f, 0xb0,
+ 0x82, 0x41, 0x0b, 0xcc,
+ 0xe0, 0x88, 0xa0, 0xd0,
+ 0xdd, 0x11, 0x00, 0x1d,
+ 0x40, 0x1b, 0xbb, 0xd8,
+ 0x08, 0x00, 0x99, 0xa1,
+ 0x90, 0xdd, 0x20, 0xd9,
+ 0x08, 0xf7, 0x9c, 0xdc,
+ 0x2d, 0x0a, 0x1d, 0xf0,
+ 0x36, 0x41, 0x00, 0xa2,
+ 0xd2, 0x01, 0xa2, 0xca,
+ 0x8c, 0x65, 0x8c, 0xff,
+ 0xa2, 0xd2, 0x01, 0xa2,
+ 0xca, 0x98, 0xe5, 0x8b,
+ 0xff, 0xa2, 0xd2, 0x01,
+ 0xa2, 0xca, 0x80, 0x65,
+ 0x8b, 0xff, 0xa2, 0xc2,
+ 0x74, 0xe5, 0x8a, 0xff,
+ 0xa2, 0xc2, 0x68, 0xa5,
+ 0x8a, 0xff, 0xa2, 0xc2,
+ 0x5c, 0x25, 0x8a, 0xff,
+ 0xa2, 0xc2, 0x50, 0xe5,
+ 0x89, 0xff, 0xa2, 0xc2,
+ 0x44, 0x65, 0x89, 0xff,
+ 0xa2, 0xc2, 0x38, 0x25,
+ 0x89, 0xff, 0xa2, 0xc2,
+ 0x2c, 0xa5, 0x88, 0xff,
+ 0xa2, 0xc2, 0x20, 0x65,
+ 0x88, 0xff, 0xa2, 0xc2,
+ 0x14, 0xe5, 0x87, 0xff,
+ 0x8b, 0xa2, 0xa5, 0x87,
+ 0xff, 0x1d, 0xf0, 0x00,
+ 0x36, 0xe1, 0x01, 0xbd,
+ 0x05, 0xad, 0x01, 0xe5,
+ 0x05, 0x05, 0xcd, 0x03,
+ 0xbd, 0x02, 0xad, 0x01,
+ 0xa5, 0xfc, 0x04, 0xbd,
+ 0x04, 0xad, 0x01, 0x25,
+ 0xf3, 0x04, 0xad, 0x01,
+ 0x0c, 0x0b, 0xc2, 0xa0,
+ 0xcc, 0xe5, 0xfb, 0x05,
+ 0x1d, 0xf0, 0x00, 0x00,
+ 0x36, 0xe1, 0x00, 0x2c,
+ 0x0b, 0xcd, 0x01, 0xa1,
+ 0xf3, 0xf2, 0xe2, 0xa2,
+ 0x6e, 0xe0, 0xe2, 0xd1,
+ 0x0c, 0x0d, 0xea, 0xaa,
+ 0xa2, 0xda, 0x4b, 0xa2,
+ 0xca, 0xdd, 0xe5, 0xfb,
+ 0xff, 0x2c, 0x0b, 0xc2,
+ 0xc1, 0x20, 0x0c, 0x5d,
+ 0xe2, 0xc1, 0x30, 0x0c,
+ 0x0f, 0x42, 0x41, 0x21,
+ 0xf2, 0x41, 0x20, 0xa2,
+ 0x05, 0x00, 0xa2, 0x41,
+ 0x22, 0xad, 0x01, 0x92,
+ 0x05, 0x01, 0x92, 0x41,
+ 0x23, 0x82, 0x05, 0x02,
+ 0x82, 0x41, 0x24, 0x65,
+ 0x06, 0xfe, 0xad, 0x03,
+ 0xb2, 0xc1, 0x30, 0x2c,
+ 0x0c, 0xa5, 0xdc, 0x05,
+ 0x0c, 0x1b, 0x0c, 0x02,
+ 0xa0, 0x2b, 0x83, 0x1d,
+ 0xf0, 0x00, 0x00, 0x00,
+ 0x36, 0xa1, 0x00, 0xbd,
+ 0x05, 0x60, 0xc8, 0x41,
+ 0x5d, 0x07, 0x7d, 0x02,
+ 0x60, 0x24, 0x44, 0x20,
+ 0x22, 0xa0, 0x4a, 0xa2,
+ 0xc2, 0x4a, 0x00, 0x62,
+ 0x4a, 0x01, 0x0c, 0x3c,
+ 0x2b, 0xaa, 0xa5, 0xe0,
+ 0x05, 0xcd, 0x04, 0x5b,
+ 0xd2, 0xed, 0x01, 0xa1,
+ 0xd4, 0xf2, 0xb2, 0xa2,
+ 0x6e, 0xb0, 0xb7, 0xd1,
+ 0x0c, 0x0f, 0xba, 0xaa,
+ 0x2c, 0x0b, 0xa2, 0xda,
+ 0x4b, 0xa2, 0xca, 0xdd,
+ 0xe5, 0x00, 0xfe, 0xad,
+ 0x03, 0xbd, 0x01, 0x1c,
+ 0x0c, 0x65, 0xd7, 0x05,
+ 0xcc, 0xca, 0xad, 0x05,
+ 0xb2, 0xc1, 0x10, 0x1c,
+ 0x0c, 0x65, 0xdd, 0x05,
+ 0x0c, 0x12, 0x1d, 0xf0,
+ 0x0c, 0x02, 0x1d, 0xf0,
+ 0x36, 0xe1, 0x00, 0xb2,
+ 0xc1, 0x84, 0x62, 0xc1,
+ 0x94, 0xa2, 0xc1, 0x8b,
+ 0xe1, 0x0a, 0xf3, 0x42,
+ 0x61, 0x10, 0x32, 0x61,
+ 0x13, 0x42, 0x21, 0x13,
+ 0x32, 0xa2, 0x6e, 0x30,
+ 0x34, 0xd1, 0x71, 0xbf,
+ 0xf2, 0xea, 0xe3, 0x7a,
+ 0x73, 0x52, 0xd7, 0x4b,
+ 0x52, 0xc5, 0x80, 0xcd,
+ 0x05, 0xb7, 0x2a, 0x0e,
+ 0x92, 0x0c, 0x55, 0x82,
+ 0x0c, 0x4d, 0x90, 0x88,
+ 0x30, 0x82, 0x4b, 0x84,
+ 0x46, 0x01, 0x00, 0xd2,
+ 0x0c, 0x3d, 0xd2, 0x4b,
+ 0x74, 0x1b, 0xcc, 0x1b,
+ 0xbb, 0x67, 0x9b, 0xe0,
+ 0xe2, 0x61, 0x11, 0xc2,
+ 0xd7, 0x4b, 0xdb, 0xfc,
+ 0xe2, 0x0e, 0x7d, 0xf2,
+ 0x61, 0x12, 0xcc, 0xee,
+ 0xa2, 0xcc, 0xfd, 0x1c,
+ 0x0b, 0x25, 0x7c, 0x00,
+ 0xa2, 0x21, 0x12, 0x0c,
+ 0x8b, 0xa5, 0x7b, 0x00,
+ 0xad, 0x01, 0x65, 0x0c,
+ 0xfe, 0xa2, 0xc1, 0x10,
+ 0x0c, 0x8c, 0xb2, 0xd7,
+ 0x4b, 0xb2, 0xcb, 0x15,
+ 0xe5, 0xd4, 0x05, 0xa2,
+ 0xc1, 0x18, 0x0c, 0x8c,
+ 0xb2, 0xd7, 0x4b, 0xb2,
+ 0xcb, 0xba, 0x25, 0xd4,
+ 0x05, 0xa2, 0xc1, 0x10,
+ 0xf2, 0x21, 0x11, 0xb2,
+ 0xc1, 0x20, 0xf2, 0x0f,
+ 0x21, 0x0c, 0x28, 0x80,
+ 0xff, 0x30, 0xf2, 0x41,
+ 0x1f, 0xa5, 0xf7, 0xfd,
+ 0xcd, 0x05, 0xe2, 0xc1,
+ 0x20, 0xb2, 0xc1, 0x30,
+ 0xa2, 0xc1, 0x27, 0x0c,
+ 0x0d, 0x82, 0x0c, 0x7d,
+ 0x2a, 0x7d, 0xf2, 0x0e,
+ 0x00, 0x1b, 0xdd, 0x80,
+ 0xff, 0x30, 0xf2, 0x47,
+ 0x00, 0xe7, 0xaa, 0x08,
+ 0x92, 0x0c, 0x32, 0xf0,
+ 0x99, 0x30, 0x92, 0x47,
+ 0x00, 0x1b, 0xcc, 0x1b,
+ 0xee, 0xb7, 0x9e, 0xdc,
+ 0xa2, 0xc2, 0x10, 0xb2,
+ 0x21, 0x12, 0x0c, 0x8c,
+ 0xe5, 0xce, 0x05, 0xa1,
+ 0xd6, 0xf2, 0xa2, 0x0a,
+ 0x80, 0xb1, 0xd5, 0xf2,
+ 0x8c, 0xea, 0xa1, 0xd5,
+ 0xf2, 0xc2, 0xc1, 0x30,
+ 0x1c, 0x0d, 0x0c, 0x0e,
+ 0x65, 0x22, 0x01, 0xc6,
+ 0x01, 0x00, 0xa2, 0xc1,
+ 0x30, 0x1c, 0x0c, 0xe5,
+ 0xcc, 0x05, 0xa2, 0x21,
+ 0x10, 0xb2, 0xc1, 0x84,
+ 0xc2, 0xc1, 0x30, 0x81,
+ 0xce, 0xf2, 0x1b, 0xbb,
+ 0xe2, 0x05, 0x7d, 0xd2,
+ 0x0c, 0x00, 0x1b, 0x55,
+ 0x1b, 0xcc, 0xe0, 0xdd,
+ 0x30, 0xd2, 0x4b, 0x7b,
+ 0x67, 0x9b, 0xea, 0x90,
+ 0xb4, 0x11, 0xc0, 0x20,
+ 0x00, 0xd8, 0x08, 0x1c,
+ 0x1c, 0xba, 0xdd, 0xc0,
+ 0x20, 0x00, 0xc9, 0x3d,
+ 0xc0, 0x20, 0x00, 0x98,
+ 0x08, 0x2c, 0x1f, 0xba,
+ 0x99, 0xc0, 0x20, 0x00,
+ 0xf9, 0x39, 0xc0, 0x20,
+ 0x00, 0xe8, 0x08, 0x0c,
+ 0x0d, 0xba, 0xee, 0xc0,
+ 0x20, 0x00, 0xd9, 0xee,
+ 0xc0, 0x20, 0x00, 0x92,
+ 0x01, 0x0f, 0xd2, 0x01,
+ 0x0c, 0xe2, 0x01, 0x0d,
+ 0xc2, 0x01, 0x0e, 0x00,
+ 0xee, 0x11, 0x80, 0xcc,
+ 0x11, 0x80, 0xdd, 0x01,
+ 0xc0, 0x99, 0x20, 0xc8,
+ 0x08, 0xe0, 0xdd, 0x20,
+ 0xd0, 0x99, 0x20, 0xba,
+ 0xcc, 0xc0, 0x20, 0x00,
+ 0x99, 0x4c, 0xc0, 0x20,
+ 0x00, 0xe2, 0x01, 0x0b,
+ 0x92, 0x01, 0x08, 0xc2,
+ 0x01, 0x09, 0xf2, 0x01,
+ 0x0a, 0x00, 0xcc, 0x11,
+ 0x80, 0xff, 0x11, 0x80,
+ 0x99, 0x01, 0xf0, 0xee,
+ 0x20, 0xf8, 0x08, 0xc0,
+ 0x99, 0x20, 0x90, 0xee,
+ 0x20, 0xba, 0xff, 0xc0,
+ 0x20, 0x00, 0xe9, 0x5f,
+ 0xc0, 0x20, 0x00, 0xc2,
+ 0x01, 0x07, 0xe2, 0x01,
+ 0x04, 0xf2, 0x01, 0x05,
+ 0xd2, 0x01, 0x06, 0x00,
+ 0xff, 0x11, 0x80, 0xdd,
+ 0x11, 0x80, 0xee, 0x01,
+ 0xd0, 0xcc, 0x20, 0xd8,
+ 0x08, 0xf0, 0xee, 0x20,
+ 0xe0, 0xcc, 0x20, 0xba,
+ 0xdd, 0xc0, 0x20, 0x00,
+ 0xc9, 0x6d, 0xc0, 0x20,
+ 0x00, 0xf2, 0x01, 0x03,
+ 0xc2, 0x01, 0x00, 0xd2,
+ 0x01, 0x01, 0x92, 0x01,
+ 0x02, 0x00, 0xdd, 0x11,
+ 0x80, 0x99, 0x11, 0x80,
+ 0xcc, 0x01, 0x90, 0xff,
+ 0x20, 0x98, 0x08, 0xd0,
+ 0xcc, 0x20, 0xc0, 0xff,
+ 0x20, 0xba, 0x99, 0xc0,
+ 0x20, 0x00, 0xf9, 0x79,
+ 0xc0, 0x20, 0x00, 0x91,
+ 0x93, 0xf2, 0x9a, 0xd3,
+ 0xe2, 0x0d, 0x7f, 0xc2,
+ 0x0d, 0x80, 0x80, 0xee,
+ 0x11, 0xe0, 0xcc, 0x20,
+ 0xe2, 0x0d, 0x7e, 0xd2,
+ 0x0d, 0x7d, 0x00, 0xee,
+ 0x11, 0x80, 0xdd, 0x01,
+ 0xe0, 0xdd, 0x20, 0xd0,
+ 0xcc, 0x20, 0xd8, 0x08,
+ 0xc0, 0xca, 0x30, 0xba,
+ 0xdd, 0xc0, 0x20, 0x00,
+ 0xc9, 0x8d, 0xc0, 0x20,
+ 0x00, 0x88, 0x08, 0x92,
+ 0xc9, 0xfc, 0x9a, 0x93,
+ 0xba, 0x88, 0xb2, 0x09,
+ 0x7f, 0xf2, 0x09, 0x80,
+ 0x80, 0xbb, 0x11, 0xb0,
+ 0xff, 0x20, 0xb2, 0x09,
+ 0x7e, 0x92, 0x09, 0x7d,
+ 0x00, 0xbb, 0x11, 0x80,
+ 0x99, 0x01, 0xb0, 0x99,
+ 0x20, 0x90, 0xff, 0x20,
+ 0xc0, 0x20, 0x00, 0xf9,
+ 0x98, 0x1d, 0xf0, 0x00,
+ 0x36, 0xc1, 0x00, 0xa2,
+ 0xc1, 0x8c, 0xd2, 0xc1,
+ 0xac, 0xe1, 0x2d, 0xf2,
+ 0xf2, 0xa2, 0x6e, 0xf0,
+ 0xf3, 0xd1, 0xc2, 0xc1,
+ 0x93, 0xfa, 0xee, 0xb2,
+ 0xde, 0x4a, 0xa7, 0x2c,
+ 0x0e, 0x92, 0x0b, 0xf5,
+ 0x82, 0x0b, 0xba, 0x90,
+ 0x88, 0x30, 0x82, 0x4a,
+ 0x8c, 0x46, 0x01, 0x00,
+ 0xf2, 0x0b, 0xd5, 0xf2,
+ 0x4a, 0x6c, 0x1b, 0xbb,
+ 0x1b, 0xaa, 0xd7, 0x9a,
+ 0xe0, 0xad, 0x01, 0x2c,
+ 0x0b, 0x0c, 0x8d, 0x0c,
+ 0x0f, 0xc2, 0xde, 0x4b,
+ 0xc2, 0xcc, 0xd5, 0xe2,
+ 0xc1, 0x20, 0xa5, 0xd4,
+ 0xfd, 0xbd, 0x02, 0xa2,
+ 0xc1, 0x20, 0x2c, 0x0c,
+ 0xe5, 0xaa, 0x05, 0x0c,
+ 0x08, 0x0c, 0x12, 0xa0,
+ 0x28, 0x93, 0x1d, 0xf0,
+ 0x36, 0x41, 0x00, 0xa1,
+ 0x63, 0xf2, 0x92, 0xa2,
+ 0x6e, 0x90, 0x93, 0xd1,
+ 0x82, 0xca, 0xcb, 0x8a,
+ 0x89, 0x82, 0x08, 0x7d,
+ 0xaa, 0x39, 0xcc, 0x58,
+ 0xad, 0x03, 0x0c, 0x8b,
+ 0xa5, 0x54, 0x00, 0xbd,
+ 0x03, 0xad, 0x02, 0x0c,
+ 0x8c, 0xa5, 0xae, 0x05,
+ 0x1d, 0xf0, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0xbd,
+ 0x02, 0xa2, 0xc4, 0x25,
+ 0x1c, 0x0c, 0xa5, 0xad,
+ 0x05, 0x5b, 0xa4, 0x21,
+ 0x09, 0xf2, 0x82, 0xa2,
+ 0x6e, 0x80, 0x83, 0xd1,
+ 0x0c, 0x8c, 0x8a, 0x22,
+ 0xb2, 0xd2, 0x4b, 0xb2,
+ 0xcb, 0x15, 0x25, 0xac,
+ 0x05, 0xdb, 0xa4, 0x0c,
+ 0x8c, 0xb2, 0xd2, 0x4b,
+ 0xb2, 0xcb, 0xba, 0x65,
+ 0xab, 0x05, 0xa2, 0xc4,
+ 0x15, 0x1c, 0x0c, 0xb2,
+ 0xd2, 0x4b, 0xb2, 0xcb,
+ 0xc5, 0x65, 0xaa, 0x05,
+ 0xad, 0x04, 0x0c, 0x5c,
+ 0xb2, 0xd2, 0x49, 0xb2,
+ 0xcb, 0xb0, 0xa5, 0xa9,
+ 0x05, 0x1d, 0xf0, 0x00,
+ 0x36, 0x21, 0x01, 0x81,
+ 0xf8, 0xf1, 0x52, 0xa2,
+ 0x6e, 0x50, 0x53, 0xd1,
+ 0x8a, 0x35, 0xa2, 0xd3,
+ 0x4b, 0xa2, 0xca, 0xc5,
+ 0x65, 0xde, 0xfd, 0xbd,
+ 0x01, 0xe2, 0xc1, 0x10,
+ 0x7b, 0xd1, 0xa2, 0xd3,
+ 0x4b, 0xa2, 0xca, 0x98,
+ 0xb7, 0xad, 0x05, 0xc2,
+ 0x0a, 0x1a, 0x86, 0x00,
+ 0x00, 0xc2, 0x0a, 0x7d,
+ 0x1b, 0xaa, 0xc2, 0x4b,
+ 0x00, 0x1b, 0xbb, 0xe7,
+ 0x9b, 0xe9, 0xad, 0x01,
+ 0x42, 0xd3, 0x4b, 0x42,
+ 0xc4, 0xdd, 0xbd, 0x04,
+ 0xe5, 0xc9, 0xfd, 0xad,
+ 0x01, 0x0c, 0x19, 0x81,
+ 0x33, 0xf2, 0xb2, 0xd3,
+ 0x4b, 0x8a, 0x85, 0x82,
+ 0x08, 0x7d, 0xb2, 0xcb,
+ 0xed, 0x90, 0x88, 0x30,
+ 0x82, 0x41, 0x0f, 0x65,
+ 0xc8, 0xfd, 0xa2, 0xc1,
+ 0x10, 0x0c, 0x8c, 0xb2,
+ 0xd3, 0x4b, 0xb2, 0xcb,
+ 0x15, 0x65, 0xa2, 0x05,
+ 0xa2, 0xc1, 0x18, 0x0c,
+ 0x3c, 0xb2, 0xd3, 0x4b,
+ 0xb2, 0xcb, 0xc2, 0xa5,
+ 0xa1, 0x05, 0xa2, 0xc1,
+ 0x1b, 0xb1, 0x26, 0xf2,
+ 0x0c, 0x3c, 0xe5, 0xa0,
+ 0x05, 0xad, 0x04, 0x2c,
+ 0x0b, 0xc2, 0xc1, 0x10,
+ 0x0c, 0xed, 0xe2, 0xc1,
+ 0x50, 0x0c, 0x0f, 0x25,
+ 0xc2, 0xfd, 0xbd, 0x02,
+ 0xa2, 0xc1, 0x50, 0x2c,
+ 0x0c, 0x65, 0x98, 0x05,
+ 0x0c, 0x09, 0x0c, 0x12,
+ 0xa0, 0x29, 0x93, 0x1d,
+ 0xf0, 0x00, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0x51,
+ 0x1b, 0xf2, 0x0c, 0x06,
+ 0x82, 0x05, 0x00, 0x41,
+ 0x1a, 0xf2, 0x8c, 0xb8,
+ 0xad, 0x04, 0xbd, 0x06,
+ 0xc2, 0xa0, 0xac, 0x25,
+ 0xb0, 0x05, 0x62, 0x45,
+ 0x00, 0x51, 0xf9, 0xf1,
+ 0x0c, 0x1b, 0xa2, 0x05,
+ 0x7f, 0x92, 0x05, 0x80,
+ 0x8c, 0x4a, 0x30, 0x99,
+ 0xc0, 0x56, 0xe9, 0x0a,
+ 0xd1, 0x12, 0xf2, 0x92,
+ 0xa2, 0x6e, 0x90, 0x93,
+ 0xd1, 0xc1, 0xbe, 0xf1,
+ 0xda, 0x79, 0xec, 0x3a,
+ 0x62, 0x45, 0x7e, 0x62,
+ 0x45, 0x81, 0x62, 0x45,
+ 0x82, 0xb2, 0x45, 0x7f,
+ 0x32, 0x45, 0x80, 0xa2,
+ 0xcd, 0xdb, 0xaa, 0xa9,
+ 0xa2, 0x0a, 0x7d, 0xca,
+ 0x39, 0xcc, 0xaa, 0xad,
+ 0x07, 0x1c, 0x0b, 0xe5,
+ 0x3d, 0x00, 0x46, 0x00,
+ 0x00, 0xca, 0x39, 0xc2,
+ 0x05, 0x7e, 0xfc, 0xcc,
+ 0xad, 0x04, 0xe5, 0xa6,
+ 0xff, 0xad, 0x04, 0x0c,
+ 0x0b, 0xc2, 0xa0, 0xac,
+ 0xe5, 0xa9, 0x05, 0xa1,
+ 0x00, 0xf2, 0xc2, 0xa0,
+ 0x80, 0x0c, 0x3d, 0xe1,
+ 0xff, 0xf1, 0x0c, 0x1f,
+ 0xb2, 0xd3, 0x49, 0xb2,
+ 0xcb, 0xb5, 0xf2, 0x6e,
+ 0x69, 0xd2, 0x6e, 0x6a,
+ 0xa5, 0x9d, 0xff, 0xa1,
+ 0xfb, 0xf1, 0x0c, 0x3c,
+ 0xb2, 0xd3, 0x49, 0xb2,
+ 0xcb, 0x35, 0xe5, 0x9c,
+ 0xff, 0x82, 0xa0, 0x80,
+ 0x89, 0x14, 0xcd, 0x07,
+ 0xad, 0x04, 0x31, 0xd4,
+ 0xf1, 0xb1, 0xf5, 0xf1,
+ 0xdd, 0x03, 0x65, 0x3b,
+ 0xff, 0x8c, 0xca, 0x26,
+ 0x9a, 0x20, 0x62, 0x45,
+ 0x7f, 0xad, 0x04, 0xa5,
+ 0xa1, 0xff, 0x46, 0x04,
+ 0x00, 0xad, 0x02, 0xbd,
+ 0x03, 0xc2, 0xa0, 0x80,
+ 0x25, 0x91, 0x05, 0x62,
+ 0x45, 0x7f, 0xad, 0x04,
+ 0x25, 0xa0, 0xff, 0x0c,
+ 0x12, 0x1d, 0xf0, 0x1c,
+ 0x12, 0x1d, 0xf0, 0x00,
+ 0x36, 0x41, 0x00, 0xad,
+ 0x02, 0xb2, 0xc4, 0x25,
+ 0x1c, 0x0c, 0x65, 0x8f,
+ 0x05, 0xa2, 0xc2, 0x10,
+ 0x5b, 0xb4, 0x1c, 0x0c,
+ 0xa5, 0x8e, 0x05, 0xa1,
+ 0x8e, 0xf1, 0xc2, 0xa2,
+ 0x6e, 0xc0, 0xc3, 0xd1,
+ 0xb2, 0xc4, 0x15, 0xca,
+ 0xaa, 0x1c, 0x0c, 0xa2,
+ 0xda, 0x4b, 0xa2, 0xca,
+ 0xc5, 0x25, 0x8d, 0x05,
+ 0x1d, 0xf0, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0x31,
+ 0xdc, 0xf1, 0x0c, 0x05,
+ 0x82, 0x03, 0x00, 0x41,
+ 0xdb, 0xf1, 0x8c, 0xb8,
+ 0xad, 0x04, 0xbd, 0x05,
+ 0xc2, 0xa0, 0xac, 0xa5,
+ 0x9e, 0x05, 0x52, 0x43,
+ 0x00, 0x31, 0xd7, 0xf1,
+ 0x92, 0x03, 0x27, 0xa2,
+ 0x03, 0x28, 0x16, 0x99,
+ 0x0e, 0x20, 0xaa, 0xc0,
+ 0x56, 0x3a, 0x0d, 0x16,
+ 0x09, 0x0e, 0x92, 0x03,
+ 0x26, 0xb1, 0x79, 0xf1,
+ 0x62, 0xa2, 0x6e, 0x60,
+ 0x22, 0xd1, 0x61, 0xd0,
+ 0xf1, 0x2a, 0x2b, 0x56,
+ 0x39, 0x04, 0xb2, 0xa0,
+ 0x8a, 0xcd, 0x06, 0x0c,
+ 0x0d, 0xa2, 0xd2, 0x49,
+ 0xa2, 0xca, 0xb0, 0xe5,
+ 0x9c, 0xff, 0xad, 0x04,
+ 0xa5, 0x96, 0xff, 0xad,
+ 0x04, 0x0c, 0x0b, 0xc2,
+ 0xa0, 0xac, 0xe5, 0x99,
+ 0x05, 0xa1, 0xc7, 0xf1,
+ 0xb1, 0xc8, 0xf1, 0x81,
+ 0x99, 0xf1, 0xc2, 0xa1,
+ 0x80, 0x52, 0x68, 0x69,
+ 0x52, 0x68, 0x6a, 0x25,
+ 0x8e, 0xff, 0xa1, 0xc4,
+ 0xf1, 0xb1, 0xc4, 0xf1,
+ 0x0c, 0x3c, 0x65, 0x8d,
+ 0xff, 0x92, 0xa1, 0x80,
+ 0x99, 0x14, 0xc0, 0x20,
+ 0x00, 0xa2, 0x23, 0xf1,
+ 0x1b, 0xaa, 0xc0, 0x20,
+ 0x00, 0xa2, 0x63, 0xf1,
+ 0x25, 0xa3, 0x05, 0xbd,
+ 0x06, 0xc0, 0x20, 0x00,
+ 0xa2, 0x63, 0xf2, 0xc2,
+ 0xd2, 0x49, 0xc2, 0xcc,
+ 0x3a, 0xad, 0x04, 0x65,
+ 0x75, 0xff, 0x2d, 0x0a,
+ 0xa5, 0xa1, 0x05, 0xc0,
+ 0x20, 0x00, 0xa2, 0x63,
+ 0xf3, 0xc0, 0x20, 0x00,
+ 0xd2, 0x23, 0xf2, 0xc0,
+ 0x20, 0x00, 0xc2, 0x23,
+ 0xf3, 0xd0, 0xcc, 0xc0,
+ 0xc0, 0x20, 0x00, 0xb2,
+ 0x23, 0xf4, 0xc7, 0xbb,
+ 0x20, 0xc0, 0x20, 0x00,
+ 0x82, 0x23, 0xf2, 0xc0,
+ 0x20, 0x00, 0xf2, 0x23,
+ 0xf3, 0x80, 0xff, 0xc0,
+ 0xc0, 0x20, 0x00, 0xf2,
+ 0x63, 0xf4, 0xc0, 0x20,
+ 0x00, 0xe2, 0x23, 0xf1,
+ 0xc0, 0x20, 0x00, 0xe2,
+ 0x63, 0xf5, 0x9c, 0x12,
+ 0x26, 0x92, 0x0b, 0x52,
+ 0x43, 0x27, 0xad, 0x04,
+ 0x65, 0x8c, 0xff, 0x0c,
+ 0x02, 0x1d, 0xf0, 0x1c,
+ 0x12, 0x1d, 0xf0, 0xad,
+ 0x04, 0x52, 0x43, 0x27,
+ 0x65, 0x8b, 0xff, 0x0c,
+ 0x12, 0x1d, 0xf0, 0x22,
+ 0x43, 0x28, 0x52, 0x43,
+ 0x2a, 0x0c, 0x19, 0x52,
+ 0x43, 0x29, 0x92, 0x43,
+ 0x27, 0x0c, 0x09, 0x92,
+ 0x43, 0x26, 0xc0, 0x20,
+ 0x00, 0x52, 0x63, 0xf1,
+ 0x46, 0xc1, 0xff, 0x00,
+ 0x36, 0x41, 0x00, 0x91,
+ 0x98, 0xf1, 0x4c, 0xca,
+ 0xa0, 0xa2, 0x82, 0xab,
+ 0x84, 0xaa, 0x29, 0x32,
+ 0x42, 0x80, 0x82, 0x52,
+ 0x41, 0x65, 0x98, 0x05,
+ 0x52, 0x42, 0x7e, 0xa2,
+ 0x62, 0x21, 0x0c, 0x49,
+ 0x2c, 0xeb, 0xb2, 0x62,
+ 0x1d, 0x92, 0x42, 0x7f,
+ 0x26, 0x73, 0x1d, 0x26,
+ 0x83, 0x02, 0x66, 0xa3,
+ 0x1f, 0x26, 0x73, 0x14,
+ 0x66, 0x83, 0x02, 0x92,
+ 0x42, 0xbd, 0x3c, 0x0d,
+ 0x66, 0xa3, 0x04, 0x0c,
+ 0x1c, 0xc2, 0x42, 0xbd,
+ 0xd2, 0x62, 0x1d, 0x1d,
+ 0xf0, 0x0c, 0x2e, 0xe2,
+ 0x42, 0xbd, 0x86, 0xf8,
+ 0xff, 0xb2, 0xa3, 0xe8,
+ 0xb0, 0xa4, 0xc1, 0xa5,
+ 0x4a, 0x02, 0x1d, 0xf0,
+ 0x36, 0x41, 0x00, 0xa1,
+ 0x82, 0xf1, 0x92, 0xa2,
+ 0x6e, 0x90, 0x93, 0xd1,
+ 0x82, 0xca, 0x8b, 0x8a,
+ 0x89, 0x82, 0x08, 0x7d,
+ 0xaa, 0x39, 0xcc, 0x58,
+ 0xad, 0x03, 0x0c, 0x8b,
+ 0xa5, 0x17, 0x00, 0xbd,
+ 0x03, 0xad, 0x02, 0x0c,
+ 0x8c, 0xa5, 0x71, 0x05,
+ 0x8b, 0xa2, 0xb1, 0x67,
+ 0xf1, 0x0c, 0x3c, 0x25,
+ 0x71, 0x05, 0x1d, 0xf0,
+ 0x36, 0x41, 0x00, 0xc0,
+ 0x20, 0x00, 0x39, 0x02,
+ 0x1d, 0xf0, 0x00, 0x00,
+ 0x36, 0x61, 0x00, 0xa1,
+ 0x73, 0xf1, 0xb1, 0x73,
+ 0xf1, 0xe5, 0x08, 0x00,
+ 0x22, 0xc3, 0x40, 0xa2,
+ 0x03, 0x01, 0x92, 0x03,
+ 0x02, 0x82, 0x03, 0x03,
+ 0x80, 0x99, 0x11, 0x90,
+ 0x88, 0x20, 0x92, 0x03,
+ 0x00, 0x00, 0xaa, 0x11,
+ 0x80, 0x99, 0x01, 0xa0,
+ 0x99, 0x20, 0x90, 0x88,
+ 0x20, 0xc0, 0x20, 0x00,
+ 0x89, 0x01, 0xa1, 0x69,
+ 0xf1, 0xc0, 0x20, 0x00,
+ 0xb8, 0x01, 0xe5, 0x05,
+ 0x00, 0x4b, 0x33, 0x27,
+ 0x93, 0xcc, 0xa1, 0x66,
+ 0xf1, 0xe5, 0x05, 0x00,
+ 0xa1, 0x65, 0xf1, 0xa5,
+ 0x05, 0x00, 0xa1, 0x63,
+ 0xf1, 0x25, 0x05, 0x00,
+ 0xa1, 0x62, 0xf1, 0xe5,
+ 0x04, 0x00, 0xa1, 0x60,
+ 0xf1, 0x65, 0x04, 0x00,
+ 0xa1, 0x5f, 0xf1, 0x25,
+ 0x04, 0x00, 0xa1, 0x5d,
+ 0xf1, 0xa5, 0x03, 0x00,
+ 0xa1, 0x5c, 0xf1, 0x65,
+ 0x03, 0x00, 0xa1, 0x5a,
+ 0xf1, 0xe5, 0x02, 0x00,
+ 0xa1, 0x59, 0xf1, 0xa5,
+ 0x02, 0x00, 0xa1, 0x57,
+ 0xf1, 0x25, 0x02, 0x00,
+ 0x21, 0x57, 0xf1, 0x17,
+ 0xfa, 0x08, 0xa1, 0x54,
+ 0xf1, 0x65, 0x01, 0x00,
+ 0x27, 0x0a, 0xf6, 0x1d,
+ 0xf0, 0x00, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0xc0,
+ 0x20, 0x00, 0x39, 0x02,
+ 0x1d, 0xf0, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0xc0,
+ 0x20, 0x00, 0x28, 0x02,
+ 0x1d, 0xf0, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0x16,
+ 0x34, 0x06, 0x88, 0x02,
+ 0x98, 0x12, 0x80, 0x50,
+ 0x54, 0x4a, 0x88, 0x89,
+ 0x02, 0x47, 0xb8, 0x03,
+ 0x1b, 0x99, 0x99, 0x12,
+ 0xac, 0x35, 0x4c, 0x0c,
+ 0x50, 0xcc, 0xc0, 0xc7,
+ 0x34, 0x1c, 0xbd, 0x03,
+ 0x5a, 0xa2, 0x8b, 0xaa,
+ 0x65, 0x62, 0x05, 0xad,
+ 0x02, 0x8b, 0xb2, 0x25,
+ 0xf2, 0xff, 0x5a, 0x44,
+ 0x50, 0x33, 0xc0, 0x32,
+ 0xc3, 0x40, 0x42, 0xc4,
+ 0xc0, 0x0c, 0x05, 0x6d,
+ 0x04, 0xb6, 0xd4, 0x18,
+ 0x40, 0x76, 0x41, 0xad,
+ 0x02, 0xbd, 0x03, 0x65,
+ 0xf0, 0xff, 0x32, 0xc3,
+ 0x40, 0x42, 0xc4, 0xc0,
+ 0xf6, 0xd4, 0xef, 0xa0,
+ 0x47, 0x11, 0x40, 0x46,
+ 0xc0, 0x8c, 0x94, 0xcd,
+ 0x04, 0xbd, 0x03, 0x5a,
+ 0xa2, 0x8b, 0xaa, 0xa5,
+ 0x5e, 0x05, 0x1d, 0xf0,
+ 0x36, 0x41, 0x00, 0xc0,
+ 0x20, 0x00, 0x28, 0x02,
+ 0x1d, 0xf0, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0xc0,
+ 0x20, 0x00, 0x39, 0x02,
+ 0x1d, 0xf0, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0x30,
+ 0x51, 0x41, 0x9c, 0x55,
+ 0x3a, 0x32, 0x2a, 0x65,
+ 0x0b, 0x33, 0x42, 0x02,
+ 0x00, 0x52, 0x03, 0x00,
+ 0x52, 0x42, 0x00, 0x1b,
+ 0x22, 0x42, 0x43, 0x00,
+ 0x67, 0x92, 0xec, 0x1d,
+ 0xf0, 0x00, 0x00, 0x00,
+ 0x36, 0xe1, 0x00, 0x22,
+ 0x61, 0x10, 0x16, 0x53,
+ 0x0a, 0x42, 0xc1, 0x10,
+ 0x0c, 0x05, 0x71, 0x1f,
+ 0xf1, 0x21, 0x1f, 0xf1,
+ 0x62, 0xc7, 0xf0, 0xad,
+ 0x07, 0x65, 0x8f, 0xfd,
+ 0xb1, 0x1e, 0xf1, 0xc2,
+ 0x2b, 0x7f, 0xd2, 0x2b,
+ 0x7e, 0xd9, 0x41, 0x1b,
+ 0xad, 0xa2, 0x6b, 0x7e,
+ 0xa9, 0x61, 0xd0, 0xaa,
+ 0x62, 0xca, 0xaa, 0xa9,
+ 0x51, 0xa2, 0x6b, 0x7f,
+ 0xa9, 0x71, 0xbd, 0x01,
+ 0xa2, 0xc1, 0x10, 0xa5,
+ 0x7b, 0xfd, 0xcd, 0x02,
+ 0xbd, 0x01, 0xa2, 0xc1,
+ 0x20, 0xf2, 0x2c, 0x7f,
+ 0xe8, 0x0b, 0x4b, 0xcc,
+ 0x4b, 0xbb, 0xf0, 0xee,
+ 0x30, 0xe9, 0x0a, 0x4b,
+ 0xaa, 0x47, 0x9b, 0xec,
+ 0xa2, 0xc1, 0x20, 0xb2,
+ 0xc1, 0x30, 0x65, 0x79,
+ 0xfd, 0xbd, 0x01, 0xa2,
+ 0xc1, 0x20, 0xc2, 0xc1,
+ 0x30, 0x98, 0x0c, 0x88,
+ 0x0b, 0x4b, 0xcc, 0x4b,
+ 0xbb, 0x90, 0x88, 0x30,
+ 0x89, 0x0a, 0x4b, 0xaa,
+ 0x47, 0x9b, 0xed, 0xbd,
+ 0x06, 0xa2, 0xc1, 0x20,
+ 0x25, 0x77, 0xfd, 0xc2,
+ 0xc5, 0x10, 0xc7, 0xa5,
+ 0x19, 0xa2, 0x21, 0x10,
+ 0xb2, 0xc1, 0x30, 0xaa,
+ 0xa5, 0x37, 0xa5, 0x0e,
+ 0x1b, 0x55, 0xd2, 0x0b,
+ 0x00, 0xd2, 0x4a, 0x00,
+ 0x1b, 0xbb, 0x1b, 0xaa,
+ 0x57, 0x9c, 0xed, 0x5d,
+ 0x0c, 0x37, 0xac, 0x02,
+ 0xc6, 0xd9, 0xff, 0x1d,
+ 0xf0, 0x00, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0xad,
+ 0x03, 0x1c, 0x4b, 0x25,
+ 0xf2, 0xff, 0xad, 0x03,
+ 0x20, 0xc2, 0x90, 0xb1,
+ 0x8d, 0xf0, 0xc0, 0xcc,
+ 0x11, 0xca, 0xbb, 0x1c,
+ 0x4c, 0xb2, 0xdb, 0x46,
+ 0xb2, 0xcb, 0xd2, 0xa5,
+ 0x46, 0x05, 0x0c, 0x1d,
+ 0x0c, 0x02, 0xa0, 0x2d,
+ 0x83, 0x1d, 0xf0, 0x00,
+ 0x36, 0x21, 0x01, 0x50,
+ 0xb8, 0x41, 0x20, 0xc2,
+ 0x90, 0x40, 0x64, 0xa0,
+ 0x60, 0x60, 0x74, 0xc0,
+ 0x4c, 0x11, 0x3a, 0xa6,
+ 0x0c, 0x8c, 0xb2, 0x4a,
+ 0x01, 0x52, 0x4a, 0x00,
+ 0xb1, 0xe7, 0xf0, 0x2b,
+ 0xaa, 0xba, 0xb4, 0x65,
+ 0x4a, 0x05, 0xbd, 0x03,
+ 0xab, 0xc6, 0xad, 0x01,
+ 0x0c, 0x08, 0x89, 0x01,
+ 0x89, 0x11, 0x65, 0xe4,
+ 0xff, 0x3c, 0x7c, 0x10,
+ 0x4d, 0x40, 0x98, 0x01,
+ 0xf8, 0x11, 0x90, 0xb0,
+ 0x54, 0xd0, 0x89, 0x11,
+ 0x90, 0xd5, 0x75, 0x90,
+ 0xad, 0xf4, 0xa2, 0x41,
+ 0x4d, 0xd2, 0x41, 0x4c,
+ 0x82, 0x41, 0x4f, 0x90,
+ 0xff, 0x81, 0x80, 0x88,
+ 0x41, 0x82, 0x41, 0x4e,
+ 0xf2, 0x41, 0x4b, 0xf0,
+ 0xd8, 0x41, 0xf0, 0xe0,
+ 0xf5, 0xe2, 0x41, 0x49,
+ 0xd2, 0x41, 0x4a, 0xf0,
+ 0xf8, 0x75, 0xf2, 0x41,
+ 0x48, 0xb7, 0xbc, 0x02,
+ 0x46, 0x29, 0x00, 0x3c,
+ 0x8a, 0xb0, 0xca, 0xc0,
+ 0xad, 0x01, 0xb1, 0xcf,
+ 0xf0, 0x65, 0xdf, 0xff,
+ 0xad, 0x01, 0xb2, 0xc1,
+ 0x48, 0x0c, 0x8c, 0xe5,
+ 0xde, 0xff, 0x0c, 0x02,
+ 0x51, 0xcc, 0xf0, 0x62,
+ 0xc1, 0x50, 0xe0, 0x32,
+ 0x11, 0x50, 0xa2, 0xa0,
+ 0xe5, 0xdc, 0xff, 0xa0,
+ 0x98, 0x41, 0xa0, 0xb0,
+ 0xf5, 0xa0, 0xc8, 0x75,
+ 0x1b, 0x22, 0x6a, 0x83,
+ 0xa2, 0x48, 0x03, 0x20,
+ 0x20, 0x74, 0xc2, 0x48,
+ 0x00, 0xb2, 0x48, 0x01,
+ 0x92, 0x48, 0x02, 0x66,
+ 0x52, 0xd7, 0xa1, 0xc1,
+ 0xf0, 0x0c, 0x8b, 0xe5,
+ 0xd9, 0xff, 0xa1, 0xbf,
+ 0xf0, 0x0c, 0x0b, 0x65,
+ 0xd9, 0xff, 0xad, 0x01,
+ 0x0c, 0x0b, 0x4c, 0x8c,
+ 0x65, 0x52, 0x05, 0xd2,
+ 0x21, 0x14, 0xf2, 0x21,
+ 0x15, 0x82, 0x21, 0x16,
+ 0x92, 0x21, 0x17, 0xe1,
+ 0xb9, 0xf0, 0xa2, 0x21,
+ 0x18, 0xea, 0xe4, 0xa2,
+ 0x5e, 0xff, 0xa0, 0xa0,
+ 0xf5, 0xe2, 0xde, 0x02,
+ 0x92, 0x5e, 0x01, 0x82,
+ 0x5e, 0x03, 0xf2, 0x5e,
+ 0x05, 0xd2, 0x5e, 0x07,
+ 0xa2, 0x5e, 0x00, 0xd0,
+ 0xd0, 0xf5, 0xf0, 0xf0,
+ 0xf5, 0x80, 0x80, 0xf5,
+ 0x90, 0x90, 0xf5, 0x92,
+ 0x5e, 0x02, 0x82, 0x5e,
+ 0x04, 0xf2, 0x5e, 0x06,
+ 0xd2, 0x5e, 0x08, 0x1d,
+ 0xf0, 0xa2, 0xa0, 0x78,
+ 0x46, 0xd5, 0xff, 0x00,
+ 0x36, 0x41, 0x00, 0x41,
+ 0x86, 0xf0, 0x0c, 0x13,
+ 0x20, 0x50, 0x74, 0x90,
+ 0x55, 0x11, 0xc0, 0x20,
+ 0x00, 0x68, 0x04, 0x5a,
+ 0x66, 0xc0, 0x20, 0x00,
+ 0x32, 0x66, 0x13, 0xc0,
+ 0x20, 0x00, 0x48, 0x04,
+ 0x5a, 0x44, 0xc0, 0x20,
+ 0x00, 0x32, 0x64, 0x11,
+ 0x1d, 0xf0, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0xad,
+ 0x03, 0x20, 0xc2, 0x90,
+ 0xb1, 0x30, 0xf0, 0xc0,
+ 0xcc, 0x11, 0xca, 0xbb,
+ 0x0c, 0x5c, 0xb2, 0xdb,
+ 0x46, 0xb2, 0xcb, 0xc8,
+ 0xe5, 0x35, 0x05, 0xad,
+ 0x03, 0x0c, 0x5b, 0xe5,
+ 0xd8, 0xff, 0x1d, 0xf0,
+ 0x36, 0x61, 0x00, 0x31,
+ 0x96, 0xf0, 0xb1, 0x96,
+ 0xf0, 0x6d, 0x02, 0x51,
+ 0x93, 0xf0, 0x81, 0x6c,
+ 0xf0, 0x20, 0x72, 0x90,
+ 0xc0, 0x77, 0x11, 0x82,
+ 0x08, 0x80, 0x5a, 0x57,
+ 0x92, 0x25, 0x1d, 0x22,
+ 0x05, 0x7d, 0x99, 0x01,
+ 0x92, 0x25, 0x1c, 0x99,
+ 0x11, 0x9c, 0x08, 0xa1,
+ 0x67, 0xf0, 0xcd, 0x03,
+ 0xd2, 0xa1, 0x18, 0x0c,
+ 0x0e, 0xe5, 0x86, 0x00,
+ 0x4d, 0x03, 0x46, 0x00,
+ 0x00, 0x4d, 0x0b, 0xa1,
+ 0x89, 0xf0, 0x0c, 0x0b,
+ 0x65, 0xd3, 0xff, 0xa1,
+ 0x82, 0xf0, 0x0c, 0x8b,
+ 0xe5, 0xd2, 0xff, 0xa1,
+ 0x80, 0xf0, 0x0c, 0x0b,
+ 0x65, 0xd2, 0xff, 0xc1,
+ 0x84, 0xf0, 0xa1, 0x84,
+ 0xf0, 0xca, 0xc7, 0xb2,
+ 0x0c, 0x80, 0xd2, 0x0c,
+ 0x7e, 0xe2, 0x0c, 0x7f,
+ 0x00, 0xdd, 0x11, 0x80,
+ 0xee, 0x11, 0xc2, 0x0c,
+ 0x7d, 0xe0, 0xbb, 0x20,
+ 0x80, 0xcc, 0x01, 0xd0,
+ 0xcc, 0x20, 0xc0, 0xbb,
+ 0x20, 0xe5, 0xcf, 0xff,
+ 0xb1, 0x7c, 0xf0, 0xa1,
+ 0x7c, 0xf0, 0xba, 0xb7,
+ 0xb2, 0x0b, 0x80, 0x25,
+ 0xcf, 0xff, 0xa1, 0x75,
+ 0xf0, 0x0c, 0x2b, 0xa5,
+ 0xce, 0xff, 0xc1, 0x78,
+ 0xf0, 0xa1, 0x78, 0xf0,
+ 0xb2, 0x0c, 0x80, 0xd2,
+ 0x0c, 0x7e, 0xe2, 0x0c,
+ 0x7f, 0x00, 0xdd, 0x11,
+ 0x80, 0xee, 0x11, 0xc2,
+ 0x0c, 0x7d, 0xe0, 0xbb,
+ 0x20, 0x80, 0xcc, 0x01,
+ 0xd0, 0xcc, 0x20, 0xc0,
+ 0xbb, 0x20, 0x25, 0xcc,
+ 0xff, 0xb1, 0x70, 0xf0,
+ 0xa1, 0x71, 0xf0, 0xb2,
+ 0x0b, 0x80, 0x65, 0xcb,
+ 0xff, 0xa1, 0x66, 0xf0,
+ 0x0c, 0x3b, 0x59, 0x21,
+ 0xa5, 0xca, 0xff, 0x0c,
+ 0x03, 0x2c, 0x85, 0x69,
+ 0x31, 0xa1, 0x68, 0xf0,
+ 0x30, 0x83, 0xf0, 0x8a,
+ 0x84, 0x62, 0x08, 0x02,
+ 0xb2, 0x08, 0x06, 0xd2,
+ 0x08, 0x04, 0x92, 0x08,
+ 0x01, 0xc2, 0x08, 0x05,
+ 0x80, 0x99, 0x11, 0x80,
+ 0xcc, 0x11, 0x00, 0xdd,
+ 0x11, 0xc0, 0xbb, 0x20,
+ 0xc2, 0x08, 0x03, 0x82,
+ 0x08, 0x00, 0x80, 0xcc,
+ 0x01, 0xd0, 0xcc, 0x20,
+ 0xc0, 0xbb, 0x20, 0x00,
+ 0x88, 0x11, 0x90, 0x88,
+ 0x20, 0x80, 0x66, 0x20,
+ 0x65, 0xc6, 0xff, 0xbd,
+ 0x06, 0xa1, 0x5a, 0xf0,
+ 0xe5, 0xc5, 0xff, 0x1b,
+ 0x33, 0x30, 0x30, 0x74,
+ 0x57, 0x93, 0xb1, 0x81,
+ 0x26, 0xf0, 0x82, 0x08,
+ 0x80, 0x8c, 0x98, 0xa1,
+ 0x4b, 0xf0, 0x0c, 0x0b,
+ 0xc2, 0xa1, 0x18, 0x25,
+ 0x35, 0x05, 0xa1, 0x3d,
+ 0xf0, 0x25, 0xc3, 0xff,
+ 0x07, 0xea, 0x08, 0xa1,
+ 0x3b, 0xf0, 0xa5, 0xc2,
+ 0xff, 0x07, 0x6a, 0xf6,
+ 0x38, 0x01, 0xb8, 0x11,
+ 0xa1, 0x4e, 0xf0, 0x6d,
+ 0x0b, 0x65, 0xc2, 0xff,
+ 0xbd, 0x03, 0x5d, 0x03,
+ 0xa1, 0x4c, 0xf0, 0xe5,
+ 0xc1, 0xff, 0x2c, 0x04,
+ 0xb0, 0x32, 0x11, 0xa1,
+ 0x3f, 0xf0, 0x40, 0x33,
+ 0x10, 0x0c, 0x34, 0x40,
+ 0x43, 0x20, 0xbd, 0x04,
+ 0x65, 0xc0, 0xff, 0xa1,
+ 0x3b, 0xf0, 0x0c, 0x7b,
+ 0xb0, 0xb3, 0x20, 0xe5,
+ 0xbf, 0xff, 0xbd, 0x04,
+ 0xa1, 0x38, 0xf0, 0x65,
+ 0xbf, 0xff, 0xa1, 0x29,
+ 0xf0, 0x25, 0xbe, 0xff,
+ 0x0c, 0x44, 0x27, 0xea,
+ 0x08, 0xa1, 0x26, 0xf0,
+ 0x65, 0xbd, 0xff, 0x47,
+ 0x0a, 0xf6, 0xa1, 0x31,
+ 0xf0, 0x4c, 0x3b, 0xb0,
+ 0xb3, 0x20, 0x65, 0xbd,
+ 0xff, 0xa1, 0x39, 0xf0,
+ 0x25, 0xbc, 0xff, 0x41,
+ 0x39, 0xf0, 0x38, 0x31,
+ 0x4a, 0x47, 0xa2, 0x64,
+ 0x7f, 0xa1, 0x37, 0xf0,
+ 0x25, 0xbb, 0xff, 0xa2,
+ 0x64, 0x80, 0x90, 0x33,
+ 0x11, 0x91, 0x01, 0xf0,
+ 0xc0, 0x20, 0x00, 0x98,
+ 0x09, 0x4c, 0x08, 0xa0,
+ 0x42, 0x11, 0x80, 0x44,
+ 0x10, 0x3a, 0x99, 0x2c,
+ 0x28, 0x80, 0x84, 0x20,
+ 0xc0, 0x20, 0x00, 0x89,
+ 0x39, 0xa1, 0x2e, 0xf0,
+ 0xa5, 0xb8, 0xff, 0x2d,
+ 0x0a, 0xa1, 0x2d, 0xf0,
+ 0x25, 0xb8, 0xff, 0x7c,
+ 0xf8, 0x78, 0x21, 0xc0,
+ 0x20, 0x00, 0xb1, 0xf5,
+ 0xef, 0x98, 0x0b, 0x3a,
+ 0x99, 0xc0, 0x20, 0x00,
+ 0x89, 0x49, 0xc0, 0x20,
+ 0x00, 0xf8, 0x0b, 0x3a,
+ 0xff, 0xc0, 0x20, 0x00,
+ 0x89, 0x5f, 0xc0, 0x20,
+ 0x00, 0xe8, 0x0b, 0x3a,
+ 0xee, 0xc0, 0x20, 0x00,
+ 0x89, 0x6e, 0xc0, 0x20,
+ 0x00, 0xd8, 0x0b, 0x3a,
+ 0xdd, 0xc0, 0x20, 0x00,
+ 0x89, 0x7d, 0xc0, 0x20,
+ 0x00, 0xc8, 0x0b, 0x3a,
+ 0xcc, 0xc0, 0x20, 0x00,
+ 0x89, 0x8c, 0xc0, 0x20,
+ 0x00, 0x98, 0x0b, 0x3a,
+ 0x99, 0xc0, 0x20, 0x00,
+ 0x89, 0x99, 0xc0, 0x20,
+ 0x00, 0xf8, 0x0b, 0x3a,
+ 0xff, 0xc0, 0x20, 0x00,
+ 0x29, 0xaf, 0xc0, 0x20,
+ 0x00, 0xe8, 0x0b, 0x3a,
+ 0xee, 0xc0, 0x20, 0x00,
+ 0xa9, 0xbe, 0xc0, 0x20,
+ 0x00, 0xd8, 0x0b, 0x3a,
+ 0xdd, 0xc0, 0x20, 0x00,
+ 0x69, 0xfd, 0xc0, 0x20,
+ 0x00, 0xc8, 0x0b, 0x3a,
+ 0xcc, 0xc0, 0x20, 0x00,
+ 0x52, 0x6c, 0x10, 0xc0,
+ 0x20, 0x00, 0xb8, 0x0b,
+ 0x0c, 0x2a, 0xa0, 0xa4,
+ 0x20, 0x3a, 0xbb, 0xc0,
+ 0x20, 0x00, 0xa9, 0x3b,
+ 0xa1, 0x09, 0xf0, 0xe5,
+ 0xae, 0xff, 0xa2, 0x57,
+ 0x40, 0x1d, 0xf0, 0x00,
+ 0x36, 0x41, 0x00, 0x0c,
+ 0x07, 0x0c, 0x04, 0x61,
+ 0x84, 0xef, 0x20, 0x82,
+ 0x90, 0x0c, 0x02, 0xc0,
+ 0x88, 0x11, 0x8a, 0x66,
+ 0x62, 0xd6, 0x45, 0x1b,
+ 0x77, 0x52, 0x06, 0xc8,
+ 0x1b, 0x66, 0x00, 0x02,
+ 0x40, 0x1b, 0x22, 0x50,
+ 0x90, 0xb1, 0x90, 0x90,
+ 0x04, 0x9a, 0x44, 0x66,
+ 0x82, 0xef, 0x0c, 0x02,
+ 0x66, 0x57, 0xe3, 0xb2,
+ 0xc4, 0xec, 0x0c, 0x0a,
+ 0x0c, 0x12, 0xb0, 0x2a,
+ 0x93, 0x1d, 0xf0, 0x00,
+ 0x36, 0x41, 0x00, 0xbd,
+ 0x03, 0x0c, 0x5c, 0x81,
+ 0x74, 0xef, 0x20, 0x92,
+ 0x90, 0xc0, 0x99, 0x11,
+ 0x9a, 0x88, 0x82, 0xd8,
+ 0x46, 0x22, 0xc8, 0xc8,
+ 0xad, 0x02, 0xe5, 0x06,
+ 0x05, 0xad, 0x02, 0x0c,
+ 0x5b, 0xa5, 0xa9, 0xff,
+ 0x1d, 0xf0, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0xad,
+ 0x03, 0xb1, 0xeb, 0xef,
+ 0x0c, 0x5c, 0x65, 0x05,
+ 0x05, 0xad, 0x03, 0x0c,
+ 0x5b, 0x25, 0xa8, 0xff,
+ 0x1d, 0xf0, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0xb2,
+ 0xa2, 0xbc, 0x0c, 0x0c,
+ 0xd1, 0x64, 0xef, 0x20,
+ 0xa2, 0xf0, 0xd0, 0xaa,
+ 0xa0, 0xc0, 0x20, 0x00,
+ 0xc2, 0x5a, 0x0b, 0x0c,
+ 0x2e, 0xc0, 0x20, 0x00,
+ 0xe2, 0x4a, 0x08, 0xc0,
+ 0x20, 0x00, 0x42, 0x4a,
+ 0x18, 0xc0, 0x20, 0x00,
+ 0xc9, 0x1a, 0xc0, 0x20,
+ 0x00, 0x52, 0x5a, 0x0d,
+ 0xc0, 0x20, 0x00, 0xc9,
+ 0x7a, 0xc0, 0x20, 0x00,
+ 0x69, 0x3a, 0x1b, 0x93,
+ 0xc0, 0x20, 0x00, 0x92,
+ 0x5a, 0x0a, 0xc0, 0x20,
+ 0x00, 0x82, 0x1a, 0x0a,
+ 0x87, 0xbb, 0x08, 0xc0,
+ 0x20, 0x00, 0xc2, 0x1a,
+ 0x0a, 0xc7, 0x3b, 0xf6,
+ 0x49, 0xad, 0x39, 0xbd,
+ 0x69, 0xed, 0xa1, 0xd2,
+ 0xef, 0xb1, 0xd0, 0xef,
+ 0x0c, 0x8e, 0xe2, 0x4d,
+ 0x24, 0xb9, 0xfd, 0x65,
+ 0x8a, 0x03, 0x1d, 0xf0,
+ 0x36, 0x41, 0x00, 0x20,
+ 0x92, 0x90, 0xa1, 0xcd,
+ 0xef, 0xc0, 0x99, 0x11,
+ 0x82, 0xca, 0x90, 0x8a,
+ 0x89, 0x82, 0x08, 0x7e,
+ 0xaa, 0x29, 0xcc, 0x58,
+ 0xad, 0x02, 0x0c, 0x8b,
+ 0x65, 0xa1, 0xff, 0xbd,
+ 0x02, 0xad, 0x03, 0x0c,
+ 0x8c, 0x65, 0xfb, 0x04,
+ 0x1d, 0xf0, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0x31,
+ 0xc4, 0xef, 0x41, 0xc4,
+ 0xef, 0x27, 0xb3, 0x1e,
+ 0x27, 0xb4, 0x4b, 0x81,
+ 0xc3, 0xef, 0x91, 0xc3,
+ 0xef, 0x27, 0xb8, 0x46,
+ 0x27, 0xb9, 0x3f, 0xa1,
+ 0xc2, 0xef, 0xb1, 0xc2,
+ 0xef, 0x27, 0xba, 0x64,
+ 0x27, 0x3b, 0x2f, 0x4c,
+ 0x02, 0x1d, 0xf0, 0xc1,
+ 0xc0, 0xef, 0xd1, 0xc0,
+ 0xef, 0x27, 0xbc, 0x06,
+ 0x27, 0x3d, 0x37, 0x0c,
+ 0x82, 0x1d, 0xf0, 0xe1,
+ 0xbe, 0xef, 0xf1, 0xbe,
+ 0xef, 0x27, 0xbe, 0x0c,
+ 0x27, 0xbf, 0x3d, 0x31,
+ 0xbd, 0xef, 0x37, 0x92,
+ 0x09, 0x0c, 0x52, 0x1d,
+ 0xf0, 0x41, 0xbb, 0xef,
+ 0x47, 0x12, 0xf5, 0x0c,
+ 0x02, 0x1d, 0xf0, 0x0c,
+ 0x12, 0x1d, 0xf0, 0x81,
+ 0xb9, 0xef, 0x91, 0xb9,
+ 0xef, 0x27, 0xb8, 0x16,
+ 0x27, 0x39, 0xeb, 0x0c,
+ 0xf2, 0x1d, 0xf0, 0xa1,
+ 0xb7, 0xef, 0xb1, 0xb7,
+ 0xef, 0x27, 0x3a, 0xe2,
+ 0xb7, 0x92, 0xdb, 0x1c,
+ 0x42, 0x1d, 0xf0, 0xc1,
+ 0xb5, 0xef, 0xc7, 0x92,
+ 0xd1, 0x0c, 0x22, 0x1d,
+ 0xf0, 0xd1, 0xb3, 0xef,
+ 0xd7, 0x92, 0xc7, 0x22,
+ 0xa0, 0x84, 0x1d, 0xf0,
+ 0x36, 0x41, 0x00, 0x81,
+ 0x1a, 0xef, 0x20, 0x42,
+ 0xf0, 0x80, 0x44, 0xa0,
+ 0xc0, 0x20, 0x00, 0x0c,
+ 0x03, 0x28, 0x14, 0xc0,
+ 0x20, 0x00, 0x39, 0x14,
+ 0x1d, 0xf0, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0xc0,
+ 0x20, 0x00, 0x39, 0x02,
+ 0x1d, 0xf0, 0x00, 0x00,
+ 0x36, 0xe1, 0x10, 0x72,
+ 0xc1, 0x40, 0x29, 0x61,
+ 0x91, 0xa7, 0xef, 0x5d,
+ 0x03, 0xe1, 0xa4, 0xef,
+ 0x31, 0x1e, 0xef, 0x59,
+ 0x71, 0x42, 0x2e, 0x7f,
+ 0xf2, 0xc9, 0xd8, 0x56,
+ 0x54, 0x24, 0x0c, 0x1c,
+ 0x0c, 0x05, 0x0c, 0x0b,
+ 0x1c, 0xb8, 0xa2, 0xc7,
+ 0x10, 0x62, 0xd7, 0x04,
+ 0x62, 0xc6, 0x10, 0xdd,
+ 0x0a, 0xc0, 0x47, 0x04,
+ 0xc9, 0x0d, 0x60, 0xec,
+ 0xa0, 0x59, 0x0e, 0x4b,
+ 0xdd, 0xed, 0x0b, 0x1b,
+ 0x55, 0x40, 0xe8, 0x93,
+ 0xf0, 0x4c, 0x11, 0x40,
+ 0xee, 0x30, 0xe0, 0xcc,
+ 0x30, 0xc0, 0xc0, 0x74,
+ 0x66, 0xf5, 0xdd, 0xdd,
+ 0x0f, 0x0c, 0x1c, 0xf0,
+ 0xec, 0x11, 0xc2, 0x6d,
+ 0x7f, 0xc0, 0x47, 0x04,
+ 0x4b, 0xdd, 0xcd, 0x0b,
+ 0x40, 0xc8, 0x93, 0xe0,
+ 0xcc, 0x30, 0xc0, 0xc0,
+ 0x74, 0x97, 0x9d, 0xe6,
+ 0x10, 0x48, 0x40, 0x0c,
+ 0x15, 0x81, 0x8c, 0xef,
+ 0x91, 0x8d, 0xef, 0xc2,
+ 0xd7, 0x04, 0x22, 0xa0,
+ 0x63, 0x22, 0x43, 0x80,
+ 0xc2, 0xcc, 0x14, 0xb2,
+ 0x49, 0x7f, 0x92, 0xc9,
+ 0x9c, 0xd8, 0x0c, 0x1b,
+ 0x88, 0xe0, 0xdd, 0x11,
+ 0xd0, 0xda, 0xc0, 0xd2,
+ 0x2d, 0xff, 0x4b, 0xcc,
+ 0xf0, 0xbd, 0x11, 0xd0,
+ 0x47, 0x21, 0xb0, 0x44,
+ 0x20, 0x40, 0x40, 0x74,
+ 0x40, 0xdd, 0x30, 0xf0,
+ 0xb4, 0x11, 0x40, 0x47,
+ 0x21, 0xb0, 0x44, 0x20,
+ 0x40, 0x40, 0x74, 0xf0,
+ 0xe4, 0x11, 0x40, 0xb7,
+ 0x21, 0xe0, 0xbb, 0x20,
+ 0xb0, 0xb0, 0x74, 0xf0,
+ 0xfb, 0x11, 0xb0, 0xe7,
+ 0x21, 0xb0, 0x44, 0x30,
+ 0x40, 0xdd, 0x30, 0xf0,
+ 0xee, 0x20, 0xe0, 0xe0,
+ 0x74, 0xe0, 0xdd, 0x30,
+ 0x20, 0xdd, 0x30, 0xd2,
+ 0x48, 0x7f, 0x9a, 0xdd,
+ 0x52, 0x4d, 0x80, 0x1b,
+ 0x55, 0x66, 0xf5, 0xa4,
+ 0x81, 0xe8, 0xee, 0xf2,
+ 0xa1, 0x00, 0x21, 0xe5,
+ 0xee, 0x0c, 0x05, 0xdd,
+ 0x02, 0xe2, 0xd2, 0xfc,
+ 0xc2, 0xd2, 0x04, 0xb2,
+ 0xd2, 0x08, 0x42, 0xd2,
+ 0x0c, 0x32, 0xd2, 0x10,
+ 0x39, 0x51, 0x49, 0x41,
+ 0x32, 0xd2, 0x14, 0x22,
+ 0xd2, 0x18, 0x29, 0x81,
+ 0x39, 0x91, 0x42, 0x08,
+ 0x80, 0x1c, 0xb3, 0x40,
+ 0x27, 0x04, 0x20, 0x53,
+ 0x93, 0xf0, 0x24, 0x11,
+ 0x20, 0x55, 0x30, 0x50,
+ 0x30, 0x74, 0x80, 0x24,
+ 0x11, 0x40, 0x55, 0x30,
+ 0x20, 0x33, 0x30, 0x80,
+ 0x55, 0x01, 0x00, 0x44,
+ 0x11, 0x50, 0x44, 0x30,
+ 0x40, 0x33, 0x30, 0x32,
+ 0x6e, 0x7f, 0x52, 0x09,
+ 0x80, 0x30, 0x33, 0x81,
+ 0x32, 0x6d, 0x7f, 0x30,
+ 0x33, 0x81, 0x30, 0x23,
+ 0x81, 0x32, 0x6c, 0x7f,
+ 0x22, 0x6b, 0x7f, 0x28,
+ 0x81, 0x38, 0x91, 0xcc,
+ 0x55, 0x0c, 0x04, 0x49,
+ 0x11, 0x06, 0x09, 0x00,
+ 0x60, 0xa5, 0xa0, 0x42,
+ 0xd7, 0x04, 0x42, 0x24,
+ 0x12, 0xa8, 0x0a, 0x62,
+ 0xd7, 0x04, 0x62, 0xc6,
+ 0x10, 0x4a, 0xaa, 0x42,
+ 0xa0, 0xff, 0x40, 0xaa,
+ 0xf2, 0x42, 0xc7, 0x10,
+ 0x40, 0xaa, 0xa0, 0xa8,
+ 0x0a, 0xa9, 0x11, 0xad,
+ 0x04, 0xcc, 0x55, 0x0c,
+ 0x04, 0x49, 0x21, 0x86,
+ 0x09, 0x00, 0x60, 0xa5,
+ 0xa0, 0x42, 0xd7, 0x04,
+ 0x48, 0xd4, 0xa8, 0x0a,
+ 0x62, 0xd7, 0x04, 0x4a,
+ 0xaa, 0x42, 0xa0, 0xff,
+ 0x40, 0xaa, 0xf2, 0x42,
+ 0xc7, 0x10, 0x40, 0xaa,
+ 0xa0, 0xa8, 0x0a, 0x62,
+ 0xc6, 0x10, 0x80, 0xaa,
+ 0x11, 0xa9, 0x21, 0xad,
+ 0x04, 0xcc, 0x55, 0x0c,
+ 0x04, 0x49, 0x31, 0xc6,
+ 0x09, 0x00, 0x60, 0xa5,
+ 0xa0, 0x42, 0xd7, 0x04,
+ 0x42, 0x24, 0x11, 0xa8,
+ 0x0a, 0x62, 0xd7, 0x04,
+ 0x4a, 0xaa, 0x42, 0xa0,
+ 0xff, 0x40, 0xaa, 0xf2,
+ 0x42, 0xc7, 0x10, 0x40,
+ 0xaa, 0xa0, 0xa8, 0x0a,
+ 0x62, 0xc6, 0x10, 0x00,
+ 0xaa, 0x11, 0xa9, 0x31,
+ 0xad, 0x04, 0x1b, 0x99,
+ 0x1b, 0x88, 0x4b, 0xbb,
+ 0x4b, 0xcc, 0x4b, 0xdd,
+ 0x4b, 0xee, 0x0b, 0xff,
+ 0x10, 0x48, 0x40, 0xa9,
+ 0xc1, 0x69, 0xb1, 0xcc,
+ 0x35, 0x0c, 0x05, 0x46,
+ 0x06, 0x00, 0x60, 0x55,
+ 0xa0, 0x42, 0xd7, 0x04,
+ 0x48, 0xf4, 0x58, 0x05,
+ 0x4a, 0x55, 0x42, 0xa0,
+ 0xff, 0x40, 0x55, 0xf2,
+ 0xa0, 0x55, 0xa0, 0x58,
+ 0x05, 0x80, 0x55, 0x01,
+ 0x68, 0x21, 0xa8, 0x31,
+ 0x48, 0x11, 0x50, 0x5a,
+ 0x30, 0x60, 0x44, 0x30,
+ 0x50, 0x44, 0x30, 0x40,
+ 0x64, 0x81, 0x60, 0xa6,
+ 0x81, 0xa2, 0x63, 0x7f,
+ 0xa0, 0x5a, 0x81, 0x4b,
+ 0x33, 0x52, 0x62, 0x7f,
+ 0x10, 0x48, 0x40, 0x4b,
+ 0x22, 0x58, 0x51, 0xa8,
+ 0x41, 0x62, 0x65, 0x7f,
+ 0x42, 0x6a, 0x7f, 0x68,
+ 0xb1, 0x4b, 0x55, 0x4b,
+ 0xaa, 0xa9, 0x41, 0x59,
+ 0x51, 0xa8, 0xc1, 0x0c,
+ 0x05, 0x56, 0x1f, 0xeb,
+ 0xc1, 0x11, 0xef, 0x0c,
+ 0x1b, 0xb2, 0x6c, 0x7f,
+ 0x31, 0x89, 0xee, 0x58,
+ 0x71, 0x0c, 0x08, 0x28,
+ 0x61, 0x91, 0x0d, 0xef,
+ 0x0c, 0xad, 0xf2, 0xc9,
+ 0xd8, 0xd9, 0x02, 0x8b,
+ 0xa2, 0xa9, 0x12, 0x6d,
+ 0x0a, 0x50, 0x48, 0xa0,
+ 0x1b, 0x88, 0xb2, 0x04,
+ 0x01, 0xe2, 0x04, 0x00,
+ 0x80, 0xbb, 0x11, 0xb0,
+ 0xee, 0x20, 0xb2, 0x04,
+ 0x03, 0x42, 0x04, 0x02,
+ 0x80, 0xbb, 0x01, 0x00,
+ 0x44, 0x11, 0xb0, 0x44,
+ 0x20, 0x40, 0xee, 0x20,
+ 0xe9, 0x0a, 0x4b, 0xaa,
+ 0x66, 0x48, 0xd5, 0x28,
+ 0x02, 0xc2, 0xc2, 0xf6,
+ 0x16, 0xec, 0x0b, 0xd2,
+ 0xc2, 0xf4, 0x16, 0xad,
+ 0x11, 0xe2, 0xc2, 0xf2,
+ 0x56, 0x0e, 0x11, 0x0c,
+ 0x75, 0x2d, 0x0f, 0x0b,
+ 0x55, 0xb8, 0x36, 0xc8,
+ 0x26, 0xd8, 0x16, 0x88,
+ 0x06, 0x92, 0x22, 0x7f,
+ 0xf8, 0x76, 0x4b, 0x22,
+ 0xf0, 0xe8, 0x74, 0xf0,
+ 0x40, 0x75, 0x90, 0x88,
+ 0x30, 0x4a, 0x43, 0xea,
+ 0xe3, 0xe2, 0x0e, 0x80,
+ 0x42, 0x04, 0x80, 0xf0,
+ 0x98, 0x75, 0x9a, 0x93,
+ 0x92, 0x09, 0x80, 0x80,
+ 0x44, 0x11, 0x40, 0xee,
+ 0x30, 0x00, 0x99, 0x11,
+ 0x80, 0xee, 0x30, 0xf0,
+ 0x40, 0x74, 0x4a, 0x43,
+ 0x42, 0x04, 0x80, 0x88,
+ 0x56, 0x80, 0x44, 0x01,
+ 0x90, 0x44, 0x30, 0x40,
+ 0xee, 0x30, 0xe9, 0x86,
+ 0x48, 0x66, 0xe0, 0xdd,
+ 0x30, 0xd9, 0x96, 0xd0,
+ 0xcc, 0x30, 0xc9, 0xa6,
+ 0xc0, 0xbb, 0x30, 0xb9,
+ 0xb6, 0xb0, 0x90, 0x74,
+ 0xb0, 0xa0, 0x75, 0xb0,
+ 0xc8, 0x75, 0xaa, 0xa3,
+ 0x9a, 0x93, 0x92, 0x09,
+ 0x80, 0xa2, 0x0a, 0x80,
+ 0xca, 0xc3, 0xc2, 0x0c,
+ 0x80, 0x00, 0xaa, 0x11,
+ 0xb0, 0xb8, 0x74, 0xba,
+ 0xb3, 0x80, 0xcc, 0x01,
+ 0xc0, 0xaa, 0x30, 0xb2,
+ 0x0b, 0x80, 0xc8, 0x46,
+ 0x80, 0xbb, 0x11, 0xc0,
+ 0x99, 0x30, 0xb0, 0x99,
+ 0x30, 0xa0, 0x99, 0x30,
+ 0x99, 0xc6, 0x90, 0x88,
+ 0x30, 0x89, 0xd6, 0x80,
+ 0x44, 0x30, 0x49, 0xe6,
+ 0x40, 0xff, 0x30, 0xf9,
+ 0xf6, 0x62, 0xc6, 0x20,
+ 0x56, 0x35, 0xf5, 0x46,
+ 0x17, 0x00, 0x2d, 0x0f,
+ 0xb8, 0x26, 0xc8, 0x16,
+ 0xf8, 0x06, 0x42, 0x22,
+ 0x7f, 0xa8, 0x36, 0x4b,
+ 0x22, 0xa0, 0xd8, 0x74,
+ 0xa0, 0xe0, 0x75, 0x40,
+ 0xff, 0x30, 0xea, 0xe3,
+ 0xda, 0xd3, 0xd2, 0x0d,
+ 0x80, 0xe2, 0x0e, 0x80,
+ 0xa0, 0x48, 0x75, 0x4a,
+ 0x43, 0x42, 0x04, 0x80,
+ 0x80, 0xee, 0x11, 0xe0,
+ 0xdd, 0x30, 0xf0, 0xdd,
+ 0x30, 0xa0, 0xe0, 0x74,
+ 0xea, 0xe3, 0xe2, 0x0e,
+ 0x80, 0x00, 0x44, 0x11,
+ 0x80, 0xee, 0x01, 0x40,
+ 0xee, 0x30, 0xe0, 0xdd,
+ 0x30, 0xd9, 0x46, 0xd0,
+ 0xcc, 0x30, 0xc9, 0x56,
+ 0xc0, 0xbb, 0x30, 0xb9,
+ 0x66, 0xb0, 0xaa, 0x30,
+ 0xa9, 0x76, 0x62, 0xc6,
+ 0x10, 0x97, 0x92, 0xa3,
+ 0x0c, 0x02, 0x1d, 0xf0,
+ 0x2d, 0x0f, 0xb1, 0xb7,
+ 0xee, 0x88, 0x46, 0x98,
+ 0x36, 0xa8, 0x26, 0xc8,
+ 0x16, 0xf8, 0x06, 0x42,
+ 0x22, 0x7f, 0x58, 0x56,
+ 0x4b, 0x22, 0x50, 0xd8,
+ 0x74, 0x50, 0xe0, 0x75,
+ 0x40, 0xff, 0x30, 0xea,
+ 0xe3, 0xda, 0xd3, 0xd2,
+ 0x0d, 0x80, 0xe2, 0x0e,
+ 0x80, 0x50, 0x48, 0x75,
+ 0x4a, 0x43, 0x42, 0x04,
+ 0x80, 0x80, 0xee, 0x11,
+ 0xe0, 0xdd, 0x30, 0xf0,
+ 0xdd, 0x30, 0x50, 0xe0,
+ 0x74, 0xea, 0xe3, 0xe2,
+ 0x0e, 0x80, 0x00, 0x44,
+ 0x11, 0x80, 0xee, 0x01,
+ 0x40, 0xee, 0x30, 0xe0,
+ 0xdd, 0x30, 0xd9, 0x66,
+ 0xd0, 0xcc, 0x30, 0xc9,
+ 0x76, 0xc0, 0xaa, 0x30,
+ 0xa9, 0x86, 0xa0, 0x99,
+ 0x30, 0x99, 0x96, 0x90,
+ 0x88, 0x30, 0x89, 0xa6,
+ 0x80, 0x55, 0x30, 0x59,
+ 0xb6, 0x62, 0xc6, 0x18,
+ 0xb7, 0x92, 0x95, 0x46,
+ 0xe2, 0xff, 0x00, 0x00,
+ 0x36, 0x81, 0x00, 0xad,
+ 0x05, 0x9d, 0x03, 0x3d,
+ 0x04, 0x16, 0xf9, 0x06,
+ 0x16, 0xc4, 0x06, 0xb6,
+ 0xb5, 0x69, 0x99, 0x41,
+ 0x50, 0x84, 0x41, 0x89,
+ 0x51, 0xa6, 0x18, 0x20,
+ 0xa9, 0x61, 0x7d, 0x04,
+ 0xc0, 0x88, 0x11, 0x4d,
+ 0x09, 0x8a, 0x59, 0xad,
+ 0x02, 0xbd, 0x06, 0xcd,
+ 0x04, 0xdd, 0x07, 0xa5,
+ 0x40, 0xfc, 0x72, 0xc7,
+ 0x10, 0x42, 0xc4, 0x10,
+ 0x57, 0x94, 0xeb, 0xa8,
+ 0x61, 0xa0, 0x40, 0x34,
+ 0xbc, 0x44, 0x58, 0x51,
+ 0xcd, 0x04, 0xc0, 0x55,
+ 0x11, 0x3a, 0xa5, 0x72,
+ 0xca, 0xf0, 0xbd, 0x07,
+ 0xe5, 0xa5, 0x04, 0xad,
+ 0x01, 0xb8, 0x41, 0xcd,
+ 0x04, 0xba, 0xb5, 0x65,
+ 0xa5, 0x04, 0x1a, 0xa4,
+ 0x1c, 0x0c, 0x40, 0xb5,
+ 0xc0, 0xba, 0xb3, 0x40,
+ 0xcc, 0xc0, 0x65, 0xa4,
+ 0x04, 0xad, 0x02, 0xbd,
+ 0x06, 0xcd, 0x01, 0xdd,
+ 0x07, 0x25, 0x3c, 0xfc,
+ 0x0c, 0x02, 0x1d, 0xf0,
+ 0x7c, 0xf2, 0x1d, 0xf0,
+ 0x36, 0x81, 0x02, 0x31,
+ 0x26, 0xee, 0x82, 0x03,
+ 0x80, 0x8c, 0x28, 0x7c,
+ 0xf2, 0x1d, 0xf0, 0xa1,
+ 0x78, 0xee, 0xbd, 0x02,
+ 0x65, 0xb2, 0xff, 0xbd,
+ 0x02, 0x91, 0x76, 0xee,
+ 0x0c, 0xaa, 0xa2, 0x63,
+ 0x67, 0x92, 0x63, 0x68,
+ 0xad, 0x01, 0x65, 0xb1,
+ 0xff, 0x56, 0xea, 0x0a,
+ 0xc1, 0x73, 0xee, 0xb8,
+ 0x01, 0xa8, 0x11, 0xc0,
+ 0xbb, 0x11, 0xba, 0xaa,
+ 0xf8, 0x0a, 0xf2, 0x6c,
+ 0x7f, 0xe8, 0x1a, 0xe2,
+ 0x6c, 0x80, 0xd8, 0x2a,
+ 0xd2, 0x6c, 0x81, 0xb8,
+ 0x3a, 0xb2, 0x6c, 0x82,
+ 0xa2, 0xca, 0xf0, 0xc2,
+ 0x23, 0x67, 0xb1, 0x6a,
+ 0xee, 0x0b, 0x6c, 0xa6,
+ 0x2c, 0x66, 0x41, 0x69,
+ 0xee, 0x51, 0xd9, 0xed,
+ 0x32, 0xd4, 0xfc, 0x22,
+ 0xd4, 0xf8, 0xf2, 0xd4,
+ 0xf4, 0x0c, 0x09, 0x0b,
+ 0x66, 0x1b, 0x99, 0xd8,
+ 0x0a, 0x4b, 0xaa, 0xd0,
+ 0x80, 0x74, 0xd0, 0xe0,
+ 0x75, 0xd0, 0xc8, 0x75,
+ 0xca, 0xc5, 0xea, 0xe5,
+ 0x8a, 0x85, 0x82, 0x08,
+ 0x80, 0xe2, 0x0e, 0x80,
+ 0xc2, 0x0c, 0x80, 0xd0,
+ 0xd8, 0x74, 0x40, 0xcc,
+ 0xa0, 0xda, 0xd5, 0x30,
+ 0xee, 0xa0, 0xf0, 0x88,
+ 0xa0, 0x82, 0x28, 0x7f,
+ 0xe2, 0x2e, 0x7f, 0xd2,
+ 0x0d, 0x80, 0xc2, 0x2c,
+ 0x7f, 0x20, 0xdd, 0xa0,
+ 0xd2, 0x2d, 0x7f, 0xe0,
+ 0xcc, 0x30, 0x80, 0xdd,
+ 0x30, 0xd0, 0xcc, 0x30,
+ 0xc9, 0x0b, 0x4b, 0xbb,
+ 0x66, 0x49, 0xb1, 0xa2,
+ 0xca, 0xe0, 0xe6, 0x16,
+ 0xa7, 0xc2, 0xa1, 0x18,
+ 0x98, 0x0a, 0x99, 0x0b,
+ 0x88, 0x1a, 0x89, 0x1b,
+ 0xf8, 0x2a, 0xf9, 0x2b,
+ 0xe8, 0x3a, 0xe9, 0x3b,
+ 0xad, 0x01, 0x0c, 0x0b,
+ 0xa5, 0xa8, 0x04, 0x0c,
+ 0x02, 0x1d, 0xf0, 0x00,
+ 0x36, 0x41, 0x00, 0xbd,
+ 0x03, 0x81, 0xa6, 0xed,
+ 0x3d, 0x04, 0x42, 0xa2,
+ 0x6e, 0x40, 0x42, 0xd1,
+ 0x1c, 0x0c, 0x8a, 0x24,
+ 0xa2, 0xd2, 0x4b, 0xa2,
+ 0xca, 0xc5, 0x65, 0x93,
+ 0x04, 0xbd, 0x03, 0x0c,
+ 0x8c, 0xa2, 0xd2, 0x4b,
+ 0xa2, 0xca, 0xd5, 0xa5,
+ 0x92, 0x04, 0xbd, 0x05,
+ 0x1c, 0x0c, 0xa2, 0xd2,
+ 0x4b, 0xa2, 0xca, 0xfd,
+ 0xa5, 0x91, 0x04, 0xbd,
+ 0x06, 0x0c, 0x8c, 0xa2,
+ 0xd2, 0x4b, 0xdb, 0xaa,
+ 0xe5, 0x90, 0x04, 0xbd,
+ 0x07, 0x0c, 0x8c, 0xa2,
+ 0xd2, 0x4b, 0xa2, 0xca,
+ 0x15, 0x25, 0x90, 0x04,
+ 0x91, 0xda, 0xed, 0x0c,
+ 0x18, 0x9a, 0x94, 0x82,
+ 0x49, 0x7d, 0x1d, 0xf0,
+ 0x36, 0x41, 0x00, 0xbd,
+ 0x03, 0xa1, 0xea, 0xed,
+ 0xc2, 0xa1, 0x80, 0xa5,
+ 0x8e, 0x04, 0xbd, 0x04,
+ 0xa1, 0xea, 0xed, 0x0c,
+ 0x3c, 0xe5, 0x8d, 0x04,
+ 0x91, 0xd1, 0xed, 0xa2,
+ 0xa2, 0x6e, 0xa0, 0xa2,
+ 0xd1, 0x0c, 0x08, 0xaa,
+ 0x99, 0x82, 0x49, 0x7d,
+ 0x1d, 0xf0, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0x0c,
+ 0x08, 0x91, 0x25, 0xee,
+ 0xa2, 0xa5, 0x20, 0xa0,
+ 0xa2, 0xd1, 0x1c, 0x0c,
+ 0xaa, 0x99, 0xb2, 0x29,
+ 0x7f, 0x7c, 0x3a, 0xa0,
+ 0xab, 0x10, 0xb0, 0xb0,
+ 0x14, 0xe0, 0xbb, 0x11,
+ 0xb0, 0xaa, 0x20, 0xb2,
+ 0xaf, 0x0f, 0xb0, 0xaa,
+ 0x10, 0xc0, 0xaa, 0x20,
+ 0xb1, 0x1d, 0xee, 0xc1,
+ 0x1d, 0xee, 0xb0, 0xaa,
+ 0x10, 0xb1, 0x1c, 0xee,
+ 0xc0, 0xaa, 0x10, 0xb0,
+ 0xaa, 0x10, 0xa2, 0x69,
+ 0x7f, 0xad, 0x02, 0x92,
+ 0xd9, 0x02, 0x82, 0x59,
+ 0x00, 0xe5, 0x61, 0x01,
+ 0xad, 0x02, 0x25, 0x60,
+ 0x01, 0x1d, 0xf0, 0x00,
+ 0x36, 0xc1, 0x00, 0x2c,
+ 0x0c, 0x0c, 0x0a, 0xd1,
+ 0x16, 0xee, 0x51, 0x6e,
+ 0xed, 0x1c, 0xd9, 0x41,
+ 0x7f, 0xed, 0x61, 0x11,
+ 0xee, 0x4c, 0xc3, 0xf2,
+ 0xa5, 0x20, 0xf0, 0xf2,
+ 0x82, 0x30, 0x32, 0x82,
+ 0x39, 0xe1, 0x6a, 0x6f,
+ 0x4a, 0x33, 0x82, 0x23,
+ 0x7f, 0x72, 0xd6, 0x02,
+ 0x2c, 0xa4, 0x49, 0xb1,
+ 0x72, 0x17, 0x14, 0x41,
+ 0x0a, 0xee, 0x82, 0xc8,
+ 0xfc, 0x90, 0x77, 0x10,
+ 0x2c, 0xe9, 0x99, 0xf1,
+ 0x97, 0x38, 0x02, 0x86,
+ 0x2b, 0x00, 0xc9, 0xa1,
+ 0xf9, 0xc1, 0x91, 0x06,
+ 0xee, 0x80, 0x88, 0x90,
+ 0x9a, 0x88, 0xa0, 0x08,
+ 0x00, 0xc6, 0x33, 0x00,
+ 0x06, 0xcc, 0x01, 0x86,
+ 0x25, 0x00, 0xc6, 0x24,
+ 0x00, 0x46, 0xb2, 0x01,
+ 0x46, 0xad, 0x01, 0x86,
+ 0xa2, 0x01, 0x06, 0x90,
+ 0x01, 0xc6, 0x7a, 0x01,
+ 0x46, 0x20, 0x00, 0x86,
+ 0x1f, 0x00, 0xc6, 0x1e,
+ 0x00, 0x46, 0x6d, 0x01,
+ 0x46, 0x1d, 0x00, 0x86,
+ 0x56, 0x01, 0x46, 0x4c,
+ 0x01, 0x06, 0x1b, 0x00,
+ 0xc6, 0x3a, 0x01, 0x46,
+ 0x29, 0x01, 0xc6, 0x18,
+ 0x00, 0x06, 0x18, 0x00,
+ 0xc6, 0x1d, 0x01, 0x86,
+ 0x16, 0x00, 0x06, 0x0a,
+ 0x01, 0x06, 0x15, 0x00,
+ 0xc6, 0x1b, 0x00, 0x46,
+ 0x1e, 0x00, 0x06, 0xf5,
+ 0x00, 0x86, 0x0c, 0x00,
+ 0x46, 0xef, 0x00, 0xc6,
+ 0xea, 0x00, 0x46, 0x1b,
+ 0x00, 0x86, 0x1a, 0x00,
+ 0xc6, 0xca, 0x00, 0x06,
+ 0xac, 0x00, 0x46, 0x18,
+ 0x00, 0x46, 0x8f, 0x00,
+ 0xc6, 0x7a, 0x00, 0x86,
+ 0x71, 0x00, 0xc6, 0x09,
+ 0x00, 0x06, 0x09, 0x00,
+ 0x46, 0x08, 0x00, 0x46,
+ 0x56, 0x00, 0xc6, 0x4f,
+ 0x00, 0xc6, 0x40, 0x00,
+ 0x06, 0x34, 0x00, 0xad,
+ 0x02, 0x25, 0xa1, 0x01,
+ 0x8c, 0xda, 0x0c, 0x14,
+ 0xad, 0x02, 0x65, 0x3e,
+ 0xff, 0x40, 0x77, 0x20,
+ 0x2c, 0x19, 0x92, 0x63,
+ 0x7f, 0x0c, 0x09, 0xdc,
+ 0x69, 0xb2, 0xd3, 0x02,
+ 0xb2, 0xcb, 0x80, 0xb2,
+ 0x0b, 0x81, 0x20, 0xa0,
+ 0x74, 0xf0, 0xbb, 0x11,
+ 0xb0, 0xb7, 0x20, 0xb0,
+ 0xb0, 0x74, 0xa5, 0x53,
+ 0x01, 0x1d, 0xf0, 0x1c,
+ 0xfd, 0xe2, 0xd3, 0x02,
+ 0xe2, 0x0e, 0x01, 0x2c,
+ 0x2c, 0xe0, 0xcd, 0x83,
+ 0xc2, 0x63, 0x7f, 0x9d,
+ 0x0a, 0x86, 0xf3, 0xff,
+ 0xad, 0x02, 0xe5, 0xd1,
+ 0x01, 0xad, 0x02, 0x65,
+ 0x9c, 0x01, 0x16, 0xfa,
+ 0xfb, 0xa1, 0xcc, 0xed,
+ 0x0c, 0x1b, 0xe5, 0x02,
+ 0xff, 0x0c, 0x2a, 0xc1,
+ 0xc8, 0xed, 0x20, 0xb0,
+ 0x74, 0xe2, 0xa9, 0xff,
+ 0xd2, 0x26, 0x89, 0x0c,
+ 0x18, 0x42, 0xd3, 0x02,
+ 0x0c, 0x89, 0x0c, 0x0f,
+ 0xf2, 0x66, 0x8c, 0xf2,
+ 0x66, 0x8d, 0x90, 0x77,
+ 0x20, 0x42, 0xc4, 0x80,
+ 0xf2, 0x44, 0x81, 0x82,
+ 0x44, 0x80, 0xe0, 0xdd,
+ 0x10, 0xd2, 0x66, 0x89,
+ 0x82, 0xa0, 0xee, 0x42,
+ 0xa5, 0x20, 0x40, 0x4b,
+ 0xd1, 0x80, 0x77, 0x10,
+ 0xca, 0xc4, 0xa2, 0x4c,
+ 0x80, 0xad, 0x01, 0x65,
+ 0xfb, 0xfe, 0xbd, 0x01,
+ 0x0c, 0xbc, 0x52, 0xd5,
+ 0x07, 0x52, 0xc5, 0xd1,
+ 0x5a, 0x54, 0xad, 0x05,
+ 0x25, 0x6e, 0x04, 0xa1,
+ 0xb6, 0xed, 0x65, 0x2d,
+ 0x01, 0xed, 0x05, 0xc1,
+ 0xb4, 0xed, 0xa0, 0xb0,
+ 0xf4, 0x0c, 0x0d, 0xad,
+ 0x02, 0x65, 0x68, 0xff,
+ 0x0c, 0x59, 0x92, 0x63,
+ 0x7f, 0x06, 0xd1, 0xff,
+ 0xad, 0x02, 0x25, 0x94,
+ 0x01, 0x16, 0xca, 0xf3,
+ 0xb1, 0xaa, 0xed, 0xd2,
+ 0xa5, 0x20, 0x20, 0xc0,
+ 0x74, 0xa2, 0xd3, 0x02,
+ 0xa2, 0xca, 0x80, 0xd0,
+ 0xcc, 0xd1, 0xa2, 0x0a,
+ 0xc5, 0xca, 0xbb, 0xb2,
+ 0x0b, 0x80, 0xb7, 0x8a,
+ 0x02, 0xc6, 0xa8, 0x01,
+ 0xb8, 0xf1, 0xb2, 0x63,
+ 0x7f, 0x06, 0xc5, 0xff,
+ 0xad, 0x02, 0x65, 0x77,
+ 0xff, 0xec, 0x1a, 0xe5,
+ 0x88, 0x04, 0xbd, 0x0a,
+ 0xa2, 0x23, 0x83, 0xe5,
+ 0x6c, 0x03, 0xe2, 0xa3,
+ 0xe8, 0xc2, 0xd3, 0x02,
+ 0xd2, 0x25, 0x1f, 0xc2,
+ 0x1c, 0x05, 0xd0, 0xda,
+ 0xc2, 0xe0, 0xdd, 0xc2,
+ 0xd7, 0x3c, 0x02, 0xc6,
+ 0x43, 0x02, 0x92, 0xd3,
+ 0x02, 0x92, 0xc9, 0x80,
+ 0x92, 0x09, 0x87, 0x92,
+ 0x63, 0x7f, 0xc6, 0xb6,
+ 0xff, 0xad, 0x02, 0xa5,
+ 0x8d, 0x01, 0x16, 0x3a,
+ 0xed, 0xa2, 0xd3, 0x02,
+ 0xa2, 0xca, 0x80, 0xa2,
+ 0x0a, 0x86, 0xa2, 0x63,
+ 0x7f, 0x06, 0xb1, 0xff,
+ 0xad, 0x02, 0x25, 0x8c,
+ 0x01, 0x16, 0xca, 0xeb,
+ 0x2c, 0xfc, 0xa2, 0xd3,
+ 0x02, 0xa2, 0xca, 0x80,
+ 0x92, 0x0a, 0x88, 0xc2,
+ 0x63, 0x7f, 0xb2, 0xc9,
+ 0xfd, 0x16, 0x6b, 0x65,
+ 0x66, 0x79, 0x02, 0x46,
+ 0x02, 0x02, 0x66, 0x89,
+ 0x02, 0x86, 0x0a, 0x02,
+ 0x66, 0x99, 0x02, 0xc6,
+ 0x12, 0x02, 0x66, 0xa9,
+ 0x02, 0x06, 0x1b, 0x02,
+ 0xb2, 0xc9, 0xef, 0x56,
+ 0xab, 0xe8, 0xa1, 0x81,
+ 0xed, 0xe5, 0x1f, 0x01,
+ 0xc1, 0x80, 0xed, 0x0c,
+ 0x0d, 0xa0, 0xb0, 0xf4,
+ 0xf2, 0xa5, 0x20, 0x20,
+ 0xe0, 0x74, 0xf0, 0xee,
+ 0xd1, 0xad, 0x02, 0xea,
+ 0xe5, 0xe2, 0xde, 0x07,
+ 0xe2, 0xce, 0xd0, 0xe5,
+ 0x16, 0x01, 0xc6, 0x98,
+ 0xff, 0x92, 0x26, 0x8c,
+ 0xb2, 0xa9, 0xff, 0x82,
+ 0x26, 0x89, 0xc2, 0xa0,
+ 0xef, 0x2c, 0x8d, 0xd2,
+ 0x63, 0x7f, 0xc0, 0x77,
+ 0x10, 0xb0, 0x88, 0x10,
+ 0x1b, 0x99, 0x92, 0x66,
+ 0x8c, 0x82, 0x66, 0x89,
+ 0xc6, 0x9b, 0xff, 0x48,
+ 0xb1, 0xc2, 0x26, 0x89,
+ 0xb2, 0xa5, 0x20, 0x20,
+ 0xa0, 0x74, 0xe2, 0xa6,
+ 0xc8, 0xea, 0xe5, 0xea,
+ 0xdf, 0xb0, 0xba, 0xd1,
+ 0xc0, 0xc8, 0x04, 0xba,
+ 0xb5, 0xb2, 0xdb, 0x07,
+ 0xb2, 0xcb, 0xd0, 0xe5,
+ 0x71, 0xfe, 0xac, 0x2a,
+ 0x1c, 0x05, 0xa1, 0x66,
+ 0xed, 0xb2, 0xa3, 0xe8,
+ 0x65, 0x2f, 0x01, 0x50,
+ 0x77, 0x20, 0x48, 0xa1,
+ 0xe2, 0x26, 0x8c, 0xc2,
+ 0x26, 0x89, 0xd2, 0xa6,
+ 0x00, 0xd0, 0xcc, 0x20,
+ 0x1b, 0xee, 0xe2, 0x66,
+ 0x8c, 0xc2, 0x66, 0x89,
+ 0x42, 0x63, 0x7f, 0x86,
+ 0x7c, 0xff, 0xad, 0x02,
+ 0xe5, 0x7e, 0x01, 0x16,
+ 0x2a, 0x58, 0xf2, 0x26,
+ 0x89, 0xf0, 0xf9, 0x14,
+ 0x56, 0xaf, 0x50, 0x0c,
+ 0x1f, 0x1c, 0x0e, 0x0c,
+ 0x0b, 0xa1, 0x51, 0xed,
+ 0x92, 0xa5, 0x20, 0x20,
+ 0x40, 0x74, 0x90, 0x94,
+ 0xd1, 0x99, 0x61, 0xaa,
+ 0x99, 0xb2, 0x49, 0x84,
+ 0xe2, 0x49, 0x80, 0xf2,
+ 0x49, 0x85, 0xd2, 0x26,
+ 0x8c, 0xd0, 0xd0, 0xf5,
+ 0xd2, 0x49, 0x81, 0xc2,
+ 0x26, 0x8c, 0xc0, 0xc8,
+ 0x41, 0xc2, 0x49, 0x82,
+ 0xa2, 0x26, 0x8c, 0xa2,
+ 0x49, 0x83, 0xb2, 0x49,
+ 0x86, 0x82, 0x26, 0x89,
+ 0xad, 0x04, 0x80, 0x88,
+ 0x04, 0x82, 0x49, 0x87,
+ 0xa5, 0x72, 0x01, 0x16,
+ 0xea, 0x7e, 0xad, 0x04,
+ 0x0c, 0x1b, 0x25, 0x76,
+ 0x01, 0x0c, 0x19, 0x0c,
+ 0x4a, 0xa2, 0x63, 0x7f,
+ 0xc6, 0x61, 0xff, 0xad,
+ 0x02, 0x25, 0x78, 0x01,
+ 0x16, 0xda, 0xd7, 0xa2,
+ 0x24, 0x1f, 0x0c, 0x7b,
+ 0x25, 0x59, 0x02, 0x16,
+ 0x6a, 0x4c, 0xad, 0x02,
+ 0xe5, 0x76, 0x01, 0x16,
+ 0xea, 0x4b, 0xb1, 0x8c,
+ 0xec, 0xa2, 0x24, 0x1f,
+ 0x91, 0x3a, 0xed, 0xb0,
+ 0xaa, 0x82, 0x9a, 0xba,
+ 0xb2, 0x0b, 0x80, 0xb2,
+ 0xcb, 0xf6, 0x56, 0xbb,
+ 0x4c, 0x61, 0x2e, 0xed,
+ 0x4b, 0xc9, 0xca, 0xca,
+ 0xc2, 0x0c, 0x80, 0x20,
+ 0x40, 0x74, 0x0b, 0xcc,
+ 0x56, 0x9c, 0x61, 0xa1,
+ 0x32, 0xed, 0x65, 0x0b,
+ 0x01, 0xc1, 0x30, 0xed,
+ 0x0c, 0x0d, 0xa0, 0xb0,
+ 0xf4, 0xe2, 0xa5, 0x20,
+ 0xe0, 0xe4, 0xd1, 0xad,
+ 0x02, 0xea, 0xe5, 0xe2,
+ 0xde, 0x07, 0xe2, 0xce,
+ 0xd1, 0xa5, 0x45, 0xff,
+ 0xa1, 0xa0, 0xec, 0xb2,
+ 0xa3, 0xe8, 0xe5, 0x1f,
+ 0x01, 0x0c, 0x09, 0x2c,
+ 0x8f, 0xf2, 0x63, 0x7f,
+ 0xc6, 0x7c, 0x01, 0xb1,
+ 0x75, 0xec, 0x92, 0x24,
+ 0x1f, 0x81, 0x74, 0xec,
+ 0xb0, 0x99, 0x82, 0x9a,
+ 0x88, 0x82, 0x08, 0x80,
+ 0x56, 0x78, 0x40, 0xa2,
+ 0xa5, 0x20, 0x20, 0x40,
+ 0x74, 0xa0, 0xa4, 0xd1,
+ 0x4b, 0xcd, 0xca, 0xca,
+ 0xe2, 0x0c, 0x7f, 0xb2,
+ 0x0c, 0x7c, 0x92, 0x0c,
+ 0x7d, 0x80, 0xbb, 0x11,
+ 0xba, 0x99, 0x80, 0xee,
+ 0x11, 0xb2, 0x0c, 0x80,
+ 0xc2, 0x0c, 0x7e, 0x92,
+ 0x51, 0x06, 0x00, 0xcc,
+ 0x11, 0xea, 0xcc, 0xca,
+ 0xbb, 0x27, 0xe9, 0x20,
+ 0x37, 0xe9, 0x1d, 0x99,
+ 0x41, 0xcc, 0x7b, 0xd1,
+ 0x13, 0xed, 0xc2, 0x26,
+ 0x8d, 0xd7, 0x1c, 0x10,
+ 0xe2, 0xd3, 0x02, 0xe2,
+ 0xce, 0x80, 0xe2, 0x0e,
+ 0x80, 0x0b, 0xee, 0x56,
+ 0x6e, 0x54, 0x16, 0x3b,
+ 0x54, 0xad, 0x04, 0x0c,
+ 0x9b, 0x25, 0x67, 0x01,
+ 0x0c, 0x19, 0x0c, 0x4f,
+ 0xf2, 0x63, 0x7f, 0x06,
+ 0x26, 0xff, 0xad, 0x02,
+ 0x0c, 0xcb, 0xc1, 0x08,
+ 0xed, 0x2c, 0x5d, 0x25,
+ 0xc7, 0xfe, 0xc6, 0x21,
+ 0xff, 0xa1, 0x01, 0xed,
+ 0xb2, 0xa3, 0xe8, 0x65,
+ 0x16, 0x01, 0x88, 0xa1,
+ 0x82, 0x63, 0x7f, 0x86,
+ 0x1d, 0xff, 0xad, 0x02,
+ 0x25, 0x67, 0x01, 0x16,
+ 0xea, 0xc6, 0xa1, 0x00,
+ 0xed, 0x92, 0x26, 0x89,
+ 0x82, 0xa5, 0x20, 0x20,
+ 0x40, 0x74, 0x80, 0x44,
+ 0xd1, 0x90, 0x98, 0x04,
+ 0xaa, 0xa4, 0x92, 0x4a,
+ 0x51, 0xa1, 0xfb, 0xec,
+ 0xa5, 0xfc, 0x00, 0xc1,
+ 0xfa, 0xec, 0x0c, 0x0d,
+ 0xa0, 0xb0, 0xf4, 0xe2,
+ 0xd5, 0x07, 0xad, 0x02,
+ 0xe2, 0xce, 0xd1, 0xea,
+ 0xe4, 0x65, 0x37, 0xff,
+ 0xa1, 0xf6, 0xec, 0xb2,
+ 0xa3, 0xe8, 0xa5, 0x11,
+ 0x01, 0x1c, 0xe9, 0xc6,
+ 0x0a, 0xff, 0xad, 0x02,
+ 0xa5, 0x62, 0x01, 0x16,
+ 0x6a, 0xc2, 0x0c, 0xb8,
+ 0x91, 0xe4, 0xec, 0x52,
+ 0xd5, 0x07, 0xd2, 0xa5,
+ 0x20, 0x20, 0x40, 0x74,
+ 0xbd, 0x04, 0xd0, 0xd4,
+ 0xd1, 0x52, 0xc5, 0xd1,
+ 0x5a, 0x5d, 0x9a, 0x9d,
+ 0x82, 0x49, 0x80, 0xc2,
+ 0x26, 0x89, 0xad, 0x05,
+ 0xc0, 0xc8, 0x04, 0x65,
+ 0x5b, 0xfe, 0xad, 0x04,
+ 0xa5, 0x58, 0x01, 0x16,
+ 0x4a, 0x44, 0xad, 0x04,
+ 0x0c, 0x1b, 0x25, 0x5c,
+ 0x01, 0x0c, 0x19, 0x0c,
+ 0x4e, 0xe2, 0x63, 0x7f,
+ 0xc6, 0xf9, 0xfe, 0xa2,
+ 0xa5, 0x20, 0x20, 0x40,
+ 0x74, 0xa0, 0xa4, 0xd1,
+ 0xbd, 0x04, 0xaa, 0xa5,
+ 0xa2, 0xda, 0x07, 0xa2,
+ 0xca, 0xd0, 0x25, 0x7e,
+ 0xfe, 0x0b, 0xba, 0x56,
+ 0xdb, 0x2d, 0x1c, 0xb9,
+ 0x92, 0x63, 0x7f, 0x0c,
+ 0x09, 0x86, 0xf0, 0xfe,
+ 0xad, 0x02, 0xe5, 0x5b,
+ 0x01, 0x16, 0x8a, 0xbb,
+ 0x0c, 0x98, 0x91, 0xc8,
+ 0xec, 0x52, 0xd5, 0x07,
+ 0xc2, 0xa5, 0x20, 0x20,
+ 0x40, 0x74, 0xbd, 0x04,
+ 0xc0, 0xc4, 0xd1, 0x52,
+ 0xc5, 0xd1, 0x9a, 0x9c,
+ 0x5a, 0x5c, 0xad, 0x05,
+ 0x82, 0x49, 0x80, 0xa5,
+ 0x80, 0xfe, 0xad, 0x04,
+ 0x25, 0x52, 0x01, 0x16,
+ 0x5a, 0x40, 0xad, 0x04,
+ 0x0c, 0x1b, 0xa5, 0x55,
+ 0x01, 0x0c, 0x19, 0x0c,
+ 0x4d, 0xd2, 0x63, 0x7f,
+ 0xc6, 0xdf, 0xfe, 0xc8,
+ 0xe1, 0xd1, 0xc6, 0xec,
+ 0xa2, 0xa5, 0x20, 0x20,
+ 0xb0, 0x74, 0xa0, 0xab,
+ 0xd1, 0xda, 0xd5, 0xda,
+ 0xcc, 0xaa, 0xa5, 0xa2,
+ 0xda, 0x07, 0xa2, 0xca,
+ 0xd0, 0xe5, 0x7f, 0xfe,
+ 0x1c, 0x65, 0xa2, 0xa0,
+ 0xa0, 0x4c, 0x0b, 0xe5,
+ 0xbc, 0xfe, 0x52, 0x63,
+ 0x7f, 0xc2, 0xd3, 0x02,
+ 0x0c, 0x0b, 0xd2, 0x24,
+ 0x23, 0x4c, 0x0e, 0xe0,
+ 0xdd, 0x20, 0xd2, 0x64,
+ 0x23, 0xb2, 0x5c, 0x02,
+ 0x46, 0xcf, 0xfe, 0xf2,
+ 0x04, 0x80, 0x1c, 0x0d,
+ 0x16, 0x3f, 0xb6, 0x82,
+ 0x04, 0x81, 0x0b, 0x88,
+ 0x56, 0x08, 0x26, 0x92,
+ 0xd3, 0x02, 0x92, 0x09,
+ 0x02, 0x56, 0x99, 0x26,
+ 0x0c, 0x7b, 0xad, 0x02,
+ 0xc2, 0xa1, 0x2c, 0x25,
+ 0xb0, 0xfe, 0x86, 0x99,
+ 0x00, 0x0c, 0x16, 0xd2,
+ 0xa2, 0x6e, 0xc1, 0xad,
+ 0xec, 0x20, 0xb0, 0x74,
+ 0xca, 0xc5, 0xd0, 0xbb,
+ 0xd1, 0xca, 0xaf, 0x0c,
+ 0x5c, 0xba, 0xb5, 0xb2,
+ 0xdb, 0x49, 0xb2, 0xcb,
+ 0xb0, 0xa5, 0x27, 0x04,
+ 0x52, 0xa0, 0x80, 0xa2,
+ 0xa0, 0xa0, 0xb2, 0xa0,
+ 0x80, 0x0c, 0x78, 0xf1,
+ 0xa5, 0xec, 0xe8, 0xc1,
+ 0x0c, 0x0d, 0xfa, 0xfe,
+ 0xd2, 0x4f, 0x81, 0x62,
+ 0x4f, 0x80, 0x82, 0x6f,
+ 0xc0, 0x4a, 0xee, 0xd2,
+ 0x4e, 0x80, 0xa5, 0xb4,
+ 0xfe, 0x82, 0x24, 0x23,
+ 0x1c, 0x39, 0x92, 0x63,
+ 0x7f, 0x50, 0x88, 0x20,
+ 0x82, 0x64, 0x23, 0x86,
+ 0xb0, 0xfe, 0xa2, 0xa5,
+ 0x20, 0x20, 0x40, 0x74,
+ 0xa0, 0xa4, 0xd1, 0xbd,
+ 0x04, 0xaa, 0xa5, 0xa2,
+ 0xda, 0x07, 0xa2, 0xca,
+ 0xd0, 0xa5, 0x79, 0xfe,
+ 0x56, 0xaa, 0x18, 0xad,
+ 0x04, 0x0c, 0x4b, 0x65,
+ 0x47, 0x01, 0x0c, 0x19,
+ 0x0c, 0x4b, 0xb2, 0x63,
+ 0x7f, 0x86, 0xa6, 0xfe,
+ 0xad, 0x02, 0x65, 0x49,
+ 0x01, 0x16, 0x0a, 0xa9,
+ 0x0c, 0x58, 0x91, 0x7e,
+ 0xec, 0x52, 0xd5, 0x07,
+ 0xc2, 0xa5, 0x20, 0x20,
+ 0xb0, 0x74, 0xc0, 0xcb,
+ 0xd1, 0x52, 0xc5, 0xd1,
+ 0x9a, 0x9c, 0x5a, 0x5c,
+ 0xad, 0x05, 0x82, 0x49,
+ 0x80, 0xc1, 0x87, 0xec,
+ 0xe5, 0x8e, 0xfe, 0xa1,
+ 0x87, 0xec, 0x25, 0xde,
+ 0x00, 0x6d, 0x0a, 0xa1,
+ 0x86, 0xec, 0xa5, 0xdd,
+ 0x00, 0xed, 0x05, 0x1c,
+ 0x24, 0xc1, 0x82, 0xec,
+ 0x0c, 0x0d, 0xaa, 0xb6,
+ 0xb0, 0xb0, 0xf4, 0xad,
+ 0x02, 0x65, 0x18, 0xff,
+ 0x42, 0x63, 0x7f, 0x86,
+ 0x91, 0xfe, 0x0c, 0x46,
+ 0xad, 0x02, 0x25, 0x44,
+ 0x01, 0x16, 0xca, 0xa3,
+ 0xd1, 0x6a, 0xec, 0x52,
+ 0xd5, 0x07, 0xc2, 0xa5,
+ 0x20, 0x20, 0x40, 0x74,
+ 0xbd, 0x04, 0xc0, 0xc4,
+ 0xd1, 0x52, 0xc5, 0xd1,
+ 0x5a, 0x5c, 0xad, 0x05,
+ 0xda, 0xcc, 0x62, 0x4c,
+ 0x80, 0xa5, 0x7b, 0xfe,
+ 0xd2, 0xca, 0xef, 0x16,
+ 0x9d, 0x18, 0xad, 0x04,
+ 0x25, 0x3a, 0x01, 0x16,
+ 0x7a, 0x16, 0xad, 0x04,
+ 0x0c, 0x1b, 0xa5, 0x3d,
+ 0x01, 0x62, 0x63, 0x7f,
+ 0x0c, 0x19, 0x46, 0x80,
+ 0xfe, 0x20, 0x40, 0x74,
+ 0xad, 0x04, 0xe5, 0x8a,
+ 0xfe, 0x16, 0x6a, 0x2e,
+ 0x66, 0x1a, 0x14, 0x0c,
+ 0xbf, 0x82, 0xd3, 0x02,
+ 0x82, 0xc8, 0x80, 0x82,
+ 0x08, 0x82, 0x0c, 0xce,
+ 0x0b, 0x88, 0x80, 0xef,
+ 0x83, 0xe2, 0x63, 0x7f,
+ 0x0c, 0x09, 0x46, 0x76,
+ 0xfe, 0x92, 0xd3, 0x02,
+ 0x92, 0x09, 0x03, 0x16,
+ 0xc9, 0x9f, 0x0c, 0xab,
+ 0xb2, 0x63, 0x7f, 0x06,
+ 0x7d, 0xfe, 0xd1, 0xb7,
+ 0xeb, 0xc2, 0xa5, 0x20,
+ 0x20, 0xa0, 0x74, 0xb2,
+ 0xa6, 0xd0, 0xba, 0xb5,
+ 0xc0, 0xca, 0xd1, 0xd2,
+ 0xdd, 0xfa, 0xba, 0xbc,
+ 0xda, 0xcc, 0xd2, 0xa2,
+ 0x6e, 0xc2, 0x0c, 0x80,
+ 0xd0, 0xaa, 0xd1, 0xd2,
+ 0xd3, 0x02, 0xc0, 0xc0,
+ 0x04, 0xaa, 0xa5, 0xc2,
+ 0x4d, 0x01, 0xa2, 0xda,
+ 0x49, 0xa2, 0xca, 0xb0,
+ 0xc2, 0xa2, 0x15, 0x25,
+ 0x11, 0x04, 0x0c, 0x95,
+ 0xa2, 0xa0, 0xa0, 0x2c,
+ 0x0b, 0xa5, 0x9f, 0xfe,
+ 0xf8, 0xa1, 0xe2, 0x24,
+ 0x23, 0x0c, 0x08, 0x92,
+ 0xd3, 0x02, 0x92, 0xc9,
+ 0x80, 0x82, 0x49, 0x83,
+ 0x52, 0x63, 0x7f, 0xf0,
+ 0xee, 0x20, 0xe2, 0x64,
+ 0x23, 0x06, 0x5a, 0xfe,
+ 0xad, 0x02, 0x65, 0x36,
+ 0x01, 0x16, 0x0a, 0x96,
+ 0xa1, 0x46, 0xec, 0xc1,
+ 0x32, 0xec, 0x82, 0xa5,
+ 0x20, 0x20, 0x40, 0x74,
+ 0x80, 0x44, 0xd1, 0x0c,
+ 0x2b, 0xca, 0xc4, 0xb2,
+ 0x4c, 0x80, 0x25, 0xcc,
+ 0x00, 0xc1, 0x3f, 0xec,
+ 0x0c, 0x0d, 0xa0, 0xb0,
+ 0xf4, 0xe2, 0xd5, 0x07,
+ 0xad, 0x02, 0xe2, 0xce,
+ 0xd9, 0xea, 0xe4, 0xe5,
+ 0x06, 0xff, 0xad, 0x02,
+ 0x0c, 0x3b, 0xc2, 0xa0,
+ 0x64, 0x0c, 0x8d, 0x0c,
+ 0x7f, 0xf2, 0x63, 0x7f,
+ 0x65, 0x90, 0xfe, 0x86,
+ 0x47, 0xfe, 0x82, 0xd3,
+ 0x02, 0x82, 0xc8, 0x80,
+ 0x82, 0x08, 0x82, 0x66,
+ 0x18, 0x0e, 0xad, 0x02,
+ 0x0c, 0x8b, 0xc2, 0xa0,
+ 0xc8, 0x1c, 0x5d, 0xe5,
+ 0x8e, 0xfe, 0x06, 0x03,
+ 0x00, 0xa2, 0xd3, 0x02,
+ 0x0c, 0x09, 0x1c, 0x6b,
+ 0xb2, 0x63, 0x7f, 0x92,
+ 0x5a, 0x02, 0x0c, 0x09,
+ 0xc6, 0x3c, 0xfe, 0x9d,
+ 0x0a, 0x86, 0x3b, 0xfe,
+ 0xf2, 0xd3, 0x02, 0xd2,
+ 0x1f, 0x02, 0xc2, 0xa3,
+ 0xfe, 0x1b, 0xed, 0xe2,
+ 0x5f, 0x02, 0xd7, 0x3c,
+ 0x78, 0x1c, 0x69, 0x46,
+ 0x43, 0xff, 0x0c, 0x09,
+ 0x88, 0xa1, 0x82, 0x63,
+ 0x7f, 0x86, 0x33, 0xfe,
+ 0x20, 0xa0, 0x74, 0x0c,
+ 0x2b, 0x65, 0x29, 0x01,
+ 0x0c, 0x49, 0x92, 0x63,
+ 0x7f, 0x0c, 0x19, 0x06,
+ 0x2f, 0xfe, 0x0c, 0x7b,
+ 0xad, 0x02, 0xc2, 0xa3,
+ 0xe8, 0x65, 0x89, 0xfe,
+ 0x0c, 0x09, 0x46, 0x2b,
+ 0xfe, 0x0c, 0x09, 0x06,
+ 0x2a, 0xfe, 0xa1, 0x18,
+ 0xec, 0xa5, 0xc1, 0x00,
+ 0xed, 0x05, 0x1c, 0x24,
+ 0xc1, 0x16, 0xec, 0xa0,
+ 0xb0, 0xf4, 0x0c, 0x0d,
+ 0xad, 0x02, 0xa5, 0xfc,
+ 0xfe, 0x42, 0x63, 0x7f,
+ 0x0c, 0x09, 0x46, 0x22,
+ 0xfe, 0x0c, 0x09, 0xc1,
+ 0x57, 0xeb, 0x0c, 0x0b,
+ 0xca, 0xca, 0xb2, 0x6c,
+ 0x7f, 0x86, 0x1e, 0xfe,
+ 0xa1, 0x0e, 0xec, 0xb2,
+ 0xa3, 0xe8, 0x3c, 0x0d,
+ 0xd2, 0x63, 0x7f, 0x25,
+ 0xd5, 0x00, 0xc6, 0x19,
+ 0xfe, 0x0c, 0x09, 0x06,
+ 0x19, 0xfe, 0xad, 0x04,
+ 0x0c, 0x6b, 0xe5, 0x22,
+ 0x01, 0x0c, 0x19, 0x0c,
+ 0x4e, 0xe2, 0x63, 0x7f,
+ 0xc6, 0x14, 0xfe, 0x92,
+ 0x0a, 0xc6, 0xdc, 0xa9,
+ 0xa1, 0x04, 0xec, 0x25,
+ 0xbc, 0x00, 0x0c, 0x0e,
+ 0xc1, 0x02, 0xec, 0x42,
+ 0xd3, 0x02, 0x0c, 0x1f,
+ 0x42, 0xc4, 0x80, 0xf2,
+ 0x44, 0xc6, 0xa0, 0x40,
+ 0xf4, 0x06, 0x14, 0x00,
+ 0x66, 0x19, 0x21, 0xa1,
+ 0xfd, 0xeb, 0x25, 0xba,
+ 0x00, 0xa0, 0x40, 0xf4,
+ 0xa1, 0xfa, 0xeb, 0xa5,
+ 0xb9, 0x00, 0xed, 0x0a,
+ 0xc1, 0xf9, 0xeb, 0x0c,
+ 0x28, 0x92, 0xd3, 0x02,
+ 0x92, 0xc9, 0x80, 0x82,
+ 0x49, 0xc6, 0xc6, 0x0a,
+ 0x00, 0x66, 0x29, 0x4c,
+ 0xa1, 0xf5, 0xeb, 0xe5,
+ 0xb7, 0x00, 0xa0, 0x40,
+ 0xf4, 0xa1, 0xf0, 0xeb,
+ 0x25, 0xb7, 0x00, 0xa9,
+ 0x51, 0x0c, 0x36, 0xa1,
+ 0xef, 0xeb, 0xa5, 0xb6,
+ 0x00, 0xc1, 0xee, 0xeb,
+ 0xe8, 0x51, 0xb2, 0xd3,
+ 0x02, 0xb2, 0xcb, 0x80,
+ 0xaa, 0xee, 0x62, 0x4b,
+ 0xc6, 0xbd, 0x04, 0xad,
+ 0x02, 0x92, 0xa5, 0x20,
+ 0x20, 0x80, 0x74, 0x90,
+ 0x88, 0xd1, 0x0c, 0x0d,
+ 0x8a, 0x85, 0x8a, 0xee,
+ 0xe2, 0xde, 0x07, 0xe2,
+ 0xce, 0xd0, 0xa5, 0xac,
+ 0x00, 0xa8, 0xf1, 0xa2,
+ 0x63, 0x7f, 0xc6, 0xee,
+ 0xfd, 0xc9, 0xf1, 0x0c,
+ 0x0d, 0xd2, 0x4a, 0xc6,
+ 0x46, 0xfb, 0xff, 0xa1,
+ 0xe0, 0xeb, 0x65, 0xb2,
+ 0x00, 0x6d, 0x0a, 0xa1,
+ 0xdf, 0xeb, 0xe5, 0xb1,
+ 0x00, 0xed, 0x05, 0x1c,
+ 0xd4, 0xc1, 0xdb, 0xeb,
+ 0x0c, 0x0d, 0xaa, 0xb6,
+ 0xb0, 0xb0, 0xf4, 0xad,
+ 0x02, 0xa5, 0xec, 0xfe,
+ 0x42, 0x63, 0x7f, 0x0c,
+ 0x09, 0x86, 0xe2, 0xfd,
+ 0xa1, 0xd8, 0xeb, 0xe5,
+ 0xaf, 0x00, 0xed, 0x05,
+ 0xc1, 0xd6, 0xeb, 0xa0,
+ 0xb0, 0xf4, 0x0c, 0x0d,
+ 0xad, 0x02, 0xe5, 0xea,
+ 0xfe, 0xad, 0x02, 0x0c,
+ 0xab, 0x1c, 0x4c, 0x1c,
+ 0x9d, 0xe5, 0x74, 0xfe,
+ 0x0c, 0x09, 0x46, 0xd9,
+ 0xfd, 0xb2, 0x66, 0x8d,
+ 0x82, 0xd3, 0x02, 0xcb,
+ 0xe1, 0xe2, 0x9e, 0x00,
+ 0x82, 0xc8, 0x80, 0x5a,
+ 0xba, 0x0c, 0x06, 0xad,
+ 0x04, 0xf2, 0xdb, 0x07,
+ 0xf2, 0xcf, 0xd1, 0x62,
+ 0x48, 0x80, 0xb2, 0xdb,
+ 0x07, 0xdd, 0x0b, 0x62,
+ 0xcb, 0xe5, 0xd2, 0xcd,
+ 0xd2, 0xb2, 0xcb, 0xd5,
+ 0xcd, 0x06, 0xe5, 0x08,
+ 0xfe, 0xfc, 0x3a, 0xad,
+ 0x04, 0x0c, 0x5b, 0xe5,
+ 0x0f, 0x01, 0x86, 0xa1,
+ 0xfe, 0xad, 0x04, 0x0c,
+ 0x2b, 0x25, 0x0f, 0x01,
+ 0x0c, 0x49, 0x92, 0x63,
+ 0x7f, 0x0c, 0x19, 0xb1,
+ 0xf8, 0xea, 0xa2, 0x26,
+ 0x1f, 0xb0, 0xaa, 0x82,
+ 0xc6, 0xa1, 0xff, 0xad,
+ 0x04, 0x0c, 0x3b, 0xa5,
+ 0x0d, 0x01, 0x0c, 0x19,
+ 0x0c, 0x4c, 0xc2, 0x63,
+ 0x7f, 0x86, 0xbf, 0xfd,
+ 0x0c, 0x39, 0x81, 0xa8,
+ 0xeb, 0x48, 0x41, 0xb8,
+ 0xc1, 0x40, 0x44, 0x44,
+ 0x5a, 0x5b, 0x8a, 0x8b,
+ 0xa2, 0xd5, 0x09, 0xbd,
+ 0x06, 0xa2, 0xca, 0x52,
+ 0x42, 0x48, 0x80, 0x92,
+ 0x48, 0x81, 0x40, 0x44,
+ 0xa0, 0xcd, 0x04, 0xa5,
+ 0xe5, 0x03, 0x62, 0xa0,
+ 0x80, 0x4b, 0x94, 0xb1,
+ 0x8e, 0xeb, 0xa8, 0xc1,
+ 0xc8, 0x41, 0x5a, 0xd4,
+ 0xd2, 0xdd, 0x09, 0xc2,
+ 0x4d, 0x52, 0xc0, 0xe8,
+ 0x41, 0xba, 0xaa, 0xe2,
+ 0x4d, 0x53, 0xb2, 0xa0,
+ 0x80, 0x92, 0x6a, 0x1e,
+ 0xa2, 0xa0, 0xa0, 0x65,
+ 0x72, 0xfe, 0x0c, 0x09,
+ 0xf1, 0x85, 0xeb, 0x2c,
+ 0x68, 0xe2, 0x2f, 0x23,
+ 0x82, 0x63, 0x7f, 0x60,
+ 0xee, 0x20, 0xe2, 0x6f,
+ 0x23, 0x86, 0xa6, 0xfd,
+ 0xa1, 0x9d, 0xeb, 0xe5,
+ 0xa0, 0x00, 0xc1, 0x9b,
+ 0xeb, 0x0c, 0x0d, 0xa0,
+ 0xb0, 0xf4, 0xf2, 0xa5,
+ 0x20, 0x20, 0xe0, 0x74,
+ 0xf0, 0xee, 0xd1, 0xad,
+ 0x02, 0xea, 0xe5, 0xe2,
+ 0xde, 0x07, 0xe2, 0xce,
+ 0xd0, 0xa5, 0x97, 0x00,
+ 0x46, 0x9c, 0xfd, 0xa1,
+ 0x94, 0xeb, 0x65, 0x9e,
+ 0x00, 0xc1, 0x92, 0xeb,
+ 0x0c, 0x0d, 0xa0, 0xb0,
+ 0xf4, 0xf2, 0xa5, 0x20,
+ 0x20, 0xe0, 0x74, 0xf0,
+ 0xee, 0xd1, 0xad, 0x02,
+ 0xea, 0xe5, 0xe2, 0xde,
+ 0x07, 0xe2, 0xce, 0xd0,
+ 0x25, 0x95, 0x00, 0x86,
+ 0x92, 0xfd, 0xa1, 0x8b,
+ 0xeb, 0xe5, 0x9b, 0x00,
+ 0xc1, 0x8a, 0xeb, 0x0c,
+ 0x0d, 0xa0, 0xb0, 0xf4,
+ 0xf2, 0xa5, 0x20, 0x20,
+ 0xe0, 0x74, 0xf0, 0xee,
+ 0xd1, 0xad, 0x02, 0xea,
+ 0xe5, 0xe2, 0xde, 0x07,
+ 0xe2, 0xce, 0xd0, 0xe5,
+ 0x92, 0x00, 0xc6, 0x88,
+ 0xfd, 0xa1, 0x82, 0xeb,
+ 0x65, 0x99, 0x00, 0x4d,
+ 0x0a, 0xa1, 0x81, 0xeb,
+ 0xe5, 0x98, 0x00, 0x6d,
+ 0x0a, 0x49, 0x91, 0xa1,
+ 0x80, 0xeb, 0x65, 0x98,
+ 0x00, 0x4d, 0x0a, 0xa1,
+ 0x7f, 0xeb, 0xe5, 0x97,
+ 0x00, 0x0c, 0x0d, 0xb8,
+ 0x91, 0xf2, 0xa5, 0x20,
+ 0xaa, 0xc4, 0x20, 0xe0,
+ 0x74, 0xad, 0x02, 0xf0,
+ 0xee, 0xd1, 0x6a, 0xbb,
+ 0xca, 0xbb, 0xb0, 0xb0,
+ 0xf4, 0xc1, 0x74, 0xeb,
+ 0xea, 0xe5, 0xe2, 0xde,
+ 0x07, 0xe2, 0xce, 0xd0,
+ 0x25, 0x8e, 0x00, 0x86,
+ 0x76, 0xfd, 0xad, 0x02,
+ 0x65, 0xfd, 0x00, 0xcc,
+ 0x1a, 0x06, 0x74, 0xfd,
+ 0xa1, 0x72, 0xeb, 0x65,
+ 0x94, 0x00, 0xc1, 0x70,
+ 0xeb, 0x0c, 0x0d, 0xa0,
+ 0xb0, 0xf4, 0xf2, 0xa5,
+ 0x20, 0x20, 0xe0, 0x74,
+ 0xf0, 0xee, 0xd1, 0xad,
+ 0x02, 0xea, 0xe5, 0xe2,
+ 0xde, 0x07, 0xe2, 0xce,
+ 0xd0, 0x25, 0x8b, 0x00,
+ 0x3c, 0x19, 0x46, 0xb1,
+ 0xfd, 0xa1, 0x68, 0xeb,
+ 0xa5, 0x91, 0x00, 0xa9,
+ 0x71, 0xa1, 0x67, 0xeb,
+ 0x25, 0x91, 0x00, 0xa9,
+ 0x81, 0x48, 0x61, 0xa1,
+ 0x66, 0xeb, 0xa5, 0x90,
+ 0x00, 0x0c, 0x0d, 0xc8,
+ 0x81, 0xb8, 0x71, 0xe2,
+ 0xd5, 0x07, 0xe2, 0xce,
+ 0xd1, 0xea, 0xe4, 0xca,
+ 0xbb, 0xc1, 0x5e, 0xeb,
+ 0xba, 0xba, 0xb0, 0xb0,
+ 0xf4, 0xad, 0x02, 0xe5,
+ 0xca, 0xfe, 0x48, 0xb1,
+ 0xad, 0x02, 0x1c, 0x1b,
+ 0xc2, 0xa0, 0x64, 0x2c,
+ 0x9d, 0xa5, 0x54, 0xfe,
+ 0x0c, 0x09, 0x81, 0xea,
+ 0xea, 0xf2, 0xa9, 0xff,
+ 0xd2, 0x26, 0x89, 0xe2,
+ 0xa2, 0x00, 0xf0, 0xdd,
+ 0x10, 0xf8, 0xe1, 0xe0,
+ 0xdd, 0x20, 0xd2, 0x66,
+ 0x89, 0x8a, 0xff, 0x42,
+ 0x4f, 0x7f, 0x46, 0x51,
+ 0xfd, 0x00, 0x00, 0x00,
+ 0x36, 0xc1, 0x00, 0xad,
+ 0x02, 0xe5, 0xd9, 0xfe,
+ 0x0c, 0x04, 0x1c, 0xdb,
+ 0x1c, 0x6e, 0x0c, 0x1d,
+ 0x72, 0xa6, 0xd0, 0xc0,
+ 0x82, 0x11, 0x51, 0x4c,
+ 0xeb, 0x0c, 0xe3, 0x0c,
+ 0x4f, 0xf9, 0x91, 0x39,
+ 0x71, 0x8a, 0x55, 0x0c,
+ 0x93, 0x0c, 0xcf, 0xcc,
+ 0x6a, 0x92, 0x25, 0x7f,
+ 0x99, 0x81, 0x06, 0x01,
+ 0x00, 0x42, 0x65, 0x7f,
+ 0x49, 0x81, 0x0c, 0x3a,
+ 0x1c, 0xf9, 0x1c, 0x16,
+ 0x88, 0x81, 0x69, 0x61,
+ 0x61, 0x74, 0xea, 0x97,
+ 0xb8, 0x74, 0xd9, 0xa1,
+ 0xa9, 0xb1, 0xb9, 0x21,
+ 0xf9, 0x41, 0xe9, 0x31,
+ 0x91, 0x3f, 0xeb, 0x80,
+ 0x88, 0x90, 0x9a, 0x88,
+ 0x91, 0x3e, 0xeb, 0xa0,
+ 0x08, 0x00, 0x86, 0x36,
+ 0x00, 0x06, 0x86, 0x01,
+ 0x06, 0x16, 0x00, 0x06,
+ 0x73, 0x01, 0x86, 0x62,
+ 0x01, 0x86, 0x51, 0x01,
+ 0x46, 0x43, 0x01, 0x86,
+ 0x33, 0x01, 0x86, 0x1f,
+ 0x00, 0x06, 0x2d, 0x01,
+ 0x86, 0x1c, 0x01, 0x86,
+ 0x15, 0x01, 0x46, 0x07,
+ 0x01, 0xc6, 0x02, 0x01,
+ 0x06, 0xa9, 0x00, 0x46,
+ 0xed, 0x00, 0x46, 0xe2,
+ 0x00, 0x06, 0xd1, 0x00,
+ 0x46, 0xc6, 0x00, 0x06,
+ 0xba, 0x00, 0xc6, 0xaf,
+ 0x00, 0x86, 0x9c, 0x00,
+ 0xc6, 0x91, 0x00, 0x86,
+ 0x87, 0x00, 0x46, 0x72,
+ 0x00, 0x06, 0x63, 0x00,
+ 0x46, 0x50, 0x00, 0x06,
+ 0x4b, 0x00, 0x06, 0x44,
+ 0x00, 0x86, 0x38, 0x00,
+ 0x06, 0x2f, 0x00, 0x9d,
+ 0x04, 0x86, 0x0c, 0x00,
+ 0xad, 0x02, 0xe5, 0xe7,
+ 0x00, 0x16, 0x0a, 0x0d,
+ 0xa1, 0xd7, 0xea, 0x65,
+ 0xc4, 0xfe, 0x4d, 0x0a,
+ 0x20, 0x30, 0x74, 0xad,
+ 0x03, 0xa5, 0x7c, 0x00,
+ 0xbd, 0x04, 0xc1, 0xd2,
+ 0xea, 0xdd, 0x0a, 0xe2,
+ 0xa5, 0x20, 0xad, 0x02,
+ 0xe0, 0xe3, 0xd1, 0xd0,
+ 0xd0, 0xf4, 0xea, 0xe6,
+ 0x7a, 0xee, 0x65, 0x75,
+ 0x00, 0x98, 0xb1, 0x2d,
+ 0x09, 0x86, 0x0f, 0x00,
+ 0xad, 0x02, 0x39, 0xc1,
+ 0x25, 0xe4, 0x00, 0x16,
+ 0x6a, 0x09, 0xa1, 0xcb,
+ 0xea, 0x81, 0xf3, 0xea,
+ 0x42, 0xa5, 0x20, 0x20,
+ 0x30, 0x74, 0x40, 0x43,
+ 0xd1, 0xf8, 0xa1, 0x8a,
+ 0x84, 0xf2, 0x48, 0x50,
+ 0x65, 0xbf, 0xfe, 0xa9,
+ 0x01, 0xad, 0x03, 0x25,
+ 0x78, 0x00, 0xb8, 0x01,
+ 0xc1, 0xc3, 0xea, 0xdd,
+ 0x0a, 0x7a, 0xe6, 0xea,
+ 0xe4, 0xad, 0x02, 0xd0,
+ 0xd0, 0xf4, 0x65, 0xb4,
+ 0xfe, 0x28, 0xc1, 0x3d,
+ 0x02, 0x86, 0x0d, 0x00,
+ 0x62, 0xa1, 0x80, 0x3d,
+ 0x0d, 0xad, 0x02, 0x25,
+ 0x15, 0x01, 0xa1, 0xdb,
+ 0xea, 0x0c, 0x2b, 0xf1,
+ 0x34, 0xea, 0x92, 0xd5,
+ 0x02, 0x6a, 0x85, 0x42,
+ 0x48, 0x81, 0x42, 0x59,
+ 0x05, 0xf2, 0x0f, 0xc1,
+ 0x91, 0x31, 0xea, 0x42,
+ 0x48, 0x88, 0x42, 0x65,
+ 0x81, 0x90, 0xff, 0xa0,
+ 0xf2, 0x2f, 0x7f, 0x42,
+ 0x48, 0x82, 0x49, 0x6f,
+ 0xe5, 0xc4, 0xfe, 0x32,
+ 0x65, 0x7f, 0x1d, 0xf0,
+ 0xad, 0x02, 0x65, 0xdc,
+ 0x00, 0x9c, 0x8a, 0xb2,
+ 0xa5, 0x20, 0x20, 0xa0,
+ 0x74, 0xb0, 0xba, 0xd1,
+ 0x1c, 0x04, 0xba, 0xb6,
+ 0x7a, 0xbb, 0xe5, 0x63,
+ 0xfe, 0x38, 0x21, 0xa0,
+ 0x34, 0x93, 0x46, 0xf6,
+ 0xff, 0x1d, 0xf0, 0xad,
+ 0x02, 0x25, 0xda, 0x00,
+ 0x16, 0x5a, 0xff, 0xe2,
+ 0xd5, 0x02, 0xe2, 0xce,
+ 0x80, 0xc2, 0x0e, 0x81,
+ 0x20, 0x30, 0x74, 0x1b,
+ 0xdc, 0xd2, 0x4e, 0x81,
+ 0xf6, 0x3c, 0x02, 0x86,
+ 0x3d, 0x01, 0xad, 0x03,
+ 0x0c, 0x5b, 0x25, 0xd5,
+ 0x00, 0x3d, 0x04, 0x06,
+ 0xeb, 0xff, 0xf2, 0x09,
+ 0x7c, 0x16, 0xcf, 0xfc,
+ 0x82, 0x09, 0x7d, 0x0b,
+ 0x88, 0x56, 0x78, 0x50,
+ 0x92, 0xd5, 0x02, 0x42,
+ 0x49, 0x01, 0x3d, 0x0b,
+ 0xc6, 0xe4, 0xff, 0xa2,
+ 0xd5, 0x02, 0x72, 0x1a,
+ 0x05, 0x70, 0x70, 0x64,
+ 0x56, 0xd7, 0x4f, 0x42,
+ 0x4a, 0x01, 0x06, 0xfa,
+ 0xff, 0xad, 0x02, 0xe5,
+ 0xd4, 0x00, 0x16, 0xfa,
+ 0xf9, 0x82, 0xd5, 0x02,
+ 0xb1, 0x0b, 0xea, 0x92,
+ 0xa5, 0x20, 0x20, 0x30,
+ 0x74, 0x90, 0x93, 0xd1,
+ 0xa1, 0xb3, 0xea, 0xba,
+ 0xb9, 0xaa, 0xa9, 0xc2,
+ 0x0a, 0x51, 0xa2, 0x0a,
+ 0x50, 0x80, 0xcc, 0x11,
+ 0xc0, 0xaa, 0x20, 0xa2,
+ 0x5b, 0x7e, 0xa2, 0x58,
+ 0x05, 0x77, 0xea, 0x42,
+ 0xb7, 0xea, 0x3f, 0x1c,
+ 0x84, 0xa0, 0xb0, 0x64,
+ 0x7a, 0xd6, 0xda, 0xd9,
+ 0xd2, 0x65, 0x81, 0xb2,
+ 0x48, 0x02, 0x06, 0x0d,
+ 0x00, 0xad, 0x02, 0x65,
+ 0xd0, 0x00, 0x16, 0x7a,
+ 0xf5, 0xa1, 0x88, 0xea,
+ 0xa5, 0xac, 0xfe, 0xc1,
+ 0x87, 0xea, 0x0c, 0x0d,
+ 0xbd, 0x0a, 0xf2, 0xa5,
+ 0x20, 0x20, 0xe0, 0x74,
+ 0xf0, 0xee, 0xd1, 0xad,
+ 0x02, 0xea, 0xe6, 0x7a,
+ 0xee, 0x65, 0x5e, 0x00,
+ 0x1c, 0xaa, 0x4d, 0x0a,
+ 0x86, 0x01, 0x00, 0xad,
+ 0x03, 0x0c, 0x9b, 0x65,
+ 0xca, 0x00, 0x3d, 0x04,
+ 0xc6, 0xbf, 0xff, 0xad,
+ 0x02, 0xa5, 0xcc, 0x00,
+ 0x16, 0xda, 0xf1, 0xb2,
+ 0xd5, 0x02, 0xb2, 0xcb,
+ 0x80, 0xa2, 0x0b, 0x82,
+ 0x20, 0x30, 0x74, 0x16,
+ 0x9a, 0x54, 0x68, 0xb1,
+ 0x60, 0x6a, 0x63, 0xad,
+ 0x03, 0x60, 0x46, 0xa0,
+ 0x40, 0x40, 0x74, 0xa5,
+ 0x60, 0x00, 0xbd, 0x04,
+ 0xc1, 0x6f, 0xea, 0xdd,
+ 0x0a, 0xe2, 0x25, 0x81,
+ 0xad, 0x02, 0xd0, 0xd0,
+ 0xf4, 0xa5, 0x59, 0x00,
+ 0x82, 0x25, 0x81, 0xf2,
+ 0xd5, 0x02, 0xf2, 0xcf,
+ 0x80, 0xe2, 0x0f, 0x82,
+ 0x8a, 0x84, 0x82, 0x65,
+ 0x81, 0x60, 0xee, 0xc0,
+ 0xe2, 0x4f, 0x82, 0x1d,
+ 0xf0, 0xad, 0x02, 0xa5,
+ 0xc7, 0x00, 0x16, 0xba,
+ 0xec, 0x81, 0x77, 0xea,
+ 0xa2, 0xa5, 0x20, 0x20,
+ 0x90, 0x74, 0xa0, 0x99,
+ 0xd1, 0x9a, 0x88, 0x82,
+ 0x08, 0x80, 0x80, 0x80,
+ 0x04, 0x16, 0xc8, 0x4d,
+ 0x1c, 0x99, 0x4d, 0x09,
+ 0x86, 0xe0, 0xff, 0xad,
+ 0x02, 0x25, 0xc5, 0x00,
+ 0x16, 0x5a, 0xea, 0x20,
+ 0x30, 0x74, 0xa2, 0xd5,
+ 0x02, 0xa2, 0xca, 0x80,
+ 0xb2, 0x0a, 0x80, 0x3c,
+ 0x2c, 0xb7, 0x3c, 0x02,
+ 0x06, 0x1f, 0x01, 0xad,
+ 0x03, 0x0c, 0xeb, 0x65,
+ 0xc0, 0x00, 0x9d, 0x04,
+ 0x86, 0xf4, 0xff, 0xb1,
+ 0x2c, 0xea, 0x20, 0xc0,
+ 0x74, 0xc0, 0xcc, 0x90,
+ 0xc0, 0xcc, 0x11, 0xca,
+ 0xbb, 0xb2, 0x0b, 0x7d,
+ 0x16, 0x7b, 0x4a, 0xd2,
+ 0xd5, 0x02, 0x42, 0x4d,
+ 0x00, 0xc6, 0x09, 0x00,
+ 0xad, 0x02, 0xe5, 0xc0,
+ 0x00, 0x16, 0x0a, 0xe6,
+ 0x82, 0xd5, 0x02, 0x82,
+ 0xc8, 0x80, 0xe2, 0x08,
+ 0x81, 0x20, 0x30, 0x74,
+ 0x1b, 0xfe, 0xf2, 0x48,
+ 0x81, 0xf6, 0x3e, 0x02,
+ 0x46, 0x02, 0x01, 0xad,
+ 0x03, 0x0c, 0xdb, 0xe5,
+ 0xbb, 0x00, 0xed, 0x04,
+ 0x3d, 0x0e, 0x46, 0x85,
+ 0xff, 0xad, 0x02, 0x25,
+ 0xbe, 0x00, 0x16, 0x3a,
+ 0xe3, 0x91, 0x51, 0xea,
+ 0xb2, 0xa5, 0x20, 0x20,
+ 0xa0, 0x74, 0xb0, 0xaa,
+ 0xd1, 0xb8, 0x41, 0xaa,
+ 0x99, 0x92, 0x09, 0x80,
+ 0xa8, 0x61, 0xb0, 0x99,
+ 0x10, 0x90, 0xa4, 0x93,
+ 0x86, 0xb7, 0xff, 0xad,
+ 0x02, 0xa5, 0xbb, 0x00,
+ 0x16, 0xda, 0xe0, 0xa1,
+ 0x27, 0xea, 0x25, 0x98,
+ 0xfe, 0xc1, 0x25, 0xea,
+ 0x0c, 0x0d, 0xbd, 0x0a,
+ 0xf2, 0xa5, 0x20, 0x20,
+ 0xe0, 0x74, 0xf0, 0xee,
+ 0xd1, 0xad, 0x02, 0xea,
+ 0xe6, 0x7a, 0xee, 0xe5,
+ 0x49, 0x00, 0x1c, 0x49,
+ 0xed, 0x09, 0x86, 0xe9,
+ 0xff, 0xad, 0x02, 0xe5,
+ 0xb8, 0x00, 0x16, 0xfa,
+ 0xdd, 0xa1, 0x46, 0xea,
+ 0xc2, 0xa5, 0x20, 0x20,
+ 0xb0, 0x74, 0xc0, 0xbb,
+ 0xd1, 0x1c, 0x38, 0xba,
+ 0xaa, 0xb8, 0x91, 0xa2,
+ 0x0a, 0x50, 0x98, 0x61,
+ 0xb0, 0xaa, 0x10, 0xa0,
+ 0x98, 0x93, 0x86, 0xf4,
+ 0xff, 0xad, 0x02, 0x65,
+ 0xb6, 0x00, 0x16, 0x7a,
+ 0xdb, 0xf1, 0x30, 0xea,
+ 0x32, 0xa5, 0x20, 0x30,
+ 0x82, 0x82, 0x8a, 0xff,
+ 0xe2, 0x2f, 0x89, 0xe0,
+ 0xd0, 0x05, 0x16, 0x3d,
+ 0xda, 0xad, 0x02, 0x0c,
+ 0x1b, 0xc2, 0xa2, 0x01,
+ 0x0c, 0x0d, 0x91, 0x28,
+ 0xea, 0x20, 0x80, 0x74,
+ 0x30, 0x88, 0xd1, 0x90,
+ 0x9e, 0x10, 0x92, 0x6f,
+ 0x89, 0x8a, 0xe6, 0x7a,
+ 0xee, 0x25, 0x43, 0x00,
+ 0x1c, 0x29, 0xed, 0x09,
+ 0x06, 0xcf, 0xff, 0x38,
+ 0x61, 0xb1, 0x21, 0xea,
+ 0xc2, 0xa5, 0x20, 0xc0,
+ 0xc2, 0x82, 0x20, 0xa0,
+ 0x74, 0xca, 0xbb, 0xb2,
+ 0x2b, 0x89, 0x0c, 0x5c,
+ 0xb0, 0xbe, 0x04, 0x70,
+ 0xbb, 0x11, 0xc0, 0xbb,
+ 0x20, 0xb0, 0xb0, 0xf4,
+ 0x65, 0x65, 0x00, 0x9d,
+ 0x03, 0x46, 0xf4, 0xff,
+ 0xad, 0x02, 0xa5, 0xaf,
+ 0x00, 0x16, 0xca, 0xd4,
+ 0xd1, 0x42, 0xea, 0x82,
+ 0xa5, 0x20, 0x20, 0xf0,
+ 0x74, 0xe1, 0x15, 0xea,
+ 0x80, 0x8f, 0xd1, 0xf0,
+ 0xff, 0x90, 0xc0, 0xff,
+ 0x11, 0x8a, 0xee, 0x82,
+ 0x0e, 0x81, 0xfa, 0xdd,
+ 0xd2, 0x1d, 0x7e, 0xf1,
+ 0x39, 0xea, 0xe2, 0x0e,
+ 0x80, 0x80, 0x88, 0x11,
+ 0x8a, 0xee, 0xe0, 0xe0,
+ 0xf4, 0xe2, 0x5f, 0x40,
+ 0xe0, 0xdd, 0xc0, 0x56,
+ 0x9d, 0x22, 0xad, 0x02,
+ 0x65, 0x49, 0xfe, 0xa1,
+ 0x0b, 0xea, 0x0c, 0x2b,
+ 0x25, 0x93, 0xfe, 0x1c,
+ 0x59, 0x46, 0xe0, 0xff,
+ 0x38, 0x71, 0xad, 0x02,
+ 0x65, 0xaa, 0x00, 0x16,
+ 0xaa, 0xcf, 0x4d, 0x03,
+ 0x86, 0xac, 0xff, 0xad,
+ 0x02, 0xa5, 0xa9, 0x00,
+ 0x16, 0xda, 0xce, 0xa1,
+ 0xdf, 0xe9, 0x25, 0x86,
+ 0xfe, 0x4d, 0x0a, 0x20,
+ 0x30, 0x74, 0xad, 0x03,
+ 0x65, 0x3e, 0x00, 0xbd,
+ 0x04, 0xc1, 0xda, 0xe9,
+ 0xdd, 0x0a, 0xe2, 0xa5,
+ 0x20, 0xad, 0x02, 0xe0,
+ 0xe3, 0xd1, 0xd0, 0xd0,
+ 0xf4, 0xea, 0xe6, 0x7a,
+ 0xee, 0x25, 0x37, 0x00,
+ 0x0c, 0xd3, 0x06, 0xf1,
+ 0xff, 0x82, 0x09, 0x7c,
+ 0x16, 0x98, 0xcb, 0xa2,
+ 0x09, 0x7d, 0x26, 0x1a,
+ 0x46, 0x20, 0xa0, 0x74,
+ 0x0c, 0x2b, 0x65, 0xa2,
+ 0x00, 0xfd, 0x04, 0x46,
+ 0x0e, 0x00, 0x72, 0xc9,
+ 0xfc, 0x20, 0xa0, 0x74,
+ 0xc1, 0xfb, 0xe9, 0xb2,
+ 0xa5, 0x20, 0xb0, 0xb2,
+ 0x82, 0xca, 0xc6, 0x61,
+ 0xf9, 0xe9, 0xb9, 0x11,
+ 0x6a, 0x6b, 0xd2, 0x46,
+ 0x80, 0xca, 0xbb, 0x42,
+ 0x46, 0x81, 0x65, 0x43,
+ 0xfe, 0xa2, 0xa0, 0xa0,
+ 0xb2, 0xa0, 0x80, 0xc8,
+ 0x11, 0x32, 0x66, 0xc0,
+ 0x7a, 0xcc, 0x42, 0x4c,
+ 0x80, 0xa5, 0x89, 0xfe,
+ 0x0c, 0xb9, 0xfd, 0x09,
+ 0x4d, 0x0f, 0x06, 0x89,
+ 0xff, 0xa1, 0xe3, 0xe9,
+ 0xb2, 0xa3, 0xe8, 0xe5,
+ 0x4e, 0x00, 0x20, 0xa0,
+ 0x74, 0xe5, 0x42, 0xfe,
+ 0x0c, 0xa9, 0x06, 0xf9,
+ 0xff, 0xad, 0x02, 0xa5,
+ 0x9f, 0x00, 0x39, 0xc1,
+ 0x16, 0x9a, 0xc4, 0xb2,
+ 0xa5, 0x20, 0x20, 0x30,
+ 0x74, 0xb0, 0xb3, 0xd1,
+ 0xad, 0x03, 0xba, 0xb6,
+ 0x7a, 0xbb, 0xa5, 0x6d,
+ 0xfe, 0x28, 0xc1, 0xad,
+ 0x03, 0x25, 0x69, 0xfe,
+ 0x16, 0xfa, 0x28, 0xd1,
+ 0x96, 0xe9, 0x30, 0xe3,
+ 0x90, 0xc0, 0xee, 0x11,
+ 0xea, 0xdd, 0xd2, 0x0d,
+ 0x7d, 0x0c, 0x8c, 0xd0,
+ 0x2c, 0x93, 0x46, 0xed,
+ 0xfe, 0xad, 0x02, 0xe5,
+ 0x9b, 0x00, 0x16, 0xfa,
+ 0xc0, 0xa1, 0xb1, 0xe9,
+ 0x25, 0x78, 0xfe, 0x4d,
+ 0x0a, 0x20, 0x30, 0x74,
+ 0xad, 0x03, 0xa5, 0x30,
+ 0x00, 0xbd, 0x04, 0xc1,
+ 0xad, 0xe9, 0xdd, 0x0a,
+ 0xe2, 0xa5, 0x20, 0xad,
+ 0x02, 0xe0, 0xe3, 0xd1,
+ 0xd0, 0xd0, 0xf4, 0xea,
+ 0xe6, 0x7a, 0xee, 0x65,
+ 0x29, 0x00, 0x0c, 0x72,
+ 0xc6, 0xdf, 0xfe, 0xad,
+ 0x02, 0x65, 0x98, 0x00,
+ 0x16, 0x9a, 0xbd, 0x42,
+ 0xa5, 0x20, 0x20, 0x30,
+ 0x74, 0x40, 0x43, 0xd1,
+ 0xad, 0x03, 0x4a, 0x46,
+ 0x7a, 0x44, 0xbd, 0x04,
+ 0xe5, 0x68, 0xfe, 0xa1,
+ 0x9e, 0xe9, 0xa5, 0x73,
+ 0xfe, 0x6d, 0x0a, 0xad,
+ 0x03, 0x25, 0x2c, 0x00,
+ 0xbd, 0x06, 0xc1, 0x9a,
+ 0xe9, 0xdd, 0x0a, 0xed,
+ 0x04, 0xad, 0x02, 0xd0,
+ 0xd0, 0xf4, 0xa5, 0x68,
+ 0xfe, 0x0c, 0x6b, 0x2d,
+ 0x0b, 0x86, 0xcf, 0xfe,
+ 0xad, 0x02, 0x65, 0x94,
+ 0x00, 0x16, 0x8a, 0xb9,
+ 0x42, 0xa5, 0x20, 0x20,
+ 0x30, 0x74, 0x40, 0x43,
+ 0xd1, 0xad, 0x03, 0x4a,
+ 0x46, 0x7a, 0x44, 0xbd,
+ 0x04, 0x25, 0x6d, 0xfe,
+ 0xa1, 0x8b, 0xe9, 0xa5,
+ 0x6f, 0xfe, 0x6d, 0x0a,
+ 0xad, 0x03, 0x25, 0x28,
+ 0x00, 0xbd, 0x06, 0xc1,
+ 0x87, 0xe9, 0xdd, 0x0a,
+ 0xed, 0x04, 0xad, 0x02,
+ 0xd0, 0xd0, 0xf4, 0xa5,
+ 0x64, 0xfe, 0x0c, 0x5b,
+ 0xc6, 0xee, 0xff, 0xad,
+ 0x02, 0x65, 0x90, 0x00,
+ 0x16, 0x9a, 0xb5, 0x81,
+ 0xc6, 0xe9, 0x91, 0xa4,
+ 0xe9, 0xa2, 0xd5, 0x02,
+ 0xf2, 0xa5, 0x20, 0x20,
+ 0x30, 0x74, 0xf0, 0xf3,
+ 0xd1, 0xa2, 0xca, 0x80,
+ 0x9a, 0x9f, 0x8a, 0xff,
+ 0x92, 0x09, 0x50, 0x92,
+ 0x4a, 0x88, 0x92, 0x4f,
+ 0x7e, 0x90, 0xe0, 0x04,
+ 0x16, 0xde, 0x14, 0x90,
+ 0x81, 0x04, 0xa1, 0x56,
+ 0xe9, 0x30, 0xb3, 0x90,
+ 0xc0, 0xbb, 0x11, 0xba,
+ 0xaa, 0x82, 0x4a, 0x7d,
+ 0xb8, 0x91, 0x46, 0xdd,
+ 0xff, 0xc1, 0xea, 0xe8,
+ 0xc2, 0x0c, 0x80, 0x16,
+ 0x2c, 0xb1, 0x0c, 0x23,
+ 0xe1, 0x87, 0xe9, 0xf2,
+ 0xa5, 0x20, 0xf0, 0xf2,
+ 0x82, 0x20, 0xa0, 0x74,
+ 0xfa, 0xee, 0xf1, 0xb1,
+ 0xe9, 0xd2, 0x2e, 0x89,
+ 0xb8, 0x91, 0xf0, 0xdd,
+ 0x10, 0xd2, 0x6e, 0x89,
+ 0xe5, 0x3e, 0x00, 0x9d,
+ 0x03, 0x86, 0x91, 0xfe,
+ 0x98, 0x71, 0x06, 0x59,
+ 0xff, 0xa1, 0x6b, 0xe9,
+ 0xa5, 0x65, 0xfe, 0x4d,
+ 0x0a, 0xad, 0x03, 0x65,
+ 0x1e, 0x00, 0xbd, 0x04,
+ 0xc1, 0x68, 0xe9, 0xdd,
+ 0x0a, 0xe2, 0xa5, 0x20,
+ 0xad, 0x02, 0xe0, 0xe3,
+ 0xd1, 0xd0, 0xd0, 0xf4,
+ 0xea, 0xe6, 0x7a, 0xee,
+ 0xe5, 0x16, 0x00, 0x1c,
+ 0xe4, 0x06, 0xb9, 0xfe,
+ 0x20, 0xa0, 0x74, 0x0c,
+ 0x2b, 0xe5, 0x82, 0x00,
+ 0xbd, 0x04, 0x06, 0xbc,
+ 0xfe, 0x70, 0xc7, 0xa0,
+ 0xb2, 0x25, 0x81, 0x32,
+ 0xc9, 0xfc, 0x81, 0x7d,
+ 0xe9, 0x92, 0x0a, 0x08,
+ 0xa2, 0xa5, 0x20, 0x90,
+ 0x91, 0x04, 0xa0, 0x22,
+ 0x82, 0x29, 0x11, 0xf0,
+ 0x99, 0x11, 0x8a, 0x82,
+ 0x92, 0x48, 0x81, 0x72,
+ 0x48, 0x80, 0x6a, 0x22,
+ 0xa2, 0xd2, 0x09, 0xa2,
+ 0xca, 0x52, 0xa5, 0x5a,
+ 0x03, 0xa2, 0xa0, 0xa0,
+ 0xc8, 0x11, 0x70, 0xb7,
+ 0xa0, 0xd2, 0xd5, 0x02,
+ 0xd2, 0x1d, 0x05, 0x2a,
+ 0xeb, 0x3a, 0xcc, 0xe2,
+ 0xde, 0x09, 0xd2, 0x4e,
+ 0x53, 0x4b, 0xbb, 0xd0,
+ 0xd8, 0x41, 0xd2, 0x4e,
+ 0x52, 0xb2, 0x6c, 0x1e,
+ 0xb2, 0xa0, 0x80, 0x25,
+ 0x68, 0xfe, 0x1c, 0xcb,
+ 0x42, 0x65, 0x81, 0x81,
+ 0x82, 0xe9, 0xf2, 0xd5,
+ 0x02, 0xf2, 0xcf, 0x80,
+ 0x42, 0x48, 0x7c, 0x42,
+ 0x4f, 0x82, 0x06, 0xa0,
+ 0xfe, 0xa1, 0x3b, 0xe9,
+ 0x25, 0x5b, 0xfe, 0x4d,
+ 0x0a, 0xad, 0x03, 0xe5,
+ 0x13, 0x00, 0xbd, 0x04,
+ 0xc1, 0x38, 0xe9, 0xdd,
+ 0x0a, 0xe2, 0xa5, 0x20,
+ 0xad, 0x02, 0xe0, 0xe3,
+ 0xd1, 0xd0, 0xd0, 0xf4,
+ 0xea, 0xe6, 0x7a, 0xee,
+ 0x65, 0x0c, 0x00, 0x0c,
+ 0xf4, 0x46, 0xf4, 0xfe,
+ 0x1b, 0xfb, 0xf2, 0x4a,
+ 0x80, 0xa1, 0x27, 0xe9,
+ 0x25, 0x58, 0xfe, 0x4d,
+ 0x0a, 0xa1, 0x34, 0xe9,
+ 0xa5, 0x57, 0xfe, 0xc1,
+ 0x24, 0xe9, 0x0c, 0x0d,
+ 0xaa, 0xb4, 0xe2, 0xa5,
+ 0x20, 0xad, 0x02, 0xe0,
+ 0xe3, 0xd1, 0xb0, 0xb0,
+ 0xf4, 0xea, 0xe6, 0x7a,
+ 0xee, 0x65, 0x09, 0x00,
+ 0x1c, 0x74, 0x06, 0xd6,
+ 0xfe, 0xad, 0x03, 0x0c,
+ 0xbb, 0x65, 0x75, 0x00,
+ 0x49, 0x91, 0x86, 0xad,
+ 0xff, 0xa1, 0x3f, 0xe9,
+ 0xb2, 0xa0, 0x64, 0xe5,
+ 0x25, 0x00, 0x98, 0x31,
+ 0x86, 0xc5, 0xfe, 0x1c,
+ 0x0e, 0xc6, 0xe0, 0xfe,
+ 0xad, 0x03, 0xd2, 0xd5,
+ 0x02, 0x82, 0xa5, 0x20,
+ 0x80, 0x83, 0xd1, 0xd2,
+ 0x1d, 0x05, 0x8a, 0x86,
+ 0xd0, 0xc0, 0x64, 0xc2,
+ 0x4b, 0x82, 0x7a, 0x88,
+ 0xbd, 0x08, 0x82, 0x65,
+ 0x81, 0x65, 0x00, 0xfe,
+ 0x1c, 0xb9, 0x92, 0x65,
+ 0x7f, 0x1d, 0xf0, 0xad,
+ 0x03, 0x0c, 0x2b, 0x25,
+ 0x71, 0x00, 0x2d, 0x04,
+ 0xc6, 0x4b, 0xfe, 0x00,
+ 0x36, 0x41, 0x00, 0xad,
+ 0x02, 0x65, 0x59, 0xfe,
+ 0x8c, 0xea, 0x0c, 0x22,
+ 0x1d, 0xf0, 0xa1, 0x52,
+ 0xe9, 0x0c, 0x0b, 0xa5,
+ 0x20, 0x00, 0x0c, 0x32,
+ 0x1d, 0xf0, 0xad, 0x02,
+ 0xa5, 0x71, 0x00, 0x16,
+ 0xba, 0xfe, 0x91, 0x1a,
+ 0xe9, 0xa2, 0xa5, 0x20,
+ 0xa0, 0xa2, 0xd1, 0x0c,
+ 0x42, 0xaa, 0x99, 0x82,
+ 0x29, 0x7f, 0x7c, 0x3a,
+ 0xa0, 0x88, 0x10, 0x82,
+ 0x69, 0x7f, 0x1d, 0xf0,
+ 0x36, 0x41, 0x00, 0x82,
+ 0xa2, 0x80, 0x37, 0xb8,
+ 0x06, 0xad, 0x02, 0xe5,
+ 0x46, 0x02, 0x1d, 0xf0,
+ 0xb1, 0x44, 0xe9, 0xa1,
+ 0x6e, 0xe8, 0x20, 0xd2,
+ 0xf0, 0x0c, 0x0e, 0xa0,
+ 0xdd, 0xa0, 0xc0, 0x20,
+ 0x00, 0xe9, 0x1d, 0xc0,
+ 0x20, 0x00, 0xe2, 0x5d,
+ 0x0b, 0xc0, 0x20, 0x00,
+ 0x32, 0x5d, 0x0a, 0x0c,
+ 0x5f, 0xc0, 0x20, 0x00,
+ 0xf2, 0x4d, 0x08, 0xc0,
+ 0x20, 0x00, 0x52, 0x5d,
+ 0x0d, 0xc0, 0x20, 0x00,
+ 0xe9, 0x7d, 0xc0, 0x20,
+ 0x00, 0x69, 0x4d, 0x49,
+ 0xaa, 0x39, 0xba, 0x69,
+ 0xea, 0x0c, 0x9c, 0xb9,
+ 0xfa, 0xc2, 0x4a, 0x24,
+ 0xa2, 0xca, 0x24, 0xa5,
+ 0xce, 0x01, 0x1d, 0xf0,
+ 0x36, 0x41, 0x00, 0x00,
+ 0x02, 0x40, 0x0c, 0x03,
+ 0x30, 0x30, 0xb1, 0x07,
+ 0x63, 0x03, 0x3c, 0xb2,
+ 0x1d, 0xf0, 0x3c, 0xa2,
+ 0x1d, 0xf0, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0x31,
+ 0x2b, 0xe9, 0x41, 0x15,
+ 0xe9, 0x27, 0xb3, 0x3c,
+ 0x27, 0x34, 0x02, 0x46,
+ 0x24, 0x00, 0x81, 0x28,
+ 0xe9, 0x91, 0x1c, 0xe9,
+ 0x27, 0x38, 0x02, 0x46,
+ 0x22, 0x00, 0x27, 0x39,
+ 0x02, 0x86, 0x35, 0x00,
+ 0x51, 0x17, 0xe9, 0xa1,
+ 0xfe, 0xe8, 0x27, 0x35,
+ 0x02, 0xc6, 0x38, 0x00,
+ 0x27, 0x3a, 0x02, 0xc6,
+ 0x3b, 0x00, 0xb1, 0x20,
+ 0xe9, 0x27, 0x3b, 0x02,
+ 0x46, 0x47, 0x00, 0xc1,
+ 0x1f, 0xe9, 0x27, 0x3c,
+ 0x54, 0x4c, 0x02, 0x1d,
+ 0xf0, 0xd1, 0x1d, 0xe9,
+ 0xe1, 0xfb, 0xe8, 0x27,
+ 0xbd, 0x24, 0x27, 0xbe,
+ 0x1d, 0xf1, 0x1b, 0xe9,
+ 0x31, 0x02, 0xe9, 0x27,
+ 0x3f, 0x02, 0x46, 0x27,
+ 0x00, 0x27, 0xb3, 0x3f,
+ 0x41, 0x19, 0xe9, 0x27,
+ 0x34, 0x02, 0x06, 0x2f,
+ 0x00, 0x81, 0xfa, 0xe8,
+ 0x27, 0x38, 0x26, 0x1c,
+ 0x02, 0x1d, 0xf0, 0x91,
+ 0x15, 0xe9, 0xa1, 0xf5,
+ 0xe8, 0x27, 0xb9, 0x38,
+ 0x27, 0xba, 0x20, 0xb1,
+ 0x13, 0xe9, 0x27, 0xbb,
+ 0x0a, 0xc1, 0xee, 0xe8,
+ 0x27, 0x3c, 0x0a, 0x22,
+ 0xa0, 0x80, 0x1d, 0xf0,
+ 0xd1, 0xf0, 0xe8, 0xd7,
+ 0x12, 0x41, 0x0c, 0x02,
+ 0x1d, 0xf0, 0xe1, 0xd8,
+ 0xe8, 0xe7, 0x92, 0xf5,
+ 0x0c, 0x82, 0x1d, 0xf0,
+ 0xf1, 0x0b, 0xe9, 0x31,
+ 0xf4, 0xe8, 0x27, 0xbf,
+ 0x2e, 0x27, 0x33, 0x1b,
+ 0x22, 0xa0, 0x9b, 0x1d,
+ 0xf0, 0x41, 0x07, 0xe9,
+ 0x27, 0xb4, 0xde, 0x81,
+ 0xe0, 0xe8, 0x27, 0xb8,
+ 0x16, 0x91, 0xe1, 0xe8,
+ 0x97, 0x92, 0xce, 0x22,
+ 0xa2, 0x0a, 0x1d, 0xf0,
+ 0xa1, 0x03, 0xe9, 0x27,
+ 0xba, 0x7a, 0xb1, 0xeb,
+ 0xe8, 0x27, 0x3b, 0xbd,
+ 0x0c, 0x32, 0x1d, 0xf0,
+ 0xc1, 0x00, 0xe9, 0x27,
+ 0xbc, 0x0e, 0xd1, 0xe3,
+ 0xe8, 0x27, 0xbd, 0xef,
+ 0xe1, 0xe3, 0xe8, 0xe7,
+ 0x92, 0xa7, 0x46, 0xdf,
+ 0xff, 0xf1, 0xde, 0xe8,
+ 0xf7, 0x92, 0x9e, 0x0c,
+ 0x22, 0x1d, 0xf0, 0x31,
+ 0xf9, 0xe8, 0x27, 0xb3,
+ 0x31, 0x41, 0xd7, 0xe8,
+ 0x27, 0xb4, 0x27, 0x81,
+ 0xd7, 0xe8, 0x87, 0x92,
+ 0x88, 0x86, 0xd7, 0xff,
+ 0x91, 0xf5, 0xe8, 0x27,
+ 0xb9, 0x28, 0xa1, 0xba,
+ 0xe8, 0x27, 0xba, 0x12,
+ 0x50, 0xb2, 0xc0, 0x56,
+ 0x3b, 0xf7, 0x0c, 0x12,
+ 0x1d, 0xf0, 0xc1, 0xd0,
+ 0xe8, 0xc0, 0xc2, 0xc0,
+ 0x56, 0x6c, 0xf6, 0x2c,
+ 0x02, 0x1d, 0xf0, 0xd1,
+ 0xc1, 0xe8, 0xd0, 0xd2,
+ 0xc0, 0x56, 0x9d, 0xf5,
+ 0xc6, 0xcb, 0xff, 0xe1,
+ 0xd2, 0xe8, 0xe0, 0xe2,
+ 0xc0, 0x56, 0xde, 0xf4,
+ 0x22, 0xa0, 0x7e, 0x1d,
+ 0xf0, 0xf1, 0xaf, 0xe8,
+ 0xf0, 0xf2, 0xc0, 0x56,
+ 0xff, 0xf3, 0x46, 0xc5,
+ 0xff, 0x31, 0xe3, 0xe8,
+ 0x30, 0x32, 0xc0, 0x56,
+ 0x33, 0xf3, 0x22, 0xa0,
+ 0x83, 0x1d, 0xf0, 0x00,
+ 0x36, 0x41, 0x00, 0x51,
+ 0xe0, 0xe8, 0xc0, 0x20,
+ 0x00, 0x61, 0xfc, 0xe7,
+ 0x42, 0xc5, 0xd0, 0x42,
+ 0x04, 0xc1, 0x52, 0x05,
+ 0x6c, 0x60, 0x44, 0xa0,
+ 0x42, 0x24, 0x7f, 0x50,
+ 0x23, 0x93, 0x29, 0x44,
+ 0x1d, 0xf0, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0xa1,
+ 0x9a, 0xe8, 0x0c, 0x0b,
+ 0x81, 0xbe, 0xe8, 0xc0,
+ 0x92, 0x11, 0x9a, 0x88,
+ 0xb2, 0x68, 0x7f, 0x65,
+ 0x36, 0xfe, 0x1d, 0xf0,
+ 0x36, 0x41, 0x00, 0x0c,
+ 0x44, 0x51, 0xfc, 0xe7,
+ 0x71, 0x1e, 0xe8, 0x4c,
+ 0xc6, 0x60, 0x62, 0x82,
+ 0x32, 0x07, 0x80, 0x6a,
+ 0x55, 0x42, 0x65, 0x7f,
+ 0x27, 0x93, 0x15, 0x82,
+ 0x07, 0x7f, 0x0c, 0x09,
+ 0x8c, 0xd8, 0x92, 0x47,
+ 0x7e, 0x92, 0x47, 0x7f,
+ 0x92, 0x47, 0x80, 0x92,
+ 0x47, 0x81, 0x92, 0x47,
+ 0x82, 0x1d, 0xf0, 0x00,
+ 0x36, 0x41, 0x00, 0x61,
+ 0xc5, 0xe8, 0x92, 0xa5,
+ 0x20, 0x90, 0x92, 0xd1,
+ 0x81, 0xc4, 0xe8, 0x9a,
+ 0x66, 0x22, 0x16, 0x7e,
+ 0x80, 0x43, 0x10, 0x80,
+ 0x52, 0x10, 0x57, 0x14,
+ 0x26, 0xb1, 0xc0, 0xe8,
+ 0xa2, 0x26, 0x3e, 0x52,
+ 0xa1, 0xe0, 0x42, 0xae,
+ 0x1f, 0x40, 0x43, 0x10,
+ 0x50, 0x22, 0x10, 0x40,
+ 0x22, 0x20, 0xb0, 0xaa,
+ 0x20, 0xa2, 0x66, 0x3e,
+ 0x22, 0x56, 0x7e, 0xc7,
+ 0xea, 0x05, 0x80, 0x92,
+ 0x10, 0x92, 0x56, 0x7e,
+ 0x1d, 0xf0, 0x00, 0x00,
+ 0x36, 0x81, 0x00, 0x0c,
+ 0x0a, 0x0c, 0x7b, 0xa5,
+ 0x27, 0x01, 0x16, 0xea,
+ 0x07, 0x0c, 0x04, 0x46,
+ 0x00, 0x00, 0x0c, 0x14,
+ 0x0c, 0x1b, 0x0c, 0x05,
+ 0x71, 0x0e, 0xe8, 0x61,
+ 0xc8, 0xe7, 0xf1, 0xb0,
+ 0xe8, 0xc1, 0xb0, 0xe8,
+ 0x31, 0xc2, 0xe7, 0x91,
+ 0xad, 0xe8, 0x30, 0x34,
+ 0x82, 0xe2, 0xc9, 0xfc,
+ 0xea, 0xe3, 0xa2, 0x0e,
+ 0x80, 0x0c, 0xe8, 0x87,
+ 0xba, 0x34, 0x91, 0xab,
+ 0xe8, 0xa0, 0x8a, 0x90,
+ 0x9a, 0x88, 0xa0, 0x08,
+ 0x00, 0xc6, 0x13, 0x00,
+ 0x46, 0xc3, 0x00, 0x86,
+ 0xba, 0x00, 0xc6, 0xa2,
+ 0x00, 0x86, 0x97, 0x00,
+ 0x46, 0x0b, 0x00, 0x46,
+ 0x7e, 0x00, 0x46, 0x73,
+ 0x00, 0x46, 0x68, 0x00,
+ 0x86, 0x55, 0x00, 0x46,
+ 0x49, 0x00, 0x86, 0x42,
+ 0x00, 0x06, 0x3d, 0x00,
+ 0x86, 0x33, 0x00, 0xa1,
+ 0x9f, 0xe8, 0xb2, 0xa5,
+ 0x20, 0xb0, 0xb2, 0xd1,
+ 0xba, 0xaa, 0xa2, 0xda,
+ 0x02, 0xa2, 0x0a, 0x20,
+ 0xa0, 0xa4, 0x41, 0xcc,
+ 0xfa, 0x6a, 0xc3, 0x52,
+ 0x6c, 0x7f, 0x1d, 0xf0,
+ 0x0c, 0x1a, 0x0c, 0x7b,
+ 0xe5, 0x1e, 0x01, 0x56,
+ 0xba, 0xf7, 0x1d, 0xf0,
+ 0x26, 0x14, 0x05, 0xd2,
+ 0x07, 0x80, 0x16, 0x3d,
+ 0xfe, 0xe1, 0xa7, 0xe7,
+ 0xf1, 0xa8, 0xe7, 0xe2,
+ 0x0e, 0xc1, 0xf0, 0xee,
+ 0xa0, 0xe2, 0x2e, 0x7f,
+ 0xad, 0x02, 0x59, 0x6e,
+ 0x65, 0x86, 0xfe, 0x7c,
+ 0xcb, 0x41, 0x8c, 0xe8,
+ 0xa1, 0x88, 0xe8, 0x82,
+ 0xa5, 0x20, 0x80, 0x82,
+ 0xd1, 0xaa, 0xa3, 0xa2,
+ 0x0a, 0x80, 0x8a, 0x44,
+ 0x92, 0x24, 0x88, 0xa0,
+ 0xc3, 0x04, 0xb0, 0x99,
+ 0x10, 0x80, 0xcc, 0x11,
+ 0xa0, 0xb0, 0x14, 0xb0,
+ 0x99, 0x20, 0xb2, 0xae,
+ 0xff, 0xb0, 0x99, 0x10,
+ 0xc0, 0x99, 0x20, 0xb1,
+ 0x82, 0xe8, 0xa0, 0xc5,
+ 0x04, 0x30, 0xcc, 0x11,
+ 0xb0, 0x99, 0x10, 0xb1,
+ 0x80, 0xe8, 0xc0, 0x99,
+ 0x20, 0xb0, 0x99, 0x10,
+ 0xa0, 0xb7, 0x04, 0x10,
+ 0xbb, 0x11, 0xb0, 0x99,
+ 0x20, 0x92, 0x64, 0x88,
+ 0x47, 0x6a, 0x09, 0xb2,
+ 0x07, 0x80, 0xcc, 0x3b,
+ 0x0c, 0x1d, 0xd2, 0x47,
+ 0x80, 0x72, 0xaf, 0x0f,
+ 0xa0, 0xe2, 0x04, 0xf2,
+ 0xa9, 0xff, 0xf0, 0x99,
+ 0x10, 0x92, 0x64, 0x88,
+ 0x16, 0x6e, 0x2b, 0x70,
+ 0x99, 0x10, 0x7c, 0x38,
+ 0x90, 0xa0, 0x14, 0xe0,
+ 0xaa, 0x11, 0x80, 0x89,
+ 0x10, 0xa0, 0x88, 0x20,
+ 0x82, 0x64, 0x88, 0x86,
+ 0xd1, 0xff, 0x26, 0x14,
+ 0x05, 0xb2, 0x07, 0x80,
+ 0x16, 0xdb, 0xf3, 0xd1,
+ 0x4d, 0xe8, 0xf2, 0xa5,
+ 0x20, 0xf0, 0xf2, 0xd1,
+ 0xe1, 0x6a, 0xe8, 0xfa,
+ 0xdd, 0xc2, 0x2d, 0x1e,
+ 0xe0, 0xcc, 0x20, 0xc2,
+ 0x6d, 0x1e, 0xc6, 0xc8,
+ 0xff, 0x0b, 0x84, 0x56,
+ 0xe8, 0xf1, 0xa2, 0xdc,
+ 0xfc, 0xa2, 0xca, 0xf0,
+ 0xaa, 0xa3, 0x65, 0x64,
+ 0xfe, 0x06, 0xc4, 0xff,
+ 0xad, 0x04, 0x0c, 0xbc,
+ 0xb1, 0x61, 0xe8, 0x0c,
+ 0x7d, 0xba, 0xb3, 0x52,
+ 0x4b, 0x80, 0x52, 0x66,
+ 0x7f, 0x0c, 0x1b, 0xa5,
+ 0xe6, 0x00, 0x1d, 0xf0,
+ 0x26, 0x14, 0x05, 0xc2,
+ 0x07, 0x80, 0x16, 0xfc,
+ 0xee, 0xd1, 0x5a, 0xe8,
+ 0xe1, 0x51, 0xe8, 0xf2,
+ 0xa5, 0x20, 0xf0, 0xf2,
+ 0xd1, 0xea, 0xe3, 0xe2,
+ 0x0e, 0x80, 0xfa, 0xdd,
+ 0xd2, 0xdd, 0x02, 0xe0,
+ 0xe0, 0x04, 0xd2, 0xcd,
+ 0x80, 0xb2, 0x4d, 0x84,
+ 0xe2, 0x4d, 0x85, 0x86,
+ 0xb2, 0xff, 0xa2, 0xa5,
+ 0x20, 0xa0, 0xa2, 0xd1,
+ 0x21, 0x50, 0xe8, 0x2a,
+ 0x2a, 0x66, 0x14, 0x15,
+ 0xb2, 0xdc, 0xf4, 0xb2,
+ 0xcb, 0x50, 0xba, 0xba,
+ 0xa2, 0xcc, 0xf0, 0xaa,
+ 0xa3, 0xc2, 0x22, 0x7f,
+ 0xa5, 0x00, 0x03, 0x06,
+ 0x04, 0x00, 0xd2, 0xcc,
+ 0xf0, 0xda, 0xd3, 0x52,
+ 0x4d, 0x00, 0x52, 0x4d,
+ 0x01, 0x52, 0x4d, 0x02,
+ 0x52, 0x4d, 0x03, 0xad,
+ 0x04, 0xb2, 0x22, 0x7f,
+ 0x0c, 0x9c, 0x0c, 0x7d,
+ 0x6a, 0xe3, 0x52, 0x6e,
+ 0x7f, 0x25, 0xdf, 0x00,
+ 0x1d, 0xf0, 0x0b, 0x84,
+ 0x16, 0x88, 0x17, 0x92,
+ 0x07, 0x80, 0x56, 0x29,
+ 0x17, 0xbd, 0x05, 0xa2,
+ 0xcc, 0xf0, 0xaa, 0xa3,
+ 0x3c, 0x5c, 0x25, 0x10,
+ 0x03, 0xad, 0x04, 0x0c,
+ 0x8c, 0x6a, 0xb3, 0x0c,
+ 0x7d, 0x52, 0x6b, 0x7f,
+ 0x3c, 0x5b, 0xa5, 0xdc,
+ 0x00, 0x1d, 0xf0, 0x0b,
+ 0xd4, 0x16, 0x0d, 0x19,
+ 0xe2, 0x07, 0x80, 0x56,
+ 0xae, 0x18, 0xbd, 0x05,
+ 0xa2, 0xcc, 0xf0, 0xaa,
+ 0xa3, 0x0c, 0x5c, 0xa5,
+ 0x0d, 0x03, 0xad, 0x04,
+ 0x0c, 0x7c, 0x6a, 0xb3,
+ 0x0c, 0x7d, 0x52, 0x6b,
+ 0x7f, 0x0c, 0x5b, 0x25,
+ 0xda, 0x00, 0x1d, 0xf0,
+ 0x26, 0x14, 0x04, 0xd2,
+ 0x07, 0x80, 0xbc, 0x7d,
+ 0x81, 0x24, 0xe8, 0x91,
+ 0x07, 0xe8, 0xf1, 0x26,
+ 0xe8, 0xe2, 0xa5, 0x20,
+ 0xe0, 0xe2, 0xd1, 0xfa,
+ 0xf3, 0x9a, 0x9e, 0x8a,
+ 0xee, 0xe2, 0xde, 0x02,
+ 0x82, 0x19, 0x40, 0x82,
+ 0x4f, 0x84, 0xe2, 0x1e,
+ 0x12, 0x92, 0x09, 0x7e,
+ 0x92, 0x4f, 0x82, 0xe2,
+ 0x4f, 0x81, 0x80, 0x88,
+ 0x21, 0x82, 0x4f, 0x83,
+ 0xe0, 0xe8, 0x21, 0xe2,
+ 0x4f, 0x80, 0xc6, 0x02,
+ 0x00, 0xbd, 0x05, 0xa2,
+ 0xcc, 0xf0, 0xaa, 0xa3,
+ 0x0c, 0x5c, 0xa5, 0x07,
+ 0x03, 0xad, 0x04, 0x0c,
+ 0x6c, 0x6a, 0xb3, 0x0c,
+ 0x7d, 0x52, 0x6b, 0x7f,
+ 0x0c, 0x5b, 0x25, 0xd4,
+ 0x00, 0x1d, 0xf0, 0x0b,
+ 0xc4, 0x56, 0xcc, 0xdc,
+ 0xa1, 0xa0, 0xe7, 0x21,
+ 0x1e, 0xe7, 0x0c, 0x5c,
+ 0x2a, 0x23, 0xb2, 0xd2,
+ 0x11, 0xb2, 0xcb, 0xf0,
+ 0xa5, 0xf1, 0x02, 0xa1,
+ 0x89, 0xe7, 0xc2, 0xa1,
+ 0x18, 0xb2, 0xd2, 0x11,
+ 0xb2, 0xcb, 0xf5, 0xe5,
+ 0xf0, 0x02, 0xc6, 0x69,
+ 0xff, 0x26, 0x14, 0x05,
+ 0x82, 0x07, 0x80, 0x16,
+ 0xe8, 0xd9, 0x92, 0x0e,
+ 0x83, 0x4c, 0xc4, 0xa2,
+ 0x0e, 0x82, 0x40, 0x42,
+ 0xd1, 0x21, 0x04, 0xe8,
+ 0x80, 0xaa, 0x11, 0xa0,
+ 0x99, 0x20, 0x2a, 0x24,
+ 0x90, 0x90, 0xf4, 0x16,
+ 0x49, 0x07, 0xb1, 0xc3,
+ 0xe7, 0x0c, 0x4c, 0xba,
+ 0xa4, 0xb2, 0xcb, 0x7c,
+ 0xba, 0xb3, 0x65, 0xed,
+ 0x02, 0xc2, 0x07, 0x80,
+ 0x9c, 0x9c, 0xa1, 0x50,
+ 0xe7, 0x1c, 0x0d, 0xc1,
+ 0xfb, 0xe7, 0xb1, 0x05,
+ 0xe7, 0x0c, 0x0e, 0xca,
+ 0xcb, 0xca, 0xc4, 0xb2,
+ 0xdb, 0x11, 0x5b, 0xbb,
+ 0xba, 0xb3, 0x65, 0x40,
+ 0xfe, 0x0c, 0x1b, 0x52,
+ 0x42, 0x7e, 0x06, 0x10,
+ 0x00, 0x0b, 0xd4, 0x56,
+ 0x6d, 0xd4, 0xad, 0x02,
+ 0xb2, 0xdc, 0xeb, 0xba,
+ 0xb3, 0xc2, 0xdb, 0x11,
+ 0xb2, 0xcc, 0xf0, 0x8b,
+ 0xdc, 0xe2, 0xcc, 0x18,
+ 0xf2, 0xcc, 0x20, 0x25,
+ 0x54, 0xfe, 0xc6, 0x4a,
+ 0xff, 0x0b, 0xc4, 0x56,
+ 0x6c, 0xd2, 0xb1, 0xf5,
+ 0xe6, 0xad, 0x02, 0xba,
+ 0xb3, 0xc2, 0xdb, 0x12,
+ 0xc2, 0xcc, 0x70, 0xb2,
+ 0xdb, 0x11, 0xb2, 0xcb,
+ 0xf0, 0xe5, 0x57, 0xfe,
+ 0x46, 0x43, 0xff, 0xb2,
+ 0x42, 0x7e, 0xb2, 0x42,
+ 0x7f, 0x06, 0x41, 0xff,
+ 0x71, 0xe2, 0xe7, 0x3c,
+ 0x5c, 0xb1, 0xeb, 0xe6,
+ 0x4c, 0xcd, 0xd0, 0xd2,
+ 0xd1, 0xba, 0xa3, 0xa9,
+ 0x51, 0xda, 0xbb, 0xb9,
+ 0x41, 0xfa, 0xaa, 0xb2,
+ 0xdb, 0x10, 0xb2, 0xcb,
+ 0x74, 0x65, 0xe4, 0x02,
+ 0x28, 0x51, 0xad, 0x01,
+ 0xb8, 0x41, 0x1c, 0x0c,
+ 0x7a, 0xbb, 0xa5, 0xe3,
+ 0x02, 0xa1, 0x7d, 0xe7,
+ 0xbd, 0x01, 0x1c, 0x0d,
+ 0x0c, 0x1e, 0xc2, 0xd2,
+ 0x15, 0x5b, 0xcc, 0xa5,
+ 0x37, 0xfe, 0xc6, 0x95,
+ 0xff, 0xb1, 0xdc, 0xe6,
+ 0xc2, 0xa2, 0x6e, 0xc0,
+ 0xc2, 0xd1, 0xfa, 0xab,
+ 0xca, 0xbb, 0xaa, 0xa3,
+ 0x0c, 0x5c, 0xb2, 0xdb,
+ 0x49, 0xb2, 0xcb, 0xb0,
+ 0xa5, 0xe0, 0x02, 0xc6,
+ 0x98, 0xff, 0xad, 0x02,
+ 0x65, 0x3d, 0x00, 0x92,
+ 0x24, 0x88, 0x1c, 0x0a,
+ 0x70, 0x99, 0x10, 0xa0,
+ 0x99, 0x20, 0x06, 0x4e,
+ 0xff, 0x00, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0x81,
+ 0xc5, 0xe7, 0x61, 0xbf,
+ 0xe7, 0x42, 0x28, 0x7f,
+ 0x52, 0xc8, 0x78, 0x27,
+ 0x64, 0x18, 0x7c, 0xb9,
+ 0x72, 0xa5, 0x20, 0x70,
+ 0x72, 0xd1, 0x90, 0x44,
+ 0x10, 0x7a, 0x55, 0x32,
+ 0x25, 0x7f, 0x42, 0x68,
+ 0x7f, 0x60, 0x33, 0x20,
+ 0x32, 0x65, 0x7f, 0x17,
+ 0xe4, 0x03, 0x0c, 0x02,
+ 0x1d, 0xf0, 0x0c, 0x12,
+ 0x7c, 0xd9, 0x90, 0x94,
+ 0x10, 0x92, 0x68, 0x7f,
+ 0x1d, 0xf0, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0x81,
+ 0xa6, 0xe7, 0x92, 0xa5,
+ 0x20, 0x90, 0x92, 0xd1,
+ 0xb1, 0xb4, 0xe7, 0x9a,
+ 0x28, 0x52, 0x12, 0x7e,
+ 0x30, 0x40, 0xf4, 0x50,
+ 0x55, 0x41, 0x57, 0x14,
+ 0x0e, 0xb0, 0xc3, 0x11,
+ 0xa2, 0x22, 0x3e, 0xc2,
+ 0x52, 0x7e, 0xb0, 0xaa,
+ 0x20, 0xa2, 0x62, 0x3e,
+ 0x1d, 0xf0, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0x91,
+ 0xb3, 0xe6, 0x20, 0x82,
+ 0xf0, 0x90, 0x88, 0xa0,
+ 0xc0, 0x20, 0x00, 0x82,
+ 0x08, 0x08, 0xcc, 0x48,
+ 0xe5, 0x67, 0x01, 0x26,
+ 0x1a, 0x03, 0x0c, 0x02,
+ 0x1d, 0xf0, 0x0c, 0x12,
+ 0x1d, 0xf0, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0xad,
+ 0x02, 0x0c, 0x9b, 0x25,
+ 0xdf, 0x00, 0x16, 0xca,
+ 0x06, 0xd1, 0xa7, 0xe6,
+ 0x0c, 0x04, 0xb1, 0xa4,
+ 0xe6, 0xa1, 0x52, 0xe7,
+ 0xb0, 0xb2, 0x82, 0x31,
+ 0xa6, 0xe6, 0xaa, 0x9b,
+ 0x92, 0x09, 0x80, 0x3a,
+ 0x3b, 0xbc, 0xc9, 0x26,
+ 0x19, 0x04, 0x42, 0x63,
+ 0x7f, 0x1d, 0xf0, 0x66,
+ 0x12, 0xf7, 0xc1, 0x04,
+ 0xe7, 0xda, 0xdb, 0xa2,
+ 0xdd, 0x0f, 0xa2, 0xca,
+ 0xf4, 0xb2, 0xcc, 0x10,
+ 0xe2, 0x2a, 0x7f, 0x4b,
+ 0xaa, 0xe2, 0x6c, 0x7f,
+ 0x4b, 0xcc, 0xb7, 0x9c,
+ 0xf2, 0xc1, 0x8f, 0xe7,
+ 0xa2, 0xdd, 0x0f, 0x4b,
+ 0xaa, 0xd2, 0x2a, 0x7f,
+ 0x4b, 0xaa, 0xd2, 0x6b,
+ 0x7f, 0x4b, 0xbb, 0xc7,
+ 0x9b, 0xf2, 0x06, 0xf1,
+ 0xff, 0x66, 0x12, 0xc1,
+ 0xa2, 0xca, 0xe4, 0xe1,
+ 0x89, 0xe7, 0x1c, 0x0c,
+ 0xea, 0xed, 0xea, 0xbb,
+ 0x65, 0xce, 0x02, 0xc6,
+ 0xeb, 0xff, 0x1d, 0xf0,
+ 0x36, 0x61, 0x00, 0x41,
+ 0x5b, 0xe7, 0xa2, 0x24,
+ 0x1e, 0xa5, 0xf7, 0xff,
+ 0xad, 0x02, 0x25, 0xf5,
+ 0xff, 0x0c, 0x05, 0x71,
+ 0x8a, 0xe6, 0x81, 0x27,
+ 0xe7, 0x32, 0xa5, 0x20,
+ 0x30, 0x32, 0xd1, 0x39,
+ 0x01, 0x8a, 0x33, 0x92,
+ 0x23, 0x7f, 0x61, 0x86,
+ 0xe6, 0x90, 0x94, 0x34,
+ 0x56, 0x1a, 0x05, 0x0b,
+ 0xa9, 0x16, 0xea, 0x0a,
+ 0xb2, 0x07, 0xc1, 0x60,
+ 0xbb, 0xa0, 0xb2, 0x2b,
+ 0x7f, 0xb8, 0x6b, 0x66,
+ 0x2b, 0x49, 0xad, 0x02,
+ 0x0c, 0x7b, 0xa5, 0xee,
+ 0xff, 0xe1, 0x79, 0xe6,
+ 0x20, 0xd2, 0xf0, 0xe0,
+ 0xdd, 0xa0, 0xc0, 0x20,
+ 0x00, 0xc2, 0x04, 0x84,
+ 0x52, 0x4d, 0x08, 0x27,
+ 0x9c, 0x13, 0xf2, 0x04,
+ 0x83, 0x8c, 0xdf, 0x52,
+ 0x44, 0x82, 0x52, 0x44,
+ 0x83, 0x52, 0x44, 0x84,
+ 0x52, 0x44, 0x85, 0x52,
+ 0x44, 0x86, 0x92, 0x23,
+ 0x7f, 0xa2, 0xaf, 0x0f,
+ 0xa0, 0x99, 0x10, 0x92,
+ 0x63, 0x7f, 0x90, 0x94,
+ 0x34, 0xb2, 0x07, 0xc1,
+ 0x60, 0xbb, 0xa0, 0xb2,
+ 0x2b, 0x7f, 0x59, 0x6b,
+ 0x26, 0x19, 0x53, 0xad,
+ 0x02, 0xe5, 0xe5, 0xff,
+ 0x16, 0xba, 0x04, 0xad,
+ 0x02, 0x0c, 0x1b, 0x65,
+ 0xe9, 0xff, 0xd1, 0x64,
+ 0xe6, 0x20, 0xc2, 0xf0,
+ 0xd0, 0xcc, 0xa0, 0xc0,
+ 0x20, 0x00, 0x52, 0x4c,
+ 0x08, 0xad, 0x02, 0x65,
+ 0x20, 0x00, 0xe2, 0x04,
+ 0x84, 0x82, 0x07, 0xc1,
+ 0x92, 0x23, 0x7f, 0xa2,
+ 0xaf, 0x0f, 0xa0, 0x99,
+ 0x10, 0x60, 0x88, 0xa0,
+ 0x82, 0x28, 0x7f, 0x27,
+ 0x9e, 0x13, 0xf2, 0x04,
+ 0x83, 0x8c, 0xdf, 0x52,
+ 0x44, 0x82, 0x52, 0x44,
+ 0x83, 0x52, 0x44, 0x84,
+ 0x52, 0x44, 0x85, 0x52,
+ 0x44, 0x86, 0x59, 0x68,
+ 0x92, 0x63, 0x7f, 0xad,
+ 0x02, 0x65, 0xa1, 0xff,
+ 0x92, 0x23, 0x7f, 0x90,
+ 0xa4, 0x34, 0x0b, 0xba,
+ 0x16, 0xab, 0x0b, 0x16,
+ 0x1a, 0x0c, 0x26, 0x2a,
+ 0x48, 0x26, 0x3a, 0x5a,
+ 0x66, 0x4a, 0x15, 0x90,
+ 0xc2, 0x14, 0x66, 0x1c,
+ 0x07, 0xad, 0x02, 0xa5,
+ 0xf1, 0xfe, 0x06, 0x01,
+ 0x00, 0xad, 0x02, 0xe5,
+ 0x35, 0xfe, 0x92, 0x23,
+ 0x7f, 0xb7, 0xe9, 0x02,
+ 0xc7, 0x69, 0x24, 0x1c,
+ 0x0f, 0x82, 0xa0, 0xa0,
+ 0xc0, 0x20, 0x00, 0xf9,
+ 0x08, 0xd1, 0xe4, 0xe6,
+ 0xe2, 0x24, 0x22, 0xd0,
+ 0xd9, 0x10, 0xf0, 0xee,
+ 0x20, 0xe2, 0x64, 0x22,
+ 0xe1, 0xe2, 0xe6, 0xd2,
+ 0x63, 0x7f, 0xe0, 0xdd,
+ 0x10, 0xd2, 0x63, 0x7f,
+ 0x1d, 0xf0, 0x90, 0xa0,
+ 0x14, 0x66, 0x1a, 0x2b,
+ 0x7c, 0x3b, 0x0c, 0x4a,
+ 0xb0, 0x99, 0x10, 0xa0,
+ 0x99, 0x20, 0x4c, 0x0a,
+ 0x46, 0x03, 0x00, 0xad,
+ 0x02, 0xe5, 0x6c, 0xff,
+ 0x92, 0x23, 0x7f, 0xa0,
+ 0xa0, 0x34, 0xc0, 0xaa,
+ 0x11, 0xb2, 0xaf, 0x0f,
+ 0xb0, 0x99, 0x10, 0xa0,
+ 0x99, 0x20, 0x92, 0x63,
+ 0x7f, 0x06, 0xe8, 0xff,
+ 0xad, 0x02, 0xa5, 0xde,
+ 0xff, 0x16, 0x5a, 0xf9,
+ 0xa1, 0xec, 0xe6, 0xa5,
+ 0x75, 0xff, 0x5d, 0x0a,
+ 0xad, 0x02, 0xa5, 0x73,
+ 0xff, 0x50, 0xb0, 0xf4,
+ 0xc1, 0xe8, 0xe6, 0xe8,
+ 0x01, 0xdd, 0x0a, 0xf1,
+ 0x27, 0xe6, 0xad, 0x02,
+ 0xd0, 0xd0, 0xf4, 0xf2,
+ 0xdf, 0x07, 0xf2, 0xcf,
+ 0xd0, 0xfa, 0xee, 0x25,
+ 0x6c, 0xff, 0x3c, 0x0a,
+ 0x92, 0x23, 0x7f, 0x86,
+ 0xed, 0xff, 0xad, 0x02,
+ 0x0c, 0x0b, 0x25, 0x90,
+ 0xff, 0x46, 0xd6, 0xff,
+ 0xad, 0x02, 0x65, 0x8c,
+ 0xff, 0xad, 0x02, 0xa5,
+ 0x8a, 0xff, 0xa2, 0xa0,
+ 0x64, 0x0c, 0xab, 0xe5,
+ 0x87, 0xff, 0x2c, 0x0a,
+ 0x06, 0xf6, 0xff, 0x00,
+ 0x36, 0x41, 0x00, 0x41,
+ 0x1b, 0xe6, 0x31, 0x19,
+ 0xe6, 0x0c, 0x18, 0x32,
+ 0x03, 0xc1, 0x40, 0x33,
+ 0xa0, 0x32, 0x23, 0x7f,
+ 0x0c, 0x02, 0x48, 0x83,
+ 0x29, 0x43, 0x80, 0x44,
+ 0x20, 0x49, 0x83, 0x1d,
+ 0xf0, 0x00, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0x61,
+ 0x08, 0xe7, 0x7d, 0x02,
+ 0x62, 0x06, 0x80, 0x0c,
+ 0x02, 0x9c, 0x66, 0x81,
+ 0x0f, 0xe6, 0x80, 0x52,
+ 0xa0, 0x52, 0x25, 0x7f,
+ 0x8c, 0x35, 0x98, 0x35,
+ 0x77, 0x19, 0x0a, 0x1b,
+ 0x22, 0x20, 0x20, 0x74,
+ 0x27, 0x96, 0xea, 0x22,
+ 0xa0, 0xff, 0x1d, 0xf0,
+ 0x36, 0x41, 0x00, 0xc0,
+ 0x20, 0x00, 0x39, 0x02,
+ 0x1d, 0xf0, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0xad,
+ 0x02, 0x25, 0xfc, 0xff,
+ 0x82, 0xa0, 0xff, 0x87,
+ 0x1a, 0x3b, 0xd1, 0x01,
+ 0xe6, 0xc1, 0xf6, 0xe6,
+ 0xd0, 0x9a, 0xa0, 0x92,
+ 0x29, 0x7f, 0xb2, 0x0c,
+ 0x80, 0xac, 0x99, 0x0b,
+ 0xfb, 0xf7, 0xaa, 0x15,
+ 0xd0, 0xea, 0xa0, 0x1b,
+ 0xaa, 0xb2, 0x2e, 0x80,
+ 0xb2, 0x6e, 0x7f, 0xb2,
+ 0x0c, 0x80, 0xa0, 0xa0,
+ 0x74, 0x0b, 0x8b, 0x87,
+ 0x2a, 0xe9, 0x0c, 0x0f,
+ 0x0b, 0x8b, 0x80, 0x80,
+ 0x74, 0x82, 0x4c, 0x80,
+ 0xd0, 0x88, 0xa0, 0xf2,
+ 0x68, 0x7f, 0x1d, 0xf0,
+ 0x36, 0x41, 0x00, 0x52,
+ 0x02, 0x09, 0x2c, 0x49,
+ 0x97, 0x15, 0x29, 0x3c,
+ 0x9b, 0x2c, 0xf8, 0x0c,
+ 0x96, 0x0c, 0x1a, 0x0c,
+ 0x07, 0x1b, 0x66, 0x57,
+ 0xb8, 0x0f, 0x57, 0x3b,
+ 0x0c, 0x70, 0x7a, 0x82,
+ 0x0c, 0xaa, 0x7a, 0x75,
+ 0x72, 0xc7, 0xd0, 0x70,
+ 0x70, 0xf4, 0x2a, 0x56,
+ 0x52, 0x05, 0x00, 0x97,
+ 0x95, 0xe2, 0x46, 0x00,
+ 0x00, 0x0c, 0x07, 0x2d,
+ 0x07, 0x1d, 0xf0, 0x00,
+ 0x36, 0x41, 0x00, 0x31,
+ 0xd9, 0xe6, 0xc0, 0x20,
+ 0x00, 0x88, 0x03, 0xc0,
+ 0x20, 0x00, 0x38, 0x03,
+ 0xa1, 0x25, 0xe6, 0x30,
+ 0x30, 0x04, 0x16, 0xa3,
+ 0x09, 0x20, 0xb0, 0x74,
+ 0x0c, 0x09, 0x90, 0xbb,
+ 0x11, 0xc0, 0x20, 0x00,
+ 0xd8, 0x0a, 0xba, 0xdd,
+ 0xc0, 0x20, 0x00, 0x92,
+ 0x6d, 0x13, 0xc0, 0x20,
+ 0x00, 0xc8, 0x0a, 0xba,
+ 0xcc, 0xc0, 0x20, 0x00,
+ 0x92, 0x6c, 0x11, 0xc0,
+ 0x20, 0x00, 0x88, 0x0a,
+ 0xba, 0x88, 0xc0, 0x20,
+ 0x00, 0x99, 0x38, 0xc0,
+ 0x20, 0x00, 0x68, 0x0a,
+ 0xba, 0x66, 0xc0, 0x20,
+ 0x00, 0x99, 0xb6, 0xc0,
+ 0x20, 0x00, 0x58, 0x0a,
+ 0xba, 0x55, 0xc0, 0x20,
+ 0x00, 0x99, 0xf5, 0xc0,
+ 0x20, 0x00, 0x48, 0x0a,
+ 0xba, 0x44, 0xc0, 0x20,
+ 0x00, 0x92, 0x64, 0x10,
+ 0xc0, 0x20, 0x00, 0x38,
+ 0x0a, 0xba, 0x33, 0xc0,
+ 0x20, 0x00, 0x99, 0x43,
+ 0xc0, 0x20, 0x00, 0xf8,
+ 0x0a, 0xba, 0xff, 0xc0,
+ 0x20, 0x00, 0x99, 0x5f,
+ 0xc0, 0x20, 0x00, 0xe8,
+ 0x0a, 0xba, 0xee, 0xc0,
+ 0x20, 0x00, 0x99, 0x6e,
+ 0xc0, 0x20, 0x00, 0xd8,
+ 0x0a, 0xba, 0xdd, 0xc0,
+ 0x20, 0x00, 0x99, 0x7d,
+ 0xc0, 0x20, 0x00, 0xc8,
+ 0x0a, 0xba, 0xcc, 0xc0,
+ 0x20, 0x00, 0x99, 0x8c,
+ 0xc0, 0x20, 0x00, 0xa8,
+ 0x0a, 0xba, 0xaa, 0xc0,
+ 0x20, 0x00, 0x99, 0x9a,
+ 0x1d, 0xf0, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0x31,
+ 0xac, 0xe6, 0xc0, 0x20,
+ 0x00, 0x22, 0x23, 0x7f,
+ 0x1b, 0x22, 0xc0, 0x20,
+ 0x00, 0x22, 0x63, 0x7f,
+ 0x1d, 0xf0, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0x80,
+ 0x6f, 0x00, 0x60, 0x6d,
+ 0x03, 0x8c, 0xd6, 0x92,
+ 0xae, 0xff, 0xa2, 0xa2,
+ 0x00, 0xa0, 0x66, 0x20,
+ 0x90, 0x66, 0x10, 0x60,
+ 0x6d, 0x61, 0x78, 0x02,
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+ 0xf0, 0x1d, 0xf0, 0x32,
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+ 0x86, 0x92, 0x0b, 0x85,
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+ 0x99, 0x11, 0x80, 0x33,
+ 0x20, 0x82, 0x0b, 0x84,
+ 0x0c, 0x1b, 0x80, 0x88,
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+ 0x80, 0x33, 0x20, 0xad,
+ 0x03, 0x65, 0x65, 0x00,
+ 0x16, 0xda, 0xfc, 0xb2,
+ 0x04, 0x81, 0xa2, 0x04,
+ 0x82, 0x92, 0x04, 0x83,
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+ 0x99, 0x20, 0xa2, 0x04,
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+ 0xaa, 0x20, 0xa0, 0x99,
+ 0x20, 0xc0, 0x20, 0x00,
+ 0x99, 0x03, 0xc6, 0xe9,
+ 0xff, 0x32, 0x0b, 0x87,
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+ 0x0b, 0x85, 0x80, 0x88,
+ 0x11, 0x00, 0x99, 0x11,
+ 0x80, 0x33, 0x20, 0x82,
+ 0x0b, 0x84, 0x0c, 0x1b,
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+ 0x20, 0xad, 0x03, 0xa5,
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+ 0xfa, 0xc0, 0xc6, 0xc0,
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+ 0x80, 0xee, 0x11, 0xe0,
+ 0xbb, 0x20, 0xd0, 0xcc,
+ 0x20, 0xc0, 0xbb, 0x20,
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+ 0x99, 0x20, 0xc0, 0x20,
+ 0x00, 0x99, 0x03, 0x86,
+ 0xcb, 0xff, 0x32, 0x0b,
+ 0x87, 0x82, 0x0b, 0x86,
+ 0x92, 0x0b, 0x85, 0x80,
+ 0x88, 0x11, 0x00, 0x99,
+ 0x11, 0x80, 0x33, 0x20,
+ 0x82, 0x0b, 0x84, 0x0c,
+ 0x1b, 0x80, 0x88, 0x01,
+ 0x90, 0x88, 0x20, 0x80,
+ 0x33, 0x20, 0xad, 0x03,
+ 0xe5, 0x58, 0x00, 0x9d,
+ 0x0a, 0xa1, 0xd9, 0xe5,
+ 0x16, 0xa9, 0x30, 0xc0,
+ 0x20, 0x00, 0xb8, 0x03,
+ 0xc0, 0x20, 0x00, 0xb9,
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+ 0x92, 0x4a, 0x80, 0x82,
+ 0x04, 0x7d, 0x82, 0x4a,
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+ 0x04, 0x7f, 0xe2, 0x4a,
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+ 0xd8, 0x01, 0xd0, 0xd8,
+ 0x75, 0xd2, 0x4a, 0x84,
+ 0xc0, 0x20, 0x00, 0xc8,
+ 0x01, 0xc0, 0xc0, 0xf5,
+ 0xc2, 0x4a, 0x85, 0xc0,
+ 0x20, 0x00, 0xb8, 0x01,
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+ 0x4a, 0x86, 0xc0, 0x20,
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+ 0x0c, 0xad, 0x0c, 0x1a,
+ 0x0c, 0x8b, 0xe5, 0x34,
+ 0x00, 0x06, 0xaa, 0xff,
+ 0x0c, 0x4d, 0x9d, 0x0c,
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+ 0x0c, 0x80, 0xc1, 0x86,
+ 0xe5, 0x27, 0x6b, 0x0e,
+ 0xc0, 0x20, 0x00, 0xa2,
+ 0x4c, 0x6c, 0xd2, 0x44,
+ 0x80, 0xb2, 0x09, 0x80,
+ 0x46, 0x01, 0x00, 0xc0,
+ 0x20, 0x00, 0x22, 0x4c,
+ 0x6c, 0xb0, 0x90, 0x04,
+ 0x07, 0x6b, 0x0e, 0xc2,
+ 0x03, 0xab, 0xa9, 0x21,
+ 0xcc, 0x6c, 0xa5, 0xc5,
+ 0xff, 0xa8, 0x21, 0x86,
+ 0x03, 0x00, 0xcc, 0xb9,
+ 0xd2, 0x03, 0xab, 0xa9,
+ 0x21, 0x66, 0x1d, 0x04,
+ 0x25, 0xbe, 0xff, 0xa8,
+ 0x21, 0xe2, 0x03, 0xab,
+ 0x66, 0x1e, 0x08, 0xf2,
+ 0x04, 0x80, 0xa0, 0xff,
+ 0x20, 0xf2, 0x44, 0x80,
+ 0xbd, 0x07, 0x0c, 0x0a,
+ 0x0c, 0x1c, 0x0c, 0xad,
+ 0x65, 0x2e, 0x00, 0x46,
+ 0x76, 0xff, 0x1c, 0x1c,
+ 0x0c, 0xad, 0x91, 0xa8,
+ 0xe5, 0xbd, 0x0a, 0x82,
+ 0x03, 0x68, 0x0c, 0x0a,
+ 0x82, 0x49, 0x70, 0x25,
+ 0x2d, 0x00, 0x86, 0x70,
+ 0xff, 0xa1, 0xa5, 0xe5,
+ 0xb1, 0xa4, 0xe5, 0x29,
+ 0x0a, 0x29, 0x0b, 0x00,
+ 0x00, 0x00, 0x0d, 0xf0,
+ 0x06, 0x6c, 0xff, 0x92,
+ 0x0c, 0x81, 0x82, 0x0c,
+ 0x82, 0x72, 0x0c, 0x83,
+ 0x80, 0x88, 0x11, 0x80,
+ 0x77, 0x20, 0x82, 0x0c,
+ 0x80, 0x00, 0x99, 0x11,
+ 0x80, 0x88, 0x01, 0x90,
+ 0x88, 0x20, 0x80, 0x77,
+ 0x20, 0x92, 0x0c, 0x84,
+ 0xc2, 0x0c, 0x85, 0x0b,
+ 0xd9, 0x16, 0x4d, 0x24,
+ 0xa2, 0xc9, 0xfe, 0x56,
+ 0x1a, 0xd8, 0xbd, 0x07,
+ 0xa1, 0x96, 0xe5, 0xe5,
+ 0xb1, 0xff, 0xb1, 0xbb,
+ 0xe4, 0xc0, 0x20, 0x00,
+ 0xb8, 0x2b, 0xb2, 0x44,
+ 0x80, 0xc6, 0x5a, 0xff,
+ 0xe2, 0x0c, 0x85, 0xd2,
+ 0x0c, 0x86, 0xb2, 0x0c,
+ 0x87, 0x80, 0xdd, 0x11,
+ 0xd0, 0xbb, 0x20, 0xd2,
+ 0x0c, 0x82, 0xa2, 0x0c,
+ 0x83, 0x80, 0xdd, 0x11,
+ 0xd0, 0xaa, 0x20, 0xd2,
+ 0x0c, 0x84, 0x00, 0xee,
+ 0x11, 0x80, 0xdd, 0x01,
+ 0xe0, 0xdd, 0x20, 0xd0,
+ 0xbb, 0x20, 0xe2, 0x0c,
+ 0x81, 0xc2, 0x0c, 0x80,
+ 0x00, 0xee, 0x11, 0x80,
+ 0xcc, 0x01, 0xe0, 0xcc,
+ 0x20, 0xc0, 0xaa, 0x20,
+ 0x65, 0x6e, 0x01, 0x46,
+ 0x4a, 0xff, 0x81, 0x61,
+ 0xe4, 0xe2, 0x0c, 0x83,
+ 0x92, 0x0c, 0x80, 0xa2,
+ 0x0c, 0x81, 0xf2, 0x0c,
+ 0x82, 0x00, 0xaa, 0x11,
+ 0x80, 0xff, 0x11, 0x80,
+ 0x99, 0x01, 0xfa, 0xee,
+ 0xf1, 0x5a, 0xe4, 0xaa,
+ 0x99, 0xf2, 0x0f, 0xc1,
+ 0x9a, 0xee, 0x80, 0xff,
+ 0xa0, 0xf2, 0x2f, 0x7f,
+ 0xe2, 0x63, 0x2b, 0xe9,
+ 0x4f, 0xc6, 0x3d, 0xff,
+ 0xc9, 0x11, 0x0c, 0x0b,
+ 0x92, 0x0c, 0x81, 0x82,
+ 0x0c, 0x82, 0x72, 0x0c,
+ 0x83, 0x80, 0x88, 0x11,
+ 0x80, 0x77, 0x20, 0x82,
+ 0x0c, 0x80, 0x00, 0x99,
+ 0x11, 0x80, 0x88, 0x01,
+ 0x90, 0x88, 0x20, 0x80,
+ 0x77, 0x20, 0xad, 0x07,
+ 0xe5, 0x3b, 0x00, 0x16,
+ 0x9a, 0x15, 0xc0, 0x20,
+ 0x00, 0x88, 0x07, 0xc0,
+ 0x20, 0x00, 0xc8, 0x11,
+ 0x89, 0x01, 0xf2, 0x0c,
+ 0x80, 0xf2, 0x44, 0x80,
+ 0xe2, 0x0c, 0x81, 0xe2,
+ 0x44, 0x81, 0xd2, 0x0c,
+ 0x82, 0xd2, 0x44, 0x82,
+ 0xc2, 0x0c, 0x83, 0xc2,
+ 0x44, 0x83, 0xc0, 0x20,
+ 0x00, 0xb8, 0x01, 0xb0,
+ 0xb8, 0x75, 0xb2, 0x44,
+ 0x84, 0xc0, 0x20, 0x00,
+ 0xa8, 0x01, 0xa0, 0xa0,
+ 0xf5, 0xa2, 0x44, 0x85,
+ 0xc0, 0x20, 0x00, 0x98,
+ 0x01, 0x90, 0x98, 0x41,
+ 0x92, 0x44, 0x86, 0xc0,
+ 0x20, 0x00, 0xa8, 0x01,
+ 0x0c, 0x8b, 0x0c, 0x7c,
+ 0xa2, 0x44, 0x87, 0x0c,
+ 0xad, 0x0c, 0x0a, 0x25,
+ 0x18, 0x00, 0x86, 0x1c,
+ 0xff, 0x0c, 0x0b, 0x4d,
+ 0x0c, 0x92, 0x04, 0x81,
+ 0x82, 0x04, 0x82, 0x72,
+ 0x04, 0x83, 0x80, 0x88,
+ 0x11, 0x80, 0x77, 0x20,
+ 0x82, 0x04, 0x80, 0x00,
+ 0x99, 0x11, 0x80, 0x88,
+ 0x01, 0x90, 0x88, 0x20,
+ 0x80, 0x77, 0x20, 0xad,
+ 0x07, 0xa5, 0x33, 0x00,
+ 0x16, 0x8a, 0xc4, 0xc2,
+ 0x04, 0x85, 0xa2, 0x04,
+ 0x84, 0xc0, 0xb6, 0xc0,
+ 0xca, 0xaa, 0x00, 0x1b,
+ 0x40, 0x00, 0x95, 0xa1,
+ 0xa0, 0xa6, 0xc0, 0x00,
+ 0x0a, 0x40, 0x90, 0x90,
+ 0x91, 0x50, 0xb9, 0x30,
+ 0xc0, 0x20, 0x00, 0xe2,
+ 0x04, 0x87, 0xc2, 0x04,
+ 0x89, 0xd2, 0x04, 0x88,
+ 0xa8, 0x07, 0x80, 0xdd,
+ 0x11, 0xb0, 0xaa, 0x10,
+ 0xd0, 0xcc, 0x20, 0xd2,
+ 0x04, 0x86, 0x00, 0xee,
+ 0x11, 0x80, 0xdd, 0x01,
+ 0xe0, 0xdd, 0x20, 0xd0,
+ 0xcc, 0x20, 0xc0, 0x99,
+ 0x10, 0xa0, 0x99, 0x20,
+ 0xc0, 0x20, 0x00, 0x99,
+ 0x07, 0xc6, 0xfd, 0xfe,
+ 0x0c, 0x0b, 0x82, 0x0c,
+ 0x81, 0x72, 0x0c, 0x82,
+ 0x42, 0x0c, 0x83, 0x80,
+ 0x77, 0x11, 0x70, 0x44,
+ 0x20, 0x72, 0x0c, 0x80,
+ 0x00, 0x88, 0x11, 0x80,
+ 0x77, 0x01, 0x80, 0x77,
+ 0x20, 0x70, 0x44, 0x20,
+ 0x7d, 0x0c, 0xad, 0x04,
+ 0xe5, 0x2b, 0x00, 0x16,
+ 0xda, 0xbc, 0xa2, 0x07,
+ 0x85, 0x92, 0x07, 0x86,
+ 0x82, 0x07, 0x87, 0x80,
+ 0x99, 0x11, 0x90, 0x88,
+ 0x20, 0x92, 0x07, 0x84,
+ 0x00, 0xaa, 0x11, 0x80,
+ 0x99, 0x01, 0xa0, 0x99,
+ 0x20, 0x90, 0x88, 0x20,
+ 0xc0, 0x20, 0x00, 0x89,
+ 0x04, 0xc6, 0xe9, 0xfe,
+ 0xb2, 0x03, 0xa8, 0x22,
+ 0x44, 0x80, 0x16, 0x4b,
+ 0x04, 0xa2, 0x44, 0x80,
+ 0x0c, 0x0a, 0x0c, 0x1b,
+ 0x0c, 0x3c, 0x0c, 0xad,
+ 0xa5, 0x09, 0x00, 0x46,
+ 0xe3, 0xfe, 0x22, 0x4a,
+ 0x80, 0x22, 0x4a, 0x81,
+ 0x22, 0x4a, 0x82, 0x22,
+ 0x4a, 0x83, 0x22, 0x4a,
+ 0x84, 0x22, 0x4a, 0x85,
+ 0x22, 0x4a, 0x86, 0xbd,
+ 0x02, 0x86, 0x48, 0xff,
+ 0x22, 0x44, 0x80, 0x22,
+ 0x44, 0x81, 0x22, 0x44,
+ 0x82, 0x22, 0x44, 0x83,
+ 0x22, 0x44, 0x84, 0x22,
+ 0x44, 0x85, 0x22, 0x44,
+ 0x86, 0xad, 0x02, 0x46,
+ 0xb5, 0xff, 0xd2, 0x0c,
+ 0x80, 0xd0, 0xe1, 0x04,
+ 0xe0, 0xba, 0x93, 0xb2,
+ 0x43, 0xa8, 0x07, 0xed,
+ 0x01, 0xad, 0x02, 0xa2,
+ 0x63, 0x15, 0x86, 0xe9,
+ 0xff, 0xbd, 0x07, 0xa1,
+ 0x07, 0xe5, 0xe5, 0x8d,
+ 0xff, 0x25, 0x8c, 0xff,
+ 0x06, 0xcd, 0xfe, 0x00,
+ 0x36, 0x41, 0x00, 0x41,
+ 0xe3, 0xe3, 0x31, 0xe1,
+ 0xe3, 0x0c, 0x18, 0x32,
+ 0x03, 0xc1, 0x40, 0x33,
+ 0xa0, 0x32, 0x23, 0x7f,
+ 0x0c, 0x02, 0x48, 0x83,
+ 0x29, 0x43, 0x80, 0x44,
+ 0x20, 0x49, 0x83, 0x1d,
+ 0xf0, 0x00, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0x0c,
+ 0x18, 0x31, 0xfa, 0xe4,
+ 0x0c, 0x02, 0x22, 0x43,
+ 0x7c, 0x82, 0x43, 0x7d,
+ 0x82, 0x43, 0x7e, 0x1d,
+ 0xf0, 0x00, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0x0c,
+ 0x16, 0x30, 0x98, 0x41,
+ 0xa1, 0xf5, 0xe4, 0x71,
+ 0xcc, 0xe3, 0x81, 0xf4,
+ 0xe4, 0x70, 0x72, 0x82,
+ 0xaa, 0xa7, 0x32, 0x4a,
+ 0x83, 0x42, 0x4a, 0x80,
+ 0x52, 0x4a, 0x81, 0x8a,
+ 0x77, 0x92, 0x4a, 0x82,
+ 0x0c, 0x08, 0x4b, 0x93,
+ 0x92, 0x67, 0x7e, 0x82,
+ 0x67, 0x7f, 0x72, 0xd7,
+ 0x02, 0x62, 0x47, 0x00,
+ 0x1d, 0xf0, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0x88,
+ 0x12, 0x91, 0xc1, 0xe3,
+ 0x0c, 0x0a, 0xa9, 0x32,
+ 0xa2, 0x49, 0x64, 0xa2,
+ 0x49, 0x65, 0xa2, 0x49,
+ 0x6c, 0xa2, 0x49, 0x6d,
+ 0xa2, 0x69, 0x1a, 0x22,
+ 0x69, 0x11, 0x32, 0x69,
+ 0x1c, 0x82, 0x69, 0x13,
+ 0xa5, 0xf6, 0x00, 0x1d,
+ 0xf0, 0x00, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0xa1,
+ 0xdf, 0xe4, 0xe5, 0x0b,
+ 0x01, 0x0c, 0x4b, 0xb0,
+ 0xba, 0x20, 0xa1, 0xdc,
+ 0xe4, 0xe5, 0x0b, 0x01,
+ 0xa1, 0xdb, 0xe4, 0xe5,
+ 0x0a, 0x01, 0x0c, 0x1b,
+ 0xb0, 0xba, 0x20, 0xa1,
+ 0xd8, 0xe4, 0xe5, 0x0a,
+ 0x01, 0xa6, 0x13, 0x64,
+ 0x62, 0xa2, 0x00, 0xa2,
+ 0x02, 0x00, 0x66, 0x13,
+ 0x0e, 0xb2, 0xa3, 0x00,
+ 0xb0, 0xba, 0x20, 0xa1,
+ 0xd3, 0xe4, 0x65, 0x09,
+ 0x01, 0xc6, 0x0c, 0x00,
+ 0xb2, 0xa1, 0x00, 0xb0,
+ 0xba, 0x20, 0xa1, 0xcf,
+ 0xe4, 0x65, 0x08, 0x01,
+ 0xa6, 0x33, 0x13, 0x1b,
+ 0x42, 0x0b, 0x53, 0x5a,
+ 0x52, 0xa1, 0xcb, 0xe4,
+ 0xb2, 0x04, 0x00, 0x65,
+ 0x07, 0x01, 0x1b, 0x44,
+ 0x57, 0x94, 0xf1, 0x2a,
+ 0xb3, 0xb2, 0xdb, 0xff,
+ 0xb2, 0x0b, 0xff, 0xa1,
+ 0xc6, 0xe4, 0x60, 0xbb,
+ 0x20, 0xe5, 0x05, 0x01,
+ 0x0c, 0x83, 0xa1, 0xa2,
+ 0xe3, 0xa5, 0x04, 0x01,
+ 0x37, 0x0a, 0xf6, 0xa1,
+ 0xc2, 0xe4, 0x25, 0x04,
+ 0x01, 0xa2, 0x42, 0x00,
+ 0x1b, 0x22, 0x67, 0x0a,
+ 0xf1, 0xa1, 0xbc, 0xe4,
+ 0x0c, 0x4b, 0xe5, 0x03,
+ 0x01, 0x1d, 0xf0, 0x00,
+ 0x36, 0x41, 0x00, 0x92,
+ 0x03, 0x00, 0x82, 0x03,
+ 0x01, 0x80, 0x99, 0x11,
+ 0x90, 0x88, 0x20, 0x80,
+ 0x80, 0xf4, 0xcc, 0x64,
+ 0xf6, 0x42, 0x04, 0x0c,
+ 0x07, 0x46, 0x00, 0x00,
+ 0x0c, 0x17, 0x0c, 0x0b,
+ 0xd2, 0x03, 0x03, 0x0c,
+ 0x1c, 0xe2, 0x03, 0x02,
+ 0xf2, 0xa3, 0xf7, 0x80,
+ 0xff, 0x62, 0x80, 0xee,
+ 0x01, 0xe0, 0xe8, 0x31,
+ 0xd0, 0xcc, 0x62, 0x8c,
+ 0x54, 0x4b, 0xa8, 0xa7,
+ 0xa2, 0x01, 0x0c, 0x07,
+ 0xf0, 0x7b, 0x93, 0xe0,
+ 0x7b, 0xa3, 0x70, 0x20,
+ 0x74, 0xc0, 0x2b, 0x93,
+ 0x1d, 0xf0, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0x61,
+ 0xa8, 0xe4, 0x81, 0xa8,
+ 0xe4, 0x0c, 0x17, 0x92,
+ 0x28, 0x21, 0xa2, 0x28,
+ 0x22, 0xb2, 0xa1, 0x03,
+ 0x97, 0x9a, 0x34, 0xbc,
+ 0x12, 0xb2, 0x66, 0x1e,
+ 0xc1, 0xa5, 0xe4, 0x22,
+ 0x66, 0x1f, 0x41, 0xa2,
+ 0xe4, 0x0c, 0x85, 0x52,
+ 0x46, 0x74, 0x42, 0x66,
+ 0x22, 0x0c, 0x02, 0xa2,
+ 0x03, 0x00, 0xb2, 0x26,
+ 0x22, 0x1b, 0x33, 0x2a,
+ 0xbb, 0xa2, 0x4b, 0x00,
+ 0x92, 0x26, 0x1f, 0x1b,
+ 0x22, 0x97, 0x32, 0xea,
+ 0xc2, 0x68, 0x1d, 0x72,
+ 0x66, 0x1c, 0x1d, 0xf0,
+ 0xd2, 0x28, 0x24, 0x0c,
+ 0x52, 0xec, 0x4d, 0x22,
+ 0x68, 0x1e, 0x0c, 0x03,
+ 0x0c, 0x42, 0x22, 0x68,
+ 0x1f, 0x97, 0x9a, 0x01,
+ 0x2d, 0x03, 0x22, 0x48,
+ 0x8c, 0x32, 0x46, 0x8c,
+ 0x32, 0x46, 0x8d, 0x32,
+ 0x46, 0x8e, 0x72, 0x46,
+ 0x8f, 0xb2, 0x46, 0x90,
+ 0x0c, 0x37, 0x46, 0xf3,
+ 0xff, 0x7d, 0x02, 0x06,
+ 0xf2, 0xff, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0x41,
+ 0x8c, 0xe4, 0xc0, 0x20,
+ 0x00, 0x81, 0x5b, 0xe3,
+ 0x22, 0x68, 0x75, 0x38,
+ 0x04, 0xc0, 0x20, 0x00,
+ 0x39, 0x04, 0x1d, 0xf0,
+ 0x36, 0x41, 0x00, 0x9c,
+ 0xb3, 0x71, 0x86, 0xe4,
+ 0x0c, 0x03, 0x70, 0x63,
+ 0xb0, 0x48, 0x06, 0x1b,
+ 0x33, 0x47, 0x32, 0x04,
+ 0x58, 0x16, 0x57, 0x32,
+ 0x26, 0x30, 0x30, 0x74,
+ 0x66, 0x33, 0xea, 0x46,
+ 0x06, 0x00, 0x71, 0x80,
+ 0xe4, 0x0c, 0x03, 0x70,
+ 0x63, 0xb0, 0x48, 0x06,
+ 0x1b, 0x33, 0x47, 0x32,
+ 0x04, 0x58, 0x16, 0x57,
+ 0x32, 0x09, 0x30, 0x30,
+ 0x74, 0x66, 0x73, 0xea,
+ 0x0c, 0x12, 0x1d, 0xf0,
+ 0x0c, 0x02, 0x1d, 0xf0,
+ 0x36, 0x41, 0x00, 0x91,
+ 0x72, 0xe4, 0x61, 0x70,
+ 0xe4, 0x72, 0x29, 0x21,
+ 0x82, 0x29, 0x22, 0x0c,
+ 0x3b, 0x77, 0x98, 0x1f,
+ 0x9c, 0xc3, 0x32, 0x66,
+ 0x1f, 0x71, 0x73, 0xe4,
+ 0x22, 0x66, 0x1e, 0x41,
+ 0x71, 0xe4, 0x0c, 0x95,
+ 0x52, 0x46, 0x74, 0x42,
+ 0x66, 0x22, 0x0c, 0x12,
+ 0x72, 0x69, 0x1d, 0x22,
+ 0x66, 0x1c, 0x1d, 0xf0,
+ 0x0c, 0x5a, 0xb2, 0x69,
+ 0x1f, 0xa2, 0x69, 0x1e,
+ 0x0c, 0x0a, 0x77, 0x18,
+ 0x1e, 0x0c, 0x43, 0x20,
+ 0xc8, 0x41, 0x20, 0xd0,
+ 0xf5, 0x32, 0x49, 0x8c,
+ 0xa2, 0x46, 0x8c, 0xa2,
+ 0x46, 0x8d, 0x22, 0x46,
+ 0x90, 0xd2, 0x46, 0x8e,
+ 0xc2, 0x46, 0x8f, 0x2d,
+ 0x0b, 0x86, 0xf3, 0xff,
+ 0x3d, 0x0a, 0x46, 0xf7,
+ 0xff, 0x00, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0x81,
+ 0x2a, 0xe3, 0x51, 0x2d,
+ 0xe3, 0x80, 0x82, 0x82,
+ 0x8a, 0x25, 0x42, 0x22,
+ 0x7f, 0x92, 0xd2, 0x02,
+ 0x66, 0x54, 0x09, 0x92,
+ 0x09, 0x09, 0x0c, 0x12,
+ 0x37, 0x99, 0x01, 0x1d,
+ 0xf0, 0x0c, 0x02, 0x1d,
+ 0xf0, 0x00, 0x00, 0x00,
+ 0x36, 0x61, 0x00, 0x0c,
+ 0x59, 0x0c, 0x04, 0xd1,
+ 0x55, 0xe4, 0x51, 0x20,
+ 0xe3, 0x32, 0xcd, 0xe0,
+ 0xb2, 0x2d, 0x19, 0x22,
+ 0xd5, 0x06, 0x16, 0xdb,
+ 0x07, 0x62, 0xcd, 0x68,
+ 0x0b, 0x8b, 0x16, 0x78,
+ 0x15, 0xa2, 0xcb, 0xfe,
+ 0x16, 0xea, 0x16, 0x26,
+ 0x3b, 0x14, 0x26, 0x4b,
+ 0x50, 0x66, 0x5b, 0x0c,
+ 0x42, 0x62, 0x10, 0xa2,
+ 0xa2, 0x02, 0x0c, 0x6b,
+ 0x65, 0xf3, 0xff, 0x1d,
+ 0xf0, 0x1d, 0xf0, 0xc1,
+ 0x11, 0xe3, 0xa8, 0xe2,
+ 0xb1, 0x11, 0xe3, 0xc0,
+ 0xca, 0x82, 0xba, 0xbc,
+ 0xb2, 0x0b, 0x80, 0x56,
+ 0xab, 0xfe, 0xb8, 0xa2,
+ 0x9c, 0x9b, 0xe1, 0x42,
+ 0xe4, 0x5a, 0xfc, 0xcd,
+ 0x04, 0xda, 0x8c, 0xca,
+ 0x9f, 0xea, 0x99, 0x82,
+ 0x08, 0x80, 0x1b, 0xcc,
+ 0x82, 0x49, 0x70, 0xc0,
+ 0xc0, 0x74, 0xb7, 0x3c,
+ 0xeb, 0xc2, 0x02, 0x2c,
+ 0x0c, 0x1d, 0x25, 0xcd,
+ 0xff, 0x42, 0x63, 0x21,
+ 0x1d, 0xf0, 0xb1, 0x06,
+ 0xe3, 0xc1, 0x06, 0xe3,
+ 0xb2, 0x0b, 0xc1, 0x92,
+ 0x6d, 0x19, 0xc0, 0xbb,
+ 0xa0, 0xb2, 0x2b, 0x7f,
+ 0xa2, 0x22, 0x10, 0xa9,
+ 0x4b, 0x1d, 0xf0, 0xad,
+ 0x04, 0x0c, 0x1b, 0xe5,
+ 0xf3, 0xff, 0x0c, 0x1e,
+ 0xe9, 0x01, 0x16, 0xba,
+ 0x39, 0x9d, 0x0e, 0x49,
+ 0xe2, 0x0c, 0x0b, 0x16,
+ 0xe9, 0xf8, 0xc1, 0xf5,
+ 0xe2, 0xa8, 0xe2, 0x0c,
+ 0x37, 0xc0, 0xca, 0x82,
+ 0x61, 0xa2, 0xe3, 0x5a,
+ 0xfc, 0x6a, 0x6c, 0xd2,
+ 0x06, 0x83, 0x52, 0x06,
+ 0x82, 0x62, 0x06, 0x80,
+ 0x80, 0x55, 0x11, 0x50,
+ 0xdd, 0x20, 0xd9, 0x11,
+ 0x52, 0xdf, 0x11, 0x52,
+ 0xc5, 0xf0, 0xd0, 0xd0,
+ 0xf4, 0xd9, 0x21, 0x66,
+ 0x1a, 0x08, 0x26, 0x36,
+ 0x05, 0xd2, 0xc6, 0xfc,
+ 0x56, 0x5d, 0xf5, 0x91,
+ 0x16, 0xe4, 0xd1, 0xd2,
+ 0xe3, 0x0c, 0xc8, 0x67,
+ 0xb8, 0x36, 0x0c, 0xda,
+ 0x67, 0x3a, 0x0a, 0xda,
+ 0xbc, 0xb2, 0x0b, 0x80,
+ 0xb2, 0x63, 0x15, 0x06,
+ 0x07, 0x00, 0x1c, 0x68,
+ 0x67, 0x38, 0x02, 0xc6,
+ 0x43, 0x00, 0x1c, 0x7d,
+ 0x67, 0xbd, 0x02, 0x06,
+ 0x81, 0x00, 0x92, 0x02,
+ 0x3d, 0x92, 0x43, 0xa0,
+ 0xe9, 0xa2, 0xd9, 0xb2,
+ 0x72, 0x63, 0x21, 0x91,
+ 0xdd, 0xe2, 0x9a, 0x9c,
+ 0x42, 0x69, 0x7f, 0x1d,
+ 0xf0, 0xfd, 0x09, 0x0c,
+ 0x89, 0xf6, 0x66, 0x02,
+ 0x86, 0x20, 0x00, 0xb6,
+ 0x76, 0x02, 0x46, 0x2c,
+ 0x00, 0xda, 0x3c, 0x82,
+ 0x03, 0x80, 0x32, 0x03,
+ 0x81, 0x80, 0x88, 0x11,
+ 0x80, 0x33, 0x20, 0xad,
+ 0x03, 0x25, 0xde, 0xff,
+ 0x9c, 0xea, 0xa2, 0x05,
+ 0x03, 0x92, 0x05, 0x04,
+ 0x82, 0x05, 0x05, 0x80,
+ 0x99, 0x11, 0x90, 0x88,
+ 0x20, 0x92, 0x05, 0x02,
+ 0x00, 0xaa, 0x11, 0x80,
+ 0x99, 0x01, 0xa0, 0x99,
+ 0x20, 0x90, 0x88, 0x20,
+ 0x89, 0x03, 0xd1, 0xc5,
+ 0xe2, 0xc8, 0xe2, 0xd0,
+ 0xcc, 0x82, 0x46, 0xe9,
+ 0xff, 0x65, 0x6d, 0x00,
+ 0xb8, 0x92, 0x16, 0x0a,
+ 0x1e, 0xad, 0x06, 0xe5,
+ 0x67, 0x00, 0x0c, 0x2e,
+ 0xe2, 0x63, 0x21, 0x25,
+ 0xfb, 0x01, 0xc0, 0x20,
+ 0x00, 0xa2, 0x62, 0x13,
+ 0x1d, 0xf0, 0x65, 0xfa,
+ 0x01, 0xbd, 0x0a, 0xc0,
+ 0x20, 0x00, 0xa2, 0x22,
+ 0x13, 0x25, 0xde, 0x00,
+ 0xf1, 0xf0, 0xe3, 0xa7,
+ 0x3f, 0x02, 0xc6, 0xa3,
+ 0xff, 0xad, 0x06, 0xb8,
+ 0x92, 0xe5, 0xbc, 0xff,
+ 0x1d, 0xf0, 0xf6, 0x36,
+ 0x02, 0x06, 0x23, 0x00,
+ 0xb6, 0x46, 0x02, 0xc6,
+ 0x50, 0x00, 0xda, 0xcc,
+ 0xa2, 0x0c, 0x84, 0xd2,
+ 0x0c, 0x80, 0xb2, 0x0c,
+ 0x81, 0x80, 0xdd, 0x11,
+ 0xd0, 0xbb, 0x20, 0xd2,
+ 0x0c, 0x83, 0xc2, 0x0c,
+ 0x82, 0x80, 0xdd, 0x11,
+ 0x00, 0xcc, 0x11, 0xd0,
+ 0xcc, 0x20, 0xc0, 0xaa,
+ 0x20, 0xa5, 0xd8, 0xff,
+ 0x86, 0xe0, 0xff, 0xf6,
+ 0x96, 0x02, 0x46, 0x28,
+ 0x00, 0x0c, 0xaa, 0x67,
+ 0xba, 0x02, 0x06, 0xac,
+ 0x00, 0x0c, 0x88, 0x91,
+ 0xdb, 0xe3, 0xb1, 0xd7,
+ 0xe3, 0x92, 0x09, 0x7f,
+ 0x92, 0x4b, 0x80, 0x72,
+ 0x63, 0x21, 0xa9, 0xb2,
+ 0xf2, 0x02, 0x33, 0xe9,
+ 0xa2, 0x80, 0xff, 0x10,
+ 0xf2, 0x42, 0x33, 0xc6,
+ 0xd4, 0xff, 0x1c, 0x1a,
+ 0x67, 0x3a, 0x02, 0xc6,
+ 0x49, 0x00, 0x1c, 0x2a,
+ 0x67, 0xba, 0x02, 0x86,
+ 0x4f, 0x00, 0xda, 0xac,
+ 0xb2, 0xdf, 0x11, 0xb2,
+ 0xcb, 0xf3, 0xc2, 0x0a,
+ 0x82, 0xd2, 0x0a, 0x81,
+ 0xa2, 0x0a, 0x80, 0x80,
+ 0xdd, 0x11, 0xda, 0xcc,
+ 0xc2, 0x62, 0x10, 0x25,
+ 0xc5, 0xff, 0x06, 0xc9,
+ 0xff, 0xa1, 0xc8, 0xe3,
+ 0xf6, 0x26, 0x02, 0xc6,
+ 0x80, 0x00, 0x42, 0x43,
+ 0x88, 0xe2, 0x63, 0x24,
+ 0x42, 0x43, 0x98, 0xda,
+ 0xbc, 0x92, 0xa0, 0x80,
+ 0x82, 0x0b, 0x81, 0xb2,
+ 0x0b, 0x80, 0xb2, 0x42,
+ 0x30, 0x80, 0x94, 0x83,
+ 0x92, 0x42, 0x31, 0x16,
+ 0xfb, 0x2f, 0xf2, 0x63,
+ 0x27, 0xb2, 0x4a, 0xa4,
+ 0x3c, 0x0d, 0xa1, 0xbd,
+ 0xe3, 0xd2, 0x63, 0x23,
+ 0x92, 0x42, 0x31, 0xa9,
+ 0x92, 0x42, 0x43, 0x98,
+ 0x42, 0x43, 0x88, 0xe2,
+ 0x63, 0x24, 0x7d, 0x0e,
+ 0x06, 0xa2, 0xff, 0xf6,
+ 0x86, 0x02, 0x46, 0x88,
+ 0x00, 0x0c, 0x8e, 0x67,
+ 0xbe, 0x02, 0x46, 0x9f,
+ 0xff, 0xda, 0x6c, 0x82,
+ 0x06, 0x80, 0x62, 0x06,
+ 0x81, 0x80, 0x88, 0x11,
+ 0x80, 0x66, 0x20, 0xad,
+ 0x06, 0xa5, 0xc7, 0xff,
+ 0x16, 0x6a, 0xeb, 0x88,
+ 0x06, 0xe2, 0x05, 0x03,
+ 0xd2, 0x05, 0x02, 0x1c,
+ 0xfc, 0x92, 0x05, 0x07,
+ 0xb2, 0x05, 0x05, 0xa2,
+ 0x05, 0x06, 0x00, 0xbb,
+ 0x11, 0x80, 0xaa, 0x11,
+ 0xa0, 0x99, 0x20, 0xd0,
+ 0xcc, 0xc0, 0xa2, 0x05,
+ 0x04, 0x2c, 0x0d, 0xe0,
+ 0xdd, 0xc0, 0x00, 0x1d,
+ 0x40, 0x80, 0xaa, 0x01,
+ 0xb0, 0xaa, 0x20, 0xa0,
+ 0x99, 0x20, 0x7c, 0xfb,
+ 0x00, 0xab, 0xa1, 0x00,
+ 0x0c, 0x40, 0xa0, 0xa0,
+ 0x91, 0x90, 0x9a, 0x10,
+ 0xb0, 0xaa, 0x30, 0xa0,
+ 0x88, 0x10, 0x90, 0x88,
+ 0x20, 0x89, 0x06, 0xc6,
+ 0x99, 0xff, 0xf6, 0x56,
+ 0x02, 0x86, 0x24, 0x00,
+ 0xda, 0xbc, 0xb2, 0x0b,
+ 0x80, 0xb2, 0x42, 0x32,
+ 0xc6, 0x81, 0xff, 0xd2,
+ 0xa0, 0xfd, 0x67, 0x3d,
+ 0x02, 0x86, 0x7f, 0xff,
+ 0xe2, 0xa0, 0xfe, 0x67,
+ 0xbe, 0x02, 0x46, 0x7d,
+ 0xff, 0xf8, 0x21, 0x9c,
+ 0x0f, 0xc2, 0xc9, 0x80,
+ 0x5a, 0xdf, 0xe2, 0x05,
+ 0x00, 0xe2, 0x4c, 0x80,
+ 0x1b, 0x55, 0x1b, 0xcc,
+ 0xd7, 0x95, 0xf2, 0xa1,
+ 0x80, 0xe3, 0xb8, 0x21,
+ 0x65, 0xa6, 0xff, 0xc6,
+ 0x88, 0xff, 0x1c, 0x0f,
+ 0x67, 0x3f, 0x02, 0xc6,
+ 0x6e, 0x00, 0x92, 0x02,
+ 0x48, 0x90, 0x90, 0x04,
+ 0x92, 0x43, 0xa0, 0xe9,
+ 0xa2, 0xa9, 0xb2, 0x46,
+ 0x6e, 0xff, 0xad, 0x06,
+ 0xa5, 0xa1, 0xff, 0x1d,
+ 0xf0, 0xe9, 0x01, 0x1c,
+ 0x5a, 0x67, 0x3a, 0x02,
+ 0x46, 0x40, 0x00, 0xbd,
+ 0x05, 0xa8, 0x11, 0x0c,
+ 0x1c, 0xa0, 0xa0, 0xf4,
+ 0x65, 0xac, 0xff, 0x56,
+ 0x9a, 0x19, 0xdd, 0x06,
+ 0x42, 0x43, 0xa1, 0x42,
+ 0x43, 0xa2, 0x42, 0x42,
+ 0x3d, 0x42, 0x42, 0x3c,
+ 0xe1, 0x3d, 0xe2, 0xc8,
+ 0xe2, 0x9d, 0x04, 0xe0,
+ 0xcc, 0x82, 0xed, 0x07,
+ 0x46, 0x5d, 0xff, 0x82,
+ 0xc6, 0xfc, 0x56, 0x98,
+ 0xd7, 0x0c, 0x09, 0xb8,
+ 0xd2, 0x92, 0x63, 0x24,
+ 0xa7, 0x9b, 0x63, 0x0c,
+ 0x88, 0xf2, 0x63, 0x27,
+ 0x82, 0x43, 0x88, 0xda,
+ 0x8c, 0x92, 0x08, 0x83,
+ 0x62, 0x08, 0x80, 0xd2,
+ 0x08, 0x81, 0x80, 0x66,
+ 0x11, 0x60, 0xdd, 0x20,
+ 0x80, 0x99, 0x11, 0x62,
+ 0x08, 0x84, 0x82, 0x08,
+ 0x82, 0xd2, 0x63, 0x24,
+ 0x00, 0x88, 0x11, 0x90,
+ 0x88, 0x20, 0x80, 0x66,
+ 0x20, 0x62, 0x63, 0x23,
+ 0xac, 0x9d, 0xad, 0x05,
+ 0x0c, 0x0b, 0x92, 0x0a,
+ 0x05, 0xc2, 0x23, 0x27,
+ 0x1b, 0xaa, 0xba, 0xcc,
+ 0x92, 0x4c, 0x00, 0xd2,
+ 0x23, 0x24, 0x1b, 0xbb,
+ 0xd7, 0x3b, 0xea, 0xe2,
+ 0x63, 0x21, 0xb8, 0xd2,
+ 0xc1, 0x21, 0xe2, 0xf1,
+ 0x50, 0xe3, 0xa8, 0xe2,
+ 0xf9, 0x92, 0xc0, 0xca,
+ 0x82, 0xa7, 0x9b, 0x02,
+ 0x56, 0xbd, 0xd0, 0x0c,
+ 0x4d, 0x0c, 0x58, 0x89,
+ 0xa2, 0xd9, 0xb2, 0xa7,
+ 0x9b, 0x01, 0xdd, 0x04,
+ 0xd2, 0x42, 0x3c, 0x72,
+ 0x63, 0x21, 0x42, 0x43,
+ 0xa0, 0x42, 0x43, 0xa1,
+ 0x92, 0x05, 0x04, 0xa2,
+ 0x05, 0x03, 0xb2, 0x05,
+ 0x02, 0xb2, 0x43, 0xa2,
+ 0xa2, 0x43, 0xa3, 0x92,
+ 0x43, 0xa4, 0x46, 0x37,
+ 0xff, 0xad, 0x0e, 0x0c,
+ 0x1b, 0x25, 0xb9, 0xff,
+ 0xe8, 0x01, 0x16, 0xfa,
+ 0x11, 0xe9, 0xe2, 0x0c,
+ 0x19, 0x0c, 0x1b, 0x06,
+ 0x15, 0xff, 0x56, 0x56,
+ 0xcc, 0x92, 0x43, 0x88,
+ 0xf2, 0x63, 0x27, 0xb1,
+ 0x45, 0xe3, 0xda, 0x8c,
+ 0x82, 0x08, 0x80, 0xb9,
+ 0x92, 0x82, 0x4a, 0xa4,
+ 0x82, 0xa6, 0x00, 0x82,
+ 0x63, 0x23, 0x46, 0x85,
+ 0xff, 0xe9, 0x01, 0x92,
+ 0xc6, 0xeb, 0x56, 0x19,
+ 0xca, 0xbd, 0x05, 0xa8,
+ 0x11, 0x0c, 0x0c, 0xa0,
+ 0xa0, 0xf4, 0xe5, 0x9b,
+ 0xff, 0xd1, 0xfe, 0xe1,
+ 0xc8, 0xe2, 0xd0, 0xcc,
+ 0x82, 0x56, 0x0a, 0x0f,
+ 0x69, 0xb2, 0x79, 0xa2,
+ 0x42, 0x42, 0x3d, 0x42,
+ 0x42, 0x3c, 0x42, 0x43,
+ 0xa0, 0x42, 0x43, 0xa1,
+ 0x42, 0x43, 0xa2, 0x46,
+ 0x1c, 0xff, 0xe2, 0xc6,
+ 0xf4, 0x56, 0xee, 0xc6,
+ 0xda, 0xac, 0xa2, 0x0a,
+ 0x80, 0xe5, 0xa5, 0xff,
+ 0x86, 0x2c, 0xff, 0xe2,
+ 0xc6, 0xf9, 0x56, 0xde,
+ 0xc5, 0xda, 0x6c, 0x82,
+ 0x06, 0x80, 0x62, 0x06,
+ 0x81, 0x80, 0x88, 0x11,
+ 0x80, 0x66, 0x20, 0xad,
+ 0x06, 0xa5, 0xa5, 0xff,
+ 0x16, 0x2a, 0x0e, 0xc2,
+ 0x05, 0x01, 0xb2, 0x05,
+ 0x00, 0xb2, 0x43, 0xa0,
+ 0xc2, 0x43, 0xa1, 0xa8,
+ 0x06, 0xa0, 0xa8, 0x75,
+ 0xa2, 0x43, 0xa2, 0x98,
+ 0x06, 0x90, 0x90, 0xf5,
+ 0x92, 0x43, 0xa3, 0x88,
+ 0x06, 0x80, 0x88, 0x41,
+ 0x82, 0x43, 0xa4, 0x98,
+ 0x06, 0x72, 0x63, 0x21,
+ 0x0c, 0x7d, 0x92, 0x43,
+ 0xa5, 0x0c, 0x6e, 0xe9,
+ 0xa2, 0xd9, 0xb2, 0xc6,
+ 0x17, 0xff, 0x0c, 0xea,
+ 0xf2, 0xc6, 0xf2, 0x56,
+ 0x8f, 0xc0, 0x92, 0x02,
+ 0x3c, 0xc6, 0x8e, 0xff,
+ 0x42, 0x43, 0x88, 0xc2,
+ 0x05, 0x03, 0x0c, 0x1b,
+ 0x0c, 0x0a, 0x82, 0x05,
+ 0x01, 0x92, 0x05, 0x00,
+ 0xd1, 0x13, 0xe3, 0xe2,
+ 0x05, 0x02, 0xe2, 0x63,
+ 0x23, 0xd2, 0x63, 0x27,
+ 0x80, 0x99, 0x11, 0x90,
+ 0x88, 0x20, 0xc0, 0xab,
+ 0x83, 0xa2, 0x43, 0x98,
+ 0x82, 0x63, 0x24, 0x9c,
+ 0x58, 0x0c, 0x0b, 0x82,
+ 0x05, 0x04, 0x92, 0x23,
+ 0x27, 0x1b, 0x55, 0xba,
+ 0x99, 0x82, 0x49, 0x00,
+ 0xf2, 0x23, 0x24, 0x1b,
+ 0xbb, 0xf7, 0x3b, 0xea,
+ 0xa1, 0x07, 0xe3, 0xb8,
+ 0x01, 0xb2, 0x63, 0x21,
+ 0xa9, 0x92, 0x06, 0x00,
+ 0xff, 0x0c, 0x09, 0x86,
+ 0xcd, 0xfe, 0x92, 0x4a,
+ 0xa5, 0x5c, 0x0d, 0x1b,
+ 0x8f, 0x82, 0x63, 0x27,
+ 0xd2, 0x63, 0x23, 0xa1,
+ 0x00, 0xe3, 0x86, 0x3e,
+ 0xff, 0xe2, 0x05, 0x01,
+ 0xd2, 0x05, 0x03, 0x0c,
+ 0x1b, 0x0c, 0x0a, 0xf2,
+ 0x05, 0x00, 0x72, 0x05,
+ 0x02, 0x91, 0xfc, 0xe2,
+ 0x81, 0xfb, 0xe2, 0x89,
+ 0x92, 0x92, 0x63, 0x27,
+ 0x72, 0x63, 0x23, 0x80,
+ 0xff, 0x11, 0x78, 0x01,
+ 0x72, 0x43, 0x88, 0xd0,
+ 0xab, 0x83, 0xf0, 0xee,
+ 0x20, 0xe2, 0x63, 0x24,
+ 0xa2, 0x43, 0x98, 0x46,
+ 0xd8, 0xfe, 0x42, 0x43,
+ 0xa0, 0x42, 0x43, 0xa1,
+ 0x42, 0x43, 0xa2, 0x42,
+ 0x43, 0xa3, 0x42, 0x43,
+ 0xa4, 0x9d, 0x04, 0x86,
+ 0xcb, 0xff, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0x41,
+ 0xb2, 0xe1, 0x31, 0xb0,
+ 0xe1, 0x0c, 0x18, 0x32,
+ 0x03, 0xc1, 0x40, 0x33,
+ 0xa0, 0x32, 0x23, 0x7f,
+ 0x0c, 0x02, 0x48, 0x83,
+ 0x29, 0x43, 0x80, 0x44,
+ 0x20, 0x49, 0x83, 0x1d,
+ 0xf0, 0x00, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0x41,
+ 0xe5, 0xe2, 0x31, 0xa4,
+ 0xe1, 0x0c, 0x02, 0x22,
+ 0x63, 0x82, 0x22, 0x64,
+ 0x20, 0x22, 0x44, 0x7c,
+ 0x22, 0x44, 0x7d, 0x1d,
+ 0xf0, 0x00, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0x1c,
+ 0x6b, 0x0c, 0x33, 0x41,
+ 0xc8, 0xe2, 0xd2, 0x02,
+ 0x00, 0xa1, 0xd2, 0xe2,
+ 0xd0, 0xd0, 0x14, 0xd2,
+ 0x4a, 0x88, 0xc2, 0x02,
+ 0x00, 0x32, 0x6a, 0x1d,
+ 0xb2, 0x6a, 0x1e, 0xc0,
+ 0xc2, 0x14, 0xc2, 0x4a,
+ 0x89, 0x98, 0x32, 0x90,
+ 0x98, 0x41, 0x92, 0x44,
+ 0x8c, 0x88, 0x32, 0x82,
+ 0x44, 0x8d, 0x58, 0x12,
+ 0x52, 0x44, 0x8e, 0x32,
+ 0x64, 0x1c, 0x1d, 0xf0,
+ 0x36, 0x41, 0x00, 0x0c,
+ 0x33, 0x1c, 0x5b, 0xf2,
+ 0x02, 0x00, 0xc1, 0xc4,
+ 0xe2, 0xf0, 0xf0, 0x14,
+ 0xf2, 0x4c, 0x88, 0xe2,
+ 0x02, 0x00, 0xe0, 0xe2,
+ 0x14, 0xe2, 0x4c, 0x89,
+ 0xd8, 0x32, 0xb2, 0x6c,
+ 0x1e, 0x3b, 0xdd, 0xd2,
+ 0x6c, 0x1d, 0xa8, 0x32,
+ 0x41, 0xb1, 0xe2, 0xa0,
+ 0xa8, 0x41, 0xa2, 0x44,
+ 0x8c, 0x98, 0x32, 0x92,
+ 0x44, 0x8d, 0x88, 0x12,
+ 0x82, 0x44, 0x8e, 0x32,
+ 0x64, 0x1c, 0x1d, 0xf0,
+ 0x36, 0x41, 0x00, 0x51,
+ 0xaa, 0xe2, 0x0c, 0x46,
+ 0x42, 0x02, 0x00, 0x71,
+ 0xb4, 0xe2, 0x40, 0x40,
+ 0x14, 0x42, 0x47, 0x88,
+ 0x32, 0x27, 0x23, 0x0c,
+ 0x34, 0xec, 0xd3, 0x62,
+ 0x67, 0x1e, 0x0c, 0x5d,
+ 0xd2, 0x67, 0x1d, 0xc8,
+ 0x32, 0xc0, 0xc8, 0x41,
+ 0xc2, 0x45, 0x8c, 0xb8,
+ 0x32, 0xb2, 0x45, 0x8d,
+ 0xa8, 0x12, 0xa0, 0xa0,
+ 0x35, 0xa2, 0x45, 0x8e,
+ 0x98, 0x12, 0x90, 0x98,
+ 0x41, 0x92, 0x45, 0x8f,
+ 0x88, 0x12, 0x82, 0x45,
+ 0x90, 0x42, 0x65, 0x1c,
+ 0x1d, 0xf0, 0x4d, 0x06,
+ 0x46, 0xfd, 0xff, 0x00,
+ 0x36, 0x41, 0x00, 0x41,
+ 0x96, 0xe2, 0x0c, 0x33,
+ 0xe8, 0x32, 0xd1, 0xa0,
+ 0xe2, 0x5b, 0xee, 0x32,
+ 0x6d, 0x1e, 0xe2, 0x6d,
+ 0x1d, 0xc2, 0x02, 0x00,
+ 0xc0, 0xc0, 0x14, 0xc2,
+ 0x4d, 0x88, 0xb8, 0x32,
+ 0xb0, 0xb8, 0x41, 0xb2,
+ 0x44, 0x8c, 0xa8, 0x32,
+ 0xa2, 0x44, 0x8d, 0x98,
+ 0x12, 0x90, 0x90, 0x35,
+ 0x92, 0x44, 0x8e, 0x88,
+ 0x12, 0x80, 0x88, 0x41,
+ 0x82, 0x44, 0x8f, 0x58,
+ 0x12, 0x52, 0x44, 0x90,
+ 0x32, 0x64, 0x1c, 0x1d,
+ 0xf0, 0x00, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0x71,
+ 0x9b, 0xe2, 0x0c, 0x16,
+ 0x0c, 0x05, 0x32, 0x02,
+ 0x00, 0x41, 0x97, 0xe2,
+ 0x9c, 0xc3, 0x82, 0x04,
+ 0x84, 0x21, 0x97, 0xe2,
+ 0x9c, 0x48, 0x52, 0x67,
+ 0x20, 0x62, 0x47, 0x88,
+ 0x3c, 0x09, 0x92, 0x67,
+ 0x1f, 0x22, 0x64, 0x1e,
+ 0x62, 0x67, 0x1d, 0x52,
+ 0x47, 0x78, 0x1d, 0xf0,
+ 0x62, 0x67, 0x20, 0x52,
+ 0x47, 0x88, 0x21, 0x89,
+ 0xe2, 0xb1, 0x83, 0xe2,
+ 0xa2, 0x04, 0x85, 0xc1,
+ 0x8e, 0xe2, 0x5c, 0x0d,
+ 0xd2, 0x67, 0x1f, 0xc2,
+ 0x67, 0x23, 0xa2, 0x4b,
+ 0xa5, 0x06, 0xf5, 0xff,
+ 0x36, 0x41, 0x00, 0x0c,
+ 0x08, 0x0c, 0x2a, 0x91,
+ 0x85, 0xe2, 0x31, 0x6e,
+ 0xe2, 0x0c, 0x32, 0x22,
+ 0x63, 0x1c, 0xa2, 0x69,
+ 0x20, 0xa2, 0x69, 0x1f,
+ 0x82, 0x43, 0x8c, 0x92,
+ 0x09, 0x84, 0x92, 0x43,
+ 0x8d, 0x1d, 0xf0, 0x00,
+ 0x36, 0x41, 0x00, 0x0c,
+ 0x1c, 0x31, 0x81, 0xe2,
+ 0x21, 0x82, 0xe2, 0x81,
+ 0x7f, 0xe2, 0xa2, 0xa0,
+ 0x80, 0x91, 0x7a, 0xe2,
+ 0x5c, 0x0b, 0xb2, 0x69,
+ 0x1f, 0xa2, 0x69, 0x20,
+ 0x82, 0x69, 0x23, 0x22,
+ 0x63, 0x7f, 0xc2, 0x69,
+ 0x1d, 0xc2, 0x49, 0x88,
+ 0xc2, 0x49, 0x78, 0x1d,
+ 0xf0, 0x00, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0x0c,
+ 0x33, 0x41, 0x5a, 0xe2,
+ 0x51, 0x70, 0xe2, 0x98,
+ 0x32, 0x0c, 0x28, 0x2b,
+ 0x99, 0x82, 0x65, 0x20,
+ 0x92, 0x65, 0x1f, 0x52,
+ 0x05, 0x84, 0x88, 0x32,
+ 0x82, 0x44, 0x8c, 0x32,
+ 0x64, 0x1c, 0x52, 0x44,
+ 0x8d, 0x1d, 0xf0, 0x00,
+ 0x36, 0x41, 0x00, 0x31,
+ 0x26, 0xe1, 0x0c, 0x02,
+ 0x22, 0x63, 0x82, 0x1d,
+ 0xf0, 0x00, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0xa2,
+ 0x02, 0x00, 0xc8, 0x22,
+ 0x88, 0x12, 0x41, 0x20,
+ 0xe1, 0x0c, 0x09, 0x99,
+ 0x32, 0x22, 0x64, 0x11,
+ 0x92, 0x44, 0x64, 0x92,
+ 0x44, 0x65, 0x32, 0x64,
+ 0x1c, 0x92, 0x44, 0x6c,
+ 0x82, 0x64, 0x13, 0xc2,
+ 0x64, 0x1a, 0x37, 0xea,
+ 0x07, 0x0c, 0x1b, 0xc0,
+ 0xb9, 0x83, 0x46, 0x00,
+ 0x00, 0xbd, 0x09, 0xb2,
+ 0x44, 0x6d, 0xa2, 0x44,
+ 0x48, 0xa5, 0x36, 0x00,
+ 0xe5, 0x8f, 0x01, 0xc0,
+ 0x20, 0x00, 0xa2, 0x64,
+ 0x20, 0x0c, 0x12, 0x0c,
+ 0x49, 0x92, 0x64, 0x10,
+ 0x1d, 0xf0, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0x41,
+ 0x0e, 0xe1, 0x0c, 0x13,
+ 0x42, 0x24, 0x10, 0x0c,
+ 0x02, 0x0b, 0x44, 0x40,
+ 0x23, 0x83, 0x1d, 0xf0,
+ 0x36, 0x41, 0x00, 0x21,
+ 0x09, 0xe1, 0x82, 0x02,
+ 0xb5, 0x92, 0x22, 0x2c,
+ 0x66, 0x18, 0x0a, 0x26,
+ 0x19, 0x07, 0x0c, 0x09,
+ 0x92, 0x42, 0xb5, 0x92,
+ 0x62, 0x2c, 0x8c, 0x79,
+ 0x26, 0x19, 0x05, 0x26,
+ 0x29, 0x27, 0x26, 0x39,
+ 0x01, 0x1d, 0xf0, 0x0c,
+ 0x29, 0xa1, 0x48, 0xe2,
+ 0xb1, 0x47, 0xe2, 0x0c,
+ 0x6c, 0xd2, 0xa2, 0x00,
+ 0x0c, 0x9e, 0xe2, 0x42,
+ 0xb8, 0xd2, 0x62, 0x2f,
+ 0xc2, 0x62, 0x30, 0xb2,
+ 0x62, 0x33, 0xa2, 0x62,
+ 0x34, 0x92, 0x62, 0x2c,
+ 0x1d, 0xf0, 0x25, 0xfa,
+ 0xff, 0x16, 0x4a, 0xfd,
+ 0xa1, 0x40, 0xe2, 0xb2,
+ 0x22, 0x34, 0x65, 0xf4,
+ 0xff, 0x0c, 0x1f, 0xf2,
+ 0x62, 0x2c, 0x1d, 0xf0,
+ 0x36, 0x41, 0x00, 0x41,
+ 0xf5, 0xe0, 0x31, 0xf3,
+ 0xe0, 0x0c, 0x18, 0x32,
+ 0x03, 0xc1, 0x40, 0x33,
+ 0xa0, 0x32, 0x23, 0x7f,
+ 0x0c, 0x02, 0x48, 0x83,
+ 0x29, 0x43, 0x80, 0x44,
+ 0x20, 0x49, 0x83, 0x1d,
+ 0xf0, 0x00, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0x31,
+ 0xe8, 0xe0, 0x0c, 0x02,
+ 0x22, 0x63, 0x2c, 0x1d,
+ 0xf0, 0x00, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0x31,
+ 0xe4, 0xe0, 0x0c, 0x02,
+ 0x22, 0x43, 0xb6, 0x22,
+ 0x63, 0x2c, 0x1d, 0xf0,
+ 0x36, 0x41, 0x00, 0xc1,
+ 0xe0, 0xe0, 0x82, 0xa1,
+ 0x90, 0x92, 0x0c, 0x65,
+ 0xa1, 0xe1, 0xe0, 0xf6,
+ 0x79, 0x22, 0xa2, 0x0a,
+ 0xc1, 0xb2, 0x2c, 0x11,
+ 0x1b, 0xd9, 0xd2, 0x4c,
+ 0x65, 0xb2, 0x0b, 0x00,
+ 0xb2, 0x4c, 0x48, 0xb1,
+ 0xdc, 0xe0, 0x0c, 0x5d,
+ 0xb0, 0xaa, 0xa0, 0xa2,
+ 0x2a, 0x7f, 0xd2, 0x6c,
+ 0x10, 0x89, 0x4a, 0x1d,
+ 0xf0, 0x25, 0x3d, 0x00,
+ 0x1d, 0xf0, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0x61,
+ 0x08, 0xe2, 0x0c, 0x15,
+ 0x42, 0x26, 0x24, 0x32,
+ 0x06, 0x7e, 0x20, 0x44,
+ 0x20, 0x42, 0x66, 0x24,
+ 0x07, 0x63, 0x0a, 0x22,
+ 0x46, 0x7f, 0x82, 0xa0,
+ 0xa0, 0xc0, 0x20, 0x00,
+ 0x59, 0x08, 0x1d, 0xf0,
+ 0x36, 0x41, 0x00, 0x0c,
+ 0x44, 0x21, 0xc7, 0xe0,
+ 0x0c, 0x03, 0xa2, 0x22,
+ 0x11, 0x32, 0x42, 0x64,
+ 0xc2, 0x0a, 0x00, 0xb2,
+ 0x02, 0x48, 0x37, 0x6c,
+ 0x1b, 0x16, 0xbb, 0x07,
+ 0x0b, 0x8b, 0x16, 0xf8,
+ 0x1e, 0x92, 0xcb, 0xfe,
+ 0x16, 0xe9, 0x0d, 0x32,
+ 0x62, 0x1a, 0x32, 0x42,
+ 0x6c, 0x32, 0x42, 0x6d,
+ 0x65, 0x37, 0x00, 0x1d,
+ 0xf0, 0xb0, 0x90, 0x14,
+ 0xec, 0x29, 0x0c, 0x2d,
+ 0x0c, 0xcf, 0xf0, 0xeb,
+ 0x10, 0xf7, 0x0b, 0x21,
+ 0x82, 0xce, 0xfc, 0x16,
+ 0x48, 0x17, 0x92, 0xce,
+ 0xf8, 0x16, 0xa9, 0x13,
+ 0x32, 0x62, 0x1a, 0x32,
+ 0x42, 0x6c, 0x32, 0x42,
+ 0x6d, 0xe5, 0x34, 0x00,
+ 0x1d, 0xf0, 0x66, 0x29,
+ 0x02, 0xe5, 0xf3, 0xff,
+ 0x1d, 0xf0, 0xc0, 0x90,
+ 0x14, 0x0b, 0xb9, 0x56,
+ 0xcb, 0x09, 0xc2, 0x02,
+ 0x50, 0xc2, 0x42, 0x66,
+ 0xe6, 0x1c, 0x02, 0xc6,
+ 0x2e, 0x00, 0xed, 0x02,
+ 0xb8, 0x3a, 0x2a, 0xfc,
+ 0x98, 0x5a, 0x82, 0x0e,
+ 0x51, 0xba, 0x99, 0x82,
+ 0x49, 0x00, 0xb8, 0x3a,
+ 0x1b, 0xee, 0x1b, 0xbb,
+ 0xb9, 0x3a, 0xf7, 0x9e,
+ 0xea, 0x46, 0x27, 0x00,
+ 0xc0, 0x90, 0x24, 0xc2,
+ 0x02, 0x66, 0x66, 0x19,
+ 0x2b, 0xf2, 0x02, 0x50,
+ 0xa6, 0x1f, 0x1a, 0xdd,
+ 0x02, 0xb8, 0x3a, 0x2a,
+ 0xef, 0x98, 0x5a, 0x82,
+ 0x0d, 0x51, 0xba, 0x99,
+ 0x82, 0x49, 0x00, 0xb8,
+ 0x3a, 0x1b, 0xdd, 0x1b,
+ 0xbb, 0xb9, 0x3a, 0xe7,
+ 0x9d, 0xea, 0xf7, 0x1c,
+ 0x0f, 0x32, 0x62, 0x1a,
+ 0xe5, 0x2d, 0x00, 0x1d,
+ 0xf0, 0xcc, 0x49, 0xb8,
+ 0x3a, 0xca, 0xbb, 0xb9,
+ 0x3a, 0xd2, 0x22, 0x1a,
+ 0xc0, 0xdd, 0xc0, 0xd2,
+ 0x62, 0x1a, 0x16, 0xdd,
+ 0x13, 0x32, 0x42, 0x64,
+ 0x32, 0x42, 0x65, 0xe2,
+ 0x22, 0x13, 0xa2, 0x0a,
+ 0x00, 0xa2, 0x42, 0x48,
+ 0xca, 0xee, 0xe2, 0x62,
+ 0x13, 0x65, 0x14, 0x00,
+ 0xa5, 0x6d, 0x01, 0xc0,
+ 0x20, 0x00, 0xa2, 0x62,
+ 0x20, 0x42, 0x62, 0x10,
+ 0x1d, 0xf0, 0xa5, 0xe9,
+ 0xff, 0x1d, 0xf0, 0xec,
+ 0x49, 0xb8, 0x3a, 0xf2,
+ 0x02, 0x50, 0x92, 0x02,
+ 0x6c, 0x16, 0x0f, 0x11,
+ 0x32, 0x42, 0x64, 0x32,
+ 0x42, 0x65, 0xd2, 0x42,
+ 0x48, 0x82, 0x02, 0x51,
+ 0x82, 0x42, 0x6c, 0x90,
+ 0x88, 0xc0, 0x8a, 0x8b,
+ 0x89, 0x3a, 0xd2, 0x62,
+ 0x10, 0x1d, 0xf0, 0xc2,
+ 0x02, 0x66, 0x92, 0x22,
+ 0x1a, 0xb2, 0x02, 0x6e,
+ 0xc0, 0x99, 0xc0, 0x92,
+ 0x62, 0x1a, 0x9c, 0xb9,
+ 0x32, 0x42, 0x64, 0x32,
+ 0x42, 0x65, 0xa2, 0x0a,
+ 0x00, 0xa2, 0x42, 0x48,
+ 0xa5, 0x0e, 0x00, 0x25,
+ 0x68, 0x01, 0xdd, 0x04,
+ 0xc0, 0x20, 0x00, 0xa2,
+ 0x62, 0x20, 0x06, 0xf3,
+ 0xff, 0x66, 0x1b, 0x0e,
+ 0x32, 0x42, 0x6e, 0x0c,
+ 0x1c, 0xd8, 0x2a, 0xd2,
+ 0x62, 0x1a, 0xc2, 0x4a,
+ 0x00, 0x1d, 0xf0, 0xe2,
+ 0x02, 0x6d, 0x66, 0x1e,
+ 0x40, 0xf2, 0x0a, 0x10,
+ 0x66, 0x1f, 0x3a, 0x32,
+ 0x42, 0x6d, 0x82, 0x0a,
+ 0x00, 0x82, 0x42, 0x48,
+ 0x86, 0xe8, 0xff, 0x92,
+ 0x02, 0x65, 0x0c, 0x5e,
+ 0xf6, 0x79, 0x69, 0xa2,
+ 0xa1, 0x90, 0xc0, 0xf0,
+ 0x14, 0xb1, 0x65, 0xe0,
+ 0xf0, 0xdc, 0x93, 0xf1,
+ 0x65, 0xe0, 0xb2, 0x0b,
+ 0xc1, 0x1b, 0x89, 0xf0,
+ 0xbb, 0xa0, 0xb2, 0x2b,
+ 0x7f, 0x82, 0x42, 0x65,
+ 0xa9, 0x4b, 0xd2, 0x42,
+ 0x48, 0xe2, 0x62, 0x10,
+ 0x1d, 0xf0, 0xe5, 0x1e,
+ 0x00, 0x1d, 0xf0, 0x82,
+ 0x02, 0x50, 0x9c, 0xf8,
+ 0xc2, 0x42, 0x48, 0xd2,
+ 0x62, 0x10, 0x32, 0x62,
+ 0x1a, 0x32, 0x42, 0x6d,
+ 0x98, 0x3a, 0xb2, 0x02,
+ 0x51, 0xe2, 0x02, 0x6c,
+ 0x32, 0x42, 0x6c, 0xe0,
+ 0xbb, 0xc0, 0xba, 0x99,
+ 0x99, 0x3a, 0x46, 0x01,
+ 0x00, 0xb2, 0x4a, 0x00,
+ 0xe5, 0x1b, 0x00, 0xf2,
+ 0x02, 0x6e, 0x0b, 0xff,
+ 0x56, 0x0f, 0xe7, 0x82,
+ 0x22, 0x11, 0x32, 0x42,
+ 0x6e, 0x39, 0x38, 0x1d,
+ 0xf0, 0x92, 0x02, 0x6d,
+ 0x66, 0x19, 0x20, 0x32,
+ 0x62, 0x1a, 0x32, 0x42,
+ 0x6c, 0x32, 0x42, 0x6d,
+ 0xdd, 0x0c, 0x06, 0xe8,
+ 0xff, 0xc8, 0x3a, 0xb2,
+ 0x02, 0x51, 0xca, 0xbb,
+ 0xb9, 0x3a, 0xe5, 0x18,
+ 0x00, 0x1d, 0xf0, 0xa5,
+ 0x18, 0x00, 0x1d, 0xf0,
+ 0x25, 0x18, 0x00, 0x1d,
+ 0xf0, 0xc2, 0x02, 0x66,
+ 0x32, 0x42, 0x6c, 0x90,
+ 0xec, 0xc0, 0xea, 0xeb,
+ 0xe9, 0x3a, 0x06, 0xbf,
+ 0xff, 0x00, 0x00, 0x00,
+ 0x36, 0x61, 0x00, 0x0c,
+ 0x07, 0xb1, 0x38, 0xe0,
+ 0x1c, 0x0a, 0xc2, 0x2b,
+ 0x13, 0xd2, 0x2b, 0x1a,
+ 0xc0, 0x68, 0x74, 0xd0,
+ 0xaa, 0x63, 0xc0, 0x40,
+ 0x74, 0xd2, 0x2b, 0x11,
+ 0xa0, 0x30, 0x74, 0xa0,
+ 0x90, 0x74, 0x92, 0x4b,
+ 0x66, 0x37, 0xe2, 0x15,
+ 0x0c, 0x48, 0xf2, 0x0b,
+ 0x6d, 0xe2, 0xa0, 0xfb,
+ 0xe0, 0xe2, 0x10, 0x0b,
+ 0xff, 0x80, 0x22, 0x20,
+ 0x20, 0x20, 0x74, 0xf0,
+ 0x2e, 0x93, 0x0c, 0x28,
+ 0xf2, 0x0d, 0x00, 0x80,
+ 0x82, 0x10, 0x80, 0x37,
+ 0x93, 0x7d, 0x01, 0x07,
+ 0xef, 0x18, 0x9c, 0x59,
+ 0x5d, 0x01, 0xe8, 0x3d,
+ 0xa8, 0x5d, 0x1a, 0xb9,
+ 0xea, 0xaa, 0xf2, 0x0a,
+ 0x00, 0x1b, 0xaa, 0xf2,
+ 0x45, 0x00, 0x1b, 0x55,
+ 0xb7, 0x95, 0xf2, 0xc0,
+ 0xc0, 0x75, 0xc0, 0xb2,
+ 0x11, 0xa1, 0x47, 0xe1,
+ 0xc0, 0xbb, 0x20, 0xc2,
+ 0xa1, 0x00, 0xc0, 0xbb,
+ 0x20, 0xe5, 0x25, 0x00,
+ 0xbd, 0x06, 0xa1, 0x43,
+ 0xe1, 0x65, 0x25, 0x00,
+ 0x62, 0xa2, 0x00, 0xcc,
+ 0x93, 0x60, 0xb4, 0x20,
+ 0xa1, 0x40, 0xe1, 0xa5,
+ 0x24, 0x00, 0x1d, 0xf0,
+ 0xbd, 0x04, 0xa1, 0x3d,
+ 0xe1, 0xe5, 0x23, 0x00,
+ 0x0b, 0x43, 0x07, 0xe2,
+ 0x32, 0xa1, 0x3a, 0xe1,
+ 0xbd, 0x04, 0x25, 0x23,
+ 0x00, 0x9c, 0x54, 0x5d,
+ 0x01, 0x0b, 0x23, 0x7a,
+ 0x34, 0xa1, 0x36, 0xe1,
+ 0xb2, 0x05, 0x00, 0x25,
+ 0x22, 0x00, 0x1b, 0x55,
+ 0x37, 0x95, 0xf1, 0x46,
+ 0x00, 0x00, 0x0c, 0x02,
+ 0x7a, 0xb2, 0xb2, 0x0b,
+ 0x00, 0xa1, 0x30, 0xe1,
+ 0x60, 0xbb, 0x20, 0xa5,
+ 0x20, 0x00, 0x1d, 0xf0,
+ 0x60, 0xb4, 0x20, 0xa1,
+ 0x2d, 0xe1, 0xe5, 0x1f,
+ 0x00, 0x1d, 0xf0, 0x00,
+ 0x36, 0x41, 0x00, 0xa1,
+ 0x2b, 0xe1, 0x65, 0x1e,
+ 0x00, 0x22, 0xa2, 0x00,
+ 0x0c, 0x0b, 0x31, 0xfe,
+ 0xdf, 0xa0, 0x84, 0x34,
+ 0x82, 0x43, 0x48, 0xb2,
+ 0x43, 0x50, 0x20, 0xca,
+ 0x10, 0x27, 0x8a, 0x1e,
+ 0xf6, 0xbb, 0x1b, 0xa1,
+ 0x23, 0xe1, 0x65, 0x1c,
+ 0x00, 0xc2, 0x03, 0x50,
+ 0x3a, 0xcc, 0xa2, 0x4c,
+ 0x51, 0xb2, 0x03, 0x50,
+ 0x1b, 0xbb, 0xb0, 0xb0,
+ 0x74, 0xb2, 0x43, 0x50,
+ 0x86, 0xf6, 0xff, 0xcc,
+ 0x3c, 0x0c, 0x3d, 0xd2,
+ 0x43, 0x48, 0xa1, 0x3b,
+ 0xe1, 0x0c, 0x1b, 0xe5,
+ 0x1a, 0x00, 0x1d, 0xf0,
+ 0x36, 0x41, 0x00, 0x21,
+ 0xed, 0xdf, 0x32, 0x02,
+ 0x75, 0x26, 0x13, 0x03,
+ 0x0c, 0x02, 0x1d, 0xf0,
+ 0x0c, 0x08, 0x82, 0x42,
+ 0x75, 0x0c, 0x12, 0x1d,
+ 0xf0, 0x00, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0x91,
+ 0xe6, 0xdf, 0x0c, 0x18,
+ 0x22, 0x49, 0xb4, 0x82,
+ 0x49, 0xb5, 0x66, 0x12,
+ 0x06, 0x0c, 0x9a, 0x25,
+ 0xc4, 0xff, 0x1d, 0xf0,
+ 0x0c, 0x2a, 0xa5, 0xc3,
+ 0xff, 0x1d, 0xf0, 0x00,
+ 0x36, 0x41, 0x00, 0x21,
+ 0xde, 0xdf, 0xb2, 0x22,
+ 0x1c, 0x8c, 0xfb, 0xa2,
+ 0x22, 0x11, 0x82, 0x02,
+ 0x48, 0x82, 0x4a, 0x00,
+ 0xe0, 0x0b, 0x00, 0x0c,
+ 0x09, 0x92, 0x62, 0x1c,
+ 0x0c, 0x1a, 0xa2, 0x62,
+ 0x10, 0x1d, 0xf0, 0x00,
+ 0x36, 0x41, 0x00, 0x21,
+ 0xd5, 0xdf, 0x0c, 0x04,
+ 0x82, 0x02, 0x76, 0x92,
+ 0x22, 0x10, 0x8c, 0xe8,
+ 0x42, 0x42, 0x76, 0x8c,
+ 0x99, 0x65, 0xfc, 0xff,
+ 0x42, 0x62, 0x10, 0x0c,
+ 0x0a, 0xe5, 0xf9, 0xff,
+ 0xa2, 0x02, 0x77, 0xb2,
+ 0x22, 0x10, 0x8c, 0xea,
+ 0x42, 0x42, 0x77, 0xcc,
+ 0x9b, 0xe5, 0xfa, 0xff,
+ 0x0c, 0x1a, 0xa2, 0x62,
+ 0x10, 0x65, 0xf8, 0xff,
+ 0x92, 0x22, 0x10, 0xac,
+ 0x09, 0x26, 0x19, 0x1e,
+ 0x0c, 0x43, 0x26, 0x39,
+ 0x4c, 0xc2, 0xc9, 0xfe,
+ 0x16, 0xfc, 0x0b, 0x26,
+ 0x49, 0x12, 0x26, 0x59,
+ 0x5d, 0xd2, 0xc9, 0xfa,
+ 0x16, 0x9d, 0x0a, 0x66,
+ 0x79, 0x04, 0x25, 0xf8,
+ 0xff, 0x1d, 0xf0, 0x1d,
+ 0xf0, 0xe2, 0x02, 0x74,
+ 0x66, 0x1e, 0x11, 0x42,
+ 0x42, 0x74, 0xa1, 0x07,
+ 0xe1, 0x0c, 0x1b, 0xa5,
+ 0x0d, 0x00, 0x0c, 0x2f,
+ 0xf2, 0x62, 0x10, 0x1d,
+ 0xf0, 0xe5, 0x38, 0x01,
+ 0xbd, 0x0a, 0xc0, 0x20,
+ 0x00, 0xa2, 0x22, 0x20,
+ 0xa5, 0x1c, 0x00, 0x81,
+ 0x01, 0xe1, 0xa7, 0xb8,
+ 0xd1, 0xe5, 0xf4, 0xff,
+ 0x1d, 0xf0, 0x65, 0x37,
+ 0x01, 0xbd, 0x0a, 0xa2,
+ 0x22, 0x1e, 0x65, 0x1b,
+ 0x00, 0x4d, 0x0a, 0x25,
+ 0xf0, 0xff, 0x66, 0x1a,
+ 0x1d, 0xa5, 0xea, 0xff,
+ 0x0c, 0x69, 0x3d, 0x09,
+ 0x86, 0x03, 0x00, 0xa2,
+ 0x02, 0x48, 0xe5, 0xdb,
+ 0xff, 0x25, 0x35, 0x01,
+ 0xc0, 0x20, 0x00, 0xa2,
+ 0x62, 0x20, 0x32, 0x62,
+ 0x10, 0x1d, 0xf0, 0xa2,
+ 0x22, 0x1f, 0x92, 0xa1,
+ 0x8f, 0xa0, 0xa4, 0xc2,
+ 0xa7, 0xb9, 0x8f, 0xb2,
+ 0x02, 0x64, 0xf6, 0x5b,
+ 0x30, 0xa1, 0xec, 0xe0,
+ 0x0c, 0x1b, 0xe5, 0x06,
+ 0x00, 0xa1, 0xe9, 0xe0,
+ 0x0c, 0x1b, 0x65, 0x06,
+ 0x00, 0xc2, 0x02, 0x64,
+ 0xa2, 0x02, 0x48, 0x1b,
+ 0xcc, 0xc2, 0x42, 0x64,
+ 0xe5, 0xd7, 0xff, 0x65,
+ 0x31, 0x01, 0x9d, 0x03,
+ 0xc0, 0x20, 0x00, 0xa2,
+ 0x62, 0x20, 0x06, 0xea,
+ 0xff, 0x25, 0xb3, 0xff,
+ 0x1d, 0xf0, 0x0c, 0x79,
+ 0x86, 0xe7, 0xff, 0xe5,
+ 0x2f, 0x01, 0xa2, 0x62,
+ 0x1e, 0x0c, 0x33, 0xc6,
+ 0xe9, 0xff, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0x41,
+ 0x93, 0xdf, 0x31, 0x91,
+ 0xdf, 0x0c, 0x18, 0x32,
+ 0x03, 0xc1, 0x40, 0x33,
+ 0xa0, 0x32, 0x23, 0x7f,
+ 0x0c, 0x02, 0x48, 0x83,
+ 0x29, 0x43, 0x80, 0x44,
+ 0x20, 0x49, 0x83, 0x1d,
+ 0xf0, 0x00, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0xc0,
+ 0x20, 0x00, 0x28, 0x02,
+ 0x1d, 0xf0, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0xc0,
+ 0x20, 0x00, 0x39, 0x02,
+ 0x1d, 0xf0, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0xa1,
+ 0xce, 0xe0, 0x0c, 0x2c,
+ 0x21, 0x7f, 0xdf, 0x0c,
+ 0x0d, 0xd2, 0x62, 0x10,
+ 0xd2, 0x42, 0x74, 0xb2,
+ 0x22, 0x1f, 0xd2, 0x42,
+ 0x75, 0xc0, 0xbb, 0xd2,
+ 0x0b, 0xbb, 0x65, 0xfd,
+ 0xff, 0xa1, 0xc7, 0xe0,
+ 0xb2, 0x22, 0x1f, 0xc2,
+ 0xa0, 0x64, 0xc0, 0xbb,
+ 0x82, 0x5c, 0x3c, 0xc0,
+ 0xbb, 0xd2, 0x25, 0xfc,
+ 0xff, 0xa1, 0xc3, 0xe0,
+ 0xb2, 0x22, 0x1f, 0xc2,
+ 0xa0, 0x64, 0xc0, 0xbb,
+ 0x82, 0xc2, 0xa0, 0x7d,
+ 0xc0, 0xbb, 0xd2, 0xe5,
+ 0xfa, 0xff, 0xa1, 0x96,
+ 0xe0, 0xa5, 0xf9, 0xff,
+ 0x0c, 0x4b, 0xb0, 0xba,
+ 0x20, 0xa1, 0x93, 0xe0,
+ 0xa5, 0xf9, 0xff, 0xa1,
+ 0xb6, 0xe0, 0x0c, 0x1b,
+ 0x25, 0xf9, 0xff, 0xa1,
+ 0xb3, 0xe0, 0x0c, 0x1b,
+ 0xa5, 0xf8, 0xff, 0xa1,
+ 0xb7, 0xe0, 0x0c, 0x1b,
+ 0x25, 0xf8, 0xff, 0xa1,
+ 0x6b, 0xdf, 0x25, 0xf7,
+ 0xff, 0x47, 0x6a, 0x04,
+ 0x0c, 0x1c, 0xc2, 0x42,
+ 0x77, 0x1d, 0xf0, 0x00,
+ 0x36, 0x41, 0x00, 0x0c,
+ 0x04, 0x31, 0x5e, 0xdf,
+ 0xc0, 0x20, 0x00, 0x92,
+ 0x13, 0x0a, 0x88, 0x32,
+ 0x0b, 0x99, 0x97, 0x18,
+ 0x0c, 0x0c, 0x0a, 0x65,
+ 0x01, 0x00, 0xc0, 0x20,
+ 0x00, 0x42, 0x43, 0x08,
+ 0x1d, 0xf0, 0xc0, 0x20,
+ 0x00, 0x42, 0x43, 0x08,
+ 0x1d, 0xf0, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0x0c,
+ 0x13, 0x81, 0x53, 0xdf,
+ 0x20, 0x42, 0xf0, 0x80,
+ 0x44, 0xa0, 0xc0, 0x20,
+ 0x00, 0x39, 0x14, 0x1d,
+ 0xf0, 0x00, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0x0c,
+ 0x04, 0x31, 0x4d, 0xdf,
+ 0xc0, 0x20, 0x00, 0x92,
+ 0x13, 0x0a, 0x88, 0x32,
+ 0x97, 0x18, 0x0c, 0x0c,
+ 0x0a, 0x25, 0xfd, 0xff,
+ 0xc0, 0x20, 0x00, 0x42,
+ 0x43, 0x08, 0x1d, 0xf0,
+ 0xc0, 0x20, 0x00, 0x42,
+ 0x43, 0x08, 0x1d, 0xf0,
+ 0x36, 0x41, 0x00, 0xc0,
+ 0x20, 0x00, 0x39, 0x02,
+ 0x1d, 0xf0, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0x37,
+ 0xb2, 0x04, 0x20, 0x23,
+ 0xc0, 0x1d, 0xf0, 0x30,
+ 0x22, 0xc0, 0x0b, 0x22,
+ 0x1d, 0xf0, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0xc0,
+ 0x20, 0x00, 0x39, 0x02,
+ 0x1d, 0xf0, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0x41,
+ 0x3d, 0xdf, 0x81, 0x32,
+ 0xe0, 0x0c, 0x03, 0x52,
+ 0x08, 0x80, 0x40, 0x55,
+ 0xa0, 0x22, 0x65, 0x7f,
+ 0x52, 0x08, 0x80, 0x40,
+ 0x45, 0xa0, 0x42, 0x24,
+ 0x7f, 0x1b, 0x55, 0x52,
+ 0x48, 0x80, 0x39, 0x44,
+ 0x39, 0x54, 0x39, 0x64,
+ 0x32, 0x44, 0x1c, 0x39,
+ 0x84, 0x39, 0x94, 0x1d,
+ 0xf0, 0x00, 0x00, 0x00,
+ 0x36, 0x61, 0x00, 0x10,
+ 0x4d, 0x40, 0xf8, 0x02,
+ 0xe8, 0x12, 0xd0, 0x8f,
+ 0x11, 0xf0, 0xa5, 0x75,
+ 0xf0, 0x9d, 0xf4, 0x92,
+ 0x41, 0x05, 0xa2, 0x41,
+ 0x04, 0x82, 0x41, 0x07,
+ 0xf0, 0xee, 0x81, 0x80,
+ 0x88, 0x41, 0x82, 0x41,
+ 0x06, 0xe2, 0x41, 0x03,
+ 0xe0, 0xc8, 0x41, 0xe0,
+ 0xd0, 0xf5, 0xd2, 0x41,
+ 0x01, 0xc2, 0x41, 0x02,
+ 0xe0, 0xe8, 0x75, 0xe2,
+ 0x41, 0x00, 0xb8, 0x02,
+ 0x3c, 0x78, 0xb0, 0xb0,
+ 0x54, 0xb7, 0x38, 0x47,
+ 0x3c, 0x8a, 0xb0, 0xca,
+ 0xc0, 0xad, 0x02, 0xb1,
+ 0x83, 0xdf, 0x65, 0x04,
+ 0x00, 0xad, 0x02, 0xbd,
+ 0x01, 0x0c, 0x8c, 0xe5,
+ 0x03, 0x00, 0xa1, 0x68,
+ 0xe0, 0xb1, 0x68, 0xe0,
+ 0xc0, 0x20, 0x00, 0xc2,
+ 0x2a, 0x7f, 0x4b, 0xaa,
+ 0xc2, 0x43, 0x03, 0xc0,
+ 0xd0, 0xf5, 0xc0, 0xe8,
+ 0x75, 0xe2, 0x43, 0x00,
+ 0xd2, 0x43, 0x01, 0xc0,
+ 0xc8, 0x41, 0xc2, 0x43,
+ 0x02, 0x4b, 0x33, 0xb7,
+ 0x9a, 0xdd, 0xa1, 0x60,
+ 0xe0, 0x0c, 0x0b, 0x65,
+ 0x3b, 0xf8, 0x1d, 0xf0,
+ 0xa2, 0xa0, 0x78, 0xc6,
+ 0xec, 0xff, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0x16,
+ 0x34, 0x06, 0x88, 0x02,
+ 0x98, 0x12, 0x80, 0x50,
+ 0x54, 0x4a, 0x88, 0x89,
+ 0x02, 0x47, 0xb8, 0x03,
+ 0x1b, 0x99, 0x99, 0x12,
+ 0xac, 0x35, 0x4c, 0x0c,
+ 0x50, 0xcc, 0xc0, 0xc7,
+ 0x34, 0x1c, 0xbd, 0x03,
+ 0x5a, 0xa2, 0x8b, 0xaa,
+ 0x65, 0xea, 0x00, 0xad,
+ 0x02, 0x8b, 0xb2, 0x25,
+ 0x41, 0xf8, 0x5a, 0x44,
+ 0x50, 0x33, 0xc0, 0x32,
+ 0xc3, 0x40, 0x42, 0xc4,
+ 0xc0, 0x0c, 0x05, 0x6d,
+ 0x04, 0xb6, 0xd4, 0x18,
+ 0x40, 0x76, 0x41, 0xad,
+ 0x02, 0xbd, 0x03, 0x65,
+ 0x3f, 0xf8, 0x32, 0xc3,
+ 0x40, 0x42, 0xc4, 0xc0,
+ 0xf6, 0xd4, 0xef, 0xa0,
+ 0x47, 0x11, 0x40, 0x46,
+ 0xc0, 0x8c, 0x94, 0xcd,
+ 0x04, 0xbd, 0x03, 0x5a,
+ 0xa2, 0x8b, 0xaa, 0xa5,
+ 0xe6, 0x00, 0x1d, 0xf0,
+ 0x36, 0x41, 0x00, 0x0c,
+ 0x04, 0x5d, 0x02, 0x0c,
+ 0x02, 0x1b, 0x44, 0x50,
+ 0x30, 0x04, 0x30, 0x22,
+ 0x30, 0x50, 0x51, 0x41,
+ 0x66, 0xb4, 0xf1, 0x1d,
+ 0xf0, 0x00, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0xa1,
+ 0x39, 0xe0, 0x0c, 0x0b,
+ 0x65, 0x31, 0xf8, 0xa1,
+ 0x37, 0xe0, 0x0c, 0x1b,
+ 0xe5, 0x30, 0xf8, 0x32,
+ 0x62, 0x32, 0x0c, 0x08,
+ 0x89, 0x02, 0x89, 0x12,
+ 0x1d, 0xf0, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0x65,
+ 0x02, 0x01, 0x31, 0xe0,
+ 0xde, 0x71, 0xdb, 0xde,
+ 0x0c, 0x14, 0x21, 0x2f,
+ 0xe0, 0x4c, 0x86, 0xa2,
+ 0x62, 0x20, 0x25, 0x01,
+ 0x01, 0x5d, 0x0a, 0xa2,
+ 0x22, 0x20, 0xbd, 0x05,
+ 0xe5, 0xe4, 0xff, 0x52,
+ 0x62, 0x20, 0x52, 0x27,
+ 0x1f, 0xb2, 0x02, 0x7c,
+ 0x50, 0x5a, 0xc2, 0x0c,
+ 0x0a, 0xa2, 0x42, 0x7d,
+ 0x16, 0xeb, 0x08, 0x30,
+ 0xaa, 0xa0, 0xa2, 0x2a,
+ 0x7f, 0x98, 0x9a, 0x9c,
+ 0xc9, 0x66, 0x19, 0x30,
+ 0x88, 0x1a, 0xa2, 0x0a,
+ 0x28, 0xe0, 0x08, 0x00,
+ 0xa1, 0xce, 0xde, 0xa2,
+ 0x0a, 0xc1, 0x30, 0xaa,
+ 0xa0, 0xa2, 0x2a, 0x7f,
+ 0x0c, 0x29, 0x99, 0x9a,
+ 0x46, 0x05, 0x00, 0x88,
+ 0x0a, 0xa2, 0x0a, 0x28,
+ 0xe0, 0x08, 0x00, 0xa1,
+ 0xc7, 0xde, 0xa2, 0x0a,
+ 0xc1, 0x30, 0xaa, 0xa0,
+ 0xa2, 0x2a, 0x7f, 0x49,
+ 0x9a, 0xb8, 0x6a, 0x98,
+ 0x4a, 0x66, 0x1b, 0x0d,
+ 0xc8, 0x5a, 0x50, 0xcc,
+ 0xc0, 0xc9, 0x5a, 0xe6,
+ 0x1c, 0x03, 0x0c, 0x2d,
+ 0xd9, 0x6a, 0xa6, 0x19,
+ 0x17, 0x50, 0xe9, 0xc0,
+ 0xe9, 0x4a, 0xe6, 0x1e,
+ 0x1c, 0xf8, 0x8a, 0x07,
+ 0x6f, 0x17, 0x88, 0x2a,
+ 0xa2, 0x0a, 0x28, 0xe0,
+ 0x08, 0x00, 0x06, 0x03,
+ 0x00, 0x98, 0x8a, 0x07,
+ 0x69, 0x07, 0x88, 0x2a,
+ 0xa2, 0x0a, 0x28, 0xe0,
+ 0x08, 0x00, 0xa2, 0x02,
+ 0x7d, 0x92, 0x02, 0x7c,
+ 0x1b, 0xaa, 0xa0, 0xa0,
+ 0x74, 0xa2, 0x42, 0x7d,
+ 0x97, 0xba, 0x02, 0x06,
+ 0xdc, 0xff, 0xc0, 0x20,
+ 0x00, 0x49, 0x06, 0xa2,
+ 0xa0, 0xe0, 0xb1, 0x00,
+ 0xe0, 0x25, 0xdb, 0xff,
+ 0x86, 0xcf, 0xff, 0x00,
+ 0x36, 0x41, 0x00, 0x0c,
+ 0x0a, 0x65, 0xb1, 0x00,
+ 0x1d, 0xf0, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0xbd,
+ 0x02, 0xa2, 0xa0, 0xd8,
+ 0x65, 0xd9, 0xff, 0xbd,
+ 0x03, 0xa2, 0xa0, 0xdc,
+ 0xe5, 0xd8, 0xff, 0x1d,
+ 0xf0, 0x00, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0x0c,
+ 0x0b, 0x0c, 0x7c, 0xd1,
+ 0xf7, 0xdf, 0xe1, 0xf5,
+ 0xdf, 0xa1, 0xf2, 0xdf,
+ 0xf1, 0xf3, 0xdf, 0xf2,
+ 0x6a, 0x1c, 0xe2, 0x6a,
+ 0x1d, 0xd2, 0x6a, 0x1e,
+ 0xc2, 0x6a, 0x1f, 0xb2,
+ 0x4a, 0x8c, 0xa2, 0xca,
+ 0x70, 0xe5, 0xd6, 0xff,
+ 0x1d, 0xf0, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0xb1,
+ 0xee, 0xdf, 0xc1, 0xee,
+ 0xdf, 0xd1, 0xee, 0xdf,
+ 0x91, 0xef, 0xdf, 0xa1,
+ 0xef, 0xdf, 0x0c, 0x2e,
+ 0x0c, 0x33, 0x2c, 0xc8,
+ 0x80, 0x82, 0x82, 0x20,
+ 0x3e, 0x83, 0xaa, 0xa8,
+ 0x9a, 0x88, 0xd2, 0x68,
+ 0x7f, 0xc2, 0x68, 0x80,
+ 0xb2, 0x68, 0x81, 0x92,
+ 0xd8, 0x02, 0x22, 0x49,
+ 0x24, 0x32, 0x68, 0x82,
+ 0x25, 0xd3, 0xff, 0x1d,
+ 0xf0, 0x00, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0x51,
+ 0xea, 0xde, 0x0c, 0x03,
+ 0x42, 0xc5, 0x10, 0x32,
+ 0x64, 0x7f, 0x32, 0x65,
+ 0x7f, 0x4b, 0x44, 0x4b,
+ 0x55, 0x1b, 0x33, 0x66,
+ 0x43, 0xf0, 0x1d, 0xf0,
+ 0x36, 0x41, 0x00, 0x2c,
+ 0x8a, 0x7c, 0xeb, 0xe5,
+ 0xcd, 0xff, 0xa2, 0xa0,
+ 0x6c, 0x7c, 0xcb, 0x65,
+ 0xcd, 0xff, 0xa1, 0xd9,
+ 0xdf, 0x7c, 0xeb, 0xe5,
+ 0xcc, 0xff, 0xa1, 0xd8,
+ 0xdf, 0x7c, 0x2b, 0x65,
+ 0xcc, 0xff, 0xa1, 0xd7,
+ 0xdf, 0x7c, 0x5b, 0xe5,
+ 0xcb, 0xff, 0x0c, 0x3a,
+ 0xb1, 0xd6, 0xdf, 0x25,
+ 0xa1, 0x00, 0x0c, 0x8a,
+ 0xa5, 0xa1, 0x00, 0x1d,
+ 0xf0, 0x00, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0x21,
+ 0x6e, 0xde, 0xa1, 0xd1,
+ 0xdf, 0xb2, 0x22, 0x1f,
+ 0xc2, 0xa1, 0xf4, 0xc0,
+ 0xbb, 0x82, 0xa5, 0xb9,
+ 0xff, 0xa1, 0xce, 0xdf,
+ 0xb2, 0x22, 0x1f, 0xc2,
+ 0xa3, 0xe8, 0xc0, 0xbb,
+ 0x82, 0xa5, 0xb8, 0xff,
+ 0x1d, 0xf0, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0x21,
+ 0xca, 0xdf, 0x22, 0x02,
+ 0x80, 0xcc, 0xb2, 0x3c,
+ 0xc3, 0xc0, 0x20, 0x00,
+ 0x81, 0x61, 0xde, 0x38,
+ 0x03, 0x32, 0x68, 0x1f,
+ 0x1d, 0xf0, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0xa1,
+ 0xc4, 0xdf, 0xa5, 0x1b,
+ 0xfe, 0x2d, 0x0a, 0x4c,
+ 0xca, 0x20, 0xb0, 0x74,
+ 0x65, 0x02, 0x00, 0x20,
+ 0xb8, 0x41, 0x5c, 0x0a,
+ 0xe5, 0x01, 0x00, 0xa1,
+ 0xbf, 0xdf, 0x25, 0x1a,
+ 0xfe, 0x2d, 0x0a, 0x5c,
+ 0x4a, 0x20, 0xb0, 0x74,
+ 0xe5, 0x00, 0x00, 0x20,
+ 0xb8, 0x41, 0x5c, 0x8a,
+ 0x65, 0x00, 0x00, 0x1d,
+ 0xf0, 0x00, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0xc0,
+ 0x20, 0x00, 0x39, 0x02,
+ 0x1d, 0xf0, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0xa2,
+ 0xa0, 0xd4, 0xc0, 0x20,
+ 0x00, 0x7c, 0xe8, 0xb8,
+ 0x0a, 0x0c, 0x1c, 0x80,
+ 0x8b, 0x10, 0xc0, 0xbb,
+ 0x20, 0x20, 0xb8, 0x83,
+ 0x65, 0xc2, 0xff, 0x1d,
+ 0xf0, 0x00, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0x0c,
+ 0x0a, 0xa5, 0xfd, 0xff,
+ 0x0c, 0xca, 0x0c, 0x0b,
+ 0x65, 0xfc, 0xff, 0x1c,
+ 0x0a, 0x1c, 0x0b, 0x25,
+ 0xfc, 0xff, 0x3c, 0x0a,
+ 0x0c, 0x0b, 0xa5, 0xfb,
+ 0xff, 0x3c, 0x4a, 0x0c,
+ 0x0b, 0x25, 0xfb, 0xff,
+ 0x65, 0xf7, 0xff, 0xa5,
+ 0xf5, 0xff, 0xa1, 0xa3,
+ 0xdf, 0x0c, 0xcb, 0x0c,
+ 0x02, 0x81, 0x6f, 0xdf,
+ 0x92, 0xa0, 0xff, 0x92,
+ 0x48, 0x7e, 0x22, 0x68,
+ 0x20, 0x65, 0xf9, 0xff,
+ 0xa1, 0x9f, 0xdf, 0x0c,
+ 0x3b, 0xe5, 0xf8, 0xff,
+ 0xa1, 0x31, 0xdf, 0x3c,
+ 0xcb, 0x65, 0xf8, 0xff,
+ 0x65, 0xf0, 0xff, 0xa5,
+ 0xec, 0xff, 0xa5, 0xea,
+ 0xff, 0x0c, 0x09, 0xb1,
+ 0x83, 0xdf, 0xa1, 0x31,
+ 0xde, 0x22, 0x4b, 0x7c,
+ 0x22, 0x4b, 0x7d, 0xa0,
+ 0xb9, 0xa0, 0x22, 0x6b,
+ 0x7f, 0x1b, 0x99, 0x90,
+ 0x90, 0x74, 0x66, 0x79,
+ 0xf1, 0x0c, 0x0a, 0xe5,
+ 0xe4, 0xff, 0x0c, 0x1a,
+ 0x65, 0xe4, 0xff, 0xa5,
+ 0xe1, 0xff, 0xa2, 0xa0,
+ 0xe0, 0xb1, 0x79, 0xdf,
+ 0x65, 0xb9, 0xff, 0xa2,
+ 0xa0, 0x64, 0xb1, 0x8c,
+ 0xdf, 0xe5, 0xde, 0xff,
+ 0x0c, 0x1a, 0xa5, 0xf4,
+ 0xff, 0xa5, 0xdd, 0xff,
+ 0xe5, 0xcf, 0xff, 0x0c,
+ 0x12, 0x1d, 0xf0, 0x00,
+ 0x36, 0xa1, 0x00, 0x7d,
+ 0x04, 0x6d, 0x03, 0x16,
+ 0xb5, 0x0b, 0x29, 0x81,
+ 0x57, 0xb3, 0x06, 0x0c,
+ 0x02, 0x0c, 0x03, 0x1d,
+ 0xf0, 0x00, 0xad, 0x05,
+ 0xa5, 0x24, 0x00, 0x4d,
+ 0x0a, 0x16, 0xfa, 0x21,
+ 0x2c, 0x03, 0xf8, 0x81,
+ 0xa0, 0x33, 0xc0, 0x00,
+ 0x03, 0x40, 0x60, 0x80,
+ 0x91, 0x00, 0x1a, 0x40,
+ 0x00, 0x26, 0xa1, 0x70,
+ 0xd5, 0x81, 0xd0, 0xe0,
+ 0xf4, 0x00, 0x03, 0x40,
+ 0xf0, 0xf0, 0x91, 0x20,
+ 0xff, 0x20, 0x10, 0x40,
+ 0x40, 0xd0, 0x20, 0xf5,
+ 0x20, 0x58, 0xe2, 0x20,
+ 0x38, 0xc2, 0xbd, 0x03,
+ 0x30, 0xce, 0x82, 0xf0,
+ 0x55, 0x81, 0xad, 0x05,
+ 0xf0, 0xf0, 0xf4, 0xc7,
+ 0xb5, 0x0e, 0x0b, 0xb3,
+ 0x5a, 0xad, 0xd7, 0x3a,
+ 0x07, 0xc7, 0xba, 0x04,
+ 0xaa, 0xad, 0xb2, 0xc3,
+ 0xfe, 0xc0, 0x3a, 0xc0,
+ 0x20, 0x53, 0xc2, 0xad,
+ 0x05, 0x50, 0xce, 0x82,
+ 0x20, 0x33, 0xe2, 0x00,
+ 0x33, 0x11, 0x30, 0xff,
+ 0x20, 0x3d, 0x0f, 0xc7,
+ 0xbf, 0x0e, 0x0b, 0xa5,
+ 0xfa, 0x3d, 0xd7, 0x33,
+ 0x07, 0xc7, 0xb3, 0x04,
+ 0x3a, 0x3d, 0xa2, 0xc5,
+ 0xfe, 0xc0, 0x33, 0xc0,
+ 0x00, 0x14, 0x40, 0x00,
+ 0x2b, 0x11, 0x20, 0x2a,
+ 0x20, 0x00, 0xb7, 0xa1,
+ 0xad, 0x02, 0x65, 0x9d,
+ 0x00, 0xb7, 0x33, 0x13,
+ 0xb0, 0x83, 0xc0, 0x56,
+ 0x98, 0x18, 0x98, 0x81,
+ 0x00, 0x14, 0x40, 0x00,
+ 0x99, 0xa1, 0xa7, 0x39,
+ 0x02, 0xc6, 0x5e, 0x00,
+ 0x0b, 0x22, 0x0c, 0x03,
+ 0x1d, 0xf0, 0x29, 0x81,
+ 0x47, 0x33, 0x02, 0xc6,
+ 0x1f, 0x00, 0xad, 0x04,
+ 0x25, 0x19, 0x00, 0x16,
+ 0xda, 0x00, 0x28, 0x81,
+ 0x00, 0x1a, 0x40, 0x00,
+ 0x47, 0xa1, 0x20, 0x36,
+ 0x81, 0x00, 0x22, 0xa1,
+ 0x10, 0x40, 0x40, 0x40,
+ 0xa0, 0xf4, 0x40, 0xb0,
+ 0xf5, 0xb0, 0xf3, 0xc2,
+ 0xed, 0x0f, 0xf0, 0xca,
+ 0x82, 0xb0, 0x33, 0xe2,
+ 0x20, 0x33, 0x81, 0xdd,
+ 0x03, 0xc7, 0xb3, 0x0e,
+ 0x0b, 0xef, 0x4a, 0xd3,
+ 0x47, 0x3d, 0x07, 0xc7,
+ 0xbd, 0x04, 0xda, 0xd4,
+ 0xe2, 0xcf, 0xfe, 0xc0,
+ 0xdd, 0xc0, 0xb0, 0xcd,
+ 0xc2, 0xb0, 0xdd, 0xe2,
+ 0x00, 0xdd, 0x11, 0x20,
+ 0xb0, 0xf4, 0xd0, 0xbb,
+ 0x20, 0xc0, 0xda, 0x82,
+ 0xad, 0x0c, 0xd7, 0xbb,
+ 0x17, 0x0b, 0xac, 0x4a,
+ 0xbb, 0x47, 0x3b, 0x10,
+ 0xd7, 0xbb, 0x0d, 0x0c,
+ 0x03, 0x00, 0x2e, 0x11,
+ 0xa2, 0xcc, 0xfe, 0x20,
+ 0x2a, 0x20, 0x1d, 0xf0,
+ 0x00, 0x0c, 0x03, 0x00,
+ 0x2e, 0x11, 0x20, 0x2a,
+ 0x20, 0x1d, 0xf0, 0x00,
+ 0x00, 0x00, 0x0c, 0x14,
+ 0x70, 0x44, 0xc2, 0x70,
+ 0x74, 0x83, 0x4d, 0x07,
+ 0xad, 0x07, 0xa5, 0x10,
+ 0x00, 0x16, 0xfa, 0x0e,
+ 0x28, 0x81, 0x00, 0x1a,
+ 0x40, 0x2c, 0x09, 0xa0,
+ 0x99, 0xc0, 0x00, 0x47,
+ 0xa1, 0x40, 0xb0, 0xf5,
+ 0x00, 0x09, 0x40, 0x60,
+ 0x50, 0x91, 0x00, 0x1a,
+ 0x40, 0xb0, 0xf5, 0xc2,
+ 0xed, 0x0f, 0xb0, 0x55,
+ 0xe2, 0x20, 0x36, 0x81,
+ 0x40, 0xa0, 0xf4, 0x00,
+ 0x22, 0xa1, 0xf0, 0xda,
+ 0x82, 0x10, 0x40, 0x40,
+ 0x30, 0x55, 0x81, 0xcd,
+ 0x05, 0xd7, 0xb5, 0x0e,
+ 0x0b, 0xef, 0x4a, 0xc5,
+ 0x47, 0x3c, 0x07, 0xd7,
+ 0xbc, 0x04, 0xca, 0xc4,
+ 0xe2, 0xcf, 0xfe, 0x30,
+ 0x50, 0xf4, 0xd0, 0xcc,
+ 0xc0, 0xb0, 0x8c, 0xe2,
+ 0x00, 0x88, 0x11, 0xb0,
+ 0x3c, 0xc2, 0xdd, 0x03,
+ 0x80, 0x55, 0x20, 0x30,
+ 0xfa, 0x82, 0xcd, 0x05,
+ 0xf7, 0xb5, 0x0e, 0x0b,
+ 0xd3, 0x4a, 0xc5, 0x47,
+ 0x3c, 0x07, 0xf7, 0xbc,
+ 0x04, 0xca, 0xc4, 0xd2,
+ 0xc3, 0xfe, 0xf0, 0x3c,
+ 0xc0, 0x00, 0xee, 0x11,
+ 0xe0, 0xed, 0x20, 0x10,
+ 0x40, 0x40, 0xb0, 0x53,
+ 0xc2, 0xfd, 0x05, 0x50,
+ 0xca, 0x82, 0xb0, 0x33,
+ 0xe2, 0x20, 0x33, 0x81,
+ 0xdd, 0x03, 0xc7, 0xb3,
+ 0x0e, 0x0b, 0xf5, 0x4a,
+ 0xd3, 0x47, 0x3d, 0x07,
+ 0xc7, 0xbd, 0x04, 0xda,
+ 0xd4, 0xf2, 0xc5, 0xfe,
+ 0xc0, 0xdd, 0xc0, 0xb0,
+ 0xcd, 0xc2, 0xb0, 0xdd,
+ 0xe2, 0x00, 0xdd, 0x11,
+ 0x20, 0xb0, 0xf4, 0xd0,
+ 0xbb, 0x20, 0xc0, 0xda,
+ 0x82, 0xad, 0x0c, 0xd7,
+ 0xbb, 0x16, 0x0b, 0xac,
+ 0x4a, 0xbb, 0x47, 0x3b,
+ 0x0f, 0xd7, 0xbb, 0x0c,
+ 0x00, 0x3f, 0x11, 0x22,
+ 0xcc, 0xfe, 0x30, 0x22,
+ 0x20, 0x3d, 0x0e, 0x1d,
+ 0xf0, 0x3d, 0x0e, 0x00,
+ 0x2f, 0x11, 0x20, 0x2a,
+ 0x20, 0x1d, 0xf0, 0x00,
+ 0x0c, 0x03, 0x1d, 0xf0,
+ 0x67, 0x35, 0x04, 0x88,
+ 0x81, 0x77, 0x38, 0x15,
+ 0x0c, 0x12, 0x0c, 0x03,
+ 0x1d, 0xf0, 0x00, 0x00,
+ 0x70, 0x36, 0xc0, 0x70,
+ 0xb0, 0xf5, 0x70, 0xa0,
+ 0xf4, 0x0c, 0x1e, 0x06,
+ 0xdf, 0xff, 0x0c, 0x02,
+ 0x0c, 0x03, 0x1d, 0xf0,
+ 0x36, 0x21, 0x00, 0x4d,
+ 0x02, 0x0c, 0x02, 0x40,
+ 0x30, 0xf5, 0xcc, 0x33,
+ 0x1c, 0x02, 0x00, 0x44,
+ 0x11, 0x40, 0x38, 0x75,
+ 0xcc, 0x43, 0x22, 0xc2,
+ 0x08, 0x80, 0x44, 0x11,
+ 0x31, 0xe8, 0xde, 0x40,
+ 0x48, 0x75, 0x4a, 0x33,
+ 0x32, 0x03, 0x00, 0x3a,
+ 0x22, 0x1d, 0xf0, 0x00,
+ 0x36, 0x41, 0x00, 0x41,
+ 0xe4, 0xde, 0xa8, 0x04,
+ 0xb8, 0x14, 0xa0, 0x21,
+ 0x41, 0x16, 0x1b, 0x05,
+ 0xaa, 0xa2, 0xe0, 0xaa,
+ 0x11, 0xe0, 0x0b, 0x00,
+ 0x3d, 0x0a, 0x16, 0x4a,
+ 0x04, 0xc1, 0xde, 0xde,
+ 0xc8, 0x0c, 0xb8, 0x24,
+ 0xe0, 0xcc, 0x11, 0xa5,
+ 0x86, 0x00, 0xc8, 0x04,
+ 0xd8, 0x34, 0xb8, 0x24,
+ 0xda, 0xa2, 0x30, 0xaa,
+ 0xa0, 0xb0, 0xbd, 0xa0,
+ 0xd0, 0xcc, 0xc0, 0xe0,
+ 0xcc, 0x11, 0x25, 0x85,
+ 0x00, 0xb1, 0xd6, 0xde,
+ 0xa8, 0x24, 0xb7, 0x1a,
+ 0x06, 0xb8, 0x44, 0x8c,
+ 0x1b, 0xe0, 0x0b, 0x00,
+ 0x39, 0x24, 0xc8, 0x04,
+ 0xd8, 0x34, 0x2a, 0xcc,
+ 0x2a, 0xdd, 0xd9, 0x34,
+ 0xc9, 0x04, 0x0c, 0x12,
+ 0x1d, 0xf0, 0x0c, 0x02,
+ 0x1d, 0xf0, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0x3d,
+ 0x02, 0x0c, 0x1a, 0x65,
+ 0x31, 0x00, 0x41, 0xc8,
+ 0xde, 0x81, 0xc8, 0xde,
+ 0xa8, 0x34, 0x88, 0x08,
+ 0xa7, 0x38, 0x06, 0x25,
+ 0xf8, 0xff, 0x9c, 0x6a,
+ 0xa8, 0x34, 0x0c, 0x02,
+ 0xb8, 0x24, 0x0b, 0x9a,
+ 0x99, 0x34, 0xb0, 0x99,
+ 0xa0, 0x39, 0x09, 0x0c,
+ 0x1a, 0xa5, 0x31, 0x00,
+ 0x1d, 0xf0, 0x00, 0x00,
+ 0x7c, 0xf2, 0x46, 0xfc,
+ 0xff, 0x00, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0x31,
+ 0xbb, 0xde, 0x88, 0x03,
+ 0xa8, 0x33, 0x87, 0xba,
+ 0x18, 0x1b, 0x8a, 0x98,
+ 0x23, 0x89, 0x33, 0x90,
+ 0x88, 0xa0, 0x82, 0xd8,
+ 0xff, 0x82, 0x28, 0x3f,
+ 0xe0, 0x08, 0x00, 0xb8,
+ 0x03, 0xa8, 0x33, 0xb7,
+ 0x3a, 0xe6, 0x41, 0xb3,
+ 0xde, 0xa8, 0x04, 0x16,
+ 0x2a, 0x01, 0x0b, 0x8a,
+ 0x98, 0x23, 0x89, 0x04,
+ 0x90, 0x88, 0xa0, 0x88,
+ 0x08, 0xe0, 0x08, 0x00,
+ 0xa8, 0x04, 0x56, 0xca,
+ 0xfe, 0x41, 0xad, 0xde,
+ 0xa8, 0x23, 0xb8, 0x43,
+ 0x47, 0x1a, 0x05, 0x16,
+ 0x2b, 0x00, 0xe0, 0x0b,
+ 0x00, 0x4c, 0x0a, 0x49,
+ 0x23, 0xa9, 0x03, 0xad,
+ 0x02, 0xe5, 0x18, 0x00,
+ 0x36, 0x41, 0x00, 0x16,
+ 0x82, 0x04, 0x32, 0xc2,
+ 0xf8, 0xa2, 0xd2, 0xff,
+ 0xa2, 0x2a, 0x3e, 0x2d,
+ 0x03, 0xb6, 0x8a, 0x3a,
+ 0x0c, 0x7b, 0xa7, 0x8b,
+ 0x35, 0x0c, 0x1a, 0xa5,
+ 0x26, 0x00, 0xc1, 0xa0,
+ 0xde, 0xb8, 0x1c, 0x16,
+ 0x2b, 0x00, 0xb7, 0xb3,
+ 0x27, 0xb9, 0x13, 0x39,
+ 0x1c, 0xa8, 0x12, 0xd8,
+ 0x02, 0x9c, 0x5a, 0x2a,
+ 0xdd, 0xd7, 0x9a, 0x11,
+ 0x0c, 0x09, 0x99, 0x0c,
+ 0xe8, 0x12, 0x88, 0x02,
+ 0xf8, 0x0e, 0x8a, 0xff,
+ 0xf9, 0x02, 0xe8, 0x1e,
+ 0xe9, 0x12, 0x0c, 0x1a,
+ 0x25, 0x26, 0x00, 0x1d,
+ 0xf0, 0xa8, 0x1b, 0x8c,
+ 0xaa, 0x37, 0xba, 0x08,
+ 0xbd, 0x0a, 0xa8, 0x1a,
+ 0x8c, 0x1a, 0x37, 0x3a,
+ 0xf6, 0xd8, 0x0b, 0xba,
+ 0xad, 0xa7, 0x33, 0x1f,
+ 0xa7, 0x93, 0x0a, 0xa8,
+ 0x03, 0x2d, 0x0b, 0xda,
+ 0xaa, 0xa9, 0x0b, 0x86,
+ 0xed, 0xff, 0xa8, 0x1b,
+ 0x8c, 0x5a, 0xd8, 0x03,
+ 0x3a, 0xdd, 0xd7, 0x3a,
+ 0x10, 0xa9, 0x13, 0x39,
+ 0x1b, 0x06, 0xe9, 0xff,
+ 0x0c, 0x1a, 0x65, 0x22,
+ 0x00, 0x1d, 0xf0, 0x00,
+ 0x00, 0x00, 0x0c, 0x1a,
+ 0xa5, 0x21, 0x00, 0x1d,
+ 0xf0, 0x00, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0x0c,
+ 0x1a, 0x25, 0x1e, 0x00,
+ 0x7c, 0x8b, 0xfb, 0xa2,
+ 0xb0, 0xaa, 0x10, 0xa7,
+ 0x32, 0x02, 0x86, 0x33,
+ 0x00, 0x61, 0x7d, 0xde,
+ 0x0c, 0x82, 0x51, 0x7b,
+ 0xde, 0xa0, 0x22, 0x73,
+ 0x42, 0xc5, 0xfc, 0xb8,
+ 0x04, 0x98, 0x14, 0x16,
+ 0xeb, 0x08, 0xc8, 0x0b,
+ 0xf8, 0x14, 0x16, 0xcc,
+ 0x05, 0xad, 0x0c, 0x46,
+ 0x02, 0x00, 0x00, 0x00,
+ 0x00, 0x4b, 0xba, 0xa8,
+ 0x1a, 0x16, 0xda, 0x04,
+ 0x88, 0x0a, 0x27, 0x38,
+ 0xf3, 0xbc, 0x9b, 0x38,
+ 0x0b, 0x98, 0x03, 0x92,
+ 0xc9, 0xf8, 0x27, 0xb9,
+ 0x06, 0x98, 0x13, 0x99,
+ 0x0b, 0x06, 0x05, 0x00,
+ 0x3a, 0xd2, 0xd9, 0x0b,
+ 0xc8, 0x13, 0xc9, 0x1d,
+ 0xa8, 0x03, 0xc8, 0x0b,
+ 0x20, 0xaa, 0xc0, 0xa9,
+ 0x0c, 0x29, 0x03, 0x98,
+ 0x0b, 0x16, 0x19, 0x06,
+ 0xe8, 0x19, 0x16, 0xce,
+ 0x05, 0x4b, 0xa9, 0xa9,
+ 0x04, 0x0c, 0x1a, 0xa5,
+ 0x19, 0x00, 0x8b, 0x23,
+ 0x1d, 0xf0, 0x0c, 0x1a,
+ 0xe5, 0x18, 0x00, 0x0c,
+ 0x02, 0x1d, 0xf0, 0x00,
+ 0x00, 0x00, 0xbd, 0x05,
+ 0xc7, 0x1f, 0x0d, 0xa8,
+ 0x05, 0x88, 0x0a, 0x27,
+ 0xb8, 0xaa, 0x4b, 0xba,
+ 0xa8, 0x1a, 0xc7, 0x9a,
+ 0xf3, 0x38, 0x06, 0x30,
+ 0x32, 0x73, 0xad, 0x03,
+ 0xe5, 0x04, 0x00, 0xec,
+ 0xba, 0x37, 0x12, 0xd1,
+ 0x30, 0x31, 0x41, 0x06,
+ 0xfb, 0xff, 0x00, 0x00,
+ 0x00, 0xbd, 0x05, 0x16,
+ 0x29, 0xfe, 0xa8, 0x05,
+ 0xc8, 0x0a, 0x27, 0x3c,
+ 0x02, 0x06, 0xdf, 0xff,
+ 0x4b, 0xba, 0xa8, 0x1a,
+ 0x56, 0x0a, 0xff, 0x86,
+ 0xf3, 0xff, 0x0c, 0x0a,
+ 0xc6, 0xe7, 0xff, 0x00,
+ 0x00, 0x00, 0x39, 0x0a,
+ 0x8b, 0xaa, 0x65, 0xe8,
+ 0xff, 0x86, 0xcf, 0xff,
+ 0x0c, 0x1a, 0xe5, 0x12,
+ 0x00, 0x0c, 0x02, 0x1d,
+ 0xf0, 0x00, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0xad,
+ 0x02, 0xe5, 0x7a, 0x00,
+ 0x36, 0x41, 0x00, 0xa6,
+ 0x12, 0x1b, 0xad, 0x02,
+ 0xa5, 0x16, 0x00, 0x26,
+ 0x0a, 0x13, 0x7c, 0x88,
+ 0x7b, 0x2a, 0x80, 0x22,
+ 0x10, 0xa7, 0x12, 0x0d,
+ 0xa0, 0xa2, 0xc0, 0xa5,
+ 0x15, 0x00, 0x1d, 0xf0,
+ 0x00, 0x00, 0x0c, 0x02,
+ 0x1d, 0xf0, 0x2d, 0x0a,
+ 0x1d, 0xf0, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0x81,
+ 0x3a, 0xde, 0x88, 0x08,
+ 0x51, 0x3a, 0xde, 0xac,
+ 0x18, 0x32, 0xc5, 0x60,
+ 0x22, 0xc5, 0x10, 0x0c,
+ 0x04, 0x49, 0x05, 0xad,
+ 0x02, 0x65, 0x74, 0x00,
+ 0x4b, 0x22, 0x37, 0x92,
+ 0xf5, 0x49, 0x15, 0x21,
+ 0x34, 0xde, 0xad, 0x03,
+ 0x65, 0x73, 0x00, 0x4b,
+ 0x33, 0x27, 0x93, 0xf5,
+ 0x1d, 0xf0, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0x81,
+ 0x2d, 0xde, 0x31, 0x2f,
+ 0xde, 0x88, 0x08, 0x22,
+ 0xc3, 0xb0, 0xac, 0x68,
+ 0xad, 0x02, 0x25, 0x71,
+ 0x00, 0x4b, 0x22, 0x37,
+ 0x92, 0xf5, 0x41, 0x28,
+ 0xde, 0x1c, 0x49, 0x99,
+ 0x04, 0x22, 0xc4, 0x70,
+ 0xad, 0x03, 0xe5, 0x6f,
+ 0x00, 0x4b, 0x33, 0x27,
+ 0x93, 0xf5, 0x0c, 0x4a,
+ 0xa9, 0x14, 0xa1, 0x25,
+ 0xde, 0xe5, 0x09, 0x00,
+ 0x1d, 0xf0, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0x31,
+ 0x1f, 0xde, 0x3d, 0xf0,
+ 0x82, 0x03, 0x08, 0x9c,
+ 0xa8, 0x8c, 0x72, 0x92,
+ 0x23, 0x00, 0xa2, 0x02,
+ 0x02, 0x97, 0x2a, 0x03,
+ 0x1d, 0xf0, 0x00, 0x00,
+ 0xb1, 0x1d, 0xde, 0xb0,
+ 0xaa, 0xa0, 0x65, 0x6d,
+ 0x00, 0x1d, 0xf0, 0x00,
+ 0x00, 0xa5, 0xf9, 0xff,
+ 0x0c, 0x2c, 0xc2, 0x43,
+ 0x08, 0x06, 0xf6, 0xff,
+ 0x36, 0x41, 0x00, 0x8c,
+ 0x92, 0xb1, 0x11, 0xde,
+ 0xa2, 0x02, 0x02, 0x88,
+ 0x0b, 0x87, 0x2a, 0x03,
+ 0x1d, 0xf0, 0x00, 0x00,
+ 0x92, 0xcb, 0x10, 0x90,
+ 0xaa, 0xa0, 0x25, 0x6b,
+ 0x00, 0x1d, 0xf0, 0x00,
+ 0x36, 0x41, 0x00, 0x31,
+ 0x0a, 0xde, 0x82, 0x03,
+ 0x08, 0x16, 0x48, 0x01,
+ 0x98, 0x13, 0x97, 0x22,
+ 0x02, 0x1d, 0xf0, 0x00,
+ 0xa1, 0x08, 0xde, 0xa0,
+ 0xa2, 0xa0, 0xa5, 0x68,
+ 0x00, 0x1d, 0xf0, 0x00,
+ 0x00, 0xe5, 0xf4, 0xff,
+ 0x0c, 0x2b, 0xb2, 0x43,
+ 0x08, 0xc6, 0xf7, 0xff,
+ 0x36, 0x41, 0x00, 0xa1,
+ 0xff, 0xdd, 0x88, 0x1a,
+ 0x87, 0x22, 0x01, 0x1d,
+ 0xf0, 0xa2, 0xca, 0x60,
+ 0xa0, 0xa2, 0xa0, 0xe5,
+ 0x66, 0x00, 0x1d, 0xf0,
+ 0x36, 0x41, 0x00, 0x31,
+ 0xfe, 0xdd, 0x81, 0xf2,
+ 0xdd, 0xa8, 0x03, 0x88,
+ 0x08, 0xc1, 0xfc, 0xdd,
+ 0xa7, 0x38, 0x19, 0x65,
+ 0xc2, 0xff, 0xac, 0x2a,
+ 0x98, 0x03, 0xa1, 0xf9,
+ 0xdd, 0x0b, 0x99, 0xa8,
+ 0x0a, 0x99, 0x03, 0xa0,
+ 0x99, 0xa0, 0x29, 0x09,
+ 0x1d, 0xf0, 0x00, 0x00,
+ 0x00, 0x0b, 0xba, 0xc8,
+ 0x0c, 0xb9, 0x03, 0xc0,
+ 0xbb, 0xa0, 0x29, 0x0b,
+ 0x1d, 0xf0, 0x00, 0x00,
+ 0xa5, 0x06, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0xa1,
+ 0xf0, 0xdd, 0xbd, 0x02,
+ 0xa8, 0x0a, 0x65, 0x0c,
+ 0x00, 0x2d, 0x0a, 0x1d,
+ 0xf0, 0x00, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0x8c,
+ 0x53, 0x91, 0xeb, 0xdd,
+ 0x88, 0x03, 0x89, 0x09,
+ 0xa1, 0xeb, 0xdd, 0x49,
+ 0x0a, 0xe5, 0x02, 0x00,
+ 0x8c, 0x15, 0xe0, 0x05,
+ 0x00, 0x8c, 0x36, 0xad,
+ 0x06, 0xe5, 0xc2, 0xff,
+ 0x1d, 0xf0, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0xad,
+ 0x02, 0x0c, 0x0b, 0xc2,
+ 0xa0, 0xf4, 0xa5, 0x57,
+ 0x00, 0x81, 0xe2, 0xdd,
+ 0x0c, 0x19, 0x92, 0x62,
+ 0x1b, 0x89, 0x12, 0x1d,
+ 0xf0, 0x00, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0x0c,
+ 0x18, 0x31, 0xde, 0xdd,
+ 0x21, 0xdd, 0xdd, 0x29,
+ 0x13, 0x82, 0x63, 0x1b,
+ 0x1d, 0xf0, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0x1c,
+ 0x6a, 0xa5, 0x00, 0x00,
+ 0x0c, 0x1a, 0x25, 0xe1,
+ 0xff, 0x00, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0xad,
+ 0x02, 0x0c, 0x1b, 0xa5,
+ 0x02, 0x00, 0x3d, 0x0a,
+ 0x26, 0x0a, 0x1b, 0x26,
+ 0x1a, 0x0d, 0x9c, 0x0a,
+ 0xad, 0x02, 0x0c, 0x0b,
+ 0x65, 0x01, 0x00, 0xad,
+ 0x02, 0xe0, 0x03, 0x00,
+ 0x0c, 0x02, 0x1d, 0xf0,
+ 0x00, 0x00, 0x0c, 0x1a,
+ 0x25, 0xde, 0xff, 0x7c,
+ 0xf2, 0x1d, 0xf0, 0x00,
+ 0x36, 0x41, 0x00, 0xa6,
+ 0x12, 0x05, 0xe6, 0xc2,
+ 0x02, 0x66, 0x03, 0x03,
+ 0x7c, 0xf2, 0x1d, 0xf0,
+ 0x0c, 0x1a, 0x25, 0xec,
+ 0xff, 0x81, 0xc6, 0xdd,
+ 0x0c, 0x1a, 0x80, 0x82,
+ 0xa0, 0x28, 0x08, 0x39,
+ 0x08, 0xe5, 0xed, 0xff,
+ 0x1d, 0xf0, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0x41,
+ 0xc4, 0xdd, 0x9d, 0x02,
+ 0x61, 0xc1, 0xdd, 0x21,
+ 0xc1, 0xdd, 0x58, 0x06,
+ 0x48, 0x04, 0x50, 0x25,
+ 0x93, 0x2a, 0x33, 0x47,
+ 0x33, 0x07, 0x7c, 0xf2,
+ 0x0c, 0xc8, 0x89, 0x09,
+ 0x1d, 0xf0, 0x39, 0x06,
+ 0x1d, 0xf0, 0x00, 0x00,
+ 0x00, 0x6d, 0x03, 0x17,
+ 0xe0, 0x52, 0xe7, 0xf0,
+ 0x5b, 0x20, 0x6f, 0x61,
+ 0x87, 0x70, 0x1a, 0x01,
+ 0xb8, 0xdd, 0x49, 0x00,
+ 0x48, 0x02, 0x00, 0x0c,
+ 0x03, 0x40, 0x0c, 0x13,
+ 0x42, 0xe2, 0x00, 0x41,
+ 0xb4, 0xdd, 0x00, 0x0c,
+ 0x13, 0x48, 0x04, 0xc6,
+ 0x00, 0x00, 0x08, 0x02,
+ 0x09, 0x02, 0x20, 0x6f,
+ 0x61, 0x01, 0xb0, 0xdd,
+ 0x16, 0x80, 0x01, 0x01,
+ 0xae, 0xdd, 0x22, 0x60,
+ 0x00, 0x32, 0x60, 0x01,
+ 0x01, 0xad, 0xdd, 0x20,
+ 0x6d, 0x03, 0xc0, 0x00,
+ 0x00, 0x31, 0xa9, 0xdd,
+ 0x28, 0x03, 0x38, 0x13,
+ 0x01, 0xaa, 0xdd, 0x00,
+ 0x6c, 0x61, 0x20, 0x30,
+ 0x00, 0x01, 0xa8, 0xdd,
+ 0x16, 0xc0, 0xff, 0xa0,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x01, 0xa6, 0xdd,
+ 0x16, 0xc0, 0xff, 0xa0,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x30, 0xb1, 0x03, 0x28,
+ 0x41, 0x3b, 0x33, 0x30,
+ 0xb1, 0x13, 0x32, 0x21,
+ 0x05, 0x56, 0x82, 0x05,
+ 0x32, 0x61, 0x11, 0x42,
+ 0x61, 0x12, 0x52, 0x61,
+ 0x13, 0x31, 0x9e, 0xdd,
+ 0x20, 0xe6, 0x03, 0x30,
+ 0xe6, 0x13, 0x30, 0xb1,
+ 0x03, 0x12, 0xc1, 0x60,
+ 0x10, 0x20, 0x00, 0x42,
+ 0xa0, 0x00, 0x36, 0x81,
+ 0x00, 0xf5, 0x01, 0x00,
+ 0xe1, 0x99, 0xdd, 0xea,
+ 0x0c, 0x1d, 0xf0, 0x20,
+ 0xe6, 0x13, 0x0c, 0x02,
+ 0x48, 0xa5, 0x10, 0x20,
+ 0x00, 0x30, 0xb1, 0x13,
+ 0x38, 0x95, 0x58, 0xb5,
+ 0x00, 0x30, 0x00, 0x00,
+ 0x36, 0x61, 0x00, 0xc1,
+ 0x92, 0xdd, 0xca, 0xc0,
+ 0x36, 0x61, 0x00, 0xcd,
+ 0x00, 0x36, 0x61, 0x00,
+ 0xcd, 0x00, 0x36, 0x21,
+ 0x00, 0xbd, 0x0b, 0x1d,
+ 0xf0, 0x7c, 0xf2, 0x12,
+ 0xc1, 0x60, 0x00, 0x30,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0x96,
+ 0x92, 0x02, 0xe6, 0x42,
+ 0x26, 0x51, 0x88, 0xdd,
+ 0x81, 0x8a, 0xdd, 0x5a,
+ 0x52, 0x52, 0x05, 0x00,
+ 0x71, 0x87, 0xdd, 0xf6,
+ 0x35, 0x15, 0x70, 0x72,
+ 0xb0, 0x68, 0x07, 0xdc,
+ 0x13, 0x89, 0x07, 0x29,
+ 0x17, 0x80, 0x96, 0xc0,
+ 0x0c, 0x02, 0x90, 0x26,
+ 0x93, 0x1d, 0xf0, 0x00,
+ 0x0c, 0x02, 0x1d, 0xf0,
+ 0x39, 0x07, 0x49, 0x17,
+ 0x80, 0xa6, 0xc0, 0x0c,
+ 0x02, 0xa0, 0x26, 0x93,
+ 0x1d, 0xf0, 0x00, 0x00,
+ 0x36, 0x41, 0x00, 0xbd,
+ 0x03, 0xad, 0x02, 0xcd,
+ 0x02, 0x25, 0xfb, 0xff,
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+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00
+};
+
+uint8_t gDctrlDpDram[DCTRL_DP_DMEM_SIZE] = {
+ 0x01, 0x02, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x01, 0x00, 0x00,
+ 0x00, 0x00, 0x01, 0x00,
+ 0x00, 0x00, 0x02, 0x00,
+ 0x00, 0x00, 0x02, 0x00,
+ 0x00, 0x00, 0x03, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x01, 0x00, 0x00,
+ 0x00, 0x40, 0x00, 0x00,
+ 0x00, 0x41, 0x00, 0x00,
+ 0x00, 0x50, 0x00, 0x00,
+ 0x00, 0x51, 0x00, 0x00,
+ 0x00, 0x24, 0x00, 0x00,
+ 0x00, 0x25, 0x00, 0x00,
+ 0x00, 0x24, 0x00, 0x00,
+ 0x00, 0x25, 0x00, 0x00,
+ 0x00, 0x00, 0x01, 0x00,
+ 0x00, 0x00, 0x02, 0x00,
+ 0x00, 0x00, 0x02, 0x00,
+ 0x00, 0x00, 0x03, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x07, 0x03, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x07, 0x00, 0x00, 0x00,
+ 0x02, 0x00, 0x00, 0x00,
+ 0xd0, 0x02, 0xff, 0x3f,
+ 0x1c, 0x00, 0x00, 0x00,
+ 0x0c, 0x13, 0x00, 0x30,
+ 0xfc, 0x12, 0x00, 0x30,
+ 0xf0, 0x12, 0x00, 0x30,
+ 0xe0, 0x12, 0x00, 0x30,
+ 0xd8, 0x12, 0x00, 0x30,
+ 0xc8, 0x12, 0x00, 0x30,
+ 0x40, 0x12, 0x00, 0x30,
+ 0x34, 0x12, 0x00, 0x30,
+ 0xe4, 0x11, 0x00, 0x30,
+ 0xb8, 0x11, 0x00, 0x30,
+ 0xa8, 0x11, 0x00, 0x30,
+ 0x9c, 0x11, 0x00, 0x30,
+ 0x90, 0x11, 0x00, 0x30,
+ 0x03, 0x00, 0x00, 0x00,
+ 0xd8, 0x02, 0xff, 0x3f,
+ 0x20, 0x00, 0x00, 0x00,
+ 0x30, 0x11, 0x00, 0x30,
+ 0x20, 0x11, 0x00, 0x30,
+ 0x14, 0x11, 0x00, 0x30,
+ 0x04, 0x11, 0x00, 0x30,
+ 0xfc, 0x10, 0x00, 0x30,
+ 0xec, 0x10, 0x00, 0x30,
+ 0xdc, 0x10, 0x00, 0x30,
+ 0xd0, 0x10, 0x00, 0x30,
+ 0xc4, 0x10, 0x00, 0x30,
+ 0xb0, 0x10, 0x00, 0x30,
+ 0x94, 0x10, 0x00, 0x30,
+ 0x88, 0x10, 0x00, 0x30,
+ 0x7c, 0x10, 0x00, 0x30,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0xb0, 0x02, 0xff, 0x3f,
+ 0x09, 0x00, 0x00, 0x00,
+ 0xbc, 0x02, 0xff, 0x3f,
+ 0xc8, 0x02, 0xff, 0x3f,
+ 0x03, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x02, 0x00, 0x00, 0x00,
+ 0x03, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x80, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x08, 0x07, 0x06, 0x06,
+ 0x05, 0x05, 0x05, 0x05,
+ 0x04, 0x04, 0x04, 0x04,
+ 0x04, 0x04, 0x04, 0x04,
+ 0x03, 0x03, 0x03, 0x03,
+ 0x03, 0x03, 0x03, 0x03,
+ 0x03, 0x03, 0x03, 0x03,
+ 0x03, 0x03, 0x03, 0x03,
+ 0x02, 0x02, 0x02, 0x02,
+ 0x02, 0x02, 0x02, 0x02,
+ 0x02, 0x02, 0x02, 0x02,
+ 0x02, 0x02, 0x02, 0x02,
+ 0x02, 0x02, 0x02, 0x02,
+ 0x02, 0x02, 0x02, 0x02,
+ 0x02, 0x02, 0x02, 0x02,
+ 0x02, 0x02, 0x02, 0x02,
+ 0x01, 0x01, 0x01, 0x01,
+ 0x01, 0x01, 0x01, 0x01,
+ 0x01, 0x01, 0x01, 0x01,
+ 0x01, 0x01, 0x01, 0x01,
+ 0x01, 0x01, 0x01, 0x01,
+ 0x01, 0x01, 0x01, 0x01,
+ 0x01, 0x01, 0x01, 0x01,
+ 0x01, 0x01, 0x01, 0x01,
+ 0x01, 0x01, 0x01, 0x01,
+ 0x01, 0x01, 0x01, 0x01,
+ 0x01, 0x01, 0x01, 0x01,
+ 0x01, 0x01, 0x01, 0x01,
+ 0x01, 0x01, 0x01, 0x01,
+ 0x01, 0x01, 0x01, 0x01,
+ 0x01, 0x01, 0x01, 0x01,
+ 0x01, 0x01, 0x01, 0x01,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x01, 0x01, 0x01, 0x01,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x60, 0x86, 0x48, 0x01,
+ 0x65, 0x03, 0x04, 0x02,
+ 0x01, 0x00, 0x00, 0x00,
+ 0x69, 0x64, 0x2d, 0x73,
+ 0x68, 0x61, 0x32, 0x35,
+ 0x36, 0x00, 0x00, 0x00,
+ 0x53, 0x48, 0x41, 0x2d,
+ 0x32, 0x35, 0x36, 0x00,
+ 0x53, 0x48, 0x41, 0x32,
+ 0x32, 0x34, 0x00, 0x00,
+ 0x53, 0x48, 0x41, 0x32,
+ 0x35, 0x36, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0xff, 0xff, 0xff, 0xff,
+ 0x00, 0x00, 0x00, 0x00,
+ 0xff, 0xff, 0xff, 0xff,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x10,
+ 0x00, 0x00, 0x00, 0x10,
+ 0xd0, 0x04, 0xff, 0x3f,
+ 0xb8, 0x5c, 0xff, 0x3f,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x14, 0x03, 0xff, 0x3f,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0xf4, 0x02, 0xff, 0x3f,
+ 0x01, 0x01, 0x01, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x50, 0x00, 0x00,
+ 0x02, 0x00, 0x00, 0x00,
+ 0x78, 0x56, 0x34, 0x12,
+ 0x78, 0x56, 0x34, 0x12,
+ 0x24, 0x52, 0x65, 0x76,
+ 0x69, 0x73, 0x69, 0x6f,
+ 0x6e, 0x24, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x24, 0x52, 0x65, 0x76,
+ 0x69, 0x73, 0x69, 0x6f,
+ 0x6e, 0x24, 0x00, 0x00,
+ 0x40, 0x00, 0x00, 0x00,
+ 0xd8, 0x94, 0x00, 0x30,
+ 0xa0, 0x59, 0xff, 0x3f,
+ 0x40, 0x00, 0x00, 0x00,
+ 0x3c, 0x94, 0x00, 0x30,
+ 0x00, 0x02, 0x00, 0x00,
+ 0x24, 0x5b, 0xff, 0x3f,
+ 0xa4, 0x5c, 0xff, 0x3f,
+ 0x00, 0x00, 0x00, 0x40,
+ 0xa0, 0x9d, 0x00, 0x30,
+ 0xac, 0x98, 0x00, 0x30,
+ 0xa0, 0x9d, 0x00, 0x30,
+ 0xa0, 0x9d, 0x00, 0x30,
+ 0xa8, 0x99, 0x00, 0x30,
+ 0x10, 0x06, 0x00, 0x30,
+ 0xa0, 0x9d, 0x00, 0x30,
+ 0xa0, 0x9d, 0x00, 0x30,
+ 0xa0, 0x9d, 0x00, 0x30,
+ 0xa0, 0x9d, 0x00, 0x30,
+ 0xa0, 0x9d, 0x00, 0x30,
+ 0xa0, 0x9d, 0x00, 0x30,
+ 0xa0, 0x9d, 0x00, 0x30,
+ 0xa0, 0x9d, 0x00, 0x30,
+ 0xa0, 0x9d, 0x00, 0x30,
+ 0xa0, 0x9d, 0x00, 0x30,
+ 0xa0, 0x9d, 0x00, 0x30,
+ 0xa0, 0x9d, 0x00, 0x30,
+ 0xa0, 0x9d, 0x00, 0x30,
+ 0xa0, 0x9d, 0x00, 0x30,
+ 0xa0, 0x9d, 0x00, 0x30,
+ 0xa0, 0x9d, 0x00, 0x30,
+ 0xa0, 0x9d, 0x00, 0x30,
+ 0xa0, 0x9d, 0x00, 0x30,
+ 0xa0, 0x9d, 0x00, 0x30,
+ 0xa0, 0x9d, 0x00, 0x30,
+ 0xa0, 0x9d, 0x00, 0x30,
+ 0xa0, 0x9d, 0x00, 0x30,
+ 0xa0, 0x9d, 0x00, 0x30,
+ 0xa0, 0x9d, 0x00, 0x30,
+ 0xa0, 0x9d, 0x00, 0x30,
+ 0xa0, 0x9d, 0x00, 0x30,
+ 0xa0, 0x9d, 0x00, 0x30,
+ 0xa0, 0x9d, 0x00, 0x30,
+ 0xa0, 0x9d, 0x00, 0x30,
+ 0xa0, 0x9d, 0x00, 0x30,
+ 0xa0, 0x9d, 0x00, 0x30,
+ 0xa0, 0x9d, 0x00, 0x30,
+ 0xa0, 0x9d, 0x00, 0x30,
+ 0xa0, 0x9d, 0x00, 0x30,
+ 0xa0, 0x9d, 0x00, 0x30,
+ 0xa0, 0x9d, 0x00, 0x30,
+ 0xa0, 0x9d, 0x00, 0x30,
+ 0xa0, 0x9d, 0x00, 0x30,
+ 0xa0, 0x9d, 0x00, 0x30,
+ 0xa0, 0x9d, 0x00, 0x30,
+ 0xa0, 0x9d, 0x00, 0x30,
+ 0xa0, 0x9d, 0x00, 0x30,
+ 0xa0, 0x9d, 0x00, 0x30,
+ 0xa0, 0x9d, 0x00, 0x30,
+ 0xa0, 0x9d, 0x00, 0x30,
+ 0xa0, 0x9d, 0x00, 0x30,
+ 0xa0, 0x9d, 0x00, 0x30,
+ 0xa0, 0x9d, 0x00, 0x30,
+ 0xa0, 0x9d, 0x00, 0x30,
+ 0xa0, 0x9d, 0x00, 0x30,
+ 0xa0, 0x9d, 0x00, 0x30,
+ 0xa0, 0x9d, 0x00, 0x30,
+ 0xa0, 0x9d, 0x00, 0x30,
+ 0xa0, 0x9d, 0x00, 0x30,
+ 0xa0, 0x9d, 0x00, 0x30,
+ 0xa0, 0x9d, 0x00, 0x30,
+ 0xa0, 0x9d, 0x00, 0x30,
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+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00
+};
+
+/* ========================================================================== */
+/* Function Definitions */
+/* ========================================================================== */
+
+/* None */
diff --git a/packages/ti/drv/dss/soc/V1/dss_soc_graph.c b/packages/ti/drv/dss/soc/V1/dss_soc_graph.c
--- /dev/null
@@ -0,0 +1,213 @@
+/*
+ * Copyright (c) Texas Instruments Incorporated 2018
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * \file dss_soc_graph.c
+ *
+ * \brief File containing the graph related configuration functions for DSS.
+ *
+ */
+
+/* ========================================================================== */
+/* Include Files */
+/* ========================================================================== */
+
+#include <ti/drv/dss/dss.h>
+#include "dss_soc_priv.h"
+
+/* ========================================================================== */
+/* Macros & Typedefs */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/* Structure Declarations */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/* Function Declarations */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/* Global Variables */
+/* ========================================================================== */
+
+static const Fvid2_GraphNodeInfo gDctrlGraphNodeInfoDefaults[DSS_DCTRL_MAX_NODES] =
+{
+ {DSS_DCTRL_NODE_INVALID,
+ FVID2_GRAPH_NODE_IN_NONE, FVID2_GRAPH_NODE_IN_NONE,
+ FVID2_GRAPH_NODE_TYPE_DUMMY,
+ 0U, 0U, {0U, {NULL}, {0}}, {0U, {NULL}, {0}}},
+ {DSS_DCTRL_NODE_VID1,
+ FVID2_GRAPH_NODE_IN_SINGLE, FVID2_GRAPH_NODE_OUT_MULTI,
+ FVID2_GRAPH_NODE_TYPE_DSS_PIPE,
+ 0U, 0U, {0U, {NULL}, {0}}, {0U, {NULL}, {0}}},
+ {DSS_DCTRL_NODE_VIDL1,
+ FVID2_GRAPH_NODE_IN_SINGLE, FVID2_GRAPH_NODE_OUT_MULTI,
+ FVID2_GRAPH_NODE_TYPE_DSS_PIPE,
+ 0U, 0U, {0U, {NULL}, {0}}, {0U, {NULL}, {0}}},
+ {DSS_DCTRL_NODE_VID2,
+ FVID2_GRAPH_NODE_IN_SINGLE, FVID2_GRAPH_NODE_OUT_MULTI,
+ FVID2_GRAPH_NODE_TYPE_DSS_PIPE,
+ 0U, 0U, {0U, {NULL}, {0}}, {0U, {NULL}, {0}}},
+ {DSS_DCTRL_NODE_VIDL2,
+ FVID2_GRAPH_NODE_IN_SINGLE, FVID2_GRAPH_NODE_OUT_MULTI,
+ FVID2_GRAPH_NODE_TYPE_DSS_PIPE,
+ 0U, 0U, {0U, {NULL}, {0}}, {0U, {NULL}, {0}}},
+ {DSS_DCTRL_NODE_OVERLAY1,
+ FVID2_GRAPH_NODE_IN_MULTI, FVID2_GRAPH_NODE_OUT_SINGLE,
+ FVID2_GRAPH_NODE_TYPE_DSS_OVERLAY,
+ 0U, 0U, {0U, {NULL}, {0}}, {0U, {NULL}, {0}}},
+ {DSS_DCTRL_NODE_OVERLAY2,
+ FVID2_GRAPH_NODE_IN_MULTI, FVID2_GRAPH_NODE_OUT_SINGLE,
+ FVID2_GRAPH_NODE_TYPE_DSS_OVERLAY,
+ 0U, 0U, {0U, {NULL}, {0}}, {0U, {NULL}, {0}}},
+ {DSS_DCTRL_NODE_OVERLAY3,
+ FVID2_GRAPH_NODE_IN_MULTI, FVID2_GRAPH_NODE_OUT_SINGLE,
+ FVID2_GRAPH_NODE_TYPE_DSS_OVERLAY,
+ 0U, 0U, {0U, {NULL}, {0}}, {0U, {NULL}, {0}}},
+ {DSS_DCTRL_NODE_OVERLAY4,
+ FVID2_GRAPH_NODE_IN_MULTI, FVID2_GRAPH_NODE_OUT_SINGLE,
+ FVID2_GRAPH_NODE_TYPE_DSS_OVERLAY,
+ 0U, 0U, {0U, {NULL}, {0}}, {0U, {NULL}, {0}}},
+ {DSS_DCTRL_NODE_VP1,
+ FVID2_GRAPH_NODE_IN_SINGLE, FVID2_GRAPH_NODE_OUT_SINGLE,
+ FVID2_GRAPH_NODE_TYPE_DSS_VP,
+ 0U, 0U, {0U, {NULL}, {0}}, {0U, {NULL}, {0}}},
+ {DSS_DCTRL_NODE_VP2,
+ FVID2_GRAPH_NODE_IN_SINGLE, FVID2_GRAPH_NODE_OUT_MULTI,
+ FVID2_GRAPH_NODE_TYPE_DSS_VP,
+ 0U, 0U, {0U, {NULL}, {0}}, {0U, {NULL}, {0}}},
+ {DSS_DCTRL_NODE_VP3,
+ FVID2_GRAPH_NODE_IN_SINGLE, FVID2_GRAPH_NODE_OUT_MULTI,
+ FVID2_GRAPH_NODE_TYPE_DSS_VP,
+ 0U, 0U, {0U, {NULL}, {0}}, {0U, {NULL}, {0}}},
+ {DSS_DCTRL_NODE_VP4,
+ FVID2_GRAPH_NODE_IN_SINGLE, FVID2_GRAPH_NODE_OUT_MULTI,
+ FVID2_GRAPH_NODE_TYPE_DSS_VP,
+ 0U, 0U, {0U, {NULL}, {0}}, {0U, {NULL}, {0}}},
+ {DSS_DCTRL_NODE_DPI_DPI0,
+ FVID2_GRAPH_NODE_IN_MULTI, FVID2_GRAPH_NODE_OUT_SINGLE,
+ FVID2_GRAPH_NODE_TYPE_DSS_OUT,
+ 0U, 0U, {0U, {NULL}, {0}}, {0U, {NULL}, {0}}},
+ {DSS_DCTRL_NODE_DPI_DPI1,
+ FVID2_GRAPH_NODE_IN_MULTI, FVID2_GRAPH_NODE_OUT_SINGLE,
+ FVID2_GRAPH_NODE_TYPE_DSS_OUT,
+ 0U, 0U, {0U, {NULL}, {0}}, {0U, {NULL}, {0}}},
+ {DSS_DCTRL_NODE_EDP_DPI0,
+ FVID2_GRAPH_NODE_IN_SINGLE, FVID2_GRAPH_NODE_OUT_SINGLE,
+ FVID2_GRAPH_NODE_TYPE_DSS_OUT,
+ 0U, 0U, {0U, {NULL}, {0}}, {0U, {NULL}, {0}}},
+ {DSS_DCTRL_NODE_EDP_DPI1,
+ FVID2_GRAPH_NODE_IN_SINGLE, FVID2_GRAPH_NODE_OUT_SINGLE,
+ FVID2_GRAPH_NODE_TYPE_DSS_OUT,
+ 0U, 0U, {0U, {NULL}, {0}}, {0U, {NULL}, {0}}},
+ {DSS_DCTRL_NODE_EDP_DPI2,
+ FVID2_GRAPH_NODE_IN_SINGLE, FVID2_GRAPH_NODE_OUT_SINGLE,
+ FVID2_GRAPH_NODE_TYPE_DSS_OUT,
+ 0U, 0U, {0U, {NULL}, {0}}, {0U, {NULL}, {0}}},
+ {DSS_DCTRL_NODE_EDP_DPI3,
+ FVID2_GRAPH_NODE_IN_SINGLE, FVID2_GRAPH_NODE_OUT_SINGLE,
+ FVID2_GRAPH_NODE_TYPE_DSS_OUT,
+ 0U, 0U, {0U, {NULL}, {0}}, {0U, {NULL}, {0}}},
+ {DSS_DCTRL_NODE_DSI,
+ FVID2_GRAPH_NODE_IN_SINGLE, FVID2_GRAPH_NODE_OUT_SINGLE,
+ FVID2_GRAPH_NODE_TYPE_DSS_OUT,
+ 0U, 0U, {0U, {NULL}, {0}}, {0U, {NULL}, {0}}},
+ {DSS_DCTRL_NODE_DISCSYNC0,
+ FVID2_GRAPH_NODE_IN_SINGLE, FVID2_GRAPH_NODE_OUT_SINGLE,
+ FVID2_GRAPH_NODE_TYPE_DSS_OUT,
+ 0U, 0U, {0U, {NULL}, {0}}, {0U, {NULL}, {0}}},
+ {DSS_DCTRL_NODE_DISCSYNC1,
+ FVID2_GRAPH_NODE_IN_SINGLE, FVID2_GRAPH_NODE_OUT_SINGLE,
+ FVID2_GRAPH_NODE_TYPE_DSS_OUT,
+ 0U, 0U, {0U, {NULL}, {0}}, {0U, {NULL}, {0}}}
+
+};
+
+static const Fvid2_GraphEdgeInfo gDctrlGraphEdgeInfoDefaults[DSS_DCTRL_MAX_EDGES] =
+{
+ {DSS_DCTRL_NODE_VID1, DSS_DCTRL_NODE_OVERLAY1},
+ {DSS_DCTRL_NODE_VIDL1, DSS_DCTRL_NODE_OVERLAY1},
+ {DSS_DCTRL_NODE_VID2, DSS_DCTRL_NODE_OVERLAY1},
+ {DSS_DCTRL_NODE_VIDL2, DSS_DCTRL_NODE_OVERLAY1},
+ {DSS_DCTRL_NODE_VID1, DSS_DCTRL_NODE_OVERLAY2},
+ {DSS_DCTRL_NODE_VIDL1, DSS_DCTRL_NODE_OVERLAY2},
+ {DSS_DCTRL_NODE_VID2, DSS_DCTRL_NODE_OVERLAY2},
+ {DSS_DCTRL_NODE_VIDL2, DSS_DCTRL_NODE_OVERLAY2},
+ {DSS_DCTRL_NODE_VID1, DSS_DCTRL_NODE_OVERLAY3},
+ {DSS_DCTRL_NODE_VIDL1, DSS_DCTRL_NODE_OVERLAY3},
+ {DSS_DCTRL_NODE_VID2, DSS_DCTRL_NODE_OVERLAY3},
+ {DSS_DCTRL_NODE_VIDL2, DSS_DCTRL_NODE_OVERLAY3},
+ {DSS_DCTRL_NODE_VID1, DSS_DCTRL_NODE_OVERLAY4},
+ {DSS_DCTRL_NODE_VIDL1, DSS_DCTRL_NODE_OVERLAY4},
+ {DSS_DCTRL_NODE_VID2, DSS_DCTRL_NODE_OVERLAY4},
+ {DSS_DCTRL_NODE_VIDL2, DSS_DCTRL_NODE_OVERLAY4},
+ {DSS_DCTRL_NODE_OVERLAY1, DSS_DCTRL_NODE_VP1},
+ {DSS_DCTRL_NODE_OVERLAY2, DSS_DCTRL_NODE_VP2},
+ {DSS_DCTRL_NODE_OVERLAY3, DSS_DCTRL_NODE_VP3},
+ {DSS_DCTRL_NODE_OVERLAY4, DSS_DCTRL_NODE_VP4},
+ {DSS_DCTRL_NODE_VP1, DSS_DCTRL_NODE_EDP_DPI0},
+ {DSS_DCTRL_NODE_VP1, DSS_DCTRL_NODE_DISCSYNC0},
+ {DSS_DCTRL_NODE_VP1, DSS_DCTRL_NODE_DISCSYNC1},
+ {DSS_DCTRL_NODE_VP2, DSS_DCTRL_NODE_DPI_DPI0},
+ {DSS_DCTRL_NODE_VP2, DSS_DCTRL_NODE_DPI_DPI1},
+ {DSS_DCTRL_NODE_VP2, DSS_DCTRL_NODE_EDP_DPI1},
+ {DSS_DCTRL_NODE_VP3, DSS_DCTRL_NODE_DSI},
+ {DSS_DCTRL_NODE_VP3, DSS_DCTRL_NODE_EDP_DPI2},
+ {DSS_DCTRL_NODE_VP3, DSS_DCTRL_NODE_DISCSYNC0},
+ {DSS_DCTRL_NODE_VP4, DSS_DCTRL_NODE_DPI_DPI0},
+ {DSS_DCTRL_NODE_VP4, DSS_DCTRL_NODE_DPI_DPI1},
+ {DSS_DCTRL_NODE_VP4, DSS_DCTRL_NODE_EDP_DPI3}
+};
+
+/* ========================================================================== */
+/* Function Definitions */
+/* ========================================================================== */
+
+const Fvid2_GraphEdgeInfo* Dss_dctrlGetDefaultEdgeInfo(uint32_t *edgeMemSize)
+{
+ *edgeMemSize = sizeof (gDctrlGraphEdgeInfoDefaults);
+ return &gDctrlGraphEdgeInfoDefaults[0U];
+}
+
+const Fvid2_GraphNodeInfo* Dss_dctrlGetDefaultNodeInfo(uint32_t *nodeMemSize)
+{
+ *nodeMemSize = sizeof (gDctrlGraphNodeInfoDefaults);
+ return &gDctrlGraphNodeInfoDefaults[0U];
+}
diff --git a/packages/ti/drv/dss/soc/V1/dss_soc_priv.h b/packages/ti/drv/dss/soc/V1/dss_soc_priv.h
--- /dev/null
@@ -0,0 +1,622 @@
+/*
+ * Copyright (c) Texas Instruments Incorporated 2018
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * \file dss_soc_priv.h
+ *
+ * \brief DSS Driver J7 SOC file containing private APIs used by display
+ * and display controller driver.
+ */
+
+#ifndef DSS_SOC_PRIV_H_
+#define DSS_SOC_PRIV_H_
+
+/* ========================================================================== */
+/* Include Files */
+/* ========================================================================== */
+
+/* None */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* ========================================================================== */
+/* Macros & Typedefs */
+/* ========================================================================== */
+
+/**
+ * \anchor Dss_EventGroup
+ * \name DSS Events are logically grouped under one of the following
+ * categories.
+ *
+ * @{
+ */
+/**< \brief Event Group for VP1 */
+#define DSS_EVENT_GROUP_VP1 CSL_DSS_DISPC_INTR_VP1_MASK
+/**< \brief Event Group for VP2 */
+#define DSS_EVENT_GROUP_VP2 CSL_DSS_DISPC_INTR_VP2_MASK
+/**< \brief Event Group for VP3 */
+#define DSS_EVENT_GROUP_VP3 CSL_DSS_DISPC_INTR_VP3_MASK
+/**< \brief Event Group for VP4 */
+#define DSS_EVENT_GROUP_VP4 CSL_DSS_DISPC_INTR_VP4_MASK
+/**< \brief Event Group for VID1 */
+#define DSS_EVENT_GROUP_VID1 CSL_DSS_DISPC_INTR_VID1_MASK
+/**< \brief Event Group for VIDL1 */
+#define DSS_EVENT_GROUP_VIDL1 CSL_DSS_DISPC_INTR_VIDL1_MASK
+/**< \brief Event Group for VID2 */
+#define DSS_EVENT_GROUP_VID2 CSL_DSS_DISPC_INTR_VID2_MASK
+/**< \brief Event Group for VIDL2 */
+#define DSS_EVENT_GROUP_VIDL2 CSL_DSS_DISPC_INTR_VIDL2_MASK
+/**< \brief Invalid Event Group */
+#define DSS_EVENT_GROUP_INVALID ((uint32_t) 0xFFU)
+/* @} */
+
+/**
+ * \anchor Dss_EventGroupType
+ * \name DSS Event Groups are logically grouped under one of the following
+ * categories.
+ *
+ * @{
+ */
+/**< \brief Event Group for VP */
+#define DSS_EVENT_GROUP_TYPE_VP ((uint32_t) 0x00U)
+/**< \brief Event Group for Pipe */
+#define DSS_EVENT_GROUP_TYPE_PIPE ((uint32_t) 0x01U)
+/**< \brief Invalid Event Group */
+#define DSS_EVENT_GROUP_TYPE_INVALID ((uint32_t) 0xFFU)
+/* @} */
+
+/**
+ * \anchor Dss_VpEvents
+ * \name List of Video Port Events.
+ *
+ * @{
+ */
+/**< \brief Frame done interrupt */
+#define DSS_VP_EVENT_FRAME_DONE \
+ CSL_DSS_VP_INTR_FRAMEDONE_MASK
+/**< \brief Vsync interrupt */
+#define DSS_VP_EVENT_VSYNC \
+ CSL_DSS_VP_INTR_VSYNC_MASK
+/**< \brief Odd Vsync interrupt in case of interlace display */
+#define DSS_VP_EVENT_ODD_VSYNC \
+ CSL_DSS_VP_INTR_ODDVSYNC_MASK
+/**< \brief Line number interrupt */
+#define DSS_VP_EVENT_LINE_NUM \
+ CSL_DSS_VP_INTR_PROGLINENUM_MASK
+/**< \brief Sync lost Interrupt */
+#define DSS_VP_EVENT_SYNC_LOST \
+ CSL_DSS_VP_INTR_SYNCLOST_MASK
+/**< \brief AC Bias transition counter 0 interrupt */
+#define DSS_VP_EVENT_ACBIAS_COUNT \
+ CSL_DSS_VP_INTR_ACBIASCOUNT_MASK
+/**< \brief Safety violation region 0 interrupt */
+#define DSS_VP_EVENT_SAFETY_VIOLATION_0 \
+ CSL_DSS_VP_INTR_SAFETYVIOLATION_REGION0_MASK
+/**< \brief Safety violation region 1 interrupt */
+#define DSS_VP_EVENT_SAFETY_VIOLATION_1 \
+ CSL_DSS_VP_INTR_SAFETYVIOLATION_REGION1_MASK
+/**< \brief Safety violation region 2 interrupt */
+#define DSS_VP_EVENT_SAFETY_VIOLATION_2 \
+ CSL_DSS_VP_INTR_SAFETYVIOLATION_REGION2_MASK
+/**< \brief Safety violation region 3 interrupt */
+#define DSS_VP_EVENT_SAFETY_VIOLATION_3 \
+ CSL_DSS_VP_INTR_SAFETYVIOLATION_REGION3_MASK
+/**< \brief Safety violation region 4 interrupt */
+#define DSS_VP_EVENT_SAFETY_VIOLATION_4 \
+ CSL_DSS_VP_INTR_SAFETYVIOLATION_REGION4_MASK
+/**< \brief Safety violation region 5 interrupt */
+#define DSS_VP_EVENT_SAFETY_VIOLATION_5 \
+ CSL_DSS_VP_INTR_SAFETYVIOLATION_REGION5_MASK
+/**< \brief Safety violation region 6 interrupt */
+#define DSS_VP_EVENT_SAFETY_VIOLATION_6 \
+ CSL_DSS_VP_INTR_SAFETYVIOLATION_REGION6_MASK
+/**< \brief Safety violation region 7 interrupt */
+#define DSS_VP_EVENT_SAFETY_VIOLATION_7 \
+ CSL_DSS_VP_INTR_SAFETYVIOLATION_REGION7_MASK
+/**< \brief Security violation Interrupt */
+#define DSS_VP_EVENT_SECURITY_VIOLATION \
+ CSL_DSS_VP_INTR_SECURITYVIOLATION_MASK
+/**< \brief Go bit clear interrupt */
+#define DSS_VP_EVENT_GO_BIT_CLEAR \
+ CSL_DSS_VP_INTR_GOBITCLEAR_MASK
+/**< \brief Invalid event Id */
+#define DSS_VP_EVENT_INVALID ((uint32_t) 0xFFU)
+/* @} */
+
+/**
+ * \anchor Dss_PipeEvents
+ * \name List of Video Pipe Events.
+ *
+ * @{
+ */
+/**< \brief FBDC illegal tile request interrupt */
+#define DSS_PIPE_EVENT_FBDC_ILLEGALTILE \
+ CSL_DSS_VID_PIPE_INTR_FBDC_ILLEGALTILE_MASK
+/**< \brief FBDC corrupted tile detection interrupt */
+#define DSS_PIPE_EVENT_FBDC_CORRUPTTILE \
+ CSL_DSS_VID_PIPE_INTR_FBDC_CORRUPTTILE_MASK
+/**< \brief Safety violation interrupt */
+#define DSS_PIPE_EVENT_SAFETY_VIOLATION \
+ CSL_DSS_VID_PIPE_INTR_SAFETYVIOLATION_MASK
+/**< \brief Window end Interrupt */
+#define DSS_PIPE_EVENT_WINDOW_END \
+ CSL_DSS_VID_PIPE_INTR_WINDOWEND_MASK
+/**< \brief Buffer underflow interrupt */
+#define DSS_PIPE_EVENT_BUFF_UNDERFLOW \
+ CSL_DSS_VID_PIPE_INTR_BUFUNDERFLOW_MASK
+/* @} */
+
+/** \brief Maximum number of clients for Event Manager */
+#define DSS_EVT_MGR_MAX_CLIENTS ((uint32_t) 28U)
+
+/** \brief Maximum number of client events */
+#define DSS_EVT_MGR_MAX_CLIENT_EVENTS ((uint32_t) 21U)
+
+/** \brief Maximum number of display clients for Event Manager */
+#define DSS_DISP_EVT_MGR_MAX_CLIENTS ((uint32_t) 12U)
+
+/** \brief Maximum number of display clients per instance for Event Manager */
+#define DSS_DISP_INST_EVT_MGR_MAX_CLIENTS ((uint32_t) 3U)
+
+/** \brief Maximum number of display controller clients for Event Manager */
+#define DSS_DCTRL_EVT_MGR_MAX_CLIENTS ((uint32_t) 16U)
+
+/** \brief Size of DP Firmware (IMEM) */
+#define DCTRL_DP_IMEM_SIZE ((uint32_t) 65536U)
+
+/** \brief Size of DP Firmware (DMEM) */
+#define DCTRL_DP_DMEM_SIZE ((uint32_t) 65536U)
+
+/* ========================================================================== */
+/* Structure Declarations */
+/* ========================================================================== */
+
+/** \brief Forward declaration of Event Manager information structure */
+typedef struct Dss_EvtMgrInfo_t Dss_EvtMgrInfo;
+
+/** \brief Forward declaration of Event Manager initialization structure */
+typedef struct Dss_EvtMgrInitParams_t Dss_EvtMgrInitParams;
+
+/**
+ * \brief This structure contains common region register information
+ */
+typedef struct
+{
+ uint32_t commRegId;
+ /**< Common region id. Refer #CSL_DssCommRegId for valid values */
+ void *commRegs;
+ /**< Common region registers */
+} Dss_CommRegInfo;
+
+/**
+ * \brief This structure contains video pipe register information
+ */
+typedef struct
+{
+ uint32_t pipeId;
+ /**< Video pipe id. Refer #CSL_DssVidPipeId for valid values */
+ void *pipeRegs;
+ /**< Video Pipe registers */
+} Dss_PipeRegInfo;
+
+/**
+ * \brief This structure contains overlay register information
+ */
+typedef struct
+{
+ uint32_t overlayId;
+ /**< Overlay id. Refer #CSL_DssOverlayId for valid values */
+ void *overlayRegs;
+ /**< Overlay registers */
+} Dss_OverlayRegInfo;
+
+/**
+ * \brief This structure contains video port register information
+ */
+typedef struct
+{
+ uint32_t vpId;
+ /**< Video port id. Refer #CSL_DssVpId for valid values */
+ void *vpRegs;
+ /**< Video port registers */
+} Dss_VpRegInfo;
+
+/**
+ * \brief This structure defines module id for a particular nodeId
+ */
+typedef struct
+{
+ uint32_t nodeId;
+ /**< Node Id. Refer #Dss_DctrlNodeId for valid values */
+ uint32_t moduleId;
+ /**< Module Id */
+ uint32_t nodeType;
+ /**< Node type. Refer #Dss_DctrlNodeType for valid values */
+} Dss_DctrlNodeIdInfo;
+
+/**
+ * \brief Structure containing information about DSS register space.
+ */
+typedef struct
+{
+ CSL_dss_commRegs *commRegs[CSL_DSS_COMM_REG_ID_MAX];
+ /**< Common region registers */
+ CSL_dss_pipeRegs *pipeRegs[CSL_DSS_VID_PIPE_ID_MAX];
+ /**< Pipe registers */
+ CSL_dss_overlayRegs *overlayRegs[CSL_DSS_OVERLAY_ID_MAX];
+ /**< Overlay registers */
+ CSL_dss_vpRegs *vpRegs[CSL_DSS_VP_ID_MAX];
+ /**< Video Port registers */
+} Dss_SocInfo;
+
+/**
+ * \brief This structure defines information about overlay connection
+ */
+typedef struct
+{
+ uint32_t overlayId;
+ /**< Overlay Id. Refer #CSL_DssOverlayId for valid values */
+ uint32_t vpId;
+ /**< Video Port Id. Refer #CSL_DssVpId for valid values */
+} Dss_OverlayConnInfo;
+
+/**
+ * \brief This structure contains event group information
+ */
+typedef struct
+{
+ uint32_t eventGroup;
+ /**< Event Group. Refer \ref Dss_EventGroup for valid values */
+ uint32_t moduleId;
+ /**< Event Group's module id */
+ uint32_t eventGroupType;
+ /**< Event Group's type. Refer \ref Dss_EventGroupType for values */
+} Dss_EventGroupInfo;
+
+/**
+ * \brief This structure contains safety region information
+ */
+typedef struct
+{
+ uint32_t regionId;
+ /**< Safety region Id */
+ uint32_t regionErrEvt;
+ /**< Safety region error event */
+} Dss_VpSafetyRegionIdInfo;
+
+/* ========================================================================== */
+/* Internal/Private Function Declarations */
+/* ========================================================================== */
+
+/**
+ * \brief Dss_SocInfo structure init function
+ *
+ * \param socInfo Pointer to #Dss_SocInfo structure
+ *
+ * \return None
+ */
+static inline void Dss_socInfoInit(Dss_SocInfo *socInfo);
+
+/* ========================================================================== */
+/* Function Declarations */
+/* ========================================================================== */
+
+/**
+ * \brief This API fills the SoC information depending on the resources
+ * available to the DSS driver.
+ *
+ * \param rmInfo Resource information. Refer #Dss_RmInfo for details
+ *
+ * \return None
+ */
+void Dss_fillSocInfo(Dss_RmInfo *rmInfo);
+
+/**
+ * \brief This API gets the SoC information depending on the resources
+ * available to the DSS driver.
+ *
+ * \param None
+ *
+ * \return Pointer to Dss_SocInfo object
+ */
+const Dss_SocInfo* Dss_getSocInfo(void);
+
+/**
+ * \brief Get the module id for a given graph node.
+ *
+ * \param nodeId Node Id. Refer \ref Dss_DctrlNodeId for valid values
+ * \param moduleId Module Id
+ *
+ * \return FVID2_SOK if successful, else failure
+ */
+int32_t Dss_convNodetoModule(uint32_t nodeId,
+ uint32_t *moduleId);
+
+/**
+ * \brief Get the graph node id for a given module.
+ *
+ * \param nodeId Node Id. Refer \ref Dss_DctrlNodeId for valid values
+ * \param moduleId Module Id
+ *
+ * \return FVID2_SOK if successful, else failure
+ */
+int32_t Dss_convModuletoNode(uint32_t *nodeId,
+ uint32_t moduleId,
+ uint32_t nodeType);
+
+/**
+ * \brief Get the module id for a given event group.
+ *
+ * \param eventGroup Event Group. Refer \ref Dss_EventGroup for valid values
+ * \param moduleId Module Id
+ *
+ * \return None
+ */
+void Dss_convEventGrouptoModule(uint32_t eventGroup,
+ uint32_t *moduleId);
+
+/**
+ * \brief Get the event group for a given module.
+ *
+ * \param eventGroup Event Group. Refer \ref Dss_EventGroup.
+ * \param moduleId Module Id
+ * \param eventGroupType Event group type
+ *
+ * \return None
+ */
+void Dss_convModuletoEventGroup(uint32_t *eventGroup,
+ uint32_t moduleId,
+ uint32_t eventGroupType);
+
+/**
+ * \brief This API gets the default edge information.
+ *
+ * \param edgeMemSize Graph edge memory size
+ *
+ * \return Pointer to Fvid2_GraphEdgeInfo object
+ */
+const Fvid2_GraphEdgeInfo* Dss_dctrlGetDefaultEdgeInfo(uint32_t *edgeMemSize);
+
+/**
+ * \brief This API gets the default node information.
+ *
+ * \param nodeMemSize Graph node memory size
+ *
+ * \return Pointer to Fvid2_GraphNodeInfo object
+ */
+const Fvid2_GraphNodeInfo* Dss_dctrlGetDefaultNodeInfo(uint32_t *nodeMemSize);
+
+/**
+ * \brief Get the Video Port connected to a particular overlay.
+ *
+ * \param overlayId Overlay id. Refer #CSL_DssOverlayId for valid values
+ *
+ * \return vpId Video Port Id
+ */
+uint32_t Dss_getVpConnId(uint32_t overlayId);
+
+/**
+ * \brief This API enables the DSS event in level 1 registers for a particular
+ * event group.
+ *
+ * \param evtMgrInfo Event manager information.
+ * Refer #Dss_EvtMgrInfo for details.
+ * \param dssCommonRegionId DSS common region id
+ * \param eventGroup Event group for which event should be enabled
+ * \param event Event id
+ * \param eventCnt Event Count
+ *
+ * \return FVID2_SOK if successful, else failure
+ */
+int32_t Dss_enableL1Event(Dss_EvtMgrInfo *evtMgrInfo,
+ uint32_t dssCommonRegionId,
+ uint32_t eventGroup,
+ uint32_t event,
+ uint32_t eventCnt);
+
+/**
+ * \brief This API returns the list of enabled VP functional events.
+ *
+ * \param events Array of events.
+ * \param numEvts Pointer to number of events.
+ *
+ * \return Pointer to VP functional events.
+ */
+void Dss_getEnabledVpFuncEvents(uint32_t events[DSS_EVT_MGR_MAX_CLIENT_EVENTS],
+ uint32_t *numEvts);
+
+/**
+ * \brief This API returns the list of enabled VP error events.
+ *
+ * \param events Array of events.
+ * \param numEvts Pointer to number of events.
+ *
+ * \return Pointer to VP error events.
+ */
+void Dss_getEnabledVpErrEvents(uint32_t events[DSS_EVT_MGR_MAX_CLIENT_EVENTS],
+ uint32_t *numEvts);
+
+/**
+ * \brief This API returns the list of enabled pipe error events.
+ *
+ * \param events Array of events.
+ * \param numEvts Pointer to number of events.
+ *
+ * \return Pointer to Pipe error events.
+ */
+void Dss_getEnabledPipeErrEvents(uint32_t events[DSS_EVT_MGR_MAX_CLIENT_EVENTS],
+ uint32_t *numEvts);
+
+/**
+ * \brief Check if the given node is video pipe node
+ *
+ * \param nodeId Node Id.
+ *
+ * \return TRUE if node is Video pipe node else returns FALSE.
+ */
+uint32_t Dss_dctrlIsPipeNode(uint32_t nodeId);
+
+/**
+ * \brief Check if the given node is valid
+ *
+ * \param nodeId Node Id.
+ *
+ * \return TRUE if given node is valid else returns FALSE.
+ */
+uint32_t Dss_dctrlIsValidNode(uint32_t nodeId);
+
+/**
+ * \brief Check if the Video Mux Programming is Needed
+ *
+ * \param vpNodeId Video Port Node Id.
+ * \param outNodeId Output Node Id.
+ *
+ * \return TRUE if programming is needed else returns FALSE.
+ */
+uint32_t Dss_dctrlIsVideoMuxNeeded(uint32_t vpNodeId,
+ uint32_t outNodeId);
+
+/**
+ * \brief This API does the required video mux programming.
+ *
+ * \param vpNodeId Video Port Node Id.
+ * \param outNodeId Output Node Id.
+ *
+ * \return FVID2_SOK if programming is successful else failure.
+ */
+int32_t Dss_dctrlProgramVideoMux(uint32_t vpNodeId,
+ uint32_t outNodeId);
+
+/**
+ * \brief Get the event manager id for functional interrupts.
+ *
+ * \param None
+ *
+ * \return evtMgrId Event Manager Id
+ */
+uint32_t Dss_getEvtMgrFuncIntrId(void);
+
+/**
+ * \brief Get the event manager id for safety interrupts.
+ *
+ * \param None
+ *
+ * \return evtMgrId Event Manager Id
+ */
+uint32_t Dss_getEvtMgrSafetyIntrId(void);
+
+/**
+ * \brief Get the event manager id for security interrupts.
+ *
+ * \param None
+ *
+ * \return evtMgrId Event Manager Id
+ */
+uint32_t Dss_getEvtMgrSecurityIntrId(void);
+
+/**
+ * \brief This API fills the event manager initialization information depending
+ * on interrupt parameters passed by application.
+ *
+ * \param evtMgrParams Event manager initialization parameters.
+ * Refer #Dss_EvtMgrInitParams for details.
+ * \param irqParams DSS IRQ initialization parameters.
+ * Refer #Dss_IrqParams for details.
+ *
+ * \return FVID2_SOK if programming is successful else failure.
+ */
+int32_t Dss_fillEvtMgrInitInfo(Dss_EvtMgrInitParams *evtMgrParams,
+ Dss_IrqParams *irqParams);
+
+/**
+ * \brief Get the Safety region id for a particular safety error event.
+ *
+ * \param evtId Safety error event id.
+ *
+ * \return Safety region id.
+ */
+uint32_t Dss_dctrlGetVpSafetyRegionId(uint32_t evtId);
+
+/**
+ * \brief Get if the particular event is Safety Event.
+ *
+ * \param evtId Event id.
+ *
+ * \return TRUE if event is safety event, else FALSE.
+ */
+uint32_t Dss_dctrlIsSafetyEvent(uint32_t evtId);
+
+/**
+ * \brief Get the Safety error event id for a particular region id.
+ *
+ * \param regionId Safety region id.
+ *
+ * \return Safety error event id.
+ */
+uint32_t Dss_dctrlGetVpSafetyEvtId(uint32_t regionId);
+
+/* ========================================================================== */
+/* Static Function Definitions */
+/* ========================================================================== */
+
+static inline void Dss_socInfoInit(Dss_SocInfo *socInfo)
+{
+ uint32_t i = 0U;
+ if(NULL != socInfo)
+ {
+ for(i=CSL_DSS_COMM_REG_ID_0; i<CSL_DSS_COMM_REG_ID_MAX; i++)
+ {
+ socInfo->commRegs[i]=NULL;
+ }
+ for(i=CSL_DSS_VID_PIPE_ID_VID1; i<CSL_DSS_VID_PIPE_ID_MAX; i++)
+ {
+ socInfo->pipeRegs[i]=NULL;
+ }
+ for(i=CSL_DSS_OVERLAY_ID_1; i<CSL_DSS_OVERLAY_ID_MAX; i++)
+ {
+ socInfo->overlayRegs[i]=NULL;
+ }
+ for(i=CSL_DSS_VP_ID_1; i<CSL_DSS_VP_ID_MAX; i++)
+ {
+ socInfo->vpRegs[i]=NULL;
+ }
+ }
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #ifndef DSS_SOC_PRIV_H_ */
diff --git a/packages/ti/drv/dss/soc/dss_soc.h b/packages/ti/drv/dss/soc/dss_soc.h
--- /dev/null
@@ -0,0 +1,91 @@
+/*
+ * Copyright (c) Texas Instruments Incorporated 2018
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * \file dss_soc.h
+ *
+ * \brief DSS Driver SOC specific file.
+ */
+
+#ifndef DSS_SOC_TOP_H_
+#define DSS_SOC_TOP_H_
+
+/* ========================================================================== */
+/* Include Files */
+/* ========================================================================== */
+
+#if defined (SOC_AM65XX)
+#include <ti/drv/dss/soc/V0/dss_soc.h>
+#elif defined (SOC_J721E)
+#include <ti/drv/dss/soc/V1/dss_soc.h>
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* ========================================================================== */
+/* Macros & Typedefs */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/* Structure Declarations */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/* Internal/Private Function Declarations */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/* Function Declarations */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/* Static Function Definitions */
+/* ========================================================================== */
+
+/* None */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #ifndef DSS_SOC_TOP_H_ */
diff --git a/packages/ti/drv/dss/soc/src_files_soc.mk b/packages/ti/drv/dss/soc/src_files_soc.mk
--- /dev/null
@@ -0,0 +1,5 @@
+SRCS_COMMON += dss_soc.c dss_soc_graph.c
+
+ifeq ($(SOC),$(filter $(SOC), j721e))
+SRCS_COMMON += dss_soc_fw.c
+endif
\ No newline at end of file
diff --git a/packages/ti/drv/dss/src/csl/common/cdn_assert.h b/packages/ti/drv/dss/src/csl/common/cdn_assert.h
--- /dev/null
@@ -0,0 +1,37 @@
+/**********************************************************************
+ * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ ***********************************************************************
+ * cdn_assert.h
+ * Cadence assert file
+ ***********************************************************************/
+
+#ifndef INCLUDE_CDN_ASSERT_H
+#define INCLUDE_CDN_ASSERT_H
+
+#include <assert.h>
+
+#endif /* INCLUDE_CDN_ASSERT_H */
diff --git a/packages/ti/drv/dss/src/csl/common/cdn_errno.h b/packages/ti/drv/dss/src/csl/common/cdn_errno.h
--- /dev/null
@@ -0,0 +1,165 @@
+/******************************************************************************
+ * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ * cdn_errno.h
+ * Cadence error codes
+ ******************************************************************************
+ */
+
+#ifndef INCLUDE_CDN_ERRNO_H
+#define INCLUDE_CDN_ERRNO_H
+
+#ifndef ERRNO_H_NOT_PRESENT
+#include <errno.h>
+#endif /* ERRNO_H_NOT_PRESENT */
+
+#ifndef REMOVE_OLD_ERRORCODES
+
+#ifndef EOK
+#define EOK 0 /* no error */
+#endif /* EOK */
+
+#ifndef EPERM
+#define EPERM 1 /* Operation not permitted */
+#endif /* EPERM */
+
+#ifndef ENOENT
+#define ENOENT 2 /* No such file or directory */
+#endif /* ENOENT */
+
+#ifndef EIO
+#define EIO 5 /* I/O error */
+#endif /* EIO */
+
+#ifndef ENOEXEC
+#define ENOEXEC 8 /* Exec format error */
+#endif /* ENOEXEC */
+
+#ifndef EAGAIN
+#define EAGAIN 11 /* Try again */
+#endif /* EAGAIN */
+
+#ifndef ENOMEM
+#define ENOMEM 12 /* Out of memory */
+#endif /* ENOMEM */
+
+#ifndef EFAULT
+#define EFAULT 14 /* Bad address */
+#endif /* EFAULT */
+
+#ifndef EBUSY
+#define EBUSY 16 /* Device or resource busy */
+#endif /* EBUSY */
+
+#ifndef EINVAL
+#define EINVAL 22 /* Invalid argument */
+#endif /* EINVAL */
+
+#ifndef ENOSPC
+#define ENOSPC 28 /* No space left on device */
+#endif /* ENOSPC */
+
+#ifndef EBADSLT
+#define EBADSLT 57 /* Invalid slot */
+#endif /* EBADSLT */
+
+#ifndef EPROTO
+#define EPROTO 71 /* Protocol error */
+#endif /* EPROTO */
+
+#ifndef EOVERFLOW
+#define EOVERFLOW 75 /* Value too large for defined data type */
+#endif /* EOVERFLOW */
+
+#ifndef EOPNOTSUPP
+#define EOPNOTSUPP 95 /* Operation not supported */
+#endif /* EOPNOTSUPP */
+
+#ifndef ETIMEDOUT
+#define ETIMEDOUT 110 /* Connection timed out */
+#endif /* ETIMEDOUT */
+
+#ifndef EINPROGRESS
+#define EINPROGRESS 115 /* Operation now in progress */
+#endif /* EINPROGRESS */
+
+#ifndef EDQUOT
+#define EDQUOT 122 /* Quota exceeded */
+#endif /* EDQUOT */
+
+#ifndef ENOTSUP
+#define ENOTSUP EOPNOTSUPP
+#endif /* ENOTSUP */
+
+#ifndef ECANCELED
+#define ECANCELED 126 /* Cancelled */
+#endif /* ECANCELED */
+
+#endif /* REMOVE_OLD_ERRORCODES */
+
+#define CDN_EOK 0U /* no error */
+
+#define CDN_EPERM 1U /* Operation not permitted */
+
+#define CDN_ENOENT 2U /* No such file or directory */
+
+#define CDN_EIO 5U /* I/O error */
+
+#define CDN_ENOEXEC 8U /* Exec format error */
+
+#define CDN_EAGAIN 11U /* Try again */
+
+#define CDN_ENOMEM 12U /* Out of memory */
+
+#define CDN_EFAULT 14U /* Bad address */
+
+#define CDN_EBUSY 16U /* Device or resource busy */
+
+#define CDN_EINVAL 22U /* Invalid argument */
+
+#define CDN_ENOSPC 28U /* No space left on device */
+
+#define CDN_EBADSLT 57U /* Invalid slot */
+
+#define CDN_EPROTO 71U /* Protocol error */
+
+#define CDN_EOVERFLOW 75U /* Value too large for defined data type */
+
+#define CDN_EOPNOTSUPP 95U /* Operation not supported */
+
+#define CDN_ETIMEDOUT 110U /* Connection timed out */
+
+#define CDN_EINPROGRESS 115U /* Operation now in progress */
+
+#define CDN_EDQUOT 122U /* Quota exceeded */
+
+#define CDN_ENOTSUP CDN_EOPNOTSUPP
+
+#define CDN_ECANCELED 126U /* Cancelled */
+
+#endif /* INCLUDE_CDN_ERRNO_H */
diff --git a/packages/ti/drv/dss/src/csl/common/cdn_inttypes.h b/packages/ti/drv/dss/src/csl/common/cdn_inttypes.h
--- /dev/null
@@ -0,0 +1,40 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ * cdn_inttypes.h
+ *
+ * Header with support for integral types.
+ ******************************************************************************
+ */
+#ifndef CDN_INTTYPES_H
+#define CDN_INTTYPES_H
+
+#include <inttypes.h>
+
+#endif
diff --git a/packages/ti/drv/dss/src/csl/common/cdn_log.h b/packages/ti/drv/dss/src/csl/common/cdn_log.h
--- /dev/null
@@ -0,0 +1,148 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ * cdn_log.h
+ * System wide debug log messaging framework
+ *****************************************************************************/
+
+#ifndef INCLUDE_CDN_LOG_H
+
+#define INCLUDE_CDN_LOG_H
+
+#include "cdn_assert.h"
+#include "cdn_inttypes.h"
+
+/* parasoft-begin-suppress MISRA2012-RULE-8_6-2 "An identifier with external linkage shall have exactly one external definition, DRV-4757" */
+/* parasoft-begin-suppress MISRA2012-DIR-4_9-4 "A function should be used in preference to a function-like macro where they are interchangeable, DRV-4759" */
+
+#ifdef DEBUG
+ #if DEBUG
+ #define CFP_DBG_MSG 1
+ #endif
+#endif
+
+/**
+ * Modules definitions
+ */
+#define CLIENT_MSG 0x01000000
+
+#define DBG_GEN_MSG 0xFFFFFFFF
+
+/**
+ * Log level:
+ * DBG_CRIT - critical
+ * DBG_WARN - warning
+ * DBG_FYI - fyi
+ * DBG_HIVERB - highly verbose
+ * DBG_INFLOOP - infinite loop debug
+ */
+#define DBG_CRIT 0
+#define DBG_WARN 5
+#define DBG_FYI 10
+#define DBG_HIVERB 100
+#define DBG_INFLOOP 200
+
+/* module mask: */
+#ifdef _HAVE_DBG_LOG_INT_
+uint32_t g_dbg_enable_log = 0;
+#else
+extern uint32_t g_dbg_enable_log;
+#endif
+
+/* level, counter, state: */
+#ifdef _HAVE_DBG_LOG_INT_
+uint32_t g_dbg_log_lvl = DBG_CRIT;
+uint32_t g_dbg_log_cnt = 0;
+uint32_t g_dbg_state = 0;
+#else
+extern uint32_t g_dbg_log_lvl;
+extern uint32_t g_dbg_log_cnt;
+extern uint32_t g_dbg_state;
+#endif
+
+/* There is possibility to provide custom logging functions instead of default
+ * - DbgMsg
+ * by defining macros:
+ * - DEBUG for DbgMsg with custom print implementation
+ *
+ * There is also possibility to provide own implementation of printf() routine by
+ * defining function:
+ * DbgPrint
+ * that provides name of functions that replace printf().
+ * Their prototype:
+ * void DbgPrint(const char *fmt, ...)
+ *
+ * If DEBUG symbol is defined, then appropriate prototype is declared within this header file.
+ *
+ * If DEBUG is not defined, print is not used. Existing macros will not print any data.
+ */
+
+/* For DEBUG build, use custom logging with own implementation of DbgPrint */
+#ifdef DEBUG
+extern void DbgPrint(const char *fmt, ...);
+#define cDbgMsg( _t, _x, ...) ( ((_x) == 0) || \
+ (((_t) & g_dbg_enable_log) && ((_x) <= g_dbg_log_lvl)) ? \
+ DbgPrint( __VA_ARGS__) : 0 )
+#else
+#define cDbgMsg( _t, _x, ...)
+#endif /* DEBUG */
+
+#ifdef CFP_DBG_MSG
+#define DbgMsg( t, x, ...) cDbgMsg( (t), (x), __VA_ARGS__ )
+#else
+#define DbgMsg( t, x, ...)
+#endif
+
+#define DEBUG_PREFIX "[%-20.20s %4d %4" PRId32 "]-"
+
+/* ******** Default vDbgMsg ******** */
+# define vDbgMsg(log_lvl, module, msg, ...) DbgMsg( (log_lvl), (module), (DEBUG_PREFIX msg), __func__, \
+ __LINE__, g_dbg_log_cnt++, __VA_ARGS__)
+
+/* ******** Default cvDbgMsg ******** */
+# define cvDbgMsg(log_lvl, module, msg, ...) cDbgMsg( (log_lvl), (module), (DEBUG_PREFIX msg), __func__, \
+ __LINE__, g_dbg_log_cnt++, __VA_ARGS__)
+
+/* ******** Default cvDbgMsg ******** */
+# define evDbgMsg(log_lvl, module, msg, ...) { cDbgMsg( (log_lvl), (module), (DEBUG_PREFIX msg), __func__, \
+ __LINE__, g_dbg_log_cnt++, __VA_ARGS__); \
+ assert(0); }
+
+#define DbgMsgSetLvl( x ) (g_dbg_log_lvl = (x))
+#define DbgMsgEnableModule( x ) (g_dbg_enable_log |= (x) )
+#define DbgMsgDisableModule( x ) (g_dbg_enable_log &= ~( (uint32_t) (x) ))
+#define DbgMsgClearAll( _x ) ( g_dbg_enable_log = (_x) )
+
+#define SetDbgState( _x ) (g_dbg_state = (_x) )
+#define GetDbgState (g_dbg_state)
+
+/* parasoft-end-suppress MISRA2012-RULE-8_6-2 */
+/* parasoft-end-suppress MISRA2012-DIR-4_4-4 */
+
+#endif /* INCLUDE_CDN_LOG_H */
diff --git a/packages/ti/drv/dss/src/csl/common/cdn_math.h b/packages/ti/drv/dss/src/csl/common/cdn_math.h
--- /dev/null
@@ -0,0 +1,41 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ *
+ * cdn_math.h
+ *
+ ******************************************************************************
+ */
+
+#ifndef CDN_MATH_H
+#define CDN_MATH_H
+
+#include <math.h>
+
+#endif
diff --git a/packages/ti/drv/dss/src/csl/common/cdn_stdint.h b/packages/ti/drv/dss/src/csl/common/cdn_stdint.h
--- /dev/null
@@ -0,0 +1,61 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ * cdn_stdint.h
+ ******************************************************************************
+ */
+#ifndef CDN_STDINT
+#define CDN_STDINT
+
+#include <stdint.h>
+
+/* NOTE - The driver uses fixed width types as defined in C99
+
+ If not provided by your environment, these are typical definitions for the
+ * fixed width types used in the driver, and should be provided here.
+ * typedef signed char int8_t
+ * typedef unsigned char uint8_t
+ * typedef signed short int16_t
+ * typedef unsigned short uint16_t
+ * typedef signed long int int32_t
+ * typedef unsigned long int uint32_t
+ * typedef signed long long int int64_t
+ * typedef unsigned long long int uint64_t
+ * typedef int32_t intptr_t
+ * typedef uint32_t uintptr_t
+
+ * These definitions are for a 32bit system with 32bit int, and should be adjusted
+ * for your actual target system and toolchain.
+
+ Under Linux, these will be available in:
+ linux/types.h
+
+ */
+
+#endif
diff --git a/packages/ti/drv/dss/src/csl/common/cdn_stdtypes.h b/packages/ti/drv/dss/src/csl/common/cdn_stdtypes.h
--- /dev/null
@@ -0,0 +1,46 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ * cdn_stdtypes.h
+ * Cadence types and definitions
+ ******************************************************************************
+ */
+
+#ifndef INCLUDE_CDN_STDTYPES_H___
+#define INCLUDE_CDN_STDTYPES_H___
+#ifdef __KERNEL__
+#include <linux/types.h>
+#else
+#include "cdn_stdint.h"
+#include <stddef.h>
+#include <stdbool.h>
+
+#endif /* __KERNEL__ */
+#endif /* INCLUDE_CDN_STDTYPES_H__ */
+
diff --git a/packages/ti/drv/dss/src/csl/common/cps.h b/packages/ti/drv/dss/src/csl/common/cps.h
--- /dev/null
@@ -0,0 +1,235 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ * cps_v3.h
+ * Interface for Cadence Platform Services (CPS), version 3
+ *
+ * This is the "hardware abstraction layer" upon which all drivers are built.
+ * It must be implemented for each platform.
+ ******************************************************************************
+ */
+#ifndef CPS_V3_H
+#define CPS_V3_H
+
+#ifdef ERROR_INJECTION
+#include "cps_ei.h"
+#else
+
+#include "cdn_stdtypes.h"
+
+/* parasoft-begin-suppress MISRA2012-RULE-8_6-2 "An identifier with external linkage shall have exactly one external definition, DRV-4757" */
+/* parasoft-begin-suppress METRICS-36-3 "A function should not be called from more than 5 different functions, DRV-3823" */
+/****************************************************************************
+ * Prototypes
+ ***************************************************************************/
+
+/**
+ * Read a (32-bit) word
+ * @param[in] address the address
+ * @return the word at the given address
+ */
+extern uint32_t CPS_ReadReg32(volatile uint32_t* address);
+
+/**
+ * Write a (32-bit) word to memory
+ * @param[in] address the address
+ * @param[in] value the word to write
+ */
+extern void CPS_WriteReg32(volatile uint32_t* address, uint32_t value);
+
+/**
+ * Read a (64-bit) word
+ * @param[in] address the address
+ * @return the word at the given address
+ */
+extern uint64_t CPS_ReadReg64(volatile uint64_t* address);
+
+/**
+ * Write a (64-bit) word to memory
+ * @param[in] address the address
+ * @param[in] value the word to write
+ */
+extern void CPS_WriteReg64(volatile uint64_t* address, uint64_t value);
+
+/**
+ * Read a byte, bypassing the cache
+ * @param[in] address the address
+ * @return the byte at the given address
+ */
+extern uint8_t CPS_UncachedRead8(volatile uint8_t* address);
+
+/**
+ * Read a short, bypassing the cache
+ * @param[in] address the address
+ * @return the short at the given address
+ */
+extern uint16_t CPS_UncachedRead16(volatile uint16_t* address);
+
+/**
+ * Read a (32-bit) word, bypassing the cache
+ * @param[in] address the address
+ * @return the word at the given address
+ */
+extern uint32_t CPS_UncachedRead32(volatile uint32_t* address);
+
+/**
+ * Read a (64-bit) dword, bypassing the cache
+ * @param[in] address the address
+ * @return the 64-bit dword at the given address
+ */
+extern uint64_t CPS_UncachedRead64(volatile uint64_t* address);
+
+/**
+ * Write a byte to memory, bypassing the cache
+ * @param[in] address the address
+ * @param[in] value the byte to write
+ */
+extern void CPS_UncachedWrite8(volatile uint8_t* address, uint8_t value);
+
+/**
+ * Write a short to memory, bypassing the cache
+ * @param[in] address the address
+ * @param[in] value the short to write
+ */
+extern void CPS_UncachedWrite16(volatile uint16_t* address, uint16_t value);
+
+/**
+ * Write a (32-bit) word to memory, bypassing the cache
+ * @param[in] address the address
+ * @param[in] value the word to write
+ */
+extern void CPS_UncachedWrite32(volatile uint32_t* address, uint32_t value);
+
+/**
+ * Write a (64-bit) dword to memory, bypassing the cache
+ * @param[in] address the address
+ * @param[in] value the (64-bit) dword to write
+ */
+extern void CPS_UncachedWrite64(volatile uint64_t* address, uint64_t value);
+
+/**
+ * Write a (32-bit) address value to memory, bypassing the cache.
+ * This function is for writing an address value, i.e. something that
+ * will be treated as an address by hardware, and therefore might need
+ * to be translated to a physical bus address.
+ * @param[in] location the (CPU) location where to write the address value
+ * @param[in] addrValue the address value to write
+ */
+extern void CPS_WritePhysAddress32(volatile uint32_t* location, uint32_t addrValue);
+
+/**
+ * Hardware specific memcpy.
+ * @param[in] src src address
+ * @param[in] dst destination address
+ * @param[in] size size of the copy
+ */
+extern void CPS_BufferCopy(volatile uint8_t *dst, volatile const uint8_t *src, uint32_t size);
+
+/**
+ * Invalidate the cache for the specified memory region.
+ * This function may be stubbed out if caching is disabled for memory regions
+ * as described in the driver documentation, or if the driver configuration does
+ * not require this function.
+ * @param[in] address Virtual address of memory region. (If an MMU is not in use,
+ * this will be equivalent to the physical address.) This address should be
+ * rounded down to the nearest cache line boundary.
+ * @param[in] size size of memory in bytes. This size should be rounded up to
+ * the nearest cache line boundary. Use size UINTPTR_MAX to invalidate all
+ * memory cache. A size of 0 should be ignored and the function should return
+ * immediately with no effect.
+ * @param[in] devInfo This parameter can be used to pass implementation specific
+ * data to this function. The content and use of this parameter is up to the
+ * implementor of this function to determine, and if not required it may be ignored.
+ * For example, under Linux it can be used to pass a pointer to
+ * the device struct to be used in a call to dma_sync_single_for_device(). If
+ * used, the parameter should be passed to the core driver at initialisation as
+ * part of the configurationInfo struct. Please
+ * see the core driver documentation for details of how to do this.
+ */
+extern void CPS_CacheInvalidate(void* address, size_t size, uintptr_t devInfo);
+
+/**
+ * Flush the cache for the specified memory region
+ * This function may be stubbed out if caching is disabled for memory regions
+ * as described in the driver documentation, or if the driver configuration does
+ * not require this function.
+ * @param[in] address Virtual address of memory region. (If an MMU is not in use,
+ * this will be equivalent to the physical address.) This address should be
+ * rounded down to the nearest cache line boundary.
+ * @param[in] size size of memory in bytes. This size should be rounded up to
+ * the nearest cache line boundary. Use size UINTPTR_MAX to flush all
+ * memory cache. A size of 0 should be ignored and the function should return
+ * immediately with no effect.
+ * @param[in] devInfo This parameter can be used to pass implementation specific
+ * data to this function. The content and use of this parameter is up to the
+ * implementor of this function to determine, and if not required it may be ignored.
+ * For example, under Linux it can be used to pass a pointer to
+ * the device struct to be used in a call to dma_sync_single_for_device(). If
+ * used, the parameter should be passed to the core driver at initialisation as
+ * part of the configurationInfo struct. Please
+ * see the core driver documentation for details of how to do this.
+ */
+extern void CPS_CacheFlush(void* address, size_t size, uintptr_t devInfo);
+
+/**
+ * Delay software execution by a number of nanoseconds
+ * @param[in] ns number of nanoseconds to delay software execution
+ */
+extern void CPS_DelayNs(uint32_t ns);
+
+/**
+ * Memory barrier
+ * Waits until previous data accesses are finished
+ */
+extern void CPS_MemoryBarrier(void);
+
+/**
+ * Write Memory Barrier
+ * Waits until previous data stores are finished
+ */
+extern void CPS_MemoryBarrierWrite(void);
+
+/**
+ * Read Memory barrier
+ * Waits until previous data loads are finished
+ */
+extern void CPS_MemoryBarrierRead(void);
+
+/**
+ * External (platform specific PHY reset
+ */
+extern void CPS_ExtPhyReset(bool reset);
+
+
+/* parasoft-end-suppress METRICS-36-3 */
+/* parasoft-end-suppress MISRA2012-RULE-8_6-2 */
+
+#endif /* ERROR_INJECTION */
+
+#endif /* multiple inclusion protection */
diff --git a/packages/ti/drv/dss/src/csl/common/cps_drv.h b/packages/ti/drv/dss/src/csl/common/cps_drv.h
--- /dev/null
@@ -0,0 +1,238 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ * cps_drv.h
+ * Interface for the Register Access Layer of Cadence Platform Service (CPS)
+ ******************************************************************************
+ */
+
+#ifndef CPS_DRV_H_
+#define CPS_DRV_H_
+
+#include "cps.h"
+
+/* parasoft-begin-suppress MISRA2012-DIR-4_9-4 "function-like macro, DRV-4760" */
+/* parasoft-begin-suppress MISRA2012-RULE-20_10-4 "## preprocessor operator, DRV-4761" */
+/* parasoft-begin-suppress METRICS-36-3 "A function should not be called from more than 5 different functions, DRV-3823" */
+
+/**
+ * \brief Read a 32-bit value from memory.
+ * \param reg address of the memory mapped hardware register
+ * \return the value at the given address
+ */
+#define CPS_REG_READ(reg) (CPS_RegRead((volatile uint32_t*)(reg)))
+
+/**
+ * \brief Write a 32-bit address value to memory.
+ * \param reg address of the memory mapped hardware register
+ * \param value unsigned 32-bit value to write
+ */
+#define CPS_REG_WRITE(reg, value) (CPS_RegWrite((volatile uint32_t*)(reg), (uint32_t)(value)))
+
+/**
+ * \brief Read a 64-bit value from memory.
+ * \param reg address of the memory mapped hardware register
+ * \return the value at the given address
+ */
+#define CPS_REG_READ64(reg) (CPS_RegRead64((volatile uint64_t*)(reg)))
+
+/**
+ * \brief Write a 64-bit address value to memory.
+ * \param reg address of the memory mapped hardware register
+ * \param value unsigned 64-bit value to write
+ */
+#define CPS_REG_WRITE64(reg, value) (CPS_RegWrite64((volatile uint64_t*)(reg), (uint64_t)(value)))
+
+/**
+ * \brief Read a value of bit-field from the register value.
+ * \param reg register name
+ * \param fld field name
+ * \param reg_value register value
+ * \return bit-field value
+ */
+#define CPS_FLD_READ(reg, fld, reg_value) (CPS_FldRead((uint32_t)(reg ## __ ## fld ## _MASK), \
+ (uint32_t)(reg ## __ ## fld ## _SHIFT), \
+ (uint32_t)(reg_value)))
+
+/**
+ * \brief Write a value of the bit-field into the register value.
+ * \param reg register name
+ * \param fld field name
+ * \param reg_value register value
+ * \param value value to be written to bit-field
+ * \return modified register value
+ */
+#define CPS_FLD_WRITE(reg, fld, reg_value, value) (CPS_FldWrite((uint32_t)(reg ## __ ## fld ## _MASK), \
+ (uint32_t)(reg ## __ ## fld ## _SHIFT), \
+ (uint32_t)(reg_value), (uint32_t)(value)))
+
+/**
+ * \brief Set bit within the register value.
+ * \param reg register name
+ * \param fld field name
+ * \param reg_value register value
+ * \return modified register value
+ */
+#define CPS_FLD_SET(reg, fld, reg_value) (CPS_FldSet((uint32_t)(reg ## __ ## fld ## _WIDTH), \
+ (uint32_t)(reg ## __ ## fld ## _MASK), \
+ (uint32_t)(reg ## __ ## fld ## _WOCLR), \
+ (uint32_t)(reg_value)))
+
+/**
+ * \brief Clear bit within the register value.
+ * \param reg register name
+ * \param fld field name
+ * \param reg_value register value
+ * \return modified register value
+ */
+#define CPS_FLD_CLEAR(reg, fld, reg_value) (CPS_FldClear((uint32_t)(reg ## __ ## fld ## _WIDTH), \
+ (uint32_t)(reg ## __ ## fld ## _MASK), \
+ (uint32_t)(reg ## __ ## fld ## _WOSET), \
+ (uint32_t)(reg ## __ ## fld ## _WOCLR), \
+ (uint32_t)(reg_value)))
+
+/**
+ * \brief Read a 32-bit value from memory.
+ * \param reg address of the memory mapped hardware register
+ * \return the value at the given address
+ */
+static inline uint32_t CPS_RegRead(volatile uint32_t* reg)
+{
+ return (CPS_ReadReg32(reg));
+}
+
+/**
+ * \brief Write a 32-bit address value to memory.
+ * \param reg address of the memory mapped hardware register
+ * \param value unsigned 32-bit value to write
+ */
+static inline void CPS_RegWrite(volatile uint32_t* reg, uint32_t value)
+{
+ CPS_WriteReg32(reg, value);
+}
+
+/**
+ * \brief Read a 64-bit value from memory.
+ * \param reg address of the memory mapped hardware register
+ * \return the value at the given address
+ */
+static inline uint64_t CPS_RegRead64(volatile uint64_t* reg)
+{
+ return (CPS_ReadReg64(reg));
+}
+
+/**
+ * \brief Write a 64-bit address value to memory.
+ * \param reg address of the memory mapped hardware register
+ * \param value unsigned 64-bit value to write
+ */
+static inline void CPS_RegWrite64(volatile uint64_t* reg, uint64_t value)
+{
+ CPS_WriteReg64(reg, value);
+}
+
+/**
+ * \brief Read a value of bit-field from the register value.
+ * \param mask mask for the bit-field
+ * \param shift bit-field shift from LSB
+ * \param reg_value register value
+ * \return bit-field value
+ */
+static inline uint32_t CPS_FldRead(uint32_t mask, uint32_t shift, uint32_t reg_value)
+{
+ /* parasoft-begin-suppress MISRA2012-RULE-12_2-2 "shift ranges, DRV-4915" */
+ uint32_t result = (reg_value & mask) >> shift;
+ /* parasoft-end-suppress MISRA2012-RULE-12_2-2 */
+
+ return (result);
+}
+
+/**
+ * \brief Write a value of the bit-field into the register value.
+ * \param mask mask for the bit-field
+ * \param shift bit-field shift from LSB
+ * \param reg_value register value
+ * \param value value to be written to bit-field
+ * \return modified register value
+ */
+static inline uint32_t CPS_FldWrite(uint32_t mask, uint32_t shift, uint32_t reg_value, uint32_t value)
+{
+ /* parasoft-begin-suppress MISRA2012-RULE-12_2-2 "shift ranges, DRV-4915" */
+ uint32_t new_value = (value << shift) & mask;
+ /* parasoft-end-suppress MISRA2012-RULE-12_2-2 */
+
+ new_value = (reg_value & ~mask) | new_value;
+ return (new_value);
+}
+
+/**
+ * \brief Set bit within the register value.
+ * \param width width of the bit-field
+ * \param mask mask for the bit-field
+ * \param is_woclr is bit-field has 'write one to clear' flag set
+ * \param reg_value register value
+ * \return modified register value
+ */
+static inline uint32_t CPS_FldSet(uint32_t width, uint32_t mask, uint32_t is_woclr, uint32_t reg_value)
+{
+ uint32_t new_value = reg_value;
+ if ((width == 1U) && (is_woclr == 0U)) {
+ new_value |= mask;
+ }
+
+ return (new_value);
+}
+
+/**
+ * \brief Clear bit within the register value.
+ *
+ * \param width Width of the bit-field.
+ * \param mask Mask for the bit-field.
+ * \param is_woset Is bit-field has 'write one to set' flag set.
+ * \param is_woclr Is bit-field has 'write one to clear' flag set.
+ * \param reg_value Register value.
+ *
+ * \return Modified register value.
+ */
+static inline uint32_t CPS_FldClear(uint32_t width, uint32_t mask, uint32_t is_woset, uint32_t is_woclr, uint32_t reg_value)
+{
+ uint32_t new_value = reg_value;
+ if ((width == 1U) && (is_woset == 0U)) {
+ new_value = (new_value & ~mask) | ((is_woclr != 0U) ? mask : 0U);
+ }
+
+ return (new_value);
+}
+
+/* parasoft-end-suppress MISRA2012-RULE-20_10-4 */
+/* parasoft-end-suppress MISRA2012-DIR-4_9-4 */
+/* parasoft-end-suppress METRICS-36-3 */
+
+#endif /* CPS_DRV_H_ */
+
diff --git a/packages/ti/drv/dss/src/csl/csl_priv.c b/packages/ti/drv/dss/src/csl/csl_priv.c
--- /dev/null
@@ -0,0 +1,141 @@
+#include <ti/drv/dss/src/csl/dp/csl_dp.h>
+#include <ti/drv/dss/src/csl/dp_sd0801/csl_dp_sd0801.h>
+#include <ti/drv/dss/dss.h>
+
+#define ADDR_AFE (0x05050000)
+#define DSSEDP0_CFGR1_BASE (0x0A000000)
+#define DSSEDP0_CFGR2_BASE (0x04F48000)
+#define APB_BASE DSSEDP0_CFGR1_BASE
+#define SAPB_BASE DSSEDP0_CFGR2_BASE
+#define PHAPB_BASE ADDR_AFE
+#define APB_SIZE (0x00100000)
+#define SAPB_SIZE (0x00100000)
+#define PHAPB_SIZE (0x00100000)
+
+/*
+ * CDNS PHY memory map is based on 16b halfword in 32-bit word address
+ * TI wiz wrapper collapsed them into 16b word addresses.
+ * But, kept the same section addressing [17:14]
+ * cdn_phapb_read/write converts CDNS PHY access to TI access
+ * by mapping addr[17:14] in 15:12 and addr[12:2] in 11:1
+ */
+static uint32_t cdn_phapb_xlate(uint32_t addr)
+{
+ return (((addr & 0x3C000) >> 2) | ((addr & 0x1FFC) >> 1));
+}
+
+static uint32_t cdn_phapb_read(uint32_t addr)
+{
+ return CSL_REG16_RD(ADDR_AFE + cdn_phapb_xlate(addr));
+}
+
+static void cdn_phapb_write(uint32_t addr, uint32_t data)
+{
+ CSL_REG16_WR(ADDR_AFE + cdn_phapb_xlate(addr), (0xFFFF & data));
+}
+
+static uint32_t cdn_apb_read(uint32_t addr)
+{
+ return CSL_REG32_RD(DSSEDP0_CFGR1_BASE + addr);
+}
+
+static void cdn_apb_write(uint32_t addr, uint32_t data)
+{
+ CSL_REG32_WR(DSSEDP0_CFGR1_BASE + addr, data);
+}
+
+static uint32_t cdn_sapb_read(uint32_t addr)
+{
+ return CSL_REG32_RD(DSSEDP0_CFGR2_BASE + addr);
+}
+
+static void cdn_sapb_write(uint32_t addr, uint32_t data)
+{
+ CSL_REG32_WR(DSSEDP0_CFGR2_BASE + addr, data);
+}
+
+void CPS_BufferCopy(volatile uint8_t *dst, volatile const uint8_t *src, uint32_t size)
+{
+ memcpy((void *)dst, (void *)src, size);
+}
+
+void CPS_DelayNs(uint32_t ns)
+{
+ uint32_t us = ns / 1000;
+ if(0U == us)
+ {
+ /* If less than 1 us sleep requested, fall back to 1 us */
+ us = 1;
+ }
+
+ Osal_delay(us);
+}
+
+void CPS_ExtPhyReset(bool reset)
+{
+ uint32_t regVal;
+
+ regVal = CSL_REG32_RD(ADDR_AFE + 0x40C);
+ CSL_FINSR(regVal, 31, 31, reset ? 0 : 1);
+ CSL_REG32_WR(ADDR_AFE + 0x40C, regVal);
+}
+
+uint32_t CPS_ReadReg32(volatile uint32_t* address)
+{
+ uint32_t data;
+ uintptr_t address_int = (uintptr_t)address;
+
+ if ((address_int >= APB_BASE) &&
+ (address_int < APB_BASE + APB_SIZE))
+ {
+ data = cdn_apb_read(address_int - APB_BASE);
+ }
+ else if ((address_int >= SAPB_BASE) &&
+ (address_int < SAPB_BASE + SAPB_SIZE))
+ {
+ data = cdn_sapb_read(address_int - SAPB_BASE);
+ }
+ else if((address_int >= PHAPB_BASE) &&
+ (address_int < PHAPB_BASE + PHAPB_SIZE))
+ {
+ data = cdn_phapb_read(address_int - PHAPB_BASE);
+ }
+ else
+ {
+ GT_1trace(DssTrace,
+ GT_ERR,
+ "Address %d (read) doesn't map to any DP bus",
+ address);
+ data = 0u;
+ }
+
+ return data;
+}
+
+void CPS_WriteReg32(volatile uint32_t* address, uint32_t value)
+{
+ uintptr_t address_int = (uintptr_t)address;
+
+ if((address_int >= APB_BASE) &&
+ (address_int < APB_BASE + APB_SIZE))
+ {
+ cdn_apb_write(address_int - APB_BASE, value);
+ }
+ else if ((address_int >= SAPB_BASE) &&
+ (address_int < SAPB_BASE + SAPB_SIZE))
+ {
+ cdn_sapb_write(address_int - SAPB_BASE, value);
+ }
+ else if((address_int >= PHAPB_BASE) &&
+ (address_int < PHAPB_BASE + PHAPB_SIZE))
+ {
+ cdn_phapb_write(address_int - PHAPB_BASE, value);
+ }
+ else
+ {
+ GT_1trace(DssTrace,
+ GT_ERR,
+ "Address %d (write) doesn't map to any DP bus",
+ address);
+ }
+}
diff --git a/packages/ti/drv/dss/src/csl/dp/csl_dp.h b/packages/ti/drv/dss/src/csl/dp/csl_dp.h
--- /dev/null
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) Texas Instruments Incorporated 2018
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+/**
+ * \file csl_dp.h
+ *
+ * \brief CSL APIs for Display Port (DP).
+ */
+
+#ifndef CSL_DP_H_
+#define CSL_DP_H_
+
+#include <src/csl/dp/include/dp_if.h>
+#include <src/csl/dp/include/dp_structs_if.h>
+
+#endif
diff --git a/packages/ti/drv/dss/src/csl/dp/include/dp_aux_if.h b/packages/ti/drv/dss/src/csl/dp/include/dp_aux_if.h
--- /dev/null
@@ -0,0 +1,66 @@
+/**********************************************************************
+* Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* 1. Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* 2. Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the distribution.
+* 3. Neither the name of the copyright holder nor the names of its
+* contributors may be used to endorse or promote products derived from
+* this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+**********************************************************************
+* WARNING: This file is auto-generated using api-generator utility.
+* api-generator: 12.03.9e11b77(origin/DRV-3827_extract_sanity_to_c_file)
+* Do not edit it manually.
+**********************************************************************
+* Cadence Core Driver for the Cadence DisplayPort (DP) core. This header
+* file lists the Supporting structures for the DP core driver
+**********************************************************************/
+
+#ifndef DP_AUX_IF_H
+#define DP_AUX_IF_H
+
+/* parasoft-begin-suppress MISRA2012-RULE-1_1_a_c90-2 "C90 - limits, DRV-3906" */
+/* parasoft-begin-suppress MISRA2012-RULE-1_1_b_c90-2 "C90 - limits, DRV-3906" */
+
+#include "cdn_log.h"
+#include "cdn_stdtypes.h"
+#include "dp_if.h"
+
+/** @defgroup DataStructure Dynamic Data Structures
+ * This section defines the data structures used by the driver to provide
+ * hardware information, modification and dynamic operation of the driver.
+ * These data structures are defined in the header file of the core driver
+ * and utilized by the API.
+ * @{
+ */
+
+/**********************************************************************
+* Forward declarations
+**********************************************************************/
+typedef struct AUX_drm_dp_s AUX_drm_dp;
+
+/**
+ * @}
+ */
+
+/* parasoft-end-suppress MISRA2012-RULE-1_1_b_c90-2 */
+/* parasoft-end-suppress MISRA2012-RULE-1_1_a_c90-2 */
+
+#endif /* DP_AUX_IF_H */
diff --git a/packages/ti/drv/dss/src/csl/dp/include/dp_aux_obj_if.h b/packages/ti/drv/dss/src/csl/dp/include/dp_aux_obj_if.h
--- /dev/null
@@ -0,0 +1,40 @@
+/**********************************************************************
+* Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* 1. Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* 2. Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the distribution.
+* 3. Neither the name of the copyright holder nor the names of its
+* contributors may be used to endorse or promote products derived from
+* this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+**********************************************************************
+* WARNING: This file is auto-generated using api-generator utility.
+* api-generator: 12.03.9e11b77(origin/DRV-3827_extract_sanity_to_c_file)
+* Do not edit it manually.
+**********************************************************************
+* Cadence Core Driver for the Cadence DisplayPort (DP) core. This header
+* file lists the Supporting structures for the DP core driver
+**********************************************************************/
+#ifndef DP_AUX_OBJ_IF_H
+#define DP_AUX_OBJ_IF_H
+
+#include "dp_aux_if.h"
+
+#endif /* DP_AUX_OBJ_IF_H */
diff --git a/packages/ti/drv/dss/src/csl/dp/include/dp_aux_structs_if.h b/packages/ti/drv/dss/src/csl/dp/include/dp_aux_structs_if.h
--- /dev/null
@@ -0,0 +1,61 @@
+/* parasoft suppress item MISRA2012-DIR-4_8 "Consider hiding implementation of structure" */
+/**********************************************************************
+* Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* 1. Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* 2. Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the distribution.
+* 3. Neither the name of the copyright holder nor the names of its
+* contributors may be used to endorse or promote products derived from
+* this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+**********************************************************************
+* WARNING: This file is auto-generated using api-generator utility.
+* api-generator: 12.03.9e11b77(origin/DRV-3827_extract_sanity_to_c_file)
+* Do not edit it manually.
+**********************************************************************
+* Cadence Core Driver for the Cadence DisplayPort (DP) core. This header
+* file lists the Supporting structures for the DP core driver
+**********************************************************************/
+#ifndef DP_AUX_STRUCTS_IF_H
+#define DP_AUX_STRUCTS_IF_H
+
+#include "cdn_stdtypes.h"
+#include "dp_aux_if.h"
+
+/** @defgroup DataStructure Dynamic Data Structures
+ * This section defines the data structures used by the driver to provide
+ * hardware information, modification and dynamic operation of the driver.
+ * These data structures are defined in the header file of the core driver
+ * and utilized by the API.
+ * @{
+ */
+
+/**********************************************************************
+* Structures and unions
+**********************************************************************/
+struct AUX_drm_dp_s {
+ DP_PrivateData* pD;
+};
+
+/**
+ * @}
+ */
+
+#endif /* DP_AUX_STRUCTS_IF_H */
diff --git a/packages/ti/drv/dss/src/csl/dp/include/dp_if.h b/packages/ti/drv/dss/src/csl/dp/include/dp_if.h
--- /dev/null
@@ -0,0 +1,2025 @@
+/**********************************************************************
+* Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* 1. Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* 2. Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the distribution.
+* 3. Neither the name of the copyright holder nor the names of its
+* contributors may be used to endorse or promote products derived from
+* this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+**********************************************************************
+* WARNING: This file is auto-generated using api-generator utility.
+* api-generator: 12.03.9e11b77(origin/DRV-3827_extract_sanity_to_c_file)
+* Do not edit it manually.
+**********************************************************************
+* Cadence Core Driver for the Cadence DisplayPort (DP) core. This header
+* file lists the API providing a HAL (hardware abstraction layer)
+* interface for the DP core
+**********************************************************************/
+
+#ifndef DP_IF_H
+#define DP_IF_H
+
+/* parasoft-begin-suppress MISRA2012-RULE-1_1_a_c90-2 "C90 - limits, DRV-3906" */
+/* parasoft-begin-suppress MISRA2012-RULE-1_1_b_c90-2 "C90 - limits, DRV-3906" */
+
+#include "cdn_errno.h"
+#include "cdn_stdtypes.h"
+#include "custom_types.h"
+#include "dp_aux_if.h"
+#include "dp_mst_if.h"
+#include "dp_sd0801_if.h"
+#include "dp_sideband_msg_if.h"
+#include "dp_topology_mgr.h"
+
+/** @defgroup ConfigInfo Configuration and Hardware Operation Information
+ * The following definitions specify the driver operation environment that
+ * is defined by hardware configuration or client code. These defines are
+ * located in the header file of the core driver.
+ * @{
+ */
+
+/**********************************************************************
+* Defines
+**********************************************************************/
+/** Max. possible amount of DPCD bytes to write/read using a single request. */
+#define DP_MAX_DPCD_TRANSFER_SIZE 1014U
+
+/** Max. possible DPCD read retries before bailing out */
+#define DP_MAX_DPCD_READ_RETRIES 3U
+
+/**
+ * Max. possible amount of bytes to write/read using I2C-over-AUX using a
+ * single request.
+ */
+#define DP_MAX_I2C_TRANSFER_SIZE 1014U
+
+/** Number of voltage swing levels. */
+#define DP_SWING_LEVEL_COUNT 4U
+
+/** Number of pre-emphasis levels. */
+#define DP_EMPHASIS_LEVEL_COUNT 4U
+
+#define DP_DSC_NUM_BUF_RANGES (15U)
+
+#define DP_DSC_PPS_SIZE (128U)
+
+/** number of existing encoders */
+#define DP_NUMBER_OF_DSC_ENCODERS (2U)
+
+/** maximum number of SDP packets per stream */
+#define DP_MAX_NUMBER_OF_SDPS (16U)
+
+/** maximum number of streams in MST mode */
+#define DP_MAX_NUMBER_OF_STREAMS (4U)
+
+#define DP_HDCP2_PUBLIC_KEY_N_LENGTH (384U)
+
+#define DP_HDCP2_PUBLIC_KEY_E_LENGTH (3U)
+
+#define DP_HDCP_CUSTOM_KEY_LENGTH (16U)
+
+#define DP_HDCP_RECV_ID_LENGTH (5U)
+
+#define DP_HDCP1_KEY_SET_LENGTH (280U)
+
+#define DP_HDCP_M_LENGTH (16U)
+
+#define DP_HDCP_KM_LENGTH (16U)
+
+#define DP_HDCP_RANDOM_RN_LENGTH (8U)
+
+#define DP_HDCP_RANDOM_KS_LENGTH (16U)
+
+#define DP_HDCP_RANDOM_RIV_LENGTH (8U)
+
+#define DP_HDCP_RANDOM_RTX_LENGTH (8U)
+
+#define DP_HDCP_LC128_LENGTH (16U)
+
+#define DP_HDCP_SEED_LENGTH (32U)
+
+#define DP_MAX_NUMBER_OF_LANES (4U)
+
+/**
+ * @}
+ */
+
+/** @defgroup DataStructure Dynamic Data Structures
+ * This section defines the data structures used by the driver to provide
+ * hardware information, modification and dynamic operation of the driver.
+ * These data structures are defined in the header file of the core driver
+ * and utilized by the API.
+ * @{
+ */
+
+/**********************************************************************
+* Forward declarations
+**********************************************************************/
+typedef struct DP_VideoFormatParams_s DP_VideoFormatParams;
+typedef struct DP_SourceDeviceCapabilities_s DP_SourceDeviceCapabilities;
+typedef struct DP_SinkDeviceCapabilities_s DP_SinkDeviceCapabilities;
+typedef struct DP_ReadEdidResponse_s DP_ReadEdidResponse;
+typedef struct DP_DpcdTransfer_s DP_DpcdTransfer;
+typedef struct DP_I2cTransfer_s DP_I2cTransfer;
+typedef struct DP_VideoParameters_s DP_VideoParameters;
+typedef struct DP_LinkState_s DP_LinkState;
+typedef struct DP_SdpEntry_s DP_SdpEntry;
+typedef struct DP_HdcpTxConfiguration_s DP_HdcpTxConfiguration;
+typedef struct DP_Hdcp2TxPublicKey_s DP_Hdcp2TxPublicKey;
+typedef struct DP_HdcpTxKmEncCustomKey_s DP_HdcpTxKmEncCustomKey;
+typedef struct DP_HdcpDebugRandomNumbers_s DP_HdcpDebugRandomNumbers;
+typedef struct DP_HdcpPairingData_s DP_HdcpPairingData;
+typedef struct DP_Hdcp1Keys_s DP_Hdcp1Keys;
+typedef struct DP_HdcpTxStatus_s DP_HdcpTxStatus;
+typedef struct DP_HdcpRecvIdList_s DP_HdcpRecvIdList;
+typedef struct DP_AudioParams_s DP_AudioParams;
+typedef struct DP_DscRangeCfg_s DP_DscRangeCfg;
+typedef struct DP_DscConfig_s DP_DscConfig;
+typedef struct DP_Config_s DP_Config;
+typedef struct DP_Callbacks_s DP_Callbacks;
+typedef struct DP_SinkDevice_s DP_SinkDevice;
+typedef struct DP_FirmwareImage_s DP_FirmwareImage;
+typedef struct DP_UcpuClock_s DP_UcpuClock;
+typedef struct DP_AudioVideoClkCfg_s DP_AudioVideoClkCfg;
+
+typedef struct DP_PrivateData_s DP_PrivateData;
+
+/**********************************************************************
+* Enumerations
+**********************************************************************/
+typedef enum
+{
+ /** Set sink device to D0 power state (normal operation) */
+ DP_POWER_NORMAL_OPERATION = 1U,
+ /** Set sink device to D3 power state (power down) */
+ DP_POWER_DOWN = 2U,
+ /** Similar to POWER_DOWN, but keep AUX block fully powered. */
+ DP_POWER_AUX_ONLY = 5U
+} DP_PwrMode;
+
+typedef enum
+{
+ DP_LINK_RATE_1_62 = 0x00U,
+ DP_LINK_RATE_2_16 = 0x01U,
+ DP_LINK_RATE_2_43 = 0x02U,
+ DP_LINK_RATE_2_70 = 0x03U,
+ DP_LINK_RATE_3_24 = 0x04U,
+ DP_LINK_RATE_4_32 = 0x05U,
+ DP_LINK_RATE_5_40 = 0x06U,
+ DP_LINK_RATE_8_10 = 0x07U
+} DP_LinkRate;
+
+/** Specifies, how physical PHY lanes are mapped to ports of receiver(s) */
+typedef enum
+{
+ /** Single controller is used. Lanes are not crossed (0->0, 1->1, 2->2, 3->3). */
+ DP_LANE_MAPPING_SINGLE_REGULAR = 0xE4U,
+ /**
+ * Up to two controllers are used with a PHY. Currently configured
+ * controller uses only up to 2 lanes: lane 0 and lane 1. (0->0, 1->1)
+ */
+ DP_LANE_MAPPING_DUAL_LANES_01 = 0x04U,
+ /**
+ * Up to two controllers are used with a PHY. Currently configured
+ * controller uses only up to 2 lanes: lane 2 and lane 3. (0->2, 1->3)
+ */
+ DP_LANE_MAPPING_DUAL_LANES_23 = 0x0EU
+} DP_LaneMapping;
+
+/** Number of controllers per PHY. */
+typedef enum
+{
+ /** Only one controller is used with PHY. */
+ DP_SINGLE_CONTROLLER = 0x01U,
+ /** Two controllers are used with PHY. */
+ DP_DUAL_CONTROLLER = 0x02U
+} DP_ControllersPerPhy;
+
+/** Selects test pattern to be transmitted. */
+typedef enum
+{
+ /** Transmit PRBS7 pattern. */
+ DP_PATTERN_PRBS7 = 0x00U,
+ /** Transmit TPS1 pattern. */
+ DP_PATTERN_TPS1 = 0x01U,
+ /** Transmit TPS2 pattern. */
+ DP_PATTERN_TPS2 = 0x02U,
+ /** Transmit TPS3 pattern. */
+ DP_PATTERN_TPS3 = 0x03U,
+ /** Transmit TPS4 pattern. */
+ DP_PATTERN_TPS4 = 0x04U,
+ /** Transmit custom 80-bit pattern (set using DP_SetCustomPattern). */
+ DP_PATTERN_80_BIT = 0x05U,
+ /** Transmit D10.2 pattern (same as TPS1). */
+ DP_PATTERN_D10_2 = 0x06U,
+ /** Transmit Symbol Error Rate Measurement pattern. */
+ DP_PATTERN_SYMBOL_ERM = 0x07U,
+ /** Transmit CP2520 pattern 1. */
+ DP_PATTERN_CP2520_1 = 0x08U,
+ /** Transmit CP2520 pattern 2. */
+ DP_PATTERN_CP2520_2 = 0x09U,
+ /** Transmit CP2520 pattern 3. */
+ DP_PATTERN_CP2520_3 = 0x0AU,
+ /** Stop transmitting test pattern. */
+ DP_PATTERN_DISABLE = 0x0BU
+} DP_TestPattern;
+
+/** DP events. Each value represents one bit and may be set or cleared. */
+typedef enum
+{
+ /** HPD state has changed. */
+ DP_TX_HPD_EVENT = 0x01U,
+ /** HDCP TX status has changed. */
+ DP_HDCP_TX_STATUS_EVENT = 0x10U,
+ /**
+ * Host needs to check, if pairing data (including km) associated with
+ * Receiver ID is currently stored.
+ */
+ DP_HDCP2_TX_IS_KM_STORED_EVENT = 0x20U,
+ /** HDCP FW has pairing data to store. */
+ DP_HDCP2_TX_STORE_KM_EVENT = 0x40U,
+ /** Host needs to check, if Receiver IDs are valid (not on revocation list). */
+ DP_HDCP_TX_IS_RECV_ID_VALID_EVENT = 0x80U
+} DP_Events;
+
+/** HPD - related events. Each value represents one bit and may be set or cleared. */
+typedef enum
+{
+ /** HPD line change to high. */
+ DP_HPD_TO_HIGH = 0x01U,
+ /** HPD line change to low. */
+ DP_HPD_TO_LOW = 0x02U,
+ /** HPD line pulse */
+ DP_HPD_PULSE = 0x04U,
+ /** HPD line current state (high - bit set, low - bit cleared) */
+ DP_HPD_STATE = 0x08U
+} DP_HpdEvents;
+
+/**
+ * Status of last AUX transaction. For meaning of values 0-2, please refer to
+ * DisplayPort specification, "Reply Command Definition".
+ */
+typedef enum
+{
+ DP_AUX_ACK = 0U,
+ DP_AUX_NACK = 1U,
+ DP_AUX_DEFER = 2U,
+ /**
+ * Sink error - Maximum number of bytes (16) was received by AUX, but
+ * there was no STOP condition.
+ */
+ DP_AUX_SINK_ERROR = 3U,
+ /** Firmware returned incorrect value */
+ DP_AUX_UNKNOWN_ERROR = 5U
+} DP_AuxStatus;
+
+/**
+ * Status of last I2C-over-AUX transaction. For meaning of values 0-2,
+ * please refer to DisplayPort specification, "Reply Command Definition".
+ * This value is only relevant, if AUX status of that transaction was
+ * DP_AUX_ACK.
+ */
+typedef enum
+{
+ DP_I2C_ACK = 0U,
+ DP_I2C_NACK = 1U,
+ DP_I2C_DEFER = 2U,
+ /** Firmware returned incorrect value */
+ DP_I2C_UNKNOWN_ERROR = 5U
+} DP_I2cStatus;
+
+typedef enum
+{
+ DP_VIC_MODE_1_59_94HZ = 0U,
+ DP_VIC_MODE_1_60HZ = 1U,
+ DP_VIC_MODE_2_59_94HZ = 2U,
+ DP_VIC_MODE_2_60HZ = 3U,
+ DP_VIC_MODE_3_59_94HZ = 4U,
+ DP_VIC_MODE_3_60HZ = 5U,
+ DP_VIC_MODE_4_59_94HZ = 6U,
+ DP_VIC_MODE_4_60HZ = 7U,
+ DP_VIC_MODE_5_59_94HZ = 8U,
+ DP_VIC_MODE_5_60HZ = 9U,
+ DP_VIC_MODE_6_59_94HZ = 10U,
+ DP_VIC_MODE_6_60HZ = 11U,
+ DP_VIC_MODE_7_59_94HZ = 12U,
+ DP_VIC_MODE_7_60HZ = 13U,
+ DP_VIC_MODE_8_MODE1_59_94HZ = 14U,
+ DP_VIC_MODE_8_MODE1_60HZ = 15U,
+ DP_VIC_MODE_8_MODE2_59_94HZ = 16U,
+ DP_VIC_MODE_8_MODE2_60HZ = 17U,
+ DP_VIC_MODE_9_MODE1_59_94HZ = 18U,
+ DP_VIC_MODE_9_MODE1_60HZ = 19U,
+ DP_VIC_MODE_9_MODE2_59_94HZ = 20U,
+ DP_VIC_MODE_9_MODE2_60HZ = 21U,
+ DP_VIC_MODE_10_59_94HZ = 22U,
+ DP_VIC_MODE_10_60HZ = 23U,
+ DP_VIC_MODE_11_59_94HZ = 24U,
+ DP_VIC_MODE_11_60HZ = 25U,
+ DP_VIC_MODE_12_MODE_1_59_94HZ = 26U,
+ DP_VIC_MODE_12_MODE_1_60HZ = 27U,
+ DP_VIC_MODE_12_MODE_2_59_94HZ = 28U,
+ DP_VIC_MODE_12_MODE_2_60HZ = 29U,
+ DP_VIC_MODE_13_MODE_1_59_94HZ = 30U,
+ DP_VIC_MODE_13_MODE_1_60HZ = 31U,
+ DP_VIC_MODE_13_MODE_2_59_94HZ = 32U,
+ DP_VIC_MODE_13_MODE_2_60HZ = 33U,
+ DP_VIC_MODE_14_59_94HZ = 34U,
+ DP_VIC_MODE_14_60HZ = 35U,
+ DP_VIC_MODE_15_59_94HZ = 36U,
+ DP_VIC_MODE_15_60HZ = 37U,
+ DP_VIC_MODE_16_59_94HZ = 38U,
+ DP_VIC_MODE_16_60HZ = 39U,
+ DP_VIC_MODE_17_50HZ = 40U,
+ DP_VIC_MODE_18_50HZ = 41U,
+ DP_VIC_MODE_19_50HZ = 42U,
+ DP_VIC_MODE_20_50HZ = 43U,
+ DP_VIC_MODE_21_50HZ = 44U,
+ DP_VIC_MODE_22_50HZ = 45U,
+ DP_VIC_MODE_23_MODE_1_50HZ = 46U,
+ DP_VIC_MODE_23_MODE_2_50HZ = 47U,
+ DP_VIC_MODE_23_MODE_3_50HZ = 48U,
+ DP_VIC_MODE_24_MODE_1_50HZ = 49U,
+ DP_VIC_MODE_24_MODE_2_50HZ = 50U,
+ DP_VIC_MODE_24_MODE_3_50HZ = 51U,
+ DP_VIC_MODE_25_50HZ = 52U,
+ DP_VIC_MODE_26_50HZ = 53U,
+ DP_VIC_MODE_27_MODE_1_50HZ = 54U,
+ DP_VIC_MODE_27_MODE_2_50HZ = 55U,
+ DP_VIC_MODE_27_MODE_3_50HZ = 56U,
+ DP_VIC_MODE_28_MODE_1_50HZ = 57U,
+ DP_VIC_MODE_28_MODE_2_50HZ = 58U,
+ DP_VIC_MODE_28_MODE_3_50HZ = 59U,
+ DP_VIC_MODE_29_50HZ = 60U,
+ DP_VIC_MODE_30_50HZ = 61U,
+ DP_VIC_MODE_31_50HZ = 62U,
+ DP_VIC_MODE_32_23_97HZ = 63U,
+ DP_VIC_MODE_32_24HZ = 64U,
+ DP_VIC_MODE_33_25HZ = 65U,
+ DP_VIC_MODE_34_29_97HZ = 66U,
+ DP_VIC_MODE_34_30HZ = 67U,
+ DP_VIC_MODE_35_59_94HZ = 68U,
+ DP_VIC_MODE_35_60HZ = 69U,
+ DP_VIC_MODE_36_59_94HZ = 70U,
+ DP_VIC_MODE_36_60HZ = 71U,
+ DP_VIC_MODE_37_50HZ = 72U,
+ DP_VIC_MODE_38_50HZ = 73U,
+ DP_VIC_MODE_39_50HZ = 74U,
+ DP_VIC_MODE_40_100HZ = 75U,
+ DP_VIC_MODE_41_100HZ = 76U,
+ DP_VIC_MODE_42_100HZ = 77U,
+ DP_VIC_MODE_43_100HZ = 78U,
+ DP_VIC_MODE_44_100HZ = 79U,
+ DP_VIC_MODE_45_100HZ = 80U,
+ DP_VIC_MODE_46_119_88HZ = 81U,
+ DP_VIC_MODE_46_120HZ = 82U,
+ DP_VIC_MODE_47_119_88HZ = 83U,
+ DP_VIC_MODE_47_120HZ = 84U,
+ DP_VIC_MODE_48_119_88HZ = 85U,
+ DP_VIC_MODE_48_120HZ = 86U,
+ DP_VIC_MODE_49_119_88HZ = 87U,
+ DP_VIC_MODE_49_120HZ = 88U,
+ DP_VIC_MODE_50_119_88HZ = 89U,
+ DP_VIC_MODE_50_120HZ = 90U,
+ DP_VIC_MODE_51_119_88HZ = 91U,
+ DP_VIC_MODE_51_120HZ = 92U,
+ DP_VIC_MODE_52_200HZ = 93U,
+ DP_VIC_MODE_53_200HZ = 94U,
+ DP_VIC_MODE_54_200HZ = 95U,
+ DP_VIC_MODE_55_200HZ = 96U,
+ DP_VIC_MODE_56_239HZ = 97U,
+ DP_VIC_MODE_56_240HZ = 98U,
+ DP_VIC_MODE_57_239HZ = 99U,
+ DP_VIC_MODE_57_240HZ = 100U,
+ DP_VIC_MODE_58_239HZ = 101U,
+ DP_VIC_MODE_58_240HZ = 102U,
+ DP_VIC_MODE_59_239HZ = 103U,
+ DP_VIC_MODE_59_240HZ = 104U,
+ DP_VIC_MODE_60_23_97HZ = 105U,
+ DP_VIC_MODE_60_24HZ = 106U,
+ DP_VIC_MODE_61_25HZ = 107U,
+ DP_VIC_MODE_62_29_97HZ = 108U,
+ DP_VIC_MODE_62_30HZ = 109U,
+ DP_VIC_MODE_63_119_88HZ = 110U,
+ DP_VIC_MODE_63_120HZ = 111U,
+ DP_VIC_MODE_64_100HZ = 112U,
+ DP_VIC_MODE_97_60HZ = 113U,
+ DP_VIC_MODE_VESA_800X600P_60HZ = 114U,
+ DP_VIC_MODE_VESA_720X400P_70HZ = 115U,
+ DP_VIC_MODE_VESA_720X400P_88HZ = 116U,
+ DP_VIC_MODE_VESA_640X480P_60HZ = 117U,
+ DP_VIC_MODE_VESA_640X480P_67HZ = 118U,
+ DP_VIC_MODE_VESA_640X480P_72HZ = 119U,
+ DP_VIC_MODE_VESA_640X480P_75HZ = 120U,
+ DP_VIC_MODE_VESA_800X600P_56HZ = 121U,
+ DP_VIC_MODE_VESA_800X600P_72HZ = 122U,
+ DP_VIC_MODE_VESA_832X624P_75HZ = 123U,
+ DP_VIC_MODE_VESA_1024X768I_87HZ = 124U,
+ DP_VIC_MODE_VESA_1024X768P_60HZ = 125U,
+ DP_VIC_MODE_VESA_1024X768P_72HZ = 126U,
+ DP_VIC_MODE_VESA_1024X768P_75HZ = 127U,
+ DP_VIC_MODE_VESA_1280X1024P_75HZ = 128U,
+ DP_VIC_MODE_VESA_1152X870P_75HZ = 129U,
+ DP_VIC_MODE_126_60HZ = 130U,
+ DP_VIC_MODE_DUMMY_1_59_94HZ = 131U,
+ DP_VIC_MODE_DUMMY_2_59_94HZ = 132U,
+ DP_VIC_MODE_DUMMY_4_59_94HZ = 133U,
+ DP_VIC_MODE_DUMMY_14_59_94HZ = 134U,
+ DP_VIC_MODE_DUMMY_16_59_94HZ = 135U,
+ DP_VIC_MODE_DUMMY_17_50HZ = 136U,
+ DP_VIC_MODE_DUMMY_25_50HZ = 137U,
+ DP_VIC_MODE_DUMMY_28_MODE_1_50HZ = 138U,
+ DP_VIC_MODE_DUMMY_31_50HZ = 139U,
+ DP_VIC_MODE_DUMMY_32_23_97HZ = 140U,
+ DP_VIC_MODE_DUMMY_35_59_94HZ = 141U,
+ DP_VIC_MODE_DUMMY_47_119_88HZ = 142U,
+ DP_VIC_MODE_DUMMY_49_119_88HZ = 143U,
+ DP_VIC_MODE_DUMMY_52_200HZ = 144U,
+ DP_VIC_MODE_DUMMY_57_239HZ = 145U,
+ DP_VIC_MODE_DUMMY_58_239HZ = 146U,
+ DP_VIC_MODE_DUMMY_61_25HZ = 147U,
+ DP_VIC_MODE_DUMMY_63_119_88HZ = 148U,
+ DP_VIC_MODE_DUMMY_126_60HZ = 149U,
+ DP_VIC_MODE_COUNT = 150U
+} DP_VicModes;
+
+/** Selecting progressive or interlaced scan mode. */
+typedef enum
+{
+ DP_SM_PROGRESSIVE = 0U,
+ DP_SM_INTERLACED = 1U
+} DP_ScanMode;
+
+/** Selecting synchronization signal polarity */
+typedef enum
+{
+ DP_SP_ACTIVE_LOW = 0U,
+ DP_SP_ACTIVE_HIGH = 1U
+} DP_SyncPolarity;
+
+typedef enum
+{
+ DP_PXENC_PXL_RGB = 0x01U,
+ DP_PXENC_YCBCR_4_4_4 = 0x02U,
+ DP_PXENC_YCBCR_4_2_2 = 0x04U,
+ DP_PXENC_YCBCR_4_2_0 = 0x08U,
+ DP_PXENC_Y_ONLY = 0x10U
+} DP_PixelEncodingFormat;
+
+typedef enum
+{
+ DP_STEREO_VIDEO_LEFT = 0x00U,
+ DP_STEREO_VIDEO_RIGHT = 0x01U
+} DP_StereoVideoAttr;
+
+/**
+ * Only applicable to YCbCr 4:4:4 and 4:2:2 modes. Value to be placed in
+ * MISC0, according to DisplayPort standard. Indicates adherence to
+ * particular colorimetry format.
+ */
+typedef enum
+{
+ /** Video stream uses ITU-R BT.601 colorimetry specification. */
+ DP_BT_601 = 0x00U,
+ /** Video stream uses ITU-R BT.709 colorimetry specification. */
+ DP_BT_709 = 0x01U
+} DP_BtType;
+
+/** Alignment of the input pixel data at the pixel interface. */
+typedef enum
+{
+ /** Pixel data is aligned to most significant bit. (default) */
+ DP_ALIGN_MSB = 0U,
+ /** Pixel data is aligned to least significant bit. */
+ DP_ALIGN_LSB = 1U
+} DP_PxlAlignment;
+
+/** Selecting SDP Active Idle mode. */
+typedef enum
+{
+ /** SDP will be sent during the period when the video is disabled. */
+ DP_SDP_ACTIVE_NO_VIDEO = 0x00U,
+ /**
+ * SDP will be sent during the vertical blank periods in the active video
+ * mode.
+ */
+ DP_SDP_ACTIVE_VIDEO = 0x01U
+} DP_SdpActiveIdleMode;
+
+/** Selecting HDCP version support. */
+typedef enum
+{
+ /** Support only HDCP 2.2 */
+ DP_HDCP_2_SUPPORT = 0x00U,
+ /** Support only HDCP 1.4 */
+ DP_HDCP_1_SUPPORT = 0x01U,
+ /** Support both HDCP versions, trying using HDCP 2.2 first. */
+ DP_HDCP_BOTH_SUPPORT = 0x02U
+} DP_HdcpVerSupport;
+
+/** Selecting Content Stream type, when receiver is a repeater. */
+typedef enum
+{
+ /** Stream may be transmitted to all HDCP devices. */
+ DP_TYPE_0_CONTENT_STREAM = 0x00U,
+ /**
+ * Stream must not be transmitted to HDCP 1.x-compliant devices and HDCP
+ * 2.0-compliant repeaters. This option is incompatible with MST operation.
+ */
+ DP_TYPE_1_CONTENT_STREAM = 0x01U
+} DP_ContentStreamType;
+
+/** HDCP Error codes. */
+typedef enum
+{
+ /** No error occurred. */
+ DP_HDCP_ERR_NO_ERROR = 0x00U,
+ /** HPD is down. */
+ DP_HDCP_ERR_HPD_DOWN = 0x01U,
+ /** SRM failure */
+ DP_HDCP_ERR_SRM_FAIL = 0x02U,
+ /** signature verification error */
+ DP_HDCP_ERR_SIGN_ERROR = 0x03U,
+ /**
+ * (for HDCP 2.x) Hash H', computed by receiver, differs from H computed
+ * by transmitter.
+ */
+ DP_HDCP_ERR_H_HASH_MISMATCH = 0x04U,
+ /**
+ * (for HDCP 1.x) Hash V', computed by receiver, differs from V computed
+ * by transmitter.
+ */
+ DP_HDCP_ERR_V_HASH_MISMATCH = 0x05U,
+ /** (for HDCP 2.x) Locality check failed and could not be retried anymore. */
+ DP_HDCP_ERR_LOCALITY_CHECK_FAIL = 0x06U,
+ /** DDC (AUX channel) error. */
+ DP_HDCP_ERR_DDC_ERROR = 0x07U,
+ /** Re-authentication is required */
+ DP_HDCP_ERR_REAUTH_REQ = 0x08U,
+ /**
+ * Topology error. Exceeded max number of devices (MAX_DEVS_EXCEEDED) or
+ * max repeater cascade depth (MAX_CASCADE_EXCEEDED), or seq_num_V is invalid.
+ */
+ DP_HDCP_ERR_TOPOLOGY_ERROR = 0x09U,
+ /**
+ * Not all reserved (Rsvd) bytes in HDCP port were read as zero, or receiver
+ * is not HDCP-capable.
+ */
+ DP_HDCP_ERR_RSVD_NOT_ZERO = 0x0BU,
+ /** Link synchronization verification values RI differ. */
+ DP_HDCP_ERR_RI_MISMATCH = 0x0DU,
+ /**
+ * Repeater's "KSV List ready" status bit was not set before 5-second
+ * watchdog timer expired.
+ */
+ DP_HDCP_ERR_WATCHDOG_EXPIRED = 0x0EU
+} DP_HdcpErrCode;
+
+/** Audio stream sampling frequency */
+typedef enum
+{
+ /** 32 kHz */
+ DP_AUDIO_FREQ_32 = 0x00U,
+ /** 48 kHz */
+ DP_AUDIO_FREQ_48 = 0x01U,
+ /** 96 kHz */
+ DP_AUDIO_FREQ_96 = 0x02U,
+ /** 192 kHz */
+ DP_AUDIO_FREQ_192 = 0x03U,
+ /** 44.1 kHz */
+ DP_AUDIO_FREQ_44_1 = 0x04U,
+ /** 88.2 kHz */
+ DP_AUDIO_FREQ_88_2 = 0x05U,
+ /** 176.4 kHz */
+ DP_AUDIO_FREQ_176_4 = 0x06U
+} DP_AudioFreq;
+
+/** Audio stream sample size (width) */
+typedef enum
+{
+ /** 16 bits */
+ DP_AUDIO_WIDTH_16 = 0x00U,
+ /** 24 bits */
+ DP_AUDIO_WIDTH_24 = 0x01U,
+ /** 32 bits */
+ DP_AUDIO_WIDTH_32 = 0x02U
+} DP_AudioWidth;
+
+/** Audio enable/disable mode */
+typedef enum
+{
+ /** Disable audio */
+ DP_AUDIO_MODE_OFF = 0x00U,
+ /** Enable audio */
+ DP_AUDIO_MODE_ON = 0x01U
+} DP_AudioMode;
+
+/** Audio mute mode */
+typedef enum
+{
+ /** Mute audio */
+ DP_AUDIO_MUTE = 0x00U,
+ /** Unmute audio */
+ DP_AUDIO_UNMUTE = 0x01U
+} DP_AudioMuteMode;
+
+typedef enum
+{
+ /** 8 bits/component */
+ DP_BITS_PER_COMPONENT_8 = 0U,
+ /** 10 bits/component */
+ DP_BITS_PER_COMPONENT_10 = 1U
+} DP_BitsPerComponent;
+
+/** Status codes used for Link Training process. */
+typedef enum
+{
+ /** Link Training succeeded. */
+ DP_LT_OK = 0U,
+ /** Link Training finished prematurely, due to unexpected or invalid situation. */
+ DP_LT_UNFINISHED = 1U,
+ /** Link Training failed during Clock Recovery phase. */
+ DP_LT_CR_FAIL = 2U,
+ /** Link Training failed during Channel Equalization phase. */
+ DP_LT_EQ_FAIL = 3U
+} DP_TrainingStatus;
+
+typedef enum
+{
+ /** Regular APB bus */
+ DP_BUS_TYPE_APB = 0U,
+ /** Secure APB bus */
+ DP_BUS_TYPE_SAPB = 1U
+} DP_BusType;
+
+typedef enum
+{
+ /** Inject error to IRAM */
+ DP_ECC_ERROR_MEM_TYPE_IRAM = 1U,
+ /** Inject error to DRAM */
+ DP_ECC_ERROR_MEM_TYPE_DRAM = 2U
+} DP_EccErrorMemType;
+
+typedef enum
+{
+ /** Inject error to data bits */
+ DP_ECC_ERROR_TYPE_DATA = 1U,
+ /** Inject error to check bits */
+ DP_ECC_ERROR_TYPE_CHECK = 0U
+} DP_EccErrorType;
+
+/**********************************************************************
+* Callbacks
+**********************************************************************/
+/**
+ * Called on hardware interrupt.
+ * Should call getEvent to check, which event-related bits have been set.
+ */
+typedef void (*DP_CbEvent)(DP_PrivateData* pD);
+
+/**
+ * @}
+ */
+
+/** @defgroup DriverFunctionAPI Driver Function API
+ * Prototypes for the driver API functions. The user application can link statically to the
+ * necessary API functions and call them directly.
+ * @{
+ */
+
+/**********************************************************************
+* API methods
+**********************************************************************/
+
+/**
+ * Get the driver's memory requirements.
+ * @param[in] config Proposed driver/hardware configuration.
+ * @param[out] memReq Size of memory, that needs to be allocated (in bytes).
+ */
+uint32_t DP_Probe(const DP_Config* config, uint32_t* memReq);
+
+/**
+ * brief set up API, must be called before any other API call
+ * @param[in,out] pD Driver state info specific to this instance.
+ * @param[in] config Specifies driver/hardware configuration.
+ * @param[in] callbacks Client-supplied callback functions.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD, config or callbacks is NULL.
+ * @return CDN_ENOTSUP If HW is not supported by this driver.
+ */
+uint32_t DP_Init(DP_PrivateData* pD, const DP_Config* config, const DP_Callbacks* callbacks);
+
+/**
+ * Driver ISR. Platform-specific code is responsible for ensuring this
+ * gets called when the corresponding hardware's interrupt is
+ * asserted. Registering the ISR should be done after calling init,
+ * and before calling start. The driver's ISR will not attempt to lock
+ * any locks, but will perform client callbacks. If the client wishes
+ * to defer processing to non-interrupt time, it is responsible for
+ * doing so. This function must not be called after calling destroy
+ * and releasing private data memory.
+ * @param[in] pD Driver instance data.
+ */
+void DP_Isr(DP_PrivateData* pD);
+
+/**
+ * Start the Display Port Core Driver by enabling interrupts. This is
+ * called after the client has successfully initialized the driver and
+ * hooked the driver's ISR (the isr member of this struct) to the IRQ.
+ * @param[in] pD Driver instance data.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL pD is NULL
+ */
+uint32_t DP_Start(DP_PrivateData* pD);
+
+/**
+ * Stops the Display Port Core Driver by disabling interrupts.
+ * @param[in] pD Driver instance data.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL pD is NULL
+ */
+uint32_t DP_Stop(DP_PrivateData* pD);
+
+/**
+ * Destroy the driver.
+ * @param[in] pD Driver instance data.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL pD is NULL
+ */
+uint32_t DP_Destroy(const DP_PrivateData* pD);
+
+/**
+ * Set address of PHY driver's private data structure.
+ * @param[in] pD Driver instance data.
+ * @param[out] phyPd Pointer to private data of PHY driver's instance to use.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL pD or phyPd is NULL
+ */
+uint32_t DP_SetPhyPd(DP_PrivateData* pD, DP_SD0801_PrivateData* phyPd);
+
+/**
+ * Releases uCPU reset and stalls it, then loads firmware from
+ * provided image.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] image Pointer to structure with FW image information.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If IMEM size or DMEM size is not divisible by 4.
+ */
+uint32_t DP_LoadFirmware(const DP_PrivateData* pD, const DP_FirmwareImage* image);
+
+/**
+ * Starts uCPU. Should be called after loading firmware.
+ * @param[in] pD Driver state info specific to this instance.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD is NULL.
+ */
+uint32_t DP_StartUcpu(const DP_PrivateData* pD);
+
+/**
+ * Check, if there is a response awaiting in mailbox.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] awaits Pointer to store flag indicating presence of response.
+ * @param[in] busType
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If busType is outside enum range.
+ */
+uint32_t DP_CheckResponse(const DP_PrivateData* pD, bool* awaits, DP_BusType busType);
+
+/**
+ * Debug echo command for APB.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] message Value to echo
+ * @param[in] busType
+ * @return CDN_EOK success
+ * @return CDN_EIO reply message doesn't match request
+ * @return CDN_EINVAL If busType is outside enum range.
+ */
+uint32_t DP_TestEcho(DP_PrivateData* pD, uint32_t message, DP_BusType busType);
+
+/**
+ * Extended Echo test for mailbox. This test will send msg buffer to
+ * firmware's mailbox and receive it back to the resp buffer. Received
+ * data will be check against data sent and status will be returned as
+ * well as received data.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] message Pointer to a buffer to send.
+ * @param[out] response Pointer to buffer for receiving msg payload back.
+ * @param[in] messageSize Number of bytes to send and receive.
+ * @param[in] busType
+ * @return CDN_EOK success
+ * @return CDN_EIO reply message's size or content doesn't match request's.
+ * @return CDN_ENOEXEC Wrong Module or Operation ID was received in response form FW.
+ * @return CDN_EINVAL If number of bytes to use is invalid.
+ */
+uint32_t DP_TestEchoExt(DP_PrivateData* pD, const uint8_t* message, uint8_t* response, uint16_t messageSize, DP_BusType busType);
+
+/**
+ * Get current FW version.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] ver fw version
+ * @param[out] verlib lib version
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD or fw/lib version pointer is NULL.
+ */
+uint32_t DP_GetCurVersion(const DP_PrivateData* pD, uint16_t* ver, uint16_t* verlib);
+
+/**
+ * Read event registers (SW_EVENTS) value.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] events pointer to store 32-bit events value
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD or events pointer is NULL.
+ */
+uint32_t DP_GetEvent(const DP_PrivateData* pD, uint32_t* events);
+
+/**
+ * Read debug register value.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] debug pointer to store 16-bit debug reg value
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD or debug pointer is NULL.
+ */
+uint32_t DP_GetDebugRegVal(const DP_PrivateData* pD, uint16_t* debug);
+
+/**
+ * Check, if KEEP_ALIVE register has changed. To check if FW on uCPU
+ * is still running, it is necessary to keep calling this function,
+ * until 'updated' parameter is set to 'true' twice.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] updated Pointer to store flag, whether (true) or not (false) KEEP_ALIVE register
+ * changed since initialization or last call of this function, whichever
+ * happened later.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD or updated pointer is NULL.
+ */
+uint32_t DP_CheckAlive(DP_PrivateData* pD, bool* updated);
+
+/**
+ * Wait, until KEEP_ALIVE register changes. WARNING: If Firmware on
+ * uCPU is not running, this function will block indefinitely.
+ * DP_CheckAlive is a non-blocking equivalent.
+ * @param[in] pD Driver state info specific to this instance.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD is NULL.
+ */
+uint32_t DP_WaitAlive(DP_PrivateData* pD);
+
+/**
+ * Sends request for setting uCPU/FW mode. DP_CheckResponse for
+ * (regular) APB may be used to check, if reply is available.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] mode 1 for active, 0 for standby
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD is NULL.
+ */
+uint32_t DP_SendMainControlRequest(DP_PrivateData* pD, uint8_t mode);
+
+/**
+ * Gets response for setting uCPU/FW mode.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] resp pointer to store response.
+ * @return CDN_EOK success
+ * @return CDN_ENOEXEC Wrong Module or Operation ID was received in response form FW.
+ * @return CDN_EINVAL If pD or resp pointer is NULL.
+ */
+uint32_t DP_GetMainControlResponse(DP_PrivateData* pD, uint8_t* resp);
+
+/**
+ * Set uCPU/FW to standby or active. Await for response.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] mode 1 for active, 0 for standby
+ * @param[out] resp Response: 1 for active, 0 for standby
+ * @return CDN_EOK success
+ * @return CDN_ENOEXEC Wrong Module or Operation ID was received in response form FW.
+ * @return CDN_EINVAL If pD or resp pointer is NULL.
+ */
+uint32_t DP_MainControl(DP_PrivateData* pD, uint8_t mode, uint8_t* resp);
+
+/**
+ * Specify the Xtensa clock. This function shall be called before
+ * turning on the CPU.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] ucpuClock Clock, that Xtensa uCPU is running at.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If clock is outside range (1.0 - 255.99 MHz).
+ */
+uint32_t DP_SetClock(DP_PrivateData* pD, const DP_UcpuClock* ucpuClock);
+
+/**
+ * set maximum and minimum watchdog counters
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] watchdogMin Minimum value of the watchdog counter.
+ * @param[in] watchdogMax Maximum value of the watchdog counter.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD is NULL.
+ */
+uint32_t DP_SetWatchdogConfig(DP_PrivateData* pD, uint32_t watchdogMin, uint32_t watchdogMax);
+
+/**
+ * Inject memory error. Function is used for testing ECC mechanism.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] errorMask It is the bit flip mask for check bits and databits for both IRAM and DRAM.
+ * @param[in] memType Select memory where shall be injected IRAM or DRAM.
+ * @param[in] errorType Select whether error shall be injected either in data bits or in check bits.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD is NULL.
+ */
+uint32_t DP_InjectEccError(DP_PrivateData* pD, uint32_t errorMask, DP_EccErrorMemType memType, DP_EccErrorType errorType);
+
+/**
+ * Force fatal error. Fuction is used to test PFatalError output.
+ * @param[in] pD Driver state info specific to this instance.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD is NULL.
+ */
+uint32_t DP_ForceFatalError(DP_PrivateData* pD);
+
+/**
+ * set audio video clock configuration
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] streamId stream number which should be configured
+ * for SST it should be always 0
+ * for MST proper values are from to DP_MAX_NUMBER_OF_STREAMS - 1
+ * @param[in] audioVideoClkCfg audio video clock configuration to be set
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If streamId is has wrong value
+ */
+uint32_t DP_SetAudioVideoClkCfg(DP_PrivateData* pD, uint8_t streamId, const DP_AudioVideoClkCfg* audioVideoClkCfg);
+
+/**
+ * set audio video clock configuration
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] streamId stream number which should be configured
+ * for SST it should be always 0
+ * for MST proper values are from to DP_MAX_NUMBER_OF_STREAMS - 1
+ * @param[out] audioVideoClkCfg audio video clock configuration to be set
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If streamId is has wrong value
+ */
+uint32_t DP_GetAudioVideoClkCfg(DP_PrivateData* pD, uint8_t streamId, DP_AudioVideoClkCfg* audioVideoClkCfg);
+
+/**
+ * set HDCP clock configuration
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] hdcpClockEnable HDCP clock config
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD is NULL.
+ */
+uint32_t DP_SetHdcpClockConfig(DP_PrivateData* pD, bool hdcpClockEnable);
+
+/**
+ * get HDCP clock configuration
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] hdcpClockEnable HDCP clock config
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD is NULL.
+ */
+uint32_t DP_GetHdcpClockConfig(DP_PrivateData* pD, bool* hdcpClockEnable);
+
+/**
+ * Initialize part of PHY responsible for AUX channel. Has to be
+ * called before performing any DPCD or EDID operations.
+ * Alternatively, respective PHY driver's function may be called
+ * instead.
+ * @param[in] pD Driver state info specific to this instance.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD is NULL.
+ */
+uint32_t DP_ConfigurePhyAuxCtrl(const DP_PrivateData* pD);
+
+/**
+ * Automatically initialize and configure DP Main Link on PHY. Has to
+ * be called before performing Link Training. This is a recommended
+ * way to bring up PHY, instead of manual initialization. AUX channel
+ * still has to be initialized separately. alternatively, respective
+ * PHY driver's function may be called instead.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] laneCount Number of lanes to initialize PHY with.
+ * @param[in] linkRate Link rate to initialize PHY with.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD is NULL or parameters are invalid.
+ */
+uint32_t DP_ConfigurePhyStartUp(DP_PrivateData* pD, uint8_t laneCount, DP_LinkRate linkRate);
+
+/**
+ * Sends request for reading EDID from sink device. DP_checkResponse
+ * for (regular) APB may be used to check, if reply is available.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] segment EDID segment to read.
+ * @param[in] extension EDID extension to read
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD is NULL.
+ */
+uint32_t DP_SendEdidReadRequest(DP_PrivateData* pD, uint8_t segment, uint8_t extension);
+
+/**
+ * Gets response with EDID read from sink device.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] resp Pointer structure to be filled with response.
+ * @return CDN_EOK success
+ * @return CDN_ENOEXEC Wrong Module or Operation ID was received in response form FW.
+ * @return CDN_EIO Size of EDID read was not 128 bytes.
+ * @return CDN_EINVAL If pD or resp pointer is NULL.
+ */
+uint32_t DP_GetEdidReadResponse(DP_PrivateData* pD, DP_ReadEdidResponse* resp);
+
+/**
+ * Reads EDID from sink device.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] segment EDID segment to read.
+ * @param[in] extension EDID extension to read
+ * @param[in] resp Pointer structure to be filled with response.
+ * @return CDN_EOK success
+ * @return CDN_ENOEXEC Wrong Module or Operation ID was received in response form FW.
+ * @return CDN_EIO Size of EDID read was not 128 bytes.
+ * @return CDN_EINVAL If pD or resp pointer is NULL.
+ */
+uint32_t DP_ReadEdid(DP_PrivateData* pD, uint8_t segment, uint8_t extension, DP_ReadEdidResponse* resp);
+
+/**
+ * Set power mode of sink device.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] mode Power mode
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If PwrMode value is outside respective enum.
+ */
+uint32_t DP_SetPowerMode(DP_PrivateData* pD, DP_PwrMode mode);
+
+/**
+ * Sets source capabilities, according to filled
+ * DP_SourceDeviceCapabilities structure, provided by user.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] caps Pointer to structure with source capabilities.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If there are invalid values in capabilities (outside range or enum).
+ */
+uint32_t DP_SetSourceCapabilities(DP_PrivateData* pD, const DP_SourceDeviceCapabilities* caps);
+
+/**
+ * Perform a series of DPCD register reads, used to determine
+ * capabilities of sink device, and get structure with them.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] caps Pointer to structure to be filled with sink capabilities.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD or caps is NULL.
+ */
+uint32_t DP_GetSinkCapabilities(DP_PrivateData* pD, DP_SinkDeviceCapabilities* caps);
+
+/**
+ * Set custom 80-bit pattern to be transmitted for testing. To
+ * transmit that pattern, DP_setTestPattern needs to be called, with
+ * PATTERN_80_BIT as "pattern" argument.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] customPattern Array of 10 bytes (80 bits) to be transmitted as the pattern. Bytes are
+ * to be transmitted in order they're placed in the table ([0] -> [9]).
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD or customPattern is NULL.
+ */
+uint32_t DP_SetCustomPattern(DP_PrivateData * pD, uint8_t customPattern[10]);
+
+/**
+ * Transmit (or stop transmitting) selected test pattern at requested
+ * main link parameters (link rate, lane count, voltage swing, pre-
+ * emphasis). Does not inform sink about transmitted pattern (DPCD
+ * registers 10Bh - 10Eh).
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] pattern Test pattern to be transmitted. Selecting PATTERN_DISABLE will stop
+ * transmitting test pattern.
+ * @param[in] linkParams Pointer to structure containing main link parameters to be used. If
+ * pattern is PATTERN_DISABLE, main link parameters will not be changed.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pattern or any member of linkParams is out of range.
+ */
+uint32_t DP_SetTestPattern(DP_PrivateData* pD, DP_TestPattern pattern, DP_LinkState* linkParams);
+
+/**
+ * Sends request for reading DPCD register(s) from sink device.
+ * DP_checkResponse for (regular) APB may be used to check, if reply
+ * is available.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] request Parameters related to DPCD read operation.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD or request pointer is NULL.
+ */
+uint32_t DP_SendDpcdReadRequest(DP_PrivateData* pD, const DP_DpcdTransfer* request);
+
+/**
+ * Gets response with DPCD register(s) read from sink device.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in,out] transfer Pointer with request structure, to be filled with results from the
+ * response. If, as result of an error, more bytes were read, than were
+ * requested, only as many bytes as were requested will be copied to the
+ * buffer, to avoid overflow.
+ * @return CDN_EOK success
+ * @return CDN_ENOEXEC Wrong Module or Operation ID was received in response form FW.
+ * @return CDN_EIO Address or count of DPCD registers, that were read, does not match request
+ * @return CDN_EINVAL If pD or transfer pointer is NULL.
+ */
+uint32_t DP_GetDpcdReadResponse(DP_PrivateData* pD, DP_DpcdTransfer* transfer);
+
+/**
+ * Reads DPCD register(s) from sink device.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in,out] transfer Pointer with request structure, to be filled with results from the
+ * response. If, as result of an error, more bytes were read, than were
+ * requested, only as many bytes as were requested will be copied to the
+ * buffer, to avoid overflow.
+ * @return CDN_EOK success
+ * @return CDN_ENOEXEC Wrong Module or Operation ID was received in response form FW.
+ * @return CDN_EIO Address or count of DPCD registers, that were read, does not match request
+ * @return CDN_EINVAL If pD or transfer pointer is NULL.
+ */
+uint32_t DP_ReadDpcd(DP_PrivateData* pD, DP_DpcdTransfer* transfer);
+
+/**
+ * Sends request for writing DPCD register(s) to sink device.
+ * DP_checkResponse for (regular) APB may be used to check, if reply
+ * is available.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] request Parameters related to DPCD write operation.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD or request pointer is NULL.
+ */
+uint32_t DP_SendDpcdWriteRequest(DP_PrivateData* pD, const DP_DpcdTransfer* request);
+
+/**
+ * Gets response with DPCD register(s) write operation status.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in,out] transfer Pointer with request structure, to be filled with results from the
+ * response.
+ * @return CDN_EOK success
+ * @return CDN_ENOEXEC Wrong Module or Operation ID was received in response form FW.
+ * @return CDN_EIO Address or count of DPCD registers, that were written, does not match request
+ * @return CDN_EINVAL If pD or transfer pointer is NULL.
+ */
+uint32_t DP_GetDpcdWriteResponse(DP_PrivateData* pD, DP_DpcdTransfer* transfer);
+
+/**
+ * Writes DPCD register(s) to sink device.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in,out] transfer Pointer with request structure, to be filled with results from
+ * response.
+ * @return CDN_EOK success
+ * @return CDN_ENOEXEC Wrong Module or Operation ID was received in response form FW.
+ * @return CDN_EIO Address or count of DPCD registers, that were written, does not match request
+ * @return CDN_EINVAL If pD or transfer pointer is NULL.
+ */
+uint32_t DP_WriteDpcd(DP_PrivateData* pD, DP_DpcdTransfer* transfer);
+
+/**
+ * Sends request for I2C-over-AUX read from given I2C address, using
+ * sink device. DP_checkResponse for (regular) APB may be used to
+ * check, if reply is available.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] request Parameters related to I2C-over-AUX read operation.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD or request pointer is NULL.
+ */
+uint32_t DP_SendI2cReadRequest(DP_PrivateData* pD, const DP_I2cTransfer* request);
+
+/**
+ * Gets response with bytes read over I2C-over-AUX, using sink device.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in,out] transfer Pointer with request structure, to be filled with results from the
+ * response. If, as result of an error, more bytes were read, than were
+ * requested, only as many bytes as were requested will be copied to the
+ * buffer, to avoid overflow.
+ * @return CDN_EOK success
+ * @return CDN_ENOEXEC Wrong Module or Operation ID was received in response form FW.
+ * @return CDN_EIO Address or I2C slave or number of bytes, that were read, does not match request
+ * @return CDN_EINVAL If pD or transfer pointer is NULL.
+ */
+uint32_t DP_GetI2cReadResponse(DP_PrivateData* pD, DP_I2cTransfer* transfer);
+
+/**
+ * Reads bytes over I2C-over-AUX, using sink device.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in,out] transfer Pointer with request structure, to be filled with results from the
+ * response. If, as result of an error, more bytes were read, than were
+ * requested, only as many bytes as were requested will be copied to the
+ * buffer, to avoid overflow.
+ * @return CDN_EOK success
+ * @return CDN_ENOEXEC Wrong Module or Operation ID was received in response form FW.
+ * @return CDN_EIO Address or I2C slave or number of bytes, that were read, does not match request
+ * @return CDN_EINVAL If pD or transfer pointer is NULL.
+ */
+uint32_t DP_I2cRead(DP_PrivateData* pD, DP_I2cTransfer* transfer);
+
+/**
+ * Sends request for I2C-over-AUX write to given I2C address, using
+ * sink device. DP_checkResponse for (regular) APB may be used to
+ * check, if reply is available.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] request Parameters related to I2C-over-AUX write operation.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD or request pointer is NULL.
+ */
+uint32_t DP_SendI2cWriteRequest(DP_PrivateData* pD, const DP_I2cTransfer* request);
+
+/**
+ * Gets response with I2C-over-AUX write operation status.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in,out] transfer Pointer with request structure, to be filled with results from the
+ * response.
+ * @return CDN_EOK success
+ * @return CDN_ENOEXEC Wrong Module or Operation ID was received in response form FW.
+ * @return CDN_EIO Address or I2C slave or number of bytes, that were written, does not match request
+ * @return CDN_EINVAL If pD or transfer pointer is NULL.
+ */
+uint32_t DP_GetI2cWriteResponse(DP_PrivateData* pD, DP_I2cTransfer* transfer);
+
+/**
+ * Writes bytes over I2C-over-AUX, using sink device.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in,out] transfer Pointer with request structure, to be filled with results from
+ * response.
+ * @return CDN_EOK success
+ * @return CDN_ENOEXEC Wrong Module or Operation ID was received in response form FW.
+ * @return CDN_EIO Address or I2C slave or number of bytes, that were written, does not match request
+ * @return CDN_EINVAL If pD or transfer pointer is NULL.
+ */
+uint32_t DP_I2cWrite(DP_PrivateData* pD, DP_I2cTransfer* transfer);
+
+/**
+ * Enables or disables ASSR (Alternate Scrambler Seed Reset) in sink
+ * and source devices, if it's supported by sink.
+ * DP_getSinkCapabilities function may also be used to check, if sink
+ * supports that feature. Standard value of 0xFFFE is used as an
+ * alternate seed.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] enable Whether to enable ('true') or disable ('false') ASSR.
+ * @return CDN_EOK success
+ * @return CDN_ENOEXEC Wrong Module or Operation ID was received in response form FW.
+ * @return CDN_EIO DPCD transaction or register write was unsuccessful.
+ * @return CDN_ENOTSUP Enabling ASSR was requested, but sink device does not support it.
+ * @return CDN_EINVAL If pD is NULL.
+ */
+uint32_t DP_SetAssrEnable(DP_PrivateData* pD, bool enable);
+
+/**
+ * Enables or disables shortening of AUX transaction preamble (sync
+ * pattern) from 16 to 8 pulses (as required by eDP standard). Default
+ * (false) is 16 pulses, as required by regular DisplayPort standard.
+ * It is required, by the eDP standard, to enable shortened preamble.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] enable Whether to shorten ('true') or not ('false') the AUX preamble.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD is NULL.
+ */
+uint32_t DP_SetShortenedAuxPreamble(DP_PrivateData* pD, bool enable);
+
+/**
+ * Performs DisplayPort Link Training, according to capabilities set
+ * via setHostCapabilities and sink capabilities read from DPCD.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] resultLt Result of Link Training process, according to TrainingStatus enum.
+ * @return CDN_EOK success
+ * @return CDN_ENOENT Source device capabilities were not set.
+ * @return CDN_ECANCELED Sink device capabilities are not correct.
+ * @return CDN_EINVAL If pD or result pointer is NULL.
+ */
+uint32_t DP_LinkTraining(DP_PrivateData* pD, DP_TrainingStatus* resultLt);
+
+/**
+ * Checks, if link is stable and synchronized, according to sink
+ * device.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] resultLs Whether ('true') or not link is stable and synchronized.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD or result pointer is NULL.
+ */
+uint32_t DP_CheckLinkStable(DP_PrivateData* pD, bool* resultLs);
+
+/**
+ * Sets mask disabling events.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] mask Event mask (bit '1' at given position disables event).
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD is NULL.
+ */
+uint32_t DP_SetEventMask(DP_PrivateData* pD, uint32_t mask);
+
+/**
+ * Gets mask disabling events.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] mask Event mask (bit '1' at given position disables event).
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD or mask pointer is NULL.
+ * @return CDN_ENOTSUP Operation currently not implemented
+ */
+uint32_t DP_GetEventMask(const DP_PrivateData* pD, const uint32_t* mask);
+
+/**
+ * Sends request for reading events related to HPD from uCPU.
+ * DP_CheckResponse for (regular) APB may be used to check, if reply
+ * is available.
+ * @param[in] pD Driver state info specific to this instance.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD is NULL.
+ */
+uint32_t DP_SendReadHpdEventRequest(DP_PrivateData* pD);
+
+/**
+ * Gets response for reading events related to HPD from uCPU.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] hpdEvents pointer to store response.
+ * @return CDN_EOK success
+ * @return CDN_ENOEXEC Wrong Module or Operation ID was received in response form FW.
+ * @return CDN_EINVAL If pD or hpdEvents pointer is NULL.
+ */
+uint32_t DP_GetReadHpdEventResponse(DP_PrivateData* pD, uint8_t* hpdEvents);
+
+/**
+ * Reads events.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] hpdEvents Set of HPD-related events, as bits defined in DP_HpdEvents enum.
+ * @return CDN_EOK success
+ * @return CDN_ENOEXEC Wrong Module or Operation ID was received in response form FW.
+ * @return CDN_EINVAL If pD or hpdEvents pointer is NULL.
+ */
+uint32_t DP_ReadHpdEvent(DP_PrivateData* pD, uint8_t* hpdEvents);
+
+/**
+ * Fills DP_VideoFormatParams structure, based on entry in VIC
+ * parameters table, as defined in VicModes enum.
+ * @param[out] vicParams Structure with VIC-relared parameters to fill.
+ * @param[in] vicMode VIC mode to take from table and fill into structure.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If vicMode is outside enum range.
+ */
+uint32_t DP_FillVideoFormat(DP_VideoFormatParams* vicParams, DP_VicModes vicMode);
+
+/**
+ * Set vic mode according to vic table, or requested video parameters.
+ * May be called after successful Link Training. If different
+ * synchronization pulse is desired for MSA data, than one present on
+ * the Video Interface (VIF), DP_SetMsaSyncPolarity may be called
+ * after this function.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] streamId ID of stream to be configured. Maximum stream ID is DP_MAX_NUMBER_OF_STREAMS - 1 DSC can be enabled only for stream 0 or 1.
+ * @param[in] parameters Structure with video parameters to set.
+ * @return CDN_EOK success
+ * @return CDN_ENOENT PHY was not initialized and Link Training was not done yet.
+ * @return CDN_EINVAL If incorrect video parameters were detected.
+ */
+uint32_t DP_SetVic(DP_PrivateData* pD, uint8_t streamId, const DP_VideoParameters* parameters);
+
+/**
+ * DP_SetVic function sets the same synchronization pulse polarity for
+ * VIF (Video Interface) input and MSA (Main Steam Attribute). If it
+ * is desired to use different polarity in MSA data, this function may
+ * be called after DP_SetVic to override sync polarity for MSA
+ * (leaving polarity for VIF as DP_SetVic had set it).
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] streamId ID of stream to be configured. Maximum stream ID is DP_MAX_NUMBER_OF_STREAMS - 1
+ * @param[in] hSyncPolarity Horizontal sync pulse polarity to set in MSA.
+ * @param[in] vSyncPolarity Vertical sync pulse polarity to set in MSA.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If there are invalid values in parameters (outside of enum).
+ */
+uint32_t DP_SetMsaSyncPolarity(DP_PrivateData* pD, uint8_t streamId, DP_SyncPolarity hSyncPolarity, DP_SyncPolarity vSyncPolarity);
+
+/**
+ * Turn framer on or off. Enabling framer on is required before
+ * enabling video. Disabling framer is required before performing Link
+ * Training.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] enable Framer enable (true - on, false - off)
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD is NULL.
+ */
+uint32_t DP_SetFramerEnable(DP_PrivateData* pD, bool enable);
+
+/**
+ * Turn video on or off. Applicable to SST mode only. Disabling video
+ * is required before performing Link Training.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] mode Video Mode (true - on, false - off)
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD is NULL.
+ */
+uint32_t DP_SetVideoSst(DP_PrivateData* pD, bool mode);
+
+/**
+ * Get current link status (link rate, lane count, voltage sing level
+ * and pre-emphasis level). Values are valid after successful Link
+ * Training.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] linkState Link State.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD or linkState pointer is NULL.
+ */
+uint32_t DP_ReadLinkStat(DP_PrivateData* pD, DP_LinkState* linkState);
+
+/**
+ * Sends request for reading status of last AUX transaction.
+ * DP_CheckResponse for (regular) APB may be used to check, if reply
+ * is available.
+ * @param[in] pD Driver state info specific to this instance.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD is NULL.
+ */
+uint32_t DP_SendAuxStatusRequest(DP_PrivateData* pD);
+
+/**
+ * Gets response with status of last AUX transaction.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] status Latest AUX status
+ * @return CDN_EOK success
+ * @return CDN_ENOEXEC Wrong Module or Operation ID was received in response form FW.
+ * @return CDN_EINVAL If pD or status pointer is NULL.
+ */
+uint32_t DP_GetAuxStatusResponse(DP_PrivateData* pD, DP_AuxStatus* status);
+
+/**
+ * Reads and returns status of most recent AUX transaction.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] status Latest AUX status
+ * @return CDN_EOK success
+ * @return CDN_ENOEXEC Wrong Module or Operation ID was received in response form FW.
+ * @return CDN_EINVAL If pD or status pointer is NULL.
+ */
+uint32_t DP_GetAuxStatus(DP_PrivateData* pD, DP_AuxStatus* status);
+
+/**
+ * Sends request for reading status of last I2C-over-AUX transaction.
+ * DP_CheckResponse for (regular) APB may be used to check, if reply
+ * is available.
+ * @param[in] pD Driver state info specific to this instance.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD is NULL.
+ */
+uint32_t DP_SendI2cStatusRequest(DP_PrivateData* pD);
+
+/**
+ * Gets response with status of last I2C-over-AUX transaction.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] status Latest I2C-over-AUX status
+ * @return CDN_EOK success
+ * @return CDN_ENOEXEC Wrong Module or Operation ID was received in response form FW.
+ * @return CDN_EINVAL If pD or status pointer is NULL.
+ */
+uint32_t DP_GetI2cStatusResponse(DP_PrivateData* pD, DP_I2cStatus* status);
+
+/**
+ * Reads and returns status of most recent I2C-over-AUX transaction.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] status Latest I2C-over-AUX status
+ * @return CDN_EOK success
+ * @return CDN_ENOEXEC Wrong Module or Operation ID was received in response form FW.
+ * @return CDN_EINVAL If pD or status pointer is NULL.
+ */
+uint32_t DP_GetI2cStatus(DP_PrivateData* pD, DP_I2cStatus* status);
+
+/**
+ * Sends request for reading HPD status. DP_CheckResponse for
+ * (regular) APB may be used to check, if reply is available.
+ * @param[in] pD Driver state info specific to this instance.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD pointer is NULL.
+ */
+uint32_t DP_SendHpdStatusRequest(DP_PrivateData* pD);
+
+/**
+ * Gets response with HPD status.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] status Whether or not HPD is connected and stable.
+ * @return CDN_EOK success
+ * @return CDN_ENOEXEC Wrong Module or Operation ID was received in response form FW.
+ * @return CDN_EINVAL If pD or status pointer is NULL.
+ */
+uint32_t DP_GetHpdStatusResponse(DP_PrivateData* pD, bool* status);
+
+/**
+ * Reads and returns status of HPD.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] status Whether or not HPD is connected and stable.
+ * @return CDN_EOK success
+ * @return CDN_ENOEXEC Wrong Module or Operation ID was received in response form FW.
+ * @return CDN_EINVAL If pD or status pointer is NULL.
+ */
+uint32_t DP_GetHpdStatus(DP_PrivateData* pD, bool* status);
+
+/**
+ * Enables/Disables FEC on DP TX Controller
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] fecEnable informs if FEC should be enabled (true), or disabled (false).
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD is NULL.
+ */
+uint32_t DP_SetFecEnable(DP_PrivateData* pD, bool fecEnable);
+
+/**
+ * Sets/clears FEC_READY bit in DPCD on sink device and in source
+ * registers. Function must be called before link training.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] enable informs if FEC_READY should be set (true), or cleared (false).
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD is NULL.
+ */
+uint32_t DP_SetFecReady(DP_PrivateData* pD, bool enable);
+
+/**
+ * Sets provided SDP under corresponding entry_id into controller. SDP
+ * currently residing under entry_id gets invalidated first.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] streamId ID of stream to be configured. Maximum stream ID is DP_MAX_NUMBER_OF_STREAMS - 1
+ * @param[in] entryID 4 Most significant bits of the packet memory address to write.
+ * @param[in] packetData Data of SDP entry to write
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If streamId is outside range.
+ */
+uint32_t DP_SetSdp(DP_PrivateData* pD, uint8_t streamId, uint8_t entryID, const DP_SdpEntry* packetData);
+
+/**
+ * Invalidates SDP under corresponding entry_id in controller.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] streamId ID of stream to be configured. Maximum stream ID is DP_MAX_NUMBER_OF_STREAMS - 1
+ * @param[in] entryID 4 Most significant bits of the packet memory containing SDP to remove
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If entryId is outside range.
+ */
+uint32_t DP_RemoveSdp(DP_PrivateData* pD, uint8_t streamId, uint8_t entryID);
+
+/**
+ * Set configuration of HDCP transmitter
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] config Pointer to structure with configuration for HDCP transmitter.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD or config pointer is NULL.
+ */
+uint32_t DP_ConfigureHdcpTx(DP_PrivateData* pD, const DP_HdcpTxConfiguration* config);
+
+/**
+ * Set public key for HDCP 2.x transmitter
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] key Pointer to structure with HDCP 2.x public key.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD or key pointer is NULL.
+ */
+uint32_t DP_SetHdcp2TxPublicKey(DP_PrivateData* pD, const DP_Hdcp2TxPublicKey* key);
+
+/**
+ * Set km-key used to decrypt other HDCP keys.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] key Pointer to structure with km-key.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD or key pointer is NULL.
+ */
+uint32_t DP_SetHdcpKmEncCustomKey(DP_PrivateData* pD, const DP_HdcpTxKmEncCustomKey* key);
+
+/**
+ * Set HDCP 2.x random numbers for debug purposes.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] numbers Pointer to structure with random numbers.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD or numbers pointer is NULL.
+ */
+uint32_t DP_SetHdcp2DebugRandom(DP_PrivateData* pD, const DP_HdcpDebugRandomNumbers* numbers);
+
+/**
+ * Send a response to HDCP 2.x engine, that pairing data (including
+ * km) associated with Receiver ID is currently not stored.
+ * @param[in] pD Driver state info specific to this instance.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD is NULL.
+ */
+uint32_t DP_Hdcp2RespondKmNotStored(DP_PrivateData* pD);
+
+/**
+ * Send a response to HDCP 2.x engine containing stored pairing data
+ * (including km) associated with Receiver ID.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] pairingData Pointer to filled structure containing HDCP 2.x pairing data.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD or pairingData pointer is NULL.
+ */
+uint32_t DP_Hdcp2RespondKmStored(DP_PrivateData* pD, const DP_HdcpPairingData* pairingData);
+
+/**
+ * Set private keys for HDCP 1.x transmitter.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] keySet Pointer to filled structure containing HDCP 1.x Device Key Set.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD or keySet pointer is NULL.
+ */
+uint32_t DP_SetHdcp1TxKeys(DP_PrivateData* pD, const DP_Hdcp1Keys* keySet);
+
+/**
+ * Set 'An' random number (for debug only), used in HDCP 1.x
+ * authentication.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] an 8-byte array containing 'An' number.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD or address of 'an' array is NULL.
+ */
+uint32_t DP_SetHdcp1RandomAn(DP_PrivateData* pD, const uint8_t an[8]);
+
+/**
+ * Send request for status of HDCP transmitter. DP_CheckResponse for
+ * (secure) SAPB may be used to check, if reply is available.
+ * @param[in] pD Driver state info specific to this instance.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD is NULL.
+ */
+uint32_t DP_SendHdcpTxStatusRequest(DP_PrivateData* pD);
+
+/**
+ * Get response with status of HDCP transmitter.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] status Pointer to structure with HDCP TX status, to be filled.
+ * @return CDN_EOK success
+ * @return CDN_ENOEXEC Wrong Module or Operation ID was received in response form FW.
+ * @return CDN_EINVAL If pD or status pointer is NULL.
+ */
+uint32_t DP_GetHdcpTxStatusResponse(DP_PrivateData* pD, DP_HdcpTxStatus* status);
+
+/**
+ * Get status of HDCP transmitter. Should be called in response to
+ * HDCP status event.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] status Pointer to structure with HDCP TX status, to be filled.
+ * @return CDN_EOK success
+ * @return CDN_ENOEXEC Wrong Module or Operation ID was received in response form FW.
+ * @return CDN_EINVAL If pD or status pointer is NULL.
+ */
+uint32_t DP_GetHdcpTxStatus(DP_PrivateData* pD, DP_HdcpTxStatus* status);
+
+/**
+ * Send request for Receiver ID, which should looked up in storage, to
+ * get pairing data (if exists in storage). DP_CheckResponse for
+ * (secure) SAPB may be used to check, if reply is available.
+ * @param[in] pD Driver state info specific to this instance.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD is NULL.
+ */
+uint32_t DP_SendHdcp2RecvIdRequest(DP_PrivateData* pD);
+
+/**
+ * Get response with Receiver ID, which should looked up in storage.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] id 5-byte array to be filled with Receiver ID.
+ * @return CDN_EOK success
+ * @return CDN_ENOEXEC Wrong Module or Operation ID was received in response form FW.
+ * @return CDN_EINVAL If pD or address of 'id' array is NULL.
+ */
+uint32_t DP_GetHdcp2RecvIdResponse(DP_PrivateData * pD, uint8_t id[5]);
+
+/**
+ * Get Receiver ID, which should looked up in storage, to get pairing
+ * data (if exists in storage).
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] id 5-byte array to be filled with Receiver ID.
+ * @return CDN_EOK success
+ * @return CDN_ENOEXEC Wrong Module or Operation ID was received in response form FW.
+ * @return CDN_EINVAL If pD or address of 'id' array is NULL.
+ */
+uint32_t DP_GetHdcp2RecvId(DP_PrivateData * pD, uint8_t id[5]);
+
+/**
+ * Send request for pairing data (receiver ID and associated
+ * cryptographic keys and values) of receiver being currently
+ * authenticated. DP_CheckResponse for (secure) SAPB may be used to
+ * check, if reply is available.
+ * @param[in] pD Driver state info specific to this instance.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD is NULL.
+ */
+uint32_t DP_SendHdcp2PairingDataRequest(DP_PrivateData* pD);
+
+/**
+ * Get response with pairing data of receiver being currently
+ * authenticated.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] pairingData Pointer to structure with HDCP pairing data to be filled.
+ * @return CDN_EOK success
+ * @return CDN_ENOEXEC Wrong Module or Operation ID was received in response form FW.
+ * @return CDN_EINVAL If pD or pairingData pointer is NULL.
+ */
+uint32_t DP_GetHdcp2PairingDataResponse(DP_PrivateData* pD, DP_HdcpPairingData* pairingData);
+
+/**
+ * Get pairing data (receiver ID and associated cryptographic keys and
+ * values) of receiver being currently authenticated.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] pairingData Pointer to structure with HDCP pairing data to be filled.
+ * @return CDN_EOK success
+ * @return CDN_ENOEXEC Wrong Module or Operation ID was received in response form FW.
+ * @return CDN_EINVAL If pD or pairingData pointer is NULL.
+ */
+uint32_t DP_GetHdcp2PairingData(DP_PrivateData* pD, DP_HdcpPairingData* pairingData);
+
+/**
+ * Send request for list of all receiver IDs connected directly or via
+ * repeaters, for checking them in revocation list. DP_CheckResponse
+ * for (secure) SAPB may be used to check, if reply is available.
+ * @param[in] pD Driver state info specific to this instance.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD is NULL.
+ */
+uint32_t DP_SendHdcpRecvIdListRequest(DP_PrivateData* pD);
+
+/**
+ * Get response with list of all receiver IDs connected directly or
+ * via repeaters.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] list Pointer to structure with list of all receiver IDs, and their count,
+ * to be filled.
+ * @return CDN_EOK success
+ * @return CDN_ENOEXEC Wrong Module or Operation ID was received in response form FW.
+ * @return CDN_EINVAL If pD or list pointer is NULL.
+ */
+uint32_t DP_GetHdcpRecvIdListResponse(DP_PrivateData* pD, DP_HdcpRecvIdList* list);
+
+/**
+ * Get list of all receiver IDs connected directly or via repeaters,
+ * for checking them in revocation list.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] list Pointer to structure with list of all receiver IDs, and their count,
+ * to be filled.
+ * @return CDN_EOK success
+ * @return CDN_ENOEXEC Wrong Module or Operation ID was received in response form FW.
+ * @return CDN_EINVAL If pD or list pointer is NULL.
+ */
+uint32_t DP_GetHdcpRecvIdList(DP_PrivateData* pD, DP_HdcpRecvIdList* list);
+
+/**
+ * Inform HDCP engine, if all receiver IDs are valid (not present on
+ * the revocation list)
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] valid 'true' - no receiver ID was found on revocation list.
+ * 'false' - at least one receiver was found on revocation list.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD is NULL.
+ */
+uint32_t DP_SetHdcpRecvValid(DP_PrivateData* pD, bool valid);
+
+/**
+ * Set 128-bit Global Constant lc.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] lc128 16-byte array with LC128 value to use. If km-key encryption is enabled,
+ * it is expected to be provided in encrypted form.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD or address of lc128 array is NULL.
+ */
+uint32_t DP_SetHdcp2Lc(DP_PrivateData* pD, const uint8_t lc128[16]);
+
+/**
+ * Set random seed from external TRNG.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] seed 32-byte array with random seed. Number is expected to come from TRNG
+ * and have sufficiently high entropy level.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD or address of seed array is NULL.
+ */
+uint32_t DP_SetHdcpSeed(DP_PrivateData* pD, const uint8_t seed[32]);
+
+/**
+ * Mute or unmute audio.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] streamId ID of stream to be configured. Maximum stream ID is DP_MAX_NUMBER_OF_STREAMS - 1
+ * @param[in] muteMode Select mute/unmute.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If muteMode is outside of enum range.
+ */
+uint32_t DP_AudioSetMute(DP_PrivateData* pD, uint8_t streamId, DP_AudioMuteMode muteMode);
+
+/**
+ * Start playing audio with the given parameters.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] streamId ID of stream to be configured. Maximum stream ID is DP_MAX_NUMBER_OF_STREAMS - 1
+ * @param[in] params Parameters to configure audio with.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If streamId is outside range.
+ */
+uint32_t DP_AudioAutoConfig(DP_PrivateData* pD, uint8_t streamId, const DP_AudioParams* params);
+
+/**
+ * Stop current audio, to allow setting up new one.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] streamId ID of stream to be configured. Maximum stream ID is DP_MAX_NUMBER_OF_STREAMS - 1
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If streamId is outside range.
+ */
+uint32_t DP_AudioStop(DP_PrivateData* pD, uint8_t streamId);
+
+/**
+ * Set audio on or off in internal registers
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] streamId ID of stream to be configured. Maximum stream ID is DP_MAX_NUMBER_OF_STREAMS - 1
+ * @param[in] mode Audio on/off mode.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If mode is outside of enum range.
+ */
+uint32_t DP_AudioSetMode(DP_PrivateData* pD, uint8_t streamId, DP_AudioMode mode);
+
+/**
+ * Set DSC configuration.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] streamId ID of stream to be configured. Maximum stream ID is 1.
+ * @param[in] dscConfig Parameters to configure DSC module
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If streamId is outside range.
+ */
+uint32_t DP_SetDscConfig(DP_PrivateData* pD, uint8_t streamId, const DP_DscConfig* dscConfig);
+
+/**
+ * Get DSC configuration.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] streamId ID of stream to be configured. Maximum stream ID is 1.
+ * @param[out] dscConfig Parameters current DSC configuration
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If streamId is outside range.
+ */
+uint32_t DP_GetDscConfig(DP_PrivateData* pD, uint8_t streamId, DP_DscConfig* dscConfig);
+
+/**
+ * Send PPS packet.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] streamId ID of stream to be configured. Maximum stream ID is 1.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If streamId is outside range.
+ */
+uint32_t DP_DscSendPps(DP_PrivateData* pD, uint8_t streamId);
+
+/**
+ * Function set CompressedStream_Flag in VB_ID register.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] streamId ID of stream to be configured. Maximum stream ID is DP_MAX_NUMBER_OF_STREAMS - 1
+ * @param[in] val Whether or not to set CompressedStreamFlag.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If streamId is outside range.
+ */
+uint32_t DP_SetCompressedStreamFlag(DP_PrivateData* pD, uint8_t streamId, bool val);
+
+/**
+ * Function resets DSC module.
+ * @param[in] pD Driver state info specific to this instance.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL if pD is NULL
+ */
+uint32_t DP_DscReset(DP_PrivateData* pD);
+
+/**
+ * Function enables MST in DP controller and in directly connected
+ * device.
+ * @param[in] pD Driver state info specific to this instance.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL if pD is NULL
+ */
+uint32_t DP_MstEnable(DP_PrivateData* pD);
+
+/**
+ * Function disables MST in DP controller and in directly connected
+ * device
+ * @param[in] pD Driver state info specific to this instance.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL if pD is NULL
+ */
+uint32_t DP_MstDisable(DP_PrivateData* pD);
+
+/**
+ * Function enables stream for MST mode in DP controller.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] streamId ID of stream to be configured. Maximum stream ID is DP_MAX_NUMBER_OF_STREAMS - 1
+ * @return CDN_EOK success
+ * @return CDN_EINVAL if streamID is bigger than DP_MAX_NUMBER_OF_STREAMS - 1
+ * @return CDN_ENOTSUP if MST feature is not enabled
+ */
+uint32_t DP_MstStreamEnable(DP_PrivateData* pD, uint8_t streamId);
+
+/**
+ * Function disables stream for MST mode in DP controller.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] streamId ID of stream to be configured. Maximum stream ID is DP_MAX_NUMBER_OF_STREAMS - 1
+ * @return CDN_EOK success
+ * @return CDN_EINVAL if streamID is bigger than DP_MAX_NUMBER_OF_STREAMS - 1
+ * @return CDN_ENOTSUP if MST feature is not enabled
+ */
+uint32_t DP_MstStreamDisable(DP_PrivateData* pD, uint8_t streamId);
+
+/**
+ * Function calculate payload base on current stream configuration
+ * Next configures controller and sends payload allocate request.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] streamId ID of stream to be configured. Maximum stream ID is DP_MAX_NUMBER_OF_STREAMS - 1
+ * @param[in] sinkDevice Sink device associated with stream
+ * @return CDN_EOK success
+ * @return CDN_EINVAL if streamID is bigger than DP_MAX_NUMBER_OF_STREAMS - 1
+ */
+uint32_t DP_MstAllocateVcpi(DP_PrivateData* pD, uint8_t streamId, DP_SinkDevice* sinkDevice);
+
+/**
+ * Function clear payload for given stream and sink device Next
+ * configures controller and sends payload allocate request.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] streamId ID of stream to be configured. Maximum stream ID is DP_MAX_NUMBER_OF_STREAMS - 1
+ * @param[in] sinkDevice Sink device associated with stream
+ * @return CDN_EOK success
+ * @return CDN_EINVAL if streamID is bigger than DP_MAX_NUMBER_OF_STREAMS - 1
+ */
+uint32_t DP_MstDeallocateVcpi(DP_PrivateData* pD, uint8_t streamId, DP_SinkDevice* sinkDevice);
+
+/**
+ * Get number of connected sink devices for MST mode
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] sinkCount Number of connected sinks
+ * @return CDN_EOK success
+ * @return CDN_EINVAL if cannot count all sink devices
+ */
+uint32_t DP_MstGetSinkCount(DP_PrivateData* pD, uint8_t* sinkCount);
+
+/**
+ * Returns pointers to sink devices according to number returned by
+ * DP_MstGetSinkCount.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] sinkList Array for pointers to sink devices
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD or sinkList pointer is NULL.
+ */
+uint32_t DP_MstGetSinkList(const DP_PrivateData* pD, const DP_SinkDevice** sinkList);
+
+/**
+ * Function used to enable encryption in MST mode. Function should be
+ * called after authentication succeed. Before any payload is
+ * allocated.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] enable 'true' - enable encryption
+ * 'false' - disable encryption
+ * @return CDN_EOK success
+ * @return CDN_EINVAL if pD is NULL
+ */
+uint32_t DP_MstSetEncryptionEnable(DP_PrivateData* pD, bool enable);
+
+/**
+ * Function used to configure encryption for given stream. It enables
+ * or disables encryption for all slots used by given stream.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] streamId ID of stream which encryption is configured. Maximum stream ID is DP_MAX_NUMBER_OF_STREAMS - 1
+ * @param[in] enable 'true' - enable encryption
+ * 'false' - disable encryption
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If no payload allocated for given streamId
+ */
+uint32_t DP_MstSetEncryption(DP_PrivateData* pD, uint8_t streamId, bool enable);
+
+/**
+ * Scan current topology. User can scan topology at initial state.
+ * Scanning is done automatically by DP_MstHpdIrq function always
+ * when something is changed in topology.
+ * @param[in] pD Driver state info specific to this instance.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL if pD is NULL
+ * @return CDN_ENOTSUP if MST is disabled
+ */
+uint32_t DP_MstScanTopology(DP_PrivateData* pD);
+
+/**
+ * Reads EDID from remote sink device using sideband channel.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] sinkDevice sink device from which EDID shall be read
+ * @param[in] block EDID block to read
+ * @param[in] edidResponse Pointer structure to be filled with response
+ * @return CDN_EOK success
+ * @return CDN_EINVAL if any of input parameter has wrong value or is a NULL pointer
+ * @return CDN_EIO if MST is not configured correctly or if an transmission error occurs
+ */
+uint32_t DP_MstReadRemoteEdid(const DP_PrivateData* pD, DP_SinkDevice* sinkDevice, uint32_t block, DP_ReadEdidResponse* edidResponse);
+
+/**
+ * Handle HPD IRQ. It handles incoming sideband messages. It
+ * should be called if MST is enabled and HPD pulse event occurs.
+ * This function must not be called inside interrupt handling routine.
+ * @param[in] pD Driver state info specific to this instance.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL if pD is NULL
+ * @return CDN_EIO if MST is not configured correctly
+ */
+uint32_t DP_MstHpdIrq(DP_PrivateData* pD);
+
+/**
+ * @}
+ */
+
+/* parasoft-end-suppress MISRA2012-RULE-1_1_b_c90-2 */
+/* parasoft-end-suppress MISRA2012-RULE-1_1_a_c90-2 */
+
+#endif /* DP_IF_H */
diff --git a/packages/ti/drv/dss/src/csl/dp/include/dp_mst_if.h b/packages/ti/drv/dss/src/csl/dp/include/dp_mst_if.h
--- /dev/null
@@ -0,0 +1,156 @@
+/**********************************************************************
+* Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* 1. Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* 2. Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the distribution.
+* 3. Neither the name of the copyright holder nor the names of its
+* contributors may be used to endorse or promote products derived from
+* this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+**********************************************************************
+* WARNING: This file is auto-generated using api-generator utility.
+* api-generator: 12.03.9e11b77(origin/DRV-3827_extract_sanity_to_c_file)
+* Do not edit it manually.
+**********************************************************************
+* Cadence Core Driver for the Cadence DisplayPort (DP) core. This header
+* file lists the Supporting structures for the DP core driver
+**********************************************************************/
+
+#ifndef DP_MST_IF_H
+#define DP_MST_IF_H
+
+/* parasoft-begin-suppress MISRA2012-RULE-1_1_a_c90-2 "C90 - limits, DRV-3906" */
+/* parasoft-begin-suppress MISRA2012-RULE-1_1_b_c90-2 "C90 - limits, DRV-3906" */
+
+#include "cdn_errno.h"
+#include "cdn_math.h"
+#include "cdn_stdtypes.h"
+#include "custom_types.h"
+#include "dp_aux_if.h"
+#include "dp_if.h"
+#include "dp_sideband_msg_if.h"
+#include "dp_sideband_msg_structs_if.h"
+
+/** @defgroup ConfigInfo Configuration and Hardware Operation Information
+ * The following definitions specify the driver operation environment that
+ * is defined by hardware configuration or client code. These defines are
+ * located in the header file of the core driver.
+ * @{
+ */
+
+/**********************************************************************
+* Defines
+**********************************************************************/
+#define MST_DPCD_MSTM_CAP 0x021U
+
+#define MST_DPCD_MST_CAP (1U << 0U)
+
+#define MST_DPCD_LINK_BW_SET 0x100U
+
+#define MST_DPCD_LINK_RATE_TABLE 0x00U
+
+#define MST_DPCD_LINK_BW_1_62 0x06U
+
+#define MST_DPCD_LINK_BW_2_7 0x0aU
+
+#define MST_DPCD_LINK_BW_5_4 0x14U
+
+#define MST_DPCD_LINK_BW_8_1 0x1eU
+
+#define MST_DPCD_PAYLOAD_TABLE_UPDATE_STATUS 0x2c0U
+
+#define MST_DPCD_PAYLOAD_TABLE_UPDATED (1U << 0U)
+
+#define MST_DPCD_PAYLOAD_ACT_HANDLED (1U << 1U)
+
+#define MST_DPCD_PAYLOAD_ALLOCATE_SET 0x1c0U
+
+#define MST_DPCD_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1U
+
+#define MST_DPCD_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2U
+
+#define MST_DPCD_RECEIVER_CAP_SIZE 0xfU
+
+#define MST_DPCD_REV 0x000U
+
+#define MST_DPCD_MAX_LANE_COUNT_MASK 0x1fU
+
+#define MST_DPCD_MSTM_CTRL 0x111U
+
+#define MST_DPCD_MST_EN (1U << 0U)
+
+#define MST_DPCD_UP_REQ_EN (1U << 1U)
+
+#define MST_DPCD_UPSTREAM_IS_SRC (1U << 2U)
+
+#define MST_DPCD_FAUX_CAP 0x020U
+
+#define MST_DPCD_BRANCH_OUI 0x500U
+
+#define MST_DPCD_BRANCH_OUI_HEADER_SIZE 0xcU
+
+#define MST_LINK_RATE_MULTIPLIER (54U)
+
+#define MST_BRANCH_MAX_PORTS 16U
+
+#define MST_MAX_PAYLOAD 63U
+
+#define MST_PAYLOAD_LOCAL 1U
+
+#define MST_PAYLOAD_REMOTE 2U
+
+#define MST_PAYLOAD_DELETE_LOCAL 3U
+
+#define MST_MAX_BRANCH_NUMBER 64U
+
+#define MST_MAX_BRANCH_DEEP_LEVEL 15U
+
+#define MST_NUMBER_OF_SDP 16U
+
+/**
+ * @}
+ */
+
+/** @defgroup DataStructure Dynamic Data Structures
+ * This section defines the data structures used by the driver to provide
+ * hardware information, modification and dynamic operation of the driver.
+ * These data structures are defined in the header file of the core driver
+ * and utilized by the API.
+ * @{
+ */
+
+/**********************************************************************
+* Forward declarations
+**********************************************************************/
+typedef struct MST_drm_dp_vcpi_s MST_drm_dp_vcpi;
+typedef struct MST_drm_dp_port_s MST_drm_dp_port;
+typedef struct MST_drm_dp_branch_s MST_drm_dp_branch;
+typedef struct MST_drm_dp_payload_s MST_drm_dp_payload;
+typedef struct MST_demoTb_s MST_demoTb;
+typedef struct MST_drm_dp_topology_mgr_s MST_drm_dp_topology_mgr;
+
+/**
+ * @}
+ */
+
+/* parasoft-end-suppress MISRA2012-RULE-1_1_b_c90-2 */
+/* parasoft-end-suppress MISRA2012-RULE-1_1_a_c90-2 */
+
+#endif /* DP_MST_IF_H */
diff --git a/packages/ti/drv/dss/src/csl/dp/include/dp_mst_obj_if.h b/packages/ti/drv/dss/src/csl/dp/include/dp_mst_obj_if.h
--- /dev/null
@@ -0,0 +1,40 @@
+/**********************************************************************
+* Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* 1. Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* 2. Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the distribution.
+* 3. Neither the name of the copyright holder nor the names of its
+* contributors may be used to endorse or promote products derived from
+* this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+**********************************************************************
+* WARNING: This file is auto-generated using api-generator utility.
+* api-generator: 12.03.9e11b77(origin/DRV-3827_extract_sanity_to_c_file)
+* Do not edit it manually.
+**********************************************************************
+* Cadence Core Driver for the Cadence DisplayPort (DP) core. This header
+* file lists the Supporting structures for the DP core driver
+**********************************************************************/
+#ifndef DP_MST_OBJ_IF_H
+#define DP_MST_OBJ_IF_H
+
+#include "dp_mst_if.h"
+
+#endif /* DP_MST_OBJ_IF_H */
diff --git a/packages/ti/drv/dss/src/csl/dp/include/dp_mst_structs_if.h b/packages/ti/drv/dss/src/csl/dp/include/dp_mst_structs_if.h
--- /dev/null
@@ -0,0 +1,245 @@
+/* parasoft suppress item MISRA2012-DIR-4_8 "Consider hiding implementation of structure" */
+/**********************************************************************
+* Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* 1. Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* 2. Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the distribution.
+* 3. Neither the name of the copyright holder nor the names of its
+* contributors may be used to endorse or promote products derived from
+* this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+**********************************************************************
+* WARNING: This file is auto-generated using api-generator utility.
+* api-generator: 12.03.9e11b77(origin/DRV-3827_extract_sanity_to_c_file)
+* Do not edit it manually.
+**********************************************************************
+* Cadence Core Driver for the Cadence DisplayPort (DP) core. This header
+* file lists the Supporting structures for the DP core driver
+**********************************************************************/
+#ifndef DP_MST_STRUCTS_IF_H
+#define DP_MST_STRUCTS_IF_H
+
+#include "cdn_stdtypes.h"
+#include "dp_mst_if.h"
+
+/** @defgroup DataStructure Dynamic Data Structures
+ * This section defines the data structures used by the driver to provide
+ * hardware information, modification and dynamic operation of the driver.
+ * These data structures are defined in the header file of the core driver
+ * and utilized by the API.
+ * @{
+ */
+
+/**********************************************************************
+* Structures and unions
+**********************************************************************/
+/**
+ * struct DP_drm_dp_vcpi - Virtual Channel Payload Identifier
+ * @vcpi: Virtual channel ID.
+ * @pbn: Payload Bandwidth Number for this channel
+ * @aligned_pbn: PBN aligned with slot size
+ * @num_slots: number of slots for this PBN
+ * @parent: Pointer to port containing this VCPI
+ */
+struct MST_drm_dp_vcpi_s {
+ int32_t vcpi;
+ int32_t pbn;
+ int32_t aligned_pbn;
+ int32_t num_slots;
+ MST_drm_dp_port* parent;
+};
+
+/**
+ * struct DP_drm_dp_port - MST port
+ * @kref: reference count for this port.
+ * @port_num: port number
+ * @input: if this port is an input port.
+ * @mcs: message capability status - DP 1.2 spec.
+ * @ddps: DisplayPort Device Plug Status - DP 1.2
+ * @pdt: Peer Device Type
+ * @ldps: Legacy Device Plug Status
+ * @dpcd_rev: DPCD revision of device on this port
+ * @num_sdp_streams: Number of simultaneous streams
+ * @num_sdp_stream_sinks: Number of stream sinks
+ * @available_pbn: Available bandwidth for this port.
+ * @next: link to next port on this branch device
+ * @mstb: branch device attach below this port
+ * @aux: i2c aux transport to talk to device connected to this port.
+ * @parent: branch device parent of this port
+ * @vcpi: Virtual Channel Payload info for this port.
+ * @connector: DRM connector this port is connected to.
+ * @mgr: topology manager this port lives under.
+ * This structure represents an MST port endpoint on a device somewhere
+ * in the MST topology.
+ */
+struct MST_drm_dp_port_s {
+ uint32_t refcount;
+ uint8_t port_num;
+ bool input;
+ bool mcs;
+ bool ddps;
+ uint8_t pdt;
+ bool ldps;
+ uint8_t dpcd_rev;
+ uint8_t num_sdp_streams;
+ uint8_t num_sdp_stream_sinks;
+ int16_t available_pbn;
+ /** pointer to an mstb if this port has one. */
+ MST_drm_dp_branch* mstb;
+ MST_drm_dp_branch* parent;
+ MST_drm_dp_vcpi vcpi;
+ struct drm_connector* connector;
+ MST_drm_dp_topology_mgr* mgr;
+ /**
+ * @cached_edid: for DP logical ports - make tiling work by ensuring
+ * that the EDID for all connectors is read immediately.
+ */
+ struct edid* cached_edid;
+ /**
+ * @has_audio: Tracks whether the sink connector to this port is
+ * audio-capable.
+ */
+ bool has_audio;
+};
+
+/**
+ * struct DP_drm_dp_branch - MST branch device.
+ * @kref: reference count for this port.
+ * @rad: Relative Address to talk to this branch device.
+ * @lct: Link count total to talk to this branch device.
+ * @num_ports: number of ports on the branch.
+ * @msg_slots: one bit per transmitted msg slot.
+ * @ports: linked list of ports on this branch.
+ * @port_parent: pointer to the port parent, NULL if toplevel.
+ * @mgr: topology manager for this branch device.
+ * @tx_slots: transmission slots for this device.
+ * @last_seqno: last sequence number used to talk to this.
+ * @link_address_sent: if a link address message has been sent to this device yet.
+ * @guid: guid for DP 1.2 branch device. port under this branch can be
+ * identified by port #.
+ * This structure represents an MST branch device, there is one
+ * primary branch device at the root, along with any other branches connected
+ * to downstream port of parent branches.
+ */
+struct MST_drm_dp_branch_s {
+ uint32_t refcount;
+ uint8_t rad[8];
+ uint8_t lct;
+ uint8_t num_ports;
+ int32_t msg_slots;
+ MST_drm_dp_port ports[MST_BRANCH_MAX_PORTS];
+ MST_drm_dp_port* port_parent;
+ MST_drm_dp_topology_mgr* mgr;
+ SBM_drm_dp_sideband_msg_tx* tx_slots[2];
+ int32_t last_seqno;
+ bool link_address_sent;
+ uint8_t guid[16];
+ /** @isOccupied: if memory slot is currently used */
+ bool isOccupied;
+};
+
+struct MST_drm_dp_payload_s {
+ int32_t payload_state;
+ uint8_t start_slot;
+ uint8_t num_slots;
+ int32_t vcpi;
+};
+
+struct MST_demoTb_s {
+ /** Disable sending sideband messages through AUX channel */
+ bool disableMessaging;
+ /** Inject requested number as VCPI */
+ uint8_t requestedVcpi;
+};
+
+/**
+ * struct DP_drm_dp_topology_mgr - DisplayPort MST manager
+ * This struct represents the toplevel displayport MST topology manager.
+ * There should be one instance of this for every MST capable DP connector
+ * on the GPU.
+ */
+struct MST_drm_dp_topology_mgr_s {
+ /** information if incoming communication is handled by interrupt or polling */
+ bool int_enabled;
+ /**
+ * @max_dpcd_transaction_bytes: maximum number of bytes to read/write
+ * in one go.
+ */
+ uint32_t max_dpcd_transaction_bytes;
+ /**
+ * @aux: AUX channel for the DP MST connector this topolgy mgr is
+ * controlling.
+ */
+ struct AUX_drm_dp_s* aux;
+ /**
+ * @down_rep_recv: Message receiver state for down replies. This and
+ * @up_req_recv are only ever access from the work item, which is
+ * serialised.
+ */
+ SBM_drm_dp_sideband_msg_rx down_rep_recv;
+ /**
+ * @up_req_recv: Message receiver state for up requests. This and
+ * @down_rep_recv are only ever access from the work item, which is
+ * serialised.
+ */
+ SBM_drm_dp_sideband_msg_rx up_req_recv;
+ /**
+ * @mst_state: If this manager is enabled for an MST capable port. False
+ * if no MST sink/branch devices is connected.
+ */
+ bool mst_state;
+ /** @mst_primary: Pointer to the primary/first branch device. */
+ MST_drm_dp_branch* mst_primary;
+ /** @branch_list: list of branches */
+ MST_drm_dp_branch branch_list[MST_MAX_BRANCH_NUMBER];
+ /** Cache of DPCD for primary port. */
+ uint8_t dpcd[MST_DPCD_RECEIVER_CAP_SIZE];
+ /** @sink_count: Sink count from DEVICE_SERVICE_IRQ_VECTOR_ESI0. */
+ uint8_t sink_count;
+ /** @pbn_div: PBN to slots divisor. */
+ int32_t pbn_div;
+ /** Number of available, free slots. */
+ int32_t avail_slots;
+ /** Implemented as single element null or message. */
+ SBM_drm_dp_sideband_msg_tx* tx_msg_downq;
+ /**
+ * @proposed_vcpis: Array of pointers for the new VCPI allocation. The
+ * VCPI structure itself is &DP_drm_dp_port.vcpi.
+ */
+ MST_drm_dp_vcpi* proposed_vcpis[MST_MAX_PAYLOAD];
+ /** @payloads: Array of payloads. */
+ MST_drm_dp_payload payloads[MST_MAX_PAYLOAD];
+ /**
+ * @payload_mask: Elements of @payloads actually in use. Since
+ * reallocation of active outputs isn't possible gaps can be created by
+ * disabling outputs out of order compared to how they've been enabled.
+ */
+ uint64_t payload_mask;
+ /** @vcpi_mask: Similar to @payload_mask, but for @proposed_vcpis. */
+ uint64_t vcpi_mask;
+ /** Specifies the target bits */
+ MST_demoTb demotb;
+};
+
+/**
+ * @}
+ */
+
+#endif /* DP_MST_STRUCTS_IF_H */
diff --git a/packages/ti/drv/dss/src/csl/dp/include/dp_obj_if.h b/packages/ti/drv/dss/src/csl/dp/include/dp_obj_if.h
--- /dev/null
@@ -0,0 +1,1381 @@
+/**********************************************************************
+* Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* 1. Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* 2. Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the distribution.
+* 3. Neither the name of the copyright holder nor the names of its
+* contributors may be used to endorse or promote products derived from
+* this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+**********************************************************************
+* WARNING: This file is auto-generated using api-generator utility.
+* api-generator: 12.03.9e11b77(origin/DRV-3827_extract_sanity_to_c_file)
+* Do not edit it manually.
+**********************************************************************
+* Cadence Core Driver for the Cadence DisplayPort (DP) core. This header
+* file lists the API providing a HAL (hardware abstraction layer)
+* interface for the DP core
+**********************************************************************/
+#ifndef DP_OBJ_IF_H
+#define DP_OBJ_IF_H
+
+#include "dp_if.h"
+
+/** @defgroup DriverObject Driver API Object
+ * API listing for the driver. The API is contained in the object as
+ * function pointers in the object structure. As the actual functions
+ * resides in the Driver Object, the client software must first use the
+ * global GetInstance function to obtain the Driver Object Pointer.
+ * The actual APIs then can be invoked using obj->(api_name)() syntax.
+ * These functions are defined in the header file of the core driver
+ * and utilized by the API.
+ * @{
+ */
+
+/**********************************************************************
+* API methods
+**********************************************************************/
+typedef struct DP_OBJ_s
+{
+ /**
+ * Get the driver's memory requirements.
+ * @param[in] config Proposed driver/hardware configuration.
+ * @param[out] memReq Size of memory, that needs to be allocated (in bytes).
+ */
+ uint32_t (*probe)(const DP_Config* config, uint32_t* memReq);
+
+ /**
+ * brief set up API, must be called before any other API call
+ * @param[in,out] pD Driver state info specific to this instance.
+ * @param[in] config Specifies driver/hardware configuration.
+ * @param[in] callbacks Client-supplied callback functions.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD, config or callbacks is NULL.
+ * @return CDN_ENOTSUP If HW is not supported by this driver.
+ */
+ uint32_t (*init)(DP_PrivateData* pD, const DP_Config* config, const DP_Callbacks* callbacks);
+
+ /**
+ * Driver ISR. Platform-specific code is responsible for ensuring
+ * this gets called when the corresponding hardware's interrupt is
+ * asserted. Registering the ISR should be done after calling init,
+ * and before calling start. The driver's ISR will not attempt to
+ * lock any locks, but will perform client callbacks. If the client
+ * wishes to defer processing to non-interrupt time, it is
+ * responsible for doing so. This function must not be called after
+ * calling destroy and releasing private data memory.
+ * @param[in] pD Driver instance data.
+ */
+ void (*isr)(DP_PrivateData* pD);
+
+ /**
+ * Start the Display Port Core Driver by enabling interrupts. This is
+ * called after the client has successfully initialized the driver
+ * and hooked the driver's ISR (the isr member of this struct) to the
+ * IRQ.
+ * @param[in] pD Driver instance data.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL pD is NULL
+ */
+ uint32_t (*start)(DP_PrivateData* pD);
+
+ /**
+ * Stops the Display Port Core Driver by disabling interrupts.
+ * @param[in] pD Driver instance data.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL pD is NULL
+ */
+ uint32_t (*stop)(DP_PrivateData* pD);
+
+ /**
+ * Destroy the driver.
+ * @param[in] pD Driver instance data.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL pD is NULL
+ */
+ uint32_t (*destroy)(const DP_PrivateData* pD);
+
+ /**
+ * Set address of PHY driver's private data structure.
+ * @param[in] pD Driver instance data.
+ * @param[out] phyPd Pointer to private data of PHY driver's instance to use.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL pD or phyPd is NULL
+ */
+ uint32_t (*setPhyPd)(DP_PrivateData* pD, DP_SD0801_PrivateData* phyPd);
+
+ /**
+ * Releases uCPU reset and stalls it, then loads firmware from
+ * provided image.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] image Pointer to structure with FW image information.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If IMEM size or DMEM size is not divisible by 4.
+ */
+ uint32_t (*loadFirmware)(const DP_PrivateData* pD, const DP_FirmwareImage* image);
+
+ /**
+ * Starts uCPU. Should be called after loading firmware.
+ * @param[in] pD Driver state info specific to this instance.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD is NULL.
+ */
+ uint32_t (*startUcpu)(const DP_PrivateData* pD);
+
+ /**
+ * Check, if there is a response awaiting in mailbox.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] awaits Pointer to store flag indicating presence of response.
+ * @param[in] busType
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If busType is outside enum range.
+ */
+ uint32_t (*checkResponse)(const DP_PrivateData* pD, bool* awaits, DP_BusType busType);
+
+ /**
+ * Debug echo command for APB.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] message Value to echo
+ * @param[in] busType
+ * @return CDN_EOK success
+ * @return CDN_EIO reply message doesn't match request
+ * @return CDN_EINVAL If busType is outside enum range.
+ */
+ uint32_t (*testEcho)(DP_PrivateData* pD, uint32_t message, DP_BusType busType);
+
+ /**
+ * Extended Echo test for mailbox. This test will send msg buffer to
+ * firmware's mailbox and receive it back to the resp buffer.
+ * Received data will be check against data sent and status will be
+ * returned as well as received data.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] message Pointer to a buffer to send.
+ * @param[out] response Pointer to buffer for receiving msg payload back.
+ * @param[in] messageSize Number of bytes to send and receive.
+ * @param[in] busType
+ * @return CDN_EOK success
+ * @return CDN_EIO reply message's size or content doesn't match request's.
+ * @return CDN_ENOEXEC Wrong Module or Operation ID was received in response form FW.
+ * @return CDN_EINVAL If number of bytes to use is invalid.
+ */
+ uint32_t (*testEchoExt)(DP_PrivateData* pD, const uint8_t* message, uint8_t* response, uint16_t messageSize, DP_BusType busType);
+
+ /**
+ * Get current FW version.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] ver fw version
+ * @param[out] verlib lib version
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD or fw/lib version pointer is NULL.
+ */
+ uint32_t (*getCurVersion)(const DP_PrivateData* pD, uint16_t* ver, uint16_t* verlib);
+
+ /**
+ * Read event registers (SW_EVENTS) value.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] events pointer to store 32-bit events value
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD or events pointer is NULL.
+ */
+ uint32_t (*getEvent)(const DP_PrivateData* pD, uint32_t* events);
+
+ /**
+ * Read debug register value.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] debug pointer to store 16-bit debug reg value
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD or debug pointer is NULL.
+ */
+ uint32_t (*getDebugRegVal)(const DP_PrivateData* pD, uint16_t* debug);
+
+ /**
+ * Check, if KEEP_ALIVE register has changed. To check if FW on uCPU
+ * is still running, it is necessary to keep calling this function,
+ * until 'updated' parameter is set to 'true' twice.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] updated Pointer to store flag, whether (true) or not (false) KEEP_ALIVE register
+ * changed since initialization or last call of this function, whichever
+ * happened later.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD or updated pointer is NULL.
+ */
+ uint32_t (*checkAlive)(DP_PrivateData* pD, bool* updated);
+
+ /**
+ * Wait, until KEEP_ALIVE register changes. WARNING: If Firmware on
+ * uCPU is not running, this function will block indefinitely.
+ * DP_CheckAlive is a non-blocking equivalent.
+ * @param[in] pD Driver state info specific to this instance.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD is NULL.
+ */
+ uint32_t (*waitAlive)(DP_PrivateData* pD);
+
+ /**
+ * Sends request for setting uCPU/FW mode. DP_CheckResponse for
+ * (regular) APB may be used to check, if reply is available.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] mode 1 for active, 0 for standby
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD is NULL.
+ */
+ uint32_t (*sendMainControlRequest)(DP_PrivateData* pD, uint8_t mode);
+
+ /**
+ * Gets response for setting uCPU/FW mode.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] resp pointer to store response.
+ * @return CDN_EOK success
+ * @return CDN_ENOEXEC Wrong Module or Operation ID was received in response form FW.
+ * @return CDN_EINVAL If pD or resp pointer is NULL.
+ */
+ uint32_t (*getMainControlResponse)(DP_PrivateData* pD, uint8_t* resp);
+
+ /**
+ * Set uCPU/FW to standby or active. Await for response.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] mode 1 for active, 0 for standby
+ * @param[out] resp Response: 1 for active, 0 for standby
+ * @return CDN_EOK success
+ * @return CDN_ENOEXEC Wrong Module or Operation ID was received in response form FW.
+ * @return CDN_EINVAL If pD or resp pointer is NULL.
+ */
+ uint32_t (*mainControl)(DP_PrivateData* pD, uint8_t mode, uint8_t* resp);
+
+ /**
+ * Specify the Xtensa clock. This function shall be called before
+ * turning on the CPU.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] ucpuClock Clock, that Xtensa uCPU is running at.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If clock is outside range (1.0 - 255.99 MHz).
+ */
+ uint32_t (*setClock)(DP_PrivateData* pD, const DP_UcpuClock* ucpuClock);
+
+ /**
+ * set maximum and minimum watchdog counters
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] watchdogMin Minimum value of the watchdog counter.
+ * @param[in] watchdogMax Maximum value of the watchdog counter.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD is NULL.
+ */
+ uint32_t (*setWatchdogConfig)(DP_PrivateData* pD, uint32_t watchdogMin, uint32_t watchdogMax);
+
+ /**
+ * Inject memory error. Function is used for testing ECC mechanism.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] errorMask It is the bit flip mask for check bits and databits for both IRAM and DRAM.
+ * @param[in] memType Select memory where shall be injected IRAM or DRAM.
+ * @param[in] errorType Select whether error shall be injected either in data bits or in check bits.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD is NULL.
+ */
+ uint32_t (*injectEccError)(DP_PrivateData* pD, uint32_t errorMask, DP_EccErrorMemType memType, DP_EccErrorType errorType);
+
+ /**
+ * Force fatal error. Fuction is used to test PFatalError output.
+ * @param[in] pD Driver state info specific to this instance.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD is NULL.
+ */
+ uint32_t (*forceFatalError)(DP_PrivateData* pD);
+
+ /**
+ * set audio video clock configuration
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] streamId stream number which should be configured
+ * for SST it should be always 0
+ * for MST proper values are from to DP_MAX_NUMBER_OF_STREAMS - 1
+ * @param[in] audioVideoClkCfg audio video clock configuration to be set
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If streamId is has wrong value
+ */
+ uint32_t (*setAudioVideoClkCfg)(DP_PrivateData* pD, uint8_t streamId, const DP_AudioVideoClkCfg* audioVideoClkCfg);
+
+ /**
+ * set audio video clock configuration
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] streamId stream number which should be configured
+ * for SST it should be always 0
+ * for MST proper values are from to DP_MAX_NUMBER_OF_STREAMS - 1
+ * @param[out] audioVideoClkCfg audio video clock configuration to be set
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If streamId is has wrong value
+ */
+ uint32_t (*getAudioVideoClkCfg)(DP_PrivateData* pD, uint8_t streamId, DP_AudioVideoClkCfg* audioVideoClkCfg);
+
+ /**
+ * set HDCP clock configuration
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] hdcpClockEnable HDCP clock config
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD is NULL.
+ */
+ uint32_t (*setHdcpClockConfig)(DP_PrivateData* pD, bool hdcpClockEnable);
+
+ /**
+ * get HDCP clock configuration
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] hdcpClockEnable HDCP clock config
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD is NULL.
+ */
+ uint32_t (*getHdcpClockConfig)(DP_PrivateData* pD, bool* hdcpClockEnable);
+
+ /**
+ * Initialize part of PHY responsible for AUX channel. Has to be
+ * called before performing any DPCD or EDID operations.
+ * Alternatively, respective PHY driver's function may be called
+ * instead.
+ * @param[in] pD Driver state info specific to this instance.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD is NULL.
+ */
+ uint32_t (*configurePhyAuxCtrl)(const DP_PrivateData* pD);
+
+ /**
+ * Automatically initialize and configure DP Main Link on PHY. Has to
+ * be called before performing Link Training. This is a recommended
+ * way to bring up PHY, instead of manual initialization. AUX channel
+ * still has to be initialized separately. alternatively, respective
+ * PHY driver's function may be called instead.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] laneCount Number of lanes to initialize PHY with.
+ * @param[in] linkRate Link rate to initialize PHY with.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD is NULL or parameters are invalid.
+ */
+ uint32_t (*configurePhyStartUp)(DP_PrivateData* pD, uint8_t laneCount, DP_LinkRate linkRate);
+
+ /**
+ * Sends request for reading EDID from sink device. DP_checkResponse
+ * for (regular) APB may be used to check, if reply is available.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] segment EDID segment to read.
+ * @param[in] extension EDID extension to read
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD is NULL.
+ */
+ uint32_t (*sendEdidReadRequest)(DP_PrivateData* pD, uint8_t segment, uint8_t extension);
+
+ /**
+ * Gets response with EDID read from sink device.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] resp Pointer structure to be filled with response.
+ * @return CDN_EOK success
+ * @return CDN_ENOEXEC Wrong Module or Operation ID was received in response form FW.
+ * @return CDN_EIO Size of EDID read was not 128 bytes.
+ * @return CDN_EINVAL If pD or resp pointer is NULL.
+ */
+ uint32_t (*getEdidReadResponse)(DP_PrivateData* pD, DP_ReadEdidResponse* resp);
+
+ /**
+ * Reads EDID from sink device.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] segment EDID segment to read.
+ * @param[in] extension EDID extension to read
+ * @param[in] resp Pointer structure to be filled with response.
+ * @return CDN_EOK success
+ * @return CDN_ENOEXEC Wrong Module or Operation ID was received in response form FW.
+ * @return CDN_EIO Size of EDID read was not 128 bytes.
+ * @return CDN_EINVAL If pD or resp pointer is NULL.
+ */
+ uint32_t (*readEdid)(DP_PrivateData* pD, uint8_t segment, uint8_t extension, DP_ReadEdidResponse* resp);
+
+ /**
+ * Set power mode of sink device.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] mode Power mode
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If PwrMode value is outside respective enum.
+ */
+ uint32_t (*setPowerMode)(DP_PrivateData* pD, DP_PwrMode mode);
+
+ /**
+ * Sets source capabilities, according to filled
+ * DP_SourceDeviceCapabilities structure, provided by user.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] caps Pointer to structure with source capabilities.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If there are invalid values in capabilities (outside range or enum).
+ */
+ uint32_t (*setSourceCapabilities)(DP_PrivateData* pD, const DP_SourceDeviceCapabilities* caps);
+
+ /**
+ * Perform a series of DPCD register reads, used to determine
+ * capabilities of sink device, and get structure with them.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] caps Pointer to structure to be filled with sink capabilities.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD or caps is NULL.
+ */
+ uint32_t (*getSinkCapabilities)(DP_PrivateData* pD, DP_SinkDeviceCapabilities* caps);
+
+ /**
+ * Set custom 80-bit pattern to be transmitted for testing. To
+ * transmit that pattern, DP_setTestPattern needs to be called, with
+ * PATTERN_80_BIT as "pattern" argument.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] customPattern Array of 10 bytes (80 bits) to be transmitted as the pattern. Bytes are
+ * to be transmitted in order they're placed in the table ([0] -> [9]).
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD or customPattern is NULL.
+ */
+ uint32_t (*setCustomPattern)(DP_PrivateData* pD, uint8_t customPattern[10]);
+
+ /**
+ * Transmit (or stop transmitting) selected test pattern at requested
+ * main link parameters (link rate, lane count, voltage swing, pre-
+ * emphasis). Does not inform sink about transmitted pattern (DPCD
+ * registers 10Bh - 10Eh).
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] pattern Test pattern to be transmitted. Selecting PATTERN_DISABLE will stop
+ * transmitting test pattern.
+ * @param[in] linkParams Pointer to structure containing main link parameters to be used. If
+ * pattern is PATTERN_DISABLE, main link parameters will not be changed.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pattern or any member of linkParams is out of range.
+ */
+ uint32_t (*setTestPattern)(DP_PrivateData* pD, DP_TestPattern pattern, DP_LinkState* linkParams);
+
+ /**
+ * Sends request for reading DPCD register(s) from sink device.
+ * DP_checkResponse for (regular) APB may be used to check, if reply
+ * is available.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] request Parameters related to DPCD read operation.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD or request pointer is NULL.
+ */
+ uint32_t (*sendDpcdReadRequest)(DP_PrivateData* pD, const DP_DpcdTransfer* request);
+
+ /**
+ * Gets response with DPCD register(s) read from sink device.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in,out] transfer Pointer with request structure, to be filled with results from the
+ * response. If, as result of an error, more bytes were read, than were
+ * requested, only as many bytes as were requested will be copied to the
+ * buffer, to avoid overflow.
+ * @return CDN_EOK success
+ * @return CDN_ENOEXEC Wrong Module or Operation ID was received in response form FW.
+ * @return CDN_EIO Address or count of DPCD registers, that were read, does not match request
+ * @return CDN_EINVAL If pD or transfer pointer is NULL.
+ */
+ uint32_t (*getDpcdReadResponse)(DP_PrivateData* pD, DP_DpcdTransfer* transfer);
+
+ /**
+ * Reads DPCD register(s) from sink device.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in,out] transfer Pointer with request structure, to be filled with results from the
+ * response. If, as result of an error, more bytes were read, than were
+ * requested, only as many bytes as were requested will be copied to the
+ * buffer, to avoid overflow.
+ * @return CDN_EOK success
+ * @return CDN_ENOEXEC Wrong Module or Operation ID was received in response form FW.
+ * @return CDN_EIO Address or count of DPCD registers, that were read, does not match request
+ * @return CDN_EINVAL If pD or transfer pointer is NULL.
+ */
+ uint32_t (*readDpcd)(DP_PrivateData* pD, DP_DpcdTransfer* transfer);
+
+ /**
+ * Sends request for writing DPCD register(s) to sink device.
+ * DP_checkResponse for (regular) APB may be used to check, if reply
+ * is available.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] request Parameters related to DPCD write operation.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD or request pointer is NULL.
+ */
+ uint32_t (*SendDpcdWriteRequest)(DP_PrivateData* pD, const DP_DpcdTransfer* request);
+
+ /**
+ * Gets response with DPCD register(s) write operation status.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in,out] transfer Pointer with request structure, to be filled with results from the
+ * response.
+ * @return CDN_EOK success
+ * @return CDN_ENOEXEC Wrong Module or Operation ID was received in response form FW.
+ * @return CDN_EIO Address or count of DPCD registers, that were written, does not match request
+ * @return CDN_EINVAL If pD or transfer pointer is NULL.
+ */
+ uint32_t (*GetDpcdWriteResponse)(DP_PrivateData* pD, DP_DpcdTransfer* transfer);
+
+ /**
+ * Writes DPCD register(s) to sink device.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in,out] transfer Pointer with request structure, to be filled with results from
+ * response.
+ * @return CDN_EOK success
+ * @return CDN_ENOEXEC Wrong Module or Operation ID was received in response form FW.
+ * @return CDN_EIO Address or count of DPCD registers, that were written, does not match request
+ * @return CDN_EINVAL If pD or transfer pointer is NULL.
+ */
+ uint32_t (*writeDpcd)(DP_PrivateData* pD, DP_DpcdTransfer* transfer);
+
+ /**
+ * Sends request for I2C-over-AUX read from given I2C address, using
+ * sink device. DP_checkResponse for (regular) APB may be used to
+ * check, if reply is available.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] request Parameters related to I2C-over-AUX read operation.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD or request pointer is NULL.
+ */
+ uint32_t (*sendI2cReadRequest)(DP_PrivateData* pD, const DP_I2cTransfer* request);
+
+ /**
+ * Gets response with bytes read over I2C-over-AUX, using sink
+ * device.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in,out] transfer Pointer with request structure, to be filled with results from the
+ * response. If, as result of an error, more bytes were read, than were
+ * requested, only as many bytes as were requested will be copied to the
+ * buffer, to avoid overflow.
+ * @return CDN_EOK success
+ * @return CDN_ENOEXEC Wrong Module or Operation ID was received in response form FW.
+ * @return CDN_EIO Address or I2C slave or number of bytes, that were read, does not match request
+ * @return CDN_EINVAL If pD or transfer pointer is NULL.
+ */
+ uint32_t (*getI2cReadResponse)(DP_PrivateData* pD, DP_I2cTransfer* transfer);
+
+ /**
+ * Reads bytes over I2C-over-AUX, using sink device.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in,out] transfer Pointer with request structure, to be filled with results from the
+ * response. If, as result of an error, more bytes were read, than were
+ * requested, only as many bytes as were requested will be copied to the
+ * buffer, to avoid overflow.
+ * @return CDN_EOK success
+ * @return CDN_ENOEXEC Wrong Module or Operation ID was received in response form FW.
+ * @return CDN_EIO Address or I2C slave or number of bytes, that were read, does not match request
+ * @return CDN_EINVAL If pD or transfer pointer is NULL.
+ */
+ uint32_t (*i2cRead)(DP_PrivateData* pD, DP_I2cTransfer* transfer);
+
+ /**
+ * Sends request for I2C-over-AUX write to given I2C address, using
+ * sink device. DP_checkResponse for (regular) APB may be used to
+ * check, if reply is available.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] request Parameters related to I2C-over-AUX write operation.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD or request pointer is NULL.
+ */
+ uint32_t (*SendI2cWriteRequest)(DP_PrivateData* pD, const DP_I2cTransfer* request);
+
+ /**
+ * Gets response with I2C-over-AUX write operation status.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in,out] transfer Pointer with request structure, to be filled with results from the
+ * response.
+ * @return CDN_EOK success
+ * @return CDN_ENOEXEC Wrong Module or Operation ID was received in response form FW.
+ * @return CDN_EIO Address or I2C slave or number of bytes, that were written, does not match request
+ * @return CDN_EINVAL If pD or transfer pointer is NULL.
+ */
+ uint32_t (*GetI2cWriteResponse)(DP_PrivateData* pD, DP_I2cTransfer* transfer);
+
+ /**
+ * Writes bytes over I2C-over-AUX, using sink device.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in,out] transfer Pointer with request structure, to be filled with results from
+ * response.
+ * @return CDN_EOK success
+ * @return CDN_ENOEXEC Wrong Module or Operation ID was received in response form FW.
+ * @return CDN_EIO Address or I2C slave or number of bytes, that were written, does not match request
+ * @return CDN_EINVAL If pD or transfer pointer is NULL.
+ */
+ uint32_t (*i2cWrite)(DP_PrivateData* pD, DP_I2cTransfer* transfer);
+
+ /**
+ * Enables or disables ASSR (Alternate Scrambler Seed Reset) in sink
+ * and source devices, if it's supported by sink.
+ * DP_getSinkCapabilities function may also be used to check, if sink
+ * supports that feature. Standard value of 0xFFFE is used as an
+ * alternate seed.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] enable Whether to enable ('true') or disable ('false') ASSR.
+ * @return CDN_EOK success
+ * @return CDN_ENOEXEC Wrong Module or Operation ID was received in response form FW.
+ * @return CDN_EIO DPCD transaction or register write was unsuccessful.
+ * @return CDN_ENOTSUP Enabling ASSR was requested, but sink device does not support it.
+ * @return CDN_EINVAL If pD is NULL.
+ */
+ uint32_t (*setAssrEnable)(DP_PrivateData* pD, bool enable);
+
+ /**
+ * Enables or disables shortening of AUX transaction preamble (sync
+ * pattern) from 16 to 8 pulses (as required by eDP standard).
+ * Default (false) is 16 pulses, as required by regular DisplayPort
+ * standard. It is required, by the eDP standard, to enable shortened
+ * preamble.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] enable Whether to shorten ('true') or not ('false') the AUX preamble.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD is NULL.
+ */
+ uint32_t (*setShortenedAuxPreamble)(DP_PrivateData* pD, bool enable);
+
+ /**
+ * Performs DisplayPort Link Training, according to capabilities set
+ * via setHostCapabilities and sink capabilities read from DPCD.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] resultLt Result of Link Training process, according to TrainingStatus enum.
+ * @return CDN_EOK success
+ * @return CDN_ENOENT Source device capabilities were not set.
+ * @return CDN_ECANCELED Sink device capabilities are not correct.
+ * @return CDN_EINVAL If pD or result pointer is NULL.
+ */
+ uint32_t (*linkTraining)(DP_PrivateData* pD, DP_TrainingStatus* resultLt);
+
+ /**
+ * Checks, if link is stable and synchronized, according to sink
+ * device.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] resultLs Whether ('true') or not link is stable and synchronized.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD or result pointer is NULL.
+ */
+ uint32_t (*checkLinkStable)(DP_PrivateData* pD, bool* resultLs);
+
+ /**
+ * Sets mask disabling events.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] mask Event mask (bit '1' at given position disables event).
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD is NULL.
+ */
+ uint32_t (*setEventMask)(DP_PrivateData* pD, uint32_t mask);
+
+ /**
+ * Gets mask disabling events.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] mask Event mask (bit '1' at given position disables event).
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD or mask pointer is NULL.
+ * @return CDN_ENOTSUP Operation currently not implemented
+ */
+ uint32_t (*getEventMask)(const DP_PrivateData* pD, const uint32_t* mask);
+
+ /**
+ * Sends request for reading events related to HPD from uCPU.
+ * DP_CheckResponse for (regular) APB may be used to check, if reply
+ * is available.
+ * @param[in] pD Driver state info specific to this instance.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD is NULL.
+ */
+ uint32_t (*sendReadHpdEventRequest)(DP_PrivateData* pD);
+
+ /**
+ * Gets response for reading events related to HPD from uCPU.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] hpdEvents pointer to store response.
+ * @return CDN_EOK success
+ * @return CDN_ENOEXEC Wrong Module or Operation ID was received in response form FW.
+ * @return CDN_EINVAL If pD or hpdEvents pointer is NULL.
+ */
+ uint32_t (*getReadHpdEventResponse)(DP_PrivateData* pD, uint8_t* hpdEvents);
+
+ /**
+ * Reads events.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] hpdEvents Set of HPD-related events, as bits defined in DP_HpdEvents enum.
+ * @return CDN_EOK success
+ * @return CDN_ENOEXEC Wrong Module or Operation ID was received in response form FW.
+ * @return CDN_EINVAL If pD or hpdEvents pointer is NULL.
+ */
+ uint32_t (*readHpdEvent)(DP_PrivateData* pD, uint8_t* hpdEvents);
+
+ /**
+ * Fills DP_VideoFormatParams structure, based on entry in VIC
+ * parameters table, as defined in VicModes enum.
+ * @param[out] vicParams Structure with VIC-relared parameters to fill.
+ * @param[in] vicMode VIC mode to take from table and fill into structure.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If vicMode is outside enum range.
+ */
+ uint32_t (*fillVideoFormat)(DP_VideoFormatParams* vicParams, DP_VicModes vicMode);
+
+ /**
+ * Set vic mode according to vic table, or requested video
+ * parameters. May be called after successful Link Training. If
+ * different synchronization pulse is desired for MSA data, than one
+ * present on the Video Interface (VIF), DP_SetMsaSyncPolarity may be
+ * called after this function.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] streamId ID of stream to be configured. Maximum stream ID is DP_MAX_NUMBER_OF_STREAMS - 1 DSC can be enabled only for stream 0 or 1.
+ * @param[in] parameters Structure with video parameters to set.
+ * @return CDN_EOK success
+ * @return CDN_ENOENT PHY was not initialized and Link Training was not done yet.
+ * @return CDN_EINVAL If incorrect video parameters were detected.
+ */
+ uint32_t (*setVic)(DP_PrivateData* pD, uint8_t streamId, const DP_VideoParameters* parameters);
+
+ /**
+ * DP_SetVic function sets the same synchronization pulse polarity
+ * for VIF (Video Interface) input and MSA (Main Steam Attribute). If
+ * it is desired to use different polarity in MSA data, this function
+ * may be called after DP_SetVic to override sync polarity for MSA
+ * (leaving polarity for VIF as DP_SetVic had set it).
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] streamId ID of stream to be configured. Maximum stream ID is DP_MAX_NUMBER_OF_STREAMS - 1
+ * @param[in] hSyncPolarity Horizontal sync pulse polarity to set in MSA.
+ * @param[in] vSyncPolarity Vertical sync pulse polarity to set in MSA.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If there are invalid values in parameters (outside of enum).
+ */
+ uint32_t (*setMsaSyncPolarity)(DP_PrivateData* pD, uint8_t streamId, DP_SyncPolarity hSyncPolarity, DP_SyncPolarity vSyncPolarity);
+
+ /**
+ * Turn framer on or off. Enabling framer on is required before
+ * enabling video. Disabling framer is required before performing
+ * Link Training.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] enable Framer enable (true - on, false - off)
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD is NULL.
+ */
+ uint32_t (*setFramerEnable)(DP_PrivateData* pD, bool enable);
+
+ /**
+ * Turn video on or off. Applicable to SST mode only. Disabling video
+ * is required before performing Link Training.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] mode Video Mode (true - on, false - off)
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD is NULL.
+ */
+ uint32_t (*setVideoSst)(DP_PrivateData* pD, bool mode);
+
+ /**
+ * Get current link status (link rate, lane count, voltage sing level
+ * and pre-emphasis level). Values are valid after successful Link
+ * Training.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] linkState Link State.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD or linkState pointer is NULL.
+ */
+ uint32_t (*readLinkStat)(DP_PrivateData* pD, DP_LinkState* linkState);
+
+ /**
+ * Sends request for reading status of last AUX transaction.
+ * DP_CheckResponse for (regular) APB may be used to check, if reply
+ * is available.
+ * @param[in] pD Driver state info specific to this instance.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD is NULL.
+ */
+ uint32_t (*sendAuxStatusRequest)(DP_PrivateData* pD);
+
+ /**
+ * Gets response with status of last AUX transaction.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] status Latest AUX status
+ * @return CDN_EOK success
+ * @return CDN_ENOEXEC Wrong Module or Operation ID was received in response form FW.
+ * @return CDN_EINVAL If pD or status pointer is NULL.
+ */
+ uint32_t (*getAuxStatusResponse)(DP_PrivateData* pD, DP_AuxStatus* status);
+
+ /**
+ * Reads and returns status of most recent AUX transaction.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] status Latest AUX status
+ * @return CDN_EOK success
+ * @return CDN_ENOEXEC Wrong Module or Operation ID was received in response form FW.
+ * @return CDN_EINVAL If pD or status pointer is NULL.
+ */
+ uint32_t (*getAuxStatus)(DP_PrivateData* pD, DP_AuxStatus* status);
+
+ /**
+ * Sends request for reading status of last I2C-over-AUX transaction.
+ * DP_CheckResponse for (regular) APB may be used to check, if reply
+ * is available.
+ * @param[in] pD Driver state info specific to this instance.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD is NULL.
+ */
+ uint32_t (*sendI2cStatusRequest)(DP_PrivateData* pD);
+
+ /**
+ * Gets response with status of last I2C-over-AUX transaction.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] status Latest I2C-over-AUX status
+ * @return CDN_EOK success
+ * @return CDN_ENOEXEC Wrong Module or Operation ID was received in response form FW.
+ * @return CDN_EINVAL If pD or status pointer is NULL.
+ */
+ uint32_t (*getI2cStatusResponse)(DP_PrivateData* pD, DP_I2cStatus* status);
+
+ /**
+ * Reads and returns status of most recent I2C-over-AUX transaction.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] status Latest I2C-over-AUX status
+ * @return CDN_EOK success
+ * @return CDN_ENOEXEC Wrong Module or Operation ID was received in response form FW.
+ * @return CDN_EINVAL If pD or status pointer is NULL.
+ */
+ uint32_t (*getI2cStatus)(DP_PrivateData* pD, DP_I2cStatus* status);
+
+ /**
+ * Sends request for reading HPD status. DP_CheckResponse for
+ * (regular) APB may be used to check, if reply is available.
+ * @param[in] pD Driver state info specific to this instance.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD pointer is NULL.
+ */
+ uint32_t (*sendHpdStatusRequest)(DP_PrivateData* pD);
+
+ /**
+ * Gets response with HPD status.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] status Whether or not HPD is connected and stable.
+ * @return CDN_EOK success
+ * @return CDN_ENOEXEC Wrong Module or Operation ID was received in response form FW.
+ * @return CDN_EINVAL If pD or status pointer is NULL.
+ */
+ uint32_t (*getHpdStatusResponse)(DP_PrivateData* pD, bool* status);
+
+ /**
+ * Reads and returns status of HPD.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] status Whether or not HPD is connected and stable.
+ * @return CDN_EOK success
+ * @return CDN_ENOEXEC Wrong Module or Operation ID was received in response form FW.
+ * @return CDN_EINVAL If pD or status pointer is NULL.
+ */
+ uint32_t (*getHpdStatus)(DP_PrivateData* pD, bool* status);
+
+ /**
+ * Enables/Disables FEC on DP TX Controller
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] fecEnable informs if FEC should be enabled (true), or disabled (false).
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD is NULL.
+ */
+ uint32_t (*setFecEnable)(DP_PrivateData* pD, bool fecEnable);
+
+ /**
+ * Sets/clears FEC_READY bit in DPCD on sink device and in source
+ * registers. Function must be called before link training.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] enable informs if FEC_READY should be set (true), or cleared (false).
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD is NULL.
+ */
+ uint32_t (*setFecReady)(DP_PrivateData* pD, bool enable);
+
+ /**
+ * Sets provided SDP under corresponding entry_id into controller.
+ * SDP currently residing under entry_id gets invalidated first.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] streamId ID of stream to be configured. Maximum stream ID is DP_MAX_NUMBER_OF_STREAMS - 1
+ * @param[in] entryID 4 Most significant bits of the packet memory address to write.
+ * @param[in] packetData Data of SDP entry to write
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If streamId is outside range.
+ */
+ uint32_t (*setSdp)(DP_PrivateData* pD, uint8_t streamId, uint8_t entryID, const DP_SdpEntry* packetData);
+
+ /**
+ * Invalidates SDP under corresponding entry_id in controller.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] streamId ID of stream to be configured. Maximum stream ID is DP_MAX_NUMBER_OF_STREAMS - 1
+ * @param[in] entryID 4 Most significant bits of the packet memory containing SDP to remove
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If entryId is outside range.
+ */
+ uint32_t (*removeSdp)(DP_PrivateData* pD, uint8_t streamId, uint8_t entryID);
+
+ /**
+ * Set configuration of HDCP transmitter
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] config Pointer to structure with configuration for HDCP transmitter.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD or config pointer is NULL.
+ */
+ uint32_t (*configureHdcpTx)(DP_PrivateData* pD, const DP_HdcpTxConfiguration* config);
+
+ /**
+ * Set public key for HDCP 2.x transmitter
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] key Pointer to structure with HDCP 2.x public key.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD or key pointer is NULL.
+ */
+ uint32_t (*setHdcp2TxPublicKey)(DP_PrivateData* pD, const DP_Hdcp2TxPublicKey* key);
+
+ /**
+ * Set km-key used to decrypt other HDCP keys.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] key Pointer to structure with km-key.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD or key pointer is NULL.
+ */
+ uint32_t (*setHdcpKmEncCustomKey)(DP_PrivateData* pD, const DP_HdcpTxKmEncCustomKey* key);
+
+ /**
+ * Set HDCP 2.x random numbers for debug purposes.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] numbers Pointer to structure with random numbers.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD or numbers pointer is NULL.
+ */
+ uint32_t (*setHdcp2DebugRandom)(DP_PrivateData* pD, const DP_HdcpDebugRandomNumbers* numbers);
+
+ /**
+ * Send a response to HDCP 2.x engine, that pairing data (including
+ * km) associated with Receiver ID is currently not stored.
+ * @param[in] pD Driver state info specific to this instance.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD is NULL.
+ */
+ uint32_t (*hdcp2RespondKmNotStored)(DP_PrivateData* pD);
+
+ /**
+ * Send a response to HDCP 2.x engine containing stored pairing data
+ * (including km) associated with Receiver ID.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] pairingData Pointer to filled structure containing HDCP 2.x pairing data.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD or pairingData pointer is NULL.
+ */
+ uint32_t (*hdcp2RespondKmStored)(DP_PrivateData* pD, const DP_HdcpPairingData* pairingData);
+
+ /**
+ * Set private keys for HDCP 1.x transmitter.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] keySet Pointer to filled structure containing HDCP 1.x Device Key Set.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD or keySet pointer is NULL.
+ */
+ uint32_t (*setHdcp1TxKeys)(DP_PrivateData* pD, const DP_Hdcp1Keys* keySet);
+
+ /**
+ * Set 'An' random number (for debug only), used in HDCP 1.x
+ * authentication.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] an 8-byte array containing 'An' number.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD or address of 'an' array is NULL.
+ */
+ uint32_t (*setHdcp1RandomAn)(DP_PrivateData* pD, const uint8_t an[8]);
+
+ /**
+ * Send request for status of HDCP transmitter. DP_CheckResponse for
+ * (secure) SAPB may be used to check, if reply is available.
+ * @param[in] pD Driver state info specific to this instance.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD is NULL.
+ */
+ uint32_t (*sendHdcpTxStatusRequest)(DP_PrivateData* pD);
+
+ /**
+ * Get response with status of HDCP transmitter.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] status Pointer to structure with HDCP TX status, to be filled.
+ * @return CDN_EOK success
+ * @return CDN_ENOEXEC Wrong Module or Operation ID was received in response form FW.
+ * @return CDN_EINVAL If pD or status pointer is NULL.
+ */
+ uint32_t (*getHdcpTxStatusResponse)(DP_PrivateData* pD, DP_HdcpTxStatus* status);
+
+ /**
+ * Get status of HDCP transmitter. Should be called in response to
+ * HDCP status event.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] status Pointer to structure with HDCP TX status, to be filled.
+ * @return CDN_EOK success
+ * @return CDN_ENOEXEC Wrong Module or Operation ID was received in response form FW.
+ * @return CDN_EINVAL If pD or status pointer is NULL.
+ */
+ uint32_t (*getHdcpTxStatus)(DP_PrivateData* pD, DP_HdcpTxStatus* status);
+
+ /**
+ * Send request for Receiver ID, which should looked up in storage,
+ * to get pairing data (if exists in storage). DP_CheckResponse for
+ * (secure) SAPB may be used to check, if reply is available.
+ * @param[in] pD Driver state info specific to this instance.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD is NULL.
+ */
+ uint32_t (*sendHdcp2RecvIdRequest)(DP_PrivateData* pD);
+
+ /**
+ * Get response with Receiver ID, which should looked up in storage.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] id 5-byte array to be filled with Receiver ID.
+ * @return CDN_EOK success
+ * @return CDN_ENOEXEC Wrong Module or Operation ID was received in response form FW.
+ * @return CDN_EINVAL If pD or address of 'id' array is NULL.
+ */
+ uint32_t (*getHdcp2RecvIdResponse)(DP_PrivateData* pD, uint8_t id[5]);
+
+ /**
+ * Get Receiver ID, which should looked up in storage, to get pairing
+ * data (if exists in storage).
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] id 5-byte array to be filled with Receiver ID.
+ * @return CDN_EOK success
+ * @return CDN_ENOEXEC Wrong Module or Operation ID was received in response form FW.
+ * @return CDN_EINVAL If pD or address of 'id' array is NULL.
+ */
+ uint32_t (*getHdcp2RecvId)(DP_PrivateData* pD, uint8_t id[5]);
+
+ /**
+ * Send request for pairing data (receiver ID and associated
+ * cryptographic keys and values) of receiver being currently
+ * authenticated. DP_CheckResponse for (secure) SAPB may be used to
+ * check, if reply is available.
+ * @param[in] pD Driver state info specific to this instance.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD is NULL.
+ */
+ uint32_t (*sendHdcp2PairingDataRequest)(DP_PrivateData* pD);
+
+ /**
+ * Get response with pairing data of receiver being currently
+ * authenticated.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] pairingData Pointer to structure with HDCP pairing data to be filled.
+ * @return CDN_EOK success
+ * @return CDN_ENOEXEC Wrong Module or Operation ID was received in response form FW.
+ * @return CDN_EINVAL If pD or pairingData pointer is NULL.
+ */
+ uint32_t (*getHdcp2PairingDataResponse)(DP_PrivateData* pD, DP_HdcpPairingData* pairingData);
+
+ /**
+ * Get pairing data (receiver ID and associated cryptographic keys
+ * and values) of receiver being currently authenticated.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] pairingData Pointer to structure with HDCP pairing data to be filled.
+ * @return CDN_EOK success
+ * @return CDN_ENOEXEC Wrong Module or Operation ID was received in response form FW.
+ * @return CDN_EINVAL If pD or pairingData pointer is NULL.
+ */
+ uint32_t (*getHdcp2PairingData)(DP_PrivateData* pD, DP_HdcpPairingData* pairingData);
+
+ /**
+ * Send request for list of all receiver IDs connected directly or
+ * via repeaters, for checking them in revocation list.
+ * DP_CheckResponse for (secure) SAPB may be used to check, if reply
+ * is available.
+ * @param[in] pD Driver state info specific to this instance.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD is NULL.
+ */
+ uint32_t (*sendHdcpRecvIdListRequest)(DP_PrivateData* pD);
+
+ /**
+ * Get response with list of all receiver IDs connected directly or
+ * via repeaters.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] list Pointer to structure with list of all receiver IDs, and their count,
+ * to be filled.
+ * @return CDN_EOK success
+ * @return CDN_ENOEXEC Wrong Module or Operation ID was received in response form FW.
+ * @return CDN_EINVAL If pD or list pointer is NULL.
+ */
+ uint32_t (*getHdcpRecvIdListResponse)(DP_PrivateData* pD, DP_HdcpRecvIdList* list);
+
+ /**
+ * Get list of all receiver IDs connected directly or via repeaters,
+ * for checking them in revocation list.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] list Pointer to structure with list of all receiver IDs, and their count,
+ * to be filled.
+ * @return CDN_EOK success
+ * @return CDN_ENOEXEC Wrong Module or Operation ID was received in response form FW.
+ * @return CDN_EINVAL If pD or list pointer is NULL.
+ */
+ uint32_t (*getHdcpRecvIdList)(DP_PrivateData* pD, DP_HdcpRecvIdList* list);
+
+ /**
+ * Inform HDCP engine, if all receiver IDs are valid (not present on
+ * the revocation list)
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] valid 'true' - no receiver ID was found on revocation list.
+ * 'false' - at least one receiver was found on revocation list.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD is NULL.
+ */
+ uint32_t (*setHdcpRecvValid)(DP_PrivateData* pD, bool valid);
+
+ /**
+ * Set 128-bit Global Constant lc.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] lc128 16-byte array with LC128 value to use. If km-key encryption is enabled,
+ * it is expected to be provided in encrypted form.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD or address of lc128 array is NULL.
+ */
+ uint32_t (*setHdcp2Lc)(DP_PrivateData* pD, const uint8_t lc128[16]);
+
+ /**
+ * Set random seed from external TRNG.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] seed 32-byte array with random seed. Number is expected to come from TRNG
+ * and have sufficiently high entropy level.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD or address of seed array is NULL.
+ */
+ uint32_t (*setHdcpSeed)(DP_PrivateData* pD, const uint8_t seed[32]);
+
+ /**
+ * Mute or unmute audio.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] streamId ID of stream to be configured. Maximum stream ID is DP_MAX_NUMBER_OF_STREAMS - 1
+ * @param[in] muteMode Select mute/unmute.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If muteMode is outside of enum range.
+ */
+ uint32_t (*audioSetMute)(DP_PrivateData* pD, uint8_t streamId, DP_AudioMuteMode muteMode);
+
+ /**
+ * Start playing audio with the given parameters.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] streamId ID of stream to be configured. Maximum stream ID is DP_MAX_NUMBER_OF_STREAMS - 1
+ * @param[in] params Parameters to configure audio with.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If streamId is outside range.
+ */
+ uint32_t (*audioAutoConfig)(DP_PrivateData* pD, uint8_t streamId, const DP_AudioParams* params);
+
+ /**
+ * Stop current audio, to allow setting up new one.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] streamId ID of stream to be configured. Maximum stream ID is DP_MAX_NUMBER_OF_STREAMS - 1
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If streamId is outside range.
+ */
+ uint32_t (*audioStop)(DP_PrivateData* pD, uint8_t streamId);
+
+ /**
+ * Set audio on or off in internal registers
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] streamId ID of stream to be configured. Maximum stream ID is DP_MAX_NUMBER_OF_STREAMS - 1
+ * @param[in] mode Audio on/off mode.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If mode is outside of enum range.
+ */
+ uint32_t (*audioSetMode)(DP_PrivateData* pD, uint8_t streamId, DP_AudioMode mode);
+
+ /**
+ * Set DSC configuration.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] streamId ID of stream to be configured. Maximum stream ID is 1.
+ * @param[in] dscConfig Parameters to configure DSC module
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If streamId is outside range.
+ */
+ uint32_t (*setDscConfig)(DP_PrivateData* pD, uint8_t streamId, const DP_DscConfig* dscConfig);
+
+ /**
+ * Get DSC configuration.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] streamId ID of stream to be configured. Maximum stream ID is 1.
+ * @param[out] dscConfig Parameters current DSC configuration
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If streamId is outside range.
+ */
+ uint32_t (*getDscConfig)(DP_PrivateData* pD, uint8_t streamId, DP_DscConfig* dscConfig);
+
+ /**
+ * Send PPS packet.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] streamId ID of stream to be configured. Maximum stream ID is 1.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If streamId is outside range.
+ */
+ uint32_t (*dscSendPps)(DP_PrivateData* pD, uint8_t streamId);
+
+ /**
+ * Function set CompressedStream_Flag in VB_ID register.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] streamId ID of stream to be configured. Maximum stream ID is DP_MAX_NUMBER_OF_STREAMS - 1
+ * @param[in] val Whether or not to set CompressedStreamFlag.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If streamId is outside range.
+ */
+ uint32_t (*setCompressedStreamFlag)(DP_PrivateData* pD, uint8_t streamId, bool val);
+
+ /**
+ * Function resets DSC module.
+ * @param[in] pD Driver state info specific to this instance.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL if pD is NULL
+ */
+ uint32_t (*dscReset)(DP_PrivateData* pD);
+
+ /**
+ * Function enables MST in DP controller and in directly connected
+ * device.
+ * @param[in] pD Driver state info specific to this instance.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL if pD is NULL
+ */
+ uint32_t (*MstEnable)(DP_PrivateData* pD);
+
+ /**
+ * Function disables MST in DP controller and in directly connected
+ * device
+ * @param[in] pD Driver state info specific to this instance.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL if pD is NULL
+ */
+ uint32_t (*MstDisable)(DP_PrivateData* pD);
+
+ /**
+ * Function enables stream for MST mode in DP controller.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] streamId ID of stream to be configured. Maximum stream ID is DP_MAX_NUMBER_OF_STREAMS - 1
+ * @return CDN_EOK success
+ * @return CDN_EINVAL if streamID is bigger than DP_MAX_NUMBER_OF_STREAMS - 1
+ * @return CDN_ENOTSUP if MST feature is not enabled
+ */
+ uint32_t (*MstStreamEnable)(DP_PrivateData* pD, uint8_t streamId);
+
+ /**
+ * Function disables stream for MST mode in DP controller.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] streamId ID of stream to be configured. Maximum stream ID is DP_MAX_NUMBER_OF_STREAMS - 1
+ * @return CDN_EOK success
+ * @return CDN_EINVAL if streamID is bigger than DP_MAX_NUMBER_OF_STREAMS - 1
+ * @return CDN_ENOTSUP if MST feature is not enabled
+ */
+ uint32_t (*MstStreamDisable)(DP_PrivateData* pD, uint8_t streamId);
+
+ /**
+ * Function calculate payload base on current stream configuration
+ * Next configures controller and sends payload allocate request.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] streamId ID of stream to be configured. Maximum stream ID is DP_MAX_NUMBER_OF_STREAMS - 1
+ * @param[in] sinkDevice Sink device associated with stream
+ * @return CDN_EOK success
+ * @return CDN_EINVAL if streamID is bigger than DP_MAX_NUMBER_OF_STREAMS - 1
+ */
+ uint32_t (*MstAllocateVcpi)(DP_PrivateData* pD, uint8_t streamId, DP_SinkDevice* sinkDevice);
+
+ /**
+ * Function clear payload for given stream and sink device Next
+ * configures controller and sends payload allocate request.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] streamId ID of stream to be configured. Maximum stream ID is DP_MAX_NUMBER_OF_STREAMS - 1
+ * @param[in] sinkDevice Sink device associated with stream
+ * @return CDN_EOK success
+ * @return CDN_EINVAL if streamID is bigger than DP_MAX_NUMBER_OF_STREAMS - 1
+ */
+ uint32_t (*MstDeallocateVcpi)(DP_PrivateData* pD, uint8_t streamId, DP_SinkDevice* sinkDevice);
+
+ /**
+ * Get number of connected sink devices for MST mode
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] sinkCount Number of connected sinks
+ * @return CDN_EOK success
+ * @return CDN_EINVAL if cannot count all sink devices
+ */
+ uint32_t (*MstGetSinkCount)(DP_PrivateData* pD, uint8_t* sinkCount);
+
+ /**
+ * Returns pointers to sink devices according to number returned by
+ * DP_MstGetSinkCount.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] sinkList Array for pointers to sink devices
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD or sinkList pointer is NULL.
+ */
+ uint32_t (*MstGetSinkList)(const DP_PrivateData* pD, const DP_SinkDevice** sinkList);
+
+ /**
+ * Function used to enable encryption in MST mode. Function should be
+ * called after authentication succeed. Before any payload is
+ * allocated.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] enable 'true' - enable encryption
+ * 'false' - disable encryption
+ * @return CDN_EOK success
+ * @return CDN_EINVAL if pD is NULL
+ */
+ uint32_t (*MstSetEncryptionEnable)(DP_PrivateData* pD, bool enable);
+
+ /**
+ * Function used to configure encryption for given stream. It enables
+ * or disables encryption for all slots used by given stream.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] streamId ID of stream which encryption is configured. Maximum stream ID is DP_MAX_NUMBER_OF_STREAMS - 1
+ * @param[in] enable 'true' - enable encryption
+ * 'false' - disable encryption
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If no payload allocated for given streamId
+ */
+ uint32_t (*MstSetEncryption)(DP_PrivateData* pD, uint8_t streamId, bool enable);
+
+ /**
+ * Scan current topology. User can scan topology at initial state.
+ * Scanning is done automatically by DP_MstHpdIrq function always
+ * when something is changed in topology.
+ * @param[in] pD Driver state info specific to this instance.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL if pD is NULL
+ * @return CDN_ENOTSUP if MST is disabled
+ */
+ uint32_t (*MstScanTopology)(DP_PrivateData* pD);
+
+ /**
+ * Reads EDID from remote sink device using sideband channel.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] sinkDevice sink device from which EDID shall be read
+ * @param[in] block EDID block to read
+ * @param[in] edidResponse Pointer structure to be filled with response
+ * @return CDN_EOK success
+ * @return CDN_EINVAL if any of input parameter has wrong value or is a NULL pointer
+ * @return CDN_EIO if MST is not configured correctly or if an transmission error occurs
+ */
+ uint32_t (*MstReadRemoteEdid)(const DP_PrivateData* pD, DP_SinkDevice* sinkDevice, uint32_t block, DP_ReadEdidResponse* edidResponse);
+
+ /**
+ * Handle HPD IRQ. It handles incoming sideband messages. It
+ * should be called if MST is enabled and HPD pulse event occurs.
+ * This function must not be called inside interrupt handling
+ * routine.
+ * @param[in] pD Driver state info specific to this instance.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL if pD is NULL
+ * @return CDN_EIO if MST is not configured correctly
+ */
+ uint32_t (*MstHpdIrq)(DP_PrivateData* pD);
+
+} DP_OBJ;
+
+/**
+ * In order to access the DP APIs, the upper layer software must call
+ * this global function to obtain the pointer to the driver object.
+ * @return DP_OBJ* Driver Object Pointer
+ */
+extern DP_OBJ *DP_GetInstance(void);
+
+/**
+ * @}
+ */
+
+#endif /* DP_OBJ_IF_H */
diff --git a/packages/ti/drv/dss/src/csl/dp/include/dp_sideband_msg_if.h b/packages/ti/drv/dss/src/csl/dp/include/dp_sideband_msg_if.h
--- /dev/null
@@ -0,0 +1,112 @@
+/**********************************************************************
+* Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* 1. Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* 2. Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the distribution.
+* 3. Neither the name of the copyright holder nor the names of its
+* contributors may be used to endorse or promote products derived from
+* this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+**********************************************************************
+* WARNING: This file is auto-generated using api-generator utility.
+* api-generator: 12.03.9e11b77(origin/DRV-3827_extract_sanity_to_c_file)
+* Do not edit it manually.
+**********************************************************************
+* Cadence Core Driver for the Cadence DisplayPort (DP) core. This header
+* file lists the Supporting structures for the DP core driver
+**********************************************************************/
+
+#ifndef DP_SIDEBAND_MSG_IF_H
+#define DP_SIDEBAND_MSG_IF_H
+
+/* parasoft-begin-suppress MISRA2012-RULE-1_1_a_c90-2 "C90 - limits, DRV-3906" */
+/* parasoft-begin-suppress MISRA2012-RULE-1_1_b_c90-2 "C90 - limits, DRV-3906" */
+
+#include "cdn_stdtypes.h"
+#include "custom_types.h"
+
+/** @defgroup ConfigInfo Configuration and Hardware Operation Information
+ * The following definitions specify the driver operation environment that
+ * is defined by hardware configuration or client code. These defines are
+ * located in the header file of the core driver.
+ * @{
+ */
+
+/**********************************************************************
+* Defines
+**********************************************************************/
+/** Maximum number of I2C Transactions */
+#define SBM_DP_REMOTE_I2C_READ_MAX_TRANSACTIONS (4U)
+
+/** Maximum number of SDP streams */
+#define SBM_DRM_DP_MAX_SDP_STREAMS (16U)
+
+/**
+ * @}
+ */
+
+/** @defgroup DataStructure Dynamic Data Structures
+ * This section defines the data structures used by the driver to provide
+ * hardware information, modification and dynamic operation of the driver.
+ * These data structures are defined in the header file of the core driver
+ * and utilized by the API.
+ * @{
+ */
+
+/**********************************************************************
+* Forward declarations
+**********************************************************************/
+typedef struct SBM_drm_dp_nak_reply_s SBM_drm_dp_nak_reply;
+typedef struct SBM_drm_dp_link_addr_reply_port_s SBM_drm_dp_link_addr_reply_port;
+typedef struct SBM_drm_dp_link_address_ack_reply_s SBM_drm_dp_link_address_ack_reply;
+typedef struct SBM_drm_dp_remote_dpcd_read_ack_reply_s SBM_drm_dp_remote_dpcd_read_ack_reply;
+typedef struct SBM_drm_dp_remote_dpcd_write_ack_reply_s SBM_drm_dp_remote_dpcd_write_ack_reply;
+typedef struct SBM_drm_dp_remote_dpcd_write_nak_reply_s SBM_drm_dp_remote_dpcd_write_nak_reply;
+typedef struct SBM_drm_dp_remote_i2c_read_ack_reply_s SBM_drm_dp_remote_i2c_read_ack_reply;
+typedef struct SBM_drm_dp_remote_i2c_read_nak_reply_s SBM_drm_dp_remote_i2c_read_nak_reply;
+typedef struct SBM_drm_dp_remote_i2c_write_ack_reply_s SBM_drm_dp_remote_i2c_write_ack_reply;
+typedef struct SBM_drm_dp_allocate_payload_s SBM_drm_dp_allocate_payload;
+typedef struct SBM_drm_dp_allocate_payload_ack_reply_s SBM_drm_dp_allocate_payload_ack_reply;
+typedef struct SBM_drm_dp_connection_status_notify_s SBM_drm_dp_connection_status_notify;
+typedef struct SBM_drm_dp_remote_dpcd_read_s SBM_drm_dp_remote_dpcd_read;
+typedef struct SBM_drm_dp_remote_dpcd_write_s SBM_drm_dp_remote_dpcd_write;
+typedef struct SBM_drm_dp_transactions_s SBM_drm_dp_transactions;
+typedef struct SBM_drm_dp_remote_i2c_read_s SBM_drm_dp_remote_i2c_read;
+typedef struct SBM_drm_dp_remote_i2c_write_s SBM_drm_dp_remote_i2c_write;
+typedef struct SBM_drm_dp_port_number_req_s SBM_drm_dp_port_number_req;
+typedef struct SBM_drm_dp_enum_path_resources_ack_reply_s SBM_drm_dp_enum_path_resources_ack_reply;
+typedef struct SBM_drm_dp_port_number_rep_s SBM_drm_dp_port_number_rep;
+typedef struct SBM_drm_dp_resource_status_notify_s SBM_drm_dp_resource_status_notify;
+typedef struct SBM_ack_req_s SBM_ack_req;
+typedef struct SBM_drm_dp_sideband_msg_req_body_s SBM_drm_dp_sideband_msg_req_body;
+typedef struct SBM_ack_replies_s SBM_ack_replies;
+typedef struct SBM_drm_dp_sideband_msg_reply_body_s SBM_drm_dp_sideband_msg_reply_body;
+typedef struct SBM_drm_dp_sideband_msg_tx_s SBM_drm_dp_sideband_msg_tx;
+typedef struct SBM_drm_dp_sideband_msg_hdr_s SBM_drm_dp_sideband_msg_hdr;
+typedef struct SBM_drm_dp_sideband_msg_rx_s SBM_drm_dp_sideband_msg_rx;
+
+/**
+ * @}
+ */
+
+/* parasoft-end-suppress MISRA2012-RULE-1_1_b_c90-2 */
+/* parasoft-end-suppress MISRA2012-RULE-1_1_a_c90-2 */
+
+#endif /* DP_SIDEBAND_MSG_IF_H */
diff --git a/packages/ti/drv/dss/src/csl/dp/include/dp_sideband_msg_obj_if.h b/packages/ti/drv/dss/src/csl/dp/include/dp_sideband_msg_obj_if.h
--- /dev/null
@@ -0,0 +1,40 @@
+/**********************************************************************
+* Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* 1. Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* 2. Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the distribution.
+* 3. Neither the name of the copyright holder nor the names of its
+* contributors may be used to endorse or promote products derived from
+* this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+**********************************************************************
+* WARNING: This file is auto-generated using api-generator utility.
+* api-generator: 12.03.9e11b77(origin/DRV-3827_extract_sanity_to_c_file)
+* Do not edit it manually.
+**********************************************************************
+* Cadence Core Driver for the Cadence DisplayPort (DP) core. This header
+* file lists the Supporting structures for the DP core driver
+**********************************************************************/
+#ifndef DP_SIDEBAND_MSG_OBJ_IF_H
+#define DP_SIDEBAND_MSG_OBJ_IF_H
+
+#include "dp_sideband_msg_if.h"
+
+#endif /* DP_SIDEBAND_MSG_OBJ_IF_H */
diff --git a/packages/ti/drv/dss/src/csl/dp/include/dp_sideband_msg_structs_if.h b/packages/ti/drv/dss/src/csl/dp/include/dp_sideband_msg_structs_if.h
--- /dev/null
@@ -0,0 +1,266 @@
+/* parasoft suppress item MISRA2012-DIR-4_8 "Consider hiding implementation of structure" */
+/**********************************************************************
+* Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* 1. Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* 2. Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the distribution.
+* 3. Neither the name of the copyright holder nor the names of its
+* contributors may be used to endorse or promote products derived from
+* this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+**********************************************************************
+* WARNING: This file is auto-generated using api-generator utility.
+* api-generator: 12.03.9e11b77(origin/DRV-3827_extract_sanity_to_c_file)
+* Do not edit it manually.
+**********************************************************************
+* Cadence Core Driver for the Cadence DisplayPort (DP) core. This header
+* file lists the Supporting structures for the DP core driver
+**********************************************************************/
+#ifndef DP_SIDEBAND_MSG_STRUCTS_IF_H
+#define DP_SIDEBAND_MSG_STRUCTS_IF_H
+
+#include "cdn_stdtypes.h"
+#include "dp_sideband_msg_if.h"
+
+/** @defgroup DataStructure Dynamic Data Structures
+ * This section defines the data structures used by the driver to provide
+ * hardware information, modification and dynamic operation of the driver.
+ * These data structures are defined in the header file of the core driver
+ * and utilized by the API.
+ * @{
+ */
+
+/**********************************************************************
+* Structures and unions
+**********************************************************************/
+struct SBM_drm_dp_nak_reply_s {
+ uint8_t guid[16];
+ uint8_t reason;
+ uint8_t nak_data;
+};
+
+struct SBM_drm_dp_link_addr_reply_port_s {
+ bool input_port;
+ uint8_t peer_device_type;
+ uint8_t port_number;
+ bool mcs;
+ bool ddps;
+ bool legacy_device_plug_status;
+ uint8_t dpcd_revision;
+ uint8_t peer_guid[16];
+ uint8_t num_sdp_streams;
+ uint8_t num_sdp_stream_sinks;
+};
+
+struct SBM_drm_dp_link_address_ack_reply_s {
+ uint8_t guid[16];
+ uint8_t nports;
+ SBM_drm_dp_link_addr_reply_port ports[16];
+};
+
+struct SBM_drm_dp_remote_dpcd_read_ack_reply_s {
+ uint8_t port_number;
+ uint8_t num_bytes;
+ uint8_t bytes[255];
+};
+
+struct SBM_drm_dp_remote_dpcd_write_ack_reply_s {
+ uint8_t port_number;
+};
+
+struct SBM_drm_dp_remote_dpcd_write_nak_reply_s {
+ uint8_t port_number;
+ uint8_t reason;
+ uint8_t bytes_written_before_failure;
+};
+
+struct SBM_drm_dp_remote_i2c_read_ack_reply_s {
+ uint8_t port_number;
+ uint8_t num_bytes;
+ uint8_t bytes[255];
+};
+
+struct SBM_drm_dp_remote_i2c_read_nak_reply_s {
+ uint8_t port_number;
+ uint8_t nak_reason;
+ uint8_t i2c_nak_transaction;
+};
+
+struct SBM_drm_dp_remote_i2c_write_ack_reply_s {
+ uint8_t port_number;
+};
+
+struct SBM_drm_dp_allocate_payload_s {
+ uint8_t port_number;
+ uint8_t number_sdp_streams;
+ uint8_t vcpi;
+ uint16_t pbn;
+ uint8_t sdp_stream_sink[SBM_DRM_DP_MAX_SDP_STREAMS];
+};
+
+struct SBM_drm_dp_allocate_payload_ack_reply_s {
+ uint8_t port_number;
+ uint8_t vcpi;
+ uint16_t allocated_pbn;
+};
+
+struct SBM_drm_dp_connection_status_notify_s {
+ uint8_t guid[16];
+ uint8_t port_number;
+ bool legacy_device_plug_status;
+ bool displayport_device_plug_status;
+ bool message_capability_status;
+ bool input_port;
+ uint8_t peer_device_type;
+};
+
+struct SBM_drm_dp_remote_dpcd_read_s {
+ uint8_t port_number;
+ uint32_t dpcd_address;
+ uint8_t num_bytes;
+};
+
+struct SBM_drm_dp_remote_dpcd_write_s {
+ uint8_t port_number;
+ uint32_t dpcd_address;
+ uint8_t num_bytes;
+ uint8_t* bytes;
+};
+
+struct SBM_drm_dp_transactions_s {
+ uint8_t i2c_dev_id;
+ uint8_t num_bytes;
+ uint8_t* bytes;
+ uint8_t no_stop_bit;
+ uint8_t i2c_transaction_delay;
+};
+
+struct SBM_drm_dp_remote_i2c_read_s {
+ uint8_t num_transactions;
+ uint8_t port_number;
+ SBM_drm_dp_transactions transactions[SBM_DP_REMOTE_I2C_READ_MAX_TRANSACTIONS];
+ uint8_t read_i2c_device_id;
+ uint8_t num_bytes_read;
+};
+
+struct SBM_drm_dp_remote_i2c_write_s {
+ uint8_t port_number;
+ uint8_t write_i2c_device_id;
+ uint8_t num_bytes;
+ uint8_t* bytes;
+};
+
+struct SBM_drm_dp_port_number_req_s {
+ uint8_t port_number;
+};
+
+struct SBM_drm_dp_enum_path_resources_ack_reply_s {
+ uint8_t port_number;
+ uint16_t full_payload_bw_number;
+ uint16_t avail_payload_bw_number;
+};
+
+struct SBM_drm_dp_port_number_rep_s {
+ uint8_t port_number;
+};
+
+struct SBM_drm_dp_resource_status_notify_s {
+ uint8_t port_number;
+ uint8_t guid[16];
+ uint16_t available_pbn;
+};
+
+struct SBM_ack_req_s {
+ SBM_drm_dp_connection_status_notify conn_stat;
+ SBM_drm_dp_port_number_req port_num;
+ SBM_drm_dp_resource_status_notify resource_stat;
+ SBM_drm_dp_allocate_payload allocate_payload;
+ SBM_drm_dp_remote_dpcd_read dpcd_read;
+ SBM_drm_dp_remote_dpcd_write dpcd_write;
+ SBM_drm_dp_remote_i2c_read i2c_read;
+ SBM_drm_dp_remote_i2c_write i2c_write;
+};
+
+struct SBM_drm_dp_sideband_msg_req_body_s {
+ uint8_t req_type;
+ SBM_ack_req u;
+};
+
+struct SBM_ack_replies_s {
+ SBM_drm_dp_nak_reply nak;
+ SBM_drm_dp_link_address_ack_reply link_addr;
+ SBM_drm_dp_port_number_rep port_number;
+ SBM_drm_dp_enum_path_resources_ack_reply path_resources;
+ SBM_drm_dp_allocate_payload_ack_reply allocate_payload;
+ SBM_drm_dp_remote_dpcd_read_ack_reply remote_dpcd_read_ack;
+ SBM_drm_dp_remote_dpcd_write_ack_reply remote_dpcd_write_ack;
+ SBM_drm_dp_remote_dpcd_write_nak_reply remote_dpcd_write_nack;
+ SBM_drm_dp_remote_i2c_read_ack_reply remote_i2c_read_ack;
+ SBM_drm_dp_remote_i2c_read_nak_reply remote_i2c_read_nack;
+ SBM_drm_dp_remote_i2c_write_ack_reply remote_i2c_write_ack;
+};
+
+struct SBM_drm_dp_sideband_msg_reply_body_s {
+ uint8_t reply_type;
+ uint8_t req_type;
+ SBM_ack_replies u;
+};
+
+struct SBM_drm_dp_sideband_msg_tx_s {
+ uint8_t msg[256];
+ uint8_t chunk[48];
+ uint8_t cur_offset;
+ uint8_t cur_len;
+ struct MST_drm_dp_branch_s* dst;
+ int32_t seqno;
+ uint32_t state;
+ bool path_msg;
+ SBM_drm_dp_sideband_msg_reply_body reply;
+};
+
+struct SBM_drm_dp_sideband_msg_hdr_s {
+ uint8_t lct;
+ uint8_t lcr;
+ uint8_t rad[8];
+ bool broadcast;
+ bool path_msg;
+ uint8_t msg_len;
+ bool somt;
+ bool eomt;
+ bool seqno;
+};
+
+struct SBM_drm_dp_sideband_msg_rx_s {
+ uint8_t chunk[48];
+ uint8_t msg[256];
+ uint8_t curchunk_len;
+ uint8_t curchunk_idx;
+ uint8_t curchunk_hdrlen;
+ uint8_t curlen;
+ bool have_somt;
+ bool have_eomt;
+ SBM_drm_dp_sideband_msg_hdr initial_hdr;
+};
+
+/**
+ * @}
+ */
+
+#endif /* DP_SIDEBAND_MSG_STRUCTS_IF_H */
diff --git a/packages/ti/drv/dss/src/csl/dp/include/dp_structs_if.h b/packages/ti/drv/dss/src/csl/dp/include/dp_structs_if.h
--- /dev/null
@@ -0,0 +1,632 @@
+/* parasoft suppress item MISRA2012-DIR-4_8 "Consider hiding implementation of structure" */
+/**********************************************************************
+* Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* 1. Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* 2. Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the distribution.
+* 3. Neither the name of the copyright holder nor the names of its
+* contributors may be used to endorse or promote products derived from
+* this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+**********************************************************************
+* WARNING: This file is auto-generated using api-generator utility.
+* api-generator: 12.03.9e11b77(origin/DRV-3827_extract_sanity_to_c_file)
+* Do not edit it manually.
+**********************************************************************
+* Cadence Core Driver for the Cadence DisplayPort (DP) core. This header
+* file lists the API providing a HAL (hardware abstraction layer)
+* interface for the DP core
+**********************************************************************/
+#ifndef DP_STRUCTS_IF_H
+#define DP_STRUCTS_IF_H
+
+#include "cdn_stdtypes.h"
+#include "dp_if.h"
+
+/** @defgroup DataStructure Dynamic Data Structures
+ * This section defines the data structures used by the driver to provide
+ * hardware information, modification and dynamic operation of the driver.
+ * These data structures are defined in the header file of the core driver
+ * and utilized by the API.
+ * @{
+ */
+
+/**********************************************************************
+* Structures and unions
+**********************************************************************/
+struct DP_VideoFormatParams_s
+{
+ /**
+ * Video Information Code - An integer value used to identify a particular
+ * Video Format, as in ANSI-CEA-861-F standard. '0' means, that video format
+ * timings do not correspond to any from the standard.
+ * Informative only - when structure is filled manually, this
+ * value is not used.
+ */
+ uint32_t vic;
+ /**
+ * Total amount of pixel clock periods in a video line, including blanking
+ * period.
+ */
+ uint32_t hTotal;
+ /**
+ * Amount of pixel clock periods used for active pixels (conveying pixel
+ * data) in a video line.
+ * For RGB pixel encoding, it has to be a multiple of 2.
+ * For other pixel encodings (like YCbCr), it has to be a multiple of 16.
+ */
+ uint32_t hActive;
+ /**
+ * Amount of pixel clock periods used for blank pixels (conveying data
+ * other than pixel data) in a video line.
+ */
+ uint32_t hBlank;
+ /**
+ * Amount of pixel clock periods contributing to horizontal sync signal in
+ * a video line.
+ */
+ uint32_t hSync;
+ /**
+ * Amount of pixel clock periods contributing to front porch in a video
+ * line.
+ */
+ uint32_t hFrontPorch;
+ /**
+ * Amount of pixel clock periods contributing to back porch in a video
+ * line.
+ */
+ uint32_t hBackPorch;
+ /** Horizontal frequency, expressed in kilohertz (kHz). */
+ float64_t hFreq;
+ /** Total amount of lines in a video frame, including blanking period. */
+ uint32_t vTotal;
+ /**
+ * Amount of active lines (containing both active and blanking pixels) in
+ * a video frame.
+ */
+ uint32_t vActive;
+ /**
+ * Amount of blanking lines (containing only blanking pixels) in a video
+ * frame. Might be fractional fir interlaced video formats.
+ */
+ float64_t vBlank;
+ /** Amount of blanking lines contributing to vertical sync in a video frame. */
+ uint32_t vSync;
+ /**
+ * Amount of blanking lines contributing to vertical front porch in a video
+ * frame.
+ */
+ uint32_t vFrontPorch;
+ /**
+ * Amount of blanking lines contributing to vertical back porch in a video
+ * frame.
+ */
+ uint32_t vBackPorch;
+ /** Vertical frequency, expressed in hertz (Hz). */
+ float64_t vFreq;
+ /** Pixel clock frequency, expressed in megahertz (MHz). */
+ float64_t pxlFreq;
+ /** Video scan mode (progressive / interlaced) */
+ DP_ScanMode scanMode;
+ /** Polarity of horizontal sync pulse. */
+ DP_SyncPolarity hSyncPolarity;
+ /** Polarity of vertical sync pulse. */
+ DP_SyncPolarity vSyncPolarity;
+ /**
+ * 4-bit value used as bits R3 - R0 in AVI InfoFrame, related to aspect
+ * ratio of active frame potion.
+ */
+ uint8_t vicR;
+ /**
+ * 4-bit value used as bits PR3 - PR0 in AVI InfoFrame, related to pixel
+ * repetition factor.
+ */
+ uint8_t vicPR;
+};
+
+/** Structure used to store source device capabilities. */
+struct DP_SourceDeviceCapabilities_s
+{
+ /** Maximum link rate supported. */
+ DP_LinkRate maxLinkRate;
+ /** Maximum lane count supported. */
+ uint8_t laneCount;
+ /** Spread spectrum clock supported. */
+ bool ssc;
+ /** Prevents enabling scrambler in DPTX (also outside Link Training). */
+ bool scramblerDisable;
+ /** Fast Link Training supported. */
+ bool fastLinkTraining;
+ /** Use Training Pattern Sequence 3 (TPS3), when supported. */
+ bool tps3;
+ /** Use Training Pattern Sequence 4 (TPS4), when supported. */
+ bool tps4;
+ /** Maximum voltage swing supported. */
+ uint8_t maxVoltageSwing;
+ /** Maximum pre-emphasis supported. */
+ uint8_t maxPreemphasis;
+ /** Force voltage swing level to one set as maximum supported. */
+ bool forceVoltageSwing;
+ /** Force pre-emphasis level to one set as maximum supported. */
+ bool forcePreemphasis;
+ /** Specifies lane mapping. */
+ DP_LaneMapping laneMapping;
+ /** Number of controllers to be used with single PHY. */
+ DP_ControllersPerPhy controllersPerPhy;
+ /** Whether device is an eDP device or not. */
+ bool isEdp;
+};
+
+/** Structure used to store sink device capabilities. */
+struct DP_SinkDeviceCapabilities_s
+{
+ /** Maximum link rate supported. */
+ DP_LinkRate maxLinkRate;
+ /** Maximum lane count supported. */
+ uint8_t laneCount;
+ /** Spread spectrum clock supported. */
+ bool ssc;
+ /** Fast Link Training supported */
+ bool fastLinkTraining;
+ /** Training Pattern Sequence 3 (TPS3) is supported. */
+ bool tps3;
+ /** Training Pattern Sequence 3 (TPS3) is supported. */
+ bool tps4;
+ /** Enhanced framing mode is supported. */
+ bool enhanced;
+ /** ASSR (Alternate Scrambler Seed Reset) mode is supported. */
+ bool assr;
+ /**
+ * Indicates, if sink supports selecting link rate using LINK_BW_SET DPCD
+ * register (100h).
+ */
+ bool linkBwSupported;
+ /**
+ * Time interval required before reading status of Channel Equalization
+ * during Link Training, in microseconds.
+ */
+ uint32_t TrainingInterval;
+ /**
+ * Indicates, if sink supports selecting link rate using LINK_RATE_SET DPCD
+ * register (115h), specific to eDP.
+ */
+ bool linkRateSupported;
+ /**
+ * Number of valid (non-zero) 16-bit entries in SUPPORTED_LINK_RATES DPCD
+ * registers(10h - 1Fh), indicating number of link rates sink device
+ * supports using LINK_RATE_SET method, specific to eDP.
+ */
+ uint8_t edpRateCount;
+ /**
+ * Values of 16-bit entries in SUPPORTED_LINK_RATES DPCD registers,
+ * specific to eDP.
+ */
+ uint16_t edpRatesRegisters[8];
+ /**
+ * Flags indicating support of DP 1.4 and eDP 1.4 link rates, as defined
+ * in DP_LinkRate
+ */
+ bool ratesSupported[8];
+};
+
+/** Reply data struct for DP_ReadEdid and DP_GetEdidReadResponse. */
+struct DP_ReadEdidResponse_s
+{
+ /**
+ * Address of buffer used to store response with EDID.
+ * Must fit at least 128 bytes.
+ */
+ uint8_t* buff;
+ /** Size of data read (in bytes) */
+ uint8_t size;
+ /** Number of EDID block, that was read. */
+ uint8_t blockNo;
+};
+
+/** Structure for performing DPCD read/write operations. */
+struct DP_DpcdTransfer_s
+{
+ /**
+ * For reading DPCD registers: Pointer to buffer used to store response
+ * with DPCD register read. Must fit at least as many bytes, as were
+ * requested to read.
+ * For writing DPCD register: Pointer to buffer with values to write to
+ * DPCD registers.
+ */
+ uint8_t* buff;
+ /**
+ * Address of first DPCD register, to read/write. After operation - address
+ * of first DPCD register, that was read/written. If it differs from
+ * requested address, an error occurred, which may be checked using
+ * DP_GetAuxStatus.
+ */
+ uint32_t addr;
+ /**
+ * Size of data to read/write (in bytes). After operation - size of data
+ * actually read/written. If it differs from requested size, an error
+ * occurred, which may be checked using DP_GetAuxStatus.
+ */
+ uint16_t size;
+};
+
+/** Structure for performing I2C-over-AUX read/write operations. */
+struct DP_I2cTransfer_s
+{
+ /**
+ * For Reading from I2C slave over AUX: Pointer to buffer used to store
+ * response with bytes read. Must fit at least as many bytes, as were
+ * requested to read.
+ * For writing to I2C slave over AUX: Pointer to buffer with values to
+ * write to I2C slave device.
+ */
+ uint8_t* buff;
+ /**
+ * 7-bit address of I2C slave to read/write, placed at bits 0-6 (without
+ * direction bit). After operation - address of I2C device, that was
+ * read/written. If it differs from requested address, an error occurred,
+ * which may be checked using DP_GetAuxStatus and DP_GetI2cStatus functions.
+ */
+ uint8_t addr;
+ /**
+ * Whether or not to set MoT (Middle-of-Transaction) flag during the last
+ * I2C-over-AUX transaction handling this operation. If "false", DPRX will
+ * assert a STOP condition after this operation. Otherwise, it will do the
+ * clock stretching until the next transaction happens, asserting Repeated
+ * Start condition if address or direction of transfer has changed.
+ * If an error occurs, an address-only transaction with MoT bit cleared will
+ * be sent regardless of this setting, to terminate I2C-over-AUX sequence.
+ */
+ bool mot;
+ /**
+ * Size of data to read/write (in bytes). After operation - size of data
+ * actually read/written. If it differs from requested size, an error occurred,
+ * which may be checked using DP_GetAuxStatus and DP_GetI2cStatus functions.
+ */
+ uint16_t size;
+};
+
+/** VIC-related video parameters. */
+struct DP_VideoParameters_s
+{
+ /**
+ * Pointer to structure containing parameters related to VIC. Structure
+ * may be filled manually, or using DP_FillVideoFormat function.
+ */
+ DP_VideoFormatParams vicParams;
+ /** Bits per subpixel or pixel component. */
+ uint8_t bitsPerSubpixel;
+ /** Pixel encoding format */
+ DP_PixelEncodingFormat pxEncFormat;
+ /** Stereo video attribute */
+ DP_StereoVideoAttr stereoVidAttr;
+ /** BT type */
+ DP_BtType btType;
+ /**
+ * When set to 'true', force setting bit 6 in MSA_MISC1 value, for
+ * configuring video using SDP, similarly to YCbCr 4:2:0 mode.
+ */
+ bool forceMiscIgnoreBit;
+ /** DSC enabled, 'true' - enable DSC. */
+ bool dscEnable;
+ /** Alignment of the input pixel data at the pixel interface. */
+ DP_PxlAlignment alignment;
+};
+
+/** Structure containing parameters of physical link. */
+struct DP_LinkState_s
+{
+ /** Link Rate */
+ DP_LinkRate linkRate;
+ /** Lane count */
+ uint8_t laneCount;
+ /** Voltage swing level, one per lane. */
+ uint8_t voltageSwing[DP_MAX_NUMBER_OF_LANES];
+ /** Pre-emphasis level, one per lane. */
+ uint8_t preEmphasis[DP_MAX_NUMBER_OF_LANES];
+ /** SSC (Spread-Spectrum Clock) enabled. */
+ bool ssc;
+};
+
+/** Structure describing single SDP (Secondary Data Packet) entry. */
+struct DP_SdpEntry_s
+{
+ /** Length of data packet, expressed in 4-byte words ( = size in bytes / 4) */
+ uint8_t length;
+ /** 8-bit value describing SDP type. */
+ uint8_t type;
+ /** Pointer to beginning of buffer containing SDP itself. */
+ uint32_t* packet;
+ /** Selects, when SDP will be active. */
+ DP_SdpActiveIdleMode activeMode;
+};
+
+/** Structure used for values used to configure and control HDCP transmitter. */
+struct DP_HdcpTxConfiguration_s
+{
+ /**
+ * HDCP version(s), that shall be supported. '0' - only HDCP 2.2,
+ * '1' - only HDCP 1.4, '2' - both (HDCP 2.2 will be attempted first)
+ */
+ DP_HdcpVerSupport hdcpVerSupport;
+ /** activate/stop transmitter (1 to activate, 0 to stop) */
+ bool activate;
+ /** Content Stream type. For MST operation, type 0 must be selected. */
+ DP_ContentStreamType contentStreamType;
+ /**
+ * Enable km-key encryption. Once enabled (using value 'true'), cannot be
+ * disabled, except for reset. When enabled, HDCP controller will expect
+ * Master Key, HDCP 1.4 Device Keys and Global Constant (lc128) to be
+ * encrypted by custom key, loaded using function DP_SetHdcpKmEncCustomKey
+ */
+ bool enableKmEncryption;
+};
+
+/**
+ * Structure containing public key values for HDCP 2.x transmitter. It is
+ * called "DCP LLC public key" in HDCP 2.2 specification.
+ */
+struct DP_Hdcp2TxPublicKey_s
+{
+ /** Modulus n */
+ uint8_t modulusN[384];
+ /** Public exponent e */
+ uint8_t exponentE[3];
+};
+
+/** Structure containing custom key for decrypting other HDCP keys. */
+struct DP_HdcpTxKmEncCustomKey_s
+{
+ /** 16-byte custom key for km-key encryption. */
+ uint8_t kmEncCutomKey[16];
+};
+
+/** Structure containing random numbers for debug purposes. */
+struct DP_HdcpDebugRandomNumbers_s
+{
+ /** KM random value */
+ uint8_t km[16];
+ /** RN random value */
+ uint8_t rn[8];
+ /** KS random value */
+ uint8_t ks[16];
+ /** RIV random value */
+ uint8_t riv[8];
+ /** RTX random value */
+ uint8_t rtx[8];
+};
+
+/** Structure containing pairing associated with HDCP 2.x receiver. */
+struct DP_HdcpPairingData_s
+{
+ /** Receiver ID. */
+ uint8_t id[5];
+ /** 'm' value associated with Receiver ID. */
+ uint8_t m[16];
+ /**
+ * Value of km key associated with Receiver ID. If km-key encryption is
+ * enabled, it will be encrypted while reading and is expected to be
+ * encrypted for setting, using 16-byte custom key for km-key encryption.
+ */
+ uint8_t km[16];
+ /**
+ * Ekh(km) - km key in a form, that was encrypted (and can be
+ * decrypted) by receiver with associated Receiver ID.
+ */
+ uint8_t ekhKm[16];
+};
+
+/** Structure containing HDCP 1.x device keys, with associated KSV. */
+struct DP_Hdcp1Keys_s
+{
+ /** Key Seletion Vector */
+ uint8_t ksv[5];
+ /**
+ * 40 Device Private Keys, 7-bytes each. If km-key encryption is
+ * enabled, they are expected to be provided in encrypted form.
+ */
+ uint8_t keys[280];
+};
+
+/** Structure containing status for HDCP. */
+struct DP_HdcpTxStatus_s
+{
+ /** Authenticated - 'true', if receiver is authenticated. */
+ bool authenticated;
+ /** Repeater - 'true', if receiver is a repeater. */
+ bool repeater;
+ /** HDCP receiver type - 1, if HDCP receiver supports 1.x . 2 if HDCP 2.x . */
+ uint8_t rxType;
+ /** AuthStreamId - 'true' for success. */
+ bool authStreamIdSuccess;
+ /** Last HDCP error. */
+ DP_HdcpErrCode lastErr;
+ /** Work with ENABLE_1.1_FEATURES */
+ bool enable1d1Features;
+};
+
+/**
+ * Structure containing Receiver IDs (HDCP 2.x) or KSVs (HDCP 1.x) of all
+ * receivers, connected directly or via repeaters
+ */
+struct DP_HdcpRecvIdList_s
+{
+ /** List of 5-byte entries (Rx IDs / KSVs) - up to 127 of these. */
+ uint8_t ids[635];
+ /** Number of 5-byte entries in the list (Rx IDs / KSVs) */
+ uint8_t count;
+};
+
+/** Aggregate of parameters for configuring audio. */
+struct DP_AudioParams_s
+{
+ /** Number of audio channels */
+ uint32_t channelCount;
+ DP_AudioFreq freq;
+ uint32_t laneCount;
+ DP_AudioWidth width;
+};
+
+/** Configuration for a single RC model range */
+struct DP_DscRangeCfg_s
+{
+ /** Specifies the minimum QP that is allowed to the current range */
+ uint32_t rangeMinQp;
+ /** Specifies the maximum QP that is allowed to the current range */
+ uint32_t rangeMaxQp;
+ /** Specifies the target bits per group adjustment to the current range */
+ int32_t rangeBpgOffset;
+};
+
+/** DSC configuration */
+struct DP_DscConfig_s
+{
+ /** Bits / component for previous reconstructed line buffer */
+ uint32_t linebufDepth;
+ /** Bits / component to code */
+ DP_BitsPerComponent bitsPerComponent;
+ /** slice width in pixels */
+ uint32_t sliceWidth;
+ /** slice height in pixels */
+ uint32_t sliceHeight;
+ /** picture width */
+ uint32_t picWidth;
+ /** picture height */
+ uint32_t picHeight;
+ /** Offset to bits/group used by RC to determine QP adjustment */
+ uint32_t rcTgtOffsetHi;
+ /** Offset to bits/group used by RC to determine QP adjustment */
+ uint32_t rcTgtOffsetLo;
+ /** Bits/pixel target << 4 (ie., 4 fractional bits) */
+ uint32_t bitsPerPixel;
+ /** Factor to determine if an edge is present based on the bits produced */
+ uint32_t rcEdgeFactor;
+ /** Slow down incrementing once the range reaches this value */
+ uint32_t rcQuantIncrLimit1;
+ /** Slow down incrementing once the range reaches this value */
+ uint32_t rcQuantIncrLimit0;
+ /** Number of pixels to delay the initial transmission */
+ uint32_t initialXmitDelay;
+ /** Block prediction range (in pixels) */
+ uint32_t blockPredEnable;
+ /** Value to use for RC model offset at slice start */
+ uint32_t initialOffset;
+ /** Thresholds defining each of the buffer ranges */
+ uint32_t rcBufThresh[DP_DSC_NUM_BUF_RANGES - 1U];
+ /** Parameters for each of the RC ranges */
+ DP_DscRangeCfg rcRangeParameters[DP_DSC_NUM_BUF_RANGES];
+ /** Total size of RC model */
+ uint32_t rcModelSize;
+ /** Minimum QP where flatness information is sent */
+ uint32_t flatnessMinQp;
+ /** Maximum QP where flatness information is sent */
+ uint32_t flatnessMaxQp;
+ /** Enable on-off VBR (ie., disable stuffing bits) */
+ uint32_t vbrEnable;
+ /** Placeholder for PPS identifier */
+ uint32_t ppsIdentifier;
+ /**
+ * When 'true', both encoders are used in parallel for one video stream (L and R split).
+ * When 'false', one encoder is used.
+ */
+ bool splitPanel;
+ /** Number of lines to wait before initiating transport in Command Mode */
+ uint32_t initialLines;
+ /** the upstream source timing controller total line time (in clock cycles, not in pixels) */
+ uint32_t hTotal;
+ /** Flatness Detection Threshold */
+ uint32_t flatnessDetThresh;
+};
+
+/** Configuration parameters passed to probe & init functions. */
+struct DP_Config_s
+{
+ /**
+ * Base address of the APB register space.
+ *
+ */
+ struct MHDP_ApbRegs_s* regBase;
+ /**
+ * Base address of the SAPB (Secure APB) register space.
+ *
+ */
+ struct MHDP_ApbRegs_s* regBaseSapb;
+};
+
+/**
+ * Structure containing function pointers for event notification callbacks
+ * issued by isr().
+ * Each call passes the driver's privateData (pD) pointer for instance
+ * identification if necessary.
+ */
+struct DP_Callbacks_s
+{
+ DP_CbEvent event;
+};
+
+/** Structure used for storing information about sink device */
+struct DP_SinkDevice_s
+{
+ /** Connection port of device */
+ MST_drm_dp_port* port;
+ /** Stores source stream ID */
+ uint8_t streamId;
+};
+
+/** Structure used for storing addreses and sizes of image of FW to load. */
+struct DP_FirmwareImage_s
+{
+ /** Pointer to instruction memory image. */
+ uint8_t* iMem;
+ /** Size of instruction memory buffer, in bytes. */
+ uint32_t iMemSize;
+ /** Pointer to data memory image. */
+ uint8_t* dMem;
+ /** Size of data memory buffer, in bytes. */
+ uint32_t dMemSize;
+};
+
+/** Structure used for specifying clock of embedded uCPU. */
+struct DP_UcpuClock_s
+{
+ /** Clock, that Xtensa uCPU is running at, in MHz. */
+ uint8_t mhz;
+ /**
+ * Fractional part of clock, that Xtensa uCPU is running at, in MHz.
+ * Expressed in units of 1/100th of MHz (10 kHz)
+ */
+ uint8_t fraction;
+};
+
+/** Structure used for specifying audio video clocks configuration */
+struct DP_AudioVideoClkCfg_s
+{
+ /** dptx video clock configuration (true - enabled, false - disabled) */
+ bool videoClockEnable;
+ /** source audio clock configuration (true - enabled, false - disabled) */
+ bool audioClockEnable;
+ /** source packet data clock configuration (true - enabled, false - disabled) */
+ bool pktDataClockEnable;
+};
+
+/**
+ * @}
+ */
+
+#endif /* DP_STRUCTS_IF_H */
diff --git a/packages/ti/drv/dss/src/csl/dp/src/custom_types.h b/packages/ti/drv/dss/src/csl/dp/src/custom_types.h
--- /dev/null
@@ -0,0 +1,44 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ *
+ * custom_types.h
+ *
+ ******************************************************************************
+ */
+
+#ifndef CUSTOM_TYPES_H_
+#define CUSTOM_TYPES_H_
+
+#include "cdn_stdtypes.h"
+
+typedef float float32_t;
+typedef double float64_t;
+
+#endif /* CUSTOM_TYPES_H_ */
diff --git a/packages/ti/drv/dss/src/csl/dp/src/dp_audio.c b/packages/ti/drv/dss/src/csl/dp/src/dp_audio.c
--- /dev/null
@@ -0,0 +1,466 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ *
+ * dp_audio.c
+ *
+ ******************************************************************************
+ */
+
+/* parasoft-begin-suppress METRICS-41 "Number of comments blocks before and inside function" */
+
+#include "dp_if.h"
+#include "dp_priv.h"
+#include "dp_mst.h"
+#include "dp_sanity.h"
+#include "dp_register.h"
+
+#include "mhdp_apb_regs.h"
+#include "cps_drv.h"
+
+#include "cdn_errno.h"
+#include "cdn_stdint.h"
+
+typedef struct RegisterConfig_s {
+ volatile uint32_t* regAddress;
+ uint32_t regValue;
+} RegisterConfig;
+
+uint32_t DP_AudioSetMute(DP_PrivateData* pD, uint8_t streamId, DP_AudioMuteMode muteMode)
+{
+ const uint8_t audioMuteBitPos = 4U; /* As in DP specification, VB-ID. */
+ uint32_t retVal;
+ DP_RegisterTransfer regTransfer = {0U};
+ uint32_t addr = offsetof(MHDP_ApbRegs, mhdp_apb_regs.mhdp_dptx_stream[0].DP_VB_ID_p);
+ addr += streamId * (uint32_t)sizeof(pD->regBase->mhdp_apb_regs.mhdp_dptx_stream[0]);
+ DP_WriteFieldRequest req = {.addr = addr,
+ .startBit = audioMuteBitPos,
+ .bitCount = 1U,
+ .val = ((DP_AUDIO_MUTE == muteMode) ? (1U << audioMuteBitPos) : 0U)};
+
+ retVal = DP_AudioSetMuteSF(pD, muteMode);
+
+ if (CDN_EOK == retVal)
+ {
+ retVal = DP_StreamIdMstSstSanity(pD, streamId);
+ }
+
+ if (CDN_EOK == retVal)
+ {
+ retVal = DP_WriteField(pD, &req);
+ }
+
+ if (CDN_EOK == retVal)
+ {
+ /* Register read - to make sure uCPU has finished writing the register. */
+ regTransfer.addr = req.addr;
+ retVal = DP_ReadRegister(pD, ®Transfer);
+ }
+
+ return retVal;
+}
+
+uint32_t DP_AudioSetMode(DP_PrivateData* pD, uint8_t streamId, DP_AudioMode mode)
+{
+ uint32_t retVal;
+ DP_RegisterTransfer regTransfer = {0U};
+
+ retVal = DP_AudioSetModeSF(pD, mode);
+ if (CDN_EOK == retVal)
+ {
+ retVal = DP_StreamIdMstSstSanity(pD, streamId);
+ }
+
+ if (CDN_EOK == retVal)
+ {
+ regTransfer.addr = offsetof(MHDP_ApbRegs, mhdp_apb_regs.mhdp_dptx_stream[0].AUDIO_PACK_CONTROL_p);
+ regTransfer.addr += streamId * (uint32_t)sizeof(pD->regBase->mhdp_apb_regs.mhdp_dptx_stream[0]);
+ regTransfer.val = CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__AUDIO_PACK_CONTROL_P, AUDIO_PACK_EN, 0U, (uint8_t)mode);
+ retVal = DP_WriteRegister(pD, ®Transfer);
+ }
+
+ if (CDN_EOK == retVal)
+ {
+ /* Register read - to make sure uCPU has finished writing the register. */
+ retVal = DP_ReadRegister(pD, ®Transfer);
+ }
+
+ return retVal;
+}
+
+static uint16_t getLanesParameter(const DP_AudioParams* params)
+{
+ uint16_t lanesParam;
+
+ if (params->channelCount == 2U) {
+ if (params->laneCount == 1U) {
+ lanesParam = 1U;
+ } else {
+ lanesParam = 3U;
+ }
+ } else {
+ lanesParam = 0U;
+ }
+
+ return lanesParam;
+}
+
+static uint32_t getI2SPortEnableValue(uint32_t channelCount)
+{
+ uint32_t I2S_DEC_PORT_EN_Val;
+
+ if (channelCount == 2U) {
+ I2S_DEC_PORT_EN_Val = 0x1U;
+ } else if (channelCount == 4U) {
+ I2S_DEC_PORT_EN_Val = 0x3U;
+ } else {
+ I2S_DEC_PORT_EN_Val = 0xFU;
+ }
+
+ return I2S_DEC_PORT_EN_Val;
+}
+
+static void setStatusBitRegisters(const DP_PrivateData* pD, uint8_t streamId, uint32_t channelCount) {
+ uint32_t i;
+ uint32_t regVal;
+ uint32_t wordLength = CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH01_P, WORD_LENGTH_CH0, 0U, 0x2U)
+ | CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH01_P, WORD_LENGTH_CH1, 0U, 0x2U);
+
+ volatile uint32_t* regAddress = &pD->regBase->mhdp_apb_regs.mhdp_audio_decoder[streamId].STTS_BIT_CH01_p;
+
+ for (i = 0U; i < ((channelCount + 1U) / 2U); i++) {
+ regVal = CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH01_P, CHANNEL_NUM_CH0, 0U, i * 2U)
+ | CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH01_P, CHANNEL_NUM_CH1, 0U, (i * 2U) + 1U);
+
+ CPS_REG_WRITE(regAddress, (wordLength | regVal));
+ regAddress++;
+ }
+}
+
+static void audioConfigCoreI2S(const DP_PrivateData* pD, uint8_t streamId, const DP_AudioParams* params)
+{
+ uint8_t i;
+ uint32_t channelCount = params->channelCount;
+ uint32_t maxChannelNumber = channelCount - 1U;
+ uint32_t numOfI2SPorts = (channelCount / 2U) - 1U;
+ struct MHDP_ApbRegs_s* regBase = pD->regBase;
+
+ typedef struct {
+ uint8_t samplingFrequency;
+ uint8_t orginalSamplingFrequency;
+
+ } ChannelSampling;
+
+ static ChannelSampling channelSamplings[] = {{0x3U, 0xCU}, /* DP_AUDIO_FREQ_32 */
+ {0x2U, 0xDU}, /* DP_AUDIO_FREQ_48 */
+ {0xAU, 0x5U}, /* DP_AUDIO_FREQ_96 */
+ {0xEU, 0x1U}, /* DP_AUDIO_FREQ_192 */
+ {0x0U, 0xFU}, /* DP_AUDIO_FREQ_44_1 */
+ {0x8U, 0x7U}, /* DP_AUDIO_FREQ_88_2 */
+ {0xCU, 0x3U}}; /* DP_AUDIO_FREQ_176_4 */
+
+ RegisterConfig config[] = {
+ { ®Base->mhdp_apb_regs.mhdp_audio_decoder[streamId].FIFO_CNTL_p,
+ CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__FIFO_CNTL_P, SYNC_WR_TO_CH_ZERO, 0U, 0x1U)},
+ { ®Base->mhdp_apb_regs.mhdp_audio_decoder[streamId].SMPL2PKT_CNFG_p,
+ CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SMPL2PKT_CNFG_P, MAX_NUM_CH, 0U, maxChannelNumber) |
+ CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SMPL2PKT_CNFG_P, NUM_OF_I2S_PORTS, 0U, numOfI2SPorts) |
+ CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SMPL2PKT_CNFG_P, AUDIO_TYPE, 0U, 0x2U) |
+ CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SMPL2PKT_CNFG_P, CFG_SUB_PCKT_NUM, 0U, getLanesParameter(params))},
+ { ®Base->mhdp_apb_regs.mhdp_audio_decoder[streamId].AUDIO_SRC_CNFG_p,
+ CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__AUDIO_SRC_CNFG_P, TRANS_SMPL_WIDTH, 0U, 0x2U) |
+ CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__AUDIO_SRC_CNFG_P, AUDIO_SAMPLE_WIDTH, 0U, params->width) |
+ CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__AUDIO_SRC_CNFG_P, AUDIO_CH_NUM, 0U, maxChannelNumber) |
+ CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__AUDIO_SRC_CNFG_P, I2S_DEC_PORT_EN, 0U, getI2SPortEnableValue(channelCount))},
+ { ®Base->mhdp_apb_regs.mhdp_audio_decoder[streamId].COM_CH_STTS_BITS_p,
+ CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__COM_CH_STTS_BITS_P, BYTE0, 0U, 0x4U) |
+ CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__COM_CH_STTS_BITS_P, SAMPLING_FREQ, 0U, channelSamplings[params->freq].samplingFrequency) |
+ CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__COM_CH_STTS_BITS_P, ORIGINAL_SAMP_FREQ, 0U, channelSamplings[params->freq].orginalSamplingFrequency)},
+ { ®Base->mhdp_apb_regs.mhdp_audio_decoder[streamId].AUDIO_SRC_CNTL_p,
+ CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__AUDIO_SRC_CNTL_P, I2S_DEC_START, 0U, 0x1U)},
+ { ®Base->mhdp_apb_regs.mhdp_audio_decoder[streamId].SMPL2PKT_CNTL_p,
+ CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SMPL2PKT_CNTL_P, SMPL2PKT_EN, 0U, 0x1U)}
+ };
+
+ setStatusBitRegisters(pD, streamId, channelCount);
+
+ for (i = 0U; i < 6U; i++) {
+ CPS_REG_WRITE(config[i].regAddress, config[i].regValue);
+ }
+}
+
+#ifdef CDNS_NEVER_SPDIF
+static void audioConfigCoreNoI2s(const DP_PrivateData* pD, uint8_t streamId, const DP_AudioParams* params)
+{
+ uint8_t i;
+ uint16_t lanesParameter = getLanesParameter(params);
+
+ RegisterConfig config [] = {
+ { &pD->regBase->mhdp_apb_regs.mhdp_audio_decoder[streamId].FIFO_CNTL_p,
+ CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__FIFO_CNTL_P, SYNC_WR_TO_CH_ZERO, 0U, 0x1U)},
+ { &pD->regBase->mhdp_apb_regs.mhdp_audio_decoder[streamId].SMPL2PKT_CNFG_p,
+ CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SMPL2PKT_CNFG_P, MAX_NUM_CH, 0U, 0x1U) |
+ CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SMPL2PKT_CNFG_P, AUDIO_TYPE, 0U, 0x2U) |
+ CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SMPL2PKT_CNFG_P, CFG_SUB_PCKT_NUM, 0U, lanesParameter)},
+ { &pD->regBase->mhdp_apb_regs.mhdp_audio_decoder[streamId].SMPL2PKT_CNTL_p,
+ CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SMPL2PKT_CNTL_P, SMPL2PKT_EN, 0U, 0x1U)},
+ { &pD->regBase->mhdp_apb_regs.mhdp_audio_decoder[streamId].SPDIF_CTRL_ADDR_p,
+ CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CTRL_ADDR_P, SPDIF_JITTER_AVG_WIN, 0U, 0x7U) |
+ CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CTRL_ADDR_P, SPDIF_JITTER_THRSH, 0U, 0xE0U) |
+ CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CTRL_ADDR_P, SPDIF_FIFO_MID_RANGE, 0U, 0xE0U) |
+ CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CTRL_ADDR_P, SPDIF_JITTER_BYPASS, 0U, 0x1U) |
+ CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CTRL_ADDR_P, SPDIF_AVG_SEL, 0U, 0x1U) |
+ CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CTRL_ADDR_P, SPDIF_ENABLE, 0U, 0x1U)}
+ };
+
+ for (i = 0U; i < 4U; i++) {
+ CPS_REG_WRITE(config[i].regAddress, config[i].regValue);
+ }
+}
+#endif /* CDNS_NEVER_SPDIF */
+
+static uint32_t setCmLaneCtrl(DP_PrivateData* pD, uint8_t stream, const uint32_t referenceCycles)
+{
+ DP_RegisterTransfer regTransfer = {0U};
+ uint8_t streamId = stream;
+
+ regTransfer.addr = offsetof(MHDP_ApbRegs, mhdp_apb_regs.mhdp_clock_meter[0].CM_LANE_CTRL_p);
+ regTransfer.addr += streamId * (uint32_t)sizeof(pD->regBase->mhdp_apb_regs.mhdp_clock_meter[0]);
+
+ if (referenceCycles != 0U) {
+ regTransfer.val = CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__CM_LANE_CTRL_P, LANE_REF_CYC, 0U, referenceCycles);
+ } else {
+ regTransfer.val = 0U;
+ }
+
+ return DP_WriteRegister(pD, ®Transfer);
+}
+
+static uint32_t setAudioPackStatus(DP_PrivateData* pD, uint8_t stream, const uint32_t audioTsVersion)
+{
+ DP_RegisterTransfer regTransfer = {0U};
+ uint8_t streamId = stream;
+
+ regTransfer.addr = offsetof(MHDP_ApbRegs, mhdp_apb_regs.mhdp_dptx_stream[0].AUDIO_PACK_STATUS_p);
+ regTransfer.addr += streamId * (uint32_t)sizeof(pD->regBase->mhdp_apb_regs.mhdp_dptx_stream[0]);
+ regTransfer.val = CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__AUDIO_PACK_STATUS_P, AUDIO_TS_VERSION, 0U, audioTsVersion);
+
+ return DP_WriteRegister(pD, ®Transfer);
+}
+
+static uint32_t configAudioCore(DP_PrivateData* pD, uint8_t streamId, const DP_AudioParams* params)
+{
+ DP_RegisterTransfer regTransfer = {0U};
+
+#ifdef CDNS_NEVER_SPDIF
+ if (params->type == DP_AUDIO_TYPE_I2S) {
+ audioConfigCoreI2S(pD, streamId, params);
+ } else {
+ audioConfigCoreNoI2s(pD, streamId, params);
+ }
+#else /* CDNS_NEVER_SPDIF */
+ audioConfigCoreI2S(pD, streamId, params);
+#endif /* CDNS_NEVER_SPDIF */
+
+ /* Register read - to make sure uCPU has finished writing the register. */
+ regTransfer.addr = offsetof(MHDP_ApbRegs, mhdp_apb_regs.mhdp_clock_meter[0].CM_CTRL_p);
+ regTransfer.addr += streamId * (uint32_t)sizeof(pD->regBase->mhdp_apb_regs.mhdp_clock_meter[0]);
+ return DP_ReadRegister(pD, ®Transfer);
+}
+
+uint32_t DP_AudioAutoConfig(DP_PrivateData* pD, uint8_t streamId, const DP_AudioParams* params)
+{
+ const uint32_t audioTsVersion = 0x11U; /* Audio timestamp version */
+ const uint32_t referenceCycles = 0x8000U;
+ uint32_t retVal;
+
+ retVal = DP_AudioAutoConfigSF(pD, params);
+ if (CDN_EOK == retVal)
+ {
+ retVal = DP_StreamIdMstSstSanity(pD, streamId);
+ }
+
+ if (CDN_EOK == retVal)
+ {
+ retVal = setAudioPackStatus(pD, streamId, audioTsVersion);
+ }
+
+ if (CDN_EOK == retVal)
+ {
+ retVal = setCmLaneCtrl(pD, streamId, referenceCycles);
+ }
+
+ if (CDN_EOK == retVal)
+ {
+ retVal = DP_AudioSetMode(pD, streamId, DP_AUDIO_MODE_ON);
+ }
+
+ if (CDN_EOK == retVal)
+ {
+ retVal = setCmLaneCtrl(pD, streamId, referenceCycles);
+ }
+
+#ifdef CDNS_NEVER_SPDIF
+ if ((CDN_EOK == retVal) && (DP_AUDIO_TYPE_I2S != params->type))
+ {
+ DP_RegisterTransfer regTransfer = {0U};
+ /* TODO: Handle CAR correctly */
+ regTransfer.addr = offsetof(MHDP_ApbRegs, mhdp_apb_regs.source_aif_car_p);
+ regTransfer.val = 0xFFU;
+ retVal = DP_WriteRegister(pD, ®Transfer);
+ }
+#endif /* CDNS_NEVER_SPDIF */
+
+ if (CDN_EOK == retVal)
+ {
+ retVal = setCmLaneCtrl(pD, streamId, 0U);
+ }
+
+ if (CDN_EOK == retVal)
+ {
+ retVal = configAudioCore(pD, streamId, params);
+ }
+
+ return retVal;
+}
+
+static void resetAudioSrcCntlRegister(const DP_PrivateData* pD, uint8_t streamId)
+{
+ struct MHDP_ApbRegs_s *mhdpApbReg = pD->regBase;
+
+ CPS_REG_WRITE(&mhdpApbReg->mhdp_apb_regs.mhdp_audio_decoder[streamId].AUDIO_SRC_CNTL_p, 0U);
+
+ CPS_REG_WRITE(&mhdpApbReg->mhdp_apb_regs.mhdp_audio_decoder[streamId].AUDIO_SRC_CNTL_p,
+ CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__AUDIO_SRC_CNTL_P, SW_RST, 0U, 0x1U));
+
+ CPS_REG_WRITE(&mhdpApbReg->mhdp_apb_regs.mhdp_audio_decoder[streamId].AUDIO_SRC_CNTL_p, 0U);
+}
+
+static void resetSmpl2PktCntlRegister(const DP_PrivateData* pD, uint8_t streamId)
+{
+ struct MHDP_ApbRegs_s *mhdpApbReg = pD->regBase;
+
+ CPS_REG_WRITE(&mhdpApbReg->mhdp_apb_regs.mhdp_audio_decoder[streamId].SMPL2PKT_CNTL_p, 0U);
+
+ CPS_REG_WRITE(&mhdpApbReg->mhdp_apb_regs.mhdp_audio_decoder[streamId].SMPL2PKT_CNTL_p,
+ CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SMPL2PKT_CNTL_P, SW_RST, 0U, 0x1U));
+
+ CPS_REG_WRITE(&mhdpApbReg->mhdp_apb_regs.mhdp_audio_decoder[streamId].SMPL2PKT_CNTL_p, 0U);
+
+}
+
+static void resetFifoCntlRegister(const DP_PrivateData* pD, uint8_t streamId)
+{
+ struct MHDP_ApbRegs_s *mhdpApbReg = pD->regBase;
+
+ CPS_REG_WRITE(&mhdpApbReg->mhdp_apb_regs.mhdp_audio_decoder[streamId].FIFO_CNTL_p, 0U);
+
+ CPS_REG_WRITE(&mhdpApbReg->mhdp_apb_regs.mhdp_audio_decoder[streamId].FIFO_CNTL_p,
+ CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__FIFO_CNTL_P, FIFO_SW_RST, 0U, 0x1U));
+
+ CPS_REG_WRITE(&mhdpApbReg->mhdp_apb_regs.mhdp_audio_decoder[streamId].FIFO_CNTL_p, 0U);
+
+}
+
+#ifdef CDNS_NEVER_SPDIF
+static void resetSpdifCtrlAddrRegister(const DP_PrivateData* pD, uint8_t streamId) {
+
+/* Can be called as part of resetAudioRegisters */
+ uint32_t reg = CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CTRL_ADDR_P, SPDIF_JITTER_AVG_WIN, 0U, 0x7U)
+ | CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CTRL_ADDR_P, SPDIF_JITTER_THRSH, 0U, 0xE0U)
+ | CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CTRL_ADDR_P, SPDIF_FIFO_MID_RANGE, 0U, 0xE0U)
+ | CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CTRL_ADDR_P, SPDIF_JITTER_BYPASS, 0U, 0x1U)
+ | CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CTRL_ADDR_P, SPDIF_AVG_SEL, 0U, 0x1U)
+ | CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CTRL_ADDR_P, SPDIF_ENABLE, 0U, 0x0U);
+
+ CPS_REG_WRITE(&pD->regBase->mhdp_apb_regs.mhdp_audio_decoder[streamId].SPDIF_CTRL_ADDR_p, reg);
+
+}
+#endif /* CDNS_NEVER_SPDIF */
+
+static void resetAudioSrcCnfgRegister(const DP_PrivateData* pD, uint8_t streamId) {
+ CPS_REG_WRITE(&pD->regBase->mhdp_apb_regs.mhdp_audio_decoder[streamId].AUDIO_SRC_CNFG_p, 0U);
+}
+
+static void resetAudioRegisters(const DP_PrivateData* pD, uint8_t streamId)
+{
+ static void (*resetRegister[]) (const DP_PrivateData*, uint8_t) = {
+ resetAudioSrcCnfgRegister,
+#ifdef CDNS_NEVER_SPDIF
+ resetSpdifCtrlAddrRegister,
+#endif /* CDNS_NEVER_SPDIF */
+ resetAudioSrcCntlRegister,
+ resetSmpl2PktCntlRegister,
+ resetFifoCntlRegister
+ };
+
+ uint8_t i;
+ static uint8_t count = (uint8_t)(sizeof(resetRegister) / sizeof(resetRegister[0]));
+ for (i = 0U; i < count; i++) {
+ resetRegister[i](pD, streamId);
+ }
+}
+
+uint32_t DP_AudioStop(DP_PrivateData* pD, uint8_t streamId)
+{
+ uint32_t retVal;
+ DP_RegisterTransfer regTransfer = {0U};
+
+ retVal = DP_AudioStopSF(pD);
+ if (CDN_EOK == retVal)
+ {
+ retVal = DP_StreamIdMstSstSanity(pD, streamId);
+ }
+
+ if (CDN_EOK == retVal)
+ {
+
+ resetAudioRegisters(pD, streamId);
+
+ /* TODO: Handle CAR correctly. */
+ regTransfer.addr = offsetof(MHDP_ApbRegs, mhdp_apb_regs.source_aif_car_p);
+ regTransfer.val = 0x5FU;
+ retVal = DP_WriteRegister(pD, ®Transfer);
+ }
+
+ if (CDN_EOK == retVal)
+ {
+ regTransfer.addr = offsetof(MHDP_ApbRegs, mhdp_apb_regs.source_aif_car_p);
+ regTransfer.val = 0x0FU;
+ retVal = DP_WriteRegister(pD, ®Transfer);
+ }
+
+ if (CDN_EOK == retVal)
+ {
+ /* Register read - to make sure uCPU has finished writing the register. */
+ retVal = DP_ReadRegister(pD, ®Transfer);
+ }
+
+ return retVal;
+}
diff --git a/packages/ti/drv/dss/src/csl/dp/src/dp_aux.c b/packages/ti/drv/dss/src/csl/dp/src/dp_aux.c
--- /dev/null
@@ -0,0 +1,88 @@
+/* parasoft-begin-suppress METRICS-41 "Number of comments before and inside functions" */
+/******************************************************************************
+ *
+ * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ *
+ * dp_aux.c
+ *
+ ******************************************************************************
+ */
+
+#include <cdn_errno.h>
+#include "dp_aux.h"
+#include "dp_if.h"
+#include "dp_structs_if.h"
+#include "cps.h"
+#include "dp_aux_if.h"
+#include "dp_aux_structs_if.h"
+
+uint32_t drm_dp_dpcd_read(AUX_drm_dp *aux, uint32_t offset,
+ uint8_t *buffer, size_t size) {
+ uint32_t retVal = CDN_EOK;
+
+ DP_DpcdTransfer transfer = {0};
+
+ transfer.size = (uint16_t) size;
+ transfer.addr = offset;
+ transfer.buff = buffer;
+
+ retVal = DP_ReadDpcd(aux->pD, &transfer);
+ if (retVal != CDN_EOK) {
+ DbgMsg(DBG_GEN_MSG, DBG_CRIT, "Reading DPCD register failed\n");
+ }
+
+ return retVal;
+}
+
+uint32_t drm_dp_dpcd_write(AUX_drm_dp *aux, uint32_t offset,
+ uint8_t *buffer, size_t size) {
+ uint32_t retVal = CDN_EOK;
+
+ DP_DpcdTransfer transfer = { 0 };
+ transfer.size = (uint16_t) size;
+ transfer.addr = offset;
+ transfer.buff = buffer;
+
+ retVal = DP_WriteDpcd(aux->pD, &transfer);
+ if (retVal != CDN_EOK) {
+ DbgMsg(DBG_GEN_MSG, DBG_CRIT, "Writing DPCD register failed\n");
+ }
+
+ return retVal;
+}
+
+uint32_t drm_dp_dpcd_read_byte(AUX_drm_dp *aux, uint32_t offset,
+ uint8_t *value) {
+ return drm_dp_dpcd_read(aux, offset, value, 1U);
+}
+
+uint32_t drm_dp_dpcd_write_byte(AUX_drm_dp *aux, uint32_t offset,
+ uint8_t value) {
+ return drm_dp_dpcd_write(aux, offset, &value, 1U);
+}
diff --git a/packages/ti/drv/dss/src/csl/dp/src/dp_aux.h b/packages/ti/drv/dss/src/csl/dp/src/dp_aux.h
--- /dev/null
@@ -0,0 +1,58 @@
+/* parasoft-begin-suppress METRICS-36 "Function called from more than 5 functions" */
+/* parasoft-begin-suppress MISRA2012-DIR-4_8 "Hidden implementation when never dereferenced structure" */
+/******************************************************************************
+ *
+ * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ *
+ * dp_aux.h
+ *
+ ******************************************************************************
+ */
+
+#ifndef DP_AUX_H
+#define DP_AUX_H
+
+#include <cdn_stdtypes.h>
+#include "dp_if.h"
+#include "cdn_log.h"
+#include "dp_aux_if.h"
+
+uint32_t drm_dp_dpcd_read(AUX_drm_dp *aux, uint32_t offset,
+ uint8_t *buffer, size_t size);
+
+uint32_t drm_dp_dpcd_write(AUX_drm_dp *aux, uint32_t offset,
+ uint8_t *buffer, size_t size);
+
+uint32_t drm_dp_dpcd_read_byte(AUX_drm_dp *aux, uint32_t offset,
+ uint8_t *value);
+
+uint32_t drm_dp_dpcd_write_byte(AUX_drm_dp *aux, uint32_t offset,
+ uint8_t value);
+
+#endif
diff --git a/packages/ti/drv/dss/src/csl/dp/src/dp_demotb.h b/packages/ti/drv/dss/src/csl/dp/src/dp_demotb.h
--- /dev/null
@@ -0,0 +1,50 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ *
+ * dp_demotb.h
+ *
+ ******************************************************************************
+ */
+
+#ifndef DP_DEMOTB_H
+#define DP_DEMOTB_H
+
+typedef struct DP_DemoTb_s DP_DemoTb;
+
+struct DP_DemoTb_s
+{
+ /** Disable sending sideband messages through AUX channel */
+ bool disableMessaging;
+
+ /** Inject requested number as VCPI */
+ uint8_t requestedVcpi;
+};
+
+#endif
diff --git a/packages/ti/drv/dss/src/csl/dp/src/dp_dsc.c b/packages/ti/drv/dss/src/csl/dp/src/dp_dsc.c
--- /dev/null
@@ -0,0 +1,773 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ *
+ * dp_dsc.c
+ *
+ ******************************************************************************
+ */
+
+/* parasoft-begin-suppress METRICS-41 "Number of blocks of comments per statement in the function" */
+
+#include "dp_if.h"
+#include "dp_dsc.h"
+#include "dp_priv.h"
+#include "dsc_utils.h"
+#include "dp_register.h"
+
+#include "mhdp_apb_regs.h"
+#include "cps_drv.h"
+
+/* Output Buffer (max pointer address)
+ * For 8k max in split mode, 4K per Hard Slice
+ * use 3667U value
+ *
+ * For 4k max in split mode, 2K per Hard Slice
+ * use 1885U value
+ */
+
+#define DSC_OUTPUT_BUFFER_MAX_ADDRESS 3667U
+
+#define DSC_CFG_READ_WRITE_FUNC_NUM 16U
+#define DSC_BPG_OFFSET_SIGN_MASK 0x20U
+#define DSC_BGP_OFFSET_MASK 0x3FU
+
+static volatile uint32_t* getEncAddress(const DP_PrivateData* pD, uint8_t encIdx) {
+
+ volatile uint32_t* retVal;
+ if (encIdx == 1U) {
+ retVal = &pD->regBase->mhdp_apb_regs.ENC1_MAIN_CONF_p;
+ } else {
+ retVal = &pD->regBase->mhdp_apb_regs.ENC0_MAIN_CONF_p;
+ }
+ return retVal;
+}
+
+static void writeMainConf(const DP_PrivateData* pD, const DP_DscConfigFull* dscCfg){
+
+ uint32_t splitPanel = 0U;
+ uint32_t reg;
+
+ if (dscCfg->splitPanel) {
+ splitPanel = 1U;
+ }
+
+ reg = CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__COM_MAIN_CONF_P, REGS_SPLIT_PANEL, 0U, splitPanel)
+ | CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__COM_MAIN_CONF_P, REGS_MULTIPLEX_MODE, 0U, splitPanel)
+ | CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__COM_MAIN_CONF_P, REGS_MULTIPLEX_SEL_OUT, 0U, 0U)
+ | CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__COM_MAIN_CONF_P, REGS_DE_RASTER_ENABLE, 0U, 0U)
+ | CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__COM_MAIN_CONF_P, INPUT_MODE, 0U, 1U)
+ | CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__COM_MAIN_CONF_P, MULTIPLEX_MODE_EOC_ENABLE, 0U, 1U)
+ | CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__COM_MAIN_CONF_P, AUTO_REGS_DB_UPDATE, 0U, 0U);
+
+ CPS_REG_WRITE(&pD->regBase->mhdp_apb_regs.COM_MAIN_CONF_p, reg);
+}
+
+/*
+ *****************************************************************************************************************
+ * Create write functions for each ENC configuration register
+ *****************************************************************************************************************
+ */
+static void writeEncMainConf(volatile uint32_t** regAddress, const DP_DscConfigFull *dscCfg) {
+
+ uint32_t reg = 0U;
+
+ if (dscCfg->bitsPerComponent != 8U) {
+ reg = CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__ENC0_MAIN_CONF_P, INPUT_BPC, 0U, 1U);
+ }
+
+ reg |= CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__ENC0_MAIN_CONF_P, CONVERT_RGB, 0U, dscCfg->convertRgb)
+ | CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__ENC0_MAIN_CONF_P, ENABLE_422, 0U, 0U)
+ | CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__ENC0_MAIN_CONF_P, LINEBUF_DEPTH, 0U, dscCfg->linebufDepth)
+ | CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__ENC0_MAIN_CONF_P, BITS_PER_PIXEL, 0U, dscCfg->bitsPerPixel)
+ | CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__ENC0_MAIN_CONF_P, BLOCK_PRED_ENABLE, 0U, dscCfg->blockPredEnable)
+ | CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__ENC0_MAIN_CONF_P, VIDEO_MODE, 0U, 1U)
+ | CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__ENC0_MAIN_CONF_P, ICH_RST_EOL, 0U, 0U)
+ | CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__ENC0_MAIN_CONF_P, INITIAL_LINES, 0U, dscCfg->initialLines);
+
+ CPS_REG_WRITE(*regAddress, reg);
+}
+
+static void writeEncPictureSize(volatile uint32_t** regAddress, const DP_DscConfigFull *dscCfg) {
+
+ uint32_t reg;
+
+ reg = CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__ENC0_PICTURE_SIZE_P, PICTURE_WIDTH, 0U, dscCfg->picWidth)
+ | CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__ENC0_PICTURE_SIZE_P, PICTURE_HEIGHT, 0U, dscCfg->picHeight);
+
+ CPS_REG_WRITE(*regAddress, reg);
+}
+
+static void writeEncSliceWidth (volatile uint32_t** regAddress, const DP_DscConfigFull *dscCfg){
+
+ uint32_t reg;
+
+ reg = CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__ENC0_SLICE_SIZE_P, SLICE_WIDTH, 0U, dscCfg->sliceWidth)
+ | CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__ENC0_SLICE_SIZE_P, SLICE_HEIGHT, 0U, dscCfg->sliceHeight);
+
+ CPS_REG_WRITE(*regAddress, reg);
+}
+
+static void writeEncMiscSize(volatile uint32_t** regAddress, const DP_DscConfigFull *dscCfg) {
+
+ uint32_t reg;
+ uint32_t sliceWidth = ((uint32_t)dscCfg->sliceWidth + 2U) % 3U;
+
+ reg = CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__ENC0_MISC_SIZE_P, SLICE_LAST_GROUP_SIZE, 0U, sliceWidth)
+ | CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__ENC0_MISC_SIZE_P, OB_MAX_ADDR, 0U, DSC_OUTPUT_BUFFER_MAX_ADDRESS)
+ | CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__ENC0_MISC_SIZE_P, CHUNK_SIZE, 0U, dscCfg->chunkSize);
+
+ CPS_REG_WRITE(*regAddress, reg);
+}
+
+static void writeEncHrdDelays(volatile uint32_t** regAddress, const DP_DscConfigFull *dscCfg) {
+
+ uint32_t reg;
+
+ reg = CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__ENC0_HRD_DELAYS_P, INITIAL_XMIT_DELAY, 0U, dscCfg->initialXmitDelay)
+ | CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__ENC0_HRD_DELAYS_P, INITIAL_DEC_DELAY, 0U, dscCfg->initialDecDelay);
+
+ CPS_REG_WRITE(*regAddress, reg);
+}
+
+static void writeEncRcScale(volatile uint32_t** regAddress, const DP_DscConfigFull *dscCfg) {
+
+ uint32_t reg;
+
+ reg = CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__ENC0_RC_SCALE_P, INITIAL_SCALE_VALUE, 0U, dscCfg->initialScaleValue);
+
+ CPS_REG_WRITE(*regAddress, reg);
+}
+
+static void writeEncRcScaleIncDec(volatile uint32_t** regAddress, const DP_DscConfigFull *dscCfg) {
+
+ uint32_t reg;
+
+ reg = CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__ENC0_RC_SCALE_INC_DEC_P, SCALE_INCREMENT_INTERVAL, 0U, dscCfg->scaleIncrementInterval)
+ | CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__ENC0_RC_SCALE_INC_DEC_P, SCALE_DECREMENT_INTERVAL, 0U, dscCfg->scaleDecrementInterval);
+
+ CPS_REG_WRITE(*regAddress, reg);
+}
+
+static void writeEncRcOffsets(volatile uint32_t** regAddress, const DP_DscConfigFull *dscCfg) {
+
+ uint32_t reg;
+
+ reg = CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__ENC0_RC_OFFSETS_1_P, FIRST_LINE_BPG_OFFSET, 0U, dscCfg->firstLineBpgOfs);
+ CPS_REG_WRITE(*regAddress, reg);
+ (*regAddress)++;
+
+ reg = CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__ENC0_RC_OFFSETS_2_P, NFL_BPG_OFFSET, 0U, dscCfg->nflBpgOffset)
+ | CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__ENC0_RC_OFFSETS_2_P, SLICE_BPG_OFFSET, 0U, dscCfg->sliceBpgOffset);
+ CPS_REG_WRITE(*regAddress, reg);
+ (*regAddress)++;
+
+ reg = CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__ENC0_RC_OFFSETS_3_P, INITIAL_OFFSET, 0U, dscCfg->initialOffset)
+ | CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__ENC0_RC_OFFSETS_3_P, FINAL_OFFSET, 0U, dscCfg->finalOffset);
+ CPS_REG_WRITE(*regAddress, reg);
+}
+
+static void writeEncFlatnessDetection(volatile uint32_t** regAddress, const DP_DscConfigFull *dscCfg) {
+
+ uint32_t reg;
+
+ reg = CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__ENC0_FLATNESS_DETECTION_P, FLATNESS_MIN_QP, 0U, dscCfg->flatnessMinQp)
+ | CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__ENC0_FLATNESS_DETECTION_P, FLATNESS_MAX_QP, 0U, dscCfg->flatnessMaxQp)
+ | CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__ENC0_FLATNESS_DETECTION_P, FLATNESS_DET_THRESH, 0U, dscCfg->flatnessDetThresh);
+
+ CPS_REG_WRITE(*regAddress, reg);
+}
+
+static void writeEncModelSize(volatile uint32_t** regAddress, const DP_DscConfigFull *dscCfg) {
+
+ uint32_t reg;
+
+ reg = CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__ENC0_RC_MODEL_SIZE_P, RC_MODEL_SIZE, 0U, dscCfg->rcModelSize);
+
+ CPS_REG_WRITE(*regAddress, reg);
+}
+
+static void writeEncRcConfig(volatile uint32_t** regAddress, const DP_DscConfigFull *dscCfg) {
+
+ uint32_t reg;
+
+ reg = CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__ENC0_RC_CONFIG_P, RC_EDGE_FACTOR, 0U, dscCfg->rcEdgeFactor)
+ | CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__ENC0_RC_CONFIG_P, RC_QUANT_INCR_LIMIT0, 0U, dscCfg->rcQuantIncrLimit0)
+ | CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__ENC0_RC_CONFIG_P, RC_QUANT_INCR_LIMIT1, 0U, dscCfg->rcQuantIncrLimit1)
+ | CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__ENC0_RC_CONFIG_P, RC_TGT_OFFSET_HI, 0U, dscCfg->rcTgtOffsetHi)
+ | CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__ENC0_RC_CONFIG_P, RC_TGT_OFFSET_LO, 0U, dscCfg->rcTgtOffsetLo);
+
+ CPS_REG_WRITE(*regAddress, reg);
+}
+
+static void writeEncRcBufThresh(volatile uint32_t** regAddress, const DP_DscConfigFull *dscCfg) {
+
+ uint32_t reg;
+ uint8_t i;
+ uint8_t index;
+
+ /* each BUF_THRESH buffer have same masks and shifts */
+ for (i = 0U; i < 3U; i++) {
+ index = 4U * i;
+ reg = CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__ENC0_RC_BUF_THRESH_0_P, RC_BUF_THRESH_0, 0U, (dscCfg->rcBufThresh[index] >> 6U))
+ | CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__ENC0_RC_BUF_THRESH_0_P, RC_BUF_THRESH_1, 0U, (dscCfg->rcBufThresh[index + 1U] >> 6U))
+ | CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__ENC0_RC_BUF_THRESH_0_P, RC_BUF_THRESH_2, 0U, (dscCfg->rcBufThresh[index + 2U] >> 6U))
+ | CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__ENC0_RC_BUF_THRESH_0_P, RC_BUF_THRESH_3, 0U, (dscCfg->rcBufThresh[index + 3U] >> 6U));
+
+ CPS_REG_WRITE(*regAddress, reg);
+ (*regAddress)++;
+ }
+
+ reg = CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__ENC0_RC_BUF_THRESH_3_P, RC_BUF_THRESH_12, 0U, (dscCfg->rcBufThresh[12] >> 6U))
+ | CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__ENC0_RC_BUF_THRESH_3_P, RC_BUF_THRESH_13, 0U, (dscCfg->rcBufThresh[13] >> 6U));
+
+ CPS_REG_WRITE(*regAddress, reg);
+}
+
+static void writeEncRcMinQp(volatile uint32_t** regAddress, const DP_DscConfigFull *dscCfg) {
+
+ uint32_t reg;
+ uint8_t i;
+ uint8_t index;
+
+ /* each RANGE_MIN buffer have same masks and shifts */
+ for (i = 0U; i < 3U; i++) {
+ index = i * 5U;
+ reg = CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__ENC0_RC_MIN_QP_0_P, RANGE_MIN_QP_0, 0U, dscCfg->rcRangeParameters[index].rangeMinQp)
+ | CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__ENC0_RC_MIN_QP_0_P, RANGE_MIN_QP_1, 0U, dscCfg->rcRangeParameters[index + 1U].rangeMinQp)
+ | CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__ENC0_RC_MIN_QP_0_P, RANGE_MIN_QP_2, 0U, dscCfg->rcRangeParameters[index + 2U].rangeMinQp)
+ | CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__ENC0_RC_MIN_QP_0_P, RANGE_MIN_QP_3, 0U, dscCfg->rcRangeParameters[index + 3U].rangeMinQp)
+ | CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__ENC0_RC_MIN_QP_0_P, RANGE_MIN_QP_4, 0U, dscCfg->rcRangeParameters[index + 4U].rangeMinQp);
+
+ CPS_REG_WRITE(*regAddress, reg);
+ if (2U != i) {
+ (*regAddress)++;
+ }
+ }
+}
+
+static void writeEncRcMaxQp(volatile uint32_t** regAddress, const DP_DscConfigFull *dscCfg) {
+
+ uint32_t reg;
+ uint8_t i;
+ uint8_t index;
+
+ /* each RANGE_MAX buffer have same masks and shifts */
+ for (i = 0U; i < 3U; i++) {
+ index = 5U * i;
+ reg = CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__ENC0_RC_MAX_QP_0_P, RANGE_MAX_QP_0, 0U, dscCfg->rcRangeParameters[index].rangeMaxQp)
+ | CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__ENC0_RC_MAX_QP_0_P, RANGE_MAX_QP_1, 0U, dscCfg->rcRangeParameters[index + 1U].rangeMaxQp)
+ | CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__ENC0_RC_MAX_QP_0_P, RANGE_MAX_QP_2, 0U, dscCfg->rcRangeParameters[index + 2U].rangeMaxQp)
+ | CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__ENC0_RC_MAX_QP_0_P, RANGE_MAX_QP_3, 0U, dscCfg->rcRangeParameters[index + 3U].rangeMaxQp)
+ | CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__ENC0_RC_MAX_QP_0_P, RANGE_MAX_QP_4, 0U, dscCfg->rcRangeParameters[index + 4U].rangeMaxQp);
+
+ CPS_REG_WRITE(*regAddress, reg);
+ if (2U != i) {
+ (*regAddress)++;
+ }
+ }
+}
+
+static void writeEncRcRangeBpgOffsets(volatile uint32_t** regAddress, const DP_DscConfigFull *dscCfg) {
+
+ uint32_t reg;
+ uint8_t i;
+ uint8_t index;
+
+ /* each RANGE_BPG_OFFSET buffer have same masks and shifts */
+ for (i = 0U; i < 3U; i++) {
+ index = 5U * i;
+ reg = CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__ENC0_RC_RANGE_BPG_OFFSETS_0_P, RANGE_BPG_OFFSET_0, 0U, dscCfg->rcRangeParameters[index].rangeBpgOffset)
+ | CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__ENC0_RC_RANGE_BPG_OFFSETS_0_P, RANGE_BPG_OFFSET_1, 0U, dscCfg->rcRangeParameters[index + 1U].rangeBpgOffset)
+ | CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__ENC0_RC_RANGE_BPG_OFFSETS_0_P, RANGE_BPG_OFFSET_2, 0U, dscCfg->rcRangeParameters[index + 2U].rangeBpgOffset)
+ | CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__ENC0_RC_RANGE_BPG_OFFSETS_0_P, RANGE_BPG_OFFSET_3, 0U, dscCfg->rcRangeParameters[index + 3U].rangeBpgOffset)
+ | CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__ENC0_RC_RANGE_BPG_OFFSETS_0_P, RANGE_BPG_OFFSET_4, 0U, dscCfg->rcRangeParameters[index + 4U].rangeBpgOffset);
+
+ CPS_REG_WRITE(*regAddress, reg);
+ if (2U != i) {
+ (*regAddress)++;
+ }
+ }
+}
+
+static void writeEncDpiCtrlOutDelay(volatile uint32_t** regAddress, const DP_DscConfigFull *dscCfg) {
+
+ uint32_t reg;
+ uint32_t regVal = (dscCfg->initialLines * dscCfg->hTotal);
+
+ reg = CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__ENC0_DPI_CTRL_OUT_DELAY_P, DPI_CTRL_OUT_DELAY, 0U, regVal);
+
+ CPS_REG_WRITE(*regAddress, reg);
+}
+/*
+ **************************************************************************************************************************
+ * End of write functions section
+ **************************************************************************************************************************
+ */
+
+static void writeEncConf(const DP_PrivateData* pD, const DP_DscConfigFull *dscCfg, uint8_t encIdx)
+{
+ /* Array with pointers to write functions */
+ void (*writeCfg[DSC_CFG_READ_WRITE_FUNC_NUM]) (volatile uint32_t * *, const DP_DscConfigFull*) = {
+ writeEncMainConf,
+ writeEncPictureSize,
+ writeEncSliceWidth,
+ writeEncMiscSize,
+ writeEncHrdDelays,
+ writeEncRcScale,
+ writeEncRcScaleIncDec,
+ writeEncRcOffsets,
+ writeEncFlatnessDetection,
+ writeEncModelSize,
+ writeEncRcConfig,
+ writeEncRcBufThresh,
+ writeEncRcMinQp,
+ writeEncRcMaxQp,
+ writeEncRcRangeBpgOffsets,
+ writeEncDpiCtrlOutDelay
+ };
+
+ volatile uint32_t** actualRegAddress;
+ volatile uint32_t* firstRegAddress;
+ uint8_t i;
+
+ firstRegAddress = getEncAddress(pD, encIdx);
+ actualRegAddress = &firstRegAddress;
+
+ for (i = 0U; i < DSC_CFG_READ_WRITE_FUNC_NUM; i++) {
+ (*writeCfg[i])(actualRegAddress, dscCfg);
+ (*actualRegAddress)++;
+ }
+
+}
+
+uint32_t DP_DscWriteConfiguration(const DP_PrivateData* pD, const DP_DscConfigFull *dscCfg, uint8_t streamId)
+{
+ writeMainConf(pD, dscCfg);
+ writeEncConf(pD, dscCfg, streamId);
+
+ /* if split panel mode enabled then write the same configuration to the second
+ * encoder */
+ if (dscCfg->splitPanel) {
+ writeEncConf(pD, dscCfg, 1U);
+ }
+
+ return CDN_EOK;
+}
+
+static void extendSignedInt(int32_t *value)
+{
+ uint32_t tempValue = (uint32_t)*value;
+
+ if ((tempValue & DSC_BPG_OFFSET_SIGN_MASK) != 0U) {
+ tempValue |= ~DSC_BGP_OFFSET_MASK;
+ *value = (int32_t)tempValue;
+ }
+
+}
+
+static void readMainConf(const DP_PrivateData* pD, DP_DscConfigFull* dscCfg) {
+
+ uint32_t reg;
+
+ reg = CPS_REG_READ(&pD->regBase->mhdp_apb_regs.COM_MAIN_CONF_p);
+
+ dscCfg->splitPanel = (0U != CPS_FLD_READ(MHDP__MHDP_APB_REGS__COM_MAIN_CONF_P, REGS_SPLIT_PANEL, reg));
+}
+
+/*
+ * *********************************************************************************************************
+ * Create read functions for each register
+ * *********************************************************************************************************
+ */
+
+static void readEncMainConf(volatile uint32_t** regAddress, DP_DscConfigFull *dscCfg) {
+
+ uint32_t reg;
+ uint32_t bitsPerComponent;
+
+ reg = CPS_REG_READ(*regAddress);
+ bitsPerComponent = CPS_FLD_READ(MHDP__MHDP_APB_REGS__ENC0_MAIN_CONF_P, INPUT_BPC, reg);
+
+ if (bitsPerComponent == 0U) {
+ dscCfg->bitsPerComponent = 8U;
+ } else {
+ dscCfg->bitsPerComponent = 10U;
+ }
+
+ dscCfg->convertRgb = CPS_FLD_READ(MHDP__MHDP_APB_REGS__ENC0_MAIN_CONF_P, CONVERT_RGB, reg);
+ dscCfg->linebufDepth = CPS_FLD_READ(MHDP__MHDP_APB_REGS__ENC0_MAIN_CONF_P, LINEBUF_DEPTH, reg);
+ dscCfg->bitsPerPixel = CPS_FLD_READ(MHDP__MHDP_APB_REGS__ENC0_MAIN_CONF_P, BITS_PER_PIXEL, reg);
+ dscCfg->blockPredEnable = CPS_FLD_READ(MHDP__MHDP_APB_REGS__ENC0_MAIN_CONF_P, BLOCK_PRED_ENABLE, reg);
+ dscCfg->initialLines = CPS_FLD_READ(MHDP__MHDP_APB_REGS__ENC0_MAIN_CONF_P, INITIAL_LINES, reg);
+}
+
+static void readEncPictureSize(volatile uint32_t** regAddress, DP_DscConfigFull *dscCfg) {
+
+ uint32_t reg;
+
+ reg = CPS_REG_READ(*regAddress);
+
+ dscCfg->picWidth = CPS_FLD_READ(MHDP__MHDP_APB_REGS__ENC0_PICTURE_SIZE_P, PICTURE_WIDTH, reg);
+ dscCfg->picHeight = CPS_FLD_READ(MHDP__MHDP_APB_REGS__ENC0_PICTURE_SIZE_P, PICTURE_HEIGHT, reg);
+}
+
+static void readEncSliceWidth (volatile uint32_t** regAddress, DP_DscConfigFull *dscCfg){
+
+ uint32_t reg;
+
+ reg = CPS_REG_READ(*regAddress);
+
+ dscCfg->sliceWidth = CPS_FLD_READ(MHDP__MHDP_APB_REGS__ENC0_SLICE_SIZE_P, SLICE_WIDTH, reg);
+ dscCfg->sliceHeight = CPS_FLD_READ(MHDP__MHDP_APB_REGS__ENC0_SLICE_SIZE_P, SLICE_HEIGHT, reg);
+}
+
+static void readEncMiscSize(volatile uint32_t** regAddress, DP_DscConfigFull *dscCfg) {
+
+ uint32_t reg;
+
+ reg = CPS_REG_READ(*regAddress);
+
+ dscCfg->chunkSize = CPS_FLD_READ(MHDP__MHDP_APB_REGS__ENC0_MISC_SIZE_P, CHUNK_SIZE, reg);
+
+}
+
+static void readEncHrdDelays(volatile uint32_t** regAddress, DP_DscConfigFull *dscCfg) {
+
+ uint32_t reg;
+
+ reg = CPS_REG_READ(*regAddress);
+
+ dscCfg->initialXmitDelay = CPS_FLD_READ(MHDP__MHDP_APB_REGS__ENC0_HRD_DELAYS_P, INITIAL_XMIT_DELAY, reg);
+ dscCfg->initialDecDelay = CPS_FLD_READ(MHDP__MHDP_APB_REGS__ENC0_HRD_DELAYS_P, INITIAL_DEC_DELAY, reg);
+}
+
+static void readEncRcScale(volatile uint32_t** regAddress, DP_DscConfigFull *dscCfg) {
+
+ uint32_t reg;
+
+ reg = CPS_REG_READ(*regAddress);
+
+ dscCfg->initialScaleValue = CPS_FLD_READ(MHDP__MHDP_APB_REGS__ENC0_RC_SCALE_P, INITIAL_SCALE_VALUE, reg);
+}
+
+static void readEncRcScaleIncDec(volatile uint32_t** regAddress, DP_DscConfigFull *dscCfg) {
+
+ uint32_t reg;
+
+ reg = CPS_REG_READ(*regAddress);
+
+ dscCfg->scaleIncrementInterval = CPS_FLD_READ(MHDP__MHDP_APB_REGS__ENC0_RC_SCALE_INC_DEC_P, SCALE_INCREMENT_INTERVAL, reg);
+ dscCfg->scaleDecrementInterval = CPS_FLD_READ(MHDP__MHDP_APB_REGS__ENC0_RC_SCALE_INC_DEC_P, SCALE_DECREMENT_INTERVAL, reg);
+
+}
+
+static void readEncRcOffsets(volatile uint32_t** regAddress, DP_DscConfigFull *dscCfg) {
+
+ uint32_t reg;
+
+ reg = CPS_REG_READ(*regAddress);
+ dscCfg->firstLineBpgOfs = CPS_FLD_READ(MHDP__MHDP_APB_REGS__ENC0_RC_OFFSETS_1_P, FIRST_LINE_BPG_OFFSET, reg);
+ (*regAddress)++;
+
+ reg = CPS_REG_READ(*regAddress);
+ dscCfg->nflBpgOffset = CPS_FLD_READ(MHDP__MHDP_APB_REGS__ENC0_RC_OFFSETS_2_P, NFL_BPG_OFFSET, reg);
+ dscCfg->sliceBpgOffset = CPS_FLD_READ(MHDP__MHDP_APB_REGS__ENC0_RC_OFFSETS_2_P, SLICE_BPG_OFFSET, reg);
+ (*regAddress)++;
+
+ reg = CPS_REG_READ(*regAddress);
+ dscCfg->initialOffset = CPS_FLD_READ(MHDP__MHDP_APB_REGS__ENC0_RC_OFFSETS_3_P, INITIAL_OFFSET, reg);
+ dscCfg->finalOffset = CPS_FLD_READ(MHDP__MHDP_APB_REGS__ENC0_RC_OFFSETS_3_P, FINAL_OFFSET, reg);
+}
+
+static void readEncFlatnessDetection(volatile uint32_t** regAddress, DP_DscConfigFull *dscCfg) {
+
+ uint32_t reg;
+
+ reg = CPS_REG_READ(*regAddress);
+
+ dscCfg->flatnessMinQp = CPS_FLD_READ(MHDP__MHDP_APB_REGS__ENC0_FLATNESS_DETECTION_P, FLATNESS_MIN_QP, reg);
+ dscCfg->flatnessMaxQp = CPS_FLD_READ(MHDP__MHDP_APB_REGS__ENC0_FLATNESS_DETECTION_P, FLATNESS_MAX_QP, reg);
+ dscCfg->flatnessDetThresh = CPS_FLD_READ(MHDP__MHDP_APB_REGS__ENC0_FLATNESS_DETECTION_P, FLATNESS_DET_THRESH, reg);
+}
+
+static void readEncModelSize(volatile uint32_t** regAddress, DP_DscConfigFull *dscCfg) {
+
+ uint32_t reg;
+
+ reg = CPS_REG_READ(*regAddress);
+
+ dscCfg->rcModelSize = CPS_FLD_READ(MHDP__MHDP_APB_REGS__ENC0_RC_MODEL_SIZE_P, RC_MODEL_SIZE, reg);
+}
+
+static void readEncRcConfig(volatile uint32_t** regAddress, DP_DscConfigFull *dscCfg) {
+
+ uint32_t reg;
+
+ reg = CPS_REG_READ(*regAddress);
+
+ dscCfg->rcEdgeFactor = CPS_FLD_READ(MHDP__MHDP_APB_REGS__ENC0_RC_CONFIG_P, RC_EDGE_FACTOR, reg);
+ dscCfg->rcQuantIncrLimit0 = CPS_FLD_READ(MHDP__MHDP_APB_REGS__ENC0_RC_CONFIG_P, RC_QUANT_INCR_LIMIT0, reg);
+ dscCfg->rcQuantIncrLimit1 = CPS_FLD_READ(MHDP__MHDP_APB_REGS__ENC0_RC_CONFIG_P, RC_QUANT_INCR_LIMIT1, reg);
+ dscCfg->rcTgtOffsetHi = CPS_FLD_READ(MHDP__MHDP_APB_REGS__ENC0_RC_CONFIG_P, RC_TGT_OFFSET_HI, reg);
+ dscCfg->rcTgtOffsetLo = CPS_FLD_READ(MHDP__MHDP_APB_REGS__ENC0_RC_CONFIG_P, RC_TGT_OFFSET_LO, reg);
+}
+
+static void readEncRcBufThresh(volatile uint32_t** regAddress, DP_DscConfigFull *dscCfg) {
+
+ uint32_t reg;
+ uint8_t i;
+ uint8_t index;
+
+ for (i = 0U; i < 3U; i++) {
+ reg = CPS_REG_READ(*regAddress);
+ index = 4U * i;
+ dscCfg->rcBufThresh[index] = (CPS_FLD_READ(MHDP__MHDP_APB_REGS__ENC0_RC_BUF_THRESH_0_P, RC_BUF_THRESH_0, reg) << 6U);
+ dscCfg->rcBufThresh[1U + index] = (CPS_FLD_READ(MHDP__MHDP_APB_REGS__ENC0_RC_BUF_THRESH_0_P, RC_BUF_THRESH_1, reg) << 6U);
+ dscCfg->rcBufThresh[2U + index] = (CPS_FLD_READ(MHDP__MHDP_APB_REGS__ENC0_RC_BUF_THRESH_0_P, RC_BUF_THRESH_2, reg) << 6U);
+ dscCfg->rcBufThresh[3U + index] = (CPS_FLD_READ(MHDP__MHDP_APB_REGS__ENC0_RC_BUF_THRESH_0_P, RC_BUF_THRESH_3, reg) << 6U);
+ (*regAddress)++;
+ }
+
+ reg = CPS_REG_READ(*regAddress);
+
+ dscCfg->rcBufThresh[12] = (CPS_FLD_READ(MHDP__MHDP_APB_REGS__ENC0_RC_BUF_THRESH_3_P, RC_BUF_THRESH_12, reg) << 6U);
+ dscCfg->rcBufThresh[13] = (CPS_FLD_READ(MHDP__MHDP_APB_REGS__ENC0_RC_BUF_THRESH_3_P, RC_BUF_THRESH_13, reg) << 6U);
+}
+
+static void readEncRcMinQp(volatile uint32_t** regAddress, DP_DscConfigFull *dscCfg) {
+
+ uint32_t reg;
+ uint8_t i;
+ uint8_t index;
+
+ for (i = 0U; i < 3U; i++) {
+ reg = CPS_REG_READ(*regAddress);
+ index = 5U * i;
+ dscCfg->rcRangeParameters[index].rangeMinQp = CPS_FLD_READ(MHDP__MHDP_APB_REGS__ENC0_RC_MIN_QP_0_P, RANGE_MIN_QP_0, reg);
+ dscCfg->rcRangeParameters[1U + index].rangeMinQp = CPS_FLD_READ(MHDP__MHDP_APB_REGS__ENC0_RC_MIN_QP_0_P, RANGE_MIN_QP_1, reg);
+ dscCfg->rcRangeParameters[2U + index].rangeMinQp = CPS_FLD_READ(MHDP__MHDP_APB_REGS__ENC0_RC_MIN_QP_0_P, RANGE_MIN_QP_2, reg);
+ dscCfg->rcRangeParameters[3U + index].rangeMinQp = CPS_FLD_READ(MHDP__MHDP_APB_REGS__ENC0_RC_MIN_QP_0_P, RANGE_MIN_QP_3, reg);
+ dscCfg->rcRangeParameters[4U + index].rangeMinQp = CPS_FLD_READ(MHDP__MHDP_APB_REGS__ENC0_RC_MIN_QP_0_P, RANGE_MIN_QP_4, reg);
+ if (2U != i) {
+ (*regAddress)++;
+ }
+ }
+}
+
+static void readEncEcMaxQp(volatile uint32_t** regAddress, DP_DscConfigFull *dscCfg) {
+
+ uint32_t reg;
+ uint8_t i;
+ uint8_t index;
+
+ for (i = 0U; i < 3U; i++) {
+ reg = CPS_REG_READ(*regAddress);
+ index = 5U * i;
+ dscCfg->rcRangeParameters[index].rangeMaxQp = CPS_FLD_READ(MHDP__MHDP_APB_REGS__ENC0_RC_MAX_QP_0_P, RANGE_MAX_QP_0, reg);
+ dscCfg->rcRangeParameters[1U + index].rangeMaxQp = CPS_FLD_READ(MHDP__MHDP_APB_REGS__ENC0_RC_MAX_QP_0_P, RANGE_MAX_QP_1, reg);
+ dscCfg->rcRangeParameters[2U + index].rangeMaxQp = CPS_FLD_READ(MHDP__MHDP_APB_REGS__ENC0_RC_MAX_QP_0_P, RANGE_MAX_QP_2, reg);
+ dscCfg->rcRangeParameters[3U + index].rangeMaxQp = CPS_FLD_READ(MHDP__MHDP_APB_REGS__ENC0_RC_MAX_QP_0_P, RANGE_MAX_QP_3, reg);
+ dscCfg->rcRangeParameters[4U + index].rangeMaxQp = CPS_FLD_READ(MHDP__MHDP_APB_REGS__ENC0_RC_MAX_QP_0_P, RANGE_MAX_QP_4, reg);
+ if (2U != i) {
+ (*regAddress)++;
+ }
+ }
+}
+
+static void readEncRcRangeBpgOffsets(volatile uint32_t** regAddress, DP_DscConfigFull *dscCfg) {
+
+ uint32_t reg;
+ uint8_t i;
+ uint8_t j;
+ uint8_t index;
+ uint32_t value[5];
+
+ for (i = 0U; i < 3U; i++) {
+ reg = CPS_REG_READ(*regAddress);
+ index = 5U * i;
+
+ value[0] = CPS_FLD_READ(MHDP__MHDP_APB_REGS__ENC0_RC_RANGE_BPG_OFFSETS_0_P, RANGE_BPG_OFFSET_0, reg);
+ value[1] = CPS_FLD_READ(MHDP__MHDP_APB_REGS__ENC0_RC_RANGE_BPG_OFFSETS_0_P, RANGE_BPG_OFFSET_1, reg);
+ value[2] = CPS_FLD_READ(MHDP__MHDP_APB_REGS__ENC0_RC_RANGE_BPG_OFFSETS_0_P, RANGE_BPG_OFFSET_2, reg);
+ value[3] = CPS_FLD_READ(MHDP__MHDP_APB_REGS__ENC0_RC_RANGE_BPG_OFFSETS_0_P, RANGE_BPG_OFFSET_3, reg);
+ value[4] = CPS_FLD_READ(MHDP__MHDP_APB_REGS__ENC0_RC_RANGE_BPG_OFFSETS_0_P, RANGE_BPG_OFFSET_4, reg);
+
+ for (j = 0U; j < 5U; j++) {
+ dscCfg->rcRangeParameters[index + j].rangeBpgOffset = (int32_t)value[j];
+ }
+
+ if (2U != i) {
+ (*regAddress)++;
+ }
+ }
+
+ for (i = 0U; i < 15U; i++) {
+ extendSignedInt(&dscCfg->rcRangeParameters[i].rangeBpgOffset);
+ }
+}
+
+static void readEncDpiCtrlOutDelay(volatile uint32_t** regAddress, DP_DscConfigFull *dscCfg) {
+
+ uint32_t reg;
+
+ if (dscCfg->initialLines != 0U ) {
+ reg = CPS_REG_READ(*regAddress);
+ dscCfg->hTotal = CPS_FLD_READ(MHDP__MHDP_APB_REGS__ENC0_DPI_CTRL_OUT_DELAY_P, DPI_CTRL_OUT_DELAY, reg)
+ / dscCfg->initialLines;
+ }
+}
+/*
+ * *******************************************************************************************************
+ * End READ FUNC section
+ * *******************************************************************************************************
+ */
+
+/* parasoft-begin-suppress MISRA2012-RULE-8_13_a-4 "Pass 'dscCfg' parameter as const, DRV-3900" */
+static void readEncConf(const DP_PrivateData* pD, DP_DscConfigFull *dscCfg, uint8_t encIdx)
+{
+ /* Array with pointers to read functions */
+ void (*readCfg[DSC_CFG_READ_WRITE_FUNC_NUM]) (volatile uint32_t * *, DP_DscConfigFull*) = {
+ readEncMainConf,
+ readEncPictureSize,
+ readEncSliceWidth,
+ readEncMiscSize,
+ readEncHrdDelays,
+ readEncRcScale,
+ readEncRcScaleIncDec,
+ readEncRcOffsets,
+ readEncFlatnessDetection,
+ readEncModelSize,
+ readEncRcConfig,
+ readEncRcBufThresh,
+ readEncRcMinQp,
+ readEncEcMaxQp,
+ readEncRcRangeBpgOffsets,
+ readEncDpiCtrlOutDelay
+ };
+
+ volatile uint32_t** actualRegAddress;
+ volatile uint32_t* firstRegAddress;
+ uint8_t i;
+
+ firstRegAddress = getEncAddress(pD, encIdx);
+ actualRegAddress = &firstRegAddress;
+
+ for (i = 0U; i < DSC_CFG_READ_WRITE_FUNC_NUM; i++) {
+ (*readCfg[i])(actualRegAddress, dscCfg);
+ (*actualRegAddress)++;
+ }
+}
+/* parasoft-end-suppress MISRA2012-RULE-8_13_a-4 */
+
+uint32_t DP_DscReadConfiguration(const DP_PrivateData* pD, DP_DscConfigFull* dscCfg, uint8_t streamId)
+{
+ readMainConf(pD, dscCfg);
+ readEncConf(pD, dscCfg, streamId);
+
+ return CDN_EOK;
+}
+
+uint32_t DP_DscSoftwareReset(DP_PrivateData* pD)
+{
+ uint32_t retVal;
+ uint32_t reg;
+ uint32_t softwareReset;
+ DP_RegisterTransfer regTransfer = {0};
+
+ regTransfer.addr = offsetof(MHDP_ApbRegs, mhdp_apb_regs.mhdp_vif_ctrl[0].DSC_CTRL_p);
+ /* Setting reset bit in any stream resets entire DSC - stream '0' may always be used for it. */
+ retVal = DP_ReadRegister(pD, ®Transfer);
+
+ if (CDN_EOK == retVal) {
+ regTransfer.val |= CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__DSC_CTRL_P, DSC_SW_RST, 0U, 1U);
+ regTransfer.addr = offsetof(MHDP_ApbRegs, mhdp_apb_regs.mhdp_vif_ctrl[0].DSC_CTRL_p);
+ retVal = DP_WriteRegister(pD, ®Transfer);
+ }
+
+ if (CDN_EOK == retVal) {
+ regTransfer.addr = offsetof(MHDP_ApbRegs, mhdp_apb_regs.mhdp_vif_ctrl[0].DSC_CTRL_p);
+ /* Might need a timeout// */
+ do {
+ retVal = DP_ReadRegister(pD, ®Transfer);
+ if (CDN_EOK != retVal) {
+ break;
+ }
+ reg = (regTransfer.val);
+ softwareReset = CPS_FLD_READ(MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__DSC_CTRL_P, DSC_SW_RST, reg);
+ } while (softwareReset != 0U);
+ }
+ return retVal;
+}
+
+uint32_t DP_DscRegistersUpdate(DP_PrivateData* pD, uint8_t streamId)
+{
+ uint32_t retVal;
+ uint32_t reg;
+ uint32_t registersUpdate;
+ DP_RegisterTransfer regTransfer = {0};
+
+ regTransfer.addr = offsetof(MHDP_ApbRegs, mhdp_apb_regs.mhdp_vif_ctrl[0].DSC_CTRL_p);
+ regTransfer.addr += streamId * (uint32_t)sizeof(pD->regBase->mhdp_apb_regs.mhdp_vif_ctrl[0]);
+ retVal = DP_ReadRegister(pD, ®Transfer);
+
+ if (CDN_EOK == retVal) {
+ regTransfer.val |= CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__DSC_CTRL_P, DSC_REG_UPDATE, 0U, 1U);
+ retVal = DP_WriteRegister(pD, ®Transfer);
+ }
+
+ if (CDN_EOK == retVal) {
+ /* Might need a timeout// */
+ do {
+ retVal = DP_ReadRegister(pD, ®Transfer);
+ if (CDN_EOK != retVal) {
+ break;
+ }
+ reg = (regTransfer.val);
+ registersUpdate = CPS_FLD_READ(MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__DSC_CTRL_P, DSC_REG_UPDATE, reg);
+ } while (registersUpdate != 0U);
+ }
+
+ return retVal;
+}
+
+uint32_t DP_DscStreamEnable(DP_PrivateData* pD, uint8_t streamId, bool enable)
+{
+ DP_WriteFieldRequest req = {0};
+
+ req.addr = offsetof(MHDP_ApbRegs, mhdp_apb_regs.mhdp_vif_ctrl[0].DSC_CTRL_p);
+ req.addr += streamId * (uint32_t)sizeof(pD->regBase->mhdp_apb_regs.mhdp_vif_ctrl[0]);
+ req.startBit = MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__DSC_CTRL_P__DSC_EN_SHIFT;
+ req.bitCount = MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__DSC_CTRL_P__DSC_EN_WIDTH;
+ req.val = CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__DSC_CTRL_P, DSC_EN, 0U, (enable) ? 1U : 0U);
+
+ return DP_WriteField(pD, &req);
+}
+
+/* parasoft-end-suppress METRICS-41 */
diff --git a/packages/ti/drv/dss/src/csl/dp/src/dp_dsc.h b/packages/ti/drv/dss/src/csl/dp/src/dp_dsc.h
--- /dev/null
@@ -0,0 +1,51 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ *
+ * dp_dsc.h
+ *
+ ******************************************************************************
+ */
+
+#ifndef DP_DSC_H
+#define DP_DSC_H
+
+#include "dp_priv.h"
+
+uint32_t DP_DscWriteConfiguration(const DP_PrivateData* pD, const DP_DscConfigFull* dscCfg, uint8_t streamId);
+
+uint32_t DP_DscReadConfiguration(const DP_PrivateData* pD, DP_DscConfigFull* dscCfg, uint8_t streamId);
+
+uint32_t DP_DscRegistersUpdate(DP_PrivateData* pD, uint8_t streamId);
+
+uint32_t DP_DscSoftwareReset(DP_PrivateData* pD);
+
+uint32_t DP_DscStreamEnable(DP_PrivateData* pD, uint8_t streamId, bool enable);
+
+#endif
diff --git a/packages/ti/drv/dss/src/csl/dp/src/dp_hdcp.c b/packages/ti/drv/dss/src/csl/dp/src/dp_hdcp.c
--- /dev/null
@@ -0,0 +1,596 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ *
+ * dp_hdcp.c
+ *
+ ******************************************************************************
+ */
+
+/* parasoft-begin-suppress METRICS-41-3 "Number of blocks of comments per statement" */
+
+#include "dp_hdcp.h"
+#include "dp_if.h"
+#include "dp_structs_if.h"
+#include "dp_priv.h"
+#include "dp_sanity.h"
+#include "dp_mailbox.h"
+#include "cdn_log.h"
+#include "cdn_errno.h"
+#include "cdn_stdtypes.h"
+
+static uint32_t getErrorCode(uint8_t i, DP_HdcpErrCode* error)
+{
+ uint32_t retVal = CDN_EOK;
+
+ static const DP_HdcpErrCode errorsArray[] = {
+ DP_HDCP_ERR_NO_ERROR,
+ DP_HDCP_ERR_HPD_DOWN,
+ DP_HDCP_ERR_SRM_FAIL,
+ DP_HDCP_ERR_SIGN_ERROR,
+ DP_HDCP_ERR_H_HASH_MISMATCH,
+ DP_HDCP_ERR_V_HASH_MISMATCH,
+ DP_HDCP_ERR_LOCALITY_CHECK_FAIL,
+ DP_HDCP_ERR_DDC_ERROR,
+ DP_HDCP_ERR_REAUTH_REQ,
+ DP_HDCP_ERR_TOPOLOGY_ERROR,
+ DP_HDCP_ERR_RSVD_NOT_ZERO,
+ DP_HDCP_ERR_RI_MISMATCH,
+ DP_HDCP_ERR_WATCHDOG_EXPIRED
+ };
+
+ if (i >= (sizeof(errorsArray) / sizeof(DP_HdcpErrCode))) {
+ retVal = CDN_EINVAL;
+ }
+
+ if (retVal == CDN_EOK) {
+ *error = errorsArray[i];
+ }
+
+ return retVal;
+}
+
+static void fillHdcpConfigVal(const DP_HdcpTxConfiguration* config, uint8_t* val)
+{
+ *val = (uint8_t)config->hdcpVerSupport & 0x03U;
+ *val |= config->activate ? 0x04U : 0U;
+ *val |= (DP_TYPE_1_CONTENT_STREAM == config->contentStreamType) ? 0x08U : 0U;
+ *val |= config->enableKmEncryption ? 0x10U : 0U;
+}
+
+uint32_t DP_ConfigureHdcpTx(DP_PrivateData* pD,
+ const DP_HdcpTxConfiguration* config)
+{
+ uint32_t retVal;
+ uint8_t val;
+
+ retVal = DP_ConfigureHdcpTxSF(pD, config);
+ if (CDN_EOK == retVal)
+ {
+ fillHdcpConfigVal(config, &val);
+
+ messageStart(pD, MB_MODULE_ID_HDCP_TX, (uint8_t)HDCP_TX_CONFIGURATION);
+ messageWriteUint8(pD, val);
+ messageFinish(pD);
+ messageTransmit(pD, DP_BUS_TYPE_SAPB);
+ }
+ return retVal;
+}
+
+uint32_t DP_SetHdcp2TxPublicKey(DP_PrivateData* pD,
+ const DP_Hdcp2TxPublicKey* key)
+{
+ uint32_t retVal;
+
+ retVal = DP_SetHdcp2TxPublicKeySF(pD, key);
+ if (CDN_EOK == retVal)
+ {
+ messageStart(pD, MB_MODULE_ID_HDCP_TX, (uint8_t)HDCP2_TX_SET_PUBLIC_KEY_PARAMS);
+ messageWriteBuffer(pD, key->modulusN, DP_HDCP2_PUBLIC_KEY_N_LENGTH);
+ messageWriteBuffer(pD, key->exponentE, DP_HDCP2_PUBLIC_KEY_E_LENGTH);
+ messageFinish(pD);
+ messageTransmit(pD, DP_BUS_TYPE_SAPB);
+ }
+ return retVal;
+}
+
+uint32_t DP_SetHdcpKmEncCustomKey(DP_PrivateData* pD,
+ const DP_HdcpTxKmEncCustomKey* key)
+{
+ uint32_t retVal;
+
+ retVal = DP_SetHdcpKmEncCustomKeySF(pD, key);
+ if (CDN_EOK == retVal)
+ {
+ messageStart(pD, MB_MODULE_ID_HDCP_TX, (uint8_t)HDCP2_TX_SET_KM_KEY_PARAMS);
+ messageWriteBuffer(pD, key->kmEncCutomKey, DP_HDCP_CUSTOM_KEY_LENGTH);
+ messageFinish(pD);
+ messageTransmit(pD, DP_BUS_TYPE_SAPB);
+ }
+ return retVal;
+}
+
+uint32_t DP_SetHdcp2DebugRandom(DP_PrivateData* pD,
+ const DP_HdcpDebugRandomNumbers* numbers)
+{
+ uint32_t retVal;
+
+ retVal = DP_SetHdcp2DebugRandomSF(pD, numbers);
+ if (CDN_EOK == retVal)
+ {
+ messageStart(pD, MB_MODULE_ID_HDCP_TX, (uint8_t)HDCP2_TX_SET_KM_KEY_PARAMS);
+ messageWriteBuffer(pD, numbers->km, DP_HDCP_KM_LENGTH);
+ messageWriteBuffer(pD, numbers->rn, DP_HDCP_RANDOM_RN_LENGTH);
+ messageWriteBuffer(pD, numbers->ks, DP_HDCP_RANDOM_KS_LENGTH);
+ messageWriteBuffer(pD, numbers->riv, DP_HDCP_RANDOM_RIV_LENGTH);
+ messageWriteBuffer(pD, numbers->rtx, DP_HDCP_RANDOM_RTX_LENGTH);
+ messageFinish(pD);
+ messageTransmit(pD, DP_BUS_TYPE_SAPB);
+ }
+
+ return retVal;
+}
+
+uint32_t DP_Hdcp2RespondKmNotStored(DP_PrivateData* pD)
+{
+ uint32_t retVal;
+
+ retVal = DP_Hdcp2RespondKmNotStoredSF(pD);
+ if (CDN_EOK == retVal)
+ {
+ messageStart(pD, MB_MODULE_ID_HDCP_TX, (uint8_t)HDCP2_TX_RESPOND_KM);
+ messageFinish(pD);
+ messageTransmit(pD, DP_BUS_TYPE_SAPB);
+ }
+
+ return retVal;
+}
+
+uint32_t DP_Hdcp2RespondKmStored(DP_PrivateData* pD,
+ const DP_HdcpPairingData* pairingData)
+{
+ uint32_t retVal;
+
+ retVal = DP_Hdcp2RespondKmStoredSF(pD, pairingData);
+ if (CDN_EOK == retVal)
+ {
+ messageStart(pD, MB_MODULE_ID_HDCP_TX, (uint8_t)HDCP2_TX_RESPOND_KM);
+ messageWriteBuffer(pD, pairingData->id, DP_HDCP_RECV_ID_LENGTH);
+ messageWriteBuffer(pD, pairingData->m, DP_HDCP_M_LENGTH);
+ messageWriteBuffer(pD, pairingData->km, DP_HDCP_KM_LENGTH);
+ messageWriteBuffer(pD, pairingData->ekhKm, DP_HDCP_KM_LENGTH);
+ messageFinish(pD);
+ messageTransmit(pD, DP_BUS_TYPE_SAPB);
+ }
+
+ return retVal;
+}
+
+uint32_t DP_SetHdcp1TxKeys(DP_PrivateData* pD,
+ const DP_Hdcp1Keys* keySet)
+{
+ uint32_t retVal;
+
+ retVal = DP_SetHdcp1TxKeysSF(pD, keySet);
+ if (CDN_EOK == retVal)
+ {
+ messageStart(pD, MB_MODULE_ID_HDCP_TX, (uint8_t)HDCP1_TX_SEND_KEYS);
+ messageWriteBuffer(pD, keySet->ksv, DP_HDCP_RECV_ID_LENGTH);
+ messageWriteBuffer(pD, keySet->keys, DP_HDCP1_KEY_SET_LENGTH);
+ messageFinish(pD);
+ messageTransmit(pD, DP_BUS_TYPE_SAPB);
+ }
+
+ return retVal;
+}
+
+uint32_t DP_SetHdcp1RandomAn(DP_PrivateData* pD,
+ const uint8_t an[8])
+{
+ uint32_t retVal;
+
+ retVal = DP_SetHdcp1RandomAnSF(pD);
+ if ((NULL == an))
+ {
+ retVal = CDN_EINVAL;
+ }
+ if (CDN_EOK == retVal)
+ {
+ messageStart(pD, MB_MODULE_ID_HDCP_TX, (uint8_t)HDCP1_TX_SEND_RANDOM_AN);
+ messageWriteBuffer(pD, an, 8U);
+ messageFinish(pD);
+ messageTransmit(pD, DP_BUS_TYPE_SAPB);
+ }
+
+ return retVal;
+}
+
+uint32_t DP_SendHdcpTxStatusRequest(DP_PrivateData* pD)
+{
+ uint32_t retVal = CDN_EOK;
+
+ retVal = DP_SendHdcpTxStatusRequestSF(pD);
+
+ if (CDN_EOK == retVal)
+ {
+ messageStart(pD, MB_MODULE_ID_HDCP_TX, (uint8_t)HDCP_TX_STATUS_CHANGE);
+ messageFinish(pD);
+ messageTransmit(pD, DP_BUS_TYPE_SAPB);
+ }
+
+ return retVal;
+}
+
+uint32_t DP_GetHdcpTxStatusResponse(DP_PrivateData* pD,
+ DP_HdcpTxStatus* status)
+{
+ uint8_t resp[DP_HDCP_TX_STATUS_SIZE];
+ uint32_t retVal = CDN_EOK;
+ uint8_t errorCode;
+ DP_HdcpErrCode error;
+
+ retVal = DP_GetHdcpTxStatusResponseSF(pD, status);
+
+ if (CDN_EOK != retVal)
+ {
+ DbgMsg(DBG_GEN_MSG, DBG_CRIT,
+ "Function for receiving data containing response with HDCP TX "
+ "status was called incorrectly. DPTX Mailbox may not be able to "
+ "operate any more.\n");
+ }
+
+ if (CDN_EOK == retVal)
+ {
+ messageReceive(pD, DP_BUS_TYPE_SAPB);
+ if (0U == messageHeaderMatches(pD, MB_MODULE_ID_HDCP_TX, (uint8_t)HDCP_TX_STATUS_CHANGE))
+ {
+ retVal = CDN_ENOEXEC;
+ }
+ }
+
+ if (CDN_EOK == retVal)
+ {
+ messageGetHeader(pD, NULL, NULL, NULL);
+ messageReadBuffer(pD, resp, DP_HDCP_TX_STATUS_SIZE);
+
+ errorCode = ((resp[1] & 0xE0U) >> 5) | ((resp[0] & 0x01U) << 3);
+ retVal = getErrorCode(errorCode, &error);
+
+ if (CDN_EOK == retVal) {
+ status->authenticated = (0U != (resp[1] & 0x01U));
+ status->repeater = (0U != (resp[1] & 0x02U));
+ status->rxType = (resp[1] >> 2) & 0x03U;
+ status->authStreamIdSuccess = (0U != (resp[1] & 0x10U));
+ status->lastErr = error;
+ status->enable1d1Features = (0U != (resp[0] & 0x02U));
+ }
+ }
+
+ return retVal;
+}
+
+uint32_t DP_GetHdcpTxStatus(DP_PrivateData* pD,
+ DP_HdcpTxStatus* status)
+{
+ uint32_t retVal = CDN_EOK;
+
+ retVal = DP_GetHdcpTxStatusSF(pD, status);
+
+ if (CDN_EOK == retVal)
+ {
+ retVal = DP_SendHdcpTxStatusRequest(pD);
+ }
+ if (CDN_EOK == retVal)
+ {
+ retVal = DP_GetHdcpTxStatusResponse(pD, status);
+ }
+
+ return retVal;
+}
+
+uint32_t DP_SendHdcp2RecvIdRequest(DP_PrivateData* pD)
+{
+ uint32_t retVal = CDN_EOK;
+
+ retVal = DP_SendHdcp2RecvIdRequestSF(pD);
+
+ if (CDN_EOK == retVal)
+ {
+ messageStart(pD, (uint8_t)MB_MODULE_ID_HDCP_TX, (uint8_t)HDCP2_TX_IS_KM_STORED);
+ messageFinish(pD);
+ messageTransmit(pD, DP_BUS_TYPE_SAPB);
+ }
+
+ return retVal;
+}
+
+uint32_t DP_GetHdcp2RecvIdResponse(DP_PrivateData* pD,
+ uint8_t id[5])
+{
+ uint32_t retVal = CDN_EOK;
+
+ retVal = DP_GetHdcp2RecvIdResponseSF(pD);
+ if (NULL == id)
+ {
+ retVal = CDN_EINVAL;
+ }
+
+ if (CDN_EOK != retVal)
+ {
+ DbgMsg(DBG_GEN_MSG, DBG_CRIT,
+ "Function for receiving data containing response with HDCP2.x "
+ "Receiver ID was called incorrectly. DPTX Mailbox may not be "
+ "able to operate any more.\n");
+ }
+
+ if (CDN_EOK == retVal)
+ {
+ messageReceive(pD, DP_BUS_TYPE_SAPB);
+ if (0U == messageHeaderMatches(pD, MB_MODULE_ID_HDCP_TX, (uint8_t)HDCP2_TX_IS_KM_STORED))
+ {
+ retVal = CDN_ENOEXEC;
+ }
+ }
+
+ if (CDN_EOK == retVal)
+ {
+ messageGetHeader(pD, NULL, NULL, NULL);
+ messageReadBuffer(pD, id, DP_HDCP_RECV_ID_LENGTH);
+ }
+
+ return retVal;
+}
+
+uint32_t DP_GetHdcp2RecvId(DP_PrivateData* pD,
+ uint8_t id[5])
+{
+ uint32_t retVal = CDN_EOK;
+
+ retVal = DP_GetHdcp2RecvIdSF(pD);
+ if (NULL == id)
+ {
+ retVal = CDN_EINVAL;
+ }
+
+ if (CDN_EOK == retVal)
+ {
+ retVal = DP_SendHdcp2RecvIdRequest(pD);
+ }
+ if (CDN_EOK == retVal)
+ {
+ retVal = DP_GetHdcp2RecvIdResponse(pD, id);
+ }
+
+ return retVal;
+}
+
+uint32_t DP_SendHdcp2PairingDataRequest(DP_PrivateData* pD)
+{
+ uint32_t retVal = CDN_EOK;
+
+ retVal = DP_SendHdcp2PairingDataRequeSF(pD);
+
+ if (CDN_EOK == retVal)
+ {
+ messageStart(pD, MB_MODULE_ID_HDCP_TX, (uint8_t)HDCP2_TX_STORE_KM);
+ messageFinish(pD);
+ messageTransmit(pD, DP_BUS_TYPE_SAPB);
+ }
+
+ return retVal;
+}
+
+uint32_t DP_GetHdcp2PairingDataResponse(DP_PrivateData* pD,
+ DP_HdcpPairingData* pairingData)
+{
+ uint32_t retVal = CDN_EOK;
+
+ retVal = DP_GetHdcp2PairingDataResponSF(pD, pairingData);
+
+ if (CDN_EOK != retVal)
+ {
+ DbgMsg(DBG_GEN_MSG, DBG_CRIT,
+ "Function for receiving data containing response with HDCP 2.x "
+ "receiver pairing data was called incorrectly. DPTX Mailbox may "
+ "not be able to operate any more.\n");
+ }
+
+ if (CDN_EOK == retVal)
+ {
+ messageReceive(pD, DP_BUS_TYPE_SAPB);
+ if (0U == messageHeaderMatches(pD, MB_MODULE_ID_HDCP_TX, (uint8_t)HDCP2_TX_STORE_KM))
+ {
+ retVal = CDN_ENOEXEC;
+ }
+ }
+
+ if (CDN_EOK == retVal)
+ {
+ messageGetHeader(pD, NULL, NULL, NULL);
+ messageReadBuffer(pD, pairingData->id, DP_HDCP_RECV_ID_LENGTH);
+ messageReadBuffer(pD, pairingData->m, DP_HDCP_M_LENGTH);
+ messageReadBuffer(pD, pairingData->km, DP_HDCP_KM_LENGTH);
+ messageReadBuffer(pD, pairingData->ekhKm, DP_HDCP_KM_LENGTH);
+ }
+
+ return retVal;
+}
+
+uint32_t DP_GetHdcp2PairingData(DP_PrivateData* pD,
+ DP_HdcpPairingData* pairingData)
+{
+ uint32_t retVal = CDN_EOK;
+
+ retVal = DP_GetHdcp2PairingDataSF(pD, pairingData);
+
+ if (CDN_EOK == retVal)
+ {
+ retVal = DP_SendHdcp2PairingDataRequest(pD);
+ }
+ if (CDN_EOK == retVal)
+ {
+ retVal = DP_GetHdcp2PairingDataResponse(pD, pairingData);
+ }
+
+ return retVal;
+}
+
+uint32_t DP_SendHdcpRecvIdListRequest(DP_PrivateData* pD)
+{
+ uint32_t retVal = CDN_EOK;
+
+ retVal = DP_SendHdcpRecvIdListRequestSF(pD);
+
+ if (CDN_EOK == retVal)
+ {
+ messageStart(pD, MB_MODULE_ID_HDCP_TX, (uint8_t)HDCP_TX_IS_RECEIVER_ID_VALID);
+ messageFinish(pD);
+ messageTransmit(pD, DP_BUS_TYPE_SAPB);
+ }
+
+ return retVal;
+}
+
+uint32_t DP_GetHdcpRecvIdListResponse(DP_PrivateData* pD,
+ DP_HdcpRecvIdList* list)
+{
+ uint32_t retVal = CDN_EOK;
+ uint8_t dummy;
+
+ retVal = DP_GetHdcpRecvIdListResponseSF(pD, list);
+
+ if (CDN_EOK != retVal)
+ {
+ DbgMsg(DBG_GEN_MSG, DBG_CRIT,
+ "Function for receiving data containing response with HDCP "
+ "Receiver ID/KSV list was called incorrectly. DPTX Mailbox may "
+ "not be able to operate any more.\n");
+ }
+
+ if (CDN_EOK == retVal)
+ {
+ messageReceive(pD, DP_BUS_TYPE_SAPB);
+ if (0U == messageHeaderMatches(pD, MB_MODULE_ID_HDCP_TX, (uint8_t)HDCP_TX_IS_RECEIVER_ID_VALID))
+ {
+ retVal = CDN_ENOEXEC;
+ }
+ }
+
+ if (CDN_EOK == retVal)
+ {
+ messageGetHeader(pD, NULL, NULL, NULL);
+ messageReadUint8(pD, &(list->count));
+ messageReadUint8(pD, &dummy);
+ messageReadBuffer(pD, list->ids, ((uint16_t)list->count * DP_HDCP_RECV_ID_LENGTH));
+ }
+
+ return retVal;
+}
+
+uint32_t DP_GetHdcpRecvIdList(DP_PrivateData* pD,
+ DP_HdcpRecvIdList* list)
+{
+ uint32_t retVal = CDN_EOK;
+
+ retVal = DP_GetHdcpRecvIdListSF(pD, list);
+
+ if (CDN_EOK == retVal)
+ {
+ retVal = DP_SendHdcpRecvIdListRequest(pD);
+ }
+ if (CDN_EOK == retVal)
+ {
+ retVal = DP_GetHdcpRecvIdListResponse(pD, list);
+ }
+
+ return retVal;
+}
+
+uint32_t DP_SetHdcpRecvValid(DP_PrivateData* pD,
+ bool valid)
+{
+ uint32_t retVal;
+
+ retVal = DP_SetHdcpRecvValidSF(pD);
+
+ if (CDN_EOK == retVal)
+ {
+ messageStart(pD, MB_MODULE_ID_HDCP_TX, (uint8_t)HDCP_TX_RESPOND_RECEIVER_ID_VALID);
+ messageWriteUint8(pD, valid ? 1U : 0U);
+ messageFinish(pD);
+ messageTransmit(pD, DP_BUS_TYPE_SAPB);
+ }
+ return retVal;
+}
+
+uint32_t DP_SetHdcp2Lc(DP_PrivateData* pD,
+ const uint8_t lc128[DP_HDCP_LC128_LENGTH])
+{
+ uint32_t retVal;
+
+ retVal = DP_SetHdcp2LcSF(pD);
+ if (NULL == lc128)
+ {
+ retVal = CDN_EINVAL;
+ }
+
+ if (CDN_EOK == retVal)
+ {
+ messageStart(pD, MB_MODULE_ID_HDCP_GENERAL, (uint8_t)HDCP_GENERAL_SET_LC_128);
+ messageWriteBuffer(pD, lc128, DP_HDCP_LC128_LENGTH);
+ messageFinish(pD);
+ messageTransmit(pD, DP_BUS_TYPE_SAPB);
+ }
+
+ return retVal;
+}
+
+uint32_t DP_SetHdcpSeed(DP_PrivateData* pD,
+ const uint8_t seed[DP_HDCP_SEED_LENGTH])
+{
+ uint32_t retVal;
+
+ retVal = DP_SetHdcpSeedSF(pD);
+ if (NULL == seed)
+ {
+ retVal = CDN_EINVAL;
+ }
+
+ if (CDN_EOK == retVal)
+ {
+ messageStart(pD, MB_MODULE_ID_HDCP_GENERAL, (uint8_t)HDCP_SET_SEED);
+ messageWriteBuffer(pD, seed, DP_HDCP_SEED_LENGTH);
+ messageFinish(pD);
+ messageTransmit(pD, DP_BUS_TYPE_SAPB);
+ }
+
+ return retVal;
+}
+
+/* parasoft-end-suppress METRICS-41-3 */
diff --git a/packages/ti/drv/dss/src/csl/dp/src/dp_hdcp.h b/packages/ti/drv/dss/src/csl/dp/src/dp_hdcp.h
--- /dev/null
@@ -0,0 +1,70 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ *
+ * dp_hdcp.h
+ *
+ ******************************************************************************
+ */
+
+#ifndef DP_HDCP_H
+#define DP_HDCP_H
+
+/**
+ *
+ * \brief transmitter supported API (via mailbox)
+ */
+typedef enum
+{
+ HDCP_TX_CONFIGURATION, /*!< use this command to set HDCP transmitter type and wake it up (or stop ), 1 byte with following bits : Bit (0-1)= 0 - support only HDCP 2, 1 - support only HDCP 1, 2 - support both HDCP, Bit 2 - active (to activate port set to 1), to stop port set to 0 */
+ HDCP2_TX_SET_PUBLIC_KEY_PARAMS, /*!< use it to set public key for the HDCP2.x transmitter(HDCP2.x), Modulus n - 384 bytes, E - 3 bytes */
+ HDCP2_TX_SET_DEBUG_RANDOM_NUMBERS, /*!< use this command to enforce the random parameters (for debug only!), instead of the random data generated by the embedded RNG.Use this command after HDCP_TX_SET_PUBLIC_KEY_PARAMS command. Relevant to (HDCP2.x), data is : KM 16 bytes,RN 8 bytes,KS 16 bytes,RIV 8 bytes,RTX 8 bytes */
+ HDCP2_TX_RESPOND_KM, /*!< If km is stored, return all parameters, else there is no extra data(HDCP2.x), data is : Receiver ID (5 bytes),m (16 bytes),Km (16 bytes),Ekh(Km)(16 bytes) */
+ HDCP1_TX_SEND_KEYS, /*!< send keys needed for HDCP 1, data is : AKSV (5 bytes), ksv (7*40 = 280 bytes)*/
+ HDCP1_TX_SEND_RANDOM_AN, /*!< set AN, use it for debug purpose, if not use, it will be random number, data is (8 bytes) */
+ HDCP_TX_STATUS_CHANGE, /*!< Will be called in port status change event by cadence HDCP IP, Status for the port:Bit 0 - AUTHENTICATED (1 - link is authenticated), Bit 1 - receiver is REPEATER (1 for repeater, 0 not),Bit 2 - 0 for HDCP1, 1 for HDCP2, */
+ HDCP2_TX_IS_KM_STORED, /*!< controller check if KM is stored by host(HDCP2.x), data is : Receiver ID (5 bytes) */
+ HDCP2_TX_STORE_KM, /*!< controller ask host to store KM, host may store it on non-volatile memory for faster authentication(HDCP2.x), data is : Receiver ID (5 bytes),m (16 bytes),Km(16 bytes),Ekh(Km),(16 bytes) */
+ HDCP_TX_IS_RECEIVER_ID_VALID, /*!< controller check if receivers ID are not in revocation list, input is->first byte for number of receivers, then list of receivers (5 bytes each) */
+ HDCP_TX_RESPOND_RECEIVER_ID_VALID, /*!< If receivers ID are valid return 1, otherwise return 0, same for HDCP1,HDCP2*/
+ HDCP_TX_TEST_KEYS, /*!< compare HDCP keys with facsimile key*/
+ HDCP2_TX_SET_KM_KEY_PARAMS, /*!< This Command is used to load customer defined Key for km-key encryption into the HDCP2.x transmitter controller. */
+} HDCP_TRNAS_MAILBOX_MSG_ID;
+/** @} */ /* */
+
+/* //////////////////////////////////////////////////////////////// */
+/* HDCP ports mail box messages */
+/* //////////////////////////////////////////////////////////////// */
+typedef enum
+{
+ HDCP_GENERAL_SET_LC_128 = 0,
+ HDCP_SET_SEED,
+} HDCP_GENERAL_MSG;
+
+#endif /*DP_HDCP_H_ */
diff --git a/packages/ti/drv/dss/src/csl/dp/src/dp_if.c b/packages/ti/drv/dss/src/csl/dp/src/dp_if.c
--- /dev/null
@@ -0,0 +1,4540 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ *
+ * dp_if.c
+ *
+ ******************************************************************************
+ */
+
+/* parasoft-begin-suppress METRICS-36-3 "Function called from more than 5 different functions, DRV-3823" */
+/* parasoft-begin-suppress METRICS-41 "Number of comments per block" */
+
+#include "dp_structs_if.h"
+#include "dp_priv.h"
+#include "dp_sanity.h"
+#include "dp_internal.h"
+#include "dp_dsc.h"
+#include "dp_link_policy.h"
+#include "dp_utils.h"
+#include "dp_register.h"
+#include "dsc_utils.h"
+#include "dp_aux.h"
+#include "dp_aux_if.h"
+#include "dp_aux_structs_if.h"
+#include "dp_mst.h"
+#include "dp_transaction.h"
+#include "dp_mst_if.h"
+#include "dp_mailbox.h"
+
+#include "mhdp_apb_regs.h"
+#include "cps_drv.h"
+
+#include "cdn_log.h"
+#include "cdn_errno.h"
+#include "custom_types.h"
+
+#include <string.h> /* for memset */
+
+static bool isSinkPort(const MST_drm_dp_port *port)
+{
+ bool isOutputConnected = ((port->refcount != 0U) && (!port->input) && (port->ddps));
+ bool isSink = (port->pdt == DP_PEER_DEVICE_SST_SINK) || (port->pdt == DP_PEER_DEVICE_DP_LEGACY_CONV);
+
+ return isOutputConnected && isSink;
+}
+
+static uint32_t collectSinkPorts(const MST_drm_dp_branch* mstBranch,
+ const MST_drm_dp_port** portList,
+ const MST_drm_dp_branch** branchesArray,
+ uint8_t* sinkCount,
+ uint8_t* branchesArrayHead)
+{
+ uint32_t retVal = CDN_EOK;
+ const MST_drm_dp_port *port;
+ uint8_t i;
+
+ for (i = 0U; i < MST_BRANCH_MAX_PORTS; i++) {
+ port = &(mstBranch->ports[i]);
+ if ((isSinkPort(port)) && (*sinkCount < DP_MAX_NUMBER_OF_STREAMS)) {
+ portList[*sinkCount] = port;
+ (*sinkCount)++;
+ } else if ((port->pdt == DP_PEER_DEVICE_MST_BRANCHING) && (port->refcount != 0U)) {
+ if (*branchesArrayHead < MST_MAX_BRANCH_NUMBER) {
+ branchesArray[*branchesArrayHead] = port->mstb;
+ (*branchesArrayHead)++;
+ } else {
+ retVal = CDN_EINVAL;
+ break;
+ }
+ } else {
+ /*
+ * All 'if ... else if' constructs shall be terminated with an 'else' statement
+ * (MISRA2012-RULE-15_7-3)
+ */
+ }
+ }
+
+ return retVal;
+}
+
+static uint32_t collectSinkPortList(const MST_drm_dp_branch* mstBranch,
+ const MST_drm_dp_port** portList,
+ uint8_t* sinkCount)
+{
+ MST_drm_dp_branch* branchesArray[MST_MAX_BRANCH_NUMBER] = {NULL};
+ bool maxDeepLevelReached;
+ uint8_t branchesArrayHead = 0U;
+ uint8_t branchesArrayActualPosition = 0U;
+ uint8_t deepLevelIndex = 0U;
+ uint8_t deepLevel = 1U;
+ uint32_t retVal;
+ MST_drm_dp_branch* actualBranch;
+
+ /* Collect ports and branches for first node. */
+ retVal = collectSinkPorts(mstBranch,
+ portList,
+ (const MST_drm_dp_branch**) branchesArray,
+ sinkCount,
+ &branchesArrayHead);
+
+ actualBranch = branchesArray[branchesArrayActualPosition];
+ deepLevelIndex = branchesArrayHead;
+
+ while ((actualBranch != NULL) && (CDN_EOK == retVal)) {
+ retVal = collectSinkPorts(actualBranch,
+ portList,
+ (const MST_drm_dp_branch**) branchesArray,
+ sinkCount,
+ &branchesArrayHead);
+
+ branchesArrayActualPosition++;
+ actualBranch = branchesArray[branchesArrayActualPosition];
+
+ if (branchesArrayActualPosition == deepLevelIndex) {
+ deepLevel++;
+ deepLevelIndex = branchesArrayHead;
+ }
+
+ maxDeepLevelReached = (MST_MAX_BRANCH_DEEP_LEVEL == deepLevel);
+
+ /* Max depth level of branches was reached, but there is more to check */
+ if ((maxDeepLevelReached) && (NULL != actualBranch)) {
+ retVal = CDN_EINVAL;
+ }
+
+ /* Break collecting sink ports upon reaching max depth level of branches or collecting max number of ports. */
+ if ((*sinkCount == DP_MAX_NUMBER_OF_STREAMS) || (maxDeepLevelReached)) {
+ break;
+ }
+ }
+ return retVal;
+}
+
+static void removeDisconnectedSinks(DP_PrivateData* pD,
+ const MST_drm_dp_port** portList,
+ uint8_t sinkCount)
+{
+ uint8_t i;
+ uint8_t j;
+ bool markRemove = false;
+
+ for (i = 0U; i < DP_MAX_NUMBER_OF_STREAMS; i++) {
+ if (NULL != pD->sinkList[i].port) {
+ markRemove = true;
+ for (j = 0U; j < sinkCount; j++) {
+ if (pD->sinkList[i].port == portList[j]) {
+ markRemove = false;
+ }
+ }
+ if (markRemove) {
+ pD->sinkList[i].port = NULL;
+ }
+ }
+ }
+}
+
+static uint32_t updateConnectedSinks(DP_PrivateData* pD,
+ MST_drm_dp_port** port_list,
+ uint8_t sink_count) {
+ uint32_t retVal = CDN_EOK;
+ bool newSink = false;
+ uint8_t i;
+ uint8_t j;
+
+ for (i = 0U; i < sink_count; i++) {
+ newSink = true;
+ for (j = 0U; j < DP_MAX_NUMBER_OF_STREAMS; j++) {
+ if (pD->sinkList[j].port == port_list[i]) {
+ newSink = false;
+ break;
+ }
+ }
+
+ if (newSink) {
+ for (j = 0U; j < DP_MAX_NUMBER_OF_STREAMS; j++) {
+
+ if (pD->sinkList[j].port == NULL) {
+ pD->sinkList[j].port = port_list[i];
+ newSink = false;
+ break;
+ }
+ }
+
+ if (newSink) {
+ retVal = CDN_EINVAL;
+ }
+ }
+ }
+
+ return retVal;
+}
+
+/**
+ * Get symbol rate, in units of 1M symbols / second / lane (equal to tens of Mib/s)
+ */
+uint16_t getSymbolRate(DP_LinkRate linkRate)
+{
+ uint16_t result;
+ switch (linkRate)
+ {
+ case DP_LINK_RATE_1_62:
+ result = 162U;
+ break;
+ case DP_LINK_RATE_2_16:
+ result = 216U;
+ break;
+ case DP_LINK_RATE_2_43:
+ result = 243U;
+ break;
+ case DP_LINK_RATE_2_70:
+ result = 270U;
+ break;
+ case DP_LINK_RATE_3_24:
+ result = 324U;
+ break;
+ case DP_LINK_RATE_4_32:
+ result = 432U;
+ break;
+ case DP_LINK_RATE_5_40:
+ result = 540U;
+ break;
+ default:
+ result = 810U;
+ break;
+ }
+ return result;
+}
+
+/**
+ * Function calculates bits per component, adjusted for pixel encoding format
+ */
+float64_t calculateBitsPerComponent(const DP_PrivateData* pD, uint8_t streamId)
+{
+ float64_t bitsPerCompCalc;
+ DP_PixelEncodingFormat pixelEncodingFormat = pD->videoParameters[streamId].pxEncFormat;
+ float64_t bitsPerComp = (float64_t)pD->videoParameters[streamId].bitsPerSubpixel;
+
+ if (pixelEncodingFormat == DP_PXENC_YCBCR_4_2_2) {
+ bitsPerCompCalc = (bitsPerComp * 2.0) / 3.0;
+ }
+ else if (pixelEncodingFormat == DP_PXENC_YCBCR_4_2_0) {
+ bitsPerCompCalc = bitsPerComp / 2.0;
+ }
+ else {
+ bitsPerCompCalc = bitsPerComp;
+ }
+
+ if (pD->videoParameters[streamId].dscEnable) {
+ bitsPerComp = (float64_t)pD->dscConfig[streamId].bitsPerPixel;
+ bitsPerCompCalc = (bitsPerComp / 16.0) / 3.0;
+ }
+
+ return bitsPerCompCalc;
+
+}
+
+/**
+ * Local struct containing parameters used for calculation of Valid Symbols per
+ * Transfer Unit.
+ */
+struct validSymbolCalcParams
+{
+ uint8_t tuSize;
+ float64_t pxlClk;
+ float64_t bitsPerComp;
+ uint8_t laneCount;
+ float64_t rate;
+ float64_t validSymPercentOverhead;
+};
+
+/**
+ * Calculate integer and fractional parts of valid symbols per transfer unit
+ * (TU), based on TU size, pixel clock (in MHz), bits per component (adjusted
+ * for pixel encoding), lane count and symbol rate (in M Symbols/lane/second)
+ */
+static void calculateValidSymbol(const struct validSymbolCalcParams* params,
+ uint32_t * validSym,
+ uint16_t * validSymF)
+{
+ float64_t tempValidSym = (float64_t)params->tuSize * params->pxlClk * params->bitsPerComp * 3000.0;
+ tempValidSym = floor(tempValidSym);
+
+ if (params->validSymPercentOverhead > 0.0) {
+ tempValidSym *= ((params->validSymPercentOverhead / 100.0) + 1.0);
+ tempValidSym = floor(tempValidSym);
+ }
+
+ tempValidSym /= (float64_t)params->laneCount * params->rate * 8.0;
+
+ *validSymF = (uint16_t)tempValidSym % 1000U;
+ *validSym = (uint32_t)tempValidSym / 1000U;
+}
+
+static bool isTuSizeOptimal(uint8_t tu_size,
+ uint32_t validSym,
+ uint16_t validSymF,
+ uint32_t validSym2,
+ uint16_t validSym2F)
+{
+ bool tuOptimal = true;
+
+ /* too few valid symbols (VS) per TU */
+ if (validSym == 1U) {
+ tuOptimal = false;
+ }
+
+ /* VS too close to TU size */
+ if ((tu_size - validSym) < 2U) {
+ tuOptimal = false;
+ }
+
+ /* down-spread changes integer part of VS per TU */
+ if (validSym != validSym2) {
+ tuOptimal = false;
+ }
+
+ /* fractional part of VS per TU too close to 1 (1000/1000) */
+ if (validSymF > 850U) {
+ tuOptimal = false;
+ }
+
+ /* fractional part of VS per TU too close to 0 (0/1000) */
+ if (validSymF < 100U) {
+ tuOptimal = false;
+ }
+
+ /* fractional part of VS per TU (down-spread) too close to 1 (1000/1000) */
+ if (validSym2F > 850U) {
+ tuOptimal = false;
+ }
+
+ /* fractional part of VS per TU (down-spread) too close to 0 (0/1000) */
+ if (validSym2F < 100U) {
+ tuOptimal = false;
+ }
+
+ /* Maximum TU size is reached - no much choice, have to accept. */
+ if (tu_size >= 64U) {
+ tuOptimal = true;
+ }
+
+ return tuOptimal;
+}
+
+/**
+ * Copies structure for calculating valid symbols per TU, applying 0.5% down-spread.
+ */
+static void fillPostSpreadParams(const struct validSymbolCalcParams* preSpreadParams,
+ struct validSymbolCalcParams* postSpreadParams)
+{
+ postSpreadParams->tuSize = preSpreadParams->tuSize;
+ postSpreadParams->pxlClk = preSpreadParams->pxlClk;
+ postSpreadParams->bitsPerComp = preSpreadParams->bitsPerComp;
+ postSpreadParams->laneCount = preSpreadParams->laneCount;
+ /* link rate adjusted for 0.5% down-spread */
+ postSpreadParams->rate = (preSpreadParams->rate * 0.995);
+ postSpreadParams->validSymPercentOverhead = preSpreadParams->validSymPercentOverhead;
+}
+
+/**
+ * Calculate transfer unit parametrs
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] validSymOverhead valid symbols overhead in percents,
+ * if no extra overhead to be added should be 0
+ * @param[out] validSym valid symbols (VS) per TU - integer part
+ * @param[out] validSymF valid symbols per TU - fractional part (thousandth parts, 0 - 999)
+ * @param[out] tuSize Transfer Unit (TU) size
+ * @return CDN_OK success
+ * @return CDN_ERROR_NOT_SUPPORTED if link bandwidth is oversubscribed
+ */
+
+static uint32_t calculateTuParams(const DP_PrivateData* pD,
+ float64_t validSymOverhead,
+ uint32_t * validSym,
+ uint16_t * validSymF,
+ uint8_t * tuSize)
+{
+ const uint8_t streamId = 0U; /* SST mode */
+ uint32_t retVal = CDN_EOK;
+ /* value of validSym being currently tested */
+ uint32_t currValidSym;
+ /* value of validSymF being currently tested */
+ uint16_t currValidSymF;
+ /* like validSym, but taking 0.5% down-spread into consideration */
+ uint32_t currValidSym2;
+ /* like validSymF, but taking down-spread into consideration */
+ uint16_t currValidSym2F;
+ /* value of tuSize being currently tested */
+ uint8_t currTuSize = 32U;
+
+ bool optimalSize;
+ float64_t bitsPerCompCalc = calculateBitsPerComponent(pD, streamId);
+ float64_t pxlFreq = pD->videoParameters[streamId].vicParams.pxlFreq;
+ float64_t symbolRate = (float64_t)(getSymbolRate(pD->linkState.linkRate));
+ uint8_t laneCount = pD->linkState.laneCount;
+
+ struct validSymbolCalcParams preSpreadParams;
+ struct validSymbolCalcParams postSpreadParams;
+
+ preSpreadParams.tuSize = currTuSize;
+ preSpreadParams.pxlClk = pxlFreq;
+ preSpreadParams.bitsPerComp = bitsPerCompCalc;
+ preSpreadParams.laneCount = laneCount;
+ preSpreadParams.rate = symbolRate;
+ preSpreadParams.validSymPercentOverhead = validSymOverhead;
+
+ fillPostSpreadParams(&preSpreadParams, &postSpreadParams);
+
+ /* Find optimal value for the TU_SIZE, incrementally trying even values, */
+ /* starting from minimum (32), up to maximum (64) */
+ while (true) {
+ calculateValidSymbol(&preSpreadParams, &currValidSym, &currValidSymF);
+
+ calculateValidSymbol(&postSpreadParams, &currValidSym2, &currValidSym2F);
+
+ optimalSize = isTuSizeOptimal(currTuSize,
+ currValidSym,
+ currValidSymF,
+ currValidSym2,
+ currValidSym2F);
+
+ if (false == optimalSize) {
+ currTuSize += 2U;
+ preSpreadParams.tuSize = currTuSize;
+ postSpreadParams.tuSize = currTuSize;
+ } else {
+ break;
+ }
+ }
+
+ /* Link bandwidth is oversubscribed. */
+ if (currValidSym >= 64U) {
+ retVal = CDN_ENOTSUP;
+ }
+
+ if (CDN_EOK == retVal) {
+ *tuSize = currTuSize;
+ *validSym = currValidSym;
+ *validSymF = currValidSymF;
+ }
+ return retVal;
+}
+
+/**
+ * Calculate line threshold parameter for FIFO
+ */
+static uint8_t calcLineThresh(const DP_PrivateData* pD,
+ uint32_t validSym)
+{
+ const uint8_t streamId = 0U; /* SST mode */
+ float64_t lineThresh;
+ float64_t bitsPerCompCalc = calculateBitsPerComponent(pD, streamId);
+ float64_t pxlFreq = pD->videoParameters[streamId].vicParams.pxlFreq;
+ uint16_t symbolRate = getSymbolRate(pD->linkState.linkRate);
+ uint8_t laneCount = pD->linkState.laneCount;
+
+ float64_t calcBpc = (3.0 * bitsPerCompCalc) / 8.0;
+ float64_t validSymUp = (float64_t)validSym + 1.0;
+
+ /* LINE_THRESH set according to presentation. */
+ lineThresh = ((validSymUp * (float64_t)laneCount) -
+ (((pxlFreq / (float64_t)symbolRate) * validSymUp * calcBpc) - calcBpc)) /
+ (calcBpc * (float64_t)laneCount);
+
+ lineThresh = ceil(lineThresh);
+ lineThresh += 2.0;
+
+ if (lineThresh > 12.0) {
+ lineThresh = 12.0;
+ }
+
+ return (uint8_t)lineThresh;
+}
+
+/**
+ * Calculate difference between TU size and VS per TU
+ * @param[in] tuSize Transfer Unit (TU) size
+ * @param[out] validSym valid symbols (VS) per TU - integer part
+ * @return calculated difference between TU size and VS per TU.
+ */
+static uint32_t calcTuVsDiff(uint8_t tuSize, uint32_t validSym)
+{
+ uint32_t tuVsDiff = 0U;
+
+ if ((tuSize - validSym) <= 3U ) {
+ tuVsDiff = tuSize - validSym;
+ }
+
+ return tuVsDiff;
+}
+
+static float64_t calculateTargetAverageSlots(const DP_PrivateData* pD,
+ uint8_t streamId,
+ bool fecEnabled)
+{
+ uint32_t payloadBandwidth;
+ uint32_t payloadBandwidthDiv;
+ float64_t targetAverageSlots;
+
+ const float64_t pixelFrequency = pD->videoParameters[streamId].vicParams.pxlFreq * 1000.0;
+ const float64_t bitsPerComponentCalc = calculateBitsPerComponent(pD, streamId) * 3.0;
+ uint32_t symbolRate = (uint32_t)getSymbolRate(pD->linkState.linkRate);
+
+ payloadBandwidth = DP_MST_MgrCalcPbnMode((uint32_t)pixelFrequency,
+ (uint8_t)bitsPerComponentCalc,
+ fecEnabled);
+
+ payloadBandwidthDiv = ((uint32_t)pD->linkState.laneCount * symbolRate) / MST_LINK_RATE_MULTIPLIER;
+
+ targetAverageSlots = (float64_t)payloadBandwidth / (float64_t)payloadBandwidthDiv;
+
+ return targetAverageSlots;
+}
+
+static uint32_t calcSdpBlockVblank(const DP_PrivateData* pD,
+ uint8_t streamId,
+ float64_t targAvgSlots)
+{
+ const uint32_t vblankCyclesMax = 65535U; /* 16 bits */
+
+ float64_t vblankCycles;
+ uint8_t laneCountCalc; /* Number of lanes, used for calculations. */
+
+ const uint8_t laneCount = pD->linkState.laneCount;
+ const uint32_t vTotal = pD->videoParameters[streamId].vicParams.vTotal;
+ const uint32_t symbolRate = (uint32_t)getSymbolRate(pD->linkState.linkRate);
+ const float64_t pixelClock = pD->videoParameters[streamId].vicParams.pxlFreq;
+
+ /* For MST, calculate like there are always 4 lanes. */
+ laneCountCalc = (!pD->mstEnabled) ? laneCount : 4U;
+
+ /* Calculate number of data_clk cycles. */
+ uint32_t init = (vTotal * symbolRate) / 2U;
+ vblankCycles = (float64_t)init / pixelClock;
+ vblankCycles = floor(vblankCycles);
+
+ if (pD->mstEnabled) {
+ /* Quantize to slot allocation */
+ vblankCycles *= (targAvgSlots / 64.0);
+ vblankCycles = floor(vblankCycles);
+ }
+
+ /* Apply safety margin. */
+ vblankCycles = (vblankCycles * 90.0) / 100.0;
+ vblankCycles = floor(vblankCycles);
+
+ float64_t marigin = (36.0 / (float64_t)laneCountCalc) + 1.0;
+ if (vblankCycles > marigin) {
+ vblankCycles -= marigin;
+ vblankCycles = floor(vblankCycles);
+ } else {
+ vblankCycles = 0.0;
+ }
+
+ if (pD->mstEnabled) {
+ /* Adjust for actual number of lanes */
+ vblankCycles *= ((float64_t)laneCount / 4.0);
+ vblankCycles = floor(vblankCycles);
+ }
+
+ if ((uint32_t)vblankCycles > vblankCyclesMax) {
+ vblankCycles = (float64_t)vblankCyclesMax;
+ }
+
+ return (uint32_t)vblankCycles;
+}
+
+static uint32_t calcSdpBlockHblank(const DP_PrivateData* pD,
+ uint8_t streamId,
+ float64_t targAvgSlots)
+{
+ const uint16_t hblankCyclesMax = 32767U; /* 15 bits */
+ float64_t hblankCycles;
+ uint8_t laneCountCalc; /* Number of lanes, used for calculations. */
+
+ const uint8_t laneCount = pD->linkState.laneCount;
+ const uint32_t hTotal = pD->videoParameters[streamId].vicParams.hTotal;
+ const uint32_t hActive = pD->videoParameters[streamId].vicParams.hActive;
+ const uint16_t symbolRate = getSymbolRate(pD->linkState.linkRate);
+ const float64_t pixelClock = pD->videoParameters[streamId].vicParams.pxlFreq;
+
+ /* For MST, calculate like there are always 4 lanes. */
+ laneCountCalc = (!pD->mstEnabled) ? laneCount : 4U;
+ uint32_t init = ((hTotal - hActive) * (uint32_t)symbolRate) / 2U;
+ hblankCycles = (float64_t)init / pixelClock;
+ hblankCycles = floor(hblankCycles);
+
+ if (pD->mstEnabled) {
+ /* Quantize to slot allocation */
+ hblankCycles *= (targAvgSlots / 64.0);
+ hblankCycles = floor(hblankCycles);
+ }
+
+ /* Apply safety margin. */
+ hblankCycles = (hblankCycles * 90.0) / 100.0;
+ hblankCycles = floor(hblankCycles);
+
+ float64_t marigin = (36.0 / (float64_t)laneCountCalc) + 1.0;
+ if (hblankCycles > marigin) {
+ hblankCycles -= marigin;
+ hblankCycles = floor(hblankCycles);
+ } else {
+ hblankCycles = 0.0;
+ }
+
+ if (pD->mstEnabled) {
+ /* Adjust for actual number of lanes */
+ hblankCycles *= ((float64_t)laneCount / 4.0);
+ hblankCycles = floor(hblankCycles);
+ }
+
+ if ((uint32_t)hblankCycles > hblankCyclesMax) {
+ hblankCycles = (float64_t)hblankCyclesMax;
+ }
+
+ return (uint32_t)hblankCycles;
+}
+
+static uint32_t calcByteCount(const DP_PrivateData* pD,
+ uint8_t streamId)
+{
+
+ uint8_t laneCountCalc; /* Number of lanes, used for calculations. */
+ float64_t bitsPerPixel = calculateBitsPerComponent(pD, streamId) * 3.0;
+ float64_t pixelsPerLane; /* Number of pixels to be distributed per lane */
+ float64_t byteCount;
+
+ /* For MST, calculate like there are always 4 lanes. */
+ laneCountCalc = (!pD->mstEnabled) ? pD->linkState.laneCount : 4U;
+ pixelsPerLane = (float64_t)pD->videoParameters[streamId].vicParams.hActive / (float64_t)laneCountCalc;
+ pixelsPerLane = ceil(pixelsPerLane);
+ if (DP_PXENC_YCBCR_4_2_0 == pD->videoParameters[streamId].pxEncFormat)
+ {
+ /* For 4:2:0 mode, each lane will store pairs of pixels consecutively */
+ pixelsPerLane = 2.0 * ceil(pixelsPerLane / 2.0);
+ }
+ byteCount = pixelsPerLane * (float64_t)laneCountCalc * (bitsPerPixel / 8.0);
+ byteCount = ceil(byteCount);
+
+ return (uint32_t)byteCount;
+}
+
+static uint32_t configureSstVideoParams(DP_PrivateData* pD, uint16_t *validSymF, bool fecEnabled)
+{
+ const uint8_t framerTuUpdateBits = 16U;
+ const uint8_t streamId = 0U; /* SST mode */
+ uint32_t retVal;
+ uint32_t validSym;
+ uint8_t tuSize;
+ uint32_t tuVsDiff; /* difference between TU size and VS per TU. 0 used for values > 3. */
+ uint32_t lineThresh;
+ DP_RegisterTransfer regTransfer = {0U};
+ DP_WriteFieldRequest req;
+ float64_t overhead = (fecEnabled) ? DP_FEC_OVERHEAD : 0.0;
+
+ retVal = calculateTuParams(pD, overhead, &validSym, validSymF, &tuSize);
+
+ if (CDN_EOK == retVal)
+ {
+ req.addr = offsetof(MHDP_ApbRegs, mhdp_apb_regs.DP_FRAMER_TU_p);
+ req.startBit = 0U;
+ req.bitCount = framerTuUpdateBits;
+ req.val = CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__DP_FRAMER_TU_P, TU_VALID_SYMBOLS, 0U, validSym) |
+ CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__DP_FRAMER_TU_P, TU_SIZE, 0U, tuSize);
+
+ retVal = DP_WriteField(pD, &req);
+ }
+
+ if (CDN_EOK == retVal)
+ {
+ tuVsDiff = calcTuVsDiff(tuSize, validSym);
+ regTransfer.addr = offsetof(MHDP_ApbRegs, mhdp_apb_regs.mhdp_dptx_stream[0].STREAM_CONFIG_2_p);
+ regTransfer.addr += streamId * (uint32_t)sizeof(pD->regBase->mhdp_apb_regs.mhdp_dptx_stream[0]);
+ regTransfer.val = CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__STREAM_CONFIG_2_P, CFG_TU_VS_DIFF, 0U, tuVsDiff);
+ retVal = DP_WriteRegister(pD, ®Transfer);
+ }
+
+ if (CDN_EOK == retVal)
+ {
+ lineThresh = calcLineThresh(pD, validSym);
+ regTransfer.addr = offsetof(MHDP_ApbRegs, mhdp_apb_regs.mhdp_dptx_stream[0].LINE_THRESH_p);
+ regTransfer.addr += streamId * (uint32_t)sizeof(pD->regBase->mhdp_apb_regs.mhdp_dptx_stream[0]);
+ regTransfer.val = CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__LINE_THRESH_P, CFG_ACTIVE_LINE_TRESH, 0U, lineThresh);
+ retVal = DP_WriteRegister(pD, ®Transfer);
+ }
+
+ return retVal;
+}
+
+/* Local structure used to configure horizontal and vertical params of stream */
+typedef struct HorizontalVerticalParams_t {
+ uint32_t backPorch;
+ uint32_t frontPorch;
+ uint32_t sync;
+ uint32_t active;
+ uint32_t total;
+ DP_SyncPolarity syncPolarity;
+} HorizontalVerticalParams;
+
+/* Set of functions used to properly configure horizontal parameters of stream */
+static uint32_t configureMsaHorizontal0(DP_PrivateData* pD,
+ uint8_t streamId,
+ const HorizontalVerticalParams* hParams)
+{
+ DP_RegisterTransfer regTransfer = {0U};
+
+ uint32_t hStart = hParams->sync + hParams->backPorch;
+
+ regTransfer.addr = offsetof(MHDP_ApbRegs, mhdp_apb_regs.mhdp_dptx_stream[0].MSA_HORIZONTAL_0_p);
+ regTransfer.addr += streamId * (uint32_t)sizeof(pD->regBase->mhdp_apb_regs.mhdp_dptx_stream[0]);
+ regTransfer.val = CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__MSA_HORIZONTAL_0_P, PCK_STUFF_HTOTAL, 0U, hParams->total) |
+ CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__MSA_HORIZONTAL_0_P, PCK_STUFF_HSTART, 0U, hStart);
+
+ return DP_WriteRegister(pD, ®Transfer);
+}
+
+static uint32_t configureMsaHorizontal1(DP_PrivateData* pD,
+ uint8_t streamId,
+ const HorizontalVerticalParams* hParams)
+{
+ DP_RegisterTransfer regTransfer = {0U};
+
+ uint32_t hSyncPolarity = (DP_SP_ACTIVE_LOW == hParams->syncPolarity) ? 1U : 0U;
+
+ regTransfer.addr = offsetof(MHDP_ApbRegs, mhdp_apb_regs.mhdp_dptx_stream[0].MSA_HORIZONTAL_1_p);
+ regTransfer.addr += streamId * (uint32_t)sizeof(pD->regBase->mhdp_apb_regs.mhdp_dptx_stream[0]);
+ regTransfer.val = CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__MSA_HORIZONTAL_1_P, PCK_STUFF_HSYNCWIDTH, 0U, hParams->sync) |
+ CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__MSA_HORIZONTAL_1_P, PCK_STUFF_HWIDTH, 0U, hParams->active) |
+ CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__MSA_HORIZONTAL_1_P, PCK_STUFF_HSYNCPOLARITY, 0U, hSyncPolarity);
+
+ return DP_WriteRegister(pD, ®Transfer);
+}
+
+static uint32_t configureDpFrontBackPorch(DP_PrivateData* pD,
+ uint8_t streamId,
+ const HorizontalVerticalParams* hParams)
+{
+ DP_RegisterTransfer regTransfer = {0U};
+
+ regTransfer.addr = offsetof(MHDP_ApbRegs, mhdp_apb_regs.mhdp_dptx_stream[0].DP_FRONT_BACK_PORCH_p);
+ regTransfer.addr += streamId * (uint32_t)sizeof(pD->regBase->mhdp_apb_regs.mhdp_dptx_stream[0]);
+ regTransfer.val = CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_FRONT_BACK_PORCH_P, BACK_PORCH, 0U, hParams->backPorch) |
+ CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_FRONT_BACK_PORCH_P, FRONT_PORCH, 0U, hParams->frontPorch);
+
+ return DP_WriteRegister(pD, ®Transfer);
+}
+
+static uint32_t configureDpHorizontal(DP_PrivateData* pD,
+ uint8_t streamId,
+ const HorizontalVerticalParams* hParams)
+{
+ DP_RegisterTransfer regTransfer = {0U};
+
+ regTransfer.addr = offsetof(MHDP_ApbRegs, mhdp_apb_regs.mhdp_dptx_stream[0].DP_HORIZONTAL_p);
+ regTransfer.addr += streamId * (uint32_t)sizeof(pD->regBase->mhdp_apb_regs.mhdp_dptx_stream[0]);
+ regTransfer.val = CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_HORIZONTAL_P, HSYNCWIDTH, 0U, hParams->sync) |
+ CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_HORIZONTAL_P, HWIDTH, 0U, hParams->active);
+
+ return DP_WriteRegister(pD, ®Transfer);
+}
+
+static uint32_t configureHorizontalParams(DP_PrivateData* pD, uint8_t streamId)
+{
+ uint32_t retVal;
+ DP_VideoFormatParams* vicParams = &(pD->videoParameters[streamId].vicParams);
+
+ HorizontalVerticalParams hParams;
+ hParams.backPorch = vicParams->hBackPorch;
+ hParams.frontPorch = vicParams->hFrontPorch;
+ hParams.sync = vicParams->hSync;
+ hParams.total = vicParams->hTotal;
+ hParams.active = vicParams->hActive;
+ hParams.syncPolarity = vicParams->hSyncPolarity;
+
+ retVal = configureMsaHorizontal0(pD, streamId, &hParams);
+
+ if (CDN_EOK == retVal) {
+ retVal = configureMsaHorizontal1(pD, streamId, &hParams);
+ }
+
+ if (CDN_EOK == retVal) {
+
+ if ((pD->videoParameters[streamId].dscEnable) && (pD->dscConfig[0].splitPanel)) {
+ hParams.frontPorch /= 2U;
+ hParams.backPorch /= 2U;
+ hParams.sync /= 2U;
+ hParams.active /= 2U;
+ }
+
+ retVal = configureDpFrontBackPorch(pD, streamId, &hParams);
+ }
+
+ if (CDN_EOK == retVal) {
+ retVal = configureDpHorizontal(pD, streamId, &hParams);
+ }
+
+ return retVal;
+}
+
+/* Set of functions used to properly configure vertical params of stream -> analog to horizontal */
+static uint32_t configureMsaVertical0(DP_PrivateData* pD,
+ uint8_t streamId,
+ const HorizontalVerticalParams* vParams)
+{
+ DP_RegisterTransfer regTransfer = {0U};
+ uint32_t vStart = vParams->sync + vParams->backPorch;
+
+ regTransfer.addr = offsetof(MHDP_ApbRegs, mhdp_apb_regs.mhdp_dptx_stream[0].MSA_VERTICAL_0_p);
+ regTransfer.addr += streamId * (uint32_t)sizeof(pD->regBase->mhdp_apb_regs.mhdp_dptx_stream[0]);
+ regTransfer.val = CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__MSA_VERTICAL_0_P, PCK_STUFF_VSTART, 0U, vStart) |
+ CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__MSA_VERTICAL_0_P, PCK_STUFF_VTOTAL, 0U, vParams->total);
+
+ return DP_WriteRegister(pD, ®Transfer);
+}
+
+static uint32_t configureMsaVertical1(DP_PrivateData* pD,
+ uint8_t streamId,
+ const HorizontalVerticalParams* vParams)
+{
+ DP_RegisterTransfer regTransfer = {0U};
+ uint32_t vSyncPolarity = (DP_SP_ACTIVE_LOW == vParams->syncPolarity) ? 1U : 0U;
+
+ regTransfer.addr = offsetof(MHDP_ApbRegs, mhdp_apb_regs.mhdp_dptx_stream[0].MSA_VERTICAL_1_p);
+ regTransfer.addr += streamId * (uint32_t)sizeof(pD->regBase->mhdp_apb_regs.mhdp_dptx_stream[0]);
+ regTransfer.val = CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__MSA_VERTICAL_1_P, PCK_STUFF_VSYNCWIDTH, 0U, vParams->sync) |
+ CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__MSA_VERTICAL_1_P, PCK_STUFF_VHEIGHT, 0U, vParams->active) |
+ CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__MSA_VERTICAL_1_P, PCK_STUFF_VSYNCPOLARITY, 0U, vSyncPolarity);
+
+ return DP_WriteRegister(pD, ®Transfer);
+}
+
+static uint32_t configureDpVertical0(DP_PrivateData* pD,
+ uint8_t streamId,
+ const HorizontalVerticalParams* vParams)
+{
+ DP_RegisterTransfer regTransfer = {0U};
+
+ uint32_t vStart = vParams->backPorch + vParams->sync;
+
+ regTransfer.addr = offsetof(MHDP_ApbRegs, mhdp_apb_regs.mhdp_dptx_stream[0].DP_VERTICAL_0_p);
+ regTransfer.addr += streamId * (uint32_t)sizeof(pD->regBase->mhdp_apb_regs.mhdp_dptx_stream[0]);
+ regTransfer.val = CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_VERTICAL_0_P, VSTART, 0U, vStart) |
+ CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_VERTICAL_0_P, VHEIGHT, 0U, vParams->active);
+ return DP_WriteRegister(pD, ®Transfer);
+}
+
+static uint32_t configureDpVertical1(DP_PrivateData* pD,
+ uint8_t streamId,
+ const HorizontalVerticalParams* vParams)
+{
+ DP_RegisterTransfer regTransfer = {0U};
+ DP_VideoFormatParams* vicParams = &(pD->videoParameters[streamId].vicParams);
+
+ regTransfer.addr = offsetof(MHDP_ApbRegs, mhdp_apb_regs.mhdp_dptx_stream[0].DP_VERTICAL_1_p);
+ regTransfer.addr += streamId * (uint32_t)sizeof(pD->regBase->mhdp_apb_regs.mhdp_dptx_stream[0]);
+ regTransfer.val = CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_VERTICAL_1_P, VTOTAL, 0U, vParams->total);
+
+ if ((0U == (vicParams->vTotal & 0x01U)) && (DP_SM_INTERLACED == vicParams->scanMode)) {
+ /* Image is interlaced and has even number of total lines. */
+ regTransfer.val |= CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_VERTICAL_1_P, VTOTAL_EVEN, 0U, 1U);
+ }
+
+ return DP_WriteRegister(pD, ®Transfer);
+}
+
+static uint32_t configureVerticalParams(DP_PrivateData* pD, uint8_t streamId)
+{
+ uint32_t retVal;
+ DP_VideoFormatParams* vicParams = &(pD->videoParameters[streamId].vicParams);
+
+ HorizontalVerticalParams vParams;
+ vParams.backPorch = vicParams->vBackPorch;
+ vParams.frontPorch = 0U; /* unused there */
+ vParams.sync = vicParams->vSync;
+ vParams.total = vicParams->vTotal;
+ vParams.active = vicParams->vActive;
+ vParams.syncPolarity = vicParams->vSyncPolarity;
+
+ if (DP_SM_INTERLACED == vicParams->scanMode) {
+ vParams.total /= 2U;
+ vParams.active /= 2U;
+ }
+
+ retVal = configureMsaVertical0(pD, streamId, &vParams);
+
+ if (CDN_EOK == retVal) {
+ retVal = configureMsaVertical1(pD, streamId, &vParams);
+ }
+
+ if (CDN_EOK == retVal) {
+ retVal = configureDpVertical0(pD, streamId, &vParams);
+ }
+
+ if (CDN_EOK == retVal) {
+ retVal = configureDpVertical1(pD, streamId, &vParams);
+ }
+
+ return retVal;
+}
+
+/**
+ * Sets fractional part of TU_VALID in RAMER_PXL_REPR register, for DSC operation.
+ */
+static void setDscTuValidFract(uint32_t *reg, uint16_t validSymF)
+{
+ uint32_t m = (uint32_t)validSymF / 10U;
+ uint32_t diff = 100U - m;
+
+ *reg = CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_FRAMER_PXL_REPR_P, DIFF, *reg, diff);
+ *reg = CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_FRAMER_PXL_REPR_P, M, *reg, m);
+}
+
+/*
+ * Get MISC0[7:5] bits correlate with bitsPerComponent and colorDepth
+ * Return CDN_EINVAL when bitPerComponent incorrect
+ */
+static uint32_t getColorDepth(uint8_t bitsPerComponent, uint8_t* colorDepth, uint8_t* miscBpc)
+{
+ uint32_t retVal = CDN_EOK;
+
+ switch (bitsPerComponent)
+ {
+ case 6U:
+ *colorDepth = 0x01U;
+ *miscBpc = 0U;
+ break;
+ case 8U:
+ *colorDepth = 0x02U;
+ *miscBpc = 1U;
+ break;
+ case 10U:
+ *colorDepth = 0x04U;
+ *miscBpc = 2U;
+ break;
+ case 12U:
+ *colorDepth = 0x08U;
+ *miscBpc = 3U;
+ break;
+ case 16U:
+ *colorDepth = 0x10U;
+ *miscBpc = 4U;
+ break;
+ default:
+ retVal = CDN_EINVAL;
+ break;
+ }
+
+ return retVal;
+}
+
+static uint8_t getMisc0(const DP_VideoParameters* videoParameters, uint8_t miscBpc)
+{
+ uint8_t btType = (uint8_t)videoParameters->btType;
+ uint8_t misc0;
+
+ switch (videoParameters->pxEncFormat)
+ {
+ /* values are being set according to DisplayPort standard. */
+ case DP_PXENC_PXL_RGB:
+ case DP_PXENC_Y_ONLY:
+ misc0 = (miscBpc << 5);
+ break;
+ case DP_PXENC_YCBCR_4_4_4:
+ misc0 = (6U << 1) | (btType << 4) | (miscBpc << 5);
+ break;
+ case DP_PXENC_YCBCR_4_2_2:
+ misc0 = (5U << 1) | (btType << 4) | (miscBpc << 5);
+ break;
+ case DP_PXENC_YCBCR_4_2_0:
+ misc0 = 0U; /* values are ignored for 4:2:0 */
+ break;
+ default:
+ misc0 = 0U;
+ break;
+ }
+
+ if (videoParameters->forceMiscIgnoreBit) {
+ misc0 = 0U;
+ }
+
+ return misc0;
+}
+
+static uint8_t getMisc1(const DP_VideoParameters* videoParameters)
+{
+ uint8_t misc1;
+ const DP_VideoFormatParams* vicParams;
+
+ if ((DP_PXENC_YCBCR_4_2_0 == videoParameters->pxEncFormat) ||
+ (videoParameters->forceMiscIgnoreBit)) {
+ /* When this bit has been set, VSC SDP has to be used instead, to */
+ /* indicate pixel encoding / colorimetry. This is required for 4:2:0. */
+ misc1 = (1U << 6);
+ } else {
+ vicParams = &(videoParameters->vicParams);
+ misc1 = 0U;
+
+ if (DP_PXENC_Y_ONLY == videoParameters->pxEncFormat) {
+ misc1 |= (1U << 7);
+ }
+
+ if ((0U == (vicParams->vTotal & 0x01U)) &&
+ (DP_SM_INTERLACED == vicParams->scanMode)) {
+ /* Image is interlaced and has even number of total lines. */
+ misc1 |= 1U;
+ }
+ }
+ return misc1;
+}
+
+static uint32_t configureColorimetry(DP_PrivateData* pD, uint8_t streamId, uint16_t validSymF)
+{
+ DP_VideoParameters* videoParameters = &(pD->videoParameters[streamId]);
+ uint32_t retVal;
+ DP_RegisterTransfer regTransfer = {0U};
+ uint8_t colorDepth;
+ uint8_t misc0;
+ uint8_t misc1;
+ uint8_t miscBpc;
+
+ retVal = getColorDepth(videoParameters->bitsPerSubpixel, &colorDepth, &miscBpc);
+
+ if (CDN_EOK == retVal)
+ {
+ regTransfer.addr = offsetof(MHDP_ApbRegs, mhdp_apb_regs.mhdp_dptx_stream[0].DP_FRAMER_PXL_REPR_p);
+ regTransfer.addr += streamId * (uint32_t)sizeof(pD->regBase->mhdp_apb_regs.mhdp_dptx_stream[0]);
+ regTransfer.val = CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_FRAMER_PXL_REPR_P, COLOR_DEPTH, 0U, colorDepth) |
+ CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_FRAMER_PXL_REPR_P, PXL_ENC_FORMAT, 0U, videoParameters->pxEncFormat);
+
+ if ((!pD->mstEnabled) && (pD->videoParameters[streamId].dscEnable)) {
+ setDscTuValidFract(&(regTransfer.val), validSymF);
+ }
+
+ retVal = DP_WriteRegister(pD, ®Transfer);
+ }
+
+ if (CDN_EOK == retVal)
+ {
+ misc0 = getMisc0(videoParameters, miscBpc);
+ misc1 = getMisc1(videoParameters);
+
+ regTransfer.addr = offsetof(MHDP_ApbRegs, mhdp_apb_regs.mhdp_dptx_stream[0].MSA_MISC_p);
+ regTransfer.addr += streamId * (uint32_t)sizeof(pD->regBase->mhdp_apb_regs.mhdp_dptx_stream[0]);
+ regTransfer.val = CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__MSA_MISC_P, MSA_MISC0, 0U, misc0) |
+ CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__MSA_MISC_P, MSA_MISC1, 0U, misc1);
+ retVal = DP_WriteRegister(pD, ®Transfer);
+ }
+
+ return retVal;
+}
+
+static uint32_t configureByteCount(DP_PrivateData* pD, uint8_t streamId)
+{
+ uint32_t retVal;
+
+ DP_RegisterTransfer regTransfer = {0U};
+ uint32_t bytesInChunk;
+ uint8_t chunkCount = 1U;
+ uint32_t byteCount; /* Byte Count parameter calculated, when DSC is not being used. */
+
+ regTransfer.addr = offsetof(MHDP_ApbRegs, mhdp_apb_regs.mhdp_dptx_stream[0].DP_BYTE_COUNT_p);
+ regTransfer.addr += streamId * (uint32_t)sizeof(pD->regBase->mhdp_apb_regs.mhdp_dptx_stream[0]);
+
+ if (pD->videoParameters[streamId].dscEnable)
+ {
+ if (pD->mstEnabled) {
+ bytesInChunk = (pD->dscConfig[streamId].chunkSize / 4U) + 1U;
+ } else {
+ bytesInChunk = (pD->dscConfig[streamId].chunkSize / pD->linkState.laneCount) + 1U;
+ }
+
+ if (pD->dscConfig[streamId].splitPanel) {
+ chunkCount = 2U;
+ }
+
+ regTransfer.val = CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_BYTE_COUNT_P, BYTE_COUNT, 0U, bytesInChunk * chunkCount) |
+ CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_BYTE_COUNT_P, BYTES_IN_CHUNK, 0U, bytesInChunk);
+ } else {
+ byteCount = calcByteCount(pD, streamId);
+ regTransfer.val = CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_BYTE_COUNT_P, BYTE_COUNT, 0U, byteCount);
+ }
+
+ retVal = DP_WriteRegister(pD, ®Transfer);
+
+ return retVal;
+}
+
+static uint32_t configureBndHsync2Vsync(DP_PrivateData* pD, uint8_t streamId)
+{
+ DP_RegisterTransfer regTransfer = {0U};
+
+ regTransfer.addr = offsetof(MHDP_ApbRegs, mhdp_apb_regs.mhdp_vif_ctrl[0].BND_HSYNC2VSYNC_p);
+ regTransfer.addr += streamId * (uint32_t)sizeof(pD->regBase->mhdp_apb_regs.mhdp_vif_ctrl[0]);
+ regTransfer.val = CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__BND_HSYNC2VSYNC_P, IP_VIF_BYPASS, 0U, 1U);
+
+ if (DP_SM_INTERLACED == pD->videoParameters[streamId].vicParams.scanMode) {
+ regTransfer.val |= CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__BND_HSYNC2VSYNC_P, IP_DTCT_WIN, 0U, 0x20U)
+ | CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__BND_HSYNC2VSYNC_P, IP_DET_EN, 0U, 1U);
+ }
+
+ regTransfer.val |= CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__BND_HSYNC2VSYNC_P,
+ IP_VIF_ALIGNMENT,
+ 0U,
+ (uint8_t)pD->videoParameters[streamId].alignment);
+
+ return DP_WriteRegister(pD, ®Transfer);
+}
+
+static uint32_t configureHsync2VsyncPolCtrl(DP_PrivateData* pD, uint8_t streamId)
+{
+ DP_RegisterTransfer regTransfer = {0U};
+
+ regTransfer.addr = offsetof(MHDP_ApbRegs, mhdp_apb_regs.mhdp_vif_ctrl[0].HSYNC2VSYNC_POL_CTRL_p);
+ regTransfer.addr += streamId * (uint32_t)sizeof(pD->regBase->mhdp_apb_regs.mhdp_vif_ctrl[0]);
+
+ if (DP_SP_ACTIVE_LOW == pD->videoParameters[streamId].vicParams.hSyncPolarity) {
+ regTransfer.val |= CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__HSYNC2VSYNC_POL_CTRL_P, HPOL, 0U, 1U);
+ }
+
+ if (DP_SP_ACTIVE_LOW == pD->videoParameters[streamId].vicParams.vSyncPolarity) {
+ regTransfer.val |= CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__HSYNC2VSYNC_POL_CTRL_P, VPOL, 0U, 1U);
+ }
+
+ return DP_WriteRegister(pD, ®Transfer);
+}
+
+static uint32_t configureDpFramerPxlRepr(DP_PrivateData* pD, uint8_t streamId)
+{
+ DP_RegisterTransfer regTransfer = {0U};
+ DP_VideoFormatParams* vicParams = &(pD->videoParameters[streamId].vicParams);
+
+ regTransfer.addr = offsetof(MHDP_ApbRegs, mhdp_apb_regs.mhdp_dptx_stream[0].DP_FRAMER_SP_p);
+ regTransfer.addr += streamId * (uint32_t)sizeof(pD->regBase->mhdp_apb_regs.mhdp_dptx_stream[0]);
+
+ if (DP_SP_ACTIVE_LOW == vicParams->hSyncPolarity) {
+ regTransfer.val |= CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_FRAMER_SP_P, HSP, 0U, 1U);
+ }
+
+ if (DP_SP_ACTIVE_LOW == vicParams->vSyncPolarity) {
+ regTransfer.val |= CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_FRAMER_SP_P, VSP, 0U, 1U);
+ }
+
+ if (DP_SM_INTERLACED == vicParams->scanMode) {
+ regTransfer.val |= CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_FRAMER_SP_P, INTERLACE_EN, 0U, 1U);
+ }
+
+ return DP_WriteRegister(pD, ®Transfer);
+}
+
+static uint32_t setVerticalBlankingInterlaced(DP_PrivateData* pD, uint8_t streamId)
+{
+ const uint8_t vbIdInterlacedBitPos = 2U;
+ uint32_t addr = offsetof(MHDP_ApbRegs, mhdp_apb_regs.mhdp_dptx_stream[0].DP_VB_ID_p);
+ addr += streamId * (uint32_t)sizeof(pD->regBase->mhdp_apb_regs.mhdp_dptx_stream[0]);
+ DP_WriteFieldRequest req;
+
+ req.addr = addr;
+ req.startBit = vbIdInterlacedBitPos;
+ req.bitCount = 1U;
+ req.val = 0U;
+
+ if (DP_SM_INTERLACED == pD->videoParameters[streamId].vicParams.scanMode) {
+ req.val = 1U << vbIdInterlacedBitPos;
+ }
+
+ return DP_WriteField(pD, &req);
+
+}
+
+static uint32_t configureSync(DP_PrivateData* pD, uint8_t streamId)
+{
+ uint32_t retVal;
+
+ retVal = configureBndHsync2Vsync(pD, streamId);
+
+ if (CDN_EOK == retVal) {
+ retVal = configureHsync2VsyncPolCtrl(pD, streamId);
+ }
+
+ if (CDN_EOK == retVal) {
+ retVal = configureDpFramerPxlRepr(pD, streamId);
+ }
+
+ if (CDN_EOK == retVal) {
+ retVal = setVerticalBlankingInterlaced(pD, streamId);
+ }
+
+ return retVal;
+}
+
+static uint32_t configureSdpBlocking(DP_PrivateData* pD, uint8_t streamId, bool fecEnabled)
+{
+ uint32_t retVal;
+
+ DP_RegisterTransfer regTransfer = {0U};
+ float64_t targAvgSlots = 0.0; /* calculated target average slots for stream. Applicable only for MST. */
+ uint32_t vblankSdpCycles; /* block SDP scheduling after specified cycles after BS/VB-ID during vertical blank. */
+ uint32_t hblankSdpCycles; /* block SDP scheduling after specified cycles after BS/VB-ID during horizontal blank. */
+
+ if (pD->mstEnabled) {
+ targAvgSlots = calculateTargetAverageSlots(pD, streamId, fecEnabled);
+ }
+
+ vblankSdpCycles = calcSdpBlockVblank(pD, streamId, targAvgSlots);
+ hblankSdpCycles = calcSdpBlockHblank(pD, streamId, targAvgSlots);
+
+ regTransfer.addr = offsetof(MHDP_ApbRegs, mhdp_apb_regs.mhdp_dptx_stream[0].DP_BLOCK_SDP_p);
+ regTransfer.addr += streamId * (uint32_t)sizeof(pD->regBase->mhdp_apb_regs.mhdp_dptx_stream[0]);
+ regTransfer.val = CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_BLOCK_SDP_P, BS_SDP_STOP_OVR_EN, 0U, 1U)
+ | CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_BLOCK_SDP_P, BS_SDP_STOP_ACTIVE, 0U, hblankSdpCycles)
+ | CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_BLOCK_SDP_P, BS_SDP_STOP_BLANK, 0U, vblankSdpCycles);
+
+ retVal = DP_WriteRegister(pD, ®Transfer);
+
+ return retVal;
+}
+
+static uint32_t startStream(DP_PrivateData* pD, uint8_t streamId)
+{
+ DP_RegisterTransfer regTransfer = {0U};
+
+ regTransfer.addr = offsetof(MHDP_ApbRegs, mhdp_apb_regs.mhdp_dptx_stream[0].STREAM_CONFIG_p);
+ regTransfer.addr += streamId * (uint32_t)sizeof(pD->regBase->mhdp_apb_regs.mhdp_dptx_stream[0]);
+ regTransfer.val = CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__STREAM_CONFIG_P, STREAM_EN, 0U, 1U);
+
+ return DP_WriteRegister(pD, ®Transfer);
+}
+
+static uint32_t configureVicParams(DP_PrivateData* pD,
+ uint8_t streamId,
+ const DP_VideoParameters* videoParameters)
+{
+ uint32_t retVal = CDN_EOK;
+ uint8_t i;
+ uint16_t validSymF = 0U; /* valid symbols per TU - fractional part (thousandth parts, 0 - 999) */
+
+ uint32_t (*config[5]) (DP_PrivateData*, uint8_t) = {
+ startStream, /* Starting stream early, proper place to be determined. Temporary solution. */
+ configureHorizontalParams,
+ configureVerticalParams,
+ configureByteCount,
+ configureSync
+ };
+
+ pD->videoParameters[streamId] = *videoParameters;
+
+ if (!pD->mstEnabled) {
+ retVal = configureSstVideoParams(pD, &validSymF, pD->fecEnabled);
+ }
+
+ if (CDN_EOK == retVal) {
+ for (i = 0U; i < (sizeof(config) / sizeof(config[0])); i++) {
+ retVal = config[i](pD, streamId);
+ if (CDN_EOK != retVal) {
+ break;
+ }
+ }
+ }
+
+ if (CDN_EOK == retVal) {
+ retVal = configureColorimetry(pD, streamId, validSymF);
+ }
+
+ if (CDN_EOK == retVal) {
+ retVal = configureSdpBlocking(pD, streamId, pD->fecEnabled);
+ }
+
+ return retVal;
+}
+
+/* Check correctness of some video parameters. */
+static uint32_t checkVideoParams(const DP_VideoParameters *parameters)
+{
+ uint32_t retVal = CDN_EOK;
+
+ if (DP_PXENC_PXL_RGB == parameters->pxEncFormat) {
+ /* For RGB encoding, active video width has to be multiple of 2. */
+ if (0U != (parameters->vicParams.hActive % 2U)) {
+ retVal = CDN_EINVAL;
+ }
+ } else {
+ /* For other encodings, active video width has to be multiple of 16. */
+ if (0U != (parameters->vicParams.hActive % 16U)) {
+ retVal = CDN_EINVAL;
+ }
+ }
+
+ return retVal;
+}
+
+static uint32_t checkPhyInit(DP_PrivateData* pD)
+{
+ uint32_t retVal;
+
+ /* In case PHY was initialized directly through PHY driver, valid link */
+ /* parameters will only be known to PHY driver - need to fetch them first. */
+ retVal = fetchLinkState(pD);
+ if (CDN_EOK == retVal) {
+ if (0U == pD->linkState.laneCount) {
+ /* Not even PHY initialization was done since PHY driver's init. */
+ retVal = CDN_ENOENT;
+ }
+ }
+
+ return retVal;
+}
+static uint32_t setVifClock(DP_PrivateData* pD, uint32_t streamId, bool enable)
+{
+ DP_RegisterTransfer regTransfer = {0U};
+ uint32_t reg;
+ uint32_t retVal;
+ uint8_t clockEnable = (enable) ? 1U : 0U;
+
+ regTransfer.addr = offsetof(MHDP_ApbRegs, mhdp_apb_regs.source_dptx_car_p);
+ retVal = DP_ReadRegister(pD, ®Transfer);
+
+ if (retVal == CDN_EOK) {
+ reg = regTransfer.val;
+
+ switch (streamId) {
+ case 0U:
+ reg = CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P, CFG_DPTX_VIF_CLK_EN, reg, clockEnable);
+ reg = CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P, CFG_DPTX_VIF_CLK_RSTN_EN, reg, clockEnable);
+ break;
+ case 1U:
+ reg = CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P, CFG_DPTX_VIF_CLK_EN1, reg, clockEnable);
+ reg = CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P, CFG_DPTX_VIF_CLK_RSTN_EN1, reg, clockEnable);
+ break;
+ case 2U:
+ reg = CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P, CFG_DPTX_VIF_CLK_EN2, reg, clockEnable);
+ reg = CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P, CFG_DPTX_VIF_CLK_RSTN_EN2, reg, clockEnable);
+ break;
+ /*
+ * 'Default' statement is called only for 'streamId' = 3U. 'streamId' is in range <0,3> and
+ * out of range should be checked by sanity function.
+ */
+ default:
+ reg = CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P, CFG_DPTX_VIF_CLK_EN3, reg, clockEnable);
+ reg = CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P, CFG_DPTX_VIF_CLK_RSTN_EN3, reg, clockEnable);
+ break;
+ }
+
+ regTransfer.val = reg;
+ retVal = DP_WriteRegister(pD, ®Transfer);
+ }
+
+ return retVal;
+}
+
+static uint32_t getVifClock(DP_PrivateData* pD, uint32_t streamId, bool* enable)
+{
+ DP_RegisterTransfer regTransfer = {0U};
+ uint32_t reg;
+ uint32_t retVal;
+ uint32_t clockEnable = 0U;
+
+ regTransfer.addr = offsetof(MHDP_ApbRegs, mhdp_apb_regs.source_dptx_car_p);
+ retVal = DP_ReadRegister(pD, ®Transfer);
+
+ if (retVal == CDN_EOK) {
+ reg = regTransfer.val;
+
+ switch (streamId) {
+ case 0U:
+ clockEnable = CPS_FLD_READ(MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P, CFG_DPTX_VIF_CLK_EN, reg);
+ break;
+ case 1U:
+ clockEnable = CPS_FLD_READ(MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P, CFG_DPTX_VIF_CLK_EN1, reg);
+ break;
+ case 2U:
+ clockEnable = CPS_FLD_READ(MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P, CFG_DPTX_VIF_CLK_EN2, reg);
+ break;
+ /*
+ * 'Default' statement is called only for 'streamId' = 3U. 'streamId' is in range <0,3> and
+ * out of range should be checked by sanity function.
+ */
+ default:
+ clockEnable = CPS_FLD_READ(MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P, CFG_DPTX_VIF_CLK_EN3, reg);
+ break;
+ }
+
+ if (clockEnable == 0U) {
+ *enable = false;
+ } else {
+ *enable = true;
+ }
+
+ }
+
+ return retVal;
+}
+
+static uint32_t setAifClock(DP_PrivateData* pD, uint32_t streamId, bool enable)
+{
+ DP_RegisterTransfer regTransfer = {0U};
+ uint32_t reg;
+ uint32_t retVal;
+ uint8_t clockEnable = (enable) ? 1U : 0U;
+
+ regTransfer.addr = offsetof(MHDP_ApbRegs, mhdp_apb_regs.source_aif_car_p);
+ retVal = DP_ReadRegister(pD, ®Transfer);
+
+ if (retVal == CDN_EOK) {
+ reg = regTransfer.val;
+
+ switch (streamId) {
+ case 0U:
+ reg = CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__SOURCE_AIF_CAR_P, SOURCE_AIF_PKT_CLK_EN, reg, clockEnable);
+ reg = CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__SOURCE_AIF_CAR_P, SOURCE_AIF_PKT_CLK_RSTN_EN, reg, clockEnable);
+ break;
+ case 1U:
+ reg = CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__SOURCE_AIF_CAR_P, SOURCE_AIF_PKT_CLK_EN1, reg, clockEnable);
+ reg = CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__SOURCE_AIF_CAR_P, SOURCE_AIF_PKT_CLK_RSTN_EN1, reg, clockEnable);
+ break;
+ case 2U:
+ reg = CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__SOURCE_AIF_CAR_P, SOURCE_AIF_PKT_CLK_EN2, reg, clockEnable);
+ reg = CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__SOURCE_AIF_CAR_P, SOURCE_AIF_PKT_CLK_RSTN_EN2, reg, clockEnable);
+ break;
+ /*
+ * 'Default' statement is called only for 'streamId' = 3U. 'streamId' is in range <0,3> and
+ * out of range should be checked by sanity function.
+ */
+ default:
+ reg = CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__SOURCE_AIF_CAR_P, SOURCE_AIF_PKT_CLK_EN3, reg, clockEnable);
+ reg = CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__SOURCE_AIF_CAR_P, SOURCE_AIF_PKT_CLK_RSTN_EN3, reg, clockEnable);
+ break;
+ }
+
+ regTransfer.val = reg;
+ retVal = DP_WriteRegister(pD, ®Transfer);
+ }
+
+ return retVal;
+}
+
+static uint32_t getAifClock(DP_PrivateData* pD, uint32_t streamId, bool* enable)
+{
+ DP_RegisterTransfer regTransfer = {0U};
+ uint32_t reg;
+ uint32_t retVal;
+ uint32_t clockEnable = 0U;
+
+ regTransfer.addr = offsetof(MHDP_ApbRegs, mhdp_apb_regs.source_aif_car_p);
+ retVal = DP_ReadRegister(pD, ®Transfer);
+ if (retVal == CDN_EOK) {
+ reg = regTransfer.val;
+
+ switch (streamId) {
+ case 0U:
+ clockEnable = CPS_FLD_READ(MHDP__MHDP_APB_REGS__SOURCE_AIF_CAR_P, SOURCE_AIF_PKT_CLK_EN, reg);
+ break;
+ case 1U:
+ clockEnable = CPS_FLD_READ(MHDP__MHDP_APB_REGS__SOURCE_AIF_CAR_P, SOURCE_AIF_PKT_CLK_EN1, reg);
+ break;
+ case 2U:
+ clockEnable = CPS_FLD_READ(MHDP__MHDP_APB_REGS__SOURCE_AIF_CAR_P, SOURCE_AIF_PKT_CLK_EN2, reg);
+ break;
+ /*
+ * 'Default' statement is called only for 'streamId' = 3U. 'streamId' is in range <0,3> and
+ * out of range should be checked by sanity function.
+ */
+ default:
+ clockEnable = CPS_FLD_READ(MHDP__MHDP_APB_REGS__SOURCE_AIF_CAR_P, SOURCE_AIF_PKT_CLK_EN3, reg);
+ break;
+
+ }
+
+ if (clockEnable == 0U) {
+ *enable = false;
+ } else {
+ *enable = true;
+ }
+
+ }
+
+ return retVal;
+}
+
+static uint32_t setPktClock(DP_PrivateData* pD, uint32_t streamId, bool enable)
+{
+ DP_RegisterTransfer regTransfer = {0U};
+ uint32_t retVal;
+ uint32_t reg;
+ uint8_t clockEnable = (enable) ? 1U : 0U;
+
+ regTransfer.addr = offsetof(MHDP_ApbRegs, mhdp_apb_regs.source_pkt_car_p);
+ retVal = DP_ReadRegister(pD, ®Transfer);
+
+ if (retVal == CDN_EOK) {
+ reg = regTransfer.val;
+
+ switch (streamId) {
+ case 0U:
+ reg = CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P, SOURCE_PKT_DATA_CLK_EN, reg, clockEnable);
+ reg = CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P, SOURCE_PKT_DATA_RSTN_EN, reg, clockEnable);
+ break;
+ case 1U:
+ reg = CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P, SOURCE_PKT_DATA_CLK_EN1, reg, clockEnable);
+ reg = CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P, SOURCE_PKT_DATA_RSTN_EN1, reg, clockEnable);
+ break;
+ case 2U:
+ reg = CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P, SOURCE_PKT_DATA_CLK_EN2, reg, clockEnable);
+ reg = CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P, SOURCE_PKT_DATA_RSTN_EN2, reg, clockEnable);
+ break;
+ /*
+ * 'Default' statement is called only for 'streamId' = 3U. 'streamId' is in range <0,3> and
+ * out of range should be checked by sanity function.
+ */
+ default:
+ reg = CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P, SOURCE_PKT_DATA_CLK_EN3, reg, clockEnable);
+ reg = CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P, SOURCE_PKT_DATA_RSTN_EN3, reg, clockEnable);
+ break;
+
+ }
+
+ regTransfer.val = reg;
+ retVal = DP_WriteRegister(pD, ®Transfer);
+ }
+
+ return retVal;
+}
+
+static uint32_t getPktClock(DP_PrivateData* pD, uint32_t streamId, bool *enable)
+{
+ DP_RegisterTransfer regTransfer = {0U};
+ uint32_t retVal;
+ uint32_t reg;
+ uint32_t clockEnable = 0U;
+
+ regTransfer.addr = offsetof(MHDP_ApbRegs, mhdp_apb_regs.source_pkt_car_p);
+ retVal = DP_ReadRegister(pD, ®Transfer);
+
+ if (retVal == CDN_EOK) {
+ reg = regTransfer.val;
+
+ switch (streamId) {
+ case 0U:
+ clockEnable = CPS_FLD_READ(MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P, SOURCE_PKT_DATA_CLK_EN, reg);
+ break;
+ case 1U:
+ clockEnable = CPS_FLD_READ(MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P, SOURCE_PKT_DATA_CLK_EN1, reg);
+ break;
+ case 2U:
+ clockEnable = CPS_FLD_READ(MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P, SOURCE_PKT_DATA_CLK_EN2, reg);
+ break;
+ /*
+ * 'Default' statement is called only for 'streamId' = 3U. 'streamId' is in range <0,3> and
+ * out of range should be checked by sanity function.
+ */
+ default:
+ clockEnable = CPS_FLD_READ(MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P, SOURCE_PKT_DATA_CLK_EN3, reg);
+ break;
+ }
+
+ if (clockEnable == 0U) {
+ *enable = false;
+ } else {
+ *enable = true;
+ }
+
+ }
+
+ return retVal;
+}
+
+/**
+ * Set FEC ready in sink in DPCD registers
+ */
+static uint32_t sinkSetFecReady(DP_PrivateData* pD, bool enable)
+{
+ uint32_t retVal;
+
+ DP_DpcdTransfer transfer;
+ uint8_t dpcdBuff[1];
+ uint8_t fecCaps;
+
+ transfer.addr = DP_DPCD_FEC_CAPABILITY;
+ transfer.size = 1U;
+ transfer.buff = dpcdBuff;
+
+ retVal = DP_ReadDpcd(pD, &transfer);
+
+ if (CDN_EOK == retVal) {
+ fecCaps = transfer.buff[0];
+ if ((fecCaps & DP_DPCD_FEC_CAPABILITY_FEC_CAPABLE_MASK) == 0U) {
+ retVal = CDN_ENOTSUP;
+ }
+ }
+
+ if (CDN_EOK == retVal) {
+ transfer.addr = DP_DPCD_FEC_CONFIGURATION;
+ transfer.size = 1U;
+ retVal = DP_ReadDpcd(pD, &transfer);
+ }
+
+ if (CDN_EOK == retVal)
+ {
+ if (enable) {
+ transfer.buff[0] |= (uint8_t)DP_DPCD_FEC_CONFIGURATION_FEC_READY;
+ } else {
+ transfer.buff[0] &= ~((uint8_t)DP_DPCD_FEC_CONFIGURATION_FEC_READY);
+ }
+
+ transfer.addr = DP_DPCD_FEC_CONFIGURATION;
+ transfer.size = 1U;
+ retVal = DP_WriteDpcd(pD, &transfer);
+ }
+
+ return retVal;
+}
+
+static uint32_t isSstVideoOn(DP_PrivateData* pD, bool *isOn)
+{
+ uint32_t retVal;
+
+ DP_RegisterTransfer regTransfer = {0U};
+
+ regTransfer.addr = offsetof(MHDP_ApbRegs, mhdp_apb_regs.DP_FRAMER_GLOBAL_CONFIG_p);
+ retVal = DP_ReadRegister(pD, ®Transfer);
+
+ if (CDN_EOK == retVal) {
+ if ((regTransfer.val & MHDP__MHDP_APB_REGS__DP_FRAMER_GLOBAL_CONFIG_P__NO_VIDEO_MASK) == 0U) {
+ *isOn = true;
+ } else {
+ *isOn = false;
+ }
+ }
+
+ return retVal;
+}
+
+static uint32_t checkIfCanSetFec(DP_PrivateData* pD, bool fecEnable)
+{
+ bool isOn;
+ uint32_t retVal;
+
+ retVal = DP_SetFecEnableSF(pD);
+
+ if (retVal == CDN_EOK) {
+ if (!pD->mstEnabled) {
+ retVal = isSstVideoOn(pD, &isOn);
+ } else {
+ retVal = DP_MST_IsAnyVideoOn(pD, &isOn);
+ }
+ }
+
+ if (retVal == CDN_EOK) {
+ if (isOn) {
+ DbgMsg(DBG_GEN_MSG, DBG_CRIT, "Video must be disabled to change FEC configuration\n");
+ retVal = CDN_EIO;
+ }
+ }
+
+ if (CDN_EOK == retVal) {
+ if (fecEnable == pD->fecEnabled) {
+ /* Nothing to do. New setting equals current setting. */
+ retVal = CDN_EAGAIN;
+ }
+ }
+
+ return retVal;
+}
+
+static uint32_t configureSdpBlockingForStreams(DP_PrivateData* pD, bool fecEnable)
+{
+ uint32_t retVal = CDN_EOK;
+ uint8_t i;
+
+ if (pD->mstEnabled) {
+ for (i = 0U; i < DP_MAX_NUMBER_OF_STREAMS; i++) {
+
+ if (pD->streamEnabled[i]) {
+ retVal = configureSdpBlocking(pD, i, fecEnable);
+ }
+
+ if (CDN_EOK != retVal) {
+ break;
+ }
+ }
+ } else {
+ retVal = configureSdpBlocking(pD, 0U, fecEnable);
+ }
+
+ return retVal;
+}
+
+/*Set numerator and diffrence beetween denominator and numerator of ratio.
+ * It describes valid symbols distribution. Only if DSC is enabled */
+static uint32_t setValidSymDistRatio(DP_PrivateData* pD, uint16_t validSymF)
+{
+ DP_WriteFieldRequest req = {0U};
+
+ req.addr = offsetof(MHDP_ApbRegs, mhdp_apb_regs.mhdp_dptx_stream[0].DP_FRAMER_PXL_REPR_p);
+ req.startBit = MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_FRAMER_PXL_REPR_P__M_SHIFT;
+ /* bit count is calculated, taking into consideration gap between fields. */
+ req.bitCount = (MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_FRAMER_PXL_REPR_P__DIFF_SHIFT -
+ MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_FRAMER_PXL_REPR_P__M_SHIFT) +
+ MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_FRAMER_PXL_REPR_P__DIFF_WIDTH;
+
+ setDscTuValidFract(&(req.val), validSymF);
+
+ return DP_WriteField(pD, &req);
+}
+
+static uint32_t setFecEnable(DP_PrivateData* pD, bool fecEnable)
+{
+ uint32_t retVal = CDN_EOK;
+ uint16_t validSymF;
+ DP_WriteFieldRequest req = {0U};
+
+ bool sstAndVideoParamsSet = (!pD->mstEnabled) && (pD->sstVicSet);
+ bool dscEnable = pD->videoParameters[0].dscEnable;
+
+ if (sstAndVideoParamsSet) {
+ retVal = configureSstVideoParams(pD, &validSymF, fecEnable);
+
+ if ((CDN_EOK == retVal) && (dscEnable)) {
+ retVal = setValidSymDistRatio(pD, validSymF);
+ }
+ }
+
+ if (CDN_EOK == retVal) {
+ retVal = configureSdpBlockingForStreams(pD, fecEnable);
+ }
+
+ if (CDN_EOK == retVal) {
+
+ uint32_t reqValue = (fecEnable) ? 1U : 0U;
+
+ req.addr = offsetof(MHDP_ApbRegs, mhdp_apb_regs.DPTX_FEC_CTRL_p);
+ req.startBit = MHDP__MHDP_APB_REGS__DPTX_FEC_CTRL_P__CFG_FEC_EN_SHIFT;
+ req.bitCount = MHDP__MHDP_APB_REGS__DPTX_FEC_CTRL_P__CFG_FEC_EN_WIDTH;
+ req.val = CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__DPTX_FEC_CTRL_P, CFG_FEC_EN, 0U, reqValue);
+ retVal = DP_WriteField(pD, &req);
+ }
+
+ return retVal;
+}
+
+/**
+ * Set FEC ready in source register
+ */
+static uint32_t sourceSetFecReady(DP_PrivateData* pD, bool enable)
+{
+ uint32_t retVal;
+
+ DP_RegisterTransfer regTransfer = {0U};
+
+ regTransfer.addr = offsetof(MHDP_ApbRegs, mhdp_apb_regs.DPTX_FEC_CTRL_p);
+ retVal = DP_ReadRegister(pD, ®Transfer);
+
+ if (CDN_EOK == retVal)
+ {
+ uint32_t reg = (enable) ? 1U : 0U;
+
+ regTransfer.val = CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__DPTX_FEC_CTRL_P,
+ CFG_FEC_READY,
+ regTransfer.val,
+ reg);
+ regTransfer.addr = offsetof(MHDP_ApbRegs, mhdp_apb_regs.DPTX_FEC_CTRL_p);
+
+ retVal = DP_WriteRegister(pD, ®Transfer);
+ }
+ return retVal;
+}
+
+/**
+ * Get value of KEEP_ALIVE register and update it in pD.
+ * Return true, if it has changed.
+ */
+static bool updateAlive(DP_PrivateData* pD)
+{
+ uint32_t readVal;
+ uint8_t aliveVal;
+ bool updated = false;
+
+ readVal = CPS_REG_READ(&pD->regBase->mhdp_apb_regs.KEEP_ALIVE_p);
+ aliveVal = (uint8_t)(CPS_FLD_READ(MHDP__MHDP_APB_REGS__KEEP_ALIVE_P, KEEP_ALIVE_CNT, readVal));
+ if (aliveVal != pD->lastAlive)
+ {
+ updated = true;
+ pD->lastAlive = aliveVal;
+ }
+ return updated;
+}
+
+/**
+ * Reads signature and functionality registers
+ */
+
+static void updateSignatures(DP_PrivateData* pD)
+{
+ uint32_t readVal;
+
+ readVal = CPS_REG_READ(&pD->regBase->mhdp_apb_regs.CDNS_DID_p);
+ pD->hwConfig.ipPartNumber = readVal;
+
+ readVal = CPS_REG_READ(&pD->regBase->mhdp_apb_regs.CDNS_RID0_p);
+ pD->hwConfig.ipVersion = (uint16_t) CPS_FLD_READ(MHDP__MHDP_APB_REGS__CDNS_RID0_P, IP_VERSION, readVal);
+
+ readVal = CPS_REG_READ(&pD->regBase->mhdp_apb_regs.CDNS_RID1_p);
+ pD->hwConfig.phyVersion = (uint16_t) CPS_FLD_READ(MHDP__MHDP_APB_REGS__CDNS_RID1_P, PHY_VERSION, readVal);
+ pD->hwConfig.auxVersion = (uint16_t) CPS_FLD_READ(MHDP__MHDP_APB_REGS__CDNS_RID1_P, AUX_VERSION, readVal);
+}
+
+static void updateHardwareConfiguration(DP_PrivateData* pD)
+{
+ uint32_t readVal;
+
+ updateSignatures(pD);
+
+ readVal = CPS_REG_READ(&pD->regBase->mhdp_apb_regs.CDNS_CFGS0_p);
+ pD->hwConfig.mainConfigType = (uint8_t) CPS_FLD_READ(MHDP__MHDP_APB_REGS__CDNS_CFGS0_P, IP_NUMBER_CONFIGURATION, readVal);
+ pD->hwConfig.ipFamilyCode = (uint8_t) CPS_FLD_READ(MHDP__MHDP_APB_REGS__CDNS_CFGS0_P, IP_NUMBER_FAMILY, readVal);
+ pD->hwConfig.dscSupport = (CPS_FLD_READ(MHDP__MHDP_APB_REGS__CDNS_CFGS0_P, DSC_SUPPORT, readVal) > 0U);
+ pD->hwConfig.asfSupport = (CPS_FLD_READ(MHDP__MHDP_APB_REGS__CDNS_CFGS0_P, ASF_SUPPORT, readVal) > 0U);
+ pD->hwConfig.videoStreams = (uint8_t) CPS_FLD_READ(MHDP__MHDP_APB_REGS__CDNS_CFGS0_P, VIDEO_STREAM_NUMBER, readVal);
+ pD->hwConfig.audioStreams = (uint8_t) CPS_FLD_READ(MHDP__MHDP_APB_REGS__CDNS_CFGS0_P, AUDIO_STREAM_NUMBER, readVal);
+
+ readVal = CPS_REG_READ(&pD->regBase->mhdp_apb_regs.CDNS_CFGS1_p);
+ pD->hwConfig.phyType = (uint16_t) CPS_FLD_READ(MHDP__MHDP_APB_REGS__CDNS_CFGS1_P, PHY_NUMBER, readVal);
+ pD->hwConfig.auxType = (uint16_t) CPS_FLD_READ(MHDP__MHDP_APB_REGS__CDNS_CFGS1_P, AUX_NUMBER, readVal);
+}
+
+static void echoUint32(DP_PrivateData* pD, uint32_t message, DP_BusType busType)
+{
+ messageStart(pD, MB_MODULE_ID_GENERAL, (uint8_t)GENERAL_TEST_ECHO);
+ messageWriteUint32(pD, message);
+ messageFinish(pD);
+ messageTransmit(pD, busType);
+ messageReceive(pD, busType);
+}
+
+static uint32_t checkEchoUint32(DP_PrivateData* pD, uint32_t message)
+{
+ uint32_t retVal = CDN_EOK;
+ uint32_t readVal;
+ uint8_t headerMatching = messageHeaderMatches(pD, MB_MODULE_ID_GENERAL, (uint8_t)GENERAL_TEST_ECHO);
+
+ if (0U == headerMatching) {
+ retVal = CDN_ENOEXEC;
+ }
+
+ if (CDN_EOK == retVal) {
+ messageGetHeader(pD, NULL, NULL, NULL);
+ messageReadUint32(pD, &readVal);
+
+ if (message != readVal) {
+ retVal = CDN_EIO;
+ }
+ }
+
+ return retVal;
+}
+
+static void echoBuffer(DP_PrivateData* pD, const uint8_t* message, uint16_t messageSize, DP_BusType busType)
+{
+ messageStart(pD, MB_MODULE_ID_GENERAL, (uint8_t)GENERAL_TEST_ECHO);
+ messageWriteBuffer(pD, message, messageSize);
+ messageFinish(pD);
+ messageTransmit(pD, busType);
+ messageReceive(pD, busType);
+}
+
+static uint32_t checkEchoBuffer(DP_PrivateData* pD,
+ const uint8_t* message,
+ uint8_t* response,
+ uint16_t messageSize)
+{
+ uint16_t readLen;
+ uint32_t retVal = CDN_EOK;
+ uint8_t headerMatching = messageHeaderMatches(pD, MB_MODULE_ID_GENERAL, (uint8_t)GENERAL_TEST_ECHO);
+
+ if (0U == headerMatching) {
+ retVal = CDN_ENOEXEC;
+ }
+
+ if (CDN_EOK == retVal) {
+ uint8_t i;
+
+ messageGetHeader(pD, NULL, NULL, &readLen);
+ messageReadBuffer(pD, response, readLen);
+
+ if (readLen != messageSize) {
+ retVal = CDN_EIO;
+ } else {
+ for (i = 0U; i < messageSize; i++) {
+ if (message[i] != response[i]) {
+ retVal = CDN_EIO;
+ break;
+ }
+ }
+ }
+ }
+
+ return retVal;
+}
+
+static uint32_t waitFecStatus(DP_PrivateData* pD, bool fecBusy)
+{
+ uint32_t retVal;
+ uint32_t actualFecBusy;
+ uint32_t expectedFecBusy = (fecBusy) ? 1U : 0U;
+
+ DP_RegisterTransfer regTransfer = {0U};
+
+ regTransfer.addr = offsetof(MHDP_ApbRegs, mhdp_apb_regs.DPTX_FEC_STATUS_p);
+
+ do {
+ retVal = DP_ReadRegister(pD, ®Transfer);
+ actualFecBusy = CPS_FLD_READ(MHDP__MHDP_APB_REGS__DPTX_FEC_STATUS_P, FEC_BUSY, regTransfer.val);
+ } while ((retVal == CDN_EOK) && (actualFecBusy != expectedFecBusy));
+
+ return retVal;
+}
+
+static uint32_t setCustomPatternSF(const DP_PrivateData* pD, const uint8_t* customPattern)
+{
+ uint32_t retVal = DP_SetCustomPatternSF(pD);
+ if (CDN_EOK == retVal) {
+ if (NULL == customPattern) {
+ retVal = CDN_EINVAL;
+ }
+ }
+
+ return retVal;
+}
+
+static uint32_t configurePhy(DP_PrivateData* pD, const DP_LinkState* linkParams)
+{
+ uint32_t retVal;
+ uint8_t i;
+ /* 1:1 conversion from DP driver's structure to PHY driver's structure */
+ DP_SD0801_LinkState sdState;
+ toSdLinkState(linkParams, &sdState);
+
+ retVal = DP_SD0801_SetLinkRate(pD->phyPd, &sdState);
+ if (CDN_EOK == retVal) {
+ retVal = DP_SD0801_EnableLanes(pD->phyPd, &sdState);
+ }
+
+ if (CDN_EOK == retVal)
+ {
+ for (i = 0U; i < (sdState.laneCount); i++) {
+ retVal = DP_SD0801_ConfigLane(pD->phyPd, i, &sdState);
+ if (CDN_EOK != retVal) {
+ /* Stop execution in case of error */
+ break;
+ }
+ }
+ }
+ return retVal;
+}
+
+static uint32_t updateAssrEnable(DP_PrivateData* pD, bool enable)
+{
+ uint32_t retVal = CDN_EOK;
+ DP_DpcdTransfer transfer = {0U};
+ uint8_t dpcdBuffer[1];
+
+ if (pD->sinkCaps.assr) {
+ transfer.addr = DP_EDP_CONF_REG;
+ transfer.size = 1U;
+ transfer.buff = dpcdBuffer;
+
+ retVal = DP_ReadDpcd(pD, &transfer);
+
+ if (CDN_EOK == retVal) {
+ bool actualEnable = (0U == (dpcdBuffer[0] & DP_ASSR_ENABLE_MASK));
+
+ bool setEnable = (enable) && (!actualEnable);
+ bool setDisable = (!enable) && (actualEnable);
+
+ if ((setEnable) || (setDisable))
+ {
+ /* Value of DPCD register has to be updated */
+ transfer.addr = DP_EDP_CONF_REG;
+ transfer.size = 1U;
+
+ if (enable) {
+ dpcdBuffer[0] |= DP_ASSR_ENABLE_MASK;
+ } else {
+ dpcdBuffer[0] &= ~DP_ASSR_ENABLE_MASK;
+ }
+
+ retVal = DP_WriteDpcd(pD, &transfer);
+ }
+ }
+ }
+
+ return retVal;
+}
+
+static DP_AuxStatus getAuxStatus(uint8_t code)
+{
+ DP_AuxStatus result;
+
+ static const DP_AuxStatus auxStatus[4] = {
+ DP_AUX_ACK,
+ DP_AUX_NACK,
+ DP_AUX_DEFER,
+ DP_AUX_SINK_ERROR
+ };
+
+ if (code <= 3U) {
+ result = auxStatus[code];
+ } else {
+ result = DP_AUX_UNKNOWN_ERROR;
+ }
+
+ return result;
+}
+
+static DP_I2cStatus getI2cStatus(uint8_t code)
+{
+ DP_I2cStatus result;
+
+ static const DP_I2cStatus i2cStatus[3] = {
+ DP_I2C_ACK,
+ DP_I2C_NACK,
+ DP_I2C_DEFER
+ };
+
+ if (code <= 2U) {
+ result = i2cStatus[code];
+ } else {
+ result = DP_I2C_UNKNOWN_ERROR;
+ }
+
+ return result;
+}
+
+static void clearRxTxBuffers(DP_PrivateData* pD)
+{
+ uint32_t i;
+
+ pD->txi = 0U;
+ pD->rxi = 0U;
+ pD->txEnable = 0U;
+ pD->rxEnable = 0U;
+
+ for (i = 0U; i < sizeof(pD->txBuffer); i++) {
+ pD->txBuffer[i] = 0U;
+ }
+
+ for (i = 0U; i < sizeof(pD->rxBuffer); i++) {
+ pD->rxBuffer[i] = 0U;
+ }
+}
+
+static void clearCapabilities(DP_PrivateData* pD) {
+ clearSourceCapabilities(&(pD->sourceCaps));
+ pD->sourceCapsStored = 0U;
+
+ clearSinkCapabilities(&(pD->sinkCaps));
+ pD->sinkCapsStored = 0U;
+}
+
+static uint32_t loadFirmwareSF(const DP_PrivateData* pD, const DP_FirmwareImage* image)
+{
+ uint32_t retVal;
+
+ retVal = DP_LoadFirmwareSF(pD, image);
+
+ if (CDN_EOK == retVal) {
+ /* Size of instruction memory and data memory must be divisible by 4. */
+ if ((NULL == image->iMem) ||
+ (NULL == image->dMem) ||
+ (0U != (image->iMemSize % 4U)) ||
+ (0U != (image->dMemSize % 4U)))
+ {
+ retVal = CDN_EINVAL;
+ }
+ }
+
+ return retVal;
+}
+
+static void writeFirmwareImageToMemory(volatile uint32_t* address, const uint8_t* image, uint32_t memorySize)
+{
+ uint32_t i;
+ uint32_t reg;
+ volatile uint32_t* localAddress = address;
+
+ for (i = 0U; i < memorySize; i += 4U) {
+
+ reg = ((uint32_t)image[i] << 0) |
+ ((uint32_t)image[i + 1U] << 8) |
+ ((uint32_t)image[i + 2U] << 16) |
+ ((uint32_t)image[i + 3U] << 24);
+
+ CPS_REG_WRITE(localAddress, reg);
+
+ localAddress++;
+
+ }
+}
+
+/**
+ * Check, if PHY ID (version) is on list of versions supported by the driver.
+ */
+static bool checkPhyVersion(uint16_t phyVer)
+{
+ /* PHY version ID is 16-bit. */
+ static const uint16_t supportedPhys[] = {
+ DP_PHY_VERSION_1100,
+ DP_PHY_VERSION_1200
+ };
+ bool supported = false;
+ uint32_t i;
+
+ for (i = 0; i < (sizeof(supportedPhys) / sizeof(uint16_t)); i++)
+ {
+ if (supportedPhys[i] == phyVer)
+ {
+ supported = true;
+ }
+ }
+
+ return supported;
+}
+
+static uint32_t checkHardwareConfiguration(const DP_HardwareConfig* hwConfig)
+{
+ uint32_t retVal = CDN_EOK;
+
+ if ((hwConfig->ipPartNumber != DP_IP_PART_NUMBER) ||
+ (hwConfig->ipVersion != DP_IP_VERSION) ||
+ (hwConfig->auxVersion != DP_AUX_VERSION) ||
+ (!checkPhyVersion(hwConfig->phyVersion)))
+ {
+ retVal = CDN_ENOTSUP;
+ }
+
+ return retVal;
+}
+
+static void clearPrivateData(DP_PrivateData* pD)
+{
+ uint8_t i;
+
+ pD->running = 0U;
+ pD->busType = DP_BUS_TYPE_APB;
+ pD->tmp = 0U;
+
+ clearRxTxBuffers(pD);
+
+ clearCapabilities(pD);
+
+ clearLinkState(&(pD->linkState));
+
+ (void)updateAlive(pD);
+
+ pD->mstEnabled = false;
+ pD->fecEnabled = false;
+ pD->sstVicSet = false;
+
+ for (i = 0U; i < DP_MAX_NUMBER_OF_STREAMS; i++) {
+ /* remaining parameters may be auto-initialized to '0' */
+ (void)memset(&(pD->videoParameters[i]), 0, sizeof(DP_VideoParameters));
+ pD->videoParameters[i].pxEncFormat = DP_PXENC_PXL_RGB;
+ pD->streamEnabled[i] = false;
+ pD->sinkList[i].port = NULL;
+
+ uint8_t sdpIdx;
+
+ for (sdpIdx = 0U; sdpIdx < DP_MAX_NUMBER_OF_SDPS; sdpIdx++) {
+ pD->sdpPacketType[i][sdpIdx] = 0U;
+ }
+ }
+
+ for (i = 0U; i < DP_NUMBER_OF_DSC_ENCODERS; i++) {
+ pD->dscConfig[i] = (DP_DscConfigFull){0U};
+ }
+}
+
+static uint32_t setCipherClockConfig(DP_PrivateData* pD, uint8_t clockEnable)
+{
+ uint32_t retVal;
+ uint32_t reg;
+ DP_RegisterTransfer regTransfer = {0U};
+
+ regTransfer.addr = offsetof(MHDP_ApbRegs, mhdp_apb_regs.source_cipher_car_p);
+ retVal = DP_ReadRegister(pD, ®Transfer);
+
+ if (retVal == CDN_EOK) {
+
+ reg = regTransfer.val;
+
+ reg = CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__SOURCE_CIPHER_CAR_P, SOURCE_CIPHER_CHAR_CLK_EN, reg, clockEnable);
+ reg = CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__SOURCE_CIPHER_CAR_P, SOURCE_CIPHER_CHAR_CLK_RSTN_EN, reg, clockEnable);
+ reg = CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__SOURCE_CIPHER_CAR_P, SOURCE_CIPHER_SYS_CLK_EN, reg, clockEnable);
+ reg = CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__SOURCE_CIPHER_CAR_P, SOURCE_CIPHER_SYSTEM_CLK_RSTN_EN, reg, clockEnable);
+
+ regTransfer.val = reg;
+ retVal = DP_WriteRegister(pD, ®Transfer);
+ }
+
+ return retVal;
+}
+
+static uint32_t setCryptoClockConfig(DP_PrivateData* pD, uint8_t clockEnable)
+{
+ uint32_t retVal;
+ uint32_t reg;
+ DP_RegisterTransfer regTransfer = {0U};
+
+ regTransfer.addr = offsetof(MHDP_ApbRegs, mhdp_apb_regs.source_crypto_car_p);
+ retVal = DP_ReadRegister(pD, ®Transfer);
+
+ if (retVal == CDN_EOK) {
+
+ reg = regTransfer.val;
+
+ reg = CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__SOURCE_CRYPTO_CAR_P, SOURCE_CRYPTO_SYS_CLK_EN, reg, clockEnable);
+ reg = CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__SOURCE_CRYPTO_CAR_P, SOURCE_CRYPTO_SYS_CLK_RSTN_EN, reg, clockEnable);
+
+ regTransfer.val = reg;
+ retVal = DP_WriteRegister(pD, ®Transfer);
+ }
+
+ return retVal;
+}
+
+/* API FUNCTIONS */
+
+uint32_t DP_Probe(const DP_Config* config, uint32_t* memReq)
+{
+ uint32_t retVal = CDN_EOK;
+ if (CDN_EOK != DP_ProbeSF(config, memReq)) {
+ retVal = CDN_EINVAL;
+ } else {
+ *memReq = (uint32_t)(sizeof(DP_PrivateData));
+ }
+ return retVal;
+}
+
+uint32_t DP_Init(DP_PrivateData* pD, const DP_Config* config, const DP_Callbacks* callbacks)
+{
+ uint32_t retVal;
+ static AUX_drm_dp aux;
+
+ retVal = DP_InitSF(pD, config, callbacks);
+
+ if (CDN_EOK == retVal) {
+
+ pD->regBase = config->regBase;
+ pD->regBaseSapb = config->regBaseSapb;
+
+ updateHardwareConfiguration(pD);
+ retVal = checkHardwareConfiguration(&(pD->hwConfig));
+ }
+
+ if (CDN_EOK == retVal) {
+
+ pD->cb = *callbacks;
+
+ clearPrivateData(pD);
+
+ /* TODO this should me moved to topology manager */
+ aux.pD = pD;
+ DP_MST_MgrInit(&pD->mstTopMgr, &aux, 16);
+
+ }
+
+ return retVal;
+}
+
+void DP_Isr(DP_PrivateData* pD)
+{
+ if (CDN_EOK == DP_IsrSF(pD))
+ {
+ if (NULL != pD->cb.event) {
+ (*(pD->cb.event))(pD);
+ }
+ }
+}
+
+uint32_t DP_Start(DP_PrivateData* pD)
+{
+ uint32_t reg = 0U;
+ uint32_t retVal = DP_StartSF(pD);
+
+ if (CDN_EOK == retVal) {
+ /* Disable the mailbox interrupt. Else it will keep interrupting */
+ CPS_REG_WRITE(&pD->regBase->mhdp_apb_regs.MAILBOX_INT_MASK_p, ~(0U));
+
+ reg = CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__APB_INT_MASK_P, APB_MAILBOX_INTR_MASK, 0U, 0U)
+ | CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__APB_INT_MASK_P, APB_SW_INTR_MASK, 0U, 0U)
+ | CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__APB_INT_MASK_P, APB_PIF_INTR_MASK, 0U, 0U)
+ | CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__APB_INT_MASK_P, APB_CEC_INTR_MASK, 0U, 0U);
+
+ CPS_REG_WRITE(&pD->regBase->mhdp_apb_regs.APB_INT_MASK_p, reg);
+ }
+
+ return retVal;
+}
+
+uint32_t DP_Stop(DP_PrivateData* pD)
+{
+ uint32_t reg = 0U;
+ uint32_t retVal = DP_StopSF(pD);
+
+ if (CDN_EOK == retVal) {
+ reg = CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__APB_INT_MASK_P, APB_MAILBOX_INTR_MASK, 0U, 1U)
+ | CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__APB_INT_MASK_P, APB_SW_INTR_MASK, 0U, 1U)
+ | CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__APB_INT_MASK_P, APB_PIF_INTR_MASK, 0U, 1U)
+ | CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__APB_INT_MASK_P, APB_CEC_INTR_MASK, 0U, 1U);
+
+ CPS_REG_WRITE(&pD->regBase->mhdp_apb_regs.APB_INT_MASK_p, reg);
+ }
+
+ return retVal;
+}
+
+uint32_t DP_Destroy(const DP_PrivateData* pD)
+{
+ return DP_DestroySF(pD);
+}
+
+uint32_t DP_SetPhyPd(DP_PrivateData* pD, DP_SD0801_PrivateData* phyPd)
+{
+ uint32_t retVal;
+
+ retVal = DP_SetPhyPdSF(pD, phyPd);
+
+ if (CDN_EOK == retVal)
+ {
+ pD->phyPd = phyPd;
+ }
+
+ return retVal;
+}
+
+uint32_t DP_LoadFirmware(const DP_PrivateData* pD, const DP_FirmwareImage* image)
+{
+ uint32_t retVal;
+ uint32_t reg;
+
+ retVal = loadFirmwareSF(pD, image);
+
+ if (CDN_EOK == retVal)
+ {
+ /* Stall the uCPU and release reset to load FW */
+ reg = CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__APB_CTRL_P, APB_XT_RUNSTALL, 0U, 1U);
+ CPS_REG_WRITE(&pD->regBase->mhdp_apb_regs.APB_CTRL_p, reg);
+
+ volatile uint32_t* address = pD->regBase->mhdp_apb_regs.IRAM_REG_p;
+ writeFirmwareImageToMemory(address, image->iMem, image->iMemSize);
+
+ address = pD->regBase->mhdp_apb_regs.DRAM_REG_p;
+ writeFirmwareImageToMemory(address, image->dMem, image->dMemSize);
+ }
+
+ return retVal;
+}
+
+uint32_t DP_StartUcpu(const DP_PrivateData* pD)
+{
+ uint32_t retVal;
+
+ retVal = DP_StartUcpuSF(pD);
+ if (CDN_EOK == retVal)
+ {
+ CPS_REG_WRITE(&pD->regBase->mhdp_apb_regs.APB_CTRL_p, 0);
+ }
+
+ return retVal;
+}
+
+uint32_t DP_TestEcho(DP_PrivateData* pD,
+ uint32_t message,
+ DP_BusType busType)
+{
+ uint32_t retVal = DP_TestEchoSF(pD, busType);
+
+ if (CDN_EOK == retVal)
+ {
+ echoUint32(pD, message, busType);
+ retVal = checkEchoUint32(pD, message);
+ }
+
+ return retVal;
+}
+
+uint32_t DP_TestEchoExt(DP_PrivateData* pD,
+ const uint8_t* message,
+ uint8_t* response,
+ uint16_t messageSize,
+ DP_BusType busType)
+{
+ uint32_t retVal;
+
+ retVal = DP_TestEchoExtSF(pD, message, response, messageSize, busType);
+
+ if (CDN_EOK == retVal) {
+ echoBuffer(pD, message, messageSize, busType);
+ retVal = checkEchoBuffer(pD, message, response, messageSize);
+ }
+
+ return retVal;
+}
+
+uint32_t DP_GetCurVersion(const DP_PrivateData* pD, uint16_t* ver, uint16_t* verlib)
+{
+ uint32_t retVal;
+ uint32_t lowByte;
+ uint32_t highByte;
+
+ retVal = DP_GetCurVersionSF(pD, ver, verlib);
+
+ if (CDN_EOK == retVal)
+ {
+
+ lowByte = CPS_REG_READ(&pD->regBase->mhdp_apb_regs.VER_L_p);
+ highByte = CPS_REG_READ(&pD->regBase->mhdp_apb_regs.VER_H_p);
+ *ver = (uint16_t)(CPS_FLD_READ(MHDP__MHDP_APB_REGS__VER_H_P, VER_MSB, highByte) << 8)
+ | (uint16_t)(CPS_FLD_READ(MHDP__MHDP_APB_REGS__VER_L_P, VER_LSB, lowByte));
+
+ lowByte = CPS_REG_READ(&pD->regBase->mhdp_apb_regs.VER_LIB_L_ADDR_p);
+ highByte = CPS_REG_READ(&pD->regBase->mhdp_apb_regs.VER_LIB_H_ADDR_p);
+ *verlib = (uint16_t)(CPS_FLD_READ(MHDP__MHDP_APB_REGS__VER_LIB_H_ADDR_P, SW_LIB_VER_H, highByte) << 8)
+ | (uint16_t)(CPS_FLD_READ(MHDP__MHDP_APB_REGS__VER_LIB_L_ADDR_P, SW_LIB_VER_L, lowByte));
+ }
+
+ return retVal;
+}
+
+uint32_t DP_GetEvent(const DP_PrivateData* pD, uint32_t* events)
+{
+ uint32_t retVal;
+ uint32_t readVal;
+
+ retVal = DP_GetEventSF(pD, events);
+
+ if (CDN_EOK == retVal)
+ {
+ *events = 0;
+ readVal = CPS_REG_READ(&pD->regBase->mhdp_apb_regs.APB_INT_STATUS_p);
+ }
+
+ if ((CDN_EOK == retVal) &&
+ (0U != readVal))
+ {
+ readVal = CPS_REG_READ(&pD->regBase->mhdp_apb_regs.SW_EVENTS0_p);
+ *events = CPS_FLD_READ(MHDP__MHDP_APB_REGS__SW_EVENTS0_P, SW_EVENTS7_0, readVal);
+
+ readVal = CPS_REG_READ(&pD->regBase->mhdp_apb_regs.SW_EVENTS1_p);
+ *events |= (CPS_FLD_READ(MHDP__MHDP_APB_REGS__SW_EVENTS1_P, SW_EVENTS15_8, readVal) << 8);
+
+ readVal = CPS_REG_READ(&pD->regBase->mhdp_apb_regs.SW_EVENTS2_p);
+ *events |= (CPS_FLD_READ(MHDP__MHDP_APB_REGS__SW_EVENTS2_P, SW_EVENTS23_16, readVal) << 16);
+
+ readVal = CPS_REG_READ(&pD->regBase->mhdp_apb_regs.SW_EVENTS3_p);
+ *events |= (CPS_FLD_READ(MHDP__MHDP_APB_REGS__SW_EVENTS3_P, SW_EVENTS31_24, readVal) << 24);
+ }
+
+ return retVal;
+}
+
+uint32_t DP_GetDebugRegVal(const DP_PrivateData* pD, uint16_t* debug)
+{
+ uint32_t retVal;
+ uint32_t lowByte;
+ uint32_t highByte;
+
+ retVal = DP_GetDebugRegValSF(pD, debug);
+
+ if (CDN_EOK == retVal)
+ {
+ lowByte = CPS_REG_READ(&pD->regBase->mhdp_apb_regs.SW_DEBUG_L_p);
+ highByte = CPS_REG_READ(&pD->regBase->mhdp_apb_regs.SW_DEBUG_H_p);
+ *debug = (uint16_t)(CPS_FLD_READ(MHDP__MHDP_APB_REGS__SW_DEBUG_H_P, SW_DEBUG_15_8, highByte) << 8)
+ | (uint16_t)(CPS_FLD_READ(MHDP__MHDP_APB_REGS__SW_DEBUG_L_P, SW_DEBUG_7_0, lowByte));
+ }
+
+ return retVal;
+}
+
+uint32_t DP_CheckAlive(DP_PrivateData* pD, bool* updated)
+{
+ uint32_t retVal = DP_CheckAliveSF(pD, updated);
+
+ if (CDN_EOK == retVal)
+ {
+ *updated = updateAlive(pD);
+ }
+
+ return retVal;
+}
+
+uint32_t DP_WaitAlive(DP_PrivateData* pD)
+{
+ uint32_t retVal;
+ bool updated;
+
+ retVal = DP_WaitAliveSF(pD);
+
+ if (CDN_EOK == retVal)
+ {
+ updated = updateAlive(pD);
+ /* Result of first updateAlive is insignificant here. It is performed */
+ /* just to update value in pD */
+ updated = false;
+
+ while (!updated)
+ {
+ updated = updateAlive(pD);
+ }
+ }
+
+ return retVal;
+}
+
+uint32_t DP_SendMainControlRequest(DP_PrivateData* pD, uint8_t mode)
+{
+ uint32_t retVal;
+
+ retVal = DP_SendMainControlRequestSF(pD);
+
+ if (CDN_EOK == retVal)
+ {
+ messageStart(pD, MB_MODULE_ID_GENERAL, (uint8_t)GENERAL_MAIN_CONTROL);
+ messageWriteUint8(pD, mode);
+ messageFinish(pD);
+ messageTransmit(pD, DP_BUS_TYPE_APB);
+ }
+
+ return retVal;
+}
+
+uint32_t DP_GetMainControlResponse(DP_PrivateData* pD, uint8_t* resp)
+{
+ uint32_t retVal;
+ uint8_t headerMatching;
+
+ retVal = DP_GetMainControlResponseSF(pD, resp);
+
+ if (CDN_EOK == retVal)
+ {
+ messageReceive(pD, DP_BUS_TYPE_APB);
+ headerMatching = messageHeaderMatches(pD, MB_MODULE_ID_GENERAL, (uint8_t)GENERAL_MAIN_CONTROL);
+
+ if (0U == headerMatching) {
+ retVal = CDN_ENOEXEC;
+ }
+ }
+
+ if (CDN_EOK == retVal)
+ {
+ messageGetHeader(pD, NULL, NULL, NULL);
+ messageReadUint8(pD, resp);
+ }
+
+ return retVal;
+}
+
+uint32_t DP_MainControl(DP_PrivateData* pD, uint8_t mode, uint8_t* resp)
+{
+ uint32_t retVal;
+
+ retVal = DP_MainControlSF(pD, resp);
+
+ if (CDN_EOK == retVal)
+ {
+ retVal = DP_SendMainControlRequest(pD, mode);
+ }
+ if (CDN_EOK == retVal)
+ {
+ retVal = DP_GetMainControlResponse(pD, resp);
+ }
+
+ return retVal;
+}
+
+uint32_t DP_SetClock(DP_PrivateData* pD, const DP_UcpuClock* ucpuClock)
+{
+ uint32_t retVal;
+
+ retVal = DP_SetClockSF(pD, ucpuClock);
+
+ if ((CDN_EOK == retVal) && (0U == ucpuClock->mhz)) {
+ retVal = CDN_EPROTO;
+ }
+
+ if (CDN_EOK == retVal)
+ {
+ uint32_t writeVal;
+
+ writeVal = CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__SW_CLK_H_P, SW_CLOCK_VAL_H, 0U, ucpuClock->mhz);
+ CPS_REG_WRITE(&pD->regBase->mhdp_apb_regs.SW_CLK_H_p, writeVal);
+
+ writeVal = CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__SW_CLK_L_P, SW_CLOCK_VAL_L, 0U, ucpuClock->fraction);
+ CPS_REG_WRITE(&pD->regBase->mhdp_apb_regs.SW_CLK_L_p, writeVal);
+ }
+
+ return retVal;
+}
+
+/**
+ * Initialize part of PHY responsible for AUX channel.
+ */
+uint32_t DP_ConfigurePhyAuxCtrl(const DP_PrivateData* pD)
+{
+ uint32_t retVal = CDN_EOK;
+
+ retVal = DP_ConfigurePhyAuxCtrlSF(pD);
+
+ if (CDN_EOK == retVal)
+ {
+ retVal = DP_SD0801_ConfigurePhyAuxCtrl(pD->phyPd);
+ }
+ return retVal;
+}
+
+uint32_t DP_ConfigurePhyStartUp(DP_PrivateData* pD, uint8_t laneCount, DP_LinkRate linkRate)
+{
+ uint32_t retVal;
+
+ retVal = DP_ConfigurePhyStartUpSF(pD, linkRate);
+
+ if (CDN_EOK == retVal) {
+ retVal = DP_SD0801_PhyStartUp(pD->phyPd, laneCount, toLinkRateSd(linkRate));
+ }
+
+ return retVal;
+}
+
+uint32_t DP_SendEdidReadRequest(DP_PrivateData* pD,
+ uint8_t segment,
+ uint8_t extension)
+{
+ uint32_t retVal;
+
+ retVal = DP_SendEdidReadRequestSF(pD);
+
+ if (CDN_EOK == retVal)
+ {
+ messageStart(pD, MB_MODULE_ID_DP_TX, (uint8_t)DPTX_GET_EDID);
+ messageWriteUint8(pD, segment);
+ messageWriteUint8(pD, extension);
+ messageFinish(pD);
+ messageTransmit(pD, DP_BUS_TYPE_APB);
+ }
+
+ return retVal;
+}
+
+uint32_t DP_GetEdidReadResponse(DP_PrivateData* pD,
+ DP_ReadEdidResponse* resp)
+{
+ uint32_t retVal;
+ uint8_t headerMatching;
+ retVal = DP_GetEdidReadResponseSF(pD, resp);
+
+ if (CDN_EOK != retVal)
+ {
+ DbgMsg(DBG_GEN_MSG, DBG_CRIT,
+ "Function for receiving data containing response with read EDID "
+ "data was called incorrectly. DPTX Mailbox may not be able to "
+ "operate any more.\n");
+ }
+
+ if (CDN_EOK == retVal)
+ {
+ messageReceive(pD, DP_BUS_TYPE_APB);
+ headerMatching = messageHeaderMatches(pD, MB_MODULE_ID_DP_TX, (uint8_t)DPTX_GET_EDID);
+
+ if (0U == headerMatching) {
+ retVal = CDN_ENOEXEC;
+ }
+ }
+
+ if (CDN_EOK == retVal)
+ {
+ messageGetHeader(pD, NULL, NULL, NULL);
+ messageReadUint8(pD, &(resp->size));
+ messageReadUint8(pD, &(resp->blockNo));
+ if (128U == resp->size)
+ {
+ messageReadBuffer(pD, resp->buff, resp->size);
+ } else {
+ retVal = CDN_EIO;
+ }
+ }
+
+ return retVal;
+}
+
+uint32_t DP_ReadEdid(DP_PrivateData* pD,
+ uint8_t segment,
+ uint8_t extension,
+ DP_ReadEdidResponse* resp)
+{
+ uint32_t retVal = DP_ReadEdidSF(pD, resp);
+
+ if (CDN_EOK == retVal)
+ {
+ retVal = DP_SendEdidReadRequest(pD, segment, extension);
+ }
+ if (CDN_EOK == retVal)
+ {
+ retVal = DP_GetEdidReadResponse(pD, resp);
+ }
+
+ return retVal;
+
+}
+
+uint32_t DP_SetPowerMode(DP_PrivateData* pD, DP_PwrMode mode)
+{
+ /* DP_PwrMode fits within range of uint8_t. */
+ uint32_t retVal = DP_SetPowerModeSF(pD, mode);
+
+ if (CDN_EOK == retVal)
+ {
+ messageStart(pD, MB_MODULE_ID_DP_TX, (uint8_t)DPTX_SET_POWER_MNG);
+ messageWriteUint8(pD, (uint8_t)mode);
+ messageFinish(pD);
+ messageTransmit(pD, DP_BUS_TYPE_APB);
+ }
+
+ return retVal;
+}
+
+uint32_t DP_SetCustomPattern(DP_PrivateData* pD, uint8_t customPattern[10])
+{
+ uint32_t retVal;
+ DP_RegisterTransfer regTransfer = {0U};
+ uint8_t i;
+
+ const static uint32_t trainingRegAddress[3] = {
+ offsetof(MHDP_ApbRegs, mhdp_apb_regs.DP_TX_PHY_TRAINING_01_04_p),
+ offsetof(MHDP_ApbRegs, mhdp_apb_regs.DP_TX_PHY_TRAINING_05_08_p),
+ offsetof(MHDP_ApbRegs, mhdp_apb_regs.DP_TX_PHY_TRAINING_09_10_p)
+ };
+
+ retVal = setCustomPatternSF(pD, customPattern);
+
+ if (CDN_EOK == retVal) {
+ const uint8_t patternRegisterNumber = 3U;
+ uint8_t index;
+ for (i = 0U; i < patternRegisterNumber; i++) {
+ index = i * 4U;
+ regTransfer.addr = trainingRegAddress[i];
+
+ /* Same masks for each register */
+ regTransfer.val = CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__DP_TX_PHY_TRAINING_01_04_P, DP_TX_PHY_TRAINING_01, 0U, customPattern[index])
+ | CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__DP_TX_PHY_TRAINING_01_04_P, DP_TX_PHY_TRAINING_02, 0U, customPattern[index + 1U]);
+
+ /* Last training register have only 16bits of data */
+ if (i < (patternRegisterNumber - 1U)) {
+ regTransfer.val |= CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__DP_TX_PHY_TRAINING_01_04_P, DP_TX_PHY_TRAINING_03, 0U, customPattern[index + 2U])
+ | CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__DP_TX_PHY_TRAINING_01_04_P, DP_TX_PHY_TRAINING_04, 0U, customPattern[index + 3U]);
+
+ }
+
+ retVal = DP_WriteRegister(pD, ®Transfer);
+
+ if (CDN_EOK != retVal) {
+ break;
+ }
+ }
+
+ }
+
+ return retVal;
+}
+
+/**
+ * Set SCRAMBLER_BYPASS and ENCODER_BYPASS fields in DP_TX_PHY_CONFIG_REG.
+ */
+static void setPatternBypasses(DP_TestPattern pattern, DP_RegisterTransfer* regTransfer)
+{
+ /* Disable scrambling for selected patterns */
+ if ((DP_PATTERN_TPS1 == pattern) ||
+ (DP_PATTERN_TPS2 == pattern) ||
+ (DP_PATTERN_TPS3 == pattern) ||
+ (DP_PATTERN_D10_2 == pattern)) {
+ regTransfer->val |= CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__DP_TX_PHY_CONFIG_REG_P, DP_TX_PHY_SCRAMBLER_BYPASS, 0U, 1U);
+ }
+
+ /* Disable 8b/10b encoding and scrambling for selected patterns */
+ if ((DP_PATTERN_PRBS7 == pattern) || (DP_PATTERN_80_BIT == pattern)) {
+ regTransfer->val |= CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__DP_TX_PHY_CONFIG_REG_P, DP_TX_PHY_SCRAMBLER_BYPASS, 0U, 1U);
+ regTransfer->val |= CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__DP_TX_PHY_CONFIG_REG_P, DP_TX_PHY_ENCODER_BYPASS, 0U, 1U);
+ }
+}
+
+uint32_t DP_SetTestPattern(DP_PrivateData* pD, DP_TestPattern pattern, DP_LinkState* linkParams)
+{
+ uint32_t retVal;
+ DP_RegisterTransfer regTransfer = {0U};
+
+ retVal = DP_SetTestPatternSF(pD, pattern, linkParams);
+
+ if (CDN_EOK == retVal)
+ {
+ regTransfer.addr = offsetof(MHDP_ApbRegs, mhdp_apb_regs.DP_TX_PHY_CONFIG_REG_p);
+ regTransfer.val = COMMON_DPHY_CONFIG;
+
+ /* Enable training (pattern) and set pattern type, if disabling it was not chosen. */
+ if (DP_PATTERN_DISABLE != pattern) {
+ retVal = configurePhy(pD, linkParams);
+ regTransfer.val |= CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__DP_TX_PHY_CONFIG_REG_P, DP_TX_PHY_TRAINING_ENABLE, 0U, 1U);
+ regTransfer.val |= CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__DP_TX_PHY_CONFIG_REG_P, DP_TX_PHY_TRAINING_TYPE, 0U, pattern);
+ }
+ if (CDN_EOK == retVal) {
+ /* Disable scrambler and/or encoder, if pattern requires it. */
+ setPatternBypasses(pattern, ®Transfer);
+ retVal = DP_WriteRegister(pD, ®Transfer);
+ }
+ }
+
+ if (CDN_EOK == retVal) {
+ /* parasoft-begin-suppress MISRA2012-RULE-12_2-2 "Shifting operation should be checked, DRV-3828" */
+ /* laneCount is checked by sanity function */
+ uint8_t value = ((1U << linkParams->laneCount) - 1U);
+ /* parasoft-end-suppress MISRA2012-RULE-12_2-2 */
+ regTransfer.addr = offsetof(MHDP_ApbRegs, mhdp_apb_regs.DPTX_LANE_EN_p);
+ regTransfer.val = (uint32_t)value;
+
+ retVal = DP_WriteRegister(pD, ®Transfer);
+ }
+
+ return retVal;
+}
+
+uint32_t DP_SendDpcdReadRequest(DP_PrivateData* pD,
+ const DP_DpcdTransfer* request)
+{
+ uint32_t retVal;
+
+ retVal = DP_SendDpcdReadRequestSF(pD, request);
+
+ if (CDN_EOK == retVal) {
+ if ((request->size > DP_MAX_DPCD_TRANSFER_SIZE) || (request->size < 1U)) {
+ retVal = CDN_EINVAL;
+ }
+ }
+
+ if (CDN_EOK == retVal) {
+ messageStart(pD, MB_MODULE_ID_DP_TX, (uint8_t)DPTX_READ_DPCD);
+ messageWriteUint16(pD, request->size);
+ messageWrite3Bytes(pD, request->addr);
+ messageFinish(pD);
+ messageTransmit(pD, DP_BUS_TYPE_APB);
+ }
+ return retVal;
+}
+
+uint32_t DP_GetDpcdReadResponse(DP_PrivateData* pD,
+ DP_DpcdTransfer* transfer)
+{
+ uint32_t retVal;
+ uint32_t readAddr;
+ uint16_t readSize;
+ uint16_t copyLen;
+
+ retVal = DP_GetDpcdReadResponseSF(pD, transfer);
+
+ if (CDN_EOK != retVal)
+ {
+ DbgMsg(DBG_GEN_MSG, DBG_CRIT,
+ "Function for receiving data containing response with read DPCD "
+ "values was called incorrectly. DPTX Mailbox may not be able to "
+ "operate any more.\n");
+ }
+
+ if (CDN_EOK == retVal)
+ {
+
+ messageReceive(pD, DP_BUS_TYPE_APB);
+ uint8_t headerMatching = messageHeaderMatches(pD, MB_MODULE_ID_DP_TX, (uint8_t)DPTX_READ_DPCD);
+ if (0U == headerMatching)
+ {
+ retVal = CDN_ENOEXEC;
+ }
+ }
+
+ if (CDN_EOK == retVal)
+ {
+ messageGetHeader(pD, NULL, NULL, NULL);
+ messageReadUint16(pD, &readSize);
+ messageRead3Bytes(pD, &readAddr);
+
+ if ((readSize != transfer->size) || (readAddr != transfer->addr))
+ {
+ retVal = CDN_EIO;
+ /* CDN_EIO error is not fatal in this case - continue execution. */
+ }
+
+ if (readSize <= transfer->size)
+ {
+ copyLen = readSize;
+ } else {
+ /* Prevent copying more data, than was requested (avoid buffer overflow). */
+ copyLen = transfer->size;
+ }
+
+ transfer->size = readSize;
+ transfer->addr = readAddr;
+ messageReadBuffer(pD, transfer->buff, copyLen);
+ }
+
+ return retVal;
+}
+
+static uint32_t DP_ReadDpcdInternal(DP_PrivateData* pD,
+ DP_DpcdTransfer* transfer)
+{
+ uint32_t retVal;
+
+ retVal = DP_SendDpcdReadRequest(pD, transfer);
+
+ if (CDN_EOK == retVal)
+ {
+ retVal = DP_GetDpcdReadResponse(pD, transfer);
+ }
+
+ return retVal;
+}
+
+uint32_t DP_ReadDpcd(DP_PrivateData* pD,
+ DP_DpcdTransfer* transfer)
+{
+ uint32_t retVal;
+ uint32_t i = DP_MAX_DPCD_READ_RETRIES;
+
+ retVal = DP_ReadDpcdSF(pD, transfer);
+
+ if(CDN_EOK == retVal)
+ {
+ /* Store addr and size, FW can corrupt it */
+ uint32_t addr_c = transfer->addr;
+ uint16_t size_c = transfer->size;
+
+ while(i--) {
+ transfer->addr = addr_c;
+ transfer->size = size_c;
+
+ retVal = DP_ReadDpcdInternal(pD, transfer);
+ if(CDN_EOK == retVal)
+ {
+ break;
+ }
+ }
+ }
+
+ return retVal;
+}
+
+uint32_t DP_SendDpcdWriteRequest(DP_PrivateData* pD,
+ const DP_DpcdTransfer* request)
+{
+ uint32_t retVal;
+
+ retVal = DP_SendDpcdWriteRequestSF(pD, request);
+
+ if (CDN_EOK == retVal)
+ {
+ if ((request->size > DP_MAX_DPCD_TRANSFER_SIZE) || (request->size < 1U))
+ {
+ retVal = CDN_EINVAL;
+ }
+ }
+ if (CDN_EOK == retVal)
+ {
+ messageStart(pD, MB_MODULE_ID_DP_TX, (uint8_t)DPTX_WRITE_DPCD);
+ messageWriteUint16(pD, request->size);
+ messageWrite3Bytes(pD, request->addr);
+ messageWriteBuffer(pD, request->buff, request->size);
+ messageFinish(pD);
+ messageTransmit(pD, DP_BUS_TYPE_APB);
+ }
+ return retVal;
+}
+
+uint32_t DP_GetDpcdWriteResponse(DP_PrivateData* pD,
+ DP_DpcdTransfer* transfer)
+{
+ uint32_t retVal;
+ uint32_t writtenAddr;
+ uint16_t writtenSize;
+ uint8_t headerMatching;
+
+ retVal = DP_GetDpcdWriteResponseSF(pD, transfer);
+
+ if (CDN_EOK != retVal)
+ {
+ DbgMsg(DBG_GEN_MSG, DBG_CRIT,
+ "Function for receiving data containing response for DPCD write "
+ "was called incorrectly. DPTX Mailbox may not be able to "
+ "operate any more.\n");
+ }
+
+ if (CDN_EOK == retVal)
+ {
+ messageReceive(pD, DP_BUS_TYPE_APB);
+ headerMatching = messageHeaderMatches(pD, MB_MODULE_ID_DP_TX, (uint8_t)DPTX_WRITE_DPCD);
+ if (0U == headerMatching)
+ {
+ retVal = CDN_ENOEXEC;
+ }
+ }
+ if (CDN_EOK == retVal)
+ {
+ messageGetHeader(pD, NULL, NULL, NULL);
+ messageReadUint16(pD, &writtenSize);
+ messageRead3Bytes(pD, &writtenAddr);
+
+ if ((writtenSize != transfer->size) || (writtenAddr != transfer->addr))
+ {
+ retVal = CDN_EIO;
+ /* CDN_EIO error is not fatal in this case - continue execution. */
+ }
+
+ transfer->size = writtenSize;
+ transfer->addr = writtenAddr;
+ }
+
+ return retVal;
+}
+
+uint32_t DP_WriteDpcd(DP_PrivateData* pD,
+ DP_DpcdTransfer* transfer)
+{
+ uint32_t retVal;
+
+ retVal = DP_WriteDpcdSF(pD, transfer);
+
+ if (CDN_EOK == retVal)
+ {
+ retVal = DP_SendDpcdWriteRequest(pD, transfer);
+ }
+ if (CDN_EOK == retVal)
+ {
+ retVal = DP_GetDpcdWriteResponse(pD, transfer);
+ }
+ return retVal;
+}
+
+uint32_t DP_SendI2cReadRequest(DP_PrivateData* pD,
+ const DP_I2cTransfer* request)
+{
+ uint32_t retVal;
+
+ retVal = DP_SendI2cReadRequestSF(pD, request);
+
+ if (CDN_EOK == retVal) {
+ if ((request->size > DP_MAX_I2C_TRANSFER_SIZE) || (request->size < 1U)) {
+ retVal = CDN_EINVAL;
+ }
+ }
+
+ if (CDN_EOK == retVal) {
+ messageStart(pD, MB_MODULE_ID_DP_TX, (uint8_t)DPTX_I2C_READ);
+ messageWriteUint16(pD, request->size);
+ messageWriteUint8(pD, request->addr);
+ messageWriteUint8(pD, ((request->mot) ? 1U : 0U));
+ messageFinish(pD);
+ messageTransmit(pD, DP_BUS_TYPE_APB);
+ }
+ return retVal;
+}
+
+uint32_t DP_GetI2cReadResponse(DP_PrivateData* pD,
+ DP_I2cTransfer* transfer)
+{
+ uint32_t retVal;
+ uint8_t readAddr;
+ uint16_t readSize;
+ uint16_t copyLen;
+
+ retVal = DP_GetI2cReadResponseSF(pD, transfer);
+
+ if (CDN_EOK != retVal)
+ {
+ DbgMsg(DBG_GEN_MSG, DBG_CRIT,
+ "Function for receiving data containing response with read I2C "
+ "values was called incorrectly. DPTX Mailbox may not be able to "
+ "operate any more.\n");
+ }
+
+ if (CDN_EOK == retVal)
+ {
+
+ messageReceive(pD, DP_BUS_TYPE_APB);
+ uint8_t headerMatching = messageHeaderMatches(pD, MB_MODULE_ID_DP_TX, (uint8_t)DPTX_I2C_READ);
+ if (0U == headerMatching)
+ {
+ retVal = CDN_ENOEXEC;
+ }
+ }
+
+ if (CDN_EOK == retVal)
+ {
+ messageGetHeader(pD, NULL, NULL, NULL);
+ messageReadUint16(pD, &readSize);
+ messageReadUint8(pD, &readAddr);
+
+ if ((readSize != transfer->size) || (readAddr != transfer->addr))
+ {
+ retVal = CDN_EIO;
+ /* CDN_EIO error is not fatal in this case - continue execution. */
+ }
+
+ if (readSize <= transfer->size)
+ {
+ copyLen = readSize;
+ } else {
+ /* Prevent copying more data, than was requested (avoid buffer overflow). */
+ copyLen = transfer->size;
+ }
+
+ transfer->size = readSize;
+ transfer->addr = readAddr;
+ messageReadBuffer(pD, transfer->buff, copyLen);
+ }
+
+ return retVal;
+}
+
+uint32_t DP_I2cRead(DP_PrivateData* pD,
+ DP_I2cTransfer* transfer)
+{
+ uint32_t retVal;
+
+ retVal = DP_I2cReadSF(pD, transfer);
+
+ if (CDN_EOK == retVal)
+ {
+ retVal = DP_SendI2cReadRequest(pD, transfer);
+ }
+ if (CDN_EOK == retVal)
+ {
+ retVal = DP_GetI2cReadResponse(pD, transfer);
+ }
+
+ return retVal;
+}
+
+uint32_t DP_SendI2cWriteRequest(DP_PrivateData* pD,
+ const DP_I2cTransfer* request)
+{
+ uint32_t retVal;
+
+ retVal = DP_SendI2cWriteRequestSF(pD, request);
+
+ if (CDN_EOK == retVal)
+ {
+ if ((request->size > DP_MAX_I2C_TRANSFER_SIZE) || (request->size < 1U))
+ {
+ retVal = CDN_EINVAL;
+ }
+ }
+ if (CDN_EOK == retVal)
+ {
+ messageStart(pD, MB_MODULE_ID_DP_TX, (uint8_t)DPTX_I2C_WRITE);
+ messageWriteUint16(pD, request->size);
+ messageWriteUint8(pD, request->addr);
+ messageWriteUint8(pD, ((request->mot) ? 1U : 0U));
+ messageWriteBuffer(pD, request->buff, request->size);
+ messageFinish(pD);
+ messageTransmit(pD, DP_BUS_TYPE_APB);
+ }
+ return retVal;
+}
+
+uint32_t DP_GetI2cWriteResponse(DP_PrivateData* pD,
+ DP_I2cTransfer* transfer)
+{
+ uint32_t retVal;
+ uint8_t writtenAddr;
+ uint16_t writtenSize;
+ uint8_t headerMatching;
+
+ retVal = DP_GetI2cWriteResponseSF(pD, transfer);
+
+ if (CDN_EOK != retVal)
+ {
+ DbgMsg(DBG_GEN_MSG, DBG_CRIT,
+ "Function for receiving data containing response for I2C write "
+ "was called incorrectly. DPTX Mailbox may not be able to "
+ "operate any more.\n");
+ }
+
+ if (CDN_EOK == retVal)
+ {
+ messageReceive(pD, DP_BUS_TYPE_APB);
+ headerMatching = messageHeaderMatches(pD, MB_MODULE_ID_DP_TX, (uint8_t)DPTX_I2C_WRITE);
+ if (0U == headerMatching)
+ {
+ retVal = CDN_ENOEXEC;
+ }
+ }
+ if (CDN_EOK == retVal)
+ {
+ messageGetHeader(pD, NULL, NULL, NULL);
+ messageReadUint16(pD, &writtenSize);
+ messageReadUint8(pD, &writtenAddr);
+
+ if ((writtenSize != transfer->size) || (writtenAddr != transfer->addr))
+ {
+ retVal = CDN_EIO;
+ /* CDN_EIO error is not fatal in this case - continue execution. */
+ }
+
+ transfer->size = writtenSize;
+ transfer->addr = writtenAddr;
+ }
+
+ return retVal;
+}
+
+uint32_t DP_I2cWrite(DP_PrivateData* pD,
+ DP_I2cTransfer* transfer)
+{
+ uint32_t retVal;
+
+ retVal = DP_I2cWriteSF(pD, transfer);
+
+ if (CDN_EOK == retVal)
+ {
+ retVal = DP_SendI2cWriteRequest(pD, transfer);
+ }
+ if (CDN_EOK == retVal)
+ {
+ retVal = DP_GetI2cWriteResponse(pD, transfer);
+ }
+ return retVal;
+}
+
+uint32_t DP_SetAssrEnable(DP_PrivateData* pD, bool enable)
+{
+ uint32_t retVal;
+ DP_RegisterTransfer regTransfer = {0U};
+ uint32_t seed;
+
+ retVal = DP_SetAssrEnableSF(pD);
+
+ if (CDN_EOK == retVal) {
+ retVal = readSinkCapabilities(pD);
+ }
+
+ if (CDN_EOK == retVal)
+ {
+ if ((enable) && (!pD->sinkCaps.assr))
+ {
+ retVal = CDN_ENOTSUP;
+ }
+ }
+
+ if (CDN_EOK == retVal) {
+ seed = (enable) ? DP_SCRAMBLER_SEED_ALTERNATE : DP_SCRAMBLER_SEED_REGULAR;
+
+ regTransfer.addr = offsetof(MHDP_ApbRegs, mhdp_apb_regs.DP_TX_PHY_SCRAMBLER_SEED_p);
+ regTransfer.val = CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__DP_TX_PHY_SCRAMBLER_SEED_P,
+ DP_TX_PHY_SCRAMBLER_SEED,
+ 0U,
+ seed);
+
+ retVal = DP_WriteRegister(pD, ®Transfer);
+ }
+
+ if (CDN_EOK == retVal) {
+ retVal = updateAssrEnable(pD, enable);
+ }
+
+ return retVal;
+}
+
+uint32_t DP_SetShortenedAuxPreamble(DP_PrivateData* pD, bool enable)
+{
+ uint32_t retVal;
+ DP_RegisterTransfer regTransfer = {0U};
+
+ retVal = DP_SetShortenedAuxPreambleSF(pD);
+
+ if (CDN_EOK == retVal) {
+ regTransfer.addr = offsetof(MHDP_ApbRegs, mhdp_apb_regs.DP_AUX_TX_PREACHARGE_LENGTH_p);
+ /* Set 8 pulses for shortened (eDP) preamble. */
+ /* Set 16 pulses otherwise. */
+ regTransfer.val = CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__DP_AUX_TX_PREACHARGE_LENGTH_P,
+ AUX_HOST_PRECHARGE_LENGTH,
+ 0U,
+ (enable ? 8 : 16));
+ retVal = DP_WriteRegister(pD, ®Transfer);
+ }
+
+ return retVal;
+}
+
+uint32_t DP_SetEventMask(DP_PrivateData* pD, uint32_t mask)
+{
+ uint32_t retVal;
+ uint8_t events = 0U;
+
+ retVal = DP_SetEventMaskSF(pD);
+
+ if (CDN_EOK == retVal)
+ {
+ if (0U == (mask & DP_HPD_EVENT_ENABLE_BIT)) {
+ events = DP_HPD_EVENT_ENABLE_BIT;
+ }
+
+ messageStart(pD, MB_MODULE_ID_DP_TX, (uint8_t)DPTX_ENABLE_EVENT);
+ messageWriteUint8(pD, events);
+ messageWriteUint32(pD, 0U); /* reserved bits */
+ messageFinish(pD);
+ messageTransmit(pD, DP_BUS_TYPE_APB);
+ }
+
+ return retVal;
+}
+
+uint32_t DP_GetEventMask(const DP_PrivateData* pD, const uint32_t* mask)
+{
+ uint32_t retVal;
+
+ retVal = DP_GetEventMaskSF(pD, mask);
+
+ if (CDN_EOK == retVal) {
+ retVal = CDN_ENOTSUP;
+ }
+
+ return retVal;
+}
+
+uint32_t DP_SendReadHpdEventRequest(DP_PrivateData* pD)
+{
+ uint32_t retVal;
+
+ retVal = DP_SendReadHpdEventRequestSF(pD);
+
+ if (CDN_EOK == retVal)
+ {
+ messageStart(pD, MB_MODULE_ID_DP_TX, (uint8_t)DPTX_READ_EVENT);
+ messageFinish(pD);
+ messageTransmit(pD, DP_BUS_TYPE_APB);
+ }
+
+ return retVal;
+}
+
+uint32_t DP_GetReadHpdEventResponse(DP_PrivateData* pD, uint8_t* hpdEvents)
+{
+ uint32_t retVal;
+ uint8_t headerMatching;
+
+ retVal = DP_GetReadHpdEventResponseSF(pD, hpdEvents);
+
+ if (CDN_EOK != retVal)
+ {
+ DbgMsg(DBG_GEN_MSG, DBG_CRIT,
+ "Function for receiving data containing response with HPD events"
+ " was called incorrectly. DPTX Mailbox may not be able to "
+ "operate any more.\n");
+ }
+
+ if (CDN_EOK == retVal)
+ {
+ messageReceive(pD, DP_BUS_TYPE_APB);
+ headerMatching = messageHeaderMatches(pD, MB_MODULE_ID_DP_TX, (uint8_t)DPTX_READ_EVENT);
+
+ if (0U == headerMatching) {
+ retVal = CDN_ENOEXEC;
+ }
+ }
+
+ if (CDN_EOK == retVal)
+ {
+ messageGetHeader(pD, NULL, NULL, NULL);
+ messageReadUint8(pD, hpdEvents);
+ }
+
+ return retVal;
+}
+
+uint32_t DP_ReadHpdEvent(DP_PrivateData* pD, uint8_t* hpdEvents)
+{
+ uint32_t retVal;
+
+ retVal = DP_ReadHpdEventSF(pD, hpdEvents);
+
+ if (CDN_EOK == retVal)
+ {
+ retVal = DP_SendReadHpdEventRequest(pD);
+ }
+ if (CDN_EOK == retVal)
+ {
+ retVal = DP_GetReadHpdEventResponse(pD, hpdEvents);
+ }
+
+ return retVal;
+}
+
+/* parasoft-begin-suppress METRICS-39-3 "The value of VOCF parameter for function should be not higher than 4, DRV-3839" */
+uint32_t DP_FillVideoFormat(DP_VideoFormatParams* vicParams, DP_VicModes vicMode)
+{
+ uint32_t retVal;
+
+ /* Array of video timings format provided by the driver, based on */
+ /* ANSI/CEA-861-F (August 2013), chapter 4, Table 1 and 2. */
+ /* Each row represents one video format. Values in row correspond to */
+ /* subsequent members of DP_VideoFormatParams structure. */
+ static const DP_VideoFormatParams vicTable[] = {
+ {1U, 800U, 640U, 160U, 96U, 16U, 48U, 31.469, 525U, 480U, 45.0, 2U, 10U, 33U, 59.94, 25.18, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_LOW, DP_SP_ACTIVE_LOW, 8U, 0U},
+ {1U, 800U, 640U, 160U, 96U, 16U, 48U, 31.5, 525U, 480U, 45.0, 2U, 10U, 33U, 60.0, 25.20, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_LOW, DP_SP_ACTIVE_LOW, 8U, 0U},
+ {2U, 858U, 720U, 138U, 62U, 16U, 60U, 31.469, 525U, 480U, 45.0, 6U, 9U, 30U, 59.94, 27.00, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_LOW, DP_SP_ACTIVE_LOW, 8U, 0U},
+ {2U, 858U, 720U, 138U, 62U, 16U, 60U, 31.5, 525U, 480U, 45.0, 6U, 9U, 30U, 60.0, 27.03, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_LOW, DP_SP_ACTIVE_LOW, 8U, 0U},
+ {3U, 858U, 720U, 138U, 62U, 16U, 60U, 31.469, 525U, 480U, 45.0, 6U, 9U, 30U, 59.94, 27.00, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_LOW, DP_SP_ACTIVE_LOW, 8U, 0U},
+ {3U, 858U, 720U, 138U, 62U, 16U, 60U, 31.5, 525U, 480U, 45.0, 6U, 9U, 30U, 60.0, 27.03, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_LOW, DP_SP_ACTIVE_LOW, 8U, 0U},
+ {4U, 1650U, 1280U, 370U, 40U, 110U, 220U, 44.955, 750U, 720U, 30.0, 5U, 5U, 20U, 59.94, 74.18, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_HIGH, DP_SP_ACTIVE_HIGH, 8U, 0U},
+ {4U, 1650U, 1280U, 370U, 40U, 110U, 220U, 45.0, 750U, 720U, 30.0, 5U, 5U, 20U, 60.0, 74.25, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_HIGH, DP_SP_ACTIVE_HIGH, 8U, 0U},
+ {5U, 2200U, 1920U, 280U, 44U, 88U, 148U, 33.716, 1125U, 1080U, 22.51, 5U, 2U, 15U, 59.94, 74.18, DP_SM_INTERLACED, DP_SP_ACTIVE_HIGH, DP_SP_ACTIVE_HIGH, 8U, 0U},
+ {5U, 2200U, 1920U, 280U, 44U, 88U, 148U, 33.75, 1125U, 1080U, 22.51, 5U, 2U, 15U, 60.0, 74.25, DP_SM_INTERLACED, DP_SP_ACTIVE_HIGH, DP_SP_ACTIVE_HIGH, 8U, 0U},
+ {6U, 1716U, 1440U, 276U, 124U, 38U, 114U, 15.734, 525U, 480U, 22.51, 3U, 4U, 15U, 59.94, 27.00, DP_SM_INTERLACED, DP_SP_ACTIVE_LOW, DP_SP_ACTIVE_LOW, 8U, 1U},
+ {6U, 1716U, 1440U, 276U, 124U, 38U, 114U, 15.75, 525U, 480U, 22.51, 3U, 4U, 15U, 60.0, 27.03, DP_SM_INTERLACED, DP_SP_ACTIVE_LOW, DP_SP_ACTIVE_LOW, 8U, 1U},
+ {7U, 1716U, 1440U, 276U, 124U, 38U, 114U, 15.734, 525U, 480U, 22.51, 3U, 4U, 15U, 59.94, 27.00, DP_SM_INTERLACED, DP_SP_ACTIVE_LOW, DP_SP_ACTIVE_LOW, 8U, 1U},
+ {7U, 1716U, 1440U, 276U, 124U, 38U, 114U, 15.75, 525U, 480U, 22.51, 3U, 4U, 15U, 60.0, 27.03, DP_SM_INTERLACED, DP_SP_ACTIVE_LOW, DP_SP_ACTIVE_LOW, 8U, 1U},
+ {8U, 1716U, 1440U, 276U, 124U, 38U, 114U, 15.734, 262U, 240U, 22.0, 3U, 4U, 15U, 60.054, 27.00, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_LOW, DP_SP_ACTIVE_LOW, 8U, 1U},
+ {8U, 1716U, 1440U, 276U, 124U, 38U, 114U, 15.75, 262U, 240U, 22.0, 3U, 4U, 15U, 60.115, 27.03, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_LOW, DP_SP_ACTIVE_LOW, 8U, 1U},
+ {8U, 1716U, 1440U, 276U, 124U, 38U, 114U, 15.734, 263U, 240U, 23.0, 3U, 5U, 15U, 59.826, 27.00, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_LOW, DP_SP_ACTIVE_LOW, 8U, 1U},
+ {8U, 1716U, 1440U, 276U, 124U, 38U, 114U, 15.75, 263U, 240U, 23.0, 3U, 5U, 15U, 59.886, 27.03, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_LOW, DP_SP_ACTIVE_LOW, 8U, 1U},
+ {9U, 1716U, 1440U, 276U, 124U, 38U, 114U, 15.734, 262U, 240U, 22.0, 3U, 4U, 15U, 60.054, 27.00, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_LOW, DP_SP_ACTIVE_LOW, 8U, 1U},
+ {9U, 1716U, 1440U, 276U, 124U, 38U, 114U, 15.75, 262U, 240U, 22.0, 3U, 4U, 15U, 60.115, 27.03, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_LOW, DP_SP_ACTIVE_LOW, 8U, 1U},
+ {9U, 1716U, 1440U, 276U, 124U, 38U, 114U, 15.734, 263U, 240U, 23.0, 3U, 5U, 15U, 59.826, 27.00, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_LOW, DP_SP_ACTIVE_LOW, 8U, 1U},
+ {9U, 1716U, 1440U, 276U, 124U, 38U, 114U, 15.75, 263U, 240U, 23.0, 3U, 5U, 15U, 59.886, 27.03, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_LOW, DP_SP_ACTIVE_LOW, 8U, 1U},
+ {10U, 3432U, 2880U, 552U, 248U, 76U, 228U, 15.734, 525U, 480U, 22.51, 3U, 4U, 15U, 59.94, 54.00, DP_SM_INTERLACED, DP_SP_ACTIVE_LOW, DP_SP_ACTIVE_LOW, 8U, 3U},
+ {10U, 3432U, 2880U, 552U, 248U, 76U, 228U, 15.75, 525U, 480U, 22.51, 3U, 4U, 15U, 60.0, 54.05, DP_SM_INTERLACED, DP_SP_ACTIVE_LOW, DP_SP_ACTIVE_LOW, 8U, 3U},
+ {11U, 3432U, 2880U, 552U, 248U, 76U, 228U, 15.734, 525U, 480U, 22.51, 3U, 4U, 15U, 59.94, 54.00, DP_SM_INTERLACED, DP_SP_ACTIVE_LOW, DP_SP_ACTIVE_LOW, 8U, 3U},
+ {11U, 3432U, 2880U, 552U, 248U, 76U, 228U, 15.75, 525U, 480U, 22.51, 3U, 4U, 15U, 60.0, 54.05, DP_SM_INTERLACED, DP_SP_ACTIVE_LOW, DP_SP_ACTIVE_LOW, 8U, 3U},
+ {12U, 3432U, 2880U, 552U, 248U, 76U, 228U, 15.734, 262U, 240U, 22.0, 3U, 4U, 15U, 60.054, 54.00, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_LOW, DP_SP_ACTIVE_LOW, 8U, 3U},
+ {12U, 3432U, 2880U, 552U, 248U, 76U, 228U, 15.75, 262U, 240U, 22.0, 3U, 4U, 15U, 60.115, 54.05, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_LOW, DP_SP_ACTIVE_LOW, 8U, 3U},
+ {12U, 3432U, 2880U, 552U, 248U, 76U, 228U, 15.734, 263U, 240U, 23.0, 3U, 5U, 15U, 59.826, 54.00, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_LOW, DP_SP_ACTIVE_LOW, 8U, 3U},
+ {12U, 3432U, 2880U, 552U, 248U, 76U, 228U, 15.75, 263U, 240U, 23.0, 3U, 5U, 15U, 59.886, 54.05, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_LOW, DP_SP_ACTIVE_LOW, 8U, 3U},
+ {13U, 3432U, 2880U, 552U, 248U, 76U, 228U, 15.734, 262U, 240U, 22.0, 3U, 4U, 15U, 60.054, 54.00, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_LOW, DP_SP_ACTIVE_LOW, 8U, 3U},
+ {13U, 3432U, 2880U, 552U, 248U, 76U, 228U, 15.75, 262U, 240U, 22.0, 3U, 4U, 15U, 60.115, 54.05, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_LOW, DP_SP_ACTIVE_LOW, 8U, 3U},
+ {13U, 3432U, 2880U, 552U, 248U, 76U, 228U, 15.734, 263U, 240U, 23.0, 3U, 5U, 15U, 59.826, 54.00, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_LOW, DP_SP_ACTIVE_LOW, 8U, 3U},
+ {13U, 3432U, 2880U, 552U, 248U, 76U, 228U, 15.75, 263U, 240U, 23.0, 3U, 5U, 15U, 59.886, 54.05, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_LOW, DP_SP_ACTIVE_LOW, 8U, 3U},
+ {14U, 1716U, 1440U, 276U, 124U, 32U, 120U, 31.469, 525U, 480U, 45.0, 6U, 9U, 30U, 59.94, 54.00, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_LOW, DP_SP_ACTIVE_LOW, 8U, 0U},
+ {14U, 1716U, 1440U, 276U, 124U, 32U, 120U, 31.5, 525U, 480U, 45.0, 6U, 9U, 30U, 60.0, 54.05, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_LOW, DP_SP_ACTIVE_LOW, 8U, 0U},
+ {15U, 1716U, 1440U, 276U, 124U, 32U, 120U, 31.469, 525U, 480U, 45.0, 6U, 9U, 30U, 59.94, 54.00, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_LOW, DP_SP_ACTIVE_LOW, 8U, 0U},
+ {15U, 1716U, 1440U, 276U, 124U, 32U, 120U, 31.5, 525U, 480U, 45.0, 6U, 9U, 30U, 60.0, 54.05, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_LOW, DP_SP_ACTIVE_LOW, 8U, 0U},
+ {16U, 2200U, 1920U, 280U, 44U, 88U, 148U, 67.433, 1125U, 1080U, 45.0, 5U, 4U, 36U, 59.94, 148.35, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_HIGH, DP_SP_ACTIVE_HIGH, 8U, 0U},
+ {16U, 2200U, 1920U, 280U, 44U, 88U, 148U, 67.5, 1125U, 1080U, 45.0, 5U, 4U, 36U, 60.0, 148.50, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_HIGH, DP_SP_ACTIVE_HIGH, 8U, 0U},
+ {17U, 864U, 720U, 144U, 64U, 12U, 68U, 31.25, 625U, 576U, 49.0, 5U, 5U, 39U, 50.0, 27.00, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_LOW, DP_SP_ACTIVE_LOW, 8U, 0U},
+ {18U, 864U, 720U, 144U, 64U, 12U, 68U, 31.25, 625U, 576U, 49.0, 5U, 5U, 39U, 50.0, 27.00, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_LOW, DP_SP_ACTIVE_LOW, 8U, 0U},
+ {19U, 1980U, 1280U, 700U, 40U, 440U, 220U, 37.5, 750U, 720U, 30.0, 5U, 5U, 20U, 50.0, 74.25, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_HIGH, DP_SP_ACTIVE_HIGH, 8U, 0U},
+ {20U, 2640U, 1920U, 720U, 44U, 528U, 148U, 28.125, 1125U, 1080U, 22.51, 5U, 2U, 15U, 50.0, 74.25, DP_SM_INTERLACED, DP_SP_ACTIVE_HIGH, DP_SP_ACTIVE_HIGH, 8U, 0U},
+ {21U, 1728U, 1440U, 288U, 126U, 24U, 138U, 15.625, 625U, 576U, 24.51, 3U, 2U, 19U, 50.0, 27.00, DP_SM_INTERLACED, DP_SP_ACTIVE_LOW, DP_SP_ACTIVE_LOW, 8U, 1U},
+ {22U, 1728U, 1440U, 288U, 126U, 24U, 138U, 15.625, 625U, 576U, 24.51, 3U, 2U, 19U, 50.0, 27.00, DP_SM_INTERLACED, DP_SP_ACTIVE_LOW, DP_SP_ACTIVE_LOW, 8U, 1U},
+ {23U, 1728U, 1440U, 288U, 126U, 24U, 138U, 15.625, 312U, 288U, 24.0, 3U, 2U, 19U, 50.08, 27.00, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_LOW, DP_SP_ACTIVE_LOW, 8U, 1U},
+ {23U, 1728U, 1440U, 288U, 126U, 24U, 138U, 15.625, 313U, 288U, 25.0, 3U, 3U, 19U, 49.92, 27.00, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_LOW, DP_SP_ACTIVE_LOW, 8U, 1U},
+ {23U, 1728U, 1440U, 288U, 126U, 24U, 138U, 15.625, 314U, 288U, 26.0, 3U, 4U, 19U, 49.761, 27.00, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_LOW, DP_SP_ACTIVE_LOW, 8U, 1U},
+ {24U, 1728U, 1440U, 288U, 126U, 24U, 138U, 15.625, 312U, 288U, 24.0, 3U, 2U, 19U, 50.08, 27.00, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_LOW, DP_SP_ACTIVE_LOW, 8U, 1U},
+ {24U, 1728U, 1440U, 288U, 126U, 24U, 138U, 15.625, 313U, 288U, 25.0, 3U, 3U, 19U, 49.92, 27.00, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_LOW, DP_SP_ACTIVE_LOW, 8U, 1U},
+ {24U, 1728U, 1440U, 288U, 126U, 24U, 138U, 15.625, 314U, 288U, 26.0, 3U, 4U, 19U, 49.761, 27.00, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_LOW, DP_SP_ACTIVE_LOW, 8U, 1U},
+ {25U, 3456U, 2880U, 576U, 252U, 48U, 276U, 15.625, 625U, 576U, 24.51, 3U, 2U, 19U, 50.0, 54.00, DP_SM_INTERLACED, DP_SP_ACTIVE_LOW, DP_SP_ACTIVE_LOW, 8U, 3U},
+ {26U, 3456U, 2880U, 576U, 252U, 48U, 276U, 15.625, 625U, 576U, 24.51, 3U, 2U, 19U, 50.0, 54.00, DP_SM_INTERLACED, DP_SP_ACTIVE_LOW, DP_SP_ACTIVE_LOW, 8U, 3U},
+ {27U, 3456U, 2880U, 576U, 252U, 48U, 276U, 15.625, 312U, 288U, 24.0, 3U, 2U, 19U, 50.08, 54.00, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_LOW, DP_SP_ACTIVE_LOW, 8U, 3U},
+ {27U, 3456U, 2880U, 576U, 252U, 48U, 276U, 15.625, 313U, 288U, 25.0, 3U, 3U, 19U, 49.92, 54.00, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_LOW, DP_SP_ACTIVE_LOW, 8U, 3U},
+ {27U, 3456U, 2880U, 576U, 252U, 48U, 276U, 15.625, 314U, 288U, 26.0, 3U, 4U, 19U, 49.761, 54.00, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_LOW, DP_SP_ACTIVE_LOW, 8U, 3U},
+ {28U, 3456U, 2880U, 576U, 252U, 48U, 276U, 15.625, 312U, 288U, 24.0, 3U, 2U, 19U, 50.08, 54.00, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_LOW, DP_SP_ACTIVE_LOW, 8U, 3U},
+ {28U, 3456U, 2880U, 576U, 252U, 48U, 276U, 15.625, 313U, 288U, 25.0, 3U, 3U, 19U, 49.92, 54.00, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_LOW, DP_SP_ACTIVE_LOW, 8U, 3U},
+ {28U, 3456U, 2880U, 576U, 252U, 48U, 276U, 15.625, 314U, 288U, 26.0, 3U, 4U, 19U, 49.761, 54.00, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_LOW, DP_SP_ACTIVE_LOW, 8U, 3U},
+ {29U, 1728U, 1440U, 288U, 128U, 24U, 136U, 31.25, 625U, 576U, 49.0, 5U, 5U, 39U, 50.0, 54.00, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_LOW, DP_SP_ACTIVE_LOW, 8U, 3U},
+ {30U, 1728U, 1440U, 288U, 128U, 24U, 136U, 31.25, 625U, 576U, 49.0, 5U, 5U, 39U, 50.0, 54.00, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_LOW, DP_SP_ACTIVE_LOW, 8U, 3U},
+ {31U, 2640U, 1920U, 720U, 44U, 528U, 148U, 56.25, 1125U, 1080U, 45.0, 5U, 4U, 36U, 50.0, 148.50, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_HIGH, DP_SP_ACTIVE_HIGH, 8U, 0U},
+ {32U, 2750U, 1920U, 830U, 44U, 638U, 148U, 26.973, 1125U, 1080U, 45.0, 5U, 4U, 36U, 23.976, 74.18, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_HIGH, DP_SP_ACTIVE_HIGH, 8U, 0U},
+ {32U, 2750U, 1920U, 830U, 44U, 638U, 148U, 27.0, 1125U, 1080U, 45.0, 5U, 4U, 36U, 24.0003, 74.25, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_HIGH, DP_SP_ACTIVE_HIGH, 8U, 0U},
+ {33U, 2640U, 1920U, 720U, 44U, 528U, 148U, 28.125, 1125U, 1080U, 45.0, 5U, 4U, 36U, 25.0, 74.25, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_HIGH, DP_SP_ACTIVE_HIGH, 8U, 0U},
+ {34U, 2200U, 1920U, 280U, 44U, 88U, 148U, 33.716, 1125U, 1080U, 45.0, 5U, 4U, 36U, 29.97, 74.18, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_HIGH, DP_SP_ACTIVE_HIGH, 8U, 0U},
+ {34U, 2200U, 1920U, 280U, 44U, 88U, 148U, 33.75, 1125U, 1080U, 45.0, 5U, 4U, 36U, 30.0003, 74.25, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_HIGH, DP_SP_ACTIVE_HIGH, 8U, 0U},
+ {35U, 3432U, 2880U, 552U, 248U, 64U, 240U, 31.469, 525U, 480U, 45.0, 6U, 9U, 30U, 59.94, 108.00, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_LOW, DP_SP_ACTIVE_LOW, 8U, 0U},
+ {35U, 3432U, 2880U, 552U, 248U, 64U, 240U, 31.5, 525U, 480U, 45.0, 6U, 9U, 30U, 60.0, 108.11, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_LOW, DP_SP_ACTIVE_LOW, 8U, 0U},
+ {36U, 3432U, 2880U, 552U, 248U, 64U, 240U, 31.469, 525U, 480U, 45.0, 6U, 9U, 30U, 59.94, 108.00, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_LOW, DP_SP_ACTIVE_LOW, 8U, 0U},
+ {36U, 3432U, 2880U, 552U, 248U, 64U, 240U, 31.5, 525U, 480U, 45.0, 6U, 9U, 30U, 60.0, 108.11, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_LOW, DP_SP_ACTIVE_LOW, 8U, 0U},
+ {37U, 3456U, 2880U, 576U, 256U, 48U, 272U, 31.25, 625U, 576U, 49.0, 5U, 5U, 39U, 50.0, 108.00, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_LOW, DP_SP_ACTIVE_LOW, 8U, 0U},
+ {38U, 3456U, 2880U, 576U, 256U, 48U, 272U, 31.25, 625U, 576U, 49.0, 5U, 5U, 39U, 50.0, 108.00, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_LOW, DP_SP_ACTIVE_LOW, 8U, 0U},
+ {39U, 2304U, 1920U, 384U, 168U, 32U, 184U, 31.25, 1250U, 1080U, 85.0, 5U, 23U, 57U, 50.0, 72.00, DP_SM_INTERLACED, DP_SP_ACTIVE_HIGH, DP_SP_ACTIVE_LOW, 8U, 0U},
+ {40U, 2640U, 1920U, 720U, 44U, 528U, 148U, 56.25, 1125U, 1080U, 22.51, 5U, 2U, 15U, 100.0, 148.50, DP_SM_INTERLACED, DP_SP_ACTIVE_HIGH, DP_SP_ACTIVE_HIGH, 8U, 0U},
+ {41U, 1980U, 1280U, 700U, 40U, 440U, 220U, 75.0, 750U, 720U, 30.0, 5U, 5U, 20U, 100.0, 148.50, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_HIGH, DP_SP_ACTIVE_HIGH, 8U, 0U},
+ {42U, 864U, 720U, 144U, 64U, 12U, 68U, 62.5, 625U, 576U, 49.0, 5U, 5U, 39U, 100.0, 54.00, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_LOW, DP_SP_ACTIVE_LOW, 8U, 0U},
+ {43U, 864U, 720U, 144U, 64U, 12U, 68U, 62.5, 625U, 576U, 49.0, 5U, 5U, 39U, 100.0, 54.00, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_LOW, DP_SP_ACTIVE_LOW, 8U, 0U},
+ {44U, 1728U, 1440U, 288U, 126U, 24U, 138U, 31.25, 625U, 576U, 24.51, 3U, 2U, 19U, 100.0, 54.00, DP_SM_INTERLACED, DP_SP_ACTIVE_LOW, DP_SP_ACTIVE_LOW, 8U, 1U},
+ {45U, 1728U, 1440U, 288U, 126U, 24U, 138U, 31.25, 625U, 576U, 24.51, 3U, 2U, 19U, 100.0, 54.00, DP_SM_INTERLACED, DP_SP_ACTIVE_LOW, DP_SP_ACTIVE_LOW, 8U, 1U},
+ {46U, 2200U, 1920U, 280U, 44U, 88U, 148U, 67.432, 1125U, 1080U, 22.51, 5U, 2U, 15U, 119.88, 148.35, DP_SM_INTERLACED, DP_SP_ACTIVE_HIGH, DP_SP_ACTIVE_HIGH, 8U, 0U},
+ {46U, 2200U, 1920U, 280U, 44U, 88U, 148U, 67.5, 1125U, 1080U, 22.51, 5U, 2U, 15U, 120.0, 148.50, DP_SM_INTERLACED, DP_SP_ACTIVE_HIGH, DP_SP_ACTIVE_HIGH, 8U, 0U},
+ {47U, 1650U, 1280U, 370U, 40U, 110U, 220U, 89.909, 750U, 720U, 30.0, 5U, 5U, 20U, 119.88, 148.35, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_HIGH, DP_SP_ACTIVE_HIGH, 8U, 0U},
+ {47U, 1650U, 1280U, 370U, 40U, 110U, 220U, 90.0, 750U, 720U, 30.0, 5U, 5U, 20U, 120.0, 148.50, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_HIGH, DP_SP_ACTIVE_HIGH, 8U, 0U},
+ {48U, 858U, 720U, 138U, 62U, 16U, 60U, 62.937, 525U, 480U, 45.0, 6U, 9U, 30U, 119.88, 54.00, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_LOW, DP_SP_ACTIVE_LOW, 8U, 0U},
+ {48U, 858U, 720U, 138U, 62U, 16U, 60U, 63.0, 525U, 480U, 45.0, 6U, 9U, 30U, 120.0, 54.05, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_LOW, DP_SP_ACTIVE_LOW, 8U, 0U},
+ {49U, 858U, 720U, 138U, 62U, 16U, 60U, 62.937, 525U, 480U, 45.0, 6U, 9U, 30U, 119.88, 54.00, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_LOW, DP_SP_ACTIVE_LOW, 8U, 0U},
+ {49U, 858U, 720U, 138U, 62U, 16U, 60U, 63.0, 525U, 480U, 45.0, 6U, 9U, 30U, 120.0, 54.05, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_LOW, DP_SP_ACTIVE_LOW, 8U, 0U},
+ {50U, 1716U, 1440U, 276U, 124U, 38U, 114U, 31.469, 525U, 480U, 22.51, 3U, 4U, 15U, 119.88, 54.00, DP_SM_INTERLACED, DP_SP_ACTIVE_LOW, DP_SP_ACTIVE_LOW, 8U, 1U},
+ {50U, 1716U, 1440U, 276U, 124U, 38U, 114U, 31.5, 525U, 480U, 22.51, 3U, 4U, 15U, 120.0, 54.05, DP_SM_INTERLACED, DP_SP_ACTIVE_LOW, DP_SP_ACTIVE_LOW, 8U, 1U},
+ {51U, 1716U, 1440U, 276U, 124U, 38U, 114U, 31.469, 525U, 480U, 22.51, 3U, 4U, 15U, 119.88, 54.00, DP_SM_INTERLACED, DP_SP_ACTIVE_LOW, DP_SP_ACTIVE_LOW, 8U, 1U},
+ {51U, 1716U, 1440U, 276U, 124U, 38U, 114U, 31.5, 525U, 480U, 22.51, 3U, 4U, 15U, 120.0, 54.05, DP_SM_INTERLACED, DP_SP_ACTIVE_LOW, DP_SP_ACTIVE_LOW, 8U, 1U},
+ {52U, 864U, 720U, 144U, 64U, 12U, 68U, 125.0, 625U, 576U, 49.0, 5U, 5U, 39U, 200.0, 108.00, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_LOW, DP_SP_ACTIVE_LOW, 8U, 0U},
+ {53U, 864U, 720U, 144U, 64U, 12U, 68U, 125.0, 625U, 576U, 49.0, 5U, 5U, 39U, 200.0, 108.00, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_LOW, DP_SP_ACTIVE_LOW, 8U, 0U},
+ {54U, 1728U, 1440U, 288U, 126U, 24U, 138U, 62.5, 625U, 576U, 24.51, 3U, 2U, 19U, 200.0, 108.00, DP_SM_INTERLACED, DP_SP_ACTIVE_LOW, DP_SP_ACTIVE_LOW, 8U, 1U},
+ {55U, 1728U, 1440U, 288U, 126U, 24U, 138U, 62.5, 625U, 576U, 24.51, 3U, 2U, 19U, 200.0, 108.00, DP_SM_INTERLACED, DP_SP_ACTIVE_LOW, DP_SP_ACTIVE_LOW, 8U, 1U},
+ {56U, 858U, 720U, 138U, 62U, 16U, 60U, 125.874, 525U, 480U, 45.0, 6U, 9U, 30U, 239.76, 108.00, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_LOW, DP_SP_ACTIVE_LOW, 8U, 0U},
+ {56U, 858U, 720U, 138U, 62U, 16U, 60U, 126.0, 525U, 480U, 45.0, 6U, 9U, 30U, 240.0, 108.11, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_LOW, DP_SP_ACTIVE_LOW, 8U, 0U},
+ {57U, 858U, 720U, 138U, 62U, 16U, 60U, 125.874, 525U, 480U, 45.0, 6U, 9U, 30U, 239.76, 108.00, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_LOW, DP_SP_ACTIVE_LOW, 8U, 0U},
+ {57U, 858U, 720U, 138U, 62U, 16U, 60U, 126.0, 525U, 480U, 45.0, 6U, 9U, 30U, 240.0, 108.11, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_LOW, DP_SP_ACTIVE_LOW, 8U, 0U},
+ {58U, 1716U, 1440U, 276U, 124U, 38U, 114U, 62.937, 525U, 480U, 22.51, 3U, 4U, 15U, 239.76, 108.00, DP_SM_INTERLACED, DP_SP_ACTIVE_LOW, DP_SP_ACTIVE_LOW, 8U, 1U},
+ {58U, 1716U, 1440U, 276U, 124U, 38U, 114U, 63.0, 525U, 480U, 22.51, 3U, 4U, 15U, 240.0, 108.11, DP_SM_INTERLACED, DP_SP_ACTIVE_LOW, DP_SP_ACTIVE_LOW, 8U, 1U},
+ {59U, 1716U, 1440U, 276U, 124U, 38U, 114U, 62.937, 525U, 480U, 22.51, 3U, 4U, 15U, 239.76, 108.00, DP_SM_INTERLACED, DP_SP_ACTIVE_LOW, DP_SP_ACTIVE_LOW, 8U, 1U},
+ {59U, 1716U, 1440U, 276U, 124U, 38U, 114U, 63.0, 525U, 480U, 22.51, 3U, 4U, 15U, 240.0, 108.11, DP_SM_INTERLACED, DP_SP_ACTIVE_LOW, DP_SP_ACTIVE_LOW, 8U, 1U},
+ {60U, 3300U, 1280U, 2020U, 40U, 1760U, 220U, 17.977, 750U, 720U, 30.0, 5U, 5U, 20U, 23.97, 59.34, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_HIGH, DP_SP_ACTIVE_HIGH, 8U, 0U},
+ {60U, 3300U, 1280U, 2020U, 40U, 1760U, 220U, 18.0, 750U, 720U, 30.0, 5U, 5U, 20U, 24.0, 59.4, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_HIGH, DP_SP_ACTIVE_HIGH, 8U, 0U},
+ {61U, 3960U, 1280U, 2680U, 40U, 2420U, 220U, 18.75, 750U, 720U, 30.0, 5U, 5U, 20U, 25.0, 74.25, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_HIGH, DP_SP_ACTIVE_HIGH, 8U, 0U},
+ {62U, 3300U, 1280U, 2020U, 40U, 1760U, 220U, 22.477, 750U, 720U, 30.0, 5U, 5U, 20U, 29.97, 74.176, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_HIGH, DP_SP_ACTIVE_HIGH, 8U, 0U},
+ {62U, 3300U, 1280U, 2020U, 40U, 1760U, 220U, 22.5, 750U, 720U, 30.0, 5U, 5U, 20U, 30.0, 74.25, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_HIGH, DP_SP_ACTIVE_HIGH, 8U, 0U},
+ {63U, 2200U, 1920U, 280U, 44U, 88U, 148U, 134.865, 1125U, 1080U, 45.0, 5U, 4U, 36U, 119.88, 296.703, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_HIGH, DP_SP_ACTIVE_HIGH, 8U, 0U},
+ {63U, 2200U, 1920U, 280U, 44U, 88U, 148U, 135.0, 1125U, 1080U, 45.0, 5U, 4U, 36U, 120.0, 297.0, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_HIGH, DP_SP_ACTIVE_HIGH, 8U, 0U},
+ {64U, 2640U, 1920U, 720U, 44U, 528U, 148U, 112.5, 1125U, 1080U, 45.0, 5U, 4U, 36U, 100.0, 297.0, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_HIGH, DP_SP_ACTIVE_HIGH, 8U, 0U},
+ {97U, 4400U, 3840U, 560U, 88U, 176U, 296U, 135.0, 2250U, 2160U, 90.0, 10U, 8U, 72U, 60.0, 594.0, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_HIGH, DP_SP_ACTIVE_HIGH, 8U, 0U},
+ {114U, 1056U, 800U, 256U, 128U, 40U, 88U, 37.879, 628U, 600U, 28.0, 4U, 1U, 23U, 60.317, 40.0, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_HIGH, DP_SP_ACTIVE_HIGH, 8U, 0U},
+ {115U, 896U, 720U, 176U, 64U, 24U, 88U, 24.833, 419U, 400U, 19.0, 10U, 3U, 6U, 59.26, 22.250, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_HIGH, DP_SP_ACTIVE_HIGH, 8U, 0U},
+ {116U, 912U, 720U, 192U, 72U, 24U, 96U, 37.00657895, 424U, 400U, 24.0, 10U, 3U, 11U, 87.27966733, 33.75, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_HIGH, DP_SP_ACTIVE_HIGH, 8U, 0U},
+ {117U, 800U, 640U, 160U, 64U, 16U, 80U, 29.6875, 500U, 480U, 20.0, 4U, 3U, 13U, 59.375, 23.75, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_HIGH, DP_SP_ACTIVE_HIGH, 8U, 0U},
+ {118U, 800U, 640U, 160U, 64U, 16U, 80U, 33.4375, 502U, 480U, 22.0, 4U, 3U, 15U, 66.60856574, 26.75, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_HIGH, DP_SP_ACTIVE_HIGH, 8U, 0U},
+ {119U, 816U, 640U, 176U, 64U, 24U, 88U, 36.15196078, 503U, 480U, 23.0, 4U, 3U, 16U, 71.87268546, 29.5, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_HIGH, DP_SP_ACTIVE_HIGH, 8U, 0U},
+ {120U, 816U, 640U, 176U, 64U, 24U, 88U, 37.68382353, 504U, 480U, 24.0, 4U, 3U, 17U, 74.76949113, 30.75, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_HIGH, DP_SP_ACTIVE_HIGH, 8U, 0U},
+ {121U, 1008U, 800U, 208U, 80U, 24U, 104U, 34.72222222, 623U, 600U, 23.0, 4U, 3U, 16U, 55.73390405, 35.0, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_HIGH, DP_SP_ACTIVE_HIGH, 8U, 0U},
+ {122U, 1040U, 800U, 240U, 80U, 40U, 120U, 45.19230769, 628U, 600U, 28.0, 4U, 3U, 21U, 71.9622734, 47.0, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_HIGH, DP_SP_ACTIVE_HIGH, 8U, 0U},
+ {123U, 1088U, 832U, 256U, 80U, 48U, 128U, 48.94301471, 654U, 624U, 30.0, 4U, 3U, 23U, 74.83641392, 53.25, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_HIGH, DP_SP_ACTIVE_HIGH, 8U, 0U},
+ {124U, 1376U, 1024U, 352U, 104U, 72U, 176U, 74.49127907, 859U, 768U, 45.0, 4U, 3U, 38U, 86.71860194, 102.5, DP_SM_INTERLACED, DP_SP_ACTIVE_HIGH, DP_SP_ACTIVE_HIGH, 8U, 0U},
+ {125U, 1328U, 1024U, 304U, 104U, 48U, 152U, 47.81626506, 798U, 768U, 30.0, 4U, 3U, 23U, 59.92013165, 63.5, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_HIGH, DP_SP_ACTIVE_HIGH, 8U, 0U},
+ {126U, 1360U, 1024U, 336U, 104U, 64U, 168U, 57.72058824, 803U, 768U, 35.0, 4U, 3U, 28U, 71.88118087, 78.5, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_HIGH, DP_SP_ACTIVE_HIGH, 8U, 0U},
+ {127U, 1360U, 1024U, 336U, 104U, 64U, 168U, 60.29411765, 805U, 768U, 37.0, 4U, 3U, 30U, 74.89952503, 82.0, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_HIGH, DP_SP_ACTIVE_HIGH, 8U, 0U},
+ {128U, 1728U, 1280U, 448U, 136U, 88U, 224U, 80.29513889, 1072U, 1024U, 48.0, 7U, 3U, 38U, 74.9021818, 138.75, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_HIGH, DP_SP_ACTIVE_HIGH, 8U, 0U},
+ {129U, 1536U, 1152U, 384U, 120U, 72U, 192U, 68.19661458, 911U, 870U, 41.0, 10U, 3U, 28U, 74.85907199, 104.75, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_HIGH, DP_SP_ACTIVE_HIGH, 8U, 0U},
+ {130U, 2200, 1920, 280, 44, 88, 148, 66.587, 1125, 1080, 45, 5, 4, 36, 59.93, 148.5, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_HIGH, DP_SP_ACTIVE_HIGH, 8, 0},
+ {131U, 2720, 2560, 160, 32, 48, 80, 88.787, 1481, 1440, 41, 5, 3, 33, 59.95, 240, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_HIGH, DP_SP_ACTIVE_HIGH, 8, 0},
+ {132U, 4000, 3840, 160, 32, 48, 80, 133.313, 2222, 2160, 62, 5, 3, 54, 59.99, 533.25, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_HIGH, DP_SP_ACTIVE_HIGH, 8, 0},
+ {0U, 5500U, 5120U, 380U, 88U, 164U, 128U, 135.0, 2250U, 2160U, 90.0, 10U, 8U, 72U, 60.0, 742.50, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_HIGH, DP_SP_ACTIVE_HIGH, 8U, 0U},
+ {1U, 800U, 640U, 160U, 96U, 16U, 48U, 31.469, 36U, 20U, 16.0, 2U, 3U, 11U, 59.94, 25.18, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_LOW, DP_SP_ACTIVE_LOW, 8U, 0U},
+ {2U, 858U, 720U, 138U, 62U, 16U, 60U, 31.469, 36U, 20U, 16.0, 2U, 3U, 11U, 59.94, 27.00, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_LOW, DP_SP_ACTIVE_LOW, 8U, 0U},
+ {4U, 1650U, 1280U, 370U, 40U, 110U, 220U, 44.955, 36U, 20U, 16.0, 2U, 3U, 11U, 59.94, 74.18, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_HIGH, DP_SP_ACTIVE_HIGH, 8U, 0U},
+ {14U, 1716U, 1440U, 276U, 124U, 32U, 120U, 31.469, 36U, 20U, 16.0, 2U, 3U, 11U, 59.94, 54.00, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_LOW, DP_SP_ACTIVE_LOW, 8U, 0U},
+ {16U, 2200U, 1920U, 280U, 44U, 88U, 148U, 67.433, 36U, 20U, 16.0, 2U, 3U, 11U, 59.94, 148.35, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_HIGH, DP_SP_ACTIVE_HIGH, 8U, 0U},
+ {17U, 864U, 720U, 144U, 64U, 12U, 68U, 31.25, 36U, 20U, 16.0, 2U, 3U, 11U, 50.0, 27.00, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_LOW, DP_SP_ACTIVE_LOW, 8U, 0U},
+ {25U, 3456U, 2880U, 576U, 252U, 48U, 276U, 15.625, 36U, 20U, 16.0, 2U, 3U, 11U, 50.0, 54.00, DP_SM_INTERLACED, DP_SP_ACTIVE_LOW, DP_SP_ACTIVE_LOW, 8U, 3U},
+ {28U, 3456U, 2880U, 576U, 252U, 48U, 276U, 15.625, 36U, 20U, 16.0, 2U, 3U, 11U, 50.08, 54.00, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_LOW, DP_SP_ACTIVE_LOW, 8U, 3U},
+ {31U, 2640U, 1920U, 720U, 44U, 528U, 148U, 56.25, 36U, 20U, 16.0, 2U, 3U, 11U, 50.0, 148.50, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_HIGH, DP_SP_ACTIVE_HIGH, 8U, 0U},
+ {32U, 2750U, 1920U, 830U, 44U, 638U, 148U, 26.973, 36U, 20U, 16.0, 2U, 3U, 11U, 23.976, 74.18, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_HIGH, DP_SP_ACTIVE_HIGH, 8U, 0U},
+ {35U, 3432U, 2880U, 552U, 248U, 64U, 240U, 31.469, 36U, 20U, 16.0, 2U, 3U, 11U, 59.94, 108.00, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_LOW, DP_SP_ACTIVE_LOW, 8U, 0U},
+ {47U, 1650U, 1280U, 370U, 40U, 110U, 220U, 89.909, 36U, 20U, 16.0, 2U, 3U, 11U, 119.88, 148.35, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_HIGH, DP_SP_ACTIVE_HIGH, 8U, 0U},
+ {49U, 858U, 720U, 138U, 62U, 16U, 60U, 62.937, 36U, 20U, 16.0, 2U, 3U, 11U, 119.88, 54.00, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_LOW, DP_SP_ACTIVE_LOW, 8U, 0U},
+ {52U, 864U, 720U, 144U, 64U, 12U, 68U, 125.0, 36U, 20U, 16.0, 2U, 3U, 11U, 200.0, 108.00, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_LOW, DP_SP_ACTIVE_LOW, 8U, 0U},
+ {57U, 858U, 720U, 138U, 62U, 16U, 60U, 125.874, 36U, 20U, 16.0, 2U, 3U, 11U, 239.76, 108.00, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_LOW, DP_SP_ACTIVE_LOW, 8U, 0U},
+ {58U, 1716U, 1440U, 276U, 124U, 38U, 114U, 62.937, 36U, 20U, 16.0, 2U, 3U, 11U, 239.76, 108.00, DP_SM_INTERLACED, DP_SP_ACTIVE_LOW, DP_SP_ACTIVE_LOW, 8U, 1U},
+ {61U, 3960U, 1280U, 2680U, 40U, 2420U, 220U, 18.75, 36U, 20U, 16.0, 2U, 3U, 11U, 25.0, 74.25, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_HIGH, DP_SP_ACTIVE_HIGH, 8U, 0U},
+ {63U, 2200U, 1920U, 280U, 44U, 88U, 148U, 134.865, 36U, 20U, 16.0, 2U, 3U, 11U, 119.88, 296.703, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_HIGH, DP_SP_ACTIVE_HIGH, 8U, 0U},
+ {0U, 5500U, 5120U, 380U, 88U, 164U, 128U, 135.0, 36U, 20U, 16.0, 2U, 3U, 11U, 60.0, 742.50, DP_SM_PROGRESSIVE, DP_SP_ACTIVE_HIGH, DP_SP_ACTIVE_HIGH, 8U, 0U}
+ };
+
+ retVal = DP_FillVideoFormatSF(vicParams, vicMode);
+
+ if (CDN_EOK == retVal) {
+ if (DP_VIC_MODE_COUNT == vicMode) {
+ retVal = CDN_EINVAL;
+ }
+ }
+
+ if (CDN_EOK == retVal)
+ {
+ CPS_BufferCopy((uint8_t*)vicParams,
+ (const uint8_t*)&(vicTable[vicMode]),
+ (uint32_t)sizeof(DP_VideoFormatParams));
+ }
+
+ return retVal;
+}
+/* parasoft-end-suppress METRICS-39-3 */
+
+uint32_t DP_SetVic(DP_PrivateData* pD, uint8_t streamId, const DP_VideoParameters *parameters)
+{
+ uint32_t retVal;
+
+ retVal = DP_SetVicSF(pD, parameters);
+
+ if (CDN_EOK == retVal) {
+ retVal = checkVideoParams(parameters);
+ }
+
+ if (CDN_EOK == retVal) {
+ retVal = checkPhyInit(pD);
+ }
+
+ if (CDN_EOK == retVal) {
+ retVal = DP_StreamIdMstSstSanity(pD, streamId);
+ }
+
+ if (CDN_EOK == retVal) {
+ retVal = configureVicParams(pD, streamId, parameters);
+ }
+
+ if (CDN_EOK == retVal) {
+ retVal = setVifClock(pD, streamId, true);
+ }
+
+ if (CDN_EOK == retVal) {
+ if (streamId < DP_NUMBER_OF_DSC_ENCODERS) {
+ retVal = DP_DscStreamEnable(pD, streamId, pD->videoParameters[streamId].dscEnable);
+ }
+ }
+
+ if (CDN_EOK == retVal) {
+ if (!pD->mstEnabled) {
+ pD->sstVicSet = true;
+ }
+ }
+
+ return retVal;
+}
+
+uint32_t DP_SetMsaSyncPolarity(DP_PrivateData* pD,
+ uint8_t streamId,
+ DP_SyncPolarity hSyncPolarity,
+ DP_SyncPolarity vSyncPolarity)
+{
+ uint32_t retVal;
+ uint32_t addr;
+ DP_WriteFieldRequest req;
+
+ retVal = DP_SetMsaSyncPolaritySF(pD, hSyncPolarity, vSyncPolarity);
+
+ if (CDN_EOK == retVal) {
+ retVal = DP_StreamIdMstSstSanity(pD, streamId);
+ }
+
+ if (CDN_EOK == retVal) {
+ addr = offsetof(MHDP_ApbRegs, mhdp_apb_regs.mhdp_dptx_stream[0].MSA_HORIZONTAL_1_p);
+ addr += streamId * (uint32_t)sizeof(pD->regBase->mhdp_apb_regs.mhdp_dptx_stream[0]);
+ req.addr = addr;
+ req.startBit = MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__MSA_HORIZONTAL_1_P__PCK_STUFF_HSYNCPOLARITY_SHIFT;
+ req.bitCount = MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__MSA_HORIZONTAL_1_P__PCK_STUFF_HSYNCPOLARITY_WIDTH;
+ req.val = CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__MSA_HORIZONTAL_1_P,
+ PCK_STUFF_HSYNCPOLARITY,
+ 0U,
+ (DP_SP_ACTIVE_LOW == hSyncPolarity) ? 1U : 0U);
+ retVal = DP_WriteField(pD, &req);
+ }
+ if (CDN_EOK == retVal) {
+ addr = offsetof(MHDP_ApbRegs, mhdp_apb_regs.mhdp_dptx_stream[0].MSA_VERTICAL_1_p);
+ addr += streamId * (uint32_t)sizeof(pD->regBase->mhdp_apb_regs.mhdp_dptx_stream[0]);
+ req.addr = addr;
+ req.startBit = MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__MSA_VERTICAL_1_P__PCK_STUFF_VSYNCPOLARITY_SHIFT;
+ req.bitCount = MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__MSA_VERTICAL_1_P__PCK_STUFF_VSYNCPOLARITY_WIDTH;
+ req.val = CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__MSA_VERTICAL_1_P,
+ PCK_STUFF_VSYNCPOLARITY,
+ 0U,
+ (DP_SP_ACTIVE_LOW == vSyncPolarity) ? 1U : 0U);
+ retVal = DP_WriteField(pD, &req);
+ }
+
+ return retVal;
+}
+
+uint32_t DP_SetFramerEnable(DP_PrivateData* pD, bool enable)
+{
+ uint32_t retVal;
+ const uint8_t FramerEnableBitPos = MHDP__MHDP_APB_REGS__DP_FRAMER_GLOBAL_CONFIG_P__GLOBAL_EN_SHIFT;
+ DP_RegisterTransfer regTransfer = {0};
+ DP_WriteFieldRequest req;
+
+ req.addr = offsetof(MHDP_ApbRegs, mhdp_apb_regs.DP_FRAMER_GLOBAL_CONFIG_p);
+ req.startBit = FramerEnableBitPos;
+ req.bitCount = 1;
+ req.val = enable ? MHDP__MHDP_APB_REGS__DP_FRAMER_GLOBAL_CONFIG_P__GLOBAL_EN_MASK : 0U;
+
+ retVal = DP_SetFramerEnableSF(pD);
+
+ if (CDN_EOK == retVal)
+ {
+ retVal = DP_WriteField(pD, &req);
+ }
+
+ if (CDN_EOK == retVal)
+ {
+ /* Register read - to make sure uCPU has finished writing the register. */
+ regTransfer.addr = offsetof(MHDP_ApbRegs, mhdp_apb_regs.DP_FRAMER_GLOBAL_CONFIG_p);
+ retVal = DP_ReadRegister(pD, ®Transfer);
+ }
+
+ return retVal;
+}
+
+uint32_t DP_SetVideoSst(DP_PrivateData* pD, bool mode)
+{
+ uint32_t retVal;
+ const uint8_t noVideoBitPos = MHDP__MHDP_APB_REGS__DP_FRAMER_GLOBAL_CONFIG_P__NO_VIDEO_SHIFT;
+ DP_RegisterTransfer regTransfer = {0};
+ DP_WriteFieldRequest req;
+
+ req.addr = offsetof(MHDP_ApbRegs, mhdp_apb_regs.DP_FRAMER_GLOBAL_CONFIG_p);
+ req.startBit = noVideoBitPos;
+ req.bitCount = 1;
+ req.val = mode ? 0U : MHDP__MHDP_APB_REGS__DP_FRAMER_GLOBAL_CONFIG_P__NO_VIDEO_MASK;
+
+ retVal = DP_SetVideoSstSF(pD);
+
+ if (CDN_EOK == retVal)
+ {
+ retVal = DP_WriteField(pD, &req);
+ }
+
+ if (CDN_EOK == retVal)
+ {
+ /* Register read - to make sure uCPU has finished writing the register. */
+ regTransfer.addr = offsetof(MHDP_ApbRegs, mhdp_apb_regs.DP_FRAMER_GLOBAL_CONFIG_p);
+ retVal = DP_ReadRegister(pD, ®Transfer);
+ }
+
+ return retVal;
+}
+
+uint32_t DP_SendAuxStatusRequest(DP_PrivateData* pD)
+{
+ uint32_t retVal;
+
+ retVal = DP_SendAuxStatusRequestSF(pD);
+
+ if (CDN_EOK == retVal)
+ {
+ messageStart(pD, MB_MODULE_ID_DP_TX, (uint8_t)DPTX_GET_LAST_AUX_STAUS);
+ messageFinish(pD);
+ messageTransmit(pD, DP_BUS_TYPE_APB);
+ }
+
+ return retVal;
+}
+
+uint32_t DP_GetAuxStatusResponse(DP_PrivateData* pD, DP_AuxStatus* status)
+{
+ uint32_t retVal;
+ uint8_t result;
+ uint8_t headerMatching;
+
+ retVal = DP_GetAuxStatusResponseSF(pD, status);
+
+ if (CDN_EOK != retVal)
+ {
+ DbgMsg(DBG_GEN_MSG, DBG_CRIT,
+ "Function for receiving data containing response with AUX status"
+ " was called incorrectly. DPTX Mailbox may not be able to "
+ "operate any more.\n");
+ }
+
+ if (CDN_EOK == retVal)
+ {
+ messageReceive(pD, DP_BUS_TYPE_APB);
+ headerMatching = messageHeaderMatches(pD, MB_MODULE_ID_DP_TX, (uint8_t)DPTX_GET_LAST_AUX_STAUS);
+
+ if (0U == headerMatching) {
+ retVal = CDN_ENOEXEC;
+ }
+ }
+
+ if (CDN_EOK == retVal)
+ {
+ messageGetHeader(pD, NULL, NULL, NULL);
+ messageReadUint8(pD, &result);
+
+ *status = getAuxStatus(result);
+ }
+
+ return retVal;
+}
+
+uint32_t DP_GetAuxStatus(DP_PrivateData* pD, DP_AuxStatus* status)
+{
+ uint32_t retVal;
+
+ retVal = DP_GetAuxStatusSF(pD, status);
+
+ if (CDN_EOK == retVal)
+ {
+ retVal = DP_SendAuxStatusRequest(pD);
+ }
+ if (CDN_EOK == retVal)
+ {
+ retVal = DP_GetAuxStatusResponse(pD, status);
+ }
+
+ return retVal;
+}
+
+uint32_t DP_SendI2cStatusRequest(DP_PrivateData* pD)
+{
+ uint32_t retVal;
+
+ retVal = DP_SendI2cStatusRequestSF(pD);
+
+ if (CDN_EOK == retVal)
+ {
+ messageStart(pD, MB_MODULE_ID_DP_TX, (uint8_t)DPTX_GET_LAST_I2C_STATUS);
+ messageFinish(pD);
+ messageTransmit(pD, DP_BUS_TYPE_APB);
+ }
+
+ return retVal;
+}
+
+uint32_t DP_GetI2cStatusResponse(DP_PrivateData* pD, DP_I2cStatus* status)
+{
+ uint32_t retVal;
+ uint8_t result;
+ uint8_t headerMatching;
+
+ retVal = DP_GetI2cStatusResponseSF(pD, status);
+
+ if (CDN_EOK != retVal)
+ {
+ DbgMsg(DBG_GEN_MSG, DBG_CRIT,
+ "Function for receiving data containing response with I2C status"
+ " was called incorrectly. DPTX Mailbox may not be able to "
+ "operate any more.\n");
+ }
+
+ if (CDN_EOK == retVal)
+ {
+ messageReceive(pD, DP_BUS_TYPE_APB);
+ headerMatching = messageHeaderMatches(pD, MB_MODULE_ID_DP_TX, (uint8_t)DPTX_GET_LAST_I2C_STATUS);
+
+ if (0U == headerMatching) {
+ retVal = CDN_ENOEXEC;
+ }
+ }
+
+ if (CDN_EOK == retVal)
+ {
+ messageGetHeader(pD, NULL, NULL, NULL);
+ messageReadUint8(pD, &result);
+
+ *status = getI2cStatus(result);
+ }
+
+ return retVal;
+}
+
+uint32_t DP_GetI2cStatus(DP_PrivateData* pD, DP_I2cStatus* status)
+{
+ uint32_t retVal;
+
+ retVal = DP_GetI2cStatusSF(pD, status);
+
+ if (CDN_EOK == retVal)
+ {
+ retVal = DP_SendI2cStatusRequest(pD);
+ }
+ if (CDN_EOK == retVal)
+ {
+ retVal = DP_GetI2cStatusResponse(pD, status);
+ }
+
+ return retVal;
+}
+
+uint32_t DP_SendHpdStatusRequest(DP_PrivateData* pD)
+{
+ uint32_t retVal;
+
+ retVal = DP_SendHpdStatusRequestSF(pD);
+
+ if (CDN_EOK == retVal)
+ {
+ messageStart(pD, MB_MODULE_ID_DP_TX, (uint8_t)DPTX_HPD_STATE);
+ messageFinish(pD);
+ messageTransmit(pD, DP_BUS_TYPE_APB);
+ }
+
+ return retVal;
+}
+
+uint32_t DP_GetHpdStatusResponse(DP_PrivateData* pD, bool* status)
+{
+ uint32_t retVal;
+ uint8_t statusRead;
+ uint8_t headerMatching;
+
+ retVal = DP_GetHpdStatusResponseSF(pD, status);
+ if (CDN_EOK != retVal)
+ {
+ DbgMsg(DBG_GEN_MSG, DBG_CRIT,
+ "Function for receiving data containing response with HPD status"
+ " was called incorrectly. DPTX Mailbox may not be able to "
+ "operate any more.\n");
+ }
+
+ if (CDN_EOK == retVal)
+ {
+ messageReceive(pD, DP_BUS_TYPE_APB);
+ headerMatching = messageHeaderMatches(pD, MB_MODULE_ID_DP_TX, (uint8_t)DPTX_HPD_STATE);
+ if (0U == headerMatching) {
+ retVal = CDN_ENOEXEC;
+ }
+ }
+
+ if (CDN_EOK == retVal)
+ {
+ messageGetHeader(pD, NULL, NULL, NULL);
+ messageReadUint8(pD, &statusRead);
+
+ if (statusRead == 0U) {
+ *status = false;
+ } else {
+ *status = true;
+ }
+
+ }
+
+ return retVal;
+}
+
+uint32_t DP_GetHpdStatus(DP_PrivateData* pD, bool* status)
+{
+ uint32_t retVal;
+
+ retVal = DP_GetHpdStatusSF(pD, status);
+
+ if (CDN_EOK == retVal)
+ {
+ retVal = DP_SendHpdStatusRequest(pD);
+ }
+ if (CDN_EOK == retVal)
+ {
+ retVal = DP_GetHpdStatusResponse(pD, status);
+ }
+
+ return retVal;
+}
+
+uint32_t DP_SetDscConfig(DP_PrivateData* pD, uint8_t streamId, const DP_DscConfig* dscConfig)
+{
+ uint32_t retVal;
+ DP_DscConfigFull* currentDscConfig;
+
+ retVal = DP_SetDscConfigSF(pD, dscConfig);
+
+ if (CDN_EOK == retVal)
+ {
+ retVal = DP_StreamIdMstSstDscSanity(pD, streamId, dscConfig->splitPanel);
+ }
+
+ if (CDN_EOK == retVal)
+ {
+ currentDscConfig = &pD->dscConfig[streamId];
+ retVal = DscCopyCfgToFull(dscConfig, currentDscConfig);
+ }
+
+ if (CDN_EOK == retVal)
+ {
+ retVal = DscCalcParameters(currentDscConfig);
+ }
+
+ if (CDN_EOK == retVal)
+ {
+ retVal = DP_DscWriteConfiguration(pD, currentDscConfig, streamId);
+ }
+
+ if (CDN_EOK == retVal)
+ {
+ /* udpate DSC registers for seleted encoder */
+ retVal = DP_DscRegistersUpdate(pD, streamId);
+ }
+
+ if (CDN_EOK == retVal)
+ {
+ /* udpate DSC registers for encoder 1 */
+ if (dscConfig->splitPanel) {
+ retVal = DP_DscRegistersUpdate(pD, 1U);
+ }
+ }
+
+ return retVal;
+}
+
+uint32_t DP_GetDscConfig(DP_PrivateData* pD, uint8_t streamId, DP_DscConfig* dscConfig)
+{
+ uint32_t retVal;
+
+ retVal = DP_GetDscConfigSF(pD, dscConfig);
+
+ if (CDN_EOK == retVal)
+ {
+ retVal = DP_StreamIdMstSstDscSanity(pD, streamId, pD->dscConfig[0].splitPanel);
+ }
+
+ if (CDN_EOK == retVal)
+ {
+ retVal = DP_DscReadConfiguration(pD, &pD->dscConfig[streamId], streamId);
+ }
+
+ if (CDN_EOK == retVal)
+ {
+ DscCopyFromFull(dscConfig, &pD->dscConfig[streamId]);
+ }
+
+ return retVal;
+}
+
+uint32_t DP_DscSendPps(DP_PrivateData* pD, uint8_t streamId)
+{
+ uint32_t retVal;
+ const uint8_t packetType = 0x10U; /* PPS packet type*/
+ uint8_t pps[DP_DSC_PPS_SIZE + DP_SDP_HEADER_SIZE];
+ DP_SdpEntry sdpEntry;
+
+ retVal = DP_DscSendPpsSF(pD);
+
+ if (CDN_EOK == retVal) {
+ retVal = DP_StreamIdMstSstDscSanity(pD, streamId, pD->dscConfig[0].splitPanel);
+ }
+
+ if (CDN_EOK == retVal) {
+ DscWritePps(&pps[DP_SDP_HEADER_SIZE], &pD->dscConfig[streamId]);
+
+ /* fill pps header as defined in DP standard */
+ pps[0] = 0U; /* datat packet ID*/
+ pps[1] = packetType;
+ pps[2] = (uint8_t)DP_DSC_PPS_SIZE - 1U;
+ pps[3] = 0U; /* Reserved */
+
+ sdpEntry.packet = (uint32_t*)pps;
+ sdpEntry.type = packetType;
+ sdpEntry.length = (uint8_t)DP_DSC_PPS_SIZE + (uint8_t)DP_SDP_HEADER_SIZE;
+ sdpEntry.activeMode = DP_SDP_ACTIVE_VIDEO;
+
+ retVal = DP_SetSdp(pD, streamId, 0U, &sdpEntry);
+ }
+
+ return retVal;
+}
+
+uint32_t DP_SetCompressedStreamFlag(DP_PrivateData* pD, uint8_t streamId, bool val)
+{
+ uint32_t retVal;
+
+ DP_RegisterTransfer regTransfer = {0U};
+ const uint32_t DP_VBID_COMPRESSED_STREAM_FLAG = 1U << 6;
+
+ retVal = DP_SetCompressedStreamFlagSF(pD);
+
+ if (CDN_EOK == retVal)
+ {
+ retVal = DP_StreamIdMstSstDscSanity(pD, streamId, pD->dscConfig[0].splitPanel);
+ }
+
+ if (CDN_EOK == retVal)
+ {
+ regTransfer.addr = offsetof(MHDP_ApbRegs, mhdp_apb_regs.mhdp_dptx_stream[0].DP_VB_ID_p);
+ regTransfer.addr += streamId * (uint32_t)sizeof(pD->regBase->mhdp_apb_regs.mhdp_dptx_stream[0]);
+ retVal = DP_ReadRegister(pD, ®Transfer);
+ }
+
+ if (CDN_EOK == retVal)
+ {
+ if (val)
+ {
+ regTransfer.val |= DP_VBID_COMPRESSED_STREAM_FLAG;
+ } else {
+ regTransfer.val &= ~DP_VBID_COMPRESSED_STREAM_FLAG;
+ }
+
+ regTransfer.addr = offsetof(MHDP_ApbRegs, mhdp_apb_regs.mhdp_dptx_stream[0].DP_VB_ID_p);
+ regTransfer.addr += streamId * (uint32_t)sizeof(pD->regBase->mhdp_apb_regs.mhdp_dptx_stream[0]);
+ retVal = DP_WriteRegister(pD, ®Transfer);
+ }
+
+ return retVal;
+}
+
+uint32_t DP_DscReset(DP_PrivateData *pD)
+{
+ uint32_t retVal;
+
+ retVal = DP_DscResetSF(pD);
+
+ if (CDN_EOK == retVal) {
+ retVal = DP_DscSoftwareReset(pD);
+ } else {
+ DbgMsg(DBG_GEN_MSG, DBG_CRIT, "DSC reset failed\n");
+ }
+
+ return retVal;
+}
+
+uint32_t DP_SetWatchdogConfig(DP_PrivateData* pD, uint32_t watchdogMin,
+ uint32_t watchdogMax)
+{
+ uint32_t retVal;
+
+ retVal = DP_SetWatchdogConfigSF(pD);
+
+ if (CDN_EOK == retVal)
+ {
+ messageStart(pD, MB_MODULE_ID_GENERAL, (uint8_t)GENERAL_SET_WATCHDOG_CFG);
+ messageWriteUint32(pD, watchdogMin);
+ messageWriteUint32(pD, watchdogMax);
+ messageFinish(pD);
+ messageTransmit(pD, DP_BUS_TYPE_APB);
+ }
+
+ return retVal;
+}
+
+uint32_t DP_InjectEccError(DP_PrivateData* pD,
+ uint32_t errorMask,
+ DP_EccErrorMemType memType,
+ DP_EccErrorType errorType)
+{
+ uint32_t retVal;
+
+ retVal = DP_InjectEccErrorSF(pD, memType, errorType);
+
+ if (CDN_EOK == retVal)
+ {
+ messageStart(pD, MB_MODULE_ID_GENERAL, (uint8_t)GENERAL_INJECT_ECC_ERROR);
+ messageWriteUint32(pD, errorMask);
+ messageWriteUint8(pD, (uint8_t)memType);
+ messageWriteUint8(pD, (uint8_t)errorType);
+ messageFinish(pD);
+ messageTransmit(pD, DP_BUS_TYPE_APB);
+ }
+
+ return retVal;
+}
+
+uint32_t DP_ForceFatalError(DP_PrivateData* pD)
+{
+ uint32_t retVal;
+
+ retVal = DP_ForceFatalErrorSF(pD);
+
+ if (CDN_EOK == retVal)
+ {
+ messageStart(pD, MB_MODULE_ID_GENERAL, (uint8_t)GENERAL_FORCE_FATAL_ERROR);
+ messageFinish(pD);
+ messageTransmit(pD, DP_BUS_TYPE_APB);
+ }
+
+ return retVal;
+}
+
+uint32_t DP_SetFecEnable(DP_PrivateData* pD, bool fecEnable)
+{
+ uint32_t retVal;
+
+ retVal = checkIfCanSetFec(pD, fecEnable);
+
+ if (CDN_EOK == retVal) {
+ retVal = setFecEnable(pD, fecEnable);
+ }
+
+ if (retVal == CDN_EOK) {
+ retVal = waitFecStatus(pD, fecEnable);
+ }
+
+ if (CDN_EOK == retVal) {
+ pD->fecEnabled = fecEnable;
+ }
+
+ if (CDN_EAGAIN == retVal) {
+ retVal = CDN_EOK;
+ }
+
+ return retVal;
+}
+
+uint32_t DP_SetFecReady(DP_PrivateData* pD, bool enable)
+{
+ uint32_t retVal;
+
+ retVal = DP_SetFecReadySF(pD);
+
+ if (retVal == CDN_EOK) {
+ retVal = sinkSetFecReady(pD, enable);
+ }
+
+ if (retVal == CDN_EOK) {
+ retVal = sourceSetFecReady(pD, enable);
+ }
+
+ return retVal;
+}
+
+uint32_t DP_MstAllocateVcpi(DP_PrivateData *pD, uint8_t streamId, DP_SinkDevice *sinkDevice)
+{
+ uint32_t retVal;
+
+ retVal = DP_MstAllocateVcpiSF(pD, sinkDevice);
+
+ if (retVal == CDN_EOK) {
+ retVal = DP_StreamIdMstSanity(pD, streamId);
+ }
+
+ if (retVal == CDN_EOK) {
+ retVal = DP_MST_AllocateVcpi(pD, streamId, sinkDevice);
+ }
+
+ return retVal;
+}
+
+uint32_t DP_MstDeallocateVcpi(DP_PrivateData *pD, uint8_t streamId, DP_SinkDevice *sinkDevice)
+{
+ uint32_t retVal;
+
+ retVal = DP_MstDeallocateVcpiSF(pD, sinkDevice);
+
+ if (retVal == CDN_EOK) {
+ retVal = DP_StreamIdMstSanity(pD, streamId);
+ }
+
+ if (retVal == CDN_EOK) {
+ retVal = DP_MST_DeallocateVcpi(pD, streamId, sinkDevice);
+ }
+
+ return retVal;
+}
+
+uint32_t DP_MstEnable(DP_PrivateData* pD)
+{
+ uint32_t retVal;
+
+ retVal = DP_MstEnableSF(pD);
+
+ if (retVal == CDN_EOK) {
+ retVal = DP_MST_SetMstEnable(pD, true);
+ }
+
+ return retVal;
+}
+
+uint32_t DP_MstDisable(DP_PrivateData* pD)
+{
+ uint32_t retVal;
+
+ retVal = DP_MstDisableSF(pD);
+
+ if (retVal == CDN_EOK) {
+ retVal = DP_MST_SetMstEnable(pD, false);
+ }
+
+ return retVal;
+}
+
+uint32_t DP_MstStreamEnable(DP_PrivateData* pD, uint8_t streamId)
+{
+ uint32_t retVal;
+
+ retVal = DP_MstStreamEnableSF(pD);
+
+ if (retVal == CDN_EOK) {
+ retVal = DP_StreamIdMstSanity(pD, streamId);
+ }
+
+ if (retVal == CDN_EOK) {
+ retVal = DP_MST_SetStreamEnable(pD, streamId, true);
+ }
+
+ return retVal;
+}
+
+uint32_t DP_MstStreamDisable(DP_PrivateData* pD, uint8_t streamId)
+{
+ uint32_t retVal;
+
+ retVal = DP_MstStreamDisableSF(pD);
+
+ if (retVal == CDN_EOK) {
+ retVal = DP_StreamIdMstSanity(pD, streamId);
+ }
+
+ if (retVal == CDN_EOK) {
+ retVal = DP_MST_SetStreamEnable(pD, streamId, false);
+ }
+
+ return retVal;
+}
+
+uint32_t DP_SetAudioVideoClkCfg(DP_PrivateData* pD,
+ uint8_t streamId,
+ const DP_AudioVideoClkCfg* audioVideoClkCfg)
+{
+ uint32_t retVal;
+
+ retVal = DP_SetAudioVideoClkCfgSF(pD, streamId, audioVideoClkCfg);
+
+ if (retVal == CDN_EOK) {
+ retVal = DP_StreamIdMstSstSanity(pD, streamId);
+ }
+
+ if (retVal == CDN_EOK) {
+ retVal = setPktClock(pD, streamId, audioVideoClkCfg->pktDataClockEnable);
+ }
+ if (retVal == CDN_EOK) {
+ retVal = setAifClock(pD, streamId, audioVideoClkCfg->audioClockEnable);
+ }
+ if (retVal == CDN_EOK) {
+ retVal = setVifClock(pD, streamId, audioVideoClkCfg->videoClockEnable);
+ }
+
+ return retVal;
+}
+
+uint32_t DP_GetAudioVideoClkCfg(DP_PrivateData* pD,
+ uint8_t streamId,
+ DP_AudioVideoClkCfg* audioVideoClkCfg)
+{
+ uint32_t retVal;
+
+ retVal = DP_GetAudioVideoClkCfgSF(pD, streamId, audioVideoClkCfg);
+
+ if (retVal == CDN_EOK) {
+ retVal = DP_StreamIdMstSstSanity(pD, streamId);
+ }
+
+ if (retVal == CDN_EOK) {
+ retVal = getPktClock(pD, streamId, &audioVideoClkCfg->pktDataClockEnable);
+ }
+ if (retVal == CDN_EOK) {
+ retVal = getAifClock(pD, streamId, &audioVideoClkCfg->audioClockEnable);
+ }
+ if (retVal == CDN_EOK) {
+ retVal = getVifClock(pD, streamId, &audioVideoClkCfg->videoClockEnable);
+ }
+
+ return retVal;
+}
+
+uint32_t DP_GetHdcpClockConfig(DP_PrivateData* pD, bool *hdcpClockEnable)
+{
+ uint32_t retVal;
+ uint32_t clockEnabled;
+ uint32_t reg;
+ DP_RegisterTransfer regTransfer = {0U};
+
+ retVal = DP_GetHdcpClockConfigSF(pD, hdcpClockEnable);
+
+ if (retVal == CDN_EOK) {
+ regTransfer.addr = offsetof(MHDP_ApbRegs, mhdp_apb_regs.source_cipher_car_p);
+ retVal = DP_ReadRegister(pD, ®Transfer);
+ }
+
+ if (retVal == CDN_EOK) {
+ reg = regTransfer.val;
+ clockEnabled = CPS_FLD_READ(MHDP__MHDP_APB_REGS__SOURCE_CIPHER_CAR_P, SOURCE_CIPHER_CHAR_CLK_EN, reg);
+
+ if (clockEnabled == 0U) {
+ *hdcpClockEnable = false;
+ } else {
+ *hdcpClockEnable = true;
+ }
+ }
+
+ return retVal;
+}
+
+uint32_t DP_SetHdcpClockConfig(DP_PrivateData* pD, bool hdcpClockEnable)
+{
+ uint32_t retVal;
+ uint8_t clockEnable = (hdcpClockEnable) ? 1U : 0U;
+
+ retVal = DP_SetHdcpClockConfigSF(pD);
+
+ if (CDN_EOK == retVal) {
+ retVal = setCipherClockConfig(pD, clockEnable);
+ }
+
+ if (CDN_EOK == retVal) {
+ retVal = setCryptoClockConfig(pD, clockEnable);
+ }
+
+ return retVal;
+}
+
+uint32_t DP_MstGetSinkCount(DP_PrivateData *pD, uint8_t *sinkCount) {
+ MST_drm_dp_port* portList[DP_MAX_NUMBER_OF_STREAMS];
+ uint32_t retVal;
+
+ retVal = DP_MstGetSinkCountSF(pD, sinkCount);
+
+ if (retVal == CDN_EOK) {
+ *sinkCount = 0U;
+ retVal = collectSinkPortList(pD->mstTopMgr.mst_primary,
+ (const MST_drm_dp_port**) portList,
+ sinkCount);
+ }
+
+ if (retVal == CDN_EOK) {
+ removeDisconnectedSinks(pD, (const MST_drm_dp_port**) portList, *sinkCount);
+
+ retVal = updateConnectedSinks(pD, portList, *sinkCount);
+ }
+
+ return retVal;
+}
+
+uint32_t DP_MstGetSinkList(const DP_PrivateData *pD, const DP_SinkDevice** sinkList) {
+ uint32_t retVal;
+ uint8_t i;
+ uint8_t sinkNumber = 0U;
+
+ retVal = DP_MstGetSinkListSF(pD, sinkList);
+
+ if (retVal == CDN_EOK) {
+ for (i = 0U; i < DP_MAX_NUMBER_OF_STREAMS; i++) {
+ if (pD->sinkList[i].port != NULL) {
+ sinkList[sinkNumber] = &pD->sinkList[i];
+ sinkNumber++;
+ }
+ }
+ }
+
+ return retVal;
+}
+
+uint32_t DP_MstSetEncryption(DP_PrivateData* pD, uint8_t streamId, bool enable)
+{
+ uint32_t retVal;
+
+ retVal = DP_MstSetEncryptionSF(pD);
+
+ if (retVal == CDN_EOK) {
+ retVal = DP_MST_SetEncryption(pD, streamId, enable);
+ }
+
+ return retVal;
+}
+
+uint32_t DP_MstSetEncryptionEnable(DP_PrivateData* pD, bool enable)
+{
+ uint32_t retVal;
+ DP_RegisterTransfer regTransfer = {0U};
+
+ retVal = DP_MstSetEncryptionEnableSF(pD);
+
+ if (retVal == CDN_EOK) {
+ regTransfer.addr = offsetof(MHDP_ApbRegs, mhdp_apb_regs.DP_MTPH_ECF_SLOTS_31_0_p);
+ retVal = DP_ReadRegister(pD, ®Transfer);
+ }
+
+ if (retVal == CDN_EOK) {
+
+ if (enable) {
+ regTransfer.val |= 1U;
+ } else {
+ regTransfer.val &= ~1U;
+ }
+
+ retVal = DP_WriteRegister(pD, ®Transfer);
+ }
+
+ return retVal;
+}
+
+uint32_t DP_MstReadRemoteEdid(const DP_PrivateData* pD,
+ DP_SinkDevice * sinkDevice,
+ uint32_t block,
+ DP_ReadEdidResponse * edidResponse)
+{
+ uint32_t retVal;
+
+ retVal = DP_MstReadRemoteEdidSF(pD, sinkDevice, edidResponse);
+
+ if (retVal == CDN_EOK) {
+ retVal = drm_do_probe_ddc_edid(sinkDevice->port,
+ edidResponse->buff,
+ block,
+ edidResponse->size);
+ }
+
+ if (retVal == CDN_EOK) {
+ edidResponse->blockNo = (uint8_t)block;
+ }
+
+ return retVal;
+}
+
+uint32_t DP_MstScanTopology(DP_PrivateData* pD)
+{
+ uint32_t retVal;
+
+ retVal = DP_MstScanTopologySF(pD);
+
+ if (retVal == CDN_EOK) {
+ retVal = drm_dp_mst_link_probe_work(&pD->mstTopMgr);
+ }
+
+ return retVal;
+}
+
+uint32_t DP_MstHpdIrq(DP_PrivateData* pD)
+{
+ uint32_t retVal;
+
+ retVal = DP_MstHpdIrqSF(pD);
+
+ if (retVal == CDN_EOK) {
+ (void)drm_dp_mst_handle_hpd(&pD->mstTopMgr);
+ }
+
+ return retVal;
+}
+
+/* parasoft-end-suppress METRICS-36-3 */
+/* parasoft-end-suppress METRICS-41 */
diff --git a/packages/ti/drv/dss/src/csl/dp/src/dp_internal.h b/packages/ti/drv/dss/src/csl/dp/src/dp_internal.h
--- /dev/null
@@ -0,0 +1,102 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ *
+ * dp_internal.h
+ *
+ ******************************************************************************
+ */
+
+#ifndef DP_INERNAL_H
+#define DP_INERNAL_H
+
+#include "cdn_stdtypes.h"
+
+/**
+ * Prototypes of non-API functions used in multiple driver's files.
+ */
+
+uint16_t getSymbolRate(DP_LinkRate linkRate);
+
+float64_t calculateBitsPerComponent(const DP_PrivateData* pD, uint8_t streamId);
+
+/**
+ * General and DPTX command/response IDs
+ */
+
+typedef enum
+{
+ GENERAL_MAIN_CONTROL = 0x01,
+ GENERAL_TEST_ECHO = 0x02,
+ GENERAL_WRITE_REGISTER = 0x05,
+ GENERAL_WRITE_FIELD = 0x06,
+ GENERAL_READ_REGISTER = 0x07,
+ GENERAL_GET_HPD_STATE = 0x11,
+ GENERAL_WAIT = 0x08,
+ GENERAL_SET_WATCHDOG_CFG = 0x09,
+ GENERAL_INJECT_ECC_ERROR = 0x0A,
+ GENERAL_FORCE_FATAL_ERROR = 0x0B
+} GENERAL_MAILBOX_MSG_ID;
+
+typedef enum
+{
+ DPTX_SET_POWER_MNG = 0x00,
+ DPTX_GET_EDID = 0x02,
+ DPTX_READ_DPCD = 0x03,
+ DPTX_WRITE_DPCD = 0x04,
+ DPTX_ENABLE_EVENT = 0x05,
+ DPTX_READ_EVENT = 0x0A,
+ DPTX_GET_LAST_AUX_STAUS = 0x0E,
+ DPTX_HPD_STATE = 0x11,
+ DPTX_LT_ADJUST = 0x12,
+ DPTX_I2C_READ = 0x15,
+ DPTX_I2C_WRITE = 0x16,
+ DPTX_GET_LAST_I2C_STATUS = 0x17
+} DPTX_MAILBOX_MSG_ID;
+
+/* DisplayPort Configuration Data defines */
+/*****************************************************************************/
+/* FEC_CAPABILITY offset in DPCD */
+#define DP_DPCD_FEC_CAPABILITY 0x90U
+/* FEC capable mask */
+#define DP_DPCD_FEC_CAPABILITY_FEC_CAPABLE_MASK (1U << 0)
+/* FEC uncorrected block error count capable mask*/
+#define DP_DPCD_FEC_CAPABILITY_UBECC_MASK (1U << 1)
+/* FEC corrected block error count capable mask*/
+#define DP_DPCD_FEC_CAPABILITY_CBECC_MASK (1U << 2)
+/* FEC bit error count capable mask*/
+#define DP_DPCD_FEC_CAPABILITY_BECC_MASK (1U << 3)
+
+/* FEC_CAPABILITY offset in DPCD */
+#define DP_DPCD_FEC_CONFIGURATION 0x120U
+/* FEC_READY mask*/
+#define DP_DPCD_FEC_CONFIGURATION_FEC_READY (1U << 0)
+/*****************************************************************************/
+
+#endif /* DP_INERNAL_H */
diff --git a/packages/ti/drv/dss/src/csl/dp/src/dp_link_policy.c b/packages/ti/drv/dss/src/csl/dp/src/dp_link_policy.c
--- /dev/null
@@ -0,0 +1,2544 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ *
+ * dp_link_policy.c
+ *
+ ******************************************************************************
+ */
+
+/* parasoft-begin-suppress METRICS-36 "Function called from more than 5 different functions in one translation unit, DRV-3823" */
+
+#include "dp_if.h"
+#include "dp_structs_if.h"
+#include "dp_priv.h"
+#include "dp_sanity.h"
+
+#include "dp_sd0801_if.h"
+#include "dp_sd0801_structs_if.h"
+
+#include "dp_mailbox.h"
+#include "dp_register.h"
+#include "dp_link_policy.h"
+#include "dp_internal.h"
+
+#include "mhdp_apb_regs.h"
+#include "cps_drv.h"
+
+#include "cdn_errno.h"
+#include "cdn_stdtypes.h"
+#include "cdn_log.h"
+
+/**
+ * Status of last Clock Recovery (CR) or Channel Equalization (EQ) Link
+ * Training phase. For CR phase, there is one such value per lane. For EQ
+ * phase, there is one value for entire link.
+ */
+typedef enum
+{
+ /** Phase of Link Training succeeded. */
+ LT_PHASE_PASS = 0U,
+ /** Phase of Link Training failed. */
+ LT_PHASE_FAIL = 1U,
+} TrainingPhaseStatus;
+
+/**
+ * Contains detailed result of single step of Link Training (per lane, where
+ * applicable), taken from DPCD registers 0x202 - 0x204.
+ */
+typedef struct TrainingStepStatus_s
+{
+ /** Clock Recovery for given lane was successful (field LANEx_CR_DONE). */
+ uint8_t crDone[4];
+ /**
+ * Channel Equalization for given lane was successful (field
+ * LANEx_CHANNEL_EQ_DONE).
+ */
+ uint8_t eqDone[4];
+ /** Symbol Lock for given lane was achieved (field LANEx_SYMBOL_LOCKED). */
+ uint8_t symbolLocked[4];
+ /**
+ * Symbol boundaries of all the enabled lanes are aligned with one another
+ * (field INTERLANE_ALIGN_DONE)
+ */
+ uint8_t interlaneAligned;
+} TrainingStepStatus;
+
+/*
+ * Clear parameters of source device
+ * @param[in] caps pointer to source capabilities object
+ */
+void clearSourceCapabilities(DP_SourceDeviceCapabilities *caps)
+{
+ /* set default source parameters */
+ caps->maxLinkRate = DP_LINK_RATE_1_62;
+ caps->laneCount = 0U;
+ caps->ssc = false;
+ caps->scramblerDisable = false;
+
+ /* disable fast training and patterns */
+ caps->fastLinkTraining = false;
+ caps->tps3 = false;
+ caps->tps4 = false;
+ caps->maxVoltageSwing = 0U;
+ caps->maxPreemphasis = 0U;
+ caps->forceVoltageSwing = false;
+ caps->forcePreemphasis = false;
+ caps->laneMapping = DP_LANE_MAPPING_SINGLE_REGULAR;
+ caps->controllersPerPhy = DP_SINGLE_CONTROLLER;
+ caps->isEdp = false;
+}
+
+DP_SD0801_LinkRate toLinkRateSd(DP_LinkRate rate)
+{
+ /* 1:1 mapping */
+ /* From DP_LinkRate to DP_SD0801_LinkRate */
+ DP_SD0801_LinkRate ret;
+ switch (rate)
+ {
+ case DP_LINK_RATE_1_62:
+ /* 1.62 Gb/s */
+ ret = DP_SD0801_LINK_RATE_1_62;
+ break;
+ case DP_LINK_RATE_2_16:
+ /* 2.16 Gb/s */
+ ret = DP_SD0801_LINK_RATE_2_16;
+ break;
+ case DP_LINK_RATE_2_43:
+ /* 2.43 Gb/s */
+ ret = DP_SD0801_LINK_RATE_2_43;
+ break;
+ case DP_LINK_RATE_2_70:
+ /* 2.7 Gb/s */
+ ret = DP_SD0801_LINK_RATE_2_70;
+ break;
+ case DP_LINK_RATE_3_24:
+ /* 3.24 Gb/s */
+ ret = DP_SD0801_LINK_RATE_3_24;
+ break;
+ case DP_LINK_RATE_4_32:
+ /* 4.32 Gb/s */
+ ret = DP_SD0801_LINK_RATE_4_32;
+ break;
+ case DP_LINK_RATE_5_40:
+ /* 5.4 Gb/s */
+ ret = DP_SD0801_LINK_RATE_5_40;
+ break;
+ default:
+ ret = DP_SD0801_LINK_RATE_8_10;
+ break;
+ }
+ return ret;
+}
+
+static DP_LinkRate toLinkRateDp(DP_SD0801_LinkRate rate)
+{
+ /* 1:1 mapping */
+ /* From DP_SD0801_LinkRate to DP_LinkRate */
+ DP_LinkRate ret;
+ switch (rate)
+ {
+ case DP_SD0801_LINK_RATE_1_62:
+ /* 1.62 Gb/s */
+ ret = DP_LINK_RATE_1_62;
+ break;
+ case DP_SD0801_LINK_RATE_2_16:
+ /* 2.16 Gb/s */
+ ret = DP_LINK_RATE_2_16;
+ break;
+ case DP_SD0801_LINK_RATE_2_43:
+ /* 2.43 Gb/s */
+ ret = DP_LINK_RATE_2_43;
+ break;
+ case DP_SD0801_LINK_RATE_2_70:
+ /* 2.7 Gb/s */
+ ret = DP_LINK_RATE_2_70;
+ break;
+ case DP_SD0801_LINK_RATE_3_24:
+ /* 3.24 Gb/s */
+ ret = DP_LINK_RATE_3_24;
+ break;
+ case DP_SD0801_LINK_RATE_4_32:
+ /* 4.32 Gb/s */
+ ret = DP_LINK_RATE_4_32;
+ break;
+ case DP_SD0801_LINK_RATE_5_40:
+ /* 5.4 Gb/s */
+ ret = DP_LINK_RATE_5_40;
+ break;
+ default:
+ ret = DP_LINK_RATE_8_10;
+ break;
+ }
+ return ret;
+}
+
+/**
+ * Converts LinkState struct from DP driver's one to SD0801 driver's one.
+ */
+void toSdLinkState (const DP_LinkState* dpState, DP_SD0801_LinkState* sdState)
+{
+ uint8_t i;
+
+ /* Values for LinkRate are the same. */
+ sdState->linkRate = toLinkRateSd(dpState->linkRate);
+ sdState->laneCount = dpState->laneCount;
+ sdState->ssc = dpState->ssc;
+
+ for (i = 0; i < 4U; i++)
+ {
+ sdState->voltageSwing[i] = dpState->voltageSwing[i];
+ sdState->preEmphasis[i] = dpState->preEmphasis[i];
+ }
+}
+
+/*
+ * Clear parameters of sink device
+ * @param[in] caps pointer to sink capabilities object
+ */
+void clearSinkCapabilities(DP_SinkDeviceCapabilities *caps)
+{
+ uint8_t i;
+
+ /* set default sink parameters */
+ caps->maxLinkRate = DP_LINK_RATE_1_62;
+ caps->laneCount = 0U;
+ caps->ssc = false;
+
+ /* disable fast training and patterns */
+ caps->fastLinkTraining = false;
+ caps->tps3 = false;
+ caps->tps4 = false;
+ caps->enhanced = false;
+ caps->assr = false;
+ caps->linkBwSupported = false;
+ caps->TrainingInterval = 0U;
+ caps->linkRateSupported = false;
+ caps->edpRateCount = 0U;
+
+ /* clear for each link rate */
+ for (i = 0U; i < 8U; i++) {
+ caps->edpRatesRegisters[i] = 0U;
+ caps->ratesSupported[i] = false;
+ }
+}
+
+/**
+ * Initialize structure for link state to its default values. This does not
+ * impact PHY itself in any way.
+ */
+void clearLinkState(DP_LinkState* state)
+{
+ uint8_t i;
+ state->linkRate = DP_LINK_RATE_1_62;
+ state->laneCount = 0U;
+ state->ssc = false;
+
+ /* clear link state for each lane */
+ for (i = 0U; i < 4U; i++)
+ {
+ state->voltageSwing[i] = 0U;
+ state->preEmphasis[i] = 0U;
+ }
+}
+
+/**
+ * Get most recent version of linkState structure from PHY driver and put values
+ * into DP driver.
+ */
+uint32_t fetchLinkState(DP_PrivateData* pD)
+{
+ /* Temporary struct, for type conversion */
+ DP_SD0801_LinkState tmp;
+ uint8_t i;
+
+ uint32_t retVal = DP_SD0801_ReadLinkStat(pD->phyPd, &tmp);
+
+ if (CDN_EOK == retVal)
+ {
+ pD->linkState.linkRate = toLinkRateDp(tmp.linkRate);
+ pD->linkState.laneCount = tmp.laneCount;
+ pD->linkState.ssc = tmp.ssc;
+
+ for (i = 0; i < 4U; i++)
+ {
+ pD->linkState.voltageSwing[i] = tmp.voltageSwing[i];
+ pD->linkState.preEmphasis[i] = tmp.preEmphasis[i];
+ }
+ }
+ return retVal;
+}
+
+/*
+ * Clear training step status
+ * @param[in] status pointer to TrainingStepStatus object
+ */
+static void clearTrainingResult(TrainingStepStatus* status)
+{
+ uint8_t i;
+
+ /* clear for each lane */
+ for (i = 0U; i < 4U; i++) {
+ status->crDone[i] = 0U;
+ status->eqDone[i] = 0U;
+ status->symbolLocked[i] = 0U;
+ }
+
+ status->interlaneAligned = 0U;
+}
+
+/*
+ * Calculate interval time for training
+ * @param[in] dpcdReg value of dpcd register
+ */
+static uint32_t calcTrainingInterval(const uint8_t dpcdReg)
+{
+ uint32_t result;
+
+ uint8_t trainingIntervalValue = dpcdReg & DP_TRAINING_AUX_RD_INTERVAL_MASK;
+
+ if (trainingIntervalValue == 0x00U) {
+ /* set default time */
+ result = 400U;
+ } else {
+ result = (uint32_t)trainingIntervalValue * 4000U;
+ }
+
+ return result;
+}
+
+/*
+ * Set rate support
+ * @param[in] sinkCaps pointer to sink capabilities object
+ * @param[in] regNumber
+ */
+static void setRateSupport(DP_SinkDeviceCapabilities* sinkCaps, uint16_t edpRateRegister) {
+
+ sinkCaps->linkRateSupported = true;
+
+ switch (edpRateRegister)
+ {
+ case 8100U: /* RBR */
+ sinkCaps->ratesSupported[DP_LINK_RATE_1_62] = true;
+ break;
+ case 10800U: /* 2.16 Gb/s */
+ sinkCaps->ratesSupported[DP_LINK_RATE_2_16] = true;
+ break;
+ case 12150U: /* 2.43 Gb/s */
+ sinkCaps->ratesSupported[DP_LINK_RATE_2_43] = true;
+ break;
+ case 13500U: /* HBR */
+ sinkCaps->ratesSupported[DP_LINK_RATE_2_70] = true;
+ break;
+ case 16200U: /* 3.24 Gb/s */
+ sinkCaps->ratesSupported[DP_LINK_RATE_3_24] = true;
+ break;
+ case 21600U: /* 4.32 Gb/s */
+ sinkCaps->ratesSupported[DP_LINK_RATE_4_32] = true;
+ break;
+ case 27000U: /* HBR2 */
+ sinkCaps->ratesSupported[DP_LINK_RATE_5_40] = true;
+ break;
+ case 40500U: /* HBR3 */
+ sinkCaps->ratesSupported[DP_LINK_RATE_8_10] = true;
+ break;
+ default:
+ sinkCaps->linkRateSupported = true;
+ break;
+ }
+}
+
+/**
+ * Based on values in DPCD registers 10h - 1Fh, determine which rates are
+ * supported, and what are their indices.
+ * @param[in] pD pointer to driver's private data object
+ * @param[in] dpcdRegs pointer to DPCD registers
+ */
+static void fillEdpRates(DP_PrivateData* pD, const uint8_t* dpcdRegs)
+{
+ uint8_t i;
+ uint8_t index;
+ DP_SinkDeviceCapabilities* sinkCaps = &(pD->sinkCaps);
+
+ for (i = 0U; i < 8U; i++) {
+ /* Store value from 2 DPCD registers in a 16-bit one, to get its index later. */
+ index = 2U * i;
+ sinkCaps->edpRatesRegisters[i] = ((uint16_t)dpcdRegs[index + 1U] << 8) |
+ (uint16_t)dpcdRegs[index];
+
+ /* Stop on entry equal to 0. */
+ if (0U == sinkCaps->edpRatesRegisters[i]) {
+ break;
+ }
+
+ sinkCaps->edpRateCount++;
+ setRateSupport(sinkCaps, sinkCaps->edpRatesRegisters[i]);
+ }
+}
+
+/*
+ * Returns maximum lane count for connection
+ * @param[in] pD pointer to driver's private data object
+ * @return lane count value
+ */
+static uint8_t getMaxLaneCount(const DP_PrivateData* pD)
+{
+ uint8_t laneCount = pD->sinkCaps.laneCount;
+
+ if (pD->sourceCaps.laneCount < laneCount) {
+ laneCount = pD->sourceCaps.laneCount;
+ }
+
+ return laneCount;
+}
+
+/*
+ * Returns Spread-Spectrum clock support
+ * @param[in] pD pointer to driver's private data object
+ * @return true if SSC is supported
+ * @return false if SSC is not supported
+ */
+static bool getSscSupported(const DP_PrivateData* pD)
+{
+ bool ssc = false;
+
+ /* test if SSC is supported by both sides */
+ if ((pD->sourceCaps.ssc) && (pD->sinkCaps.ssc)) {
+ ssc = true;
+ }
+ return ssc;
+}
+
+/**
+ * Find out, which Training Pattern Sequence (TPS) is the highest one, supported
+ * by both Source and Sink device.
+ * @param[in] pD pointer to driver's private data object
+ * @return highest Common TPS value
+ */
+static uint8_t getHighestCommonTps(const DP_PrivateData* pD)
+{
+ uint8_t highest;
+
+ /* test if TPS for source are sink are same */
+ if (pD->sourceCaps.tps4 && pD->sinkCaps.tps4) {
+ highest = 4U;
+ } else if (pD->sourceCaps.tps3 && pD->sinkCaps.tps3) {
+ highest = 3U;
+ } else {
+ highest = 2U;
+ }
+
+ return highest;
+}
+
+/*
+ * Check support for fast training
+ * @param[in] pD pointer to driver's private data object
+ * @return true if fast training is supported
+ * @return false if fast training is supported
+ */
+static bool getFastTrainingSupported(const DP_PrivateData* pD)
+{
+ bool fastLinkTrainingSupport = false;
+
+ if ((pD->sourceCaps.fastLinkTraining) && (pD->sinkCaps.fastLinkTraining)) {
+ fastLinkTrainingSupport = true;
+ }
+
+ return fastLinkTrainingSupport;
+}
+
+/*
+ * Check if sink capabilities are correct
+ * @param[in] dpcpCaps pointer to DPCD params
+ * @return EOK if success
+ * @return ECANCELLED if DPCD params are incorrect
+ */
+static uint32_t verifySinkCapabilities(uint8_t dpcdCaps[16])
+{
+ uint32_t retVal = CDN_EOK;
+ const uint8_t laneCount = dpcdCaps[DP_MAX_LANE_COUNT_OFF] & DP_MAX_LANE_COUNT_MASK;
+
+ /* test if MAX_LINK_RATE is correct */
+ if ((dpcdCaps[DP_MAX_LINK_RATE_OFF] > 0x00U) && (dpcdCaps[DP_MAX_LINK_RATE_OFF] < 0x06U)) {
+ /* Unless this rate selection method is not supported, max link rate */
+ /* must be at least 1.62 Gb/s (RBR), represented by value 0x06. */
+ DbgMsg(DBG_GEN_MSG, DBG_CRIT, "Value in sink's MAX_LINK_RATE DPCD register is invalid.\n");
+ retVal = CDN_ECANCELED;
+ }
+
+ /* test if MAX_LANE_COUNT is correct */
+ if ((laneCount != 1U) && (laneCount != 2U) && (laneCount != 4U)) {
+ /* incorrect lane count */
+ DbgMsg(DBG_GEN_MSG, DBG_CRIT, "Value in sink's MAX_LANE_COUNT DPCD register is invalid.\n");
+ retVal = CDN_ECANCELED;
+ }
+
+ /* test if 8b/10b encoding is supported */
+ if ((dpcdCaps[DP_ML_CODING_OFF] & DP_CAPABLE_8B10B_MASK) == 0U) {
+ DbgMsg(DBG_GEN_MSG, DBG_WARN, "Sink doesn't indicate support for mandatory 8b/10b encoding.\n");
+ }
+
+ /* test if training interval is correct */
+ if ((dpcdCaps[DP_TRAINING_AUX_RD_INTERVAL_OFF] & DP_TRAINING_AUX_RD_INTERVAL_MASK) > 0x04U) {
+ DbgMsg(DBG_GEN_MSG, DBG_WARN, "Value of interval for reading training status is outside known range. "
+ "Driver will attempt to predict correct behaviour.\n");
+ }
+
+ return retVal;
+}
+
+/*
+ * Set maximium link rate for sink device
+ * @param[in] pD pointer to driver's private data object
+ * @param[in] maxLinkBw maximum link bandwidth
+ */
+static void setSinkMaxLinkRate(DP_SinkDeviceCapabilities* sinkCaps, const uint8_t maxLinkBw) {
+
+ bool* linkBwSupported = &(sinkCaps->linkBwSupported);
+ DP_LinkRate* maxLinkRate = &(sinkCaps->maxLinkRate);
+
+ *linkBwSupported = true;
+
+ /* set max link rate according to max link bandwidth */
+ switch (maxLinkBw) {
+ case 0x00:
+ *linkBwSupported = false;
+ break;
+ case 0x06:
+ *maxLinkRate = DP_LINK_RATE_1_62;
+ break;
+ case 0x0A:
+ *maxLinkRate = DP_LINK_RATE_2_70;
+ break;
+ case 0x14:
+ *maxLinkRate = DP_LINK_RATE_5_40;
+ break;
+ default:
+ /* Future versions of DP may define higher link rates. In such case, */
+ /* use 8.1 Gb/s */
+ *maxLinkRate = DP_LINK_RATE_8_10;
+ break;
+ }
+}
+
+/*
+ * Set support for "regular" DP rates
+ * @params[in] sinkCaps pointer to sink capabilities object
+ */
+static void setRegularDpRateSupport(DP_SinkDeviceCapabilities* sinkCaps) {
+
+ DP_LinkRate linkRate;
+ uint8_t supportedRatesNumber;
+ uint8_t i;
+ DP_LinkRate regularLinkRates[4] = {DP_LINK_RATE_1_62,
+ DP_LINK_RATE_2_70,
+ DP_LINK_RATE_5_40,
+ DP_LINK_RATE_8_10};
+
+ /* set number of supported links */
+ switch (sinkCaps->maxLinkRate)
+ {
+ case DP_LINK_RATE_8_10:
+ supportedRatesNumber = 4U;
+ break;
+
+ case DP_LINK_RATE_5_40:
+ supportedRatesNumber = 3U;
+ break;
+
+ case DP_LINK_RATE_2_70:
+ supportedRatesNumber = 2U;
+ break;
+
+ case DP_LINK_RATE_1_62:
+ supportedRatesNumber = 1U;
+ break;
+
+ default:
+ supportedRatesNumber = 0U;
+ break;
+ }
+
+ /* set 'ratesSupported' flags */
+ for (i = 0U; i < supportedRatesNumber; i++) {
+ linkRate = regularLinkRates[i];
+ sinkCaps->ratesSupported[linkRate] = true;
+ }
+}
+
+/*
+ * Write into sink capabilities object data from DPCD
+ * @param[in] sinkCaps pointer to sink capabilities object
+ * @param[in] transfer pointer to DPCD transfer object
+ */
+static void fillSinkCapabilities(DP_SinkDeviceCapabilities* sinkCaps, const DP_DpcdTransfer* transfer) {
+
+ sinkCaps->TrainingInterval = calcTrainingInterval(transfer->buff[DP_TRAINING_AUX_RD_INTERVAL_OFF]);
+
+ /* set max link rate */
+ uint8_t maxLinkBw = transfer->buff[DP_MAX_LINK_RATE_OFF];
+ setSinkMaxLinkRate(sinkCaps, maxLinkBw);
+
+ sinkCaps->laneCount = transfer->buff[DP_MAX_LANE_COUNT_OFF] & DP_MAX_LANE_COUNT_MASK;
+
+ /* set SSC supported */
+ sinkCaps->ssc = (0U != (transfer->buff[DP_MAX_DOWNSPREAD_OFF] & DP_MAX_DOWNSPREAD_MASK));
+
+ /* set TPS support */
+ sinkCaps->tps3 = (0U != (transfer->buff[DP_MAX_LANE_COUNT_OFF] & DP_TPS3_SUPPORTED_MASK));
+ sinkCaps->tps4 = (0U != (transfer->buff[DP_MAX_DOWNSPREAD_OFF] & DP_TPS4_SUPPORTED_MASK));
+
+ sinkCaps->fastLinkTraining = (0U != (transfer->buff[DP_MAX_DOWNSPREAD_OFF] & DP_NO_AUX_TRAINING_MASK));
+ sinkCaps->enhanced = (0U != (transfer->buff[DP_MAX_LANE_COUNT_OFF] & DP_ENHANCED_FRAME_CAP_MASK));
+ sinkCaps->assr = (0U != (transfer->buff[DP_EDP_CONF_CAP_OFF] & DP_ASSR_CAP_MASK));
+
+ setRegularDpRateSupport(sinkCaps);
+
+}
+/*
+ * Set parameters of DPCD transfer
+ * @param[in] transfer pointer to DPCD transfer object
+ * @param[in] address value of DPCD register address
+ * @param[in] size value of transfer size
+ * @param[in] buff pointer to data buffer
+ */
+static void setDpcdTransfer(DP_DpcdTransfer* transfer, uint32_t address, uint8_t size, uint8_t* buffer) {
+ transfer->addr = address;
+ transfer->size = size;
+ transfer->buff = buffer;
+}
+
+/**
+ * Performs a series of DPCD register reads, used to determine and
+ * store capabilities of sink device.
+ * @param[in] pD pointer to driver's private data object
+ */
+uint32_t readSinkCapabilities(DP_PrivateData* pD)
+{
+ uint32_t retVal = CDN_EOK;
+ DP_DpcdTransfer transfer;
+ uint8_t dpcdRespBuff[16];
+
+ DP_SinkDeviceCapabilities* sinkCaps = &(pD->sinkCaps);
+
+ clearSinkCapabilities(sinkCaps);
+
+ /* Read capabilities from DPCD registers starting at address 0h. */
+ setDpcdTransfer(&transfer, 0U, 16U, dpcdRespBuff);
+ retVal = DP_ReadDpcd(pD, &transfer);
+
+ if (CDN_EOK == retVal) {
+ /* Test for presence of Extended Receiver Capability at DPCD 2200h. */
+ /* If present, read it, and use for further capability reading. */
+ if (0U != (transfer.buff[DP_TRAINING_AUX_RD_INTERVAL_OFF] & DP_EXT_RECV_CAP_FIELD_PRESENT_MASK)) {
+ setDpcdTransfer(&transfer, 0x2200U, 16U, dpcdRespBuff);
+ retVal = DP_ReadDpcd(pD, &transfer);
+ }
+ }
+
+ if (CDN_EOK == retVal) {
+ retVal = verifySinkCapabilities(transfer.buff);
+ }
+
+ if (CDN_EOK == retVal) {
+ fillSinkCapabilities(sinkCaps, &transfer);
+
+ /* eDP 1.4 requires fast link training support from source device. */
+ if (sinkCaps->fastLinkTraining) {
+ /* Read supported link rates from DPCD 10h - 1Fh */
+ setDpcdTransfer(&transfer, 0x10U, 16U, dpcdRespBuff);
+ retVal = DP_ReadDpcd(pD, &transfer);
+ }
+ }
+
+ if (CDN_EOK == retVal) {
+ if (sinkCaps->fastLinkTraining) {
+ fillEdpRates(pD, transfer.buff);
+ }
+ pD->sinkCapsStored = 1U;
+ }
+
+ return retVal;
+}
+
+/**
+ * Return 1, if given link rate is specific to eDP. 0 otherwise.
+ * @param[in] rate rate value
+ * @return 1 if rate is specific to eDP
+ * @return 0 if not
+ */
+static uint8_t isEdpRate(DP_LinkRate rate)
+{
+ uint8_t result;
+
+ /* check if rate is specific to eDP */
+ switch (rate) {
+ case DP_LINK_RATE_2_16:
+ case DP_LINK_RATE_2_43:
+ case DP_LINK_RATE_3_24:
+ case DP_LINK_RATE_4_32:
+ result = 1U;
+ break;
+ default:
+ result = 0U;
+ break;
+ }
+
+ return result;
+}
+
+/*
+ * Return maximum available link rate
+ * @param[in] sourceRate maximum link rate for source
+ * @param[in] sinkRate maximum link rate for sink
+ * @return maximum available link
+ */
+static DP_LinkRate getMaxCommonRate(DP_LinkRate sourceRate, DP_LinkRate sinkRate)
+{
+ DP_LinkRate rate = sourceRate;
+
+ if (sinkRate < sourceRate) {
+ rate = sinkRate;
+ }
+
+ return rate;
+}
+
+/*
+ * Test if link rates are supported
+ * @param[in] pD pointer to DP private data object
+ * @return CDN_EOK if are supported
+ * @return CDN_ENOTSUP if not
+ */
+static uint32_t checkLinkRateSupport(const DP_PrivateData* pD)
+{
+ uint32_t retVal = CDN_ENOTSUP;
+
+ if ((!pD->sourceCaps.fastLinkTraining) &&
+ (0U != isEdpRate(pD->sourceCaps.maxLinkRate))) {
+ /* eDP link rate requested without supporting fast link training. */
+ /* Combination is not supported by driver. */
+ DbgMsg(DBG_GEN_MSG, DBG_CRIT, "Please enable fast training to use eDP link rates.\n");
+ } else if ((!pD->sinkCaps.linkBwSupported) && (!pD->sinkCaps.linkRateSupported)) {
+ DbgMsg(DBG_GEN_MSG, DBG_CRIT, "Sink doesn't seem to support any form of rate selection.\n");
+ } else if ((!pD->sinkCaps.fastLinkTraining) && (pD->sinkCaps.linkRateSupported)) {
+ /* If sink declares support for flexible link rates, it must adhere to eDP v1.4. */
+ /* Fast link training is required for sink device since eDP v1.2 */
+ DbgMsg(DBG_GEN_MSG, DBG_CRIT, "Sink violates eDP standard, by not supporting fast training\n");
+ } else {
+ retVal = CDN_EOK;
+ }
+
+ return retVal;
+}
+/**
+ * Based on source device capabilities set by client, and sink device
+ * capabilities read from DPCD, determine link rate to use, which also
+ * determines, link rate selection method in DPCD.
+ * @param[in] pD pointer to DP private data object
+ * @param[out] rate value of rate
+ * @return CDN_EOK, when acceptable link rate was found
+ * @return CDN_ENOTSUP, when acceptable link rate was not found.
+ */
+static uint32_t getMaxLinkRate(DP_PrivateData* pD, DP_LinkRate* rate)
+{
+ uint32_t retVal;
+ DP_SourceDeviceCapabilities* sourceCaps = &(pD->sourceCaps);
+ DP_SinkDeviceCapabilities* sinkCaps = &(pD->sinkCaps);
+
+ retVal = checkLinkRateSupport(pD);
+
+ if (CDN_EOK == retVal) {
+ /* Perform fast link training, if supported. */
+ if ((sourceCaps->fastLinkTraining) && (sinkCaps->fastLinkTraining)) {
+ /* Test if source maximum link rate is supported. If not, check if sink supports
+ * link rate.
+ */
+ if (sinkCaps->ratesSupported[sourceCaps->maxLinkRate]) {
+ *rate = sourceCaps->maxLinkRate;
+ retVal = CDN_EOK;
+ } else if (!(sinkCaps->linkRateSupported)) {
+ *rate = getMaxCommonRate(sourceCaps->maxLinkRate, sinkCaps->maxLinkRate);
+ retVal = CDN_EOK;
+ } else {
+ DbgMsg(DBG_GEN_MSG, DBG_CRIT, "Desired rate for fast training is not supported by sink.\n");
+ retVal = CDN_ENOTSUP;
+ }
+ } else if (sinkCaps->linkBwSupported) {
+ /* consider as regular DP device and find highest common rate, without fast training */
+ *rate = getMaxCommonRate(sourceCaps->maxLinkRate, sinkCaps->maxLinkRate);
+ retVal = CDN_EOK;
+ } else {
+ DbgMsg(DBG_GEN_MSG, DBG_CRIT, "Could not determine allowed link rate.\n");
+ retVal = CDN_ENOTSUP;
+ }
+ }
+
+ return retVal;
+}
+
+/**
+ * Step link rate down, according to regular DP 1.4.
+ * @param[in] linkRate current link rate value
+ * @return reduced link rate value
+ */
+static DP_LinkRate reduceLinkRate(DP_LinkRate linkRate)
+{
+ DP_LinkRate reduced;
+
+ /* Reduce link rate by one level */
+ switch (linkRate) {
+ case DP_LINK_RATE_8_10:
+ reduced = DP_LINK_RATE_5_40;
+ break;
+ case DP_LINK_RATE_5_40:
+ reduced = DP_LINK_RATE_2_70;
+ break;
+ case DP_LINK_RATE_2_70:
+ reduced = DP_LINK_RATE_1_62;
+ break;
+ default:
+ /* cannot reduce or link rate is unrecognized */
+ reduced = DP_LINK_RATE_1_62;
+ break;
+ }
+
+ return reduced;
+}
+
+/**
+ * Check, if lane count reduction during CR phase of link training is allowed as
+ * a fallback, when CR phase failed at RBR. If yes, calculate target lane count.
+ * Check, if CR phase passed only for lowest-numbered lanes.
+ * @param[in] pD pointer to DP private data object
+ * @param[in] status array with current status of training
+ * @param[out] target count reduced lane value
+ * @return 0, if no lane passed CR phase, or if there is a lane that passed CR,
+ * while any of lower-numbered ones did not.
+ * @return 1 otherwise and sets variable pointed by targetCount.
+ */
+static uint8_t checkLaneCountFallback(const DP_PrivateData* pD,
+ const TrainingPhaseStatus status[4],
+ uint8_t* targetCount)
+{
+ uint8_t result = 1U; /* fallback is allowed */
+ uint8_t reduced = 0U;
+ uint8_t i;
+ uint8_t zeroEncountered = 0U;
+
+ /* If only one lane was used, or even first lane didn't pass, return 0. */
+ if ((1U >= pD->linkState.laneCount) || (LT_PHASE_FAIL == status[0])) {
+ result = 0U;
+ }
+
+ if (1U == result) {
+ for (i = 0U; i < pD->linkState.laneCount; i++) {
+ if (LT_PHASE_PASS == status[i]) {
+ if (0U == zeroEncountered) {
+ reduced++;
+ } else {
+ result = 0U;
+ break;
+ }
+ } else {
+ zeroEncountered = 1U;
+ }
+ }
+ }
+
+ if (1U == result) {
+ /* if 3 first lanes passed, fall-back to 2. */
+ if (3U == reduced) {
+ reduced = 2U;
+ }
+ *targetCount = reduced;
+ }
+
+ return result;
+}
+
+/**
+ * Step lane count down, according to regular DP 1.4.
+ * @param[in] laneCount current lane count
+ * @return reduced lane count
+ */
+static uint8_t reduceLaneCount(uint8_t laneCount)
+{
+ uint8_t reduced;
+
+ /* Reduce lane count by one level */
+ switch (laneCount) {
+ case 4U:
+ reduced = 2U;
+ break;
+ case 2U:
+ reduced = 1U;
+ break;
+ default:
+ reduced = 1U;
+ break;
+ }
+ return reduced;
+}
+
+/*
+ * Reset configuration of PHY
+ * @param[in] pD pointer to DP private data object
+ * @return CDN_EOK if success
+ * @return CDN_EINVAL if cannot reset
+ */
+static uint32_t resetDigitalPhyConfig(DP_PrivateData* pD)
+{
+ uint32_t regTmp;
+ DP_RegisterTransfer regTransfer = {0U};
+
+ /* stop transmitting TPS */
+ regTmp = CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__DP_TX_PHY_CONFIG_REG_P, DP_TX_PHY_TRAINING_ENABLE, 0U, 0U) |
+ CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__DP_TX_PHY_CONFIG_REG_P, DP_TX_PHY_TRAINING_TYPE, 0U, 1U) |
+ CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__DP_TX_PHY_CONFIG_REG_P, DP_TX_PHY_SCRAMBLER_BYPASS, 0U, pD->sourceCaps.scramblerDisable ? 1U : 0U) |
+ CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__DP_TX_PHY_CONFIG_REG_P, DP_TX_PHY_ENCODER_BYPASS, 0U, 0U) |
+ COMMON_DPHY_CONFIG;
+
+ regTransfer.val = regTmp;
+ regTransfer.addr = offsetof(MHDP_ApbRegs, mhdp_apb_regs.DP_TX_PHY_CONFIG_REG_p);
+
+ return DP_WriteRegister(pD, ®Transfer);
+}
+
+/**
+ * Resets Voltage Swing and Pre-Emphaisis levels for lanes to '0', or to values
+ * requested in source capabilities.
+ * @param[in] pD pointer to DP private data object
+ * @param[in] laneCount count of lanes
+ */
+static void resetLaneSettings(DP_PrivateData* pD, uint8_t laneCount)
+{
+ uint8_t i;
+
+ /* reset lane setting for each lane */
+ for (i = 0U; i < laneCount; i++) {
+
+ if (!pD->sourceCaps.forceVoltageSwing) {
+ pD->linkState.voltageSwing[i] = 0U;
+ } else {
+ pD->linkState.voltageSwing[i] = pD->sourceCaps.maxVoltageSwing;
+ }
+
+ if (!pD->sourceCaps.forcePreemphasis) {
+ pD->linkState.preEmphasis[i] = 0U;
+ } else {
+ pD->linkState.preEmphasis[i] = pD->sourceCaps.maxPreemphasis;
+ }
+ }
+}
+
+/**
+ * Set Voltage Swing and Pre-emphasis levels as current ones, where applicable.
+ * @param[in] pD pointer to DP private data object
+ * @param[in] requestedLevels pointer to link state object
+ */
+static void adjustLaneSettings(DP_PrivateData* pD, const DP_LinkState* requestedLevels, uint8_t laneCount)
+{
+ uint8_t i;
+
+ /* adjust lane setting for each lane */
+ for (i = 0U; i < laneCount; i++) {
+
+ if (!pD->sourceCaps.forceVoltageSwing) {
+ pD->linkState.voltageSwing[i] = requestedLevels->voltageSwing[i];
+ }
+
+ if (!pD->sourceCaps.forcePreemphasis) {
+ pD->linkState.preEmphasis[i] = requestedLevels->preEmphasis[i];
+ }
+ }
+}
+
+/**
+ * Apply Voltage Swing and Pre-Emphasis levels for lanes.
+ * @param[in] pD pointer to DP private data object
+ * @param[in] laneCount count of lanes
+ */
+static uint32_t applyLaneSettings(DP_PrivateData* pD, uint8_t laneCount)
+{
+ uint8_t i;
+ uint32_t retVal = CDN_EOK;
+ DP_SD0801_LinkState sdState;
+ toSdLinkState(&(pD->linkState), &sdState);
+
+ for (i = 0U; i < laneCount; i++) {
+ if (CDN_EOK == retVal) {
+ /* Configure voltage swing and pre-emphasis for all enabled lanes. */
+ retVal = DP_SD0801_ConfigLane(pD->phyPd, i, &sdState);
+ }
+ }
+
+ return retVal;
+}
+
+/**
+ * Check, if voltage swing / pre-emphasis levels requested by sink device differ
+ * from ones currently set.
+ * @param[in] pD pointer to DP private data object
+ * @param[in] requestedLevels pointer to link state object
+ * @param[in] laneCount count of lanes
+ * @return 1 if there are differences
+ * @return 0 if no differences
+ */
+static uint8_t laneSetingsDiffer(const DP_PrivateData* pD,
+ const DP_LinkState* requestedLevels,
+ uint8_t laneCount)
+{
+ uint8_t i;
+ uint8_t retVal = 0U;
+
+ /* check for each available lane */
+ for (i = 0U; i < laneCount; i++) {
+ if (pD->linkState.voltageSwing[i] != requestedLevels->voltageSwing[i]) {
+ retVal = 1U;
+ }
+ if (pD->linkState.preEmphasis[i] != requestedLevels->preEmphasis[i]) {
+ retVal = 1U;
+ }
+ if (1U == retVal) {
+ break;
+ }
+ }
+
+ return retVal;
+}
+
+/**
+ * Checks, if there is a lane, that failed CR training while being set to
+ * highest Voltage Swing + Pre-emphasis value.
+ */
+static uint8_t maxSwingCheck(const DP_PrivateData* pD, const TrainingStepStatus *status, uint8_t laneCount)
+{
+ uint8_t i;
+ uint8_t retVal = 0U;
+
+ for (i = 0U; i < laneCount; i++) {
+ if (1U == status->crDone[i]) {
+ continue; /* lane passed training */
+ }
+ if ((pD->linkState.voltageSwing[i] + pD->linkState.preEmphasis[i]) >= 3U) {
+ /* at least one lane reached max allowed value. */
+ retVal = 1U;
+ break;
+ }
+ }
+ return retVal;
+}
+
+/**
+ * Check, if clock recovery for enabled lanes was reached or maintained.
+ * @param[in] status pointer to training step status object
+ * @param[in] laneCount number of lanes
+ * @return 1 if clock recovery reached
+ * @return 0 if clock recovery maintained
+ */
+static uint8_t trainingStepCrCheck(const TrainingStepStatus *status, uint8_t laneCount)
+{
+ uint8_t i;
+ uint8_t retVal = 1U;
+
+ /* check clock recovery for each lane */
+ for (i = 0U; i < laneCount; i++) {
+ if (1U != status->crDone[i]) {
+ retVal = 0U;
+ break;
+ }
+ }
+ return retVal;
+}
+
+/**
+ * Check, if channel equalization for enabled lanes was reached or maintained.
+ * @param[in] status pointer to training step status object
+ * @param[in] laneCount number of lanes
+ * @return 1 if channel equalization reached
+ * @return 0 if channel equalization maintained
+ */
+static uint8_t trainingStepEqCheck(const TrainingStepStatus *status, uint8_t laneCount)
+{
+ uint8_t i;
+ uint8_t retVal = 1U;
+
+ /* check channel equalization for each lane */
+ for (i = 0U; i < laneCount; i++) {
+
+ if (1U != status->crDone[i]) {
+ retVal = 0U;
+ } else if (1U != status->eqDone[i]) {
+ retVal = 0U;
+ } else if (1U != status->symbolLocked[i]) {
+ retVal = 0U;
+ } else {
+ continue;
+ }
+
+ break;
+ }
+
+ /* check if interlane aligned */
+ if (1U != status->interlaneAligned) {
+ retVal = 0U;
+ }
+
+ return retVal;
+}
+
+/**
+ * Check, if training for enabled lanes succeeded.
+ * @param[in] status pointer to training step status object
+ * @param[in] laneCount number of lanes
+ * @return 1 if success
+ * @return 0 if not success
+ */
+static uint8_t trainingPassCheck(const TrainingPhaseStatus *status, uint8_t laneCount)
+{
+ uint8_t i;
+ uint8_t retVal = 1U;
+
+ /* check for each lane */
+ for (i = 0U; i < laneCount; i++) {
+ if (LT_PHASE_PASS != status[i]) {
+ retVal = 0U;
+ break;
+ }
+ }
+
+ return retVal;
+}
+
+/*
+ * Write training pattern to DPCD
+ * @param[in] pD pointer to DP private data object
+ * @param[in] pattern value to write
+ * @return CDN_EOK if success
+ * @return CDN_EINVAL if cannot write
+ */
+static uint32_t writePatternToDpcd(DP_PrivateData* pD, uint8_t pattern)
+{
+ DP_DpcdTransfer transfer;
+ uint8_t dpcdWrBuff[4];
+
+ setDpcdTransfer(&transfer, 0x102U, 1U, dpcdWrBuff);
+
+ if (0U == pattern) {
+ transfer.buff[0] = 0U;
+ } else if (4U == pattern) {
+ transfer.buff[0] = 0x07;
+ } else {
+ /* disable scrambling for patterns 1-3 */
+ transfer.buff[0] = pattern | DP_SCRAMBLING_DISABLE_MASK;
+ }
+
+ return DP_WriteDpcd(pD, &transfer);
+}
+
+/**
+ * Selects Training Pattern Sequence to be transmitted by source
+ * device and informs sink about it using DPCD write.
+ * @param[in] pattern Training Pattern to be used (1 - 4). Value of '0' disables transmission
+ * of Training Pattern.
+ * @param[in] writeDpcd Whether or not to issue DPCD write transaction about pattern set.
+ * @return CDN_EOK if paterrn was set correctly
+ * @return CDN_EINVAL if pattern is out of range or cannot write pattern to DPCD
+ */
+static uint32_t setTrainingPattern(DP_PrivateData* pD, uint8_t pattern, uint8_t writeDpcd)
+{
+ uint32_t retVal = CDN_EOK;
+ uint32_t regTmp;
+ DP_RegisterTransfer regTransfer = {0U};
+
+ /* test if pattern is out of range */
+ if (4U < pattern) {
+ retVal = CDN_EINVAL;
+ }
+
+ if (CDN_EOK == retVal) {
+ if (0U != pattern) {
+ /* set training configuration */
+ regTmp = CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__DP_TX_PHY_CONFIG_REG_P, DP_TX_PHY_TRAINING_ENABLE, 0U, 1U) |
+ CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__DP_TX_PHY_CONFIG_REG_P, DP_TX_PHY_TRAINING_TYPE, 0U, pattern) |
+ CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__DP_TX_PHY_CONFIG_REG_P, DP_TX_PHY_SCRAMBLER_BYPASS, 0U, (pattern == 4U) ? 0U : 1U) |
+ CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__DP_TX_PHY_CONFIG_REG_P, DP_TX_PHY_ENCODER_BYPASS, 0U, 0U) |
+ COMMON_DPHY_CONFIG;
+
+ regTransfer.val = regTmp;
+ regTransfer.addr = offsetof(MHDP_ApbRegs, mhdp_apb_regs.DP_TX_PHY_CONFIG_REG_p);
+ retVal = DP_WriteRegister(pD, ®Transfer);
+ } else {
+ /* Stop transmitting TPS */
+ retVal = resetDigitalPhyConfig(pD);
+ }
+ }
+
+ if (CDN_EOK == retVal) {
+ if (0U != writeDpcd) {
+ /* write pattern to DPCD */
+ retVal = writePatternToDpcd(pD, pattern);
+ }
+ }
+
+ return retVal;
+}
+
+/**
+ * Configure value for 101h DPCD register.
+ * @param[in] pD pointer to DP private data object
+ * @param[in] pointer to buffer with data
+ */
+static void fillDpcd101h(const DP_PrivateData* pD, uint8_t* dpcdBuff)
+{
+ dpcdBuff[0] = (pD->linkState.laneCount) & DP_LANE_COUNT_SET_MASK;
+ if (pD->sinkCaps.enhanced) {
+ dpcdBuff[0] |= DP_ENHANCED_FRAME_EN_MASK;
+ }
+}
+
+/**
+ * Configure and transmit values for 100h and 101h DPCD registers:
+ * link rate, lane count and enhanced mode.
+ * @param[in] pD pointer to DP private data object
+ * @return CDN_EOK if success
+ * @return CDN_EINVAL if cannot write data to DPCD
+ */
+static uint32_t sendDpcd100h(DP_PrivateData* pD)
+{
+ uint8_t dpcdBuff[2];
+ DP_DpcdTransfer transfer;
+
+ /* Set buffer according to link rate */
+ switch (pD->linkState.linkRate) {
+ case DP_LINK_RATE_1_62:
+ dpcdBuff[0] = 0x06U;
+ break;
+ case DP_LINK_RATE_2_70:
+ dpcdBuff[0] = 0x0AU;
+ break;
+ case DP_LINK_RATE_5_40:
+ dpcdBuff[0] = 0x14U;
+ break;
+ case DP_LINK_RATE_8_10:
+ dpcdBuff[0] = 0x1EU;
+ break;
+ default:
+ dpcdBuff[0] = 0x00U;
+ break;
+ }
+
+ /* fill buffer with data */
+ fillDpcd101h(pD, &(dpcdBuff[1]));
+ setDpcdTransfer(&transfer, 0x100U, 2U, dpcdBuff);
+
+ return DP_WriteDpcd(pD, &transfer);
+}
+
+/**
+ * configure and transmit value for 101h DPCD register:
+ * lane count and enhanced mode.
+ */
+static uint32_t sendDpcd101h(DP_PrivateData* pD)
+{
+ uint8_t dpcdBuff[1];
+ DP_DpcdTransfer transfer;
+
+ fillDpcd101h(pD, &(dpcdBuff[0]));
+
+ setDpcdTransfer(&transfer, 0x101U, 1U, dpcdBuff);
+
+ return DP_WriteDpcd(pD, &transfer);
+}
+
+/*
+ * Set DPCD rate according to link rate
+ * @param[in] rate value of link rate
+ * @param[in] rateDpcd pointer to DPCD rate
+ * @return CDN_EOK if success
+ * @return CDN_EINVAL if rate is not supported
+ */
+static uint32_t getRateDpcd(const DP_LinkRate rate, uint32_t* rateDpcd) {
+
+ /* return CDN_EOK if link rate is supported */
+ uint32_t retVal = CDN_EOK;
+
+ /* designate rateDpcd depends to rate */
+ switch (rate)
+ {
+ /* each link rate have own rateDpcd value */
+ case DP_LINK_RATE_1_62:
+ *rateDpcd = 8100U;
+ break;
+ case DP_LINK_RATE_2_16:
+ *rateDpcd = 10800U;
+ break;
+ case DP_LINK_RATE_2_43:
+ *rateDpcd = 12150U;
+ break;
+ case DP_LINK_RATE_2_70:
+ *rateDpcd = 13500U;
+ break;
+ case DP_LINK_RATE_3_24:
+ *rateDpcd = 16200U;
+ break;
+ case DP_LINK_RATE_4_32:
+ *rateDpcd = 21600U;
+ break;
+ case DP_LINK_RATE_5_40:
+ *rateDpcd = 27000U;
+ break;
+ case DP_LINK_RATE_8_10:
+ *rateDpcd = 40500U;
+ break;
+ default:
+ /* link rate is unsupported */
+ retVal = CDN_EINVAL;
+ break;
+ }
+
+ return retVal;
+}
+
+/**
+ * Find, which 2-byte entry (taken from DPCD registers 0x10 - 0x1F) corresponds
+ * to desired link rate. Return value of 'CDN_ENOTSUP' means, that rate was not found.
+ * @param[in] pD pointer to DP private data object
+ * @param[in] rate rate value
+ * @param[out] idx index of link rate
+ * @return CDN_EOK if rate was found
+ * @retrun CDN_EINVAL if not found
+ */
+static uint32_t findLinkRateIndex(const DP_PrivateData* pD,
+ const DP_LinkRate rate,
+ uint8_t* idx)
+{
+ uint32_t rateDpcd;
+ uint32_t retVal = getRateDpcd(rate, &rateDpcd);
+ uint8_t i;
+
+ if (CDN_EOK == retVal) {
+ retVal = CDN_ENOTSUP;
+ /* test if rate is supported by device */
+ for (i = 0U; i < pD->sinkCaps.edpRateCount; i++) {
+ if (rateDpcd == pD->sinkCaps.edpRatesRegisters[i]) {
+ retVal = CDN_EOK;
+ *idx = i;
+ }
+ }
+ }
+
+ return retVal;
+}
+
+/**
+ * Configure and transmit value for 115h DPCD register:
+ * link rate, when using eDP-specific LINK_RATE_SET rate selection approach.
+ * @param[in] pD pointer to DP private data object
+ * @return CDN_EOK if success
+ * @return CDN_EINVAL if cannot find link rate or write data to DPCD
+ */
+static uint32_t sendDpcd115h(DP_PrivateData* pD)
+{
+ uint32_t retVal;
+ uint8_t dpcdBuff[1];
+ DP_DpcdTransfer transfer;
+
+ /* find index of link rate in eDP register */
+ retVal = findLinkRateIndex(pD, pD->linkState.linkRate, &(dpcdBuff[0]));
+
+ if (CDN_EOK == retVal) {
+ /* send data do DPCD register */
+ setDpcdTransfer(&transfer, 0x115U, 1U, dpcdBuff);
+ retVal = DP_WriteDpcd(pD, &transfer);
+ }
+
+ return retVal;
+}
+
+/*
+ * Get value of downspread
+ * @param[in] pD pointer to PDP private data object
+ * @return downspread value
+ */
+static uint8_t configureDownspread(const DP_PrivateData* pD) {
+
+ uint8_t retVal;
+
+ if (getSscSupported(pD)) {
+ retVal = DP_SPREAD_AMP_MASK;
+ } else {
+ retVal = 0U;
+ }
+
+ return retVal;
+}
+
+/**
+ * Performs initial Link Training operations, common to full and fast
+ * training. May be called once Source capabilities were set, and sink
+ * capabilities were read.
+ * @param[in] pD pointer to DP private data object
+ * @return CDN_EOK if success
+ */
+static uint32_t initTraining(DP_PrivateData* pD)
+{
+ uint32_t retVal = CDN_EOK;
+ uint8_t dpcdWrBuff[16];
+ DP_RegisterTransfer regTransfer = {0U};
+ DP_DpcdTransfer transfer;
+
+ /* Configure downspread and 8b/10 encoding */
+ setDpcdTransfer(&transfer, 0x107U, 2U, dpcdWrBuff);
+ transfer.buff[0] = configureDownspread(pD);
+ transfer.buff[1] = DP_SET_8B_10B_MASK;
+ retVal = DP_WriteDpcd(pD, &transfer);
+
+ if (CDN_EOK == retVal) {
+ /* Enable enhanced framing mode, if supported by Sink. */
+ if (pD->sinkCaps.enhanced) {
+ regTransfer.val = CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__DPTX_ENHNCD_P, DPTX_ENHANCED_MODE, 0U, 1U);
+ } else {
+ regTransfer.val = 0U;
+ }
+
+ regTransfer.addr = offsetof(MHDP_ApbRegs, mhdp_apb_regs.DPTX_ENHNCD_p);
+ retVal = DP_WriteRegister(pD, ®Transfer);
+ }
+
+ return retVal;
+}
+
+/*
+ * Enable software reset
+ * @param[in] pD pointer to DP private data object
+ * @return CDN_EOK if success
+ */
+static uint32_t resetRequest(DP_PrivateData* pD)
+{
+ DP_RegisterTransfer regTransfer = {0U};
+ uint32_t retVal;
+
+ /* set reset flag */
+ regTransfer.addr = offsetof(MHDP_ApbRegs, mhdp_apb_regs.DP_SW_RESET_p);
+ regTransfer.val = 1U;
+ retVal = DP_WriteRegister(pD, ®Transfer);
+
+ if (CDN_EOK == retVal) {
+ /* clean reset flag */
+ regTransfer.val = 0U;
+ retVal = DP_WriteRegister(pD, ®Transfer);
+ }
+
+ return retVal;
+}
+/**
+ * Performs operations done after Link Training.
+ * @param[in] pD pointer to DP private data object
+ * @param[in] writeDpcd whether or not to issue DPCD write transaction about
+ * pattern set.
+ * @return CDN_EOK if success
+ */
+static uint32_t cleanupTraining(DP_PrivateData* pD, uint8_t writeDpcd)
+{
+ uint32_t retVal;
+ DP_RegisterTransfer regTransfer = {0U};
+
+ /* request reset. */
+ retVal = resetRequest(pD);
+
+ if (CDN_EOK == retVal) {
+ retVal = setTrainingPattern(pD, 0U, writeDpcd);
+ }
+
+ /* read DP_FRAMER_GLOBAL_CONFIG */
+ if (CDN_EOK == retVal) {
+ regTransfer.addr = offsetof(MHDP_ApbRegs, mhdp_apb_regs.DP_FRAMER_GLOBAL_CONFIG_p);
+ retVal = DP_ReadRegister(pD, ®Transfer);
+ }
+
+ /* set lane count and WR_VHSYNC_FALL */
+ if (CDN_EOK == retVal) {
+ regTransfer.val = CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__DP_FRAMER_GLOBAL_CONFIG_P, NUM_LANES, regTransfer.val, (uint32_t)pD->linkState.laneCount - 1U);
+ regTransfer.val |= CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__DP_FRAMER_GLOBAL_CONFIG_P, WR_VHSYNC_FALL, regTransfer.val, 1U);
+ regTransfer.addr = offsetof(MHDP_ApbRegs, mhdp_apb_regs.DP_FRAMER_GLOBAL_CONFIG_p);
+ retVal = DP_WriteRegister(pD, ®Transfer);
+ }
+
+ return retVal;
+}
+
+/**
+ * Based on values read from DPCD registers, fills structure containing result
+ * of Link Training's phase.
+ * @param[in] dpcdBuff pointer to DPCD data buffer
+ * @oaram[out] status pointer to training status object
+ */
+static void parseLanesStatus(const uint8_t* dpcdBuff, TrainingStepStatus* status)
+{
+ uint8_t i;
+ uint8_t tmp;
+
+ for (i = 0U; i < 4U; i++) {
+ tmp = dpcdBuff[i / 2U]; /* 0 for lanes 0-1, 1 for lanes 2-3 */
+
+ if (0U != (i & 0x01U)) { /* odd-numbered lane - values on most significant nibble */
+ tmp = tmp >> DP_LANE_STATUS_ODD_LANE_SHIFT;
+ }
+
+ if (0U != (tmp & DP_LANE_CR_DONE_MASK))
+ {
+ status->crDone[i] = 1U;
+ }
+ if (0U != (tmp & DP_LANE_EQ_DONE_MASK)) {
+ status->eqDone[i] = 1U;
+ }
+
+ if (0U != (tmp & DP_LANE_SYMBOL_LOCKED_MASK)) {
+ status->symbolLocked[i] = 1U;
+ }
+ }
+
+ if (0U != (dpcdBuff[2] & DP_INTERLANE_ALIGN_DONE_MASK)) {
+ status->interlaneAligned = 1U;
+ }
+}
+
+/**
+ * Based on values read from DPCD registers, fills structure containing result
+ * of Link Training's phase.
+ * @param[in] pD pointer to DP private data object
+ * @param[in] dpcdBuffer pointer to DPCD buffer
+ * @param[out] status pointer to training status object
+ * @param[out] requestedAdjust pointer to link state object
+ */
+static void parseTrainingResult(const DP_PrivateData* pD,
+ const uint8_t* dpcdBuff,
+ TrainingStepStatus* status,
+ DP_LinkState* requestedAdjust)
+{
+ uint8_t i;
+ uint8_t tmp;
+
+ clearTrainingResult(status);
+
+ parseLanesStatus(dpcdBuff, status);
+
+ for (i = 0U; i < 4U; i++)
+ {
+ tmp = dpcdBuff[(i / 2U) + 4U]; /* 4 for lanes 0-1, 5 for lanes 2-3 */
+ if (0U != (i & 0x01U)) { /* odd-numbered lane */
+ tmp = tmp >> DP_LANE_STATUS_ODD_LANE_SHIFT;
+ }
+
+ requestedAdjust->voltageSwing[i] = tmp & DP_VOLTAGE_SWING_ADJ_MASK;
+ requestedAdjust->preEmphasis[i] = (tmp & DP_PREEEMPHASIS_ADJ_MASK) >> DP_PREEEMPHASIS_ADJ_SHIFT;
+
+ /* verify requested lane count and pre-emphasis, step-down if required. */
+ if (requestedAdjust->voltageSwing[i] > pD->sourceCaps.maxVoltageSwing) {
+ requestedAdjust->voltageSwing[i] = pD->sourceCaps.maxVoltageSwing;
+ }
+ if (requestedAdjust->preEmphasis[i] > pD->sourceCaps.maxPreemphasis) {
+ requestedAdjust->preEmphasis[i] = pD->sourceCaps.maxPreemphasis;
+ }
+
+ if ((requestedAdjust->voltageSwing[i] + requestedAdjust->preEmphasis[i]) > 3U) {
+ /* voltage swing level and pre-emphasis level combination is not allowed: */
+ /* leaving pre-emphasis as-is, and adjusting voltage swing. */
+ requestedAdjust->voltageSwing[i] = 3U - requestedAdjust->preEmphasis[i];
+ }
+ }
+}
+
+/**
+ * Based on current Voltage Swing and Pre-emphasis levels, construct values to
+ * write to DPCD registers (starting from address 103h) by uCPU.
+ * @param[in,out] pD pointer to DP private data object
+ * @param[out] dpcdBuff pointer to DPCP buffer
+ * @param[in] laneCount nubmer of lanes
+ */
+
+/* parasoft-begin-suppress MISRA2012-RULE-8_13_a "Pass pD parameter as const, DRV-3854" */
+static void configureDpcdLaneSettings(DP_PrivateData* pD,
+ uint8_t* dpcdBuff,
+ uint8_t laneCount)
+{
+ uint8_t i;
+ uint8_t* voltageSwing;
+ uint8_t* preEmphasis;
+
+ uint8_t maxVoltageSwing = pD->sourceCaps.maxVoltageSwing;
+ uint8_t maxPreemphasis = pD->sourceCaps.maxPreemphasis;
+
+ for (i = 0U; i < laneCount; i++)
+ {
+ voltageSwing = &pD->linkState.voltageSwing[i];
+ preEmphasis = &pD->linkState.preEmphasis[i];
+
+ /* first, validate max voltage swing and pre-emphasis and adjust, if needed. */
+ if (*voltageSwing > maxVoltageSwing) {
+ *voltageSwing = maxVoltageSwing;
+ }
+
+ if (*preEmphasis > maxPreemphasis) {
+ *preEmphasis = maxPreemphasis;
+ }
+
+ /* then, prepare data to be written to DPCD as a part of LT_ADJUST command. */
+ dpcdBuff[i] = *voltageSwing & DP_VOLTAGE_SWING_MASK;
+
+ if (*voltageSwing == maxVoltageSwing) {
+ dpcdBuff[i] |= DP_MAX_SWING_REACHED_MASK;
+ }
+
+ dpcdBuff[i] |= (*preEmphasis << DP_PREEMPHASIS_SET_SHIFT) & DP_PREEMPHASIS_SET_MASK;
+ if (*preEmphasis == maxPreemphasis) {
+ dpcdBuff[i] |= DP_MAX_PREEMPHASIS_REACHED_MASK;
+ }
+ }
+}
+/* parasoft-end-suppress MISRA2012-RULE-8_13_a */
+
+/**
+ * Send request for do link training step
+ * @param[in,out] pD pointer to DP private data object
+ * @param[in] laneCount Number of lanes used.
+ * @param[in] delay Minimum amount of time (in microseconds) to wait before reading result.
+ * Shall comply with value read from TRAINING_AUX_RD_INTERVAL DPCD
+ * register (0x00E).
+ *
+ */
+static void sendTrainingStepRequest(DP_PrivateData* pD,
+ uint8_t laneCount,
+ uint16_t delay)
+{
+ uint8_t dpcdBuff[4] = {0U};
+ configureDpcdLaneSettings(pD, dpcdBuff, laneCount);
+
+ /* send training request via Mailbox */
+ messageStart(pD, MB_MODULE_ID_DP_TX, (uint8_t)DPTX_LT_ADJUST);
+ messageWriteUint8(pD, laneCount);
+ messageWriteUint16(pD, delay);
+ messageWriteBuffer(pD, dpcdBuff, laneCount);
+ messageFinish(pD);
+ messageTransmit(pD, DP_BUS_TYPE_APB);
+
+}
+
+/**
+ * Performs single step of Full Link Training: writing current levels
+ * of Voltage Swing and Pre-Emphasis via DPCD, waiting for required
+ * amount of time (while training pattern is being transmitted) and
+ * reading back result of training step.
+ * @param[in] pD pointer to DP private data object
+ * @param[out] status Detailed result of Link Training step.
+ * @param[out] requestedAdjust Voltage swing and pre-emphasis level adjustments, required by sink,
+ * per lane.
+ * @return CDN_EOK if success
+ * @return CDN_EIO if incorrect length of DPCD response was received
+ */
+static uint32_t getTrainingStepResponse(DP_PrivateData* pD,
+ TrainingStepStatus* status,
+ DP_LinkState* requestedAdjust)
+{
+ uint32_t result = CDN_EOK;
+ uint8_t dpcdBuff[6];
+ uint16_t readSize;
+ uint32_t readAddr;
+
+ messageReceive(pD, DP_BUS_TYPE_APB);
+
+ /* check if header is equal expected */
+ if (0U == messageHeaderMatches(pD, MB_MODULE_ID_DP_TX, (uint8_t)DPTX_READ_DPCD)) {
+ result = CDN_ENOEXEC;
+ }
+
+ /* read buffer size */
+ if (result == CDN_EOK) {
+ messageGetHeader(pD, NULL, NULL, NULL);
+ messageReadUint16(pD, &readSize);
+ if (6U != readSize) {
+ result = CDN_EIO;
+ }
+ }
+
+ /* read address and buffer */
+ if (result == CDN_EOK) {
+ messageRead3Bytes(pD, &readAddr);
+ messageReadBuffer(pD, dpcdBuff, readSize);
+ parseTrainingResult(pD, dpcdBuff, status, requestedAdjust);
+ }
+
+ return result;
+}
+
+/**
+ * Performs single step of Full Link Training: writing current levels
+ * of Voltage Swing and Pre-Emphasis via DPCD, waiting for required
+ * amount of time (while training pattern is being transmitted) and
+ * reading back result of training step.
+ * @param[in] pD pointer to DP private data object
+ * @param[in] laneCount Number of lanes used.
+ * @param[in] delay Minimum amount of time (in microseconds) to wait before reading result.
+ * Shall comply with value read from TRAINING_AUX_RD_INTERVAL DPCD
+ * register (0x00E).
+ * @param[out] status Detailed result of Link Training step.
+ * @param[out] requestedAdjust Voltage swing and pre-emphasis level adjustments, required by sink,
+ * per lane.
+ * @return CDN_EOK if success
+ * @return CDN_EIO if incorrect length of DPCD response was received
+ */
+static uint32_t trainingSingleStep(DP_PrivateData* pD,
+ uint8_t laneCount,
+ uint16_t delay,
+ TrainingStepStatus* status,
+ DP_LinkState* requestedAdjust)
+{
+ uint32_t retVal = CDN_EOK;
+
+ /* check if parameters are valid */
+ if ((NULL == pD) || (NULL == status) || (NULL == requestedAdjust)) {
+ retVal = CDN_EINVAL;
+ }
+
+ if (CDN_EOK == retVal) {
+ /* send request and check response */
+ sendTrainingStepRequest(pD, laneCount, delay);
+ retVal = getTrainingStepResponse(pD, status, requestedAdjust);
+ }
+
+ return retVal;
+}
+
+/*
+ * Send via Mailbox request for delay
+ * @param[in,out] pD pointer to DP private data object
+ * @param[in] delay length of delay in microseconds
+ */
+static void sendWaitMessage(DP_PrivateData* pD, uint32_t delay)
+{
+ messageStart(pD, MB_MODULE_ID_GENERAL, (uint8_t)GENERAL_WAIT);
+ messageWriteUint32(pD, delay);
+ messageFinish(pD);
+ messageTransmit(pD, DP_BUS_TYPE_APB);
+}
+
+/**
+ * Perform delay on Xtensa.
+ * Sends GENERAL_WAIT Command via regular Mailbox. Response means, that at least
+ * specified time has passed. Completion of the delay is signified by response.
+ * @param[in,out] pD pointer to DP private data object
+ * @param[in] delay Amount of microseconds, that Xtensa shall wait before sending response.
+ * @return CDN_EOK if success
+ * @return CDN_ENOEXEC if header is not match expected
+ * @return CDN_EIO delay in response didn't match one requested
+ */
+static uint32_t waitOnUcpu(DP_PrivateData* pD, uint32_t delay)
+{
+ uint32_t retVal = CDN_EOK;
+ uint32_t resp;
+
+ /* send wait request */
+ sendWaitMessage(pD, delay);
+
+ messageReceive(pD, DP_BUS_TYPE_APB);
+ /* test if header matches */
+ if (0U == messageHeaderMatches(pD, MB_MODULE_ID_GENERAL, (uint8_t)GENERAL_WAIT)) {
+ retVal = CDN_ENOEXEC;
+ }
+
+ if (CDN_EOK == retVal) {
+ messageGetHeader(pD, NULL, NULL, NULL);
+ messageReadUint32(pD, &resp);
+ /* test if response is equal expected value */
+ if (resp != delay) {
+ retVal = CDN_EIO;
+ }
+ }
+
+ return retVal;
+}
+
+/*
+ * Adjust drive settings for link establish. Do single training steps and check it as long
+ * as max swing was reached, clock recovery was not passed 10 times or adjust is requested
+ * for 5 times in row.
+ * @param[in] pD pointer to DP private data object
+ * @param[in] laneCount number of lanes
+ * @param[out] stepStatus pointer to training step status object
+ * @return CDN_EOK if success
+ * @retrun CDN_EIO if single step was failed
+ */
+static uint32_t establishLinkCr(DP_PrivateData* pD,
+ uint8_t laneCount,
+ TrainingStepStatus* stepStatus) {
+ uint8_t isAdjustRequested = 0U;
+ uint8_t counterShort = 0U; /* retries with same voltage swing and pre-emphasis */
+ uint8_t counterLong = 0U; /* retries with same link rate and lane count */
+ uint8_t crDone = 0U;
+ uint8_t maxSwingReached = 0U;
+ DP_LinkState requestedAdjust;
+ uint32_t retVal = CDN_EOK;
+
+ while ((0U == crDone) && (counterShort < 5U) && (counterLong < 10U) && (0U == maxSwingReached)) {
+ /* Try to establish link by adjusting drive settings, as described in DP v1.4 */
+ if (0U != isAdjustRequested) {
+ DbgMsg(DBG_GEN_MSG, DBG_FYI, "Link Training: Voltage swing / pre-emphasis "
+ "adjust requested during CR phase.\n");
+ counterShort = 0U;
+ adjustLaneSettings(pD, &requestedAdjust, laneCount);
+ retVal = applyLaneSettings(pD, laneCount);
+ }
+
+ if (CDN_EOK == retVal) {
+ /* do single training step */
+ retVal = trainingSingleStep(pD,
+ laneCount,
+ DP_LINK_TRAINING_CR_DELAY_US,
+ stepStatus,
+ &requestedAdjust);
+ }
+ if (CDN_EOK != retVal) {
+ break;
+ }
+
+ /* check clock recovery */
+ crDone = trainingStepCrCheck(stepStatus, laneCount);
+
+ /* calculate max reached swing */
+ maxSwingReached = maxSwingCheck(pD, stepStatus, laneCount);
+
+ if (0U == crDone) {
+ DbgMsg(DBG_GEN_MSG, DBG_FYI, "Link Training: Not all CR_DONE bits set.\n");
+ counterLong++;
+ isAdjustRequested = laneSetingsDiffer(pD, &requestedAdjust, laneCount);
+ if (0U == isAdjustRequested) {
+ counterShort++;
+ }
+ }
+ }
+
+ return retVal;
+}
+/**
+ * Performs Full Link Training operations for Clock Recovery phase.
+ * @param[in] pD pointer to DP private data object
+ * @param[in] laneCount number of lanes
+ * @param[out] phaseStatus array with current trainig phase status for lanes
+ * @return CDN_EOK if success
+ * @return other code if cannot establish clock recovery or set training pattern
+ */
+static uint32_t fullTrainingCr(DP_PrivateData* pD,
+ uint8_t laneCount,
+ TrainingPhaseStatus phaseStatus[4])
+{
+ uint32_t retVal = CDN_EOK;
+ uint8_t i;
+ TrainingStepStatus stepStatus;
+
+ /* prepare lane settings */
+ resetLaneSettings(pD, laneCount);
+ retVal = applyLaneSettings(pD, laneCount);
+
+ if (CDN_EOK == retVal) {
+ /* send data to 100h DPCD register */
+ retVal = sendDpcd100h(pD);
+ }
+
+ if (CDN_EOK == retVal) {
+ /* set pattern for clock recovery phase */
+ retVal = setTrainingPattern(pD, 1U, 1U);
+ }
+
+ if (CDN_EOK == retVal) {
+ /* establish link */
+ retVal = establishLinkCr(pD, laneCount, &stepStatus);
+ }
+
+ if (CDN_EOK == retVal) {
+ /* set phase status for each lane */
+ for (i = 0U; i < laneCount; i++) {
+ if (0U != stepStatus.crDone[i]) {
+ phaseStatus[i] = LT_PHASE_PASS;
+ } else {
+ phaseStatus[i] = LT_PHASE_FAIL;
+ }
+ }
+ }
+
+ return retVal;
+}
+
+/*
+ * Adjust drive settings for link establish. Do single training steps and check it as long
+ * as max swing was reached, clock recovery was not passed 10 times or adjust is requested
+ * for 5 times in row.
+ * @param[in] pD pointer to DP private data object
+ * @param[in, out] crFailed clock recovery failed flag
+ * @param[out] eqDone status of equalization phase
+ * @param[in] laneCount number of lanes
+ * @return CDN_EOK if success
+ * @retrun CDN_EIO if single step was failed
+ */
+static uint32_t establishLinkEq(DP_PrivateData* pD, uint8_t* crFailed, uint8_t* eqDone, uint8_t laneCount)
+{
+ uint8_t isAdjustRequested = 0U;
+ uint8_t failCounter = 0U; /* retries with same voltage swing and pre-emphasis */
+ TrainingStepStatus stepStatus;
+ DP_LinkState requestedAdjust;
+ uint32_t retVal = CDN_EOK;
+
+ while ((0U == *crFailed) && (0U == *eqDone) && (failCounter < 5U)) {
+ /* Try to establish link by adjusting drive settings, as described in DP v1.4 */
+ if (0U != isAdjustRequested) {
+ DbgMsg(DBG_GEN_MSG, DBG_FYI, "Link Training: Voltage swing / pre-emphasis "
+ "adjust requested during EQ phase.\n");
+ adjustLaneSettings(pD, &requestedAdjust, laneCount);
+ retVal = applyLaneSettings(pD, laneCount);
+ }
+
+ if (CDN_EOK == retVal) {
+ /* do single training step */
+ retVal = trainingSingleStep(pD,
+ laneCount,
+ (uint16_t)pD->sinkCaps.TrainingInterval,
+ &stepStatus,
+ &requestedAdjust);
+ }
+ if (CDN_EOK != retVal) {
+ break;
+ }
+
+ if (0U == trainingStepCrCheck(&stepStatus, laneCount)) {
+ DbgMsg(DBG_GEN_MSG, DBG_FYI, "Link Training: CR_DONE no longer set during EQ phase.\n");
+ *crFailed = 1U;
+ } else {
+ *eqDone = trainingStepEqCheck(&stepStatus, laneCount);
+ if (0U == *eqDone)
+ {
+ DbgMsg(DBG_GEN_MSG, DBG_FYI, "Link Training: Not all bits, required for "
+ "successful EQ, were set.\n");
+ failCounter++;
+ isAdjustRequested = laneSetingsDiffer(pD, &requestedAdjust, laneCount);
+ }
+ }
+ }
+
+ return retVal;
+}
+/**
+ * Performs Full Link Training operations for Channel Equalization phase.
+ * @param[in] pD pointer to DP private datat object
+ * @param[in] laneCount nubmer of lanes
+ * @param[out] phaseStatus pointer to training phase status object
+ * @return CDN_EOK if success
+ * @return CDN_EIO if cannot establish for equalization or set training pattern
+ */
+static uint32_t fullTrainingEq(DP_PrivateData* pD,
+ uint8_t laneCount,
+ TrainingPhaseStatus* phaseStatus)
+{
+ uint32_t retVal = CDN_EOK;
+ uint8_t crFailed = 0U;
+ uint8_t eqDone = 0U;
+
+ /* set pattern */
+ retVal = setTrainingPattern(pD, getHighestCommonTps(pD), 1U);
+
+ if (CDN_EOK == retVal) {
+ /* establish link phase */
+ retVal = establishLinkEq(pD, &crFailed, &eqDone, laneCount);
+ }
+
+ if (CDN_EOK == retVal) {
+ /* set current phase status */
+ if ((0U != crFailed) || (0U == eqDone)) {
+ *phaseStatus = LT_PHASE_FAIL;
+ } else {
+ *phaseStatus = LT_PHASE_PASS;
+ }
+ }
+
+ return retVal;
+}
+
+/**
+ * Set both main link rate and lane count
+ */
+static uint32_t setPhyLink(DP_PrivateData* pD, DP_SD0801_LinkState* sdState)
+{
+ uint32_t retVal;
+
+ retVal = DP_SD0801_SetLinkRate(pD->phyPd, sdState);
+
+ if (CDN_EOK == retVal) {
+ /* Set lane count if setting link rate succeeds. */
+ retVal = DP_SD0801_EnableLanes(pD->phyPd, sdState);
+ }
+
+ return retVal;
+}
+
+/*
+ * Enable lanes and configure link state
+ * @param[in] pD pointer to DP private data object
+ * @return CDN_EOK if success
+ * @return CDN_ENOTSUP if lane count is greater than max
+ * @return other code if cannot enable lanes or stop transmitting TPS
+ */
+static uint32_t prepareFullTraining(DP_PrivateData* pD)
+{
+ DP_RegisterTransfer regTransfer = {0U};
+ uint8_t maxLaneCount;
+ uint32_t retVal;
+ DP_SD0801_LinkState sdState;
+
+ DbgMsg(DBG_GEN_MSG, DBG_FYI, "Full Link Training start.\n");
+
+ /* Stop transmitting TPS */
+ retVal = setTrainingPattern(pD, 0U, 1U);
+
+ if (CDN_EOK == retVal) {
+ /* enable lanes for DPTX */
+ maxLaneCount = getMaxLaneCount(pD);
+ if (32U > maxLaneCount) {
+ regTransfer.val = ((uint32_t)1U << maxLaneCount) - 1U;
+ regTransfer.addr = offsetof(MHDP_ApbRegs, mhdp_apb_regs.DPTX_LANE_EN_p);
+ retVal = DP_WriteRegister(pD, ®Transfer);
+ }
+ else {
+ retVal = CDN_ENOTSUP;
+ }
+ }
+
+ if (CDN_EOK == retVal) {
+
+ /* configure link state */
+ pD->linkState.laneCount = maxLaneCount;
+ pD->linkState.linkRate = getMaxCommonRate(
+ pD->sourceCaps.maxLinkRate,
+ pD->sinkCaps.maxLinkRate);
+ /* Use SSC, if enabled and supported by sink device. */
+ pD->linkState.ssc = getSscSupported(pD);
+ toSdLinkState(&(pD->linkState), &sdState);
+ retVal = setPhyLink(pD, &sdState);
+ }
+
+ return retVal;
+}
+
+/*
+ * Reduce link rate if not minimal or reduce lane count when possible for
+ * clock recovery phase
+ * @param[in, out] pointer to DP private data object
+ * @param[in,out] lanesPassed number of passed lanes
+ * @param[in] phaseStatus pointer to phase status object
+ * @param[in,out] result pointer to current training status
+ * @return CDN_EOK if fixing success or was failed
+ * @return other code if cannot stop TPS transmiting
+ */
+static uint32_t fixPhaseCr(DP_PrivateData* pD,
+ uint8_t* lanesPassed,
+ const TrainingPhaseStatus* phaseStatus,
+ DP_TrainingStatus* result) {
+
+ uint32_t retVal = CDN_EOK;
+ DP_SD0801_LinkState sdState;
+
+ if (DP_LINK_RATE_1_62 != pD->linkState.linkRate) {
+ retVal = setTrainingPattern(pD, 0U, 1U);
+
+ if (CDN_EOK == retVal) {
+ /* Fallback: Reduce link rate, when possible. */
+ pD->linkState.linkRate = reduceLinkRate(pD->linkState.linkRate);
+ toSdLinkState(&(pD->linkState), &sdState);
+ DbgMsg(DBG_GEN_MSG, DBG_FYI, "Link Training: Reducing Link Rate during CR phase.\n");
+ retVal = DP_SD0801_SetLinkRate(pD->phyPd, &sdState);
+ }
+
+ } else if (0U != checkLaneCountFallback(pD, phaseStatus, lanesPassed)) {
+ /* Fallback: Reduce lane count, when possible and allowed. */
+ pD->linkState.laneCount = *lanesPassed;
+ /* restore link rate */
+ pD->linkState.linkRate = getMaxCommonRate(
+ pD->sourceCaps.maxLinkRate,
+ pD->sinkCaps.maxLinkRate);
+ toSdLinkState(&(pD->linkState), &sdState);
+ DbgMsg(DBG_GEN_MSG, DBG_FYI, "Link Training: Reducing Lane Count during CR phase.\n");
+ retVal = DP_SD0801_SetLinkRate(pD->phyPd, &sdState);
+ if (CDN_EOK == retVal) {
+ retVal = DP_SD0801_EnableLanes(pD->phyPd, &sdState);
+ }
+ } else {
+ /* Clock Recovery (CR) failed. */
+ *result = DP_LT_CR_FAIL;
+ }
+
+ return retVal;
+}
+
+/*
+ * Reduce lane count if greater than 1 or reduce link rate when possible for
+ * equalization phase
+ * @param[in, out] pointer to DP private data object
+ * @param[in,out] lanesPassed number of passed lanes
+ * @param[in] phaseStatus pointer to phase status object
+ * @param[in,out] result pointer to current training status
+ * @return CDN_EOK if fixing success or was failed
+ * @return other code if cannot stop TPS transmiting
+ */
+static uint32_t fixPhaseEq(DP_PrivateData* pD, DP_TrainingStatus* result) {
+
+ uint32_t retVal = CDN_EOK;
+ DP_SD0801_LinkState sdState;
+
+ if (1U < pD->linkState.laneCount) {
+ /* reduce lane count for device, when possible */
+ pD->linkState.laneCount = reduceLaneCount(pD->linkState.laneCount);
+ toSdLinkState(&(pD->linkState), &sdState);
+ DbgMsg(DBG_GEN_MSG, DBG_FYI, "Link Training: Reducing Lane Count during EQ phase.\n");
+ retVal = DP_SD0801_EnableLanes(pD->phyPd, &sdState);
+ } else if (DP_LINK_RATE_1_62 != pD->linkState.linkRate) {
+ retVal = setTrainingPattern(pD, 0U, 1U);
+ if (CDN_EOK == retVal) {
+ /* reduce link rate for device, when possible */
+ pD->linkState.linkRate = reduceLinkRate(pD->linkState.linkRate);
+ /* restore lane count */
+ pD->linkState.laneCount = getMaxLaneCount(pD);
+ toSdLinkState(&(pD->linkState), &sdState);
+ DbgMsg(DBG_GEN_MSG, DBG_FYI, "Link Training: Reducing Link Rate during EQ phase.\n");
+ retVal = DP_SD0801_SetLinkRate(pD->phyPd, &sdState);
+ }
+ if (CDN_EOK == retVal) {
+ retVal = DP_SD0801_EnableLanes(pD->phyPd, &sdState);
+ }
+ } else {
+ *result = DP_LT_EQ_FAIL;
+ }
+
+ return retVal;
+}
+
+/*
+ * Execute training for clock recovery phase
+ * @param[in,out] pD pointer to DP private data object
+ * @param[in,out] result current result of training phase
+ * @return CDN_EOK if success or cannot reduce link rate/lane count
+ * @return other error code if phase was not executed properly
+ */
+static uint32_t executeCrTrainingPhase(DP_PrivateData* pD, DP_TrainingStatus* result, uint8_t* crDone)
+{
+ uint32_t retVal;
+ TrainingPhaseStatus phaseStatus[4];
+ uint8_t lanesPassed;
+
+ /* do full trainig for clock recovery phase */
+ retVal = fullTrainingCr(pD, pD->linkState.laneCount, phaseStatus);
+
+ if (CDN_EOK == retVal) {
+ /* check if training passed */
+ *crDone = trainingPassCheck(phaseStatus, pD->linkState.laneCount);
+ if (0U == *crDone) {
+ retVal = fixPhaseCr(pD, &lanesPassed, phaseStatus, result);
+ }
+ }
+
+ return retVal;
+}
+
+/*
+ * Execute training for equalization phase
+ * @param[in,out] pD pointer to DP private data object
+ * @param[in,out] result current result of training phase
+ * @return CDN_EOK if success or cannot reduce link rate/lane count
+ * @return other error code if phase was not executed properly
+ */
+static uint32_t executeEqTrainingPhase(DP_PrivateData* pD, DP_TrainingStatus* result, uint8_t* eqDone)
+{
+ TrainingPhaseStatus phaseStatus[4];
+ uint32_t retVal;
+
+ retVal = fullTrainingEq(pD, pD->linkState.laneCount, phaseStatus);
+
+ if (retVal == CDN_EOK) {
+ /* Check only first value, as it applies to all lanes during EQ phase */
+ *eqDone = trainingPassCheck(phaseStatus, 1U);
+ if (0U == *eqDone) {
+ retVal = fixPhaseEq(pD, result);
+ }
+ }
+
+ return retVal;
+}
+
+/*
+ * Execute full training
+ * @param[in,out] pD pointer to DP private data object
+ * @param[in,out] result current result of training phase
+ * @return CDN_EOK if success or cannot reduce link rate/lane count
+ * @return other error code if training was not executed properly
+ */
+static uint32_t executeFullTraining(DP_PrivateData* pD, DP_TrainingStatus* result)
+{
+ uint32_t retVal;
+ uint8_t eqDone = 0U;
+ uint8_t crDone = 0U;
+
+ *result = DP_LT_OK;
+
+ while (DP_LT_OK == *result)
+ {
+ /* Perform CR training phase. */
+ retVal = executeCrTrainingPhase(pD, result, &crDone);
+
+ if ((CDN_EOK == retVal) && (DP_LT_OK == *result)) {
+ if (0U == crDone) {
+ /* Reducing was passed, try again */
+ continue;
+ }
+ /* If this point is reached, CR phase has passed. */
+ DbgMsg(DBG_GEN_MSG, DBG_FYI, "Link Training: CR phase done.\n");
+ retVal = executeEqTrainingPhase(pD, result, &eqDone);
+ }
+
+ /* Need not check result, because if eqDone is 1U, it means that */
+ /* executeEqTraining was executed and not change value of result, */
+ /* so it is DP_LT_OK (previous if checked it) */
+ if ((CDN_EOK == retVal) && (0U != eqDone)) {
+ /* If this point is reached, EQ phase has passed */
+ break;
+ }
+
+ if (CDN_EOK != retVal) {
+ /* Something going wrong. If retVal is CDN_EOK, but result is not DP_LT_OK loop */
+ /* will break by 'while' statement */
+ *result = DP_LT_UNFINISHED;
+ }
+ }
+
+ if ((CDN_EOK == retVal) && (DP_LT_OK == *result)) {
+ DbgMsg(DBG_GEN_MSG, DBG_FYI, "Link Training: Full Training finished.\n");
+ }
+
+ return retVal;
+}
+/**
+ * Performs Full Link Training operations. May be called after calling
+ * DP_InitTraining.
+ * @param[in,out] pD pointer to DP private data object
+ * @param[in,out] result pointer to training status object
+ * @return CDN_EOK if success
+ * @return CDN_ENOTSUP if sink doesn't support link method
+ * @return other code if training was not executed correctly
+ */
+static uint32_t fullTraining(DP_PrivateData* pD, DP_TrainingStatus* result)
+{
+ uint32_t retVal;
+ *result = DP_LT_OK;
+
+ /* test if link method is supported by sink */
+ if (0U == pD->sinkCaps.linkBwSupported) {
+ DbgMsg(DBG_GEN_MSG, DBG_CRIT, "Full training was requested, while sink device"
+ "doesn't support LINK_BW_SET method.\n");
+ retVal = CDN_ENOTSUP;
+ } else {
+ /* do full link training */
+ retVal = prepareFullTraining(pD);
+ if (CDN_EOK == retVal) {
+ retVal = executeFullTraining(pD, result);
+ }
+ (void)cleanupTraining(pD, 1U);
+ }
+
+ return retVal;
+}
+
+/* Transmit patterns for fast training
+ * @param[in,out] pD pointer to DP private data object
+ * @return CDN_EOK if success
+ * @return other code when cannot set training pattern or uCOU waits
+ * different time than expected
+ */
+static uint32_t fastTrainingTransmitPatterns(DP_PrivateData* pD)
+{
+ uint32_t retVal;
+
+ /* Transmit TPS1 for 500 us */
+ retVal = setTrainingPattern(pD, 1U, 0U);
+ if (CDN_EOK == retVal) {
+ retVal = waitOnUcpu(pD, 500U);
+ }
+
+ /* Transmit TPSx (2-4) for 500 us */
+ if (CDN_EOK == retVal) {
+ retVal = setTrainingPattern(pD, getHighestCommonTps(pD), 0U);
+ }
+
+ if (CDN_EOK == retVal) {
+ retVal = waitOnUcpu(pD, 500U);
+ }
+
+ return retVal;
+}
+
+/*
+ * Send display port configuration data
+ * @param[in] pD pointer to DP private data object
+ * @param[in] maxRate maximum rate
+ * @return CDN_EOK if success
+ * @return CDN_EIVAL if cannot send
+ */
+static uint32_t sendDpcd(DP_PrivateData* pD, DP_LinkRate maxRate) {
+
+ uint32_t retVal = CDN_EOK;
+
+ if ((0U == isEdpRate(maxRate)) &&
+ (0U != pD->sinkCaps.linkBwSupported) &&
+ (maxRate <= pD->sourceCaps.maxLinkRate))
+ {
+ /* use LINK_BW_SET DPCD approach */
+ retVal = sendDpcd100h(pD);
+ } else {
+ /* use LINK_RATE_SET approach. */
+ retVal = sendDpcd101h(pD);
+ if (CDN_EOK == retVal) {
+ retVal = sendDpcd115h(pD);
+ }
+ }
+
+ return retVal;
+}
+
+/*
+ * Prepare device for fast training
+ * @param[in] pD pointer to driver's private data object
+ * @param[in] linkRate pointer to link rate object
+ * @return CDN_EOK if success
+ * @return CDN_EINVAL if transfer parameters not vailid
+ */
+static uint32_t prepareFastTraining(DP_PrivateData* pD, DP_LinkRate* linkRate)
+{
+ DP_RegisterTransfer regTransfer = {0U};
+ uint32_t retVal = getMaxLinkRate(pD, linkRate);
+ DP_SD0801_LinkState sdState;
+
+ if (CDN_EOK == retVal) {
+ DbgMsg(DBG_GEN_MSG, DBG_FYI, "Fast Link Training start.\n");
+ uint8_t maxLaneCount = getMaxLaneCount(pD);
+
+ pD->linkState.laneCount = maxLaneCount;
+ pD->linkState.linkRate = *linkRate;
+ /* Use SSC, if enabled and supported by sink device. */
+ pD->linkState.ssc = getSscSupported(pD);
+
+ if (32U > maxLaneCount) {
+ /* enable lanes */
+ uint8_t value = (1U << maxLaneCount) - 1U;
+ regTransfer.val = (uint32_t)value;
+ regTransfer.addr = offsetof(MHDP_ApbRegs, mhdp_apb_regs.DPTX_LANE_EN_p);
+ retVal = DP_WriteRegister(pD, ®Transfer);
+ }
+ if (CDN_EOK == retVal)
+ {
+ /* configure phy for training */
+ toSdLinkState(&(pD->linkState), &sdState);
+ retVal = DP_SD0801_SetLinkRate(pD->phyPd, &sdState);
+ }
+ if (CDN_EOK == retVal)
+ {
+ retVal = DP_SD0801_EnableLanes(pD->phyPd, &sdState);
+ }
+ }
+
+ return retVal;
+
+}
+
+/*
+ * Execute fast training
+ * @param[in,out] pD pointer to DP private data object
+ * @return CDN_EOK if success
+ * @return other code if not success
+ */
+static uint32_t fastTraining(DP_PrivateData* pD)
+{
+ DP_LinkRate maxRate;
+ uint32_t retVal = prepareFastTraining(pD, &maxRate);
+
+ if (CDN_EOK == retVal) {
+
+ /* Set voltage swing and pre-emphasis levels to '0', or to ones forced. */
+ resetLaneSettings(pD, pD->linkState.laneCount);
+ retVal = applyLaneSettings(pD, pD->linkState.laneCount);
+
+ if (CDN_EOK == retVal)
+ {
+ retVal = sendDpcd(pD, maxRate);
+ }
+
+ if (CDN_EOK == retVal) {
+ /* transmit pattern for fast training */
+ retVal = fastTrainingTransmitPatterns(pD);
+
+ (void)cleanupTraining(pD, 0U);
+ DbgMsg(DBG_GEN_MSG, DBG_FYI, "Fast Link Training finished.\n");
+ }
+ }
+
+ return retVal;
+}
+
+uint32_t DP_SetSourceCapabilities(DP_PrivateData* pD, const DP_SourceDeviceCapabilities* caps)
+{
+ uint32_t retVal = DP_SetSourceCapabilitiesSF(pD, caps);
+
+ if (CDN_EOK == retVal) {
+ /* write source capabilities into driver's private data */
+ CPS_BufferCopy((uint8_t*)&(pD->sourceCaps),
+ (const uint8_t*)caps,
+ (uint32_t)sizeof(DP_SourceDeviceCapabilities));
+ pD->sourceCapsStored = 1U;
+ }
+
+ return retVal;
+}
+
+uint32_t DP_GetSinkCapabilities(DP_PrivateData* pD, DP_SinkDeviceCapabilities* caps)
+{
+ /* test if parameters are valid */
+ uint32_t retVal = DP_GetSinkCapabilitiesSF(pD, caps);
+
+ if (CDN_EOK == retVal) {
+ retVal = readSinkCapabilities(pD);
+ }
+
+ if (CDN_EOK == retVal) {
+ /* copy sink capabilities from driver's private data into sink capabilities object */
+ CPS_BufferCopy((uint8_t*)caps,
+ (uint8_t*)(&(pD->sinkCaps)),
+ (uint32_t)sizeof(DP_SinkDeviceCapabilities));
+ }
+
+ return retVal;
+}
+
+uint32_t DP_LinkTraining(DP_PrivateData* pD, DP_TrainingStatus* resultLt)
+{
+ /* test if parameters are valid */
+ uint32_t retVal = DP_LinkTrainingSF(pD, resultLt);
+
+ if (CDN_EOK == retVal) {
+ /* test if any source caps stored */
+ if (0U == pD->sourceCapsStored) {
+ retVal = CDN_ENOENT;
+ }
+ }
+
+ if (CDN_EOK == retVal) {
+ /* read sink capabilities */
+ retVal = readSinkCapabilities(pD);
+ }
+
+ if (CDN_EOK == retVal) {
+ /* prepare training */
+ retVal = initTraining(pD);
+ }
+
+ if (CDN_EOK == retVal) {
+ /* do full training if fast training is not supported */
+ if (!getFastTrainingSupported(pD)) {
+ retVal = fullTraining(pD, resultLt);
+ } else {
+ *resultLt = DP_LT_OK;
+ retVal = fastTraining(pD);
+ }
+
+ if (CDN_EOK != retVal) {
+ *resultLt = DP_LT_UNFINISHED;
+ }
+ }
+
+ return retVal;
+}
+
+uint32_t DP_CheckLinkStable(DP_PrivateData* pD, bool* resultLs)
+{
+ uint32_t retVal;
+ uint8_t dpcdBuff[3];
+ uint8_t stepResult;
+ DP_DpcdTransfer transfer = {0U};
+ TrainingStepStatus status;
+
+ /* check if parameters are valid. */
+ retVal = DP_CheckLinkStableSF(pD, resultLs);
+
+ if (CDN_EOK == retVal) {
+ /* read 0x202 DPCD buffer */
+ setDpcdTransfer(&transfer, 0x202U, 3U, dpcdBuff);
+ retVal = DP_ReadDpcd(pD, &transfer);
+ }
+
+ if (CDN_EOK == retVal) {
+ /* check if link is stable and synchronized with sink. */
+ clearTrainingResult(&status);
+ parseLanesStatus(transfer.buff, &status);
+ stepResult = trainingStepEqCheck(&status, pD->linkState.laneCount);
+ *resultLs = (0U != stepResult);
+ }
+
+ return retVal;
+}
+
+uint32_t DP_ReadLinkStat(DP_PrivateData* pD, DP_LinkState* linkState)
+{
+ uint32_t retVal = DP_ReadLinkStatSF(pD, linkState);
+ uint8_t i;
+
+ if (CDN_EOK == retVal) {
+ /* get link state from PHY driver and update it in private data. */
+ retVal = fetchLinkState(pD);
+ }
+ if (CDN_EOK == retVal) {
+ /* copy link state from driver's private data to link state structure. */
+ linkState->laneCount = pD->linkState.laneCount;
+ linkState->linkRate = pD->linkState.linkRate;
+ linkState->ssc = pD->linkState.ssc;
+ for (i = 0; i < 4U; i++) {
+ /* copy voltage levels, per-lane. */
+ linkState->voltageSwing[i] = pD->linkState.voltageSwing[i];
+ linkState->preEmphasis[i] = pD->linkState.preEmphasis[i];
+ }
+ }
+
+ return retVal;
+}
+
+/* parasoft-end-suppress METRICS-36 */
diff --git a/packages/ti/drv/dss/src/csl/dp/src/dp_link_policy.h b/packages/ti/drv/dss/src/csl/dp/src/dp_link_policy.h
--- /dev/null
@@ -0,0 +1,59 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ *
+ * dp_link_policy.h
+ *
+ ******************************************************************************
+ */
+
+#ifndef DP_LINK_POLICY_H
+#define DP_LINK_POLICY_H
+
+#include "dp_if.h"
+#include "dp_priv.h"
+
+#include "dp_sd0801_if.h"
+
+#define COMMON_DPHY_CONFIG CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__DP_TX_PHY_CONFIG_REG_P, DP_TX_PHY_SKEW_BYPASS, 0, 0) | \
+ CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__DP_TX_PHY_CONFIG_REG_P, DP_TX_PHY_LANE0_SKEW, 0, 0) | \
+ CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__DP_TX_PHY_CONFIG_REG_P, DP_TX_PHY_LANE1_SKEW, 0, 1) | \
+ CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__DP_TX_PHY_CONFIG_REG_P, DP_TX_PHY_LANE2_SKEW, 0, 2) | \
+ CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__DP_TX_PHY_CONFIG_REG_P, DP_TX_PHY_LANE3_SKEW, 0, 3) | \
+ CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__DP_TX_PHY_CONFIG_REG_P, DP_TX_PHY_10BIT_ENABLE, 0, 0)
+
+void toSdLinkState (const DP_LinkState* dpState, DP_SD0801_LinkState* sdState);
+DP_SD0801_LinkRate toLinkRateSd(DP_LinkRate rate);
+void clearSourceCapabilities(DP_SourceDeviceCapabilities *caps);
+void clearSinkCapabilities(DP_SinkDeviceCapabilities *caps);
+uint32_t readSinkCapabilities(DP_PrivateData *pD);
+void clearLinkState(DP_LinkState* state);
+uint32_t fetchLinkState(DP_PrivateData* pD);
+
+#endif /* DP_LINK_POLICY_H */
diff --git a/packages/ti/drv/dss/src/csl/dp/src/dp_mailbox.c b/packages/ti/drv/dss/src/csl/dp/src/dp_mailbox.c
--- /dev/null
@@ -0,0 +1,285 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ *
+ * dp_mailbox.c
+ *
+ ******************************************************************************
+ */
+
+#include "dp_if.h"
+#include "dp_priv.h"
+#include "dp_sanity.h"
+
+#include "dp_mailbox.h"
+#include "dp_utils.h"
+#include "mhdp_apb_regs.h"
+
+#include "cdn_errno.h"
+#include "cdn_stdint.h"
+#include "cps_drv.h"
+
+void messageStart(DP_PrivateData *pD, uint8_t module, uint8_t opcode)
+{
+ /* put IDs of module and code into txBuffer */
+ pD->txBuffer[0] = opcode;
+ pD->txBuffer[1] = module;
+
+ /* set size of message header */
+ pD->txi = DP_MAILBOX_HEADER_SIZE;
+}
+
+void messageWriteUint8(DP_PrivateData *pD, uint8_t value)
+{
+ /* put 1B message to write into buffer */
+ pD->txBuffer[pD->txi] = value;
+
+ /* add size of message to counter */
+ pD->txi += 1U;
+}
+
+void messageWriteUint16(DP_PrivateData *pD, uint16_t value)
+{
+ /* put 2B message to write into buffer */
+ pD->txBuffer[pD->txi] = (uint8_t)((value & 0xFF00U) >> 8);
+ pD->txBuffer[pD->txi + 1U] = (uint8_t)(value & 0x00FFU);
+
+ /* add size of message to counter */
+ pD->txi += 2U;
+}
+
+void messageWriteUint32(DP_PrivateData *pD, uint32_t value)
+{
+ /* put 4B message to write into buffer */
+ pD->txBuffer[pD->txi] = (uint8_t)((value & 0xFF000000U) >> 24);
+ pD->txBuffer[pD->txi + 1U] = (uint8_t)((value & 0x00FF0000U) >> 16);
+ pD->txBuffer[pD->txi + 2U] = (uint8_t)((value & 0x0000FF00U) >> 8);
+ pD->txBuffer[pD->txi + 3U] = (uint8_t)(value & 0x000000FFU);
+
+ /* add size of message to counter */
+ pD->txi += 4U;
+}
+
+void messageWrite3Bytes(DP_PrivateData *pD, uint32_t value)
+{
+ /* put 3B message to write into buffer */
+ pD->txBuffer[pD->txi] = (uint8_t)((value & 0x00FF0000U) >> 16);
+ pD->txBuffer[pD->txi + 1U] = (uint8_t)((value & 0x0000FF00U) >> 8);
+ pD->txBuffer[pD->txi + 2U] = (uint8_t)(value & 0x000000FFU);
+
+ /* add size of message to counter */
+ pD->txi += 3U;
+}
+
+void messageWriteBuffer(DP_PrivateData *pD, const uint8_t *buffer, uint16_t length)
+{
+ /* put message to write into buffer */
+ CPS_BufferCopy(&(pD->txBuffer[pD->txi]), buffer, length);
+
+ /* add size of message to counter */
+ pD->txi += length;
+}
+
+void messageFinish(DP_PrivateData *pD)
+{
+ uint16_t length = (uint16_t)(pD->txi - DP_MAILBOX_HEADER_SIZE);
+
+ /* put length of message into buffer */
+ pD->txBuffer[2] = (uint8_t)((length & 0xFF00U) >> 8);
+ pD->txBuffer[3] = (uint8_t)(length & 0x00FFU);
+}
+
+void messageTransmit(DP_PrivateData *pD, DP_BusType busType)
+{
+ uint16_t i = 0U;
+ uint32_t mailboxFull;
+ MHDP_ApbRegs* regBase = selectRegBase(pD, busType);
+
+ /* loop through all bytes to send */
+ while (i < pD->txi)
+ {
+ mailboxFull = CPS_REG_READ(®Base->mhdp_apb_regs.MAILBOX_FULL_ADDR_p);
+
+ /* test if mailbox is not full */
+ if (0U == mailboxFull) {
+ CPS_REG_WRITE(®Base->mhdp_apb_regs.mailbox0_wr_data_p, pD->txBuffer[i]);
+ i++;
+ }
+ }
+}
+
+uint32_t DP_CheckResponse(const DP_PrivateData* pD, bool* awaits, DP_BusType busType)
+{
+ uint32_t mailboxEmpty;
+ uint32_t retVal;
+
+ retVal = DP_CheckResponseSF(pD, awaits, busType);
+
+ if (CDN_EOK == retVal)
+ {
+ /* select properly regBase */
+ MHDP_ApbRegs* regBase = selectRegBase(pD, busType);
+
+ mailboxEmpty = CPS_REG_READ(®Base->mhdp_apb_regs.MAILBOX_EMPTY_ADDR_p);
+
+ /* set if message was not received */
+ *awaits = (0U == mailboxEmpty);
+ }
+
+ return retVal;
+}
+
+void messageReceive(DP_PrivateData *pD, DP_BusType busType)
+{
+ uint16_t i = 0U;
+ uint16_t messageSize;
+ uint32_t mailboxEmpty;
+ uint32_t readVal;
+ MHDP_ApbRegs* regBase = selectRegBase(pD, busType);
+
+ /* read header first, to get size of message */
+ while (i < DP_MAILBOX_HEADER_SIZE)
+ {
+ mailboxEmpty = CPS_REG_READ(®Base->mhdp_apb_regs.MAILBOX_EMPTY_ADDR_p);
+
+ /* test if mailbox is not empty */
+ if (0U == mailboxEmpty)
+ {
+ readVal = CPS_REG_READ(®Base->mhdp_apb_regs.mailbox0_rd_data_p);
+ pD->rxBuffer[i] = (uint8_t)(readVal & 0x000000FFU);
+ i++;
+ }
+ }
+
+ messageSize = (uint16_t)(((uint16_t)pD->rxBuffer[2] << 8) |
+ (uint16_t)pD->rxBuffer[3]);
+ messageSize += DP_MAILBOX_HEADER_SIZE;
+
+ /* read message */
+ while (i < messageSize)
+ {
+ mailboxEmpty = CPS_REG_READ(®Base->mhdp_apb_regs.MAILBOX_EMPTY_ADDR_p);
+
+ /* test if mailbox is not empty */
+ if (0U == mailboxEmpty)
+ {
+ readVal = CPS_REG_READ(®Base->mhdp_apb_regs.mailbox0_rd_data_p);
+ pD->rxBuffer[i] = (uint8_t)(readVal & 0x000000FFU);
+ i++;
+ }
+ }
+}
+
+void messageGetHeader(DP_PrivateData *pD, uint8_t *module, uint8_t *opcode, uint16_t *length)
+{
+ /* get header of received package */
+ if (NULL != opcode)
+ {
+ *opcode = pD->rxBuffer[0];
+ }
+
+ /* get moduleID from received package */
+ if (NULL != module)
+ {
+ *module = pD->rxBuffer[1];
+ }
+
+ /* get length of message */
+ if (NULL != length)
+ {
+ *length = (uint16_t)(((uint16_t)pD->rxBuffer[2] << 8) |
+ (uint16_t)pD->rxBuffer[3]);
+ }
+
+ pD->rxi = DP_MAILBOX_HEADER_SIZE;
+}
+
+uint8_t messageHeaderMatches(const DP_PrivateData *pD, uint8_t module, uint8_t opcode)
+{
+ uint8_t retVal = 0U;
+
+ /* test if received header and moduleID as same as expected */
+ if ((opcode == pD->rxBuffer[0]) && (module == pD->rxBuffer[1]))
+ {
+ retVal = 1U;
+ }
+
+ return retVal;
+}
+
+void messageReadUint8(DP_PrivateData *pD, uint8_t *value)
+{
+ /* read 1B from buffer */
+ *value = pD->rxBuffer[pD->rxi];
+
+ /* add message size to counter */
+ pD->rxi += 1U;
+}
+
+void messageReadUint16(DP_PrivateData *pD, uint16_t *value)
+{
+ /* read 2B from buffer */
+ *value = (((uint16_t)pD->rxBuffer[pD->rxi] << 8) |
+ (uint16_t)pD->rxBuffer[pD->rxi + 1U]);
+
+ /* add message size to counter */
+ pD->rxi += 2U;
+}
+
+void messageReadUint32(DP_PrivateData *pD, uint32_t *value)
+{
+ /* read 4B from buffer */
+ *value = (((uint32_t)pD->rxBuffer[pD->rxi] << 24) |
+ ((uint32_t)pD->rxBuffer[pD->rxi + 1U] << 16) |
+ ((uint32_t)pD->rxBuffer[pD->rxi + 2U] << 8) |
+ (uint32_t)pD->rxBuffer[pD->rxi + 3U]);
+
+ /* add message size to counter */
+ pD->rxi += 4U;
+}
+
+void messageRead3Bytes(DP_PrivateData *pD, uint32_t *value)
+{
+ /* read 3B from buffer */
+ *value = (((uint32_t)pD->rxBuffer[pD->rxi] << 16) |
+ ((uint32_t)pD->rxBuffer[pD->rxi + 1U] << 8) |
+ (uint32_t)pD->rxBuffer[pD->rxi + 2U]);
+
+ /* add message size to counter */
+ pD->rxi += 3U;
+}
+
+void messageReadBuffer(DP_PrivateData *pD, uint8_t *buffer, uint16_t length)
+{
+ /* read message from buffer */
+ CPS_BufferCopy(buffer, &(pD->rxBuffer[pD->rxi]), length);
+
+ /* add size of message to counter */
+ pD->rxi += length;
+}
diff --git a/packages/ti/drv/dss/src/csl/dp/src/dp_mailbox.h b/packages/ti/drv/dss/src/csl/dp/src/dp_mailbox.h
--- /dev/null
@@ -0,0 +1,177 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ *
+ * dp_mailbox.h
+ *
+ ******************************************************************************
+ */
+
+/* parasoft-begin-suppress METRICS-36 "Function called from more then 5 functions, DRV-3823" */
+
+#ifndef DP_MAILBOX_H
+#define DP_MAILBOX_H
+
+#define DP_MAILBOX_HEADER_SIZE 4U
+
+/**
+ * Mailbox module IDs
+ */
+#define MB_MODULE_ID_DP_TX 0x01
+#define MB_MODULE_ID_HDCP_TX 0x07
+#define MB_MODULE_ID_HDCP_GENERAL 0x09
+#define MB_MODULE_ID_GENERAL 0x0A
+
+/**
+ * Start mailbox message.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] module ID of firmware module responsible for processing command.
+ * @param[in] opcode ID (code) of the command.
+ */
+void messageStart(DP_PrivateData* pD, uint8_t module, uint8_t opcode);
+
+/**
+ * Append 8-bit value to message.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] value Value to append to message.
+ */
+void messageWriteUint8(DP_PrivateData* pD, uint8_t value);
+
+/**
+ * Append 16-bit value to message, in Big Endian.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] value Value to append to message.
+ */
+void messageWriteUint16(DP_PrivateData* pD, uint16_t value);
+
+/**
+ * Append 32-bit value to message, in Big Endian.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] value Value to append to message.
+ */
+void messageWriteUint32(DP_PrivateData* pD, uint32_t value);
+
+/**
+ * Append 3-byte value to message, in Big Endian. MSB is unused.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] value Value to append to message.
+ */
+void messageWrite3Bytes(DP_PrivateData* pD, uint32_t value);
+
+/**
+ * Copy bytes from buffer to mailbox command.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] buff Pointer to buffer to copy data from.
+ * @param[in] length Length (in bytes) of data to copy. Max value is defined by
+ * DP_MAX_MAILBOX_PAYLOAD.
+ */
+void messageWriteBuffer(DP_PrivateData *pD, const uint8_t *buffer, uint16_t length);
+
+/**
+ * Finish mailbox message, by writing its size to appropriate
+ * location.
+ * @param[in] pD Driver state info specific to this instance.
+ */
+void messageFinish(DP_PrivateData* pD);
+
+/**
+ * Transmit mailbox message. Function blocks, until transmission is
+ * complete.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] busType Bus type (APB or SAPB) to be used for transmission.
+ */
+void messageTransmit(DP_PrivateData* pD, DP_BusType busType);
+
+/**
+ * Receive mailbox message. Function blocks, until message is received.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] busType Bus type (APB or SAPB) to be used for receive.
+ */
+void messageReceive(DP_PrivateData* pD, DP_BusType busType);
+
+/**
+ * Get mailbox message header. NULL pointer may be used for any value, except
+ * pD, if that value is not needed.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] module ID of firmware module that sent response.
+ * @param[out] opcode ID (code) of the response.
+ * @param[out] length Length of the response, excluding header.
+ */
+void messageGetHeader(DP_PrivateData *pD, uint8_t *module, uint8_t *opcode, uint16_t *length);
+
+/**
+ * Verify message and opcode of the message
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] module ID of firmware module, that should be in the response.
+ * @param[in] opcode ID (code) of the command, that should be in the response.
+ * @return 1 module and opcode matches response.
+ * @return 0 module and opcode does not match response.
+ */
+uint8_t messageHeaderMatches(const DP_PrivateData *pD, uint8_t module, uint8_t opcode);
+
+/**
+ * Read 8-bit value from message.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] value Pointer to variable to be filled with value read.
+ */
+void messageReadUint8(DP_PrivateData *pD, uint8_t *value);
+
+/**
+ * Read 16-bit Big Endian value from message.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] value Pointer to variable to be filled with value read.
+ */
+void messageReadUint16(DP_PrivateData *pD, uint16_t *value);
+
+/**
+ * Read 32-bit Big Endian value from message.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] value Pointer to variable to be filled with value read.
+ */
+void messageReadUint32(DP_PrivateData *pD, uint32_t *value);
+
+/**
+ * Read 3-byte Big Endian value from message. MSB is unused.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] value Pointer to variable to be filled with value read.
+ */
+void messageRead3Bytes(DP_PrivateData* pD, uint32_t* value);
+
+/**
+ * Copy bytes from mailbox response to a buffer.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] buff Pointer to buffer to be filled with values read.
+ * @param[in] length Length (in bytes) of data to copy. Max value is defined by
+ * DP_MAX_MAILBOX_PAYLOAD.
+ */
+void messageReadBuffer(DP_PrivateData *pD, uint8_t *buffer, uint16_t length);
+
+#endif
+
+/* parasoft-end-suppress METRICS-36 */
diff --git a/packages/ti/drv/dss/src/csl/dp/src/dp_mst.c b/packages/ti/drv/dss/src/csl/dp/src/dp_mst.c
--- /dev/null
@@ -0,0 +1,985 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2014-2018 Cadence Design Systems, Inc.
+ * All rights reserved worldwide
+ * The material contained herein is the proprietary and confidential
+ * information of Cadence or its licensors, and is supplied subject to, and may
+ * be used only by Cadence's customer in accordance with a previously executed
+ * license and maintenance agreement between Cadence and that customer.
+ *
+ ******************************************************************************
+ *
+ * dp_mst.c
+ *
+ ******************************************************************************
+ */
+
+#include "dp_if.h"
+#include "dp_mst_if.h"
+#include "dp_priv.h"
+#include "dp_internal.h"
+#include "dp_mst.h"
+#include "dp_mst_structs_if.h"
+#include "dp_topology_mgr.h"
+#include "dp_utils.h"
+#include "dp_register.h"
+#include "mhdp_apb_regs.h"
+#include "cdn_errno.h"
+#include "cdn_math.h"
+#include "cdn_log.h"
+#include "cps_drv.h"
+#include "custom_types.h"
+
+typedef struct DP_RateGovConfig_s {
+ uint32_t targAvSlotsX;
+ uint32_t targAvSlotsY;
+ uint32_t rateGovEn;
+} DP_RateGovConfig;
+
+typedef struct DP_SlotsCfg_s {
+ uint8_t slots;
+ float32_t fracSlots;
+ uint32_t payloadBandwidth;
+} DP_SlotsCfg;
+
+uint32_t DP_StreamIdMstSanity(const DP_PrivateData* pD, uint8_t streamId)
+{
+ uint32_t ret;
+
+ /* Fail check for SST mode. */
+ if (!pD->mstEnabled) {
+ ret = CDN_ENOTSUP;
+ }
+ /* test if streamId is greater than max allowed by hardware */
+ else if (streamId > (pD->hwConfig.videoStreams - 1U)) {
+ ret = CDN_EINVAL;
+ }
+ else {
+ ret = CDN_EOK;
+ }
+
+ return ret;
+}
+
+uint32_t DP_StreamIdMstSstDscSanity(const DP_PrivateData* pD,
+ uint8_t streamId,
+ bool splitPanel)
+{
+ uint8_t maxStreamId = 0U;
+ uint32_t ret = CDN_EOK;
+
+ /* For Split Panel mode, only stream 0 can be used for DSC. */
+ if ((pD->mstEnabled) && (!splitPanel)) {
+ maxStreamId = DP_NUMBER_OF_DSC_ENCODERS - 1U;
+ }
+
+ /* test if streamId is greater than max allowed */
+ if (streamId > maxStreamId) {
+ ret = CDN_EINVAL;
+ }
+
+ return ret;
+}
+
+uint32_t DP_StreamIdMstSstSanity(const DP_PrivateData* pD, uint8_t streamId)
+{
+ uint8_t maxStreamId = 0U;
+ uint32_t ret = CDN_EOK;
+
+ /* With MST disabled, only stream 0 can be used. */
+ if (pD->mstEnabled) {
+ maxStreamId = pD->hwConfig.videoStreams - 1U;
+ }
+
+ /* test if streamId is greater than allowed by hardware */
+ if (streamId > maxStreamId) {
+ ret = CDN_EINVAL;
+ }
+
+ return ret;
+}
+
+/*
+ * Calculate bits-per-component to bits-pet-pixel
+ * @param[in] bitsPerComponent number of bits-per-component
+ * return number of bits-per-pixel
+ */
+static inline uint8_t bpcToBpp(float64_t bitsPerComponent)
+{
+ /* For RGB and YCbCr 4:4:4 */
+ float64_t result = bitsPerComponent * 3.0;
+ return (uint8_t)result;
+}
+
+/*
+ * Calculate time slots for sink's stream
+ * @param[in] pD pointer to DP private data object
+ * @param[in] streamId number of stream
+ * @param[in] port pointer to sink port object
+ * @param[in] slotsCfg pointer to slot configuration object
+ * @return CDN_EOK if success
+ * @return CDN_EINVAL if parameters are invalid
+ * @return CDN_ENOSPEC if not enough slots
+ */
+static uint32_t calculateSlots(DP_PrivateData* pD,
+ uint8_t streamId,
+ MST_drm_dp_port* port,
+ DP_SlotsCfg* slotsCfg)
+{
+ uint32_t ret;
+ float64_t pixelClock = pD->videoParameters[streamId].vicParams.pxlFreq * 1000.0;
+ float64_t bitsPerComponent = calculateBitsPerComponent(pD, streamId);
+ uint8_t bitPerPixel = bpcToBpp(bitsPerComponent);
+
+ slotsCfg->payloadBandwidth = DP_MST_MgrCalcPbnMode((uint32_t)pixelClock,
+ bitPerPixel,
+ pD->fecEnabled);
+
+ ret = DP_MST_MgrFindVcpiSlots(&pD->mstTopMgr,
+ port,
+ slotsCfg->payloadBandwidth,
+ &(slotsCfg->slots),
+ &(slotsCfg->fracSlots));
+
+ return ret;
+}
+
+/*
+ * Set payload bandwidth for topology
+ * @param[in] pD pointer to DP private data object
+ */
+static void setPayloadBandwidth(DP_PrivateData* pD)
+{
+ uint16_t symbolRate = getSymbolRate(pD->linkState.linkRate);
+
+ DP_MST_MgrSetPayloadBandwidth(&pD->mstTopMgr,
+ symbolRate,
+ pD->linkState.laneCount);
+}
+
+/*
+ * Read data from global config to check, if uCPU has finished writing
+ * @param[in] pD pointer to DP private data object
+ * @return CDN_EOK if success
+ * @return CDN_EINVAL if writing was not finished
+ */
+static uint32_t finishVcpiAllocation(DP_PrivateData* pD)
+{
+ DP_RegisterTransfer regTransfer = {0U};
+
+ regTransfer.addr = offsetof(MHDP_ApbRegs, mhdp_apb_regs.DP_FRAMER_GLOBAL_CONFIG_p);
+ return DP_ReadRegister(pD, ®Transfer);
+}
+
+/*
+ * Check, if video on given stream is on
+ * @param[in] pD pointer to private data object
+ * @param[in] streamId number of stream
+ * @param[in, out] isOn is video or not
+ * @return CDN_EOK if success
+ * @return other error code if cannot read config register
+ */
+static uint32_t isVideoOn(DP_PrivateData* pD, uint8_t streamId, bool *isOn)
+
+{
+ uint32_t retVal;
+ DP_RegisterTransfer regTransfer = {0U};
+
+ /* read configuration for stream */
+ regTransfer.addr = offsetof(MHDP_ApbRegs, mhdp_apb_regs.mhdp_dptx_stream[0].STREAM_CONFIG_p);
+ regTransfer.addr += streamId * (uint32_t)sizeof(pD->regBase->mhdp_apb_regs.mhdp_dptx_stream[0]);
+ retVal = DP_ReadRegister(pD, ®Transfer);
+
+ if (retVal == CDN_EOK) {
+ uint32_t videoBit = CPS_FLD_READ(MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM,
+ STREAM_CONFIG_P__NO_VIDEO,
+ regTransfer.val);
+ /* set isOn due to videoBit */
+ if (videoBit != 0U) {
+ *isOn = false;
+ } else {
+ *isOn = true;
+ }
+ }
+
+ return retVal;
+}
+
+/* Set slot allocation for particular stream in DP controller
+ * @param[in] pD pointer to private data object
+ * @param[in] streamId number of stream
+ * @param[in] startSlot number of first slot
+ * @param[in] endSlot number of last slot
+ * @return CDN_EOK if success
+ * @return CDN_EINVAL if cannot do R/W operation
+ */
+static uint32_t setSlotAllocation(DP_PrivateData* pD,
+ uint8_t streamId,
+ uint8_t startSlot,
+ uint8_t endSlot)
+{
+ uint32_t reg = 0U;
+ DP_RegisterTransfer regTransfer = {0U};
+
+ /* set start slot */
+ reg = CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM,
+ DP_MST_SLOT_ALLOCATE_P__STREAM_START_SLOT,
+ reg,
+ startSlot);
+ /* set end slot */
+ reg = CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM,
+ DP_MST_SLOT_ALLOCATE_P__STREAM_END_SLOT,
+ reg,
+ endSlot);
+
+ /* write slot allocation configuration */
+ regTransfer.addr = offsetof(MHDP_ApbRegs, mhdp_apb_regs.mhdp_dptx_stream[0].DP_MST_SLOT_ALLOCATE_p);
+ regTransfer.addr += streamId * (uint32_t)sizeof(pD->regBase->mhdp_apb_regs.mhdp_dptx_stream[0]);
+ regTransfer.val = reg;
+
+ return DP_WriteRegister(pD, ®Transfer);
+}
+
+/* Get slot allocation for particular stream in DP controller
+ * @param[in] pD pointer to private data object
+ * @param[in] streamId number of stream
+ * @param[in] startSlot number of first slot
+ * @param[in] endSlot number of last slot
+ * @return CDN_EOK if success
+ * @return CDN_EINVAL if cannot do read data from register
+ */
+static uint32_t getSlotAllocation(DP_PrivateData* pD,
+ uint8_t streamId,
+ uint8_t * startSlot,
+ uint8_t * endSlot)
+{
+ uint32_t retVal;
+ DP_RegisterTransfer regTransfer = {0U};
+
+ /* read slot allocation from register */
+ regTransfer.addr = offsetof(MHDP_ApbRegs, mhdp_apb_regs.mhdp_dptx_stream[0].DP_MST_SLOT_ALLOCATE_p);
+ regTransfer.addr += streamId * (uint32_t)sizeof(pD->regBase->mhdp_apb_regs.mhdp_dptx_stream[0]);
+ retVal = DP_ReadRegister(pD, ®Transfer);
+
+ if (retVal == CDN_EOK) {
+
+ *startSlot = (uint8_t)CPS_FLD_READ(MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM,
+ DP_MST_SLOT_ALLOCATE_P__STREAM_START_SLOT,
+ regTransfer.val);
+
+ *endSlot = (uint8_t)CPS_FLD_READ(MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM,
+ DP_MST_SLOT_ALLOCATE_P__STREAM_END_SLOT,
+ regTransfer.val);
+ }
+
+ return retVal;
+}
+
+/* Calculate Target average number of slots per MTP configuration parameters
+ * (with fractional part)
+ * @param[in] targetAverageSlots
+ * @param[out] targetAverageSlotsX
+ * @param[out] targetAverageSlotsY
+ */
+static void calcRateGoverningComponents(float64_t targetAverageSlots,
+ DP_RateGovConfig* rateCfg)
+{
+ float64_t targetAverageSlotsFraction;
+ float64_t yReal;
+
+ /* Truncate */
+ rateCfg->targAvSlotsX = (uint32_t)targetAverageSlots;
+ targetAverageSlotsFraction = targetAverageSlots - (float64_t)rateCfg->targAvSlotsX;
+ yReal = targetAverageSlotsFraction * 16.0;
+
+ /* Round up */
+ rateCfg->targAvSlotsY = (uint32_t)ceil(yReal);
+
+ DbgMsg(DBG_GEN_MSG, DBG_FYI, "Rate governing components : X = %0d (%f) Y = %0d (%f)",
+ rateCfg->targAvSlotsX, targetAverageSlots,
+ rateCfg->targAvSlotsY, yReal);
+
+}
+
+/*
+ * Calculate video FIFO latency threshold.
+ * @param[in] targetAverageSlots average number of slots
+ * @param[in] lanesNumber number of lanes
+ * @return threshold
+ */
+static uint32_t calculateThreshold(float64_t targetAverageSlots, uint8_t lanesNumber)
+{
+ uint32_t threshold;
+ float64_t targetEntries;
+ float64_t threshTemp;
+
+ /* calculate threshold */
+ targetEntries = targetAverageSlots / 2.0;
+ threshTemp = targetEntries - ((targetEntries * targetEntries) / 32.0);
+ threshold = (uint32_t)ceil((threshTemp * (float64_t)lanesNumber) / 4.0);
+
+ if (threshold < 2U) {
+ threshold = 2U;
+ }
+
+ return threshold;
+}
+
+/*
+ * Start ACT sequence
+ * @param[in] pD pointer to DP private data object
+ * @return CDN_EOK if success
+ * @return CDN_EIO if cannot read payload table
+ * @return CDN_EINVAL if cannot start sequence
+ */
+static uint32_t startActSequence(DP_PrivateData* pD)
+{
+ uint32_t retVal;
+ DP_RegisterTransfer regTransfer = {0U};
+
+ /* read MTPH control register */
+ regTransfer.addr = offsetof(MHDP_ApbRegs, mhdp_apb_regs.DP_MTPH_CONTROL_p);
+ retVal = DP_ReadRegister(pD, ®Transfer);
+
+ /* set ACT bit in MTPH register */
+ if (retVal == CDN_EOK) {
+ regTransfer.val = CPS_FLD_SET(MHDP__MHDP_APB_REGS__DP_MTPH_CONTROL_P, MTPH_ACT_EN, regTransfer.val);
+ regTransfer.addr = offsetof(MHDP_ApbRegs, mhdp_apb_regs.DP_MTPH_CONTROL_p);
+ retVal = DP_WriteRegister(pD, ®Transfer);
+ }
+
+ DbgMsg(DBG_GEN_MSG, DBG_FYI, "ACT enabled in MTPH control\n");
+
+#ifndef IS_SPEEDBRIDGE
+
+ if (retVal == CDN_EOK) {
+ uint32_t actStatus;
+ do {
+ regTransfer.addr = offsetof(MHDP_ApbRegs, mhdp_apb_regs.DP_MTPH_STATUS_p);
+ retVal = DP_ReadRegister(pD, ®Transfer);
+
+ if (retVal != CDN_EOK) {
+ break;
+ }
+
+ actStatus = CPS_FLD_READ(MHDP__MHDP_APB_REGS,
+ DP_MTPH_STATUS_P__MTPH_ACT_STATUS,
+ regTransfer.val);
+
+ } while (actStatus != 0U);
+ }
+
+#endif
+
+ /* check ACT status */
+ if (retVal == CDN_EOK) {
+ DbgMsg(DBG_GEN_MSG, DBG_FYI, "ACT status in source is set\n");
+ retVal = DP_MST_MgrCheckActStatus(&pD->mstTopMgr);
+ }
+
+ return retVal;
+}
+
+/*
+ * Set configuration of range governing
+ * @param[in] pD pointer to DP private data object
+ * @param[in] streamId stream number
+ * @param[in] cfg pointer to rate configuration object
+ * @return CDN_EOK if success
+ * @return CD_EINVAL if cannot set
+ */
+static uint32_t setRateGoverningConfig(DP_PrivateData *pD, uint8_t streamId, const DP_RateGovConfig *cfg)
+{
+ uint32_t retVal;
+ uint32_t reg = 0U;
+ DP_RegisterTransfer regTransfer = {0U};
+
+ /* set X average slots */
+ reg = CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM,
+ RATE_GOVERNING_CTRL_P__TARG_AV_SLOTS_X,
+ reg,
+ cfg->targAvSlotsX);
+ /* set Y average slots */
+ reg = CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM,
+ RATE_GOVERNING_CTRL_P__TARG_AV_SLOTS_Y,
+ reg,
+ cfg->targAvSlotsY);
+
+ if (cfg->rateGovEn != 0U) {
+ /* enable rate governing */
+ reg = CPS_FLD_SET(MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM,
+ RATE_GOVERNING_CTRL_P__RATE_GOV_EN,
+ reg);
+ }
+
+ /* write rate governing configuration */
+ regTransfer.addr = offsetof(MHDP_ApbRegs, mhdp_apb_regs.mhdp_dptx_stream[0].RATE_GOVERNING_CTRL_p);
+ regTransfer.addr += streamId * (uint32_t)sizeof(pD->regBase->mhdp_apb_regs.mhdp_dptx_stream[0]);
+ regTransfer.val = reg;
+
+ retVal = DP_WriteRegister(pD, ®Transfer);
+
+ return retVal;
+}
+
+/* Set video FIFO latency threshold based on fracSlots for given stream.
+ * @param[in] pD pointer to private data object
+ * @param[in] streamId number of streams
+ * @param[in] fracSlots value of fractional part of slot
+ * @return CDN_EOK if success
+ * @return CDN_EINVAL if cannot write data
+ */
+static uint32_t setLineThreshold(DP_PrivateData *pD, uint8_t streamId, float64_t fracSlots)
+{
+ DP_RegisterTransfer regTransfer = {0U};
+
+ regTransfer.val = calculateThreshold(fracSlots, pD->linkState.laneCount);
+ regTransfer.addr = offsetof(MHDP_ApbRegs, mhdp_apb_regs.mhdp_dptx_stream[0].LINE_THRESH_p);
+ regTransfer.addr += streamId * (uint32_t)sizeof(pD->regBase->mhdp_apb_regs.mhdp_dptx_stream[0]);
+
+ return DP_WriteRegister(pD, ®Transfer);
+}
+
+/*
+ * Calculate start and end slot for payload
+ * @param[in] payload pointer to MST payload object
+ * @param[out] startSlot start slot number
+ * @param[out] endSlot end slot number
+ */
+static inline void calculateSlotRange(const MST_drm_dp_payload *payload, uint8_t* startSlot, uint8_t* endSlot)
+{
+ *startSlot = payload->start_slot;
+ *endSlot = (*startSlot + payload->num_slots) - 1U;
+}
+
+/*
+ * Get payload (for port) and update if differences
+ * @param[in] pD pointer to private data object
+ * @return CDN_EOK if success
+ * @return CDN_EINVAL if cannot set new allocation
+ */
+static uint32_t updateSlotAllocation(DP_PrivateData *pD)
+{
+ uint32_t retVal = CDN_EOK;
+ MST_drm_dp_payload *payload;
+ uint8_t startSlot;
+ uint8_t endSlot;
+ uint8_t i;
+
+ for (i = 0U; i < DP_MAX_NUMBER_OF_STREAMS; i++) {
+
+ if (pD->sinkList[i].port == NULL) {
+ continue;
+ }
+
+ /* get payload configuration from topology manager */
+ payload = DP_MST_MgrGetPortPayload(&pD->mstTopMgr, pD->sinkList[i].port);
+ if (payload == NULL) {
+ continue;
+ }
+
+ /* get payload configuration from DPTX registers */
+ retVal = getSlotAllocation(pD, pD->sinkList[i].streamId, &startSlot, &endSlot);
+
+ if (retVal == CDN_EOK) {
+ /* if payload configuration in topology manager is different than in DPTX registers
+ * then update DPTX registers */
+ if (startSlot != payload->start_slot) {
+ calculateSlotRange(payload, &startSlot, &endSlot);
+ retVal = setSlotAllocation(pD, pD->sinkList[i].streamId, startSlot, endSlot);
+ }
+ }
+
+ if (retVal != CDN_EOK) {
+ break;
+ }
+ }
+
+ return retVal;
+
+}
+
+/*
+ * Clear slot allocation for stream
+ * @param[in] pD pointer to private data object
+ * @param[in] streamId stream number
+ * @return CDN_EOK if success
+ * @return CDN_EINVAL if cannot reset
+ */
+static uint32_t clearSlotAllocation(DP_PrivateData* pD, uint8_t streamId)
+{
+ /* clear slot allocation in source registers */
+ uint32_t retVal = setSlotAllocation(pD, streamId, 0U, 0U);
+
+ if (retVal == CDN_EOK) {
+ retVal = updateSlotAllocation(pD);
+ }
+
+ if (retVal == CDN_EOK) {
+ retVal = startActSequence(pD);
+ }
+
+ return retVal;
+}
+
+/*
+ * Clear SDP packets for stream
+ * @param[in] pD pointer to private data object
+ * @param[in] streamId stream number
+ * @return CDN_EOK if success
+ * @return CDN_EINVAL if parameters are invalid
+ */
+static uint32_t clearSdpPackets(DP_PrivateData *pD, uint8_t streamId)
+{
+ uint8_t i;
+ uint32_t retVal;
+
+ /* clear each SDP from stream */
+ for (i = 0U; i < MST_NUMBER_OF_SDP; i++) {
+ retVal = DP_RemoveSdp(pD, streamId, i);
+
+ if (CDN_EOK != retVal) {
+ break;
+ }
+ }
+
+ return retVal;
+}
+
+/*
+ * Calculate and set rate governing components
+ * @param[in] pD pointer to private data object
+ * @param[in] streamId stream number
+ * @param[in] fracSlots fractional part of slots
+ * @retrun CDN_EOK if success
+ * @return CDN_EINVAL if cannot set rate governing
+ */
+static uint32_t configureRateGoverning(DP_PrivateData* pD, uint8_t streamId, float64_t fracSlots)
+{
+ DP_RateGovConfig rateGovConfig;
+
+ calcRateGoverningComponents(fracSlots, &rateGovConfig);
+
+ rateGovConfig.rateGovEn = 1U;
+
+ return setRateGoverningConfig(pD, streamId, &rateGovConfig);
+
+}
+
+/*
+ * Set clear rate governing components
+ * @param[in] pD pointer to private data object
+ * @param[in] streamId stream number
+ * @retrun CDN_EOK if success
+ * @return CDN_EINVAL if cannot reset rate governing
+ */
+static inline uint32_t clearRateGoverning(DP_PrivateData* pD, uint8_t streamId)
+{
+ DP_RateGovConfig rateGovConfig = {0U};
+
+ return setRateGoverningConfig(pD, streamId, &rateGovConfig);
+}
+
+/*
+ * Returns pointer to sink device
+ * @param[in] pD pointer to private data object
+ * @param[in] streamId stream number
+ * @retrun pointer to sink device if found
+ * @return NULL if sink device was not found
+ */
+/* parasoft-begin-suppress MISRA2012-RULE-8_13_a-4 "Pass parameter 'pD' as const, DRV-3895" */
+static DP_SinkDevice* findSinkDevice(DP_PrivateData* pD, uint8_t streamId)
+{
+ uint32_t i;
+ DP_SinkDevice *sinkDevice = NULL;
+
+ /* look for sink device in each stream */
+ for (i = 0U; i < DP_MAX_NUMBER_OF_STREAMS; i++) {
+ if ((pD->sinkList[i].port != NULL) && (streamId == pD->sinkList[i].streamId)) {
+ sinkDevice = &pD->sinkList[i];
+ break;
+ }
+ }
+
+ return sinkDevice;
+}
+/* parasoft-end-suppress MISRA2012-RULE-8_13_a-4 */
+
+/*
+ * Set or reset bits of payload, due to enable flag
+ * @param[in, out] payload actual payload
+ * @param[in] mask mask value
+ * @param[in] set if payload is mask directly (set = 'true') or by negation (set = 'false')
+ */
+static void maskPayload(uint32_t* payload, uint32_t mask, bool set)
+{
+ if (set) {
+ *payload |= mask;
+ } else {
+ *payload &= ~mask;
+ }
+}
+
+/*
+ * Set timeslots for MST which should be encrypted
+ * @param[in] pD pointer to DP private data object
+ * @param[in] payload_31_0 payload for slots 0 - 31
+ * @param[in] payload_32_63 payload for slots 32 - 63
+ * @retrun CDN_EOK if success
+ * @return CDN_EINVAL if parameters are invalid
+ */
+static uint32_t setEncryption(DP_PrivateData* pD, uint32_t payload_31_0,
+ uint32_t payload_63_32, bool enable)
+{
+ uint32_t retVal;
+ uint8_t i;
+
+ uint32_t payload[] = {payload_31_0, payload_63_32};
+
+ /* array of payload registers addresses */
+ uint32_t payloadAddr[] = {
+ offsetof(MHDP_ApbRegs,
+ mhdp_apb_regs.DP_MTPH_ECF_SLOTS_31_0_p),
+ offsetof(MHDP_ApbRegs,
+ mhdp_apb_regs.DP_MTPH_ECF_SLOTS_63_32_p)
+ };
+
+ uint8_t size = (uint8_t)(sizeof(payload) / sizeof(payload[0]));
+
+ DP_RegisterTransfer regTransfer = {0U};
+
+ for (i = 0U; i < size; i++) {
+
+ /* read actual state of encryption */
+ regTransfer.addr = payloadAddr[i];
+ retVal = DP_ReadRegister(pD, ®Transfer);
+
+ if (retVal == CDN_EOK) {
+
+ /* set new encryption */
+ maskPayload(®Transfer.val, payload[i], enable);
+ retVal = DP_WriteRegister(pD, ®Transfer);
+
+ } else {
+ DbgMsg(DBG_GEN_MSG, DBG_CRIT, "Set encryption failed, cannot read register\n");
+ }
+
+ if (retVal != CDN_EOK) {
+ break;
+ }
+ }
+
+ /* start ACT sequence */
+ if (retVal == CDN_EOK) {
+ retVal = startActSequence(pD);
+ }
+
+ return retVal;
+}
+
+/*
+ * Calculate timeslots for payload
+ * @param[in] payload pointer to MST payload object
+ * @param[out] payload_31_0 payload for slots 0 - 31
+ * @param[out] payload_32_63 payload for slots 32 - 63
+ * @return CDN_EOK if success
+ * @return CDN_EINVAL if endSlot greater than max
+ */
+static uint32_t calculateTimeSlotsForPayload(const MST_drm_dp_payload *payload, uint32_t* payload_31_0, uint32_t* payload_63_32)
+{
+ uint8_t i;
+ uint8_t endSlot;
+ uint8_t startSlot;
+ uint64_t fullPayload = 0U;
+ uint32_t retVal = CDN_EOK;
+
+ calculateSlotRange(payload, &startSlot, &endSlot);
+
+ /* test if endSlot is not greater than max */
+ if (endSlot > 63U) {
+ retVal = CDN_EINVAL;
+ }
+
+ if (CDN_EOK == retVal) {
+
+ /* generate payload */
+ for (i = startSlot; i <= endSlot; i++) {
+ /* parasoft-begin-suppress MISRA2012-RULE-12_2-2 "Shift operation should be enclosed, DRV-3822" */
+ fullPayload |= (uint64_t)1U << i;
+ /* parasoft-end-suppress MISRA2012-RULE-12_2-2 */
+ }
+
+ /* truncate payloads */
+ *payload_31_0 = (uint32_t)fullPayload;
+ *payload_63_32 = (uint32_t)(fullPayload >> 32U);
+ }
+
+ return retVal;
+}
+
+/*
+ * Set slots allocation for given source stream
+ * @param[in] pD pointer to DP private data object
+ * @param[in] streamId stream number
+ * @param[in] port pointer to MST port object
+ * @return CDN_EOK if success
+ * @retrun CDN_EINVAL if cannot set
+ */
+static uint32_t setSourceSlotsAllocation(DP_PrivateData* pD, uint8_t streamId, MST_drm_dp_port* port)
+{
+ uint32_t retVal = CDN_EOK;
+ MST_drm_dp_payload *payload = NULL;
+ uint8_t startSlot;
+ uint8_t endSlot;
+
+ payload = DP_MST_MgrGetPortPayload(&pD->mstTopMgr, port);
+ if (payload == NULL) {
+ retVal = CDN_EINVAL;
+ }
+
+ if (retVal == CDN_EOK) {
+ /* set slot allocation in source registers */
+ calculateSlotRange(payload, &startSlot, &endSlot);
+ retVal = setSlotAllocation(pD, streamId, startSlot, endSlot);
+ }
+
+ if (retVal == CDN_EOK) {
+ retVal = startActSequence(pD);
+ }
+
+ return retVal;
+}
+
+/*
+ * Configure payload for MST virtual channel
+ * @param[in] pD pointer to DP private data object
+ * @param[in] streamId stream number
+ * @param[in] port pointer to MST port object
+ * @return CDN_EOK if success
+ * @return CDN_EINVAL if cannot configure payload
+ */
+static uint32_t configurePayload(DP_PrivateData* pD, uint8_t streamId, MST_drm_dp_port* port)
+{
+ /* update first part of payload */
+ uint32_t retVal = DP_MST_MgrUpdatePayloadPart1(&pD->mstTopMgr);
+
+ /* set slots allocation for port */
+ if (retVal == CDN_EOK) {
+ retVal = setSourceSlotsAllocation(pD, streamId, port);
+ }
+
+ /* update second part of payload */
+ if (retVal == CDN_EOK) {
+ retVal = DP_MST_MgrUpdatePayloadPart2(&pD->mstTopMgr);
+ }
+
+ return retVal;
+}
+
+uint32_t DP_MST_SetStreamEnable(DP_PrivateData* pD, uint8_t streamId, bool streamEnable)
+{
+ uint32_t retVal;
+ uint32_t reg;
+ DP_RegisterTransfer regTransfer = {0U};
+
+ /* read current stream configuration */
+ regTransfer.addr = offsetof(MHDP_ApbRegs, mhdp_apb_regs.mhdp_dptx_stream[0].STREAM_CONFIG_p);
+ regTransfer.addr += streamId * (uint32_t)sizeof(pD->regBase->mhdp_apb_regs.mhdp_dptx_stream[0]);
+ retVal = DP_ReadRegister(pD, ®Transfer);
+
+ if (retVal == CDN_EOK) {
+
+ reg = regTransfer.val;
+
+ /* enable stream and clear no-vieo if 'enable' is true */
+ if (streamEnable) {
+ reg = CPS_FLD_SET(MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM, STREAM_CONFIG_P__STREAM_EN, reg);
+ reg = CPS_FLD_CLEAR(MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM, STREAM_CONFIG_P__NO_VIDEO, reg);
+ } else {
+ reg = CPS_FLD_CLEAR(MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM, STREAM_CONFIG_P__STREAM_EN, reg);
+ reg = CPS_FLD_SET(MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM, STREAM_CONFIG_P__NO_VIDEO, reg);
+ }
+
+ /* write current stream configuration */
+ regTransfer.val = reg;
+ retVal = DP_WriteRegister(pD, ®Transfer);
+ }
+
+ if (retVal == CDN_EOK) {
+ /* set streamEnabled flag in pD */
+ pD->streamEnabled[streamId] = streamEnable;
+ }
+
+ return retVal;
+}
+
+uint32_t DP_MST_AllocateVcpi(DP_PrivateData *pD, uint8_t streamId, DP_SinkDevice *sinkDevice)
+{
+ DP_SlotsCfg slotsCfg = {0};
+ uint32_t ret;
+
+ setPayloadBandwidth(pD);
+
+ ret = calculateSlots(pD, streamId, sinkDevice->port, &slotsCfg);
+
+ if (ret == CDN_EOK) {
+ /* allocate virtual channel */
+ ret = DP_MST_MgrAllocateVcpi(&pD->mstTopMgr,
+ sinkDevice->port,
+ slotsCfg.payloadBandwidth,
+ slotsCfg.slots);
+ }
+
+ if (ret == CDN_EOK) {
+ ret = configurePayload(pD, streamId, sinkDevice->port);
+ }
+
+ if (ret == CDN_EOK) {
+ /* configure rate governing for stream */
+ ret = configureRateGoverning(pD, streamId, slotsCfg.fracSlots);
+ }
+
+ if (ret == CDN_EOK) {
+ /* set threshold for stream */
+ ret = setLineThreshold(pD, streamId, slotsCfg.fracSlots);
+ }
+
+ /* assign streamId to sink device */
+ sinkDevice->streamId = streamId;
+
+ if (ret == CDN_EOK) {
+ /* check if allocation was finished */
+ ret = finishVcpiAllocation(pD);
+ }
+
+ return ret;
+}
+
+uint32_t DP_MST_DeallocateVcpi(DP_PrivateData *pD, uint8_t streamId, DP_SinkDevice *sinkDevice)
+{
+ MST_drm_dp_topology_mgr* topologyManager = &(pD->mstTopMgr);
+
+ DP_MST_MgrDeallocateVcpi(&pD->mstTopMgr, sinkDevice->port);
+
+ uint32_t retVal = DP_MST_MgrUpdatePayloadPart1(topologyManager);
+
+ if (retVal == CDN_EOK) {
+ /* clear slots allocation for stream */
+ retVal = clearSlotAllocation(pD, streamId);
+ }
+
+ if (retVal == CDN_EOK) {
+ retVal = DP_MST_MgrUpdatePayloadPart2(topologyManager);
+ }
+
+ if (retVal == CDN_EOK) {
+ /* clear rate govern configuration */
+ retVal = clearRateGoverning(pD, streamId);
+ }
+
+ if (retVal == CDN_EOK) {
+ /* clear SDP packets from current stream */
+ retVal = clearSdpPackets(pD, streamId);
+ }
+
+ return retVal;
+}
+
+uint32_t DP_MST_SetMstEnable(DP_PrivateData* pD, bool mstEnable)
+{
+ uint32_t retVal;
+ uint32_t reg;
+ DP_RegisterTransfer regTransfer = {0U};
+
+ /* set MST state */
+ retVal = DP_MST_MgrSetState(&pD->mstTopMgr, mstEnable);
+
+ if (retVal != CDN_EOK) {
+ DbgMsg(DBG_GEN_MSG, DBG_CRIT, "MST set state to %d failed\n", mstEnable);
+ }
+
+ if (retVal == CDN_EOK) {
+ /* read global configuration for framer */
+ regTransfer.addr = offsetof(MHDP_ApbRegs, mhdp_apb_regs.DP_FRAMER_GLOBAL_CONFIG_p);
+ retVal = DP_ReadRegister(pD, ®Transfer);
+ }
+
+ if (retVal == CDN_EOK) {
+
+ /* set MST enable/disable */
+ if (!mstEnable) {
+ reg = CPS_FLD_CLEAR(MHDP__MHDP_APB_REGS__DP_FRAMER_GLOBAL_CONFIG_P, MST_SST, regTransfer.val);
+ } else {
+ reg = CPS_FLD_SET(MHDP__MHDP_APB_REGS__DP_FRAMER_GLOBAL_CONFIG_P, MST_SST, regTransfer.val);
+ }
+
+ regTransfer.val = reg;
+ regTransfer.addr = offsetof(MHDP_ApbRegs, mhdp_apb_regs.DP_FRAMER_GLOBAL_CONFIG_p);
+
+ retVal = DP_WriteRegister(pD, ®Transfer);
+ }
+
+ if (retVal == CDN_EOK) {
+ /* set 'mstEnable' flag in private data */
+ pD->mstEnabled = mstEnable;
+ }
+
+ return retVal;
+}
+
+uint32_t DP_MST_SetEncryption(DP_PrivateData* pD, uint8_t streamId, bool enable)
+{
+ uint32_t retVal = CDN_EOK;
+ uint32_t payload_31_0 = 0U;
+ uint32_t payload_63_32 = 0U;
+ MST_drm_dp_payload *payload;
+
+ /* looking for sink device on stream */
+ DP_SinkDevice* sinkDevice = findSinkDevice(pD, streamId);
+
+ if (sinkDevice == NULL) {
+ DbgMsg(DBG_GEN_MSG, DBG_CRIT, "Sink device not exists\n");
+ retVal = CDN_EINVAL;
+ }
+
+ if (retVal == CDN_EOK) {
+ /* get payload for sink */
+ payload = DP_MST_MgrGetPortPayload(&pD->mstTopMgr, sinkDevice->port);
+
+ if (payload == NULL) {
+ DbgMsg(DBG_GEN_MSG, DBG_CRIT, "Payload for given stream not found\n");
+ retVal = CDN_EINVAL;
+ }
+ }
+
+ if (retVal == CDN_EOK) {
+ /* calculate timeslots for payload */
+ retVal = calculateTimeSlotsForPayload(payload, &payload_31_0, &payload_63_32);
+ }
+
+ if (retVal == CDN_EOK) {
+ /* set encryption */
+ retVal = setEncryption(pD, payload_31_0, payload_63_32, enable);
+ }
+
+ return retVal;
+}
+
+uint32_t DP_MST_IsAnyVideoOn(DP_PrivateData* pD, bool *isOn)
+{
+ uint8_t i;
+ uint32_t retVal;
+
+ /* check each stream */
+ for (i = 0U; i < DP_MAX_NUMBER_OF_STREAMS; i++) {
+ retVal = isVideoOn(pD, i, isOn);
+
+ /* break if any stream have video on */
+ if ((retVal != CDN_EOK) || (*isOn)) {
+ break;
+ }
+
+ }
+
+ return retVal;
+}
diff --git a/packages/ti/drv/dss/src/csl/dp/src/dp_mst.h b/packages/ti/drv/dss/src/csl/dp/src/dp_mst.h
--- /dev/null
@@ -0,0 +1,137 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ *
+ * dp_mst.h
+ *
+ ******************************************************************************
+ */
+
+/* parasoft-begin-suppress METRICS-36 "Function called from more then 5 functions in one translation unit" */
+
+#ifndef DP_MST_H
+#define DP_MST_H
+
+#include "cdn_stdtypes.h"
+#include "dp_if.h"
+#include "dp_priv.h"
+
+/*
+ * Set MST (enable = 'true') or SST (enable = 'false') mode
+ * @param[in] pD pointer to private data object
+ * @param[in] enable indicates if mode is SST/MST
+ * @return CDN_EOK if success
+ * @return CDN_EINVAL if input parameters are invaild
+ */
+uint32_t DP_MST_SetMstEnable(DP_PrivateData* pD, bool mstEnable);
+
+/*
+ * Set stream disabled/enabled
+ * @param[in] pD pointer to DP private data object
+ * @param[in] streamId stream number
+ * @param[in] enable indicator if disable/enable stream
+ * @return CDN_EOK if success
+ * @return CDN_EINVAL if input parameters are invaild
+ */
+uint32_t DP_MST_SetStreamEnable(DP_PrivateData* pD, uint8_t streamId, bool streamEnable);
+
+/*
+ * Allocate virtual channel for sink device stream
+ * @param[in] pD pointer to DP private data object
+ * @param[in] streamId stream number
+ * @param[in] sinkDevice pointer to sink device object
+ * @return CDN_EOK if success
+ * @return CDN_EINVAL if failed
+ */
+uint32_t DP_MST_AllocateVcpi(DP_PrivateData *pD, uint8_t streamId, DP_SinkDevice *sinkDevice);
+
+/*
+ * Deallocate virtual channel for sink device stream
+ * @param[in] pD pointer to DP private data object
+ * @param[in] streamId stream number
+ * @param[in] sinkDevice pointer to sink device object
+ * @return CDN_EOK if success
+ * @return CDN_EINVAL if failed
+ */
+uint32_t DP_MST_DeallocateVcpi(DP_PrivateData *pD, uint8_t streamId, DP_SinkDevice *sinkDevice);
+
+/*
+ * Set encryption for MST timeslots
+ * @param[in] pD pointer to DP private data object
+ * @param[in] streamId stream number
+ * @param[in] enable if encyption should be disabled/enabled
+ * @return CDN_EOK if success
+ * @return CDN_EINVAL if failed
+ */
+uint32_t DP_MST_SetEncryption(DP_PrivateData* pD, uint8_t streamId, bool enable);
+
+/*
+ * Check if any stream has video on
+ * @param[in] pD pointer to DP private data object
+ * @param[in] isOn indicator if any video is on
+ * @return CDN_EOK if success
+ * @return CDN_EINVAL if failed
+ */
+uint32_t DP_MST_IsAnyVideoOn(DP_PrivateData* pD, bool *isOn);
+
+/*
+ * Check, if MST feature is enabled and if given stream ID is within number of
+ * streams supported by hardware.
+ * @param[in] pD pointer to DP private data object
+ * @param[in] streamId stream number
+ * @return CDN_EOK if success
+ * @return CDN_ENOTSUP if MST mode is not enabled
+ * @return CDN_EINVAL if streamId is greater than number of streams
+ */
+uint32_t DP_StreamIdMstSanity(const DP_PrivateData* pD, uint8_t streamId);
+
+/*
+ * Check, if given stream ID is valid for current DSC configuration.
+ * @param[in] pD pointer to DP private data object
+ * @param[in] streamId number of stream
+ * @param[in] splitPanel inicator if panel is splitted
+ * @return CDN_EOK if success
+ * @return CDN_EINVAL if stream is not supported
+ */
+uint32_t DP_StreamIdMstSstDscSanity(const DP_PrivateData* pD,
+ uint8_t streamId,
+ bool splitPanel);
+
+/*
+ * Check, if given stream ID is within number of streams supported by hardware.
+ * @param[in] pD pointer to DP private data object
+ * @param[in] streamId stream number
+ * @return CDN_EOK if success
+ * @return CDN_EINVAL if stream is not supported
+ */
+uint32_t DP_StreamIdMstSstSanity(const DP_PrivateData* pD, uint8_t streamId);
+
+#endif
+
+/* parasoft-end-suppress METRICS-36 */
diff --git a/packages/ti/drv/dss/src/csl/dp/src/dp_obj_if.c b/packages/ti/drv/dss/src/csl/dp/src/dp_obj_if.c
--- /dev/null
@@ -0,0 +1,171 @@
+/**********************************************************************
+* Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* 1. Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* 2. Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the distribution.
+* 3. Neither the name of the copyright holder nor the names of its
+* contributors may be used to endorse or promote products derived from
+* this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+**********************************************************************
+* WARNING: This file is auto-generated using api-generator utility.
+* api-generator: 12.03.9e11b77(origin/DRV-3827_extract_sanity_to_c_file)
+* Do not edit it manually.
+**********************************************************************
+* Cadence Core Driver for the Cadence DisplayPort (DP) core. This header
+* file lists the API providing a HAL (hardware abstraction layer)
+* interface for the DP core
+**********************************************************************/
+
+#include "dp_obj_if.h"
+
+/* parasoft suppress item METRICS-41-3 "Number of blocks of comments per statement" */
+
+DP_OBJ *DP_GetInstance(void)
+{
+ static DP_OBJ driver =
+ {
+ .probe = DP_Probe,
+ .init = DP_Init,
+ .isr = DP_Isr,
+ .start = DP_Start,
+ .stop = DP_Stop,
+ .destroy = DP_Destroy,
+ .setPhyPd = DP_SetPhyPd,
+ .loadFirmware = DP_LoadFirmware,
+ .startUcpu = DP_StartUcpu,
+ .checkResponse = DP_CheckResponse,
+ .testEcho = DP_TestEcho,
+ .testEchoExt = DP_TestEchoExt,
+ .getCurVersion = DP_GetCurVersion,
+ .getEvent = DP_GetEvent,
+ .getDebugRegVal = DP_GetDebugRegVal,
+ .checkAlive = DP_CheckAlive,
+ .waitAlive = DP_WaitAlive,
+ .sendMainControlRequest = DP_SendMainControlRequest,
+ .getMainControlResponse = DP_GetMainControlResponse,
+ .mainControl = DP_MainControl,
+ .setClock = DP_SetClock,
+ .setWatchdogConfig = DP_SetWatchdogConfig,
+ .injectEccError = DP_InjectEccError,
+ .forceFatalError = DP_ForceFatalError,
+ .setAudioVideoClkCfg = DP_SetAudioVideoClkCfg,
+ .getAudioVideoClkCfg = DP_GetAudioVideoClkCfg,
+ .setHdcpClockConfig = DP_SetHdcpClockConfig,
+ .getHdcpClockConfig = DP_GetHdcpClockConfig,
+ .configurePhyAuxCtrl = DP_ConfigurePhyAuxCtrl,
+ .configurePhyStartUp = DP_ConfigurePhyStartUp,
+ .sendEdidReadRequest = DP_SendEdidReadRequest,
+ .getEdidReadResponse = DP_GetEdidReadResponse,
+ .readEdid = DP_ReadEdid,
+ .setPowerMode = DP_SetPowerMode,
+ .setSourceCapabilities = DP_SetSourceCapabilities,
+ .getSinkCapabilities = DP_GetSinkCapabilities,
+ .setCustomPattern = DP_SetCustomPattern,
+ .setTestPattern = DP_SetTestPattern,
+ .sendDpcdReadRequest = DP_SendDpcdReadRequest,
+ .getDpcdReadResponse = DP_GetDpcdReadResponse,
+ .readDpcd = DP_ReadDpcd,
+ .SendDpcdWriteRequest = DP_SendDpcdWriteRequest,
+ .GetDpcdWriteResponse = DP_GetDpcdWriteResponse,
+ .writeDpcd = DP_WriteDpcd,
+ .sendI2cReadRequest = DP_SendI2cReadRequest,
+ .getI2cReadResponse = DP_GetI2cReadResponse,
+ .i2cRead = DP_I2cRead,
+ .SendI2cWriteRequest = DP_SendI2cWriteRequest,
+ .GetI2cWriteResponse = DP_GetI2cWriteResponse,
+ .i2cWrite = DP_I2cWrite,
+ .setAssrEnable = DP_SetAssrEnable,
+ .setShortenedAuxPreamble = DP_SetShortenedAuxPreamble,
+ .linkTraining = DP_LinkTraining,
+ .checkLinkStable = DP_CheckLinkStable,
+ .setEventMask = DP_SetEventMask,
+ .getEventMask = DP_GetEventMask,
+ .sendReadHpdEventRequest = DP_SendReadHpdEventRequest,
+ .getReadHpdEventResponse = DP_GetReadHpdEventResponse,
+ .readHpdEvent = DP_ReadHpdEvent,
+ .fillVideoFormat = DP_FillVideoFormat,
+ .setVic = DP_SetVic,
+ .setMsaSyncPolarity = DP_SetMsaSyncPolarity,
+ .setFramerEnable = DP_SetFramerEnable,
+ .setVideoSst = DP_SetVideoSst,
+ .readLinkStat = DP_ReadLinkStat,
+ .sendAuxStatusRequest = DP_SendAuxStatusRequest,
+ .getAuxStatusResponse = DP_GetAuxStatusResponse,
+ .getAuxStatus = DP_GetAuxStatus,
+ .sendI2cStatusRequest = DP_SendI2cStatusRequest,
+ .getI2cStatusResponse = DP_GetI2cStatusResponse,
+ .getI2cStatus = DP_GetI2cStatus,
+ .sendHpdStatusRequest = DP_SendHpdStatusRequest,
+ .getHpdStatusResponse = DP_GetHpdStatusResponse,
+ .getHpdStatus = DP_GetHpdStatus,
+ .setFecEnable = DP_SetFecEnable,
+ .setFecReady = DP_SetFecReady,
+ .setSdp = DP_SetSdp,
+ .removeSdp = DP_RemoveSdp,
+ .configureHdcpTx = DP_ConfigureHdcpTx,
+ .setHdcp2TxPublicKey = DP_SetHdcp2TxPublicKey,
+ .setHdcpKmEncCustomKey = DP_SetHdcpKmEncCustomKey,
+ .setHdcp2DebugRandom = DP_SetHdcp2DebugRandom,
+ .hdcp2RespondKmNotStored = DP_Hdcp2RespondKmNotStored,
+ .hdcp2RespondKmStored = DP_Hdcp2RespondKmStored,
+ .setHdcp1TxKeys = DP_SetHdcp1TxKeys,
+ .setHdcp1RandomAn = DP_SetHdcp1RandomAn,
+ .sendHdcpTxStatusRequest = DP_SendHdcpTxStatusRequest,
+ .getHdcpTxStatusResponse = DP_GetHdcpTxStatusResponse,
+ .getHdcpTxStatus = DP_GetHdcpTxStatus,
+ .sendHdcp2RecvIdRequest = DP_SendHdcp2RecvIdRequest,
+ .getHdcp2RecvIdResponse = DP_GetHdcp2RecvIdResponse,
+ .getHdcp2RecvId = DP_GetHdcp2RecvId,
+ .sendHdcp2PairingDataRequest = DP_SendHdcp2PairingDataRequest,
+ .getHdcp2PairingDataResponse = DP_GetHdcp2PairingDataResponse,
+ .getHdcp2PairingData = DP_GetHdcp2PairingData,
+ .sendHdcpRecvIdListRequest = DP_SendHdcpRecvIdListRequest,
+ .getHdcpRecvIdListResponse = DP_GetHdcpRecvIdListResponse,
+ .getHdcpRecvIdList = DP_GetHdcpRecvIdList,
+ .setHdcpRecvValid = DP_SetHdcpRecvValid,
+ .setHdcp2Lc = DP_SetHdcp2Lc,
+ .setHdcpSeed = DP_SetHdcpSeed,
+ .audioSetMute = DP_AudioSetMute,
+ .audioAutoConfig = DP_AudioAutoConfig,
+ .audioStop = DP_AudioStop,
+ .audioSetMode = DP_AudioSetMode,
+ .setDscConfig = DP_SetDscConfig,
+ .getDscConfig = DP_GetDscConfig,
+ .dscSendPps = DP_DscSendPps,
+ .setCompressedStreamFlag = DP_SetCompressedStreamFlag,
+ .dscReset = DP_DscReset,
+ .MstEnable = DP_MstEnable,
+ .MstDisable = DP_MstDisable,
+ .MstStreamEnable = DP_MstStreamEnable,
+ .MstStreamDisable = DP_MstStreamDisable,
+ .MstAllocateVcpi = DP_MstAllocateVcpi,
+ .MstDeallocateVcpi = DP_MstDeallocateVcpi,
+ .MstGetSinkCount = DP_MstGetSinkCount,
+ .MstGetSinkList = DP_MstGetSinkList,
+ .MstSetEncryptionEnable = DP_MstSetEncryptionEnable,
+ .MstSetEncryption = DP_MstSetEncryption,
+ .MstScanTopology = DP_MstScanTopology,
+ .MstReadRemoteEdid = DP_MstReadRemoteEdid,
+ .MstHpdIrq = DP_MstHpdIrq,
+ };
+
+ return &driver;
+}
diff --git a/packages/ti/drv/dss/src/csl/dp/src/dp_priv.h b/packages/ti/drv/dss/src/csl/dp/src/dp_priv.h
--- /dev/null
@@ -0,0 +1,424 @@
+/**********************************************************************
+* Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* 1. Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* 2. Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the distribution.
+* 3. Neither the name of the copyright holder nor the names of its
+* contributors may be used to endorse or promote products derived from
+* this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+**********************************************************************
+* WARNING: This file is auto-generated using api-generator utility.
+* api-generator: 12.03.9e11b77(origin/DRV-3827_extract_sanity_to_c_file)
+* Do not edit it manually.
+**********************************************************************
+* Cadence Core Driver for the Cadence DisplayPort (DP) core. This header
+* file lists the API providing a HAL (hardware abstraction layer)
+* interface for the DP core
+**********************************************************************/
+
+#ifndef DP_PRIV_H
+#define DP_PRIV_H
+
+/* parasoft-begin-suppress MISRA2012-RULE-1_1_a_c90-2 "C90 - limits, DRV-3906" */
+/* parasoft-begin-suppress MISRA2012-RULE-1_1_b_c90-2 "C90 - limits, DRV-3906" */
+/* parasoft suppress item MISRA2012-DIR-4_8 "Consider hiding implementation of structure" */
+
+#include "dp_if.h"
+#include "dp_mst_if.h"
+#include "dp_mst_structs_if.h"
+#include "dp_sd0801_structs_if.h"
+#include "dp_sideband_msg_if.h"
+#include "dp_sideband_msg_structs_if.h"
+#include "dp_structs_if.h"
+
+/** @defgroup ConfigInfo Configuration and Hardware Operation Information
+ * The following definitions specify the driver operation environment that
+ * is defined by hardware configuration or client code. These defines are
+ * located in the header file of the core driver.
+ * @{
+ */
+
+/**********************************************************************
+* Defines
+**********************************************************************/
+/** Used to enable/disable HPD events */
+#define DP_HPD_EVENT_ENABLE_BIT (1U)
+
+#define DP_LINK_TRAINING_CR_DELAY_US 100U
+
+#define DP_FAST_LINK_TRAINING_DELAY_US 500U
+
+/** relative to 0x0000 or 0x2200 */
+#define DP_TRAINING_AUX_RD_INTERVAL_OFF 0x0EU
+
+#define DP_TRAINING_AUX_RD_INTERVAL_MASK 0x7FU
+
+#define DP_EXT_RECV_CAP_FIELD_PRESENT_MASK 0x80U
+
+/** relative to 0x0000 or 0x2200 */
+#define DP_MAX_LINK_RATE_OFF 0x01U
+
+/** relative to 0x0000 or 0x2200 */
+#define DP_MAX_LANE_COUNT_OFF 0x02U
+
+#define DP_MAX_LANE_COUNT_MASK 0x0FU
+
+#define DP_TPS3_SUPPORTED_MASK 0x40U
+
+#define DP_ENHANCED_FRAME_CAP_MASK 0x80U
+
+/** relative to 0x0000 or 0x2200 */
+#define DP_MAX_DOWNSPREAD_OFF 0x03U
+
+#define DP_MAX_DOWNSPREAD_MASK 0x01U
+
+#define DP_NO_AUX_TRAINING_MASK 0x40U
+
+#define DP_TPS4_SUPPORTED_MASK 0x80U
+
+/** relative to 0x0000 or 0x2200 */
+#define DP_ML_CODING_OFF 0x06U
+
+#define DP_CAPABLE_8B10B_MASK 0x01U
+
+/** relative to 0x0000 or 0x2200 */
+#define DP_EDP_CONF_CAP_OFF 0x0DU
+
+#define DP_ASSR_CAP_MASK 0x01U
+
+#define DP_SPREAD_AMP_MASK 0x10U
+
+#define DP_SET_8B_10B_MASK 0x01U
+
+#define DP_VOLTAGE_SWING_MASK 0x03U
+
+#define DP_MAX_SWING_REACHED_MASK 0x04U
+
+#define DP_PREEMPHASIS_SET_SHIFT 3U
+
+#define DP_PREEMPHASIS_SET_MASK 0x18U
+
+#define DP_MAX_PREEMPHASIS_REACHED_MASK 0x20U
+
+#define DP_LANE_CR_DONE_MASK 0x01U
+
+#define DP_LANE_EQ_DONE_MASK 0x02U
+
+#define DP_LANE_SYMBOL_LOCKED_MASK 0x04U
+
+#define DP_LANE_STATUS_ODD_LANE_SHIFT 4U
+
+#define DP_INTERLANE_ALIGN_DONE_MASK 0x01U
+
+#define DP_VOLTAGE_SWING_ADJ_MASK 0x03U
+
+#define DP_PREEEMPHASIS_ADJ_SHIFT 2U
+
+#define DP_PREEEMPHASIS_ADJ_MASK 0x0CU
+
+#define DP_LANE_COUNT_SET_MASK 0x1FU
+
+#define DP_ENHANCED_FRAME_EN_MASK 0x80U
+
+#define DP_SCRAMBLING_DISABLE_MASK 0x20U
+
+/** Address of DPCD register for configuring eDP */
+#define DP_EDP_CONF_REG 0x10AU
+
+#define DP_ASSR_ENABLE_MASK 0x01U
+
+#define DP_SCRAMBLER_SEED_REGULAR 0xFFFFU
+
+#define DP_SCRAMBLER_SEED_ALTERNATE 0xFFFEU
+
+/** FEC overhead, in % */
+#define DP_FEC_OVERHEAD 2.4
+
+#define DP_GENERAL_TEST_ECHO_MAX_PAYLOAD (100U)
+
+#define DP_GENERAL_TEST_ECHO_MIN_PAYLOAD (1U)
+
+#define DP_MAX_MAILBOX_PAYLOAD (1019U)
+
+#define DP_HDCP_TX_STATUS_SIZE (5U)
+
+#define DP_IP_PART_NUMBER 0x8546U
+
+#define DP_IP_VERSION 0x2000U
+
+#define DP_AUX_VERSION 0x1000U
+
+#define DP_PHY_VERSION_1100 0x1100U
+
+#define DP_PHY_VERSION_1200 0x1200U
+
+/**
+ * @}
+ */
+
+/** @defgroup DataStructure Dynamic Data Structures
+ * This section defines the data structures used by the driver to provide
+ * hardware information, modification and dynamic operation of the driver.
+ * These data structures are defined in the header file of the core driver
+ * and utilized by the API.
+ * @{
+ */
+
+/**********************************************************************
+* Forward declarations
+**********************************************************************/
+typedef struct DP_DscConfigFull_s DP_DscConfigFull;
+typedef struct DP_HardwareConfig_s DP_HardwareConfig;
+
+/**********************************************************************
+* Structures and unions
+**********************************************************************/
+/** DSC full configuration containing input parameters, calculated parameters and fixed parameters necessary to be put to PPS. Private structure used internally by driver. */
+struct DP_DscConfigFull_s
+{
+ /** Bits / component for previous reconstructed line buffer */
+ uint32_t linebufDepth;
+ /** Bits / component to code */
+ uint32_t bitsPerComponent;
+ /** slice width in pixels */
+ uint32_t sliceWidth;
+ /** slice height in pixels */
+ uint32_t sliceHeight;
+ /** picture width */
+ uint32_t picWidth;
+ /** picture height */
+ uint32_t picHeight;
+ /** Offset to bits/group used by RC to determine QP adjustment */
+ uint32_t rcTgtOffsetHi;
+ /** Offset to bits/group used by RC to determine QP adjustment */
+ uint32_t rcTgtOffsetLo;
+ /** Bits/pixel target << 4 (ie., 4 fractional bits) */
+ uint32_t bitsPerPixel;
+ /** Factor to determine if an edge is present based on the bits produced */
+ uint32_t rcEdgeFactor;
+ /** Slow down incrementing once the range reaches this value */
+ uint32_t rcQuantIncrLimit1;
+ /** Slow down incrementing once the range reaches this value */
+ uint32_t rcQuantIncrLimit0;
+ /** Number of pixels to delay the initial transmission */
+ uint32_t initialXmitDelay;
+ /** Block prediction range (in pixels) */
+ uint32_t blockPredEnable;
+ /** Value to use for RC model offset at slice start */
+ uint32_t initialOffset;
+ /** Thresholds defining each of the buffer ranges */
+ uint32_t rcBufThresh[DP_DSC_NUM_BUF_RANGES - 1U];
+ /** Parameters for each of the RC ranges */
+ DP_DscRangeCfg rcRangeParameters[DP_DSC_NUM_BUF_RANGES];
+ /** Total size of RC model */
+ uint32_t rcModelSize;
+ /** Minimum QP where flatness information is sent */
+ uint32_t flatnessMinQp;
+ /** Maximum QP where flatness information is sent */
+ uint32_t flatnessMaxQp;
+ /** Enable on-off VBR (ie., disable stuffing bits) */
+ uint32_t vbrEnable;
+ /** Placeholder for PPS identifier */
+ uint32_t ppsIdentifier;
+ /**
+ * When 'true', both encoders are used in parallel for one video stream (L and R split).
+ * When 'false', one encoder is used.
+ */
+ bool splitPanel;
+ /** Number of lines to wait before initiating transport in Command Mode */
+ uint32_t initialLines;
+ /** the upstream source timing controller total line time (in clock cycles, not in pixels) */
+ uint32_t hTotal;
+ /** Flatness Detection Threshold */
+ uint32_t flatnessDetThresh;
+ /** Number of pixels to delay the VLD on the decoder, not including SSM */
+ uint32_t initialDecDelay;
+ /** Bits/group offset to use for first line of the slice */
+ uint32_t firstLineBpgOfs;
+ /** Initial value for scale factor */
+ uint32_t initialScaleValue;
+ /** Decrement scale factor every scaleDecrementInterval groups */
+ uint32_t scaleDecrementInterval;
+ /** Increment scale factor every scaleIncrementInterval groups */
+ uint32_t scaleIncrementInterval;
+ /** non-first line BPG offset to uses */
+ uint32_t nflBpgOffset;
+ /** non-second line BPG offset to uses */
+ uint32_t nslBpgOffset;
+ /** BPG offset used to enforce slice bit constraint */
+ uint32_t sliceBpgOffset;
+ /** final RC linear transformation offset value */
+ uint32_t finalOffset;
+ /** The (max) size in bytes of the "chunks" that are used in slice multiplexing */
+ uint32_t chunkSize;
+ /** For 4:2:0, bits/group offset to use for the 2nd line of the slice */
+ uint32_t secondLineBpgOfs;
+ /** DSC minor version */
+ uint32_t dscVersionMinor;
+ /** 4:2:2 simple mode (from PPS, 4:2:2 conversion happens outside of DSC encode/decode algorithm) */
+ uint32_t simple_422;
+ /** 4:2:2 native mode (no conversion is done) */
+ uint32_t native_422;
+ /** 4:2:0 native mode (no conversion is done) */
+ uint32_t native_420;
+ /** Flag indicating to do RGB - YCoCg conversion and back (should be 1 for RGB input) */
+ uint32_t convertRgb;
+ /** Adjustment to offset for 2nd line in 4:2:0 (since chroma has no prediction) */
+ uint32_t secondLineOfsAdj;
+};
+
+/** Hardware configuration parameters. */
+struct DP_HardwareConfig_s
+{
+ /**
+ * Number identifying the IP. Corresponds to Cadence IP Part Number.
+ *
+ */
+ uint32_t ipPartNumber;
+ /**
+ * Number identifying the IP version.
+ *
+ */
+ uint16_t ipVersion;
+ /**
+ * IP Family Code. 0x00: Display TX Controller, 0x01: Display RX Controller
+ *
+ */
+ uint8_t ipFamilyCode;
+ /**
+ * Main configuration type.
+ *
+ */
+ uint8_t mainConfigType;
+ /**
+ * AUX version.
+ *
+ */
+ uint16_t auxVersion;
+ /**
+ * PHY version.
+ *
+ */
+ uint16_t phyVersion;
+ /**
+ * Number identifying AUX type.
+ *
+ */
+ uint16_t auxType;
+ /**
+ * Number identifying PHY type.
+ *
+ */
+ uint16_t phyType;
+ /**
+ * DSC supported.
+ *
+ */
+ bool dscSupport;
+ /**
+ * ASF supported.
+ *
+ */
+ bool asfSupport;
+ /**
+ * Number of video streams.
+ *
+ */
+ uint8_t videoStreams;
+ /**
+ * Number of audio streams.
+ *
+ */
+ uint8_t audioStreams;
+};
+
+/**
+ * Structure contains private data for Core Driver that should not be used by
+ * upper layers. This is not a part of API and manipulation of those data may cause
+ * unpredictable behaviour of Core Driver.
+ */
+struct DP_PrivateData_s
+{
+ /** Base address of the register space. */
+ struct MHDP_ApbRegs_s* regBase;
+ /** Base address of the SAPB (Secure APB) register space. */
+ struct MHDP_ApbRegs_s* regBaseSapb;
+ /** Pointer to PHY driver's private data */
+ DP_SD0801_PrivateData* phyPd;
+ /** Structure to pointers to callback functions. */
+ DP_Callbacks cb;
+ /** buffer for transmitting data to FW via mailbox. */
+ uint8_t txBuffer[1024];
+ /** buffer for receiving data from FW via mailbox. */
+ uint8_t rxBuffer[1024];
+ /** TX iterations */
+ uint32_t txi;
+ /** RX iterations */
+ uint32_t rxi;
+ /** data ready to send */
+ uint8_t txEnable;
+ /** data ready to receive */
+ uint8_t rxEnable;
+ uint8_t running;
+ DP_BusType busType;
+ uint32_t tmp;
+ /** structure used to store capabilities of source (TX) device. */
+ DP_SourceDeviceCapabilities sourceCaps;
+ /** structure used to store capabilities of sink (RX) device. */
+ DP_SinkDeviceCapabilities sinkCaps;
+ /** Indicates (when !=0), if source capabilities are currently stored. */
+ uint8_t sourceCapsStored;
+ /** Indicates (when !=0), if sink capabilities are currently stored. */
+ uint8_t sinkCapsStored;
+ /** structure used to store current link state. */
+ DP_LinkState linkState;
+ /** Last value of register incremented by FW, used to determine, if it's alive */
+ uint8_t lastAlive;
+ /** Current dsc configuration */
+ DP_DscConfigFull dscConfig[DP_NUMBER_OF_DSC_ENCODERS];
+ /** Current video configuration for each of stream */
+ DP_VideoParameters videoParameters[DP_MAX_NUMBER_OF_STREAMS];
+ /** Whether or not FEC is enabled */
+ bool fecEnabled;
+ /** Whether or not MST feature is enabled */
+ bool mstEnabled;
+ /** Whether or not video format-related parameters were set for SST mode. */
+ bool sstVicSet;
+ /** Whether or not particular MST stream is enabled */
+ bool streamEnabled[DP_MAX_NUMBER_OF_STREAMS];
+ /** MST topology manager */
+ MST_drm_dp_topology_mgr mstTopMgr;
+ /** List of connected sink devices */
+ DP_SinkDevice sinkList[DP_MAX_NUMBER_OF_STREAMS];
+ /** SDP packet type */
+ uint8_t sdpPacketType[DP_MAX_NUMBER_OF_STREAMS][DP_MAX_NUMBER_OF_SDPS];
+ /** Hardware configuration parameters structure. */
+ DP_HardwareConfig hwConfig;
+};
+
+/**
+ * @}
+ */
+
+/* parasoft-end-suppress MISRA2012-RULE-1_1_b_c90-2 */
+/* parasoft-end-suppress MISRA2012-RULE-1_1_a_c90-2 */
+
+#endif /* DP_PRIV_H */
diff --git a/packages/ti/drv/dss/src/csl/dp/src/dp_register.c b/packages/ti/drv/dss/src/csl/dp/src/dp_register.c
--- /dev/null
@@ -0,0 +1,187 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ *
+ * dp_register.c
+ *
+ ******************************************************************************
+ */
+
+/* parasoft-begin-suppress METRICS-41-4 "Number of blocks of comments per statement in function" */
+
+#include "dp_register.h"
+#include "dp_if.h"
+#include "dp_priv.h"
+#include "dp_mailbox.h"
+#include "dp_utils.h"
+#include "mhdp_apb_regs.h"
+
+#include "cdn_errno.h"
+#include "cdn_stdtypes.h"
+#include "cps_drv.h"
+
+#include "dp_internal.h"
+
+static void sendReadRegisterRequest(DP_PrivateData* pD, const DP_RegisterTransfer* transfer)
+{
+ messageStart(pD, MB_MODULE_ID_GENERAL, (uint8_t)GENERAL_READ_REGISTER);
+ messageWriteUint32(pD, transfer->addr);
+ messageFinish(pD);
+ messageTransmit(pD, transfer->busType);
+
+}
+
+static uint32_t getReadRegisterResponse(DP_PrivateData* pD, DP_RegisterTransfer* transfer)
+{
+ uint32_t retVal = CDN_EOK;
+ uint32_t readAddr;
+
+ messageReceive(pD, transfer->busType);
+ if (0U == messageHeaderMatches(pD,
+ MB_MODULE_ID_GENERAL,
+ (uint8_t)GENERAL_READ_REGISTER)) {
+ retVal = CDN_ENOEXEC;
+ }
+
+ if (CDN_EOK == retVal) {
+ messageGetHeader(pD, NULL, NULL, NULL);
+ messageReadUint32(pD, &readAddr);
+ messageReadUint32(pD, &(transfer->val));
+
+ if ((readAddr != transfer->addr) || (0U == readAddr)) {
+ retVal = CDN_EIO;
+ }
+ transfer->addr = readAddr;
+ }
+
+ return retVal;
+}
+
+uint32_t DP_ReadRegister(DP_PrivateData* pD,
+ DP_RegisterTransfer* transfer)
+{
+ uint32_t retVal = CDN_EOK;
+
+ if ((NULL == pD) || (NULL == transfer) || (0U == transfer->addr)) {
+ retVal = CDN_EINVAL;
+ }
+
+ if (CDN_EOK == retVal) {
+ sendReadRegisterRequest(pD, transfer);
+ retVal = getReadRegisterResponse(pD, transfer);
+ }
+
+ return retVal;
+}
+
+uint32_t DP_WriteRegister(DP_PrivateData* pD, const DP_RegisterTransfer* transfer)
+{
+ uint32_t retVal = CDN_EOK;
+
+ if ((NULL == pD) || (NULL == transfer) || (0U == transfer->addr)) {
+ retVal = CDN_EINVAL;
+ }
+
+ if (CDN_EOK == retVal) {
+ messageStart(pD, MB_MODULE_ID_GENERAL, (uint8_t)GENERAL_WRITE_REGISTER);
+ messageWriteUint32(pD, transfer->addr);
+ messageWriteUint32(pD, transfer->val);
+ messageFinish(pD);
+ messageTransmit(pD, transfer->busType);
+ }
+
+ return retVal;
+}
+
+uint32_t DP_WriteField(DP_PrivateData* pD, const DP_WriteFieldRequest* request)
+{
+ uint32_t retVal = CDN_EOK;
+
+ if ((NULL == pD) || (NULL == request)) {
+ retVal = CDN_EINVAL;
+ }
+
+ if (CDN_EOK == retVal) {
+ messageStart(pD, MB_MODULE_ID_GENERAL, (uint8_t)GENERAL_WRITE_FIELD);
+ messageWriteUint32(pD, request->addr);
+ messageWriteUint8(pD, request->startBit);
+ messageWriteUint8(pD, request->bitCount);
+ messageWriteUint32(pD, request->val);
+ messageFinish(pD);
+ messageTransmit(pD, DP_BUS_TYPE_APB);
+ }
+
+ return retVal;
+}
+
+uint32_t DP_ReadLocalRegister(DP_PrivateData* pD, DP_RegisterTransfer* transfer)
+{
+ uint32_t retVal = CDN_EOK;
+ MHDP_ApbRegs* regBase;
+ uintptr_t address;
+
+ if ((NULL == pD) || (NULL == transfer)) {
+ retVal = CDN_EINVAL;
+ }
+
+ if (CDN_EOK == retVal) {
+ /* parasoft-begin-suppress MISRA2012-RULE-11_4-4 "Cast pointer to integral and vice-versa" */
+ regBase = selectRegBase(pD, transfer->busType);
+ address = (uintptr_t)regBase + (transfer->addr);
+ transfer->val = CPS_REG_READ((volatile uint32_t*)address);
+ /* parasoft-end-suppress MISRA2012-RULE-11_4-4 */
+ }
+
+ return retVal;
+}
+
+uint32_t DP_WriteLocalRegister(DP_PrivateData* pD, const DP_RegisterTransfer* transfer)
+{
+ uint32_t retVal = CDN_EOK;
+ MHDP_ApbRegs* regBase;
+ uintptr_t address;
+
+ if ((NULL == pD) || (NULL == transfer))
+ {
+ retVal = CDN_EINVAL;
+ }
+
+ if (CDN_EOK == retVal)
+ {
+ /* parasoft-begin-suppress MISRA2012-RULE-11_4-4 "Cast pointer to integral and vice-versa" */
+ regBase = selectRegBase(pD, transfer->busType);
+ address = (uintptr_t)regBase + (transfer->addr);
+ CPS_REG_WRITE((volatile uint32_t*)address, transfer->val);
+ /* parasoft-end-suppress MISRA2012-RULE-11_4-4 */
+ }
+
+ return retVal;
+}
+
+/* parasoft-end-suppress METRICS-41-4 */
diff --git a/packages/ti/drv/dss/src/csl/dp/src/dp_register.h b/packages/ti/drv/dss/src/csl/dp/src/dp_register.h
--- /dev/null
@@ -0,0 +1,123 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ *
+ * dp_register.h
+ *
+ ******************************************************************************
+ */
+
+/* parasoft-begin-suppress MISRA2012-DIR-4_8-4 "Consider hiding of implementation" */
+/* parasoft-begin-suppress METRICS-36-3 "Function is called from 5 different functions, DRV-3823" */
+
+#ifndef DP_REGISTER_H
+#define DP_REGISTER_H
+
+#include "cdn_stdtypes.h"
+#include "dp_if.h"
+#include "dp_priv.h"
+
+/** Structure used for reading/writing registers. */
+struct DP_RegisterTransfer_s
+{
+ /** Address of register to read/write (relative to register base address) */
+ uint32_t addr;
+ /** Value read from / to write to register */
+ uint32_t val;
+ /** Bus Type to use. */
+ DP_BusType busType;
+};
+
+/** Structure with request data for writing register field. */
+struct DP_WriteFieldRequest_s
+{
+ /** Address of register, which contains field to be written. */
+ uint32_t addr;
+ /** Position of first bit of field in the register. */
+ uint8_t startBit;
+ /** Number of bits of the field. */
+ uint8_t bitCount;
+ /** Value to write to field (relative to register's least significant bit, not field's). */
+ uint32_t val;
+};
+
+typedef struct DP_RegisterTransfer_s DP_RegisterTransfer;
+typedef struct DP_WriteFieldRequest_s DP_WriteFieldRequest;
+
+/**
+ * Reads DP controller's register via Firmware.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in,out] transfer Pointer with structure used to read register.
+ * @return CDN_EOK success
+ * @return CDN_ENOEXEC Wrong Module or Operation ID was received in response form FW.
+ * @return CDN_EIO Address of read register does not match request, or is invalid.
+ * @return CDN_EINVAL If pD or transfer pointer is NULL.
+ */
+uint32_t DP_ReadRegister(DP_PrivateData* pD, DP_RegisterTransfer* transfer);
+
+/**
+ * Writes DP controller's register via Firmware.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] transfer Pointer with structure used to write register.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD or transfer pointer is NULL.
+ */
+uint32_t DP_WriteRegister(DP_PrivateData* pD, const DP_RegisterTransfer* transfer);
+
+/**
+ * Writes field of DP controller's register via Firmware.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] request Pointer to structure with register field write request.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD or request pointer is NULL.
+ */
+uint32_t DP_WriteField(DP_PrivateData* pD, const DP_WriteFieldRequest* request);
+
+/**
+ * Reads DP controller's register via APB.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in,out] transfer Pointer with structure used to read register.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD or transfer pointer is NULL.
+ */
+uint32_t DP_ReadLocalRegister(DP_PrivateData* pD, DP_RegisterTransfer* transfer);
+
+/**
+ * Writes DP controller's register via APB.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] transfer Pointer with structure used to write register.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD or transfer pointer is NULL.
+ */
+uint32_t DP_WriteLocalRegister(DP_PrivateData* pD, const DP_RegisterTransfer* transfer);
+
+#endif /* DP_REGISTER_H */
+
+/* parasoft-end-suppress MISRA2012-DIR-4_8-4 */
+/* parasoft-end-suppress METRICS-36-3 */
diff --git a/packages/ti/drv/dss/src/csl/dp/src/dp_sanity.c b/packages/ti/drv/dss/src/csl/dp/src/dp_sanity.c
--- /dev/null
@@ -0,0 +1,2727 @@
+/**********************************************************************
+* Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* 1. Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* 2. Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the distribution.
+* 3. Neither the name of the copyright holder nor the names of its
+* contributors may be used to endorse or promote products derived from
+* this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+**********************************************************************
+* WARNING: This file is auto-generated using api-generator utility.
+* api-generator: 12.03.9e11b77(origin/DRV-3827_extract_sanity_to_c_file)
+* Do not edit it manually.
+**********************************************************************
+* Cadence Core Driver for the Cadence DisplayPort (DP) core. This header
+* file lists the API providing a HAL (hardware abstraction layer)
+* interface for the DP core
+**********************************************************************/
+
+/* parasoft-begin-suppress METRICS-18-3 "Follow the Cyclomatic Complexity limit of 10" */
+/* parasoft-begin-suppress METRICS-36-3 "A function should not be called from more than 5 different functions" */
+/* parasoft-begin-suppress METRICS-39-3 "The value of VOCF metric for a function should not be higher than 4" */
+/* parasoft-begin-suppress METRICS-41-3 "Number of blocks of comments per statement" */
+/* parasoft-begin-suppress MISRA2012-RULE-8_7 "Functions and objects should not be defined with external linkage if they are referenced in only one translation unit" */
+
+/**
+ * This file contains sanity API functions. The purpose of sanity functions
+ * is to check input parameters validity. They take the same parameters as
+ * original API functions and return 0 on success or CDN_EINVAL on wrong parameter
+ * value(s).
+ */
+
+#include "cdn_errno.h"
+#include "cdn_stdtypes.h"
+#include "dp_priv.h"
+#include "dp_sanity.h"
+#include "dp_structs_if.h"
+
+/**
+ * Function to validate struct SourceDeviceCapabilities
+ *
+ * @param[in] obj pointer to struct to be verified
+ * @returns 0 for valid
+ * @returns CDN_EINVAL for invalid
+ */
+uint32_t DP_SourceDeviceCapabilitiesSF(const DP_SourceDeviceCapabilities *obj)
+{
+ uint32_t ret = 0;
+
+ if (obj == NULL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ if (
+ (obj->maxLinkRate != DP_LINK_RATE_1_62) &&
+ (obj->maxLinkRate != DP_LINK_RATE_2_16) &&
+ (obj->maxLinkRate != DP_LINK_RATE_2_43) &&
+ (obj->maxLinkRate != DP_LINK_RATE_2_70) &&
+ (obj->maxLinkRate != DP_LINK_RATE_3_24) &&
+ (obj->maxLinkRate != DP_LINK_RATE_4_32) &&
+ (obj->maxLinkRate != DP_LINK_RATE_5_40) &&
+ (obj->maxLinkRate != DP_LINK_RATE_8_10)
+ )
+ {
+ ret = CDN_EINVAL;
+ }
+ if (obj->maxVoltageSwing > (3U))
+ {
+ ret = CDN_EINVAL;
+ }
+ if (obj->maxPreemphasis > (3U))
+ {
+ ret = CDN_EINVAL;
+ }
+ if (
+ (obj->laneMapping != DP_LANE_MAPPING_SINGLE_REGULAR) &&
+ (obj->laneMapping != DP_LANE_MAPPING_DUAL_LANES_01) &&
+ (obj->laneMapping != DP_LANE_MAPPING_DUAL_LANES_23)
+ )
+ {
+ ret = CDN_EINVAL;
+ }
+ if (
+ (obj->controllersPerPhy != DP_SINGLE_CONTROLLER) &&
+ (obj->controllersPerPhy != DP_DUAL_CONTROLLER)
+ )
+ {
+ ret = CDN_EINVAL;
+ }
+ }
+
+ return ret;
+}
+
+/**
+ * Function to validate struct ReadEdidResponse
+ *
+ * @param[in] obj pointer to struct to be verified
+ * @returns 0 for valid
+ * @returns CDN_EINVAL for invalid
+ */
+uint32_t DP_ReadEdidResponseSF(const DP_ReadEdidResponse *obj)
+{
+ uint32_t ret = 0;
+
+ if (obj == NULL)
+ {
+ ret = CDN_EINVAL;
+ }
+
+ return ret;
+}
+
+/**
+ * Function to validate struct DpcdTransfer
+ *
+ * @param[in] obj pointer to struct to be verified
+ * @returns 0 for valid
+ * @returns CDN_EINVAL for invalid
+ */
+uint32_t DP_DpcdTransferSF(const DP_DpcdTransfer *obj)
+{
+ uint32_t ret = 0;
+
+ if (obj == NULL)
+ {
+ ret = CDN_EINVAL;
+ }
+
+ return ret;
+}
+
+/**
+ * Function to validate struct I2cTransfer
+ *
+ * @param[in] obj pointer to struct to be verified
+ * @returns 0 for valid
+ * @returns CDN_EINVAL for invalid
+ */
+uint32_t DP_I2cTransferSF(const DP_I2cTransfer *obj)
+{
+ uint32_t ret = 0;
+
+ if (obj == NULL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ if (obj->addr > (127U))
+ {
+ ret = CDN_EINVAL;
+ }
+ }
+
+ return ret;
+}
+
+/**
+ * Function to validate struct VideoParameters
+ *
+ * @param[in] obj pointer to struct to be verified
+ * @returns 0 for valid
+ * @returns CDN_EINVAL for invalid
+ */
+uint32_t DP_VideoParametersSF(const DP_VideoParameters *obj)
+{
+ uint32_t ret = 0;
+
+ if (obj == NULL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ if (DP_VideoFormatParamsSF(&obj->vicParams) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ if (
+ (obj->pxEncFormat != DP_PXENC_PXL_RGB) &&
+ (obj->pxEncFormat != DP_PXENC_YCBCR_4_4_4) &&
+ (obj->pxEncFormat != DP_PXENC_YCBCR_4_2_2) &&
+ (obj->pxEncFormat != DP_PXENC_YCBCR_4_2_0) &&
+ (obj->pxEncFormat != DP_PXENC_Y_ONLY)
+ )
+ {
+ ret = CDN_EINVAL;
+ }
+ if (
+ (obj->stereoVidAttr != DP_STEREO_VIDEO_LEFT) &&
+ (obj->stereoVidAttr != DP_STEREO_VIDEO_RIGHT)
+ )
+ {
+ ret = CDN_EINVAL;
+ }
+ if (
+ (obj->btType != DP_BT_601) &&
+ (obj->btType != DP_BT_709)
+ )
+ {
+ ret = CDN_EINVAL;
+ }
+ if (
+ (obj->alignment != DP_ALIGN_MSB) &&
+ (obj->alignment != DP_ALIGN_LSB)
+ )
+ {
+ ret = CDN_EINVAL;
+ }
+ }
+
+ return ret;
+}
+
+/**
+ * Function to validate struct LinkState
+ *
+ * @param[in] obj pointer to struct to be verified
+ * @returns 0 for valid
+ * @returns CDN_EINVAL for invalid
+ */
+uint32_t DP_LinkStateSF(const DP_LinkState *obj)
+{
+ uint32_t ret = 0;
+
+ if (obj == NULL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ if (
+ (obj->linkRate != DP_LINK_RATE_1_62) &&
+ (obj->linkRate != DP_LINK_RATE_2_16) &&
+ (obj->linkRate != DP_LINK_RATE_2_43) &&
+ (obj->linkRate != DP_LINK_RATE_2_70) &&
+ (obj->linkRate != DP_LINK_RATE_3_24) &&
+ (obj->linkRate != DP_LINK_RATE_4_32) &&
+ (obj->linkRate != DP_LINK_RATE_5_40) &&
+ (obj->linkRate != DP_LINK_RATE_8_10)
+ )
+ {
+ ret = CDN_EINVAL;
+ }
+ if (obj->laneCount > ((DP_MAX_NUMBER_OF_LANES)))
+ {
+ ret = CDN_EINVAL;
+ }
+ }
+
+ return ret;
+}
+
+/**
+ * Function to validate struct SdpEntry
+ *
+ * @param[in] obj pointer to struct to be verified
+ * @returns 0 for valid
+ * @returns CDN_EINVAL for invalid
+ */
+uint32_t DP_SdpEntrySF(const DP_SdpEntry *obj)
+{
+ uint32_t ret = 0;
+
+ if (obj == NULL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ if (
+ (obj->activeMode != DP_SDP_ACTIVE_NO_VIDEO) &&
+ (obj->activeMode != DP_SDP_ACTIVE_VIDEO)
+ )
+ {
+ ret = CDN_EINVAL;
+ }
+ }
+
+ return ret;
+}
+
+/**
+ * Function to validate struct HdcpTxConfiguration
+ *
+ * @param[in] obj pointer to struct to be verified
+ * @returns 0 for valid
+ * @returns CDN_EINVAL for invalid
+ */
+uint32_t DP_HdcpTxConfigurationSF(const DP_HdcpTxConfiguration *obj)
+{
+ uint32_t ret = 0;
+
+ if (obj == NULL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ if (
+ (obj->hdcpVerSupport != DP_HDCP_2_SUPPORT) &&
+ (obj->hdcpVerSupport != DP_HDCP_1_SUPPORT) &&
+ (obj->hdcpVerSupport != DP_HDCP_BOTH_SUPPORT)
+ )
+ {
+ ret = CDN_EINVAL;
+ }
+ if (
+ (obj->contentStreamType != DP_TYPE_0_CONTENT_STREAM) &&
+ (obj->contentStreamType != DP_TYPE_1_CONTENT_STREAM)
+ )
+ {
+ ret = CDN_EINVAL;
+ }
+ }
+
+ return ret;
+}
+
+/**
+ * Function to validate struct Hdcp2TxPublicKey
+ *
+ * @param[in] obj pointer to struct to be verified
+ * @returns 0 for valid
+ * @returns CDN_EINVAL for invalid
+ */
+uint32_t DP_Hdcp2TxPublicKeySF(const DP_Hdcp2TxPublicKey *obj)
+{
+ uint32_t ret = 0;
+
+ if (obj == NULL)
+ {
+ ret = CDN_EINVAL;
+ }
+
+ return ret;
+}
+
+/**
+ * Function to validate struct HdcpTxKmEncCustomKey
+ *
+ * @param[in] obj pointer to struct to be verified
+ * @returns 0 for valid
+ * @returns CDN_EINVAL for invalid
+ */
+uint32_t DP_HdcpTxKmEncCustomKeySF(const DP_HdcpTxKmEncCustomKey *obj)
+{
+ uint32_t ret = 0;
+
+ if (obj == NULL)
+ {
+ ret = CDN_EINVAL;
+ }
+
+ return ret;
+}
+
+/**
+ * Function to validate struct HdcpDebugRandomNumbers
+ *
+ * @param[in] obj pointer to struct to be verified
+ * @returns 0 for valid
+ * @returns CDN_EINVAL for invalid
+ */
+uint32_t DP_HdcpDebugRandomNumbersSF(const DP_HdcpDebugRandomNumbers *obj)
+{
+ uint32_t ret = 0;
+
+ if (obj == NULL)
+ {
+ ret = CDN_EINVAL;
+ }
+
+ return ret;
+}
+
+/**
+ * Function to validate struct HdcpPairingData
+ *
+ * @param[in] obj pointer to struct to be verified
+ * @returns 0 for valid
+ * @returns CDN_EINVAL for invalid
+ */
+uint32_t DP_HdcpPairingDataSF(const DP_HdcpPairingData *obj)
+{
+ uint32_t ret = 0;
+
+ if (obj == NULL)
+ {
+ ret = CDN_EINVAL;
+ }
+
+ return ret;
+}
+
+/**
+ * Function to validate struct Hdcp1Keys
+ *
+ * @param[in] obj pointer to struct to be verified
+ * @returns 0 for valid
+ * @returns CDN_EINVAL for invalid
+ */
+uint32_t DP_Hdcp1KeysSF(const DP_Hdcp1Keys *obj)
+{
+ uint32_t ret = 0;
+
+ if (obj == NULL)
+ {
+ ret = CDN_EINVAL;
+ }
+
+ return ret;
+}
+
+/**
+ * Function to validate struct AudioParams
+ *
+ * @param[in] obj pointer to struct to be verified
+ * @returns 0 for valid
+ * @returns CDN_EINVAL for invalid
+ */
+uint32_t DP_AudioParamsSF(const DP_AudioParams *obj)
+{
+ uint32_t ret = 0;
+
+ if (obj == NULL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ if (
+ (obj->freq != DP_AUDIO_FREQ_32) &&
+ (obj->freq != DP_AUDIO_FREQ_48) &&
+ (obj->freq != DP_AUDIO_FREQ_96) &&
+ (obj->freq != DP_AUDIO_FREQ_192) &&
+ (obj->freq != DP_AUDIO_FREQ_44_1) &&
+ (obj->freq != DP_AUDIO_FREQ_88_2) &&
+ (obj->freq != DP_AUDIO_FREQ_176_4)
+ )
+ {
+ ret = CDN_EINVAL;
+ }
+ if (
+ (obj->width != DP_AUDIO_WIDTH_16) &&
+ (obj->width != DP_AUDIO_WIDTH_24) &&
+ (obj->width != DP_AUDIO_WIDTH_32)
+ )
+ {
+ ret = CDN_EINVAL;
+ }
+ }
+
+ return ret;
+}
+
+/**
+ * Function to validate struct DscConfig
+ *
+ * @param[in] obj pointer to struct to be verified
+ * @returns 0 for valid
+ * @returns CDN_EINVAL for invalid
+ */
+uint32_t DP_DscConfigSF(const DP_DscConfig *obj)
+{
+ uint32_t ret = 0;
+
+ if (obj == NULL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ if (
+ (obj->bitsPerComponent != DP_BITS_PER_COMPONENT_8) &&
+ (obj->bitsPerComponent != DP_BITS_PER_COMPONENT_10)
+ )
+ {
+ ret = CDN_EINVAL;
+ }
+ }
+
+ return ret;
+}
+
+/**
+ * Function to validate struct Config
+ *
+ * @param[in] obj pointer to struct to be verified
+ * @returns 0 for valid
+ * @returns CDN_EINVAL for invalid
+ */
+uint32_t DP_ConfigSF(const DP_Config *obj)
+{
+ uint32_t ret = 0;
+
+ if (obj == NULL)
+ {
+ ret = CDN_EINVAL;
+ }
+
+ return ret;
+}
+
+/**
+ * Function to validate struct Callbacks
+ *
+ * @param[in] obj pointer to struct to be verified
+ * @returns 0 for valid
+ * @returns CDN_EINVAL for invalid
+ */
+uint32_t DP_CallbacksSF(const DP_Callbacks *obj)
+{
+ uint32_t ret = 0;
+
+ if (obj == NULL)
+ {
+ ret = CDN_EINVAL;
+ }
+
+ return ret;
+}
+
+/**
+ * Function to validate struct SinkDevice
+ *
+ * @param[in] obj pointer to struct to be verified
+ * @returns 0 for valid
+ * @returns CDN_EINVAL for invalid
+ */
+uint32_t DP_SinkDeviceSF(const DP_SinkDevice *obj)
+{
+ uint32_t ret = 0;
+
+ if (obj == NULL)
+ {
+ ret = CDN_EINVAL;
+ }
+
+ return ret;
+}
+
+/**
+ * Function to validate struct FirmwareImage
+ *
+ * @param[in] obj pointer to struct to be verified
+ * @returns 0 for valid
+ * @returns CDN_EINVAL for invalid
+ */
+uint32_t DP_FirmwareImageSF(const DP_FirmwareImage *obj)
+{
+ uint32_t ret = 0;
+
+ if (obj == NULL)
+ {
+ ret = CDN_EINVAL;
+ }
+
+ return ret;
+}
+
+/**
+ * Function to validate struct UcpuClock
+ *
+ * @param[in] obj pointer to struct to be verified
+ * @returns 0 for valid
+ * @returns CDN_EINVAL for invalid
+ */
+uint32_t DP_UcpuClockSF(const DP_UcpuClock *obj)
+{
+ uint32_t ret = 0;
+
+ if (obj == NULL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ if (obj->mhz < (1U))
+ {
+ ret = CDN_EINVAL;
+ }
+ if (obj->fraction > (99U))
+ {
+ ret = CDN_EINVAL;
+ }
+ }
+
+ return ret;
+}
+
+/**
+ * Function to validate struct AudioVideoClkCfg
+ *
+ * @param[in] obj pointer to struct to be verified
+ * @returns 0 for valid
+ * @returns CDN_EINVAL for invalid
+ */
+uint32_t DP_AudioVideoClkCfgSF(const DP_AudioVideoClkCfg *obj)
+{
+ uint32_t ret = 0;
+
+ if (obj == NULL)
+ {
+ ret = CDN_EINVAL;
+ }
+
+ return ret;
+}
+
+/**
+ * Function to validate struct PrivateData
+ *
+ * @param[in] obj pointer to struct to be verified
+ * @returns 0 for valid
+ * @returns CDN_EINVAL for invalid
+ */
+uint32_t DP_PrivateDataSF(const DP_PrivateData *obj)
+{
+ uint32_t ret = 0;
+
+ if (obj == NULL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ if (
+ (obj->busType != DP_BUS_TYPE_APB) &&
+ (obj->busType != DP_BUS_TYPE_SAPB)
+ )
+ {
+ ret = CDN_EINVAL;
+ }
+ if (DP_SourceDeviceCapabilitiesSF(&obj->sourceCaps) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ if (DP_SinkDeviceCapabilitiesSF(&obj->sinkCaps) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ if (DP_LinkStateSF(&obj->linkState) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ uint32_t idx_videoParameters;
+
+ for (idx_videoParameters = 0; idx_videoParameters < DP_MAX_NUMBER_OF_STREAMS; idx_videoParameters++)
+ {
+ if (DP_VideoParametersSF(&obj->videoParameters[idx_videoParameters]) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ }
+ }
+
+ return ret;
+}
+
+/**
+ * Function to validate struct VideoFormatParams
+ *
+ * @param[in] obj pointer to struct to be verified
+ * @returns 0 for valid
+ * @returns CDN_EINVAL for invalid
+ */
+uint32_t DP_VideoFormatParamsSF(const DP_VideoFormatParams *obj)
+{
+ uint32_t ret = 0;
+
+ if (obj == NULL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ if (
+ (obj->scanMode != DP_SM_PROGRESSIVE) &&
+ (obj->scanMode != DP_SM_INTERLACED)
+ )
+ {
+ ret = CDN_EINVAL;
+ }
+ if (
+ (obj->hSyncPolarity != DP_SP_ACTIVE_LOW) &&
+ (obj->hSyncPolarity != DP_SP_ACTIVE_HIGH)
+ )
+ {
+ ret = CDN_EINVAL;
+ }
+ if (
+ (obj->vSyncPolarity != DP_SP_ACTIVE_LOW) &&
+ (obj->vSyncPolarity != DP_SP_ACTIVE_HIGH)
+ )
+ {
+ ret = CDN_EINVAL;
+ }
+ }
+
+ return ret;
+}
+
+/**
+ * Function to validate struct SinkDeviceCapabilities
+ *
+ * @param[in] obj pointer to struct to be verified
+ * @returns 0 for valid
+ * @returns CDN_EINVAL for invalid
+ */
+uint32_t DP_SinkDeviceCapabilitiesSF(const DP_SinkDeviceCapabilities *obj)
+{
+ uint32_t ret = 0;
+
+ if (obj == NULL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ if (
+ (obj->maxLinkRate != DP_LINK_RATE_1_62) &&
+ (obj->maxLinkRate != DP_LINK_RATE_2_16) &&
+ (obj->maxLinkRate != DP_LINK_RATE_2_43) &&
+ (obj->maxLinkRate != DP_LINK_RATE_2_70) &&
+ (obj->maxLinkRate != DP_LINK_RATE_3_24) &&
+ (obj->maxLinkRate != DP_LINK_RATE_4_32) &&
+ (obj->maxLinkRate != DP_LINK_RATE_5_40) &&
+ (obj->maxLinkRate != DP_LINK_RATE_8_10)
+ )
+ {
+ ret = CDN_EINVAL;
+ }
+ }
+
+ return ret;
+}
+
+/**
+ * A common function to check the validity of API functions with
+ * following parameter types
+ * @param[in] config Proposed driver/hardware configuration.
+ * @param[out] memReq Size of memory, that needs to be allocated (in bytes).
+ * @return 0 success
+ * @return CDN_EINVAL invalid parameters
+ */
+uint32_t DP_SanityFunction1(const DP_Config* config, const uint32_t* memReq)
+{
+ /* Declaring return variable */
+ uint32_t ret = 0;
+
+ if (memReq == NULL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (DP_ConfigSF(config) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ /*
+ * All 'if ... else if' constructs shall be terminated with an 'else' statement
+ * (MISRA2012-RULE-15_7-3)
+ */
+ }
+
+ return ret;
+}
+
+/**
+ * A common function to check the validity of API functions with
+ * following parameter types
+ * @param[in,out] pD Driver state info specific to this instance.
+ * @param[in] config Specifies driver/hardware configuration.
+ * @param[in] callbacks Client-supplied callback functions.
+ * @return 0 success
+ * @return CDN_EINVAL invalid parameters
+ */
+uint32_t DP_SanityFunction2(const DP_PrivateData* pD, const DP_Config* config, const DP_Callbacks* callbacks)
+{
+ /* Declaring return variable */
+ uint32_t ret = 0;
+
+ if (pD == NULL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (DP_ConfigSF(config) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (DP_CallbacksSF(callbacks) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ /*
+ * All 'if ... else if' constructs shall be terminated with an 'else' statement
+ * (MISRA2012-RULE-15_7-3)
+ */
+ }
+
+ return ret;
+}
+
+/**
+ * A common function to check the validity of API functions with
+ * following parameter types
+ * @param[in] pD Driver instance data.
+ * @return 0 success
+ * @return CDN_EINVAL invalid parameters
+ */
+uint32_t DP_SanityFunction3(const DP_PrivateData* pD)
+{
+ /* Declaring return variable */
+ uint32_t ret = 0;
+
+ if (DP_PrivateDataSF(pD) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+
+ return ret;
+}
+
+/**
+ * A common function to check the validity of API functions with
+ * following parameter types
+ * @param[in] pD Driver instance data.
+ * @param[out] phyPd Pointer to private data of PHY driver's instance to use.
+ * @return 0 success
+ * @return CDN_EINVAL invalid parameters
+ */
+uint32_t DP_SanityFunction7(const DP_PrivateData* pD, const DP_SD0801_PrivateData* phyPd)
+{
+ /* Declaring return variable */
+ uint32_t ret = 0;
+
+ if (phyPd == NULL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (DP_PrivateDataSF(pD) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ /*
+ * All 'if ... else if' constructs shall be terminated with an 'else' statement
+ * (MISRA2012-RULE-15_7-3)
+ */
+ }
+
+ return ret;
+}
+
+/**
+ * A common function to check the validity of API functions with
+ * following parameter types
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] image Pointer to structure with FW image information.
+ * @return 0 success
+ * @return CDN_EINVAL invalid parameters
+ */
+uint32_t DP_SanityFunction8(const DP_PrivateData* pD, const DP_FirmwareImage* image)
+{
+ /* Declaring return variable */
+ uint32_t ret = 0;
+
+ if (DP_PrivateDataSF(pD) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (DP_FirmwareImageSF(image) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ /*
+ * All 'if ... else if' constructs shall be terminated with an 'else' statement
+ * (MISRA2012-RULE-15_7-3)
+ */
+ }
+
+ return ret;
+}
+
+/**
+ * A common function to check the validity of API functions with
+ * following parameter types
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] awaits Pointer to store flag indicating presence of response.
+ * @param[in] busType
+ * @return 0 success
+ * @return CDN_EINVAL invalid parameters
+ */
+uint32_t DP_SanityFunction10(const DP_PrivateData* pD, const bool* awaits, const DP_BusType busType)
+{
+ /* Declaring return variable */
+ uint32_t ret = 0;
+
+ if (awaits == NULL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (DP_PrivateDataSF(pD) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (
+ (busType != DP_BUS_TYPE_APB) &&
+ (busType != DP_BUS_TYPE_SAPB)
+ )
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ /*
+ * All 'if ... else if' constructs shall be terminated with an 'else' statement
+ * (MISRA2012-RULE-15_7-3)
+ */
+ }
+
+ return ret;
+}
+
+/**
+ * A common function to check the validity of API functions with
+ * following parameter types
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] busType
+ * @return 0 success
+ * @return CDN_EINVAL invalid parameters
+ */
+uint32_t DP_SanityFunction11(const DP_PrivateData* pD, const DP_BusType busType)
+{
+ /* Declaring return variable */
+ uint32_t ret = 0;
+
+ if (DP_PrivateDataSF(pD) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (
+ (busType != DP_BUS_TYPE_APB) &&
+ (busType != DP_BUS_TYPE_SAPB)
+ )
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ /*
+ * All 'if ... else if' constructs shall be terminated with an 'else' statement
+ * (MISRA2012-RULE-15_7-3)
+ */
+ }
+
+ return ret;
+}
+
+/**
+ * A common function to check the validity of API functions with
+ * following parameter types
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] message Pointer to a buffer to send.
+ * @param[out] response Pointer to buffer for receiving msg payload back.
+ * @param[in] messageSize Number of bytes to send and receive.
+ * @param[in] busType
+ * @return 0 success
+ * @return CDN_EINVAL invalid parameters
+ */
+uint32_t DP_SanityFunction12(const DP_PrivateData* pD, const uint8_t* message, const uint8_t* response, const uint16_t messageSize, const DP_BusType busType)
+{
+ /* Declaring return variable */
+ uint32_t ret = 0;
+
+ if (message == NULL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (response == NULL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (DP_PrivateDataSF(pD) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if ((messageSize < ((DP_GENERAL_TEST_ECHO_MIN_PAYLOAD))) || (messageSize > ((DP_GENERAL_TEST_ECHO_MAX_PAYLOAD))))
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (
+ (busType != DP_BUS_TYPE_APB) &&
+ (busType != DP_BUS_TYPE_SAPB)
+ )
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ /*
+ * All 'if ... else if' constructs shall be terminated with an 'else' statement
+ * (MISRA2012-RULE-15_7-3)
+ */
+ }
+
+ return ret;
+}
+
+/**
+ * A common function to check the validity of API functions with
+ * following parameter types
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] ver fw version
+ * @param[out] verlib lib version
+ * @return 0 success
+ * @return CDN_EINVAL invalid parameters
+ */
+uint32_t DP_SanityFunction13(const DP_PrivateData* pD, const uint16_t* ver, const uint16_t* verlib)
+{
+ /* Declaring return variable */
+ uint32_t ret = 0;
+
+ if (ver == NULL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (verlib == NULL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (DP_PrivateDataSF(pD) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ /*
+ * All 'if ... else if' constructs shall be terminated with an 'else' statement
+ * (MISRA2012-RULE-15_7-3)
+ */
+ }
+
+ return ret;
+}
+
+/**
+ * A common function to check the validity of API functions with
+ * following parameter types
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] events pointer to store 32-bit events value
+ * @return 0 success
+ * @return CDN_EINVAL invalid parameters
+ */
+uint32_t DP_SanityFunction14(const DP_PrivateData* pD, const uint32_t* events)
+{
+ /* Declaring return variable */
+ uint32_t ret = 0;
+
+ if (events == NULL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (DP_PrivateDataSF(pD) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ /*
+ * All 'if ... else if' constructs shall be terminated with an 'else' statement
+ * (MISRA2012-RULE-15_7-3)
+ */
+ }
+
+ return ret;
+}
+
+/**
+ * A common function to check the validity of API functions with
+ * following parameter types
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] debug pointer to store 16-bit debug reg value
+ * @return 0 success
+ * @return CDN_EINVAL invalid parameters
+ */
+uint32_t DP_SanityFunction15(const DP_PrivateData* pD, const uint16_t* debug)
+{
+ /* Declaring return variable */
+ uint32_t ret = 0;
+
+ if (debug == NULL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (DP_PrivateDataSF(pD) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ /*
+ * All 'if ... else if' constructs shall be terminated with an 'else' statement
+ * (MISRA2012-RULE-15_7-3)
+ */
+ }
+
+ return ret;
+}
+
+/**
+ * A common function to check the validity of API functions with
+ * following parameter types
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] updated Pointer to store flag, whether (true) or not (false) KEEP_ALIVE register
+ * changed since initialization or last call of this function, whichever
+ * happened later.
+ * @return 0 success
+ * @return CDN_EINVAL invalid parameters
+ */
+uint32_t DP_SanityFunction16(const DP_PrivateData* pD, const bool* updated)
+{
+ /* Declaring return variable */
+ uint32_t ret = 0;
+
+ if (updated == NULL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (DP_PrivateDataSF(pD) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ /*
+ * All 'if ... else if' constructs shall be terminated with an 'else' statement
+ * (MISRA2012-RULE-15_7-3)
+ */
+ }
+
+ return ret;
+}
+
+/**
+ * A common function to check the validity of API functions with
+ * following parameter types
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] resp pointer to store response.
+ * @return 0 success
+ * @return CDN_EINVAL invalid parameters
+ */
+uint32_t DP_SanityFunction19(const DP_PrivateData* pD, const uint8_t* resp)
+{
+ /* Declaring return variable */
+ uint32_t ret = 0;
+
+ if (resp == NULL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (DP_PrivateDataSF(pD) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ /*
+ * All 'if ... else if' constructs shall be terminated with an 'else' statement
+ * (MISRA2012-RULE-15_7-3)
+ */
+ }
+
+ return ret;
+}
+
+/**
+ * A common function to check the validity of API functions with
+ * following parameter types
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] ucpuClock Clock, that Xtensa uCPU is running at.
+ * @return 0 success
+ * @return CDN_EINVAL invalid parameters
+ */
+uint32_t DP_SanityFunction21(const DP_PrivateData* pD, const DP_UcpuClock* ucpuClock)
+{
+ /* Declaring return variable */
+ uint32_t ret = 0;
+
+ if (DP_PrivateDataSF(pD) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (DP_UcpuClockSF(ucpuClock) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ /*
+ * All 'if ... else if' constructs shall be terminated with an 'else' statement
+ * (MISRA2012-RULE-15_7-3)
+ */
+ }
+
+ return ret;
+}
+
+/**
+ * A common function to check the validity of API functions with
+ * following parameter types
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] memType Select memory where shall be injected IRAM or DRAM.
+ * @param[in] errorType Select whether error shall be injected either in data bits or in check bits.
+ * @return 0 success
+ * @return CDN_EINVAL invalid parameters
+ */
+uint32_t DP_SanityFunction23(const DP_PrivateData* pD, const DP_EccErrorMemType memType, const DP_EccErrorType errorType)
+{
+ /* Declaring return variable */
+ uint32_t ret = 0;
+
+ if (DP_PrivateDataSF(pD) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (
+ (memType != DP_ECC_ERROR_MEM_TYPE_IRAM) &&
+ (memType != DP_ECC_ERROR_MEM_TYPE_DRAM)
+ )
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (
+ (errorType != DP_ECC_ERROR_TYPE_DATA) &&
+ (errorType != DP_ECC_ERROR_TYPE_CHECK)
+ )
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ /*
+ * All 'if ... else if' constructs shall be terminated with an 'else' statement
+ * (MISRA2012-RULE-15_7-3)
+ */
+ }
+
+ return ret;
+}
+
+/**
+ * A common function to check the validity of API functions with
+ * following parameter types
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] streamId stream number which should be configured
+ * for SST it should be always 0
+ * for MST proper values are from to DP_MAX_NUMBER_OF_STREAMS - 1
+ * @param[in] audioVideoClkCfg audio video clock configuration to be set
+ * @return 0 success
+ * @return CDN_EINVAL invalid parameters
+ */
+uint32_t DP_SanityFunction25(const DP_PrivateData* pD, const uint8_t streamId, const DP_AudioVideoClkCfg* audioVideoClkCfg)
+{
+ /* Declaring return variable */
+ uint32_t ret = 0;
+
+ if (DP_PrivateDataSF(pD) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (streamId > ((DP_MAX_NUMBER_OF_STREAMS - 1U)))
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (DP_AudioVideoClkCfgSF(audioVideoClkCfg) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ /*
+ * All 'if ... else if' constructs shall be terminated with an 'else' statement
+ * (MISRA2012-RULE-15_7-3)
+ */
+ }
+
+ return ret;
+}
+
+/**
+ * A common function to check the validity of API functions with
+ * following parameter types
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] streamId stream number which should be configured
+ * for SST it should be always 0
+ * for MST proper values are from to DP_MAX_NUMBER_OF_STREAMS - 1
+ * @param[out] audioVideoClkCfg audio video clock configuration to be set
+ * @return 0 success
+ * @return CDN_EINVAL invalid parameters
+ */
+uint32_t DP_SanityFunction26(const DP_PrivateData* pD, const uint8_t streamId, const DP_AudioVideoClkCfg* audioVideoClkCfg)
+{
+ /* Declaring return variable */
+ uint32_t ret = 0;
+
+ if (audioVideoClkCfg == NULL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (DP_PrivateDataSF(pD) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (streamId > ((DP_MAX_NUMBER_OF_STREAMS - 1U)))
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ /*
+ * All 'if ... else if' constructs shall be terminated with an 'else' statement
+ * (MISRA2012-RULE-15_7-3)
+ */
+ }
+
+ return ret;
+}
+
+/**
+ * A common function to check the validity of API functions with
+ * following parameter types
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] linkRate Link rate to initialize PHY with.
+ * @return 0 success
+ * @return CDN_EINVAL invalid parameters
+ */
+uint32_t DP_SanityFunction30(const DP_PrivateData* pD, const DP_LinkRate linkRate)
+{
+ /* Declaring return variable */
+ uint32_t ret = 0;
+
+ if (DP_PrivateDataSF(pD) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (
+ (linkRate != DP_LINK_RATE_1_62) &&
+ (linkRate != DP_LINK_RATE_2_16) &&
+ (linkRate != DP_LINK_RATE_2_43) &&
+ (linkRate != DP_LINK_RATE_2_70) &&
+ (linkRate != DP_LINK_RATE_3_24) &&
+ (linkRate != DP_LINK_RATE_4_32) &&
+ (linkRate != DP_LINK_RATE_5_40) &&
+ (linkRate != DP_LINK_RATE_8_10)
+ )
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ /*
+ * All 'if ... else if' constructs shall be terminated with an 'else' statement
+ * (MISRA2012-RULE-15_7-3)
+ */
+ }
+
+ return ret;
+}
+
+/**
+ * A common function to check the validity of API functions with
+ * following parameter types
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] resp Pointer structure to be filled with response.
+ * @return 0 success
+ * @return CDN_EINVAL invalid parameters
+ */
+uint32_t DP_SanityFunction32(const DP_PrivateData* pD, const DP_ReadEdidResponse* resp)
+{
+ /* Declaring return variable */
+ uint32_t ret = 0;
+
+ if (DP_PrivateDataSF(pD) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (DP_ReadEdidResponseSF(resp) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ /*
+ * All 'if ... else if' constructs shall be terminated with an 'else' statement
+ * (MISRA2012-RULE-15_7-3)
+ */
+ }
+
+ return ret;
+}
+
+/**
+ * A common function to check the validity of API functions with
+ * following parameter types
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] mode Power mode
+ * @return 0 success
+ * @return CDN_EINVAL invalid parameters
+ */
+uint32_t DP_SanityFunction34(const DP_PrivateData* pD, const DP_PwrMode mode)
+{
+ /* Declaring return variable */
+ uint32_t ret = 0;
+
+ if (DP_PrivateDataSF(pD) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (
+ (mode != DP_POWER_NORMAL_OPERATION) &&
+ (mode != DP_POWER_DOWN) &&
+ (mode != DP_POWER_AUX_ONLY)
+ )
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ /*
+ * All 'if ... else if' constructs shall be terminated with an 'else' statement
+ * (MISRA2012-RULE-15_7-3)
+ */
+ }
+
+ return ret;
+}
+
+/**
+ * A common function to check the validity of API functions with
+ * following parameter types
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] caps Pointer to structure with source capabilities.
+ * @return 0 success
+ * @return CDN_EINVAL invalid parameters
+ */
+uint32_t DP_SanityFunction35(const DP_PrivateData* pD, const DP_SourceDeviceCapabilities* caps)
+{
+ /* Declaring return variable */
+ uint32_t ret = 0;
+
+ if (DP_PrivateDataSF(pD) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (DP_SourceDeviceCapabilitiesSF(caps) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ /*
+ * All 'if ... else if' constructs shall be terminated with an 'else' statement
+ * (MISRA2012-RULE-15_7-3)
+ */
+ }
+
+ return ret;
+}
+
+/**
+ * A common function to check the validity of API functions with
+ * following parameter types
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] caps Pointer to structure to be filled with sink capabilities.
+ * @return 0 success
+ * @return CDN_EINVAL invalid parameters
+ */
+uint32_t DP_SanityFunction36(const DP_PrivateData* pD, const DP_SinkDeviceCapabilities* caps)
+{
+ /* Declaring return variable */
+ uint32_t ret = 0;
+
+ if (caps == NULL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (DP_PrivateDataSF(pD) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ /*
+ * All 'if ... else if' constructs shall be terminated with an 'else' statement
+ * (MISRA2012-RULE-15_7-3)
+ */
+ }
+
+ return ret;
+}
+
+/**
+ * A common function to check the validity of API functions with
+ * following parameter types
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] pattern Test pattern to be transmitted. Selecting PATTERN_DISABLE will stop
+ * transmitting test pattern.
+ * @param[in] linkParams Pointer to structure containing main link parameters to be used. If
+ * pattern is PATTERN_DISABLE, main link parameters will not be changed.
+ * @return 0 success
+ * @return CDN_EINVAL invalid parameters
+ */
+uint32_t DP_SanityFunction38(const DP_PrivateData* pD, const DP_TestPattern pattern, const DP_LinkState* linkParams)
+{
+ /* Declaring return variable */
+ uint32_t ret = 0;
+
+ if (DP_PrivateDataSF(pD) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (
+ (pattern != DP_PATTERN_PRBS7) &&
+ (pattern != DP_PATTERN_TPS1) &&
+ (pattern != DP_PATTERN_TPS2) &&
+ (pattern != DP_PATTERN_TPS3) &&
+ (pattern != DP_PATTERN_TPS4) &&
+ (pattern != DP_PATTERN_80_BIT) &&
+ (pattern != DP_PATTERN_D10_2) &&
+ (pattern != DP_PATTERN_SYMBOL_ERM) &&
+ (pattern != DP_PATTERN_CP2520_1) &&
+ (pattern != DP_PATTERN_CP2520_2) &&
+ (pattern != DP_PATTERN_CP2520_3) &&
+ (pattern != DP_PATTERN_DISABLE)
+ )
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (DP_LinkStateSF(linkParams) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ /*
+ * All 'if ... else if' constructs shall be terminated with an 'else' statement
+ * (MISRA2012-RULE-15_7-3)
+ */
+ }
+
+ return ret;
+}
+
+/**
+ * A common function to check the validity of API functions with
+ * following parameter types
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] request Parameters related to DPCD read operation.
+ * @return 0 success
+ * @return CDN_EINVAL invalid parameters
+ */
+uint32_t DP_SanityFunction39(const DP_PrivateData* pD, const DP_DpcdTransfer* request)
+{
+ /* Declaring return variable */
+ uint32_t ret = 0;
+
+ if (DP_PrivateDataSF(pD) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (DP_DpcdTransferSF(request) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ /*
+ * All 'if ... else if' constructs shall be terminated with an 'else' statement
+ * (MISRA2012-RULE-15_7-3)
+ */
+ }
+
+ return ret;
+}
+
+/**
+ * A common function to check the validity of API functions with
+ * following parameter types
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in,out] transfer Pointer with request structure, to be filled with results from the
+ * response. If, as result of an error, more bytes were read, than were
+ * requested, only as many bytes as were requested will be copied to the
+ * buffer, to avoid overflow.
+ * @return 0 success
+ * @return CDN_EINVAL invalid parameters
+ */
+uint32_t DP_SanityFunction40(const DP_PrivateData* pD, const DP_DpcdTransfer* transfer)
+{
+ /* Declaring return variable */
+ uint32_t ret = 0;
+
+ if (transfer == NULL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (DP_PrivateDataSF(pD) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ /*
+ * All 'if ... else if' constructs shall be terminated with an 'else' statement
+ * (MISRA2012-RULE-15_7-3)
+ */
+ }
+
+ return ret;
+}
+
+/**
+ * A common function to check the validity of API functions with
+ * following parameter types
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] request Parameters related to I2C-over-AUX read operation.
+ * @return 0 success
+ * @return CDN_EINVAL invalid parameters
+ */
+uint32_t DP_SanityFunction45(const DP_PrivateData* pD, const DP_I2cTransfer* request)
+{
+ /* Declaring return variable */
+ uint32_t ret = 0;
+
+ if (DP_PrivateDataSF(pD) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (DP_I2cTransferSF(request) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ /*
+ * All 'if ... else if' constructs shall be terminated with an 'else' statement
+ * (MISRA2012-RULE-15_7-3)
+ */
+ }
+
+ return ret;
+}
+
+/**
+ * A common function to check the validity of API functions with
+ * following parameter types
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in,out] transfer Pointer with request structure, to be filled with results from the
+ * response. If, as result of an error, more bytes were read, than were
+ * requested, only as many bytes as were requested will be copied to the
+ * buffer, to avoid overflow.
+ * @return 0 success
+ * @return CDN_EINVAL invalid parameters
+ */
+uint32_t DP_SanityFunction46(const DP_PrivateData* pD, const DP_I2cTransfer* transfer)
+{
+ /* Declaring return variable */
+ uint32_t ret = 0;
+
+ if (transfer == NULL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (DP_PrivateDataSF(pD) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ /*
+ * All 'if ... else if' constructs shall be terminated with an 'else' statement
+ * (MISRA2012-RULE-15_7-3)
+ */
+ }
+
+ return ret;
+}
+
+/**
+ * A common function to check the validity of API functions with
+ * following parameter types
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] resultLt Result of Link Training process, according to TrainingStatus enum.
+ * @return 0 success
+ * @return CDN_EINVAL invalid parameters
+ */
+uint32_t DP_SanityFunction53(const DP_PrivateData* pD, const DP_TrainingStatus* resultLt)
+{
+ /* Declaring return variable */
+ uint32_t ret = 0;
+
+ if (resultLt == NULL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (DP_PrivateDataSF(pD) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ /*
+ * All 'if ... else if' constructs shall be terminated with an 'else' statement
+ * (MISRA2012-RULE-15_7-3)
+ */
+ }
+
+ return ret;
+}
+
+/**
+ * A common function to check the validity of API functions with
+ * following parameter types
+ * @param[out] vicParams Structure with VIC-relared parameters to fill.
+ * @param[in] vicMode VIC mode to take from table and fill into structure.
+ * @return 0 success
+ * @return CDN_EINVAL invalid parameters
+ */
+uint32_t DP_SanityFunction60(const DP_VideoFormatParams* vicParams, const DP_VicModes vicMode)
+{
+ /* Declaring return variable */
+ uint32_t ret = 0;
+
+ if (vicParams == NULL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (
+ (vicMode != DP_VIC_MODE_1_59_94HZ) &&
+ (vicMode != DP_VIC_MODE_1_60HZ) &&
+ (vicMode != DP_VIC_MODE_2_59_94HZ) &&
+ (vicMode != DP_VIC_MODE_2_60HZ) &&
+ (vicMode != DP_VIC_MODE_3_59_94HZ) &&
+ (vicMode != DP_VIC_MODE_3_60HZ) &&
+ (vicMode != DP_VIC_MODE_4_59_94HZ) &&
+ (vicMode != DP_VIC_MODE_4_60HZ) &&
+ (vicMode != DP_VIC_MODE_5_59_94HZ) &&
+ (vicMode != DP_VIC_MODE_5_60HZ) &&
+ (vicMode != DP_VIC_MODE_6_59_94HZ) &&
+ (vicMode != DP_VIC_MODE_6_60HZ) &&
+ (vicMode != DP_VIC_MODE_7_59_94HZ) &&
+ (vicMode != DP_VIC_MODE_7_60HZ) &&
+ (vicMode != DP_VIC_MODE_8_MODE1_59_94HZ) &&
+ (vicMode != DP_VIC_MODE_8_MODE1_60HZ) &&
+ (vicMode != DP_VIC_MODE_8_MODE2_59_94HZ) &&
+ (vicMode != DP_VIC_MODE_8_MODE2_60HZ) &&
+ (vicMode != DP_VIC_MODE_9_MODE1_59_94HZ) &&
+ (vicMode != DP_VIC_MODE_9_MODE1_60HZ) &&
+ (vicMode != DP_VIC_MODE_9_MODE2_59_94HZ) &&
+ (vicMode != DP_VIC_MODE_9_MODE2_60HZ) &&
+ (vicMode != DP_VIC_MODE_10_59_94HZ) &&
+ (vicMode != DP_VIC_MODE_10_60HZ) &&
+ (vicMode != DP_VIC_MODE_11_59_94HZ) &&
+ (vicMode != DP_VIC_MODE_11_60HZ) &&
+ (vicMode != DP_VIC_MODE_12_MODE_1_59_94HZ) &&
+ (vicMode != DP_VIC_MODE_12_MODE_1_60HZ) &&
+ (vicMode != DP_VIC_MODE_12_MODE_2_59_94HZ) &&
+ (vicMode != DP_VIC_MODE_12_MODE_2_60HZ) &&
+ (vicMode != DP_VIC_MODE_13_MODE_1_59_94HZ) &&
+ (vicMode != DP_VIC_MODE_13_MODE_1_60HZ) &&
+ (vicMode != DP_VIC_MODE_13_MODE_2_59_94HZ) &&
+ (vicMode != DP_VIC_MODE_13_MODE_2_60HZ) &&
+ (vicMode != DP_VIC_MODE_14_59_94HZ) &&
+ (vicMode != DP_VIC_MODE_14_60HZ) &&
+ (vicMode != DP_VIC_MODE_15_59_94HZ) &&
+ (vicMode != DP_VIC_MODE_15_60HZ) &&
+ (vicMode != DP_VIC_MODE_16_59_94HZ) &&
+ (vicMode != DP_VIC_MODE_16_60HZ) &&
+ (vicMode != DP_VIC_MODE_17_50HZ) &&
+ (vicMode != DP_VIC_MODE_18_50HZ) &&
+ (vicMode != DP_VIC_MODE_19_50HZ) &&
+ (vicMode != DP_VIC_MODE_20_50HZ) &&
+ (vicMode != DP_VIC_MODE_21_50HZ) &&
+ (vicMode != DP_VIC_MODE_22_50HZ) &&
+ (vicMode != DP_VIC_MODE_23_MODE_1_50HZ) &&
+ (vicMode != DP_VIC_MODE_23_MODE_2_50HZ) &&
+ (vicMode != DP_VIC_MODE_23_MODE_3_50HZ) &&
+ (vicMode != DP_VIC_MODE_24_MODE_1_50HZ) &&
+ (vicMode != DP_VIC_MODE_24_MODE_2_50HZ) &&
+ (vicMode != DP_VIC_MODE_24_MODE_3_50HZ) &&
+ (vicMode != DP_VIC_MODE_25_50HZ) &&
+ (vicMode != DP_VIC_MODE_26_50HZ) &&
+ (vicMode != DP_VIC_MODE_27_MODE_1_50HZ) &&
+ (vicMode != DP_VIC_MODE_27_MODE_2_50HZ) &&
+ (vicMode != DP_VIC_MODE_27_MODE_3_50HZ) &&
+ (vicMode != DP_VIC_MODE_28_MODE_1_50HZ) &&
+ (vicMode != DP_VIC_MODE_28_MODE_2_50HZ) &&
+ (vicMode != DP_VIC_MODE_28_MODE_3_50HZ) &&
+ (vicMode != DP_VIC_MODE_29_50HZ) &&
+ (vicMode != DP_VIC_MODE_30_50HZ) &&
+ (vicMode != DP_VIC_MODE_31_50HZ) &&
+ (vicMode != DP_VIC_MODE_32_23_97HZ) &&
+ (vicMode != DP_VIC_MODE_32_24HZ) &&
+ (vicMode != DP_VIC_MODE_33_25HZ) &&
+ (vicMode != DP_VIC_MODE_34_29_97HZ) &&
+ (vicMode != DP_VIC_MODE_34_30HZ) &&
+ (vicMode != DP_VIC_MODE_35_59_94HZ) &&
+ (vicMode != DP_VIC_MODE_35_60HZ) &&
+ (vicMode != DP_VIC_MODE_36_59_94HZ) &&
+ (vicMode != DP_VIC_MODE_36_60HZ) &&
+ (vicMode != DP_VIC_MODE_37_50HZ) &&
+ (vicMode != DP_VIC_MODE_38_50HZ) &&
+ (vicMode != DP_VIC_MODE_39_50HZ) &&
+ (vicMode != DP_VIC_MODE_40_100HZ) &&
+ (vicMode != DP_VIC_MODE_41_100HZ) &&
+ (vicMode != DP_VIC_MODE_42_100HZ) &&
+ (vicMode != DP_VIC_MODE_43_100HZ) &&
+ (vicMode != DP_VIC_MODE_44_100HZ) &&
+ (vicMode != DP_VIC_MODE_45_100HZ) &&
+ (vicMode != DP_VIC_MODE_46_119_88HZ) &&
+ (vicMode != DP_VIC_MODE_46_120HZ) &&
+ (vicMode != DP_VIC_MODE_47_119_88HZ) &&
+ (vicMode != DP_VIC_MODE_47_120HZ) &&
+ (vicMode != DP_VIC_MODE_48_119_88HZ) &&
+ (vicMode != DP_VIC_MODE_48_120HZ) &&
+ (vicMode != DP_VIC_MODE_49_119_88HZ) &&
+ (vicMode != DP_VIC_MODE_49_120HZ) &&
+ (vicMode != DP_VIC_MODE_50_119_88HZ) &&
+ (vicMode != DP_VIC_MODE_50_120HZ) &&
+ (vicMode != DP_VIC_MODE_51_119_88HZ) &&
+ (vicMode != DP_VIC_MODE_51_120HZ) &&
+ (vicMode != DP_VIC_MODE_52_200HZ) &&
+ (vicMode != DP_VIC_MODE_53_200HZ) &&
+ (vicMode != DP_VIC_MODE_54_200HZ) &&
+ (vicMode != DP_VIC_MODE_55_200HZ) &&
+ (vicMode != DP_VIC_MODE_56_239HZ) &&
+ (vicMode != DP_VIC_MODE_56_240HZ) &&
+ (vicMode != DP_VIC_MODE_57_239HZ) &&
+ (vicMode != DP_VIC_MODE_57_240HZ) &&
+ (vicMode != DP_VIC_MODE_58_239HZ) &&
+ (vicMode != DP_VIC_MODE_58_240HZ) &&
+ (vicMode != DP_VIC_MODE_59_239HZ) &&
+ (vicMode != DP_VIC_MODE_59_240HZ) &&
+ (vicMode != DP_VIC_MODE_60_23_97HZ) &&
+ (vicMode != DP_VIC_MODE_60_24HZ) &&
+ (vicMode != DP_VIC_MODE_61_25HZ) &&
+ (vicMode != DP_VIC_MODE_62_29_97HZ) &&
+ (vicMode != DP_VIC_MODE_62_30HZ) &&
+ (vicMode != DP_VIC_MODE_63_119_88HZ) &&
+ (vicMode != DP_VIC_MODE_63_120HZ) &&
+ (vicMode != DP_VIC_MODE_64_100HZ) &&
+ (vicMode != DP_VIC_MODE_97_60HZ) &&
+ (vicMode != DP_VIC_MODE_VESA_800X600P_60HZ) &&
+ (vicMode != DP_VIC_MODE_VESA_720X400P_70HZ) &&
+ (vicMode != DP_VIC_MODE_VESA_720X400P_88HZ) &&
+ (vicMode != DP_VIC_MODE_VESA_640X480P_60HZ) &&
+ (vicMode != DP_VIC_MODE_VESA_640X480P_67HZ) &&
+ (vicMode != DP_VIC_MODE_VESA_640X480P_72HZ) &&
+ (vicMode != DP_VIC_MODE_VESA_640X480P_75HZ) &&
+ (vicMode != DP_VIC_MODE_VESA_800X600P_56HZ) &&
+ (vicMode != DP_VIC_MODE_VESA_800X600P_72HZ) &&
+ (vicMode != DP_VIC_MODE_VESA_832X624P_75HZ) &&
+ (vicMode != DP_VIC_MODE_VESA_1024X768I_87HZ) &&
+ (vicMode != DP_VIC_MODE_VESA_1024X768P_60HZ) &&
+ (vicMode != DP_VIC_MODE_VESA_1024X768P_72HZ) &&
+ (vicMode != DP_VIC_MODE_VESA_1024X768P_75HZ) &&
+ (vicMode != DP_VIC_MODE_VESA_1280X1024P_75HZ) &&
+ (vicMode != DP_VIC_MODE_VESA_1152X870P_75HZ) &&
+ (vicMode != DP_VIC_MODE_126_60HZ) &&
+ (vicMode != DP_VIC_MODE_DUMMY_1_59_94HZ) &&
+ (vicMode != DP_VIC_MODE_DUMMY_2_59_94HZ) &&
+ (vicMode != DP_VIC_MODE_DUMMY_4_59_94HZ) &&
+ (vicMode != DP_VIC_MODE_DUMMY_14_59_94HZ) &&
+ (vicMode != DP_VIC_MODE_DUMMY_16_59_94HZ) &&
+ (vicMode != DP_VIC_MODE_DUMMY_17_50HZ) &&
+ (vicMode != DP_VIC_MODE_DUMMY_25_50HZ) &&
+ (vicMode != DP_VIC_MODE_DUMMY_28_MODE_1_50HZ) &&
+ (vicMode != DP_VIC_MODE_DUMMY_31_50HZ) &&
+ (vicMode != DP_VIC_MODE_DUMMY_32_23_97HZ) &&
+ (vicMode != DP_VIC_MODE_DUMMY_35_59_94HZ) &&
+ (vicMode != DP_VIC_MODE_DUMMY_47_119_88HZ) &&
+ (vicMode != DP_VIC_MODE_DUMMY_49_119_88HZ) &&
+ (vicMode != DP_VIC_MODE_DUMMY_52_200HZ) &&
+ (vicMode != DP_VIC_MODE_DUMMY_57_239HZ) &&
+ (vicMode != DP_VIC_MODE_DUMMY_58_239HZ) &&
+ (vicMode != DP_VIC_MODE_DUMMY_61_25HZ) &&
+ (vicMode != DP_VIC_MODE_DUMMY_63_119_88HZ) &&
+ (vicMode != DP_VIC_MODE_DUMMY_126_60HZ) &&
+ (vicMode != DP_VIC_MODE_COUNT)
+ )
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ /*
+ * All 'if ... else if' constructs shall be terminated with an 'else' statement
+ * (MISRA2012-RULE-15_7-3)
+ */
+ }
+
+ return ret;
+}
+
+/**
+ * A common function to check the validity of API functions with
+ * following parameter types
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] parameters Structure with video parameters to set.
+ * @return 0 success
+ * @return CDN_EINVAL invalid parameters
+ */
+uint32_t DP_SanityFunction61(const DP_PrivateData* pD, const DP_VideoParameters* parameters)
+{
+ /* Declaring return variable */
+ uint32_t ret = 0;
+
+ if (DP_PrivateDataSF(pD) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (DP_VideoParametersSF(parameters) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ /*
+ * All 'if ... else if' constructs shall be terminated with an 'else' statement
+ * (MISRA2012-RULE-15_7-3)
+ */
+ }
+
+ return ret;
+}
+
+/**
+ * A common function to check the validity of API functions with
+ * following parameter types
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] hSyncPolarity Horizontal sync pulse polarity to set in MSA.
+ * @param[in] vSyncPolarity Vertical sync pulse polarity to set in MSA.
+ * @return 0 success
+ * @return CDN_EINVAL invalid parameters
+ */
+uint32_t DP_SanityFunction62(const DP_PrivateData* pD, const DP_SyncPolarity hSyncPolarity, const DP_SyncPolarity vSyncPolarity)
+{
+ /* Declaring return variable */
+ uint32_t ret = 0;
+
+ if (DP_PrivateDataSF(pD) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (
+ (hSyncPolarity != DP_SP_ACTIVE_LOW) &&
+ (hSyncPolarity != DP_SP_ACTIVE_HIGH)
+ )
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (
+ (vSyncPolarity != DP_SP_ACTIVE_LOW) &&
+ (vSyncPolarity != DP_SP_ACTIVE_HIGH)
+ )
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ /*
+ * All 'if ... else if' constructs shall be terminated with an 'else' statement
+ * (MISRA2012-RULE-15_7-3)
+ */
+ }
+
+ return ret;
+}
+
+/**
+ * A common function to check the validity of API functions with
+ * following parameter types
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] linkState Link State.
+ * @return 0 success
+ * @return CDN_EINVAL invalid parameters
+ */
+uint32_t DP_SanityFunction65(const DP_PrivateData* pD, const DP_LinkState* linkState)
+{
+ /* Declaring return variable */
+ uint32_t ret = 0;
+
+ if (linkState == NULL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (DP_PrivateDataSF(pD) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ /*
+ * All 'if ... else if' constructs shall be terminated with an 'else' statement
+ * (MISRA2012-RULE-15_7-3)
+ */
+ }
+
+ return ret;
+}
+
+/**
+ * A common function to check the validity of API functions with
+ * following parameter types
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] status Latest AUX status
+ * @return 0 success
+ * @return CDN_EINVAL invalid parameters
+ */
+uint32_t DP_SanityFunction67(const DP_PrivateData* pD, const DP_AuxStatus* status)
+{
+ /* Declaring return variable */
+ uint32_t ret = 0;
+
+ if (status == NULL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (DP_PrivateDataSF(pD) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ /*
+ * All 'if ... else if' constructs shall be terminated with an 'else' statement
+ * (MISRA2012-RULE-15_7-3)
+ */
+ }
+
+ return ret;
+}
+
+/**
+ * A common function to check the validity of API functions with
+ * following parameter types
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] status Latest I2C-over-AUX status
+ * @return 0 success
+ * @return CDN_EINVAL invalid parameters
+ */
+uint32_t DP_SanityFunction70(const DP_PrivateData* pD, const DP_I2cStatus* status)
+{
+ /* Declaring return variable */
+ uint32_t ret = 0;
+
+ if (status == NULL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (DP_PrivateDataSF(pD) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ /*
+ * All 'if ... else if' constructs shall be terminated with an 'else' statement
+ * (MISRA2012-RULE-15_7-3)
+ */
+ }
+
+ return ret;
+}
+
+/**
+ * A common function to check the validity of API functions with
+ * following parameter types
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] packetData Data of SDP entry to write
+ * @return 0 success
+ * @return CDN_EINVAL invalid parameters
+ */
+uint32_t DP_SanityFunction77(const DP_PrivateData* pD, const DP_SdpEntry* packetData)
+{
+ /* Declaring return variable */
+ uint32_t ret = 0;
+
+ if (DP_PrivateDataSF(pD) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (DP_SdpEntrySF(packetData) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ /*
+ * All 'if ... else if' constructs shall be terminated with an 'else' statement
+ * (MISRA2012-RULE-15_7-3)
+ */
+ }
+
+ return ret;
+}
+
+/**
+ * A common function to check the validity of API functions with
+ * following parameter types
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] entryID 4 Most significant bits of the packet memory containing SDP to remove
+ * @return 0 success
+ * @return CDN_EINVAL invalid parameters
+ */
+uint32_t DP_SanityFunction78(const DP_PrivateData* pD, const uint8_t entryID)
+{
+ /* Declaring return variable */
+ uint32_t ret = 0;
+
+ if (DP_PrivateDataSF(pD) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (entryID > ((DP_MAX_NUMBER_OF_SDPS - 1U)))
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ /*
+ * All 'if ... else if' constructs shall be terminated with an 'else' statement
+ * (MISRA2012-RULE-15_7-3)
+ */
+ }
+
+ return ret;
+}
+
+/**
+ * A common function to check the validity of API functions with
+ * following parameter types
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] config Pointer to structure with configuration for HDCP transmitter.
+ * @return 0 success
+ * @return CDN_EINVAL invalid parameters
+ */
+uint32_t DP_SanityFunction79(const DP_PrivateData* pD, const DP_HdcpTxConfiguration* config)
+{
+ /* Declaring return variable */
+ uint32_t ret = 0;
+
+ if (DP_PrivateDataSF(pD) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (DP_HdcpTxConfigurationSF(config) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ /*
+ * All 'if ... else if' constructs shall be terminated with an 'else' statement
+ * (MISRA2012-RULE-15_7-3)
+ */
+ }
+
+ return ret;
+}
+
+/**
+ * A common function to check the validity of API functions with
+ * following parameter types
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] key Pointer to structure with HDCP 2.x public key.
+ * @return 0 success
+ * @return CDN_EINVAL invalid parameters
+ */
+uint32_t DP_SanityFunction80(const DP_PrivateData* pD, const DP_Hdcp2TxPublicKey* key)
+{
+ /* Declaring return variable */
+ uint32_t ret = 0;
+
+ if (DP_PrivateDataSF(pD) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (DP_Hdcp2TxPublicKeySF(key) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ /*
+ * All 'if ... else if' constructs shall be terminated with an 'else' statement
+ * (MISRA2012-RULE-15_7-3)
+ */
+ }
+
+ return ret;
+}
+
+/**
+ * A common function to check the validity of API functions with
+ * following parameter types
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] key Pointer to structure with km-key.
+ * @return 0 success
+ * @return CDN_EINVAL invalid parameters
+ */
+uint32_t DP_SanityFunction81(const DP_PrivateData* pD, const DP_HdcpTxKmEncCustomKey* key)
+{
+ /* Declaring return variable */
+ uint32_t ret = 0;
+
+ if (DP_PrivateDataSF(pD) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (DP_HdcpTxKmEncCustomKeySF(key) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ /*
+ * All 'if ... else if' constructs shall be terminated with an 'else' statement
+ * (MISRA2012-RULE-15_7-3)
+ */
+ }
+
+ return ret;
+}
+
+/**
+ * A common function to check the validity of API functions with
+ * following parameter types
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] numbers Pointer to structure with random numbers.
+ * @return 0 success
+ * @return CDN_EINVAL invalid parameters
+ */
+uint32_t DP_SanityFunction82(const DP_PrivateData* pD, const DP_HdcpDebugRandomNumbers* numbers)
+{
+ /* Declaring return variable */
+ uint32_t ret = 0;
+
+ if (DP_PrivateDataSF(pD) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (DP_HdcpDebugRandomNumbersSF(numbers) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ /*
+ * All 'if ... else if' constructs shall be terminated with an 'else' statement
+ * (MISRA2012-RULE-15_7-3)
+ */
+ }
+
+ return ret;
+}
+
+/**
+ * A common function to check the validity of API functions with
+ * following parameter types
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] pairingData Pointer to filled structure containing HDCP 2.x pairing data.
+ * @return 0 success
+ * @return CDN_EINVAL invalid parameters
+ */
+uint32_t DP_SanityFunction84(const DP_PrivateData* pD, const DP_HdcpPairingData* pairingData)
+{
+ /* Declaring return variable */
+ uint32_t ret = 0;
+
+ if (DP_PrivateDataSF(pD) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (DP_HdcpPairingDataSF(pairingData) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ /*
+ * All 'if ... else if' constructs shall be terminated with an 'else' statement
+ * (MISRA2012-RULE-15_7-3)
+ */
+ }
+
+ return ret;
+}
+
+/**
+ * A common function to check the validity of API functions with
+ * following parameter types
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] keySet Pointer to filled structure containing HDCP 1.x Device Key Set.
+ * @return 0 success
+ * @return CDN_EINVAL invalid parameters
+ */
+uint32_t DP_SanityFunction85(const DP_PrivateData* pD, const DP_Hdcp1Keys* keySet)
+{
+ /* Declaring return variable */
+ uint32_t ret = 0;
+
+ if (DP_PrivateDataSF(pD) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (DP_Hdcp1KeysSF(keySet) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ /*
+ * All 'if ... else if' constructs shall be terminated with an 'else' statement
+ * (MISRA2012-RULE-15_7-3)
+ */
+ }
+
+ return ret;
+}
+
+/**
+ * A common function to check the validity of API functions with
+ * following parameter types
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] status Pointer to structure with HDCP TX status, to be filled.
+ * @return 0 success
+ * @return CDN_EINVAL invalid parameters
+ */
+uint32_t DP_SanityFunction88(const DP_PrivateData* pD, const DP_HdcpTxStatus* status)
+{
+ /* Declaring return variable */
+ uint32_t ret = 0;
+
+ if (status == NULL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (DP_PrivateDataSF(pD) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ /*
+ * All 'if ... else if' constructs shall be terminated with an 'else' statement
+ * (MISRA2012-RULE-15_7-3)
+ */
+ }
+
+ return ret;
+}
+
+/**
+ * A common function to check the validity of API functions with
+ * following parameter types
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] pairingData Pointer to structure with HDCP pairing data to be filled.
+ * @return 0 success
+ * @return CDN_EINVAL invalid parameters
+ */
+uint32_t DP_SanityFunction94(const DP_PrivateData* pD, const DP_HdcpPairingData* pairingData)
+{
+ /* Declaring return variable */
+ uint32_t ret = 0;
+
+ if (pairingData == NULL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (DP_PrivateDataSF(pD) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ /*
+ * All 'if ... else if' constructs shall be terminated with an 'else' statement
+ * (MISRA2012-RULE-15_7-3)
+ */
+ }
+
+ return ret;
+}
+
+/**
+ * A common function to check the validity of API functions with
+ * following parameter types
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] list Pointer to structure with list of all receiver IDs, and their count,
+ * to be filled.
+ * @return 0 success
+ * @return CDN_EINVAL invalid parameters
+ */
+uint32_t DP_SanityFunction97(const DP_PrivateData* pD, const DP_HdcpRecvIdList* list)
+{
+ /* Declaring return variable */
+ uint32_t ret = 0;
+
+ if (list == NULL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (DP_PrivateDataSF(pD) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ /*
+ * All 'if ... else if' constructs shall be terminated with an 'else' statement
+ * (MISRA2012-RULE-15_7-3)
+ */
+ }
+
+ return ret;
+}
+
+/**
+ * A common function to check the validity of API functions with
+ * following parameter types
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] muteMode Select mute/unmute.
+ * @return 0 success
+ * @return CDN_EINVAL invalid parameters
+ */
+uint32_t DP_SanityFunction102(const DP_PrivateData* pD, const DP_AudioMuteMode muteMode)
+{
+ /* Declaring return variable */
+ uint32_t ret = 0;
+
+ if (DP_PrivateDataSF(pD) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (
+ (muteMode != DP_AUDIO_MUTE) &&
+ (muteMode != DP_AUDIO_UNMUTE)
+ )
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ /*
+ * All 'if ... else if' constructs shall be terminated with an 'else' statement
+ * (MISRA2012-RULE-15_7-3)
+ */
+ }
+
+ return ret;
+}
+
+/**
+ * A common function to check the validity of API functions with
+ * following parameter types
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] params Parameters to configure audio with.
+ * @return 0 success
+ * @return CDN_EINVAL invalid parameters
+ */
+uint32_t DP_SanityFunction103(const DP_PrivateData* pD, const DP_AudioParams* params)
+{
+ /* Declaring return variable */
+ uint32_t ret = 0;
+
+ if (DP_PrivateDataSF(pD) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (DP_AudioParamsSF(params) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ /*
+ * All 'if ... else if' constructs shall be terminated with an 'else' statement
+ * (MISRA2012-RULE-15_7-3)
+ */
+ }
+
+ return ret;
+}
+
+/**
+ * A common function to check the validity of API functions with
+ * following parameter types
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] mode Audio on/off mode.
+ * @return 0 success
+ * @return CDN_EINVAL invalid parameters
+ */
+uint32_t DP_SanityFunction105(const DP_PrivateData* pD, const DP_AudioMode mode)
+{
+ /* Declaring return variable */
+ uint32_t ret = 0;
+
+ if (DP_PrivateDataSF(pD) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (
+ (mode != DP_AUDIO_MODE_OFF) &&
+ (mode != DP_AUDIO_MODE_ON)
+ )
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ /*
+ * All 'if ... else if' constructs shall be terminated with an 'else' statement
+ * (MISRA2012-RULE-15_7-3)
+ */
+ }
+
+ return ret;
+}
+
+/**
+ * A common function to check the validity of API functions with
+ * following parameter types
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] dscConfig Parameters to configure DSC module
+ * @return 0 success
+ * @return CDN_EINVAL invalid parameters
+ */
+uint32_t DP_SanityFunction106(const DP_PrivateData* pD, const DP_DscConfig* dscConfig)
+{
+ /* Declaring return variable */
+ uint32_t ret = 0;
+
+ if (DP_PrivateDataSF(pD) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (DP_DscConfigSF(dscConfig) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ /*
+ * All 'if ... else if' constructs shall be terminated with an 'else' statement
+ * (MISRA2012-RULE-15_7-3)
+ */
+ }
+
+ return ret;
+}
+
+/**
+ * A common function to check the validity of API functions with
+ * following parameter types
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] dscConfig Parameters current DSC configuration
+ * @return 0 success
+ * @return CDN_EINVAL invalid parameters
+ */
+uint32_t DP_SanityFunction107(const DP_PrivateData* pD, const DP_DscConfig* dscConfig)
+{
+ /* Declaring return variable */
+ uint32_t ret = 0;
+
+ if (dscConfig == NULL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (DP_PrivateDataSF(pD) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ /*
+ * All 'if ... else if' constructs shall be terminated with an 'else' statement
+ * (MISRA2012-RULE-15_7-3)
+ */
+ }
+
+ return ret;
+}
+
+/**
+ * A common function to check the validity of API functions with
+ * following parameter types
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] sinkDevice Sink device associated with stream
+ * @return 0 success
+ * @return CDN_EINVAL invalid parameters
+ */
+uint32_t DP_SanityFunction115(const DP_PrivateData* pD, const DP_SinkDevice* sinkDevice)
+{
+ /* Declaring return variable */
+ uint32_t ret = 0;
+
+ if (DP_PrivateDataSF(pD) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (DP_SinkDeviceSF(sinkDevice) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ /*
+ * All 'if ... else if' constructs shall be terminated with an 'else' statement
+ * (MISRA2012-RULE-15_7-3)
+ */
+ }
+
+ return ret;
+}
+
+/**
+ * A common function to check the validity of API functions with
+ * following parameter types
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] sinkList Array for pointers to sink devices
+ * @return 0 success
+ * @return CDN_EINVAL invalid parameters
+ */
+uint32_t DP_SanityFunction118(const DP_PrivateData* pD, const DP_SinkDevice** sinkList)
+{
+ /* Declaring return variable */
+ uint32_t ret = 0;
+
+ if (sinkList == NULL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (DP_PrivateDataSF(pD) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ /*
+ * All 'if ... else if' constructs shall be terminated with an 'else' statement
+ * (MISRA2012-RULE-15_7-3)
+ */
+ }
+
+ return ret;
+}
+
+/**
+ * A common function to check the validity of API functions with
+ * following parameter types
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] sinkDevice sink device from which EDID shall be read
+ * @param[in] edidResponse Pointer structure to be filled with response
+ * @return 0 success
+ * @return CDN_EINVAL invalid parameters
+ */
+uint32_t DP_SanityFunction122(const DP_PrivateData* pD, const DP_SinkDevice* sinkDevice, const DP_ReadEdidResponse* edidResponse)
+{
+ /* Declaring return variable */
+ uint32_t ret = 0;
+
+ if (DP_PrivateDataSF(pD) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (DP_SinkDeviceSF(sinkDevice) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (DP_ReadEdidResponseSF(edidResponse) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ /*
+ * All 'if ... else if' constructs shall be terminated with an 'else' statement
+ * (MISRA2012-RULE-15_7-3)
+ */
+ }
+
+ return ret;
+}
+
+/* parasoft-end-suppress MISRA2012-RULE-8_7 */
+/* parasoft-end-suppress METRICS-41-3 */
+/* parasoft-end-suppress METRICS-39-3 */
+/* parasoft-end-suppress METRICS-36-3 */
+/* parasoft-end-suppress METRICS-18-3 */
diff --git a/packages/ti/drv/dss/src/csl/dp/src/dp_sanity.h b/packages/ti/drv/dss/src/csl/dp/src/dp_sanity.h
--- /dev/null
@@ -0,0 +1,266 @@
+/**********************************************************************
+* Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* 1. Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* 2. Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the distribution.
+* 3. Neither the name of the copyright holder nor the names of its
+* contributors may be used to endorse or promote products derived from
+* this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+**********************************************************************
+* WARNING: This file is auto-generated using api-generator utility.
+* api-generator: 12.03.9e11b77(origin/DRV-3827_extract_sanity_to_c_file)
+* Do not edit it manually.
+**********************************************************************
+* Cadence Core Driver for the Cadence DisplayPort (DP) core. This header
+* file lists the API providing a HAL (hardware abstraction layer)
+* interface for the DP core
+**********************************************************************/
+
+/* parasoft-begin-suppress METRICS-18-3 "Follow the Cyclomatic Complexity limit of 10" */
+/* parasoft-begin-suppress METRICS-36-3 "A function should not be called from more than 5 different functions" */
+/* parasoft-begin-suppress METRICS-39-3 "The value of VOCF metric for a function should not be higher than 4" */
+/* parasoft-begin-suppress METRICS-41-3 "Number of blocks of comments per statement" */
+/* parasoft-begin-suppress MISRA2012-RULE-8_7 "Functions and objects should not be defined with external linkage if they are referenced in only one translation unit" */
+
+/**
+ * This file contains sanity API functions. The purpose of sanity functions
+ * is to check input parameters validity. They take the same parameters as
+ * original API functions and return 0 on success or CDN_EINVAL on wrong parameter
+ * value(s).
+ */
+
+#ifndef DP_SANITY_H
+#define DP_SANITY_H
+
+#include "cdn_errno.h"
+#include "cdn_stdtypes.h"
+#include "dp_if.h"
+
+uint32_t DP_AudioParamsSF(const DP_AudioParams *obj);
+uint32_t DP_AudioVideoClkCfgSF(const DP_AudioVideoClkCfg *obj);
+uint32_t DP_CallbacksSF(const DP_Callbacks *obj);
+uint32_t DP_ConfigSF(const DP_Config *obj);
+uint32_t DP_DpcdTransferSF(const DP_DpcdTransfer *obj);
+uint32_t DP_DscConfigSF(const DP_DscConfig *obj);
+uint32_t DP_FirmwareImageSF(const DP_FirmwareImage *obj);
+uint32_t DP_Hdcp1KeysSF(const DP_Hdcp1Keys *obj);
+uint32_t DP_Hdcp2TxPublicKeySF(const DP_Hdcp2TxPublicKey *obj);
+uint32_t DP_HdcpDebugRandomNumbersSF(const DP_HdcpDebugRandomNumbers *obj);
+uint32_t DP_HdcpPairingDataSF(const DP_HdcpPairingData *obj);
+uint32_t DP_HdcpTxConfigurationSF(const DP_HdcpTxConfiguration *obj);
+uint32_t DP_HdcpTxKmEncCustomKeySF(const DP_HdcpTxKmEncCustomKey *obj);
+uint32_t DP_I2cTransferSF(const DP_I2cTransfer *obj);
+uint32_t DP_LinkStateSF(const DP_LinkState *obj);
+uint32_t DP_PrivateDataSF(const DP_PrivateData *obj);
+uint32_t DP_ReadEdidResponseSF(const DP_ReadEdidResponse *obj);
+uint32_t DP_SdpEntrySF(const DP_SdpEntry *obj);
+uint32_t DP_SinkDeviceCapabilitiesSF(const DP_SinkDeviceCapabilities *obj);
+uint32_t DP_SinkDeviceSF(const DP_SinkDevice *obj);
+uint32_t DP_SourceDeviceCapabilitiesSF(const DP_SourceDeviceCapabilities *obj);
+uint32_t DP_UcpuClockSF(const DP_UcpuClock *obj);
+uint32_t DP_VideoFormatParamsSF(const DP_VideoFormatParams *obj);
+uint32_t DP_VideoParametersSF(const DP_VideoParameters *obj);
+
+uint32_t DP_SanityFunction1(const DP_Config* config, const uint32_t* memReq);
+uint32_t DP_SanityFunction2(const DP_PrivateData* pD, const DP_Config* config, const DP_Callbacks* callbacks);
+uint32_t DP_SanityFunction3(const DP_PrivateData* pD);
+uint32_t DP_SanityFunction7(const DP_PrivateData* pD, const DP_SD0801_PrivateData* phyPd);
+uint32_t DP_SanityFunction8(const DP_PrivateData* pD, const DP_FirmwareImage* image);
+uint32_t DP_SanityFunction10(const DP_PrivateData* pD, const bool* awaits, const DP_BusType busType);
+uint32_t DP_SanityFunction11(const DP_PrivateData* pD, const DP_BusType busType);
+uint32_t DP_SanityFunction12(const DP_PrivateData* pD, const uint8_t* message, const uint8_t* response, const uint16_t messageSize, const DP_BusType busType);
+uint32_t DP_SanityFunction13(const DP_PrivateData* pD, const uint16_t* ver, const uint16_t* verlib);
+uint32_t DP_SanityFunction14(const DP_PrivateData* pD, const uint32_t* events);
+uint32_t DP_SanityFunction15(const DP_PrivateData* pD, const uint16_t* debug);
+uint32_t DP_SanityFunction16(const DP_PrivateData* pD, const bool* updated);
+uint32_t DP_SanityFunction19(const DP_PrivateData* pD, const uint8_t* resp);
+uint32_t DP_SanityFunction21(const DP_PrivateData* pD, const DP_UcpuClock* ucpuClock);
+uint32_t DP_SanityFunction23(const DP_PrivateData* pD, const DP_EccErrorMemType memType, const DP_EccErrorType errorType);
+uint32_t DP_SanityFunction25(const DP_PrivateData* pD, const uint8_t streamId, const DP_AudioVideoClkCfg* audioVideoClkCfg);
+uint32_t DP_SanityFunction26(const DP_PrivateData* pD, const uint8_t streamId, const DP_AudioVideoClkCfg* audioVideoClkCfg);
+uint32_t DP_SanityFunction30(const DP_PrivateData* pD, const DP_LinkRate linkRate);
+uint32_t DP_SanityFunction32(const DP_PrivateData* pD, const DP_ReadEdidResponse* resp);
+uint32_t DP_SanityFunction34(const DP_PrivateData* pD, const DP_PwrMode mode);
+uint32_t DP_SanityFunction35(const DP_PrivateData* pD, const DP_SourceDeviceCapabilities* caps);
+uint32_t DP_SanityFunction36(const DP_PrivateData* pD, const DP_SinkDeviceCapabilities* caps);
+uint32_t DP_SanityFunction38(const DP_PrivateData* pD, const DP_TestPattern pattern, const DP_LinkState* linkParams);
+uint32_t DP_SanityFunction39(const DP_PrivateData* pD, const DP_DpcdTransfer* request);
+uint32_t DP_SanityFunction40(const DP_PrivateData* pD, const DP_DpcdTransfer* transfer);
+uint32_t DP_SanityFunction45(const DP_PrivateData* pD, const DP_I2cTransfer* request);
+uint32_t DP_SanityFunction46(const DP_PrivateData* pD, const DP_I2cTransfer* transfer);
+uint32_t DP_SanityFunction53(const DP_PrivateData* pD, const DP_TrainingStatus* resultLt);
+uint32_t DP_SanityFunction60(const DP_VideoFormatParams* vicParams, const DP_VicModes vicMode);
+uint32_t DP_SanityFunction61(const DP_PrivateData* pD, const DP_VideoParameters* parameters);
+uint32_t DP_SanityFunction62(const DP_PrivateData* pD, const DP_SyncPolarity hSyncPolarity, const DP_SyncPolarity vSyncPolarity);
+uint32_t DP_SanityFunction65(const DP_PrivateData* pD, const DP_LinkState* linkState);
+uint32_t DP_SanityFunction67(const DP_PrivateData* pD, const DP_AuxStatus* status);
+uint32_t DP_SanityFunction70(const DP_PrivateData* pD, const DP_I2cStatus* status);
+uint32_t DP_SanityFunction77(const DP_PrivateData* pD, const DP_SdpEntry* packetData);
+uint32_t DP_SanityFunction78(const DP_PrivateData* pD, const uint8_t entryID);
+uint32_t DP_SanityFunction79(const DP_PrivateData* pD, const DP_HdcpTxConfiguration* config);
+uint32_t DP_SanityFunction80(const DP_PrivateData* pD, const DP_Hdcp2TxPublicKey* key);
+uint32_t DP_SanityFunction81(const DP_PrivateData* pD, const DP_HdcpTxKmEncCustomKey* key);
+uint32_t DP_SanityFunction82(const DP_PrivateData* pD, const DP_HdcpDebugRandomNumbers* numbers);
+uint32_t DP_SanityFunction84(const DP_PrivateData* pD, const DP_HdcpPairingData* pairingData);
+uint32_t DP_SanityFunction85(const DP_PrivateData* pD, const DP_Hdcp1Keys* keySet);
+uint32_t DP_SanityFunction88(const DP_PrivateData* pD, const DP_HdcpTxStatus* status);
+uint32_t DP_SanityFunction94(const DP_PrivateData* pD, const DP_HdcpPairingData* pairingData);
+uint32_t DP_SanityFunction97(const DP_PrivateData* pD, const DP_HdcpRecvIdList* list);
+uint32_t DP_SanityFunction102(const DP_PrivateData* pD, const DP_AudioMuteMode muteMode);
+uint32_t DP_SanityFunction103(const DP_PrivateData* pD, const DP_AudioParams* params);
+uint32_t DP_SanityFunction105(const DP_PrivateData* pD, const DP_AudioMode mode);
+uint32_t DP_SanityFunction106(const DP_PrivateData* pD, const DP_DscConfig* dscConfig);
+uint32_t DP_SanityFunction107(const DP_PrivateData* pD, const DP_DscConfig* dscConfig);
+uint32_t DP_SanityFunction115(const DP_PrivateData* pD, const DP_SinkDevice* sinkDevice);
+uint32_t DP_SanityFunction118(const DP_PrivateData* pD, const DP_SinkDevice** sinkList);
+uint32_t DP_SanityFunction122(const DP_PrivateData* pD, const DP_SinkDevice* sinkDevice, const DP_ReadEdidResponse* edidResponse);
+
+#define DP_ProbeSF DP_SanityFunction1
+#define DP_InitSF DP_SanityFunction2
+#define DP_IsrSF DP_SanityFunction3
+#define DP_StartSF DP_SanityFunction3
+#define DP_StopSF DP_SanityFunction3
+#define DP_DestroySF DP_SanityFunction3
+#define DP_SetPhyPdSF DP_SanityFunction7
+#define DP_LoadFirmwareSF DP_SanityFunction8
+#define DP_StartUcpuSF DP_SanityFunction3
+#define DP_CheckResponseSF DP_SanityFunction10
+#define DP_TestEchoSF DP_SanityFunction11
+#define DP_TestEchoExtSF DP_SanityFunction12
+#define DP_GetCurVersionSF DP_SanityFunction13
+#define DP_GetEventSF DP_SanityFunction14
+#define DP_GetDebugRegValSF DP_SanityFunction15
+#define DP_CheckAliveSF DP_SanityFunction16
+#define DP_WaitAliveSF DP_SanityFunction3
+#define DP_SendMainControlRequestSF DP_SanityFunction3
+#define DP_GetMainControlResponseSF DP_SanityFunction19
+#define DP_MainControlSF DP_SanityFunction19
+#define DP_SetClockSF DP_SanityFunction21
+#define DP_SetWatchdogConfigSF DP_SanityFunction3
+#define DP_InjectEccErrorSF DP_SanityFunction23
+#define DP_ForceFatalErrorSF DP_SanityFunction3
+#define DP_SetAudioVideoClkCfgSF DP_SanityFunction25
+#define DP_GetAudioVideoClkCfgSF DP_SanityFunction26
+#define DP_SetHdcpClockConfigSF DP_SanityFunction3
+#define DP_GetHdcpClockConfigSF DP_SanityFunction16
+#define DP_ConfigurePhyAuxCtrlSF DP_SanityFunction3
+#define DP_ConfigurePhyStartUpSF DP_SanityFunction30
+#define DP_SendEdidReadRequestSF DP_SanityFunction3
+#define DP_GetEdidReadResponseSF DP_SanityFunction32
+#define DP_ReadEdidSF DP_SanityFunction32
+#define DP_SetPowerModeSF DP_SanityFunction34
+#define DP_SetSourceCapabilitiesSF DP_SanityFunction35
+#define DP_GetSinkCapabilitiesSF DP_SanityFunction36
+#define DP_SetCustomPatternSF DP_SanityFunction3
+#define DP_SetTestPatternSF DP_SanityFunction38
+#define DP_SendDpcdReadRequestSF DP_SanityFunction39
+#define DP_GetDpcdReadResponseSF DP_SanityFunction40
+#define DP_ReadDpcdSF DP_SanityFunction40
+#define DP_SendDpcdWriteRequestSF DP_SanityFunction39
+#define DP_GetDpcdWriteResponseSF DP_SanityFunction40
+#define DP_WriteDpcdSF DP_SanityFunction40
+#define DP_SendI2cReadRequestSF DP_SanityFunction45
+#define DP_GetI2cReadResponseSF DP_SanityFunction46
+#define DP_I2cReadSF DP_SanityFunction46
+#define DP_SendI2cWriteRequestSF DP_SanityFunction45
+#define DP_GetI2cWriteResponseSF DP_SanityFunction46
+#define DP_I2cWriteSF DP_SanityFunction46
+#define DP_SetAssrEnableSF DP_SanityFunction3
+#define DP_SetShortenedAuxPreambleSF DP_SanityFunction3
+#define DP_LinkTrainingSF DP_SanityFunction53
+#define DP_CheckLinkStableSF DP_SanityFunction16
+#define DP_SetEventMaskSF DP_SanityFunction3
+#define DP_GetEventMaskSF DP_SanityFunction14
+#define DP_SendReadHpdEventRequestSF DP_SanityFunction3
+#define DP_GetReadHpdEventResponseSF DP_SanityFunction19
+#define DP_ReadHpdEventSF DP_SanityFunction19
+#define DP_FillVideoFormatSF DP_SanityFunction60
+#define DP_SetVicSF DP_SanityFunction61
+#define DP_SetMsaSyncPolaritySF DP_SanityFunction62
+#define DP_SetFramerEnableSF DP_SanityFunction3
+#define DP_SetVideoSstSF DP_SanityFunction3
+#define DP_ReadLinkStatSF DP_SanityFunction65
+#define DP_SendAuxStatusRequestSF DP_SanityFunction3
+#define DP_GetAuxStatusResponseSF DP_SanityFunction67
+#define DP_GetAuxStatusSF DP_SanityFunction67
+#define DP_SendI2cStatusRequestSF DP_SanityFunction3
+#define DP_GetI2cStatusResponseSF DP_SanityFunction70
+#define DP_GetI2cStatusSF DP_SanityFunction70
+#define DP_SendHpdStatusRequestSF DP_SanityFunction3
+#define DP_GetHpdStatusResponseSF DP_SanityFunction16
+#define DP_GetHpdStatusSF DP_SanityFunction16
+#define DP_SetFecEnableSF DP_SanityFunction3
+#define DP_SetFecReadySF DP_SanityFunction3
+#define DP_SetSdpSF DP_SanityFunction77
+#define DP_RemoveSdpSF DP_SanityFunction78
+#define DP_ConfigureHdcpTxSF DP_SanityFunction79
+#define DP_SetHdcp2TxPublicKeySF DP_SanityFunction80
+#define DP_SetHdcpKmEncCustomKeySF DP_SanityFunction81
+#define DP_SetHdcp2DebugRandomSF DP_SanityFunction82
+#define DP_Hdcp2RespondKmNotStoredSF DP_SanityFunction3
+#define DP_Hdcp2RespondKmStoredSF DP_SanityFunction84
+#define DP_SetHdcp1TxKeysSF DP_SanityFunction85
+#define DP_SetHdcp1RandomAnSF DP_SanityFunction3
+#define DP_SendHdcpTxStatusRequestSF DP_SanityFunction3
+#define DP_GetHdcpTxStatusResponseSF DP_SanityFunction88
+#define DP_GetHdcpTxStatusSF DP_SanityFunction88
+#define DP_SendHdcp2RecvIdRequestSF DP_SanityFunction3
+#define DP_GetHdcp2RecvIdResponseSF DP_SanityFunction3
+#define DP_GetHdcp2RecvIdSF DP_SanityFunction3
+#define DP_SendHdcp2PairingDataRequeSF DP_SanityFunction3
+#define DP_GetHdcp2PairingDataResponSF DP_SanityFunction94
+#define DP_GetHdcp2PairingDataSF DP_SanityFunction94
+#define DP_SendHdcpRecvIdListRequestSF DP_SanityFunction3
+#define DP_GetHdcpRecvIdListResponseSF DP_SanityFunction97
+#define DP_GetHdcpRecvIdListSF DP_SanityFunction97
+#define DP_SetHdcpRecvValidSF DP_SanityFunction3
+#define DP_SetHdcp2LcSF DP_SanityFunction3
+#define DP_SetHdcpSeedSF DP_SanityFunction3
+#define DP_AudioSetMuteSF DP_SanityFunction102
+#define DP_AudioAutoConfigSF DP_SanityFunction103
+#define DP_AudioStopSF DP_SanityFunction3
+#define DP_AudioSetModeSF DP_SanityFunction105
+#define DP_SetDscConfigSF DP_SanityFunction106
+#define DP_GetDscConfigSF DP_SanityFunction107
+#define DP_DscSendPpsSF DP_SanityFunction3
+#define DP_SetCompressedStreamFlagSF DP_SanityFunction3
+#define DP_DscResetSF DP_SanityFunction3
+#define DP_MstEnableSF DP_SanityFunction3
+#define DP_MstDisableSF DP_SanityFunction3
+#define DP_MstStreamEnableSF DP_SanityFunction3
+#define DP_MstStreamDisableSF DP_SanityFunction3
+#define DP_MstAllocateVcpiSF DP_SanityFunction115
+#define DP_MstDeallocateVcpiSF DP_SanityFunction115
+#define DP_MstGetSinkCountSF DP_SanityFunction19
+#define DP_MstGetSinkListSF DP_SanityFunction118
+#define DP_MstSetEncryptionEnableSF DP_SanityFunction3
+#define DP_MstSetEncryptionSF DP_SanityFunction3
+#define DP_MstScanTopologySF DP_SanityFunction3
+#define DP_MstReadRemoteEdidSF DP_SanityFunction122
+#define DP_MstHpdIrqSF DP_SanityFunction3
+
+#endif /* DP_SANITY_H */
+
+/* parasoft-end-suppress MISRA2012-RULE-8_7 */
+/* parasoft-end-suppress METRICS-41-3 */
+/* parasoft-end-suppress METRICS-39-3 */
+/* parasoft-end-suppress METRICS-36-3 */
+/* parasoft-end-suppress METRICS-18-3 */
diff --git a/packages/ti/drv/dss/src/csl/dp/src/dp_sdp.c b/packages/ti/drv/dss/src/csl/dp/src/dp_sdp.c
--- /dev/null
@@ -0,0 +1,183 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ *
+ * dp_sdp.c
+ *
+ ******************************************************************************
+ */
+
+/* parasoft-begin-suppress METRICS-41 "Number of blocks comments per statement" */
+
+#include "dp_if.h"
+#include "dp_priv.h"
+#include "dp_mst.h"
+#include "dp_utils.h"
+#include "dp_sanity.h"
+#include "mhdp_apb_regs.h"
+
+#include "cdn_errno.h"
+#include "cdn_stdint.h"
+
+static uint32_t getActiveIdleBit(DP_SdpActiveIdleMode activeMode) {
+ uint32_t activeIdleBit = 0U;
+ if (DP_SDP_ACTIVE_VIDEO == activeMode) {
+ activeIdleBit = CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_PKT_ALLOC_REG_P, ACTIVE_IDLE_TYPE, 0U, 1U);
+ }
+ return activeIdleBit;
+}
+
+static void writeEntryId(DP_PrivateData* pD, uint8_t streamId, uint8_t entryId) {
+
+ /* write entry id */
+ CPS_REG_WRITE(&pD->regBase->mhdp_apb_regs.mhdp_sdp_control[streamId].SOURCE_PIF_WR_ADDR_p,
+ CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_WR_ADDR_P, WR_ADDR, 0U, entryId));
+ /* write request */
+ CPS_REG_WRITE(&pD->regBase->mhdp_apb_regs.mhdp_sdp_control[streamId].SOURCE_PIF_WR_REQ_p,
+ CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_WR_REQ_P, HOST_WR, 0U, 1U));
+}
+
+static void writeDataToPacketMemory(DP_PrivateData* pD, uint8_t streamId, uint8_t size, const uint32_t* buffer) {
+
+ uint8_t i;
+
+ for (i = 0U; i < size; i++) {
+ CPS_REG_WRITE(&pD->regBase->mhdp_apb_regs.mhdp_sdp_control[streamId].SOURCE_PIF_DATA_WR_p,
+ buffer[i]);
+ }
+}
+
+static void updateEntry(DP_PrivateData* pD, uint8_t streamId, uint8_t entryID, const DP_SdpEntry* packetData) {
+
+ uint32_t activeIdleBit = getActiveIdleBit(packetData->activeMode);
+
+ CPS_REG_WRITE(&pD->regBase->mhdp_apb_regs.mhdp_sdp_control[streamId].SOURCE_PIF_PKT_ALLOC_REG_p,
+ activeIdleBit |
+ CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_PKT_ALLOC_REG_P, TYPE_VALID, 0U, 1U) |
+ CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_PKT_ALLOC_REG_P, PACKET_TYPE, 0U, packetData->type) |
+ CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_PKT_ALLOC_REG_P, PKT_ALLOC_ADDRESS, 0U, entryID));
+
+ CPS_REG_WRITE(&pD->regBase->mhdp_apb_regs.mhdp_sdp_control[streamId].SOURCE_PIF_PKT_ALLOC_WR_EN_p,
+ CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_PKT_ALLOC_WR_EN_P, PKT_ALLOC_WR_EN, 0U, 1U));
+
+ /* save packet type for given stream and given entryID */
+ /* packet is neccessary to proper removing */
+ pD->sdpPacketType[streamId][entryID] = packetData->type;
+}
+static void setPpsHeader(DP_PrivateData* pD, uint8_t streamId, uint32_t header) {
+
+ CPS_REG_WRITE(&pD->regBase->mhdp_apb_regs.mhdp_sdp_control[streamId].SOURCE_PIF_PPS_p,
+ CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_PPS_P, PPS, 0U, 1U));
+
+ /* write PPS header */
+ CPS_REG_WRITE(&pD->regBase->mhdp_apb_regs.mhdp_sdp_control[streamId].SOURCE_PIF_PPS_HEADER_p,
+ header);
+}
+
+static void setSdpEntry(DP_PrivateData* pD, uint8_t streamId, uint8_t entryID, const DP_SdpEntry* packetData) {
+
+ uint8_t index = 0U;
+
+ /* flush fifo 1 */
+ CPS_REG_WRITE(&pD->regBase->mhdp_apb_regs.mhdp_sdp_control[streamId].SOURCE_PIF_FIFO1_FLUSH_p,
+ CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_FIFO1_FLUSH_P, FIFO1_FLUSH, 0U, 1U));
+
+ if (packetData->type == 0x10U) { /* PPS */
+ setPpsHeader(pD, streamId, packetData->packet[0]);
+ index = 1U;
+ }
+
+ writeDataToPacketMemory(pD, streamId, (packetData->length - index), &packetData->packet[index]);
+
+ writeEntryId(pD, streamId, entryID);
+
+ updateEntry(pD, streamId, entryID, packetData);
+
+}
+
+uint32_t DP_SetSdp(DP_PrivateData* pD, uint8_t streamId, uint8_t entryID, const DP_SdpEntry* packetData)
+{
+ uint32_t retVal = CDN_EOK;
+
+ if ((NULL == pD) || (NULL == packetData)) {
+ retVal = CDN_EINVAL;
+ }
+
+ if (CDN_EOK == retVal) {
+ retVal = DP_StreamIdMstSstSanity(pD, streamId);
+ }
+
+ if (CDN_EOK == retVal) {
+ /* invalidate entry */
+ retVal = DP_RemoveSdp(pD, streamId, entryID);
+ }
+
+ if (CDN_EOK == retVal) {
+ setSdpEntry(pD, streamId, entryID, packetData);
+ }
+
+ return retVal;
+
+}
+
+uint32_t DP_RemoveSdp(DP_PrivateData* pD, uint8_t streamId, uint8_t entryID)
+{
+ uint32_t retVal = CDN_EOK;
+
+ if (NULL == pD)
+ {
+ retVal = CDN_EINVAL;
+ }
+
+ if (CDN_EOK == retVal) {
+ retVal = DP_StreamIdMstSstSanity(pD, streamId);
+ }
+
+ if (CDN_EOK == retVal) {
+ retVal = DP_RemoveSdpSF(pD, entryID);
+ }
+
+ if (CDN_EOK == retVal)
+ {
+ /* invalidate entry */
+ CPS_REG_WRITE(&pD->regBase->mhdp_apb_regs.mhdp_sdp_control[streamId].SOURCE_PIF_PKT_ALLOC_REG_p,
+ CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_PKT_ALLOC_REG_P, ACTIVE_IDLE_TYPE, 0U, 1U) |
+ CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_PKT_ALLOC_REG_P, PACKET_TYPE, 0U, pD->sdpPacketType[streamId][entryID]) |
+ CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_PKT_ALLOC_REG_P, PKT_ALLOC_ADDRESS, 0U, entryID));
+ CPS_REG_WRITE(&pD->regBase->mhdp_apb_regs.mhdp_sdp_control[streamId].SOURCE_PIF_PKT_ALLOC_WR_EN_p,
+ CPS_FLD_WRITE(MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_PKT_ALLOC_WR_EN_P, PKT_ALLOC_WR_EN, 0U, 1U));
+
+ /* reset packet type to 0 */
+ pD->sdpPacketType[streamId][entryID] = 0U;
+ }
+
+ return retVal;
+}
+
+/* parasoft-end-suppress METRICS-41 "Number of blocks comments per statement" */
diff --git a/packages/ti/drv/dss/src/csl/dp/src/dp_sideband_msg.c b/packages/ti/drv/dss/src/csl/dp/src/dp_sideband_msg.c
--- /dev/null
@@ -0,0 +1,549 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ *
+ * dp_sideband_msg.c
+ *
+ ******************************************************************************
+ */
+
+/*
+ * Copyright (C) 2014 Red Hat
+ *
+ * Permission to use, copy, modify, distribute, and sell this software and its
+ * documentation for any purpose is hereby granted without fee, provided that
+ * the above copyright notice appear in all copies and that both that copyright
+ * notice and this permission notice appear in supporting documentation, and
+ * that the name of the copyright holders not be used in advertising or
+ * publicity pertaining to distribution of the software without specific,
+ * written prior permission. The copyright holders make no representations
+ * about the suitability of this software for any purpose. It is provided "as
+ * is" without express or implied warranty.
+ *
+ * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
+ * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
+ * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
+ * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
+ * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
+ * OF THIS SOFTWARE.
+ */
+
+#include <cdn_stdtypes.h>
+#include <cdn_errno.h>
+#include <cdn_log.h>
+
+#include "dp_aux.h"
+#include "dp_aux_if.h"
+#include "dp_sideband_msg.h"
+#include "dp_sideband_msg_if.h"
+#include "dp_sideband_msg_structs_if.h"
+
+/* parasoft-begin-suppress METRICS-41-3 "Number of blocks of comments per statement" */
+
+static uint8_t drm_dp_msg_header_crc4(const uint8_t *data, uint32_t num_nibbles)
+{
+ uint8_t bitmask = 0x80;
+ uint8_t bitshift = 7;
+ uint8_t array_index = 0;
+ uint32_t number_of_bits = num_nibbles * 4U;
+ uint8_t remainder_value = 0;
+
+ while (number_of_bits != 0U) {
+ number_of_bits--;
+ remainder_value <<= 1;
+ if (bitshift < 8U) {
+ remainder_value |= (data[array_index] & bitmask) >> bitshift;
+ }
+ bitmask >>= 1;
+ bitshift--;
+ if (bitmask == 0U) {
+ bitmask = 0x80;
+ bitshift = 7;
+ array_index++;
+ }
+ if ((remainder_value & 0x10U) == 0x10U) {
+ remainder_value ^= 0x13U;
+ }
+ }
+
+ number_of_bits = 4;
+ while (number_of_bits != 0U) {
+ number_of_bits--;
+ remainder_value <<= 1;
+ if ((remainder_value & 0x10U) != 0U) {
+ remainder_value ^= 0x13U;
+ }
+ }
+
+ return remainder_value;
+}
+
+/** Return minimum of 2 - element set (uint32_t). */
+static uint32_t min(uint32_t a, uint32_t b)
+{
+ uint32_t result = a;
+ if (b < a) {
+ result = b;
+ }
+ return result;
+}
+
+/** Return minimum of 3 - element set (uint32_t). */
+static uint32_t min3(uint32_t x, uint32_t y, uint32_t z)
+{
+ return min(min(x, y), z);
+}
+
+/** Send sideband msg. Returns CDN_EOK on success.*/
+static uint32_t drm_dp_send_sideband_msg(struct MST_drm_dp_topology_mgr_s *mgr,
+ bool up, uint8_t *msg, uint32_t len)
+{
+ uint32_t ret = CDN_EOK;
+ uint32_t regbase = up ? DP_SIDEBAND_MSG_UP_REP_BASE : DP_SIDEBAND_MSG_DOWN_REQ_BASE;
+ uint32_t tosend, total, offset;
+ uint32_t retries = 0;
+
+ do {
+ total = len;
+ offset = 0;
+ do {
+ tosend = min3(mgr->max_dpcd_transaction_bytes, 16U, total);
+ ret = drm_dp_dpcd_write(mgr->aux, regbase + offset,
+ &msg[offset], tosend);
+ if (ret != CDN_EOK) { /* if writing DPCD register failed */
+ retries++;
+ break;
+ }
+ offset += tosend;
+ total -= tosend;
+ } while (total > 0U);
+ } while ((total > 0U) && (retries < 5U)); /* repeat max 5 times */
+
+ if ((ret != CDN_EOK) || (total > 0U)) {
+ DbgMsg(DBG_GEN_MSG, DBG_CRIT,
+ "failed to dpcd write %d %d\n", tosend, ret);
+ }
+ return ret;
+}
+
+/** Calculate a 4-bit crc for a given uint8_t array. */
+static uint8_t drm_dp_msg_data_crc4(const uint8_t *data, uint8_t number_of_bytes)
+{
+ uint8_t bitmask = 0x80;
+ uint8_t bitshift = 7;
+ uint8_t array_index = 0;
+ /* data is treated as one continuous value to checksum */
+ uint32_t number_of_bits = (uint32_t)number_of_bytes * 8U; /* number of bits in value to checksum */
+ uint16_t remainder_value = 0;
+
+ while (number_of_bits != 0U) {
+ number_of_bits--;
+ remainder_value <<= 1;
+ if (bitshift < 8U) {
+ uint8_t new_remainder_value = ((data[array_index]) & bitmask) >> bitshift;
+ remainder_value |= (uint16_t) new_remainder_value;
+ }
+ bitmask >>= 1;
+ bitshift--;
+ if (bitmask == 0U) {
+ bitmask = 0x80;
+ bitshift = 7;
+ array_index++;
+ }
+ if ((remainder_value & 0x100U) == 0x100U) {
+ remainder_value ^= 0xd5U;
+ }
+ }
+ /* last byte */
+ number_of_bits = 8;
+ while (number_of_bits != 0U) {
+ number_of_bits--;
+ remainder_value <<= 1;
+ if ((remainder_value & 0x100U) != 0U) {
+ remainder_value ^= 0xd5U;
+ }
+ }
+
+ return (uint8_t)(remainder_value & 0xffU);
+}
+
+static void drm_dp_crc_sideband_chunk_req(uint8_t *msg, uint8_t len)
+{
+ uint8_t crc4;
+ /* calculate the 4-bit crc and save it at the end of msg */
+ crc4 = drm_dp_msg_data_crc4(msg, len);
+ msg[len] = crc4;
+}
+
+/** Decode sideband message header. */
+static void drm_dp_encode_sideband_msg_hdr(const SBM_drm_dp_sideband_msg_hdr *hdr,
+ uint8_t *buf, uint32_t *len)
+{
+ uint32_t idx = 0;
+ uint8_t i;
+ uint8_t crc4;
+ /* buf table is filled with data from SBM_drm_dp_sideband_msg_hdr hdr structure */
+ buf[idx] = ((hdr->lct & 0xfU) << 4) | (hdr->lcr & 0xfU);
+ ++idx;
+ for (i = 0; i < (hdr->lct / 2U); i++) {
+ buf[idx] = hdr->rad[i];
+ ++idx;
+ }
+ buf[idx] = ((hdr->broadcast ? 1U : 0U) << 7) | ((hdr->path_msg ? 1U : 0U) << 6) |
+ (hdr->msg_len & 0x3fU);
+ ++idx;
+ buf[idx] = ((hdr->somt ? 1U : 0U) << 7) | ((hdr->eomt ? 1U : 0U) << 6) | ((hdr->seqno ? 1U : 0U) << 4);
+ ++idx;
+ /* calculate 4-bit crc... */
+ crc4 = drm_dp_msg_header_crc4(buf, (idx * 2U) - 1U);
+ buf[idx - 1U] |= (crc4 & 0xfU); /* and save it at the end of buf table. */
+
+ *len = idx;
+}
+
+/** Calculate DRM DP Sideband header size */
+static inline uint8_t drm_dp_calc_sb_hdr_size(const SBM_drm_dp_sideband_msg_hdr *hdr)
+{
+ uint8_t size = 3;
+ size += (hdr->lct / 2U);
+ return size;
+}
+
+static uint32_t set_hdr_from_dst_qlock(SBM_drm_dp_sideband_msg_hdr *hdr,
+ SBM_drm_dp_sideband_msg_tx * txmsg)
+{
+ uint32_t ret = CDN_EOK;
+
+ /* both msg slots are full */
+ MST_drm_dp_branch *mstb = txmsg->dst;
+ if (txmsg->seqno == -1) {
+ if (mstb->tx_slots[0] != NULL) {
+ if (mstb->tx_slots[1] != NULL) {
+ /* ok, ok */
+ DbgMsg(DBG_GEN_MSG, DBG_CRIT, "%s: failed to find slot\n", __func__);
+ ret = CDN_EAGAIN;
+ } else {
+ /* ok, null */
+ txmsg->seqno = 1;
+ mstb->tx_slots[txmsg->seqno] = txmsg;
+ }
+ } else {
+ if (mstb->tx_slots[1] == NULL) {
+ /* null, null */
+ txmsg->seqno = mstb->last_seqno;
+ uint32_t new_last_segno = (uint32_t) mstb->last_seqno ^ 1U; /* need to be unsigned */
+ mstb->last_seqno = (int32_t) new_last_segno;
+ mstb->tx_slots[txmsg->seqno] = txmsg;
+ } else {
+ /* null, ok */
+ txmsg->seqno = 0;
+ mstb->tx_slots[txmsg->seqno] = txmsg;
+ }
+ }
+ }
+
+ if (ret == CDN_EOK) {
+ switch (txmsg->msg[0] & 0x7fU) { /* reg type */
+ case DP_CONNECTION_STATUS_NOTIFY:
+ case DP_RESOURCE_STATUS_NOTIFY:
+ hdr->broadcast = 1;
+ break;
+ default:
+ hdr->broadcast = 0;
+ break;
+ }
+
+ hdr->path_msg = txmsg->path_msg;
+ hdr->lct = mstb->lct;
+ hdr->lcr = mstb->lct - 1U;
+ if (mstb->lct > 1U) {
+ (void) memcpy(hdr->rad, mstb->rad, (uint8_t)(mstb->lct / 2U));
+ }
+ hdr->seqno = (txmsg->seqno != 0) ? (bool)true : (bool)false;
+ }
+ return ret;
+}
+
+/** make hdr from dst mst */
+static uint32_t single_tx_data_prepare(SBM_drm_dp_sideband_msg_hdr *hdr,
+ SBM_drm_dp_sideband_msg_tx * txmsg,
+ uint8_t * chunk,
+ uint32_t * idx,
+ uint32_t * tosend)
+{
+ uint32_t ret;
+ uint32_t len, space;
+ /* make hdr from dst mst - for replies use seqno
+ otherwise assign one */
+ ret = set_hdr_from_dst_qlock(hdr, txmsg);
+ if (ret == CDN_EOK) {
+ /* amount left to send in this message */
+ len = (uint32_t) txmsg->cur_len - (uint32_t) txmsg->cur_offset;
+
+ /* 48 - sideband msg size - 1 byte for data CRC, x header bytes */
+ space = 48U - 1U - (uint32_t) drm_dp_calc_sb_hdr_size(hdr);
+
+ *tosend = min(len, space);
+ if (len == txmsg->cur_len) {
+ hdr->somt = 1;
+ }
+ if (space >= len) {
+ hdr->eomt = 1;
+ }
+
+ hdr->msg_len = (uint8_t)(*tosend + 1U);
+ drm_dp_encode_sideband_msg_hdr(hdr, chunk, idx);
+ (void) memcpy(&chunk[*idx], &txmsg->msg[txmsg->cur_offset], *tosend);
+ /* add crc at end */
+ drm_dp_crc_sideband_chunk_req(&chunk[*idx], (uint8_t)*tosend);
+ *idx += *tosend + 1U;
+ }
+ return ret;
+}
+
+/*
+ * process a single block of the next message in the sideband queue
+ */
+uint32_t process_single_tx_qlock(struct MST_drm_dp_topology_mgr_s *mgr,
+ SBM_drm_dp_sideband_msg_tx * txmsg,
+ bool up)
+{
+ uint8_t chunk[48];
+ SBM_drm_dp_sideband_msg_hdr hdr;
+ uint32_t idx, tosend;
+ uint32_t ret;
+
+ /* Clear the header */
+ (void) memset(&hdr, 0, sizeof(SBM_drm_dp_sideband_msg_hdr));
+
+ if (txmsg->state == DRM_DP_SIDEBAND_TX_QUEUED) {
+ txmsg->seqno = -1;
+ txmsg->state = DRM_DP_SIDEBAND_TX_START_SEND;
+ }
+
+ /* Fill the header */
+ ret = single_tx_data_prepare(&hdr, txmsg, &chunk[0], &idx, &tosend);
+ /* single_tx_data_prepare also writes to uint32_t variables idx, tosend, which are declared here */
+
+ if (ret == CDN_EOK) {
+ ret = drm_dp_send_sideband_msg(mgr, up, chunk, idx);
+ if (ret != CDN_EOK) {
+ DbgMsg(DBG_GEN_MSG, DBG_CRIT,
+ "sideband msg failed to send\n");
+ }
+ }
+
+ if (ret == CDN_EOK) {
+ txmsg->cur_offset += (uint8_t) tosend;
+ if (txmsg->cur_offset == txmsg->cur_len) {
+ txmsg->state = DRM_DP_SIDEBAND_TX_SENT;
+ ret = 1U;
+ }
+ }
+
+ return ret;
+}
+
+/****************** RX *********************************************/
+
+/** Validate sideband message header. Helper function of drm_dp_decode_sideband_msg_hdr().
+ * Returns false if header is corrupted. */
+static bool drm_dp_dec_sb_msg_hdr_validate(const uint8_t *buf, int32_t buflen) {
+ bool ret = true;
+ if (buf[0] == 0U) {
+ ret = false;
+ }
+ if (ret) {
+ /* calculate length from the first element of buf */
+ uint8_t len = 3U;
+ len += ((buf[0] & 0xf0U) >> 4) / 2U;
+ /* fail if calculated length is greater than length passed as an argument */
+ if (len > (uint8_t) buflen) {
+ ret = false;
+ } else {
+ /* calculate the 4-bit crc */
+ uint8_t crc4 = drm_dp_msg_header_crc4(buf, (((uint32_t) len * 2U) - 1U));
+ /* compare it with a previously calculated crc at the end of the buf table */
+ if ((crc4 & 0xfU) != (buf[len - 1U] & 0xfU)) {
+ DbgMsg(DBG_GEN_MSG, DBG_CRIT,
+ "crc4 mismatch 0x%x 0x%x\n", crc4, buf[len - 1U]);
+ ret = false;
+ }
+ }
+ }
+ return ret;
+}
+
+/** Decode sideband message header. Returns false if header is corrupted and was not decoded. */
+static bool drm_dp_decode_sideband_msg_hdr(SBM_drm_dp_sideband_msg_hdr *hdr,
+ const uint8_t *buf, int32_t buflen, uint8_t *hdrlen)
+{
+ bool ret = true;
+ int32_t i;
+ uint8_t idx;
+
+ /* Validate the header */
+ ret = drm_dp_dec_sb_msg_hdr_validate(buf, buflen);
+
+ if (ret) {
+ /* Decode the header */
+ hdr->lct = (buf[0] & 0xf0U) >> 4;
+ hdr->lcr = (buf[0] & 0xfU);
+ idx = 1U;
+ for (i = 0; i < ((int32_t) hdr->lct / 2); i++) {
+ hdr->rad[i] = buf[idx];
+ ++idx;
+ }
+ if (((buf[idx] >> 7) & 0x1U) != 0U) {
+ hdr->broadcast = true;
+ }
+
+ hdr->broadcast = (((buf[idx] >> 7) & 0x1U) != 0U) ? (bool)true : (bool)false;
+ hdr->path_msg = (((buf[idx] >> 6) & 0x1U) != 0U) ? (bool)true : (bool)false;
+ hdr->msg_len = buf[idx] & 0x3fU;
+ idx++;
+ hdr->somt = (((buf[idx] >> 7) & 0x1U) != 0U) ? (bool)true : (bool)false;
+ hdr->eomt = (((buf[idx] >> 6) & 0x1U) != 0U) ? (bool)true : (bool)false;
+ hdr->seqno = (((buf[idx] >> 4) & 0x1U) != 0U) ? (bool)true : (bool)false;
+ idx++;
+ *hdrlen = idx;
+ }
+ return ret;
+}
+
+static bool drm_dp_sideband_msg_build(SBM_drm_dp_sideband_msg_rx *msg,
+ uint8_t *replybuf, uint8_t replybuflen, bool hdr)
+{
+ bool ret = true;
+
+ if (hdr) {
+ uint8_t hdrlen;
+ SBM_drm_dp_sideband_msg_hdr recv_hdr;
+ ret = drm_dp_decode_sideband_msg_hdr(&recv_hdr, replybuf, (int32_t) replybuflen, &hdrlen);
+ if (ret) {
+ msg->curchunk_len = recv_hdr.msg_len;
+ msg->curchunk_hdrlen = hdrlen;
+
+ /* we have already gotten an somt - don't bother parsing */
+ if (recv_hdr.somt && msg->have_somt) {
+ ret = false;
+ } else {
+ if (recv_hdr.somt) {
+ (void) memcpy(&msg->initial_hdr, &recv_hdr, sizeof(SBM_drm_dp_sideband_msg_hdr));
+ msg->have_somt = true;
+ }
+ if (recv_hdr.eomt) {
+ msg->have_eomt = true;
+ }
+ /* copy the bytes for the remainder of this header chunk */
+ msg->curchunk_idx = (uint8_t) min(msg->curchunk_len, (uint8_t)(replybuflen - hdrlen));
+ (void) memcpy(&msg->chunk[0], &replybuf[hdrlen], msg->curchunk_idx);
+ }
+ }
+ } else {
+ (void) memcpy(&msg->chunk[msg->curchunk_idx], replybuf, replybuflen);
+ msg->curchunk_idx += replybuflen;
+ }
+
+ if (ret && (msg->curchunk_idx >= msg->curchunk_len)) {
+ /* copy chunk into bigger msg */
+ uint8_t memcpy_size = msg->curchunk_len - 1U;
+ (void) memcpy(&msg->msg[msg->curlen], msg->chunk, memcpy_size);
+ msg->curlen += msg->curchunk_len - 1U;
+ }
+ return ret;
+}
+
+bool drm_dp_get_one_sb_msg(struct MST_drm_dp_topology_mgr_s *mgr, bool up)
+{
+ uint32_t len, curreply;
+ uint8_t replyblock[32];
+ int32_t replylen;
+ bool ret = true;
+ uint32_t dpcdReadRetVal;
+ SBM_drm_dp_sideband_msg_rx *msg;
+ uint32_t basereg;
+ if (up) {
+ basereg = DP_SIDEBAND_MSG_UP_REQ_BASE;
+ msg = &mgr->up_req_recv;
+ } else {
+ basereg = DP_SIDEBAND_MSG_DOWN_REP_BASE;
+ msg = &mgr->down_rep_recv;
+ }
+
+ len = min(mgr->max_dpcd_transaction_bytes, 16);
+ dpcdReadRetVal = drm_dp_dpcd_read(mgr->aux, basereg,
+ replyblock, len);
+ if (dpcdReadRetVal != CDN_EOK) {
+ DbgMsg(DBG_GEN_MSG, DBG_CRIT,
+ "failed to read DPCD down rep %d %d\n", len, ret);
+ ret = false;
+ }
+ if (ret) {
+ ret = drm_dp_sideband_msg_build(msg, replyblock, (uint8_t) len, true);
+ if (!ret) {
+ DbgMsg(DBG_GEN_MSG, DBG_CRIT,
+ "sideband msg build failed %d\n", replyblock[0]);
+ }
+ }
+
+ if (ret) {
+ bool has_to_break = false;
+ replylen = (int32_t) msg->curchunk_len + (int32_t) msg->curchunk_hdrlen;
+ replylen -= (int32_t) len;
+ curreply = len;
+ while (replylen > 0) {
+ len = min3((uint32_t)replylen, mgr->max_dpcd_transaction_bytes, 16U);
+ dpcdReadRetVal = drm_dp_dpcd_read(mgr->aux, basereg + curreply,
+ replyblock, len);
+ if (has_to_break) {
+ break;
+ } else if (dpcdReadRetVal != CDN_EOK) {
+ DbgMsg(DBG_GEN_MSG, DBG_CRIT,
+ "failed to read a chunk (len %d, ret %d)\n",
+ len, dpcdReadRetVal);
+ ret = false;
+ has_to_break = true;
+ } else {
+ ret = drm_dp_sideband_msg_build(msg, replyblock, (uint8_t)len, false);
+ if (!ret) {
+ DbgMsg(DBG_GEN_MSG, DBG_CRIT,
+ "failed to build sideband msg\n");
+ ret = false;
+ has_to_break = true;
+ }
+ curreply += len;
+ replylen -= (int32_t) len;
+ }
+ }
+ }
+ return ret;
+}
+/* parasoft-end-suppress METRICS-41-3 "Number of blocks of comments per statement" */
diff --git a/packages/ti/drv/dss/src/csl/dp/src/dp_sideband_msg.h b/packages/ti/drv/dss/src/csl/dp/src/dp_sideband_msg.h
--- /dev/null
@@ -0,0 +1,123 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ *
+ * dp_sideband_msg.h
+ *
+ ******************************************************************************
+ */
+
+/*
+ * Copyright (C) 2014 Red Hat
+ *
+ * Permission to use, copy, modify, distribute, and sell this software and its
+ * documentation for any purpose is hereby granted without fee, provided that
+ * the above copyright notice appear in all copies and that both that copyright
+ * notice and this permission notice appear in supporting documentation, and
+ * that the name of the copyright holders not be used in advertising or
+ * publicity pertaining to distribution of the software without specific,
+ * written prior permission. The copyright holders make no representations
+ * about the suitability of this software for any purpose. It is provided "as
+ * is" without express or implied warranty.
+ *
+ * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
+ * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
+ * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
+ * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
+ * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
+ * OF THIS SOFTWARE.
+ */
+
+#ifndef DP_SIDEBAND_MSG
+#define DP_SIDEBAND_MSG
+
+#include <cdn_stdtypes.h>
+#include "dp_sideband_msg_if.h"
+#include "dp_sideband_msg_structs_if.h"
+
+/***************************************/
+/*TODO to be removed*/
+/***************************************/
+#include <stdio.h>
+#include <string.h>
+/***************************************/
+
+#define DP_GUID 0x030 /* 1.2 */
+
+/* DPCD */
+
+#define DP_SIDEBAND_MSG_DOWN_REQ_BASE 0x1000U /* 1.2 MST */
+#define DP_SIDEBAND_MSG_UP_REP_BASE 0x1200U /* 1.2 MST */
+#define DP_SIDEBAND_MSG_DOWN_REP_BASE 0x1400U /* 1.2 MST */
+#define DP_SIDEBAND_MSG_UP_REQ_BASE 0x1600U /* 1.2 MST */
+/* DPCD */
+
+/* msg is queued to be put into a slot */
+#define DRM_DP_SIDEBAND_TX_QUEUED 0U
+/* msg has started transmitting on a slot - still on msgq */
+#define DRM_DP_SIDEBAND_TX_START_SEND 1U
+/* msg has finished transmitting on a slot - removed from msgq only in slot */
+#define DRM_DP_SIDEBAND_TX_SENT 2U
+/* msg has received a response - removed from slot */
+#define DRM_DP_SIDEBAND_TX_RX 3U
+#define DRM_DP_SIDEBAND_TX_TIMEOUT 4U
+
+#define DP_SINK_COUNT_ESI 0x2002 /* 1.2 */
+/* 0-5 sink count */
+# define DP_SINK_COUNT_CP_READY (1U << 6)
+#define DP_DEV_SERVICE_IRQ_VECTOR_ESI0 0x2003 /* 1.2 */
+# define DP_DOWN_REP_MSG_RDY (1U << 4) /* 1.2 MST */
+# define DP_UP_REQ_MSG_RDY (1U << 5) /* 1.2 MST */
+
+#define DP_DEV_SERVICE_IRQ_VECTOR_ESI1 0x2004 /* 1.2 */
+
+/* DP 1.2 MST sideband request names DP 1.2a Table 2-80 */
+#define DP_LINK_ADDRESS 0x01U
+#define DP_CONNECTION_STATUS_NOTIFY 0x02U
+#define DP_ENUM_PATH_RESOURCES 0x10U
+#define DP_ALLOCATE_PAYLOAD 0x11U
+#define DP_RESOURCE_STATUS_NOTIFY 0x13U
+#define DP_CLEAR_PAYLOAD_ID_TABLE 0x14U
+#define DP_REMOTE_DPCD_READ 0x20U
+#define DP_REMOTE_DPCD_WRITE 0x21U
+#define DP_REMOTE_I2C_READ 0x22U
+#define DP_REMOTE_I2C_WRITE 0x23U
+#define DP_POWER_UP_PHY 0x24U
+#define DP_POWER_DOWN_PHY 0x25U
+#define DP_SINK_EVENT_NOTIFY 0x30U
+#define DP_QUERY_STREAM_ENC_STATUS 0x38U
+
+uint32_t process_single_tx_qlock(MST_drm_dp_topology_mgr * mgr,
+ SBM_drm_dp_sideband_msg_tx *txmsg,
+ bool up);
+
+bool drm_dp_get_one_sb_msg(MST_drm_dp_topology_mgr *mgr, bool up);
+
+#endif
diff --git a/packages/ti/drv/dss/src/csl/dp/src/dp_topology_mgr.c b/packages/ti/drv/dss/src/csl/dp/src/dp_topology_mgr.c
--- /dev/null
@@ -0,0 +1,951 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ *
+ * dp_topology_mgr.c
+ *
+ ******************************************************************************
+ */
+
+/*
+ * Copyright (C) 2014 Red Hat
+ *
+ * Permission to use, copy, modify, distribute, and sell this software and its
+ * documentation for any purpose is hereby granted without fee, provided that
+ * the above copyright notice appear in all copies and that both that copyright
+ * notice and this permission notice appear in supporting documentation, and
+ * that the name of the copyright holders not be used in advertising or
+ * publicity pertaining to distribution of the software without specific,
+ * written prior permission. The copyright holders make no representations
+ * about the suitability of this software for any purpose. It is provided "as
+ * is" without express or implied warranty.
+ *
+ * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
+ * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
+ * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
+ * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
+ * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
+ * OF THIS SOFTWARE.
+ */
+
+#include <stddef.h>
+#include <stdlib.h>
+#include "cdn_math.h"
+#include "cdn_stdtypes.h"
+#include "cps.h"
+#include "dp_aux.h"
+#include "dp_sideband_msg.h"
+#include "dp_topology_mgr.h"
+#include "dp_topology_utils.h"
+#include "dp_transaction.h"
+#include "cdn_log.h"
+
+/**
+ * DOC: dp mst helper
+ *
+ * These functions contain parts of the DisplayPort 1.2a MultiStream Transport
+ * protocol. The helpers contain a topology manager and bandwidth manager.
+ * The helpers encapsulate the sending and received of sideband msgs.
+ */
+
+/* parasoft-begin-suppress METRICS-41-3 "Number of blocks of comments per statement in the function" */
+
+/* XXX: Linux macro, but it is idiom */
+static inline uint32_t DIV_ROUND_UP (uint32_t numerator, uint32_t denominator) {
+ return (numerator + (denominator - 1U )) / denominator;
+}
+
+/* parasoft-begin-suppress METRICS-36 "Function called from more than 5 different functions in one translation unit, DRV-3823" */
+/**
+ * Set requested bit in 64-bit value.
+ */
+static void set_bit(uint8_t bit, uint64_t *address) {
+ if (bit < 64U) {
+ *address |= (1UL << bit);
+ }
+}
+/* parasoft-end-suppress METRICS-36-3 */
+
+/**
+ * Clear requested bit in 64-bit value.
+ */
+static void clear_bit(uint8_t bit, uint64_t *address) {
+ if (bit < 64U) {
+ *address &= ~(1UL << bit);
+ }
+}
+
+/**
+ * Find position of first cleared bit in 64-bit value, starting from lsb.
+ */
+static uint8_t find_first_zero_bit(const uint64_t *address, uint8_t size) {
+ uint8_t i;
+ uint8_t clampedSize = size;
+
+ if (size > 64U)
+ {
+ clampedSize = 64U;
+ }
+
+ for (i = 0; i < clampedSize; i++)
+ {
+ if (i < 64U)
+ {
+ if (0U == (*address & (1UL << i)))
+ {
+ break;
+ }
+ }
+ };
+
+ /* Will return size or '64', if zero was not found. */
+ return i;
+}
+
+static uint32_t drm_dp_dpcd_write_payload(MST_drm_dp_topology_mgr *mgr,
+ int32_t id, const MST_drm_dp_payload *payload);
+
+static uint32_t drm_dp_mst_assign_payload_id(MST_drm_dp_topology_mgr *mgr,
+ MST_drm_dp_vcpi * vcpi) {
+ uint32_t retVal = CDN_EOK;
+ uint8_t ret;
+ uint8_t vcpi_ret;
+
+ /* Find position of first unused Payload ID. */
+ ret = find_first_zero_bit(&mgr->payload_mask, MST_MAX_PAYLOAD + 1U);
+ if (ret > MST_MAX_PAYLOAD) {
+ retVal = CDN_EINVAL;
+ DbgMsg(DBG_GEN_MSG, DBG_CRIT, "out of payload ids %d\n", ret);
+ }
+
+#ifdef IS_DEMO_TB
+ if (!(mgr->vcpi_mask & (1 << (mgr->demotb.requestedVcpi - 1)))) {
+ vcpi_ret = mgr->demotb.requestedVcpi - 1;
+ } else {
+ retVal = CDN_EINVAL;
+ DbgMsg(DBG_GEN_MSG, DBG_CRIT, "Requested VCPI %d is in use\n",
+ mgr->demotb.requestedVcpi);
+ }
+#else
+ /* Find position of first unused VCPI. */
+ vcpi_ret = find_first_zero_bit(&mgr->vcpi_mask, MST_MAX_PAYLOAD + 1U);
+ if (vcpi_ret > MST_MAX_PAYLOAD) {
+ retVal = CDN_EINVAL;
+ DbgMsg(DBG_GEN_MSG, DBG_CRIT, "out of vcpi ids %d\n", ret);
+ }
+#endif
+
+ if (retVal == CDN_EOK) {
+ /* Set Payload ID as used. */
+ set_bit(ret, &mgr->payload_mask);
+ /* Set VCPI as used. */
+ set_bit(vcpi_ret, &mgr->vcpi_mask);
+ vcpi->vcpi = (int32_t)vcpi_ret + 1;
+ mgr->proposed_vcpis[ret - 1U] = vcpi;
+ }
+
+ return retVal;
+}
+
+static void drm_dp_mst_put_payload_id(MST_drm_dp_topology_mgr *mgr,
+ int32_t vcpi) {
+
+ uint32_t i;
+ if (vcpi != 0) {
+ DbgMsg(DBG_GEN_MSG, DBG_FYI, "putting payload %d\n", vcpi);
+ /* Set Payload ID as unused. */
+ clear_bit((uint8_t)vcpi - 1U, &mgr->vcpi_mask);
+
+ for (i = 0; i < MST_MAX_PAYLOAD; i++) {
+ if (mgr->proposed_vcpis[i] != NULL) {
+ if (mgr->proposed_vcpis[i]->vcpi == vcpi) {
+ mgr->proposed_vcpis[i] = NULL;
+ /* Set Payload ID as used. */
+ clear_bit((uint8_t)i + 1U, &mgr->payload_mask);
+ }
+ }
+ }
+ }
+}
+
+static uint32_t drm_dp_create_payload_step1(MST_drm_dp_topology_mgr *mgr,
+ int32_t id, MST_drm_dp_payload *payload) {
+ uint32_t ret;
+
+ /* Write Payload-related data to DPCD and wait for sink to acknowledge the */
+ /* change. */
+ ret = drm_dp_dpcd_write_payload(mgr, id, payload);
+ if (CDN_EOK != ret) {
+ payload->payload_state = 0;
+ } else {
+ payload->payload_state = (int32_t)MST_PAYLOAD_LOCAL;
+ }
+ return ret;
+}
+
+static uint32_t drm_dp_create_payload_step2(MST_drm_dp_topology_mgr *mgr,
+ MST_drm_dp_port *port, int32_t id, MST_drm_dp_payload *payload) {
+ uint32_t ret = CDN_EOK;
+
+#ifdef IS_DEMO_TB
+ if (!mgr->demotb.disableMessaging) {
+#endif
+ /* Send Payload-related data through sideband channel */
+ ret = drm_dp_payload_send_msg(mgr, port, id, port->vcpi.pbn);
+#ifdef IS_DEMO_TB
+}
+#endif
+ if (ret == 0U) {
+ payload->payload_state = (int32_t)MST_PAYLOAD_REMOTE;
+ }
+ return ret;
+}
+
+static uint32_t drm_dp_destroy_payload_step1(MST_drm_dp_topology_mgr *mgr,
+ MST_drm_dp_port *port, int32_t id, MST_drm_dp_payload *payload) {
+
+ uint32_t ret = CDN_EOK;
+ DbgMsg(DBG_GEN_MSG, DBG_FYI, "\n");
+ /* its okay for these to fail */
+
+ if (port != NULL) {
+#ifdef IS_DEMO_TB
+ if (!mgr->demotb.disableMessaging) {
+#endif
+ ret = drm_dp_payload_send_msg(mgr, port, id, 0);
+#ifdef IS_DEMO_TB
+ }
+#endif
+ }
+
+ if (ret == CDN_EOK) {
+ /* Write Payload-related data to DPCD and wait for sink to acknowledge */
+ /* the change. */
+ ret = drm_dp_dpcd_write_payload(mgr, id, payload);
+ if (ret != CDN_EOK) {
+ payload->payload_state = 0;
+ } else {
+ payload->payload_state = (int32_t)MST_PAYLOAD_DELETE_LOCAL;
+ }
+ }
+
+ return ret;
+}
+
+/**
+ * Check, if a given bit is set in 64-bit mask, with required size checks.
+ */
+static inline bool is64bBitSet(uint64_t mask, uint32_t bit)
+{
+ bool result = false;
+ if (bit < 64U) {
+ if (0U != (mask & (1ULL << bit))) {
+ result = true;
+ }
+ }
+ return result;
+}
+
+/**
+ * solve the current payloads - compare to the hw ones - update the hw view.
+ */
+static inline uint32_t solvePayloads(MST_drm_dp_topology_mgr *mgr,
+ MST_drm_dp_payload * req_payload,
+ MST_drm_dp_port ** port,
+ int32_t cur_slots,
+ uint32_t payloadId)
+{
+ uint32_t ret = CDN_EOK;
+ MST_drm_dp_port **portTmp = port;
+
+ req_payload->start_slot = (uint8_t)cur_slots;
+ if (mgr->proposed_vcpis[payloadId] != NULL) {
+ *port = mgr->proposed_vcpis[payloadId]->parent;
+ *portTmp = DRM_DP_getValidatedPortRef(mgr, *port);
+ *port = *portTmp;
+ if (*port == NULL) {
+ ret = CDN_EINVAL;
+ }
+ req_payload->num_slots = (uint8_t)mgr->proposed_vcpis[payloadId]->num_slots;
+ req_payload->vcpi = mgr->proposed_vcpis[payloadId]->vcpi;
+ } else {
+ *port = NULL;
+ req_payload->num_slots = 0U;
+ }
+
+ if (mgr->payloads[payloadId].start_slot != req_payload->start_slot) {
+ mgr->payloads[payloadId].start_slot = req_payload->start_slot;
+ }
+
+ return ret;
+}
+
+/**
+ * Push an update for given payload.
+ */
+static inline uint32_t pushPayloadUpdate(MST_drm_dp_topology_mgr *mgr,
+ MST_drm_dp_port * port,
+ MST_drm_dp_payload * req_payload,
+ uint32_t payloadId)
+{
+ uint32_t ret = CDN_EOK;
+ /* Get pointer to currently processed payload */
+ MST_drm_dp_payload *currPayload = &(mgr->payloads[payloadId]);
+
+ if (req_payload->num_slots > 0U) {
+ ret = drm_dp_create_payload_step1(mgr, mgr->proposed_vcpis[payloadId]->vcpi, req_payload);
+ if (CDN_EOK == ret) {
+ currPayload->num_slots = req_payload->num_slots;
+ currPayload->vcpi = req_payload->vcpi;
+ }
+ } else if (currPayload->num_slots > 0U) {
+ currPayload->num_slots = 0;
+ ret = drm_dp_destroy_payload_step1(mgr, port, currPayload->vcpi, currPayload);
+ if (CDN_EOK == ret)
+ {
+ req_payload->payload_state = currPayload->payload_state;
+ currPayload->start_slot = 0;
+ }
+ } else {
+ /* TODO provide else */
+ }
+ return ret;
+}
+
+/**
+ * Remove payloads, that were marked for deletion.
+ */
+static inline void removeMarkedPayloads(MST_drm_dp_topology_mgr *mgr)
+{
+ uint32_t i, j;
+
+ for (i = 0; i < MST_MAX_PAYLOAD; i++) {
+ if (mgr->payloads[i].payload_state == (int32_t)MST_PAYLOAD_DELETE_LOCAL) {
+ DbgMsg(DBG_GEN_MSG, DBG_FYI, "removing payload %d\n", i);
+ /* Move subsequent payloads to the front (beginning) */
+ for (j = i; j < (MST_MAX_PAYLOAD - 1U); j++) {
+ (void)memcpy(&mgr->payloads[j], &mgr->payloads[j + 1U], sizeof(MST_drm_dp_payload));
+ mgr->proposed_vcpis[j] = mgr->proposed_vcpis[j + 1U];
+ if ((mgr->proposed_vcpis[j] != NULL) && (mgr->proposed_vcpis[j]->num_slots != 0)) {
+ set_bit((uint8_t)j + 1U, &mgr->payload_mask);
+ } else {
+ clear_bit((uint8_t)j + 1U, &mgr->payload_mask);
+ }
+ }
+ /* Clear structure of last (now unused) payload. */
+ (void)memset(&mgr->payloads[MST_MAX_PAYLOAD - 1U], 0, sizeof(MST_drm_dp_payload));
+ mgr->proposed_vcpis[MST_MAX_PAYLOAD - 1U] = NULL;
+ clear_bit(MST_MAX_PAYLOAD, &mgr->payload_mask);
+ }
+ }
+}
+
+/**
+ * drm_dp_update_payload_part1() - Execute payload update part 1
+ * @mgr: manager to use.
+ *
+ * This iterates over all proposed virtual channels, and tries to
+ * allocate space in the link for them. For 0->slots transitions,
+ * this step just writes the VCPI to the MST device. For slots->0
+ * transitions, this writes the updated VCPIs and removes the
+ * remote VC payloads.
+ *
+ * after calling this the driver should generate ACT and payload
+ * packets.
+ */
+uint32_t DP_MST_MgrUpdatePayloadPart1(MST_drm_dp_topology_mgr *mgr)
+{
+ uint32_t ret = CDN_EOK;
+ uint32_t i;
+ int32_t cur_slots = 1;
+ MST_drm_dp_payload req_payload;
+ MST_drm_dp_port *port;
+ req_payload.payload_state = 0; /* TODO: kwitos, confirm it, initialize it prior to use */
+
+ for (i = 0; i < MST_MAX_PAYLOAD; i++) {
+
+ ret = solvePayloads(mgr, &req_payload, &port, cur_slots, i);
+ if (CDN_EOK != ret) {
+ break;
+ }
+
+ /* work out what is required to happen with this payload */
+ if (mgr->payloads[i].num_slots != req_payload.num_slots) {
+
+ ret = pushPayloadUpdate(mgr, port, &req_payload, i);
+
+ if (CDN_EOK == ret)
+ {
+ mgr->payloads[i].payload_state = req_payload.payload_state;
+ }
+ }
+ if (CDN_EOK == ret)
+ {
+ cur_slots += (int32_t)req_payload.num_slots;
+
+ if (port != NULL) {
+ DRM_DP_putPort(port);
+ }
+ }
+ }
+
+ if (ret == CDN_EOK) {
+ removeMarkedPayloads(mgr);
+ }
+
+ return ret;
+}
+
+/**
+ * drm_dp_update_payload_part2() - Execute payload update part 2
+ * @mgr: manager to use.
+ *
+ * This iterates over all proposed virtual channels, and tries to
+ * allocate space in the link for them. For 0->slots transitions,
+ * this step writes the remote VC payload commands. For slots->0
+ * this just resets some internal state.
+ */
+uint32_t DP_MST_MgrUpdatePayloadPart2(MST_drm_dp_topology_mgr *mgr)
+{
+ MST_drm_dp_port *port;
+ uint8_t i;
+ uint32_t ret = CDN_EOK;
+
+ for (i = 0; i < MST_MAX_PAYLOAD; i++) {
+
+ if (mgr->proposed_vcpis[i] == NULL) {
+ continue;
+ }
+ port = mgr->proposed_vcpis[i]->parent;
+
+ DbgMsg(DBG_GEN_MSG, DBG_FYI, "payload %d %d\n", i, mgr->payloads[i].payload_state);
+ if (mgr->payloads[i].payload_state == (int32_t)MST_PAYLOAD_LOCAL) {
+ ret = drm_dp_create_payload_step2(mgr, port, mgr->proposed_vcpis[i]->vcpi, &mgr->payloads[i]);
+ } else if (mgr->payloads[i].payload_state == (int32_t)MST_PAYLOAD_DELETE_LOCAL) {
+ mgr->payloads[i].payload_state = 0;
+ } else {
+ /* TODO: check other states */
+ }
+ if (ret != CDN_EOK) {
+ ret = CDN_EINVAL;
+ }
+ }
+ return (uint32_t)ret;
+}
+
+MST_drm_dp_payload *DP_MST_MgrGetPortPayload(MST_drm_dp_topology_mgr *mgr,
+ MST_drm_dp_port * port) {
+ uint8_t i;
+ MST_drm_dp_payload *payload = NULL;
+ MST_drm_dp_port *mport = NULL;
+
+ mport = DRM_DP_getValidatedPortRef(mgr, port);
+ if (mport != NULL) {
+ int32_t vcpi_value = mport->vcpi.vcpi - 1;
+ if (is64bBitSet(mgr->vcpi_mask, (uint32_t)vcpi_value)) {
+ for (i = 0; i < MST_MAX_PAYLOAD; i++) {
+ if ((mgr->payloads[i].vcpi == mport->vcpi.vcpi) &&
+ (is64bBitSet(mgr->payload_mask, (uint32_t)i))) {
+ payload = &mgr->payloads[i];
+ break;
+ }
+ }
+ }
+ DRM_DP_putPort(mport);
+ }
+ return payload;
+}
+
+void DP_MST_MgrSetPayloadBandwidth(MST_drm_dp_topology_mgr *mgr,
+ uint32_t symbolRate,
+ uint8_t laneCount) {
+
+ uint32_t pbn_div = (laneCount * symbolRate) / MST_LINK_RATE_MULTIPLIER; /* TODO kwitos: confirm */
+ mgr->pbn_div = (int32_t)pbn_div;
+ DbgMsg(DBG_GEN_MSG, DBG_FYI, "laneCount %d, symbolRate %d\n",
+ laneCount, symbolRate);
+}
+
+/**
+ * drm_dp_topology_mgr_set_mst() - Set the MST state for a topology manager
+ * @mgr: manager to set state for
+ * @mst_state: true to enable MST on this connector - false to disable.
+ *
+ * This is called by the driver when it detects an MST capable device plugged
+ * into a DP MST capable port, or when a DP MST capable device is unplugged.
+ */
+uint32_t DP_MST_MgrSetState(MST_drm_dp_topology_mgr *mgr, bool mst_state)
+{
+ uint32_t ret = CDN_EOK;
+ MST_drm_dp_branch *mstb = NULL;
+ MST_drm_dp_branch **primary = &(mgr->mst_primary);
+
+ if (mst_state == mgr->mst_state) {
+ /* CDN_EAGAIN is used to return CDN_EOK at the end, but skipping */
+ /* execution of code. */
+ ret = CDN_EAGAIN;
+ } else {
+ mgr->mst_state = mst_state;
+ /* set the device into MST mode */
+ if (mst_state) {
+ /* add initial branch device at LCT 1 */
+ mstb = DRM_DP_addBranchDevice(mgr, 1, NULL);
+ if (mstb == NULL) {
+ ret = CDN_ENOMEM;
+ }
+ if (CDN_EOK == ret) {
+ mstb->mgr = mgr;
+
+ /* give this the main reference */
+ *primary = mstb;
+ (*primary)->refcount++;
+
+ ret = drm_dp_dpcd_write_byte(mgr->aux,
+ MST_DPCD_MSTM_CTRL,
+ MST_DPCD_MST_EN | MST_DPCD_UP_REQ_EN | MST_DPCD_UPSTREAM_IS_SRC);
+ if (ret != CDN_EOK) {
+ ret = CDN_EIO;
+ } else {
+ MST_drm_dp_payload reset_pay;
+ reset_pay.start_slot = 0;
+ reset_pay.num_slots = 0x3f;
+ /*FIXME result of this function is not checked*/
+ ret = drm_dp_dpcd_write_payload(mgr, 0, &reset_pay);
+ }
+
+ }
+ } else {
+ /* disable MST on the device */
+ mstb = *primary;
+ *primary = NULL;
+ /* this can fail if the device is gone */
+ ret = drm_dp_dpcd_write_byte(mgr->aux, MST_DPCD_MSTM_CTRL, 0);
+ (void)memset(mgr->payloads, 0, MST_MAX_PAYLOAD * sizeof(MST_drm_dp_payload));
+ mgr->payload_mask = 0;
+ set_bit(0, &mgr->payload_mask);
+ mgr->vcpi_mask = 0;
+ }
+ }
+
+ if (mstb != NULL) {
+ DRM_DP_putBranchDevice(mstb);
+ }
+
+ return ((CDN_EAGAIN == ret) ? CDN_EOK : ret);
+}
+
+/**
+ * drm_dp_mst_hpd_irq() - MST hotplug IRQ notify
+ * @mgr: manager to notify irq for.
+ * @esi: 4 bytes from SINK_COUNT_ESI
+ * @handled: whether the hpd interrupt was consumed or not
+ *
+ * This should be called from the driver when it detects a short IRQ,
+ * along with the value of the DEVICE_SERVICE_IRQ_VECTOR_ESI0. The
+ * topology manager will process the sideband messages received as a result
+ * of this.
+ */
+void drm_dp_mst_hpd_irq(MST_drm_dp_topology_mgr *mgr, const uint8_t *esi,
+ bool *handled) {
+ uint8_t sc;
+ *handled = false;
+ sc = esi[0] & 0x3fU;
+
+ if (sc != mgr->sink_count) {
+ mgr->sink_count = sc;
+ *handled = true;
+ }
+
+ if ((esi[1] & DP_DOWN_REP_MSG_RDY) != 0U) {
+ drm_dp_mst_handle_down_rep(mgr);
+ *handled = true;
+ }
+
+ if ((esi[1] & DP_UP_REQ_MSG_RDY) != 0U) {
+ drm_dp_mst_handle_up_req(mgr);
+ *handled = true;
+ }
+
+}
+
+#define DDC_SEGMENT_ADDR 0x30U
+#define EDID_LENGTH 128U
+#define DDC_ADDR 0x50U
+
+uint32_t drm_do_probe_ddc_edid(MST_drm_dp_port *port, uint8_t *buf, uint32_t block,
+ uint8_t len)
+{
+ uint8_t start = (uint8_t)(block * EDID_LENGTH);
+ uint8_t segment = (uint8_t)block >> 1U;
+ uint8_t xfers = (segment != 0U) ? 3U : 2U;
+ uint8_t retries = 5;
+ uint32_t ret;
+
+ /*
+ * The core I2C driver will automatically retry the transfer if the
+ * adapter reports CDN_EAGAIN. However, we find that bit-banging transfers
+ * are susceptible to errors under a heavily loaded machine and
+ * generate spurious NAKs and timeouts. Retrying the transfer
+ * of the individual block a few times seems to overcome this.
+ */
+ do {
+ struct mst_i2c_message msgs[3];
+
+ msgs[0].address = DDC_SEGMENT_ADDR;
+ msgs[0].length = 1U;
+ msgs[0].data = &segment;
+
+ msgs[1].address = DDC_ADDR;
+ msgs[1].length = 1U;
+ msgs[1].data = &start;
+
+ msgs[2].address = DDC_ADDR;
+ msgs[2].length = len;
+ msgs[2].data = buf;
+
+ /*
+ * Avoid sending the segment addr to not upset non-compliant
+ * DDC monitors.
+ */
+ ret = drm_dp_mst_i2c_xfer(port, &msgs[3U - xfers], xfers);
+ retries--;
+ } while ((ret != xfers) && (retries > 0U));
+
+ return (ret == xfers) ? CDN_EOK : CDN_EINVAL;
+}
+
+static uint32_t drm_dp_init_vcpi(MST_drm_dp_topology_mgr *mgr,
+ MST_drm_dp_vcpi * vcpi,
+ uint32_t pbn,
+ uint32_t slots,
+ MST_drm_dp_port* port) {
+ uint32_t ret = CDN_EOK;
+
+ /* max. time slots - one slot for MTP header */
+ if (slots > 63U) {
+ ret = CDN_ENOSPC;
+ } else {
+ vcpi->pbn = (int32_t)pbn;
+ vcpi->aligned_pbn = (int32_t)slots * mgr->pbn_div;
+ vcpi->num_slots = (int32_t)slots;
+ vcpi->parent = port;
+ ret = drm_dp_mst_assign_payload_id(mgr, vcpi);
+ }
+ return ret;
+}
+
+/**
+ * drm_dp_atomic_find_vcpi_slots() - Find and add vcpi slots to the state
+ * @state: global atomic state
+ * @mgr: MST topology manager for the port
+ * @port: port to find vcpi slots for
+ * @pbn: bandwidth required for the mode in PBN
+ *
+ * RETURNS:
+ * Total slots in the atomic state assigned for this port or error
+ */
+/* int drm_dp_atomic_release_vcpi_slots(struct drm_atomic_state *state,
+ MST_drm_dp_topology_mgr *mgr,
+ int slots) */
+uint32_t DP_MST_MgrFindVcpiSlots(MST_drm_dp_topology_mgr *mgr,
+ MST_drm_dp_port *port, uint32_t pbn, uint8_t *slots, float32_t *fracSlots)
+{
+ uint32_t retVal = CDN_EOK;
+ MST_drm_dp_port *mport = NULL;
+
+ mport = DRM_DP_getValidatedPortRef(mgr, port);
+ if ((mport == NULL) || (fracSlots == NULL) || (slots == NULL)) {
+ retVal = CDN_EINVAL;
+ }
+ if (retVal == CDN_EOK) {
+ *fracSlots = (float32_t)pbn / (float32_t)mgr->pbn_div;
+ *slots = (uint8_t)(DIV_ROUND_UP(pbn, (uint32_t)mgr->pbn_div));
+
+ DbgMsg(DBG_GEN_MSG, DBG_FYI, "pbn %d, pbn_div %d\n",
+ pbn, mgr->pbn_div);
+
+ DbgMsg(DBG_GEN_MSG, DBG_FYI, "floating slots=%f\n", *fracSlots);
+
+ DbgMsg(DBG_GEN_MSG, DBG_FYI, "vcpi slots req=%d, avail=%d\n", *slots, mgr->avail_slots);
+
+ if (*slots > (uint8_t)mgr->avail_slots) {
+ retVal = CDN_ENOSPC;
+ } else {
+ mgr->avail_slots -= (int32_t)*slots;
+ DbgMsg(DBG_GEN_MSG, DBG_FYI, "vcpi slots avail=%d", mgr->avail_slots);
+ }
+ }
+
+ DRM_DP_putPort(mport);
+ return retVal;
+}
+
+/**
+ * drm_dp_mst_allocate_vcpi() - Allocate a virtual channel
+ * @mgr: manager for this port
+ * @port: port to allocate a virtual channel for.
+ * @pbn: payload bandwidth number to request
+ * @slots: returned number of slots for this PBN.
+ */
+uint32_t DP_MST_MgrAllocateVcpi(MST_drm_dp_topology_mgr *mgr,
+ MST_drm_dp_port *port, uint32_t pbn, uint8_t slots) {
+ uint32_t ret = CDN_EOK;
+ MST_drm_dp_port *mport = NULL;
+ mport = DRM_DP_getValidatedPortRef(mgr, port);
+
+ if ((mport != NULL) && (mport->vcpi.vcpi > 0)) {
+ DbgMsg(DBG_GEN_MSG, DBG_FYI,
+ "payload: vcpi %d already allocated for pbn %d - requested pbn %d\n",
+ mport->vcpi.vcpi, mport->vcpi.pbn, pbn);
+ if (pbn == (uint32_t)(mport->vcpi.pbn)) {
+ DRM_DP_putPort(mport);
+ }
+ }
+
+ if ((mport != NULL) && (pbn != (uint32_t)(mport->vcpi.pbn))) {
+ DbgMsg(DBG_GEN_MSG, DBG_FYI, "initing vcpi for pbn=%d slots=%d\n", pbn, mport->vcpi.num_slots);
+ ret = drm_dp_init_vcpi(mgr, &mport->vcpi, pbn, slots, mport);
+ if (ret != CDN_EOK) {
+ DbgMsg(DBG_GEN_MSG, DBG_CRIT, "failed to init vcpi slots=%d max=63 ret=%d\n",
+ DIV_ROUND_UP(pbn, mgr->pbn_div), ret);
+ } else {
+ DRM_DP_putPort(mport);
+ }
+ }
+
+ return ret;
+}
+
+/**
+ * drm_dp_mst_deallocate_vcpi() - deallocate a VCPI
+ * @mgr: manager for this port
+ * @portIn: unverified port to deallocate vcpi for
+ * */
+void DP_MST_MgrDeallocateVcpi(MST_drm_dp_topology_mgr *mgr,
+ MST_drm_dp_port * portIn) {
+ MST_drm_dp_port *port = DRM_DP_getValidatedPortRef(mgr, portIn);
+ if (NULL != port) {
+ drm_dp_mst_put_payload_id(mgr, port->vcpi.vcpi);
+ port->vcpi.num_slots = 0;
+ port->vcpi.pbn = 0;
+ port->vcpi.aligned_pbn = 0;
+ port->vcpi.vcpi = 0;
+ port->parent = NULL;
+ DRM_DP_putPort(port);
+ }
+}
+
+static uint32_t drm_dp_dpcd_write_payload(MST_drm_dp_topology_mgr *mgr,
+ int32_t id, const MST_drm_dp_payload *payload) {
+ uint8_t payload_alloc[3], status;
+ uint32_t ret;
+ uint32_t retries = 20;
+ bool readError = false;
+
+#ifdef IS_DEMO_TB
+ retries = 1;
+#endif
+
+ ret = drm_dp_dpcd_write_byte(mgr->aux, MST_DPCD_PAYLOAD_TABLE_UPDATE_STATUS,
+ MST_DPCD_PAYLOAD_TABLE_UPDATED);
+
+ if (CDN_EOK == ret)
+ {
+ payload_alloc[0] = (uint8_t)id;
+ payload_alloc[1] = (uint8_t)(payload->start_slot);
+ payload_alloc[2] = (uint8_t)(payload->num_slots);
+
+ ret = drm_dp_dpcd_write(mgr->aux, MST_DPCD_PAYLOAD_ALLOCATE_SET, payload_alloc,
+ 3);
+ if (ret != CDN_EOK) {
+ DbgMsg(DBG_GEN_MSG, DBG_CRIT, "failed to write payload allocation %d\n", ret);
+ }
+ }
+
+ if (CDN_EOK == ret) {
+ while (retries > 0U)
+ {
+ ret = drm_dp_dpcd_read_byte(mgr->aux, MST_DPCD_PAYLOAD_TABLE_UPDATE_STATUS,
+ &status);
+ if (ret != CDN_EOK) {
+ DbgMsg(DBG_GEN_MSG, DBG_CRIT, "failed to read payload table status %d\n", ret);
+ readError = true;
+ }
+
+ /* Break if read error occurred, of if desired bits are set. */
+ if (readError || (0U != (status & MST_DPCD_PAYLOAD_TABLE_UPDATED))) {
+ break;
+ }
+ retries--;
+ if (retries > 0U) {
+
+ CPS_DelayNs(10000000);
+ continue;
+ }
+ DbgMsg(DBG_GEN_MSG, DBG_CRIT, "status not set after read payload table status %d\n", status);
+ ret = CDN_EINVAL;
+ }
+ }
+ return ret;
+}
+
+/**
+ * drm_dp_check_act_status() - Check ACT handled status.
+ * @mgr: manager to use
+ *
+ * Check the payload status bits in the DPCD for ACT handled completion.
+ */
+uint32_t DP_MST_MgrCheckActStatus(MST_drm_dp_topology_mgr *mgr) {
+ uint8_t status;
+ uint32_t ret = CDN_EOK;
+ uint32_t count = 0;
+
+ do {
+ ret = drm_dp_dpcd_read_byte(mgr->aux, MST_DPCD_PAYLOAD_TABLE_UPDATE_STATUS,
+ &status);
+
+ if (ret != CDN_EOK) {
+ DbgMsg(DBG_GEN_MSG, DBG_CRIT, "failed to read payload table status %d\n", ret);
+ ret = CDN_EIO;
+ }
+
+ if (CDN_EOK == ret)
+ {
+ if (0U != (status & MST_DPCD_PAYLOAD_ACT_HANDLED)) {
+ break;
+ }
+ count++;
+ CPS_DelayNs(100000);
+ }
+
+ } while ((CDN_EOK == ret) && (count < 30U));
+
+ if (CDN_EOK == ret)
+ {
+ if ((status & MST_DPCD_PAYLOAD_ACT_HANDLED) == 0U) {
+ DbgMsg(DBG_GEN_MSG, DBG_CRIT, "failed to get ACT bit %d after %d retries\n", status, count);
+ ret = CDN_EINVAL;
+ }
+ }
+
+ return ret;
+}
+
+/**
+ * drm_dp_calc_pbn_mode() - Calculate the PBN for a mode.
+ * @dot_clock: dot clock for the mode
+ * @bpp: bpp for the mode.
+ *
+ * This uses the formula in the spec to calculate the PBN value for a mode.
+ */
+uint32_t DP_MST_MgrCalcPbnMode(uint32_t dot_clock, uint8_t bpp, bool fecEnabled)
+{
+ float64_t kbps;
+ float64_t numerator;
+ float64_t denominator;
+
+ DbgMsg(DBG_GEN_MSG, DBG_FYI, "clock %d, bpp %d\n",
+ dot_clock, bpp);
+ kbps = (float64_t)dot_clock * (float64_t)bpp;
+ numerator = 64.0 * 1006.0;
+ denominator = 54.0 * 8.0 * 1000.0 * 1000.0;
+ if (fecEnabled) {
+ numerator *= 100.0;
+ denominator *= (100.0 - 3.0);
+ }
+ kbps *= numerator;
+ return (uint32_t)ceil(kbps / denominator);
+}
+
+static uint32_t test_calc_pbn_mode(void)
+{
+ uint32_t res;
+ uint32_t retVal = CDN_EOK;
+ res = DP_MST_MgrCalcPbnMode(154000, 30, false);
+ if (res != 689U) {
+ DbgMsg(DBG_GEN_MSG, DBG_CRIT, "PBN calculation test failed - clock %d, bpp %d, expected PBN %d, actual PBN %d.\n",
+ 154000, 30, 689, res);
+ retVal = CDN_EINVAL;
+ }
+ if (CDN_EOK == retVal) {
+ res = DP_MST_MgrCalcPbnMode(234000, 30, false);
+ if (res != 1047U) {
+ DbgMsg(DBG_GEN_MSG, DBG_CRIT, "PBN calculation test failed - clock %d, bpp %d, expected PBN %d, actual PBN %d.\n",
+ 234000, 30, 1047, res);
+ retVal = CDN_EINVAL;
+ }
+ }
+ if (CDN_EOK == retVal) {
+ res = DP_MST_MgrCalcPbnMode(297000, 24, false);
+ if (res != 1063U) {
+ DbgMsg(DBG_GEN_MSG, DBG_CRIT, "PBN calculation test failed - clock %d, bpp %d, expected PBN %d, actual PBN %d.\n",
+ 297000, 24, 1063, res);
+ retVal = CDN_EINVAL;
+ }
+ }
+ return retVal;
+}
+
+/**
+ * drm_dp_topology_mgr_init - initialise a topology manager
+ * @mgr: manager struct to initialise
+ * @dev: device providing this structure - for i2c addition.
+ * @aux: DP helper aux channel to talk to this device
+ * @max_dpcd_transaction_bytes: hw specific DPCD transaction limit
+ * @max_payloads: maximum number of payloads this GPU can source
+ * @conn_base_id: the connector object ID the MST device is connected to.
+ *
+ */
+void DP_MST_MgrInit(MST_drm_dp_topology_mgr *mgr,
+ AUX_drm_dp *aux, uint32_t max_dpcd_transaction_bytes) {
+
+ mgr->tx_msg_downq = NULL;
+ mgr->int_enabled = false;
+ mgr->mst_primary = NULL;
+
+ mgr->aux = aux;
+ mgr->max_dpcd_transaction_bytes = max_dpcd_transaction_bytes;
+
+ (void)memset(mgr->payloads, 0, sizeof(mgr->payloads));
+ (void)memset(mgr->proposed_vcpis, 0, sizeof(mgr->proposed_vcpis));
+ mgr->payload_mask = 0;
+ mgr->vcpi_mask = 0;
+ set_bit(0, &mgr->payload_mask);
+
+ if (test_calc_pbn_mode() != 0U) {
+ DbgMsg(DBG_GEN_MSG, DBG_CRIT, "MST PBN self-test failed\n");
+ }
+
+ mgr->avail_slots = 63;
+ mgr->mst_state = false;
+
+}
+
+/* parasoft-end-suppress METRICS-41-3 */
diff --git a/packages/ti/drv/dss/src/csl/dp/src/dp_topology_mgr.h b/packages/ti/drv/dss/src/csl/dp/src/dp_topology_mgr.h
--- /dev/null
@@ -0,0 +1,121 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ *
+ * dp_topology_mgr.h
+ *
+ ******************************************************************************
+ */
+
+/*
+ * Copyright (C) 2014 Red Hat
+ *
+ * Permission to use, copy, modify, distribute, and sell this software and its
+ * documentation for any purpose is hereby granted without fee, provided that
+ * the above copyright notice appear in all copies and that both that copyright
+ * notice and this permission notice appear in supporting documentation, and
+ * that the name of the copyright holders not be used in advertising or
+ * publicity pertaining to distribution of the software without specific,
+ * written prior permission. The copyright holders make no representations
+ * about the suitability of this software for any purpose. It is provided "as
+ * is" without express or implied warranty.
+ *
+ * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
+ * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
+ * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
+ * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
+ * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
+ * OF THIS SOFTWARE.
+ */
+
+#ifndef TOPOLOGY_MGR
+#define TOPOLOGY_MGR
+
+#include "dp_sideband_msg.h"
+#include "dp_if.h"
+#include "dp_mst_if.h"
+#include "dp_mst_structs_if.h"
+#include "dp_sideband_msg_if.h"
+#include "dp_sideband_msg_structs_if.h"
+
+#ifdef IS_DEMO_TB
+#include "dp_demotb.h"
+#endif
+
+#include "cdn_stdtypes.h"
+#include "cdn_errno.h"
+#include "custom_types.h"
+#include "cdn_math.h"
+
+/* DP 1.2 Sideband message defines */
+/* peer device type - DP 1.2a Table 2-92 */
+#define DP_PEER_DEVICE_NONE 0x0U
+#define DP_PEER_DEVICE_SOURCE_OR_SST 0x1U
+#define DP_PEER_DEVICE_MST_BRANCHING 0x2U
+#define DP_PEER_DEVICE_SST_SINK 0x3U
+#define DP_PEER_DEVICE_DP_LEGACY_CONV 0x4U
+
+void DP_MST_MgrInit(MST_drm_dp_topology_mgr *mgr,
+ struct AUX_drm_dp_s * aux,
+ uint32_t max_dpcd_transaction_bytes);
+
+uint32_t DP_MST_MgrSetState(MST_drm_dp_topology_mgr *mgr, bool mst_state);
+
+void drm_dp_mst_hpd_irq(MST_drm_dp_topology_mgr *mgr, const uint8_t *esi, bool *handled);
+
+void DP_MST_MgrSetPayloadBandwidth(MST_drm_dp_topology_mgr *mgr,
+ uint32_t symbolRate,
+ uint8_t laneCount);
+
+uint32_t DP_MST_MgrCalcPbnMode(uint32_t dot_clock, uint8_t bpp, bool fecEnabled);
+
+uint32_t DP_MST_MgrAllocateVcpi(MST_drm_dp_topology_mgr *mgr,
+ MST_drm_dp_port *port, uint32_t pbn, uint8_t slots);
+
+void DP_MST_MgrDeallocateVcpi(MST_drm_dp_topology_mgr *mgr, MST_drm_dp_port *portIn);
+
+uint32_t DP_MST_MgrUpdatePayloadPart1(MST_drm_dp_topology_mgr *mgr);
+
+uint32_t DP_MST_MgrUpdatePayloadPart2(MST_drm_dp_topology_mgr *mgr);
+
+uint32_t DP_MST_MgrCheckActStatus(MST_drm_dp_topology_mgr *mgr);
+
+uint32_t DP_MST_MgrFindVcpiSlots(MST_drm_dp_topology_mgr *mgr,
+ MST_drm_dp_port *port, uint32_t pbn, uint8_t *slots, float32_t *fracSlots);
+
+MST_drm_dp_payload *DP_MST_MgrGetPortPayload(MST_drm_dp_topology_mgr *mgr,
+ MST_drm_dp_port * port);
+
+bool drm_dp_mst_handle_hpd(MST_drm_dp_topology_mgr *mgr);
+
+uint32_t drm_do_probe_ddc_edid(MST_drm_dp_port *port, uint8_t *buf, uint32_t block,
+ uint8_t len);
+
+#endif
diff --git a/packages/ti/drv/dss/src/csl/dp/src/dp_topology_utils.c b/packages/ti/drv/dss/src/csl/dp/src/dp_topology_utils.c
--- /dev/null
@@ -0,0 +1,855 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ *
+ * dp_topology_utils.c
+ *
+ ******************************************************************************
+ */
+
+/*
+ * Copyright (C) 2014 Red Hat.
+ *
+ * Permission to use, copy, modify, distribute, and sell this software and its
+ * documentation for any purpose is hereby granted without fee, provided that
+ * the above copyright notice appear in all copies and that both that copyright
+ * notice and this permission notice appear in supporting documentation, and
+ * that the name of the copyright holders not be used in advertising or
+ * publicity pertaining to distribution of the software without specific,
+ * written prior permission. The copyright holders make no representations
+ * about the suitability of this software for any purpose. It is provided "as
+ * is" without express or implied warranty.
+ *
+ * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
+ * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
+ * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
+ * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
+ * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
+ * OF THIS SOFTWARE.
+ */
+
+#include <stdlib.h>
+#include "dp_aux.h"
+#include "dp_topology_utils.h"
+#include "cdn_log.h"
+
+/*
+ * Clean branch parameters
+ * @param[in] mstBranch pointer to branch object to be cleaned
+ */
+static void cleanBranch(MST_drm_dp_branch* mstBranch)
+{
+ uint8_t i;
+ mstBranch->refcount = 0U;
+
+ /* clear relative address of branch */
+ for (i = 0U; i < 8U; i++) {
+ mstBranch->rad[i] = 0U;
+ }
+
+ mstBranch->lct = 0U;
+ mstBranch->num_ports = 0U;
+ mstBranch->msg_slots = 0;
+
+ /* clean ports */
+ for (i = 0U; i < MST_BRANCH_MAX_PORTS; i++) {
+ mstBranch->ports[i] = (MST_drm_dp_port){0};
+ }
+
+ mstBranch->port_parent = NULL;
+ mstBranch->mgr = NULL;
+ mstBranch->tx_slots[0] = NULL;
+ mstBranch->tx_slots[1] = NULL;
+ mstBranch->last_seqno = 0;
+ mstBranch->link_address_sent = false;
+
+ /* clean global unique identifier */
+ for (i = 0U; i < 16U; i++) {
+ mstBranch->guid[i] = 0U;
+ }
+}
+
+/*
+ * Set 'occupied' flag and return reference for branch
+ * @param[in] topologyManager pointer to topology manager object
+ * @return reference to branch if success
+ * @return NULL if not enough space for new branch
+ */
+/* parasoft-begin-suppress MISRA2012-RULE-8_13_a-4 "Pass parameter 'topologyManager' as const, DRV-3885' */
+static MST_drm_dp_branch* allocateBranch(MST_drm_dp_topology_mgr* topologyManager)
+{
+ uint8_t i;
+ MST_drm_dp_branch* branch = NULL;
+ MST_drm_dp_branch* retBranch = NULL;
+
+ /* looks for first empty slot */
+ for (i = 0U; i < MST_MAX_BRANCH_NUMBER; i++) {
+ branch = &(topologyManager->branch_list[i]);
+ if (branch->isOccupied == false) {
+ branch->isOccupied = true;
+ retBranch = branch;
+ break;
+ }
+ }
+
+ /* clean branch */
+ if (retBranch != NULL) {
+ cleanBranch(retBranch);
+ }
+
+ return retBranch;
+}
+/* parasoft-end-suppress MISRA2012-RULE-8_13_a-4 */
+
+/*
+ * Unset ocuppied flag for branch memory space
+ * @param[in] topologyManager pointer to topology manager object
+ * @param[in] mstBranch pointer to deallocated branch
+ */
+/* parasoft-begin-suppress MISRA2012-RULE-8_13_a-4 "Pass parameter 'topologyManager' as const, DRV-3885' */
+static void deallocateBranch(MST_drm_dp_topology_mgr* topologyManager,
+ const MST_drm_dp_branch* mstBranch)
+{
+ uint8_t i;
+ MST_drm_dp_branch* branch = NULL;
+
+ for (i = 0U; i < MST_MAX_BRANCH_NUMBER; i++) {
+ branch = &(topologyManager->branch_list[i]);
+ /* check if branches are the same */
+ if (branch == mstBranch) {
+ /* reset 'isOcuppied' flag */
+ branch->isOccupied = false;
+ break;
+ }
+ }
+}
+/* parasoft-end-suppress MISRA2012-RULE-8_13_a-4 */
+
+MST_drm_dp_branch *DRM_DP_addBranchDevice(MST_drm_dp_topology_mgr* topologyManager,
+ uint8_t linkCount,
+ uint8_t * relativeAddress)
+{
+ MST_drm_dp_branch *mstBranch;
+
+ /* get address of new branch */
+ mstBranch = allocateBranch(topologyManager);
+
+ if (mstBranch != NULL) {
+
+ mstBranch->lct = linkCount;
+
+ /* copy realtive address to branch */
+ if (linkCount > 1U) {
+ uint8_t size = linkCount / 2U;
+ (void)memcpy(mstBranch->rad, relativeAddress, size);
+ }
+
+ mstBranch->refcount = 1U;
+ }
+ return mstBranch;
+}
+
+/*
+ * Compare two branch references
+ * @param[in] mstBranch pointer to first branch
+ * @param[in] branchToFind pointer to second branch
+ * @return true if equal
+ * @return false if not equal
+ */
+static bool checkBranch(MST_drm_dp_branch* mstBranch,
+ const MST_drm_dp_branch *branchToFind)
+{
+ bool addressEqual = false;
+
+ if (branchToFind == mstBranch) {
+ mstBranch->refcount++;
+ addressEqual = true;
+ }
+
+ return addressEqual;
+}
+
+/*
+ * Looking for branch in device tree
+ * @param[in] mstBranch pointer to MST branch object
+ * @param[in] branchToFind pojnter to MST branch object which is searched
+ * @return reference to searched branch if success
+ * @return NULL if branch not found
+ */
+static MST_drm_dp_branch *getValidatedBranchRef(MST_drm_dp_branch* mstBranch,
+ const MST_drm_dp_branch *branchToFind)
+{
+ MST_drm_dp_branch* actualBranch = mstBranch;
+ MST_drm_dp_branch* retBranch = NULL;
+ uint8_t analyzedPortNumber = 0U;
+ uint8_t stack[MST_MAX_BRANCH_DEEP_LEVEL] = {0U};
+ uint8_t stackPointer = 0U;
+ MST_drm_dp_port* port;
+
+ bool foundBranch = checkBranch(mstBranch, branchToFind);
+
+ if (foundBranch) {
+ retBranch = mstBranch;
+ }
+
+ /* check if branch was founded */
+ while (retBranch == NULL) {
+
+ /* analyze each port for branch */
+ while (analyzedPortNumber < MST_BRANCH_MAX_PORTS) {
+ port = &actualBranch->ports[analyzedPortNumber];
+ analyzedPortNumber++;
+
+ if ((port->mstb != NULL) && (port->refcount > 0U)) {
+
+ foundBranch = checkBranch(port->mstb, branchToFind);
+
+ /* if actualBranch was not found, remember port number */
+ /* and check next actualBranch */
+ if (!foundBranch) {
+ stack[stackPointer] = analyzedPortNumber;
+ stackPointer++;
+ actualBranch = port->mstb;
+ analyzedPortNumber = 0U;
+ continue;
+ } else {
+ retBranch = port->mstb;
+ break;
+ }
+ }
+ }
+
+ /* break searching when no branches to check */
+ if ((stackPointer > 0U)) {
+ stackPointer--;
+ analyzedPortNumber = stack[stackPointer];
+ actualBranch = actualBranch->port_parent->parent;
+ } else {
+ break;
+ }
+
+ }
+
+ return retBranch;
+
+}
+
+MST_drm_dp_branch* DRM_DP_getValidatedBranchRef(MST_drm_dp_topology_mgr* topologyManager,
+ const MST_drm_dp_branch* mstBranch)
+{
+ MST_drm_dp_branch* retBranch = NULL;
+
+ /* test if topology has branch */
+ if (topologyManager->mst_primary != NULL) {
+ retBranch = getValidatedBranchRef(topologyManager->mst_primary, mstBranch);
+ }
+
+ return retBranch;
+}
+
+/* Check if ports are the same and have any references to itself
+ * @param[in] port pointer to first port
+ * @param[in] portToFind pointer to second port
+ * @return true if same
+ * @return false if not same
+ */
+static bool checkPort( MST_drm_dp_port* port,
+ const MST_drm_dp_port* portToFind)
+{
+ bool addressEqual = false;
+
+ if ((port == portToFind) && (port->refcount > 0U)) {
+ port->refcount++;
+ addressEqual = true;
+ }
+
+ return addressEqual;
+}
+
+/*
+ * Returns reference to searched port
+ * @param[in] mstBranch pointer to analyzed MST branch
+ * @param[in] portToFind pointer to searched port
+ * @return pointer to searched port if success
+ * @return NULL if cannot find port
+ */
+static MST_drm_dp_port *getPortRef(MST_drm_dp_branch* mstBranch,
+ const MST_drm_dp_port* portToFind)
+{
+ MST_drm_dp_branch* actualBranch = mstBranch;
+ MST_drm_dp_port* retPort = NULL;
+ uint8_t actualPortNumber = 0U;
+ uint8_t stack[MST_MAX_BRANCH_DEEP_LEVEL] = {0U};
+ uint8_t stackPointer = 0U;
+ MST_drm_dp_port* port;
+
+ bool check = false;
+
+ while (retPort == NULL) {
+
+ /* analyze for each port in branch */
+ while (actualPortNumber < MST_BRANCH_MAX_PORTS) {
+ port = &actualBranch->ports[actualPortNumber];
+ actualPortNumber++;
+
+ /* check if ports are the same */
+ check = checkPort(port, portToFind);
+
+ if (!check) {
+ /* put into stack when ports not the same but port have */
+ /* branch and no reference */
+ if ((port->mstb != NULL) && (port->refcount > 0U)) {
+ stack[stackPointer] = actualPortNumber;
+ stackPointer++;
+ actualBranch = port->mstb;
+ actualPortNumber = 0U;
+ continue;
+ }
+ } else {
+ retPort = port;
+ break;
+ }
+ }
+
+ /* break when any ports to check */
+ if (stackPointer > 0U) {
+ stackPointer--;
+ actualPortNumber = stack[stackPointer];
+ actualBranch = actualBranch->port_parent->parent;
+ } else {
+ break;
+ }
+
+ }
+
+ return retPort;
+}
+
+MST_drm_dp_port *DRM_DP_getValidatedPortRef(MST_drm_dp_topology_mgr *topologyManager,
+ const MST_drm_dp_port* port)
+{
+ MST_drm_dp_port *retPort = NULL;
+
+ /* test if topology have any (main) branch */
+ if (topologyManager->mst_primary != NULL) {
+ retPort = getPortRef(topologyManager->mst_primary, port);
+ }
+
+ return retPort;
+}
+
+/*
+ * Check if reference count for each port in branch is 0
+ * @patam[in] branch pointer to branch object
+ * @return true if branch have no references to ports
+ * @return false if not
+ */
+static bool checkIfBranchEmpty(const MST_drm_dp_branch* branch)
+{
+ uint8_t i;
+ bool retVal = true;
+
+ for (i = 0U; i < MST_BRANCH_MAX_PORTS; i++) {
+ if (branch->ports[i].refcount > 0U) {
+ retVal = false;
+ break;
+ }
+ }
+ return retVal;
+}
+
+/*
+ * Check if branch has reference to parent
+ * @param[in] branch pointer to branch object
+ * @return true if parent exists
+ * @return false if not exists
+ */
+static bool parentChecker(const MST_drm_dp_branch* branch)
+{
+ bool hasParent = false;
+
+ if (branch->port_parent != NULL) {
+ if (branch->port_parent->parent != NULL) {
+ hasParent = true;
+ }
+ }
+
+ return hasParent;
+}
+
+/*
+ * Check if branch's parent exists and has empty ports
+ * @param[in] branch pointer to branch object
+ * @return true if success
+ * @return false if parent have references
+ */
+static bool checkIfParentEmpty(const MST_drm_dp_branch* branch)
+{
+ bool hasParent = false;
+ bool isEmpty = false;
+
+ hasParent = parentChecker(branch);
+
+ if (hasParent) {
+ isEmpty = checkIfBranchEmpty(branch->port_parent->parent);
+ }
+
+ return isEmpty;
+}
+
+/*
+ * Free port
+ * @param[in] port pointer to port object
+ * @return NULL if success
+ * @return pointer to next branch which should be deallocated
+ */
+static MST_drm_dp_branch* freePort(MST_drm_dp_port*port);
+
+/*
+ * Deallocate memory space for branch
+ * @param[in] mstBranch pointer to branch
+ */
+static void removeBranch(MST_drm_dp_branch* mstBranch)
+{
+ MST_drm_dp_branch* branchStack[MST_MAX_BRANCH_DEEP_LEVEL] = {NULL};
+ uint8_t stackPointer = 0U;
+
+ MST_drm_dp_port* portParent = NULL;
+ MST_drm_dp_branch* branchParent = NULL;
+ MST_drm_dp_branch* branch = mstBranch;
+ bool isEmpty;
+
+ branchStack[0] = mstBranch;
+ stackPointer++;
+
+ while (branch != NULL) {
+ isEmpty = checkIfParentEmpty(branch);
+
+ if (isEmpty) {
+ portParent = branch->port_parent;
+ portParent->refcount--;
+
+ /* free ports of branch when reference count is 0 */
+ if (portParent->refcount == 0U) {
+ branchParent = freePort(portParent);
+
+ /* if branch parent should be deallocated, push branch into stack and */
+ /* analyze branch parent */
+ if (branchParent != NULL) {
+ branchStack[stackPointer] = branch;
+ branch = branchParent;
+ stackPointer++;
+ continue;
+ }
+ }
+ }
+ break;
+ }
+
+ /* deallocate branches from stack */
+ while (stackPointer > 0U) {
+ stackPointer--;
+ branch = branchStack[stackPointer];
+ deallocateBranch(branch->mgr, branch);
+ }
+
+}
+
+/*
+ * Assign 0 to portreference counter
+ * @param[in] port pointer to port object
+ * @return reference to branch if branch should be removed
+ * @return NULL if branch should be not removed
+ */
+static MST_drm_dp_branch* freePort(MST_drm_dp_port *port) {
+
+ MST_drm_dp_branch* mstBranch = port->parent;
+ MST_drm_dp_branch* retBranch = NULL;
+
+ mstBranch->refcount--;
+ if (mstBranch->refcount == 0U) {
+ retBranch = mstBranch;
+ }
+
+ /* clean reference count for port */
+ port->refcount = 0U;
+
+ return retBranch;
+}
+
+/*
+ * Drop messages from sideband slots for branch
+ * @param[in] mstBranch pointer to MST branch object
+ */
+static void dropSidebandTxSlotsMessages(MST_drm_dp_branch *mstBranch)
+{
+ /* test if first slot exists */
+ if (mstBranch->tx_slots[0] != NULL) {
+ mstBranch->tx_slots[0]->state = DRM_DP_SIDEBAND_TX_TIMEOUT;
+ mstBranch->tx_slots[0] = NULL;
+ }
+
+ /* test if second slot exists */
+ if (mstBranch->tx_slots[1] != NULL) {
+ mstBranch->tx_slots[1]->state = DRM_DP_SIDEBAND_TX_TIMEOUT;
+ mstBranch->tx_slots[1] = NULL;
+ }
+}
+
+/*
+ * Free (deallocate) memory for branch
+ * @param[in] mstBranch pointer to branch object
+ */
+static void freeBranch(MST_drm_dp_branch *mstBranch)
+{
+ dropSidebandTxSlotsMessages(mstBranch);
+
+ mstBranch->refcount--;
+
+ if (mstBranch->refcount == 0U) {
+ removeBranch(mstBranch);
+ }
+
+}
+
+/*
+ * Decrease reference counter for branch
+ * @param[in] pointer to branch object
+ * @return pointer to branch if should be deallocated
+ * @return NULL if branch should not be deallocated
+ */
+static MST_drm_dp_branch* putBranch(MST_drm_dp_branch* branch)
+{
+ MST_drm_dp_branch* retBranch = NULL;
+
+ branch->refcount--;
+ /* test if branch have any reference */
+ if (branch->refcount == 0U) {
+ branch->refcount = 1U;
+ retBranch = branch;
+ }
+
+ return retBranch;
+}
+
+/*
+ * Clean reference to device if branch
+ * @param[in] port pointer to port object
+ * @param[in] oldPdt peer device type
+ * @return pointer to branch if should be deallocated
+ * @return NULL if branch should not be deallocated
+ */
+static MST_drm_dp_branch* teardownPdt(MST_drm_dp_port *port, uint8_t oldPdt)
+{
+ MST_drm_dp_branch* retBranch = NULL;
+
+ if (oldPdt == DP_PEER_DEVICE_MST_BRANCHING) {
+ retBranch = putBranch(port->mstb);
+ port->mstb = NULL;
+ }
+
+ return retBranch;
+}
+
+/*
+ * Destroy port if not input
+ * @param[in] port pointer to port object
+ * @return pointer to branch if should be deallocated
+ * @return NULL if branch should not be deallocated
+ */
+static MST_drm_dp_branch* destroyPort(MST_drm_dp_port *port)
+{
+ MST_drm_dp_branch* retBranch = NULL;
+
+ /* test if port is output */
+ if (!port->input) {
+ port->vcpi.num_slots = 0;
+ retBranch = teardownPdt(port, port->pdt);
+ port->refcount = 0U;
+ }
+
+ return retBranch;
+}
+
+/*
+ * Decrease reference count for port
+ * @param[in] port pointer to port object
+ * @return pointer to branch if should be deallocated
+ * @return NULL if branch should not be deallocated
+ */
+static MST_drm_dp_branch* putPort(MST_drm_dp_port *port)
+{
+ MST_drm_dp_branch* retBranch = NULL;
+
+ port->refcount--;
+ if (port->refcount == 0U) {
+ retBranch = destroyPort(port);
+ }
+
+ return retBranch;
+}
+
+/*
+ * Destroy branch
+ * @param[in] mstb pointer to branch object
+ */
+/* parasoft-begin-suppress METRICS-36-3 "Function is called from more than 5 functions, DRV-3823" */
+static void destroyBranch(MST_drm_dp_branch* mstb)
+{
+ uint8_t stackPointer = 0U;
+ MST_drm_dp_branch* branch = mstb;
+ MST_drm_dp_branch* childBranch = mstb;
+ MST_drm_dp_branch* branchParent = NULL;
+ uint8_t i = 0U;
+ uint8_t stack[16U] = {0U};
+
+ while (true) {
+
+ while (i < MST_BRANCH_MAX_PORTS) {
+ childBranch = putPort(&(branch->ports[i]));
+ i++;
+
+ /* if branch have child, push into stack and analyze child */
+ if (childBranch != NULL) {
+ stack[stackPointer] = i;
+ stackPointer++;
+ branch = childBranch;
+ i = 0U;
+ continue;
+ }
+ }
+
+ /* mstb is top of device tree */
+ if (branch != mstb) {
+ branchParent = branch->port_parent->parent;
+ }
+
+ freeBranch(branch);
+
+ /* break if any branch to check */
+ if (stackPointer > 0U) {
+ stackPointer--;
+ i = stack[stackPointer];
+ branch = branchParent;
+
+ } else {
+ break;
+ }
+
+ }
+}
+/* parasoft-end-suppress METRICS-36-3 */
+
+void DRM_DP_putBranchDevice(MST_drm_dp_branch *mstBranch)
+{
+ MST_drm_dp_branch* branch = NULL;
+
+ if (mstBranch != NULL) {
+ branch = putBranch(mstBranch);
+ }
+
+ if (branch != NULL) {
+ destroyBranch(branch);
+ }
+}
+
+void DRM_DP_teardownPort(MST_drm_dp_port *port, uint8_t oldPeerDeviceType)
+{
+ MST_drm_dp_branch* branch = NULL;
+
+ /* check if port exists */
+ if (port != NULL) {
+ branch = teardownPdt(port, oldPeerDeviceType);
+ }
+
+ /* destroy branch */
+ if (branch != NULL) {
+ destroyBranch(branch);
+ }
+}
+
+void DRM_DP_putPort(MST_drm_dp_port *port)
+{
+ MST_drm_dp_branch* branch = NULL;
+
+ /* here we analyze main port, if we need destroy branch, do it again for */
+ /* each port in destroyed branch */
+ if (port != NULL) {
+ branch = putPort(port);
+ }
+
+ if (branch != NULL) {
+ destroyBranch(branch);
+ }
+
+}
+
+/* parasoft-begin-suppress MISRA2012-RULE-8_13_a-4 "Pass parameter 'topologyManager' as const, DRV-3885" */
+MST_drm_dp_branch *DRM_DP_getBranchDevice(MST_drm_dp_topology_mgr *topologyManager,
+ uint8_t linkCount,
+ const uint8_t * relativeAddress)
+{
+ const uint8_t PortNumberMask = 0x0FU;
+ MST_drm_dp_branch *mstb = topologyManager->mst_primary;
+ MST_drm_dp_port port;
+ uint8_t i;
+ uint8_t j;
+ uint8_t shift;
+ uint8_t portNumber;
+
+ for (i = 0U; i < (linkCount - 1U); i++) {
+
+ if (mstb == NULL) {
+ DbgMsg(DBG_GEN_MSG, DBG_WARN,
+ "WARNING: Failed to lookup MSTB with linkCount %d, relativeAddress %02x\n",
+ linkCount, relativeAddress[0]);
+ break;
+ }
+
+ shift = ((i % 2U) != 0U) ? 0U : 4U;
+
+ /* parasoft-begin-suppress MISRA2012-RULE-12_2-2 "Shifting operation should be checked, DRV-3822" */
+ portNumber = (relativeAddress[i / 2U] >> shift) & PortNumberMask;
+ /* parasoft-begin-suppress MISRA2012-RULE-12_2-2 */
+
+ for (j = 0U; j < MST_BRANCH_MAX_PORTS; j++) {
+ port = mstb->ports[j];
+ if ((port.refcount > 0U) && (port.port_num == portNumber)) {
+ mstb = port.mstb;
+ break;
+ }
+ }
+ }
+
+ /* increase reference count */
+ if (mstb != NULL) {
+ mstb->refcount++;
+ }
+
+ return mstb;
+}
+/* parasoft-end-suppress MISRA2012-RULE-8_13_a-4 */
+
+/* parasoft-begin-suppress MISRA2012-RULE-8_13_a-4 "Pass parameter 'mstBranch as const, DRV-3885" */
+MST_drm_dp_port* DRM_DP_getPort(MST_drm_dp_branch *mstBranch,
+ uint8_t portNumber) {
+ uint8_t i;
+ MST_drm_dp_port* currPort;
+ MST_drm_dp_port* retPort = NULL;
+
+ for (i = 0U; i < MST_BRANCH_MAX_PORTS; i++) {
+ currPort = &(mstBranch->ports[i]);
+ /* check if port have references and number of port equals */
+ if ((currPort->refcount > 0U) && (currPort->port_num == portNumber)) {
+ currPort->refcount++;
+ retPort = &(mstBranch->ports[i]);
+ break;
+ }
+ }
+
+ return retPort;
+}
+/* parasoft-end-suppress MISRA2012-RULE-8_13_a-4 */
+
+/*
+ * Looking for device using GUID
+ * @param[in] mstBranch pointer to branch object
+ * @param[in] guid pointer to global unique identifier
+ */
+static MST_drm_dp_branch *getBranchDeviceByGuidHelper(MST_drm_dp_branch *mstBranch,
+ uint8_t * guid)
+{
+ MST_drm_dp_branch *foundBranch = NULL;
+ MST_drm_dp_branch *actualBranch = mstBranch;
+ MST_drm_dp_port* actualPort = NULL;
+ uint8_t stack[MST_MAX_BRANCH_DEEP_LEVEL] = {0U};
+ uint8_t stackPointer = 0U;
+ uint8_t actualPortNumber = 0U;
+
+ uint8_t memoryEqual = (uint8_t)(memcmp(mstBranch->guid, guid, 16));
+
+ while (memoryEqual != 0U) {
+
+ while (actualPortNumber < MST_BRANCH_MAX_PORTS) {
+
+ actualPort = &(actualBranch->ports[actualPortNumber]);
+ actualPortNumber++;
+
+ /* test if port have references */
+ if (actualPort->refcount > 0U) {
+
+ /* test if port have connected branch */
+ if (actualPort->mstb == NULL) {
+ continue;
+ }
+
+ /* check if guid equals */
+ memoryEqual = (uint8_t)(memcmp(actualPort->mstb->guid, guid, 16));
+
+ if (memoryEqual == 0U) {
+ foundBranch = actualPort->mstb;
+ break;
+ }
+
+ /* push port number into stack an analyze next branch */
+ actualBranch = actualPort->mstb;
+ stack[stackPointer] = actualPortNumber;
+ stackPointer++;
+ actualPortNumber = 0U;
+ }
+ }
+
+ /* if any port to check, pop it from stack */
+ if (stackPointer > 0U) {
+ stackPointer--;
+ actualBranch = actualBranch->port_parent->parent;
+ actualPortNumber = stack[stackPointer];
+ } else {
+ break;
+ }
+ }
+
+ return foundBranch;
+}
+
+MST_drm_dp_branch *DRM_DP_getBranchDeviceByGuid(MST_drm_dp_topology_mgr *topologyManager,
+ uint8_t * guid)
+{
+ MST_drm_dp_branch *mstb;
+
+ mstb = getBranchDeviceByGuidHelper(topologyManager->mst_primary, guid);
+
+ /* increase reference counter for branch if not NUL */
+ if (mstb != NULL) {
+ mstb->refcount++;
+ }
+
+ return mstb;
+}
diff --git a/packages/ti/drv/dss/src/csl/dp/src/dp_topology_utils.h b/packages/ti/drv/dss/src/csl/dp/src/dp_topology_utils.h
--- /dev/null
@@ -0,0 +1,151 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ *
+ * dp_topology_utils.h
+ *
+ ******************************************************************************
+ */
+
+/*
+ * Copyright C 2014 Red Hat.
+ *
+ * Permission to use, copy, modify, distribute, and sell this software and its
+ * documentation for any purpose is hereby granted without fee, provided that
+ * the above copyright notice appear in all copies and that both that copyright
+ * notice and this permission notice appear in supporting documentation, and
+ * that the name of the copyright holders not be used in advertising or
+ * publicity pertaining to distribution of the software without specific,
+ * written prior permission. The copyright holders make no representations
+ * about the suitability of this software for any purpose. It is provided "as
+ * is" without express or implied warranty.
+ *
+ * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
+ * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
+ * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
+ * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
+ * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
+ * OF THIS SOFTWARE.
+ */
+
+/* parasoft-begin-suppress METRICS-36-3 "Function is called from more than 5 different functions, DRV-3823" */
+
+#ifndef DP_TOPOLOGY_UTILS_H_
+#define DP_TOPOLOGY_UTILS_H_
+
+#include "dp_mst_if.h"
+#include "dp_mst_structs_if.h"
+#include "dp_topology_mgr.h"
+
+/*
+ * Returns address to new branch device
+ * @param[in] topologyManager pointer to topology manager object
+ * @param[in] linkCount number of links for branch
+ * @param[in] relativeAddress pointer to buffer with relative address of branch
+ * @return pointer to branch if success
+ * @return NULL if no space for new branch
+ */
+MST_drm_dp_branch *DRM_DP_addBranchDevice(MST_drm_dp_topology_mgr* topologyManager,
+ uint8_t linkCount,
+ uint8_t * relativeAddress);
+
+/* Looking for branch in topology
+ * @param[in] toplogyManager pointer to topology object
+ * @param[in] mstBranch pointer to searched branch
+ * @return pointer to founded branch if success
+ * @return NULL if branch is not in topology
+ */
+MST_drm_dp_branch *DRM_DP_getValidatedBranchRef(MST_drm_dp_topology_mgr *topologyManager,
+ const MST_drm_dp_branch *mstBranch);
+
+/*
+ * Looking for port in topology
+ * @param[in] topologyManager pointer to topology object
+ * @param[in] port pointer to searched port
+ * @return pointer to searched port if success
+ * @return NULL if port is not in topology
+ */
+MST_drm_dp_port *DRM_DP_getValidatedPortRef(MST_drm_dp_topology_mgr *topologyManager,
+ const MST_drm_dp_port * port);
+
+/*
+ * Return reference to searched branch
+ * @param[in] topologyManager pointer to topology object
+ * @param[in] linkCount number of links for branch
+ * @param[in] relativeAddress pointer to buffer with relative address of branch
+ * @return pointer to branch if success
+ * @return NULL if branch not found
+ */
+MST_drm_dp_branch *DRM_DP_getBranchDevice(MST_drm_dp_topology_mgr* topologyManager,
+ uint8_t linkCount,
+ const uint8_t* relativeAddress);
+
+/*
+ * Decrease reference count for branch and deallocate branches if should
+ * @param[in] mstBranch pointer to branch object
+ */
+void DRM_DP_putBranchDevice(MST_drm_dp_branch *mstBranch);
+
+/*
+ * Decrease reference count for port and deallocate branches if should
+ * @param[in] port pointer to port object
+ */
+void DRM_DP_putPort(MST_drm_dp_port *port);
+
+/*
+ * Return reference to searched port
+ * @param[in] mstBranch pointer to branch object
+ * @param[in] portNumber number of port
+ * @return pointer to port if success
+ * @return NULL if port not found
+ */
+MST_drm_dp_port *DRM_DP_getPort(MST_drm_dp_branch *mstBranch, uint8_t portNumber);
+
+/*
+ * Remove reference to branch in port when branch type is oldPeerDEviceType
+ * and deallocate branches if should
+ * @param[in] port pointer to port object
+ * @param[in] oldPeerDeviceType peerDeviceType for port
+ */
+void DRM_DP_teardownPort(MST_drm_dp_port *port, uint8_t oldPeerDeviceType);
+
+/*
+ * Find reference to branch using GUID
+ * @param[in] topologyManager pointer to topology object
+ * @param[in] guid pointer to GUID buffer
+ * @return reference to branch if found
+ * @return NULL if not found
+ * */
+MST_drm_dp_branch *DRM_DP_getBranchDeviceByGuid(MST_drm_dp_topology_mgr *topologyManager,
+ uint8_t * guid);
+
+#endif /* DP_TOPOLOGY_UTILS_H_ */
+
+/* parasoft-end-suppress METRICS-36-3 */
diff --git a/packages/ti/drv/dss/src/csl/dp/src/dp_transaction.c b/packages/ti/drv/dss/src/csl/dp/src/dp_transaction.c
--- /dev/null
@@ -0,0 +1,1520 @@
+/* parasoft-begin-suppress MISRA2012-RULE-1_1_a_c90-2 "C90 - limits" */
+/******************************************************************************
+ *
+ * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ *
+ * dp_transaction.c
+ *
+ ******************************************************************************
+ */
+
+/*
+ * Copyright (C) 2014 Red Hat
+ *
+ * Permission to use, copy, modify, distribute, and sell this software and its
+ * documentation for any purpose is hereby granted without fee, provided that
+ * the above copyright notice appear in all copies and that both that copyright
+ * notice and this permission notice appear in supporting documentation, and
+ * that the name of the copyright holders not be used in advertising or
+ * publicity pertaining to distribution of the software without specific,
+ * written prior permission. The copyright holders make no representations
+ * about the suitability of this software for any purpose. It is provided "as
+ * is" without express or implied warranty.
+ *
+ * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
+ * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
+ * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
+ * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
+ * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
+ * OF THIS SOFTWARE.
+ */
+
+#include <stdlib.h>
+#include <cdn_log.h>
+#include "cps.h"
+#include "dp_aux.h"
+#include "dp_aux_if.h"
+#include "dp_transaction.h"
+#include "dp_sideband_msg_if.h"
+#include "dp_topology_utils.h"
+
+/* parasoft-begin-suppress METRICS-41-3 "Number of blocks of comments per statement" */
+/* parasoft-begin-suppress METRICS-36-3 "Function called from more than 5 different functions, DRV-3823" */
+
+static uint32_t drm_dp_send_dpcd_write(MST_drm_dp_topology_mgr *mgr,
+ MST_drm_dp_port *port,
+ uint32_t offset, uint8_t size, uint8_t *bytes);
+
+static void drm_dp_send_enum_path_resources(MST_drm_dp_topology_mgr *mgr,
+ MST_drm_dp_branch *mstb, MST_drm_dp_port *port);
+
+static void drm_dp_send_link_address(MST_drm_dp_topology_mgr *topologyManager,
+ MST_drm_dp_branch * mstb);
+
+static bool drm_dp_validate_guid(uint8_t *guid) {
+ int32_t i;
+ bool ret = false;
+
+ for (i = 0; i < 16; i++) {
+ if (guid[i] != 0U) {
+ ret = true;
+ }
+ }
+
+ if (!ret) {
+ for (i = 0; i < 16; i++) {
+ guid[i] = (uint8_t)i;
+ }
+ }
+ return ret;
+}
+
+static void drm_dp_check_mstb_guid(MST_drm_dp_branch *mstb, uint8_t *guid) {
+
+ (void)memcpy(mstb->guid, guid, 16);
+ if (!drm_dp_validate_guid(mstb->guid)) {
+ if (mstb->port_parent != NULL) {
+ (void)drm_dp_send_dpcd_write(mstb->mgr, mstb->port_parent,
+ DP_GUID, 16U, mstb->guid);
+ } else {
+ (void)drm_dp_dpcd_write(mstb->mgr->aux,
+ DP_GUID, mstb->guid, 16);
+ }
+ }
+}
+
+static void encode_sb_req_alloc_payload(const SBM_drm_dp_sideband_msg_req_body *req, uint8_t *buf,
+ uint8_t *idx) {
+ const SBM_drm_dp_allocate_payload *allocate_payload = &req->u.allocate_payload;
+ uint8_t i;
+
+ buf[*idx] = (uint8_t) ((allocate_payload->port_number & 0xfU) << 4U)
+ | (allocate_payload->number_sdp_streams & 0xfU);
+ buf[*idx + 1U] = (allocate_payload->vcpi & 0x7fU);
+ buf[*idx + 2U] = (uint8_t) (allocate_payload->pbn >> 8);
+ buf[*idx + 3U] = (uint8_t) (allocate_payload->pbn & 0xffU);
+ (*idx) += 4U;
+ for (i = 0U; i < (allocate_payload->number_sdp_streams / 2U); i++) {
+ buf[*idx] = ((allocate_payload->sdp_stream_sink[i * 2U] & 0xfU) << 4)
+ | (allocate_payload->sdp_stream_sink[(i * 2U) + 1U] & 0xfU);
+ (*idx)++;
+ }
+ if ((allocate_payload->number_sdp_streams & 1U) != 0U) {
+ uint8_t j = allocate_payload->number_sdp_streams - 1U;
+ buf[*idx] = (allocate_payload->sdp_stream_sink[j] & 0xfU) << 4;
+ (*idx)++;
+ }
+}
+
+static void encode_sb_req_rem_dpcd_read(const SBM_drm_dp_sideband_msg_req_body *req, uint8_t *buf,
+ uint8_t *idx) {
+ const SBM_drm_dp_remote_dpcd_read *remote_dpcd_read = &req->u.dpcd_read;
+
+ buf[*idx] = (remote_dpcd_read->port_number & 0xfU) << 4;
+ buf[*idx] |= (uint8_t) (((remote_dpcd_read->dpcd_address & 0xf0000U) >> 16) & 0xfU);
+ (*idx)++;
+ buf[*idx] = (uint8_t) ((remote_dpcd_read->dpcd_address & 0xff00U) >> 8);
+ (*idx)++;
+ buf[*idx] = (uint8_t) (remote_dpcd_read->dpcd_address & 0xffU);
+ (*idx)++;
+ buf[*idx] = remote_dpcd_read->num_bytes;
+ (*idx)++;
+}
+
+static void encode_sb_req_rem_dpcd_write(const SBM_drm_dp_sideband_msg_req_body *req, uint8_t *buf,
+ uint8_t *idx) {
+ const SBM_drm_dp_remote_dpcd_write *remote_dpcd_write = &req->u.dpcd_write;
+
+ buf[*idx] = (remote_dpcd_write->port_number & 0xfU) << 4;
+ buf[*idx] |= (uint8_t) (((remote_dpcd_write->dpcd_address & 0xf0000U) >> 16) & 0xfU);
+ (*idx)++;
+ buf[*idx] = (uint8_t) ((remote_dpcd_write->dpcd_address & 0xff00U) >> 8);
+ (*idx)++;
+ buf[*idx] = (uint8_t) (remote_dpcd_write->dpcd_address & 0xffU);
+ (*idx)++;
+ buf[*idx] = (remote_dpcd_write->num_bytes);
+ (*idx)++;
+ (void) memcpy(&buf[*idx], remote_dpcd_write->bytes, remote_dpcd_write->num_bytes);
+ *idx += remote_dpcd_write->num_bytes;
+}
+
+static void encode_sb_req_rem_i2c_read(const SBM_drm_dp_sideband_msg_req_body *req, uint8_t *buf,
+ uint8_t *idx) {
+ const SBM_drm_dp_remote_i2c_read *remote_i2c_read = &req->u.i2c_read;
+ uint8_t i;
+
+ buf[*idx] = (((remote_i2c_read->port_number & 0xfU) << 4)
+ | (remote_i2c_read->num_transactions & 0x3U));
+ (*idx)++;
+ for (i = 0U; i < (remote_i2c_read->num_transactions & 0x3U); i++) {
+ const SBM_drm_dp_transactions *this_transaction = &remote_i2c_read->transactions[i];
+
+ buf[*idx] = this_transaction->i2c_dev_id & 0x7fU;
+ buf[*idx + 1U] = this_transaction->num_bytes;
+ (*idx) += 2U;
+ (void) memcpy(&buf[*idx], this_transaction->bytes,
+ this_transaction->num_bytes);
+ *idx += this_transaction->num_bytes;
+
+ buf[*idx] = (((this_transaction->no_stop_bit & 0x1U) << 5)
+ | (this_transaction->i2c_transaction_delay & 0xfU));
+ (*idx)++;
+ }
+ buf[*idx] = (remote_i2c_read->read_i2c_device_id) & 0x7fU;
+ buf[*idx + 1U] = (remote_i2c_read->num_bytes_read);
+ (*idx) += 2U;
+}
+
+static void encode_sb_req_rem_i2c_write(const SBM_drm_dp_sideband_msg_req_body *req, uint8_t *buf,
+ uint8_t *idx) {
+ const SBM_drm_dp_remote_i2c_write *remote_i2c_write = &req->u.i2c_write;
+
+ buf[*idx] = (remote_i2c_write->port_number & 0xfU) << 4;
+ (*idx)++;
+ buf[*idx] = (remote_i2c_write->write_i2c_device_id) & 0x7fU;
+ (*idx)++;
+ buf[*idx] = (remote_i2c_write->num_bytes);
+ (*idx)++;
+ (void) memcpy(&buf[*idx], remote_i2c_write->bytes, remote_i2c_write->num_bytes);
+ *idx += remote_i2c_write->num_bytes;
+}
+
+static void drm_dp_encode_sideband_req(const SBM_drm_dp_sideband_msg_req_body *req,
+ SBM_drm_dp_sideband_msg_tx * raw) {
+ uint8_t idx = 0;
+ uint8_t *buf = raw->msg;
+ buf[idx] = req->req_type & 0x7fU;
+ idx++;
+
+ switch (req->req_type) {
+ case DP_ENUM_PATH_RESOURCES:
+ buf[idx] = (req->u.port_num.port_number & 0xfU) << 4;
+ idx++;
+ break;
+ case DP_ALLOCATE_PAYLOAD:
+ encode_sb_req_alloc_payload(req, buf, &idx);
+ break;
+ case DP_REMOTE_DPCD_READ:
+ encode_sb_req_rem_dpcd_read(req, buf, &idx);
+ break;
+ case DP_REMOTE_DPCD_WRITE:
+ encode_sb_req_rem_dpcd_write(req, buf, &idx);
+ break;
+ case DP_REMOTE_I2C_READ:
+ encode_sb_req_rem_i2c_read(req, buf, &idx);
+ break;
+ case DP_REMOTE_I2C_WRITE:
+ encode_sb_req_rem_i2c_write(req, buf, &idx);
+ break;
+
+ default:
+ DbgMsg(DBG_GEN_MSG, DBG_CRIT, "Unknown req type %d \n", req->req_type);
+ break;
+ }
+ raw->cur_len = idx;
+}
+
+static void drm_dp_encode_sideband_reply(
+ const SBM_drm_dp_sideband_msg_reply_body *rep,
+ SBM_drm_dp_sideband_msg_tx * raw) {
+ uint8_t idx = 0;
+ uint8_t *buf = raw->msg;
+
+ buf[idx] = ((rep->reply_type & 0x1U) << 7) | (rep->req_type & 0x7fU);
+ idx++;
+
+ raw->cur_len = idx;
+}
+
+static bool drm_dp_sb_parse_link_addr_iterative(
+ SBM_drm_dp_sideband_msg_rx *raw,
+ SBM_drm_dp_sideband_msg_reply_body *repmsg,
+ uint32_t i, uint32_t *idx) {
+ bool ret = true;
+
+ if ((raw->msg[*idx] & 0x80U) != 0U) {
+ repmsg->u.link_addr.ports[i].input_port = 1;
+ }
+
+ repmsg->u.link_addr.ports[i].peer_device_type = (raw->msg[*idx] >> 4) & 0x7U;
+ repmsg->u.link_addr.ports[i].port_number = (raw->msg[*idx] & 0xfU);
+
+ (*idx)++;
+ if (*idx <= raw->curlen) {
+ repmsg->u.link_addr.ports[i].mcs = ((raw->msg[*idx] >> 7) & 0x1U) != 0U;
+ repmsg->u.link_addr.ports[i].ddps = ((raw->msg[*idx] >> 6) & 0x1U) != 0U;
+ if (repmsg->u.link_addr.ports[i].input_port == 0) {
+ repmsg->u.link_addr.ports[i].legacy_device_plug_status =
+ ((raw->msg[*idx] >> 5) & 0x1U) != 0U;
+ }
+ }
+ (*idx)++;
+ if ((*idx <= raw->curlen) && (repmsg->u.link_addr.ports[i].input_port == 0)) {
+ repmsg->u.link_addr.ports[i].dpcd_revision = (raw->msg[*idx]);
+ (*idx)++;
+ if (*idx <= raw->curlen) {
+ (void) memcpy(repmsg->u.link_addr.ports[i].peer_guid, &raw->msg[*idx], 16);
+ }
+ *idx += 16U;
+ if (*idx <= raw->curlen) {
+ repmsg->u.link_addr.ports[i].num_sdp_streams = (raw->msg[*idx] >> 4) & 0xfU;
+ repmsg->u.link_addr.ports[i].num_sdp_stream_sinks = (raw->msg[*idx] & 0xfU);
+ (*idx)++;
+ }
+ }
+
+ if (*idx > raw->curlen) {
+ ret = false;
+ }
+ return ret;
+}
+
+static bool drm_dp_sideband_parse_link_address(
+ SBM_drm_dp_sideband_msg_rx * raw,
+ SBM_drm_dp_sideband_msg_reply_body *repmsg) {
+
+ bool ret = true;
+ uint32_t idx = 1;
+ uint32_t i;
+ (void) memcpy(repmsg->u.link_addr.guid, &raw->msg[idx], 16);
+ idx += 16U;
+ repmsg->u.link_addr.nports = raw->msg[idx] & 0xfU;
+ idx++;
+ if (idx > raw->curlen) {
+ ret = false;
+ }
+ for (i = 0; (i < repmsg->u.link_addr.nports) && ret; i++) {
+ ret = drm_dp_sb_parse_link_addr_iterative(raw, repmsg, i, &idx);
+ }
+
+ if (!ret) {
+ DbgMsg(DBG_GEN_MSG, DBG_CRIT, "link address reply parse length fail %d %d\n", idx,
+ raw->curlen);
+ }
+ return ret;
+}
+
+static bool sideband_parse_remote_dpcd_read(
+ SBM_drm_dp_sideband_msg_rx * raw,
+ SBM_drm_dp_sideband_msg_reply_body *repmsg) {
+ bool ret;
+ uint32_t idx = 1;
+ repmsg->u.remote_dpcd_read_ack.port_number = raw->msg[idx] & 0xfU;
+ idx++;
+ if (idx > raw->curlen) {
+ DbgMsg(DBG_GEN_MSG, DBG_CRIT, "link address reply parse length fail %d %d\n", idx,
+ raw->curlen);
+ ret = false;
+ } else {
+ repmsg->u.remote_dpcd_read_ack.num_bytes = raw->msg[idx];
+ idx++;
+ (void)memcpy(repmsg->u.remote_dpcd_read_ack.bytes, &raw->msg[idx],
+ repmsg->u.remote_dpcd_read_ack.num_bytes);
+ ret = true;
+ }
+ return ret;
+}
+
+static bool sideband_parse_remote_dpcd_write(
+ const SBM_drm_dp_sideband_msg_rx * raw,
+ SBM_drm_dp_sideband_msg_reply_body *repmsg) {
+ bool ret;
+ uint32_t idx = 1;
+ repmsg->u.remote_dpcd_write_ack.port_number = raw->msg[idx] & 0xfU;
+ idx++;
+ if (idx > raw->curlen) {
+ ret = false;
+ DbgMsg(DBG_GEN_MSG, DBG_CRIT, "parse length fail %d %d\n", idx, raw->curlen);
+ } else {
+ ret = true;
+ }
+ return ret;
+}
+
+static bool drm_dp_sideband_parse_remote_i2c_read_ack(
+ SBM_drm_dp_sideband_msg_rx * raw,
+ SBM_drm_dp_sideband_msg_reply_body *repmsg) {
+ bool ret;
+ uint32_t idx = 1;
+ repmsg->u.remote_i2c_read_ack.port_number = (raw->msg[idx] & 0xfU);
+ idx++;
+ if (idx > raw->curlen) {
+ DbgMsg(DBG_GEN_MSG, DBG_CRIT, "remote i2c reply parse length fail %d %d\n", idx,
+ raw->curlen);
+ ret = false;
+ } else {
+ repmsg->u.remote_i2c_read_ack.num_bytes = raw->msg[idx];
+ idx++;
+ (void)memcpy(repmsg->u.remote_i2c_read_ack.bytes, &raw->msg[idx],
+ repmsg->u.remote_i2c_read_ack.num_bytes);
+ ret = true;
+ }
+ return ret;
+}
+
+static bool drm_dp_sideband_parse_enum_path_resources_ack(
+ const SBM_drm_dp_sideband_msg_rx * raw,
+ SBM_drm_dp_sideband_msg_reply_body *repmsg) {
+
+ bool ret = true;
+ uint32_t idx = 1;
+ repmsg->u.path_resources.port_number = (raw->msg[idx] >> 4) & 0xfU;
+ idx++;
+ if (idx <= raw->curlen) {
+ repmsg->u.path_resources.full_payload_bw_number = ((uint16_t)raw->msg[idx] << 8)
+ | (raw->msg[idx + 1U]);
+ idx += 2U;
+ }
+ if (idx <= raw->curlen) {
+ repmsg->u.path_resources.avail_payload_bw_number = ((uint16_t)raw->msg[idx] << 8)
+ | (raw->msg[idx + 1U]);
+ idx += 2U;
+ }
+ if (idx > raw->curlen) {
+ ret = false;
+ DbgMsg(DBG_GEN_MSG, DBG_CRIT, "enum resource parse length fail %d %d\n", idx,
+ raw->curlen);
+ }
+ return ret;
+}
+
+static bool drm_dp_sideband_parse_allocate_payload_ack(
+ const SBM_drm_dp_sideband_msg_rx * raw,
+ SBM_drm_dp_sideband_msg_reply_body *repmsg) {
+
+ bool ret = true;
+ uint8_t idx = 1;
+ repmsg->u.allocate_payload.port_number = (raw->msg[idx] >> 4) & 0xfU;
+ idx++;
+ if (idx <= raw->curlen) {
+ repmsg->u.allocate_payload.vcpi = raw->msg[idx];
+ idx++;
+ }
+ if (idx <= raw->curlen) {
+ repmsg->u.allocate_payload.allocated_pbn = ((uint16_t)raw->msg[idx] << 8)
+ | ((uint16_t)raw->msg[idx + 1U]);
+ idx += 2U;
+ }
+ if (idx > raw->curlen) {
+ ret = false;
+ DbgMsg(DBG_GEN_MSG, DBG_CRIT, "allocate payload parse length fail %d %d\n", idx,
+ raw->curlen);
+ }
+ return ret;
+}
+
+static bool drm_dp_sb_parse_reply_prepare(SBM_drm_dp_sideband_msg_rx * raw,
+ SBM_drm_dp_sideband_msg_reply_body *msg) {
+ bool ret = true;
+
+ (void)memset(msg, 0, sizeof(*msg));
+
+ msg->reply_type = (raw->msg[0] & 0x80U) >> 7;
+ msg->req_type = (raw->msg[0] & 0x7fU);
+
+ if (msg->reply_type > 0U) {
+ (void)memcpy(msg->u.nak.guid, &raw->msg[1], 16);
+ msg->u.nak.reason = raw->msg[17];
+ msg->u.nak.nak_data = raw->msg[18];
+ ret = false;
+ }
+ return ret;
+}
+
+static bool drm_dp_sideband_parse_reply(SBM_drm_dp_sideband_msg_rx * raw,
+ SBM_drm_dp_sideband_msg_reply_body *msg) {
+ bool ret = true;
+
+ ret = drm_dp_sb_parse_reply_prepare(raw, msg);
+
+ if (ret) {
+ switch (msg->req_type) {
+ case DP_LINK_ADDRESS:
+ ret = drm_dp_sideband_parse_link_address(raw, msg);
+ break;
+ case DP_REMOTE_DPCD_READ:
+ ret = sideband_parse_remote_dpcd_read(raw, msg);
+ break;
+ case DP_REMOTE_DPCD_WRITE:
+ ret = sideband_parse_remote_dpcd_write(raw, msg);
+ break;
+ case DP_REMOTE_I2C_READ:
+ ret = drm_dp_sideband_parse_remote_i2c_read_ack(raw, msg);
+ break;
+ case DP_ENUM_PATH_RESOURCES:
+ ret = drm_dp_sideband_parse_enum_path_resources_ack(raw, msg);
+ break;
+ case DP_ALLOCATE_PAYLOAD:
+ ret = drm_dp_sideband_parse_allocate_payload_ack(raw, msg);
+ break;
+ default:
+ ret = false;
+ DbgMsg(DBG_GEN_MSG, DBG_CRIT, "Got unknown reply 0x%02x\n", msg->req_type);
+ break;
+ }
+ }
+ return ret;
+}
+
+static bool drm_dp_sideband_parse_connection_status_notify(
+ SBM_drm_dp_sideband_msg_rx * raw,
+ SBM_drm_dp_sideband_msg_req_body *msg) {
+
+ bool ret = false;
+ uint8_t idx = 1;
+
+ msg->u.conn_stat.port_number = (raw->msg[idx] & 0xf0U) >> 4;
+ idx++;
+ if (idx <= raw->curlen) {
+ (void)memcpy(msg->u.conn_stat.guid, &raw->msg[idx], 16);
+ idx += 16U;
+ }
+ if (idx <= raw->curlen) {
+ msg->u.conn_stat.legacy_device_plug_status = ((raw->msg[idx] >> 6) & 0x1U) != 0U;
+ msg->u.conn_stat.displayport_device_plug_status = ((raw->msg[idx] >> 5)
+ & 0x1U) != 0U;
+ msg->u.conn_stat.message_capability_status = ((raw->msg[idx] >> 4) & 0x1U) != 0U;
+ msg->u.conn_stat.input_port = ((raw->msg[idx] >> 3) & 0x1U) != 0U;
+ msg->u.conn_stat.peer_device_type = (raw->msg[idx] & 0x7U);
+ idx++;
+ ret = true;
+ }
+
+ if (!ret) {
+ DbgMsg(DBG_GEN_MSG, DBG_CRIT, "connection status reply parse length fail %d %d\n", idx,
+ raw->curlen);
+ }
+ return ret;
+}
+
+static bool drm_dp_sideband_parse_resource_status_notify(
+ SBM_drm_dp_sideband_msg_rx * raw,
+ SBM_drm_dp_sideband_msg_req_body *msg) {
+ bool ret = false;
+ uint8_t idx = 1;
+
+ msg->u.resource_stat.port_number = (raw->msg[idx] & 0xf0U) >> 4;
+ idx++;
+ if (idx <= raw->curlen) {
+ (void)memcpy(msg->u.resource_stat.guid, &raw->msg[idx], 16);
+ idx += 16U;
+ }
+ if (idx <= raw->curlen) {
+ msg->u.resource_stat.available_pbn = ((uint16_t)raw->msg[idx] << 8)
+ | (raw->msg[idx + 1U]);
+ idx++;
+ ret = true;
+ }
+
+ if (!ret) {
+ DbgMsg(DBG_GEN_MSG, DBG_CRIT, "resource status reply parse length fail %d %d\n", idx,
+ raw->curlen);
+ }
+ return ret;
+}
+
+static bool drm_dp_sideband_parse_req(SBM_drm_dp_sideband_msg_rx * raw,
+ SBM_drm_dp_sideband_msg_req_body *msg) {
+ bool ret;
+ (void)memset(msg, 0, sizeof(*msg));
+ msg->req_type = (raw->msg[0] & 0x7fU);
+
+ switch (msg->req_type) {
+ case DP_CONNECTION_STATUS_NOTIFY:
+ ret = drm_dp_sideband_parse_connection_status_notify(raw, msg);
+ break;
+ case DP_RESOURCE_STATUS_NOTIFY:
+ ret = drm_dp_sideband_parse_resource_status_notify(raw, msg);
+ break;
+ default:
+ ret = false;
+ DbgMsg(DBG_GEN_MSG, DBG_CRIT, "Got unknown request 0x%02x\n", msg->req_type);
+ break;
+ }
+
+ return ret;
+}
+
+static void build_dpcd_write(SBM_drm_dp_sideband_msg_tx *msg, uint8_t port_num,
+ uint32_t offset, uint8_t num_bytes, uint8_t *bytes) {
+ SBM_drm_dp_sideband_msg_req_body req;
+
+ req.req_type = DP_REMOTE_DPCD_WRITE;
+ req.u.dpcd_write.port_number = port_num;
+ req.u.dpcd_write.dpcd_address = offset;
+ req.u.dpcd_write.num_bytes = num_bytes;
+ req.u.dpcd_write.bytes = bytes;
+ drm_dp_encode_sideband_req(&req, msg);
+}
+
+static void build_link_address(SBM_drm_dp_sideband_msg_tx *msg) {
+ SBM_drm_dp_sideband_msg_req_body req;
+
+ req.req_type = DP_LINK_ADDRESS;
+ drm_dp_encode_sideband_req(&req, msg);
+}
+
+static void build_enum_path_resources(SBM_drm_dp_sideband_msg_tx *msg,
+ uint8_t port_num) {
+ SBM_drm_dp_sideband_msg_req_body req;
+
+ req.req_type = DP_ENUM_PATH_RESOURCES;
+ req.u.port_num.port_number = port_num;
+ drm_dp_encode_sideband_req(&req, msg);
+ msg->path_msg = true;
+}
+
+static void build_allocate_payload(SBM_drm_dp_sideband_msg_tx *msg,
+ uint8_t port_num, uint8_t vcpi, uint16_t pbn, uint8_t number_sdp_streams) {
+
+ uint8_t i;
+ uint8_t sinks[SBM_DRM_DP_MAX_SDP_STREAMS] = {0};
+ SBM_drm_dp_sideband_msg_req_body req;
+
+ (void)memset(&req, 0, sizeof(req));
+ req.req_type = DP_ALLOCATE_PAYLOAD;
+ req.u.allocate_payload.port_number = port_num;
+ req.u.allocate_payload.vcpi = vcpi;
+ req.u.allocate_payload.pbn = pbn;
+ req.u.allocate_payload.number_sdp_streams = number_sdp_streams;
+
+ for (i = 0U; i < number_sdp_streams; i++) {
+ sinks[i] = i;
+ }
+ (void)memcpy(req.u.allocate_payload.sdp_stream_sink, sinks,
+ number_sdp_streams);
+ drm_dp_encode_sideband_req(&req, msg);
+ msg->path_msg = true;
+}
+
+static bool check_txmsg_state(const SBM_drm_dp_sideband_msg_tx *txmsg) {
+ uint32_t state;
+
+ /*
+ * All updates to txmsg->state are protected by mgr->qlock, and the two
+ * cases we check here are terminal states. For those the barriers
+ * provided by the wake_up/wait_event pair are enough.
+ */
+ state = txmsg->state;
+ return ((state == DRM_DP_SIDEBAND_TX_RX)
+ || (state == DRM_DP_SIDEBAND_TX_TIMEOUT));
+}
+
+bool drm_dp_mst_handle_hpd(MST_drm_dp_topology_mgr *mgr) {
+ uint8_t esi[4];
+ uint32_t ret;
+ bool handled = false;
+
+ ret = drm_dp_dpcd_read(mgr->aux, DP_SINK_COUNT_ESI, esi, 4);
+ if (ret == CDN_EOK) {
+ (void)drm_dp_mst_hpd_irq(mgr, esi, &handled);
+ if (handled) {
+ uint8_t irq_handled = esi[1] & (uint8_t)((uint8_t)DP_DOWN_REP_MSG_RDY | (uint8_t)DP_UP_REQ_MSG_RDY);
+ (void)drm_dp_dpcd_write_byte(mgr->aux, DP_DEV_SERVICE_IRQ_VECTOR_ESI0, irq_handled);
+ }
+ }
+
+ return handled;
+}
+
+/*
+ * Wait for sideband Tx reply. Timeout is set to 4 seconds
+ * @param[in,out] mstBranch pointer to MST branch object
+ * @param[in] txMessage pointer to sideband message object
+ * @return CDN_EOK if response was received
+ * @return CDN_EIO if timeout
+ */
+static uint32_t drm_dp_mst_wait_tx_reply(MST_drm_dp_branch * mstBranch,
+ SBM_drm_dp_sideband_msg_tx *txMessage)
+
+{
+ uint32_t timeout = 4000U;
+ MST_drm_dp_topology_mgr *topologyManager = mstBranch->mgr;
+ uint32_t retVal = CDN_EOK;
+ bool isState = false;
+ uint32_t state;
+
+ /* wait for response or break if time expired */
+ while (timeout != 0U) {
+ CPS_DelayNs(1000000);
+ if (!topologyManager->int_enabled) {
+ (void)drm_dp_mst_handle_hpd(topologyManager);
+ }
+ isState = check_txmsg_state(txMessage);
+ if (isState) {
+ /* break if response was received */
+ break;
+ }
+ timeout--;
+ }
+
+ state = txMessage->state;
+
+ if (isState) {
+ if (state == DRM_DP_SIDEBAND_TX_TIMEOUT) {
+ retVal = CDN_EIO;
+ } else {
+ retVal = CDN_EPERM;
+ }
+ } else {
+
+ DbgMsg(DBG_GEN_MSG, DBG_CRIT, "ERROR: Message timeout. txMessage %p state %d seqno %d, mstBranch %p\n",
+ txMessage, txMessage->state, txMessage->seqno, mstBranch);
+
+ /* clean slot if Tx was during sending */
+ if ((state == DRM_DP_SIDEBAND_TX_START_SEND) || (state == DRM_DP_SIDEBAND_TX_SENT)) {
+ mstBranch->tx_slots[txMessage->seqno] = NULL;
+ }
+
+ retVal = CDN_EIO;
+ }
+ return retVal;
+}
+
+/*
+ * calculate a new RAD for this MST branch device
+ * if parent has an LCT of 2 then it has 1 nibble of RAD,
+ * if parent has an LCT of 3 then it has 2 nibbles of RAD,
+ */
+static uint8_t drm_dp_calculate_rad(MST_drm_dp_port *port, uint8_t *rad) {
+ uint8_t parent_lct = port->parent->lct;
+ uint8_t shift = 4U;
+ uint8_t idx = (parent_lct - 1U) / 2U;
+ if (parent_lct > 1U) {
+ uint8_t len = idx + 1U;
+ (void)memcpy(rad, port->parent->rad, len);
+ shift = ((parent_lct % 2U) != 0U) ? 4U : 0U;
+ } else {
+ rad[0] = 0;
+ }
+ /* parasoft-begin-suppress MISRA2012-RULE-12_2-2 "Shifting operation should be checked, DRV-3828" */
+ /* shift is always correct: 0U or 4U */
+ rad[idx] |= (port->port_num << shift);
+ /* parasoft-end-suppress MISRA2012-RULE-12_2-2 */
+
+ return parent_lct + 1U;
+}
+
+/*
+ * return sends link address for new mstb
+ */
+static bool drm_dp_port_setup_pdt(MST_drm_dp_port *port) {
+ uint8_t rad[6], lct;
+ bool send_link = false;
+ MST_drm_dp_topology_mgr* mgr = port->mgr;
+ switch (port->pdt) {
+ case DP_PEER_DEVICE_DP_LEGACY_CONV:
+ case DP_PEER_DEVICE_SST_SINK:
+ break;
+ case DP_PEER_DEVICE_MST_BRANCHING:
+ lct = drm_dp_calculate_rad(port, rad);
+
+ DbgMsg(DBG_GEN_MSG, DBG_FYI, "Add branch device on port %p lct %d rad %02d %02d %02d %02d %02d %02d\n",
+ port, lct, rad[0], rad[1], rad[2], rad[3], rad[4], rad[5]);
+ port->mstb = DRM_DP_addBranchDevice(mgr, lct, rad);
+ if (port->mstb != NULL) {
+ port->mstb->mgr = port->mgr;
+ port->mstb->port_parent = port;
+ send_link = true;
+ }
+ break;
+ default:
+ send_link = false;
+ break;
+ }
+ return send_link;
+}
+
+static int8_t drm_dp_get_free_port(const MST_drm_dp_branch *mstb,
+ uint8_t port_number) {
+ int8_t free_port_number = -1;
+
+ if (mstb->ports[port_number].refcount == 0U) {
+ free_port_number = (int8_t)port_number;
+ } else {
+ int8_t i;
+ for (i = 0; i < (int8_t)MST_BRANCH_MAX_PORTS; i++) {
+ if (mstb->ports[i].refcount == 0U) {
+ free_port_number = i;
+ }
+ }
+ }
+ return free_port_number;
+}
+
+/*
+ * Returns reference to first empty port.
+ * @param[in] mstb pointer to MST branch object
+ * @param[in] portNumber number of port
+ * @return pointer to port if success
+ * @return NULL if no empty port available
+ */
+static MST_drm_dp_port* createNewPort(MST_drm_dp_branch *mstb,
+ uint8_t portNumber)
+{
+ MST_drm_dp_port* port = NULL;
+ int8_t freePortNumber = drm_dp_get_free_port(mstb, portNumber);
+
+ if (freePortNumber >= 0) {
+ port = &(mstb->ports[freePortNumber]);
+ port->refcount = 1U;
+ port->parent = mstb;
+ port->port_num = portNumber;
+ port->mgr = mstb->mgr;
+ }
+
+ return port;
+}
+
+/*
+ * Function fill port parameters
+ * @param[in] pointer to MST port object to be filled
+ * @param[in] portMsg
+ */
+static void fillPortParams(MST_drm_dp_port* port,
+ const SBM_drm_dp_link_addr_reply_port *portMsg)
+{
+ port->pdt = portMsg->peer_device_type;
+ port->input = portMsg->input_port;
+ port->mcs = portMsg->mcs;
+ port->ddps = portMsg->ddps;
+ port->ldps = portMsg->legacy_device_plug_status;
+ port->dpcd_rev = portMsg->dpcd_revision;
+ port->num_sdp_streams = portMsg->num_sdp_streams;
+ port->num_sdp_stream_sinks = portMsg->num_sdp_stream_sinks;
+}
+
+/*
+ * Clean available payload bandwidth if DisplayPort Device Plug Status was changed to 'false'
+ * or get it from path resources if DisplayPort Device Plug Status was changed to 'true' and
+ * port is output
+ * @param[in] port pointer to MST port object
+ * @param[in] mstBranch pointer to MST branch object
+ * @param[in] oldDdps old state of DP Device Plug Status
+ */
+static void reloadAvailablePayloadBandwidth(MST_drm_dp_port* port,
+ MST_drm_dp_branch* mstBranch,
+ bool oldDpps)
+{
+ /* test if DP Device Plug Status was changed */
+ if (oldDpps != port->ddps) {
+ /* check if device is plug-in */
+ if (port->ddps) {
+ /* check if port is output */
+ if (!port->input) {
+ drm_dp_send_enum_path_resources(mstBranch->mgr, mstBranch, port);
+ }
+ } else {
+ port->available_pbn = 0;
+ }
+ }
+}
+
+/*
+ * Teardown port and set new peer-device-type
+ * @param[in] port pointer to MST port object
+ * @param[in] oldPdt old value of peer-device-type
+ * @return true if link-address should be sent
+ * @return false if not
+ */
+static bool reloadPeerDeviceType(MST_drm_dp_port* port,
+ uint8_t oldPdt)
+{
+ bool retVal = false;
+
+ if ((oldPdt != port->pdt) && (!port->input)) {
+ DRM_DP_teardownPort(port, oldPdt);
+ retVal = drm_dp_port_setup_pdt(port);
+ }
+
+ return retVal;
+}
+
+static void drm_dp_add_port(MST_drm_dp_branch * mstb,
+ SBM_drm_dp_link_addr_reply_port *port_msg)
+{
+
+ bool created = false;
+ uint8_t old_pdt = 0U;
+ bool old_ddps = false;
+ MST_drm_dp_port *port = DRM_DP_getPort(mstb, port_msg->port_number);
+
+ /* check if port exists */
+ if (port == NULL) {
+
+ port = createNewPort(mstb, port_msg->port_number);
+
+ if (port != NULL) {
+ created = true;
+ }
+
+ } else {
+ /* save old parameters of port */
+ old_pdt = port->pdt;
+ old_ddps = port->ddps;
+ }
+
+ /* do if port exists or was created correctly */
+ if (port != NULL) {
+ fillPortParams(port, port_msg);
+
+ if (created) {
+ port->refcount++;
+ }
+
+ reloadAvailablePayloadBandwidth(port, mstb, old_ddps);
+
+ (void)reloadPeerDeviceType(port, old_pdt);
+
+ /* put reference to this port */
+ DRM_DP_putPort(port);
+ }
+}
+
+static void drm_dp_update_port(MST_drm_dp_branch * mstb,
+ SBM_drm_dp_connection_status_notify *conn_stat) {
+
+ MST_drm_dp_port *port;
+ uint8_t old_pdt;
+ bool old_ddps;
+ bool dowork = false;
+ bool linkAddress;
+ port = DRM_DP_getPort(mstb, conn_stat->port_number);
+
+ if (port != NULL) {
+ old_ddps = port->ddps;
+ old_pdt = port->pdt;
+ port->pdt = conn_stat->peer_device_type;
+ port->mcs = conn_stat->message_capability_status;
+ port->ldps = conn_stat->legacy_device_plug_status;
+ port->ddps = conn_stat->displayport_device_plug_status;
+
+ if (old_ddps != port->ddps) {
+ if (port->ddps) {
+ dowork = true;
+ } else {
+ port->available_pbn = 0;
+ }
+ }
+
+ linkAddress = reloadPeerDeviceType(port, old_pdt);
+ if (linkAddress) {
+ dowork = true;
+ }
+
+ DRM_DP_putPort(port);
+ if (dowork) {
+ (void)drm_dp_mst_link_probe_work(mstb->mgr);
+ }
+ }
+}
+
+static MST_drm_dp_branch * drm_dp_configure_port(MST_drm_dp_branch *mstb, MST_drm_dp_port *port) {
+
+ MST_drm_dp_branch *mstb_child = NULL;
+
+ if (port->refcount > 0U) {
+ if ((!port->input) && port->ddps) {
+ if (port->available_pbn <= 0) {
+ drm_dp_send_enum_path_resources(mstb->mgr, mstb, port);
+ }
+
+ if (port->mstb != NULL) {
+ mstb_child = DRM_DP_getValidatedBranchRef(mstb->mgr, port->mstb);
+ }
+ }
+ }
+ return mstb_child;
+}
+
+static int8_t drm_dp_mst_build_next(const MST_drm_dp_branch *mstb_array[]) {
+ int8_t i;
+ int8_t ret = -1;
+ for (i = 0; (uint8_t)i < MST_BRANCH_MAX_PORTS; ++i) {
+ if (mstb_array[i] != NULL) {
+ ret = i;
+ break;
+ }
+ }
+ return ret;
+}
+
+uint32_t drm_dp_mst_link_probe_work(MST_drm_dp_topology_mgr *mgr)
+{
+ uint32_t i;
+ uint32_t ret = CDN_EOK;
+ MST_drm_dp_branch *mstb_array[MST_BRANCH_MAX_PORTS] = {NULL};
+ mstb_array[0] = mgr->mst_primary;
+
+ while (drm_dp_mst_build_next((const MST_drm_dp_branch**)mstb_array) >= 0) {
+ int8_t current_index = drm_dp_mst_build_next((const MST_drm_dp_branch**)mstb_array);
+ MST_drm_dp_branch *mstb = mstb_array[current_index];
+ if (!mstb->link_address_sent) {
+ drm_dp_send_link_address(mgr, mstb);
+ mstb_array[current_index] = NULL;
+ }
+ for (i = 0; i < MST_BRANCH_MAX_PORTS; i++) {
+ MST_drm_dp_branch *mstb_child = NULL;
+ mstb_child = drm_dp_configure_port(mstb, &mstb->ports[i]);
+ if (mstb_child != NULL) {
+ current_index++;
+ mstb_array[current_index] = mstb_child;
+ }
+ }
+ }
+
+ return ret;
+}
+
+static void process_single_down_tx_qlock(MST_drm_dp_topology_mgr *mgr) {
+
+ if (mgr->tx_msg_downq != NULL) {
+ SBM_drm_dp_sideband_msg_tx *txmsg;
+ uint32_t ret;
+
+ txmsg = mgr->tx_msg_downq;
+ ret = process_single_tx_qlock(mgr, txmsg, false);
+ if (ret == 1U) {
+ /* txmsg is sent it should be in the slots now */
+ mgr->tx_msg_downq = NULL;
+ } else if (ret > 0U) {
+ DbgMsg(DBG_GEN_MSG, DBG_CRIT, "failed to send msg in q %d\n", ret);
+ mgr->tx_msg_downq = NULL;
+ if (txmsg->seqno != -1) {
+ txmsg->dst->tx_slots[txmsg->seqno] = NULL;
+ }
+ txmsg->state = DRM_DP_SIDEBAND_TX_TIMEOUT;
+ } else {
+ /* TODO: add else action */
+ }
+ }
+}
+
+/* called holding qlock */
+static void process_single_up_tx_qlock(MST_drm_dp_topology_mgr * mgr,
+ SBM_drm_dp_sideband_msg_tx *txmsg) {
+ uint32_t ret;
+
+ /* construct a chunk from the first msg in the tx_msg queue */
+ ret = process_single_tx_qlock(mgr, txmsg, true);
+
+ if (ret != 1U) {
+ DbgMsg(DBG_GEN_MSG, DBG_CRIT, "failed to send msg in q %d\n", ret);
+ }
+
+ txmsg->dst->tx_slots[txmsg->seqno] = NULL;
+}
+
+static void drm_dp_queue_down_tx(MST_drm_dp_topology_mgr * mgr,
+ SBM_drm_dp_sideband_msg_tx *txmsg) {
+
+ if (mgr->tx_msg_downq != NULL) {
+ DbgMsg(DBG_GEN_MSG, DBG_CRIT, "Not enough space to add sideband message\n");
+ } else {
+ mgr->tx_msg_downq = txmsg;
+ process_single_down_tx_qlock(mgr);
+ }
+}
+
+/*
+ * Send link address to branch device
+ * param[in] mgr pointer to MST topology manager object
+ * param[in] mstb pointer to MST branch device
+ */
+static void drm_dp_send_link_address(MST_drm_dp_topology_mgr *topologyManager,
+ MST_drm_dp_branch * mstb)
+{
+ SBM_drm_dp_link_address_ack_reply* linkAddress;
+ SBM_drm_dp_sideband_msg_tx txmsg;
+ SBM_drm_dp_link_addr_reply_port* port;
+ uint32_t ret;
+
+ /* send link address to branch device */
+ (void)memset(&txmsg, 0, sizeof(txmsg));
+ txmsg.dst = mstb;
+ build_link_address(&txmsg);
+ mstb->link_address_sent = true;
+ drm_dp_queue_down_tx(topologyManager, &txmsg);
+
+ ret = drm_dp_mst_wait_tx_reply(mstb, &txmsg);
+
+ if (ret != CDN_EOK) {
+ uint32_t i;
+
+ /* check reply for message */
+ if (txmsg.reply.reply_type == 1U) {
+ DbgMsg(DBG_GEN_MSG, DBG_FYI, "INFO: Link address nak received\n");
+ }
+ else {
+
+ linkAddress = &(txmsg.reply.u.link_addr);
+ DbgMsg(DBG_GEN_MSG, DBG_FYI, "INFO :Link address reply: %d\n", linkAddress->nports);
+
+ /* print configuration of ports from link address */
+ for (i = 0U; i < linkAddress->nports; i++) {
+ port = &(linkAddress->ports[i]);
+ DbgMsg(DBG_GEN_MSG, DBG_FYI,
+ "port %d: input %d, pdt: %d, pn: %d, dpcd_rev: %02x, mcs: %d, ddps: %d, ldps %d, sdp %d/%d\n",
+ i,
+ port->input_port,
+ port->peer_device_type,
+ port->port_number,
+ port->dpcd_revision,
+ port->mcs,
+ port->ddps,
+ port->legacy_device_plug_status,
+ port->num_sdp_streams,
+ port->num_sdp_stream_sinks);
+ }
+
+ drm_dp_check_mstb_guid(mstb, linkAddress->guid);
+
+ for (i = 0U; i < linkAddress->nports; i++) {
+ port = &(linkAddress->ports[i]);
+ drm_dp_add_port(mstb, port);
+ }
+ }
+ } else {
+ mstb->link_address_sent = false;
+ DbgMsg(DBG_GEN_MSG, DBG_CRIT, "ERROR: Link address failed %d\n", ret);
+ }
+}
+
+static void drm_dp_send_enum_path_resources(MST_drm_dp_topology_mgr *mgr,
+ MST_drm_dp_branch *mstb, MST_drm_dp_port *port) {
+
+ SBM_drm_dp_sideband_msg_tx txmsg;
+ uint32_t ret;
+
+ (void)memset(&txmsg, 0, sizeof(txmsg));
+ txmsg.dst = mstb;
+ build_enum_path_resources(&txmsg, port->port_num);
+
+ drm_dp_queue_down_tx(mgr, &txmsg);
+
+ ret = drm_dp_mst_wait_tx_reply(mstb, &txmsg);
+ if (ret > 0U) {
+ if (txmsg.reply.reply_type == 1U) {
+ DbgMsg(DBG_GEN_MSG, DBG_CRIT, "enum path resources nak received\n");
+ }
+ else {
+ if (port->port_num != txmsg.reply.u.path_resources.port_number) {
+ DbgMsg(DBG_GEN_MSG, DBG_CRIT, "got incorrect port in response\n");
+ }
+ DbgMsg(DBG_GEN_MSG, DBG_CRIT, "enum path resources %d: %d %d\n",
+ txmsg.reply.u.path_resources.port_number,
+ txmsg.reply.u.path_resources.full_payload_bw_number,
+ txmsg.reply.u.path_resources.avail_payload_bw_number);
+ port->available_pbn = (int16_t)
+ txmsg.reply.u.path_resources.avail_payload_bw_number;
+ }
+ }
+}
+
+static MST_drm_dp_port *get_last_connected_port_to_mstb(MST_drm_dp_branch *mstb) {
+
+ MST_drm_dp_branch *current_mstb = mstb;
+ MST_drm_dp_port *port = current_mstb->port_parent;
+
+ while (current_mstb->port_parent != NULL) {
+ if (current_mstb->port_parent->mstb != current_mstb) {
+ port = current_mstb->port_parent;
+ break;
+ } else {
+ current_mstb = current_mstb->port_parent->parent;
+ }
+ }
+ return port;
+}
+
+static MST_drm_dp_branch *get_last_connected_port_and_mstb(
+ const MST_drm_dp_topology_mgr *mgr, MST_drm_dp_branch *mstb,
+ uint8_t *port_num) {
+ MST_drm_dp_branch *rmstb = NULL;
+ MST_drm_dp_port *found_port;
+
+ if (mgr->mst_primary != NULL) {
+ found_port = get_last_connected_port_to_mstb(mstb);
+
+ if (found_port != NULL) {
+ rmstb = found_port->parent;
+ rmstb->refcount++;
+ *port_num = found_port->port_num;
+ }
+ }
+ return rmstb;
+}
+
+/*
+ * Secondary structure for sending payload messages
+ */
+typedef struct {
+ uint8_t id;
+ uint16_t payloadBandwidth;
+ uint8_t sdpNumber;
+ uint8_t portNumber;
+} DP_PayloadMsg;
+
+/*
+ * Send payload message to topology manager
+ * @param[in] topologyManager pointer to MST topology manager object
+ * @param[in] branch pointer to MST branch object
+ * @param[in] message pointer to DP_PayloadMsg object
+ * @return CDN_EOK if success
+ * @return CDN_EINVAL if reply type is '1'
+ */
+static uint32_t sendPayloadMsg(MST_drm_dp_topology_mgr *topologyManager,
+ MST_drm_dp_branch * branch,
+ const DP_PayloadMsg* message)
+{
+ SBM_drm_dp_sideband_msg_tx txmsg;
+ uint32_t retVal;
+
+ (void)memset(&txmsg, 0, sizeof(txmsg));
+
+ txmsg.dst = branch;
+
+ /* allocate payload */
+ build_allocate_payload(&txmsg,
+ message->portNumber,
+ message->id,
+ message->payloadBandwidth,
+ message->sdpNumber);
+
+ /* put message into Tx queue */
+ drm_dp_queue_down_tx(topologyManager, &txmsg);
+
+ /* wait for reply */
+ retVal = drm_dp_mst_wait_tx_reply(branch, &txmsg);
+
+ if (retVal != CDN_EOK) {
+
+ if (txmsg.reply.reply_type == 1U) {
+ retVal = CDN_EINVAL;
+ } else {
+ retVal = CDN_EOK;
+ }
+ }
+
+ return retVal;
+}
+
+/*
+ * Look for correct branch and send payload message
+ * @param[in] topologyManager pointer to MST topologyManager object
+ * @param[in] port pointer to MST port object
+ * @param[in] id identifier of message
+ * @param[in] pbn value of payload bandwidth
+ * @return CDN_EOK if success
+ * @return CDN_EINVAL if cannot find branch or reply is incorrect
+ */
+uint32_t drm_dp_payload_send_msg(MST_drm_dp_topology_mgr *mgr,
+ MST_drm_dp_port * port,
+ int32_t id,
+ int32_t pbn)
+{
+ DP_PayloadMsg message;
+ MST_drm_dp_branch *mstb;
+ uint32_t retVal = CDN_EOK;
+ uint8_t port_num;
+ MST_drm_dp_port *dst_port;
+
+ /* get reference to port */
+ dst_port = DRM_DP_getValidatedPortRef(mgr, port);
+
+ if (dst_port == NULL) {
+ retVal = CDN_EINVAL;
+ } else {
+ /* find branch connected with port */
+ port_num = dst_port->port_num;
+ mstb = DRM_DP_getValidatedBranchRef(mgr, dst_port->parent);
+
+ if (mstb == NULL) {
+ mstb = get_last_connected_port_and_mstb(mgr, dst_port->parent, &port_num);
+ }
+
+ if (mstb == NULL) {
+ DRM_DP_putPort(dst_port);
+ retVal = CDN_EINVAL;
+ }
+ }
+
+ if (retVal == CDN_EOK) {
+
+ /* fill payload message */
+ message.id = (uint8_t)id;
+ message.payloadBandwidth = (uint16_t)pbn;
+ message.portNumber = port_num;
+ message.sdpNumber = dst_port->num_sdp_streams;
+
+ retVal = sendPayloadMsg(mgr, mstb, &message);
+
+ /* put device */
+ DRM_DP_putBranchDevice(mstb);
+ DRM_DP_putPort(dst_port);
+ }
+
+ return retVal;
+}
+
+static uint32_t drm_dp_send_dpcd_write(MST_drm_dp_topology_mgr *mgr,
+ MST_drm_dp_port *port, uint32_t offset, uint8_t size, uint8_t *bytes) {
+
+ uint32_t ret = CDN_EINVAL;
+ SBM_drm_dp_sideband_msg_tx txmsg;
+ MST_drm_dp_branch *mstb;
+
+ (void)memset(&txmsg, 0, sizeof(txmsg));
+ mstb = DRM_DP_getValidatedBranchRef(mgr, port->parent);
+ if (mstb != NULL) {
+ build_dpcd_write(&txmsg, port->port_num, offset, size, bytes);
+ txmsg.dst = mstb;
+
+ drm_dp_queue_down_tx(mgr, &txmsg);
+
+ ret = drm_dp_mst_wait_tx_reply(mstb, &txmsg);
+ if (ret > 0U) {
+ if (txmsg.reply.reply_type == 1U) {
+ ret = CDN_EINVAL;
+ } else {
+ ret = CDN_EOK;
+ }
+ }
+ DRM_DP_putBranchDevice(mstb);
+ }
+ return ret;
+}
+
+/**************** RX **********************************************************/
+
+static void drm_dp_encode_up_ack_reply(SBM_drm_dp_sideband_msg_tx *msg,
+ uint8_t req_type) {
+ SBM_drm_dp_sideband_msg_reply_body reply;
+
+ reply.reply_type = 0;
+ reply.req_type = req_type;
+ drm_dp_encode_sideband_reply(&reply, msg);
+}
+
+static void drm_dp_send_up_ack_reply(MST_drm_dp_topology_mgr *mgr,
+ MST_drm_dp_branch *mstb, uint8_t req_type, int32_t seqno) {
+ SBM_drm_dp_sideband_msg_tx txmsg;
+
+ (void)memset(&txmsg, 0, sizeof(txmsg));
+ txmsg.dst = mstb;
+ txmsg.seqno = seqno;
+ drm_dp_encode_up_ack_reply(&txmsg, req_type);
+ process_single_up_tx_qlock(mgr, &txmsg);
+}
+
+void drm_dp_mst_handle_down_rep(MST_drm_dp_topology_mgr *mgr) {
+ SBM_drm_dp_sideband_msg_tx *txmsg;
+ MST_drm_dp_branch *mstb;
+ bool ret = drm_dp_get_one_sb_msg(mgr, false);
+ if (ret && mgr->down_rep_recv.have_eomt) {
+ SBM_drm_dp_sideband_msg_hdr *initial_hdr = &mgr->down_rep_recv.initial_hdr;
+ mstb = DRM_DP_getBranchDevice(mgr, initial_hdr->lct, initial_hdr->rad);
+ if (mstb == NULL) {
+ DbgMsg(DBG_GEN_MSG, DBG_CRIT, "Got MST reply from unknown device %d\n",
+ initial_hdr->lct);
+ } else {
+ /* find the message */
+ int32_t slot = initial_hdr->seqno ? 1 : 0;
+ txmsg = mstb->tx_slots[slot];
+ /* remove from slots */
+ if (txmsg == NULL) {
+ DbgMsg(DBG_GEN_MSG, DBG_CRIT, "Got MST reply with no msg %p segno %d lct %d rad[0] %02x msg[0] %02x\n",
+ mstb,
+ initial_hdr->seqno,
+ initial_hdr->lct,
+ initial_hdr->rad[0],
+ mgr->down_rep_recv.msg[0]);
+ DRM_DP_putBranchDevice(mstb);
+ } else {
+ (void)drm_dp_sideband_parse_reply(&mgr->down_rep_recv, &txmsg->reply);
+ if (txmsg->reply.reply_type == 1U) {
+ DbgMsg(DBG_GEN_MSG, DBG_CRIT,
+ "Got NAK reply: req 0x%02x, reason 0x%02x, nak data 0x%02x\n",
+ txmsg->reply.req_type, txmsg->reply.u.nak.reason,
+ txmsg->reply.u.nak.nak_data);
+ }
+ DRM_DP_putBranchDevice(mstb);
+ txmsg->state = DRM_DP_SIDEBAND_TX_RX;
+ mstb->tx_slots[slot] = NULL;
+ }
+ }
+ (void)memset(&mgr->down_rep_recv, 0, sizeof(SBM_drm_dp_sideband_msg_rx));
+ }
+}
+
+static void handle_connection_status_notify(MST_drm_dp_topology_mgr * mgr,
+ MST_drm_dp_branch * mstb,
+ SBM_drm_dp_sideband_msg_req_body *msg) {
+
+ int32_t seqno = mgr->up_req_recv.initial_hdr.seqno ? 1 : 0;
+ MST_drm_dp_branch *current_mstb = mstb;
+ drm_dp_send_up_ack_reply(mgr, mgr->mst_primary, msg->req_type, seqno);
+
+ if (current_mstb == NULL) {
+ current_mstb = DRM_DP_getBranchDeviceByGuid(mgr, msg->u.conn_stat.guid);
+ }
+ if (current_mstb == NULL) {
+ DbgMsg(DBG_GEN_MSG, DBG_CRIT, "Got MST reply from unknown device %d\n",
+ mgr->up_req_recv.initial_hdr.lct);
+ (void)memset(&mgr->up_req_recv, 0,
+ sizeof(SBM_drm_dp_sideband_msg_rx));
+ } else {
+ drm_dp_update_port(current_mstb, &msg->u.conn_stat);
+ DbgMsg(DBG_GEN_MSG, DBG_CRIT, "Got CSN: pn: %d ldps:%d ddps: %d mcs: %d ip: %d pdt: %d\n",
+ msg->u.conn_stat.port_number,
+ msg->u.conn_stat.legacy_device_plug_status,
+ msg->u.conn_stat.displayport_device_plug_status,
+ msg->u.conn_stat.message_capability_status,
+ msg->u.conn_stat.input_port,
+ msg->u.conn_stat.peer_device_type);
+ }
+}
+
+static void handle_resource_status_notify(MST_drm_dp_topology_mgr * mgr,
+ MST_drm_dp_branch * mstb,
+ SBM_drm_dp_sideband_msg_req_body *msg) {
+
+ int32_t seqno = mgr->up_req_recv.initial_hdr.seqno ? 1 : 0;
+ MST_drm_dp_branch *current_mstb = mstb;
+
+ drm_dp_send_up_ack_reply(mgr, mgr->mst_primary, msg->req_type, seqno);
+ if (current_mstb == NULL) {
+ current_mstb = DRM_DP_getBranchDeviceByGuid(mgr, msg->u.resource_stat.guid);
+ }
+ if (current_mstb == NULL) {
+ DbgMsg(DBG_GEN_MSG, DBG_CRIT, "Got MST reply from unknown device %d\n",
+ mgr->up_req_recv.initial_hdr.lct);
+ (void)memset(&mgr->up_req_recv, 0,
+ sizeof(SBM_drm_dp_sideband_msg_rx));
+ } else {
+ DbgMsg(DBG_GEN_MSG, DBG_CRIT, "Got RSN: pn: %d avail_pbn %d\n",
+ msg->u.resource_stat.port_number,
+ msg->u.resource_stat.available_pbn);
+ }
+}
+
+void drm_dp_mst_handle_up_req(MST_drm_dp_topology_mgr *mgr) {
+ bool cont = true;
+
+ if (!drm_dp_get_one_sb_msg(mgr, true)) {
+ (void)memset(&mgr->up_req_recv, 0, sizeof(SBM_drm_dp_sideband_msg_rx));
+ cont = false;
+ }
+
+ if (cont && mgr->up_req_recv.have_eomt) {
+ SBM_drm_dp_sideband_msg_req_body msg;
+ MST_drm_dp_branch *mstb = NULL;
+ SBM_drm_dp_sideband_msg_rx *up_req_recv = &mgr->up_req_recv;
+
+ if (!up_req_recv->initial_hdr.broadcast) {
+ SBM_drm_dp_sideband_msg_hdr *initial_hdr = &up_req_recv->initial_hdr;
+ mstb = DRM_DP_getBranchDevice(mgr, initial_hdr->lct, initial_hdr->rad);
+ if (mstb == NULL) {
+ DbgMsg(DBG_GEN_MSG, DBG_CRIT, "Got MST reply from unknown device %d\n",
+ initial_hdr->lct);
+ (void)memset(up_req_recv, 0, sizeof(SBM_drm_dp_sideband_msg_rx));
+ cont = false;
+ }
+ }
+ if (cont) {
+ (void)drm_dp_sideband_parse_req(up_req_recv, &msg);
+
+ if (msg.req_type == DP_CONNECTION_STATUS_NOTIFY) {
+ handle_connection_status_notify(mgr, mstb, &msg);
+ } else if (msg.req_type == DP_RESOURCE_STATUS_NOTIFY) {
+ handle_resource_status_notify(mgr, mstb, &msg);
+ } else {
+ DbgMsg(DBG_GEN_MSG, DBG_CRIT, "Other req type: %d\n", msg.req_type);
+ }
+
+ DRM_DP_putBranchDevice(mstb);
+ (void)memset(up_req_recv, 0, sizeof(SBM_drm_dp_sideband_msg_rx));
+ }
+ }
+}
+
+uint32_t drm_dp_mst_i2c_xfer(MST_drm_dp_port *port,
+ struct mst_i2c_message *msgs, uint32_t num)
+{
+ MST_drm_dp_branch *mstb;
+ MST_drm_dp_topology_mgr *mgr = port->mgr;
+ SBM_drm_dp_sideband_msg_req_body msg;
+ SBM_drm_dp_sideband_msg_tx txmsg;
+ uint32_t ret = CDN_EOK;
+ uint32_t i;
+
+ mstb = DRM_DP_getValidatedBranchRef(mgr, port->parent);
+ if (mstb == NULL) {
+ ret = CDN_EIO;
+ } else if ((num - 1U) > SBM_DP_REMOTE_I2C_READ_MAX_TRANSACTIONS) {
+ DbgMsg(DBG_GEN_MSG, DBG_CRIT, "Unsupported I2C transaction for MST device\n");
+ ret = CDN_EIO;
+ } else {
+ SBM_drm_dp_remote_i2c_read *msg_i2c_read = &msg.u.i2c_read;
+ (void)memset(&msg, 0, sizeof(msg));
+ msg.req_type = DP_REMOTE_I2C_READ;
+ msg_i2c_read->num_transactions = (uint8_t)num - 1U;
+ msg_i2c_read->port_number = port->port_num;
+ for (i = 0; i < (num - 1U); i++) {
+ msg_i2c_read->transactions[i].i2c_dev_id = msgs[i].address;
+ msg_i2c_read->transactions[i].num_bytes = msgs[i].length;
+ msg_i2c_read->transactions[i].bytes = msgs[i].data;
+ }
+ msg_i2c_read->read_i2c_device_id = msgs[num - 1U].address;
+ msg_i2c_read->num_bytes_read = msgs[num - 1U].length;
+
+ (void)memset(&txmsg, 0, sizeof(txmsg));
+ txmsg.dst = mstb;
+ drm_dp_encode_sideband_req(&msg, &txmsg);
+ drm_dp_queue_down_tx(mgr, &txmsg);
+ ret = drm_dp_mst_wait_tx_reply(mstb, &txmsg);
+ if (ret > 0U) {
+ SBM_drm_dp_remote_i2c_read_ack_reply *remote_i2c_reply = \
+ &txmsg.reply.u.remote_i2c_read_ack;
+ if ((txmsg.reply.reply_type == 1U) \
+ || (remote_i2c_reply->num_bytes != msgs[num - 1U].length)) {
+ ret = CDN_EIO;
+ } else {
+ (void)memcpy(msgs[num - 1U].data, remote_i2c_reply->bytes, msgs[num - 1U].length);
+ ret = num;
+ }
+ }
+ }
+ DRM_DP_putBranchDevice(mstb);
+ return ret;
+}
+/* parasoft-end-suppress MISRA2012-RULE-1_1_a_c90-2 "C90 - limits" */
+/* parasoft-end-suppress METRICS-41-3 */
+/* parasoft-end-suppress METRICS-36-3 */
diff --git a/packages/ti/drv/dss/src/csl/dp/src/dp_transaction.h b/packages/ti/drv/dss/src/csl/dp/src/dp_transaction.h
--- /dev/null
@@ -0,0 +1,87 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ *
+ * dp_transaction.h
+ *
+ ******************************************************************************
+ */
+
+/*
+ * Copyright (C) 2014 Red Hat
+ *
+ * Permission to use, copy, modify, distribute, and sell this software and its
+ * documentation for any purpose is hereby granted without fee, provided that
+ * the above copyright notice appear in all copies and that both that copyright
+ * notice and this permission notice appear in supporting documentation, and
+ * that the name of the copyright holders not be used in advertising or
+ * publicity pertaining to distribution of the software without specific,
+ * written prior permission. The copyright holders make no representations
+ * about the suitability of this software for any purpose. It is provided "as
+ * is" without express or implied warranty.
+ *
+ * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
+ * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
+ * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
+ * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
+ * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
+ * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
+ * OF THIS SOFTWARE.
+ */
+
+#ifndef DP_TRANSACTION_H_
+#define DP_TRANSACTION_H_
+
+#include "dp_topology_mgr.h"
+#include "dp_mst_if.h"
+
+/* parasoft-begin-suppress MISRA2012-DIR-4_8-4 "Consider hiding of implementation, DRV-3820" */
+/**
+ * Structure used for I2C over AUX communication
+ */
+struct mst_i2c_message {
+ uint8_t address;
+ uint8_t *data;
+ uint8_t length;
+};
+/* parasoft-end-suppress MISRA2012-DIR-4_8-4 */
+
+uint32_t drm_dp_payload_send_msg(MST_drm_dp_topology_mgr *mgr,
+ MST_drm_dp_port * port,
+ int32_t id,
+ int32_t pbn);
+
+uint32_t drm_dp_mst_i2c_xfer(MST_drm_dp_port *port, struct mst_i2c_message *msgs,
+ uint32_t num);
+
+void drm_dp_mst_handle_down_rep(MST_drm_dp_topology_mgr *mgr);
+void drm_dp_mst_handle_up_req(MST_drm_dp_topology_mgr *mgr);
+uint32_t drm_dp_mst_link_probe_work(MST_drm_dp_topology_mgr *mgr);
+
+#endif /* DP_TRANSACTION_H_ */
diff --git a/packages/ti/drv/dss/src/csl/dp/src/dp_utils.c b/packages/ti/drv/dss/src/csl/dp/src/dp_utils.c
--- /dev/null
@@ -0,0 +1,55 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ *
+ * dp_utils.c
+ *
+ ******************************************************************************
+ */
+#include "dp_utils.h"
+#include "cdn_stdtypes.h"
+
+/*
+ * Select properly register base according to bus type
+ */
+MHDP_ApbRegs* selectRegBase(const DP_PrivateData* pD, DP_BusType busType)
+{
+ MHDP_ApbRegs* result;
+
+ if (DP_BUS_TYPE_SAPB == busType)
+ {
+ /* return secure APB */
+ result = pD->regBaseSapb;
+ } else {
+ /* return APB */
+ result = pD->regBase;
+ }
+
+ return result;
+}
diff --git a/packages/ti/drv/dss/src/csl/dp/src/dp_utils.h b/packages/ti/drv/dss/src/csl/dp/src/dp_utils.h
--- /dev/null
@@ -0,0 +1,49 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ *
+ * dp_utils.h
+ *
+ ******************************************************************************
+ */
+
+#ifndef DP_UTILS_H_
+#define DP_UTILS_H_
+
+#include "cdn_stdtypes.h"
+#include "dp_if.h"
+#include "dp_priv.h"
+#include "mhdp_apb_regs.h"
+
+/* parasoft-begin-suppress METRICS-36-3 "Function called from more than 5 functions, DRV-3823" */
+MHDP_ApbRegs* selectRegBase(const DP_PrivateData* pD, DP_BusType busType);
+/* parasoft-end-suppress METRICS-36-3 */
+
+#endif /* DP_UTILS_H_ */
+
diff --git a/packages/ti/drv/dss/src/csl/dp/src/dsc_utils.c b/packages/ti/drv/dss/src/csl/dp/src/dsc_utils.c
--- /dev/null
@@ -0,0 +1,985 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ *
+ * dsc_utils.c
+ *
+ ******************************************************************************
+ */
+/***************************************************************************
+* Copyright (c) 2013-2016, Broadcom Ltd.
+* All rights reserved.
+*
+* Statement regarding contribution of copyrighted materials to VESA:
+*
+* This code is owned by Broadcom Limited and is contributed to VESA
+* for inclusion and use in its VESA Display Stream Compression specification.
+* Accordingly, VESA is hereby granted a worldwide, perpetual, non-exclusive
+* license to revise, modify and create derivative works to this code and
+* VESA shall own all right, title and interest in and to any derivative
+* works authored by VESA.
+*
+* Terms and Conditions
+*
+* Without limiting the foregoing, you agree that your use
+* of this software program does not convey any rights to you in any of
+* Broadcom's patent and other intellectual property, and you
+* acknowledge that your use of this software may require that
+* you separately obtain patent or other intellectual property
+* rights from Broadcom or third parties.
+*
+* Except as expressly set forth in a separate written license agreement
+* between you and Broadcom, if applicable:
+*
+* 1. TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED
+* "AS IS" AND WITH ALL FAULTS AND BROADCOM MAKES NO PROMISES,
+* REPRESENTATIONS OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR
+* OTHERWISE, WITH RESPECT TO THE SOFTWARE. BROADCOM SPECIFICALLY
+* DISCLAIMS ANY AND ALL IMPLIED WARRANTIES OF TITLE, MERCHANTABILITY,
+* NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF VIRUSES,
+* ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+* CORRESPONDENCE TO DESCRIPTION. YOU ASSUME THE ENTIRE RISK ARISING
+* OUT OF USE OR PERFORMANCE OF THE SOFTWARE.
+*
+* 2. TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT SHALL
+* BROADCOM OR ITS LICENSORS BE LIABLE FOR (i) CONSEQUENTIAL, INCIDENTAL,
+* SPECIAL, INDIRECT, OR EXEMPLARY DAMAGES WHATSOEVER ARISING OUT OF OR
+* IN ANY WAY RELATING TO YOUR USE OF OR INABILITY TO USE THE SOFTWARE EVEN
+* IF BROADCOM HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES; OR (ii)
+* ANY AMOUNT IN EXCESS OF THE AMOUNT ACTUALLY PAID FOR THE SOFTWARE ITSELF
+* OR U.S. $1, WHICHEVER IS GREATER. THESE LIMITATIONS SHALL APPLY
+* NOTWITHSTANDING ANY FAILURE OF ESSENTIAL PURPOSE OF ANY LIMITED REMEDY.
+***************************************************************************/
+
+/* parasoft-begin-suppress METRICS-36-3 "A function should not be called from more than 5 different functions" */
+/* DRV-3823 */
+
+#include "cdn_math.h"
+#include <cdn_log.h>
+#include "dsc_utils.h"
+
+/** Return maximum of 2 - element set (int32_t). */
+static int32_t max_signed_int_32(int32_t x, int32_t y) {
+ return ((x > y) ? x : y);
+}
+
+/** Return minimum of 2 - element set (uint32_t). */
+static uint32_t min_unsigned_int_32(uint32_t x, uint32_t y) {
+ return ((x < y) ? x : y);
+}
+
+/** Return x clamped to <min, max> range (uint32_t). */
+static uint32_t clamp_unsigned_int_32(uint32_t x, uint32_t min, uint32_t max) {
+ return ((x > max) ? max : (x < min) ? min : x);
+}
+
+/** Return CDN_EINVAL if int32_t value is not in range <bottom, top>. */
+static uint32_t RangeCheck(const char *s, int32_t val, int32_t bottom, int32_t top) {
+ uint32_t ret = CDN_EOK;
+ if ((val < bottom) || (val > top)) {
+ const char *s_copy = s; /* this ensures parameter is always used in a function */
+ if (s_copy != NULL) {
+ DbgMsg(DBG_GEN_MSG, DBG_CRIT, "%s out of range, needs to be between %d and %d\n", s_copy, bottom, top);
+ }
+ ret = CDN_EINVAL;
+ }
+ return ret;
+}
+
+/** Return CDN_EINVAL if uint32_t value is not in range <bottom, top>. */
+static uint32_t RangeCheck_unsigned(const char *s, uint32_t val, uint32_t bottom, uint32_t top) {
+ uint32_t ret = CDN_EOK;
+ if ((val < bottom) || (val > top)) {
+ const char *s_copy = s; /* this ensures parameter is always used in a function */
+ if (s_copy != NULL) {
+ DbgMsg(DBG_GEN_MSG, DBG_CRIT, "%s out of range, needs to be between %d and %d\n", s_copy, bottom, top);
+ }
+ ret = CDN_EINVAL;
+ }
+ return ret;
+}
+
+/** Extracted part of ComputeOffset */
+static void adjust_offset_in_native_420(const DP_DscConfigFull *dscCfg, uint32_t groupsPerLine,
+ uint32_t grpcnt, int32_t *offset) {
+
+ /* calculations are made in 2 steps to avoid casting composite expression of unsigned type to signed type. */
+ if (grpcnt <= groupsPerLine) {
+ uint32_t offset_subtract_val = (grpcnt * dscCfg->nslBpgOffset) >> OFFSET_FRACTIONAL_BITS;
+ *offset -= (int32_t) offset_subtract_val;
+ } else if (grpcnt <= (2U * groupsPerLine)) {
+ uint32_t offset_add_val = (((grpcnt - groupsPerLine) * dscCfg->secondLineBpgOfs)
+ - ((groupsPerLine * dscCfg->nslBpgOffset) >> OFFSET_FRACTIONAL_BITS));
+ *offset += (int32_t) offset_add_val;
+ } else {
+ uint32_t offset_add_val = (((grpcnt - groupsPerLine) * dscCfg->secondLineBpgOfs)
+ - (((grpcnt - groupsPerLine) * dscCfg->nslBpgOffset) >> OFFSET_FRACTIONAL_BITS));
+ *offset += (int32_t) offset_add_val;
+ }
+}
+
+/*!
+ ************************************************************************
+ * \brief
+ * ComputeOffset() - Compute offset value at a specific group
+ *
+ * \param dscCfg
+ * Pointer to DSC configuration structure
+ * \param pixelsPerGroup
+ * Number of pixels per group
+ * \param groupsPerLine
+ * Number of groups per line
+ * \param grpcnt
+ * Group to Compute offset for
+ * \return
+ * Offset value for the group grpcnt
+ ************************************************************************
+ */
+static int32_t ComputeOffset(const DP_DscConfigFull *dscCfg, uint32_t pixelsPerGroup, uint32_t groupsPerLine, uint32_t grpcnt)
+{
+ int32_t offset = 0;
+ uint32_t grpcntId = (uint32_t) ceil((float64_t) dscCfg->initialXmitDelay / (float64_t) pixelsPerGroup);
+ float64_t bitsPerGroup = (float64_t) pixelsPerGroup * ((float64_t) dscCfg->bitsPerPixel / 16.0);
+
+ if (grpcnt <= grpcntId) {
+ offset = (int32_t) ceil((float64_t) grpcnt * bitsPerGroup);
+ } else {
+ /* calculation is made in 2 steps to avoid casting composite expression of unsigned type to signed type. */
+ uint32_t offset_prepare_value = (uint32_t) ceil(
+ (float64_t) grpcntId * bitsPerGroup)
+ - (((grpcnt - grpcntId) * dscCfg->sliceBpgOffset) >> OFFSET_FRACTIONAL_BITS);
+ offset = (int32_t) offset_prepare_value;
+ }
+
+ if (grpcnt <= groupsPerLine) {
+ offset += ((int32_t) grpcnt * (int32_t) dscCfg->firstLineBpgOfs);
+ } else {
+ /* calculation is made in 2 steps to avoid casting composite expression of unsigned type to signed type. */
+ uint32_t offset_add_val = (((groupsPerLine * dscCfg->firstLineBpgOfs)
+ - (((grpcnt - groupsPerLine) * dscCfg->nflBpgOffset) >> OFFSET_FRACTIONAL_BITS)));
+ offset += (int32_t) offset_add_val;
+ }
+ if (dscCfg->native_420 != 0U) {
+ adjust_offset_in_native_420(dscCfg, groupsPerLine, grpcnt, &offset);
+ }
+ return (offset);
+}
+
+/** Compute first and second line bpg offsets - helper function of ComputeRcParameters() */
+static void compute_line_bpg_offsets(DP_DscConfigFull *dscCfg) {
+ uint32_t firstLineBpgOfs;
+ uint32_t bitsPerComponent = dscCfg->bitsPerComponent;
+ uint32_t useYuvInput = (dscCfg->convertRgb == 0U) ? 1U : 0U;
+ uint32_t uncompressedBpgRate =
+ (dscCfg->native_422 != 0U) ?
+ ((3U * bitsPerComponent) * 4U) :
+ (((3U * bitsPerComponent) + ((useYuvInput != 0U) ? 0U : 2U)) * 3U);
+
+ if (dscCfg->sliceHeight >= 8U) {
+ float32_t first_line_bpg_ofs_add_value = 0.09F * (float32_t) min_unsigned_int_32(34U, dscCfg->sliceHeight - 8U);
+ firstLineBpgOfs = 12U + (uint32_t) first_line_bpg_ofs_add_value;
+ } else {
+ firstLineBpgOfs = 2U * (dscCfg->sliceHeight - 1U);
+ }
+
+ float32_t line_bpg_ofs_top_limit = (float32_t) uncompressedBpgRate - (3.0F * ((float32_t) dscCfg->bitsPerPixel / 16.0F));
+ firstLineBpgOfs = clamp_unsigned_int_32(firstLineBpgOfs, 0U,
+ (uint32_t) line_bpg_ofs_top_limit);
+
+ uint32_t secondLineBpgOfs = (dscCfg->native_420 != 0U) ? 12U : 0U;
+ secondLineBpgOfs = clamp_unsigned_int_32(secondLineBpgOfs, 0U,
+ (uint32_t) line_bpg_ofs_top_limit);
+
+ /* values are calculated - update the structure */
+ dscCfg->firstLineBpgOfs = firstLineBpgOfs;
+ (void) RangeCheck_unsigned("firstLineBpgOffset", dscCfg->firstLineBpgOfs, 0, 31U);
+ dscCfg->secondLineBpgOfs = secondLineBpgOfs;
+ (void) RangeCheck_unsigned("secondLineBpgOffset", dscCfg->secondLineBpgOfs, 0, 31U);
+}
+
+/** Compute initial lines parameter - helper function of ComputeRcParameters() */
+static void compute_initial_lines(DP_DscConfigFull *dscCfg) {
+ float64_t k1;
+ const float64_t bitsPerPixel = (float64_t) dscCfg->bitsPerPixel / 16.0;
+
+ if (dscCfg->bitsPerComponent == 8U) {
+ k1 = 296.0;
+ } else {
+ k1 = 320.0;
+ }
+
+ if (dscCfg->splitPanel) { /* when both encoders are used in parallel for one video stream */
+ dscCfg->initialLines = (uint32_t) ceil(
+ (k1 + (float64_t) dscCfg->initialXmitDelay
+ + ((((float64_t) dscCfg->chunkSize * 8.0) + 144.0) / bitsPerPixel))
+ / (float64_t) dscCfg->sliceWidth);
+ } else {
+ dscCfg->initialLines = (uint32_t) ceil(
+ (k1 + (float64_t) dscCfg->initialXmitDelay
+ + ( (ceil( (1.0 - (bitsPerPixel / 48.0))
+ * ((float64_t) dscCfg->chunkSize * 8.0)
+ )
+ + 144.0
+ ) / bitsPerPixel
+ )
+ ) / (float64_t) dscCfg->sliceWidth
+ );
+ }
+}
+
+/** Compute initialDecDelay parameter - helper function of ComputeRcParameters() */
+static void compute_initial_dec_delay(DP_DscConfigFull *dscCfg, uint32_t pixelsPerGroup,
+ uint32_t groupsPerLine) {
+ uint32_t hrdDelay;
+ uint32_t initialDelay = dscCfg->initialXmitDelay;
+ int32_t initialFullnessOfs = (int32_t) dscCfg->initialOffset;
+ int32_t rbsMin = ((int32_t) dscCfg->rcModelSize - initialFullnessOfs);
+ const float64_t bitsPerPixel = (float64_t) dscCfg->bitsPerPixel / 16.0;
+
+ if ((dscCfg->dscVersionMinor == 2U)
+ && ((dscCfg->native_420 != 0U) || (dscCfg->native_422 != 0U))) {
+ /* OPTIMIZED computation of rbsMin: */
+ /* Compute max by sampling offset at points of inflection */
+ /* *MODEL NOTE* MN_RBS_MIN */
+ int32_t maxOffset = ComputeOffset(dscCfg, pixelsPerGroup, groupsPerLine,
+ (uint32_t) ceil(((float64_t) initialDelay / (float64_t) pixelsPerGroup))); /* After initial delay */
+ maxOffset = max_signed_int_32(maxOffset,
+ ComputeOffset(dscCfg, pixelsPerGroup, groupsPerLine, groupsPerLine)); /* After first line */
+ maxOffset = max_signed_int_32(maxOffset,
+ ComputeOffset(dscCfg, pixelsPerGroup, groupsPerLine, 2U * groupsPerLine));
+ rbsMin += maxOffset;
+ } else {
+ /* DSC 1.1 method */
+ rbsMin += ((int32_t) ceil(
+ ((float64_t) initialDelay * bitsPerPixel)))
+ + ((int32_t) groupsPerLine * (int32_t) dscCfg->firstLineBpgOfs);
+ }
+
+ hrdDelay = (uint32_t) (ceil((float64_t) rbsMin / bitsPerPixel));
+ dscCfg->initialDecDelay = hrdDelay - initialDelay;
+ (void) RangeCheck_unsigned("initialDecDelay", dscCfg->initialDecDelay, 0, 65535U);
+}
+
+/** Compute non-first and non-second line bpg offsets - helper function of ComputeRcParameters() */
+static void compute_nfl_nsl_bpg_offsets(DP_DscConfigFull *dscCfg, uint32_t *invalid) {
+ /* Calculate nflBpgOffset */
+ if (dscCfg->sliceHeight > 1U) {
+ uint32_t first_line_bpg_ofs_shifted = dscCfg->firstLineBpgOfs << OFFSET_FRACTIONAL_BITS;
+ dscCfg->nflBpgOffset = (uint32_t) ceil(
+ (float64_t) first_line_bpg_ofs_shifted / ((float64_t) dscCfg->sliceHeight - 1.0));
+ } else {
+ dscCfg->nflBpgOffset = 0U;
+ }
+ if (dscCfg->nflBpgOffset > 65535U) {
+ DbgMsg(DBG_GEN_MSG, DBG_CRIT, "nflBpgOffset is too large for this slice height\n");
+ *invalid = 1U; /* status of parent function is being modified, calculation continues though */
+ }
+
+ /* Calculate nslBpgOffset */
+ if (dscCfg->sliceHeight > 2U) {
+ uint32_t second_line_bpg_ofs_shifted = dscCfg->secondLineBpgOfs << OFFSET_FRACTIONAL_BITS;
+ dscCfg->nslBpgOffset = (uint32_t) ceil(
+ (float64_t) second_line_bpg_ofs_shifted / ((float64_t) dscCfg->sliceHeight - 1.0));
+ } else {
+ dscCfg->nslBpgOffset = 0U;
+ }
+ if (dscCfg->nslBpgOffset > 65535U) {
+ DbgMsg(DBG_GEN_MSG, DBG_CRIT, "nslBpgOffset is too large for this slice height\n");
+ *invalid = 1U;
+ }
+}
+
+/** Compute slice bpg offset - helper function of ComputeRcParameters() */
+static void compute_slice_bpg_offset(DP_DscConfigFull *dscCfg, uint32_t numExtraMuxBits,
+ uint32_t groupsTotal, uint32_t pixelsPerGroup) {
+ dscCfg->sliceBpgOffset = (uint32_t) ceil(
+ ((float64_t)((uint32_t) 1U << OFFSET_FRACTIONAL_BITS)
+ * (((float64_t) dscCfg->rcModelSize - (float64_t) dscCfg->initialOffset) + (float64_t) numExtraMuxBits))
+ / (float64_t) groupsTotal);
+ (void) RangeCheck_unsigned("sliceBpgOffset", dscCfg->sliceBpgOffset, 0, 65535U);
+
+ if (dscCfg->sliceHeight == 1U) {
+ if (dscCfg->firstLineBpgOfs > 0U) {
+ DbgMsg(DBG_GEN_MSG, DBG_CRIT, "For sliceHeight == 1, the FIRST_LINE_BPG_OFFSET must be 0\n");
+ }
+ } else if ((((float32_t) pixelsPerGroup * ((float32_t) dscCfg->bitsPerPixel / 16.0F))
+ - (((float32_t) dscCfg->sliceBpgOffset + (float32_t) dscCfg->nflBpgOffset)
+ / (float32_t) ((uint32_t) 1U << OFFSET_FRACTIONAL_BITS))) < (1.0F + (5.0F * (float32_t) pixelsPerGroup))) {
+ DbgMsg(DBG_GEN_MSG, DBG_CRIT, "The bits/pixel allocation for non-first lines is too low (<5.33bpp).\n"
+ "Consider decreasing FIRST_LINE_BPG_OFFSET.");
+ } else {
+ /* do nothing */
+ }
+}
+
+/** Compute final offset and final scale - helper function of ComputeRcParameters() */
+static void compute_final_offset_scale(DP_DscConfigFull *dscCfg, uint32_t *finalScale,
+ uint32_t numExtraMuxBits) {
+ uint32_t finalValue = (dscCfg->rcModelSize
+ - (((dscCfg->initialXmitDelay * dscCfg->bitsPerPixel) + 8U) >> 4U)) + numExtraMuxBits;
+ dscCfg->finalOffset = finalValue;
+ (void) RangeCheck_unsigned("finalOffset", dscCfg->finalOffset, 0, 65535U);
+ if (finalValue >= dscCfg->rcModelSize) {
+ DbgMsg(DBG_GEN_MSG, DBG_CRIT, "The finalOffset must be less than the rcModelSize. "
+ "Try increasing initialXmitDelay.\n");
+ }
+ /* update finalScale - variable is then used in the parent function */
+ *finalScale = (8U * dscCfg->rcModelSize) / (dscCfg->rcModelSize - finalValue);
+ if (*finalScale > 63U) {
+ DbgMsg(DBG_GEN_MSG, DBG_WARN, "WARNING: A final scale value > than 63/8 may have undefined"
+ " behavior on some implementations. Try increasing initialXmitDelay.\n");
+ }
+}
+
+/** Compute numExtraMuxBits - helper function of ComputeRcParameters() */
+static void compute_num_extra_mux_bits(const DP_DscConfigFull *dscCfg, uint32_t *numExtraMuxBits,
+ const uint32_t numSsps) {
+ uint32_t muxWordSize = (dscCfg->bitsPerComponent <= 10U) ? 48U : 64U;
+ uint32_t sliceBits;
+
+ /* numExtraMuxBits is then used in the parent function */
+ if (dscCfg->convertRgb != 0U) {
+ *numExtraMuxBits = (numSsps * (muxWordSize + (((4U * dscCfg->bitsPerComponent) + 4U) - 2U)));
+ } else if (dscCfg->native_422 == 0U) { /* YCbCr */
+ *numExtraMuxBits = (numSsps * muxWordSize) + ((4U * dscCfg->bitsPerComponent) + 4U)
+ + ((2U * (4U * dscCfg->bitsPerComponent)) - 2U);
+ } else {
+ *numExtraMuxBits = (numSsps * muxWordSize) + ((4U * dscCfg->bitsPerComponent) + 4U)
+ + ((3U * (4U * dscCfg->bitsPerComponent)) - 2U);
+ }
+ sliceBits = 8U * dscCfg->chunkSize * dscCfg->sliceHeight;
+ while ((*numExtraMuxBits > 0U) && (((sliceBits - *numExtraMuxBits) % muxWordSize) != 0U)) {
+ (*numExtraMuxBits)--;
+ }
+}
+
+/** Compute number of bytes per chunk - helper function of ComputeRcParameters() */
+static void compute_chunk_size(DP_DscConfigFull *dscCfg, const uint32_t slicew) {
+ dscCfg->chunkSize = (uint32_t) (ceil(
+ ((float64_t) slicew * ((float64_t) dscCfg->bitsPerPixel / 16.0)) / 8.0));
+ DbgMsg(DBG_GEN_MSG, DBG_CRIT, "%s: chunkSize = %d, bitsPerPixel %f, slicew %d\n", __func__,
+ dscCfg->chunkSize, (float32_t) dscCfg->bitsPerPixel / 16.0F, slicew );
+ (void) RangeCheck_unsigned("chunkSize", dscCfg->chunkSize, 0, 65535);
+}
+
+/** 1st function grouping various calculations for ComputeRcParameters() function */
+static void compute_rc_params_1(DP_DscConfigFull *dscCfg, const uint32_t slicew,
+ uint32_t *numExtraMuxBits, const uint32_t numSsps) {
+ compute_line_bpg_offsets(dscCfg);
+ compute_chunk_size(dscCfg, slicew);
+ compute_num_extra_mux_bits(dscCfg, numExtraMuxBits, numSsps);
+}
+
+/** 2nd function grouping various calculations for ComputeRcParameters() function */
+static void compute_rc_params_2(DP_DscConfigFull *dscCfg, uint32_t numExtraMuxBits, uint32_t *invalid,
+ uint32_t groupsTotal, uint32_t pixelsPerGroup) {
+ uint32_t finalScale;
+
+ compute_final_offset_scale(dscCfg, &finalScale, numExtraMuxBits);
+ compute_nfl_nsl_bpg_offsets(dscCfg, invalid);
+ compute_slice_bpg_offset(dscCfg, numExtraMuxBits, groupsTotal, pixelsPerGroup);
+
+ /* BEGIN scaleIncrementInterval fix */
+ if (finalScale > 9U) {
+ /* Note: the following calculation assumes that the rcXformOffset crosses 0 at some point. */
+ /* If the zero-crossing doesn't occur in a configuration, we recommend to reconfigure the */
+ /* rcModelSize and thresholds to be smaller for that configuration. */
+ dscCfg->scaleIncrementInterval = ((((uint32_t) 1U << OFFSET_FRACTIONAL_BITS) * dscCfg->finalOffset)
+ / ((finalScale - 9U)
+ * (dscCfg->nflBpgOffset + dscCfg->sliceBpgOffset + dscCfg->nslBpgOffset)));
+ if (dscCfg->scaleIncrementInterval > 65535U) {
+ DbgMsg(DBG_GEN_MSG, DBG_CRIT, "scaleIncrementInterval is too large for this slice height.\n");
+ *invalid = 1U;
+ }
+ } else {
+ dscCfg->scaleIncrementInterval = 0U;
+ }
+ /* END scaleIncrementInterval fix */
+}
+
+/** Compute RC parameters */
+static uint32_t ComputeRcParameters(DP_DscConfigFull *dscCfg, uint32_t pixelsPerGroup, uint32_t numSsps) {
+ uint32_t invalid = 0U;
+
+ uint32_t numExtraMuxBits;
+ uint32_t slicew = ((dscCfg->native_420 != 0U) || (dscCfg->native_422 != 0U)) ? (dscCfg->sliceWidth >> 1U) : dscCfg->sliceWidth; /* /2 in 4:2:0 mode */
+ uint32_t groupsPerLine = (slicew + (pixelsPerGroup - 1U)) / pixelsPerGroup;
+ uint32_t groupsTotal = groupsPerLine * dscCfg->sliceHeight;
+
+ if (groupsPerLine < (dscCfg->initialScaleValue - 8U)) {
+ dscCfg->initialScaleValue = groupsPerLine + 8U;
+ }
+
+ dscCfg->scaleDecrementInterval = (dscCfg->initialScaleValue > 8U) ? (groupsPerLine / (dscCfg->initialScaleValue - 8U)) : 4095U;
+ (void) RangeCheck_unsigned("scaleDecrementInterval", dscCfg->scaleDecrementInterval, 0, 4095U);
+
+ /* call grouping functions that contains further steps - need to be called in order */
+ compute_rc_params_1(dscCfg, slicew, &numExtraMuxBits, numSsps);
+ compute_rc_params_2(dscCfg, numExtraMuxBits, &invalid, groupsTotal, pixelsPerGroup);
+
+ /* calculate initialDecDelay */
+ compute_initial_dec_delay(dscCfg, pixelsPerGroup, groupsPerLine);
+
+ /* calculate initial lines */
+ compute_initial_lines(dscCfg);
+
+ return (invalid);
+}
+
+/** Part 1 out of 4 of CheckInputParameters()'s routine. */
+static void check_input_parameters_1(const DP_DscConfigFull *dscCfg, uint32_t *status) {
+ /* Range check performs checking and can optionally print a warning. */
+ if (RangeCheck_unsigned("picWidth", dscCfg->picWidth, 0U, 65535U) != CDN_EOK) {
+ *status = CDN_EINVAL; /* status of parent function is being modified */
+ }
+ /* Every parameter is being checked even if one is already invalid */
+ if (RangeCheck_unsigned("picHeight", dscCfg->picHeight, 0U, 65535U) != CDN_EOK) {
+ *status = CDN_EINVAL;
+ }
+
+ if (RangeCheck_unsigned("linebufDepth", dscCfg->linebufDepth, 8U, 13U) != CDN_EOK) { /* 13 or 16? */
+ *status = CDN_EINVAL;
+ }
+
+ if (RangeCheck_unsigned("rcTgtOffsetHi", dscCfg->rcTgtOffsetHi, 0U, 15U) != CDN_EOK) {
+ *status = CDN_EINVAL;
+ }
+
+ if (RangeCheck_unsigned("rcTgtOffsetLo", dscCfg->rcTgtOffsetLo, 0U, 15U) != CDN_EOK) {
+ *status = CDN_EINVAL;
+ }
+
+ if (RangeCheck_unsigned("bitsPerPixel (*16)", dscCfg->bitsPerPixel, 96U, 1023U) != CDN_EOK) {
+ *status = CDN_EINVAL;
+ }
+
+ if (RangeCheck_unsigned("rcEdgeFactor", dscCfg->rcEdgeFactor, 0U, 15U) != CDN_EOK) {
+ *status = CDN_EINVAL;
+ }
+}
+
+/* parasoft-begin-suppress MISRA2012-RULE-2_7-4 "Parameter is not used" */
+/* This is a Parasoft bug, all parameters of check_in_params_2_iterative_2 are used. */
+
+/** Part 1 of iterative checks to be called by check_input_parameters_2() */
+static void check_in_params_2_iterative_1(const DP_DscConfigFull *dscCfg, uint32_t *status,
+ const int32_t *prevOffset, const uint32_t *prevMaxQp, const uint32_t i) {
+
+ if (RangeCheck("rangeBpgOffset", dscCfg->rcRangeParameters[i].rangeBpgOffset, -32,
+ 31) != CDN_EOK) {
+ *status = CDN_EINVAL;
+ }
+
+ if (i > 0U) { /* if values were updated by parent function at least 1 time */
+ if ((*prevOffset < dscCfg->rcRangeParameters[i].rangeBpgOffset)) {
+ DbgMsg(DBG_GEN_MSG, DBG_WARN, "WARNING: The RC_OFFSET values should not increase as the range increases\n");
+ }
+ if ((*prevMaxQp > dscCfg->rcRangeParameters[i].rangeMaxQp)) {
+ DbgMsg(DBG_GEN_MSG, DBG_WARN, "WARNING: The RC_MAX_QP values should not decrease as the range increases\n");
+ }
+ }
+ /* calculate part of the limit here instead of calculating it 4 different places */
+ uint32_t range_max_qp_part_of_top_limit = 2U * (dscCfg->bitsPerComponent - 8U);
+ if (RangeCheck_unsigned("rangeMaxQp", dscCfg->rcRangeParameters[i].rangeMaxQp, 0,
+ 15U + range_max_qp_part_of_top_limit) != CDN_EOK) {
+ *status = CDN_EINVAL;
+ }
+ if ((dscCfg->dscVersionMinor == 1U) && (dscCfg->convertRgb != 1U) /* when using YUV in DSC 1.1 */
+ && (dscCfg->rcRangeParameters[i].rangeMaxQp
+ > (12U + range_max_qp_part_of_top_limit))) {
+ DbgMsg(DBG_GEN_MSG, DBG_CRIT, "ERROR: In DSC 1.1 mode with YCbCr, the max QP for range %d must be less than %d\n",
+ i, 12U + range_max_qp_part_of_top_limit);
+ *status = CDN_EINVAL;
+ }
+ if (RangeCheck_unsigned("rangeMinQp", dscCfg->rcRangeParameters[i].rangeMinQp, 0,
+ 15U + range_max_qp_part_of_top_limit) != CDN_EOK) {
+ *status = CDN_EINVAL;
+ }
+
+}
+/* parasoft-end-suppress MISRA2012-RULE-2_7-4 "Parameter is not used" */
+
+/* parasoft-begin-suppress MISRA2012-RULE-2_7-4 "Parameter is not used" */
+/* This is a Parasoft bug, all parameters of check_in_params_2_iterative_2 are used. */
+
+/** Part 2 of iterative checks to be called by check_input_parameters_2() */
+static void check_in_params_2_iterative_2(const DP_DscConfigFull *dscCfg, uint32_t *status,
+ const uint32_t *prevMinQp, uint32_t *prevThresh, const uint32_t i) {
+ if ((i > 0U) && (*prevMinQp > dscCfg->rcRangeParameters[i].rangeMinQp)) {
+ DbgMsg(DBG_GEN_MSG, DBG_WARN, "WARNING: The rangeMinQp values should not decrease as the range increases\n");
+ }
+
+ /* parent function calls this function up to i=DP_DSC_NUM_BUF_RANGES-1, */
+ if (i < (DP_DSC_NUM_BUF_RANGES - 1U)) { /* this excludes the last call */
+ if (RangeCheck_unsigned("rcBufThresh", dscCfg->rcBufThresh[i], 0,
+ dscCfg->rcModelSize) != CDN_EOK) {
+ *status = CDN_EINVAL;
+ }
+
+ if ((dscCfg->rcBufThresh[i] & 0x3fU) != 0U) {
+ DbgMsg(DBG_GEN_MSG, DBG_CRIT, "All rcBufThresh must be evenly divisible by 64");
+ *status = CDN_EINVAL;
+ }
+ if ((i > 0U) && (*prevThresh > dscCfg->rcBufThresh[i])) {
+ DbgMsg(DBG_GEN_MSG, DBG_CRIT, "WARNING: The rcBufThresh values should not decrease as the range increases\n");
+ }
+ *prevThresh = dscCfg->rcBufThresh[i];
+ }
+}
+
+/* parasoft-end-suppress MISRA2012-RULE-2_7-4 "Parameter is not used" */
+
+/** Part 2 of CheckInputParameters()'s routine. */
+static void check_input_parameters_2(const DP_DscConfigFull *dscCfg, uint32_t *status) {
+ uint32_t prevMinQp = dscCfg->rcRangeParameters[0].rangeMinQp;
+ uint32_t prevMaxQp = dscCfg->rcRangeParameters[0].rangeMaxQp;
+ int32_t prevOffset = dscCfg->rcRangeParameters[0].rangeBpgOffset;
+ uint32_t prevThresh = dscCfg->rcBufThresh[0];
+
+ uint32_t i;
+ if (RangeCheck_unsigned("rcQuantIncrLimit1", dscCfg->rcQuantIncrLimit1, 0U, 31U) != CDN_EOK) {
+ *status = CDN_EINVAL;
+ }
+
+ if (RangeCheck_unsigned("rcQuantIncrLimit0", dscCfg->rcQuantIncrLimit0, 0U, 31U) != CDN_EOK) {
+ *status = CDN_EINVAL;
+ }
+
+ for (i = 0U; i < DP_DSC_NUM_BUF_RANGES; ++i) {
+ /* perform iterative actions */
+ check_in_params_2_iterative_1(dscCfg, status, &prevOffset, &prevMaxQp, i);
+ check_in_params_2_iterative_2(dscCfg, status, &prevMinQp, &prevThresh, i);
+
+ /* update values */
+ prevMinQp = dscCfg->rcRangeParameters[i].rangeMinQp;
+ prevMaxQp = dscCfg->rcRangeParameters[i].rangeMaxQp;
+ prevOffset = dscCfg->rcRangeParameters[i].rangeBpgOffset;
+ /* prevThresh is updated inside check_input_params_2_iterative_2() except for last call. */
+ }
+}
+
+/** Part 3 out of 4 of CheckInputParameters()'s routine. */
+static void check_input_parameters_3(const DP_DscConfigFull *dscCfg, uint32_t *status) {
+ /* Range check performs checking and can optionally print a warning. */
+ if (RangeCheck_unsigned("rcBufThresh", dscCfg->rcBufThresh[0], 0,
+ dscCfg->rcModelSize) != CDN_EOK) {
+ *status = CDN_EINVAL; /* status of parent function is being modified */
+ }
+
+ if (RangeCheck_unsigned("rcModelSize", dscCfg->rcModelSize, 0, 65535) != CDN_EOK) {
+ *status = CDN_EINVAL;
+ }
+
+ if (RangeCheck_unsigned("initialXmitDelay", dscCfg->initialXmitDelay, 0, 1023) != CDN_EOK) {
+ *status = CDN_EINVAL;
+ }
+
+ if (RangeCheck_unsigned("blockPredEnable", dscCfg->blockPredEnable, 0, 1) != CDN_EOK) {
+ *status = CDN_EINVAL;
+ }
+
+ if (RangeCheck_unsigned("initialOffset", dscCfg->initialOffset, 0,
+ dscCfg->rcModelSize) != CDN_EOK) {
+ *status = CDN_EINVAL;
+ }
+
+ if (RangeCheck_unsigned("flatnessMinQp", dscCfg->flatnessMinQp, 0, 31) != CDN_EOK) {
+ *status = CDN_EINVAL;
+ }
+
+ if (RangeCheck_unsigned("flatnessMaxQp", dscCfg->flatnessMaxQp, 0, 31) != CDN_EOK) {
+ *status = CDN_EINVAL;
+ }
+}
+
+/** Part 4 out of 4 of CheckInputParameters()'s routine. */
+static void check_input_parameters_4(const DP_DscConfigFull *dscCfg, uint32_t *status) {
+ /* Range check performs checking and can optionally print a warning. */
+ if (RangeCheck_unsigned("rcEdgeFactor", dscCfg->rcEdgeFactor, 0U, 15U) != CDN_EOK) {
+ *status = CDN_EINVAL; /* status of parent function is being modified */
+ }
+ if (RangeCheck_unsigned("rcQuantIncrLimit1", dscCfg->rcQuantIncrLimit1, 0U, 31U) != CDN_EOK) {
+ *status = CDN_EINVAL;
+ }
+
+ if (RangeCheck_unsigned("rcQuantIncrLimit0", dscCfg->rcQuantIncrLimit0, 0U, 31U) != CDN_EOK) {
+ *status = CDN_EINVAL;
+ }
+ if (RangeCheck_unsigned("vbrEnable", dscCfg->vbrEnable, 0, 1) != CDN_EOK) {
+ *status = CDN_EINVAL;
+ }
+
+ if (RangeCheck_unsigned("sliceWidth", dscCfg->sliceWidth, 1, 65535) != CDN_EOK) {
+ *status = CDN_EINVAL;
+ }
+
+ if (RangeCheck_unsigned("sliceHeight", dscCfg->sliceHeight, 1, 65535) != CDN_EOK) {
+ *status = CDN_EINVAL;
+ }
+}
+
+/** Verify if input parameters are valid. Returns CDN_OK if yes, CDN_EINVAL if no. */
+static uint32_t CheckInputParameters(const DP_DscConfigFull *dscCfg)
+{
+ uint32_t status = CDN_EOK;
+
+ /* Function's routine is split into 4 smaller functions */
+ check_input_parameters_1(dscCfg, &status);
+ check_input_parameters_2(dscCfg, &status);
+ check_input_parameters_3(dscCfg, &status);
+ check_input_parameters_4(dscCfg, &status);
+
+ return status;
+}
+
+/** Extracted part of DscCopyCfgToFull */
+static void dsc_copy_cfg_to_full_1(const DP_DscConfig *dscCfg, DP_DscConfigFull *dscCfgFull) {
+ /* Configuration is copied from DP_DscConfig structure to DP_DscConfigFull structure */
+ dscCfgFull->picWidth = dscCfg->picWidth;
+ dscCfgFull->picHeight = dscCfg->picHeight;
+ dscCfgFull->rcTgtOffsetHi = dscCfg->rcTgtOffsetHi;
+ dscCfgFull->rcTgtOffsetLo = dscCfg->rcTgtOffsetLo;
+ dscCfgFull->rcModelSize = dscCfg->rcModelSize;
+ dscCfgFull->flatnessMinQp = dscCfg->flatnessMinQp;
+ dscCfgFull->flatnessMaxQp = dscCfg->flatnessMaxQp;
+ dscCfgFull->vbrEnable = dscCfg->vbrEnable;
+ dscCfgFull->ppsIdentifier = dscCfg->ppsIdentifier;
+ dscCfgFull->splitPanel = dscCfg->splitPanel;
+ dscCfgFull->hTotal = dscCfg->hTotal;
+ /* This function is only to be called by DscCopyCfgToFull() as a part of its routine */
+}
+
+/** Extracted part of DscCopyCfgToFull */
+static void dsc_copy_cfg_to_full_2(const DP_DscConfig *dscCfg, DP_DscConfigFull *dscCfgFull) {
+ /* Configuration is copied from DP_DscConfig structure to DP_DscConfigFull structure */
+ dscCfgFull->linebufDepth = dscCfg->linebufDepth;
+ dscCfgFull->sliceWidth = dscCfg->sliceWidth;
+ dscCfgFull->sliceHeight = dscCfg->sliceHeight;
+ dscCfgFull->bitsPerPixel = dscCfg->bitsPerPixel * 16U;
+ dscCfgFull->rcEdgeFactor = dscCfg->rcEdgeFactor;
+ dscCfgFull->rcQuantIncrLimit1 = dscCfg->rcQuantIncrLimit1;
+ dscCfgFull->rcQuantIncrLimit0 = dscCfg->rcQuantIncrLimit0;
+ dscCfgFull->initialXmitDelay = dscCfg->initialXmitDelay;
+ dscCfgFull->blockPredEnable = dscCfg->blockPredEnable;
+ dscCfgFull->initialOffset = dscCfg->initialOffset;
+ dscCfgFull->flatnessDetThresh = dscCfg->flatnessDetThresh;
+ /* This function is only to be called by DscCopyCfgToFull() as a part of its routine */
+}
+
+/** Copy the DSC configuration from DP_DscConfig structure to DP_DscConfigFull structure */
+uint32_t DscCopyCfgToFull(const DP_DscConfig *dscCfg, DP_DscConfigFull *dscCfgFull)
+{
+ uint32_t i;
+ uint32_t ret = CDN_EOK;
+ dscCfgFull->native_420 = 0U;
+ dscCfgFull->native_422 = 0U;
+ dscCfgFull->simple_422 = 0U;
+ dscCfgFull->convertRgb = 1U;
+ dscCfgFull->secondLineBpgOfs = 0U;
+ dscCfgFull->secondLineOfsAdj = 0U;
+ dscCfgFull->dscVersionMinor = 1U;
+
+ switch (dscCfg->bitsPerComponent) {
+ case DP_BITS_PER_COMPONENT_8:
+ dscCfgFull->bitsPerComponent = 8U;
+ break;
+ case DP_BITS_PER_COMPONENT_10:
+ dscCfgFull->bitsPerComponent = 10U;
+ break;
+ /* if the value does not fit any DP_BitsPerComponent enum value */
+ default:
+ DbgMsg(DBG_GEN_MSG, DBG_CRIT, "Wrong BPC value\n");
+ ret = CDN_ENOTSUP;
+ break;
+ }
+
+ /* Copy next parts of the structure */
+ dsc_copy_cfg_to_full_1(dscCfg, dscCfgFull);
+ dsc_copy_cfg_to_full_2(dscCfg, dscCfgFull);
+
+ /* Iterate over all elements of rcBufThresh (DP_DSC_NUM_BUF_RANGES - 1U) */
+ for (i = 0U; i < (DP_DSC_NUM_BUF_RANGES - 1U); i++) {
+ dscCfgFull->rcBufThresh[i] = dscCfg->rcBufThresh[i];
+ }
+
+ /* Iterate over all elements of rcRangeParameters (DP_DSC_NUM_BUF_RANGES) */
+ for (i = 0U; i < DP_DSC_NUM_BUF_RANGES; i++) {
+ dscCfgFull->rcRangeParameters[i].rangeBpgOffset =
+ dscCfg->rcRangeParameters[i].rangeBpgOffset;
+ dscCfgFull->rcRangeParameters[i].rangeMinQp = dscCfg->rcRangeParameters[i].rangeMinQp;
+ dscCfgFull->rcRangeParameters[i].rangeMaxQp = dscCfg->rcRangeParameters[i].rangeMaxQp;
+ }
+ return ret;
+
+}
+
+/** Extracted part of DscCopyFromFull */
+static void dsc_copy_from_full_1(DP_DscConfig *dscCfg, const DP_DscConfigFull *dscCfgFull) {
+ /* Configuration is copied from DP_DscConfigFull structure to DP_DscConfig structure */
+ dscCfg->linebufDepth = dscCfgFull->linebufDepth;
+ dscCfg->sliceWidth = dscCfgFull->sliceWidth;
+ dscCfg->sliceHeight = dscCfgFull->sliceHeight;
+ dscCfg->rcModelSize = dscCfgFull->rcModelSize;
+ dscCfg->flatnessMinQp = dscCfgFull->flatnessMinQp;
+ dscCfg->flatnessMaxQp = dscCfgFull->flatnessMaxQp;
+ dscCfg->vbrEnable = dscCfgFull->vbrEnable;
+ dscCfg->ppsIdentifier = dscCfgFull->ppsIdentifier;
+ dscCfg->splitPanel = dscCfgFull->splitPanel;
+ dscCfg->hTotal = dscCfgFull->hTotal;
+ dscCfg->flatnessDetThresh = dscCfgFull->flatnessDetThresh;
+ /* This function is only to be called by DscCopyCfgFromFull() as a part of its routine */
+}
+
+/** Extracted part of DscCopyFromFull */
+static void dsc_copy_from_full_2(DP_DscConfig *dscCfg, const DP_DscConfigFull *dscCfgFull) {
+ /* Configuration is copied from DP_DscConfigFull structure to DP_DscConfig structure */
+ dscCfg->picWidth = dscCfgFull->picWidth;
+ dscCfg->picHeight = dscCfgFull->picHeight;
+ dscCfg->rcTgtOffsetHi = dscCfgFull->rcTgtOffsetHi;
+ dscCfg->rcTgtOffsetLo = dscCfgFull->rcTgtOffsetLo;
+ dscCfg->bitsPerPixel = dscCfgFull->bitsPerPixel / 16U;
+ dscCfg->rcEdgeFactor = dscCfgFull->rcEdgeFactor;
+ dscCfg->rcQuantIncrLimit1 = dscCfgFull->rcQuantIncrLimit1;
+ dscCfg->rcQuantIncrLimit0 = dscCfgFull->rcQuantIncrLimit0;
+ dscCfg->initialXmitDelay = dscCfgFull->initialXmitDelay;
+ dscCfg->blockPredEnable = dscCfgFull->blockPredEnable;
+ dscCfg->initialOffset = dscCfgFull->initialOffset;
+ /* This function is only to be called by DscCopyCfgFromFull() as a part of its routine */
+}
+
+/** Copy the DSC configuration from DP_DscConfigFull structure to DP_DscConfig structure */
+void DscCopyFromFull(DP_DscConfig *dscCfg, const DP_DscConfigFull *dscCfgFull)
+{
+ uint32_t i;
+
+ switch (dscCfgFull->bitsPerComponent) {
+ case 8U:
+ dscCfg->bitsPerComponent = DP_BITS_PER_COMPONENT_8;
+ break;
+ case 10U:
+ dscCfg->bitsPerComponent = DP_BITS_PER_COMPONENT_10;
+ break;
+ default:
+ /* default clause and comment */
+ break;
+ }
+
+ /* Copy next parts of the structure */
+ dsc_copy_from_full_1(dscCfg, dscCfgFull);
+ dsc_copy_from_full_2(dscCfg, dscCfgFull);
+
+ /* Continue copying */
+ for (i = 0U; i < (DP_DSC_NUM_BUF_RANGES - 1U); i++) {
+ dscCfg->rcBufThresh[i] = dscCfgFull->rcBufThresh[i];
+ }
+
+ for (i = 0U; i < DP_DSC_NUM_BUF_RANGES; i++) {
+ dscCfg->rcRangeParameters[i].rangeBpgOffset =
+ dscCfgFull->rcRangeParameters[i].rangeBpgOffset;
+ dscCfg->rcRangeParameters[i].rangeMinQp = dscCfgFull->rcRangeParameters[i].rangeMinQp;
+ dscCfg->rcRangeParameters[i].rangeMaxQp = dscCfgFull->rcRangeParameters[i].rangeMaxQp;
+ }
+}
+
+uint32_t DscCalcParameters(DP_DscConfigFull *dscCfg)
+{
+ uint32_t numSsps;
+ uint32_t pixelsPerGroup = 3U;
+ uint32_t status;
+
+ dscCfg->initialScaleValue = (8U * dscCfg->rcModelSize)
+ / (dscCfg->rcModelSize - dscCfg->initialOffset);
+
+ /* Compute rate buffer size for auto mode */
+ if (dscCfg->native_422 != 0U) {
+ numSsps = 4U;
+ } else {
+ numSsps = 3U;
+ }
+
+ status = CheckInputParameters(dscCfg);
+ /* continue if input parameters are correct */
+ if (status == CDN_EOK) {
+ status = ComputeRcParameters(dscCfg, pixelsPerGroup, numSsps);
+ }
+
+ return status;
+}
+
+/* ! Put bits into a buffer in memory */
+/*! \param val Value to write
+ \param size Number of bits to write
+ \param buf Pointer to buffer location
+ \param bitCount Bit index into buffer (modified) */
+static void PutBits(uint32_t val, uint32_t size, uint8_t *buf, uint32_t *bitCount)
+{
+ int32_t i;
+ uint32_t curbit;
+ uint32_t bitcntmod8;
+ uint32_t bufidx;
+
+ if (size > 32U) {
+ DbgMsg(DBG_GEN_MSG, DBG_CRIT, "error: PutBits supports max of 32 bits\n");
+ }
+ for (i = (int32_t) size - 1; i >= 0; --i) {
+ bitcntmod8 = (*bitCount) % 8U;
+ bufidx = (*bitCount) >> 3U;
+ curbit = (val >> (uint32_t)i) & 1U;
+ if (bitcntmod8 == 0U) {
+ buf[bufidx] = 0U; /* Zero current byte */
+ }
+ if (curbit != 0U) {
+ /* parasoft-begin-suppress MISRA2012-RULE-12_2-2 "Shifting operation should be
+ enclosed with if checking that RHS operand does not exceed the upper limit" */
+ buf[bufidx] |= (1U << (7U - bitcntmod8));
+ /* parasoft-end-suppress MISRA2012-RULE-12_2-2 */
+ }
+ (*bitCount)++;
+ }
+}
+
+void static dsc_write_pps_1(uint8_t *buf, const DP_DscConfigFull *dscCfg, uint32_t *nbits) {
+ uint32_t i;
+
+ /* For every row of this array we have a pair of value and size: arguments of PutBits() */
+ uint32_t parameter_array[25][2] = {
+ {1U, 4U}, /* dsc major version */
+ {dscCfg->dscVersionMinor, 4U},
+ {dscCfg->ppsIdentifier, 8U},
+ {0U, 8U}, /* reserved */
+ {dscCfg->bitsPerComponent, 4U},
+ {dscCfg->linebufDepth, 4U},
+ {0U, 2U}, /* reserved */
+ {dscCfg->blockPredEnable, 1U},
+ {dscCfg->convertRgb, 1U},
+ {dscCfg->simple_422, 1U},
+ {dscCfg->vbrEnable, 1U},
+ {dscCfg->bitsPerPixel, 10U},
+ {dscCfg->picHeight, 16U},
+ {dscCfg->picWidth, 16U},
+ {dscCfg->sliceHeight, 16U},
+ {dscCfg->sliceWidth, 16U},
+ {dscCfg->chunkSize, 16U},
+ {0U, 6U}, /* reserved */
+ {dscCfg->initialXmitDelay, 10U},
+ {dscCfg->initialDecDelay, 16U},
+ {0U, 10U}, /* reserved */
+ {dscCfg->initialScaleValue, 6U},
+ {dscCfg->scaleIncrementInterval, 16U},
+ {0U, 4U}, /* reserved */
+ {dscCfg->scaleDecrementInterval, 12U},
+ };
+
+ for (i = 0U; i < 25U; i++) {
+ PutBits(parameter_array[i][0], parameter_array[i][1], buf, nbits);
+ }
+}
+
+void static dsc_write_pps_2(uint8_t *buf, const DP_DscConfigFull *dscCfg, uint32_t *nbits) {
+ uint32_t i;
+
+ uint32_t parameter_array[19][2] = {
+ {0U, 11U}, /* reserved */
+ {dscCfg->firstLineBpgOfs, 5U},
+ {dscCfg->nflBpgOffset, 16U},
+ {dscCfg->sliceBpgOffset, 16U},
+
+ {dscCfg->initialOffset, 16U},
+ {dscCfg->finalOffset, 16U},
+ {0U, 3U}, /* reserved */
+ {dscCfg->flatnessMinQp, 5U},
+ {0U, 3U}, /* reserved */
+ {dscCfg->flatnessMaxQp, 5U},
+
+ /* RC parameter set */
+ {dscCfg->rcModelSize, 16U},
+ {0U, 4U}, /* reserved */
+ {dscCfg->rcEdgeFactor, 4U},
+ {0U, 3U}, /* reserved */
+ {dscCfg->rcQuantIncrLimit0, 5U},
+ {0U, 3U}, /* reserved */
+ {dscCfg->rcQuantIncrLimit1, 5U},
+ {dscCfg->rcTgtOffsetHi, 4U},
+ {dscCfg->rcTgtOffsetLo, 4U}
+ };
+ for (i = 0U; i < 19U; i++) {
+ PutBits(parameter_array[i][0], parameter_array[i][1], buf, nbits);
+ }
+}
+
+void static dsc_write_pps_3(uint8_t *buf, const DP_DscConfigFull *dscCfg, uint32_t *nbits) {
+ uint32_t i;
+
+ for (i = 0U; i < 14U; ++i) {
+ PutBits(dscCfg->rcBufThresh[i] >> 6U, 8U, buf, nbits);
+ }
+ for (i = 0U; i < 15U; ++i) {
+ PutBits(dscCfg->rcRangeParameters[i].rangeMinQp, 5U, buf, nbits);
+ PutBits(dscCfg->rcRangeParameters[i].rangeMaxQp, 5U, buf, nbits);
+ PutBits((uint32_t) dscCfg->rcRangeParameters[i].rangeBpgOffset, 6U, buf, nbits);
+ }
+ /* / DSC 1.2 bits */
+ if (dscCfg->dscVersionMinor == 2U) {
+ uint32_t dsc_1_2_parameter_array[7][2] = {
+ {0U, 6U}, /* Reserved */
+ {dscCfg->native_420, 1U},
+ {dscCfg->native_422, 1U},
+ {0U, 3U}, /* Reserved (ignored) */
+ {dscCfg->secondLineBpgOfs, 5U},
+ {dscCfg->nslBpgOffset, 16U},
+ {dscCfg->secondLineOfsAdj, 16U}
+ };
+ for (i = 0U; i < 7U; ++i) {
+ PutBits(dsc_1_2_parameter_array[i][0], dsc_1_2_parameter_array[i][1], buf, nbits);
+ }
+ }
+}
+
+/************************************************************************
+ * \brief
+ * DscwritePps() - Construct picture parameter set (PPS)
+ *
+ * \param buf
+ * Pointer to PPS buffer
+ * \param dscCfg
+ * Configuration structure
+ *
+ ************************************************************************
+ */
+void DscWritePps(uint8_t *buf, const DP_DscConfigFull *dscCfg)
+{
+ uint32_t nbits = 0U;
+
+ dsc_write_pps_1(buf, dscCfg, &nbits);
+ dsc_write_pps_2(buf, dscCfg, &nbits);
+ dsc_write_pps_3(buf, dscCfg, &nbits);
+}
+
+/* parasoft-end-suppress METRICS-36-3 "A function should not be called from more than 5 different functions" */
+
diff --git a/packages/ti/drv/dss/src/csl/dp/src/dsc_utils.h b/packages/ti/drv/dss/src/csl/dp/src/dsc_utils.h
--- /dev/null
@@ -0,0 +1,94 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ *
+ * dsc_utils.h
+ *
+ ******************************************************************************
+ */
+/***************************************************************************
+* Copyright (c) 2013-2016, Broadcom Ltd.
+* All rights reserved.
+*
+* Statement regarding contribution of copyrighted materials to VESA:
+*
+* This code is owned by Broadcom Limited and is contributed to VESA
+* for inclusion and use in its VESA Display Stream Compression specification.
+* Accordingly, VESA is hereby granted a worldwide, perpetual, non-exclusive
+* license to revise, modify and create derivative works to this code and
+* VESA shall own all right, title and interest in and to any derivative
+* works authored by VESA.
+*
+* Terms and Conditions
+*
+* Without limiting the foregoing, you agree that your use
+* of this software program does not convey any rights to you in any of
+* Broadcom's patent and other intellectual property, and you
+* acknowledge that your use of this software may require that
+* you separately obtain patent or other intellectual property
+* rights from Broadcom or third parties.
+*
+* Except as expressly set forth in a separate written license agreement
+* between you and Broadcom, if applicable:
+*
+* 1. TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED
+* "AS IS" AND WITH ALL FAULTS AND BROADCOM MAKES NO PROMISES,
+* REPRESENTATIONS OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR
+* OTHERWISE, WITH RESPECT TO THE SOFTWARE. BROADCOM SPECIFICALLY
+* DISCLAIMS ANY AND ALL IMPLIED WARRANTIES OF TITLE, MERCHANTABILITY,
+* NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF VIRUSES,
+* ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
+* CORRESPONDENCE TO DESCRIPTION. YOU ASSUME THE ENTIRE RISK ARISING
+* OUT OF USE OR PERFORMANCE OF THE SOFTWARE.
+*
+* 2. TO THE MAXIMUM EXTENT PERMITTED BY LAW, IN NO EVENT SHALL
+* BROADCOM OR ITS LICENSORS BE LIABLE FOR (i) CONSEQUENTIAL, INCIDENTAL,
+* SPECIAL, INDIRECT, OR EXEMPLARY DAMAGES WHATSOEVER ARISING OUT OF OR
+* IN ANY WAY RELATING TO YOUR USE OF OR INABILITY TO USE THE SOFTWARE EVEN
+* IF BROADCOM HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES; OR (ii)
+* ANY AMOUNT IN EXCESS OF THE AMOUNT ACTUALLY PAID FOR THE SOFTWARE ITSELF
+* OR U.S. $1, WHICHEVER IS GREATER. THESE LIMITATIONS SHALL APPLY
+* NOTWITHSTANDING ANY FAILURE OF ESSENTIAL PURPOSE OF ANY LIMITED REMEDY.
+***************************************************************************/
+
+#ifndef DSC_UTILS_H
+#define DSC_UTILS_H
+
+#include "dp_if.h"
+#include "dp_priv.h"
+#include "custom_types.h"
+
+#define OFFSET_FRACTIONAL_BITS 11U
+#define DP_SDP_HEADER_SIZE 4U
+
+uint32_t DscCalcParameters(DP_DscConfigFull *dscCfg);
+uint32_t DscCopyCfgToFull(const DP_DscConfig *dscCfg, DP_DscConfigFull *dscCfgFull);
+void DscCopyFromFull(DP_DscConfig *dscCfg, const DP_DscConfigFull *dscCfgFull);
+void DscWritePps(uint8_t *buf, const DP_DscConfigFull *dscCfg);
+#endif
diff --git a/packages/ti/drv/dss/src/csl/dp/src/mhdp_apb_regs.h b/packages/ti/drv/dss/src/csl/dp/src/mhdp_apb_regs.h
--- /dev/null
@@ -0,0 +1,472 @@
+/* parasoft-begin-suppress MISRA2012-RULE-1_1_a_c99-2 "C99 - limits, DRV-4754" parasoft-begin-suppress MISRA2012-RULE-1_1_a_c90-2 "C90 - limits, DRV-4754" */
+/* parasoft-begin-suppress item MISRA2012-DIR-4_8 "Consider hiding implementation of structure, DRV-3667" */
+
+/**********************************************************************
+* Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* 1. Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* 2. Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the distribution.
+* 3. Neither the name of the copyright holder nor the names of its
+* contributors may be used to endorse or promote products derived from
+* this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+* THIS FILE IS AUTOMATICALLY GENERATED, DO NOT EDIT
+*
+**********************************************************************/
+
+#ifndef REG_MHDP_APB_REGS_H_
+#define REG_MHDP_APB_REGS_H_
+
+#include <cps_drv.h>
+
+#include "mhdp_apb_regs_macros.h"
+
+typedef struct __attribute__((packed)) MHDP_ApbRegs_s {
+ struct {
+ volatile uint32_t APB_CTRL_p;
+ volatile uint32_t xt_int_ctrl_p;
+ volatile uint32_t MAILBOX_FULL_ADDR_p;
+ volatile uint32_t MAILBOX_EMPTY_ADDR_p;
+ volatile uint32_t mailbox0_wr_data_p;
+ volatile uint32_t mailbox0_rd_data_p;
+ volatile uint32_t KEEP_ALIVE_p;
+ volatile uint32_t VER_L_p;
+ volatile uint32_t VER_H_p;
+ volatile uint32_t VER_LIB_L_ADDR_p;
+ volatile uint32_t VER_LIB_H_ADDR_p;
+ volatile uint32_t SW_DEBUG_L_p;
+ volatile uint32_t SW_DEBUG_H_p;
+ volatile uint32_t MAILBOX_INT_MASK_p;
+ volatile uint32_t MAILBOX_INT_STATUS_p;
+ volatile uint32_t SW_CLK_L_p;
+ volatile uint32_t SW_CLK_H_p;
+ volatile uint32_t SW_EVENTS0_p;
+ volatile uint32_t SW_EVENTS1_p;
+ volatile uint32_t SW_EVENTS2_p;
+ volatile uint32_t SW_EVENTS3_p;
+ volatile char pad__0[0xCU];
+ volatile uint32_t XT_OCD_CTRL_p;
+ volatile uint32_t XT_OCD_CTRL_RO_p;
+ volatile char pad__1[0x4U];
+ volatile uint32_t APB_INT_MASK_p;
+ volatile uint32_t APB_INT_STATUS_p;
+ volatile char pad__2[0x2CU];
+ volatile uint32_t CDNS_DID_p;
+ volatile uint32_t CDNS_RID0_p;
+ volatile uint32_t CDNS_RID1_p;
+ volatile uint32_t CDNS_CFGS0_p;
+ volatile uint32_t CDNS_CFGS1_p;
+ volatile char pad__3[0x74CU];
+ volatile uint32_t SHIFT_PATTERN_IN_3_0_p;
+ volatile uint32_t SHIFT_PATTERN_IN_4_7_p;
+ volatile uint32_t SHIFT_PATTERN_IN9_8_p;
+ volatile uint32_t PRBS_CNTRL_p;
+ volatile uint32_t PRBS_ERR_INSERTION_p;
+ volatile uint32_t LANES_CONFIG_p;
+ volatile uint32_t PHY_DATA_SEL_p;
+ volatile uint32_t LANES_DEL_VAL_p;
+ volatile char pad__4[0xE4U];
+ volatile uint32_t source_dptx_car_p;
+ volatile uint32_t source_phy_car_p;
+ volatile char pad__5[0xCU];
+ volatile uint32_t source_pkt_car_p;
+ volatile uint32_t source_aif_car_p;
+ volatile uint32_t source_cipher_car_p;
+ volatile uint32_t source_crypto_car_p;
+ volatile uint32_t source_spdif_car_p;
+ volatile char pad__6[0xD4U];
+ struct {
+ volatile uint32_t CM_CTRL_p;
+ volatile uint32_t CM_I2S_CTRL_p;
+ volatile uint32_t CM_SPDIF_CTRL_p;
+ volatile uint32_t CM_VID_CTRL_p;
+ volatile uint32_t CM_LANE_CTRL_p;
+ volatile uint32_t I2S_NM_STABLE_p;
+ volatile uint32_t I2S_NCTS_STABLE_p;
+ volatile uint32_t SPDIF_NM_STABLE_p;
+ volatile uint32_t SPDIF_NCTS_STABLE_p;
+ volatile uint32_t NMVID_MEAS_STABLE_p;
+ volatile uint32_t CM_VID_MEAS_p;
+ volatile uint32_t CM_AUD_MEAS_p;
+ volatile uint32_t I2S_MEAS_p;
+ volatile uint32_t SPDIF_MEAS_p;
+ volatile uint32_t NMVID_MEAS_p;
+ volatile char pad__7[0x4U];
+ } mhdp_clock_meter[4];
+ struct {
+ volatile uint32_t BND_HSYNC2VSYNC_p;
+ volatile uint32_t HSYNC2VSYNC_F1_L1_p;
+ volatile uint32_t HSYNC2VSYNC_F2_L1_p;
+ volatile uint32_t HSYNC2VSYNC_STATUS_p;
+ volatile uint32_t HSYNC2VSYNC_POL_CTRL_p;
+ volatile uint32_t DSC_CTRL_p;
+ volatile char pad__8[0x8U];
+ } mhdp_vif_ctrl[4];
+ volatile char pad__9[0x1480U];
+ volatile uint32_t DP_TX_PHY_CONFIG_REG_p;
+ volatile uint32_t DP_TX_PHY_SW_RESET_p;
+ volatile uint32_t DP_TX_PHY_SCRAMBLER_SEED_p;
+ volatile uint32_t DP_TX_PHY_TRAINING_01_04_p;
+ volatile uint32_t DP_TX_PHY_TRAINING_05_08_p;
+ volatile uint32_t DP_TX_PHY_TRAINING_09_10_p;
+ volatile uint32_t DP_TX_PHY_SR_INTERVAL_p;
+ volatile uint32_t DP_TX_PHY_FEC_TEST_p;
+ volatile char pad__10[0xE0U];
+ volatile uint32_t HPD_IRQ_DET_MIN_TIMER_p;
+ volatile uint32_t HPD_IRQ_DET_MAX_TIMER_p;
+ volatile uint32_t HPD_UNPLGED_DET_MIN_TIMER_p;
+ volatile uint32_t HPD_STABLE_TIMER_p;
+ volatile uint32_t HPD_FILTER_TIMER_p;
+ volatile uint32_t HPD_DBNC_TIMER_p;
+ volatile char pad__11[0x4U];
+ volatile uint32_t HPD_EVENT_MASK_p;
+ volatile uint32_t HPD_EVENT_DET_p;
+ volatile char pad__12[0xDCU];
+ volatile uint32_t DP_FRAMER_GLOBAL_CONFIG_p;
+ volatile uint32_t DP_SW_RESET_p;
+ volatile uint32_t DP_FRAMER_TU_p;
+ volatile char pad__13[0xCU];
+ volatile uint32_t DP_FRAMER_BS_SR_INTRVL_p;
+ volatile char pad__14[0x3CU];
+ volatile uint32_t DP_MTPH_ECF_SLOTS_31_0_p;
+ volatile uint32_t DP_MTPH_ECF_SLOTS_63_32_p;
+ volatile uint32_t DP_MTPH_LVP_SYMBOL_p;
+ volatile uint32_t DP_MTPH_CONTROL_p;
+ volatile char pad__15[0x4U];
+ volatile uint32_t DP_MTPH_STATUS_p;
+ volatile char pad__16[0x90U];
+ volatile uint32_t DPTX_LANE_EN_p;
+ volatile uint32_t DPTX_ENHNCD_p;
+ volatile uint32_t DPTX_INT_MASK_p;
+ volatile uint32_t DPTX_INT_STATUS_p;
+ volatile uint32_t DPTX_FEC_CTRL_p;
+ volatile uint32_t DPTX_FEC_STATUS_p;
+ volatile char pad__17[0xE8U];
+ volatile uint32_t HDCP_DP_STATUS_p;
+ volatile uint32_t HDCP_DP_CONFIG_p;
+ volatile uint32_t HDCP_DP_SW_RST_p;
+ volatile uint32_t HDCP_DP_FIFO_STATUS_p;
+ volatile char pad__18[0x3F0U];
+ volatile uint32_t DP_AUX_HOST_CONTROL_p;
+ volatile uint32_t DP_AUX_INTERRUPT_SOURCE_p;
+ volatile uint32_t DP_AUX_INTERRUPT_MASK_p;
+ volatile uint32_t DP_AUX_SWAP_INVERSION_CONTROL_p;
+ volatile uint32_t DP_AUX_SEND_NACK_TRANSACTION_p;
+ volatile uint32_t DP_AUX_CLEAR_RX_p;
+ volatile uint32_t DP_AUX_CLEAR_TX_p;
+ volatile uint32_t DP_AUX_TIMER_STOP_p;
+ volatile uint32_t DP_AUX_TIMER_CLEAR_p;
+ volatile uint32_t DP_AUX_RESET_SW_p;
+ volatile uint32_t DP_AUX_DIVIDE_2M_p;
+ volatile uint32_t DP_AUX_TX_PREACHARGE_LENGTH_p;
+ volatile uint32_t DP_AUX_FREQUENCY_1M_MAX_p;
+ volatile uint32_t DP_AUX_FREQUENCY_1M_MIN_p;
+ volatile uint32_t DP_AUX_RX_PRE_MIN_p;
+ volatile uint32_t DP_AUX_RX_PRE_MAX_p;
+ volatile uint32_t DP_AUX_TIMER_PRESET_p;
+ volatile uint32_t DP_AUX_NACK_FORMAT_p;
+ volatile uint32_t DP_AUX_TX_DATA_p;
+ volatile uint32_t DP_AUX_RX_DATA_p;
+ volatile uint32_t DP_AUX_TX_STATUS_p;
+ volatile uint32_t DP_AUX_RX_STATUS_p;
+ volatile uint32_t DP_AUX_RX_CYCLE_COUNTER_p;
+ volatile uint32_t DP_AUX_MAIN_STATES_p;
+ volatile uint32_t DP_AUX_MAIN_TIMER_p;
+ volatile uint32_t DP_AUX_AFE_OUT_p;
+ volatile char pad__19[0x798U];
+ struct {
+ volatile uint32_t MSA_HORIZONTAL_0_p;
+ volatile uint32_t MSA_HORIZONTAL_1_p;
+ volatile uint32_t MSA_VERTICAL_0_p;
+ volatile uint32_t MSA_VERTICAL_1_p;
+ volatile uint32_t MSA_MISC_p;
+ volatile uint32_t STREAM_CONFIG_p;
+ volatile uint32_t AUDIO_PACK_STATUS_p;
+ volatile uint32_t VIF_STATUS_p;
+ volatile uint32_t PCK_STUFF_STATUS_0_p;
+ volatile uint32_t PCK_STUFF_STATUS_1_p;
+ volatile uint32_t INFO_PACK_STATUS_p;
+ volatile uint32_t STREAM_CONFIG_2_p;
+ volatile uint32_t DP_HORIZONTAL_p;
+ volatile uint32_t DP_VERTICAL_0_p;
+ volatile uint32_t DP_VERTICAL_1_p;
+ volatile uint32_t DP_BLOCK_SDP_p;
+ volatile char pad__20[0x4U];
+ volatile uint32_t DP_MST_SLOT_ALLOCATE_p;
+ volatile uint32_t RATE_GOVERNING_CTRL_p;
+ volatile uint32_t DP_FRAMER_PXL_REPR_p;
+ volatile uint32_t DP_FRAMER_SP_p;
+ volatile uint32_t AUDIO_PACK_CONTROL_p;
+ volatile char pad__21[0xCU];
+ volatile uint32_t LINE_THRESH_p;
+ volatile uint32_t DP_VB_ID_p;
+ volatile uint32_t DP_FIELDSEQ_3D_p;
+ volatile char pad__22[0x8U];
+ volatile uint32_t DP_FRONT_BACK_PORCH_p;
+ volatile uint32_t DP_BYTE_COUNT_p;
+ } mhdp_dptx_stream[4];
+ volatile char pad__23[0xE00U];
+ volatile uint32_t CRYPTO_HDCP_REVISION_p;
+ volatile uint32_t HDCP_CRYPTO_CONFIG_p;
+ volatile uint32_t CRYPTO_INTERRUPT_SOURCE_p;
+ volatile uint32_t CRYPTO_INTERRUPT_MASK_p;
+ volatile char pad__24[0x8U];
+ volatile uint32_t CRYPTO22_CONFIG_p;
+ volatile uint32_t CRYPTO22_STATUS_p;
+ volatile char pad__25[0x1CU];
+ volatile uint32_t SHA_256_DATA_IN_p;
+ volatile char pad__26[0x10U];
+ volatile uint32_t SHA_256_DATA_OUT_0_p;
+ volatile uint32_t SHA_256_DATA_OUT_1_p;
+ volatile uint32_t SHA_256_DATA_OUT_2_p;
+ volatile uint32_t SHA_256_DATA_OUT_3_p;
+ volatile uint32_t SHA_256_DATA_OUT_4_p;
+ volatile uint32_t SHA_256_DATA_OUT_5_p;
+ volatile uint32_t SHA_256_DATA_OUT_6_p;
+ volatile uint32_t SHA_256_DATA_OUT_7_p;
+ volatile uint32_t AES_32_KEY_0_p;
+ volatile uint32_t AES_32_KEY_1_p;
+ volatile uint32_t AES_32_KEY_2_p;
+ volatile uint32_t AES_32_KEY_3_p;
+ volatile uint32_t AES_32_DATA_IN_p;
+ volatile uint32_t AES_32_DATA_OUT_0_p;
+ volatile uint32_t AES_32_DATA_OUT_1_p;
+ volatile uint32_t AES_32_DATA_OUT_2_p;
+ volatile uint32_t AES_32_DATA_OUT_3_p;
+ volatile char pad__27[0xCU];
+ volatile uint32_t CRYPTO14_CONFIG_p;
+ volatile uint32_t CRYPTO14_STATUS_p;
+ volatile uint32_t CRYPTO14_PRNM_OUT_p;
+ volatile uint32_t CRYPTO14_KM_0_p;
+ volatile uint32_t CRYPTO14_KM_1_p;
+ volatile uint32_t CRYPTO14_AN_0_p;
+ volatile uint32_t CRYPTO14_AN_1_p;
+ volatile uint32_t CRYPTO14_YOUR_KSV_0_p;
+ volatile uint32_t CRYPTO14_YOUR_KSV_1_p;
+ volatile uint32_t CRYPTO14_MI_0_p;
+ volatile uint32_t CRYPTO14_MI_1_p;
+ volatile uint32_t CRYPTO14_TI_0_p;
+ volatile uint32_t CRYPTO14_KI_0_p;
+ volatile uint32_t CRYPTO14_KI_1_p;
+ volatile uint32_t CRYPTO14_BLOCKS_NUM_p;
+ volatile uint32_t CRYPTO14_KEY_MEM_DATA_0_p;
+ volatile uint32_t CRYPTO14_KEY_MEM_DATA_1_p;
+ volatile uint32_t CRYPTO14_SHA1_MSG_DATA_p;
+ volatile uint32_t CRYPTO14_SHA1_V_VALUE_0_p;
+ volatile uint32_t CRYPTO14_SHA1_V_VALUE_1_p;
+ volatile uint32_t CRYPTO14_SHA1_V_VALUE_2_p;
+ volatile uint32_t CRYPTO14_SHA1_V_VALUE_3_p;
+ volatile uint32_t CRYPTO14_SHA1_V_VALUE_4_p;
+ volatile char pad__28[0xBF04U];
+ volatile uint32_t IRAM_REG_p[16384];
+ volatile uint32_t DRAM_REG_p[16384];
+ struct {
+ volatile uint32_t AUDIO_SRC_CNTL_p;
+ volatile uint32_t AUDIO_SRC_CNFG_p;
+ volatile uint32_t COM_CH_STTS_BITS_p;
+ volatile uint32_t STTS_BIT_CH01_p;
+ volatile uint32_t STTS_BIT_CH23_p;
+ volatile uint32_t STTS_BIT_CH45_p;
+ volatile uint32_t STTS_BIT_CH67_p;
+ volatile uint32_t STTS_BIT_CH89_p;
+ volatile uint32_t STTS_BIT_CH1011_p;
+ volatile uint32_t STTS_BIT_CH1213_p;
+ volatile uint32_t STTS_BIT_CH1415_p;
+ volatile uint32_t STTS_BIT_CH1617_p;
+ volatile uint32_t STTS_BIT_CH1819_p;
+ volatile uint32_t STTS_BIT_CH2021_p;
+ volatile uint32_t STTS_BIT_CH2223_p;
+ volatile uint32_t STTS_BIT_CH2425_p;
+ volatile uint32_t STTS_BIT_CH2627_p;
+ volatile uint32_t STTS_BIT_CH2829_p;
+ volatile uint32_t STTS_BIT_CH3031_p;
+ volatile uint32_t SPDIF_CTRL_ADDR_p;
+ volatile uint32_t SPDIF_CH1_CS_3100_ADDR_p;
+ volatile uint32_t SPDIF_CH1_CS_6332_ADDR_p;
+ volatile uint32_t SPDIF_CH1_CS_9564_ADDR_p;
+ volatile uint32_t SPDIF_CH1_CS_12796_ADDR_p;
+ volatile uint32_t SPDIF_CH1_CS_159128_ADDR_p;
+ volatile uint32_t SPDIF_CH1_CS_191160_ADDR_p;
+ volatile uint32_t SPDIF_CH2_CS_3100_ADDR_p;
+ volatile uint32_t SPDIF_CH2_CS_6332_ADDR_p;
+ volatile uint32_t SPDIF_CH2_CS_9564_ADDR_p;
+ volatile uint32_t SPDIF_CH2_CS_12796_ADDR_p;
+ volatile uint32_t SPDIF_CH2_CS_159128_ADDR_p;
+ volatile uint32_t SPDIF_CH2_CS_191160_ADDR_p;
+ volatile uint32_t SMPL2PKT_CNTL_p;
+ volatile uint32_t SMPL2PKT_CNFG_p;
+ volatile uint32_t FIFO_CNTL_p;
+ volatile uint32_t FIFO_STTS_p;
+ volatile uint32_t SUB_PCKT_THRSH_p;
+ volatile char pad__29[0x6CU];
+ } mhdp_audio_decoder[4];
+ volatile char pad__30[0x400U];
+ struct {
+ volatile uint32_t SOURCE_PIF_WR_ADDR_p;
+ volatile uint32_t SOURCE_PIF_WR_REQ_p;
+ volatile uint32_t SOURCE_PIF_RD_ADDR_p;
+ volatile uint32_t SOURCE_PIF_RD_REQ_p;
+ volatile uint32_t SOURCE_PIF_DATA_WR_p;
+ volatile uint32_t SOURCE_PIF_DATA_RD_p;
+ volatile uint32_t SOURCE_PIF_FIFO1_FLUSH_p;
+ volatile uint32_t SOURCE_PIF_FIFO2_FLUSH_p;
+ volatile uint32_t SOURCE_PIF_STATUS_p;
+ volatile uint32_t SOURCE_PIF_INTERRUPT_SOURCE_p;
+ volatile uint32_t SOURCE_PIF_INTERRUPT_MASK_p;
+ volatile uint32_t SOURCE_PIF_PKT_ALLOC_REG_p;
+ volatile uint32_t SOURCE_PIF_PKT_ALLOC_WR_EN_p;
+ volatile uint32_t SOURCE_PIF_SW_RESET_p;
+ volatile uint32_t SOURCE_PIF_PPS_HEADER_p;
+ volatile uint32_t SOURCE_PIF_PPS_p;
+ } mhdp_sdp_control[4];
+ volatile char pad__31[0x100U];
+ volatile uint32_t AUX_CONFIG_p;
+ volatile uint32_t AUX_CTRL_p;
+ volatile uint32_t AUX_ATBSEL_p;
+ volatile uint32_t AUX_TESTMODE_CTL_p;
+ volatile uint32_t AUX_TESTMODE_ST_p;
+ volatile char pad__32[0xCU];
+ volatile uint32_t PHY_RESET_p;
+ volatile uint32_t PMA_PLLCLK_EN_p;
+ volatile uint32_t PMA_PLLCLK_EN_ACK_p;
+ volatile uint32_t PMA_POWER_STATE_REQ_p;
+ volatile uint32_t PMA_POWER_STATE_ACK_p;
+ volatile uint32_t PMA_CMN_READY_p;
+ volatile uint32_t PMA_TX_VMARGIN_p;
+ volatile uint32_t PMA_TX_DEEMPH_p;
+ volatile char pad__33[0x20U];
+ volatile uint32_t asf_ips_ctrl;
+ volatile char pad__34[0x9CU];
+ volatile uint32_t asf_int_status;
+ volatile uint32_t asf_int_raw_status;
+ volatile uint32_t asf_int_mask;
+ volatile uint32_t asf_int_test;
+ volatile uint32_t asf_fatal_nonfatal_select;
+ volatile char pad__35[0xCU];
+ volatile uint32_t asf_sram_corr_fault_status;
+ volatile uint32_t asf_sram_uncorr_fault_status;
+ volatile uint32_t asf_sram_fault_status;
+ volatile char pad__36[0x4U];
+ volatile uint32_t asf_trans_to_ctrl;
+ volatile uint32_t asf_trans_to_fault_mask;
+ volatile uint32_t asf_trans_to_fault_status;
+ volatile char pad__37[0x4U];
+ volatile uint32_t asf_protocol_fault_mask;
+ volatile uint32_t asf_protocol_fault_status;
+ volatile char pad__38[0xB8U];
+ volatile uint32_t COM_MAIN_CONF_p;
+ volatile char pad__39[0x11CU];
+ volatile uint32_t ENC0_MAIN_CONF_p;
+ volatile uint32_t ENC0_PICTURE_SIZE_p;
+ volatile uint32_t ENC0_SLICE_SIZE_p;
+ volatile uint32_t ENC0_MISC_SIZE_p;
+ volatile uint32_t ENC0_HRD_DELAYS_p;
+ volatile uint32_t ENC0_RC_SCALE_p;
+ volatile uint32_t ENC0_RC_SCALE_INC_DEC_p;
+ volatile uint32_t ENC0_RC_OFFSETS_1_p;
+ volatile uint32_t ENC0_RC_OFFSETS_2_p;
+ volatile uint32_t ENC0_RC_OFFSETS_3_p;
+ volatile uint32_t ENC0_FLATNESS_DETECTION_p;
+ volatile uint32_t ENC0_RC_MODEL_SIZE_p;
+ volatile uint32_t ENC0_RC_CONFIG_p;
+ volatile uint32_t ENC0_RC_BUF_THRESH_0_p;
+ volatile uint32_t ENC0_RC_BUF_THRESH_1_p;
+ volatile uint32_t ENC0_RC_BUF_THRESH_2_p;
+ volatile uint32_t ENC0_RC_BUF_THRESH_3_p;
+ volatile uint32_t ENC0_RC_MIN_QP_0_p;
+ volatile uint32_t ENC0_RC_MIN_QP_1_p;
+ volatile uint32_t ENC0_RC_MIN_QP_2_p;
+ volatile uint32_t ENC0_RC_MAX_QP_0_p;
+ volatile uint32_t ENC0_RC_MAX_QP_1_p;
+ volatile uint32_t ENC0_RC_MAX_QP_2_p;
+ volatile uint32_t ENC0_RC_RANGE_BPG_OFFSETS_0_p;
+ volatile uint32_t ENC0_RC_RANGE_BPG_OFFSETS_1_p;
+ volatile uint32_t ENC0_RC_RANGE_BPG_OFFSETS_2_p;
+ volatile uint32_t ENC0_DPI_CTRL_OUT_DELAY_p;
+ volatile char pad__40[0x34U];
+ volatile uint32_t ENC0_GENERAL_STATUS_p;
+ volatile uint32_t ENC0_HSLICE_STATUS_p;
+ volatile uint32_t ENC0_OUT_STATUS_p;
+ volatile uint32_t ENC0_INT_STAT_p;
+ volatile uint32_t ENC0_INT_CLR_p;
+ volatile uint32_t ENC0_INT_MASK_p;
+ volatile uint32_t ENC0_INT_TEST_p;
+ volatile char pad__41[0x44U];
+ volatile uint32_t ENC1_MAIN_CONF_p;
+ volatile uint32_t ENC1_PICTURE_SIZE_p;
+ volatile uint32_t ENC1_SLICE_SIZE_p;
+ volatile uint32_t ENC1_MISC_SIZE_p;
+ volatile uint32_t ENC1_HRD_DELAYS_p;
+ volatile uint32_t ENC1_RC_SCALE_p;
+ volatile uint32_t ENC1_RC_SCALE_INC_DEC_p;
+ volatile uint32_t ENC1_RC_OFFSETS_1_p;
+ volatile uint32_t ENC1_RC_OFFSETS_2_p;
+ volatile uint32_t ENC1_RC_OFFSETS_3_p;
+ volatile uint32_t ENC1_FLATNESS_DETECTION_p;
+ volatile uint32_t ENC1_RC_MODEL_SIZE_p;
+ volatile uint32_t ENC1_RC_CONFIG_p;
+ volatile uint32_t ENC1_RC_BUF_THRESH_0_p;
+ volatile uint32_t ENC1_RC_BUF_THRESH_1_p;
+ volatile uint32_t ENC1_RC_BUF_THRESH_2_p;
+ volatile uint32_t ENC1_RC_BUF_THRESH_3_p;
+ volatile uint32_t ENC1_RC_MIN_QP_0_p;
+ volatile uint32_t ENC1_RC_MIN_QP_1_p;
+ volatile uint32_t ENC1_RC_MIN_QP_2_p;
+ volatile uint32_t ENC1_RC_MAX_QP_0_p;
+ volatile uint32_t ENC1_RC_MAX_QP_1_p;
+ volatile uint32_t ENC1_RC_MAX_QP_2_p;
+ volatile uint32_t ENC1_RC_RANGE_BPG_OFFSETS_0_p;
+ volatile uint32_t ENC1_RC_RANGE_BPG_OFFSETS_1_p;
+ volatile uint32_t ENC1_RC_RANGE_BPG_OFFSETS_2_p;
+ volatile uint32_t ENC1_DPI_CTRL_OUT_DELAY_p;
+ volatile char pad__42[0x34U];
+ volatile uint32_t ENC1_GENERAL_STATUS_p;
+ volatile uint32_t ENC1_HSLICE_STATUS_p;
+ volatile uint32_t ENC1_OUT_STATUS_p;
+ volatile uint32_t ENC1_INT_STAT_p;
+ volatile uint32_t ENC1_INT_CLR_p;
+ volatile uint32_t ENC1_INT_MASK_p;
+ volatile uint32_t ENC1_INT_TEST_p;
+ volatile char pad__43[0x24U];
+ volatile uint32_t ENC_ASF_INT_STAT_p;
+ volatile uint32_t ENC_ASF_INT_MASK_p;
+ volatile uint32_t ENC_ASF_INT_CLR_p;
+ volatile uint32_t ENC_ASF_INT_TEST_p;
+ volatile char pad__44[0x10U];
+ volatile uint32_t ENC0_ASF_SRAM_CORR_p;
+ volatile uint32_t ENC0_ASF_SRAM_UNCORR_p;
+ volatile uint32_t ENC1_ASF_SRAM_CORR_p;
+ volatile uint32_t ENC1_ASF_SRAM_UNCORR_p;
+ volatile uint32_t ENC0_ASF_CSR_CHK_TEST_p;
+ volatile uint32_t ENC1_ASF_CSR_CHK_TEST_p;
+ volatile uint32_t ENC0_ASF_SELF_CHK_TEST_p;
+ volatile uint32_t ENC1_ASF_SELF_CHK_TEST_p;
+ volatile uint32_t ENC0_ASF_OUT_CHK_TEST_p;
+ volatile uint32_t ENC1_ASF_OUT_CHK_TEST_p;
+ } mhdp_apb_regs;
+} MHDP_ApbRegs;
+
+#endif /* REG_MHDP_APB_REGS_H_ */
+
+/* parasoft-end-suppress MISRA2012-RULE-1_1_a_c99-2 "C99 - limits, DRV-4754" */
+/* parasoft-end-suppress MISRA2012-RULE-1_1_a_c90-2 "C90 - limits, DRV-4754" */
+/* parasoft-end-suppress MISRA2012-DIR-4_8 "Consider hiding implementation of structure, DRV-3667" */
+
diff --git a/packages/ti/drv/dss/src/csl/dp/src/mhdp_apb_regs_macros.h b/packages/ti/drv/dss/src/csl/dp/src/mhdp_apb_regs_macros.h
--- /dev/null
@@ -0,0 +1,7036 @@
+/* parasoft-begin-suppress MISRA2012-RULE-1_1_b_c99-2 "C99 - limits, DRV-4754" parasoft-begin-suppress MISRA2012-RULE-1_1_b_c90-2 "C90 - limits, DRV-4754" */
+/* parasoft-begin-suppress MISRA2012-RULE-5_4_b_c90-2 "C90 - similar names, DRV-4756" */
+/* parasoft-begin-suppress MISRA2012-RULE-5_4_b_c99-2 "C99 - similar names, DRV-4756" */
+
+/**********************************************************************
+* Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* 1. Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* 2. Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the distribution.
+* 3. Neither the name of the copyright holder nor the names of its
+* contributors may be used to endorse or promote products derived from
+* this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+* THIS FILE IS AUTOMATICALLY GENERATED, DO NOT EDIT
+*
+**********************************************************************/
+
+#ifndef REG_MHDP_APB_REGS_MACROS_H_
+#define REG_MHDP_APB_REGS_MACROS_H_
+
+#define MHDP__MHDP_APB_REGS__APB_CTRL_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__APB_CTRL_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__APB_CTRL_P__APB_XT_RESET_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__APB_CTRL_P__APB_XT_RESET_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__APB_CTRL_P__APB_XT_RESET_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__APB_CTRL_P__APB_XT_RESET_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__APB_CTRL_P__APB_XT_RESET_WOSET 0U
+#define MHDP__MHDP_APB_REGS__APB_CTRL_P__APB_DRAM_PATH_MASK 0x00000002U
+#define MHDP__MHDP_APB_REGS__APB_CTRL_P__APB_DRAM_PATH_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__APB_CTRL_P__APB_DRAM_PATH_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__APB_CTRL_P__APB_DRAM_PATH_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__APB_CTRL_P__APB_DRAM_PATH_WOSET 0U
+#define MHDP__MHDP_APB_REGS__APB_CTRL_P__APB_IRAM_PATH_MASK 0x00000004U
+#define MHDP__MHDP_APB_REGS__APB_CTRL_P__APB_IRAM_PATH_SHIFT 2U
+#define MHDP__MHDP_APB_REGS__APB_CTRL_P__APB_IRAM_PATH_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__APB_CTRL_P__APB_IRAM_PATH_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__APB_CTRL_P__APB_IRAM_PATH_WOSET 0U
+#define MHDP__MHDP_APB_REGS__APB_CTRL_P__APB_XT_RUNSTALL_MASK 0x00000008U
+#define MHDP__MHDP_APB_REGS__APB_CTRL_P__APB_XT_RUNSTALL_SHIFT 3U
+#define MHDP__MHDP_APB_REGS__APB_CTRL_P__APB_XT_RUNSTALL_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__APB_CTRL_P__APB_XT_RUNSTALL_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__APB_CTRL_P__APB_XT_RUNSTALL_WOSET 0U
+#define MHDP__MHDP_APB_REGS__APB_CTRL_P__RESERVED_MASK 0xFFFFFFF0U
+#define MHDP__MHDP_APB_REGS__APB_CTRL_P__RESERVED_SHIFT 4U
+#define MHDP__MHDP_APB_REGS__APB_CTRL_P__RESERVED_WIDTH 28U
+
+#define MHDP__MHDP_APB_REGS__XT_INT_CTRL_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__XT_INT_CTRL_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__XT_INT_CTRL_P__XT_INT_POLARITY_MASK 0x00000003U
+#define MHDP__MHDP_APB_REGS__XT_INT_CTRL_P__XT_INT_POLARITY_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__XT_INT_CTRL_P__XT_INT_POLARITY_WIDTH 2U
+#define MHDP__MHDP_APB_REGS__XT_INT_CTRL_P__RESERVED_MASK 0xFFFFFFFCU
+#define MHDP__MHDP_APB_REGS__XT_INT_CTRL_P__RESERVED_SHIFT 2U
+#define MHDP__MHDP_APB_REGS__XT_INT_CTRL_P__RESERVED_WIDTH 30U
+
+#define MHDP__MHDP_APB_REGS__MAILBOX_FULL_ADDR_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MAILBOX_FULL_ADDR_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MAILBOX_FULL_ADDR_P__MAILBOX_FULL_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__MAILBOX_FULL_ADDR_P__MAILBOX_FULL_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MAILBOX_FULL_ADDR_P__MAILBOX_FULL_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MAILBOX_FULL_ADDR_P__MAILBOX_FULL_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MAILBOX_FULL_ADDR_P__MAILBOX_FULL_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MAILBOX_FULL_ADDR_P__RESERVED_MASK 0xFFFFFFFEU
+#define MHDP__MHDP_APB_REGS__MAILBOX_FULL_ADDR_P__RESERVED_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__MAILBOX_FULL_ADDR_P__RESERVED_WIDTH 31U
+
+#define MHDP__MHDP_APB_REGS__MAILBOX_EMPTY_ADDR_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MAILBOX_EMPTY_ADDR_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MAILBOX_EMPTY_ADDR_P__MAILBOX_EMPTY_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__MAILBOX_EMPTY_ADDR_P__MAILBOX_EMPTY_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MAILBOX_EMPTY_ADDR_P__MAILBOX_EMPTY_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MAILBOX_EMPTY_ADDR_P__MAILBOX_EMPTY_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MAILBOX_EMPTY_ADDR_P__MAILBOX_EMPTY_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MAILBOX_EMPTY_ADDR_P__RESERVED_MASK 0xFFFFFFFEU
+#define MHDP__MHDP_APB_REGS__MAILBOX_EMPTY_ADDR_P__RESERVED_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__MAILBOX_EMPTY_ADDR_P__RESERVED_WIDTH 31U
+
+#define MHDP__MHDP_APB_REGS__MAILBOX0_WR_DATA_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MAILBOX0_WR_DATA_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MAILBOX0_WR_DATA_P__MAILBOX0_WR_DATA_MASK 0x000000FFU
+#define MHDP__MHDP_APB_REGS__MAILBOX0_WR_DATA_P__MAILBOX0_WR_DATA_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MAILBOX0_WR_DATA_P__MAILBOX0_WR_DATA_WIDTH 8U
+#define MHDP__MHDP_APB_REGS__MAILBOX0_WR_DATA_P__RESERVED_0_MASK 0xFFFFFF00U
+#define MHDP__MHDP_APB_REGS__MAILBOX0_WR_DATA_P__RESERVED_0_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__MAILBOX0_WR_DATA_P__RESERVED_0_WIDTH 24U
+
+#define MHDP__MHDP_APB_REGS__MAILBOX0_RD_DATA_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MAILBOX0_RD_DATA_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MAILBOX0_RD_DATA_P__MAILBOX0_RD_DATA_MASK 0x000000FFU
+#define MHDP__MHDP_APB_REGS__MAILBOX0_RD_DATA_P__MAILBOX0_RD_DATA_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MAILBOX0_RD_DATA_P__MAILBOX0_RD_DATA_WIDTH 8U
+#define MHDP__MHDP_APB_REGS__MAILBOX0_RD_DATA_P__RESERVED_0_MASK 0xFFFFFF00U
+#define MHDP__MHDP_APB_REGS__MAILBOX0_RD_DATA_P__RESERVED_0_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__MAILBOX0_RD_DATA_P__RESERVED_0_WIDTH 24U
+
+#define MHDP__MHDP_APB_REGS__KEEP_ALIVE_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__KEEP_ALIVE_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__KEEP_ALIVE_P__KEEP_ALIVE_CNT_MASK 0x000000FFU
+#define MHDP__MHDP_APB_REGS__KEEP_ALIVE_P__KEEP_ALIVE_CNT_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__KEEP_ALIVE_P__KEEP_ALIVE_CNT_WIDTH 8U
+#define MHDP__MHDP_APB_REGS__KEEP_ALIVE_P__RESERVED_0_MASK 0xFFFFFF00U
+#define MHDP__MHDP_APB_REGS__KEEP_ALIVE_P__RESERVED_0_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__KEEP_ALIVE_P__RESERVED_0_WIDTH 24U
+
+#define MHDP__MHDP_APB_REGS__VER_L_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__VER_L_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__VER_L_P__VER_LSB_MASK 0x000000FFU
+#define MHDP__MHDP_APB_REGS__VER_L_P__VER_LSB_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__VER_L_P__VER_LSB_WIDTH 8U
+#define MHDP__MHDP_APB_REGS__VER_L_P__RESERVED_0_MASK 0xFFFFFF00U
+#define MHDP__MHDP_APB_REGS__VER_L_P__RESERVED_0_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__VER_L_P__RESERVED_0_WIDTH 24U
+
+#define MHDP__MHDP_APB_REGS__VER_H_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__VER_H_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__VER_H_P__VER_MSB_MASK 0x000000FFU
+#define MHDP__MHDP_APB_REGS__VER_H_P__VER_MSB_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__VER_H_P__VER_MSB_WIDTH 8U
+#define MHDP__MHDP_APB_REGS__VER_H_P__RESERVED_0_MASK 0xFFFFFF00U
+#define MHDP__MHDP_APB_REGS__VER_H_P__RESERVED_0_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__VER_H_P__RESERVED_0_WIDTH 24U
+
+#define MHDP__MHDP_APB_REGS__VER_LIB_L_ADDR_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__VER_LIB_L_ADDR_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__VER_LIB_L_ADDR_P__SW_LIB_VER_L_MASK 0x000000FFU
+#define MHDP__MHDP_APB_REGS__VER_LIB_L_ADDR_P__SW_LIB_VER_L_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__VER_LIB_L_ADDR_P__SW_LIB_VER_L_WIDTH 8U
+#define MHDP__MHDP_APB_REGS__VER_LIB_L_ADDR_P__RESERVED_0_MASK 0xFFFFFF00U
+#define MHDP__MHDP_APB_REGS__VER_LIB_L_ADDR_P__RESERVED_0_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__VER_LIB_L_ADDR_P__RESERVED_0_WIDTH 24U
+
+#define MHDP__MHDP_APB_REGS__VER_LIB_H_ADDR_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__VER_LIB_H_ADDR_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__VER_LIB_H_ADDR_P__SW_LIB_VER_H_MASK 0x000000FFU
+#define MHDP__MHDP_APB_REGS__VER_LIB_H_ADDR_P__SW_LIB_VER_H_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__VER_LIB_H_ADDR_P__SW_LIB_VER_H_WIDTH 8U
+#define MHDP__MHDP_APB_REGS__VER_LIB_H_ADDR_P__RESERVED_0_MASK 0xFFFFFF00U
+#define MHDP__MHDP_APB_REGS__VER_LIB_H_ADDR_P__RESERVED_0_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__VER_LIB_H_ADDR_P__RESERVED_0_WIDTH 24U
+
+#define MHDP__MHDP_APB_REGS__SW_DEBUG_L_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__SW_DEBUG_L_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__SW_DEBUG_L_P__SW_DEBUG_7_0_MASK 0x000000FFU
+#define MHDP__MHDP_APB_REGS__SW_DEBUG_L_P__SW_DEBUG_7_0_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__SW_DEBUG_L_P__SW_DEBUG_7_0_WIDTH 8U
+#define MHDP__MHDP_APB_REGS__SW_DEBUG_L_P__RESERVED_0_MASK 0xFFFFFF00U
+#define MHDP__MHDP_APB_REGS__SW_DEBUG_L_P__RESERVED_0_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__SW_DEBUG_L_P__RESERVED_0_WIDTH 24U
+
+#define MHDP__MHDP_APB_REGS__SW_DEBUG_H_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__SW_DEBUG_H_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__SW_DEBUG_H_P__SW_DEBUG_15_8_MASK 0x000000FFU
+#define MHDP__MHDP_APB_REGS__SW_DEBUG_H_P__SW_DEBUG_15_8_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__SW_DEBUG_H_P__SW_DEBUG_15_8_WIDTH 8U
+#define MHDP__MHDP_APB_REGS__SW_DEBUG_H_P__RESERVED_0_MASK 0xFFFFFF00U
+#define MHDP__MHDP_APB_REGS__SW_DEBUG_H_P__RESERVED_0_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__SW_DEBUG_H_P__RESERVED_0_WIDTH 24U
+
+#define MHDP__MHDP_APB_REGS__MAILBOX_INT_MASK_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MAILBOX_INT_MASK_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MAILBOX_INT_MASK_P__MAILBOX_EMPTY_INT_MASK_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__MAILBOX_INT_MASK_P__MAILBOX_EMPTY_INT_MASK_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MAILBOX_INT_MASK_P__MAILBOX_EMPTY_INT_MASK_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MAILBOX_INT_MASK_P__MAILBOX_EMPTY_INT_MASK_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MAILBOX_INT_MASK_P__MAILBOX_EMPTY_INT_MASK_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MAILBOX_INT_MASK_P__MAILBOX_FULL_INT_MASK_MASK 0x00000002U
+#define MHDP__MHDP_APB_REGS__MAILBOX_INT_MASK_P__MAILBOX_FULL_INT_MASK_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__MAILBOX_INT_MASK_P__MAILBOX_FULL_INT_MASK_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MAILBOX_INT_MASK_P__MAILBOX_FULL_INT_MASK_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MAILBOX_INT_MASK_P__MAILBOX_FULL_INT_MASK_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MAILBOX_INT_MASK_P__RESERVED_0_MASK 0xFFFFFFFCU
+#define MHDP__MHDP_APB_REGS__MAILBOX_INT_MASK_P__RESERVED_0_SHIFT 2U
+#define MHDP__MHDP_APB_REGS__MAILBOX_INT_MASK_P__RESERVED_0_WIDTH 30U
+
+#define MHDP__MHDP_APB_REGS__MAILBOX_INT_STATUS_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MAILBOX_INT_STATUS_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MAILBOX_INT_STATUS_P__MAILBOX_EMPTY_INT_STATUS_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__MAILBOX_INT_STATUS_P__MAILBOX_EMPTY_INT_STATUS_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MAILBOX_INT_STATUS_P__MAILBOX_EMPTY_INT_STATUS_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MAILBOX_INT_STATUS_P__MAILBOX_EMPTY_INT_STATUS_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MAILBOX_INT_STATUS_P__MAILBOX_EMPTY_INT_STATUS_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MAILBOX_INT_STATUS_P__MAILBOX_FULL_INT_STATUS_MASK 0x00000002U
+#define MHDP__MHDP_APB_REGS__MAILBOX_INT_STATUS_P__MAILBOX_FULL_INT_STATUS_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__MAILBOX_INT_STATUS_P__MAILBOX_FULL_INT_STATUS_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MAILBOX_INT_STATUS_P__MAILBOX_FULL_INT_STATUS_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MAILBOX_INT_STATUS_P__MAILBOX_FULL_INT_STATUS_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MAILBOX_INT_STATUS_P__RESERVED_0_MASK 0xFFFFFFFCU
+#define MHDP__MHDP_APB_REGS__MAILBOX_INT_STATUS_P__RESERVED_0_SHIFT 2U
+#define MHDP__MHDP_APB_REGS__MAILBOX_INT_STATUS_P__RESERVED_0_WIDTH 30U
+
+#define MHDP__MHDP_APB_REGS__SW_CLK_L_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__SW_CLK_L_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__SW_CLK_L_P__SW_CLOCK_VAL_L_MASK 0x000000FFU
+#define MHDP__MHDP_APB_REGS__SW_CLK_L_P__SW_CLOCK_VAL_L_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__SW_CLK_L_P__SW_CLOCK_VAL_L_WIDTH 8U
+#define MHDP__MHDP_APB_REGS__SW_CLK_L_P__RESERVED_0_MASK 0xFFFFFF00U
+#define MHDP__MHDP_APB_REGS__SW_CLK_L_P__RESERVED_0_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__SW_CLK_L_P__RESERVED_0_WIDTH 24U
+
+#define MHDP__MHDP_APB_REGS__SW_CLK_H_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__SW_CLK_H_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__SW_CLK_H_P__SW_CLOCK_VAL_H_MASK 0x000000FFU
+#define MHDP__MHDP_APB_REGS__SW_CLK_H_P__SW_CLOCK_VAL_H_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__SW_CLK_H_P__SW_CLOCK_VAL_H_WIDTH 8U
+#define MHDP__MHDP_APB_REGS__SW_CLK_H_P__RESERVED_0_MASK 0xFFFFFF00U
+#define MHDP__MHDP_APB_REGS__SW_CLK_H_P__RESERVED_0_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__SW_CLK_H_P__RESERVED_0_WIDTH 24U
+
+#define MHDP__MHDP_APB_REGS__SW_EVENTS0_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__SW_EVENTS0_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__SW_EVENTS0_P__SW_EVENTS7_0_MASK 0x000000FFU
+#define MHDP__MHDP_APB_REGS__SW_EVENTS0_P__SW_EVENTS7_0_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__SW_EVENTS0_P__SW_EVENTS7_0_WIDTH 8U
+#define MHDP__MHDP_APB_REGS__SW_EVENTS0_P__RESERVED_0_MASK 0xFFFFFF00U
+#define MHDP__MHDP_APB_REGS__SW_EVENTS0_P__RESERVED_0_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__SW_EVENTS0_P__RESERVED_0_WIDTH 24U
+
+#define MHDP__MHDP_APB_REGS__SW_EVENTS1_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__SW_EVENTS1_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__SW_EVENTS1_P__SW_EVENTS15_8_MASK 0x000000FFU
+#define MHDP__MHDP_APB_REGS__SW_EVENTS1_P__SW_EVENTS15_8_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__SW_EVENTS1_P__SW_EVENTS15_8_WIDTH 8U
+#define MHDP__MHDP_APB_REGS__SW_EVENTS1_P__RESERVED_0_MASK 0xFFFFFF00U
+#define MHDP__MHDP_APB_REGS__SW_EVENTS1_P__RESERVED_0_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__SW_EVENTS1_P__RESERVED_0_WIDTH 24U
+
+#define MHDP__MHDP_APB_REGS__SW_EVENTS2_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__SW_EVENTS2_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__SW_EVENTS2_P__SW_EVENTS23_16_MASK 0x000000FFU
+#define MHDP__MHDP_APB_REGS__SW_EVENTS2_P__SW_EVENTS23_16_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__SW_EVENTS2_P__SW_EVENTS23_16_WIDTH 8U
+#define MHDP__MHDP_APB_REGS__SW_EVENTS2_P__RESERVED_0_MASK 0xFFFFFF00U
+#define MHDP__MHDP_APB_REGS__SW_EVENTS2_P__RESERVED_0_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__SW_EVENTS2_P__RESERVED_0_WIDTH 24U
+
+#define MHDP__MHDP_APB_REGS__SW_EVENTS3_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__SW_EVENTS3_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__SW_EVENTS3_P__SW_EVENTS31_24_MASK 0x000000FFU
+#define MHDP__MHDP_APB_REGS__SW_EVENTS3_P__SW_EVENTS31_24_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__SW_EVENTS3_P__SW_EVENTS31_24_WIDTH 8U
+#define MHDP__MHDP_APB_REGS__SW_EVENTS3_P__RESERVED_0_MASK 0xFFFFFF00U
+#define MHDP__MHDP_APB_REGS__SW_EVENTS3_P__RESERVED_0_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__SW_EVENTS3_P__RESERVED_0_WIDTH 24U
+
+#define MHDP__MHDP_APB_REGS__XT_OCD_CTRL_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__XT_OCD_CTRL_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__XT_OCD_CTRL_P__XT_DRESET_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__XT_OCD_CTRL_P__XT_DRESET_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__XT_OCD_CTRL_P__XT_DRESET_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__XT_OCD_CTRL_P__XT_DRESET_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__XT_OCD_CTRL_P__XT_DRESET_WOSET 0U
+#define MHDP__MHDP_APB_REGS__XT_OCD_CTRL_P__XT_OCDHALTONRESET_MASK 0x00000002U
+#define MHDP__MHDP_APB_REGS__XT_OCD_CTRL_P__XT_OCDHALTONRESET_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__XT_OCD_CTRL_P__XT_OCDHALTONRESET_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__XT_OCD_CTRL_P__XT_OCDHALTONRESET_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__XT_OCD_CTRL_P__XT_OCDHALTONRESET_WOSET 0U
+#define MHDP__MHDP_APB_REGS__XT_OCD_CTRL_P__RESERVED_0_MASK 0xFFFFFFFCU
+#define MHDP__MHDP_APB_REGS__XT_OCD_CTRL_P__RESERVED_0_SHIFT 2U
+#define MHDP__MHDP_APB_REGS__XT_OCD_CTRL_P__RESERVED_0_WIDTH 30U
+
+#define MHDP__MHDP_APB_REGS__XT_OCD_CTRL_RO_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__XT_OCD_CTRL_RO_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__XT_OCD_CTRL_RO_P__XT_XOCDMODE_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__XT_OCD_CTRL_RO_P__XT_XOCDMODE_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__XT_OCD_CTRL_RO_P__XT_XOCDMODE_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__XT_OCD_CTRL_RO_P__XT_XOCDMODE_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__XT_OCD_CTRL_RO_P__XT_XOCDMODE_WOSET 0U
+#define MHDP__MHDP_APB_REGS__XT_OCD_CTRL_RO_P__RESERVED_0_MASK 0xFFFFFFFEU
+#define MHDP__MHDP_APB_REGS__XT_OCD_CTRL_RO_P__RESERVED_0_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__XT_OCD_CTRL_RO_P__RESERVED_0_WIDTH 31U
+
+#define MHDP__MHDP_APB_REGS__APB_INT_MASK_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__APB_INT_MASK_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__APB_INT_MASK_P__APB_MAILBOX_INTR_MASK_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__APB_INT_MASK_P__APB_MAILBOX_INTR_MASK_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__APB_INT_MASK_P__APB_MAILBOX_INTR_MASK_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__APB_INT_MASK_P__APB_MAILBOX_INTR_MASK_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__APB_INT_MASK_P__APB_MAILBOX_INTR_MASK_WOSET 0U
+#define MHDP__MHDP_APB_REGS__APB_INT_MASK_P__APB_SW_INTR_MASK_MASK 0x00000002U
+#define MHDP__MHDP_APB_REGS__APB_INT_MASK_P__APB_SW_INTR_MASK_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__APB_INT_MASK_P__APB_SW_INTR_MASK_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__APB_INT_MASK_P__APB_SW_INTR_MASK_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__APB_INT_MASK_P__APB_SW_INTR_MASK_WOSET 0U
+#define MHDP__MHDP_APB_REGS__APB_INT_MASK_P__APB_PIF_INTR_MASK_MASK 0x00000004U
+#define MHDP__MHDP_APB_REGS__APB_INT_MASK_P__APB_PIF_INTR_MASK_SHIFT 2U
+#define MHDP__MHDP_APB_REGS__APB_INT_MASK_P__APB_PIF_INTR_MASK_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__APB_INT_MASK_P__APB_PIF_INTR_MASK_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__APB_INT_MASK_P__APB_PIF_INTR_MASK_WOSET 0U
+#define MHDP__MHDP_APB_REGS__APB_INT_MASK_P__APB_CEC_INTR_MASK_MASK 0x00000008U
+#define MHDP__MHDP_APB_REGS__APB_INT_MASK_P__APB_CEC_INTR_MASK_SHIFT 3U
+#define MHDP__MHDP_APB_REGS__APB_INT_MASK_P__APB_CEC_INTR_MASK_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__APB_INT_MASK_P__APB_CEC_INTR_MASK_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__APB_INT_MASK_P__APB_CEC_INTR_MASK_WOSET 0U
+#define MHDP__MHDP_APB_REGS__APB_INT_MASK_P__RESERVED_0_MASK 0xFFFFFFF0U
+#define MHDP__MHDP_APB_REGS__APB_INT_MASK_P__RESERVED_0_SHIFT 4U
+#define MHDP__MHDP_APB_REGS__APB_INT_MASK_P__RESERVED_0_WIDTH 28U
+
+#define MHDP__MHDP_APB_REGS__APB_INT_STATUS_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__APB_INT_STATUS_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__APB_INT_STATUS_P__APB_MAILBOX_INTR_STATUS_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__APB_INT_STATUS_P__APB_MAILBOX_INTR_STATUS_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__APB_INT_STATUS_P__APB_MAILBOX_INTR_STATUS_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__APB_INT_STATUS_P__APB_MAILBOX_INTR_STATUS_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__APB_INT_STATUS_P__APB_MAILBOX_INTR_STATUS_WOSET 0U
+#define MHDP__MHDP_APB_REGS__APB_INT_STATUS_P__APB_SW_INTR_STATUS_MASK 0x00000002U
+#define MHDP__MHDP_APB_REGS__APB_INT_STATUS_P__APB_SW_INTR_STATUS_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__APB_INT_STATUS_P__APB_SW_INTR_STATUS_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__APB_INT_STATUS_P__APB_SW_INTR_STATUS_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__APB_INT_STATUS_P__APB_SW_INTR_STATUS_WOSET 0U
+#define MHDP__MHDP_APB_REGS__APB_INT_STATUS_P__APB_PIF_INTR_STATUS_MASK 0x00000004U
+#define MHDP__MHDP_APB_REGS__APB_INT_STATUS_P__APB_PIF_INTR_STATUS_SHIFT 2U
+#define MHDP__MHDP_APB_REGS__APB_INT_STATUS_P__APB_PIF_INTR_STATUS_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__APB_INT_STATUS_P__APB_PIF_INTR_STATUS_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__APB_INT_STATUS_P__APB_PIF_INTR_STATUS_WOSET 0U
+#define MHDP__MHDP_APB_REGS__APB_INT_STATUS_P__APB_CEC_INTR_STATUS_MASK 0x00000008U
+#define MHDP__MHDP_APB_REGS__APB_INT_STATUS_P__APB_CEC_INTR_STATUS_SHIFT 3U
+#define MHDP__MHDP_APB_REGS__APB_INT_STATUS_P__APB_CEC_INTR_STATUS_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__APB_INT_STATUS_P__APB_CEC_INTR_STATUS_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__APB_INT_STATUS_P__APB_CEC_INTR_STATUS_WOSET 0U
+#define MHDP__MHDP_APB_REGS__APB_INT_STATUS_P__RESERVED_0_MASK 0xFFFFFFF0U
+#define MHDP__MHDP_APB_REGS__APB_INT_STATUS_P__RESERVED_0_SHIFT 4U
+#define MHDP__MHDP_APB_REGS__APB_INT_STATUS_P__RESERVED_0_WIDTH 28U
+
+#define MHDP__MHDP_APB_REGS__CDNS_DID_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__CDNS_DID_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__CDNS_DID_P__IPVER_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__CDNS_DID_P__IPVER_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__CDNS_DID_P__IPVER_WIDTH 32U
+
+#define MHDP__MHDP_APB_REGS__CDNS_RID0_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__CDNS_RID0_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__CDNS_RID0_P__IP_VERSION_MASK 0x0000FFFFU
+#define MHDP__MHDP_APB_REGS__CDNS_RID0_P__IP_VERSION_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__CDNS_RID0_P__IP_VERSION_WIDTH 16U
+#define MHDP__MHDP_APB_REGS__CDNS_RID0_P__RESERVED_0_MASK 0xFFFF0000U
+#define MHDP__MHDP_APB_REGS__CDNS_RID0_P__RESERVED_0_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__CDNS_RID0_P__RESERVED_0_WIDTH 16U
+
+#define MHDP__MHDP_APB_REGS__CDNS_RID1_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__CDNS_RID1_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__CDNS_RID1_P__PHY_VERSION_MASK 0x0000FFFFU
+#define MHDP__MHDP_APB_REGS__CDNS_RID1_P__PHY_VERSION_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__CDNS_RID1_P__PHY_VERSION_WIDTH 16U
+#define MHDP__MHDP_APB_REGS__CDNS_RID1_P__AUX_VERSION_MASK 0xFFFF0000U
+#define MHDP__MHDP_APB_REGS__CDNS_RID1_P__AUX_VERSION_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__CDNS_RID1_P__AUX_VERSION_WIDTH 16U
+
+#define MHDP__MHDP_APB_REGS__CDNS_CFGS0_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__CDNS_CFGS0_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__CDNS_CFGS0_P__IP_NUMBER_CONFIGURATION_MASK 0x000000FFU
+#define MHDP__MHDP_APB_REGS__CDNS_CFGS0_P__IP_NUMBER_CONFIGURATION_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__CDNS_CFGS0_P__IP_NUMBER_CONFIGURATION_WIDTH 8U
+#define MHDP__MHDP_APB_REGS__CDNS_CFGS0_P__IP_NUMBER_FAMILY_MASK 0x0000FF00U
+#define MHDP__MHDP_APB_REGS__CDNS_CFGS0_P__IP_NUMBER_FAMILY_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__CDNS_CFGS0_P__IP_NUMBER_FAMILY_WIDTH 8U
+#define MHDP__MHDP_APB_REGS__CDNS_CFGS0_P__DSC_SUPPORT_MASK 0x00030000U
+#define MHDP__MHDP_APB_REGS__CDNS_CFGS0_P__DSC_SUPPORT_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__CDNS_CFGS0_P__DSC_SUPPORT_WIDTH 2U
+#define MHDP__MHDP_APB_REGS__CDNS_CFGS0_P__ASF_SUPPORT_MASK 0x000C0000U
+#define MHDP__MHDP_APB_REGS__CDNS_CFGS0_P__ASF_SUPPORT_SHIFT 18U
+#define MHDP__MHDP_APB_REGS__CDNS_CFGS0_P__ASF_SUPPORT_WIDTH 2U
+#define MHDP__MHDP_APB_REGS__CDNS_CFGS0_P__VIDEO_STREAM_NUMBER_MASK 0x00F00000U
+#define MHDP__MHDP_APB_REGS__CDNS_CFGS0_P__VIDEO_STREAM_NUMBER_SHIFT 20U
+#define MHDP__MHDP_APB_REGS__CDNS_CFGS0_P__VIDEO_STREAM_NUMBER_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__CDNS_CFGS0_P__AUDIO_STREAM_NUMBER_MASK 0x0F000000U
+#define MHDP__MHDP_APB_REGS__CDNS_CFGS0_P__AUDIO_STREAM_NUMBER_SHIFT 24U
+#define MHDP__MHDP_APB_REGS__CDNS_CFGS0_P__AUDIO_STREAM_NUMBER_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__CDNS_CFGS0_P__RESERVED_0_MASK 0xF0000000U
+#define MHDP__MHDP_APB_REGS__CDNS_CFGS0_P__RESERVED_0_SHIFT 28U
+#define MHDP__MHDP_APB_REGS__CDNS_CFGS0_P__RESERVED_0_WIDTH 4U
+
+#define MHDP__MHDP_APB_REGS__CDNS_CFGS1_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__CDNS_CFGS1_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__CDNS_CFGS1_P__PHY_NUMBER_MASK 0x0000FFFFU
+#define MHDP__MHDP_APB_REGS__CDNS_CFGS1_P__PHY_NUMBER_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__CDNS_CFGS1_P__PHY_NUMBER_WIDTH 16U
+#define MHDP__MHDP_APB_REGS__CDNS_CFGS1_P__AUX_NUMBER_MASK 0xFFFF0000U
+#define MHDP__MHDP_APB_REGS__CDNS_CFGS1_P__AUX_NUMBER_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__CDNS_CFGS1_P__AUX_NUMBER_WIDTH 16U
+
+#define MHDP__MHDP_APB_REGS__SHIFT_PATTERN_IN_3_0_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__SHIFT_PATTERN_IN_3_0_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__SHIFT_PATTERN_IN_3_0_P__SOURCE_PHY_SHIFT_PATTERN0_MASK 0x000000FFU
+#define MHDP__MHDP_APB_REGS__SHIFT_PATTERN_IN_3_0_P__SOURCE_PHY_SHIFT_PATTERN0_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__SHIFT_PATTERN_IN_3_0_P__SOURCE_PHY_SHIFT_PATTERN0_WIDTH 8U
+#define MHDP__MHDP_APB_REGS__SHIFT_PATTERN_IN_3_0_P__SOURCE_PHY_SHIFT_PATTERN1_MASK 0x0000FF00U
+#define MHDP__MHDP_APB_REGS__SHIFT_PATTERN_IN_3_0_P__SOURCE_PHY_SHIFT_PATTERN1_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__SHIFT_PATTERN_IN_3_0_P__SOURCE_PHY_SHIFT_PATTERN1_WIDTH 8U
+#define MHDP__MHDP_APB_REGS__SHIFT_PATTERN_IN_3_0_P__SOURCE_PHY_SHIFT_PATTERN2_MASK 0x00FF0000U
+#define MHDP__MHDP_APB_REGS__SHIFT_PATTERN_IN_3_0_P__SOURCE_PHY_SHIFT_PATTERN2_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__SHIFT_PATTERN_IN_3_0_P__SOURCE_PHY_SHIFT_PATTERN2_WIDTH 8U
+#define MHDP__MHDP_APB_REGS__SHIFT_PATTERN_IN_3_0_P__SOURCE_PHY_SHIFT_PATTERN3_MASK 0xFF000000U
+#define MHDP__MHDP_APB_REGS__SHIFT_PATTERN_IN_3_0_P__SOURCE_PHY_SHIFT_PATTERN3_SHIFT 24U
+#define MHDP__MHDP_APB_REGS__SHIFT_PATTERN_IN_3_0_P__SOURCE_PHY_SHIFT_PATTERN3_WIDTH 8U
+
+#define MHDP__MHDP_APB_REGS__SHIFT_PATTERN_IN_4_7_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__SHIFT_PATTERN_IN_4_7_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__SHIFT_PATTERN_IN_4_7_P__SOURCE_PHY_SHIFT_PATTERN4_MASK 0x000000FFU
+#define MHDP__MHDP_APB_REGS__SHIFT_PATTERN_IN_4_7_P__SOURCE_PHY_SHIFT_PATTERN4_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__SHIFT_PATTERN_IN_4_7_P__SOURCE_PHY_SHIFT_PATTERN4_WIDTH 8U
+#define MHDP__MHDP_APB_REGS__SHIFT_PATTERN_IN_4_7_P__SOURCE_PHY_SHIFT_PATTERN5_MASK 0x0000FF00U
+#define MHDP__MHDP_APB_REGS__SHIFT_PATTERN_IN_4_7_P__SOURCE_PHY_SHIFT_PATTERN5_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__SHIFT_PATTERN_IN_4_7_P__SOURCE_PHY_SHIFT_PATTERN5_WIDTH 8U
+#define MHDP__MHDP_APB_REGS__SHIFT_PATTERN_IN_4_7_P__SOURCE_PHY_SHIFT_PATTERN6_MASK 0x00FF0000U
+#define MHDP__MHDP_APB_REGS__SHIFT_PATTERN_IN_4_7_P__SOURCE_PHY_SHIFT_PATTERN6_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__SHIFT_PATTERN_IN_4_7_P__SOURCE_PHY_SHIFT_PATTERN6_WIDTH 8U
+#define MHDP__MHDP_APB_REGS__SHIFT_PATTERN_IN_4_7_P__SOURCE_PHY_SHIFT_PATTERN7_MASK 0xFF000000U
+#define MHDP__MHDP_APB_REGS__SHIFT_PATTERN_IN_4_7_P__SOURCE_PHY_SHIFT_PATTERN7_SHIFT 24U
+#define MHDP__MHDP_APB_REGS__SHIFT_PATTERN_IN_4_7_P__SOURCE_PHY_SHIFT_PATTERN7_WIDTH 8U
+
+#define MHDP__MHDP_APB_REGS__SHIFT_PATTERN_IN9_8_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__SHIFT_PATTERN_IN9_8_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__SHIFT_PATTERN_IN9_8_P__SOURCE_PHY_SHIFT_PATTERN8_MASK 0x000000FFU
+#define MHDP__MHDP_APB_REGS__SHIFT_PATTERN_IN9_8_P__SOURCE_PHY_SHIFT_PATTERN8_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__SHIFT_PATTERN_IN9_8_P__SOURCE_PHY_SHIFT_PATTERN8_WIDTH 8U
+#define MHDP__MHDP_APB_REGS__SHIFT_PATTERN_IN9_8_P__SOURCE_PHY_SHIFT_PATTERN9_MASK 0x0000FF00U
+#define MHDP__MHDP_APB_REGS__SHIFT_PATTERN_IN9_8_P__SOURCE_PHY_SHIFT_PATTERN9_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__SHIFT_PATTERN_IN9_8_P__SOURCE_PHY_SHIFT_PATTERN9_WIDTH 8U
+#define MHDP__MHDP_APB_REGS__SHIFT_PATTERN_IN9_8_P__SOURCE_PHY_SHIFT_LOAD_MASK 0x00010000U
+#define MHDP__MHDP_APB_REGS__SHIFT_PATTERN_IN9_8_P__SOURCE_PHY_SHIFT_LOAD_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__SHIFT_PATTERN_IN9_8_P__SOURCE_PHY_SHIFT_LOAD_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__SHIFT_PATTERN_IN9_8_P__SOURCE_PHY_SHIFT_LOAD_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__SHIFT_PATTERN_IN9_8_P__SOURCE_PHY_SHIFT_LOAD_WOSET 0U
+#define MHDP__MHDP_APB_REGS__SHIFT_PATTERN_IN9_8_P__SOURCE_PHY_SHIFT_EN_MASK 0x00020000U
+#define MHDP__MHDP_APB_REGS__SHIFT_PATTERN_IN9_8_P__SOURCE_PHY_SHIFT_EN_SHIFT 17U
+#define MHDP__MHDP_APB_REGS__SHIFT_PATTERN_IN9_8_P__SOURCE_PHY_SHIFT_EN_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__SHIFT_PATTERN_IN9_8_P__SOURCE_PHY_SHIFT_EN_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__SHIFT_PATTERN_IN9_8_P__SOURCE_PHY_SHIFT_EN_WOSET 0U
+#define MHDP__MHDP_APB_REGS__SHIFT_PATTERN_IN9_8_P__SOURCE_PHY_SHIFT_REPETITION_MASK 0x001C0000U
+#define MHDP__MHDP_APB_REGS__SHIFT_PATTERN_IN9_8_P__SOURCE_PHY_SHIFT_REPETITION_SHIFT 18U
+#define MHDP__MHDP_APB_REGS__SHIFT_PATTERN_IN9_8_P__SOURCE_PHY_SHIFT_REPETITION_WIDTH 3U
+#define MHDP__MHDP_APB_REGS__SHIFT_PATTERN_IN9_8_P__RESERVED_0_MASK 0xFFE00000U
+#define MHDP__MHDP_APB_REGS__SHIFT_PATTERN_IN9_8_P__RESERVED_0_SHIFT 21U
+#define MHDP__MHDP_APB_REGS__SHIFT_PATTERN_IN9_8_P__RESERVED_0_WIDTH 11U
+
+#define MHDP__MHDP_APB_REGS__PRBS_CNTRL_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__PRBS_CNTRL_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__PRBS_CNTRL_P__SOURCE_PHY_PRBS0_MODE_MASK 0x00000003U
+#define MHDP__MHDP_APB_REGS__PRBS_CNTRL_P__SOURCE_PHY_PRBS0_MODE_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__PRBS_CNTRL_P__SOURCE_PHY_PRBS0_MODE_WIDTH 2U
+#define MHDP__MHDP_APB_REGS__PRBS_CNTRL_P__SOURCE_PHY_PRBS0_OUT_MODE_MASK 0x0000000CU
+#define MHDP__MHDP_APB_REGS__PRBS_CNTRL_P__SOURCE_PHY_PRBS0_OUT_MODE_SHIFT 2U
+#define MHDP__MHDP_APB_REGS__PRBS_CNTRL_P__SOURCE_PHY_PRBS0_OUT_MODE_WIDTH 2U
+#define MHDP__MHDP_APB_REGS__PRBS_CNTRL_P__SOURCE_PHY_PRBS1_MODE_MASK 0x00000030U
+#define MHDP__MHDP_APB_REGS__PRBS_CNTRL_P__SOURCE_PHY_PRBS1_MODE_SHIFT 4U
+#define MHDP__MHDP_APB_REGS__PRBS_CNTRL_P__SOURCE_PHY_PRBS1_MODE_WIDTH 2U
+#define MHDP__MHDP_APB_REGS__PRBS_CNTRL_P__SOURCE_PHY_PRBS1_OUT_MODE_MASK 0x000000C0U
+#define MHDP__MHDP_APB_REGS__PRBS_CNTRL_P__SOURCE_PHY_PRBS1_OUT_MODE_SHIFT 6U
+#define MHDP__MHDP_APB_REGS__PRBS_CNTRL_P__SOURCE_PHY_PRBS1_OUT_MODE_WIDTH 2U
+#define MHDP__MHDP_APB_REGS__PRBS_CNTRL_P__SOURCE_PHY_PRBS2_MODE_MASK 0x00000300U
+#define MHDP__MHDP_APB_REGS__PRBS_CNTRL_P__SOURCE_PHY_PRBS2_MODE_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__PRBS_CNTRL_P__SOURCE_PHY_PRBS2_MODE_WIDTH 2U
+#define MHDP__MHDP_APB_REGS__PRBS_CNTRL_P__SOURCE_PHY_PRBS2_OUT_MODE_MASK 0x00000C00U
+#define MHDP__MHDP_APB_REGS__PRBS_CNTRL_P__SOURCE_PHY_PRBS2_OUT_MODE_SHIFT 10U
+#define MHDP__MHDP_APB_REGS__PRBS_CNTRL_P__SOURCE_PHY_PRBS2_OUT_MODE_WIDTH 2U
+#define MHDP__MHDP_APB_REGS__PRBS_CNTRL_P__SOURCE_PHY_PRBS3_MODE_MASK 0x00003000U
+#define MHDP__MHDP_APB_REGS__PRBS_CNTRL_P__SOURCE_PHY_PRBS3_MODE_SHIFT 12U
+#define MHDP__MHDP_APB_REGS__PRBS_CNTRL_P__SOURCE_PHY_PRBS3_MODE_WIDTH 2U
+#define MHDP__MHDP_APB_REGS__PRBS_CNTRL_P__SOURCE_PHY_PRBS3_OUT_MODE_MASK 0x0000C000U
+#define MHDP__MHDP_APB_REGS__PRBS_CNTRL_P__SOURCE_PHY_PRBS3_OUT_MODE_SHIFT 14U
+#define MHDP__MHDP_APB_REGS__PRBS_CNTRL_P__SOURCE_PHY_PRBS3_OUT_MODE_WIDTH 2U
+#define MHDP__MHDP_APB_REGS__PRBS_CNTRL_P__RESERVED_0_MASK 0xFFFF0000U
+#define MHDP__MHDP_APB_REGS__PRBS_CNTRL_P__RESERVED_0_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__PRBS_CNTRL_P__RESERVED_0_WIDTH 16U
+
+#define MHDP__MHDP_APB_REGS__PRBS_ERR_INSERTION_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__PRBS_ERR_INSERTION_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__PRBS_ERR_INSERTION_P__ADD_ERROR0_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__PRBS_ERR_INSERTION_P__ADD_ERROR0_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__PRBS_ERR_INSERTION_P__ADD_ERROR0_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__PRBS_ERR_INSERTION_P__ADD_ERROR0_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__PRBS_ERR_INSERTION_P__ADD_ERROR0_WOSET 0U
+#define MHDP__MHDP_APB_REGS__PRBS_ERR_INSERTION_P__NUMBER_OF_ERRORS0_MASK 0x0000003EU
+#define MHDP__MHDP_APB_REGS__PRBS_ERR_INSERTION_P__NUMBER_OF_ERRORS0_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__PRBS_ERR_INSERTION_P__NUMBER_OF_ERRORS0_WIDTH 5U
+#define MHDP__MHDP_APB_REGS__PRBS_ERR_INSERTION_P__ADD_ERROR1_MASK 0x00000040U
+#define MHDP__MHDP_APB_REGS__PRBS_ERR_INSERTION_P__ADD_ERROR1_SHIFT 6U
+#define MHDP__MHDP_APB_REGS__PRBS_ERR_INSERTION_P__ADD_ERROR1_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__PRBS_ERR_INSERTION_P__ADD_ERROR1_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__PRBS_ERR_INSERTION_P__ADD_ERROR1_WOSET 0U
+#define MHDP__MHDP_APB_REGS__PRBS_ERR_INSERTION_P__NUMBER_OF_ERRORS1_MASK 0x00000F80U
+#define MHDP__MHDP_APB_REGS__PRBS_ERR_INSERTION_P__NUMBER_OF_ERRORS1_SHIFT 7U
+#define MHDP__MHDP_APB_REGS__PRBS_ERR_INSERTION_P__NUMBER_OF_ERRORS1_WIDTH 5U
+#define MHDP__MHDP_APB_REGS__PRBS_ERR_INSERTION_P__ADD_ERROR2_MASK 0x00001000U
+#define MHDP__MHDP_APB_REGS__PRBS_ERR_INSERTION_P__ADD_ERROR2_SHIFT 12U
+#define MHDP__MHDP_APB_REGS__PRBS_ERR_INSERTION_P__ADD_ERROR2_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__PRBS_ERR_INSERTION_P__ADD_ERROR2_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__PRBS_ERR_INSERTION_P__ADD_ERROR2_WOSET 0U
+#define MHDP__MHDP_APB_REGS__PRBS_ERR_INSERTION_P__NUMBER_OF_ERRORS2_MASK 0x0003E000U
+#define MHDP__MHDP_APB_REGS__PRBS_ERR_INSERTION_P__NUMBER_OF_ERRORS2_SHIFT 13U
+#define MHDP__MHDP_APB_REGS__PRBS_ERR_INSERTION_P__NUMBER_OF_ERRORS2_WIDTH 5U
+#define MHDP__MHDP_APB_REGS__PRBS_ERR_INSERTION_P__ADD_ERROR3_MASK 0x00040000U
+#define MHDP__MHDP_APB_REGS__PRBS_ERR_INSERTION_P__ADD_ERROR3_SHIFT 18U
+#define MHDP__MHDP_APB_REGS__PRBS_ERR_INSERTION_P__ADD_ERROR3_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__PRBS_ERR_INSERTION_P__ADD_ERROR3_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__PRBS_ERR_INSERTION_P__ADD_ERROR3_WOSET 0U
+#define MHDP__MHDP_APB_REGS__PRBS_ERR_INSERTION_P__NUMBER_OF_ERRORS3_MASK 0x00F80000U
+#define MHDP__MHDP_APB_REGS__PRBS_ERR_INSERTION_P__NUMBER_OF_ERRORS3_SHIFT 19U
+#define MHDP__MHDP_APB_REGS__PRBS_ERR_INSERTION_P__NUMBER_OF_ERRORS3_WIDTH 5U
+#define MHDP__MHDP_APB_REGS__PRBS_ERR_INSERTION_P__RESERVED_0_MASK 0xFF000000U
+#define MHDP__MHDP_APB_REGS__PRBS_ERR_INSERTION_P__RESERVED_0_SHIFT 24U
+#define MHDP__MHDP_APB_REGS__PRBS_ERR_INSERTION_P__RESERVED_0_WIDTH 8U
+
+#define MHDP__MHDP_APB_REGS__LANES_CONFIG_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__LANES_CONFIG_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__LANES_CONFIG_P__SOURCE_PHY_LANE0_SWAP_MASK 0x00000003U
+#define MHDP__MHDP_APB_REGS__LANES_CONFIG_P__SOURCE_PHY_LANE0_SWAP_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__LANES_CONFIG_P__SOURCE_PHY_LANE0_SWAP_WIDTH 2U
+#define MHDP__MHDP_APB_REGS__LANES_CONFIG_P__SOURCE_PHY_LANE1_SWAP_MASK 0x0000000CU
+#define MHDP__MHDP_APB_REGS__LANES_CONFIG_P__SOURCE_PHY_LANE1_SWAP_SHIFT 2U
+#define MHDP__MHDP_APB_REGS__LANES_CONFIG_P__SOURCE_PHY_LANE1_SWAP_WIDTH 2U
+#define MHDP__MHDP_APB_REGS__LANES_CONFIG_P__SOURCE_PHY_LANE2_SWAP_MASK 0x00000030U
+#define MHDP__MHDP_APB_REGS__LANES_CONFIG_P__SOURCE_PHY_LANE2_SWAP_SHIFT 4U
+#define MHDP__MHDP_APB_REGS__LANES_CONFIG_P__SOURCE_PHY_LANE2_SWAP_WIDTH 2U
+#define MHDP__MHDP_APB_REGS__LANES_CONFIG_P__SOURCE_PHY_LANE3_SWAP_MASK 0x000000C0U
+#define MHDP__MHDP_APB_REGS__LANES_CONFIG_P__SOURCE_PHY_LANE3_SWAP_SHIFT 6U
+#define MHDP__MHDP_APB_REGS__LANES_CONFIG_P__SOURCE_PHY_LANE3_SWAP_WIDTH 2U
+#define MHDP__MHDP_APB_REGS__LANES_CONFIG_P__SOURCE_PHY_LANE0_LSB_MSB_MASK 0x00000100U
+#define MHDP__MHDP_APB_REGS__LANES_CONFIG_P__SOURCE_PHY_LANE0_LSB_MSB_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__LANES_CONFIG_P__SOURCE_PHY_LANE0_LSB_MSB_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__LANES_CONFIG_P__SOURCE_PHY_LANE0_LSB_MSB_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__LANES_CONFIG_P__SOURCE_PHY_LANE0_LSB_MSB_WOSET 0U
+#define MHDP__MHDP_APB_REGS__LANES_CONFIG_P__SOURCE_PHY_LANE1_LSB_MSB_MASK 0x00000200U
+#define MHDP__MHDP_APB_REGS__LANES_CONFIG_P__SOURCE_PHY_LANE1_LSB_MSB_SHIFT 9U
+#define MHDP__MHDP_APB_REGS__LANES_CONFIG_P__SOURCE_PHY_LANE1_LSB_MSB_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__LANES_CONFIG_P__SOURCE_PHY_LANE1_LSB_MSB_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__LANES_CONFIG_P__SOURCE_PHY_LANE1_LSB_MSB_WOSET 0U
+#define MHDP__MHDP_APB_REGS__LANES_CONFIG_P__SOURCE_PHY_LANE2_LSB_MSB_MASK 0x00000400U
+#define MHDP__MHDP_APB_REGS__LANES_CONFIG_P__SOURCE_PHY_LANE2_LSB_MSB_SHIFT 10U
+#define MHDP__MHDP_APB_REGS__LANES_CONFIG_P__SOURCE_PHY_LANE2_LSB_MSB_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__LANES_CONFIG_P__SOURCE_PHY_LANE2_LSB_MSB_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__LANES_CONFIG_P__SOURCE_PHY_LANE2_LSB_MSB_WOSET 0U
+#define MHDP__MHDP_APB_REGS__LANES_CONFIG_P__SOURCE_PHY_LANE3_LSB_MSB_MASK 0x00000800U
+#define MHDP__MHDP_APB_REGS__LANES_CONFIG_P__SOURCE_PHY_LANE3_LSB_MSB_SHIFT 11U
+#define MHDP__MHDP_APB_REGS__LANES_CONFIG_P__SOURCE_PHY_LANE3_LSB_MSB_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__LANES_CONFIG_P__SOURCE_PHY_LANE3_LSB_MSB_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__LANES_CONFIG_P__SOURCE_PHY_LANE3_LSB_MSB_WOSET 0U
+#define MHDP__MHDP_APB_REGS__LANES_CONFIG_P__SOURCE_PHY_AUX_SPARE_MASK 0x0000F000U
+#define MHDP__MHDP_APB_REGS__LANES_CONFIG_P__SOURCE_PHY_AUX_SPARE_SHIFT 12U
+#define MHDP__MHDP_APB_REGS__LANES_CONFIG_P__SOURCE_PHY_AUX_SPARE_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__LANES_CONFIG_P__SOURCE_PHY_LANE0_POLARITY_MASK 0x00010000U
+#define MHDP__MHDP_APB_REGS__LANES_CONFIG_P__SOURCE_PHY_LANE0_POLARITY_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__LANES_CONFIG_P__SOURCE_PHY_LANE0_POLARITY_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__LANES_CONFIG_P__SOURCE_PHY_LANE0_POLARITY_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__LANES_CONFIG_P__SOURCE_PHY_LANE0_POLARITY_WOSET 0U
+#define MHDP__MHDP_APB_REGS__LANES_CONFIG_P__SOURCE_PHY_LANE1_POLARITY_MASK 0x00020000U
+#define MHDP__MHDP_APB_REGS__LANES_CONFIG_P__SOURCE_PHY_LANE1_POLARITY_SHIFT 17U
+#define MHDP__MHDP_APB_REGS__LANES_CONFIG_P__SOURCE_PHY_LANE1_POLARITY_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__LANES_CONFIG_P__SOURCE_PHY_LANE1_POLARITY_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__LANES_CONFIG_P__SOURCE_PHY_LANE1_POLARITY_WOSET 0U
+#define MHDP__MHDP_APB_REGS__LANES_CONFIG_P__SOURCE_PHY_LANE2_POLARITY_MASK 0x00040000U
+#define MHDP__MHDP_APB_REGS__LANES_CONFIG_P__SOURCE_PHY_LANE2_POLARITY_SHIFT 18U
+#define MHDP__MHDP_APB_REGS__LANES_CONFIG_P__SOURCE_PHY_LANE2_POLARITY_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__LANES_CONFIG_P__SOURCE_PHY_LANE2_POLARITY_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__LANES_CONFIG_P__SOURCE_PHY_LANE2_POLARITY_WOSET 0U
+#define MHDP__MHDP_APB_REGS__LANES_CONFIG_P__SOURCE_PHY_LANE3_POLARITY_MASK 0x00080000U
+#define MHDP__MHDP_APB_REGS__LANES_CONFIG_P__SOURCE_PHY_LANE3_POLARITY_SHIFT 19U
+#define MHDP__MHDP_APB_REGS__LANES_CONFIG_P__SOURCE_PHY_LANE3_POLARITY_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__LANES_CONFIG_P__SOURCE_PHY_LANE3_POLARITY_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__LANES_CONFIG_P__SOURCE_PHY_LANE3_POLARITY_WOSET 0U
+#define MHDP__MHDP_APB_REGS__LANES_CONFIG_P__SOURCE_PHY_DATA_DEL_EN_MASK 0x00100000U
+#define MHDP__MHDP_APB_REGS__LANES_CONFIG_P__SOURCE_PHY_DATA_DEL_EN_SHIFT 20U
+#define MHDP__MHDP_APB_REGS__LANES_CONFIG_P__SOURCE_PHY_DATA_DEL_EN_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__LANES_CONFIG_P__SOURCE_PHY_DATA_DEL_EN_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__LANES_CONFIG_P__SOURCE_PHY_DATA_DEL_EN_WOSET 0U
+#define MHDP__MHDP_APB_REGS__LANES_CONFIG_P__SOURCE_PHY_COMB_BYPASS_MASK 0x00200000U
+#define MHDP__MHDP_APB_REGS__LANES_CONFIG_P__SOURCE_PHY_COMB_BYPASS_SHIFT 21U
+#define MHDP__MHDP_APB_REGS__LANES_CONFIG_P__SOURCE_PHY_COMB_BYPASS_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__LANES_CONFIG_P__SOURCE_PHY_COMB_BYPASS_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__LANES_CONFIG_P__SOURCE_PHY_COMB_BYPASS_WOSET 0U
+#define MHDP__MHDP_APB_REGS__LANES_CONFIG_P__SOURCE_PHY_20_10_MASK 0x00400000U
+#define MHDP__MHDP_APB_REGS__LANES_CONFIG_P__SOURCE_PHY_20_10_SHIFT 22U
+#define MHDP__MHDP_APB_REGS__LANES_CONFIG_P__SOURCE_PHY_20_10_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__LANES_CONFIG_P__SOURCE_PHY_20_10_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__LANES_CONFIG_P__SOURCE_PHY_20_10_WOSET 0U
+#define MHDP__MHDP_APB_REGS__LANES_CONFIG_P__RESERVED_0_MASK 0xFF800000U
+#define MHDP__MHDP_APB_REGS__LANES_CONFIG_P__RESERVED_0_SHIFT 23U
+#define MHDP__MHDP_APB_REGS__LANES_CONFIG_P__RESERVED_0_WIDTH 9U
+
+#define MHDP__MHDP_APB_REGS__PHY_DATA_SEL_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__PHY_DATA_SEL_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__PHY_DATA_SEL_P__SOURCE_PHY_DATA_SEL_MASK 0x00000007U
+#define MHDP__MHDP_APB_REGS__PHY_DATA_SEL_P__SOURCE_PHY_DATA_SEL_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__PHY_DATA_SEL_P__SOURCE_PHY_DATA_SEL_WIDTH 3U
+#define MHDP__MHDP_APB_REGS__PHY_DATA_SEL_P__SOURCE_PHY_MHDP_SEL_MASK 0x00000018U
+#define MHDP__MHDP_APB_REGS__PHY_DATA_SEL_P__SOURCE_PHY_MHDP_SEL_SHIFT 3U
+#define MHDP__MHDP_APB_REGS__PHY_DATA_SEL_P__SOURCE_PHY_MHDP_SEL_WIDTH 2U
+#define MHDP__MHDP_APB_REGS__PHY_DATA_SEL_P__RESERVED_0_MASK 0xFFFFFFE0U
+#define MHDP__MHDP_APB_REGS__PHY_DATA_SEL_P__RESERVED_0_SHIFT 5U
+#define MHDP__MHDP_APB_REGS__PHY_DATA_SEL_P__RESERVED_0_WIDTH 27U
+
+#define MHDP__MHDP_APB_REGS__LANES_DEL_VAL_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__LANES_DEL_VAL_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__LANES_DEL_VAL_P__SOURCE_PHY_LANE0_DEL_VAL_MASK 0x0000000FU
+#define MHDP__MHDP_APB_REGS__LANES_DEL_VAL_P__SOURCE_PHY_LANE0_DEL_VAL_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__LANES_DEL_VAL_P__SOURCE_PHY_LANE0_DEL_VAL_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__LANES_DEL_VAL_P__SOURCE_PHY_LANE1_DEL_VAL_MASK 0x000000F0U
+#define MHDP__MHDP_APB_REGS__LANES_DEL_VAL_P__SOURCE_PHY_LANE1_DEL_VAL_SHIFT 4U
+#define MHDP__MHDP_APB_REGS__LANES_DEL_VAL_P__SOURCE_PHY_LANE1_DEL_VAL_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__LANES_DEL_VAL_P__SOURCE_PHY_LANE2_DEL_VAL_MASK 0x00000F00U
+#define MHDP__MHDP_APB_REGS__LANES_DEL_VAL_P__SOURCE_PHY_LANE2_DEL_VAL_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__LANES_DEL_VAL_P__SOURCE_PHY_LANE2_DEL_VAL_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__LANES_DEL_VAL_P__SOURCE_PHY_LANE3_DEL_VAL_MASK 0x0000F000U
+#define MHDP__MHDP_APB_REGS__LANES_DEL_VAL_P__SOURCE_PHY_LANE3_DEL_VAL_SHIFT 12U
+#define MHDP__MHDP_APB_REGS__LANES_DEL_VAL_P__SOURCE_PHY_LANE3_DEL_VAL_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__LANES_DEL_VAL_P__RESERVED_0_MASK 0xFFFF0000U
+#define MHDP__MHDP_APB_REGS__LANES_DEL_VAL_P__RESERVED_0_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__LANES_DEL_VAL_P__RESERVED_0_WIDTH 16U
+
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__CFG_DPTX_VIF_CLK_EN_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__CFG_DPTX_VIF_CLK_EN_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__CFG_DPTX_VIF_CLK_EN_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__CFG_DPTX_VIF_CLK_EN_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__CFG_DPTX_VIF_CLK_EN_WOSET 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__CFG_DPTX_VIF_CLK_RSTN_EN_MASK 0x00000002U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__CFG_DPTX_VIF_CLK_RSTN_EN_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__CFG_DPTX_VIF_CLK_RSTN_EN_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__CFG_DPTX_VIF_CLK_RSTN_EN_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__CFG_DPTX_VIF_CLK_RSTN_EN_WOSET 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__DPTX_SYS_CLK_EN_MASK 0x00000004U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__DPTX_SYS_CLK_EN_SHIFT 2U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__DPTX_SYS_CLK_EN_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__DPTX_SYS_CLK_EN_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__DPTX_SYS_CLK_EN_WOSET 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__DPTX_SYS_CLK_RSTN_EN_MASK 0x00000008U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__DPTX_SYS_CLK_RSTN_EN_SHIFT 3U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__DPTX_SYS_CLK_RSTN_EN_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__DPTX_SYS_CLK_RSTN_EN_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__DPTX_SYS_CLK_RSTN_EN_WOSET 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__SOURCE_AUX_SYS_CLK_EN_MASK 0x00000010U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__SOURCE_AUX_SYS_CLK_EN_SHIFT 4U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__SOURCE_AUX_SYS_CLK_EN_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__SOURCE_AUX_SYS_CLK_EN_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__SOURCE_AUX_SYS_CLK_EN_WOSET 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__SOURCE_AUX_SYS_CLK_RSTN_EN_MASK 0x00000020U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__SOURCE_AUX_SYS_CLK_RSTN_EN_SHIFT 5U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__SOURCE_AUX_SYS_CLK_RSTN_EN_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__SOURCE_AUX_SYS_CLK_RSTN_EN_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__SOURCE_AUX_SYS_CLK_RSTN_EN_WOSET 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__DPTX_PHY_CHAR_CLK_EN_MASK 0x00000040U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__DPTX_PHY_CHAR_CLK_EN_SHIFT 6U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__DPTX_PHY_CHAR_CLK_EN_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__DPTX_PHY_CHAR_CLK_EN_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__DPTX_PHY_CHAR_CLK_EN_WOSET 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__DPTX_PHY_CHAR_RSTN_EN_MASK 0x00000080U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__DPTX_PHY_CHAR_RSTN_EN_SHIFT 7U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__DPTX_PHY_CHAR_RSTN_EN_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__DPTX_PHY_CHAR_RSTN_EN_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__DPTX_PHY_CHAR_RSTN_EN_WOSET 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__DPTX_PHY_DATA_CLK_EN_MASK 0x00000100U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__DPTX_PHY_DATA_CLK_EN_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__DPTX_PHY_DATA_CLK_EN_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__DPTX_PHY_DATA_CLK_EN_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__DPTX_PHY_DATA_CLK_EN_WOSET 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__DPTX_PHY_DATA_RSTN_EN_MASK 0x00000200U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__DPTX_PHY_DATA_RSTN_EN_SHIFT 9U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__DPTX_PHY_DATA_RSTN_EN_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__DPTX_PHY_DATA_RSTN_EN_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__DPTX_PHY_DATA_RSTN_EN_WOSET 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__DPTX_FRMR_DATA_CLK_EN_MASK 0x00000400U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__DPTX_FRMR_DATA_CLK_EN_SHIFT 10U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__DPTX_FRMR_DATA_CLK_EN_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__DPTX_FRMR_DATA_CLK_EN_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__DPTX_FRMR_DATA_CLK_EN_WOSET 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__DPTX_FRMR_DATA_CLK_RSTN_EN_MASK 0x00000800U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__DPTX_FRMR_DATA_CLK_RSTN_EN_SHIFT 11U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__DPTX_FRMR_DATA_CLK_RSTN_EN_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__DPTX_FRMR_DATA_CLK_RSTN_EN_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__DPTX_FRMR_DATA_CLK_RSTN_EN_WOSET 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__CFG_DPTX_VIF_CLK_EN1_MASK 0x00001000U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__CFG_DPTX_VIF_CLK_EN1_SHIFT 12U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__CFG_DPTX_VIF_CLK_EN1_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__CFG_DPTX_VIF_CLK_EN1_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__CFG_DPTX_VIF_CLK_EN1_WOSET 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__CFG_DPTX_VIF_CLK_RSTN_EN1_MASK 0x00002000U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__CFG_DPTX_VIF_CLK_RSTN_EN1_SHIFT 13U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__CFG_DPTX_VIF_CLK_RSTN_EN1_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__CFG_DPTX_VIF_CLK_RSTN_EN1_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__CFG_DPTX_VIF_CLK_RSTN_EN1_WOSET 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__CFG_DPTX_VIF_CLK_EN2_MASK 0x00004000U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__CFG_DPTX_VIF_CLK_EN2_SHIFT 14U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__CFG_DPTX_VIF_CLK_EN2_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__CFG_DPTX_VIF_CLK_EN2_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__CFG_DPTX_VIF_CLK_EN2_WOSET 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__CFG_DPTX_VIF_CLK_RSTN_EN2_MASK 0x00008000U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__CFG_DPTX_VIF_CLK_RSTN_EN2_SHIFT 15U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__CFG_DPTX_VIF_CLK_RSTN_EN2_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__CFG_DPTX_VIF_CLK_RSTN_EN2_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__CFG_DPTX_VIF_CLK_RSTN_EN2_WOSET 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__CFG_DPTX_VIF_CLK_EN3_MASK 0x00010000U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__CFG_DPTX_VIF_CLK_EN3_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__CFG_DPTX_VIF_CLK_EN3_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__CFG_DPTX_VIF_CLK_EN3_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__CFG_DPTX_VIF_CLK_EN3_WOSET 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__CFG_DPTX_VIF_CLK_RSTN_EN3_MASK 0x00020000U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__CFG_DPTX_VIF_CLK_RSTN_EN3_SHIFT 17U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__CFG_DPTX_VIF_CLK_RSTN_EN3_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__CFG_DPTX_VIF_CLK_RSTN_EN3_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__CFG_DPTX_VIF_CLK_RSTN_EN3_WOSET 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__CFG_DPTX_VIF_CLK_EN4_MASK 0x00040000U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__CFG_DPTX_VIF_CLK_EN4_SHIFT 18U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__CFG_DPTX_VIF_CLK_EN4_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__CFG_DPTX_VIF_CLK_EN4_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__CFG_DPTX_VIF_CLK_EN4_WOSET 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__CFG_DPTX_VIF_CLK_RSTN_EN4_MASK 0x00080000U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__CFG_DPTX_VIF_CLK_RSTN_EN4_SHIFT 19U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__CFG_DPTX_VIF_CLK_RSTN_EN4_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__CFG_DPTX_VIF_CLK_RSTN_EN4_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__CFG_DPTX_VIF_CLK_RSTN_EN4_WOSET 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__CFG_DPTX_VIF_CLK_EN5_MASK 0x00100000U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__CFG_DPTX_VIF_CLK_EN5_SHIFT 20U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__CFG_DPTX_VIF_CLK_EN5_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__CFG_DPTX_VIF_CLK_EN5_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__CFG_DPTX_VIF_CLK_EN5_WOSET 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__CFG_DPTX_VIF_CLK_RSTN_EN5_MASK 0x00200000U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__CFG_DPTX_VIF_CLK_RSTN_EN5_SHIFT 21U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__CFG_DPTX_VIF_CLK_RSTN_EN5_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__CFG_DPTX_VIF_CLK_RSTN_EN5_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__CFG_DPTX_VIF_CLK_RSTN_EN5_WOSET 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__CFG_DPTX_VIF_CLK_EN6_MASK 0x00400000U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__CFG_DPTX_VIF_CLK_EN6_SHIFT 22U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__CFG_DPTX_VIF_CLK_EN6_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__CFG_DPTX_VIF_CLK_EN6_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__CFG_DPTX_VIF_CLK_EN6_WOSET 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__CFG_DPTX_VIF_CLK_RSTN_EN6_MASK 0x00800000U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__CFG_DPTX_VIF_CLK_RSTN_EN6_SHIFT 23U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__CFG_DPTX_VIF_CLK_RSTN_EN6_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__CFG_DPTX_VIF_CLK_RSTN_EN6_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__CFG_DPTX_VIF_CLK_RSTN_EN6_WOSET 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__CFG_DPTX_VIF_CLK_EN7_MASK 0x01000000U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__CFG_DPTX_VIF_CLK_EN7_SHIFT 24U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__CFG_DPTX_VIF_CLK_EN7_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__CFG_DPTX_VIF_CLK_EN7_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__CFG_DPTX_VIF_CLK_EN7_WOSET 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__CFG_DPTX_VIF_CLK_RSTN_EN7_MASK 0x02000000U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__CFG_DPTX_VIF_CLK_RSTN_EN7_SHIFT 25U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__CFG_DPTX_VIF_CLK_RSTN_EN7_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__CFG_DPTX_VIF_CLK_RSTN_EN7_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__CFG_DPTX_VIF_CLK_RSTN_EN7_WOSET 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__RESERVED_0_MASK 0xFC000000U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__RESERVED_0_SHIFT 26U
+#define MHDP__MHDP_APB_REGS__SOURCE_DPTX_CAR_P__RESERVED_0_WIDTH 6U
+
+#define MHDP__MHDP_APB_REGS__SOURCE_PHY_CAR_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__SOURCE_PHY_CAR_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__SOURCE_PHY_CAR_P__SOURCE_PHY_DATA_OUT_CLK_EN_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__SOURCE_PHY_CAR_P__SOURCE_PHY_DATA_OUT_CLK_EN_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_PHY_CAR_P__SOURCE_PHY_DATA_OUT_CLK_EN_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__SOURCE_PHY_CAR_P__SOURCE_PHY_DATA_OUT_CLK_EN_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_PHY_CAR_P__SOURCE_PHY_DATA_OUT_CLK_EN_WOSET 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_PHY_CAR_P__SOURCE_PHY_DATA_OUT_CLK_RSTN_EN_MASK 0x00000002U
+#define MHDP__MHDP_APB_REGS__SOURCE_PHY_CAR_P__SOURCE_PHY_DATA_OUT_CLK_RSTN_EN_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__SOURCE_PHY_CAR_P__SOURCE_PHY_DATA_OUT_CLK_RSTN_EN_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__SOURCE_PHY_CAR_P__SOURCE_PHY_DATA_OUT_CLK_RSTN_EN_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_PHY_CAR_P__SOURCE_PHY_DATA_OUT_CLK_RSTN_EN_WOSET 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_PHY_CAR_P__SOURCE_PHY_CHAR_OUT_CLK_EN_MASK 0x00000004U
+#define MHDP__MHDP_APB_REGS__SOURCE_PHY_CAR_P__SOURCE_PHY_CHAR_OUT_CLK_EN_SHIFT 2U
+#define MHDP__MHDP_APB_REGS__SOURCE_PHY_CAR_P__SOURCE_PHY_CHAR_OUT_CLK_EN_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__SOURCE_PHY_CAR_P__SOURCE_PHY_CHAR_OUT_CLK_EN_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_PHY_CAR_P__SOURCE_PHY_CHAR_OUT_CLK_EN_WOSET 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_PHY_CAR_P__SOURCE_PHY_CHAR_OUT_CLK_RSTN_EN_MASK 0x00000008U
+#define MHDP__MHDP_APB_REGS__SOURCE_PHY_CAR_P__SOURCE_PHY_CHAR_OUT_CLK_RSTN_EN_SHIFT 3U
+#define MHDP__MHDP_APB_REGS__SOURCE_PHY_CAR_P__SOURCE_PHY_CHAR_OUT_CLK_RSTN_EN_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__SOURCE_PHY_CAR_P__SOURCE_PHY_CHAR_OUT_CLK_RSTN_EN_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_PHY_CAR_P__SOURCE_PHY_CHAR_OUT_CLK_RSTN_EN_WOSET 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_PHY_CAR_P__RESERVED_0_MASK 0xFFFFFFF0U
+#define MHDP__MHDP_APB_REGS__SOURCE_PHY_CAR_P__RESERVED_0_SHIFT 4U
+#define MHDP__MHDP_APB_REGS__SOURCE_PHY_CAR_P__RESERVED_0_WIDTH 28U
+
+#define MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P__SOURCE_PKT_DATA_CLK_EN_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P__SOURCE_PKT_DATA_CLK_EN_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P__SOURCE_PKT_DATA_CLK_EN_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P__SOURCE_PKT_DATA_CLK_EN_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P__SOURCE_PKT_DATA_CLK_EN_WOSET 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P__SOURCE_PKT_DATA_RSTN_EN_MASK 0x00000002U
+#define MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P__SOURCE_PKT_DATA_RSTN_EN_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P__SOURCE_PKT_DATA_RSTN_EN_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P__SOURCE_PKT_DATA_RSTN_EN_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P__SOURCE_PKT_DATA_RSTN_EN_WOSET 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P__SOURCE_PKT_SYS_CLK_EN_MASK 0x00000004U
+#define MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P__SOURCE_PKT_SYS_CLK_EN_SHIFT 2U
+#define MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P__SOURCE_PKT_SYS_CLK_EN_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P__SOURCE_PKT_SYS_CLK_EN_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P__SOURCE_PKT_SYS_CLK_EN_WOSET 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P__SOURCE_PKT_SYS_RSTN_EN_MASK 0x00000008U
+#define MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P__SOURCE_PKT_SYS_RSTN_EN_SHIFT 3U
+#define MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P__SOURCE_PKT_SYS_RSTN_EN_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P__SOURCE_PKT_SYS_RSTN_EN_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P__SOURCE_PKT_SYS_RSTN_EN_WOSET 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P__SOURCE_PKT_DATA_CLK_EN1_MASK 0x00000010U
+#define MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P__SOURCE_PKT_DATA_CLK_EN1_SHIFT 4U
+#define MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P__SOURCE_PKT_DATA_CLK_EN1_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P__SOURCE_PKT_DATA_CLK_EN1_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P__SOURCE_PKT_DATA_CLK_EN1_WOSET 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P__SOURCE_PKT_DATA_RSTN_EN1_MASK 0x00000020U
+#define MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P__SOURCE_PKT_DATA_RSTN_EN1_SHIFT 5U
+#define MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P__SOURCE_PKT_DATA_RSTN_EN1_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P__SOURCE_PKT_DATA_RSTN_EN1_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P__SOURCE_PKT_DATA_RSTN_EN1_WOSET 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P__SOURCE_PKT_DATA_CLK_EN2_MASK 0x00000040U
+#define MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P__SOURCE_PKT_DATA_CLK_EN2_SHIFT 6U
+#define MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P__SOURCE_PKT_DATA_CLK_EN2_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P__SOURCE_PKT_DATA_CLK_EN2_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P__SOURCE_PKT_DATA_CLK_EN2_WOSET 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P__SOURCE_PKT_DATA_RSTN_EN2_MASK 0x00000080U
+#define MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P__SOURCE_PKT_DATA_RSTN_EN2_SHIFT 7U
+#define MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P__SOURCE_PKT_DATA_RSTN_EN2_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P__SOURCE_PKT_DATA_RSTN_EN2_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P__SOURCE_PKT_DATA_RSTN_EN2_WOSET 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P__SOURCE_PKT_DATA_CLK_EN3_MASK 0x00000100U
+#define MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P__SOURCE_PKT_DATA_CLK_EN3_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P__SOURCE_PKT_DATA_CLK_EN3_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P__SOURCE_PKT_DATA_CLK_EN3_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P__SOURCE_PKT_DATA_CLK_EN3_WOSET 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P__SOURCE_PKT_DATA_RSTN_EN3_MASK 0x00000200U
+#define MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P__SOURCE_PKT_DATA_RSTN_EN3_SHIFT 9U
+#define MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P__SOURCE_PKT_DATA_RSTN_EN3_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P__SOURCE_PKT_DATA_RSTN_EN3_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P__SOURCE_PKT_DATA_RSTN_EN3_WOSET 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P__SOURCE_PKT_DATA_CLK_EN4_MASK 0x00000400U
+#define MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P__SOURCE_PKT_DATA_CLK_EN4_SHIFT 10U
+#define MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P__SOURCE_PKT_DATA_CLK_EN4_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P__SOURCE_PKT_DATA_CLK_EN4_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P__SOURCE_PKT_DATA_CLK_EN4_WOSET 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P__SOURCE_PKT_DATA_RSTN_EN4_MASK 0x00000800U
+#define MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P__SOURCE_PKT_DATA_RSTN_EN4_SHIFT 11U
+#define MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P__SOURCE_PKT_DATA_RSTN_EN4_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P__SOURCE_PKT_DATA_RSTN_EN4_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P__SOURCE_PKT_DATA_RSTN_EN4_WOSET 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P__SOURCE_PKT_DATA_CLK_EN5_MASK 0x00001000U
+#define MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P__SOURCE_PKT_DATA_CLK_EN5_SHIFT 12U
+#define MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P__SOURCE_PKT_DATA_CLK_EN5_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P__SOURCE_PKT_DATA_CLK_EN5_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P__SOURCE_PKT_DATA_CLK_EN5_WOSET 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P__SOURCE_PKT_DATA_RSTN_EN5_MASK 0x00002000U
+#define MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P__SOURCE_PKT_DATA_RSTN_EN5_SHIFT 13U
+#define MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P__SOURCE_PKT_DATA_RSTN_EN5_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P__SOURCE_PKT_DATA_RSTN_EN5_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P__SOURCE_PKT_DATA_RSTN_EN5_WOSET 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P__SOURCE_PKT_DATA_CLK_EN6_MASK 0x00004000U
+#define MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P__SOURCE_PKT_DATA_CLK_EN6_SHIFT 14U
+#define MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P__SOURCE_PKT_DATA_CLK_EN6_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P__SOURCE_PKT_DATA_CLK_EN6_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P__SOURCE_PKT_DATA_CLK_EN6_WOSET 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P__SOURCE_PKT_DATA_RSTN_EN6_MASK 0x00008000U
+#define MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P__SOURCE_PKT_DATA_RSTN_EN6_SHIFT 15U
+#define MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P__SOURCE_PKT_DATA_RSTN_EN6_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P__SOURCE_PKT_DATA_RSTN_EN6_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P__SOURCE_PKT_DATA_RSTN_EN6_WOSET 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P__SOURCE_PKT_DATA_CLK_EN7_MASK 0x00010000U
+#define MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P__SOURCE_PKT_DATA_CLK_EN7_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P__SOURCE_PKT_DATA_CLK_EN7_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P__SOURCE_PKT_DATA_CLK_EN7_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P__SOURCE_PKT_DATA_CLK_EN7_WOSET 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P__SOURCE_PKT_DATA_RSTN_EN7_MASK 0x00020000U
+#define MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P__SOURCE_PKT_DATA_RSTN_EN7_SHIFT 17U
+#define MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P__SOURCE_PKT_DATA_RSTN_EN7_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P__SOURCE_PKT_DATA_RSTN_EN7_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P__SOURCE_PKT_DATA_RSTN_EN7_WOSET 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P__RESERVED_0_MASK 0xFFFC0000U
+#define MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P__RESERVED_0_SHIFT 18U
+#define MHDP__MHDP_APB_REGS__SOURCE_PKT_CAR_P__RESERVED_0_WIDTH 14U
+
+#define MHDP__MHDP_APB_REGS__SOURCE_AIF_CAR_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__SOURCE_AIF_CAR_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__SOURCE_AIF_CAR_P__SOURCE_AIF_PKT_CLK_EN_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__SOURCE_AIF_CAR_P__SOURCE_AIF_PKT_CLK_EN_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_AIF_CAR_P__SOURCE_AIF_PKT_CLK_EN_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__SOURCE_AIF_CAR_P__SOURCE_AIF_PKT_CLK_EN_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_AIF_CAR_P__SOURCE_AIF_PKT_CLK_EN_WOSET 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_AIF_CAR_P__SOURCE_AIF_PKT_CLK_RSTN_EN_MASK 0x00000002U
+#define MHDP__MHDP_APB_REGS__SOURCE_AIF_CAR_P__SOURCE_AIF_PKT_CLK_RSTN_EN_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__SOURCE_AIF_CAR_P__SOURCE_AIF_PKT_CLK_RSTN_EN_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__SOURCE_AIF_CAR_P__SOURCE_AIF_PKT_CLK_RSTN_EN_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_AIF_CAR_P__SOURCE_AIF_PKT_CLK_RSTN_EN_WOSET 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_AIF_CAR_P__SOURCE_AIF_SYS_CLK_EN_MASK 0x00000004U
+#define MHDP__MHDP_APB_REGS__SOURCE_AIF_CAR_P__SOURCE_AIF_SYS_CLK_EN_SHIFT 2U
+#define MHDP__MHDP_APB_REGS__SOURCE_AIF_CAR_P__SOURCE_AIF_SYS_CLK_EN_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__SOURCE_AIF_CAR_P__SOURCE_AIF_SYS_CLK_EN_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_AIF_CAR_P__SOURCE_AIF_SYS_CLK_EN_WOSET 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_AIF_CAR_P__SOURCE_AIF_SYS_RSTN_EN_MASK 0x00000008U
+#define MHDP__MHDP_APB_REGS__SOURCE_AIF_CAR_P__SOURCE_AIF_SYS_RSTN_EN_SHIFT 3U
+#define MHDP__MHDP_APB_REGS__SOURCE_AIF_CAR_P__SOURCE_AIF_SYS_RSTN_EN_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__SOURCE_AIF_CAR_P__SOURCE_AIF_SYS_RSTN_EN_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_AIF_CAR_P__SOURCE_AIF_SYS_RSTN_EN_WOSET 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_AIF_CAR_P__SOURCE_AIF_PKT_CLK_EN1_MASK 0x00000010U
+#define MHDP__MHDP_APB_REGS__SOURCE_AIF_CAR_P__SOURCE_AIF_PKT_CLK_EN1_SHIFT 4U
+#define MHDP__MHDP_APB_REGS__SOURCE_AIF_CAR_P__SOURCE_AIF_PKT_CLK_EN1_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__SOURCE_AIF_CAR_P__SOURCE_AIF_PKT_CLK_EN1_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_AIF_CAR_P__SOURCE_AIF_PKT_CLK_EN1_WOSET 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_AIF_CAR_P__SOURCE_AIF_PKT_CLK_RSTN_EN1_MASK 0x00000020U
+#define MHDP__MHDP_APB_REGS__SOURCE_AIF_CAR_P__SOURCE_AIF_PKT_CLK_RSTN_EN1_SHIFT 5U
+#define MHDP__MHDP_APB_REGS__SOURCE_AIF_CAR_P__SOURCE_AIF_PKT_CLK_RSTN_EN1_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__SOURCE_AIF_CAR_P__SOURCE_AIF_PKT_CLK_RSTN_EN1_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_AIF_CAR_P__SOURCE_AIF_PKT_CLK_RSTN_EN1_WOSET 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_AIF_CAR_P__SOURCE_AIF_PKT_CLK_EN2_MASK 0x00000040U
+#define MHDP__MHDP_APB_REGS__SOURCE_AIF_CAR_P__SOURCE_AIF_PKT_CLK_EN2_SHIFT 6U
+#define MHDP__MHDP_APB_REGS__SOURCE_AIF_CAR_P__SOURCE_AIF_PKT_CLK_EN2_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__SOURCE_AIF_CAR_P__SOURCE_AIF_PKT_CLK_EN2_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_AIF_CAR_P__SOURCE_AIF_PKT_CLK_EN2_WOSET 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_AIF_CAR_P__SOURCE_AIF_PKT_CLK_RSTN_EN2_MASK 0x00000080U
+#define MHDP__MHDP_APB_REGS__SOURCE_AIF_CAR_P__SOURCE_AIF_PKT_CLK_RSTN_EN2_SHIFT 7U
+#define MHDP__MHDP_APB_REGS__SOURCE_AIF_CAR_P__SOURCE_AIF_PKT_CLK_RSTN_EN2_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__SOURCE_AIF_CAR_P__SOURCE_AIF_PKT_CLK_RSTN_EN2_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_AIF_CAR_P__SOURCE_AIF_PKT_CLK_RSTN_EN2_WOSET 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_AIF_CAR_P__SOURCE_AIF_PKT_CLK_EN3_MASK 0x00000100U
+#define MHDP__MHDP_APB_REGS__SOURCE_AIF_CAR_P__SOURCE_AIF_PKT_CLK_EN3_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__SOURCE_AIF_CAR_P__SOURCE_AIF_PKT_CLK_EN3_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__SOURCE_AIF_CAR_P__SOURCE_AIF_PKT_CLK_EN3_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_AIF_CAR_P__SOURCE_AIF_PKT_CLK_EN3_WOSET 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_AIF_CAR_P__SOURCE_AIF_PKT_CLK_RSTN_EN3_MASK 0x00000200U
+#define MHDP__MHDP_APB_REGS__SOURCE_AIF_CAR_P__SOURCE_AIF_PKT_CLK_RSTN_EN3_SHIFT 9U
+#define MHDP__MHDP_APB_REGS__SOURCE_AIF_CAR_P__SOURCE_AIF_PKT_CLK_RSTN_EN3_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__SOURCE_AIF_CAR_P__SOURCE_AIF_PKT_CLK_RSTN_EN3_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_AIF_CAR_P__SOURCE_AIF_PKT_CLK_RSTN_EN3_WOSET 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_AIF_CAR_P__RESERVED_0_MASK 0xFFFFFC00U
+#define MHDP__MHDP_APB_REGS__SOURCE_AIF_CAR_P__RESERVED_0_SHIFT 10U
+#define MHDP__MHDP_APB_REGS__SOURCE_AIF_CAR_P__RESERVED_0_WIDTH 22U
+
+#define MHDP__MHDP_APB_REGS__SOURCE_CIPHER_CAR_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__SOURCE_CIPHER_CAR_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__SOURCE_CIPHER_CAR_P__SOURCE_CIPHER_CHAR_CLK_EN_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__SOURCE_CIPHER_CAR_P__SOURCE_CIPHER_CHAR_CLK_EN_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_CIPHER_CAR_P__SOURCE_CIPHER_CHAR_CLK_EN_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__SOURCE_CIPHER_CAR_P__SOURCE_CIPHER_CHAR_CLK_EN_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_CIPHER_CAR_P__SOURCE_CIPHER_CHAR_CLK_EN_WOSET 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_CIPHER_CAR_P__SOURCE_CIPHER_CHAR_CLK_RSTN_EN_MASK 0x00000002U
+#define MHDP__MHDP_APB_REGS__SOURCE_CIPHER_CAR_P__SOURCE_CIPHER_CHAR_CLK_RSTN_EN_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__SOURCE_CIPHER_CAR_P__SOURCE_CIPHER_CHAR_CLK_RSTN_EN_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__SOURCE_CIPHER_CAR_P__SOURCE_CIPHER_CHAR_CLK_RSTN_EN_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_CIPHER_CAR_P__SOURCE_CIPHER_CHAR_CLK_RSTN_EN_WOSET 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_CIPHER_CAR_P__SOURCE_CIPHER_SYS_CLK_EN_MASK 0x00000004U
+#define MHDP__MHDP_APB_REGS__SOURCE_CIPHER_CAR_P__SOURCE_CIPHER_SYS_CLK_EN_SHIFT 2U
+#define MHDP__MHDP_APB_REGS__SOURCE_CIPHER_CAR_P__SOURCE_CIPHER_SYS_CLK_EN_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__SOURCE_CIPHER_CAR_P__SOURCE_CIPHER_SYS_CLK_EN_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_CIPHER_CAR_P__SOURCE_CIPHER_SYS_CLK_EN_WOSET 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_CIPHER_CAR_P__SOURCE_CIPHER_SYSTEM_CLK_RSTN_EN_MASK 0x00000008U
+#define MHDP__MHDP_APB_REGS__SOURCE_CIPHER_CAR_P__SOURCE_CIPHER_SYSTEM_CLK_RSTN_EN_SHIFT 3U
+#define MHDP__MHDP_APB_REGS__SOURCE_CIPHER_CAR_P__SOURCE_CIPHER_SYSTEM_CLK_RSTN_EN_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__SOURCE_CIPHER_CAR_P__SOURCE_CIPHER_SYSTEM_CLK_RSTN_EN_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_CIPHER_CAR_P__SOURCE_CIPHER_SYSTEM_CLK_RSTN_EN_WOSET 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_CIPHER_CAR_P__RESERVED_0_MASK 0xFFFFFFF0U
+#define MHDP__MHDP_APB_REGS__SOURCE_CIPHER_CAR_P__RESERVED_0_SHIFT 4U
+#define MHDP__MHDP_APB_REGS__SOURCE_CIPHER_CAR_P__RESERVED_0_WIDTH 28U
+
+#define MHDP__MHDP_APB_REGS__SOURCE_CRYPTO_CAR_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__SOURCE_CRYPTO_CAR_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__SOURCE_CRYPTO_CAR_P__SOURCE_CRYPTO_SYS_CLK_EN_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__SOURCE_CRYPTO_CAR_P__SOURCE_CRYPTO_SYS_CLK_EN_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_CRYPTO_CAR_P__SOURCE_CRYPTO_SYS_CLK_EN_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__SOURCE_CRYPTO_CAR_P__SOURCE_CRYPTO_SYS_CLK_EN_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_CRYPTO_CAR_P__SOURCE_CRYPTO_SYS_CLK_EN_WOSET 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_CRYPTO_CAR_P__SOURCE_CRYPTO_SYS_CLK_RSTN_EN_MASK 0x00000002U
+#define MHDP__MHDP_APB_REGS__SOURCE_CRYPTO_CAR_P__SOURCE_CRYPTO_SYS_CLK_RSTN_EN_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__SOURCE_CRYPTO_CAR_P__SOURCE_CRYPTO_SYS_CLK_RSTN_EN_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__SOURCE_CRYPTO_CAR_P__SOURCE_CRYPTO_SYS_CLK_RSTN_EN_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_CRYPTO_CAR_P__SOURCE_CRYPTO_SYS_CLK_RSTN_EN_WOSET 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_CRYPTO_CAR_P__RESERVED_0_MASK 0xFFFFFFFCU
+#define MHDP__MHDP_APB_REGS__SOURCE_CRYPTO_CAR_P__RESERVED_0_SHIFT 2U
+#define MHDP__MHDP_APB_REGS__SOURCE_CRYPTO_CAR_P__RESERVED_0_WIDTH 30U
+
+#define MHDP__MHDP_APB_REGS__SOURCE_SPDIF_CAR_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__SOURCE_SPDIF_CAR_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__SOURCE_SPDIF_CAR_P__SPDIF_CDR_CLK_EN0_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__SOURCE_SPDIF_CAR_P__SPDIF_CDR_CLK_EN0_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_SPDIF_CAR_P__SPDIF_CDR_CLK_EN0_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__SOURCE_SPDIF_CAR_P__SPDIF_CDR_CLK_EN0_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_SPDIF_CAR_P__SPDIF_CDR_CLK_EN0_WOSET 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_SPDIF_CAR_P__SPDIF_CDR_CLK_RSTN_EN0_MASK 0x00000002U
+#define MHDP__MHDP_APB_REGS__SOURCE_SPDIF_CAR_P__SPDIF_CDR_CLK_RSTN_EN0_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__SOURCE_SPDIF_CAR_P__SPDIF_CDR_CLK_RSTN_EN0_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__SOURCE_SPDIF_CAR_P__SPDIF_CDR_CLK_RSTN_EN0_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_SPDIF_CAR_P__SPDIF_CDR_CLK_RSTN_EN0_WOSET 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_SPDIF_CAR_P__SPDIF_MCLK_EN0_MASK 0x00000004U
+#define MHDP__MHDP_APB_REGS__SOURCE_SPDIF_CAR_P__SPDIF_MCLK_EN0_SHIFT 2U
+#define MHDP__MHDP_APB_REGS__SOURCE_SPDIF_CAR_P__SPDIF_MCLK_EN0_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__SOURCE_SPDIF_CAR_P__SPDIF_MCLK_EN0_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_SPDIF_CAR_P__SPDIF_MCLK_EN0_WOSET 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_SPDIF_CAR_P__SPDIF_MCLK_RSTN_EN0_MASK 0x00000008U
+#define MHDP__MHDP_APB_REGS__SOURCE_SPDIF_CAR_P__SPDIF_MCLK_RSTN_EN0_SHIFT 3U
+#define MHDP__MHDP_APB_REGS__SOURCE_SPDIF_CAR_P__SPDIF_MCLK_RSTN_EN0_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__SOURCE_SPDIF_CAR_P__SPDIF_MCLK_RSTN_EN0_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_SPDIF_CAR_P__SPDIF_MCLK_RSTN_EN0_WOSET 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_SPDIF_CAR_P__SPDIF_CDR_CLK_EN1_MASK 0x00000010U
+#define MHDP__MHDP_APB_REGS__SOURCE_SPDIF_CAR_P__SPDIF_CDR_CLK_EN1_SHIFT 4U
+#define MHDP__MHDP_APB_REGS__SOURCE_SPDIF_CAR_P__SPDIF_CDR_CLK_EN1_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__SOURCE_SPDIF_CAR_P__SPDIF_CDR_CLK_EN1_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_SPDIF_CAR_P__SPDIF_CDR_CLK_EN1_WOSET 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_SPDIF_CAR_P__SPDIF_CDR_CLK_RSTN_EN1_MASK 0x00000020U
+#define MHDP__MHDP_APB_REGS__SOURCE_SPDIF_CAR_P__SPDIF_CDR_CLK_RSTN_EN1_SHIFT 5U
+#define MHDP__MHDP_APB_REGS__SOURCE_SPDIF_CAR_P__SPDIF_CDR_CLK_RSTN_EN1_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__SOURCE_SPDIF_CAR_P__SPDIF_CDR_CLK_RSTN_EN1_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_SPDIF_CAR_P__SPDIF_CDR_CLK_RSTN_EN1_WOSET 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_SPDIF_CAR_P__SPDIF_MCLK_EN1_MASK 0x00000040U
+#define MHDP__MHDP_APB_REGS__SOURCE_SPDIF_CAR_P__SPDIF_MCLK_EN1_SHIFT 6U
+#define MHDP__MHDP_APB_REGS__SOURCE_SPDIF_CAR_P__SPDIF_MCLK_EN1_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__SOURCE_SPDIF_CAR_P__SPDIF_MCLK_EN1_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_SPDIF_CAR_P__SPDIF_MCLK_EN1_WOSET 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_SPDIF_CAR_P__SPDIF_MCLK_RSTN_EN1_MASK 0x00000080U
+#define MHDP__MHDP_APB_REGS__SOURCE_SPDIF_CAR_P__SPDIF_MCLK_RSTN_EN1_SHIFT 7U
+#define MHDP__MHDP_APB_REGS__SOURCE_SPDIF_CAR_P__SPDIF_MCLK_RSTN_EN1_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__SOURCE_SPDIF_CAR_P__SPDIF_MCLK_RSTN_EN1_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_SPDIF_CAR_P__SPDIF_MCLK_RSTN_EN1_WOSET 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_SPDIF_CAR_P__SPDIF_CDR_CLK_EN2_MASK 0x00000100U
+#define MHDP__MHDP_APB_REGS__SOURCE_SPDIF_CAR_P__SPDIF_CDR_CLK_EN2_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__SOURCE_SPDIF_CAR_P__SPDIF_CDR_CLK_EN2_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__SOURCE_SPDIF_CAR_P__SPDIF_CDR_CLK_EN2_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_SPDIF_CAR_P__SPDIF_CDR_CLK_EN2_WOSET 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_SPDIF_CAR_P__SPDIF_CDR_CLK_RSTN_EN2_MASK 0x00000200U
+#define MHDP__MHDP_APB_REGS__SOURCE_SPDIF_CAR_P__SPDIF_CDR_CLK_RSTN_EN2_SHIFT 9U
+#define MHDP__MHDP_APB_REGS__SOURCE_SPDIF_CAR_P__SPDIF_CDR_CLK_RSTN_EN2_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__SOURCE_SPDIF_CAR_P__SPDIF_CDR_CLK_RSTN_EN2_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_SPDIF_CAR_P__SPDIF_CDR_CLK_RSTN_EN2_WOSET 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_SPDIF_CAR_P__SPDIF_MCLK_EN2_MASK 0x00000400U
+#define MHDP__MHDP_APB_REGS__SOURCE_SPDIF_CAR_P__SPDIF_MCLK_EN2_SHIFT 10U
+#define MHDP__MHDP_APB_REGS__SOURCE_SPDIF_CAR_P__SPDIF_MCLK_EN2_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__SOURCE_SPDIF_CAR_P__SPDIF_MCLK_EN2_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_SPDIF_CAR_P__SPDIF_MCLK_EN2_WOSET 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_SPDIF_CAR_P__SPDIF_MCLK_RSTN_EN2_MASK 0x00000800U
+#define MHDP__MHDP_APB_REGS__SOURCE_SPDIF_CAR_P__SPDIF_MCLK_RSTN_EN2_SHIFT 11U
+#define MHDP__MHDP_APB_REGS__SOURCE_SPDIF_CAR_P__SPDIF_MCLK_RSTN_EN2_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__SOURCE_SPDIF_CAR_P__SPDIF_MCLK_RSTN_EN2_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_SPDIF_CAR_P__SPDIF_MCLK_RSTN_EN2_WOSET 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_SPDIF_CAR_P__SPDIF_CDR_CLK_EN3_MASK 0x00001000U
+#define MHDP__MHDP_APB_REGS__SOURCE_SPDIF_CAR_P__SPDIF_CDR_CLK_EN3_SHIFT 12U
+#define MHDP__MHDP_APB_REGS__SOURCE_SPDIF_CAR_P__SPDIF_CDR_CLK_EN3_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__SOURCE_SPDIF_CAR_P__SPDIF_CDR_CLK_EN3_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_SPDIF_CAR_P__SPDIF_CDR_CLK_EN3_WOSET 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_SPDIF_CAR_P__SPDIF_CDR_CLK_RSTN_EN3_MASK 0x00002000U
+#define MHDP__MHDP_APB_REGS__SOURCE_SPDIF_CAR_P__SPDIF_CDR_CLK_RSTN_EN3_SHIFT 13U
+#define MHDP__MHDP_APB_REGS__SOURCE_SPDIF_CAR_P__SPDIF_CDR_CLK_RSTN_EN3_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__SOURCE_SPDIF_CAR_P__SPDIF_CDR_CLK_RSTN_EN3_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_SPDIF_CAR_P__SPDIF_CDR_CLK_RSTN_EN3_WOSET 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_SPDIF_CAR_P__SPDIF_MCLK_EN3_MASK 0x00004000U
+#define MHDP__MHDP_APB_REGS__SOURCE_SPDIF_CAR_P__SPDIF_MCLK_EN3_SHIFT 14U
+#define MHDP__MHDP_APB_REGS__SOURCE_SPDIF_CAR_P__SPDIF_MCLK_EN3_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__SOURCE_SPDIF_CAR_P__SPDIF_MCLK_EN3_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_SPDIF_CAR_P__SPDIF_MCLK_EN3_WOSET 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_SPDIF_CAR_P__SPDIF_MCLK_RSTN_EN3_MASK 0x00008000U
+#define MHDP__MHDP_APB_REGS__SOURCE_SPDIF_CAR_P__SPDIF_MCLK_RSTN_EN3_SHIFT 15U
+#define MHDP__MHDP_APB_REGS__SOURCE_SPDIF_CAR_P__SPDIF_MCLK_RSTN_EN3_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__SOURCE_SPDIF_CAR_P__SPDIF_MCLK_RSTN_EN3_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_SPDIF_CAR_P__SPDIF_MCLK_RSTN_EN3_WOSET 0U
+#define MHDP__MHDP_APB_REGS__SOURCE_SPDIF_CAR_P__RESERVED_MASK 0xFFFF0000U
+#define MHDP__MHDP_APB_REGS__SOURCE_SPDIF_CAR_P__RESERVED_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__SOURCE_SPDIF_CAR_P__RESERVED_WIDTH 16U
+
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__CM_CTRL_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__CM_CTRL_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__CM_CTRL_P__NMVID_SEL_EXTERNAL_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__CM_CTRL_P__NMVID_SEL_EXTERNAL_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__CM_CTRL_P__NMVID_SEL_EXTERNAL_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__CM_CTRL_P__NMVID_SEL_EXTERNAL_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__CM_CTRL_P__NMVID_SEL_EXTERNAL_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__CM_CTRL_P__SPDIF_SEL_EXTERNAL_MASK 0x00000002U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__CM_CTRL_P__SPDIF_SEL_EXTERNAL_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__CM_CTRL_P__SPDIF_SEL_EXTERNAL_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__CM_CTRL_P__SPDIF_SEL_EXTERNAL_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__CM_CTRL_P__SPDIF_SEL_EXTERNAL_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__CM_CTRL_P__I2S_SEL_EXTERNAL_MASK 0x00000004U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__CM_CTRL_P__I2S_SEL_EXTERNAL_SHIFT 2U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__CM_CTRL_P__I2S_SEL_EXTERNAL_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__CM_CTRL_P__I2S_SEL_EXTERNAL_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__CM_CTRL_P__I2S_SEL_EXTERNAL_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__CM_CTRL_P__SEL_AUD_LANE_REF_MASK 0x00000008U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__CM_CTRL_P__SEL_AUD_LANE_REF_SHIFT 3U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__CM_CTRL_P__SEL_AUD_LANE_REF_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__CM_CTRL_P__SEL_AUD_LANE_REF_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__CM_CTRL_P__SEL_AUD_LANE_REF_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__CM_CTRL_P__I2S_MULT_MASK 0x00000070U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__CM_CTRL_P__I2S_MULT_SHIFT 4U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__CM_CTRL_P__I2S_MULT_WIDTH 3U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__CM_CTRL_P__RESERVED_0_MASK 0xFFFFFF80U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__CM_CTRL_P__RESERVED_0_SHIFT 7U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__CM_CTRL_P__RESERVED_0_WIDTH 25U
+
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__CM_I2S_CTRL_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__CM_I2S_CTRL_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__CM_I2S_CTRL_P__I2S_REF_CYC_MASK 0x00FFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__CM_I2S_CTRL_P__I2S_REF_CYC_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__CM_I2S_CTRL_P__I2S_REF_CYC_WIDTH 24U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__CM_I2S_CTRL_P__I2S_MEAS_TOLERANCE_MASK 0x0F000000U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__CM_I2S_CTRL_P__I2S_MEAS_TOLERANCE_SHIFT 24U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__CM_I2S_CTRL_P__I2S_MEAS_TOLERANCE_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__CM_I2S_CTRL_P__RESERVED_0_MASK 0xF0000000U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__CM_I2S_CTRL_P__RESERVED_0_SHIFT 28U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__CM_I2S_CTRL_P__RESERVED_0_WIDTH 4U
+
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__CM_SPDIF_CTRL_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__CM_SPDIF_CTRL_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__CM_SPDIF_CTRL_P__SPDIF_REF_CYC_MASK 0x00FFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__CM_SPDIF_CTRL_P__SPDIF_REF_CYC_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__CM_SPDIF_CTRL_P__SPDIF_REF_CYC_WIDTH 24U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__CM_SPDIF_CTRL_P__SPDIF_MEAS_TOLERANCE_MASK 0x0F000000U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__CM_SPDIF_CTRL_P__SPDIF_MEAS_TOLERANCE_SHIFT 24U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__CM_SPDIF_CTRL_P__SPDIF_MEAS_TOLERANCE_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__CM_SPDIF_CTRL_P__RESERVED_0_MASK 0xF0000000U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__CM_SPDIF_CTRL_P__RESERVED_0_SHIFT 28U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__CM_SPDIF_CTRL_P__RESERVED_0_WIDTH 4U
+
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__CM_VID_CTRL_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__CM_VID_CTRL_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__CM_VID_CTRL_P__NMVID_REF_CYC_MASK 0x00FFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__CM_VID_CTRL_P__NMVID_REF_CYC_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__CM_VID_CTRL_P__NMVID_REF_CYC_WIDTH 24U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__CM_VID_CTRL_P__NMVID_MEAS_TOLERANCE_MASK 0x0F000000U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__CM_VID_CTRL_P__NMVID_MEAS_TOLERANCE_SHIFT 24U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__CM_VID_CTRL_P__NMVID_MEAS_TOLERANCE_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__CM_VID_CTRL_P__RESERVED_0_MASK 0xF0000000U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__CM_VID_CTRL_P__RESERVED_0_SHIFT 28U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__CM_VID_CTRL_P__RESERVED_0_WIDTH 4U
+
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__CM_LANE_CTRL_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__CM_LANE_CTRL_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__CM_LANE_CTRL_P__LANE_REF_CYC_MASK 0x00FFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__CM_LANE_CTRL_P__LANE_REF_CYC_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__CM_LANE_CTRL_P__LANE_REF_CYC_WIDTH 24U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__CM_LANE_CTRL_P__RESERVED_0_MASK 0xFF000000U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__CM_LANE_CTRL_P__RESERVED_0_SHIFT 24U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__CM_LANE_CTRL_P__RESERVED_0_WIDTH 8U
+
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__I2S_NM_STABLE_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__I2S_NM_STABLE_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__I2S_NM_STABLE_P__I2S_MNAUD_STABLE_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__I2S_NM_STABLE_P__I2S_MNAUD_STABLE_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__I2S_NM_STABLE_P__I2S_MNAUD_STABLE_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__I2S_NM_STABLE_P__I2S_MNAUD_STABLE_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__I2S_NM_STABLE_P__I2S_MNAUD_STABLE_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__I2S_NM_STABLE_P__RESERVED_0_MASK 0xFFFFFFFEU
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__I2S_NM_STABLE_P__RESERVED_0_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__I2S_NM_STABLE_P__RESERVED_0_WIDTH 31U
+
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__I2S_NCTS_STABLE_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__I2S_NCTS_STABLE_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__I2S_NCTS_STABLE_P__I2S_NCTS_STABLE_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__I2S_NCTS_STABLE_P__I2S_NCTS_STABLE_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__I2S_NCTS_STABLE_P__I2S_NCTS_STABLE_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__I2S_NCTS_STABLE_P__I2S_NCTS_STABLE_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__I2S_NCTS_STABLE_P__I2S_NCTS_STABLE_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__I2S_NCTS_STABLE_P__RESERVED_0_MASK 0xFFFFFFFEU
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__I2S_NCTS_STABLE_P__RESERVED_0_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__I2S_NCTS_STABLE_P__RESERVED_0_WIDTH 31U
+
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__SPDIF_NM_STABLE_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__SPDIF_NM_STABLE_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__SPDIF_NM_STABLE_P__SPDIF_MNAUD_STABLE_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__SPDIF_NM_STABLE_P__SPDIF_MNAUD_STABLE_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__SPDIF_NM_STABLE_P__SPDIF_MNAUD_STABLE_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__SPDIF_NM_STABLE_P__SPDIF_MNAUD_STABLE_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__SPDIF_NM_STABLE_P__SPDIF_MNAUD_STABLE_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__SPDIF_NM_STABLE_P__RESERVED_0_MASK 0xFFFFFFFEU
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__SPDIF_NM_STABLE_P__RESERVED_0_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__SPDIF_NM_STABLE_P__RESERVED_0_WIDTH 31U
+
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__SPDIF_NCTS_STABLE_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__SPDIF_NCTS_STABLE_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__SPDIF_NCTS_STABLE_P__SPDIF_NCTS_STABLE_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__SPDIF_NCTS_STABLE_P__SPDIF_NCTS_STABLE_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__SPDIF_NCTS_STABLE_P__SPDIF_NCTS_STABLE_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__SPDIF_NCTS_STABLE_P__SPDIF_NCTS_STABLE_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__SPDIF_NCTS_STABLE_P__SPDIF_NCTS_STABLE_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__SPDIF_NCTS_STABLE_P__RESERVED_0_MASK 0xFFFFFFFEU
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__SPDIF_NCTS_STABLE_P__RESERVED_0_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__SPDIF_NCTS_STABLE_P__RESERVED_0_WIDTH 31U
+
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__NMVID_MEAS_STABLE_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__NMVID_MEAS_STABLE_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__NMVID_MEAS_STABLE_P__ST_NMVID_MEAS_STABLE_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__NMVID_MEAS_STABLE_P__ST_NMVID_MEAS_STABLE_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__NMVID_MEAS_STABLE_P__ST_NMVID_MEAS_STABLE_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__NMVID_MEAS_STABLE_P__ST_NMVID_MEAS_STABLE_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__NMVID_MEAS_STABLE_P__ST_NMVID_MEAS_STABLE_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__NMVID_MEAS_STABLE_P__RESERVED_0_MASK 0xFFFFFFFEU
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__NMVID_MEAS_STABLE_P__RESERVED_0_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__NMVID_MEAS_STABLE_P__RESERVED_0_WIDTH 31U
+
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__CM_VID_MEAS_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__CM_VID_MEAS_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__CM_VID_MEAS_P__NMVID_MEAS_CYC_MASK 0x00FFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__CM_VID_MEAS_P__NMVID_MEAS_CYC_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__CM_VID_MEAS_P__NMVID_MEAS_CYC_WIDTH 24U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__CM_VID_MEAS_P__NMVID_MEAS_VALID_INDC_MASK 0x01000000U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__CM_VID_MEAS_P__NMVID_MEAS_VALID_INDC_SHIFT 24U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__CM_VID_MEAS_P__NMVID_MEAS_VALID_INDC_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__CM_VID_MEAS_P__NMVID_MEAS_VALID_INDC_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__CM_VID_MEAS_P__NMVID_MEAS_VALID_INDC_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__CM_VID_MEAS_P__RESERVED_0_MASK 0xFE000000U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__CM_VID_MEAS_P__RESERVED_0_SHIFT 25U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__CM_VID_MEAS_P__RESERVED_0_WIDTH 7U
+
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__CM_AUD_MEAS_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__CM_AUD_MEAS_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__CM_AUD_MEAS_P__NMAUD_MEAS_CYC_MASK 0x00FFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__CM_AUD_MEAS_P__NMAUD_MEAS_CYC_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__CM_AUD_MEAS_P__NMAUD_MEAS_CYC_WIDTH 24U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__CM_AUD_MEAS_P__NMAUD_MEAS_VALID_INDC_MASK 0x01000000U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__CM_AUD_MEAS_P__NMAUD_MEAS_VALID_INDC_SHIFT 24U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__CM_AUD_MEAS_P__NMAUD_MEAS_VALID_INDC_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__CM_AUD_MEAS_P__NMAUD_MEAS_VALID_INDC_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__CM_AUD_MEAS_P__NMAUD_MEAS_VALID_INDC_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__CM_AUD_MEAS_P__RESERVED_0_MASK 0xFE000000U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__CM_AUD_MEAS_P__RESERVED_0_SHIFT 25U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__CM_AUD_MEAS_P__RESERVED_0_WIDTH 7U
+
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__I2S_MEAS_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__I2S_MEAS_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__I2S_MEAS_P__I2_MEAS_MASK 0x00FFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__I2S_MEAS_P__I2_MEAS_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__I2S_MEAS_P__I2_MEAS_WIDTH 24U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__I2S_MEAS_P__RESERVED_0_MASK 0xFF000000U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__I2S_MEAS_P__RESERVED_0_SHIFT 24U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__I2S_MEAS_P__RESERVED_0_WIDTH 8U
+
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__SPDIF_MEAS_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__SPDIF_MEAS_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__SPDIF_MEAS_P__SPDIF_MEAS_MASK 0x00FFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__SPDIF_MEAS_P__SPDIF_MEAS_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__SPDIF_MEAS_P__SPDIF_MEAS_WIDTH 24U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__SPDIF_MEAS_P__RESERVED_0_MASK 0xFF000000U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__SPDIF_MEAS_P__RESERVED_0_SHIFT 24U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__SPDIF_MEAS_P__RESERVED_0_WIDTH 8U
+
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__NMVID_MEAS_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__NMVID_MEAS_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__NMVID_MEAS_P__NMVID_MEAS_MASK 0x00FFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__NMVID_MEAS_P__NMVID_MEAS_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__NMVID_MEAS_P__NMVID_MEAS_WIDTH 24U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__NMVID_MEAS_P__RESERVED_0_MASK 0xFF000000U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__NMVID_MEAS_P__RESERVED_0_SHIFT 24U
+#define MHDP__MHDP_APB_REGS__MHDP_CLOCK_METER__NMVID_MEAS_P__RESERVED_0_WIDTH 8U
+
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__BND_HSYNC2VSYNC_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__BND_HSYNC2VSYNC_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__BND_HSYNC2VSYNC_P__IP_DTCT_WIN_MASK 0x00000FFFU
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__BND_HSYNC2VSYNC_P__IP_DTCT_WIN_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__BND_HSYNC2VSYNC_P__IP_DTCT_WIN_WIDTH 12U
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__BND_HSYNC2VSYNC_P__IP_DET_EN_MASK 0x00001000U
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__BND_HSYNC2VSYNC_P__IP_DET_EN_SHIFT 12U
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__BND_HSYNC2VSYNC_P__IP_DET_EN_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__BND_HSYNC2VSYNC_P__IP_DET_EN_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__BND_HSYNC2VSYNC_P__IP_DET_EN_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__BND_HSYNC2VSYNC_P__IP_VIF_BYPASS_MASK 0x00002000U
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__BND_HSYNC2VSYNC_P__IP_VIF_BYPASS_SHIFT 13U
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__BND_HSYNC2VSYNC_P__IP_VIF_BYPASS_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__BND_HSYNC2VSYNC_P__IP_VIF_BYPASS_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__BND_HSYNC2VSYNC_P__IP_VIF_BYPASS_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__BND_HSYNC2VSYNC_P__IP_VIF_ALIGNMENT_MASK 0x00004000U
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__BND_HSYNC2VSYNC_P__IP_VIF_ALIGNMENT_SHIFT 14U
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__BND_HSYNC2VSYNC_P__IP_VIF_ALIGNMENT_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__BND_HSYNC2VSYNC_P__IP_VIF_ALIGNMENT_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__BND_HSYNC2VSYNC_P__IP_VIF_ALIGNMENT_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__BND_HSYNC2VSYNC_P__RESERVED_0_MASK 0xFFFF8000U
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__BND_HSYNC2VSYNC_P__RESERVED_0_SHIFT 15U
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__BND_HSYNC2VSYNC_P__RESERVED_0_WIDTH 17U
+
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__HSYNC2VSYNC_F1_L1_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__HSYNC2VSYNC_F1_L1_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__HSYNC2VSYNC_F1_L1_P__IP_DTCT_HSYNC2VSYNC_F1_MASK 0x0000FFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__HSYNC2VSYNC_F1_L1_P__IP_DTCT_HSYNC2VSYNC_F1_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__HSYNC2VSYNC_F1_L1_P__IP_DTCT_HSYNC2VSYNC_F1_WIDTH 16U
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__HSYNC2VSYNC_F1_L1_P__RESERVED_0_MASK 0xFFFF0000U
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__HSYNC2VSYNC_F1_L1_P__RESERVED_0_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__HSYNC2VSYNC_F1_L1_P__RESERVED_0_WIDTH 16U
+
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__HSYNC2VSYNC_F2_L1_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__HSYNC2VSYNC_F2_L1_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__HSYNC2VSYNC_F2_L1_P__IP_DTCT_HSYNC2VSYNC_F2_MASK 0x0000FFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__HSYNC2VSYNC_F2_L1_P__IP_DTCT_HSYNC2VSYNC_F2_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__HSYNC2VSYNC_F2_L1_P__IP_DTCT_HSYNC2VSYNC_F2_WIDTH 16U
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__HSYNC2VSYNC_F2_L1_P__RESERVED_0_MASK 0xFFFF0000U
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__HSYNC2VSYNC_F2_L1_P__RESERVED_0_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__HSYNC2VSYNC_F2_L1_P__RESERVED_0_WIDTH 16U
+
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__HSYNC2VSYNC_STATUS_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__HSYNC2VSYNC_STATUS_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__HSYNC2VSYNC_STATUS_P__IP_DTCT_ERR_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__HSYNC2VSYNC_STATUS_P__IP_DTCT_ERR_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__HSYNC2VSYNC_STATUS_P__IP_DTCT_ERR_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__HSYNC2VSYNC_STATUS_P__IP_DTCT_ERR_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__HSYNC2VSYNC_STATUS_P__IP_DTCT_ERR_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__HSYNC2VSYNC_STATUS_P__IP_DCT_IP_MASK 0x00000002U
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__HSYNC2VSYNC_STATUS_P__IP_DCT_IP_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__HSYNC2VSYNC_STATUS_P__IP_DCT_IP_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__HSYNC2VSYNC_STATUS_P__IP_DCT_IP_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__HSYNC2VSYNC_STATUS_P__IP_DCT_IP_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__HSYNC2VSYNC_STATUS_P__IP_DTCT_VJITTER_MASK 0x00000004U
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__HSYNC2VSYNC_STATUS_P__IP_DTCT_VJITTER_SHIFT 2U
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__HSYNC2VSYNC_STATUS_P__IP_DTCT_VJITTER_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__HSYNC2VSYNC_STATUS_P__IP_DTCT_VJITTER_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__HSYNC2VSYNC_STATUS_P__IP_DTCT_VJITTER_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__HSYNC2VSYNC_STATUS_P__IP_DTCT_HJITTER_MASK 0x00000008U
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__HSYNC2VSYNC_STATUS_P__IP_DTCT_HJITTER_SHIFT 3U
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__HSYNC2VSYNC_STATUS_P__IP_DTCT_HJITTER_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__HSYNC2VSYNC_STATUS_P__IP_DTCT_HJITTER_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__HSYNC2VSYNC_STATUS_P__IP_DTCT_HJITTER_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__HSYNC2VSYNC_STATUS_P__RESERVED_0_MASK 0xFFFFFFF0U
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__HSYNC2VSYNC_STATUS_P__RESERVED_0_SHIFT 4U
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__HSYNC2VSYNC_STATUS_P__RESERVED_0_WIDTH 28U
+
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__HSYNC2VSYNC_POL_CTRL_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__HSYNC2VSYNC_POL_CTRL_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__HSYNC2VSYNC_POL_CTRL_P__VIF_AUTO_MODE_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__HSYNC2VSYNC_POL_CTRL_P__VIF_AUTO_MODE_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__HSYNC2VSYNC_POL_CTRL_P__VIF_AUTO_MODE_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__HSYNC2VSYNC_POL_CTRL_P__VIF_AUTO_MODE_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__HSYNC2VSYNC_POL_CTRL_P__VIF_AUTO_MODE_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__HSYNC2VSYNC_POL_CTRL_P__HPOL_MASK 0x00000002U
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__HSYNC2VSYNC_POL_CTRL_P__HPOL_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__HSYNC2VSYNC_POL_CTRL_P__HPOL_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__HSYNC2VSYNC_POL_CTRL_P__HPOL_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__HSYNC2VSYNC_POL_CTRL_P__HPOL_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__HSYNC2VSYNC_POL_CTRL_P__VPOL_MASK 0x00000004U
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__HSYNC2VSYNC_POL_CTRL_P__VPOL_SHIFT 2U
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__HSYNC2VSYNC_POL_CTRL_P__VPOL_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__HSYNC2VSYNC_POL_CTRL_P__VPOL_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__HSYNC2VSYNC_POL_CTRL_P__VPOL_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__HSYNC2VSYNC_POL_CTRL_P__RESERVED_0_MASK 0xFFFFFFF8U
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__HSYNC2VSYNC_POL_CTRL_P__RESERVED_0_SHIFT 3U
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__HSYNC2VSYNC_POL_CTRL_P__RESERVED_0_WIDTH 29U
+
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__DSC_CTRL_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__DSC_CTRL_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__DSC_CTRL_P__DSC_EN_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__DSC_CTRL_P__DSC_EN_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__DSC_CTRL_P__DSC_EN_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__DSC_CTRL_P__DSC_EN_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__DSC_CTRL_P__DSC_EN_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__DSC_CTRL_P__DSC_SW_RST_MASK 0x00000002U
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__DSC_CTRL_P__DSC_SW_RST_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__DSC_CTRL_P__DSC_SW_RST_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__DSC_CTRL_P__DSC_SW_RST_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__DSC_CTRL_P__DSC_SW_RST_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__DSC_CTRL_P__DSC_REG_UPDATE_MASK 0x00000004U
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__DSC_CTRL_P__DSC_REG_UPDATE_SHIFT 2U
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__DSC_CTRL_P__DSC_REG_UPDATE_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__DSC_CTRL_P__DSC_REG_UPDATE_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__DSC_CTRL_P__DSC_REG_UPDATE_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__DSC_CTRL_P__RESERVED_0_MASK 0xFFFFFFF8U
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__DSC_CTRL_P__RESERVED_0_SHIFT 3U
+#define MHDP__MHDP_APB_REGS__MHDP_VIF_CTRL__DSC_CTRL_P__RESERVED_0_WIDTH 29U
+
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_CONFIG_REG_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_CONFIG_REG_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_CONFIG_REG_P__DP_TX_PHY_TRAINING_ENABLE_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_CONFIG_REG_P__DP_TX_PHY_TRAINING_ENABLE_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_CONFIG_REG_P__DP_TX_PHY_TRAINING_ENABLE_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_CONFIG_REG_P__DP_TX_PHY_TRAINING_ENABLE_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_CONFIG_REG_P__DP_TX_PHY_TRAINING_ENABLE_WOSET 0U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_CONFIG_REG_P__DP_TX_PHY_TRAINING_TYPE_MASK 0x0000001EU
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_CONFIG_REG_P__DP_TX_PHY_TRAINING_TYPE_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_CONFIG_REG_P__DP_TX_PHY_TRAINING_TYPE_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_CONFIG_REG_P__DP_TX_PHY_SCRAMBLER_BYPASS_MASK 0x00000020U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_CONFIG_REG_P__DP_TX_PHY_SCRAMBLER_BYPASS_SHIFT 5U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_CONFIG_REG_P__DP_TX_PHY_SCRAMBLER_BYPASS_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_CONFIG_REG_P__DP_TX_PHY_SCRAMBLER_BYPASS_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_CONFIG_REG_P__DP_TX_PHY_SCRAMBLER_BYPASS_WOSET 0U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_CONFIG_REG_P__DP_TX_PHY_ENCODER_BYPASS_MASK 0x00000040U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_CONFIG_REG_P__DP_TX_PHY_ENCODER_BYPASS_SHIFT 6U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_CONFIG_REG_P__DP_TX_PHY_ENCODER_BYPASS_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_CONFIG_REG_P__DP_TX_PHY_ENCODER_BYPASS_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_CONFIG_REG_P__DP_TX_PHY_ENCODER_BYPASS_WOSET 0U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_CONFIG_REG_P__DP_TX_PHY_SKEW_BYPASS_MASK 0x00000080U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_CONFIG_REG_P__DP_TX_PHY_SKEW_BYPASS_SHIFT 7U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_CONFIG_REG_P__DP_TX_PHY_SKEW_BYPASS_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_CONFIG_REG_P__DP_TX_PHY_SKEW_BYPASS_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_CONFIG_REG_P__DP_TX_PHY_SKEW_BYPASS_WOSET 0U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_CONFIG_REG_P__DP_TX_PHY_TRAINING_AUTOMATIC_MASK 0x00000100U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_CONFIG_REG_P__DP_TX_PHY_TRAINING_AUTOMATIC_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_CONFIG_REG_P__DP_TX_PHY_TRAINING_AUTOMATIC_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_CONFIG_REG_P__DP_TX_PHY_TRAINING_AUTOMATIC_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_CONFIG_REG_P__DP_TX_PHY_TRAINING_AUTOMATIC_WOSET 0U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_CONFIG_REG_P__DP_TX_PHY_LANE0_SKEW_MASK 0x00000E00U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_CONFIG_REG_P__DP_TX_PHY_LANE0_SKEW_SHIFT 9U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_CONFIG_REG_P__DP_TX_PHY_LANE0_SKEW_WIDTH 3U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_CONFIG_REG_P__DP_TX_PHY_LANE1_SKEW_MASK 0x00007000U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_CONFIG_REG_P__DP_TX_PHY_LANE1_SKEW_SHIFT 12U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_CONFIG_REG_P__DP_TX_PHY_LANE1_SKEW_WIDTH 3U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_CONFIG_REG_P__DP_TX_PHY_LANE2_SKEW_MASK 0x00038000U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_CONFIG_REG_P__DP_TX_PHY_LANE2_SKEW_SHIFT 15U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_CONFIG_REG_P__DP_TX_PHY_LANE2_SKEW_WIDTH 3U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_CONFIG_REG_P__DP_TX_PHY_LANE3_SKEW_MASK 0x001C0000U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_CONFIG_REG_P__DP_TX_PHY_LANE3_SKEW_SHIFT 18U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_CONFIG_REG_P__DP_TX_PHY_LANE3_SKEW_WIDTH 3U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_CONFIG_REG_P__DP_TX_PHY_10BIT_ENABLE_MASK 0x00200000U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_CONFIG_REG_P__DP_TX_PHY_10BIT_ENABLE_SHIFT 21U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_CONFIG_REG_P__DP_TX_PHY_10BIT_ENABLE_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_CONFIG_REG_P__DP_TX_PHY_10BIT_ENABLE_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_CONFIG_REG_P__DP_TX_PHY_10BIT_ENABLE_WOSET 0U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_CONFIG_REG_P__RESERVED_0_MASK 0xFFC00000U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_CONFIG_REG_P__RESERVED_0_SHIFT 22U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_CONFIG_REG_P__RESERVED_0_WIDTH 10U
+
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_SW_RESET_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_SW_RESET_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_SW_RESET_P__DP_TX_PHY_SW_RST_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_SW_RESET_P__DP_TX_PHY_SW_RST_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_SW_RESET_P__DP_TX_PHY_SW_RST_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_SW_RESET_P__DP_TX_PHY_SW_RST_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_SW_RESET_P__DP_TX_PHY_SW_RST_WOSET 0U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_SW_RESET_P__RESERVED_0_MASK 0xFFFFFFFEU
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_SW_RESET_P__RESERVED_0_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_SW_RESET_P__RESERVED_0_WIDTH 31U
+
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_SCRAMBLER_SEED_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_SCRAMBLER_SEED_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_SCRAMBLER_SEED_P__DP_TX_PHY_SCRAMBLER_SEED_MASK 0x0000FFFFU
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_SCRAMBLER_SEED_P__DP_TX_PHY_SCRAMBLER_SEED_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_SCRAMBLER_SEED_P__DP_TX_PHY_SCRAMBLER_SEED_WIDTH 16U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_SCRAMBLER_SEED_P__RESERVED_0_MASK 0xFFFF0000U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_SCRAMBLER_SEED_P__RESERVED_0_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_SCRAMBLER_SEED_P__RESERVED_0_WIDTH 16U
+
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_TRAINING_01_04_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_TRAINING_01_04_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_TRAINING_01_04_P__DP_TX_PHY_TRAINING_01_MASK 0x000000FFU
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_TRAINING_01_04_P__DP_TX_PHY_TRAINING_01_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_TRAINING_01_04_P__DP_TX_PHY_TRAINING_01_WIDTH 8U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_TRAINING_01_04_P__DP_TX_PHY_TRAINING_02_MASK 0x0000FF00U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_TRAINING_01_04_P__DP_TX_PHY_TRAINING_02_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_TRAINING_01_04_P__DP_TX_PHY_TRAINING_02_WIDTH 8U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_TRAINING_01_04_P__DP_TX_PHY_TRAINING_03_MASK 0x00FF0000U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_TRAINING_01_04_P__DP_TX_PHY_TRAINING_03_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_TRAINING_01_04_P__DP_TX_PHY_TRAINING_03_WIDTH 8U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_TRAINING_01_04_P__DP_TX_PHY_TRAINING_04_MASK 0xFF000000U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_TRAINING_01_04_P__DP_TX_PHY_TRAINING_04_SHIFT 24U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_TRAINING_01_04_P__DP_TX_PHY_TRAINING_04_WIDTH 8U
+
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_TRAINING_05_08_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_TRAINING_05_08_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_TRAINING_05_08_P__DP_TX_PHY_TRAINING_05_MASK 0x000000FFU
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_TRAINING_05_08_P__DP_TX_PHY_TRAINING_05_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_TRAINING_05_08_P__DP_TX_PHY_TRAINING_05_WIDTH 8U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_TRAINING_05_08_P__DP_TX_PHY_TRAINING_06_MASK 0x0000FF00U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_TRAINING_05_08_P__DP_TX_PHY_TRAINING_06_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_TRAINING_05_08_P__DP_TX_PHY_TRAINING_06_WIDTH 8U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_TRAINING_05_08_P__DP_TX_PHY_TRAINING_07_MASK 0x00FF0000U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_TRAINING_05_08_P__DP_TX_PHY_TRAINING_07_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_TRAINING_05_08_P__DP_TX_PHY_TRAINING_07_WIDTH 8U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_TRAINING_05_08_P__DP_TX_PHY_TRAINING_08_MASK 0xFF000000U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_TRAINING_05_08_P__DP_TX_PHY_TRAINING_08_SHIFT 24U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_TRAINING_05_08_P__DP_TX_PHY_TRAINING_08_WIDTH 8U
+
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_TRAINING_09_10_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_TRAINING_09_10_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_TRAINING_09_10_P__DP_TX_PHY_TRAINING_09_MASK 0x000000FFU
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_TRAINING_09_10_P__DP_TX_PHY_TRAINING_09_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_TRAINING_09_10_P__DP_TX_PHY_TRAINING_09_WIDTH 8U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_TRAINING_09_10_P__DP_TX_PHY_TRAINING_10_MASK 0x0000FF00U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_TRAINING_09_10_P__DP_TX_PHY_TRAINING_10_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_TRAINING_09_10_P__DP_TX_PHY_TRAINING_10_WIDTH 8U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_TRAINING_09_10_P__RESERVED_0_MASK 0xFFFF0000U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_TRAINING_09_10_P__RESERVED_0_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_TRAINING_09_10_P__RESERVED_0_WIDTH 16U
+
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_SR_INTERVAL_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_SR_INTERVAL_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_SR_INTERVAL_P__DP_TX_PHY_SR_INTERVAL_MASK 0x0000FFFFU
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_SR_INTERVAL_P__DP_TX_PHY_SR_INTERVAL_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_SR_INTERVAL_P__DP_TX_PHY_SR_INTERVAL_WIDTH 16U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_SR_INTERVAL_P__RESERVED_0_MASK 0xFFFF0000U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_SR_INTERVAL_P__RESERVED_0_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_SR_INTERVAL_P__RESERVED_0_WIDTH 16U
+
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_FEC_TEST_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_FEC_TEST_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_FEC_TEST_P__FEC_L01_DATA_BYPASS_TEST_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_FEC_TEST_P__FEC_L01_DATA_BYPASS_TEST_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_FEC_TEST_P__FEC_L01_DATA_BYPASS_TEST_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_FEC_TEST_P__FEC_L01_DATA_BYPASS_TEST_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_FEC_TEST_P__FEC_L01_DATA_BYPASS_TEST_WOSET 0U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_FEC_TEST_P__FEC_L01_PARITY_GEN_TEST_MASK 0x00000002U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_FEC_TEST_P__FEC_L01_PARITY_GEN_TEST_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_FEC_TEST_P__FEC_L01_PARITY_GEN_TEST_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_FEC_TEST_P__FEC_L01_PARITY_GEN_TEST_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_FEC_TEST_P__FEC_L01_PARITY_GEN_TEST_WOSET 0U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_FEC_TEST_P__FEC_L01_PARITY_ENC_TEST_MASK 0x00000004U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_FEC_TEST_P__FEC_L01_PARITY_ENC_TEST_SHIFT 2U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_FEC_TEST_P__FEC_L01_PARITY_ENC_TEST_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_FEC_TEST_P__FEC_L01_PARITY_ENC_TEST_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_FEC_TEST_P__FEC_L01_PARITY_ENC_TEST_WOSET 0U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_FEC_TEST_P__FEC_L01_8B10B_TEST_MASK 0x00000008U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_FEC_TEST_P__FEC_L01_8B10B_TEST_SHIFT 3U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_FEC_TEST_P__FEC_L01_8B10B_TEST_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_FEC_TEST_P__FEC_L01_8B10B_TEST_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_FEC_TEST_P__FEC_L01_8B10B_TEST_WOSET 0U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_FEC_TEST_P__FEC_L23_DATA_BYPASS_TEST_MASK 0x00000010U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_FEC_TEST_P__FEC_L23_DATA_BYPASS_TEST_SHIFT 4U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_FEC_TEST_P__FEC_L23_DATA_BYPASS_TEST_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_FEC_TEST_P__FEC_L23_DATA_BYPASS_TEST_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_FEC_TEST_P__FEC_L23_DATA_BYPASS_TEST_WOSET 0U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_FEC_TEST_P__FEC_L23_PARITY_GEN_TEST_MASK 0x00000020U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_FEC_TEST_P__FEC_L23_PARITY_GEN_TEST_SHIFT 5U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_FEC_TEST_P__FEC_L23_PARITY_GEN_TEST_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_FEC_TEST_P__FEC_L23_PARITY_GEN_TEST_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_FEC_TEST_P__FEC_L23_PARITY_GEN_TEST_WOSET 0U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_FEC_TEST_P__FEC_L23_PARITY_ENC_TEST_MASK 0x00000040U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_FEC_TEST_P__FEC_L23_PARITY_ENC_TEST_SHIFT 6U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_FEC_TEST_P__FEC_L23_PARITY_ENC_TEST_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_FEC_TEST_P__FEC_L23_PARITY_ENC_TEST_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_FEC_TEST_P__FEC_L23_PARITY_ENC_TEST_WOSET 0U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_FEC_TEST_P__FEC_L23_8B10B_TEST_MASK 0x00000080U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_FEC_TEST_P__FEC_L23_8B10B_TEST_SHIFT 7U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_FEC_TEST_P__FEC_L23_8B10B_TEST_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_FEC_TEST_P__FEC_L23_8B10B_TEST_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_FEC_TEST_P__FEC_L23_8B10B_TEST_WOSET 0U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_FEC_TEST_P__FEC_L01_EXT_DIAG_TEST_EN_MASK 0x00000100U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_FEC_TEST_P__FEC_L01_EXT_DIAG_TEST_EN_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_FEC_TEST_P__FEC_L01_EXT_DIAG_TEST_EN_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_FEC_TEST_P__FEC_L01_EXT_DIAG_TEST_EN_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_FEC_TEST_P__FEC_L01_EXT_DIAG_TEST_EN_WOSET 0U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_FEC_TEST_P__FEC_L23_EXT_DIAG_TEST_EN_MASK 0x00000200U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_FEC_TEST_P__FEC_L23_EXT_DIAG_TEST_EN_SHIFT 9U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_FEC_TEST_P__FEC_L23_EXT_DIAG_TEST_EN_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_FEC_TEST_P__FEC_L23_EXT_DIAG_TEST_EN_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_FEC_TEST_P__FEC_L23_EXT_DIAG_TEST_EN_WOSET 0U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_FEC_TEST_P__RESERVED_0_MASK 0xFFFFFC00U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_FEC_TEST_P__RESERVED_0_SHIFT 10U
+#define MHDP__MHDP_APB_REGS__DP_TX_PHY_FEC_TEST_P__RESERVED_0_WIDTH 22U
+
+#define MHDP__MHDP_APB_REGS__HPD_IRQ_DET_MIN_TIMER_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__HPD_IRQ_DET_MIN_TIMER_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__HPD_IRQ_DET_MIN_TIMER_P__HPD_IRQ_DET_MIN_TIMER_MASK 0x00FFFFFFU
+#define MHDP__MHDP_APB_REGS__HPD_IRQ_DET_MIN_TIMER_P__HPD_IRQ_DET_MIN_TIMER_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__HPD_IRQ_DET_MIN_TIMER_P__HPD_IRQ_DET_MIN_TIMER_WIDTH 24U
+#define MHDP__MHDP_APB_REGS__HPD_IRQ_DET_MIN_TIMER_P__RESERVED_0_MASK 0xFF000000U
+#define MHDP__MHDP_APB_REGS__HPD_IRQ_DET_MIN_TIMER_P__RESERVED_0_SHIFT 24U
+#define MHDP__MHDP_APB_REGS__HPD_IRQ_DET_MIN_TIMER_P__RESERVED_0_WIDTH 8U
+
+#define MHDP__MHDP_APB_REGS__HPD_IRQ_DET_MAX_TIMER_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__HPD_IRQ_DET_MAX_TIMER_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__HPD_IRQ_DET_MAX_TIMER_P__HPD_IRQ_DET_MAX_TIMER_MASK 0x00FFFFFFU
+#define MHDP__MHDP_APB_REGS__HPD_IRQ_DET_MAX_TIMER_P__HPD_IRQ_DET_MAX_TIMER_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__HPD_IRQ_DET_MAX_TIMER_P__HPD_IRQ_DET_MAX_TIMER_WIDTH 24U
+#define MHDP__MHDP_APB_REGS__HPD_IRQ_DET_MAX_TIMER_P__RESERVED_0_MASK 0xFF000000U
+#define MHDP__MHDP_APB_REGS__HPD_IRQ_DET_MAX_TIMER_P__RESERVED_0_SHIFT 24U
+#define MHDP__MHDP_APB_REGS__HPD_IRQ_DET_MAX_TIMER_P__RESERVED_0_WIDTH 8U
+
+#define MHDP__MHDP_APB_REGS__HPD_UNPLGED_DET_MIN_TIMER_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__HPD_UNPLGED_DET_MIN_TIMER_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__HPD_UNPLGED_DET_MIN_TIMER_P__HPD_UNPLGED_DET_MIN_TIMER_MASK 0x00FFFFFFU
+#define MHDP__MHDP_APB_REGS__HPD_UNPLGED_DET_MIN_TIMER_P__HPD_UNPLGED_DET_MIN_TIMER_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__HPD_UNPLGED_DET_MIN_TIMER_P__HPD_UNPLGED_DET_MIN_TIMER_WIDTH 24U
+#define MHDP__MHDP_APB_REGS__HPD_UNPLGED_DET_MIN_TIMER_P__RESERVED_0_MASK 0xFF000000U
+#define MHDP__MHDP_APB_REGS__HPD_UNPLGED_DET_MIN_TIMER_P__RESERVED_0_SHIFT 24U
+#define MHDP__MHDP_APB_REGS__HPD_UNPLGED_DET_MIN_TIMER_P__RESERVED_0_WIDTH 8U
+
+#define MHDP__MHDP_APB_REGS__HPD_STABLE_TIMER_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__HPD_STABLE_TIMER_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__HPD_STABLE_TIMER_P__HPD_STABLE_TIMER_MASK 0x00FFFFFFU
+#define MHDP__MHDP_APB_REGS__HPD_STABLE_TIMER_P__HPD_STABLE_TIMER_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__HPD_STABLE_TIMER_P__HPD_STABLE_TIMER_WIDTH 24U
+#define MHDP__MHDP_APB_REGS__HPD_STABLE_TIMER_P__RESERVED_0_MASK 0xFF000000U
+#define MHDP__MHDP_APB_REGS__HPD_STABLE_TIMER_P__RESERVED_0_SHIFT 24U
+#define MHDP__MHDP_APB_REGS__HPD_STABLE_TIMER_P__RESERVED_0_WIDTH 8U
+
+#define MHDP__MHDP_APB_REGS__HPD_FILTER_TIMER_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__HPD_FILTER_TIMER_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__HPD_FILTER_TIMER_P__HPD_FILTER_TIMER_MASK 0x00FFFFFFU
+#define MHDP__MHDP_APB_REGS__HPD_FILTER_TIMER_P__HPD_FILTER_TIMER_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__HPD_FILTER_TIMER_P__HPD_FILTER_TIMER_WIDTH 24U
+#define MHDP__MHDP_APB_REGS__HPD_FILTER_TIMER_P__RESERVED_0_MASK 0xFF000000U
+#define MHDP__MHDP_APB_REGS__HPD_FILTER_TIMER_P__RESERVED_0_SHIFT 24U
+#define MHDP__MHDP_APB_REGS__HPD_FILTER_TIMER_P__RESERVED_0_WIDTH 8U
+
+#define MHDP__MHDP_APB_REGS__HPD_DBNC_TIMER_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__HPD_DBNC_TIMER_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__HPD_DBNC_TIMER_P__HPD_DEBOUNCE_TIMER_MASK 0x00FFFFFFU
+#define MHDP__MHDP_APB_REGS__HPD_DBNC_TIMER_P__HPD_DEBOUNCE_TIMER_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__HPD_DBNC_TIMER_P__HPD_DEBOUNCE_TIMER_WIDTH 24U
+#define MHDP__MHDP_APB_REGS__HPD_DBNC_TIMER_P__SEL_HPDTX_DB_22_MASK 0x01000000U
+#define MHDP__MHDP_APB_REGS__HPD_DBNC_TIMER_P__SEL_HPDTX_DB_22_SHIFT 24U
+#define MHDP__MHDP_APB_REGS__HPD_DBNC_TIMER_P__SEL_HPDTX_DB_22_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__HPD_DBNC_TIMER_P__SEL_HPDTX_DB_22_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__HPD_DBNC_TIMER_P__SEL_HPDTX_DB_22_WOSET 0U
+#define MHDP__MHDP_APB_REGS__HPD_DBNC_TIMER_P__RESERVED_0_MASK 0xFE000000U
+#define MHDP__MHDP_APB_REGS__HPD_DBNC_TIMER_P__RESERVED_0_SHIFT 25U
+#define MHDP__MHDP_APB_REGS__HPD_DBNC_TIMER_P__RESERVED_0_WIDTH 7U
+
+#define MHDP__MHDP_APB_REGS__HPD_EVENT_MASK_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__HPD_EVENT_MASK_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__HPD_EVENT_MASK_P__HPD_EVENTS_MASK_MASK 0x0000000FU
+#define MHDP__MHDP_APB_REGS__HPD_EVENT_MASK_P__HPD_EVENTS_MASK_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__HPD_EVENT_MASK_P__HPD_EVENTS_MASK_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__HPD_EVENT_MASK_P__RESERVED_0_MASK 0xFFFFFFF0U
+#define MHDP__MHDP_APB_REGS__HPD_EVENT_MASK_P__RESERVED_0_SHIFT 4U
+#define MHDP__MHDP_APB_REGS__HPD_EVENT_MASK_P__RESERVED_0_WIDTH 28U
+
+#define MHDP__MHDP_APB_REGS__HPD_EVENT_DET_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__HPD_EVENT_DET_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__HPD_EVENT_DET_P_RCLR_MASK 0x0000001FU
+#define MHDP__MHDP_APB_REGS__HPD_EVENT_DET_P__HPD_IRQ_DET_EVENT_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__HPD_EVENT_DET_P__HPD_IRQ_DET_EVENT_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__HPD_EVENT_DET_P__HPD_IRQ_DET_EVENT_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__HPD_EVENT_DET_P__HPD_IRQ_DET_EVENT_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__HPD_EVENT_DET_P__HPD_IRQ_DET_EVENT_WOSET 0U
+#define MHDP__MHDP_APB_REGS__HPD_EVENT_DET_P__HPD_STABLE_MASK 0x00000002U
+#define MHDP__MHDP_APB_REGS__HPD_EVENT_DET_P__HPD_STABLE_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__HPD_EVENT_DET_P__HPD_STABLE_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__HPD_EVENT_DET_P__HPD_STABLE_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__HPD_EVENT_DET_P__HPD_STABLE_WOSET 0U
+#define MHDP__MHDP_APB_REGS__HPD_EVENT_DET_P__HPD_UNPLUGGED_DET_ACLK_MASK 0x00000004U
+#define MHDP__MHDP_APB_REGS__HPD_EVENT_DET_P__HPD_UNPLUGGED_DET_ACLK_SHIFT 2U
+#define MHDP__MHDP_APB_REGS__HPD_EVENT_DET_P__HPD_UNPLUGGED_DET_ACLK_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__HPD_EVENT_DET_P__HPD_UNPLUGGED_DET_ACLK_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__HPD_EVENT_DET_P__HPD_UNPLUGGED_DET_ACLK_WOSET 0U
+#define MHDP__MHDP_APB_REGS__HPD_EVENT_DET_P__HPD_RE_PLGED_DET_EVENT_MASK 0x00000008U
+#define MHDP__MHDP_APB_REGS__HPD_EVENT_DET_P__HPD_RE_PLGED_DET_EVENT_SHIFT 3U
+#define MHDP__MHDP_APB_REGS__HPD_EVENT_DET_P__HPD_RE_PLGED_DET_EVENT_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__HPD_EVENT_DET_P__HPD_RE_PLGED_DET_EVENT_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__HPD_EVENT_DET_P__HPD_RE_PLGED_DET_EVENT_WOSET 0U
+#define MHDP__MHDP_APB_REGS__HPD_EVENT_DET_P__HPD_IN_SYNC_MASK 0x00000010U
+#define MHDP__MHDP_APB_REGS__HPD_EVENT_DET_P__HPD_IN_SYNC_SHIFT 4U
+#define MHDP__MHDP_APB_REGS__HPD_EVENT_DET_P__HPD_IN_SYNC_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__HPD_EVENT_DET_P__HPD_IN_SYNC_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__HPD_EVENT_DET_P__HPD_IN_SYNC_WOSET 0U
+#define MHDP__MHDP_APB_REGS__HPD_EVENT_DET_P__RESERVED_0_MASK 0xFFFFFFE0U
+#define MHDP__MHDP_APB_REGS__HPD_EVENT_DET_P__RESERVED_0_SHIFT 5U
+#define MHDP__MHDP_APB_REGS__HPD_EVENT_DET_P__RESERVED_0_WIDTH 27U
+
+#define MHDP__MHDP_APB_REGS__DP_FRAMER_GLOBAL_CONFIG_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DP_FRAMER_GLOBAL_CONFIG_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DP_FRAMER_GLOBAL_CONFIG_P__NUM_LANES_MASK 0x00000003U
+#define MHDP__MHDP_APB_REGS__DP_FRAMER_GLOBAL_CONFIG_P__NUM_LANES_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__DP_FRAMER_GLOBAL_CONFIG_P__NUM_LANES_WIDTH 2U
+#define MHDP__MHDP_APB_REGS__DP_FRAMER_GLOBAL_CONFIG_P__MST_SST_MASK 0x00000004U
+#define MHDP__MHDP_APB_REGS__DP_FRAMER_GLOBAL_CONFIG_P__MST_SST_SHIFT 2U
+#define MHDP__MHDP_APB_REGS__DP_FRAMER_GLOBAL_CONFIG_P__MST_SST_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__DP_FRAMER_GLOBAL_CONFIG_P__MST_SST_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__DP_FRAMER_GLOBAL_CONFIG_P__MST_SST_WOSET 0U
+#define MHDP__MHDP_APB_REGS__DP_FRAMER_GLOBAL_CONFIG_P__GLOBAL_EN_MASK 0x00000008U
+#define MHDP__MHDP_APB_REGS__DP_FRAMER_GLOBAL_CONFIG_P__GLOBAL_EN_SHIFT 3U
+#define MHDP__MHDP_APB_REGS__DP_FRAMER_GLOBAL_CONFIG_P__GLOBAL_EN_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__DP_FRAMER_GLOBAL_CONFIG_P__GLOBAL_EN_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__DP_FRAMER_GLOBAL_CONFIG_P__GLOBAL_EN_WOSET 0U
+#define MHDP__MHDP_APB_REGS__DP_FRAMER_GLOBAL_CONFIG_P__RESERVED_4_MASK 0x00000010U
+#define MHDP__MHDP_APB_REGS__DP_FRAMER_GLOBAL_CONFIG_P__RESERVED_4_SHIFT 4U
+#define MHDP__MHDP_APB_REGS__DP_FRAMER_GLOBAL_CONFIG_P__RESERVED_4_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__DP_FRAMER_GLOBAL_CONFIG_P__RESERVED_4_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__DP_FRAMER_GLOBAL_CONFIG_P__RESERVED_4_WOSET 0U
+#define MHDP__MHDP_APB_REGS__DP_FRAMER_GLOBAL_CONFIG_P__NO_VIDEO_MASK 0x00000020U
+#define MHDP__MHDP_APB_REGS__DP_FRAMER_GLOBAL_CONFIG_P__NO_VIDEO_SHIFT 5U
+#define MHDP__MHDP_APB_REGS__DP_FRAMER_GLOBAL_CONFIG_P__NO_VIDEO_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__DP_FRAMER_GLOBAL_CONFIG_P__NO_VIDEO_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__DP_FRAMER_GLOBAL_CONFIG_P__NO_VIDEO_WOSET 0U
+#define MHDP__MHDP_APB_REGS__DP_FRAMER_GLOBAL_CONFIG_P__ENC_RST_DIS_MASK 0x00000040U
+#define MHDP__MHDP_APB_REGS__DP_FRAMER_GLOBAL_CONFIG_P__ENC_RST_DIS_SHIFT 6U
+#define MHDP__MHDP_APB_REGS__DP_FRAMER_GLOBAL_CONFIG_P__ENC_RST_DIS_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__DP_FRAMER_GLOBAL_CONFIG_P__ENC_RST_DIS_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__DP_FRAMER_GLOBAL_CONFIG_P__ENC_RST_DIS_WOSET 0U
+#define MHDP__MHDP_APB_REGS__DP_FRAMER_GLOBAL_CONFIG_P__WR_VHSYNC_FALL_MASK 0x00000080U
+#define MHDP__MHDP_APB_REGS__DP_FRAMER_GLOBAL_CONFIG_P__WR_VHSYNC_FALL_SHIFT 7U
+#define MHDP__MHDP_APB_REGS__DP_FRAMER_GLOBAL_CONFIG_P__WR_VHSYNC_FALL_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__DP_FRAMER_GLOBAL_CONFIG_P__WR_VHSYNC_FALL_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__DP_FRAMER_GLOBAL_CONFIG_P__WR_VHSYNC_FALL_WOSET 0U
+#define MHDP__MHDP_APB_REGS__DP_FRAMER_GLOBAL_CONFIG_P__RESERVED_0_MASK 0xFFFFFF00U
+#define MHDP__MHDP_APB_REGS__DP_FRAMER_GLOBAL_CONFIG_P__RESERVED_0_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__DP_FRAMER_GLOBAL_CONFIG_P__RESERVED_0_WIDTH 24U
+
+#define MHDP__MHDP_APB_REGS__DP_SW_RESET_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DP_SW_RESET_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DP_SW_RESET_P__SW_RST_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__DP_SW_RESET_P__SW_RST_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__DP_SW_RESET_P__SW_RST_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__DP_SW_RESET_P__SW_RST_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__DP_SW_RESET_P__SW_RST_WOSET 0U
+#define MHDP__MHDP_APB_REGS__DP_SW_RESET_P__RESERVED_0_MASK 0xFFFFFFFEU
+#define MHDP__MHDP_APB_REGS__DP_SW_RESET_P__RESERVED_0_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__DP_SW_RESET_P__RESERVED_0_WIDTH 31U
+
+#define MHDP__MHDP_APB_REGS__DP_FRAMER_TU_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DP_FRAMER_TU_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DP_FRAMER_TU_P__TU_VALID_SYMBOLS_MASK 0x0000003FU
+#define MHDP__MHDP_APB_REGS__DP_FRAMER_TU_P__TU_VALID_SYMBOLS_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__DP_FRAMER_TU_P__TU_VALID_SYMBOLS_WIDTH 6U
+#define MHDP__MHDP_APB_REGS__DP_FRAMER_TU_P__TU_SST_FAST_DRAIN_MASK 0x00000040U
+#define MHDP__MHDP_APB_REGS__DP_FRAMER_TU_P__TU_SST_FAST_DRAIN_SHIFT 6U
+#define MHDP__MHDP_APB_REGS__DP_FRAMER_TU_P__TU_SST_FAST_DRAIN_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__DP_FRAMER_TU_P__TU_SST_FAST_DRAIN_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__DP_FRAMER_TU_P__TU_SST_FAST_DRAIN_WOSET 0U
+#define MHDP__MHDP_APB_REGS__DP_FRAMER_TU_P__RESERVED_0_MASK 0x00000080U
+#define MHDP__MHDP_APB_REGS__DP_FRAMER_TU_P__RESERVED_0_SHIFT 7U
+#define MHDP__MHDP_APB_REGS__DP_FRAMER_TU_P__RESERVED_0_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__DP_FRAMER_TU_P__RESERVED_0_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__DP_FRAMER_TU_P__RESERVED_0_WOSET 0U
+#define MHDP__MHDP_APB_REGS__DP_FRAMER_TU_P__TU_SIZE_MASK 0x00007F00U
+#define MHDP__MHDP_APB_REGS__DP_FRAMER_TU_P__TU_SIZE_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__DP_FRAMER_TU_P__TU_SIZE_WIDTH 7U
+#define MHDP__MHDP_APB_REGS__DP_FRAMER_TU_P__TU_CNT_RST_EN_MASK 0x00008000U
+#define MHDP__MHDP_APB_REGS__DP_FRAMER_TU_P__TU_CNT_RST_EN_SHIFT 15U
+#define MHDP__MHDP_APB_REGS__DP_FRAMER_TU_P__TU_CNT_RST_EN_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__DP_FRAMER_TU_P__TU_CNT_RST_EN_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__DP_FRAMER_TU_P__TU_CNT_RST_EN_WOSET 0U
+#define MHDP__MHDP_APB_REGS__DP_FRAMER_TU_P__BS_SR_REPLACE_POSITION_MASK 0x01FF0000U
+#define MHDP__MHDP_APB_REGS__DP_FRAMER_TU_P__BS_SR_REPLACE_POSITION_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__DP_FRAMER_TU_P__BS_SR_REPLACE_POSITION_WIDTH 9U
+#define MHDP__MHDP_APB_REGS__DP_FRAMER_TU_P__RESERVED_1_MASK 0xFE000000U
+#define MHDP__MHDP_APB_REGS__DP_FRAMER_TU_P__RESERVED_1_SHIFT 25U
+#define MHDP__MHDP_APB_REGS__DP_FRAMER_TU_P__RESERVED_1_WIDTH 7U
+
+#define MHDP__MHDP_APB_REGS__DP_FRAMER_BS_SR_INTRVL_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DP_FRAMER_BS_SR_INTRVL_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DP_FRAMER_BS_SR_INTRVL_P__BS_SR_INTERVAL_MASK 0x000003FFU
+#define MHDP__MHDP_APB_REGS__DP_FRAMER_BS_SR_INTRVL_P__BS_SR_INTERVAL_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__DP_FRAMER_BS_SR_INTRVL_P__BS_SR_INTERVAL_WIDTH 10U
+#define MHDP__MHDP_APB_REGS__DP_FRAMER_BS_SR_INTRVL_P__RESERVED_0_MASK 0xFFFFFC00U
+#define MHDP__MHDP_APB_REGS__DP_FRAMER_BS_SR_INTRVL_P__RESERVED_0_SHIFT 10U
+#define MHDP__MHDP_APB_REGS__DP_FRAMER_BS_SR_INTRVL_P__RESERVED_0_WIDTH 22U
+
+#define MHDP__MHDP_APB_REGS__DP_MTPH_ECF_SLOTS_31_0_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DP_MTPH_ECF_SLOTS_31_0_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DP_MTPH_ECF_SLOTS_31_0_P__TSLOT_ENCRYPT31_0_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DP_MTPH_ECF_SLOTS_31_0_P__TSLOT_ENCRYPT31_0_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__DP_MTPH_ECF_SLOTS_31_0_P__TSLOT_ENCRYPT31_0_WIDTH 32U
+
+#define MHDP__MHDP_APB_REGS__DP_MTPH_ECF_SLOTS_63_32_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DP_MTPH_ECF_SLOTS_63_32_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DP_MTPH_ECF_SLOTS_63_32_P__TSLOT_ENCRYPT63_32_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DP_MTPH_ECF_SLOTS_63_32_P__TSLOT_ENCRYPT63_32_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__DP_MTPH_ECF_SLOTS_63_32_P__TSLOT_ENCRYPT63_32_WIDTH 32U
+
+#define MHDP__MHDP_APB_REGS__DP_MTPH_LVP_SYMBOL_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DP_MTPH_LVP_SYMBOL_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DP_MTPH_LVP_SYMBOL_P__MTPH_LVP_SYM_MASK 0x0000FFFFU
+#define MHDP__MHDP_APB_REGS__DP_MTPH_LVP_SYMBOL_P__MTPH_LVP_SYM_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__DP_MTPH_LVP_SYMBOL_P__MTPH_LVP_SYM_WIDTH 16U
+#define MHDP__MHDP_APB_REGS__DP_MTPH_LVP_SYMBOL_P__RESERVED_0_MASK 0xFFFF0000U
+#define MHDP__MHDP_APB_REGS__DP_MTPH_LVP_SYMBOL_P__RESERVED_0_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__DP_MTPH_LVP_SYMBOL_P__RESERVED_0_WIDTH 16U
+
+#define MHDP__MHDP_APB_REGS__DP_MTPH_CONTROL_P_READ_MASK 0xFFFFFFFDU
+#define MHDP__MHDP_APB_REGS__DP_MTPH_CONTROL_P_WRITE_MASK 0xFFFFFFFDU
+#define MHDP__MHDP_APB_REGS__DP_MTPH_CONTROL_P__MTPH_ECF_EN_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__DP_MTPH_CONTROL_P__MTPH_ECF_EN_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__DP_MTPH_CONTROL_P__MTPH_ECF_EN_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__DP_MTPH_CONTROL_P__MTPH_ECF_EN_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__DP_MTPH_CONTROL_P__MTPH_ECF_EN_WOSET 0U
+#define MHDP__MHDP_APB_REGS__DP_MTPH_CONTROL_P__MTPH_ACT_EN_MASK 0x00000002U
+#define MHDP__MHDP_APB_REGS__DP_MTPH_CONTROL_P__MTPH_ACT_EN_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__DP_MTPH_CONTROL_P__MTPH_ACT_EN_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__DP_MTPH_CONTROL_P__MTPH_ACT_EN_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__DP_MTPH_CONTROL_P__MTPH_ACT_EN_WOSET 0U
+#define MHDP__MHDP_APB_REGS__DP_MTPH_CONTROL_P__MTPH_LVP_EN_MASK 0x00000004U
+#define MHDP__MHDP_APB_REGS__DP_MTPH_CONTROL_P__MTPH_LVP_EN_SHIFT 2U
+#define MHDP__MHDP_APB_REGS__DP_MTPH_CONTROL_P__MTPH_LVP_EN_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__DP_MTPH_CONTROL_P__MTPH_LVP_EN_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__DP_MTPH_CONTROL_P__MTPH_LVP_EN_WOSET 0U
+#define MHDP__MHDP_APB_REGS__DP_MTPH_CONTROL_P__RESERVED_0_MASK 0xFFFFFFF8U
+#define MHDP__MHDP_APB_REGS__DP_MTPH_CONTROL_P__RESERVED_0_SHIFT 3U
+#define MHDP__MHDP_APB_REGS__DP_MTPH_CONTROL_P__RESERVED_0_WIDTH 29U
+
+#define MHDP__MHDP_APB_REGS__DP_MTPH_STATUS_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DP_MTPH_STATUS_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DP_MTPH_STATUS_P__MTPH_ACT_STATUS_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__DP_MTPH_STATUS_P__MTPH_ACT_STATUS_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__DP_MTPH_STATUS_P__MTPH_ACT_STATUS_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__DP_MTPH_STATUS_P__MTPH_ACT_STATUS_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__DP_MTPH_STATUS_P__MTPH_ACT_STATUS_WOSET 0U
+#define MHDP__MHDP_APB_REGS__DP_MTPH_STATUS_P__RESERVED_0_MASK 0xFFFFFFFEU
+#define MHDP__MHDP_APB_REGS__DP_MTPH_STATUS_P__RESERVED_0_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__DP_MTPH_STATUS_P__RESERVED_0_WIDTH 31U
+
+#define MHDP__MHDP_APB_REGS__DPTX_LANE_EN_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DPTX_LANE_EN_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DPTX_LANE_EN_P__DPTX_LANE_ENABLE_MASK 0x0000000FU
+#define MHDP__MHDP_APB_REGS__DPTX_LANE_EN_P__DPTX_LANE_ENABLE_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__DPTX_LANE_EN_P__DPTX_LANE_ENABLE_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__DPTX_LANE_EN_P__RESERVED_0_MASK 0xFFFFFFF0U
+#define MHDP__MHDP_APB_REGS__DPTX_LANE_EN_P__RESERVED_0_SHIFT 4U
+#define MHDP__MHDP_APB_REGS__DPTX_LANE_EN_P__RESERVED_0_WIDTH 28U
+
+#define MHDP__MHDP_APB_REGS__DPTX_ENHNCD_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DPTX_ENHNCD_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DPTX_ENHNCD_P__DPTX_ENHANCED_MODE_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__DPTX_ENHNCD_P__DPTX_ENHANCED_MODE_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__DPTX_ENHNCD_P__DPTX_ENHANCED_MODE_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__DPTX_ENHNCD_P__DPTX_ENHANCED_MODE_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__DPTX_ENHNCD_P__DPTX_ENHANCED_MODE_WOSET 0U
+#define MHDP__MHDP_APB_REGS__DPTX_ENHNCD_P__RESERVED_0_MASK 0xFFFFFFFEU
+#define MHDP__MHDP_APB_REGS__DPTX_ENHNCD_P__RESERVED_0_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__DPTX_ENHNCD_P__RESERVED_0_WIDTH 31U
+
+#define MHDP__MHDP_APB_REGS__DPTX_INT_MASK_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DPTX_INT_MASK_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DPTX_INT_MASK_P__HPD_SRC_INT_MASK_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__DPTX_INT_MASK_P__HPD_SRC_INT_MASK_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__DPTX_INT_MASK_P__HPD_SRC_INT_MASK_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__DPTX_INT_MASK_P__HPD_SRC_INT_MASK_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__DPTX_INT_MASK_P__HPD_SRC_INT_MASK_WOSET 0U
+#define MHDP__MHDP_APB_REGS__DPTX_INT_MASK_P__FRAMER_SRC_INT_MASK_MASK 0x00000002U
+#define MHDP__MHDP_APB_REGS__DPTX_INT_MASK_P__FRAMER_SRC_INT_MASK_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__DPTX_INT_MASK_P__FRAMER_SRC_INT_MASK_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__DPTX_INT_MASK_P__FRAMER_SRC_INT_MASK_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__DPTX_INT_MASK_P__FRAMER_SRC_INT_MASK_WOSET 0U
+#define MHDP__MHDP_APB_REGS__DPTX_INT_MASK_P__RESERVED_0_MASK 0xFFFFFFFCU
+#define MHDP__MHDP_APB_REGS__DPTX_INT_MASK_P__RESERVED_0_SHIFT 2U
+#define MHDP__MHDP_APB_REGS__DPTX_INT_MASK_P__RESERVED_0_WIDTH 30U
+
+#define MHDP__MHDP_APB_REGS__DPTX_INT_STATUS_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DPTX_INT_STATUS_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DPTX_INT_STATUS_P__HPD_SRC_INT_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__DPTX_INT_STATUS_P__HPD_SRC_INT_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__DPTX_INT_STATUS_P__HPD_SRC_INT_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__DPTX_INT_STATUS_P__HPD_SRC_INT_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__DPTX_INT_STATUS_P__HPD_SRC_INT_WOSET 0U
+#define MHDP__MHDP_APB_REGS__DPTX_INT_STATUS_P__FRAMER_SRC_INT_MASK 0x00000002U
+#define MHDP__MHDP_APB_REGS__DPTX_INT_STATUS_P__FRAMER_SRC_INT_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__DPTX_INT_STATUS_P__FRAMER_SRC_INT_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__DPTX_INT_STATUS_P__FRAMER_SRC_INT_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__DPTX_INT_STATUS_P__FRAMER_SRC_INT_WOSET 0U
+#define MHDP__MHDP_APB_REGS__DPTX_INT_STATUS_P__RESERVED_0_MASK 0xFFFFFFFCU
+#define MHDP__MHDP_APB_REGS__DPTX_INT_STATUS_P__RESERVED_0_SHIFT 2U
+#define MHDP__MHDP_APB_REGS__DPTX_INT_STATUS_P__RESERVED_0_WIDTH 30U
+
+#define MHDP__MHDP_APB_REGS__DPTX_FEC_CTRL_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DPTX_FEC_CTRL_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DPTX_FEC_CTRL_P__CFG_FEC_EN_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__DPTX_FEC_CTRL_P__CFG_FEC_EN_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__DPTX_FEC_CTRL_P__CFG_FEC_EN_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__DPTX_FEC_CTRL_P__CFG_FEC_EN_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__DPTX_FEC_CTRL_P__CFG_FEC_EN_WOSET 0U
+#define MHDP__MHDP_APB_REGS__DPTX_FEC_CTRL_P__CFG_FEC_READY_MASK 0x00000002U
+#define MHDP__MHDP_APB_REGS__DPTX_FEC_CTRL_P__CFG_FEC_READY_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__DPTX_FEC_CTRL_P__CFG_FEC_READY_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__DPTX_FEC_CTRL_P__CFG_FEC_READY_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__DPTX_FEC_CTRL_P__CFG_FEC_READY_WOSET 0U
+#define MHDP__MHDP_APB_REGS__DPTX_FEC_CTRL_P__RESERVED_0_MASK 0xFFFFFFFCU
+#define MHDP__MHDP_APB_REGS__DPTX_FEC_CTRL_P__RESERVED_0_SHIFT 2U
+#define MHDP__MHDP_APB_REGS__DPTX_FEC_CTRL_P__RESERVED_0_WIDTH 30U
+
+#define MHDP__MHDP_APB_REGS__DPTX_FEC_STATUS_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DPTX_FEC_STATUS_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DPTX_FEC_STATUS_P__FEC_BUSY_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__DPTX_FEC_STATUS_P__FEC_BUSY_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__DPTX_FEC_STATUS_P__FEC_BUSY_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__DPTX_FEC_STATUS_P__FEC_BUSY_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__DPTX_FEC_STATUS_P__FEC_BUSY_WOSET 0U
+#define MHDP__MHDP_APB_REGS__DPTX_FEC_STATUS_P__FEC_FSM_STATUS_MASK 0x0000001EU
+#define MHDP__MHDP_APB_REGS__DPTX_FEC_STATUS_P__FEC_FSM_STATUS_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__DPTX_FEC_STATUS_P__FEC_FSM_STATUS_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__DPTX_FEC_STATUS_P__RESERVED_0_MASK 0xFFFFFFE0U
+#define MHDP__MHDP_APB_REGS__DPTX_FEC_STATUS_P__RESERVED_0_SHIFT 5U
+#define MHDP__MHDP_APB_REGS__DPTX_FEC_STATUS_P__RESERVED_0_WIDTH 27U
+
+#define MHDP__MHDP_APB_REGS__HDCP_DP_STATUS_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__HDCP_DP_STATUS_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__HDCP_DP_STATUS_P__HDCP_DP_AUTHENTICATED_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_STATUS_P__HDCP_DP_AUTHENTICATED_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_STATUS_P__HDCP_DP_AUTHENTICATED_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_STATUS_P__HDCP_DP_AUTHENTICATED_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_STATUS_P__HDCP_DP_AUTHENTICATED_WOSET 0U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_STATUS_P__HDCP_DP_ENCRYPTION_ENABLE_MASK 0x0000001EU
+#define MHDP__MHDP_APB_REGS__HDCP_DP_STATUS_P__HDCP_DP_ENCRYPTION_ENABLE_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_STATUS_P__HDCP_DP_ENCRYPTION_ENABLE_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_STATUS_P__PSLVERR_HDCP_MASK 0x00000020U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_STATUS_P__PSLVERR_HDCP_SHIFT 5U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_STATUS_P__PSLVERR_HDCP_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_STATUS_P__PSLVERR_HDCP_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_STATUS_P__PSLVERR_HDCP_WOSET 0U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_STATUS_P__RESERVED_0_MASK 0xFFFFFFC0U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_STATUS_P__RESERVED_0_SHIFT 6U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_STATUS_P__RESERVED_0_WIDTH 26U
+
+#define MHDP__MHDP_APB_REGS__HDCP_DP_CONFIG_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__HDCP_DP_CONFIG_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__HDCP_DP_CONFIG_P__HDCP_DP_VERSION_MASK 0x00000007U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_CONFIG_P__HDCP_DP_VERSION_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_CONFIG_P__HDCP_DP_VERSION_WIDTH 3U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_CONFIG_P__HDCP_DP_BYPASS_MASK 0x00000018U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_CONFIG_P__HDCP_DP_BYPASS_SHIFT 3U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_CONFIG_P__HDCP_DP_BYPASS_WIDTH 2U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_CONFIG_P__HDCP_VBID5_ALIGN_DIS_MASK 0x00000020U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_CONFIG_P__HDCP_VBID5_ALIGN_DIS_SHIFT 5U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_CONFIG_P__HDCP_VBID5_ALIGN_DIS_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_CONFIG_P__HDCP_VBID5_ALIGN_DIS_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_CONFIG_P__HDCP_VBID5_ALIGN_DIS_WOSET 0U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_CONFIG_P__SST_HDCP_ENCRYPT_DIS_MASK 0x00000040U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_CONFIG_P__SST_HDCP_ENCRYPT_DIS_SHIFT 6U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_CONFIG_P__SST_HDCP_ENCRYPT_DIS_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_CONFIG_P__SST_HDCP_ENCRYPT_DIS_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_CONFIG_P__SST_HDCP_ENCRYPT_DIS_WOSET 0U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_CONFIG_P__RESERVED_0_MASK 0xFFFFFF80U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_CONFIG_P__RESERVED_0_SHIFT 7U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_CONFIG_P__RESERVED_0_WIDTH 25U
+
+#define MHDP__MHDP_APB_REGS__HDCP_DP_SW_RST_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__HDCP_DP_SW_RST_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__HDCP_DP_SW_RST_P__SW_RST_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_SW_RST_P__SW_RST_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_SW_RST_P__SW_RST_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_SW_RST_P__SW_RST_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_SW_RST_P__SW_RST_WOSET 0U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_SW_RST_P__CIPHER_CTRL_SW_RST_MASK 0x00000002U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_SW_RST_P__CIPHER_CTRL_SW_RST_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_SW_RST_P__CIPHER_CTRL_SW_RST_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_SW_RST_P__CIPHER_CTRL_SW_RST_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_SW_RST_P__CIPHER_CTRL_SW_RST_WOSET 0U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_SW_RST_P__RESERVED_0_MASK 0xFFFFFFFCU
+#define MHDP__MHDP_APB_REGS__HDCP_DP_SW_RST_P__RESERVED_0_SHIFT 2U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_SW_RST_P__RESERVED_0_WIDTH 30U
+
+#define MHDP__MHDP_APB_REGS__HDCP_DP_FIFO_STATUS_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__HDCP_DP_FIFO_STATUS_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__HDCP_DP_FIFO_STATUS_P__HDCP_DP_SST_2_2_FIFO0_OVERFLOW_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_FIFO_STATUS_P__HDCP_DP_SST_2_2_FIFO0_OVERFLOW_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_FIFO_STATUS_P__HDCP_DP_SST_2_2_FIFO0_OVERFLOW_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_FIFO_STATUS_P__HDCP_DP_SST_2_2_FIFO0_OVERFLOW_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_FIFO_STATUS_P__HDCP_DP_SST_2_2_FIFO0_OVERFLOW_WOSET 0U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_FIFO_STATUS_P__HDCP_DP_SST_2_2_FIFO0_UNDERFLOW_MASK 0x00000002U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_FIFO_STATUS_P__HDCP_DP_SST_2_2_FIFO0_UNDERFLOW_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_FIFO_STATUS_P__HDCP_DP_SST_2_2_FIFO0_UNDERFLOW_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_FIFO_STATUS_P__HDCP_DP_SST_2_2_FIFO0_UNDERFLOW_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_FIFO_STATUS_P__HDCP_DP_SST_2_2_FIFO0_UNDERFLOW_WOSET 0U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_FIFO_STATUS_P__HDCP_DP_SST_2_2_FIFO1_OVERFLOW_MASK 0x00000004U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_FIFO_STATUS_P__HDCP_DP_SST_2_2_FIFO1_OVERFLOW_SHIFT 2U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_FIFO_STATUS_P__HDCP_DP_SST_2_2_FIFO1_OVERFLOW_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_FIFO_STATUS_P__HDCP_DP_SST_2_2_FIFO1_OVERFLOW_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_FIFO_STATUS_P__HDCP_DP_SST_2_2_FIFO1_OVERFLOW_WOSET 0U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_FIFO_STATUS_P__HDCP_DP_SST_2_2_FIFO1_UNDERFLOW_MASK 0x00000008U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_FIFO_STATUS_P__HDCP_DP_SST_2_2_FIFO1_UNDERFLOW_SHIFT 3U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_FIFO_STATUS_P__HDCP_DP_SST_2_2_FIFO1_UNDERFLOW_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_FIFO_STATUS_P__HDCP_DP_SST_2_2_FIFO1_UNDERFLOW_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_FIFO_STATUS_P__HDCP_DP_SST_2_2_FIFO1_UNDERFLOW_WOSET 0U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_FIFO_STATUS_P__HDCP_DP_SST_2_2_FIFO2_OVERFLOW_MASK 0x00000010U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_FIFO_STATUS_P__HDCP_DP_SST_2_2_FIFO2_OVERFLOW_SHIFT 4U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_FIFO_STATUS_P__HDCP_DP_SST_2_2_FIFO2_OVERFLOW_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_FIFO_STATUS_P__HDCP_DP_SST_2_2_FIFO2_OVERFLOW_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_FIFO_STATUS_P__HDCP_DP_SST_2_2_FIFO2_OVERFLOW_WOSET 0U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_FIFO_STATUS_P__HDCP_DP_SST_2_2_FIFO2_UNDERFLOW_MASK 0x00000020U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_FIFO_STATUS_P__HDCP_DP_SST_2_2_FIFO2_UNDERFLOW_SHIFT 5U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_FIFO_STATUS_P__HDCP_DP_SST_2_2_FIFO2_UNDERFLOW_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_FIFO_STATUS_P__HDCP_DP_SST_2_2_FIFO2_UNDERFLOW_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_FIFO_STATUS_P__HDCP_DP_SST_2_2_FIFO2_UNDERFLOW_WOSET 0U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_FIFO_STATUS_P__HDCP_DP_SST_2_2_FIFO3_OVERFLOW_MASK 0x00000040U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_FIFO_STATUS_P__HDCP_DP_SST_2_2_FIFO3_OVERFLOW_SHIFT 6U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_FIFO_STATUS_P__HDCP_DP_SST_2_2_FIFO3_OVERFLOW_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_FIFO_STATUS_P__HDCP_DP_SST_2_2_FIFO3_OVERFLOW_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_FIFO_STATUS_P__HDCP_DP_SST_2_2_FIFO3_OVERFLOW_WOSET 0U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_FIFO_STATUS_P__HDCP_DP_SST_2_2_FIFO3_UNDERFLOW_MASK 0x00000080U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_FIFO_STATUS_P__HDCP_DP_SST_2_2_FIFO3_UNDERFLOW_SHIFT 7U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_FIFO_STATUS_P__HDCP_DP_SST_2_2_FIFO3_UNDERFLOW_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_FIFO_STATUS_P__HDCP_DP_SST_2_2_FIFO3_UNDERFLOW_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_FIFO_STATUS_P__HDCP_DP_SST_2_2_FIFO3_UNDERFLOW_WOSET 0U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_FIFO_STATUS_P__HDCP_DP_SST_1_4_FIFO0_OVERFLOW_MASK 0x00000100U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_FIFO_STATUS_P__HDCP_DP_SST_1_4_FIFO0_OVERFLOW_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_FIFO_STATUS_P__HDCP_DP_SST_1_4_FIFO0_OVERFLOW_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_FIFO_STATUS_P__HDCP_DP_SST_1_4_FIFO0_OVERFLOW_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_FIFO_STATUS_P__HDCP_DP_SST_1_4_FIFO0_OVERFLOW_WOSET 0U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_FIFO_STATUS_P__HDCP_DP_SST_1_4_FIFO0_UNDERFLOW_MASK 0x00000200U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_FIFO_STATUS_P__HDCP_DP_SST_1_4_FIFO0_UNDERFLOW_SHIFT 9U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_FIFO_STATUS_P__HDCP_DP_SST_1_4_FIFO0_UNDERFLOW_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_FIFO_STATUS_P__HDCP_DP_SST_1_4_FIFO0_UNDERFLOW_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_FIFO_STATUS_P__HDCP_DP_SST_1_4_FIFO0_UNDERFLOW_WOSET 0U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_FIFO_STATUS_P__HDCP_DP_SST_1_4_FIFO1_OVERFLOW_MASK 0x00000400U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_FIFO_STATUS_P__HDCP_DP_SST_1_4_FIFO1_OVERFLOW_SHIFT 10U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_FIFO_STATUS_P__HDCP_DP_SST_1_4_FIFO1_OVERFLOW_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_FIFO_STATUS_P__HDCP_DP_SST_1_4_FIFO1_OVERFLOW_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_FIFO_STATUS_P__HDCP_DP_SST_1_4_FIFO1_OVERFLOW_WOSET 0U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_FIFO_STATUS_P__HDCP_DP_SST_1_4_FIFO1_UNDERFLOW_MASK 0x00000800U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_FIFO_STATUS_P__HDCP_DP_SST_1_4_FIFO1_UNDERFLOW_SHIFT 11U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_FIFO_STATUS_P__HDCP_DP_SST_1_4_FIFO1_UNDERFLOW_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_FIFO_STATUS_P__HDCP_DP_SST_1_4_FIFO1_UNDERFLOW_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_FIFO_STATUS_P__HDCP_DP_SST_1_4_FIFO1_UNDERFLOW_WOSET 0U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_FIFO_STATUS_P__RESERVED_0_MASK 0xFFFFF000U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_FIFO_STATUS_P__RESERVED_0_SHIFT 12U
+#define MHDP__MHDP_APB_REGS__HDCP_DP_FIFO_STATUS_P__RESERVED_0_WIDTH 20U
+
+#define MHDP__MHDP_APB_REGS__DP_AUX_HOST_CONTROL_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DP_AUX_HOST_CONTROL_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DP_AUX_HOST_CONTROL_P__AUX_HOST_ALWAYS_READ_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__DP_AUX_HOST_CONTROL_P__AUX_HOST_ALWAYS_READ_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_HOST_CONTROL_P__AUX_HOST_ALWAYS_READ_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__DP_AUX_HOST_CONTROL_P__AUX_HOST_ALWAYS_READ_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_HOST_CONTROL_P__AUX_HOST_ALWAYS_READ_WOSET 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_HOST_CONTROL_P__AUX_HOST_PRECHARGE_ENABLE_MASK 0x00000002U
+#define MHDP__MHDP_APB_REGS__DP_AUX_HOST_CONTROL_P__AUX_HOST_PRECHARGE_ENABLE_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__DP_AUX_HOST_CONTROL_P__AUX_HOST_PRECHARGE_ENABLE_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__DP_AUX_HOST_CONTROL_P__AUX_HOST_PRECHARGE_ENABLE_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_HOST_CONTROL_P__AUX_HOST_PRECHARGE_ENABLE_WOSET 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_HOST_CONTROL_P__AUX_HOST_TRANSMIT_IMMEDIATE_MASK 0x00000004U
+#define MHDP__MHDP_APB_REGS__DP_AUX_HOST_CONTROL_P__AUX_HOST_TRANSMIT_IMMEDIATE_SHIFT 2U
+#define MHDP__MHDP_APB_REGS__DP_AUX_HOST_CONTROL_P__AUX_HOST_TRANSMIT_IMMEDIATE_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__DP_AUX_HOST_CONTROL_P__AUX_HOST_TRANSMIT_IMMEDIATE_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_HOST_CONTROL_P__AUX_HOST_TRANSMIT_IMMEDIATE_WOSET 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_HOST_CONTROL_P__RESERVED_0_MASK 0xFFFFFFF8U
+#define MHDP__MHDP_APB_REGS__DP_AUX_HOST_CONTROL_P__RESERVED_0_SHIFT 3U
+#define MHDP__MHDP_APB_REGS__DP_AUX_HOST_CONTROL_P__RESERVED_0_WIDTH 29U
+
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_SOURCE_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_SOURCE_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_SOURCE_P__PSLVERR_DPAUX_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_SOURCE_P__PSLVERR_DPAUX_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_SOURCE_P__PSLVERR_DPAUX_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_SOURCE_P__PSLVERR_DPAUX_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_SOURCE_P__PSLVERR_DPAUX_WOSET 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_SOURCE_P__AUX_TX_DONE_MASK 0x00000002U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_SOURCE_P__AUX_TX_DONE_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_SOURCE_P__AUX_TX_DONE_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_SOURCE_P__AUX_TX_DONE_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_SOURCE_P__AUX_TX_DONE_WOSET 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_SOURCE_P__AUX_RX_DATA_TRANSFER_INIT_MASK 0x00000004U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_SOURCE_P__AUX_RX_DATA_TRANSFER_INIT_SHIFT 2U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_SOURCE_P__AUX_RX_DATA_TRANSFER_INIT_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_SOURCE_P__AUX_RX_DATA_TRANSFER_INIT_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_SOURCE_P__AUX_RX_DATA_TRANSFER_INIT_WOSET 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_SOURCE_P__AUX_MAIN_RX_STATUS_DONE_MASK 0x00000008U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_SOURCE_P__AUX_MAIN_RX_STATUS_DONE_SHIFT 3U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_SOURCE_P__AUX_MAIN_RX_STATUS_DONE_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_SOURCE_P__AUX_MAIN_RX_STATUS_DONE_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_SOURCE_P__AUX_MAIN_RX_STATUS_DONE_WOSET 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_SOURCE_P__AUX_MAIN_RX_STATUS_SHORT_PREAMBLE_MASK 0x00000010U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_SOURCE_P__AUX_MAIN_RX_STATUS_SHORT_PREAMBLE_SHIFT 4U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_SOURCE_P__AUX_MAIN_RX_STATUS_SHORT_PREAMBLE_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_SOURCE_P__AUX_MAIN_RX_STATUS_SHORT_PREAMBLE_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_SOURCE_P__AUX_MAIN_RX_STATUS_SHORT_PREAMBLE_WOSET 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_SOURCE_P__AUX_MAIN_RX_STATUS_LONG_PREAMBLE_MASK 0x00000020U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_SOURCE_P__AUX_MAIN_RX_STATUS_LONG_PREAMBLE_SHIFT 5U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_SOURCE_P__AUX_MAIN_RX_STATUS_LONG_PREAMBLE_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_SOURCE_P__AUX_MAIN_RX_STATUS_LONG_PREAMBLE_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_SOURCE_P__AUX_MAIN_RX_STATUS_LONG_PREAMBLE_WOSET 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_SOURCE_P__AUX_MAIN_RX_STATUS_LONG_DATA_MASK 0x00000040U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_SOURCE_P__AUX_MAIN_RX_STATUS_LONG_DATA_SHIFT 6U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_SOURCE_P__AUX_MAIN_RX_STATUS_LONG_DATA_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_SOURCE_P__AUX_MAIN_RX_STATUS_LONG_DATA_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_SOURCE_P__AUX_MAIN_RX_STATUS_LONG_DATA_WOSET 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_SOURCE_P__AUX_MAIN_RX_STATUS_CORRUPTED_MASK 0x00000080U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_SOURCE_P__AUX_MAIN_RX_STATUS_CORRUPTED_SHIFT 7U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_SOURCE_P__AUX_MAIN_RX_STATUS_CORRUPTED_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_SOURCE_P__AUX_MAIN_RX_STATUS_CORRUPTED_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_SOURCE_P__AUX_MAIN_RX_STATUS_CORRUPTED_WOSET 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_SOURCE_P__AUX_RX_ERROR_CYCLE_TIME_MASK 0x00000100U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_SOURCE_P__AUX_RX_ERROR_CYCLE_TIME_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_SOURCE_P__AUX_RX_ERROR_CYCLE_TIME_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_SOURCE_P__AUX_RX_ERROR_CYCLE_TIME_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_SOURCE_P__AUX_RX_ERROR_CYCLE_TIME_WOSET 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_SOURCE_P__AUX_MAIN_EXPIRE_TX_MASK 0x00000200U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_SOURCE_P__AUX_MAIN_EXPIRE_TX_SHIFT 9U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_SOURCE_P__AUX_MAIN_EXPIRE_TX_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_SOURCE_P__AUX_MAIN_EXPIRE_TX_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_SOURCE_P__AUX_MAIN_EXPIRE_TX_WOSET 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_SOURCE_P__RESERVED_0_MASK 0xFFFFFC00U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_SOURCE_P__RESERVED_0_SHIFT 10U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_SOURCE_P__RESERVED_0_WIDTH 22U
+
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_MASK_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_MASK_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_MASK_P__PSLVERR_MASK_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_MASK_P__PSLVERR_MASK_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_MASK_P__PSLVERR_MASK_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_MASK_P__PSLVERR_MASK_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_MASK_P__PSLVERR_MASK_WOSET 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_MASK_P__AUX_TX_DONE_MASK_MASK 0x00000002U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_MASK_P__AUX_TX_DONE_MASK_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_MASK_P__AUX_TX_DONE_MASK_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_MASK_P__AUX_TX_DONE_MASK_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_MASK_P__AUX_TX_DONE_MASK_WOSET 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_MASK_P__AUX_RX_DATA_TRANSFER_INIT_MASK_MASK 0x00000004U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_MASK_P__AUX_RX_DATA_TRANSFER_INIT_MASK_SHIFT 2U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_MASK_P__AUX_RX_DATA_TRANSFER_INIT_MASK_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_MASK_P__AUX_RX_DATA_TRANSFER_INIT_MASK_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_MASK_P__AUX_RX_DATA_TRANSFER_INIT_MASK_WOSET 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_MASK_P__AUX_MAIN_RX_STATUS_DONE_MASK_MASK 0x00000008U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_MASK_P__AUX_MAIN_RX_STATUS_DONE_MASK_SHIFT 3U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_MASK_P__AUX_MAIN_RX_STATUS_DONE_MASK_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_MASK_P__AUX_MAIN_RX_STATUS_DONE_MASK_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_MASK_P__AUX_MAIN_RX_STATUS_DONE_MASK_WOSET 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_MASK_P__AUX_MAIN_RX_STATUS_SHORT_PREAMBLE_MASK_MASK 0x00000010U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_MASK_P__AUX_MAIN_RX_STATUS_SHORT_PREAMBLE_MASK_SHIFT 4U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_MASK_P__AUX_MAIN_RX_STATUS_SHORT_PREAMBLE_MASK_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_MASK_P__AUX_MAIN_RX_STATUS_SHORT_PREAMBLE_MASK_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_MASK_P__AUX_MAIN_RX_STATUS_SHORT_PREAMBLE_MASK_WOSET 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_MASK_P__AUX_MAIN_RX_STATUS_LONG_PREAMBLE_MASK_MASK 0x00000020U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_MASK_P__AUX_MAIN_RX_STATUS_LONG_PREAMBLE_MASK_SHIFT 5U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_MASK_P__AUX_MAIN_RX_STATUS_LONG_PREAMBLE_MASK_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_MASK_P__AUX_MAIN_RX_STATUS_LONG_PREAMBLE_MASK_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_MASK_P__AUX_MAIN_RX_STATUS_LONG_PREAMBLE_MASK_WOSET 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_MASK_P__AUX_MAIN_RX_STATUS_LONG_DATA_MASK_MASK 0x00000040U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_MASK_P__AUX_MAIN_RX_STATUS_LONG_DATA_MASK_SHIFT 6U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_MASK_P__AUX_MAIN_RX_STATUS_LONG_DATA_MASK_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_MASK_P__AUX_MAIN_RX_STATUS_LONG_DATA_MASK_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_MASK_P__AUX_MAIN_RX_STATUS_LONG_DATA_MASK_WOSET 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_MASK_P__AUX_MAIN_RX_STATUS_CORRUPTED_MASK_MASK 0x00000080U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_MASK_P__AUX_MAIN_RX_STATUS_CORRUPTED_MASK_SHIFT 7U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_MASK_P__AUX_MAIN_RX_STATUS_CORRUPTED_MASK_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_MASK_P__AUX_MAIN_RX_STATUS_CORRUPTED_MASK_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_MASK_P__AUX_MAIN_RX_STATUS_CORRUPTED_MASK_WOSET 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_MASK_P__AUX_RX_ERROR_CYCLE_TIME_MASK_MASK 0x00000100U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_MASK_P__AUX_RX_ERROR_CYCLE_TIME_MASK_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_MASK_P__AUX_RX_ERROR_CYCLE_TIME_MASK_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_MASK_P__AUX_RX_ERROR_CYCLE_TIME_MASK_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_MASK_P__AUX_RX_ERROR_CYCLE_TIME_MASK_WOSET 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_MASK_P__AUX_MAIN_EXPIRE_TX_MASK_MASK 0x00000200U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_MASK_P__AUX_MAIN_EXPIRE_TX_MASK_SHIFT 9U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_MASK_P__AUX_MAIN_EXPIRE_TX_MASK_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_MASK_P__AUX_MAIN_EXPIRE_TX_MASK_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_MASK_P__AUX_MAIN_EXPIRE_TX_MASK_WOSET 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_MASK_P__RESERVED_0_MASK 0xFFFFFC00U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_MASK_P__RESERVED_0_SHIFT 10U
+#define MHDP__MHDP_APB_REGS__DP_AUX_INTERRUPT_MASK_P__RESERVED_0_WIDTH 22U
+
+#define MHDP__MHDP_APB_REGS__DP_AUX_SWAP_INVERSION_CONTROL_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DP_AUX_SWAP_INVERSION_CONTROL_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DP_AUX_SWAP_INVERSION_CONTROL_P__AUX_HOST_TX_INVERT_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__DP_AUX_SWAP_INVERSION_CONTROL_P__AUX_HOST_TX_INVERT_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_SWAP_INVERSION_CONTROL_P__AUX_HOST_TX_INVERT_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__DP_AUX_SWAP_INVERSION_CONTROL_P__AUX_HOST_TX_INVERT_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_SWAP_INVERSION_CONTROL_P__AUX_HOST_TX_INVERT_WOSET 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_SWAP_INVERSION_CONTROL_P__AUX_HOST_RX_INVERT_MASK 0x00000002U
+#define MHDP__MHDP_APB_REGS__DP_AUX_SWAP_INVERSION_CONTROL_P__AUX_HOST_RX_INVERT_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__DP_AUX_SWAP_INVERSION_CONTROL_P__AUX_HOST_RX_INVERT_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__DP_AUX_SWAP_INVERSION_CONTROL_P__AUX_HOST_RX_INVERT_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_SWAP_INVERSION_CONTROL_P__AUX_HOST_RX_INVERT_WOSET 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_SWAP_INVERSION_CONTROL_P__AUX_HOST_TX_SWAP_MASK 0x00000004U
+#define MHDP__MHDP_APB_REGS__DP_AUX_SWAP_INVERSION_CONTROL_P__AUX_HOST_TX_SWAP_SHIFT 2U
+#define MHDP__MHDP_APB_REGS__DP_AUX_SWAP_INVERSION_CONTROL_P__AUX_HOST_TX_SWAP_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__DP_AUX_SWAP_INVERSION_CONTROL_P__AUX_HOST_TX_SWAP_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_SWAP_INVERSION_CONTROL_P__AUX_HOST_TX_SWAP_WOSET 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_SWAP_INVERSION_CONTROL_P__AUX_HOST_RX_SWAP_MASK 0x00000008U
+#define MHDP__MHDP_APB_REGS__DP_AUX_SWAP_INVERSION_CONTROL_P__AUX_HOST_RX_SWAP_SHIFT 3U
+#define MHDP__MHDP_APB_REGS__DP_AUX_SWAP_INVERSION_CONTROL_P__AUX_HOST_RX_SWAP_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__DP_AUX_SWAP_INVERSION_CONTROL_P__AUX_HOST_RX_SWAP_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_SWAP_INVERSION_CONTROL_P__AUX_HOST_RX_SWAP_WOSET 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_SWAP_INVERSION_CONTROL_P__RESERVED_0_MASK 0xFFFFFFF0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_SWAP_INVERSION_CONTROL_P__RESERVED_0_SHIFT 4U
+#define MHDP__MHDP_APB_REGS__DP_AUX_SWAP_INVERSION_CONTROL_P__RESERVED_0_WIDTH 28U
+
+#define MHDP__MHDP_APB_REGS__DP_AUX_SEND_NACK_TRANSACTION_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DP_AUX_SEND_NACK_TRANSACTION_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DP_AUX_SEND_NACK_TRANSACTION_P__AUX_HOST_SEND_NACK_TRANSACTION_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__DP_AUX_SEND_NACK_TRANSACTION_P__AUX_HOST_SEND_NACK_TRANSACTION_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_SEND_NACK_TRANSACTION_P__AUX_HOST_SEND_NACK_TRANSACTION_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__DP_AUX_SEND_NACK_TRANSACTION_P__AUX_HOST_SEND_NACK_TRANSACTION_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_SEND_NACK_TRANSACTION_P__AUX_HOST_SEND_NACK_TRANSACTION_WOSET 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_SEND_NACK_TRANSACTION_P__RESERVED_0_MASK 0xFFFFFFFEU
+#define MHDP__MHDP_APB_REGS__DP_AUX_SEND_NACK_TRANSACTION_P__RESERVED_0_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__DP_AUX_SEND_NACK_TRANSACTION_P__RESERVED_0_WIDTH 31U
+
+#define MHDP__MHDP_APB_REGS__DP_AUX_CLEAR_RX_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DP_AUX_CLEAR_RX_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DP_AUX_CLEAR_RX_P__AUX_HOST_CLEAR_RX_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__DP_AUX_CLEAR_RX_P__AUX_HOST_CLEAR_RX_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_CLEAR_RX_P__AUX_HOST_CLEAR_RX_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__DP_AUX_CLEAR_RX_P__AUX_HOST_CLEAR_RX_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_CLEAR_RX_P__AUX_HOST_CLEAR_RX_WOSET 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_CLEAR_RX_P__RESERVED_0_MASK 0xFFFFFFFEU
+#define MHDP__MHDP_APB_REGS__DP_AUX_CLEAR_RX_P__RESERVED_0_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__DP_AUX_CLEAR_RX_P__RESERVED_0_WIDTH 31U
+
+#define MHDP__MHDP_APB_REGS__DP_AUX_CLEAR_TX_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DP_AUX_CLEAR_TX_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DP_AUX_CLEAR_TX_P__AUX_HOST_CLEAR_TX_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__DP_AUX_CLEAR_TX_P__AUX_HOST_CLEAR_TX_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_CLEAR_TX_P__AUX_HOST_CLEAR_TX_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__DP_AUX_CLEAR_TX_P__AUX_HOST_CLEAR_TX_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_CLEAR_TX_P__AUX_HOST_CLEAR_TX_WOSET 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_CLEAR_TX_P__RESERVED_0_MASK 0xFFFFFFFEU
+#define MHDP__MHDP_APB_REGS__DP_AUX_CLEAR_TX_P__RESERVED_0_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__DP_AUX_CLEAR_TX_P__RESERVED_0_WIDTH 31U
+
+#define MHDP__MHDP_APB_REGS__DP_AUX_TIMER_STOP_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DP_AUX_TIMER_STOP_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DP_AUX_TIMER_STOP_P__AUX_HOST_STOP_TIMER_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__DP_AUX_TIMER_STOP_P__AUX_HOST_STOP_TIMER_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_TIMER_STOP_P__AUX_HOST_STOP_TIMER_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__DP_AUX_TIMER_STOP_P__AUX_HOST_STOP_TIMER_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_TIMER_STOP_P__AUX_HOST_STOP_TIMER_WOSET 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_TIMER_STOP_P__RESERVED_0_MASK 0xFFFFFFFEU
+#define MHDP__MHDP_APB_REGS__DP_AUX_TIMER_STOP_P__RESERVED_0_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__DP_AUX_TIMER_STOP_P__RESERVED_0_WIDTH 31U
+
+#define MHDP__MHDP_APB_REGS__DP_AUX_TIMER_CLEAR_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DP_AUX_TIMER_CLEAR_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DP_AUX_TIMER_CLEAR_P__AUX_HOST_CLEAR_TIMER_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__DP_AUX_TIMER_CLEAR_P__AUX_HOST_CLEAR_TIMER_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_TIMER_CLEAR_P__AUX_HOST_CLEAR_TIMER_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__DP_AUX_TIMER_CLEAR_P__AUX_HOST_CLEAR_TIMER_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_TIMER_CLEAR_P__AUX_HOST_CLEAR_TIMER_WOSET 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_TIMER_CLEAR_P__RESERVED_0_MASK 0xFFFFFFFEU
+#define MHDP__MHDP_APB_REGS__DP_AUX_TIMER_CLEAR_P__RESERVED_0_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__DP_AUX_TIMER_CLEAR_P__RESERVED_0_WIDTH 31U
+
+#define MHDP__MHDP_APB_REGS__DP_AUX_RESET_SW_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DP_AUX_RESET_SW_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DP_AUX_RESET_SW_P__AUX_HOST_SW_RESET_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__DP_AUX_RESET_SW_P__AUX_HOST_SW_RESET_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_RESET_SW_P__AUX_HOST_SW_RESET_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__DP_AUX_RESET_SW_P__AUX_HOST_SW_RESET_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_RESET_SW_P__AUX_HOST_SW_RESET_WOSET 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_RESET_SW_P__RESERVED_0_MASK 0xFFFFFFFEU
+#define MHDP__MHDP_APB_REGS__DP_AUX_RESET_SW_P__RESERVED_0_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__DP_AUX_RESET_SW_P__RESERVED_0_WIDTH 31U
+
+#define MHDP__MHDP_APB_REGS__DP_AUX_DIVIDE_2M_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DP_AUX_DIVIDE_2M_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DP_AUX_DIVIDE_2M_P__AUX_HOST_DIVIDE_2M_MASK 0x000000FFU
+#define MHDP__MHDP_APB_REGS__DP_AUX_DIVIDE_2M_P__AUX_HOST_DIVIDE_2M_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_DIVIDE_2M_P__AUX_HOST_DIVIDE_2M_WIDTH 8U
+#define MHDP__MHDP_APB_REGS__DP_AUX_DIVIDE_2M_P__RESERVED_0_MASK 0xFFFFFF00U
+#define MHDP__MHDP_APB_REGS__DP_AUX_DIVIDE_2M_P__RESERVED_0_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__DP_AUX_DIVIDE_2M_P__RESERVED_0_WIDTH 24U
+
+#define MHDP__MHDP_APB_REGS__DP_AUX_TX_PREACHARGE_LENGTH_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DP_AUX_TX_PREACHARGE_LENGTH_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DP_AUX_TX_PREACHARGE_LENGTH_P__AUX_HOST_PRECHARGE_LENGTH_MASK 0x0000003FU
+#define MHDP__MHDP_APB_REGS__DP_AUX_TX_PREACHARGE_LENGTH_P__AUX_HOST_PRECHARGE_LENGTH_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_TX_PREACHARGE_LENGTH_P__AUX_HOST_PRECHARGE_LENGTH_WIDTH 6U
+#define MHDP__MHDP_APB_REGS__DP_AUX_TX_PREACHARGE_LENGTH_P__RESERVED_0_MASK 0xFFFFFFC0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_TX_PREACHARGE_LENGTH_P__RESERVED_0_SHIFT 6U
+#define MHDP__MHDP_APB_REGS__DP_AUX_TX_PREACHARGE_LENGTH_P__RESERVED_0_WIDTH 26U
+
+#define MHDP__MHDP_APB_REGS__DP_AUX_FREQUENCY_1M_MAX_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DP_AUX_FREQUENCY_1M_MAX_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DP_AUX_FREQUENCY_1M_MAX_P__AUX_HOST_1M_MAX_MASK 0x000007FFU
+#define MHDP__MHDP_APB_REGS__DP_AUX_FREQUENCY_1M_MAX_P__AUX_HOST_1M_MAX_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_FREQUENCY_1M_MAX_P__AUX_HOST_1M_MAX_WIDTH 11U
+#define MHDP__MHDP_APB_REGS__DP_AUX_FREQUENCY_1M_MAX_P__RESERVED_0_MASK 0xFFFFF800U
+#define MHDP__MHDP_APB_REGS__DP_AUX_FREQUENCY_1M_MAX_P__RESERVED_0_SHIFT 11U
+#define MHDP__MHDP_APB_REGS__DP_AUX_FREQUENCY_1M_MAX_P__RESERVED_0_WIDTH 21U
+
+#define MHDP__MHDP_APB_REGS__DP_AUX_FREQUENCY_1M_MIN_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DP_AUX_FREQUENCY_1M_MIN_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DP_AUX_FREQUENCY_1M_MIN_P__AUX_HOST_1M_MIN_MASK 0x000007FFU
+#define MHDP__MHDP_APB_REGS__DP_AUX_FREQUENCY_1M_MIN_P__AUX_HOST_1M_MIN_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_FREQUENCY_1M_MIN_P__AUX_HOST_1M_MIN_WIDTH 11U
+#define MHDP__MHDP_APB_REGS__DP_AUX_FREQUENCY_1M_MIN_P__RESERVED_0_MASK 0xFFFFF800U
+#define MHDP__MHDP_APB_REGS__DP_AUX_FREQUENCY_1M_MIN_P__RESERVED_0_SHIFT 11U
+#define MHDP__MHDP_APB_REGS__DP_AUX_FREQUENCY_1M_MIN_P__RESERVED_0_WIDTH 21U
+
+#define MHDP__MHDP_APB_REGS__DP_AUX_RX_PRE_MIN_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DP_AUX_RX_PRE_MIN_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DP_AUX_RX_PRE_MIN_P__AUX_HOST_PRE_MIN_MASK 0x0000003FU
+#define MHDP__MHDP_APB_REGS__DP_AUX_RX_PRE_MIN_P__AUX_HOST_PRE_MIN_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_RX_PRE_MIN_P__AUX_HOST_PRE_MIN_WIDTH 6U
+#define MHDP__MHDP_APB_REGS__DP_AUX_RX_PRE_MIN_P__RESERVED_0_MASK 0xFFFFFFC0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_RX_PRE_MIN_P__RESERVED_0_SHIFT 6U
+#define MHDP__MHDP_APB_REGS__DP_AUX_RX_PRE_MIN_P__RESERVED_0_WIDTH 26U
+
+#define MHDP__MHDP_APB_REGS__DP_AUX_RX_PRE_MAX_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DP_AUX_RX_PRE_MAX_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DP_AUX_RX_PRE_MAX_P__AUX_HOST_PRE_MAX_MASK 0x0000003FU
+#define MHDP__MHDP_APB_REGS__DP_AUX_RX_PRE_MAX_P__AUX_HOST_PRE_MAX_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_RX_PRE_MAX_P__AUX_HOST_PRE_MAX_WIDTH 6U
+#define MHDP__MHDP_APB_REGS__DP_AUX_RX_PRE_MAX_P__RESERVED_0_MASK 0xFFFFFFC0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_RX_PRE_MAX_P__RESERVED_0_SHIFT 6U
+#define MHDP__MHDP_APB_REGS__DP_AUX_RX_PRE_MAX_P__RESERVED_0_WIDTH 26U
+
+#define MHDP__MHDP_APB_REGS__DP_AUX_TIMER_PRESET_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DP_AUX_TIMER_PRESET_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DP_AUX_TIMER_PRESET_P__AUX_HOST_TIMER_PRESET_MASK 0x0000FFFFU
+#define MHDP__MHDP_APB_REGS__DP_AUX_TIMER_PRESET_P__AUX_HOST_TIMER_PRESET_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_TIMER_PRESET_P__AUX_HOST_TIMER_PRESET_WIDTH 16U
+#define MHDP__MHDP_APB_REGS__DP_AUX_TIMER_PRESET_P__RESERVED_0_MASK 0xFFFF0000U
+#define MHDP__MHDP_APB_REGS__DP_AUX_TIMER_PRESET_P__RESERVED_0_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__DP_AUX_TIMER_PRESET_P__RESERVED_0_WIDTH 16U
+
+#define MHDP__MHDP_APB_REGS__DP_AUX_NACK_FORMAT_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DP_AUX_NACK_FORMAT_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DP_AUX_NACK_FORMAT_P__AUX_HOST_NACK_FORMAT_MASK 0x000000FFU
+#define MHDP__MHDP_APB_REGS__DP_AUX_NACK_FORMAT_P__AUX_HOST_NACK_FORMAT_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_NACK_FORMAT_P__AUX_HOST_NACK_FORMAT_WIDTH 8U
+#define MHDP__MHDP_APB_REGS__DP_AUX_NACK_FORMAT_P__RESERVED_0_MASK 0xFFFFFF00U
+#define MHDP__MHDP_APB_REGS__DP_AUX_NACK_FORMAT_P__RESERVED_0_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__DP_AUX_NACK_FORMAT_P__RESERVED_0_WIDTH 24U
+
+#define MHDP__MHDP_APB_REGS__DP_AUX_TX_DATA_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DP_AUX_TX_DATA_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DP_AUX_TX_DATA_P__MAILBOX_TX_DATA_MASK 0x000003FFU
+#define MHDP__MHDP_APB_REGS__DP_AUX_TX_DATA_P__MAILBOX_TX_DATA_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_TX_DATA_P__MAILBOX_TX_DATA_WIDTH 10U
+#define MHDP__MHDP_APB_REGS__DP_AUX_TX_DATA_P__RESERVED_0_MASK 0xFFFFFC00U
+#define MHDP__MHDP_APB_REGS__DP_AUX_TX_DATA_P__RESERVED_0_SHIFT 10U
+#define MHDP__MHDP_APB_REGS__DP_AUX_TX_DATA_P__RESERVED_0_WIDTH 22U
+
+#define MHDP__MHDP_APB_REGS__DP_AUX_RX_DATA_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DP_AUX_RX_DATA_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DP_AUX_RX_DATA_P__MAILBOX_RX_DATA_MASK 0x000003FFU
+#define MHDP__MHDP_APB_REGS__DP_AUX_RX_DATA_P__MAILBOX_RX_DATA_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_RX_DATA_P__MAILBOX_RX_DATA_WIDTH 10U
+#define MHDP__MHDP_APB_REGS__DP_AUX_RX_DATA_P__RESERVED_0_MASK 0xFFFFFC00U
+#define MHDP__MHDP_APB_REGS__DP_AUX_RX_DATA_P__RESERVED_0_SHIFT 10U
+#define MHDP__MHDP_APB_REGS__DP_AUX_RX_DATA_P__RESERVED_0_WIDTH 22U
+
+#define MHDP__MHDP_APB_REGS__DP_AUX_TX_STATUS_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DP_AUX_TX_STATUS_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DP_AUX_TX_STATUS_P__AUX_TX_STATE_MASK 0x0000007FU
+#define MHDP__MHDP_APB_REGS__DP_AUX_TX_STATUS_P__AUX_TX_STATE_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_TX_STATUS_P__AUX_TX_STATE_WIDTH 7U
+#define MHDP__MHDP_APB_REGS__DP_AUX_TX_STATUS_P__AUX_TX_FRAME_ONGOING_MASK 0x00000080U
+#define MHDP__MHDP_APB_REGS__DP_AUX_TX_STATUS_P__AUX_TX_FRAME_ONGOING_SHIFT 7U
+#define MHDP__MHDP_APB_REGS__DP_AUX_TX_STATUS_P__AUX_TX_FRAME_ONGOING_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__DP_AUX_TX_STATUS_P__AUX_TX_FRAME_ONGOING_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_TX_STATUS_P__AUX_TX_FRAME_ONGOING_WOSET 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_TX_STATUS_P__MAILBOX_TX_EMPTY_MASK 0x00000100U
+#define MHDP__MHDP_APB_REGS__DP_AUX_TX_STATUS_P__MAILBOX_TX_EMPTY_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__DP_AUX_TX_STATUS_P__MAILBOX_TX_EMPTY_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__DP_AUX_TX_STATUS_P__MAILBOX_TX_EMPTY_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_TX_STATUS_P__MAILBOX_TX_EMPTY_WOSET 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_TX_STATUS_P__MAILBOX_TX_FULL_MASK 0x00000200U
+#define MHDP__MHDP_APB_REGS__DP_AUX_TX_STATUS_P__MAILBOX_TX_FULL_SHIFT 9U
+#define MHDP__MHDP_APB_REGS__DP_AUX_TX_STATUS_P__MAILBOX_TX_FULL_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__DP_AUX_TX_STATUS_P__MAILBOX_TX_FULL_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_TX_STATUS_P__MAILBOX_TX_FULL_WOSET 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_TX_STATUS_P__RESERVED_0_MASK 0xFFFFFC00U
+#define MHDP__MHDP_APB_REGS__DP_AUX_TX_STATUS_P__RESERVED_0_SHIFT 10U
+#define MHDP__MHDP_APB_REGS__DP_AUX_TX_STATUS_P__RESERVED_0_WIDTH 22U
+
+#define MHDP__MHDP_APB_REGS__DP_AUX_RX_STATUS_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DP_AUX_RX_STATUS_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DP_AUX_RX_STATUS_P__AUX_RX_MAIN_STATE_MASK 0x0000001FU
+#define MHDP__MHDP_APB_REGS__DP_AUX_RX_STATUS_P__AUX_RX_MAIN_STATE_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_RX_STATUS_P__AUX_RX_MAIN_STATE_WIDTH 5U
+#define MHDP__MHDP_APB_REGS__DP_AUX_RX_STATUS_P__AUX_RX_FRAME_ONGOING_MASK 0x00000020U
+#define MHDP__MHDP_APB_REGS__DP_AUX_RX_STATUS_P__AUX_RX_FRAME_ONGOING_SHIFT 5U
+#define MHDP__MHDP_APB_REGS__DP_AUX_RX_STATUS_P__AUX_RX_FRAME_ONGOING_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__DP_AUX_RX_STATUS_P__AUX_RX_FRAME_ONGOING_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_RX_STATUS_P__AUX_RX_FRAME_ONGOING_WOSET 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_RX_STATUS_P__MAILBOX_RX_EMPTY_MASK 0x00000040U
+#define MHDP__MHDP_APB_REGS__DP_AUX_RX_STATUS_P__MAILBOX_RX_EMPTY_SHIFT 6U
+#define MHDP__MHDP_APB_REGS__DP_AUX_RX_STATUS_P__MAILBOX_RX_EMPTY_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__DP_AUX_RX_STATUS_P__MAILBOX_RX_EMPTY_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_RX_STATUS_P__MAILBOX_RX_EMPTY_WOSET 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_RX_STATUS_P__MAILBOX_RX_FULL_MASK 0x00000080U
+#define MHDP__MHDP_APB_REGS__DP_AUX_RX_STATUS_P__MAILBOX_RX_FULL_SHIFT 7U
+#define MHDP__MHDP_APB_REGS__DP_AUX_RX_STATUS_P__MAILBOX_RX_FULL_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__DP_AUX_RX_STATUS_P__MAILBOX_RX_FULL_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_RX_STATUS_P__MAILBOX_RX_FULL_WOSET 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_RX_STATUS_P__AUX_RX_PREAMBLE_STATE_MASK 0x00003F00U
+#define MHDP__MHDP_APB_REGS__DP_AUX_RX_STATUS_P__AUX_RX_PREAMBLE_STATE_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__DP_AUX_RX_STATUS_P__AUX_RX_PREAMBLE_STATE_WIDTH 6U
+#define MHDP__MHDP_APB_REGS__DP_AUX_RX_STATUS_P__RESERVED_0_MASK 0x0000C000U
+#define MHDP__MHDP_APB_REGS__DP_AUX_RX_STATUS_P__RESERVED_0_SHIFT 14U
+#define MHDP__MHDP_APB_REGS__DP_AUX_RX_STATUS_P__RESERVED_0_WIDTH 2U
+#define MHDP__MHDP_APB_REGS__DP_AUX_RX_STATUS_P__AUX_RX_HHLL_STATE_MASK 0x000F0000U
+#define MHDP__MHDP_APB_REGS__DP_AUX_RX_STATUS_P__AUX_RX_HHLL_STATE_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__DP_AUX_RX_STATUS_P__AUX_RX_HHLL_STATE_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__DP_AUX_RX_STATUS_P__RESERVED_1_MASK 0x00700000U
+#define MHDP__MHDP_APB_REGS__DP_AUX_RX_STATUS_P__RESERVED_1_SHIFT 20U
+#define MHDP__MHDP_APB_REGS__DP_AUX_RX_STATUS_P__RESERVED_1_WIDTH 3U
+#define MHDP__MHDP_APB_REGS__DP_AUX_RX_STATUS_P__AUX_MAIN_RX_STATUS_LAST_EQUAL_MASK 0x00800000U
+#define MHDP__MHDP_APB_REGS__DP_AUX_RX_STATUS_P__AUX_MAIN_RX_STATUS_LAST_EQUAL_SHIFT 23U
+#define MHDP__MHDP_APB_REGS__DP_AUX_RX_STATUS_P__AUX_MAIN_RX_STATUS_LAST_EQUAL_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__DP_AUX_RX_STATUS_P__AUX_MAIN_RX_STATUS_LAST_EQUAL_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_RX_STATUS_P__AUX_MAIN_RX_STATUS_LAST_EQUAL_WOSET 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_RX_STATUS_P__AUX_RX_DATA_STATE_MASK 0xFF000000U
+#define MHDP__MHDP_APB_REGS__DP_AUX_RX_STATUS_P__AUX_RX_DATA_STATE_SHIFT 24U
+#define MHDP__MHDP_APB_REGS__DP_AUX_RX_STATUS_P__AUX_RX_DATA_STATE_WIDTH 8U
+
+#define MHDP__MHDP_APB_REGS__DP_AUX_RX_CYCLE_COUNTER_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DP_AUX_RX_CYCLE_COUNTER_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DP_AUX_RX_CYCLE_COUNTER_P__AUX_RX_CYCLE_COUNTER_MASK 0x000007FFU
+#define MHDP__MHDP_APB_REGS__DP_AUX_RX_CYCLE_COUNTER_P__AUX_RX_CYCLE_COUNTER_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_RX_CYCLE_COUNTER_P__AUX_RX_CYCLE_COUNTER_WIDTH 11U
+#define MHDP__MHDP_APB_REGS__DP_AUX_RX_CYCLE_COUNTER_P__RESERVED_0_MASK 0xFFFFF800U
+#define MHDP__MHDP_APB_REGS__DP_AUX_RX_CYCLE_COUNTER_P__RESERVED_0_SHIFT 11U
+#define MHDP__MHDP_APB_REGS__DP_AUX_RX_CYCLE_COUNTER_P__RESERVED_0_WIDTH 21U
+
+#define MHDP__MHDP_APB_REGS__DP_AUX_MAIN_STATES_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DP_AUX_MAIN_STATES_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DP_AUX_MAIN_STATES_P__AUX_MAIN_TX_STATE_MASK 0x00000003U
+#define MHDP__MHDP_APB_REGS__DP_AUX_MAIN_STATES_P__AUX_MAIN_TX_STATE_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_MAIN_STATES_P__AUX_MAIN_TX_STATE_WIDTH 2U
+#define MHDP__MHDP_APB_REGS__DP_AUX_MAIN_STATES_P__AUX_MAIN_RX_STATE_MASK 0x0000001CU
+#define MHDP__MHDP_APB_REGS__DP_AUX_MAIN_STATES_P__AUX_MAIN_RX_STATE_SHIFT 2U
+#define MHDP__MHDP_APB_REGS__DP_AUX_MAIN_STATES_P__AUX_MAIN_RX_STATE_WIDTH 3U
+#define MHDP__MHDP_APB_REGS__DP_AUX_MAIN_STATES_P__AUX_MAIN_DP_STATE_MASK 0x00000060U
+#define MHDP__MHDP_APB_REGS__DP_AUX_MAIN_STATES_P__AUX_MAIN_DP_STATE_SHIFT 5U
+#define MHDP__MHDP_APB_REGS__DP_AUX_MAIN_STATES_P__AUX_MAIN_DP_STATE_WIDTH 2U
+#define MHDP__MHDP_APB_REGS__DP_AUX_MAIN_STATES_P__RESERVED_1_MASK 0x00000080U
+#define MHDP__MHDP_APB_REGS__DP_AUX_MAIN_STATES_P__RESERVED_1_SHIFT 7U
+#define MHDP__MHDP_APB_REGS__DP_AUX_MAIN_STATES_P__RESERVED_1_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__DP_AUX_MAIN_STATES_P__RESERVED_1_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_MAIN_STATES_P__RESERVED_1_WOSET 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_MAIN_STATES_P__AUX_MAIN_TIMER_STATE_MASK 0x00000300U
+#define MHDP__MHDP_APB_REGS__DP_AUX_MAIN_STATES_P__AUX_MAIN_TIMER_STATE_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__DP_AUX_MAIN_STATES_P__AUX_MAIN_TIMER_STATE_WIDTH 2U
+#define MHDP__MHDP_APB_REGS__DP_AUX_MAIN_STATES_P__AUX_MAIN_EXTERNAL_STATE_MASK 0x00003C00U
+#define MHDP__MHDP_APB_REGS__DP_AUX_MAIN_STATES_P__AUX_MAIN_EXTERNAL_STATE_SHIFT 10U
+#define MHDP__MHDP_APB_REGS__DP_AUX_MAIN_STATES_P__AUX_MAIN_EXTERNAL_STATE_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__DP_AUX_MAIN_STATES_P__RESERVED_2_MASK 0xFFFFC000U
+#define MHDP__MHDP_APB_REGS__DP_AUX_MAIN_STATES_P__RESERVED_2_SHIFT 14U
+#define MHDP__MHDP_APB_REGS__DP_AUX_MAIN_STATES_P__RESERVED_2_WIDTH 18U
+
+#define MHDP__MHDP_APB_REGS__DP_AUX_MAIN_TIMER_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DP_AUX_MAIN_TIMER_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DP_AUX_MAIN_TIMER_P__AUX_MAIN_TIMER_MASK 0x0000FFFFU
+#define MHDP__MHDP_APB_REGS__DP_AUX_MAIN_TIMER_P__AUX_MAIN_TIMER_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_MAIN_TIMER_P__AUX_MAIN_TIMER_WIDTH 16U
+#define MHDP__MHDP_APB_REGS__DP_AUX_MAIN_TIMER_P__RESERVED_0_MASK 0xFFFF0000U
+#define MHDP__MHDP_APB_REGS__DP_AUX_MAIN_TIMER_P__RESERVED_0_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__DP_AUX_MAIN_TIMER_P__RESERVED_0_WIDTH 16U
+
+#define MHDP__MHDP_APB_REGS__DP_AUX_AFE_OUT_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DP_AUX_AFE_OUT_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DP_AUX_AFE_OUT_P__AUX_HOST_AFE_IF_TEST_EN_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__DP_AUX_AFE_OUT_P__AUX_HOST_AFE_IF_TEST_EN_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_AFE_OUT_P__AUX_HOST_AFE_IF_TEST_EN_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__DP_AUX_AFE_OUT_P__AUX_HOST_AFE_IF_TEST_EN_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_AFE_OUT_P__AUX_HOST_AFE_IF_TEST_EN_WOSET 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_AFE_OUT_P__AUX_HOST_AUX_AFE_CLK_MASK 0x00000002U
+#define MHDP__MHDP_APB_REGS__DP_AUX_AFE_OUT_P__AUX_HOST_AUX_AFE_CLK_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__DP_AUX_AFE_OUT_P__AUX_HOST_AUX_AFE_CLK_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__DP_AUX_AFE_OUT_P__AUX_HOST_AUX_AFE_CLK_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_AFE_OUT_P__AUX_HOST_AUX_AFE_CLK_WOSET 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_AFE_OUT_P__AUX_HOST_AUX_AFE_DATA_MASK 0x00000004U
+#define MHDP__MHDP_APB_REGS__DP_AUX_AFE_OUT_P__AUX_HOST_AUX_AFE_DATA_SHIFT 2U
+#define MHDP__MHDP_APB_REGS__DP_AUX_AFE_OUT_P__AUX_HOST_AUX_AFE_DATA_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__DP_AUX_AFE_OUT_P__AUX_HOST_AUX_AFE_DATA_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_AFE_OUT_P__AUX_HOST_AUX_AFE_DATA_WOSET 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_AFE_OUT_P__AUX_HOST_AUX_AFE_PRECH_MASK 0x00000008U
+#define MHDP__MHDP_APB_REGS__DP_AUX_AFE_OUT_P__AUX_HOST_AUX_AFE_PRECH_SHIFT 3U
+#define MHDP__MHDP_APB_REGS__DP_AUX_AFE_OUT_P__AUX_HOST_AUX_AFE_PRECH_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__DP_AUX_AFE_OUT_P__AUX_HOST_AUX_AFE_PRECH_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_AFE_OUT_P__AUX_HOST_AUX_AFE_PRECH_WOSET 0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_AFE_OUT_P__RESERVED_0_MASK 0xFFFFFFF0U
+#define MHDP__MHDP_APB_REGS__DP_AUX_AFE_OUT_P__RESERVED_0_SHIFT 4U
+#define MHDP__MHDP_APB_REGS__DP_AUX_AFE_OUT_P__RESERVED_0_WIDTH 28U
+
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__MSA_HORIZONTAL_0_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__MSA_HORIZONTAL_0_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__MSA_HORIZONTAL_0_P__PCK_STUFF_HTOTAL_MASK 0x0000FFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__MSA_HORIZONTAL_0_P__PCK_STUFF_HTOTAL_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__MSA_HORIZONTAL_0_P__PCK_STUFF_HTOTAL_WIDTH 16U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__MSA_HORIZONTAL_0_P__PCK_STUFF_HSTART_MASK 0xFFFF0000U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__MSA_HORIZONTAL_0_P__PCK_STUFF_HSTART_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__MSA_HORIZONTAL_0_P__PCK_STUFF_HSTART_WIDTH 16U
+
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__MSA_HORIZONTAL_1_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__MSA_HORIZONTAL_1_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__MSA_HORIZONTAL_1_P__PCK_STUFF_HSYNCWIDTH_MASK 0x00007FFFU
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__MSA_HORIZONTAL_1_P__PCK_STUFF_HSYNCWIDTH_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__MSA_HORIZONTAL_1_P__PCK_STUFF_HSYNCWIDTH_WIDTH 15U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__MSA_HORIZONTAL_1_P__PCK_STUFF_HSYNCPOLARITY_MASK 0x00008000U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__MSA_HORIZONTAL_1_P__PCK_STUFF_HSYNCPOLARITY_SHIFT 15U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__MSA_HORIZONTAL_1_P__PCK_STUFF_HSYNCPOLARITY_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__MSA_HORIZONTAL_1_P__PCK_STUFF_HSYNCPOLARITY_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__MSA_HORIZONTAL_1_P__PCK_STUFF_HSYNCPOLARITY_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__MSA_HORIZONTAL_1_P__PCK_STUFF_HWIDTH_MASK 0xFFFF0000U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__MSA_HORIZONTAL_1_P__PCK_STUFF_HWIDTH_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__MSA_HORIZONTAL_1_P__PCK_STUFF_HWIDTH_WIDTH 16U
+
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__MSA_VERTICAL_0_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__MSA_VERTICAL_0_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__MSA_VERTICAL_0_P__PCK_STUFF_VTOTAL_MASK 0x0000FFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__MSA_VERTICAL_0_P__PCK_STUFF_VTOTAL_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__MSA_VERTICAL_0_P__PCK_STUFF_VTOTAL_WIDTH 16U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__MSA_VERTICAL_0_P__PCK_STUFF_VSTART_MASK 0xFFFF0000U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__MSA_VERTICAL_0_P__PCK_STUFF_VSTART_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__MSA_VERTICAL_0_P__PCK_STUFF_VSTART_WIDTH 16U
+
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__MSA_VERTICAL_1_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__MSA_VERTICAL_1_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__MSA_VERTICAL_1_P__PCK_STUFF_VSYNCWIDTH_MASK 0x00007FFFU
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__MSA_VERTICAL_1_P__PCK_STUFF_VSYNCWIDTH_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__MSA_VERTICAL_1_P__PCK_STUFF_VSYNCWIDTH_WIDTH 15U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__MSA_VERTICAL_1_P__PCK_STUFF_VSYNCPOLARITY_MASK 0x00008000U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__MSA_VERTICAL_1_P__PCK_STUFF_VSYNCPOLARITY_SHIFT 15U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__MSA_VERTICAL_1_P__PCK_STUFF_VSYNCPOLARITY_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__MSA_VERTICAL_1_P__PCK_STUFF_VSYNCPOLARITY_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__MSA_VERTICAL_1_P__PCK_STUFF_VSYNCPOLARITY_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__MSA_VERTICAL_1_P__PCK_STUFF_VHEIGHT_MASK 0xFFFF0000U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__MSA_VERTICAL_1_P__PCK_STUFF_VHEIGHT_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__MSA_VERTICAL_1_P__PCK_STUFF_VHEIGHT_WIDTH 16U
+
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__MSA_MISC_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__MSA_MISC_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__MSA_MISC_P__MSA_MISC0_MASK 0x000000FFU
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__MSA_MISC_P__MSA_MISC0_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__MSA_MISC_P__MSA_MISC0_WIDTH 8U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__MSA_MISC_P__MSA_MISC1_MASK 0x0000FF00U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__MSA_MISC_P__MSA_MISC1_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__MSA_MISC_P__MSA_MISC1_WIDTH 8U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__MSA_MISC_P__MSA_MISC1_INV_MASK 0x00010000U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__MSA_MISC_P__MSA_MISC1_INV_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__MSA_MISC_P__MSA_MISC1_INV_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__MSA_MISC_P__MSA_MISC1_INV_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__MSA_MISC_P__MSA_MISC1_INV_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__MSA_MISC_P__MSA_IN_MID_INTERLACE_EN_MASK 0x00020000U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__MSA_MISC_P__MSA_IN_MID_INTERLACE_EN_SHIFT 17U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__MSA_MISC_P__MSA_IN_MID_INTERLACE_EN_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__MSA_MISC_P__MSA_IN_MID_INTERLACE_EN_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__MSA_MISC_P__MSA_IN_MID_INTERLACE_EN_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__MSA_MISC_P__RESERVED_0_MASK 0xFFFC0000U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__MSA_MISC_P__RESERVED_0_SHIFT 18U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__MSA_MISC_P__RESERVED_0_WIDTH 14U
+
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__STREAM_CONFIG_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__STREAM_CONFIG_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__STREAM_CONFIG_P__STREAM_EN_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__STREAM_CONFIG_P__STREAM_EN_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__STREAM_CONFIG_P__STREAM_EN_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__STREAM_CONFIG_P__STREAM_EN_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__STREAM_CONFIG_P__STREAM_EN_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__STREAM_CONFIG_P__NO_VIDEO_MASK 0x00000002U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__STREAM_CONFIG_P__NO_VIDEO_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__STREAM_CONFIG_P__NO_VIDEO_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__STREAM_CONFIG_P__NO_VIDEO_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__STREAM_CONFIG_P__NO_VIDEO_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__STREAM_CONFIG_P__RESERVED_0_MASK 0xFFFFFFFCU
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__STREAM_CONFIG_P__RESERVED_0_SHIFT 2U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__STREAM_CONFIG_P__RESERVED_0_WIDTH 30U
+
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__AUDIO_PACK_STATUS_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__AUDIO_PACK_STATUS_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__AUDIO_PACK_STATUS_P__AP_FIFO_EMPTY_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__AUDIO_PACK_STATUS_P__AP_FIFO_EMPTY_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__AUDIO_PACK_STATUS_P__AP_FIFO_EMPTY_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__AUDIO_PACK_STATUS_P__AP_FIFO_EMPTY_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__AUDIO_PACK_STATUS_P__AP_FIFO_EMPTY_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__AUDIO_PACK_STATUS_P__AP_FIFO_FULL_MASK 0x00000002U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__AUDIO_PACK_STATUS_P__AP_FIFO_FULL_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__AUDIO_PACK_STATUS_P__AP_FIFO_FULL_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__AUDIO_PACK_STATUS_P__AP_FIFO_FULL_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__AUDIO_PACK_STATUS_P__AP_FIFO_FULL_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__AUDIO_PACK_STATUS_P__AP_AIF_FSM_CURR_ST_MASK 0x00000004U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__AUDIO_PACK_STATUS_P__AP_AIF_FSM_CURR_ST_SHIFT 2U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__AUDIO_PACK_STATUS_P__AP_AIF_FSM_CURR_ST_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__AUDIO_PACK_STATUS_P__AP_AIF_FSM_CURR_ST_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__AUDIO_PACK_STATUS_P__AP_AIF_FSM_CURR_ST_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__AUDIO_PACK_STATUS_P__AP_SDP_TRANSFER_FSM_CURR_ST_MASK 0x00000038U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__AUDIO_PACK_STATUS_P__AP_SDP_TRANSFER_FSM_CURR_ST_SHIFT 3U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__AUDIO_PACK_STATUS_P__AP_SDP_TRANSFER_FSM_CURR_ST_WIDTH 3U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__AUDIO_PACK_STATUS_P__AP_FIFO_RD_FSM_CURR_ST_MASK 0x000000C0U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__AUDIO_PACK_STATUS_P__AP_FIFO_RD_FSM_CURR_ST_SHIFT 6U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__AUDIO_PACK_STATUS_P__AP_FIFO_RD_FSM_CURR_ST_WIDTH 2U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__AUDIO_PACK_STATUS_P__AP_FIFO_WR_FSM_CURR_ST_MASK 0x00000300U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__AUDIO_PACK_STATUS_P__AP_FIFO_WR_FSM_CURR_ST_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__AUDIO_PACK_STATUS_P__AP_FIFO_WR_FSM_CURR_ST_WIDTH 2U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__AUDIO_PACK_STATUS_P__AP_PARITY_FSM_CURRENT_STATE_MASK 0x00001C00U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__AUDIO_PACK_STATUS_P__AP_PARITY_FSM_CURRENT_STATE_SHIFT 10U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__AUDIO_PACK_STATUS_P__AP_PARITY_FSM_CURRENT_STATE_WIDTH 3U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__AUDIO_PACK_STATUS_P__RESERVED_1_MASK 0x0000E000U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__AUDIO_PACK_STATUS_P__RESERVED_1_SHIFT 13U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__AUDIO_PACK_STATUS_P__RESERVED_1_WIDTH 3U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__AUDIO_PACK_STATUS_P__AUDIO_TS_VERSION_MASK 0x003F0000U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__AUDIO_PACK_STATUS_P__AUDIO_TS_VERSION_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__AUDIO_PACK_STATUS_P__AUDIO_TS_VERSION_WIDTH 6U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__AUDIO_PACK_STATUS_P__RESERVED_0_MASK 0xFFC00000U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__AUDIO_PACK_STATUS_P__RESERVED_0_SHIFT 22U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__AUDIO_PACK_STATUS_P__RESERVED_0_WIDTH 10U
+
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__VIF_STATUS_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__VIF_STATUS_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__VIF_STATUS_P__VIF_FIFO_EMPTY_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__VIF_STATUS_P__VIF_FIFO_EMPTY_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__VIF_STATUS_P__VIF_FIFO_EMPTY_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__VIF_STATUS_P__VIF_FIFO_EMPTY_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__VIF_STATUS_P__VIF_FIFO_EMPTY_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__VIF_STATUS_P__VIF_FIFO_FULL_MASK 0x00000002U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__VIF_STATUS_P__VIF_FIFO_FULL_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__VIF_STATUS_P__VIF_FIFO_FULL_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__VIF_STATUS_P__VIF_FIFO_FULL_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__VIF_STATUS_P__VIF_FIFO_FULL_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__VIF_STATUS_P__VIF_WR_CTRL_STATE_MASK 0x000000FCU
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__VIF_STATUS_P__VIF_WR_CTRL_STATE_SHIFT 2U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__VIF_STATUS_P__VIF_WR_CTRL_STATE_WIDTH 6U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__VIF_STATUS_P__VIF_RD_CTRL_STATE_MASK 0x0FFFFF00U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__VIF_STATUS_P__VIF_RD_CTRL_STATE_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__VIF_STATUS_P__VIF_RD_CTRL_STATE_WIDTH 20U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__VIF_STATUS_P__RESERVED_0_MASK 0xF0000000U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__VIF_STATUS_P__RESERVED_0_SHIFT 28U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__VIF_STATUS_P__RESERVED_0_WIDTH 4U
+
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__PCK_STUFF_STATUS_0_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__PCK_STUFF_STATUS_0_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__PCK_STUFF_STATUS_0_P__NO_VIDEO_GEN_STATE_MASK 0x0000001FU
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__PCK_STUFF_STATUS_0_P__NO_VIDEO_GEN_STATE_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__PCK_STUFF_STATUS_0_P__NO_VIDEO_GEN_STATE_WIDTH 5U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__PCK_STUFF_STATUS_0_P__RESERVED_0_MASK 0x000000E0U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__PCK_STUFF_STATUS_0_P__RESERVED_0_SHIFT 5U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__PCK_STUFF_STATUS_0_P__RESERVED_0_WIDTH 3U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__PCK_STUFF_STATUS_0_P__SST_VIDEO_GEN_STATE_MASK 0x00007F00U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__PCK_STUFF_STATUS_0_P__SST_VIDEO_GEN_STATE_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__PCK_STUFF_STATUS_0_P__SST_VIDEO_GEN_STATE_WIDTH 7U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__PCK_STUFF_STATUS_0_P__RESERVED_1_MASK 0x00008000U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__PCK_STUFF_STATUS_0_P__RESERVED_1_SHIFT 15U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__PCK_STUFF_STATUS_0_P__RESERVED_1_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__PCK_STUFF_STATUS_0_P__RESERVED_1_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__PCK_STUFF_STATUS_0_P__RESERVED_1_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__PCK_STUFF_STATUS_0_P__RESERVED_2_MASK 0x00FF0000U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__PCK_STUFF_STATUS_0_P__RESERVED_2_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__PCK_STUFF_STATUS_0_P__RESERVED_2_WIDTH 8U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__PCK_STUFF_STATUS_0_P__MSA_GEN_STATE_MASK 0x7F000000U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__PCK_STUFF_STATUS_0_P__MSA_GEN_STATE_SHIFT 24U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__PCK_STUFF_STATUS_0_P__MSA_GEN_STATE_WIDTH 7U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__PCK_STUFF_STATUS_0_P__RESERVED_3_MASK 0x80000000U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__PCK_STUFF_STATUS_0_P__RESERVED_3_SHIFT 31U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__PCK_STUFF_STATUS_0_P__RESERVED_3_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__PCK_STUFF_STATUS_0_P__RESERVED_3_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__PCK_STUFF_STATUS_0_P__RESERVED_3_WOSET 0U
+
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__PCK_STUFF_STATUS_1_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__PCK_STUFF_STATUS_1_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__PCK_STUFF_STATUS_1_P__SST_SS_GEN_STATE_MASK 0x0000003FU
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__PCK_STUFF_STATUS_1_P__SST_SS_GEN_STATE_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__PCK_STUFF_STATUS_1_P__SST_SS_GEN_STATE_WIDTH 6U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__PCK_STUFF_STATUS_1_P__RESERVED_0_MASK 0x000000C0U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__PCK_STUFF_STATUS_1_P__RESERVED_0_SHIFT 6U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__PCK_STUFF_STATUS_1_P__RESERVED_0_WIDTH 2U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__PCK_STUFF_STATUS_1_P__RESERVED_1_MASK 0xFFFFFF00U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__PCK_STUFF_STATUS_1_P__RESERVED_1_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__PCK_STUFF_STATUS_1_P__RESERVED_1_WIDTH 24U
+
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__INFO_PACK_STATUS_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__INFO_PACK_STATUS_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__INFO_PACK_STATUS_P__INFO_PACK_FIFO_FULL_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__INFO_PACK_STATUS_P__INFO_PACK_FIFO_FULL_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__INFO_PACK_STATUS_P__INFO_PACK_FIFO_FULL_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__INFO_PACK_STATUS_P__INFO_PACK_FIFO_FULL_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__INFO_PACK_STATUS_P__INFO_PACK_FIFO_FULL_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__INFO_PACK_STATUS_P__INFO_PACK_FIFO_EMPTY_MASK 0x00000002U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__INFO_PACK_STATUS_P__INFO_PACK_FIFO_EMPTY_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__INFO_PACK_STATUS_P__INFO_PACK_FIFO_EMPTY_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__INFO_PACK_STATUS_P__INFO_PACK_FIFO_EMPTY_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__INFO_PACK_STATUS_P__INFO_PACK_FIFO_EMPTY_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__INFO_PACK_STATUS_P__IP_PARITY_FSM_CURRENT_STATE_MASK 0x0000001CU
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__INFO_PACK_STATUS_P__IP_PARITY_FSM_CURRENT_STATE_SHIFT 2U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__INFO_PACK_STATUS_P__IP_PARITY_FSM_CURRENT_STATE_WIDTH 3U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__INFO_PACK_STATUS_P__IP_FIFO_WR_FSM_CURRENT_STATE_MASK 0x000000E0U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__INFO_PACK_STATUS_P__IP_FIFO_WR_FSM_CURRENT_STATE_SHIFT 5U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__INFO_PACK_STATUS_P__IP_FIFO_WR_FSM_CURRENT_STATE_WIDTH 3U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__INFO_PACK_STATUS_P__IP_FIFO_RD_FSM_CURRENT_STATE_MASK 0x00000F00U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__INFO_PACK_STATUS_P__IP_FIFO_RD_FSM_CURRENT_STATE_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__INFO_PACK_STATUS_P__IP_FIFO_RD_FSM_CURRENT_STATE_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__INFO_PACK_STATUS_P__IP_SEND_DATA_FSM_CURRENT_STATE_MASK 0x0000F000U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__INFO_PACK_STATUS_P__IP_SEND_DATA_FSM_CURRENT_STATE_SHIFT 12U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__INFO_PACK_STATUS_P__IP_SEND_DATA_FSM_CURRENT_STATE_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__INFO_PACK_STATUS_P__RESERVED_0_MASK 0x00FF0000U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__INFO_PACK_STATUS_P__RESERVED_0_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__INFO_PACK_STATUS_P__RESERVED_0_WIDTH 8U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__INFO_PACK_STATUS_P__IN_VBID_MASK 0xFF000000U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__INFO_PACK_STATUS_P__IN_VBID_SHIFT 24U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__INFO_PACK_STATUS_P__IN_VBID_WIDTH 8U
+
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__STREAM_CONFIG_2_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__STREAM_CONFIG_2_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__STREAM_CONFIG_2_P__MST_SF_EVAL_PERIOD_MASK 0x0000007FU
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__STREAM_CONFIG_2_P__MST_SF_EVAL_PERIOD_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__STREAM_CONFIG_2_P__MST_SF_EVAL_PERIOD_WIDTH 7U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__STREAM_CONFIG_2_P__MST_SF_EVAL_OVR_EN_MASK 0x00000080U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__STREAM_CONFIG_2_P__MST_SF_EVAL_OVR_EN_SHIFT 7U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__STREAM_CONFIG_2_P__MST_SF_EVAL_OVR_EN_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__STREAM_CONFIG_2_P__MST_SF_EVAL_OVR_EN_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__STREAM_CONFIG_2_P__MST_SF_EVAL_OVR_EN_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__STREAM_CONFIG_2_P__CFG_TU_VS_DIFF_MASK 0x00000300U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__STREAM_CONFIG_2_P__CFG_TU_VS_DIFF_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__STREAM_CONFIG_2_P__CFG_TU_VS_DIFF_WIDTH 2U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__STREAM_CONFIG_2_P__MST_SF_EVAL_VAL_SYM_MASK 0x0000FC00U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__STREAM_CONFIG_2_P__MST_SF_EVAL_VAL_SYM_SHIFT 10U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__STREAM_CONFIG_2_P__MST_SF_EVAL_VAL_SYM_WIDTH 6U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__STREAM_CONFIG_2_P__CFG_HSYNC_DELAY_MASK 0x00FF0000U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__STREAM_CONFIG_2_P__CFG_HSYNC_DELAY_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__STREAM_CONFIG_2_P__CFG_HSYNC_DELAY_WIDTH 8U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__STREAM_CONFIG_2_P__CFG_EN_HSYNC_DELAY_MASK 0x01000000U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__STREAM_CONFIG_2_P__CFG_EN_HSYNC_DELAY_SHIFT 24U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__STREAM_CONFIG_2_P__CFG_EN_HSYNC_DELAY_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__STREAM_CONFIG_2_P__CFG_EN_HSYNC_DELAY_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__STREAM_CONFIG_2_P__CFG_EN_HSYNC_DELAY_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__STREAM_CONFIG_2_P__RESERVED_2_MASK 0xFE000000U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__STREAM_CONFIG_2_P__RESERVED_2_SHIFT 25U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__STREAM_CONFIG_2_P__RESERVED_2_WIDTH 7U
+
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_HORIZONTAL_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_HORIZONTAL_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_HORIZONTAL_P__HSYNCWIDTH_MASK 0x00007FFFU
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_HORIZONTAL_P__HSYNCWIDTH_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_HORIZONTAL_P__HSYNCWIDTH_WIDTH 15U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_HORIZONTAL_P__RESERVED_MASK 0x00008000U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_HORIZONTAL_P__RESERVED_SHIFT 15U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_HORIZONTAL_P__RESERVED_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_HORIZONTAL_P__RESERVED_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_HORIZONTAL_P__RESERVED_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_HORIZONTAL_P__HWIDTH_MASK 0xFFFF0000U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_HORIZONTAL_P__HWIDTH_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_HORIZONTAL_P__HWIDTH_WIDTH 16U
+
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_VERTICAL_0_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_VERTICAL_0_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_VERTICAL_0_P__VHEIGHT_MASK 0x0000FFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_VERTICAL_0_P__VHEIGHT_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_VERTICAL_0_P__VHEIGHT_WIDTH 16U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_VERTICAL_0_P__VSTART_MASK 0xFFFF0000U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_VERTICAL_0_P__VSTART_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_VERTICAL_0_P__VSTART_WIDTH 16U
+
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_VERTICAL_1_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_VERTICAL_1_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_VERTICAL_1_P__VTOTAL_MASK 0x0000FFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_VERTICAL_1_P__VTOTAL_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_VERTICAL_1_P__VTOTAL_WIDTH 16U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_VERTICAL_1_P__VTOTAL_EVEN_MASK 0x00010000U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_VERTICAL_1_P__VTOTAL_EVEN_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_VERTICAL_1_P__VTOTAL_EVEN_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_VERTICAL_1_P__VTOTAL_EVEN_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_VERTICAL_1_P__VTOTAL_EVEN_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_VERTICAL_1_P__RESERVED_0_MASK 0xFFFE0000U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_VERTICAL_1_P__RESERVED_0_SHIFT 17U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_VERTICAL_1_P__RESERVED_0_WIDTH 15U
+
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_BLOCK_SDP_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_BLOCK_SDP_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_BLOCK_SDP_P__BS_SDP_STOP_BLANK_MASK 0x0000FFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_BLOCK_SDP_P__BS_SDP_STOP_BLANK_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_BLOCK_SDP_P__BS_SDP_STOP_BLANK_WIDTH 16U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_BLOCK_SDP_P__BS_SDP_STOP_ACTIVE_MASK 0x7FFF0000U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_BLOCK_SDP_P__BS_SDP_STOP_ACTIVE_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_BLOCK_SDP_P__BS_SDP_STOP_ACTIVE_WIDTH 15U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_BLOCK_SDP_P__BS_SDP_STOP_OVR_EN_MASK 0x80000000U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_BLOCK_SDP_P__BS_SDP_STOP_OVR_EN_SHIFT 31U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_BLOCK_SDP_P__BS_SDP_STOP_OVR_EN_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_BLOCK_SDP_P__BS_SDP_STOP_OVR_EN_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_BLOCK_SDP_P__BS_SDP_STOP_OVR_EN_WOSET 0U
+
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_MST_SLOT_ALLOCATE_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_MST_SLOT_ALLOCATE_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_MST_SLOT_ALLOCATE_P__STREAM_START_SLOT_MASK 0x0000003FU
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_MST_SLOT_ALLOCATE_P__STREAM_START_SLOT_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_MST_SLOT_ALLOCATE_P__STREAM_START_SLOT_WIDTH 6U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_MST_SLOT_ALLOCATE_P__RESERVED_0_MASK 0x000000C0U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_MST_SLOT_ALLOCATE_P__RESERVED_0_SHIFT 6U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_MST_SLOT_ALLOCATE_P__RESERVED_0_WIDTH 2U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_MST_SLOT_ALLOCATE_P__STREAM_END_SLOT_MASK 0x00003F00U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_MST_SLOT_ALLOCATE_P__STREAM_END_SLOT_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_MST_SLOT_ALLOCATE_P__STREAM_END_SLOT_WIDTH 6U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_MST_SLOT_ALLOCATE_P__RESERVED_1_MASK 0xFFFFC000U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_MST_SLOT_ALLOCATE_P__RESERVED_1_SHIFT 14U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_MST_SLOT_ALLOCATE_P__RESERVED_1_WIDTH 18U
+
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__RATE_GOVERNING_CTRL_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__RATE_GOVERNING_CTRL_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__RATE_GOVERNING_CTRL_P__TARG_AV_SLOTS_Y_MASK 0x0000000FU
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__RATE_GOVERNING_CTRL_P__TARG_AV_SLOTS_Y_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__RATE_GOVERNING_CTRL_P__TARG_AV_SLOTS_Y_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__RATE_GOVERNING_CTRL_P__TARG_AV_SLOTS_X_MASK 0x000003F0U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__RATE_GOVERNING_CTRL_P__TARG_AV_SLOTS_X_SHIFT 4U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__RATE_GOVERNING_CTRL_P__TARG_AV_SLOTS_X_WIDTH 6U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__RATE_GOVERNING_CTRL_P__RATE_GOV_EN_MASK 0x00000400U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__RATE_GOVERNING_CTRL_P__RATE_GOV_EN_SHIFT 10U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__RATE_GOVERNING_CTRL_P__RATE_GOV_EN_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__RATE_GOVERNING_CTRL_P__RATE_GOV_EN_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__RATE_GOVERNING_CTRL_P__RATE_GOV_EN_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__RATE_GOVERNING_CTRL_P__RESERVED_MASK 0xFFFFF800U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__RATE_GOVERNING_CTRL_P__RESERVED_SHIFT 11U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__RATE_GOVERNING_CTRL_P__RESERVED_WIDTH 21U
+
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_FRAMER_PXL_REPR_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_FRAMER_PXL_REPR_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_FRAMER_PXL_REPR_P__COLOR_DEPTH_MASK 0x0000001FU
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_FRAMER_PXL_REPR_P__COLOR_DEPTH_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_FRAMER_PXL_REPR_P__COLOR_DEPTH_WIDTH 5U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_FRAMER_PXL_REPR_P__RESERVED_0_MASK 0x000000E0U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_FRAMER_PXL_REPR_P__RESERVED_0_SHIFT 5U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_FRAMER_PXL_REPR_P__RESERVED_0_WIDTH 3U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_FRAMER_PXL_REPR_P__PXL_ENC_FORMAT_MASK 0x00001F00U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_FRAMER_PXL_REPR_P__PXL_ENC_FORMAT_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_FRAMER_PXL_REPR_P__PXL_ENC_FORMAT_WIDTH 5U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_FRAMER_PXL_REPR_P__RESERVED_1_MASK 0x0000E000U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_FRAMER_PXL_REPR_P__RESERVED_1_SHIFT 13U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_FRAMER_PXL_REPR_P__RESERVED_1_WIDTH 3U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_FRAMER_PXL_REPR_P__M_MASK 0x007F0000U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_FRAMER_PXL_REPR_P__M_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_FRAMER_PXL_REPR_P__M_WIDTH 7U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_FRAMER_PXL_REPR_P__RESERVED_2_MASK 0x00800000U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_FRAMER_PXL_REPR_P__RESERVED_2_SHIFT 23U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_FRAMER_PXL_REPR_P__RESERVED_2_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_FRAMER_PXL_REPR_P__RESERVED_2_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_FRAMER_PXL_REPR_P__RESERVED_2_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_FRAMER_PXL_REPR_P__DIFF_MASK 0x7F000000U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_FRAMER_PXL_REPR_P__DIFF_SHIFT 24U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_FRAMER_PXL_REPR_P__DIFF_WIDTH 7U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_FRAMER_PXL_REPR_P__RESERVED_3_MASK 0x80000000U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_FRAMER_PXL_REPR_P__RESERVED_3_SHIFT 31U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_FRAMER_PXL_REPR_P__RESERVED_3_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_FRAMER_PXL_REPR_P__RESERVED_3_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_FRAMER_PXL_REPR_P__RESERVED_3_WOSET 0U
+
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_FRAMER_SP_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_FRAMER_SP_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_FRAMER_SP_P__VSP_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_FRAMER_SP_P__VSP_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_FRAMER_SP_P__VSP_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_FRAMER_SP_P__VSP_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_FRAMER_SP_P__VSP_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_FRAMER_SP_P__HSP_MASK 0x00000002U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_FRAMER_SP_P__HSP_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_FRAMER_SP_P__HSP_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_FRAMER_SP_P__HSP_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_FRAMER_SP_P__HSP_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_FRAMER_SP_P__INTERLACE_EN_MASK 0x00000004U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_FRAMER_SP_P__INTERLACE_EN_SHIFT 2U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_FRAMER_SP_P__INTERLACE_EN_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_FRAMER_SP_P__INTERLACE_EN_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_FRAMER_SP_P__INTERLACE_EN_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_FRAMER_SP_P__FRAMER_3D_EN_MASK 0x00000008U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_FRAMER_SP_P__FRAMER_3D_EN_SHIFT 3U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_FRAMER_SP_P__FRAMER_3D_EN_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_FRAMER_SP_P__FRAMER_3D_EN_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_FRAMER_SP_P__FRAMER_3D_EN_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_FRAMER_SP_P__STACKED_3D_EN_MASK 0x00000010U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_FRAMER_SP_P__STACKED_3D_EN_SHIFT 4U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_FRAMER_SP_P__STACKED_3D_EN_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_FRAMER_SP_P__STACKED_3D_EN_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_FRAMER_SP_P__STACKED_3D_EN_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_FRAMER_SP_P__RESERVED_0_MASK 0xFFFFFFE0U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_FRAMER_SP_P__RESERVED_0_SHIFT 5U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_FRAMER_SP_P__RESERVED_0_WIDTH 27U
+
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__AUDIO_PACK_CONTROL_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__AUDIO_PACK_CONTROL_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__AUDIO_PACK_CONTROL_P__MST_SDP_ID_MASK 0x000000FFU
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__AUDIO_PACK_CONTROL_P__MST_SDP_ID_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__AUDIO_PACK_CONTROL_P__MST_SDP_ID_WIDTH 8U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__AUDIO_PACK_CONTROL_P__AUDIO_PACK_EN_MASK 0x00000100U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__AUDIO_PACK_CONTROL_P__AUDIO_PACK_EN_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__AUDIO_PACK_CONTROL_P__AUDIO_PACK_EN_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__AUDIO_PACK_CONTROL_P__AUDIO_PACK_EN_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__AUDIO_PACK_CONTROL_P__AUDIO_PACK_EN_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__AUDIO_PACK_CONTROL_P__MONO_MASK 0x00000200U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__AUDIO_PACK_CONTROL_P__MONO_SHIFT 9U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__AUDIO_PACK_CONTROL_P__MONO_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__AUDIO_PACK_CONTROL_P__MONO_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__AUDIO_PACK_CONTROL_P__MONO_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__AUDIO_PACK_CONTROL_P__RESERVED_0_MASK 0xFFFFFC00U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__AUDIO_PACK_CONTROL_P__RESERVED_0_SHIFT 10U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__AUDIO_PACK_CONTROL_P__RESERVED_0_WIDTH 22U
+
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__LINE_THRESH_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__LINE_THRESH_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__LINE_THRESH_P__CFG_ACTIVE_LINE_TRESH_MASK 0x0000003FU
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__LINE_THRESH_P__CFG_ACTIVE_LINE_TRESH_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__LINE_THRESH_P__CFG_ACTIVE_LINE_TRESH_WIDTH 6U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__LINE_THRESH_P__RESERVED_MASK 0xFFFFFFC0U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__LINE_THRESH_P__RESERVED_SHIFT 6U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__LINE_THRESH_P__RESERVED_WIDTH 26U
+
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_VB_ID_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_VB_ID_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_VB_ID_P__VB_ID_MASK 0x000000FFU
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_VB_ID_P__VB_ID_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_VB_ID_P__VB_ID_WIDTH 8U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_VB_ID_P__RESERVED_MASK 0xFFFFFF00U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_VB_ID_P__RESERVED_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_VB_ID_P__RESERVED_WIDTH 24U
+
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_FIELDSEQ_3D_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_FIELDSEQ_3D_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_FIELDSEQ_3D_P__FIELD_SEQ_START_MASK 0x0000FFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_FIELDSEQ_3D_P__FIELD_SEQ_START_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_FIELDSEQ_3D_P__FIELD_SEQ_START_WIDTH 16U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_FIELDSEQ_3D_P__FIELD_SEQ_END_MASK 0xFFFF0000U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_FIELDSEQ_3D_P__FIELD_SEQ_END_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_FIELDSEQ_3D_P__FIELD_SEQ_END_WIDTH 16U
+
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_FRONT_BACK_PORCH_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_FRONT_BACK_PORCH_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_FRONT_BACK_PORCH_P__BACK_PORCH_MASK 0x0000FFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_FRONT_BACK_PORCH_P__BACK_PORCH_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_FRONT_BACK_PORCH_P__BACK_PORCH_WIDTH 16U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_FRONT_BACK_PORCH_P__FRONT_PORCH_MASK 0xFFFF0000U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_FRONT_BACK_PORCH_P__FRONT_PORCH_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_FRONT_BACK_PORCH_P__FRONT_PORCH_WIDTH 16U
+
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_BYTE_COUNT_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_BYTE_COUNT_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_BYTE_COUNT_P__BYTE_COUNT_MASK 0x0000FFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_BYTE_COUNT_P__BYTE_COUNT_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_BYTE_COUNT_P__BYTE_COUNT_WIDTH 16U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_BYTE_COUNT_P__BYTES_IN_CHUNK_MASK 0xFFFF0000U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_BYTE_COUNT_P__BYTES_IN_CHUNK_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__MHDP_DPTX_STREAM__DP_BYTE_COUNT_P__BYTES_IN_CHUNK_WIDTH 16U
+
+#define MHDP__MHDP_APB_REGS__CRYPTO_HDCP_REVISION_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__CRYPTO_HDCP_REVISION_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__CRYPTO_HDCP_REVISION_P__CRYPTO_HDCP_14_REV_MASK 0x000003FFU
+#define MHDP__MHDP_APB_REGS__CRYPTO_HDCP_REVISION_P__CRYPTO_HDCP_14_REV_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__CRYPTO_HDCP_REVISION_P__CRYPTO_HDCP_14_REV_WIDTH 10U
+#define MHDP__MHDP_APB_REGS__CRYPTO_HDCP_REVISION_P__CRYPTO_HDCP_22_REV_MASK 0x000FFC00U
+#define MHDP__MHDP_APB_REGS__CRYPTO_HDCP_REVISION_P__CRYPTO_HDCP_22_REV_SHIFT 10U
+#define MHDP__MHDP_APB_REGS__CRYPTO_HDCP_REVISION_P__CRYPTO_HDCP_22_REV_WIDTH 10U
+#define MHDP__MHDP_APB_REGS__CRYPTO_HDCP_REVISION_P__HDCP_CRYP_REV_MASK 0x3FF00000U
+#define MHDP__MHDP_APB_REGS__CRYPTO_HDCP_REVISION_P__HDCP_CRYP_REV_SHIFT 20U
+#define MHDP__MHDP_APB_REGS__CRYPTO_HDCP_REVISION_P__HDCP_CRYP_REV_WIDTH 10U
+#define MHDP__MHDP_APB_REGS__CRYPTO_HDCP_REVISION_P__RESERVED_0_MASK 0xC0000000U
+#define MHDP__MHDP_APB_REGS__CRYPTO_HDCP_REVISION_P__RESERVED_0_SHIFT 30U
+#define MHDP__MHDP_APB_REGS__CRYPTO_HDCP_REVISION_P__RESERVED_0_WIDTH 2U
+
+#define MHDP__MHDP_APB_REGS__HDCP_CRYPTO_CONFIG_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__HDCP_CRYPTO_CONFIG_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__HDCP_CRYPTO_CONFIG_P__CRYPTO_HDCP_FUNCTION_MASK 0x00000007U
+#define MHDP__MHDP_APB_REGS__HDCP_CRYPTO_CONFIG_P__CRYPTO_HDCP_FUNCTION_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__HDCP_CRYPTO_CONFIG_P__CRYPTO_HDCP_FUNCTION_WIDTH 3U
+#define MHDP__MHDP_APB_REGS__HDCP_CRYPTO_CONFIG_P__CRYPTO_SW_RST_MASK 0x00000008U
+#define MHDP__MHDP_APB_REGS__HDCP_CRYPTO_CONFIG_P__CRYPTO_SW_RST_SHIFT 3U
+#define MHDP__MHDP_APB_REGS__HDCP_CRYPTO_CONFIG_P__CRYPTO_SW_RST_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__HDCP_CRYPTO_CONFIG_P__CRYPTO_SW_RST_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__HDCP_CRYPTO_CONFIG_P__CRYPTO_SW_RST_WOSET 0U
+#define MHDP__MHDP_APB_REGS__HDCP_CRYPTO_CONFIG_P__RESERVED_0_MASK 0xFFFFFFF0U
+#define MHDP__MHDP_APB_REGS__HDCP_CRYPTO_CONFIG_P__RESERVED_0_SHIFT 4U
+#define MHDP__MHDP_APB_REGS__HDCP_CRYPTO_CONFIG_P__RESERVED_0_WIDTH 28U
+
+#define MHDP__MHDP_APB_REGS__CRYPTO_INTERRUPT_SOURCE_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__CRYPTO_INTERRUPT_SOURCE_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__CRYPTO_INTERRUPT_SOURCE_P__SHA256_NEXT_MESSAGE_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__CRYPTO_INTERRUPT_SOURCE_P__SHA256_NEXT_MESSAGE_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__CRYPTO_INTERRUPT_SOURCE_P__SHA256_NEXT_MESSAGE_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__CRYPTO_INTERRUPT_SOURCE_P__SHA256_NEXT_MESSAGE_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__CRYPTO_INTERRUPT_SOURCE_P__SHA256_NEXT_MESSAGE_WOSET 0U
+#define MHDP__MHDP_APB_REGS__CRYPTO_INTERRUPT_SOURCE_P__APB_SLVERR_MASK 0x00000002U
+#define MHDP__MHDP_APB_REGS__CRYPTO_INTERRUPT_SOURCE_P__APB_SLVERR_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__CRYPTO_INTERRUPT_SOURCE_P__APB_SLVERR_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__CRYPTO_INTERRUPT_SOURCE_P__APB_SLVERR_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__CRYPTO_INTERRUPT_SOURCE_P__APB_SLVERR_WOSET 0U
+#define MHDP__MHDP_APB_REGS__CRYPTO_INTERRUPT_SOURCE_P__RESERVED_0_MASK 0x000000FCU
+#define MHDP__MHDP_APB_REGS__CRYPTO_INTERRUPT_SOURCE_P__RESERVED_0_SHIFT 2U
+#define MHDP__MHDP_APB_REGS__CRYPTO_INTERRUPT_SOURCE_P__RESERVED_0_WIDTH 6U
+#define MHDP__MHDP_APB_REGS__CRYPTO_INTERRUPT_SOURCE_P__AES_32_DONE_MASK 0x00000100U
+#define MHDP__MHDP_APB_REGS__CRYPTO_INTERRUPT_SOURCE_P__AES_32_DONE_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__CRYPTO_INTERRUPT_SOURCE_P__AES_32_DONE_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__CRYPTO_INTERRUPT_SOURCE_P__AES_32_DONE_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__CRYPTO_INTERRUPT_SOURCE_P__AES_32_DONE_WOSET 0U
+#define MHDP__MHDP_APB_REGS__CRYPTO_INTERRUPT_SOURCE_P__CRYPTO14_KM_DONE_MASK 0x00000200U
+#define MHDP__MHDP_APB_REGS__CRYPTO_INTERRUPT_SOURCE_P__CRYPTO14_KM_DONE_SHIFT 9U
+#define MHDP__MHDP_APB_REGS__CRYPTO_INTERRUPT_SOURCE_P__CRYPTO14_KM_DONE_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__CRYPTO_INTERRUPT_SOURCE_P__CRYPTO14_KM_DONE_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__CRYPTO_INTERRUPT_SOURCE_P__CRYPTO14_KM_DONE_WOSET 0U
+#define MHDP__MHDP_APB_REGS__CRYPTO_INTERRUPT_SOURCE_P__CRYPTO14_PRNM_DONE_MASK 0x00000400U
+#define MHDP__MHDP_APB_REGS__CRYPTO_INTERRUPT_SOURCE_P__CRYPTO14_PRNM_DONE_SHIFT 10U
+#define MHDP__MHDP_APB_REGS__CRYPTO_INTERRUPT_SOURCE_P__CRYPTO14_PRNM_DONE_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__CRYPTO_INTERRUPT_SOURCE_P__CRYPTO14_PRNM_DONE_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__CRYPTO_INTERRUPT_SOURCE_P__CRYPTO14_PRNM_DONE_WOSET 0U
+#define MHDP__MHDP_APB_REGS__CRYPTO_INTERRUPT_SOURCE_P__RESERVED_1_MASK 0xFFFFF800U
+#define MHDP__MHDP_APB_REGS__CRYPTO_INTERRUPT_SOURCE_P__RESERVED_1_SHIFT 11U
+#define MHDP__MHDP_APB_REGS__CRYPTO_INTERRUPT_SOURCE_P__RESERVED_1_WIDTH 21U
+
+#define MHDP__MHDP_APB_REGS__CRYPTO_INTERRUPT_MASK_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__CRYPTO_INTERRUPT_MASK_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__CRYPTO_INTERRUPT_MASK_P__SHA256_NEXT_MESSAGE_MASK_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__CRYPTO_INTERRUPT_MASK_P__SHA256_NEXT_MESSAGE_MASK_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__CRYPTO_INTERRUPT_MASK_P__SHA256_NEXT_MESSAGE_MASK_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__CRYPTO_INTERRUPT_MASK_P__SHA256_NEXT_MESSAGE_MASK_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__CRYPTO_INTERRUPT_MASK_P__SHA256_NEXT_MESSAGE_MASK_WOSET 0U
+#define MHDP__MHDP_APB_REGS__CRYPTO_INTERRUPT_MASK_P__APB_SLVERR_MASK_MASK 0x00000002U
+#define MHDP__MHDP_APB_REGS__CRYPTO_INTERRUPT_MASK_P__APB_SLVERR_MASK_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__CRYPTO_INTERRUPT_MASK_P__APB_SLVERR_MASK_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__CRYPTO_INTERRUPT_MASK_P__APB_SLVERR_MASK_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__CRYPTO_INTERRUPT_MASK_P__APB_SLVERR_MASK_WOSET 0U
+#define MHDP__MHDP_APB_REGS__CRYPTO_INTERRUPT_MASK_P__RESERVED_0_MASK 0x000000FCU
+#define MHDP__MHDP_APB_REGS__CRYPTO_INTERRUPT_MASK_P__RESERVED_0_SHIFT 2U
+#define MHDP__MHDP_APB_REGS__CRYPTO_INTERRUPT_MASK_P__RESERVED_0_WIDTH 6U
+#define MHDP__MHDP_APB_REGS__CRYPTO_INTERRUPT_MASK_P__AES_32_DONE_MASK_MASK 0x00000100U
+#define MHDP__MHDP_APB_REGS__CRYPTO_INTERRUPT_MASK_P__AES_32_DONE_MASK_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__CRYPTO_INTERRUPT_MASK_P__AES_32_DONE_MASK_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__CRYPTO_INTERRUPT_MASK_P__AES_32_DONE_MASK_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__CRYPTO_INTERRUPT_MASK_P__AES_32_DONE_MASK_WOSET 0U
+#define MHDP__MHDP_APB_REGS__CRYPTO_INTERRUPT_MASK_P__CRYPTO14_KM_DONE_MASK_MASK 0x00000200U
+#define MHDP__MHDP_APB_REGS__CRYPTO_INTERRUPT_MASK_P__CRYPTO14_KM_DONE_MASK_SHIFT 9U
+#define MHDP__MHDP_APB_REGS__CRYPTO_INTERRUPT_MASK_P__CRYPTO14_KM_DONE_MASK_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__CRYPTO_INTERRUPT_MASK_P__CRYPTO14_KM_DONE_MASK_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__CRYPTO_INTERRUPT_MASK_P__CRYPTO14_KM_DONE_MASK_WOSET 0U
+#define MHDP__MHDP_APB_REGS__CRYPTO_INTERRUPT_MASK_P__CRYPTO14_PRNM_DONE_MASK_MASK 0x00000400U
+#define MHDP__MHDP_APB_REGS__CRYPTO_INTERRUPT_MASK_P__CRYPTO14_PRNM_DONE_MASK_SHIFT 10U
+#define MHDP__MHDP_APB_REGS__CRYPTO_INTERRUPT_MASK_P__CRYPTO14_PRNM_DONE_MASK_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__CRYPTO_INTERRUPT_MASK_P__CRYPTO14_PRNM_DONE_MASK_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__CRYPTO_INTERRUPT_MASK_P__CRYPTO14_PRNM_DONE_MASK_WOSET 0U
+#define MHDP__MHDP_APB_REGS__CRYPTO_INTERRUPT_MASK_P__RESERVED_1_MASK 0xFFFFF800U
+#define MHDP__MHDP_APB_REGS__CRYPTO_INTERRUPT_MASK_P__RESERVED_1_SHIFT 11U
+#define MHDP__MHDP_APB_REGS__CRYPTO_INTERRUPT_MASK_P__RESERVED_1_WIDTH 21U
+
+#define MHDP__MHDP_APB_REGS__CRYPTO22_CONFIG_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__CRYPTO22_CONFIG_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__CRYPTO22_CONFIG_P__SHA_256_START_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__CRYPTO22_CONFIG_P__SHA_256_START_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__CRYPTO22_CONFIG_P__SHA_256_START_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__CRYPTO22_CONFIG_P__SHA_256_START_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__CRYPTO22_CONFIG_P__SHA_256_START_WOSET 0U
+#define MHDP__MHDP_APB_REGS__CRYPTO22_CONFIG_P__RESERVED_0_MASK 0xFFFFFFFEU
+#define MHDP__MHDP_APB_REGS__CRYPTO22_CONFIG_P__RESERVED_0_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__CRYPTO22_CONFIG_P__RESERVED_0_WIDTH 31U
+
+#define MHDP__MHDP_APB_REGS__CRYPTO22_STATUS_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__CRYPTO22_STATUS_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__CRYPTO22_STATUS_P__SHA_256_STATE_MASK 0x0000000FU
+#define MHDP__MHDP_APB_REGS__CRYPTO22_STATUS_P__SHA_256_STATE_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__CRYPTO22_STATUS_P__SHA_256_STATE_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__CRYPTO22_STATUS_P__AES_32_STATE_MASK 0x000000F0U
+#define MHDP__MHDP_APB_REGS__CRYPTO22_STATUS_P__AES_32_STATE_SHIFT 4U
+#define MHDP__MHDP_APB_REGS__CRYPTO22_STATUS_P__AES_32_STATE_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__CRYPTO22_STATUS_P__SHA256_NEXT_MESSAGE_ST_MASK 0x00000100U
+#define MHDP__MHDP_APB_REGS__CRYPTO22_STATUS_P__SHA256_NEXT_MESSAGE_ST_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__CRYPTO22_STATUS_P__SHA256_NEXT_MESSAGE_ST_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__CRYPTO22_STATUS_P__SHA256_NEXT_MESSAGE_ST_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__CRYPTO22_STATUS_P__SHA256_NEXT_MESSAGE_ST_WOSET 0U
+#define MHDP__MHDP_APB_REGS__CRYPTO22_STATUS_P__AES_32_DONE_ST_MASK 0x00000200U
+#define MHDP__MHDP_APB_REGS__CRYPTO22_STATUS_P__AES_32_DONE_ST_SHIFT 9U
+#define MHDP__MHDP_APB_REGS__CRYPTO22_STATUS_P__AES_32_DONE_ST_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__CRYPTO22_STATUS_P__AES_32_DONE_ST_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__CRYPTO22_STATUS_P__AES_32_DONE_ST_WOSET 0U
+#define MHDP__MHDP_APB_REGS__CRYPTO22_STATUS_P__RESERVED_0_MASK 0xFFFFFC00U
+#define MHDP__MHDP_APB_REGS__CRYPTO22_STATUS_P__RESERVED_0_SHIFT 10U
+#define MHDP__MHDP_APB_REGS__CRYPTO22_STATUS_P__RESERVED_0_WIDTH 22U
+
+#define MHDP__MHDP_APB_REGS__SHA_256_DATA_IN_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__SHA_256_DATA_IN_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__SHA_256_DATA_IN_P__SHA_256_DATA_IN_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__SHA_256_DATA_IN_P__SHA_256_DATA_IN_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__SHA_256_DATA_IN_P__SHA_256_DATA_IN_WIDTH 32U
+
+#define MHDP__MHDP_APB_REGS__SHA_256_DATA_OUT_0_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__SHA_256_DATA_OUT_0_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__SHA_256_DATA_OUT_0_P__SHA_256_DATA_OUT_0_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__SHA_256_DATA_OUT_0_P__SHA_256_DATA_OUT_0_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__SHA_256_DATA_OUT_0_P__SHA_256_DATA_OUT_0_WIDTH 32U
+
+#define MHDP__MHDP_APB_REGS__SHA_256_DATA_OUT_1_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__SHA_256_DATA_OUT_1_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__SHA_256_DATA_OUT_1_P__SHA_256_DATA_OUT_1_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__SHA_256_DATA_OUT_1_P__SHA_256_DATA_OUT_1_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__SHA_256_DATA_OUT_1_P__SHA_256_DATA_OUT_1_WIDTH 32U
+
+#define MHDP__MHDP_APB_REGS__SHA_256_DATA_OUT_2_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__SHA_256_DATA_OUT_2_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__SHA_256_DATA_OUT_2_P__SHA_256_DATA_OUT_2_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__SHA_256_DATA_OUT_2_P__SHA_256_DATA_OUT_2_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__SHA_256_DATA_OUT_2_P__SHA_256_DATA_OUT_2_WIDTH 32U
+
+#define MHDP__MHDP_APB_REGS__SHA_256_DATA_OUT_3_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__SHA_256_DATA_OUT_3_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__SHA_256_DATA_OUT_3_P__SHA_256_DATA_OUT_3_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__SHA_256_DATA_OUT_3_P__SHA_256_DATA_OUT_3_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__SHA_256_DATA_OUT_3_P__SHA_256_DATA_OUT_3_WIDTH 32U
+
+#define MHDP__MHDP_APB_REGS__SHA_256_DATA_OUT_4_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__SHA_256_DATA_OUT_4_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__SHA_256_DATA_OUT_4_P__SHA_256_DATA_OUT_4_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__SHA_256_DATA_OUT_4_P__SHA_256_DATA_OUT_4_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__SHA_256_DATA_OUT_4_P__SHA_256_DATA_OUT_4_WIDTH 32U
+
+#define MHDP__MHDP_APB_REGS__SHA_256_DATA_OUT_5_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__SHA_256_DATA_OUT_5_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__SHA_256_DATA_OUT_5_P__SHA_256_DATA_OUT_5_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__SHA_256_DATA_OUT_5_P__SHA_256_DATA_OUT_5_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__SHA_256_DATA_OUT_5_P__SHA_256_DATA_OUT_5_WIDTH 32U
+
+#define MHDP__MHDP_APB_REGS__SHA_256_DATA_OUT_6_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__SHA_256_DATA_OUT_6_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__SHA_256_DATA_OUT_6_P__SHA_256_DATA_OUT_6_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__SHA_256_DATA_OUT_6_P__SHA_256_DATA_OUT_6_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__SHA_256_DATA_OUT_6_P__SHA_256_DATA_OUT_6_WIDTH 32U
+
+#define MHDP__MHDP_APB_REGS__SHA_256_DATA_OUT_7_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__SHA_256_DATA_OUT_7_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__SHA_256_DATA_OUT_7_P__SHA_256_DATA_OUT_7_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__SHA_256_DATA_OUT_7_P__SHA_256_DATA_OUT_7_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__SHA_256_DATA_OUT_7_P__SHA_256_DATA_OUT_7_WIDTH 32U
+
+#define MHDP__MHDP_APB_REGS__AES_32_KEY_0_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__AES_32_KEY_0_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__AES_32_KEY_0_P__AES_32_KEY_0_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__AES_32_KEY_0_P__AES_32_KEY_0_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__AES_32_KEY_0_P__AES_32_KEY_0_WIDTH 32U
+
+#define MHDP__MHDP_APB_REGS__AES_32_KEY_1_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__AES_32_KEY_1_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__AES_32_KEY_1_P__AES_32_KEY_1_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__AES_32_KEY_1_P__AES_32_KEY_1_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__AES_32_KEY_1_P__AES_32_KEY_1_WIDTH 32U
+
+#define MHDP__MHDP_APB_REGS__AES_32_KEY_2_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__AES_32_KEY_2_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__AES_32_KEY_2_P__AES_32_KEY_2_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__AES_32_KEY_2_P__AES_32_KEY_2_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__AES_32_KEY_2_P__AES_32_KEY_2_WIDTH 32U
+
+#define MHDP__MHDP_APB_REGS__AES_32_KEY_3_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__AES_32_KEY_3_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__AES_32_KEY_3_P__AES_32_KEY_3_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__AES_32_KEY_3_P__AES_32_KEY_3_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__AES_32_KEY_3_P__AES_32_KEY_3_WIDTH 32U
+
+#define MHDP__MHDP_APB_REGS__AES_32_DATA_IN_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__AES_32_DATA_IN_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__AES_32_DATA_IN_P__AES_32_DATA_IN_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__AES_32_DATA_IN_P__AES_32_DATA_IN_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__AES_32_DATA_IN_P__AES_32_DATA_IN_WIDTH 32U
+
+#define MHDP__MHDP_APB_REGS__AES_32_DATA_OUT_0_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__AES_32_DATA_OUT_0_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__AES_32_DATA_OUT_0_P__AES_32_DATA_OUT_0_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__AES_32_DATA_OUT_0_P__AES_32_DATA_OUT_0_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__AES_32_DATA_OUT_0_P__AES_32_DATA_OUT_0_WIDTH 32U
+
+#define MHDP__MHDP_APB_REGS__AES_32_DATA_OUT_1_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__AES_32_DATA_OUT_1_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__AES_32_DATA_OUT_1_P__AES_32_DATA_OUT_1_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__AES_32_DATA_OUT_1_P__AES_32_DATA_OUT_1_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__AES_32_DATA_OUT_1_P__AES_32_DATA_OUT_1_WIDTH 32U
+
+#define MHDP__MHDP_APB_REGS__AES_32_DATA_OUT_2_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__AES_32_DATA_OUT_2_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__AES_32_DATA_OUT_2_P__AES_32_DATA_OUT_2_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__AES_32_DATA_OUT_2_P__AES_32_DATA_OUT_2_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__AES_32_DATA_OUT_2_P__AES_32_DATA_OUT_2_WIDTH 32U
+
+#define MHDP__MHDP_APB_REGS__AES_32_DATA_OUT_3_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__AES_32_DATA_OUT_3_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__AES_32_DATA_OUT_3_P__AES_32_DATA_OUT_3_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__AES_32_DATA_OUT_3_P__AES_32_DATA_OUT_3_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__AES_32_DATA_OUT_3_P__AES_32_DATA_OUT_3_WIDTH 32U
+
+#define MHDP__MHDP_APB_REGS__CRYPTO14_CONFIG_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__CRYPTO14_CONFIG_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__CRYPTO14_CONFIG_P__VALID_KSV_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_CONFIG_P__VALID_KSV_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_CONFIG_P__VALID_KSV_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_CONFIG_P__VALID_KSV_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_CONFIG_P__VALID_KSV_WOSET 0U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_CONFIG_P__GET_KSV_MASK 0x00000002U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_CONFIG_P__GET_KSV_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_CONFIG_P__GET_KSV_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_CONFIG_P__GET_KSV_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_CONFIG_P__GET_KSV_WOSET 0U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_CONFIG_P__START_BLOCK_SEQ_MASK 0x00000004U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_CONFIG_P__START_BLOCK_SEQ_SHIFT 2U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_CONFIG_P__START_BLOCK_SEQ_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_CONFIG_P__START_BLOCK_SEQ_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_CONFIG_P__START_BLOCK_SEQ_WOSET 0U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_CONFIG_P__CRYPTO_START_FREE_RUN_MASK 0x00000008U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_CONFIG_P__CRYPTO_START_FREE_RUN_SHIFT 3U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_CONFIG_P__CRYPTO_START_FREE_RUN_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_CONFIG_P__CRYPTO_START_FREE_RUN_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_CONFIG_P__CRYPTO_START_FREE_RUN_WOSET 0U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_CONFIG_P__START_REKEY_MASK 0x00000010U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_CONFIG_P__START_REKEY_SHIFT 4U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_CONFIG_P__START_REKEY_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_CONFIG_P__START_REKEY_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_CONFIG_P__START_REKEY_WOSET 0U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_CONFIG_P__HDCP_REPEATER_MASK 0x00000020U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_CONFIG_P__HDCP_REPEATER_SHIFT 5U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_CONFIG_P__HDCP_REPEATER_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_CONFIG_P__HDCP_REPEATER_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_CONFIG_P__HDCP_REPEATER_WOSET 0U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_CONFIG_P__HDCP_AUTHENTICATED_MASK 0x00000040U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_CONFIG_P__HDCP_AUTHENTICATED_SHIFT 6U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_CONFIG_P__HDCP_AUTHENTICATED_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_CONFIG_P__HDCP_AUTHENTICATED_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_CONFIG_P__HDCP_AUTHENTICATED_WOSET 0U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_CONFIG_P__RESERVED_0_MASK 0xFFFFFF80U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_CONFIG_P__RESERVED_0_SHIFT 7U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_CONFIG_P__RESERVED_0_WIDTH 25U
+
+#define MHDP__MHDP_APB_REGS__CRYPTO14_STATUS_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__CRYPTO14_STATUS_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__CRYPTO14_STATUS_P__KM_DONE_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_STATUS_P__KM_DONE_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_STATUS_P__KM_DONE_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_STATUS_P__KM_DONE_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_STATUS_P__KM_DONE_WOSET 0U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_STATUS_P__RESERVED_0_MASK 0x00000002U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_STATUS_P__RESERVED_0_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_STATUS_P__RESERVED_0_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_STATUS_P__RESERVED_0_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_STATUS_P__RESERVED_0_WOSET 0U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_STATUS_P__PRNM_DONE_MASK 0x00000004U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_STATUS_P__PRNM_DONE_SHIFT 2U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_STATUS_P__PRNM_DONE_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_STATUS_P__PRNM_DONE_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_STATUS_P__PRNM_DONE_WOSET 0U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_STATUS_P__DKS_STATE_MASK 0x00000038U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_STATUS_P__DKS_STATE_SHIFT 3U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_STATUS_P__DKS_STATE_WIDTH 3U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_STATUS_P__RESERVED_1_MASK 0x000001C0U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_STATUS_P__RESERVED_1_SHIFT 6U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_STATUS_P__RESERVED_1_WIDTH 3U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_STATUS_P__SHA1_STATE_MASK 0x00000E00U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_STATUS_P__SHA1_STATE_SHIFT 9U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_STATUS_P__SHA1_STATE_WIDTH 3U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_STATUS_P__RESERVED_2_MASK 0x0001F000U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_STATUS_P__RESERVED_2_SHIFT 12U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_STATUS_P__RESERVED_2_WIDTH 5U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_STATUS_P__SHA1_NEXT_MSG_MASK 0x00020000U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_STATUS_P__SHA1_NEXT_MSG_SHIFT 17U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_STATUS_P__SHA1_NEXT_MSG_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_STATUS_P__SHA1_NEXT_MSG_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_STATUS_P__SHA1_NEXT_MSG_WOSET 0U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_STATUS_P__SHA1_V_READY_MASK 0x00040000U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_STATUS_P__SHA1_V_READY_SHIFT 18U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_STATUS_P__SHA1_V_READY_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_STATUS_P__SHA1_V_READY_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_STATUS_P__SHA1_V_READY_WOSET 0U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_STATUS_P__CRYPTO14_STATE_MASK 0x00180000U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_STATUS_P__CRYPTO14_STATE_SHIFT 19U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_STATUS_P__CRYPTO14_STATE_WIDTH 2U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_STATUS_P__RESERVED_3_MASK 0xFFE00000U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_STATUS_P__RESERVED_3_SHIFT 21U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_STATUS_P__RESERVED_3_WIDTH 11U
+
+#define MHDP__MHDP_APB_REGS__CRYPTO14_PRNM_OUT_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__CRYPTO14_PRNM_OUT_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__CRYPTO14_PRNM_OUT_P__PRNM_OUT_MASK 0x00FFFFFFU
+#define MHDP__MHDP_APB_REGS__CRYPTO14_PRNM_OUT_P__PRNM_OUT_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_PRNM_OUT_P__PRNM_OUT_WIDTH 24U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_PRNM_OUT_P__RESERVED_0_MASK 0xFF000000U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_PRNM_OUT_P__RESERVED_0_SHIFT 24U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_PRNM_OUT_P__RESERVED_0_WIDTH 8U
+
+#define MHDP__MHDP_APB_REGS__CRYPTO14_KM_0_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__CRYPTO14_KM_0_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__CRYPTO14_KM_0_P__CRYPTO14_KM_0_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__CRYPTO14_KM_0_P__CRYPTO14_KM_0_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_KM_0_P__CRYPTO14_KM_0_WIDTH 32U
+
+#define MHDP__MHDP_APB_REGS__CRYPTO14_KM_1_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__CRYPTO14_KM_1_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__CRYPTO14_KM_1_P__CRYPTO14_KM_1_MASK 0x00FFFFFFU
+#define MHDP__MHDP_APB_REGS__CRYPTO14_KM_1_P__CRYPTO14_KM_1_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_KM_1_P__CRYPTO14_KM_1_WIDTH 24U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_KM_1_P__RESERVED_0_MASK 0xFF000000U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_KM_1_P__RESERVED_0_SHIFT 24U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_KM_1_P__RESERVED_0_WIDTH 8U
+
+#define MHDP__MHDP_APB_REGS__CRYPTO14_AN_0_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__CRYPTO14_AN_0_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__CRYPTO14_AN_0_P__CRYPTO14_AN_0_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__CRYPTO14_AN_0_P__CRYPTO14_AN_0_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_AN_0_P__CRYPTO14_AN_0_WIDTH 32U
+
+#define MHDP__MHDP_APB_REGS__CRYPTO14_AN_1_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__CRYPTO14_AN_1_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__CRYPTO14_AN_1_P__CRYPTO14_AN_1_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__CRYPTO14_AN_1_P__CRYPTO14_AN_1_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_AN_1_P__CRYPTO14_AN_1_WIDTH 32U
+
+#define MHDP__MHDP_APB_REGS__CRYPTO14_YOUR_KSV_0_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__CRYPTO14_YOUR_KSV_0_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__CRYPTO14_YOUR_KSV_0_P__CRYPTO14_YOUR_KSV_0_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__CRYPTO14_YOUR_KSV_0_P__CRYPTO14_YOUR_KSV_0_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_YOUR_KSV_0_P__CRYPTO14_YOUR_KSV_0_WIDTH 32U
+
+#define MHDP__MHDP_APB_REGS__CRYPTO14_YOUR_KSV_1_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__CRYPTO14_YOUR_KSV_1_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__CRYPTO14_YOUR_KSV_1_P__CRYPTO14_YOUR_KSV_1_MASK 0x000000FFU
+#define MHDP__MHDP_APB_REGS__CRYPTO14_YOUR_KSV_1_P__CRYPTO14_YOUR_KSV_1_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_YOUR_KSV_1_P__CRYPTO14_YOUR_KSV_1_WIDTH 8U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_YOUR_KSV_1_P__RESERVED_0_MASK 0xFFFFFF00U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_YOUR_KSV_1_P__RESERVED_0_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_YOUR_KSV_1_P__RESERVED_0_WIDTH 24U
+
+#define MHDP__MHDP_APB_REGS__CRYPTO14_MI_0_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__CRYPTO14_MI_0_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__CRYPTO14_MI_0_P__CRYPTO14_MI_0_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__CRYPTO14_MI_0_P__CRYPTO14_MI_0_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_MI_0_P__CRYPTO14_MI_0_WIDTH 32U
+
+#define MHDP__MHDP_APB_REGS__CRYPTO14_MI_1_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__CRYPTO14_MI_1_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__CRYPTO14_MI_1_P__CRYPTO14_MI_1_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__CRYPTO14_MI_1_P__CRYPTO14_MI_1_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_MI_1_P__CRYPTO14_MI_1_WIDTH 32U
+
+#define MHDP__MHDP_APB_REGS__CRYPTO14_TI_0_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__CRYPTO14_TI_0_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__CRYPTO14_TI_0_P__CRYPTO14_TI_0_MASK 0x0000FFFFU
+#define MHDP__MHDP_APB_REGS__CRYPTO14_TI_0_P__CRYPTO14_TI_0_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_TI_0_P__CRYPTO14_TI_0_WIDTH 16U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_TI_0_P__RESERVED_0_MASK 0xFFFF0000U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_TI_0_P__RESERVED_0_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_TI_0_P__RESERVED_0_WIDTH 16U
+
+#define MHDP__MHDP_APB_REGS__CRYPTO14_KI_0_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__CRYPTO14_KI_0_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__CRYPTO14_KI_0_P__CRYPTO14_KI_0_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__CRYPTO14_KI_0_P__CRYPTO14_KI_0_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_KI_0_P__CRYPTO14_KI_0_WIDTH 32U
+
+#define MHDP__MHDP_APB_REGS__CRYPTO14_KI_1_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__CRYPTO14_KI_1_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__CRYPTO14_KI_1_P__CRYPTO14_KI_1_MASK 0x00FFFFFFU
+#define MHDP__MHDP_APB_REGS__CRYPTO14_KI_1_P__CRYPTO14_KI_1_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_KI_1_P__CRYPTO14_KI_1_WIDTH 24U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_KI_1_P__RESERVED_0_MASK 0xFF000000U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_KI_1_P__RESERVED_0_SHIFT 24U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_KI_1_P__RESERVED_0_WIDTH 8U
+
+#define MHDP__MHDP_APB_REGS__CRYPTO14_BLOCKS_NUM_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__CRYPTO14_BLOCKS_NUM_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__CRYPTO14_BLOCKS_NUM_P__BLOCKS_NUM_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__CRYPTO14_BLOCKS_NUM_P__BLOCKS_NUM_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_BLOCKS_NUM_P__BLOCKS_NUM_WIDTH 32U
+
+#define MHDP__MHDP_APB_REGS__CRYPTO14_KEY_MEM_DATA_0_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__CRYPTO14_KEY_MEM_DATA_0_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__CRYPTO14_KEY_MEM_DATA_0_P__KEY_MEM_DATA_0_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__CRYPTO14_KEY_MEM_DATA_0_P__KEY_MEM_DATA_0_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_KEY_MEM_DATA_0_P__KEY_MEM_DATA_0_WIDTH 32U
+
+#define MHDP__MHDP_APB_REGS__CRYPTO14_KEY_MEM_DATA_1_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__CRYPTO14_KEY_MEM_DATA_1_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__CRYPTO14_KEY_MEM_DATA_1_P__KEY_MEM_DATA_1_MASK 0x00FFFFFFU
+#define MHDP__MHDP_APB_REGS__CRYPTO14_KEY_MEM_DATA_1_P__KEY_MEM_DATA_1_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_KEY_MEM_DATA_1_P__KEY_MEM_DATA_1_WIDTH 24U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_KEY_MEM_DATA_1_P__RESERVED_0_MASK 0xFF000000U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_KEY_MEM_DATA_1_P__RESERVED_0_SHIFT 24U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_KEY_MEM_DATA_1_P__RESERVED_0_WIDTH 8U
+
+#define MHDP__MHDP_APB_REGS__CRYPTO14_SHA1_MSG_DATA_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__CRYPTO14_SHA1_MSG_DATA_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__CRYPTO14_SHA1_MSG_DATA_P__SHA1_MSG_DATA_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__CRYPTO14_SHA1_MSG_DATA_P__SHA1_MSG_DATA_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_SHA1_MSG_DATA_P__SHA1_MSG_DATA_WIDTH 32U
+
+#define MHDP__MHDP_APB_REGS__CRYPTO14_SHA1_V_VALUE_0_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__CRYPTO14_SHA1_V_VALUE_0_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__CRYPTO14_SHA1_V_VALUE_0_P__V_VALUE_0_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__CRYPTO14_SHA1_V_VALUE_0_P__V_VALUE_0_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_SHA1_V_VALUE_0_P__V_VALUE_0_WIDTH 32U
+
+#define MHDP__MHDP_APB_REGS__CRYPTO14_SHA1_V_VALUE_1_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__CRYPTO14_SHA1_V_VALUE_1_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__CRYPTO14_SHA1_V_VALUE_1_P__V_VALUE_1_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__CRYPTO14_SHA1_V_VALUE_1_P__V_VALUE_1_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_SHA1_V_VALUE_1_P__V_VALUE_1_WIDTH 32U
+
+#define MHDP__MHDP_APB_REGS__CRYPTO14_SHA1_V_VALUE_2_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__CRYPTO14_SHA1_V_VALUE_2_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__CRYPTO14_SHA1_V_VALUE_2_P__V_VALUE_2_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__CRYPTO14_SHA1_V_VALUE_2_P__V_VALUE_2_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_SHA1_V_VALUE_2_P__V_VALUE_2_WIDTH 32U
+
+#define MHDP__MHDP_APB_REGS__CRYPTO14_SHA1_V_VALUE_3_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__CRYPTO14_SHA1_V_VALUE_3_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__CRYPTO14_SHA1_V_VALUE_3_P__V_VALUE_3_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__CRYPTO14_SHA1_V_VALUE_3_P__V_VALUE_3_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_SHA1_V_VALUE_3_P__V_VALUE_3_WIDTH 32U
+
+#define MHDP__MHDP_APB_REGS__CRYPTO14_SHA1_V_VALUE_4_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__CRYPTO14_SHA1_V_VALUE_4_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__CRYPTO14_SHA1_V_VALUE_4_P__V_VALUE_4_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__CRYPTO14_SHA1_V_VALUE_4_P__V_VALUE_4_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__CRYPTO14_SHA1_V_VALUE_4_P__V_VALUE_4_WIDTH 32U
+
+#define MHDP__MHDP_APB_REGS__IRAM_REG_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__IRAM_REG_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__IRAM_REG_P__IRAM_DATA_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__IRAM_REG_P__IRAM_DATA_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__IRAM_REG_P__IRAM_DATA_WIDTH 32U
+
+#define MHDP__MHDP_APB_REGS__DRAM_REG_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DRAM_REG_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DRAM_REG_P__DRAM_DATA_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__DRAM_REG_P__DRAM_DATA_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__DRAM_REG_P__DRAM_DATA_WIDTH 32U
+
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__AUDIO_SRC_CNTL_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__AUDIO_SRC_CNTL_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__AUDIO_SRC_CNTL_P__SW_RST_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__AUDIO_SRC_CNTL_P__SW_RST_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__AUDIO_SRC_CNTL_P__SW_RST_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__AUDIO_SRC_CNTL_P__SW_RST_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__AUDIO_SRC_CNTL_P__SW_RST_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__AUDIO_SRC_CNTL_P__I2S_DEC_START_MASK 0x00000002U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__AUDIO_SRC_CNTL_P__I2S_DEC_START_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__AUDIO_SRC_CNTL_P__I2S_DEC_START_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__AUDIO_SRC_CNTL_P__I2S_DEC_START_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__AUDIO_SRC_CNTL_P__I2S_DEC_START_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__AUDIO_SRC_CNTL_P__I2S_BLOCK_START_FORCE_MASK 0x00000004U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__AUDIO_SRC_CNTL_P__I2S_BLOCK_START_FORCE_SHIFT 2U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__AUDIO_SRC_CNTL_P__I2S_BLOCK_START_FORCE_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__AUDIO_SRC_CNTL_P__I2S_BLOCK_START_FORCE_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__AUDIO_SRC_CNTL_P__I2S_BLOCK_START_FORCE_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__AUDIO_SRC_CNTL_P__SPDIF_TS_EN_MASK 0x00000008U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__AUDIO_SRC_CNTL_P__SPDIF_TS_EN_SHIFT 3U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__AUDIO_SRC_CNTL_P__SPDIF_TS_EN_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__AUDIO_SRC_CNTL_P__SPDIF_TS_EN_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__AUDIO_SRC_CNTL_P__SPDIF_TS_EN_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__AUDIO_SRC_CNTL_P__I2S_TS_EN_MASK 0x00000010U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__AUDIO_SRC_CNTL_P__I2S_TS_EN_SHIFT 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__AUDIO_SRC_CNTL_P__I2S_TS_EN_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__AUDIO_SRC_CNTL_P__I2S_TS_EN_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__AUDIO_SRC_CNTL_P__I2S_TS_EN_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__AUDIO_SRC_CNTL_P__VALID_BITS_FORCE_MASK 0x00000020U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__AUDIO_SRC_CNTL_P__VALID_BITS_FORCE_SHIFT 5U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__AUDIO_SRC_CNTL_P__VALID_BITS_FORCE_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__AUDIO_SRC_CNTL_P__VALID_BITS_FORCE_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__AUDIO_SRC_CNTL_P__VALID_BITS_FORCE_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__AUDIO_SRC_CNTL_P__VALID_ALL_MASK 0x00000040U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__AUDIO_SRC_CNTL_P__VALID_ALL_SHIFT 6U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__AUDIO_SRC_CNTL_P__VALID_ALL_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__AUDIO_SRC_CNTL_P__VALID_ALL_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__AUDIO_SRC_CNTL_P__VALID_ALL_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__AUDIO_SRC_CNTL_P__RESERVED_0_MASK 0xFFFFFF80U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__AUDIO_SRC_CNTL_P__RESERVED_0_SHIFT 7U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__AUDIO_SRC_CNTL_P__RESERVED_0_WIDTH 25U
+
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__AUDIO_SRC_CNFG_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__AUDIO_SRC_CNFG_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__AUDIO_SRC_CNFG_P__LOW_INDEX_MSB_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__AUDIO_SRC_CNFG_P__LOW_INDEX_MSB_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__AUDIO_SRC_CNFG_P__LOW_INDEX_MSB_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__AUDIO_SRC_CNFG_P__LOW_INDEX_MSB_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__AUDIO_SRC_CNFG_P__LOW_INDEX_MSB_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__AUDIO_SRC_CNFG_P__WS_POLARITY_MASK 0x00000002U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__AUDIO_SRC_CNFG_P__WS_POLARITY_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__AUDIO_SRC_CNFG_P__WS_POLARITY_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__AUDIO_SRC_CNFG_P__WS_POLARITY_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__AUDIO_SRC_CNFG_P__WS_POLARITY_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__AUDIO_SRC_CNFG_P__AUDIO_CH_NUM_MASK 0x0000007CU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__AUDIO_SRC_CNFG_P__AUDIO_CH_NUM_SHIFT 2U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__AUDIO_SRC_CNFG_P__AUDIO_CH_NUM_WIDTH 5U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__AUDIO_SRC_CNFG_P__AUDIO_SAMPLE_JUST_MASK 0x00000180U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__AUDIO_SRC_CNFG_P__AUDIO_SAMPLE_JUST_SHIFT 7U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__AUDIO_SRC_CNFG_P__AUDIO_SAMPLE_JUST_WIDTH 2U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__AUDIO_SRC_CNFG_P__AUDIO_SAMPLE_WIDTH_MASK 0x00000600U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__AUDIO_SRC_CNFG_P__AUDIO_SAMPLE_WIDTH_SHIFT 9U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__AUDIO_SRC_CNFG_P__AUDIO_SAMPLE_WIDTH_WIDTH 2U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__AUDIO_SRC_CNFG_P__TRANS_SMPL_WIDTH_MASK 0x00001800U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__AUDIO_SRC_CNFG_P__TRANS_SMPL_WIDTH_SHIFT 11U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__AUDIO_SRC_CNFG_P__TRANS_SMPL_WIDTH_WIDTH 2U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__AUDIO_SRC_CNFG_P__AUDIO_CHANNEL_TYPE_MASK 0x0001E000U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__AUDIO_SRC_CNFG_P__AUDIO_CHANNEL_TYPE_SHIFT 13U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__AUDIO_SRC_CNFG_P__AUDIO_CHANNEL_TYPE_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__AUDIO_SRC_CNFG_P__I2S_DEC_PORT_EN_MASK 0x001E0000U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__AUDIO_SRC_CNFG_P__I2S_DEC_PORT_EN_SHIFT 17U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__AUDIO_SRC_CNFG_P__I2S_DEC_PORT_EN_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__AUDIO_SRC_CNFG_P__RESERVED_0_MASK 0xFFE00000U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__AUDIO_SRC_CNFG_P__RESERVED_0_SHIFT 21U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__AUDIO_SRC_CNFG_P__RESERVED_0_WIDTH 11U
+
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__COM_CH_STTS_BITS_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__COM_CH_STTS_BITS_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__COM_CH_STTS_BITS_P__BYTE0_MASK 0x000000FFU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__COM_CH_STTS_BITS_P__BYTE0_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__COM_CH_STTS_BITS_P__BYTE0_WIDTH 8U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__COM_CH_STTS_BITS_P__CATEGORY_CODE_MASK 0x0000FF00U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__COM_CH_STTS_BITS_P__CATEGORY_CODE_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__COM_CH_STTS_BITS_P__CATEGORY_CODE_WIDTH 8U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__COM_CH_STTS_BITS_P__SAMPLING_FREQ_MASK 0x000F0000U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__COM_CH_STTS_BITS_P__SAMPLING_FREQ_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__COM_CH_STTS_BITS_P__SAMPLING_FREQ_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__COM_CH_STTS_BITS_P__CLOCK_ACCURACY_MASK 0x00F00000U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__COM_CH_STTS_BITS_P__CLOCK_ACCURACY_SHIFT 20U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__COM_CH_STTS_BITS_P__CLOCK_ACCURACY_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__COM_CH_STTS_BITS_P__ORIGINAL_SAMP_FREQ_MASK 0x0F000000U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__COM_CH_STTS_BITS_P__ORIGINAL_SAMP_FREQ_SHIFT 24U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__COM_CH_STTS_BITS_P__ORIGINAL_SAMP_FREQ_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__COM_CH_STTS_BITS_P__RESERVED_0_MASK 0xF0000000U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__COM_CH_STTS_BITS_P__RESERVED_0_SHIFT 28U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__COM_CH_STTS_BITS_P__RESERVED_0_WIDTH 4U
+
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH01_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH01_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH01_P__SOURCE_NUM_CH0_MASK 0x0000000FU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH01_P__SOURCE_NUM_CH0_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH01_P__SOURCE_NUM_CH0_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH01_P__CHANNEL_NUM_CH0_MASK 0x000000F0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH01_P__CHANNEL_NUM_CH0_SHIFT 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH01_P__CHANNEL_NUM_CH0_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH01_P__WORD_LENGTH_CH0_MASK 0x00000F00U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH01_P__WORD_LENGTH_CH0_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH01_P__WORD_LENGTH_CH0_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH01_P__SOURCE_NUM_CH1_MASK 0x0000F000U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH01_P__SOURCE_NUM_CH1_SHIFT 12U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH01_P__SOURCE_NUM_CH1_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH01_P__CHANNEL_NUM_CH1_MASK 0x000F0000U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH01_P__CHANNEL_NUM_CH1_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH01_P__CHANNEL_NUM_CH1_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH01_P__WORD_LENGTH_CH1_MASK 0x00F00000U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH01_P__WORD_LENGTH_CH1_SHIFT 20U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH01_P__WORD_LENGTH_CH1_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH01_P__VALID_BITS1_0_MASK 0x03000000U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH01_P__VALID_BITS1_0_SHIFT 24U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH01_P__VALID_BITS1_0_WIDTH 2U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH01_P__RESERVED_0_MASK 0xFC000000U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH01_P__RESERVED_0_SHIFT 26U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH01_P__RESERVED_0_WIDTH 6U
+
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH23_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH23_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH23_P__SOURCE_NUM_CH2_MASK 0x0000000FU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH23_P__SOURCE_NUM_CH2_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH23_P__SOURCE_NUM_CH2_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH23_P__CHANNEL_NUM_CH2_MASK 0x000000F0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH23_P__CHANNEL_NUM_CH2_SHIFT 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH23_P__CHANNEL_NUM_CH2_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH23_P__WORD_LENGTH_CH2_MASK 0x00000F00U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH23_P__WORD_LENGTH_CH2_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH23_P__WORD_LENGTH_CH2_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH23_P__SOURCE_NUM_CH3_MASK 0x0000F000U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH23_P__SOURCE_NUM_CH3_SHIFT 12U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH23_P__SOURCE_NUM_CH3_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH23_P__CHANNEL_NUM_CH3_MASK 0x000F0000U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH23_P__CHANNEL_NUM_CH3_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH23_P__CHANNEL_NUM_CH3_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH23_P__WORD_LENGTH_CH3_MASK 0x00F00000U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH23_P__WORD_LENGTH_CH3_SHIFT 20U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH23_P__WORD_LENGTH_CH3_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH23_P__VALID_BITS3_2_MASK 0x03000000U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH23_P__VALID_BITS3_2_SHIFT 24U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH23_P__VALID_BITS3_2_WIDTH 2U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH23_P__RESERVED_0_MASK 0xFC000000U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH23_P__RESERVED_0_SHIFT 26U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH23_P__RESERVED_0_WIDTH 6U
+
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH45_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH45_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH45_P__SOURCE_NUM_CH4_MASK 0x0000000FU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH45_P__SOURCE_NUM_CH4_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH45_P__SOURCE_NUM_CH4_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH45_P__CHANNEL_NUM_CH4_MASK 0x000000F0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH45_P__CHANNEL_NUM_CH4_SHIFT 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH45_P__CHANNEL_NUM_CH4_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH45_P__WORD_LENGTH_CH4_MASK 0x00000F00U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH45_P__WORD_LENGTH_CH4_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH45_P__WORD_LENGTH_CH4_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH45_P__SOURCE_NUM_CH5_MASK 0x0000F000U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH45_P__SOURCE_NUM_CH5_SHIFT 12U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH45_P__SOURCE_NUM_CH5_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH45_P__CHANNEL_NUM_CH5_MASK 0x000F0000U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH45_P__CHANNEL_NUM_CH5_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH45_P__CHANNEL_NUM_CH5_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH45_P__WORD_LENGTH_CH5_MASK 0x00F00000U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH45_P__WORD_LENGTH_CH5_SHIFT 20U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH45_P__WORD_LENGTH_CH5_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH45_P__VALID_BITS5_4_MASK 0x03000000U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH45_P__VALID_BITS5_4_SHIFT 24U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH45_P__VALID_BITS5_4_WIDTH 2U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH45_P__RESERVED_0_MASK 0xFC000000U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH45_P__RESERVED_0_SHIFT 26U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH45_P__RESERVED_0_WIDTH 6U
+
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH67_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH67_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH67_P__SOURCE_NUM_CH6_MASK 0x0000000FU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH67_P__SOURCE_NUM_CH6_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH67_P__SOURCE_NUM_CH6_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH67_P__CHANNEL_NUM_CH6_MASK 0x000000F0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH67_P__CHANNEL_NUM_CH6_SHIFT 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH67_P__CHANNEL_NUM_CH6_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH67_P__WORD_LENGTH_CH6_MASK 0x00000F00U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH67_P__WORD_LENGTH_CH6_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH67_P__WORD_LENGTH_CH6_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH67_P__SOURCE_NUM_CH7_MASK 0x0000F000U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH67_P__SOURCE_NUM_CH7_SHIFT 12U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH67_P__SOURCE_NUM_CH7_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH67_P__CHANNEL_NUM_CH7_MASK 0x000F0000U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH67_P__CHANNEL_NUM_CH7_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH67_P__CHANNEL_NUM_CH7_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH67_P__WORD_LENGTH_CH7_MASK 0x00F00000U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH67_P__WORD_LENGTH_CH7_SHIFT 20U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH67_P__WORD_LENGTH_CH7_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH67_P__VALID_BITS7_6_MASK 0x03000000U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH67_P__VALID_BITS7_6_SHIFT 24U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH67_P__VALID_BITS7_6_WIDTH 2U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH67_P__RESERVED_0_MASK 0xFC000000U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH67_P__RESERVED_0_SHIFT 26U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH67_P__RESERVED_0_WIDTH 6U
+
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH89_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH89_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH89_P__SOURCE_NUM_CH8_MASK 0x0000000FU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH89_P__SOURCE_NUM_CH8_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH89_P__SOURCE_NUM_CH8_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH89_P__CHANNEL_NUM_CH8_MASK 0x000000F0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH89_P__CHANNEL_NUM_CH8_SHIFT 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH89_P__CHANNEL_NUM_CH8_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH89_P__WORD_LENGTH_CH8_MASK 0x00000F00U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH89_P__WORD_LENGTH_CH8_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH89_P__WORD_LENGTH_CH8_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH89_P__SOURCE_NUM_CH9_MASK 0x0000F000U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH89_P__SOURCE_NUM_CH9_SHIFT 12U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH89_P__SOURCE_NUM_CH9_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH89_P__CHANNEL_NUM_CH9_MASK 0x000F0000U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH89_P__CHANNEL_NUM_CH9_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH89_P__CHANNEL_NUM_CH9_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH89_P__WORD_LENGTH_CH9_MASK 0x00F00000U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH89_P__WORD_LENGTH_CH9_SHIFT 20U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH89_P__WORD_LENGTH_CH9_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH89_P__VALID_BITS9_8_MASK 0x03000000U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH89_P__VALID_BITS9_8_SHIFT 24U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH89_P__VALID_BITS9_8_WIDTH 2U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH89_P__RESERVED_0_MASK 0xFC000000U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH89_P__RESERVED_0_SHIFT 26U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH89_P__RESERVED_0_WIDTH 6U
+
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1011_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1011_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1011_P__SOURCE_NUM_CH10_MASK 0x0000000FU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1011_P__SOURCE_NUM_CH10_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1011_P__SOURCE_NUM_CH10_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1011_P__CHANNEL_NUM_CH10_MASK 0x000000F0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1011_P__CHANNEL_NUM_CH10_SHIFT 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1011_P__CHANNEL_NUM_CH10_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1011_P__WORD_LENGTH_CH10_MASK 0x00000F00U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1011_P__WORD_LENGTH_CH10_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1011_P__WORD_LENGTH_CH10_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1011_P__SOURCE_NUM_CH11_MASK 0x0000F000U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1011_P__SOURCE_NUM_CH11_SHIFT 12U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1011_P__SOURCE_NUM_CH11_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1011_P__CHANNEL_NUM_CH11_MASK 0x000F0000U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1011_P__CHANNEL_NUM_CH11_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1011_P__CHANNEL_NUM_CH11_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1011_P__WORD_LENGTH_CH11_MASK 0x00F00000U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1011_P__WORD_LENGTH_CH11_SHIFT 20U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1011_P__WORD_LENGTH_CH11_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1011_P__VALID_BITS11_10_MASK 0x03000000U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1011_P__VALID_BITS11_10_SHIFT 24U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1011_P__VALID_BITS11_10_WIDTH 2U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1011_P__RESERVED_0_MASK 0xFC000000U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1011_P__RESERVED_0_SHIFT 26U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1011_P__RESERVED_0_WIDTH 6U
+
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1213_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1213_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1213_P__SOURCE_NUM_CH12_MASK 0x0000000FU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1213_P__SOURCE_NUM_CH12_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1213_P__SOURCE_NUM_CH12_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1213_P__CHANNEL_NUM_CH12_MASK 0x000000F0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1213_P__CHANNEL_NUM_CH12_SHIFT 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1213_P__CHANNEL_NUM_CH12_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1213_P__WORD_LENGTH_CH12_MASK 0x00000F00U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1213_P__WORD_LENGTH_CH12_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1213_P__WORD_LENGTH_CH12_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1213_P__SOURCE_NUM_CH13_MASK 0x0000F000U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1213_P__SOURCE_NUM_CH13_SHIFT 12U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1213_P__SOURCE_NUM_CH13_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1213_P__CHANNEL_NUM_CH13_MASK 0x000F0000U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1213_P__CHANNEL_NUM_CH13_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1213_P__CHANNEL_NUM_CH13_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1213_P__WORD_LENGTH_CH13_MASK 0x00F00000U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1213_P__WORD_LENGTH_CH13_SHIFT 20U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1213_P__WORD_LENGTH_CH13_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1213_P__VALID_BITS13_12_MASK 0x03000000U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1213_P__VALID_BITS13_12_SHIFT 24U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1213_P__VALID_BITS13_12_WIDTH 2U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1213_P__RESERVED_0_MASK 0xFC000000U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1213_P__RESERVED_0_SHIFT 26U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1213_P__RESERVED_0_WIDTH 6U
+
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1415_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1415_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1415_P__SOURCE_NUM_CH14_MASK 0x0000000FU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1415_P__SOURCE_NUM_CH14_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1415_P__SOURCE_NUM_CH14_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1415_P__CHANNEL_NUM_CH14_MASK 0x000000F0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1415_P__CHANNEL_NUM_CH14_SHIFT 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1415_P__CHANNEL_NUM_CH14_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1415_P__WORD_LENGTH_CH14_MASK 0x00000F00U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1415_P__WORD_LENGTH_CH14_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1415_P__WORD_LENGTH_CH14_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1415_P__SOURCE_NUM_CH15_MASK 0x0000F000U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1415_P__SOURCE_NUM_CH15_SHIFT 12U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1415_P__SOURCE_NUM_CH15_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1415_P__CHANNEL_NUM_CH15_MASK 0x000F0000U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1415_P__CHANNEL_NUM_CH15_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1415_P__CHANNEL_NUM_CH15_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1415_P__WORD_LENGTH_CH15_MASK 0x00F00000U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1415_P__WORD_LENGTH_CH15_SHIFT 20U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1415_P__WORD_LENGTH_CH15_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1415_P__VALID_BITS15_14_MASK 0x03000000U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1415_P__VALID_BITS15_14_SHIFT 24U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1415_P__VALID_BITS15_14_WIDTH 2U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1415_P__RESERVED_0_MASK 0xFC000000U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1415_P__RESERVED_0_SHIFT 26U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1415_P__RESERVED_0_WIDTH 6U
+
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1617_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1617_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1617_P__SOURCE_NUM_CH16_MASK 0x0000000FU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1617_P__SOURCE_NUM_CH16_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1617_P__SOURCE_NUM_CH16_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1617_P__CHANNEL_NUM_CH16_MASK 0x000000F0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1617_P__CHANNEL_NUM_CH16_SHIFT 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1617_P__CHANNEL_NUM_CH16_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1617_P__WORD_LENGTH_CH16_MASK 0x00000F00U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1617_P__WORD_LENGTH_CH16_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1617_P__WORD_LENGTH_CH16_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1617_P__SOURCE_NUM_CH17_MASK 0x0000F000U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1617_P__SOURCE_NUM_CH17_SHIFT 12U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1617_P__SOURCE_NUM_CH17_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1617_P__CHANNEL_NUM_CH17_MASK 0x000F0000U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1617_P__CHANNEL_NUM_CH17_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1617_P__CHANNEL_NUM_CH17_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1617_P__WORD_LENGTH_CH17_MASK 0x00F00000U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1617_P__WORD_LENGTH_CH17_SHIFT 20U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1617_P__WORD_LENGTH_CH17_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1617_P__VALID_BITS17_16_MASK 0x03000000U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1617_P__VALID_BITS17_16_SHIFT 24U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1617_P__VALID_BITS17_16_WIDTH 2U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1617_P__RESERVED_0_MASK 0xFC000000U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1617_P__RESERVED_0_SHIFT 26U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1617_P__RESERVED_0_WIDTH 6U
+
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1819_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1819_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1819_P__SOURCE_NUM_CH18_MASK 0x0000000FU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1819_P__SOURCE_NUM_CH18_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1819_P__SOURCE_NUM_CH18_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1819_P__CHANNEL_NUM_CH18_MASK 0x000000F0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1819_P__CHANNEL_NUM_CH18_SHIFT 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1819_P__CHANNEL_NUM_CH18_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1819_P__WORD_LENGTH_CH18_MASK 0x00000F00U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1819_P__WORD_LENGTH_CH18_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1819_P__WORD_LENGTH_CH18_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1819_P__SOURCE_NUM_CH19_MASK 0x0000F000U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1819_P__SOURCE_NUM_CH19_SHIFT 12U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1819_P__SOURCE_NUM_CH19_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1819_P__CHANNEL_NUM_CH19_MASK 0x000F0000U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1819_P__CHANNEL_NUM_CH19_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1819_P__CHANNEL_NUM_CH19_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1819_P__WORD_LENGTH_CH19_MASK 0x00F00000U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1819_P__WORD_LENGTH_CH19_SHIFT 20U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1819_P__WORD_LENGTH_CH19_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1819_P__VALID_BITS19_18_MASK 0x03000000U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1819_P__VALID_BITS19_18_SHIFT 24U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1819_P__VALID_BITS19_18_WIDTH 2U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1819_P__RESERVED_0_MASK 0xFC000000U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1819_P__RESERVED_0_SHIFT 26U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH1819_P__RESERVED_0_WIDTH 6U
+
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2021_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2021_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2021_P__SOURCE_NUM_CH20_MASK 0x0000000FU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2021_P__SOURCE_NUM_CH20_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2021_P__SOURCE_NUM_CH20_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2021_P__CHANNEL_NUM_CH20_MASK 0x000000F0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2021_P__CHANNEL_NUM_CH20_SHIFT 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2021_P__CHANNEL_NUM_CH20_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2021_P__WORD_LENGTH_CH20_MASK 0x00000F00U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2021_P__WORD_LENGTH_CH20_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2021_P__WORD_LENGTH_CH20_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2021_P__SOURCE_NUM_CH21_MASK 0x0000F000U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2021_P__SOURCE_NUM_CH21_SHIFT 12U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2021_P__SOURCE_NUM_CH21_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2021_P__CHANNEL_NUM_CH21_MASK 0x000F0000U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2021_P__CHANNEL_NUM_CH21_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2021_P__CHANNEL_NUM_CH21_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2021_P__WORD_LENGTH_CH21_MASK 0x00F00000U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2021_P__WORD_LENGTH_CH21_SHIFT 20U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2021_P__WORD_LENGTH_CH21_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2021_P__VALID_BITS21_20_MASK 0x03000000U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2021_P__VALID_BITS21_20_SHIFT 24U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2021_P__VALID_BITS21_20_WIDTH 2U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2021_P__RESERVED_0_MASK 0xFC000000U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2021_P__RESERVED_0_SHIFT 26U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2021_P__RESERVED_0_WIDTH 6U
+
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2223_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2223_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2223_P__SOURCE_NUM_CH22_MASK 0x0000000FU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2223_P__SOURCE_NUM_CH22_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2223_P__SOURCE_NUM_CH22_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2223_P__CHANNEL_NUM_CH22_MASK 0x000000F0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2223_P__CHANNEL_NUM_CH22_SHIFT 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2223_P__CHANNEL_NUM_CH22_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2223_P__WORD_LENGTH_CH22_MASK 0x00000F00U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2223_P__WORD_LENGTH_CH22_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2223_P__WORD_LENGTH_CH22_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2223_P__SOURCE_NUM_CH23_MASK 0x0000F000U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2223_P__SOURCE_NUM_CH23_SHIFT 12U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2223_P__SOURCE_NUM_CH23_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2223_P__CHANNEL_NUM_CH23_MASK 0x000F0000U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2223_P__CHANNEL_NUM_CH23_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2223_P__CHANNEL_NUM_CH23_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2223_P__WORD_LENGTH_CH23_MASK 0x00F00000U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2223_P__WORD_LENGTH_CH23_SHIFT 20U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2223_P__WORD_LENGTH_CH23_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2223_P__VALID_BITS23_22_MASK 0x03000000U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2223_P__VALID_BITS23_22_SHIFT 24U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2223_P__VALID_BITS23_22_WIDTH 2U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2223_P__RESERVED_0_MASK 0xFC000000U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2223_P__RESERVED_0_SHIFT 26U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2223_P__RESERVED_0_WIDTH 6U
+
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2425_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2425_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2425_P__SOURCE_NUM_CH24_MASK 0x0000000FU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2425_P__SOURCE_NUM_CH24_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2425_P__SOURCE_NUM_CH24_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2425_P__CHANNEL_NUM_CH24_MASK 0x000000F0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2425_P__CHANNEL_NUM_CH24_SHIFT 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2425_P__CHANNEL_NUM_CH24_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2425_P__WORD_LENGTH_CH24_MASK 0x00000F00U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2425_P__WORD_LENGTH_CH24_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2425_P__WORD_LENGTH_CH24_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2425_P__SOURCE_NUM_CH25_MASK 0x0000F000U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2425_P__SOURCE_NUM_CH25_SHIFT 12U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2425_P__SOURCE_NUM_CH25_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2425_P__CHANNEL_NUM_CH25_MASK 0x000F0000U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2425_P__CHANNEL_NUM_CH25_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2425_P__CHANNEL_NUM_CH25_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2425_P__WORD_LENGTH_CH25_MASK 0x00F00000U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2425_P__WORD_LENGTH_CH25_SHIFT 20U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2425_P__WORD_LENGTH_CH25_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2425_P__VALID_BITS25_24_MASK 0x03000000U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2425_P__VALID_BITS25_24_SHIFT 24U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2425_P__VALID_BITS25_24_WIDTH 2U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2425_P__RESERVED_0_MASK 0xFC000000U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2425_P__RESERVED_0_SHIFT 26U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2425_P__RESERVED_0_WIDTH 6U
+
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2627_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2627_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2627_P__SOURCE_NUM_CH26_MASK 0x0000000FU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2627_P__SOURCE_NUM_CH26_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2627_P__SOURCE_NUM_CH26_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2627_P__CHANNEL_NUM_CH26_MASK 0x000000F0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2627_P__CHANNEL_NUM_CH26_SHIFT 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2627_P__CHANNEL_NUM_CH26_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2627_P__WORD_LENGTH_CH26_MASK 0x00000F00U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2627_P__WORD_LENGTH_CH26_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2627_P__WORD_LENGTH_CH26_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2627_P__SOURCE_NUM_CH27_MASK 0x0000F000U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2627_P__SOURCE_NUM_CH27_SHIFT 12U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2627_P__SOURCE_NUM_CH27_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2627_P__CHANNEL_NUM_CH27_MASK 0x000F0000U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2627_P__CHANNEL_NUM_CH27_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2627_P__CHANNEL_NUM_CH27_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2627_P__WORD_LENGTH_CH27_MASK 0x00F00000U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2627_P__WORD_LENGTH_CH27_SHIFT 20U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2627_P__WORD_LENGTH_CH27_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2627_P__VALID_BITS27_26_MASK 0x03000000U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2627_P__VALID_BITS27_26_SHIFT 24U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2627_P__VALID_BITS27_26_WIDTH 2U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2627_P__RESERVED_0_MASK 0xFC000000U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2627_P__RESERVED_0_SHIFT 26U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2627_P__RESERVED_0_WIDTH 6U
+
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2829_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2829_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2829_P__SOURCE_NUM_CH28_MASK 0x0000000FU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2829_P__SOURCE_NUM_CH28_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2829_P__SOURCE_NUM_CH28_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2829_P__CHANNEL_NUM_CH28_MASK 0x000000F0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2829_P__CHANNEL_NUM_CH28_SHIFT 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2829_P__CHANNEL_NUM_CH28_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2829_P__WORD_LENGTH_CH28_MASK 0x00000F00U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2829_P__WORD_LENGTH_CH28_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2829_P__WORD_LENGTH_CH28_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2829_P__SOURCE_NUM_CH29_MASK 0x0000F000U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2829_P__SOURCE_NUM_CH29_SHIFT 12U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2829_P__SOURCE_NUM_CH29_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2829_P__CHANNEL_NUM_CH29_MASK 0x000F0000U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2829_P__CHANNEL_NUM_CH29_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2829_P__CHANNEL_NUM_CH29_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2829_P__WORD_LENGTH_CH29_MASK 0x00F00000U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2829_P__WORD_LENGTH_CH29_SHIFT 20U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2829_P__WORD_LENGTH_CH29_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2829_P__VALID_BITS29_28_MASK 0x03000000U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2829_P__VALID_BITS29_28_SHIFT 24U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2829_P__VALID_BITS29_28_WIDTH 2U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2829_P__RESERVED_0_MASK 0xFC000000U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2829_P__RESERVED_0_SHIFT 26U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH2829_P__RESERVED_0_WIDTH 6U
+
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH3031_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH3031_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH3031_P__SOURCE_NUM_CH30_MASK 0x0000000FU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH3031_P__SOURCE_NUM_CH30_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH3031_P__SOURCE_NUM_CH30_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH3031_P__CHANNEL_NUM_CH30_MASK 0x000000F0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH3031_P__CHANNEL_NUM_CH30_SHIFT 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH3031_P__CHANNEL_NUM_CH30_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH3031_P__WORD_LENGTH_CH30_MASK 0x00000F00U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH3031_P__WORD_LENGTH_CH30_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH3031_P__WORD_LENGTH_CH30_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH3031_P__SOURCE_NUM_CH31_MASK 0x0000F000U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH3031_P__SOURCE_NUM_CH31_SHIFT 12U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH3031_P__SOURCE_NUM_CH31_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH3031_P__CHANNEL_NUM_CH31_MASK 0x000F0000U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH3031_P__CHANNEL_NUM_CH31_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH3031_P__CHANNEL_NUM_CH31_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH3031_P__WORD_LENGTH_CH31_MASK 0x00F00000U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH3031_P__WORD_LENGTH_CH31_SHIFT 20U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH3031_P__WORD_LENGTH_CH31_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH3031_P__VALID_BITS31_30_MASK 0x03000000U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH3031_P__VALID_BITS31_30_SHIFT 24U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH3031_P__VALID_BITS31_30_WIDTH 2U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH3031_P__RESERVED_0_MASK 0xFC000000U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH3031_P__RESERVED_0_SHIFT 26U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__STTS_BIT_CH3031_P__RESERVED_0_WIDTH 6U
+
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CTRL_ADDR_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CTRL_ADDR_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CTRL_ADDR_P__SPDIF_JITTER_AVG_WIN_MASK 0x00000007U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CTRL_ADDR_P__SPDIF_JITTER_AVG_WIN_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CTRL_ADDR_P__SPDIF_JITTER_AVG_WIN_WIDTH 3U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CTRL_ADDR_P__SPDIF_JITTER_THRSH_MASK 0x000007F8U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CTRL_ADDR_P__SPDIF_JITTER_THRSH_SHIFT 3U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CTRL_ADDR_P__SPDIF_JITTER_THRSH_WIDTH 8U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CTRL_ADDR_P__SPDIF_FIFO_MID_RANGE_MASK 0x0007F800U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CTRL_ADDR_P__SPDIF_FIFO_MID_RANGE_SHIFT 11U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CTRL_ADDR_P__SPDIF_FIFO_MID_RANGE_WIDTH 8U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CTRL_ADDR_P__SPDIF_JITTER_BYPASS_MASK 0x00080000U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CTRL_ADDR_P__SPDIF_JITTER_BYPASS_SHIFT 19U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CTRL_ADDR_P__SPDIF_JITTER_BYPASS_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CTRL_ADDR_P__SPDIF_JITTER_BYPASS_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CTRL_ADDR_P__SPDIF_JITTER_BYPASS_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CTRL_ADDR_P__SPDIF_AVG_SEL_MASK 0x00100000U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CTRL_ADDR_P__SPDIF_AVG_SEL_SHIFT 20U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CTRL_ADDR_P__SPDIF_AVG_SEL_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CTRL_ADDR_P__SPDIF_AVG_SEL_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CTRL_ADDR_P__SPDIF_AVG_SEL_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CTRL_ADDR_P__SPDIF_ENABLE_MASK 0x00200000U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CTRL_ADDR_P__SPDIF_ENABLE_SHIFT 21U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CTRL_ADDR_P__SPDIF_ENABLE_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CTRL_ADDR_P__SPDIF_ENABLE_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CTRL_ADDR_P__SPDIF_ENABLE_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CTRL_ADDR_P__SPDIF_JITTER_STATUS_MASK 0x03C00000U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CTRL_ADDR_P__SPDIF_JITTER_STATUS_SHIFT 22U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CTRL_ADDR_P__SPDIF_JITTER_STATUS_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CTRL_ADDR_P__RESERVED_0_MASK 0xFC000000U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CTRL_ADDR_P__RESERVED_0_SHIFT 26U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CTRL_ADDR_P__RESERVED_0_WIDTH 6U
+
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CH1_CS_3100_ADDR_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CH1_CS_3100_ADDR_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CH1_CS_3100_ADDR_P__SPDIF_CH1_ST_STTS_BITS3100_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CH1_CS_3100_ADDR_P__SPDIF_CH1_ST_STTS_BITS3100_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CH1_CS_3100_ADDR_P__SPDIF_CH1_ST_STTS_BITS3100_WIDTH 32U
+
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CH1_CS_6332_ADDR_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CH1_CS_6332_ADDR_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CH1_CS_6332_ADDR_P__SPDIF_CH1_ST_STTS_BITS6332_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CH1_CS_6332_ADDR_P__SPDIF_CH1_ST_STTS_BITS6332_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CH1_CS_6332_ADDR_P__SPDIF_CH1_ST_STTS_BITS6332_WIDTH 32U
+
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CH1_CS_9564_ADDR_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CH1_CS_9564_ADDR_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CH1_CS_9564_ADDR_P__SPDIF_CH1_ST_STTS_BITS9564_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CH1_CS_9564_ADDR_P__SPDIF_CH1_ST_STTS_BITS9564_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CH1_CS_9564_ADDR_P__SPDIF_CH1_ST_STTS_BITS9564_WIDTH 32U
+
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CH1_CS_12796_ADDR_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CH1_CS_12796_ADDR_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CH1_CS_12796_ADDR_P__SPDIF_CH1_ST_STTS_BITS12796_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CH1_CS_12796_ADDR_P__SPDIF_CH1_ST_STTS_BITS12796_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CH1_CS_12796_ADDR_P__SPDIF_CH1_ST_STTS_BITS12796_WIDTH 32U
+
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CH1_CS_159128_ADDR_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CH1_CS_159128_ADDR_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CH1_CS_159128_ADDR_P__SPDIF_CH1_ST_STTS_BITS159128_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CH1_CS_159128_ADDR_P__SPDIF_CH1_ST_STTS_BITS159128_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CH1_CS_159128_ADDR_P__SPDIF_CH1_ST_STTS_BITS159128_WIDTH 32U
+
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CH1_CS_191160_ADDR_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CH1_CS_191160_ADDR_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CH1_CS_191160_ADDR_P__SPDIF_CH1_ST_STTS_BITS191160_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CH1_CS_191160_ADDR_P__SPDIF_CH1_ST_STTS_BITS191160_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CH1_CS_191160_ADDR_P__SPDIF_CH1_ST_STTS_BITS191160_WIDTH 32U
+
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CH2_CS_3100_ADDR_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CH2_CS_3100_ADDR_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CH2_CS_3100_ADDR_P__SPDIF_CH2_ST_STTS_BITS3100_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CH2_CS_3100_ADDR_P__SPDIF_CH2_ST_STTS_BITS3100_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CH2_CS_3100_ADDR_P__SPDIF_CH2_ST_STTS_BITS3100_WIDTH 32U
+
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CH2_CS_6332_ADDR_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CH2_CS_6332_ADDR_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CH2_CS_6332_ADDR_P__SPDIF_CH2_ST_STTS_BITS6332_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CH2_CS_6332_ADDR_P__SPDIF_CH2_ST_STTS_BITS6332_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CH2_CS_6332_ADDR_P__SPDIF_CH2_ST_STTS_BITS6332_WIDTH 32U
+
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CH2_CS_9564_ADDR_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CH2_CS_9564_ADDR_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CH2_CS_9564_ADDR_P__SPDIF_CH2_ST_STTS_BITS9564_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CH2_CS_9564_ADDR_P__SPDIF_CH2_ST_STTS_BITS9564_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CH2_CS_9564_ADDR_P__SPDIF_CH2_ST_STTS_BITS9564_WIDTH 32U
+
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CH2_CS_12796_ADDR_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CH2_CS_12796_ADDR_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CH2_CS_12796_ADDR_P__SPDIF_CH2_ST_STTS_BITS12796_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CH2_CS_12796_ADDR_P__SPDIF_CH2_ST_STTS_BITS12796_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CH2_CS_12796_ADDR_P__SPDIF_CH2_ST_STTS_BITS12796_WIDTH 32U
+
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CH2_CS_159128_ADDR_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CH2_CS_159128_ADDR_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CH2_CS_159128_ADDR_P__SPDIF_CH2_ST_STTS_BITS159128_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CH2_CS_159128_ADDR_P__SPDIF_CH2_ST_STTS_BITS159128_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CH2_CS_159128_ADDR_P__SPDIF_CH2_ST_STTS_BITS159128_WIDTH 32U
+
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CH2_CS_191160_ADDR_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CH2_CS_191160_ADDR_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CH2_CS_191160_ADDR_P__SPDIF_CH2_ST_STTS_BITS191160_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CH2_CS_191160_ADDR_P__SPDIF_CH2_ST_STTS_BITS191160_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SPDIF_CH2_CS_191160_ADDR_P__SPDIF_CH2_ST_STTS_BITS191160_WIDTH 32U
+
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SMPL2PKT_CNTL_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SMPL2PKT_CNTL_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SMPL2PKT_CNTL_P__SW_RST_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SMPL2PKT_CNTL_P__SW_RST_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SMPL2PKT_CNTL_P__SW_RST_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SMPL2PKT_CNTL_P__SW_RST_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SMPL2PKT_CNTL_P__SW_RST_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SMPL2PKT_CNTL_P__SMPL2PKT_EN_MASK 0x00000002U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SMPL2PKT_CNTL_P__SMPL2PKT_EN_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SMPL2PKT_CNTL_P__SMPL2PKT_EN_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SMPL2PKT_CNTL_P__SMPL2PKT_EN_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SMPL2PKT_CNTL_P__SMPL2PKT_EN_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SMPL2PKT_CNTL_P__RESERVED_0_MASK 0xFFFFFFFCU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SMPL2PKT_CNTL_P__RESERVED_0_SHIFT 2U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SMPL2PKT_CNTL_P__RESERVED_0_WIDTH 30U
+
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SMPL2PKT_CNFG_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SMPL2PKT_CNFG_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SMPL2PKT_CNFG_P__MAX_NUM_CH_MASK 0x0000001FU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SMPL2PKT_CNFG_P__MAX_NUM_CH_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SMPL2PKT_CNFG_P__MAX_NUM_CH_WIDTH 5U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SMPL2PKT_CNFG_P__NUM_OF_I2S_PORTS_MASK 0x00000060U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SMPL2PKT_CNFG_P__NUM_OF_I2S_PORTS_SHIFT 5U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SMPL2PKT_CNFG_P__NUM_OF_I2S_PORTS_WIDTH 2U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SMPL2PKT_CNFG_P__AUDIO_TYPE_MASK 0x00000780U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SMPL2PKT_CNFG_P__AUDIO_TYPE_SHIFT 7U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SMPL2PKT_CNFG_P__AUDIO_TYPE_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SMPL2PKT_CNFG_P__CFG_SUB_PCKT_NUM_MASK 0x00003800U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SMPL2PKT_CNFG_P__CFG_SUB_PCKT_NUM_SHIFT 11U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SMPL2PKT_CNFG_P__CFG_SUB_PCKT_NUM_WIDTH 3U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SMPL2PKT_CNFG_P__CFG_BLOCK_LPCM_FIRST_PKT_MASK 0x00004000U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SMPL2PKT_CNFG_P__CFG_BLOCK_LPCM_FIRST_PKT_SHIFT 14U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SMPL2PKT_CNFG_P__CFG_BLOCK_LPCM_FIRST_PKT_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SMPL2PKT_CNFG_P__CFG_BLOCK_LPCM_FIRST_PKT_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SMPL2PKT_CNFG_P__CFG_BLOCK_LPCM_FIRST_PKT_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SMPL2PKT_CNFG_P__CFG_EN_AUTO_SUB_PCKT_NUM_MASK 0x00008000U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SMPL2PKT_CNFG_P__CFG_EN_AUTO_SUB_PCKT_NUM_SHIFT 15U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SMPL2PKT_CNFG_P__CFG_EN_AUTO_SUB_PCKT_NUM_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SMPL2PKT_CNFG_P__CFG_EN_AUTO_SUB_PCKT_NUM_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SMPL2PKT_CNFG_P__CFG_EN_AUTO_SUB_PCKT_NUM_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SMPL2PKT_CNFG_P__CFG_SAMPLE_PRESENT_MASK 0x000F0000U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SMPL2PKT_CNFG_P__CFG_SAMPLE_PRESENT_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SMPL2PKT_CNFG_P__CFG_SAMPLE_PRESENT_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SMPL2PKT_CNFG_P__CFG_SAMPLE_PRESENT_FORCE_MASK 0x00100000U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SMPL2PKT_CNFG_P__CFG_SAMPLE_PRESENT_FORCE_SHIFT 20U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SMPL2PKT_CNFG_P__CFG_SAMPLE_PRESENT_FORCE_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SMPL2PKT_CNFG_P__CFG_SAMPLE_PRESENT_FORCE_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SMPL2PKT_CNFG_P__CFG_SAMPLE_PRESENT_FORCE_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SMPL2PKT_CNFG_P__RESERVED_0_MASK 0xFFE00000U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SMPL2PKT_CNFG_P__RESERVED_0_SHIFT 21U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SMPL2PKT_CNFG_P__RESERVED_0_WIDTH 11U
+
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__FIFO_CNTL_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__FIFO_CNTL_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__FIFO_CNTL_P__FIFO_SW_RST_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__FIFO_CNTL_P__FIFO_SW_RST_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__FIFO_CNTL_P__FIFO_SW_RST_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__FIFO_CNTL_P__FIFO_SW_RST_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__FIFO_CNTL_P__FIFO_SW_RST_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__FIFO_CNTL_P__SYNC_WR_TO_CH_ZERO_MASK 0x00000002U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__FIFO_CNTL_P__SYNC_WR_TO_CH_ZERO_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__FIFO_CNTL_P__SYNC_WR_TO_CH_ZERO_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__FIFO_CNTL_P__SYNC_WR_TO_CH_ZERO_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__FIFO_CNTL_P__SYNC_WR_TO_CH_ZERO_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__FIFO_CNTL_P__FIFO_DIR_MASK 0x00000004U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__FIFO_CNTL_P__FIFO_DIR_SHIFT 2U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__FIFO_CNTL_P__FIFO_DIR_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__FIFO_CNTL_P__FIFO_DIR_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__FIFO_CNTL_P__FIFO_DIR_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__FIFO_CNTL_P__FIFO_EMPTY_CALC_MASK 0x00000008U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__FIFO_CNTL_P__FIFO_EMPTY_CALC_SHIFT 3U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__FIFO_CNTL_P__FIFO_EMPTY_CALC_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__FIFO_CNTL_P__FIFO_EMPTY_CALC_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__FIFO_CNTL_P__FIFO_EMPTY_CALC_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__FIFO_CNTL_P__CFG_DIS_PORT3_MASK 0x00000010U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__FIFO_CNTL_P__CFG_DIS_PORT3_SHIFT 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__FIFO_CNTL_P__CFG_DIS_PORT3_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__FIFO_CNTL_P__CFG_DIS_PORT3_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__FIFO_CNTL_P__CFG_DIS_PORT3_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__FIFO_CNTL_P__RESERVED_0_MASK 0xFFFFFFE0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__FIFO_CNTL_P__RESERVED_0_SHIFT 5U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__FIFO_CNTL_P__RESERVED_0_WIDTH 27U
+
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__FIFO_STTS_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__FIFO_STTS_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__FIFO_STTS_P__WFULL_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__FIFO_STTS_P__WFULL_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__FIFO_STTS_P__WFULL_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__FIFO_STTS_P__WFULL_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__FIFO_STTS_P__WFULL_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__FIFO_STTS_P__REMPTY_MASK 0x00000002U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__FIFO_STTS_P__REMPTY_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__FIFO_STTS_P__REMPTY_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__FIFO_STTS_P__REMPTY_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__FIFO_STTS_P__REMPTY_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__FIFO_STTS_P__OVERRUN_MASK 0x00000004U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__FIFO_STTS_P__OVERRUN_SHIFT 2U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__FIFO_STTS_P__OVERRUN_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__FIFO_STTS_P__OVERRUN_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__FIFO_STTS_P__OVERRUN_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__FIFO_STTS_P__UNDERRUN_MASK 0x00000008U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__FIFO_STTS_P__UNDERRUN_SHIFT 3U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__FIFO_STTS_P__UNDERRUN_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__FIFO_STTS_P__UNDERRUN_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__FIFO_STTS_P__UNDERRUN_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__FIFO_STTS_P__RESERVED_0_MASK 0xFFFFFFF0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__FIFO_STTS_P__RESERVED_0_SHIFT 4U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__FIFO_STTS_P__RESERVED_0_WIDTH 28U
+
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SUB_PCKT_THRSH_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SUB_PCKT_THRSH_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SUB_PCKT_THRSH_P__CFG_MEM_FIFO_THRSH1_MASK 0x000000FFU
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SUB_PCKT_THRSH_P__CFG_MEM_FIFO_THRSH1_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SUB_PCKT_THRSH_P__CFG_MEM_FIFO_THRSH1_WIDTH 8U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SUB_PCKT_THRSH_P__CFG_MEM_FIFO_THRSH2_MASK 0x0000FF00U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SUB_PCKT_THRSH_P__CFG_MEM_FIFO_THRSH2_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SUB_PCKT_THRSH_P__CFG_MEM_FIFO_THRSH2_WIDTH 8U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SUB_PCKT_THRSH_P__CFG_MEM_FIFO_THRSH3_MASK 0x00FF0000U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SUB_PCKT_THRSH_P__CFG_MEM_FIFO_THRSH3_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SUB_PCKT_THRSH_P__CFG_MEM_FIFO_THRSH3_WIDTH 8U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SUB_PCKT_THRSH_P__RESERVED_0_MASK 0xFF000000U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SUB_PCKT_THRSH_P__RESERVED_0_SHIFT 24U
+#define MHDP__MHDP_APB_REGS__MHDP_AUDIO_DECODER__SUB_PCKT_THRSH_P__RESERVED_0_WIDTH 8U
+
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_WR_ADDR_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_WR_ADDR_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_WR_ADDR_P__WR_ADDR_MASK 0x0000000FU
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_WR_ADDR_P__WR_ADDR_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_WR_ADDR_P__WR_ADDR_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_WR_ADDR_P__RESERVED_0_MASK 0xFFFFFFF0U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_WR_ADDR_P__RESERVED_0_SHIFT 4U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_WR_ADDR_P__RESERVED_0_WIDTH 28U
+
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_WR_REQ_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_WR_REQ_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_WR_REQ_P__HOST_WR_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_WR_REQ_P__HOST_WR_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_WR_REQ_P__HOST_WR_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_WR_REQ_P__HOST_WR_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_WR_REQ_P__HOST_WR_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_WR_REQ_P__RESERVED_0_MASK 0xFFFFFFFEU
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_WR_REQ_P__RESERVED_0_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_WR_REQ_P__RESERVED_0_WIDTH 31U
+
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_RD_ADDR_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_RD_ADDR_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_RD_ADDR_P__RD_ADDR_MASK 0x0000000FU
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_RD_ADDR_P__RD_ADDR_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_RD_ADDR_P__RD_ADDR_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_RD_ADDR_P__RESERVED_0_MASK 0xFFFFFFF0U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_RD_ADDR_P__RESERVED_0_SHIFT 4U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_RD_ADDR_P__RESERVED_0_WIDTH 28U
+
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_RD_REQ_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_RD_REQ_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_RD_REQ_P__HOST_RD_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_RD_REQ_P__HOST_RD_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_RD_REQ_P__HOST_RD_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_RD_REQ_P__HOST_RD_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_RD_REQ_P__HOST_RD_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_RD_REQ_P__RESERVED_0_MASK 0xFFFFFFFEU
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_RD_REQ_P__RESERVED_0_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_RD_REQ_P__RESERVED_0_WIDTH 31U
+
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_DATA_WR_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_DATA_WR_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_DATA_WR_P__DATA_WR_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_DATA_WR_P__DATA_WR_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_DATA_WR_P__DATA_WR_WIDTH 32U
+
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_DATA_RD_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_DATA_RD_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_DATA_RD_P__FIFO2_DATA_OUT_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_DATA_RD_P__FIFO2_DATA_OUT_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_DATA_RD_P__FIFO2_DATA_OUT_WIDTH 32U
+
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_FIFO1_FLUSH_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_FIFO1_FLUSH_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_FIFO1_FLUSH_P__FIFO1_FLUSH_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_FIFO1_FLUSH_P__FIFO1_FLUSH_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_FIFO1_FLUSH_P__FIFO1_FLUSH_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_FIFO1_FLUSH_P__FIFO1_FLUSH_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_FIFO1_FLUSH_P__FIFO1_FLUSH_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_FIFO1_FLUSH_P__RESERVED_0_MASK 0xFFFFFFFEU
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_FIFO1_FLUSH_P__RESERVED_0_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_FIFO1_FLUSH_P__RESERVED_0_WIDTH 31U
+
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_FIFO2_FLUSH_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_FIFO2_FLUSH_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_FIFO2_FLUSH_P__FIFO2_FLUSH_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_FIFO2_FLUSH_P__FIFO2_FLUSH_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_FIFO2_FLUSH_P__FIFO2_FLUSH_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_FIFO2_FLUSH_P__FIFO2_FLUSH_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_FIFO2_FLUSH_P__FIFO2_FLUSH_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_FIFO2_FLUSH_P__RESERVED_0_MASK 0xFFFFFFFEU
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_FIFO2_FLUSH_P__RESERVED_0_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_FIFO2_FLUSH_P__RESERVED_0_WIDTH 31U
+
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_STATUS_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_STATUS_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_STATUS_P__SOURCE_PKT_MEM_CTRL_FSM_STATE_MASK 0x00000007U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_STATUS_P__SOURCE_PKT_MEM_CTRL_FSM_STATE_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_STATUS_P__SOURCE_PKT_MEM_CTRL_FSM_STATE_WIDTH 3U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_STATUS_P__FIFO1_FULL_MASK 0x00000008U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_STATUS_P__FIFO1_FULL_SHIFT 3U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_STATUS_P__FIFO1_FULL_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_STATUS_P__FIFO1_FULL_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_STATUS_P__FIFO1_FULL_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_STATUS_P__FIFO2_EMPTY_MASK 0x00000010U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_STATUS_P__FIFO2_EMPTY_SHIFT 4U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_STATUS_P__FIFO2_EMPTY_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_STATUS_P__FIFO2_EMPTY_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_STATUS_P__FIFO2_EMPTY_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_STATUS_P__RESERVED_0_MASK 0xFFFFFFE0U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_STATUS_P__RESERVED_0_SHIFT 5U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_STATUS_P__RESERVED_0_WIDTH 27U
+
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_SOURCE_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_SOURCE_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_SOURCE_P__HOST_WR_DONE_INT_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_SOURCE_P__HOST_WR_DONE_INT_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_SOURCE_P__HOST_WR_DONE_INT_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_SOURCE_P__HOST_WR_DONE_INT_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_SOURCE_P__HOST_WR_DONE_INT_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_SOURCE_P__HOST_RD_DONE_INT_MASK 0x00000002U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_SOURCE_P__HOST_RD_DONE_INT_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_SOURCE_P__HOST_RD_DONE_INT_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_SOURCE_P__HOST_RD_DONE_INT_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_SOURCE_P__HOST_RD_DONE_INT_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_SOURCE_P__NONVALID_TYPE_REQUESTED_INT_MASK 0x00000004U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_SOURCE_P__NONVALID_TYPE_REQUESTED_INT_SHIFT 2U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_SOURCE_P__NONVALID_TYPE_REQUESTED_INT_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_SOURCE_P__NONVALID_TYPE_REQUESTED_INT_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_SOURCE_P__NONVALID_TYPE_REQUESTED_INT_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_SOURCE_P__RESERVED_0_MASK 0x00000008U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_SOURCE_P__RESERVED_0_SHIFT 3U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_SOURCE_P__RESERVED_0_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_SOURCE_P__RESERVED_0_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_SOURCE_P__RESERVED_0_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_SOURCE_P__ALLOC_WR_DONE_MASK 0x00000010U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_SOURCE_P__ALLOC_WR_DONE_SHIFT 4U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_SOURCE_P__ALLOC_WR_DONE_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_SOURCE_P__ALLOC_WR_DONE_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_SOURCE_P__ALLOC_WR_DONE_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_SOURCE_P__ALLOC_WR_ERROR_MASK 0x00000020U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_SOURCE_P__ALLOC_WR_ERROR_SHIFT 5U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_SOURCE_P__ALLOC_WR_ERROR_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_SOURCE_P__ALLOC_WR_ERROR_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_SOURCE_P__ALLOC_WR_ERROR_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_SOURCE_P__FIFO1_OVERFLOW_MASK 0x00000040U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_SOURCE_P__FIFO1_OVERFLOW_SHIFT 6U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_SOURCE_P__FIFO1_OVERFLOW_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_SOURCE_P__FIFO1_OVERFLOW_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_SOURCE_P__FIFO1_OVERFLOW_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_SOURCE_P__FIFO1_UNDERFLOW_MASK 0x00000080U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_SOURCE_P__FIFO1_UNDERFLOW_SHIFT 7U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_SOURCE_P__FIFO1_UNDERFLOW_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_SOURCE_P__FIFO1_UNDERFLOW_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_SOURCE_P__FIFO1_UNDERFLOW_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_SOURCE_P__FIFO2_OVERFLOW_MASK 0x00000100U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_SOURCE_P__FIFO2_OVERFLOW_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_SOURCE_P__FIFO2_OVERFLOW_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_SOURCE_P__FIFO2_OVERFLOW_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_SOURCE_P__FIFO2_OVERFLOW_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_SOURCE_P__FIFO2_UNDERFLOW_MASK 0x00000200U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_SOURCE_P__FIFO2_UNDERFLOW_SHIFT 9U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_SOURCE_P__FIFO2_UNDERFLOW_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_SOURCE_P__FIFO2_UNDERFLOW_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_SOURCE_P__FIFO2_UNDERFLOW_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_SOURCE_P__PPS_SENT_MASK 0x00000400U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_SOURCE_P__PPS_SENT_SHIFT 10U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_SOURCE_P__PPS_SENT_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_SOURCE_P__PPS_SENT_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_SOURCE_P__PPS_SENT_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_SOURCE_P__RESERVED_1_MASK 0xFFFFF800U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_SOURCE_P__RESERVED_1_SHIFT 11U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_SOURCE_P__RESERVED_1_WIDTH 21U
+
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_MASK_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_MASK_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_MASK_P__HOST_WR_DONE_INT_MASK_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_MASK_P__HOST_WR_DONE_INT_MASK_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_MASK_P__HOST_WR_DONE_INT_MASK_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_MASK_P__HOST_WR_DONE_INT_MASK_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_MASK_P__HOST_WR_DONE_INT_MASK_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_MASK_P__HOST_RD_DONE_INT_MASK_MASK 0x00000002U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_MASK_P__HOST_RD_DONE_INT_MASK_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_MASK_P__HOST_RD_DONE_INT_MASK_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_MASK_P__HOST_RD_DONE_INT_MASK_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_MASK_P__HOST_RD_DONE_INT_MASK_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_MASK_P__NONVALID_TYPE_REQUESTED_INT_MASK_MASK 0x00000004U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_MASK_P__NONVALID_TYPE_REQUESTED_INT_MASK_SHIFT 2U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_MASK_P__NONVALID_TYPE_REQUESTED_INT_MASK_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_MASK_P__NONVALID_TYPE_REQUESTED_INT_MASK_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_MASK_P__NONVALID_TYPE_REQUESTED_INT_MASK_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_MASK_P__RESERVED_0_MASK 0x00000008U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_MASK_P__RESERVED_0_SHIFT 3U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_MASK_P__RESERVED_0_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_MASK_P__RESERVED_0_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_MASK_P__RESERVED_0_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_MASK_P__ALLOC_WR_DONE_MASK_MASK 0x00000010U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_MASK_P__ALLOC_WR_DONE_MASK_SHIFT 4U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_MASK_P__ALLOC_WR_DONE_MASK_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_MASK_P__ALLOC_WR_DONE_MASK_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_MASK_P__ALLOC_WR_DONE_MASK_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_MASK_P__ALLOC_WR_ERROR_MASK_MASK 0x00000020U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_MASK_P__ALLOC_WR_ERROR_MASK_SHIFT 5U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_MASK_P__ALLOC_WR_ERROR_MASK_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_MASK_P__ALLOC_WR_ERROR_MASK_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_MASK_P__ALLOC_WR_ERROR_MASK_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_MASK_P__FIFO1_OVERFLOW_MASK_MASK 0x00000040U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_MASK_P__FIFO1_OVERFLOW_MASK_SHIFT 6U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_MASK_P__FIFO1_OVERFLOW_MASK_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_MASK_P__FIFO1_OVERFLOW_MASK_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_MASK_P__FIFO1_OVERFLOW_MASK_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_MASK_P__FIFO1_UNDERFLOW_MASK_MASK 0x00000080U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_MASK_P__FIFO1_UNDERFLOW_MASK_SHIFT 7U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_MASK_P__FIFO1_UNDERFLOW_MASK_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_MASK_P__FIFO1_UNDERFLOW_MASK_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_MASK_P__FIFO1_UNDERFLOW_MASK_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_MASK_P__FIFO2_OVERFLOW_MASK_MASK 0x00000100U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_MASK_P__FIFO2_OVERFLOW_MASK_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_MASK_P__FIFO2_OVERFLOW_MASK_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_MASK_P__FIFO2_OVERFLOW_MASK_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_MASK_P__FIFO2_OVERFLOW_MASK_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_MASK_P__FIFO2_UNDERFLOW_MASK_MASK 0x00000200U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_MASK_P__FIFO2_UNDERFLOW_MASK_SHIFT 9U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_MASK_P__FIFO2_UNDERFLOW_MASK_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_MASK_P__FIFO2_UNDERFLOW_MASK_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_MASK_P__FIFO2_UNDERFLOW_MASK_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_MASK_P__PPS_SENT_MASK_MASK 0x00000400U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_MASK_P__PPS_SENT_MASK_SHIFT 10U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_MASK_P__PPS_SENT_MASK_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_MASK_P__PPS_SENT_MASK_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_MASK_P__PPS_SENT_MASK_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_MASK_P__RESERVED_1_MASK 0xFFFFF800U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_MASK_P__RESERVED_1_SHIFT 11U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_INTERRUPT_MASK_P__RESERVED_1_WIDTH 21U
+
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_PKT_ALLOC_REG_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_PKT_ALLOC_REG_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_PKT_ALLOC_REG_P__PKT_ALLOC_ADDRESS_MASK 0x0000000FU
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_PKT_ALLOC_REG_P__PKT_ALLOC_ADDRESS_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_PKT_ALLOC_REG_P__PKT_ALLOC_ADDRESS_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_PKT_ALLOC_REG_P__RESERVED_0_MASK 0x000000F0U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_PKT_ALLOC_REG_P__RESERVED_0_SHIFT 4U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_PKT_ALLOC_REG_P__RESERVED_0_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_PKT_ALLOC_REG_P__PACKET_TYPE_MASK 0x0000FF00U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_PKT_ALLOC_REG_P__PACKET_TYPE_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_PKT_ALLOC_REG_P__PACKET_TYPE_WIDTH 8U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_PKT_ALLOC_REG_P__TYPE_VALID_MASK 0x00010000U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_PKT_ALLOC_REG_P__TYPE_VALID_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_PKT_ALLOC_REG_P__TYPE_VALID_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_PKT_ALLOC_REG_P__TYPE_VALID_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_PKT_ALLOC_REG_P__TYPE_VALID_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_PKT_ALLOC_REG_P__ACTIVE_IDLE_TYPE_MASK 0x00020000U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_PKT_ALLOC_REG_P__ACTIVE_IDLE_TYPE_SHIFT 17U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_PKT_ALLOC_REG_P__ACTIVE_IDLE_TYPE_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_PKT_ALLOC_REG_P__ACTIVE_IDLE_TYPE_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_PKT_ALLOC_REG_P__ACTIVE_IDLE_TYPE_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_PKT_ALLOC_REG_P__RESERVED_1_MASK 0xFFFC0000U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_PKT_ALLOC_REG_P__RESERVED_1_SHIFT 18U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_PKT_ALLOC_REG_P__RESERVED_1_WIDTH 14U
+
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_PKT_ALLOC_WR_EN_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_PKT_ALLOC_WR_EN_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_PKT_ALLOC_WR_EN_P__PKT_ALLOC_WR_EN_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_PKT_ALLOC_WR_EN_P__PKT_ALLOC_WR_EN_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_PKT_ALLOC_WR_EN_P__PKT_ALLOC_WR_EN_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_PKT_ALLOC_WR_EN_P__PKT_ALLOC_WR_EN_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_PKT_ALLOC_WR_EN_P__PKT_ALLOC_WR_EN_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_PKT_ALLOC_WR_EN_P__RESERVED_0_MASK 0xFFFFFFFEU
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_PKT_ALLOC_WR_EN_P__RESERVED_0_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_PKT_ALLOC_WR_EN_P__RESERVED_0_WIDTH 31U
+
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_SW_RESET_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_SW_RESET_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_SW_RESET_P__SW_RST_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_SW_RESET_P__SW_RST_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_SW_RESET_P__SW_RST_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_SW_RESET_P__SW_RST_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_SW_RESET_P__SW_RST_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_SW_RESET_P__RESERVED_0_MASK 0xFFFFFFFEU
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_SW_RESET_P__RESERVED_0_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_SW_RESET_P__RESERVED_0_WIDTH 31U
+
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_PPS_HEADER_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_PPS_HEADER_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_PPS_HEADER_P__PPS_HEADER_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_PPS_HEADER_P__PPS_HEADER_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_PPS_HEADER_P__PPS_HEADER_WIDTH 32U
+
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_PPS_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_PPS_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_PPS_P__PPS_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_PPS_P__PPS_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_PPS_P__PPS_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_PPS_P__PPS_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_PPS_P__PPS_WOSET 0U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_PPS_P__RESERVED_0_MASK 0xFFFFFFFEU
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_PPS_P__RESERVED_0_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__MHDP_SDP_CONTROL__SOURCE_PIF_PPS_P__RESERVED_0_WIDTH 31U
+
+#define MHDP__MHDP_APB_REGS__AUX_CONFIG_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__AUX_CONFIG_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__AUX_CONFIG_P__BANDGAP_ADJUST_MASK 0x00000003U
+#define MHDP__MHDP_APB_REGS__AUX_CONFIG_P__BANDGAP_ADJUST_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__AUX_CONFIG_P__BANDGAP_ADJUST_WIDTH 2U
+#define MHDP__MHDP_APB_REGS__AUX_CONFIG_P__RX_OFFSET_DIS_MASK 0x00000004U
+#define MHDP__MHDP_APB_REGS__AUX_CONFIG_P__RX_OFFSET_DIS_SHIFT 2U
+#define MHDP__MHDP_APB_REGS__AUX_CONFIG_P__RX_OFFSET_DIS_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__AUX_CONFIG_P__RX_OFFSET_DIS_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__AUX_CONFIG_P__RX_OFFSET_DIS_WOSET 0U
+#define MHDP__MHDP_APB_REGS__AUX_CONFIG_P__RESERVED_0_MASK 0x00000008U
+#define MHDP__MHDP_APB_REGS__AUX_CONFIG_P__RESERVED_0_SHIFT 3U
+#define MHDP__MHDP_APB_REGS__AUX_CONFIG_P__RESERVED_0_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__AUX_CONFIG_P__RESERVED_0_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__AUX_CONFIG_P__RESERVED_0_WOSET 0U
+#define MHDP__MHDP_APB_REGS__AUX_CONFIG_P__RX_DEGLITCH_FILTER_MASK 0x00000030U
+#define MHDP__MHDP_APB_REGS__AUX_CONFIG_P__RX_DEGLITCH_FILTER_SHIFT 4U
+#define MHDP__MHDP_APB_REGS__AUX_CONFIG_P__RX_DEGLITCH_FILTER_WIDTH 2U
+#define MHDP__MHDP_APB_REGS__AUX_CONFIG_P__RESERVED_1_MASK 0x000000C0U
+#define MHDP__MHDP_APB_REGS__AUX_CONFIG_P__RESERVED_1_SHIFT 6U
+#define MHDP__MHDP_APB_REGS__AUX_CONFIG_P__RESERVED_1_WIDTH 2U
+#define MHDP__MHDP_APB_REGS__AUX_CONFIG_P__RX_HYST_LVL_MASK 0x00000700U
+#define MHDP__MHDP_APB_REGS__AUX_CONFIG_P__RX_HYST_LVL_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__AUX_CONFIG_P__RX_HYST_LVL_WIDTH 3U
+#define MHDP__MHDP_APB_REGS__AUX_CONFIG_P__RESERVED_2_MASK 0x00000800U
+#define MHDP__MHDP_APB_REGS__AUX_CONFIG_P__RESERVED_2_SHIFT 11U
+#define MHDP__MHDP_APB_REGS__AUX_CONFIG_P__RESERVED_2_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__AUX_CONFIG_P__RESERVED_2_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__AUX_CONFIG_P__RESERVED_2_WOSET 0U
+#define MHDP__MHDP_APB_REGS__AUX_CONFIG_P__TX_REDUCED_SWING_MASK 0x00001000U
+#define MHDP__MHDP_APB_REGS__AUX_CONFIG_P__TX_REDUCED_SWING_SHIFT 12U
+#define MHDP__MHDP_APB_REGS__AUX_CONFIG_P__TX_REDUCED_SWING_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__AUX_CONFIG_P__TX_REDUCED_SWING_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__AUX_CONFIG_P__TX_REDUCED_SWING_WOSET 0U
+#define MHDP__MHDP_APB_REGS__AUX_CONFIG_P__TX_SLEW_RATE_MASK 0x00006000U
+#define MHDP__MHDP_APB_REGS__AUX_CONFIG_P__TX_SLEW_RATE_SHIFT 13U
+#define MHDP__MHDP_APB_REGS__AUX_CONFIG_P__TX_SLEW_RATE_WIDTH 2U
+#define MHDP__MHDP_APB_REGS__AUX_CONFIG_P__RESERVED_3_MASK 0x00008000U
+#define MHDP__MHDP_APB_REGS__AUX_CONFIG_P__RESERVED_3_SHIFT 15U
+#define MHDP__MHDP_APB_REGS__AUX_CONFIG_P__RESERVED_3_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__AUX_CONFIG_P__RESERVED_3_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__AUX_CONFIG_P__RESERVED_3_WOSET 0U
+#define MHDP__MHDP_APB_REGS__AUX_CONFIG_P__TX_CURR_CTRL_MASK 0x001F0000U
+#define MHDP__MHDP_APB_REGS__AUX_CONFIG_P__TX_CURR_CTRL_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__AUX_CONFIG_P__TX_CURR_CTRL_WIDTH 5U
+#define MHDP__MHDP_APB_REGS__AUX_CONFIG_P__RESERVED_4_MASK 0x00E00000U
+#define MHDP__MHDP_APB_REGS__AUX_CONFIG_P__RESERVED_4_SHIFT 21U
+#define MHDP__MHDP_APB_REGS__AUX_CONFIG_P__RESERVED_4_WIDTH 3U
+#define MHDP__MHDP_APB_REGS__AUX_CONFIG_P__TERM_SEG_EN_MASK 0x1F000000U
+#define MHDP__MHDP_APB_REGS__AUX_CONFIG_P__TERM_SEG_EN_SHIFT 24U
+#define MHDP__MHDP_APB_REGS__AUX_CONFIG_P__TERM_SEG_EN_WIDTH 5U
+#define MHDP__MHDP_APB_REGS__AUX_CONFIG_P__RESERVED_5_MASK 0xE0000000U
+#define MHDP__MHDP_APB_REGS__AUX_CONFIG_P__RESERVED_5_SHIFT 29U
+#define MHDP__MHDP_APB_REGS__AUX_CONFIG_P__RESERVED_5_WIDTH 3U
+
+#define MHDP__MHDP_APB_REGS__AUX_CTRL_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__AUX_CTRL_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__AUX_CTRL_P__BANDGAP_EN_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__AUX_CTRL_P__BANDGAP_EN_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__AUX_CTRL_P__BANDGAP_EN_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__AUX_CTRL_P__BANDGAP_EN_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__AUX_CTRL_P__BANDGAP_EN_WOSET 0U
+#define MHDP__MHDP_APB_REGS__AUX_CTRL_P__DECAP_EN_MASK 0x00000002U
+#define MHDP__MHDP_APB_REGS__AUX_CTRL_P__DECAP_EN_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__AUX_CTRL_P__DECAP_EN_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__AUX_CTRL_P__DECAP_EN_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__AUX_CTRL_P__DECAP_EN_WOSET 0U
+#define MHDP__MHDP_APB_REGS__AUX_CTRL_P__RESERVED_0_MASK 0xFFFFFFFCU
+#define MHDP__MHDP_APB_REGS__AUX_CTRL_P__RESERVED_0_SHIFT 2U
+#define MHDP__MHDP_APB_REGS__AUX_CTRL_P__RESERVED_0_WIDTH 30U
+
+#define MHDP__MHDP_APB_REGS__AUX_ATBSEL_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__AUX_ATBSEL_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__AUX_ATBSEL_P__AUXIP_ATBSEL_ONEHOT_MASK 0x000000FFU
+#define MHDP__MHDP_APB_REGS__AUX_ATBSEL_P__AUXIP_ATBSEL_ONEHOT_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__AUX_ATBSEL_P__AUXIP_ATBSEL_ONEHOT_WIDTH 8U
+#define MHDP__MHDP_APB_REGS__AUX_ATBSEL_P__RESERVED_0_MASK 0xFFFFFF00U
+#define MHDP__MHDP_APB_REGS__AUX_ATBSEL_P__RESERVED_0_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__AUX_ATBSEL_P__RESERVED_0_WIDTH 24U
+
+#define MHDP__MHDP_APB_REGS__AUX_TESTMODE_CTL_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__AUX_TESTMODE_CTL_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__AUX_TESTMODE_CTL_P__AUX_TESTMODE_EN_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__AUX_TESTMODE_CTL_P__AUX_TESTMODE_EN_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__AUX_TESTMODE_CTL_P__AUX_TESTMODE_EN_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__AUX_TESTMODE_CTL_P__AUX_TESTMODE_EN_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__AUX_TESTMODE_CTL_P__AUX_TESTMODE_EN_WOSET 0U
+#define MHDP__MHDP_APB_REGS__AUX_TESTMODE_CTL_P__RX_EN_CTRL_MASK 0x00000002U
+#define MHDP__MHDP_APB_REGS__AUX_TESTMODE_CTL_P__RX_EN_CTRL_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__AUX_TESTMODE_CTL_P__RX_EN_CTRL_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__AUX_TESTMODE_CTL_P__RX_EN_CTRL_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__AUX_TESTMODE_CTL_P__RX_EN_CTRL_WOSET 0U
+#define MHDP__MHDP_APB_REGS__AUX_TESTMODE_CTL_P__TX_EN_CTRL_MASK 0x00000004U
+#define MHDP__MHDP_APB_REGS__AUX_TESTMODE_CTL_P__TX_EN_CTRL_SHIFT 2U
+#define MHDP__MHDP_APB_REGS__AUX_TESTMODE_CTL_P__TX_EN_CTRL_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__AUX_TESTMODE_CTL_P__TX_EN_CTRL_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__AUX_TESTMODE_CTL_P__TX_EN_CTRL_WOSET 0U
+#define MHDP__MHDP_APB_REGS__AUX_TESTMODE_CTL_P__AUX_DATA_IN_MASK 0x00000008U
+#define MHDP__MHDP_APB_REGS__AUX_TESTMODE_CTL_P__AUX_DATA_IN_SHIFT 3U
+#define MHDP__MHDP_APB_REGS__AUX_TESTMODE_CTL_P__AUX_DATA_IN_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__AUX_TESTMODE_CTL_P__AUX_DATA_IN_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__AUX_TESTMODE_CTL_P__AUX_DATA_IN_WOSET 0U
+#define MHDP__MHDP_APB_REGS__AUX_TESTMODE_CTL_P__DECAP_EN_DEL_MASK 0x00000010U
+#define MHDP__MHDP_APB_REGS__AUX_TESTMODE_CTL_P__DECAP_EN_DEL_SHIFT 4U
+#define MHDP__MHDP_APB_REGS__AUX_TESTMODE_CTL_P__DECAP_EN_DEL_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__AUX_TESTMODE_CTL_P__DECAP_EN_DEL_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__AUX_TESTMODE_CTL_P__DECAP_EN_DEL_WOSET 0U
+#define MHDP__MHDP_APB_REGS__AUX_TESTMODE_CTL_P__RESERVED_MASK 0xFFFFFFE0U
+#define MHDP__MHDP_APB_REGS__AUX_TESTMODE_CTL_P__RESERVED_SHIFT 5U
+#define MHDP__MHDP_APB_REGS__AUX_TESTMODE_CTL_P__RESERVED_WIDTH 27U
+
+#define MHDP__MHDP_APB_REGS__AUX_TESTMODE_ST_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__AUX_TESTMODE_ST_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__AUX_TESTMODE_ST_P__HPD_DATA_OUT_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__AUX_TESTMODE_ST_P__HPD_DATA_OUT_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__AUX_TESTMODE_ST_P__HPD_DATA_OUT_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__AUX_TESTMODE_ST_P__HPD_DATA_OUT_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__AUX_TESTMODE_ST_P__HPD_DATA_OUT_WOSET 0U
+#define MHDP__MHDP_APB_REGS__AUX_TESTMODE_ST_P__AUX_DATA_OUT_MASK 0x00000002U
+#define MHDP__MHDP_APB_REGS__AUX_TESTMODE_ST_P__AUX_DATA_OUT_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__AUX_TESTMODE_ST_P__AUX_DATA_OUT_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__AUX_TESTMODE_ST_P__AUX_DATA_OUT_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__AUX_TESTMODE_ST_P__AUX_DATA_OUT_WOSET 0U
+#define MHDP__MHDP_APB_REGS__AUX_TESTMODE_ST_P__RESERVED_MASK 0xFFFFFFFCU
+#define MHDP__MHDP_APB_REGS__AUX_TESTMODE_ST_P__RESERVED_SHIFT 2U
+#define MHDP__MHDP_APB_REGS__AUX_TESTMODE_ST_P__RESERVED_WIDTH 30U
+
+#define MHDP__MHDP_APB_REGS__PHY_RESET_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__PHY_RESET_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__PHY_RESET_P__PHY_L00_RESET_N_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__PHY_RESET_P__PHY_L00_RESET_N_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__PHY_RESET_P__PHY_L00_RESET_N_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__PHY_RESET_P__PHY_L00_RESET_N_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__PHY_RESET_P__PHY_L00_RESET_N_WOSET 0U
+#define MHDP__MHDP_APB_REGS__PHY_RESET_P__PHY_L01_RESET_N_MASK 0x00000002U
+#define MHDP__MHDP_APB_REGS__PHY_RESET_P__PHY_L01_RESET_N_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__PHY_RESET_P__PHY_L01_RESET_N_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__PHY_RESET_P__PHY_L01_RESET_N_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__PHY_RESET_P__PHY_L01_RESET_N_WOSET 0U
+#define MHDP__MHDP_APB_REGS__PHY_RESET_P__PHY_L02_RESET_N_MASK 0x00000004U
+#define MHDP__MHDP_APB_REGS__PHY_RESET_P__PHY_L02_RESET_N_SHIFT 2U
+#define MHDP__MHDP_APB_REGS__PHY_RESET_P__PHY_L02_RESET_N_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__PHY_RESET_P__PHY_L02_RESET_N_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__PHY_RESET_P__PHY_L02_RESET_N_WOSET 0U
+#define MHDP__MHDP_APB_REGS__PHY_RESET_P__PHY_L03_RESET_N_MASK 0x00000008U
+#define MHDP__MHDP_APB_REGS__PHY_RESET_P__PHY_L03_RESET_N_SHIFT 3U
+#define MHDP__MHDP_APB_REGS__PHY_RESET_P__PHY_L03_RESET_N_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__PHY_RESET_P__PHY_L03_RESET_N_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__PHY_RESET_P__PHY_L03_RESET_N_WOSET 0U
+#define MHDP__MHDP_APB_REGS__PHY_RESET_P__PMA_TX_ELEC_IDLE_LN_0_MASK 0x00000010U
+#define MHDP__MHDP_APB_REGS__PHY_RESET_P__PMA_TX_ELEC_IDLE_LN_0_SHIFT 4U
+#define MHDP__MHDP_APB_REGS__PHY_RESET_P__PMA_TX_ELEC_IDLE_LN_0_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__PHY_RESET_P__PMA_TX_ELEC_IDLE_LN_0_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__PHY_RESET_P__PMA_TX_ELEC_IDLE_LN_0_WOSET 0U
+#define MHDP__MHDP_APB_REGS__PHY_RESET_P__PMA_TX_ELEC_IDLE_LN_1_MASK 0x00000020U
+#define MHDP__MHDP_APB_REGS__PHY_RESET_P__PMA_TX_ELEC_IDLE_LN_1_SHIFT 5U
+#define MHDP__MHDP_APB_REGS__PHY_RESET_P__PMA_TX_ELEC_IDLE_LN_1_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__PHY_RESET_P__PMA_TX_ELEC_IDLE_LN_1_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__PHY_RESET_P__PMA_TX_ELEC_IDLE_LN_1_WOSET 0U
+#define MHDP__MHDP_APB_REGS__PHY_RESET_P__PMA_TX_ELEC_IDLE_LN_2_MASK 0x00000040U
+#define MHDP__MHDP_APB_REGS__PHY_RESET_P__PMA_TX_ELEC_IDLE_LN_2_SHIFT 6U
+#define MHDP__MHDP_APB_REGS__PHY_RESET_P__PMA_TX_ELEC_IDLE_LN_2_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__PHY_RESET_P__PMA_TX_ELEC_IDLE_LN_2_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__PHY_RESET_P__PMA_TX_ELEC_IDLE_LN_2_WOSET 0U
+#define MHDP__MHDP_APB_REGS__PHY_RESET_P__PMA_TX_ELEC_IDLE_LN_3_MASK 0x00000080U
+#define MHDP__MHDP_APB_REGS__PHY_RESET_P__PMA_TX_ELEC_IDLE_LN_3_SHIFT 7U
+#define MHDP__MHDP_APB_REGS__PHY_RESET_P__PMA_TX_ELEC_IDLE_LN_3_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__PHY_RESET_P__PMA_TX_ELEC_IDLE_LN_3_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__PHY_RESET_P__PMA_TX_ELEC_IDLE_LN_3_WOSET 0U
+#define MHDP__MHDP_APB_REGS__PHY_RESET_P__PHY_RESET_MASK 0x00000100U
+#define MHDP__MHDP_APB_REGS__PHY_RESET_P__PHY_RESET_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__PHY_RESET_P__PHY_RESET_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__PHY_RESET_P__PHY_RESET_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__PHY_RESET_P__PHY_RESET_WOSET 0U
+#define MHDP__MHDP_APB_REGS__PHY_RESET_P__RESERVED_1_MASK 0xFFFFFE00U
+#define MHDP__MHDP_APB_REGS__PHY_RESET_P__RESERVED_1_SHIFT 9U
+#define MHDP__MHDP_APB_REGS__PHY_RESET_P__RESERVED_1_WIDTH 23U
+
+#define MHDP__MHDP_APB_REGS__PMA_PLLCLK_EN_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__PMA_PLLCLK_EN_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__PMA_PLLCLK_EN_P__PMA_XCVR_PLLCLK_EN_LN_0_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__PMA_PLLCLK_EN_P__PMA_XCVR_PLLCLK_EN_LN_0_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__PMA_PLLCLK_EN_P__PMA_XCVR_PLLCLK_EN_LN_0_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__PMA_PLLCLK_EN_P__PMA_XCVR_PLLCLK_EN_LN_0_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__PMA_PLLCLK_EN_P__PMA_XCVR_PLLCLK_EN_LN_0_WOSET 0U
+#define MHDP__MHDP_APB_REGS__PMA_PLLCLK_EN_P__PMA_XCVR_PLLCLK_EN_LN_1_MASK 0x00000002U
+#define MHDP__MHDP_APB_REGS__PMA_PLLCLK_EN_P__PMA_XCVR_PLLCLK_EN_LN_1_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__PMA_PLLCLK_EN_P__PMA_XCVR_PLLCLK_EN_LN_1_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__PMA_PLLCLK_EN_P__PMA_XCVR_PLLCLK_EN_LN_1_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__PMA_PLLCLK_EN_P__PMA_XCVR_PLLCLK_EN_LN_1_WOSET 0U
+#define MHDP__MHDP_APB_REGS__PMA_PLLCLK_EN_P__PMA_XCVR_PLLCLK_EN_LN_2_MASK 0x00000004U
+#define MHDP__MHDP_APB_REGS__PMA_PLLCLK_EN_P__PMA_XCVR_PLLCLK_EN_LN_2_SHIFT 2U
+#define MHDP__MHDP_APB_REGS__PMA_PLLCLK_EN_P__PMA_XCVR_PLLCLK_EN_LN_2_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__PMA_PLLCLK_EN_P__PMA_XCVR_PLLCLK_EN_LN_2_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__PMA_PLLCLK_EN_P__PMA_XCVR_PLLCLK_EN_LN_2_WOSET 0U
+#define MHDP__MHDP_APB_REGS__PMA_PLLCLK_EN_P__PMA_XCVR_PLLCLK_EN_LN_3_MASK 0x00000008U
+#define MHDP__MHDP_APB_REGS__PMA_PLLCLK_EN_P__PMA_XCVR_PLLCLK_EN_LN_3_SHIFT 3U
+#define MHDP__MHDP_APB_REGS__PMA_PLLCLK_EN_P__PMA_XCVR_PLLCLK_EN_LN_3_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__PMA_PLLCLK_EN_P__PMA_XCVR_PLLCLK_EN_LN_3_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__PMA_PLLCLK_EN_P__PMA_XCVR_PLLCLK_EN_LN_3_WOSET 0U
+#define MHDP__MHDP_APB_REGS__PMA_PLLCLK_EN_P__RESERVED_0_MASK 0xFFFFFFF0U
+#define MHDP__MHDP_APB_REGS__PMA_PLLCLK_EN_P__RESERVED_0_SHIFT 4U
+#define MHDP__MHDP_APB_REGS__PMA_PLLCLK_EN_P__RESERVED_0_WIDTH 28U
+
+#define MHDP__MHDP_APB_REGS__PMA_PLLCLK_EN_ACK_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__PMA_PLLCLK_EN_ACK_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__PMA_PLLCLK_EN_ACK_P__PMA_XCVR_PLLCLK_EN_ACK_LN_0_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__PMA_PLLCLK_EN_ACK_P__PMA_XCVR_PLLCLK_EN_ACK_LN_0_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__PMA_PLLCLK_EN_ACK_P__PMA_XCVR_PLLCLK_EN_ACK_LN_0_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__PMA_PLLCLK_EN_ACK_P__PMA_XCVR_PLLCLK_EN_ACK_LN_0_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__PMA_PLLCLK_EN_ACK_P__PMA_XCVR_PLLCLK_EN_ACK_LN_0_WOSET 0U
+#define MHDP__MHDP_APB_REGS__PMA_PLLCLK_EN_ACK_P__PMA_XCVR_PLLCLK_EN_ACK_LN_1_MASK 0x00000002U
+#define MHDP__MHDP_APB_REGS__PMA_PLLCLK_EN_ACK_P__PMA_XCVR_PLLCLK_EN_ACK_LN_1_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__PMA_PLLCLK_EN_ACK_P__PMA_XCVR_PLLCLK_EN_ACK_LN_1_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__PMA_PLLCLK_EN_ACK_P__PMA_XCVR_PLLCLK_EN_ACK_LN_1_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__PMA_PLLCLK_EN_ACK_P__PMA_XCVR_PLLCLK_EN_ACK_LN_1_WOSET 0U
+#define MHDP__MHDP_APB_REGS__PMA_PLLCLK_EN_ACK_P__PMA_XCVR_PLLCLK_EN_ACK_LN_2_MASK 0x00000004U
+#define MHDP__MHDP_APB_REGS__PMA_PLLCLK_EN_ACK_P__PMA_XCVR_PLLCLK_EN_ACK_LN_2_SHIFT 2U
+#define MHDP__MHDP_APB_REGS__PMA_PLLCLK_EN_ACK_P__PMA_XCVR_PLLCLK_EN_ACK_LN_2_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__PMA_PLLCLK_EN_ACK_P__PMA_XCVR_PLLCLK_EN_ACK_LN_2_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__PMA_PLLCLK_EN_ACK_P__PMA_XCVR_PLLCLK_EN_ACK_LN_2_WOSET 0U
+#define MHDP__MHDP_APB_REGS__PMA_PLLCLK_EN_ACK_P__PMA_XCVR_PLLCLK_EN_ACK_LN_3_MASK 0x00000008U
+#define MHDP__MHDP_APB_REGS__PMA_PLLCLK_EN_ACK_P__PMA_XCVR_PLLCLK_EN_ACK_LN_3_SHIFT 3U
+#define MHDP__MHDP_APB_REGS__PMA_PLLCLK_EN_ACK_P__PMA_XCVR_PLLCLK_EN_ACK_LN_3_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__PMA_PLLCLK_EN_ACK_P__PMA_XCVR_PLLCLK_EN_ACK_LN_3_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__PMA_PLLCLK_EN_ACK_P__PMA_XCVR_PLLCLK_EN_ACK_LN_3_WOSET 0U
+#define MHDP__MHDP_APB_REGS__PMA_PLLCLK_EN_ACK_P__RESERVED_0_MASK 0xFFFFFFF0U
+#define MHDP__MHDP_APB_REGS__PMA_PLLCLK_EN_ACK_P__RESERVED_0_SHIFT 4U
+#define MHDP__MHDP_APB_REGS__PMA_PLLCLK_EN_ACK_P__RESERVED_0_WIDTH 28U
+
+#define MHDP__MHDP_APB_REGS__PMA_POWER_STATE_REQ_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__PMA_POWER_STATE_REQ_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__PMA_POWER_STATE_REQ_P__PMA_XCVR_POWER_STATE_REQ_LN_0_MASK 0x0000003FU
+#define MHDP__MHDP_APB_REGS__PMA_POWER_STATE_REQ_P__PMA_XCVR_POWER_STATE_REQ_LN_0_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__PMA_POWER_STATE_REQ_P__PMA_XCVR_POWER_STATE_REQ_LN_0_WIDTH 6U
+#define MHDP__MHDP_APB_REGS__PMA_POWER_STATE_REQ_P__RESERVED_0_MASK 0x000000C0U
+#define MHDP__MHDP_APB_REGS__PMA_POWER_STATE_REQ_P__RESERVED_0_SHIFT 6U
+#define MHDP__MHDP_APB_REGS__PMA_POWER_STATE_REQ_P__RESERVED_0_WIDTH 2U
+#define MHDP__MHDP_APB_REGS__PMA_POWER_STATE_REQ_P__PMA_XCVR_POWER_STATE_REQ_LN_1_MASK 0x00003F00U
+#define MHDP__MHDP_APB_REGS__PMA_POWER_STATE_REQ_P__PMA_XCVR_POWER_STATE_REQ_LN_1_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__PMA_POWER_STATE_REQ_P__PMA_XCVR_POWER_STATE_REQ_LN_1_WIDTH 6U
+#define MHDP__MHDP_APB_REGS__PMA_POWER_STATE_REQ_P__RESERVED_1_MASK 0x0000C000U
+#define MHDP__MHDP_APB_REGS__PMA_POWER_STATE_REQ_P__RESERVED_1_SHIFT 14U
+#define MHDP__MHDP_APB_REGS__PMA_POWER_STATE_REQ_P__RESERVED_1_WIDTH 2U
+#define MHDP__MHDP_APB_REGS__PMA_POWER_STATE_REQ_P__PMA_XCVR_POWER_STATE_REQ_LN_2_MASK 0x003F0000U
+#define MHDP__MHDP_APB_REGS__PMA_POWER_STATE_REQ_P__PMA_XCVR_POWER_STATE_REQ_LN_2_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__PMA_POWER_STATE_REQ_P__PMA_XCVR_POWER_STATE_REQ_LN_2_WIDTH 6U
+#define MHDP__MHDP_APB_REGS__PMA_POWER_STATE_REQ_P__RESERVED_2_MASK 0x00C00000U
+#define MHDP__MHDP_APB_REGS__PMA_POWER_STATE_REQ_P__RESERVED_2_SHIFT 22U
+#define MHDP__MHDP_APB_REGS__PMA_POWER_STATE_REQ_P__RESERVED_2_WIDTH 2U
+#define MHDP__MHDP_APB_REGS__PMA_POWER_STATE_REQ_P__PMA_XCVR_POWER_STATE_REQ_LN_3_MASK 0x3F000000U
+#define MHDP__MHDP_APB_REGS__PMA_POWER_STATE_REQ_P__PMA_XCVR_POWER_STATE_REQ_LN_3_SHIFT 24U
+#define MHDP__MHDP_APB_REGS__PMA_POWER_STATE_REQ_P__PMA_XCVR_POWER_STATE_REQ_LN_3_WIDTH 6U
+#define MHDP__MHDP_APB_REGS__PMA_POWER_STATE_REQ_P__RESERVED_3_MASK 0xC0000000U
+#define MHDP__MHDP_APB_REGS__PMA_POWER_STATE_REQ_P__RESERVED_3_SHIFT 30U
+#define MHDP__MHDP_APB_REGS__PMA_POWER_STATE_REQ_P__RESERVED_3_WIDTH 2U
+
+#define MHDP__MHDP_APB_REGS__PMA_POWER_STATE_ACK_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__PMA_POWER_STATE_ACK_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__PMA_POWER_STATE_ACK_P__PMA_XCVR_POWER_STATE_ACK_LN_0_MASK 0x0000003FU
+#define MHDP__MHDP_APB_REGS__PMA_POWER_STATE_ACK_P__PMA_XCVR_POWER_STATE_ACK_LN_0_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__PMA_POWER_STATE_ACK_P__PMA_XCVR_POWER_STATE_ACK_LN_0_WIDTH 6U
+#define MHDP__MHDP_APB_REGS__PMA_POWER_STATE_ACK_P__RESERVED_0_MASK 0x000000C0U
+#define MHDP__MHDP_APB_REGS__PMA_POWER_STATE_ACK_P__RESERVED_0_SHIFT 6U
+#define MHDP__MHDP_APB_REGS__PMA_POWER_STATE_ACK_P__RESERVED_0_WIDTH 2U
+#define MHDP__MHDP_APB_REGS__PMA_POWER_STATE_ACK_P__PMA_XCVR_POWER_STATE_ACK_LN_1_MASK 0x00003F00U
+#define MHDP__MHDP_APB_REGS__PMA_POWER_STATE_ACK_P__PMA_XCVR_POWER_STATE_ACK_LN_1_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__PMA_POWER_STATE_ACK_P__PMA_XCVR_POWER_STATE_ACK_LN_1_WIDTH 6U
+#define MHDP__MHDP_APB_REGS__PMA_POWER_STATE_ACK_P__RESERVED_1_MASK 0x0000C000U
+#define MHDP__MHDP_APB_REGS__PMA_POWER_STATE_ACK_P__RESERVED_1_SHIFT 14U
+#define MHDP__MHDP_APB_REGS__PMA_POWER_STATE_ACK_P__RESERVED_1_WIDTH 2U
+#define MHDP__MHDP_APB_REGS__PMA_POWER_STATE_ACK_P__PMA_XCVR_POWER_STATE_ACK_LN_2_MASK 0x003F0000U
+#define MHDP__MHDP_APB_REGS__PMA_POWER_STATE_ACK_P__PMA_XCVR_POWER_STATE_ACK_LN_2_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__PMA_POWER_STATE_ACK_P__PMA_XCVR_POWER_STATE_ACK_LN_2_WIDTH 6U
+#define MHDP__MHDP_APB_REGS__PMA_POWER_STATE_ACK_P__RESERVED_2_MASK 0x00C00000U
+#define MHDP__MHDP_APB_REGS__PMA_POWER_STATE_ACK_P__RESERVED_2_SHIFT 22U
+#define MHDP__MHDP_APB_REGS__PMA_POWER_STATE_ACK_P__RESERVED_2_WIDTH 2U
+#define MHDP__MHDP_APB_REGS__PMA_POWER_STATE_ACK_P__PMA_XCVR_POWER_STATE_ACK_LN_3_MASK 0x3F000000U
+#define MHDP__MHDP_APB_REGS__PMA_POWER_STATE_ACK_P__PMA_XCVR_POWER_STATE_ACK_LN_3_SHIFT 24U
+#define MHDP__MHDP_APB_REGS__PMA_POWER_STATE_ACK_P__PMA_XCVR_POWER_STATE_ACK_LN_3_WIDTH 6U
+#define MHDP__MHDP_APB_REGS__PMA_POWER_STATE_ACK_P__RESERVED_3_MASK 0xC0000000U
+#define MHDP__MHDP_APB_REGS__PMA_POWER_STATE_ACK_P__RESERVED_3_SHIFT 30U
+#define MHDP__MHDP_APB_REGS__PMA_POWER_STATE_ACK_P__RESERVED_3_WIDTH 2U
+
+#define MHDP__MHDP_APB_REGS__PMA_CMN_READY_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__PMA_CMN_READY_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__PMA_CMN_READY_P__PMA_CMN_READY_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__PMA_CMN_READY_P__PMA_CMN_READY_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__PMA_CMN_READY_P__PMA_CMN_READY_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__PMA_CMN_READY_P__PMA_CMN_READY_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__PMA_CMN_READY_P__PMA_CMN_READY_WOSET 0U
+#define MHDP__MHDP_APB_REGS__PMA_CMN_READY_P__RESERVED_0_MASK 0xFFFFFFFEU
+#define MHDP__MHDP_APB_REGS__PMA_CMN_READY_P__RESERVED_0_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__PMA_CMN_READY_P__RESERVED_0_WIDTH 31U
+
+#define MHDP__MHDP_APB_REGS__PMA_TX_VMARGIN_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__PMA_TX_VMARGIN_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__PMA_TX_VMARGIN_P__PMA_TX_VMARGIN_LN_0_MASK 0x00000003U
+#define MHDP__MHDP_APB_REGS__PMA_TX_VMARGIN_P__PMA_TX_VMARGIN_LN_0_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__PMA_TX_VMARGIN_P__PMA_TX_VMARGIN_LN_0_WIDTH 2U
+#define MHDP__MHDP_APB_REGS__PMA_TX_VMARGIN_P__RESERVED_0_MASK 0x000000FCU
+#define MHDP__MHDP_APB_REGS__PMA_TX_VMARGIN_P__RESERVED_0_SHIFT 2U
+#define MHDP__MHDP_APB_REGS__PMA_TX_VMARGIN_P__RESERVED_0_WIDTH 6U
+#define MHDP__MHDP_APB_REGS__PMA_TX_VMARGIN_P__PMA_TX_VMARGIN_LN_1_MASK 0x00000300U
+#define MHDP__MHDP_APB_REGS__PMA_TX_VMARGIN_P__PMA_TX_VMARGIN_LN_1_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__PMA_TX_VMARGIN_P__PMA_TX_VMARGIN_LN_1_WIDTH 2U
+#define MHDP__MHDP_APB_REGS__PMA_TX_VMARGIN_P__RESERVED_1_MASK 0x0000FC00U
+#define MHDP__MHDP_APB_REGS__PMA_TX_VMARGIN_P__RESERVED_1_SHIFT 10U
+#define MHDP__MHDP_APB_REGS__PMA_TX_VMARGIN_P__RESERVED_1_WIDTH 6U
+#define MHDP__MHDP_APB_REGS__PMA_TX_VMARGIN_P__PMA_TX_VMARGIN_LN_2_MASK 0x00030000U
+#define MHDP__MHDP_APB_REGS__PMA_TX_VMARGIN_P__PMA_TX_VMARGIN_LN_2_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__PMA_TX_VMARGIN_P__PMA_TX_VMARGIN_LN_2_WIDTH 2U
+#define MHDP__MHDP_APB_REGS__PMA_TX_VMARGIN_P__RESERVED_2_MASK 0x00FC0000U
+#define MHDP__MHDP_APB_REGS__PMA_TX_VMARGIN_P__RESERVED_2_SHIFT 18U
+#define MHDP__MHDP_APB_REGS__PMA_TX_VMARGIN_P__RESERVED_2_WIDTH 6U
+#define MHDP__MHDP_APB_REGS__PMA_TX_VMARGIN_P__PMA_TX_VMARGIN_LN_3_MASK 0x03000000U
+#define MHDP__MHDP_APB_REGS__PMA_TX_VMARGIN_P__PMA_TX_VMARGIN_LN_3_SHIFT 24U
+#define MHDP__MHDP_APB_REGS__PMA_TX_VMARGIN_P__PMA_TX_VMARGIN_LN_3_WIDTH 2U
+#define MHDP__MHDP_APB_REGS__PMA_TX_VMARGIN_P__RESERVED_3_MASK 0xFC000000U
+#define MHDP__MHDP_APB_REGS__PMA_TX_VMARGIN_P__RESERVED_3_SHIFT 26U
+#define MHDP__MHDP_APB_REGS__PMA_TX_VMARGIN_P__RESERVED_3_WIDTH 6U
+
+#define MHDP__MHDP_APB_REGS__PMA_TX_DEEMPH_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__PMA_TX_DEEMPH_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__PMA_TX_DEEMPH_P__PMA_TX_DEEMPHASIS_LN_0_MASK 0x00000003U
+#define MHDP__MHDP_APB_REGS__PMA_TX_DEEMPH_P__PMA_TX_DEEMPHASIS_LN_0_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__PMA_TX_DEEMPH_P__PMA_TX_DEEMPHASIS_LN_0_WIDTH 2U
+#define MHDP__MHDP_APB_REGS__PMA_TX_DEEMPH_P__RESERVED_0_MASK 0x000000FCU
+#define MHDP__MHDP_APB_REGS__PMA_TX_DEEMPH_P__RESERVED_0_SHIFT 2U
+#define MHDP__MHDP_APB_REGS__PMA_TX_DEEMPH_P__RESERVED_0_WIDTH 6U
+#define MHDP__MHDP_APB_REGS__PMA_TX_DEEMPH_P__PMA_TX_DEEMPHASIS_LN_1_MASK 0x00000300U
+#define MHDP__MHDP_APB_REGS__PMA_TX_DEEMPH_P__PMA_TX_DEEMPHASIS_LN_1_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__PMA_TX_DEEMPH_P__PMA_TX_DEEMPHASIS_LN_1_WIDTH 2U
+#define MHDP__MHDP_APB_REGS__PMA_TX_DEEMPH_P__RESERVED_1_MASK 0x0000FC00U
+#define MHDP__MHDP_APB_REGS__PMA_TX_DEEMPH_P__RESERVED_1_SHIFT 10U
+#define MHDP__MHDP_APB_REGS__PMA_TX_DEEMPH_P__RESERVED_1_WIDTH 6U
+#define MHDP__MHDP_APB_REGS__PMA_TX_DEEMPH_P__PMA_TX_DEEMPHASIS_LN_2_MASK 0x00030000U
+#define MHDP__MHDP_APB_REGS__PMA_TX_DEEMPH_P__PMA_TX_DEEMPHASIS_LN_2_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__PMA_TX_DEEMPH_P__PMA_TX_DEEMPHASIS_LN_2_WIDTH 2U
+#define MHDP__MHDP_APB_REGS__PMA_TX_DEEMPH_P__RESERVED_2_MASK 0x00FC0000U
+#define MHDP__MHDP_APB_REGS__PMA_TX_DEEMPH_P__RESERVED_2_SHIFT 18U
+#define MHDP__MHDP_APB_REGS__PMA_TX_DEEMPH_P__RESERVED_2_WIDTH 6U
+#define MHDP__MHDP_APB_REGS__PMA_TX_DEEMPH_P__PMA_TX_DEEMPHASIS_LN_3_MASK 0x03000000U
+#define MHDP__MHDP_APB_REGS__PMA_TX_DEEMPH_P__PMA_TX_DEEMPHASIS_LN_3_SHIFT 24U
+#define MHDP__MHDP_APB_REGS__PMA_TX_DEEMPH_P__PMA_TX_DEEMPHASIS_LN_3_WIDTH 2U
+#define MHDP__MHDP_APB_REGS__PMA_TX_DEEMPH_P__RESERVED_3_MASK 0xFC000000U
+#define MHDP__MHDP_APB_REGS__PMA_TX_DEEMPH_P__RESERVED_3_SHIFT 26U
+#define MHDP__MHDP_APB_REGS__PMA_TX_DEEMPH_P__RESERVED_3_WIDTH 6U
+
+#define MHDP__MHDP_APB_REGS__ASF_IPS_CTRL_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ASF_IPS_CTRL_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ASF_IPS_CTRL__IF_ADDR_PARCHECK_EN_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__ASF_IPS_CTRL__IF_ADDR_PARCHECK_EN_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__ASF_IPS_CTRL__IF_ADDR_PARCHECK_EN_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ASF_IPS_CTRL__IF_ADDR_PARCHECK_EN_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ASF_IPS_CTRL__IF_ADDR_PARCHECK_EN_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ASF_IPS_CTRL__RESERVED_MASK 0xFFFFFFFEU
+#define MHDP__MHDP_APB_REGS__ASF_IPS_CTRL__RESERVED_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__ASF_IPS_CTRL__RESERVED_WIDTH 31U
+
+#define MHDP__MHDP_APB_REGS__ASF_INT_STATUS_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ASF_INT_STATUS_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ASF_INT_STATUS__ASF_SRAM_CORR_ERR_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__ASF_INT_STATUS__ASF_SRAM_CORR_ERR_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__ASF_INT_STATUS__ASF_SRAM_CORR_ERR_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ASF_INT_STATUS__ASF_SRAM_CORR_ERR_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ASF_INT_STATUS__ASF_SRAM_CORR_ERR_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ASF_INT_STATUS__ASF_SRAM_UNCORR_ERR_MASK 0x00000002U
+#define MHDP__MHDP_APB_REGS__ASF_INT_STATUS__ASF_SRAM_UNCORR_ERR_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__ASF_INT_STATUS__ASF_SRAM_UNCORR_ERR_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ASF_INT_STATUS__ASF_SRAM_UNCORR_ERR_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ASF_INT_STATUS__ASF_SRAM_UNCORR_ERR_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ASF_INT_STATUS__ASF_DAP_ERR_MASK 0x00000004U
+#define MHDP__MHDP_APB_REGS__ASF_INT_STATUS__ASF_DAP_ERR_SHIFT 2U
+#define MHDP__MHDP_APB_REGS__ASF_INT_STATUS__ASF_DAP_ERR_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ASF_INT_STATUS__ASF_DAP_ERR_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ASF_INT_STATUS__ASF_DAP_ERR_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ASF_INT_STATUS__ASF_CSR_ERR_MASK 0x00000008U
+#define MHDP__MHDP_APB_REGS__ASF_INT_STATUS__ASF_CSR_ERR_SHIFT 3U
+#define MHDP__MHDP_APB_REGS__ASF_INT_STATUS__ASF_CSR_ERR_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ASF_INT_STATUS__ASF_CSR_ERR_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ASF_INT_STATUS__ASF_CSR_ERR_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ASF_INT_STATUS__ASF_TRANS_TO_ERR_MASK 0x00000010U
+#define MHDP__MHDP_APB_REGS__ASF_INT_STATUS__ASF_TRANS_TO_ERR_SHIFT 4U
+#define MHDP__MHDP_APB_REGS__ASF_INT_STATUS__ASF_TRANS_TO_ERR_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ASF_INT_STATUS__ASF_TRANS_TO_ERR_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ASF_INT_STATUS__ASF_TRANS_TO_ERR_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ASF_INT_STATUS__ASF_PROTOCOL_ERR_MASK 0x00000020U
+#define MHDP__MHDP_APB_REGS__ASF_INT_STATUS__ASF_PROTOCOL_ERR_SHIFT 5U
+#define MHDP__MHDP_APB_REGS__ASF_INT_STATUS__ASF_PROTOCOL_ERR_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ASF_INT_STATUS__ASF_PROTOCOL_ERR_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ASF_INT_STATUS__ASF_PROTOCOL_ERR_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ASF_INT_STATUS__ASF_INTEGRITY_ERR_MASK 0x00000040U
+#define MHDP__MHDP_APB_REGS__ASF_INT_STATUS__ASF_INTEGRITY_ERR_SHIFT 6U
+#define MHDP__MHDP_APB_REGS__ASF_INT_STATUS__ASF_INTEGRITY_ERR_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ASF_INT_STATUS__ASF_INTEGRITY_ERR_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ASF_INT_STATUS__ASF_INTEGRITY_ERR_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ASF_INT_STATUS__RESERVED_31_7_MASK 0xFFFFFF80U
+#define MHDP__MHDP_APB_REGS__ASF_INT_STATUS__RESERVED_31_7_SHIFT 7U
+#define MHDP__MHDP_APB_REGS__ASF_INT_STATUS__RESERVED_31_7_WIDTH 25U
+
+#define MHDP__MHDP_APB_REGS__ASF_INT_RAW_STATUS_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ASF_INT_RAW_STATUS_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ASF_INT_RAW_STATUS__ASF_SRAM_CORR_ERR_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__ASF_INT_RAW_STATUS__ASF_SRAM_CORR_ERR_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__ASF_INT_RAW_STATUS__ASF_SRAM_CORR_ERR_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ASF_INT_RAW_STATUS__ASF_SRAM_CORR_ERR_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ASF_INT_RAW_STATUS__ASF_SRAM_CORR_ERR_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ASF_INT_RAW_STATUS__ASF_SRAM_UNCORR_ERR_MASK 0x00000002U
+#define MHDP__MHDP_APB_REGS__ASF_INT_RAW_STATUS__ASF_SRAM_UNCORR_ERR_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__ASF_INT_RAW_STATUS__ASF_SRAM_UNCORR_ERR_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ASF_INT_RAW_STATUS__ASF_SRAM_UNCORR_ERR_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ASF_INT_RAW_STATUS__ASF_SRAM_UNCORR_ERR_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ASF_INT_RAW_STATUS__ASF_DAP_ERR_MASK 0x00000004U
+#define MHDP__MHDP_APB_REGS__ASF_INT_RAW_STATUS__ASF_DAP_ERR_SHIFT 2U
+#define MHDP__MHDP_APB_REGS__ASF_INT_RAW_STATUS__ASF_DAP_ERR_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ASF_INT_RAW_STATUS__ASF_DAP_ERR_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ASF_INT_RAW_STATUS__ASF_DAP_ERR_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ASF_INT_RAW_STATUS__ASF_CSR_ERR_MASK 0x00000008U
+#define MHDP__MHDP_APB_REGS__ASF_INT_RAW_STATUS__ASF_CSR_ERR_SHIFT 3U
+#define MHDP__MHDP_APB_REGS__ASF_INT_RAW_STATUS__ASF_CSR_ERR_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ASF_INT_RAW_STATUS__ASF_CSR_ERR_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ASF_INT_RAW_STATUS__ASF_CSR_ERR_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ASF_INT_RAW_STATUS__ASF_TRANS_TO_ERR_MASK 0x00000010U
+#define MHDP__MHDP_APB_REGS__ASF_INT_RAW_STATUS__ASF_TRANS_TO_ERR_SHIFT 4U
+#define MHDP__MHDP_APB_REGS__ASF_INT_RAW_STATUS__ASF_TRANS_TO_ERR_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ASF_INT_RAW_STATUS__ASF_TRANS_TO_ERR_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ASF_INT_RAW_STATUS__ASF_TRANS_TO_ERR_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ASF_INT_RAW_STATUS__ASF_PROTOCOL_ERR_MASK 0x00000020U
+#define MHDP__MHDP_APB_REGS__ASF_INT_RAW_STATUS__ASF_PROTOCOL_ERR_SHIFT 5U
+#define MHDP__MHDP_APB_REGS__ASF_INT_RAW_STATUS__ASF_PROTOCOL_ERR_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ASF_INT_RAW_STATUS__ASF_PROTOCOL_ERR_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ASF_INT_RAW_STATUS__ASF_PROTOCOL_ERR_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ASF_INT_RAW_STATUS__SF_INTEGRITY_ERR_MASK 0x00000040U
+#define MHDP__MHDP_APB_REGS__ASF_INT_RAW_STATUS__SF_INTEGRITY_ERR_SHIFT 6U
+#define MHDP__MHDP_APB_REGS__ASF_INT_RAW_STATUS__SF_INTEGRITY_ERR_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ASF_INT_RAW_STATUS__SF_INTEGRITY_ERR_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ASF_INT_RAW_STATUS__SF_INTEGRITY_ERR_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ASF_INT_RAW_STATUS__RESERVED_31_7_MASK 0xFFFFFF80U
+#define MHDP__MHDP_APB_REGS__ASF_INT_RAW_STATUS__RESERVED_31_7_SHIFT 7U
+#define MHDP__MHDP_APB_REGS__ASF_INT_RAW_STATUS__RESERVED_31_7_WIDTH 25U
+
+#define MHDP__MHDP_APB_REGS__ASF_INT_MASK_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ASF_INT_MASK_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ASF_INT_MASK__ASF_SRAM_CORR_ERR_MASK_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__ASF_INT_MASK__ASF_SRAM_CORR_ERR_MASK_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__ASF_INT_MASK__ASF_SRAM_CORR_ERR_MASK_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ASF_INT_MASK__ASF_SRAM_CORR_ERR_MASK_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ASF_INT_MASK__ASF_SRAM_CORR_ERR_MASK_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ASF_INT_MASK__ASF_SRAM_UNCORR_ERR_MASK_MASK 0x00000002U
+#define MHDP__MHDP_APB_REGS__ASF_INT_MASK__ASF_SRAM_UNCORR_ERR_MASK_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__ASF_INT_MASK__ASF_SRAM_UNCORR_ERR_MASK_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ASF_INT_MASK__ASF_SRAM_UNCORR_ERR_MASK_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ASF_INT_MASK__ASF_SRAM_UNCORR_ERR_MASK_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ASF_INT_MASK__ASF_DAP_ERR_MASK_MASK 0x00000004U
+#define MHDP__MHDP_APB_REGS__ASF_INT_MASK__ASF_DAP_ERR_MASK_SHIFT 2U
+#define MHDP__MHDP_APB_REGS__ASF_INT_MASK__ASF_DAP_ERR_MASK_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ASF_INT_MASK__ASF_DAP_ERR_MASK_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ASF_INT_MASK__ASF_DAP_ERR_MASK_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ASF_INT_MASK__ASF_CSR_ERR_MASK_MASK 0x00000008U
+#define MHDP__MHDP_APB_REGS__ASF_INT_MASK__ASF_CSR_ERR_MASK_SHIFT 3U
+#define MHDP__MHDP_APB_REGS__ASF_INT_MASK__ASF_CSR_ERR_MASK_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ASF_INT_MASK__ASF_CSR_ERR_MASK_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ASF_INT_MASK__ASF_CSR_ERR_MASK_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ASF_INT_MASK__ASF_TRANS_TO_ERR_MASK_MASK 0x00000010U
+#define MHDP__MHDP_APB_REGS__ASF_INT_MASK__ASF_TRANS_TO_ERR_MASK_SHIFT 4U
+#define MHDP__MHDP_APB_REGS__ASF_INT_MASK__ASF_TRANS_TO_ERR_MASK_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ASF_INT_MASK__ASF_TRANS_TO_ERR_MASK_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ASF_INT_MASK__ASF_TRANS_TO_ERR_MASK_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ASF_INT_MASK__ASF_PROTOCOL_ERR_MASK_MASK 0x00000020U
+#define MHDP__MHDP_APB_REGS__ASF_INT_MASK__ASF_PROTOCOL_ERR_MASK_SHIFT 5U
+#define MHDP__MHDP_APB_REGS__ASF_INT_MASK__ASF_PROTOCOL_ERR_MASK_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ASF_INT_MASK__ASF_PROTOCOL_ERR_MASK_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ASF_INT_MASK__ASF_PROTOCOL_ERR_MASK_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ASF_INT_MASK__ASF_INTEGRITY_ERR_MASK_MASK 0x00000040U
+#define MHDP__MHDP_APB_REGS__ASF_INT_MASK__ASF_INTEGRITY_ERR_MASK_SHIFT 6U
+#define MHDP__MHDP_APB_REGS__ASF_INT_MASK__ASF_INTEGRITY_ERR_MASK_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ASF_INT_MASK__ASF_INTEGRITY_ERR_MASK_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ASF_INT_MASK__ASF_INTEGRITY_ERR_MASK_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ASF_INT_MASK__RESERVED_31_7_MASK 0xFFFFFF80U
+#define MHDP__MHDP_APB_REGS__ASF_INT_MASK__RESERVED_31_7_SHIFT 7U
+#define MHDP__MHDP_APB_REGS__ASF_INT_MASK__RESERVED_31_7_WIDTH 25U
+
+#define MHDP__MHDP_APB_REGS__ASF_INT_TEST_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ASF_INT_TEST_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ASF_INT_TEST__ASF_SRAM_CORR_ERR_TEST_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__ASF_INT_TEST__ASF_SRAM_CORR_ERR_TEST_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__ASF_INT_TEST__ASF_SRAM_CORR_ERR_TEST_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ASF_INT_TEST__ASF_SRAM_CORR_ERR_TEST_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ASF_INT_TEST__ASF_SRAM_CORR_ERR_TEST_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ASF_INT_TEST__ASF_SRAM_UNCORR_ERR_TEST_MASK 0x00000002U
+#define MHDP__MHDP_APB_REGS__ASF_INT_TEST__ASF_SRAM_UNCORR_ERR_TEST_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__ASF_INT_TEST__ASF_SRAM_UNCORR_ERR_TEST_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ASF_INT_TEST__ASF_SRAM_UNCORR_ERR_TEST_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ASF_INT_TEST__ASF_SRAM_UNCORR_ERR_TEST_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ASF_INT_TEST__ASF_DAP_ERR_TEST_MASK 0x00000004U
+#define MHDP__MHDP_APB_REGS__ASF_INT_TEST__ASF_DAP_ERR_TEST_SHIFT 2U
+#define MHDP__MHDP_APB_REGS__ASF_INT_TEST__ASF_DAP_ERR_TEST_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ASF_INT_TEST__ASF_DAP_ERR_TEST_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ASF_INT_TEST__ASF_DAP_ERR_TEST_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ASF_INT_TEST__ASF_CSR_ERR_TEST_MASK 0x00000008U
+#define MHDP__MHDP_APB_REGS__ASF_INT_TEST__ASF_CSR_ERR_TEST_SHIFT 3U
+#define MHDP__MHDP_APB_REGS__ASF_INT_TEST__ASF_CSR_ERR_TEST_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ASF_INT_TEST__ASF_CSR_ERR_TEST_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ASF_INT_TEST__ASF_CSR_ERR_TEST_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ASF_INT_TEST__ASF_TRANS_TO_ERR_TEST_MASK 0x00000010U
+#define MHDP__MHDP_APB_REGS__ASF_INT_TEST__ASF_TRANS_TO_ERR_TEST_SHIFT 4U
+#define MHDP__MHDP_APB_REGS__ASF_INT_TEST__ASF_TRANS_TO_ERR_TEST_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ASF_INT_TEST__ASF_TRANS_TO_ERR_TEST_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ASF_INT_TEST__ASF_TRANS_TO_ERR_TEST_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ASF_INT_TEST__ASF_PROTOCOL_ERR_TEST_MASK 0x00000020U
+#define MHDP__MHDP_APB_REGS__ASF_INT_TEST__ASF_PROTOCOL_ERR_TEST_SHIFT 5U
+#define MHDP__MHDP_APB_REGS__ASF_INT_TEST__ASF_PROTOCOL_ERR_TEST_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ASF_INT_TEST__ASF_PROTOCOL_ERR_TEST_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ASF_INT_TEST__ASF_PROTOCOL_ERR_TEST_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ASF_INT_TEST__ASF_INTEGRITY_ERR_TEST_MASK 0x00000040U
+#define MHDP__MHDP_APB_REGS__ASF_INT_TEST__ASF_INTEGRITY_ERR_TEST_SHIFT 6U
+#define MHDP__MHDP_APB_REGS__ASF_INT_TEST__ASF_INTEGRITY_ERR_TEST_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ASF_INT_TEST__ASF_INTEGRITY_ERR_TEST_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ASF_INT_TEST__ASF_INTEGRITY_ERR_TEST_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ASF_INT_TEST__RESERVED_31_7_MASK 0xFFFFFF80U
+#define MHDP__MHDP_APB_REGS__ASF_INT_TEST__RESERVED_31_7_SHIFT 7U
+#define MHDP__MHDP_APB_REGS__ASF_INT_TEST__RESERVED_31_7_WIDTH 25U
+
+#define MHDP__MHDP_APB_REGS__ASF_FATAL_NONFATAL_SELECT_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ASF_FATAL_NONFATAL_SELECT_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_SRAM_CORR_ERR_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_SRAM_CORR_ERR_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_SRAM_CORR_ERR_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_SRAM_CORR_ERR_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_SRAM_CORR_ERR_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_SRAM_UNCORR_ERR_MASK 0x00000002U
+#define MHDP__MHDP_APB_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_SRAM_UNCORR_ERR_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_SRAM_UNCORR_ERR_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_SRAM_UNCORR_ERR_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_SRAM_UNCORR_ERR_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_DAP_ERR_MASK 0x00000004U
+#define MHDP__MHDP_APB_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_DAP_ERR_SHIFT 2U
+#define MHDP__MHDP_APB_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_DAP_ERR_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_DAP_ERR_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_DAP_ERR_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_CSR_ERR_MASK 0x00000008U
+#define MHDP__MHDP_APB_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_CSR_ERR_SHIFT 3U
+#define MHDP__MHDP_APB_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_CSR_ERR_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_CSR_ERR_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_CSR_ERR_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_TRANS_TO_ERR_MASK 0x00000010U
+#define MHDP__MHDP_APB_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_TRANS_TO_ERR_SHIFT 4U
+#define MHDP__MHDP_APB_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_TRANS_TO_ERR_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_TRANS_TO_ERR_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_TRANS_TO_ERR_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_PROTOCOL_ERR_MASK 0x00000020U
+#define MHDP__MHDP_APB_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_PROTOCOL_ERR_SHIFT 5U
+#define MHDP__MHDP_APB_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_PROTOCOL_ERR_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_PROTOCOL_ERR_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_PROTOCOL_ERR_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_INTEGRITY_ERR_MASK 0x00000040U
+#define MHDP__MHDP_APB_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_INTEGRITY_ERR_SHIFT 6U
+#define MHDP__MHDP_APB_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_INTEGRITY_ERR_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_INTEGRITY_ERR_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ASF_FATAL_NONFATAL_SELECT__ASF_INTEGRITY_ERR_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ASF_FATAL_NONFATAL_SELECT__RESERVED_31_7_MASK 0xFFFFFF80U
+#define MHDP__MHDP_APB_REGS__ASF_FATAL_NONFATAL_SELECT__RESERVED_31_7_SHIFT 7U
+#define MHDP__MHDP_APB_REGS__ASF_FATAL_NONFATAL_SELECT__RESERVED_31_7_WIDTH 25U
+
+#define MHDP__MHDP_APB_REGS__ASF_SRAM_CORR_FAULT_STATUS_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ASF_SRAM_CORR_FAULT_STATUS_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ASF_SRAM_CORR_FAULT_STATUS__ASF_SRAM_CORR_FAULT_ADDR_MASK 0x00FFFFFFU
+#define MHDP__MHDP_APB_REGS__ASF_SRAM_CORR_FAULT_STATUS__ASF_SRAM_CORR_FAULT_ADDR_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__ASF_SRAM_CORR_FAULT_STATUS__ASF_SRAM_CORR_FAULT_ADDR_WIDTH 24U
+#define MHDP__MHDP_APB_REGS__ASF_SRAM_CORR_FAULT_STATUS__ASF_SRAM_CORR_FAULT_INST_MASK 0xFF000000U
+#define MHDP__MHDP_APB_REGS__ASF_SRAM_CORR_FAULT_STATUS__ASF_SRAM_CORR_FAULT_INST_SHIFT 24U
+#define MHDP__MHDP_APB_REGS__ASF_SRAM_CORR_FAULT_STATUS__ASF_SRAM_CORR_FAULT_INST_WIDTH 8U
+
+#define MHDP__MHDP_APB_REGS__ASF_SRAM_UNCORR_FAULT_STATUS_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ASF_SRAM_UNCORR_FAULT_STATUS_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ASF_SRAM_UNCORR_FAULT_STATUS__ASF_SRAM_UNCORR_FAULT_ADDR_MASK 0x00FFFFFFU
+#define MHDP__MHDP_APB_REGS__ASF_SRAM_UNCORR_FAULT_STATUS__ASF_SRAM_UNCORR_FAULT_ADDR_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__ASF_SRAM_UNCORR_FAULT_STATUS__ASF_SRAM_UNCORR_FAULT_ADDR_WIDTH 24U
+#define MHDP__MHDP_APB_REGS__ASF_SRAM_UNCORR_FAULT_STATUS__ASF_SRAM_UNCORR_FAULT_INST_MASK 0xFF000000U
+#define MHDP__MHDP_APB_REGS__ASF_SRAM_UNCORR_FAULT_STATUS__ASF_SRAM_UNCORR_FAULT_INST_SHIFT 24U
+#define MHDP__MHDP_APB_REGS__ASF_SRAM_UNCORR_FAULT_STATUS__ASF_SRAM_UNCORR_FAULT_INST_WIDTH 8U
+
+#define MHDP__MHDP_APB_REGS__ASF_SRAM_FAULT_STATUS_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ASF_SRAM_FAULT_STATUS_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ASF_SRAM_FAULT_STATUS__ASF_SRAM_FAULT_CORR_STATS_MASK 0x0000FFFFU
+#define MHDP__MHDP_APB_REGS__ASF_SRAM_FAULT_STATUS__ASF_SRAM_FAULT_CORR_STATS_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__ASF_SRAM_FAULT_STATUS__ASF_SRAM_FAULT_CORR_STATS_WIDTH 16U
+#define MHDP__MHDP_APB_REGS__ASF_SRAM_FAULT_STATUS__ASF_SRAM_FAULT_UNCORR_STATS_MASK 0xFFFF0000U
+#define MHDP__MHDP_APB_REGS__ASF_SRAM_FAULT_STATUS__ASF_SRAM_FAULT_UNCORR_STATS_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__ASF_SRAM_FAULT_STATUS__ASF_SRAM_FAULT_UNCORR_STATS_WIDTH 16U
+
+#define MHDP__MHDP_APB_REGS__ASF_TRANS_TO_CTRL_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ASF_TRANS_TO_CTRL_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ASF_TRANS_TO_CTRL__ASF_TRANS_TO_CTRL_MASK 0x0000FFFFU
+#define MHDP__MHDP_APB_REGS__ASF_TRANS_TO_CTRL__ASF_TRANS_TO_CTRL_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__ASF_TRANS_TO_CTRL__ASF_TRANS_TO_CTRL_WIDTH 16U
+#define MHDP__MHDP_APB_REGS__ASF_TRANS_TO_CTRL__RESERVED_30_16_MASK 0x7FFF0000U
+#define MHDP__MHDP_APB_REGS__ASF_TRANS_TO_CTRL__RESERVED_30_16_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__ASF_TRANS_TO_CTRL__RESERVED_30_16_WIDTH 15U
+#define MHDP__MHDP_APB_REGS__ASF_TRANS_TO_CTRL__ASF_TRANS_TO_EN_MASK 0x80000000U
+#define MHDP__MHDP_APB_REGS__ASF_TRANS_TO_CTRL__ASF_TRANS_TO_EN_SHIFT 31U
+#define MHDP__MHDP_APB_REGS__ASF_TRANS_TO_CTRL__ASF_TRANS_TO_EN_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ASF_TRANS_TO_CTRL__ASF_TRANS_TO_EN_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ASF_TRANS_TO_CTRL__ASF_TRANS_TO_EN_WOSET 0U
+
+#define MHDP__MHDP_APB_REGS__ASF_TRANS_TO_FAULT_MASK_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ASF_TRANS_TO_FAULT_MASK_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ASF_TRANS_TO_FAULT_MASK__ASF_TRANS_TO_FAULT_0_MASK_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__ASF_TRANS_TO_FAULT_MASK__ASF_TRANS_TO_FAULT_0_MASK_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__ASF_TRANS_TO_FAULT_MASK__ASF_TRANS_TO_FAULT_0_MASK_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ASF_TRANS_TO_FAULT_MASK__ASF_TRANS_TO_FAULT_0_MASK_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ASF_TRANS_TO_FAULT_MASK__ASF_TRANS_TO_FAULT_0_MASK_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ASF_TRANS_TO_FAULT_MASK__ASF_TRANS_TO_FAULT_1_MASK_MASK 0x00000002U
+#define MHDP__MHDP_APB_REGS__ASF_TRANS_TO_FAULT_MASK__ASF_TRANS_TO_FAULT_1_MASK_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__ASF_TRANS_TO_FAULT_MASK__ASF_TRANS_TO_FAULT_1_MASK_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ASF_TRANS_TO_FAULT_MASK__ASF_TRANS_TO_FAULT_1_MASK_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ASF_TRANS_TO_FAULT_MASK__ASF_TRANS_TO_FAULT_1_MASK_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ASF_TRANS_TO_FAULT_MASK__ASF_TRANS_TO_FAULT_2_MASK_MASK 0x00000004U
+#define MHDP__MHDP_APB_REGS__ASF_TRANS_TO_FAULT_MASK__ASF_TRANS_TO_FAULT_2_MASK_SHIFT 2U
+#define MHDP__MHDP_APB_REGS__ASF_TRANS_TO_FAULT_MASK__ASF_TRANS_TO_FAULT_2_MASK_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ASF_TRANS_TO_FAULT_MASK__ASF_TRANS_TO_FAULT_2_MASK_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ASF_TRANS_TO_FAULT_MASK__ASF_TRANS_TO_FAULT_2_MASK_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ASF_TRANS_TO_FAULT_MASK__RESERVED_31_3_MASK 0xFFFFFFF8U
+#define MHDP__MHDP_APB_REGS__ASF_TRANS_TO_FAULT_MASK__RESERVED_31_3_SHIFT 3U
+#define MHDP__MHDP_APB_REGS__ASF_TRANS_TO_FAULT_MASK__RESERVED_31_3_WIDTH 29U
+
+#define MHDP__MHDP_APB_REGS__ASF_TRANS_TO_FAULT_STATUS_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ASF_TRANS_TO_FAULT_STATUS_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ASF_TRANS_TO_FAULT_STATUS__ASF_TRANS_TO_FAULT_0_STATUS_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__ASF_TRANS_TO_FAULT_STATUS__ASF_TRANS_TO_FAULT_0_STATUS_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__ASF_TRANS_TO_FAULT_STATUS__ASF_TRANS_TO_FAULT_0_STATUS_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ASF_TRANS_TO_FAULT_STATUS__ASF_TRANS_TO_FAULT_0_STATUS_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ASF_TRANS_TO_FAULT_STATUS__ASF_TRANS_TO_FAULT_0_STATUS_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ASF_TRANS_TO_FAULT_STATUS__ASF_TRANS_TO_FAULT_1_STATUS_MASK 0x00000002U
+#define MHDP__MHDP_APB_REGS__ASF_TRANS_TO_FAULT_STATUS__ASF_TRANS_TO_FAULT_1_STATUS_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__ASF_TRANS_TO_FAULT_STATUS__ASF_TRANS_TO_FAULT_1_STATUS_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ASF_TRANS_TO_FAULT_STATUS__ASF_TRANS_TO_FAULT_1_STATUS_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ASF_TRANS_TO_FAULT_STATUS__ASF_TRANS_TO_FAULT_1_STATUS_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ASF_TRANS_TO_FAULT_STATUS__ASF_TRANS_TO_FAULT_2_STATUS_MASK 0x00000004U
+#define MHDP__MHDP_APB_REGS__ASF_TRANS_TO_FAULT_STATUS__ASF_TRANS_TO_FAULT_2_STATUS_SHIFT 2U
+#define MHDP__MHDP_APB_REGS__ASF_TRANS_TO_FAULT_STATUS__ASF_TRANS_TO_FAULT_2_STATUS_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ASF_TRANS_TO_FAULT_STATUS__ASF_TRANS_TO_FAULT_2_STATUS_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ASF_TRANS_TO_FAULT_STATUS__ASF_TRANS_TO_FAULT_2_STATUS_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ASF_TRANS_TO_FAULT_STATUS__RESERVED_31_3_MASK 0xFFFFFFF8U
+#define MHDP__MHDP_APB_REGS__ASF_TRANS_TO_FAULT_STATUS__RESERVED_31_3_SHIFT 3U
+#define MHDP__MHDP_APB_REGS__ASF_TRANS_TO_FAULT_STATUS__RESERVED_31_3_WIDTH 29U
+
+#define MHDP__MHDP_APB_REGS__ASF_PROTOCOL_FAULT_MASK_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ASF_PROTOCOL_FAULT_MASK_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ASF_PROTOCOL_FAULT_MASK__ASF_PROTOCOL_FAULT_0_MASK_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__ASF_PROTOCOL_FAULT_MASK__ASF_PROTOCOL_FAULT_0_MASK_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__ASF_PROTOCOL_FAULT_MASK__ASF_PROTOCOL_FAULT_0_MASK_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ASF_PROTOCOL_FAULT_MASK__ASF_PROTOCOL_FAULT_0_MASK_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ASF_PROTOCOL_FAULT_MASK__ASF_PROTOCOL_FAULT_0_MASK_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ASF_PROTOCOL_FAULT_MASK__ASF_PROTOCOL_FAULT_1_MASK_MASK 0x00000002U
+#define MHDP__MHDP_APB_REGS__ASF_PROTOCOL_FAULT_MASK__ASF_PROTOCOL_FAULT_1_MASK_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__ASF_PROTOCOL_FAULT_MASK__ASF_PROTOCOL_FAULT_1_MASK_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ASF_PROTOCOL_FAULT_MASK__ASF_PROTOCOL_FAULT_1_MASK_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ASF_PROTOCOL_FAULT_MASK__ASF_PROTOCOL_FAULT_1_MASK_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ASF_PROTOCOL_FAULT_MASK__ASF_PROTOCOL_FAULT_2_MASK_MASK 0x00000004U
+#define MHDP__MHDP_APB_REGS__ASF_PROTOCOL_FAULT_MASK__ASF_PROTOCOL_FAULT_2_MASK_SHIFT 2U
+#define MHDP__MHDP_APB_REGS__ASF_PROTOCOL_FAULT_MASK__ASF_PROTOCOL_FAULT_2_MASK_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ASF_PROTOCOL_FAULT_MASK__ASF_PROTOCOL_FAULT_2_MASK_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ASF_PROTOCOL_FAULT_MASK__ASF_PROTOCOL_FAULT_2_MASK_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ASF_PROTOCOL_FAULT_MASK__ASF_PROTOCOL_FAULT_3_MASK_MASK 0x00000008U
+#define MHDP__MHDP_APB_REGS__ASF_PROTOCOL_FAULT_MASK__ASF_PROTOCOL_FAULT_3_MASK_SHIFT 3U
+#define MHDP__MHDP_APB_REGS__ASF_PROTOCOL_FAULT_MASK__ASF_PROTOCOL_FAULT_3_MASK_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ASF_PROTOCOL_FAULT_MASK__ASF_PROTOCOL_FAULT_3_MASK_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ASF_PROTOCOL_FAULT_MASK__ASF_PROTOCOL_FAULT_3_MASK_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ASF_PROTOCOL_FAULT_MASK__RESERVED_31_4_MASK 0xFFFFFFF0U
+#define MHDP__MHDP_APB_REGS__ASF_PROTOCOL_FAULT_MASK__RESERVED_31_4_SHIFT 4U
+#define MHDP__MHDP_APB_REGS__ASF_PROTOCOL_FAULT_MASK__RESERVED_31_4_WIDTH 28U
+
+#define MHDP__MHDP_APB_REGS__ASF_PROTOCOL_FAULT_STATUS_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ASF_PROTOCOL_FAULT_STATUS_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ASF_PROTOCOL_FAULT_STATUS__ASF_PROTOCOL_FAULT_0_STATUS_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__ASF_PROTOCOL_FAULT_STATUS__ASF_PROTOCOL_FAULT_0_STATUS_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__ASF_PROTOCOL_FAULT_STATUS__ASF_PROTOCOL_FAULT_0_STATUS_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ASF_PROTOCOL_FAULT_STATUS__ASF_PROTOCOL_FAULT_0_STATUS_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ASF_PROTOCOL_FAULT_STATUS__ASF_PROTOCOL_FAULT_0_STATUS_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ASF_PROTOCOL_FAULT_STATUS__ASF_PROTOCOL_FAULT_1_STATUS_MASK 0x00000002U
+#define MHDP__MHDP_APB_REGS__ASF_PROTOCOL_FAULT_STATUS__ASF_PROTOCOL_FAULT_1_STATUS_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__ASF_PROTOCOL_FAULT_STATUS__ASF_PROTOCOL_FAULT_1_STATUS_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ASF_PROTOCOL_FAULT_STATUS__ASF_PROTOCOL_FAULT_1_STATUS_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ASF_PROTOCOL_FAULT_STATUS__ASF_PROTOCOL_FAULT_1_STATUS_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ASF_PROTOCOL_FAULT_STATUS__ASF_PROTOCOL_FAULT_2_STATUS_MASK 0x00000004U
+#define MHDP__MHDP_APB_REGS__ASF_PROTOCOL_FAULT_STATUS__ASF_PROTOCOL_FAULT_2_STATUS_SHIFT 2U
+#define MHDP__MHDP_APB_REGS__ASF_PROTOCOL_FAULT_STATUS__ASF_PROTOCOL_FAULT_2_STATUS_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ASF_PROTOCOL_FAULT_STATUS__ASF_PROTOCOL_FAULT_2_STATUS_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ASF_PROTOCOL_FAULT_STATUS__ASF_PROTOCOL_FAULT_2_STATUS_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ASF_PROTOCOL_FAULT_STATUS__ASF_PROTOCOL_FAULT_3_STATUS_MASK 0x00000008U
+#define MHDP__MHDP_APB_REGS__ASF_PROTOCOL_FAULT_STATUS__ASF_PROTOCOL_FAULT_3_STATUS_SHIFT 3U
+#define MHDP__MHDP_APB_REGS__ASF_PROTOCOL_FAULT_STATUS__ASF_PROTOCOL_FAULT_3_STATUS_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ASF_PROTOCOL_FAULT_STATUS__ASF_PROTOCOL_FAULT_3_STATUS_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ASF_PROTOCOL_FAULT_STATUS__ASF_PROTOCOL_FAULT_3_STATUS_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ASF_PROTOCOL_FAULT_STATUS__RESERVED_MASK 0xFFFFFFF0U
+#define MHDP__MHDP_APB_REGS__ASF_PROTOCOL_FAULT_STATUS__RESERVED_SHIFT 4U
+#define MHDP__MHDP_APB_REGS__ASF_PROTOCOL_FAULT_STATUS__RESERVED_WIDTH 28U
+
+#define MHDP__MHDP_APB_REGS__COM_MAIN_CONF_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__COM_MAIN_CONF_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__COM_MAIN_CONF_P__REGS_SPLIT_PANEL_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__COM_MAIN_CONF_P__REGS_SPLIT_PANEL_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__COM_MAIN_CONF_P__REGS_SPLIT_PANEL_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__COM_MAIN_CONF_P__REGS_SPLIT_PANEL_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__COM_MAIN_CONF_P__REGS_SPLIT_PANEL_WOSET 0U
+#define MHDP__MHDP_APB_REGS__COM_MAIN_CONF_P__REGS_MULTIPLEX_MODE_MASK 0x00000002U
+#define MHDP__MHDP_APB_REGS__COM_MAIN_CONF_P__REGS_MULTIPLEX_MODE_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__COM_MAIN_CONF_P__REGS_MULTIPLEX_MODE_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__COM_MAIN_CONF_P__REGS_MULTIPLEX_MODE_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__COM_MAIN_CONF_P__REGS_MULTIPLEX_MODE_WOSET 0U
+#define MHDP__MHDP_APB_REGS__COM_MAIN_CONF_P__REGS_MULTIPLEX_SEL_OUT_MASK 0x00000004U
+#define MHDP__MHDP_APB_REGS__COM_MAIN_CONF_P__REGS_MULTIPLEX_SEL_OUT_SHIFT 2U
+#define MHDP__MHDP_APB_REGS__COM_MAIN_CONF_P__REGS_MULTIPLEX_SEL_OUT_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__COM_MAIN_CONF_P__REGS_MULTIPLEX_SEL_OUT_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__COM_MAIN_CONF_P__REGS_MULTIPLEX_SEL_OUT_WOSET 0U
+#define MHDP__MHDP_APB_REGS__COM_MAIN_CONF_P__REGS_DE_RASTER_ENABLE_MASK 0x00000008U
+#define MHDP__MHDP_APB_REGS__COM_MAIN_CONF_P__REGS_DE_RASTER_ENABLE_SHIFT 3U
+#define MHDP__MHDP_APB_REGS__COM_MAIN_CONF_P__REGS_DE_RASTER_ENABLE_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__COM_MAIN_CONF_P__REGS_DE_RASTER_ENABLE_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__COM_MAIN_CONF_P__REGS_DE_RASTER_ENABLE_WOSET 0U
+#define MHDP__MHDP_APB_REGS__COM_MAIN_CONF_P__INPUT_MODE_MASK 0x00000010U
+#define MHDP__MHDP_APB_REGS__COM_MAIN_CONF_P__INPUT_MODE_SHIFT 4U
+#define MHDP__MHDP_APB_REGS__COM_MAIN_CONF_P__INPUT_MODE_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__COM_MAIN_CONF_P__INPUT_MODE_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__COM_MAIN_CONF_P__INPUT_MODE_WOSET 0U
+#define MHDP__MHDP_APB_REGS__COM_MAIN_CONF_P__MULTIPLEX_MODE_EOC_ENABLE_MASK 0x00000020U
+#define MHDP__MHDP_APB_REGS__COM_MAIN_CONF_P__MULTIPLEX_MODE_EOC_ENABLE_SHIFT 5U
+#define MHDP__MHDP_APB_REGS__COM_MAIN_CONF_P__MULTIPLEX_MODE_EOC_ENABLE_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__COM_MAIN_CONF_P__MULTIPLEX_MODE_EOC_ENABLE_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__COM_MAIN_CONF_P__MULTIPLEX_MODE_EOC_ENABLE_WOSET 0U
+#define MHDP__MHDP_APB_REGS__COM_MAIN_CONF_P__AUTO_REGS_DB_UPDATE_MASK 0x00000040U
+#define MHDP__MHDP_APB_REGS__COM_MAIN_CONF_P__AUTO_REGS_DB_UPDATE_SHIFT 6U
+#define MHDP__MHDP_APB_REGS__COM_MAIN_CONF_P__AUTO_REGS_DB_UPDATE_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__COM_MAIN_CONF_P__AUTO_REGS_DB_UPDATE_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__COM_MAIN_CONF_P__AUTO_REGS_DB_UPDATE_WOSET 0U
+#define MHDP__MHDP_APB_REGS__COM_MAIN_CONF_P__RESERVED_0_MASK 0xFFFFFF80U
+#define MHDP__MHDP_APB_REGS__COM_MAIN_CONF_P__RESERVED_0_SHIFT 7U
+#define MHDP__MHDP_APB_REGS__COM_MAIN_CONF_P__RESERVED_0_WIDTH 25U
+
+#define MHDP__MHDP_APB_REGS__ENC0_MAIN_CONF_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC0_MAIN_CONF_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC0_MAIN_CONF_P__INPUT_BPC_MASK 0x00000003U
+#define MHDP__MHDP_APB_REGS__ENC0_MAIN_CONF_P__INPUT_BPC_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__ENC0_MAIN_CONF_P__INPUT_BPC_WIDTH 2U
+#define MHDP__MHDP_APB_REGS__ENC0_MAIN_CONF_P__CONVERT_RGB_MASK 0x00000004U
+#define MHDP__MHDP_APB_REGS__ENC0_MAIN_CONF_P__CONVERT_RGB_SHIFT 2U
+#define MHDP__MHDP_APB_REGS__ENC0_MAIN_CONF_P__CONVERT_RGB_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC0_MAIN_CONF_P__CONVERT_RGB_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC0_MAIN_CONF_P__CONVERT_RGB_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC0_MAIN_CONF_P__ENABLE_422_MASK 0x00000008U
+#define MHDP__MHDP_APB_REGS__ENC0_MAIN_CONF_P__ENABLE_422_SHIFT 3U
+#define MHDP__MHDP_APB_REGS__ENC0_MAIN_CONF_P__ENABLE_422_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC0_MAIN_CONF_P__ENABLE_422_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC0_MAIN_CONF_P__ENABLE_422_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC0_MAIN_CONF_P__LINEBUF_DEPTH_MASK 0x000000F0U
+#define MHDP__MHDP_APB_REGS__ENC0_MAIN_CONF_P__LINEBUF_DEPTH_SHIFT 4U
+#define MHDP__MHDP_APB_REGS__ENC0_MAIN_CONF_P__LINEBUF_DEPTH_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__ENC0_MAIN_CONF_P__BITS_PER_PIXEL_MASK 0x0003FF00U
+#define MHDP__MHDP_APB_REGS__ENC0_MAIN_CONF_P__BITS_PER_PIXEL_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__ENC0_MAIN_CONF_P__BITS_PER_PIXEL_WIDTH 10U
+#define MHDP__MHDP_APB_REGS__ENC0_MAIN_CONF_P__BLOCK_PRED_ENABLE_MASK 0x00040000U
+#define MHDP__MHDP_APB_REGS__ENC0_MAIN_CONF_P__BLOCK_PRED_ENABLE_SHIFT 18U
+#define MHDP__MHDP_APB_REGS__ENC0_MAIN_CONF_P__BLOCK_PRED_ENABLE_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC0_MAIN_CONF_P__BLOCK_PRED_ENABLE_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC0_MAIN_CONF_P__BLOCK_PRED_ENABLE_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC0_MAIN_CONF_P__VIDEO_MODE_MASK 0x00080000U
+#define MHDP__MHDP_APB_REGS__ENC0_MAIN_CONF_P__VIDEO_MODE_SHIFT 19U
+#define MHDP__MHDP_APB_REGS__ENC0_MAIN_CONF_P__VIDEO_MODE_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC0_MAIN_CONF_P__VIDEO_MODE_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC0_MAIN_CONF_P__VIDEO_MODE_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC0_MAIN_CONF_P__ICH_RST_EOL_MASK 0x00100000U
+#define MHDP__MHDP_APB_REGS__ENC0_MAIN_CONF_P__ICH_RST_EOL_SHIFT 20U
+#define MHDP__MHDP_APB_REGS__ENC0_MAIN_CONF_P__ICH_RST_EOL_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC0_MAIN_CONF_P__ICH_RST_EOL_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC0_MAIN_CONF_P__ICH_RST_EOL_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC0_MAIN_CONF_P__RESERVED_1_MASK 0x00E00000U
+#define MHDP__MHDP_APB_REGS__ENC0_MAIN_CONF_P__RESERVED_1_SHIFT 21U
+#define MHDP__MHDP_APB_REGS__ENC0_MAIN_CONF_P__RESERVED_1_WIDTH 3U
+#define MHDP__MHDP_APB_REGS__ENC0_MAIN_CONF_P__INITIAL_LINES_MASK 0xFF000000U
+#define MHDP__MHDP_APB_REGS__ENC0_MAIN_CONF_P__INITIAL_LINES_SHIFT 24U
+#define MHDP__MHDP_APB_REGS__ENC0_MAIN_CONF_P__INITIAL_LINES_WIDTH 8U
+
+#define MHDP__MHDP_APB_REGS__ENC0_PICTURE_SIZE_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC0_PICTURE_SIZE_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC0_PICTURE_SIZE_P__PICTURE_WIDTH_MASK 0x0000FFFFU
+#define MHDP__MHDP_APB_REGS__ENC0_PICTURE_SIZE_P__PICTURE_WIDTH_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__ENC0_PICTURE_SIZE_P__PICTURE_WIDTH_WIDTH 16U
+#define MHDP__MHDP_APB_REGS__ENC0_PICTURE_SIZE_P__PICTURE_HEIGHT_MASK 0xFFFF0000U
+#define MHDP__MHDP_APB_REGS__ENC0_PICTURE_SIZE_P__PICTURE_HEIGHT_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__ENC0_PICTURE_SIZE_P__PICTURE_HEIGHT_WIDTH 16U
+
+#define MHDP__MHDP_APB_REGS__ENC0_SLICE_SIZE_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC0_SLICE_SIZE_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC0_SLICE_SIZE_P__SLICE_WIDTH_MASK 0x0000FFFFU
+#define MHDP__MHDP_APB_REGS__ENC0_SLICE_SIZE_P__SLICE_WIDTH_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__ENC0_SLICE_SIZE_P__SLICE_WIDTH_WIDTH 16U
+#define MHDP__MHDP_APB_REGS__ENC0_SLICE_SIZE_P__SLICE_HEIGHT_MASK 0xFFFF0000U
+#define MHDP__MHDP_APB_REGS__ENC0_SLICE_SIZE_P__SLICE_HEIGHT_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__ENC0_SLICE_SIZE_P__SLICE_HEIGHT_WIDTH 16U
+
+#define MHDP__MHDP_APB_REGS__ENC0_MISC_SIZE_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC0_MISC_SIZE_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC0_MISC_SIZE_P__SLICE_LAST_GROUP_SIZE_MASK 0x00000003U
+#define MHDP__MHDP_APB_REGS__ENC0_MISC_SIZE_P__SLICE_LAST_GROUP_SIZE_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__ENC0_MISC_SIZE_P__SLICE_LAST_GROUP_SIZE_WIDTH 2U
+#define MHDP__MHDP_APB_REGS__ENC0_MISC_SIZE_P__OB_MAX_ADDR_MASK 0x0000FFFCU
+#define MHDP__MHDP_APB_REGS__ENC0_MISC_SIZE_P__OB_MAX_ADDR_SHIFT 2U
+#define MHDP__MHDP_APB_REGS__ENC0_MISC_SIZE_P__OB_MAX_ADDR_WIDTH 14U
+#define MHDP__MHDP_APB_REGS__ENC0_MISC_SIZE_P__CHUNK_SIZE_MASK 0xFFFF0000U
+#define MHDP__MHDP_APB_REGS__ENC0_MISC_SIZE_P__CHUNK_SIZE_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__ENC0_MISC_SIZE_P__CHUNK_SIZE_WIDTH 16U
+
+#define MHDP__MHDP_APB_REGS__ENC0_HRD_DELAYS_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC0_HRD_DELAYS_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC0_HRD_DELAYS_P__INITIAL_XMIT_DELAY_MASK 0x000003FFU
+#define MHDP__MHDP_APB_REGS__ENC0_HRD_DELAYS_P__INITIAL_XMIT_DELAY_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__ENC0_HRD_DELAYS_P__INITIAL_XMIT_DELAY_WIDTH 10U
+#define MHDP__MHDP_APB_REGS__ENC0_HRD_DELAYS_P__RESERVED_0_MASK 0x0000FC00U
+#define MHDP__MHDP_APB_REGS__ENC0_HRD_DELAYS_P__RESERVED_0_SHIFT 10U
+#define MHDP__MHDP_APB_REGS__ENC0_HRD_DELAYS_P__RESERVED_0_WIDTH 6U
+#define MHDP__MHDP_APB_REGS__ENC0_HRD_DELAYS_P__INITIAL_DEC_DELAY_MASK 0xFFFF0000U
+#define MHDP__MHDP_APB_REGS__ENC0_HRD_DELAYS_P__INITIAL_DEC_DELAY_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__ENC0_HRD_DELAYS_P__INITIAL_DEC_DELAY_WIDTH 16U
+
+#define MHDP__MHDP_APB_REGS__ENC0_RC_SCALE_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC0_RC_SCALE_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC0_RC_SCALE_P__INITIAL_SCALE_VALUE_MASK 0x0000003FU
+#define MHDP__MHDP_APB_REGS__ENC0_RC_SCALE_P__INITIAL_SCALE_VALUE_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_SCALE_P__INITIAL_SCALE_VALUE_WIDTH 6U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_SCALE_P__RESERVED_0_MASK 0xFFFFFFC0U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_SCALE_P__RESERVED_0_SHIFT 6U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_SCALE_P__RESERVED_0_WIDTH 26U
+
+#define MHDP__MHDP_APB_REGS__ENC0_RC_SCALE_INC_DEC_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC0_RC_SCALE_INC_DEC_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC0_RC_SCALE_INC_DEC_P__SCALE_INCREMENT_INTERVAL_MASK 0x0000FFFFU
+#define MHDP__MHDP_APB_REGS__ENC0_RC_SCALE_INC_DEC_P__SCALE_INCREMENT_INTERVAL_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_SCALE_INC_DEC_P__SCALE_INCREMENT_INTERVAL_WIDTH 16U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_SCALE_INC_DEC_P__SCALE_DECREMENT_INTERVAL_MASK 0x0FFF0000U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_SCALE_INC_DEC_P__SCALE_DECREMENT_INTERVAL_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_SCALE_INC_DEC_P__SCALE_DECREMENT_INTERVAL_WIDTH 12U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_SCALE_INC_DEC_P__RESERVED_0_MASK 0xF0000000U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_SCALE_INC_DEC_P__RESERVED_0_SHIFT 28U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_SCALE_INC_DEC_P__RESERVED_0_WIDTH 4U
+
+#define MHDP__MHDP_APB_REGS__ENC0_RC_OFFSETS_1_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC0_RC_OFFSETS_1_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC0_RC_OFFSETS_1_P__FIRST_LINE_BPG_OFFSET_MASK 0x0000001FU
+#define MHDP__MHDP_APB_REGS__ENC0_RC_OFFSETS_1_P__FIRST_LINE_BPG_OFFSET_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_OFFSETS_1_P__FIRST_LINE_BPG_OFFSET_WIDTH 5U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_OFFSETS_1_P__RESERVED_0_MASK 0xFFFFFFE0U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_OFFSETS_1_P__RESERVED_0_SHIFT 5U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_OFFSETS_1_P__RESERVED_0_WIDTH 27U
+
+#define MHDP__MHDP_APB_REGS__ENC0_RC_OFFSETS_2_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC0_RC_OFFSETS_2_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC0_RC_OFFSETS_2_P__NFL_BPG_OFFSET_MASK 0x0000FFFFU
+#define MHDP__MHDP_APB_REGS__ENC0_RC_OFFSETS_2_P__NFL_BPG_OFFSET_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_OFFSETS_2_P__NFL_BPG_OFFSET_WIDTH 16U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_OFFSETS_2_P__SLICE_BPG_OFFSET_MASK 0xFFFF0000U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_OFFSETS_2_P__SLICE_BPG_OFFSET_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_OFFSETS_2_P__SLICE_BPG_OFFSET_WIDTH 16U
+
+#define MHDP__MHDP_APB_REGS__ENC0_RC_OFFSETS_3_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC0_RC_OFFSETS_3_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC0_RC_OFFSETS_3_P__INITIAL_OFFSET_MASK 0x0000FFFFU
+#define MHDP__MHDP_APB_REGS__ENC0_RC_OFFSETS_3_P__INITIAL_OFFSET_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_OFFSETS_3_P__INITIAL_OFFSET_WIDTH 16U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_OFFSETS_3_P__FINAL_OFFSET_MASK 0xFFFF0000U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_OFFSETS_3_P__FINAL_OFFSET_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_OFFSETS_3_P__FINAL_OFFSET_WIDTH 16U
+
+#define MHDP__MHDP_APB_REGS__ENC0_FLATNESS_DETECTION_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC0_FLATNESS_DETECTION_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC0_FLATNESS_DETECTION_P__FLATNESS_MIN_QP_MASK 0x0000001FU
+#define MHDP__MHDP_APB_REGS__ENC0_FLATNESS_DETECTION_P__FLATNESS_MIN_QP_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__ENC0_FLATNESS_DETECTION_P__FLATNESS_MIN_QP_WIDTH 5U
+#define MHDP__MHDP_APB_REGS__ENC0_FLATNESS_DETECTION_P__FLATNESS_MAX_QP_MASK 0x000003E0U
+#define MHDP__MHDP_APB_REGS__ENC0_FLATNESS_DETECTION_P__FLATNESS_MAX_QP_SHIFT 5U
+#define MHDP__MHDP_APB_REGS__ENC0_FLATNESS_DETECTION_P__FLATNESS_MAX_QP_WIDTH 5U
+#define MHDP__MHDP_APB_REGS__ENC0_FLATNESS_DETECTION_P__FLATNESS_DET_THRESH_MASK 0x0003FC00U
+#define MHDP__MHDP_APB_REGS__ENC0_FLATNESS_DETECTION_P__FLATNESS_DET_THRESH_SHIFT 10U
+#define MHDP__MHDP_APB_REGS__ENC0_FLATNESS_DETECTION_P__FLATNESS_DET_THRESH_WIDTH 8U
+#define MHDP__MHDP_APB_REGS__ENC0_FLATNESS_DETECTION_P__RESERVED_0_MASK 0xFFFC0000U
+#define MHDP__MHDP_APB_REGS__ENC0_FLATNESS_DETECTION_P__RESERVED_0_SHIFT 18U
+#define MHDP__MHDP_APB_REGS__ENC0_FLATNESS_DETECTION_P__RESERVED_0_WIDTH 14U
+
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MODEL_SIZE_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MODEL_SIZE_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MODEL_SIZE_P__RC_MODEL_SIZE_MASK 0x0000FFFFU
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MODEL_SIZE_P__RC_MODEL_SIZE_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MODEL_SIZE_P__RC_MODEL_SIZE_WIDTH 16U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MODEL_SIZE_P__RESERVED_0_MASK 0xFFFF0000U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MODEL_SIZE_P__RESERVED_0_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MODEL_SIZE_P__RESERVED_0_WIDTH 16U
+
+#define MHDP__MHDP_APB_REGS__ENC0_RC_CONFIG_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC0_RC_CONFIG_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC0_RC_CONFIG_P__RC_EDGE_FACTOR_MASK 0x0000000FU
+#define MHDP__MHDP_APB_REGS__ENC0_RC_CONFIG_P__RC_EDGE_FACTOR_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_CONFIG_P__RC_EDGE_FACTOR_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_CONFIG_P__RESERVED_0_MASK 0x000000F0U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_CONFIG_P__RESERVED_0_SHIFT 4U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_CONFIG_P__RESERVED_0_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_CONFIG_P__RC_QUANT_INCR_LIMIT0_MASK 0x00001F00U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_CONFIG_P__RC_QUANT_INCR_LIMIT0_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_CONFIG_P__RC_QUANT_INCR_LIMIT0_WIDTH 5U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_CONFIG_P__RC_QUANT_INCR_LIMIT1_MASK 0x0003E000U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_CONFIG_P__RC_QUANT_INCR_LIMIT1_SHIFT 13U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_CONFIG_P__RC_QUANT_INCR_LIMIT1_WIDTH 5U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_CONFIG_P__RESERVED_1_MASK 0x000C0000U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_CONFIG_P__RESERVED_1_SHIFT 18U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_CONFIG_P__RESERVED_1_WIDTH 2U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_CONFIG_P__RC_TGT_OFFSET_HI_MASK 0x00F00000U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_CONFIG_P__RC_TGT_OFFSET_HI_SHIFT 20U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_CONFIG_P__RC_TGT_OFFSET_HI_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_CONFIG_P__RC_TGT_OFFSET_LO_MASK 0x0F000000U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_CONFIG_P__RC_TGT_OFFSET_LO_SHIFT 24U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_CONFIG_P__RC_TGT_OFFSET_LO_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_CONFIG_P__RESERVED_2_MASK 0xF0000000U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_CONFIG_P__RESERVED_2_SHIFT 28U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_CONFIG_P__RESERVED_2_WIDTH 4U
+
+#define MHDP__MHDP_APB_REGS__ENC0_RC_BUF_THRESH_0_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC0_RC_BUF_THRESH_0_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC0_RC_BUF_THRESH_0_P__RC_BUF_THRESH_0_MASK 0x000000FFU
+#define MHDP__MHDP_APB_REGS__ENC0_RC_BUF_THRESH_0_P__RC_BUF_THRESH_0_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_BUF_THRESH_0_P__RC_BUF_THRESH_0_WIDTH 8U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_BUF_THRESH_0_P__RC_BUF_THRESH_1_MASK 0x0000FF00U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_BUF_THRESH_0_P__RC_BUF_THRESH_1_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_BUF_THRESH_0_P__RC_BUF_THRESH_1_WIDTH 8U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_BUF_THRESH_0_P__RC_BUF_THRESH_2_MASK 0x00FF0000U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_BUF_THRESH_0_P__RC_BUF_THRESH_2_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_BUF_THRESH_0_P__RC_BUF_THRESH_2_WIDTH 8U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_BUF_THRESH_0_P__RC_BUF_THRESH_3_MASK 0xFF000000U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_BUF_THRESH_0_P__RC_BUF_THRESH_3_SHIFT 24U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_BUF_THRESH_0_P__RC_BUF_THRESH_3_WIDTH 8U
+
+#define MHDP__MHDP_APB_REGS__ENC0_RC_BUF_THRESH_1_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC0_RC_BUF_THRESH_1_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC0_RC_BUF_THRESH_1_P__RC_BUF_THRESH_4_MASK 0x000000FFU
+#define MHDP__MHDP_APB_REGS__ENC0_RC_BUF_THRESH_1_P__RC_BUF_THRESH_4_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_BUF_THRESH_1_P__RC_BUF_THRESH_4_WIDTH 8U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_BUF_THRESH_1_P__RC_BUF_THRESH_5_MASK 0x0000FF00U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_BUF_THRESH_1_P__RC_BUF_THRESH_5_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_BUF_THRESH_1_P__RC_BUF_THRESH_5_WIDTH 8U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_BUF_THRESH_1_P__RC_BUF_THRESH_6_MASK 0x00FF0000U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_BUF_THRESH_1_P__RC_BUF_THRESH_6_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_BUF_THRESH_1_P__RC_BUF_THRESH_6_WIDTH 8U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_BUF_THRESH_1_P__RC_BUF_THRESH_7_MASK 0xFF000000U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_BUF_THRESH_1_P__RC_BUF_THRESH_7_SHIFT 24U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_BUF_THRESH_1_P__RC_BUF_THRESH_7_WIDTH 8U
+
+#define MHDP__MHDP_APB_REGS__ENC0_RC_BUF_THRESH_2_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC0_RC_BUF_THRESH_2_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC0_RC_BUF_THRESH_2_P__RC_BUF_THRESH_8_MASK 0x000000FFU
+#define MHDP__MHDP_APB_REGS__ENC0_RC_BUF_THRESH_2_P__RC_BUF_THRESH_8_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_BUF_THRESH_2_P__RC_BUF_THRESH_8_WIDTH 8U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_BUF_THRESH_2_P__RC_BUF_THRESH_9_MASK 0x0000FF00U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_BUF_THRESH_2_P__RC_BUF_THRESH_9_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_BUF_THRESH_2_P__RC_BUF_THRESH_9_WIDTH 8U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_BUF_THRESH_2_P__RC_BUF_THRESH_10_MASK 0x00FF0000U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_BUF_THRESH_2_P__RC_BUF_THRESH_10_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_BUF_THRESH_2_P__RC_BUF_THRESH_10_WIDTH 8U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_BUF_THRESH_2_P__RC_BUF_THRESH_11_MASK 0xFF000000U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_BUF_THRESH_2_P__RC_BUF_THRESH_11_SHIFT 24U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_BUF_THRESH_2_P__RC_BUF_THRESH_11_WIDTH 8U
+
+#define MHDP__MHDP_APB_REGS__ENC0_RC_BUF_THRESH_3_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC0_RC_BUF_THRESH_3_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC0_RC_BUF_THRESH_3_P__RC_BUF_THRESH_12_MASK 0x000000FFU
+#define MHDP__MHDP_APB_REGS__ENC0_RC_BUF_THRESH_3_P__RC_BUF_THRESH_12_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_BUF_THRESH_3_P__RC_BUF_THRESH_12_WIDTH 8U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_BUF_THRESH_3_P__RC_BUF_THRESH_13_MASK 0x0000FF00U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_BUF_THRESH_3_P__RC_BUF_THRESH_13_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_BUF_THRESH_3_P__RC_BUF_THRESH_13_WIDTH 8U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_BUF_THRESH_3_P__RESERVED_0_MASK 0xFFFF0000U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_BUF_THRESH_3_P__RESERVED_0_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_BUF_THRESH_3_P__RESERVED_0_WIDTH 16U
+
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MIN_QP_0_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MIN_QP_0_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MIN_QP_0_P__RANGE_MIN_QP_0_MASK 0x0000001FU
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MIN_QP_0_P__RANGE_MIN_QP_0_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MIN_QP_0_P__RANGE_MIN_QP_0_WIDTH 5U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MIN_QP_0_P__RANGE_MIN_QP_1_MASK 0x000003E0U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MIN_QP_0_P__RANGE_MIN_QP_1_SHIFT 5U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MIN_QP_0_P__RANGE_MIN_QP_1_WIDTH 5U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MIN_QP_0_P__RANGE_MIN_QP_2_MASK 0x00007C00U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MIN_QP_0_P__RANGE_MIN_QP_2_SHIFT 10U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MIN_QP_0_P__RANGE_MIN_QP_2_WIDTH 5U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MIN_QP_0_P__RANGE_MIN_QP_3_MASK 0x000F8000U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MIN_QP_0_P__RANGE_MIN_QP_3_SHIFT 15U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MIN_QP_0_P__RANGE_MIN_QP_3_WIDTH 5U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MIN_QP_0_P__RANGE_MIN_QP_4_MASK 0x01F00000U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MIN_QP_0_P__RANGE_MIN_QP_4_SHIFT 20U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MIN_QP_0_P__RANGE_MIN_QP_4_WIDTH 5U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MIN_QP_0_P__RESERVED_0_MASK 0xFE000000U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MIN_QP_0_P__RESERVED_0_SHIFT 25U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MIN_QP_0_P__RESERVED_0_WIDTH 7U
+
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MIN_QP_1_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MIN_QP_1_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MIN_QP_1_P__RANGE_MIN_QP_5_MASK 0x0000001FU
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MIN_QP_1_P__RANGE_MIN_QP_5_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MIN_QP_1_P__RANGE_MIN_QP_5_WIDTH 5U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MIN_QP_1_P__RANGE_MIN_QP_6_MASK 0x000003E0U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MIN_QP_1_P__RANGE_MIN_QP_6_SHIFT 5U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MIN_QP_1_P__RANGE_MIN_QP_6_WIDTH 5U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MIN_QP_1_P__RANGE_MIN_QP_7_MASK 0x00007C00U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MIN_QP_1_P__RANGE_MIN_QP_7_SHIFT 10U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MIN_QP_1_P__RANGE_MIN_QP_7_WIDTH 5U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MIN_QP_1_P__RANGE_MIN_QP_8_MASK 0x000F8000U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MIN_QP_1_P__RANGE_MIN_QP_8_SHIFT 15U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MIN_QP_1_P__RANGE_MIN_QP_8_WIDTH 5U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MIN_QP_1_P__RANGE_MIN_QP_9_MASK 0x01F00000U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MIN_QP_1_P__RANGE_MIN_QP_9_SHIFT 20U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MIN_QP_1_P__RANGE_MIN_QP_9_WIDTH 5U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MIN_QP_1_P__RESERVED_0_MASK 0xFE000000U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MIN_QP_1_P__RESERVED_0_SHIFT 25U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MIN_QP_1_P__RESERVED_0_WIDTH 7U
+
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MIN_QP_2_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MIN_QP_2_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MIN_QP_2_P__RANGE_MIN_QP_10_MASK 0x0000001FU
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MIN_QP_2_P__RANGE_MIN_QP_10_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MIN_QP_2_P__RANGE_MIN_QP_10_WIDTH 5U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MIN_QP_2_P__RANGE_MIN_QP_11_MASK 0x000003E0U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MIN_QP_2_P__RANGE_MIN_QP_11_SHIFT 5U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MIN_QP_2_P__RANGE_MIN_QP_11_WIDTH 5U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MIN_QP_2_P__RANGE_MIN_QP_12_MASK 0x00007C00U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MIN_QP_2_P__RANGE_MIN_QP_12_SHIFT 10U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MIN_QP_2_P__RANGE_MIN_QP_12_WIDTH 5U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MIN_QP_2_P__RANGE_MIN_QP_13_MASK 0x000F8000U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MIN_QP_2_P__RANGE_MIN_QP_13_SHIFT 15U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MIN_QP_2_P__RANGE_MIN_QP_13_WIDTH 5U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MIN_QP_2_P__RANGE_MIN_QP_14_MASK 0x01F00000U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MIN_QP_2_P__RANGE_MIN_QP_14_SHIFT 20U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MIN_QP_2_P__RANGE_MIN_QP_14_WIDTH 5U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MIN_QP_2_P__RESERVED_0_MASK 0xFE000000U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MIN_QP_2_P__RESERVED_0_SHIFT 25U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MIN_QP_2_P__RESERVED_0_WIDTH 7U
+
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MAX_QP_0_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MAX_QP_0_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MAX_QP_0_P__RANGE_MAX_QP_0_MASK 0x0000001FU
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MAX_QP_0_P__RANGE_MAX_QP_0_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MAX_QP_0_P__RANGE_MAX_QP_0_WIDTH 5U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MAX_QP_0_P__RANGE_MAX_QP_1_MASK 0x000003E0U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MAX_QP_0_P__RANGE_MAX_QP_1_SHIFT 5U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MAX_QP_0_P__RANGE_MAX_QP_1_WIDTH 5U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MAX_QP_0_P__RANGE_MAX_QP_2_MASK 0x00007C00U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MAX_QP_0_P__RANGE_MAX_QP_2_SHIFT 10U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MAX_QP_0_P__RANGE_MAX_QP_2_WIDTH 5U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MAX_QP_0_P__RANGE_MAX_QP_3_MASK 0x000F8000U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MAX_QP_0_P__RANGE_MAX_QP_3_SHIFT 15U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MAX_QP_0_P__RANGE_MAX_QP_3_WIDTH 5U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MAX_QP_0_P__RANGE_MAX_QP_4_MASK 0x01F00000U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MAX_QP_0_P__RANGE_MAX_QP_4_SHIFT 20U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MAX_QP_0_P__RANGE_MAX_QP_4_WIDTH 5U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MAX_QP_0_P__RESERVED_0_MASK 0xFE000000U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MAX_QP_0_P__RESERVED_0_SHIFT 25U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MAX_QP_0_P__RESERVED_0_WIDTH 7U
+
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MAX_QP_1_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MAX_QP_1_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MAX_QP_1_P__RANGE_MAX_QP_5_MASK 0x0000001FU
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MAX_QP_1_P__RANGE_MAX_QP_5_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MAX_QP_1_P__RANGE_MAX_QP_5_WIDTH 5U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MAX_QP_1_P__RANGE_MAX_QP_6_MASK 0x000003E0U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MAX_QP_1_P__RANGE_MAX_QP_6_SHIFT 5U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MAX_QP_1_P__RANGE_MAX_QP_6_WIDTH 5U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MAX_QP_1_P__RANGE_MAX_QP_7_MASK 0x00007C00U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MAX_QP_1_P__RANGE_MAX_QP_7_SHIFT 10U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MAX_QP_1_P__RANGE_MAX_QP_7_WIDTH 5U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MAX_QP_1_P__RANGE_MAX_QP_8_MASK 0x000F8000U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MAX_QP_1_P__RANGE_MAX_QP_8_SHIFT 15U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MAX_QP_1_P__RANGE_MAX_QP_8_WIDTH 5U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MAX_QP_1_P__RANGE_MAX_QP_9_MASK 0x01F00000U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MAX_QP_1_P__RANGE_MAX_QP_9_SHIFT 20U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MAX_QP_1_P__RANGE_MAX_QP_9_WIDTH 5U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MAX_QP_1_P__RESERVED_0_MASK 0xFE000000U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MAX_QP_1_P__RESERVED_0_SHIFT 25U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MAX_QP_1_P__RESERVED_0_WIDTH 7U
+
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MAX_QP_2_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MAX_QP_2_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MAX_QP_2_P__RANGE_MAX_QP_10_MASK 0x0000001FU
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MAX_QP_2_P__RANGE_MAX_QP_10_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MAX_QP_2_P__RANGE_MAX_QP_10_WIDTH 5U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MAX_QP_2_P__RANGE_MAX_QP_11_MASK 0x000003E0U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MAX_QP_2_P__RANGE_MAX_QP_11_SHIFT 5U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MAX_QP_2_P__RANGE_MAX_QP_11_WIDTH 5U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MAX_QP_2_P__RANGE_MAX_QP_12_MASK 0x00007C00U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MAX_QP_2_P__RANGE_MAX_QP_12_SHIFT 10U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MAX_QP_2_P__RANGE_MAX_QP_12_WIDTH 5U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MAX_QP_2_P__RANGE_MAX_QP_13_MASK 0x000F8000U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MAX_QP_2_P__RANGE_MAX_QP_13_SHIFT 15U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MAX_QP_2_P__RANGE_MAX_QP_13_WIDTH 5U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MAX_QP_2_P__RANGE_MAX_QP_14_MASK 0x01F00000U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MAX_QP_2_P__RANGE_MAX_QP_14_SHIFT 20U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MAX_QP_2_P__RANGE_MAX_QP_14_WIDTH 5U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MAX_QP_2_P__RESERVED_0_MASK 0xFE000000U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MAX_QP_2_P__RESERVED_0_SHIFT 25U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_MAX_QP_2_P__RESERVED_0_WIDTH 7U
+
+#define MHDP__MHDP_APB_REGS__ENC0_RC_RANGE_BPG_OFFSETS_0_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC0_RC_RANGE_BPG_OFFSETS_0_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC0_RC_RANGE_BPG_OFFSETS_0_P__RANGE_BPG_OFFSET_0_MASK 0x0000003FU
+#define MHDP__MHDP_APB_REGS__ENC0_RC_RANGE_BPG_OFFSETS_0_P__RANGE_BPG_OFFSET_0_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_RANGE_BPG_OFFSETS_0_P__RANGE_BPG_OFFSET_0_WIDTH 6U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_RANGE_BPG_OFFSETS_0_P__RANGE_BPG_OFFSET_1_MASK 0x00000FC0U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_RANGE_BPG_OFFSETS_0_P__RANGE_BPG_OFFSET_1_SHIFT 6U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_RANGE_BPG_OFFSETS_0_P__RANGE_BPG_OFFSET_1_WIDTH 6U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_RANGE_BPG_OFFSETS_0_P__RANGE_BPG_OFFSET_2_MASK 0x0003F000U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_RANGE_BPG_OFFSETS_0_P__RANGE_BPG_OFFSET_2_SHIFT 12U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_RANGE_BPG_OFFSETS_0_P__RANGE_BPG_OFFSET_2_WIDTH 6U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_RANGE_BPG_OFFSETS_0_P__RANGE_BPG_OFFSET_3_MASK 0x00FC0000U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_RANGE_BPG_OFFSETS_0_P__RANGE_BPG_OFFSET_3_SHIFT 18U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_RANGE_BPG_OFFSETS_0_P__RANGE_BPG_OFFSET_3_WIDTH 6U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_RANGE_BPG_OFFSETS_0_P__RANGE_BPG_OFFSET_4_MASK 0x3F000000U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_RANGE_BPG_OFFSETS_0_P__RANGE_BPG_OFFSET_4_SHIFT 24U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_RANGE_BPG_OFFSETS_0_P__RANGE_BPG_OFFSET_4_WIDTH 6U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_RANGE_BPG_OFFSETS_0_P__RESERVED_0_MASK 0xC0000000U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_RANGE_BPG_OFFSETS_0_P__RESERVED_0_SHIFT 30U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_RANGE_BPG_OFFSETS_0_P__RESERVED_0_WIDTH 2U
+
+#define MHDP__MHDP_APB_REGS__ENC0_RC_RANGE_BPG_OFFSETS_1_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC0_RC_RANGE_BPG_OFFSETS_1_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC0_RC_RANGE_BPG_OFFSETS_1_P__RANGE_BPG_OFFSET_5_MASK 0x0000003FU
+#define MHDP__MHDP_APB_REGS__ENC0_RC_RANGE_BPG_OFFSETS_1_P__RANGE_BPG_OFFSET_5_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_RANGE_BPG_OFFSETS_1_P__RANGE_BPG_OFFSET_5_WIDTH 6U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_RANGE_BPG_OFFSETS_1_P__RANGE_BPG_OFFSET_6_MASK 0x00000FC0U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_RANGE_BPG_OFFSETS_1_P__RANGE_BPG_OFFSET_6_SHIFT 6U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_RANGE_BPG_OFFSETS_1_P__RANGE_BPG_OFFSET_6_WIDTH 6U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_RANGE_BPG_OFFSETS_1_P__RANGE_BPG_OFFSET_7_MASK 0x0003F000U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_RANGE_BPG_OFFSETS_1_P__RANGE_BPG_OFFSET_7_SHIFT 12U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_RANGE_BPG_OFFSETS_1_P__RANGE_BPG_OFFSET_7_WIDTH 6U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_RANGE_BPG_OFFSETS_1_P__RANGE_BPG_OFFSET_8_MASK 0x00FC0000U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_RANGE_BPG_OFFSETS_1_P__RANGE_BPG_OFFSET_8_SHIFT 18U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_RANGE_BPG_OFFSETS_1_P__RANGE_BPG_OFFSET_8_WIDTH 6U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_RANGE_BPG_OFFSETS_1_P__RANGE_BPG_OFFSET_9_MASK 0x3F000000U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_RANGE_BPG_OFFSETS_1_P__RANGE_BPG_OFFSET_9_SHIFT 24U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_RANGE_BPG_OFFSETS_1_P__RANGE_BPG_OFFSET_9_WIDTH 6U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_RANGE_BPG_OFFSETS_1_P__RESERVED_0_MASK 0xC0000000U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_RANGE_BPG_OFFSETS_1_P__RESERVED_0_SHIFT 30U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_RANGE_BPG_OFFSETS_1_P__RESERVED_0_WIDTH 2U
+
+#define MHDP__MHDP_APB_REGS__ENC0_RC_RANGE_BPG_OFFSETS_2_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC0_RC_RANGE_BPG_OFFSETS_2_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC0_RC_RANGE_BPG_OFFSETS_2_P__RANGE_BPG_OFFSET_10_MASK 0x0000003FU
+#define MHDP__MHDP_APB_REGS__ENC0_RC_RANGE_BPG_OFFSETS_2_P__RANGE_BPG_OFFSET_10_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_RANGE_BPG_OFFSETS_2_P__RANGE_BPG_OFFSET_10_WIDTH 6U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_RANGE_BPG_OFFSETS_2_P__RANGE_BPG_OFFSET_11_MASK 0x00000FC0U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_RANGE_BPG_OFFSETS_2_P__RANGE_BPG_OFFSET_11_SHIFT 6U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_RANGE_BPG_OFFSETS_2_P__RANGE_BPG_OFFSET_11_WIDTH 6U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_RANGE_BPG_OFFSETS_2_P__RANGE_BPG_OFFSET_12_MASK 0x0003F000U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_RANGE_BPG_OFFSETS_2_P__RANGE_BPG_OFFSET_12_SHIFT 12U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_RANGE_BPG_OFFSETS_2_P__RANGE_BPG_OFFSET_12_WIDTH 6U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_RANGE_BPG_OFFSETS_2_P__RANGE_BPG_OFFSET_13_MASK 0x00FC0000U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_RANGE_BPG_OFFSETS_2_P__RANGE_BPG_OFFSET_13_SHIFT 18U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_RANGE_BPG_OFFSETS_2_P__RANGE_BPG_OFFSET_13_WIDTH 6U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_RANGE_BPG_OFFSETS_2_P__RANGE_BPG_OFFSET_14_MASK 0x3F000000U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_RANGE_BPG_OFFSETS_2_P__RANGE_BPG_OFFSET_14_SHIFT 24U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_RANGE_BPG_OFFSETS_2_P__RANGE_BPG_OFFSET_14_WIDTH 6U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_RANGE_BPG_OFFSETS_2_P__RESERVED_0_MASK 0xC0000000U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_RANGE_BPG_OFFSETS_2_P__RESERVED_0_SHIFT 30U
+#define MHDP__MHDP_APB_REGS__ENC0_RC_RANGE_BPG_OFFSETS_2_P__RESERVED_0_WIDTH 2U
+
+#define MHDP__MHDP_APB_REGS__ENC0_DPI_CTRL_OUT_DELAY_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC0_DPI_CTRL_OUT_DELAY_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC0_DPI_CTRL_OUT_DELAY_P__DPI_CTRL_OUT_DELAY_MASK 0x0000FFFFU
+#define MHDP__MHDP_APB_REGS__ENC0_DPI_CTRL_OUT_DELAY_P__DPI_CTRL_OUT_DELAY_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__ENC0_DPI_CTRL_OUT_DELAY_P__DPI_CTRL_OUT_DELAY_WIDTH 16U
+#define MHDP__MHDP_APB_REGS__ENC0_DPI_CTRL_OUT_DELAY_P__RESERVED_0_MASK 0xFFFF0000U
+#define MHDP__MHDP_APB_REGS__ENC0_DPI_CTRL_OUT_DELAY_P__RESERVED_0_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__ENC0_DPI_CTRL_OUT_DELAY_P__RESERVED_0_WIDTH 16U
+
+#define MHDP__MHDP_APB_REGS__ENC0_GENERAL_STATUS_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC0_GENERAL_STATUS_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC0_GENERAL_STATUS_P__CE_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__ENC0_GENERAL_STATUS_P__CE_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__ENC0_GENERAL_STATUS_P__CE_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC0_GENERAL_STATUS_P__CE_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC0_GENERAL_STATUS_P__CE_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC0_GENERAL_STATUS_P__FRAME_STARTED_MASK 0x00000002U
+#define MHDP__MHDP_APB_REGS__ENC0_GENERAL_STATUS_P__FRAME_STARTED_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__ENC0_GENERAL_STATUS_P__FRAME_STARTED_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC0_GENERAL_STATUS_P__FRAME_STARTED_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC0_GENERAL_STATUS_P__FRAME_STARTED_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC0_GENERAL_STATUS_P__FRAME_DONE_MASK 0x00000004U
+#define MHDP__MHDP_APB_REGS__ENC0_GENERAL_STATUS_P__FRAME_DONE_SHIFT 2U
+#define MHDP__MHDP_APB_REGS__ENC0_GENERAL_STATUS_P__FRAME_DONE_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC0_GENERAL_STATUS_P__FRAME_DONE_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC0_GENERAL_STATUS_P__FRAME_DONE_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC0_GENERAL_STATUS_P__OUT_BUFF_EMPTY_CONTEXT_0_MASK 0x00000008U
+#define MHDP__MHDP_APB_REGS__ENC0_GENERAL_STATUS_P__OUT_BUFF_EMPTY_CONTEXT_0_SHIFT 3U
+#define MHDP__MHDP_APB_REGS__ENC0_GENERAL_STATUS_P__OUT_BUFF_EMPTY_CONTEXT_0_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC0_GENERAL_STATUS_P__OUT_BUFF_EMPTY_CONTEXT_0_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC0_GENERAL_STATUS_P__OUT_BUFF_EMPTY_CONTEXT_0_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC0_GENERAL_STATUS_P__OUT_BUFF_EMPTY_CONTEXT_1_MASK 0x00000010U
+#define MHDP__MHDP_APB_REGS__ENC0_GENERAL_STATUS_P__OUT_BUFF_EMPTY_CONTEXT_1_SHIFT 4U
+#define MHDP__MHDP_APB_REGS__ENC0_GENERAL_STATUS_P__OUT_BUFF_EMPTY_CONTEXT_1_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC0_GENERAL_STATUS_P__OUT_BUFF_EMPTY_CONTEXT_1_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC0_GENERAL_STATUS_P__OUT_BUFF_EMPTY_CONTEXT_1_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC0_GENERAL_STATUS_P__OUT_BUFF_FULL_CONTEXT_0_MASK 0x00000020U
+#define MHDP__MHDP_APB_REGS__ENC0_GENERAL_STATUS_P__OUT_BUFF_FULL_CONTEXT_0_SHIFT 5U
+#define MHDP__MHDP_APB_REGS__ENC0_GENERAL_STATUS_P__OUT_BUFF_FULL_CONTEXT_0_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC0_GENERAL_STATUS_P__OUT_BUFF_FULL_CONTEXT_0_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC0_GENERAL_STATUS_P__OUT_BUFF_FULL_CONTEXT_0_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC0_GENERAL_STATUS_P__OUT_BUFF_FULL_CONTEXT_1_MASK 0x00000040U
+#define MHDP__MHDP_APB_REGS__ENC0_GENERAL_STATUS_P__OUT_BUFF_FULL_CONTEXT_1_SHIFT 6U
+#define MHDP__MHDP_APB_REGS__ENC0_GENERAL_STATUS_P__OUT_BUFF_FULL_CONTEXT_1_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC0_GENERAL_STATUS_P__OUT_BUFF_FULL_CONTEXT_1_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC0_GENERAL_STATUS_P__OUT_BUFF_FULL_CONTEXT_1_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC0_GENERAL_STATUS_P__RESERVED_0_MASK 0xFFFFFF80U
+#define MHDP__MHDP_APB_REGS__ENC0_GENERAL_STATUS_P__RESERVED_0_SHIFT 7U
+#define MHDP__MHDP_APB_REGS__ENC0_GENERAL_STATUS_P__RESERVED_0_WIDTH 25U
+
+#define MHDP__MHDP_APB_REGS__ENC0_HSLICE_STATUS_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC0_HSLICE_STATUS_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC0_HSLICE_STATUS_P__SLICE_LINE_COUNT_ENCODED_MASK 0x0000FFFFU
+#define MHDP__MHDP_APB_REGS__ENC0_HSLICE_STATUS_P__SLICE_LINE_COUNT_ENCODED_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__ENC0_HSLICE_STATUS_P__SLICE_LINE_COUNT_ENCODED_WIDTH 16U
+#define MHDP__MHDP_APB_REGS__ENC0_HSLICE_STATUS_P__SLICE_COUNT_ENCODED_MASK 0xFFFF0000U
+#define MHDP__MHDP_APB_REGS__ENC0_HSLICE_STATUS_P__SLICE_COUNT_ENCODED_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__ENC0_HSLICE_STATUS_P__SLICE_COUNT_ENCODED_WIDTH 16U
+
+#define MHDP__MHDP_APB_REGS__ENC0_OUT_STATUS_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC0_OUT_STATUS_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC0_OUT_STATUS_P__SLICE_LINE_COUNT_OUT_MASK 0x0000FFFFU
+#define MHDP__MHDP_APB_REGS__ENC0_OUT_STATUS_P__SLICE_LINE_COUNT_OUT_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__ENC0_OUT_STATUS_P__SLICE_LINE_COUNT_OUT_WIDTH 16U
+#define MHDP__MHDP_APB_REGS__ENC0_OUT_STATUS_P__SLICE_COUNT_OUT_MASK 0xFFFF0000U
+#define MHDP__MHDP_APB_REGS__ENC0_OUT_STATUS_P__SLICE_COUNT_OUT_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__ENC0_OUT_STATUS_P__SLICE_COUNT_OUT_WIDTH 16U
+
+#define MHDP__MHDP_APB_REGS__ENC0_INT_STAT_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC0_INT_STAT_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC0_INT_STAT_P__ENC_UNDERFLOW_CONTEXT_0_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_STAT_P__ENC_UNDERFLOW_CONTEXT_0_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_STAT_P__ENC_UNDERFLOW_CONTEXT_0_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_STAT_P__ENC_UNDERFLOW_CONTEXT_0_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_STAT_P__ENC_UNDERFLOW_CONTEXT_0_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_STAT_P__ENC_UNDERFLOW_CONTEXT_1_MASK 0x00000002U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_STAT_P__ENC_UNDERFLOW_CONTEXT_1_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_STAT_P__ENC_UNDERFLOW_CONTEXT_1_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_STAT_P__ENC_UNDERFLOW_CONTEXT_1_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_STAT_P__ENC_UNDERFLOW_CONTEXT_1_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_STAT_P__RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_0_MASK 0x00000004U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_STAT_P__RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_0_SHIFT 2U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_STAT_P__RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_0_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_STAT_P__RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_0_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_STAT_P__RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_0_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_STAT_P__RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_1_MASK 0x00000008U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_STAT_P__RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_1_SHIFT 3U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_STAT_P__RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_1_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_STAT_P__RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_1_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_STAT_P__RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_1_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_STAT_P__CE_MASK 0x00000010U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_STAT_P__CE_SHIFT 4U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_STAT_P__CE_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_STAT_P__CE_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_STAT_P__CE_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_STAT_P__FRAME_STARTED_MASK 0x00000020U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_STAT_P__FRAME_STARTED_SHIFT 5U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_STAT_P__FRAME_STARTED_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_STAT_P__FRAME_STARTED_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_STAT_P__FRAME_STARTED_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_STAT_P__FRAME_DONE_MASK 0x00000040U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_STAT_P__FRAME_DONE_SHIFT 6U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_STAT_P__FRAME_DONE_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_STAT_P__FRAME_DONE_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_STAT_P__FRAME_DONE_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_STAT_P__OUT_BUFF_EMPTY_CONTEXT_0_MASK 0x00000080U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_STAT_P__OUT_BUFF_EMPTY_CONTEXT_0_SHIFT 7U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_STAT_P__OUT_BUFF_EMPTY_CONTEXT_0_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_STAT_P__OUT_BUFF_EMPTY_CONTEXT_0_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_STAT_P__OUT_BUFF_EMPTY_CONTEXT_0_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_STAT_P__OUT_BUFF_EMPTY_CONTEXT_1_MASK 0x00000100U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_STAT_P__OUT_BUFF_EMPTY_CONTEXT_1_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_STAT_P__OUT_BUFF_EMPTY_CONTEXT_1_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_STAT_P__OUT_BUFF_EMPTY_CONTEXT_1_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_STAT_P__OUT_BUFF_EMPTY_CONTEXT_1_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_STAT_P__OUT_BUFF_FULL_CONTEXT_0_MASK 0x00000200U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_STAT_P__OUT_BUFF_FULL_CONTEXT_0_SHIFT 9U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_STAT_P__OUT_BUFF_FULL_CONTEXT_0_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_STAT_P__OUT_BUFF_FULL_CONTEXT_0_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_STAT_P__OUT_BUFF_FULL_CONTEXT_0_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_STAT_P__OUT_BUFF_FULL_CONTEXT_1_MASK 0x00000400U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_STAT_P__OUT_BUFF_FULL_CONTEXT_1_SHIFT 10U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_STAT_P__OUT_BUFF_FULL_CONTEXT_1_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_STAT_P__OUT_BUFF_FULL_CONTEXT_1_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_STAT_P__OUT_BUFF_FULL_CONTEXT_1_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_STAT_P__RESERVED_0_MASK 0xFFFFF800U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_STAT_P__RESERVED_0_SHIFT 11U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_STAT_P__RESERVED_0_WIDTH 21U
+
+#define MHDP__MHDP_APB_REGS__ENC0_INT_CLR_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC0_INT_CLR_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC0_INT_CLR_P__ENC_UNDERFLOW_CONTEXT_0_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_CLR_P__ENC_UNDERFLOW_CONTEXT_0_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_CLR_P__ENC_UNDERFLOW_CONTEXT_0_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_CLR_P__ENC_UNDERFLOW_CONTEXT_0_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_CLR_P__ENC_UNDERFLOW_CONTEXT_0_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_CLR_P__ENC_UNDERFLOW_CONTEXT_1_MASK 0x00000002U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_CLR_P__ENC_UNDERFLOW_CONTEXT_1_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_CLR_P__ENC_UNDERFLOW_CONTEXT_1_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_CLR_P__ENC_UNDERFLOW_CONTEXT_1_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_CLR_P__ENC_UNDERFLOW_CONTEXT_1_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_CLR_P__RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_0_MASK 0x00000004U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_CLR_P__RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_0_SHIFT 2U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_CLR_P__RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_0_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_CLR_P__RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_0_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_CLR_P__RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_0_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_CLR_P__RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_1_MASK 0x00000008U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_CLR_P__RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_1_SHIFT 3U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_CLR_P__RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_1_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_CLR_P__RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_1_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_CLR_P__RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_1_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_CLR_P__CE_MASK 0x00000010U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_CLR_P__CE_SHIFT 4U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_CLR_P__CE_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_CLR_P__CE_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_CLR_P__CE_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_CLR_P__FRAME_STARTED_MASK 0x00000020U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_CLR_P__FRAME_STARTED_SHIFT 5U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_CLR_P__FRAME_STARTED_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_CLR_P__FRAME_STARTED_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_CLR_P__FRAME_STARTED_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_CLR_P__FRAME_DONE_MASK 0x00000040U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_CLR_P__FRAME_DONE_SHIFT 6U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_CLR_P__FRAME_DONE_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_CLR_P__FRAME_DONE_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_CLR_P__FRAME_DONE_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_CLR_P__OUT_BUFF_EMPTY_CONTEXT_0_MASK 0x00000080U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_CLR_P__OUT_BUFF_EMPTY_CONTEXT_0_SHIFT 7U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_CLR_P__OUT_BUFF_EMPTY_CONTEXT_0_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_CLR_P__OUT_BUFF_EMPTY_CONTEXT_0_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_CLR_P__OUT_BUFF_EMPTY_CONTEXT_0_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_CLR_P__OUT_BUFF_EMPTY_CONTEXT_1_MASK 0x00000100U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_CLR_P__OUT_BUFF_EMPTY_CONTEXT_1_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_CLR_P__OUT_BUFF_EMPTY_CONTEXT_1_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_CLR_P__OUT_BUFF_EMPTY_CONTEXT_1_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_CLR_P__OUT_BUFF_EMPTY_CONTEXT_1_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_CLR_P__OUT_BUFF_FULL_CONTEXT_0_MASK 0x00000200U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_CLR_P__OUT_BUFF_FULL_CONTEXT_0_SHIFT 9U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_CLR_P__OUT_BUFF_FULL_CONTEXT_0_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_CLR_P__OUT_BUFF_FULL_CONTEXT_0_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_CLR_P__OUT_BUFF_FULL_CONTEXT_0_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_CLR_P__OUT_BUFF_FULL_CONTEXT_1_MASK 0x00000400U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_CLR_P__OUT_BUFF_FULL_CONTEXT_1_SHIFT 10U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_CLR_P__OUT_BUFF_FULL_CONTEXT_1_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_CLR_P__OUT_BUFF_FULL_CONTEXT_1_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_CLR_P__OUT_BUFF_FULL_CONTEXT_1_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_CLR_P__RESERVED_0_MASK 0xFFFFF800U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_CLR_P__RESERVED_0_SHIFT 11U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_CLR_P__RESERVED_0_WIDTH 21U
+
+#define MHDP__MHDP_APB_REGS__ENC0_INT_MASK_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC0_INT_MASK_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC0_INT_MASK_P__ENC_UNDERFLOW_CONTEXT_0_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_MASK_P__ENC_UNDERFLOW_CONTEXT_0_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_MASK_P__ENC_UNDERFLOW_CONTEXT_0_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_MASK_P__ENC_UNDERFLOW_CONTEXT_0_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_MASK_P__ENC_UNDERFLOW_CONTEXT_0_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_MASK_P__ENC_UNDERFLOW_CONTEXT_1_MASK 0x00000002U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_MASK_P__ENC_UNDERFLOW_CONTEXT_1_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_MASK_P__ENC_UNDERFLOW_CONTEXT_1_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_MASK_P__ENC_UNDERFLOW_CONTEXT_1_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_MASK_P__ENC_UNDERFLOW_CONTEXT_1_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_MASK_P__RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_0_MASK 0x00000004U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_MASK_P__RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_0_SHIFT 2U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_MASK_P__RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_0_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_MASK_P__RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_0_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_MASK_P__RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_0_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_MASK_P__RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_1_MASK 0x00000008U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_MASK_P__RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_1_SHIFT 3U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_MASK_P__RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_1_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_MASK_P__RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_1_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_MASK_P__RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_1_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_MASK_P__CE_MASK 0x00000010U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_MASK_P__CE_SHIFT 4U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_MASK_P__CE_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_MASK_P__CE_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_MASK_P__CE_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_MASK_P__FRAME_STARTED_MASK 0x00000020U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_MASK_P__FRAME_STARTED_SHIFT 5U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_MASK_P__FRAME_STARTED_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_MASK_P__FRAME_STARTED_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_MASK_P__FRAME_STARTED_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_MASK_P__FRAME_DONE_MASK 0x00000040U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_MASK_P__FRAME_DONE_SHIFT 6U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_MASK_P__FRAME_DONE_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_MASK_P__FRAME_DONE_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_MASK_P__FRAME_DONE_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_MASK_P__OUT_BUFF_EMPTY_CONTEXT_0_MASK 0x00000080U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_MASK_P__OUT_BUFF_EMPTY_CONTEXT_0_SHIFT 7U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_MASK_P__OUT_BUFF_EMPTY_CONTEXT_0_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_MASK_P__OUT_BUFF_EMPTY_CONTEXT_0_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_MASK_P__OUT_BUFF_EMPTY_CONTEXT_0_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_MASK_P__OUT_BUFF_EMPTY_CONTEXT_1_MASK 0x00000100U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_MASK_P__OUT_BUFF_EMPTY_CONTEXT_1_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_MASK_P__OUT_BUFF_EMPTY_CONTEXT_1_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_MASK_P__OUT_BUFF_EMPTY_CONTEXT_1_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_MASK_P__OUT_BUFF_EMPTY_CONTEXT_1_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_MASK_P__OUT_BUFF_FULL_CONTEXT_0_MASK 0x00000200U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_MASK_P__OUT_BUFF_FULL_CONTEXT_0_SHIFT 9U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_MASK_P__OUT_BUFF_FULL_CONTEXT_0_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_MASK_P__OUT_BUFF_FULL_CONTEXT_0_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_MASK_P__OUT_BUFF_FULL_CONTEXT_0_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_MASK_P__OUT_BUFF_FULL_CONTEXT_1_MASK 0x00000400U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_MASK_P__OUT_BUFF_FULL_CONTEXT_1_SHIFT 10U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_MASK_P__OUT_BUFF_FULL_CONTEXT_1_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_MASK_P__OUT_BUFF_FULL_CONTEXT_1_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_MASK_P__OUT_BUFF_FULL_CONTEXT_1_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_MASK_P__RESERVED_0_MASK 0xFFFFF800U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_MASK_P__RESERVED_0_SHIFT 11U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_MASK_P__RESERVED_0_WIDTH 21U
+
+#define MHDP__MHDP_APB_REGS__ENC0_INT_TEST_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC0_INT_TEST_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC0_INT_TEST_P__ENC_UNDERFLOW_CONTEXT_0_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_TEST_P__ENC_UNDERFLOW_CONTEXT_0_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_TEST_P__ENC_UNDERFLOW_CONTEXT_0_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_TEST_P__ENC_UNDERFLOW_CONTEXT_0_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_TEST_P__ENC_UNDERFLOW_CONTEXT_0_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_TEST_P__ENC_UNDERFLOW_CONTEXT_1_MASK 0x00000002U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_TEST_P__ENC_UNDERFLOW_CONTEXT_1_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_TEST_P__ENC_UNDERFLOW_CONTEXT_1_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_TEST_P__ENC_UNDERFLOW_CONTEXT_1_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_TEST_P__ENC_UNDERFLOW_CONTEXT_1_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_TEST_P__RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_0_MASK 0x00000004U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_TEST_P__RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_0_SHIFT 2U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_TEST_P__RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_0_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_TEST_P__RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_0_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_TEST_P__RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_0_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_TEST_P__RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_1_MASK 0x00000008U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_TEST_P__RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_1_SHIFT 3U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_TEST_P__RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_1_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_TEST_P__RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_1_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_TEST_P__RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_1_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_TEST_P__CE_MASK 0x00000010U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_TEST_P__CE_SHIFT 4U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_TEST_P__CE_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_TEST_P__CE_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_TEST_P__CE_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_TEST_P__FRAME_STARTED_MASK 0x00000020U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_TEST_P__FRAME_STARTED_SHIFT 5U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_TEST_P__FRAME_STARTED_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_TEST_P__FRAME_STARTED_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_TEST_P__FRAME_STARTED_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_TEST_P__FRAME_DONE_MASK 0x00000040U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_TEST_P__FRAME_DONE_SHIFT 6U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_TEST_P__FRAME_DONE_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_TEST_P__FRAME_DONE_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_TEST_P__FRAME_DONE_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_TEST_P__OUT_BUFF_EMPTY_CONTEXT_0_MASK 0x00000080U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_TEST_P__OUT_BUFF_EMPTY_CONTEXT_0_SHIFT 7U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_TEST_P__OUT_BUFF_EMPTY_CONTEXT_0_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_TEST_P__OUT_BUFF_EMPTY_CONTEXT_0_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_TEST_P__OUT_BUFF_EMPTY_CONTEXT_0_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_TEST_P__OUT_BUFF_EMPTY_CONTEXT_1_MASK 0x00000100U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_TEST_P__OUT_BUFF_EMPTY_CONTEXT_1_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_TEST_P__OUT_BUFF_EMPTY_CONTEXT_1_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_TEST_P__OUT_BUFF_EMPTY_CONTEXT_1_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_TEST_P__OUT_BUFF_EMPTY_CONTEXT_1_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_TEST_P__OUT_BUFF_FULL_CONTEXT_0_MASK 0x00000200U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_TEST_P__OUT_BUFF_FULL_CONTEXT_0_SHIFT 9U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_TEST_P__OUT_BUFF_FULL_CONTEXT_0_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_TEST_P__OUT_BUFF_FULL_CONTEXT_0_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_TEST_P__OUT_BUFF_FULL_CONTEXT_0_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_TEST_P__OUT_BUFF_FULL_CONTEXT_1_MASK 0x00000400U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_TEST_P__OUT_BUFF_FULL_CONTEXT_1_SHIFT 10U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_TEST_P__OUT_BUFF_FULL_CONTEXT_1_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_TEST_P__OUT_BUFF_FULL_CONTEXT_1_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_TEST_P__OUT_BUFF_FULL_CONTEXT_1_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_TEST_P__RESERVED_0_MASK 0xFFFFF800U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_TEST_P__RESERVED_0_SHIFT 11U
+#define MHDP__MHDP_APB_REGS__ENC0_INT_TEST_P__RESERVED_0_WIDTH 21U
+
+#define MHDP__MHDP_APB_REGS__ENC1_MAIN_CONF_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC1_MAIN_CONF_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC1_MAIN_CONF_P__INPUT_BPC_MASK 0x00000003U
+#define MHDP__MHDP_APB_REGS__ENC1_MAIN_CONF_P__INPUT_BPC_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__ENC1_MAIN_CONF_P__INPUT_BPC_WIDTH 2U
+#define MHDP__MHDP_APB_REGS__ENC1_MAIN_CONF_P__CONVERT_RGB_MASK 0x00000004U
+#define MHDP__MHDP_APB_REGS__ENC1_MAIN_CONF_P__CONVERT_RGB_SHIFT 2U
+#define MHDP__MHDP_APB_REGS__ENC1_MAIN_CONF_P__CONVERT_RGB_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC1_MAIN_CONF_P__CONVERT_RGB_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC1_MAIN_CONF_P__CONVERT_RGB_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC1_MAIN_CONF_P__ENABLE_422_MASK 0x00000008U
+#define MHDP__MHDP_APB_REGS__ENC1_MAIN_CONF_P__ENABLE_422_SHIFT 3U
+#define MHDP__MHDP_APB_REGS__ENC1_MAIN_CONF_P__ENABLE_422_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC1_MAIN_CONF_P__ENABLE_422_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC1_MAIN_CONF_P__ENABLE_422_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC1_MAIN_CONF_P__LINEBUF_DEPTH_MASK 0x000000F0U
+#define MHDP__MHDP_APB_REGS__ENC1_MAIN_CONF_P__LINEBUF_DEPTH_SHIFT 4U
+#define MHDP__MHDP_APB_REGS__ENC1_MAIN_CONF_P__LINEBUF_DEPTH_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__ENC1_MAIN_CONF_P__BITS_PER_PIXEL_MASK 0x0003FF00U
+#define MHDP__MHDP_APB_REGS__ENC1_MAIN_CONF_P__BITS_PER_PIXEL_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__ENC1_MAIN_CONF_P__BITS_PER_PIXEL_WIDTH 10U
+#define MHDP__MHDP_APB_REGS__ENC1_MAIN_CONF_P__BLOCK_PRED_ENABLE_MASK 0x00040000U
+#define MHDP__MHDP_APB_REGS__ENC1_MAIN_CONF_P__BLOCK_PRED_ENABLE_SHIFT 18U
+#define MHDP__MHDP_APB_REGS__ENC1_MAIN_CONF_P__BLOCK_PRED_ENABLE_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC1_MAIN_CONF_P__BLOCK_PRED_ENABLE_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC1_MAIN_CONF_P__BLOCK_PRED_ENABLE_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC1_MAIN_CONF_P__VIDEO_MODE_MASK 0x00080000U
+#define MHDP__MHDP_APB_REGS__ENC1_MAIN_CONF_P__VIDEO_MODE_SHIFT 19U
+#define MHDP__MHDP_APB_REGS__ENC1_MAIN_CONF_P__VIDEO_MODE_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC1_MAIN_CONF_P__VIDEO_MODE_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC1_MAIN_CONF_P__VIDEO_MODE_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC1_MAIN_CONF_P__ICH_RST_EOL_MASK 0x00100000U
+#define MHDP__MHDP_APB_REGS__ENC1_MAIN_CONF_P__ICH_RST_EOL_SHIFT 20U
+#define MHDP__MHDP_APB_REGS__ENC1_MAIN_CONF_P__ICH_RST_EOL_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC1_MAIN_CONF_P__ICH_RST_EOL_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC1_MAIN_CONF_P__ICH_RST_EOL_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC1_MAIN_CONF_P__RESERVED_1_MASK 0x00E00000U
+#define MHDP__MHDP_APB_REGS__ENC1_MAIN_CONF_P__RESERVED_1_SHIFT 21U
+#define MHDP__MHDP_APB_REGS__ENC1_MAIN_CONF_P__RESERVED_1_WIDTH 3U
+#define MHDP__MHDP_APB_REGS__ENC1_MAIN_CONF_P__INITIAL_LINES_MASK 0xFF000000U
+#define MHDP__MHDP_APB_REGS__ENC1_MAIN_CONF_P__INITIAL_LINES_SHIFT 24U
+#define MHDP__MHDP_APB_REGS__ENC1_MAIN_CONF_P__INITIAL_LINES_WIDTH 8U
+
+#define MHDP__MHDP_APB_REGS__ENC1_PICTURE_SIZE_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC1_PICTURE_SIZE_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC1_PICTURE_SIZE_P__PICTURE_WIDTH_MASK 0x0000FFFFU
+#define MHDP__MHDP_APB_REGS__ENC1_PICTURE_SIZE_P__PICTURE_WIDTH_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__ENC1_PICTURE_SIZE_P__PICTURE_WIDTH_WIDTH 16U
+#define MHDP__MHDP_APB_REGS__ENC1_PICTURE_SIZE_P__PICTURE_HEIGHT_MASK 0xFFFF0000U
+#define MHDP__MHDP_APB_REGS__ENC1_PICTURE_SIZE_P__PICTURE_HEIGHT_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__ENC1_PICTURE_SIZE_P__PICTURE_HEIGHT_WIDTH 16U
+
+#define MHDP__MHDP_APB_REGS__ENC1_SLICE_SIZE_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC1_SLICE_SIZE_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC1_SLICE_SIZE_P__SLICE_WIDTH_MASK 0x0000FFFFU
+#define MHDP__MHDP_APB_REGS__ENC1_SLICE_SIZE_P__SLICE_WIDTH_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__ENC1_SLICE_SIZE_P__SLICE_WIDTH_WIDTH 16U
+#define MHDP__MHDP_APB_REGS__ENC1_SLICE_SIZE_P__SLICE_HEIGHT_MASK 0xFFFF0000U
+#define MHDP__MHDP_APB_REGS__ENC1_SLICE_SIZE_P__SLICE_HEIGHT_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__ENC1_SLICE_SIZE_P__SLICE_HEIGHT_WIDTH 16U
+
+#define MHDP__MHDP_APB_REGS__ENC1_MISC_SIZE_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC1_MISC_SIZE_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC1_MISC_SIZE_P__SLICE_LAST_GROUP_SIZE_MASK 0x00000003U
+#define MHDP__MHDP_APB_REGS__ENC1_MISC_SIZE_P__SLICE_LAST_GROUP_SIZE_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__ENC1_MISC_SIZE_P__SLICE_LAST_GROUP_SIZE_WIDTH 2U
+#define MHDP__MHDP_APB_REGS__ENC1_MISC_SIZE_P__OB_MAX_ADDR_MASK 0x0000FFFCU
+#define MHDP__MHDP_APB_REGS__ENC1_MISC_SIZE_P__OB_MAX_ADDR_SHIFT 2U
+#define MHDP__MHDP_APB_REGS__ENC1_MISC_SIZE_P__OB_MAX_ADDR_WIDTH 14U
+#define MHDP__MHDP_APB_REGS__ENC1_MISC_SIZE_P__CHUNK_SIZE_MASK 0xFFFF0000U
+#define MHDP__MHDP_APB_REGS__ENC1_MISC_SIZE_P__CHUNK_SIZE_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__ENC1_MISC_SIZE_P__CHUNK_SIZE_WIDTH 16U
+
+#define MHDP__MHDP_APB_REGS__ENC1_HRD_DELAYS_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC1_HRD_DELAYS_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC1_HRD_DELAYS_P__INITIAL_XMIT_DELAY_MASK 0x000003FFU
+#define MHDP__MHDP_APB_REGS__ENC1_HRD_DELAYS_P__INITIAL_XMIT_DELAY_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__ENC1_HRD_DELAYS_P__INITIAL_XMIT_DELAY_WIDTH 10U
+#define MHDP__MHDP_APB_REGS__ENC1_HRD_DELAYS_P__RESERVED_0_MASK 0x0000FC00U
+#define MHDP__MHDP_APB_REGS__ENC1_HRD_DELAYS_P__RESERVED_0_SHIFT 10U
+#define MHDP__MHDP_APB_REGS__ENC1_HRD_DELAYS_P__RESERVED_0_WIDTH 6U
+#define MHDP__MHDP_APB_REGS__ENC1_HRD_DELAYS_P__INITIAL_DEC_DELAY_MASK 0xFFFF0000U
+#define MHDP__MHDP_APB_REGS__ENC1_HRD_DELAYS_P__INITIAL_DEC_DELAY_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__ENC1_HRD_DELAYS_P__INITIAL_DEC_DELAY_WIDTH 16U
+
+#define MHDP__MHDP_APB_REGS__ENC1_RC_SCALE_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC1_RC_SCALE_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC1_RC_SCALE_P__INITIAL_SCALE_VALUE_MASK 0x0000003FU
+#define MHDP__MHDP_APB_REGS__ENC1_RC_SCALE_P__INITIAL_SCALE_VALUE_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_SCALE_P__INITIAL_SCALE_VALUE_WIDTH 6U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_SCALE_P__RESERVED_0_MASK 0xFFFFFFC0U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_SCALE_P__RESERVED_0_SHIFT 6U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_SCALE_P__RESERVED_0_WIDTH 26U
+
+#define MHDP__MHDP_APB_REGS__ENC1_RC_SCALE_INC_DEC_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC1_RC_SCALE_INC_DEC_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC1_RC_SCALE_INC_DEC_P__SCALE_INCREMENT_INTERVAL_MASK 0x0000FFFFU
+#define MHDP__MHDP_APB_REGS__ENC1_RC_SCALE_INC_DEC_P__SCALE_INCREMENT_INTERVAL_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_SCALE_INC_DEC_P__SCALE_INCREMENT_INTERVAL_WIDTH 16U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_SCALE_INC_DEC_P__SCALE_DECREMENT_INTERVAL_MASK 0x0FFF0000U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_SCALE_INC_DEC_P__SCALE_DECREMENT_INTERVAL_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_SCALE_INC_DEC_P__SCALE_DECREMENT_INTERVAL_WIDTH 12U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_SCALE_INC_DEC_P__RESERVED_0_MASK 0xF0000000U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_SCALE_INC_DEC_P__RESERVED_0_SHIFT 28U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_SCALE_INC_DEC_P__RESERVED_0_WIDTH 4U
+
+#define MHDP__MHDP_APB_REGS__ENC1_RC_OFFSETS_1_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC1_RC_OFFSETS_1_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC1_RC_OFFSETS_1_P__FIRST_LINE_BPG_OFFSET_MASK 0x0000001FU
+#define MHDP__MHDP_APB_REGS__ENC1_RC_OFFSETS_1_P__FIRST_LINE_BPG_OFFSET_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_OFFSETS_1_P__FIRST_LINE_BPG_OFFSET_WIDTH 5U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_OFFSETS_1_P__RESERVED_0_MASK 0xFFFFFFE0U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_OFFSETS_1_P__RESERVED_0_SHIFT 5U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_OFFSETS_1_P__RESERVED_0_WIDTH 27U
+
+#define MHDP__MHDP_APB_REGS__ENC1_RC_OFFSETS_2_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC1_RC_OFFSETS_2_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC1_RC_OFFSETS_2_P__NFL_BPG_OFFSET_MASK 0x0000FFFFU
+#define MHDP__MHDP_APB_REGS__ENC1_RC_OFFSETS_2_P__NFL_BPG_OFFSET_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_OFFSETS_2_P__NFL_BPG_OFFSET_WIDTH 16U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_OFFSETS_2_P__SLICE_BPG_OFFSET_MASK 0xFFFF0000U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_OFFSETS_2_P__SLICE_BPG_OFFSET_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_OFFSETS_2_P__SLICE_BPG_OFFSET_WIDTH 16U
+
+#define MHDP__MHDP_APB_REGS__ENC1_RC_OFFSETS_3_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC1_RC_OFFSETS_3_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC1_RC_OFFSETS_3_P__INITIAL_OFFSET_MASK 0x0000FFFFU
+#define MHDP__MHDP_APB_REGS__ENC1_RC_OFFSETS_3_P__INITIAL_OFFSET_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_OFFSETS_3_P__INITIAL_OFFSET_WIDTH 16U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_OFFSETS_3_P__FINAL_OFFSET_MASK 0xFFFF0000U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_OFFSETS_3_P__FINAL_OFFSET_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_OFFSETS_3_P__FINAL_OFFSET_WIDTH 16U
+
+#define MHDP__MHDP_APB_REGS__ENC1_FLATNESS_DETECTION_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC1_FLATNESS_DETECTION_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC1_FLATNESS_DETECTION_P__FLATNESS_MIN_QP_MASK 0x0000001FU
+#define MHDP__MHDP_APB_REGS__ENC1_FLATNESS_DETECTION_P__FLATNESS_MIN_QP_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__ENC1_FLATNESS_DETECTION_P__FLATNESS_MIN_QP_WIDTH 5U
+#define MHDP__MHDP_APB_REGS__ENC1_FLATNESS_DETECTION_P__FLATNESS_MAX_QP_MASK 0x000003E0U
+#define MHDP__MHDP_APB_REGS__ENC1_FLATNESS_DETECTION_P__FLATNESS_MAX_QP_SHIFT 5U
+#define MHDP__MHDP_APB_REGS__ENC1_FLATNESS_DETECTION_P__FLATNESS_MAX_QP_WIDTH 5U
+#define MHDP__MHDP_APB_REGS__ENC1_FLATNESS_DETECTION_P__FLATNESS_DET_THRESH_MASK 0x0003FC00U
+#define MHDP__MHDP_APB_REGS__ENC1_FLATNESS_DETECTION_P__FLATNESS_DET_THRESH_SHIFT 10U
+#define MHDP__MHDP_APB_REGS__ENC1_FLATNESS_DETECTION_P__FLATNESS_DET_THRESH_WIDTH 8U
+#define MHDP__MHDP_APB_REGS__ENC1_FLATNESS_DETECTION_P__RESERVED_0_MASK 0xFFFC0000U
+#define MHDP__MHDP_APB_REGS__ENC1_FLATNESS_DETECTION_P__RESERVED_0_SHIFT 18U
+#define MHDP__MHDP_APB_REGS__ENC1_FLATNESS_DETECTION_P__RESERVED_0_WIDTH 14U
+
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MODEL_SIZE_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MODEL_SIZE_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MODEL_SIZE_P__RC_MODEL_SIZE_MASK 0x0000FFFFU
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MODEL_SIZE_P__RC_MODEL_SIZE_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MODEL_SIZE_P__RC_MODEL_SIZE_WIDTH 16U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MODEL_SIZE_P__RESERVED_0_MASK 0xFFFF0000U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MODEL_SIZE_P__RESERVED_0_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MODEL_SIZE_P__RESERVED_0_WIDTH 16U
+
+#define MHDP__MHDP_APB_REGS__ENC1_RC_CONFIG_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC1_RC_CONFIG_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC1_RC_CONFIG_P__RC_EDGE_FACTOR_MASK 0x0000000FU
+#define MHDP__MHDP_APB_REGS__ENC1_RC_CONFIG_P__RC_EDGE_FACTOR_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_CONFIG_P__RC_EDGE_FACTOR_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_CONFIG_P__RESERVED_0_MASK 0x000000F0U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_CONFIG_P__RESERVED_0_SHIFT 4U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_CONFIG_P__RESERVED_0_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_CONFIG_P__RC_QUANT_INCR_LIMIT0_MASK 0x00001F00U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_CONFIG_P__RC_QUANT_INCR_LIMIT0_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_CONFIG_P__RC_QUANT_INCR_LIMIT0_WIDTH 5U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_CONFIG_P__RC_QUANT_INCR_LIMIT1_MASK 0x0003E000U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_CONFIG_P__RC_QUANT_INCR_LIMIT1_SHIFT 13U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_CONFIG_P__RC_QUANT_INCR_LIMIT1_WIDTH 5U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_CONFIG_P__RESERVED_1_MASK 0x000C0000U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_CONFIG_P__RESERVED_1_SHIFT 18U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_CONFIG_P__RESERVED_1_WIDTH 2U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_CONFIG_P__RC_TGT_OFFSET_HI_MASK 0x00F00000U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_CONFIG_P__RC_TGT_OFFSET_HI_SHIFT 20U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_CONFIG_P__RC_TGT_OFFSET_HI_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_CONFIG_P__RC_TGT_OFFSET_LO_MASK 0x0F000000U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_CONFIG_P__RC_TGT_OFFSET_LO_SHIFT 24U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_CONFIG_P__RC_TGT_OFFSET_LO_WIDTH 4U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_CONFIG_P__RESERVED_2_MASK 0xF0000000U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_CONFIG_P__RESERVED_2_SHIFT 28U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_CONFIG_P__RESERVED_2_WIDTH 4U
+
+#define MHDP__MHDP_APB_REGS__ENC1_RC_BUF_THRESH_0_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC1_RC_BUF_THRESH_0_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC1_RC_BUF_THRESH_0_P__RC_BUF_THRESH_0_MASK 0x000000FFU
+#define MHDP__MHDP_APB_REGS__ENC1_RC_BUF_THRESH_0_P__RC_BUF_THRESH_0_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_BUF_THRESH_0_P__RC_BUF_THRESH_0_WIDTH 8U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_BUF_THRESH_0_P__RC_BUF_THRESH_1_MASK 0x0000FF00U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_BUF_THRESH_0_P__RC_BUF_THRESH_1_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_BUF_THRESH_0_P__RC_BUF_THRESH_1_WIDTH 8U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_BUF_THRESH_0_P__RC_BUF_THRESH_2_MASK 0x00FF0000U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_BUF_THRESH_0_P__RC_BUF_THRESH_2_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_BUF_THRESH_0_P__RC_BUF_THRESH_2_WIDTH 8U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_BUF_THRESH_0_P__RC_BUF_THRESH_3_MASK 0xFF000000U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_BUF_THRESH_0_P__RC_BUF_THRESH_3_SHIFT 24U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_BUF_THRESH_0_P__RC_BUF_THRESH_3_WIDTH 8U
+
+#define MHDP__MHDP_APB_REGS__ENC1_RC_BUF_THRESH_1_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC1_RC_BUF_THRESH_1_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC1_RC_BUF_THRESH_1_P__RC_BUF_THRESH_4_MASK 0x000000FFU
+#define MHDP__MHDP_APB_REGS__ENC1_RC_BUF_THRESH_1_P__RC_BUF_THRESH_4_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_BUF_THRESH_1_P__RC_BUF_THRESH_4_WIDTH 8U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_BUF_THRESH_1_P__RC_BUF_THRESH_5_MASK 0x0000FF00U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_BUF_THRESH_1_P__RC_BUF_THRESH_5_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_BUF_THRESH_1_P__RC_BUF_THRESH_5_WIDTH 8U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_BUF_THRESH_1_P__RC_BUF_THRESH_6_MASK 0x00FF0000U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_BUF_THRESH_1_P__RC_BUF_THRESH_6_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_BUF_THRESH_1_P__RC_BUF_THRESH_6_WIDTH 8U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_BUF_THRESH_1_P__RC_BUF_THRESH_7_MASK 0xFF000000U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_BUF_THRESH_1_P__RC_BUF_THRESH_7_SHIFT 24U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_BUF_THRESH_1_P__RC_BUF_THRESH_7_WIDTH 8U
+
+#define MHDP__MHDP_APB_REGS__ENC1_RC_BUF_THRESH_2_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC1_RC_BUF_THRESH_2_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC1_RC_BUF_THRESH_2_P__RC_BUF_THRESH_8_MASK 0x000000FFU
+#define MHDP__MHDP_APB_REGS__ENC1_RC_BUF_THRESH_2_P__RC_BUF_THRESH_8_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_BUF_THRESH_2_P__RC_BUF_THRESH_8_WIDTH 8U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_BUF_THRESH_2_P__RC_BUF_THRESH_9_MASK 0x0000FF00U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_BUF_THRESH_2_P__RC_BUF_THRESH_9_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_BUF_THRESH_2_P__RC_BUF_THRESH_9_WIDTH 8U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_BUF_THRESH_2_P__RC_BUF_THRESH_10_MASK 0x00FF0000U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_BUF_THRESH_2_P__RC_BUF_THRESH_10_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_BUF_THRESH_2_P__RC_BUF_THRESH_10_WIDTH 8U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_BUF_THRESH_2_P__RC_BUF_THRESH_11_MASK 0xFF000000U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_BUF_THRESH_2_P__RC_BUF_THRESH_11_SHIFT 24U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_BUF_THRESH_2_P__RC_BUF_THRESH_11_WIDTH 8U
+
+#define MHDP__MHDP_APB_REGS__ENC1_RC_BUF_THRESH_3_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC1_RC_BUF_THRESH_3_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC1_RC_BUF_THRESH_3_P__RC_BUF_THRESH_12_MASK 0x000000FFU
+#define MHDP__MHDP_APB_REGS__ENC1_RC_BUF_THRESH_3_P__RC_BUF_THRESH_12_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_BUF_THRESH_3_P__RC_BUF_THRESH_12_WIDTH 8U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_BUF_THRESH_3_P__RC_BUF_THRESH_13_MASK 0x0000FF00U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_BUF_THRESH_3_P__RC_BUF_THRESH_13_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_BUF_THRESH_3_P__RC_BUF_THRESH_13_WIDTH 8U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_BUF_THRESH_3_P__RESERVED_0_MASK 0xFFFF0000U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_BUF_THRESH_3_P__RESERVED_0_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_BUF_THRESH_3_P__RESERVED_0_WIDTH 16U
+
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MIN_QP_0_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MIN_QP_0_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MIN_QP_0_P__RANGE_MIN_QP_0_MASK 0x0000001FU
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MIN_QP_0_P__RANGE_MIN_QP_0_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MIN_QP_0_P__RANGE_MIN_QP_0_WIDTH 5U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MIN_QP_0_P__RANGE_MIN_QP_1_MASK 0x000003E0U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MIN_QP_0_P__RANGE_MIN_QP_1_SHIFT 5U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MIN_QP_0_P__RANGE_MIN_QP_1_WIDTH 5U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MIN_QP_0_P__RANGE_MIN_QP_2_MASK 0x00007C00U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MIN_QP_0_P__RANGE_MIN_QP_2_SHIFT 10U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MIN_QP_0_P__RANGE_MIN_QP_2_WIDTH 5U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MIN_QP_0_P__RANGE_MIN_QP_3_MASK 0x000F8000U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MIN_QP_0_P__RANGE_MIN_QP_3_SHIFT 15U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MIN_QP_0_P__RANGE_MIN_QP_3_WIDTH 5U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MIN_QP_0_P__RANGE_MIN_QP_4_MASK 0x01F00000U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MIN_QP_0_P__RANGE_MIN_QP_4_SHIFT 20U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MIN_QP_0_P__RANGE_MIN_QP_4_WIDTH 5U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MIN_QP_0_P__RESERVED_0_MASK 0xFE000000U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MIN_QP_0_P__RESERVED_0_SHIFT 25U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MIN_QP_0_P__RESERVED_0_WIDTH 7U
+
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MIN_QP_1_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MIN_QP_1_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MIN_QP_1_P__RANGE_MIN_QP_5_MASK 0x0000001FU
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MIN_QP_1_P__RANGE_MIN_QP_5_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MIN_QP_1_P__RANGE_MIN_QP_5_WIDTH 5U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MIN_QP_1_P__RANGE_MIN_QP_6_MASK 0x000003E0U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MIN_QP_1_P__RANGE_MIN_QP_6_SHIFT 5U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MIN_QP_1_P__RANGE_MIN_QP_6_WIDTH 5U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MIN_QP_1_P__RANGE_MIN_QP_7_MASK 0x00007C00U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MIN_QP_1_P__RANGE_MIN_QP_7_SHIFT 10U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MIN_QP_1_P__RANGE_MIN_QP_7_WIDTH 5U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MIN_QP_1_P__RANGE_MIN_QP_8_MASK 0x000F8000U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MIN_QP_1_P__RANGE_MIN_QP_8_SHIFT 15U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MIN_QP_1_P__RANGE_MIN_QP_8_WIDTH 5U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MIN_QP_1_P__RANGE_MIN_QP_9_MASK 0x01F00000U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MIN_QP_1_P__RANGE_MIN_QP_9_SHIFT 20U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MIN_QP_1_P__RANGE_MIN_QP_9_WIDTH 5U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MIN_QP_1_P__RESERVED_0_MASK 0xFE000000U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MIN_QP_1_P__RESERVED_0_SHIFT 25U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MIN_QP_1_P__RESERVED_0_WIDTH 7U
+
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MIN_QP_2_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MIN_QP_2_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MIN_QP_2_P__RANGE_MIN_QP_10_MASK 0x0000001FU
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MIN_QP_2_P__RANGE_MIN_QP_10_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MIN_QP_2_P__RANGE_MIN_QP_10_WIDTH 5U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MIN_QP_2_P__RANGE_MIN_QP_11_MASK 0x000003E0U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MIN_QP_2_P__RANGE_MIN_QP_11_SHIFT 5U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MIN_QP_2_P__RANGE_MIN_QP_11_WIDTH 5U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MIN_QP_2_P__RANGE_MIN_QP_12_MASK 0x00007C00U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MIN_QP_2_P__RANGE_MIN_QP_12_SHIFT 10U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MIN_QP_2_P__RANGE_MIN_QP_12_WIDTH 5U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MIN_QP_2_P__RANGE_MIN_QP_13_MASK 0x000F8000U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MIN_QP_2_P__RANGE_MIN_QP_13_SHIFT 15U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MIN_QP_2_P__RANGE_MIN_QP_13_WIDTH 5U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MIN_QP_2_P__RANGE_MIN_QP_14_MASK 0x01F00000U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MIN_QP_2_P__RANGE_MIN_QP_14_SHIFT 20U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MIN_QP_2_P__RANGE_MIN_QP_14_WIDTH 5U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MIN_QP_2_P__RESERVED_0_MASK 0xFE000000U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MIN_QP_2_P__RESERVED_0_SHIFT 25U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MIN_QP_2_P__RESERVED_0_WIDTH 7U
+
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MAX_QP_0_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MAX_QP_0_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MAX_QP_0_P__RANGE_MAX_QP_0_MASK 0x0000001FU
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MAX_QP_0_P__RANGE_MAX_QP_0_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MAX_QP_0_P__RANGE_MAX_QP_0_WIDTH 5U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MAX_QP_0_P__RANGE_MAX_QP_1_MASK 0x000003E0U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MAX_QP_0_P__RANGE_MAX_QP_1_SHIFT 5U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MAX_QP_0_P__RANGE_MAX_QP_1_WIDTH 5U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MAX_QP_0_P__RANGE_MAX_QP_2_MASK 0x00007C00U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MAX_QP_0_P__RANGE_MAX_QP_2_SHIFT 10U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MAX_QP_0_P__RANGE_MAX_QP_2_WIDTH 5U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MAX_QP_0_P__RANGE_MAX_QP_3_MASK 0x000F8000U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MAX_QP_0_P__RANGE_MAX_QP_3_SHIFT 15U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MAX_QP_0_P__RANGE_MAX_QP_3_WIDTH 5U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MAX_QP_0_P__RANGE_MAX_QP_4_MASK 0x01F00000U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MAX_QP_0_P__RANGE_MAX_QP_4_SHIFT 20U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MAX_QP_0_P__RANGE_MAX_QP_4_WIDTH 5U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MAX_QP_0_P__RESERVED_0_MASK 0xFE000000U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MAX_QP_0_P__RESERVED_0_SHIFT 25U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MAX_QP_0_P__RESERVED_0_WIDTH 7U
+
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MAX_QP_1_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MAX_QP_1_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MAX_QP_1_P__RANGE_MAX_QP_5_MASK 0x0000001FU
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MAX_QP_1_P__RANGE_MAX_QP_5_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MAX_QP_1_P__RANGE_MAX_QP_5_WIDTH 5U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MAX_QP_1_P__RANGE_MAX_QP_6_MASK 0x000003E0U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MAX_QP_1_P__RANGE_MAX_QP_6_SHIFT 5U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MAX_QP_1_P__RANGE_MAX_QP_6_WIDTH 5U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MAX_QP_1_P__RANGE_MAX_QP_7_MASK 0x00007C00U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MAX_QP_1_P__RANGE_MAX_QP_7_SHIFT 10U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MAX_QP_1_P__RANGE_MAX_QP_7_WIDTH 5U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MAX_QP_1_P__RANGE_MAX_QP_8_MASK 0x000F8000U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MAX_QP_1_P__RANGE_MAX_QP_8_SHIFT 15U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MAX_QP_1_P__RANGE_MAX_QP_8_WIDTH 5U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MAX_QP_1_P__RANGE_MAX_QP_9_MASK 0x01F00000U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MAX_QP_1_P__RANGE_MAX_QP_9_SHIFT 20U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MAX_QP_1_P__RANGE_MAX_QP_9_WIDTH 5U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MAX_QP_1_P__RESERVED_0_MASK 0xFE000000U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MAX_QP_1_P__RESERVED_0_SHIFT 25U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MAX_QP_1_P__RESERVED_0_WIDTH 7U
+
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MAX_QP_2_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MAX_QP_2_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MAX_QP_2_P__RANGE_MAX_QP_10_MASK 0x0000001FU
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MAX_QP_2_P__RANGE_MAX_QP_10_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MAX_QP_2_P__RANGE_MAX_QP_10_WIDTH 5U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MAX_QP_2_P__RANGE_MAX_QP_11_MASK 0x000003E0U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MAX_QP_2_P__RANGE_MAX_QP_11_SHIFT 5U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MAX_QP_2_P__RANGE_MAX_QP_11_WIDTH 5U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MAX_QP_2_P__RANGE_MAX_QP_12_MASK 0x00007C00U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MAX_QP_2_P__RANGE_MAX_QP_12_SHIFT 10U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MAX_QP_2_P__RANGE_MAX_QP_12_WIDTH 5U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MAX_QP_2_P__RANGE_MAX_QP_13_MASK 0x000F8000U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MAX_QP_2_P__RANGE_MAX_QP_13_SHIFT 15U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MAX_QP_2_P__RANGE_MAX_QP_13_WIDTH 5U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MAX_QP_2_P__RANGE_MAX_QP_14_MASK 0x01F00000U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MAX_QP_2_P__RANGE_MAX_QP_14_SHIFT 20U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MAX_QP_2_P__RANGE_MAX_QP_14_WIDTH 5U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MAX_QP_2_P__RESERVED_0_MASK 0xFE000000U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MAX_QP_2_P__RESERVED_0_SHIFT 25U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_MAX_QP_2_P__RESERVED_0_WIDTH 7U
+
+#define MHDP__MHDP_APB_REGS__ENC1_RC_RANGE_BPG_OFFSETS_0_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC1_RC_RANGE_BPG_OFFSETS_0_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC1_RC_RANGE_BPG_OFFSETS_0_P__RANGE_BPG_OFFSET_0_MASK 0x0000003FU
+#define MHDP__MHDP_APB_REGS__ENC1_RC_RANGE_BPG_OFFSETS_0_P__RANGE_BPG_OFFSET_0_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_RANGE_BPG_OFFSETS_0_P__RANGE_BPG_OFFSET_0_WIDTH 6U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_RANGE_BPG_OFFSETS_0_P__RANGE_BPG_OFFSET_1_MASK 0x00000FC0U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_RANGE_BPG_OFFSETS_0_P__RANGE_BPG_OFFSET_1_SHIFT 6U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_RANGE_BPG_OFFSETS_0_P__RANGE_BPG_OFFSET_1_WIDTH 6U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_RANGE_BPG_OFFSETS_0_P__RANGE_BPG_OFFSET_2_MASK 0x0003F000U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_RANGE_BPG_OFFSETS_0_P__RANGE_BPG_OFFSET_2_SHIFT 12U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_RANGE_BPG_OFFSETS_0_P__RANGE_BPG_OFFSET_2_WIDTH 6U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_RANGE_BPG_OFFSETS_0_P__RANGE_BPG_OFFSET_3_MASK 0x00FC0000U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_RANGE_BPG_OFFSETS_0_P__RANGE_BPG_OFFSET_3_SHIFT 18U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_RANGE_BPG_OFFSETS_0_P__RANGE_BPG_OFFSET_3_WIDTH 6U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_RANGE_BPG_OFFSETS_0_P__RANGE_BPG_OFFSET_4_MASK 0x3F000000U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_RANGE_BPG_OFFSETS_0_P__RANGE_BPG_OFFSET_4_SHIFT 24U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_RANGE_BPG_OFFSETS_0_P__RANGE_BPG_OFFSET_4_WIDTH 6U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_RANGE_BPG_OFFSETS_0_P__RESERVED_0_MASK 0xC0000000U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_RANGE_BPG_OFFSETS_0_P__RESERVED_0_SHIFT 30U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_RANGE_BPG_OFFSETS_0_P__RESERVED_0_WIDTH 2U
+
+#define MHDP__MHDP_APB_REGS__ENC1_RC_RANGE_BPG_OFFSETS_1_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC1_RC_RANGE_BPG_OFFSETS_1_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC1_RC_RANGE_BPG_OFFSETS_1_P__RANGE_BPG_OFFSET_5_MASK 0x0000003FU
+#define MHDP__MHDP_APB_REGS__ENC1_RC_RANGE_BPG_OFFSETS_1_P__RANGE_BPG_OFFSET_5_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_RANGE_BPG_OFFSETS_1_P__RANGE_BPG_OFFSET_5_WIDTH 6U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_RANGE_BPG_OFFSETS_1_P__RANGE_BPG_OFFSET_6_MASK 0x00000FC0U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_RANGE_BPG_OFFSETS_1_P__RANGE_BPG_OFFSET_6_SHIFT 6U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_RANGE_BPG_OFFSETS_1_P__RANGE_BPG_OFFSET_6_WIDTH 6U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_RANGE_BPG_OFFSETS_1_P__RANGE_BPG_OFFSET_7_MASK 0x0003F000U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_RANGE_BPG_OFFSETS_1_P__RANGE_BPG_OFFSET_7_SHIFT 12U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_RANGE_BPG_OFFSETS_1_P__RANGE_BPG_OFFSET_7_WIDTH 6U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_RANGE_BPG_OFFSETS_1_P__RANGE_BPG_OFFSET_8_MASK 0x00FC0000U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_RANGE_BPG_OFFSETS_1_P__RANGE_BPG_OFFSET_8_SHIFT 18U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_RANGE_BPG_OFFSETS_1_P__RANGE_BPG_OFFSET_8_WIDTH 6U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_RANGE_BPG_OFFSETS_1_P__RANGE_BPG_OFFSET_9_MASK 0x3F000000U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_RANGE_BPG_OFFSETS_1_P__RANGE_BPG_OFFSET_9_SHIFT 24U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_RANGE_BPG_OFFSETS_1_P__RANGE_BPG_OFFSET_9_WIDTH 6U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_RANGE_BPG_OFFSETS_1_P__RESERVED_0_MASK 0xC0000000U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_RANGE_BPG_OFFSETS_1_P__RESERVED_0_SHIFT 30U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_RANGE_BPG_OFFSETS_1_P__RESERVED_0_WIDTH 2U
+
+#define MHDP__MHDP_APB_REGS__ENC1_RC_RANGE_BPG_OFFSETS_2_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC1_RC_RANGE_BPG_OFFSETS_2_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC1_RC_RANGE_BPG_OFFSETS_2_P__RANGE_BPG_OFFSET_10_MASK 0x0000003FU
+#define MHDP__MHDP_APB_REGS__ENC1_RC_RANGE_BPG_OFFSETS_2_P__RANGE_BPG_OFFSET_10_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_RANGE_BPG_OFFSETS_2_P__RANGE_BPG_OFFSET_10_WIDTH 6U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_RANGE_BPG_OFFSETS_2_P__RANGE_BPG_OFFSET_11_MASK 0x00000FC0U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_RANGE_BPG_OFFSETS_2_P__RANGE_BPG_OFFSET_11_SHIFT 6U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_RANGE_BPG_OFFSETS_2_P__RANGE_BPG_OFFSET_11_WIDTH 6U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_RANGE_BPG_OFFSETS_2_P__RANGE_BPG_OFFSET_12_MASK 0x0003F000U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_RANGE_BPG_OFFSETS_2_P__RANGE_BPG_OFFSET_12_SHIFT 12U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_RANGE_BPG_OFFSETS_2_P__RANGE_BPG_OFFSET_12_WIDTH 6U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_RANGE_BPG_OFFSETS_2_P__RANGE_BPG_OFFSET_13_MASK 0x00FC0000U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_RANGE_BPG_OFFSETS_2_P__RANGE_BPG_OFFSET_13_SHIFT 18U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_RANGE_BPG_OFFSETS_2_P__RANGE_BPG_OFFSET_13_WIDTH 6U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_RANGE_BPG_OFFSETS_2_P__RANGE_BPG_OFFSET_14_MASK 0x3F000000U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_RANGE_BPG_OFFSETS_2_P__RANGE_BPG_OFFSET_14_SHIFT 24U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_RANGE_BPG_OFFSETS_2_P__RANGE_BPG_OFFSET_14_WIDTH 6U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_RANGE_BPG_OFFSETS_2_P__RESERVED_0_MASK 0xC0000000U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_RANGE_BPG_OFFSETS_2_P__RESERVED_0_SHIFT 30U
+#define MHDP__MHDP_APB_REGS__ENC1_RC_RANGE_BPG_OFFSETS_2_P__RESERVED_0_WIDTH 2U
+
+#define MHDP__MHDP_APB_REGS__ENC1_DPI_CTRL_OUT_DELAY_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC1_DPI_CTRL_OUT_DELAY_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC1_DPI_CTRL_OUT_DELAY_P__DPI_CTRL_OUT_DELAY_MASK 0x0000FFFFU
+#define MHDP__MHDP_APB_REGS__ENC1_DPI_CTRL_OUT_DELAY_P__DPI_CTRL_OUT_DELAY_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__ENC1_DPI_CTRL_OUT_DELAY_P__DPI_CTRL_OUT_DELAY_WIDTH 16U
+#define MHDP__MHDP_APB_REGS__ENC1_DPI_CTRL_OUT_DELAY_P__RESERVED_0_MASK 0xFFFF0000U
+#define MHDP__MHDP_APB_REGS__ENC1_DPI_CTRL_OUT_DELAY_P__RESERVED_0_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__ENC1_DPI_CTRL_OUT_DELAY_P__RESERVED_0_WIDTH 16U
+
+#define MHDP__MHDP_APB_REGS__ENC1_GENERAL_STATUS_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC1_GENERAL_STATUS_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC1_GENERAL_STATUS_P__CE_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__ENC1_GENERAL_STATUS_P__CE_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__ENC1_GENERAL_STATUS_P__CE_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC1_GENERAL_STATUS_P__CE_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC1_GENERAL_STATUS_P__CE_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC1_GENERAL_STATUS_P__FRAME_STARTED_MASK 0x00000002U
+#define MHDP__MHDP_APB_REGS__ENC1_GENERAL_STATUS_P__FRAME_STARTED_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__ENC1_GENERAL_STATUS_P__FRAME_STARTED_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC1_GENERAL_STATUS_P__FRAME_STARTED_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC1_GENERAL_STATUS_P__FRAME_STARTED_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC1_GENERAL_STATUS_P__FRAME_DONE_MASK 0x00000004U
+#define MHDP__MHDP_APB_REGS__ENC1_GENERAL_STATUS_P__FRAME_DONE_SHIFT 2U
+#define MHDP__MHDP_APB_REGS__ENC1_GENERAL_STATUS_P__FRAME_DONE_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC1_GENERAL_STATUS_P__FRAME_DONE_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC1_GENERAL_STATUS_P__FRAME_DONE_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC1_GENERAL_STATUS_P__OUT_BUFF_EMPTY_CONTEXT_0_MASK 0x00000008U
+#define MHDP__MHDP_APB_REGS__ENC1_GENERAL_STATUS_P__OUT_BUFF_EMPTY_CONTEXT_0_SHIFT 3U
+#define MHDP__MHDP_APB_REGS__ENC1_GENERAL_STATUS_P__OUT_BUFF_EMPTY_CONTEXT_0_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC1_GENERAL_STATUS_P__OUT_BUFF_EMPTY_CONTEXT_0_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC1_GENERAL_STATUS_P__OUT_BUFF_EMPTY_CONTEXT_0_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC1_GENERAL_STATUS_P__OUT_BUFF_EMPTY_CONTEXT_1_MASK 0x00000010U
+#define MHDP__MHDP_APB_REGS__ENC1_GENERAL_STATUS_P__OUT_BUFF_EMPTY_CONTEXT_1_SHIFT 4U
+#define MHDP__MHDP_APB_REGS__ENC1_GENERAL_STATUS_P__OUT_BUFF_EMPTY_CONTEXT_1_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC1_GENERAL_STATUS_P__OUT_BUFF_EMPTY_CONTEXT_1_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC1_GENERAL_STATUS_P__OUT_BUFF_EMPTY_CONTEXT_1_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC1_GENERAL_STATUS_P__OUT_BUFF_FULL_CONTEXT_0_MASK 0x00000020U
+#define MHDP__MHDP_APB_REGS__ENC1_GENERAL_STATUS_P__OUT_BUFF_FULL_CONTEXT_0_SHIFT 5U
+#define MHDP__MHDP_APB_REGS__ENC1_GENERAL_STATUS_P__OUT_BUFF_FULL_CONTEXT_0_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC1_GENERAL_STATUS_P__OUT_BUFF_FULL_CONTEXT_0_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC1_GENERAL_STATUS_P__OUT_BUFF_FULL_CONTEXT_0_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC1_GENERAL_STATUS_P__OUT_BUFF_FULL_CONTEXT_1_MASK 0x00000040U
+#define MHDP__MHDP_APB_REGS__ENC1_GENERAL_STATUS_P__OUT_BUFF_FULL_CONTEXT_1_SHIFT 6U
+#define MHDP__MHDP_APB_REGS__ENC1_GENERAL_STATUS_P__OUT_BUFF_FULL_CONTEXT_1_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC1_GENERAL_STATUS_P__OUT_BUFF_FULL_CONTEXT_1_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC1_GENERAL_STATUS_P__OUT_BUFF_FULL_CONTEXT_1_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC1_GENERAL_STATUS_P__RESERVED_0_MASK 0xFFFFFF80U
+#define MHDP__MHDP_APB_REGS__ENC1_GENERAL_STATUS_P__RESERVED_0_SHIFT 7U
+#define MHDP__MHDP_APB_REGS__ENC1_GENERAL_STATUS_P__RESERVED_0_WIDTH 25U
+
+#define MHDP__MHDP_APB_REGS__ENC1_HSLICE_STATUS_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC1_HSLICE_STATUS_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC1_HSLICE_STATUS_P__SLICE_LINE_COUNT_ENCODED_MASK 0x0000FFFFU
+#define MHDP__MHDP_APB_REGS__ENC1_HSLICE_STATUS_P__SLICE_LINE_COUNT_ENCODED_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__ENC1_HSLICE_STATUS_P__SLICE_LINE_COUNT_ENCODED_WIDTH 16U
+#define MHDP__MHDP_APB_REGS__ENC1_HSLICE_STATUS_P__SLICE_COUNT_ENCODED_MASK 0xFFFF0000U
+#define MHDP__MHDP_APB_REGS__ENC1_HSLICE_STATUS_P__SLICE_COUNT_ENCODED_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__ENC1_HSLICE_STATUS_P__SLICE_COUNT_ENCODED_WIDTH 16U
+
+#define MHDP__MHDP_APB_REGS__ENC1_OUT_STATUS_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC1_OUT_STATUS_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC1_OUT_STATUS_P__SLICE_LINE_COUNT_OUT_MASK 0x0000FFFFU
+#define MHDP__MHDP_APB_REGS__ENC1_OUT_STATUS_P__SLICE_LINE_COUNT_OUT_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__ENC1_OUT_STATUS_P__SLICE_LINE_COUNT_OUT_WIDTH 16U
+#define MHDP__MHDP_APB_REGS__ENC1_OUT_STATUS_P__SLICE_COUNT_OUT_MASK 0xFFFF0000U
+#define MHDP__MHDP_APB_REGS__ENC1_OUT_STATUS_P__SLICE_COUNT_OUT_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__ENC1_OUT_STATUS_P__SLICE_COUNT_OUT_WIDTH 16U
+
+#define MHDP__MHDP_APB_REGS__ENC1_INT_STAT_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC1_INT_STAT_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC1_INT_STAT_P__ENC_UNDERFLOW_CONTEXT_0_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_STAT_P__ENC_UNDERFLOW_CONTEXT_0_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_STAT_P__ENC_UNDERFLOW_CONTEXT_0_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_STAT_P__ENC_UNDERFLOW_CONTEXT_0_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_STAT_P__ENC_UNDERFLOW_CONTEXT_0_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_STAT_P__ENC_UNDERFLOW_CONTEXT_1_MASK 0x00000002U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_STAT_P__ENC_UNDERFLOW_CONTEXT_1_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_STAT_P__ENC_UNDERFLOW_CONTEXT_1_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_STAT_P__ENC_UNDERFLOW_CONTEXT_1_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_STAT_P__ENC_UNDERFLOW_CONTEXT_1_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_STAT_P__RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_0_MASK 0x00000004U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_STAT_P__RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_0_SHIFT 2U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_STAT_P__RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_0_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_STAT_P__RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_0_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_STAT_P__RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_0_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_STAT_P__RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_1_MASK 0x00000008U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_STAT_P__RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_1_SHIFT 3U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_STAT_P__RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_1_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_STAT_P__RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_1_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_STAT_P__RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_1_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_STAT_P__CE_MASK 0x00000010U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_STAT_P__CE_SHIFT 4U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_STAT_P__CE_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_STAT_P__CE_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_STAT_P__CE_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_STAT_P__FRAME_STARTED_MASK 0x00000020U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_STAT_P__FRAME_STARTED_SHIFT 5U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_STAT_P__FRAME_STARTED_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_STAT_P__FRAME_STARTED_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_STAT_P__FRAME_STARTED_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_STAT_P__FRAME_DONE_MASK 0x00000040U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_STAT_P__FRAME_DONE_SHIFT 6U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_STAT_P__FRAME_DONE_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_STAT_P__FRAME_DONE_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_STAT_P__FRAME_DONE_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_STAT_P__OUT_BUFF_EMPTY_CONTEXT_0_MASK 0x00000080U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_STAT_P__OUT_BUFF_EMPTY_CONTEXT_0_SHIFT 7U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_STAT_P__OUT_BUFF_EMPTY_CONTEXT_0_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_STAT_P__OUT_BUFF_EMPTY_CONTEXT_0_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_STAT_P__OUT_BUFF_EMPTY_CONTEXT_0_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_STAT_P__OUT_BUFF_EMPTY_CONTEXT_1_MASK 0x00000100U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_STAT_P__OUT_BUFF_EMPTY_CONTEXT_1_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_STAT_P__OUT_BUFF_EMPTY_CONTEXT_1_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_STAT_P__OUT_BUFF_EMPTY_CONTEXT_1_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_STAT_P__OUT_BUFF_EMPTY_CONTEXT_1_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_STAT_P__OUT_BUFF_FULL_CONTEXT_0_MASK 0x00000200U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_STAT_P__OUT_BUFF_FULL_CONTEXT_0_SHIFT 9U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_STAT_P__OUT_BUFF_FULL_CONTEXT_0_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_STAT_P__OUT_BUFF_FULL_CONTEXT_0_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_STAT_P__OUT_BUFF_FULL_CONTEXT_0_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_STAT_P__OUT_BUFF_FULL_CONTEXT_1_MASK 0x00000400U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_STAT_P__OUT_BUFF_FULL_CONTEXT_1_SHIFT 10U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_STAT_P__OUT_BUFF_FULL_CONTEXT_1_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_STAT_P__OUT_BUFF_FULL_CONTEXT_1_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_STAT_P__OUT_BUFF_FULL_CONTEXT_1_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_STAT_P__RESERVED_0_MASK 0xFFFFF800U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_STAT_P__RESERVED_0_SHIFT 11U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_STAT_P__RESERVED_0_WIDTH 21U
+
+#define MHDP__MHDP_APB_REGS__ENC1_INT_CLR_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC1_INT_CLR_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC1_INT_CLR_P__ENC_UNDERFLOW_CONTEXT_0_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_CLR_P__ENC_UNDERFLOW_CONTEXT_0_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_CLR_P__ENC_UNDERFLOW_CONTEXT_0_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_CLR_P__ENC_UNDERFLOW_CONTEXT_0_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_CLR_P__ENC_UNDERFLOW_CONTEXT_0_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_CLR_P__ENC_UNDERFLOW_CONTEXT_1_MASK 0x00000002U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_CLR_P__ENC_UNDERFLOW_CONTEXT_1_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_CLR_P__ENC_UNDERFLOW_CONTEXT_1_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_CLR_P__ENC_UNDERFLOW_CONTEXT_1_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_CLR_P__ENC_UNDERFLOW_CONTEXT_1_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_CLR_P__RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_0_MASK 0x00000004U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_CLR_P__RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_0_SHIFT 2U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_CLR_P__RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_0_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_CLR_P__RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_0_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_CLR_P__RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_0_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_CLR_P__RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_1_MASK 0x00000008U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_CLR_P__RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_1_SHIFT 3U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_CLR_P__RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_1_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_CLR_P__RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_1_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_CLR_P__RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_1_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_CLR_P__CE_MASK 0x00000010U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_CLR_P__CE_SHIFT 4U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_CLR_P__CE_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_CLR_P__CE_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_CLR_P__CE_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_CLR_P__FRAME_STARTED_MASK 0x00000020U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_CLR_P__FRAME_STARTED_SHIFT 5U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_CLR_P__FRAME_STARTED_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_CLR_P__FRAME_STARTED_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_CLR_P__FRAME_STARTED_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_CLR_P__FRAME_DONE_MASK 0x00000040U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_CLR_P__FRAME_DONE_SHIFT 6U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_CLR_P__FRAME_DONE_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_CLR_P__FRAME_DONE_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_CLR_P__FRAME_DONE_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_CLR_P__OUT_BUFF_EMPTY_CONTEXT_0_MASK 0x00000080U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_CLR_P__OUT_BUFF_EMPTY_CONTEXT_0_SHIFT 7U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_CLR_P__OUT_BUFF_EMPTY_CONTEXT_0_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_CLR_P__OUT_BUFF_EMPTY_CONTEXT_0_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_CLR_P__OUT_BUFF_EMPTY_CONTEXT_0_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_CLR_P__OUT_BUFF_EMPTY_CONTEXT_1_MASK 0x00000100U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_CLR_P__OUT_BUFF_EMPTY_CONTEXT_1_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_CLR_P__OUT_BUFF_EMPTY_CONTEXT_1_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_CLR_P__OUT_BUFF_EMPTY_CONTEXT_1_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_CLR_P__OUT_BUFF_EMPTY_CONTEXT_1_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_CLR_P__OUT_BUFF_FULL_CONTEXT_0_MASK 0x00000200U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_CLR_P__OUT_BUFF_FULL_CONTEXT_0_SHIFT 9U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_CLR_P__OUT_BUFF_FULL_CONTEXT_0_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_CLR_P__OUT_BUFF_FULL_CONTEXT_0_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_CLR_P__OUT_BUFF_FULL_CONTEXT_0_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_CLR_P__OUT_BUFF_FULL_CONTEXT_1_MASK 0x00000400U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_CLR_P__OUT_BUFF_FULL_CONTEXT_1_SHIFT 10U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_CLR_P__OUT_BUFF_FULL_CONTEXT_1_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_CLR_P__OUT_BUFF_FULL_CONTEXT_1_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_CLR_P__OUT_BUFF_FULL_CONTEXT_1_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_CLR_P__RESERVED_0_MASK 0xFFFFF800U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_CLR_P__RESERVED_0_SHIFT 11U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_CLR_P__RESERVED_0_WIDTH 21U
+
+#define MHDP__MHDP_APB_REGS__ENC1_INT_MASK_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC1_INT_MASK_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC1_INT_MASK_P__ENC_UNDERFLOW_CONTEXT_0_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_MASK_P__ENC_UNDERFLOW_CONTEXT_0_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_MASK_P__ENC_UNDERFLOW_CONTEXT_0_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_MASK_P__ENC_UNDERFLOW_CONTEXT_0_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_MASK_P__ENC_UNDERFLOW_CONTEXT_0_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_MASK_P__ENC_UNDERFLOW_CONTEXT_1_MASK 0x00000002U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_MASK_P__ENC_UNDERFLOW_CONTEXT_1_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_MASK_P__ENC_UNDERFLOW_CONTEXT_1_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_MASK_P__ENC_UNDERFLOW_CONTEXT_1_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_MASK_P__ENC_UNDERFLOW_CONTEXT_1_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_MASK_P__RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_0_MASK 0x00000004U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_MASK_P__RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_0_SHIFT 2U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_MASK_P__RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_0_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_MASK_P__RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_0_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_MASK_P__RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_0_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_MASK_P__RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_1_MASK 0x00000008U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_MASK_P__RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_1_SHIFT 3U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_MASK_P__RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_1_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_MASK_P__RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_1_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_MASK_P__RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_1_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_MASK_P__CE_MASK 0x00000010U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_MASK_P__CE_SHIFT 4U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_MASK_P__CE_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_MASK_P__CE_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_MASK_P__CE_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_MASK_P__FRAME_STARTED_MASK 0x00000020U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_MASK_P__FRAME_STARTED_SHIFT 5U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_MASK_P__FRAME_STARTED_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_MASK_P__FRAME_STARTED_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_MASK_P__FRAME_STARTED_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_MASK_P__FRAME_DONE_MASK 0x00000040U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_MASK_P__FRAME_DONE_SHIFT 6U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_MASK_P__FRAME_DONE_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_MASK_P__FRAME_DONE_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_MASK_P__FRAME_DONE_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_MASK_P__OUT_BUFF_EMPTY_CONTEXT_0_MASK 0x00000080U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_MASK_P__OUT_BUFF_EMPTY_CONTEXT_0_SHIFT 7U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_MASK_P__OUT_BUFF_EMPTY_CONTEXT_0_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_MASK_P__OUT_BUFF_EMPTY_CONTEXT_0_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_MASK_P__OUT_BUFF_EMPTY_CONTEXT_0_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_MASK_P__OUT_BUFF_EMPTY_CONTEXT_1_MASK 0x00000100U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_MASK_P__OUT_BUFF_EMPTY_CONTEXT_1_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_MASK_P__OUT_BUFF_EMPTY_CONTEXT_1_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_MASK_P__OUT_BUFF_EMPTY_CONTEXT_1_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_MASK_P__OUT_BUFF_EMPTY_CONTEXT_1_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_MASK_P__OUT_BUFF_FULL_CONTEXT_0_MASK 0x00000200U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_MASK_P__OUT_BUFF_FULL_CONTEXT_0_SHIFT 9U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_MASK_P__OUT_BUFF_FULL_CONTEXT_0_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_MASK_P__OUT_BUFF_FULL_CONTEXT_0_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_MASK_P__OUT_BUFF_FULL_CONTEXT_0_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_MASK_P__OUT_BUFF_FULL_CONTEXT_1_MASK 0x00000400U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_MASK_P__OUT_BUFF_FULL_CONTEXT_1_SHIFT 10U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_MASK_P__OUT_BUFF_FULL_CONTEXT_1_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_MASK_P__OUT_BUFF_FULL_CONTEXT_1_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_MASK_P__OUT_BUFF_FULL_CONTEXT_1_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_MASK_P__RESERVED_0_MASK 0xFFFFF800U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_MASK_P__RESERVED_0_SHIFT 11U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_MASK_P__RESERVED_0_WIDTH 21U
+
+#define MHDP__MHDP_APB_REGS__ENC1_INT_TEST_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC1_INT_TEST_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC1_INT_TEST_P__ENC_UNDERFLOW_CONTEXT_0_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_TEST_P__ENC_UNDERFLOW_CONTEXT_0_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_TEST_P__ENC_UNDERFLOW_CONTEXT_0_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_TEST_P__ENC_UNDERFLOW_CONTEXT_0_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_TEST_P__ENC_UNDERFLOW_CONTEXT_0_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_TEST_P__ENC_UNDERFLOW_CONTEXT_1_MASK 0x00000002U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_TEST_P__ENC_UNDERFLOW_CONTEXT_1_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_TEST_P__ENC_UNDERFLOW_CONTEXT_1_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_TEST_P__ENC_UNDERFLOW_CONTEXT_1_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_TEST_P__ENC_UNDERFLOW_CONTEXT_1_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_TEST_P__RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_0_MASK 0x00000004U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_TEST_P__RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_0_SHIFT 2U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_TEST_P__RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_0_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_TEST_P__RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_0_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_TEST_P__RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_0_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_TEST_P__RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_1_MASK 0x00000008U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_TEST_P__RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_1_SHIFT 3U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_TEST_P__RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_1_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_TEST_P__RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_1_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_TEST_P__RC_MODEL_BUFFER_FULLNESS_OVERFLOW_CONTEXT_1_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_TEST_P__CE_MASK 0x00000010U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_TEST_P__CE_SHIFT 4U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_TEST_P__CE_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_TEST_P__CE_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_TEST_P__CE_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_TEST_P__FRAME_STARTED_MASK 0x00000020U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_TEST_P__FRAME_STARTED_SHIFT 5U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_TEST_P__FRAME_STARTED_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_TEST_P__FRAME_STARTED_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_TEST_P__FRAME_STARTED_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_TEST_P__FRAME_DONE_MASK 0x00000040U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_TEST_P__FRAME_DONE_SHIFT 6U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_TEST_P__FRAME_DONE_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_TEST_P__FRAME_DONE_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_TEST_P__FRAME_DONE_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_TEST_P__OUT_BUFF_EMPTY_CONTEXT_0_MASK 0x00000080U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_TEST_P__OUT_BUFF_EMPTY_CONTEXT_0_SHIFT 7U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_TEST_P__OUT_BUFF_EMPTY_CONTEXT_0_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_TEST_P__OUT_BUFF_EMPTY_CONTEXT_0_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_TEST_P__OUT_BUFF_EMPTY_CONTEXT_0_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_TEST_P__OUT_BUFF_EMPTY_CONTEXT_1_MASK 0x00000100U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_TEST_P__OUT_BUFF_EMPTY_CONTEXT_1_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_TEST_P__OUT_BUFF_EMPTY_CONTEXT_1_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_TEST_P__OUT_BUFF_EMPTY_CONTEXT_1_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_TEST_P__OUT_BUFF_EMPTY_CONTEXT_1_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_TEST_P__OUT_BUFF_FULL_CONTEXT_0_MASK 0x00000200U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_TEST_P__OUT_BUFF_FULL_CONTEXT_0_SHIFT 9U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_TEST_P__OUT_BUFF_FULL_CONTEXT_0_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_TEST_P__OUT_BUFF_FULL_CONTEXT_0_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_TEST_P__OUT_BUFF_FULL_CONTEXT_0_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_TEST_P__OUT_BUFF_FULL_CONTEXT_1_MASK 0x00000400U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_TEST_P__OUT_BUFF_FULL_CONTEXT_1_SHIFT 10U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_TEST_P__OUT_BUFF_FULL_CONTEXT_1_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_TEST_P__OUT_BUFF_FULL_CONTEXT_1_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_TEST_P__OUT_BUFF_FULL_CONTEXT_1_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_TEST_P__RESERVED_0_MASK 0xFFFFF800U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_TEST_P__RESERVED_0_SHIFT 11U
+#define MHDP__MHDP_APB_REGS__ENC1_INT_TEST_P__RESERVED_0_WIDTH 21U
+
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_STAT_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_STAT_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_STAT_P__ENC0_ASF_SRAM_CORR_ERR_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_STAT_P__ENC0_ASF_SRAM_CORR_ERR_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_STAT_P__ENC0_ASF_SRAM_CORR_ERR_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_STAT_P__ENC0_ASF_SRAM_CORR_ERR_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_STAT_P__ENC0_ASF_SRAM_CORR_ERR_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_STAT_P__ENC0_ASF_SRAM_UNCORR_ERR_MASK 0x00000002U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_STAT_P__ENC0_ASF_SRAM_UNCORR_ERR_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_STAT_P__ENC0_ASF_SRAM_UNCORR_ERR_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_STAT_P__ENC0_ASF_SRAM_UNCORR_ERR_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_STAT_P__ENC0_ASF_SRAM_UNCORR_ERR_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_STAT_P__ENC0_OUT_CHK_ERR_MASK 0x00000004U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_STAT_P__ENC0_OUT_CHK_ERR_SHIFT 2U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_STAT_P__ENC0_OUT_CHK_ERR_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_STAT_P__ENC0_OUT_CHK_ERR_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_STAT_P__ENC0_OUT_CHK_ERR_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_STAT_P__ENC0_SELF_CHK_ERR_MASK 0x00000008U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_STAT_P__ENC0_SELF_CHK_ERR_SHIFT 3U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_STAT_P__ENC0_SELF_CHK_ERR_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_STAT_P__ENC0_SELF_CHK_ERR_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_STAT_P__ENC0_SELF_CHK_ERR_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_STAT_P__ENC1_ASF_SRAM_CORR_ERR_MASK 0x00000010U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_STAT_P__ENC1_ASF_SRAM_CORR_ERR_SHIFT 4U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_STAT_P__ENC1_ASF_SRAM_CORR_ERR_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_STAT_P__ENC1_ASF_SRAM_CORR_ERR_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_STAT_P__ENC1_ASF_SRAM_CORR_ERR_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_STAT_P__ENC1_ASF_SRAM_UNCORR_ERR_MASK 0x00000020U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_STAT_P__ENC1_ASF_SRAM_UNCORR_ERR_SHIFT 5U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_STAT_P__ENC1_ASF_SRAM_UNCORR_ERR_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_STAT_P__ENC1_ASF_SRAM_UNCORR_ERR_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_STAT_P__ENC1_ASF_SRAM_UNCORR_ERR_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_STAT_P__ENC1_OUT_CHK_ERR_MASK 0x00000040U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_STAT_P__ENC1_OUT_CHK_ERR_SHIFT 6U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_STAT_P__ENC1_OUT_CHK_ERR_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_STAT_P__ENC1_OUT_CHK_ERR_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_STAT_P__ENC1_OUT_CHK_ERR_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_STAT_P__ENC1_SELF_CHK_ERR_MASK 0x00000080U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_STAT_P__ENC1_SELF_CHK_ERR_SHIFT 7U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_STAT_P__ENC1_SELF_CHK_ERR_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_STAT_P__ENC1_SELF_CHK_ERR_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_STAT_P__ENC1_SELF_CHK_ERR_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_STAT_P__ASF_CSR_ERR_MASK 0x00000100U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_STAT_P__ASF_CSR_ERR_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_STAT_P__ASF_CSR_ERR_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_STAT_P__ASF_CSR_ERR_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_STAT_P__ASF_CSR_ERR_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_STAT_P__RESERVED_0_MASK 0xFFFFFE00U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_STAT_P__RESERVED_0_SHIFT 9U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_STAT_P__RESERVED_0_WIDTH 23U
+
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_MASK_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_MASK_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_MASK_P__ENC0_ASF_SRAM_CORR_ERR_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_MASK_P__ENC0_ASF_SRAM_CORR_ERR_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_MASK_P__ENC0_ASF_SRAM_CORR_ERR_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_MASK_P__ENC0_ASF_SRAM_CORR_ERR_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_MASK_P__ENC0_ASF_SRAM_CORR_ERR_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_MASK_P__ENC0_ASF_SRAM_UNCORR_ERR_MASK 0x00000002U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_MASK_P__ENC0_ASF_SRAM_UNCORR_ERR_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_MASK_P__ENC0_ASF_SRAM_UNCORR_ERR_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_MASK_P__ENC0_ASF_SRAM_UNCORR_ERR_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_MASK_P__ENC0_ASF_SRAM_UNCORR_ERR_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_MASK_P__ENC0_OUT_CHK_ERR_MASK 0x00000004U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_MASK_P__ENC0_OUT_CHK_ERR_SHIFT 2U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_MASK_P__ENC0_OUT_CHK_ERR_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_MASK_P__ENC0_OUT_CHK_ERR_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_MASK_P__ENC0_OUT_CHK_ERR_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_MASK_P__ENC0_SELF_CHK_ERR_MASK 0x00000008U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_MASK_P__ENC0_SELF_CHK_ERR_SHIFT 3U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_MASK_P__ENC0_SELF_CHK_ERR_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_MASK_P__ENC0_SELF_CHK_ERR_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_MASK_P__ENC0_SELF_CHK_ERR_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_MASK_P__ENC1_ASF_SRAM_CORR_ERR_MASK 0x00000010U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_MASK_P__ENC1_ASF_SRAM_CORR_ERR_SHIFT 4U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_MASK_P__ENC1_ASF_SRAM_CORR_ERR_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_MASK_P__ENC1_ASF_SRAM_CORR_ERR_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_MASK_P__ENC1_ASF_SRAM_CORR_ERR_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_MASK_P__ENC1_ASF_SRAM_UNCORR_ERR_MASK 0x00000020U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_MASK_P__ENC1_ASF_SRAM_UNCORR_ERR_SHIFT 5U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_MASK_P__ENC1_ASF_SRAM_UNCORR_ERR_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_MASK_P__ENC1_ASF_SRAM_UNCORR_ERR_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_MASK_P__ENC1_ASF_SRAM_UNCORR_ERR_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_MASK_P__ENC1_OUT_CHK_ERR_MASK 0x00000040U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_MASK_P__ENC1_OUT_CHK_ERR_SHIFT 6U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_MASK_P__ENC1_OUT_CHK_ERR_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_MASK_P__ENC1_OUT_CHK_ERR_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_MASK_P__ENC1_OUT_CHK_ERR_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_MASK_P__ENC1_SELF_CHK_ERR_MASK 0x00000080U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_MASK_P__ENC1_SELF_CHK_ERR_SHIFT 7U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_MASK_P__ENC1_SELF_CHK_ERR_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_MASK_P__ENC1_SELF_CHK_ERR_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_MASK_P__ENC1_SELF_CHK_ERR_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_MASK_P__ASF_CSR_ERR_MASK 0x00000100U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_MASK_P__ASF_CSR_ERR_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_MASK_P__ASF_CSR_ERR_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_MASK_P__ASF_CSR_ERR_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_MASK_P__ASF_CSR_ERR_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_MASK_P__RESERVED_0_MASK 0xFFFFFE00U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_MASK_P__RESERVED_0_SHIFT 9U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_MASK_P__RESERVED_0_WIDTH 23U
+
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_CLR_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_CLR_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_CLR_P__ENC0_ASF_SRAM_CORR_ERR_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_CLR_P__ENC0_ASF_SRAM_CORR_ERR_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_CLR_P__ENC0_ASF_SRAM_CORR_ERR_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_CLR_P__ENC0_ASF_SRAM_CORR_ERR_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_CLR_P__ENC0_ASF_SRAM_CORR_ERR_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_CLR_P__ENC0_ASF_SRAM_UNCORR_ERR_MASK 0x00000002U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_CLR_P__ENC0_ASF_SRAM_UNCORR_ERR_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_CLR_P__ENC0_ASF_SRAM_UNCORR_ERR_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_CLR_P__ENC0_ASF_SRAM_UNCORR_ERR_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_CLR_P__ENC0_ASF_SRAM_UNCORR_ERR_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_CLR_P__ENC0_OUT_CHK_ERR_MASK 0x00000004U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_CLR_P__ENC0_OUT_CHK_ERR_SHIFT 2U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_CLR_P__ENC0_OUT_CHK_ERR_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_CLR_P__ENC0_OUT_CHK_ERR_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_CLR_P__ENC0_OUT_CHK_ERR_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_CLR_P__ENC0_SELF_CHK_ERR_MASK 0x00000008U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_CLR_P__ENC0_SELF_CHK_ERR_SHIFT 3U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_CLR_P__ENC0_SELF_CHK_ERR_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_CLR_P__ENC0_SELF_CHK_ERR_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_CLR_P__ENC0_SELF_CHK_ERR_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_CLR_P__ENC1_ASF_SRAM_CORR_ERR_MASK 0x00000010U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_CLR_P__ENC1_ASF_SRAM_CORR_ERR_SHIFT 4U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_CLR_P__ENC1_ASF_SRAM_CORR_ERR_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_CLR_P__ENC1_ASF_SRAM_CORR_ERR_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_CLR_P__ENC1_ASF_SRAM_CORR_ERR_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_CLR_P__ENC1_ASF_SRAM_UNCORR_ERR_MASK 0x00000020U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_CLR_P__ENC1_ASF_SRAM_UNCORR_ERR_SHIFT 5U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_CLR_P__ENC1_ASF_SRAM_UNCORR_ERR_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_CLR_P__ENC1_ASF_SRAM_UNCORR_ERR_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_CLR_P__ENC1_ASF_SRAM_UNCORR_ERR_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_CLR_P__ENC1_OUT_CHK_ERR_MASK 0x00000040U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_CLR_P__ENC1_OUT_CHK_ERR_SHIFT 6U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_CLR_P__ENC1_OUT_CHK_ERR_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_CLR_P__ENC1_OUT_CHK_ERR_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_CLR_P__ENC1_OUT_CHK_ERR_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_CLR_P__ENC1_SELF_CHK_ERR_MASK 0x00000080U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_CLR_P__ENC1_SELF_CHK_ERR_SHIFT 7U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_CLR_P__ENC1_SELF_CHK_ERR_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_CLR_P__ENC1_SELF_CHK_ERR_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_CLR_P__ENC1_SELF_CHK_ERR_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_CLR_P__ASF_CSR_ERR_MASK 0x00000100U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_CLR_P__ASF_CSR_ERR_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_CLR_P__ASF_CSR_ERR_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_CLR_P__ASF_CSR_ERR_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_CLR_P__ASF_CSR_ERR_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_CLR_P__RESERVED_0_MASK 0xFFFFFE00U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_CLR_P__RESERVED_0_SHIFT 9U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_CLR_P__RESERVED_0_WIDTH 23U
+
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_TEST_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_TEST_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_TEST_P__ENC0_ASF_SRAM_CORR_ERR_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_TEST_P__ENC0_ASF_SRAM_CORR_ERR_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_TEST_P__ENC0_ASF_SRAM_CORR_ERR_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_TEST_P__ENC0_ASF_SRAM_CORR_ERR_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_TEST_P__ENC0_ASF_SRAM_CORR_ERR_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_TEST_P__ENC0_ASF_SRAM_UNCORR_ERR_MASK 0x00000002U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_TEST_P__ENC0_ASF_SRAM_UNCORR_ERR_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_TEST_P__ENC0_ASF_SRAM_UNCORR_ERR_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_TEST_P__ENC0_ASF_SRAM_UNCORR_ERR_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_TEST_P__ENC0_ASF_SRAM_UNCORR_ERR_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_TEST_P__ENC0_OUT_CHK_ERR_MASK 0x00000004U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_TEST_P__ENC0_OUT_CHK_ERR_SHIFT 2U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_TEST_P__ENC0_OUT_CHK_ERR_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_TEST_P__ENC0_OUT_CHK_ERR_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_TEST_P__ENC0_OUT_CHK_ERR_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_TEST_P__ENC0_SELF_CHK_ERR_MASK 0x00000008U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_TEST_P__ENC0_SELF_CHK_ERR_SHIFT 3U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_TEST_P__ENC0_SELF_CHK_ERR_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_TEST_P__ENC0_SELF_CHK_ERR_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_TEST_P__ENC0_SELF_CHK_ERR_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_TEST_P__ENC1_ASF_SRAM_CORR_ERR_MASK 0x00000010U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_TEST_P__ENC1_ASF_SRAM_CORR_ERR_SHIFT 4U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_TEST_P__ENC1_ASF_SRAM_CORR_ERR_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_TEST_P__ENC1_ASF_SRAM_CORR_ERR_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_TEST_P__ENC1_ASF_SRAM_CORR_ERR_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_TEST_P__ENC1_ASF_SRAM_UNCORR_ERR_MASK 0x00000020U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_TEST_P__ENC1_ASF_SRAM_UNCORR_ERR_SHIFT 5U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_TEST_P__ENC1_ASF_SRAM_UNCORR_ERR_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_TEST_P__ENC1_ASF_SRAM_UNCORR_ERR_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_TEST_P__ENC1_ASF_SRAM_UNCORR_ERR_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_TEST_P__ENC1_OUT_CHK_ERR_MASK 0x00000040U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_TEST_P__ENC1_OUT_CHK_ERR_SHIFT 6U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_TEST_P__ENC1_OUT_CHK_ERR_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_TEST_P__ENC1_OUT_CHK_ERR_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_TEST_P__ENC1_OUT_CHK_ERR_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_TEST_P__ENC1_SELF_CHK_ERR_MASK 0x00000080U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_TEST_P__ENC1_SELF_CHK_ERR_SHIFT 7U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_TEST_P__ENC1_SELF_CHK_ERR_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_TEST_P__ENC1_SELF_CHK_ERR_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_TEST_P__ENC1_SELF_CHK_ERR_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_TEST_P__ASF_CSR_ERR_MASK 0x00000100U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_TEST_P__ASF_CSR_ERR_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_TEST_P__ASF_CSR_ERR_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_TEST_P__ASF_CSR_ERR_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_TEST_P__ASF_CSR_ERR_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_TEST_P__RESERVED_0_MASK 0xFFFFFE00U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_TEST_P__RESERVED_0_SHIFT 9U
+#define MHDP__MHDP_APB_REGS__ENC_ASF_INT_TEST_P__RESERVED_0_WIDTH 23U
+
+#define MHDP__MHDP_APB_REGS__ENC0_ASF_SRAM_CORR_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC0_ASF_SRAM_CORR_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC0_ASF_SRAM_CORR_P__ASF_SRAM_CORR_FAULT_ADDR_MASK 0x00FFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC0_ASF_SRAM_CORR_P__ASF_SRAM_CORR_FAULT_ADDR_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__ENC0_ASF_SRAM_CORR_P__ASF_SRAM_CORR_FAULT_ADDR_WIDTH 24U
+#define MHDP__MHDP_APB_REGS__ENC0_ASF_SRAM_CORR_P__ASF_SRAM_CORR_FAULT_INST_MASK 0x03000000U
+#define MHDP__MHDP_APB_REGS__ENC0_ASF_SRAM_CORR_P__ASF_SRAM_CORR_FAULT_INST_SHIFT 24U
+#define MHDP__MHDP_APB_REGS__ENC0_ASF_SRAM_CORR_P__ASF_SRAM_CORR_FAULT_INST_WIDTH 2U
+#define MHDP__MHDP_APB_REGS__ENC0_ASF_SRAM_CORR_P__RESERVED_0_MASK 0xFC000000U
+#define MHDP__MHDP_APB_REGS__ENC0_ASF_SRAM_CORR_P__RESERVED_0_SHIFT 26U
+#define MHDP__MHDP_APB_REGS__ENC0_ASF_SRAM_CORR_P__RESERVED_0_WIDTH 6U
+
+#define MHDP__MHDP_APB_REGS__ENC0_ASF_SRAM_UNCORR_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC0_ASF_SRAM_UNCORR_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC0_ASF_SRAM_UNCORR_P__ASF_SRAM_UNCORR_FAULT_ADDR_MASK 0x00FFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC0_ASF_SRAM_UNCORR_P__ASF_SRAM_UNCORR_FAULT_ADDR_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__ENC0_ASF_SRAM_UNCORR_P__ASF_SRAM_UNCORR_FAULT_ADDR_WIDTH 24U
+#define MHDP__MHDP_APB_REGS__ENC0_ASF_SRAM_UNCORR_P__ASF_SRAM_UNCORR_FAULT_INST_MASK 0x03000000U
+#define MHDP__MHDP_APB_REGS__ENC0_ASF_SRAM_UNCORR_P__ASF_SRAM_UNCORR_FAULT_INST_SHIFT 24U
+#define MHDP__MHDP_APB_REGS__ENC0_ASF_SRAM_UNCORR_P__ASF_SRAM_UNCORR_FAULT_INST_WIDTH 2U
+#define MHDP__MHDP_APB_REGS__ENC0_ASF_SRAM_UNCORR_P__RESERVED_0_MASK 0xFC000000U
+#define MHDP__MHDP_APB_REGS__ENC0_ASF_SRAM_UNCORR_P__RESERVED_0_SHIFT 26U
+#define MHDP__MHDP_APB_REGS__ENC0_ASF_SRAM_UNCORR_P__RESERVED_0_WIDTH 6U
+
+#define MHDP__MHDP_APB_REGS__ENC1_ASF_SRAM_CORR_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC1_ASF_SRAM_CORR_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC1_ASF_SRAM_CORR_P__ASF_SRAM_CORR_FAULT_ADDR_MASK 0x00FFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC1_ASF_SRAM_CORR_P__ASF_SRAM_CORR_FAULT_ADDR_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__ENC1_ASF_SRAM_CORR_P__ASF_SRAM_CORR_FAULT_ADDR_WIDTH 24U
+#define MHDP__MHDP_APB_REGS__ENC1_ASF_SRAM_CORR_P__ASF_SRAM_CORR_FAULT_INST_MASK 0x03000000U
+#define MHDP__MHDP_APB_REGS__ENC1_ASF_SRAM_CORR_P__ASF_SRAM_CORR_FAULT_INST_SHIFT 24U
+#define MHDP__MHDP_APB_REGS__ENC1_ASF_SRAM_CORR_P__ASF_SRAM_CORR_FAULT_INST_WIDTH 2U
+#define MHDP__MHDP_APB_REGS__ENC1_ASF_SRAM_CORR_P__RESERVED_0_MASK 0xFC000000U
+#define MHDP__MHDP_APB_REGS__ENC1_ASF_SRAM_CORR_P__RESERVED_0_SHIFT 26U
+#define MHDP__MHDP_APB_REGS__ENC1_ASF_SRAM_CORR_P__RESERVED_0_WIDTH 6U
+
+#define MHDP__MHDP_APB_REGS__ENC1_ASF_SRAM_UNCORR_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC1_ASF_SRAM_UNCORR_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC1_ASF_SRAM_UNCORR_P__ASF_SRAM_UNCORR_FAULT_ADDR_MASK 0x00FFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC1_ASF_SRAM_UNCORR_P__ASF_SRAM_UNCORR_FAULT_ADDR_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__ENC1_ASF_SRAM_UNCORR_P__ASF_SRAM_UNCORR_FAULT_ADDR_WIDTH 24U
+#define MHDP__MHDP_APB_REGS__ENC1_ASF_SRAM_UNCORR_P__ASF_SRAM_UNCORR_FAULT_INST_MASK 0x03000000U
+#define MHDP__MHDP_APB_REGS__ENC1_ASF_SRAM_UNCORR_P__ASF_SRAM_UNCORR_FAULT_INST_SHIFT 24U
+#define MHDP__MHDP_APB_REGS__ENC1_ASF_SRAM_UNCORR_P__ASF_SRAM_UNCORR_FAULT_INST_WIDTH 2U
+#define MHDP__MHDP_APB_REGS__ENC1_ASF_SRAM_UNCORR_P__RESERVED_0_MASK 0xFC000000U
+#define MHDP__MHDP_APB_REGS__ENC1_ASF_SRAM_UNCORR_P__RESERVED_0_SHIFT 26U
+#define MHDP__MHDP_APB_REGS__ENC1_ASF_SRAM_UNCORR_P__RESERVED_0_WIDTH 6U
+
+#define MHDP__MHDP_APB_REGS__ENC0_ASF_CSR_CHK_TEST_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC0_ASF_CSR_CHK_TEST_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC0_ASF_CSR_CHK_TEST_P__ENC0_ASF_CSR_CHK_TEST_MASK 0x0000FFFFU
+#define MHDP__MHDP_APB_REGS__ENC0_ASF_CSR_CHK_TEST_P__ENC0_ASF_CSR_CHK_TEST_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__ENC0_ASF_CSR_CHK_TEST_P__ENC0_ASF_CSR_CHK_TEST_WIDTH 16U
+#define MHDP__MHDP_APB_REGS__ENC0_ASF_CSR_CHK_TEST_P__RESERVED_0_MASK 0xFFFF0000U
+#define MHDP__MHDP_APB_REGS__ENC0_ASF_CSR_CHK_TEST_P__RESERVED_0_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__ENC0_ASF_CSR_CHK_TEST_P__RESERVED_0_WIDTH 16U
+
+#define MHDP__MHDP_APB_REGS__ENC1_ASF_CSR_CHK_TEST_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC1_ASF_CSR_CHK_TEST_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC1_ASF_CSR_CHK_TEST_P__ENC1_ASF_CSR_CHK_TEST_MASK 0x0000FFFFU
+#define MHDP__MHDP_APB_REGS__ENC1_ASF_CSR_CHK_TEST_P__ENC1_ASF_CSR_CHK_TEST_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__ENC1_ASF_CSR_CHK_TEST_P__ENC1_ASF_CSR_CHK_TEST_WIDTH 16U
+#define MHDP__MHDP_APB_REGS__ENC1_ASF_CSR_CHK_TEST_P__RESERVED_0_MASK 0xFFFF0000U
+#define MHDP__MHDP_APB_REGS__ENC1_ASF_CSR_CHK_TEST_P__RESERVED_0_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__ENC1_ASF_CSR_CHK_TEST_P__RESERVED_0_WIDTH 16U
+
+#define MHDP__MHDP_APB_REGS__ENC0_ASF_SELF_CHK_TEST_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC0_ASF_SELF_CHK_TEST_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC0_ASF_SELF_CHK_TEST_P__ENC0_ASF_SELF_CHK_TEST_MASK 0x0000FFFFU
+#define MHDP__MHDP_APB_REGS__ENC0_ASF_SELF_CHK_TEST_P__ENC0_ASF_SELF_CHK_TEST_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__ENC0_ASF_SELF_CHK_TEST_P__ENC0_ASF_SELF_CHK_TEST_WIDTH 16U
+#define MHDP__MHDP_APB_REGS__ENC0_ASF_SELF_CHK_TEST_P__RESERVED_0_MASK 0xFFFF0000U
+#define MHDP__MHDP_APB_REGS__ENC0_ASF_SELF_CHK_TEST_P__RESERVED_0_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__ENC0_ASF_SELF_CHK_TEST_P__RESERVED_0_WIDTH 16U
+
+#define MHDP__MHDP_APB_REGS__ENC1_ASF_SELF_CHK_TEST_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC1_ASF_SELF_CHK_TEST_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC1_ASF_SELF_CHK_TEST_P__ENC1_ASF_SELF_CHK_TEST_MASK 0x0000FFFFU
+#define MHDP__MHDP_APB_REGS__ENC1_ASF_SELF_CHK_TEST_P__ENC1_ASF_SELF_CHK_TEST_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__ENC1_ASF_SELF_CHK_TEST_P__ENC1_ASF_SELF_CHK_TEST_WIDTH 16U
+#define MHDP__MHDP_APB_REGS__ENC1_ASF_SELF_CHK_TEST_P__RESERVED_0_MASK 0xFFFF0000U
+#define MHDP__MHDP_APB_REGS__ENC1_ASF_SELF_CHK_TEST_P__RESERVED_0_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__ENC1_ASF_SELF_CHK_TEST_P__RESERVED_0_WIDTH 16U
+
+#define MHDP__MHDP_APB_REGS__ENC0_ASF_OUT_CHK_TEST_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC0_ASF_OUT_CHK_TEST_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC0_ASF_OUT_CHK_TEST_P__BYTE_CNT_ERR_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__ENC0_ASF_OUT_CHK_TEST_P__BYTE_CNT_ERR_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__ENC0_ASF_OUT_CHK_TEST_P__BYTE_CNT_ERR_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC0_ASF_OUT_CHK_TEST_P__BYTE_CNT_ERR_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC0_ASF_OUT_CHK_TEST_P__BYTE_CNT_ERR_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC0_ASF_OUT_CHK_TEST_P__LINE_CNT_ERR_MASK 0x00000002U
+#define MHDP__MHDP_APB_REGS__ENC0_ASF_OUT_CHK_TEST_P__LINE_CNT_ERR_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__ENC0_ASF_OUT_CHK_TEST_P__LINE_CNT_ERR_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC0_ASF_OUT_CHK_TEST_P__LINE_CNT_ERR_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC0_ASF_OUT_CHK_TEST_P__LINE_CNT_ERR_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC0_ASF_OUT_CHK_TEST_P__NVB_VALUE_ERR_MASK 0x00000004U
+#define MHDP__MHDP_APB_REGS__ENC0_ASF_OUT_CHK_TEST_P__NVB_VALUE_ERR_SHIFT 2U
+#define MHDP__MHDP_APB_REGS__ENC0_ASF_OUT_CHK_TEST_P__NVB_VALUE_ERR_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC0_ASF_OUT_CHK_TEST_P__NVB_VALUE_ERR_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC0_ASF_OUT_CHK_TEST_P__NVB_VALUE_ERR_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC0_ASF_OUT_CHK_TEST_P__VALID_STUCK0_ERR_MASK 0x00000008U
+#define MHDP__MHDP_APB_REGS__ENC0_ASF_OUT_CHK_TEST_P__VALID_STUCK0_ERR_SHIFT 3U
+#define MHDP__MHDP_APB_REGS__ENC0_ASF_OUT_CHK_TEST_P__VALID_STUCK0_ERR_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC0_ASF_OUT_CHK_TEST_P__VALID_STUCK0_ERR_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC0_ASF_OUT_CHK_TEST_P__VALID_STUCK0_ERR_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC0_ASF_OUT_CHK_TEST_P__DATA_OUT_STUCK1_ERR_MASK 0x00000010U
+#define MHDP__MHDP_APB_REGS__ENC0_ASF_OUT_CHK_TEST_P__DATA_OUT_STUCK1_ERR_SHIFT 4U
+#define MHDP__MHDP_APB_REGS__ENC0_ASF_OUT_CHK_TEST_P__DATA_OUT_STUCK1_ERR_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC0_ASF_OUT_CHK_TEST_P__DATA_OUT_STUCK1_ERR_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC0_ASF_OUT_CHK_TEST_P__DATA_OUT_STUCK1_ERR_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC0_ASF_OUT_CHK_TEST_P__VALID_OUT_STUCK1_ERR_MASK 0x00000020U
+#define MHDP__MHDP_APB_REGS__ENC0_ASF_OUT_CHK_TEST_P__VALID_OUT_STUCK1_ERR_SHIFT 5U
+#define MHDP__MHDP_APB_REGS__ENC0_ASF_OUT_CHK_TEST_P__VALID_OUT_STUCK1_ERR_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC0_ASF_OUT_CHK_TEST_P__VALID_OUT_STUCK1_ERR_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC0_ASF_OUT_CHK_TEST_P__VALID_OUT_STUCK1_ERR_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC0_ASF_OUT_CHK_TEST_P__END_CHUNK_STUCK1_ERR_MASK 0x00000040U
+#define MHDP__MHDP_APB_REGS__ENC0_ASF_OUT_CHK_TEST_P__END_CHUNK_STUCK1_ERR_SHIFT 6U
+#define MHDP__MHDP_APB_REGS__ENC0_ASF_OUT_CHK_TEST_P__END_CHUNK_STUCK1_ERR_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC0_ASF_OUT_CHK_TEST_P__END_CHUNK_STUCK1_ERR_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC0_ASF_OUT_CHK_TEST_P__END_CHUNK_STUCK1_ERR_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC0_ASF_OUT_CHK_TEST_P__END_LINE_OUT_STUCK1_ERR_MASK 0x00000080U
+#define MHDP__MHDP_APB_REGS__ENC0_ASF_OUT_CHK_TEST_P__END_LINE_OUT_STUCK1_ERR_SHIFT 7U
+#define MHDP__MHDP_APB_REGS__ENC0_ASF_OUT_CHK_TEST_P__END_LINE_OUT_STUCK1_ERR_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC0_ASF_OUT_CHK_TEST_P__END_LINE_OUT_STUCK1_ERR_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC0_ASF_OUT_CHK_TEST_P__END_LINE_OUT_STUCK1_ERR_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC0_ASF_OUT_CHK_TEST_P__END_FRAME_OUT_STUCK1_ERR_MASK 0x00000100U
+#define MHDP__MHDP_APB_REGS__ENC0_ASF_OUT_CHK_TEST_P__END_FRAME_OUT_STUCK1_ERR_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__ENC0_ASF_OUT_CHK_TEST_P__END_FRAME_OUT_STUCK1_ERR_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC0_ASF_OUT_CHK_TEST_P__END_FRAME_OUT_STUCK1_ERR_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC0_ASF_OUT_CHK_TEST_P__END_FRAME_OUT_STUCK1_ERR_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC0_ASF_OUT_CHK_TEST_P__RESERVED0_MASK 0x0000FE00U
+#define MHDP__MHDP_APB_REGS__ENC0_ASF_OUT_CHK_TEST_P__RESERVED0_SHIFT 9U
+#define MHDP__MHDP_APB_REGS__ENC0_ASF_OUT_CHK_TEST_P__RESERVED0_WIDTH 7U
+#define MHDP__MHDP_APB_REGS__ENC0_ASF_OUT_CHK_TEST_P__RESERVED1_MASK 0xFFFF0000U
+#define MHDP__MHDP_APB_REGS__ENC0_ASF_OUT_CHK_TEST_P__RESERVED1_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__ENC0_ASF_OUT_CHK_TEST_P__RESERVED1_WIDTH 16U
+
+#define MHDP__MHDP_APB_REGS__ENC1_ASF_OUT_CHK_TEST_P_READ_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC1_ASF_OUT_CHK_TEST_P_WRITE_MASK 0xFFFFFFFFU
+#define MHDP__MHDP_APB_REGS__ENC1_ASF_OUT_CHK_TEST_P__BYTE_CNT_ERR_MASK 0x00000001U
+#define MHDP__MHDP_APB_REGS__ENC1_ASF_OUT_CHK_TEST_P__BYTE_CNT_ERR_SHIFT 0U
+#define MHDP__MHDP_APB_REGS__ENC1_ASF_OUT_CHK_TEST_P__BYTE_CNT_ERR_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC1_ASF_OUT_CHK_TEST_P__BYTE_CNT_ERR_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC1_ASF_OUT_CHK_TEST_P__BYTE_CNT_ERR_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC1_ASF_OUT_CHK_TEST_P__LINE_CNT_ERR_MASK 0x00000002U
+#define MHDP__MHDP_APB_REGS__ENC1_ASF_OUT_CHK_TEST_P__LINE_CNT_ERR_SHIFT 1U
+#define MHDP__MHDP_APB_REGS__ENC1_ASF_OUT_CHK_TEST_P__LINE_CNT_ERR_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC1_ASF_OUT_CHK_TEST_P__LINE_CNT_ERR_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC1_ASF_OUT_CHK_TEST_P__LINE_CNT_ERR_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC1_ASF_OUT_CHK_TEST_P__NVB_VALUE_ERR_MASK 0x00000004U
+#define MHDP__MHDP_APB_REGS__ENC1_ASF_OUT_CHK_TEST_P__NVB_VALUE_ERR_SHIFT 2U
+#define MHDP__MHDP_APB_REGS__ENC1_ASF_OUT_CHK_TEST_P__NVB_VALUE_ERR_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC1_ASF_OUT_CHK_TEST_P__NVB_VALUE_ERR_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC1_ASF_OUT_CHK_TEST_P__NVB_VALUE_ERR_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC1_ASF_OUT_CHK_TEST_P__VALID_STUCK0_ERR_MASK 0x00000008U
+#define MHDP__MHDP_APB_REGS__ENC1_ASF_OUT_CHK_TEST_P__VALID_STUCK0_ERR_SHIFT 3U
+#define MHDP__MHDP_APB_REGS__ENC1_ASF_OUT_CHK_TEST_P__VALID_STUCK0_ERR_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC1_ASF_OUT_CHK_TEST_P__VALID_STUCK0_ERR_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC1_ASF_OUT_CHK_TEST_P__VALID_STUCK0_ERR_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC1_ASF_OUT_CHK_TEST_P__DATA_OUT_STUCK1_ERR_MASK 0x00000010U
+#define MHDP__MHDP_APB_REGS__ENC1_ASF_OUT_CHK_TEST_P__DATA_OUT_STUCK1_ERR_SHIFT 4U
+#define MHDP__MHDP_APB_REGS__ENC1_ASF_OUT_CHK_TEST_P__DATA_OUT_STUCK1_ERR_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC1_ASF_OUT_CHK_TEST_P__DATA_OUT_STUCK1_ERR_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC1_ASF_OUT_CHK_TEST_P__DATA_OUT_STUCK1_ERR_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC1_ASF_OUT_CHK_TEST_P__VALID_OUT_STUCK1_ERR_MASK 0x00000020U
+#define MHDP__MHDP_APB_REGS__ENC1_ASF_OUT_CHK_TEST_P__VALID_OUT_STUCK1_ERR_SHIFT 5U
+#define MHDP__MHDP_APB_REGS__ENC1_ASF_OUT_CHK_TEST_P__VALID_OUT_STUCK1_ERR_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC1_ASF_OUT_CHK_TEST_P__VALID_OUT_STUCK1_ERR_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC1_ASF_OUT_CHK_TEST_P__VALID_OUT_STUCK1_ERR_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC1_ASF_OUT_CHK_TEST_P__END_CHUNK_STUCK1_ERR_MASK 0x00000040U
+#define MHDP__MHDP_APB_REGS__ENC1_ASF_OUT_CHK_TEST_P__END_CHUNK_STUCK1_ERR_SHIFT 6U
+#define MHDP__MHDP_APB_REGS__ENC1_ASF_OUT_CHK_TEST_P__END_CHUNK_STUCK1_ERR_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC1_ASF_OUT_CHK_TEST_P__END_CHUNK_STUCK1_ERR_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC1_ASF_OUT_CHK_TEST_P__END_CHUNK_STUCK1_ERR_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC1_ASF_OUT_CHK_TEST_P__END_LINE_OUT_STUCK1_ERR_MASK 0x00000080U
+#define MHDP__MHDP_APB_REGS__ENC1_ASF_OUT_CHK_TEST_P__END_LINE_OUT_STUCK1_ERR_SHIFT 7U
+#define MHDP__MHDP_APB_REGS__ENC1_ASF_OUT_CHK_TEST_P__END_LINE_OUT_STUCK1_ERR_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC1_ASF_OUT_CHK_TEST_P__END_LINE_OUT_STUCK1_ERR_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC1_ASF_OUT_CHK_TEST_P__END_LINE_OUT_STUCK1_ERR_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC1_ASF_OUT_CHK_TEST_P__END_FRAME_OUT_STUCK1_ERR_MASK 0x00000100U
+#define MHDP__MHDP_APB_REGS__ENC1_ASF_OUT_CHK_TEST_P__END_FRAME_OUT_STUCK1_ERR_SHIFT 8U
+#define MHDP__MHDP_APB_REGS__ENC1_ASF_OUT_CHK_TEST_P__END_FRAME_OUT_STUCK1_ERR_WIDTH 1U
+#define MHDP__MHDP_APB_REGS__ENC1_ASF_OUT_CHK_TEST_P__END_FRAME_OUT_STUCK1_ERR_WOCLR 0U
+#define MHDP__MHDP_APB_REGS__ENC1_ASF_OUT_CHK_TEST_P__END_FRAME_OUT_STUCK1_ERR_WOSET 0U
+#define MHDP__MHDP_APB_REGS__ENC1_ASF_OUT_CHK_TEST_P__RESERVED0_MASK 0x0000FE00U
+#define MHDP__MHDP_APB_REGS__ENC1_ASF_OUT_CHK_TEST_P__RESERVED0_SHIFT 9U
+#define MHDP__MHDP_APB_REGS__ENC1_ASF_OUT_CHK_TEST_P__RESERVED0_WIDTH 7U
+#define MHDP__MHDP_APB_REGS__ENC1_ASF_OUT_CHK_TEST_P__RESERVED1_MASK 0xFFFF0000U
+#define MHDP__MHDP_APB_REGS__ENC1_ASF_OUT_CHK_TEST_P__RESERVED1_SHIFT 16U
+#define MHDP__MHDP_APB_REGS__ENC1_ASF_OUT_CHK_TEST_P__RESERVED1_WIDTH 16U
+
+#endif /* REG_MHDP_APB_REGS_MACROS_H_ */
+
+/* parasoft-end-suppress MISRA2012-RULE-5_4_b_c99-2 "C99 - similar names, DRV-4756" */
+/* parasoft-end-suppress MISRA2012-RULE-5_4_b_c90-2 "C90 - similar names, DRV-4756" */
+/* parasoft-end-suppress MISRA2012-RULE-1_1_b_c99-2 "C99 - limits, DRV-4754" */
+/* parasoft-end-suppress MISRA2012-RULE-1_1_b_c90-2 "C90 - limits, DRV-4754" */
+
diff --git a/packages/ti/drv/dss/src/csl/dp/src/src_files_dp.mk b/packages/ti/drv/dss/src/csl/dp/src/src_files_dp.mk
--- /dev/null
@@ -0,0 +1,5 @@
+SRCDIR += src/csl/dp/src
+INCDIR += src/csl/dp/include src/csl/dp/src
+SRCS_COMMON += dp_aux.c dp_dsc.c dp_hdcp.c dp_if.c dp_link_policy.c dp_mailbox.c dp_mst.c dp_register.c \
+ dp_sanity.c dp_sdp.c dp_sideband_msg.c dp_topology_mgr.c dp_topology_utils.c dp_transaction.c \
+ dp_utils.c dsc_utils.c
diff --git a/packages/ti/drv/dss/src/csl/dp_sd0801/csl_dp_sd0801.h b/packages/ti/drv/dss/src/csl/dp_sd0801/csl_dp_sd0801.h
--- /dev/null
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) Texas Instruments Incorporated 2018
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+/**
+ * \file csl_dp_sd0801.h
+ *
+ * \brief CSL APIs for Torrent PHY.
+ */
+
+#ifndef CSL_DP_SD0801_H_
+#define CSL_DP_SD0801_H_
+
+#include <src/csl/dp_sd0801/include/dp_sd0801_if.h>
+#include <src/csl/dp_sd0801/include/dp_sd0801_structs_if.h>
+
+#endif
diff --git a/packages/ti/drv/dss/src/csl/dp_sd0801/include/dp_sd0801_if.h b/packages/ti/drv/dss/src/csl/dp_sd0801/include/dp_sd0801_if.h
--- /dev/null
@@ -0,0 +1,315 @@
+/**********************************************************************
+* Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* 1. Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* 2. Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the distribution.
+* 3. Neither the name of the copyright holder nor the names of its
+* contributors may be used to endorse or promote products derived from
+* this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+**********************************************************************
+* WARNING: This file is auto-generated using api-generator utility.
+* api-generator: 12.03.9e11b77(origin/DRV-3827_extract_sanity_to_c_file)
+* Do not edit it manually.
+**********************************************************************
+* Cadence Core Driver for the Cadence DP_SD0801 PHY for DisplayPort (DP)
+* core. This header file lists the API providing a HAL (hardware
+* abstraction layer) interface for the DP_SD0801 "Torrent" core.
+**********************************************************************/
+
+#ifndef DP_SD0801_IF_H
+#define DP_SD0801_IF_H
+
+/* parasoft-begin-suppress MISRA2012-RULE-1_1_a_c90-2 "C90 - limits, DRV-3906" */
+/* parasoft-begin-suppress MISRA2012-RULE-1_1_b_c90-2 "C90 - limits, DRV-3906" */
+
+#include "cdn_errno.h"
+#include "cdn_stdtypes.h"
+
+/** @defgroup ConfigInfo Configuration and Hardware Operation Information
+ * The following definitions specify the driver operation environment that
+ * is defined by hardware configuration or client code. These defines are
+ * located in the header file of the core driver.
+ * @{
+ */
+
+/**********************************************************************
+* Defines
+**********************************************************************/
+/** Number of voltage swing levels. */
+#define DP_SD0801_SWING_LEVEL_COUNT 4U
+
+/** Number of pre-emphasis levels. */
+#define DP_SD0801_EMPHASIS_LEVEL_COUNT 4U
+
+#define DP_SD0801_MAX_LANE_COUNT (4U)
+
+/**
+ * @}
+ */
+
+/** @defgroup DataStructure Dynamic Data Structures
+ * This section defines the data structures used by the driver to provide
+ * hardware information, modification and dynamic operation of the driver.
+ * These data structures are defined in the header file of the core driver
+ * and utilized by the API.
+ * @{
+ */
+
+/**********************************************************************
+* Forward declarations
+**********************************************************************/
+typedef struct DP_SD0801_VoltageCoefficients_s DP_SD0801_VoltageCoefficients;
+typedef struct DP_SD0801_LinkState_s DP_SD0801_LinkState;
+typedef struct DP_SD0801_Config_s DP_SD0801_Config;
+
+typedef struct DP_SD0801_PrivateData_s DP_SD0801_PrivateData;
+
+/**********************************************************************
+* Enumerations
+**********************************************************************/
+typedef enum
+{
+ DP_SD0801_LINK_RATE_1_62 = 0x00U,
+ DP_SD0801_LINK_RATE_2_16 = 0x01U,
+ DP_SD0801_LINK_RATE_2_43 = 0x02U,
+ DP_SD0801_LINK_RATE_2_70 = 0x03U,
+ DP_SD0801_LINK_RATE_3_24 = 0x04U,
+ DP_SD0801_LINK_RATE_4_32 = 0x05U,
+ DP_SD0801_LINK_RATE_5_40 = 0x06U,
+ DP_SD0801_LINK_RATE_8_10 = 0x07U
+} DP_SD0801_LinkRate;
+
+/** Specifies, how physical PHY lanes are mapped to ports of receiver(s) */
+typedef enum
+{
+ /** Single controller is used. Lanes are not crossed (0->0, 1->1, 2->2, 3->3). */
+ DP_SD0801_LANE_MAPPING_REGULAR_SINGLE = 0xE4U,
+ /**
+ * Up to two controllers are used with a PHY. Currently configured
+ * controller uses only up to 2 lanes: lane 0 and lane 1. (0->0, 1->1)
+ */
+ DP_SD0801_LANE_MAPPING_LANES_01_DUAL = 0x04U,
+ /**
+ * Up to two controllers are used with a PHY. Currently configured
+ * controller uses only up to 2 lanes: lane 2 and lane 3. (0->2, 1->3)
+ */
+ DP_SD0801_LANE_MAPPING_LANES_23_DUAL = 0x0EU
+} DP_SD0801_LaneMapping;
+
+/** Number of controllers per PHY. */
+typedef enum
+{
+ /** Only one controller is used with PHY. */
+ DP_SD0801_SINGLE_CONTROLLER = 0x01U,
+ /** Two controllers are used with PHY. */
+ DP_SD0801_DUAL_CONTROLLER = 0x02U
+} DP_SD0801_ControllersPerPhy;
+
+/**
+ * @}
+ */
+
+/** @defgroup DriverFunctionAPI Driver Function API
+ * Prototypes for the driver API functions. The user application can link statically to the
+ * necessary API functions and call them directly.
+ * @{
+ */
+
+/**********************************************************************
+* API methods
+**********************************************************************/
+
+/**
+ * Get the driver's memory requirements.
+ * @param[in] config Driver/hardware configuration.
+ * @param[out] memReq Size of memory, that needs to be allocated (in bytes).
+ */
+uint32_t DP_SD0801_Probe(const DP_SD0801_Config* config, uint32_t* memReq);
+
+/**
+ * Brief set up of driver, must be called before any other driver's
+ * API function call.
+ * @param[in,out] pD Driver state info specific to this instance.
+ * @param[in] config Specifies driver/hardware configuration.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD, config or callbacks is NULL.
+ * @return CDN_ENOTSUP If HW is not supported by this driver.
+ */
+uint32_t DP_SD0801_Init(DP_SD0801_PrivateData* pD, const DP_SD0801_Config* config);
+
+/**
+ * Initialize part of PHY responsible for AUX channel. Has to be
+ * called before performing any DPCD or EDID operations.
+ * @param[in] pD Driver state info specific to this instance.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD is NULL.
+ */
+uint32_t DP_SD0801_ConfigurePhyAuxCtrl(const DP_SD0801_PrivateData* pD);
+
+/**
+ * Automatically initialize and configure DP Main Link on PHY. Has to
+ * be called before performing Link Training. This is a recommended
+ * way to bring up PHY, instead of manual initialization. AUX channel
+ * still has to be initialized separately.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] laneCount Number of lanes to initialize PHY with.
+ * @param[in] linkRate Link rate to initialize PHY with.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD is NULL or parameters are invalid.
+ */
+uint32_t DP_SD0801_PhyStartUp(DP_SD0801_PrivateData* pD, uint8_t laneCount, DP_SD0801_LinkRate linkRate);
+
+/**
+ * Part of manual DP PHY Main Link initialization. Performs operations
+ * to be done before releasing PHY reset.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] laneCount Number of lanes to initialize PHY with.
+ * @param[in] linkRate Link rate to initialize PHY with.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD is NULL or parameters are invalid.
+ */
+uint32_t DP_SD0801_PhyInit(DP_SD0801_PrivateData* pD, uint8_t laneCount, DP_SD0801_LinkRate linkRate);
+
+/**
+ * Part of manual DP PHY Main Link initialization. Assert or release
+ * PHY reset signal.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] reset 'true' - Assert PHY reset. 'false' - Release PHY reset.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD is NULL.
+ */
+uint32_t DP_SD0801_PhySetReset(const DP_SD0801_PrivateData* pD, bool reset);
+
+/**
+ * Part of manual DP PHY Main Link initialization. Wait, until PHY
+ * gets ready after releasing PHY reset signal.
+ * @param[in] pD Driver state info specific to this instance.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD is NULL.
+ */
+uint32_t DP_SD0801_WaitPmaCmnReady(const DP_SD0801_PrivateData* pD);
+
+/**
+ * Part of manual DP PHY Main Link initialization. Enable DP Main Link
+ * lanes, after releasing PHY reset and waiting for PHY to get ready.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] laneCount Number of lanes to initialize PHY with.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD is NULL.
+ */
+uint32_t DP_SD0801_PhyRun(const DP_SD0801_PrivateData* pD, uint8_t laneCount);
+
+/**
+ * Configure voltage swing and pre-emphasis values for a specified
+ * lane, according to values in linkState.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] lane Index of lane to configure.
+ * @param[in] linkState Pointer to structure with link state, containing lane settings to use.
+ *
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD is NULL.
+ */
+uint32_t DP_SD0801_ConfigLane(DP_SD0801_PrivateData* pD, uint8_t lane, const DP_SD0801_LinkState* linkState);
+
+/**
+ * Set link rate for main link, according to value in linkState. This
+ * function also enables or disables SSC for main link, as SSC affects
+ * the link rate slightly.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] linkState Pointer to structure with link state, containing link rate to use, and
+ * SSC enable flag.
+ *
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD is NULL.
+ */
+uint32_t DP_SD0801_SetLinkRate(DP_SD0801_PrivateData* pD, const DP_SD0801_LinkState* linkState);
+
+/**
+ * Set number of lanes to be used by main link, according to value in
+ * linkState.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] linkState Pointer to structure with link state, containing lane count to use.
+ *
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD is NULL.
+ */
+uint32_t DP_SD0801_EnableLanes(DP_SD0801_PrivateData* pD, const DP_SD0801_LinkState* linkState);
+
+/**
+ * Get default values of voltage-related PHY registers, for given
+ * voltage swing and pre-emphasis. Value of 0xFFFF means, that such
+ * combination of swing and emphasis is not supported by PHY or is
+ * forbidden, or that PHY does not contain particular register.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] voltageSwing Voltage swing level to use to select register values.
+ * @param[in] preEmphasis Pre-emphasis level to use to select register values.
+ * @param[out] coefficients Pointer to struct to be filled with default values of coefficients.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If voltage swing or pre-emphasis is outside of range (0-3).
+ */
+uint32_t DP_SD0801_GetDefaultCoeffs(const DP_SD0801_PrivateData* pD, uint8_t voltageSwing, uint8_t preEmphasis, DP_SD0801_VoltageCoefficients* coefficients);
+
+/**
+ * Get current values of voltage-related PHY registers, for given
+ * voltage swing and pre-emphasis. After driver initialization values
+ * will be the same, as default ones.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] voltageSwing Voltage swing level to use to select register values.
+ * @param[in] preEmphasis Pre-emphasis level to use to select register values.
+ * @param[out] coefficients Pointer to struct to be filled with current values of coefficients.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If voltage swing or pre-emphasis is outside of range (0-3).
+ */
+uint32_t DP_SD0801_GetCoefficients(const DP_SD0801_PrivateData* pD, uint8_t voltageSwing, uint8_t preEmphasis, DP_SD0801_VoltageCoefficients* coefficients);
+
+/**
+ * Set values of voltage-related PHY registers, to be used for given
+ * voltage swing and pre-emphasis. Values for non-existent registers,
+ * or for unsupported or forbidden swing/emphasis combinations will
+ * have no effect.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] voltageSwing Voltage swing level to use to select register values.
+ * @param[in] preEmphasis Pre-emphasis level to use to select register values.
+ * @param[in] coefficients Pointer to struct containing values of coefficients to use.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If voltage swing or pre-emphasis is outside of range (0-3).
+ */
+uint32_t DP_SD0801_SetCoefficients(DP_SD0801_PrivateData* pD, uint8_t voltageSwing, uint8_t preEmphasis, const DP_SD0801_VoltageCoefficients* coefficients);
+
+/**
+ * Get current link status (link rate, lane count, voltage sing level
+ * and pre-emphasis level). Values are valid after successful Link
+ * Training.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] linkState Link State.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD or linkState pointer is NULL.
+ */
+uint32_t DP_SD0801_ReadLinkStat(const DP_SD0801_PrivateData* pD, DP_SD0801_LinkState* linkState);
+
+/**
+ * @}
+ */
+
+/* parasoft-end-suppress MISRA2012-RULE-1_1_b_c90-2 */
+/* parasoft-end-suppress MISRA2012-RULE-1_1_a_c90-2 */
+
+#endif /* DP_SD0801_IF_H */
diff --git a/packages/ti/drv/dss/src/csl/dp_sd0801/include/dp_sd0801_obj_if.h b/packages/ti/drv/dss/src/csl/dp_sd0801/include/dp_sd0801_obj_if.h
--- /dev/null
@@ -0,0 +1,239 @@
+/**********************************************************************
+* Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* 1. Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* 2. Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the distribution.
+* 3. Neither the name of the copyright holder nor the names of its
+* contributors may be used to endorse or promote products derived from
+* this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+**********************************************************************
+* WARNING: This file is auto-generated using api-generator utility.
+* api-generator: 12.03.9e11b77(origin/DRV-3827_extract_sanity_to_c_file)
+* Do not edit it manually.
+**********************************************************************
+* Cadence Core Driver for the Cadence DP_SD0801 PHY for DisplayPort (DP)
+* core. This header file lists the API providing a HAL (hardware
+* abstraction layer) interface for the DP_SD0801 "Torrent" core.
+**********************************************************************/
+#ifndef DP_SD0801_OBJ_IF_H
+#define DP_SD0801_OBJ_IF_H
+
+#include "dp_sd0801_if.h"
+
+/** @defgroup DriverObject Driver API Object
+ * API listing for the driver. The API is contained in the object as
+ * function pointers in the object structure. As the actual functions
+ * resides in the Driver Object, the client software must first use the
+ * global GetInstance function to obtain the Driver Object Pointer.
+ * The actual APIs then can be invoked using obj->(api_name)() syntax.
+ * These functions are defined in the header file of the core driver
+ * and utilized by the API.
+ * @{
+ */
+
+/**********************************************************************
+* API methods
+**********************************************************************/
+typedef struct DP_SD0801_OBJ_s
+{
+ /**
+ * Get the driver's memory requirements.
+ * @param[in] config Driver/hardware configuration.
+ * @param[out] memReq Size of memory, that needs to be allocated (in bytes).
+ */
+ uint32_t (*probe)(const DP_SD0801_Config* config, uint32_t* memReq);
+
+ /**
+ * Brief set up of driver, must be called before any other driver's
+ * API function call.
+ * @param[in,out] pD Driver state info specific to this instance.
+ * @param[in] config Specifies driver/hardware configuration.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD, config or callbacks is NULL.
+ * @return CDN_ENOTSUP If HW is not supported by this driver.
+ */
+ uint32_t (*init)(DP_SD0801_PrivateData* pD, const DP_SD0801_Config* config);
+
+ /**
+ * Initialize part of PHY responsible for AUX channel. Has to be
+ * called before performing any DPCD or EDID operations.
+ * @param[in] pD Driver state info specific to this instance.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD is NULL.
+ */
+ uint32_t (*configurePhyAuxCtrl)(const DP_SD0801_PrivateData* pD);
+
+ /**
+ * Automatically initialize and configure DP Main Link on PHY. Has to
+ * be called before performing Link Training. This is a recommended
+ * way to bring up PHY, instead of manual initialization. AUX channel
+ * still has to be initialized separately.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] laneCount Number of lanes to initialize PHY with.
+ * @param[in] linkRate Link rate to initialize PHY with.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD is NULL or parameters are invalid.
+ */
+ uint32_t (*phyStartUp)(DP_SD0801_PrivateData* pD, uint8_t laneCount, DP_SD0801_LinkRate linkRate);
+
+ /**
+ * Part of manual DP PHY Main Link initialization. Performs
+ * operations to be done before releasing PHY reset.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] laneCount Number of lanes to initialize PHY with.
+ * @param[in] linkRate Link rate to initialize PHY with.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD is NULL or parameters are invalid.
+ */
+ uint32_t (*PhyInit)(DP_SD0801_PrivateData* pD, uint8_t laneCount, DP_SD0801_LinkRate linkRate);
+
+ /**
+ * Part of manual DP PHY Main Link initialization. Assert or release
+ * PHY reset signal.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] reset 'true' - Assert PHY reset. 'false' - Release PHY reset.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD is NULL.
+ */
+ uint32_t (*phySetReset)(const DP_SD0801_PrivateData* pD, bool reset);
+
+ /**
+ * Part of manual DP PHY Main Link initialization. Wait, until PHY
+ * gets ready after releasing PHY reset signal.
+ * @param[in] pD Driver state info specific to this instance.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD is NULL.
+ */
+ uint32_t (*waitPmaCmnReady)(const DP_SD0801_PrivateData* pD);
+
+ /**
+ * Part of manual DP PHY Main Link initialization. Enable DP Main
+ * Link lanes, after releasing PHY reset and waiting for PHY to get
+ * ready.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] laneCount Number of lanes to initialize PHY with.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD is NULL.
+ */
+ uint32_t (*phyRun)(const DP_SD0801_PrivateData* pD, uint8_t laneCount);
+
+ /**
+ * Configure voltage swing and pre-emphasis values for a specified
+ * lane, according to values in linkState.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] lane Index of lane to configure.
+ * @param[in] linkState Pointer to structure with link state, containing lane settings to use.
+ *
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD is NULL.
+ */
+ uint32_t (*configLane)(DP_SD0801_PrivateData* pD, uint8_t lane, const DP_SD0801_LinkState* linkState);
+
+ /**
+ * Set link rate for main link, according to value in linkState. This
+ * function also enables or disables SSC for main link, as SSC
+ * affects the link rate slightly.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] linkState Pointer to structure with link state, containing link rate to use, and
+ * SSC enable flag.
+ *
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD is NULL.
+ */
+ uint32_t (*setLinkRate)(DP_SD0801_PrivateData* pD, const DP_SD0801_LinkState* linkState);
+
+ /**
+ * Set number of lanes to be used by main link, according to value in
+ * linkState.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] linkState Pointer to structure with link state, containing lane count to use.
+ *
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD is NULL.
+ */
+ uint32_t (*enableLanes)(DP_SD0801_PrivateData* pD, const DP_SD0801_LinkState* linkState);
+
+ /**
+ * Get default values of voltage-related PHY registers, for given
+ * voltage swing and pre-emphasis. Value of 0xFFFF means, that such
+ * combination of swing and emphasis is not supported by PHY or is
+ * forbidden, or that PHY does not contain particular register.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] voltageSwing Voltage swing level to use to select register values.
+ * @param[in] preEmphasis Pre-emphasis level to use to select register values.
+ * @param[out] coefficients Pointer to struct to be filled with default values of coefficients.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If voltage swing or pre-emphasis is outside of range (0-3).
+ */
+ uint32_t (*getDefaultCoeffs)(const DP_SD0801_PrivateData* pD, uint8_t voltageSwing, uint8_t preEmphasis, DP_SD0801_VoltageCoefficients* coefficients);
+
+ /**
+ * Get current values of voltage-related PHY registers, for given
+ * voltage swing and pre-emphasis. After driver initialization values
+ * will be the same, as default ones.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] voltageSwing Voltage swing level to use to select register values.
+ * @param[in] preEmphasis Pre-emphasis level to use to select register values.
+ * @param[out] coefficients Pointer to struct to be filled with current values of coefficients.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If voltage swing or pre-emphasis is outside of range (0-3).
+ */
+ uint32_t (*getCoefficients)(const DP_SD0801_PrivateData* pD, uint8_t voltageSwing, uint8_t preEmphasis, DP_SD0801_VoltageCoefficients* coefficients);
+
+ /**
+ * Set values of voltage-related PHY registers, to be used for given
+ * voltage swing and pre-emphasis. Values for non-existent registers,
+ * or for unsupported or forbidden swing/emphasis combinations will
+ * have no effect.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] voltageSwing Voltage swing level to use to select register values.
+ * @param[in] preEmphasis Pre-emphasis level to use to select register values.
+ * @param[in] coefficients Pointer to struct containing values of coefficients to use.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If voltage swing or pre-emphasis is outside of range (0-3).
+ */
+ uint32_t (*setCoefficients)(DP_SD0801_PrivateData* pD, uint8_t voltageSwing, uint8_t preEmphasis, const DP_SD0801_VoltageCoefficients* coefficients);
+
+ /**
+ * Get current link status (link rate, lane count, voltage sing level
+ * and pre-emphasis level). Values are valid after successful Link
+ * Training.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] linkState Link State.
+ * @return CDN_EOK success
+ * @return CDN_EINVAL If pD or linkState pointer is NULL.
+ */
+ uint32_t (*readLinkStat)(const DP_SD0801_PrivateData* pD, DP_SD0801_LinkState* linkState);
+
+} DP_SD0801_OBJ;
+
+/**
+ * In order to access the DP_SD0801 APIs, the upper layer software must call
+ * this global function to obtain the pointer to the driver object.
+ * @return DP_SD0801_OBJ* Driver Object Pointer
+ */
+extern DP_SD0801_OBJ *DP_SD0801_GetInstance(void);
+
+/**
+ * @}
+ */
+
+#endif /* DP_SD0801_OBJ_IF_H */
diff --git a/packages/ti/drv/dss/src/csl/dp_sd0801/include/dp_sd0801_structs_if.h b/packages/ti/drv/dss/src/csl/dp_sd0801/include/dp_sd0801_structs_if.h
--- /dev/null
@@ -0,0 +1,97 @@
+/* parasoft suppress item MISRA2012-DIR-4_8 "Consider hiding implementation of structure" */
+/**********************************************************************
+* Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* 1. Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* 2. Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the distribution.
+* 3. Neither the name of the copyright holder nor the names of its
+* contributors may be used to endorse or promote products derived from
+* this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+**********************************************************************
+* WARNING: This file is auto-generated using api-generator utility.
+* api-generator: 12.03.9e11b77(origin/DRV-3827_extract_sanity_to_c_file)
+* Do not edit it manually.
+**********************************************************************
+* Cadence Core Driver for the Cadence DP_SD0801 PHY for DisplayPort (DP)
+* core. This header file lists the API providing a HAL (hardware
+* abstraction layer) interface for the DP_SD0801 "Torrent" core.
+**********************************************************************/
+#ifndef DP_SD0801_STRUCTS_IF_H
+#define DP_SD0801_STRUCTS_IF_H
+
+#include "cdn_stdtypes.h"
+#include "dp_sd0801_if.h"
+
+/** @defgroup DataStructure Dynamic Data Structures
+ * This section defines the data structures used by the driver to provide
+ * hardware information, modification and dynamic operation of the driver.
+ * These data structures are defined in the header file of the core driver
+ * and utilized by the API.
+ * @{
+ */
+
+/**********************************************************************
+* Structures and unions
+**********************************************************************/
+/**
+ * Structure used to store values of PHY registers for voltage-related
+ * coefficients, for particular voltage swing and re-emphasis level. Values
+ * are shared across all physical lanes.
+ */
+struct DP_SD0801_VoltageCoefficients_s
+{
+ /** Value of DRV_DIAG_TX_DRV register to use */
+ uint16_t DiagTxDrv;
+ /** Value of TX_TXCC_MGNFS_MULT_000 register to use */
+ uint16_t MgnfsMult;
+ /** Value of TX_TXCC_CPOST_MULT_00 register to use */
+ uint16_t CpostMult;
+};
+
+/** Structure containing parameters of physical link. */
+struct DP_SD0801_LinkState_s
+{
+ /** Link Rate */
+ DP_SD0801_LinkRate linkRate;
+ /** Lane count */
+ uint8_t laneCount;
+ /** Voltage swing level, one per lane. */
+ uint8_t voltageSwing[DP_SD0801_MAX_LANE_COUNT];
+ /** Pre-emphasis level, one per lane. */
+ uint8_t preEmphasis[DP_SD0801_MAX_LANE_COUNT];
+ /** SSC (Spread-Spectrum Clock) enabled. */
+ bool ssc;
+};
+
+/** Configuration parameters passed to probe & init functions. */
+struct DP_SD0801_Config_s
+{
+ /** Base address of the PHY APB register space. */
+ uint32_t* regBase;
+ /** Base address of the DPTX controller's register space. */
+ struct DP_Regs_s* regBaseDp;
+};
+
+/**
+ * @}
+ */
+
+#endif /* DP_SD0801_STRUCTS_IF_H */
diff --git a/packages/ti/drv/dss/src/csl/dp_sd0801/src/dp_regs.h b/packages/ti/drv/dss/src/csl/dp_sd0801/src/dp_regs.h
--- /dev/null
@@ -0,0 +1,67 @@
+/* parasoft-begin-suppress MISRA2012-RULE-1_1_a_c99-2 "C99 - limits, DRV-4754" parasoft-begin-suppress MISRA2012-RULE-1_1_a_c90-2 "C90 - limits, DRV-4754" */
+/* parasoft-begin-suppress item MISRA2012-DIR-4_8 "Consider hiding implementation of structure, DRV-3667" */
+
+/**********************************************************************
+* Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* 1. Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* 2. Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the distribution.
+* 3. Neither the name of the copyright holder nor the names of its
+* contributors may be used to endorse or promote products derived from
+* this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+* THIS FILE IS AUTOMATICALLY GENERATED, DO NOT EDIT
+*
+**********************************************************************/
+
+#ifndef REG_DP_REGS_H_
+#define REG_DP_REGS_H_
+
+#include <cps_drv.h>
+
+#include "dp_regs_macros.h"
+
+typedef struct __attribute__((packed)) DP_Regs_s {
+ struct {
+ volatile char pad__0[0x30A00U];
+ volatile uint32_t AUX_CONFIG_p;
+ volatile uint32_t AUX_CTRL_p;
+ volatile uint32_t AUX_ATBSEL_p;
+ volatile uint32_t AUX_TESTMODE_CTL_p;
+ volatile uint32_t AUX_TESTMODE_ST_p;
+ volatile char pad__1[0xCU];
+ volatile uint32_t PHY_RESET_p;
+ volatile uint32_t PMA_PLLCLK_EN_p;
+ volatile uint32_t PMA_PLLCLK_EN_ACK_p;
+ volatile uint32_t PMA_POWER_STATE_REQ_p;
+ volatile uint32_t PMA_POWER_STATE_ACK_p;
+ volatile uint32_t PMA_CMN_READY_p;
+ volatile uint32_t PMA_TX_VMARGIN_p;
+ volatile uint32_t PMA_TX_DEEMPH_p;
+ } dp_regs;
+} DP_Regs;
+
+#endif /* REG_DP_REGS_H_ */
+
+/* parasoft-end-suppress MISRA2012-RULE-1_1_a_c99-2 "C99 - limits, DRV-4754" */
+/* parasoft-end-suppress MISRA2012-RULE-1_1_a_c90-2 "C90 - limits, DRV-4754" */
+/* parasoft-end-suppress MISRA2012-DIR-4_8 "Consider hiding implementation of structure, DRV-3667" */
+
diff --git a/packages/ti/drv/dss/src/csl/dp_sd0801/src/dp_regs_macros.h b/packages/ti/drv/dss/src/csl/dp_sd0801/src/dp_regs_macros.h
--- /dev/null
@@ -0,0 +1,394 @@
+/* parasoft-begin-suppress MISRA2012-RULE-1_1_b_c99-2 "C99 - limits, DRV-4754" parasoft-begin-suppress MISRA2012-RULE-1_1_b_c90-2 "C90 - limits, DRV-4754" */
+/* parasoft-begin-suppress MISRA2012-RULE-5_4_b_c90-2 "C90 - similar names, DRV-4756" */
+/* parasoft-begin-suppress MISRA2012-RULE-5_4_b_c99-2 "C99 - similar names, DRV-4756" */
+
+/**********************************************************************
+* Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* 1. Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* 2. Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the distribution.
+* 3. Neither the name of the copyright holder nor the names of its
+* contributors may be used to endorse or promote products derived from
+* this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+*
+* THIS FILE IS AUTOMATICALLY GENERATED, DO NOT EDIT
+*
+**********************************************************************/
+
+#ifndef REG_DP_REGS_MACROS_H_
+#define REG_DP_REGS_MACROS_H_
+
+#define DP__DP_REGS__AUX_CONFIG_P_READ_MASK 0xFFFFFFFFU
+#define DP__DP_REGS__AUX_CONFIG_P_WRITE_MASK 0xFFFFFFFFU
+#define DP__DP_REGS__AUX_CONFIG_P__BANDGAP_ADJUST_MASK 0x00000003U
+#define DP__DP_REGS__AUX_CONFIG_P__BANDGAP_ADJUST_SHIFT 0U
+#define DP__DP_REGS__AUX_CONFIG_P__BANDGAP_ADJUST_WIDTH 2U
+#define DP__DP_REGS__AUX_CONFIG_P__RX_OFFSET_DIS_MASK 0x00000004U
+#define DP__DP_REGS__AUX_CONFIG_P__RX_OFFSET_DIS_SHIFT 2U
+#define DP__DP_REGS__AUX_CONFIG_P__RX_OFFSET_DIS_WIDTH 1U
+#define DP__DP_REGS__AUX_CONFIG_P__RX_OFFSET_DIS_WOCLR 0U
+#define DP__DP_REGS__AUX_CONFIG_P__RX_OFFSET_DIS_WOSET 0U
+#define DP__DP_REGS__AUX_CONFIG_P__RESERVED_0_MASK 0x00000008U
+#define DP__DP_REGS__AUX_CONFIG_P__RESERVED_0_SHIFT 3U
+#define DP__DP_REGS__AUX_CONFIG_P__RESERVED_0_WIDTH 1U
+#define DP__DP_REGS__AUX_CONFIG_P__RESERVED_0_WOCLR 0U
+#define DP__DP_REGS__AUX_CONFIG_P__RESERVED_0_WOSET 0U
+#define DP__DP_REGS__AUX_CONFIG_P__RX_DEGLITCH_FILTER_MASK 0x00000030U
+#define DP__DP_REGS__AUX_CONFIG_P__RX_DEGLITCH_FILTER_SHIFT 4U
+#define DP__DP_REGS__AUX_CONFIG_P__RX_DEGLITCH_FILTER_WIDTH 2U
+#define DP__DP_REGS__AUX_CONFIG_P__RESERVED_1_MASK 0x000000C0U
+#define DP__DP_REGS__AUX_CONFIG_P__RESERVED_1_SHIFT 6U
+#define DP__DP_REGS__AUX_CONFIG_P__RESERVED_1_WIDTH 2U
+#define DP__DP_REGS__AUX_CONFIG_P__RX_HYST_LVL_MASK 0x00000700U
+#define DP__DP_REGS__AUX_CONFIG_P__RX_HYST_LVL_SHIFT 8U
+#define DP__DP_REGS__AUX_CONFIG_P__RX_HYST_LVL_WIDTH 3U
+#define DP__DP_REGS__AUX_CONFIG_P__RESERVED_2_MASK 0x00000800U
+#define DP__DP_REGS__AUX_CONFIG_P__RESERVED_2_SHIFT 11U
+#define DP__DP_REGS__AUX_CONFIG_P__RESERVED_2_WIDTH 1U
+#define DP__DP_REGS__AUX_CONFIG_P__RESERVED_2_WOCLR 0U
+#define DP__DP_REGS__AUX_CONFIG_P__RESERVED_2_WOSET 0U
+#define DP__DP_REGS__AUX_CONFIG_P__TX_REDUCED_SWING_MASK 0x00001000U
+#define DP__DP_REGS__AUX_CONFIG_P__TX_REDUCED_SWING_SHIFT 12U
+#define DP__DP_REGS__AUX_CONFIG_P__TX_REDUCED_SWING_WIDTH 1U
+#define DP__DP_REGS__AUX_CONFIG_P__TX_REDUCED_SWING_WOCLR 0U
+#define DP__DP_REGS__AUX_CONFIG_P__TX_REDUCED_SWING_WOSET 0U
+#define DP__DP_REGS__AUX_CONFIG_P__TX_SLEW_RATE_MASK 0x00006000U
+#define DP__DP_REGS__AUX_CONFIG_P__TX_SLEW_RATE_SHIFT 13U
+#define DP__DP_REGS__AUX_CONFIG_P__TX_SLEW_RATE_WIDTH 2U
+#define DP__DP_REGS__AUX_CONFIG_P__RESERVED_3_MASK 0x00008000U
+#define DP__DP_REGS__AUX_CONFIG_P__RESERVED_3_SHIFT 15U
+#define DP__DP_REGS__AUX_CONFIG_P__RESERVED_3_WIDTH 1U
+#define DP__DP_REGS__AUX_CONFIG_P__RESERVED_3_WOCLR 0U
+#define DP__DP_REGS__AUX_CONFIG_P__RESERVED_3_WOSET 0U
+#define DP__DP_REGS__AUX_CONFIG_P__TX_CURR_CTRL_MASK 0x001F0000U
+#define DP__DP_REGS__AUX_CONFIG_P__TX_CURR_CTRL_SHIFT 16U
+#define DP__DP_REGS__AUX_CONFIG_P__TX_CURR_CTRL_WIDTH 5U
+#define DP__DP_REGS__AUX_CONFIG_P__RESERVED_4_MASK 0x00E00000U
+#define DP__DP_REGS__AUX_CONFIG_P__RESERVED_4_SHIFT 21U
+#define DP__DP_REGS__AUX_CONFIG_P__RESERVED_4_WIDTH 3U
+#define DP__DP_REGS__AUX_CONFIG_P__TERM_SEG_EN_MASK 0x1F000000U
+#define DP__DP_REGS__AUX_CONFIG_P__TERM_SEG_EN_SHIFT 24U
+#define DP__DP_REGS__AUX_CONFIG_P__TERM_SEG_EN_WIDTH 5U
+#define DP__DP_REGS__AUX_CONFIG_P__RESERVED_5_MASK 0xE0000000U
+#define DP__DP_REGS__AUX_CONFIG_P__RESERVED_5_SHIFT 29U
+#define DP__DP_REGS__AUX_CONFIG_P__RESERVED_5_WIDTH 3U
+
+#define DP__DP_REGS__AUX_CTRL_P_READ_MASK 0xFFFFFFFFU
+#define DP__DP_REGS__AUX_CTRL_P_WRITE_MASK 0xFFFFFFFFU
+#define DP__DP_REGS__AUX_CTRL_P__BANDGAP_EN_MASK 0x00000001U
+#define DP__DP_REGS__AUX_CTRL_P__BANDGAP_EN_SHIFT 0U
+#define DP__DP_REGS__AUX_CTRL_P__BANDGAP_EN_WIDTH 1U
+#define DP__DP_REGS__AUX_CTRL_P__BANDGAP_EN_WOCLR 0U
+#define DP__DP_REGS__AUX_CTRL_P__BANDGAP_EN_WOSET 0U
+#define DP__DP_REGS__AUX_CTRL_P__DECAP_EN_MASK 0x00000002U
+#define DP__DP_REGS__AUX_CTRL_P__DECAP_EN_SHIFT 1U
+#define DP__DP_REGS__AUX_CTRL_P__DECAP_EN_WIDTH 1U
+#define DP__DP_REGS__AUX_CTRL_P__DECAP_EN_WOCLR 0U
+#define DP__DP_REGS__AUX_CTRL_P__DECAP_EN_WOSET 0U
+#define DP__DP_REGS__AUX_CTRL_P__RESERVED_0_MASK 0xFFFFFFFCU
+#define DP__DP_REGS__AUX_CTRL_P__RESERVED_0_SHIFT 2U
+#define DP__DP_REGS__AUX_CTRL_P__RESERVED_0_WIDTH 30U
+
+#define DP__DP_REGS__AUX_ATBSEL_P_READ_MASK 0xFFFFFFFFU
+#define DP__DP_REGS__AUX_ATBSEL_P_WRITE_MASK 0xFFFFFFFFU
+#define DP__DP_REGS__AUX_ATBSEL_P__AUXIP_ATBSEL_ONEHOT_MASK 0x000000FFU
+#define DP__DP_REGS__AUX_ATBSEL_P__AUXIP_ATBSEL_ONEHOT_SHIFT 0U
+#define DP__DP_REGS__AUX_ATBSEL_P__AUXIP_ATBSEL_ONEHOT_WIDTH 8U
+#define DP__DP_REGS__AUX_ATBSEL_P__RESERVED_0_MASK 0xFFFFFF00U
+#define DP__DP_REGS__AUX_ATBSEL_P__RESERVED_0_SHIFT 8U
+#define DP__DP_REGS__AUX_ATBSEL_P__RESERVED_0_WIDTH 24U
+
+#define DP__DP_REGS__AUX_TESTMODE_CTL_P_READ_MASK 0xFFFFFFFFU
+#define DP__DP_REGS__AUX_TESTMODE_CTL_P_WRITE_MASK 0xFFFFFFFFU
+#define DP__DP_REGS__AUX_TESTMODE_CTL_P__AUX_TESTMODE_EN_MASK 0x00000001U
+#define DP__DP_REGS__AUX_TESTMODE_CTL_P__AUX_TESTMODE_EN_SHIFT 0U
+#define DP__DP_REGS__AUX_TESTMODE_CTL_P__AUX_TESTMODE_EN_WIDTH 1U
+#define DP__DP_REGS__AUX_TESTMODE_CTL_P__AUX_TESTMODE_EN_WOCLR 0U
+#define DP__DP_REGS__AUX_TESTMODE_CTL_P__AUX_TESTMODE_EN_WOSET 0U
+#define DP__DP_REGS__AUX_TESTMODE_CTL_P__RX_EN_CTRL_MASK 0x00000002U
+#define DP__DP_REGS__AUX_TESTMODE_CTL_P__RX_EN_CTRL_SHIFT 1U
+#define DP__DP_REGS__AUX_TESTMODE_CTL_P__RX_EN_CTRL_WIDTH 1U
+#define DP__DP_REGS__AUX_TESTMODE_CTL_P__RX_EN_CTRL_WOCLR 0U
+#define DP__DP_REGS__AUX_TESTMODE_CTL_P__RX_EN_CTRL_WOSET 0U
+#define DP__DP_REGS__AUX_TESTMODE_CTL_P__TX_EN_CTRL_MASK 0x00000004U
+#define DP__DP_REGS__AUX_TESTMODE_CTL_P__TX_EN_CTRL_SHIFT 2U
+#define DP__DP_REGS__AUX_TESTMODE_CTL_P__TX_EN_CTRL_WIDTH 1U
+#define DP__DP_REGS__AUX_TESTMODE_CTL_P__TX_EN_CTRL_WOCLR 0U
+#define DP__DP_REGS__AUX_TESTMODE_CTL_P__TX_EN_CTRL_WOSET 0U
+#define DP__DP_REGS__AUX_TESTMODE_CTL_P__AUX_DATA_IN_MASK 0x00000008U
+#define DP__DP_REGS__AUX_TESTMODE_CTL_P__AUX_DATA_IN_SHIFT 3U
+#define DP__DP_REGS__AUX_TESTMODE_CTL_P__AUX_DATA_IN_WIDTH 1U
+#define DP__DP_REGS__AUX_TESTMODE_CTL_P__AUX_DATA_IN_WOCLR 0U
+#define DP__DP_REGS__AUX_TESTMODE_CTL_P__AUX_DATA_IN_WOSET 0U
+#define DP__DP_REGS__AUX_TESTMODE_CTL_P__DECAP_EN_DEL_MASK 0x00000010U
+#define DP__DP_REGS__AUX_TESTMODE_CTL_P__DECAP_EN_DEL_SHIFT 4U
+#define DP__DP_REGS__AUX_TESTMODE_CTL_P__DECAP_EN_DEL_WIDTH 1U
+#define DP__DP_REGS__AUX_TESTMODE_CTL_P__DECAP_EN_DEL_WOCLR 0U
+#define DP__DP_REGS__AUX_TESTMODE_CTL_P__DECAP_EN_DEL_WOSET 0U
+#define DP__DP_REGS__AUX_TESTMODE_CTL_P__RESERVED_MASK 0xFFFFFFE0U
+#define DP__DP_REGS__AUX_TESTMODE_CTL_P__RESERVED_SHIFT 5U
+#define DP__DP_REGS__AUX_TESTMODE_CTL_P__RESERVED_WIDTH 27U
+
+#define DP__DP_REGS__AUX_TESTMODE_ST_P_READ_MASK 0xFFFFFFFFU
+#define DP__DP_REGS__AUX_TESTMODE_ST_P_WRITE_MASK 0xFFFFFFFFU
+#define DP__DP_REGS__AUX_TESTMODE_ST_P__HPD_DATA_OUT_MASK 0x00000001U
+#define DP__DP_REGS__AUX_TESTMODE_ST_P__HPD_DATA_OUT_SHIFT 0U
+#define DP__DP_REGS__AUX_TESTMODE_ST_P__HPD_DATA_OUT_WIDTH 1U
+#define DP__DP_REGS__AUX_TESTMODE_ST_P__HPD_DATA_OUT_WOCLR 0U
+#define DP__DP_REGS__AUX_TESTMODE_ST_P__HPD_DATA_OUT_WOSET 0U
+#define DP__DP_REGS__AUX_TESTMODE_ST_P__AUX_DATA_OUT_MASK 0x00000002U
+#define DP__DP_REGS__AUX_TESTMODE_ST_P__AUX_DATA_OUT_SHIFT 1U
+#define DP__DP_REGS__AUX_TESTMODE_ST_P__AUX_DATA_OUT_WIDTH 1U
+#define DP__DP_REGS__AUX_TESTMODE_ST_P__AUX_DATA_OUT_WOCLR 0U
+#define DP__DP_REGS__AUX_TESTMODE_ST_P__AUX_DATA_OUT_WOSET 0U
+#define DP__DP_REGS__AUX_TESTMODE_ST_P__RESERVED_MASK 0xFFFFFFFCU
+#define DP__DP_REGS__AUX_TESTMODE_ST_P__RESERVED_SHIFT 2U
+#define DP__DP_REGS__AUX_TESTMODE_ST_P__RESERVED_WIDTH 30U
+
+#define DP__DP_REGS__PHY_RESET_P_READ_MASK 0xFFFFFFFFU
+#define DP__DP_REGS__PHY_RESET_P_WRITE_MASK 0xFFFFFFFFU
+#define DP__DP_REGS__PHY_RESET_P__PHY_L00_RESET_N_MASK 0x00000001U
+#define DP__DP_REGS__PHY_RESET_P__PHY_L00_RESET_N_SHIFT 0U
+#define DP__DP_REGS__PHY_RESET_P__PHY_L00_RESET_N_WIDTH 1U
+#define DP__DP_REGS__PHY_RESET_P__PHY_L00_RESET_N_WOCLR 0U
+#define DP__DP_REGS__PHY_RESET_P__PHY_L00_RESET_N_WOSET 0U
+#define DP__DP_REGS__PHY_RESET_P__PHY_L01_RESET_N_MASK 0x00000002U
+#define DP__DP_REGS__PHY_RESET_P__PHY_L01_RESET_N_SHIFT 1U
+#define DP__DP_REGS__PHY_RESET_P__PHY_L01_RESET_N_WIDTH 1U
+#define DP__DP_REGS__PHY_RESET_P__PHY_L01_RESET_N_WOCLR 0U
+#define DP__DP_REGS__PHY_RESET_P__PHY_L01_RESET_N_WOSET 0U
+#define DP__DP_REGS__PHY_RESET_P__PHY_L02_RESET_N_MASK 0x00000004U
+#define DP__DP_REGS__PHY_RESET_P__PHY_L02_RESET_N_SHIFT 2U
+#define DP__DP_REGS__PHY_RESET_P__PHY_L02_RESET_N_WIDTH 1U
+#define DP__DP_REGS__PHY_RESET_P__PHY_L02_RESET_N_WOCLR 0U
+#define DP__DP_REGS__PHY_RESET_P__PHY_L02_RESET_N_WOSET 0U
+#define DP__DP_REGS__PHY_RESET_P__PHY_L03_RESET_N_MASK 0x00000008U
+#define DP__DP_REGS__PHY_RESET_P__PHY_L03_RESET_N_SHIFT 3U
+#define DP__DP_REGS__PHY_RESET_P__PHY_L03_RESET_N_WIDTH 1U
+#define DP__DP_REGS__PHY_RESET_P__PHY_L03_RESET_N_WOCLR 0U
+#define DP__DP_REGS__PHY_RESET_P__PHY_L03_RESET_N_WOSET 0U
+#define DP__DP_REGS__PHY_RESET_P__PMA_TX_ELEC_IDLE_LN_0_MASK 0x00000010U
+#define DP__DP_REGS__PHY_RESET_P__PMA_TX_ELEC_IDLE_LN_0_SHIFT 4U
+#define DP__DP_REGS__PHY_RESET_P__PMA_TX_ELEC_IDLE_LN_0_WIDTH 1U
+#define DP__DP_REGS__PHY_RESET_P__PMA_TX_ELEC_IDLE_LN_0_WOCLR 0U
+#define DP__DP_REGS__PHY_RESET_P__PMA_TX_ELEC_IDLE_LN_0_WOSET 0U
+#define DP__DP_REGS__PHY_RESET_P__PMA_TX_ELEC_IDLE_LN_1_MASK 0x00000020U
+#define DP__DP_REGS__PHY_RESET_P__PMA_TX_ELEC_IDLE_LN_1_SHIFT 5U
+#define DP__DP_REGS__PHY_RESET_P__PMA_TX_ELEC_IDLE_LN_1_WIDTH 1U
+#define DP__DP_REGS__PHY_RESET_P__PMA_TX_ELEC_IDLE_LN_1_WOCLR 0U
+#define DP__DP_REGS__PHY_RESET_P__PMA_TX_ELEC_IDLE_LN_1_WOSET 0U
+#define DP__DP_REGS__PHY_RESET_P__PMA_TX_ELEC_IDLE_LN_2_MASK 0x00000040U
+#define DP__DP_REGS__PHY_RESET_P__PMA_TX_ELEC_IDLE_LN_2_SHIFT 6U
+#define DP__DP_REGS__PHY_RESET_P__PMA_TX_ELEC_IDLE_LN_2_WIDTH 1U
+#define DP__DP_REGS__PHY_RESET_P__PMA_TX_ELEC_IDLE_LN_2_WOCLR 0U
+#define DP__DP_REGS__PHY_RESET_P__PMA_TX_ELEC_IDLE_LN_2_WOSET 0U
+#define DP__DP_REGS__PHY_RESET_P__PMA_TX_ELEC_IDLE_LN_3_MASK 0x00000080U
+#define DP__DP_REGS__PHY_RESET_P__PMA_TX_ELEC_IDLE_LN_3_SHIFT 7U
+#define DP__DP_REGS__PHY_RESET_P__PMA_TX_ELEC_IDLE_LN_3_WIDTH 1U
+#define DP__DP_REGS__PHY_RESET_P__PMA_TX_ELEC_IDLE_LN_3_WOCLR 0U
+#define DP__DP_REGS__PHY_RESET_P__PMA_TX_ELEC_IDLE_LN_3_WOSET 0U
+#define DP__DP_REGS__PHY_RESET_P__PHY_RESET_MASK 0x00000100U
+#define DP__DP_REGS__PHY_RESET_P__PHY_RESET_SHIFT 8U
+#define DP__DP_REGS__PHY_RESET_P__PHY_RESET_WIDTH 1U
+#define DP__DP_REGS__PHY_RESET_P__PHY_RESET_WOCLR 0U
+#define DP__DP_REGS__PHY_RESET_P__PHY_RESET_WOSET 0U
+#define DP__DP_REGS__PHY_RESET_P__RESERVED_1_MASK 0xFFFFFE00U
+#define DP__DP_REGS__PHY_RESET_P__RESERVED_1_SHIFT 9U
+#define DP__DP_REGS__PHY_RESET_P__RESERVED_1_WIDTH 23U
+
+#define DP__DP_REGS__PMA_PLLCLK_EN_P_READ_MASK 0xFFFFFFFFU
+#define DP__DP_REGS__PMA_PLLCLK_EN_P_WRITE_MASK 0xFFFFFFFFU
+#define DP__DP_REGS__PMA_PLLCLK_EN_P__PMA_XCVR_PLLCLK_EN_LN_0_MASK 0x00000001U
+#define DP__DP_REGS__PMA_PLLCLK_EN_P__PMA_XCVR_PLLCLK_EN_LN_0_SHIFT 0U
+#define DP__DP_REGS__PMA_PLLCLK_EN_P__PMA_XCVR_PLLCLK_EN_LN_0_WIDTH 1U
+#define DP__DP_REGS__PMA_PLLCLK_EN_P__PMA_XCVR_PLLCLK_EN_LN_0_WOCLR 0U
+#define DP__DP_REGS__PMA_PLLCLK_EN_P__PMA_XCVR_PLLCLK_EN_LN_0_WOSET 0U
+#define DP__DP_REGS__PMA_PLLCLK_EN_P__PMA_XCVR_PLLCLK_EN_LN_1_MASK 0x00000002U
+#define DP__DP_REGS__PMA_PLLCLK_EN_P__PMA_XCVR_PLLCLK_EN_LN_1_SHIFT 1U
+#define DP__DP_REGS__PMA_PLLCLK_EN_P__PMA_XCVR_PLLCLK_EN_LN_1_WIDTH 1U
+#define DP__DP_REGS__PMA_PLLCLK_EN_P__PMA_XCVR_PLLCLK_EN_LN_1_WOCLR 0U
+#define DP__DP_REGS__PMA_PLLCLK_EN_P__PMA_XCVR_PLLCLK_EN_LN_1_WOSET 0U
+#define DP__DP_REGS__PMA_PLLCLK_EN_P__PMA_XCVR_PLLCLK_EN_LN_2_MASK 0x00000004U
+#define DP__DP_REGS__PMA_PLLCLK_EN_P__PMA_XCVR_PLLCLK_EN_LN_2_SHIFT 2U
+#define DP__DP_REGS__PMA_PLLCLK_EN_P__PMA_XCVR_PLLCLK_EN_LN_2_WIDTH 1U
+#define DP__DP_REGS__PMA_PLLCLK_EN_P__PMA_XCVR_PLLCLK_EN_LN_2_WOCLR 0U
+#define DP__DP_REGS__PMA_PLLCLK_EN_P__PMA_XCVR_PLLCLK_EN_LN_2_WOSET 0U
+#define DP__DP_REGS__PMA_PLLCLK_EN_P__PMA_XCVR_PLLCLK_EN_LN_3_MASK 0x00000008U
+#define DP__DP_REGS__PMA_PLLCLK_EN_P__PMA_XCVR_PLLCLK_EN_LN_3_SHIFT 3U
+#define DP__DP_REGS__PMA_PLLCLK_EN_P__PMA_XCVR_PLLCLK_EN_LN_3_WIDTH 1U
+#define DP__DP_REGS__PMA_PLLCLK_EN_P__PMA_XCVR_PLLCLK_EN_LN_3_WOCLR 0U
+#define DP__DP_REGS__PMA_PLLCLK_EN_P__PMA_XCVR_PLLCLK_EN_LN_3_WOSET 0U
+#define DP__DP_REGS__PMA_PLLCLK_EN_P__RESERVED_0_MASK 0xFFFFFFF0U
+#define DP__DP_REGS__PMA_PLLCLK_EN_P__RESERVED_0_SHIFT 4U
+#define DP__DP_REGS__PMA_PLLCLK_EN_P__RESERVED_0_WIDTH 28U
+
+#define DP__DP_REGS__PMA_PLLCLK_EN_ACK_P_READ_MASK 0xFFFFFFFFU
+#define DP__DP_REGS__PMA_PLLCLK_EN_ACK_P_WRITE_MASK 0xFFFFFFFFU
+#define DP__DP_REGS__PMA_PLLCLK_EN_ACK_P__PMA_XCVR_PLLCLK_EN_ACK_LN_0_MASK 0x00000001U
+#define DP__DP_REGS__PMA_PLLCLK_EN_ACK_P__PMA_XCVR_PLLCLK_EN_ACK_LN_0_SHIFT 0U
+#define DP__DP_REGS__PMA_PLLCLK_EN_ACK_P__PMA_XCVR_PLLCLK_EN_ACK_LN_0_WIDTH 1U
+#define DP__DP_REGS__PMA_PLLCLK_EN_ACK_P__PMA_XCVR_PLLCLK_EN_ACK_LN_0_WOCLR 0U
+#define DP__DP_REGS__PMA_PLLCLK_EN_ACK_P__PMA_XCVR_PLLCLK_EN_ACK_LN_0_WOSET 0U
+#define DP__DP_REGS__PMA_PLLCLK_EN_ACK_P__PMA_XCVR_PLLCLK_EN_ACK_LN_1_MASK 0x00000002U
+#define DP__DP_REGS__PMA_PLLCLK_EN_ACK_P__PMA_XCVR_PLLCLK_EN_ACK_LN_1_SHIFT 1U
+#define DP__DP_REGS__PMA_PLLCLK_EN_ACK_P__PMA_XCVR_PLLCLK_EN_ACK_LN_1_WIDTH 1U
+#define DP__DP_REGS__PMA_PLLCLK_EN_ACK_P__PMA_XCVR_PLLCLK_EN_ACK_LN_1_WOCLR 0U
+#define DP__DP_REGS__PMA_PLLCLK_EN_ACK_P__PMA_XCVR_PLLCLK_EN_ACK_LN_1_WOSET 0U
+#define DP__DP_REGS__PMA_PLLCLK_EN_ACK_P__PMA_XCVR_PLLCLK_EN_ACK_LN_2_MASK 0x00000004U
+#define DP__DP_REGS__PMA_PLLCLK_EN_ACK_P__PMA_XCVR_PLLCLK_EN_ACK_LN_2_SHIFT 2U
+#define DP__DP_REGS__PMA_PLLCLK_EN_ACK_P__PMA_XCVR_PLLCLK_EN_ACK_LN_2_WIDTH 1U
+#define DP__DP_REGS__PMA_PLLCLK_EN_ACK_P__PMA_XCVR_PLLCLK_EN_ACK_LN_2_WOCLR 0U
+#define DP__DP_REGS__PMA_PLLCLK_EN_ACK_P__PMA_XCVR_PLLCLK_EN_ACK_LN_2_WOSET 0U
+#define DP__DP_REGS__PMA_PLLCLK_EN_ACK_P__PMA_XCVR_PLLCLK_EN_ACK_LN_3_MASK 0x00000008U
+#define DP__DP_REGS__PMA_PLLCLK_EN_ACK_P__PMA_XCVR_PLLCLK_EN_ACK_LN_3_SHIFT 3U
+#define DP__DP_REGS__PMA_PLLCLK_EN_ACK_P__PMA_XCVR_PLLCLK_EN_ACK_LN_3_WIDTH 1U
+#define DP__DP_REGS__PMA_PLLCLK_EN_ACK_P__PMA_XCVR_PLLCLK_EN_ACK_LN_3_WOCLR 0U
+#define DP__DP_REGS__PMA_PLLCLK_EN_ACK_P__PMA_XCVR_PLLCLK_EN_ACK_LN_3_WOSET 0U
+#define DP__DP_REGS__PMA_PLLCLK_EN_ACK_P__RESERVED_0_MASK 0xFFFFFFF0U
+#define DP__DP_REGS__PMA_PLLCLK_EN_ACK_P__RESERVED_0_SHIFT 4U
+#define DP__DP_REGS__PMA_PLLCLK_EN_ACK_P__RESERVED_0_WIDTH 28U
+
+#define DP__DP_REGS__PMA_POWER_STATE_REQ_P_READ_MASK 0xFFFFFFFFU
+#define DP__DP_REGS__PMA_POWER_STATE_REQ_P_WRITE_MASK 0xFFFFFFFFU
+#define DP__DP_REGS__PMA_POWER_STATE_REQ_P__PMA_XCVR_POWER_STATE_REQ_LN_0_MASK 0x0000003FU
+#define DP__DP_REGS__PMA_POWER_STATE_REQ_P__PMA_XCVR_POWER_STATE_REQ_LN_0_SHIFT 0U
+#define DP__DP_REGS__PMA_POWER_STATE_REQ_P__PMA_XCVR_POWER_STATE_REQ_LN_0_WIDTH 6U
+#define DP__DP_REGS__PMA_POWER_STATE_REQ_P__RESERVED_0_MASK 0x000000C0U
+#define DP__DP_REGS__PMA_POWER_STATE_REQ_P__RESERVED_0_SHIFT 6U
+#define DP__DP_REGS__PMA_POWER_STATE_REQ_P__RESERVED_0_WIDTH 2U
+#define DP__DP_REGS__PMA_POWER_STATE_REQ_P__PMA_XCVR_POWER_STATE_REQ_LN_1_MASK 0x00003F00U
+#define DP__DP_REGS__PMA_POWER_STATE_REQ_P__PMA_XCVR_POWER_STATE_REQ_LN_1_SHIFT 8U
+#define DP__DP_REGS__PMA_POWER_STATE_REQ_P__PMA_XCVR_POWER_STATE_REQ_LN_1_WIDTH 6U
+#define DP__DP_REGS__PMA_POWER_STATE_REQ_P__RESERVED_1_MASK 0x0000C000U
+#define DP__DP_REGS__PMA_POWER_STATE_REQ_P__RESERVED_1_SHIFT 14U
+#define DP__DP_REGS__PMA_POWER_STATE_REQ_P__RESERVED_1_WIDTH 2U
+#define DP__DP_REGS__PMA_POWER_STATE_REQ_P__PMA_XCVR_POWER_STATE_REQ_LN_2_MASK 0x003F0000U
+#define DP__DP_REGS__PMA_POWER_STATE_REQ_P__PMA_XCVR_POWER_STATE_REQ_LN_2_SHIFT 16U
+#define DP__DP_REGS__PMA_POWER_STATE_REQ_P__PMA_XCVR_POWER_STATE_REQ_LN_2_WIDTH 6U
+#define DP__DP_REGS__PMA_POWER_STATE_REQ_P__RESERVED_2_MASK 0x00C00000U
+#define DP__DP_REGS__PMA_POWER_STATE_REQ_P__RESERVED_2_SHIFT 22U
+#define DP__DP_REGS__PMA_POWER_STATE_REQ_P__RESERVED_2_WIDTH 2U
+#define DP__DP_REGS__PMA_POWER_STATE_REQ_P__PMA_XCVR_POWER_STATE_REQ_LN_3_MASK 0x3F000000U
+#define DP__DP_REGS__PMA_POWER_STATE_REQ_P__PMA_XCVR_POWER_STATE_REQ_LN_3_SHIFT 24U
+#define DP__DP_REGS__PMA_POWER_STATE_REQ_P__PMA_XCVR_POWER_STATE_REQ_LN_3_WIDTH 6U
+#define DP__DP_REGS__PMA_POWER_STATE_REQ_P__RESERVED_3_MASK 0xC0000000U
+#define DP__DP_REGS__PMA_POWER_STATE_REQ_P__RESERVED_3_SHIFT 30U
+#define DP__DP_REGS__PMA_POWER_STATE_REQ_P__RESERVED_3_WIDTH 2U
+
+#define DP__DP_REGS__PMA_POWER_STATE_ACK_P_READ_MASK 0xFFFFFFFFU
+#define DP__DP_REGS__PMA_POWER_STATE_ACK_P_WRITE_MASK 0xFFFFFFFFU
+#define DP__DP_REGS__PMA_POWER_STATE_ACK_P__PMA_XCVR_POWER_STATE_ACK_LN_0_MASK 0x0000003FU
+#define DP__DP_REGS__PMA_POWER_STATE_ACK_P__PMA_XCVR_POWER_STATE_ACK_LN_0_SHIFT 0U
+#define DP__DP_REGS__PMA_POWER_STATE_ACK_P__PMA_XCVR_POWER_STATE_ACK_LN_0_WIDTH 6U
+#define DP__DP_REGS__PMA_POWER_STATE_ACK_P__RESERVED_0_MASK 0x000000C0U
+#define DP__DP_REGS__PMA_POWER_STATE_ACK_P__RESERVED_0_SHIFT 6U
+#define DP__DP_REGS__PMA_POWER_STATE_ACK_P__RESERVED_0_WIDTH 2U
+#define DP__DP_REGS__PMA_POWER_STATE_ACK_P__PMA_XCVR_POWER_STATE_ACK_LN_1_MASK 0x00003F00U
+#define DP__DP_REGS__PMA_POWER_STATE_ACK_P__PMA_XCVR_POWER_STATE_ACK_LN_1_SHIFT 8U
+#define DP__DP_REGS__PMA_POWER_STATE_ACK_P__PMA_XCVR_POWER_STATE_ACK_LN_1_WIDTH 6U
+#define DP__DP_REGS__PMA_POWER_STATE_ACK_P__RESERVED_1_MASK 0x0000C000U
+#define DP__DP_REGS__PMA_POWER_STATE_ACK_P__RESERVED_1_SHIFT 14U
+#define DP__DP_REGS__PMA_POWER_STATE_ACK_P__RESERVED_1_WIDTH 2U
+#define DP__DP_REGS__PMA_POWER_STATE_ACK_P__PMA_XCVR_POWER_STATE_ACK_LN_2_MASK 0x003F0000U
+#define DP__DP_REGS__PMA_POWER_STATE_ACK_P__PMA_XCVR_POWER_STATE_ACK_LN_2_SHIFT 16U
+#define DP__DP_REGS__PMA_POWER_STATE_ACK_P__PMA_XCVR_POWER_STATE_ACK_LN_2_WIDTH 6U
+#define DP__DP_REGS__PMA_POWER_STATE_ACK_P__RESERVED_2_MASK 0x00C00000U
+#define DP__DP_REGS__PMA_POWER_STATE_ACK_P__RESERVED_2_SHIFT 22U
+#define DP__DP_REGS__PMA_POWER_STATE_ACK_P__RESERVED_2_WIDTH 2U
+#define DP__DP_REGS__PMA_POWER_STATE_ACK_P__PMA_XCVR_POWER_STATE_ACK_LN_3_MASK 0x3F000000U
+#define DP__DP_REGS__PMA_POWER_STATE_ACK_P__PMA_XCVR_POWER_STATE_ACK_LN_3_SHIFT 24U
+#define DP__DP_REGS__PMA_POWER_STATE_ACK_P__PMA_XCVR_POWER_STATE_ACK_LN_3_WIDTH 6U
+#define DP__DP_REGS__PMA_POWER_STATE_ACK_P__RESERVED_3_MASK 0xC0000000U
+#define DP__DP_REGS__PMA_POWER_STATE_ACK_P__RESERVED_3_SHIFT 30U
+#define DP__DP_REGS__PMA_POWER_STATE_ACK_P__RESERVED_3_WIDTH 2U
+
+#define DP__DP_REGS__PMA_CMN_READY_P_READ_MASK 0xFFFFFFFFU
+#define DP__DP_REGS__PMA_CMN_READY_P_WRITE_MASK 0xFFFFFFFFU
+#define DP__DP_REGS__PMA_CMN_READY_P__PMA_CMN_READY_MASK 0x00000001U
+#define DP__DP_REGS__PMA_CMN_READY_P__PMA_CMN_READY_SHIFT 0U
+#define DP__DP_REGS__PMA_CMN_READY_P__PMA_CMN_READY_WIDTH 1U
+#define DP__DP_REGS__PMA_CMN_READY_P__PMA_CMN_READY_WOCLR 0U
+#define DP__DP_REGS__PMA_CMN_READY_P__PMA_CMN_READY_WOSET 0U
+#define DP__DP_REGS__PMA_CMN_READY_P__RESERVED_0_MASK 0xFFFFFFFEU
+#define DP__DP_REGS__PMA_CMN_READY_P__RESERVED_0_SHIFT 1U
+#define DP__DP_REGS__PMA_CMN_READY_P__RESERVED_0_WIDTH 31U
+
+#define DP__DP_REGS__PMA_TX_VMARGIN_P_READ_MASK 0xFFFFFFFFU
+#define DP__DP_REGS__PMA_TX_VMARGIN_P_WRITE_MASK 0xFFFFFFFFU
+#define DP__DP_REGS__PMA_TX_VMARGIN_P__PMA_TX_VMARGIN_LN_0_MASK 0x00000003U
+#define DP__DP_REGS__PMA_TX_VMARGIN_P__PMA_TX_VMARGIN_LN_0_SHIFT 0U
+#define DP__DP_REGS__PMA_TX_VMARGIN_P__PMA_TX_VMARGIN_LN_0_WIDTH 2U
+#define DP__DP_REGS__PMA_TX_VMARGIN_P__RESERVED_0_MASK 0x000000FCU
+#define DP__DP_REGS__PMA_TX_VMARGIN_P__RESERVED_0_SHIFT 2U
+#define DP__DP_REGS__PMA_TX_VMARGIN_P__RESERVED_0_WIDTH 6U
+#define DP__DP_REGS__PMA_TX_VMARGIN_P__PMA_TX_VMARGIN_LN_1_MASK 0x00000300U
+#define DP__DP_REGS__PMA_TX_VMARGIN_P__PMA_TX_VMARGIN_LN_1_SHIFT 8U
+#define DP__DP_REGS__PMA_TX_VMARGIN_P__PMA_TX_VMARGIN_LN_1_WIDTH 2U
+#define DP__DP_REGS__PMA_TX_VMARGIN_P__RESERVED_1_MASK 0x0000FC00U
+#define DP__DP_REGS__PMA_TX_VMARGIN_P__RESERVED_1_SHIFT 10U
+#define DP__DP_REGS__PMA_TX_VMARGIN_P__RESERVED_1_WIDTH 6U
+#define DP__DP_REGS__PMA_TX_VMARGIN_P__PMA_TX_VMARGIN_LN_2_MASK 0x00030000U
+#define DP__DP_REGS__PMA_TX_VMARGIN_P__PMA_TX_VMARGIN_LN_2_SHIFT 16U
+#define DP__DP_REGS__PMA_TX_VMARGIN_P__PMA_TX_VMARGIN_LN_2_WIDTH 2U
+#define DP__DP_REGS__PMA_TX_VMARGIN_P__RESERVED_2_MASK 0x00FC0000U
+#define DP__DP_REGS__PMA_TX_VMARGIN_P__RESERVED_2_SHIFT 18U
+#define DP__DP_REGS__PMA_TX_VMARGIN_P__RESERVED_2_WIDTH 6U
+#define DP__DP_REGS__PMA_TX_VMARGIN_P__PMA_TX_VMARGIN_LN_3_MASK 0x03000000U
+#define DP__DP_REGS__PMA_TX_VMARGIN_P__PMA_TX_VMARGIN_LN_3_SHIFT 24U
+#define DP__DP_REGS__PMA_TX_VMARGIN_P__PMA_TX_VMARGIN_LN_3_WIDTH 2U
+#define DP__DP_REGS__PMA_TX_VMARGIN_P__RESERVED_3_MASK 0xFC000000U
+#define DP__DP_REGS__PMA_TX_VMARGIN_P__RESERVED_3_SHIFT 26U
+#define DP__DP_REGS__PMA_TX_VMARGIN_P__RESERVED_3_WIDTH 6U
+
+#define DP__DP_REGS__PMA_TX_DEEMPH_P_READ_MASK 0xFFFFFFFFU
+#define DP__DP_REGS__PMA_TX_DEEMPH_P_WRITE_MASK 0xFFFFFFFFU
+#define DP__DP_REGS__PMA_TX_DEEMPH_P__PMA_TX_DEEMPHASIS_LN_0_MASK 0x00000003U
+#define DP__DP_REGS__PMA_TX_DEEMPH_P__PMA_TX_DEEMPHASIS_LN_0_SHIFT 0U
+#define DP__DP_REGS__PMA_TX_DEEMPH_P__PMA_TX_DEEMPHASIS_LN_0_WIDTH 2U
+#define DP__DP_REGS__PMA_TX_DEEMPH_P__RESERVED_0_MASK 0x000000FCU
+#define DP__DP_REGS__PMA_TX_DEEMPH_P__RESERVED_0_SHIFT 2U
+#define DP__DP_REGS__PMA_TX_DEEMPH_P__RESERVED_0_WIDTH 6U
+#define DP__DP_REGS__PMA_TX_DEEMPH_P__PMA_TX_DEEMPHASIS_LN_1_MASK 0x00000300U
+#define DP__DP_REGS__PMA_TX_DEEMPH_P__PMA_TX_DEEMPHASIS_LN_1_SHIFT 8U
+#define DP__DP_REGS__PMA_TX_DEEMPH_P__PMA_TX_DEEMPHASIS_LN_1_WIDTH 2U
+#define DP__DP_REGS__PMA_TX_DEEMPH_P__RESERVED_1_MASK 0x0000FC00U
+#define DP__DP_REGS__PMA_TX_DEEMPH_P__RESERVED_1_SHIFT 10U
+#define DP__DP_REGS__PMA_TX_DEEMPH_P__RESERVED_1_WIDTH 6U
+#define DP__DP_REGS__PMA_TX_DEEMPH_P__PMA_TX_DEEMPHASIS_LN_2_MASK 0x00030000U
+#define DP__DP_REGS__PMA_TX_DEEMPH_P__PMA_TX_DEEMPHASIS_LN_2_SHIFT 16U
+#define DP__DP_REGS__PMA_TX_DEEMPH_P__PMA_TX_DEEMPHASIS_LN_2_WIDTH 2U
+#define DP__DP_REGS__PMA_TX_DEEMPH_P__RESERVED_2_MASK 0x00FC0000U
+#define DP__DP_REGS__PMA_TX_DEEMPH_P__RESERVED_2_SHIFT 18U
+#define DP__DP_REGS__PMA_TX_DEEMPH_P__RESERVED_2_WIDTH 6U
+#define DP__DP_REGS__PMA_TX_DEEMPH_P__PMA_TX_DEEMPHASIS_LN_3_MASK 0x03000000U
+#define DP__DP_REGS__PMA_TX_DEEMPH_P__PMA_TX_DEEMPHASIS_LN_3_SHIFT 24U
+#define DP__DP_REGS__PMA_TX_DEEMPH_P__PMA_TX_DEEMPHASIS_LN_3_WIDTH 2U
+#define DP__DP_REGS__PMA_TX_DEEMPH_P__RESERVED_3_MASK 0xFC000000U
+#define DP__DP_REGS__PMA_TX_DEEMPH_P__RESERVED_3_SHIFT 26U
+#define DP__DP_REGS__PMA_TX_DEEMPH_P__RESERVED_3_WIDTH 6U
+
+#endif /* REG_DP_REGS_MACROS_H_ */
+
+/* parasoft-end-suppress MISRA2012-RULE-5_4_b_c99-2 "C99 - similar names, DRV-4756" */
+/* parasoft-end-suppress MISRA2012-RULE-5_4_b_c90-2 "C90 - similar names, DRV-4756" */
+/* parasoft-end-suppress MISRA2012-RULE-1_1_b_c99-2 "C99 - limits, DRV-4754" */
+/* parasoft-end-suppress MISRA2012-RULE-1_1_b_c90-2 "C90 - limits, DRV-4754" */
+
diff --git a/packages/ti/drv/dss/src/csl/dp_sd0801/src/dp_sd0801.c b/packages/ti/drv/dss/src/csl/dp_sd0801/src/dp_sd0801.c
--- /dev/null
@@ -0,0 +1,258 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ *
+ * dp_afe_sd0801.c
+ *
+ ******************************************************************************
+ */
+
+#include "dp_sd0801_if.h"
+#include "dp_sd0801_priv.h"
+#include "dp_sd0801_sanity.h"
+#include "dp_regs.h"
+
+#include "cdn_log.h"
+
+#include "dp_sd0801_internal.h"
+
+bool isPhySupported(const DP_SD0801_PrivateData* pD);
+
+/**
+ * Adapt address to bus and write to PHY APB.
+ */
+void afeWrite(const DP_SD0801_PrivateData* pD, uint32_t offset, uint16_t val)
+{
+ CPS_REG_WRITE(&(pD->regBase[offset]), val);
+}
+
+/**
+ * Adapt address to bus and read from PHY APB.
+ */
+uint16_t afeRead(const DP_SD0801_PrivateData* pD, uint32_t offset)
+{
+ return (uint16_t)(CPS_REG_READ(&(pD->regBase[offset])));
+}
+
+/**
+ * Write value to PHY register, but only if that's required (when value
+ * provided to function is different from one already in register)
+ */
+void afeWriteChanged(const DP_SD0801_PrivateData* pD, uint32_t offset, uint16_t val)
+{
+ uint16_t reg_val = afeRead(pD, offset);
+ if (val != reg_val)
+ {
+ afeWrite(pD, offset, val);
+ }
+}
+
+/**
+ * Fill table of voltage-related coefficients with default values.
+ */
+static uint32_t fillDefaultCoefficients(DP_SD0801_PrivateData* pD)
+{
+ uint8_t i;
+ uint8_t j;
+ uint32_t retVal = CDN_EOK;
+
+ for (i = 0U; i < DP_SD0801_SWING_LEVEL_COUNT; i++) {
+ for (j = 0U; j < DP_SD0801_EMPHASIS_LEVEL_COUNT; j++) {
+ if (CDN_EOK == retVal) {
+ /* Put values in driver's Private Data. */
+ retVal = DP_SD0801_GetDefaultCoeffs(pD, i, j, &(pD->vCoeffs[i][j]));
+ }
+ }
+ }
+
+ return retVal;
+}
+
+/**
+ * Get memory requirements of the driver
+ */
+uint32_t DP_SD0801_Probe(const DP_SD0801_Config* config, uint32_t* memReq)
+{
+ uint32_t retVal = CDN_EOK;
+ if (CDN_EOK != DP_SD0801_ProbeSF(config, memReq)) {
+ retVal = CDN_EINVAL;
+ } else {
+ /* No more memory, than for driver's Private Data, is required. */
+ *memReq = (uint32_t)(sizeof(DP_SD0801_PrivateData));
+ }
+ return retVal;
+}
+
+uint32_t DP_SD0801_Init(DP_SD0801_PrivateData* pD, const DP_SD0801_Config* config)
+{
+ uint32_t retVal;
+ uint8_t i;
+
+ retVal = DP_SD0801_InitSF(pD, config);
+
+ if (CDN_EOK == retVal) {
+ /* Assign addresses of register bases from configuration. */
+ pD->regBase = config->regBase;
+ pD->regBaseDp = config->regBaseDp;
+ pD->linkState.laneCount = 0; /* Indicates uninitialized PHY driver. */
+ pD->linkState.linkRate = DP_SD0801_LINK_RATE_1_62;
+ for (i = 0; i < 4U; i++)
+ {
+ pD->linkState.voltageSwing[i] = 0;
+ pD->linkState.preEmphasis[i] = 0;
+ }
+ /* put default voltage coefficients to Private Data (may be modified later). */
+ retVal = fillDefaultCoefficients(pD);
+ }
+ if (CDN_EOK == retVal)
+ {
+ if (!isPhySupported(pD))
+ {
+ retVal = CDN_ENOTSUP;
+ }
+ }
+
+ return retVal;
+}
+
+/**
+ * Assert or release PHY reset signal.
+ */
+uint32_t DP_SD0801_PhySetReset(const DP_SD0801_PrivateData* pD, bool reset)
+{
+ uint32_t regTmp;
+ uint32_t retVal = CDN_EOK;
+
+ retVal = DP_SD0801_PhySetResetSF(pD);
+
+ if (CDN_EOK == retVal)
+ {
+ /* Set or clear PHY_RESET bit in register. */
+ regTmp = CPS_REG_READ(&pD->regBaseDp->dp_regs.PHY_RESET_p);
+ regTmp = CPS_FLD_WRITE(DP__DP_REGS__PHY_RESET_P, PHY_RESET, regTmp, (reset ? 0 : 1));
+ CPS_REG_WRITE(&pD->regBaseDp->dp_regs.PHY_RESET_p, regTmp);
+
+ CPS_ExtPhyReset(reset);
+ }
+ return retVal;
+}
+
+/**
+ * Get current values of voltage-related PHY registers, for given voltage
+ * swing and pre-emphasis.
+ */
+uint32_t DP_SD0801_GetCoefficients(const DP_SD0801_PrivateData* pD,
+ uint8_t voltageSwing,
+ uint8_t preEmphasis,
+ DP_SD0801_VoltageCoefficients* coefficients)
+{
+ uint32_t retVal;
+ retVal = DP_SD0801_GetCoefficientsSF(pD, voltageSwing, preEmphasis, coefficients);
+
+ if (CDN_EOK == retVal)
+ {
+ /* Fill the structure. */
+ coefficients->DiagTxDrv = pD->vCoeffs[voltageSwing][preEmphasis].DiagTxDrv;
+ coefficients->MgnfsMult = pD->vCoeffs[voltageSwing][preEmphasis].MgnfsMult;
+ coefficients->CpostMult = pD->vCoeffs[voltageSwing][preEmphasis].CpostMult;
+ }
+
+ return retVal;
+}
+
+/**
+ * Set values of voltage-related PHY registers, to be used for given
+ * voltage swing and pre-emphasis.
+ */
+uint32_t DP_SD0801_SetCoefficients(DP_SD0801_PrivateData* pD,
+ uint8_t voltageSwing,
+ uint8_t preEmphasis,
+ const DP_SD0801_VoltageCoefficients* coefficients)
+{
+ uint32_t retVal;
+ retVal = DP_SD0801_SetCoefficientsSF(pD, voltageSwing, preEmphasis, coefficients);
+
+ if (CDN_EOK == retVal)
+ {
+ /* Set values from provided structure. */
+ pD->vCoeffs[voltageSwing][preEmphasis].DiagTxDrv = coefficients->DiagTxDrv;
+ pD->vCoeffs[voltageSwing][preEmphasis].MgnfsMult = coefficients->MgnfsMult;
+ pD->vCoeffs[voltageSwing][preEmphasis].CpostMult = coefficients->CpostMult;
+ }
+
+ return retVal;
+}
+
+/**
+ * Get current link status.
+ */
+uint32_t DP_SD0801_ReadLinkStat(const DP_SD0801_PrivateData* pD, DP_SD0801_LinkState* linkState)
+{
+ uint32_t retVal = DP_SD0801_ReadLinkStatSF(pD, linkState);
+ if (CDN_EOK == retVal)
+ {
+ /* Copy structure from driver's private data to one provided by user. */
+ CPS_BufferCopy((uint8_t*)linkState,
+ (const uint8_t*)(&(pD->linkState)),
+ (uint32_t)sizeof(DP_SD0801_LinkState));
+ }
+
+ return retVal;
+}
+
+/**
+ * Automatically initialize and configure DP Main Link on PHY.
+ */
+uint32_t DP_SD0801_PhyStartUp(DP_SD0801_PrivateData* pD, uint8_t laneCount, DP_SD0801_LinkRate linkRate)
+{
+ uint32_t retVal;
+
+ retVal = DP_SD0801_PhyStartUpSF(pD, linkRate);
+
+ if (CDN_EOK == retVal) {
+ /* Perform operations to be done before releasing reset. */
+ retVal = DP_SD0801_PhyInit(pD, laneCount, linkRate);
+ }
+
+ if (CDN_EOK == retVal) {
+ /* release PHY reset */
+ retVal = DP_SD0801_PhySetReset(pD, false);
+ }
+
+ if (CDN_EOK == retVal) {
+ retVal = DP_SD0801_WaitPmaCmnReady(pD);
+ }
+
+ if (CDN_EOK == retVal) {
+ /* Perform operations to be done after releasing reset. */
+ retVal = DP_SD0801_PhyRun(pD, laneCount);
+ }
+
+ return retVal;
+}
diff --git a/packages/ti/drv/dss/src/csl/dp_sd0801/src/dp_sd0801_internal.h b/packages/ti/drv/dss/src/csl/dp_sd0801/src/dp_sd0801_internal.h
--- /dev/null
@@ -0,0 +1,47 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ *
+ * dp_sd0801_internal.h
+ *
+ ******************************************************************************
+ */
+
+#ifndef DP_SD0801_INERNAL_H
+#define DP_SD0801_INERNAL_H
+
+/* parasoft-begin-suppress METRICS-36-3 "Function called from more than 5 different functions, DRV-3823" */
+
+void afeWrite(const DP_SD0801_PrivateData* pD, uint32_t offset, uint16_t val);
+uint16_t afeRead(const DP_SD0801_PrivateData* pD, uint32_t offset);
+void afeWriteChanged(const DP_SD0801_PrivateData* pD, uint32_t offset, uint16_t val);
+
+/* parasoft-end-suppress METRICS-36-3 */
+
+#endif /* DP_SD0801_INERNAL_H */
diff --git a/packages/ti/drv/dss/src/csl/dp_sd0801/src/dp_sd0801_obj_if.c b/packages/ti/drv/dss/src/csl/dp_sd0801/src/dp_sd0801_obj_if.c
--- /dev/null
@@ -0,0 +1,63 @@
+/**********************************************************************
+* Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* 1. Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* 2. Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the distribution.
+* 3. Neither the name of the copyright holder nor the names of its
+* contributors may be used to endorse or promote products derived from
+* this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+**********************************************************************
+* WARNING: This file is auto-generated using api-generator utility.
+* api-generator: 12.03.9e11b77(origin/DRV-3827_extract_sanity_to_c_file)
+* Do not edit it manually.
+**********************************************************************
+* Cadence Core Driver for the Cadence DP_SD0801 PHY for DisplayPort (DP)
+* core. This header file lists the API providing a HAL (hardware
+* abstraction layer) interface for the DP_SD0801 "Torrent" core.
+**********************************************************************/
+
+#include "dp_sd0801_obj_if.h"
+
+/* parasoft suppress item METRICS-41-3 "Number of blocks of comments per statement" */
+
+DP_SD0801_OBJ *DP_SD0801_GetInstance(void)
+{
+ static DP_SD0801_OBJ driver =
+ {
+ .probe = DP_SD0801_Probe,
+ .init = DP_SD0801_Init,
+ .configurePhyAuxCtrl = DP_SD0801_ConfigurePhyAuxCtrl,
+ .phyStartUp = DP_SD0801_PhyStartUp,
+ .PhyInit = DP_SD0801_PhyInit,
+ .phySetReset = DP_SD0801_PhySetReset,
+ .waitPmaCmnReady = DP_SD0801_WaitPmaCmnReady,
+ .phyRun = DP_SD0801_PhyRun,
+ .configLane = DP_SD0801_ConfigLane,
+ .setLinkRate = DP_SD0801_SetLinkRate,
+ .enableLanes = DP_SD0801_EnableLanes,
+ .getDefaultCoeffs = DP_SD0801_GetDefaultCoeffs,
+ .getCoefficients = DP_SD0801_GetCoefficients,
+ .setCoefficients = DP_SD0801_SetCoefficients,
+ .readLinkStat = DP_SD0801_ReadLinkStat,
+ };
+
+ return &driver;
+}
diff --git a/packages/ti/drv/dss/src/csl/dp_sd0801/src/dp_sd0801_priv.h b/packages/ti/drv/dss/src/csl/dp_sd0801/src/dp_sd0801_priv.h
--- /dev/null
@@ -0,0 +1,84 @@
+/**********************************************************************
+* Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* 1. Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* 2. Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the distribution.
+* 3. Neither the name of the copyright holder nor the names of its
+* contributors may be used to endorse or promote products derived from
+* this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+**********************************************************************
+* WARNING: This file is auto-generated using api-generator utility.
+* api-generator: 12.03.9e11b77(origin/DRV-3827_extract_sanity_to_c_file)
+* Do not edit it manually.
+**********************************************************************
+* Cadence Core Driver for the Cadence DP_SD0801 PHY for DisplayPort (DP)
+* core. This header file lists the API providing a HAL (hardware
+* abstraction layer) interface for the DP_SD0801 "Torrent" core.
+**********************************************************************/
+
+#ifndef DP_SD0801_PRIV_H
+#define DP_SD0801_PRIV_H
+
+/* parasoft-begin-suppress MISRA2012-RULE-1_1_a_c90-2 "C90 - limits, DRV-3906" */
+/* parasoft-begin-suppress MISRA2012-RULE-1_1_b_c90-2 "C90 - limits, DRV-3906" */
+/* parasoft suppress item MISRA2012-DIR-4_8 "Consider hiding implementation of structure" */
+
+#include "dp_sd0801_structs_if.h"
+
+/** @defgroup DataStructure Dynamic Data Structures
+ * This section defines the data structures used by the driver to provide
+ * hardware information, modification and dynamic operation of the driver.
+ * These data structures are defined in the header file of the core driver
+ * and utilized by the API.
+ * @{
+ */
+
+/**********************************************************************
+* Structures and unions
+**********************************************************************/
+/**
+ * Structure contains private data for Core Driver that should not be used by
+ * upper layers. This is not a part of API and manipulation of those data may cause
+ * unpredictable behaviour of Core Driver.
+ */
+struct DP_SD0801_PrivateData_s
+{
+ /** Base address of the PHY APB register space. */
+ uint32_t* regBase;
+ /** Base address of the DPTX controller's register space. */
+ struct DP_Regs_s* regBaseDp;
+ /** structure used to store current link state. */
+ DP_SD0801_LinkState linkState;
+ /**
+ * Array of voltage-related PHY register values, for given voltage swing
+ * (first array index, 0-3) and pre-emphasis (second array index, 0-3).
+ */
+ DP_SD0801_VoltageCoefficients vCoeffs[DP_SD0801_SWING_LEVEL_COUNT][DP_SD0801_EMPHASIS_LEVEL_COUNT];
+};
+
+/**
+ * @}
+ */
+
+/* parasoft-end-suppress MISRA2012-RULE-1_1_b_c90-2 */
+/* parasoft-end-suppress MISRA2012-RULE-1_1_a_c90-2 */
+
+#endif /* DP_SD0801_PRIV_H */
diff --git a/packages/ti/drv/dss/src/csl/dp_sd0801/src/dp_sd0801_sanity.c b/packages/ti/drv/dss/src/csl/dp_sd0801/src/dp_sd0801_sanity.c
--- /dev/null
@@ -0,0 +1,432 @@
+/**********************************************************************
+* Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* 1. Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* 2. Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the distribution.
+* 3. Neither the name of the copyright holder nor the names of its
+* contributors may be used to endorse or promote products derived from
+* this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+**********************************************************************
+* WARNING: This file is auto-generated using api-generator utility.
+* api-generator: 12.03.9e11b77(origin/DRV-3827_extract_sanity_to_c_file)
+* Do not edit it manually.
+**********************************************************************
+* Cadence Core Driver for the Cadence DP_SD0801 PHY for DisplayPort (DP)
+* core. This header file lists the API providing a HAL (hardware
+* abstraction layer) interface for the DP_SD0801 "Torrent" core.
+**********************************************************************/
+
+/* parasoft-begin-suppress METRICS-18-3 "Follow the Cyclomatic Complexity limit of 10" */
+/* parasoft-begin-suppress METRICS-36-3 "A function should not be called from more than 5 different functions" */
+/* parasoft-begin-suppress METRICS-39-3 "The value of VOCF metric for a function should not be higher than 4" */
+/* parasoft-begin-suppress METRICS-41-3 "Number of blocks of comments per statement" */
+/* parasoft-begin-suppress MISRA2012-RULE-8_7 "Functions and objects should not be defined with external linkage if they are referenced in only one translation unit" */
+
+/**
+ * This file contains sanity API functions. The purpose of sanity functions
+ * is to check input parameters validity. They take the same parameters as
+ * original API functions and return 0 on success or CDN_EINVAL on wrong parameter
+ * value(s).
+ */
+
+#include "cdn_errno.h"
+#include "cdn_stdtypes.h"
+#include "dp_sd0801_priv.h"
+#include "dp_sd0801_sanity.h"
+
+/**
+ * Function to validate struct VoltageCoefficients
+ *
+ * @param[in] obj pointer to struct to be verified
+ * @returns 0 for valid
+ * @returns CDN_EINVAL for invalid
+ */
+uint32_t DP_SD0801_VoltageCoefficientSF(const DP_SD0801_VoltageCoefficients *obj)
+{
+ uint32_t ret = 0;
+
+ if (obj == NULL)
+ {
+ ret = CDN_EINVAL;
+ }
+
+ return ret;
+}
+
+/**
+ * Function to validate struct LinkState
+ *
+ * @param[in] obj pointer to struct to be verified
+ * @returns 0 for valid
+ * @returns CDN_EINVAL for invalid
+ */
+uint32_t DP_SD0801_LinkStateSF(const DP_SD0801_LinkState *obj)
+{
+ uint32_t ret = 0;
+
+ if (obj == NULL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ if (
+ (obj->linkRate != DP_SD0801_LINK_RATE_1_62) &&
+ (obj->linkRate != DP_SD0801_LINK_RATE_2_16) &&
+ (obj->linkRate != DP_SD0801_LINK_RATE_2_43) &&
+ (obj->linkRate != DP_SD0801_LINK_RATE_2_70) &&
+ (obj->linkRate != DP_SD0801_LINK_RATE_3_24) &&
+ (obj->linkRate != DP_SD0801_LINK_RATE_4_32) &&
+ (obj->linkRate != DP_SD0801_LINK_RATE_5_40) &&
+ (obj->linkRate != DP_SD0801_LINK_RATE_8_10)
+ )
+ {
+ ret = CDN_EINVAL;
+ }
+ }
+
+ return ret;
+}
+
+/**
+ * Function to validate struct Config
+ *
+ * @param[in] obj pointer to struct to be verified
+ * @returns 0 for valid
+ * @returns CDN_EINVAL for invalid
+ */
+uint32_t DP_SD0801_ConfigSF(const DP_SD0801_Config *obj)
+{
+ uint32_t ret = 0;
+
+ if (obj == NULL)
+ {
+ ret = CDN_EINVAL;
+ }
+
+ return ret;
+}
+
+/**
+ * Function to validate struct PrivateData
+ *
+ * @param[in] obj pointer to struct to be verified
+ * @returns 0 for valid
+ * @returns CDN_EINVAL for invalid
+ */
+uint32_t DP_SD0801_PrivateDataSF(const DP_SD0801_PrivateData *obj)
+{
+ uint32_t ret = 0;
+
+ if (obj == NULL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ if (DP_SD0801_LinkStateSF(&obj->linkState) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ }
+
+ return ret;
+}
+
+/**
+ * A common function to check the validity of API functions with
+ * following parameter types
+ * @param[in] config Driver/hardware configuration.
+ * @param[out] memReq Size of memory, that needs to be allocated (in bytes).
+ * @return 0 success
+ * @return CDN_EINVAL invalid parameters
+ */
+uint32_t DP_SD0801_SanityFunction1(const DP_SD0801_Config* config, const uint32_t* memReq)
+{
+ /* Declaring return variable */
+ uint32_t ret = 0;
+
+ if (memReq == NULL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (DP_SD0801_ConfigSF(config) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ /*
+ * All 'if ... else if' constructs shall be terminated with an 'else' statement
+ * (MISRA2012-RULE-15_7-3)
+ */
+ }
+
+ return ret;
+}
+
+/**
+ * A common function to check the validity of API functions with
+ * following parameter types
+ * @param[in,out] pD Driver state info specific to this instance.
+ * @param[in] config Specifies driver/hardware configuration.
+ * @return 0 success
+ * @return CDN_EINVAL invalid parameters
+ */
+uint32_t DP_SD0801_SanityFunction2(const DP_SD0801_PrivateData* pD, const DP_SD0801_Config* config)
+{
+ /* Declaring return variable */
+ uint32_t ret = 0;
+
+ if (pD == NULL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (DP_SD0801_ConfigSF(config) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ /*
+ * All 'if ... else if' constructs shall be terminated with an 'else' statement
+ * (MISRA2012-RULE-15_7-3)
+ */
+ }
+
+ return ret;
+}
+
+/**
+ * A common function to check the validity of API functions with
+ * following parameter types
+ * @param[in] pD Driver state info specific to this instance.
+ * @return 0 success
+ * @return CDN_EINVAL invalid parameters
+ */
+uint32_t DP_SD0801_SanityFunction3(const DP_SD0801_PrivateData* pD)
+{
+ /* Declaring return variable */
+ uint32_t ret = 0;
+
+ if (DP_SD0801_PrivateDataSF(pD) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+
+ return ret;
+}
+
+/**
+ * A common function to check the validity of API functions with
+ * following parameter types
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] linkRate Link rate to initialize PHY with.
+ * @return 0 success
+ * @return CDN_EINVAL invalid parameters
+ */
+uint32_t DP_SD0801_SanityFunction4(const DP_SD0801_PrivateData* pD, const DP_SD0801_LinkRate linkRate)
+{
+ /* Declaring return variable */
+ uint32_t ret = 0;
+
+ if (DP_SD0801_PrivateDataSF(pD) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (
+ (linkRate != DP_SD0801_LINK_RATE_1_62) &&
+ (linkRate != DP_SD0801_LINK_RATE_2_16) &&
+ (linkRate != DP_SD0801_LINK_RATE_2_43) &&
+ (linkRate != DP_SD0801_LINK_RATE_2_70) &&
+ (linkRate != DP_SD0801_LINK_RATE_3_24) &&
+ (linkRate != DP_SD0801_LINK_RATE_4_32) &&
+ (linkRate != DP_SD0801_LINK_RATE_5_40) &&
+ (linkRate != DP_SD0801_LINK_RATE_8_10)
+ )
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ /*
+ * All 'if ... else if' constructs shall be terminated with an 'else' statement
+ * (MISRA2012-RULE-15_7-3)
+ */
+ }
+
+ return ret;
+}
+
+/**
+ * A common function to check the validity of API functions with
+ * following parameter types
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] linkState Pointer to structure with link state, containing lane settings to use.
+ *
+ * @return 0 success
+ * @return CDN_EINVAL invalid parameters
+ */
+uint32_t DP_SD0801_SanityFunction9(const DP_SD0801_PrivateData* pD, const DP_SD0801_LinkState* linkState)
+{
+ /* Declaring return variable */
+ uint32_t ret = 0;
+
+ if (DP_SD0801_PrivateDataSF(pD) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (DP_SD0801_LinkStateSF(linkState) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ /*
+ * All 'if ... else if' constructs shall be terminated with an 'else' statement
+ * (MISRA2012-RULE-15_7-3)
+ */
+ }
+
+ return ret;
+}
+
+/**
+ * A common function to check the validity of API functions with
+ * following parameter types
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] voltageSwing Voltage swing level to use to select register values.
+ * @param[in] preEmphasis Pre-emphasis level to use to select register values.
+ * @param[out] coefficients Pointer to struct to be filled with default values of coefficients.
+ * @return 0 success
+ * @return CDN_EINVAL invalid parameters
+ */
+uint32_t DP_SD0801_SanityFunction12(const DP_SD0801_PrivateData* pD, const uint8_t voltageSwing, const uint8_t preEmphasis, const DP_SD0801_VoltageCoefficients* coefficients)
+{
+ /* Declaring return variable */
+ uint32_t ret = 0;
+
+ if (coefficients == NULL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (DP_SD0801_PrivateDataSF(pD) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (voltageSwing > ((DP_SD0801_SWING_LEVEL_COUNT - 1U)))
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (preEmphasis > ((DP_SD0801_EMPHASIS_LEVEL_COUNT - 1U)))
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ /*
+ * All 'if ... else if' constructs shall be terminated with an 'else' statement
+ * (MISRA2012-RULE-15_7-3)
+ */
+ }
+
+ return ret;
+}
+
+/**
+ * A common function to check the validity of API functions with
+ * following parameter types
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] voltageSwing Voltage swing level to use to select register values.
+ * @param[in] preEmphasis Pre-emphasis level to use to select register values.
+ * @param[in] coefficients Pointer to struct containing values of coefficients to use.
+ * @return 0 success
+ * @return CDN_EINVAL invalid parameters
+ */
+uint32_t DP_SD0801_SanityFunction14(const DP_SD0801_PrivateData* pD, const uint8_t voltageSwing, const uint8_t preEmphasis, const DP_SD0801_VoltageCoefficients* coefficients)
+{
+ /* Declaring return variable */
+ uint32_t ret = 0;
+
+ if (DP_SD0801_PrivateDataSF(pD) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (voltageSwing > ((DP_SD0801_SWING_LEVEL_COUNT - 1U)))
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (preEmphasis > ((DP_SD0801_EMPHASIS_LEVEL_COUNT - 1U)))
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (DP_SD0801_VoltageCoefficientSF(coefficients) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ /*
+ * All 'if ... else if' constructs shall be terminated with an 'else' statement
+ * (MISRA2012-RULE-15_7-3)
+ */
+ }
+
+ return ret;
+}
+
+/**
+ * A common function to check the validity of API functions with
+ * following parameter types
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] linkState Link State.
+ * @return 0 success
+ * @return CDN_EINVAL invalid parameters
+ */
+uint32_t DP_SD0801_SanityFunction15(const DP_SD0801_PrivateData* pD, const DP_SD0801_LinkState* linkState)
+{
+ /* Declaring return variable */
+ uint32_t ret = 0;
+
+ if (linkState == NULL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (DP_SD0801_PrivateDataSF(pD) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ /*
+ * All 'if ... else if' constructs shall be terminated with an 'else' statement
+ * (MISRA2012-RULE-15_7-3)
+ */
+ }
+
+ return ret;
+}
+
+/* parasoft-end-suppress MISRA2012-RULE-8_7 */
+/* parasoft-end-suppress METRICS-41-3 */
+/* parasoft-end-suppress METRICS-39-3 */
+/* parasoft-end-suppress METRICS-36-3 */
+/* parasoft-end-suppress METRICS-18-3 */
diff --git a/packages/ti/drv/dss/src/csl/dp_sd0801/src/dp_sd0801_sanity.h b/packages/ti/drv/dss/src/csl/dp_sd0801/src/dp_sd0801_sanity.h
--- /dev/null
@@ -0,0 +1,93 @@
+/**********************************************************************
+* Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* 1. Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* 2. Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the distribution.
+* 3. Neither the name of the copyright holder nor the names of its
+* contributors may be used to endorse or promote products derived from
+* this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+* POSSIBILITY OF SUCH DAMAGE.
+**********************************************************************
+* WARNING: This file is auto-generated using api-generator utility.
+* api-generator: 12.03.9e11b77(origin/DRV-3827_extract_sanity_to_c_file)
+* Do not edit it manually.
+**********************************************************************
+* Cadence Core Driver for the Cadence DP_SD0801 PHY for DisplayPort (DP)
+* core. This header file lists the API providing a HAL (hardware
+* abstraction layer) interface for the DP_SD0801 "Torrent" core.
+**********************************************************************/
+
+/* parasoft-begin-suppress METRICS-18-3 "Follow the Cyclomatic Complexity limit of 10" */
+/* parasoft-begin-suppress METRICS-36-3 "A function should not be called from more than 5 different functions" */
+/* parasoft-begin-suppress METRICS-39-3 "The value of VOCF metric for a function should not be higher than 4" */
+/* parasoft-begin-suppress METRICS-41-3 "Number of blocks of comments per statement" */
+/* parasoft-begin-suppress MISRA2012-RULE-8_7 "Functions and objects should not be defined with external linkage if they are referenced in only one translation unit" */
+
+/**
+ * This file contains sanity API functions. The purpose of sanity functions
+ * is to check input parameters validity. They take the same parameters as
+ * original API functions and return 0 on success or CDN_EINVAL on wrong parameter
+ * value(s).
+ */
+
+#ifndef DP_SD0801_SANITY_H
+#define DP_SD0801_SANITY_H
+
+#include "cdn_errno.h"
+#include "cdn_stdtypes.h"
+#include "dp_sd0801_if.h"
+
+uint32_t DP_SD0801_ConfigSF(const DP_SD0801_Config *obj);
+uint32_t DP_SD0801_LinkStateSF(const DP_SD0801_LinkState *obj);
+uint32_t DP_SD0801_PrivateDataSF(const DP_SD0801_PrivateData *obj);
+uint32_t DP_SD0801_VoltageCoefficientSF(const DP_SD0801_VoltageCoefficients *obj);
+
+uint32_t DP_SD0801_SanityFunction1(const DP_SD0801_Config* config, const uint32_t* memReq);
+uint32_t DP_SD0801_SanityFunction2(const DP_SD0801_PrivateData* pD, const DP_SD0801_Config* config);
+uint32_t DP_SD0801_SanityFunction3(const DP_SD0801_PrivateData* pD);
+uint32_t DP_SD0801_SanityFunction4(const DP_SD0801_PrivateData* pD, const DP_SD0801_LinkRate linkRate);
+uint32_t DP_SD0801_SanityFunction9(const DP_SD0801_PrivateData* pD, const DP_SD0801_LinkState* linkState);
+uint32_t DP_SD0801_SanityFunction12(const DP_SD0801_PrivateData* pD, const uint8_t voltageSwing, const uint8_t preEmphasis, const DP_SD0801_VoltageCoefficients* coefficients);
+uint32_t DP_SD0801_SanityFunction14(const DP_SD0801_PrivateData* pD, const uint8_t voltageSwing, const uint8_t preEmphasis, const DP_SD0801_VoltageCoefficients* coefficients);
+uint32_t DP_SD0801_SanityFunction15(const DP_SD0801_PrivateData* pD, const DP_SD0801_LinkState* linkState);
+
+#define DP_SD0801_ProbeSF DP_SD0801_SanityFunction1
+#define DP_SD0801_InitSF DP_SD0801_SanityFunction2
+#define DP_SD0801_ConfigurePhyAuxCtrSF DP_SD0801_SanityFunction3
+#define DP_SD0801_PhyStartUpSF DP_SD0801_SanityFunction4
+#define DP_SD0801_PhyInitSF DP_SD0801_SanityFunction3
+#define DP_SD0801_PhySetResetSF DP_SD0801_SanityFunction3
+#define DP_SD0801_WaitPmaCmnReadySF DP_SD0801_SanityFunction3
+#define DP_SD0801_PhyRunSF DP_SD0801_SanityFunction3
+#define DP_SD0801_ConfigLaneSF DP_SD0801_SanityFunction9
+#define DP_SD0801_SetLinkRateSF DP_SD0801_SanityFunction9
+#define DP_SD0801_EnableLanesSF DP_SD0801_SanityFunction9
+#define DP_SD0801_GetDefaultCoeffsSF DP_SD0801_SanityFunction12
+#define DP_SD0801_GetCoefficientsSF DP_SD0801_SanityFunction12
+#define DP_SD0801_SetCoefficientsSF DP_SD0801_SanityFunction14
+#define DP_SD0801_ReadLinkStatSF DP_SD0801_SanityFunction15
+
+#endif /* DP_SD0801_SANITY_H */
+
+/* parasoft-end-suppress MISRA2012-RULE-8_7 */
+/* parasoft-end-suppress METRICS-41-3 */
+/* parasoft-end-suppress METRICS-39-3 */
+/* parasoft-end-suppress METRICS-36-3 */
+/* parasoft-end-suppress METRICS-18-3 */
diff --git a/packages/ti/drv/dss/src/csl/dp_sd0801/src/specific/dp_dummy_spec.c b/packages/ti/drv/dss/src/csl/dp_sd0801/src/specific/dp_dummy_spec.c
--- /dev/null
@@ -0,0 +1,200 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ *
+ * dp_dummy_spec.c
+ *
+ ******************************************************************************
+ */
+
+#include "dp_sd0801_if.h"
+#include "dp_sd0801_priv.h"
+#include "dp_sd0801_sanity.h"
+#include "dp_regs.h"
+
+#include "cdn_log.h"
+
+#include "dp_sd0801_internal.h"
+
+bool isPhySupported(const DP_SD0801_PrivateData* pD)
+{
+ return true;
+}
+
+uint32_t DP_SD0801_PhyInit(DP_SD0801_PrivateData* pD, uint8_t laneCount, DP_SD0801_LinkRate linkRate)
+{
+ /* Internal reg Addr 2 controls line for link rate. */
+ /* B16 (0x8----) enables control from regs - otherwise dummy phy is */
+ /* controlled by state on the lines. */
+ uint32_t retVal;
+
+ retVal = DP_SD0801_PhyInitSF(pD);
+
+ if (CDN_EOK == retVal)
+ {
+ switch (linkRate)
+ {
+ case DP_SD0801_LINK_RATE_1_62:
+ afeWrite(pD, 2, 0x8000);
+ DbgMsg(DBG_GEN_MSG, DBG_FYI, "Set dummy rate to 162\n");
+ break;
+
+ case DP_SD0801_LINK_RATE_2_70:
+ afeWrite(pD, 2, 0x8001);
+ DbgMsg(DBG_GEN_MSG, DBG_FYI, "Set dummy rate to 270\n");
+ break;
+
+ case DP_SD0801_LINK_RATE_5_40:
+ afeWrite(pD, 2, 0x8002);
+ DbgMsg(DBG_GEN_MSG, DBG_FYI, "Set dummy rate to 540\n");
+ break;
+
+ case DP_SD0801_LINK_RATE_8_10:
+ afeWrite(pD, 2, 0x8004);
+ DbgMsg(DBG_GEN_MSG, DBG_FYI, "Set dummy rate to 810\n");
+ break;
+
+ case DP_SD0801_LINK_RATE_2_16:
+ afeWrite(pD, 2, 0x8008);
+ DbgMsg(DBG_GEN_MSG, DBG_FYI, "Set dummy rate to 216\n");
+ break;
+
+ case DP_SD0801_LINK_RATE_2_43:
+ afeWrite(pD, 2, 0x8010);
+ DbgMsg(DBG_GEN_MSG, DBG_FYI, "Set dummy rate to 243\n");
+ break;
+
+ case DP_SD0801_LINK_RATE_3_24:
+ afeWrite(pD, 2, 0x8020);
+ DbgMsg(DBG_GEN_MSG, DBG_FYI, "Set dummy rate to 324\n");
+ break;
+
+ case DP_SD0801_LINK_RATE_4_32:
+ afeWrite(pD, 2, 0x8040);
+ DbgMsg(DBG_GEN_MSG, DBG_FYI, "Set dummy rate to 432\n");
+ break;
+
+ default:
+ DbgMsg(DBG_GEN_MSG, DBG_FYI, "ERROR: Wrong rate code: 0x%x\n",linkRate);
+ break;
+ }
+ /* Release PHY reset */
+ DP_SD0801_PhySetReset(pD, false);
+
+ pD->linkState.linkRate = linkRate;
+ pD->linkState.laneCount = laneCount;
+
+ }
+
+ return retVal;
+}
+
+/**
+ * Enable DP Main Link lanes, after releasing PHY reset and waiting for PHY to
+ * get ready.
+ */
+uint32_t DP_SD0801_PhyRun(const DP_SD0801_PrivateData* pD, uint8_t laneCount)
+{
+ return DP_SD0801_PhyRunSF(pD);
+}
+
+/**
+ * Initialize part of PHY responsible for AUX channel.
+ */
+uint32_t DP_SD0801_ConfigurePhyAuxCtrl(const DP_SD0801_PrivateData* pD)
+{
+ return DP_SD0801_ConfigurePhyAuxCtrSF(pD);
+}
+
+/**
+ * Wait, until PHY gets ready after releasing PHY reset signal.
+ */
+uint32_t DP_SD0801_WaitPmaCmnReady(const DP_SD0801_PrivateData* pD)
+{
+ return DP_SD0801_WaitPmaCmnReadySF(pD);
+}
+
+uint32_t DP_SD0801_ConfigLane(DP_SD0801_PrivateData* pD, uint8_t lane, const DP_SD0801_LinkState* linkState)
+{
+ uint32_t retVal = DP_SD0801_ConfigLaneSF(pD, linkState);
+ if (CDN_EOK == retVal) {
+ /* Store new settings in pD. */
+ pD->linkState.voltageSwing[lane] = linkState->voltageSwing[lane];
+ pD->linkState.preEmphasis[lane] = linkState->preEmphasis[lane];
+ }
+
+ return retVal;
+}
+
+uint32_t DP_SD0801_SetLinkRate(DP_SD0801_PrivateData* pD, const DP_SD0801_LinkState* linkState)
+{
+ uint32_t retVal;
+
+ retVal = DP_SD0801_SetLinkRateSF(pD, linkState);
+ if (CDN_EOK == retVal) {
+ /* Store new settings in pD. */
+ pD->linkState.linkRate = linkState->linkRate;
+ pD->linkState.laneCount = linkState->laneCount;
+ }
+
+ return retVal;
+}
+
+uint32_t DP_SD0801_EnableLanes(DP_SD0801_PrivateData* pD, const DP_SD0801_LinkState* linkState)
+{
+ /* set active lane count (1, 2 or 4) as in linkState->laneCount. */
+
+ uint32_t retVal;
+
+ retVal = DP_SD0801_EnableLanesSF(pD, linkState);
+ if (CDN_EOK == retVal) {
+ /* Store new setting in pD. */
+ pD->linkState.laneCount = linkState->laneCount;
+ }
+
+ return retVal;
+}
+
+uint32_t DP_SD0801_GetDefaultCoeffs(const DP_SD0801_PrivateData* pD,
+ uint8_t voltageSwing,
+ uint8_t preEmphasis,
+ DP_SD0801_VoltageCoefficients* coefficients)
+{
+ uint32_t retVal;
+ retVal = DP_SD0801_GetDefaultCoeffsSF(pD, voltageSwing, preEmphasis, coefficients);
+
+ if (CDN_EOK == retVal)
+ {
+ coefficients->DiagTxDrv = 0xFFFF;
+ coefficients->MgnfsMult = 0xFFFF;
+ coefficients->CpostMult = 0xFFFF;
+ }
+
+ return retVal;
+}
diff --git a/packages/ti/drv/dss/src/csl/dp_sd0801/src/specific/dp_sd0801_spec.c b/packages/ti/drv/dss/src/csl/dp_sd0801/src/specific/dp_sd0801_spec.c
--- /dev/null
@@ -0,0 +1,1836 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ *
+ * dp_sd0801_spec.c
+ *
+ ******************************************************************************
+ */
+
+#include "dp_sd0801_if.h"
+#include "dp_sd0801_priv.h"
+#include "dp_sd0801_sanity.h"
+#include "dp_regs.h"
+
+#include "cdn_log.h"
+
+#include "dp_sd0801_internal.h"
+#include "dp_sd0801_spec.h"
+
+typedef struct phyRegValue_t
+{
+ uint32_t addr;
+ uint16_t val;
+} phyRegValue;
+
+typedef enum
+{
+ POWERSTATE_A0 = 0U,
+ /* Powerstate A1 is unused */
+ POWERSTATE_A2 = 2U,
+ POWERSTATE_A3 = 3U,
+} phyPowerstate;
+
+#define PID_TYPE_SD (uint16_t)0x7364 /* ASCII for "SD", SerDes */
+#define PID_NUM_0801 (uint16_t)0x0801
+
+bool isPhySupported(const DP_SD0801_PrivateData* pD);
+
+/**
+ * Return true for supported device, false for unsupported one)
+ */
+bool isPhySupported(const DP_SD0801_PrivateData* pD)
+{
+ bool retVal = true;
+ const uint16_t pidType = afeRead(pD, CMN_PID_TYPE);
+ const uint16_t pidNum = afeRead(pD, CMN_PID_NUM);
+
+ if ((pidType != PID_TYPE_SD) || (pidNum != PID_NUM_0801))
+ {
+ retVal = false;
+ }
+
+ return retVal;
+}
+
+#ifdef REF_CLK_19_2MHz
+
+#define TxRcvdetStTmrVal 0x0780 /* Avoids MISRA C violation. */
+
+/* parasoft-begin-suppress METRICS-39-3 "The value of VOCF metric for a function should not be higher than 4, DRV-3852" */
+static void configurePhyPmaCmnCfg(const DP_SD0801_PrivateData* pD)
+{
+ /* Configuring for 19.2 MHz reference clock */
+ /* Values of registers to write are taken from sd0801 PHY programming guide. */
+ static const phyRegValue PhyPmaCmnCfg19[] = {
+ /* Refclock Registers */
+ {.addr = CMN_SSM_BIAS_TMR, .val = 0x0014},
+ {.addr = CMN_PLLSM0_PLLPRE_TMR, .val = 0x0027},
+ {.addr = CMN_PLLSM0_PLLLOCK_TMR, .val = 0x00A1},
+ {.addr = CMN_PLLSM1_PLLPRE_TMR, .val = 0x0027},
+ {.addr = CMN_PLLSM1_PLLLOCK_TMR, .val = 0x00A1},
+ {.addr = CMN_BGCAL_INIT_TMR, .val = 0x0060},
+ {.addr = CMN_BGCAL_ITER_TMR, .val = 0x0060},
+ {.addr = CMN_IBCAL_INIT_TMR, .val = 0x0014},
+ {.addr = CMN_TXPUCAL_INIT_TMR, .val = 0x0018},
+ {.addr = CMN_TXPUCAL_ITER_TMR, .val = 0x0005},
+ {.addr = CMN_TXPDCAL_INIT_TMR, .val = 0x0018},
+ {.addr = CMN_TXPDCAL_ITER_TMR, .val = 0x0005},
+ {.addr = CMN_RXCAL_INIT_TMR, .val = 0x0240},
+ {.addr = CMN_RXCAL_ITER_TMR, .val = 0x0005},
+ {.addr = CMN_SD_CAL_INIT_TMR, .val = 0x0002},
+ {.addr = CMN_SD_CAL_ITER_TMR, .val = 0x0002},
+ {.addr = CMN_SD_CAL_REFTIM_START, .val = 0x000B},
+ {.addr = CMN_SD_CAL_PLLCNT_START, .val = 0x0137},
+ /* PLL Registers */
+ {.addr = CMN_PDIAG_PLL0_CP_PADJ_M0, .val = 0x0509},
+ {.addr = CMN_PDIAG_PLL0_CP_IADJ_M0, .val = 0x0F00},
+ {.addr = CMN_PDIAG_PLL0_FILT_PADJ_M0, .val = 0x0F08},
+ {.addr = CMN_PLL0_DSM_DIAG_M0, .val = 0x0004},
+ {.addr = CMN_PLL0_VCOCAL_INIT_TMR, .val = 0x00C0},
+ {.addr = CMN_PLL0_VCOCAL_ITER_TMR, .val = 0x0004},
+ {.addr = CMN_PLL0_VCOCAL_REFTIM_START, .val = 0x0260},
+ {.addr = CMN_PLL0_VCOCAL_TCTRL, .val = 0x0003},
+#ifdef HAVE_CMN_PLL1
+ {.addr = CMN_PDIAG_PLL1_CP_PADJ_M0, .val = 0x0509},
+ {.addr = CMN_PDIAG_PLL1_CP_IADJ_M0, .val = 0x0F00},
+ {.addr = CMN_PDIAG_PLL1_FILT_PADJ_M0, .val = 0x0F08},
+ {.addr = CMN_PLL1_DSM_DIAG_M0, .val = 0x0004},
+ {.addr = CMN_PLL1_VCOCAL_INIT_TMR, .val = 0x00C0},
+ {.addr = CMN_PLL1_VCOCAL_ITER_TMR, .val = 0x0004},
+ {.addr = CMN_PLL1_VCOCAL_REFTIM_START, .val = 0x0260},
+ {.addr = CMN_PLL1_VCOCAL_TCTRL, .val = 0x0003},
+#endif
+ };
+ uint32_t i, regCount;
+ regCount = (uint32_t)sizeof(PhyPmaCmnCfg19) / (uint32_t)sizeof(phyRegValue);
+ for (i = 0; i < regCount; i++)
+ {
+ afeWrite(pD, PhyPmaCmnCfg19[i].addr, PhyPmaCmnCfg19[i].val);
+ }
+}
+/* parasoft-end-suppress METRICS-39-3 */
+
+#elif defined REF_CLK_20MHz
+
+#define TxRcvdetStTmrVal 0x07D0
+
+/* parasoft-begin-suppress METRICS-39-3 "The value of VOCF metric for a function should not be higher than 4, DRV-3852" */
+static void configurePhyPmaCmnCfg(const DP_SD0801_PrivateData* pD)
+{
+ /* Configuring for 20 MHz reference clock */
+ /* Values of registers to write are taken from sd0801 PHY programming guide. */
+ static const phyRegValue PhyPmaCmnCfg20[] = {
+ /* Refclock Registers */
+ {.addr = CMN_SSM_BIAS_TMR, .val = 0x0014},
+ {.addr = CMN_PLLSM0_PLLPRE_TMR, .val = 0x0028},
+ {.addr = CMN_PLLSM0_PLLLOCK_TMR, .val = 0x00A8},
+ {.addr = CMN_PLLSM1_PLLPRE_TMR, .val = 0x0028},
+ {.addr = CMN_PLLSM1_PLLLOCK_TMR, .val = 0x00A8},
+ {.addr = CMN_BGCAL_INIT_TMR, .val = 0x0064},
+ {.addr = CMN_BGCAL_ITER_TMR, .val = 0x0064},
+ {.addr = CMN_IBCAL_INIT_TMR, .val = 0x0014},
+ {.addr = CMN_TXPUCAL_INIT_TMR, .val = 0x0018},
+ {.addr = CMN_TXPUCAL_ITER_TMR, .val = 0x0005},
+ {.addr = CMN_TXPDCAL_INIT_TMR, .val = 0x0018},
+ {.addr = CMN_TXPDCAL_ITER_TMR, .val = 0x0005},
+ {.addr = CMN_RXCAL_INIT_TMR, .val = 0x0258},
+ {.addr = CMN_RXCAL_ITER_TMR, .val = 0x0005},
+ {.addr = CMN_SD_CAL_INIT_TMR, .val = 0x0002},
+ {.addr = CMN_SD_CAL_ITER_TMR, .val = 0x0002},
+ {.addr = CMN_SD_CAL_REFTIM_START, .val = 0x000B},
+ {.addr = CMN_SD_CAL_PLLCNT_START, .val = 0x012B},
+ /* PLL Registers */
+ {.addr = CMN_PDIAG_PLL0_CP_PADJ_M0, .val = 0x0509},
+ {.addr = CMN_PDIAG_PLL0_CP_IADJ_M0, .val = 0x0F00},
+ {.addr = CMN_PDIAG_PLL0_FILT_PADJ_M0, .val = 0x0F08},
+ {.addr = CMN_PLL0_DSM_DIAG_M0, .val = 0x0004},
+ {.addr = CMN_PLL0_VCOCAL_INIT_TMR, .val = 0x00C8},
+ {.addr = CMN_PLL0_VCOCAL_ITER_TMR, .val = 0x0004},
+ {.addr = CMN_PLL1_VCOCAL_INIT_TMR, .val = 0x00C8},
+ {.addr = CMN_PLL1_VCOCAL_ITER_TMR, .val = 0x0004},
+ {.addr = CMN_PLL0_VCOCAL_REFTIM_START, .val = 0x0279},
+ {.addr = CMN_PLL0_VCOCAL_TCTRL, .val = 0x0003},
+ };
+ uint32_t i, regCount;
+ regCount = (uint32_t)sizeof(PhyPmaCmnCfg20) / (uint32_t)sizeof(phyRegValue);
+ for (i = 0; i < regCount; i++)
+ {
+ afeWrite(pD, PhyPmaCmnCfg20[i].addr, PhyPmaCmnCfg20[i].val);
+ }
+}
+/* parasoft-end-suppress METRICS-39-3 */
+
+#elif defined REF_CLK_24MHz
+
+#define TxRcvdetStTmrVal 0x0960
+
+/* parasoft-begin-suppress METRICS-39-3 "The value of VOCF metric for a function should not be higher than 4, DRV-3852" */
+static void configurePhyPmaCmnCfg(const DP_SD0801_PrivateData* pD)
+{
+ /* Configuring for 24 MHz reference clock */
+ /* Values of registers to write are taken from sd0801 PHY programming guide. */
+ static const phyRegValue PhyPmaCmnCfg24[] = {
+ /* Refclock Registers */
+ {.addr = CMN_SSM_BIAS_TMR, .val = 0x0018},
+ {.addr = CMN_PLLSM0_PLLPRE_TMR, .val = 0x0030},
+ {.addr = CMN_PLLSM0_PLLLOCK_TMR, .val = 0x00C9},
+ {.addr = CMN_PLLSM1_PLLPRE_TMR, .val = 0x0030},
+ {.addr = CMN_PLLSM1_PLLLOCK_TMR, .val = 0x00C9},
+ {.addr = CMN_BGCAL_INIT_TMR, .val = 0x0078},
+ {.addr = CMN_BGCAL_ITER_TMR, .val = 0x0078},
+ {.addr = CMN_IBCAL_INIT_TMR, .val = 0x0018},
+ {.addr = CMN_TXPUCAL_INIT_TMR, .val = 0x001D},
+ {.addr = CMN_TXPUCAL_ITER_TMR, .val = 0x0006},
+ {.addr = CMN_TXPDCAL_INIT_TMR, .val = 0x001D},
+ {.addr = CMN_TXPDCAL_ITER_TMR, .val = 0x0006},
+ {.addr = CMN_RXCAL_INIT_TMR, .val = 0x02D0},
+ {.addr = CMN_RXCAL_ITER_TMR, .val = 0x0006},
+ {.addr = CMN_SD_CAL_INIT_TMR, .val = 0x0002},
+ {.addr = CMN_SD_CAL_ITER_TMR, .val = 0x0002},
+ {.addr = CMN_SD_CAL_REFTIM_START, .val = 0x000E},
+ {.addr = CMN_SD_CAL_PLLCNT_START, .val = 0x0137},
+ /* PLL Registers */
+ {.addr = CMN_PDIAG_PLL0_CP_PADJ_M0, .val = 0x0509},
+ {.addr = CMN_PDIAG_PLL0_CP_IADJ_M0, .val = 0x0F00},
+ {.addr = CMN_PDIAG_PLL0_FILT_PADJ_M0, .val = 0x0F08},
+ {.addr = CMN_PLL0_DSM_DIAG_M0, .val = 0x0004},
+ {.addr = CMN_PLL0_VCOCAL_INIT_TMR, .val = 0x00F0},
+ {.addr = CMN_PLL0_VCOCAL_ITER_TMR, .val = 0x0004},
+ {.addr = CMN_PLL1_VCOCAL_INIT_TMR, .val = 0x00F0},
+ {.addr = CMN_PLL1_VCOCAL_ITER_TMR, .val = 0x0004},
+ {.addr = CMN_PLL0_VCOCAL_REFTIM_START, .val = 0x02F8},
+ {.addr = CMN_PLL0_VCOCAL_TCTRL, .val = 0x0003},
+ };
+ uint32_t i, regCount;
+ regCount = (uint32_t)sizeof(PhyPmaCmnCfg24) / (uint32_t)sizeof(phyRegValue);
+ for (i = 0; i < regCount; i++)
+ {
+ afeWrite(pD, PhyPmaCmnCfg24[i].addr, PhyPmaCmnCfg24[i].val);
+ }
+}
+/* parasoft-end-suppress METRICS-39-3 */
+
+#elif defined REF_CLK_26MHz
+
+#define TxRcvdetStTmrVal 0x0A28
+
+/* parasoft-begin-suppress METRICS-39-3 "The value of VOCF metric for a function should not be higher than 4, DRV-3852" */
+static void configurePhyPmaCmnCfg(const DP_SD0801_PrivateData* pD)
+{
+ /* Configuring for 26 MHz reference clock */
+ /* Values of registers to write are taken from sd0801 PHY programming guide. */
+ static const phyRegValue PhyPmaCmnCfg26[] = {
+ /* Refclock Registers */
+ {.addr = CMN_SSM_BIAS_TMR, .val = 0x001A},
+ {.addr = CMN_PLLSM0_PLLPRE_TMR, .val = 0x0034},
+ {.addr = CMN_PLLSM0_PLLLOCK_TMR, .val = 0x00DA},
+ {.addr = CMN_PLLSM1_PLLPRE_TMR, .val = 0x0034},
+ {.addr = CMN_PLLSM1_PLLLOCK_TMR, .val = 0x00DA},
+ {.addr = CMN_BGCAL_INIT_TMR, .val = 0x0082},
+ {.addr = CMN_BGCAL_ITER_TMR, .val = 0x0082},
+ {.addr = CMN_IBCAL_INIT_TMR, .val = 0x001A},
+ {.addr = CMN_TXPUCAL_INIT_TMR, .val = 0x0020},
+ {.addr = CMN_TXPUCAL_ITER_TMR, .val = 0x0007},
+ {.addr = CMN_TXPDCAL_INIT_TMR, .val = 0x0020},
+ {.addr = CMN_TXPDCAL_ITER_TMR, .val = 0x0007},
+ {.addr = CMN_RXCAL_INIT_TMR, .val = 0x030C},
+ {.addr = CMN_RXCAL_ITER_TMR, .val = 0x0007},
+ {.addr = CMN_SD_CAL_INIT_TMR, .val = 0x0003},
+ {.addr = CMN_SD_CAL_ITER_TMR, .val = 0x0003},
+ {.addr = CMN_SD_CAL_REFTIM_START, .val = 0x000F},
+ {.addr = CMN_SD_CAL_PLLCNT_START, .val = 0x0132},
+ /* PLL Registers */
+ {.addr = CMN_PDIAG_PLL0_CP_PADJ_M0, .val = 0x0509},
+ {.addr = CMN_PDIAG_PLL0_CP_IADJ_M0, .val = 0x0F00},
+ {.addr = CMN_PDIAG_PLL0_FILT_PADJ_M0, .val = 0x0F08},
+ {.addr = CMN_PLL0_DSM_DIAG_M0, .val = 0x0004},
+ {.addr = CMN_PLL0_VCOCAL_INIT_TMR, .val = 0x0104},
+ {.addr = CMN_PLL0_VCOCAL_ITER_TMR, .val = 0x0005},
+ {.addr = CMN_PLL1_VCOCAL_INIT_TMR, .val = 0x0104},
+ {.addr = CMN_PLL1_VCOCAL_ITER_TMR, .val = 0x0005},
+ {.addr = CMN_PLL0_VCOCAL_REFTIM_START, .val = 0x0337},
+ {.addr = CMN_PLL0_VCOCAL_TCTRL, .val = 0x0003},
+ };
+ uint32_t i, regCount;
+ regCount = (uint32_t)sizeof(PhyPmaCmnCfg26) / (uint32_t)sizeof(phyRegValue);
+ for (i = 0; i < regCount; i++)
+ {
+ afeWrite(pD, PhyPmaCmnCfg26[i].addr, PhyPmaCmnCfg26[i].val);
+ }
+}
+/* parasoft-end-suppress METRICS-39-3 */
+
+#elif defined REF_CLK_27MHz
+
+#define TxRcvdetStTmrVal 0x0A8C
+
+/* parasoft-begin-suppress METRICS-39-3 "The value of VOCF metric for a function should not be higher than 4, DRV-3852" */
+static void configurePhyPmaCmnCfg(const DP_SD0801_PrivateData* pD)
+{
+ /* Configuring for 27 MHz reference clock */
+ /* Values of registers to write are taken from sd0801 PHY programming guide. */
+ static const phyRegValue PhyPmaCmnCfg27[] = {
+ /* Refclock Registers */
+ {.addr = CMN_SSM_BIAS_TMR, .val = 0x001B},
+ {.addr = CMN_PLLSM0_PLLPRE_TMR, .val = 0x0036},
+ {.addr = CMN_PLLSM0_PLLLOCK_TMR, .val = 0x00E2},
+ {.addr = CMN_PLLSM1_PLLPRE_TMR, .val = 0x0036},
+ {.addr = CMN_PLLSM1_PLLLOCK_TMR, .val = 0x00E2},
+ {.addr = CMN_BGCAL_INIT_TMR, .val = 0x0087},
+ {.addr = CMN_BGCAL_ITER_TMR, .val = 0x0087},
+ {.addr = CMN_IBCAL_INIT_TMR, .val = 0x001B},
+ {.addr = CMN_TXPUCAL_INIT_TMR, .val = 0x0021},
+ {.addr = CMN_TXPUCAL_ITER_TMR, .val = 0x0007},
+ {.addr = CMN_TXPDCAL_INIT_TMR, .val = 0x0021},
+ {.addr = CMN_TXPDCAL_ITER_TMR, .val = 0x0007},
+ {.addr = CMN_RXCAL_INIT_TMR, .val = 0x032A},
+ {.addr = CMN_RXCAL_ITER_TMR, .val = 0x0007},
+ {.addr = CMN_SD_CAL_INIT_TMR, .val = 0x0003},
+ {.addr = CMN_SD_CAL_ITER_TMR, .val = 0x0003},
+ {.addr = CMN_SD_CAL_REFTIM_START, .val = 0x0010},
+ {.addr = CMN_SD_CAL_PLLCNT_START, .val = 0x0139},
+ /* PLL Registers */
+ {.addr = CMN_PDIAG_PLL0_CP_PADJ_M0, .val = 0x0509},
+ {.addr = CMN_PDIAG_PLL0_CP_IADJ_M0, .val = 0x0F00},
+ {.addr = CMN_PDIAG_PLL0_FILT_PADJ_M0, .val = 0x0F08},
+ {.addr = CMN_PLL0_DSM_DIAG_M0, .val = 0x0004},
+ {.addr = CMN_PLL0_VCOCAL_INIT_TMR, .val = 0x010E},
+ {.addr = CMN_PLL0_VCOCAL_ITER_TMR, .val = 0x0005},
+ {.addr = CMN_PLL1_VCOCAL_INIT_TMR, .val = 0x010E},
+ {.addr = CMN_PLL1_VCOCAL_ITER_TMR, .val = 0x0005},
+ {.addr = CMN_PLL0_VCOCAL_REFTIM_START, .val = 0x0357},
+ {.addr = CMN_PLL0_VCOCAL_TCTRL, .val = 0x0003},
+ };
+ uint32_t i, regCount;
+ regCount = (uint32_t)sizeof(PhyPmaCmnCfg27) / (uint32_t)sizeof(phyRegValue);
+ for (i = 0; i < regCount; i++)
+ {
+ afeWrite(pD, PhyPmaCmnCfg27[i].addr, PhyPmaCmnCfg27[i].val);
+ }
+}
+/* parasoft-end-suppress METRICS-39-3 */
+
+#else /* 25 MHz - default */
+
+#define TxRcvdetStTmrVal 0x09C4
+
+/* parasoft-begin-suppress METRICS-39-3 "The value of VOCF metric for a function should not be higher than 4, DRV-3852" */
+static void configurePhyPmaCmnCfg(const DP_SD0801_PrivateData* pD)
+{
+ /* Configuring for 25 MHz reference clock */
+ /* Values of registers to write are taken from sd0801 PHY programming guide. */
+ static const phyRegValue PhyPmaCmnCfg25[] = {
+ /* Refclock Registers */
+ {.addr = CMN_SSM_BIAS_TMR, .val = 0x0019},
+ {.addr = CMN_PLLSM0_PLLPRE_TMR, .val = 0x0032},
+ {.addr = CMN_PLLSM0_PLLLOCK_TMR, .val = 0x00D1},
+ {.addr = CMN_PLLSM1_PLLPRE_TMR, .val = 0x0032},
+ {.addr = CMN_PLLSM1_PLLLOCK_TMR, .val = 0x00D1},
+ {.addr = CMN_BGCAL_INIT_TMR, .val = 0x007D},
+ {.addr = CMN_BGCAL_ITER_TMR, .val = 0x007D},
+ {.addr = CMN_IBCAL_INIT_TMR, .val = 0x0019},
+ {.addr = CMN_TXPUCAL_INIT_TMR, .val = 0x001E},
+ {.addr = CMN_TXPUCAL_ITER_TMR, .val = 0x0006},
+ {.addr = CMN_TXPDCAL_INIT_TMR, .val = 0x001E},
+ {.addr = CMN_TXPDCAL_ITER_TMR, .val = 0x0006},
+ {.addr = CMN_RXCAL_INIT_TMR, .val = 0x02EE},
+ {.addr = CMN_RXCAL_ITER_TMR, .val = 0x0006},
+ {.addr = CMN_SD_CAL_INIT_TMR, .val = 0x0002},
+ {.addr = CMN_SD_CAL_ITER_TMR, .val = 0x0002},
+ {.addr = CMN_SD_CAL_REFTIM_START, .val = 0x000E},
+ {.addr = CMN_SD_CAL_PLLCNT_START, .val = 0x012B},
+ /* PLL Registers */
+ {.addr = CMN_PDIAG_PLL0_CP_PADJ_M0, .val = 0x0509},
+ {.addr = CMN_PDIAG_PLL0_CP_IADJ_M0, .val = 0x0F00},
+ {.addr = CMN_PDIAG_PLL0_FILT_PADJ_M0, .val = 0x0F08},
+ {.addr = CMN_PLL0_DSM_DIAG_M0, .val = 0x0004},
+ {.addr = CMN_PLL0_VCOCAL_INIT_TMR, .val = 0x00FA},
+ {.addr = CMN_PLL0_VCOCAL_ITER_TMR, .val = 0x0004},
+ {.addr = CMN_PLL1_VCOCAL_INIT_TMR, .val = 0x00FA},
+ {.addr = CMN_PLL1_VCOCAL_ITER_TMR, .val = 0x0004},
+ {.addr = CMN_PLL0_VCOCAL_REFTIM_START, .val = 0x0317},
+ {.addr = CMN_PLL0_VCOCAL_TCTRL, .val = 0x0003},
+ };
+ uint32_t i, regCount;
+ regCount = (uint32_t)sizeof(PhyPmaCmnCfg25) / (uint32_t)sizeof(phyRegValue);
+ for (i = 0; i < regCount; i++)
+ {
+ afeWrite(pD, PhyPmaCmnCfg25[i].addr, PhyPmaCmnCfg25[i].val);
+ }
+}
+/* parasoft-end-suppress METRICS-39-3 */
+
+#endif /* refclock */
+
+/**
+ * This driver supports only DPTX.
+ */
+static void disableRx(const DP_SD0801_PrivateData* pD, uint32_t laneOffset)
+{
+ uint32_t regsToClear[] = {
+ /* Powerstate-related */
+ RX_PSC_A0,
+ RX_PSC_A2,
+ RX_PSC_A3,
+ RX_PSC_CAL,
+
+ RX_REE_GCSM1_CTRL,
+ RX_REE_GCSM2_CTRL,
+ RX_REE_PERGCSM_CTRL
+ };
+ uint8_t i;
+
+ for (i = 0; i < (sizeof(regsToClear) / sizeof(uint32_t)); i++)
+ {
+ afeWrite(pD, (uint32_t)(regsToClear[i] | laneOffset), 0x0000U);
+ }
+}
+
+static void configurePhyPmaLnDpCfg(const DP_SD0801_PrivateData* pD, uint8_t lane)
+{
+ /* DP supports lanes 0-3 - wrap. */
+ /* uint32_t used for consistency with bitwise operations. */
+ const uint32_t i = 0x0003U & (uint32_t)lane;
+
+ /* Bits 9 and 10 of address indicate lane number. */
+ const uint32_t laneOffset = (i << 9);
+
+#ifdef TxRcvdetStTmrVal
+ const uint16_t rcvdetVal = (uint16_t)TxRcvdetStTmrVal;
+ /* Per lane, refclock-dependent receiver detection setting. */
+ afeWrite(pD, (uint32_t)(TX_RCVDET_ST_TMR | laneOffset), rcvdetVal);
+#endif /* for reflock of 100 MHz, use reset value */
+
+ /* Writing Tx/Rx Power State Controllers Registers */
+
+ /* 2.8.3 Display Port / Embedded Display Port */
+ afeWrite(pD, (uint32_t)(TX_PSC_A0 | laneOffset), 0x00FBU);
+ afeWrite(pD, (uint32_t)(TX_PSC_A2 | laneOffset), 0x04AAU);
+ afeWrite(pD, (uint32_t)(TX_PSC_A3 | laneOffset), 0x04AAU);
+
+ disableRx(pD, laneOffset);
+
+ afeWrite(pD, (uint32_t)(XCVR_DIAG_BIDI_CTRL | laneOffset), 0x000F);
+ afeWrite(pD, (uint32_t)(XCVR_DIAG_PLLDRC_CTRL | laneOffset), 0x0001U);
+ afeWrite(pD, (uint32_t)(XCVR_DIAG_HSCLK_SEL | laneOffset), 0x0000U);
+}
+
+static void configurePhyPmaDpCfg(const DP_SD0801_PrivateData* pD, uint8_t linkCfg)
+{
+ uint8_t i;
+ /* PMA cmn configuration */
+ configurePhyPmaCmnCfg(pD);
+
+ /* PMA lane configuration to deal with multi-link operation */
+ for (i = 0; i < 4U; i++) {
+ /* Configure lane for DP operation */
+ if (0U != (linkCfg & (1U << i))) {
+ configurePhyPmaLnDpCfg(pD, i);
+ }
+ }
+}
+
+static ENUM_VCO_FREQ getVcoFreq(DP_SD0801_LinkRate linkRate)
+{
+ ENUM_VCO_FREQ retVal;
+
+ switch (linkRate)
+ {
+ case DP_SD0801_LINK_RATE_1_62:
+ retVal = VCO_9GHz72_refclk; /* Setting VCO for 9.72GHz */
+ break;
+ case DP_SD0801_LINK_RATE_2_16:
+ retVal = VCO_8GHz64_refclk; /* Setting VCO for 8.64GHz */
+ break;
+ case DP_SD0801_LINK_RATE_2_43:
+ retVal = VCO_9GHz72_refclk; /* Setting VCO for 9.72GHz */
+ break;
+ case DP_SD0801_LINK_RATE_2_70:
+ retVal = VCO_10GHz8_refclk; /* Setting VCO for 10.8GHz */
+ break;
+ case DP_SD0801_LINK_RATE_3_24:
+ retVal = VCO_9GHz72_refclk; /* Setting VCO for 9.72GHz */
+ break;
+ case DP_SD0801_LINK_RATE_4_32:
+ retVal = VCO_8GHz64_refclk; /* Setting VCO for 8.64GHz */
+ break;
+ case DP_SD0801_LINK_RATE_5_40:
+ retVal = VCO_10GHz8_refclk; /* Setting VCO for 10.8GHz */
+ break;
+ case DP_SD0801_LINK_RATE_8_10:
+ retVal = VCO_8GHz1_refclk; /* Setting VCO for 8.1GHz */
+ break;
+ default:
+ retVal = VCO_9GHz72_refclk;
+ break;
+ }
+ return retVal;
+}
+
+#ifdef REF_CLK_19_2MHz
+
+/**
+ * Set registers responsible for enabling and configuring SSC, with second and
+ * third register values provided by parameters.
+ */
+static void enableSsc(const DP_SD0801_PrivateData* pD, uint16_t ctrl2Val, uint16_t ctrl3Val)
+{
+ afeWrite(pD, CMN_PLL0_SS_CTRL1_M0, 0x0001); /* Enable SSC */
+ afeWrite(pD, CMN_PLL0_SS_CTRL2_M0, ctrl2Val);
+ afeWrite(pD, CMN_PLL0_SS_CTRL3_M0, ctrl3Val);
+ afeWrite(pD, CMN_PLL0_SS_CTRL4_M0, 0x0003);
+
+#ifdef HAVE_CMN_PLL1
+ afeWrite(pD, CMN_PLL1_SS_CTRL1_M0, 0x0001); /* Enable SSC */
+ afeWrite(pD, CMN_PLL1_SS_CTRL2_M0, ctrl2Val);
+ afeWrite(pD, CMN_PLL1_SS_CTRL3_M0, ctrl3Val);
+ afeWrite(pD, CMN_PLL1_SS_CTRL4_M0, 0x0003);
+#endif
+}
+
+static void configurePhyPmaCmnVcoCfg10_8(const DP_SD0801_PrivateData* pD, bool ssc)
+{
+ /* Setting VCO for 10.8GHz -- 19.2MHz */
+ afeWrite(pD, CMN_PLL0_INTDIV_M0, 0x0119);
+ afeWrite(pD, CMN_PLL0_FRACDIVL_M0, 0x4000);
+ afeWrite(pD, CMN_PLL0_FRACDIVH_M0, 0x0002);
+ afeWrite(pD, CMN_PLL0_HIGH_THR_M0, 0x00BC);
+ afeWrite(pD, CMN_PDIAG_PLL0_CTRL_M0, 0x0012);
+
+#ifdef HAVE_CMN_PLL1
+ afeWrite(pD, CMN_PLL1_INTDIV_M0, 0x0119);
+ afeWrite(pD, CMN_PLL1_FRACDIVL_M0, 0x4000);
+ afeWrite(pD, CMN_PLL1_FRACDIVH_M0, 0x0002);
+ afeWrite(pD, CMN_PLL1_HIGH_THR_M0, 0x00BC);
+ afeWrite(pD, CMN_PDIAG_PLL1_CTRL_M0, 0x0012);
+#endif
+
+ if (ssc)
+ {
+ enableSsc(pD, 0x033A, 0x006A); /* values specific for VCO. */
+ }
+}
+
+static void configurePhyPmaCmnVcoCfg9_72(const DP_SD0801_PrivateData* pD, bool ssc)
+{
+ /* Setting VCO for 9.72GHz -- 19.2MHz */
+ afeWrite(pD, CMN_PLL0_INTDIV_M0, 0x01FA);
+ afeWrite(pD, CMN_PLL0_FRACDIVL_M0, 0x4000);
+ afeWrite(pD, CMN_PLL0_FRACDIVH_M0, 0x0002);
+ afeWrite(pD, CMN_PLL0_HIGH_THR_M0, 0x0152);
+ afeWrite(pD, CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
+
+#ifdef HAVE_CMN_PLL1
+ afeWrite(pD, CMN_PLL1_INTDIV_M0, 0x01FA);
+ afeWrite(pD, CMN_PLL1_FRACDIVL_M0, 0x4000);
+ afeWrite(pD, CMN_PLL1_FRACDIVH_M0, 0x0002);
+ afeWrite(pD, CMN_PLL1_HIGH_THR_M0, 0x0152);
+ afeWrite(pD, CMN_PDIAG_PLL1_CTRL_M0, 0x0002);
+#endif
+
+ if (ssc)
+ {
+ enableSsc(pD, 0x05DD, 0x0069); /* values specific for VCO. */
+ }
+}
+
+static void configurePhyPmaCmnVcoCfg8_64(const DP_SD0801_PrivateData* pD, bool ssc)
+{
+ /* Setting VCO for 8.64GHz -- 19.2MHz */
+ afeWrite(pD, CMN_PLL0_INTDIV_M0, 0x01C2);
+ afeWrite(pD, CMN_PLL0_FRACDIVL_M0, 0x0000);
+ afeWrite(pD, CMN_PLL0_FRACDIVH_M0, 0x0002);
+ afeWrite(pD, CMN_PLL0_HIGH_THR_M0, 0x012C);
+ afeWrite(pD, CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
+
+#ifdef HAVE_CMN_PLL1
+ afeWrite(pD, CMN_PLL1_INTDIV_M0, 0x01C2);
+ afeWrite(pD, CMN_PLL1_FRACDIVL_M0, 0x0000);
+ afeWrite(pD, CMN_PLL1_FRACDIVH_M0, 0x0002);
+ afeWrite(pD, CMN_PLL1_HIGH_THR_M0, 0x012C);
+ afeWrite(pD, CMN_PDIAG_PLL1_CTRL_M0, 0x0002);
+#endif
+
+ if (ssc)
+ {
+ enableSsc(pD, 0x0536, 0x0069); /* values specific for VCO. */
+ }
+}
+
+static void configurePhyPmaCmnVcoCfg8_1(const DP_SD0801_PrivateData* pD, bool ssc)
+{
+ /* Setting VCO for 8.1GHz -- 19.2MHz */
+ afeWrite(pD, CMN_PLL0_INTDIV_M0, 0x01A5);
+ afeWrite(pD, CMN_PLL0_FRACDIVL_M0, 0xE000);
+ afeWrite(pD, CMN_PLL0_FRACDIVH_M0, 0x0002);
+ afeWrite(pD, CMN_PLL0_HIGH_THR_M0, 0x011A);
+ afeWrite(pD, CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
+
+#ifdef HAVE_CMN_PLL1
+ /* Setting VCO for 8.1GHz -- 19.2MHz */
+ afeWrite(pD, CMN_PLL1_INTDIV_M0, 0x01A5);
+ afeWrite(pD, CMN_PLL1_FRACDIVL_M0, 0xE000);
+ afeWrite(pD, CMN_PLL1_FRACDIVH_M0, 0x0002);
+ afeWrite(pD, CMN_PLL1_HIGH_THR_M0, 0x011A);
+ afeWrite(pD, CMN_PDIAG_PLL1_CTRL_M0, 0x0002);
+#endif
+
+ if (ssc)
+ {
+ enableSsc(pD, 0x04D7, 0x006A); /* values specific for VCO. */
+ }
+}
+
+static void configurePhyPmaCmnVcoCommon(const DP_SD0801_PrivateData* pD, bool ssc)
+{
+ /* Settings common for all VCOs - 19.2 MHz */
+ if (ssc)
+ {
+ /* Settings for SSC enabled. */
+ afeWrite(pD, CMN_PLL0_VCOCAL_PLLCNT_START, 0x025E);
+ afeWrite(pD, CMN_PLL0_LOCK_PLLCNT_THR, 0x0005);
+ } else {
+ afeWrite(pD, CMN_PLL0_VCOCAL_PLLCNT_START, 0x0260);
+ /* Set reset register values to disable SSC. */
+ afeWrite(pD, CMN_PLL0_SS_CTRL1_M0, 0x0002); /* Disable SSC */
+ afeWrite(pD, CMN_PLL0_SS_CTRL2_M0, 0x0000);
+ afeWrite(pD, CMN_PLL0_SS_CTRL3_M0, 0x0000);
+ afeWrite(pD, CMN_PLL0_SS_CTRL4_M0, 0x0000);
+ afeWrite(pD, CMN_PLL0_LOCK_PLLCNT_THR, 0x0003);
+ }
+
+ afeWrite(pD, CMN_PLL0_LOCK_REFCNT_START, 0x0099);
+ afeWrite(pD, CMN_PLL0_LOCK_PLLCNT_START, 0x0099);
+
+#ifdef HAVE_CMN_PLL1
+ /* Settings common for all VCOs - 19.2 MHz */
+ if (ssc)
+ {
+ /* Settings for SSC enabled. */
+ afeWrite(pD, CMN_PLL1_VCOCAL_PLLCNT_START, 0x025E);
+ afeWrite(pD, CMN_PLL1_LOCK_PLLCNT_THR, 0x0005);
+ } else {
+ afeWrite(pD, CMN_PLL1_VCOCAL_PLLCNT_START, 0x0260);
+ /* Set reset register values to disable SSC. */
+ afeWrite(pD, CMN_PLL1_SS_CTRL1_M0, 0x0002); /* Disable SSC */
+ afeWrite(pD, CMN_PLL1_SS_CTRL2_M0, 0x0000);
+ afeWrite(pD, CMN_PLL1_SS_CTRL3_M0, 0x0000);
+ afeWrite(pD, CMN_PLL1_SS_CTRL4_M0, 0x0000);
+ afeWrite(pD, CMN_PLL1_LOCK_PLLCNT_THR, 0x0003);
+ }
+
+ afeWrite(pD, CMN_PLL1_LOCK_REFCNT_START, 0x0099);
+ afeWrite(pD, CMN_PLL1_LOCK_PLLCNT_START, 0x0099);
+#endif
+}
+
+#elif defined REF_CLK_20MHz
+
+/**
+ * Set registers responsible for enabling and configuring SSC, with second and
+ * third register values provided by parameters.
+ */
+static void enableSsc(const DP_SD0801_PrivateData* pD, uint16_t ctrl2Val, uint16_t ctrl3Val)
+{
+ afeWrite(pD, CMN_PLL0_SS_CTRL1_M0, 0x0001); /* Enable SSC */
+ afeWrite(pD, CMN_PLL0_SS_CTRL2_M0, ctrl2Val);
+ afeWrite(pD, CMN_PLL0_SS_CTRL3_M0, ctrl3Val);
+ afeWrite(pD, CMN_PLL0_SS_CTRL4_M0, 0x0003);
+}
+
+static void configurePhyPmaCmnVcoCfg10_8(const DP_SD0801_PrivateData* pD, bool ssc)
+{
+ /* Setting VCO for 10.8GHz -- 20MHz */
+ afeWrite(pD, CMN_PLL0_INTDIV_M0, 0x010E);
+ afeWrite(pD, CMN_PLL0_FRACDIVL_M0, 0x0000);
+ afeWrite(pD, CMN_PLL0_FRACDIVH_M0, 0x0002);
+ afeWrite(pD, CMN_PLL0_HIGH_THR_M0, 0x00B4);
+ afeWrite(pD, CMN_PDIAG_PLL0_CTRL_M0, 0x0012);
+ if (ssc)
+ {
+ enableSsc(pD, 0x05F8, 0x006E); /* values specific for VCO. */
+ }
+}
+
+static void configurePhyPmaCmnVcoCfg9_72(const DP_SD0801_PrivateData* pD, bool ssc)
+{
+ /* Setting VCO for 9.72GHz -- 20MHz */
+ afeWrite(pD, CMN_PLL0_INTDIV_M0, 0x01E6);
+ afeWrite(pD, CMN_PLL0_FRACDIVL_M0, 0x0000);
+ afeWrite(pD, CMN_PLL0_FRACDIVH_M0, 0x0002);
+ afeWrite(pD, CMN_PLL0_HIGH_THR_M0, 0x0144);
+ afeWrite(pD, CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
+ if (ssc)
+ {
+ enableSsc(pD, 0x0553, 0x006F); /* values specific for VCO. */
+ }
+}
+
+static void configurePhyPmaCmnVcoCfg8_64(const DP_SD0801_PrivateData* pD, bool ssc)
+{
+ /* Setting VCO for 8.64GHz -- 20MHz */
+ afeWrite(pD, CMN_PLL0_INTDIV_M0, 0x01B0);
+ afeWrite(pD, CMN_PLL0_FRACDIVL_M0, 0x0000);
+ afeWrite(pD, CMN_PLL0_FRACDIVH_M0, 0x0002);
+ afeWrite(pD, CMN_PLL0_HIGH_THR_M0, 0x0120);
+ afeWrite(pD, CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
+ if (ssc)
+ {
+ enableSsc(pD, 0x04DD, 0x006C); /* values specific for VCO. */
+ }
+}
+
+static void configurePhyPmaCmnVcoCfg8_1(const DP_SD0801_PrivateData* pD, bool ssc)
+{
+ /* Setting VCO for 8.1GHz -- 20MHz */
+ afeWrite(pD, CMN_PLL0_INTDIV_M0, 0x0195);
+ afeWrite(pD, CMN_PLL0_FRACDIVL_M0, 0x0000);
+ afeWrite(pD, CMN_PLL0_FRACDIVH_M0, 0x0002);
+ afeWrite(pD, CMN_PLL0_HIGH_THR_M0, 0x010E);
+ afeWrite(pD, CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
+ if (ssc)
+ {
+ enableSsc(pD, 0x047A, 0x006E); /* values specific for VCO. */
+ }
+}
+
+static void configurePhyPmaCmnVcoCommon(const DP_SD0801_PrivateData* pD, bool ssc)
+{
+ /* Settings common for all VCOs - 20 MHz */
+ if (ssc)
+ {
+ /* Settings for SSC enabled. */
+ afeWrite(pD, CMN_PLL0_VCOCAL_PLLCNT_START, 0x0277);
+ afeWrite(pD, CMN_PLL0_LOCK_PLLCNT_THR, 0x0005);
+ } else {
+ afeWrite(pD, CMN_PLL0_VCOCAL_PLLCNT_START, 0x0279);
+ /* Set reset register values to disable SSC */
+ afeWrite(pD, CMN_PLL0_SS_CTRL1_M0, 0x0002); /* Disable SSC */
+ afeWrite(pD, CMN_PLL0_SS_CTRL2_M0, 0x0000);
+ afeWrite(pD, CMN_PLL0_SS_CTRL3_M0, 0x0000);
+ afeWrite(pD, CMN_PLL0_SS_CTRL4_M0, 0x0000);
+ afeWrite(pD, CMN_PLL0_LOCK_PLLCNT_THR, 0x0003);
+ }
+
+ afeWrite(pD, CMN_PLL0_LOCK_REFCNT_START, 0x009F);
+ afeWrite(pD, CMN_PLL0_LOCK_PLLCNT_START, 0x009F);
+}
+
+#elif defined REF_CLK_24MHz
+
+/**
+ * Set registers responsible for enabling and configuring SSC, with second and
+ * third register values provided by parameters.
+ */
+static void enableSsc(const DP_SD0801_PrivateData* pD, uint16_t ctrl2Val, uint16_t ctrl3Val)
+{
+ afeWrite(pD, CMN_PLL0_SS_CTRL1_M0, 0x0001); /* Enable SSC */
+ afeWrite(pD, CMN_PLL0_SS_CTRL2_M0, ctrl2Val);
+ afeWrite(pD, CMN_PLL0_SS_CTRL3_M0, ctrl3Val);
+ afeWrite(pD, CMN_PLL0_SS_CTRL4_M0, 0x0003);
+}
+
+static void configurePhyPmaCmnVcoCfg10_8(const DP_SD0801_PrivateData* pD, bool ssc)
+{
+ /* Setting VCO for 10.8GHz -- 24MHz */
+ afeWrite(pD, CMN_PLL0_INTDIV_M0, 0x01C2);
+ afeWrite(pD, CMN_PLL0_FRACDIVL_M0, 0x0000);
+ afeWrite(pD, CMN_PLL0_FRACDIVH_M0, 0x0002);
+ afeWrite(pD, CMN_PLL0_HIGH_THR_M0, 0x012C);
+ if (ssc)
+ {
+ enableSsc(pD, 0x044F, 0x007F); /* values specific for VCO. */
+ }
+}
+
+static void configurePhyPmaCmnVcoCfg9_72(const DP_SD0801_PrivateData* pD, bool ssc)
+{
+ /* Setting VCO for 9.72GHz -- 24MHz */
+ afeWrite(pD, CMN_PLL0_INTDIV_M0, 0x0195);
+ afeWrite(pD, CMN_PLL0_FRACDIVL_M0, 0x0000);
+ afeWrite(pD, CMN_PLL0_FRACDIVH_M0, 0x0002);
+ afeWrite(pD, CMN_PLL0_HIGH_THR_M0, 0x010E);
+ if (ssc)
+ {
+ enableSsc(pD, 0x0401, 0x007B); /* values specific for VCO. */
+ }
+}
+
+static void configurePhyPmaCmnVcoCfg8_64(const DP_SD0801_PrivateData* pD, bool ssc)
+{
+ /* Setting VCO for 8.64GHz -- 24MHz */
+ afeWrite(pD, CMN_PLL0_INTDIV_M0, 0x0168);
+ afeWrite(pD, CMN_PLL0_FRACDIVL_M0, 0x0000);
+ afeWrite(pD, CMN_PLL0_FRACDIVH_M0, 0x0002);
+ afeWrite(pD, CMN_PLL0_HIGH_THR_M0, 0x00F0);
+
+ if (ssc)
+ {
+ enableSsc(pD, 0x038F, 0x007B); /* values specific for VCO. */
+ }
+}
+
+static void configurePhyPmaCmnVcoCfg8_1(const DP_SD0801_PrivateData* pD, bool ssc)
+{
+ /* Setting VCO for 8.1GHz -- 24MHz */
+ afeWrite(pD, CMN_PLL0_INTDIV_M0, 0x0151);
+ afeWrite(pD, CMN_PLL0_FRACDIVL_M0, 0x8000);
+ afeWrite(pD, CMN_PLL0_FRACDIVH_M0, 0x0002);
+ afeWrite(pD, CMN_PLL0_HIGH_THR_M0, 0x00E2);
+ if (ssc)
+ {
+ enableSsc(pD, 0x0342, 0x007E); /* values specific for VCO. */
+ }
+}
+
+static void configurePhyPmaCmnVcoCommon(const DP_SD0801_PrivateData* pD, bool ssc)
+{
+ /* Settings common for all VCOs - 24 MHz */
+ afeWrite(pD, CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
+
+ if (ssc)
+ {
+ /* Settings for SSC enabled. */
+ afeWrite(pD, CMN_PLL0_VCOCAL_PLLCNT_START, 0x02F6);
+ afeWrite(pD, CMN_PLL0_LOCK_PLLCNT_THR, 0x0005);
+ } else {
+ afeWrite(pD, CMN_PLL0_VCOCAL_PLLCNT_START, 0x02F8);
+ /* Set reset register values to disable SSC */
+ afeWrite(pD, CMN_PLL0_SS_CTRL1_M0, 0x0002); /* Disable SSC */
+ afeWrite(pD, CMN_PLL0_SS_CTRL2_M0, 0x0000);
+ afeWrite(pD, CMN_PLL0_SS_CTRL3_M0, 0x0000);
+ afeWrite(pD, CMN_PLL0_SS_CTRL4_M0, 0x0000);
+ afeWrite(pD, CMN_PLL0_LOCK_PLLCNT_THR, 0x0003);
+ }
+
+ afeWrite(pD, CMN_PLL0_LOCK_REFCNT_START, 0x00BF);
+ afeWrite(pD, CMN_PLL0_LOCK_PLLCNT_START, 0x00BF);
+
+}
+
+#elif defined REF_CLK_26MHz
+
+/**
+ * Set registers responsible for enabling and configuring SSC, with second and
+ * third register values provided by parameters.
+ */
+static void enableSsc(const DP_SD0801_PrivateData* pD, uint16_t ctrl2Val, uint16_t ctrl3Val)
+{
+ afeWrite(pD, CMN_PLL0_SS_CTRL1_M0, 0x0001); /* Enable SSC */
+ afeWrite(pD, CMN_PLL0_SS_CTRL2_M0, ctrl2Val);
+ afeWrite(pD, CMN_PLL0_SS_CTRL3_M0, ctrl3Val);
+ afeWrite(pD, CMN_PLL0_SS_CTRL4_M0, 0x0004);
+}
+
+static void configurePhyPmaCmnVcoCfg10_8(const DP_SD0801_PrivateData* pD, bool ssc)
+{
+ /* Setting VCO for 10.8GHz -- 26MHz */
+ afeWrite(pD, CMN_PLL0_INTDIV_M0, 0x019F);
+ afeWrite(pD, CMN_PLL0_FRACDIVL_M0, 0x6276);
+ afeWrite(pD, CMN_PLL0_FRACDIVH_M0, 0x0002);
+ afeWrite(pD, CMN_PLL0_HIGH_THR_M0, 0x0115);
+ if (ssc)
+ {
+ enableSsc(pD, 0x04C4, 0x006A); /* values specific for VCO. */
+ }
+}
+
+static void configurePhyPmaCmnVcoCfg9_72(const DP_SD0801_PrivateData* pD, bool ssc)
+{
+ /* Setting VCO for 9.72GHz -- 26MHz */
+ afeWrite(pD, CMN_PLL0_INTDIV_M0, 0x0175);
+ afeWrite(pD, CMN_PLL0_FRACDIVL_M0, 0xD89E);
+ afeWrite(pD, CMN_PLL0_FRACDIVH_M0, 0x0002);
+ afeWrite(pD, CMN_PLL0_HIGH_THR_M0, 0x00FA);
+ if (ssc)
+ {
+ enableSsc(pD, 0x044A, 0x006A); /* values specific for VCO. */
+ }
+}
+
+static void configurePhyPmaCmnVcoCfg8_64(const DP_SD0801_PrivateData* pD, bool ssc)
+{
+ /* Setting VCO for 8.64GHz -- 26MHz */
+ afeWrite(pD, CMN_PLL0_INTDIV_M0, 0x014C);
+ afeWrite(pD, CMN_PLL0_FRACDIVL_M0, 0x4EC5);
+ afeWrite(pD, CMN_PLL0_FRACDIVH_M0, 0x0002);
+ afeWrite(pD, CMN_PLL0_HIGH_THR_M0, 0x00DE);
+ if (ssc)
+ {
+ enableSsc(pD, 0x03D0, 0x006A); /* values specific for VCO. */
+ }
+}
+
+static void configurePhyPmaCmnVcoCfg8_1(const DP_SD0801_PrivateData* pD, bool ssc)
+{
+ /* Setting VCO for 8.1GHz -- 26MHz */
+ afeWrite(pD, CMN_PLL0_INTDIV_M0, 0x0137);
+ afeWrite(pD, CMN_PLL0_FRACDIVL_M0, 0x89D9);
+ afeWrite(pD, CMN_PLL0_FRACDIVH_M0, 0x0002);
+ afeWrite(pD, CMN_PLL0_HIGH_THR_M0, 0x00D0);
+ if (ssc)
+ {
+ enableSsc(pD, 0x0382, 0x006C); /* values specific for VCO. */
+ }
+}
+
+static void configurePhyPmaCmnVcoCommon(const DP_SD0801_PrivateData* pD, bool ssc)
+{
+ /* Settings common for all VCOs - 26 MHz */
+ afeWrite(pD, CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
+
+ if (ssc)
+ {
+ /* Settings for SSC enabled. */
+ afeWrite(pD, CMN_PLL0_VCOCAL_PLLCNT_START, 0x0335);
+ afeWrite(pD, CMN_PLL0_LOCK_PLLCNT_START, 0x00CE);
+ afeWrite(pD, CMN_PLL0_LOCK_PLLCNT_THR, 0x0005);
+ } else {
+ afeWrite(pD, CMN_PLL0_VCOCAL_PLLCNT_START, 0x0337);
+ afeWrite(pD, CMN_PLL0_LOCK_PLLCNT_START, 0x00CF);
+ /* Set reset register values to disable SSC */
+ afeWrite(pD, CMN_PLL0_SS_CTRL1_M0, 0x0002); /* Disable SSC */
+ afeWrite(pD, CMN_PLL0_SS_CTRL2_M0, 0x0000);
+ afeWrite(pD, CMN_PLL0_SS_CTRL3_M0, 0x0000);
+ afeWrite(pD, CMN_PLL0_SS_CTRL4_M0, 0x0000);
+ afeWrite(pD, CMN_PLL0_LOCK_PLLCNT_THR, 0x0003);
+ }
+
+ afeWrite(pD, CMN_PLL0_LOCK_REFCNT_START, 0x00CF);
+}
+
+#elif defined REF_CLK_27MHz
+
+/**
+ * Set registers responsible for enabling and configuring SSC, with second and
+ * third register values provided by parameters.
+ */
+static void enableSsc(const DP_SD0801_PrivateData* pD, uint16_t ctrl2Val, uint16_t ctrl3Val)
+{
+ afeWrite(pD, CMN_PLL0_SS_CTRL1_M0, 0x0001); /* Enable SSC */
+ afeWrite(pD, CMN_PLL0_SS_CTRL2_M0, ctrl2Val);
+ afeWrite(pD, CMN_PLL0_SS_CTRL3_M0, ctrl3Val);
+ afeWrite(pD, CMN_PLL0_SS_CTRL4_M0, 0x0004);
+}
+
+static void configurePhyPmaCmnVcoCfg10_8(const DP_SD0801_PrivateData* pD, bool ssc)
+{
+ /* Setting VCO for 10.8GHz -- 27MHz */
+ afeWrite(pD, CMN_PLL0_INTDIV_M0, 0x0190);
+ afeWrite(pD, CMN_PLL0_FRACDIVL_M0, 0x0000);
+ afeWrite(pD, CMN_PLL0_FRACDIVH_M0, 0x0002);
+ afeWrite(pD, CMN_PLL0_HIGH_THR_M0, 0x010C);
+ if (ssc)
+ {
+ enableSsc(pD, 0x046C, 0x006E); /* values specific for VCO. */
+ }
+}
+
+static void configurePhyPmaCmnVcoCfg9_72(const DP_SD0801_PrivateData* pD, bool ssc)
+{
+ /* Setting VCO for 9.72GHz -- 27MHz */
+ afeWrite(pD, CMN_PLL0_INTDIV_M0, 0x0168);
+ afeWrite(pD, CMN_PLL0_FRACDIVL_M0, 0x0000);
+ afeWrite(pD, CMN_PLL0_FRACDIVH_M0, 0x0002);
+ afeWrite(pD, CMN_PLL0_HIGH_THR_M0, 0x00F0);
+ if (ssc)
+ {
+ enableSsc(pD, 0x0404, 0x006D); /* values specific for VCO. */
+ }
+}
+
+static void configurePhyPmaCmnVcoCfg8_64(const DP_SD0801_PrivateData* pD, bool ssc)
+{
+ /* Setting VCO for 8.64GHz -- 27MHz */
+ afeWrite(pD, CMN_PLL0_INTDIV_M0, 0x0140);
+ afeWrite(pD, CMN_PLL0_FRACDIVL_M0, 0x0000);
+ afeWrite(pD, CMN_PLL0_FRACDIVH_M0, 0x0002);
+ afeWrite(pD, CMN_PLL0_HIGH_THR_M0, 0x00D6);
+ if (ssc)
+ {
+ enableSsc(pD, 0x03A3, 0x006B); /* values specific for VCO. */
+ }
+}
+
+static void configurePhyPmaCmnVcoCfg8_1(const DP_SD0801_PrivateData* pD, bool ssc)
+{
+ /* Setting VCO for 8.1GHz -- 27MHz */
+ afeWrite(pD, CMN_PLL0_INTDIV_M0, 0x012C);
+ afeWrite(pD, CMN_PLL0_FRACDIVL_M0, 0x0000);
+ afeWrite(pD, CMN_PLL0_FRACDIVH_M0, 0x0002);
+ afeWrite(pD, CMN_PLL0_HIGH_THR_M0, 0x00C8);
+ if (ssc)
+ {
+ enableSsc(pD, 0x0351, 0x006E); /* values specific for VCO. */
+ }
+}
+
+static void configurePhyPmaCmnVcoCommon(const DP_SD0801_PrivateData* pD, bool ssc)
+{
+ /* Settings common for all VCOs - 27 MHz */
+ afeWrite(pD, CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
+
+ if (ssc)
+ {
+ /* Settings for SSC enabled. */
+ afeWrite(pD, CMN_PLL0_VCOCAL_PLLCNT_START, 0x0355);
+ afeWrite(pD, CMN_PLL0_LOCK_PLLCNT_START, 0x00D6);
+ afeWrite(pD, CMN_PLL0_LOCK_PLLCNT_THR, 0x0005);
+ } else {
+ afeWrite(pD, CMN_PLL0_VCOCAL_PLLCNT_START, 0x0357);
+ afeWrite(pD, CMN_PLL0_LOCK_PLLCNT_START, 0x00D7);
+ /* Set reset register values to disable SSC */
+ afeWrite(pD, CMN_PLL0_SS_CTRL1_M0, 0x0002); /* Disable SSC */
+ afeWrite(pD, CMN_PLL0_SS_CTRL2_M0, 0x0000);
+ afeWrite(pD, CMN_PLL0_SS_CTRL3_M0, 0x0000);
+ afeWrite(pD, CMN_PLL0_SS_CTRL4_M0, 0x0000);
+ afeWrite(pD, CMN_PLL0_LOCK_PLLCNT_THR, 0x0003);
+ }
+
+ afeWrite(pD, CMN_PLL0_LOCK_REFCNT_START, 0x00D7);
+}
+
+#else /* 25 MHz - default */
+
+/**
+ * Set registers responsible for enabling and configuring SSC, with second
+ * register value provided by a parameter.
+ */
+static void enableSsc(const DP_SD0801_PrivateData* pD, uint16_t ctrl2Val)
+{
+ afeWrite(pD, CMN_PLL0_SS_CTRL1_M0, 0x0001); /* Enable SSC */
+ afeWrite(pD, CMN_PLL0_SS_CTRL2_M0, ctrl2Val);
+ afeWrite(pD, CMN_PLL0_SS_CTRL3_M0, 0x007F);
+ afeWrite(pD, CMN_PLL0_SS_CTRL4_M0, 0x0003);
+}
+
+static void configurePhyPmaCmnVcoCfg10_8(const DP_SD0801_PrivateData* pD, bool ssc)
+{
+ /* Setting VCO for 10.8GHz -- 25MHz */
+ afeWrite(pD, CMN_PLL0_INTDIV_M0, 0x01B0);
+ afeWrite(pD, CMN_PLL0_FRACDIVL_M0, 0x0000);
+ afeWrite(pD, CMN_PLL0_FRACDIVH_M0, 0x0002);
+ afeWrite(pD, CMN_PLL0_HIGH_THR_M0, 0x0120);
+ if (ssc)
+ {
+ enableSsc(pD, 0x0423); /* value specific for VCO. */
+ }
+}
+
+static void configurePhyPmaCmnVcoCfg9_72(const DP_SD0801_PrivateData* pD, bool ssc)
+{
+ /* Setting VCO for 9.72GHz -- 25MHz */
+ afeWrite(pD, CMN_PLL0_INTDIV_M0, 0x0184);
+ afeWrite(pD, CMN_PLL0_FRACDIVL_M0, 0xCCCD);
+ afeWrite(pD, CMN_PLL0_FRACDIVH_M0, 0x0002);
+ afeWrite(pD, CMN_PLL0_HIGH_THR_M0, 0x0104);
+ if (ssc)
+ {
+ enableSsc(pD, 0x03B9); /* value specific for VCO. */
+ }
+}
+
+static void configurePhyPmaCmnVcoCfg8_64(const DP_SD0801_PrivateData* pD, bool ssc)
+{
+ /* Setting VCO for 8.64GHz -- 25MHz */
+ afeWrite(pD, CMN_PLL0_INTDIV_M0, 0x0159);
+ afeWrite(pD, CMN_PLL0_FRACDIVL_M0, 0x999A);
+ afeWrite(pD, CMN_PLL0_FRACDIVH_M0, 0x0002);
+ afeWrite(pD, CMN_PLL0_HIGH_THR_M0, 0x00E8);
+ if (ssc)
+ {
+ enableSsc(pD, 0x034F); /* value specific for VCO. */
+ }
+}
+
+static void configurePhyPmaCmnVcoCfg8_1(const DP_SD0801_PrivateData* pD, bool ssc)
+{
+ /* Setting VCO for 8.1GHz -- 25MHz */
+ afeWrite(pD, CMN_PLL0_INTDIV_M0, 0x0144);
+ afeWrite(pD, CMN_PLL0_FRACDIVL_M0, 0x0000);
+ afeWrite(pD, CMN_PLL0_FRACDIVH_M0, 0x0002);
+ afeWrite(pD, CMN_PLL0_HIGH_THR_M0, 0x00D8);
+ if (ssc)
+ {
+ enableSsc(pD, 0x031A); /* value specific for VCO. */
+ }
+}
+
+static void configurePhyPmaCmnVcoCommon(const DP_SD0801_PrivateData* pD, bool ssc)
+{
+ /* Settings common for all VCOs - 25 MHz */
+ afeWrite(pD, CMN_PDIAG_PLL0_CTRL_M0, 0x0002);
+
+ if (ssc)
+ {
+ /* Settings for SSC enabled. */
+ afeWrite(pD, CMN_PLL0_VCOCAL_PLLCNT_START, 0x0315);
+ afeWrite(pD, CMN_PLL0_LOCK_PLLCNT_THR, 0x0005);
+ } else {
+ afeWrite(pD, CMN_PLL0_VCOCAL_PLLCNT_START, 0x0317);
+ /* Set reset register values to disable SSC */
+ afeWrite(pD, CMN_PLL0_SS_CTRL1_M0, 0x0002); /* Disable SSC */
+ afeWrite(pD, CMN_PLL0_SS_CTRL2_M0, 0x0000);
+ afeWrite(pD, CMN_PLL0_SS_CTRL3_M0, 0x0000);
+ afeWrite(pD, CMN_PLL0_SS_CTRL4_M0, 0x0000);
+ afeWrite(pD, CMN_PLL0_LOCK_PLLCNT_THR, 0x0003);
+ }
+
+ afeWrite(pD, CMN_PLL0_LOCK_REFCNT_START, 0x00C7);
+ afeWrite(pD, CMN_PLL0_LOCK_PLLCNT_START, 0x00C7);
+}
+
+#endif /* refclock */
+
+/* Configure PLL for requested VCO frequency. */
+static void configurePhyPmaCmnVcoCfg(const DP_SD0801_PrivateData* pD, ENUM_VCO_FREQ vco_freq, bool ssc)
+{
+ /* Perform register writes specific to VCO frequency. */
+ switch (vco_freq)
+ {
+ case VCO_10GHz8_refclk:
+ configurePhyPmaCmnVcoCfg10_8(pD, ssc);
+ break;
+ case VCO_9GHz72_refclk:
+ configurePhyPmaCmnVcoCfg9_72(pD, ssc);
+ break;
+ case VCO_8GHz64_refclk:
+ configurePhyPmaCmnVcoCfg8_64(pD, ssc);
+ break;
+ default:
+ configurePhyPmaCmnVcoCfg8_1(pD, ssc);
+ break;
+ }
+ /* Write register values common for all VCO frequencies. */
+ configurePhyPmaCmnVcoCommon(pD, ssc);
+}
+
+static bool isPllSet(uint8_t pllBits, uint8_t pllIdx)
+{
+ bool result = false;
+ if (pllIdx < 2U) {
+ /* Check, if bit for particular PLL (0 or 1) is set. */
+ if (0U != ((pllBits >> pllIdx) & 1U)) {
+ result = true;
+ }
+ }
+
+ return result;
+}
+
+static uint16_t getClkSelM0Val(DP_SD0801_LinkRate linkRate)
+{
+ uint16_t clkSelM0Val;
+ switch (linkRate)
+ {
+ /* Rate: 1.62G */
+ case (DP_SD0801_LINK_RATE_1_62):
+ clkSelM0Val = 0x0F01;
+ break;
+ /* Rate: 2.16G */
+ case (DP_SD0801_LINK_RATE_2_16):
+ clkSelM0Val = 0x0701;
+ break;
+ /* Rate: 2.43G */
+ case (DP_SD0801_LINK_RATE_2_43):
+ clkSelM0Val = 0x0701;
+ break;
+ /* Rate: 2.7G */
+ case (DP_SD0801_LINK_RATE_2_70):
+ clkSelM0Val = 0x0701;
+ break;
+ /* Rate: 3.24G */
+ case (DP_SD0801_LINK_RATE_3_24):
+ clkSelM0Val = 0x0B00;
+ break;
+ /* Rate: 4.32G */
+ case (DP_SD0801_LINK_RATE_4_32):
+ clkSelM0Val = 0x0301;
+ break;
+ /* Rate: 5.4G */
+ case (DP_SD0801_LINK_RATE_5_40):
+ clkSelM0Val = 0x0301;
+ break;
+ /* Rate: 8.1G */
+ default:
+ clkSelM0Val = 0x0200;
+ break;
+ }
+
+ return clkSelM0Val;
+}
+
+static uint16_t getHsclkDivVal(DP_SD0801_LinkRate linkRate)
+{
+ uint16_t hsclkDivVal;
+
+ switch (linkRate)
+ {
+ /* ******* Writing XCVR_DIAG_HSCLK_DIV Register for Lane %d ******* */
+ /* Rate: 1.62G */
+ case (DP_SD0801_LINK_RATE_1_62):
+ hsclkDivVal = 0x0002U;
+ break;
+ /* Rate: 2.16G */
+ case (DP_SD0801_LINK_RATE_2_16):
+ hsclkDivVal = 0x0001U;
+ break;
+ /* Rate: 2.43G */
+ case (DP_SD0801_LINK_RATE_2_43):
+ hsclkDivVal = 0x0001U;
+ break;
+ /* Rate: 2.7G */
+ case (DP_SD0801_LINK_RATE_2_70):
+ hsclkDivVal = 0x0001U;
+ break;
+ /* Rate: 3.24G */
+ case (DP_SD0801_LINK_RATE_3_24):
+ hsclkDivVal = 0x0002U;
+ break;
+ /* Rate: 4.32G */
+ case (DP_SD0801_LINK_RATE_4_32):
+ hsclkDivVal = 0x0000U;
+ break;
+ /* Rate: 5.4G */
+ case (DP_SD0801_LINK_RATE_5_40):
+ hsclkDivVal = 0x0000U;
+ break;
+ /* Rate: 8.1G */
+ default:
+ hsclkDivVal = 0x0000U;
+ break;
+ }
+
+ return hsclkDivVal;
+}
+
+static void configurePhyPmaCmnDpRate(const DP_SD0801_PrivateData* pD, uint8_t linkCfg, DP_SD0801_LinkRate dp_rate, uint8_t dp_pll)
+{
+ uint16_t hsclkDivVal = getHsclkDivVal(dp_rate);
+ /* uint32_t used for consistency with bitwise operations. */
+ uint32_t i;
+
+ /* 16’h0000 for single DP link configuration */
+ /* 16’h0002 for 2 DP link configuration */
+ afeWrite(pD, PHY_PLL_CFG, 0x0000);
+
+ /* Configure appropriate PLL (0 / 1) */
+ if (isPllSet(dp_pll, 0)) {
+ afeWrite(pD, CMN_PDIAG_PLL0_CLK_SEL_M0, getClkSelM0Val(dp_rate));
+ }
+ if (isPllSet(dp_pll, 1)) {
+ afeWrite(pD, CMN_PDIAG_PLL1_CLK_SEL_M0, getClkSelM0Val(dp_rate));
+ }
+
+ /* PMA lane configuration to deal with multi-link operation */
+ for (i = 0; i < 4U; i++) /* depends of active lane. If not it results in timeout */
+ {
+ if (0U != (linkCfg & (1U << i)))
+ {
+ /* ******* Writing XCVR_DIAG_HSCLK_DIV Register for Lane 'i' ******* */
+ afeWrite(pD, (XCVR_DIAG_HSCLK_DIV | (i << 9U)), hsclkDivVal);
+ }
+ }
+}
+
+static void setA0PowerRegPwrState(uint32_t* pwrState, uint8_t laneCount)
+{
+ /* lane 0 */
+ *pwrState = CPS_FLD_WRITE(DP__DP_REGS__PMA_POWER_STATE_REQ_P, PMA_XCVR_POWER_STATE_REQ_LN_0, *pwrState, 0x00);
+
+ if (laneCount > 1U)
+ {
+ /* lane 1 */
+ *pwrState = CPS_FLD_WRITE(DP__DP_REGS__PMA_POWER_STATE_REQ_P, PMA_XCVR_POWER_STATE_REQ_LN_1, *pwrState, 0x00);
+ }
+
+ if (laneCount > 2U)
+ {
+ /* lanes 2 and 3 */
+ *pwrState = CPS_FLD_WRITE(DP__DP_REGS__PMA_POWER_STATE_REQ_P, PMA_XCVR_POWER_STATE_REQ_LN_2, *pwrState, 0x00);
+ *pwrState = CPS_FLD_WRITE(DP__DP_REGS__PMA_POWER_STATE_REQ_P, PMA_XCVR_POWER_STATE_REQ_LN_3, *pwrState, 0x00);
+ }
+}
+
+static void setA0PowerRegPllclkEn(uint32_t* pllclkEn, uint8_t laneCount)
+{
+ /* lane 0 */
+ *pllclkEn = CPS_FLD_WRITE(DP__DP_REGS__PMA_PLLCLK_EN_P, PMA_XCVR_PLLCLK_EN_LN_0, *pllclkEn, 0x00);
+
+ if (laneCount > 1U)
+ {
+ /* lane 1 */
+ *pllclkEn = CPS_FLD_WRITE(DP__DP_REGS__PMA_PLLCLK_EN_P, PMA_XCVR_PLLCLK_EN_LN_1, *pllclkEn, 0x00);
+ }
+
+ if (laneCount > 2U)
+ {
+ /* lanes 2 and 3 */
+ *pllclkEn = CPS_FLD_WRITE(DP__DP_REGS__PMA_PLLCLK_EN_P, PMA_XCVR_PLLCLK_EN_LN_2, *pllclkEn, 0x00);
+ *pllclkEn = CPS_FLD_WRITE(DP__DP_REGS__PMA_PLLCLK_EN_P, PMA_XCVR_PLLCLK_EN_LN_3, *pllclkEn, 0x00);
+ }
+}
+
+/**
+ * Set lines power state to A0
+ * Set lines pll clk enable to 0
+ */
+static void setPowerA0(const DP_SD0801_PrivateData* pD, uint8_t laneCount)
+{
+ uint32_t pwrState = CPS_REG_READ(&pD->regBaseDp->dp_regs.PMA_POWER_STATE_REQ_p);
+ uint32_t pllclkEn = CPS_REG_READ(&pD->regBaseDp->dp_regs.PMA_PLLCLK_EN_p);
+
+ setA0PowerRegPwrState(&pwrState, laneCount);
+ setA0PowerRegPllclkEn(&pllclkEn, laneCount);
+
+ CPS_REG_WRITE(&pD->regBaseDp->dp_regs.PMA_POWER_STATE_REQ_p, pwrState);
+ CPS_REG_WRITE(&pD->regBaseDp->dp_regs.PMA_PLLCLK_EN_p, pllclkEn);
+}
+
+uint32_t DP_SD0801_PhyInit(DP_SD0801_PrivateData* pD, uint8_t laneCount, DP_SD0801_LinkRate linkRate)
+{
+ uint32_t regTmp;
+ uint8_t lane_cfg = 0U;
+#ifdef HAVE_CMN_PLL1
+ uint8_t dp_pll = 3;
+#else
+ uint8_t dp_pll = 1;
+#endif
+ uint32_t retVal = CDN_EOK;
+
+ retVal = DP_SD0801_PhyInitSF(pD);
+
+ if (CDN_EOK == retVal)
+ {
+ if ((laneCount <= 4U) && (laneCount > 0U))
+ {
+ lane_cfg = (uint8_t)((1U << (laneCount)) - 1U);
+ }
+
+ /* PHY PMA registers configuration function */
+ configurePhyPmaDpCfg(pD, lane_cfg);
+
+ setPowerA0(pD, laneCount);
+
+ /* release phy_l0*_reset_n and pma_tx_elec_idle_ln_* based on used laneCount */
+ regTmp = ((0x000FU & ~(uint32_t)lane_cfg) << 4U) | (0x000FU & (uint32_t)lane_cfg);
+ CPS_REG_WRITE(&pD->regBaseDp->dp_regs.PHY_RESET_p, regTmp);
+
+ /* release pma_xcvr_pllclk_en_ln_*, only for the master lane */
+ CPS_REG_WRITE(&pD->regBaseDp->dp_regs.PMA_PLLCLK_EN_p, 0x0001);
+
+ /* PHY PMA registers configuration functions */
+ /* Set SSC disabled on init, can be enabled on link rate change. */
+ configurePhyPmaCmnVcoCfg(pD, getVcoFreq(linkRate), false);
+ configurePhyPmaCmnDpRate(pD, lane_cfg,linkRate, dp_pll);
+
+ pD->linkState.linkRate = linkRate;
+ pD->linkState.laneCount = laneCount;
+ }
+
+ return retVal;
+}
+
+static void setPowerState(const DP_SD0801_PrivateData* pD, phyPowerstate pwrState, uint8_t laneCount)
+{
+ uint32_t regTmp;
+
+ /* Register value for power state for a single byte. */
+ uint32_t pmaPowerStateValPart;
+
+ uint32_t pmaPowerStateVal;
+ uint32_t pmaPowerStateMask;
+
+ switch (pwrState)
+ {
+ case (POWERSTATE_A0):
+ pmaPowerStateValPart = 0x01U;
+ break;
+ case (POWERSTATE_A2):
+ pmaPowerStateValPart = 0x04U;
+ break;
+ default:
+ pmaPowerStateValPart = 0x08U;
+ break;
+ }
+
+ /* Select values of registers and mask, depending on enabled lane count. */
+ switch (laneCount)
+ {
+ /* lane 0 */
+ case (0x0001):
+ pmaPowerStateVal = pmaPowerStateValPart;
+ pmaPowerStateMask = 0x0000003FU;
+ break;
+ /* lanes 0-1 */
+ case (0x0002):
+ pmaPowerStateVal = (pmaPowerStateValPart
+ | (pmaPowerStateValPart << 8));
+ pmaPowerStateMask = 0x00003F3FU;
+ break;
+ /* lanes 0-3, all */
+ default:
+ pmaPowerStateVal = (pmaPowerStateValPart
+ | (pmaPowerStateValPart << 8)
+ | (pmaPowerStateValPart << 16)
+ | (pmaPowerStateValPart << 24));
+ pmaPowerStateMask = 0x3F3F3F3FU;
+ break;
+ }
+
+ /* Set power state A<n> */
+ CPS_REG_WRITE(&pD->regBaseDp->dp_regs.PMA_POWER_STATE_REQ_p, pmaPowerStateVal);
+ /* Wait, until PHY acknowledges power state completion */
+ do {
+ regTmp = CPS_REG_READ(&pD->regBaseDp->dp_regs.PMA_POWER_STATE_ACK_p);
+ } while (((regTmp) & pmaPowerStateMask) != pmaPowerStateVal);
+ CPS_REG_WRITE(&pD->regBaseDp->dp_regs.PMA_POWER_STATE_REQ_p, 0x00000000U);
+ CPS_DelayNs(100);
+}
+
+/**
+ * Version of function DP_SD0801_PhyRun internal to driver.
+ * To be used, if parameters (sanity) are ensured to be correct by caller.
+ */
+static void phyRun(const DP_SD0801_PrivateData* pD, uint8_t laneCount)
+{
+ uint32_t regTmp;
+
+ /* waiting for ACK of pma_xcvr_pllclk_en_ln_*, only for the master lane */
+ do {
+ regTmp = CPS_REG_READ(&pD->regBaseDp->dp_regs.PMA_PLLCLK_EN_ACK_p);
+ } while (((regTmp) & 0x0001U) == 0x0000U);
+
+ CPS_DelayNs(100);
+
+ setPowerState(pD, POWERSTATE_A2, laneCount);
+ setPowerState(pD, POWERSTATE_A0, laneCount);
+}
+
+/**
+ * Enable DP Main Link lanes, after releasing PHY reset and waiting for PHY to
+ * get ready.
+ */
+uint32_t DP_SD0801_PhyRun(const DP_SD0801_PrivateData* pD, uint8_t laneCount)
+{
+ uint32_t retVal = CDN_EOK;
+
+ retVal = DP_SD0801_PhyRunSF(pD);
+
+ if (CDN_EOK == retVal)
+ {
+ phyRun(pD, laneCount);
+ }
+ return retVal;
+}
+
+/**
+ * Initialize part of PHY responsible for AUX channel.
+ */
+uint32_t DP_SD0801_ConfigurePhyAuxCtrl(const DP_SD0801_PrivateData* pD)
+{
+ uint32_t retVal = CDN_EOK;
+
+ retVal = DP_SD0801_ConfigurePhyAuxCtrSF(pD);
+
+ if (CDN_EOK == retVal)
+ {
+ CPS_REG_WRITE(&pD->regBaseDp->dp_regs.AUX_CTRL_p, 0x0003);
+ }
+ return retVal;
+}
+
+/**
+ * Version of function DP_SD0801_waitPmaCmnReady internal to driver.
+ * To be used, if parameter (sanity) is ensured to be correct by caller.
+ */
+static void waitPmaCmnReady(const DP_SD0801_PrivateData* pD)
+{
+ uint32_t regTmp;
+
+ do {
+ regTmp = CPS_REG_READ(&pD->regBaseDp->dp_regs.PMA_CMN_READY_p);
+ } while (((regTmp) & 1U) == 0U);
+}
+
+/**
+ * Wait, until PHY gets ready after releasing PHY reset signal.
+ */
+uint32_t DP_SD0801_WaitPmaCmnReady(const DP_SD0801_PrivateData* pD)
+{
+ uint32_t retVal = CDN_EOK;
+
+ retVal = DP_SD0801_WaitPmaCmnReadySF(pD);
+ if (CDN_EOK == retVal)
+ {
+ waitPmaCmnReady(pD);
+ }
+
+ return retVal;
+}
+
+/* ------------------------------------------------------------------------------------------------------------------- */
+
+uint32_t DP_SD0801_ConfigLane(DP_SD0801_PrivateData* pD, uint8_t lane, const DP_SD0801_LinkState* linkState)
+{
+ /* set voltage swing level (0 - 3) for lane (passed as parameter "lane", */
+ /* ranging 0-3) as in linkState->voltageSwing[lane] */
+ /* set pre-emphasis level (0 - 3) for lane (passed as parameter "lane", */
+ /* ranging 0-3) as in linkState->preEmphasis[lane] */
+
+ /* 3.5 Procedure: Change PMA TX Emphasis */
+ /* 2.8.3 Display Port / Embedded Display Port */
+ /* Torrent16FFC_Programmers_Guide_v0.6.pdf */
+
+ uint32_t retVal;
+ uint8_t voltageSwing;
+ uint8_t preEmphasis;
+ uint16_t regTmp;
+ DP_SD0801_VoltageCoefficients* coeffs;
+ /* Bits 9 and 10 of address indicate lane number. */
+ const uint32_t laneOffset = ((uint32_t)lane << 9);
+ uint32_t DiagAcyaAddr = (TX_DIAG_ACYA | laneOffset);
+
+ retVal = DP_SD0801_ConfigLaneSF(pD, linkState);
+ if (CDN_EOK == retVal) {
+
+ voltageSwing = linkState->voltageSwing[lane];
+ preEmphasis = linkState->preEmphasis[lane];
+
+ /* Store new settings in pD. */
+ pD->linkState.voltageSwing[lane] = voltageSwing;
+ pD->linkState.preEmphasis[lane] = preEmphasis;
+
+ /* Write register bit TX_DIAG_ACYA[0] to 1'b1 to freeze the current state of the analog TX driver. */
+ regTmp = afeRead(pD, DiagAcyaAddr);
+ regTmp |= TX_DIAG_ACYA_HBDC_MASK;
+ afeWrite(pD, DiagAcyaAddr, regTmp);
+
+ if ((voltageSwing + preEmphasis) <= 3U)
+ {
+ coeffs = &(pD->vCoeffs[voltageSwing][preEmphasis]);
+ afeWriteChanged(pD, (TX_TXCC_CTRL | laneOffset), 0x08A4);
+ afeWriteChanged(pD, (DRV_DIAG_TX_DRV | laneOffset), coeffs->DiagTxDrv);
+ afeWriteChanged(pD, (TX_TXCC_MGNFS_MULT_000 | laneOffset), coeffs->MgnfsMult);
+ afeWriteChanged(pD, (TX_TXCC_CPOST_MULT_00 | laneOffset), coeffs->CpostMult);
+ }
+
+ /* Write register bit TX_DIAG_ACYA[0] to 1'b0 */
+ /* to allow the state of the analog TX driver to reflect the new programmed. */
+ regTmp = afeRead(pD, DiagAcyaAddr);
+ regTmp &= ~(TX_DIAG_ACYA_HBDC_MASK);
+ afeWrite(pD, DiagAcyaAddr, regTmp);
+ }
+
+ return retVal;
+}
+
+/**
+ * Enable or disable PLL for selected lanes)
+ */
+static void setPllEnable(const DP_SD0801_PrivateData* pD, uint8_t laneCount, bool enable)
+{
+ uint32_t regTmp;
+ /* used to determine, which bits to check for or enable in PMA_PLLCLK_EN register */
+ uint32_t pllRegBits;
+ /* used to enable or disable lanes */
+ uint32_t pllRegWriteVal;
+
+ /* Select values of registers and mask, depending on enabled lane count. */
+ switch (laneCount)
+ {
+ /* lane 0 */
+ case (0x0001):
+ pllRegBits = 0x00000001U;
+ break;
+ /* lanes 0-1 */
+ case (0x0002):
+ pllRegBits = 0x00000003U;
+ break;
+ /* lanes 0-3, all */
+ default:
+ pllRegBits = 0x0000000FU;
+ break;
+ }
+
+ if (enable) {
+ pllRegWriteVal = pllRegBits;
+ } else {
+ pllRegWriteVal = 0x00000000U;
+ }
+
+ CPS_REG_WRITE(&pD->regBaseDp->dp_regs.PMA_PLLCLK_EN_p, pllRegWriteVal); /* Enable / disable PLL */
+ do {
+ regTmp = CPS_REG_READ(&pD->regBaseDp->dp_regs.PMA_PLLCLK_EN_ACK_p);
+ } while (((regTmp) & pllRegBits) != pllRegWriteVal);
+ CPS_DelayNs(100);
+}
+
+/**
+ * Reconfigure VCO to required one and configure Link Rate, while PLLs are
+ * disabled
+ */
+static void reconfigureLinkRate(const DP_SD0801_PrivateData* pD, DP_SD0801_LinkRate linkRate, uint8_t dpPll, uint8_t linkCfg, bool ssc)
+{
+ uint32_t regTmp;
+ /* Disable the cmn_pll0_en before re-programming the new data rate */
+ afeWrite(pD, PHY_PMA_PLL_RAW_CTRL, 0x0000U);
+
+ /* Wait for PLL ready de-assertion */
+ /* For PLL0 - PHY_PMA_CMN_CTRL2[2] == 1 */
+ /* For PLL1 - PHY_PMA_CMN_CTRL2[3] == 1 */
+ if (isPllSet(dpPll, 0)) {
+ do {
+ regTmp = afeRead(pD, PHY_PMA_CMN_CTRL2);
+ } while (((regTmp >> 2U) & 1U) == 0U);
+ }
+ if (isPllSet(dpPll, 1)) {
+ do {
+ regTmp = afeRead(pD, PHY_PMA_CMN_CTRL2);
+ } while (((regTmp >> 3U) & 1U) == 0U);
+ }
+ CPS_DelayNs(200);
+ /* DP Rate Change - VCO Output setting */
+ configurePhyPmaCmnVcoCfg(pD, getVcoFreq(linkRate), ssc);
+ configurePhyPmaCmnDpRate(pD, linkCfg, linkRate, dpPll);
+
+ /* Enable the cmn_pll0_en */
+ afeWrite(pD, PHY_PMA_PLL_RAW_CTRL, 0x0003U);
+
+ /* Wait for PLL ready assertion */
+ /* For PLL0 - PHY_PMA_CMN_CTRL2[0] == 1 */
+ /* For PLL1 - PHY_PMA_CMN_CTRL2[1] == 1 */
+ if (isPllSet(dpPll, 0)) {
+ do {
+ regTmp = afeRead(pD, PHY_PMA_CMN_CTRL2);
+ } while (((regTmp) & 1U) == 0U);
+ }
+ if (isPllSet(dpPll, 1)) {
+ do {
+ regTmp = afeRead(pD, PHY_PMA_CMN_CTRL2);
+ } while (((regTmp >> 1U) & 1U) == 0U);
+ }
+}
+
+uint32_t DP_SD0801_SetLinkRate(DP_SD0801_PrivateData* pD, const DP_SD0801_LinkState* linkState)
+{
+ /* set link rate as in linkState->linkRate */
+
+ /* Both pma_xcvr_standard_mode_ln_* and pma_xcvr_data_width_ln_* are IPS fixed */
+ /* According to above there's no need to place link in A3 power state */
+
+ uint32_t retVal;
+ uint8_t linkCfg = 0U;
+ uint8_t dpPll = 1; /* TBD how to set */
+
+ retVal = DP_SD0801_SetLinkRateSF(pD, linkState);
+ if (CDN_EOK == retVal) {
+
+ const uint8_t laneCount = linkState->laneCount;
+ const DP_SD0801_LinkRate linkRate = linkState->linkRate;
+ const bool ssc = linkState->ssc;
+
+ /* Store new settings in pD. */
+ pD->linkState.linkRate = linkRate;
+ pD->linkState.laneCount = laneCount;
+ pD->linkState.ssc = ssc;
+
+ if ((laneCount <= 4U) && (laneCount > 0U))
+ {
+ linkCfg = (uint8_t)((1U << (laneCount)) - 1U);
+ }
+
+ setPowerState(pD, POWERSTATE_A3, laneCount);
+
+ /* Disable PLLs */
+ setPllEnable(pD, laneCount, false);
+ CPS_DelayNs(100);
+
+ reconfigureLinkRate(pD, linkRate, dpPll, linkCfg, ssc);
+ /* No need as far as pma_xcvr_standard_mode_ln_* and pma_xcvr_data_width_ln_* are IPS fixed */
+ CPS_DelayNs(200);
+
+ /* Enable PLLs */
+ setPllEnable(pD, laneCount, true);
+
+ setPowerState(pD, POWERSTATE_A2, laneCount);
+ setPowerState(pD, POWERSTATE_A0, laneCount);
+ CPS_DelayNs(900); /* 100ns in total with delay in setPowerState */
+ }
+
+ return retVal;
+}
+
+static void setPhyIdleBits(uint32_t *regTmp, uint8_t laneCount)
+{
+ /* always enable lane 0 */
+ *regTmp = CPS_FLD_WRITE(DP__DP_REGS__PHY_RESET_P, PMA_TX_ELEC_IDLE_LN_0, *regTmp, 0);
+
+ /* Enable lane 1 for > 1 lanes */
+ *regTmp = CPS_FLD_WRITE(DP__DP_REGS__PHY_RESET_P, PMA_TX_ELEC_IDLE_LN_1, *regTmp, ((laneCount > 1U) ? 0U : 1U));
+
+ /* Enable lanes 2 and 3 for > 2 lanes */
+ *regTmp = CPS_FLD_WRITE(DP__DP_REGS__PHY_RESET_P, PMA_TX_ELEC_IDLE_LN_2, *regTmp, ((laneCount > 2U) ? 0U : 1U));
+ *regTmp = CPS_FLD_WRITE(DP__DP_REGS__PHY_RESET_P, PMA_TX_ELEC_IDLE_LN_3, *regTmp, ((laneCount > 2U) ? 0U : 1U));
+}
+
+/**
+ * Assert lane reset (Active low) on lane 0, among disabled lanes.
+ */
+static void resetLane0(const DP_SD0801_PrivateData* pD, uint8_t linkCfg)
+{
+ uint32_t regTmp;
+
+ /* Assert lane reset low so that unused lanes remain in reset and powered down when re-enable the link */
+ regTmp = CPS_REG_READ(&pD->regBaseDp->dp_regs.PHY_RESET_p);
+ CPS_REG_WRITE(&pD->regBaseDp->dp_regs.PHY_RESET_p, ((regTmp & 0x0000FFF0U) | (0x0000000EU & (uint32_t)linkCfg)));
+}
+
+static void startupLanes(const DP_SD0801_PrivateData* pD, uint8_t laneCount)
+{
+ uint32_t regTmp;
+ uint8_t linkCfg = 0U;
+
+ if ((laneCount <= 4U) && (laneCount > 0U))
+ {
+ linkCfg = (uint8_t)((1U << (laneCount)) - 1U);
+ }
+
+ /* Assert lane reset (Active low) on lane 0, among disabled lanes. */
+ resetLane0(pD, linkCfg);
+
+ /* Set lanes into power state A0 */
+ setPowerA0(pD, laneCount);
+
+ /* release phy_l0*_reset_n based on used laneCount */
+ regTmp = CPS_REG_READ(&pD->regBaseDp->dp_regs.PHY_RESET_p);
+ CPS_REG_WRITE(&pD->regBaseDp->dp_regs.PHY_RESET_p, ((regTmp & 0x0000FFF0U) | (0x0000000FU & (uint32_t)linkCfg)));
+}
+
+/**
+ * Start-up PHY lanes and wait for pma_cmn_ready, then delay for 100 ns
+ */
+static void startupLanesAndWait(const DP_SD0801_PrivateData* pD, uint8_t laneCount)
+{
+ startupLanes(pD, laneCount);
+
+ /* Checking pma_cmn_ready */
+ waitPmaCmnReady(pD);
+
+ CPS_DelayNs(100);
+}
+
+uint32_t DP_SD0801_EnableLanes(DP_SD0801_PrivateData* pD, const DP_SD0801_LinkState* linkState)
+{
+ /* set active lane count (1, 2 or 4) as in linkState->laneCount. */
+
+ uint32_t retVal;
+ uint32_t regTmp;
+
+ retVal = DP_SD0801_EnableLanesSF(pD, linkState);
+ if (CDN_EOK == retVal) {
+
+ const uint8_t laneCount = linkState->laneCount;
+
+ /* Store new setting in pD. */
+ pD->linkState.laneCount = laneCount;
+
+ /* Assert pma_tx_elec_idle_ln_* for disabled lanes */
+ regTmp = CPS_REG_READ(&pD->regBaseDp->dp_regs.PHY_RESET_p);
+ setPhyIdleBits(®Tmp, laneCount);
+ CPS_REG_WRITE(&pD->regBaseDp->dp_regs.PHY_RESET_p, regTmp);
+
+ /* reset the link by asserting phy_l00_reset_n low */
+ regTmp = CPS_REG_READ(&pD->regBaseDp->dp_regs.PHY_RESET_p);
+ CPS_REG_WRITE(&pD->regBaseDp->dp_regs.PHY_RESET_p, (regTmp & 0x0000FFFEU));
+
+ startupLanesAndWait(pD, laneCount);
+
+ /* release pma_xcvr_pllclk_en_ln_*, only for the master lane */
+ CPS_REG_WRITE(&pD->regBaseDp->dp_regs.PMA_PLLCLK_EN_p, 0x0001);
+
+ phyRun(pD, laneCount);
+ }
+
+ return retVal;
+}
+
+/* parasoft-begin-suppress METRICS-39-3 "The value of VOCF metric for a function should not be higher than 4, DRV-3852" */
+/**
+ * Get default values of voltage-related PHY registers, for given
+ * voltage swing and pre-emphasis.
+ */
+uint32_t DP_SD0801_GetDefaultCoeffs(const DP_SD0801_PrivateData* pD,
+ uint8_t voltageSwing,
+ uint8_t preEmphasis,
+ DP_SD0801_VoltageCoefficients* coefficients)
+{
+ /* Array consist of default values of voltage-related registers for sd0801 PHY. */
+ static const DP_SD0801_VoltageCoefficients defaults[DP_SD0801_SWING_LEVEL_COUNT][DP_SD0801_EMPHASIS_LEVEL_COUNT] = \
+ /* voltage swing 0, pre-emphasis 0->3 */
+ {{{.DiagTxDrv = 0x0003, .MgnfsMult = 0x002A, .CpostMult = 0x0000},
+ {.DiagTxDrv = 0x0003, .MgnfsMult = 0x001F, .CpostMult = 0x0014},
+ {.DiagTxDrv = 0x0003, .MgnfsMult = 0x0012, .CpostMult = 0x0020},
+ {.DiagTxDrv = 0x0003, .MgnfsMult = 0x0000, .CpostMult = 0x002A}},
+
+ /* voltage swing 1, pre-emphasis 0->3 */
+ {{.DiagTxDrv = 0x0003, .MgnfsMult = 0x001F, .CpostMult = 0x0000},
+ {.DiagTxDrv = 0x0003, .MgnfsMult = 0x0013, .CpostMult = 0x0012},
+ {.DiagTxDrv = 0x0003, .MgnfsMult = 0x0000, .CpostMult = 0x001F},
+ {.DiagTxDrv = 0xFFFF, .MgnfsMult = 0xFFFF, .CpostMult = 0xFFFF}},
+
+ /* voltage swing 2, pre-emphasis 0->3 */
+ {{.DiagTxDrv = 0x0003, .MgnfsMult = 0x0013, .CpostMult = 0x0000},
+ {.DiagTxDrv = 0x0003, .MgnfsMult = 0x0000, .CpostMult = 0x0013},
+ {.DiagTxDrv = 0xFFFF, .MgnfsMult = 0xFFFF, .CpostMult = 0xFFFF},
+ {.DiagTxDrv = 0xFFFF, .MgnfsMult = 0xFFFF, .CpostMult = 0xFFFF}},
+
+ /* voltage swing 3, pre-emphasis 0->3 */
+ {{.DiagTxDrv = 0x0003, .MgnfsMult = 0x0000, .CpostMult = 0x0000},
+ {.DiagTxDrv = 0xFFFF, .MgnfsMult = 0xFFFF, .CpostMult = 0xFFFF},
+ {.DiagTxDrv = 0xFFFF, .MgnfsMult = 0xFFFF, .CpostMult = 0xFFFF},
+ {.DiagTxDrv = 0xFFFF, .MgnfsMult = 0xFFFF, .CpostMult = 0xFFFF}}};
+
+ uint32_t retVal;
+ retVal = DP_SD0801_GetDefaultCoeffsSF(pD, voltageSwing, preEmphasis, coefficients);
+
+ if (CDN_EOK == retVal)
+ {
+ /* Fill structure with default values for voltage swing and pre-emphasis */
+ /* taken from the table. */
+ coefficients->DiagTxDrv = defaults[voltageSwing][preEmphasis].DiagTxDrv;
+ coefficients->MgnfsMult = defaults[voltageSwing][preEmphasis].MgnfsMult;
+ coefficients->CpostMult = defaults[voltageSwing][preEmphasis].CpostMult;
+ }
+
+ return retVal;
+}
+
+/* parasoft-end-suppress METRICS-39-3 */
diff --git a/packages/ti/drv/dss/src/csl/dp_sd0801/src/specific/dp_sd0801_spec.h b/packages/ti/drv/dss/src/csl/dp_sd0801/src/specific/dp_sd0801_spec.h
--- /dev/null
@@ -0,0 +1,667 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ *
+ * dp_sd0801_spec.h
+ *
+ ******************************************************************************
+ */
+
+#ifndef DP_SD0801_SPEC_H
+#define DP_SD0801_SPEC_H
+
+#define AUX_CONFIG_ADDR 0xC280U
+#define AUX_CTRL_ADDR 0xC281U
+#define PHY_RESET_ADDR 0xC288U
+#define PMA_XCVR_PLLCLK_EN_ADDR 0xC289U
+#define PMA_XCVR_PLLCLK_EN_ACK_ADDR 0xC28AU
+#define PMA_XCVR_POWER_STATE_REQ_ADDR 0xC28BU
+#define PMA_XCVR_POWER_STATE_ACK_ADDR 0xC28CU
+#define PMA_CMN_READY_ADDR 0xC28DU
+#define PMA_XCVR_TX_VMARGIN_ADDR 0xC28EU
+#define PMA_XCVR_TX_DEEMPH_ADDR 0xC28FU
+
+#define PHY_LN_0 0x0000U
+#define PHY_LN_1 0x0001U
+#define PHY_LN_2 0x0002U
+#define PHY_LN_3 0x0003U
+
+#define PHY_POWER_STATE_LN_0 0x0000U
+#define PHY_POWER_STATE_LN_1 0x0008U
+#define PHY_POWER_STATE_LN_2 0x0010U
+#define PHY_POWER_STATE_LN_3 0x0018U
+
+#define PHY_POWER_STATE_A0 0x0001U
+#define PHY_POWER_STATE_A1 0x0002U
+#define PHY_POWER_STATE_A2 0x0004U
+#define PHY_POWER_STATE_A3 0x0008U
+#define PHY_POWER_STATE_A4 0x0010U
+#define PHY_POWER_STATE_A5 0x0020U
+
+#define TX_DIAG_ACYA_HBDC_MASK 0x0001U
+
+#define CMN_BGCAL_CTRL 0x0060U
+#define CMN_BGCAL_INIT_TMR 0x0064U
+#define CMN_BGCAL_ITER_TMR 0x0065U
+#define CMN_BGCAL_OVRD 0x0061U
+#define CMN_BGCAL_START 0x0062U
+#define CMN_BGCAL_TUNE 0x0063U
+#define CMN_CDIAG_CCAL_PWRI_OVRD 0x0045U
+#define CMN_CDIAG_CCAL_PWRI_STAT 0x0046U
+#define CMN_CDIAG_CDB_DIAG 0x005cU
+#define CMN_CDIAG_CDB_PWRI_OVRD 0x0041U
+#define CMN_CDIAG_CDB_PWRI_STAT 0x0042U
+#define CMN_CDIAG_DCYA 0x005fU
+#define CMN_CDIAG_DIAG_PWRI_OVRD 0x0049U
+#define CMN_CDIAG_DIAG_PWRI_STAT 0x004aU
+#define CMN_CDIAG_PLLC_PWRI_OVRD 0x0043U
+#define CMN_CDIAG_PLLC_PWRI_STAT 0x0044U
+#define CMN_CDIAG_PRATECLK_CTRL 0x004bU
+#define CMN_CDIAG_PSMCLK_CTRL 0x004eU
+#define CMN_CDIAG_PWRI_TMR 0x0040U
+#define CMN_CDIAG_REFCLK_DRV0_CTRL 0x0050U
+#define CMN_CDIAG_REFCLK_OVRD 0x004cU
+#define CMN_CDIAG_REFCLK_TEST 0x004dU
+#define CMN_CDIAG_RST_DIAG 0x005dU
+#define CMN_CDIAG_SDOSC_CTRL 0x004fU
+#define CMN_CDIAG_XCVRC_PWRI_OVRD 0x0047U
+#define CMN_CDIAG_XCVRC_PWRI_STAT 0x0048U
+#define CMN_CMSMT_CLK_FREQ_MSMT_CTRL 0x0180U
+#define CMN_CMSMT_REF_CLK_TMR_VALUE 0x0182U
+#define CMN_CMSMT_TEST_CLK_CNT_VALUE 0x0183U
+#define CMN_CMSMT_TEST_CLK_SEL 0x0181U
+#define CMN_DIAG_ACYA 0x01efU
+#define CMN_DIAG_ATB_ADC_CTRL0 0x01eaU
+#define CMN_DIAG_ATB_ADC_CTRL1 0x01ebU
+#define CMN_DIAG_ATB_CTRL1 0x01e8U
+#define CMN_DIAG_ATB_CTRL2 0x01e9U
+#define CMN_DIAG_BANDGAP_OVRD 0x01e0U
+#define CMN_DIAG_BIAS_OVRD1 0x01e1U
+#define CMN_DIAG_BIAS_OVRD2 0x01e2U
+#define CMN_DIAG_DCYA 0x01eeU
+#define CMN_DIAG_HSRRSM_CTRL 0x01ecU
+#define CMN_DIAG_PM_CTRL 0x01e4U
+#define CMN_DIAG_RST_DIAG 0x01edU
+#define CMN_DIAG_SH_BANDGAP 0x01e5U
+#define CMN_DIAG_SH_RESISTOR 0x01e6U
+#define CMN_DIAG_SH_SDCLK 0x01e7U
+#define CMN_DIAG_VREG_CTRL 0x01e3U
+#define CMN_IBCAL_CTRL 0x0070U
+#define CMN_IBCAL_INIT_TMR 0x0074U
+#define CMN_IBCAL_ITER_TMR 0x0075U
+#define CMN_IBCAL_OVRD 0x0071U
+#define CMN_IBCAL_START 0x0072U
+#define CMN_IBCAL_TUNE 0x0073U
+#define CMN_PDIAG_PLL0_CLK_SEL_M0 0x01a1U
+#define CMN_PDIAG_PLL0_CLK_SEL_M1 0x01b1U
+#define CMN_PDIAG_PLL0_CP_IADJ_M0 0x01a5U
+#define CMN_PDIAG_PLL0_CP_IADJ_M1 0x01b5U
+#define CMN_PDIAG_PLL0_CP_PADJ_M0 0x01a4U
+#define CMN_PDIAG_PLL0_CP_PADJ_M1 0x01b4U
+#define CMN_PDIAG_PLL0_CP_TUNE_M0 0x01a7U
+#define CMN_PDIAG_PLL0_CP_TUNE_M1 0x01b7U
+#define CMN_PDIAG_PLL0_CTRL_M0 0x01a0U
+#define CMN_PDIAG_PLL0_CTRL_M1 0x01b0U
+#define CMN_PDIAG_PLL0_FILT_PADJ_M0 0x01a6U
+#define CMN_PDIAG_PLL0_FILT_PADJ_M1 0x01b6U
+#define CMN_PDIAG_PLL0_ITRIM_M0 0x01a3U
+#define CMN_PDIAG_PLL0_ITRIM_M1 0x01b3U
+#define CMN_PDIAG_PLL0_OVRD_M0 0x01a2U
+#define CMN_PDIAG_PLL0_OVRD_M1 0x01b2U
+#define CMN_PDIAG_PLL1_CLK_SEL_M0 0x01c1U
+#define CMN_PDIAG_PLL1_CLK_SEL_M1 0x01d1U
+#define CMN_PDIAG_PLL1_CP_IADJ_M0 0x01c5U
+#define CMN_PDIAG_PLL1_CP_IADJ_M1 0x01d5U
+#define CMN_PDIAG_PLL1_CP_PADJ_M0 0x01c4U
+#define CMN_PDIAG_PLL1_CP_PADJ_M1 0x01d4U
+#define CMN_PDIAG_PLL1_CP_TUNE_M0 0x01c7U
+#define CMN_PDIAG_PLL1_CP_TUNE_M1 0x01d7U
+#define CMN_PDIAG_PLL1_CTRL_M0 0x01c0U
+#define CMN_PDIAG_PLL1_CTRL_M1 0x01d0U
+#define CMN_PDIAG_PLL1_FILT_PADJ_M0 0x01c6U
+#define CMN_PDIAG_PLL1_FILT_PADJ_M1 0x01d6U
+#define CMN_PDIAG_PLL1_ITRIM_M0 0x01c3U
+#define CMN_PDIAG_PLL1_ITRIM_M1 0x01d3U
+#define CMN_PDIAG_PLL1_OVRD_M0 0x01c2U
+#define CMN_PDIAG_PLL1_OVRD_M1 0x01d2U
+#define CMN_PID_FLV0 0x000aU
+#define CMN_PID_FLV1 0x000bU
+#define CMN_PID_IOV 0x000cU
+#define CMN_PID_LANES 0x000dU
+#define CMN_PID_METAL0 0x0010U
+#define CMN_PID_METAL1 0x0011U
+#define CMN_PID_METAL2 0x0012U
+#define CMN_PID_METAL3 0x0013U
+#define CMN_PID_METALD 0x0014U
+#define CMN_PID_MFG 0x0008U
+#define CMN_PID_NODE 0x0009U
+#define CMN_PID_NUM 0x0003U
+#define CMN_PID_REV 0x0004U
+#define CMN_PID_TYPE 0x0000U
+#define CMN_PLL0_DSM_DIAG_M0 0x0094U
+#define CMN_PLL0_DSM_DIAG_M1 0x00a4U
+#define CMN_PLL0_DSM_FBH_OVRD_M0 0x0095U
+#define CMN_PLL0_DSM_FBH_OVRD_M1 0x00a5U
+#define CMN_PLL0_DSM_FBL_OVRD_M0 0x0096U
+#define CMN_PLL0_DSM_FBL_OVRD_M1 0x00a6U
+#define CMN_PLL0_FRACDIVH_M0 0x0092U
+#define CMN_PLL0_FRACDIVH_M1 0x00a2U
+#define CMN_PLL0_FRACDIVL_M0 0x0091U
+#define CMN_PLL0_FRACDIVL_M1 0x00a1U
+#define CMN_PLL0_HIGH_THR_M0 0x0093U
+#define CMN_PLL0_HIGH_THR_M1 0x00a3U
+#define CMN_PLL0_INTDIV_M0 0x0090U
+#define CMN_PLL0_INTDIV_M1 0x00a0U
+#define CMN_PLL0_LOCK_PLLCNT_START 0x009eU
+#define CMN_PLL0_LOCK_PLLCNT_THR 0x009fU
+#define CMN_PLL0_LOCK_REFCNT_IDLE 0x009dU
+#define CMN_PLL0_LOCK_REFCNT_START 0x009cU
+#define CMN_PLL0_SS_CTRL1_M0 0x0098U
+#define CMN_PLL0_SS_CTRL1_M1 0x00a8U
+#define CMN_PLL0_SS_CTRL2_M0 0x0099U
+#define CMN_PLL0_SS_CTRL2_M1 0x00a9U
+#define CMN_PLL0_SS_CTRL3_M0 0x009aU
+#define CMN_PLL0_SS_CTRL3_M1 0x00aaU
+#define CMN_PLL0_SS_CTRL4_M0 0x009bU
+#define CMN_PLL0_SS_CTRL4_M1 0x00abU
+#define CMN_PLL0_VCOCAL_CTRL 0x0080U
+#define CMN_PLL0_VCOCAL_INIT_TMR 0x0084U
+#define CMN_PLL0_VCOCAL_ITER_TMR 0x0085U
+#define CMN_PLL0_VCOCAL_OVRD 0x0083U
+#define CMN_PLL0_VCOCAL_PLLCNT_START 0x0088U
+#define CMN_PLL0_VCOCAL_REFTIM_START 0x0086U
+#define CMN_PLL0_VCOCAL_START 0x0081U
+#define CMN_PLL0_VCOCAL_TCTRL 0x0082U
+#define CMN_PLL1_DSM_DIAG_M0 0x00d4U
+#define CMN_PLL1_DSM_DIAG_M1 0x00e4U
+#define CMN_PLL1_DSM_FBH_OVRD_M0 0x00d5U
+#define CMN_PLL1_DSM_FBH_OVRD_M1 0x00e5U
+#define CMN_PLL1_DSM_FBL_OVRD_M0 0x00d6U
+#define CMN_PLL1_DSM_FBL_OVRD_M1 0x00e6U
+#define CMN_PLL1_FRACDIVH_M0 0x00d2U
+#define CMN_PLL1_FRACDIVH_M1 0x00e2U
+#define CMN_PLL1_FRACDIVL_M0 0x00d1U
+#define CMN_PLL1_FRACDIVL_M1 0x00e1U
+#define CMN_PLL1_HIGH_THR_M0 0x00d3U
+#define CMN_PLL1_HIGH_THR_M1 0x00e3U
+#define CMN_PLL1_INTDIV_M0 0x00d0U
+#define CMN_PLL1_INTDIV_M1 0x00e0U
+#define CMN_PLL1_LOCK_PLLCNT_START 0x00deU
+#define CMN_PLL1_LOCK_PLLCNT_THR 0x00dfU
+#define CMN_PLL1_LOCK_REFCNT_IDLE 0x00ddU
+#define CMN_PLL1_LOCK_REFCNT_START 0x00dcU
+#define CMN_PLL1_SS_CTRL1_M0 0x00d8U
+#define CMN_PLL1_SS_CTRL1_M1 0x00e8U
+#define CMN_PLL1_SS_CTRL2_M0 0x00d9U
+#define CMN_PLL1_SS_CTRL2_M1 0x00e9U
+#define CMN_PLL1_SS_CTRL3_M0 0x00daU
+#define CMN_PLL1_SS_CTRL3_M1 0x00eaU
+#define CMN_PLL1_SS_CTRL4_M0 0x00dbU
+#define CMN_PLL1_SS_CTRL4_M1 0x00ebU
+#define CMN_PLL1_VCOCAL_CTRL 0x00c0U
+#define CMN_PLL1_VCOCAL_INIT_TMR 0x00c4U
+#define CMN_PLL1_VCOCAL_ITER_TMR 0x00c5U
+#define CMN_PLL1_VCOCAL_OVRD 0x00c3U
+#define CMN_PLL1_VCOCAL_PLLCNT_START 0x00c8U
+#define CMN_PLL1_VCOCAL_REFTIM_START 0x00c6U
+#define CMN_PLL1_VCOCAL_START 0x00c1U
+#define CMN_PLL1_VCOCAL_TCTRL 0x00c2U
+#define CMN_PLLSM0_PLLCLKDIS_TMR 0x002dU
+#define CMN_PLLSM0_PLLEN_TMR 0x0029U
+#define CMN_PLLSM0_PLLLOCK_TMR 0x002cU
+#define CMN_PLLSM0_PLLPRE_TMR 0x002aU
+#define CMN_PLLSM0_PLLVREF_TMR 0x002bU
+#define CMN_PLLSM0_SM_CTRL 0x0028U
+#define CMN_PLLSM0_USER_DEF_CTRL 0x002fU
+#define CMN_PLLSM1_PLLCLKDIS_TMR 0x0035U
+#define CMN_PLLSM1_PLLEN_TMR 0x0031U
+#define CMN_PLLSM1_PLLLOCK_TMR 0x0034U
+#define CMN_PLLSM1_PLLPRE_TMR 0x0032U
+#define CMN_PLLSM1_PLLVREF_TMR 0x0033U
+#define CMN_PLLSM1_SM_CTRL 0x0030U
+#define CMN_PLLSM1_USER_DEF_CTRL 0x0037U
+#define CMN_RXCAL_CTRL 0x0110U
+#define CMN_RXCAL_INIT_TMR 0x0114U
+#define CMN_RXCAL_ITER_TMR 0x0115U
+#define CMN_RXCAL_OVRD 0x0111U
+#define CMN_RXCAL_START 0x0112U
+#define CMN_RXCAL_TUNE 0x0113U
+#define CMN_SD_CAL_CTRL 0x0120U
+#define CMN_SD_CAL_INIT_TMR 0x0124U
+#define CMN_SD_CAL_ITER_TMR 0x0125U
+#define CMN_SD_CAL_OVRD 0x0123U
+#define CMN_SD_CAL_PLLCNT_START 0x0128U
+#define CMN_SD_CAL_REFTIM_START 0x0126U
+#define CMN_SD_CAL_START 0x0121U
+#define CMN_SD_CAL_TCTRL 0x0122U
+#define CMN_SSM_BANDGAP_TMR 0x0021U
+#define CMN_SSM_BIAS_TMR 0x0022U
+#define CMN_SSM_SM_CTRL 0x0020U
+#define CMN_SSM_USER_DEF_CTRL 0x0027U
+#define CMN_TXPDCAL_CTRL 0x0108U
+#define CMN_TXPDCAL_INIT_TMR 0x010cU
+#define CMN_TXPDCAL_ITER_TMR 0x010dU
+#define CMN_TXPDCAL_OVRD 0x0109U
+#define CMN_TXPDCAL_START 0x010aU
+#define CMN_TXPDCAL_TUNE 0x010bU
+#define CMN_TXPUCAL_CTRL 0x0100U
+#define CMN_TXPUCAL_INIT_TMR 0x0104U
+#define CMN_TXPUCAL_ITER_TMR 0x0105U
+#define CMN_TXPUCAL_OVRD 0x0101U
+#define CMN_TXPUCAL_START 0x0102U
+#define CMN_TXPUCAL_TUNE 0x0103U
+#define DRV_DIAG_LANE_FCM_EN_MGN_TMR 0x40c2U
+#define DRV_DIAG_LANE_FCM_EN_SWAIT_TMR 0x40c1U
+#define DRV_DIAG_LANE_FCM_EN_TO 0x40c0U
+#define DRV_DIAG_LANE_FCM_EN_TUNE 0x40c3U
+#define DRV_DIAG_LFPS_CTRL 0x40c4U
+#define DRV_DIAG_RDVDET_TUNE 0x40c5U
+#define DRV_DIAG_TX_DRV 0x40c6U
+#define PHY_AUTO_CFG_SPDUP 0xc00fU
+#define PHY_ETH_ISO_MAC_CLK_CFG 0xd010U
+#define PHY_ETH_ISO_MAC_CLK_DIV 0xd011U
+#define PHY_INTERRUPT_STS 0xd012U
+#define PHY_ISO_CMN_CTRL 0xc008U
+#define PHY_ISO_LINK_CFG 0xd00aU
+#define PHY_PCS_ISO_LINK_CTRL 0xd00bU
+#define PHY_PCS_ISO_RX_CTRL 0xd008U
+#define PHY_PCS_ISO_RX_DATA_HI 0xd00fU
+#define PHY_PCS_ISO_RX_DATA_LO 0xd00eU
+#define PHY_PCS_ISO_TX_DATA_HI 0xd007U
+#define PHY_PCS_ISO_TX_DATA_LO 0xd006U
+#define PHY_PCS_ISO_TX_DMPH_LO 0xd003U
+#define PHY_PIPE_CMN_CTRL1 0xc000U
+#define PHY_PIPE_CMN_CTRL2 0xc001U
+#define PHY_PIPE_COM_LOCK_CFG1 0xc002U
+#define PHY_PIPE_COM_LOCK_CFG2 0xc003U
+#define PHY_PIPE_EIE_LOCK_CFG 0xc004U
+#define PHY_PIPE_ISO_RX_EQ_EVAL 0xd009U
+#define PHY_PIPE_ISO_TX_CTRL 0xd000U
+#define PHY_PIPE_ISO_TX_DMPH_HI 0xd004U
+#define PHY_PIPE_ISO_TX_FSLF 0xd005U
+#define PHY_PIPE_ISO_TX_LPC_HI 0xd002U
+#define PHY_PIPE_ISO_TX_LPC_LO 0xd001U
+#define PHY_PIPE_ISO_USB_BER_CNT 0xd00cU
+#define PHY_PIPE_LANE_DSBL 0xc005U
+#define PHY_PIPE_RCV_DET_INH 0xc006U
+#define PHY_PIPE_RX_ELEC_IDLE_DLY 0xc007U
+#define PHY_PLL_CFG 0xc00eU
+#define PHY_PMA_CMN_CTRL1 0xe000U
+#define PHY_PMA_CMN_CTRL2 0xe001U
+#define PHY_PMA_ISOLATION_CTRL 0xe00fU
+#define PHY_PMA_ISO_CMN_CTRL 0xe004U
+#define PHY_PMA_ISO_DATA_HI 0xf00fU
+#define PHY_PMA_ISO_DATA_LO 0xf00eU
+#define PHY_PMA_ISO_LINK_MODE 0xf00aU
+#define PHY_PMA_ISO_PLL_CTRL0 0xe005U
+#define PHY_PMA_ISO_PLL_CTRL1 0xe006U
+#define PHY_PMA_ISO_PWRST_CTRL 0xf00bU
+#define PHY_PMA_ISO_RX_EQ_CTRL 0xf00dU
+#define PHY_PMA_ISO_TX_DMPH_HI 0xf007U
+#define PHY_PMA_ISO_TX_DMPH_LO 0xf006U
+#define PHY_PMA_ISO_TX_FSLF 0xf008U
+#define PHY_PMA_ISO_TX_LPC_HI 0xf005U
+#define PHY_PMA_ISO_TX_LPC_LO 0xf004U
+#define PHY_PMA_ISO_TX_MGN 0xf009U
+#define PHY_PMA_ISO_XCVR_CTRL 0xf003U
+#define PHY_PMA_PI_POS 0xf002U
+#define PHY_PMA_PLL0_SM_STATE 0xe00bU
+#define PHY_PMA_PLL1_SM_STATE 0xe00cU
+#define PHY_PMA_PLL_RAW_CTRL 0xe003U
+#define PHY_PMA_PSM_STATE_HI 0xf011U
+#define PHY_PMA_PSM_STATE_LO 0xf010U
+#define PHY_PMA_SSM_STATE 0xe002U
+#define PHY_PMA_XCVR_CTRL 0xf000U
+#define PHY_PMA_XCVR_LPBK 0xf001U
+#define PHY_REFCLK_DET_INTERVAL 0xc012U
+#define PHY_REFCLK_DET_ISO_CTRL 0xc014U
+#define PHY_REFCLK_DET_OP_DELAY 0xc013U
+#define PHY_REFCLK_DET_THRES_HIGH 0xc011U
+#define PHY_REFCLK_DET_THRES_LOW 0xc010U
+#define PHY_STATE_CHG_TIMEOUT 0xc00aU
+#define RX_BIST_CTRL 0x80b0U
+#define RX_BIST_ERRCNT 0x80b3U
+#define RX_BIST_SYNCCNT 0x80b1U
+#define RX_BIST_UDDWR 0x80b2U
+#define RX_CDRLF_CNFG 0x8080U
+#define RX_CDRLF_CNFG2 0x8081U
+#define RX_CDRLF_CNFG3 0x8082U
+#define RX_CDRLF_FPL_TMR0 0x8084U
+#define RX_CDRLF_FPL_TMR1 0x8085U
+#define RX_CDRLF_MGN_DIAG 0x8083U
+#define RX_DIAG_ACYA 0x81ffU
+#define RX_DIAG_DCYA 0x81feU
+#define RX_DIAG_DFE_AMP_TUNE 0x81e1U
+#define RX_DIAG_DFE_AMP_TUNE_2 0x81e2U
+#define RX_DIAG_DFE_AMP_TUNE_3 0x81e3U
+#define RX_DIAG_DFE_CTRL 0x81e0U
+#define RX_DIAG_LFEQ_TUNE 0x81e6U
+#define RX_DIAG_LPBK_CTRL 0x81f8U
+#define RX_DIAG_NQST_CTRL 0x81e5U
+#define RX_DIAG_PI_CAP 0x81f5U
+#define RX_DIAG_PI_RATE 0x81f4U
+#define RX_DIAG_PI_TUNE 0x81f6U
+#define RX_DIAG_REE_DAC_CTRL 0x81e4U
+#define RX_DIAG_RST_DIAG 0x81f9U
+#define RX_DIAG_SAMP_CTRL 0x81ecU
+#define RX_DIAG_SD_TEST 0x81eaU
+#define RX_DIAG_SH_SIGDET 0x81e9U
+#define RX_DIAG_SH_SLC_EPM 0x81f2U
+#define RX_DIAG_SH_SLC_EPP 0x81f1U
+#define RX_DIAG_SH_SLC_IPM 0x81eeU
+#define RX_DIAG_SH_SLC_IPP 0x81edU
+#define RX_DIAG_SH_SLC_QPM 0x81f0U
+#define RX_DIAG_SH_SLC_QPP 0x81efU
+#define RX_DIAG_SIGDET_TUNE 0x81e8U
+#define RX_EYESURF_CTRL 0x80a0U
+#define RX_EYESURF_ERRCNT 0x80aaU
+#define RX_EYESURF_EW_COORD 0x80a9U
+#define RX_EYESURF_NS_COORD 0x80a8U
+#define RX_EYESURF_TMR_DELHIGH 0x80a5U
+#define RX_EYESURF_TMR_DELLOW 0x80a4U
+#define RX_EYESURF_TMR_TESTHIGH 0x80a7U
+#define RX_EYESURF_TMR_TESTLOW 0x80a6U
+#define RX_LFPSDET_DIAG_CTRL 0x809cU
+#define RX_LFPSDET_MD_CNT 0x8098U
+#define RX_LFPSDET_MP_CNT 0x809bU
+#define RX_LFPSDET_NS_CNT 0x8099U
+#define RX_LFPSDET_RD_CNT 0x809aU
+#define RX_PSC_A0 0x8000U
+#define RX_PSC_A1 0x8001U
+#define RX_PSC_A2 0x8002U
+#define RX_PSC_A3 0x8003U
+#define RX_PSC_A4 0x8004U
+#define RX_PSC_A5 0x8005U
+#define RX_PSC_CAL 0x8006U
+#define RX_PSC_RDY 0x8007U
+#define RX_REE_ADDR_CFG 0x8170U
+#define RX_REE_ANAENSM_DEL_TMR 0x8128U
+#define RX_REE_ATTEN_CNT 0x814aU
+#define RX_REE_ATTEN_CTRL 0x8148U
+#define RX_REE_ATTEN_DIAG 0x814cU
+#define RX_REE_ATTEN_OVRD 0x814bU
+#define RX_REE_ATTEN_THR 0x8149U
+#define RX_REE_CTRL_DATA_MASK 0x8173U
+#define RX_REE_DIAG_CTRL 0x8175U
+#define RX_REE_FIFO_DIAG 0x8174U
+#define RX_REE_GCSM1_CTRL 0x8108U
+#define RX_REE_GCSM1_EQENM_PH1 0x8109U
+#define RX_REE_GCSM1_EQENM_PH2 0x810aU
+#define RX_REE_GCSM1_RUN_PH1_TMR 0x810cU
+#define RX_REE_GCSM1_RUN_PH2_TMR 0x810dU
+#define RX_REE_GCSM1_START_TMR 0x810bU
+#define RX_REE_GCSM2_CTRL 0x8110U
+#define RX_REE_GCSM2_EQENM_PH1 0x8111U
+#define RX_REE_GCSM2_EQENM_PH2 0x8112U
+#define RX_REE_GCSM2_RUN_PH1_TMR 0x8114U
+#define RX_REE_GCSM2_RUN_PH2_TMR 0x8115U
+#define RX_REE_GCSM2_START_TMR 0x8113U
+#define RX_REE_LFEQ_CTRL 0x815cU
+#define RX_REE_LFEQ_DIAG 0x815eU
+#define RX_REE_LFEQ_OVRD 0x815dU
+#define RX_REE_OFF_COR_CTRL 0x8164U
+#define RX_REE_OFF_COR_DIAG 0x8166U
+#define RX_REE_OFF_COR_OVRD 0x8165U
+#define RX_REE_PEAK_CODE_CTRL 0x8141U
+#define RX_REE_PEAK_COVRD0 0x8145U
+#define RX_REE_PEAK_COVRD1 0x8146U
+#define RX_REE_PEAK_CTRL 0x8140U
+#define RX_REE_PEAK_DIAG 0x8147U
+#define RX_REE_PEAK_IOVRD 0x8144U
+#define RX_REE_PEAK_LTHR 0x8143U
+#define RX_REE_PEAK_UTHR 0x8142U
+#define RX_REE_PERGCSM_CTRL 0x8118U
+#define RX_REE_PERGCSM_EQENM_PH1 0x8119U
+#define RX_REE_PERGCSM_EQENM_PH2 0x811aU
+#define RX_REE_PERGCSM_RUN_PH1_TMR 0x811cU
+#define RX_REE_PERGCSM_RUN_PH2_TMR 0x811dU
+#define RX_REE_PERGCSM_START_TMR 0x811bU
+#define RX_REE_PTXEQSM_CTRL 0x8100U
+#define RX_REE_PTXEQSM_EQENM_EVAL 0x8101U
+#define RX_REE_PTXEQSM_EQENM_PEVAL 0x8102U
+#define RX_REE_PTXEQSM_MAX_EVAL_CNT 0x8105U
+#define RX_REE_PTXEQSM_PEVAL_TMR 0x8103U
+#define RX_REE_PTXEQSM_TIMEOUT_TMR 0x8104U
+#define RX_REE_SC_COR_TCNT 0x8169U
+#define RX_REE_SC_COR_WCNT 0x8168U
+#define RX_REE_SMGM_CTRL1 0x8177U
+#define RX_REE_SMGM_CTRL2 0x8178U
+#define RX_REE_TAP1_CLIP 0x8171U
+#define RX_REE_TAP1_CTRL 0x8150U
+#define RX_REE_TAP1_DIAG 0x8152U
+#define RX_REE_TAP1_OVRD 0x8151U
+#define RX_REE_TAP2TON_CLIP 0x8172U
+#define RX_REE_TAP2_CTRL 0x8154U
+#define RX_REE_TAP2_DIAG 0x8156U
+#define RX_REE_TAP2_OVRD 0x8155U
+#define RX_REE_TAP3_CTRL 0x8158U
+#define RX_REE_TAP3_DIAG 0x815aU
+#define RX_REE_TAP3_OVRD 0x8159U
+#define RX_REE_TXEQEVAL_CTRL 0x8176U
+#define RX_REE_TXEQEVAL_POST 0x817aU
+#define RX_REE_TXEQEVAL_PRE 0x8179U
+#define RX_REE_TXPOST_CODE_CTRL 0x8131U
+#define RX_REE_TXPOST_COVRD0 0x8135U
+#define RX_REE_TXPOST_COVRD1 0x8136U
+#define RX_REE_TXPOST_CTRL 0x8130U
+#define RX_REE_TXPOST_DIAG 0x8137U
+#define RX_REE_TXPOST_IOVRD 0x8134U
+#define RX_REE_TXPOST_LTHR 0x8133U
+#define RX_REE_TXPOST_UTHR 0x8132U
+#define RX_REE_TXPRE_CTRL 0x8138U
+#define RX_REE_TXPRE_DIAG 0x813aU
+#define RX_REE_TXPRE_OVRD 0x8139U
+#define RX_REE_U3GCSM_CTRL 0x8120U
+#define RX_REE_U3GCSM_EQENM_PH1 0x8121U
+#define RX_REE_U3GCSM_EQENM_PH2 0x8122U
+#define RX_REE_U3GCSM_RUN_PH1_TMR 0x8124U
+#define RX_REE_U3GCSM_RUN_PH2_TMR 0x8125U
+#define RX_REE_U3GCSM_START_TMR 0x8123U
+#define RX_REE_VGA_GAIN_CTRL 0x8160U
+#define RX_REE_VGA_GAIN_DIAG 0x8162U
+#define RX_REE_VGA_GAIN_OVRD 0x8161U
+#define RX_REE_VGA_GAIN_TGT_DIAG 0x8163U
+#define RX_SAMP_DAC_CTRL 0x8058U
+#define RX_SDCAL0_CTRL 0x8040U
+#define RX_SDCAL0_INIT_TMR 0x8044U
+#define RX_SDCAL0_ITER_TMR 0x8045U
+#define RX_SDCAL0_OVRD 0x8041U
+#define RX_SDCAL0_START 0x8042U
+#define RX_SDCAL0_TUNE 0x8043U
+#define RX_SDCAL1_CTRL 0x8048U
+#define RX_SDCAL1_INIT_TMR 0x804cU
+#define RX_SDCAL1_ITER_TMR 0x804dU
+#define RX_SDCAL1_OVRD 0x8049U
+#define RX_SDCAL1_START 0x804aU
+#define RX_SDCAL1_TUNE 0x804bU
+#define RX_SIGDET_HL_DLY_TMR 0x8091U
+#define RX_SIGDET_HL_FILT_TMR 0x8090U
+#define RX_SIGDET_HL_INIT_TMR 0x8093U
+#define RX_SIGDET_HL_MIN_TMR 0x8092U
+#define RX_SIGDET_LH_DLY_TMR 0x8095U
+#define RX_SIGDET_LH_FILT_TMR 0x8094U
+#define RX_SIGDET_LH_INIT_TMR 0x8097U
+#define RX_SIGDET_LH_MIN_TMR 0x8096U
+#define RX_SLC_CTRL 0x8060U
+#define RX_SLC_DIAG_CTRL 0x806fU
+#define RX_SLC_DIS 0x8070U
+#define RX_SLC_EPM_OVRD 0x806cU
+#define RX_SLC_EPM_STAT 0x806bU
+#define RX_SLC_EPP_OVRD 0x806aU
+#define RX_SLC_EPP_STAT 0x8069U
+#define RX_SLC_INIT_TMR 0x806dU
+#define RX_SLC_IPM_OVRD 0x8064U
+#define RX_SLC_IPM_STAT 0x8063U
+#define RX_SLC_IPP_OVRD 0x8062U
+#define RX_SLC_IPP_STAT 0x8061U
+#define RX_SLC_QPM_OVRD 0x8068U
+#define RX_SLC_QPM_STAT 0x8067U
+#define RX_SLC_QPP_OVRD 0x8066U
+#define RX_SLC_QPP_STAT 0x8065U
+#define RX_SLC_RUN_TMR 0x806eU
+#define TX_BIST_CTRL 0x4140U
+#define TX_BIST_SEED0 0x4142U
+#define TX_BIST_SEED1 0x4143U
+#define TX_BIST_UDDWR 0x4141U
+#define TX_DIAG_ACYA 0x41e7U
+#define TX_DIAG_DCYA 0x41e6U
+#define TX_DIAG_ELEC_IDLE 0x41e2U
+#define TX_DIAG_RST_DIAG 0x41e5U
+#define TX_DIAG_SFIFO_CTRL 0x41e0U
+#define TX_DIAG_SFIFO_TMR 0x41e1U
+#define TX_PSC_A0 0x4100U
+#define TX_PSC_A1 0x4101U
+#define TX_PSC_A2 0x4102U
+#define TX_PSC_A3 0x4103U
+#define TX_PSC_A4 0x4104U
+#define TX_PSC_A5 0x4105U
+#define TX_PSC_CAL 0x4106U
+#define TX_PSC_RDY 0x4107U
+#define TX_RCVDET_CTRL 0x4120U
+#define TX_RCVDET_EN_TMR 0x4122U
+#define TX_RCVDET_OVRD 0x4121U
+#define TX_RCVDET_ST_TMR 0x4123U
+#define TX_TXCC_CPOST_MULT_00 0x404cU
+#define TX_TXCC_CPOST_MULT_01 0x404dU
+#define TX_TXCC_CPOST_MULT_10 0x404eU
+#define TX_TXCC_CPOST_MULT_11 0x404fU
+#define TX_TXCC_CPRE_MULT_00 0x4048U
+#define TX_TXCC_CPRE_MULT_01 0x4049U
+#define TX_TXCC_CPRE_MULT_10 0x404aU
+#define TX_TXCC_CPRE_MULT_11 0x404bU
+#define TX_TXCC_CTRL 0x4040U
+#define TX_TXCC_LF_MULT 0x4047U
+#define TX_TXCC_MAIN_CVAL 0x4045U
+#define TX_TXCC_MAIN_OVRD 0x4042U
+#define TX_TXCC_MGNFS_MULT_000 0x4050U
+#define TX_TXCC_MGNFS_MULT_001 0x4051U
+#define TX_TXCC_MGNFS_MULT_010 0x4052U
+#define TX_TXCC_MGNFS_MULT_011 0x4053U
+#define TX_TXCC_MGNFS_MULT_100 0x4054U
+#define TX_TXCC_MGNFS_MULT_101 0x4055U
+#define TX_TXCC_MGNFS_MULT_110 0x4056U
+#define TX_TXCC_MGNFS_MULT_111 0x4057U
+#define TX_TXCC_MGNLS_MULT_000 0x4058U
+#define TX_TXCC_MGNLS_MULT_001 0x4059U
+#define TX_TXCC_MGNLS_MULT_010 0x405aU
+#define TX_TXCC_MGNLS_MULT_011 0x405bU
+#define TX_TXCC_MGNLS_MULT_100 0x405cU
+#define TX_TXCC_MGNLS_MULT_101 0x405dU
+#define TX_TXCC_MGNLS_MULT_110 0x405eU
+#define TX_TXCC_MGNLS_MULT_111 0x405fU
+#define TX_TXCC_P0POST_COEF_MULT 0x4070U
+#define TX_TXCC_P0PRE_COEF_MULT 0x4060U
+#define TX_TXCC_P1POST_COEF_MULT 0x4071U
+#define TX_TXCC_P1PRE_COEF_MULT 0x4061U
+#define TX_TXCC_P2POST_COEF_MULT 0x4072U
+#define TX_TXCC_P2PRE_COEF_MULT 0x4062U
+#define TX_TXCC_P3POST_COEF_MULT 0x4073U
+#define TX_TXCC_P3PRE_COEF_MULT 0x4063U
+#define TX_TXCC_P4POST_COEF_MULT 0x4074U
+#define TX_TXCC_P4PRE_COEF_MULT 0x4064U
+#define TX_TXCC_P5POST_COEF_MULT 0x4075U
+#define TX_TXCC_P5PRE_COEF_MULT 0x4065U
+#define TX_TXCC_P6POST_COEF_MULT 0x4076U
+#define TX_TXCC_P6PRE_COEF_MULT 0x4066U
+#define TX_TXCC_P7POST_COEF_MULT 0x4077U
+#define TX_TXCC_P7PRE_COEF_MULT 0x4067U
+#define TX_TXCC_P8POST_COEF_MULT 0x4078U
+#define TX_TXCC_P8PRE_COEF_MULT 0x4068U
+#define TX_TXCC_P9POST_COEF_MULT 0x4079U
+#define TX_TXCC_P9PRE_COEF_MULT 0x4069U
+#define TX_TXCC_POST_CVAL 0x4046U
+#define TX_TXCC_POST_OVRD 0x4043U
+#define TX_TXCC_PRE_CVAL 0x4044U
+#define TX_TXCC_PRE_OVRD 0x4041U
+#define XCVR_CMSMT_CLK_FREQ_MSMT_CTRL 0x81c0U
+#define XCVR_CMSMT_REF_CLK_TMR_VALUE 0x81c2U
+#define XCVR_CMSMT_TEST_CLK_CNT_VALUE 0x81c3U
+#define XCVR_CMSMT_TEST_CLK_SEL 0x81c1U
+#define XCVR_DIAG_BIDI_CTRL 0x40eaU
+#define XCVR_DIAG_DCYA 0x40efU
+#define XCVR_DIAG_HSCLK_DIV 0x40e7U
+#define XCVR_DIAG_HSCLK_SEL 0x40e6U
+#define XCVR_DIAG_PLLDRC_CTRL 0x40e5U
+#define XCVR_DIAG_PSC_OVRD 0x40ebU
+#define XCVR_DIAG_PWRI_TMR 0x40e0U
+#define XCVR_DIAG_RST_DIAG 0x40ecU
+#define XCVR_DIAG_RXCLK_CTRL 0x40e9U
+#define XCVR_DIAG_TXCLK_CTRL 0x40e8U
+#define XCVR_DIAG_XCAL_PWRI_OVRD 0x40e1U
+#define XCVR_DIAG_XCAL_PWRI_STAT 0x40e2U
+#define XCVR_DIAG_XCVR_CLK_CTRL 0x40edU
+#define XCVR_DIAG_XDP_PWRI_OVRD 0x40e3U
+#define XCVR_DIAG_XDP_PWRI_STAT 0x40e4U
+#define XCVR_PSM_A0BYP_TMR 0x4004U
+#define XCVR_PSM_A0IN_TMR 0x4003U
+#define XCVR_PSM_A0OUT_TMR 0x400bU
+#define XCVR_PSM_A1IN_TMR 0x4005U
+#define XCVR_PSM_A1OUT_TMR 0x400cU
+#define XCVR_PSM_A2IN_TMR 0x4006U
+#define XCVR_PSM_A2OUT_TMR 0x400dU
+#define XCVR_PSM_A3IN_TMR 0x4007U
+#define XCVR_PSM_A3OUT_TMR 0x400eU
+#define XCVR_PSM_A4IN_TMR 0x4008U
+#define XCVR_PSM_A4OUT_TMR 0x400fU
+#define XCVR_PSM_A5IN_TMR 0x4009U
+#define XCVR_PSM_A5OUT_TMR 0x4010U
+#define XCVR_PSM_CALIN_TMR 0x4002U
+#define XCVR_PSM_CALOUT_TMR 0x400aU
+#define XCVR_PSM_CTRL 0x4000U
+#define XCVR_PSM_DIAG 0x4012U
+#define XCVR_PSM_RCTRL 0x4001U
+#define XCVR_PSM_RDY_TMR 0x4011U
+#define XCVR_PSM_ST_0 0x4013U
+#define XCVR_PSM_ST_1 0x4014U
+#define XCVR_PSM_USER_DEF_CTRL 0x401fU
+
+/* ****************************** */
+/* VCO Cal Frequency programming */
+/* ****************************** */
+/* 4'b0000: 10G */
+/* 4'b0001: 8G Not Ring Osc Mode */
+/* 4'b0010: 8G Ring Osc Mode (JESD) */
+/* 4'b0011: 10.8G */
+/* 4'b0100: 9.72G */
+/* 4'b0101: 8.64G */
+/* 4'b0110: 8.1G */
+/* 4'b0111: 6.25G */
+/* 4'b1000: 6G */
+/* 4'b1001: 4G */
+/* 4'b1010: 10.3125G */
+/* ****************************** */
+typedef enum
+{
+ VCO_10GHz8_refclk = 0,
+ VCO_9GHz72_refclk = 1,
+ VCO_8GHz64_refclk = 2,
+ VCO_8GHz1_refclk = 3
+} ENUM_VCO_FREQ;
+
+#endif /* DP_SD0801_SPEC_H */
diff --git a/packages/ti/drv/dss/src/csl/dp_sd0801/src/src_files_sd0801.mk b/packages/ti/drv/dss/src/csl/dp_sd0801/src/src_files_sd0801.mk
--- /dev/null
@@ -0,0 +1,3 @@
+SRCDIR += src/csl/dp_sd0801/src src/csl/dp_sd0801/src/specific
+INCDIR += src/csl/dp_sd0801/include src/csl/dp_sd0801/src src/csl/dp_sd0801/src/specific
+SRCS_COMMON += dp_sd0801.c dp_sd0801_sanity.c dp_sd0801_spec.c dp_dummy_spec.c
diff --git a/packages/ti/drv/dss/src/csl/dphy/csl_dphy.h b/packages/ti/drv/dss/src/csl/dphy/csl_dphy.h
--- /dev/null
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) Texas Instruments Incorporated 2018
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+/**
+ * \file csl_dphy.h
+ *
+ * \brief CSL APIs for DPHY.
+ */
+
+#ifndef CSL_DPHY_H_
+#define CSL_DPHY_H_
+
+#include <src/csl/dphy/cslr_dphy.h>
+#include <src/csl/dphy/include/cdn_errno.h>
+#include <src/csl/dphy/include/dphy_if.h>
+#include <src/csl/dphy/include/dphy_structs_if.h>
+
+#endif
diff --git a/packages/ti/drv/dss/src/csl/dphy/cslr_dphy.h b/packages/ti/drv/dss/src/csl/dphy/cslr_dphy.h
--- /dev/null
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) Texas Instruments Incorporated 2018
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+/**
+ * \file cslr_dphy.h
+ *
+ * \brief CSLR for DPHY.
+ */
+
+#ifndef CSLR_DPHY_H_
+#define CSLR_DPHY_H_
+
+#include <stdbool.h>
+#include <stddef.h>
+#include <stdint.h>
+
+#include <ti/csl/cslr_dss.h>
+#include <src/csl/dphy/include/dphy_regs.h>
+#include <src/csl/dphy/include/dphy_regs_macros.h>
+#include <src/csl/dphy/include/cslr_wiz16b8m4cdt.h>
+
+#endif
diff --git a/packages/ti/drv/dss/src/csl/dphy/include/cdn_errno.h b/packages/ti/drv/dss/src/csl/dphy/include/cdn_errno.h
--- /dev/null
@@ -0,0 +1,165 @@
+/******************************************************************************
+ * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ * cdn_errno.h
+ * Cadence error codes
+ ******************************************************************************
+ */
+
+#ifndef INCLUDE_CDN_ERRNO_H
+#define INCLUDE_CDN_ERRNO_H
+
+#ifndef ERRNO_H_NOT_PRESENT
+#include <errno.h>
+#endif //ERRNO_H_NOT_PRESENT
+
+#ifndef REMOVE_OLD_ERRORCODES
+
+#ifndef EOK
+#define EOK 0 /* no error */
+#endif //EOK
+
+#ifndef EPERM
+#define EPERM 1 /* Operation not permitted */
+#endif //EPERM
+
+#ifndef ENOENT
+#define ENOENT 2 /* No such file or directory */
+#endif //ENOENT
+
+#ifndef EIO
+#define EIO 5 /* I/O error */
+#endif //EIO
+
+#ifndef ENOEXEC
+#define ENOEXEC 8 /* Exec format error */
+#endif //ENOEXEC
+
+#ifndef EAGAIN
+#define EAGAIN 11 /* Try again */
+#endif //EAGAIN
+
+#ifndef ENOMEM
+#define ENOMEM 12 /* Out of memory */
+#endif //ENOMEM
+
+#ifndef EFAULT
+#define EFAULT 14 /* Bad address */
+#endif //EFAULT
+
+#ifndef EBUSY
+#define EBUSY 16 /* Device or resource busy */
+#endif //EBUSY
+
+#ifndef EINVAL
+#define EINVAL 22 /* Invalid argument */
+#endif //EINVAL
+
+#ifndef ENOSPC
+#define ENOSPC 28 /* No space left on device */
+#endif //ENOSPC
+
+#ifndef EBADSLT
+#define EBADSLT 57 /* Invalid slot */
+#endif //EBADSLT
+
+#ifndef EPROTO
+#define EPROTO 71 /* Protocol error */
+#endif //EPROTO
+
+#ifndef EOVERFLOW
+#define EOVERFLOW 75 /* Value too large for defined data type */
+#endif //EOVERFLOW
+
+#ifndef EOPNOTSUPP
+#define EOPNOTSUPP 95 /* Operation not supported */
+#endif //EOPNOTSUPP
+
+#ifndef ETIMEDOUT
+#define ETIMEDOUT 110 /* Connection timed out */
+#endif //ETIMEDOUT
+
+#ifndef EINPROGRESS
+#define EINPROGRESS 115 /* Operation now in progress */
+#endif //EINPROGRESS
+
+#ifndef EDQUOT
+#define EDQUOT 122 /* Quota exceeded */
+#endif //EDQUOT
+
+#ifndef ENOTSUP
+#define ENOTSUP EOPNOTSUPP
+#endif //ENOTSUP
+
+#ifndef ECANCELED
+#define ECANCELED 126 /* Cancelled */
+#endif //ECANCELED
+
+#endif //REMOVE_OLD_ERRORCODES
+
+#define CDN_EOK 0U /* no error */
+
+#define CDN_EPERM 1U /* Operation not permitted */
+
+#define CDN_ENOENT 2U /* No such file or directory */
+
+#define CDN_EIO 5U /* I/O error */
+
+#define CDN_ENOEXEC 8U /* Exec format error */
+
+#define CDN_EAGAIN 11U /* Try again */
+
+#define CDN_ENOMEM 12U /* Out of memory */
+
+#define CDN_EFAULT 14U /* Bad address */
+
+#define CDN_EBUSY 16U /* Device or resource busy */
+
+#define CDN_EINVAL 22U /* Invalid argument */
+
+#define CDN_ENOSPC 28U /* No space left on device */
+
+#define CDN_EBADSLT 57U /* Invalid slot */
+
+#define CDN_EPROTO 71U /* Protocol error */
+
+#define CDN_EOVERFLOW 75U /* Value too large for defined data type */
+
+#define CDN_EOPNOTSUPP 95U /* Operation not supported */
+
+#define CDN_ETIMEDOUT 110U /* Connection timed out */
+
+#define CDN_EINPROGRESS 115U /* Operation now in progress */
+
+#define CDN_EDQUOT 122U /* Quota exceeded */
+
+#define CDN_ENOTSUP CDN_EOPNOTSUPP
+
+#define CDN_ECANCELED 126U /* Cancelled */
+
+#endif //INCLUDE_CDN_ERRNO_H
diff --git a/packages/ti/drv/dss/src/csl/dphy/include/cslr_wiz16b8m4cdt.h b/packages/ti/drv/dss/src/csl/dphy/include/cslr_wiz16b8m4cdt.h
--- /dev/null
@@ -0,0 +1,5828 @@
+/********************************************************************
+ * Copyright (C) 2019 Texas Instruments Incorporated.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Name : cslr_wiz16b8m4cdt.h
+*/
+#ifndef CSLR_WIZ16B8M4CDT_H_
+#define CSLR_WIZ16B8M4CDT_H_
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+#include <ti/csl/cslr.h>
+#include <stdint.h>
+
+/**************************************************************************
+* Module Base Offset Values
+**************************************************************************/
+
+#define CSL_WIZ16B8M4CDT_REGS_BASE (0x00000000U)
+
+
+/**************************************************************************
+* Hardware Region : wiz16b8m4cdt registers
+**************************************************************************/
+
+
+/**************************************************************************
+* Register Overlay Structure
+**************************************************************************/
+
+typedef struct {
+ volatile uint32_t CMN0_CMN_ANA_TBIT0;
+ volatile uint32_t CMN0_CMN_ANA_TBIT1;
+ volatile uint32_t CMN0_CMN_ANA_TBIT2;
+ volatile uint32_t CMN0_CMN_ANA_TBIT3;
+ volatile uint32_t CMN0_CMN_ANA_TBIT4;
+ volatile uint32_t CMN0_CMN_ANA_TBIT5;
+ volatile uint32_t CMN0_CMN_DIG_TBIT0;
+ volatile uint32_t CMN0_CMN_DIG_TBIT1;
+ volatile uint32_t CMN0_CMN_DIG_TBIT2;
+ volatile uint32_t CMN0_CMN_DIG_TBIT3;
+ volatile uint32_t CMN0_CMN_DIG_TBIT4;
+ volatile uint32_t CMN0_CMN_DIG_TBIT5;
+ volatile uint32_t CMN0_CMN_DIG_TBIT6;
+ volatile uint32_t CMN0_CMN_DIG_TBIT7;
+ volatile uint32_t CMN0_CMN_DIG_TBIT8;
+ volatile uint32_t CMN0_CMN_DIG_TBIT9;
+ volatile uint32_t CMN0_CMN_DIG_TBIT10;
+ volatile uint32_t CMN0_CMN_DIG_TBIT11;
+ volatile uint32_t CMN0_CMN_DIG_TBIT12;
+ volatile uint32_t CMN0_CMN_DIG_TBIT13;
+ volatile uint32_t CMN0_CMN_DIG_TBIT14;
+ volatile uint8_t Resv_104[20];
+ volatile uint32_t CMN0_CMN_DIG_TBIT20;
+ volatile uint32_t CMN0_CMN_DIG_TBIT21;
+ volatile uint32_t CMN0_CMN_DIG_TBIT22;
+ volatile uint32_t CMN0_CMN_DIG_TBIT23;
+ volatile uint32_t CMN0_CMN_DIG_TBIT24;
+ volatile uint32_t CMN0_CMN_DIG_TBIT25;
+ volatile uint32_t CMN0_CMN_DIG_TBIT26;
+ volatile uint32_t CMN0_CMN_DIG_TBIT27;
+ volatile uint32_t CMN0_CMN_DIG_TBIT28;
+ volatile uint8_t Resv_148[8];
+ volatile uint32_t CMN0_CMN_DIG_TBIT31;
+ volatile uint32_t CMN0_CMN_DIG_TBIT32;
+ volatile uint32_t CMN0_CMN_DIG_TBIT33;
+ volatile uint32_t CMN0_CMN_DIG_TBIT34;
+ volatile uint32_t CMN0_CMN_DIG_TBIT35;
+ volatile uint32_t CMN0_CMN_DIG_TBIT36;
+ volatile uint32_t CMN0_CMN_DIG_TBIT37;
+ volatile uint8_t Resv_180[4];
+ volatile uint32_t CMN0_CMN_DIG_TBIT39;
+ volatile uint8_t Resv_216[32];
+ volatile uint32_t CMN0_CMN_DIG_TBIT50;
+ volatile uint8_t Resv_228[8];
+ volatile uint32_t CMN0_CMN_DIG_TBIT53;
+ volatile uint32_t CMN0_CMN_DIG_TBIT54;
+ volatile uint8_t Resv_240[4];
+ volatile uint32_t CMN0_CMN_DIG_TBIT56;
+ volatile uint8_t Resv_248[4];
+ volatile uint32_t CMN0_CMN_DIG_TBIT58;
+ volatile uint8_t Resv_256[4];
+ volatile uint32_t CLK0_TX_ANA_TBIT0;
+ volatile uint32_t CLK0_TX_ANA_TBIT1;
+ volatile uint32_t CLK0_TX_ANA_TBIT2;
+ volatile uint32_t CLK0_TX_ANA_TBIT3;
+ volatile uint32_t CLK0_TX_ANA_TBIT4;
+ volatile uint8_t Resv_284[8];
+ volatile uint32_t CLK0_TX_DIG_TBIT0;
+ volatile uint32_t CLK0_TX_DIG_TBIT1;
+ volatile uint32_t CLK0_TX_DIG_TBIT2;
+ volatile uint8_t Resv_316[20];
+ volatile uint32_t CLK0_TX_DIG_TBIT8;
+ volatile uint32_t CLK0_TX_DIG_TBIT9;
+ volatile uint32_t CLK0_TX_DIG_TBIT10;
+ volatile uint8_t Resv_340[12];
+ volatile uint32_t CLK0_TX_DIG_TBIT14;
+ volatile uint32_t CLK0_TX_DIG_TBIT15;
+ volatile uint32_t CLK0_TX_DIG_TBIT16;
+ volatile uint32_t CLK0_TX_DIG_TBIT17;
+ volatile uint32_t CLK0_TX_DIG_TBIT18;
+ volatile uint32_t CLK0_TX_DIG_TBIT19;
+ volatile uint32_t CLK0_TX_DIG_TBIT20;
+ volatile uint32_t CLK0_TX_ANA_TBIT5;
+ volatile uint8_t Resv_380[8];
+ volatile uint32_t CLK0_TX_DIG_TBIT21;
+ volatile uint32_t CLK0_TX_DIG_TBIT22;
+ volatile uint8_t Resv_392[4];
+ volatile uint32_t CLK0_TX_DIG_TBIT24;
+ volatile uint32_t CLK0_TX_DIG_TBIT25;
+ volatile uint32_t CLK0_TX_DIG_TBIT26;
+ volatile uint32_t CLK0_TX_DIG_TBIT27;
+ volatile uint32_t CLK0_TX_DIG_TBIT28;
+ volatile uint32_t CLK0_TX_DIG_TBIT29;
+ volatile uint8_t Resv_512[96];
+ volatile uint32_t DL0_TX_ANA_TBIT0;
+ volatile uint32_t DL0_TX_ANA_TBIT1;
+ volatile uint32_t DL0_TX_ANA_TBIT2;
+ volatile uint32_t DL0_TX_ANA_TBIT3;
+ volatile uint32_t DL0_TX_ANA_TBIT4;
+ volatile uint8_t Resv_540[8];
+ volatile uint32_t DL0_TX_DIG_TBIT0;
+ volatile uint32_t DL0_TX_DIG_TBIT1;
+ volatile uint32_t DL0_TX_DIG_TBIT2;
+ volatile uint32_t DL0_TX_DIG_TBIT3;
+ volatile uint32_t DL0_TX_DIG_TBIT4;
+ volatile uint32_t DL0_TX_DIG_TBIT5;
+ volatile uint32_t DL0_TX_DIG_TBIT6;
+ volatile uint32_t DL0_TX_DIG_TBIT7;
+ volatile uint32_t DL0_TX_DIG_TBIT8;
+ volatile uint32_t DL0_TX_DIG_TBIT9;
+ volatile uint32_t DL0_TX_DIG_TBIT10;
+ volatile uint32_t DL0_TX_DIG_TBIT11;
+ volatile uint32_t DL0_TX_DIG_TBIT12;
+ volatile uint32_t DL0_TX_DIG_TBIT13;
+ volatile uint32_t DL0_TX_DIG_TBIT14;
+ volatile uint32_t DL0_TX_DIG_TBIT15;
+ volatile uint32_t DL0_TX_DIG_TBIT16;
+ volatile uint32_t DL0_TX_DIG_TBIT17;
+ volatile uint32_t DL0_TX_DIG_TBIT18;
+ volatile uint32_t DL0_TX_DIG_TBIT19;
+ volatile uint32_t DL0_TX_DIG_TBIT20;
+ volatile uint32_t DL0_TX_DIG_TBIT21;
+ volatile uint32_t DL0_TX_DIG_TBIT22;
+ volatile uint32_t DL0_TX_DIG_TBIT23;
+ volatile uint32_t DL0_TX_DIG_TBIT24;
+ volatile uint32_t DL0_TX_ANA_TBIT5;
+ volatile uint8_t Resv_652[8];
+ volatile uint32_t DL0_TX_DIG_TBIT25;
+ volatile uint32_t DL0_TX_DIG_TBIT26;
+ volatile uint8_t Resv_664[4];
+ volatile uint32_t DL0_TX_DIG_TBIT28;
+ volatile uint32_t DL0_TX_DIG_TBIT29;
+ volatile uint32_t DL0_TX_DIG_TBIT30;
+ volatile uint32_t DL0_TX_DIG_TBIT31;
+ volatile uint32_t DL0_TX_DIG_TBIT32;
+ volatile uint32_t DL0_TX_DIG_TBIT33;
+ volatile uint32_t DL0_TX_DIG_TBIT34;
+ volatile uint32_t DL0_TX_DIG_TBIT35;
+ volatile uint32_t DL0_TX_DIG_TBIT36;
+ volatile uint8_t Resv_768[68];
+ volatile uint32_t DL1_TX_ANA_TBIT0;
+ volatile uint32_t DL1_TX_ANA_TBIT1;
+ volatile uint32_t DL1_TX_ANA_TBIT2;
+ volatile uint32_t DL1_TX_ANA_TBIT3;
+ volatile uint32_t DL1_TX_ANA_TBIT4;
+ volatile uint8_t Resv_796[8];
+ volatile uint32_t DL1_TX_DIG_TBIT0;
+ volatile uint32_t DL1_TX_DIG_TBIT1;
+ volatile uint32_t DL1_TX_DIG_TBIT2;
+ volatile uint32_t DL1_TX_DIG_TBIT3;
+ volatile uint32_t DL1_TX_DIG_TBIT4;
+ volatile uint32_t DL1_TX_DIG_TBIT5;
+ volatile uint32_t DL1_TX_DIG_TBIT6;
+ volatile uint32_t DL1_TX_DIG_TBIT7;
+ volatile uint32_t DL1_TX_DIG_TBIT8;
+ volatile uint32_t DL1_TX_DIG_TBIT9;
+ volatile uint32_t DL1_TX_DIG_TBIT10;
+ volatile uint32_t DL1_TX_DIG_TBIT11;
+ volatile uint32_t DL1_TX_DIG_TBIT12;
+ volatile uint32_t DL1_TX_DIG_TBIT13;
+ volatile uint32_t DL1_TX_DIG_TBIT14;
+ volatile uint32_t DL1_TX_DIG_TBIT15;
+ volatile uint32_t DL1_TX_DIG_TBIT16;
+ volatile uint32_t DL1_TX_DIG_TBIT17;
+ volatile uint32_t DL1_TX_DIG_TBIT18;
+ volatile uint32_t DL1_TX_DIG_TBIT19;
+ volatile uint32_t DL1_TX_DIG_TBIT20;
+ volatile uint32_t DL1_TX_DIG_TBIT21;
+ volatile uint32_t DL1_TX_DIG_TBIT22;
+ volatile uint32_t DL1_TX_DIG_TBIT23;
+ volatile uint32_t DL1_TX_DIG_TBIT24;
+ volatile uint32_t DL1_TX_ANA_TBIT5;
+ volatile uint8_t Resv_908[8];
+ volatile uint32_t DL1_TX_DIG_TBIT25;
+ volatile uint32_t DL1_TX_DIG_TBIT26;
+ volatile uint8_t Resv_920[4];
+ volatile uint32_t DL1_TX_DIG_TBIT28;
+ volatile uint32_t DL1_TX_DIG_TBIT29;
+ volatile uint32_t DL1_TX_DIG_TBIT30;
+ volatile uint32_t DL1_TX_DIG_TBIT31;
+ volatile uint32_t DL1_TX_DIG_TBIT32;
+ volatile uint32_t DL1_TX_DIG_TBIT33;
+ volatile uint32_t DL1_TX_DIG_TBIT34;
+ volatile uint32_t DL1_TX_DIG_TBIT35;
+ volatile uint32_t DL1_TX_DIG_TBIT36;
+ volatile uint8_t Resv_1024[68];
+ volatile uint32_t DL2_TX_ANA_TBIT0;
+ volatile uint32_t DL2_TX_ANA_TBIT1;
+ volatile uint32_t DL2_TX_ANA_TBIT2;
+ volatile uint32_t DL2_TX_ANA_TBIT3;
+ volatile uint32_t DL2_TX_ANA_TBIT4;
+ volatile uint8_t Resv_1052[8];
+ volatile uint32_t DL2_TX_DIG_TBIT0;
+ volatile uint32_t DL2_TX_DIG_TBIT1;
+ volatile uint32_t DL2_TX_DIG_TBIT2;
+ volatile uint32_t DL2_TX_DIG_TBIT3;
+ volatile uint32_t DL2_TX_DIG_TBIT4;
+ volatile uint32_t DL2_TX_DIG_TBIT5;
+ volatile uint32_t DL2_TX_DIG_TBIT6;
+ volatile uint32_t DL2_TX_DIG_TBIT7;
+ volatile uint32_t DL2_TX_DIG_TBIT8;
+ volatile uint32_t DL2_TX_DIG_TBIT9;
+ volatile uint32_t DL2_TX_DIG_TBIT10;
+ volatile uint32_t DL2_TX_DIG_TBIT11;
+ volatile uint32_t DL2_TX_DIG_TBIT12;
+ volatile uint32_t DL2_TX_DIG_TBIT13;
+ volatile uint32_t DL2_TX_DIG_TBIT14;
+ volatile uint32_t DL2_TX_DIG_TBIT15;
+ volatile uint32_t DL2_TX_DIG_TBIT16;
+ volatile uint32_t DL2_TX_DIG_TBIT17;
+ volatile uint32_t DL2_TX_DIG_TBIT18;
+ volatile uint32_t DL2_TX_DIG_TBIT19;
+ volatile uint32_t DL2_TX_DIG_TBIT20;
+ volatile uint32_t DL2_TX_DIG_TBIT21;
+ volatile uint32_t DL2_TX_DIG_TBIT22;
+ volatile uint32_t DL2_TX_DIG_TBIT23;
+ volatile uint32_t DL2_TX_DIG_TBIT24;
+ volatile uint32_t DL2_TX_ANA_TBIT5;
+ volatile uint8_t Resv_1164[8];
+ volatile uint32_t DL2_TX_DIG_TBIT25;
+ volatile uint32_t DL2_TX_DIG_TBIT26;
+ volatile uint8_t Resv_1176[4];
+ volatile uint32_t DL2_TX_DIG_TBIT28;
+ volatile uint32_t DL2_TX_DIG_TBIT29;
+ volatile uint32_t DL2_TX_DIG_TBIT30;
+ volatile uint32_t DL2_TX_DIG_TBIT31;
+ volatile uint32_t DL2_TX_DIG_TBIT32;
+ volatile uint32_t DL2_TX_DIG_TBIT33;
+ volatile uint32_t DL2_TX_DIG_TBIT34;
+ volatile uint32_t DL2_TX_DIG_TBIT35;
+ volatile uint32_t DL2_TX_DIG_TBIT36;
+ volatile uint8_t Resv_1280[68];
+ volatile uint32_t DL3_TX_ANA_TBIT0;
+ volatile uint32_t DL3_TX_ANA_TBIT1;
+ volatile uint32_t DL3_TX_ANA_TBIT2;
+ volatile uint32_t DL3_TX_ANA_TBIT3;
+ volatile uint32_t DL3_TX_ANA_TBIT4;
+ volatile uint8_t Resv_1308[8];
+ volatile uint32_t DL3_TX_DIG_TBIT0;
+ volatile uint32_t DL3_TX_DIG_TBIT1;
+ volatile uint32_t DL3_TX_DIG_TBIT2;
+ volatile uint32_t DL3_TX_DIG_TBIT3;
+ volatile uint32_t DL3_TX_DIG_TBIT4;
+ volatile uint32_t DL3_TX_DIG_TBIT5;
+ volatile uint32_t DL3_TX_DIG_TBIT6;
+ volatile uint32_t DL3_TX_DIG_TBIT7;
+ volatile uint32_t DL3_TX_DIG_TBIT8;
+ volatile uint32_t DL3_TX_DIG_TBIT9;
+ volatile uint32_t DL3_TX_DIG_TBIT10;
+ volatile uint32_t DL3_TX_DIG_TBIT11;
+ volatile uint32_t DL3_TX_DIG_TBIT12;
+ volatile uint32_t DL3_TX_DIG_TBIT13;
+ volatile uint32_t DL3_TX_DIG_TBIT14;
+ volatile uint32_t DL3_TX_DIG_TBIT15;
+ volatile uint32_t DL3_TX_DIG_TBIT16;
+ volatile uint32_t DL3_TX_DIG_TBIT17;
+ volatile uint32_t DL3_TX_DIG_TBIT18;
+ volatile uint32_t DL3_TX_DIG_TBIT19;
+ volatile uint32_t DL3_TX_DIG_TBIT20;
+ volatile uint32_t DL3_TX_DIG_TBIT21;
+ volatile uint32_t DL3_TX_DIG_TBIT22;
+ volatile uint32_t DL3_TX_DIG_TBIT23;
+ volatile uint32_t DL3_TX_DIG_TBIT24;
+ volatile uint32_t DL3_TX_ANA_TBIT5;
+ volatile uint8_t Resv_1420[8];
+ volatile uint32_t DL3_TX_DIG_TBIT25;
+ volatile uint32_t DL3_TX_DIG_TBIT26;
+ volatile uint8_t Resv_1432[4];
+ volatile uint32_t DL3_TX_DIG_TBIT28;
+ volatile uint32_t DL3_TX_DIG_TBIT29;
+ volatile uint32_t DL3_TX_DIG_TBIT30;
+ volatile uint32_t DL3_TX_DIG_TBIT31;
+ volatile uint32_t DL3_TX_DIG_TBIT32;
+ volatile uint32_t DL3_TX_DIG_TBIT33;
+ volatile uint32_t DL3_TX_DIG_TBIT34;
+ volatile uint32_t DL3_TX_DIG_TBIT35;
+ volatile uint32_t DL3_TX_DIG_TBIT36;
+ volatile uint8_t Resv_2816[1348];
+ volatile uint32_t PCS_TX_DIG_TBIT0;
+ volatile uint32_t PCS_TX_DIG_TBIT1;
+ volatile uint32_t PCS_TX_DIG_TBIT2;
+ volatile uint32_t PCS_TX_DIG_TBIT3;
+ volatile uint32_t PCS_TX_DIG_TBIT4;
+ volatile uint32_t PCS_TX_DIG_TBIT5;
+ volatile uint32_t PCS_TX_DIG_TBIT6;
+ volatile uint32_t PCS_TX_DIG_TBIT7;
+ volatile uint32_t PCS_TX_DIG_TBIT8;
+ volatile uint32_t PCS_TX_DIG_TBIT9;
+ volatile uint32_t PCS_TX_DIG_TBIT10;
+ volatile uint8_t Resv_3072[212];
+ volatile uint32_t ISO_PHY_ISO_CNTRL;
+ volatile uint32_t ISO_PHY_ISO_RESET;
+ volatile uint32_t ISO_PHY_ISO_ENABLE;
+ volatile uint32_t ISO_PHY_ISO_CMN_CTRL;
+ volatile uint32_t ISO_PHY_ISO_CMN_PLL;
+ volatile uint32_t ISO_PHY_ISO_CL_CNTRL_L;
+ volatile uint32_t ISO_PHY_ISO_DL_CTRL_L0;
+ volatile uint32_t ISO_PHY_ISO_DL_HS_L0;
+ volatile uint32_t ISO_PHY_ISO_DL_TX_ESC_L0;
+ volatile uint32_t ISO_PHY_ISO_DL_RX_ESC_L0;
+ volatile uint32_t ISO_PHY_ISO_DL_CTRL_L1;
+ volatile uint32_t ISO_PHY_ISO_DL_HS_L1;
+ volatile uint32_t ISO_PHY_ISO_DL_TX_ESC_L1;
+ volatile uint32_t ISO_PHY_ISO_DL_RX_ESC_L1;
+ volatile uint32_t ISO_PHY_ISO_SPARE_1;
+ volatile uint32_t ISO_PHY_ISO_SPARE_2;
+ volatile uint32_t ISO_LDD_PHY_ISO_DL_CTRL_L2;
+ volatile uint32_t ISO_LDD_PHY_ISO_DL_HS_L2;
+ volatile uint32_t ISO_LDD_PHY_ISO_DL_TX_ESC_L2;
+ volatile uint32_t ISO_LDD_PHY_ISO_DL_RX_ESC_L2;
+ volatile uint32_t ISO_LDD_PHY_ISO_DL_CTRL_L3;
+ volatile uint32_t ISO_LDD_PHY_ISO_DL_HS_L3;
+ volatile uint32_t ISO_LDD_PHY_ISO_DL_TX_ESC_L3;
+ volatile uint32_t ISO_LDD_PHY_ISO_DL_RX_ESC_L3;
+} CSL_wiz16b8m4cdtRegs_DPHYTX;
+
+
+typedef struct {
+ volatile uint32_t MOD_VER; /* Module and Version */
+ volatile uint32_t PLL_CTRL; /* PLL Control */
+ volatile uint32_t STATUS; /* Status Register */
+ volatile uint32_t RST_CTRL; /* RST Control */
+ volatile uint32_t PSM_FREQ; /* PSM Frequency */
+ volatile uint32_t IPCONFIG; /* IP Config */
+ volatile uint8_t Resv_248[224];
+ volatile uint32_t PLLRES; /* PLL Reserved */
+ volatile uint32_t DIAG_TEST; /* Diagnostic Test Register */
+} CSL_wiz16b8m4cdtRegs_WIZ_CONFIG;
+
+
+typedef struct {
+ CSL_wiz16b8m4cdtRegs_DPHYTX DPHYTX;
+ volatile uint8_t Resv_3840[672];
+ CSL_wiz16b8m4cdtRegs_WIZ_CONFIG WIZ_CONFIG;
+} CSL_wiz16b8m4cdtRegs;
+
+
+/**************************************************************************
+* Register Macros
+**************************************************************************/
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_ANA_TBIT0 (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_ANA_TBIT1 (0x00000004U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_ANA_TBIT2 (0x00000008U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_ANA_TBIT3 (0x0000000CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_ANA_TBIT4 (0x00000010U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_ANA_TBIT5 (0x00000014U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT0 (0x00000018U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT1 (0x0000001CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT2 (0x00000020U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT3 (0x00000024U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT4 (0x00000028U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT5 (0x0000002CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT6 (0x00000030U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT7 (0x00000034U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT8 (0x00000038U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT9 (0x0000003CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT10 (0x00000040U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT11 (0x00000044U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT12 (0x00000048U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT13 (0x0000004CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT14 (0x00000050U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT20 (0x00000068U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT21 (0x0000006CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT22 (0x00000070U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT23 (0x00000074U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT24 (0x00000078U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT25 (0x0000007CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT26 (0x00000080U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT27 (0x00000084U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT28 (0x00000088U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT31 (0x00000094U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT32 (0x00000098U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT33 (0x0000009CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT34 (0x000000A0U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT35 (0x000000A4U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT36 (0x000000A8U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT37 (0x000000ACU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT39 (0x000000B4U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT50 (0x000000D8U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT53 (0x000000E4U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT54 (0x000000E8U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT56 (0x000000F0U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT58 (0x000000F8U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_ANA_TBIT0 (0x00000100U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_ANA_TBIT1 (0x00000104U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_ANA_TBIT2 (0x00000108U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_ANA_TBIT3 (0x0000010CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_ANA_TBIT4 (0x00000110U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT0 (0x0000011CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT1 (0x00000120U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT2 (0x00000124U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT8 (0x0000013CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT9 (0x00000140U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT10 (0x00000144U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT14 (0x00000154U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT15 (0x00000158U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT16 (0x0000015CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT17 (0x00000160U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT18 (0x00000164U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT19 (0x00000168U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT20 (0x0000016CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_ANA_TBIT5 (0x00000170U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT21 (0x0000017CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT22 (0x00000180U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT24 (0x00000188U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT25 (0x0000018CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT26 (0x00000190U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT27 (0x00000194U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT28 (0x00000198U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT29 (0x0000019CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_ANA_TBIT0 (0x00000200U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_ANA_TBIT1 (0x00000204U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_ANA_TBIT2 (0x00000208U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_ANA_TBIT3 (0x0000020CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_ANA_TBIT4 (0x00000210U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT0 (0x0000021CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT1 (0x00000220U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT2 (0x00000224U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT3 (0x00000228U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT4 (0x0000022CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT5 (0x00000230U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT6 (0x00000234U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT7 (0x00000238U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT8 (0x0000023CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT9 (0x00000240U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT10 (0x00000244U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT11 (0x00000248U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT12 (0x0000024CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT13 (0x00000250U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT14 (0x00000254U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT15 (0x00000258U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT16 (0x0000025CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT17 (0x00000260U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT18 (0x00000264U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT19 (0x00000268U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT20 (0x0000026CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT21 (0x00000270U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT22 (0x00000274U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT23 (0x00000278U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT24 (0x0000027CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_ANA_TBIT5 (0x00000280U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT25 (0x0000028CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT26 (0x00000290U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT28 (0x00000298U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT29 (0x0000029CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT30 (0x000002A0U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT31 (0x000002A4U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT32 (0x000002A8U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT33 (0x000002ACU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT34 (0x000002B0U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT35 (0x000002B4U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT36 (0x000002B8U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_ANA_TBIT0 (0x00000300U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_ANA_TBIT1 (0x00000304U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_ANA_TBIT2 (0x00000308U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_ANA_TBIT3 (0x0000030CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_ANA_TBIT4 (0x00000310U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT0 (0x0000031CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT1 (0x00000320U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT2 (0x00000324U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT3 (0x00000328U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT4 (0x0000032CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT5 (0x00000330U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT6 (0x00000334U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT7 (0x00000338U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT8 (0x0000033CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT9 (0x00000340U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT10 (0x00000344U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT11 (0x00000348U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT12 (0x0000034CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT13 (0x00000350U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT14 (0x00000354U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT15 (0x00000358U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT16 (0x0000035CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT17 (0x00000360U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT18 (0x00000364U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT19 (0x00000368U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT20 (0x0000036CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT21 (0x00000370U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT22 (0x00000374U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT23 (0x00000378U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT24 (0x0000037CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_ANA_TBIT5 (0x00000380U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT25 (0x0000038CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT26 (0x00000390U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT28 (0x00000398U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT29 (0x0000039CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT30 (0x000003A0U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT31 (0x000003A4U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT32 (0x000003A8U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT33 (0x000003ACU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT34 (0x000003B0U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT35 (0x000003B4U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT36 (0x000003B8U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_ANA_TBIT0 (0x00000400U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_ANA_TBIT1 (0x00000404U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_ANA_TBIT2 (0x00000408U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_ANA_TBIT3 (0x0000040CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_ANA_TBIT4 (0x00000410U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT0 (0x0000041CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT1 (0x00000420U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT2 (0x00000424U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT3 (0x00000428U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT4 (0x0000042CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT5 (0x00000430U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT6 (0x00000434U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT7 (0x00000438U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT8 (0x0000043CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT9 (0x00000440U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT10 (0x00000444U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT11 (0x00000448U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT12 (0x0000044CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT13 (0x00000450U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT14 (0x00000454U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT15 (0x00000458U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT16 (0x0000045CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT17 (0x00000460U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT18 (0x00000464U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT19 (0x00000468U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT20 (0x0000046CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT21 (0x00000470U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT22 (0x00000474U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT23 (0x00000478U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT24 (0x0000047CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_ANA_TBIT5 (0x00000480U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT25 (0x0000048CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT26 (0x00000490U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT28 (0x00000498U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT29 (0x0000049CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT30 (0x000004A0U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT31 (0x000004A4U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT32 (0x000004A8U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT33 (0x000004ACU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT34 (0x000004B0U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT35 (0x000004B4U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT36 (0x000004B8U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_ANA_TBIT0 (0x00000500U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_ANA_TBIT1 (0x00000504U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_ANA_TBIT2 (0x00000508U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_ANA_TBIT3 (0x0000050CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_ANA_TBIT4 (0x00000510U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT0 (0x0000051CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT1 (0x00000520U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT2 (0x00000524U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT3 (0x00000528U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT4 (0x0000052CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT5 (0x00000530U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT6 (0x00000534U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT7 (0x00000538U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT8 (0x0000053CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT9 (0x00000540U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT10 (0x00000544U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT11 (0x00000548U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT12 (0x0000054CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT13 (0x00000550U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT14 (0x00000554U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT15 (0x00000558U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT16 (0x0000055CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT17 (0x00000560U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT18 (0x00000564U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT19 (0x00000568U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT20 (0x0000056CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT21 (0x00000570U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT22 (0x00000574U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT23 (0x00000578U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT24 (0x0000057CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_ANA_TBIT5 (0x00000580U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT25 (0x0000058CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT26 (0x00000590U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT28 (0x00000598U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT29 (0x0000059CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT30 (0x000005A0U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT31 (0x000005A4U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT32 (0x000005A8U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT33 (0x000005ACU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT34 (0x000005B0U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT35 (0x000005B4U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT36 (0x000005B8U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT0 (0x00000B00U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT1 (0x00000B04U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT2 (0x00000B08U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT3 (0x00000B0CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT4 (0x00000B10U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT5 (0x00000B14U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT6 (0x00000B18U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT7 (0x00000B1CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT8 (0x00000B20U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT9 (0x00000B24U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT10 (0x00000B28U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_CNTRL (0x00000C00U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_RESET (0x00000C04U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_ENABLE (0x00000C08U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_CMN_CTRL (0x00000C0CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_CMN_PLL (0x00000C10U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_CL_CNTRL_L (0x00000C14U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_CTRL_L0 (0x00000C18U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_HS_L0 (0x00000C1CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L0 (0x00000C20U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_RX_ESC_L0 (0x00000C24U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_CTRL_L1 (0x00000C28U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_HS_L1 (0x00000C2CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L1 (0x00000C30U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_RX_ESC_L1 (0x00000C34U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_SPARE_1 (0x00000C38U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_SPARE_2 (0x00000C3CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_CTRL_L2 (0x00000C40U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_HS_L2 (0x00000C44U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L2 (0x00000C48U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_RX_ESC_L2 (0x00000C4CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_CTRL_L3 (0x00000C50U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_HS_L3 (0x00000C54U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L3 (0x00000C58U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_RX_ESC_L3 (0x00000C5CU)
+#define CSL_WIZ16B8M4CDT_WIZ_CONFIG_MOD_VER (0x00000F00U)
+#define CSL_WIZ16B8M4CDT_WIZ_CONFIG_PLL_CTRL (0x00000F04U)
+#define CSL_WIZ16B8M4CDT_WIZ_CONFIG_STATUS (0x00000F08U)
+#define CSL_WIZ16B8M4CDT_WIZ_CONFIG_RST_CTRL (0x00000F0CU)
+#define CSL_WIZ16B8M4CDT_WIZ_CONFIG_PSM_FREQ (0x00000F10U)
+#define CSL_WIZ16B8M4CDT_WIZ_CONFIG_IPCONFIG (0x00000F14U)
+#define CSL_WIZ16B8M4CDT_WIZ_CONFIG_PLLRES (0x00000FF8U)
+#define CSL_WIZ16B8M4CDT_WIZ_CONFIG_DIAG_TEST (0x00000FFCU)
+
+/**************************************************************************
+* Field Definition Macros
+**************************************************************************/
+
+
+/* CMN0_CMN_ANA_TBIT0 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_ANA_TBIT0_CMN0_ANA_TBIT0_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_ANA_TBIT0_CMN0_ANA_TBIT0_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_ANA_TBIT0_CMN0_ANA_TBIT0_MAX (0xFFFFFFFFU)
+
+/* CMN0_CMN_ANA_TBIT1 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_ANA_TBIT1_CMN0_ANA_TBIT1_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_ANA_TBIT1_CMN0_ANA_TBIT1_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_ANA_TBIT1_CMN0_ANA_TBIT1_MAX (0xFFFFFFFFU)
+
+/* CMN0_CMN_ANA_TBIT2 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_ANA_TBIT2_CMN0_ANA_TBIT2_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_ANA_TBIT2_CMN0_ANA_TBIT2_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_ANA_TBIT2_CMN0_ANA_TBIT2_MAX (0xFFFFFFFFU)
+
+/* CMN0_CMN_ANA_TBIT3 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_ANA_TBIT3_CMN0_ANA_TBIT3_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_ANA_TBIT3_CMN0_ANA_TBIT3_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_ANA_TBIT3_CMN0_ANA_TBIT3_MAX (0xFFFFFFFFU)
+
+/* CMN0_CMN_ANA_TBIT4 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_ANA_TBIT4_CMN0_ANA_TBIT4_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_ANA_TBIT4_CMN0_ANA_TBIT4_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_ANA_TBIT4_CMN0_ANA_TBIT4_MAX (0xFFFFFFFFU)
+
+/* CMN0_CMN_ANA_TBIT5 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_ANA_TBIT5_CMN0_ANA_TBIT5_MASK (0x000000FFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_ANA_TBIT5_CMN0_ANA_TBIT5_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_ANA_TBIT5_CMN0_ANA_TBIT5_MAX (0x000000FFU)
+
+/* CMN0_CMN_DIG_TBIT0 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT0_CMN0_O_RES_CAL_START_TM_MASK (0x10000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT0_CMN0_O_RES_CAL_START_TM_SHIFT (0x0000001CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT0_CMN0_O_RES_CAL_START_TM_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT0_CMN0_O_RES_CAL_START_TM_SEL_MASK (0x08000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT0_CMN0_O_RES_CAL_START_TM_SEL_SHIFT (0x0000001BU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT0_CMN0_O_RES_CAL_START_TM_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT0_CMN0_O_RES_COMP_OUT_POL_INV_TM_MASK (0x04000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT0_CMN0_O_RES_COMP_OUT_POL_INV_TM_SHIFT (0x0000001AU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT0_CMN0_O_RES_COMP_OUT_POL_INV_TM_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT0_CMN0_O_RES_TX_OFFSET_TEST_LOW_TM_MASK (0x03C00000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT0_CMN0_O_RES_TX_OFFSET_TEST_LOW_TM_SHIFT (0x00000016U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT0_CMN0_O_RES_TX_OFFSET_TEST_LOW_TM_MAX (0x0000000FU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT0_CMN0_O_RES_TX_OFFSET_LOW_DEC_TM_MASK (0x00200000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT0_CMN0_O_RES_TX_OFFSET_LOW_DEC_TM_SHIFT (0x00000015U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT0_CMN0_O_RES_TX_OFFSET_LOW_DEC_TM_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT0_CMN0_O_RES_TX_OFFSET_LOW_TM_SEL_MASK (0x00100000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT0_CMN0_O_RES_TX_OFFSET_LOW_TM_SEL_SHIFT (0x00000014U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT0_CMN0_O_RES_TX_OFFSET_LOW_TM_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT0_CMN0_O_RES_TX_OFFSET_TEST_HIGH_TM_MASK (0x000F0000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT0_CMN0_O_RES_TX_OFFSET_TEST_HIGH_TM_SHIFT (0x00000010U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT0_CMN0_O_RES_TX_OFFSET_TEST_HIGH_TM_MAX (0x0000000FU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT0_CMN0_O_RES_TX_OFFSET_HIGH_DEC_TM_MASK (0x00008000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT0_CMN0_O_RES_TX_OFFSET_HIGH_DEC_TM_SHIFT (0x0000000FU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT0_CMN0_O_RES_TX_OFFSET_HIGH_DEC_TM_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT0_CMN0_O_RES_TX_OFFSET_HIGH_TM_SEL_MASK (0x00004000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT0_CMN0_O_RES_TX_OFFSET_HIGH_TM_SEL_SHIFT (0x0000000EU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT0_CMN0_O_RES_TX_OFFSET_HIGH_TM_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT0_CMN0_O_RES_CALIB_DECISION_WAIT_TM_MASK (0x00003C00U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT0_CMN0_O_RES_CALIB_DECISION_WAIT_TM_SHIFT (0x0000000AU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT0_CMN0_O_RES_CALIB_DECISION_WAIT_TM_MAX (0x0000000FU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT0_CMN0_O_RES_CALIB_INIT_WAIT_TM_MASK (0x000003C0U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT0_CMN0_O_RES_CALIB_INIT_WAIT_TM_SHIFT (0x00000006U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT0_CMN0_O_RES_CALIB_INIT_WAIT_TM_MAX (0x0000000FU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT0_CMN0_O_RES_CALIB_RSTB_TM_MASK (0x00000020U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT0_CMN0_O_RES_CALIB_RSTB_TM_SHIFT (0x00000005U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT0_CMN0_O_RES_CALIB_RSTB_TM_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT0_CMN0_O_RES_CALIB_RSTB_TM_SEL_MASK (0x00000010U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT0_CMN0_O_RES_CALIB_RSTB_TM_SEL_SHIFT (0x00000004U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT0_CMN0_O_RES_CALIB_RSTB_TM_SEL_MAX (0x00000001U)
+
+/* CMN0_CMN_DIG_TBIT1 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT1_CMN0_O_ATB_EN_MASK (0x80000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT1_CMN0_O_ATB_EN_SHIFT (0x0000001FU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT1_CMN0_O_ATB_EN_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT1_CMN0_O_ATB_SRC_MASK (0x40000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT1_CMN0_O_ATB_SRC_SHIFT (0x0000001EU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT1_CMN0_O_ATB_SRC_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT1_CMN0_BF_29_17_MASK (0x3FFE0000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT1_CMN0_BF_29_17_SHIFT (0x00000011U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT1_CMN0_BF_29_17_MAX (0x00001FFFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT1_CMN0_O_ANA_PLL_ATB_CP_CUR_SEL_MASK (0x00010000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT1_CMN0_O_ANA_PLL_ATB_CP_CUR_SEL_SHIFT (0x00000010U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT1_CMN0_O_ANA_PLL_ATB_CP_CUR_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT1_CMN0_O_ANA_PLL_ATBH_GM_CUR_SEL_MASK (0x00008000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT1_CMN0_O_ANA_PLL_ATBH_GM_CUR_SEL_SHIFT (0x0000000FU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT1_CMN0_O_ANA_PLL_ATBH_GM_CUR_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT1_CMN0_O_ANA_BG_PD_TM_MASK (0x00000200U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT1_CMN0_O_ANA_BG_PD_TM_SHIFT (0x00000009U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT1_CMN0_O_ANA_BG_PD_TM_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT1_CMN0_O_ANA_BG_PD_TM_SEL_MASK (0x00000100U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT1_CMN0_O_ANA_BG_PD_TM_SEL_SHIFT (0x00000008U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT1_CMN0_O_ANA_BG_PD_TM_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT1_CMN0_O_ANA_RES_CALIB_PD_TM_MASK (0x00000080U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT1_CMN0_O_ANA_RES_CALIB_PD_TM_SHIFT (0x00000007U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT1_CMN0_O_ANA_RES_CALIB_PD_TM_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT1_CMN0_O_ANA_RES_CALIB_PD_TM_SEL_MASK (0x00000040U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT1_CMN0_O_ANA_RES_CALIB_PD_TM_SEL_SHIFT (0x00000006U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT1_CMN0_O_ANA_RES_CALIB_PD_TM_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT1_CMN0_O_ANA_RES_CALIB_CODE_TM_MASK (0x0000003EU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT1_CMN0_O_ANA_RES_CALIB_CODE_TM_SHIFT (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT1_CMN0_O_ANA_RES_CALIB_CODE_TM_MAX (0x0000001FU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT1_CMN0_O_ANA_RES_CALIB_CODE_TM_SEL_MASK (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT1_CMN0_O_ANA_RES_CALIB_CODE_TM_SEL_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT1_CMN0_O_ANA_RES_CALIB_CODE_TM_SEL_MAX (0x00000001U)
+
+/* CMN0_CMN_DIG_TBIT2 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT2_CMN0_O_CMN_RX_MODE_EN_MASK (0x00000400U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT2_CMN0_O_CMN_RX_MODE_EN_SHIFT (0x0000000AU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT2_CMN0_O_CMN_RX_MODE_EN_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT2_CMN0_O_CMN_TX_MODE_EN_MASK (0x00000200U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT2_CMN0_O_CMN_TX_MODE_EN_SHIFT (0x00000009U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT2_CMN0_O_CMN_TX_MODE_EN_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT2_CMN0_O_SSM_WAIT_BGCAL_EN_MASK (0x000001FEU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT2_CMN0_O_SSM_WAIT_BGCAL_EN_SHIFT (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT2_CMN0_O_SSM_WAIT_BGCAL_EN_MAX (0x000000FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT2_CMN0_O_CMN_SSM_EN_MASK (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT2_CMN0_O_CMN_SSM_EN_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT2_CMN0_O_CMN_SSM_EN_MAX (0x00000001U)
+
+/* CMN0_CMN_DIG_TBIT3 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT3_CMN0_O_PLL_WAIT_PLL_ACCINV_MASK (0xFF000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT3_CMN0_O_PLL_WAIT_PLL_ACCINV_SHIFT (0x00000018U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT3_CMN0_O_PLL_WAIT_PLL_ACCINV_MAX (0x000000FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT3_CMN0_O_PLL_WAIT_PLL_BIAS_MASK (0x00FF0000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT3_CMN0_O_PLL_WAIT_PLL_BIAS_SHIFT (0x00000010U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT3_CMN0_O_PLL_WAIT_PLL_BIAS_MAX (0x000000FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT3_CMN0_O_PLL_WAIT_PLL_EN_DEL_MASK (0x0000FF00U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT3_CMN0_O_PLL_WAIT_PLL_EN_DEL_SHIFT (0x00000008U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT3_CMN0_O_PLL_WAIT_PLL_EN_DEL_MAX (0x000000FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT3_CMN0_O_PLL_WAIT_PLL_EN_MASK (0x000000FFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT3_CMN0_O_PLL_WAIT_PLL_EN_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT3_CMN0_O_PLL_WAIT_PLL_EN_MAX (0x000000FFU)
+
+/* CMN0_CMN_DIG_TBIT4 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT4_CMN0_O_PLL_WAIT_PLL_LOCK_DET_WAIT_MASK (0x0FFF0000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT4_CMN0_O_PLL_WAIT_PLL_LOCK_DET_WAIT_SHIFT (0x00000010U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT4_CMN0_O_PLL_WAIT_PLL_LOCK_DET_WAIT_MAX (0x00000FFFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT4_CMN0_O_PLL_WAIT_PLL_RST_DEASSERT_2_MASK (0x0000FF00U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT4_CMN0_O_PLL_WAIT_PLL_RST_DEASSERT_2_SHIFT (0x00000008U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT4_CMN0_O_PLL_WAIT_PLL_RST_DEASSERT_2_MAX (0x000000FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT4_CMN0_O_PLL_WAIT_PLL_RST_DEASSERT_MASK (0x000000FFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT4_CMN0_O_PLL_WAIT_PLL_RST_DEASSERT_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT4_CMN0_O_PLL_WAIT_PLL_RST_DEASSERT_MAX (0x000000FFU)
+
+/* CMN0_CMN_DIG_TBIT5 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT5_CMN0_O_CMN_TX_READY_TM_SEL_MASK (0xC0000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT5_CMN0_O_CMN_TX_READY_TM_SEL_SHIFT (0x0000001EU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT5_CMN0_O_CMN_TX_READY_TM_SEL_MAX (0x00000003U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT5_CMN0_O_PLL_PROCEED_WITH_LOCK_FAIL_TM_MASK (0x20000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT5_CMN0_O_PLL_PROCEED_WITH_LOCK_FAIL_TM_SHIFT (0x0000001DU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT5_CMN0_O_PLL_PROCEED_WITH_LOCK_FAIL_TM_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT5_CMN0_O_PLL_LOCKED_TM_MASK (0x10000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT5_CMN0_O_PLL_LOCKED_TM_SHIFT (0x0000001CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT5_CMN0_O_PLL_LOCKED_TM_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT5_CMN0_O_PLL_LOCKED_TM_SEL_MASK (0x08000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT5_CMN0_O_PLL_LOCKED_TM_SEL_SHIFT (0x0000001BU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT5_CMN0_O_PLL_LOCKED_TM_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT5_CMN0_O_PLL_LOCK_DET_EN_TM_MASK (0x04000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT5_CMN0_O_PLL_LOCK_DET_EN_TM_SHIFT (0x0000001AU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT5_CMN0_O_PLL_LOCK_DET_EN_TM_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT5_CMN0_O_PLL_LOCK_DET_EN_TM_SEL_MASK (0x02000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT5_CMN0_O_PLL_LOCK_DET_EN_TM_SEL_SHIFT (0x00000019U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT5_CMN0_O_PLL_LOCK_DET_EN_TM_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT5_CMN0_O_PLL_WAIT_PLL_LOCK_TIMEOUT_MASK (0x0003FFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT5_CMN0_O_PLL_WAIT_PLL_LOCK_TIMEOUT_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT5_CMN0_O_PLL_WAIT_PLL_LOCK_TIMEOUT_MAX (0x0003FFFFU)
+
+/* CMN0_CMN_DIG_TBIT6 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT6_CMN0_O_LOCKDET_REFCNT_IDLE_VALUE_MASK (0xFFFF0000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT6_CMN0_O_LOCKDET_REFCNT_IDLE_VALUE_SHIFT (0x00000010U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT6_CMN0_O_LOCKDET_REFCNT_IDLE_VALUE_MAX (0x0000FFFFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT6_CMN0_O_LOCKDET_REFCNT_START_VALUE_MASK (0x0000FFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT6_CMN0_O_LOCKDET_REFCNT_START_VALUE_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT6_CMN0_O_LOCKDET_REFCNT_START_VALUE_MAX (0x0000FFFFU)
+
+/* CMN0_CMN_DIG_TBIT7 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT7_CMN0_O_LOCKDET_PLLCNT_LOCK_THR_VALUE_MASK (0xFFFF0000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT7_CMN0_O_LOCKDET_PLLCNT_LOCK_THR_VALUE_SHIFT (0x00000010U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT7_CMN0_O_LOCKDET_PLLCNT_LOCK_THR_VALUE_MAX (0x0000FFFFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT7_CMN0_O_LOCKDET_PLLCNT_START_VALUE_MASK (0x0000FFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT7_CMN0_O_LOCKDET_PLLCNT_START_VALUE_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT7_CMN0_O_LOCKDET_PLLCNT_START_VALUE_MAX (0x0000FFFFU)
+
+/* CMN0_CMN_DIG_TBIT8 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT8_CMN0_O_ANA_PLL_VRESET_VCTRL_TUNE_MASK (0xFF000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT8_CMN0_O_ANA_PLL_VRESET_VCTRL_TUNE_SHIFT (0x00000018U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT8_CMN0_O_ANA_PLL_VRESET_VCTRL_TUNE_MAX (0x000000FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT8_CMN0_O_ANA_PLL_VRESET_VCO_BIAS_TUNE_MASK (0x00FF0000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT8_CMN0_O_ANA_PLL_VRESET_VCO_BIAS_TUNE_SHIFT (0x00000010U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT8_CMN0_O_ANA_PLL_VRESET_VCO_BIAS_TUNE_MAX (0x000000FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT8_CMN0_O_ANA_PLL_GM_TUNE_MASK (0x0000FF00U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT8_CMN0_O_ANA_PLL_GM_TUNE_SHIFT (0x00000008U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT8_CMN0_O_ANA_PLL_GM_TUNE_MAX (0x000000FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT8_CMN0_O_ANA_PLL_CP_TUNE_MASK (0x000000FFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT8_CMN0_O_ANA_PLL_CP_TUNE_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT8_CMN0_O_ANA_PLL_CP_TUNE_MAX (0x000000FFU)
+
+/* CMN0_CMN_DIG_TBIT9 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT9_CMN0_O_ANA_PLL_VREF_VCO_BIAS_TUNE_MASK (0xFF000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT9_CMN0_O_ANA_PLL_VREF_VCO_BIAS_TUNE_SHIFT (0x00000018U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT9_CMN0_O_ANA_PLL_VREF_VCO_BIAS_TUNE_MAX (0x000000FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT9_CMN0_O_ANA_PLL_VCO_BIAS_TUNE_MASK (0x00FF0000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT9_CMN0_O_ANA_PLL_VCO_BIAS_TUNE_SHIFT (0x00000010U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT9_CMN0_O_ANA_PLL_VCO_BIAS_TUNE_MAX (0x000000FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT9_CMN0_O_ANA_PLL_GMBYC_CAP_TUNE_MASK (0x0000FF00U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT9_CMN0_O_ANA_PLL_GMBYC_CAP_TUNE_SHIFT (0x00000008U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT9_CMN0_O_ANA_PLL_GMBYC_CAP_TUNE_MAX (0x000000FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT9_CMN0_O_ANA_PLL_LOOP_FILTER_TUNE_MASK (0x000000FFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT9_CMN0_O_ANA_PLL_LOOP_FILTER_TUNE_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT9_CMN0_O_ANA_PLL_LOOP_FILTER_TUNE_MAX (0x000000FFU)
+
+/* CMN0_CMN_DIG_TBIT10 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT10_CMN0_O_ANA_PLL_BYTECLK_DIV_MASK (0x0FF00000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT10_CMN0_O_ANA_PLL_BYTECLK_DIV_SHIFT (0x00000014U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT10_CMN0_O_ANA_PLL_BYTECLK_DIV_MAX (0x000000FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT10_CMN0_O_ANA_PLL_GM_PWM_DIV_LOW_MASK (0x000FFC00U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT10_CMN0_O_ANA_PLL_GM_PWM_DIV_LOW_SHIFT (0x0000000AU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT10_CMN0_O_ANA_PLL_GM_PWM_DIV_LOW_MAX (0x000003FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT10_CMN0_O_ANA_PLL_GM_PWM_DIV_HIGH_MASK (0x000003FFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT10_CMN0_O_ANA_PLL_GM_PWM_DIV_HIGH_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT10_CMN0_O_ANA_PLL_GM_PWM_DIV_HIGH_MAX (0x000003FFU)
+
+/* CMN0_CMN_DIG_TBIT11 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT11_CMN0_O_ANA_PLL_CYA_MASK (0xFFFF0000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT11_CMN0_O_ANA_PLL_CYA_SHIFT (0x00000010U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT11_CMN0_O_ANA_PLL_CYA_MAX (0x0000FFFFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT11_CMN0_O_ANA_PLL_PFD_EN_1U_DEL_TM_SEL_MASK (0x00001000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT11_CMN0_O_ANA_PLL_PFD_EN_1U_DEL_TM_SEL_SHIFT (0x0000000CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT11_CMN0_O_ANA_PLL_PFD_EN_1U_DEL_TM_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT11_CMN0_O_ANA_PLL_VRESET_VCO_BIAS_SEL_MASK (0x00000800U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT11_CMN0_O_ANA_PLL_VRESET_VCO_BIAS_SEL_SHIFT (0x0000000BU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT11_CMN0_O_ANA_PLL_VRESET_VCO_BIAS_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT11_CMN0_O_ANA_PLL_VRESET_VCTRL_SEL_MASK (0x00000400U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT11_CMN0_O_ANA_PLL_VRESET_VCTRL_SEL_SHIFT (0x0000000AU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT11_CMN0_O_ANA_PLL_VRESET_VCTRL_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT11_CMN0_O_ANA_PLL_SEL_FBCLK_GM_PWM_MASK (0x00000200U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT11_CMN0_O_ANA_PLL_SEL_FBCLK_GM_PWM_SHIFT (0x00000009U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT11_CMN0_O_ANA_PLL_SEL_FBCLK_GM_PWM_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT11_CMN0_O_ANA_PLL_OP_BY2_BYPASS_MASK (0x00000100U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT11_CMN0_O_ANA_PLL_OP_BY2_BYPASS_SHIFT (0x00000008U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT11_CMN0_O_ANA_PLL_OP_BY2_BYPASS_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT11_CMN0_O_ANA_PLL_BYPASS_MASK (0x00000080U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT11_CMN0_O_ANA_PLL_BYPASS_SHIFT (0x00000007U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT11_CMN0_O_ANA_PLL_BYPASS_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT11_CMN0_O_ANA_PLL_FBDIV_CLKINBY2_EN_MASK (0x00000040U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT11_CMN0_O_ANA_PLL_FBDIV_CLKINBY2_EN_SHIFT (0x00000006U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT11_CMN0_O_ANA_PLL_FBDIV_CLKINBY2_EN_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT11_CMN0_O_ANA_PLL_DSM_CLK_EN_MASK (0x00000020U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT11_CMN0_O_ANA_PLL_DSM_CLK_EN_SHIFT (0x00000005U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT11_CMN0_O_ANA_PLL_DSM_CLK_EN_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT11_CMN0_O_ANA_PLL_GM_PWM_EN_MASK (0x00000010U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT11_CMN0_O_ANA_PLL_GM_PWM_EN_SHIFT (0x00000004U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT11_CMN0_O_ANA_PLL_GM_PWM_EN_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT11_CMN0_O_ANA_PLL_OP_DIV_CLK_EN_MASK (0x00000008U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT11_CMN0_O_ANA_PLL_OP_DIV_CLK_EN_SHIFT (0x00000003U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT11_CMN0_O_ANA_PLL_OP_DIV_CLK_EN_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT11_CMN0_O_ANA_PLL_IP_DIV_CLK_EN_MASK (0x00000004U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT11_CMN0_O_ANA_PLL_IP_DIV_CLK_EN_SHIFT (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT11_CMN0_O_ANA_PLL_IP_DIV_CLK_EN_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT11_CMN0_O_ANA_PLL_REF_CLK_EN_MASK (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT11_CMN0_O_ANA_PLL_REF_CLK_EN_SHIFT (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT11_CMN0_O_ANA_PLL_REF_CLK_EN_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT11_CMN0_O_ANA_PLL_FB_DIV_CLK_EN_MASK (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT11_CMN0_O_ANA_PLL_FB_DIV_CLK_EN_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT11_CMN0_O_ANA_PLL_FB_DIV_CLK_EN_MAX (0x00000001U)
+
+/* CMN0_CMN_DIG_TBIT12 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT12_CMN0_O_ANA_PLL_VRESET_GEN_EN_TM_MASK (0x80000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT12_CMN0_O_ANA_PLL_VRESET_GEN_EN_TM_SHIFT (0x0000001FU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT12_CMN0_O_ANA_PLL_VRESET_GEN_EN_TM_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT12_CMN0_O_ANA_PLL_VRESET_GEN_EN_TM_SEL_MASK (0x40000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT12_CMN0_O_ANA_PLL_VRESET_GEN_EN_TM_SEL_SHIFT (0x0000001EU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT12_CMN0_O_ANA_PLL_VRESET_GEN_EN_TM_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT12_CMN0_O_ANA_PLL_PFD_EN_TM_MASK (0x20000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT12_CMN0_O_ANA_PLL_PFD_EN_TM_SHIFT (0x0000001DU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT12_CMN0_O_ANA_PLL_PFD_EN_TM_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT12_CMN0_O_ANA_PLL_PFD_EN_TM_SEL_MASK (0x10000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT12_CMN0_O_ANA_PLL_PFD_EN_TM_SEL_SHIFT (0x0000001CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT12_CMN0_O_ANA_PLL_PFD_EN_TM_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT12_CMN0_O_ANA_PLL_LOOP_FILTER_RESET_N_TM_MASK (0x08000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT12_CMN0_O_ANA_PLL_LOOP_FILTER_RESET_N_TM_SHIFT (0x0000001BU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT12_CMN0_O_ANA_PLL_LOOP_FILTER_RESET_N_TM_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT12_CMN0_O_ANA_PLL_LOOP_FILTER_RESET_N_TM_SEL_MASK (0x04000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT12_CMN0_O_ANA_PLL_LOOP_FILTER_RESET_N_TM_SEL_SHIFT (0x0000001AU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT12_CMN0_O_ANA_PLL_LOOP_FILTER_RESET_N_TM_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT12_CMN0_O_ANA_PLL_GM_RESET_N_TM_MASK (0x02000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT12_CMN0_O_ANA_PLL_GM_RESET_N_TM_SHIFT (0x00000019U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT12_CMN0_O_ANA_PLL_GM_RESET_N_TM_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT12_CMN0_O_ANA_PLL_GM_RESET_N_TM_SEL_MASK (0x01000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT12_CMN0_O_ANA_PLL_GM_RESET_N_TM_SEL_SHIFT (0x00000018U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT12_CMN0_O_ANA_PLL_GM_RESET_N_TM_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT12_CMN0_O_ANA_PLL_GMBYC_CAP_RESET_N_TM_MASK (0x00800000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT12_CMN0_O_ANA_PLL_GMBYC_CAP_RESET_N_TM_SHIFT (0x00000017U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT12_CMN0_O_ANA_PLL_GMBYC_CAP_RESET_N_TM_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT12_CMN0_O_ANA_PLL_GMBYC_CAP_RESET_N_TM_SEL_MASK (0x00400000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT12_CMN0_O_ANA_PLL_GMBYC_CAP_RESET_N_TM_SEL_SHIFT (0x00000016U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT12_CMN0_O_ANA_PLL_GMBYC_CAP_RESET_N_TM_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT12_CMN0_O_ANA_PLL_CP_RESET_N_TM_MASK (0x00200000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT12_CMN0_O_ANA_PLL_CP_RESET_N_TM_SHIFT (0x00000015U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT12_CMN0_O_ANA_PLL_CP_RESET_N_TM_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT12_CMN0_O_ANA_PLL_CP_RESET_N_TM_SEL_MASK (0x00100000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT12_CMN0_O_ANA_PLL_CP_RESET_N_TM_SEL_SHIFT (0x00000014U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT12_CMN0_O_ANA_PLL_CP_RESET_N_TM_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT12_CMN0_O_ANA_PLL_ACCINV_EN_TM_MASK (0x00080000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT12_CMN0_O_ANA_PLL_ACCINV_EN_TM_SHIFT (0x00000013U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT12_CMN0_O_ANA_PLL_ACCINV_EN_TM_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT12_CMN0_O_ANA_PLL_ACCINV_EN_TM_SEL_MASK (0x00040000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT12_CMN0_O_ANA_PLL_ACCINV_EN_TM_SEL_SHIFT (0x00000012U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT12_CMN0_O_ANA_PLL_ACCINV_EN_TM_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT12_CMN0_O_ANA_PLL_BIAS_EN_TM_MASK (0x00020000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT12_CMN0_O_ANA_PLL_BIAS_EN_TM_SHIFT (0x00000011U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT12_CMN0_O_ANA_PLL_BIAS_EN_TM_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT12_CMN0_O_ANA_PLL_BIAS_EN_TM_SEL_MASK (0x00010000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT12_CMN0_O_ANA_PLL_BIAS_EN_TM_SEL_SHIFT (0x00000010U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT12_CMN0_O_ANA_PLL_BIAS_EN_TM_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT12_CMN0_O_ANA_PLLDA_EN_DEL_TM_MASK (0x00008000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT12_CMN0_O_ANA_PLLDA_EN_DEL_TM_SHIFT (0x0000000FU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT12_CMN0_O_ANA_PLLDA_EN_DEL_TM_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT12_CMN0_O_ANA_PLLDA_EN_DEL_TM_SEL_MASK (0x00004000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT12_CMN0_O_ANA_PLLDA_EN_DEL_TM_SEL_SHIFT (0x0000000EU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT12_CMN0_O_ANA_PLLDA_EN_DEL_TM_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT12_CMN0_O_ANA_PLLDA_EN_TM_MASK (0x00002000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT12_CMN0_O_ANA_PLLDA_EN_TM_SHIFT (0x0000000DU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT12_CMN0_O_ANA_PLLDA_EN_TM_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT12_CMN0_O_ANA_PLLDA_EN_TM_SEL_MASK (0x00001000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT12_CMN0_O_ANA_PLLDA_EN_TM_SEL_SHIFT (0x0000000CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT12_CMN0_O_ANA_PLLDA_EN_TM_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT12_CMN0_O_ANA_OP_BY2_DIV_RESET_N_TM_MASK (0x00000800U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT12_CMN0_O_ANA_OP_BY2_DIV_RESET_N_TM_SHIFT (0x0000000BU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT12_CMN0_O_ANA_OP_BY2_DIV_RESET_N_TM_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT12_CMN0_O_ANA_OP_BY2_DIV_RESET_N_TM_SEL_MASK (0x00000400U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT12_CMN0_O_ANA_OP_BY2_DIV_RESET_N_TM_SEL_SHIFT (0x0000000AU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT12_CMN0_O_ANA_OP_BY2_DIV_RESET_N_TM_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT12_CMN0_O_ANA_OP_DIV_RESET_N_TM_MASK (0x00000200U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT12_CMN0_O_ANA_OP_DIV_RESET_N_TM_SHIFT (0x00000009U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT12_CMN0_O_ANA_OP_DIV_RESET_N_TM_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT12_CMN0_O_ANA_OP_DIV_RESET_N_TM_SEL_MASK (0x00000100U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT12_CMN0_O_ANA_OP_DIV_RESET_N_TM_SEL_SHIFT (0x00000008U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT12_CMN0_O_ANA_OP_DIV_RESET_N_TM_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT12_CMN0_O_ANA_IP_DIV_RESET_N_TM_MASK (0x00000080U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT12_CMN0_O_ANA_IP_DIV_RESET_N_TM_SHIFT (0x00000007U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT12_CMN0_O_ANA_IP_DIV_RESET_N_TM_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT12_CMN0_O_ANA_IP_DIV_RESET_N_TM_SEL_MASK (0x00000040U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT12_CMN0_O_ANA_IP_DIV_RESET_N_TM_SEL_SHIFT (0x00000006U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT12_CMN0_O_ANA_IP_DIV_RESET_N_TM_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT12_CMN0_O_ANA_FB_DIV_RESET_N_TM_MASK (0x00000020U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT12_CMN0_O_ANA_FB_DIV_RESET_N_TM_SHIFT (0x00000005U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT12_CMN0_O_ANA_FB_DIV_RESET_N_TM_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT12_CMN0_O_ANA_FB_DIV_RESET_N_TM_SEL_MASK (0x00000010U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT12_CMN0_O_ANA_FB_DIV_RESET_N_TM_SEL_SHIFT (0x00000004U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT12_CMN0_O_ANA_FB_DIV_RESET_N_TM_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT12_CMN0_O_ANA_GM_PWM_DIV_RESET_N_TM_MASK (0x00000008U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT12_CMN0_O_ANA_GM_PWM_DIV_RESET_N_TM_SHIFT (0x00000003U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT12_CMN0_O_ANA_GM_PWM_DIV_RESET_N_TM_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT12_CMN0_O_ANA_GM_PWM_DIV_RESET_N_TM_SEL_MASK (0x00000004U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT12_CMN0_O_ANA_GM_PWM_DIV_RESET_N_TM_SEL_SHIFT (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT12_CMN0_O_ANA_GM_PWM_DIV_RESET_N_TM_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT12_CMN0_O_ANA_BYTECLK_DIV_RESET_N_TM_MASK (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT12_CMN0_O_ANA_BYTECLK_DIV_RESET_N_TM_SHIFT (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT12_CMN0_O_ANA_BYTECLK_DIV_RESET_N_TM_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT12_CMN0_O_ANA_BYTECLK_DIV_RESET_N_TM_SEL_MASK (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT12_CMN0_O_ANA_BYTECLK_DIV_RESET_N_TM_SEL_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT12_CMN0_O_ANA_BYTECLK_DIV_RESET_N_TM_SEL_MAX (0x00000001U)
+
+/* CMN0_CMN_DIG_TBIT13 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT13_CMN0_O_ANA_PLL_FB_DIV_LOW_TM_MASK (0xFFC00000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT13_CMN0_O_ANA_PLL_FB_DIV_LOW_TM_SHIFT (0x00000016U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT13_CMN0_O_ANA_PLL_FB_DIV_LOW_TM_MAX (0x000003FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT13_CMN0_O_ANA_PLL_FB_DIV_LOW_TM_SEL_MASK (0x00200000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT13_CMN0_O_ANA_PLL_FB_DIV_LOW_TM_SEL_SHIFT (0x00000015U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT13_CMN0_O_ANA_PLL_FB_DIV_LOW_TM_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT13_CMN0_O_ANA_PLL_FB_DIV_HIGH_TM_MASK (0x001FF800U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT13_CMN0_O_ANA_PLL_FB_DIV_HIGH_TM_SHIFT (0x0000000BU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT13_CMN0_O_ANA_PLL_FB_DIV_HIGH_TM_MAX (0x000003FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT13_CMN0_O_ANA_PLL_FB_DIV_HIGH_TM_SEL_MASK (0x00000400U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT13_CMN0_O_ANA_PLL_FB_DIV_HIGH_TM_SEL_SHIFT (0x0000000AU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT13_CMN0_O_ANA_PLL_FB_DIV_HIGH_TM_SEL_MAX (0x00000001U)
+
+/* CMN0_CMN_DIG_TBIT14 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT14_CMN0_O_ANA_PLL_OP_DIV_TM_MASK (0x00001F80U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT14_CMN0_O_ANA_PLL_OP_DIV_TM_SHIFT (0x00000007U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT14_CMN0_O_ANA_PLL_OP_DIV_TM_MAX (0x0000003FU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT14_CMN0_O_ANA_PLL_OP_DIV_TM_SEL_MASK (0x00000040U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT14_CMN0_O_ANA_PLL_OP_DIV_TM_SEL_SHIFT (0x00000006U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT14_CMN0_O_ANA_PLL_OP_DIV_TM_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT14_CMN0_O_ANA_PLL_IP_DIV_TM_MASK (0x0000003EU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT14_CMN0_O_ANA_PLL_IP_DIV_TM_SHIFT (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT14_CMN0_O_ANA_PLL_IP_DIV_TM_MAX (0x0000001FU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT14_CMN0_O_ANA_PLL_IP_DIV_TM_SEL_MASK (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT14_CMN0_O_ANA_PLL_IP_DIV_TM_SEL_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT14_CMN0_O_ANA_PLL_IP_DIV_TM_SEL_MAX (0x00000001U)
+
+/* CMN0_CMN_DIG_TBIT20 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT20_CMN0_O_CMSMT_REF_CLK_TMR_VALUE_MASK (0x000FFFF0U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT20_CMN0_O_CMSMT_REF_CLK_TMR_VALUE_SHIFT (0x00000004U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT20_CMN0_O_CMSMT_REF_CLK_TMR_VALUE_MAX (0x0000FFFFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT20_CMN0_BF_3_1_MASK (0x0000000EU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT20_CMN0_BF_3_1_SHIFT (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT20_CMN0_BF_3_1_MAX (0x00000007U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT20_CMN0_O_CMSMT_MEASUREMENT_RUN_MASK (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT20_CMN0_O_CMSMT_MEASUREMENT_RUN_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT20_CMN0_O_CMSMT_MEASUREMENT_RUN_MAX (0x00000001U)
+
+/* CMN0_CMN_DIG_TBIT21 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT21_CMN0_O_CMNDA_HSRX_BIST_CLK_SERSYNTH_SWAPDPDN_MASK (0x00000040U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT21_CMN0_O_CMNDA_HSRX_BIST_CLK_SERSYNTH_SWAPDPDN_SHIFT (0x00000006U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT21_CMN0_O_CMNDA_HSRX_BIST_CLK_SERSYNTH_SWAPDPDN_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT21_CMN0_O_CMNDA_HSRX_BIST_DATA_SERSYNTH_SWAPDPDN_MASK (0x00000020U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT21_CMN0_O_CMNDA_HSRX_BIST_DATA_SERSYNTH_SWAPDPDN_SHIFT (0x00000005U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT21_CMN0_O_CMNDA_HSRX_BIST_DATA_SERSYNTH_SWAPDPDN_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT21_CMN0_O_CMNDA_RX_BIST_EN_DEL_TM_MASK (0x00000010U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT21_CMN0_O_CMNDA_RX_BIST_EN_DEL_TM_SHIFT (0x00000004U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT21_CMN0_O_CMNDA_RX_BIST_EN_DEL_TM_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT21_CMN0_O_CMNDA_RX_BIST_EN_DEL_TM_SEL_MASK (0x00000008U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT21_CMN0_O_CMNDA_RX_BIST_EN_DEL_TM_SEL_SHIFT (0x00000003U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT21_CMN0_O_CMNDA_RX_BIST_EN_DEL_TM_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT21_CMN0_O_CMNDA_RX_BIST_EN_TM_MASK (0x00000004U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT21_CMN0_O_CMNDA_RX_BIST_EN_TM_SHIFT (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT21_CMN0_O_CMNDA_RX_BIST_EN_TM_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT21_CMN0_O_CMNDA_RX_BIST_EN_TM_SEL_MASK (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT21_CMN0_O_CMNDA_RX_BIST_EN_TM_SEL_SHIFT (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT21_CMN0_O_CMNDA_RX_BIST_EN_TM_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT21_CMN0_O_RX_DIG_BIST_EN_MASK (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT21_CMN0_O_RX_DIG_BIST_EN_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT21_CMN0_O_RX_DIG_BIST_EN_MAX (0x00000001U)
+
+/* CMN0_CMN_DIG_TBIT22 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT22_CMN0_TM_SKEW_CAL_SYNC_PKT_SEL_MASK (0x80000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT22_CMN0_TM_SKEW_CAL_SYNC_PKT_SEL_SHIFT (0x0000001FU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT22_CMN0_TM_SKEW_CAL_SYNC_PKT_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT22_CMN0_TM_SKEW_CAL_SYNC_PKT_MASK (0x7F800000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT22_CMN0_TM_SKEW_CAL_SYNC_PKT_SHIFT (0x00000017U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT22_CMN0_TM_SKEW_CAL_SYNC_PKT_MAX (0x000000FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT22_CMN0_TM_HS_SYNC_PKT_SEL_MASK (0x00400000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT22_CMN0_TM_HS_SYNC_PKT_SEL_SHIFT (0x00000016U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT22_CMN0_TM_HS_SYNC_PKT_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT22_CMN0_TM_HS_SYNC_PKT_MASK (0x003FC000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT22_CMN0_TM_HS_SYNC_PKT_SHIFT (0x0000000EU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT22_CMN0_TM_HS_SYNC_PKT_MAX (0x000000FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT22_CMN0_BIST_LENGTH_OF_DESKEW_MASK (0x00003F80U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT22_CMN0_BIST_LENGTH_OF_DESKEW_SHIFT (0x00000007U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT22_CMN0_BIST_LENGTH_OF_DESKEW_MAX (0x0000007FU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT22_CMN0_BIST_SEND_CONFIG_MASK (0x00000060U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT22_CMN0_BIST_SEND_CONFIG_SHIFT (0x00000005U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT22_CMN0_BIST_SEND_CONFIG_MAX (0x00000003U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT22_CMN0_BIST_MODE_ENTRY_WAIT_TIME_MASK (0x0000001EU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT22_CMN0_BIST_MODE_ENTRY_WAIT_TIME_SHIFT (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT22_CMN0_BIST_MODE_ENTRY_WAIT_TIME_MAX (0x0000000FU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT22_CMN0_BIST_CONTROLLER_EN_MASK (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT22_CMN0_BIST_CONTROLLER_EN_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT22_CMN0_BIST_CONTROLLER_EN_MAX (0x00000001U)
+
+/* CMN0_CMN_DIG_TBIT23 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT23_CMN0_TM_TX_DATA_HS_SEL_MASK (0x00800000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT23_CMN0_TM_TX_DATA_HS_SEL_SHIFT (0x00000017U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT23_CMN0_TM_TX_DATA_HS_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT23_CMN0_TM_TX_DATA_HS_MASK (0x007F8000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT23_CMN0_TM_TX_DATA_HS_SHIFT (0x0000000FU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT23_CMN0_TM_TX_DATA_HS_MAX (0x000000FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT23_CMN0_BIST_TM_BAND_CTRL_SEL_MASK (0x00004000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT23_CMN0_BIST_TM_BAND_CTRL_SEL_SHIFT (0x0000000EU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT23_CMN0_BIST_TM_BAND_CTRL_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT23_CMN0_BIST_TM_BAND_CTRL_MASK (0x00003E00U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT23_CMN0_BIST_TM_BAND_CTRL_SHIFT (0x00000009U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT23_CMN0_BIST_TM_BAND_CTRL_MAX (0x0000001FU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT23_CMN0_TM_SKEW_CAL_PATTERN_SEL_MASK (0x00000100U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT23_CMN0_TM_SKEW_CAL_PATTERN_SEL_SHIFT (0x00000008U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT23_CMN0_TM_SKEW_CAL_PATTERN_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT23_CMN0_TM_SKEW_CAL_PATTERN_MASK (0x000000FFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT23_CMN0_TM_SKEW_CAL_PATTERN_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT23_CMN0_TM_SKEW_CAL_PATTERN_MAX (0x000000FFU)
+
+/* CMN0_CMN_DIG_TBIT24 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT24_CMN0_BIST_FRM_IDLE_TIME_MASK (0xFF000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT24_CMN0_BIST_FRM_IDLE_TIME_SHIFT (0x00000018U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT24_CMN0_BIST_FRM_IDLE_TIME_MAX (0x000000FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT24_CMN0_BIST_PKT_NUM_MASK (0x00FF0000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT24_CMN0_BIST_PKT_NUM_SHIFT (0x00000010U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT24_CMN0_BIST_PKT_NUM_MAX (0x000000FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT24_CMN0_BIST_INF_MODE_MASK (0x00008000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT24_CMN0_BIST_INF_MODE_SHIFT (0x0000000FU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT24_CMN0_BIST_INF_MODE_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT24_CMN0_BIST_FRM_NUM_MASK (0x00007F80U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT24_CMN0_BIST_FRM_NUM_SHIFT (0x00000007U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT24_CMN0_BIST_FRM_NUM_MAX (0x000000FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT24_CMN0_BIST_CLEAR_MASK (0x00000040U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT24_CMN0_BIST_CLEAR_SHIFT (0x00000006U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT24_CMN0_BIST_CLEAR_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT24_CMN0_BIST_PRBS_MASK (0x00000030U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT24_CMN0_BIST_PRBS_SHIFT (0x00000004U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT24_CMN0_BIST_PRBS_MAX (0x00000003U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT24_CMN0_BIST_TEST_MODE_MASK (0x0000000EU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT24_CMN0_BIST_TEST_MODE_SHIFT (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT24_CMN0_BIST_TEST_MODE_MAX (0x00000007U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT24_CMN0_UNUSED_0_MASK (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT24_CMN0_UNUSED_0_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT24_CMN0_UNUSED_0_MAX (0x00000001U)
+
+/* CMN0_CMN_DIG_TBIT25 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT25_CMN0_BIST_RUN_LENGTH_MASK (0x00000FFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT25_CMN0_BIST_RUN_LENGTH_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT25_CMN0_BIST_RUN_LENGTH_MAX (0x00000FFFU)
+
+/* CMN0_CMN_DIG_TBIT26 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT26_CMN0_UNUSED_31_8_MASK (0xFFFFFF00U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT26_CMN0_UNUSED_31_8_SHIFT (0x00000008U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT26_CMN0_UNUSED_31_8_MAX (0x00FFFFFFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT26_CMN0_BIST_IDLE_TIME_MASK (0x000000FFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT26_CMN0_BIST_IDLE_TIME_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT26_CMN0_BIST_IDLE_TIME_MAX (0x000000FFU)
+
+/* CMN0_CMN_DIG_TBIT27 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT27_CMN0_BIST_PKT4_MASK (0xFF000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT27_CMN0_BIST_PKT4_SHIFT (0x00000018U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT27_CMN0_BIST_PKT4_MAX (0x000000FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT27_CMN0_BIST_PKT3_MASK (0x00FF0000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT27_CMN0_BIST_PKT3_SHIFT (0x00000010U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT27_CMN0_BIST_PKT3_MAX (0x000000FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT27_CMN0_BIST_PKT2_MASK (0x0000FF00U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT27_CMN0_BIST_PKT2_SHIFT (0x00000008U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT27_CMN0_BIST_PKT2_MAX (0x000000FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT27_CMN0_BIST_PKT1_MASK (0x000000FFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT27_CMN0_BIST_PKT1_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT27_CMN0_BIST_PKT1_MAX (0x000000FFU)
+
+/* CMN0_CMN_DIG_TBIT28 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT28_CMN0_BIST_TM_CLOCK_LP_DP_SEL_MASK (0x00800000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT28_CMN0_BIST_TM_CLOCK_LP_DP_SEL_SHIFT (0x00000017U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT28_CMN0_BIST_TM_CLOCK_LP_DP_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT28_CMN0_BIST_TM_CLOCK_LP_DP_VAL_MASK (0x00400000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT28_CMN0_BIST_TM_CLOCK_LP_DP_VAL_SHIFT (0x00000016U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT28_CMN0_BIST_TM_CLOCK_LP_DP_VAL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT28_CMN0_BIST_TM_CLOCK_LP_DN_SEL_MASK (0x00200000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT28_CMN0_BIST_TM_CLOCK_LP_DN_SEL_SHIFT (0x00000015U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT28_CMN0_BIST_TM_CLOCK_LP_DN_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT28_CMN0_BIST_TM_CLOCK_LP_DN_VAL_MASK (0x00100000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT28_CMN0_BIST_TM_CLOCK_LP_DN_VAL_SHIFT (0x00000014U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT28_CMN0_BIST_TM_CLOCK_LP_DN_VAL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT28_CMN0_BIST_TM_DATA_LP_DP_SEL_MASK (0x00080000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT28_CMN0_BIST_TM_DATA_LP_DP_SEL_SHIFT (0x00000013U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT28_CMN0_BIST_TM_DATA_LP_DP_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT28_CMN0_BIST_TM_DATA_LP_DP_VAL_MASK (0x00040000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT28_CMN0_BIST_TM_DATA_LP_DP_VAL_SHIFT (0x00000012U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT28_CMN0_BIST_TM_DATA_LP_DP_VAL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT28_CMN0_BIST_TM_DATA_LP_DN_SEL_MASK (0x00020000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT28_CMN0_BIST_TM_DATA_LP_DN_SEL_SHIFT (0x00000011U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT28_CMN0_BIST_TM_DATA_LP_DN_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT28_CMN0_BIST_TM_DATA_LP_DN_VAL_MASK (0x00010000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT28_CMN0_BIST_TM_DATA_LP_DN_VAL_SHIFT (0x00000010U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT28_CMN0_BIST_TM_DATA_LP_DN_VAL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT28_CMN0_UNUSED_INT_MASK (0x0000C000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT28_CMN0_UNUSED_INT_SHIFT (0x0000000EU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT28_CMN0_UNUSED_INT_MAX (0x00000003U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT28_CMN0_BIST_LFSR_FREEZE_MASK (0x00002000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT28_CMN0_BIST_LFSR_FREEZE_SHIFT (0x0000000DU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT28_CMN0_BIST_LFSR_FREEZE_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT28_CMN0_BIST_ERR_INJ_POINT_MASK (0x00001FFEU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT28_CMN0_BIST_ERR_INJ_POINT_SHIFT (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT28_CMN0_BIST_ERR_INJ_POINT_MAX (0x00000FFFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT28_CMN0_BIST_ERR_INJ_EN_MASK (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT28_CMN0_BIST_ERR_INJ_EN_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT28_CMN0_BIST_ERR_INJ_EN_MAX (0x00000001U)
+
+/* CMN0_CMN_DIG_TBIT31 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT31_CMN0_O_RX_SSM_LDO_EN_REF_TMR_MASK (0x00FF0000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT31_CMN0_O_RX_SSM_LDO_EN_REF_TMR_SHIFT (0x00000010U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT31_CMN0_O_RX_SSM_LDO_EN_REF_TMR_MAX (0x000000FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT31_CMN0_O_RX_SSM_LDO_EN_DEL_TMR_MASK (0x0000FF00U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT31_CMN0_O_RX_SSM_LDO_EN_DEL_TMR_SHIFT (0x00000008U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT31_CMN0_O_RX_SSM_LDO_EN_DEL_TMR_MAX (0x000000FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT31_CMN0_O_RX_SSM_LDO_EN_TMR_MASK (0x000000FFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT31_CMN0_O_RX_SSM_LDO_EN_TMR_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT31_CMN0_O_RX_SSM_LDO_EN_TMR_MAX (0x000000FFU)
+
+/* CMN0_CMN_DIG_TBIT32 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT32_CMN0_O_RX_SSM_ANA_BIST_ISO_DIS_TMR_MASK (0x0000FF00U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT32_CMN0_O_RX_SSM_ANA_BIST_ISO_DIS_TMR_SHIFT (0x00000008U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT32_CMN0_O_RX_SSM_ANA_BIST_ISO_DIS_TMR_MAX (0x000000FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT32_CMN0_O_RX_SSM_ANA_BIST_EN_DEL_TMR_MASK (0x000000FFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT32_CMN0_O_RX_SSM_ANA_BIST_EN_DEL_TMR_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT32_CMN0_O_RX_SSM_ANA_BIST_EN_DEL_TMR_MAX (0x000000FFU)
+
+/* CMN0_CMN_DIG_TBIT33 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT33_CMN0_O_RX_OSC_CAL_TIMER_SCALE_SEL_MASK (0xE0000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT33_CMN0_O_RX_OSC_CAL_TIMER_SCALE_SEL_SHIFT (0x0000001DU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT33_CMN0_O_RX_OSC_CAL_TIMER_SCALE_SEL_MAX (0x00000007U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT33_CMN0_O_RX_REFCLK_TIMER_ITER_VALUE_TM_MASK (0x03FFC000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT33_CMN0_O_RX_REFCLK_TIMER_ITER_VALUE_TM_SHIFT (0x0000000EU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT33_CMN0_O_RX_REFCLK_TIMER_ITER_VALUE_TM_MAX (0x00000FFFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT33_CMN0_O_RX_REFCLK_TIMER_ITER_VALUE_TM_SEL_MASK (0x00002000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT33_CMN0_O_RX_REFCLK_TIMER_ITER_VALUE_TM_SEL_SHIFT (0x0000000DU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT33_CMN0_O_RX_REFCLK_TIMER_ITER_VALUE_TM_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT33_CMN0_O_RX_REFCLK_TIMER_INIT_VALUE_TM_MASK (0x00001FFEU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT33_CMN0_O_RX_REFCLK_TIMER_INIT_VALUE_TM_SHIFT (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT33_CMN0_O_RX_REFCLK_TIMER_INIT_VALUE_TM_MAX (0x00000FFFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT33_CMN0_O_RX_REFCLK_TIMER_INIT_VALUE_TM_SEL_MASK (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT33_CMN0_O_RX_REFCLK_TIMER_INIT_VALUE_TM_SEL_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT33_CMN0_O_RX_REFCLK_TIMER_INIT_VALUE_TM_SEL_MAX (0x00000001U)
+
+/* CMN0_CMN_DIG_TBIT34 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT34_CMN0_O_RX_OSC_EN_DEL_TMR_VALUE_TM_MASK (0x03FFC000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT34_CMN0_O_RX_OSC_EN_DEL_TMR_VALUE_TM_SHIFT (0x0000000EU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT34_CMN0_O_RX_OSC_EN_DEL_TMR_VALUE_TM_MAX (0x00000FFFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT34_CMN0_O_RX_OSC_EN_DEL_TMR_VALUE_TM_SEL_MASK (0x00002000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT34_CMN0_O_RX_OSC_EN_DEL_TMR_VALUE_TM_SEL_SHIFT (0x0000000DU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT34_CMN0_O_RX_OSC_EN_DEL_TMR_VALUE_TM_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT34_CMN0_O_RX_REFCLK_TIMER_START_VALUE_TM_MASK (0x00001FFEU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT34_CMN0_O_RX_REFCLK_TIMER_START_VALUE_TM_SHIFT (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT34_CMN0_O_RX_REFCLK_TIMER_START_VALUE_TM_MAX (0x00000FFFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT34_CMN0_O_RX_REFCLK_TIMER_START_VALUE_TM_SEL_MASK (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT34_CMN0_O_RX_REFCLK_TIMER_START_VALUE_TM_SEL_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT34_CMN0_O_RX_REFCLK_TIMER_START_VALUE_TM_SEL_MAX (0x00000001U)
+
+/* CMN0_CMN_DIG_TBIT35 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT35_CMN0_O_RX_PLLCNT_COUNT_START_VALUE_2_MASK (0x00FFF000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT35_CMN0_O_RX_PLLCNT_COUNT_START_VALUE_2_SHIFT (0x0000000CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT35_CMN0_O_RX_PLLCNT_COUNT_START_VALUE_2_MAX (0x00000FFFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT35_CMN0_O_RX_PLLCNT_COUNT_START_VALUE_1_MASK (0x00000FFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT35_CMN0_O_RX_PLLCNT_COUNT_START_VALUE_1_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT35_CMN0_O_RX_PLLCNT_COUNT_START_VALUE_1_MAX (0x00000FFFU)
+
+/* CMN0_CMN_DIG_TBIT36 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT36_CMN0_O_RX_TM_VCOCAL_OVRD_VALUE_MASK (0x000FE000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT36_CMN0_O_RX_TM_VCOCAL_OVRD_VALUE_SHIFT (0x0000000DU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT36_CMN0_O_RX_TM_VCOCAL_OVRD_VALUE_MAX (0x0000007FU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT36_CMN0_O_RX_TM_VCO_CAL_OVERRIDE_EN_MASK (0x00001000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT36_CMN0_O_RX_TM_VCO_CAL_OVERRIDE_EN_SHIFT (0x0000000CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT36_CMN0_O_RX_TM_VCO_CAL_OVERRIDE_EN_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT36_CMN0_O_RX_OSC_CAL_CODE_START_MASK (0x00000FE0U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT36_CMN0_O_RX_OSC_CAL_CODE_START_SHIFT (0x00000005U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT36_CMN0_O_RX_OSC_CAL_CODE_START_MAX (0x0000007FU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT36_CMN0_O_RX_OSC_CAL_CODE_INIT_STEP_MASK (0x0000001CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT36_CMN0_O_RX_OSC_CAL_CODE_INIT_STEP_SHIFT (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT36_CMN0_O_RX_OSC_CAL_CODE_INIT_STEP_MAX (0x00000007U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT36_CMN0_O_RX_TM_SEL_1P5G_MODE_MASK (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT36_CMN0_O_RX_TM_SEL_1P5G_MODE_SHIFT (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT36_CMN0_O_RX_TM_SEL_1P5G_MODE_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT36_CMN0_O_RX_TM_OSC_CAL_EN_MASK (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT36_CMN0_O_RX_TM_OSC_CAL_EN_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT36_CMN0_O_RX_TM_OSC_CAL_EN_MAX (0x00000001U)
+
+/* CMN0_CMN_DIG_TBIT37 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT37_CMN0_O_CMNDA_HSRX_OSC_CALIB_SEL_TM_MASK (0x00004000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT37_CMN0_O_CMNDA_HSRX_OSC_CALIB_SEL_TM_SHIFT (0x0000000EU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT37_CMN0_O_CMNDA_HSRX_OSC_CALIB_SEL_TM_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT37_CMN0_O_CMNDA_HSRX_OSC_CALIB_SEL_TM_SEL_MASK (0x00002000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT37_CMN0_O_CMNDA_HSRX_OSC_CALIB_SEL_TM_SEL_SHIFT (0x0000000DU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT37_CMN0_O_CMNDA_HSRX_OSC_CALIB_SEL_TM_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT37_CMN0_O_CMNDA_RX_OSC_DIV_RESET_N_TM_MASK (0x00001000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT37_CMN0_O_CMNDA_RX_OSC_DIV_RESET_N_TM_SHIFT (0x0000000CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT37_CMN0_O_CMNDA_RX_OSC_DIV_RESET_N_TM_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT37_CMN0_O_CMNDA_RX_OSC_DIV_RESET_N_TM_SEL_MASK (0x00000800U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT37_CMN0_O_CMNDA_RX_OSC_DIV_RESET_N_TM_SEL_SHIFT (0x0000000BU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT37_CMN0_O_CMNDA_RX_OSC_DIV_RESET_N_TM_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT37_CMN0_O_CMNDA_RX_OSC_EN_DEL_TM_MASK (0x00000400U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT37_CMN0_O_CMNDA_RX_OSC_EN_DEL_TM_SHIFT (0x0000000AU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT37_CMN0_O_CMNDA_RX_OSC_EN_DEL_TM_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT37_CMN0_O_CMNDA_RX_OSC_EN_DEL_TM_SEL_MASK (0x00000200U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT37_CMN0_O_CMNDA_RX_OSC_EN_DEL_TM_SEL_SHIFT (0x00000009U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT37_CMN0_O_CMNDA_RX_OSC_EN_DEL_TM_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT37_CMN0_O_CMNDA_RX_OSC_EN_TM_MASK (0x00000100U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT37_CMN0_O_CMNDA_RX_OSC_EN_TM_SHIFT (0x00000008U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT37_CMN0_O_CMNDA_RX_OSC_EN_TM_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT37_CMN0_O_CMNDA_RX_OSC_EN_TM_SEL_MASK (0x00000080U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT37_CMN0_O_CMNDA_RX_OSC_EN_TM_SEL_SHIFT (0x00000007U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT37_CMN0_O_CMNDA_RX_OSC_EN_TM_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT37_CMN0_O_CMNDA_RX_LDO_BYPASS_TM_MASK (0x00000040U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT37_CMN0_O_CMNDA_RX_LDO_BYPASS_TM_SHIFT (0x00000006U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT37_CMN0_O_CMNDA_RX_LDO_BYPASS_TM_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT37_CMN0_O_CMNDA_RX_LDO_REF_EN_TM_MASK (0x00000020U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT37_CMN0_O_CMNDA_RX_LDO_REF_EN_TM_SHIFT (0x00000005U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT37_CMN0_O_CMNDA_RX_LDO_REF_EN_TM_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT37_CMN0_O_CMNDA_RX_LDO_REF_EN_TM_SEL_MASK (0x00000010U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT37_CMN0_O_CMNDA_RX_LDO_REF_EN_TM_SEL_SHIFT (0x00000004U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT37_CMN0_O_CMNDA_RX_LDO_REF_EN_TM_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT37_CMN0_O_CMNDA_RX_LDO_EN_DEL_TM_MASK (0x00000008U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT37_CMN0_O_CMNDA_RX_LDO_EN_DEL_TM_SHIFT (0x00000003U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT37_CMN0_O_CMNDA_RX_LDO_EN_DEL_TM_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT37_CMN0_O_CMNDA_RX_LDO_EN_DEL_TM_SEL_MASK (0x00000004U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT37_CMN0_O_CMNDA_RX_LDO_EN_DEL_TM_SEL_SHIFT (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT37_CMN0_O_CMNDA_RX_LDO_EN_DEL_TM_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT37_CMN0_O_CMNDA_RX_LDO_EN_TM_MASK (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT37_CMN0_O_CMNDA_RX_LDO_EN_TM_SHIFT (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT37_CMN0_O_CMNDA_RX_LDO_EN_TM_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT37_CMN0_O_CMNDA_RX_LDO_EN_TM_SEL_MASK (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT37_CMN0_O_CMNDA_RX_LDO_EN_TM_SEL_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT37_CMN0_O_CMNDA_RX_LDO_EN_TM_SEL_MAX (0x00000001U)
+
+/* CMN0_CMN_DIG_TBIT39 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT39_CMN0_SPARE_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT39_CMN0_SPARE_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT39_CMN0_SPARE_MAX (0xFFFFFFFFU)
+
+/* CMN0_CMN_DIG_TBIT50 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT50_CMN0_BIST_COMPLETE_MASK (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT50_CMN0_BIST_COMPLETE_SHIFT (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT50_CMN0_BIST_COMPLETE_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT50_CMN0_BIST_EN_ACK_MASK (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT50_CMN0_BIST_EN_ACK_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT50_CMN0_BIST_EN_ACK_MAX (0x00000001U)
+
+/* CMN0_CMN_DIG_TBIT53 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT53_CMN0_I_CMSMT_TEST_CLK_CNT_VALUE_MASK (0x0001FFFEU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT53_CMN0_I_CMSMT_TEST_CLK_CNT_VALUE_SHIFT (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT53_CMN0_I_CMSMT_TEST_CLK_CNT_VALUE_MAX (0x0000FFFFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT53_CMN0_I_CMSMT_MEASUREMENT_DONE_MASK (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT53_CMN0_I_CMSMT_MEASUREMENT_DONE_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT53_CMN0_I_CMSMT_MEASUREMENT_DONE_MAX (0x00000001U)
+
+/* CMN0_CMN_DIG_TBIT54 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT54_CMN0_I_CMN_PLL_SSM_STATE_MASK (0xFFF00000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT54_CMN0_I_CMN_PLL_SSM_STATE_SHIFT (0x00000014U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT54_CMN0_I_CMN_PLL_SSM_STATE_MAX (0x00000FFFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT54_CMN0_I_DIG_PG_ACK_MASK (0x00000010U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT54_CMN0_I_DIG_PG_ACK_SHIFT (0x00000004U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT54_CMN0_I_DIG_PG_ACK_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT54_CMN0_I_PLL_NOT_LOCKED_MASK (0x00000008U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT54_CMN0_I_PLL_NOT_LOCKED_SHIFT (0x00000003U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT54_CMN0_I_PLL_NOT_LOCKED_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT54_CMN0_I_PLL_LOCKED_MASK (0x00000004U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT54_CMN0_I_PLL_LOCKED_SHIFT (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT54_CMN0_I_PLL_LOCKED_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT54_CMN0_I_ANA_RES_COMP_OUT_MASK (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT54_CMN0_I_ANA_RES_COMP_OUT_SHIFT (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT54_CMN0_I_ANA_RES_COMP_OUT_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT54_CMN0_I_CMN_TX_READY_MASK (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT54_CMN0_I_CMN_TX_READY_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT54_CMN0_I_CMN_TX_READY_MAX (0x00000001U)
+
+/* CMN0_CMN_DIG_TBIT56 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT56_CMN0_I_CMNDA_RX_OSC_CALCODE_MASK (0x0FE00000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT56_CMN0_I_CMNDA_RX_OSC_CALCODE_SHIFT (0x00000015U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT56_CMN0_I_CMNDA_RX_OSC_CALCODE_MAX (0x0000007FU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT56_CMN0_I_CMN_RX_SSM_STATE_MASK (0x001FF800U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT56_CMN0_I_CMN_RX_SSM_STATE_SHIFT (0x0000000BU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT56_CMN0_I_CMN_RX_SSM_STATE_MAX (0x000003FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT56_CMN0_I_RX_OSC_CAL_FSM_STATE_MASK (0x000007FCU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT56_CMN0_I_RX_OSC_CAL_FSM_STATE_SHIFT (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT56_CMN0_I_RX_OSC_CAL_FSM_STATE_MAX (0x000001FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT56_CMN0_I_ANA_RES_COMP_OUT_X_MASK (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT56_CMN0_I_ANA_RES_COMP_OUT_X_SHIFT (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT56_CMN0_I_ANA_RES_COMP_OUT_X_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT56_CMN0_I_CMN_RX_READY_MASK (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT56_CMN0_I_CMN_RX_READY_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT56_CMN0_I_CMN_RX_READY_MAX (0x00000001U)
+
+/* CMN0_CMN_DIG_TBIT58 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT58_CMN0_I_RES_CALIB_CODE_MASK (0x0000003EU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT58_CMN0_I_RES_CALIB_CODE_SHIFT (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT58_CMN0_I_RES_CALIB_CODE_MAX (0x0000001FU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT58_CMN0_I_RES_CALIB_DONE_MASK (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT58_CMN0_I_RES_CALIB_DONE_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CMN0_CMN_DIG_TBIT58_CMN0_I_RES_CALIB_DONE_MAX (0x00000001U)
+
+/* CLK0_TX_ANA_TBIT0 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_ANA_TBIT0_CLK0_ANA_TBIT0_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_ANA_TBIT0_CLK0_ANA_TBIT0_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_ANA_TBIT0_CLK0_ANA_TBIT0_MAX (0xFFFFFFFFU)
+
+/* CLK0_TX_ANA_TBIT1 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_ANA_TBIT1_CLK0_ANA_TBIT1_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_ANA_TBIT1_CLK0_ANA_TBIT1_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_ANA_TBIT1_CLK0_ANA_TBIT1_MAX (0xFFFFFFFFU)
+
+/* CLK0_TX_ANA_TBIT2 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_ANA_TBIT2_CLK0_ANA_TBIT2_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_ANA_TBIT2_CLK0_ANA_TBIT2_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_ANA_TBIT2_CLK0_ANA_TBIT2_MAX (0xFFFFFFFFU)
+
+/* CLK0_TX_ANA_TBIT3 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_ANA_TBIT3_CLK0_ANA_TBIT3_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_ANA_TBIT3_CLK0_ANA_TBIT3_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_ANA_TBIT3_CLK0_ANA_TBIT3_MAX (0xFFFFFFFFU)
+
+/* CLK0_TX_ANA_TBIT4 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_ANA_TBIT4_CLK0_ANA_TBIT4_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_ANA_TBIT4_CLK0_ANA_TBIT4_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_ANA_TBIT4_CLK0_ANA_TBIT4_MAX (0xFFFFFFFFU)
+
+/* CLK0_TX_DIG_TBIT0 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT0_CLK0_ULPS_PULLDN_CNT_MASK (0x00001F00U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT0_CLK0_ULPS_PULLDN_CNT_SHIFT (0x00000008U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT0_CLK0_ULPS_PULLDN_CNT_MAX (0x0000001FU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT0_CLK0_UNUSED_7_5_MASK (0x000000E0U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT0_CLK0_UNUSED_7_5_SHIFT (0x00000005U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT0_CLK0_UNUSED_7_5_MAX (0x00000007U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT0_CLK0_LDO_EN_CNT_MASK (0x0000001FU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT0_CLK0_LDO_EN_CNT_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT0_CLK0_LDO_EN_CNT_MAX (0x0000001FU)
+
+/* CLK0_TX_DIG_TBIT1 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT1_CLK0_HS_PREP_HALF_CYC_SEL_MASK (0x00020000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT1_CLK0_HS_PREP_HALF_CYC_SEL_SHIFT (0x00000011U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT1_CLK0_HS_PREP_HALF_CYC_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT1_CLK0_HS_PREP_HALF_CYC_EN_MASK (0x00010000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT1_CLK0_HS_PREP_HALF_CYC_EN_SHIFT (0x00000010U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT1_CLK0_HS_PREP_HALF_CYC_EN_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT1_CLK0_CLK_TRAIL_OFFSET_MASK (0x0000F000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT1_CLK0_CLK_TRAIL_OFFSET_SHIFT (0x0000000CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT1_CLK0_CLK_TRAIL_OFFSET_MAX (0x0000000FU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT1_CLK0_CLK_ZERO_OFFSET_MASK (0x00000F00U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT1_CLK0_CLK_ZERO_OFFSET_SHIFT (0x00000008U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT1_CLK0_CLK_ZERO_OFFSET_MAX (0x0000000FU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT1_CLK0_CLK_PREP_OFFSET_MASK (0x000000F0U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT1_CLK0_CLK_PREP_OFFSET_SHIFT (0x00000004U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT1_CLK0_CLK_PREP_OFFSET_MAX (0x0000000FU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT1_CLK0_TLPX_OFFSET_MASK (0x0000000FU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT1_CLK0_TLPX_OFFSET_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT1_CLK0_TLPX_OFFSET_MAX (0x0000000FU)
+
+/* CLK0_TX_DIG_TBIT2 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT2_CLK0_SERSYNTH_LOOPBACK_MASK (0x00000020U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT2_CLK0_SERSYNTH_LOOPBACK_SHIFT (0x00000005U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT2_CLK0_SERSYNTH_LOOPBACK_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT2_CLK0_BAL_FORCE_STATE_MASK (0x0000001CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT2_CLK0_BAL_FORCE_STATE_SHIFT (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT2_CLK0_BAL_FORCE_STATE_MAX (0x00000007U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT2_CLK0_BAL_FORCE_EN_MASK (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT2_CLK0_BAL_FORCE_EN_SHIFT (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT2_CLK0_BAL_FORCE_EN_MAX (0x00000001U)
+
+/* CLK0_TX_DIG_TBIT8 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT8_CLK0_WAIT_TIME_MASK (0x3C000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT8_CLK0_WAIT_TIME_SHIFT (0x0000001AU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT8_CLK0_WAIT_TIME_MAX (0x0000000FU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT8_CLK0_ULPTX_TEST_TIME_MASK (0x03FC0000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT8_CLK0_ULPTX_TEST_TIME_SHIFT (0x00000012U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT8_CLK0_ULPTX_TEST_TIME_MAX (0x000000FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT8_CLK0_HS_CLK_CHECK_TIME_MASK (0x0003FFFCU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT8_CLK0_HS_CLK_CHECK_TIME_SHIFT (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT8_CLK0_HS_CLK_CHECK_TIME_MAX (0x0000FFFFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT8_CLK0_LOOPBACK_MODE_MASK (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT8_CLK0_LOOPBACK_MODE_SHIFT (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT8_CLK0_LOOPBACK_MODE_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT8_CLK0_BIST_EN_MASK (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT8_CLK0_BIST_EN_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT8_CLK0_BIST_EN_MAX (0x00000001U)
+
+/* CLK0_TX_DIG_TBIT9 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT9_CLK0_BIST_DIG_TO_DIG_LOOPBACK_MASK (0x00000400U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT9_CLK0_BIST_DIG_TO_DIG_LOOPBACK_SHIFT (0x0000000AU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT9_CLK0_BIST_DIG_TO_DIG_LOOPBACK_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT9_CLK0_UNUSED_9_5_MASK (0x000003E0U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT9_CLK0_UNUSED_9_5_SHIFT (0x00000005U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT9_CLK0_UNUSED_9_5_MAX (0x0000001FU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT9_CLK0_HS_CLK_CHECK_EXTRA_TIME_MASK (0x0000001FU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT9_CLK0_HS_CLK_CHECK_EXTRA_TIME_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT9_CLK0_HS_CLK_CHECK_EXTRA_TIME_MAX (0x0000001FU)
+
+/* CLK0_TX_DIG_TBIT10 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT10_CLK0_SPARE_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT10_CLK0_SPARE_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT10_CLK0_SPARE_MAX (0xFFFFFFFFU)
+
+/* CLK0_TX_DIG_TBIT14 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT14_CLK0_TM_ISO_EN_MASK (0x80000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT14_CLK0_TM_ISO_EN_SHIFT (0x0000001FU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT14_CLK0_TM_ISO_EN_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT14_CLK0_TM_LOAD_DPDN_SEL_MASK (0x40000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT14_CLK0_TM_LOAD_DPDN_SEL_SHIFT (0x0000001EU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT14_CLK0_TM_LOAD_DPDN_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT14_CLK0_TM_LOAD_DPDN_MASK (0x38000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT14_CLK0_TM_LOAD_DPDN_SHIFT (0x0000001BU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT14_CLK0_TM_LOAD_DPDN_MAX (0x00000007U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT14_CLK0_TM_HSTX_DATA_RATE_SEL_MASK (0x04000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT14_CLK0_TM_HSTX_DATA_RATE_SEL_SHIFT (0x0000001AU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT14_CLK0_TM_HSTX_DATA_RATE_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT14_CLK0_TM_HSTX_DATE_RATE_MASK (0x03000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT14_CLK0_TM_HSTX_DATE_RATE_SHIFT (0x00000018U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT14_CLK0_TM_HSTX_DATE_RATE_MAX (0x00000003U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT14_CLK0_TM_BIST_ULP_RCV_EN_SEL_MASK (0x00800000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT14_CLK0_TM_BIST_ULP_RCV_EN_SEL_SHIFT (0x00000017U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT14_CLK0_TM_BIST_ULP_RCV_EN_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT14_CLK0_TM_BIST_ULP_RCV_EN_MASK (0x00400000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT14_CLK0_TM_BIST_ULP_RCV_EN_SHIFT (0x00000016U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT14_CLK0_TM_BIST_ULP_RCV_EN_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT14_CLK0_TM_ULPS_PULDN_SEL_MASK (0x00200000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT14_CLK0_TM_ULPS_PULDN_SEL_SHIFT (0x00000015U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT14_CLK0_TM_ULPS_PULDN_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT14_CLK0_TM_ULPS_PULDN_MASK (0x00100000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT14_CLK0_TM_ULPS_PULDN_SHIFT (0x00000014U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT14_CLK0_TM_ULPS_PULDN_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT14_CLK0_TM_BIST_SMPLR_CLK_EDGE_SEL_MASK (0x00080000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT14_CLK0_TM_BIST_SMPLR_CLK_EDGE_SEL_SHIFT (0x00000013U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT14_CLK0_TM_BIST_SMPLR_CLK_EDGE_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT14_CLK0_TM_BIST_SMPLR_CLK_EDGE_MASK (0x00040000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT14_CLK0_TM_BIST_SMPLR_CLK_EDGE_SHIFT (0x00000012U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT14_CLK0_TM_BIST_SMPLR_CLK_EDGE_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT14_CLK0_TM_BIST_EN_SEL_MASK (0x00020000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT14_CLK0_TM_BIST_EN_SEL_SHIFT (0x00000011U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT14_CLK0_TM_BIST_EN_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT14_CLK0_TM_BIST_EN_MASK (0x00010000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT14_CLK0_TM_BIST_EN_SHIFT (0x00000010U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT14_CLK0_TM_BIST_EN_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT14_CLK0_TM_LPTX_TRST_SEL_MASK (0x00008000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT14_CLK0_TM_LPTX_TRST_SEL_SHIFT (0x0000000FU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT14_CLK0_TM_LPTX_TRST_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT14_CLK0_TM_LPTX_TRST_MASK (0x00004000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT14_CLK0_TM_LPTX_TRST_SHIFT (0x0000000EU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT14_CLK0_TM_LPTX_TRST_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT14_CLK0_TM_LPTX_RST_SEL_MASK (0x00002000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT14_CLK0_TM_LPTX_RST_SEL_SHIFT (0x0000000DU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT14_CLK0_TM_LPTX_RST_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT14_CLK0_TM_LPTX_RST_MASK (0x00001000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT14_CLK0_TM_LPTX_RST_SHIFT (0x0000000CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT14_CLK0_TM_LPTX_RST_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT14_CLK0_TM_LPTX_DP_SEL_MASK (0x00000800U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT14_CLK0_TM_LPTX_DP_SEL_SHIFT (0x0000000BU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT14_CLK0_TM_LPTX_DP_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT14_CLK0_TM_LPTX_DP_MASK (0x00000400U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT14_CLK0_TM_LPTX_DP_SHIFT (0x0000000AU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT14_CLK0_TM_LPTX_DP_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT14_CLK0_TM_LPTX_DN_SEL_MASK (0x00000200U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT14_CLK0_TM_LPTX_DN_SEL_SHIFT (0x00000009U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT14_CLK0_TM_LPTX_DN_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT14_CLK0_TM_LPTX_DN_MASK (0x00000100U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT14_CLK0_TM_LPTX_DN_SHIFT (0x00000008U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT14_CLK0_TM_LPTX_DN_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT14_CLK0_TM_LDO_REF_EN_SEL_MASK (0x00000080U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT14_CLK0_TM_LDO_REF_EN_SEL_SHIFT (0x00000007U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT14_CLK0_TM_LDO_REF_EN_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT14_CLK0_TM_LDO_REF_EN_MASK (0x00000040U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT14_CLK0_TM_LDO_REF_EN_SHIFT (0x00000006U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT14_CLK0_TM_LDO_REF_EN_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT14_CLK0_TM_HSTX_TRST_SEL_MASK (0x00000020U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT14_CLK0_TM_HSTX_TRST_SEL_SHIFT (0x00000005U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT14_CLK0_TM_HSTX_TRST_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT14_CLK0_TM_HSTX_TRST_MASK (0x00000010U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT14_CLK0_TM_HSTX_TRST_SHIFT (0x00000004U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT14_CLK0_TM_HSTX_TRST_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT14_CLK0_TM_HSTX_RQST_SEL_MASK (0x00000008U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT14_CLK0_TM_HSTX_RQST_SEL_SHIFT (0x00000003U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT14_CLK0_TM_HSTX_RQST_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT14_CLK0_TM_HSTX_RQST_MASK (0x00000004U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT14_CLK0_TM_HSTX_RQST_SHIFT (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT14_CLK0_TM_HSTX_RQST_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT14_CLK0_TM_GLOBAL_PD_SEL_MASK (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT14_CLK0_TM_GLOBAL_PD_SEL_SHIFT (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT14_CLK0_TM_GLOBAL_PD_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT14_CLK0_TM_GLOBAL_PD_MASK (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT14_CLK0_TM_GLOBAL_PD_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT14_CLK0_TM_GLOBAL_PD_MAX (0x00000001U)
+
+/* CLK0_TX_DIG_TBIT15 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT15_CLK0_TM_SERSYNTH_RST_N_SEL_MASK (0x00004000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT15_CLK0_TM_SERSYNTH_RST_N_SEL_SHIFT (0x0000000EU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT15_CLK0_TM_SERSYNTH_RST_N_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT15_CLK0_TM_SERSYNTH_RST_N_MASK (0x00002000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT15_CLK0_TM_SERSYNTH_RST_N_SHIFT (0x0000000DU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT15_CLK0_TM_SERSYNTH_RST_N_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT15_CLK0_TM_SWAP_DPDN_SEL_MASK (0x00001000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT15_CLK0_TM_SWAP_DPDN_SEL_SHIFT (0x0000000CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT15_CLK0_TM_SWAP_DPDN_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT15_CLK0_TM_SWAP_DPDN_EN_MASK (0x00000800U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT15_CLK0_TM_SWAP_DPDN_EN_SHIFT (0x0000000BU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT15_CLK0_TM_SWAP_DPDN_EN_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT15_CLK0_TM_SERSYNTH_EN_SEL_MASK (0x00000400U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT15_CLK0_TM_SERSYNTH_EN_SEL_SHIFT (0x0000000AU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT15_CLK0_TM_SERSYNTH_EN_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT15_CLK0_TM_SERSYNTH_EN_MASK (0x00000200U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT15_CLK0_TM_SERSYNTH_EN_SHIFT (0x00000009U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT15_CLK0_TM_SERSYNTH_EN_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT15_CLK0_TM_TX_DATA_HS_SEL_MASK (0x00000100U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT15_CLK0_TM_TX_DATA_HS_SEL_SHIFT (0x00000008U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT15_CLK0_TM_TX_DATA_HS_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT15_CLK0_TM_TX_DATA_HS_MASK (0x000000FFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT15_CLK0_TM_TX_DATA_HS_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT15_CLK0_TM_TX_DATA_HS_MAX (0x000000FFU)
+
+/* CLK0_TX_DIG_TBIT16 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT16_CLK0_DIG_TBIT16_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT16_CLK0_DIG_TBIT16_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT16_CLK0_DIG_TBIT16_MAX (0xFFFFFFFFU)
+
+/* CLK0_TX_DIG_TBIT17 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT17_CLK0_DIG_TBIT17_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT17_CLK0_DIG_TBIT17_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT17_CLK0_DIG_TBIT17_MAX (0xFFFFFFFFU)
+
+/* CLK0_TX_DIG_TBIT18 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT18_CLK0_DIG_TBIT18_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT18_CLK0_DIG_TBIT18_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT18_CLK0_DIG_TBIT18_MAX (0xFFFFFFFFU)
+
+/* CLK0_TX_DIG_TBIT19 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT19_CLK0_DIG_TBIT19_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT19_CLK0_DIG_TBIT19_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT19_CLK0_DIG_TBIT19_MAX (0xFFFFFFFFU)
+
+/* CLK0_TX_DIG_TBIT20 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT20_CLK0_DIG_TBIT20_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT20_CLK0_DIG_TBIT20_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT20_CLK0_DIG_TBIT20_MAX (0xFFFFFFFFU)
+
+/* CLK0_TX_ANA_TBIT5 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_ANA_TBIT5_CLK0_ANA_TBIT5_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_ANA_TBIT5_CLK0_ANA_TBIT5_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_ANA_TBIT5_CLK0_ANA_TBIT5_MAX (0xFFFFFFFFU)
+
+/* CLK0_TX_DIG_TBIT21 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT21_CLK0_ANA_CTRL_FSM_STATE_MASK (0x001F0000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT21_CLK0_ANA_CTRL_FSM_STATE_SHIFT (0x00000010U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT21_CLK0_ANA_CTRL_FSM_STATE_MAX (0x0000001FU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT21_CLK0_BIST_BAL_STATUS_MASK (0x0000FFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT21_CLK0_BIST_BAL_STATUS_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT21_CLK0_BIST_BAL_STATUS_MAX (0x0000FFFFU)
+
+/* CLK0_TX_DIG_TBIT22 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT22_CLK0_TM_ESC_FSM_STATE_MASK (0x003FF000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT22_CLK0_TM_ESC_FSM_STATE_SHIFT (0x0000000CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT22_CLK0_TM_ESC_FSM_STATE_MAX (0x000003FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT22_CLK0_TM_HS_FSM_STATE_MASK (0x00000FFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT22_CLK0_TM_HS_FSM_STATE_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT22_CLK0_TM_HS_FSM_STATE_MAX (0x00000FFFU)
+
+/* CLK0_TX_DIG_TBIT24 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT24_CLK0_BIST_ULP_DP_MASK (0x00020000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT24_CLK0_BIST_ULP_DP_SHIFT (0x00000011U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT24_CLK0_BIST_ULP_DP_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT24_CLK0_BIST_ULP_DN_MASK (0x00010000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT24_CLK0_BIST_ULP_DN_SHIFT (0x00000010U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT24_CLK0_BIST_ULP_DN_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT24_CLK0_BAL_FAIL_MASK (0x00008000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT24_CLK0_BAL_FAIL_SHIFT (0x0000000FU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT24_CLK0_BAL_FAIL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT24_CLK0_ULPTX_CHE_FSM_STATE_MASK (0x00006000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT24_CLK0_ULPTX_CHE_FSM_STATE_SHIFT (0x0000000DU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT24_CLK0_ULPTX_CHE_FSM_STATE_MAX (0x00000003U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT24_CLK0_LPTX_CHE_FSM_STATE_MASK (0x00001C00U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT24_CLK0_LPTX_CHE_FSM_STATE_SHIFT (0x0000000AU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT24_CLK0_LPTX_CHE_FSM_STATE_MAX (0x00000007U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT24_CLK0_CTRLR_FSM_STATE_MASK (0x00000380U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT24_CLK0_CTRLR_FSM_STATE_SHIFT (0x00000007U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT24_CLK0_CTRLR_FSM_STATE_MAX (0x00000007U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT24_CLK0_BIST_PASS_MASK (0x00000040U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT24_CLK0_BIST_PASS_SHIFT (0x00000006U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT24_CLK0_BIST_PASS_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT24_CLK0_ULPTX_BIST_PASS_MASK (0x00000020U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT24_CLK0_ULPTX_BIST_PASS_SHIFT (0x00000005U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT24_CLK0_ULPTX_BIST_PASS_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT24_CLK0_LPTX_BIST_PASS_MASK (0x00000010U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT24_CLK0_LPTX_BIST_PASS_SHIFT (0x00000004U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT24_CLK0_LPTX_BIST_PASS_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT24_CLK0_HS_BIST_ERR_POS_MASK (0x00000008U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT24_CLK0_HS_BIST_ERR_POS_SHIFT (0x00000003U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT24_CLK0_HS_BIST_ERR_POS_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT24_CLK0_HS_BIST_ERR_NEG_MASK (0x00000004U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT24_CLK0_HS_BIST_ERR_NEG_SHIFT (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT24_CLK0_HS_BIST_ERR_NEG_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT24_CLK0_BIST_CMPLT_MASK (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT24_CLK0_BIST_CMPLT_SHIFT (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT24_CLK0_BIST_CMPLT_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT24_CLK0_BIST_ENABLED_MASK (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT24_CLK0_BIST_ENABLED_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT24_CLK0_BIST_ENABLED_MAX (0x00000001U)
+
+/* CLK0_TX_DIG_TBIT25 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT25_CLK0_DIG_TBIT25_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT25_CLK0_DIG_TBIT25_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT25_CLK0_DIG_TBIT25_MAX (0xFFFFFFFFU)
+
+/* CLK0_TX_DIG_TBIT26 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT26_CLK0_DIG_TBIT26_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT26_CLK0_DIG_TBIT26_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT26_CLK0_DIG_TBIT26_MAX (0xFFFFFFFFU)
+
+/* CLK0_TX_DIG_TBIT27 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT27_CLK0_DIG_TBIT27_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT27_CLK0_DIG_TBIT27_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT27_CLK0_DIG_TBIT27_MAX (0xFFFFFFFFU)
+
+/* CLK0_TX_DIG_TBIT28 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT28_CLK0_DIG_TBIT28_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT28_CLK0_DIG_TBIT28_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT28_CLK0_DIG_TBIT28_MAX (0xFFFFFFFFU)
+
+/* CLK0_TX_DIG_TBIT29 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT29_CLK0_DIG_TBIT29_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT29_CLK0_DIG_TBIT29_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_CLK0_TX_DIG_TBIT29_CLK0_DIG_TBIT29_MAX (0xFFFFFFFFU)
+
+/* DL0_TX_ANA_TBIT0 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_ANA_TBIT0_DL0_ANA_TBIT0_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_ANA_TBIT0_DL0_ANA_TBIT0_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_ANA_TBIT0_DL0_ANA_TBIT0_MAX (0xFFFFFFFFU)
+
+/* DL0_TX_ANA_TBIT1 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_ANA_TBIT1_DL0_ANA_TBIT1_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_ANA_TBIT1_DL0_ANA_TBIT1_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_ANA_TBIT1_DL0_ANA_TBIT1_MAX (0xFFFFFFFFU)
+
+/* DL0_TX_ANA_TBIT2 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_ANA_TBIT2_DL0_ANA_TBIT2_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_ANA_TBIT2_DL0_ANA_TBIT2_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_ANA_TBIT2_DL0_ANA_TBIT2_MAX (0xFFFFFFFFU)
+
+/* DL0_TX_ANA_TBIT3 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_ANA_TBIT3_DL0_ANA_TBIT3_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_ANA_TBIT3_DL0_ANA_TBIT3_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_ANA_TBIT3_DL0_ANA_TBIT3_MAX (0xFFFFFFFFU)
+
+/* DL0_TX_ANA_TBIT4 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_ANA_TBIT4_DL0_ANA_TBIT4_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_ANA_TBIT4_DL0_ANA_TBIT4_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_ANA_TBIT4_DL0_ANA_TBIT4_MAX (0xFFFFFFFFU)
+
+/* DL0_TX_DIG_TBIT0 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT0_DL0_UNUSED_31_13_MASK (0xFFFFE000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT0_DL0_UNUSED_31_13_SHIFT (0x0000000DU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT0_DL0_UNUSED_31_13_MAX (0x0007FFFFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT0_DL0_ULPS_PULLDN_CNT_MASK (0x00001F00U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT0_DL0_ULPS_PULLDN_CNT_SHIFT (0x00000008U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT0_DL0_ULPS_PULLDN_CNT_MAX (0x0000001FU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT0_DL0_UNUSED_7_5_MASK (0x000000E0U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT0_DL0_UNUSED_7_5_SHIFT (0x00000005U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT0_DL0_UNUSED_7_5_MAX (0x00000007U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT0_DL0_LDO_EN_CNT_MASK (0x0000001FU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT0_DL0_LDO_EN_CNT_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT0_DL0_LDO_EN_CNT_MAX (0x0000001FU)
+
+/* DL0_TX_DIG_TBIT1 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT1_DL0_TEST_LPTX_DP_MASK (0x00200000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT1_DL0_TEST_LPTX_DP_SHIFT (0x00000015U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT1_DL0_TEST_LPTX_DP_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT1_DL0_TEST_LPTX_DN_MASK (0x00100000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT1_DL0_TEST_LPTX_DN_SHIFT (0x00000014U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT1_DL0_TEST_LPTX_DN_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT1_DL0_TEST_LPTX_EN_MASK (0x00080000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT1_DL0_TEST_LPTX_EN_SHIFT (0x00000013U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT1_DL0_TEST_LPTX_EN_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT1_DL0_TM_READY_SKEW_CAL_MASK (0x00040000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT1_DL0_TM_READY_SKEW_CAL_SHIFT (0x00000012U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT1_DL0_TM_READY_SKEW_CAL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT1_DL0_TM_HS_PREP_HAFCYC_OVERRIDE_MASK (0x00020000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT1_DL0_TM_HS_PREP_HAFCYC_OVERRIDE_SHIFT (0x00000011U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT1_DL0_TM_HS_PREP_HAFCYC_OVERRIDE_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT1_DL0_TM_HS_PREP_HSFCYC_MASK (0x00010000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT1_DL0_TM_HS_PREP_HSFCYC_SHIFT (0x00000010U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT1_DL0_TM_HS_PREP_HSFCYC_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT1_DL0_HS_TRAIL_OFFSET_MASK (0x0000F000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT1_DL0_HS_TRAIL_OFFSET_SHIFT (0x0000000CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT1_DL0_HS_TRAIL_OFFSET_MAX (0x0000000FU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT1_DL0_HS_ZERO_OFFSET_MASK (0x00000F00U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT1_DL0_HS_ZERO_OFFSET_SHIFT (0x00000008U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT1_DL0_HS_ZERO_OFFSET_MAX (0x0000000FU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT1_DL0_HS_PREP_OFFSET_MASK (0x000000F0U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT1_DL0_HS_PREP_OFFSET_SHIFT (0x00000004U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT1_DL0_HS_PREP_OFFSET_MAX (0x0000000FU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT1_DL0_HS_TLPX_OFFSET_MASK (0x0000000FU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT1_DL0_HS_TLPX_OFFSET_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT1_DL0_HS_TLPX_OFFSET_MAX (0x0000000FU)
+
+/* DL0_TX_DIG_TBIT2 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT2_DL0_TM_SKEW_CAL_SEQ_MASK (0x07F80000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT2_DL0_TM_SKEW_CAL_SEQ_SHIFT (0x00000013U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT2_DL0_TM_SKEW_CAL_SEQ_MAX (0x000000FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT2_DL0_TM_SKEW_CAL_SEQ_SEL_MASK (0x00040000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT2_DL0_TM_SKEW_CAL_SEQ_SEL_SHIFT (0x00000012U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT2_DL0_TM_SKEW_CAL_SEQ_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT2_DL0_TM_SKEW_CAL_SYNC_PKT_MASK (0x0003FC00U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT2_DL0_TM_SKEW_CAL_SYNC_PKT_SHIFT (0x0000000AU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT2_DL0_TM_SKEW_CAL_SYNC_PKT_MAX (0x000000FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT2_DL0_TM_SKEW_CAL_SYNC_PKT_SEL_MASK (0x00000200U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT2_DL0_TM_SKEW_CAL_SYNC_PKT_SEL_SHIFT (0x00000009U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT2_DL0_TM_SKEW_CAL_SYNC_PKT_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT2_DL0_TM_HS_SYNC_PKT_MASK (0x000001FEU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT2_DL0_TM_HS_SYNC_PKT_SHIFT (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT2_DL0_TM_HS_SYNC_PKT_MAX (0x000000FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT2_DL0_TM_HS_SYNC_PKT_SEL_MASK (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT2_DL0_TM_HS_SYNC_PKT_SEL_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT2_DL0_TM_HS_SYNC_PKT_SEL_MAX (0x00000001U)
+
+/* DL0_TX_DIG_TBIT3 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT3_DL0_SERSYNTH_LOOPBACK_MASK (0x00000020U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT3_DL0_SERSYNTH_LOOPBACK_SHIFT (0x00000005U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT3_DL0_SERSYNTH_LOOPBACK_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT3_DL0_BAL_FORCE_STATE_MASK (0x0000001CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT3_DL0_BAL_FORCE_STATE_SHIFT (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT3_DL0_BAL_FORCE_STATE_MAX (0x00000007U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT3_DL0_BAL_FORCE_EN_MASK (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT3_DL0_BAL_FORCE_EN_SHIFT (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT3_DL0_BAL_FORCE_EN_MAX (0x00000001U)
+
+/* DL0_TX_DIG_TBIT4 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT4_DL0_CONTENTION_EN_MASK (0x00008000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT4_DL0_CONTENTION_EN_SHIFT (0x0000000FU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT4_DL0_CONTENTION_EN_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT4_DL0_UNUSED_14_13_MASK (0x00006000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT4_DL0_UNUSED_14_13_SHIFT (0x0000000DU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT4_DL0_UNUSED_14_13_MAX (0x00000003U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT4_DL0_FORCE_RX_MODE_MASK (0x00001000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT4_DL0_FORCE_RX_MODE_SHIFT (0x0000000CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT4_DL0_FORCE_RX_MODE_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT4_DL0_TEST_DATA_LPTX_DP_SEL_MASK (0x00000800U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT4_DL0_TEST_DATA_LPTX_DP_SEL_SHIFT (0x0000000BU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT4_DL0_TEST_DATA_LPTX_DP_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT4_DL0_TEST_DATA_LPTX_DN_SEL_MASK (0x00000400U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT4_DL0_TEST_DATA_LPTX_DN_SEL_SHIFT (0x0000000AU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT4_DL0_TEST_DATA_LPTX_DN_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT4_DL0_TEST_DATA_LPTX_MASK (0x000003FCU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT4_DL0_TEST_DATA_LPTX_SHIFT (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT4_DL0_TEST_DATA_LPTX_MAX (0x000000FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT4_DL0_TEST_DATA_LPTX_RSTN_MASK (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT4_DL0_TEST_DATA_LPTX_RSTN_SHIFT (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT4_DL0_TEST_DATA_LPTX_RSTN_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT4_DL0_TEST_DATA_LPTX_EN_MASK (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT4_DL0_TEST_DATA_LPTX_EN_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT4_DL0_TEST_DATA_LPTX_EN_MAX (0x00000001U)
+
+/* DL0_TX_DIG_TBIT5 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT5_DL0_DIG_TBIT5_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT5_DL0_DIG_TBIT5_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT5_DL0_DIG_TBIT5_MAX (0xFFFFFFFFU)
+
+/* DL0_TX_DIG_TBIT6 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT6_DL0_DIG_TBIT6_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT6_DL0_DIG_TBIT6_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT6_DL0_DIG_TBIT6_MAX (0xFFFFFFFFU)
+
+/* DL0_TX_DIG_TBIT7 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT7_DL0_DIG_TBIT7_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT7_DL0_DIG_TBIT7_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT7_DL0_DIG_TBIT7_MAX (0xFFFFFFFFU)
+
+/* DL0_TX_DIG_TBIT8 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT8_DL0_DIG_TBIT8_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT8_DL0_DIG_TBIT8_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT8_DL0_DIG_TBIT8_MAX (0xFFFFFFFFU)
+
+/* DL0_TX_DIG_TBIT9 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT9_DL0_DIG_TBIT9_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT9_DL0_DIG_TBIT9_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT9_DL0_DIG_TBIT9_MAX (0xFFFFFFFFU)
+
+/* DL0_TX_DIG_TBIT10 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT10_DL0_BIST_WAIT_TIME_MASK (0x01E00000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT10_DL0_BIST_WAIT_TIME_SHIFT (0x00000015U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT10_DL0_BIST_WAIT_TIME_MAX (0x0000000FU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT10_DL0_BIST_ULPTX_TEST_TIME_MASK (0x001FE000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT10_DL0_BIST_ULPTX_TEST_TIME_SHIFT (0x0000000DU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT10_DL0_BIST_ULPTX_TEST_TIME_MAX (0x000000FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT10_DL0_BIST_SEND_CONFIG_MASK (0x00001800U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT10_DL0_BIST_SEND_CONFIG_SHIFT (0x0000000BU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT10_DL0_BIST_SEND_CONFIG_MAX (0x00000003U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT10_DL0_BIST_DIG_TO_DIG_LOOPBK_MASK (0x00000400U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT10_DL0_BIST_DIG_TO_DIG_LOOPBK_SHIFT (0x0000000AU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT10_DL0_BIST_DIG_TO_DIG_LOOPBK_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT10_DL0_BIST_RUN_NEGEDGE_FIRST_MASK (0x00000200U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT10_DL0_BIST_RUN_NEGEDGE_FIRST_SHIFT (0x00000009U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT10_DL0_BIST_RUN_NEGEDGE_FIRST_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT10_DL0_BIST_LENGTH_OF_DESKEW_MASK (0x000001FCU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT10_DL0_BIST_LENGTH_OF_DESKEW_SHIFT (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT10_DL0_BIST_LENGTH_OF_DESKEW_MAX (0x0000007FU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT10_DL0_BIST_LOOPBK_MODE_MASK (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT10_DL0_BIST_LOOPBK_MODE_SHIFT (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT10_DL0_BIST_LOOPBK_MODE_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT10_DL0_BIST_EN_MASK (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT10_DL0_BIST_EN_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT10_DL0_BIST_EN_MAX (0x00000001U)
+
+/* DL0_TX_DIG_TBIT11 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT11_DL0_BIST_FRM_IDLE_TIME_MASK (0xFF000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT11_DL0_BIST_FRM_IDLE_TIME_SHIFT (0x00000018U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT11_DL0_BIST_FRM_IDLE_TIME_MAX (0x000000FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT11_DL0_BIST_PKT_NUM_MASK (0x00FF0000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT11_DL0_BIST_PKT_NUM_SHIFT (0x00000010U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT11_DL0_BIST_PKT_NUM_MAX (0x000000FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT11_DL0_BIST_INF_MODE_MASK (0x00008000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT11_DL0_BIST_INF_MODE_SHIFT (0x0000000FU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT11_DL0_BIST_INF_MODE_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT11_DL0_BIST_FRM_NUM_MASK (0x00007F80U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT11_DL0_BIST_FRM_NUM_SHIFT (0x00000007U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT11_DL0_BIST_FRM_NUM_MAX (0x000000FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT11_DL0_BIST_CLEAR_MASK (0x00000040U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT11_DL0_BIST_CLEAR_SHIFT (0x00000006U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT11_DL0_BIST_CLEAR_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT11_DL0_BIST_PRBS_MASK (0x00000030U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT11_DL0_BIST_PRBS_SHIFT (0x00000004U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT11_DL0_BIST_PRBS_MAX (0x00000003U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT11_DL0_BIST_TEST_MODE_MASK (0x0000000EU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT11_DL0_BIST_TEST_MODE_SHIFT (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT11_DL0_BIST_TEST_MODE_MAX (0x00000007U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT11_DL0_UNUSED_0_MASK (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT11_DL0_UNUSED_0_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT11_DL0_UNUSED_0_MAX (0x00000001U)
+
+/* DL0_TX_DIG_TBIT12 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT12_DL0_BIST_RUN_LENGTH_MASK (0x00000FFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT12_DL0_BIST_RUN_LENGTH_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT12_DL0_BIST_RUN_LENGTH_MAX (0x00000FFFU)
+
+/* DL0_TX_DIG_TBIT13 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT13_DL0_UNUSED_31_8_MASK (0xFFFFFF00U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT13_DL0_UNUSED_31_8_SHIFT (0x00000008U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT13_DL0_UNUSED_31_8_MAX (0x00FFFFFFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT13_DL0_BIST_IDLE_TIME_MASK (0x000000FFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT13_DL0_BIST_IDLE_TIME_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT13_DL0_BIST_IDLE_TIME_MAX (0x000000FFU)
+
+/* DL0_TX_DIG_TBIT14 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT14_DL0_BIST_PKT4_MASK (0xFF000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT14_DL0_BIST_PKT4_SHIFT (0x00000018U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT14_DL0_BIST_PKT4_MAX (0x000000FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT14_DL0_BIST_PKT3_MASK (0x00FF0000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT14_DL0_BIST_PKT3_SHIFT (0x00000010U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT14_DL0_BIST_PKT3_MAX (0x000000FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT14_DL0_BIST_PKT2_MASK (0x0000FF00U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT14_DL0_BIST_PKT2_SHIFT (0x00000008U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT14_DL0_BIST_PKT2_MAX (0x000000FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT14_DL0_BIST_PKT1_MASK (0x000000FFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT14_DL0_BIST_PKT1_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT14_DL0_BIST_PKT1_MAX (0x000000FFU)
+
+/* DL0_TX_DIG_TBIT15 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT15_DL0_BIST_LFSR_FREEZE_MASK (0x00002000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT15_DL0_BIST_LFSR_FREEZE_SHIFT (0x0000000DU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT15_DL0_BIST_LFSR_FREEZE_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT15_DL0_BIST_ERR_INJ_POINT_MASK (0x00001FFEU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT15_DL0_BIST_ERR_INJ_POINT_SHIFT (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT15_DL0_BIST_ERR_INJ_POINT_MAX (0x00000FFFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT15_DL0_BIST_ERR_INJ_EN_MASK (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT15_DL0_BIST_ERR_INJ_EN_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT15_DL0_BIST_ERR_INJ_EN_MAX (0x00000001U)
+
+/* DL0_TX_DIG_TBIT16 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT16_DL0_DIG_TBIT16_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT16_DL0_DIG_TBIT16_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT16_DL0_DIG_TBIT16_MAX (0xFFFFFFFFU)
+
+/* DL0_TX_DIG_TBIT17 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT17_DL0_DIG_TBIT17_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT17_DL0_DIG_TBIT17_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT17_DL0_DIG_TBIT17_MAX (0xFFFFFFFFU)
+
+/* DL0_TX_DIG_TBIT18 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT18_DL0_DIG_TBIT18_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT18_DL0_DIG_TBIT18_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT18_DL0_DIG_TBIT18_MAX (0xFFFFFFFFU)
+
+/* DL0_TX_DIG_TBIT19 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT19_DL0_DIG_TBIT19_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT19_DL0_DIG_TBIT19_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT19_DL0_DIG_TBIT19_MAX (0xFFFFFFFFU)
+
+/* DL0_TX_DIG_TBIT20 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT20_DL0_TM_ISO_EN_MASK (0x80000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT20_DL0_TM_ISO_EN_SHIFT (0x0000001FU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT20_DL0_TM_ISO_EN_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT20_DL0_TM_LOAD_DPDN_SEL_MASK (0x40000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT20_DL0_TM_LOAD_DPDN_SEL_SHIFT (0x0000001EU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT20_DL0_TM_LOAD_DPDN_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT20_DL0_TM_LOAD_DPDN_MASK (0x38000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT20_DL0_TM_LOAD_DPDN_SHIFT (0x0000001BU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT20_DL0_TM_LOAD_DPDN_MAX (0x00000007U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT20_DL0_TM_HSTX_DATA_RATE_SEL_MASK (0x04000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT20_DL0_TM_HSTX_DATA_RATE_SEL_SHIFT (0x0000001AU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT20_DL0_TM_HSTX_DATA_RATE_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT20_DL0_TM_HSTX_DATE_RATE_MASK (0x03000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT20_DL0_TM_HSTX_DATE_RATE_SHIFT (0x00000018U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT20_DL0_TM_HSTX_DATE_RATE_MAX (0x00000003U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT20_DL0_TM_BIST_ULP_RCV_EN_SEL_MASK (0x00800000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT20_DL0_TM_BIST_ULP_RCV_EN_SEL_SHIFT (0x00000017U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT20_DL0_TM_BIST_ULP_RCV_EN_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT20_DL0_TM_BIST_ULP_RCV_EN_MASK (0x00400000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT20_DL0_TM_BIST_ULP_RCV_EN_SHIFT (0x00000016U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT20_DL0_TM_BIST_ULP_RCV_EN_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT20_DL0_TM_ULPS_PULDN_SEL_MASK (0x00200000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT20_DL0_TM_ULPS_PULDN_SEL_SHIFT (0x00000015U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT20_DL0_TM_ULPS_PULDN_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT20_DL0_TM_ULPS_PULDN_MASK (0x00100000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT20_DL0_TM_ULPS_PULDN_SHIFT (0x00000014U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT20_DL0_TM_ULPS_PULDN_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT20_DL0_TM_BIST_SMPLR_CLK_EDGE_SEL_MASK (0x00080000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT20_DL0_TM_BIST_SMPLR_CLK_EDGE_SEL_SHIFT (0x00000013U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT20_DL0_TM_BIST_SMPLR_CLK_EDGE_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT20_DL0_TM_BIST_SMPLR_CLK_EDGE_MASK (0x00040000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT20_DL0_TM_BIST_SMPLR_CLK_EDGE_SHIFT (0x00000012U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT20_DL0_TM_BIST_SMPLR_CLK_EDGE_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT20_DL0_TM_BIST_EN_SEL_MASK (0x00020000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT20_DL0_TM_BIST_EN_SEL_SHIFT (0x00000011U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT20_DL0_TM_BIST_EN_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT20_DL0_TM_BIST_EN_MASK (0x00010000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT20_DL0_TM_BIST_EN_SHIFT (0x00000010U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT20_DL0_TM_BIST_EN_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT20_DL0_TM_LPTX_TRST_SEL_MASK (0x00008000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT20_DL0_TM_LPTX_TRST_SEL_SHIFT (0x0000000FU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT20_DL0_TM_LPTX_TRST_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT20_DL0_TM_LPTX_TRST_MASK (0x00004000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT20_DL0_TM_LPTX_TRST_SHIFT (0x0000000EU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT20_DL0_TM_LPTX_TRST_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT20_DL0_TM_LPTX_RST_SEL_MASK (0x00002000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT20_DL0_TM_LPTX_RST_SEL_SHIFT (0x0000000DU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT20_DL0_TM_LPTX_RST_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT20_DL0_TM_LPTX_RST_MASK (0x00001000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT20_DL0_TM_LPTX_RST_SHIFT (0x0000000CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT20_DL0_TM_LPTX_RST_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT20_DL0_TM_LPTX_DP_SEL_MASK (0x00000800U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT20_DL0_TM_LPTX_DP_SEL_SHIFT (0x0000000BU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT20_DL0_TM_LPTX_DP_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT20_DL0_TM_LPTX_DP_MASK (0x00000400U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT20_DL0_TM_LPTX_DP_SHIFT (0x0000000AU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT20_DL0_TM_LPTX_DP_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT20_DL0_TM_LPTX_DN_SEL_MASK (0x00000200U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT20_DL0_TM_LPTX_DN_SEL_SHIFT (0x00000009U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT20_DL0_TM_LPTX_DN_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT20_DL0_TM_LPTX_DN_MASK (0x00000100U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT20_DL0_TM_LPTX_DN_SHIFT (0x00000008U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT20_DL0_TM_LPTX_DN_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT20_DL0_TM_LDO_REF_EN_SEL_MASK (0x00000080U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT20_DL0_TM_LDO_REF_EN_SEL_SHIFT (0x00000007U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT20_DL0_TM_LDO_REF_EN_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT20_DL0_TM_LDO_REF_EN_MASK (0x00000040U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT20_DL0_TM_LDO_REF_EN_SHIFT (0x00000006U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT20_DL0_TM_LDO_REF_EN_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT20_DL0_TM_HSTX_TRST_SEL_MASK (0x00000020U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT20_DL0_TM_HSTX_TRST_SEL_SHIFT (0x00000005U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT20_DL0_TM_HSTX_TRST_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT20_DL0_TM_HSTX_TRST_MASK (0x00000010U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT20_DL0_TM_HSTX_TRST_SHIFT (0x00000004U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT20_DL0_TM_HSTX_TRST_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT20_DL0_TM_HSTX_RQST_SEL_MASK (0x00000008U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT20_DL0_TM_HSTX_RQST_SEL_SHIFT (0x00000003U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT20_DL0_TM_HSTX_RQST_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT20_DL0_TM_HSTX_RQST_MASK (0x00000004U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT20_DL0_TM_HSTX_RQST_SHIFT (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT20_DL0_TM_HSTX_RQST_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT20_DL0_TM_GLOBAL_PD_SEL_MASK (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT20_DL0_TM_GLOBAL_PD_SEL_SHIFT (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT20_DL0_TM_GLOBAL_PD_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT20_DL0_TM_GLOBAL_PD_MASK (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT20_DL0_TM_GLOBAL_PD_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT20_DL0_TM_GLOBAL_PD_MAX (0x00000001U)
+
+/* DL0_TX_DIG_TBIT21 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT21_DL0_TM_SERSYNTH_RST_N_SEL_MASK (0x00004000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT21_DL0_TM_SERSYNTH_RST_N_SEL_SHIFT (0x0000000EU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT21_DL0_TM_SERSYNTH_RST_N_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT21_DL0_TM_SERSYNTH_RST_N_MASK (0x00002000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT21_DL0_TM_SERSYNTH_RST_N_SHIFT (0x0000000DU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT21_DL0_TM_SERSYNTH_RST_N_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT21_DL0_TM_SWAP_DPDN_SEL_MASK (0x00001000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT21_DL0_TM_SWAP_DPDN_SEL_SHIFT (0x0000000CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT21_DL0_TM_SWAP_DPDN_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT21_DL0_TM_SWAP_DPDN_EN_MASK (0x00000800U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT21_DL0_TM_SWAP_DPDN_EN_SHIFT (0x0000000BU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT21_DL0_TM_SWAP_DPDN_EN_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT21_DL0_TM_SERSYNTH_EN_SEL_MASK (0x00000400U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT21_DL0_TM_SERSYNTH_EN_SEL_SHIFT (0x0000000AU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT21_DL0_TM_SERSYNTH_EN_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT21_DL0_TM_SERSYNTH_EN_MASK (0x00000200U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT21_DL0_TM_SERSYNTH_EN_SHIFT (0x00000009U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT21_DL0_TM_SERSYNTH_EN_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT21_DL0_TM_TX_DATA_HS_SEL_MASK (0x00000100U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT21_DL0_TM_TX_DATA_HS_SEL_SHIFT (0x00000008U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT21_DL0_TM_TX_DATA_HS_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT21_DL0_TM_TX_DATA_HS_MASK (0x000000FFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT21_DL0_TM_TX_DATA_HS_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT21_DL0_TM_TX_DATA_HS_MAX (0x000000FFU)
+
+/* DL0_TX_DIG_TBIT22 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT22_DL0_DIG_TBIT22_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT22_DL0_DIG_TBIT22_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT22_DL0_DIG_TBIT22_MAX (0xFFFFFFFFU)
+
+/* DL0_TX_DIG_TBIT23 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT23_DL0_DIG_TBIT23_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT23_DL0_DIG_TBIT23_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT23_DL0_DIG_TBIT23_MAX (0xFFFFFFFFU)
+
+/* DL0_TX_DIG_TBIT24 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT24_DL0_DIG_TBIT24_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT24_DL0_DIG_TBIT24_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT24_DL0_DIG_TBIT24_MAX (0xFFFFFFFFU)
+
+/* DL0_TX_ANA_TBIT5 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_ANA_TBIT5_DL0_ANA_TBIT5_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_ANA_TBIT5_DL0_ANA_TBIT5_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_ANA_TBIT5_DL0_ANA_TBIT5_MAX (0xFFFFFFFFU)
+
+/* DL0_TX_DIG_TBIT25 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT25_DL0_ANA_CTRL_FSM_STATE_MASK (0x001F0000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT25_DL0_ANA_CTRL_FSM_STATE_SHIFT (0x00000010U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT25_DL0_ANA_CTRL_FSM_STATE_MAX (0x0000001FU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT25_DL0_BIST_BAL_STATUS_MASK (0x0000FFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT25_DL0_BIST_BAL_STATUS_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT25_DL0_BIST_BAL_STATUS_MAX (0x0000FFFFU)
+
+/* DL0_TX_DIG_TBIT26 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT26_DL0_TM_DATA_ESC_RX_FSM_STATE_MASK (0xF8000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT26_DL0_TM_DATA_ESC_RX_FSM_STATE_SHIFT (0x0000001BU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT26_DL0_TM_DATA_ESC_RX_FSM_STATE_MAX (0x0000001FU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT26_DL0_TM_DATA_ESCTX_CTRL_FSM_STATE_MASK (0x07FE0000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT26_DL0_TM_DATA_ESCTX_CTRL_FSM_STATE_SHIFT (0x00000011U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT26_DL0_TM_DATA_ESCTX_CTRL_FSM_STATE_MAX (0x000003FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT26_DL0_TM_DATA_ESCTX_DATA_FSM_STATE_MASK (0x0001F000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT26_DL0_TM_DATA_ESCTX_DATA_FSM_STATE_SHIFT (0x0000000CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT26_DL0_TM_DATA_ESCTX_DATA_FSM_STATE_MAX (0x0000001FU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT26_DL0_TM_HS_PATH_FSM_STATE_MASK (0x00000FFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT26_DL0_TM_HS_PATH_FSM_STATE_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT26_DL0_TM_HS_PATH_FSM_STATE_MAX (0x00000FFFU)
+
+/* DL0_TX_DIG_TBIT28 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT28_DL0_TM_ANA_COMP_OUTS_MASK (0x0000FF00U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT28_DL0_TM_ANA_COMP_OUTS_SHIFT (0x00000008U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT28_DL0_TM_ANA_COMP_OUTS_MAX (0x000000FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT28_DL0_UNUSED_7_0_MASK (0x000000FFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT28_DL0_UNUSED_7_0_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT28_DL0_UNUSED_7_0_MAX (0x000000FFU)
+
+/* DL0_TX_DIG_TBIT29 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT29_DL0_TM_CUR_STATE_ULPTX_CHE_MASK (0x03000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT29_DL0_TM_CUR_STATE_ULPTX_CHE_SHIFT (0x00000018U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT29_DL0_TM_CUR_STATE_ULPTX_CHE_MAX (0x00000003U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT29_DL0_TM_CUR_STATE_ULPRX_CHE_MASK (0x00E00000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT29_DL0_TM_CUR_STATE_ULPRX_CHE_SHIFT (0x00000015U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT29_DL0_TM_CUR_STATE_ULPRX_CHE_MAX (0x00000007U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT29_DL0_TM_CUR_STATE_LPCD_CHE_MASK (0x001C0000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT29_DL0_TM_CUR_STATE_LPCD_CHE_SHIFT (0x00000012U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT29_DL0_TM_CUR_STATE_LPCD_CHE_MAX (0x00000007U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT29_DL0_TM_CUR_STATE_LPRX_CHE_MASK (0x00038000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT29_DL0_TM_CUR_STATE_LPRX_CHE_SHIFT (0x0000000FU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT29_DL0_TM_CUR_STATE_LPRX_CHE_MAX (0x00000007U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT29_DL0_TM_CUR_STATE_CTRLR_MASK (0x00007800U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT29_DL0_TM_CUR_STATE_CTRLR_SHIFT (0x0000000BU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT29_DL0_TM_CUR_STATE_CTRLR_MAX (0x0000000FU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT29_DL0_BIST_DATA_LANE_PASS_MASK (0x00000400U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT29_DL0_BIST_DATA_LANE_PASS_SHIFT (0x0000000AU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT29_DL0_BIST_DATA_LANE_PASS_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT29_DL0_BIST_LPRX_PASS_MASK (0x00000200U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT29_DL0_BIST_LPRX_PASS_SHIFT (0x00000009U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT29_DL0_BIST_LPRX_PASS_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT29_DL0_BIST_LPCD_PASS_MASK (0x00000100U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT29_DL0_BIST_LPCD_PASS_SHIFT (0x00000008U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT29_DL0_BIST_LPCD_PASS_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT29_DL0_BIST_ULPRX_PASS_MASK (0x00000080U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT29_DL0_BIST_ULPRX_PASS_SHIFT (0x00000007U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT29_DL0_BIST_ULPRX_PASS_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT29_DL0_BIST_ULPTX_PASS_MASK (0x00000040U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT29_DL0_BIST_ULPTX_PASS_SHIFT (0x00000006U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT29_DL0_BIST_ULPTX_PASS_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT29_DL0_BIST_HS_NEG_ERR_MASK (0x00000020U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT29_DL0_BIST_HS_NEG_ERR_SHIFT (0x00000005U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT29_DL0_BIST_HS_NEG_ERR_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT29_DL0_BIST_HS_POS_ERR_MASK (0x00000010U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT29_DL0_BIST_HS_POS_ERR_SHIFT (0x00000004U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT29_DL0_BIST_HS_POS_ERR_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT29_DL0_BIST_POS_SYNC_MASK (0x00000008U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT29_DL0_BIST_POS_SYNC_SHIFT (0x00000003U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT29_DL0_BIST_POS_SYNC_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT29_DL0_BIST_NEG_SYNC_MASK (0x00000004U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT29_DL0_BIST_NEG_SYNC_SHIFT (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT29_DL0_BIST_NEG_SYNC_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT29_DL0_BIST_CMPLT_MASK (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT29_DL0_BIST_CMPLT_SHIFT (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT29_DL0_BIST_CMPLT_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT29_DL0_BIST_EN_STATUS_MASK (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT29_DL0_BIST_EN_STATUS_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT29_DL0_BIST_EN_STATUS_MAX (0x00000001U)
+
+/* DL0_TX_DIG_TBIT30 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT30_DL0_BIST_PAT_CHE_PKT_CNT_NEG_MASK (0xFFFF0000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT30_DL0_BIST_PAT_CHE_PKT_CNT_NEG_SHIFT (0x00000010U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT30_DL0_BIST_PAT_CHE_PKT_CNT_NEG_MAX (0x0000FFFFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT30_DL0_BIST_PAT_CHE_PKT_CNT_POS_MASK (0x0000FFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT30_DL0_BIST_PAT_CHE_PKT_CNT_POS_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT30_DL0_BIST_PAT_CHE_PKT_CNT_POS_MAX (0x0000FFFFU)
+
+/* DL0_TX_DIG_TBIT31 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT31_DL0_BIST_PAT_CHE_ERR_CNT_NEG_MASK (0xFFFF0000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT31_DL0_BIST_PAT_CHE_ERR_CNT_NEG_SHIFT (0x00000010U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT31_DL0_BIST_PAT_CHE_ERR_CNT_NEG_MAX (0x0000FFFFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT31_DL0_BIST_PAT_CHE_ERR_CNT_POS_MASK (0x0000FFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT31_DL0_BIST_PAT_CHE_ERR_CNT_POS_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT31_DL0_BIST_PAT_CHE_ERR_CNT_POS_MAX (0x0000FFFFU)
+
+/* DL0_TX_DIG_TBIT32 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT32_DL0_DIG_TBIT32_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT32_DL0_DIG_TBIT32_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT32_DL0_DIG_TBIT32_MAX (0xFFFFFFFFU)
+
+/* DL0_TX_DIG_TBIT33 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT33_DL0_DIG_TBIT33_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT33_DL0_DIG_TBIT33_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT33_DL0_DIG_TBIT33_MAX (0xFFFFFFFFU)
+
+/* DL0_TX_DIG_TBIT34 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT34_DL0_DIG_TBIT34_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT34_DL0_DIG_TBIT34_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT34_DL0_DIG_TBIT34_MAX (0xFFFFFFFFU)
+
+/* DL0_TX_DIG_TBIT35 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT35_DL0_DIG_TBIT35_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT35_DL0_DIG_TBIT35_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT35_DL0_DIG_TBIT35_MAX (0xFFFFFFFFU)
+
+/* DL0_TX_DIG_TBIT36 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT36_DL0_DIG_TBIT36_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT36_DL0_DIG_TBIT36_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL0_TX_DIG_TBIT36_DL0_DIG_TBIT36_MAX (0xFFFFFFFFU)
+
+/* DL1_TX_ANA_TBIT0 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_ANA_TBIT0_DL1_ANA_TBIT0_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_ANA_TBIT0_DL1_ANA_TBIT0_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_ANA_TBIT0_DL1_ANA_TBIT0_MAX (0xFFFFFFFFU)
+
+/* DL1_TX_ANA_TBIT1 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_ANA_TBIT1_DL1_ANA_TBIT1_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_ANA_TBIT1_DL1_ANA_TBIT1_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_ANA_TBIT1_DL1_ANA_TBIT1_MAX (0xFFFFFFFFU)
+
+/* DL1_TX_ANA_TBIT2 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_ANA_TBIT2_DL1_ANA_TBIT2_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_ANA_TBIT2_DL1_ANA_TBIT2_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_ANA_TBIT2_DL1_ANA_TBIT2_MAX (0xFFFFFFFFU)
+
+/* DL1_TX_ANA_TBIT3 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_ANA_TBIT3_DL1_ANA_TBIT3_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_ANA_TBIT3_DL1_ANA_TBIT3_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_ANA_TBIT3_DL1_ANA_TBIT3_MAX (0xFFFFFFFFU)
+
+/* DL1_TX_ANA_TBIT4 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_ANA_TBIT4_DL1_ANA_TBIT4_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_ANA_TBIT4_DL1_ANA_TBIT4_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_ANA_TBIT4_DL1_ANA_TBIT4_MAX (0xFFFFFFFFU)
+
+/* DL1_TX_DIG_TBIT0 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT0_DL1_UNUSED_31_13_MASK (0xFFFFE000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT0_DL1_UNUSED_31_13_SHIFT (0x0000000DU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT0_DL1_UNUSED_31_13_MAX (0x0007FFFFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT0_DL1_ULPS_PULLDN_CNT_MASK (0x00001F00U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT0_DL1_ULPS_PULLDN_CNT_SHIFT (0x00000008U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT0_DL1_ULPS_PULLDN_CNT_MAX (0x0000001FU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT0_DL1_UNUSED_7_5_MASK (0x000000E0U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT0_DL1_UNUSED_7_5_SHIFT (0x00000005U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT0_DL1_UNUSED_7_5_MAX (0x00000007U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT0_DL1_LDO_EN_CNT_MASK (0x0000001FU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT0_DL1_LDO_EN_CNT_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT0_DL1_LDO_EN_CNT_MAX (0x0000001FU)
+
+/* DL1_TX_DIG_TBIT1 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT1_DL1_TEST_LPTX_DP_MASK (0x00200000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT1_DL1_TEST_LPTX_DP_SHIFT (0x00000015U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT1_DL1_TEST_LPTX_DP_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT1_DL1_TEST_LPTX_DN_MASK (0x00100000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT1_DL1_TEST_LPTX_DN_SHIFT (0x00000014U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT1_DL1_TEST_LPTX_DN_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT1_DL1_TEST_LPTX_EN_MASK (0x00080000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT1_DL1_TEST_LPTX_EN_SHIFT (0x00000013U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT1_DL1_TEST_LPTX_EN_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT1_DL1_TM_READY_SKEW_CAL_MASK (0x00040000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT1_DL1_TM_READY_SKEW_CAL_SHIFT (0x00000012U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT1_DL1_TM_READY_SKEW_CAL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT1_DL1_TM_HS_PREP_HAFCYC_OVERRIDE_MASK (0x00020000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT1_DL1_TM_HS_PREP_HAFCYC_OVERRIDE_SHIFT (0x00000011U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT1_DL1_TM_HS_PREP_HAFCYC_OVERRIDE_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT1_DL1_TM_HS_PREP_HSFCYC_MASK (0x00010000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT1_DL1_TM_HS_PREP_HSFCYC_SHIFT (0x00000010U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT1_DL1_TM_HS_PREP_HSFCYC_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT1_DL1_HS_TRAIL_OFFSET_MASK (0x0000F000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT1_DL1_HS_TRAIL_OFFSET_SHIFT (0x0000000CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT1_DL1_HS_TRAIL_OFFSET_MAX (0x0000000FU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT1_DL1_HS_ZERO_OFFSET_MASK (0x00000F00U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT1_DL1_HS_ZERO_OFFSET_SHIFT (0x00000008U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT1_DL1_HS_ZERO_OFFSET_MAX (0x0000000FU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT1_DL1_HS_PREP_OFFSET_MASK (0x000000F0U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT1_DL1_HS_PREP_OFFSET_SHIFT (0x00000004U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT1_DL1_HS_PREP_OFFSET_MAX (0x0000000FU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT1_DL1_HS_TLPX_OFFSET_MASK (0x0000000FU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT1_DL1_HS_TLPX_OFFSET_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT1_DL1_HS_TLPX_OFFSET_MAX (0x0000000FU)
+
+/* DL1_TX_DIG_TBIT2 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT2_DL1_TM_SKEW_CAL_SEQ_MASK (0x07F80000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT2_DL1_TM_SKEW_CAL_SEQ_SHIFT (0x00000013U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT2_DL1_TM_SKEW_CAL_SEQ_MAX (0x000000FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT2_DL1_TM_SKEW_CAL_SEQ_SEL_MASK (0x00040000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT2_DL1_TM_SKEW_CAL_SEQ_SEL_SHIFT (0x00000012U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT2_DL1_TM_SKEW_CAL_SEQ_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT2_DL1_TM_SKEW_CAL_SYNC_PKT_MASK (0x0003FC00U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT2_DL1_TM_SKEW_CAL_SYNC_PKT_SHIFT (0x0000000AU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT2_DL1_TM_SKEW_CAL_SYNC_PKT_MAX (0x000000FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT2_DL1_TM_SKEW_CAL_SYNC_PKT_SEL_MASK (0x00000200U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT2_DL1_TM_SKEW_CAL_SYNC_PKT_SEL_SHIFT (0x00000009U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT2_DL1_TM_SKEW_CAL_SYNC_PKT_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT2_DL1_TM_HS_SYNC_PKT_MASK (0x000001FEU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT2_DL1_TM_HS_SYNC_PKT_SHIFT (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT2_DL1_TM_HS_SYNC_PKT_MAX (0x000000FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT2_DL1_TM_HS_SYNC_PKT_SEL_MASK (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT2_DL1_TM_HS_SYNC_PKT_SEL_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT2_DL1_TM_HS_SYNC_PKT_SEL_MAX (0x00000001U)
+
+/* DL1_TX_DIG_TBIT3 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT3_DL1_SERSYNTH_LOOPBACK_MASK (0x00000020U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT3_DL1_SERSYNTH_LOOPBACK_SHIFT (0x00000005U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT3_DL1_SERSYNTH_LOOPBACK_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT3_DL1_BAL_FORCE_STATE_MASK (0x0000001CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT3_DL1_BAL_FORCE_STATE_SHIFT (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT3_DL1_BAL_FORCE_STATE_MAX (0x00000007U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT3_DL1_BAL_FORCE_EN_MASK (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT3_DL1_BAL_FORCE_EN_SHIFT (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT3_DL1_BAL_FORCE_EN_MAX (0x00000001U)
+
+/* DL1_TX_DIG_TBIT4 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT4_DL1_CONTENTION_EN_MASK (0x00008000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT4_DL1_CONTENTION_EN_SHIFT (0x0000000FU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT4_DL1_CONTENTION_EN_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT4_DL1_UNUSED_14_13_MASK (0x00006000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT4_DL1_UNUSED_14_13_SHIFT (0x0000000DU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT4_DL1_UNUSED_14_13_MAX (0x00000003U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT4_DL1_FORCE_RX_MODE_MASK (0x00001000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT4_DL1_FORCE_RX_MODE_SHIFT (0x0000000CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT4_DL1_FORCE_RX_MODE_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT4_DL1_TEST_DATA_LPTX_DP_SEL_MASK (0x00000800U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT4_DL1_TEST_DATA_LPTX_DP_SEL_SHIFT (0x0000000BU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT4_DL1_TEST_DATA_LPTX_DP_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT4_DL1_TEST_DATA_LPTX_DN_SEL_MASK (0x00000400U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT4_DL1_TEST_DATA_LPTX_DN_SEL_SHIFT (0x0000000AU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT4_DL1_TEST_DATA_LPTX_DN_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT4_DL1_TEST_DATA_LPTX_MASK (0x000003FCU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT4_DL1_TEST_DATA_LPTX_SHIFT (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT4_DL1_TEST_DATA_LPTX_MAX (0x000000FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT4_DL1_TEST_DATA_LPTX_RSTN_MASK (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT4_DL1_TEST_DATA_LPTX_RSTN_SHIFT (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT4_DL1_TEST_DATA_LPTX_RSTN_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT4_DL1_TEST_DATA_LPTX_EN_MASK (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT4_DL1_TEST_DATA_LPTX_EN_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT4_DL1_TEST_DATA_LPTX_EN_MAX (0x00000001U)
+
+/* DL1_TX_DIG_TBIT5 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT5_DL1_DIG_TBIT5_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT5_DL1_DIG_TBIT5_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT5_DL1_DIG_TBIT5_MAX (0xFFFFFFFFU)
+
+/* DL1_TX_DIG_TBIT6 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT6_DL1_DIG_TBIT6_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT6_DL1_DIG_TBIT6_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT6_DL1_DIG_TBIT6_MAX (0xFFFFFFFFU)
+
+/* DL1_TX_DIG_TBIT7 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT7_DL1_DIG_TBIT7_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT7_DL1_DIG_TBIT7_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT7_DL1_DIG_TBIT7_MAX (0xFFFFFFFFU)
+
+/* DL1_TX_DIG_TBIT8 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT8_DL1_DIG_TBIT8_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT8_DL1_DIG_TBIT8_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT8_DL1_DIG_TBIT8_MAX (0xFFFFFFFFU)
+
+/* DL1_TX_DIG_TBIT9 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT9_DL1_DIG_TBIT9_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT9_DL1_DIG_TBIT9_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT9_DL1_DIG_TBIT9_MAX (0xFFFFFFFFU)
+
+/* DL1_TX_DIG_TBIT10 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT10_DL1_BIST_WAIT_TIME_MASK (0x01E00000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT10_DL1_BIST_WAIT_TIME_SHIFT (0x00000015U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT10_DL1_BIST_WAIT_TIME_MAX (0x0000000FU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT10_DL1_BIST_ULPTX_TEST_TIME_MASK (0x001FE000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT10_DL1_BIST_ULPTX_TEST_TIME_SHIFT (0x0000000DU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT10_DL1_BIST_ULPTX_TEST_TIME_MAX (0x000000FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT10_DL1_BIST_SEND_CONFIG_MASK (0x00001800U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT10_DL1_BIST_SEND_CONFIG_SHIFT (0x0000000BU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT10_DL1_BIST_SEND_CONFIG_MAX (0x00000003U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT10_DL1_BIST_DIG_TO_DIG_LOOPBK_MASK (0x00000400U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT10_DL1_BIST_DIG_TO_DIG_LOOPBK_SHIFT (0x0000000AU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT10_DL1_BIST_DIG_TO_DIG_LOOPBK_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT10_DL1_BIST_RUN_NEGEDGE_FIRST_MASK (0x00000200U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT10_DL1_BIST_RUN_NEGEDGE_FIRST_SHIFT (0x00000009U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT10_DL1_BIST_RUN_NEGEDGE_FIRST_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT10_DL1_BIST_LENGTH_OF_DESKEW_MASK (0x000001FCU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT10_DL1_BIST_LENGTH_OF_DESKEW_SHIFT (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT10_DL1_BIST_LENGTH_OF_DESKEW_MAX (0x0000007FU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT10_DL1_BIST_LOOPBK_MODE_MASK (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT10_DL1_BIST_LOOPBK_MODE_SHIFT (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT10_DL1_BIST_LOOPBK_MODE_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT10_DL1_BIST_EN_MASK (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT10_DL1_BIST_EN_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT10_DL1_BIST_EN_MAX (0x00000001U)
+
+/* DL1_TX_DIG_TBIT11 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT11_DL1_BIST_FRM_IDLE_TIME_MASK (0xFF000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT11_DL1_BIST_FRM_IDLE_TIME_SHIFT (0x00000018U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT11_DL1_BIST_FRM_IDLE_TIME_MAX (0x000000FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT11_DL1_BIST_PKT_NUM_MASK (0x00FF0000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT11_DL1_BIST_PKT_NUM_SHIFT (0x00000010U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT11_DL1_BIST_PKT_NUM_MAX (0x000000FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT11_DL1_BIST_INF_MODE_MASK (0x00008000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT11_DL1_BIST_INF_MODE_SHIFT (0x0000000FU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT11_DL1_BIST_INF_MODE_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT11_DL1_BIST_FRM_NUM_MASK (0x00007F80U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT11_DL1_BIST_FRM_NUM_SHIFT (0x00000007U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT11_DL1_BIST_FRM_NUM_MAX (0x000000FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT11_DL1_BIST_CLEAR_MASK (0x00000040U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT11_DL1_BIST_CLEAR_SHIFT (0x00000006U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT11_DL1_BIST_CLEAR_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT11_DL1_BIST_PRBS_MASK (0x00000030U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT11_DL1_BIST_PRBS_SHIFT (0x00000004U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT11_DL1_BIST_PRBS_MAX (0x00000003U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT11_DL1_BIST_TEST_MODE_MASK (0x0000000EU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT11_DL1_BIST_TEST_MODE_SHIFT (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT11_DL1_BIST_TEST_MODE_MAX (0x00000007U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT11_DL1_UNUSED_0_MASK (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT11_DL1_UNUSED_0_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT11_DL1_UNUSED_0_MAX (0x00000001U)
+
+/* DL1_TX_DIG_TBIT12 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT12_DL1_BIST_RUN_LENGTH_MASK (0x00000FFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT12_DL1_BIST_RUN_LENGTH_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT12_DL1_BIST_RUN_LENGTH_MAX (0x00000FFFU)
+
+/* DL1_TX_DIG_TBIT13 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT13_DL1_UNUSED_31_8_MASK (0xFFFFFF00U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT13_DL1_UNUSED_31_8_SHIFT (0x00000008U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT13_DL1_UNUSED_31_8_MAX (0x00FFFFFFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT13_DL1_BIST_IDLE_TIME_MASK (0x000000FFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT13_DL1_BIST_IDLE_TIME_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT13_DL1_BIST_IDLE_TIME_MAX (0x000000FFU)
+
+/* DL1_TX_DIG_TBIT14 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT14_DL1_BIST_PKT4_MASK (0xFF000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT14_DL1_BIST_PKT4_SHIFT (0x00000018U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT14_DL1_BIST_PKT4_MAX (0x000000FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT14_DL1_BIST_PKT3_MASK (0x00FF0000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT14_DL1_BIST_PKT3_SHIFT (0x00000010U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT14_DL1_BIST_PKT3_MAX (0x000000FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT14_DL1_BIST_PKT2_MASK (0x0000FF00U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT14_DL1_BIST_PKT2_SHIFT (0x00000008U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT14_DL1_BIST_PKT2_MAX (0x000000FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT14_DL1_BIST_PKT1_MASK (0x000000FFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT14_DL1_BIST_PKT1_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT14_DL1_BIST_PKT1_MAX (0x000000FFU)
+
+/* DL1_TX_DIG_TBIT15 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT15_DL1_BIST_LFSR_FREEZE_MASK (0x00002000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT15_DL1_BIST_LFSR_FREEZE_SHIFT (0x0000000DU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT15_DL1_BIST_LFSR_FREEZE_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT15_DL1_BIST_ERR_INJ_POINT_MASK (0x00001FFEU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT15_DL1_BIST_ERR_INJ_POINT_SHIFT (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT15_DL1_BIST_ERR_INJ_POINT_MAX (0x00000FFFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT15_DL1_BIST_ERR_INJ_EN_MASK (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT15_DL1_BIST_ERR_INJ_EN_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT15_DL1_BIST_ERR_INJ_EN_MAX (0x00000001U)
+
+/* DL1_TX_DIG_TBIT16 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT16_DL1_DIG_TBIT16_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT16_DL1_DIG_TBIT16_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT16_DL1_DIG_TBIT16_MAX (0xFFFFFFFFU)
+
+/* DL1_TX_DIG_TBIT17 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT17_DL1_DIG_TBIT17_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT17_DL1_DIG_TBIT17_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT17_DL1_DIG_TBIT17_MAX (0xFFFFFFFFU)
+
+/* DL1_TX_DIG_TBIT18 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT18_DL1_DIG_TBIT18_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT18_DL1_DIG_TBIT18_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT18_DL1_DIG_TBIT18_MAX (0xFFFFFFFFU)
+
+/* DL1_TX_DIG_TBIT19 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT19_DL1_DIG_TBIT19_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT19_DL1_DIG_TBIT19_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT19_DL1_DIG_TBIT19_MAX (0xFFFFFFFFU)
+
+/* DL1_TX_DIG_TBIT20 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT20_DL1_TM_ISO_EN_MASK (0x80000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT20_DL1_TM_ISO_EN_SHIFT (0x0000001FU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT20_DL1_TM_ISO_EN_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT20_DL1_TM_LOAD_DPDN_SEL_MASK (0x40000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT20_DL1_TM_LOAD_DPDN_SEL_SHIFT (0x0000001EU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT20_DL1_TM_LOAD_DPDN_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT20_DL1_TM_LOAD_DPDN_MASK (0x38000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT20_DL1_TM_LOAD_DPDN_SHIFT (0x0000001BU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT20_DL1_TM_LOAD_DPDN_MAX (0x00000007U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT20_DL1_TM_HSTX_DATA_RATE_SEL_MASK (0x04000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT20_DL1_TM_HSTX_DATA_RATE_SEL_SHIFT (0x0000001AU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT20_DL1_TM_HSTX_DATA_RATE_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT20_DL1_TM_HSTX_DATE_RATE_MASK (0x03000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT20_DL1_TM_HSTX_DATE_RATE_SHIFT (0x00000018U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT20_DL1_TM_HSTX_DATE_RATE_MAX (0x00000003U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT20_DL1_TM_BIST_ULP_RCV_EN_SEL_MASK (0x00800000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT20_DL1_TM_BIST_ULP_RCV_EN_SEL_SHIFT (0x00000017U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT20_DL1_TM_BIST_ULP_RCV_EN_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT20_DL1_TM_BIST_ULP_RCV_EN_MASK (0x00400000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT20_DL1_TM_BIST_ULP_RCV_EN_SHIFT (0x00000016U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT20_DL1_TM_BIST_ULP_RCV_EN_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT20_DL1_TM_ULPS_PULDN_SEL_MASK (0x00200000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT20_DL1_TM_ULPS_PULDN_SEL_SHIFT (0x00000015U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT20_DL1_TM_ULPS_PULDN_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT20_DL1_TM_ULPS_PULDN_MASK (0x00100000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT20_DL1_TM_ULPS_PULDN_SHIFT (0x00000014U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT20_DL1_TM_ULPS_PULDN_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT20_DL1_TM_BIST_SMPLR_CLK_EDGE_SEL_MASK (0x00080000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT20_DL1_TM_BIST_SMPLR_CLK_EDGE_SEL_SHIFT (0x00000013U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT20_DL1_TM_BIST_SMPLR_CLK_EDGE_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT20_DL1_TM_BIST_SMPLR_CLK_EDGE_MASK (0x00040000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT20_DL1_TM_BIST_SMPLR_CLK_EDGE_SHIFT (0x00000012U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT20_DL1_TM_BIST_SMPLR_CLK_EDGE_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT20_DL1_TM_BIST_EN_SEL_MASK (0x00020000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT20_DL1_TM_BIST_EN_SEL_SHIFT (0x00000011U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT20_DL1_TM_BIST_EN_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT20_DL1_TM_BIST_EN_MASK (0x00010000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT20_DL1_TM_BIST_EN_SHIFT (0x00000010U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT20_DL1_TM_BIST_EN_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT20_DL1_TM_LPTX_TRST_SEL_MASK (0x00008000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT20_DL1_TM_LPTX_TRST_SEL_SHIFT (0x0000000FU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT20_DL1_TM_LPTX_TRST_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT20_DL1_TM_LPTX_TRST_MASK (0x00004000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT20_DL1_TM_LPTX_TRST_SHIFT (0x0000000EU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT20_DL1_TM_LPTX_TRST_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT20_DL1_TM_LPTX_RST_SEL_MASK (0x00002000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT20_DL1_TM_LPTX_RST_SEL_SHIFT (0x0000000DU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT20_DL1_TM_LPTX_RST_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT20_DL1_TM_LPTX_RST_MASK (0x00001000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT20_DL1_TM_LPTX_RST_SHIFT (0x0000000CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT20_DL1_TM_LPTX_RST_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT20_DL1_TM_LPTX_DP_SEL_MASK (0x00000800U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT20_DL1_TM_LPTX_DP_SEL_SHIFT (0x0000000BU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT20_DL1_TM_LPTX_DP_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT20_DL1_TM_LPTX_DP_MASK (0x00000400U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT20_DL1_TM_LPTX_DP_SHIFT (0x0000000AU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT20_DL1_TM_LPTX_DP_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT20_DL1_TM_LPTX_DN_SEL_MASK (0x00000200U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT20_DL1_TM_LPTX_DN_SEL_SHIFT (0x00000009U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT20_DL1_TM_LPTX_DN_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT20_DL1_TM_LPTX_DN_MASK (0x00000100U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT20_DL1_TM_LPTX_DN_SHIFT (0x00000008U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT20_DL1_TM_LPTX_DN_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT20_DL1_TM_LDO_REF_EN_SEL_MASK (0x00000080U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT20_DL1_TM_LDO_REF_EN_SEL_SHIFT (0x00000007U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT20_DL1_TM_LDO_REF_EN_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT20_DL1_TM_LDO_REF_EN_MASK (0x00000040U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT20_DL1_TM_LDO_REF_EN_SHIFT (0x00000006U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT20_DL1_TM_LDO_REF_EN_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT20_DL1_TM_HSTX_TRST_SEL_MASK (0x00000020U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT20_DL1_TM_HSTX_TRST_SEL_SHIFT (0x00000005U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT20_DL1_TM_HSTX_TRST_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT20_DL1_TM_HSTX_TRST_MASK (0x00000010U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT20_DL1_TM_HSTX_TRST_SHIFT (0x00000004U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT20_DL1_TM_HSTX_TRST_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT20_DL1_TM_HSTX_RQST_SEL_MASK (0x00000008U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT20_DL1_TM_HSTX_RQST_SEL_SHIFT (0x00000003U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT20_DL1_TM_HSTX_RQST_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT20_DL1_TM_HSTX_RQST_MASK (0x00000004U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT20_DL1_TM_HSTX_RQST_SHIFT (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT20_DL1_TM_HSTX_RQST_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT20_DL1_TM_GLOBAL_PD_SEL_MASK (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT20_DL1_TM_GLOBAL_PD_SEL_SHIFT (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT20_DL1_TM_GLOBAL_PD_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT20_DL1_TM_GLOBAL_PD_MASK (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT20_DL1_TM_GLOBAL_PD_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT20_DL1_TM_GLOBAL_PD_MAX (0x00000001U)
+
+/* DL1_TX_DIG_TBIT21 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT21_DL1_TM_SERSYNTH_RST_N_SEL_MASK (0x00004000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT21_DL1_TM_SERSYNTH_RST_N_SEL_SHIFT (0x0000000EU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT21_DL1_TM_SERSYNTH_RST_N_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT21_DL1_TM_SERSYNTH_RST_N_MASK (0x00002000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT21_DL1_TM_SERSYNTH_RST_N_SHIFT (0x0000000DU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT21_DL1_TM_SERSYNTH_RST_N_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT21_DL1_TM_SWAP_DPDN_SEL_MASK (0x00001000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT21_DL1_TM_SWAP_DPDN_SEL_SHIFT (0x0000000CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT21_DL1_TM_SWAP_DPDN_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT21_DL1_TM_SWAP_DPDN_EN_MASK (0x00000800U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT21_DL1_TM_SWAP_DPDN_EN_SHIFT (0x0000000BU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT21_DL1_TM_SWAP_DPDN_EN_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT21_DL1_TM_SERSYNTH_EN_SEL_MASK (0x00000400U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT21_DL1_TM_SERSYNTH_EN_SEL_SHIFT (0x0000000AU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT21_DL1_TM_SERSYNTH_EN_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT21_DL1_TM_SERSYNTH_EN_MASK (0x00000200U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT21_DL1_TM_SERSYNTH_EN_SHIFT (0x00000009U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT21_DL1_TM_SERSYNTH_EN_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT21_DL1_TM_TX_DATA_HS_SEL_MASK (0x00000100U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT21_DL1_TM_TX_DATA_HS_SEL_SHIFT (0x00000008U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT21_DL1_TM_TX_DATA_HS_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT21_DL1_TM_TX_DATA_HS_MASK (0x000000FFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT21_DL1_TM_TX_DATA_HS_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT21_DL1_TM_TX_DATA_HS_MAX (0x000000FFU)
+
+/* DL1_TX_DIG_TBIT22 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT22_DL1_DIG_TBIT22_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT22_DL1_DIG_TBIT22_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT22_DL1_DIG_TBIT22_MAX (0xFFFFFFFFU)
+
+/* DL1_TX_DIG_TBIT23 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT23_DL1_DIG_TBIT23_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT23_DL1_DIG_TBIT23_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT23_DL1_DIG_TBIT23_MAX (0xFFFFFFFFU)
+
+/* DL1_TX_DIG_TBIT24 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT24_DL1_DIG_TBIT24_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT24_DL1_DIG_TBIT24_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT24_DL1_DIG_TBIT24_MAX (0xFFFFFFFFU)
+
+/* DL1_TX_ANA_TBIT5 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_ANA_TBIT5_DL1_ANA_TBIT5_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_ANA_TBIT5_DL1_ANA_TBIT5_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_ANA_TBIT5_DL1_ANA_TBIT5_MAX (0xFFFFFFFFU)
+
+/* DL1_TX_DIG_TBIT25 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT25_DL1_ANA_CTRL_FSM_STATE_MASK (0x001F0000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT25_DL1_ANA_CTRL_FSM_STATE_SHIFT (0x00000010U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT25_DL1_ANA_CTRL_FSM_STATE_MAX (0x0000001FU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT25_DL1_BIST_BAL_STATUS_MASK (0x0000FFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT25_DL1_BIST_BAL_STATUS_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT25_DL1_BIST_BAL_STATUS_MAX (0x0000FFFFU)
+
+/* DL1_TX_DIG_TBIT26 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT26_DL1_TM_DATA_ESC_RX_FSM_STATE_MASK (0xF8000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT26_DL1_TM_DATA_ESC_RX_FSM_STATE_SHIFT (0x0000001BU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT26_DL1_TM_DATA_ESC_RX_FSM_STATE_MAX (0x0000001FU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT26_DL1_TM_DATA_ESCTX_CTRL_FSM_STATE_MASK (0x07FE0000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT26_DL1_TM_DATA_ESCTX_CTRL_FSM_STATE_SHIFT (0x00000011U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT26_DL1_TM_DATA_ESCTX_CTRL_FSM_STATE_MAX (0x000003FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT26_DL1_TM_DATA_ESCTX_DATA_FSM_STATE_MASK (0x0001F000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT26_DL1_TM_DATA_ESCTX_DATA_FSM_STATE_SHIFT (0x0000000CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT26_DL1_TM_DATA_ESCTX_DATA_FSM_STATE_MAX (0x0000001FU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT26_DL1_TM_HS_PATH_FSM_STATE_MASK (0x00000FFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT26_DL1_TM_HS_PATH_FSM_STATE_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT26_DL1_TM_HS_PATH_FSM_STATE_MAX (0x00000FFFU)
+
+/* DL1_TX_DIG_TBIT28 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT28_DL1_TM_ANA_COMP_OUTS_MASK (0x0000FF00U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT28_DL1_TM_ANA_COMP_OUTS_SHIFT (0x00000008U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT28_DL1_TM_ANA_COMP_OUTS_MAX (0x000000FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT28_DL1_UNUSED_7_0_MASK (0x000000FFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT28_DL1_UNUSED_7_0_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT28_DL1_UNUSED_7_0_MAX (0x000000FFU)
+
+/* DL1_TX_DIG_TBIT29 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT29_DL1_TM_CUR_STATE_ULPTX_CHE_MASK (0x03000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT29_DL1_TM_CUR_STATE_ULPTX_CHE_SHIFT (0x00000018U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT29_DL1_TM_CUR_STATE_ULPTX_CHE_MAX (0x00000003U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT29_DL1_TM_CUR_STATE_ULPRX_CHE_MASK (0x00E00000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT29_DL1_TM_CUR_STATE_ULPRX_CHE_SHIFT (0x00000015U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT29_DL1_TM_CUR_STATE_ULPRX_CHE_MAX (0x00000007U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT29_DL1_TM_CUR_STATE_LPCD_CHE_MASK (0x001C0000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT29_DL1_TM_CUR_STATE_LPCD_CHE_SHIFT (0x00000012U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT29_DL1_TM_CUR_STATE_LPCD_CHE_MAX (0x00000007U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT29_DL1_TM_CUR_STATE_LPRX_CHE_MASK (0x00038000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT29_DL1_TM_CUR_STATE_LPRX_CHE_SHIFT (0x0000000FU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT29_DL1_TM_CUR_STATE_LPRX_CHE_MAX (0x00000007U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT29_DL1_TM_CUR_STATE_CTRLR_MASK (0x00007800U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT29_DL1_TM_CUR_STATE_CTRLR_SHIFT (0x0000000BU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT29_DL1_TM_CUR_STATE_CTRLR_MAX (0x0000000FU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT29_DL1_BIST_DATA_LANE_PASS_MASK (0x00000400U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT29_DL1_BIST_DATA_LANE_PASS_SHIFT (0x0000000AU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT29_DL1_BIST_DATA_LANE_PASS_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT29_DL1_BIST_LPRX_PASS_MASK (0x00000200U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT29_DL1_BIST_LPRX_PASS_SHIFT (0x00000009U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT29_DL1_BIST_LPRX_PASS_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT29_DL1_BIST_LPCD_PASS_MASK (0x00000100U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT29_DL1_BIST_LPCD_PASS_SHIFT (0x00000008U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT29_DL1_BIST_LPCD_PASS_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT29_DL1_BIST_ULPRX_PASS_MASK (0x00000080U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT29_DL1_BIST_ULPRX_PASS_SHIFT (0x00000007U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT29_DL1_BIST_ULPRX_PASS_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT29_DL1_BIST_ULPTX_PASS_MASK (0x00000040U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT29_DL1_BIST_ULPTX_PASS_SHIFT (0x00000006U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT29_DL1_BIST_ULPTX_PASS_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT29_DL1_BIST_HS_NEG_ERR_MASK (0x00000020U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT29_DL1_BIST_HS_NEG_ERR_SHIFT (0x00000005U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT29_DL1_BIST_HS_NEG_ERR_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT29_DL1_BIST_HS_POS_ERR_MASK (0x00000010U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT29_DL1_BIST_HS_POS_ERR_SHIFT (0x00000004U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT29_DL1_BIST_HS_POS_ERR_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT29_DL1_BIST_POS_SYNC_MASK (0x00000008U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT29_DL1_BIST_POS_SYNC_SHIFT (0x00000003U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT29_DL1_BIST_POS_SYNC_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT29_DL1_BIST_NEG_SYNC_MASK (0x00000004U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT29_DL1_BIST_NEG_SYNC_SHIFT (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT29_DL1_BIST_NEG_SYNC_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT29_DL1_BIST_CMPLT_MASK (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT29_DL1_BIST_CMPLT_SHIFT (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT29_DL1_BIST_CMPLT_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT29_DL1_BIST_EN_STATUS_MASK (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT29_DL1_BIST_EN_STATUS_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT29_DL1_BIST_EN_STATUS_MAX (0x00000001U)
+
+/* DL1_TX_DIG_TBIT30 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT30_DL1_BIST_PAT_CHE_PKT_CNT_NEG_MASK (0xFFFF0000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT30_DL1_BIST_PAT_CHE_PKT_CNT_NEG_SHIFT (0x00000010U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT30_DL1_BIST_PAT_CHE_PKT_CNT_NEG_MAX (0x0000FFFFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT30_DL1_BIST_PAT_CHE_PKT_CNT_POS_MASK (0x0000FFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT30_DL1_BIST_PAT_CHE_PKT_CNT_POS_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT30_DL1_BIST_PAT_CHE_PKT_CNT_POS_MAX (0x0000FFFFU)
+
+/* DL1_TX_DIG_TBIT31 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT31_DL1_BIST_PAT_CHE_ERR_CNT_NEG_MASK (0xFFFF0000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT31_DL1_BIST_PAT_CHE_ERR_CNT_NEG_SHIFT (0x00000010U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT31_DL1_BIST_PAT_CHE_ERR_CNT_NEG_MAX (0x0000FFFFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT31_DL1_BIST_PAT_CHE_ERR_CNT_POS_MASK (0x0000FFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT31_DL1_BIST_PAT_CHE_ERR_CNT_POS_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT31_DL1_BIST_PAT_CHE_ERR_CNT_POS_MAX (0x0000FFFFU)
+
+/* DL1_TX_DIG_TBIT32 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT32_DL1_DIG_TBIT32_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT32_DL1_DIG_TBIT32_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT32_DL1_DIG_TBIT32_MAX (0xFFFFFFFFU)
+
+/* DL1_TX_DIG_TBIT33 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT33_DL1_DIG_TBIT33_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT33_DL1_DIG_TBIT33_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT33_DL1_DIG_TBIT33_MAX (0xFFFFFFFFU)
+
+/* DL1_TX_DIG_TBIT34 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT34_DL1_DIG_TBIT34_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT34_DL1_DIG_TBIT34_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT34_DL1_DIG_TBIT34_MAX (0xFFFFFFFFU)
+
+/* DL1_TX_DIG_TBIT35 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT35_DL1_DIG_TBIT35_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT35_DL1_DIG_TBIT35_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT35_DL1_DIG_TBIT35_MAX (0xFFFFFFFFU)
+
+/* DL1_TX_DIG_TBIT36 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT36_DL1_DIG_TBIT36_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT36_DL1_DIG_TBIT36_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL1_TX_DIG_TBIT36_DL1_DIG_TBIT36_MAX (0xFFFFFFFFU)
+
+/* DL2_TX_ANA_TBIT0 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_ANA_TBIT0_DL2_ANA_TBIT0_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_ANA_TBIT0_DL2_ANA_TBIT0_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_ANA_TBIT0_DL2_ANA_TBIT0_MAX (0xFFFFFFFFU)
+
+/* DL2_TX_ANA_TBIT1 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_ANA_TBIT1_DL2_ANA_TBIT1_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_ANA_TBIT1_DL2_ANA_TBIT1_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_ANA_TBIT1_DL2_ANA_TBIT1_MAX (0xFFFFFFFFU)
+
+/* DL2_TX_ANA_TBIT2 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_ANA_TBIT2_DL2_ANA_TBIT2_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_ANA_TBIT2_DL2_ANA_TBIT2_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_ANA_TBIT2_DL2_ANA_TBIT2_MAX (0xFFFFFFFFU)
+
+/* DL2_TX_ANA_TBIT3 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_ANA_TBIT3_DL2_ANA_TBIT3_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_ANA_TBIT3_DL2_ANA_TBIT3_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_ANA_TBIT3_DL2_ANA_TBIT3_MAX (0xFFFFFFFFU)
+
+/* DL2_TX_ANA_TBIT4 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_ANA_TBIT4_DL2_ANA_TBIT4_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_ANA_TBIT4_DL2_ANA_TBIT4_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_ANA_TBIT4_DL2_ANA_TBIT4_MAX (0xFFFFFFFFU)
+
+/* DL2_TX_DIG_TBIT0 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT0_DL2_UNUSED_31_13_MASK (0xFFFFE000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT0_DL2_UNUSED_31_13_SHIFT (0x0000000DU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT0_DL2_UNUSED_31_13_MAX (0x0007FFFFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT0_DL2_ULPS_PULLDN_CNT_MASK (0x00001F00U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT0_DL2_ULPS_PULLDN_CNT_SHIFT (0x00000008U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT0_DL2_ULPS_PULLDN_CNT_MAX (0x0000001FU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT0_DL2_UNUSED_7_5_MASK (0x000000E0U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT0_DL2_UNUSED_7_5_SHIFT (0x00000005U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT0_DL2_UNUSED_7_5_MAX (0x00000007U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT0_DL2_LDO_EN_CNT_MASK (0x0000001FU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT0_DL2_LDO_EN_CNT_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT0_DL2_LDO_EN_CNT_MAX (0x0000001FU)
+
+/* DL2_TX_DIG_TBIT1 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT1_DL2_TEST_LPTX_DP_MASK (0x00200000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT1_DL2_TEST_LPTX_DP_SHIFT (0x00000015U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT1_DL2_TEST_LPTX_DP_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT1_DL2_TEST_LPTX_DN_MASK (0x00100000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT1_DL2_TEST_LPTX_DN_SHIFT (0x00000014U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT1_DL2_TEST_LPTX_DN_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT1_DL2_TEST_LPTX_EN_MASK (0x00080000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT1_DL2_TEST_LPTX_EN_SHIFT (0x00000013U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT1_DL2_TEST_LPTX_EN_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT1_DL2_TM_READY_SKEW_CAL_MASK (0x00040000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT1_DL2_TM_READY_SKEW_CAL_SHIFT (0x00000012U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT1_DL2_TM_READY_SKEW_CAL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT1_DL2_TM_HS_PREP_HAFCYC_OVERRIDE_MASK (0x00020000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT1_DL2_TM_HS_PREP_HAFCYC_OVERRIDE_SHIFT (0x00000011U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT1_DL2_TM_HS_PREP_HAFCYC_OVERRIDE_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT1_DL2_TM_HS_PREP_HSFCYC_MASK (0x00010000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT1_DL2_TM_HS_PREP_HSFCYC_SHIFT (0x00000010U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT1_DL2_TM_HS_PREP_HSFCYC_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT1_DL2_HS_TRAIL_OFFSET_MASK (0x0000F000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT1_DL2_HS_TRAIL_OFFSET_SHIFT (0x0000000CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT1_DL2_HS_TRAIL_OFFSET_MAX (0x0000000FU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT1_DL2_HS_ZERO_OFFSET_MASK (0x00000F00U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT1_DL2_HS_ZERO_OFFSET_SHIFT (0x00000008U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT1_DL2_HS_ZERO_OFFSET_MAX (0x0000000FU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT1_DL2_HS_PREP_OFFSET_MASK (0x000000F0U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT1_DL2_HS_PREP_OFFSET_SHIFT (0x00000004U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT1_DL2_HS_PREP_OFFSET_MAX (0x0000000FU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT1_DL2_HS_TLPX_OFFSET_MASK (0x0000000FU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT1_DL2_HS_TLPX_OFFSET_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT1_DL2_HS_TLPX_OFFSET_MAX (0x0000000FU)
+
+/* DL2_TX_DIG_TBIT2 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT2_DL2_TM_SKEW_CAL_SEQ_MASK (0x07F80000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT2_DL2_TM_SKEW_CAL_SEQ_SHIFT (0x00000013U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT2_DL2_TM_SKEW_CAL_SEQ_MAX (0x000000FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT2_DL2_TM_SKEW_CAL_SEQ_SEL_MASK (0x00040000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT2_DL2_TM_SKEW_CAL_SEQ_SEL_SHIFT (0x00000012U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT2_DL2_TM_SKEW_CAL_SEQ_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT2_DL2_TM_SKEW_CAL_SYNC_PKT_MASK (0x0003FC00U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT2_DL2_TM_SKEW_CAL_SYNC_PKT_SHIFT (0x0000000AU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT2_DL2_TM_SKEW_CAL_SYNC_PKT_MAX (0x000000FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT2_DL2_TM_SKEW_CAL_SYNC_PKT_SEL_MASK (0x00000200U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT2_DL2_TM_SKEW_CAL_SYNC_PKT_SEL_SHIFT (0x00000009U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT2_DL2_TM_SKEW_CAL_SYNC_PKT_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT2_DL2_TM_HS_SYNC_PKT_MASK (0x000001FEU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT2_DL2_TM_HS_SYNC_PKT_SHIFT (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT2_DL2_TM_HS_SYNC_PKT_MAX (0x000000FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT2_DL2_TM_HS_SYNC_PKT_SEL_MASK (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT2_DL2_TM_HS_SYNC_PKT_SEL_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT2_DL2_TM_HS_SYNC_PKT_SEL_MAX (0x00000001U)
+
+/* DL2_TX_DIG_TBIT3 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT3_DL2_SERSYNTH_LOOPBACK_MASK (0x00000020U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT3_DL2_SERSYNTH_LOOPBACK_SHIFT (0x00000005U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT3_DL2_SERSYNTH_LOOPBACK_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT3_DL2_BAL_FORCE_STATE_MASK (0x0000001CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT3_DL2_BAL_FORCE_STATE_SHIFT (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT3_DL2_BAL_FORCE_STATE_MAX (0x00000007U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT3_DL2_BAL_FORCE_EN_MASK (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT3_DL2_BAL_FORCE_EN_SHIFT (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT3_DL2_BAL_FORCE_EN_MAX (0x00000001U)
+
+/* DL2_TX_DIG_TBIT4 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT4_DL2_CONTENTION_EN_MASK (0x00008000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT4_DL2_CONTENTION_EN_SHIFT (0x0000000FU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT4_DL2_CONTENTION_EN_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT4_DL2_UNUSED_14_13_MASK (0x00006000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT4_DL2_UNUSED_14_13_SHIFT (0x0000000DU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT4_DL2_UNUSED_14_13_MAX (0x00000003U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT4_DL2_FORCE_RX_MODE_MASK (0x00001000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT4_DL2_FORCE_RX_MODE_SHIFT (0x0000000CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT4_DL2_FORCE_RX_MODE_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT4_DL2_TEST_DATA_LPTX_DP_SEL_MASK (0x00000800U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT4_DL2_TEST_DATA_LPTX_DP_SEL_SHIFT (0x0000000BU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT4_DL2_TEST_DATA_LPTX_DP_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT4_DL2_TEST_DATA_LPTX_DN_SEL_MASK (0x00000400U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT4_DL2_TEST_DATA_LPTX_DN_SEL_SHIFT (0x0000000AU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT4_DL2_TEST_DATA_LPTX_DN_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT4_DL2_TEST_DATA_LPTX_MASK (0x000003FCU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT4_DL2_TEST_DATA_LPTX_SHIFT (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT4_DL2_TEST_DATA_LPTX_MAX (0x000000FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT4_DL2_TEST_DATA_LPTX_RSTN_MASK (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT4_DL2_TEST_DATA_LPTX_RSTN_SHIFT (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT4_DL2_TEST_DATA_LPTX_RSTN_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT4_DL2_TEST_DATA_LPTX_EN_MASK (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT4_DL2_TEST_DATA_LPTX_EN_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT4_DL2_TEST_DATA_LPTX_EN_MAX (0x00000001U)
+
+/* DL2_TX_DIG_TBIT5 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT5_DL2_DIG_TBIT5_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT5_DL2_DIG_TBIT5_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT5_DL2_DIG_TBIT5_MAX (0xFFFFFFFFU)
+
+/* DL2_TX_DIG_TBIT6 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT6_DL2_DIG_TBIT6_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT6_DL2_DIG_TBIT6_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT6_DL2_DIG_TBIT6_MAX (0xFFFFFFFFU)
+
+/* DL2_TX_DIG_TBIT7 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT7_DL2_DIG_TBIT7_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT7_DL2_DIG_TBIT7_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT7_DL2_DIG_TBIT7_MAX (0xFFFFFFFFU)
+
+/* DL2_TX_DIG_TBIT8 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT8_DL2_DIG_TBIT8_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT8_DL2_DIG_TBIT8_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT8_DL2_DIG_TBIT8_MAX (0xFFFFFFFFU)
+
+/* DL2_TX_DIG_TBIT9 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT9_DL2_DIG_TBIT9_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT9_DL2_DIG_TBIT9_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT9_DL2_DIG_TBIT9_MAX (0xFFFFFFFFU)
+
+/* DL2_TX_DIG_TBIT10 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT10_DL2_BIST_WAIT_TIME_MASK (0x01E00000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT10_DL2_BIST_WAIT_TIME_SHIFT (0x00000015U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT10_DL2_BIST_WAIT_TIME_MAX (0x0000000FU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT10_DL2_BIST_ULPTX_TEST_TIME_MASK (0x001FE000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT10_DL2_BIST_ULPTX_TEST_TIME_SHIFT (0x0000000DU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT10_DL2_BIST_ULPTX_TEST_TIME_MAX (0x000000FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT10_DL2_BIST_SEND_CONFIG_MASK (0x00001800U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT10_DL2_BIST_SEND_CONFIG_SHIFT (0x0000000BU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT10_DL2_BIST_SEND_CONFIG_MAX (0x00000003U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT10_DL2_BIST_DIG_TO_DIG_LOOPBK_MASK (0x00000400U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT10_DL2_BIST_DIG_TO_DIG_LOOPBK_SHIFT (0x0000000AU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT10_DL2_BIST_DIG_TO_DIG_LOOPBK_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT10_DL2_BIST_RUN_NEGEDGE_FIRST_MASK (0x00000200U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT10_DL2_BIST_RUN_NEGEDGE_FIRST_SHIFT (0x00000009U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT10_DL2_BIST_RUN_NEGEDGE_FIRST_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT10_DL2_BIST_LENGTH_OF_DESKEW_MASK (0x000001FCU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT10_DL2_BIST_LENGTH_OF_DESKEW_SHIFT (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT10_DL2_BIST_LENGTH_OF_DESKEW_MAX (0x0000007FU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT10_DL2_BIST_LOOPBK_MODE_MASK (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT10_DL2_BIST_LOOPBK_MODE_SHIFT (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT10_DL2_BIST_LOOPBK_MODE_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT10_DL2_BIST_EN_MASK (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT10_DL2_BIST_EN_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT10_DL2_BIST_EN_MAX (0x00000001U)
+
+/* DL2_TX_DIG_TBIT11 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT11_DL2_BIST_FRM_IDLE_TIME_MASK (0xFF000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT11_DL2_BIST_FRM_IDLE_TIME_SHIFT (0x00000018U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT11_DL2_BIST_FRM_IDLE_TIME_MAX (0x000000FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT11_DL2_BIST_PKT_NUM_MASK (0x00FF0000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT11_DL2_BIST_PKT_NUM_SHIFT (0x00000010U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT11_DL2_BIST_PKT_NUM_MAX (0x000000FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT11_DL2_BIST_INF_MODE_MASK (0x00008000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT11_DL2_BIST_INF_MODE_SHIFT (0x0000000FU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT11_DL2_BIST_INF_MODE_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT11_DL2_BIST_FRM_NUM_MASK (0x00007F80U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT11_DL2_BIST_FRM_NUM_SHIFT (0x00000007U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT11_DL2_BIST_FRM_NUM_MAX (0x000000FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT11_DL2_BIST_CLEAR_MASK (0x00000040U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT11_DL2_BIST_CLEAR_SHIFT (0x00000006U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT11_DL2_BIST_CLEAR_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT11_DL2_BIST_PRBS_MASK (0x00000030U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT11_DL2_BIST_PRBS_SHIFT (0x00000004U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT11_DL2_BIST_PRBS_MAX (0x00000003U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT11_DL2_BIST_TEST_MODE_MASK (0x0000000EU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT11_DL2_BIST_TEST_MODE_SHIFT (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT11_DL2_BIST_TEST_MODE_MAX (0x00000007U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT11_DL2_UNUSED_0_MASK (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT11_DL2_UNUSED_0_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT11_DL2_UNUSED_0_MAX (0x00000001U)
+
+/* DL2_TX_DIG_TBIT12 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT12_DL2_BIST_RUN_LENGTH_MASK (0x00000FFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT12_DL2_BIST_RUN_LENGTH_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT12_DL2_BIST_RUN_LENGTH_MAX (0x00000FFFU)
+
+/* DL2_TX_DIG_TBIT13 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT13_DL2_UNUSED_31_8_MASK (0xFFFFFF00U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT13_DL2_UNUSED_31_8_SHIFT (0x00000008U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT13_DL2_UNUSED_31_8_MAX (0x00FFFFFFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT13_DL2_BIST_IDLE_TIME_MASK (0x000000FFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT13_DL2_BIST_IDLE_TIME_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT13_DL2_BIST_IDLE_TIME_MAX (0x000000FFU)
+
+/* DL2_TX_DIG_TBIT14 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT14_DL2_BIST_PKT4_MASK (0xFF000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT14_DL2_BIST_PKT4_SHIFT (0x00000018U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT14_DL2_BIST_PKT4_MAX (0x000000FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT14_DL2_BIST_PKT3_MASK (0x00FF0000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT14_DL2_BIST_PKT3_SHIFT (0x00000010U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT14_DL2_BIST_PKT3_MAX (0x000000FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT14_DL2_BIST_PKT2_MASK (0x0000FF00U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT14_DL2_BIST_PKT2_SHIFT (0x00000008U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT14_DL2_BIST_PKT2_MAX (0x000000FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT14_DL2_BIST_PKT1_MASK (0x000000FFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT14_DL2_BIST_PKT1_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT14_DL2_BIST_PKT1_MAX (0x000000FFU)
+
+/* DL2_TX_DIG_TBIT15 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT15_DL2_BIST_LFSR_FREEZE_MASK (0x00002000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT15_DL2_BIST_LFSR_FREEZE_SHIFT (0x0000000DU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT15_DL2_BIST_LFSR_FREEZE_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT15_DL2_BIST_ERR_INJ_POINT_MASK (0x00001FFEU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT15_DL2_BIST_ERR_INJ_POINT_SHIFT (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT15_DL2_BIST_ERR_INJ_POINT_MAX (0x00000FFFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT15_DL2_BIST_ERR_INJ_EN_MASK (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT15_DL2_BIST_ERR_INJ_EN_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT15_DL2_BIST_ERR_INJ_EN_MAX (0x00000001U)
+
+/* DL2_TX_DIG_TBIT16 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT16_DL2_DIG_TBIT16_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT16_DL2_DIG_TBIT16_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT16_DL2_DIG_TBIT16_MAX (0xFFFFFFFFU)
+
+/* DL2_TX_DIG_TBIT17 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT17_DL2_DIG_TBIT17_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT17_DL2_DIG_TBIT17_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT17_DL2_DIG_TBIT17_MAX (0xFFFFFFFFU)
+
+/* DL2_TX_DIG_TBIT18 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT18_DL2_DIG_TBIT18_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT18_DL2_DIG_TBIT18_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT18_DL2_DIG_TBIT18_MAX (0xFFFFFFFFU)
+
+/* DL2_TX_DIG_TBIT19 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT19_DL2_DIG_TBIT19_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT19_DL2_DIG_TBIT19_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT19_DL2_DIG_TBIT19_MAX (0xFFFFFFFFU)
+
+/* DL2_TX_DIG_TBIT20 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT20_DL2_TM_ISO_EN_MASK (0x80000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT20_DL2_TM_ISO_EN_SHIFT (0x0000001FU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT20_DL2_TM_ISO_EN_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT20_DL2_TM_LOAD_DPDN_SEL_MASK (0x40000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT20_DL2_TM_LOAD_DPDN_SEL_SHIFT (0x0000001EU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT20_DL2_TM_LOAD_DPDN_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT20_DL2_TM_LOAD_DPDN_MASK (0x38000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT20_DL2_TM_LOAD_DPDN_SHIFT (0x0000001BU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT20_DL2_TM_LOAD_DPDN_MAX (0x00000007U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT20_DL2_TM_HSTX_DATA_RATE_SEL_MASK (0x04000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT20_DL2_TM_HSTX_DATA_RATE_SEL_SHIFT (0x0000001AU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT20_DL2_TM_HSTX_DATA_RATE_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT20_DL2_TM_HSTX_DATE_RATE_MASK (0x03000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT20_DL2_TM_HSTX_DATE_RATE_SHIFT (0x00000018U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT20_DL2_TM_HSTX_DATE_RATE_MAX (0x00000003U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT20_DL2_TM_BIST_ULP_RCV_EN_SEL_MASK (0x00800000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT20_DL2_TM_BIST_ULP_RCV_EN_SEL_SHIFT (0x00000017U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT20_DL2_TM_BIST_ULP_RCV_EN_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT20_DL2_TM_BIST_ULP_RCV_EN_MASK (0x00400000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT20_DL2_TM_BIST_ULP_RCV_EN_SHIFT (0x00000016U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT20_DL2_TM_BIST_ULP_RCV_EN_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT20_DL2_TM_ULPS_PULDN_SEL_MASK (0x00200000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT20_DL2_TM_ULPS_PULDN_SEL_SHIFT (0x00000015U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT20_DL2_TM_ULPS_PULDN_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT20_DL2_TM_ULPS_PULDN_MASK (0x00100000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT20_DL2_TM_ULPS_PULDN_SHIFT (0x00000014U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT20_DL2_TM_ULPS_PULDN_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT20_DL2_TM_BIST_SMPLR_CLK_EDGE_SEL_MASK (0x00080000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT20_DL2_TM_BIST_SMPLR_CLK_EDGE_SEL_SHIFT (0x00000013U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT20_DL2_TM_BIST_SMPLR_CLK_EDGE_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT20_DL2_TM_BIST_SMPLR_CLK_EDGE_MASK (0x00040000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT20_DL2_TM_BIST_SMPLR_CLK_EDGE_SHIFT (0x00000012U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT20_DL2_TM_BIST_SMPLR_CLK_EDGE_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT20_DL2_TM_BIST_EN_SEL_MASK (0x00020000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT20_DL2_TM_BIST_EN_SEL_SHIFT (0x00000011U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT20_DL2_TM_BIST_EN_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT20_DL2_TM_BIST_EN_MASK (0x00010000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT20_DL2_TM_BIST_EN_SHIFT (0x00000010U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT20_DL2_TM_BIST_EN_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT20_DL2_TM_LPTX_TRST_SEL_MASK (0x00008000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT20_DL2_TM_LPTX_TRST_SEL_SHIFT (0x0000000FU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT20_DL2_TM_LPTX_TRST_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT20_DL2_TM_LPTX_TRST_MASK (0x00004000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT20_DL2_TM_LPTX_TRST_SHIFT (0x0000000EU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT20_DL2_TM_LPTX_TRST_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT20_DL2_TM_LPTX_RST_SEL_MASK (0x00002000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT20_DL2_TM_LPTX_RST_SEL_SHIFT (0x0000000DU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT20_DL2_TM_LPTX_RST_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT20_DL2_TM_LPTX_RST_MASK (0x00001000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT20_DL2_TM_LPTX_RST_SHIFT (0x0000000CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT20_DL2_TM_LPTX_RST_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT20_DL2_TM_LPTX_DP_SEL_MASK (0x00000800U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT20_DL2_TM_LPTX_DP_SEL_SHIFT (0x0000000BU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT20_DL2_TM_LPTX_DP_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT20_DL2_TM_LPTX_DP_MASK (0x00000400U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT20_DL2_TM_LPTX_DP_SHIFT (0x0000000AU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT20_DL2_TM_LPTX_DP_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT20_DL2_TM_LPTX_DN_SEL_MASK (0x00000200U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT20_DL2_TM_LPTX_DN_SEL_SHIFT (0x00000009U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT20_DL2_TM_LPTX_DN_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT20_DL2_TM_LPTX_DN_MASK (0x00000100U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT20_DL2_TM_LPTX_DN_SHIFT (0x00000008U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT20_DL2_TM_LPTX_DN_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT20_DL2_TM_LDO_REF_EN_SEL_MASK (0x00000080U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT20_DL2_TM_LDO_REF_EN_SEL_SHIFT (0x00000007U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT20_DL2_TM_LDO_REF_EN_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT20_DL2_TM_LDO_REF_EN_MASK (0x00000040U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT20_DL2_TM_LDO_REF_EN_SHIFT (0x00000006U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT20_DL2_TM_LDO_REF_EN_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT20_DL2_TM_HSTX_TRST_SEL_MASK (0x00000020U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT20_DL2_TM_HSTX_TRST_SEL_SHIFT (0x00000005U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT20_DL2_TM_HSTX_TRST_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT20_DL2_TM_HSTX_TRST_MASK (0x00000010U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT20_DL2_TM_HSTX_TRST_SHIFT (0x00000004U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT20_DL2_TM_HSTX_TRST_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT20_DL2_TM_HSTX_RQST_SEL_MASK (0x00000008U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT20_DL2_TM_HSTX_RQST_SEL_SHIFT (0x00000003U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT20_DL2_TM_HSTX_RQST_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT20_DL2_TM_HSTX_RQST_MASK (0x00000004U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT20_DL2_TM_HSTX_RQST_SHIFT (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT20_DL2_TM_HSTX_RQST_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT20_DL2_TM_GLOBAL_PD_SEL_MASK (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT20_DL2_TM_GLOBAL_PD_SEL_SHIFT (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT20_DL2_TM_GLOBAL_PD_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT20_DL2_TM_GLOBAL_PD_MASK (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT20_DL2_TM_GLOBAL_PD_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT20_DL2_TM_GLOBAL_PD_MAX (0x00000001U)
+
+/* DL2_TX_DIG_TBIT21 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT21_DL2_TM_SERSYNTH_RST_N_SEL_MASK (0x00004000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT21_DL2_TM_SERSYNTH_RST_N_SEL_SHIFT (0x0000000EU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT21_DL2_TM_SERSYNTH_RST_N_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT21_DL2_TM_SERSYNTH_RST_N_MASK (0x00002000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT21_DL2_TM_SERSYNTH_RST_N_SHIFT (0x0000000DU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT21_DL2_TM_SERSYNTH_RST_N_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT21_DL2_TM_SWAP_DPDN_SEL_MASK (0x00001000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT21_DL2_TM_SWAP_DPDN_SEL_SHIFT (0x0000000CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT21_DL2_TM_SWAP_DPDN_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT21_DL2_TM_SWAP_DPDN_EN_MASK (0x00000800U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT21_DL2_TM_SWAP_DPDN_EN_SHIFT (0x0000000BU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT21_DL2_TM_SWAP_DPDN_EN_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT21_DL2_TM_SERSYNTH_EN_SEL_MASK (0x00000400U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT21_DL2_TM_SERSYNTH_EN_SEL_SHIFT (0x0000000AU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT21_DL2_TM_SERSYNTH_EN_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT21_DL2_TM_SERSYNTH_EN_MASK (0x00000200U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT21_DL2_TM_SERSYNTH_EN_SHIFT (0x00000009U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT21_DL2_TM_SERSYNTH_EN_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT21_DL2_TM_TX_DATA_HS_SEL_MASK (0x00000100U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT21_DL2_TM_TX_DATA_HS_SEL_SHIFT (0x00000008U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT21_DL2_TM_TX_DATA_HS_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT21_DL2_TM_TX_DATA_HS_MASK (0x000000FFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT21_DL2_TM_TX_DATA_HS_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT21_DL2_TM_TX_DATA_HS_MAX (0x000000FFU)
+
+/* DL2_TX_DIG_TBIT22 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT22_DL2_DIG_TBIT22_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT22_DL2_DIG_TBIT22_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT22_DL2_DIG_TBIT22_MAX (0xFFFFFFFFU)
+
+/* DL2_TX_DIG_TBIT23 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT23_DL2_DIG_TBIT23_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT23_DL2_DIG_TBIT23_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT23_DL2_DIG_TBIT23_MAX (0xFFFFFFFFU)
+
+/* DL2_TX_DIG_TBIT24 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT24_DL2_DIG_TBIT24_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT24_DL2_DIG_TBIT24_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT24_DL2_DIG_TBIT24_MAX (0xFFFFFFFFU)
+
+/* DL2_TX_ANA_TBIT5 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_ANA_TBIT5_DL2_ANA_TBIT5_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_ANA_TBIT5_DL2_ANA_TBIT5_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_ANA_TBIT5_DL2_ANA_TBIT5_MAX (0xFFFFFFFFU)
+
+/* DL2_TX_DIG_TBIT25 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT25_DL2_ANA_CTRL_FSM_STATE_MASK (0x001F0000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT25_DL2_ANA_CTRL_FSM_STATE_SHIFT (0x00000010U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT25_DL2_ANA_CTRL_FSM_STATE_MAX (0x0000001FU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT25_DL2_BIST_BAL_STATUS_MASK (0x0000FFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT25_DL2_BIST_BAL_STATUS_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT25_DL2_BIST_BAL_STATUS_MAX (0x0000FFFFU)
+
+/* DL2_TX_DIG_TBIT26 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT26_DL2_TM_DATA_ESC_RX_FSM_STATE_MASK (0xF8000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT26_DL2_TM_DATA_ESC_RX_FSM_STATE_SHIFT (0x0000001BU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT26_DL2_TM_DATA_ESC_RX_FSM_STATE_MAX (0x0000001FU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT26_DL2_TM_DATA_ESCTX_CTRL_FSM_STATE_MASK (0x07FE0000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT26_DL2_TM_DATA_ESCTX_CTRL_FSM_STATE_SHIFT (0x00000011U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT26_DL2_TM_DATA_ESCTX_CTRL_FSM_STATE_MAX (0x000003FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT26_DL2_TM_DATA_ESCTX_DATA_FSM_STATE_MASK (0x0001F000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT26_DL2_TM_DATA_ESCTX_DATA_FSM_STATE_SHIFT (0x0000000CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT26_DL2_TM_DATA_ESCTX_DATA_FSM_STATE_MAX (0x0000001FU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT26_DL2_TM_HS_PATH_FSM_STATE_MASK (0x00000FFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT26_DL2_TM_HS_PATH_FSM_STATE_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT26_DL2_TM_HS_PATH_FSM_STATE_MAX (0x00000FFFU)
+
+/* DL2_TX_DIG_TBIT28 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT28_DL2_TM_ANA_COMP_OUTS_MASK (0x0000FF00U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT28_DL2_TM_ANA_COMP_OUTS_SHIFT (0x00000008U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT28_DL2_TM_ANA_COMP_OUTS_MAX (0x000000FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT28_DL2_UNUSED_7_0_MASK (0x000000FFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT28_DL2_UNUSED_7_0_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT28_DL2_UNUSED_7_0_MAX (0x000000FFU)
+
+/* DL2_TX_DIG_TBIT29 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT29_DL2_TM_CUR_STATE_ULPTX_CHE_MASK (0x03000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT29_DL2_TM_CUR_STATE_ULPTX_CHE_SHIFT (0x00000018U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT29_DL2_TM_CUR_STATE_ULPTX_CHE_MAX (0x00000003U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT29_DL2_TM_CUR_STATE_ULPRX_CHE_MASK (0x00E00000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT29_DL2_TM_CUR_STATE_ULPRX_CHE_SHIFT (0x00000015U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT29_DL2_TM_CUR_STATE_ULPRX_CHE_MAX (0x00000007U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT29_DL2_TM_CUR_STATE_LPCD_CHE_MASK (0x001C0000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT29_DL2_TM_CUR_STATE_LPCD_CHE_SHIFT (0x00000012U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT29_DL2_TM_CUR_STATE_LPCD_CHE_MAX (0x00000007U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT29_DL2_TM_CUR_STATE_LPRX_CHE_MASK (0x00038000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT29_DL2_TM_CUR_STATE_LPRX_CHE_SHIFT (0x0000000FU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT29_DL2_TM_CUR_STATE_LPRX_CHE_MAX (0x00000007U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT29_DL2_TM_CUR_STATE_CTRLR_MASK (0x00007800U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT29_DL2_TM_CUR_STATE_CTRLR_SHIFT (0x0000000BU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT29_DL2_TM_CUR_STATE_CTRLR_MAX (0x0000000FU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT29_DL2_BIST_DATA_LANE_PASS_MASK (0x00000400U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT29_DL2_BIST_DATA_LANE_PASS_SHIFT (0x0000000AU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT29_DL2_BIST_DATA_LANE_PASS_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT29_DL2_BIST_LPRX_PASS_MASK (0x00000200U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT29_DL2_BIST_LPRX_PASS_SHIFT (0x00000009U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT29_DL2_BIST_LPRX_PASS_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT29_DL2_BIST_LPCD_PASS_MASK (0x00000100U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT29_DL2_BIST_LPCD_PASS_SHIFT (0x00000008U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT29_DL2_BIST_LPCD_PASS_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT29_DL2_BIST_ULPRX_PASS_MASK (0x00000080U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT29_DL2_BIST_ULPRX_PASS_SHIFT (0x00000007U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT29_DL2_BIST_ULPRX_PASS_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT29_DL2_BIST_ULPTX_PASS_MASK (0x00000040U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT29_DL2_BIST_ULPTX_PASS_SHIFT (0x00000006U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT29_DL2_BIST_ULPTX_PASS_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT29_DL2_BIST_HS_NEG_ERR_MASK (0x00000020U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT29_DL2_BIST_HS_NEG_ERR_SHIFT (0x00000005U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT29_DL2_BIST_HS_NEG_ERR_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT29_DL2_BIST_HS_POS_ERR_MASK (0x00000010U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT29_DL2_BIST_HS_POS_ERR_SHIFT (0x00000004U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT29_DL2_BIST_HS_POS_ERR_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT29_DL2_BIST_POS_SYNC_MASK (0x00000008U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT29_DL2_BIST_POS_SYNC_SHIFT (0x00000003U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT29_DL2_BIST_POS_SYNC_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT29_DL2_BIST_NEG_SYNC_MASK (0x00000004U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT29_DL2_BIST_NEG_SYNC_SHIFT (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT29_DL2_BIST_NEG_SYNC_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT29_DL2_BIST_CMPLT_MASK (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT29_DL2_BIST_CMPLT_SHIFT (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT29_DL2_BIST_CMPLT_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT29_DL2_BIST_EN_STATUS_MASK (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT29_DL2_BIST_EN_STATUS_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT29_DL2_BIST_EN_STATUS_MAX (0x00000001U)
+
+/* DL2_TX_DIG_TBIT30 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT30_DL2_BIST_PAT_CHE_PKT_CNT_NEG_MASK (0xFFFF0000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT30_DL2_BIST_PAT_CHE_PKT_CNT_NEG_SHIFT (0x00000010U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT30_DL2_BIST_PAT_CHE_PKT_CNT_NEG_MAX (0x0000FFFFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT30_DL2_BIST_PAT_CHE_PKT_CNT_POS_MASK (0x0000FFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT30_DL2_BIST_PAT_CHE_PKT_CNT_POS_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT30_DL2_BIST_PAT_CHE_PKT_CNT_POS_MAX (0x0000FFFFU)
+
+/* DL2_TX_DIG_TBIT31 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT31_DL2_BIST_PAT_CHE_ERR_CNT_NEG_MASK (0xFFFF0000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT31_DL2_BIST_PAT_CHE_ERR_CNT_NEG_SHIFT (0x00000010U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT31_DL2_BIST_PAT_CHE_ERR_CNT_NEG_MAX (0x0000FFFFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT31_DL2_BIST_PAT_CHE_ERR_CNT_POS_MASK (0x0000FFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT31_DL2_BIST_PAT_CHE_ERR_CNT_POS_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT31_DL2_BIST_PAT_CHE_ERR_CNT_POS_MAX (0x0000FFFFU)
+
+/* DL2_TX_DIG_TBIT32 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT32_DL2_DIG_TBIT32_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT32_DL2_DIG_TBIT32_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT32_DL2_DIG_TBIT32_MAX (0xFFFFFFFFU)
+
+/* DL2_TX_DIG_TBIT33 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT33_DL2_DIG_TBIT33_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT33_DL2_DIG_TBIT33_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT33_DL2_DIG_TBIT33_MAX (0xFFFFFFFFU)
+
+/* DL2_TX_DIG_TBIT34 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT34_DL2_DIG_TBIT34_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT34_DL2_DIG_TBIT34_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT34_DL2_DIG_TBIT34_MAX (0xFFFFFFFFU)
+
+/* DL2_TX_DIG_TBIT35 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT35_DL2_DIG_TBIT35_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT35_DL2_DIG_TBIT35_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT35_DL2_DIG_TBIT35_MAX (0xFFFFFFFFU)
+
+/* DL2_TX_DIG_TBIT36 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT36_DL2_DIG_TBIT36_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT36_DL2_DIG_TBIT36_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL2_TX_DIG_TBIT36_DL2_DIG_TBIT36_MAX (0xFFFFFFFFU)
+
+/* DL3_TX_ANA_TBIT0 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_ANA_TBIT0_DL3_ANA_TBIT0_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_ANA_TBIT0_DL3_ANA_TBIT0_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_ANA_TBIT0_DL3_ANA_TBIT0_MAX (0xFFFFFFFFU)
+
+/* DL3_TX_ANA_TBIT1 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_ANA_TBIT1_DL3_ANA_TBIT1_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_ANA_TBIT1_DL3_ANA_TBIT1_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_ANA_TBIT1_DL3_ANA_TBIT1_MAX (0xFFFFFFFFU)
+
+/* DL3_TX_ANA_TBIT2 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_ANA_TBIT2_DL3_ANA_TBIT2_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_ANA_TBIT2_DL3_ANA_TBIT2_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_ANA_TBIT2_DL3_ANA_TBIT2_MAX (0xFFFFFFFFU)
+
+/* DL3_TX_ANA_TBIT3 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_ANA_TBIT3_DL3_ANA_TBIT3_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_ANA_TBIT3_DL3_ANA_TBIT3_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_ANA_TBIT3_DL3_ANA_TBIT3_MAX (0xFFFFFFFFU)
+
+/* DL3_TX_ANA_TBIT4 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_ANA_TBIT4_DL3_ANA_TBIT4_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_ANA_TBIT4_DL3_ANA_TBIT4_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_ANA_TBIT4_DL3_ANA_TBIT4_MAX (0xFFFFFFFFU)
+
+/* DL3_TX_DIG_TBIT0 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT0_DL3_UNUSED_31_13_MASK (0xFFFFE000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT0_DL3_UNUSED_31_13_SHIFT (0x0000000DU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT0_DL3_UNUSED_31_13_MAX (0x0007FFFFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT0_DL3_ULPS_PULLDN_CNT_MASK (0x00001F00U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT0_DL3_ULPS_PULLDN_CNT_SHIFT (0x00000008U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT0_DL3_ULPS_PULLDN_CNT_MAX (0x0000001FU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT0_DL3_UNUSED_7_5_MASK (0x000000E0U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT0_DL3_UNUSED_7_5_SHIFT (0x00000005U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT0_DL3_UNUSED_7_5_MAX (0x00000007U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT0_DL3_LDO_EN_CNT_MASK (0x0000001FU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT0_DL3_LDO_EN_CNT_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT0_DL3_LDO_EN_CNT_MAX (0x0000001FU)
+
+/* DL3_TX_DIG_TBIT1 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT1_DL3_TEST_LPTX_DP_MASK (0x00200000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT1_DL3_TEST_LPTX_DP_SHIFT (0x00000015U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT1_DL3_TEST_LPTX_DP_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT1_DL3_TEST_LPTX_DN_MASK (0x00100000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT1_DL3_TEST_LPTX_DN_SHIFT (0x00000014U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT1_DL3_TEST_LPTX_DN_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT1_DL3_TEST_LPTX_EN_MASK (0x00080000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT1_DL3_TEST_LPTX_EN_SHIFT (0x00000013U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT1_DL3_TEST_LPTX_EN_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT1_DL3_TM_READY_SKEW_CAL_MASK (0x00040000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT1_DL3_TM_READY_SKEW_CAL_SHIFT (0x00000012U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT1_DL3_TM_READY_SKEW_CAL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT1_DL3_TM_HS_PREP_HAFCYC_OVERRIDE_MASK (0x00020000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT1_DL3_TM_HS_PREP_HAFCYC_OVERRIDE_SHIFT (0x00000011U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT1_DL3_TM_HS_PREP_HAFCYC_OVERRIDE_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT1_DL3_TM_HS_PREP_HSFCYC_MASK (0x00010000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT1_DL3_TM_HS_PREP_HSFCYC_SHIFT (0x00000010U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT1_DL3_TM_HS_PREP_HSFCYC_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT1_DL3_HS_TRAIL_OFFSET_MASK (0x0000F000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT1_DL3_HS_TRAIL_OFFSET_SHIFT (0x0000000CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT1_DL3_HS_TRAIL_OFFSET_MAX (0x0000000FU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT1_DL3_HS_ZERO_OFFSET_MASK (0x00000F00U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT1_DL3_HS_ZERO_OFFSET_SHIFT (0x00000008U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT1_DL3_HS_ZERO_OFFSET_MAX (0x0000000FU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT1_DL3_HS_PREP_OFFSET_MASK (0x000000F0U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT1_DL3_HS_PREP_OFFSET_SHIFT (0x00000004U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT1_DL3_HS_PREP_OFFSET_MAX (0x0000000FU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT1_DL3_HS_TLPX_OFFSET_MASK (0x0000000FU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT1_DL3_HS_TLPX_OFFSET_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT1_DL3_HS_TLPX_OFFSET_MAX (0x0000000FU)
+
+/* DL3_TX_DIG_TBIT2 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT2_DL3_TM_SKEW_CAL_SEQ_MASK (0x07F80000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT2_DL3_TM_SKEW_CAL_SEQ_SHIFT (0x00000013U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT2_DL3_TM_SKEW_CAL_SEQ_MAX (0x000000FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT2_DL3_TM_SKEW_CAL_SEQ_SEL_MASK (0x00040000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT2_DL3_TM_SKEW_CAL_SEQ_SEL_SHIFT (0x00000012U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT2_DL3_TM_SKEW_CAL_SEQ_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT2_DL3_TM_SKEW_CAL_SYNC_PKT_MASK (0x0003FC00U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT2_DL3_TM_SKEW_CAL_SYNC_PKT_SHIFT (0x0000000AU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT2_DL3_TM_SKEW_CAL_SYNC_PKT_MAX (0x000000FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT2_DL3_TM_SKEW_CAL_SYNC_PKT_SEL_MASK (0x00000200U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT2_DL3_TM_SKEW_CAL_SYNC_PKT_SEL_SHIFT (0x00000009U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT2_DL3_TM_SKEW_CAL_SYNC_PKT_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT2_DL3_TM_HS_SYNC_PKT_MASK (0x000001FEU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT2_DL3_TM_HS_SYNC_PKT_SHIFT (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT2_DL3_TM_HS_SYNC_PKT_MAX (0x000000FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT2_DL3_TM_HS_SYNC_PKT_SEL_MASK (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT2_DL3_TM_HS_SYNC_PKT_SEL_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT2_DL3_TM_HS_SYNC_PKT_SEL_MAX (0x00000001U)
+
+/* DL3_TX_DIG_TBIT3 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT3_DL3_SERSYNTH_LOOPBACK_MASK (0x00000020U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT3_DL3_SERSYNTH_LOOPBACK_SHIFT (0x00000005U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT3_DL3_SERSYNTH_LOOPBACK_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT3_DL3_BAL_FORCE_STATE_MASK (0x0000001CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT3_DL3_BAL_FORCE_STATE_SHIFT (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT3_DL3_BAL_FORCE_STATE_MAX (0x00000007U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT3_DL3_BAL_FORCE_EN_MASK (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT3_DL3_BAL_FORCE_EN_SHIFT (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT3_DL3_BAL_FORCE_EN_MAX (0x00000001U)
+
+/* DL3_TX_DIG_TBIT4 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT4_DL3_CONTENTION_EN_MASK (0x00008000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT4_DL3_CONTENTION_EN_SHIFT (0x0000000FU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT4_DL3_CONTENTION_EN_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT4_DL3_UNUSED_14_13_MASK (0x00006000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT4_DL3_UNUSED_14_13_SHIFT (0x0000000DU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT4_DL3_UNUSED_14_13_MAX (0x00000003U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT4_DL3_FORCE_RX_MODE_MASK (0x00001000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT4_DL3_FORCE_RX_MODE_SHIFT (0x0000000CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT4_DL3_FORCE_RX_MODE_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT4_DL3_TEST_DATA_LPTX_DP_SEL_MASK (0x00000800U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT4_DL3_TEST_DATA_LPTX_DP_SEL_SHIFT (0x0000000BU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT4_DL3_TEST_DATA_LPTX_DP_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT4_DL3_TEST_DATA_LPTX_DN_SEL_MASK (0x00000400U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT4_DL3_TEST_DATA_LPTX_DN_SEL_SHIFT (0x0000000AU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT4_DL3_TEST_DATA_LPTX_DN_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT4_DL3_TEST_DATA_LPTX_MASK (0x000003FCU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT4_DL3_TEST_DATA_LPTX_SHIFT (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT4_DL3_TEST_DATA_LPTX_MAX (0x000000FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT4_DL3_TEST_DATA_LPTX_RSTN_MASK (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT4_DL3_TEST_DATA_LPTX_RSTN_SHIFT (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT4_DL3_TEST_DATA_LPTX_RSTN_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT4_DL3_TEST_DATA_LPTX_EN_MASK (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT4_DL3_TEST_DATA_LPTX_EN_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT4_DL3_TEST_DATA_LPTX_EN_MAX (0x00000001U)
+
+/* DL3_TX_DIG_TBIT5 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT5_DL3_DIG_TBIT5_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT5_DL3_DIG_TBIT5_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT5_DL3_DIG_TBIT5_MAX (0xFFFFFFFFU)
+
+/* DL3_TX_DIG_TBIT6 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT6_DL3_DIG_TBIT6_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT6_DL3_DIG_TBIT6_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT6_DL3_DIG_TBIT6_MAX (0xFFFFFFFFU)
+
+/* DL3_TX_DIG_TBIT7 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT7_DL3_DIG_TBIT7_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT7_DL3_DIG_TBIT7_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT7_DL3_DIG_TBIT7_MAX (0xFFFFFFFFU)
+
+/* DL3_TX_DIG_TBIT8 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT8_DL3_DIG_TBIT8_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT8_DL3_DIG_TBIT8_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT8_DL3_DIG_TBIT8_MAX (0xFFFFFFFFU)
+
+/* DL3_TX_DIG_TBIT9 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT9_DL3_DIG_TBIT9_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT9_DL3_DIG_TBIT9_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT9_DL3_DIG_TBIT9_MAX (0xFFFFFFFFU)
+
+/* DL3_TX_DIG_TBIT10 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT10_DL3_BIST_WAIT_TIME_MASK (0x01E00000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT10_DL3_BIST_WAIT_TIME_SHIFT (0x00000015U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT10_DL3_BIST_WAIT_TIME_MAX (0x0000000FU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT10_DL3_BIST_ULPTX_TEST_TIME_MASK (0x001FE000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT10_DL3_BIST_ULPTX_TEST_TIME_SHIFT (0x0000000DU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT10_DL3_BIST_ULPTX_TEST_TIME_MAX (0x000000FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT10_DL3_BIST_SEND_CONFIG_MASK (0x00001800U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT10_DL3_BIST_SEND_CONFIG_SHIFT (0x0000000BU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT10_DL3_BIST_SEND_CONFIG_MAX (0x00000003U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT10_DL3_BIST_DIG_TO_DIG_LOOPBK_MASK (0x00000400U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT10_DL3_BIST_DIG_TO_DIG_LOOPBK_SHIFT (0x0000000AU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT10_DL3_BIST_DIG_TO_DIG_LOOPBK_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT10_DL3_BIST_RUN_NEGEDGE_FIRST_MASK (0x00000200U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT10_DL3_BIST_RUN_NEGEDGE_FIRST_SHIFT (0x00000009U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT10_DL3_BIST_RUN_NEGEDGE_FIRST_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT10_DL3_BIST_LENGTH_OF_DESKEW_MASK (0x000001FCU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT10_DL3_BIST_LENGTH_OF_DESKEW_SHIFT (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT10_DL3_BIST_LENGTH_OF_DESKEW_MAX (0x0000007FU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT10_DL3_BIST_LOOPBK_MODE_MASK (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT10_DL3_BIST_LOOPBK_MODE_SHIFT (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT10_DL3_BIST_LOOPBK_MODE_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT10_DL3_BIST_EN_MASK (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT10_DL3_BIST_EN_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT10_DL3_BIST_EN_MAX (0x00000001U)
+
+/* DL3_TX_DIG_TBIT11 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT11_DL3_BIST_FRM_IDLE_TIME_MASK (0xFF000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT11_DL3_BIST_FRM_IDLE_TIME_SHIFT (0x00000018U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT11_DL3_BIST_FRM_IDLE_TIME_MAX (0x000000FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT11_DL3_BIST_PKT_NUM_MASK (0x00FF0000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT11_DL3_BIST_PKT_NUM_SHIFT (0x00000010U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT11_DL3_BIST_PKT_NUM_MAX (0x000000FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT11_DL3_BIST_INF_MODE_MASK (0x00008000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT11_DL3_BIST_INF_MODE_SHIFT (0x0000000FU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT11_DL3_BIST_INF_MODE_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT11_DL3_BIST_FRM_NUM_MASK (0x00007F80U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT11_DL3_BIST_FRM_NUM_SHIFT (0x00000007U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT11_DL3_BIST_FRM_NUM_MAX (0x000000FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT11_DL3_BIST_CLEAR_MASK (0x00000040U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT11_DL3_BIST_CLEAR_SHIFT (0x00000006U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT11_DL3_BIST_CLEAR_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT11_DL3_BIST_PRBS_MASK (0x00000030U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT11_DL3_BIST_PRBS_SHIFT (0x00000004U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT11_DL3_BIST_PRBS_MAX (0x00000003U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT11_DL3_BIST_TEST_MODE_MASK (0x0000000EU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT11_DL3_BIST_TEST_MODE_SHIFT (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT11_DL3_BIST_TEST_MODE_MAX (0x00000007U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT11_DL3_UNUSED_0_MASK (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT11_DL3_UNUSED_0_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT11_DL3_UNUSED_0_MAX (0x00000001U)
+
+/* DL3_TX_DIG_TBIT12 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT12_DL3_BIST_RUN_LENGTH_MASK (0x00000FFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT12_DL3_BIST_RUN_LENGTH_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT12_DL3_BIST_RUN_LENGTH_MAX (0x00000FFFU)
+
+/* DL3_TX_DIG_TBIT13 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT13_DL3_UNUSED_31_8_MASK (0xFFFFFF00U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT13_DL3_UNUSED_31_8_SHIFT (0x00000008U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT13_DL3_UNUSED_31_8_MAX (0x00FFFFFFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT13_DL3_BIST_IDLE_TIME_MASK (0x000000FFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT13_DL3_BIST_IDLE_TIME_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT13_DL3_BIST_IDLE_TIME_MAX (0x000000FFU)
+
+/* DL3_TX_DIG_TBIT14 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT14_DL3_BIST_PKT4_MASK (0xFF000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT14_DL3_BIST_PKT4_SHIFT (0x00000018U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT14_DL3_BIST_PKT4_MAX (0x000000FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT14_DL3_BIST_PKT3_MASK (0x00FF0000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT14_DL3_BIST_PKT3_SHIFT (0x00000010U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT14_DL3_BIST_PKT3_MAX (0x000000FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT14_DL3_BIST_PKT2_MASK (0x0000FF00U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT14_DL3_BIST_PKT2_SHIFT (0x00000008U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT14_DL3_BIST_PKT2_MAX (0x000000FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT14_DL3_BIST_PKT1_MASK (0x000000FFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT14_DL3_BIST_PKT1_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT14_DL3_BIST_PKT1_MAX (0x000000FFU)
+
+/* DL3_TX_DIG_TBIT15 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT15_DL3_BIST_LFSR_FREEZE_MASK (0x00002000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT15_DL3_BIST_LFSR_FREEZE_SHIFT (0x0000000DU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT15_DL3_BIST_LFSR_FREEZE_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT15_DL3_BIST_ERR_INJ_POINT_MASK (0x00001FFEU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT15_DL3_BIST_ERR_INJ_POINT_SHIFT (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT15_DL3_BIST_ERR_INJ_POINT_MAX (0x00000FFFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT15_DL3_BIST_ERR_INJ_EN_MASK (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT15_DL3_BIST_ERR_INJ_EN_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT15_DL3_BIST_ERR_INJ_EN_MAX (0x00000001U)
+
+/* DL3_TX_DIG_TBIT16 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT16_DL3_DIG_TBIT16_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT16_DL3_DIG_TBIT16_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT16_DL3_DIG_TBIT16_MAX (0xFFFFFFFFU)
+
+/* DL3_TX_DIG_TBIT17 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT17_DL3_DIG_TBIT17_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT17_DL3_DIG_TBIT17_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT17_DL3_DIG_TBIT17_MAX (0xFFFFFFFFU)
+
+/* DL3_TX_DIG_TBIT18 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT18_DL3_DIG_TBIT18_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT18_DL3_DIG_TBIT18_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT18_DL3_DIG_TBIT18_MAX (0xFFFFFFFFU)
+
+/* DL3_TX_DIG_TBIT19 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT19_DL3_DIG_TBIT19_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT19_DL3_DIG_TBIT19_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT19_DL3_DIG_TBIT19_MAX (0xFFFFFFFFU)
+
+/* DL3_TX_DIG_TBIT20 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT20_DL3_TM_ISO_EN_MASK (0x80000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT20_DL3_TM_ISO_EN_SHIFT (0x0000001FU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT20_DL3_TM_ISO_EN_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT20_DL3_TM_LOAD_DPDN_SEL_MASK (0x40000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT20_DL3_TM_LOAD_DPDN_SEL_SHIFT (0x0000001EU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT20_DL3_TM_LOAD_DPDN_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT20_DL3_TM_LOAD_DPDN_MASK (0x38000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT20_DL3_TM_LOAD_DPDN_SHIFT (0x0000001BU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT20_DL3_TM_LOAD_DPDN_MAX (0x00000007U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT20_DL3_TM_HSTX_DATA_RATE_SEL_MASK (0x04000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT20_DL3_TM_HSTX_DATA_RATE_SEL_SHIFT (0x0000001AU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT20_DL3_TM_HSTX_DATA_RATE_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT20_DL3_TM_HSTX_DATE_RATE_MASK (0x03000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT20_DL3_TM_HSTX_DATE_RATE_SHIFT (0x00000018U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT20_DL3_TM_HSTX_DATE_RATE_MAX (0x00000003U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT20_DL3_TM_BIST_ULP_RCV_EN_SEL_MASK (0x00800000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT20_DL3_TM_BIST_ULP_RCV_EN_SEL_SHIFT (0x00000017U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT20_DL3_TM_BIST_ULP_RCV_EN_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT20_DL3_TM_BIST_ULP_RCV_EN_MASK (0x00400000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT20_DL3_TM_BIST_ULP_RCV_EN_SHIFT (0x00000016U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT20_DL3_TM_BIST_ULP_RCV_EN_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT20_DL3_TM_ULPS_PULDN_SEL_MASK (0x00200000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT20_DL3_TM_ULPS_PULDN_SEL_SHIFT (0x00000015U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT20_DL3_TM_ULPS_PULDN_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT20_DL3_TM_ULPS_PULDN_MASK (0x00100000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT20_DL3_TM_ULPS_PULDN_SHIFT (0x00000014U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT20_DL3_TM_ULPS_PULDN_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT20_DL3_TM_BIST_SMPLR_CLK_EDGE_SEL_MASK (0x00080000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT20_DL3_TM_BIST_SMPLR_CLK_EDGE_SEL_SHIFT (0x00000013U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT20_DL3_TM_BIST_SMPLR_CLK_EDGE_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT20_DL3_TM_BIST_SMPLR_CLK_EDGE_MASK (0x00040000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT20_DL3_TM_BIST_SMPLR_CLK_EDGE_SHIFT (0x00000012U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT20_DL3_TM_BIST_SMPLR_CLK_EDGE_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT20_DL3_TM_BIST_EN_SEL_MASK (0x00020000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT20_DL3_TM_BIST_EN_SEL_SHIFT (0x00000011U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT20_DL3_TM_BIST_EN_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT20_DL3_TM_BIST_EN_MASK (0x00010000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT20_DL3_TM_BIST_EN_SHIFT (0x00000010U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT20_DL3_TM_BIST_EN_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT20_DL3_TM_LPTX_TRST_SEL_MASK (0x00008000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT20_DL3_TM_LPTX_TRST_SEL_SHIFT (0x0000000FU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT20_DL3_TM_LPTX_TRST_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT20_DL3_TM_LPTX_TRST_MASK (0x00004000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT20_DL3_TM_LPTX_TRST_SHIFT (0x0000000EU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT20_DL3_TM_LPTX_TRST_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT20_DL3_TM_LPTX_RST_SEL_MASK (0x00002000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT20_DL3_TM_LPTX_RST_SEL_SHIFT (0x0000000DU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT20_DL3_TM_LPTX_RST_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT20_DL3_TM_LPTX_RST_MASK (0x00001000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT20_DL3_TM_LPTX_RST_SHIFT (0x0000000CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT20_DL3_TM_LPTX_RST_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT20_DL3_TM_LPTX_DP_SEL_MASK (0x00000800U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT20_DL3_TM_LPTX_DP_SEL_SHIFT (0x0000000BU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT20_DL3_TM_LPTX_DP_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT20_DL3_TM_LPTX_DP_MASK (0x00000400U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT20_DL3_TM_LPTX_DP_SHIFT (0x0000000AU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT20_DL3_TM_LPTX_DP_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT20_DL3_TM_LPTX_DN_SEL_MASK (0x00000200U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT20_DL3_TM_LPTX_DN_SEL_SHIFT (0x00000009U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT20_DL3_TM_LPTX_DN_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT20_DL3_TM_LPTX_DN_MASK (0x00000100U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT20_DL3_TM_LPTX_DN_SHIFT (0x00000008U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT20_DL3_TM_LPTX_DN_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT20_DL3_TM_LDO_REF_EN_SEL_MASK (0x00000080U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT20_DL3_TM_LDO_REF_EN_SEL_SHIFT (0x00000007U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT20_DL3_TM_LDO_REF_EN_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT20_DL3_TM_LDO_REF_EN_MASK (0x00000040U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT20_DL3_TM_LDO_REF_EN_SHIFT (0x00000006U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT20_DL3_TM_LDO_REF_EN_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT20_DL3_TM_HSTX_TRST_SEL_MASK (0x00000020U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT20_DL3_TM_HSTX_TRST_SEL_SHIFT (0x00000005U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT20_DL3_TM_HSTX_TRST_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT20_DL3_TM_HSTX_TRST_MASK (0x00000010U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT20_DL3_TM_HSTX_TRST_SHIFT (0x00000004U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT20_DL3_TM_HSTX_TRST_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT20_DL3_TM_HSTX_RQST_SEL_MASK (0x00000008U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT20_DL3_TM_HSTX_RQST_SEL_SHIFT (0x00000003U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT20_DL3_TM_HSTX_RQST_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT20_DL3_TM_HSTX_RQST_MASK (0x00000004U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT20_DL3_TM_HSTX_RQST_SHIFT (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT20_DL3_TM_HSTX_RQST_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT20_DL3_TM_GLOBAL_PD_SEL_MASK (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT20_DL3_TM_GLOBAL_PD_SEL_SHIFT (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT20_DL3_TM_GLOBAL_PD_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT20_DL3_TM_GLOBAL_PD_MASK (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT20_DL3_TM_GLOBAL_PD_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT20_DL3_TM_GLOBAL_PD_MAX (0x00000001U)
+
+/* DL3_TX_DIG_TBIT21 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT21_DL3_TM_SERSYNTH_RST_N_SEL_MASK (0x00004000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT21_DL3_TM_SERSYNTH_RST_N_SEL_SHIFT (0x0000000EU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT21_DL3_TM_SERSYNTH_RST_N_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT21_DL3_TM_SERSYNTH_RST_N_MASK (0x00002000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT21_DL3_TM_SERSYNTH_RST_N_SHIFT (0x0000000DU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT21_DL3_TM_SERSYNTH_RST_N_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT21_DL3_TM_SWAP_DPDN_SEL_MASK (0x00001000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT21_DL3_TM_SWAP_DPDN_SEL_SHIFT (0x0000000CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT21_DL3_TM_SWAP_DPDN_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT21_DL3_TM_SWAP_DPDN_EN_MASK (0x00000800U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT21_DL3_TM_SWAP_DPDN_EN_SHIFT (0x0000000BU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT21_DL3_TM_SWAP_DPDN_EN_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT21_DL3_TM_SERSYNTH_EN_SEL_MASK (0x00000400U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT21_DL3_TM_SERSYNTH_EN_SEL_SHIFT (0x0000000AU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT21_DL3_TM_SERSYNTH_EN_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT21_DL3_TM_SERSYNTH_EN_MASK (0x00000200U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT21_DL3_TM_SERSYNTH_EN_SHIFT (0x00000009U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT21_DL3_TM_SERSYNTH_EN_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT21_DL3_TM_TX_DATA_HS_SEL_MASK (0x00000100U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT21_DL3_TM_TX_DATA_HS_SEL_SHIFT (0x00000008U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT21_DL3_TM_TX_DATA_HS_SEL_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT21_DL3_TM_TX_DATA_HS_MASK (0x000000FFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT21_DL3_TM_TX_DATA_HS_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT21_DL3_TM_TX_DATA_HS_MAX (0x000000FFU)
+
+/* DL3_TX_DIG_TBIT22 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT22_DL3_DIG_TBIT22_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT22_DL3_DIG_TBIT22_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT22_DL3_DIG_TBIT22_MAX (0xFFFFFFFFU)
+
+/* DL3_TX_DIG_TBIT23 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT23_DL3_DIG_TBIT23_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT23_DL3_DIG_TBIT23_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT23_DL3_DIG_TBIT23_MAX (0xFFFFFFFFU)
+
+/* DL3_TX_DIG_TBIT24 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT24_DL3_DIG_TBIT24_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT24_DL3_DIG_TBIT24_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT24_DL3_DIG_TBIT24_MAX (0xFFFFFFFFU)
+
+/* DL3_TX_ANA_TBIT5 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_ANA_TBIT5_DL3_ANA_TBIT5_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_ANA_TBIT5_DL3_ANA_TBIT5_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_ANA_TBIT5_DL3_ANA_TBIT5_MAX (0xFFFFFFFFU)
+
+/* DL3_TX_DIG_TBIT25 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT25_DL3_ANA_CTRL_FSM_STATE_MASK (0x001F0000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT25_DL3_ANA_CTRL_FSM_STATE_SHIFT (0x00000010U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT25_DL3_ANA_CTRL_FSM_STATE_MAX (0x0000001FU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT25_DL3_BIST_BAL_STATUS_MASK (0x0000FFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT25_DL3_BIST_BAL_STATUS_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT25_DL3_BIST_BAL_STATUS_MAX (0x0000FFFFU)
+
+/* DL3_TX_DIG_TBIT26 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT26_DL3_TM_DATA_ESC_RX_FSM_STATE_MASK (0xF8000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT26_DL3_TM_DATA_ESC_RX_FSM_STATE_SHIFT (0x0000001BU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT26_DL3_TM_DATA_ESC_RX_FSM_STATE_MAX (0x0000001FU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT26_DL3_TM_DATA_ESCTX_CTRL_FSM_STATE_MASK (0x07FE0000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT26_DL3_TM_DATA_ESCTX_CTRL_FSM_STATE_SHIFT (0x00000011U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT26_DL3_TM_DATA_ESCTX_CTRL_FSM_STATE_MAX (0x000003FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT26_DL3_TM_DATA_ESCTX_DATA_FSM_STATE_MASK (0x0001F000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT26_DL3_TM_DATA_ESCTX_DATA_FSM_STATE_SHIFT (0x0000000CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT26_DL3_TM_DATA_ESCTX_DATA_FSM_STATE_MAX (0x0000001FU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT26_DL3_TM_HS_PATH_FSM_STATE_MASK (0x00000FFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT26_DL3_TM_HS_PATH_FSM_STATE_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT26_DL3_TM_HS_PATH_FSM_STATE_MAX (0x00000FFFU)
+
+/* DL3_TX_DIG_TBIT28 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT28_DL3_TM_ANA_COMP_OUTS_MASK (0x0000FF00U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT28_DL3_TM_ANA_COMP_OUTS_SHIFT (0x00000008U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT28_DL3_TM_ANA_COMP_OUTS_MAX (0x000000FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT28_DL3_UNUSED_7_0_MASK (0x000000FFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT28_DL3_UNUSED_7_0_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT28_DL3_UNUSED_7_0_MAX (0x000000FFU)
+
+/* DL3_TX_DIG_TBIT29 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT29_DL3_TM_CUR_STATE_ULPTX_CHE_MASK (0x03000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT29_DL3_TM_CUR_STATE_ULPTX_CHE_SHIFT (0x00000018U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT29_DL3_TM_CUR_STATE_ULPTX_CHE_MAX (0x00000003U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT29_DL3_TM_CUR_STATE_ULPRX_CHE_MASK (0x00E00000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT29_DL3_TM_CUR_STATE_ULPRX_CHE_SHIFT (0x00000015U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT29_DL3_TM_CUR_STATE_ULPRX_CHE_MAX (0x00000007U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT29_DL3_TM_CUR_STATE_LPCD_CHE_MASK (0x001C0000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT29_DL3_TM_CUR_STATE_LPCD_CHE_SHIFT (0x00000012U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT29_DL3_TM_CUR_STATE_LPCD_CHE_MAX (0x00000007U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT29_DL3_TM_CUR_STATE_LPRX_CHE_MASK (0x00038000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT29_DL3_TM_CUR_STATE_LPRX_CHE_SHIFT (0x0000000FU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT29_DL3_TM_CUR_STATE_LPRX_CHE_MAX (0x00000007U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT29_DL3_TM_CUR_STATE_CTRLR_MASK (0x00007800U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT29_DL3_TM_CUR_STATE_CTRLR_SHIFT (0x0000000BU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT29_DL3_TM_CUR_STATE_CTRLR_MAX (0x0000000FU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT29_DL3_BIST_DATA_LANE_PASS_MASK (0x00000400U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT29_DL3_BIST_DATA_LANE_PASS_SHIFT (0x0000000AU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT29_DL3_BIST_DATA_LANE_PASS_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT29_DL3_BIST_LPRX_PASS_MASK (0x00000200U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT29_DL3_BIST_LPRX_PASS_SHIFT (0x00000009U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT29_DL3_BIST_LPRX_PASS_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT29_DL3_BIST_LPCD_PASS_MASK (0x00000100U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT29_DL3_BIST_LPCD_PASS_SHIFT (0x00000008U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT29_DL3_BIST_LPCD_PASS_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT29_DL3_BIST_ULPRX_PASS_MASK (0x00000080U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT29_DL3_BIST_ULPRX_PASS_SHIFT (0x00000007U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT29_DL3_BIST_ULPRX_PASS_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT29_DL3_BIST_ULPTX_PASS_MASK (0x00000040U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT29_DL3_BIST_ULPTX_PASS_SHIFT (0x00000006U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT29_DL3_BIST_ULPTX_PASS_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT29_DL3_BIST_HS_NEG_ERR_MASK (0x00000020U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT29_DL3_BIST_HS_NEG_ERR_SHIFT (0x00000005U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT29_DL3_BIST_HS_NEG_ERR_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT29_DL3_BIST_HS_POS_ERR_MASK (0x00000010U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT29_DL3_BIST_HS_POS_ERR_SHIFT (0x00000004U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT29_DL3_BIST_HS_POS_ERR_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT29_DL3_BIST_POS_SYNC_MASK (0x00000008U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT29_DL3_BIST_POS_SYNC_SHIFT (0x00000003U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT29_DL3_BIST_POS_SYNC_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT29_DL3_BIST_NEG_SYNC_MASK (0x00000004U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT29_DL3_BIST_NEG_SYNC_SHIFT (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT29_DL3_BIST_NEG_SYNC_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT29_DL3_BIST_CMPLT_MASK (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT29_DL3_BIST_CMPLT_SHIFT (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT29_DL3_BIST_CMPLT_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT29_DL3_BIST_EN_STATUS_MASK (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT29_DL3_BIST_EN_STATUS_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT29_DL3_BIST_EN_STATUS_MAX (0x00000001U)
+
+/* DL3_TX_DIG_TBIT30 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT30_DL3_BIST_PAT_CHE_PKT_CNT_NEG_MASK (0xFFFF0000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT30_DL3_BIST_PAT_CHE_PKT_CNT_NEG_SHIFT (0x00000010U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT30_DL3_BIST_PAT_CHE_PKT_CNT_NEG_MAX (0x0000FFFFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT30_DL3_BIST_PAT_CHE_PKT_CNT_POS_MASK (0x0000FFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT30_DL3_BIST_PAT_CHE_PKT_CNT_POS_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT30_DL3_BIST_PAT_CHE_PKT_CNT_POS_MAX (0x0000FFFFU)
+
+/* DL3_TX_DIG_TBIT31 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT31_DL3_BIST_PAT_CHE_ERR_CNT_NEG_MASK (0xFFFF0000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT31_DL3_BIST_PAT_CHE_ERR_CNT_NEG_SHIFT (0x00000010U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT31_DL3_BIST_PAT_CHE_ERR_CNT_NEG_MAX (0x0000FFFFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT31_DL3_BIST_PAT_CHE_ERR_CNT_POS_MASK (0x0000FFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT31_DL3_BIST_PAT_CHE_ERR_CNT_POS_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT31_DL3_BIST_PAT_CHE_ERR_CNT_POS_MAX (0x0000FFFFU)
+
+/* DL3_TX_DIG_TBIT32 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT32_DL3_DIG_TBIT32_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT32_DL3_DIG_TBIT32_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT32_DL3_DIG_TBIT32_MAX (0xFFFFFFFFU)
+
+/* DL3_TX_DIG_TBIT33 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT33_DL3_DIG_TBIT33_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT33_DL3_DIG_TBIT33_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT33_DL3_DIG_TBIT33_MAX (0xFFFFFFFFU)
+
+/* DL3_TX_DIG_TBIT34 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT34_DL3_DIG_TBIT34_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT34_DL3_DIG_TBIT34_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT34_DL3_DIG_TBIT34_MAX (0xFFFFFFFFU)
+
+/* DL3_TX_DIG_TBIT35 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT35_DL3_DIG_TBIT35_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT35_DL3_DIG_TBIT35_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT35_DL3_DIG_TBIT35_MAX (0xFFFFFFFFU)
+
+/* DL3_TX_DIG_TBIT36 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT36_DL3_DIG_TBIT36_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT36_DL3_DIG_TBIT36_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_DL3_TX_DIG_TBIT36_DL3_DIG_TBIT36_MAX (0xFFFFFFFFU)
+
+/* PCS_TX_DIG_TBIT0 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT0_PCS_BAND_CTL_REG_R_MASK (0x000003E0U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT0_PCS_BAND_CTL_REG_R_SHIFT (0x00000005U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT0_PCS_BAND_CTL_REG_R_MAX (0x0000001FU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT0_PCS_BAND_CTL_REG_L_MASK (0x0000001FU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT0_PCS_BAND_CTL_REG_L_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT0_PCS_BAND_CTL_REG_L_MAX (0x0000001FU)
+
+/* PCS_TX_DIG_TBIT1 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT1_PCS_PSM_CLOCK_FREQ_MASK (0x000001FEU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT1_PCS_PSM_CLOCK_FREQ_SHIFT (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT1_PCS_PSM_CLOCK_FREQ_MAX (0x000000FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT1_PCS_PSM_CLOCK_FREQ_EN_MASK (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT1_PCS_PSM_CLOCK_FREQ_EN_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT1_PCS_PSM_CLOCK_FREQ_EN_MAX (0x00000001U)
+
+/* PCS_TX_DIG_TBIT2 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT2_PCS_POWER_SW_2_TIME_DL_R_3_MASK (0xF0000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT2_PCS_POWER_SW_2_TIME_DL_R_3_SHIFT (0x0000001CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT2_PCS_POWER_SW_2_TIME_DL_R_3_MAX (0x0000000FU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT2_PCS_POWER_SW_2_TIME_DL_R_2_MASK (0x0F000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT2_PCS_POWER_SW_2_TIME_DL_R_2_SHIFT (0x00000018U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT2_PCS_POWER_SW_2_TIME_DL_R_2_MAX (0x0000000FU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT2_PCS_POWER_SW_2_TIME_DL_R_1_MASK (0x00F00000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT2_PCS_POWER_SW_2_TIME_DL_R_1_SHIFT (0x00000014U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT2_PCS_POWER_SW_2_TIME_DL_R_1_MAX (0x0000000FU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT2_PCS_POWER_SW_2_TIME_DL_R_0_MASK (0x000F0000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT2_PCS_POWER_SW_2_TIME_DL_R_0_SHIFT (0x00000010U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT2_PCS_POWER_SW_2_TIME_DL_R_0_MAX (0x0000000FU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT2_PCS_POWER_SW_2_TIME_DL_L_3_MASK (0x0000F000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT2_PCS_POWER_SW_2_TIME_DL_L_3_SHIFT (0x0000000CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT2_PCS_POWER_SW_2_TIME_DL_L_3_MAX (0x0000000FU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT2_PCS_POWER_SW_2_TIME_DL_L_2_MASK (0x00000F00U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT2_PCS_POWER_SW_2_TIME_DL_L_2_SHIFT (0x00000008U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT2_PCS_POWER_SW_2_TIME_DL_L_2_MAX (0x0000000FU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT2_PCS_POWER_SW_2_TIME_DL_L_1_MASK (0x000000F0U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT2_PCS_POWER_SW_2_TIME_DL_L_1_SHIFT (0x00000004U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT2_PCS_POWER_SW_2_TIME_DL_L_1_MAX (0x0000000FU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT2_PCS_POWER_SW_2_TIME_DL_L_0_MASK (0x0000000FU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT2_PCS_POWER_SW_2_TIME_DL_L_0_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT2_PCS_POWER_SW_2_TIME_DL_L_0_MAX (0x0000000FU)
+
+/* PCS_TX_DIG_TBIT3 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT3_PCS_POWER_SW_2_TIME_CMN_MASK (0x00000F00U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT3_PCS_POWER_SW_2_TIME_CMN_SHIFT (0x00000008U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT3_PCS_POWER_SW_2_TIME_CMN_MAX (0x0000000FU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT3_PCS_POWER_SW_2_TIME_CL_R_MASK (0x000000F0U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT3_PCS_POWER_SW_2_TIME_CL_R_SHIFT (0x00000004U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT3_PCS_POWER_SW_2_TIME_CL_R_MAX (0x0000000FU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT3_PCS_POWER_SW_2_TIME_CL_L_MASK (0x0000000FU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT3_PCS_POWER_SW_2_TIME_CL_L_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT3_PCS_POWER_SW_2_TIME_CL_L_MAX (0x0000000FU)
+
+/* PCS_TX_DIG_TBIT4 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT4_PCS_POWER_SW_1_TIME_DL_R_3_MASK (0xF0000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT4_PCS_POWER_SW_1_TIME_DL_R_3_SHIFT (0x0000001CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT4_PCS_POWER_SW_1_TIME_DL_R_3_MAX (0x0000000FU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT4_PCS_POWER_SW_1_TIME_DL_R_2_MASK (0x0F000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT4_PCS_POWER_SW_1_TIME_DL_R_2_SHIFT (0x00000018U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT4_PCS_POWER_SW_1_TIME_DL_R_2_MAX (0x0000000FU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT4_PCS_POWER_SW_1_TIME_DL_R_1_MASK (0x00F00000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT4_PCS_POWER_SW_1_TIME_DL_R_1_SHIFT (0x00000014U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT4_PCS_POWER_SW_1_TIME_DL_R_1_MAX (0x0000000FU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT4_PCS_POWER_SW_1_TIME_DL_R_0_MASK (0x000F0000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT4_PCS_POWER_SW_1_TIME_DL_R_0_SHIFT (0x00000010U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT4_PCS_POWER_SW_1_TIME_DL_R_0_MAX (0x0000000FU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT4_PCS_POWER_SW_1_TIME_DL_L_3_MASK (0x0000F000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT4_PCS_POWER_SW_1_TIME_DL_L_3_SHIFT (0x0000000CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT4_PCS_POWER_SW_1_TIME_DL_L_3_MAX (0x0000000FU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT4_PCS_POWER_SW_1_TIME_DL_L_2_MASK (0x00000F00U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT4_PCS_POWER_SW_1_TIME_DL_L_2_SHIFT (0x00000008U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT4_PCS_POWER_SW_1_TIME_DL_L_2_MAX (0x0000000FU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT4_PCS_POWER_SW_1_TIME_DL_L_1_MASK (0x000000F0U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT4_PCS_POWER_SW_1_TIME_DL_L_1_SHIFT (0x00000004U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT4_PCS_POWER_SW_1_TIME_DL_L_1_MAX (0x0000000FU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT4_PCS_POWER_SW_1_TIME_DL_L_0_MASK (0x0000000FU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT4_PCS_POWER_SW_1_TIME_DL_L_0_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT4_PCS_POWER_SW_1_TIME_DL_L_0_MAX (0x0000000FU)
+
+/* PCS_TX_DIG_TBIT5 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT5_PCS_POWER_SW_1_TIME_CMN_MASK (0x00000F00U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT5_PCS_POWER_SW_1_TIME_CMN_SHIFT (0x00000008U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT5_PCS_POWER_SW_1_TIME_CMN_MAX (0x0000000FU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT5_PCS_POWER_SW_1_TIME_CL_R_MASK (0x000000F0U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT5_PCS_POWER_SW_1_TIME_CL_R_SHIFT (0x00000004U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT5_PCS_POWER_SW_1_TIME_CL_R_MAX (0x0000000FU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT5_PCS_POWER_SW_1_TIME_CL_L_MASK (0x0000000FU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT5_PCS_POWER_SW_1_TIME_CL_L_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT5_PCS_POWER_SW_1_TIME_CL_L_MAX (0x0000000FU)
+
+/* PCS_TX_DIG_TBIT6 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT6_PCS_DTX_L_3_SPARE_MASK (0xFF000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT6_PCS_DTX_L_3_SPARE_SHIFT (0x00000018U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT6_PCS_DTX_L_3_SPARE_MAX (0x000000FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT6_PCS_DTX_L_2_SPARE_MASK (0x00FF0000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT6_PCS_DTX_L_2_SPARE_SHIFT (0x00000010U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT6_PCS_DTX_L_2_SPARE_MAX (0x000000FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT6_PCS_DTX_L_1_SPARE_MASK (0x0000FF00U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT6_PCS_DTX_L_1_SPARE_SHIFT (0x00000008U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT6_PCS_DTX_L_1_SPARE_MAX (0x000000FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT6_PCS_DTX_L_0_SPARE_MASK (0x000000FFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT6_PCS_DTX_L_0_SPARE_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT6_PCS_DTX_L_0_SPARE_MAX (0x000000FFU)
+
+/* PCS_TX_DIG_TBIT7 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT7_PCS_DTX_R_3_SPARE_MASK (0xFF000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT7_PCS_DTX_R_3_SPARE_SHIFT (0x00000018U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT7_PCS_DTX_R_3_SPARE_MAX (0x000000FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT7_PCS_DTX_R_2_SPARE_MASK (0x00FF0000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT7_PCS_DTX_R_2_SPARE_SHIFT (0x00000010U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT7_PCS_DTX_R_2_SPARE_MAX (0x000000FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT7_PCS_DTX_R_1_SPARE_MASK (0x0000FF00U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT7_PCS_DTX_R_1_SPARE_SHIFT (0x00000008U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT7_PCS_DTX_R_1_SPARE_MAX (0x000000FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT7_PCS_DTX_R_0_SPARE_MASK (0x000000FFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT7_PCS_DTX_R_0_SPARE_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT7_PCS_DTX_R_0_SPARE_MAX (0x000000FFU)
+
+/* PCS_TX_DIG_TBIT8 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT8_PCS_CMN_SPARE_MASK (0x00FF0000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT8_PCS_CMN_SPARE_SHIFT (0x00000010U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT8_PCS_CMN_SPARE_MAX (0x000000FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT8_PCS_CL_R_SPARE_MASK (0x0000FF00U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT8_PCS_CL_R_SPARE_SHIFT (0x00000008U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT8_PCS_CL_R_SPARE_MAX (0x000000FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT8_PCS_CL_L_SPARE_MASK (0x000000FFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT8_PCS_CL_L_SPARE_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT8_PCS_CL_L_SPARE_MAX (0x000000FFU)
+
+/* PCS_TX_DIG_TBIT9 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT9_PCS_PSO_DISABLE_VALUE_MASK (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT9_PCS_PSO_DISABLE_VALUE_SHIFT (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT9_PCS_PSO_DISABLE_VALUE_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT9_PCS_PSO_DISABLE_EN_MASK (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT9_PCS_PSO_DISABLE_EN_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT9_PCS_PSO_DISABLE_EN_MAX (0x00000001U)
+
+/* PCS_TX_DIG_TBIT10 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT10_PCS_DIG_TBIT10_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT10_PCS_DIG_TBIT10_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_PCS_TX_DIG_TBIT10_PCS_DIG_TBIT10_MAX (0xFFFFFFFFU)
+
+/* ISO_PHY_ISO_CNTRL */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_CNTRL_ISO_BF_31_12_MASK (0xFFFFF000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_CNTRL_ISO_BF_31_12_SHIFT (0x0000000CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_CNTRL_ISO_BF_31_12_MAX (0x000FFFFFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_CNTRL_ISO_PHY_ISOLATION_MASK (0x00000800U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_CNTRL_ISO_PHY_ISOLATION_SHIFT (0x0000000BU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_CNTRL_ISO_PHY_ISOLATION_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_CNTRL_ISO_PHY_ISO_CMN_MASK (0x00000400U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_CNTRL_ISO_PHY_ISO_CMN_SHIFT (0x0000000AU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_CNTRL_ISO_PHY_ISO_CMN_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_CNTRL_ISO_PHY_ISO_CL_MASK (0x00000300U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_CNTRL_ISO_PHY_ISO_CL_SHIFT (0x00000008U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_CNTRL_ISO_PHY_ISO_CL_MAX (0x00000003U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_CNTRL_ISO_PHY_ISO_DL_MASK (0x000000FFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_CNTRL_ISO_PHY_ISO_DL_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_CNTRL_ISO_PHY_ISO_DL_MAX (0x000000FFU)
+
+/* ISO_PHY_ISO_RESET */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_RESET_ISO_BF_31_11_MASK (0xFFFFF800U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_RESET_ISO_BF_31_11_SHIFT (0x0000000BU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_RESET_ISO_BF_31_11_MAX (0x001FFFFFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_RESET_ISO_LANE_RSTB_CMN_MASK (0x00000400U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_RESET_ISO_LANE_RSTB_CMN_SHIFT (0x0000000AU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_RESET_ISO_LANE_RSTB_CMN_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_RESET_ISO_LANE_RSTB_CL_R_MASK (0x00000200U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_RESET_ISO_LANE_RSTB_CL_R_SHIFT (0x00000009U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_RESET_ISO_LANE_RSTB_CL_R_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_RESET_ISO_LANE_RSTB_CL_L_MASK (0x00000100U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_RESET_ISO_LANE_RSTB_CL_L_SHIFT (0x00000008U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_RESET_ISO_LANE_RSTB_CL_L_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_RESET_ISO_LANE_RSTB_DL_R_3_MASK (0x00000080U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_RESET_ISO_LANE_RSTB_DL_R_3_SHIFT (0x00000007U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_RESET_ISO_LANE_RSTB_DL_R_3_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_RESET_ISO_LANE_RSTB_DL_R_2_MASK (0x00000040U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_RESET_ISO_LANE_RSTB_DL_R_2_SHIFT (0x00000006U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_RESET_ISO_LANE_RSTB_DL_R_2_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_RESET_ISO_LANE_RSTB_DL_R_1_MASK (0x00000020U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_RESET_ISO_LANE_RSTB_DL_R_1_SHIFT (0x00000005U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_RESET_ISO_LANE_RSTB_DL_R_1_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_RESET_ISO_LANE_RSTB_DL_R_0_MASK (0x00000010U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_RESET_ISO_LANE_RSTB_DL_R_0_SHIFT (0x00000004U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_RESET_ISO_LANE_RSTB_DL_R_0_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_RESET_ISO_LANE_RSTB_DL_L_3_MASK (0x00000008U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_RESET_ISO_LANE_RSTB_DL_L_3_SHIFT (0x00000003U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_RESET_ISO_LANE_RSTB_DL_L_3_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_RESET_ISO_LANE_RSTB_DL_L_2_MASK (0x00000004U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_RESET_ISO_LANE_RSTB_DL_L_2_SHIFT (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_RESET_ISO_LANE_RSTB_DL_L_2_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_RESET_ISO_LANE_RSTB_DL_L_1_MASK (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_RESET_ISO_LANE_RSTB_DL_L_1_SHIFT (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_RESET_ISO_LANE_RSTB_DL_L_1_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_RESET_ISO_LANE_RSTB_DL_L_0_MASK (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_RESET_ISO_LANE_RSTB_DL_L_0_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_RESET_ISO_LANE_RSTB_DL_L_0_MAX (0x00000001U)
+
+/* ISO_PHY_ISO_ENABLE */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_ENABLE_ISO_BF_31_10_MASK (0xFFFFFC00U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_ENABLE_ISO_BF_31_10_SHIFT (0x0000000AU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_ENABLE_ISO_BF_31_10_MAX (0x003FFFFFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_ENABLE_ISO_TXENABLECLK_CL_R_MASK (0x00000200U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_ENABLE_ISO_TXENABLECLK_CL_R_SHIFT (0x00000009U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_ENABLE_ISO_TXENABLECLK_CL_R_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_ENABLE_ISO_TXENABLECLK_CL_L_MASK (0x00000100U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_ENABLE_ISO_TXENABLECLK_CL_L_SHIFT (0x00000008U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_ENABLE_ISO_TXENABLECLK_CL_L_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_ENABLE_ISO_M_ENABLE_DL_R_3_MASK (0x00000080U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_ENABLE_ISO_M_ENABLE_DL_R_3_SHIFT (0x00000007U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_ENABLE_ISO_M_ENABLE_DL_R_3_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_ENABLE_ISO_M_ENABLE_DL_R_2_MASK (0x00000040U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_ENABLE_ISO_M_ENABLE_DL_R_2_SHIFT (0x00000006U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_ENABLE_ISO_M_ENABLE_DL_R_2_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_ENABLE_ISO_M_ENABLE_DL_R_1_MASK (0x00000020U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_ENABLE_ISO_M_ENABLE_DL_R_1_SHIFT (0x00000005U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_ENABLE_ISO_M_ENABLE_DL_R_1_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_ENABLE_ISO_M_ENABLE_DL_R_0_MASK (0x00000010U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_ENABLE_ISO_M_ENABLE_DL_R_0_SHIFT (0x00000004U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_ENABLE_ISO_M_ENABLE_DL_R_0_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_ENABLE_ISO_M_ENABLE_DL_L_3_MASK (0x00000008U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_ENABLE_ISO_M_ENABLE_DL_L_3_SHIFT (0x00000003U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_ENABLE_ISO_M_ENABLE_DL_L_3_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_ENABLE_ISO_M_ENABLE_DL_L_2_MASK (0x00000004U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_ENABLE_ISO_M_ENABLE_DL_L_2_SHIFT (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_ENABLE_ISO_M_ENABLE_DL_L_2_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_ENABLE_ISO_M_ENABLE_DL_L_1_MASK (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_ENABLE_ISO_M_ENABLE_DL_L_1_SHIFT (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_ENABLE_ISO_M_ENABLE_DL_L_1_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_ENABLE_ISO_M_ENABLE_DL_L_0_MASK (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_ENABLE_ISO_M_ENABLE_DL_L_0_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_ENABLE_ISO_M_ENABLE_DL_L_0_MAX (0x00000001U)
+
+/* ISO_PHY_ISO_CMN_CTRL */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_CMN_CTRL_ISO_BF_31_8_MASK (0xFFFFFF00U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_CMN_CTRL_ISO_BF_31_8_SHIFT (0x00000008U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_CMN_CTRL_ISO_BF_31_8_MAX (0x00FFFFFFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_CMN_CTRL_ISO_PSO_DISABLE_MASK (0x00000080U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_CMN_CTRL_ISO_PSO_DISABLE_SHIFT (0x00000007U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_CMN_CTRL_ISO_PSO_DISABLE_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_CMN_CTRL_ISO_O_SUPPLY_IO_PG_MASK (0x00000040U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_CMN_CTRL_ISO_O_SUPPLY_IO_PG_SHIFT (0x00000006U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_CMN_CTRL_ISO_O_SUPPLY_IO_PG_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_CMN_CTRL_ISO_O_SUPPLY_CORE_PG_MASK (0x00000020U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_CMN_CTRL_ISO_O_SUPPLY_CORE_PG_SHIFT (0x00000005U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_CMN_CTRL_ISO_O_SUPPLY_CORE_PG_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_CMN_CTRL_ISO_O_CMN_READY_MASK (0x00000010U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_CMN_CTRL_ISO_O_CMN_READY_SHIFT (0x00000004U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_CMN_CTRL_ISO_O_CMN_READY_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_CMN_CTRL_ISO_IP_CONFIG_CMN_MASK (0x0000000EU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_CMN_CTRL_ISO_IP_CONFIG_CMN_SHIFT (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_CMN_CTRL_ISO_IP_CONFIG_CMN_MAX (0x00000007U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_CMN_CTRL_ISO_PSO_CMN_MASK (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_CMN_CTRL_ISO_PSO_CMN_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_CMN_CTRL_ISO_PSO_CMN_MAX (0x00000001U)
+
+/* ISO_PHY_ISO_CMN_PLL */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_CMN_PLL_ISO_BF_31_24_MASK (0xFF000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_CMN_PLL_ISO_BF_31_24_SHIFT (0x00000018U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_CMN_PLL_ISO_BF_31_24_MAX (0x000000FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_CMN_PLL_ISO_PLL_LOCK_MASK (0x00800000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_CMN_PLL_ISO_PLL_LOCK_SHIFT (0x00000017U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_CMN_PLL_ISO_PLL_LOCK_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_CMN_PLL_ISO_PLL_PSO_MASK (0x00400000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_CMN_PLL_ISO_PLL_PSO_SHIFT (0x00000016U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_CMN_PLL_ISO_PLL_PSO_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_CMN_PLL_ISO_PLL_PD_MASK (0x00200000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_CMN_PLL_ISO_PLL_PD_SHIFT (0x00000015U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_CMN_PLL_ISO_PLL_PD_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_CMN_PLL_ISO_PLL_FBDIV_MASK (0x001FF800U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_CMN_PLL_ISO_PLL_FBDIV_SHIFT (0x0000000BU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_CMN_PLL_ISO_PLL_FBDIV_MAX (0x000003FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_CMN_PLL_ISO_PLL_OPDIV_MASK (0x000007E0U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_CMN_PLL_ISO_PLL_OPDIV_SHIFT (0x00000005U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_CMN_PLL_ISO_PLL_OPDIV_MAX (0x0000003FU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_CMN_PLL_ISO_PLL_IPDIV_MASK (0x0000001FU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_CMN_PLL_ISO_PLL_IPDIV_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_CMN_PLL_ISO_PLL_IPDIV_MAX (0x0000001FU)
+
+/* ISO_PHY_ISO_CL_CNTRL_L */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_CL_CNTRL_L_ISO_BF_31_8_X_MASK (0xFFFFFF00U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_CL_CNTRL_L_ISO_BF_31_8_X_SHIFT (0x00000008U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_CL_CNTRL_L_ISO_BF_31_8_X_MAX (0x00FFFFFFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_CL_CNTRL_L_ISO_LANE_READY_CL_L_MASK (0x00000080U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_CL_CNTRL_L_ISO_LANE_READY_CL_L_SHIFT (0x00000007U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_CL_CNTRL_L_ISO_LANE_READY_CL_L_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_CL_CNTRL_L_ISO_TXSTOPSTATECLK_CL_L_MASK (0x00000040U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_CL_CNTRL_L_ISO_TXSTOPSTATECLK_CL_L_SHIFT (0x00000006U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_CL_CNTRL_L_ISO_TXSTOPSTATECLK_CL_L_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_CL_CNTRL_L_ISO_TXULPSACTIVENOTCLK_CL_L_MASK (0x00000020U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_CL_CNTRL_L_ISO_TXULPSACTIVENOTCLK_CL_L_SHIFT (0x00000005U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_CL_CNTRL_L_ISO_TXULPSACTIVENOTCLK_CL_L_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_CL_CNTRL_L_ISO_TXREADYHSCLK_CL_L_MASK (0x00000010U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_CL_CNTRL_L_ISO_TXREADYHSCLK_CL_L_SHIFT (0x00000004U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_CL_CNTRL_L_ISO_TXREADYHSCLK_CL_L_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_CL_CNTRL_L_ISO_M_CLK_SWAPDPDN_CL_L_MASK (0x00000008U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_CL_CNTRL_L_ISO_M_CLK_SWAPDPDN_CL_L_SHIFT (0x00000003U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_CL_CNTRL_L_ISO_M_CLK_SWAPDPDN_CL_L_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_CL_CNTRL_L_ISO_TXULPSEXITCLK_CL_L_MASK (0x00000004U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_CL_CNTRL_L_ISO_TXULPSEXITCLK_CL_L_SHIFT (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_CL_CNTRL_L_ISO_TXULPSEXITCLK_CL_L_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_CL_CNTRL_L_ISO_TXULPSCLK_CL_L_MASK (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_CL_CNTRL_L_ISO_TXULPSCLK_CL_L_SHIFT (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_CL_CNTRL_L_ISO_TXULPSCLK_CL_L_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_CL_CNTRL_L_ISO_TXREQUESTHSCLK_CL_L_MASK (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_CL_CNTRL_L_ISO_TXREQUESTHSCLK_CL_L_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_CL_CNTRL_L_ISO_TXREQUESTHSCLK_CL_L_MAX (0x00000001U)
+
+/* ISO_PHY_ISO_DL_CTRL_L0 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_CTRL_L0_ISO_BF_31_4_MASK (0xFFFFFFF0U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_CTRL_L0_ISO_BF_31_4_SHIFT (0x00000004U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_CTRL_L0_ISO_BF_31_4_MAX (0x0FFFFFFFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_CTRL_L0_ISO_LANE_READY_DL_L_0_MASK (0x00000008U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_CTRL_L0_ISO_LANE_READY_DL_L_0_SHIFT (0x00000003U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_CTRL_L0_ISO_LANE_READY_DL_L_0_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_CTRL_L0_ISO_M_DATA_SWAPDPDN_DL_L_0_MASK (0x00000004U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_CTRL_L0_ISO_M_DATA_SWAPDPDN_DL_L_0_SHIFT (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_CTRL_L0_ISO_M_DATA_SWAPDPDN_DL_L_0_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_CTRL_L0_ISO_FORCETXSTOPMODE_DL_L_0_MASK (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_CTRL_L0_ISO_FORCETXSTOPMODE_DL_L_0_SHIFT (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_CTRL_L0_ISO_FORCETXSTOPMODE_DL_L_0_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_CTRL_L0_ISO_M_TURNREQUEST_DL_L_0_MASK (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_CTRL_L0_ISO_M_TURNREQUEST_DL_L_0_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_CTRL_L0_ISO_M_TURNREQUEST_DL_L_0_MAX (0x00000001U)
+
+/* ISO_PHY_ISO_DL_HS_L0 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_HS_L0_ISO_BF_31_16_MASK (0xFFFF0000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_HS_L0_ISO_BF_31_16_SHIFT (0x00000010U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_HS_L0_ISO_BF_31_16_MAX (0x0000FFFFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_HS_L0_ISO_TXDATAHS_DL_L_0_MASK (0x0000FF00U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_HS_L0_ISO_TXDATAHS_DL_L_0_SHIFT (0x00000008U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_HS_L0_ISO_TXDATAHS_DL_L_0_MAX (0x000000FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_HS_L0_ISO_TXREADYHS_DL_L_0_MASK (0x00000008U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_HS_L0_ISO_TXREADYHS_DL_L_0_SHIFT (0x00000003U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_HS_L0_ISO_TXREADYHS_DL_L_0_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_HS_L0_ISO_TXSKEWCALHS_DL_L_0_MASK (0x00000004U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_HS_L0_ISO_TXSKEWCALHS_DL_L_0_SHIFT (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_HS_L0_ISO_TXSKEWCALHS_DL_L_0_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_HS_L0_ISO_TXSKEWCALHSINIT_DL_L_0_MASK (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_HS_L0_ISO_TXSKEWCALHSINIT_DL_L_0_SHIFT (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_HS_L0_ISO_TXSKEWCALHSINIT_DL_L_0_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_HS_L0_ISO_TXREQUESTHS_DL_L_0_MASK (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_HS_L0_ISO_TXREQUESTHS_DL_L_0_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_HS_L0_ISO_TXREQUESTHS_DL_L_0_MAX (0x00000001U)
+
+/* ISO_PHY_ISO_DL_TX_ESC_L0 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L0_ISO_BF_31_28_MASK (0xF0000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L0_ISO_BF_31_28_SHIFT (0x0000001CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L0_ISO_BF_31_28_MAX (0x0000000FU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L0_ISO_M_ULPSACTIVENOT_DL_L_0_MASK (0x08000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L0_ISO_M_ULPSACTIVENOT_DL_L_0_SHIFT (0x0000001BU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L0_ISO_M_ULPSACTIVENOT_DL_L_0_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L0_ISO_M_DIRECTION_DL_L_0_MASK (0x04000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L0_ISO_M_DIRECTION_DL_L_0_SHIFT (0x0000001AU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L0_ISO_M_DIRECTION_DL_L_0_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L0_ISO_M_STOPSTATE_DL_L_0_MASK (0x02000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L0_ISO_M_STOPSTATE_DL_L_0_SHIFT (0x00000019U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L0_ISO_M_STOPSTATE_DL_L_0_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L0_ISO_M_ERRCONTENTIONLP1_DL_L_0_MASK (0x01000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L0_ISO_M_ERRCONTENTIONLP1_DL_L_0_SHIFT (0x00000018U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L0_ISO_M_ERRCONTENTIONLP1_DL_L_0_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L0_ISO_M_ERRCONTENTIONLP0_DL_L_0_MASK (0x00800000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L0_ISO_M_ERRCONTENTIONLP0_DL_L_0_SHIFT (0x00000017U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L0_ISO_M_ERRCONTENTIONLP0_DL_L_0_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L0_ISO_M_ERRSYNCESC_DL_L_0_MASK (0x00400000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L0_ISO_M_ERRSYNCESC_DL_L_0_SHIFT (0x00000016U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L0_ISO_M_ERRSYNCESC_DL_L_0_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L0_ISO_M_ERRCONTROL_DL_L_0_MASK (0x00200000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L0_ISO_M_ERRCONTROL_DL_L_0_SHIFT (0x00000015U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L0_ISO_M_ERRCONTROL_DL_L_0_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L0_ISO_M_ERRESC_DL_L_0_MASK (0x00100000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L0_ISO_M_ERRESC_DL_L_0_SHIFT (0x00000014U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L0_ISO_M_ERRESC_DL_L_0_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L0_ISO_M_TXTRIGGERESC_DL_L_0_MASK (0x000F0000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L0_ISO_M_TXTRIGGERESC_DL_L_0_SHIFT (0x00000010U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L0_ISO_M_TXTRIGGERESC_DL_L_0_MAX (0x0000000FU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L0_ISO_M_TXDATAESC_DL_L_0_MASK (0x0000FF00U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L0_ISO_M_TXDATAESC_DL_L_0_SHIFT (0x00000008U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L0_ISO_M_TXDATAESC_DL_L_0_MAX (0x000000FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L0_ISO_M_TXREADYESC_DL_L_0_MASK (0x00000020U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L0_ISO_M_TXREADYESC_DL_L_0_SHIFT (0x00000005U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L0_ISO_M_TXREADYESC_DL_L_0_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L0_ISO_M_TXULPSEXITESC_DL_L_0_MASK (0x00000010U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L0_ISO_M_TXULPSEXITESC_DL_L_0_SHIFT (0x00000004U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L0_ISO_M_TXULPSEXITESC_DL_L_0_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L0_ISO_M_TXULPSESC_DL_L_0_MASK (0x00000008U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L0_ISO_M_TXULPSESC_DL_L_0_SHIFT (0x00000003U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L0_ISO_M_TXULPSESC_DL_L_0_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L0_ISO_M_TXVALIDESC_DL_L_0_MASK (0x00000004U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L0_ISO_M_TXVALIDESC_DL_L_0_SHIFT (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L0_ISO_M_TXVALIDESC_DL_L_0_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L0_ISO_M_TXLPDTESC_DL_L_0_MASK (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L0_ISO_M_TXLPDTESC_DL_L_0_SHIFT (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L0_ISO_M_TXLPDTESC_DL_L_0_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L0_ISO_M_TXREQUESTESC_DL_L_0_MASK (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L0_ISO_M_TXREQUESTESC_DL_L_0_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L0_ISO_M_TXREQUESTESC_DL_L_0_MAX (0x00000001U)
+
+/* ISO_PHY_ISO_DL_RX_ESC_L0 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_RX_ESC_L0_ISO_BF_31_15_MASK (0xFFFF8000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_RX_ESC_L0_ISO_BF_31_15_SHIFT (0x0000000FU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_RX_ESC_L0_ISO_BF_31_15_MAX (0x0001FFFFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_RX_ESC_L0_ISO_M_RXDATAESC_DL_L_0_MASK (0x00007F80U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_RX_ESC_L0_ISO_M_RXDATAESC_DL_L_0_SHIFT (0x00000007U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_RX_ESC_L0_ISO_M_RXDATAESC_DL_L_0_MAX (0x000000FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_RX_ESC_L0_ISO_M_RXTRIGGERESC_DL_L_0_MASK (0x00000078U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_RX_ESC_L0_ISO_M_RXTRIGGERESC_DL_L_0_SHIFT (0x00000003U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_RX_ESC_L0_ISO_M_RXTRIGGERESC_DL_L_0_MAX (0x0000000FU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_RX_ESC_L0_ISO_M_RXULPSESC_DL_L_0_MASK (0x00000004U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_RX_ESC_L0_ISO_M_RXULPSESC_DL_L_0_SHIFT (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_RX_ESC_L0_ISO_M_RXULPSESC_DL_L_0_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_RX_ESC_L0_ISO_M_RXVALIDESC_DL_L_0_MASK (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_RX_ESC_L0_ISO_M_RXVALIDESC_DL_L_0_SHIFT (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_RX_ESC_L0_ISO_M_RXVALIDESC_DL_L_0_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_RX_ESC_L0_ISO_M_RXLPDTESC_DL_L_0_MASK (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_RX_ESC_L0_ISO_M_RXLPDTESC_DL_L_0_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_RX_ESC_L0_ISO_M_RXLPDTESC_DL_L_0_MAX (0x00000001U)
+
+/* ISO_PHY_ISO_DL_CTRL_L1 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_CTRL_L1_ISO_BF_31_4_X_MASK (0xFFFFFFF0U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_CTRL_L1_ISO_BF_31_4_X_SHIFT (0x00000004U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_CTRL_L1_ISO_BF_31_4_X_MAX (0x0FFFFFFFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_CTRL_L1_ISO_LANE_READY_DL_L_1_MASK (0x00000008U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_CTRL_L1_ISO_LANE_READY_DL_L_1_SHIFT (0x00000003U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_CTRL_L1_ISO_LANE_READY_DL_L_1_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_CTRL_L1_ISO_M_DATA_SWAPDPDN_DL_L_1_MASK (0x00000004U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_CTRL_L1_ISO_M_DATA_SWAPDPDN_DL_L_1_SHIFT (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_CTRL_L1_ISO_M_DATA_SWAPDPDN_DL_L_1_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_CTRL_L1_ISO_FORCETXSTOPMODE_DL_L_1_MASK (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_CTRL_L1_ISO_FORCETXSTOPMODE_DL_L_1_SHIFT (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_CTRL_L1_ISO_FORCETXSTOPMODE_DL_L_1_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_CTRL_L1_ISO_M_TURNREQUEST_DL_L_1_MASK (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_CTRL_L1_ISO_M_TURNREQUEST_DL_L_1_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_CTRL_L1_ISO_M_TURNREQUEST_DL_L_1_MAX (0x00000001U)
+
+/* ISO_PHY_ISO_DL_HS_L1 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_HS_L1_ISO_BF_31_16_X_MASK (0xFFFF0000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_HS_L1_ISO_BF_31_16_X_SHIFT (0x00000010U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_HS_L1_ISO_BF_31_16_X_MAX (0x0000FFFFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_HS_L1_ISO_TXDATAHS_DL_L_1_MASK (0x0000FF00U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_HS_L1_ISO_TXDATAHS_DL_L_1_SHIFT (0x00000008U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_HS_L1_ISO_TXDATAHS_DL_L_1_MAX (0x000000FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_HS_L1_ISO_TXREADYHS_DL_L_1_MASK (0x00000008U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_HS_L1_ISO_TXREADYHS_DL_L_1_SHIFT (0x00000003U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_HS_L1_ISO_TXREADYHS_DL_L_1_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_HS_L1_ISO_TXSKEWCALHS_DL_L_1_MASK (0x00000004U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_HS_L1_ISO_TXSKEWCALHS_DL_L_1_SHIFT (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_HS_L1_ISO_TXSKEWCALHS_DL_L_1_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_HS_L1_ISO_TXSKEWCALHSINIT_DL_L_1_MASK (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_HS_L1_ISO_TXSKEWCALHSINIT_DL_L_1_SHIFT (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_HS_L1_ISO_TXSKEWCALHSINIT_DL_L_1_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_HS_L1_ISO_TXREQUESTHS_DL_L_1_MASK (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_HS_L1_ISO_TXREQUESTHS_DL_L_1_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_HS_L1_ISO_TXREQUESTHS_DL_L_1_MAX (0x00000001U)
+
+/* ISO_PHY_ISO_DL_TX_ESC_L1 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L1_ISO_BF_31_28_X_MASK (0xF0000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L1_ISO_BF_31_28_X_SHIFT (0x0000001CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L1_ISO_BF_31_28_X_MAX (0x0000000FU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L1_ISO_M_ULPSACTIVENOT_DL_L_1_MASK (0x08000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L1_ISO_M_ULPSACTIVENOT_DL_L_1_SHIFT (0x0000001BU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L1_ISO_M_ULPSACTIVENOT_DL_L_1_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L1_ISO_M_DIRECTION_DL_L_1_MASK (0x04000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L1_ISO_M_DIRECTION_DL_L_1_SHIFT (0x0000001AU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L1_ISO_M_DIRECTION_DL_L_1_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L1_ISO_M_STOPSTATE_DL_L_1_MASK (0x02000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L1_ISO_M_STOPSTATE_DL_L_1_SHIFT (0x00000019U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L1_ISO_M_STOPSTATE_DL_L_1_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L1_ISO_M_ERRCONTENTIONLP1_DL_L_1_MASK (0x01000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L1_ISO_M_ERRCONTENTIONLP1_DL_L_1_SHIFT (0x00000018U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L1_ISO_M_ERRCONTENTIONLP1_DL_L_1_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L1_ISO_M_ERRCONTENTIONLP0_DL_L_1_MASK (0x00800000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L1_ISO_M_ERRCONTENTIONLP0_DL_L_1_SHIFT (0x00000017U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L1_ISO_M_ERRCONTENTIONLP0_DL_L_1_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L1_ISO_M_ERRSYNCESC_DL_L_1_MASK (0x00400000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L1_ISO_M_ERRSYNCESC_DL_L_1_SHIFT (0x00000016U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L1_ISO_M_ERRSYNCESC_DL_L_1_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L1_ISO_M_ERRCONTROL_DL_L_1_MASK (0x00200000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L1_ISO_M_ERRCONTROL_DL_L_1_SHIFT (0x00000015U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L1_ISO_M_ERRCONTROL_DL_L_1_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L1_ISO_M_ERRESC_DL_L_1_MASK (0x00100000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L1_ISO_M_ERRESC_DL_L_1_SHIFT (0x00000014U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L1_ISO_M_ERRESC_DL_L_1_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L1_ISO_M_TXTRIGGERESC_DL_L_1_MASK (0x000F0000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L1_ISO_M_TXTRIGGERESC_DL_L_1_SHIFT (0x00000010U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L1_ISO_M_TXTRIGGERESC_DL_L_1_MAX (0x0000000FU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L1_ISO_M_TXDATAESC_DL_L_1_MASK (0x0000FF00U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L1_ISO_M_TXDATAESC_DL_L_1_SHIFT (0x00000008U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L1_ISO_M_TXDATAESC_DL_L_1_MAX (0x000000FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L1_ISO_M_TXREADYESC_DL_L_1_MASK (0x00000020U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L1_ISO_M_TXREADYESC_DL_L_1_SHIFT (0x00000005U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L1_ISO_M_TXREADYESC_DL_L_1_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L1_ISO_M_TXULPSEXITESC_DL_L_1_MASK (0x00000010U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L1_ISO_M_TXULPSEXITESC_DL_L_1_SHIFT (0x00000004U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L1_ISO_M_TXULPSEXITESC_DL_L_1_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L1_ISO_M_TXULPSESC_DL_L_1_MASK (0x00000008U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L1_ISO_M_TXULPSESC_DL_L_1_SHIFT (0x00000003U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L1_ISO_M_TXULPSESC_DL_L_1_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L1_ISO_M_TXVALIDESC_DL_L_1_MASK (0x00000004U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L1_ISO_M_TXVALIDESC_DL_L_1_SHIFT (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L1_ISO_M_TXVALIDESC_DL_L_1_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L1_ISO_M_TXLPDTESC_DL_L_1_MASK (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L1_ISO_M_TXLPDTESC_DL_L_1_SHIFT (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L1_ISO_M_TXLPDTESC_DL_L_1_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L1_ISO_M_TXREQUESTESC_DL_L_1_MASK (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L1_ISO_M_TXREQUESTESC_DL_L_1_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_TX_ESC_L1_ISO_M_TXREQUESTESC_DL_L_1_MAX (0x00000001U)
+
+/* ISO_PHY_ISO_DL_RX_ESC_L1 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_RX_ESC_L1_ISO_BF_31_15_X_MASK (0xFFFF8000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_RX_ESC_L1_ISO_BF_31_15_X_SHIFT (0x0000000FU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_RX_ESC_L1_ISO_BF_31_15_X_MAX (0x0001FFFFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_RX_ESC_L1_ISO_M_RXDATAESC_DL_L_1_MASK (0x00007F80U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_RX_ESC_L1_ISO_M_RXDATAESC_DL_L_1_SHIFT (0x00000007U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_RX_ESC_L1_ISO_M_RXDATAESC_DL_L_1_MAX (0x000000FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_RX_ESC_L1_ISO_M_RXTRIGGERESC_DL_L_1_MASK (0x00000078U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_RX_ESC_L1_ISO_M_RXTRIGGERESC_DL_L_1_SHIFT (0x00000003U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_RX_ESC_L1_ISO_M_RXTRIGGERESC_DL_L_1_MAX (0x0000000FU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_RX_ESC_L1_ISO_M_RXULPSESC_DL_L_1_MASK (0x00000004U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_RX_ESC_L1_ISO_M_RXULPSESC_DL_L_1_SHIFT (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_RX_ESC_L1_ISO_M_RXULPSESC_DL_L_1_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_RX_ESC_L1_ISO_M_RXVALIDESC_DL_L_1_MASK (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_RX_ESC_L1_ISO_M_RXVALIDESC_DL_L_1_SHIFT (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_RX_ESC_L1_ISO_M_RXVALIDESC_DL_L_1_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_RX_ESC_L1_ISO_M_RXLPDTESC_DL_L_1_MASK (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_RX_ESC_L1_ISO_M_RXLPDTESC_DL_L_1_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_DL_RX_ESC_L1_ISO_M_RXLPDTESC_DL_L_1_MAX (0x00000001U)
+
+/* ISO_PHY_ISO_SPARE_1 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_SPARE_1_ISO_SPARE_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_SPARE_1_ISO_SPARE_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_SPARE_1_ISO_SPARE_MAX (0xFFFFFFFFU)
+
+/* ISO_PHY_ISO_SPARE_2 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_SPARE_2_ISO_SPARE_X_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_SPARE_2_ISO_SPARE_X_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_PHY_ISO_SPARE_2_ISO_SPARE_X_MAX (0xFFFFFFFFU)
+
+/* ISO_LDD_PHY_ISO_DL_CTRL_L2 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_CTRL_L2_ISO_BF_31_4_X_X_MASK (0xFFFFFFF0U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_CTRL_L2_ISO_BF_31_4_X_X_SHIFT (0x00000004U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_CTRL_L2_ISO_BF_31_4_X_X_MAX (0x0FFFFFFFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_CTRL_L2_ISO_LANE_READY_DL_L_2_MASK (0x00000008U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_CTRL_L2_ISO_LANE_READY_DL_L_2_SHIFT (0x00000003U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_CTRL_L2_ISO_LANE_READY_DL_L_2_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_CTRL_L2_ISO_M_DATA_SWAPDPDN_DL_L_2_MASK (0x00000004U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_CTRL_L2_ISO_M_DATA_SWAPDPDN_DL_L_2_SHIFT (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_CTRL_L2_ISO_M_DATA_SWAPDPDN_DL_L_2_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_CTRL_L2_ISO_FORCETXSTOPMODE_DL_L_2_MASK (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_CTRL_L2_ISO_FORCETXSTOPMODE_DL_L_2_SHIFT (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_CTRL_L2_ISO_FORCETXSTOPMODE_DL_L_2_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_CTRL_L2_ISO_M_TURNREQUEST_DL_L_2_MASK (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_CTRL_L2_ISO_M_TURNREQUEST_DL_L_2_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_CTRL_L2_ISO_M_TURNREQUEST_DL_L_2_MAX (0x00000001U)
+
+/* ISO_LDD_PHY_ISO_DL_HS_L2 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_HS_L2_ISO_BF_31_16_X_X_MASK (0xFFFF0000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_HS_L2_ISO_BF_31_16_X_X_SHIFT (0x00000010U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_HS_L2_ISO_BF_31_16_X_X_MAX (0x0000FFFFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_HS_L2_ISO_TXDATAHS_DL_L_2_MASK (0x0000FF00U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_HS_L2_ISO_TXDATAHS_DL_L_2_SHIFT (0x00000008U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_HS_L2_ISO_TXDATAHS_DL_L_2_MAX (0x000000FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_HS_L2_ISO_TXREADYHS_DL_L_2_MASK (0x00000008U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_HS_L2_ISO_TXREADYHS_DL_L_2_SHIFT (0x00000003U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_HS_L2_ISO_TXREADYHS_DL_L_2_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_HS_L2_ISO_TXSKEWCALHS_DL_L_2_MASK (0x00000004U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_HS_L2_ISO_TXSKEWCALHS_DL_L_2_SHIFT (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_HS_L2_ISO_TXSKEWCALHS_DL_L_2_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_HS_L2_ISO_TXSKEWCALHSINIT_DL_L_2_MASK (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_HS_L2_ISO_TXSKEWCALHSINIT_DL_L_2_SHIFT (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_HS_L2_ISO_TXSKEWCALHSINIT_DL_L_2_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_HS_L2_ISO_TXREQUESTHS_DL_L_2_MASK (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_HS_L2_ISO_TXREQUESTHS_DL_L_2_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_HS_L2_ISO_TXREQUESTHS_DL_L_2_MAX (0x00000001U)
+
+/* ISO_LDD_PHY_ISO_DL_TX_ESC_L2 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L2_ISO_BF_31_28_X_X_MASK (0xF0000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L2_ISO_BF_31_28_X_X_SHIFT (0x0000001CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L2_ISO_BF_31_28_X_X_MAX (0x0000000FU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L2_ISO_M_ULPSACTIVENOT_DL_L_2_MASK (0x08000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L2_ISO_M_ULPSACTIVENOT_DL_L_2_SHIFT (0x0000001BU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L2_ISO_M_ULPSACTIVENOT_DL_L_2_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L2_ISO_M_DIRECTION_DL_L_2_MASK (0x04000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L2_ISO_M_DIRECTION_DL_L_2_SHIFT (0x0000001AU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L2_ISO_M_DIRECTION_DL_L_2_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L2_ISO_M_STOPSTATE_DL_L_2_MASK (0x02000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L2_ISO_M_STOPSTATE_DL_L_2_SHIFT (0x00000019U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L2_ISO_M_STOPSTATE_DL_L_2_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L2_ISO_M_ERRCONTENTIONLP1_DL_L_2_MASK (0x01000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L2_ISO_M_ERRCONTENTIONLP1_DL_L_2_SHIFT (0x00000018U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L2_ISO_M_ERRCONTENTIONLP1_DL_L_2_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L2_ISO_M_ERRCONTENTIONLP0_DL_L_2_MASK (0x00800000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L2_ISO_M_ERRCONTENTIONLP0_DL_L_2_SHIFT (0x00000017U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L2_ISO_M_ERRCONTENTIONLP0_DL_L_2_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L2_ISO_M_ERRSYNCESC_DL_L_2_MASK (0x00400000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L2_ISO_M_ERRSYNCESC_DL_L_2_SHIFT (0x00000016U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L2_ISO_M_ERRSYNCESC_DL_L_2_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L2_ISO_M_ERRCONTROL_DL_L_2_MASK (0x00200000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L2_ISO_M_ERRCONTROL_DL_L_2_SHIFT (0x00000015U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L2_ISO_M_ERRCONTROL_DL_L_2_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L2_ISO_M_ERRESC_DL_L_2_MASK (0x00100000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L2_ISO_M_ERRESC_DL_L_2_SHIFT (0x00000014U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L2_ISO_M_ERRESC_DL_L_2_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L2_ISO_M_TXTRIGGERESC_DL_L_2_MASK (0x000F0000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L2_ISO_M_TXTRIGGERESC_DL_L_2_SHIFT (0x00000010U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L2_ISO_M_TXTRIGGERESC_DL_L_2_MAX (0x0000000FU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L2_ISO_M_TXDATAESC_DL_L_2_MASK (0x0000FF00U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L2_ISO_M_TXDATAESC_DL_L_2_SHIFT (0x00000008U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L2_ISO_M_TXDATAESC_DL_L_2_MAX (0x000000FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L2_ISO_M_TXREADYESC_DL_L_2_MASK (0x00000020U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L2_ISO_M_TXREADYESC_DL_L_2_SHIFT (0x00000005U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L2_ISO_M_TXREADYESC_DL_L_2_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L2_ISO_M_TXULPSEXITESC_DL_L_2_MASK (0x00000010U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L2_ISO_M_TXULPSEXITESC_DL_L_2_SHIFT (0x00000004U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L2_ISO_M_TXULPSEXITESC_DL_L_2_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L2_ISO_M_TXULPSESC_DL_L_2_MASK (0x00000008U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L2_ISO_M_TXULPSESC_DL_L_2_SHIFT (0x00000003U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L2_ISO_M_TXULPSESC_DL_L_2_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L2_ISO_M_TXVALIDESC_DL_L_2_MASK (0x00000004U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L2_ISO_M_TXVALIDESC_DL_L_2_SHIFT (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L2_ISO_M_TXVALIDESC_DL_L_2_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L2_ISO_M_TXLPDTESC_DL_L_2_MASK (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L2_ISO_M_TXLPDTESC_DL_L_2_SHIFT (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L2_ISO_M_TXLPDTESC_DL_L_2_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L2_ISO_M_TXREQUESTESC_DL_L_2_MASK (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L2_ISO_M_TXREQUESTESC_DL_L_2_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L2_ISO_M_TXREQUESTESC_DL_L_2_MAX (0x00000001U)
+
+/* ISO_LDD_PHY_ISO_DL_RX_ESC_L2 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_RX_ESC_L2_ISO_BF_31_15_X_X_MASK (0xFFFF8000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_RX_ESC_L2_ISO_BF_31_15_X_X_SHIFT (0x0000000FU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_RX_ESC_L2_ISO_BF_31_15_X_X_MAX (0x0001FFFFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_RX_ESC_L2_ISO_M_RXDATAESC_DL_L_2_MASK (0x00007F80U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_RX_ESC_L2_ISO_M_RXDATAESC_DL_L_2_SHIFT (0x00000007U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_RX_ESC_L2_ISO_M_RXDATAESC_DL_L_2_MAX (0x000000FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_RX_ESC_L2_ISO_M_RXTRIGGERESC_DL_L_2_MASK (0x00000078U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_RX_ESC_L2_ISO_M_RXTRIGGERESC_DL_L_2_SHIFT (0x00000003U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_RX_ESC_L2_ISO_M_RXTRIGGERESC_DL_L_2_MAX (0x0000000FU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_RX_ESC_L2_ISO_M_RXULPSESC_DL_L_2_MASK (0x00000004U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_RX_ESC_L2_ISO_M_RXULPSESC_DL_L_2_SHIFT (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_RX_ESC_L2_ISO_M_RXULPSESC_DL_L_2_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_RX_ESC_L2_ISO_M_RXVALIDESC_DL_L_2_MASK (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_RX_ESC_L2_ISO_M_RXVALIDESC_DL_L_2_SHIFT (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_RX_ESC_L2_ISO_M_RXVALIDESC_DL_L_2_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_RX_ESC_L2_ISO_M_RXLPDTESC_DL_L_2_MASK (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_RX_ESC_L2_ISO_M_RXLPDTESC_DL_L_2_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_RX_ESC_L2_ISO_M_RXLPDTESC_DL_L_2_MAX (0x00000001U)
+
+/* ISO_LDD_PHY_ISO_DL_CTRL_L3 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_CTRL_L3_ISO_BF_31_4_X_X_X_MASK (0xFFFFFFF0U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_CTRL_L3_ISO_BF_31_4_X_X_X_SHIFT (0x00000004U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_CTRL_L3_ISO_BF_31_4_X_X_X_MAX (0x0FFFFFFFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_CTRL_L3_ISO_LANE_READY_DL_L_3_MASK (0x00000008U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_CTRL_L3_ISO_LANE_READY_DL_L_3_SHIFT (0x00000003U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_CTRL_L3_ISO_LANE_READY_DL_L_3_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_CTRL_L3_ISO_M_DATA_SWAPDPDN_DL_L_3_MASK (0x00000004U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_CTRL_L3_ISO_M_DATA_SWAPDPDN_DL_L_3_SHIFT (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_CTRL_L3_ISO_M_DATA_SWAPDPDN_DL_L_3_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_CTRL_L3_ISO_FORCETXSTOPMODE_DL_L_3_MASK (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_CTRL_L3_ISO_FORCETXSTOPMODE_DL_L_3_SHIFT (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_CTRL_L3_ISO_FORCETXSTOPMODE_DL_L_3_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_CTRL_L3_ISO_M_TURNREQUEST_DL_L_3_MASK (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_CTRL_L3_ISO_M_TURNREQUEST_DL_L_3_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_CTRL_L3_ISO_M_TURNREQUEST_DL_L_3_MAX (0x00000001U)
+
+/* ISO_LDD_PHY_ISO_DL_HS_L3 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_HS_L3_ISO_BF_31_16_X_X_X_MASK (0xFFFF0000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_HS_L3_ISO_BF_31_16_X_X_X_SHIFT (0x00000010U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_HS_L3_ISO_BF_31_16_X_X_X_MAX (0x0000FFFFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_HS_L3_ISO_TXDATAHS_DL_L_3_MASK (0x0000FF00U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_HS_L3_ISO_TXDATAHS_DL_L_3_SHIFT (0x00000008U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_HS_L3_ISO_TXDATAHS_DL_L_3_MAX (0x000000FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_HS_L3_ISO_TXREADYHS_DL_L_3_MASK (0x00000008U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_HS_L3_ISO_TXREADYHS_DL_L_3_SHIFT (0x00000003U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_HS_L3_ISO_TXREADYHS_DL_L_3_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_HS_L3_ISO_TXSKEWCALHS_DL_L_3_MASK (0x00000004U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_HS_L3_ISO_TXSKEWCALHS_DL_L_3_SHIFT (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_HS_L3_ISO_TXSKEWCALHS_DL_L_3_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_HS_L3_ISO_TXSKEWCALHSINIT_DL_L_3_MASK (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_HS_L3_ISO_TXSKEWCALHSINIT_DL_L_3_SHIFT (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_HS_L3_ISO_TXSKEWCALHSINIT_DL_L_3_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_HS_L3_ISO_TXREQUESTHS_DL_L_3_MASK (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_HS_L3_ISO_TXREQUESTHS_DL_L_3_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_HS_L3_ISO_TXREQUESTHS_DL_L_3_MAX (0x00000001U)
+
+/* ISO_LDD_PHY_ISO_DL_TX_ESC_L3 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L3_ISO_BF_31_28_X_X_X_MASK (0xF0000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L3_ISO_BF_31_28_X_X_X_SHIFT (0x0000001CU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L3_ISO_BF_31_28_X_X_X_MAX (0x0000000FU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L3_ISO_M_ULPSACTIVENOT_DL_L_3_MASK (0x08000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L3_ISO_M_ULPSACTIVENOT_DL_L_3_SHIFT (0x0000001BU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L3_ISO_M_ULPSACTIVENOT_DL_L_3_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L3_ISO_M_DIRECTION_DL_L_3_MASK (0x04000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L3_ISO_M_DIRECTION_DL_L_3_SHIFT (0x0000001AU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L3_ISO_M_DIRECTION_DL_L_3_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L3_ISO_M_STOPSTATE_DL_L_3_MASK (0x02000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L3_ISO_M_STOPSTATE_DL_L_3_SHIFT (0x00000019U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L3_ISO_M_STOPSTATE_DL_L_3_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L3_ISO_M_ERRCONTENTIONLP1_DL_L_3_MASK (0x01000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L3_ISO_M_ERRCONTENTIONLP1_DL_L_3_SHIFT (0x00000018U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L3_ISO_M_ERRCONTENTIONLP1_DL_L_3_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L3_ISO_M_ERRCONTENTIONLP0_DL_L_3_MASK (0x00800000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L3_ISO_M_ERRCONTENTIONLP0_DL_L_3_SHIFT (0x00000017U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L3_ISO_M_ERRCONTENTIONLP0_DL_L_3_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L3_ISO_M_ERRSYNCESC_DL_L_3_MASK (0x00400000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L3_ISO_M_ERRSYNCESC_DL_L_3_SHIFT (0x00000016U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L3_ISO_M_ERRSYNCESC_DL_L_3_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L3_ISO_M_ERRCONTROL_DL_L_3_MASK (0x00200000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L3_ISO_M_ERRCONTROL_DL_L_3_SHIFT (0x00000015U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L3_ISO_M_ERRCONTROL_DL_L_3_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L3_ISO_M_ERRESC_DL_L_3_MASK (0x00100000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L3_ISO_M_ERRESC_DL_L_3_SHIFT (0x00000014U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L3_ISO_M_ERRESC_DL_L_3_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L3_ISO_M_TXTRIGGERESC_DL_L_3_MASK (0x000F0000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L3_ISO_M_TXTRIGGERESC_DL_L_3_SHIFT (0x00000010U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L3_ISO_M_TXTRIGGERESC_DL_L_3_MAX (0x0000000FU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L3_ISO_M_TXDATAESC_DL_L_3_MASK (0x0000FF00U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L3_ISO_M_TXDATAESC_DL_L_3_SHIFT (0x00000008U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L3_ISO_M_TXDATAESC_DL_L_3_MAX (0x000000FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L3_ISO_M_TXREADYESC_DL_L_3_MASK (0x00000020U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L3_ISO_M_TXREADYESC_DL_L_3_SHIFT (0x00000005U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L3_ISO_M_TXREADYESC_DL_L_3_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L3_ISO_M_TXULPSEXITESC_DL_L_3_MASK (0x00000010U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L3_ISO_M_TXULPSEXITESC_DL_L_3_SHIFT (0x00000004U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L3_ISO_M_TXULPSEXITESC_DL_L_3_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L3_ISO_M_TXULPSESC_DL_L_3_MASK (0x00000008U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L3_ISO_M_TXULPSESC_DL_L_3_SHIFT (0x00000003U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L3_ISO_M_TXULPSESC_DL_L_3_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L3_ISO_M_TXVALIDESC_DL_L_3_MASK (0x00000004U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L3_ISO_M_TXVALIDESC_DL_L_3_SHIFT (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L3_ISO_M_TXVALIDESC_DL_L_3_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L3_ISO_M_TXLPDTESC_DL_L_3_MASK (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L3_ISO_M_TXLPDTESC_DL_L_3_SHIFT (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L3_ISO_M_TXLPDTESC_DL_L_3_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L3_ISO_M_TXREQUESTESC_DL_L_3_MASK (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L3_ISO_M_TXREQUESTESC_DL_L_3_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_TX_ESC_L3_ISO_M_TXREQUESTESC_DL_L_3_MAX (0x00000001U)
+
+/* ISO_LDD_PHY_ISO_DL_RX_ESC_L3 */
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_RX_ESC_L3_ISO_BF_31_15_X_X_X_MASK (0xFFFF8000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_RX_ESC_L3_ISO_BF_31_15_X_X_X_SHIFT (0x0000000FU)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_RX_ESC_L3_ISO_BF_31_15_X_X_X_MAX (0x0001FFFFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_RX_ESC_L3_ISO_M_RXDATAESC_DL_L_3_MASK (0x00007F80U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_RX_ESC_L3_ISO_M_RXDATAESC_DL_L_3_SHIFT (0x00000007U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_RX_ESC_L3_ISO_M_RXDATAESC_DL_L_3_MAX (0x000000FFU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_RX_ESC_L3_ISO_M_RXTRIGGERESC_DL_L_3_MASK (0x00000078U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_RX_ESC_L3_ISO_M_RXTRIGGERESC_DL_L_3_SHIFT (0x00000003U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_RX_ESC_L3_ISO_M_RXTRIGGERESC_DL_L_3_MAX (0x0000000FU)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_RX_ESC_L3_ISO_M_RXULPSESC_DL_L_3_MASK (0x00000004U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_RX_ESC_L3_ISO_M_RXULPSESC_DL_L_3_SHIFT (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_RX_ESC_L3_ISO_M_RXULPSESC_DL_L_3_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_RX_ESC_L3_ISO_M_RXVALIDESC_DL_L_3_MASK (0x00000002U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_RX_ESC_L3_ISO_M_RXVALIDESC_DL_L_3_SHIFT (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_RX_ESC_L3_ISO_M_RXVALIDESC_DL_L_3_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_RX_ESC_L3_ISO_M_RXLPDTESC_DL_L_3_MASK (0x00000001U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_RX_ESC_L3_ISO_M_RXLPDTESC_DL_L_3_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_DPHYTX_ISO_LDD_PHY_ISO_DL_RX_ESC_L3_ISO_M_RXLPDTESC_DL_L_3_MAX (0x00000001U)
+
+/* MOD_VER */
+
+#define CSL_WIZ16B8M4CDT_WIZ_CONFIG_MOD_VER_SCHEME_MASK (0xC0000000U)
+#define CSL_WIZ16B8M4CDT_WIZ_CONFIG_MOD_VER_SCHEME_SHIFT (0x0000001EU)
+#define CSL_WIZ16B8M4CDT_WIZ_CONFIG_MOD_VER_SCHEME_MAX (0x00000003U)
+
+#define CSL_WIZ16B8M4CDT_WIZ_CONFIG_MOD_VER_BU_MASK (0x30000000U)
+#define CSL_WIZ16B8M4CDT_WIZ_CONFIG_MOD_VER_BU_SHIFT (0x0000001CU)
+#define CSL_WIZ16B8M4CDT_WIZ_CONFIG_MOD_VER_BU_MAX (0x00000003U)
+
+#define CSL_WIZ16B8M4CDT_WIZ_CONFIG_MOD_VER_MODULE_ID_MASK (0x0FFF0000U)
+#define CSL_WIZ16B8M4CDT_WIZ_CONFIG_MOD_VER_MODULE_ID_SHIFT (0x00000010U)
+#define CSL_WIZ16B8M4CDT_WIZ_CONFIG_MOD_VER_MODULE_ID_MAX (0x00000FFFU)
+
+#define CSL_WIZ16B8M4CDT_WIZ_CONFIG_MOD_VER_RTL_VERSION_MASK (0x0000F800U)
+#define CSL_WIZ16B8M4CDT_WIZ_CONFIG_MOD_VER_RTL_VERSION_SHIFT (0x0000000BU)
+#define CSL_WIZ16B8M4CDT_WIZ_CONFIG_MOD_VER_RTL_VERSION_MAX (0x0000001FU)
+
+#define CSL_WIZ16B8M4CDT_WIZ_CONFIG_MOD_VER_MAJOR_REVISION_MASK (0x00000700U)
+#define CSL_WIZ16B8M4CDT_WIZ_CONFIG_MOD_VER_MAJOR_REVISION_SHIFT (0x00000008U)
+#define CSL_WIZ16B8M4CDT_WIZ_CONFIG_MOD_VER_MAJOR_REVISION_MAX (0x00000007U)
+
+#define CSL_WIZ16B8M4CDT_WIZ_CONFIG_MOD_VER_CUSTOM_REVISION_MASK (0x000000C0U)
+#define CSL_WIZ16B8M4CDT_WIZ_CONFIG_MOD_VER_CUSTOM_REVISION_SHIFT (0x00000006U)
+#define CSL_WIZ16B8M4CDT_WIZ_CONFIG_MOD_VER_CUSTOM_REVISION_MAX (0x00000003U)
+
+#define CSL_WIZ16B8M4CDT_WIZ_CONFIG_MOD_VER_MINOR_REVISION_MASK (0x0000003FU)
+#define CSL_WIZ16B8M4CDT_WIZ_CONFIG_MOD_VER_MINOR_REVISION_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_WIZ_CONFIG_MOD_VER_MINOR_REVISION_MAX (0x0000003FU)
+
+/* PLL_CTRL */
+
+#define CSL_WIZ16B8M4CDT_WIZ_CONFIG_PLL_CTRL_PLL_LOCK_MASK (0x80000000U)
+#define CSL_WIZ16B8M4CDT_WIZ_CONFIG_PLL_CTRL_PLL_LOCK_SHIFT (0x0000001FU)
+#define CSL_WIZ16B8M4CDT_WIZ_CONFIG_PLL_CTRL_PLL_LOCK_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_WIZ_CONFIG_PLL_CTRL_PSO_DISABLE_MASK (0x40000000U)
+#define CSL_WIZ16B8M4CDT_WIZ_CONFIG_PLL_CTRL_PSO_DISABLE_SHIFT (0x0000001EU)
+#define CSL_WIZ16B8M4CDT_WIZ_CONFIG_PLL_CTRL_PSO_DISABLE_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_WIZ_CONFIG_PLL_CTRL_PLL_PSO_MASK (0x20000000U)
+#define CSL_WIZ16B8M4CDT_WIZ_CONFIG_PLL_CTRL_PLL_PSO_SHIFT (0x0000001DU)
+#define CSL_WIZ16B8M4CDT_WIZ_CONFIG_PLL_CTRL_PLL_PSO_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_WIZ_CONFIG_PLL_CTRL_PLL_PD_MASK (0x10000000U)
+#define CSL_WIZ16B8M4CDT_WIZ_CONFIG_PLL_CTRL_PLL_PD_SHIFT (0x0000001CU)
+#define CSL_WIZ16B8M4CDT_WIZ_CONFIG_PLL_CTRL_PLL_PD_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_WIZ_CONFIG_PLL_CTRL_PLL_FBDIV_MASK (0x03FF0000U)
+#define CSL_WIZ16B8M4CDT_WIZ_CONFIG_PLL_CTRL_PLL_FBDIV_SHIFT (0x00000010U)
+#define CSL_WIZ16B8M4CDT_WIZ_CONFIG_PLL_CTRL_PLL_FBDIV_MAX (0x000003FFU)
+
+#define CSL_WIZ16B8M4CDT_WIZ_CONFIG_PLL_CTRL_PLL_OPDIV_MASK (0x00003F00U)
+#define CSL_WIZ16B8M4CDT_WIZ_CONFIG_PLL_CTRL_PLL_OPDIV_SHIFT (0x00000008U)
+#define CSL_WIZ16B8M4CDT_WIZ_CONFIG_PLL_CTRL_PLL_OPDIV_MAX (0x0000003FU)
+
+#define CSL_WIZ16B8M4CDT_WIZ_CONFIG_PLL_CTRL_PLL_IPDIV_MASK (0x0000001FU)
+#define CSL_WIZ16B8M4CDT_WIZ_CONFIG_PLL_CTRL_PLL_IPDIV_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_WIZ_CONFIG_PLL_CTRL_PLL_IPDIV_MAX (0x0000001FU)
+
+/* STATUS */
+
+#define CSL_WIZ16B8M4CDT_WIZ_CONFIG_STATUS_O_CMN_READY_MASK (0x80000000U)
+#define CSL_WIZ16B8M4CDT_WIZ_CONFIG_STATUS_O_CMN_READY_SHIFT (0x0000001FU)
+#define CSL_WIZ16B8M4CDT_WIZ_CONFIG_STATUS_O_CMN_READY_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_WIZ_CONFIG_STATUS_O_SUPPLY_CORE_PG_MASK (0x00000004U)
+#define CSL_WIZ16B8M4CDT_WIZ_CONFIG_STATUS_O_SUPPLY_CORE_PG_SHIFT (0x00000002U)
+#define CSL_WIZ16B8M4CDT_WIZ_CONFIG_STATUS_O_SUPPLY_CORE_PG_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_WIZ_CONFIG_STATUS_O_SUPPLY_IO_PG_MASK (0x00000002U)
+#define CSL_WIZ16B8M4CDT_WIZ_CONFIG_STATUS_O_SUPPLY_IO_PG_SHIFT (0x00000001U)
+#define CSL_WIZ16B8M4CDT_WIZ_CONFIG_STATUS_O_SUPPLY_IO_PG_MAX (0x00000001U)
+
+/* RST_CTRL */
+
+#define CSL_WIZ16B8M4CDT_WIZ_CONFIG_RST_CTRL_LANE_RSTB_CMN_MASK (0x80000000U)
+#define CSL_WIZ16B8M4CDT_WIZ_CONFIG_RST_CTRL_LANE_RSTB_CMN_SHIFT (0x0000001FU)
+#define CSL_WIZ16B8M4CDT_WIZ_CONFIG_RST_CTRL_LANE_RSTB_CMN_MAX (0x00000001U)
+
+/* PSM_FREQ */
+
+#define CSL_WIZ16B8M4CDT_WIZ_CONFIG_PSM_FREQ_PSM_CLOCK_FREQ_MASK (0x000000FFU)
+#define CSL_WIZ16B8M4CDT_WIZ_CONFIG_PSM_FREQ_PSM_CLOCK_FREQ_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_WIZ_CONFIG_PSM_FREQ_PSM_CLOCK_FREQ_MAX (0x000000FFU)
+
+/* IPCONFIG */
+
+#define CSL_WIZ16B8M4CDT_WIZ_CONFIG_IPCONFIG_PSO_CMN_MASK (0x80000000U)
+#define CSL_WIZ16B8M4CDT_WIZ_CONFIG_IPCONFIG_PSO_CMN_SHIFT (0x0000001FU)
+#define CSL_WIZ16B8M4CDT_WIZ_CONFIG_IPCONFIG_PSO_CMN_MAX (0x00000001U)
+
+#define CSL_WIZ16B8M4CDT_WIZ_CONFIG_IPCONFIG_IPCONFIG_CMN_MASK (0x00000007U)
+#define CSL_WIZ16B8M4CDT_WIZ_CONFIG_IPCONFIG_IPCONFIG_CMN_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_WIZ_CONFIG_IPCONFIG_IPCONFIG_CMN_MAX (0x00000007U)
+
+/* PLLRES */
+
+#define CSL_WIZ16B8M4CDT_WIZ_CONFIG_PLLRES_PLLREFSEL_CMN_MASK (0x000000FFU)
+#define CSL_WIZ16B8M4CDT_WIZ_CONFIG_PLLRES_PLLREFSEL_CMN_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_WIZ_CONFIG_PLLRES_PLLREFSEL_CMN_MAX (0x000000FFU)
+
+/* DIAG_TEST */
+
+#define CSL_WIZ16B8M4CDT_WIZ_CONFIG_DIAG_TEST_DIAG_REG_MASK (0xFFFFFFFFU)
+#define CSL_WIZ16B8M4CDT_WIZ_CONFIG_DIAG_TEST_DIAG_REG_SHIFT (0x00000000U)
+#define CSL_WIZ16B8M4CDT_WIZ_CONFIG_DIAG_TEST_DIAG_REG_MAX (0xFFFFFFFFU)
+
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/packages/ti/drv/dss/src/csl/dphy/include/dphy_if.h b/packages/ti/drv/dss/src/csl/dphy/include/dphy_if.h
--- /dev/null
@@ -0,0 +1,116 @@
+/**********************************************************************
+ * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ **********************************************************************
+ * WARNING: This file is auto-generated using api-generator utility.
+ * api-generator: 13.00.31660be
+ * Do not edit it manually.
+ **********************************************************************
+ * DPHY PHY interface
+ **********************************************************************/
+
+#ifndef DPHY_IF_H
+#define DPHY_IF_H
+
+/* parasoft-begin-suppress MISRA2012-RULE-1_1_a_c90-2 "C90 - limits, DRV-3906" */
+/* parasoft-begin-suppress MISRA2012-RULE-1_1_b_c90-2 "C90 - limits, DRV-3906" */
+
+
+/** @defgroup DataStructure Dynamic Data Structures
+ * This section defines the data structures used by the driver to provide
+ * hardware information, modification and dynamic operation of the driver.
+ * These data structures are defined in the header file of the core driver
+ * and utilized by the API.
+ * @{
+ */
+
+/**********************************************************************
+ * Forward declarations
+ **********************************************************************/
+typedef struct DPHY_PrivateData_s DPHY_PrivateData;
+typedef struct DPHY_PllCmnDigTbit13_s DPHY_PllCmnDigTbit13;
+typedef struct DPHY_PllCmnDigTbit14_s DPHY_PllCmnDigTbit14;
+
+
+/**
+ * @}
+ */
+
+/** @defgroup DriverFunctionAPI Driver Function API
+ * Prototypes for the driver API functions. The user application can link statically to the
+ * necessary API functions and call them directly.
+ * @{
+ */
+
+/**********************************************************************
+ * API methods
+ **********************************************************************/
+
+/**
+ * Writes CmnDigTbit13 register.
+ * @param[in] pD Pointer to driver's private data object.
+ * @param[in] config Pointer to test register 13 data.
+ * @return EINVAL If pD or PllCmnDigTbit13 is NULL.
+ * @return EOK On success.
+ */
+uint32_t DPHY_SetPllCmnDigTbit13(const DPHY_PrivateData* pD, const DPHY_PllCmnDigTbit13* config);
+
+/**
+ * Reads CmnDigTbit13 register.
+ * @param[in] pD Pointer to driver's private data object.
+ * @param[out] config Pointer to test register 13 data.
+ * @return EINVAL If pD or PllCmnDigTbit13 is NULL.
+ * @return EOK On success.
+ */
+uint32_t DPHY_GetPllCmnDigTbit13(const DPHY_PrivateData* pD, DPHY_PllCmnDigTbit13* config);
+
+/**
+ * Writes CmnDigTbit14 register.
+ * @param[in] pD Pointer to driver's private data object.
+ * @param[in] config Pointer to test register 14 data.
+ * @return EINVAL If pD or PllCmnDigTbit14 is NULL.
+ * @return EOK On success.
+ */
+uint32_t DPHY_SetPllCmnDigTbit14(const DPHY_PrivateData* pD, const DPHY_PllCmnDigTbit14* config);
+
+/**
+ * Reads CmnDigTbit14 register.
+ * @param[in] pD Pointer to driver's private data object.
+ * @param[out] config Pointer to test register 14 data.
+ * @return EINVAL If pD or PllCmnDigTbit14 is NULL.
+ * @return EOK On success.
+ */
+uint32_t DPHY_GetPllCmnDigTbit14(const DPHY_PrivateData* pD, DPHY_PllCmnDigTbit14* config);
+
+/**
+ * @}
+ */
+
+
+/* parasoft-end-suppress MISRA2012-RULE-1_1_b_c90-2 */
+/* parasoft-end-suppress MISRA2012-RULE-1_1_a_c90-2 */
+
+#endif /* DPHY_IF_H */
diff --git a/packages/ti/drv/dss/src/csl/dphy/include/dphy_regs.h b/packages/ti/drv/dss/src/csl/dphy/include/dphy_regs.h
--- /dev/null
@@ -0,0 +1,51 @@
+/******************************************************************************
+ * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * THIS FILE IS AUTOMATICALLY GENERATED, DO NOT EDIT
+ *
+ *****************************************************************************/
+
+// parasoft-begin-suppress MISRA2012-RULE-1_1_a_c90-2 "C90 - limits"
+// parasoft-begin-suppress MISRA2012-RULE-1_1_a_c99-2 "C99 - limits"
+
+#ifndef REG_PHY_REGS_H_
+#define REG_PHY_REGS_H_
+
+#include <cps_drv.h>
+
+
+typedef struct __attribute__((packed)) DPHY_Regs_s {
+ volatile char pad__0[0x4CU];
+ volatile uint32_t CMN0_CMN_DIG_TBIT13;
+ volatile uint32_t CMN0_CMN_DIG_TBIT14;
+} PHY_Regs;
+
+#endif /* REG_PHY_REGS_H_ */
+
+// parasoft-end-suppress MISRA2012-RULE-1_1_a_c99-2 "C99 - limits"
+// parasoft-end-suppress MISRA2012-RULE-1_1_a_c90-2 "C90 - limits"
+
diff --git a/packages/ti/drv/dss/src/csl/dphy/include/dphy_regs_macros.h b/packages/ti/drv/dss/src/csl/dphy/include/dphy_regs_macros.h
--- /dev/null
@@ -0,0 +1,92 @@
+/******************************************************************************
+ * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * THIS FILE IS AUTOMATICALLY GENERATED, DO NOT EDIT
+ *
+ *****************************************************************************/
+
+// parasoft-begin-suppress MISRA2012-RULE-1_1_b_c90-2 "C90 - limits"
+// parasoft-begin-suppress MISRA2012-RULE-1_1_b_c99-2 "C99 - limits"
+
+// parasoft-begin-suppress MISRA2012-RULE-5_4_b_c90-2 "C90 - similar names"
+// parasoft-begin-suppress MISRA2012-RULE-5_4_b_c99-2 "C99 - similar names"
+
+#ifndef REG_DPHY_REGS_MACROS_H_
+#define REG_DPHY_REGS_MACROS_H_
+
+#define DPHY__CMN0_CMN_DIG_TBIT13_READ_MASK 0xFFFFFFFFU
+#define DPHY__CMN0_CMN_DIG_TBIT13_WRITE_MASK 0xFFFFFFFFU
+#define DPHY__CMN0_CMN_DIG_TBIT13__UNUSED_MASK 0x000003FFU
+#define DPHY__CMN0_CMN_DIG_TBIT13__UNUSED_SHIFT 0U
+#define DPHY__CMN0_CMN_DIG_TBIT13__UNUSED_WIDTH 10U
+#define DPHY__CMN0_CMN_DIG_TBIT13__O_ANA_PLL_FB_DIV_HIGH_TM_SEL_MASK 0x00000400U
+#define DPHY__CMN0_CMN_DIG_TBIT13__O_ANA_PLL_FB_DIV_HIGH_TM_SEL_SHIFT 10U
+#define DPHY__CMN0_CMN_DIG_TBIT13__O_ANA_PLL_FB_DIV_HIGH_TM_SEL_WIDTH 1U
+#define DPHY__CMN0_CMN_DIG_TBIT13__O_ANA_PLL_FB_DIV_HIGH_TM_SEL_WOCLR 0U
+#define DPHY__CMN0_CMN_DIG_TBIT13__O_ANA_PLL_FB_DIV_HIGH_TM_SEL_WOSET 0U
+#define DPHY__CMN0_CMN_DIG_TBIT13__O_ANA_PLL_FB_DIV_HIGH_TM_MASK 0x001FF800U
+#define DPHY__CMN0_CMN_DIG_TBIT13__O_ANA_PLL_FB_DIV_HIGH_TM_SHIFT 11U
+#define DPHY__CMN0_CMN_DIG_TBIT13__O_ANA_PLL_FB_DIV_HIGH_TM_WIDTH 10U
+#define DPHY__CMN0_CMN_DIG_TBIT13__O_ANA_PLL_FB_DIV_LOW_TM_SEL_MASK 0x00200000U
+#define DPHY__CMN0_CMN_DIG_TBIT13__O_ANA_PLL_FB_DIV_LOW_TM_SEL_SHIFT 21U
+#define DPHY__CMN0_CMN_DIG_TBIT13__O_ANA_PLL_FB_DIV_LOW_TM_SEL_WIDTH 1U
+#define DPHY__CMN0_CMN_DIG_TBIT13__O_ANA_PLL_FB_DIV_LOW_TM_SEL_WOCLR 0U
+#define DPHY__CMN0_CMN_DIG_TBIT13__O_ANA_PLL_FB_DIV_LOW_TM_SEL_WOSET 0U
+#define DPHY__CMN0_CMN_DIG_TBIT13__O_ANA_PLL_FB_DIV_LOW_TM_MASK 0xFFC00000U
+#define DPHY__CMN0_CMN_DIG_TBIT13__O_ANA_PLL_FB_DIV_LOW_TM_SHIFT 22U
+#define DPHY__CMN0_CMN_DIG_TBIT13__O_ANA_PLL_FB_DIV_LOW_TM_WIDTH 10U
+
+#define DPHY__CMN0_CMN_DIG_TBIT14_READ_MASK 0xFFFFFFFFU
+#define DPHY__CMN0_CMN_DIG_TBIT14_WRITE_MASK 0xFFFFFFFFU
+#define DPHY__CMN0_CMN_DIG_TBIT14__O_ANA_PLL_IP_DIV_TM_SEL_MASK 0x00000001U
+#define DPHY__CMN0_CMN_DIG_TBIT14__O_ANA_PLL_IP_DIV_TM_SEL_SHIFT 0U
+#define DPHY__CMN0_CMN_DIG_TBIT14__O_ANA_PLL_IP_DIV_TM_SEL_WIDTH 1U
+#define DPHY__CMN0_CMN_DIG_TBIT14__O_ANA_PLL_IP_DIV_TM_SEL_WOCLR 0U
+#define DPHY__CMN0_CMN_DIG_TBIT14__O_ANA_PLL_IP_DIV_TM_SEL_WOSET 0U
+#define DPHY__CMN0_CMN_DIG_TBIT14__O_ANA_PLL_IP_DIV_TM_MASK 0x0000003EU
+#define DPHY__CMN0_CMN_DIG_TBIT14__O_ANA_PLL_IP_DIV_TM_SHIFT 1U
+#define DPHY__CMN0_CMN_DIG_TBIT14__O_ANA_PLL_IP_DIV_TM_WIDTH 5U
+#define DPHY__CMN0_CMN_DIG_TBIT14__O_ANA_PLL_OP_DIV_TM_SEL_MASK 0x00000040U
+#define DPHY__CMN0_CMN_DIG_TBIT14__O_ANA_PLL_OP_DIV_TM_SEL_SHIFT 6U
+#define DPHY__CMN0_CMN_DIG_TBIT14__O_ANA_PLL_OP_DIV_TM_SEL_WIDTH 1U
+#define DPHY__CMN0_CMN_DIG_TBIT14__O_ANA_PLL_OP_DIV_TM_SEL_WOCLR 0U
+#define DPHY__CMN0_CMN_DIG_TBIT14__O_ANA_PLL_OP_DIV_TM_SEL_WOSET 0U
+#define DPHY__CMN0_CMN_DIG_TBIT14__O_ANA_PLL_OP_DIV_TM_MASK 0x00001F80U
+#define DPHY__CMN0_CMN_DIG_TBIT14__O_ANA_PLL_OP_DIV_TM_SHIFT 7U
+#define DPHY__CMN0_CMN_DIG_TBIT14__O_ANA_PLL_OP_DIV_TM_WIDTH 6U
+#define DPHY__CMN0_CMN_DIG_TBIT14__UNUSED_MASK 0xFFFFE000U
+#define DPHY__CMN0_CMN_DIG_TBIT14__UNUSED_SHIFT 13U
+#define DPHY__CMN0_CMN_DIG_TBIT14__UNUSED_WIDTH 19U
+
+#endif /* REG_DPHY_REGS_MACROS_H_ */
+
+// parasoft-end-suppress MISRA2012-RULE-5_4_b_c99-2 "C99 - similar names"
+// parasoft-end-suppress MISRA2012-RULE-5_4_b_c90-2 "C90 - similar names"
+
+// parasoft-end-suppress MISRA2012-RULE-1_1_b_c99-2 "C99 - limits"
+// parasoft-end-suppress MISRA2012-RULE-1_1_b_c90-2 "C90 - limits"
+
diff --git a/packages/ti/drv/dss/src/csl/dphy/include/dphy_structs_if.h b/packages/ti/drv/dss/src/csl/dphy/include/dphy_structs_if.h
--- /dev/null
@@ -0,0 +1,87 @@
+/* parasoft suppress item MISRA2012-DIR-4_8 "Consider hiding implementation of structure" */
+/**********************************************************************
+ * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ **********************************************************************
+ * WARNING: This file is auto-generated using api-generator utility.
+ * api-generator: 13.00.31660be
+ * Do not edit it manually.
+ **********************************************************************
+ * DPHY PHY interface
+ **********************************************************************/
+#ifndef DPHY_STRUCTS_IF_H
+#define DPHY_STRUCTS_IF_H
+
+
+/** @defgroup DataStructure Dynamic Data Structures
+ * This section defines the data structures used by the driver to provide
+ * hardware information, modification and dynamic operation of the driver.
+ * These data structures are defined in the header file of the core driver
+ * and utilized by the API.
+ * @{
+ */
+
+/**********************************************************************
+ * Structures and unions
+ **********************************************************************/
+/** Driver private data */
+struct DPHY_PrivateData_s
+{
+ /** Base address for DPHY registers. */
+ struct DPHY_Regs_s* regBase;
+};
+
+/** Common digital test register 13 */
+struct DPHY_PllCmnDigTbit13_s
+{
+ /** PLL feedback divider low setting override value. */
+ uint32_t fbDivLowVal;
+ /** PLL feedback divider low setting override enable. */
+ bool fbDivLowEn;
+ /** PLL feedback divider high setting override value. */
+ bool fbDivHighEn;
+ /** PLL feedback divider high setting override enable. */
+ uint32_t fbDivHighVal;
+};
+
+/** Common digital test register 14 */
+struct DPHY_PllCmnDigTbit14_s
+{
+ /** PLL output divider low setting override value. */
+ uint32_t outDivLowVal;
+ /** PLL output divider low setting override enable. */
+ bool outDivLowEn;
+ /** PLL input divider low setting override value. */
+ uint32_t inDivLowVal;
+ /** PLL input divider low setting override enable. */
+ bool inDivLowEn;
+};
+
+/**
+ * @}
+ */
+
+#endif /* DPHY_STRUCTS_IF_H */
diff --git a/packages/ti/drv/dss/src/csl/dphy/src/cps_drv.h b/packages/ti/drv/dss/src/csl/dphy/src/cps_drv.h
--- /dev/null
@@ -0,0 +1,238 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ * cps_drv.h
+ * Interface for the Register Access Layer of Cadence Platform Service (CPS)
+ ******************************************************************************
+ */
+
+#ifndef CPS_DRV_H_
+#define CPS_DRV_H_
+
+#include "cps.h"
+
+// parasoft-begin-suppress MISRA2012-DIR-4_9-4 "function-like macro"
+// parasoft-begin-suppress MISRA2012-RULE-20_10-4 "## preprocessor operator"
+// parasoft-begin-suppress METRICS-36-3 "A function should not be called from more than 5 different functions"
+
+/**
+ * \brief Read a 32-bit value from memory.
+ * \param reg address of the memory mapped hardware register
+ * \return the value at the given address
+ */
+#define CPS_REG_READ(reg) (CPS_RegRead((volatile uint32_t*)(reg)))
+
+/**
+ * \brief Write a 32-bit address value to memory.
+ * \param reg address of the memory mapped hardware register
+ * \param value unsigned 32-bit value to write
+ */
+#define CPS_REG_WRITE(reg, value) (CPS_RegWrite((volatile uint32_t*)(reg), (uint32_t)(value)))
+
+/**
+ * \brief Read a 64-bit value from memory.
+ * \param reg address of the memory mapped hardware register
+ * \return the value at the given address
+ */
+#define CPS_REG_READ64(reg) (CPS_RegRead64((volatile uint64_t*)(reg)))
+
+/**
+ * \brief Write a 64-bit address value to memory.
+ * \param reg address of the memory mapped hardware register
+ * \param value unsigned 64-bit value to write
+ */
+#define CPS_REG_WRITE64(reg, value) (CPS_RegWrite64((volatile uint64_t*)(reg), (uint64_t)(value)))
+
+/**
+ * \brief Read a value of bit-field from the register value.
+ * \param reg register name
+ * \param fld field name
+ * \param reg_value register value
+ * \return bit-field value
+ */
+#define CPS_FLD_READ(reg, fld, reg_value) (CPS_FldRead((uint32_t)(reg##__##fld##_MASK), \
+ (uint32_t)(reg##__##fld##_SHIFT), \
+ (uint32_t)(reg_value)))
+
+/**
+ * \brief Write a value of the bit-field into the register value.
+ * \param reg register name
+ * \param fld field name
+ * \param reg_value register value
+ * \param value value to be written to bit-field
+ * \return modified register value
+ */
+#define CPS_FLD_WRITE(reg, fld, reg_value, value) (CPS_FldWrite((uint32_t)(reg##__##fld##_MASK), \
+ (uint32_t)(reg##__##fld##_SHIFT), \
+ (uint32_t)(reg_value), (uint32_t)(value)))
+
+/**
+ * \brief Set bit within the register value.
+ * \param reg register name
+ * \param fld field name
+ * \param reg_value register value
+ * \return modified register value
+ */
+#define CPS_FLD_SET(reg, fld, reg_value) (CPS_FldSet((uint32_t)(reg##__##fld##_WIDTH), \
+ (uint32_t)(reg##__##fld##_MASK), \
+ (uint32_t)(reg##__##fld##_WOCLR), \
+ (uint32_t)(reg_value)))
+
+/**
+ * \brief Clear bit within the register value.
+ * \param reg register name
+ * \param fld field name
+ * \param reg_value register value
+ * \return modified register value
+ */
+#define CPS_FLD_CLEAR(reg, fld, reg_value) (CPS_FldClear((uint32_t)(reg##__##fld##_WIDTH), \
+ (uint32_t)(reg##__##fld##_MASK), \
+ (uint32_t)(reg##__##fld##_WOSET), \
+ (uint32_t)(reg##__##fld##_WOCLR), \
+ (uint32_t)(reg_value)))
+
+/**
+ * \brief Read a 32-bit value from memory.
+ * \param reg address of the memory mapped hardware register
+ * \return the value at the given address
+ */
+static inline uint32_t CPS_RegRead(volatile uint32_t* reg)
+{
+ return (CSL_REG32_RD_RAW(reg));
+}
+
+/**
+ * \brief Write a 32-bit address value to memory.
+ * \param reg address of the memory mapped hardware register
+ * \param value unsigned 32-bit value to write
+ */
+static inline void CPS_RegWrite(volatile uint32_t* reg, uint32_t value)
+{
+ CSL_REG32_WR_RAW(reg, value);
+}
+
+/**
+ * \brief Read a 64-bit value from memory.
+ * \param reg address of the memory mapped hardware register
+ * \return the value at the given address
+ */
+static inline uint64_t CPS_RegRead64(volatile uint64_t* reg)
+{
+ return (CPS_ReadReg64(reg));
+}
+
+/**
+ * \brief Write a 64-bit address value to memory.
+ * \param reg address of the memory mapped hardware register
+ * \param value unsigned 64-bit value to write
+ */
+static inline void CPS_RegWrite64(volatile uint64_t* reg, uint64_t value)
+{
+ CPS_WriteReg64(reg, value);
+}
+
+/**
+ * \brief Read a value of bit-field from the register value.
+ * \param mask mask for the bit-field
+ * \param shift bit-field shift from LSB
+ * \param reg_value register value
+ * \return bit-field value
+ */
+static inline uint32_t CPS_FldRead(uint32_t mask, uint32_t shift, uint32_t reg_value)
+{
+ // parasoft-begin-suppress MISRA2012-RULE-12_2-2 "shift ranges"
+ uint32_t result = (reg_value & mask) >> shift;
+ // parasoft-end-suppress MISRA2012-RULE-12_2-2
+
+ return (result);
+}
+
+/**
+ * \brief Write a value of the bit-field into the register value.
+ * \param mask mask for the bit-field
+ * \param shift bit-field shift from LSB
+ * \param reg_value register value
+ * \param value value to be written to bit-field
+ * \return modified register value
+ */
+static inline uint32_t CPS_FldWrite(uint32_t mask, uint32_t shift, uint32_t reg_value, uint32_t value)
+{
+ // parasoft-begin-suppress MISRA2012-RULE-12_2-2 "shift ranges"
+ uint32_t new_value = (value << shift) & mask;
+ // parasoft-end-suppress MISRA2012-RULE-12_2-2
+
+ new_value = (reg_value & ~mask) | new_value;
+ return (new_value);
+}
+
+/**
+ * \brief Set bit within the register value.
+ * \param width width of the bit-field
+ * \param mask mask for the bit-field
+ * \param is_woclr is bit-field has 'write one to clear' flag set
+ * \param reg_value register value
+ * \return modified register value
+ */
+static inline uint32_t CPS_FldSet(uint32_t width, uint32_t mask, uint32_t is_woclr, uint32_t reg_value)
+{
+ uint32_t new_value = reg_value;
+ if ((width == 1U) && (is_woclr == 0U)) {
+ new_value |= mask;
+ }
+
+ return (new_value);
+}
+
+/**
+ * \brief Clear bit within the register value.
+ *
+ * \param width Width of the bit-field.
+ * \param mask Mask for the bit-field.
+ * \param is_woset Is bit-field has 'write one to set' flag set.
+ * \param is_woclr Is bit-field has 'write one to clear' flag set.
+ * \param reg_value Register value.
+ *
+ * \return Modified register value.
+ */
+static inline uint32_t CPS_FldClear(uint32_t width, uint32_t mask, uint32_t is_woset, uint32_t is_woclr, uint32_t reg_value)
+{
+ uint32_t new_value = reg_value;
+ if ((width == 1U) && (is_woset == 0U)) {
+ new_value = (new_value & ~mask) | ((is_woclr != 0U) ? mask : 0U);
+ }
+
+ return (new_value);
+}
+
+// parasoft-end-suppress MISRA2012-RULE-20_10-4
+// parasoft-end-suppress MISRA2012-DIR-4_9-4
+// parasoft-end-suppress METRICS-36-3
+
+#endif /* CPS_DRV_H_ */
+
diff --git a/packages/ti/drv/dss/src/csl/dphy/src/dphy_if.c b/packages/ti/drv/dss/src/csl/dphy/src/dphy_if.c
--- /dev/null
@@ -0,0 +1,194 @@
+/******************************************************************************
+ * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * This file contains DPHY PHY API implementation.
+ *
+ *****************************************************************************/
+
+#include <src/csl/dphy/csl_dphy.h>
+
+#include "dphy_if_sanity.h"
+
+// parasoft-begin-suppress METRICS-36-3 "A function should not be called from more than 5 different functions"
+
+/**
+ * Returns 1U or 0U depending on a received flag in the type of bool.
+ */
+static inline uint32_t boolToVal(bool state) {
+ return ((state == true) ? 1U : 0U);
+}
+
+/**
+ * Returns true or false depending on a received uint32_t value.
+ */
+static inline bool valToBool(uint32_t value) {
+ return ((value != 0U) ? (bool) true : (bool) false);
+}
+
+/**
+ * Writes CmnDigTbit13 register.
+ * @param[in] pD Pointer to driver's private data object.
+ * @param[in] config Pointer to test register 13 data.
+ * @return CDN_EINVAL If pD or PllCmnDigTbit13 is NULL.
+ * @return CDN_EOK On success.
+ */
+uint32_t DPHY_SetPllCmnDigTbit13(const DPHY_PrivateData *pD,
+ const DPHY_PllCmnDigTbit13 *config) {
+ uint32_t status = CDN_EOK;
+
+ /* check params */
+ if (DPHY_SetPllCmnDigTbit13SF(pD, config) != CDN_EOK) {
+ status = CDN_EINVAL;
+ } else {
+ uint32_t regVal = 0U;
+
+ /* build dphy settings register value */
+ regVal = CPS_FLD_WRITE(DPHY__CMN0_CMN_DIG_TBIT13,
+ O_ANA_PLL_FB_DIV_LOW_TM_SEL, regVal,
+ boolToVal(config->fbDivLowEn));
+ regVal = CPS_FLD_WRITE(DPHY__CMN0_CMN_DIG_TBIT13,
+ O_ANA_PLL_FB_DIV_LOW_TM, regVal, config->fbDivLowVal);
+
+ regVal = CPS_FLD_WRITE(DPHY__CMN0_CMN_DIG_TBIT13,
+ O_ANA_PLL_FB_DIV_HIGH_TM_SEL, regVal,
+ boolToVal(config->fbDivHighEn));
+ regVal = CPS_FLD_WRITE(DPHY__CMN0_CMN_DIG_TBIT13,
+ O_ANA_PLL_FB_DIV_HIGH_TM, regVal, config->fbDivHighVal);
+
+ /* write value to register */
+ CPS_REG_WRITE(&pD->regBase->CMN0_CMN_DIG_TBIT13, regVal);
+ }
+ return status;
+}
+
+/**
+ * Reads CmnDigTbit13 register.
+ * @param[in] pD Pointer to driver's private data object.
+ * @param[out] config Pointer to test register 13 data.
+ * @return CDN_EINVAL If pD or PllCmnDigTbit13 is NULL.
+ * @return CDN_EOK On success.
+ */
+uint32_t DPHY_GetPllCmnDigTbit13(const DPHY_PrivateData *pD,
+ DPHY_PllCmnDigTbit13 *config) {
+ uint32_t status = CDN_EOK;
+
+ /* check params */
+ if (DPHY_GetPllCmnDigTbit13SF(pD, config) != CDN_EOK) {
+ status = CDN_EINVAL;
+ } else {
+ /* read register value */
+ uint32_t regVal = CPS_REG_READ(&pD->regBase->CMN0_CMN_DIG_TBIT13);
+
+ /* split value to fields */
+ config->fbDivLowEn = valToBool(
+ CPS_FLD_READ(DPHY__CMN0_CMN_DIG_TBIT13,
+ O_ANA_PLL_FB_DIV_LOW_TM_SEL,
+ regVal));
+ config->fbDivLowVal = CPS_FLD_READ(DPHY__CMN0_CMN_DIG_TBIT13,
+ O_ANA_PLL_FB_DIV_LOW_TM, regVal);
+
+ config->fbDivHighEn = valToBool(
+ CPS_FLD_READ(DPHY__CMN0_CMN_DIG_TBIT13,
+ O_ANA_PLL_FB_DIV_HIGH_TM_SEL, regVal));
+
+ config->fbDivHighVal = CPS_FLD_READ(DPHY__CMN0_CMN_DIG_TBIT13,
+ O_ANA_PLL_FB_DIV_HIGH_TM, regVal);
+ }
+ return status;
+}
+
+/**
+ * Writes CmnDigTbit14 register.
+ * @param[in] pD Pointer to driver's private data object.
+ * @param[in] config Pointer to test register 14 data.
+ * @return CDN_EINVAL If pD or PllCmnDigTbit14 is NULL.
+ * @return CDN_EOK On success.
+ */
+uint32_t DPHY_SetPllCmnDigTbit14(const DPHY_PrivateData *pD,
+ const DPHY_PllCmnDigTbit14 *config) {
+ uint32_t status = CDN_EOK;
+
+ /* check params */
+ if (DPHY_SetPllCmnDigTbit14SF(pD, config) != CDN_EOK) {
+ status = CDN_EINVAL;
+ } else {
+ uint32_t regVal = 0U;
+
+ /* build dphy settings register value */
+ regVal = CPS_FLD_WRITE(DPHY__CMN0_CMN_DIG_TBIT14,
+ O_ANA_PLL_OP_DIV_TM_SEL, regVal,
+ boolToVal(config->outDivLowEn));
+ regVal = CPS_FLD_WRITE(DPHY__CMN0_CMN_DIG_TBIT14, O_ANA_PLL_OP_DIV_TM,
+ regVal, config->outDivLowVal);
+
+ regVal = CPS_FLD_WRITE(DPHY__CMN0_CMN_DIG_TBIT14,
+ O_ANA_PLL_IP_DIV_TM_SEL, regVal, boolToVal(config->inDivLowEn));
+ regVal = CPS_FLD_WRITE(DPHY__CMN0_CMN_DIG_TBIT14, O_ANA_PLL_IP_DIV_TM,
+ regVal, config->inDivLowVal);
+
+ /* write value to register */
+ CPS_REG_WRITE(&pD->regBase->CMN0_CMN_DIG_TBIT14, regVal);
+ }
+ return status;
+}
+
+/**
+ * Reads CmnDigTbit14 register.
+ * @param[in] pD Pointer to driver's private data object.
+ * @param[out] config Pointer to test register 14 data.
+ * @return CDN_EINVAL If pD or PllCmnDigTbit14 is NULL.
+ * @return CDN_EOK On success.
+ */
+uint32_t DPHY_GetPllCmnDigTbit14(const DPHY_PrivateData *pD,
+ DPHY_PllCmnDigTbit14 *config) {
+ uint32_t status = CDN_EOK;
+
+ /* check params */
+ if (DPHY_GetPllCmnDigTbit14SF(pD, config) != CDN_EOK) {
+ status = CDN_EINVAL;
+ } else {
+ /* read register value */
+ uint32_t regVal = CPS_REG_READ(&pD->regBase->CMN0_CMN_DIG_TBIT14);
+
+ /* split value to fields */
+ config->outDivLowEn = valToBool(
+ CPS_FLD_READ(DPHY__CMN0_CMN_DIG_TBIT14,
+ O_ANA_PLL_OP_DIV_TM_SEL,
+ regVal));
+ config->outDivLowVal = CPS_FLD_READ(DPHY__CMN0_CMN_DIG_TBIT14,
+ O_ANA_PLL_OP_DIV_TM, regVal);
+
+ config->inDivLowEn = valToBool(
+ CPS_FLD_READ(DPHY__CMN0_CMN_DIG_TBIT14, O_ANA_PLL_IP_DIV_TM_SEL,
+ regVal));
+ config->inDivLowVal = CPS_FLD_READ(DPHY__CMN0_CMN_DIG_TBIT14,
+ O_ANA_PLL_IP_DIV_TM, regVal);
+ }
+ return status;
+}
+
+// parasoft-end-suppress METRICS-36-3
diff --git a/packages/ti/drv/dss/src/csl/dphy/src/dphy_if_sanity.c b/packages/ti/drv/dss/src/csl/dphy/src/dphy_if_sanity.c
--- /dev/null
@@ -0,0 +1,268 @@
+/**********************************************************************
+ * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ **********************************************************************
+ * WARNING: This file is auto-generated using api-generator utility.
+ * api-generator: 13.00.31660be
+ * Do not edit it manually.
+ **********************************************************************
+ * DPHY PHY interface
+ **********************************************************************/
+
+/* parasoft-begin-suppress METRICS-18-3 "Follow the Cyclomatic Complexity limit of 10" */
+/* parasoft-begin-suppress METRICS-36-3 "A function should not be called from more than 5 different functions" */
+/* parasoft-begin-suppress METRICS-39-3 "The value of VOCF metric for a function should not be higher than 4" */
+/* parasoft-begin-suppress METRICS-41-3 "Number of blocks of comments per statement" */
+/* parasoft-begin-suppress MISRA2012-RULE-8_7 "Functions and objects should not be defined with external linkage if they are referenced in only one translation unit" */
+
+/**
+ * This file contains sanity API functions. The purpose of sanity functions
+ * is to check input parameters validity. They take the same parameters as
+ * original API functions and return 0 on success or CDN_EINVAL on wrong parameter
+ * value(s).
+ */
+
+#include "src/csl/dphy/csl_dphy.h"
+#include "dphy_if_sanity.h"
+
+/**
+ * Function to validate struct PrivateData
+ *
+ * @param[in] obj pointer to struct to be verified
+ * @returns 0 for valid
+ * @returns CDN_EINVAL for invalid
+ */
+uint32_t DPHY_PrivateDataSF(const DPHY_PrivateData *obj)
+{
+ uint32_t ret = 0;
+
+ if (obj == NULL)
+ {
+ ret = CDN_EINVAL;
+ }
+
+ return ret;
+}
+
+
+/**
+ * Function to validate struct PllCmnDigTbit13
+ *
+ * @param[in] obj pointer to struct to be verified
+ * @returns 0 for valid
+ * @returns CDN_EINVAL for invalid
+ */
+uint32_t DPHY_PllCmnDigTbit13SF(const DPHY_PllCmnDigTbit13 *obj)
+{
+ uint32_t ret = 0;
+
+ if (obj == NULL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ if (obj->fbDivLowVal > (0x3FFU))
+ {
+ ret = CDN_EINVAL;
+ }
+ if (obj->fbDivHighVal > (0x3FFU))
+ {
+ ret = CDN_EINVAL;
+ }
+ }
+
+ return ret;
+}
+
+
+/**
+ * Function to validate struct PllCmnDigTbit14
+ *
+ * @param[in] obj pointer to struct to be verified
+ * @returns 0 for valid
+ * @returns CDN_EINVAL for invalid
+ */
+uint32_t DPHY_PllCmnDigTbit14SF(const DPHY_PllCmnDigTbit14 *obj)
+{
+ uint32_t ret = 0;
+
+ if (obj == NULL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ if (obj->outDivLowVal > (0x3FU))
+ {
+ ret = CDN_EINVAL;
+ }
+ if (obj->inDivLowVal > (0x1FU))
+ {
+ ret = CDN_EINVAL;
+ }
+ }
+
+ return ret;
+}
+
+
+/**
+ * A common function to check the validity of API functions with
+ * following parameter types
+ * @param[in] pD Pointer to driver's private data object.
+ * @param[in] config Pointer to test register 13 data.
+ * @return 0 success
+ * @return CDN_EINVAL invalid parameters
+ */
+uint32_t DPHY_SanityFunction1(const DPHY_PrivateData* pD, const DPHY_PllCmnDigTbit13* config)
+{
+ /* Declaring return variable */
+ uint32_t ret = 0;
+
+ if (DPHY_PrivateDataSF(pD) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (DPHY_PllCmnDigTbit13SF(config) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ /*
+ * All 'if ... else if' constructs shall be terminated with an 'else' statement
+ * (MISRA2012-RULE-15_7-3)
+ */
+ }
+
+ return ret;
+}
+
+
+/**
+ * A common function to check the validity of API functions with
+ * following parameter types
+ * @param[in] pD Pointer to driver's private data object.
+ * @param[out] config Pointer to test register 13 data.
+ * @return 0 success
+ * @return CDN_EINVAL invalid parameters
+ */
+uint32_t DPHY_SanityFunction2(const DPHY_PrivateData* pD, const DPHY_PllCmnDigTbit13* config)
+{
+ /* Declaring return variable */
+ uint32_t ret = 0;
+
+ if (config == NULL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (DPHY_PrivateDataSF(pD) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ /*
+ * All 'if ... else if' constructs shall be terminated with an 'else' statement
+ * (MISRA2012-RULE-15_7-3)
+ */
+ }
+
+ return ret;
+}
+
+
+/**
+ * A common function to check the validity of API functions with
+ * following parameter types
+ * @param[in] pD Pointer to driver's private data object.
+ * @param[in] config Pointer to test register 14 data.
+ * @return 0 success
+ * @return CDN_EINVAL invalid parameters
+ */
+uint32_t DPHY_SanityFunction3(const DPHY_PrivateData* pD, const DPHY_PllCmnDigTbit14* config)
+{
+ /* Declaring return variable */
+ uint32_t ret = 0;
+
+ if (DPHY_PrivateDataSF(pD) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (DPHY_PllCmnDigTbit14SF(config) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ /*
+ * All 'if ... else if' constructs shall be terminated with an 'else' statement
+ * (MISRA2012-RULE-15_7-3)
+ */
+ }
+
+ return ret;
+}
+
+
+/**
+ * A common function to check the validity of API functions with
+ * following parameter types
+ * @param[in] pD Pointer to driver's private data object.
+ * @param[out] config Pointer to test register 14 data.
+ * @return 0 success
+ * @return CDN_EINVAL invalid parameters
+ */
+uint32_t DPHY_SanityFunction4(const DPHY_PrivateData* pD, const DPHY_PllCmnDigTbit14* config)
+{
+ /* Declaring return variable */
+ uint32_t ret = 0;
+
+ if (config == NULL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (DPHY_PrivateDataSF(pD) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ /*
+ * All 'if ... else if' constructs shall be terminated with an 'else' statement
+ * (MISRA2012-RULE-15_7-3)
+ */
+ }
+
+ return ret;
+}
+
+/* parasoft-end-suppress MISRA2012-RULE-8_7 */
+/* parasoft-end-suppress METRICS-41-3 */
+/* parasoft-end-suppress METRICS-39-3 */
+/* parasoft-end-suppress METRICS-36-3 */
+/* parasoft-end-suppress METRICS-18-3 */
diff --git a/packages/ti/drv/dss/src/csl/dphy/src/dphy_if_sanity.h b/packages/ti/drv/dss/src/csl/dphy/src/dphy_if_sanity.h
--- /dev/null
@@ -0,0 +1,73 @@
+/**********************************************************************
+ * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ **********************************************************************
+ * WARNING: This file is auto-generated using api-generator utility.
+ * api-generator: 13.00.31660be
+ * Do not edit it manually.
+ **********************************************************************
+ * DPHY PHY interface
+ **********************************************************************/
+
+/* parasoft-begin-suppress METRICS-18-3 "Follow the Cyclomatic Complexity limit of 10" */
+/* parasoft-begin-suppress METRICS-36-3 "A function should not be called from more than 5 different functions" */
+/* parasoft-begin-suppress METRICS-39-3 "The value of VOCF metric for a function should not be higher than 4" */
+/* parasoft-begin-suppress METRICS-41-3 "Number of blocks of comments per statement" */
+/* parasoft-begin-suppress MISRA2012-RULE-8_7 "Functions and objects should not be defined with external linkage if they are referenced in only one translation unit" */
+
+/**
+ * This file contains sanity API functions. The purpose of sanity functions
+ * is to check input parameters validity. They take the same parameters as
+ * original API functions and return 0 on success or CDN_EINVAL on wrong parameter
+ * value(s).
+ */
+
+#ifndef DPHY_IF_SANITY_H
+#define DPHY_IF_SANITY_H
+
+
+uint32_t DPHY_PllCmnDigTbit13SF(const DPHY_PllCmnDigTbit13 *obj);
+uint32_t DPHY_PllCmnDigTbit14SF(const DPHY_PllCmnDigTbit14 *obj);
+uint32_t DPHY_PrivateDataSF(const DPHY_PrivateData *obj);
+
+uint32_t DPHY_SanityFunction1(const DPHY_PrivateData* pD, const DPHY_PllCmnDigTbit13* config);
+uint32_t DPHY_SanityFunction2(const DPHY_PrivateData* pD, const DPHY_PllCmnDigTbit13* config);
+uint32_t DPHY_SanityFunction3(const DPHY_PrivateData* pD, const DPHY_PllCmnDigTbit14* config);
+uint32_t DPHY_SanityFunction4(const DPHY_PrivateData* pD, const DPHY_PllCmnDigTbit14* config);
+
+#define DPHY_SetPllCmnDigTbit13SF DPHY_SanityFunction1
+#define DPHY_GetPllCmnDigTbit13SF DPHY_SanityFunction2
+#define DPHY_SetPllCmnDigTbit14SF DPHY_SanityFunction3
+#define DPHY_GetPllCmnDigTbit14SF DPHY_SanityFunction4
+
+
+#endif /* DPHY_IF_SANITY_H */
+
+/* parasoft-end-suppress MISRA2012-RULE-8_7 */
+/* parasoft-end-suppress METRICS-41-3 */
+/* parasoft-end-suppress METRICS-39-3 */
+/* parasoft-end-suppress METRICS-36-3 */
+/* parasoft-end-suppress METRICS-18-3 */
diff --git a/packages/ti/drv/dss/src/csl/dphy/src/src_files_dphy.mk b/packages/ti/drv/dss/src/csl/dphy/src/src_files_dphy.mk
--- /dev/null
@@ -0,0 +1,3 @@
+SRCDIR += src/csl/dphy/src
+INCDIR += src/csl/dphy/include src/csl/dphy/src
+SRCS_COMMON +=
\ No newline at end of file
diff --git a/packages/ti/drv/dss/src/csl/dsi/csl_dsi.h b/packages/ti/drv/dss/src/csl/dsi/csl_dsi.h
--- /dev/null
@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) Texas Instruments Incorporated 2018
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+/**
+ * \file csl_dsi.h
+ *
+ * \brief CSL APIs for DSI-TX.
+ */
+
+#ifndef CSL_DSI_H_
+#define CSL_DSI_H_
+
+#include <src/csl/dsi/cslr_dsi.h>
+#include <src/csl/dsi/include/cdn_errno.h>
+#include <src/csl/dsi/include/dsitx_if.h>
+#include <src/csl/dsi/include/dsitx_structs_if.h>
+#include <src/csl/dsi/include/dsitx_priv.h>
+
+#endif
diff --git a/packages/ti/drv/dss/src/csl/dsi/cslr_dsi.h b/packages/ti/drv/dss/src/csl/dsi/cslr_dsi.h
--- /dev/null
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) Texas Instruments Incorporated 2018
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+/**
+ * \file cslr_dsi.h
+ *
+ * \brief CSLR for DSI-TX.
+ */
+
+#ifndef CSLR_DSI_H_
+#define CSLR_DSI_H_
+
+#include <stdbool.h>
+#include <stddef.h>
+#include <stdint.h>
+
+#include <ti/csl/cslr_dss.h>
+#include <src/csl/dsi/include/dsitx_regs.h>
+#include <src/csl/dsi/include/dsitx_regs_macros.h>
+
+#endif
diff --git a/packages/ti/drv/dss/src/csl/dsi/include/cdn_errno.h b/packages/ti/drv/dss/src/csl/dsi/include/cdn_errno.h
--- /dev/null
@@ -0,0 +1,165 @@
+/******************************************************************************
+ * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ * cdn_errno.h
+ * Cadence error codes
+ ******************************************************************************
+ */
+
+#ifndef INCLUDE_CDN_ERRNO_H
+#define INCLUDE_CDN_ERRNO_H
+
+#ifndef ERRNO_H_NOT_PRESENT
+#include <errno.h>
+#endif //ERRNO_H_NOT_PRESENT
+
+#ifndef REMOVE_OLD_ERRORCODES
+
+#ifndef EOK
+#define EOK 0 /* no error */
+#endif //EOK
+
+#ifndef EPERM
+#define EPERM 1 /* Operation not permitted */
+#endif //EPERM
+
+#ifndef ENOENT
+#define ENOENT 2 /* No such file or directory */
+#endif //ENOENT
+
+#ifndef EIO
+#define EIO 5 /* I/O error */
+#endif //EIO
+
+#ifndef ENOEXEC
+#define ENOEXEC 8 /* Exec format error */
+#endif //ENOEXEC
+
+#ifndef EAGAIN
+#define EAGAIN 11 /* Try again */
+#endif //EAGAIN
+
+#ifndef ENOMEM
+#define ENOMEM 12 /* Out of memory */
+#endif //ENOMEM
+
+#ifndef EFAULT
+#define EFAULT 14 /* Bad address */
+#endif //EFAULT
+
+#ifndef EBUSY
+#define EBUSY 16 /* Device or resource busy */
+#endif //EBUSY
+
+#ifndef EINVAL
+#define EINVAL 22 /* Invalid argument */
+#endif //EINVAL
+
+#ifndef ENOSPC
+#define ENOSPC 28 /* No space left on device */
+#endif //ENOSPC
+
+#ifndef EBADSLT
+#define EBADSLT 57 /* Invalid slot */
+#endif //EBADSLT
+
+#ifndef EPROTO
+#define EPROTO 71 /* Protocol error */
+#endif //EPROTO
+
+#ifndef EOVERFLOW
+#define EOVERFLOW 75 /* Value too large for defined data type */
+#endif //EOVERFLOW
+
+#ifndef EOPNOTSUPP
+#define EOPNOTSUPP 95 /* Operation not supported */
+#endif //EOPNOTSUPP
+
+#ifndef ETIMEDOUT
+#define ETIMEDOUT 110 /* Connection timed out */
+#endif //ETIMEDOUT
+
+#ifndef EINPROGRESS
+#define EINPROGRESS 115 /* Operation now in progress */
+#endif //EINPROGRESS
+
+#ifndef EDQUOT
+#define EDQUOT 122 /* Quota exceeded */
+#endif //EDQUOT
+
+#ifndef ENOTSUP
+#define ENOTSUP EOPNOTSUPP
+#endif //ENOTSUP
+
+#ifndef ECANCELED
+#define ECANCELED 126 /* Cancelled */
+#endif //ECANCELED
+
+#endif //REMOVE_OLD_ERRORCODES
+
+#define CDN_EOK 0U /* no error */
+
+#define CDN_EPERM 1U /* Operation not permitted */
+
+#define CDN_ENOENT 2U /* No such file or directory */
+
+#define CDN_EIO 5U /* I/O error */
+
+#define CDN_ENOEXEC 8U /* Exec format error */
+
+#define CDN_EAGAIN 11U /* Try again */
+
+#define CDN_ENOMEM 12U /* Out of memory */
+
+#define CDN_EFAULT 14U /* Bad address */
+
+#define CDN_EBUSY 16U /* Device or resource busy */
+
+#define CDN_EINVAL 22U /* Invalid argument */
+
+#define CDN_ENOSPC 28U /* No space left on device */
+
+#define CDN_EBADSLT 57U /* Invalid slot */
+
+#define CDN_EPROTO 71U /* Protocol error */
+
+#define CDN_EOVERFLOW 75U /* Value too large for defined data type */
+
+#define CDN_EOPNOTSUPP 95U /* Operation not supported */
+
+#define CDN_ETIMEDOUT 110U /* Connection timed out */
+
+#define CDN_EINPROGRESS 115U /* Operation now in progress */
+
+#define CDN_EDQUOT 122U /* Quota exceeded */
+
+#define CDN_ENOTSUP CDN_EOPNOTSUPP
+
+#define CDN_ECANCELED 126U /* Cancelled */
+
+#endif //INCLUDE_CDN_ERRNO_H
diff --git a/packages/ti/drv/dss/src/csl/dsi/include/dsitx_if.h b/packages/ti/drv/dss/src/csl/dsi/include/dsitx_if.h
--- /dev/null
@@ -0,0 +1,1068 @@
+/**********************************************************************
+ * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ **********************************************************************
+ * WARNING: This file is auto-generated using api-generator utility.
+ * api-generator: 13.00.31660be
+ * Do not edit it manually.
+ **********************************************************************
+ * Cadence Core Driver for MIPI DSITX Host Controller
+ **********************************************************************/
+
+#ifndef DSITX_IF_H
+#define DSITX_IF_H
+
+/* parasoft-begin-suppress MISRA2012-RULE-1_1_a_c90-2 "C90 - limits, DRV-3906" */
+/* parasoft-begin-suppress MISRA2012-RULE-1_1_b_c90-2 "C90 - limits, DRV-3906" */
+
+
+/** @defgroup ConfigInfo Configuration and Hardware Operation Information
+ * The following definitions specify the driver operation environment that
+ * is defined by hardware configuration or client code. These defines are
+ * located in the header file of the core driver.
+ * @{
+ */
+
+/**********************************************************************
+* Defines
+**********************************************************************/
+#define DSITX_MAX_LANE_NUMBER 4U
+
+#define DSITX_MAGIC_NUMBER 0xCADD5U
+
+/**
+ * @}
+ */
+
+
+/** @defgroup DataStructure Dynamic Data Structures
+ * This section defines the data structures used by the driver to provide
+ * hardware information, modification and dynamic operation of the driver.
+ * These data structures are defined in the header file of the core driver
+ * and utilized by the API.
+ * @{
+ */
+
+/**********************************************************************
+ * Forward declarations
+ **********************************************************************/
+typedef struct DSITX_DphyPwrRstConfig_s DSITX_DphyPwrRstConfig;
+typedef struct DSITX_DscEventStatus_s DSITX_DscEventStatus;
+typedef struct DSITX_DphyConfig_s DSITX_DphyConfig;
+typedef struct DSITX_DataPathConfig_s DSITX_DataPathConfig;
+typedef struct DSITX_PhyConfig_s DSITX_PhyConfig;
+typedef struct DSITX_Video3dConfig_s DSITX_Video3dConfig;
+typedef struct DSITX_CommandModeSettings_s DSITX_CommandModeSettings;
+typedef struct DSITX_VideoSize_s DSITX_VideoSize;
+typedef struct DSITX_Color_s DSITX_Color;
+typedef struct DSITX_ErrorColor_s DSITX_ErrorColor;
+typedef struct DSITX_VcaConfig_s DSITX_VcaConfig;
+typedef struct DSITX_VideoModeSettings_s DSITX_VideoModeSettings;
+typedef struct DSITX_TestVideoModeConfig_s DSITX_TestVideoModeConfig;
+typedef struct DSITX_IpConf_s DSITX_IpConf;
+typedef struct DSITX_HwIdAndVersion_s DSITX_HwIdAndVersion;
+typedef struct DSITX_DsiLinkConfig_s DSITX_DsiLinkConfig;
+typedef struct DSITX_DirectCommandRequest_s DSITX_DirectCommandRequest;
+typedef struct DSITX_TestGeneric_s DSITX_TestGeneric;
+typedef struct DSITX_Config_s DSITX_Config;
+typedef struct DSITX_SysReq_s DSITX_SysReq;
+typedef struct DSITX_AsfInfo_s DSITX_AsfInfo;
+
+typedef struct DSITX_PrivateData_s DSITX_PrivateData;
+
+/**********************************************************************
+ * Enumerations
+ **********************************************************************/
+/** Status of the DSITX Link. */
+typedef enum
+{
+ /** Initial value. */
+ DSITX_LINK_STATUS_BITS_INIT = 0U,
+ /** Interface 1 signals an unterminated packet. */
+ DSITX_MAIN_STS_IF1_UNTERM_PCK = DSITX__MCTL_MAIN_STS__IF1_UNTERM_PCK_MASK,
+ /** Signals an LP_RX time-out error. */
+ DSITX_MAIN_STS_LPRX_TO_ERR = DSITX__MCTL_MAIN_STS__LPRX_TO_ERR_MASK,
+ /** Signals an HS_TX time-out error. */
+ DSITX_MAIN_STS_HSTX_TO_ERR = DSITX__MCTL_MAIN_STS__HSTX_TO_ERR_MASK,
+ /** Signals data lane 4 is ready. */
+ DSITX_MAIN_STS_DAT4_READY = DSITX__MCTL_MAIN_STS__DAT4_READY_MASK,
+ /** Signals data lane 3 is ready. */
+ DSITX_MAIN_STS_DAT3_READY = DSITX__MCTL_MAIN_STS__DAT3_READY_MASK,
+ /** Signals data lane 2 is ready. */
+ DSITX_MAIN_STS_DAT2_READY = DSITX__MCTL_MAIN_STS__DAT2_READY_MASK,
+ /** Signals data lane 1 is ready. */
+ DSITX_MAIN_STS_DAT1_READY = DSITX__MCTL_MAIN_STS__DAT1_READY_MASK,
+ /** Signals clock lane is ready (normal DSITX operation can start). */
+ DSITX_MAIN_STS_CLKLANE_READY = DSITX__MCTL_MAIN_STS__CLKLANE_READY_MASK,
+ /** Signals PLL is locked - data coming from DCB (if DSITX link is PLL master) or copy of pll_en (if DSITX link is slave). */
+ DSITX_MAIN_STS_PLL_LCK = DSITX__MCTL_MAIN_STS__PLL_LCK_MASK
+} DSITX_LinkStatusBits;
+
+/** Status and error bits of the Command Mode operations. */
+typedef enum
+{
+ /** Initial value. */
+ DSITX_CMD_MODE_STATUS_BITS_INIT = 0U,
+ /** Signals if CSM is running - command(s) are being proceeded. */
+ DSITX_CMD_MODE_STS_CSM_RUNNING = DSITX__CMD_MODE_STS__CSM_RUNNING_MASK,
+ /** A read request was received while read capability was not enabled. */
+ DSITX_CMD_MODE_STS_ERR_UNWANTED_RD = DSITX__CMD_MODE_STS__ERR_UNWANTED_RD_MASK,
+ /** Signals when a data shortage occurs on IF1. */
+ DSITX_CMD_MODE_STS_ERR_IF1_UNDERRUN = DSITX__CMD_MODE_STS__ERR_IF1_UNDERRUN_MASK,
+ /** TE window time-out. */
+ DSITX_CMD_MODE_STS_ERR_TE_MISS = DSITX__CMD_MODE_STS__ERR_TE_MISS_MASK,
+ /** No TE generated by display. */
+ DSITX_CMD_MODE_STS_ERR_NO_TE = DSITX__CMD_MODE_STS__ERR_NO_TE_MASK
+} DSITX_CmdModeStatusBits;
+
+/** Status and error bits of the Video Mode operations. */
+typedef enum
+{
+ /** Initial value. */
+ DSITX_VID_MODE_STATUS_BITS_INIT = 0U,
+ /** Specifies whether the VSG is in recovery mode or not. */
+ DSITX_VID_STS_VSG_RECOVERY = DSITX__VID_MODE_STS__VSG_RECOVERY_MASK,
+ /** Signals that packets in SDI interface differ from the expected size (as specified by rgb_size). */
+ DSITX_VID_STS_ERR_VRS_WRONG_LENGTH = DSITX__VID_MODE_STS__ERR_VRS_WRONG_LENGTH_MASK,
+ /** Signals the read was too long. */
+ DSITX_VID_STS_ERR_LONGREAD = DSITX__VID_MODE_STS__ERR_LONGREAD_MASK,
+ /** Signals the long packet is too long to pass during a long slot. */
+ DSITX_VID_STS_ERR_LINEWRITE = DSITX__VID_MODE_STS__ERR_LINEWRITE_MASK,
+ /** Signals a 'long' packet has been sent during active area. */
+ DSITX_VID_STS_ERR_BURSTWRITE = DSITX__VID_MODE_STS__ERR_BURSTWRITE_MASK,
+ /** Less lines than expected between 2 VSYNC. */
+ DSITX_VID_STS_REG_ERR_SMALL_HEIGHT = DSITX__VID_MODE_STS__REG_ERR_SMALL_HEIGHT_MASK,
+ /** Less bytes received than expected between 2 HSYNC. */
+ DSITX_VID_STS_REG_ERR_SMALL_LENGTH = DSITX__VID_MODE_STS__REG_ERR_SMALL_LENGTH_MASK,
+ /** Missing VSYNC. */
+ DSITX_VID_STS_ERR_MISSING_VSYNC = DSITX__VID_MODE_STS__ERR_MISSING_VSYNC_MASK,
+ /** Missing HSYNC. */
+ DSITX_VID_STS_ERR_MISSING_HSYNC = DSITX__VID_MODE_STS__ERR_MISSING_HSYNC_MASK,
+ /** Data starvation at input of the VSG. */
+ DSITX_VID_STS_ERR_MISSING_DATA = DSITX__VID_MODE_STS__ERR_MISSING_DATA_MASK,
+ /** VSG is running (1) or stopped (0). */
+ DSITX_VID_STS_VSG_RUNNING = DSITX__VID_MODE_STS__VSG_RUNNING_MASK
+} DSITX_VidModeStatusBits;
+
+/** Status of the Test Video Generator module. */
+typedef enum
+{
+ /** Initial value. */
+ DSITX_TVG_STATUS_BITS_INIT = 0U,
+ /** Test Video generator is running. */
+ DSITX_TVG_STS_TVG_IS_RUNNING = DSITX__TVG_STS__TVG_RUNNING_MASK
+} DSITX_TvgStatusBits;
+
+/** Status of the DPHY - errors detected by DPHY. */
+typedef enum
+{
+ /** Initial value. */
+ DSITX_DPHY_ERROR_BITS_INIT = 0U,
+ DSITX_DPHY_STS_ERR_CONT_LP1_4 = DSITX__MCTL_DPHY_ERR__ERR_CONT_LP1_4_MASK,
+ DSITX_DPHY_STS_ERR_CONT_LP1_3 = DSITX__MCTL_DPHY_ERR__ERR_CONT_LP1_3_MASK,
+ DSITX_DPHY_STS_ERR_CONT_LP1_2 = DSITX__MCTL_DPHY_ERR__ERR_CONT_LP1_2_MASK,
+ DSITX_DPHY_STS_ERR_CONT_LP1_1 = DSITX__MCTL_DPHY_ERR__ERR_CONT_LP1_1_MASK,
+ DSITX_DPHY_STS_ERR_CONT_LP0_4 = DSITX__MCTL_DPHY_ERR__ERR_CONT_LP0_4_MASK,
+ DSITX_DPHY_STS_ERR_CONT_LP0_3 = DSITX__MCTL_DPHY_ERR__ERR_CONT_LP0_3_MASK,
+ DSITX_DPHY_STS_ERR_CONT_LP0_2 = DSITX__MCTL_DPHY_ERR__ERR_CONT_LP0_2_MASK,
+ DSITX_DPHY_STS_ERR_CONT_LP0_1 = DSITX__MCTL_DPHY_ERR__ERR_CONT_LP0_1_MASK,
+ DSITX_DPHY_STS_ERR_CONTROL_4 = DSITX__MCTL_DPHY_ERR__ERR_CONTROL_4_MASK,
+ DSITX_DPHY_STS_ERR_CONTROL_3 = DSITX__MCTL_DPHY_ERR__ERR_CONTROL_3_MASK,
+ DSITX_DPHY_STS_ERR_CONTROL_2 = DSITX__MCTL_DPHY_ERR__ERR_CONTROL_2_MASK,
+ DSITX_DPHY_STS_ERR_CONTROL_1 = DSITX__MCTL_DPHY_ERR__ERR_CONTROL_1_MASK,
+ DSITX_DPHY_STS_ERR_SYNCESC_4 = DSITX__MCTL_DPHY_ERR__ERR_SYNCESC_4_MASK,
+ DSITX_DPHY_STS_ERR_SYNCESC_3 = DSITX__MCTL_DPHY_ERR__ERR_SYNCESC_3_MASK,
+ DSITX_DPHY_STS_ERR_SYNCESC_2 = DSITX__MCTL_DPHY_ERR__ERR_SYNCESC_2_MASK,
+ DSITX_DPHY_STS_ERR_SYNCESC_1 = DSITX__MCTL_DPHY_ERR__ERR_SYNCESC_1_MASK,
+ DSITX_DPHY_STS_ERR_ESC_4 = DSITX__MCTL_DPHY_ERR__ERR_ESC_4_MASK,
+ DSITX_DPHY_STS_ERR_ESC_3 = DSITX__MCTL_DPHY_ERR__ERR_ESC_3_MASK,
+ DSITX_DPHY_STS_ERR_ESC_2 = DSITX__MCTL_DPHY_ERR__ERR_ESC_2_MASK,
+ DSITX_DPHY_STS_ERR_ESC_1 = DSITX__MCTL_DPHY_ERR__ERR_ESC_1_MASK
+} DSITX_DphyErrorBits;
+
+/** DPI Status Bits */
+typedef enum
+{
+ /** Initial value. */
+ DSITX_DPI_STATUS_BITS_INIT = 0U,
+ /** DPI FIFO Overflow. */
+ DSITX_DPI_STS_PIXEL_BUF_OVERFLOW = DSITX__DPI_IRQ_STS__PIXEL_BUF_OVERFLOW_STS_MASK
+} DSITX_DpiStatusBits;
+
+/** Status of the Direct Command Request. */
+typedef enum
+{
+ /** Initial value. */
+ DSITX_DIRECT_COMMAND_STATUS_BITS_INIT = 0U,
+ /** A command is being sent. */
+ DSITX_DCR_STS_TRANSMISSION = DSITX__DIRECT_CMD_STS__CMD_TRANSMISSION_MASK,
+ /** Write command request completed. */
+ DSITX_DCR_STS_WRITE_COMPLETED = DSITX__DIRECT_CMD_STS__WRITE_COMPLETED_MASK,
+ /** Trigger command request completed. */
+ DSITX_DCR_STS_TRIGGER_COMPLETED = DSITX__DIRECT_CMD_STS__TRIGGER_COMPLETED_MASK,
+ /** Read command request completed. */
+ DSITX_DCR_STS_READ_COMPLETED = DSITX__DIRECT_CMD_STS__READ_COMPLETED_MASK,
+ /** Acknowledge with no error has been received in case of command with BTA. */
+ DSITX_DCR_STS_ACK_RECEIVED = DSITX__DIRECT_CMD_STS__ACK_RECEIVED_MASK,
+ /** Acknowledge with error has been received in case of command with BTA. */
+ DSITX_DCR_STS_ACK_WITH_ERR_RECEIVED = DSITX__DIRECT_CMD_STS__ACK_WITH_ERR_RECEIVED_MASK,
+ /** Trigger has been received in case of command with BTA. */
+ DSITX_DCR_STS_TRIGGER_RECEIVED = DSITX__DIRECT_CMD_STS__TRIGGER_RECEIVED_MASK,
+ /** TE has been received in case of command with BTA. */
+ DSITX_DCR_STS_TE_RECEIVED = DSITX__DIRECT_CMD_STS__TE_RECEIVED_MASK,
+ /** BTA request completed. */
+ DSITX_DCR_STS_BTA_COMPLETED = DSITX__DIRECT_CMD_STS__BTA_COMPLETED_MASK,
+ /** DSITX Link recovered link mastership after a BTA request. */
+ DSITX_DCR_STS_BTA_FINISHED = DSITX__DIRECT_CMD_STS__BTA_FINISHED_MASK,
+ /** Read command terminated with error. */
+ DSITX_DCR_STS_READ_COMPLETED_WITH_ERR = DSITX__DIRECT_CMD_STS__READ_COMPLETED_WITH_ERR_MASK
+} DSITX_DirectCommandStatusBits;
+
+/** Status of the Direct Command read Request. */
+typedef enum
+{
+ /** Initial value. */
+ DSITX_DIRECT_COMMAND_READ_STATUS_BITS_INIT = 0U,
+ /** One error detected and fixed by ECC. */
+ DSITX_DCR_RD_STS_ERR_FIXED = DSITX__DIRECT_CMD_RD_STS__ERR_FIXED_MASK,
+ /** More than 1 error detected by ECC. */
+ DSITX_DCR_RD_STS_ERR_UNCORRECTABLE = DSITX__DIRECT_CMD_RD_STS__ERR_UNCORRECTABLE_MASK,
+ /** Error(s) detected by checksum. */
+ DSITX_DCR_RD_STS_ERR_CHECKSUM = DSITX__DIRECT_CMD_RD_STS__ERR_CHECKSUM_MASK,
+ /** Command opcode not understood. */
+ DSITX_DCR_RD_STS_ERR_UNDECODABLE = DSITX__DIRECT_CMD_RD_STS__ERR_UNDECODABLE_MASK,
+ /** Receive packet not complete. */
+ DSITX_DCR_RD_STS_ERR_RECEIVE = DSITX__DIRECT_CMD_RD_STS__ERR_RECEIVE_MASK,
+ /** Packet size exceeds maximum. */
+ DSITX_DCR_RD_STS_ERR_OVERSIZE = DSITX__DIRECT_CMD_RD_STS__ERR_OVERSIZE_MASK,
+ /** Length error has been detected. */
+ DSITX_DCR_RD_STS_ERR_WRONG_LENGTH = DSITX__DIRECT_CMD_RD_STS__ERR_WRONG_LENGTH_MASK,
+ /** EOT requested but not received. */
+ DSITX_DCR_RD_STS_ERR_MISSING_EOT = DSITX__DIRECT_CMD_RD_STS__ERR_MISSING_EOT_MASK,
+ /** EOT received with error. */
+ DSITX_DCR_RD_STS_ERR_EOT_WITH_ERR = DSITX__DIRECT_CMD_RD_STS__ERR_EOT_WITH_ERR_MASK
+} DSITX_DirectCommandReadStatusBits;
+
+/** SDI Interface mode. */
+typedef enum
+{
+ /** Command Mode. */
+ DSITX_IF_MODE_COMMAND = 0U,
+ /** Video Mode. */
+ DSITX_IF_MODE_VIDEO = 1U
+} DSITX_InterfaceMode;
+
+/** Video Interface selections. */
+typedef enum
+{
+ /** Interface SDI. */
+ DSITX_VID_IF_SELECT_IF1 = 0U,
+ /** Interface DPI. */
+ DSITX_VID_IF_SELECT_IF2 = 1U,
+ /** Interface DSC. */
+ DSITX_VID_IF_SELECT_IF3 = 2U
+} DSITX_VideoInterfaceSelection;
+
+/** Direct Command Request event handler response. */
+typedef enum
+{
+ /**
+ * Finish processing request. After returning this value Core Driver
+ * will complete processing request and another request may be sent.
+ * This value shall be returned if status bits indicate that request
+ * was completed and user wants to send another.
+ */
+ DSITX_DCR_RESULT_FINISHED = 0U,
+ /**
+ * Continue processing request. After returning this value Core Driver
+ * will continue to process request and another event may occur.
+ * In most cases this value shall be returned in response to
+ * DCR_STS_TRANSMISSION event and if any status bits indicating
+ * that request is completed were not set.
+ */
+ DSITX_DCR_RESULT_CONTINUE = 1U,
+ /**
+ * Finish processing request and report error. After returning this
+ * value Core Driver will complete processing request and another
+ * request may be sent.
+ * This value shall be returned if status bits indicate that request
+ * was completed and user wants to send another.
+ */
+ DSITX_DCR_RESULT_FINISHED_ERR = 2U
+} DSITX_DirectCommandEventHandlerResponse;
+
+/** PLL's High Speed input type. */
+typedef enum
+{
+ /** Command Mode. */
+ DSITX_PLL_OUT_SEL_SYSTEM = 0U,
+ /** Video Mode. */
+ DSITX_PLL_OUT_SEL_DSI = 1U
+} DSITX_LinkPllOutSel;
+
+/** Type of the Direct Command. */
+typedef enum
+{
+ /** Write command. */
+ DSITX_DCR_TYPE_WRITE = 0U,
+ /** Read command. */
+ DSITX_DCR_TYPE_READ = 1U,
+ /** Tearing Effect command. */
+ DSITX_DCR_TYPE_TE = 4U,
+ /** Trigger Command. */
+ DSITX_DCR_TYPE_TRIGGER = 5U,
+ /** Bus Turn Around command. */
+ DSITX_DCR_TYPE_BTA = 6U
+} DSITX_DirectCommandType;
+
+/** Type of the Trigger value. */
+typedef enum
+{
+ /** Reset (in TX direction). */
+ DSITX_DCR_TRIGGER_VALUE_RESET = 0x01U
+} DSITX_DirectCommandTriggerType;
+
+/** Lane state */
+typedef enum
+{
+ /** Lane is in a Start state. */
+ DSITX_LANE_STATE_START = 0U,
+ /** Lane is in a Idle state. */
+ DSITX_LANE_STATE_IDLE = 1U,
+ /** Lane is in a Write state. */
+ DSITX_LANE_STATE_WRITE = 2U,
+ /** Lane is in a ULPM state. */
+ DSITX_LANE_STATE_ULMP = 3U,
+ /** Lane is in a Read state. This is state is valid only for Data Lane 1. */
+ DSITX_LANE_STATE_READ = 4U
+} DSITX_LaneState;
+
+/** Test Video Generator Display Mode. */
+typedef enum
+{
+ /** Single color. */
+ DSITX_TVG_MODE_SINGLE_COLOR = 0U,
+ /** Vertical stripes. */
+ DSITX_TVG_MODE_VERTICAL_STRIPES = 2U,
+ /** Horizontal stripes. */
+ DSITX_TVG_MODE_HORIZONTAL_STRIPES = 3U
+} DSITX_TvgDisplayMode;
+
+/** Test Video Generator Stop Mode. */
+typedef enum
+{
+ /** Stop at the end of frame. */
+ DSITX_TVG_STOP_MODE_AT_END_OF_FRAME = 0U,
+ /** Stop at the end of line. */
+ DSITX_TVG_STOP_MODE_AT_END_OF_LINE = 1U,
+ /** Stop immediate. */
+ DSITX_TVG_STOP_MODE_IMMEDIATE = 2U
+} DSITX_TvgStopMode;
+
+/** Test Video Generator stripe size. */
+typedef enum
+{
+ /** 1 pixel. */
+ DSITX_TVG_STRIPE_SIZE_1 = 0U,
+ /** 2 pixels. */
+ DSITX_TVG_STRIPE_SIZE_2 = 1U,
+ /** 4 pixels. */
+ DSITX_TVG_STRIPE_SIZE_4 = 2U,
+ /** 8 pixels. */
+ DSITX_TVG_STRIPE_SIZE_8 = 3U,
+ /** 16 pixels. */
+ DSITX_TVG_STRIPE_SIZE_16 = 4U,
+ /** 32 pixels. */
+ DSITX_TVG_STRIPE_SIZE_32 = 5U,
+ /** 64 pixels. */
+ DSITX_TVG_STRIPE_SIZE_64 = 6U,
+ /** 128 pixels. */
+ DSITX_TVG_STRIPE_SIZE_128 = 7U
+} DSITX_TvgStripeSize;
+
+/** Video3dMode */
+typedef enum
+{
+ /** 3D off 2D mode only. */
+ DSITX_VIDEO_MODE_2D = 0U,
+ /** 3D on Portrait Orientation. */
+ DSITX_VIDEO_MODE_PORTRAIT = 1U,
+ /** 3D on Landscape orientation. */
+ DSITX_VIDEO_MODE_LANDSCAPE = 2U
+} DSITX_Video3dMode;
+
+/** Video3dFormat */
+typedef enum
+{
+ /** Line Format alternating line of left and right data. */
+ DSITX_VIDEO_FORMAT_LINE = 0U,
+ /** Frame Format alternating frames of left and right data. */
+ DSITX_VIDEO_FORMAT_FRAME = 1U,
+ /** Pixel Format alternating frames of left and right data. */
+ DSITX_VIDEO_FORMAT_PIXEL = 2U
+} DSITX_Video3dFormat;
+
+/** Video3dFirstSide */
+typedef enum
+{
+ /** Data is sent left first then right. */
+ DSITX_VIDEO_START_LEFT = 0U,
+ /** Data is sent right first then left. */
+ DSITX_VIDEO_START_RIGHT = 1U
+} DSITX_Video3dFirstSide;
+
+/** Arbitration priority */
+typedef enum
+{
+ /** Initial value. */
+ DSITX_CMD_ARB_PRIORITY_INIT = 0U,
+ /** SDI interface has higher priority. */
+ DSITX_CMD_ARB_PRIORITY_SDI = 1U,
+ /** DSC interface has higher priority. */
+ DSITX_CMD_ARB_PRIORITY_DSC = 2U
+} DSITX_CmdArbitrationPriority;
+
+/** Arbitration mode type */
+typedef enum
+{
+ /** Fixed Mode. */
+ DSITX_CMD_ARBITRATION_MODE_FIXED = 0U,
+ /** Round Robin Mode. */
+ DSITX_CMD_ARBITRATION_MODE_ROUND_ROBIN = 1U
+} DSITX_CmdArbitrationMode;
+
+/** Video Pixel Modes */
+typedef enum
+{
+ /** 16-bit RGB */
+ DSITX_VID_PIXEL_MODE_RGB_16 = 0U,
+ /** 18-bit RGB */
+ DSITX_VID_PIXEL_MODE_RGB_18 = 1U,
+ /** 18-bit RGB loosely packed */
+ DSITX_VID_PIXEL_MODE_RGB_18_LOOSELY = 2U,
+ /** 24-bit RGB */
+ DSITX_VID_PIXEL_MODE_RGB_24 = 3U,
+ /** 30-bit RGB */
+ DSITX_VID_PIXEL_MODE_RGB_30 = 4U,
+ /** 36-bit RGB */
+ DSITX_VID_PIXEL_MODE_RGB_36 = 5U,
+ /** 12-bit YCbCr */
+ DSITX_VID_PIXEL_MODE_YCBCR_12 = 8U,
+ /** 16-bit YCbCr */
+ DSITX_VID_PIXEL_MODE_YCBCR_16 = 9U,
+ /** 20-bit YCbCr */
+ DSITX_VID_PIXEL_MODE_YCBCR_20 = 10U,
+ /** 24-bit YCbCr */
+ DSITX_VID_PIXEL_MODE_YCBCR_24 = 11U
+} DSITX_VideoPixelMode;
+
+/** Video Data Types */
+typedef enum
+{
+ /** Default value */
+ DSITX_VID_DATA_TYPE_DEFAULT = 0x0U,
+ /** Loosely Packed Pixel Stream 20-bit YCbCr 4_2_2 */
+ DSITX_VID_DATA_TYPE_YCBCR_20 = 0x0CU,
+ /** Packed Pixel Stream 24-bit YCbCr 4_2_2 */
+ DSITX_VID_DATA_TYPE_YCBCR_24 = 0x1CU,
+ /** Packed Pixel Stream 16-bit YCbCr 4_2_2 */
+ DSITX_VID_DATA_TYPE_YCBCR_16 = 0x2CU,
+ /** Packed Pixel Stream 30-bit RGB 10-10-10 */
+ DSITX_VID_DATA_TYPE_RGB_30 = 0x0DU,
+ /** Packed Pixel Stream 36-bit RGB 12-12-12 */
+ DSITX_VID_DATA_TYPE_RGB_36 = 0x1DU,
+ /** Packed Pixel Stream 12-bit YCbCr 4_2_0 */
+ DSITX_VID_DATA_TYPE_YCBCR_12 = 0x3DU,
+ /** Packed Pixel Stream 16-bit RGB 5-6-5 */
+ DSITX_VID_DATA_TYPE_RGB_16 = 0x0EU,
+ /** Packed Pixel Stream 18-bit RGB 6-6-6 */
+ DSITX_VID_DATA_TYPE_RGB_18 = 0x1EU,
+ /** Loosely Packed Pixel Stream 18-bit RGB 6-6-6 */
+ DSITX_VID_DATA_TYPE_RGB_18_LOOSELY = 0x2EU,
+ /** Packed Pixel Stream 24-bit RGB 8-8-8 */
+ DSITX_VID_DATA_TYPE_RGB_24 = 0x3EU
+} DSITX_VideoDataType;
+
+/** Type of video recovery modes. */
+typedef enum
+{
+ /** Continue with dummy packets till next HSYNC. */
+ DSITX_CONTINUE_TILL_NEXT_HSYNC = 0U,
+ /** Continue until next stop point (according to stop mode) */
+ DSITX_CONTINUE_UNTIL_NEXT_STOP_POINT = 2U,
+ /** Continue with dummy packets until next VSYNC. */
+ DSITX_CONTINUE_TILL_NEXT_VSYNC = 3U
+} DSITX_VideoRecoveryMode;
+
+/** Video start mode. */
+typedef enum
+{
+ /** The stream starts on the VSYNC packet. */
+ DSITX_VID_START_MODE_START_ON_VSYNC = 0U
+} DSITX_VideoStartMode;
+
+/** Video stop mode. */
+typedef enum
+{
+ /** Initial value. */
+ DSITX_VID_STOP_MODE_STOP_INIT = 0U,
+ /** Stop just before VSYNC. */
+ DSITX_VID_STOP_MODE_STOP_JUST_BEFORE_VSYNC = 1U
+} DSITX_VideoStopMode;
+
+/** Video blanking mode during blanking time or end of line in burst mode. */
+typedef enum
+{
+ /** NULL packet. */
+ DSITX_VID_BLK_MODE_NULL_PACKET = 0U,
+ /** Blanking packet. */
+ DSITX_VID_BLK_MODE_BLANKING_PACKET = 1U,
+ /** LP. */
+ DSITX_VID_BLK_MODE_LP = 2U
+} DSITX_VideoBlankingMode;
+
+/**********************************************************************
+ * Callbacks
+ **********************************************************************/
+/**
+ * DSITX Link event handler type.
+ * This event is raised when status of the DSITX Link changes and if
+ * corresponding interrupts are enabled.
+*/
+typedef void (*DSITX_DsiLinkEventHandler)(DSITX_PrivateData* pD, uint32_t status);
+
+/**
+ * Command Mode event handler type.
+ * This event is raised when status of the Command Mode changes and if
+ * corresponding interrupts are enabled.
+*/
+typedef void (*DSITX_CmdModeEventHandler)(DSITX_PrivateData* pD, uint32_t status);
+
+/**
+ * Video Mode event handler type.
+ * This event is raised when status of the Video Mode changes and if
+ * corresponding interrupts are enabled.
+*/
+typedef void (*DSITX_VidModeEventHandler)(DSITX_PrivateData* pD, uint32_t status);
+
+/**
+ * Test Video Generator event handler type.
+ * This event is raised when status of the Test Video Generator changes
+ * and if corresponding interrupts are enabled.
+*/
+typedef void (*DSITX_TvgEventHandler)(DSITX_PrivateData* pD, uint32_t status);
+
+/**
+ * DPHY error event handler type.
+ * This event is raised when errors in DPHY are detected
+ * and if corresponding interrupts are enabled.
+*/
+typedef void (*DSITX_DphyErrorEventHandler)(DSITX_PrivateData* pD, uint32_t status);
+
+/**
+ * DPI event handler type.
+ * This event is raised when enabled DPI interrupt occurs.
+*/
+typedef void (*DSITX_DpiEventHandler)(DSITX_PrivateData* pD, uint32_t status);
+
+/**
+ * Direct Command event handler type.
+ * This event is raised if status of the Direct Command Request changes
+ * and if corresponding interrupts are enabled.
+*/
+typedef DSITX_DirectCommandEventHandlerResponse (*DSITX_DirectCmdEventHandler)(DSITX_PrivateData* pD, DSITX_DirectCommandRequest* dcr);
+
+/** Display configuration handler type. */
+typedef uint32_t (*DSITX_InitializeDisplayHandler)(DSITX_PrivateData* pD);
+
+/**
+ * @}
+ */
+
+/** @defgroup DriverFunctionAPI Driver Function API
+ * Prototypes for the driver API functions. The user application can link statically to the
+ * necessary API functions and call them directly.
+ * @{
+ */
+
+/**********************************************************************
+ * API methods
+ **********************************************************************/
+
+/**
+ * Obtains the driver's memory requirements to support the given
+ * configuration.
+ * @param[in] config Proposed driver/hardware configuration.
+ * @param[out] sysReq Returns the memory requirements for given configuration in field privDataSize.
+ * @return EOK On success (requirements struct filled).
+ * @return EINVAL If config contains invalid values or not supported configuration.
+ */
+uint32_t DSITX_Probe(const DSITX_Config* config, DSITX_SysReq* sysReq);
+
+/**
+ * Initializes the Driver and the DSITX Host as specified in the
+ * config structure.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] config Specifies driver/hardware configuration.
+ * @return EOK On success
+ * @return EINVAL If illegal/inconsistent values in 'config' doesn't support feature(s) required by 'config' parameters.
+ */
+uint32_t DSITX_Init(DSITX_PrivateData* pD, const DSITX_Config* config);
+
+/**
+ * Driver ISR. Platform-specific code is responsible for ensuring this
+ * gets called when the corresponding hardware's interrupt is
+ * asserted. Registering the ISR should be done after calling init,
+ * and before calling start. The driver's ISR will not attempt to lock
+ * any locks, but will perform client callbacks. If the client wishes
+ * to defer processing to non-interrupt time, it is responsible for
+ * doing so. This function must not be called after calling destroy
+ * and releasing private data memory.
+ * @param[in] pD Driver instance data filled by init.
+ */
+void DSITX_Isr(DSITX_PrivateData* pD);
+
+/**
+ * Start the DSITX driver, enabling interrupts. This is called after
+ * the client has successfully initialized the driver and hooked the
+ * driver's ISR (the isr member of this struct) to the IRQ.
+ * @param[in] pD Driver state info specific to this instance.
+ */
+void DSITX_Start(DSITX_PrivateData* pD);
+
+/**
+ * Stops the DSITX driver by disabling interrupts.
+ * @param[in] pD Driver state info specific to this instance.
+ */
+void DSITX_Stop(DSITX_PrivateData* pD);
+
+/**
+ * Destroy the driver (automatically performs a stop).
+ * @param[in] pD Driver instance data
+ */
+void DSITX_Destroy(DSITX_PrivateData* pD);
+
+/**
+ * Sets DPHY configuration.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] config Pointer to structure which specifies DPHY configuration.
+ * @return EINVAL If pD or config is NULL.
+ * @return EOK If configuration is successfully set.
+ */
+uint32_t DSITX_SetDphyConfig(const DSITX_PrivateData* pD, const DSITX_DphyConfig* config);
+
+/**
+ * Obtains DPHY configuration.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] config Pointer to structure to which DPHY configuration will be written.
+ * @return EINVAL If pD or config is NULL.
+ * @return EOK If configuration is successfully obtained.
+ */
+uint32_t DSITX_GetDphyConfig(DSITX_PrivateData* pD, DSITX_DphyConfig* config);
+
+/**
+ * Sets Data Path configuration.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] config Pointer to structure containing Data Path configuration.
+ * @return EINVAL If pD or config is NULL.
+ * @return EOK If configuration is successfully set.
+ */
+uint32_t DSITX_SetDataPathConfig(DSITX_PrivateData* pD, const DSITX_DataPathConfig* config);
+
+/**
+ * Obtains Data Path configuration.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] config Pointer to structure to which Data Path configuration will be written.
+ * @return EINVAL If pD or config is NULL.
+ * @return EOK If configuration is successfully obtained.
+ */
+uint32_t DSITX_GetDataPathConfig(DSITX_PrivateData* pD, DSITX_DataPathConfig* config);
+
+/**
+ * Sets PHY main configuration.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] config Pointer to structure containing PHY configuration.
+ * @return EINVAL If pD or config is NULL.
+ * @return EOK If configuration is successfully set.
+ */
+uint32_t DSITX_SetPhyConfig(DSITX_PrivateData* pD, const DSITX_PhyConfig* config);
+
+/**
+ * Obtains PHY configuration.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] config Pointer to structure to which PHY configuration will be written.
+ * @return EINVAL If pD or config is NULL.
+ * @return EOK If configuration is successfully obtained.
+ */
+uint32_t DSITX_GetPhyConfig(DSITX_PrivateData* pD, DSITX_PhyConfig* config);
+
+/**
+ * Sets the DPHY Power and Reset Control configuration.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] cfg Pointer to structure containing configuration.
+ * @return EINVAL If pD or cfg is NULL.
+ * @return EOK On success.
+ */
+uint32_t DSITX_SetDphyPwrAndRstCtrl(DSITX_PrivateData* pD, const DSITX_DphyPwrRstConfig* cfg);
+
+/**
+ * Obtains the DPHY Power and Reset Control configuration.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] cfg Pointer to structure to which DPHY Power and Reset Control
+ * configuration will be written.
+ * @return EINVAL If pD or cfg is NULL.
+ * @return EOK On success.
+ */
+uint32_t DSITX_GetDphyPwrAndRstCtrl(DSITX_PrivateData* pD, DSITX_DphyPwrRstConfig* cfg);
+
+/**
+ * Sets DSITX Link configuration.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] config Pointer to structure containing DSITX Link configuration.
+ * @return EINVAL If pD or config is NULL.
+ * @return EOK If configuration is successfully set.
+ */
+uint32_t DSITX_SetDsiLinkConfig(DSITX_PrivateData* pD, const DSITX_DsiLinkConfig* config);
+
+/**
+ * Obtains DSITX Link configuration.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] config Pointer to structure to which DSITX Link setup will be stored.
+ * @return EINVAL If pD or config is NULL.
+ * @return EOK If configuration is successfully obtained.
+ */
+uint32_t DSITX_GetDsiLinkConfig(DSITX_PrivateData* pD, DSITX_DsiLinkConfig* config);
+
+/**
+ * Obtains IP configuration.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] config Pointer to structure to which DSITX IP configuration will be stored.
+ * @return EINVAL If pD or config is NULL.
+ * @return EOK If configuration is successfully obtained.
+ */
+uint32_t DSITX_GetIpConf(DSITX_PrivateData* pD, DSITX_IpConf* config);
+
+/**
+ * Reads information about DSITX version.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] id Pointer to structure where DSITX version information will be stored.
+ * @return EINVAL If pD or id is NULL.
+ * @return EOK If information is successfully obtained.
+ */
+uint32_t DSITX_GetHwIdAndVersion(DSITX_PrivateData* pD, DSITX_HwIdAndVersion* id);
+
+/**
+ * Sets Command Mode configuration.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] cmdMode Pointer to structure containing detailed information about
+ * Command Mode configuration.
+ * @return EINVAL If cmdMode contains invalid values.
+ * @return EOK On success.
+ */
+uint32_t DSITX_SetCommandMode(DSITX_PrivateData* pD, const DSITX_CommandModeSettings* cmdMode);
+
+/**
+ * Reads Command Mode configuration.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] cmdMode Pointer to structure to which detailed information about
+ * Command Mode configuration will be written.
+ * @return EINVAL If pD or cmdMode is NULL.
+ * @return EOK On success.
+ */
+uint32_t DSITX_GetCommandMode(DSITX_PrivateData* pD, DSITX_CommandModeSettings* cmdMode);
+
+/**
+ * Sets Video Mode configuration.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] vidMode Pointer to structure containing Video Mode configuration.
+ * @return EINVAL If provided configuration contains invalid values.
+ * @return EOK If configuration is successfully set.
+ */
+uint32_t DSITX_SetVideoMode(const DSITX_PrivateData* pD, const DSITX_VideoModeSettings* vidMode);
+
+/**
+ * Reads Video Mode configuration.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] vidMode Pointer to structure to which Video Mode configuration will be written.
+ * @return EINVAL If pD or vidMode is NULL.
+ * @return EOK If configuration was successfully read.
+ */
+uint32_t DSITX_GetVideoMode(const DSITX_PrivateData* pD, DSITX_VideoModeSettings* vidMode);
+
+/**
+ * Sets Video Command Arbiter configuration.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] vca Pointer to structure containing Video Command Arbiter configuration.
+ * @return EINVAL If provided configuration contains invalid values.
+ * @return EOK If configuration is successfully set.
+ */
+uint32_t DSITX_SetVcaConfig(DSITX_PrivateData* pD, const DSITX_VcaConfig* vca);
+
+/**
+ * Reads Video Command Arbiter configuration.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] vca Pointer to structure to which Video Command Arbiter configuration will be written.
+ * @return EINVAL If pD or vca is NULL.
+ * @return EOK If size is successfully set.
+ */
+uint32_t DSITX_GetVcaConfig(DSITX_PrivateData* pD, DSITX_VcaConfig* vca);
+
+/**
+ * Sets Video size configuration.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] vidSize Pointer to structure containing Video Size configuration.
+ * @return EINVAL If provided configuration contains invalid values.
+ * @return EOK If configuration is successfully set.
+ */
+uint32_t DSITX_SetVideoSize(DSITX_PrivateData* pD, const DSITX_VideoSize* vidSize);
+
+/**
+ * Reads Video size configuration.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] vidSize Pointer to structure to which Video Size configuration will be written.
+ * @return EINVAL If pD or vidSize is NULL.
+ * @return EOK If size is successfully set.
+ */
+uint32_t DSITX_GetVideoSize(DSITX_PrivateData* pD, DSITX_VideoSize* vidSize);
+
+/**
+ * Configures Test Video Generator using provided configuration. This
+ * function ignores value of 'enabled' field in config structure. New
+ * configuration can be applied only if Test Video Generator is not
+ * running.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] config Pointer to structure containing Test Video Generator configuration.
+ * Value of the enabled field is ignored. Use startTvg function to enable TVG.
+ * @return EINVAL If provided configuration contains invalid values.
+ * @return EPERM If Test Video Generator is enabled.
+ * @return EOK If Test Video Generator was successfully started.
+ */
+uint32_t DSITX_SetTvgConfig(const DSITX_PrivateData* pD, const DSITX_TestVideoModeConfig* config);
+
+/**
+ * Reads Test Video Generator configuration.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] config Pointer to structure to which received Test Video Generator
+ * configuration will be written.
+ * @return EINVAL If pD or config is NULL.
+ * @return EOK If Test Video Generator configuration was successfully read.
+ */
+uint32_t DSITX_GetTvgConfig(DSITX_PrivateData* pD, DSITX_TestVideoModeConfig* config);
+
+/**
+ * Enables Test Video Generator.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] wait Determines if function will wait until Test Video Generator is started
+ * (true) or will exit immediately (false) and raise TVG Event (if enabled)
+ * when TVG starts.
+ * @return EINVAL If pD is NULL.
+ * @return EIO On timeout.
+ * @return EOK If operation was successful.
+ */
+uint32_t DSITX_StartTvg(DSITX_PrivateData* pD, bool wait);
+
+/**
+ * Stops Test Video Generator. If stop mode is 'stop immediate' then
+ * the VSG needs to be stopped and video system restarted.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] wait Determines if function will wait until Test Video Generator is in
+ * stopped state (true) or will exit immediately (false).
+ * @return EINVAL If pD is NULL.
+ * @return EPERM If TVG stop mode is set to 'stop immediate'.
+ * @return EIO On timeout.
+ * @return EOK If operation was successful.
+ */
+uint32_t DSITX_StopTvg(DSITX_PrivateData* pD, bool wait);
+
+/**
+ * Sends Direct Command Request. Only one request can be sent at a
+ * time. After sending command request user shall not make changes to
+ * request structure unless request structure is provided to user in
+ * the callback function.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] dcr Pointer to structure containing detailed information about command.
+ * This structure will be updated by Core Driver during command
+ * execution. After passing it to Core Driver user shall not make
+ * any changes to its content until dcr status is set to completed
+ * or it is presented in callback function.
+ * @return EINVAL If pD NULL.
+ * @return EPERM If dcr cannot be sent due to state of the DSITX link (e.g. TVG enabled).
+ * @return EINPROGRESS If processing of other request has not yet been completed.
+ * @return EOK If Direct Command is accepted and pending execution.
+ */
+uint32_t DSITX_SendDirectCmd(DSITX_PrivateData* pD, DSITX_DirectCommandRequest* dcr);
+
+/**
+ * Sets DSITX Link Event Handler function and informs Core Driver
+ * which events should be reported to user.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] enabledEvents Specifies which DSITX Link events should be reported by Core Driver.
+ * @param[in] callback Pointer to function that will be called when event occurs.
+ * When value of this pointer is set to NULL then all events for
+ * DSITX Link will be disabled and value of the events argument is ignored.
+ */
+uint32_t DSITX_SetDsiLinkEventHandler(DSITX_PrivateData* pD, uint32_t enabledEvents, DSITX_DsiLinkEventHandler callback);
+
+/**
+ * Sets Command Mode Event Handler function and informs Core Driver
+ * which events should be reported to user.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] enabledEvents Specifies which Command Mode events should be reported by Core Driver.
+ * @param[in] callback Pointer to function that will be called when Command Mode event occurs.
+ * When value of this pointer is set to NULL then all events for
+ * Command Mode will be disabled and value of the events argument is ignored.
+ * @return EINVAL If pD is NULL.
+ * @return EOK If Direct Command is accepted and pending execution.
+ */
+uint32_t DSITX_SetCmdModeEventHandler(DSITX_PrivateData* pD, uint32_t enabledEvents, DSITX_CmdModeEventHandler callback);
+
+/**
+ * Sets Video Mode Event Handler function and informs Core Driver
+ * which events should be reported to user.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] enabledEvents Specifies which Video Mode events should be reported by Core Driver.
+ * @param[in] callback Pointer to function that will be called when Video Mode event occurs.
+ * When value of this pointer is set to NULL then all events for
+ * Video Mode will be disabled and value of the events argument is ignored.
+ * @return EINVAL If pD is NULL.
+ * @return EOK If Direct Command is accepted and pending execution.
+ */
+uint32_t DSITX_SetVidModeEventHandler(DSITX_PrivateData* pD, uint32_t enabledEvents, DSITX_VidModeEventHandler callback);
+
+/**
+ * Sets Test Video Generator Event Handler function and informs Core
+ * Driver which events should be reported to the user.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] enabledEvents Specifies which Test Video Generator events should be reported by Core Driver.
+ * @param[in] callback Pointer to function that will be called when Test Video Generator event occurs.
+ * When value of this pointer is set to NULL then all events for
+ * Test Video Generator will be disabled and value of events argument is ignored.
+ * @return EINVAL If pD is NULL.
+ * @return EOK If Direct Command is accepted and pending execution.
+ */
+uint32_t DSITX_SetTvgEventHandler(DSITX_PrivateData* pD, uint32_t enabledEvents, DSITX_TvgEventHandler callback);
+
+/**
+ * Sets DPHY Error Event Handler function and informs Core Driver
+ * which events should be reported to user.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] enabledEvents Specifies which DPHY errors should be reported by Core Driver.
+ * @param[in] callback Pointer to function that will be called when DPHY error occurs.
+ * When value of this pointer is set to NULL then all error events for
+ * DPHY will be disabled and value of the events argument is ignored.
+ * @return EINVAL If pD is NULL.
+ * @return EOK If Direct Command is accepted and pending execution.
+ */
+uint32_t DSITX_SetDphyErrorEventHandler(DSITX_PrivateData* pD, uint32_t enabledEvents, DSITX_DphyErrorEventHandler callback);
+
+/**
+ * Sets DPI Event Handler function and informs Core Driver which
+ * events should be reported to user.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] enabledEvents Specifies which DPI events should be reported by Core Driver.
+ * @param[in] callback Pointer to function that will be called when DPI interrupt occurs.
+ * When value of this pointer is set to NULL then all events for DPI
+ * will be disabled and value of the events argument is ignored.
+ * @return EINVAL If pD is NULL.
+ * @return EOK If Direct Command is accepted and pending execution.
+ */
+uint32_t DSITX_SetDpiEventHandler(DSITX_PrivateData* pD, uint32_t enabledEvents, DSITX_DpiEventHandler callback);
+
+/**
+ * Sets DSITX Test register.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] test Pointer to structure containing control configuration.
+ * @return EINVAL If pD is NULL.
+ * @return EOK On success.
+ */
+uint32_t DSITX_SetTestGeneric(DSITX_PrivateData* pD, const DSITX_TestGeneric* test);
+
+/**
+ * Obtains DSITX Test register value.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] test Pointer to structure to which control configuration will be
+ * written.
+ * @return EINVAL If pD or test are NULL.
+ * @return EOK On success.
+ */
+uint32_t DSITX_GetTestGeneric(DSITX_PrivateData* pD, DSITX_TestGeneric* test);
+
+/**
+ * Sets Video 3D configuration.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] cfg Video 3D configuration.
+ * @return EINVAL If pD or value is NULL.
+ * @return EOK On success.
+ */
+uint32_t DSITX_SetVideo3dConfig(DSITX_PrivateData* pD, const DSITX_Video3dConfig* cfg);
+
+/**
+ * Gets Video 3D configuration.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] cfg Video 3D configuration.
+ * @return EINVAL If pD or value is NULL.
+ * @return EOK On success.
+ */
+uint32_t DSITX_GetVideo3dConfig(DSITX_PrivateData* pD, DSITX_Video3dConfig* cfg);
+
+/**
+ * Retrieves ASF information from DSITX controller.
+ * @param[in] pD Pointer to driver's private data object.
+ * @param[out] asfInfo Pointer to ASF information structure.
+ * @return EINVAL If pD or asfInfo is NULL.
+ * @return EOK On success.
+ */
+uint32_t DSITX_GetAsfInfo(const DSITX_PrivateData* pD, DSITX_AsfInfo* asfInfo);
+
+/**
+ * Checks if lanes are ready.
+ * @param[in] pD Pointer to driver's private data object.
+ * @param[in] repeatCount status checking repeat count
+ * @return EINVAL If pD is NULL.
+ * @return EIO If lanes are not ready.
+ * @return EOK On success.
+ */
+uint32_t DSITX_CheckLanesState(const DSITX_PrivateData* pD, uint32_t repeatCount);
+
+/**
+ * Waits for PLL lock event.
+ * @param[in] pD Pointer to driver's private data object.
+ * @param[in] repeatCount status checking repeat count
+ * @return EINVAL If pD is NULL.
+ * @return EIO If timeout occurs.
+ * @return EOK On success.
+ */
+uint32_t DSITX_WaitForPllLock(const DSITX_PrivateData* pD, uint32_t repeatCount);
+
+/**
+ * @}
+ */
+
+
+/* parasoft-end-suppress MISRA2012-RULE-1_1_b_c90-2 */
+/* parasoft-end-suppress MISRA2012-RULE-1_1_a_c90-2 */
+
+#endif /* DSITX_IF_H */
diff --git a/packages/ti/drv/dss/src/csl/dsi/include/dsitx_priv.h b/packages/ti/drv/dss/src/csl/dsi/include/dsitx_priv.h
--- /dev/null
@@ -0,0 +1,108 @@
+/**********************************************************************
+ * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ **********************************************************************
+ * WARNING: This file is auto-generated using api-generator utility.
+ * api-generator: 13.00.31660be
+ * Do not edit it manually.
+ **********************************************************************
+ * Cadence Core Driver for MIPI DSITX Host Controller
+ **********************************************************************/
+
+#ifndef DSITX_PRIV_H
+#define DSITX_PRIV_H
+
+/* parasoft-begin-suppress MISRA2012-RULE-1_1_a_c90-2 "C90 - limits, DRV-3906" */
+/* parasoft-begin-suppress MISRA2012-RULE-1_1_b_c90-2 "C90 - limits, DRV-3906" */
+/* parasoft suppress item MISRA2012-DIR-4_8 "Consider hiding implementation of structure" */
+
+#include "dsitx_structs_if.h"
+
+/** @defgroup DataStructure Dynamic Data Structures
+ * This section defines the data structures used by the driver to provide
+ * hardware information, modification and dynamic operation of the driver.
+ * These data structures are defined in the header file of the core driver
+ * and utilized by the API.
+ * @{
+ */
+
+
+/**********************************************************************
+ * Structures and unions
+ **********************************************************************/
+/** Driver private data */
+struct DSITX_PrivateData_s
+{
+ /** Base address for DSITX Host registers. */
+ struct DSITX_Regs_s* regBase;
+ /** Indicates if interrupt service routine is enabled. */
+ bool interruptsEnabled;
+ /** Indicates if DCR is currently processed. */
+ bool processingDcr;
+ /** Number of enabled data lanes. */
+ uint8_t numOfLanes;
+ /** IP configuration values. */
+ DSITX_IpConf ip;
+ /** Pointer to Direct Command Request. */
+ DSITX_DirectCommandRequest* dcr;
+ /** Pointer to DSITX Link Event handler. */
+ DSITX_DsiLinkEventHandler fnDsiLinkCallback;
+ /** Pointer to Command Mode Event handler. */
+ DSITX_CmdModeEventHandler fnCmdModeCallback;
+ /** Pointer to Video Mode Event handler. */
+ DSITX_VidModeEventHandler fnVidModeCallback;
+ /** Pointer to Test Video Generator Event handler. */
+ DSITX_TvgEventHandler fnTvgCallback;
+ /** Pointer to DPHY Error Event handler. */
+ DSITX_DphyErrorEventHandler fnDphyErrCallback;
+ /** Pointer to DPI Event handler. */
+ DSITX_DpiEventHandler fnDpiCallback;
+ /** Pointer to Direct Command Request Event handler. */
+ DSITX_DirectCmdEventHandler fnDcrEventCallback;
+ /** Pointer to Display initialization handler. */
+ DSITX_InitializeDisplayHandler fnInitDispCallback;
+ /** Set of DSITX Link enabled events. */
+ uint32_t enDsiLinkStsBits;
+ /** Set of Command Mode enabled events. */
+ uint32_t enCmdModeStsBits;
+ /** Set of Video Mode enabled events. */
+ uint32_t enVidModeStsBits;
+ /** Set of Test Video Generator enabled events. */
+ uint32_t enTvgStsBits;
+ /** Set of DPHY Error enabled events. */
+ uint32_t enDphyErrBits;
+ /** Set of DPI enabled events. */
+ uint32_t enDpiStsBits;
+};
+
+/**
+ * @}
+ */
+
+/* parasoft-end-suppress MISRA2012-RULE-1_1_b_c90-2 */
+/* parasoft-end-suppress MISRA2012-RULE-1_1_a_c90-2 */
+
+#endif /* DSITX_PRIV_H */
diff --git a/packages/ti/drv/dss/src/csl/dsi/include/dsitx_regs.h b/packages/ti/drv/dss/src/csl/dsi/include/dsitx_regs.h
--- /dev/null
@@ -0,0 +1,158 @@
+/* parasoft-begin-suppress MISRA2012-RULE-1_1_a_c99-2 "C99 - limits" parasoft-begin-suppress MISRA2012-RULE-1_1_a_c90-2 "C90 - limits" */
+/* parasoft-begin-suppress item MISRA2012-DIR-4_8 "Consider hiding implementation of structure, DRV-3667" */
+
+/**********************************************************************
+ * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * THIS FILE IS AUTOMATICALLY GENERATED, DO NOT EDIT
+ *
+ **********************************************************************/
+
+#ifndef REG_DSITX_REGS_H_
+#define REG_DSITX_REGS_H_
+
+#include <cps_drv.h>
+
+#include "dsitx_regs_macros.h"
+
+typedef struct __attribute__((packed)) DSITX_Regs_s {
+ volatile uint32_t ip_conf;
+ volatile uint32_t mctl_main_data_ctl;
+ volatile uint32_t mctl_main_phy_ctl;
+ volatile uint32_t mctl_main_en;
+ volatile uint32_t mctl_dphy_cfg0;
+ volatile uint32_t mctl_dphy_timeout1;
+ volatile uint32_t mctl_dphy_timeout2;
+ volatile uint32_t mctl_ulpout_time;
+ volatile uint32_t mctl_3dvideo_ctl;
+ volatile uint32_t mctl_main_sts;
+ volatile uint32_t mctl_dphy_err;
+ volatile uint32_t mctl_lane_sts;
+ volatile uint32_t dsc_mode_ctl;
+ volatile uint32_t dsc_cmd_send;
+ volatile uint32_t dsc_pps_wrdat;
+ volatile uint32_t dsc_mode_sts;
+ volatile uint32_t mctl_dphy_skewcal_timeout;
+ volatile char pad__0[0x2CU];
+ volatile uint32_t cmd_mode_ctl;
+ volatile uint32_t cmd_mode_ctl2;
+ volatile uint32_t cmd_mode_sts;
+ volatile char pad__1[0x4U];
+ volatile uint32_t direct_cmd_send;
+ volatile uint32_t direct_cmd_main_settings;
+ volatile uint32_t direct_cmd_sts;
+ volatile uint32_t direct_cmd_rd_init;
+ volatile uint32_t direct_cmd_wrdat;
+ volatile uint32_t direct_cmd_fifo_rst;
+ volatile char pad__2[0x8U];
+ volatile uint32_t direct_cmd_rddat;
+ volatile uint32_t direct_cmd_rd_property;
+ volatile uint32_t direct_cmd_rd_sts;
+ volatile char pad__3[0x4U];
+ volatile uint32_t vid_main_ctl;
+ volatile uint32_t vid_vsize1;
+ volatile uint32_t vid_vsize2;
+ volatile char pad__4[0x4U];
+ volatile uint32_t vid_hsize1;
+ volatile uint32_t vid_hsize2;
+ volatile char pad__5[0x4U];
+ volatile uint32_t vid_blksize1;
+ volatile uint32_t vid_blksize2;
+ volatile char pad__6[0x4U];
+ volatile uint32_t vid_pck_time;
+ volatile uint32_t vid_dphy_time;
+ volatile uint32_t vid_err_color1;
+ volatile uint32_t vid_err_color2;
+ volatile uint32_t vid_vpos;
+ volatile uint32_t vid_hpos;
+ volatile uint32_t vid_mode_sts;
+ volatile uint32_t vid_vca_setting1;
+ volatile uint32_t vid_vca_setting2;
+ volatile uint32_t tvg_ctl;
+ volatile uint32_t tvg_img_size;
+ volatile uint32_t tvg_color1;
+ volatile uint32_t tvg_color1_bis;
+ volatile uint32_t tvg_color2;
+ volatile uint32_t tvg_color2_bis;
+ volatile uint32_t tvg_sts;
+ volatile char pad__7[0x18U];
+ volatile uint32_t mctl_main_sts_ctl;
+ volatile uint32_t cmd_mode_sts_ctl;
+ volatile uint32_t direct_cmd_sts_ctl;
+ volatile uint32_t direct_cmd_rd_sts_ctl;
+ volatile uint32_t vid_mode_sts_ctl;
+ volatile uint32_t tvg_sts_ctl;
+ volatile uint32_t mctl_dphy_err_ctl1;
+ volatile uint32_t mctl_dphy_err_ctl2;
+ volatile uint32_t mctl_main_sts_clr;
+ volatile uint32_t cmd_mode_sts_clr;
+ volatile uint32_t direct_cmd_sts_clr;
+ volatile uint32_t direct_cmd_rd_sts_clr;
+ volatile uint32_t vid_mode_sts_clr;
+ volatile uint32_t tg_sts_clr;
+ volatile uint32_t mctl_dphy_err_clr;
+ volatile char pad__8[0x4U];
+ volatile uint32_t mctl_main_sts_flag;
+ volatile uint32_t cmd_mode_sts_flag;
+ volatile uint32_t direct_cmd_sts_flag;
+ volatile uint32_t direct_cmd_rd_sts_flag;
+ volatile uint32_t vid_mode_sts_flag;
+ volatile uint32_t tg_sts_flag;
+ volatile uint32_t mctl_dphy_err_flag;
+ volatile char pad__9[0x14U];
+ volatile uint32_t dpi_irq_en;
+ volatile uint32_t dpi_irq_clr;
+ volatile uint32_t dpi_irq_sts;
+ volatile uint32_t dpi_cfg;
+ volatile char pad__10[0x40U];
+ volatile uint32_t test_generic;
+ volatile char pad__11[0x8U];
+ volatile uint32_t id_reg;
+ volatile uint32_t asf_int_status;
+ volatile uint32_t asf_int_raw_status;
+ volatile uint32_t asf_int_mask;
+ volatile uint32_t asf_int_test;
+ volatile uint32_t asf_fatal_nonfatal_select;
+ volatile char pad__12[0xCU];
+ volatile uint32_t asf_sram_corr_fault_status;
+ volatile uint32_t asf_sram_uncorr_fault_status;
+ volatile uint32_t asf_sram_fault_stats;
+ volatile char pad__13[0x4U];
+ volatile uint32_t asf_trans_to_ctrl;
+ volatile uint32_t asf_trans_to_fault_mask;
+ volatile uint32_t asf_trans_to_fault_status;
+ volatile char pad__14[0x4U];
+ volatile uint32_t asf_protocol_fault_mask;
+ volatile uint32_t asf_protocol_fault_status;
+} DSITX_Regs;
+
+#endif /* REG_DSITX_REGS_H_ */
+
+/* parasoft-end-suppress MISRA2012-RULE-1_1_a_c99-2 "C99 - limits" */
+/* parasoft-end-suppress MISRA2012-RULE-1_1_a_c90-2 "C90 - limits" */
+/* parasoft-end-suppress MISRA2012-DIR-4_8 "Consider hiding implementation of structure, DRV-3667" */
+
diff --git a/packages/ti/drv/dss/src/csl/dsi/include/dsitx_regs_macros.h b/packages/ti/drv/dss/src/csl/dsi/include/dsitx_regs_macros.h
--- /dev/null
@@ -0,0 +1,3418 @@
+/* parasoft-begin-suppress MISRA2012-RULE-1_1_b_c99-2 "C99 - limits" parasoft-begin-suppress MISRA2012-RULE-1_1_b_c90-2 "C90 - limits" */
+/* parasoft-begin-suppress MISRA2012-RULE-5_4_b_c90-2 "C90 - similar names" */
+/* parasoft-begin-suppress MISRA2012-RULE-5_4_b_c99-2 "C99 - similar names" */
+
+/**********************************************************************
+ * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * THIS FILE IS AUTOMATICALLY GENERATED, DO NOT EDIT
+ *
+ **********************************************************************/
+
+#ifndef REG_DSITX_REGS_MACROS_H_
+#define REG_DSITX_REGS_MACROS_H_
+
+#define DSITX__IP_CONF_READ_MASK 0xFFFFFFFFU
+#define DSITX__IP_CONF_WRITE_MASK 0xFFFFFFFFU
+#define DSITX__IP_CONF__RX_FIFO_DEPTH_MASK 0x0000003FU
+#define DSITX__IP_CONF__RX_FIFO_DEPTH_SHIFT 0U
+#define DSITX__IP_CONF__RX_FIFO_DEPTH_WIDTH 6U
+#define DSITX__IP_CONF__MAX_LANE_NB_MASK 0x000000C0U
+#define DSITX__IP_CONF__MAX_LANE_NB_SHIFT 6U
+#define DSITX__IP_CONF__MAX_LANE_NB_WIDTH 2U
+#define DSITX__IP_CONF__NUM_INTERFACE_MASK 0x00000300U
+#define DSITX__IP_CONF__NUM_INTERFACE_SHIFT 8U
+#define DSITX__IP_CONF__NUM_INTERFACE_WIDTH 2U
+#define DSITX__IP_CONF__DATAPATH_SIZE_MASK 0x00000C00U
+#define DSITX__IP_CONF__DATAPATH_SIZE_SHIFT 10U
+#define DSITX__IP_CONF__DATAPATH_SIZE_WIDTH 2U
+#define DSITX__IP_CONF__INTERFACE_DATASIZE_MASK 0x00001000U
+#define DSITX__IP_CONF__INTERFACE_DATASIZE_SHIFT 12U
+#define DSITX__IP_CONF__INTERFACE_DATASIZE_WIDTH 1U
+#define DSITX__IP_CONF__INTERFACE_DATASIZE_WOCLR 0U
+#define DSITX__IP_CONF__INTERFACE_DATASIZE_WOSET 0U
+#define DSITX__IP_CONF__DIRCMD_FIFO_DEPTH_MASK 0x0000E000U
+#define DSITX__IP_CONF__DIRCMD_FIFO_DEPTH_SHIFT 13U
+#define DSITX__IP_CONF__DIRCMD_FIFO_DEPTH_WIDTH 3U
+#define DSITX__IP_CONF__VRS_FIFO_DEPTH_MASK 0x001F0000U
+#define DSITX__IP_CONF__VRS_FIFO_DEPTH_SHIFT 16U
+#define DSITX__IP_CONF__VRS_FIFO_DEPTH_WIDTH 5U
+#define DSITX__IP_CONF__SP_LP_FIFO_DEPTH_MASK 0x03E00000U
+#define DSITX__IP_CONF__SP_LP_FIFO_DEPTH_SHIFT 21U
+#define DSITX__IP_CONF__SP_LP_FIFO_DEPTH_WIDTH 5U
+#define DSITX__IP_CONF__SP_HS_FIFO_DEPTH_MASK 0x7C000000U
+#define DSITX__IP_CONF__SP_HS_FIFO_DEPTH_SHIFT 26U
+#define DSITX__IP_CONF__SP_HS_FIFO_DEPTH_WIDTH 5U
+#define DSITX__IP_CONF__ASF_CONFIG_MASK 0x80000000U
+#define DSITX__IP_CONF__ASF_CONFIG_SHIFT 31U
+#define DSITX__IP_CONF__ASF_CONFIG_WIDTH 1U
+#define DSITX__IP_CONF__ASF_CONFIG_WOCLR 0U
+#define DSITX__IP_CONF__ASF_CONFIG_WOSET 0U
+
+#define DSITX__MCTL_MAIN_DATA_CTL_READ_MASK 0xFFFFFFFFU
+#define DSITX__MCTL_MAIN_DATA_CTL_WRITE_MASK 0xFFFFFFFFU
+#define DSITX__MCTL_MAIN_DATA_CTL__LINK_EN_MASK 0x00000001U
+#define DSITX__MCTL_MAIN_DATA_CTL__LINK_EN_SHIFT 0U
+#define DSITX__MCTL_MAIN_DATA_CTL__LINK_EN_WIDTH 1U
+#define DSITX__MCTL_MAIN_DATA_CTL__LINK_EN_WOCLR 0U
+#define DSITX__MCTL_MAIN_DATA_CTL__LINK_EN_WOSET 0U
+#define DSITX__MCTL_MAIN_DATA_CTL__SDI_IF_VID_MODE_MASK 0x00000002U
+#define DSITX__MCTL_MAIN_DATA_CTL__SDI_IF_VID_MODE_SHIFT 1U
+#define DSITX__MCTL_MAIN_DATA_CTL__SDI_IF_VID_MODE_WIDTH 1U
+#define DSITX__MCTL_MAIN_DATA_CTL__SDI_IF_VID_MODE_WOCLR 0U
+#define DSITX__MCTL_MAIN_DATA_CTL__SDI_IF_VID_MODE_WOSET 0U
+#define DSITX__MCTL_MAIN_DATA_CTL__VID_IF_SELECT_MASK 0x0000000CU
+#define DSITX__MCTL_MAIN_DATA_CTL__VID_IF_SELECT_SHIFT 2U
+#define DSITX__MCTL_MAIN_DATA_CTL__VID_IF_SELECT_WIDTH 2U
+#define DSITX__MCTL_MAIN_DATA_CTL__RSVD_0_MASK 0x00000010U
+#define DSITX__MCTL_MAIN_DATA_CTL__RSVD_0_SHIFT 4U
+#define DSITX__MCTL_MAIN_DATA_CTL__RSVD_0_WIDTH 1U
+#define DSITX__MCTL_MAIN_DATA_CTL__RSVD_0_WOCLR 0U
+#define DSITX__MCTL_MAIN_DATA_CTL__RSVD_0_WOSET 0U
+#define DSITX__MCTL_MAIN_DATA_CTL__VID_EN_MASK 0x00000020U
+#define DSITX__MCTL_MAIN_DATA_CTL__VID_EN_SHIFT 5U
+#define DSITX__MCTL_MAIN_DATA_CTL__VID_EN_WIDTH 1U
+#define DSITX__MCTL_MAIN_DATA_CTL__VID_EN_WOCLR 0U
+#define DSITX__MCTL_MAIN_DATA_CTL__VID_EN_WOSET 0U
+#define DSITX__MCTL_MAIN_DATA_CTL__TVG_SEL_MASK 0x00000040U
+#define DSITX__MCTL_MAIN_DATA_CTL__TVG_SEL_SHIFT 6U
+#define DSITX__MCTL_MAIN_DATA_CTL__TVG_SEL_WIDTH 1U
+#define DSITX__MCTL_MAIN_DATA_CTL__TVG_SEL_WOCLR 0U
+#define DSITX__MCTL_MAIN_DATA_CTL__TVG_SEL_WOSET 0U
+#define DSITX__MCTL_MAIN_DATA_CTL__RSVD_1_MASK 0x00000080U
+#define DSITX__MCTL_MAIN_DATA_CTL__RSVD_1_SHIFT 7U
+#define DSITX__MCTL_MAIN_DATA_CTL__RSVD_1_WIDTH 1U
+#define DSITX__MCTL_MAIN_DATA_CTL__RSVD_1_WOCLR 0U
+#define DSITX__MCTL_MAIN_DATA_CTL__RSVD_1_WOSET 0U
+#define DSITX__MCTL_MAIN_DATA_CTL__IF1_TE_EN_MASK 0x00000100U
+#define DSITX__MCTL_MAIN_DATA_CTL__IF1_TE_EN_SHIFT 8U
+#define DSITX__MCTL_MAIN_DATA_CTL__IF1_TE_EN_WIDTH 1U
+#define DSITX__MCTL_MAIN_DATA_CTL__IF1_TE_EN_WOCLR 0U
+#define DSITX__MCTL_MAIN_DATA_CTL__IF1_TE_EN_WOSET 0U
+#define DSITX__MCTL_MAIN_DATA_CTL__IF3_TE_EN_MASK 0x00000200U
+#define DSITX__MCTL_MAIN_DATA_CTL__IF3_TE_EN_SHIFT 9U
+#define DSITX__MCTL_MAIN_DATA_CTL__IF3_TE_EN_WIDTH 1U
+#define DSITX__MCTL_MAIN_DATA_CTL__IF3_TE_EN_WOCLR 0U
+#define DSITX__MCTL_MAIN_DATA_CTL__IF3_TE_EN_WOSET 0U
+#define DSITX__MCTL_MAIN_DATA_CTL__SPLIT_PANEL_MODE_MASK 0x00000400U
+#define DSITX__MCTL_MAIN_DATA_CTL__SPLIT_PANEL_MODE_SHIFT 10U
+#define DSITX__MCTL_MAIN_DATA_CTL__SPLIT_PANEL_MODE_WIDTH 1U
+#define DSITX__MCTL_MAIN_DATA_CTL__SPLIT_PANEL_MODE_WOCLR 0U
+#define DSITX__MCTL_MAIN_DATA_CTL__SPLIT_PANEL_MODE_WOSET 0U
+#define DSITX__MCTL_MAIN_DATA_CTL__RSVD_2_MASK 0x00000800U
+#define DSITX__MCTL_MAIN_DATA_CTL__RSVD_2_SHIFT 11U
+#define DSITX__MCTL_MAIN_DATA_CTL__RSVD_2_WIDTH 1U
+#define DSITX__MCTL_MAIN_DATA_CTL__RSVD_2_WOCLR 0U
+#define DSITX__MCTL_MAIN_DATA_CTL__RSVD_2_WOSET 0U
+#define DSITX__MCTL_MAIN_DATA_CTL__REG_TE_EN_MASK 0x00001000U
+#define DSITX__MCTL_MAIN_DATA_CTL__REG_TE_EN_SHIFT 12U
+#define DSITX__MCTL_MAIN_DATA_CTL__REG_TE_EN_WIDTH 1U
+#define DSITX__MCTL_MAIN_DATA_CTL__REG_TE_EN_WOCLR 0U
+#define DSITX__MCTL_MAIN_DATA_CTL__REG_TE_EN_WOSET 0U
+#define DSITX__MCTL_MAIN_DATA_CTL__READ_EN_MASK 0x00002000U
+#define DSITX__MCTL_MAIN_DATA_CTL__READ_EN_SHIFT 13U
+#define DSITX__MCTL_MAIN_DATA_CTL__READ_EN_WIDTH 1U
+#define DSITX__MCTL_MAIN_DATA_CTL__READ_EN_WOCLR 0U
+#define DSITX__MCTL_MAIN_DATA_CTL__READ_EN_WOSET 0U
+#define DSITX__MCTL_MAIN_DATA_CTL__BTA_EN_MASK 0x00004000U
+#define DSITX__MCTL_MAIN_DATA_CTL__BTA_EN_SHIFT 14U
+#define DSITX__MCTL_MAIN_DATA_CTL__BTA_EN_WIDTH 1U
+#define DSITX__MCTL_MAIN_DATA_CTL__BTA_EN_WOCLR 0U
+#define DSITX__MCTL_MAIN_DATA_CTL__BTA_EN_WOSET 0U
+#define DSITX__MCTL_MAIN_DATA_CTL__DISP_GEN_ECC_MASK 0x00008000U
+#define DSITX__MCTL_MAIN_DATA_CTL__DISP_GEN_ECC_SHIFT 15U
+#define DSITX__MCTL_MAIN_DATA_CTL__DISP_GEN_ECC_WIDTH 1U
+#define DSITX__MCTL_MAIN_DATA_CTL__DISP_GEN_ECC_WOCLR 0U
+#define DSITX__MCTL_MAIN_DATA_CTL__DISP_GEN_ECC_WOSET 0U
+#define DSITX__MCTL_MAIN_DATA_CTL__DISP_GEN_CHECKSUM_MASK 0x00010000U
+#define DSITX__MCTL_MAIN_DATA_CTL__DISP_GEN_CHECKSUM_SHIFT 16U
+#define DSITX__MCTL_MAIN_DATA_CTL__DISP_GEN_CHECKSUM_WIDTH 1U
+#define DSITX__MCTL_MAIN_DATA_CTL__DISP_GEN_CHECKSUM_WOCLR 0U
+#define DSITX__MCTL_MAIN_DATA_CTL__DISP_GEN_CHECKSUM_WOSET 0U
+#define DSITX__MCTL_MAIN_DATA_CTL__HOST_EOT_GEN_MASK 0x00020000U
+#define DSITX__MCTL_MAIN_DATA_CTL__HOST_EOT_GEN_SHIFT 17U
+#define DSITX__MCTL_MAIN_DATA_CTL__HOST_EOT_GEN_WIDTH 1U
+#define DSITX__MCTL_MAIN_DATA_CTL__HOST_EOT_GEN_WOCLR 0U
+#define DSITX__MCTL_MAIN_DATA_CTL__HOST_EOT_GEN_WOSET 0U
+#define DSITX__MCTL_MAIN_DATA_CTL__DISP_EOT_GEN_MASK 0x00040000U
+#define DSITX__MCTL_MAIN_DATA_CTL__DISP_EOT_GEN_SHIFT 18U
+#define DSITX__MCTL_MAIN_DATA_CTL__DISP_EOT_GEN_WIDTH 1U
+#define DSITX__MCTL_MAIN_DATA_CTL__DISP_EOT_GEN_WOCLR 0U
+#define DSITX__MCTL_MAIN_DATA_CTL__DISP_EOT_GEN_WOSET 0U
+#define DSITX__MCTL_MAIN_DATA_CTL__RSVD_3_MASK 0x00F80000U
+#define DSITX__MCTL_MAIN_DATA_CTL__RSVD_3_SHIFT 19U
+#define DSITX__MCTL_MAIN_DATA_CTL__RSVD_3_WIDTH 5U
+#define DSITX__MCTL_MAIN_DATA_CTL__TE_HW_POLLING_EN_MASK 0x01000000U
+#define DSITX__MCTL_MAIN_DATA_CTL__TE_HW_POLLING_EN_SHIFT 24U
+#define DSITX__MCTL_MAIN_DATA_CTL__TE_HW_POLLING_EN_WIDTH 1U
+#define DSITX__MCTL_MAIN_DATA_CTL__TE_HW_POLLING_EN_WOCLR 0U
+#define DSITX__MCTL_MAIN_DATA_CTL__TE_HW_POLLING_EN_WOSET 0U
+#define DSITX__MCTL_MAIN_DATA_CTL__TE_MIPI_POLLING_EN_MASK 0x02000000U
+#define DSITX__MCTL_MAIN_DATA_CTL__TE_MIPI_POLLING_EN_SHIFT 25U
+#define DSITX__MCTL_MAIN_DATA_CTL__TE_MIPI_POLLING_EN_WIDTH 1U
+#define DSITX__MCTL_MAIN_DATA_CTL__TE_MIPI_POLLING_EN_WOCLR 0U
+#define DSITX__MCTL_MAIN_DATA_CTL__TE_MIPI_POLLING_EN_WOSET 0U
+#define DSITX__MCTL_MAIN_DATA_CTL__RSVD_4_MASK 0xFC000000U
+#define DSITX__MCTL_MAIN_DATA_CTL__RSVD_4_SHIFT 26U
+#define DSITX__MCTL_MAIN_DATA_CTL__RSVD_4_WIDTH 6U
+
+#define DSITX__MCTL_MAIN_PHY_CTL_READ_MASK 0xFFFFFFFFU
+#define DSITX__MCTL_MAIN_PHY_CTL_WRITE_MASK 0xFFFFFFFFU
+#define DSITX__MCTL_MAIN_PHY_CTL__LANE2_EN_MASK 0x00000001U
+#define DSITX__MCTL_MAIN_PHY_CTL__LANE2_EN_SHIFT 0U
+#define DSITX__MCTL_MAIN_PHY_CTL__LANE2_EN_WIDTH 1U
+#define DSITX__MCTL_MAIN_PHY_CTL__LANE2_EN_WOCLR 0U
+#define DSITX__MCTL_MAIN_PHY_CTL__LANE2_EN_WOSET 0U
+#define DSITX__MCTL_MAIN_PHY_CTL__LANE3_EN_MASK 0x00000002U
+#define DSITX__MCTL_MAIN_PHY_CTL__LANE3_EN_SHIFT 1U
+#define DSITX__MCTL_MAIN_PHY_CTL__LANE3_EN_WIDTH 1U
+#define DSITX__MCTL_MAIN_PHY_CTL__LANE3_EN_WOCLR 0U
+#define DSITX__MCTL_MAIN_PHY_CTL__LANE3_EN_WOSET 0U
+#define DSITX__MCTL_MAIN_PHY_CTL__LANE4_EN_MASK 0x00000004U
+#define DSITX__MCTL_MAIN_PHY_CTL__LANE4_EN_SHIFT 2U
+#define DSITX__MCTL_MAIN_PHY_CTL__LANE4_EN_WIDTH 1U
+#define DSITX__MCTL_MAIN_PHY_CTL__LANE4_EN_WOCLR 0U
+#define DSITX__MCTL_MAIN_PHY_CTL__LANE4_EN_WOSET 0U
+#define DSITX__MCTL_MAIN_PHY_CTL__RSVD_0_MASK 0x00000008U
+#define DSITX__MCTL_MAIN_PHY_CTL__RSVD_0_SHIFT 3U
+#define DSITX__MCTL_MAIN_PHY_CTL__RSVD_0_WIDTH 1U
+#define DSITX__MCTL_MAIN_PHY_CTL__RSVD_0_WOCLR 0U
+#define DSITX__MCTL_MAIN_PHY_CTL__RSVD_0_WOSET 0U
+#define DSITX__MCTL_MAIN_PHY_CTL__CLK_CONTINUOUS_MASK 0x00000010U
+#define DSITX__MCTL_MAIN_PHY_CTL__CLK_CONTINUOUS_SHIFT 4U
+#define DSITX__MCTL_MAIN_PHY_CTL__CLK_CONTINUOUS_WIDTH 1U
+#define DSITX__MCTL_MAIN_PHY_CTL__CLK_CONTINUOUS_WOCLR 0U
+#define DSITX__MCTL_MAIN_PHY_CTL__CLK_CONTINUOUS_WOSET 0U
+#define DSITX__MCTL_MAIN_PHY_CTL__CLK_ULPM_EN_MASK 0x00000020U
+#define DSITX__MCTL_MAIN_PHY_CTL__CLK_ULPM_EN_SHIFT 5U
+#define DSITX__MCTL_MAIN_PHY_CTL__CLK_ULPM_EN_WIDTH 1U
+#define DSITX__MCTL_MAIN_PHY_CTL__CLK_ULPM_EN_WOCLR 0U
+#define DSITX__MCTL_MAIN_PHY_CTL__CLK_ULPM_EN_WOSET 0U
+#define DSITX__MCTL_MAIN_PHY_CTL__DAT1_ULPM_EN_MASK 0x00000040U
+#define DSITX__MCTL_MAIN_PHY_CTL__DAT1_ULPM_EN_SHIFT 6U
+#define DSITX__MCTL_MAIN_PHY_CTL__DAT1_ULPM_EN_WIDTH 1U
+#define DSITX__MCTL_MAIN_PHY_CTL__DAT1_ULPM_EN_WOCLR 0U
+#define DSITX__MCTL_MAIN_PHY_CTL__DAT1_ULPM_EN_WOSET 0U
+#define DSITX__MCTL_MAIN_PHY_CTL__DAT2_ULPM_EN_MASK 0x00000080U
+#define DSITX__MCTL_MAIN_PHY_CTL__DAT2_ULPM_EN_SHIFT 7U
+#define DSITX__MCTL_MAIN_PHY_CTL__DAT2_ULPM_EN_WIDTH 1U
+#define DSITX__MCTL_MAIN_PHY_CTL__DAT2_ULPM_EN_WOCLR 0U
+#define DSITX__MCTL_MAIN_PHY_CTL__DAT2_ULPM_EN_WOSET 0U
+#define DSITX__MCTL_MAIN_PHY_CTL__DAT3_ULPM_EN_MASK 0x00000100U
+#define DSITX__MCTL_MAIN_PHY_CTL__DAT3_ULPM_EN_SHIFT 8U
+#define DSITX__MCTL_MAIN_PHY_CTL__DAT3_ULPM_EN_WIDTH 1U
+#define DSITX__MCTL_MAIN_PHY_CTL__DAT3_ULPM_EN_WOCLR 0U
+#define DSITX__MCTL_MAIN_PHY_CTL__DAT3_ULPM_EN_WOSET 0U
+#define DSITX__MCTL_MAIN_PHY_CTL__DAT4_ULPM_EN_MASK 0x00000200U
+#define DSITX__MCTL_MAIN_PHY_CTL__DAT4_ULPM_EN_SHIFT 9U
+#define DSITX__MCTL_MAIN_PHY_CTL__DAT4_ULPM_EN_WIDTH 1U
+#define DSITX__MCTL_MAIN_PHY_CTL__DAT4_ULPM_EN_WOCLR 0U
+#define DSITX__MCTL_MAIN_PHY_CTL__DAT4_ULPM_EN_WOSET 0U
+#define DSITX__MCTL_MAIN_PHY_CTL__WAIT_BURST_TIME_MASK 0x00003C00U
+#define DSITX__MCTL_MAIN_PHY_CTL__WAIT_BURST_TIME_SHIFT 10U
+#define DSITX__MCTL_MAIN_PHY_CTL__WAIT_BURST_TIME_WIDTH 4U
+#define DSITX__MCTL_MAIN_PHY_CTL__RSVD_1_MASK 0x0000C000U
+#define DSITX__MCTL_MAIN_PHY_CTL__RSVD_1_SHIFT 14U
+#define DSITX__MCTL_MAIN_PHY_CTL__RSVD_1_WIDTH 2U
+#define DSITX__MCTL_MAIN_PHY_CTL__SWAP_PINS_CLK_MASK 0x00010000U
+#define DSITX__MCTL_MAIN_PHY_CTL__SWAP_PINS_CLK_SHIFT 16U
+#define DSITX__MCTL_MAIN_PHY_CTL__SWAP_PINS_CLK_WIDTH 1U
+#define DSITX__MCTL_MAIN_PHY_CTL__SWAP_PINS_CLK_WOCLR 0U
+#define DSITX__MCTL_MAIN_PHY_CTL__SWAP_PINS_CLK_WOSET 0U
+#define DSITX__MCTL_MAIN_PHY_CTL__HS_INVERT_CLK_MASK 0x00020000U
+#define DSITX__MCTL_MAIN_PHY_CTL__HS_INVERT_CLK_SHIFT 17U
+#define DSITX__MCTL_MAIN_PHY_CTL__HS_INVERT_CLK_WIDTH 1U
+#define DSITX__MCTL_MAIN_PHY_CTL__HS_INVERT_CLK_WOCLR 0U
+#define DSITX__MCTL_MAIN_PHY_CTL__HS_INVERT_CLK_WOSET 0U
+#define DSITX__MCTL_MAIN_PHY_CTL__SWAP_PINS_DAT1_MASK 0x00040000U
+#define DSITX__MCTL_MAIN_PHY_CTL__SWAP_PINS_DAT1_SHIFT 18U
+#define DSITX__MCTL_MAIN_PHY_CTL__SWAP_PINS_DAT1_WIDTH 1U
+#define DSITX__MCTL_MAIN_PHY_CTL__SWAP_PINS_DAT1_WOCLR 0U
+#define DSITX__MCTL_MAIN_PHY_CTL__SWAP_PINS_DAT1_WOSET 0U
+#define DSITX__MCTL_MAIN_PHY_CTL__HS_INVERT_DAT1_MASK 0x00080000U
+#define DSITX__MCTL_MAIN_PHY_CTL__HS_INVERT_DAT1_SHIFT 19U
+#define DSITX__MCTL_MAIN_PHY_CTL__HS_INVERT_DAT1_WIDTH 1U
+#define DSITX__MCTL_MAIN_PHY_CTL__HS_INVERT_DAT1_WOCLR 0U
+#define DSITX__MCTL_MAIN_PHY_CTL__HS_INVERT_DAT1_WOSET 0U
+#define DSITX__MCTL_MAIN_PHY_CTL__SWAP_PINS_DAT2_MASK 0x00100000U
+#define DSITX__MCTL_MAIN_PHY_CTL__SWAP_PINS_DAT2_SHIFT 20U
+#define DSITX__MCTL_MAIN_PHY_CTL__SWAP_PINS_DAT2_WIDTH 1U
+#define DSITX__MCTL_MAIN_PHY_CTL__SWAP_PINS_DAT2_WOCLR 0U
+#define DSITX__MCTL_MAIN_PHY_CTL__SWAP_PINS_DAT2_WOSET 0U
+#define DSITX__MCTL_MAIN_PHY_CTL__HS_INVERT_DAT2_MASK 0x00200000U
+#define DSITX__MCTL_MAIN_PHY_CTL__HS_INVERT_DAT2_SHIFT 21U
+#define DSITX__MCTL_MAIN_PHY_CTL__HS_INVERT_DAT2_WIDTH 1U
+#define DSITX__MCTL_MAIN_PHY_CTL__HS_INVERT_DAT2_WOCLR 0U
+#define DSITX__MCTL_MAIN_PHY_CTL__HS_INVERT_DAT2_WOSET 0U
+#define DSITX__MCTL_MAIN_PHY_CTL__SWAP_PINS_DAT3_MASK 0x00400000U
+#define DSITX__MCTL_MAIN_PHY_CTL__SWAP_PINS_DAT3_SHIFT 22U
+#define DSITX__MCTL_MAIN_PHY_CTL__SWAP_PINS_DAT3_WIDTH 1U
+#define DSITX__MCTL_MAIN_PHY_CTL__SWAP_PINS_DAT3_WOCLR 0U
+#define DSITX__MCTL_MAIN_PHY_CTL__SWAP_PINS_DAT3_WOSET 0U
+#define DSITX__MCTL_MAIN_PHY_CTL__HS_INVERT_DAT3_MASK 0x00800000U
+#define DSITX__MCTL_MAIN_PHY_CTL__HS_INVERT_DAT3_SHIFT 23U
+#define DSITX__MCTL_MAIN_PHY_CTL__HS_INVERT_DAT3_WIDTH 1U
+#define DSITX__MCTL_MAIN_PHY_CTL__HS_INVERT_DAT3_WOCLR 0U
+#define DSITX__MCTL_MAIN_PHY_CTL__HS_INVERT_DAT3_WOSET 0U
+#define DSITX__MCTL_MAIN_PHY_CTL__SWAP_PINS_DAT4_MASK 0x01000000U
+#define DSITX__MCTL_MAIN_PHY_CTL__SWAP_PINS_DAT4_SHIFT 24U
+#define DSITX__MCTL_MAIN_PHY_CTL__SWAP_PINS_DAT4_WIDTH 1U
+#define DSITX__MCTL_MAIN_PHY_CTL__SWAP_PINS_DAT4_WOCLR 0U
+#define DSITX__MCTL_MAIN_PHY_CTL__SWAP_PINS_DAT4_WOSET 0U
+#define DSITX__MCTL_MAIN_PHY_CTL__HS_INVERT_DAT4_MASK 0x02000000U
+#define DSITX__MCTL_MAIN_PHY_CTL__HS_INVERT_DAT4_SHIFT 25U
+#define DSITX__MCTL_MAIN_PHY_CTL__HS_INVERT_DAT4_WIDTH 1U
+#define DSITX__MCTL_MAIN_PHY_CTL__HS_INVERT_DAT4_WOCLR 0U
+#define DSITX__MCTL_MAIN_PHY_CTL__HS_INVERT_DAT4_WOSET 0U
+#define DSITX__MCTL_MAIN_PHY_CTL__RSVD_2_MASK 0x0C000000U
+#define DSITX__MCTL_MAIN_PHY_CTL__RSVD_2_SHIFT 26U
+#define DSITX__MCTL_MAIN_PHY_CTL__RSVD_2_WIDTH 2U
+#define DSITX__MCTL_MAIN_PHY_CTL__HS_SKEWCAL_EN_MASK 0x10000000U
+#define DSITX__MCTL_MAIN_PHY_CTL__HS_SKEWCAL_EN_SHIFT 28U
+#define DSITX__MCTL_MAIN_PHY_CTL__HS_SKEWCAL_EN_WIDTH 1U
+#define DSITX__MCTL_MAIN_PHY_CTL__HS_SKEWCAL_EN_WOCLR 0U
+#define DSITX__MCTL_MAIN_PHY_CTL__HS_SKEWCAL_EN_WOSET 0U
+#define DSITX__MCTL_MAIN_PHY_CTL__HS_SKEWCAL_FORCE_EN_MASK 0x20000000U
+#define DSITX__MCTL_MAIN_PHY_CTL__HS_SKEWCAL_FORCE_EN_SHIFT 29U
+#define DSITX__MCTL_MAIN_PHY_CTL__HS_SKEWCAL_FORCE_EN_WIDTH 1U
+#define DSITX__MCTL_MAIN_PHY_CTL__HS_SKEWCAL_FORCE_EN_WOCLR 0U
+#define DSITX__MCTL_MAIN_PHY_CTL__HS_SKEWCAL_FORCE_EN_WOSET 0U
+#define DSITX__MCTL_MAIN_PHY_CTL__HS_SKEWCAL_TIMEOUT_EN_MASK 0x40000000U
+#define DSITX__MCTL_MAIN_PHY_CTL__HS_SKEWCAL_TIMEOUT_EN_SHIFT 30U
+#define DSITX__MCTL_MAIN_PHY_CTL__HS_SKEWCAL_TIMEOUT_EN_WIDTH 1U
+#define DSITX__MCTL_MAIN_PHY_CTL__HS_SKEWCAL_TIMEOUT_EN_WOCLR 0U
+#define DSITX__MCTL_MAIN_PHY_CTL__HS_SKEWCAL_TIMEOUT_EN_WOSET 0U
+#define DSITX__MCTL_MAIN_PHY_CTL__RSVD_3_MASK 0x80000000U
+#define DSITX__MCTL_MAIN_PHY_CTL__RSVD_3_SHIFT 31U
+#define DSITX__MCTL_MAIN_PHY_CTL__RSVD_3_WIDTH 1U
+#define DSITX__MCTL_MAIN_PHY_CTL__RSVD_3_WOCLR 0U
+#define DSITX__MCTL_MAIN_PHY_CTL__RSVD_3_WOSET 0U
+
+#define DSITX__MCTL_MAIN_EN_READ_MASK 0xFFFFFFFFU
+#define DSITX__MCTL_MAIN_EN_WRITE_MASK 0xFFFFFFFFU
+#define DSITX__MCTL_MAIN_EN__PLL_START_MASK 0x00000001U
+#define DSITX__MCTL_MAIN_EN__PLL_START_SHIFT 0U
+#define DSITX__MCTL_MAIN_EN__PLL_START_WIDTH 1U
+#define DSITX__MCTL_MAIN_EN__PLL_START_WOCLR 0U
+#define DSITX__MCTL_MAIN_EN__PLL_START_WOSET 0U
+#define DSITX__MCTL_MAIN_EN__RSVD_0_MASK 0x00000006U
+#define DSITX__MCTL_MAIN_EN__RSVD_0_SHIFT 1U
+#define DSITX__MCTL_MAIN_EN__RSVD_0_WIDTH 2U
+#define DSITX__MCTL_MAIN_EN__CKLANE_EN_MASK 0x00000008U
+#define DSITX__MCTL_MAIN_EN__CKLANE_EN_SHIFT 3U
+#define DSITX__MCTL_MAIN_EN__CKLANE_EN_WIDTH 1U
+#define DSITX__MCTL_MAIN_EN__CKLANE_EN_WOCLR 0U
+#define DSITX__MCTL_MAIN_EN__CKLANE_EN_WOSET 0U
+#define DSITX__MCTL_MAIN_EN__DAT1_EN_MASK 0x00000010U
+#define DSITX__MCTL_MAIN_EN__DAT1_EN_SHIFT 4U
+#define DSITX__MCTL_MAIN_EN__DAT1_EN_WIDTH 1U
+#define DSITX__MCTL_MAIN_EN__DAT1_EN_WOCLR 0U
+#define DSITX__MCTL_MAIN_EN__DAT1_EN_WOSET 0U
+#define DSITX__MCTL_MAIN_EN__DAT2_EN_MASK 0x00000020U
+#define DSITX__MCTL_MAIN_EN__DAT2_EN_SHIFT 5U
+#define DSITX__MCTL_MAIN_EN__DAT2_EN_WIDTH 1U
+#define DSITX__MCTL_MAIN_EN__DAT2_EN_WOCLR 0U
+#define DSITX__MCTL_MAIN_EN__DAT2_EN_WOSET 0U
+#define DSITX__MCTL_MAIN_EN__DAT3_EN_MASK 0x00000040U
+#define DSITX__MCTL_MAIN_EN__DAT3_EN_SHIFT 6U
+#define DSITX__MCTL_MAIN_EN__DAT3_EN_WIDTH 1U
+#define DSITX__MCTL_MAIN_EN__DAT3_EN_WOCLR 0U
+#define DSITX__MCTL_MAIN_EN__DAT3_EN_WOSET 0U
+#define DSITX__MCTL_MAIN_EN__DAT4_EN_MASK 0x00000080U
+#define DSITX__MCTL_MAIN_EN__DAT4_EN_SHIFT 7U
+#define DSITX__MCTL_MAIN_EN__DAT4_EN_WIDTH 1U
+#define DSITX__MCTL_MAIN_EN__DAT4_EN_WOCLR 0U
+#define DSITX__MCTL_MAIN_EN__DAT4_EN_WOSET 0U
+#define DSITX__MCTL_MAIN_EN__CLKLANE_ULPM_REQ_MASK 0x00000100U
+#define DSITX__MCTL_MAIN_EN__CLKLANE_ULPM_REQ_SHIFT 8U
+#define DSITX__MCTL_MAIN_EN__CLKLANE_ULPM_REQ_WIDTH 1U
+#define DSITX__MCTL_MAIN_EN__CLKLANE_ULPM_REQ_WOCLR 0U
+#define DSITX__MCTL_MAIN_EN__CLKLANE_ULPM_REQ_WOSET 0U
+#define DSITX__MCTL_MAIN_EN__DAT1_ULPM_REQ_MASK 0x00000200U
+#define DSITX__MCTL_MAIN_EN__DAT1_ULPM_REQ_SHIFT 9U
+#define DSITX__MCTL_MAIN_EN__DAT1_ULPM_REQ_WIDTH 1U
+#define DSITX__MCTL_MAIN_EN__DAT1_ULPM_REQ_WOCLR 0U
+#define DSITX__MCTL_MAIN_EN__DAT1_ULPM_REQ_WOSET 0U
+#define DSITX__MCTL_MAIN_EN__DAT2_ULPM_REQ_MASK 0x00000400U
+#define DSITX__MCTL_MAIN_EN__DAT2_ULPM_REQ_SHIFT 10U
+#define DSITX__MCTL_MAIN_EN__DAT2_ULPM_REQ_WIDTH 1U
+#define DSITX__MCTL_MAIN_EN__DAT2_ULPM_REQ_WOCLR 0U
+#define DSITX__MCTL_MAIN_EN__DAT2_ULPM_REQ_WOSET 0U
+#define DSITX__MCTL_MAIN_EN__DAT3_ULPM_REQ_MASK 0x00000800U
+#define DSITX__MCTL_MAIN_EN__DAT3_ULPM_REQ_SHIFT 11U
+#define DSITX__MCTL_MAIN_EN__DAT3_ULPM_REQ_WIDTH 1U
+#define DSITX__MCTL_MAIN_EN__DAT3_ULPM_REQ_WOCLR 0U
+#define DSITX__MCTL_MAIN_EN__DAT3_ULPM_REQ_WOSET 0U
+#define DSITX__MCTL_MAIN_EN__DAT4_ULPM_REQ_MASK 0x00001000U
+#define DSITX__MCTL_MAIN_EN__DAT4_ULPM_REQ_SHIFT 12U
+#define DSITX__MCTL_MAIN_EN__DAT4_ULPM_REQ_WIDTH 1U
+#define DSITX__MCTL_MAIN_EN__DAT4_ULPM_REQ_WOCLR 0U
+#define DSITX__MCTL_MAIN_EN__DAT4_ULPM_REQ_WOSET 0U
+#define DSITX__MCTL_MAIN_EN__IF1_EN_MASK 0x00002000U
+#define DSITX__MCTL_MAIN_EN__IF1_EN_SHIFT 13U
+#define DSITX__MCTL_MAIN_EN__IF1_EN_WIDTH 1U
+#define DSITX__MCTL_MAIN_EN__IF1_EN_WOCLR 0U
+#define DSITX__MCTL_MAIN_EN__IF1_EN_WOSET 0U
+#define DSITX__MCTL_MAIN_EN__IF2_EN_MASK 0x00004000U
+#define DSITX__MCTL_MAIN_EN__IF2_EN_SHIFT 14U
+#define DSITX__MCTL_MAIN_EN__IF2_EN_WIDTH 1U
+#define DSITX__MCTL_MAIN_EN__IF2_EN_WOCLR 0U
+#define DSITX__MCTL_MAIN_EN__IF2_EN_WOSET 0U
+#define DSITX__MCTL_MAIN_EN__IF3_EN_MASK 0x00008000U
+#define DSITX__MCTL_MAIN_EN__IF3_EN_SHIFT 15U
+#define DSITX__MCTL_MAIN_EN__IF3_EN_WIDTH 1U
+#define DSITX__MCTL_MAIN_EN__IF3_EN_WOCLR 0U
+#define DSITX__MCTL_MAIN_EN__IF3_EN_WOSET 0U
+#define DSITX__MCTL_MAIN_EN__CLK_FORCE_STOP_MASK 0x00010000U
+#define DSITX__MCTL_MAIN_EN__CLK_FORCE_STOP_SHIFT 16U
+#define DSITX__MCTL_MAIN_EN__CLK_FORCE_STOP_WIDTH 1U
+#define DSITX__MCTL_MAIN_EN__CLK_FORCE_STOP_WOCLR 0U
+#define DSITX__MCTL_MAIN_EN__CLK_FORCE_STOP_WOSET 0U
+#define DSITX__MCTL_MAIN_EN__FORCE_STOP_MODE_MASK 0x00020000U
+#define DSITX__MCTL_MAIN_EN__FORCE_STOP_MODE_SHIFT 17U
+#define DSITX__MCTL_MAIN_EN__FORCE_STOP_MODE_WIDTH 1U
+#define DSITX__MCTL_MAIN_EN__FORCE_STOP_MODE_WOCLR 0U
+#define DSITX__MCTL_MAIN_EN__FORCE_STOP_MODE_WOSET 0U
+#define DSITX__MCTL_MAIN_EN__RSVD_1_MASK 0xFFFC0000U
+#define DSITX__MCTL_MAIN_EN__RSVD_1_SHIFT 18U
+#define DSITX__MCTL_MAIN_EN__RSVD_1_WIDTH 14U
+
+#define DSITX__MCTL_DPHY_CFG0_READ_MASK 0xFFFFFFFFU
+#define DSITX__MCTL_DPHY_CFG0_WRITE_MASK 0xFFFFFFFFU
+#define DSITX__MCTL_DPHY_CFG0__DPHY_CMN_PSO_MASK 0x00000001U
+#define DSITX__MCTL_DPHY_CFG0__DPHY_CMN_PSO_SHIFT 0U
+#define DSITX__MCTL_DPHY_CFG0__DPHY_CMN_PSO_WIDTH 1U
+#define DSITX__MCTL_DPHY_CFG0__DPHY_CMN_PSO_WOCLR 0U
+#define DSITX__MCTL_DPHY_CFG0__DPHY_CMN_PSO_WOSET 0U
+#define DSITX__MCTL_DPHY_CFG0__DPHY_PLL_PSO_MASK 0x00000002U
+#define DSITX__MCTL_DPHY_CFG0__DPHY_PLL_PSO_SHIFT 1U
+#define DSITX__MCTL_DPHY_CFG0__DPHY_PLL_PSO_WIDTH 1U
+#define DSITX__MCTL_DPHY_CFG0__DPHY_PLL_PSO_WOCLR 0U
+#define DSITX__MCTL_DPHY_CFG0__DPHY_PLL_PSO_WOSET 0U
+#define DSITX__MCTL_DPHY_CFG0__RSVD_0_MASK 0x0000000CU
+#define DSITX__MCTL_DPHY_CFG0__RSVD_0_SHIFT 2U
+#define DSITX__MCTL_DPHY_CFG0__RSVD_0_WIDTH 2U
+#define DSITX__MCTL_DPHY_CFG0__DPHY_D_PDN_MASK 0x000000F0U
+#define DSITX__MCTL_DPHY_CFG0__DPHY_D_PDN_SHIFT 4U
+#define DSITX__MCTL_DPHY_CFG0__DPHY_D_PDN_WIDTH 4U
+#define DSITX__MCTL_DPHY_CFG0__DPHY_C_PDN_MASK 0x00000100U
+#define DSITX__MCTL_DPHY_CFG0__DPHY_C_PDN_SHIFT 8U
+#define DSITX__MCTL_DPHY_CFG0__DPHY_C_PDN_WIDTH 1U
+#define DSITX__MCTL_DPHY_CFG0__DPHY_C_PDN_WOCLR 0U
+#define DSITX__MCTL_DPHY_CFG0__DPHY_C_PDN_WOSET 0U
+#define DSITX__MCTL_DPHY_CFG0__DPHY_CMN_PDN_MASK 0x00000200U
+#define DSITX__MCTL_DPHY_CFG0__DPHY_CMN_PDN_SHIFT 9U
+#define DSITX__MCTL_DPHY_CFG0__DPHY_CMN_PDN_WIDTH 1U
+#define DSITX__MCTL_DPHY_CFG0__DPHY_CMN_PDN_WOCLR 0U
+#define DSITX__MCTL_DPHY_CFG0__DPHY_CMN_PDN_WOSET 0U
+#define DSITX__MCTL_DPHY_CFG0__DPHY_PLL_PDN_MASK 0x00000400U
+#define DSITX__MCTL_DPHY_CFG0__DPHY_PLL_PDN_SHIFT 10U
+#define DSITX__MCTL_DPHY_CFG0__DPHY_PLL_PDN_WIDTH 1U
+#define DSITX__MCTL_DPHY_CFG0__DPHY_PLL_PDN_WOCLR 0U
+#define DSITX__MCTL_DPHY_CFG0__DPHY_PLL_PDN_WOSET 0U
+#define DSITX__MCTL_DPHY_CFG0__RSVD_1_MASK 0x0000F800U
+#define DSITX__MCTL_DPHY_CFG0__RSVD_1_SHIFT 11U
+#define DSITX__MCTL_DPHY_CFG0__RSVD_1_WIDTH 5U
+#define DSITX__MCTL_DPHY_CFG0__DPHY_D_RSTB_MASK 0x000F0000U
+#define DSITX__MCTL_DPHY_CFG0__DPHY_D_RSTB_SHIFT 16U
+#define DSITX__MCTL_DPHY_CFG0__DPHY_D_RSTB_WIDTH 4U
+#define DSITX__MCTL_DPHY_CFG0__DPHY_C_RSTB_MASK 0x00100000U
+#define DSITX__MCTL_DPHY_CFG0__DPHY_C_RSTB_SHIFT 20U
+#define DSITX__MCTL_DPHY_CFG0__DPHY_C_RSTB_WIDTH 1U
+#define DSITX__MCTL_DPHY_CFG0__DPHY_C_RSTB_WOCLR 0U
+#define DSITX__MCTL_DPHY_CFG0__DPHY_C_RSTB_WOSET 0U
+#define DSITX__MCTL_DPHY_CFG0__RSVD_2_MASK 0xFFE00000U
+#define DSITX__MCTL_DPHY_CFG0__RSVD_2_SHIFT 21U
+#define DSITX__MCTL_DPHY_CFG0__RSVD_2_WIDTH 11U
+
+#define DSITX__MCTL_DPHY_TIMEOUT1_READ_MASK 0xFFFFFFFFU
+#define DSITX__MCTL_DPHY_TIMEOUT1_WRITE_MASK 0xFFFFFFFFU
+#define DSITX__MCTL_DPHY_TIMEOUT1__CLK_DIV_MASK 0x0000000FU
+#define DSITX__MCTL_DPHY_TIMEOUT1__CLK_DIV_SHIFT 0U
+#define DSITX__MCTL_DPHY_TIMEOUT1__CLK_DIV_WIDTH 4U
+#define DSITX__MCTL_DPHY_TIMEOUT1__HSTX_TO_VAL_MASK 0x003FFFF0U
+#define DSITX__MCTL_DPHY_TIMEOUT1__HSTX_TO_VAL_SHIFT 4U
+#define DSITX__MCTL_DPHY_TIMEOUT1__HSTX_TO_VAL_WIDTH 18U
+#define DSITX__MCTL_DPHY_TIMEOUT1__RSVD_0_MASK 0xFFC00000U
+#define DSITX__MCTL_DPHY_TIMEOUT1__RSVD_0_SHIFT 22U
+#define DSITX__MCTL_DPHY_TIMEOUT1__RSVD_0_WIDTH 10U
+
+#define DSITX__MCTL_DPHY_TIMEOUT2_READ_MASK 0xFFFFFFFFU
+#define DSITX__MCTL_DPHY_TIMEOUT2_WRITE_MASK 0xFFFFFFFFU
+#define DSITX__MCTL_DPHY_TIMEOUT2__LPRX_TO_VAL_MASK 0x0003FFFFU
+#define DSITX__MCTL_DPHY_TIMEOUT2__LPRX_TO_VAL_SHIFT 0U
+#define DSITX__MCTL_DPHY_TIMEOUT2__LPRX_TO_VAL_WIDTH 18U
+#define DSITX__MCTL_DPHY_TIMEOUT2__RSVD_0_MASK 0xFFFC0000U
+#define DSITX__MCTL_DPHY_TIMEOUT2__RSVD_0_SHIFT 18U
+#define DSITX__MCTL_DPHY_TIMEOUT2__RSVD_0_WIDTH 14U
+
+#define DSITX__MCTL_ULPOUT_TIME_READ_MASK 0xFFFFFFFFU
+#define DSITX__MCTL_ULPOUT_TIME_WRITE_MASK 0xFFFFFFFFU
+#define DSITX__MCTL_ULPOUT_TIME__CKLANE_ULPOUT_TIME_MASK 0x000001FFU
+#define DSITX__MCTL_ULPOUT_TIME__CKLANE_ULPOUT_TIME_SHIFT 0U
+#define DSITX__MCTL_ULPOUT_TIME__CKLANE_ULPOUT_TIME_WIDTH 9U
+#define DSITX__MCTL_ULPOUT_TIME__DATA_ULPOUT_TIME_MASK 0x0003FE00U
+#define DSITX__MCTL_ULPOUT_TIME__DATA_ULPOUT_TIME_SHIFT 9U
+#define DSITX__MCTL_ULPOUT_TIME__DATA_ULPOUT_TIME_WIDTH 9U
+#define DSITX__MCTL_ULPOUT_TIME__RSVD_0_MASK 0xFFFC0000U
+#define DSITX__MCTL_ULPOUT_TIME__RSVD_0_SHIFT 18U
+#define DSITX__MCTL_ULPOUT_TIME__RSVD_0_WIDTH 14U
+
+#define DSITX__MCTL_3DVIDEO_CTL_READ_MASK 0xFFFFFFFFU
+#define DSITX__MCTL_3DVIDEO_CTL_WRITE_MASK 0xFFFFFFFFU
+#define DSITX__MCTL_3DVIDEO_CTL__VID_VSYNC_3DMODE_MASK 0x00000003U
+#define DSITX__MCTL_3DVIDEO_CTL__VID_VSYNC_3DMODE_SHIFT 0U
+#define DSITX__MCTL_3DVIDEO_CTL__VID_VSYNC_3DMODE_WIDTH 2U
+#define DSITX__MCTL_3DVIDEO_CTL__VID_VSYNC_3DFORMAT_MASK 0x0000000CU
+#define DSITX__MCTL_3DVIDEO_CTL__VID_VSYNC_3DFORMAT_SHIFT 2U
+#define DSITX__MCTL_3DVIDEO_CTL__VID_VSYNC_3DFORMAT_WIDTH 2U
+#define DSITX__MCTL_3DVIDEO_CTL__VID_VSYNC_3D_SECOND_EN_MASK 0x00000010U
+#define DSITX__MCTL_3DVIDEO_CTL__VID_VSYNC_3D_SECOND_EN_SHIFT 4U
+#define DSITX__MCTL_3DVIDEO_CTL__VID_VSYNC_3D_SECOND_EN_WIDTH 1U
+#define DSITX__MCTL_3DVIDEO_CTL__VID_VSYNC_3D_SECOND_EN_WOCLR 0U
+#define DSITX__MCTL_3DVIDEO_CTL__VID_VSYNC_3D_SECOND_EN_WOSET 0U
+#define DSITX__MCTL_3DVIDEO_CTL__VID_VSYNC_3D_LR_MASK 0x00000020U
+#define DSITX__MCTL_3DVIDEO_CTL__VID_VSYNC_3D_LR_SHIFT 5U
+#define DSITX__MCTL_3DVIDEO_CTL__VID_VSYNC_3D_LR_WIDTH 1U
+#define DSITX__MCTL_3DVIDEO_CTL__VID_VSYNC_3D_LR_WOCLR 0U
+#define DSITX__MCTL_3DVIDEO_CTL__VID_VSYNC_3D_LR_WOSET 0U
+#define DSITX__MCTL_3DVIDEO_CTL__RSVD_0_MASK 0x00000040U
+#define DSITX__MCTL_3DVIDEO_CTL__RSVD_0_SHIFT 6U
+#define DSITX__MCTL_3DVIDEO_CTL__RSVD_0_WIDTH 1U
+#define DSITX__MCTL_3DVIDEO_CTL__RSVD_0_WOCLR 0U
+#define DSITX__MCTL_3DVIDEO_CTL__RSVD_0_WOSET 0U
+#define DSITX__MCTL_3DVIDEO_CTL__VID_VSYNC_3D_EN_MASK 0x00000080U
+#define DSITX__MCTL_3DVIDEO_CTL__VID_VSYNC_3D_EN_SHIFT 7U
+#define DSITX__MCTL_3DVIDEO_CTL__VID_VSYNC_3D_EN_WIDTH 1U
+#define DSITX__MCTL_3DVIDEO_CTL__VID_VSYNC_3D_EN_WOCLR 0U
+#define DSITX__MCTL_3DVIDEO_CTL__VID_VSYNC_3D_EN_WOSET 0U
+#define DSITX__MCTL_3DVIDEO_CTL__RSVD_1_MASK 0xFFFFFF00U
+#define DSITX__MCTL_3DVIDEO_CTL__RSVD_1_SHIFT 8U
+#define DSITX__MCTL_3DVIDEO_CTL__RSVD_1_WIDTH 24U
+
+#define DSITX__MCTL_MAIN_STS_READ_MASK 0xFFFFFFFFU
+#define DSITX__MCTL_MAIN_STS_WRITE_MASK 0xFFFFFFFFU
+#define DSITX__MCTL_MAIN_STS__PLL_LCK_MASK 0x00000001U
+#define DSITX__MCTL_MAIN_STS__PLL_LCK_SHIFT 0U
+#define DSITX__MCTL_MAIN_STS__PLL_LCK_WIDTH 1U
+#define DSITX__MCTL_MAIN_STS__PLL_LCK_WOCLR 0U
+#define DSITX__MCTL_MAIN_STS__PLL_LCK_WOSET 0U
+#define DSITX__MCTL_MAIN_STS__CLKLANE_READY_MASK 0x00000002U
+#define DSITX__MCTL_MAIN_STS__CLKLANE_READY_SHIFT 1U
+#define DSITX__MCTL_MAIN_STS__CLKLANE_READY_WIDTH 1U
+#define DSITX__MCTL_MAIN_STS__CLKLANE_READY_WOCLR 0U
+#define DSITX__MCTL_MAIN_STS__CLKLANE_READY_WOSET 0U
+#define DSITX__MCTL_MAIN_STS__DAT1_READY_MASK 0x00000004U
+#define DSITX__MCTL_MAIN_STS__DAT1_READY_SHIFT 2U
+#define DSITX__MCTL_MAIN_STS__DAT1_READY_WIDTH 1U
+#define DSITX__MCTL_MAIN_STS__DAT1_READY_WOCLR 0U
+#define DSITX__MCTL_MAIN_STS__DAT1_READY_WOSET 0U
+#define DSITX__MCTL_MAIN_STS__DAT2_READY_MASK 0x00000008U
+#define DSITX__MCTL_MAIN_STS__DAT2_READY_SHIFT 3U
+#define DSITX__MCTL_MAIN_STS__DAT2_READY_WIDTH 1U
+#define DSITX__MCTL_MAIN_STS__DAT2_READY_WOCLR 0U
+#define DSITX__MCTL_MAIN_STS__DAT2_READY_WOSET 0U
+#define DSITX__MCTL_MAIN_STS__DAT3_READY_MASK 0x00000010U
+#define DSITX__MCTL_MAIN_STS__DAT3_READY_SHIFT 4U
+#define DSITX__MCTL_MAIN_STS__DAT3_READY_WIDTH 1U
+#define DSITX__MCTL_MAIN_STS__DAT3_READY_WOCLR 0U
+#define DSITX__MCTL_MAIN_STS__DAT3_READY_WOSET 0U
+#define DSITX__MCTL_MAIN_STS__DAT4_READY_MASK 0x00000020U
+#define DSITX__MCTL_MAIN_STS__DAT4_READY_SHIFT 5U
+#define DSITX__MCTL_MAIN_STS__DAT4_READY_WIDTH 1U
+#define DSITX__MCTL_MAIN_STS__DAT4_READY_WOCLR 0U
+#define DSITX__MCTL_MAIN_STS__DAT4_READY_WOSET 0U
+#define DSITX__MCTL_MAIN_STS__HSTX_TO_ERR_MASK 0x00000040U
+#define DSITX__MCTL_MAIN_STS__HSTX_TO_ERR_SHIFT 6U
+#define DSITX__MCTL_MAIN_STS__HSTX_TO_ERR_WIDTH 1U
+#define DSITX__MCTL_MAIN_STS__HSTX_TO_ERR_WOCLR 0U
+#define DSITX__MCTL_MAIN_STS__HSTX_TO_ERR_WOSET 0U
+#define DSITX__MCTL_MAIN_STS__LPRX_TO_ERR_MASK 0x00000080U
+#define DSITX__MCTL_MAIN_STS__LPRX_TO_ERR_SHIFT 7U
+#define DSITX__MCTL_MAIN_STS__LPRX_TO_ERR_WIDTH 1U
+#define DSITX__MCTL_MAIN_STS__LPRX_TO_ERR_WOCLR 0U
+#define DSITX__MCTL_MAIN_STS__LPRX_TO_ERR_WOSET 0U
+#define DSITX__MCTL_MAIN_STS__IF1_UNTERM_PCK_MASK 0x00000100U
+#define DSITX__MCTL_MAIN_STS__IF1_UNTERM_PCK_SHIFT 8U
+#define DSITX__MCTL_MAIN_STS__IF1_UNTERM_PCK_WIDTH 1U
+#define DSITX__MCTL_MAIN_STS__IF1_UNTERM_PCK_WOCLR 0U
+#define DSITX__MCTL_MAIN_STS__IF1_UNTERM_PCK_WOSET 0U
+#define DSITX__MCTL_MAIN_STS__IF2_UNTERM_PCK_MASK 0x00000200U
+#define DSITX__MCTL_MAIN_STS__IF2_UNTERM_PCK_SHIFT 9U
+#define DSITX__MCTL_MAIN_STS__IF2_UNTERM_PCK_WIDTH 1U
+#define DSITX__MCTL_MAIN_STS__IF2_UNTERM_PCK_WOCLR 0U
+#define DSITX__MCTL_MAIN_STS__IF2_UNTERM_PCK_WOSET 0U
+#define DSITX__MCTL_MAIN_STS__IF3_UNTERM_PCK_MASK 0x00000400U
+#define DSITX__MCTL_MAIN_STS__IF3_UNTERM_PCK_SHIFT 10U
+#define DSITX__MCTL_MAIN_STS__IF3_UNTERM_PCK_WIDTH 1U
+#define DSITX__MCTL_MAIN_STS__IF3_UNTERM_PCK_WOCLR 0U
+#define DSITX__MCTL_MAIN_STS__IF3_UNTERM_PCK_WOSET 0U
+#define DSITX__MCTL_MAIN_STS__HS_SKEWCAL_DONE_MASK 0x00000800U
+#define DSITX__MCTL_MAIN_STS__HS_SKEWCAL_DONE_SHIFT 11U
+#define DSITX__MCTL_MAIN_STS__HS_SKEWCAL_DONE_WIDTH 1U
+#define DSITX__MCTL_MAIN_STS__HS_SKEWCAL_DONE_WOCLR 0U
+#define DSITX__MCTL_MAIN_STS__HS_SKEWCAL_DONE_WOSET 0U
+#define DSITX__MCTL_MAIN_STS__RSVD_0_MASK 0xFFFFF000U
+#define DSITX__MCTL_MAIN_STS__RSVD_0_SHIFT 12U
+#define DSITX__MCTL_MAIN_STS__RSVD_0_WIDTH 20U
+
+#define DSITX__MCTL_DPHY_ERR_READ_MASK 0xFFFFFFFFU
+#define DSITX__MCTL_DPHY_ERR_WRITE_MASK 0xFFFFFFFFU
+#define DSITX__MCTL_DPHY_ERR__RSVD_0_MASK 0x0000003FU
+#define DSITX__MCTL_DPHY_ERR__RSVD_0_SHIFT 0U
+#define DSITX__MCTL_DPHY_ERR__RSVD_0_WIDTH 6U
+#define DSITX__MCTL_DPHY_ERR__ERR_ESC_1_MASK 0x00000040U
+#define DSITX__MCTL_DPHY_ERR__ERR_ESC_1_SHIFT 6U
+#define DSITX__MCTL_DPHY_ERR__ERR_ESC_1_WIDTH 1U
+#define DSITX__MCTL_DPHY_ERR__ERR_ESC_1_WOCLR 0U
+#define DSITX__MCTL_DPHY_ERR__ERR_ESC_1_WOSET 0U
+#define DSITX__MCTL_DPHY_ERR__ERR_ESC_2_MASK 0x00000080U
+#define DSITX__MCTL_DPHY_ERR__ERR_ESC_2_SHIFT 7U
+#define DSITX__MCTL_DPHY_ERR__ERR_ESC_2_WIDTH 1U
+#define DSITX__MCTL_DPHY_ERR__ERR_ESC_2_WOCLR 0U
+#define DSITX__MCTL_DPHY_ERR__ERR_ESC_2_WOSET 0U
+#define DSITX__MCTL_DPHY_ERR__ERR_ESC_3_MASK 0x00000100U
+#define DSITX__MCTL_DPHY_ERR__ERR_ESC_3_SHIFT 8U
+#define DSITX__MCTL_DPHY_ERR__ERR_ESC_3_WIDTH 1U
+#define DSITX__MCTL_DPHY_ERR__ERR_ESC_3_WOCLR 0U
+#define DSITX__MCTL_DPHY_ERR__ERR_ESC_3_WOSET 0U
+#define DSITX__MCTL_DPHY_ERR__ERR_ESC_4_MASK 0x00000200U
+#define DSITX__MCTL_DPHY_ERR__ERR_ESC_4_SHIFT 9U
+#define DSITX__MCTL_DPHY_ERR__ERR_ESC_4_WIDTH 1U
+#define DSITX__MCTL_DPHY_ERR__ERR_ESC_4_WOCLR 0U
+#define DSITX__MCTL_DPHY_ERR__ERR_ESC_4_WOSET 0U
+#define DSITX__MCTL_DPHY_ERR__ERR_SYNCESC_1_MASK 0x00000400U
+#define DSITX__MCTL_DPHY_ERR__ERR_SYNCESC_1_SHIFT 10U
+#define DSITX__MCTL_DPHY_ERR__ERR_SYNCESC_1_WIDTH 1U
+#define DSITX__MCTL_DPHY_ERR__ERR_SYNCESC_1_WOCLR 0U
+#define DSITX__MCTL_DPHY_ERR__ERR_SYNCESC_1_WOSET 0U
+#define DSITX__MCTL_DPHY_ERR__ERR_SYNCESC_2_MASK 0x00000800U
+#define DSITX__MCTL_DPHY_ERR__ERR_SYNCESC_2_SHIFT 11U
+#define DSITX__MCTL_DPHY_ERR__ERR_SYNCESC_2_WIDTH 1U
+#define DSITX__MCTL_DPHY_ERR__ERR_SYNCESC_2_WOCLR 0U
+#define DSITX__MCTL_DPHY_ERR__ERR_SYNCESC_2_WOSET 0U
+#define DSITX__MCTL_DPHY_ERR__ERR_SYNCESC_3_MASK 0x00001000U
+#define DSITX__MCTL_DPHY_ERR__ERR_SYNCESC_3_SHIFT 12U
+#define DSITX__MCTL_DPHY_ERR__ERR_SYNCESC_3_WIDTH 1U
+#define DSITX__MCTL_DPHY_ERR__ERR_SYNCESC_3_WOCLR 0U
+#define DSITX__MCTL_DPHY_ERR__ERR_SYNCESC_3_WOSET 0U
+#define DSITX__MCTL_DPHY_ERR__ERR_SYNCESC_4_MASK 0x00002000U
+#define DSITX__MCTL_DPHY_ERR__ERR_SYNCESC_4_SHIFT 13U
+#define DSITX__MCTL_DPHY_ERR__ERR_SYNCESC_4_WIDTH 1U
+#define DSITX__MCTL_DPHY_ERR__ERR_SYNCESC_4_WOCLR 0U
+#define DSITX__MCTL_DPHY_ERR__ERR_SYNCESC_4_WOSET 0U
+#define DSITX__MCTL_DPHY_ERR__ERR_CONTROL_1_MASK 0x00004000U
+#define DSITX__MCTL_DPHY_ERR__ERR_CONTROL_1_SHIFT 14U
+#define DSITX__MCTL_DPHY_ERR__ERR_CONTROL_1_WIDTH 1U
+#define DSITX__MCTL_DPHY_ERR__ERR_CONTROL_1_WOCLR 0U
+#define DSITX__MCTL_DPHY_ERR__ERR_CONTROL_1_WOSET 0U
+#define DSITX__MCTL_DPHY_ERR__ERR_CONTROL_2_MASK 0x00008000U
+#define DSITX__MCTL_DPHY_ERR__ERR_CONTROL_2_SHIFT 15U
+#define DSITX__MCTL_DPHY_ERR__ERR_CONTROL_2_WIDTH 1U
+#define DSITX__MCTL_DPHY_ERR__ERR_CONTROL_2_WOCLR 0U
+#define DSITX__MCTL_DPHY_ERR__ERR_CONTROL_2_WOSET 0U
+#define DSITX__MCTL_DPHY_ERR__ERR_CONTROL_3_MASK 0x00010000U
+#define DSITX__MCTL_DPHY_ERR__ERR_CONTROL_3_SHIFT 16U
+#define DSITX__MCTL_DPHY_ERR__ERR_CONTROL_3_WIDTH 1U
+#define DSITX__MCTL_DPHY_ERR__ERR_CONTROL_3_WOCLR 0U
+#define DSITX__MCTL_DPHY_ERR__ERR_CONTROL_3_WOSET 0U
+#define DSITX__MCTL_DPHY_ERR__ERR_CONTROL_4_MASK 0x00020000U
+#define DSITX__MCTL_DPHY_ERR__ERR_CONTROL_4_SHIFT 17U
+#define DSITX__MCTL_DPHY_ERR__ERR_CONTROL_4_WIDTH 1U
+#define DSITX__MCTL_DPHY_ERR__ERR_CONTROL_4_WOCLR 0U
+#define DSITX__MCTL_DPHY_ERR__ERR_CONTROL_4_WOSET 0U
+#define DSITX__MCTL_DPHY_ERR__ERR_CONT_LP0_1_MASK 0x00040000U
+#define DSITX__MCTL_DPHY_ERR__ERR_CONT_LP0_1_SHIFT 18U
+#define DSITX__MCTL_DPHY_ERR__ERR_CONT_LP0_1_WIDTH 1U
+#define DSITX__MCTL_DPHY_ERR__ERR_CONT_LP0_1_WOCLR 0U
+#define DSITX__MCTL_DPHY_ERR__ERR_CONT_LP0_1_WOSET 0U
+#define DSITX__MCTL_DPHY_ERR__ERR_CONT_LP0_2_MASK 0x00080000U
+#define DSITX__MCTL_DPHY_ERR__ERR_CONT_LP0_2_SHIFT 19U
+#define DSITX__MCTL_DPHY_ERR__ERR_CONT_LP0_2_WIDTH 1U
+#define DSITX__MCTL_DPHY_ERR__ERR_CONT_LP0_2_WOCLR 0U
+#define DSITX__MCTL_DPHY_ERR__ERR_CONT_LP0_2_WOSET 0U
+#define DSITX__MCTL_DPHY_ERR__ERR_CONT_LP0_3_MASK 0x00100000U
+#define DSITX__MCTL_DPHY_ERR__ERR_CONT_LP0_3_SHIFT 20U
+#define DSITX__MCTL_DPHY_ERR__ERR_CONT_LP0_3_WIDTH 1U
+#define DSITX__MCTL_DPHY_ERR__ERR_CONT_LP0_3_WOCLR 0U
+#define DSITX__MCTL_DPHY_ERR__ERR_CONT_LP0_3_WOSET 0U
+#define DSITX__MCTL_DPHY_ERR__ERR_CONT_LP0_4_MASK 0x00200000U
+#define DSITX__MCTL_DPHY_ERR__ERR_CONT_LP0_4_SHIFT 21U
+#define DSITX__MCTL_DPHY_ERR__ERR_CONT_LP0_4_WIDTH 1U
+#define DSITX__MCTL_DPHY_ERR__ERR_CONT_LP0_4_WOCLR 0U
+#define DSITX__MCTL_DPHY_ERR__ERR_CONT_LP0_4_WOSET 0U
+#define DSITX__MCTL_DPHY_ERR__ERR_CONT_LP1_1_MASK 0x00400000U
+#define DSITX__MCTL_DPHY_ERR__ERR_CONT_LP1_1_SHIFT 22U
+#define DSITX__MCTL_DPHY_ERR__ERR_CONT_LP1_1_WIDTH 1U
+#define DSITX__MCTL_DPHY_ERR__ERR_CONT_LP1_1_WOCLR 0U
+#define DSITX__MCTL_DPHY_ERR__ERR_CONT_LP1_1_WOSET 0U
+#define DSITX__MCTL_DPHY_ERR__ERR_CONT_LP1_2_MASK 0x00800000U
+#define DSITX__MCTL_DPHY_ERR__ERR_CONT_LP1_2_SHIFT 23U
+#define DSITX__MCTL_DPHY_ERR__ERR_CONT_LP1_2_WIDTH 1U
+#define DSITX__MCTL_DPHY_ERR__ERR_CONT_LP1_2_WOCLR 0U
+#define DSITX__MCTL_DPHY_ERR__ERR_CONT_LP1_2_WOSET 0U
+#define DSITX__MCTL_DPHY_ERR__ERR_CONT_LP1_3_MASK 0x01000000U
+#define DSITX__MCTL_DPHY_ERR__ERR_CONT_LP1_3_SHIFT 24U
+#define DSITX__MCTL_DPHY_ERR__ERR_CONT_LP1_3_WIDTH 1U
+#define DSITX__MCTL_DPHY_ERR__ERR_CONT_LP1_3_WOCLR 0U
+#define DSITX__MCTL_DPHY_ERR__ERR_CONT_LP1_3_WOSET 0U
+#define DSITX__MCTL_DPHY_ERR__ERR_CONT_LP1_4_MASK 0x02000000U
+#define DSITX__MCTL_DPHY_ERR__ERR_CONT_LP1_4_SHIFT 25U
+#define DSITX__MCTL_DPHY_ERR__ERR_CONT_LP1_4_WIDTH 1U
+#define DSITX__MCTL_DPHY_ERR__ERR_CONT_LP1_4_WOCLR 0U
+#define DSITX__MCTL_DPHY_ERR__ERR_CONT_LP1_4_WOSET 0U
+#define DSITX__MCTL_DPHY_ERR__RSVD_1_MASK 0xFC000000U
+#define DSITX__MCTL_DPHY_ERR__RSVD_1_SHIFT 26U
+#define DSITX__MCTL_DPHY_ERR__RSVD_1_WIDTH 6U
+
+#define DSITX__MCTL_LANE_STS_READ_MASK 0xFFFFFFFFU
+#define DSITX__MCTL_LANE_STS_WRITE_MASK 0xFFFFFFFFU
+#define DSITX__MCTL_LANE_STS__CLKLANE_STATE_MASK 0x00000003U
+#define DSITX__MCTL_LANE_STS__CLKLANE_STATE_SHIFT 0U
+#define DSITX__MCTL_LANE_STS__CLKLANE_STATE_WIDTH 2U
+#define DSITX__MCTL_LANE_STS__DATLANE1_STATE_MASK 0x0000001CU
+#define DSITX__MCTL_LANE_STS__DATLANE1_STATE_SHIFT 2U
+#define DSITX__MCTL_LANE_STS__DATLANE1_STATE_WIDTH 3U
+#define DSITX__MCTL_LANE_STS__DATLANE2_STATE_MASK 0x00000060U
+#define DSITX__MCTL_LANE_STS__DATLANE2_STATE_SHIFT 5U
+#define DSITX__MCTL_LANE_STS__DATLANE2_STATE_WIDTH 2U
+#define DSITX__MCTL_LANE_STS__DATLANE3_STATE_MASK 0x00000180U
+#define DSITX__MCTL_LANE_STS__DATLANE3_STATE_SHIFT 7U
+#define DSITX__MCTL_LANE_STS__DATLANE3_STATE_WIDTH 2U
+#define DSITX__MCTL_LANE_STS__DATLANE4_STATE_MASK 0x00000600U
+#define DSITX__MCTL_LANE_STS__DATLANE4_STATE_SHIFT 9U
+#define DSITX__MCTL_LANE_STS__DATLANE4_STATE_WIDTH 2U
+#define DSITX__MCTL_LANE_STS__RSVD_0_MASK 0x00000800U
+#define DSITX__MCTL_LANE_STS__RSVD_0_SHIFT 11U
+#define DSITX__MCTL_LANE_STS__RSVD_0_WIDTH 1U
+#define DSITX__MCTL_LANE_STS__RSVD_0_WOCLR 0U
+#define DSITX__MCTL_LANE_STS__RSVD_0_WOSET 0U
+#define DSITX__MCTL_LANE_STS__PPI_D_RX_ULPS_ESC_MASK 0x0000F000U
+#define DSITX__MCTL_LANE_STS__PPI_D_RX_ULPS_ESC_SHIFT 12U
+#define DSITX__MCTL_LANE_STS__PPI_D_RX_ULPS_ESC_WIDTH 4U
+#define DSITX__MCTL_LANE_STS__RSVD_1_MASK 0x00010000U
+#define DSITX__MCTL_LANE_STS__RSVD_1_SHIFT 16U
+#define DSITX__MCTL_LANE_STS__RSVD_1_WIDTH 1U
+#define DSITX__MCTL_LANE_STS__RSVD_1_WOCLR 0U
+#define DSITX__MCTL_LANE_STS__RSVD_1_WOSET 0U
+#define DSITX__MCTL_LANE_STS__DPHY_PLL_LOCK_MASK 0x00020000U
+#define DSITX__MCTL_LANE_STS__DPHY_PLL_LOCK_SHIFT 17U
+#define DSITX__MCTL_LANE_STS__DPHY_PLL_LOCK_WIDTH 1U
+#define DSITX__MCTL_LANE_STS__DPHY_PLL_LOCK_WOCLR 0U
+#define DSITX__MCTL_LANE_STS__DPHY_PLL_LOCK_WOSET 0U
+#define DSITX__MCTL_LANE_STS__PPI_C_TX_READY_HS_MASK 0x00040000U
+#define DSITX__MCTL_LANE_STS__PPI_C_TX_READY_HS_SHIFT 18U
+#define DSITX__MCTL_LANE_STS__PPI_C_TX_READY_HS_WIDTH 1U
+#define DSITX__MCTL_LANE_STS__PPI_C_TX_READY_HS_WOCLR 0U
+#define DSITX__MCTL_LANE_STS__PPI_C_TX_READY_HS_WOSET 0U
+#define DSITX__MCTL_LANE_STS__RSVD_2_MASK 0xFFF80000U
+#define DSITX__MCTL_LANE_STS__RSVD_2_SHIFT 19U
+#define DSITX__MCTL_LANE_STS__RSVD_2_WIDTH 13U
+
+#define DSITX__DSC_MODE_CTL_READ_MASK 0xFFFFFFFFU
+#define DSITX__DSC_MODE_CTL_WRITE_MASK 0xFFFFFFFFU
+#define DSITX__DSC_MODE_CTL__DSC_MODE_EN_MASK 0x00000001U
+#define DSITX__DSC_MODE_CTL__DSC_MODE_EN_SHIFT 0U
+#define DSITX__DSC_MODE_CTL__DSC_MODE_EN_WIDTH 1U
+#define DSITX__DSC_MODE_CTL__DSC_MODE_EN_WOCLR 0U
+#define DSITX__DSC_MODE_CTL__DSC_MODE_EN_WOSET 0U
+#define DSITX__DSC_MODE_CTL__RSVD_0_MASK 0xFFFFFFFEU
+#define DSITX__DSC_MODE_CTL__RSVD_0_SHIFT 1U
+#define DSITX__DSC_MODE_CTL__RSVD_0_WIDTH 31U
+
+#define DSITX__DSC_CMD_SEND_READ_MASK 0xFFFFFFFCU
+#define DSITX__DSC_CMD_SEND_WRITE_MASK 0xFFFFFFFCU
+#define DSITX__DSC_CMD_SEND__DSC_EXECUTE_QUEUE_MASK 0x00000001U
+#define DSITX__DSC_CMD_SEND__DSC_EXECUTE_QUEUE_SHIFT 0U
+#define DSITX__DSC_CMD_SEND__DSC_EXECUTE_QUEUE_WIDTH 1U
+#define DSITX__DSC_CMD_SEND__DSC_EXECUTE_QUEUE_WOCLR 0U
+#define DSITX__DSC_CMD_SEND__DSC_EXECUTE_QUEUE_WOSET 0U
+#define DSITX__DSC_CMD_SEND__DSC_SEND_PPS_MASK 0x00000002U
+#define DSITX__DSC_CMD_SEND__DSC_SEND_PPS_SHIFT 1U
+#define DSITX__DSC_CMD_SEND__DSC_SEND_PPS_WIDTH 1U
+#define DSITX__DSC_CMD_SEND__DSC_SEND_PPS_WOCLR 0U
+#define DSITX__DSC_CMD_SEND__DSC_SEND_PPS_WOSET 0U
+#define DSITX__DSC_CMD_SEND__RSVD_0_MASK 0xFFFFFFFCU
+#define DSITX__DSC_CMD_SEND__RSVD_0_SHIFT 2U
+#define DSITX__DSC_CMD_SEND__RSVD_0_WIDTH 30U
+
+#define DSITX__DSC_PPS_WRDAT_READ_MASK 0xFFFFFFFFU
+#define DSITX__DSC_PPS_WRDAT_WRITE_MASK 0xFFFFFFFFU
+#define DSITX__DSC_PPS_WRDAT__PPS_WRDAT0_MASK 0x000000FFU
+#define DSITX__DSC_PPS_WRDAT__PPS_WRDAT0_SHIFT 0U
+#define DSITX__DSC_PPS_WRDAT__PPS_WRDAT0_WIDTH 8U
+#define DSITX__DSC_PPS_WRDAT__PPS_WRDAT1_MASK 0x0000FF00U
+#define DSITX__DSC_PPS_WRDAT__PPS_WRDAT1_SHIFT 8U
+#define DSITX__DSC_PPS_WRDAT__PPS_WRDAT1_WIDTH 8U
+#define DSITX__DSC_PPS_WRDAT__PPS_WRDAT2_MASK 0x00FF0000U
+#define DSITX__DSC_PPS_WRDAT__PPS_WRDAT2_SHIFT 16U
+#define DSITX__DSC_PPS_WRDAT__PPS_WRDAT2_WIDTH 8U
+#define DSITX__DSC_PPS_WRDAT__PPS_WRDAT3_MASK 0xFF000000U
+#define DSITX__DSC_PPS_WRDAT__PPS_WRDAT3_SHIFT 24U
+#define DSITX__DSC_PPS_WRDAT__PPS_WRDAT3_WIDTH 8U
+
+#define DSITX__DSC_MODE_STS_READ_MASK 0xFFFFFFFFU
+#define DSITX__DSC_MODE_STS_WRITE_MASK 0xFFFFFFFFU
+#define DSITX__DSC_MODE_STS__DSC_EXEC_DONE_MASK 0x00000001U
+#define DSITX__DSC_MODE_STS__DSC_EXEC_DONE_SHIFT 0U
+#define DSITX__DSC_MODE_STS__DSC_EXEC_DONE_WIDTH 1U
+#define DSITX__DSC_MODE_STS__DSC_EXEC_DONE_WOCLR 0U
+#define DSITX__DSC_MODE_STS__DSC_EXEC_DONE_WOSET 0U
+#define DSITX__DSC_MODE_STS__DSC_PPS_DONE_MASK 0x00000002U
+#define DSITX__DSC_MODE_STS__DSC_PPS_DONE_SHIFT 1U
+#define DSITX__DSC_MODE_STS__DSC_PPS_DONE_WIDTH 1U
+#define DSITX__DSC_MODE_STS__DSC_PPS_DONE_WOCLR 0U
+#define DSITX__DSC_MODE_STS__DSC_PPS_DONE_WOSET 0U
+#define DSITX__DSC_MODE_STS__RSVD_0_MASK 0xFFFFFFFCU
+#define DSITX__DSC_MODE_STS__RSVD_0_SHIFT 2U
+#define DSITX__DSC_MODE_STS__RSVD_0_WIDTH 30U
+
+#define DSITX__MCTL_DPHY_SKEWCAL_TIMEOUT_READ_MASK 0xFFFFFFFFU
+#define DSITX__MCTL_DPHY_SKEWCAL_TIMEOUT_WRITE_MASK 0xFFFFFFFFU
+#define DSITX__MCTL_DPHY_SKEWCAL_TIMEOUT__SKEWCAL_TO_VAL_MASK 0xFFFFFFFFU
+#define DSITX__MCTL_DPHY_SKEWCAL_TIMEOUT__SKEWCAL_TO_VAL_SHIFT 0U
+#define DSITX__MCTL_DPHY_SKEWCAL_TIMEOUT__SKEWCAL_TO_VAL_WIDTH 32U
+
+#define DSITX__CMD_MODE_CTL_READ_MASK 0xFFFFFFFFU
+#define DSITX__CMD_MODE_CTL_WRITE_MASK 0xFFFFFFFFU
+#define DSITX__CMD_MODE_CTL__IF1_ID_MASK 0x00000003U
+#define DSITX__CMD_MODE_CTL__IF1_ID_SHIFT 0U
+#define DSITX__CMD_MODE_CTL__IF1_ID_WIDTH 2U
+#define DSITX__CMD_MODE_CTL__IF3_ID_MASK 0x0000000CU
+#define DSITX__CMD_MODE_CTL__IF3_ID_SHIFT 2U
+#define DSITX__CMD_MODE_CTL__IF3_ID_WIDTH 2U
+#define DSITX__CMD_MODE_CTL__RSVD_0_MASK 0x000001F0U
+#define DSITX__CMD_MODE_CTL__RSVD_0_SHIFT 4U
+#define DSITX__CMD_MODE_CTL__RSVD_0_WIDTH 5U
+#define DSITX__CMD_MODE_CTL__IF1_LP_EN_MASK 0x00000200U
+#define DSITX__CMD_MODE_CTL__IF1_LP_EN_SHIFT 9U
+#define DSITX__CMD_MODE_CTL__IF1_LP_EN_WIDTH 1U
+#define DSITX__CMD_MODE_CTL__IF1_LP_EN_WOCLR 0U
+#define DSITX__CMD_MODE_CTL__IF1_LP_EN_WOSET 0U
+#define DSITX__CMD_MODE_CTL__IF3_LP_EN_MASK 0x00000400U
+#define DSITX__CMD_MODE_CTL__IF3_LP_EN_SHIFT 10U
+#define DSITX__CMD_MODE_CTL__IF3_LP_EN_WIDTH 1U
+#define DSITX__CMD_MODE_CTL__IF3_LP_EN_WOCLR 0U
+#define DSITX__CMD_MODE_CTL__IF3_LP_EN_WOSET 0U
+#define DSITX__CMD_MODE_CTL__RSVD_1_MASK 0xFFFFF800U
+#define DSITX__CMD_MODE_CTL__RSVD_1_SHIFT 11U
+#define DSITX__CMD_MODE_CTL__RSVD_1_WIDTH 21U
+
+#define DSITX__CMD_MODE_CTL2_READ_MASK 0xFFFFFFFFU
+#define DSITX__CMD_MODE_CTL2_WRITE_MASK 0xFFFFFFFFU
+#define DSITX__CMD_MODE_CTL2__ARB_MODE_MASK 0x00000001U
+#define DSITX__CMD_MODE_CTL2__ARB_MODE_SHIFT 0U
+#define DSITX__CMD_MODE_CTL2__ARB_MODE_WIDTH 1U
+#define DSITX__CMD_MODE_CTL2__ARB_MODE_WOCLR 0U
+#define DSITX__CMD_MODE_CTL2__ARB_MODE_WOSET 0U
+#define DSITX__CMD_MODE_CTL2__ARB_PRI_MASK 0x00000006U
+#define DSITX__CMD_MODE_CTL2__ARB_PRI_SHIFT 1U
+#define DSITX__CMD_MODE_CTL2__ARB_PRI_WIDTH 2U
+#define DSITX__CMD_MODE_CTL2__FIL_VALUE_MASK 0x000007F8U
+#define DSITX__CMD_MODE_CTL2__FIL_VALUE_SHIFT 3U
+#define DSITX__CMD_MODE_CTL2__FIL_VALUE_WIDTH 8U
+#define DSITX__CMD_MODE_CTL2__TE_TIMEOUT_MASK 0x007FF800U
+#define DSITX__CMD_MODE_CTL2__TE_TIMEOUT_SHIFT 11U
+#define DSITX__CMD_MODE_CTL2__TE_TIMEOUT_WIDTH 12U
+#define DSITX__CMD_MODE_CTL2__RSVD_0_MASK 0xFF800000U
+#define DSITX__CMD_MODE_CTL2__RSVD_0_SHIFT 23U
+#define DSITX__CMD_MODE_CTL2__RSVD_0_WIDTH 9U
+
+#define DSITX__CMD_MODE_STS_READ_MASK 0xFFFFFFFFU
+#define DSITX__CMD_MODE_STS_WRITE_MASK 0xFFFFFFFFU
+#define DSITX__CMD_MODE_STS__CSM_RUNNING_MASK 0x00000001U
+#define DSITX__CMD_MODE_STS__CSM_RUNNING_SHIFT 0U
+#define DSITX__CMD_MODE_STS__CSM_RUNNING_WIDTH 1U
+#define DSITX__CMD_MODE_STS__CSM_RUNNING_WOCLR 0U
+#define DSITX__CMD_MODE_STS__CSM_RUNNING_WOSET 0U
+#define DSITX__CMD_MODE_STS__ERR_NO_TE_MASK 0x00000002U
+#define DSITX__CMD_MODE_STS__ERR_NO_TE_SHIFT 1U
+#define DSITX__CMD_MODE_STS__ERR_NO_TE_WIDTH 1U
+#define DSITX__CMD_MODE_STS__ERR_NO_TE_WOCLR 0U
+#define DSITX__CMD_MODE_STS__ERR_NO_TE_WOSET 0U
+#define DSITX__CMD_MODE_STS__ERR_TE_MISS_MASK 0x00000004U
+#define DSITX__CMD_MODE_STS__ERR_TE_MISS_SHIFT 2U
+#define DSITX__CMD_MODE_STS__ERR_TE_MISS_WIDTH 1U
+#define DSITX__CMD_MODE_STS__ERR_TE_MISS_WOCLR 0U
+#define DSITX__CMD_MODE_STS__ERR_TE_MISS_WOSET 0U
+#define DSITX__CMD_MODE_STS__ERR_UNWANTED_RD_MASK 0x00000008U
+#define DSITX__CMD_MODE_STS__ERR_UNWANTED_RD_SHIFT 3U
+#define DSITX__CMD_MODE_STS__ERR_UNWANTED_RD_WIDTH 1U
+#define DSITX__CMD_MODE_STS__ERR_UNWANTED_RD_WOCLR 0U
+#define DSITX__CMD_MODE_STS__ERR_UNWANTED_RD_WOSET 0U
+#define DSITX__CMD_MODE_STS__ERR_IF1_UNDERRUN_MASK 0x00000010U
+#define DSITX__CMD_MODE_STS__ERR_IF1_UNDERRUN_SHIFT 4U
+#define DSITX__CMD_MODE_STS__ERR_IF1_UNDERRUN_WIDTH 1U
+#define DSITX__CMD_MODE_STS__ERR_IF1_UNDERRUN_WOCLR 0U
+#define DSITX__CMD_MODE_STS__ERR_IF1_UNDERRUN_WOSET 0U
+#define DSITX__CMD_MODE_STS__RSVD_0_MASK 0xFFFFFFE0U
+#define DSITX__CMD_MODE_STS__RSVD_0_SHIFT 5U
+#define DSITX__CMD_MODE_STS__RSVD_0_WIDTH 27U
+
+#define DSITX__DIRECT_CMD_SEND__DIRECT_CMD_SEND_MASK 0xFFFFFFFFU
+#define DSITX__DIRECT_CMD_SEND__DIRECT_CMD_SEND_SHIFT 0U
+#define DSITX__DIRECT_CMD_SEND__DIRECT_CMD_SEND_WIDTH 32U
+
+#define DSITX__DIRECT_CMD_MAIN_SETTINGS_READ_MASK 0xFFFFFFFFU
+#define DSITX__DIRECT_CMD_MAIN_SETTINGS_WRITE_MASK 0xFFFFFFFFU
+#define DSITX__DIRECT_CMD_MAIN_SETTINGS__CMD_NAT_MASK 0x00000007U
+#define DSITX__DIRECT_CMD_MAIN_SETTINGS__CMD_NAT_SHIFT 0U
+#define DSITX__DIRECT_CMD_MAIN_SETTINGS__CMD_NAT_WIDTH 3U
+#define DSITX__DIRECT_CMD_MAIN_SETTINGS__CMD_LONGNOTSHORT_MASK 0x00000008U
+#define DSITX__DIRECT_CMD_MAIN_SETTINGS__CMD_LONGNOTSHORT_SHIFT 3U
+#define DSITX__DIRECT_CMD_MAIN_SETTINGS__CMD_LONGNOTSHORT_WIDTH 1U
+#define DSITX__DIRECT_CMD_MAIN_SETTINGS__CMD_LONGNOTSHORT_WOCLR 0U
+#define DSITX__DIRECT_CMD_MAIN_SETTINGS__CMD_LONGNOTSHORT_WOSET 0U
+#define DSITX__DIRECT_CMD_MAIN_SETTINGS__RSVD_0_MASK 0x000000F0U
+#define DSITX__DIRECT_CMD_MAIN_SETTINGS__RSVD_0_SHIFT 4U
+#define DSITX__DIRECT_CMD_MAIN_SETTINGS__RSVD_0_WIDTH 4U
+#define DSITX__DIRECT_CMD_MAIN_SETTINGS__CMD_HEAD_MASK 0x00003F00U
+#define DSITX__DIRECT_CMD_MAIN_SETTINGS__CMD_HEAD_SHIFT 8U
+#define DSITX__DIRECT_CMD_MAIN_SETTINGS__CMD_HEAD_WIDTH 6U
+#define DSITX__DIRECT_CMD_MAIN_SETTINGS__CMD_ID_MASK 0x0000C000U
+#define DSITX__DIRECT_CMD_MAIN_SETTINGS__CMD_ID_SHIFT 14U
+#define DSITX__DIRECT_CMD_MAIN_SETTINGS__CMD_ID_WIDTH 2U
+#define DSITX__DIRECT_CMD_MAIN_SETTINGS__CMD_SIZE_MASK 0x00FF0000U
+#define DSITX__DIRECT_CMD_MAIN_SETTINGS__CMD_SIZE_SHIFT 16U
+#define DSITX__DIRECT_CMD_MAIN_SETTINGS__CMD_SIZE_WIDTH 8U
+#define DSITX__DIRECT_CMD_MAIN_SETTINGS__CMD_LP_EN_MASK 0x01000000U
+#define DSITX__DIRECT_CMD_MAIN_SETTINGS__CMD_LP_EN_SHIFT 24U
+#define DSITX__DIRECT_CMD_MAIN_SETTINGS__CMD_LP_EN_WIDTH 1U
+#define DSITX__DIRECT_CMD_MAIN_SETTINGS__CMD_LP_EN_WOCLR 0U
+#define DSITX__DIRECT_CMD_MAIN_SETTINGS__CMD_LP_EN_WOSET 0U
+#define DSITX__DIRECT_CMD_MAIN_SETTINGS__TRIGGER_VAL_MASK 0x1E000000U
+#define DSITX__DIRECT_CMD_MAIN_SETTINGS__TRIGGER_VAL_SHIFT 25U
+#define DSITX__DIRECT_CMD_MAIN_SETTINGS__TRIGGER_VAL_WIDTH 4U
+#define DSITX__DIRECT_CMD_MAIN_SETTINGS__RSVD_1_MASK 0xE0000000U
+#define DSITX__DIRECT_CMD_MAIN_SETTINGS__RSVD_1_SHIFT 29U
+#define DSITX__DIRECT_CMD_MAIN_SETTINGS__RSVD_1_WIDTH 3U
+
+#define DSITX__DIRECT_CMD_STS_READ_MASK 0xFFFFFFFFU
+#define DSITX__DIRECT_CMD_STS_WRITE_MASK 0xFFFFFFFFU
+#define DSITX__DIRECT_CMD_STS__CMD_TRANSMISSION_MASK 0x00000001U
+#define DSITX__DIRECT_CMD_STS__CMD_TRANSMISSION_SHIFT 0U
+#define DSITX__DIRECT_CMD_STS__CMD_TRANSMISSION_WIDTH 1U
+#define DSITX__DIRECT_CMD_STS__CMD_TRANSMISSION_WOCLR 0U
+#define DSITX__DIRECT_CMD_STS__CMD_TRANSMISSION_WOSET 0U
+#define DSITX__DIRECT_CMD_STS__WRITE_COMPLETED_MASK 0x00000002U
+#define DSITX__DIRECT_CMD_STS__WRITE_COMPLETED_SHIFT 1U
+#define DSITX__DIRECT_CMD_STS__WRITE_COMPLETED_WIDTH 1U
+#define DSITX__DIRECT_CMD_STS__WRITE_COMPLETED_WOCLR 0U
+#define DSITX__DIRECT_CMD_STS__WRITE_COMPLETED_WOSET 0U
+#define DSITX__DIRECT_CMD_STS__TRIGGER_COMPLETED_MASK 0x00000004U
+#define DSITX__DIRECT_CMD_STS__TRIGGER_COMPLETED_SHIFT 2U
+#define DSITX__DIRECT_CMD_STS__TRIGGER_COMPLETED_WIDTH 1U
+#define DSITX__DIRECT_CMD_STS__TRIGGER_COMPLETED_WOCLR 0U
+#define DSITX__DIRECT_CMD_STS__TRIGGER_COMPLETED_WOSET 0U
+#define DSITX__DIRECT_CMD_STS__READ_COMPLETED_MASK 0x00000008U
+#define DSITX__DIRECT_CMD_STS__READ_COMPLETED_SHIFT 3U
+#define DSITX__DIRECT_CMD_STS__READ_COMPLETED_WIDTH 1U
+#define DSITX__DIRECT_CMD_STS__READ_COMPLETED_WOCLR 0U
+#define DSITX__DIRECT_CMD_STS__READ_COMPLETED_WOSET 0U
+#define DSITX__DIRECT_CMD_STS__ACK_RECEIVED_MASK 0x00000010U
+#define DSITX__DIRECT_CMD_STS__ACK_RECEIVED_SHIFT 4U
+#define DSITX__DIRECT_CMD_STS__ACK_RECEIVED_WIDTH 1U
+#define DSITX__DIRECT_CMD_STS__ACK_RECEIVED_WOCLR 0U
+#define DSITX__DIRECT_CMD_STS__ACK_RECEIVED_WOSET 0U
+#define DSITX__DIRECT_CMD_STS__ACK_WITH_ERR_RECEIVED_MASK 0x00000020U
+#define DSITX__DIRECT_CMD_STS__ACK_WITH_ERR_RECEIVED_SHIFT 5U
+#define DSITX__DIRECT_CMD_STS__ACK_WITH_ERR_RECEIVED_WIDTH 1U
+#define DSITX__DIRECT_CMD_STS__ACK_WITH_ERR_RECEIVED_WOCLR 0U
+#define DSITX__DIRECT_CMD_STS__ACK_WITH_ERR_RECEIVED_WOSET 0U
+#define DSITX__DIRECT_CMD_STS__TRIGGER_RECEIVED_MASK 0x00000040U
+#define DSITX__DIRECT_CMD_STS__TRIGGER_RECEIVED_SHIFT 6U
+#define DSITX__DIRECT_CMD_STS__TRIGGER_RECEIVED_WIDTH 1U
+#define DSITX__DIRECT_CMD_STS__TRIGGER_RECEIVED_WOCLR 0U
+#define DSITX__DIRECT_CMD_STS__TRIGGER_RECEIVED_WOSET 0U
+#define DSITX__DIRECT_CMD_STS__TE_RECEIVED_MASK 0x00000080U
+#define DSITX__DIRECT_CMD_STS__TE_RECEIVED_SHIFT 7U
+#define DSITX__DIRECT_CMD_STS__TE_RECEIVED_WIDTH 1U
+#define DSITX__DIRECT_CMD_STS__TE_RECEIVED_WOCLR 0U
+#define DSITX__DIRECT_CMD_STS__TE_RECEIVED_WOSET 0U
+#define DSITX__DIRECT_CMD_STS__BTA_COMPLETED_MASK 0x00000100U
+#define DSITX__DIRECT_CMD_STS__BTA_COMPLETED_SHIFT 8U
+#define DSITX__DIRECT_CMD_STS__BTA_COMPLETED_WIDTH 1U
+#define DSITX__DIRECT_CMD_STS__BTA_COMPLETED_WOCLR 0U
+#define DSITX__DIRECT_CMD_STS__BTA_COMPLETED_WOSET 0U
+#define DSITX__DIRECT_CMD_STS__BTA_FINISHED_MASK 0x00000200U
+#define DSITX__DIRECT_CMD_STS__BTA_FINISHED_SHIFT 9U
+#define DSITX__DIRECT_CMD_STS__BTA_FINISHED_WIDTH 1U
+#define DSITX__DIRECT_CMD_STS__BTA_FINISHED_WOCLR 0U
+#define DSITX__DIRECT_CMD_STS__BTA_FINISHED_WOSET 0U
+#define DSITX__DIRECT_CMD_STS__READ_COMPLETED_WITH_ERR_MASK 0x00000400U
+#define DSITX__DIRECT_CMD_STS__READ_COMPLETED_WITH_ERR_SHIFT 10U
+#define DSITX__DIRECT_CMD_STS__READ_COMPLETED_WITH_ERR_WIDTH 1U
+#define DSITX__DIRECT_CMD_STS__READ_COMPLETED_WITH_ERR_WOCLR 0U
+#define DSITX__DIRECT_CMD_STS__READ_COMPLETED_WITH_ERR_WOSET 0U
+#define DSITX__DIRECT_CMD_STS__TRIGGER_VAL_MASK 0x00007800U
+#define DSITX__DIRECT_CMD_STS__TRIGGER_VAL_SHIFT 11U
+#define DSITX__DIRECT_CMD_STS__TRIGGER_VAL_WIDTH 4U
+#define DSITX__DIRECT_CMD_STS__RSVD_0_MASK 0x00008000U
+#define DSITX__DIRECT_CMD_STS__RSVD_0_SHIFT 15U
+#define DSITX__DIRECT_CMD_STS__RSVD_0_WIDTH 1U
+#define DSITX__DIRECT_CMD_STS__RSVD_0_WOCLR 0U
+#define DSITX__DIRECT_CMD_STS__RSVD_0_WOSET 0U
+#define DSITX__DIRECT_CMD_STS__ACK_VAL_MASK 0xFFFF0000U
+#define DSITX__DIRECT_CMD_STS__ACK_VAL_SHIFT 16U
+#define DSITX__DIRECT_CMD_STS__ACK_VAL_WIDTH 16U
+
+#define DSITX__DIRECT_CMD_RD_INIT__STOP_READ_OPERATION_MASK 0xFFFFFFFFU
+#define DSITX__DIRECT_CMD_RD_INIT__STOP_READ_OPERATION_SHIFT 0U
+#define DSITX__DIRECT_CMD_RD_INIT__STOP_READ_OPERATION_WIDTH 32U
+
+#define DSITX__DIRECT_CMD_WRDAT_READ_MASK 0xFFFFFFFFU
+#define DSITX__DIRECT_CMD_WRDAT_WRITE_MASK 0xFFFFFFFFU
+#define DSITX__DIRECT_CMD_WRDAT__WRDAT0_MASK 0x000000FFU
+#define DSITX__DIRECT_CMD_WRDAT__WRDAT0_SHIFT 0U
+#define DSITX__DIRECT_CMD_WRDAT__WRDAT0_WIDTH 8U
+#define DSITX__DIRECT_CMD_WRDAT__WRDAT1_MASK 0x0000FF00U
+#define DSITX__DIRECT_CMD_WRDAT__WRDAT1_SHIFT 8U
+#define DSITX__DIRECT_CMD_WRDAT__WRDAT1_WIDTH 8U
+#define DSITX__DIRECT_CMD_WRDAT__WRDAT2_MASK 0x00FF0000U
+#define DSITX__DIRECT_CMD_WRDAT__WRDAT2_SHIFT 16U
+#define DSITX__DIRECT_CMD_WRDAT__WRDAT2_WIDTH 8U
+#define DSITX__DIRECT_CMD_WRDAT__WRDAT3_MASK 0xFF000000U
+#define DSITX__DIRECT_CMD_WRDAT__WRDAT3_SHIFT 24U
+#define DSITX__DIRECT_CMD_WRDAT__WRDAT3_WIDTH 8U
+
+#define DSITX__DIRECT_CMD_FIFO_RST__CMD_FIFO_RST_MASK 0xFFFFFFFFU
+#define DSITX__DIRECT_CMD_FIFO_RST__CMD_FIFO_RST_SHIFT 0U
+#define DSITX__DIRECT_CMD_FIFO_RST__CMD_FIFO_RST_WIDTH 32U
+
+#define DSITX__DIRECT_CMD_RDDAT_READ_MASK 0xFFFFFFFFU
+#define DSITX__DIRECT_CMD_RDDAT_WRITE_MASK 0xFFFFFFFFU
+#define DSITX__DIRECT_CMD_RDDAT__RDDAT0_MASK 0x000000FFU
+#define DSITX__DIRECT_CMD_RDDAT__RDDAT0_SHIFT 0U
+#define DSITX__DIRECT_CMD_RDDAT__RDDAT0_WIDTH 8U
+#define DSITX__DIRECT_CMD_RDDAT__RDDAT1_MASK 0x0000FF00U
+#define DSITX__DIRECT_CMD_RDDAT__RDDAT1_SHIFT 8U
+#define DSITX__DIRECT_CMD_RDDAT__RDDAT1_WIDTH 8U
+#define DSITX__DIRECT_CMD_RDDAT__RDDAT2_MASK 0x00FF0000U
+#define DSITX__DIRECT_CMD_RDDAT__RDDAT2_SHIFT 16U
+#define DSITX__DIRECT_CMD_RDDAT__RDDAT2_WIDTH 8U
+#define DSITX__DIRECT_CMD_RDDAT__RDDAT3_MASK 0xFF000000U
+#define DSITX__DIRECT_CMD_RDDAT__RDDAT3_SHIFT 24U
+#define DSITX__DIRECT_CMD_RDDAT__RDDAT3_WIDTH 8U
+
+#define DSITX__DIRECT_CMD_RD_PROPERTY_READ_MASK 0xFFFFFFFFU
+#define DSITX__DIRECT_CMD_RD_PROPERTY_WRITE_MASK 0xFFFFFFFFU
+#define DSITX__DIRECT_CMD_RD_PROPERTY__RD_SIZE_MASK 0x0000FFFFU
+#define DSITX__DIRECT_CMD_RD_PROPERTY__RD_SIZE_SHIFT 0U
+#define DSITX__DIRECT_CMD_RD_PROPERTY__RD_SIZE_WIDTH 16U
+#define DSITX__DIRECT_CMD_RD_PROPERTY__RD_ID_MASK 0x00030000U
+#define DSITX__DIRECT_CMD_RD_PROPERTY__RD_ID_SHIFT 16U
+#define DSITX__DIRECT_CMD_RD_PROPERTY__RD_ID_WIDTH 2U
+#define DSITX__DIRECT_CMD_RD_PROPERTY__RD_DCSNOTGENERIC_MASK 0x00040000U
+#define DSITX__DIRECT_CMD_RD_PROPERTY__RD_DCSNOTGENERIC_SHIFT 18U
+#define DSITX__DIRECT_CMD_RD_PROPERTY__RD_DCSNOTGENERIC_WIDTH 1U
+#define DSITX__DIRECT_CMD_RD_PROPERTY__RD_DCSNOTGENERIC_WOCLR 0U
+#define DSITX__DIRECT_CMD_RD_PROPERTY__RD_DCSNOTGENERIC_WOSET 0U
+#define DSITX__DIRECT_CMD_RD_PROPERTY__RSVD_0_MASK 0xFFF80000U
+#define DSITX__DIRECT_CMD_RD_PROPERTY__RSVD_0_SHIFT 19U
+#define DSITX__DIRECT_CMD_RD_PROPERTY__RSVD_0_WIDTH 13U
+
+#define DSITX__DIRECT_CMD_RD_STS_READ_MASK 0xFFFFFFFFU
+#define DSITX__DIRECT_CMD_RD_STS_WRITE_MASK 0xFFFFFFFFU
+#define DSITX__DIRECT_CMD_RD_STS__ERR_FIXED_MASK 0x00000001U
+#define DSITX__DIRECT_CMD_RD_STS__ERR_FIXED_SHIFT 0U
+#define DSITX__DIRECT_CMD_RD_STS__ERR_FIXED_WIDTH 1U
+#define DSITX__DIRECT_CMD_RD_STS__ERR_FIXED_WOCLR 0U
+#define DSITX__DIRECT_CMD_RD_STS__ERR_FIXED_WOSET 0U
+#define DSITX__DIRECT_CMD_RD_STS__ERR_UNCORRECTABLE_MASK 0x00000002U
+#define DSITX__DIRECT_CMD_RD_STS__ERR_UNCORRECTABLE_SHIFT 1U
+#define DSITX__DIRECT_CMD_RD_STS__ERR_UNCORRECTABLE_WIDTH 1U
+#define DSITX__DIRECT_CMD_RD_STS__ERR_UNCORRECTABLE_WOCLR 0U
+#define DSITX__DIRECT_CMD_RD_STS__ERR_UNCORRECTABLE_WOSET 0U
+#define DSITX__DIRECT_CMD_RD_STS__ERR_CHECKSUM_MASK 0x00000004U
+#define DSITX__DIRECT_CMD_RD_STS__ERR_CHECKSUM_SHIFT 2U
+#define DSITX__DIRECT_CMD_RD_STS__ERR_CHECKSUM_WIDTH 1U
+#define DSITX__DIRECT_CMD_RD_STS__ERR_CHECKSUM_WOCLR 0U
+#define DSITX__DIRECT_CMD_RD_STS__ERR_CHECKSUM_WOSET 0U
+#define DSITX__DIRECT_CMD_RD_STS__ERR_UNDECODABLE_MASK 0x00000008U
+#define DSITX__DIRECT_CMD_RD_STS__ERR_UNDECODABLE_SHIFT 3U
+#define DSITX__DIRECT_CMD_RD_STS__ERR_UNDECODABLE_WIDTH 1U
+#define DSITX__DIRECT_CMD_RD_STS__ERR_UNDECODABLE_WOCLR 0U
+#define DSITX__DIRECT_CMD_RD_STS__ERR_UNDECODABLE_WOSET 0U
+#define DSITX__DIRECT_CMD_RD_STS__ERR_RECEIVE_MASK 0x00000010U
+#define DSITX__DIRECT_CMD_RD_STS__ERR_RECEIVE_SHIFT 4U
+#define DSITX__DIRECT_CMD_RD_STS__ERR_RECEIVE_WIDTH 1U
+#define DSITX__DIRECT_CMD_RD_STS__ERR_RECEIVE_WOCLR 0U
+#define DSITX__DIRECT_CMD_RD_STS__ERR_RECEIVE_WOSET 0U
+#define DSITX__DIRECT_CMD_RD_STS__ERR_OVERSIZE_MASK 0x00000020U
+#define DSITX__DIRECT_CMD_RD_STS__ERR_OVERSIZE_SHIFT 5U
+#define DSITX__DIRECT_CMD_RD_STS__ERR_OVERSIZE_WIDTH 1U
+#define DSITX__DIRECT_CMD_RD_STS__ERR_OVERSIZE_WOCLR 0U
+#define DSITX__DIRECT_CMD_RD_STS__ERR_OVERSIZE_WOSET 0U
+#define DSITX__DIRECT_CMD_RD_STS__ERR_WRONG_LENGTH_MASK 0x00000040U
+#define DSITX__DIRECT_CMD_RD_STS__ERR_WRONG_LENGTH_SHIFT 6U
+#define DSITX__DIRECT_CMD_RD_STS__ERR_WRONG_LENGTH_WIDTH 1U
+#define DSITX__DIRECT_CMD_RD_STS__ERR_WRONG_LENGTH_WOCLR 0U
+#define DSITX__DIRECT_CMD_RD_STS__ERR_WRONG_LENGTH_WOSET 0U
+#define DSITX__DIRECT_CMD_RD_STS__ERR_MISSING_EOT_MASK 0x00000080U
+#define DSITX__DIRECT_CMD_RD_STS__ERR_MISSING_EOT_SHIFT 7U
+#define DSITX__DIRECT_CMD_RD_STS__ERR_MISSING_EOT_WIDTH 1U
+#define DSITX__DIRECT_CMD_RD_STS__ERR_MISSING_EOT_WOCLR 0U
+#define DSITX__DIRECT_CMD_RD_STS__ERR_MISSING_EOT_WOSET 0U
+#define DSITX__DIRECT_CMD_RD_STS__ERR_EOT_WITH_ERR_MASK 0x00000100U
+#define DSITX__DIRECT_CMD_RD_STS__ERR_EOT_WITH_ERR_SHIFT 8U
+#define DSITX__DIRECT_CMD_RD_STS__ERR_EOT_WITH_ERR_WIDTH 1U
+#define DSITX__DIRECT_CMD_RD_STS__ERR_EOT_WITH_ERR_WOCLR 0U
+#define DSITX__DIRECT_CMD_RD_STS__ERR_EOT_WITH_ERR_WOSET 0U
+#define DSITX__DIRECT_CMD_RD_STS__RSVD_0_MASK 0xFFFFFE00U
+#define DSITX__DIRECT_CMD_RD_STS__RSVD_0_SHIFT 9U
+#define DSITX__DIRECT_CMD_RD_STS__RSVD_0_WIDTH 23U
+
+#define DSITX__VID_MAIN_CTL_READ_MASK 0xFFFFFFFFU
+#define DSITX__VID_MAIN_CTL_WRITE_MASK 0xFFFFFFFFU
+#define DSITX__VID_MAIN_CTL__START_MODE_MASK 0x00000003U
+#define DSITX__VID_MAIN_CTL__START_MODE_SHIFT 0U
+#define DSITX__VID_MAIN_CTL__START_MODE_WIDTH 2U
+#define DSITX__VID_MAIN_CTL__STOP_MODE_MASK 0x0000000CU
+#define DSITX__VID_MAIN_CTL__STOP_MODE_SHIFT 2U
+#define DSITX__VID_MAIN_CTL__STOP_MODE_WIDTH 2U
+#define DSITX__VID_MAIN_CTL__VID_ID_MASK 0x00000030U
+#define DSITX__VID_MAIN_CTL__VID_ID_SHIFT 4U
+#define DSITX__VID_MAIN_CTL__VID_ID_WIDTH 2U
+#define DSITX__VID_MAIN_CTL__VID_ID_SDFD_MASK 0x000000C0U
+#define DSITX__VID_MAIN_CTL__VID_ID_SDFD_SHIFT 6U
+#define DSITX__VID_MAIN_CTL__VID_ID_SDFD_WIDTH 2U
+#define DSITX__VID_MAIN_CTL__HEADER_MASK 0x00003F00U
+#define DSITX__VID_MAIN_CTL__HEADER_SHIFT 8U
+#define DSITX__VID_MAIN_CTL__HEADER_WIDTH 6U
+#define DSITX__VID_MAIN_CTL__VID_PIXEL_MODE_MASK 0x0003C000U
+#define DSITX__VID_MAIN_CTL__VID_PIXEL_MODE_SHIFT 14U
+#define DSITX__VID_MAIN_CTL__VID_PIXEL_MODE_WIDTH 4U
+#define DSITX__VID_MAIN_CTL__BURST_MODE_MASK 0x00040000U
+#define DSITX__VID_MAIN_CTL__BURST_MODE_SHIFT 18U
+#define DSITX__VID_MAIN_CTL__BURST_MODE_WIDTH 1U
+#define DSITX__VID_MAIN_CTL__BURST_MODE_WOCLR 0U
+#define DSITX__VID_MAIN_CTL__BURST_MODE_WOSET 0U
+#define DSITX__VID_MAIN_CTL__SYNC_PULSE_ACTIVE_MASK 0x00080000U
+#define DSITX__VID_MAIN_CTL__SYNC_PULSE_ACTIVE_SHIFT 19U
+#define DSITX__VID_MAIN_CTL__SYNC_PULSE_ACTIVE_WIDTH 1U
+#define DSITX__VID_MAIN_CTL__SYNC_PULSE_ACTIVE_WOCLR 0U
+#define DSITX__VID_MAIN_CTL__SYNC_PULSE_ACTIVE_WOSET 0U
+#define DSITX__VID_MAIN_CTL__SYNC_PULSE_HORIZONTAL_MASK 0x00100000U
+#define DSITX__VID_MAIN_CTL__SYNC_PULSE_HORIZONTAL_SHIFT 20U
+#define DSITX__VID_MAIN_CTL__SYNC_PULSE_HORIZONTAL_WIDTH 1U
+#define DSITX__VID_MAIN_CTL__SYNC_PULSE_HORIZONTAL_WOCLR 0U
+#define DSITX__VID_MAIN_CTL__SYNC_PULSE_HORIZONTAL_WOSET 0U
+#define DSITX__VID_MAIN_CTL__REG_BLKLINE_MODE_MASK 0x00600000U
+#define DSITX__VID_MAIN_CTL__REG_BLKLINE_MODE_SHIFT 21U
+#define DSITX__VID_MAIN_CTL__REG_BLKLINE_MODE_WIDTH 2U
+#define DSITX__VID_MAIN_CTL__REG_BLKEOL_MODE_MASK 0x01800000U
+#define DSITX__VID_MAIN_CTL__REG_BLKEOL_MODE_SHIFT 23U
+#define DSITX__VID_MAIN_CTL__REG_BLKEOL_MODE_WIDTH 2U
+#define DSITX__VID_MAIN_CTL__RECOVERY_MODE_MASK 0x06000000U
+#define DSITX__VID_MAIN_CTL__RECOVERY_MODE_SHIFT 25U
+#define DSITX__VID_MAIN_CTL__RECOVERY_MODE_WIDTH 2U
+#define DSITX__VID_MAIN_CTL__VID_INTERLACED_EN_MASK 0x08000000U
+#define DSITX__VID_MAIN_CTL__VID_INTERLACED_EN_SHIFT 27U
+#define DSITX__VID_MAIN_CTL__VID_INTERLACED_EN_WIDTH 1U
+#define DSITX__VID_MAIN_CTL__VID_INTERLACED_EN_WOCLR 0U
+#define DSITX__VID_MAIN_CTL__VID_INTERLACED_EN_WOSET 0U
+#define DSITX__VID_MAIN_CTL__VID_FIELD_SW_MASK 0x10000000U
+#define DSITX__VID_MAIN_CTL__VID_FIELD_SW_SHIFT 28U
+#define DSITX__VID_MAIN_CTL__VID_FIELD_SW_WIDTH 1U
+#define DSITX__VID_MAIN_CTL__VID_FIELD_SW_WOCLR 0U
+#define DSITX__VID_MAIN_CTL__VID_FIELD_SW_WOSET 0U
+#define DSITX__VID_MAIN_CTL__RSVD_0_MASK 0x60000000U
+#define DSITX__VID_MAIN_CTL__RSVD_0_SHIFT 29U
+#define DSITX__VID_MAIN_CTL__RSVD_0_WIDTH 2U
+#define DSITX__VID_MAIN_CTL__VID_IGNORE_MISS_VSYNC_MASK 0x80000000U
+#define DSITX__VID_MAIN_CTL__VID_IGNORE_MISS_VSYNC_SHIFT 31U
+#define DSITX__VID_MAIN_CTL__VID_IGNORE_MISS_VSYNC_WIDTH 1U
+#define DSITX__VID_MAIN_CTL__VID_IGNORE_MISS_VSYNC_WOCLR 0U
+#define DSITX__VID_MAIN_CTL__VID_IGNORE_MISS_VSYNC_WOSET 0U
+
+#define DSITX__VID_VSIZE1_READ_MASK 0xFFFFFFFFU
+#define DSITX__VID_VSIZE1_WRITE_MASK 0xFFFFFFFFU
+#define DSITX__VID_VSIZE1__VSA_LENGTH_MASK 0x0000003FU
+#define DSITX__VID_VSIZE1__VSA_LENGTH_SHIFT 0U
+#define DSITX__VID_VSIZE1__VSA_LENGTH_WIDTH 6U
+#define DSITX__VID_VSIZE1__VBP_LENGTH_MASK 0x00000FC0U
+#define DSITX__VID_VSIZE1__VBP_LENGTH_SHIFT 6U
+#define DSITX__VID_VSIZE1__VBP_LENGTH_WIDTH 6U
+#define DSITX__VID_VSIZE1__VFP_LENGTH_MASK 0x000FF000U
+#define DSITX__VID_VSIZE1__VFP_LENGTH_SHIFT 12U
+#define DSITX__VID_VSIZE1__VFP_LENGTH_WIDTH 8U
+#define DSITX__VID_VSIZE1__RSVD_0_MASK 0xFFF00000U
+#define DSITX__VID_VSIZE1__RSVD_0_SHIFT 20U
+#define DSITX__VID_VSIZE1__RSVD_0_WIDTH 12U
+
+#define DSITX__VID_VSIZE2_READ_MASK 0xFFFFFFFFU
+#define DSITX__VID_VSIZE2_WRITE_MASK 0xFFFFFFFFU
+#define DSITX__VID_VSIZE2__VACT_LENGTH_MASK 0x00001FFFU
+#define DSITX__VID_VSIZE2__VACT_LENGTH_SHIFT 0U
+#define DSITX__VID_VSIZE2__VACT_LENGTH_WIDTH 13U
+#define DSITX__VID_VSIZE2__RSVD_0_MASK 0xFFFFE000U
+#define DSITX__VID_VSIZE2__RSVD_0_SHIFT 13U
+#define DSITX__VID_VSIZE2__RSVD_0_WIDTH 19U
+
+#define DSITX__VID_HSIZE1_READ_MASK 0xFFFFFFFFU
+#define DSITX__VID_HSIZE1_WRITE_MASK 0xFFFFFFFFU
+#define DSITX__VID_HSIZE1__HSA_LENGTH_MASK 0x000003FFU
+#define DSITX__VID_HSIZE1__HSA_LENGTH_SHIFT 0U
+#define DSITX__VID_HSIZE1__HSA_LENGTH_WIDTH 10U
+#define DSITX__VID_HSIZE1__RSVD_0_MASK 0x0000FC00U
+#define DSITX__VID_HSIZE1__RSVD_0_SHIFT 10U
+#define DSITX__VID_HSIZE1__RSVD_0_WIDTH 6U
+#define DSITX__VID_HSIZE1__HBP_LENGTH_MASK 0xFFFF0000U
+#define DSITX__VID_HSIZE1__HBP_LENGTH_SHIFT 16U
+#define DSITX__VID_HSIZE1__HBP_LENGTH_WIDTH 16U
+
+#define DSITX__VID_HSIZE2_READ_MASK 0xFFFFFFFFU
+#define DSITX__VID_HSIZE2_WRITE_MASK 0xFFFFFFFFU
+#define DSITX__VID_HSIZE2__RGB_SIZE_MASK 0x00007FFFU
+#define DSITX__VID_HSIZE2__RGB_SIZE_SHIFT 0U
+#define DSITX__VID_HSIZE2__RGB_SIZE_WIDTH 15U
+#define DSITX__VID_HSIZE2__RSVD_0_MASK 0x00008000U
+#define DSITX__VID_HSIZE2__RSVD_0_SHIFT 15U
+#define DSITX__VID_HSIZE2__RSVD_0_WIDTH 1U
+#define DSITX__VID_HSIZE2__RSVD_0_WOCLR 0U
+#define DSITX__VID_HSIZE2__RSVD_0_WOSET 0U
+#define DSITX__VID_HSIZE2__HFP_LENGTH_MASK 0x07FF0000U
+#define DSITX__VID_HSIZE2__HFP_LENGTH_SHIFT 16U
+#define DSITX__VID_HSIZE2__HFP_LENGTH_WIDTH 11U
+#define DSITX__VID_HSIZE2__RSVD_1_MASK 0xF8000000U
+#define DSITX__VID_HSIZE2__RSVD_1_SHIFT 27U
+#define DSITX__VID_HSIZE2__RSVD_1_WIDTH 5U
+
+#define DSITX__VID_BLKSIZE1_READ_MASK 0xFFFFFFFFU
+#define DSITX__VID_BLKSIZE1_WRITE_MASK 0xFFFFFFFFU
+#define DSITX__VID_BLKSIZE1__BLKLINE_EVENT_PCK_MASK 0x00007FFFU
+#define DSITX__VID_BLKSIZE1__BLKLINE_EVENT_PCK_SHIFT 0U
+#define DSITX__VID_BLKSIZE1__BLKLINE_EVENT_PCK_WIDTH 15U
+#define DSITX__VID_BLKSIZE1__BLKEOL_PCK_MASK 0x3FFF8000U
+#define DSITX__VID_BLKSIZE1__BLKEOL_PCK_SHIFT 15U
+#define DSITX__VID_BLKSIZE1__BLKEOL_PCK_WIDTH 15U
+#define DSITX__VID_BLKSIZE1__RSVD_0_MASK 0xC0000000U
+#define DSITX__VID_BLKSIZE1__RSVD_0_SHIFT 30U
+#define DSITX__VID_BLKSIZE1__RSVD_0_WIDTH 2U
+
+#define DSITX__VID_BLKSIZE2_READ_MASK 0xFFFFFFFFU
+#define DSITX__VID_BLKSIZE2_WRITE_MASK 0xFFFFFFFFU
+#define DSITX__VID_BLKSIZE2__BLKLINE_PULSE_PCK_MASK 0x00007FFFU
+#define DSITX__VID_BLKSIZE2__BLKLINE_PULSE_PCK_SHIFT 0U
+#define DSITX__VID_BLKSIZE2__BLKLINE_PULSE_PCK_WIDTH 15U
+#define DSITX__VID_BLKSIZE2__RSVD_0_MASK 0xFFFF8000U
+#define DSITX__VID_BLKSIZE2__RSVD_0_SHIFT 15U
+#define DSITX__VID_BLKSIZE2__RSVD_0_WIDTH 17U
+
+#define DSITX__VID_PCK_TIME_READ_MASK 0xFFFFFFFFU
+#define DSITX__VID_PCK_TIME_WRITE_MASK 0xFFFFFFFFU
+#define DSITX__VID_PCK_TIME__BLKEOL_DURATION_MASK 0x00007FFFU
+#define DSITX__VID_PCK_TIME__BLKEOL_DURATION_SHIFT 0U
+#define DSITX__VID_PCK_TIME__BLKEOL_DURATION_WIDTH 15U
+#define DSITX__VID_PCK_TIME__RSVD_0_MASK 0xFFFF8000U
+#define DSITX__VID_PCK_TIME__RSVD_0_SHIFT 15U
+#define DSITX__VID_PCK_TIME__RSVD_0_WIDTH 17U
+
+#define DSITX__VID_DPHY_TIME_READ_MASK 0xFFFFFFFFU
+#define DSITX__VID_DPHY_TIME_WRITE_MASK 0xFFFFFFFFU
+#define DSITX__VID_DPHY_TIME__REG_LINE_DURATION_MASK 0x0001FFFFU
+#define DSITX__VID_DPHY_TIME__REG_LINE_DURATION_SHIFT 0U
+#define DSITX__VID_DPHY_TIME__REG_LINE_DURATION_WIDTH 17U
+#define DSITX__VID_DPHY_TIME__REG_WAKEUP_TIME_MASK 0x0FFE0000U
+#define DSITX__VID_DPHY_TIME__REG_WAKEUP_TIME_SHIFT 17U
+#define DSITX__VID_DPHY_TIME__REG_WAKEUP_TIME_WIDTH 11U
+#define DSITX__VID_DPHY_TIME__RSVD_0_MASK 0xF0000000U
+#define DSITX__VID_DPHY_TIME__RSVD_0_SHIFT 28U
+#define DSITX__VID_DPHY_TIME__RSVD_0_WIDTH 4U
+
+#define DSITX__VID_ERR_COLOR1_READ_MASK 0xFFFFFFFFU
+#define DSITX__VID_ERR_COLOR1_WRITE_MASK 0xFFFFFFFFU
+#define DSITX__VID_ERR_COLOR1__COL_RED_MASK 0x00000FFFU
+#define DSITX__VID_ERR_COLOR1__COL_RED_SHIFT 0U
+#define DSITX__VID_ERR_COLOR1__COL_RED_WIDTH 12U
+#define DSITX__VID_ERR_COLOR1__COL_GREEN_MASK 0x00FFF000U
+#define DSITX__VID_ERR_COLOR1__COL_GREEN_SHIFT 12U
+#define DSITX__VID_ERR_COLOR1__COL_GREEN_WIDTH 12U
+#define DSITX__VID_ERR_COLOR1__RSVD_0_MASK 0xFF000000U
+#define DSITX__VID_ERR_COLOR1__RSVD_0_SHIFT 24U
+#define DSITX__VID_ERR_COLOR1__RSVD_0_WIDTH 8U
+
+#define DSITX__VID_ERR_COLOR2_READ_MASK 0xFFFFFFFFU
+#define DSITX__VID_ERR_COLOR2_WRITE_MASK 0xFFFFFFFFU
+#define DSITX__VID_ERR_COLOR2__COL_BLUE_MASK 0x00000FFFU
+#define DSITX__VID_ERR_COLOR2__COL_BLUE_SHIFT 0U
+#define DSITX__VID_ERR_COLOR2__COL_BLUE_WIDTH 12U
+#define DSITX__VID_ERR_COLOR2__PAD_VALUE_MASK 0x00FFF000U
+#define DSITX__VID_ERR_COLOR2__PAD_VALUE_SHIFT 12U
+#define DSITX__VID_ERR_COLOR2__PAD_VALUE_WIDTH 12U
+#define DSITX__VID_ERR_COLOR2__RSVD_0_MASK 0xFF000000U
+#define DSITX__VID_ERR_COLOR2__RSVD_0_SHIFT 24U
+#define DSITX__VID_ERR_COLOR2__RSVD_0_WIDTH 8U
+
+#define DSITX__VID_VPOS_READ_MASK 0xFFFFFFFFU
+#define DSITX__VID_VPOS_WRITE_MASK 0xFFFFFFFFU
+#define DSITX__VID_VPOS__LINE_POS_MASK 0x00000003U
+#define DSITX__VID_VPOS__LINE_POS_SHIFT 0U
+#define DSITX__VID_VPOS__LINE_POS_WIDTH 2U
+#define DSITX__VID_VPOS__LINE_VAL_MASK 0x00007FFCU
+#define DSITX__VID_VPOS__LINE_VAL_SHIFT 2U
+#define DSITX__VID_VPOS__LINE_VAL_WIDTH 13U
+#define DSITX__VID_VPOS__RSVD_0_MASK 0xFFFF8000U
+#define DSITX__VID_VPOS__RSVD_0_SHIFT 15U
+#define DSITX__VID_VPOS__RSVD_0_WIDTH 17U
+
+#define DSITX__VID_HPOS_READ_MASK 0xFFFFFFFFU
+#define DSITX__VID_HPOS_WRITE_MASK 0xFFFFFFFFU
+#define DSITX__VID_HPOS__HORIZONTAL_POS_MASK 0x00000007U
+#define DSITX__VID_HPOS__HORIZONTAL_POS_SHIFT 0U
+#define DSITX__VID_HPOS__HORIZONTAL_POS_WIDTH 3U
+#define DSITX__VID_HPOS__HORIZONTAL_VAL_MASK 0x0003FFF8U
+#define DSITX__VID_HPOS__HORIZONTAL_VAL_SHIFT 3U
+#define DSITX__VID_HPOS__HORIZONTAL_VAL_WIDTH 15U
+#define DSITX__VID_HPOS__RSVD_0_MASK 0xFFFC0000U
+#define DSITX__VID_HPOS__RSVD_0_SHIFT 18U
+#define DSITX__VID_HPOS__RSVD_0_WIDTH 14U
+
+#define DSITX__VID_MODE_STS_READ_MASK 0xFFFFFFFFU
+#define DSITX__VID_MODE_STS_WRITE_MASK 0xFFFFFFFFU
+#define DSITX__VID_MODE_STS__VSG_RUNNING_MASK 0x00000001U
+#define DSITX__VID_MODE_STS__VSG_RUNNING_SHIFT 0U
+#define DSITX__VID_MODE_STS__VSG_RUNNING_WIDTH 1U
+#define DSITX__VID_MODE_STS__VSG_RUNNING_WOCLR 0U
+#define DSITX__VID_MODE_STS__VSG_RUNNING_WOSET 0U
+#define DSITX__VID_MODE_STS__ERR_MISSING_DATA_MASK 0x00000002U
+#define DSITX__VID_MODE_STS__ERR_MISSING_DATA_SHIFT 1U
+#define DSITX__VID_MODE_STS__ERR_MISSING_DATA_WIDTH 1U
+#define DSITX__VID_MODE_STS__ERR_MISSING_DATA_WOCLR 0U
+#define DSITX__VID_MODE_STS__ERR_MISSING_DATA_WOSET 0U
+#define DSITX__VID_MODE_STS__ERR_MISSING_HSYNC_MASK 0x00000004U
+#define DSITX__VID_MODE_STS__ERR_MISSING_HSYNC_SHIFT 2U
+#define DSITX__VID_MODE_STS__ERR_MISSING_HSYNC_WIDTH 1U
+#define DSITX__VID_MODE_STS__ERR_MISSING_HSYNC_WOCLR 0U
+#define DSITX__VID_MODE_STS__ERR_MISSING_HSYNC_WOSET 0U
+#define DSITX__VID_MODE_STS__ERR_MISSING_VSYNC_MASK 0x00000008U
+#define DSITX__VID_MODE_STS__ERR_MISSING_VSYNC_SHIFT 3U
+#define DSITX__VID_MODE_STS__ERR_MISSING_VSYNC_WIDTH 1U
+#define DSITX__VID_MODE_STS__ERR_MISSING_VSYNC_WOCLR 0U
+#define DSITX__VID_MODE_STS__ERR_MISSING_VSYNC_WOSET 0U
+#define DSITX__VID_MODE_STS__REG_ERR_SMALL_LENGTH_MASK 0x00000010U
+#define DSITX__VID_MODE_STS__REG_ERR_SMALL_LENGTH_SHIFT 4U
+#define DSITX__VID_MODE_STS__REG_ERR_SMALL_LENGTH_WIDTH 1U
+#define DSITX__VID_MODE_STS__REG_ERR_SMALL_LENGTH_WOCLR 0U
+#define DSITX__VID_MODE_STS__REG_ERR_SMALL_LENGTH_WOSET 0U
+#define DSITX__VID_MODE_STS__REG_ERR_SMALL_HEIGHT_MASK 0x00000020U
+#define DSITX__VID_MODE_STS__REG_ERR_SMALL_HEIGHT_SHIFT 5U
+#define DSITX__VID_MODE_STS__REG_ERR_SMALL_HEIGHT_WIDTH 1U
+#define DSITX__VID_MODE_STS__REG_ERR_SMALL_HEIGHT_WOCLR 0U
+#define DSITX__VID_MODE_STS__REG_ERR_SMALL_HEIGHT_WOSET 0U
+#define DSITX__VID_MODE_STS__ERR_BURSTWRITE_MASK 0x00000040U
+#define DSITX__VID_MODE_STS__ERR_BURSTWRITE_SHIFT 6U
+#define DSITX__VID_MODE_STS__ERR_BURSTWRITE_WIDTH 1U
+#define DSITX__VID_MODE_STS__ERR_BURSTWRITE_WOCLR 0U
+#define DSITX__VID_MODE_STS__ERR_BURSTWRITE_WOSET 0U
+#define DSITX__VID_MODE_STS__ERR_LINEWRITE_MASK 0x00000080U
+#define DSITX__VID_MODE_STS__ERR_LINEWRITE_SHIFT 7U
+#define DSITX__VID_MODE_STS__ERR_LINEWRITE_WIDTH 1U
+#define DSITX__VID_MODE_STS__ERR_LINEWRITE_WOCLR 0U
+#define DSITX__VID_MODE_STS__ERR_LINEWRITE_WOSET 0U
+#define DSITX__VID_MODE_STS__ERR_LONGREAD_MASK 0x00000100U
+#define DSITX__VID_MODE_STS__ERR_LONGREAD_SHIFT 8U
+#define DSITX__VID_MODE_STS__ERR_LONGREAD_WIDTH 1U
+#define DSITX__VID_MODE_STS__ERR_LONGREAD_WOCLR 0U
+#define DSITX__VID_MODE_STS__ERR_LONGREAD_WOSET 0U
+#define DSITX__VID_MODE_STS__ERR_VRS_WRONG_LENGTH_MASK 0x00000200U
+#define DSITX__VID_MODE_STS__ERR_VRS_WRONG_LENGTH_SHIFT 9U
+#define DSITX__VID_MODE_STS__ERR_VRS_WRONG_LENGTH_WIDTH 1U
+#define DSITX__VID_MODE_STS__ERR_VRS_WRONG_LENGTH_WOCLR 0U
+#define DSITX__VID_MODE_STS__ERR_VRS_WRONG_LENGTH_WOSET 0U
+#define DSITX__VID_MODE_STS__VSG_RECOVERY_MASK 0x00000400U
+#define DSITX__VID_MODE_STS__VSG_RECOVERY_SHIFT 10U
+#define DSITX__VID_MODE_STS__VSG_RECOVERY_WIDTH 1U
+#define DSITX__VID_MODE_STS__VSG_RECOVERY_WOCLR 0U
+#define DSITX__VID_MODE_STS__VSG_RECOVERY_WOSET 0U
+#define DSITX__VID_MODE_STS__RSVD_0_MASK 0xFFFFF800U
+#define DSITX__VID_MODE_STS__RSVD_0_SHIFT 11U
+#define DSITX__VID_MODE_STS__RSVD_0_WIDTH 21U
+
+#define DSITX__VID_VCA_SETTING1_READ_MASK 0xFFFFFFFFU
+#define DSITX__VID_VCA_SETTING1_WRITE_MASK 0xFFFFFFFFU
+#define DSITX__VID_VCA_SETTING1__MAX_BURST_LIMIT_MASK 0x0000FFFFU
+#define DSITX__VID_VCA_SETTING1__MAX_BURST_LIMIT_SHIFT 0U
+#define DSITX__VID_VCA_SETTING1__MAX_BURST_LIMIT_WIDTH 16U
+#define DSITX__VID_VCA_SETTING1__BURST_LP_MASK 0x00010000U
+#define DSITX__VID_VCA_SETTING1__BURST_LP_SHIFT 16U
+#define DSITX__VID_VCA_SETTING1__BURST_LP_WIDTH 1U
+#define DSITX__VID_VCA_SETTING1__BURST_LP_WOCLR 0U
+#define DSITX__VID_VCA_SETTING1__BURST_LP_WOSET 0U
+#define DSITX__VID_VCA_SETTING1__RSVD_0_MASK 0xFFFE0000U
+#define DSITX__VID_VCA_SETTING1__RSVD_0_SHIFT 17U
+#define DSITX__VID_VCA_SETTING1__RSVD_0_WIDTH 15U
+
+#define DSITX__VID_VCA_SETTING2_READ_MASK 0xFFFFFFFFU
+#define DSITX__VID_VCA_SETTING2_WRITE_MASK 0xFFFFFFFFU
+#define DSITX__VID_VCA_SETTING2__EXACT_BURST_LIMIT_MASK 0x0000FFFFU
+#define DSITX__VID_VCA_SETTING2__EXACT_BURST_LIMIT_SHIFT 0U
+#define DSITX__VID_VCA_SETTING2__EXACT_BURST_LIMIT_WIDTH 16U
+#define DSITX__VID_VCA_SETTING2__MAX_LINE_LIMIT_MASK 0xFFFF0000U
+#define DSITX__VID_VCA_SETTING2__MAX_LINE_LIMIT_SHIFT 16U
+#define DSITX__VID_VCA_SETTING2__MAX_LINE_LIMIT_WIDTH 16U
+
+#define DSITX__TVG_CTL_READ_MASK 0xFFFFFFFFU
+#define DSITX__TVG_CTL_WRITE_MASK 0xFFFFFFFFU
+#define DSITX__TVG_CTL__TVG_RUN_MASK 0x00000001U
+#define DSITX__TVG_CTL__TVG_RUN_SHIFT 0U
+#define DSITX__TVG_CTL__TVG_RUN_WIDTH 1U
+#define DSITX__TVG_CTL__TVG_RUN_WOCLR 0U
+#define DSITX__TVG_CTL__TVG_RUN_WOSET 0U
+#define DSITX__TVG_CTL__TVG_STOPMODE_MASK 0x00000006U
+#define DSITX__TVG_CTL__TVG_STOPMODE_SHIFT 1U
+#define DSITX__TVG_CTL__TVG_STOPMODE_WIDTH 2U
+#define DSITX__TVG_CTL__TVG_MODE_MASK 0x00000018U
+#define DSITX__TVG_CTL__TVG_MODE_SHIFT 3U
+#define DSITX__TVG_CTL__TVG_MODE_WIDTH 2U
+#define DSITX__TVG_CTL__TVG_STRIPE_SIZE_MASK 0x000000E0U
+#define DSITX__TVG_CTL__TVG_STRIPE_SIZE_SHIFT 5U
+#define DSITX__TVG_CTL__TVG_STRIPE_SIZE_WIDTH 3U
+#define DSITX__TVG_CTL__RSVD_0_MASK 0xFFFFFF00U
+#define DSITX__TVG_CTL__RSVD_0_SHIFT 8U
+#define DSITX__TVG_CTL__RSVD_0_WIDTH 24U
+
+#define DSITX__TVG_IMG_SIZE_READ_MASK 0xFFFFFFFFU
+#define DSITX__TVG_IMG_SIZE_WRITE_MASK 0xFFFFFFFFU
+#define DSITX__TVG_IMG_SIZE__TVG_LINE_SIZE_MASK 0x00007FFFU
+#define DSITX__TVG_IMG_SIZE__TVG_LINE_SIZE_SHIFT 0U
+#define DSITX__TVG_IMG_SIZE__TVG_LINE_SIZE_WIDTH 15U
+#define DSITX__TVG_IMG_SIZE__RSVD_0_MASK 0x00008000U
+#define DSITX__TVG_IMG_SIZE__RSVD_0_SHIFT 15U
+#define DSITX__TVG_IMG_SIZE__RSVD_0_WIDTH 1U
+#define DSITX__TVG_IMG_SIZE__RSVD_0_WOCLR 0U
+#define DSITX__TVG_IMG_SIZE__RSVD_0_WOSET 0U
+#define DSITX__TVG_IMG_SIZE__TVG_NBLINE_MASK 0x1FFF0000U
+#define DSITX__TVG_IMG_SIZE__TVG_NBLINE_SHIFT 16U
+#define DSITX__TVG_IMG_SIZE__TVG_NBLINE_WIDTH 13U
+#define DSITX__TVG_IMG_SIZE__RSVD_1_MASK 0xE0000000U
+#define DSITX__TVG_IMG_SIZE__RSVD_1_SHIFT 29U
+#define DSITX__TVG_IMG_SIZE__RSVD_1_WIDTH 3U
+
+#define DSITX__TVG_COLOR1_READ_MASK 0xFFFFFFFFU
+#define DSITX__TVG_COLOR1_WRITE_MASK 0xFFFFFFFFU
+#define DSITX__TVG_COLOR1__COL1_RED_MASK 0x00000FFFU
+#define DSITX__TVG_COLOR1__COL1_RED_SHIFT 0U
+#define DSITX__TVG_COLOR1__COL1_RED_WIDTH 12U
+#define DSITX__TVG_COLOR1__COL1_GREEN_MASK 0x00FFF000U
+#define DSITX__TVG_COLOR1__COL1_GREEN_SHIFT 12U
+#define DSITX__TVG_COLOR1__COL1_GREEN_WIDTH 12U
+#define DSITX__TVG_COLOR1__RSVD_0_MASK 0xFF000000U
+#define DSITX__TVG_COLOR1__RSVD_0_SHIFT 24U
+#define DSITX__TVG_COLOR1__RSVD_0_WIDTH 8U
+
+#define DSITX__TVG_COLOR1_BIS_READ_MASK 0xFFFFFFFFU
+#define DSITX__TVG_COLOR1_BIS_WRITE_MASK 0xFFFFFFFFU
+#define DSITX__TVG_COLOR1_BIS__COL1_BLUE_MASK 0x00000FFFU
+#define DSITX__TVG_COLOR1_BIS__COL1_BLUE_SHIFT 0U
+#define DSITX__TVG_COLOR1_BIS__COL1_BLUE_WIDTH 12U
+#define DSITX__TVG_COLOR1_BIS__RSVD_0_MASK 0xFFFFF000U
+#define DSITX__TVG_COLOR1_BIS__RSVD_0_SHIFT 12U
+#define DSITX__TVG_COLOR1_BIS__RSVD_0_WIDTH 20U
+
+#define DSITX__TVG_COLOR2_READ_MASK 0xFFFFFFFFU
+#define DSITX__TVG_COLOR2_WRITE_MASK 0xFFFFFFFFU
+#define DSITX__TVG_COLOR2__COL2_RED_MASK 0x00000FFFU
+#define DSITX__TVG_COLOR2__COL2_RED_SHIFT 0U
+#define DSITX__TVG_COLOR2__COL2_RED_WIDTH 12U
+#define DSITX__TVG_COLOR2__COL2_GREEN_MASK 0x00FFF000U
+#define DSITX__TVG_COLOR2__COL2_GREEN_SHIFT 12U
+#define DSITX__TVG_COLOR2__COL2_GREEN_WIDTH 12U
+#define DSITX__TVG_COLOR2__RSVD_0_MASK 0xFF000000U
+#define DSITX__TVG_COLOR2__RSVD_0_SHIFT 24U
+#define DSITX__TVG_COLOR2__RSVD_0_WIDTH 8U
+
+#define DSITX__TVG_COLOR2_BIS_READ_MASK 0xFFFFFFFFU
+#define DSITX__TVG_COLOR2_BIS_WRITE_MASK 0xFFFFFFFFU
+#define DSITX__TVG_COLOR2_BIS__COL2_BLUE_MASK 0x00000FFFU
+#define DSITX__TVG_COLOR2_BIS__COL2_BLUE_SHIFT 0U
+#define DSITX__TVG_COLOR2_BIS__COL2_BLUE_WIDTH 12U
+#define DSITX__TVG_COLOR2_BIS__RSVD_0_MASK 0xFFFFF000U
+#define DSITX__TVG_COLOR2_BIS__RSVD_0_SHIFT 12U
+#define DSITX__TVG_COLOR2_BIS__RSVD_0_WIDTH 20U
+
+#define DSITX__TVG_STS_READ_MASK 0xFFFFFFFFU
+#define DSITX__TVG_STS_WRITE_MASK 0xFFFFFFFFU
+#define DSITX__TVG_STS__TVG_RUNNING_MASK 0x00000001U
+#define DSITX__TVG_STS__TVG_RUNNING_SHIFT 0U
+#define DSITX__TVG_STS__TVG_RUNNING_WIDTH 1U
+#define DSITX__TVG_STS__TVG_RUNNING_WOCLR 0U
+#define DSITX__TVG_STS__TVG_RUNNING_WOSET 0U
+#define DSITX__TVG_STS__RSVD_0_MASK 0xFFFFFFFEU
+#define DSITX__TVG_STS__RSVD_0_SHIFT 1U
+#define DSITX__TVG_STS__RSVD_0_WIDTH 31U
+
+#define DSITX__MCTL_MAIN_STS_CTL_READ_MASK 0xFFFFFFFFU
+#define DSITX__MCTL_MAIN_STS_CTL_WRITE_MASK 0xFFFFFFFFU
+#define DSITX__MCTL_MAIN_STS_CTL__PLL_LOCK_EN_MASK 0x00000001U
+#define DSITX__MCTL_MAIN_STS_CTL__PLL_LOCK_EN_SHIFT 0U
+#define DSITX__MCTL_MAIN_STS_CTL__PLL_LOCK_EN_WIDTH 1U
+#define DSITX__MCTL_MAIN_STS_CTL__PLL_LOCK_EN_WOCLR 0U
+#define DSITX__MCTL_MAIN_STS_CTL__PLL_LOCK_EN_WOSET 0U
+#define DSITX__MCTL_MAIN_STS_CTL__CLKLANE_READY_EN_MASK 0x00000002U
+#define DSITX__MCTL_MAIN_STS_CTL__CLKLANE_READY_EN_SHIFT 1U
+#define DSITX__MCTL_MAIN_STS_CTL__CLKLANE_READY_EN_WIDTH 1U
+#define DSITX__MCTL_MAIN_STS_CTL__CLKLANE_READY_EN_WOCLR 0U
+#define DSITX__MCTL_MAIN_STS_CTL__CLKLANE_READY_EN_WOSET 0U
+#define DSITX__MCTL_MAIN_STS_CTL__DAT1_READY_EN_MASK 0x00000004U
+#define DSITX__MCTL_MAIN_STS_CTL__DAT1_READY_EN_SHIFT 2U
+#define DSITX__MCTL_MAIN_STS_CTL__DAT1_READY_EN_WIDTH 1U
+#define DSITX__MCTL_MAIN_STS_CTL__DAT1_READY_EN_WOCLR 0U
+#define DSITX__MCTL_MAIN_STS_CTL__DAT1_READY_EN_WOSET 0U
+#define DSITX__MCTL_MAIN_STS_CTL__DAT2_READY_EN_MASK 0x00000008U
+#define DSITX__MCTL_MAIN_STS_CTL__DAT2_READY_EN_SHIFT 3U
+#define DSITX__MCTL_MAIN_STS_CTL__DAT2_READY_EN_WIDTH 1U
+#define DSITX__MCTL_MAIN_STS_CTL__DAT2_READY_EN_WOCLR 0U
+#define DSITX__MCTL_MAIN_STS_CTL__DAT2_READY_EN_WOSET 0U
+#define DSITX__MCTL_MAIN_STS_CTL__DAT3_READY_EN_MASK 0x00000010U
+#define DSITX__MCTL_MAIN_STS_CTL__DAT3_READY_EN_SHIFT 4U
+#define DSITX__MCTL_MAIN_STS_CTL__DAT3_READY_EN_WIDTH 1U
+#define DSITX__MCTL_MAIN_STS_CTL__DAT3_READY_EN_WOCLR 0U
+#define DSITX__MCTL_MAIN_STS_CTL__DAT3_READY_EN_WOSET 0U
+#define DSITX__MCTL_MAIN_STS_CTL__DAT4_READY_EN_MASK 0x00000020U
+#define DSITX__MCTL_MAIN_STS_CTL__DAT4_READY_EN_SHIFT 5U
+#define DSITX__MCTL_MAIN_STS_CTL__DAT4_READY_EN_WIDTH 1U
+#define DSITX__MCTL_MAIN_STS_CTL__DAT4_READY_EN_WOCLR 0U
+#define DSITX__MCTL_MAIN_STS_CTL__DAT4_READY_EN_WOSET 0U
+#define DSITX__MCTL_MAIN_STS_CTL__HSTX_TO_ERR_EN_MASK 0x00000040U
+#define DSITX__MCTL_MAIN_STS_CTL__HSTX_TO_ERR_EN_SHIFT 6U
+#define DSITX__MCTL_MAIN_STS_CTL__HSTX_TO_ERR_EN_WIDTH 1U
+#define DSITX__MCTL_MAIN_STS_CTL__HSTX_TO_ERR_EN_WOCLR 0U
+#define DSITX__MCTL_MAIN_STS_CTL__HSTX_TO_ERR_EN_WOSET 0U
+#define DSITX__MCTL_MAIN_STS_CTL__LPRX_TO_ERR_EN_MASK 0x00000080U
+#define DSITX__MCTL_MAIN_STS_CTL__LPRX_TO_ERR_EN_SHIFT 7U
+#define DSITX__MCTL_MAIN_STS_CTL__LPRX_TO_ERR_EN_WIDTH 1U
+#define DSITX__MCTL_MAIN_STS_CTL__LPRX_TO_ERR_EN_WOCLR 0U
+#define DSITX__MCTL_MAIN_STS_CTL__LPRX_TO_ERR_EN_WOSET 0U
+#define DSITX__MCTL_MAIN_STS_CTL__IF1_UNTERM_PCK_ERR_EN_MASK 0x00000100U
+#define DSITX__MCTL_MAIN_STS_CTL__IF1_UNTERM_PCK_ERR_EN_SHIFT 8U
+#define DSITX__MCTL_MAIN_STS_CTL__IF1_UNTERM_PCK_ERR_EN_WIDTH 1U
+#define DSITX__MCTL_MAIN_STS_CTL__IF1_UNTERM_PCK_ERR_EN_WOCLR 0U
+#define DSITX__MCTL_MAIN_STS_CTL__IF1_UNTERM_PCK_ERR_EN_WOSET 0U
+#define DSITX__MCTL_MAIN_STS_CTL__IF3_UNTERM_PCK_ERR_EN_MASK 0x00000200U
+#define DSITX__MCTL_MAIN_STS_CTL__IF3_UNTERM_PCK_ERR_EN_SHIFT 9U
+#define DSITX__MCTL_MAIN_STS_CTL__IF3_UNTERM_PCK_ERR_EN_WIDTH 1U
+#define DSITX__MCTL_MAIN_STS_CTL__IF3_UNTERM_PCK_ERR_EN_WOCLR 0U
+#define DSITX__MCTL_MAIN_STS_CTL__IF3_UNTERM_PCK_ERR_EN_WOSET 0U
+#define DSITX__MCTL_MAIN_STS_CTL__RSVD_0_MASK 0x0000FC00U
+#define DSITX__MCTL_MAIN_STS_CTL__RSVD_0_SHIFT 10U
+#define DSITX__MCTL_MAIN_STS_CTL__RSVD_0_WIDTH 6U
+#define DSITX__MCTL_MAIN_STS_CTL__PLL_LOCK_EDGE_MASK 0x00010000U
+#define DSITX__MCTL_MAIN_STS_CTL__PLL_LOCK_EDGE_SHIFT 16U
+#define DSITX__MCTL_MAIN_STS_CTL__PLL_LOCK_EDGE_WIDTH 1U
+#define DSITX__MCTL_MAIN_STS_CTL__PLL_LOCK_EDGE_WOCLR 0U
+#define DSITX__MCTL_MAIN_STS_CTL__PLL_LOCK_EDGE_WOSET 0U
+#define DSITX__MCTL_MAIN_STS_CTL__CLKLANE_READY_EDGE_MASK 0x00020000U
+#define DSITX__MCTL_MAIN_STS_CTL__CLKLANE_READY_EDGE_SHIFT 17U
+#define DSITX__MCTL_MAIN_STS_CTL__CLKLANE_READY_EDGE_WIDTH 1U
+#define DSITX__MCTL_MAIN_STS_CTL__CLKLANE_READY_EDGE_WOCLR 0U
+#define DSITX__MCTL_MAIN_STS_CTL__CLKLANE_READY_EDGE_WOSET 0U
+#define DSITX__MCTL_MAIN_STS_CTL__DAT1_READY_EDGE_MASK 0x00040000U
+#define DSITX__MCTL_MAIN_STS_CTL__DAT1_READY_EDGE_SHIFT 18U
+#define DSITX__MCTL_MAIN_STS_CTL__DAT1_READY_EDGE_WIDTH 1U
+#define DSITX__MCTL_MAIN_STS_CTL__DAT1_READY_EDGE_WOCLR 0U
+#define DSITX__MCTL_MAIN_STS_CTL__DAT1_READY_EDGE_WOSET 0U
+#define DSITX__MCTL_MAIN_STS_CTL__DAT2_READY_EDGE_MASK 0x00080000U
+#define DSITX__MCTL_MAIN_STS_CTL__DAT2_READY_EDGE_SHIFT 19U
+#define DSITX__MCTL_MAIN_STS_CTL__DAT2_READY_EDGE_WIDTH 1U
+#define DSITX__MCTL_MAIN_STS_CTL__DAT2_READY_EDGE_WOCLR 0U
+#define DSITX__MCTL_MAIN_STS_CTL__DAT2_READY_EDGE_WOSET 0U
+#define DSITX__MCTL_MAIN_STS_CTL__DAT3_READY_EDGE_MASK 0x00100000U
+#define DSITX__MCTL_MAIN_STS_CTL__DAT3_READY_EDGE_SHIFT 20U
+#define DSITX__MCTL_MAIN_STS_CTL__DAT3_READY_EDGE_WIDTH 1U
+#define DSITX__MCTL_MAIN_STS_CTL__DAT3_READY_EDGE_WOCLR 0U
+#define DSITX__MCTL_MAIN_STS_CTL__DAT3_READY_EDGE_WOSET 0U
+#define DSITX__MCTL_MAIN_STS_CTL__DAT4_READY_EDGE_MASK 0x00200000U
+#define DSITX__MCTL_MAIN_STS_CTL__DAT4_READY_EDGE_SHIFT 21U
+#define DSITX__MCTL_MAIN_STS_CTL__DAT4_READY_EDGE_WIDTH 1U
+#define DSITX__MCTL_MAIN_STS_CTL__DAT4_READY_EDGE_WOCLR 0U
+#define DSITX__MCTL_MAIN_STS_CTL__DAT4_READY_EDGE_WOSET 0U
+#define DSITX__MCTL_MAIN_STS_CTL__HSTX_TO_ERR_EDGE_MASK 0x00400000U
+#define DSITX__MCTL_MAIN_STS_CTL__HSTX_TO_ERR_EDGE_SHIFT 22U
+#define DSITX__MCTL_MAIN_STS_CTL__HSTX_TO_ERR_EDGE_WIDTH 1U
+#define DSITX__MCTL_MAIN_STS_CTL__HSTX_TO_ERR_EDGE_WOCLR 0U
+#define DSITX__MCTL_MAIN_STS_CTL__HSTX_TO_ERR_EDGE_WOSET 0U
+#define DSITX__MCTL_MAIN_STS_CTL__LPRX_TO_ERR_EDGE_MASK 0x00800000U
+#define DSITX__MCTL_MAIN_STS_CTL__LPRX_TO_ERR_EDGE_SHIFT 23U
+#define DSITX__MCTL_MAIN_STS_CTL__LPRX_TO_ERR_EDGE_WIDTH 1U
+#define DSITX__MCTL_MAIN_STS_CTL__LPRX_TO_ERR_EDGE_WOCLR 0U
+#define DSITX__MCTL_MAIN_STS_CTL__LPRX_TO_ERR_EDGE_WOSET 0U
+#define DSITX__MCTL_MAIN_STS_CTL__IF1_UNTERM_PCK_ERR_EDGE_MASK 0x01000000U
+#define DSITX__MCTL_MAIN_STS_CTL__IF1_UNTERM_PCK_ERR_EDGE_SHIFT 24U
+#define DSITX__MCTL_MAIN_STS_CTL__IF1_UNTERM_PCK_ERR_EDGE_WIDTH 1U
+#define DSITX__MCTL_MAIN_STS_CTL__IF1_UNTERM_PCK_ERR_EDGE_WOCLR 0U
+#define DSITX__MCTL_MAIN_STS_CTL__IF1_UNTERM_PCK_ERR_EDGE_WOSET 0U
+#define DSITX__MCTL_MAIN_STS_CTL__IF3_UNTERM_PCK_ERR_EDGE_MASK 0x02000000U
+#define DSITX__MCTL_MAIN_STS_CTL__IF3_UNTERM_PCK_ERR_EDGE_SHIFT 25U
+#define DSITX__MCTL_MAIN_STS_CTL__IF3_UNTERM_PCK_ERR_EDGE_WIDTH 1U
+#define DSITX__MCTL_MAIN_STS_CTL__IF3_UNTERM_PCK_ERR_EDGE_WOCLR 0U
+#define DSITX__MCTL_MAIN_STS_CTL__IF3_UNTERM_PCK_ERR_EDGE_WOSET 0U
+#define DSITX__MCTL_MAIN_STS_CTL__RSVD_1_MASK 0xFC000000U
+#define DSITX__MCTL_MAIN_STS_CTL__RSVD_1_SHIFT 26U
+#define DSITX__MCTL_MAIN_STS_CTL__RSVD_1_WIDTH 6U
+
+#define DSITX__CMD_MODE_STS_CTL_READ_MASK 0xFFFFFFFFU
+#define DSITX__CMD_MODE_STS_CTL_WRITE_MASK 0xFFFFFFFFU
+#define DSITX__CMD_MODE_STS_CTL__CSM_RUNNING_EN_MASK 0x00000001U
+#define DSITX__CMD_MODE_STS_CTL__CSM_RUNNING_EN_SHIFT 0U
+#define DSITX__CMD_MODE_STS_CTL__CSM_RUNNING_EN_WIDTH 1U
+#define DSITX__CMD_MODE_STS_CTL__CSM_RUNNING_EN_WOCLR 0U
+#define DSITX__CMD_MODE_STS_CTL__CSM_RUNNING_EN_WOSET 0U
+#define DSITX__CMD_MODE_STS_CTL__ERR_NO_TE_EN_MASK 0x00000002U
+#define DSITX__CMD_MODE_STS_CTL__ERR_NO_TE_EN_SHIFT 1U
+#define DSITX__CMD_MODE_STS_CTL__ERR_NO_TE_EN_WIDTH 1U
+#define DSITX__CMD_MODE_STS_CTL__ERR_NO_TE_EN_WOCLR 0U
+#define DSITX__CMD_MODE_STS_CTL__ERR_NO_TE_EN_WOSET 0U
+#define DSITX__CMD_MODE_STS_CTL__ERR_TE_MISS_EN_MASK 0x00000004U
+#define DSITX__CMD_MODE_STS_CTL__ERR_TE_MISS_EN_SHIFT 2U
+#define DSITX__CMD_MODE_STS_CTL__ERR_TE_MISS_EN_WIDTH 1U
+#define DSITX__CMD_MODE_STS_CTL__ERR_TE_MISS_EN_WOCLR 0U
+#define DSITX__CMD_MODE_STS_CTL__ERR_TE_MISS_EN_WOSET 0U
+#define DSITX__CMD_MODE_STS_CTL__ERR_UNWANTED_RD_EN_MASK 0x00000008U
+#define DSITX__CMD_MODE_STS_CTL__ERR_UNWANTED_RD_EN_SHIFT 3U
+#define DSITX__CMD_MODE_STS_CTL__ERR_UNWANTED_RD_EN_WIDTH 1U
+#define DSITX__CMD_MODE_STS_CTL__ERR_UNWANTED_RD_EN_WOCLR 0U
+#define DSITX__CMD_MODE_STS_CTL__ERR_UNWANTED_RD_EN_WOSET 0U
+#define DSITX__CMD_MODE_STS_CTL__ERR_IF1_UNDERRUN_EN_MASK 0x00000010U
+#define DSITX__CMD_MODE_STS_CTL__ERR_IF1_UNDERRUN_EN_SHIFT 4U
+#define DSITX__CMD_MODE_STS_CTL__ERR_IF1_UNDERRUN_EN_WIDTH 1U
+#define DSITX__CMD_MODE_STS_CTL__ERR_IF1_UNDERRUN_EN_WOCLR 0U
+#define DSITX__CMD_MODE_STS_CTL__ERR_IF1_UNDERRUN_EN_WOSET 0U
+#define DSITX__CMD_MODE_STS_CTL__ERR_IF3_UNDERRUN_EN_MASK 0x00000020U
+#define DSITX__CMD_MODE_STS_CTL__ERR_IF3_UNDERRUN_EN_SHIFT 5U
+#define DSITX__CMD_MODE_STS_CTL__ERR_IF3_UNDERRUN_EN_WIDTH 1U
+#define DSITX__CMD_MODE_STS_CTL__ERR_IF3_UNDERRUN_EN_WOCLR 0U
+#define DSITX__CMD_MODE_STS_CTL__ERR_IF3_UNDERRUN_EN_WOSET 0U
+#define DSITX__CMD_MODE_STS_CTL__RSVD_0_MASK 0x0000FFC0U
+#define DSITX__CMD_MODE_STS_CTL__RSVD_0_SHIFT 6U
+#define DSITX__CMD_MODE_STS_CTL__RSVD_0_WIDTH 10U
+#define DSITX__CMD_MODE_STS_CTL__CSM_RUNNING_EDGE_MASK 0x00010000U
+#define DSITX__CMD_MODE_STS_CTL__CSM_RUNNING_EDGE_SHIFT 16U
+#define DSITX__CMD_MODE_STS_CTL__CSM_RUNNING_EDGE_WIDTH 1U
+#define DSITX__CMD_MODE_STS_CTL__CSM_RUNNING_EDGE_WOCLR 0U
+#define DSITX__CMD_MODE_STS_CTL__CSM_RUNNING_EDGE_WOSET 0U
+#define DSITX__CMD_MODE_STS_CTL__ERR_NO_TE_EDGE_MASK 0x00020000U
+#define DSITX__CMD_MODE_STS_CTL__ERR_NO_TE_EDGE_SHIFT 17U
+#define DSITX__CMD_MODE_STS_CTL__ERR_NO_TE_EDGE_WIDTH 1U
+#define DSITX__CMD_MODE_STS_CTL__ERR_NO_TE_EDGE_WOCLR 0U
+#define DSITX__CMD_MODE_STS_CTL__ERR_NO_TE_EDGE_WOSET 0U
+#define DSITX__CMD_MODE_STS_CTL__ERR_TE_MISS_EDGE_MASK 0x00040000U
+#define DSITX__CMD_MODE_STS_CTL__ERR_TE_MISS_EDGE_SHIFT 18U
+#define DSITX__CMD_MODE_STS_CTL__ERR_TE_MISS_EDGE_WIDTH 1U
+#define DSITX__CMD_MODE_STS_CTL__ERR_TE_MISS_EDGE_WOCLR 0U
+#define DSITX__CMD_MODE_STS_CTL__ERR_TE_MISS_EDGE_WOSET 0U
+#define DSITX__CMD_MODE_STS_CTL__ERR_UNWANTED_RD_EDGE_MASK 0x00080000U
+#define DSITX__CMD_MODE_STS_CTL__ERR_UNWANTED_RD_EDGE_SHIFT 19U
+#define DSITX__CMD_MODE_STS_CTL__ERR_UNWANTED_RD_EDGE_WIDTH 1U
+#define DSITX__CMD_MODE_STS_CTL__ERR_UNWANTED_RD_EDGE_WOCLR 0U
+#define DSITX__CMD_MODE_STS_CTL__ERR_UNWANTED_RD_EDGE_WOSET 0U
+#define DSITX__CMD_MODE_STS_CTL__ERR_IF1_UNDERRUN_EDGE_MASK 0x00100000U
+#define DSITX__CMD_MODE_STS_CTL__ERR_IF1_UNDERRUN_EDGE_SHIFT 20U
+#define DSITX__CMD_MODE_STS_CTL__ERR_IF1_UNDERRUN_EDGE_WIDTH 1U
+#define DSITX__CMD_MODE_STS_CTL__ERR_IF1_UNDERRUN_EDGE_WOCLR 0U
+#define DSITX__CMD_MODE_STS_CTL__ERR_IF1_UNDERRUN_EDGE_WOSET 0U
+#define DSITX__CMD_MODE_STS_CTL__ERR_IF3_UNDERRUN_EDGE_MASK 0x00200000U
+#define DSITX__CMD_MODE_STS_CTL__ERR_IF3_UNDERRUN_EDGE_SHIFT 21U
+#define DSITX__CMD_MODE_STS_CTL__ERR_IF3_UNDERRUN_EDGE_WIDTH 1U
+#define DSITX__CMD_MODE_STS_CTL__ERR_IF3_UNDERRUN_EDGE_WOCLR 0U
+#define DSITX__CMD_MODE_STS_CTL__ERR_IF3_UNDERRUN_EDGE_WOSET 0U
+#define DSITX__CMD_MODE_STS_CTL__RSVD_1_MASK 0xFFC00000U
+#define DSITX__CMD_MODE_STS_CTL__RSVD_1_SHIFT 22U
+#define DSITX__CMD_MODE_STS_CTL__RSVD_1_WIDTH 10U
+
+#define DSITX__DIRECT_CMD_STS_CTL_READ_MASK 0xFFFFFFFFU
+#define DSITX__DIRECT_CMD_STS_CTL_WRITE_MASK 0xFFFFFFFFU
+#define DSITX__DIRECT_CMD_STS_CTL__CMD_TRANSMISSION_EN_MASK 0x00000001U
+#define DSITX__DIRECT_CMD_STS_CTL__CMD_TRANSMISSION_EN_SHIFT 0U
+#define DSITX__DIRECT_CMD_STS_CTL__CMD_TRANSMISSION_EN_WIDTH 1U
+#define DSITX__DIRECT_CMD_STS_CTL__CMD_TRANSMISSION_EN_WOCLR 0U
+#define DSITX__DIRECT_CMD_STS_CTL__CMD_TRANSMISSION_EN_WOSET 0U
+#define DSITX__DIRECT_CMD_STS_CTL__WRITE_COMPLETED_EN_MASK 0x00000002U
+#define DSITX__DIRECT_CMD_STS_CTL__WRITE_COMPLETED_EN_SHIFT 1U
+#define DSITX__DIRECT_CMD_STS_CTL__WRITE_COMPLETED_EN_WIDTH 1U
+#define DSITX__DIRECT_CMD_STS_CTL__WRITE_COMPLETED_EN_WOCLR 0U
+#define DSITX__DIRECT_CMD_STS_CTL__WRITE_COMPLETED_EN_WOSET 0U
+#define DSITX__DIRECT_CMD_STS_CTL__TRIGGER_COMPLETED_EN_MASK 0x00000004U
+#define DSITX__DIRECT_CMD_STS_CTL__TRIGGER_COMPLETED_EN_SHIFT 2U
+#define DSITX__DIRECT_CMD_STS_CTL__TRIGGER_COMPLETED_EN_WIDTH 1U
+#define DSITX__DIRECT_CMD_STS_CTL__TRIGGER_COMPLETED_EN_WOCLR 0U
+#define DSITX__DIRECT_CMD_STS_CTL__TRIGGER_COMPLETED_EN_WOSET 0U
+#define DSITX__DIRECT_CMD_STS_CTL__READ_COMPLETED_EN_MASK 0x00000008U
+#define DSITX__DIRECT_CMD_STS_CTL__READ_COMPLETED_EN_SHIFT 3U
+#define DSITX__DIRECT_CMD_STS_CTL__READ_COMPLETED_EN_WIDTH 1U
+#define DSITX__DIRECT_CMD_STS_CTL__READ_COMPLETED_EN_WOCLR 0U
+#define DSITX__DIRECT_CMD_STS_CTL__READ_COMPLETED_EN_WOSET 0U
+#define DSITX__DIRECT_CMD_STS_CTL__ACKNOWLEDGE_RECEIVED_EN_MASK 0x00000010U
+#define DSITX__DIRECT_CMD_STS_CTL__ACKNOWLEDGE_RECEIVED_EN_SHIFT 4U
+#define DSITX__DIRECT_CMD_STS_CTL__ACKNOWLEDGE_RECEIVED_EN_WIDTH 1U
+#define DSITX__DIRECT_CMD_STS_CTL__ACKNOWLEDGE_RECEIVED_EN_WOCLR 0U
+#define DSITX__DIRECT_CMD_STS_CTL__ACKNOWLEDGE_RECEIVED_EN_WOSET 0U
+#define DSITX__DIRECT_CMD_STS_CTL__ACKNOWLEDGE_WITH_ERR_EN_MASK 0x00000020U
+#define DSITX__DIRECT_CMD_STS_CTL__ACKNOWLEDGE_WITH_ERR_EN_SHIFT 5U
+#define DSITX__DIRECT_CMD_STS_CTL__ACKNOWLEDGE_WITH_ERR_EN_WIDTH 1U
+#define DSITX__DIRECT_CMD_STS_CTL__ACKNOWLEDGE_WITH_ERR_EN_WOCLR 0U
+#define DSITX__DIRECT_CMD_STS_CTL__ACKNOWLEDGE_WITH_ERR_EN_WOSET 0U
+#define DSITX__DIRECT_CMD_STS_CTL__TRIGGER_RECEIVED_EN_MASK 0x00000040U
+#define DSITX__DIRECT_CMD_STS_CTL__TRIGGER_RECEIVED_EN_SHIFT 6U
+#define DSITX__DIRECT_CMD_STS_CTL__TRIGGER_RECEIVED_EN_WIDTH 1U
+#define DSITX__DIRECT_CMD_STS_CTL__TRIGGER_RECEIVED_EN_WOCLR 0U
+#define DSITX__DIRECT_CMD_STS_CTL__TRIGGER_RECEIVED_EN_WOSET 0U
+#define DSITX__DIRECT_CMD_STS_CTL__TE_RECEIVED_EN_MASK 0x00000080U
+#define DSITX__DIRECT_CMD_STS_CTL__TE_RECEIVED_EN_SHIFT 7U
+#define DSITX__DIRECT_CMD_STS_CTL__TE_RECEIVED_EN_WIDTH 1U
+#define DSITX__DIRECT_CMD_STS_CTL__TE_RECEIVED_EN_WOCLR 0U
+#define DSITX__DIRECT_CMD_STS_CTL__TE_RECEIVED_EN_WOSET 0U
+#define DSITX__DIRECT_CMD_STS_CTL__BTA_COMPLETED_EN_MASK 0x00000100U
+#define DSITX__DIRECT_CMD_STS_CTL__BTA_COMPLETED_EN_SHIFT 8U
+#define DSITX__DIRECT_CMD_STS_CTL__BTA_COMPLETED_EN_WIDTH 1U
+#define DSITX__DIRECT_CMD_STS_CTL__BTA_COMPLETED_EN_WOCLR 0U
+#define DSITX__DIRECT_CMD_STS_CTL__BTA_COMPLETED_EN_WOSET 0U
+#define DSITX__DIRECT_CMD_STS_CTL__BTA_FINISHED_EN_MASK 0x00000200U
+#define DSITX__DIRECT_CMD_STS_CTL__BTA_FINISHED_EN_SHIFT 9U
+#define DSITX__DIRECT_CMD_STS_CTL__BTA_FINISHED_EN_WIDTH 1U
+#define DSITX__DIRECT_CMD_STS_CTL__BTA_FINISHED_EN_WOCLR 0U
+#define DSITX__DIRECT_CMD_STS_CTL__BTA_FINISHED_EN_WOSET 0U
+#define DSITX__DIRECT_CMD_STS_CTL__READ_COMPLETED_WITH_ERR_EN_MASK 0x00000400U
+#define DSITX__DIRECT_CMD_STS_CTL__READ_COMPLETED_WITH_ERR_EN_SHIFT 10U
+#define DSITX__DIRECT_CMD_STS_CTL__READ_COMPLETED_WITH_ERR_EN_WIDTH 1U
+#define DSITX__DIRECT_CMD_STS_CTL__READ_COMPLETED_WITH_ERR_EN_WOCLR 0U
+#define DSITX__DIRECT_CMD_STS_CTL__READ_COMPLETED_WITH_ERR_EN_WOSET 0U
+#define DSITX__DIRECT_CMD_STS_CTL__RSVD_0_MASK 0x0000F800U
+#define DSITX__DIRECT_CMD_STS_CTL__RSVD_0_SHIFT 11U
+#define DSITX__DIRECT_CMD_STS_CTL__RSVD_0_WIDTH 5U
+#define DSITX__DIRECT_CMD_STS_CTL__CMD_TRANSMISSION_EDGE_MASK 0x00010000U
+#define DSITX__DIRECT_CMD_STS_CTL__CMD_TRANSMISSION_EDGE_SHIFT 16U
+#define DSITX__DIRECT_CMD_STS_CTL__CMD_TRANSMISSION_EDGE_WIDTH 1U
+#define DSITX__DIRECT_CMD_STS_CTL__CMD_TRANSMISSION_EDGE_WOCLR 0U
+#define DSITX__DIRECT_CMD_STS_CTL__CMD_TRANSMISSION_EDGE_WOSET 0U
+#define DSITX__DIRECT_CMD_STS_CTL__WRITE_COMPLETED_EDGE_MASK 0x00020000U
+#define DSITX__DIRECT_CMD_STS_CTL__WRITE_COMPLETED_EDGE_SHIFT 17U
+#define DSITX__DIRECT_CMD_STS_CTL__WRITE_COMPLETED_EDGE_WIDTH 1U
+#define DSITX__DIRECT_CMD_STS_CTL__WRITE_COMPLETED_EDGE_WOCLR 0U
+#define DSITX__DIRECT_CMD_STS_CTL__WRITE_COMPLETED_EDGE_WOSET 0U
+#define DSITX__DIRECT_CMD_STS_CTL__TRIGGER_COMPLETED_EDGE_MASK 0x00040000U
+#define DSITX__DIRECT_CMD_STS_CTL__TRIGGER_COMPLETED_EDGE_SHIFT 18U
+#define DSITX__DIRECT_CMD_STS_CTL__TRIGGER_COMPLETED_EDGE_WIDTH 1U
+#define DSITX__DIRECT_CMD_STS_CTL__TRIGGER_COMPLETED_EDGE_WOCLR 0U
+#define DSITX__DIRECT_CMD_STS_CTL__TRIGGER_COMPLETED_EDGE_WOSET 0U
+#define DSITX__DIRECT_CMD_STS_CTL__READ_COMPLETED_EDGE_MASK 0x00080000U
+#define DSITX__DIRECT_CMD_STS_CTL__READ_COMPLETED_EDGE_SHIFT 19U
+#define DSITX__DIRECT_CMD_STS_CTL__READ_COMPLETED_EDGE_WIDTH 1U
+#define DSITX__DIRECT_CMD_STS_CTL__READ_COMPLETED_EDGE_WOCLR 0U
+#define DSITX__DIRECT_CMD_STS_CTL__READ_COMPLETED_EDGE_WOSET 0U
+#define DSITX__DIRECT_CMD_STS_CTL__ACKNOWLEDGE_RECEIVED_EDGE_MASK 0x00100000U
+#define DSITX__DIRECT_CMD_STS_CTL__ACKNOWLEDGE_RECEIVED_EDGE_SHIFT 20U
+#define DSITX__DIRECT_CMD_STS_CTL__ACKNOWLEDGE_RECEIVED_EDGE_WIDTH 1U
+#define DSITX__DIRECT_CMD_STS_CTL__ACKNOWLEDGE_RECEIVED_EDGE_WOCLR 0U
+#define DSITX__DIRECT_CMD_STS_CTL__ACKNOWLEDGE_RECEIVED_EDGE_WOSET 0U
+#define DSITX__DIRECT_CMD_STS_CTL__ACKNOWLEDGE_WITH_ERR_EDGE_MASK 0x00200000U
+#define DSITX__DIRECT_CMD_STS_CTL__ACKNOWLEDGE_WITH_ERR_EDGE_SHIFT 21U
+#define DSITX__DIRECT_CMD_STS_CTL__ACKNOWLEDGE_WITH_ERR_EDGE_WIDTH 1U
+#define DSITX__DIRECT_CMD_STS_CTL__ACKNOWLEDGE_WITH_ERR_EDGE_WOCLR 0U
+#define DSITX__DIRECT_CMD_STS_CTL__ACKNOWLEDGE_WITH_ERR_EDGE_WOSET 0U
+#define DSITX__DIRECT_CMD_STS_CTL__TRIGGER_RECEIVED_EDGE_MASK 0x00400000U
+#define DSITX__DIRECT_CMD_STS_CTL__TRIGGER_RECEIVED_EDGE_SHIFT 22U
+#define DSITX__DIRECT_CMD_STS_CTL__TRIGGER_RECEIVED_EDGE_WIDTH 1U
+#define DSITX__DIRECT_CMD_STS_CTL__TRIGGER_RECEIVED_EDGE_WOCLR 0U
+#define DSITX__DIRECT_CMD_STS_CTL__TRIGGER_RECEIVED_EDGE_WOSET 0U
+#define DSITX__DIRECT_CMD_STS_CTL__TE_RECEIVED_EDGE_MASK 0x00800000U
+#define DSITX__DIRECT_CMD_STS_CTL__TE_RECEIVED_EDGE_SHIFT 23U
+#define DSITX__DIRECT_CMD_STS_CTL__TE_RECEIVED_EDGE_WIDTH 1U
+#define DSITX__DIRECT_CMD_STS_CTL__TE_RECEIVED_EDGE_WOCLR 0U
+#define DSITX__DIRECT_CMD_STS_CTL__TE_RECEIVED_EDGE_WOSET 0U
+#define DSITX__DIRECT_CMD_STS_CTL__BTA_COMPLETED_EDGE_MASK 0x01000000U
+#define DSITX__DIRECT_CMD_STS_CTL__BTA_COMPLETED_EDGE_SHIFT 24U
+#define DSITX__DIRECT_CMD_STS_CTL__BTA_COMPLETED_EDGE_WIDTH 1U
+#define DSITX__DIRECT_CMD_STS_CTL__BTA_COMPLETED_EDGE_WOCLR 0U
+#define DSITX__DIRECT_CMD_STS_CTL__BTA_COMPLETED_EDGE_WOSET 0U
+#define DSITX__DIRECT_CMD_STS_CTL__BTA_FINISHED_EDGE_MASK 0x02000000U
+#define DSITX__DIRECT_CMD_STS_CTL__BTA_FINISHED_EDGE_SHIFT 25U
+#define DSITX__DIRECT_CMD_STS_CTL__BTA_FINISHED_EDGE_WIDTH 1U
+#define DSITX__DIRECT_CMD_STS_CTL__BTA_FINISHED_EDGE_WOCLR 0U
+#define DSITX__DIRECT_CMD_STS_CTL__BTA_FINISHED_EDGE_WOSET 0U
+#define DSITX__DIRECT_CMD_STS_CTL__READ_COMPLETED_WITH_ERR_EDGE_MASK 0x04000000U
+#define DSITX__DIRECT_CMD_STS_CTL__READ_COMPLETED_WITH_ERR_EDGE_SHIFT 26U
+#define DSITX__DIRECT_CMD_STS_CTL__READ_COMPLETED_WITH_ERR_EDGE_WIDTH 1U
+#define DSITX__DIRECT_CMD_STS_CTL__READ_COMPLETED_WITH_ERR_EDGE_WOCLR 0U
+#define DSITX__DIRECT_CMD_STS_CTL__READ_COMPLETED_WITH_ERR_EDGE_WOSET 0U
+#define DSITX__DIRECT_CMD_STS_CTL__RSVD_1_MASK 0xF8000000U
+#define DSITX__DIRECT_CMD_STS_CTL__RSVD_1_SHIFT 27U
+#define DSITX__DIRECT_CMD_STS_CTL__RSVD_1_WIDTH 5U
+
+#define DSITX__DIRECT_CMD_RD_STS_CTL_READ_MASK 0xFFFFFFFFU
+#define DSITX__DIRECT_CMD_RD_STS_CTL_WRITE_MASK 0xFFFFFFFFU
+#define DSITX__DIRECT_CMD_RD_STS_CTL__ERR_FIXED_EN_MASK 0x00000001U
+#define DSITX__DIRECT_CMD_RD_STS_CTL__ERR_FIXED_EN_SHIFT 0U
+#define DSITX__DIRECT_CMD_RD_STS_CTL__ERR_FIXED_EN_WIDTH 1U
+#define DSITX__DIRECT_CMD_RD_STS_CTL__ERR_FIXED_EN_WOCLR 0U
+#define DSITX__DIRECT_CMD_RD_STS_CTL__ERR_FIXED_EN_WOSET 0U
+#define DSITX__DIRECT_CMD_RD_STS_CTL__ERR_UNCORRECTABLE_EN_MASK 0x00000002U
+#define DSITX__DIRECT_CMD_RD_STS_CTL__ERR_UNCORRECTABLE_EN_SHIFT 1U
+#define DSITX__DIRECT_CMD_RD_STS_CTL__ERR_UNCORRECTABLE_EN_WIDTH 1U
+#define DSITX__DIRECT_CMD_RD_STS_CTL__ERR_UNCORRECTABLE_EN_WOCLR 0U
+#define DSITX__DIRECT_CMD_RD_STS_CTL__ERR_UNCORRECTABLE_EN_WOSET 0U
+#define DSITX__DIRECT_CMD_RD_STS_CTL__ERR_CHECKSUM_EN_MASK 0x00000004U
+#define DSITX__DIRECT_CMD_RD_STS_CTL__ERR_CHECKSUM_EN_SHIFT 2U
+#define DSITX__DIRECT_CMD_RD_STS_CTL__ERR_CHECKSUM_EN_WIDTH 1U
+#define DSITX__DIRECT_CMD_RD_STS_CTL__ERR_CHECKSUM_EN_WOCLR 0U
+#define DSITX__DIRECT_CMD_RD_STS_CTL__ERR_CHECKSUM_EN_WOSET 0U
+#define DSITX__DIRECT_CMD_RD_STS_CTL__ERR_UNDECODABLE_EN_MASK 0x00000008U
+#define DSITX__DIRECT_CMD_RD_STS_CTL__ERR_UNDECODABLE_EN_SHIFT 3U
+#define DSITX__DIRECT_CMD_RD_STS_CTL__ERR_UNDECODABLE_EN_WIDTH 1U
+#define DSITX__DIRECT_CMD_RD_STS_CTL__ERR_UNDECODABLE_EN_WOCLR 0U
+#define DSITX__DIRECT_CMD_RD_STS_CTL__ERR_UNDECODABLE_EN_WOSET 0U
+#define DSITX__DIRECT_CMD_RD_STS_CTL__ERR_RECEIVE_EN_MASK 0x00000010U
+#define DSITX__DIRECT_CMD_RD_STS_CTL__ERR_RECEIVE_EN_SHIFT 4U
+#define DSITX__DIRECT_CMD_RD_STS_CTL__ERR_RECEIVE_EN_WIDTH 1U
+#define DSITX__DIRECT_CMD_RD_STS_CTL__ERR_RECEIVE_EN_WOCLR 0U
+#define DSITX__DIRECT_CMD_RD_STS_CTL__ERR_RECEIVE_EN_WOSET 0U
+#define DSITX__DIRECT_CMD_RD_STS_CTL__ERR_OVERSIZE_EN_MASK 0x00000020U
+#define DSITX__DIRECT_CMD_RD_STS_CTL__ERR_OVERSIZE_EN_SHIFT 5U
+#define DSITX__DIRECT_CMD_RD_STS_CTL__ERR_OVERSIZE_EN_WIDTH 1U
+#define DSITX__DIRECT_CMD_RD_STS_CTL__ERR_OVERSIZE_EN_WOCLR 0U
+#define DSITX__DIRECT_CMD_RD_STS_CTL__ERR_OVERSIZE_EN_WOSET 0U
+#define DSITX__DIRECT_CMD_RD_STS_CTL__ERR_WRONG_LENGTH_EN_MASK 0x00000040U
+#define DSITX__DIRECT_CMD_RD_STS_CTL__ERR_WRONG_LENGTH_EN_SHIFT 6U
+#define DSITX__DIRECT_CMD_RD_STS_CTL__ERR_WRONG_LENGTH_EN_WIDTH 1U
+#define DSITX__DIRECT_CMD_RD_STS_CTL__ERR_WRONG_LENGTH_EN_WOCLR 0U
+#define DSITX__DIRECT_CMD_RD_STS_CTL__ERR_WRONG_LENGTH_EN_WOSET 0U
+#define DSITX__DIRECT_CMD_RD_STS_CTL__ERR_MISSING_EOT_EN_MASK 0x00000080U
+#define DSITX__DIRECT_CMD_RD_STS_CTL__ERR_MISSING_EOT_EN_SHIFT 7U
+#define DSITX__DIRECT_CMD_RD_STS_CTL__ERR_MISSING_EOT_EN_WIDTH 1U
+#define DSITX__DIRECT_CMD_RD_STS_CTL__ERR_MISSING_EOT_EN_WOCLR 0U
+#define DSITX__DIRECT_CMD_RD_STS_CTL__ERR_MISSING_EOT_EN_WOSET 0U
+#define DSITX__DIRECT_CMD_RD_STS_CTL__ERR_EOT_WITH_ERR_EN_MASK 0x00000100U
+#define DSITX__DIRECT_CMD_RD_STS_CTL__ERR_EOT_WITH_ERR_EN_SHIFT 8U
+#define DSITX__DIRECT_CMD_RD_STS_CTL__ERR_EOT_WITH_ERR_EN_WIDTH 1U
+#define DSITX__DIRECT_CMD_RD_STS_CTL__ERR_EOT_WITH_ERR_EN_WOCLR 0U
+#define DSITX__DIRECT_CMD_RD_STS_CTL__ERR_EOT_WITH_ERR_EN_WOSET 0U
+#define DSITX__DIRECT_CMD_RD_STS_CTL__RSVD_0_MASK 0x0000FE00U
+#define DSITX__DIRECT_CMD_RD_STS_CTL__RSVD_0_SHIFT 9U
+#define DSITX__DIRECT_CMD_RD_STS_CTL__RSVD_0_WIDTH 7U
+#define DSITX__DIRECT_CMD_RD_STS_CTL__ERR_FIXED_EDGE_MASK 0x00010000U
+#define DSITX__DIRECT_CMD_RD_STS_CTL__ERR_FIXED_EDGE_SHIFT 16U
+#define DSITX__DIRECT_CMD_RD_STS_CTL__ERR_FIXED_EDGE_WIDTH 1U
+#define DSITX__DIRECT_CMD_RD_STS_CTL__ERR_FIXED_EDGE_WOCLR 0U
+#define DSITX__DIRECT_CMD_RD_STS_CTL__ERR_FIXED_EDGE_WOSET 0U
+#define DSITX__DIRECT_CMD_RD_STS_CTL__ERR_UNCORRECTABLE_EDGE_MASK 0x00020000U
+#define DSITX__DIRECT_CMD_RD_STS_CTL__ERR_UNCORRECTABLE_EDGE_SHIFT 17U
+#define DSITX__DIRECT_CMD_RD_STS_CTL__ERR_UNCORRECTABLE_EDGE_WIDTH 1U
+#define DSITX__DIRECT_CMD_RD_STS_CTL__ERR_UNCORRECTABLE_EDGE_WOCLR 0U
+#define DSITX__DIRECT_CMD_RD_STS_CTL__ERR_UNCORRECTABLE_EDGE_WOSET 0U
+#define DSITX__DIRECT_CMD_RD_STS_CTL__ERR_CHECKSUM_EDGE_MASK 0x00040000U
+#define DSITX__DIRECT_CMD_RD_STS_CTL__ERR_CHECKSUM_EDGE_SHIFT 18U
+#define DSITX__DIRECT_CMD_RD_STS_CTL__ERR_CHECKSUM_EDGE_WIDTH 1U
+#define DSITX__DIRECT_CMD_RD_STS_CTL__ERR_CHECKSUM_EDGE_WOCLR 0U
+#define DSITX__DIRECT_CMD_RD_STS_CTL__ERR_CHECKSUM_EDGE_WOSET 0U
+#define DSITX__DIRECT_CMD_RD_STS_CTL__ERR_UNDECODABLE_EDGE_MASK 0x00080000U
+#define DSITX__DIRECT_CMD_RD_STS_CTL__ERR_UNDECODABLE_EDGE_SHIFT 19U
+#define DSITX__DIRECT_CMD_RD_STS_CTL__ERR_UNDECODABLE_EDGE_WIDTH 1U
+#define DSITX__DIRECT_CMD_RD_STS_CTL__ERR_UNDECODABLE_EDGE_WOCLR 0U
+#define DSITX__DIRECT_CMD_RD_STS_CTL__ERR_UNDECODABLE_EDGE_WOSET 0U
+#define DSITX__DIRECT_CMD_RD_STS_CTL__ERR_RECEIVE_EDGE_MASK 0x00100000U
+#define DSITX__DIRECT_CMD_RD_STS_CTL__ERR_RECEIVE_EDGE_SHIFT 20U
+#define DSITX__DIRECT_CMD_RD_STS_CTL__ERR_RECEIVE_EDGE_WIDTH 1U
+#define DSITX__DIRECT_CMD_RD_STS_CTL__ERR_RECEIVE_EDGE_WOCLR 0U
+#define DSITX__DIRECT_CMD_RD_STS_CTL__ERR_RECEIVE_EDGE_WOSET 0U
+#define DSITX__DIRECT_CMD_RD_STS_CTL__ERR_OVERSIZE_EDGE_MASK 0x00200000U
+#define DSITX__DIRECT_CMD_RD_STS_CTL__ERR_OVERSIZE_EDGE_SHIFT 21U
+#define DSITX__DIRECT_CMD_RD_STS_CTL__ERR_OVERSIZE_EDGE_WIDTH 1U
+#define DSITX__DIRECT_CMD_RD_STS_CTL__ERR_OVERSIZE_EDGE_WOCLR 0U
+#define DSITX__DIRECT_CMD_RD_STS_CTL__ERR_OVERSIZE_EDGE_WOSET 0U
+#define DSITX__DIRECT_CMD_RD_STS_CTL__ERR_WRONG_LENGTH_EDGE_MASK 0x00400000U
+#define DSITX__DIRECT_CMD_RD_STS_CTL__ERR_WRONG_LENGTH_EDGE_SHIFT 22U
+#define DSITX__DIRECT_CMD_RD_STS_CTL__ERR_WRONG_LENGTH_EDGE_WIDTH 1U
+#define DSITX__DIRECT_CMD_RD_STS_CTL__ERR_WRONG_LENGTH_EDGE_WOCLR 0U
+#define DSITX__DIRECT_CMD_RD_STS_CTL__ERR_WRONG_LENGTH_EDGE_WOSET 0U
+#define DSITX__DIRECT_CMD_RD_STS_CTL__ERR_MISSING_EOT_EDGE_MASK 0x00800000U
+#define DSITX__DIRECT_CMD_RD_STS_CTL__ERR_MISSING_EOT_EDGE_SHIFT 23U
+#define DSITX__DIRECT_CMD_RD_STS_CTL__ERR_MISSING_EOT_EDGE_WIDTH 1U
+#define DSITX__DIRECT_CMD_RD_STS_CTL__ERR_MISSING_EOT_EDGE_WOCLR 0U
+#define DSITX__DIRECT_CMD_RD_STS_CTL__ERR_MISSING_EOT_EDGE_WOSET 0U
+#define DSITX__DIRECT_CMD_RD_STS_CTL__ERR_EOT_WITH_ERR_EDGE_MASK 0x01000000U
+#define DSITX__DIRECT_CMD_RD_STS_CTL__ERR_EOT_WITH_ERR_EDGE_SHIFT 24U
+#define DSITX__DIRECT_CMD_RD_STS_CTL__ERR_EOT_WITH_ERR_EDGE_WIDTH 1U
+#define DSITX__DIRECT_CMD_RD_STS_CTL__ERR_EOT_WITH_ERR_EDGE_WOCLR 0U
+#define DSITX__DIRECT_CMD_RD_STS_CTL__ERR_EOT_WITH_ERR_EDGE_WOSET 0U
+#define DSITX__DIRECT_CMD_RD_STS_CTL__RSVD_1_MASK 0xFE000000U
+#define DSITX__DIRECT_CMD_RD_STS_CTL__RSVD_1_SHIFT 25U
+#define DSITX__DIRECT_CMD_RD_STS_CTL__RSVD_1_WIDTH 7U
+
+#define DSITX__VID_MODE_STS_CTL_READ_MASK 0xFFFFFFFFU
+#define DSITX__VID_MODE_STS_CTL_WRITE_MASK 0xFFFFFFFFU
+#define DSITX__VID_MODE_STS_CTL__VSG_RUNNING_EN_MASK 0x00000001U
+#define DSITX__VID_MODE_STS_CTL__VSG_RUNNING_EN_SHIFT 0U
+#define DSITX__VID_MODE_STS_CTL__VSG_RUNNING_EN_WIDTH 1U
+#define DSITX__VID_MODE_STS_CTL__VSG_RUNNING_EN_WOCLR 0U
+#define DSITX__VID_MODE_STS_CTL__VSG_RUNNING_EN_WOSET 0U
+#define DSITX__VID_MODE_STS_CTL__ERR_MISSING_DATA_EN_MASK 0x00000002U
+#define DSITX__VID_MODE_STS_CTL__ERR_MISSING_DATA_EN_SHIFT 1U
+#define DSITX__VID_MODE_STS_CTL__ERR_MISSING_DATA_EN_WIDTH 1U
+#define DSITX__VID_MODE_STS_CTL__ERR_MISSING_DATA_EN_WOCLR 0U
+#define DSITX__VID_MODE_STS_CTL__ERR_MISSING_DATA_EN_WOSET 0U
+#define DSITX__VID_MODE_STS_CTL__ERR_MISSING_HSYNC_EN_MASK 0x00000004U
+#define DSITX__VID_MODE_STS_CTL__ERR_MISSING_HSYNC_EN_SHIFT 2U
+#define DSITX__VID_MODE_STS_CTL__ERR_MISSING_HSYNC_EN_WIDTH 1U
+#define DSITX__VID_MODE_STS_CTL__ERR_MISSING_HSYNC_EN_WOCLR 0U
+#define DSITX__VID_MODE_STS_CTL__ERR_MISSING_HSYNC_EN_WOSET 0U
+#define DSITX__VID_MODE_STS_CTL__ERR_MISSING_VSYNC_EN_MASK 0x00000008U
+#define DSITX__VID_MODE_STS_CTL__ERR_MISSING_VSYNC_EN_SHIFT 3U
+#define DSITX__VID_MODE_STS_CTL__ERR_MISSING_VSYNC_EN_WIDTH 1U
+#define DSITX__VID_MODE_STS_CTL__ERR_MISSING_VSYNC_EN_WOCLR 0U
+#define DSITX__VID_MODE_STS_CTL__ERR_MISSING_VSYNC_EN_WOSET 0U
+#define DSITX__VID_MODE_STS_CTL__ERR_SMALL_LENGTH_EN_MASK 0x00000010U
+#define DSITX__VID_MODE_STS_CTL__ERR_SMALL_LENGTH_EN_SHIFT 4U
+#define DSITX__VID_MODE_STS_CTL__ERR_SMALL_LENGTH_EN_WIDTH 1U
+#define DSITX__VID_MODE_STS_CTL__ERR_SMALL_LENGTH_EN_WOCLR 0U
+#define DSITX__VID_MODE_STS_CTL__ERR_SMALL_LENGTH_EN_WOSET 0U
+#define DSITX__VID_MODE_STS_CTL__ERR_SMALL_HEIGHT_EN_MASK 0x00000020U
+#define DSITX__VID_MODE_STS_CTL__ERR_SMALL_HEIGHT_EN_SHIFT 5U
+#define DSITX__VID_MODE_STS_CTL__ERR_SMALL_HEIGHT_EN_WIDTH 1U
+#define DSITX__VID_MODE_STS_CTL__ERR_SMALL_HEIGHT_EN_WOCLR 0U
+#define DSITX__VID_MODE_STS_CTL__ERR_SMALL_HEIGHT_EN_WOSET 0U
+#define DSITX__VID_MODE_STS_CTL__ERR_BURSTWRITE_EN_MASK 0x00000040U
+#define DSITX__VID_MODE_STS_CTL__ERR_BURSTWRITE_EN_SHIFT 6U
+#define DSITX__VID_MODE_STS_CTL__ERR_BURSTWRITE_EN_WIDTH 1U
+#define DSITX__VID_MODE_STS_CTL__ERR_BURSTWRITE_EN_WOCLR 0U
+#define DSITX__VID_MODE_STS_CTL__ERR_BURSTWRITE_EN_WOSET 0U
+#define DSITX__VID_MODE_STS_CTL__ERR_LINEWRITE_EN_MASK 0x00000080U
+#define DSITX__VID_MODE_STS_CTL__ERR_LINEWRITE_EN_SHIFT 7U
+#define DSITX__VID_MODE_STS_CTL__ERR_LINEWRITE_EN_WIDTH 1U
+#define DSITX__VID_MODE_STS_CTL__ERR_LINEWRITE_EN_WOCLR 0U
+#define DSITX__VID_MODE_STS_CTL__ERR_LINEWRITE_EN_WOSET 0U
+#define DSITX__VID_MODE_STS_CTL__ERR_LONGREAD_EN_MASK 0x00000100U
+#define DSITX__VID_MODE_STS_CTL__ERR_LONGREAD_EN_SHIFT 8U
+#define DSITX__VID_MODE_STS_CTL__ERR_LONGREAD_EN_WIDTH 1U
+#define DSITX__VID_MODE_STS_CTL__ERR_LONGREAD_EN_WOCLR 0U
+#define DSITX__VID_MODE_STS_CTL__ERR_LONGREAD_EN_WOSET 0U
+#define DSITX__VID_MODE_STS_CTL__ERR_VRS_WRONG_LENGTH_EN_MASK 0x00000200U
+#define DSITX__VID_MODE_STS_CTL__ERR_VRS_WRONG_LENGTH_EN_SHIFT 9U
+#define DSITX__VID_MODE_STS_CTL__ERR_VRS_WRONG_LENGTH_EN_WIDTH 1U
+#define DSITX__VID_MODE_STS_CTL__ERR_VRS_WRONG_LENGTH_EN_WOCLR 0U
+#define DSITX__VID_MODE_STS_CTL__ERR_VRS_WRONG_LENGTH_EN_WOSET 0U
+#define DSITX__VID_MODE_STS_CTL__VSG_RECOVERY_EN_MASK 0x00000400U
+#define DSITX__VID_MODE_STS_CTL__VSG_RECOVERY_EN_SHIFT 10U
+#define DSITX__VID_MODE_STS_CTL__VSG_RECOVERY_EN_WIDTH 1U
+#define DSITX__VID_MODE_STS_CTL__VSG_RECOVERY_EN_WOCLR 0U
+#define DSITX__VID_MODE_STS_CTL__VSG_RECOVERY_EN_WOSET 0U
+#define DSITX__VID_MODE_STS_CTL__RSVD_0_MASK 0x0000F800U
+#define DSITX__VID_MODE_STS_CTL__RSVD_0_SHIFT 11U
+#define DSITX__VID_MODE_STS_CTL__RSVD_0_WIDTH 5U
+#define DSITX__VID_MODE_STS_CTL__VSG_RUNNING_EDGE_MASK 0x00010000U
+#define DSITX__VID_MODE_STS_CTL__VSG_RUNNING_EDGE_SHIFT 16U
+#define DSITX__VID_MODE_STS_CTL__VSG_RUNNING_EDGE_WIDTH 1U
+#define DSITX__VID_MODE_STS_CTL__VSG_RUNNING_EDGE_WOCLR 0U
+#define DSITX__VID_MODE_STS_CTL__VSG_RUNNING_EDGE_WOSET 0U
+#define DSITX__VID_MODE_STS_CTL__ERR_MISSING_DATA_EDGE_MASK 0x00020000U
+#define DSITX__VID_MODE_STS_CTL__ERR_MISSING_DATA_EDGE_SHIFT 17U
+#define DSITX__VID_MODE_STS_CTL__ERR_MISSING_DATA_EDGE_WIDTH 1U
+#define DSITX__VID_MODE_STS_CTL__ERR_MISSING_DATA_EDGE_WOCLR 0U
+#define DSITX__VID_MODE_STS_CTL__ERR_MISSING_DATA_EDGE_WOSET 0U
+#define DSITX__VID_MODE_STS_CTL__ERR_MISSING_HSYNC_EDGE_MASK 0x00040000U
+#define DSITX__VID_MODE_STS_CTL__ERR_MISSING_HSYNC_EDGE_SHIFT 18U
+#define DSITX__VID_MODE_STS_CTL__ERR_MISSING_HSYNC_EDGE_WIDTH 1U
+#define DSITX__VID_MODE_STS_CTL__ERR_MISSING_HSYNC_EDGE_WOCLR 0U
+#define DSITX__VID_MODE_STS_CTL__ERR_MISSING_HSYNC_EDGE_WOSET 0U
+#define DSITX__VID_MODE_STS_CTL__ERR_MISSING_VSYNC_EDGE_MASK 0x00080000U
+#define DSITX__VID_MODE_STS_CTL__ERR_MISSING_VSYNC_EDGE_SHIFT 19U
+#define DSITX__VID_MODE_STS_CTL__ERR_MISSING_VSYNC_EDGE_WIDTH 1U
+#define DSITX__VID_MODE_STS_CTL__ERR_MISSING_VSYNC_EDGE_WOCLR 0U
+#define DSITX__VID_MODE_STS_CTL__ERR_MISSING_VSYNC_EDGE_WOSET 0U
+#define DSITX__VID_MODE_STS_CTL__ERR_SMALL_LENGTH_EDGE_MASK 0x00100000U
+#define DSITX__VID_MODE_STS_CTL__ERR_SMALL_LENGTH_EDGE_SHIFT 20U
+#define DSITX__VID_MODE_STS_CTL__ERR_SMALL_LENGTH_EDGE_WIDTH 1U
+#define DSITX__VID_MODE_STS_CTL__ERR_SMALL_LENGTH_EDGE_WOCLR 0U
+#define DSITX__VID_MODE_STS_CTL__ERR_SMALL_LENGTH_EDGE_WOSET 0U
+#define DSITX__VID_MODE_STS_CTL__ERR_SMALL_HEIGHT_EDGE_MASK 0x00200000U
+#define DSITX__VID_MODE_STS_CTL__ERR_SMALL_HEIGHT_EDGE_SHIFT 21U
+#define DSITX__VID_MODE_STS_CTL__ERR_SMALL_HEIGHT_EDGE_WIDTH 1U
+#define DSITX__VID_MODE_STS_CTL__ERR_SMALL_HEIGHT_EDGE_WOCLR 0U
+#define DSITX__VID_MODE_STS_CTL__ERR_SMALL_HEIGHT_EDGE_WOSET 0U
+#define DSITX__VID_MODE_STS_CTL__ERR_BURSTWRITE_EDGE_MASK 0x00400000U
+#define DSITX__VID_MODE_STS_CTL__ERR_BURSTWRITE_EDGE_SHIFT 22U
+#define DSITX__VID_MODE_STS_CTL__ERR_BURSTWRITE_EDGE_WIDTH 1U
+#define DSITX__VID_MODE_STS_CTL__ERR_BURSTWRITE_EDGE_WOCLR 0U
+#define DSITX__VID_MODE_STS_CTL__ERR_BURSTWRITE_EDGE_WOSET 0U
+#define DSITX__VID_MODE_STS_CTL__ERR_LINEWRITE_EDGE_MASK 0x00800000U
+#define DSITX__VID_MODE_STS_CTL__ERR_LINEWRITE_EDGE_SHIFT 23U
+#define DSITX__VID_MODE_STS_CTL__ERR_LINEWRITE_EDGE_WIDTH 1U
+#define DSITX__VID_MODE_STS_CTL__ERR_LINEWRITE_EDGE_WOCLR 0U
+#define DSITX__VID_MODE_STS_CTL__ERR_LINEWRITE_EDGE_WOSET 0U
+#define DSITX__VID_MODE_STS_CTL__ERR_LONGREAD_EDGE_MASK 0x01000000U
+#define DSITX__VID_MODE_STS_CTL__ERR_LONGREAD_EDGE_SHIFT 24U
+#define DSITX__VID_MODE_STS_CTL__ERR_LONGREAD_EDGE_WIDTH 1U
+#define DSITX__VID_MODE_STS_CTL__ERR_LONGREAD_EDGE_WOCLR 0U
+#define DSITX__VID_MODE_STS_CTL__ERR_LONGREAD_EDGE_WOSET 0U
+#define DSITX__VID_MODE_STS_CTL__ERR_VRS_WRONG_LENGTH_EDGE_MASK 0x02000000U
+#define DSITX__VID_MODE_STS_CTL__ERR_VRS_WRONG_LENGTH_EDGE_SHIFT 25U
+#define DSITX__VID_MODE_STS_CTL__ERR_VRS_WRONG_LENGTH_EDGE_WIDTH 1U
+#define DSITX__VID_MODE_STS_CTL__ERR_VRS_WRONG_LENGTH_EDGE_WOCLR 0U
+#define DSITX__VID_MODE_STS_CTL__ERR_VRS_WRONG_LENGTH_EDGE_WOSET 0U
+#define DSITX__VID_MODE_STS_CTL__VSG_RECOVERY_EDGE_MASK 0x04000000U
+#define DSITX__VID_MODE_STS_CTL__VSG_RECOVERY_EDGE_SHIFT 26U
+#define DSITX__VID_MODE_STS_CTL__VSG_RECOVERY_EDGE_WIDTH 1U
+#define DSITX__VID_MODE_STS_CTL__VSG_RECOVERY_EDGE_WOCLR 0U
+#define DSITX__VID_MODE_STS_CTL__VSG_RECOVERY_EDGE_WOSET 0U
+#define DSITX__VID_MODE_STS_CTL__RSVD_1_MASK 0xF8000000U
+#define DSITX__VID_MODE_STS_CTL__RSVD_1_SHIFT 27U
+#define DSITX__VID_MODE_STS_CTL__RSVD_1_WIDTH 5U
+
+#define DSITX__TVG_STS_CTL_READ_MASK 0xFFFFFFFFU
+#define DSITX__TVG_STS_CTL_WRITE_MASK 0xFFFFFFFFU
+#define DSITX__TVG_STS_CTL__TVG_STS_EN_MASK 0x00000001U
+#define DSITX__TVG_STS_CTL__TVG_STS_EN_SHIFT 0U
+#define DSITX__TVG_STS_CTL__TVG_STS_EN_WIDTH 1U
+#define DSITX__TVG_STS_CTL__TVG_STS_EN_WOCLR 0U
+#define DSITX__TVG_STS_CTL__TVG_STS_EN_WOSET 0U
+#define DSITX__TVG_STS_CTL__RSVD_0_MASK 0x0000FFFEU
+#define DSITX__TVG_STS_CTL__RSVD_0_SHIFT 1U
+#define DSITX__TVG_STS_CTL__RSVD_0_WIDTH 15U
+#define DSITX__TVG_STS_CTL__TVG_STS_EDGE_MASK 0x00010000U
+#define DSITX__TVG_STS_CTL__TVG_STS_EDGE_SHIFT 16U
+#define DSITX__TVG_STS_CTL__TVG_STS_EDGE_WIDTH 1U
+#define DSITX__TVG_STS_CTL__TVG_STS_EDGE_WOCLR 0U
+#define DSITX__TVG_STS_CTL__TVG_STS_EDGE_WOSET 0U
+#define DSITX__TVG_STS_CTL__RSVD_1_MASK 0xFFFE0000U
+#define DSITX__TVG_STS_CTL__RSVD_1_SHIFT 17U
+#define DSITX__TVG_STS_CTL__RSVD_1_WIDTH 15U
+
+#define DSITX__MCTL_DPHY_ERR_CTL1_READ_MASK 0xFFFFFFFFU
+#define DSITX__MCTL_DPHY_ERR_CTL1_WRITE_MASK 0xFFFFFFFFU
+#define DSITX__MCTL_DPHY_ERR_CTL1__RSVD_0_MASK 0x0000003FU
+#define DSITX__MCTL_DPHY_ERR_CTL1__RSVD_0_SHIFT 0U
+#define DSITX__MCTL_DPHY_ERR_CTL1__RSVD_0_WIDTH 6U
+#define DSITX__MCTL_DPHY_ERR_CTL1__ERR_ESC_1_EN_MASK 0x00000040U
+#define DSITX__MCTL_DPHY_ERR_CTL1__ERR_ESC_1_EN_SHIFT 6U
+#define DSITX__MCTL_DPHY_ERR_CTL1__ERR_ESC_1_EN_WIDTH 1U
+#define DSITX__MCTL_DPHY_ERR_CTL1__ERR_ESC_1_EN_WOCLR 0U
+#define DSITX__MCTL_DPHY_ERR_CTL1__ERR_ESC_1_EN_WOSET 0U
+#define DSITX__MCTL_DPHY_ERR_CTL1__ERR_ESC_2_EN_MASK 0x00000080U
+#define DSITX__MCTL_DPHY_ERR_CTL1__ERR_ESC_2_EN_SHIFT 7U
+#define DSITX__MCTL_DPHY_ERR_CTL1__ERR_ESC_2_EN_WIDTH 1U
+#define DSITX__MCTL_DPHY_ERR_CTL1__ERR_ESC_2_EN_WOCLR 0U
+#define DSITX__MCTL_DPHY_ERR_CTL1__ERR_ESC_2_EN_WOSET 0U
+#define DSITX__MCTL_DPHY_ERR_CTL1__ERR_ESC_3_EN_MASK 0x00000100U
+#define DSITX__MCTL_DPHY_ERR_CTL1__ERR_ESC_3_EN_SHIFT 8U
+#define DSITX__MCTL_DPHY_ERR_CTL1__ERR_ESC_3_EN_WIDTH 1U
+#define DSITX__MCTL_DPHY_ERR_CTL1__ERR_ESC_3_EN_WOCLR 0U
+#define DSITX__MCTL_DPHY_ERR_CTL1__ERR_ESC_3_EN_WOSET 0U
+#define DSITX__MCTL_DPHY_ERR_CTL1__ERR_ESC_4_EN_MASK 0x00000200U
+#define DSITX__MCTL_DPHY_ERR_CTL1__ERR_ESC_4_EN_SHIFT 9U
+#define DSITX__MCTL_DPHY_ERR_CTL1__ERR_ESC_4_EN_WIDTH 1U
+#define DSITX__MCTL_DPHY_ERR_CTL1__ERR_ESC_4_EN_WOCLR 0U
+#define DSITX__MCTL_DPHY_ERR_CTL1__ERR_ESC_4_EN_WOSET 0U
+#define DSITX__MCTL_DPHY_ERR_CTL1__ERR_SYNCESC_1_EN_MASK 0x00000400U
+#define DSITX__MCTL_DPHY_ERR_CTL1__ERR_SYNCESC_1_EN_SHIFT 10U
+#define DSITX__MCTL_DPHY_ERR_CTL1__ERR_SYNCESC_1_EN_WIDTH 1U
+#define DSITX__MCTL_DPHY_ERR_CTL1__ERR_SYNCESC_1_EN_WOCLR 0U
+#define DSITX__MCTL_DPHY_ERR_CTL1__ERR_SYNCESC_1_EN_WOSET 0U
+#define DSITX__MCTL_DPHY_ERR_CTL1__ERR_SYNCESC_2_EN_MASK 0x00000800U
+#define DSITX__MCTL_DPHY_ERR_CTL1__ERR_SYNCESC_2_EN_SHIFT 11U
+#define DSITX__MCTL_DPHY_ERR_CTL1__ERR_SYNCESC_2_EN_WIDTH 1U
+#define DSITX__MCTL_DPHY_ERR_CTL1__ERR_SYNCESC_2_EN_WOCLR 0U
+#define DSITX__MCTL_DPHY_ERR_CTL1__ERR_SYNCESC_2_EN_WOSET 0U
+#define DSITX__MCTL_DPHY_ERR_CTL1__ERR_SYNCESC_3_EN_MASK 0x00001000U
+#define DSITX__MCTL_DPHY_ERR_CTL1__ERR_SYNCESC_3_EN_SHIFT 12U
+#define DSITX__MCTL_DPHY_ERR_CTL1__ERR_SYNCESC_3_EN_WIDTH 1U
+#define DSITX__MCTL_DPHY_ERR_CTL1__ERR_SYNCESC_3_EN_WOCLR 0U
+#define DSITX__MCTL_DPHY_ERR_CTL1__ERR_SYNCESC_3_EN_WOSET 0U
+#define DSITX__MCTL_DPHY_ERR_CTL1__ERR_SYNCESC_4_EN_MASK 0x00002000U
+#define DSITX__MCTL_DPHY_ERR_CTL1__ERR_SYNCESC_4_EN_SHIFT 13U
+#define DSITX__MCTL_DPHY_ERR_CTL1__ERR_SYNCESC_4_EN_WIDTH 1U
+#define DSITX__MCTL_DPHY_ERR_CTL1__ERR_SYNCESC_4_EN_WOCLR 0U
+#define DSITX__MCTL_DPHY_ERR_CTL1__ERR_SYNCESC_4_EN_WOSET 0U
+#define DSITX__MCTL_DPHY_ERR_CTL1__ERR_CONTROL_1_EN_MASK 0x00004000U
+#define DSITX__MCTL_DPHY_ERR_CTL1__ERR_CONTROL_1_EN_SHIFT 14U
+#define DSITX__MCTL_DPHY_ERR_CTL1__ERR_CONTROL_1_EN_WIDTH 1U
+#define DSITX__MCTL_DPHY_ERR_CTL1__ERR_CONTROL_1_EN_WOCLR 0U
+#define DSITX__MCTL_DPHY_ERR_CTL1__ERR_CONTROL_1_EN_WOSET 0U
+#define DSITX__MCTL_DPHY_ERR_CTL1__ERR_CONTROL_2_EN_MASK 0x00008000U
+#define DSITX__MCTL_DPHY_ERR_CTL1__ERR_CONTROL_2_EN_SHIFT 15U
+#define DSITX__MCTL_DPHY_ERR_CTL1__ERR_CONTROL_2_EN_WIDTH 1U
+#define DSITX__MCTL_DPHY_ERR_CTL1__ERR_CONTROL_2_EN_WOCLR 0U
+#define DSITX__MCTL_DPHY_ERR_CTL1__ERR_CONTROL_2_EN_WOSET 0U
+#define DSITX__MCTL_DPHY_ERR_CTL1__ERR_CONTROL_3_EN_MASK 0x00010000U
+#define DSITX__MCTL_DPHY_ERR_CTL1__ERR_CONTROL_3_EN_SHIFT 16U
+#define DSITX__MCTL_DPHY_ERR_CTL1__ERR_CONTROL_3_EN_WIDTH 1U
+#define DSITX__MCTL_DPHY_ERR_CTL1__ERR_CONTROL_3_EN_WOCLR 0U
+#define DSITX__MCTL_DPHY_ERR_CTL1__ERR_CONTROL_3_EN_WOSET 0U
+#define DSITX__MCTL_DPHY_ERR_CTL1__ERR_CONTROL_4_EN_MASK 0x00020000U
+#define DSITX__MCTL_DPHY_ERR_CTL1__ERR_CONTROL_4_EN_SHIFT 17U
+#define DSITX__MCTL_DPHY_ERR_CTL1__ERR_CONTROL_4_EN_WIDTH 1U
+#define DSITX__MCTL_DPHY_ERR_CTL1__ERR_CONTROL_4_EN_WOCLR 0U
+#define DSITX__MCTL_DPHY_ERR_CTL1__ERR_CONTROL_4_EN_WOSET 0U
+#define DSITX__MCTL_DPHY_ERR_CTL1__ERR_CONT_LP0_1_EN_MASK 0x00040000U
+#define DSITX__MCTL_DPHY_ERR_CTL1__ERR_CONT_LP0_1_EN_SHIFT 18U
+#define DSITX__MCTL_DPHY_ERR_CTL1__ERR_CONT_LP0_1_EN_WIDTH 1U
+#define DSITX__MCTL_DPHY_ERR_CTL1__ERR_CONT_LP0_1_EN_WOCLR 0U
+#define DSITX__MCTL_DPHY_ERR_CTL1__ERR_CONT_LP0_1_EN_WOSET 0U
+#define DSITX__MCTL_DPHY_ERR_CTL1__ERR_CONT_LP0_2_EN_MASK 0x00080000U
+#define DSITX__MCTL_DPHY_ERR_CTL1__ERR_CONT_LP0_2_EN_SHIFT 19U
+#define DSITX__MCTL_DPHY_ERR_CTL1__ERR_CONT_LP0_2_EN_WIDTH 1U
+#define DSITX__MCTL_DPHY_ERR_CTL1__ERR_CONT_LP0_2_EN_WOCLR 0U
+#define DSITX__MCTL_DPHY_ERR_CTL1__ERR_CONT_LP0_2_EN_WOSET 0U
+#define DSITX__MCTL_DPHY_ERR_CTL1__ERR_CONT_LP0_3_EN_MASK 0x00100000U
+#define DSITX__MCTL_DPHY_ERR_CTL1__ERR_CONT_LP0_3_EN_SHIFT 20U
+#define DSITX__MCTL_DPHY_ERR_CTL1__ERR_CONT_LP0_3_EN_WIDTH 1U
+#define DSITX__MCTL_DPHY_ERR_CTL1__ERR_CONT_LP0_3_EN_WOCLR 0U
+#define DSITX__MCTL_DPHY_ERR_CTL1__ERR_CONT_LP0_3_EN_WOSET 0U
+#define DSITX__MCTL_DPHY_ERR_CTL1__ERR_CONT_LP0_4_EN_MASK 0x00200000U
+#define DSITX__MCTL_DPHY_ERR_CTL1__ERR_CONT_LP0_4_EN_SHIFT 21U
+#define DSITX__MCTL_DPHY_ERR_CTL1__ERR_CONT_LP0_4_EN_WIDTH 1U
+#define DSITX__MCTL_DPHY_ERR_CTL1__ERR_CONT_LP0_4_EN_WOCLR 0U
+#define DSITX__MCTL_DPHY_ERR_CTL1__ERR_CONT_LP0_4_EN_WOSET 0U
+#define DSITX__MCTL_DPHY_ERR_CTL1__ERR_CONT_LP1_1_EN_MASK 0x00400000U
+#define DSITX__MCTL_DPHY_ERR_CTL1__ERR_CONT_LP1_1_EN_SHIFT 22U
+#define DSITX__MCTL_DPHY_ERR_CTL1__ERR_CONT_LP1_1_EN_WIDTH 1U
+#define DSITX__MCTL_DPHY_ERR_CTL1__ERR_CONT_LP1_1_EN_WOCLR 0U
+#define DSITX__MCTL_DPHY_ERR_CTL1__ERR_CONT_LP1_1_EN_WOSET 0U
+#define DSITX__MCTL_DPHY_ERR_CTL1__ERR_CONT_LP1_2_EN_MASK 0x00800000U
+#define DSITX__MCTL_DPHY_ERR_CTL1__ERR_CONT_LP1_2_EN_SHIFT 23U
+#define DSITX__MCTL_DPHY_ERR_CTL1__ERR_CONT_LP1_2_EN_WIDTH 1U
+#define DSITX__MCTL_DPHY_ERR_CTL1__ERR_CONT_LP1_2_EN_WOCLR 0U
+#define DSITX__MCTL_DPHY_ERR_CTL1__ERR_CONT_LP1_2_EN_WOSET 0U
+#define DSITX__MCTL_DPHY_ERR_CTL1__ERR_CONT_LP1_3_EN_MASK 0x01000000U
+#define DSITX__MCTL_DPHY_ERR_CTL1__ERR_CONT_LP1_3_EN_SHIFT 24U
+#define DSITX__MCTL_DPHY_ERR_CTL1__ERR_CONT_LP1_3_EN_WIDTH 1U
+#define DSITX__MCTL_DPHY_ERR_CTL1__ERR_CONT_LP1_3_EN_WOCLR 0U
+#define DSITX__MCTL_DPHY_ERR_CTL1__ERR_CONT_LP1_3_EN_WOSET 0U
+#define DSITX__MCTL_DPHY_ERR_CTL1__ERR_CONT_LP1_4_EN_MASK 0x02000000U
+#define DSITX__MCTL_DPHY_ERR_CTL1__ERR_CONT_LP1_4_EN_SHIFT 25U
+#define DSITX__MCTL_DPHY_ERR_CTL1__ERR_CONT_LP1_4_EN_WIDTH 1U
+#define DSITX__MCTL_DPHY_ERR_CTL1__ERR_CONT_LP1_4_EN_WOCLR 0U
+#define DSITX__MCTL_DPHY_ERR_CTL1__ERR_CONT_LP1_4_EN_WOSET 0U
+#define DSITX__MCTL_DPHY_ERR_CTL1__RSVD_1_MASK 0xFC000000U
+#define DSITX__MCTL_DPHY_ERR_CTL1__RSVD_1_SHIFT 26U
+#define DSITX__MCTL_DPHY_ERR_CTL1__RSVD_1_WIDTH 6U
+
+#define DSITX__MCTL_DPHY_ERR_CTL2_READ_MASK 0xFFFFFFFFU
+#define DSITX__MCTL_DPHY_ERR_CTL2_WRITE_MASK 0xFFFFFFFFU
+#define DSITX__MCTL_DPHY_ERR_CTL2__ERR_ESC_1_EDGE_MASK 0x00000001U
+#define DSITX__MCTL_DPHY_ERR_CTL2__ERR_ESC_1_EDGE_SHIFT 0U
+#define DSITX__MCTL_DPHY_ERR_CTL2__ERR_ESC_1_EDGE_WIDTH 1U
+#define DSITX__MCTL_DPHY_ERR_CTL2__ERR_ESC_1_EDGE_WOCLR 0U
+#define DSITX__MCTL_DPHY_ERR_CTL2__ERR_ESC_1_EDGE_WOSET 0U
+#define DSITX__MCTL_DPHY_ERR_CTL2__ERR_ESC_2_EDGE_MASK 0x00000002U
+#define DSITX__MCTL_DPHY_ERR_CTL2__ERR_ESC_2_EDGE_SHIFT 1U
+#define DSITX__MCTL_DPHY_ERR_CTL2__ERR_ESC_2_EDGE_WIDTH 1U
+#define DSITX__MCTL_DPHY_ERR_CTL2__ERR_ESC_2_EDGE_WOCLR 0U
+#define DSITX__MCTL_DPHY_ERR_CTL2__ERR_ESC_2_EDGE_WOSET 0U
+#define DSITX__MCTL_DPHY_ERR_CTL2__ERR_ESC_3_EDGE_MASK 0x00000004U
+#define DSITX__MCTL_DPHY_ERR_CTL2__ERR_ESC_3_EDGE_SHIFT 2U
+#define DSITX__MCTL_DPHY_ERR_CTL2__ERR_ESC_3_EDGE_WIDTH 1U
+#define DSITX__MCTL_DPHY_ERR_CTL2__ERR_ESC_3_EDGE_WOCLR 0U
+#define DSITX__MCTL_DPHY_ERR_CTL2__ERR_ESC_3_EDGE_WOSET 0U
+#define DSITX__MCTL_DPHY_ERR_CTL2__ERR_ESC_4_EDGE_MASK 0x00000008U
+#define DSITX__MCTL_DPHY_ERR_CTL2__ERR_ESC_4_EDGE_SHIFT 3U
+#define DSITX__MCTL_DPHY_ERR_CTL2__ERR_ESC_4_EDGE_WIDTH 1U
+#define DSITX__MCTL_DPHY_ERR_CTL2__ERR_ESC_4_EDGE_WOCLR 0U
+#define DSITX__MCTL_DPHY_ERR_CTL2__ERR_ESC_4_EDGE_WOSET 0U
+#define DSITX__MCTL_DPHY_ERR_CTL2__ERR_SYNCESC_1_EDGE_MASK 0x00000010U
+#define DSITX__MCTL_DPHY_ERR_CTL2__ERR_SYNCESC_1_EDGE_SHIFT 4U
+#define DSITX__MCTL_DPHY_ERR_CTL2__ERR_SYNCESC_1_EDGE_WIDTH 1U
+#define DSITX__MCTL_DPHY_ERR_CTL2__ERR_SYNCESC_1_EDGE_WOCLR 0U
+#define DSITX__MCTL_DPHY_ERR_CTL2__ERR_SYNCESC_1_EDGE_WOSET 0U
+#define DSITX__MCTL_DPHY_ERR_CTL2__ERR_SYNCESC_2_EDGE_MASK 0x00000020U
+#define DSITX__MCTL_DPHY_ERR_CTL2__ERR_SYNCESC_2_EDGE_SHIFT 5U
+#define DSITX__MCTL_DPHY_ERR_CTL2__ERR_SYNCESC_2_EDGE_WIDTH 1U
+#define DSITX__MCTL_DPHY_ERR_CTL2__ERR_SYNCESC_2_EDGE_WOCLR 0U
+#define DSITX__MCTL_DPHY_ERR_CTL2__ERR_SYNCESC_2_EDGE_WOSET 0U
+#define DSITX__MCTL_DPHY_ERR_CTL2__ERR_SYNCESC_3_EDGE_MASK 0x00000040U
+#define DSITX__MCTL_DPHY_ERR_CTL2__ERR_SYNCESC_3_EDGE_SHIFT 6U
+#define DSITX__MCTL_DPHY_ERR_CTL2__ERR_SYNCESC_3_EDGE_WIDTH 1U
+#define DSITX__MCTL_DPHY_ERR_CTL2__ERR_SYNCESC_3_EDGE_WOCLR 0U
+#define DSITX__MCTL_DPHY_ERR_CTL2__ERR_SYNCESC_3_EDGE_WOSET 0U
+#define DSITX__MCTL_DPHY_ERR_CTL2__ERR_SYNCESC_4_EDGE_MASK 0x00000080U
+#define DSITX__MCTL_DPHY_ERR_CTL2__ERR_SYNCESC_4_EDGE_SHIFT 7U
+#define DSITX__MCTL_DPHY_ERR_CTL2__ERR_SYNCESC_4_EDGE_WIDTH 1U
+#define DSITX__MCTL_DPHY_ERR_CTL2__ERR_SYNCESC_4_EDGE_WOCLR 0U
+#define DSITX__MCTL_DPHY_ERR_CTL2__ERR_SYNCESC_4_EDGE_WOSET 0U
+#define DSITX__MCTL_DPHY_ERR_CTL2__ERR_CONTROL_1_EDGE_MASK 0x00000100U
+#define DSITX__MCTL_DPHY_ERR_CTL2__ERR_CONTROL_1_EDGE_SHIFT 8U
+#define DSITX__MCTL_DPHY_ERR_CTL2__ERR_CONTROL_1_EDGE_WIDTH 1U
+#define DSITX__MCTL_DPHY_ERR_CTL2__ERR_CONTROL_1_EDGE_WOCLR 0U
+#define DSITX__MCTL_DPHY_ERR_CTL2__ERR_CONTROL_1_EDGE_WOSET 0U
+#define DSITX__MCTL_DPHY_ERR_CTL2__ERR_CONTROL_2_EDGE_MASK 0x00000200U
+#define DSITX__MCTL_DPHY_ERR_CTL2__ERR_CONTROL_2_EDGE_SHIFT 9U
+#define DSITX__MCTL_DPHY_ERR_CTL2__ERR_CONTROL_2_EDGE_WIDTH 1U
+#define DSITX__MCTL_DPHY_ERR_CTL2__ERR_CONTROL_2_EDGE_WOCLR 0U
+#define DSITX__MCTL_DPHY_ERR_CTL2__ERR_CONTROL_2_EDGE_WOSET 0U
+#define DSITX__MCTL_DPHY_ERR_CTL2__ERR_CONTROL_3_EDGE_MASK 0x00000400U
+#define DSITX__MCTL_DPHY_ERR_CTL2__ERR_CONTROL_3_EDGE_SHIFT 10U
+#define DSITX__MCTL_DPHY_ERR_CTL2__ERR_CONTROL_3_EDGE_WIDTH 1U
+#define DSITX__MCTL_DPHY_ERR_CTL2__ERR_CONTROL_3_EDGE_WOCLR 0U
+#define DSITX__MCTL_DPHY_ERR_CTL2__ERR_CONTROL_3_EDGE_WOSET 0U
+#define DSITX__MCTL_DPHY_ERR_CTL2__ERR_CONTROL_4_EDGE_MASK 0x00000800U
+#define DSITX__MCTL_DPHY_ERR_CTL2__ERR_CONTROL_4_EDGE_SHIFT 11U
+#define DSITX__MCTL_DPHY_ERR_CTL2__ERR_CONTROL_4_EDGE_WIDTH 1U
+#define DSITX__MCTL_DPHY_ERR_CTL2__ERR_CONTROL_4_EDGE_WOCLR 0U
+#define DSITX__MCTL_DPHY_ERR_CTL2__ERR_CONTROL_4_EDGE_WOSET 0U
+#define DSITX__MCTL_DPHY_ERR_CTL2__ERR_CONT_LP0_1_EDGE_MASK 0x00001000U
+#define DSITX__MCTL_DPHY_ERR_CTL2__ERR_CONT_LP0_1_EDGE_SHIFT 12U
+#define DSITX__MCTL_DPHY_ERR_CTL2__ERR_CONT_LP0_1_EDGE_WIDTH 1U
+#define DSITX__MCTL_DPHY_ERR_CTL2__ERR_CONT_LP0_1_EDGE_WOCLR 0U
+#define DSITX__MCTL_DPHY_ERR_CTL2__ERR_CONT_LP0_1_EDGE_WOSET 0U
+#define DSITX__MCTL_DPHY_ERR_CTL2__ERR_CONT_LP0_2_EDGE_MASK 0x00002000U
+#define DSITX__MCTL_DPHY_ERR_CTL2__ERR_CONT_LP0_2_EDGE_SHIFT 13U
+#define DSITX__MCTL_DPHY_ERR_CTL2__ERR_CONT_LP0_2_EDGE_WIDTH 1U
+#define DSITX__MCTL_DPHY_ERR_CTL2__ERR_CONT_LP0_2_EDGE_WOCLR 0U
+#define DSITX__MCTL_DPHY_ERR_CTL2__ERR_CONT_LP0_2_EDGE_WOSET 0U
+#define DSITX__MCTL_DPHY_ERR_CTL2__ERR_CONT_LP0_3_EDGE_MASK 0x00004000U
+#define DSITX__MCTL_DPHY_ERR_CTL2__ERR_CONT_LP0_3_EDGE_SHIFT 14U
+#define DSITX__MCTL_DPHY_ERR_CTL2__ERR_CONT_LP0_3_EDGE_WIDTH 1U
+#define DSITX__MCTL_DPHY_ERR_CTL2__ERR_CONT_LP0_3_EDGE_WOCLR 0U
+#define DSITX__MCTL_DPHY_ERR_CTL2__ERR_CONT_LP0_3_EDGE_WOSET 0U
+#define DSITX__MCTL_DPHY_ERR_CTL2__ERR_CONT_LP0_4_EDGE_MASK 0x00008000U
+#define DSITX__MCTL_DPHY_ERR_CTL2__ERR_CONT_LP0_4_EDGE_SHIFT 15U
+#define DSITX__MCTL_DPHY_ERR_CTL2__ERR_CONT_LP0_4_EDGE_WIDTH 1U
+#define DSITX__MCTL_DPHY_ERR_CTL2__ERR_CONT_LP0_4_EDGE_WOCLR 0U
+#define DSITX__MCTL_DPHY_ERR_CTL2__ERR_CONT_LP0_4_EDGE_WOSET 0U
+#define DSITX__MCTL_DPHY_ERR_CTL2__ERR_CONT_LP1_1_EDGE_MASK 0x00010000U
+#define DSITX__MCTL_DPHY_ERR_CTL2__ERR_CONT_LP1_1_EDGE_SHIFT 16U
+#define DSITX__MCTL_DPHY_ERR_CTL2__ERR_CONT_LP1_1_EDGE_WIDTH 1U
+#define DSITX__MCTL_DPHY_ERR_CTL2__ERR_CONT_LP1_1_EDGE_WOCLR 0U
+#define DSITX__MCTL_DPHY_ERR_CTL2__ERR_CONT_LP1_1_EDGE_WOSET 0U
+#define DSITX__MCTL_DPHY_ERR_CTL2__ERR_CONT_LP1_2_EDGE_MASK 0x00020000U
+#define DSITX__MCTL_DPHY_ERR_CTL2__ERR_CONT_LP1_2_EDGE_SHIFT 17U
+#define DSITX__MCTL_DPHY_ERR_CTL2__ERR_CONT_LP1_2_EDGE_WIDTH 1U
+#define DSITX__MCTL_DPHY_ERR_CTL2__ERR_CONT_LP1_2_EDGE_WOCLR 0U
+#define DSITX__MCTL_DPHY_ERR_CTL2__ERR_CONT_LP1_2_EDGE_WOSET 0U
+#define DSITX__MCTL_DPHY_ERR_CTL2__ERR_CONT_LP1_3_EDGE_MASK 0x00040000U
+#define DSITX__MCTL_DPHY_ERR_CTL2__ERR_CONT_LP1_3_EDGE_SHIFT 18U
+#define DSITX__MCTL_DPHY_ERR_CTL2__ERR_CONT_LP1_3_EDGE_WIDTH 1U
+#define DSITX__MCTL_DPHY_ERR_CTL2__ERR_CONT_LP1_3_EDGE_WOCLR 0U
+#define DSITX__MCTL_DPHY_ERR_CTL2__ERR_CONT_LP1_3_EDGE_WOSET 0U
+#define DSITX__MCTL_DPHY_ERR_CTL2__ERR_CONT_LP1_4_EDGE_MASK 0x00080000U
+#define DSITX__MCTL_DPHY_ERR_CTL2__ERR_CONT_LP1_4_EDGE_SHIFT 19U
+#define DSITX__MCTL_DPHY_ERR_CTL2__ERR_CONT_LP1_4_EDGE_WIDTH 1U
+#define DSITX__MCTL_DPHY_ERR_CTL2__ERR_CONT_LP1_4_EDGE_WOCLR 0U
+#define DSITX__MCTL_DPHY_ERR_CTL2__ERR_CONT_LP1_4_EDGE_WOSET 0U
+#define DSITX__MCTL_DPHY_ERR_CTL2__RSVD_0_MASK 0xFFF00000U
+#define DSITX__MCTL_DPHY_ERR_CTL2__RSVD_0_SHIFT 20U
+#define DSITX__MCTL_DPHY_ERR_CTL2__RSVD_0_WIDTH 12U
+
+#define DSITX__MCTL_MAIN_STS_CLR_READ_MASK 0xFFFFFC00U
+#define DSITX__MCTL_MAIN_STS_CLR_WRITE_MASK 0xFFFFFC00U
+#define DSITX__MCTL_MAIN_STS_CLR__PLL_LOCK_CLR_MASK 0x00000001U
+#define DSITX__MCTL_MAIN_STS_CLR__PLL_LOCK_CLR_SHIFT 0U
+#define DSITX__MCTL_MAIN_STS_CLR__PLL_LOCK_CLR_WIDTH 1U
+#define DSITX__MCTL_MAIN_STS_CLR__PLL_LOCK_CLR_WOCLR 0U
+#define DSITX__MCTL_MAIN_STS_CLR__PLL_LOCK_CLR_WOSET 0U
+#define DSITX__MCTL_MAIN_STS_CLR__CLKLANE_READY_CLR_MASK 0x00000002U
+#define DSITX__MCTL_MAIN_STS_CLR__CLKLANE_READY_CLR_SHIFT 1U
+#define DSITX__MCTL_MAIN_STS_CLR__CLKLANE_READY_CLR_WIDTH 1U
+#define DSITX__MCTL_MAIN_STS_CLR__CLKLANE_READY_CLR_WOCLR 0U
+#define DSITX__MCTL_MAIN_STS_CLR__CLKLANE_READY_CLR_WOSET 0U
+#define DSITX__MCTL_MAIN_STS_CLR__DAT1_READY_CLR_MASK 0x00000004U
+#define DSITX__MCTL_MAIN_STS_CLR__DAT1_READY_CLR_SHIFT 2U
+#define DSITX__MCTL_MAIN_STS_CLR__DAT1_READY_CLR_WIDTH 1U
+#define DSITX__MCTL_MAIN_STS_CLR__DAT1_READY_CLR_WOCLR 0U
+#define DSITX__MCTL_MAIN_STS_CLR__DAT1_READY_CLR_WOSET 0U
+#define DSITX__MCTL_MAIN_STS_CLR__DAT2_READY_CLR_MASK 0x00000008U
+#define DSITX__MCTL_MAIN_STS_CLR__DAT2_READY_CLR_SHIFT 3U
+#define DSITX__MCTL_MAIN_STS_CLR__DAT2_READY_CLR_WIDTH 1U
+#define DSITX__MCTL_MAIN_STS_CLR__DAT2_READY_CLR_WOCLR 0U
+#define DSITX__MCTL_MAIN_STS_CLR__DAT2_READY_CLR_WOSET 0U
+#define DSITX__MCTL_MAIN_STS_CLR__DAT3_READY_CLR_MASK 0x00000010U
+#define DSITX__MCTL_MAIN_STS_CLR__DAT3_READY_CLR_SHIFT 4U
+#define DSITX__MCTL_MAIN_STS_CLR__DAT3_READY_CLR_WIDTH 1U
+#define DSITX__MCTL_MAIN_STS_CLR__DAT3_READY_CLR_WOCLR 0U
+#define DSITX__MCTL_MAIN_STS_CLR__DAT3_READY_CLR_WOSET 0U
+#define DSITX__MCTL_MAIN_STS_CLR__DAT4_READY_CLR_MASK 0x00000020U
+#define DSITX__MCTL_MAIN_STS_CLR__DAT4_READY_CLR_SHIFT 5U
+#define DSITX__MCTL_MAIN_STS_CLR__DAT4_READY_CLR_WIDTH 1U
+#define DSITX__MCTL_MAIN_STS_CLR__DAT4_READY_CLR_WOCLR 0U
+#define DSITX__MCTL_MAIN_STS_CLR__DAT4_READY_CLR_WOSET 0U
+#define DSITX__MCTL_MAIN_STS_CLR__HSTX_TO_ERR_CLR_MASK 0x00000040U
+#define DSITX__MCTL_MAIN_STS_CLR__HSTX_TO_ERR_CLR_SHIFT 6U
+#define DSITX__MCTL_MAIN_STS_CLR__HSTX_TO_ERR_CLR_WIDTH 1U
+#define DSITX__MCTL_MAIN_STS_CLR__HSTX_TO_ERR_CLR_WOCLR 0U
+#define DSITX__MCTL_MAIN_STS_CLR__HSTX_TO_ERR_CLR_WOSET 0U
+#define DSITX__MCTL_MAIN_STS_CLR__LPRX_TO_ERR_CLR_MASK 0x00000080U
+#define DSITX__MCTL_MAIN_STS_CLR__LPRX_TO_ERR_CLR_SHIFT 7U
+#define DSITX__MCTL_MAIN_STS_CLR__LPRX_TO_ERR_CLR_WIDTH 1U
+#define DSITX__MCTL_MAIN_STS_CLR__LPRX_TO_ERR_CLR_WOCLR 0U
+#define DSITX__MCTL_MAIN_STS_CLR__LPRX_TO_ERR_CLR_WOSET 0U
+#define DSITX__MCTL_MAIN_STS_CLR__IF1_UNTERM_PCK_ERR_CLR_MASK 0x00000100U
+#define DSITX__MCTL_MAIN_STS_CLR__IF1_UNTERM_PCK_ERR_CLR_SHIFT 8U
+#define DSITX__MCTL_MAIN_STS_CLR__IF1_UNTERM_PCK_ERR_CLR_WIDTH 1U
+#define DSITX__MCTL_MAIN_STS_CLR__IF1_UNTERM_PCK_ERR_CLR_WOCLR 0U
+#define DSITX__MCTL_MAIN_STS_CLR__IF1_UNTERM_PCK_ERR_CLR_WOSET 0U
+#define DSITX__MCTL_MAIN_STS_CLR__IF3_UNTERM_PCK_ERR_CLR_MASK 0x00000200U
+#define DSITX__MCTL_MAIN_STS_CLR__IF3_UNTERM_PCK_ERR_CLR_SHIFT 9U
+#define DSITX__MCTL_MAIN_STS_CLR__IF3_UNTERM_PCK_ERR_CLR_WIDTH 1U
+#define DSITX__MCTL_MAIN_STS_CLR__IF3_UNTERM_PCK_ERR_CLR_WOCLR 0U
+#define DSITX__MCTL_MAIN_STS_CLR__IF3_UNTERM_PCK_ERR_CLR_WOSET 0U
+#define DSITX__MCTL_MAIN_STS_CLR__RSVD_0_MASK 0xFFFFFC00U
+#define DSITX__MCTL_MAIN_STS_CLR__RSVD_0_SHIFT 10U
+#define DSITX__MCTL_MAIN_STS_CLR__RSVD_0_WIDTH 22U
+
+#define DSITX__CMD_MODE_STS_CLR_READ_MASK 0xFFFFFFE0U
+#define DSITX__CMD_MODE_STS_CLR_WRITE_MASK 0xFFFFFFE0U
+#define DSITX__CMD_MODE_STS_CLR__CSM_RUNNING_CLR_MASK 0x00000001U
+#define DSITX__CMD_MODE_STS_CLR__CSM_RUNNING_CLR_SHIFT 0U
+#define DSITX__CMD_MODE_STS_CLR__CSM_RUNNING_CLR_WIDTH 1U
+#define DSITX__CMD_MODE_STS_CLR__CSM_RUNNING_CLR_WOCLR 0U
+#define DSITX__CMD_MODE_STS_CLR__CSM_RUNNING_CLR_WOSET 0U
+#define DSITX__CMD_MODE_STS_CLR__ERR_NO_TE_CLR_MASK 0x00000002U
+#define DSITX__CMD_MODE_STS_CLR__ERR_NO_TE_CLR_SHIFT 1U
+#define DSITX__CMD_MODE_STS_CLR__ERR_NO_TE_CLR_WIDTH 1U
+#define DSITX__CMD_MODE_STS_CLR__ERR_NO_TE_CLR_WOCLR 0U
+#define DSITX__CMD_MODE_STS_CLR__ERR_NO_TE_CLR_WOSET 0U
+#define DSITX__CMD_MODE_STS_CLR__ERR_TE_MISS_CLR_MASK 0x00000004U
+#define DSITX__CMD_MODE_STS_CLR__ERR_TE_MISS_CLR_SHIFT 2U
+#define DSITX__CMD_MODE_STS_CLR__ERR_TE_MISS_CLR_WIDTH 1U
+#define DSITX__CMD_MODE_STS_CLR__ERR_TE_MISS_CLR_WOCLR 0U
+#define DSITX__CMD_MODE_STS_CLR__ERR_TE_MISS_CLR_WOSET 0U
+#define DSITX__CMD_MODE_STS_CLR__ERR_UNWANTED_RD_CLR_MASK 0x00000008U
+#define DSITX__CMD_MODE_STS_CLR__ERR_UNWANTED_RD_CLR_SHIFT 3U
+#define DSITX__CMD_MODE_STS_CLR__ERR_UNWANTED_RD_CLR_WIDTH 1U
+#define DSITX__CMD_MODE_STS_CLR__ERR_UNWANTED_RD_CLR_WOCLR 0U
+#define DSITX__CMD_MODE_STS_CLR__ERR_UNWANTED_RD_CLR_WOSET 0U
+#define DSITX__CMD_MODE_STS_CLR__ERR_IF1_UNDERRUN_CLR_MASK 0x00000010U
+#define DSITX__CMD_MODE_STS_CLR__ERR_IF1_UNDERRUN_CLR_SHIFT 4U
+#define DSITX__CMD_MODE_STS_CLR__ERR_IF1_UNDERRUN_CLR_WIDTH 1U
+#define DSITX__CMD_MODE_STS_CLR__ERR_IF1_UNDERRUN_CLR_WOCLR 0U
+#define DSITX__CMD_MODE_STS_CLR__ERR_IF1_UNDERRUN_CLR_WOSET 0U
+#define DSITX__CMD_MODE_STS_CLR__ERR_IF3_UNDERRUN_CLR_MASK 0x00000020U
+#define DSITX__CMD_MODE_STS_CLR__ERR_IF3_UNDERRUN_CLR_SHIFT 5U
+#define DSITX__CMD_MODE_STS_CLR__ERR_IF3_UNDERRUN_CLR_WIDTH 1U
+#define DSITX__CMD_MODE_STS_CLR__ERR_IF3_UNDERRUN_CLR_WOCLR 0U
+#define DSITX__CMD_MODE_STS_CLR__ERR_IF3_UNDERRUN_CLR_WOSET 0U
+#define DSITX__CMD_MODE_STS_CLR__RSVD_0_MASK 0xFFFFFFC0U
+#define DSITX__CMD_MODE_STS_CLR__RSVD_0_SHIFT 6U
+#define DSITX__CMD_MODE_STS_CLR__RSVD_0_WIDTH 26U
+
+#define DSITX__DIRECT_CMD_STS_CLR_READ_MASK 0xFFFFF800U
+#define DSITX__DIRECT_CMD_STS_CLR_WRITE_MASK 0xFFFFF800U
+#define DSITX__DIRECT_CMD_STS_CLR__CMD_TRANSMISSION_CLR_MASK 0x00000001U
+#define DSITX__DIRECT_CMD_STS_CLR__CMD_TRANSMISSION_CLR_SHIFT 0U
+#define DSITX__DIRECT_CMD_STS_CLR__CMD_TRANSMISSION_CLR_WIDTH 1U
+#define DSITX__DIRECT_CMD_STS_CLR__CMD_TRANSMISSION_CLR_WOCLR 0U
+#define DSITX__DIRECT_CMD_STS_CLR__CMD_TRANSMISSION_CLR_WOSET 0U
+#define DSITX__DIRECT_CMD_STS_CLR__WRITE_COMPLETED_CLR_MASK 0x00000002U
+#define DSITX__DIRECT_CMD_STS_CLR__WRITE_COMPLETED_CLR_SHIFT 1U
+#define DSITX__DIRECT_CMD_STS_CLR__WRITE_COMPLETED_CLR_WIDTH 1U
+#define DSITX__DIRECT_CMD_STS_CLR__WRITE_COMPLETED_CLR_WOCLR 0U
+#define DSITX__DIRECT_CMD_STS_CLR__WRITE_COMPLETED_CLR_WOSET 0U
+#define DSITX__DIRECT_CMD_STS_CLR__TRIGGER_COMPLETED_CLR_MASK 0x00000004U
+#define DSITX__DIRECT_CMD_STS_CLR__TRIGGER_COMPLETED_CLR_SHIFT 2U
+#define DSITX__DIRECT_CMD_STS_CLR__TRIGGER_COMPLETED_CLR_WIDTH 1U
+#define DSITX__DIRECT_CMD_STS_CLR__TRIGGER_COMPLETED_CLR_WOCLR 0U
+#define DSITX__DIRECT_CMD_STS_CLR__TRIGGER_COMPLETED_CLR_WOSET 0U
+#define DSITX__DIRECT_CMD_STS_CLR__READ_COMPLETED_CLR_MASK 0x00000008U
+#define DSITX__DIRECT_CMD_STS_CLR__READ_COMPLETED_CLR_SHIFT 3U
+#define DSITX__DIRECT_CMD_STS_CLR__READ_COMPLETED_CLR_WIDTH 1U
+#define DSITX__DIRECT_CMD_STS_CLR__READ_COMPLETED_CLR_WOCLR 0U
+#define DSITX__DIRECT_CMD_STS_CLR__READ_COMPLETED_CLR_WOSET 0U
+#define DSITX__DIRECT_CMD_STS_CLR__ACK_RECEIVED_CLR_MASK 0x00000010U
+#define DSITX__DIRECT_CMD_STS_CLR__ACK_RECEIVED_CLR_SHIFT 4U
+#define DSITX__DIRECT_CMD_STS_CLR__ACK_RECEIVED_CLR_WIDTH 1U
+#define DSITX__DIRECT_CMD_STS_CLR__ACK_RECEIVED_CLR_WOCLR 0U
+#define DSITX__DIRECT_CMD_STS_CLR__ACK_RECEIVED_CLR_WOSET 0U
+#define DSITX__DIRECT_CMD_STS_CLR__ACK_WITH_ERR_CLR_MASK 0x00000020U
+#define DSITX__DIRECT_CMD_STS_CLR__ACK_WITH_ERR_CLR_SHIFT 5U
+#define DSITX__DIRECT_CMD_STS_CLR__ACK_WITH_ERR_CLR_WIDTH 1U
+#define DSITX__DIRECT_CMD_STS_CLR__ACK_WITH_ERR_CLR_WOCLR 0U
+#define DSITX__DIRECT_CMD_STS_CLR__ACK_WITH_ERR_CLR_WOSET 0U
+#define DSITX__DIRECT_CMD_STS_CLR__TRIGGER_RECEIVED_CLR_MASK 0x00000040U
+#define DSITX__DIRECT_CMD_STS_CLR__TRIGGER_RECEIVED_CLR_SHIFT 6U
+#define DSITX__DIRECT_CMD_STS_CLR__TRIGGER_RECEIVED_CLR_WIDTH 1U
+#define DSITX__DIRECT_CMD_STS_CLR__TRIGGER_RECEIVED_CLR_WOCLR 0U
+#define DSITX__DIRECT_CMD_STS_CLR__TRIGGER_RECEIVED_CLR_WOSET 0U
+#define DSITX__DIRECT_CMD_STS_CLR__TE_RECEIVED_CLR_MASK 0x00000080U
+#define DSITX__DIRECT_CMD_STS_CLR__TE_RECEIVED_CLR_SHIFT 7U
+#define DSITX__DIRECT_CMD_STS_CLR__TE_RECEIVED_CLR_WIDTH 1U
+#define DSITX__DIRECT_CMD_STS_CLR__TE_RECEIVED_CLR_WOCLR 0U
+#define DSITX__DIRECT_CMD_STS_CLR__TE_RECEIVED_CLR_WOSET 0U
+#define DSITX__DIRECT_CMD_STS_CLR__BTA_COMPLETED_CLR_MASK 0x00000100U
+#define DSITX__DIRECT_CMD_STS_CLR__BTA_COMPLETED_CLR_SHIFT 8U
+#define DSITX__DIRECT_CMD_STS_CLR__BTA_COMPLETED_CLR_WIDTH 1U
+#define DSITX__DIRECT_CMD_STS_CLR__BTA_COMPLETED_CLR_WOCLR 0U
+#define DSITX__DIRECT_CMD_STS_CLR__BTA_COMPLETED_CLR_WOSET 0U
+#define DSITX__DIRECT_CMD_STS_CLR__BTA_FINISHED_CLR_MASK 0x00000200U
+#define DSITX__DIRECT_CMD_STS_CLR__BTA_FINISHED_CLR_SHIFT 9U
+#define DSITX__DIRECT_CMD_STS_CLR__BTA_FINISHED_CLR_WIDTH 1U
+#define DSITX__DIRECT_CMD_STS_CLR__BTA_FINISHED_CLR_WOCLR 0U
+#define DSITX__DIRECT_CMD_STS_CLR__BTA_FINISHED_CLR_WOSET 0U
+#define DSITX__DIRECT_CMD_STS_CLR__READ_COMPLETED_WITH_ERR_CLR_MASK 0x00000400U
+#define DSITX__DIRECT_CMD_STS_CLR__READ_COMPLETED_WITH_ERR_CLR_SHIFT 10U
+#define DSITX__DIRECT_CMD_STS_CLR__READ_COMPLETED_WITH_ERR_CLR_WIDTH 1U
+#define DSITX__DIRECT_CMD_STS_CLR__READ_COMPLETED_WITH_ERR_CLR_WOCLR 0U
+#define DSITX__DIRECT_CMD_STS_CLR__READ_COMPLETED_WITH_ERR_CLR_WOSET 0U
+#define DSITX__DIRECT_CMD_STS_CLR__RSVD_0_MASK 0xFFFFF800U
+#define DSITX__DIRECT_CMD_STS_CLR__RSVD_0_SHIFT 11U
+#define DSITX__DIRECT_CMD_STS_CLR__RSVD_0_WIDTH 21U
+
+#define DSITX__DIRECT_CMD_RD_STS_CLR_READ_MASK 0xFFFFFE00U
+#define DSITX__DIRECT_CMD_RD_STS_CLR_WRITE_MASK 0xFFFFFE00U
+#define DSITX__DIRECT_CMD_RD_STS_CLR__ERR_FIXED_CLR_MASK 0x00000001U
+#define DSITX__DIRECT_CMD_RD_STS_CLR__ERR_FIXED_CLR_SHIFT 0U
+#define DSITX__DIRECT_CMD_RD_STS_CLR__ERR_FIXED_CLR_WIDTH 1U
+#define DSITX__DIRECT_CMD_RD_STS_CLR__ERR_FIXED_CLR_WOCLR 0U
+#define DSITX__DIRECT_CMD_RD_STS_CLR__ERR_FIXED_CLR_WOSET 0U
+#define DSITX__DIRECT_CMD_RD_STS_CLR__ERR_UNCORRECTABLE_CLR_MASK 0x00000002U
+#define DSITX__DIRECT_CMD_RD_STS_CLR__ERR_UNCORRECTABLE_CLR_SHIFT 1U
+#define DSITX__DIRECT_CMD_RD_STS_CLR__ERR_UNCORRECTABLE_CLR_WIDTH 1U
+#define DSITX__DIRECT_CMD_RD_STS_CLR__ERR_UNCORRECTABLE_CLR_WOCLR 0U
+#define DSITX__DIRECT_CMD_RD_STS_CLR__ERR_UNCORRECTABLE_CLR_WOSET 0U
+#define DSITX__DIRECT_CMD_RD_STS_CLR__ERR_CHECKSUM_CLR_MASK 0x00000004U
+#define DSITX__DIRECT_CMD_RD_STS_CLR__ERR_CHECKSUM_CLR_SHIFT 2U
+#define DSITX__DIRECT_CMD_RD_STS_CLR__ERR_CHECKSUM_CLR_WIDTH 1U
+#define DSITX__DIRECT_CMD_RD_STS_CLR__ERR_CHECKSUM_CLR_WOCLR 0U
+#define DSITX__DIRECT_CMD_RD_STS_CLR__ERR_CHECKSUM_CLR_WOSET 0U
+#define DSITX__DIRECT_CMD_RD_STS_CLR__ERR_UNDECODABLE_CLR_MASK 0x00000008U
+#define DSITX__DIRECT_CMD_RD_STS_CLR__ERR_UNDECODABLE_CLR_SHIFT 3U
+#define DSITX__DIRECT_CMD_RD_STS_CLR__ERR_UNDECODABLE_CLR_WIDTH 1U
+#define DSITX__DIRECT_CMD_RD_STS_CLR__ERR_UNDECODABLE_CLR_WOCLR 0U
+#define DSITX__DIRECT_CMD_RD_STS_CLR__ERR_UNDECODABLE_CLR_WOSET 0U
+#define DSITX__DIRECT_CMD_RD_STS_CLR__ERR_RECEIVE_CLR_MASK 0x00000010U
+#define DSITX__DIRECT_CMD_RD_STS_CLR__ERR_RECEIVE_CLR_SHIFT 4U
+#define DSITX__DIRECT_CMD_RD_STS_CLR__ERR_RECEIVE_CLR_WIDTH 1U
+#define DSITX__DIRECT_CMD_RD_STS_CLR__ERR_RECEIVE_CLR_WOCLR 0U
+#define DSITX__DIRECT_CMD_RD_STS_CLR__ERR_RECEIVE_CLR_WOSET 0U
+#define DSITX__DIRECT_CMD_RD_STS_CLR__ERR_OVERSIZE_CLR_MASK 0x00000020U
+#define DSITX__DIRECT_CMD_RD_STS_CLR__ERR_OVERSIZE_CLR_SHIFT 5U
+#define DSITX__DIRECT_CMD_RD_STS_CLR__ERR_OVERSIZE_CLR_WIDTH 1U
+#define DSITX__DIRECT_CMD_RD_STS_CLR__ERR_OVERSIZE_CLR_WOCLR 0U
+#define DSITX__DIRECT_CMD_RD_STS_CLR__ERR_OVERSIZE_CLR_WOSET 0U
+#define DSITX__DIRECT_CMD_RD_STS_CLR__ERR_WRONG_LENGTH_CLR_MASK 0x00000040U
+#define DSITX__DIRECT_CMD_RD_STS_CLR__ERR_WRONG_LENGTH_CLR_SHIFT 6U
+#define DSITX__DIRECT_CMD_RD_STS_CLR__ERR_WRONG_LENGTH_CLR_WIDTH 1U
+#define DSITX__DIRECT_CMD_RD_STS_CLR__ERR_WRONG_LENGTH_CLR_WOCLR 0U
+#define DSITX__DIRECT_CMD_RD_STS_CLR__ERR_WRONG_LENGTH_CLR_WOSET 0U
+#define DSITX__DIRECT_CMD_RD_STS_CLR__ERR_MISSING_EOT_CLR_MASK 0x00000080U
+#define DSITX__DIRECT_CMD_RD_STS_CLR__ERR_MISSING_EOT_CLR_SHIFT 7U
+#define DSITX__DIRECT_CMD_RD_STS_CLR__ERR_MISSING_EOT_CLR_WIDTH 1U
+#define DSITX__DIRECT_CMD_RD_STS_CLR__ERR_MISSING_EOT_CLR_WOCLR 0U
+#define DSITX__DIRECT_CMD_RD_STS_CLR__ERR_MISSING_EOT_CLR_WOSET 0U
+#define DSITX__DIRECT_CMD_RD_STS_CLR__ERR_EOT_WITH_ERR_CLR_MASK 0x00000100U
+#define DSITX__DIRECT_CMD_RD_STS_CLR__ERR_EOT_WITH_ERR_CLR_SHIFT 8U
+#define DSITX__DIRECT_CMD_RD_STS_CLR__ERR_EOT_WITH_ERR_CLR_WIDTH 1U
+#define DSITX__DIRECT_CMD_RD_STS_CLR__ERR_EOT_WITH_ERR_CLR_WOCLR 0U
+#define DSITX__DIRECT_CMD_RD_STS_CLR__ERR_EOT_WITH_ERR_CLR_WOSET 0U
+#define DSITX__DIRECT_CMD_RD_STS_CLR__RSVD_0_MASK 0xFFFFFE00U
+#define DSITX__DIRECT_CMD_RD_STS_CLR__RSVD_0_SHIFT 9U
+#define DSITX__DIRECT_CMD_RD_STS_CLR__RSVD_0_WIDTH 23U
+
+#define DSITX__VID_MODE_STS_CLR_READ_MASK 0xFFFFF800U
+#define DSITX__VID_MODE_STS_CLR_WRITE_MASK 0xFFFFF800U
+#define DSITX__VID_MODE_STS_CLR__VSG_STS_CLR_MASK 0x00000001U
+#define DSITX__VID_MODE_STS_CLR__VSG_STS_CLR_SHIFT 0U
+#define DSITX__VID_MODE_STS_CLR__VSG_STS_CLR_WIDTH 1U
+#define DSITX__VID_MODE_STS_CLR__VSG_STS_CLR_WOCLR 0U
+#define DSITX__VID_MODE_STS_CLR__VSG_STS_CLR_WOSET 0U
+#define DSITX__VID_MODE_STS_CLR__ERR_MISSING_DATA_CLR_MASK 0x00000002U
+#define DSITX__VID_MODE_STS_CLR__ERR_MISSING_DATA_CLR_SHIFT 1U
+#define DSITX__VID_MODE_STS_CLR__ERR_MISSING_DATA_CLR_WIDTH 1U
+#define DSITX__VID_MODE_STS_CLR__ERR_MISSING_DATA_CLR_WOCLR 0U
+#define DSITX__VID_MODE_STS_CLR__ERR_MISSING_DATA_CLR_WOSET 0U
+#define DSITX__VID_MODE_STS_CLR__ERR_MISSING_HSYNC_CLR_MASK 0x00000004U
+#define DSITX__VID_MODE_STS_CLR__ERR_MISSING_HSYNC_CLR_SHIFT 2U
+#define DSITX__VID_MODE_STS_CLR__ERR_MISSING_HSYNC_CLR_WIDTH 1U
+#define DSITX__VID_MODE_STS_CLR__ERR_MISSING_HSYNC_CLR_WOCLR 0U
+#define DSITX__VID_MODE_STS_CLR__ERR_MISSING_HSYNC_CLR_WOSET 0U
+#define DSITX__VID_MODE_STS_CLR__ERR_MISSING_VSYNC_CLR_MASK 0x00000008U
+#define DSITX__VID_MODE_STS_CLR__ERR_MISSING_VSYNC_CLR_SHIFT 3U
+#define DSITX__VID_MODE_STS_CLR__ERR_MISSING_VSYNC_CLR_WIDTH 1U
+#define DSITX__VID_MODE_STS_CLR__ERR_MISSING_VSYNC_CLR_WOCLR 0U
+#define DSITX__VID_MODE_STS_CLR__ERR_MISSING_VSYNC_CLR_WOSET 0U
+#define DSITX__VID_MODE_STS_CLR__ERR_SMALL_LENGTH_CLR_MASK 0x00000010U
+#define DSITX__VID_MODE_STS_CLR__ERR_SMALL_LENGTH_CLR_SHIFT 4U
+#define DSITX__VID_MODE_STS_CLR__ERR_SMALL_LENGTH_CLR_WIDTH 1U
+#define DSITX__VID_MODE_STS_CLR__ERR_SMALL_LENGTH_CLR_WOCLR 0U
+#define DSITX__VID_MODE_STS_CLR__ERR_SMALL_LENGTH_CLR_WOSET 0U
+#define DSITX__VID_MODE_STS_CLR__ERR_SMALL_HEIGHT_CLR_MASK 0x00000020U
+#define DSITX__VID_MODE_STS_CLR__ERR_SMALL_HEIGHT_CLR_SHIFT 5U
+#define DSITX__VID_MODE_STS_CLR__ERR_SMALL_HEIGHT_CLR_WIDTH 1U
+#define DSITX__VID_MODE_STS_CLR__ERR_SMALL_HEIGHT_CLR_WOCLR 0U
+#define DSITX__VID_MODE_STS_CLR__ERR_SMALL_HEIGHT_CLR_WOSET 0U
+#define DSITX__VID_MODE_STS_CLR__ERR_BURSTWRITE_CLR_MASK 0x00000040U
+#define DSITX__VID_MODE_STS_CLR__ERR_BURSTWRITE_CLR_SHIFT 6U
+#define DSITX__VID_MODE_STS_CLR__ERR_BURSTWRITE_CLR_WIDTH 1U
+#define DSITX__VID_MODE_STS_CLR__ERR_BURSTWRITE_CLR_WOCLR 0U
+#define DSITX__VID_MODE_STS_CLR__ERR_BURSTWRITE_CLR_WOSET 0U
+#define DSITX__VID_MODE_STS_CLR__ERR_LINEWRITE_CLR_MASK 0x00000080U
+#define DSITX__VID_MODE_STS_CLR__ERR_LINEWRITE_CLR_SHIFT 7U
+#define DSITX__VID_MODE_STS_CLR__ERR_LINEWRITE_CLR_WIDTH 1U
+#define DSITX__VID_MODE_STS_CLR__ERR_LINEWRITE_CLR_WOCLR 0U
+#define DSITX__VID_MODE_STS_CLR__ERR_LINEWRITE_CLR_WOSET 0U
+#define DSITX__VID_MODE_STS_CLR__ERR_LONGREAD_CLR_MASK 0x00000100U
+#define DSITX__VID_MODE_STS_CLR__ERR_LONGREAD_CLR_SHIFT 8U
+#define DSITX__VID_MODE_STS_CLR__ERR_LONGREAD_CLR_WIDTH 1U
+#define DSITX__VID_MODE_STS_CLR__ERR_LONGREAD_CLR_WOCLR 0U
+#define DSITX__VID_MODE_STS_CLR__ERR_LONGREAD_CLR_WOSET 0U
+#define DSITX__VID_MODE_STS_CLR__ERR_VRS_WRONG_LENGTH_CLR_MASK 0x00000200U
+#define DSITX__VID_MODE_STS_CLR__ERR_VRS_WRONG_LENGTH_CLR_SHIFT 9U
+#define DSITX__VID_MODE_STS_CLR__ERR_VRS_WRONG_LENGTH_CLR_WIDTH 1U
+#define DSITX__VID_MODE_STS_CLR__ERR_VRS_WRONG_LENGTH_CLR_WOCLR 0U
+#define DSITX__VID_MODE_STS_CLR__ERR_VRS_WRONG_LENGTH_CLR_WOSET 0U
+#define DSITX__VID_MODE_STS_CLR__VSG_RECOVERY_CLR_MASK 0x00000400U
+#define DSITX__VID_MODE_STS_CLR__VSG_RECOVERY_CLR_SHIFT 10U
+#define DSITX__VID_MODE_STS_CLR__VSG_RECOVERY_CLR_WIDTH 1U
+#define DSITX__VID_MODE_STS_CLR__VSG_RECOVERY_CLR_WOCLR 0U
+#define DSITX__VID_MODE_STS_CLR__VSG_RECOVERY_CLR_WOSET 0U
+#define DSITX__VID_MODE_STS_CLR__RSVD_0_MASK 0xFFFFF800U
+#define DSITX__VID_MODE_STS_CLR__RSVD_0_SHIFT 11U
+#define DSITX__VID_MODE_STS_CLR__RSVD_0_WIDTH 21U
+
+#define DSITX__TG_STS_CLR_READ_MASK 0xFFFFFFFEU
+#define DSITX__TG_STS_CLR_WRITE_MASK 0xFFFFFFFEU
+#define DSITX__TG_STS_CLR__TVG_STS_CLR_MASK 0x00000001U
+#define DSITX__TG_STS_CLR__TVG_STS_CLR_SHIFT 0U
+#define DSITX__TG_STS_CLR__TVG_STS_CLR_WIDTH 1U
+#define DSITX__TG_STS_CLR__TVG_STS_CLR_WOCLR 0U
+#define DSITX__TG_STS_CLR__TVG_STS_CLR_WOSET 0U
+#define DSITX__TG_STS_CLR__RSVD_0_MASK 0xFFFFFFFEU
+#define DSITX__TG_STS_CLR__RSVD_0_SHIFT 1U
+#define DSITX__TG_STS_CLR__RSVD_0_WIDTH 31U
+
+#define DSITX__MCTL_DPHY_ERR_CLR_READ_MASK 0xFC00003FU
+#define DSITX__MCTL_DPHY_ERR_CLR_WRITE_MASK 0xFC00003FU
+#define DSITX__MCTL_DPHY_ERR_CLR__RSVD_0_MASK 0x0000003FU
+#define DSITX__MCTL_DPHY_ERR_CLR__RSVD_0_SHIFT 0U
+#define DSITX__MCTL_DPHY_ERR_CLR__RSVD_0_WIDTH 6U
+#define DSITX__MCTL_DPHY_ERR_CLR__ERR_ESC_1_CLR_MASK 0x00000040U
+#define DSITX__MCTL_DPHY_ERR_CLR__ERR_ESC_1_CLR_SHIFT 6U
+#define DSITX__MCTL_DPHY_ERR_CLR__ERR_ESC_1_CLR_WIDTH 1U
+#define DSITX__MCTL_DPHY_ERR_CLR__ERR_ESC_1_CLR_WOCLR 0U
+#define DSITX__MCTL_DPHY_ERR_CLR__ERR_ESC_1_CLR_WOSET 0U
+#define DSITX__MCTL_DPHY_ERR_CLR__ERR_ESC_2_CLR_MASK 0x00000080U
+#define DSITX__MCTL_DPHY_ERR_CLR__ERR_ESC_2_CLR_SHIFT 7U
+#define DSITX__MCTL_DPHY_ERR_CLR__ERR_ESC_2_CLR_WIDTH 1U
+#define DSITX__MCTL_DPHY_ERR_CLR__ERR_ESC_2_CLR_WOCLR 0U
+#define DSITX__MCTL_DPHY_ERR_CLR__ERR_ESC_2_CLR_WOSET 0U
+#define DSITX__MCTL_DPHY_ERR_CLR__ERR_ESC_3_CLR_MASK 0x00000100U
+#define DSITX__MCTL_DPHY_ERR_CLR__ERR_ESC_3_CLR_SHIFT 8U
+#define DSITX__MCTL_DPHY_ERR_CLR__ERR_ESC_3_CLR_WIDTH 1U
+#define DSITX__MCTL_DPHY_ERR_CLR__ERR_ESC_3_CLR_WOCLR 0U
+#define DSITX__MCTL_DPHY_ERR_CLR__ERR_ESC_3_CLR_WOSET 0U
+#define DSITX__MCTL_DPHY_ERR_CLR__ERR_ESC_4_CLR_MASK 0x00000200U
+#define DSITX__MCTL_DPHY_ERR_CLR__ERR_ESC_4_CLR_SHIFT 9U
+#define DSITX__MCTL_DPHY_ERR_CLR__ERR_ESC_4_CLR_WIDTH 1U
+#define DSITX__MCTL_DPHY_ERR_CLR__ERR_ESC_4_CLR_WOCLR 0U
+#define DSITX__MCTL_DPHY_ERR_CLR__ERR_ESC_4_CLR_WOSET 0U
+#define DSITX__MCTL_DPHY_ERR_CLR__ERR_SYNCESC_1_CLR_MASK 0x00000400U
+#define DSITX__MCTL_DPHY_ERR_CLR__ERR_SYNCESC_1_CLR_SHIFT 10U
+#define DSITX__MCTL_DPHY_ERR_CLR__ERR_SYNCESC_1_CLR_WIDTH 1U
+#define DSITX__MCTL_DPHY_ERR_CLR__ERR_SYNCESC_1_CLR_WOCLR 0U
+#define DSITX__MCTL_DPHY_ERR_CLR__ERR_SYNCESC_1_CLR_WOSET 0U
+#define DSITX__MCTL_DPHY_ERR_CLR__ERR_SYNCESC_2_CLR_MASK 0x00000800U
+#define DSITX__MCTL_DPHY_ERR_CLR__ERR_SYNCESC_2_CLR_SHIFT 11U
+#define DSITX__MCTL_DPHY_ERR_CLR__ERR_SYNCESC_2_CLR_WIDTH 1U
+#define DSITX__MCTL_DPHY_ERR_CLR__ERR_SYNCESC_2_CLR_WOCLR 0U
+#define DSITX__MCTL_DPHY_ERR_CLR__ERR_SYNCESC_2_CLR_WOSET 0U
+#define DSITX__MCTL_DPHY_ERR_CLR__ERR_SYNCESC_3_CLR_MASK 0x00001000U
+#define DSITX__MCTL_DPHY_ERR_CLR__ERR_SYNCESC_3_CLR_SHIFT 12U
+#define DSITX__MCTL_DPHY_ERR_CLR__ERR_SYNCESC_3_CLR_WIDTH 1U
+#define DSITX__MCTL_DPHY_ERR_CLR__ERR_SYNCESC_3_CLR_WOCLR 0U
+#define DSITX__MCTL_DPHY_ERR_CLR__ERR_SYNCESC_3_CLR_WOSET 0U
+#define DSITX__MCTL_DPHY_ERR_CLR__ERR_SYNCESC_4_CLR_MASK 0x00002000U
+#define DSITX__MCTL_DPHY_ERR_CLR__ERR_SYNCESC_4_CLR_SHIFT 13U
+#define DSITX__MCTL_DPHY_ERR_CLR__ERR_SYNCESC_4_CLR_WIDTH 1U
+#define DSITX__MCTL_DPHY_ERR_CLR__ERR_SYNCESC_4_CLR_WOCLR 0U
+#define DSITX__MCTL_DPHY_ERR_CLR__ERR_SYNCESC_4_CLR_WOSET 0U
+#define DSITX__MCTL_DPHY_ERR_CLR__ERR_CONTROL_1_CLR_MASK 0x00004000U
+#define DSITX__MCTL_DPHY_ERR_CLR__ERR_CONTROL_1_CLR_SHIFT 14U
+#define DSITX__MCTL_DPHY_ERR_CLR__ERR_CONTROL_1_CLR_WIDTH 1U
+#define DSITX__MCTL_DPHY_ERR_CLR__ERR_CONTROL_1_CLR_WOCLR 0U
+#define DSITX__MCTL_DPHY_ERR_CLR__ERR_CONTROL_1_CLR_WOSET 0U
+#define DSITX__MCTL_DPHY_ERR_CLR__ERR_CONTROL_2_CLR_MASK 0x00008000U
+#define DSITX__MCTL_DPHY_ERR_CLR__ERR_CONTROL_2_CLR_SHIFT 15U
+#define DSITX__MCTL_DPHY_ERR_CLR__ERR_CONTROL_2_CLR_WIDTH 1U
+#define DSITX__MCTL_DPHY_ERR_CLR__ERR_CONTROL_2_CLR_WOCLR 0U
+#define DSITX__MCTL_DPHY_ERR_CLR__ERR_CONTROL_2_CLR_WOSET 0U
+#define DSITX__MCTL_DPHY_ERR_CLR__ERR_CONTROL_3_CLR_MASK 0x00010000U
+#define DSITX__MCTL_DPHY_ERR_CLR__ERR_CONTROL_3_CLR_SHIFT 16U
+#define DSITX__MCTL_DPHY_ERR_CLR__ERR_CONTROL_3_CLR_WIDTH 1U
+#define DSITX__MCTL_DPHY_ERR_CLR__ERR_CONTROL_3_CLR_WOCLR 0U
+#define DSITX__MCTL_DPHY_ERR_CLR__ERR_CONTROL_3_CLR_WOSET 0U
+#define DSITX__MCTL_DPHY_ERR_CLR__ERR_CONTROL_4_CLR_MASK 0x00020000U
+#define DSITX__MCTL_DPHY_ERR_CLR__ERR_CONTROL_4_CLR_SHIFT 17U
+#define DSITX__MCTL_DPHY_ERR_CLR__ERR_CONTROL_4_CLR_WIDTH 1U
+#define DSITX__MCTL_DPHY_ERR_CLR__ERR_CONTROL_4_CLR_WOCLR 0U
+#define DSITX__MCTL_DPHY_ERR_CLR__ERR_CONTROL_4_CLR_WOSET 0U
+#define DSITX__MCTL_DPHY_ERR_CLR__ERR_CONT_LP0_1_CLR_MASK 0x00040000U
+#define DSITX__MCTL_DPHY_ERR_CLR__ERR_CONT_LP0_1_CLR_SHIFT 18U
+#define DSITX__MCTL_DPHY_ERR_CLR__ERR_CONT_LP0_1_CLR_WIDTH 1U
+#define DSITX__MCTL_DPHY_ERR_CLR__ERR_CONT_LP0_1_CLR_WOCLR 0U
+#define DSITX__MCTL_DPHY_ERR_CLR__ERR_CONT_LP0_1_CLR_WOSET 0U
+#define DSITX__MCTL_DPHY_ERR_CLR__ERR_CONT_LP0_2_CLR_MASK 0x00080000U
+#define DSITX__MCTL_DPHY_ERR_CLR__ERR_CONT_LP0_2_CLR_SHIFT 19U
+#define DSITX__MCTL_DPHY_ERR_CLR__ERR_CONT_LP0_2_CLR_WIDTH 1U
+#define DSITX__MCTL_DPHY_ERR_CLR__ERR_CONT_LP0_2_CLR_WOCLR 0U
+#define DSITX__MCTL_DPHY_ERR_CLR__ERR_CONT_LP0_2_CLR_WOSET 0U
+#define DSITX__MCTL_DPHY_ERR_CLR__ERR_CONT_LP0_3_CLR_MASK 0x00100000U
+#define DSITX__MCTL_DPHY_ERR_CLR__ERR_CONT_LP0_3_CLR_SHIFT 20U
+#define DSITX__MCTL_DPHY_ERR_CLR__ERR_CONT_LP0_3_CLR_WIDTH 1U
+#define DSITX__MCTL_DPHY_ERR_CLR__ERR_CONT_LP0_3_CLR_WOCLR 0U
+#define DSITX__MCTL_DPHY_ERR_CLR__ERR_CONT_LP0_3_CLR_WOSET 0U
+#define DSITX__MCTL_DPHY_ERR_CLR__ERR_CONT_LP0_4_CLR_MASK 0x00200000U
+#define DSITX__MCTL_DPHY_ERR_CLR__ERR_CONT_LP0_4_CLR_SHIFT 21U
+#define DSITX__MCTL_DPHY_ERR_CLR__ERR_CONT_LP0_4_CLR_WIDTH 1U
+#define DSITX__MCTL_DPHY_ERR_CLR__ERR_CONT_LP0_4_CLR_WOCLR 0U
+#define DSITX__MCTL_DPHY_ERR_CLR__ERR_CONT_LP0_4_CLR_WOSET 0U
+#define DSITX__MCTL_DPHY_ERR_CLR__ERR_CONT_LP1_1_CLR_MASK 0x00400000U
+#define DSITX__MCTL_DPHY_ERR_CLR__ERR_CONT_LP1_1_CLR_SHIFT 22U
+#define DSITX__MCTL_DPHY_ERR_CLR__ERR_CONT_LP1_1_CLR_WIDTH 1U
+#define DSITX__MCTL_DPHY_ERR_CLR__ERR_CONT_LP1_1_CLR_WOCLR 0U
+#define DSITX__MCTL_DPHY_ERR_CLR__ERR_CONT_LP1_1_CLR_WOSET 0U
+#define DSITX__MCTL_DPHY_ERR_CLR__ERR_CONT_LP1_2_CLR_MASK 0x00800000U
+#define DSITX__MCTL_DPHY_ERR_CLR__ERR_CONT_LP1_2_CLR_SHIFT 23U
+#define DSITX__MCTL_DPHY_ERR_CLR__ERR_CONT_LP1_2_CLR_WIDTH 1U
+#define DSITX__MCTL_DPHY_ERR_CLR__ERR_CONT_LP1_2_CLR_WOCLR 0U
+#define DSITX__MCTL_DPHY_ERR_CLR__ERR_CONT_LP1_2_CLR_WOSET 0U
+#define DSITX__MCTL_DPHY_ERR_CLR__ERR_CONT_LP1_3_CLR_MASK 0x01000000U
+#define DSITX__MCTL_DPHY_ERR_CLR__ERR_CONT_LP1_3_CLR_SHIFT 24U
+#define DSITX__MCTL_DPHY_ERR_CLR__ERR_CONT_LP1_3_CLR_WIDTH 1U
+#define DSITX__MCTL_DPHY_ERR_CLR__ERR_CONT_LP1_3_CLR_WOCLR 0U
+#define DSITX__MCTL_DPHY_ERR_CLR__ERR_CONT_LP1_3_CLR_WOSET 0U
+#define DSITX__MCTL_DPHY_ERR_CLR__ERR_CONT_LP1_4_CLR_MASK 0x02000000U
+#define DSITX__MCTL_DPHY_ERR_CLR__ERR_CONT_LP1_4_CLR_SHIFT 25U
+#define DSITX__MCTL_DPHY_ERR_CLR__ERR_CONT_LP1_4_CLR_WIDTH 1U
+#define DSITX__MCTL_DPHY_ERR_CLR__ERR_CONT_LP1_4_CLR_WOCLR 0U
+#define DSITX__MCTL_DPHY_ERR_CLR__ERR_CONT_LP1_4_CLR_WOSET 0U
+#define DSITX__MCTL_DPHY_ERR_CLR__RSVD_1_MASK 0xFC000000U
+#define DSITX__MCTL_DPHY_ERR_CLR__RSVD_1_SHIFT 26U
+#define DSITX__MCTL_DPHY_ERR_CLR__RSVD_1_WIDTH 6U
+
+#define DSITX__MCTL_MAIN_STS_FLAG_READ_MASK 0xFFFFFFFFU
+#define DSITX__MCTL_MAIN_STS_FLAG_WRITE_MASK 0xFFFFFFFFU
+#define DSITX__MCTL_MAIN_STS_FLAG__PLL_LOCK_FLAG_MASK 0x00000001U
+#define DSITX__MCTL_MAIN_STS_FLAG__PLL_LOCK_FLAG_SHIFT 0U
+#define DSITX__MCTL_MAIN_STS_FLAG__PLL_LOCK_FLAG_WIDTH 1U
+#define DSITX__MCTL_MAIN_STS_FLAG__PLL_LOCK_FLAG_WOCLR 0U
+#define DSITX__MCTL_MAIN_STS_FLAG__PLL_LOCK_FLAG_WOSET 0U
+#define DSITX__MCTL_MAIN_STS_FLAG__CLKLANE_READY_FLAG_MASK 0x00000002U
+#define DSITX__MCTL_MAIN_STS_FLAG__CLKLANE_READY_FLAG_SHIFT 1U
+#define DSITX__MCTL_MAIN_STS_FLAG__CLKLANE_READY_FLAG_WIDTH 1U
+#define DSITX__MCTL_MAIN_STS_FLAG__CLKLANE_READY_FLAG_WOCLR 0U
+#define DSITX__MCTL_MAIN_STS_FLAG__CLKLANE_READY_FLAG_WOSET 0U
+#define DSITX__MCTL_MAIN_STS_FLAG__DAT1_READY_FLAG_MASK 0x00000004U
+#define DSITX__MCTL_MAIN_STS_FLAG__DAT1_READY_FLAG_SHIFT 2U
+#define DSITX__MCTL_MAIN_STS_FLAG__DAT1_READY_FLAG_WIDTH 1U
+#define DSITX__MCTL_MAIN_STS_FLAG__DAT1_READY_FLAG_WOCLR 0U
+#define DSITX__MCTL_MAIN_STS_FLAG__DAT1_READY_FLAG_WOSET 0U
+#define DSITX__MCTL_MAIN_STS_FLAG__DAT2_READY_FLAG_MASK 0x00000008U
+#define DSITX__MCTL_MAIN_STS_FLAG__DAT2_READY_FLAG_SHIFT 3U
+#define DSITX__MCTL_MAIN_STS_FLAG__DAT2_READY_FLAG_WIDTH 1U
+#define DSITX__MCTL_MAIN_STS_FLAG__DAT2_READY_FLAG_WOCLR 0U
+#define DSITX__MCTL_MAIN_STS_FLAG__DAT2_READY_FLAG_WOSET 0U
+#define DSITX__MCTL_MAIN_STS_FLAG__DAT3_READY_FLAG_MASK 0x00000010U
+#define DSITX__MCTL_MAIN_STS_FLAG__DAT3_READY_FLAG_SHIFT 4U
+#define DSITX__MCTL_MAIN_STS_FLAG__DAT3_READY_FLAG_WIDTH 1U
+#define DSITX__MCTL_MAIN_STS_FLAG__DAT3_READY_FLAG_WOCLR 0U
+#define DSITX__MCTL_MAIN_STS_FLAG__DAT3_READY_FLAG_WOSET 0U
+#define DSITX__MCTL_MAIN_STS_FLAG__DAT4_READY_FLAG_MASK 0x00000020U
+#define DSITX__MCTL_MAIN_STS_FLAG__DAT4_READY_FLAG_SHIFT 5U
+#define DSITX__MCTL_MAIN_STS_FLAG__DAT4_READY_FLAG_WIDTH 1U
+#define DSITX__MCTL_MAIN_STS_FLAG__DAT4_READY_FLAG_WOCLR 0U
+#define DSITX__MCTL_MAIN_STS_FLAG__DAT4_READY_FLAG_WOSET 0U
+#define DSITX__MCTL_MAIN_STS_FLAG__HSTX_TO_ERR_FLAG_MASK 0x00000040U
+#define DSITX__MCTL_MAIN_STS_FLAG__HSTX_TO_ERR_FLAG_SHIFT 6U
+#define DSITX__MCTL_MAIN_STS_FLAG__HSTX_TO_ERR_FLAG_WIDTH 1U
+#define DSITX__MCTL_MAIN_STS_FLAG__HSTX_TO_ERR_FLAG_WOCLR 0U
+#define DSITX__MCTL_MAIN_STS_FLAG__HSTX_TO_ERR_FLAG_WOSET 0U
+#define DSITX__MCTL_MAIN_STS_FLAG__LPRX_TO_ERR_FLAG_MASK 0x00000080U
+#define DSITX__MCTL_MAIN_STS_FLAG__LPRX_TO_ERR_FLAG_SHIFT 7U
+#define DSITX__MCTL_MAIN_STS_FLAG__LPRX_TO_ERR_FLAG_WIDTH 1U
+#define DSITX__MCTL_MAIN_STS_FLAG__LPRX_TO_ERR_FLAG_WOCLR 0U
+#define DSITX__MCTL_MAIN_STS_FLAG__LPRX_TO_ERR_FLAG_WOSET 0U
+#define DSITX__MCTL_MAIN_STS_FLAG__IF1_UNTERM_PCK_ERR_FLAG_MASK 0x00000100U
+#define DSITX__MCTL_MAIN_STS_FLAG__IF1_UNTERM_PCK_ERR_FLAG_SHIFT 8U
+#define DSITX__MCTL_MAIN_STS_FLAG__IF1_UNTERM_PCK_ERR_FLAG_WIDTH 1U
+#define DSITX__MCTL_MAIN_STS_FLAG__IF1_UNTERM_PCK_ERR_FLAG_WOCLR 0U
+#define DSITX__MCTL_MAIN_STS_FLAG__IF1_UNTERM_PCK_ERR_FLAG_WOSET 0U
+#define DSITX__MCTL_MAIN_STS_FLAG__IF3_UNTERM_PCK_ERR_FLAG_MASK 0x00000200U
+#define DSITX__MCTL_MAIN_STS_FLAG__IF3_UNTERM_PCK_ERR_FLAG_SHIFT 9U
+#define DSITX__MCTL_MAIN_STS_FLAG__IF3_UNTERM_PCK_ERR_FLAG_WIDTH 1U
+#define DSITX__MCTL_MAIN_STS_FLAG__IF3_UNTERM_PCK_ERR_FLAG_WOCLR 0U
+#define DSITX__MCTL_MAIN_STS_FLAG__IF3_UNTERM_PCK_ERR_FLAG_WOSET 0U
+#define DSITX__MCTL_MAIN_STS_FLAG__RSVD_0_MASK 0xFFFFFC00U
+#define DSITX__MCTL_MAIN_STS_FLAG__RSVD_0_SHIFT 10U
+#define DSITX__MCTL_MAIN_STS_FLAG__RSVD_0_WIDTH 22U
+
+#define DSITX__CMD_MODE_STS_FLAG_READ_MASK 0xFFFFFFFFU
+#define DSITX__CMD_MODE_STS_FLAG_WRITE_MASK 0xFFFFFFFFU
+#define DSITX__CMD_MODE_STS_FLAG__CSM_RUNNING_FLAG_MASK 0x00000001U
+#define DSITX__CMD_MODE_STS_FLAG__CSM_RUNNING_FLAG_SHIFT 0U
+#define DSITX__CMD_MODE_STS_FLAG__CSM_RUNNING_FLAG_WIDTH 1U
+#define DSITX__CMD_MODE_STS_FLAG__CSM_RUNNING_FLAG_WOCLR 0U
+#define DSITX__CMD_MODE_STS_FLAG__CSM_RUNNING_FLAG_WOSET 0U
+#define DSITX__CMD_MODE_STS_FLAG__ERR_NO_TE_FLAG_MASK 0x00000002U
+#define DSITX__CMD_MODE_STS_FLAG__ERR_NO_TE_FLAG_SHIFT 1U
+#define DSITX__CMD_MODE_STS_FLAG__ERR_NO_TE_FLAG_WIDTH 1U
+#define DSITX__CMD_MODE_STS_FLAG__ERR_NO_TE_FLAG_WOCLR 0U
+#define DSITX__CMD_MODE_STS_FLAG__ERR_NO_TE_FLAG_WOSET 0U
+#define DSITX__CMD_MODE_STS_FLAG__ERR_TE_MISS_FLAG_MASK 0x00000004U
+#define DSITX__CMD_MODE_STS_FLAG__ERR_TE_MISS_FLAG_SHIFT 2U
+#define DSITX__CMD_MODE_STS_FLAG__ERR_TE_MISS_FLAG_WIDTH 1U
+#define DSITX__CMD_MODE_STS_FLAG__ERR_TE_MISS_FLAG_WOCLR 0U
+#define DSITX__CMD_MODE_STS_FLAG__ERR_TE_MISS_FLAG_WOSET 0U
+#define DSITX__CMD_MODE_STS_FLAG__ERR_UNWANTED_RD_FLAG_MASK 0x00000008U
+#define DSITX__CMD_MODE_STS_FLAG__ERR_UNWANTED_RD_FLAG_SHIFT 3U
+#define DSITX__CMD_MODE_STS_FLAG__ERR_UNWANTED_RD_FLAG_WIDTH 1U
+#define DSITX__CMD_MODE_STS_FLAG__ERR_UNWANTED_RD_FLAG_WOCLR 0U
+#define DSITX__CMD_MODE_STS_FLAG__ERR_UNWANTED_RD_FLAG_WOSET 0U
+#define DSITX__CMD_MODE_STS_FLAG__ERR_IF1_UNDERRUN_FLAG_MASK 0x00000010U
+#define DSITX__CMD_MODE_STS_FLAG__ERR_IF1_UNDERRUN_FLAG_SHIFT 4U
+#define DSITX__CMD_MODE_STS_FLAG__ERR_IF1_UNDERRUN_FLAG_WIDTH 1U
+#define DSITX__CMD_MODE_STS_FLAG__ERR_IF1_UNDERRUN_FLAG_WOCLR 0U
+#define DSITX__CMD_MODE_STS_FLAG__ERR_IF1_UNDERRUN_FLAG_WOSET 0U
+#define DSITX__CMD_MODE_STS_FLAG__ERR_IF3_UNDERRUN_FLAG_MASK 0x00000020U
+#define DSITX__CMD_MODE_STS_FLAG__ERR_IF3_UNDERRUN_FLAG_SHIFT 5U
+#define DSITX__CMD_MODE_STS_FLAG__ERR_IF3_UNDERRUN_FLAG_WIDTH 1U
+#define DSITX__CMD_MODE_STS_FLAG__ERR_IF3_UNDERRUN_FLAG_WOCLR 0U
+#define DSITX__CMD_MODE_STS_FLAG__ERR_IF3_UNDERRUN_FLAG_WOSET 0U
+#define DSITX__CMD_MODE_STS_FLAG__RSVD_0_MASK 0xFFFFFFC0U
+#define DSITX__CMD_MODE_STS_FLAG__RSVD_0_SHIFT 6U
+#define DSITX__CMD_MODE_STS_FLAG__RSVD_0_WIDTH 26U
+
+#define DSITX__DIRECT_CMD_STS_FLAG_READ_MASK 0xFFFFFFFFU
+#define DSITX__DIRECT_CMD_STS_FLAG_WRITE_MASK 0xFFFFFFFFU
+#define DSITX__DIRECT_CMD_STS_FLAG__CMD_TRANSMISSION_FLAG_MASK 0x00000001U
+#define DSITX__DIRECT_CMD_STS_FLAG__CMD_TRANSMISSION_FLAG_SHIFT 0U
+#define DSITX__DIRECT_CMD_STS_FLAG__CMD_TRANSMISSION_FLAG_WIDTH 1U
+#define DSITX__DIRECT_CMD_STS_FLAG__CMD_TRANSMISSION_FLAG_WOCLR 0U
+#define DSITX__DIRECT_CMD_STS_FLAG__CMD_TRANSMISSION_FLAG_WOSET 0U
+#define DSITX__DIRECT_CMD_STS_FLAG__WRITE_COMPLETED_FLAG_MASK 0x00000002U
+#define DSITX__DIRECT_CMD_STS_FLAG__WRITE_COMPLETED_FLAG_SHIFT 1U
+#define DSITX__DIRECT_CMD_STS_FLAG__WRITE_COMPLETED_FLAG_WIDTH 1U
+#define DSITX__DIRECT_CMD_STS_FLAG__WRITE_COMPLETED_FLAG_WOCLR 0U
+#define DSITX__DIRECT_CMD_STS_FLAG__WRITE_COMPLETED_FLAG_WOSET 0U
+#define DSITX__DIRECT_CMD_STS_FLAG__TRIGGER_COMPLETED_FLAG_MASK 0x00000004U
+#define DSITX__DIRECT_CMD_STS_FLAG__TRIGGER_COMPLETED_FLAG_SHIFT 2U
+#define DSITX__DIRECT_CMD_STS_FLAG__TRIGGER_COMPLETED_FLAG_WIDTH 1U
+#define DSITX__DIRECT_CMD_STS_FLAG__TRIGGER_COMPLETED_FLAG_WOCLR 0U
+#define DSITX__DIRECT_CMD_STS_FLAG__TRIGGER_COMPLETED_FLAG_WOSET 0U
+#define DSITX__DIRECT_CMD_STS_FLAG__READ_COMPLETED_FLAG_MASK 0x00000008U
+#define DSITX__DIRECT_CMD_STS_FLAG__READ_COMPLETED_FLAG_SHIFT 3U
+#define DSITX__DIRECT_CMD_STS_FLAG__READ_COMPLETED_FLAG_WIDTH 1U
+#define DSITX__DIRECT_CMD_STS_FLAG__READ_COMPLETED_FLAG_WOCLR 0U
+#define DSITX__DIRECT_CMD_STS_FLAG__READ_COMPLETED_FLAG_WOSET 0U
+#define DSITX__DIRECT_CMD_STS_FLAG__ACKNOWLEDGE_RECEIVED_FLAG_MASK 0x00000010U
+#define DSITX__DIRECT_CMD_STS_FLAG__ACKNOWLEDGE_RECEIVED_FLAG_SHIFT 4U
+#define DSITX__DIRECT_CMD_STS_FLAG__ACKNOWLEDGE_RECEIVED_FLAG_WIDTH 1U
+#define DSITX__DIRECT_CMD_STS_FLAG__ACKNOWLEDGE_RECEIVED_FLAG_WOCLR 0U
+#define DSITX__DIRECT_CMD_STS_FLAG__ACKNOWLEDGE_RECEIVED_FLAG_WOSET 0U
+#define DSITX__DIRECT_CMD_STS_FLAG__ACK_WITH_ERR_RECEIVED_FLAG_MASK 0x00000020U
+#define DSITX__DIRECT_CMD_STS_FLAG__ACK_WITH_ERR_RECEIVED_FLAG_SHIFT 5U
+#define DSITX__DIRECT_CMD_STS_FLAG__ACK_WITH_ERR_RECEIVED_FLAG_WIDTH 1U
+#define DSITX__DIRECT_CMD_STS_FLAG__ACK_WITH_ERR_RECEIVED_FLAG_WOCLR 0U
+#define DSITX__DIRECT_CMD_STS_FLAG__ACK_WITH_ERR_RECEIVED_FLAG_WOSET 0U
+#define DSITX__DIRECT_CMD_STS_FLAG__TRIGGER_RECEIVED_FLAG_MASK 0x00000040U
+#define DSITX__DIRECT_CMD_STS_FLAG__TRIGGER_RECEIVED_FLAG_SHIFT 6U
+#define DSITX__DIRECT_CMD_STS_FLAG__TRIGGER_RECEIVED_FLAG_WIDTH 1U
+#define DSITX__DIRECT_CMD_STS_FLAG__TRIGGER_RECEIVED_FLAG_WOCLR 0U
+#define DSITX__DIRECT_CMD_STS_FLAG__TRIGGER_RECEIVED_FLAG_WOSET 0U
+#define DSITX__DIRECT_CMD_STS_FLAG__TE_RECEIVED_FLAG_MASK 0x00000080U
+#define DSITX__DIRECT_CMD_STS_FLAG__TE_RECEIVED_FLAG_SHIFT 7U
+#define DSITX__DIRECT_CMD_STS_FLAG__TE_RECEIVED_FLAG_WIDTH 1U
+#define DSITX__DIRECT_CMD_STS_FLAG__TE_RECEIVED_FLAG_WOCLR 0U
+#define DSITX__DIRECT_CMD_STS_FLAG__TE_RECEIVED_FLAG_WOSET 0U
+#define DSITX__DIRECT_CMD_STS_FLAG__BTA_COMPLETED_FLAG_MASK 0x00000100U
+#define DSITX__DIRECT_CMD_STS_FLAG__BTA_COMPLETED_FLAG_SHIFT 8U
+#define DSITX__DIRECT_CMD_STS_FLAG__BTA_COMPLETED_FLAG_WIDTH 1U
+#define DSITX__DIRECT_CMD_STS_FLAG__BTA_COMPLETED_FLAG_WOCLR 0U
+#define DSITX__DIRECT_CMD_STS_FLAG__BTA_COMPLETED_FLAG_WOSET 0U
+#define DSITX__DIRECT_CMD_STS_FLAG__BTA_FINISHED_FLAG_MASK 0x00000200U
+#define DSITX__DIRECT_CMD_STS_FLAG__BTA_FINISHED_FLAG_SHIFT 9U
+#define DSITX__DIRECT_CMD_STS_FLAG__BTA_FINISHED_FLAG_WIDTH 1U
+#define DSITX__DIRECT_CMD_STS_FLAG__BTA_FINISHED_FLAG_WOCLR 0U
+#define DSITX__DIRECT_CMD_STS_FLAG__BTA_FINISHED_FLAG_WOSET 0U
+#define DSITX__DIRECT_CMD_STS_FLAG__READ_COMPLETED_WITH_ERR_FLAG_MASK 0x00000400U
+#define DSITX__DIRECT_CMD_STS_FLAG__READ_COMPLETED_WITH_ERR_FLAG_SHIFT 10U
+#define DSITX__DIRECT_CMD_STS_FLAG__READ_COMPLETED_WITH_ERR_FLAG_WIDTH 1U
+#define DSITX__DIRECT_CMD_STS_FLAG__READ_COMPLETED_WITH_ERR_FLAG_WOCLR 0U
+#define DSITX__DIRECT_CMD_STS_FLAG__READ_COMPLETED_WITH_ERR_FLAG_WOSET 0U
+#define DSITX__DIRECT_CMD_STS_FLAG__RSVD_0_MASK 0xFFFFF800U
+#define DSITX__DIRECT_CMD_STS_FLAG__RSVD_0_SHIFT 11U
+#define DSITX__DIRECT_CMD_STS_FLAG__RSVD_0_WIDTH 21U
+
+#define DSITX__DIRECT_CMD_RD_STS_FLAG_READ_MASK 0xFFFFFFFFU
+#define DSITX__DIRECT_CMD_RD_STS_FLAG_WRITE_MASK 0xFFFFFFFFU
+#define DSITX__DIRECT_CMD_RD_STS_FLAG__ERR_FIXED_FLAG_MASK 0x00000001U
+#define DSITX__DIRECT_CMD_RD_STS_FLAG__ERR_FIXED_FLAG_SHIFT 0U
+#define DSITX__DIRECT_CMD_RD_STS_FLAG__ERR_FIXED_FLAG_WIDTH 1U
+#define DSITX__DIRECT_CMD_RD_STS_FLAG__ERR_FIXED_FLAG_WOCLR 0U
+#define DSITX__DIRECT_CMD_RD_STS_FLAG__ERR_FIXED_FLAG_WOSET 0U
+#define DSITX__DIRECT_CMD_RD_STS_FLAG__ERR_UNCORRECTABLE_FLAG_MASK 0x00000002U
+#define DSITX__DIRECT_CMD_RD_STS_FLAG__ERR_UNCORRECTABLE_FLAG_SHIFT 1U
+#define DSITX__DIRECT_CMD_RD_STS_FLAG__ERR_UNCORRECTABLE_FLAG_WIDTH 1U
+#define DSITX__DIRECT_CMD_RD_STS_FLAG__ERR_UNCORRECTABLE_FLAG_WOCLR 0U
+#define DSITX__DIRECT_CMD_RD_STS_FLAG__ERR_UNCORRECTABLE_FLAG_WOSET 0U
+#define DSITX__DIRECT_CMD_RD_STS_FLAG__ERR_CHECKSUM_FLAG_MASK 0x00000004U
+#define DSITX__DIRECT_CMD_RD_STS_FLAG__ERR_CHECKSUM_FLAG_SHIFT 2U
+#define DSITX__DIRECT_CMD_RD_STS_FLAG__ERR_CHECKSUM_FLAG_WIDTH 1U
+#define DSITX__DIRECT_CMD_RD_STS_FLAG__ERR_CHECKSUM_FLAG_WOCLR 0U
+#define DSITX__DIRECT_CMD_RD_STS_FLAG__ERR_CHECKSUM_FLAG_WOSET 0U
+#define DSITX__DIRECT_CMD_RD_STS_FLAG__ERR_UNDECODABLE_FLAG_MASK 0x00000008U
+#define DSITX__DIRECT_CMD_RD_STS_FLAG__ERR_UNDECODABLE_FLAG_SHIFT 3U
+#define DSITX__DIRECT_CMD_RD_STS_FLAG__ERR_UNDECODABLE_FLAG_WIDTH 1U
+#define DSITX__DIRECT_CMD_RD_STS_FLAG__ERR_UNDECODABLE_FLAG_WOCLR 0U
+#define DSITX__DIRECT_CMD_RD_STS_FLAG__ERR_UNDECODABLE_FLAG_WOSET 0U
+#define DSITX__DIRECT_CMD_RD_STS_FLAG__ERR_RECEIVE_FLAG_MASK 0x00000010U
+#define DSITX__DIRECT_CMD_RD_STS_FLAG__ERR_RECEIVE_FLAG_SHIFT 4U
+#define DSITX__DIRECT_CMD_RD_STS_FLAG__ERR_RECEIVE_FLAG_WIDTH 1U
+#define DSITX__DIRECT_CMD_RD_STS_FLAG__ERR_RECEIVE_FLAG_WOCLR 0U
+#define DSITX__DIRECT_CMD_RD_STS_FLAG__ERR_RECEIVE_FLAG_WOSET 0U
+#define DSITX__DIRECT_CMD_RD_STS_FLAG__ERR_OVERSIZE_FLAG_MASK 0x00000020U
+#define DSITX__DIRECT_CMD_RD_STS_FLAG__ERR_OVERSIZE_FLAG_SHIFT 5U
+#define DSITX__DIRECT_CMD_RD_STS_FLAG__ERR_OVERSIZE_FLAG_WIDTH 1U
+#define DSITX__DIRECT_CMD_RD_STS_FLAG__ERR_OVERSIZE_FLAG_WOCLR 0U
+#define DSITX__DIRECT_CMD_RD_STS_FLAG__ERR_OVERSIZE_FLAG_WOSET 0U
+#define DSITX__DIRECT_CMD_RD_STS_FLAG__ERR_WRONG_LENGTH_FLAG_MASK 0x00000040U
+#define DSITX__DIRECT_CMD_RD_STS_FLAG__ERR_WRONG_LENGTH_FLAG_SHIFT 6U
+#define DSITX__DIRECT_CMD_RD_STS_FLAG__ERR_WRONG_LENGTH_FLAG_WIDTH 1U
+#define DSITX__DIRECT_CMD_RD_STS_FLAG__ERR_WRONG_LENGTH_FLAG_WOCLR 0U
+#define DSITX__DIRECT_CMD_RD_STS_FLAG__ERR_WRONG_LENGTH_FLAG_WOSET 0U
+#define DSITX__DIRECT_CMD_RD_STS_FLAG__ERR_MISSING_EOT_FLAG_MASK 0x00000080U
+#define DSITX__DIRECT_CMD_RD_STS_FLAG__ERR_MISSING_EOT_FLAG_SHIFT 7U
+#define DSITX__DIRECT_CMD_RD_STS_FLAG__ERR_MISSING_EOT_FLAG_WIDTH 1U
+#define DSITX__DIRECT_CMD_RD_STS_FLAG__ERR_MISSING_EOT_FLAG_WOCLR 0U
+#define DSITX__DIRECT_CMD_RD_STS_FLAG__ERR_MISSING_EOT_FLAG_WOSET 0U
+#define DSITX__DIRECT_CMD_RD_STS_FLAG__ERR_EOT_WITH_ERR_FLAG_MASK 0x00000100U
+#define DSITX__DIRECT_CMD_RD_STS_FLAG__ERR_EOT_WITH_ERR_FLAG_SHIFT 8U
+#define DSITX__DIRECT_CMD_RD_STS_FLAG__ERR_EOT_WITH_ERR_FLAG_WIDTH 1U
+#define DSITX__DIRECT_CMD_RD_STS_FLAG__ERR_EOT_WITH_ERR_FLAG_WOCLR 0U
+#define DSITX__DIRECT_CMD_RD_STS_FLAG__ERR_EOT_WITH_ERR_FLAG_WOSET 0U
+#define DSITX__DIRECT_CMD_RD_STS_FLAG__RSVD_0_MASK 0xFFFFFE00U
+#define DSITX__DIRECT_CMD_RD_STS_FLAG__RSVD_0_SHIFT 9U
+#define DSITX__DIRECT_CMD_RD_STS_FLAG__RSVD_0_WIDTH 23U
+
+#define DSITX__VID_MODE_STS_FLAG_READ_MASK 0xFFFFFFFFU
+#define DSITX__VID_MODE_STS_FLAG_WRITE_MASK 0xFFFFFFFFU
+#define DSITX__VID_MODE_STS_FLAG__VSG_STS_FLAG_MASK 0x00000001U
+#define DSITX__VID_MODE_STS_FLAG__VSG_STS_FLAG_SHIFT 0U
+#define DSITX__VID_MODE_STS_FLAG__VSG_STS_FLAG_WIDTH 1U
+#define DSITX__VID_MODE_STS_FLAG__VSG_STS_FLAG_WOCLR 0U
+#define DSITX__VID_MODE_STS_FLAG__VSG_STS_FLAG_WOSET 0U
+#define DSITX__VID_MODE_STS_FLAG__ERR_MISSING_DATA_FLAG_MASK 0x00000002U
+#define DSITX__VID_MODE_STS_FLAG__ERR_MISSING_DATA_FLAG_SHIFT 1U
+#define DSITX__VID_MODE_STS_FLAG__ERR_MISSING_DATA_FLAG_WIDTH 1U
+#define DSITX__VID_MODE_STS_FLAG__ERR_MISSING_DATA_FLAG_WOCLR 0U
+#define DSITX__VID_MODE_STS_FLAG__ERR_MISSING_DATA_FLAG_WOSET 0U
+#define DSITX__VID_MODE_STS_FLAG__ERR_MISSING_HSYNC_FLAG_MASK 0x00000004U
+#define DSITX__VID_MODE_STS_FLAG__ERR_MISSING_HSYNC_FLAG_SHIFT 2U
+#define DSITX__VID_MODE_STS_FLAG__ERR_MISSING_HSYNC_FLAG_WIDTH 1U
+#define DSITX__VID_MODE_STS_FLAG__ERR_MISSING_HSYNC_FLAG_WOCLR 0U
+#define DSITX__VID_MODE_STS_FLAG__ERR_MISSING_HSYNC_FLAG_WOSET 0U
+#define DSITX__VID_MODE_STS_FLAG__ERR_MISS_VSYNC_FLAG_MASK 0x00000008U
+#define DSITX__VID_MODE_STS_FLAG__ERR_MISS_VSYNC_FLAG_SHIFT 3U
+#define DSITX__VID_MODE_STS_FLAG__ERR_MISS_VSYNC_FLAG_WIDTH 1U
+#define DSITX__VID_MODE_STS_FLAG__ERR_MISS_VSYNC_FLAG_WOCLR 0U
+#define DSITX__VID_MODE_STS_FLAG__ERR_MISS_VSYNC_FLAG_WOSET 0U
+#define DSITX__VID_MODE_STS_FLAG__ERR_SMALL_LENGTH_FLAG_MASK 0x00000010U
+#define DSITX__VID_MODE_STS_FLAG__ERR_SMALL_LENGTH_FLAG_SHIFT 4U
+#define DSITX__VID_MODE_STS_FLAG__ERR_SMALL_LENGTH_FLAG_WIDTH 1U
+#define DSITX__VID_MODE_STS_FLAG__ERR_SMALL_LENGTH_FLAG_WOCLR 0U
+#define DSITX__VID_MODE_STS_FLAG__ERR_SMALL_LENGTH_FLAG_WOSET 0U
+#define DSITX__VID_MODE_STS_FLAG__ERR_SMALL_HEIGHT_FLAG_MASK 0x00000020U
+#define DSITX__VID_MODE_STS_FLAG__ERR_SMALL_HEIGHT_FLAG_SHIFT 5U
+#define DSITX__VID_MODE_STS_FLAG__ERR_SMALL_HEIGHT_FLAG_WIDTH 1U
+#define DSITX__VID_MODE_STS_FLAG__ERR_SMALL_HEIGHT_FLAG_WOCLR 0U
+#define DSITX__VID_MODE_STS_FLAG__ERR_SMALL_HEIGHT_FLAG_WOSET 0U
+#define DSITX__VID_MODE_STS_FLAG__ERR_SHORTWRITE_FLAG_MASK 0x00000040U
+#define DSITX__VID_MODE_STS_FLAG__ERR_SHORTWRITE_FLAG_SHIFT 6U
+#define DSITX__VID_MODE_STS_FLAG__ERR_SHORTWRITE_FLAG_WIDTH 1U
+#define DSITX__VID_MODE_STS_FLAG__ERR_SHORTWRITE_FLAG_WOCLR 0U
+#define DSITX__VID_MODE_STS_FLAG__ERR_SHORTWRITE_FLAG_WOSET 0U
+#define DSITX__VID_MODE_STS_FLAG__ERR_LONGWRITE_FLAG_MASK 0x00000080U
+#define DSITX__VID_MODE_STS_FLAG__ERR_LONGWRITE_FLAG_SHIFT 7U
+#define DSITX__VID_MODE_STS_FLAG__ERR_LONGWRITE_FLAG_WIDTH 1U
+#define DSITX__VID_MODE_STS_FLAG__ERR_LONGWRITE_FLAG_WOCLR 0U
+#define DSITX__VID_MODE_STS_FLAG__ERR_LONGWRITE_FLAG_WOSET 0U
+#define DSITX__VID_MODE_STS_FLAG__ERR_LONGREAD_FLAG_MASK 0x00000100U
+#define DSITX__VID_MODE_STS_FLAG__ERR_LONGREAD_FLAG_SHIFT 8U
+#define DSITX__VID_MODE_STS_FLAG__ERR_LONGREAD_FLAG_WIDTH 1U
+#define DSITX__VID_MODE_STS_FLAG__ERR_LONGREAD_FLAG_WOCLR 0U
+#define DSITX__VID_MODE_STS_FLAG__ERR_LONGREAD_FLAG_WOSET 0U
+#define DSITX__VID_MODE_STS_FLAG__ERR_VRS_WRONG_LENGTH_FLAG_MASK 0x00000200U
+#define DSITX__VID_MODE_STS_FLAG__ERR_VRS_WRONG_LENGTH_FLAG_SHIFT 9U
+#define DSITX__VID_MODE_STS_FLAG__ERR_VRS_WRONG_LENGTH_FLAG_WIDTH 1U
+#define DSITX__VID_MODE_STS_FLAG__ERR_VRS_WRONG_LENGTH_FLAG_WOCLR 0U
+#define DSITX__VID_MODE_STS_FLAG__ERR_VRS_WRONG_LENGTH_FLAG_WOSET 0U
+#define DSITX__VID_MODE_STS_FLAG__FLAG_VSG_RECOVERY_MASK 0x00000400U
+#define DSITX__VID_MODE_STS_FLAG__FLAG_VSG_RECOVERY_SHIFT 10U
+#define DSITX__VID_MODE_STS_FLAG__FLAG_VSG_RECOVERY_WIDTH 1U
+#define DSITX__VID_MODE_STS_FLAG__FLAG_VSG_RECOVERY_WOCLR 0U
+#define DSITX__VID_MODE_STS_FLAG__FLAG_VSG_RECOVERY_WOSET 0U
+#define DSITX__VID_MODE_STS_FLAG__RSVD_0_MASK 0xFFFFF800U
+#define DSITX__VID_MODE_STS_FLAG__RSVD_0_SHIFT 11U
+#define DSITX__VID_MODE_STS_FLAG__RSVD_0_WIDTH 21U
+
+#define DSITX__TG_STS_FLAG_READ_MASK 0xFFFFFFFFU
+#define DSITX__TG_STS_FLAG_WRITE_MASK 0xFFFFFFFFU
+#define DSITX__TG_STS_FLAG__TVG_STS_FLAG_MASK 0x00000001U
+#define DSITX__TG_STS_FLAG__TVG_STS_FLAG_SHIFT 0U
+#define DSITX__TG_STS_FLAG__TVG_STS_FLAG_WIDTH 1U
+#define DSITX__TG_STS_FLAG__TVG_STS_FLAG_WOCLR 0U
+#define DSITX__TG_STS_FLAG__TVG_STS_FLAG_WOSET 0U
+#define DSITX__TG_STS_FLAG__RSVD_0_MASK 0xFFFFFFFEU
+#define DSITX__TG_STS_FLAG__RSVD_0_SHIFT 1U
+#define DSITX__TG_STS_FLAG__RSVD_0_WIDTH 31U
+
+#define DSITX__MCTL_DPHY_ERR_FLAG_READ_MASK 0xFFFFFFFFU
+#define DSITX__MCTL_DPHY_ERR_FLAG_WRITE_MASK 0xFFFFFFFFU
+#define DSITX__MCTL_DPHY_ERR_FLAG__RSVD_0_MASK 0x0000003FU
+#define DSITX__MCTL_DPHY_ERR_FLAG__RSVD_0_SHIFT 0U
+#define DSITX__MCTL_DPHY_ERR_FLAG__RSVD_0_WIDTH 6U
+#define DSITX__MCTL_DPHY_ERR_FLAG__ERR_ESC_1_FLAG_MASK 0x00000040U
+#define DSITX__MCTL_DPHY_ERR_FLAG__ERR_ESC_1_FLAG_SHIFT 6U
+#define DSITX__MCTL_DPHY_ERR_FLAG__ERR_ESC_1_FLAG_WIDTH 1U
+#define DSITX__MCTL_DPHY_ERR_FLAG__ERR_ESC_1_FLAG_WOCLR 0U
+#define DSITX__MCTL_DPHY_ERR_FLAG__ERR_ESC_1_FLAG_WOSET 0U
+#define DSITX__MCTL_DPHY_ERR_FLAG__ERR_ESC_2_FLAG_MASK 0x00000080U
+#define DSITX__MCTL_DPHY_ERR_FLAG__ERR_ESC_2_FLAG_SHIFT 7U
+#define DSITX__MCTL_DPHY_ERR_FLAG__ERR_ESC_2_FLAG_WIDTH 1U
+#define DSITX__MCTL_DPHY_ERR_FLAG__ERR_ESC_2_FLAG_WOCLR 0U
+#define DSITX__MCTL_DPHY_ERR_FLAG__ERR_ESC_2_FLAG_WOSET 0U
+#define DSITX__MCTL_DPHY_ERR_FLAG__ERR_ESC_3_FLAG_MASK 0x00000100U
+#define DSITX__MCTL_DPHY_ERR_FLAG__ERR_ESC_3_FLAG_SHIFT 8U
+#define DSITX__MCTL_DPHY_ERR_FLAG__ERR_ESC_3_FLAG_WIDTH 1U
+#define DSITX__MCTL_DPHY_ERR_FLAG__ERR_ESC_3_FLAG_WOCLR 0U
+#define DSITX__MCTL_DPHY_ERR_FLAG__ERR_ESC_3_FLAG_WOSET 0U
+#define DSITX__MCTL_DPHY_ERR_FLAG__ERR_ESC_4_FLAG_MASK 0x00000200U
+#define DSITX__MCTL_DPHY_ERR_FLAG__ERR_ESC_4_FLAG_SHIFT 9U
+#define DSITX__MCTL_DPHY_ERR_FLAG__ERR_ESC_4_FLAG_WIDTH 1U
+#define DSITX__MCTL_DPHY_ERR_FLAG__ERR_ESC_4_FLAG_WOCLR 0U
+#define DSITX__MCTL_DPHY_ERR_FLAG__ERR_ESC_4_FLAG_WOSET 0U
+#define DSITX__MCTL_DPHY_ERR_FLAG__ERR_SYNCESC_1_FLAG_MASK 0x00000400U
+#define DSITX__MCTL_DPHY_ERR_FLAG__ERR_SYNCESC_1_FLAG_SHIFT 10U
+#define DSITX__MCTL_DPHY_ERR_FLAG__ERR_SYNCESC_1_FLAG_WIDTH 1U
+#define DSITX__MCTL_DPHY_ERR_FLAG__ERR_SYNCESC_1_FLAG_WOCLR 0U
+#define DSITX__MCTL_DPHY_ERR_FLAG__ERR_SYNCESC_1_FLAG_WOSET 0U
+#define DSITX__MCTL_DPHY_ERR_FLAG__ERR_SYNCESC_2_FLAG_MASK 0x00000800U
+#define DSITX__MCTL_DPHY_ERR_FLAG__ERR_SYNCESC_2_FLAG_SHIFT 11U
+#define DSITX__MCTL_DPHY_ERR_FLAG__ERR_SYNCESC_2_FLAG_WIDTH 1U
+#define DSITX__MCTL_DPHY_ERR_FLAG__ERR_SYNCESC_2_FLAG_WOCLR 0U
+#define DSITX__MCTL_DPHY_ERR_FLAG__ERR_SYNCESC_2_FLAG_WOSET 0U
+#define DSITX__MCTL_DPHY_ERR_FLAG__ERR_SYNCESC_3_FLAG_MASK 0x00001000U
+#define DSITX__MCTL_DPHY_ERR_FLAG__ERR_SYNCESC_3_FLAG_SHIFT 12U
+#define DSITX__MCTL_DPHY_ERR_FLAG__ERR_SYNCESC_3_FLAG_WIDTH 1U
+#define DSITX__MCTL_DPHY_ERR_FLAG__ERR_SYNCESC_3_FLAG_WOCLR 0U
+#define DSITX__MCTL_DPHY_ERR_FLAG__ERR_SYNCESC_3_FLAG_WOSET 0U
+#define DSITX__MCTL_DPHY_ERR_FLAG__ERR_SYNCESC_4_FLAG_MASK 0x00002000U
+#define DSITX__MCTL_DPHY_ERR_FLAG__ERR_SYNCESC_4_FLAG_SHIFT 13U
+#define DSITX__MCTL_DPHY_ERR_FLAG__ERR_SYNCESC_4_FLAG_WIDTH 1U
+#define DSITX__MCTL_DPHY_ERR_FLAG__ERR_SYNCESC_4_FLAG_WOCLR 0U
+#define DSITX__MCTL_DPHY_ERR_FLAG__ERR_SYNCESC_4_FLAG_WOSET 0U
+#define DSITX__MCTL_DPHY_ERR_FLAG__ERR_CONTROL_1_FLAG_MASK 0x00004000U
+#define DSITX__MCTL_DPHY_ERR_FLAG__ERR_CONTROL_1_FLAG_SHIFT 14U
+#define DSITX__MCTL_DPHY_ERR_FLAG__ERR_CONTROL_1_FLAG_WIDTH 1U
+#define DSITX__MCTL_DPHY_ERR_FLAG__ERR_CONTROL_1_FLAG_WOCLR 0U
+#define DSITX__MCTL_DPHY_ERR_FLAG__ERR_CONTROL_1_FLAG_WOSET 0U
+#define DSITX__MCTL_DPHY_ERR_FLAG__ERR_CONTROL_2_FLAG_MASK 0x00008000U
+#define DSITX__MCTL_DPHY_ERR_FLAG__ERR_CONTROL_2_FLAG_SHIFT 15U
+#define DSITX__MCTL_DPHY_ERR_FLAG__ERR_CONTROL_2_FLAG_WIDTH 1U
+#define DSITX__MCTL_DPHY_ERR_FLAG__ERR_CONTROL_2_FLAG_WOCLR 0U
+#define DSITX__MCTL_DPHY_ERR_FLAG__ERR_CONTROL_2_FLAG_WOSET 0U
+#define DSITX__MCTL_DPHY_ERR_FLAG__ERR_CONTROL_3_FLAG_MASK 0x00010000U
+#define DSITX__MCTL_DPHY_ERR_FLAG__ERR_CONTROL_3_FLAG_SHIFT 16U
+#define DSITX__MCTL_DPHY_ERR_FLAG__ERR_CONTROL_3_FLAG_WIDTH 1U
+#define DSITX__MCTL_DPHY_ERR_FLAG__ERR_CONTROL_3_FLAG_WOCLR 0U
+#define DSITX__MCTL_DPHY_ERR_FLAG__ERR_CONTROL_3_FLAG_WOSET 0U
+#define DSITX__MCTL_DPHY_ERR_FLAG__ERR_CONTROL_4_FLAG_MASK 0x00020000U
+#define DSITX__MCTL_DPHY_ERR_FLAG__ERR_CONTROL_4_FLAG_SHIFT 17U
+#define DSITX__MCTL_DPHY_ERR_FLAG__ERR_CONTROL_4_FLAG_WIDTH 1U
+#define DSITX__MCTL_DPHY_ERR_FLAG__ERR_CONTROL_4_FLAG_WOCLR 0U
+#define DSITX__MCTL_DPHY_ERR_FLAG__ERR_CONTROL_4_FLAG_WOSET 0U
+#define DSITX__MCTL_DPHY_ERR_FLAG__ERR_CONT_LP0_1_FLAG_MASK 0x00040000U
+#define DSITX__MCTL_DPHY_ERR_FLAG__ERR_CONT_LP0_1_FLAG_SHIFT 18U
+#define DSITX__MCTL_DPHY_ERR_FLAG__ERR_CONT_LP0_1_FLAG_WIDTH 1U
+#define DSITX__MCTL_DPHY_ERR_FLAG__ERR_CONT_LP0_1_FLAG_WOCLR 0U
+#define DSITX__MCTL_DPHY_ERR_FLAG__ERR_CONT_LP0_1_FLAG_WOSET 0U
+#define DSITX__MCTL_DPHY_ERR_FLAG__ERR_CONT_LP0_2_FLAG_MASK 0x00080000U
+#define DSITX__MCTL_DPHY_ERR_FLAG__ERR_CONT_LP0_2_FLAG_SHIFT 19U
+#define DSITX__MCTL_DPHY_ERR_FLAG__ERR_CONT_LP0_2_FLAG_WIDTH 1U
+#define DSITX__MCTL_DPHY_ERR_FLAG__ERR_CONT_LP0_2_FLAG_WOCLR 0U
+#define DSITX__MCTL_DPHY_ERR_FLAG__ERR_CONT_LP0_2_FLAG_WOSET 0U
+#define DSITX__MCTL_DPHY_ERR_FLAG__ERR_CONT_LP0_3_FLAG_MASK 0x00100000U
+#define DSITX__MCTL_DPHY_ERR_FLAG__ERR_CONT_LP0_3_FLAG_SHIFT 20U
+#define DSITX__MCTL_DPHY_ERR_FLAG__ERR_CONT_LP0_3_FLAG_WIDTH 1U
+#define DSITX__MCTL_DPHY_ERR_FLAG__ERR_CONT_LP0_3_FLAG_WOCLR 0U
+#define DSITX__MCTL_DPHY_ERR_FLAG__ERR_CONT_LP0_3_FLAG_WOSET 0U
+#define DSITX__MCTL_DPHY_ERR_FLAG__ERR_CONT_LP0_4_FLAG_MASK 0x00200000U
+#define DSITX__MCTL_DPHY_ERR_FLAG__ERR_CONT_LP0_4_FLAG_SHIFT 21U
+#define DSITX__MCTL_DPHY_ERR_FLAG__ERR_CONT_LP0_4_FLAG_WIDTH 1U
+#define DSITX__MCTL_DPHY_ERR_FLAG__ERR_CONT_LP0_4_FLAG_WOCLR 0U
+#define DSITX__MCTL_DPHY_ERR_FLAG__ERR_CONT_LP0_4_FLAG_WOSET 0U
+#define DSITX__MCTL_DPHY_ERR_FLAG__ERR_CONT_LP1_1_FLAG_MASK 0x00400000U
+#define DSITX__MCTL_DPHY_ERR_FLAG__ERR_CONT_LP1_1_FLAG_SHIFT 22U
+#define DSITX__MCTL_DPHY_ERR_FLAG__ERR_CONT_LP1_1_FLAG_WIDTH 1U
+#define DSITX__MCTL_DPHY_ERR_FLAG__ERR_CONT_LP1_1_FLAG_WOCLR 0U
+#define DSITX__MCTL_DPHY_ERR_FLAG__ERR_CONT_LP1_1_FLAG_WOSET 0U
+#define DSITX__MCTL_DPHY_ERR_FLAG__ERR_CONT_LP1_2_FLAG_MASK 0x00800000U
+#define DSITX__MCTL_DPHY_ERR_FLAG__ERR_CONT_LP1_2_FLAG_SHIFT 23U
+#define DSITX__MCTL_DPHY_ERR_FLAG__ERR_CONT_LP1_2_FLAG_WIDTH 1U
+#define DSITX__MCTL_DPHY_ERR_FLAG__ERR_CONT_LP1_2_FLAG_WOCLR 0U
+#define DSITX__MCTL_DPHY_ERR_FLAG__ERR_CONT_LP1_2_FLAG_WOSET 0U
+#define DSITX__MCTL_DPHY_ERR_FLAG__ERR_CONT_LP1_3_FLAG_MASK 0x01000000U
+#define DSITX__MCTL_DPHY_ERR_FLAG__ERR_CONT_LP1_3_FLAG_SHIFT 24U
+#define DSITX__MCTL_DPHY_ERR_FLAG__ERR_CONT_LP1_3_FLAG_WIDTH 1U
+#define DSITX__MCTL_DPHY_ERR_FLAG__ERR_CONT_LP1_3_FLAG_WOCLR 0U
+#define DSITX__MCTL_DPHY_ERR_FLAG__ERR_CONT_LP1_3_FLAG_WOSET 0U
+#define DSITX__MCTL_DPHY_ERR_FLAG__ERR_CONT_LP1_4_FLAG_MASK 0x02000000U
+#define DSITX__MCTL_DPHY_ERR_FLAG__ERR_CONT_LP1_4_FLAG_SHIFT 25U
+#define DSITX__MCTL_DPHY_ERR_FLAG__ERR_CONT_LP1_4_FLAG_WIDTH 1U
+#define DSITX__MCTL_DPHY_ERR_FLAG__ERR_CONT_LP1_4_FLAG_WOCLR 0U
+#define DSITX__MCTL_DPHY_ERR_FLAG__ERR_CONT_LP1_4_FLAG_WOSET 0U
+#define DSITX__MCTL_DPHY_ERR_FLAG__RSVD_1_MASK 0xFC000000U
+#define DSITX__MCTL_DPHY_ERR_FLAG__RSVD_1_SHIFT 26U
+#define DSITX__MCTL_DPHY_ERR_FLAG__RSVD_1_WIDTH 6U
+
+#define DSITX__DPI_IRQ_EN_READ_MASK 0xFFFFFFFFU
+#define DSITX__DPI_IRQ_EN_WRITE_MASK 0xFFFFFFFFU
+#define DSITX__DPI_IRQ_EN__PIXEL_BUF_OVERFLOW_IRQ_EN_MASK 0x00000001U
+#define DSITX__DPI_IRQ_EN__PIXEL_BUF_OVERFLOW_IRQ_EN_SHIFT 0U
+#define DSITX__DPI_IRQ_EN__PIXEL_BUF_OVERFLOW_IRQ_EN_WIDTH 1U
+#define DSITX__DPI_IRQ_EN__PIXEL_BUF_OVERFLOW_IRQ_EN_WOCLR 0U
+#define DSITX__DPI_IRQ_EN__PIXEL_BUF_OVERFLOW_IRQ_EN_WOSET 0U
+#define DSITX__DPI_IRQ_EN__RSVD_0_MASK 0xFFFFFFFEU
+#define DSITX__DPI_IRQ_EN__RSVD_0_SHIFT 1U
+#define DSITX__DPI_IRQ_EN__RSVD_0_WIDTH 31U
+
+#define DSITX__DPI_IRQ_CLR_READ_MASK 0xFFFFFFFEU
+#define DSITX__DPI_IRQ_CLR_WRITE_MASK 0xFFFFFFFEU
+#define DSITX__DPI_IRQ_CLR__PIXEL_BUF_OVERFLOW_IRQ_CLR_MASK 0x00000001U
+#define DSITX__DPI_IRQ_CLR__PIXEL_BUF_OVERFLOW_IRQ_CLR_SHIFT 0U
+#define DSITX__DPI_IRQ_CLR__PIXEL_BUF_OVERFLOW_IRQ_CLR_WIDTH 1U
+#define DSITX__DPI_IRQ_CLR__PIXEL_BUF_OVERFLOW_IRQ_CLR_WOCLR 0U
+#define DSITX__DPI_IRQ_CLR__PIXEL_BUF_OVERFLOW_IRQ_CLR_WOSET 0U
+#define DSITX__DPI_IRQ_CLR__RSVD_0_MASK 0xFFFFFFFEU
+#define DSITX__DPI_IRQ_CLR__RSVD_0_SHIFT 1U
+#define DSITX__DPI_IRQ_CLR__RSVD_0_WIDTH 31U
+
+#define DSITX__DPI_IRQ_STS_READ_MASK 0xFFFFFFFFU
+#define DSITX__DPI_IRQ_STS_WRITE_MASK 0xFFFFFFFFU
+#define DSITX__DPI_IRQ_STS__PIXEL_BUF_OVERFLOW_STS_MASK 0x00000001U
+#define DSITX__DPI_IRQ_STS__PIXEL_BUF_OVERFLOW_STS_SHIFT 0U
+#define DSITX__DPI_IRQ_STS__PIXEL_BUF_OVERFLOW_STS_WIDTH 1U
+#define DSITX__DPI_IRQ_STS__PIXEL_BUF_OVERFLOW_STS_WOCLR 0U
+#define DSITX__DPI_IRQ_STS__PIXEL_BUF_OVERFLOW_STS_WOSET 0U
+#define DSITX__DPI_IRQ_STS__RSVD_0_MASK 0xFFFFFFFEU
+#define DSITX__DPI_IRQ_STS__RSVD_0_SHIFT 1U
+#define DSITX__DPI_IRQ_STS__RSVD_0_WIDTH 31U
+
+#define DSITX__DPI_CFG_READ_MASK 0xFFFFFFFFU
+#define DSITX__DPI_CFG_WRITE_MASK 0xFFFFFFFFU
+#define DSITX__DPI_CFG__DPI_CFG_FIFO_LEVEL_MASK 0x0000FFFFU
+#define DSITX__DPI_CFG__DPI_CFG_FIFO_LEVEL_SHIFT 0U
+#define DSITX__DPI_CFG__DPI_CFG_FIFO_LEVEL_WIDTH 16U
+#define DSITX__DPI_CFG__DPI_CFG_FIFODEPTH_MASK 0xFFFF0000U
+#define DSITX__DPI_CFG__DPI_CFG_FIFODEPTH_SHIFT 16U
+#define DSITX__DPI_CFG__DPI_CFG_FIFODEPTH_WIDTH 16U
+
+#define DSITX__TEST_GENERIC_READ_MASK 0xFFFFFFFFU
+#define DSITX__TEST_GENERIC_WRITE_MASK 0xFFFFFFFFU
+#define DSITX__TEST_GENERIC__CTRL_MASK 0x0000FFFFU
+#define DSITX__TEST_GENERIC__CTRL_SHIFT 0U
+#define DSITX__TEST_GENERIC__CTRL_WIDTH 16U
+#define DSITX__TEST_GENERIC__STATUS_MASK 0xFFFF0000U
+#define DSITX__TEST_GENERIC__STATUS_SHIFT 16U
+#define DSITX__TEST_GENERIC__STATUS_WIDTH 16U
+
+#define DSITX__ID_REG_READ_MASK 0xFFFFFFFFU
+#define DSITX__ID_REG_WRITE_MASK 0xFFFFFFFFU
+#define DSITX__ID_REG__REV_Y_MASK 0x0000000FU
+#define DSITX__ID_REG__REV_Y_SHIFT 0U
+#define DSITX__ID_REG__REV_Y_WIDTH 4U
+#define DSITX__ID_REG__REV_X_MASK 0x000000F0U
+#define DSITX__ID_REG__REV_X_SHIFT 4U
+#define DSITX__ID_REG__REV_X_WIDTH 4U
+#define DSITX__ID_REG__REV_HARDWARE_MASK 0x00000F00U
+#define DSITX__ID_REG__REV_HARDWARE_SHIFT 8U
+#define DSITX__ID_REG__REV_HARDWARE_WIDTH 4U
+#define DSITX__ID_REG__REV_PRODUCT_ID_MASK 0x000FF000U
+#define DSITX__ID_REG__REV_PRODUCT_ID_SHIFT 12U
+#define DSITX__ID_REG__REV_PRODUCT_ID_WIDTH 8U
+#define DSITX__ID_REG__REV_VENDOR_ID_MASK 0xFFF00000U
+#define DSITX__ID_REG__REV_VENDOR_ID_SHIFT 20U
+#define DSITX__ID_REG__REV_VENDOR_ID_WIDTH 12U
+
+#define DSITX__ASF_INT_STATUS_READ_MASK 0xFFFFFFFFU
+#define DSITX__ASF_INT_STATUS_WRITE_MASK 0xFFFFFFFFU
+#define DSITX__ASF_INT_STATUS_WOCLR_MASK 0x0000007FU
+#define DSITX__ASF_INT_STATUS__ASF_SRAM_CORR_ERR_MASK 0x00000001U
+#define DSITX__ASF_INT_STATUS__ASF_SRAM_CORR_ERR_SHIFT 0U
+#define DSITX__ASF_INT_STATUS__ASF_SRAM_CORR_ERR_WIDTH 1U
+#define DSITX__ASF_INT_STATUS__ASF_SRAM_CORR_ERR_WOCLR 1U
+#define DSITX__ASF_INT_STATUS__ASF_SRAM_CORR_ERR_WOSET 0U
+#define DSITX__ASF_INT_STATUS__ASF_SRAM_UNCORR_ERR_MASK 0x00000002U
+#define DSITX__ASF_INT_STATUS__ASF_SRAM_UNCORR_ERR_SHIFT 1U
+#define DSITX__ASF_INT_STATUS__ASF_SRAM_UNCORR_ERR_WIDTH 1U
+#define DSITX__ASF_INT_STATUS__ASF_SRAM_UNCORR_ERR_WOCLR 1U
+#define DSITX__ASF_INT_STATUS__ASF_SRAM_UNCORR_ERR_WOSET 0U
+#define DSITX__ASF_INT_STATUS__ASF_DAP_ERR_MASK 0x00000004U
+#define DSITX__ASF_INT_STATUS__ASF_DAP_ERR_SHIFT 2U
+#define DSITX__ASF_INT_STATUS__ASF_DAP_ERR_WIDTH 1U
+#define DSITX__ASF_INT_STATUS__ASF_DAP_ERR_WOCLR 1U
+#define DSITX__ASF_INT_STATUS__ASF_DAP_ERR_WOSET 0U
+#define DSITX__ASF_INT_STATUS__ASF_CSR_ERR_MASK 0x00000008U
+#define DSITX__ASF_INT_STATUS__ASF_CSR_ERR_SHIFT 3U
+#define DSITX__ASF_INT_STATUS__ASF_CSR_ERR_WIDTH 1U
+#define DSITX__ASF_INT_STATUS__ASF_CSR_ERR_WOCLR 1U
+#define DSITX__ASF_INT_STATUS__ASF_CSR_ERR_WOSET 0U
+#define DSITX__ASF_INT_STATUS__ASF_TRANS_TO_ERR_MASK 0x00000010U
+#define DSITX__ASF_INT_STATUS__ASF_TRANS_TO_ERR_SHIFT 4U
+#define DSITX__ASF_INT_STATUS__ASF_TRANS_TO_ERR_WIDTH 1U
+#define DSITX__ASF_INT_STATUS__ASF_TRANS_TO_ERR_WOCLR 1U
+#define DSITX__ASF_INT_STATUS__ASF_TRANS_TO_ERR_WOSET 0U
+#define DSITX__ASF_INT_STATUS__ASF_PROTOCOL_ERR_MASK 0x00000020U
+#define DSITX__ASF_INT_STATUS__ASF_PROTOCOL_ERR_SHIFT 5U
+#define DSITX__ASF_INT_STATUS__ASF_PROTOCOL_ERR_WIDTH 1U
+#define DSITX__ASF_INT_STATUS__ASF_PROTOCOL_ERR_WOCLR 1U
+#define DSITX__ASF_INT_STATUS__ASF_PROTOCOL_ERR_WOSET 0U
+#define DSITX__ASF_INT_STATUS__ASF_INTEGRITY_ERR_MASK 0x00000040U
+#define DSITX__ASF_INT_STATUS__ASF_INTEGRITY_ERR_SHIFT 6U
+#define DSITX__ASF_INT_STATUS__ASF_INTEGRITY_ERR_WIDTH 1U
+#define DSITX__ASF_INT_STATUS__ASF_INTEGRITY_ERR_WOCLR 1U
+#define DSITX__ASF_INT_STATUS__ASF_INTEGRITY_ERR_WOSET 0U
+#define DSITX__ASF_INT_STATUS__RESERVED_31_7_MASK 0xFFFFFF80U
+#define DSITX__ASF_INT_STATUS__RESERVED_31_7_SHIFT 7U
+#define DSITX__ASF_INT_STATUS__RESERVED_31_7_WIDTH 25U
+
+#define DSITX__ASF_INT_RAW_STATUS_READ_MASK 0xFFFFFFFFU
+#define DSITX__ASF_INT_RAW_STATUS_WRITE_MASK 0xFFFFFFFFU
+#define DSITX__ASF_INT_RAW_STATUS_WOCLR_MASK 0x0000007FU
+#define DSITX__ASF_INT_RAW_STATUS__ASF_SRAM_CORR_ERR_MASK 0x00000001U
+#define DSITX__ASF_INT_RAW_STATUS__ASF_SRAM_CORR_ERR_SHIFT 0U
+#define DSITX__ASF_INT_RAW_STATUS__ASF_SRAM_CORR_ERR_WIDTH 1U
+#define DSITX__ASF_INT_RAW_STATUS__ASF_SRAM_CORR_ERR_WOCLR 1U
+#define DSITX__ASF_INT_RAW_STATUS__ASF_SRAM_CORR_ERR_WOSET 0U
+#define DSITX__ASF_INT_RAW_STATUS__ASF_SRAM_UNCORR_ERR_MASK 0x00000002U
+#define DSITX__ASF_INT_RAW_STATUS__ASF_SRAM_UNCORR_ERR_SHIFT 1U
+#define DSITX__ASF_INT_RAW_STATUS__ASF_SRAM_UNCORR_ERR_WIDTH 1U
+#define DSITX__ASF_INT_RAW_STATUS__ASF_SRAM_UNCORR_ERR_WOCLR 1U
+#define DSITX__ASF_INT_RAW_STATUS__ASF_SRAM_UNCORR_ERR_WOSET 0U
+#define DSITX__ASF_INT_RAW_STATUS__ASF_DAP_ERR_MASK 0x00000004U
+#define DSITX__ASF_INT_RAW_STATUS__ASF_DAP_ERR_SHIFT 2U
+#define DSITX__ASF_INT_RAW_STATUS__ASF_DAP_ERR_WIDTH 1U
+#define DSITX__ASF_INT_RAW_STATUS__ASF_DAP_ERR_WOCLR 1U
+#define DSITX__ASF_INT_RAW_STATUS__ASF_DAP_ERR_WOSET 0U
+#define DSITX__ASF_INT_RAW_STATUS__ASF_CSR_ERR_MASK 0x00000008U
+#define DSITX__ASF_INT_RAW_STATUS__ASF_CSR_ERR_SHIFT 3U
+#define DSITX__ASF_INT_RAW_STATUS__ASF_CSR_ERR_WIDTH 1U
+#define DSITX__ASF_INT_RAW_STATUS__ASF_CSR_ERR_WOCLR 1U
+#define DSITX__ASF_INT_RAW_STATUS__ASF_CSR_ERR_WOSET 0U
+#define DSITX__ASF_INT_RAW_STATUS__ASF_TRANS_TO_ERR_MASK 0x00000010U
+#define DSITX__ASF_INT_RAW_STATUS__ASF_TRANS_TO_ERR_SHIFT 4U
+#define DSITX__ASF_INT_RAW_STATUS__ASF_TRANS_TO_ERR_WIDTH 1U
+#define DSITX__ASF_INT_RAW_STATUS__ASF_TRANS_TO_ERR_WOCLR 1U
+#define DSITX__ASF_INT_RAW_STATUS__ASF_TRANS_TO_ERR_WOSET 0U
+#define DSITX__ASF_INT_RAW_STATUS__ASF_PROTOCOL_ERR_MASK 0x00000020U
+#define DSITX__ASF_INT_RAW_STATUS__ASF_PROTOCOL_ERR_SHIFT 5U
+#define DSITX__ASF_INT_RAW_STATUS__ASF_PROTOCOL_ERR_WIDTH 1U
+#define DSITX__ASF_INT_RAW_STATUS__ASF_PROTOCOL_ERR_WOCLR 1U
+#define DSITX__ASF_INT_RAW_STATUS__ASF_PROTOCOL_ERR_WOSET 0U
+#define DSITX__ASF_INT_RAW_STATUS__ASF_INTEGRITY_ERR_MASK 0x00000040U
+#define DSITX__ASF_INT_RAW_STATUS__ASF_INTEGRITY_ERR_SHIFT 6U
+#define DSITX__ASF_INT_RAW_STATUS__ASF_INTEGRITY_ERR_WIDTH 1U
+#define DSITX__ASF_INT_RAW_STATUS__ASF_INTEGRITY_ERR_WOCLR 1U
+#define DSITX__ASF_INT_RAW_STATUS__ASF_INTEGRITY_ERR_WOSET 0U
+#define DSITX__ASF_INT_RAW_STATUS__RESERVED_31_7_MASK 0xFFFFFF80U
+#define DSITX__ASF_INT_RAW_STATUS__RESERVED_31_7_SHIFT 7U
+#define DSITX__ASF_INT_RAW_STATUS__RESERVED_31_7_WIDTH 25U
+
+#define DSITX__ASF_INT_MASK_READ_MASK 0xFFFFFFFFU
+#define DSITX__ASF_INT_MASK_WRITE_MASK 0xFFFFFFFFU
+#define DSITX__ASF_INT_MASK__ASF_SRAM_CORR_ERR_MASK_MASK 0x00000001U
+#define DSITX__ASF_INT_MASK__ASF_SRAM_CORR_ERR_MASK_SHIFT 0U
+#define DSITX__ASF_INT_MASK__ASF_SRAM_CORR_ERR_MASK_WIDTH 1U
+#define DSITX__ASF_INT_MASK__ASF_SRAM_CORR_ERR_MASK_WOCLR 0U
+#define DSITX__ASF_INT_MASK__ASF_SRAM_CORR_ERR_MASK_WOSET 0U
+#define DSITX__ASF_INT_MASK__ASF_SRAM_UNCORR_ERR_MASK_MASK 0x00000002U
+#define DSITX__ASF_INT_MASK__ASF_SRAM_UNCORR_ERR_MASK_SHIFT 1U
+#define DSITX__ASF_INT_MASK__ASF_SRAM_UNCORR_ERR_MASK_WIDTH 1U
+#define DSITX__ASF_INT_MASK__ASF_SRAM_UNCORR_ERR_MASK_WOCLR 0U
+#define DSITX__ASF_INT_MASK__ASF_SRAM_UNCORR_ERR_MASK_WOSET 0U
+#define DSITX__ASF_INT_MASK__ASF_DAP_ERR_MASK_MASK 0x00000004U
+#define DSITX__ASF_INT_MASK__ASF_DAP_ERR_MASK_SHIFT 2U
+#define DSITX__ASF_INT_MASK__ASF_DAP_ERR_MASK_WIDTH 1U
+#define DSITX__ASF_INT_MASK__ASF_DAP_ERR_MASK_WOCLR 0U
+#define DSITX__ASF_INT_MASK__ASF_DAP_ERR_MASK_WOSET 0U
+#define DSITX__ASF_INT_MASK__ASF_CSR_ERR_MASK_MASK 0x00000008U
+#define DSITX__ASF_INT_MASK__ASF_CSR_ERR_MASK_SHIFT 3U
+#define DSITX__ASF_INT_MASK__ASF_CSR_ERR_MASK_WIDTH 1U
+#define DSITX__ASF_INT_MASK__ASF_CSR_ERR_MASK_WOCLR 0U
+#define DSITX__ASF_INT_MASK__ASF_CSR_ERR_MASK_WOSET 0U
+#define DSITX__ASF_INT_MASK__ASF_TRANS_TO_ERR_MASK_MASK 0x00000010U
+#define DSITX__ASF_INT_MASK__ASF_TRANS_TO_ERR_MASK_SHIFT 4U
+#define DSITX__ASF_INT_MASK__ASF_TRANS_TO_ERR_MASK_WIDTH 1U
+#define DSITX__ASF_INT_MASK__ASF_TRANS_TO_ERR_MASK_WOCLR 0U
+#define DSITX__ASF_INT_MASK__ASF_TRANS_TO_ERR_MASK_WOSET 0U
+#define DSITX__ASF_INT_MASK__ASF_PROTOCOL_ERR_MASK_MASK 0x00000020U
+#define DSITX__ASF_INT_MASK__ASF_PROTOCOL_ERR_MASK_SHIFT 5U
+#define DSITX__ASF_INT_MASK__ASF_PROTOCOL_ERR_MASK_WIDTH 1U
+#define DSITX__ASF_INT_MASK__ASF_PROTOCOL_ERR_MASK_WOCLR 0U
+#define DSITX__ASF_INT_MASK__ASF_PROTOCOL_ERR_MASK_WOSET 0U
+#define DSITX__ASF_INT_MASK__ASF_INTEGRITY_ERR_MASK_MASK 0x00000040U
+#define DSITX__ASF_INT_MASK__ASF_INTEGRITY_ERR_MASK_SHIFT 6U
+#define DSITX__ASF_INT_MASK__ASF_INTEGRITY_ERR_MASK_WIDTH 1U
+#define DSITX__ASF_INT_MASK__ASF_INTEGRITY_ERR_MASK_WOCLR 0U
+#define DSITX__ASF_INT_MASK__ASF_INTEGRITY_ERR_MASK_WOSET 0U
+#define DSITX__ASF_INT_MASK__RESERVED_31_7_MASK 0xFFFFFF80U
+#define DSITX__ASF_INT_MASK__RESERVED_31_7_SHIFT 7U
+#define DSITX__ASF_INT_MASK__RESERVED_31_7_WIDTH 25U
+
+#define DSITX__ASF_INT_TEST_READ_MASK 0xFFFFFF80U
+#define DSITX__ASF_INT_TEST_WRITE_MASK 0xFFFFFF80U
+#define DSITX__ASF_INT_TEST__ASF_SRAM_CORR_ERR_TEST_MASK 0x00000001U
+#define DSITX__ASF_INT_TEST__ASF_SRAM_CORR_ERR_TEST_SHIFT 0U
+#define DSITX__ASF_INT_TEST__ASF_SRAM_CORR_ERR_TEST_WIDTH 1U
+#define DSITX__ASF_INT_TEST__ASF_SRAM_CORR_ERR_TEST_WOCLR 0U
+#define DSITX__ASF_INT_TEST__ASF_SRAM_CORR_ERR_TEST_WOSET 0U
+#define DSITX__ASF_INT_TEST__ASF_SRAM_UNCORR_ERR_TEST_MASK 0x00000002U
+#define DSITX__ASF_INT_TEST__ASF_SRAM_UNCORR_ERR_TEST_SHIFT 1U
+#define DSITX__ASF_INT_TEST__ASF_SRAM_UNCORR_ERR_TEST_WIDTH 1U
+#define DSITX__ASF_INT_TEST__ASF_SRAM_UNCORR_ERR_TEST_WOCLR 0U
+#define DSITX__ASF_INT_TEST__ASF_SRAM_UNCORR_ERR_TEST_WOSET 0U
+#define DSITX__ASF_INT_TEST__ASF_DAP_ERR_TEST_MASK 0x00000004U
+#define DSITX__ASF_INT_TEST__ASF_DAP_ERR_TEST_SHIFT 2U
+#define DSITX__ASF_INT_TEST__ASF_DAP_ERR_TEST_WIDTH 1U
+#define DSITX__ASF_INT_TEST__ASF_DAP_ERR_TEST_WOCLR 0U
+#define DSITX__ASF_INT_TEST__ASF_DAP_ERR_TEST_WOSET 0U
+#define DSITX__ASF_INT_TEST__ASF_CSR_ERR_TEST_MASK 0x00000008U
+#define DSITX__ASF_INT_TEST__ASF_CSR_ERR_TEST_SHIFT 3U
+#define DSITX__ASF_INT_TEST__ASF_CSR_ERR_TEST_WIDTH 1U
+#define DSITX__ASF_INT_TEST__ASF_CSR_ERR_TEST_WOCLR 0U
+#define DSITX__ASF_INT_TEST__ASF_CSR_ERR_TEST_WOSET 0U
+#define DSITX__ASF_INT_TEST__ASF_TRANS_TO_ERR_TEST_MASK 0x00000010U
+#define DSITX__ASF_INT_TEST__ASF_TRANS_TO_ERR_TEST_SHIFT 4U
+#define DSITX__ASF_INT_TEST__ASF_TRANS_TO_ERR_TEST_WIDTH 1U
+#define DSITX__ASF_INT_TEST__ASF_TRANS_TO_ERR_TEST_WOCLR 0U
+#define DSITX__ASF_INT_TEST__ASF_TRANS_TO_ERR_TEST_WOSET 0U
+#define DSITX__ASF_INT_TEST__ASF_PROTOCOL_ERR_TEST_MASK 0x00000020U
+#define DSITX__ASF_INT_TEST__ASF_PROTOCOL_ERR_TEST_SHIFT 5U
+#define DSITX__ASF_INT_TEST__ASF_PROTOCOL_ERR_TEST_WIDTH 1U
+#define DSITX__ASF_INT_TEST__ASF_PROTOCOL_ERR_TEST_WOCLR 0U
+#define DSITX__ASF_INT_TEST__ASF_PROTOCOL_ERR_TEST_WOSET 0U
+#define DSITX__ASF_INT_TEST__ASF_INTEGRITY_ERR_TEST_MASK 0x00000040U
+#define DSITX__ASF_INT_TEST__ASF_INTEGRITY_ERR_TEST_SHIFT 6U
+#define DSITX__ASF_INT_TEST__ASF_INTEGRITY_ERR_TEST_WIDTH 1U
+#define DSITX__ASF_INT_TEST__ASF_INTEGRITY_ERR_TEST_WOCLR 0U
+#define DSITX__ASF_INT_TEST__ASF_INTEGRITY_ERR_TEST_WOSET 0U
+#define DSITX__ASF_INT_TEST__RESERVED_31_7_MASK 0xFFFFFF80U
+#define DSITX__ASF_INT_TEST__RESERVED_31_7_SHIFT 7U
+#define DSITX__ASF_INT_TEST__RESERVED_31_7_WIDTH 25U
+
+#define DSITX__ASF_FATAL_NONFATAL_SELECT_READ_MASK 0xFFFFFFFFU
+#define DSITX__ASF_FATAL_NONFATAL_SELECT_WRITE_MASK 0xFFFFFFFFU
+#define DSITX__ASF_FATAL_NONFATAL_SELECT__ASF_SRAM_CORR_ERR_MASK 0x00000001U
+#define DSITX__ASF_FATAL_NONFATAL_SELECT__ASF_SRAM_CORR_ERR_SHIFT 0U
+#define DSITX__ASF_FATAL_NONFATAL_SELECT__ASF_SRAM_CORR_ERR_WIDTH 1U
+#define DSITX__ASF_FATAL_NONFATAL_SELECT__ASF_SRAM_CORR_ERR_WOCLR 0U
+#define DSITX__ASF_FATAL_NONFATAL_SELECT__ASF_SRAM_CORR_ERR_WOSET 0U
+#define DSITX__ASF_FATAL_NONFATAL_SELECT__ASF_SRAM_UNCORR_ERR_MASK 0x00000002U
+#define DSITX__ASF_FATAL_NONFATAL_SELECT__ASF_SRAM_UNCORR_ERR_SHIFT 1U
+#define DSITX__ASF_FATAL_NONFATAL_SELECT__ASF_SRAM_UNCORR_ERR_WIDTH 1U
+#define DSITX__ASF_FATAL_NONFATAL_SELECT__ASF_SRAM_UNCORR_ERR_WOCLR 0U
+#define DSITX__ASF_FATAL_NONFATAL_SELECT__ASF_SRAM_UNCORR_ERR_WOSET 0U
+#define DSITX__ASF_FATAL_NONFATAL_SELECT__ASF_DAP_ERR_MASK 0x00000004U
+#define DSITX__ASF_FATAL_NONFATAL_SELECT__ASF_DAP_ERR_SHIFT 2U
+#define DSITX__ASF_FATAL_NONFATAL_SELECT__ASF_DAP_ERR_WIDTH 1U
+#define DSITX__ASF_FATAL_NONFATAL_SELECT__ASF_DAP_ERR_WOCLR 0U
+#define DSITX__ASF_FATAL_NONFATAL_SELECT__ASF_DAP_ERR_WOSET 0U
+#define DSITX__ASF_FATAL_NONFATAL_SELECT__ASF_CSR_ERR_MASK 0x00000008U
+#define DSITX__ASF_FATAL_NONFATAL_SELECT__ASF_CSR_ERR_SHIFT 3U
+#define DSITX__ASF_FATAL_NONFATAL_SELECT__ASF_CSR_ERR_WIDTH 1U
+#define DSITX__ASF_FATAL_NONFATAL_SELECT__ASF_CSR_ERR_WOCLR 0U
+#define DSITX__ASF_FATAL_NONFATAL_SELECT__ASF_CSR_ERR_WOSET 0U
+#define DSITX__ASF_FATAL_NONFATAL_SELECT__ASF_TRANS_TO_ERR_MASK 0x00000010U
+#define DSITX__ASF_FATAL_NONFATAL_SELECT__ASF_TRANS_TO_ERR_SHIFT 4U
+#define DSITX__ASF_FATAL_NONFATAL_SELECT__ASF_TRANS_TO_ERR_WIDTH 1U
+#define DSITX__ASF_FATAL_NONFATAL_SELECT__ASF_TRANS_TO_ERR_WOCLR 0U
+#define DSITX__ASF_FATAL_NONFATAL_SELECT__ASF_TRANS_TO_ERR_WOSET 0U
+#define DSITX__ASF_FATAL_NONFATAL_SELECT__ASF_PROTOCOL_ERR_MASK 0x00000020U
+#define DSITX__ASF_FATAL_NONFATAL_SELECT__ASF_PROTOCOL_ERR_SHIFT 5U
+#define DSITX__ASF_FATAL_NONFATAL_SELECT__ASF_PROTOCOL_ERR_WIDTH 1U
+#define DSITX__ASF_FATAL_NONFATAL_SELECT__ASF_PROTOCOL_ERR_WOCLR 0U
+#define DSITX__ASF_FATAL_NONFATAL_SELECT__ASF_PROTOCOL_ERR_WOSET 0U
+#define DSITX__ASF_FATAL_NONFATAL_SELECT__ASF_INTEGRITY_ERR_MASK 0x00000040U
+#define DSITX__ASF_FATAL_NONFATAL_SELECT__ASF_INTEGRITY_ERR_SHIFT 6U
+#define DSITX__ASF_FATAL_NONFATAL_SELECT__ASF_INTEGRITY_ERR_WIDTH 1U
+#define DSITX__ASF_FATAL_NONFATAL_SELECT__ASF_INTEGRITY_ERR_WOCLR 0U
+#define DSITX__ASF_FATAL_NONFATAL_SELECT__ASF_INTEGRITY_ERR_WOSET 0U
+#define DSITX__ASF_FATAL_NONFATAL_SELECT__RESERVED_31_7_MASK 0xFFFFFF80U
+#define DSITX__ASF_FATAL_NONFATAL_SELECT__RESERVED_31_7_SHIFT 7U
+#define DSITX__ASF_FATAL_NONFATAL_SELECT__RESERVED_31_7_WIDTH 25U
+
+#define DSITX__ASF_SRAM_CORR_FAULT_STATUS_READ_MASK 0xFFFFFFFFU
+#define DSITX__ASF_SRAM_CORR_FAULT_STATUS_WRITE_MASK 0xFFFFFFFFU
+#define DSITX__ASF_SRAM_CORR_FAULT_STATUS__ASF_SRAM_CORR_FAULT_ADDR_MASK 0x00FFFFFFU
+#define DSITX__ASF_SRAM_CORR_FAULT_STATUS__ASF_SRAM_CORR_FAULT_ADDR_SHIFT 0U
+#define DSITX__ASF_SRAM_CORR_FAULT_STATUS__ASF_SRAM_CORR_FAULT_ADDR_WIDTH 24U
+#define DSITX__ASF_SRAM_CORR_FAULT_STATUS__ASF_SRAM_CORR_FAULT_INST_MASK 0xFF000000U
+#define DSITX__ASF_SRAM_CORR_FAULT_STATUS__ASF_SRAM_CORR_FAULT_INST_SHIFT 24U
+#define DSITX__ASF_SRAM_CORR_FAULT_STATUS__ASF_SRAM_CORR_FAULT_INST_WIDTH 8U
+
+#define DSITX__ASF_SRAM_UNCORR_FAULT_STATUS_READ_MASK 0xFFFFFFFFU
+#define DSITX__ASF_SRAM_UNCORR_FAULT_STATUS_WRITE_MASK 0xFFFFFFFFU
+#define DSITX__ASF_SRAM_UNCORR_FAULT_STATUS__ASF_SRAM_UNCORR_FAULT_ADDR_MASK 0x00FFFFFFU
+#define DSITX__ASF_SRAM_UNCORR_FAULT_STATUS__ASF_SRAM_UNCORR_FAULT_ADDR_SHIFT 0U
+#define DSITX__ASF_SRAM_UNCORR_FAULT_STATUS__ASF_SRAM_UNCORR_FAULT_ADDR_WIDTH 24U
+#define DSITX__ASF_SRAM_UNCORR_FAULT_STATUS__ASF_SRAM_UNCORR_FAULT_INST_MASK 0xFF000000U
+#define DSITX__ASF_SRAM_UNCORR_FAULT_STATUS__ASF_SRAM_UNCORR_FAULT_INST_SHIFT 24U
+#define DSITX__ASF_SRAM_UNCORR_FAULT_STATUS__ASF_SRAM_UNCORR_FAULT_INST_WIDTH 8U
+
+#define DSITX__ASF_SRAM_FAULT_STATS_READ_MASK 0xFFFFFFFFU
+#define DSITX__ASF_SRAM_FAULT_STATS_WRITE_MASK 0xFFFFFFFFU
+#define DSITX__ASF_SRAM_FAULT_STATS_WOCLR_MASK 0x0000FFFFU
+#define DSITX__ASF_SRAM_FAULT_STATS__ASF_SRAM_FAULT_CORR_STATS_MASK 0x0000FFFFU
+#define DSITX__ASF_SRAM_FAULT_STATS__ASF_SRAM_FAULT_CORR_STATS_SHIFT 0U
+#define DSITX__ASF_SRAM_FAULT_STATS__ASF_SRAM_FAULT_CORR_STATS_WIDTH 16U
+#define DSITX__ASF_SRAM_FAULT_STATS__RESERVED_31_16_MASK 0xFFFF0000U
+#define DSITX__ASF_SRAM_FAULT_STATS__RESERVED_31_16_SHIFT 16U
+#define DSITX__ASF_SRAM_FAULT_STATS__RESERVED_31_16_WIDTH 16U
+
+#define DSITX__ASF_TRANS_TO_CTRL_READ_MASK 0xFFFFFFFFU
+#define DSITX__ASF_TRANS_TO_CTRL_WRITE_MASK 0xFFFFFFFFU
+#define DSITX__ASF_TRANS_TO_CTRL__ASF_TRANS_TO_CTRL_MASK 0x0000FFFFU
+#define DSITX__ASF_TRANS_TO_CTRL__ASF_TRANS_TO_CTRL_SHIFT 0U
+#define DSITX__ASF_TRANS_TO_CTRL__ASF_TRANS_TO_CTRL_WIDTH 16U
+#define DSITX__ASF_TRANS_TO_CTRL__RSVD_0_MASK 0x7FFF0000U
+#define DSITX__ASF_TRANS_TO_CTRL__RSVD_0_SHIFT 16U
+#define DSITX__ASF_TRANS_TO_CTRL__RSVD_0_WIDTH 15U
+#define DSITX__ASF_TRANS_TO_CTRL__ASF_TRANS_TO_EN_MASK 0x80000000U
+#define DSITX__ASF_TRANS_TO_CTRL__ASF_TRANS_TO_EN_SHIFT 31U
+#define DSITX__ASF_TRANS_TO_CTRL__ASF_TRANS_TO_EN_WIDTH 1U
+#define DSITX__ASF_TRANS_TO_CTRL__ASF_TRANS_TO_EN_WOCLR 0U
+#define DSITX__ASF_TRANS_TO_CTRL__ASF_TRANS_TO_EN_WOSET 0U
+
+#define DSITX__ASF_TRANS_TO_FAULT_MASK_READ_MASK 0xFFFFFFFFU
+#define DSITX__ASF_TRANS_TO_FAULT_MASK_WRITE_MASK 0xFFFFFFFFU
+#define DSITX__ASF_TRANS_TO_FAULT_MASK__ASF_TRANS_TO_FAULT_0_MASK_MASK 0x00000001U
+#define DSITX__ASF_TRANS_TO_FAULT_MASK__ASF_TRANS_TO_FAULT_0_MASK_SHIFT 0U
+#define DSITX__ASF_TRANS_TO_FAULT_MASK__ASF_TRANS_TO_FAULT_0_MASK_WIDTH 1U
+#define DSITX__ASF_TRANS_TO_FAULT_MASK__ASF_TRANS_TO_FAULT_0_MASK_WOCLR 0U
+#define DSITX__ASF_TRANS_TO_FAULT_MASK__ASF_TRANS_TO_FAULT_0_MASK_WOSET 0U
+#define DSITX__ASF_TRANS_TO_FAULT_MASK__ASF_TRANS_TO_FAULT_1_MASK_MASK 0x00000002U
+#define DSITX__ASF_TRANS_TO_FAULT_MASK__ASF_TRANS_TO_FAULT_1_MASK_SHIFT 1U
+#define DSITX__ASF_TRANS_TO_FAULT_MASK__ASF_TRANS_TO_FAULT_1_MASK_WIDTH 1U
+#define DSITX__ASF_TRANS_TO_FAULT_MASK__ASF_TRANS_TO_FAULT_1_MASK_WOCLR 0U
+#define DSITX__ASF_TRANS_TO_FAULT_MASK__ASF_TRANS_TO_FAULT_1_MASK_WOSET 0U
+#define DSITX__ASF_TRANS_TO_FAULT_MASK__ASF_TRANS_TO_FAULT_2_MASK_MASK 0x00000004U
+#define DSITX__ASF_TRANS_TO_FAULT_MASK__ASF_TRANS_TO_FAULT_2_MASK_SHIFT 2U
+#define DSITX__ASF_TRANS_TO_FAULT_MASK__ASF_TRANS_TO_FAULT_2_MASK_WIDTH 1U
+#define DSITX__ASF_TRANS_TO_FAULT_MASK__ASF_TRANS_TO_FAULT_2_MASK_WOCLR 0U
+#define DSITX__ASF_TRANS_TO_FAULT_MASK__ASF_TRANS_TO_FAULT_2_MASK_WOSET 0U
+#define DSITX__ASF_TRANS_TO_FAULT_MASK__ASF_TRANS_TO_FAULT_3_MASK_MASK 0x00000008U
+#define DSITX__ASF_TRANS_TO_FAULT_MASK__ASF_TRANS_TO_FAULT_3_MASK_SHIFT 3U
+#define DSITX__ASF_TRANS_TO_FAULT_MASK__ASF_TRANS_TO_FAULT_3_MASK_WIDTH 1U
+#define DSITX__ASF_TRANS_TO_FAULT_MASK__ASF_TRANS_TO_FAULT_3_MASK_WOCLR 0U
+#define DSITX__ASF_TRANS_TO_FAULT_MASK__ASF_TRANS_TO_FAULT_3_MASK_WOSET 0U
+#define DSITX__ASF_TRANS_TO_FAULT_MASK__RSVD_0_MASK 0xFFFFFFF0U
+#define DSITX__ASF_TRANS_TO_FAULT_MASK__RSVD_0_SHIFT 4U
+#define DSITX__ASF_TRANS_TO_FAULT_MASK__RSVD_0_WIDTH 28U
+
+#define DSITX__ASF_TRANS_TO_FAULT_STATUS_READ_MASK 0xFFFFFFFFU
+#define DSITX__ASF_TRANS_TO_FAULT_STATUS_WRITE_MASK 0xFFFFFFFFU
+#define DSITX__ASF_TRANS_TO_FAULT_STATUS_WOCLR_MASK 0x0000000FU
+#define DSITX__ASF_TRANS_TO_FAULT_STATUS__ASF_TRANS_TO_FAULT_0_STATUS_MASK 0x00000001U
+#define DSITX__ASF_TRANS_TO_FAULT_STATUS__ASF_TRANS_TO_FAULT_0_STATUS_SHIFT 0U
+#define DSITX__ASF_TRANS_TO_FAULT_STATUS__ASF_TRANS_TO_FAULT_0_STATUS_WIDTH 1U
+#define DSITX__ASF_TRANS_TO_FAULT_STATUS__ASF_TRANS_TO_FAULT_0_STATUS_WOCLR 1U
+#define DSITX__ASF_TRANS_TO_FAULT_STATUS__ASF_TRANS_TO_FAULT_0_STATUS_WOSET 0U
+#define DSITX__ASF_TRANS_TO_FAULT_STATUS__ASF_TRANS_TO_FAULT_1_STATUS_MASK 0x00000002U
+#define DSITX__ASF_TRANS_TO_FAULT_STATUS__ASF_TRANS_TO_FAULT_1_STATUS_SHIFT 1U
+#define DSITX__ASF_TRANS_TO_FAULT_STATUS__ASF_TRANS_TO_FAULT_1_STATUS_WIDTH 1U
+#define DSITX__ASF_TRANS_TO_FAULT_STATUS__ASF_TRANS_TO_FAULT_1_STATUS_WOCLR 1U
+#define DSITX__ASF_TRANS_TO_FAULT_STATUS__ASF_TRANS_TO_FAULT_1_STATUS_WOSET 0U
+#define DSITX__ASF_TRANS_TO_FAULT_STATUS__ASF_TRANS_TO_FAULT_2_STATUS_MASK 0x00000004U
+#define DSITX__ASF_TRANS_TO_FAULT_STATUS__ASF_TRANS_TO_FAULT_2_STATUS_SHIFT 2U
+#define DSITX__ASF_TRANS_TO_FAULT_STATUS__ASF_TRANS_TO_FAULT_2_STATUS_WIDTH 1U
+#define DSITX__ASF_TRANS_TO_FAULT_STATUS__ASF_TRANS_TO_FAULT_2_STATUS_WOCLR 1U
+#define DSITX__ASF_TRANS_TO_FAULT_STATUS__ASF_TRANS_TO_FAULT_2_STATUS_WOSET 0U
+#define DSITX__ASF_TRANS_TO_FAULT_STATUS__ASF_TRANS_TO_FAULT_3_STATUS_MASK 0x00000008U
+#define DSITX__ASF_TRANS_TO_FAULT_STATUS__ASF_TRANS_TO_FAULT_3_STATUS_SHIFT 3U
+#define DSITX__ASF_TRANS_TO_FAULT_STATUS__ASF_TRANS_TO_FAULT_3_STATUS_WIDTH 1U
+#define DSITX__ASF_TRANS_TO_FAULT_STATUS__ASF_TRANS_TO_FAULT_3_STATUS_WOCLR 1U
+#define DSITX__ASF_TRANS_TO_FAULT_STATUS__ASF_TRANS_TO_FAULT_3_STATUS_WOSET 0U
+#define DSITX__ASF_TRANS_TO_FAULT_STATUS__RSVD_0_MASK 0xFFFFFFF0U
+#define DSITX__ASF_TRANS_TO_FAULT_STATUS__RSVD_0_SHIFT 4U
+#define DSITX__ASF_TRANS_TO_FAULT_STATUS__RSVD_0_WIDTH 28U
+
+#define DSITX__ASF_PROTOCOL_FAULT_MASK_READ_MASK 0xFFFFFFFFU
+#define DSITX__ASF_PROTOCOL_FAULT_MASK_WRITE_MASK 0xFFFFFFFFU
+#define DSITX__ASF_PROTOCOL_FAULT_MASK__ASF_PROTOCOL_FAULT_0_MASK_MASK 0x00000001U
+#define DSITX__ASF_PROTOCOL_FAULT_MASK__ASF_PROTOCOL_FAULT_0_MASK_SHIFT 0U
+#define DSITX__ASF_PROTOCOL_FAULT_MASK__ASF_PROTOCOL_FAULT_0_MASK_WIDTH 1U
+#define DSITX__ASF_PROTOCOL_FAULT_MASK__ASF_PROTOCOL_FAULT_0_MASK_WOCLR 0U
+#define DSITX__ASF_PROTOCOL_FAULT_MASK__ASF_PROTOCOL_FAULT_0_MASK_WOSET 0U
+#define DSITX__ASF_PROTOCOL_FAULT_MASK__ASF_PROTOCOL_FAULT_1_MASK_MASK 0x00000002U
+#define DSITX__ASF_PROTOCOL_FAULT_MASK__ASF_PROTOCOL_FAULT_1_MASK_SHIFT 1U
+#define DSITX__ASF_PROTOCOL_FAULT_MASK__ASF_PROTOCOL_FAULT_1_MASK_WIDTH 1U
+#define DSITX__ASF_PROTOCOL_FAULT_MASK__ASF_PROTOCOL_FAULT_1_MASK_WOCLR 0U
+#define DSITX__ASF_PROTOCOL_FAULT_MASK__ASF_PROTOCOL_FAULT_1_MASK_WOSET 0U
+#define DSITX__ASF_PROTOCOL_FAULT_MASK__ASF_PROTOCOL_FAULT_2_MASK_MASK 0x00000004U
+#define DSITX__ASF_PROTOCOL_FAULT_MASK__ASF_PROTOCOL_FAULT_2_MASK_SHIFT 2U
+#define DSITX__ASF_PROTOCOL_FAULT_MASK__ASF_PROTOCOL_FAULT_2_MASK_WIDTH 1U
+#define DSITX__ASF_PROTOCOL_FAULT_MASK__ASF_PROTOCOL_FAULT_2_MASK_WOCLR 0U
+#define DSITX__ASF_PROTOCOL_FAULT_MASK__ASF_PROTOCOL_FAULT_2_MASK_WOSET 0U
+#define DSITX__ASF_PROTOCOL_FAULT_MASK__ASF_PROTOCOL_FAULT_3_MASK_MASK 0x00000008U
+#define DSITX__ASF_PROTOCOL_FAULT_MASK__ASF_PROTOCOL_FAULT_3_MASK_SHIFT 3U
+#define DSITX__ASF_PROTOCOL_FAULT_MASK__ASF_PROTOCOL_FAULT_3_MASK_WIDTH 1U
+#define DSITX__ASF_PROTOCOL_FAULT_MASK__ASF_PROTOCOL_FAULT_3_MASK_WOCLR 0U
+#define DSITX__ASF_PROTOCOL_FAULT_MASK__ASF_PROTOCOL_FAULT_3_MASK_WOSET 0U
+#define DSITX__ASF_PROTOCOL_FAULT_MASK__RSVD_0_MASK 0xFFFFFFF0U
+#define DSITX__ASF_PROTOCOL_FAULT_MASK__RSVD_0_SHIFT 4U
+#define DSITX__ASF_PROTOCOL_FAULT_MASK__RSVD_0_WIDTH 28U
+
+#define DSITX__ASF_PROTOCOL_FAULT_STATUS_READ_MASK 0xFFFFFFFFU
+#define DSITX__ASF_PROTOCOL_FAULT_STATUS_WRITE_MASK 0xFFFFFFFFU
+#define DSITX__ASF_PROTOCOL_FAULT_STATUS_WOCLR_MASK 0x0000000FU
+#define DSITX__ASF_PROTOCOL_FAULT_STATUS__ASF_PROTOCOL_FAULT_0_STATUS_MASK 0x00000001U
+#define DSITX__ASF_PROTOCOL_FAULT_STATUS__ASF_PROTOCOL_FAULT_0_STATUS_SHIFT 0U
+#define DSITX__ASF_PROTOCOL_FAULT_STATUS__ASF_PROTOCOL_FAULT_0_STATUS_WIDTH 1U
+#define DSITX__ASF_PROTOCOL_FAULT_STATUS__ASF_PROTOCOL_FAULT_0_STATUS_WOCLR 1U
+#define DSITX__ASF_PROTOCOL_FAULT_STATUS__ASF_PROTOCOL_FAULT_0_STATUS_WOSET 0U
+#define DSITX__ASF_PROTOCOL_FAULT_STATUS__ASF_PROTOCOL_FAULT_1_STATUS_MASK 0x00000002U
+#define DSITX__ASF_PROTOCOL_FAULT_STATUS__ASF_PROTOCOL_FAULT_1_STATUS_SHIFT 1U
+#define DSITX__ASF_PROTOCOL_FAULT_STATUS__ASF_PROTOCOL_FAULT_1_STATUS_WIDTH 1U
+#define DSITX__ASF_PROTOCOL_FAULT_STATUS__ASF_PROTOCOL_FAULT_1_STATUS_WOCLR 1U
+#define DSITX__ASF_PROTOCOL_FAULT_STATUS__ASF_PROTOCOL_FAULT_1_STATUS_WOSET 0U
+#define DSITX__ASF_PROTOCOL_FAULT_STATUS__ASF_PROTOCOL_FAULT_2_STATUS_MASK 0x00000004U
+#define DSITX__ASF_PROTOCOL_FAULT_STATUS__ASF_PROTOCOL_FAULT_2_STATUS_SHIFT 2U
+#define DSITX__ASF_PROTOCOL_FAULT_STATUS__ASF_PROTOCOL_FAULT_2_STATUS_WIDTH 1U
+#define DSITX__ASF_PROTOCOL_FAULT_STATUS__ASF_PROTOCOL_FAULT_2_STATUS_WOCLR 1U
+#define DSITX__ASF_PROTOCOL_FAULT_STATUS__ASF_PROTOCOL_FAULT_2_STATUS_WOSET 0U
+#define DSITX__ASF_PROTOCOL_FAULT_STATUS__ASF_PROTOCOL_FAULT_3_STATUS_MASK 0x00000008U
+#define DSITX__ASF_PROTOCOL_FAULT_STATUS__ASF_PROTOCOL_FAULT_3_STATUS_SHIFT 3U
+#define DSITX__ASF_PROTOCOL_FAULT_STATUS__ASF_PROTOCOL_FAULT_3_STATUS_WIDTH 1U
+#define DSITX__ASF_PROTOCOL_FAULT_STATUS__ASF_PROTOCOL_FAULT_3_STATUS_WOCLR 1U
+#define DSITX__ASF_PROTOCOL_FAULT_STATUS__ASF_PROTOCOL_FAULT_3_STATUS_WOSET 0U
+#define DSITX__ASF_PROTOCOL_FAULT_STATUS__RSVD_0_MASK 0xFFFFFFF0U
+#define DSITX__ASF_PROTOCOL_FAULT_STATUS__RSVD_0_SHIFT 4U
+#define DSITX__ASF_PROTOCOL_FAULT_STATUS__RSVD_0_WIDTH 28U
+
+#endif /* REG_DSITX_REGS_MACROS_H_ */
+
+/* parasoft-end-suppress MISRA2012-RULE-5_4_b_c99-2 "C99 - similar names" */
+/* parasoft-end-suppress MISRA2012-RULE-5_4_b_c90-2 "C90 - similar names" */
+/* parasoft-end-suppress MISRA2012-RULE-1_1_b_c99-2 "C99 - limits" */
+/* parasoft-end-suppress MISRA2012-RULE-1_1_b_c90-2 "C90 - limits" */
+
diff --git a/packages/ti/drv/dss/src/csl/dsi/include/dsitx_structs_if.h b/packages/ti/drv/dss/src/csl/dsi/include/dsitx_structs_if.h
--- /dev/null
@@ -0,0 +1,633 @@
+/* parasoft suppress item MISRA2012-DIR-4_8 "Consider hiding implementation of structure" */
+/**********************************************************************
+ * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ **********************************************************************
+ * WARNING: This file is auto-generated using api-generator utility.
+ * api-generator: 13.00.31660be
+ * Do not edit it manually.
+ **********************************************************************
+ * Cadence Core Driver for MIPI DSITX Host Controller
+ **********************************************************************/
+#ifndef DSITX_STRUCTS_IF_H
+#define DSITX_STRUCTS_IF_H
+
+#include "dsitx_if.h"
+
+/** @defgroup DataStructure Dynamic Data Structures
+ * This section defines the data structures used by the driver to provide
+ * hardware information, modification and dynamic operation of the driver.
+ * These data structures are defined in the header file of the core driver
+ * and utilized by the API.
+ * @{
+ */
+
+/**********************************************************************
+ * Structures and unions
+ **********************************************************************/
+/** DPHY Power and Reset Control configuration. */
+struct DSITX_DphyPwrRstConfig_s
+{
+ /** Drives dphy_c_rstb output. */
+ bool dphyCRstb;
+ /** Drives dphy_d_rstb output. */
+ uint8_t dphyDRstb;
+ /** Drives dphy_pll_pdn output. */
+ bool dphyPllPdn;
+ /** Drives dphy_cmn_pdn output. */
+ bool dphyCmnPdn;
+ /** Drives dphy_c_pdn output. */
+ bool dphyCPdn;
+ /** Drives dphy_d_pdn output. */
+ uint8_t dphyDPdn;
+ /** Drives dphy_pll_pso output. */
+ bool dphyPllPso;
+ /** Drives dphy_cmn_pso output. */
+ bool dphyCmnPso;
+};
+
+/** DSC Event Status structure. */
+struct DSITX_DscEventStatus_s
+{
+ /** DSC PPS Command Sent */
+ bool dscPpsDone;
+ /** DSC Execute Command Sent */
+ bool dscExecDone;
+};
+
+/** DPHY timings configuration structure. */
+struct DSITX_DphyConfig_s
+{
+ /**
+ * DPHY's Clock division ratio. The clock division means that
+ * the check counter is incremented every 2^clkDivisionRatio clock cycles and
+ * not that a clock divider is built internally! The value of the division
+ * is limited to 2^11. clkDivisionRatio must not exceed 11.
+ */
+ uint8_t clkDivisionRatio;
+ /** DPHY's High Speed TX timeout detection value. */
+ uint32_t hstxTimeout;
+ /** DPHY's Low Power RX timeout detection value. */
+ uint32_t lprxTimeout;
+ /**
+ * For clock lane - specify what the duration to
+ * leave ULP mode is in system clock cycles. This value is multiplied by
+ * 1000 in DSITX Host.
+ */
+ uint16_t clkLaneUlpTimeout;
+ /**
+ * For data lane(s) - specify what the duration to
+ * leave ULP mode is in system clock cycles. This value is multiplied by
+ * 1000 in DSITX Host.
+ */
+ uint16_t dataLaneUlpTimeout;
+};
+
+/** Structure containing main data path configuration. */
+struct DSITX_DataPathConfig_s
+{
+ /** Enables or disables link. */
+ bool linkEnabled;
+ /** Operation mode of selected interface. */
+ DSITX_InterfaceMode interfaceMode;
+ /** Determines which video interface is active. */
+ DSITX_VideoInterfaceSelection videoIfSelect;
+ /** Enables Video Stream Generator or indicates if it's enabled or disabled. */
+ bool videoStreamGenEnabled;
+ /**
+ * Test Video Generator is (or should be) enabled. This is not start signal.
+ * Should not be set if Interface 1 is enabled and operating in Video Mode.
+ */
+ bool tvgEnabled;
+ /**
+ * Enables tearing effect on Interface 1.
+ * Note: Enabling TE on all SDI interfaces simultaneously is not supported.
+ */
+ bool if1TeEnabled;
+ /** Enables tearing effect from register. */
+ bool regTeEnabled;
+ /** Enables read operations. */
+ bool readOpEnabled;
+ /** Enables BTA packets. */
+ bool btaEnabled;
+ /** Display generates ECC on its response packets. */
+ bool dispGenEcc;
+ /** Display generates checksum on its response packets. */
+ bool dispGenChecksum;
+ /** Generates EOT packet after a transfer in HS Mode. */
+ bool hostEotGen;
+ /** Display adds an EOT packet to its LPDT transfers. */
+ bool dispEotGen;
+ /**
+ * Enables TE Polling feature following MIPI recommendations
+ * (Polling by software).
+ */
+ bool teHwPolling;
+ /**
+ * Enables TE Polling feature following internal solution.
+ * (Currently not supported by DSITX3 Host)
+ */
+ bool teMipiPolling;
+};
+
+/** Main control settings for physical lanes. */
+struct DSITX_PhyConfig_s
+{
+ /** Enable second lane. */
+ bool lane2Enabled;
+ /** Enable third lane. */
+ bool lane3Enabled;
+ /** Enable fourth lane. */
+ bool lane4Enabled;
+ /**
+ * Clock lane should remain in High Speed mode.
+ * No return in STOP state.
+ */
+ bool laneClkContinous;
+ /**
+ * Specifies that clock lane can be switched in
+ * Ultra Low Power mode (on demand).
+ */
+ bool laneClkUlpMode;
+ /** Data lane 1 can be switched to Ultra Low Power mode. */
+ bool laneUlpMode[DSITX_MAX_LANE_NUMBER];
+ /**
+ * Delay to respect between two High Speed bursts (in clock cycles).
+ * Value of 0 is forbidden.
+ */
+ uint8_t waitBurstTime;
+};
+
+/** Main control settings for 3d video. */
+struct DSITX_Video3dConfig_s
+{
+ /** Video 3D mode for VSYNC Control Parameter */
+ DSITX_Video3dMode vidSync3dMode;
+ /** Video 3D format for VSYNC Control Parameter1 */
+ DSITX_Video3dFormat vidSync3dFormat;
+ /** A second VSYNC enabled between L and R images */
+ bool vidVsync3dSecondEnable;
+ /** Starting Frame. */
+ DSITX_Video3dFirstSide vidVsync3dLr;
+ /** Enable 3D. */
+ bool vidVsync3dEnable;
+};
+
+/** Structure containing Command Mode configuration. */
+struct DSITX_CommandModeSettings_s
+{
+ /** Send Command from interface 1 in Low Power Mode if possible. */
+ bool sendFromInt1InLp;
+ /** Send Command from interface 3 in Low Power Mode if possible. */
+ bool sendFromInt3InLp;
+ /** Virtual Channel ID of request from interface 1. */
+ uint8_t vcIdIf1;
+ /** Virtual Channel ID of request from interface 3. */
+ uint8_t vcIdIf3;
+ /**
+ * Length of TE window.
+ * Bits 9:0 determines timeout value while bits 11:10 determines multiplier:
+ * 00b - 256x, 01b - 512x, 10b - 1024x, 11b - 2048x.
+ */
+ uint16_t teTimeout;
+ /**
+ * Value to use to fill packet during data underrun or to complete
+ * unterminated packet. Referred also as padding value.
+ */
+ uint8_t fillValue;
+ /** Specifies interface with higher priority in fixed mode. */
+ DSITX_CmdArbitrationPriority arbPriority;
+ /** Arbitration mode. */
+ DSITX_CmdArbitrationMode arbMode;
+};
+
+/** Image and Blanking Packet size configuration structure. */
+struct DSITX_VideoSize_s
+{
+ /**
+ * Duration of the VSYNC pulse (in lines).
+ * This value should be at least one and greater or equal to two when in pulse mode.
+ */
+ uint8_t vsa;
+ /** Length of the Vertical Back Porch (in lines). */
+ uint8_t vbp;
+ /**
+ * Length of the Vertical Front Porch (in lines).
+ * Needs to be greater than 0.
+ */
+ uint8_t vfp;
+ /** Vertical length of active area (in line). Must be greater than 0. */
+ uint16_t vact;
+ /**
+ * Duration of HSYNC pulse (in bytes).
+ * Need to be at least set to one if pulse mode is enabled.
+ */
+ uint16_t hsa;
+ /**
+ * Length of the Horizontal Back Porch (in bytes).
+ * If 0, HBP packet is sent with 0 payload.
+ */
+ uint16_t hbp;
+ /**
+ * Length of the Horizontal Front Porch.
+ * If 0, no HFP packet is sent.
+ */
+ uint16_t hfp;
+ /** Size of the RGB packet (in bytes). */
+ uint16_t rgb;
+ /** Packet length on end of line if burst mode (in bytes). */
+ uint16_t blkEolPacket;
+ /**
+ * Packet length in blanking line if line has to be filled with a packet
+ * and sync is an event (in bytes).
+ */
+ uint16_t blkLineEventPacket;
+ /**
+ * Packet length in blanking line if line has to be filled with a packet
+ * and sync is a pulse (in bytes).
+ */
+ uint16_t blkLinePulsePacket;
+};
+
+/** Color struct. */
+struct DSITX_Color_s
+{
+ /**
+ * Red component of the fill color.
+ * Maximum value for this field depends on chosen video pixel mode.
+ */
+ uint16_t r;
+ /**
+ * Green component of the fill color.
+ * Maximum value for this field depends on chosen video pixel mode.
+ */
+ uint16_t g;
+ /**
+ * Blue component of the fill color.
+ * Maximum value for this field depends on chosen video pixel mode.
+ */
+ uint16_t b;
+};
+
+/** Error color struct. */
+struct DSITX_ErrorColor_s
+{
+ /**
+ * Red component of the fill color.
+ * Maximum value for this field depends on chosen video pixel mode.
+ */
+ uint16_t r;
+ /**
+ * Green component of the fill color.
+ * Maximum value for this field depends on chosen video pixel mode.
+ */
+ uint16_t g;
+ /**
+ * Blue component of the fill color.
+ * Maximum value for this field depends on chosen video pixel mode.
+ */
+ uint16_t b;
+ /**
+ * Byte used do pad data (when system does not know exactly where it is).
+ * Maximum value for this field depends on chosen video pixel mode.
+ */
+ uint16_t padValue;
+};
+
+/** Video Command Arbiter settings. */
+struct DSITX_VcaConfig_s
+{
+ /** Size of biggest burst packet (packet that fits after RGB in burst mode). */
+ uint16_t maxBurstLimit;
+ /**
+ * Determines if after an active line, the system can switch in
+ * Low Power mode (true) or should complete the line with NULL packet (false).
+ */
+ bool burstLp;
+ /** Exact maximum size of the burst packet (packet that fits after RGB in burst mode). */
+ uint16_t exactBurstLimit;
+ /** Maximum size of the line packet (packet that fits in blanking line). */
+ uint16_t maxLineLimit;
+};
+
+/** Video Mode Settings. */
+struct DSITX_VideoModeSettings_s
+{
+ /**
+ * Video entry point.
+ * (Only DSITX_VID_START_MODE_START_ON_VSYNC is supported)
+ */
+ DSITX_VideoStartMode startMode;
+ /**
+ * Video stop point.
+ * (Only stop DSITX_VID_STOP_MODE_STOP_JUST_BEFORE_VSYNC is supported)
+ */
+ DSITX_VideoStopMode stopMode;
+ /**
+ * Specifies the Virtual Channel Identifier of the video packets.
+ * First field in interlaced mode.
+ */
+ uint8_t vidId;
+ /**
+ * Specifies the Virtual Channel Identifier of the
+ * second field of interlaced video packet.
+ */
+ uint8_t vidIdSdfd;
+ /** Specifies the datatype of RGB packets. */
+ DSITX_VideoDataType header;
+ /**
+ * Video Pixel Mode.
+ * (YCbCr modes are not supported by DSITX3 Host)
+ */
+ DSITX_VideoPixelMode vidPixelMode;
+ /** Signals if system works in burst mode or not. */
+ bool burstMode;
+ /** Synchro are pulse (1) or event (0) during active area. */
+ bool syncPulseActive;
+ /**
+ * Synchro are pulse (1) or event (0) all the time.
+ * To be set only when syncPulseActive is set.
+ */
+ bool syncPulseHorizontal;
+ /**
+ * Behavior during blanking time.
+ * 1xb - LP, 01b - Blanking packet, 00b - NULL packet
+ */
+ DSITX_VideoBlankingMode blkLineMode;
+ /**
+ * Behavior during end of line in burst mode.
+ * 1xb - LP, 01b - Blanking packet, 00b - NULL packet
+ */
+ DSITX_VideoBlankingMode blkEolMode;
+ /** Specifies recovery mode. */
+ DSITX_VideoRecoveryMode recoveryMode;
+ /** Enables interlaced video mode. */
+ bool interlancedVideoModeEnabled;
+ /**
+ * When interlaced mode is enabled this allows to choose which field
+ * to start the video stream.
+ */
+ uint8_t fieldSwitch;
+ /** Specifies the duration of the BLLP period (in clock cycles). */
+ uint16_t blkEolDuration;
+ /** Error color. */
+ DSITX_ErrorColor errColor;
+ /**
+ * Estimated time to perform transition from Low Power Mode to
+ * High Speed Mode on DPHY (in clock cycles).
+ * This time must be shorter than line duration.
+ */
+ uint16_t regWakeupTime;
+ /** Duration of the blanking area for VSA/VBP/VFP (in clock cycles). */
+ uint32_t regLineDuration;
+ /** Ignore miss vsync. */
+ bool ignoreMissVsync;
+};
+
+/** Test Video Generator configuration. */
+struct DSITX_TestVideoModeConfig_s
+{
+ /** Determines if TVG was enabled or disabled. */
+ bool enabled;
+ /** Size of the stripe (in pixels) - defined by 2^stripeSize. */
+ DSITX_TvgStripeSize stripeSize;
+ /** TVG display mode. */
+ DSITX_TvgDisplayMode displayMode;
+ /** TVG stop mode. */
+ DSITX_TvgStopMode stopMode;
+ /**
+ * Number of lines per frame.
+ * Must be equal to VACT size set for VSG (see VideoModeSettings).
+ */
+ uint16_t linesPerFrame;
+ /**
+ * Number of bytes per line.
+ * Must be equal to RGB size set for VSG (see VideoModeSettings).
+ */
+ uint16_t bytesPerLine;
+ /** Color 1 of Dummy frame. */
+ DSITX_Color color1;
+ /** Color 2 of Dummy frame. */
+ DSITX_Color color2;
+};
+
+/**
+ * IP configuration values. This structure is read only and it is filled by
+ * DSITX Core Driver while calling DSITX_GetIpConf function.
+*/
+struct DSITX_IpConf_s
+{
+ /** Depth of the RX FIFO. */
+ uint8_t rxFifoDepth;
+ /**
+ * Number of Data Lanes. Not fully implemented for two lanes.
+ * 0 means one data line; 1 means two data lanes;
+ * 2 means three data lanes; 3 means four data lanes.
+ */
+ uint8_t maxLaneNumber;
+ /** Number of the SDI Interfaces. */
+ uint8_t sdiIfNumber;
+ /** Datapath bus size in bits. */
+ uint8_t datapathSize;
+ /** SDI data bus size in bits. */
+ uint8_t sdiIfDataBusSize;
+ /** Direct Command FIFO depth. Each item has width equal to datapathSize. */
+ uint16_t directCmdFifoDepth;
+ /** FIFO depth in VRS block. Each item has 50-bit width. */
+ uint8_t vrsBlockFifoDepth;
+ /**
+ * Low Power FIFO depth in sending path.
+ * FIFO depth will be set to 2^lpFifoDepth. Each item has 8-bit width.
+ */
+ uint8_t lpFifoDepth;
+ /**
+ * High Speed FIFO depth in sending path.
+ * The depth of the FIFO is set to 2^hsFifoDepth. Each item has 8-bit width.
+ */
+ uint8_t hsFifoDepth;
+};
+
+/**
+ * Structure describing DSITX Host version and ID. Its content is filled by Core
+ * Driver when calling getHwIdAndVersion function.
+*/
+struct DSITX_HwIdAndVersion_s
+{
+ /** Vendor ID. */
+ uint16_t vendorId;
+ /** Product ID. */
+ uint8_t productId;
+ /** Hardware revision number. */
+ uint8_t revisionNumber;
+ /** Major revision value. */
+ uint8_t majorRevision;
+ /** Minor revision value. */
+ uint8_t minorRevision;
+};
+
+/** This structure contains information that is used to control DSITX Link. */
+struct DSITX_DsiLinkConfig_s
+{
+ /** Specifies if PLL is enabled (non 0) or disabled (0). */
+ bool pllEnabled;
+ /** Starts or stops clock lane. */
+ bool clkLaneEnabled;
+ /** Starts data lanes . */
+ bool datLaneEnabled[DSITX_MAX_LANE_NUMBER];
+ /** Switches clock lane in ULP Mode. */
+ bool clkLaneInUlpMode;
+ /** Switches data lanes in ULP Mode. */
+ bool datLaneInUlpMode[DSITX_MAX_LANE_NUMBER];
+ /** Enable SDI1 Interface. */
+ bool if1Enabled;
+ /** Enable DPI Interface. */
+ bool if2Enabled;
+ /** Enable DSC Interface. */
+ bool if3Enabled;
+ /** When enabled, data lanes are forced back in stop mode. */
+ bool forceStopMode;
+ /** Force clock lanes back in STOP mode. */
+ bool clkForceStop;
+};
+
+/** Structure describing the Direct Command Request. */
+struct DSITX_DirectCommandRequest_s
+{
+ /** Virtual Channel ID in case of read or write command type. */
+ uint8_t vcId;
+ /**
+ * Read or write command data size.
+ * In case of write request maximum size value is 16.
+ * In case of read request maximum size value is 2.
+ */
+ uint8_t cmdSize;
+ /** In case of read or write command this field state data type. */
+ uint8_t head;
+ /** If set command will be sent as long packet. */
+ bool longPacket;
+ /** Nature of command. */
+ DSITX_DirectCommandType type;
+ /** Enables Low Power mode for sending command request. */
+ bool lpMode;
+ /**
+ * Determines if function processing the request will wait for request
+ * to finish by polling status register or enable interrupts and exit
+ * immediately.
+ */
+ bool wait;
+ /** Direct Command execution status. Set after command completes. */
+ uint32_t status;
+ /**
+ * Specifies what events should be enabled and reported to the user
+ * when they occur. Set before sending request.
+ */
+ uint32_t enEvents;
+ /** Value of ACK if acknowledge with error has been received. */
+ uint16_t ackVal;
+ /** Value of the trigger in case of trigger command. */
+ DSITX_DirectCommandTriggerType triggerValue;
+ /** Direct Command read status. Set after read command completes. */
+ uint32_t rdStatus;
+ /**
+ * Specifies what read command events should be enabled and reported
+ * to the user when they occur. Set before sending request. This field
+ * will be ignored in case of command type different than
+ * DSITX_DCR_TYPE_READ.
+ */
+ uint32_t enRdEvents;
+ /** Pointer to buffer from which command data will be sent. */
+ uint8_t* cmdData;
+ /**
+ * Nature of Read Command. If true then this is a DCS packet.
+ * If false then its a generic read.
+ * This field is set by DSITX Host Driver when calling
+ * getDirectCmdRdDataProperties function.
+ */
+ bool dcsPk;
+ /**
+ * Number of bytes received from Display.
+ * Value of this field is set by the Core Driver
+ * when calling getDirectCmdRdDataProperties function.
+ */
+ uint16_t recDataSize;
+ /** Pointer to buffer where data received from Display will be stored. */
+ uint8_t* recData;
+};
+
+/**
+ * Generic Control and Status. Used by System for any extra DFT control
+ * through the DSITX controller
+*/
+struct DSITX_TestGeneric_s
+{
+ /** Test control - Drives test_generic_ctrl output. */
+ uint16_t ctrl;
+ /** Test status - Value of test_generic_status input. */
+ uint16_t status;
+};
+
+/** Configuration parameters passed to probe & init functions. */
+struct DSITX_Config_s
+{
+ /**
+ * Base address of the register space.
+ *
+ */
+ struct DSITX_Regs_s* regBase;
+ /**
+ * Number of physical lanes used in Video Mode.
+ * Valid values are 1-4.
+ */
+ uint8_t numOfLanes;
+ /** This handler is called when Direct Command request status changes. */
+ DSITX_DirectCmdEventHandler dirCmdEventHandler;
+ /**
+ * This handler is called during DSITX Host initialization to allow client
+ * configure (initialize) Display before DSITX Host Core Driver
+ * starts to operate.
+ */
+ DSITX_InitializeDisplayHandler initDisplay;
+};
+
+/** System requirements returned by probe. */
+struct DSITX_SysReq_s
+{
+ /** Size of memory required for driver's private data. */
+ uint32_t privDataSize;
+};
+
+/** Information about ASF in DSITX controller. */
+struct DSITX_AsfInfo_s
+{
+ /** ASF registers start addresses. */
+ volatile uint32_t* regBase;
+};
+
+/**
+ * @}
+ */
+
+#endif /* DSITX_STRUCTS_IF_H */
diff --git a/packages/ti/drv/dss/src/csl/dsi/src/cps_drv.h b/packages/ti/drv/dss/src/csl/dsi/src/cps_drv.h
--- /dev/null
@@ -0,0 +1,238 @@
+/******************************************************************************
+ *
+ * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ * cps_drv.h
+ * Interface for the Register Access Layer of Cadence Platform Service (CPS)
+ ******************************************************************************
+ */
+
+#ifndef CPS_DRV_H_
+#define CPS_DRV_H_
+
+#include "cps.h"
+
+// parasoft-begin-suppress MISRA2012-DIR-4_9-4 "function-like macro"
+// parasoft-begin-suppress MISRA2012-RULE-20_10-4 "## preprocessor operator"
+// parasoft-begin-suppress METRICS-36-3 "A function should not be called from more than 5 different functions"
+
+/**
+ * \brief Read a 32-bit value from memory.
+ * \param reg address of the memory mapped hardware register
+ * \return the value at the given address
+ */
+#define CPS_REG_READ(reg) (CPS_RegRead((volatile uint32_t*)(reg)))
+
+/**
+ * \brief Write a 32-bit address value to memory.
+ * \param reg address of the memory mapped hardware register
+ * \param value unsigned 32-bit value to write
+ */
+#define CPS_REG_WRITE(reg, value) (CPS_RegWrite((volatile uint32_t*)(reg), (uint32_t)(value)))
+
+/**
+ * \brief Read a 64-bit value from memory.
+ * \param reg address of the memory mapped hardware register
+ * \return the value at the given address
+ */
+#define CPS_REG_READ64(reg) (CPS_RegRead64((volatile uint64_t*)(reg)))
+
+/**
+ * \brief Write a 64-bit address value to memory.
+ * \param reg address of the memory mapped hardware register
+ * \param value unsigned 64-bit value to write
+ */
+#define CPS_REG_WRITE64(reg, value) (CPS_RegWrite64((volatile uint64_t*)(reg), (uint64_t)(value)))
+
+/**
+ * \brief Read a value of bit-field from the register value.
+ * \param reg register name
+ * \param fld field name
+ * \param reg_value register value
+ * \return bit-field value
+ */
+#define CPS_FLD_READ(reg, fld, reg_value) (CPS_FldRead((uint32_t)(reg##__##fld##_MASK), \
+ (uint32_t)(reg##__##fld##_SHIFT), \
+ (uint32_t)(reg_value)))
+
+/**
+ * \brief Write a value of the bit-field into the register value.
+ * \param reg register name
+ * \param fld field name
+ * \param reg_value register value
+ * \param value value to be written to bit-field
+ * \return modified register value
+ */
+#define CPS_FLD_WRITE(reg, fld, reg_value, value) (CPS_FldWrite((uint32_t)(reg##__##fld##_MASK), \
+ (uint32_t)(reg##__##fld##_SHIFT), \
+ (uint32_t)(reg_value), (uint32_t)(value)))
+
+/**
+ * \brief Set bit within the register value.
+ * \param reg register name
+ * \param fld field name
+ * \param reg_value register value
+ * \return modified register value
+ */
+#define CPS_FLD_SET(reg, fld, reg_value) (CPS_FldSet((uint32_t)(reg##__##fld##_WIDTH), \
+ (uint32_t)(reg##__##fld##_MASK), \
+ (uint32_t)(reg##__##fld##_WOCLR), \
+ (uint32_t)(reg_value)))
+
+/**
+ * \brief Clear bit within the register value.
+ * \param reg register name
+ * \param fld field name
+ * \param reg_value register value
+ * \return modified register value
+ */
+#define CPS_FLD_CLEAR(reg, fld, reg_value) (CPS_FldClear((uint32_t)(reg##__##fld##_WIDTH), \
+ (uint32_t)(reg##__##fld##_MASK), \
+ (uint32_t)(reg##__##fld##_WOSET), \
+ (uint32_t)(reg##__##fld##_WOCLR), \
+ (uint32_t)(reg_value)))
+
+/**
+ * \brief Read a 32-bit value from memory.
+ * \param reg address of the memory mapped hardware register
+ * \return the value at the given address
+ */
+static inline uint32_t CPS_RegRead(volatile uint32_t* reg)
+{
+ return (CSL_REG32_RD_RAW(reg));
+}
+
+/**
+ * \brief Write a 32-bit address value to memory.
+ * \param reg address of the memory mapped hardware register
+ * \param value unsigned 32-bit value to write
+ */
+static inline void CPS_RegWrite(volatile uint32_t* reg, uint32_t value)
+{
+ CSL_REG32_WR_RAW(reg, value);
+}
+
+/**
+ * \brief Read a 64-bit value from memory.
+ * \param reg address of the memory mapped hardware register
+ * \return the value at the given address
+ */
+static inline uint64_t CPS_RegRead64(volatile uint64_t* reg)
+{
+ return (CPS_ReadReg64(reg));
+}
+
+/**
+ * \brief Write a 64-bit address value to memory.
+ * \param reg address of the memory mapped hardware register
+ * \param value unsigned 64-bit value to write
+ */
+static inline void CPS_RegWrite64(volatile uint64_t* reg, uint64_t value)
+{
+ CPS_WriteReg64(reg, value);
+}
+
+/**
+ * \brief Read a value of bit-field from the register value.
+ * \param mask mask for the bit-field
+ * \param shift bit-field shift from LSB
+ * \param reg_value register value
+ * \return bit-field value
+ */
+static inline uint32_t CPS_FldRead(uint32_t mask, uint32_t shift, uint32_t reg_value)
+{
+ // parasoft-begin-suppress MISRA2012-RULE-12_2-2 "shift ranges"
+ uint32_t result = (reg_value & mask) >> shift;
+ // parasoft-end-suppress MISRA2012-RULE-12_2-2
+
+ return (result);
+}
+
+/**
+ * \brief Write a value of the bit-field into the register value.
+ * \param mask mask for the bit-field
+ * \param shift bit-field shift from LSB
+ * \param reg_value register value
+ * \param value value to be written to bit-field
+ * \return modified register value
+ */
+static inline uint32_t CPS_FldWrite(uint32_t mask, uint32_t shift, uint32_t reg_value, uint32_t value)
+{
+ // parasoft-begin-suppress MISRA2012-RULE-12_2-2 "shift ranges"
+ uint32_t new_value = (value << shift) & mask;
+ // parasoft-end-suppress MISRA2012-RULE-12_2-2
+
+ new_value = (reg_value & ~mask) | new_value;
+ return (new_value);
+}
+
+/**
+ * \brief Set bit within the register value.
+ * \param width width of the bit-field
+ * \param mask mask for the bit-field
+ * \param is_woclr is bit-field has 'write one to clear' flag set
+ * \param reg_value register value
+ * \return modified register value
+ */
+static inline uint32_t CPS_FldSet(uint32_t width, uint32_t mask, uint32_t is_woclr, uint32_t reg_value)
+{
+ uint32_t new_value = reg_value;
+ if ((width == 1U) && (is_woclr == 0U)) {
+ new_value |= mask;
+ }
+
+ return (new_value);
+}
+
+/**
+ * \brief Clear bit within the register value.
+ *
+ * \param width Width of the bit-field.
+ * \param mask Mask for the bit-field.
+ * \param is_woset Is bit-field has 'write one to set' flag set.
+ * \param is_woclr Is bit-field has 'write one to clear' flag set.
+ * \param reg_value Register value.
+ *
+ * \return Modified register value.
+ */
+static inline uint32_t CPS_FldClear(uint32_t width, uint32_t mask, uint32_t is_woset, uint32_t is_woclr, uint32_t reg_value)
+{
+ uint32_t new_value = reg_value;
+ if ((width == 1U) && (is_woset == 0U)) {
+ new_value = (new_value & ~mask) | ((is_woclr != 0U) ? mask : 0U);
+ }
+
+ return (new_value);
+}
+
+// parasoft-end-suppress MISRA2012-RULE-20_10-4
+// parasoft-end-suppress MISRA2012-DIR-4_9-4
+// parasoft-end-suppress METRICS-36-3
+
+#endif /* CPS_DRV_H_ */
+
diff --git a/packages/ti/drv/dss/src/csl/dsi/src/dsitx.c b/packages/ti/drv/dss/src/csl/dsi/src/dsitx.c
--- /dev/null
@@ -0,0 +1,2838 @@
+/******************************************************************************
+ * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * This file contains DSITX Core Driver API implementation.
+ *
+ *****************************************************************************/
+
+#include <src/csl/dsi/csl_dsi.h>
+
+#include "dsitx_priv.h"
+#include "dsitx_sanity.h"
+#include "dsitx_utils.h"
+#include "dsitx_cfg.h"
+
+#define REG_POOL_TIMEOUT 10000
+#define DIRECT_CMD_TIMEOUT 10000
+
+// parasoft-begin-suppress METRICS-36-3 "A function should not be called from more than 5 different functions"
+
+/**
+ * Returns 1U or 0U depending on a received flag in the type of bool.
+ */
+static inline uint32_t boolToVal(bool state)
+{
+ return ((state == true) ? 1U : 0U);
+}
+
+/**
+ * Returns true or false depending on a received uint32_t value.
+ */
+static inline bool valToBool(uint32_t value)
+{
+ return ((value != 0U) ? (bool)true : (bool)false);
+}
+
+#ifndef min
+/**
+ * Returns the lower value of two variables.
+ */
+static inline uint32_t min(uint32_t A, uint32_t B)
+{
+ return (((A) < (B)) ? (A) : (B));
+}
+#endif
+
+/* Structures with dsitx regs macros needed for iteration during access to fields
+grouped into arrays inside driver structures */
+static const struct {
+ uint32_t datLaneEnabled_mask;
+ uint32_t datLaneEnabled_shift;
+ uint32_t datLaneInUlpMode_mask;
+ uint32_t datLaneInUlpMode_shift;
+} dsiLinkConfig_defs[DSITX_MAX_LANE_NUMBER] = {
+ [0U].datLaneEnabled_mask = DSITX__MCTL_MAIN_EN__DAT1_EN_MASK,
+ [0U].datLaneEnabled_shift = DSITX__MCTL_MAIN_EN__DAT1_EN_SHIFT,
+ [0U].datLaneInUlpMode_mask = DSITX__MCTL_MAIN_EN__DAT1_ULPM_REQ_MASK,
+ [0U].datLaneInUlpMode_shift = DSITX__MCTL_MAIN_EN__DAT1_ULPM_REQ_SHIFT,
+
+ [1U].datLaneEnabled_mask = DSITX__MCTL_MAIN_EN__DAT2_EN_MASK,
+ [1U].datLaneEnabled_shift = DSITX__MCTL_MAIN_EN__DAT2_EN_SHIFT,
+ [1U].datLaneInUlpMode_mask = DSITX__MCTL_MAIN_EN__DAT2_ULPM_REQ_MASK,
+ [1U].datLaneInUlpMode_shift = DSITX__MCTL_MAIN_EN__DAT2_ULPM_REQ_SHIFT,
+
+ [2U].datLaneEnabled_mask = DSITX__MCTL_MAIN_EN__DAT3_EN_MASK,
+ [2U].datLaneEnabled_shift = DSITX__MCTL_MAIN_EN__DAT3_EN_SHIFT,
+ [2U].datLaneInUlpMode_mask = DSITX__MCTL_MAIN_EN__DAT3_ULPM_REQ_MASK,
+ [2U].datLaneInUlpMode_shift = DSITX__MCTL_MAIN_EN__DAT3_ULPM_REQ_SHIFT,
+
+ [3U].datLaneEnabled_mask = DSITX__MCTL_MAIN_EN__DAT4_EN_MASK,
+ [3U].datLaneEnabled_shift = DSITX__MCTL_MAIN_EN__DAT4_EN_SHIFT,
+ [3U].datLaneInUlpMode_mask = DSITX__MCTL_MAIN_EN__DAT4_ULPM_REQ_MASK,
+ [3U].datLaneInUlpMode_shift = DSITX__MCTL_MAIN_EN__DAT4_ULPM_REQ_SHIFT,
+};
+
+static const struct {
+ uint32_t laneUlpMode_mask;
+ uint32_t laneUlpMode_shift;
+} phyConfig_defs[DSITX_MAX_LANE_NUMBER] = {
+ [0U].laneUlpMode_mask = DSITX__MCTL_MAIN_PHY_CTL__DAT1_ULPM_EN_MASK,
+ [0U].laneUlpMode_shift = DSITX__MCTL_MAIN_PHY_CTL__DAT1_ULPM_EN_SHIFT,
+
+ [1U].laneUlpMode_mask = DSITX__MCTL_MAIN_PHY_CTL__DAT2_ULPM_EN_MASK,
+ [1U].laneUlpMode_shift = DSITX__MCTL_MAIN_PHY_CTL__DAT2_ULPM_EN_SHIFT,
+
+ [2U].laneUlpMode_mask = DSITX__MCTL_MAIN_PHY_CTL__DAT3_ULPM_EN_MASK,
+ [2U].laneUlpMode_shift = DSITX__MCTL_MAIN_PHY_CTL__DAT3_ULPM_EN_SHIFT,
+
+ [3U].laneUlpMode_mask = DSITX__MCTL_MAIN_PHY_CTL__DAT4_ULPM_EN_MASK,
+ [3U].laneUlpMode_shift = DSITX__MCTL_MAIN_PHY_CTL__DAT4_ULPM_EN_SHIFT,
+};
+
+/* internal function */
+static uint32_t getTvgStripeSizeEnum(const uint32_t val, DSITX_TvgStripeSize *enumVal)
+{
+ #define TVG_STRIP_SIZE_ENUMS_CNT 8U
+
+ uint32_t i;
+ uint32_t status = CDN_EINVAL;
+
+ const DSITX_TvgStripeSize tvgStripeSizeEnums[TVG_STRIP_SIZE_ENUMS_CNT] = {
+ [0U] = DSITX_TVG_STRIPE_SIZE_1,
+ [1U] = DSITX_TVG_STRIPE_SIZE_2,
+ [2U] = DSITX_TVG_STRIPE_SIZE_4,
+ [3U] = DSITX_TVG_STRIPE_SIZE_8,
+ [4U] = DSITX_TVG_STRIPE_SIZE_16,
+ [5U] = DSITX_TVG_STRIPE_SIZE_32,
+ [6U] = DSITX_TVG_STRIPE_SIZE_64,
+ [7U] = DSITX_TVG_STRIPE_SIZE_128,
+ };
+
+ /* converts uint32_t to enum */
+ for (i = 0U; i < TVG_STRIP_SIZE_ENUMS_CNT; ++i) {
+ if ((uint32_t)tvgStripeSizeEnums[i] == val) {
+ *enumVal = tvgStripeSizeEnums[i];
+ status = CDN_EOK;
+ break;
+ }
+ }
+
+ return status;
+}
+
+/* internal function */
+static uint32_t getHeaderEnum(const uint32_t val, DSITX_VideoDataType *enumVal)
+{
+ #define HEADER_ENUMS_CNT 11U
+
+ uint32_t i;
+ uint32_t status = CDN_EINVAL;
+
+ const DSITX_VideoDataType headerEnums[HEADER_ENUMS_CNT] = {
+ [0U] = DSITX_VID_DATA_TYPE_DEFAULT,
+ [1U] = DSITX_VID_DATA_TYPE_YCBCR_20,
+ [2U] = DSITX_VID_DATA_TYPE_YCBCR_24,
+ [3U] = DSITX_VID_DATA_TYPE_YCBCR_16,
+ [4U] = DSITX_VID_DATA_TYPE_RGB_30,
+ [5U] = DSITX_VID_DATA_TYPE_RGB_36,
+ [6U] = DSITX_VID_DATA_TYPE_YCBCR_12,
+ [7U] = DSITX_VID_DATA_TYPE_RGB_16,
+ [8U] = DSITX_VID_DATA_TYPE_RGB_18,
+ [9U] = DSITX_VID_DATA_TYPE_RGB_18_LOOSELY,
+ [10U] = DSITX_VID_DATA_TYPE_RGB_24,
+ };
+
+ /* converts uint32_t to enum */
+ for (i = 0U; i < HEADER_ENUMS_CNT; ++i) {
+ if ((uint32_t)headerEnums[i] == val) {
+ *enumVal = headerEnums[i];
+ status = CDN_EOK;
+ break;
+ }
+ }
+
+ return status;
+}
+
+/* internal function */
+static uint32_t getVidSync3dModeEnum(const uint32_t val, DSITX_Video3dMode *enumVal)
+{
+ uint32_t status = CDN_EOK;
+
+ /* converts uint32_t to enum */
+ if ((uint32_t)DSITX_VIDEO_MODE_2D == val) {
+ *enumVal = DSITX_VIDEO_MODE_2D;
+ } else if ((uint32_t)DSITX_VIDEO_MODE_PORTRAIT == val) {
+ *enumVal = DSITX_VIDEO_MODE_PORTRAIT;
+ } else if ((uint32_t)DSITX_VIDEO_MODE_LANDSCAPE == val) {
+ *enumVal = DSITX_VIDEO_MODE_LANDSCAPE;
+ } else {
+ status = CDN_EINVAL;
+ }
+
+ return status;
+}
+
+/* internal function */
+static uint32_t getVidSync3dFormatEnum(const uint32_t val, DSITX_Video3dFormat *enumVal)
+{
+ uint32_t status = CDN_EOK;
+
+ /* converts uint32_t to enum */
+ if ((uint32_t)DSITX_VIDEO_FORMAT_LINE == val) {
+ *enumVal = DSITX_VIDEO_FORMAT_LINE;
+ } else if ((uint32_t)DSITX_VIDEO_FORMAT_FRAME == val) {
+ *enumVal = DSITX_VIDEO_FORMAT_FRAME;
+ } else if ((uint32_t)DSITX_VIDEO_FORMAT_PIXEL == val) {
+ *enumVal = DSITX_VIDEO_FORMAT_PIXEL;
+ } else {
+ status = CDN_EINVAL;
+ }
+
+ return status;
+}
+
+/* internal function */
+static uint32_t getVideoIfSelectEnum(const uint32_t val, DSITX_VideoInterfaceSelection *enumVal)
+{
+ uint32_t status = CDN_EOK;
+
+ /* converts uint32_t to enum */
+ if ((uint32_t)DSITX_VID_IF_SELECT_IF1 == val) {
+ *enumVal = DSITX_VID_IF_SELECT_IF1;
+ } else if ((uint32_t)DSITX_VID_IF_SELECT_IF2 == val) {
+ *enumVal = DSITX_VID_IF_SELECT_IF2;
+ } else if ((uint32_t)DSITX_VID_IF_SELECT_IF3 == val) {
+ *enumVal = DSITX_VID_IF_SELECT_IF3;
+ } else {
+ status = CDN_EINVAL;
+ }
+
+ return status;
+}
+
+/* internal function */
+static uint32_t getVidVsync3dLrEnum(const uint32_t val, DSITX_Video3dFirstSide *enumVal)
+{
+ uint32_t status = CDN_EOK;
+
+ /* converts uint32_t to enum */
+ if ((uint32_t)DSITX_VIDEO_START_LEFT == val) {
+ *enumVal = DSITX_VIDEO_START_LEFT;
+ }
+ else if ((uint32_t)DSITX_VIDEO_START_RIGHT == val) {
+ *enumVal = DSITX_VIDEO_START_RIGHT;
+ } else {
+ status = CDN_EINVAL;
+ }
+
+ return status;
+}
+
+/* internal function */
+static uint32_t getInterfaceModeEnum(const uint32_t val, DSITX_InterfaceMode *enumVal)
+{
+ uint32_t status = CDN_EOK;
+
+ /* converts uint32_t to enum */
+ if ((uint32_t)DSITX_IF_MODE_COMMAND == val) {
+ *enumVal = DSITX_IF_MODE_COMMAND;
+ }
+ else if ((uint32_t)DSITX_IF_MODE_VIDEO == val) {
+ *enumVal = DSITX_IF_MODE_VIDEO;
+ } else {
+ status = CDN_EINVAL;
+ }
+
+ return status;
+}
+
+/* internal function */
+static uint32_t getCmdArbitrationPriorityEnum(const uint32_t val, DSITX_CmdArbitrationPriority *enumVal)
+{
+ uint32_t status = CDN_EOK;
+
+ /* converts uint32_t to enum */
+ if ((uint32_t)DSITX_CMD_ARB_PRIORITY_INIT == val) {
+ *enumVal = DSITX_CMD_ARB_PRIORITY_INIT;
+ } else if ((uint32_t)DSITX_CMD_ARB_PRIORITY_SDI == val) {
+ *enumVal = DSITX_CMD_ARB_PRIORITY_SDI;
+ } else if ((uint32_t)DSITX_CMD_ARB_PRIORITY_DSC == val) {
+ *enumVal = DSITX_CMD_ARB_PRIORITY_DSC;
+ } else {
+ status = CDN_EINVAL;
+ }
+
+ return status;
+}
+
+/* internal function */
+static uint32_t getCommandArbitrationModeEnum(const uint32_t val, DSITX_CmdArbitrationMode *enumVal)
+{
+ uint32_t status = CDN_EOK;
+
+ /* converts uint32_t to enum */
+ if ((uint32_t)DSITX_CMD_ARBITRATION_MODE_FIXED == val) {
+ *enumVal = DSITX_CMD_ARBITRATION_MODE_FIXED;
+ }
+ else if ((uint32_t)DSITX_CMD_ARBITRATION_MODE_ROUND_ROBIN == val) {
+ *enumVal = DSITX_CMD_ARBITRATION_MODE_ROUND_ROBIN;
+ } else {
+ status = CDN_EINVAL;
+ }
+
+ return status;
+}
+
+/* internal function */
+static uint32_t getTvgStopModeEnum(const uint32_t val, DSITX_TvgStopMode *enumVal)
+{
+ uint32_t status = CDN_EOK;
+
+ /* converts uint32_t to enum */
+ if ((uint32_t)DSITX_TVG_STOP_MODE_AT_END_OF_FRAME == val) {
+ *enumVal = DSITX_TVG_STOP_MODE_AT_END_OF_FRAME;
+ }
+ else if ((uint32_t)DSITX_TVG_STOP_MODE_AT_END_OF_LINE == val) {
+ *enumVal = DSITX_TVG_STOP_MODE_AT_END_OF_LINE;
+ }
+ else if ((uint32_t)DSITX_TVG_STOP_MODE_IMMEDIATE == val) {
+ *enumVal = DSITX_TVG_STOP_MODE_IMMEDIATE;
+ } else {
+ status = CDN_EINVAL;
+ }
+
+ return status;
+}
+
+/* internal function */
+static uint32_t getVideoBlankingModeEnum(const uint32_t val, DSITX_VideoBlankingMode *enumVal)
+{
+ uint32_t status = CDN_EOK;
+
+ /* converts uint32_t to enum */
+ if ((uint32_t)DSITX_VID_BLK_MODE_NULL_PACKET == val) {
+ *enumVal = DSITX_VID_BLK_MODE_NULL_PACKET;
+ }
+ else if ((uint32_t)DSITX_VID_BLK_MODE_BLANKING_PACKET == val) {
+ *enumVal = DSITX_VID_BLK_MODE_BLANKING_PACKET;
+ }
+ else if ((uint32_t)DSITX_VID_BLK_MODE_LP == val) {
+ *enumVal = DSITX_VID_BLK_MODE_LP;
+ } else {
+ status = CDN_EINVAL;
+ }
+
+ return status;
+}
+
+/* internal function */
+static uint32_t getVideoStartModeEnum(const uint32_t val, DSITX_VideoStartMode *enumVal)
+{
+ uint32_t status = CDN_EOK;
+
+ /* converts uint32_t to enum */
+ if ((uint32_t)DSITX_VID_START_MODE_START_ON_VSYNC == val) {
+ *enumVal = DSITX_VID_START_MODE_START_ON_VSYNC;
+ } else {
+ status = CDN_EINVAL;
+ }
+
+ return status;
+}
+
+/* internal function */
+static uint32_t getVideoStopModeEnum(const uint32_t val, DSITX_VideoStopMode *enumVal)
+{
+ uint32_t status = CDN_EOK;
+
+ /* converts uint32_t to enum */
+ if ((uint32_t)DSITX_VID_STOP_MODE_STOP_JUST_BEFORE_VSYNC == val) {
+ *enumVal = DSITX_VID_STOP_MODE_STOP_JUST_BEFORE_VSYNC;
+ } else if ((uint32_t)DSITX_VID_STOP_MODE_STOP_INIT == val) {
+ *enumVal = DSITX_VID_STOP_MODE_STOP_INIT;
+ } else {
+ status = CDN_EINVAL;
+ }
+
+ return status;
+}
+
+/* internal function */
+static uint32_t getVideoPixelModeEnum(const uint32_t val, DSITX_VideoPixelMode *enumVal)
+{
+ #define VID_STOP_PIXEL_MODE_ENUMS_CNT 10U
+
+ uint32_t status = CDN_EINVAL;
+ uint32_t i;
+
+ const DSITX_VideoPixelMode videoPixelModeEnums[VID_STOP_PIXEL_MODE_ENUMS_CNT] = {
+ [0U] = DSITX_VID_PIXEL_MODE_RGB_16,
+ [1U] = DSITX_VID_PIXEL_MODE_RGB_18,
+ [2U] = DSITX_VID_PIXEL_MODE_RGB_18_LOOSELY,
+ [3U] = DSITX_VID_PIXEL_MODE_RGB_24,
+ [4U] = DSITX_VID_PIXEL_MODE_RGB_30,
+ [5U] = DSITX_VID_PIXEL_MODE_RGB_36,
+ [6U] = DSITX_VID_PIXEL_MODE_YCBCR_12,
+ [7U] = DSITX_VID_PIXEL_MODE_YCBCR_16,
+ [8U] = DSITX_VID_PIXEL_MODE_YCBCR_20,
+ [9U] = DSITX_VID_PIXEL_MODE_YCBCR_24,
+ };
+
+ /* converts uint32_t to enum */
+ for (i = 0U; i < VID_STOP_PIXEL_MODE_ENUMS_CNT; ++i) {
+ if ((uint32_t)videoPixelModeEnums[i] == val) {
+ *enumVal = videoPixelModeEnums[i];
+ status = CDN_EOK;
+ break;
+ }
+ }
+
+ return status;
+}
+
+/* internal function */
+static uint32_t getVideoRecoveryModeEnum(const uint32_t val, DSITX_VideoRecoveryMode *enumVal)
+{
+ uint32_t status = CDN_EOK;
+
+ /* converts uint32_t to enum */
+ if ((uint32_t)DSITX_CONTINUE_TILL_NEXT_HSYNC == val) {
+ *enumVal = DSITX_CONTINUE_TILL_NEXT_HSYNC;
+ }
+ else if ((uint32_t)DSITX_CONTINUE_UNTIL_NEXT_STOP_POINT == val) {
+ *enumVal = DSITX_CONTINUE_UNTIL_NEXT_STOP_POINT;
+ }
+ else if ((uint32_t)DSITX_CONTINUE_TILL_NEXT_VSYNC == val) {
+ *enumVal = DSITX_CONTINUE_TILL_NEXT_VSYNC;
+ } else {
+ status = CDN_EINVAL;
+ }
+
+ return status;
+}
+
+/* internal function */
+static uint32_t getTvgDisplayModeEnum(const uint32_t val, DSITX_TvgDisplayMode *enumVal)
+{
+ uint32_t status = CDN_EOK;
+
+ /* converts uint32_t to enum */
+ if ((uint32_t)DSITX_TVG_MODE_SINGLE_COLOR == val) {
+ *enumVal = DSITX_TVG_MODE_SINGLE_COLOR;
+ }
+ else if ((uint32_t)DSITX_TVG_MODE_VERTICAL_STRIPES == val) {
+ *enumVal = DSITX_TVG_MODE_VERTICAL_STRIPES;
+ }
+ else if ((uint32_t)DSITX_TVG_MODE_HORIZONTAL_STRIPES == val) {
+ *enumVal = DSITX_TVG_MODE_HORIZONTAL_STRIPES;
+ } else {
+ status = CDN_EINVAL;
+ }
+
+ return status;
+}
+/**
+* END OF THE CONVERSION FUNCTION BLOCK
+*/
+
+/* internal function */
+static uint32_t readDCRData(DSITX_PrivateData *pD, DSITX_DirectCommandRequest *dcr)
+{
+ uint32_t regVal;
+ uint8_t *ptr;
+ uint8_t index = 0U;
+ uint32_t size;
+ uint32_t status = CDN_EOK;
+
+ if (dcr->recData == NULL) {
+ status = CDN_EINVAL;
+ } else {
+ /* read register */
+ regVal = CPS_REG_READ(&pD->regBase->direct_cmd_rd_property);
+
+ /* get DCR info */
+ dcr->dcsPk = valToBool(CPS_FLD_READ(DSITX__DIRECT_CMD_RD_PROPERTY, RD_DCSNOTGENERIC, regVal));
+ dcr->vcId = (uint8_t)CPS_FLD_READ(DSITX__DIRECT_CMD_RD_PROPERTY, RD_ID, regVal);
+ dcr->recDataSize = (uint16_t)CPS_FLD_READ(DSITX__DIRECT_CMD_RD_PROPERTY, RD_SIZE, regVal);
+
+ dcr->rdStatus = CPS_REG_READ(&pD->regBase->direct_cmd_rd_sts);
+
+ size = dcr->recDataSize;
+ ptr = dcr->recData;
+
+ /* read data and store in buffer */
+ while (size != 0U) {
+ regVal = CPS_REG_READ(&pD->regBase->direct_cmd_rddat);
+ WriteToBuff32le(&ptr[index], size, regVal);
+
+ index += 4U;
+ size -= min(size, 4U);
+ }
+ }
+ return status;
+}
+
+/**
+ * Reads information about DSITX version.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] id Pointer to structure where DSITX version information will be stored.
+ * @return CDN_EINVAL If pD or id is NULL.
+ * @return CDN_EOK If information is successfully obtained.
+ */
+uint32_t DSITX_GetHwIdAndVersion(DSITX_PrivateData* pD, DSITX_HwIdAndVersion* id)
+{
+ uint32_t regVal;
+ uint32_t status;
+
+ /* check params */
+ if (DSITX_GetHwIdAndVersionSF(pD, id) != CDN_EOK) {
+ status = CDN_EINVAL;
+ } else {
+ /* read register */
+ regVal = CPS_REG_READ(&pD->regBase->id_reg);
+ /* extract version information */
+ id->vendorId = (uint16_t)CPS_FLD_READ(DSITX__ID_REG, REV_VENDOR_ID, regVal);
+ id->productId = (uint8_t)CPS_FLD_READ(DSITX__ID_REG, REV_PRODUCT_ID, regVal);
+ id->revisionNumber = (uint8_t)CPS_FLD_READ(DSITX__ID_REG, REV_HARDWARE, regVal);
+ id->majorRevision = (uint8_t)CPS_FLD_READ(DSITX__ID_REG, REV_X, regVal);
+ id->minorRevision = (uint8_t)CPS_FLD_READ(DSITX__ID_REG, REV_Y, regVal);
+
+ status = CDN_EOK;
+ }
+ return status;
+}
+
+/* internal function */
+static void getIpConfSizes(DSITX_IpConf* config, uint32_t regVal)
+{
+ /* 0 - 32-bit, 1 - 16-bit, 3 - 8-bit */
+ if (CPS_FLD_READ(DSITX__IP_CONF, DATAPATH_SIZE, regVal) < 0x4U) {
+ config->datapathSize = (uint8_t)((uint8_t)32 >> CPS_FLD_READ(DSITX__IP_CONF, DATAPATH_SIZE, regVal));
+ } else {
+ config->datapathSize = 8;
+ }
+
+ /* 0 - 16-bit, 1 - 32-bit */
+ if (CPS_FLD_READ(DSITX__IP_CONF, INTERFACE_DATASIZE, regVal) < 0x4U) {
+ config->sdiIfDataBusSize = (uint8_t)((uint8_t)16 << (CPS_FLD_READ(DSITX__IP_CONF, INTERFACE_DATASIZE, regVal)));
+ }
+}
+
+/* internal function */
+static void getIpConfDepths(DSITX_IpConf* config, uint32_t regVal)
+{
+ /* Depths are 2^regval */
+ if ((CPS_FLD_READ(DSITX__IP_CONF, VRS_FIFO_DEPTH, regVal)) < (0x8U)) {
+ config->vrsBlockFifoDepth = (uint8_t)((uint8_t)1 << CPS_FLD_READ(DSITX__IP_CONF, VRS_FIFO_DEPTH, regVal));
+ }
+
+ if(CPS_FLD_READ(DSITX__IP_CONF, SP_LP_FIFO_DEPTH, regVal) < 0x8U) {
+ config->lpFifoDepth = (uint8_t)((uint8_t)1 << (CPS_FLD_READ(DSITX__IP_CONF, SP_LP_FIFO_DEPTH, regVal)));
+ }
+ if(CPS_FLD_READ(DSITX__IP_CONF, SP_HS_FIFO_DEPTH, regVal) < 0x8U) {
+ config->hsFifoDepth = (uint8_t)((uint8_t)1 << CPS_FLD_READ(DSITX__IP_CONF, SP_HS_FIFO_DEPTH, regVal));
+ }
+}
+
+/**
+ * Obtains IP configuration.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] config Pointer to structure to which DSITX IP configuration will be stored.
+ * @return CDN_EINVAL If pD or config is NULL.
+ * @return CDN_EOK If configuration is successfully obtained.
+ */
+uint32_t DSITX_GetIpConf(DSITX_PrivateData* pD, DSITX_IpConf* config)
+{
+ uint32_t regVal;
+ uint32_t status;
+
+ /* check params */
+ if (DSITX_GetIpConfSF(pD, config) != CDN_EOK) {
+ status = CDN_EINVAL;
+ } else {
+ /* read register */
+ regVal = CPS_REG_READ(&pD->regBase->ip_conf);
+
+ getIpConfSizes(config, regVal);
+
+ config->rxFifoDepth = (uint8_t)CPS_FLD_READ(DSITX__IP_CONF, RX_FIFO_DEPTH, regVal);
+ /* num = regval+1 */
+ config->maxLaneNumber = (uint8_t)(CPS_FLD_READ(DSITX__IP_CONF, MAX_LANE_NB, regVal) + 1U);
+ config->sdiIfNumber = (uint8_t)(CPS_FLD_READ(DSITX__IP_CONF, NUM_INTERFACE, regVal) + 1U);
+
+ /* Direct Command FIFO size = 2^(regval+2) */
+ if ((CPS_FLD_READ(DSITX__IP_CONF, DIRCMD_FIFO_DEPTH, regVal) + 2U) < 0xFU) {
+ config->directCmdFifoDepth = (uint16_t)((uint16_t)1 << (CPS_FLD_READ(DSITX__IP_CONF, DIRCMD_FIFO_DEPTH, regVal) + 2U));
+ }
+ getIpConfDepths(config, regVal);
+ status = CDN_EOK;
+ }
+ return status;
+}
+
+/**
+ * Obtains DSITX Link configuration.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] config Pointer to structure to which DSITX Link setup will be stored.
+ * @return CDN_EINVAL If pD or config is NULL.
+ * @return CDN_EOK If configuration is successfully obtained.
+ */
+uint32_t DSITX_GetDsiLinkConfig(DSITX_PrivateData* pD, DSITX_DsiLinkConfig* config)
+{
+ uint32_t status;
+ uint32_t regVal;
+ uint32_t i;
+
+ /* check params */
+ if (DSITX_GetDsiLinkConfigSF(pD, config) != CDN_EOK) {
+ status = CDN_EINVAL;
+ } else {
+ /* read register */
+ regVal = CPS_REG_READ(&pD->regBase->mctl_main_en);
+ /* get PLL/CLK status */
+ config->pllEnabled = valToBool(CPS_FLD_READ(DSITX__MCTL_MAIN_EN, PLL_START, regVal));
+ config->clkLaneEnabled = valToBool(CPS_FLD_READ(DSITX__MCTL_MAIN_EN, CKLANE_EN, regVal));
+
+ /* get lane status */
+ for (i = 0U; i < ((uint32_t)DSITX_MAX_LANE_NUMBER); ++i) {
+ config->datLaneEnabled[i] = valToBool(CPS_FldRead(dsiLinkConfig_defs[i].datLaneEnabled_mask, dsiLinkConfig_defs[i].datLaneEnabled_shift, regVal));
+ }
+
+ config->clkLaneInUlpMode = valToBool(CPS_FLD_READ(DSITX__MCTL_MAIN_EN, CLKLANE_ULPM_REQ, regVal));
+
+ for (i = 0U; i < ((uint32_t)DSITX_MAX_LANE_NUMBER); ++i) {
+ config->datLaneInUlpMode[i] = valToBool(CPS_FldRead(dsiLinkConfig_defs[i].datLaneInUlpMode_mask, dsiLinkConfig_defs[i].datLaneInUlpMode_shift, regVal));
+ }
+
+ config->if1Enabled = valToBool(CPS_FLD_READ(DSITX__MCTL_MAIN_EN, IF1_EN, regVal));
+ config->if2Enabled = valToBool(CPS_FLD_READ(DSITX__MCTL_MAIN_EN, IF2_EN, regVal));
+ config->if3Enabled = valToBool(CPS_FLD_READ(DSITX__MCTL_MAIN_EN, IF3_EN, regVal));
+
+ config->clkForceStop = valToBool(CPS_FLD_READ(DSITX__MCTL_MAIN_EN, CLK_FORCE_STOP, regVal));
+ config->forceStopMode = valToBool(CPS_FLD_READ(DSITX__MCTL_MAIN_EN, FORCE_STOP_MODE, regVal));
+
+ status = CDN_EOK;
+ }
+ return status;
+}
+
+/* internal function */
+static uint32_t checkMagicNumber(const DSITX_Config *config) {
+ uint32_t ret = CDN_EOK;
+ uint32_t volatile *id_reg_addr = &((DSITX_Regs volatile*)config->regBase)->id_reg;
+ uint32_t idRegValue = CPS_REG_READ(id_reg_addr);
+ uint32_t vendor_id = CPS_FLD_READ(DSITX__ID_REG, REV_VENDOR_ID, idRegValue);
+ uint32_t product_id = CPS_FLD_READ(DSITX__ID_REG, REV_PRODUCT_ID, idRegValue);
+ uint32_t magicNumber = (vendor_id << DSITX__ID_REG__REV_PRODUCT_ID_WIDTH) | product_id;
+ if (magicNumber != DSITX_MAGIC_NUMBER) {
+ ret = CDN_EINVAL;
+ }
+ return ret;
+}
+
+/**
+ * Obtains the driver's memory requirements to support the given
+ * configuration.
+ * @param[in] config Proposed driver/hardware configuration.
+ * @param[out] sysReq Returns the memory requirements for given configuration in field privDataSize.
+ * @return CDN_EOK On success (requirements struct filled).
+ * @return CDN_EINVAL If config contains invalid values or not supported configuration.
+ */
+uint32_t DSITX_Probe(const DSITX_Config* config, DSITX_SysReq* sysReq)
+{
+ uint32_t maxLanes;
+ uint32_t result;
+
+ /* check params */
+ if ((DSITX_ProbeSF(config, sysReq) != CDN_EOK) || (checkMagicNumber(config) != CDN_EOK)) {
+ result = CDN_EINVAL;
+ } else {
+ uint32_t volatile *ip_conf_addr = &((DSITX_Regs volatile*)config->regBase)->ip_conf;
+
+ /* check lanes info */
+ maxLanes = CPS_FLD_READ(DSITX__IP_CONF, MAX_LANE_NB, CPS_REG_READ(ip_conf_addr)) + 1U;
+ if (maxLanes < (uint32_t)config->numOfLanes) {
+ result = CDN_EINVAL;
+ } else {
+ sysReq->privDataSize = (uint32_t)(sizeof(DSITX_PrivateData));
+ result = CDN_EOK;
+ }
+ }
+ return result;
+}
+
+/* internal function */
+static uint32_t setDsiLinkConfigDataLanes(const DSITX_DsiLinkConfig* config, uint32_t regValue)
+{
+ uint32_t i;
+ uint32_t regVal = regValue;
+
+ /* convert array to register value */
+ for (i = 0U; i < ((uint32_t)DSITX_MAX_LANE_NUMBER); ++i) {
+ regVal = CPS_FldWrite(dsiLinkConfig_defs[i].datLaneEnabled_mask, dsiLinkConfig_defs[i].datLaneEnabled_shift, regVal, boolToVal(config->datLaneEnabled[i]));
+ }
+
+ for (i = 0U; i < ((uint32_t)DSITX_MAX_LANE_NUMBER); ++i) {
+ regVal = CPS_FldWrite(dsiLinkConfig_defs[i].datLaneInUlpMode_mask, dsiLinkConfig_defs[i].datLaneInUlpMode_shift, regVal, boolToVal(config->datLaneInUlpMode[i]));
+ }
+
+ return regVal;
+}
+
+/**
+ * Sets DSITX Link configuration.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] config Pointer to structure containing DSITX Link configuration.
+ * @return CDN_EINVAL If pD or config is NULL.
+ * @return CDN_EOK If configuration is successfully set.
+ */
+uint32_t DSITX_SetDsiLinkConfig(DSITX_PrivateData* pD, const DSITX_DsiLinkConfig* config)
+{
+ uint32_t regVal;
+ uint32_t status;
+
+ /* check params */
+ if (DSITX_SetDsiLinkConfigSF(pD, config) != CDN_EOK) {
+ status = CDN_EINVAL;
+ } else {
+ regVal = 0U;
+ regVal = setDsiLinkConfigDataLanes(config, regVal);
+
+ /* build register value */
+ regVal = CPS_FLD_WRITE(DSITX__MCTL_MAIN_EN, PLL_START, regVal, boolToVal(config->pllEnabled));
+ regVal = CPS_FLD_WRITE(DSITX__MCTL_MAIN_EN, CKLANE_EN, regVal, boolToVal(config->clkLaneEnabled));
+
+ regVal = CPS_FLD_WRITE(DSITX__MCTL_MAIN_EN, CLKLANE_ULPM_REQ, regVal, boolToVal(config->clkLaneInUlpMode));
+
+ regVal = CPS_FLD_WRITE(DSITX__MCTL_MAIN_EN, IF1_EN, regVal, boolToVal(config->if1Enabled));
+ regVal = CPS_FLD_WRITE(DSITX__MCTL_MAIN_EN, IF2_EN, regVal, boolToVal(config->if2Enabled));
+ regVal = CPS_FLD_WRITE(DSITX__MCTL_MAIN_EN, IF3_EN, regVal, boolToVal(config->if3Enabled));
+
+ regVal = CPS_FLD_WRITE(DSITX__MCTL_MAIN_EN, CLK_FORCE_STOP, regVal, boolToVal(config->clkForceStop));
+ regVal = CPS_FLD_WRITE(DSITX__MCTL_MAIN_EN, FORCE_STOP_MODE,regVal, boolToVal(config->forceStopMode));
+
+ /* write to register */
+ CPS_REG_WRITE(&pD->regBase->mctl_main_en, regVal);
+
+ status = CDN_EOK;
+ }
+ return status;
+}
+
+/* internal function */
+static uint32_t setDataPathConfigDisp(const DSITX_DataPathConfig* config, uint32_t regValue)
+{
+ uint32_t regVal = regValue;
+
+ /* set display fields */
+ regVal = CPS_FLD_WRITE(DSITX__MCTL_MAIN_DATA_CTL, DISP_GEN_ECC, regVal, boolToVal(config->dispGenEcc));
+ regVal = CPS_FLD_WRITE(DSITX__MCTL_MAIN_DATA_CTL, DISP_GEN_CHECKSUM, regVal, boolToVal(config->dispGenChecksum));
+ regVal = CPS_FLD_WRITE(DSITX__MCTL_MAIN_DATA_CTL, DISP_EOT_GEN, regVal, boolToVal(config->dispEotGen));
+
+ return (regVal);
+}
+
+/* internal function */
+static uint32_t setDataPathConfigTe(const DSITX_DataPathConfig* config, uint32_t regValue)
+{
+ uint32_t regVal = regValue;
+
+ /* set tie fields */
+ regVal = CPS_FLD_WRITE(DSITX__MCTL_MAIN_DATA_CTL, IF1_TE_EN, regVal, boolToVal(config->if1TeEnabled));
+ regVal = CPS_FLD_WRITE(DSITX__MCTL_MAIN_DATA_CTL, REG_TE_EN, regVal, boolToVal(config->regTeEnabled));
+ regVal = CPS_FLD_WRITE(DSITX__MCTL_MAIN_DATA_CTL, TE_HW_POLLING_EN, regVal, boolToVal(config->teHwPolling));
+ regVal = CPS_FLD_WRITE(DSITX__MCTL_MAIN_DATA_CTL, TE_MIPI_POLLING_EN, regVal, boolToVal(config->teMipiPolling));
+
+ return (regVal);
+}
+
+/* internal function */
+static uint32_t setDataPathConfigVid(const DSITX_DataPathConfig* config, uint32_t regValue)
+{
+ uint32_t regVal = regValue;
+
+ /* set vid/tvg fields */
+ regVal = CPS_FLD_WRITE(DSITX__MCTL_MAIN_DATA_CTL, SDI_IF_VID_MODE, regVal, config->interfaceMode);
+ regVal = CPS_FLD_WRITE(DSITX__MCTL_MAIN_DATA_CTL, VID_IF_SELECT, regVal, config->videoIfSelect);
+ regVal = CPS_FLD_WRITE(DSITX__MCTL_MAIN_DATA_CTL, VID_EN, regVal, boolToVal(config->videoStreamGenEnabled));
+ regVal = CPS_FLD_WRITE(DSITX__MCTL_MAIN_DATA_CTL, TVG_SEL, regVal, boolToVal(config->tvgEnabled));
+
+ return (regVal);
+}
+
+/* internal function */
+static uint32_t setDataPathConfigMod(const DSITX_DataPathConfig* config, uint32_t regValue)
+{
+ uint32_t regVal = regValue;
+ const DSITX_DataPathConfig* cfg = config;
+
+ regVal = setDataPathConfigVid(cfg, regVal);
+ regVal = setDataPathConfigTe(cfg, regVal);
+ regVal = setDataPathConfigDisp(cfg, regVal);
+
+ return (regVal);
+}
+
+/**
+ * Sets Data Path configuration.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] config Pointer to structure containing Data Path configuration.
+ * @return CDN_EINVAL If pD or config is NULL.
+ * @return CDN_EOK If configuration is successfully set.
+ */
+uint32_t DSITX_SetDataPathConfig(DSITX_PrivateData* pD, const DSITX_DataPathConfig* config)
+{
+ uint32_t regVal;
+ uint32_t status;
+
+ /* check params */
+ if (DSITX_SetDataPathConfigSF(pD, config) != CDN_EOK) {
+ status = CDN_EINVAL;
+ } else {
+ status = CDN_EOK;
+ }
+
+ if (status == CDN_EOK) {
+ /* read register */
+ regVal = CPS_REG_READ(&pD->regBase->mctl_main_data_ctl);
+ /* call helper function */
+ regVal = setDataPathConfigMod(config, regVal);
+ /* add more fields */
+ regVal = CPS_FLD_WRITE(DSITX__MCTL_MAIN_DATA_CTL, HOST_EOT_GEN, regVal, boolToVal(config->hostEotGen));
+ regVal = CPS_FLD_WRITE(DSITX__MCTL_MAIN_DATA_CTL, LINK_EN, regVal, boolToVal(config->linkEnabled));
+ regVal = CPS_FLD_WRITE(DSITX__MCTL_MAIN_DATA_CTL, READ_EN, regVal, boolToVal(config->readOpEnabled));
+ regVal = CPS_FLD_WRITE(DSITX__MCTL_MAIN_DATA_CTL, BTA_EN, regVal, boolToVal(config->btaEnabled));
+ /* write to register */
+ CPS_REG_WRITE(&pD->regBase->mctl_main_data_ctl, regVal);
+ }
+ return status;
+}
+
+/**
+ * Sets PHY main configuration.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] config Pointer to structure containing PHY configuration.
+ * @return CDN_EINVAL If pD or config is NULL.
+ * @return CDN_EOK If configuration is successfully set.
+ */
+uint32_t DSITX_SetPhyConfig(DSITX_PrivateData* pD, const DSITX_PhyConfig* config)
+{
+ uint32_t regVal;
+ uint32_t status;
+ uint32_t i;
+
+ /* check params */
+ if (DSITX_SetPhyConfigSF(pD, config) != CDN_EOK) {
+ status = CDN_EINVAL;
+ } else {
+ regVal = 0;
+
+ /* build register value */
+ regVal = CPS_FLD_WRITE(DSITX__MCTL_MAIN_PHY_CTL, LANE2_EN, regVal, boolToVal(config->lane2Enabled));
+ regVal = CPS_FLD_WRITE(DSITX__MCTL_MAIN_PHY_CTL, LANE3_EN, regVal, boolToVal(config->lane3Enabled));
+ regVal = CPS_FLD_WRITE(DSITX__MCTL_MAIN_PHY_CTL, LANE4_EN, regVal, boolToVal(config->lane4Enabled));
+ regVal = CPS_FLD_WRITE(DSITX__MCTL_MAIN_PHY_CTL, CLK_CONTINUOUS, regVal, boolToVal(config->laneClkContinous));
+ regVal = CPS_FLD_WRITE(DSITX__MCTL_MAIN_PHY_CTL, CLK_ULPM_EN, regVal, boolToVal(config->laneClkUlpMode));
+
+ /* set fields accordingly to array value */
+ for (i = 0U; i < ((uint32_t)DSITX_MAX_LANE_NUMBER); ++i) {
+ regVal = CPS_FldWrite(phyConfig_defs[i].laneUlpMode_mask, phyConfig_defs[i].laneUlpMode_shift, regVal, boolToVal(config->laneUlpMode[i]));
+ }
+
+ regVal = CPS_FLD_WRITE(DSITX__MCTL_MAIN_PHY_CTL, WAIT_BURST_TIME, regVal, config->waitBurstTime);
+
+ /* write to register */
+ CPS_REG_WRITE(&pD->regBase->mctl_main_phy_ctl, regVal);
+
+ status = CDN_EOK;
+ }
+ return status;
+}
+
+/* internal function */
+static uint32_t setDphyPwrAndRstCtrlPdn(DSITX_DphyPwrRstConfig const *cfg, uint32_t regValue)
+{
+ uint32_t regVal = regValue;
+
+ /* build register value */
+ regVal = CPS_FLD_WRITE(DSITX__MCTL_DPHY_CFG0, DPHY_PLL_PDN, regVal, boolToVal(cfg->dphyPllPdn));
+ regVal = CPS_FLD_WRITE(DSITX__MCTL_DPHY_CFG0, DPHY_CMN_PDN, regVal, boolToVal(cfg->dphyCmnPdn));
+ regVal = CPS_FLD_WRITE(DSITX__MCTL_DPHY_CFG0, DPHY_C_PDN, regVal, boolToVal(cfg->dphyCPdn));
+ regVal = CPS_FLD_WRITE(DSITX__MCTL_DPHY_CFG0, DPHY_D_PDN, regVal, cfg->dphyDPdn);
+
+ return regVal;
+}
+
+/**
+ * Sets the DPHY Power and Reset Control configuration.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] cfg Pointer to structure containing configuration.
+ * @return CDN_EINVAL If pD or cfg is NULL.
+ * @return CDN_EOK On success.
+ */
+uint32_t DSITX_SetDphyPwrAndRstCtrl(DSITX_PrivateData *pD, DSITX_DphyPwrRstConfig const *cfg)
+{
+ uint32_t status = CDN_EOK;
+
+ /* check params */
+ if (DSITX_SetDphyPwrAndRstCtrlSF(pD, cfg) != CDN_EOK) {
+ status = CDN_EINVAL;
+ } else {
+ /* build register value */
+ uint32_t regVal = 0;
+ regVal = setDphyPwrAndRstCtrlPdn(cfg, regVal);
+ regVal = CPS_FLD_WRITE(DSITX__MCTL_DPHY_CFG0, DPHY_C_RSTB, regVal, boolToVal(cfg->dphyCRstb));
+ regVal = CPS_FLD_WRITE(DSITX__MCTL_DPHY_CFG0, DPHY_D_RSTB, regVal, cfg->dphyDRstb);
+ regVal = CPS_FLD_WRITE(DSITX__MCTL_DPHY_CFG0, DPHY_PLL_PSO, regVal, boolToVal(cfg->dphyPllPso));
+ regVal = CPS_FLD_WRITE(DSITX__MCTL_DPHY_CFG0, DPHY_CMN_PSO, regVal, boolToVal(cfg->dphyCmnPso));
+ /* write to register */
+ CPS_REG_WRITE(&pD->regBase->mctl_dphy_cfg0, regVal);
+ }
+ return status;
+}
+
+/**
+ * Obtains the DPHY Power and Reset Control configuration.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] cfg Pointer to structure to which DPHY Power and Reset Control
+ * configuration will be written.
+ * @return CDN_EINVAL If pD or cfg is NULL.
+ * @return CDN_EOK On success.
+ */
+uint32_t DSITX_GetDphyPwrAndRstCtrl(DSITX_PrivateData *pD, DSITX_DphyPwrRstConfig *cfg)
+{
+
+ uint32_t status = CDN_EOK;
+
+ /* check params */
+ if (DSITX_GetDphyPwrAndRstCtrlSF(pD, cfg) != CDN_EOK) {
+ status = CDN_EINVAL;
+ } else {
+ /* read register */
+ uint32_t regVal = CPS_REG_READ(&pD->regBase->mctl_dphy_cfg0);
+ /* extract fields */
+ cfg->dphyCRstb = valToBool(CPS_FLD_READ(DSITX__MCTL_DPHY_CFG0, DPHY_C_RSTB, regVal));
+ cfg->dphyDRstb = (uint8_t) CPS_FLD_READ(DSITX__MCTL_DPHY_CFG0, DPHY_D_RSTB, regVal);
+ cfg->dphyPllPdn = valToBool(CPS_FLD_READ(DSITX__MCTL_DPHY_CFG0, DPHY_PLL_PDN, regVal));
+ cfg->dphyCmnPdn = valToBool(CPS_FLD_READ(DSITX__MCTL_DPHY_CFG0, DPHY_CMN_PDN, regVal));
+ cfg->dphyCPdn = valToBool(CPS_FLD_READ(DSITX__MCTL_DPHY_CFG0, DPHY_C_PDN, regVal));
+ cfg->dphyDPdn = (uint8_t) CPS_FLD_READ(DSITX__MCTL_DPHY_CFG0, DPHY_D_PDN, regVal);
+ cfg->dphyPllPso = valToBool(CPS_FLD_READ(DSITX__MCTL_DPHY_CFG0, DPHY_PLL_PSO, regVal));
+ cfg->dphyCmnPso = valToBool(CPS_FLD_READ(DSITX__MCTL_DPHY_CFG0, DPHY_CMN_PSO, regVal));
+ }
+ return status;
+}
+
+/* internal function */
+static uint32_t setInitialConfiguration( DSITX_PrivateData* pD, const DSITX_Config* config)
+{
+ uint32_t result = CDN_EOK;
+ /* reg base is taken from config */
+ DSITX_Regs* regBase = config->regBase;
+
+ /* set given params */
+ pD->regBase = regBase;
+ pD->numOfLanes = config->numOfLanes;
+ pD->interruptsEnabled = false;
+ pD->processingDcr = false;
+ pD->dcr = NULL;
+
+ /* disable callbacks */
+ pD->fnDcrEventCallback = config->dirCmdEventHandler;
+ pD->fnInitDispCallback = config->initDisplay;
+ pD->fnDsiLinkCallback = NULL;
+ pD->fnCmdModeCallback = NULL;
+ pD->fnVidModeCallback = NULL;
+ pD->fnTvgCallback = NULL;
+ pD->fnDphyErrCallback = NULL;
+
+ /* set default statuses */
+ pD->enDsiLinkStsBits = (uint32_t)DSITX_LINK_STATUS_BITS_INIT;
+ pD->enCmdModeStsBits = (uint32_t)DSITX_CMD_MODE_STATUS_BITS_INIT;
+ pD->enVidModeStsBits = (uint32_t)DSITX_VID_MODE_STATUS_BITS_INIT;
+ pD->enTvgStsBits = (uint32_t)DSITX_TVG_STATUS_BITS_INIT;
+ pD->enDphyErrBits = (uint32_t)DSITX_DPHY_ERROR_BITS_INIT;
+
+ /* Disable all interrupts */
+ CPS_REG_WRITE(®Base->mctl_main_sts_ctl, 0);
+ CPS_REG_WRITE(®Base->cmd_mode_sts_ctl, 0);
+ CPS_REG_WRITE(®Base->direct_cmd_sts_ctl, 0);
+ CPS_REG_WRITE(®Base->direct_cmd_rd_sts_ctl, 0);
+ CPS_REG_WRITE(®Base->vid_mode_sts_ctl, 0);
+ CPS_REG_WRITE(®Base->tvg_sts_ctl, 0);
+ CPS_REG_WRITE(®Base->mctl_dphy_err_ctl1, 0);
+ CPS_REG_WRITE(®Base->mctl_dphy_err_ctl2, 0);
+
+ return result;
+}
+
+/* internal function */
+static uint32_t initializeDisplay(DSITX_PrivateData* pD)
+{
+ uint32_t result = CDN_EOK;
+
+ if (pD->fnInitDispCallback != NULL) {
+ result = pD->fnInitDispCallback(pD); /* Let client app initialize Display */
+ }
+
+ return result;
+}
+
+/* internal function */
+static inline uint32_t getLanesReadyMask(const DSITX_PrivateData* pD)
+{
+ /* data lanes + clk lane */
+ uint8_t numOfLanes = pD->numOfLanes + 1U;
+ uint8_t i;
+ uint32_t lanesMask = 0U;
+
+ const uint32_t lanesReadyMasks[] = {
+ DSITX__MCTL_MAIN_STS__CLKLANE_READY_MASK,
+ DSITX__MCTL_MAIN_STS__DAT1_READY_MASK,
+ DSITX__MCTL_MAIN_STS__DAT2_READY_MASK,
+ DSITX__MCTL_MAIN_STS__DAT3_READY_MASK,
+ DSITX__MCTL_MAIN_STS__DAT4_READY_MASK
+ };
+
+ for (i = 0U; i < numOfLanes; ++i) {
+ lanesMask |= lanesReadyMasks[i];
+ }
+
+ return lanesMask;
+}
+
+/**
+ * Checks if lanes are ready.
+ * @param[in] pD Pointer to driver's private data object.
+ * @param[in] repeatCount status checking repeat count
+ * @return CDN_EINVAL If pD is NULL.
+ * @return CDN_EIO when lanes are not ready.
+ * @return CDN_EOK On success.
+ */
+uint32_t DSITX_CheckLanesState(const DSITX_PrivateData* pD, uint32_t repeatCount)
+{
+ uint32_t result = CDN_EOK;
+ uint32_t regValue;
+
+ if (DSITX_CheckLanesStateSF(pD) != CDN_EOK) {
+ result = CDN_EINVAL;
+ } else {
+ uint32_t repeatCountValue = repeatCount;
+ uint32_t lanesMask = getLanesReadyMask(pD);
+ do {
+ regValue = CPS_REG_READ(&pD->regBase->mctl_main_sts);
+ --repeatCountValue;
+ } while (((regValue & lanesMask) != lanesMask) && (repeatCountValue > 0U));
+
+ if (repeatCountValue == 0U) {
+ /* Lanes not ready */
+ result = CDN_EIO;
+ }
+ }
+ return result;
+}
+
+/**
+ * Waits for PLL lock event.
+ * @param[in] pD Pointer to driver's private data object.
+ * @param[in] repeatCount status checking repeat count
+ * @return CDN_EINVAL If pD is NULL.
+ * @return CDN_EIO when timeout occurs.
+ * @return CDN_EOK On success.
+ */
+uint32_t DSITX_WaitForPllLock(const DSITX_PrivateData* pD, uint32_t repeatCount)
+{
+ uint32_t result = CDN_EOK;
+ uint32_t regVal;
+
+ /* check params */
+ if (DSITX_WaitForPllLockSF(pD) != CDN_EOK) {
+ result = CDN_EINVAL;
+ } else {
+ uint32_t repeatCountValue = repeatCount;
+
+ /* wait for bit PLL_LCK */
+ do {
+ regVal = CPS_REG_READ(&pD->regBase->mctl_main_sts);
+ --repeatCountValue;
+ } while (((CPS_FLD_READ(DSITX__MCTL_MAIN_STS, PLL_LCK, regVal)) == (0U)) && ((repeatCountValue) > (0U)));
+
+ /* mark timeout */
+ if (repeatCountValue == 0U) {
+ result = CDN_EIO;
+ }
+ }
+ return result;
+ }
+
+/**
+ * Initializes the Driver and the DSITX Host as specified in the
+ * config structure.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] config Specifies driver/hardware configuration.
+ * @return CDN_EOK On success
+ * @return CDN_EINVAL If illegal/inconsistent values in 'config' doesn't support feature(s) required by 'config' parameters.
+ */
+uint32_t DSITX_Init(DSITX_PrivateData* pD, const DSITX_Config* config)
+{
+ uint32_t result = CDN_EOK;
+
+ /* check params */
+ if (DSITX_InitSF(pD, config) != CDN_EOK) {
+ result = CDN_EINVAL;
+ } else {
+ result = setInitialConfiguration(pD, config);
+ }
+
+ /* get configuration of IP */
+ if (result == CDN_EOK) {
+ result = DSITX_GetIpConf(pD, &pD->ip);
+ }
+
+ /* initialize display subsystem */
+ if (result == CDN_EOK) {
+ result = initializeDisplay(pD);
+ }
+
+ return result;
+}
+
+/* internal function */
+static void isrMctl(DSITX_PrivateData* pD)
+{
+ uint32_t flagRegVal = CPS_REG_READ(&pD->regBase->mctl_main_sts_flag);
+
+ if ((pD->fnDsiLinkCallback != NULL) && (flagRegVal != 0U)) {
+ if ((flagRegVal & pD->enDsiLinkStsBits)!= 0U) {
+ pD->fnDsiLinkCallback(pD, flagRegVal);
+ }
+ }
+
+ CPS_REG_WRITE(&pD->regBase->mctl_main_sts_clr, flagRegVal);
+}
+
+/* internal function */
+static void isrCommandMode(DSITX_PrivateData* pD, uint32_t flagRegVal)
+{
+ if (pD->fnCmdModeCallback != NULL) {
+ if ((flagRegVal & pD->enCmdModeStsBits) != 0U) {
+ pD->fnCmdModeCallback(pD, flagRegVal);
+ }
+ }
+
+ CPS_REG_WRITE(&pD->regBase->cmd_mode_sts_clr, flagRegVal);
+}
+
+/* internal function */
+static void isrVideoMode(DSITX_PrivateData* pD)
+{
+ uint32_t flagRegVal = CPS_REG_READ(&pD->regBase->vid_mode_sts_flag);
+
+ if ((pD->fnVidModeCallback != NULL) && (flagRegVal != 0U)) {
+ if ((flagRegVal & pD->enVidModeStsBits) != 0U) {
+ pD->fnVidModeCallback(pD, flagRegVal);
+ }
+ }
+ CPS_REG_WRITE(&pD->regBase->vid_mode_sts_clr, flagRegVal);
+}
+
+/* internal function */
+static void isrTvg(DSITX_PrivateData* pD)
+{
+ uint32_t flagRegVal = CPS_REG_READ(&pD->regBase->tg_sts_flag);
+
+ if ((pD->fnTvgCallback != NULL) && (flagRegVal != 0U)) {
+ if ((flagRegVal & pD->enTvgStsBits) != 0U) {
+ pD->fnTvgCallback(pD, flagRegVal);
+ }
+ }
+ CPS_REG_WRITE(&pD->regBase->tg_sts_clr, flagRegVal);
+}
+
+/* internal function */
+static void isrDphy(DSITX_PrivateData* pD)
+{
+ uint32_t flagRegVal = CPS_REG_READ(&pD->regBase->mctl_dphy_err_flag);
+
+ if ((pD->fnDphyErrCallback != NULL) && (flagRegVal != 0U)) {
+ if ((flagRegVal & pD->enDphyErrBits) != 0U) {
+ pD->fnDphyErrCallback(pD, flagRegVal);
+ }
+ }
+ CPS_REG_WRITE(&pD->regBase->mctl_dphy_err_clr, flagRegVal);
+}
+
+/* internal function */
+static void isrDpi(DSITX_PrivateData* pD)
+{
+ uint32_t flagRegVal = CPS_REG_READ(&pD->regBase->dpi_irq_sts);
+
+ if ((pD->fnDpiCallback != NULL) && (flagRegVal != 0U)) {
+ if ((flagRegVal & pD->enDpiStsBits) != 0U) {
+ pD->fnDpiCallback(pD, flagRegVal);
+ }
+ }
+ CPS_REG_WRITE(&pD->regBase->dpi_irq_clr, flagRegVal);
+}
+
+/* internal function */
+static bool canProcessDcr(const DSITX_PrivateData* pD, const uint8_t cmdInt)
+{
+ return ((cmdInt != 0U)
+ && (pD->dcr != NULL)
+ && (pD->dcr->wait == false)
+ && (pD->fnDcrEventCallback != NULL));
+}
+
+/* internal function */
+static uint8_t isrProcessDcrInt(DSITX_PrivateData* pD)
+{
+ uint8_t cmdInt = 0;
+ uint32_t flagRegVal = 0;
+
+ DSITX_Regs* regBase = pD->regBase;
+ flagRegVal = CPS_REG_READ(®Base->cmd_mode_sts_flag);
+ if (flagRegVal != 0U) {
+ isrCommandMode(pD, flagRegVal);
+ }
+
+ flagRegVal = CPS_REG_READ(®Base->direct_cmd_sts_flag);
+ if (flagRegVal != 0U) {
+ /* Direct Command Interrupt */
+ cmdInt = 1;
+ }
+
+ flagRegVal = CPS_REG_READ(®Base->direct_cmd_rd_sts_flag);
+ if (flagRegVal != 0U) {
+ /* Direct Command Read Interrupt */
+ cmdInt = 1;
+ }
+
+ return (cmdInt);
+}
+
+/* internal function */
+static inline void isrProcessDcrCheck(DSITX_PrivateData* pD)
+{
+ if (pD->fnDcrEventCallback(pD, pD->dcr) == DSITX_DCR_RESULT_FINISHED) {
+ pD->processingDcr = false;
+ CPS_REG_WRITE(&pD->regBase->direct_cmd_sts_ctl, 0);
+ CPS_REG_WRITE(&pD->regBase->direct_cmd_rd_sts_ctl, 0);
+ }
+}
+
+/* internal function */
+static void isrProcessDcr(DSITX_PrivateData* pD)
+{
+ const uint8_t cmdInt = isrProcessDcrInt(pD);
+
+ if (canProcessDcr(pD, cmdInt)) {
+ DSITX_DirectCommandRequest *dcr = pD->dcr;
+
+ uint32_t regVal = CPS_REG_READ(&pD->regBase->direct_cmd_sts);
+ dcr->status = regVal & dcr->enEvents;
+
+ regVal = CPS_REG_READ(&pD->regBase->direct_cmd_rd_sts);
+ dcr->rdStatus = regVal & dcr->enRdEvents;
+
+ dcr->ackVal = (uint16_t)CPS_FLD_READ(DSITX__DIRECT_CMD_STS, ACK_VAL, dcr->status);
+ /* Remove ACK value from status bits; may be removed in case of performance drop */
+ dcr->status = dcr->status & (~DSITX__DIRECT_CMD_STS__ACK_VAL_MASK);
+
+ if (dcr->type == DSITX_DCR_TYPE_READ) {
+ /* erros connected to read should be handled using status registers */
+ (void)readDCRData(pD, dcr);
+ }
+
+ isrProcessDcrCheck(pD);
+ }
+}
+
+/**
+ * Driver ISR. Platform-specific code is responsible for ensuring this
+ * gets called when the corresponding hardware's interrupt is
+ * asserted. Registering the ISR should be done after calling init,
+ * and before calling start. The driver's ISR will not attempt to lock
+ * any locks, but will perform client callbacks. If the client wishes
+ * to defer processing to non-interrupt time, it is responsible for
+ * doing so. This function must not be called after calling destroy
+ * and releasing private data memory.
+ * @param[in] pD Driver instance data filled by init.
+ */
+void DSITX_Isr(DSITX_PrivateData* pD)
+{
+ /* check params */
+ if ( (DSITX_IsrSF(pD) == CDN_EOK) &&
+ (pD->interruptsEnabled != 0U) ) {
+ /* call interrupts for each group of features */
+ isrProcessDcr(pD);
+ isrMctl(pD);
+ isrVideoMode(pD);
+ isrTvg(pD);
+ isrDphy(pD);
+ isrDpi(pD);
+ }
+}
+
+/**
+ * DSITX_Start function declaration.
+ * See start function of the DSITX_OBJ structure documentation for details.
+ */
+void DSITX_Start(DSITX_PrivateData* pD)
+{
+ /* check params */
+ if (DSITX_StartSF(pD) == CDN_EOK) {
+ pD->interruptsEnabled = 1;
+ }
+}
+
+/**
+ * DSITX_Stop function declaration.
+ * See stop function of the DSITX_OBJ structure documentation for details.
+ */
+void DSITX_Stop(DSITX_PrivateData* pD)
+{
+ /* check params */
+ if (DSITX_StopSF(pD) == CDN_EOK) {
+ pD->interruptsEnabled = 0;
+ }
+}
+
+/**
+ * DSITX_Destroy function declaration.
+ * See destroy function of the DSITX_OBJ structure documentation for details.
+ */
+void DSITX_Destroy(DSITX_PrivateData* pD)
+{
+ /* check params */
+ if (DSITX_DestroySF(pD) == CDN_EOK) {
+ DSITX_Stop(pD);
+ }
+}
+
+/**
+ * Sets DPHY configuration.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] config Pointer to structure which specifies DPHY configuration.
+ * @return CDN_EINVAL If pD or config is NULL.
+ * @return CDN_EOK If configuration is successfully set.
+ */
+uint32_t DSITX_SetDphyConfig(const DSITX_PrivateData* pD, const DSITX_DphyConfig* config)
+{
+ uint32_t regVal;
+ uint32_t status;
+
+ /* check params */
+ if (DSITX_SetDphyConfigSF(pD, config) != CDN_EOK) {
+ status = CDN_EINVAL;
+ } else {
+ /* write timing/timeout settings */
+ regVal = 0U;
+ DSITX_Regs* regBase = pD->regBase;
+ regVal = CPS_FLD_WRITE(DSITX__MCTL_DPHY_TIMEOUT1, CLK_DIV, regVal, config->clkDivisionRatio);
+ regVal = CPS_FLD_WRITE(DSITX__MCTL_DPHY_TIMEOUT1, HSTX_TO_VAL, regVal, config->hstxTimeout);
+ CPS_REG_WRITE(®Base->mctl_dphy_timeout1, regVal);
+
+ regVal = 0;
+ regVal = CPS_FLD_WRITE(DSITX__MCTL_DPHY_TIMEOUT2, LPRX_TO_VAL, regVal, config->lprxTimeout);
+ CPS_REG_WRITE(®Base->mctl_dphy_timeout2, regVal);
+
+ /* DSITX_UlpTimeout Structure that specify time to leave ULP mode. */
+ regVal = 0;
+ regVal = CPS_FLD_WRITE(DSITX__MCTL_ULPOUT_TIME, CKLANE_ULPOUT_TIME, regVal, config->clkLaneUlpTimeout);
+ regVal = CPS_FLD_WRITE(DSITX__MCTL_ULPOUT_TIME, DATA_ULPOUT_TIME, regVal, config->dataLaneUlpTimeout);
+ CPS_REG_WRITE(®Base->mctl_ulpout_time, regVal);
+
+ status = CDN_EOK;
+ }
+ return status;
+}
+
+/**
+ * Obtains DPHY configuration.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] config Pointer to structure to which DPHY configuration will be written.
+ * @return CDN_EINVAL If pD or config is NULL.
+ * @return CDN_EOK If configuration is successfully obtained.
+ */
+uint32_t DSITX_GetDphyConfig(DSITX_PrivateData* pD, DSITX_DphyConfig* config)
+{
+ uint32_t regVal;
+ uint32_t status;
+
+ /* check params */
+ if (DSITX_GetDphyConfigSF(pD, config) != CDN_EOK) {
+ status = CDN_EINVAL;
+ } else {
+ /* read timing/clock settings */
+ regVal = CPS_REG_READ(&pD->regBase->mctl_dphy_timeout1);
+ config->clkDivisionRatio = (uint8_t)CPS_FLD_READ(DSITX__MCTL_DPHY_TIMEOUT1, CLK_DIV, regVal);
+ config->hstxTimeout = (uint32_t)CPS_FLD_READ(DSITX__MCTL_DPHY_TIMEOUT1, HSTX_TO_VAL, regVal);
+
+ regVal = CPS_REG_READ(&pD->regBase->mctl_dphy_timeout2);
+ config->lprxTimeout = (uint32_t)CPS_FLD_READ(DSITX__MCTL_DPHY_TIMEOUT2, LPRX_TO_VAL, regVal);
+
+ regVal = CPS_REG_READ(&pD->regBase->mctl_ulpout_time);
+ config->clkLaneUlpTimeout = (uint16_t)CPS_FLD_READ(DSITX__MCTL_ULPOUT_TIME, CKLANE_ULPOUT_TIME, regVal);
+ config->dataLaneUlpTimeout = (uint16_t)CPS_FLD_READ(DSITX__MCTL_ULPOUT_TIME, DATA_ULPOUT_TIME, regVal);
+
+ status = CDN_EOK;
+ }
+ return status;
+}
+
+/* internal function */
+static inline void getDataPathConfigTe(DSITX_DataPathConfig* config, uint32_t regValue)
+{
+ uint32_t regVal = regValue;
+
+ config->teHwPolling = valToBool(CPS_FLD_READ(DSITX__MCTL_MAIN_DATA_CTL, TE_HW_POLLING_EN, regVal));
+ config->teMipiPolling = valToBool(CPS_FLD_READ(DSITX__MCTL_MAIN_DATA_CTL, TE_MIPI_POLLING_EN, regVal));
+ config->if1TeEnabled = valToBool(CPS_FLD_READ(DSITX__MCTL_MAIN_DATA_CTL, IF1_TE_EN, regVal));
+ config->regTeEnabled = valToBool(CPS_FLD_READ(DSITX__MCTL_MAIN_DATA_CTL, REG_TE_EN, regVal));
+}
+
+/* internal function */
+static inline void getDataPathConfigDisp(DSITX_DataPathConfig* config, uint32_t regValue)
+{
+ uint32_t regVal = regValue;
+
+ config->dispGenEcc = valToBool(CPS_FLD_READ(DSITX__MCTL_MAIN_DATA_CTL, DISP_GEN_ECC, regVal));
+ config->dispGenChecksum = valToBool(CPS_FLD_READ(DSITX__MCTL_MAIN_DATA_CTL, DISP_GEN_CHECKSUM, regVal));
+ config->dispEotGen = valToBool(CPS_FLD_READ(DSITX__MCTL_MAIN_DATA_CTL, DISP_EOT_GEN, regVal));
+}
+
+/* internal function */
+static uint32_t getDataPathConfigVid(DSITX_DataPathConfig* config, uint32_t regValue)
+{
+ uint32_t status;
+
+ status = getInterfaceModeEnum(CPS_FLD_READ(DSITX__MCTL_MAIN_DATA_CTL, SDI_IF_VID_MODE, regValue), &config->interfaceMode);
+ status |= getVideoIfSelectEnum(CPS_FLD_READ(DSITX__MCTL_MAIN_DATA_CTL, VID_IF_SELECT, regValue), &config->videoIfSelect);
+ config->videoStreamGenEnabled = valToBool(CPS_FLD_READ(DSITX__MCTL_MAIN_DATA_CTL, VID_EN, regValue));
+
+ return status;
+}
+
+/**
+ * Obtains Data Path configuration.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] config Pointer to structure to which Data Path configuration will be written.
+ * @return CDN_EINVAL If pD or config is NULL.
+ * @return CDN_EOK If configuration is successfully obtained.
+ */
+uint32_t DSITX_GetDataPathConfig(DSITX_PrivateData* pD, DSITX_DataPathConfig* config)
+{
+ uint32_t regVal;
+ uint32_t status = CDN_EOK;
+
+ /* check params */
+ if (DSITX_GetDataPathConfigSF(pD, config) != CDN_EOK) {
+ status = CDN_EINVAL;
+ } else {
+ /* read value from register */
+ regVal = CPS_REG_READ(&pD->regBase->mctl_main_data_ctl);
+
+ /* call helper functions */
+ status = getDataPathConfigVid(config, regVal);
+ getDataPathConfigTe(config, regVal);
+ getDataPathConfigDisp(config, regVal);
+
+ /* extract fields from value */
+ config->linkEnabled = valToBool(CPS_FLD_READ(DSITX__MCTL_MAIN_DATA_CTL, LINK_EN, regVal));
+ config->tvgEnabled = valToBool(CPS_FLD_READ(DSITX__MCTL_MAIN_DATA_CTL, TVG_SEL, regVal));
+ config->readOpEnabled = valToBool(CPS_FLD_READ(DSITX__MCTL_MAIN_DATA_CTL, READ_EN, regVal));
+ config->btaEnabled = valToBool(CPS_FLD_READ(DSITX__MCTL_MAIN_DATA_CTL, BTA_EN, regVal));
+ config->hostEotGen = valToBool(CPS_FLD_READ(DSITX__MCTL_MAIN_DATA_CTL, HOST_EOT_GEN, regVal));
+ }
+ return status;
+}
+
+/**
+ * Obtains PHY configuration.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] config Pointer to structure to which PHY configuration will be written.
+ * @return CDN_EINVAL If pD or config is NULL.
+ * @return CDN_EOK If configuration is successfully obtained.
+ */
+uint32_t DSITX_GetPhyConfig(DSITX_PrivateData* pD, DSITX_PhyConfig* config)
+{
+ uint32_t regVal;
+ uint32_t status;
+ uint32_t i;
+
+ /* check params */
+ if (DSITX_GetPhyConfigSF(pD, config) != CDN_EOK) {
+ status = CDN_EINVAL;
+ } else {
+ /* read register and split it to fields */
+ regVal = CPS_REG_READ(&pD->regBase->mctl_main_phy_ctl);
+ config->lane2Enabled = valToBool(CPS_FLD_READ(DSITX__MCTL_MAIN_PHY_CTL, LANE2_EN, regVal));
+ config->lane3Enabled = valToBool(CPS_FLD_READ(DSITX__MCTL_MAIN_PHY_CTL, LANE3_EN, regVal));
+ config->lane4Enabled = valToBool(CPS_FLD_READ(DSITX__MCTL_MAIN_PHY_CTL, LANE4_EN, regVal));
+ config->laneClkContinous = valToBool(CPS_FLD_READ(DSITX__MCTL_MAIN_PHY_CTL, CLK_CONTINUOUS, regVal));
+ config->laneClkUlpMode = valToBool(CPS_FLD_READ(DSITX__MCTL_MAIN_PHY_CTL, CLK_ULPM_EN, regVal));
+
+ /* convert lane ulp mode from register value to array */
+ for (i = 0U; i < ((uint32_t)DSITX_MAX_LANE_NUMBER); ++i) {
+ config->laneUlpMode[i] = valToBool(CPS_FldRead(phyConfig_defs[i].laneUlpMode_mask, phyConfig_defs[i].laneUlpMode_shift, regVal));
+ }
+
+ config->waitBurstTime = (uint8_t)(CPS_FLD_READ(DSITX__MCTL_MAIN_PHY_CTL, WAIT_BURST_TIME, regVal));
+
+ status = CDN_EOK;
+ }
+ return status;
+}
+
+/* internal function */
+static void setCommandModeCtl(DSITX_PrivateData* pD, const DSITX_CommandModeSettings* cmdMode)
+{
+ uint32_t regVal = 0U;
+
+ /* build write value */
+ regVal = CPS_FLD_WRITE(DSITX__CMD_MODE_CTL, IF1_ID, regVal, cmdMode->vcIdIf1);
+ regVal = CPS_FLD_WRITE(DSITX__CMD_MODE_CTL, IF3_ID, regVal, cmdMode->vcIdIf3);
+ regVal = CPS_FLD_WRITE(DSITX__CMD_MODE_CTL, IF1_LP_EN, regVal, boolToVal(cmdMode->sendFromInt1InLp));
+ regVal = CPS_FLD_WRITE(DSITX__CMD_MODE_CTL, IF3_LP_EN, regVal, boolToVal(cmdMode->sendFromInt3InLp));
+ CPS_REG_WRITE(&pD->regBase->cmd_mode_ctl, regVal);
+}
+
+/* internal function */
+static void setCommandModeCtl2(DSITX_PrivateData* pD, const DSITX_CommandModeSettings* cmdMode)
+{
+ uint32_t regVal = 0U;
+
+ /* build write value */
+ regVal = CPS_FLD_WRITE(DSITX__CMD_MODE_CTL2, ARB_MODE, regVal, (uint32_t)cmdMode->arbMode);
+ regVal = CPS_FLD_WRITE(DSITX__CMD_MODE_CTL2, ARB_PRI, regVal, (uint32_t)cmdMode->arbPriority);
+ regVal = CPS_FLD_WRITE(DSITX__CMD_MODE_CTL2, FIL_VALUE, regVal, cmdMode->fillValue);
+ regVal = CPS_FLD_WRITE(DSITX__CMD_MODE_CTL2, TE_TIMEOUT, regVal, cmdMode->teTimeout);
+ CPS_REG_WRITE(&pD->regBase->cmd_mode_ctl2, regVal);
+}
+
+/**
+ * Sets Command Mode configuration.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] cmdMode Pointer to structure containing detailed information about
+ * Command Mode configuration.
+ * @return CDN_EINVAL If cmdMode contains invalid values.
+ * @return CDN_EOK On success.
+ */
+uint32_t DSITX_SetCommandMode(DSITX_PrivateData* pD, const DSITX_CommandModeSettings* cmdMode)
+{
+ uint32_t status;
+
+ /* check params */
+ if (DSITX_SetCommandModeSF(pD, cmdMode) != CDN_EOK) {
+ status = CDN_EINVAL;
+ } else {
+ setCommandModeCtl(pD, cmdMode);
+ setCommandModeCtl2(pD, cmdMode);
+
+ status = CDN_EOK;
+ }
+ return status;
+}
+
+/**
+ * Reads Command Mode configuration.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] cmdMode Pointer to structure to which detailed information about
+ * Command Mode configuration will be written.
+ * @return CDN_EINVAL If pD or cmdMode is NULL.
+ * @return CDN_EOK On success.
+ */
+uint32_t DSITX_GetCommandMode(DSITX_PrivateData* pD, DSITX_CommandModeSettings* cmdMode)
+{
+ uint32_t regVal;
+ uint32_t status;
+
+ /* check params */
+ if (DSITX_GetCommandModeSF(pD, cmdMode) != CDN_EOK) {
+ status = CDN_EINVAL;
+ } else {
+ /* read register */
+ regVal = CPS_REG_READ(&pD->regBase->cmd_mode_ctl);
+ /* extract fields */
+ cmdMode->vcIdIf1 = (uint8_t)CPS_FLD_READ(DSITX__CMD_MODE_CTL, IF1_ID, regVal);
+ cmdMode->vcIdIf3 = (uint8_t)CPS_FLD_READ(DSITX__CMD_MODE_CTL, IF3_ID, regVal);
+ cmdMode->sendFromInt1InLp = valToBool(CPS_FLD_READ(DSITX__CMD_MODE_CTL, IF1_LP_EN, regVal));
+ cmdMode->sendFromInt3InLp = valToBool(CPS_FLD_READ(DSITX__CMD_MODE_CTL, IF3_LP_EN, regVal));
+
+ /* read register */
+ regVal = CPS_REG_READ(&pD->regBase->cmd_mode_ctl2);
+ /* extract fields */
+ status = getCommandArbitrationModeEnum(CPS_FLD_READ(DSITX__CMD_MODE_CTL2, ARB_MODE, regVal), &cmdMode->arbMode);
+ status |= getCmdArbitrationPriorityEnum(CPS_FLD_READ(DSITX__CMD_MODE_CTL2, ARB_PRI, regVal), &cmdMode->arbPriority);
+ cmdMode->fillValue = (uint8_t)CPS_FLD_READ(DSITX__CMD_MODE_CTL2, FIL_VALUE, regVal);
+ cmdMode->teTimeout = (uint16_t)CPS_FLD_READ(DSITX__CMD_MODE_CTL2, TE_TIMEOUT, regVal);
+ }
+ return status;
+}
+
+/* internal function */
+static uint32_t setVideoModeMainCtl1(const DSITX_VideoModeSettings* vidMode, uint32_t regValue)
+{
+ uint32_t regVal = regValue;
+
+ /* build value for register */
+ regVal = CPS_FLD_WRITE(DSITX__VID_MAIN_CTL, START_MODE, regVal, vidMode->startMode);
+ regVal = CPS_FLD_WRITE(DSITX__VID_MAIN_CTL, STOP_MODE, regVal, vidMode->stopMode);
+ regVal = CPS_FLD_WRITE(DSITX__VID_MAIN_CTL, VID_ID, regVal, vidMode->vidId);
+ regVal = CPS_FLD_WRITE(DSITX__VID_MAIN_CTL, VID_ID_SDFD, regVal, vidMode->vidIdSdfd);
+ regVal = CPS_FLD_WRITE(DSITX__VID_MAIN_CTL, VID_PIXEL_MODE, regVal, vidMode->vidPixelMode);
+ regVal = CPS_FLD_WRITE(DSITX__VID_MAIN_CTL, BURST_MODE, regVal, boolToVal(vidMode->burstMode));
+ regVal = CPS_FLD_WRITE(DSITX__VID_MAIN_CTL, SYNC_PULSE_ACTIVE, regVal, boolToVal(vidMode->syncPulseActive));
+
+ return regVal;
+}
+
+/* internal function */
+static uint32_t setVideoModeMainCtl2(const DSITX_VideoModeSettings* vidMode, uint32_t regValue)
+{
+ uint32_t regVal = regValue;
+
+ /* build value for register */
+ regVal = CPS_FLD_WRITE(DSITX__VID_MAIN_CTL, SYNC_PULSE_HORIZONTAL, regVal, boolToVal(vidMode->syncPulseHorizontal));
+ regVal = CPS_FLD_WRITE(DSITX__VID_MAIN_CTL, REG_BLKLINE_MODE, regVal, vidMode->blkLineMode);
+ regVal = CPS_FLD_WRITE(DSITX__VID_MAIN_CTL, REG_BLKEOL_MODE, regVal, vidMode->blkEolMode);
+ regVal = CPS_FLD_WRITE(DSITX__VID_MAIN_CTL, RECOVERY_MODE, regVal, vidMode->recoveryMode);
+ regVal = CPS_FLD_WRITE(DSITX__VID_MAIN_CTL, VID_INTERLACED_EN, regVal, boolToVal(vidMode->interlancedVideoModeEnabled));
+ regVal = CPS_FLD_WRITE(DSITX__VID_MAIN_CTL, VID_FIELD_SW, regVal, vidMode->fieldSwitch);
+ regVal = CPS_FLD_WRITE(DSITX__VID_MAIN_CTL, HEADER, regVal, vidMode->header);
+ regVal = CPS_FLD_WRITE(DSITX__VID_MAIN_CTL, VID_IGNORE_MISS_VSYNC, regVal, boolToVal(vidMode->ignoreMissVsync));
+
+ return regVal;
+}
+
+/* internal function */
+static void setVideoModeCfgColors(DSITX_Regs* regBase, const DSITX_VideoModeSettings* vidMode)
+{
+ uint32_t regVal = 0U;
+
+ /* set error colors */
+ regVal = CPS_FLD_WRITE(DSITX__VID_ERR_COLOR1, COL_RED, regVal, vidMode->errColor.r);
+ regVal = CPS_FLD_WRITE(DSITX__VID_ERR_COLOR1, COL_GREEN, regVal, vidMode->errColor.g);
+ CPS_REG_WRITE(®Base->vid_err_color1, regVal);
+
+ regVal = 0U;
+ regVal = CPS_FLD_WRITE(DSITX__VID_ERR_COLOR2, COL_BLUE, regVal, vidMode->errColor.b);
+ regVal = CPS_FLD_WRITE(DSITX__VID_ERR_COLOR2, PAD_VALUE, regVal, vidMode->errColor.padValue);
+ CPS_REG_WRITE(®Base->vid_err_color2, regVal);
+}
+
+/* internal function */
+static void setVideoModeCfg(const DSITX_PrivateData* pD, const DSITX_VideoModeSettings* vidMode)
+{
+ uint32_t regVal;
+ DSITX_Regs* regBase = pD->regBase;
+
+ /* write timing parameters */
+ regVal = 0;
+ regVal = CPS_FLD_WRITE(DSITX__VID_PCK_TIME, BLKEOL_DURATION, regVal, vidMode->blkEolDuration);
+ CPS_REG_WRITE(®Base->vid_pck_time, regVal);
+
+ regVal = 0;
+ regVal = CPS_FLD_WRITE(DSITX__VID_DPHY_TIME, REG_WAKEUP_TIME, regVal, vidMode->regWakeupTime);
+ regVal = CPS_FLD_WRITE(DSITX__VID_DPHY_TIME, REG_LINE_DURATION, regVal, vidMode->regLineDuration);
+ CPS_REG_WRITE(®Base->vid_dphy_time, regVal);
+
+ /* set video parameters */
+ regVal = 0U;
+ regVal = setVideoModeMainCtl1(vidMode, regVal);
+ regVal = setVideoModeMainCtl2(vidMode, regVal);
+ CPS_REG_WRITE(®Base->vid_main_ctl, regVal);
+
+ /* set error colors */
+ setVideoModeCfgColors(regBase, vidMode);
+}
+
+/**
+ * Sets Video Mode configuration.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] vidMode Pointer to structure containing Video Mode configuration.
+ * @return CDN_EINVAL If provided configuration contains invalid values.
+ * @return CDN_EOK If configuration is successfully set.
+ */
+uint32_t DSITX_SetVideoMode(const DSITX_PrivateData* pD, const DSITX_VideoModeSettings* vidMode)
+{
+ uint32_t status;
+
+ /* check params */
+ if (DSITX_SetVideoModeSF(pD, vidMode) != CDN_EOK) {
+ status = CDN_EINVAL;
+ } else {
+ /* perform setting */
+ setVideoModeCfg(pD, vidMode);
+ status = CDN_EOK;
+ }
+ return status;
+}
+
+/* internal function */
+static uint32_t getVideoModeMainCtl1(DSITX_VideoModeSettings* vidMode, uint32_t regValue)
+{
+ uint32_t regVal = regValue;
+ uint32_t status;
+
+ /* convert field value to enum */
+ status = getVideoPixelModeEnum(CPS_FLD_READ(DSITX__VID_MAIN_CTL, VID_PIXEL_MODE, regVal), &vidMode->vidPixelMode);
+ status |= getHeaderEnum(CPS_FLD_READ(DSITX__VID_MAIN_CTL, HEADER, regVal), &vidMode->header);
+ status |= getVideoStopModeEnum(CPS_FLD_READ(DSITX__VID_MAIN_CTL, STOP_MODE, regVal), &vidMode->stopMode);
+ status |= getVideoStartModeEnum(CPS_FLD_READ(DSITX__VID_MAIN_CTL, START_MODE, regVal), &vidMode->startMode);
+
+ if (CDN_EOK == status) {
+ /* convert flags to boolean */
+ vidMode->vidId = (uint8_t)CPS_FLD_READ(DSITX__VID_MAIN_CTL, VID_ID, regVal);
+ vidMode->vidIdSdfd = (uint8_t)CPS_FLD_READ(DSITX__VID_MAIN_CTL, VID_ID_SDFD, regVal);
+ vidMode->burstMode = valToBool(CPS_FLD_READ(DSITX__VID_MAIN_CTL, BURST_MODE, regVal));
+ }
+
+ return status;
+}
+
+/* internal function */
+static uint32_t getVideoModeMainCtl2(DSITX_VideoModeSettings* vidMode, uint32_t regValue)
+{
+ uint32_t regVal = regValue;
+ uint32_t status;
+
+ /* convert field value to enum */
+ status = getVideoRecoveryModeEnum(CPS_FLD_READ(DSITX__VID_MAIN_CTL, RECOVERY_MODE, regVal), &vidMode->recoveryMode);
+ status |= getVideoBlankingModeEnum(CPS_FLD_READ(DSITX__VID_MAIN_CTL, REG_BLKLINE_MODE, regVal), &vidMode->blkLineMode);
+ status |= getVideoBlankingModeEnum(CPS_FLD_READ(DSITX__VID_MAIN_CTL, REG_BLKEOL_MODE, regVal), &vidMode->blkEolMode);
+
+ if (CDN_EOK == status) {
+ /* convert flags to boolean */
+ vidMode->syncPulseActive = valToBool(CPS_FLD_READ(DSITX__VID_MAIN_CTL, SYNC_PULSE_ACTIVE, regVal));
+ vidMode->syncPulseHorizontal = valToBool(CPS_FLD_READ(DSITX__VID_MAIN_CTL, SYNC_PULSE_HORIZONTAL, regVal));
+ vidMode->interlancedVideoModeEnabled = valToBool(CPS_FLD_READ(DSITX__VID_MAIN_CTL, VID_INTERLACED_EN, regVal));
+ vidMode->fieldSwitch = (uint8_t)CPS_FLD_READ(DSITX__VID_MAIN_CTL, VID_FIELD_SW, regVal);
+ vidMode->ignoreMissVsync = valToBool(CPS_FLD_READ(DSITX__VID_MAIN_CTL, VID_IGNORE_MISS_VSYNC, regVal));
+ }
+ return status;
+}
+
+/* internal function */
+static void getVideoModeErrColors(DSITX_Regs* regBase, DSITX_VideoModeSettings* vidMode)
+{
+ uint32_t regVal;
+
+ /* read RGB values from registers */
+ regVal = CPS_REG_READ(®Base->vid_err_color1);
+ vidMode->errColor.r = (uint16_t)CPS_FLD_READ(DSITX__VID_ERR_COLOR1, COL_RED, regVal);
+ vidMode->errColor.g = (uint16_t)CPS_FLD_READ(DSITX__VID_ERR_COLOR1, COL_GREEN, regVal);
+
+ regVal = CPS_REG_READ(®Base->vid_err_color2);
+ vidMode->errColor.b = (uint16_t)CPS_FLD_READ(DSITX__VID_ERR_COLOR2, COL_BLUE, regVal);
+ vidMode->errColor.padValue = (uint16_t)CPS_FLD_READ(DSITX__VID_ERR_COLOR2, PAD_VALUE, regVal);
+}
+
+/* internal function */
+static uint32_t getVideoModeCfg(const DSITX_PrivateData* pD, DSITX_VideoModeSettings* vidMode)
+{
+ uint32_t regVal;
+ uint32_t status;
+ DSITX_Regs* regBase = pD->regBase;
+
+ regVal = CPS_REG_READ(&pD->regBase->vid_main_ctl);
+
+ /* get registers */
+ status = getVideoModeMainCtl2(vidMode, regVal);
+ status |= getVideoModeMainCtl1(vidMode, regVal);
+
+ if (CDN_EOK == status) {
+ /* get error colors */
+ getVideoModeErrColors(regBase, vidMode);
+
+ /* get rest parameters */
+ regVal = CPS_REG_READ(®Base->vid_pck_time);
+ vidMode->blkEolDuration = (uint16_t)CPS_FLD_READ(DSITX__VID_PCK_TIME, BLKEOL_DURATION, regVal);
+
+ regVal = CPS_REG_READ(®Base->vid_dphy_time);
+ vidMode->regWakeupTime = (uint16_t)CPS_FLD_READ(DSITX__VID_DPHY_TIME, REG_WAKEUP_TIME, regVal);
+ vidMode->regLineDuration = (uint16_t)CPS_FLD_READ(DSITX__VID_DPHY_TIME, REG_LINE_DURATION, regVal);
+ }
+ return status;
+}
+
+/**
+ * Reads Video Mode configuration.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] vidMode Pointer to structure to which Video Mode configuration will be written.
+ * @return CDN_EINVAL If pD or vidMode is NULL.
+ * @return CDN_EOK If configuration was successfully read.
+ */
+uint32_t DSITX_GetVideoMode(const DSITX_PrivateData* pD, DSITX_VideoModeSettings* vidMode)
+{
+ uint32_t status;
+
+ if (DSITX_GetVideoModeSF(pD, vidMode) != CDN_EOK) {
+ status = CDN_EINVAL;
+ } else {
+ status = getVideoModeCfg(pD, vidMode);
+ }
+
+ return status;
+}
+
+/**
+ * Sets Video Command Arbiter configuration.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] vca Pointer to structure containing Video Command Arbiter configuration.
+ * @return CDN_EINVAL If provided configuration contains invalid values.
+ * @return CDN_EOK If configuration is successfully set.
+ */
+uint32_t DSITX_SetVcaConfig(DSITX_PrivateData* pD, const DSITX_VcaConfig* vca)
+{
+ uint32_t regVal;
+ uint32_t status;
+
+ /* check params */
+ if (DSITX_SetVcaConfigSF(pD, vca) != CDN_EOK) {
+ status = CDN_EINVAL;
+ } else {
+ /* set first register */
+ regVal = 0;
+ regVal = CPS_FLD_WRITE(DSITX__VID_VCA_SETTING1, MAX_BURST_LIMIT, regVal, vca->maxBurstLimit);
+ regVal = CPS_FLD_WRITE(DSITX__VID_VCA_SETTING1, BURST_LP, regVal, boolToVal(vca->burstLp));
+ CPS_REG_WRITE(&pD->regBase->vid_vca_setting1, regVal);
+
+ /* set second register */
+ regVal = 0;
+ regVal = CPS_FLD_WRITE(DSITX__VID_VCA_SETTING2, EXACT_BURST_LIMIT, regVal, vca->exactBurstLimit);
+ regVal = CPS_FLD_WRITE(DSITX__VID_VCA_SETTING2, MAX_LINE_LIMIT, regVal, vca->maxLineLimit);
+ CPS_REG_WRITE(&pD->regBase->vid_vca_setting2, regVal);
+
+ status = CDN_EOK;
+ }
+ return status;
+}
+
+/**
+ * Reads Video Command Arbiter configuration.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] vca Pointer to structure to which Video Command Arbiter configuration will be written.
+ * @return CDN_EINVAL If pD or vca is NULL.
+ * @return CDN_EOK If size is successfully set.
+ */
+uint32_t DSITX_GetVcaConfig(DSITX_PrivateData* pD, DSITX_VcaConfig* vca)
+{
+ uint32_t regVal;
+ uint32_t status;
+
+ /* check params */
+ if (DSITX_GetVcaConfigSF(pD, vca) != CDN_EOK) {
+ status = CDN_EINVAL;
+ } else {
+ /* read first register */
+ regVal = CPS_REG_READ(&pD->regBase->vid_vca_setting1);
+ vca->maxBurstLimit = (uint16_t)CPS_FLD_READ(DSITX__VID_VCA_SETTING1, MAX_BURST_LIMIT, regVal);
+ vca->burstLp = valToBool(CPS_FLD_READ(DSITX__VID_VCA_SETTING1, BURST_LP, regVal));
+
+ /* read second register */
+ regVal = CPS_REG_READ(&pD->regBase->vid_vca_setting2);
+ vca->exactBurstLimit = (uint16_t)CPS_FLD_READ(DSITX__VID_VCA_SETTING2, EXACT_BURST_LIMIT, regVal);
+ vca->maxLineLimit = (uint16_t)CPS_FLD_READ(DSITX__VID_VCA_SETTING2, MAX_LINE_LIMIT, regVal);
+
+ status = CDN_EOK;
+ }
+ return status;
+}
+
+/* internal function */
+static void setVideoSizeVertical(DSITX_PrivateData* pD, const DSITX_VideoSize* vidSize)
+{
+ uint32_t regVal;
+
+ /* set video vertical parameters */
+ regVal = 0;
+ regVal = CPS_FLD_WRITE(DSITX__VID_VSIZE1, VSA_LENGTH, regVal, vidSize->vsa);
+ regVal = CPS_FLD_WRITE(DSITX__VID_VSIZE1, VBP_LENGTH, regVal, vidSize->vbp);
+ regVal = CPS_FLD_WRITE(DSITX__VID_VSIZE1, VFP_LENGTH, regVal, vidSize->vfp);
+ CPS_REG_WRITE(&pD->regBase->vid_vsize1, regVal);
+
+ regVal = 0;
+ regVal = CPS_FLD_WRITE(DSITX__VID_VSIZE2, VACT_LENGTH, regVal, vidSize->vact);
+ CPS_REG_WRITE(&pD->regBase->vid_vsize2, regVal);
+}
+
+/* internal function */
+static void setVideoSizeHorizontal(DSITX_PrivateData* pD, const DSITX_VideoSize* vidSize)
+{
+ uint32_t regVal;
+
+ /* set video horizontal parameters */
+ regVal = 0;
+ regVal = CPS_FLD_WRITE(DSITX__VID_HSIZE1, HSA_LENGTH, regVal, vidSize->hsa);
+ regVal = CPS_FLD_WRITE(DSITX__VID_HSIZE1, HBP_LENGTH, regVal, vidSize->hbp);
+ CPS_REG_WRITE(&pD->regBase->vid_hsize1, regVal);
+
+ regVal = 0;
+ regVal = CPS_FLD_WRITE(DSITX__VID_HSIZE2, HFP_LENGTH, regVal, vidSize->hfp);
+ regVal = CPS_FLD_WRITE(DSITX__VID_HSIZE2, RGB_SIZE, regVal, vidSize->rgb);
+ CPS_REG_WRITE(&pD->regBase->vid_hsize2, regVal);
+}
+
+/**
+ * Sets Video size configuration.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] vidSize Pointer to structure containing Video Size configuration.
+ * @return CDN_EINVAL If provided configuration contains invalid values.
+ * @return CDN_EOK If configuration is successfully set.
+ */
+uint32_t DSITX_SetVideoSize(DSITX_PrivateData* pD, const DSITX_VideoSize* vidSize)
+{
+ uint32_t regVal;
+ uint32_t status;
+
+ /* check params */
+ if (DSITX_SetVideoSizeSF(pD, vidSize) != CDN_EOK) {
+ status = CDN_EINVAL;
+ } else {
+ /* set size parameters */
+ setVideoSizeVertical(pD, vidSize);
+ setVideoSizeHorizontal(pD, vidSize);
+
+ /* set additional parameters */
+ regVal = 0;
+ regVal = CPS_FLD_WRITE(DSITX__VID_BLKSIZE1, BLKEOL_PCK, regVal, vidSize->blkEolPacket);
+ regVal = CPS_FLD_WRITE(DSITX__VID_BLKSIZE1, BLKLINE_EVENT_PCK, regVal, vidSize->blkLineEventPacket);
+ CPS_REG_WRITE(&pD->regBase->vid_blksize1, regVal);
+
+ regVal = 0;
+ regVal = CPS_FLD_WRITE(DSITX__VID_BLKSIZE2, BLKLINE_PULSE_PCK, regVal, vidSize->blkLinePulsePacket);
+ CPS_REG_WRITE(&pD->regBase->vid_blksize2, regVal);
+
+ status = CDN_EOK;
+ }
+ return status;
+}
+
+/* internal function */
+static void getVideoSizeVertical(DSITX_PrivateData* pD, DSITX_VideoSize* vidSize)
+{
+ uint32_t regVal;
+
+ /* read video vertical parameters */
+ regVal = CPS_REG_READ(&pD->regBase->vid_vsize1);
+ vidSize->vsa = (uint8_t)CPS_FLD_READ(DSITX__VID_VSIZE1, VSA_LENGTH, regVal);
+ vidSize->vbp = (uint8_t)CPS_FLD_READ(DSITX__VID_VSIZE1, VBP_LENGTH, regVal);
+ vidSize->vfp = (uint8_t)CPS_FLD_READ(DSITX__VID_VSIZE1, VFP_LENGTH, regVal);
+
+ regVal = CPS_REG_READ(&pD->regBase->vid_vsize2);
+ vidSize->vact = (uint16_t)CPS_FLD_READ(DSITX__VID_VSIZE2, VACT_LENGTH, regVal);
+}
+
+/* internal function */
+static void getVideoSizeHorizontal(DSITX_PrivateData* pD, DSITX_VideoSize* vidSize)
+{
+ uint32_t regVal;
+
+ /* read video horizontal parameters */
+ regVal = CPS_REG_READ(&pD->regBase->vid_hsize1);
+ vidSize->hsa = (uint16_t)CPS_FLD_READ(DSITX__VID_HSIZE1, HSA_LENGTH, regVal);
+ vidSize->hbp = (uint16_t)CPS_FLD_READ(DSITX__VID_HSIZE1, HBP_LENGTH, regVal);
+
+ regVal = CPS_REG_READ(&pD->regBase->vid_hsize2);
+ vidSize->rgb = (uint16_t)CPS_FLD_READ(DSITX__VID_HSIZE2, RGB_SIZE, regVal);
+ vidSize->hfp = (uint16_t)CPS_FLD_READ(DSITX__VID_HSIZE2, HFP_LENGTH, regVal);
+}
+
+/**
+ * Reads Video size configuration.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] vidSize Pointer to structure to which Video Size configuration will be written.
+ * @return CDN_EINVAL If pD or vidSize is NULL.
+ * @return CDN_EOK If size is successfully set.
+ */
+uint32_t DSITX_GetVideoSize(DSITX_PrivateData* pD, DSITX_VideoSize* vidSize)
+{
+ uint32_t regVal;
+ uint32_t status;
+
+ /* check params */
+ if (DSITX_GetVideoSizeSF(pD, vidSize) != CDN_EOK) {
+ status = CDN_EINVAL;
+ } else {
+ /* get size parameters */
+ getVideoSizeVertical(pD, vidSize);
+ getVideoSizeHorizontal(pD, vidSize);
+
+ /* get additional parameters */
+ regVal = CPS_REG_READ(&pD->regBase->vid_blksize1);
+ vidSize->blkEolPacket = (uint16_t)CPS_FLD_READ(DSITX__VID_BLKSIZE1, BLKEOL_PCK, regVal);
+ vidSize->blkLineEventPacket = (uint16_t)CPS_FLD_READ(DSITX__VID_BLKSIZE1, BLKLINE_EVENT_PCK, regVal);
+
+ regVal = CPS_REG_READ(&pD->regBase->vid_blksize2);
+ vidSize->blkLinePulsePacket = (uint16_t)CPS_FLD_READ(DSITX__VID_BLKSIZE2, BLKLINE_PULSE_PCK, regVal);
+
+ status = CDN_EOK;
+ }
+ return status;
+}
+
+/* internal function */
+static void setTvgConfigColor1rgb(const DSITX_PrivateData* pD, const DSITX_TestVideoModeConfig* config)
+{
+ uint32_t regVal = 0U;
+ const DSITX_Color* col1 = &config->color1;
+ DSITX_Regs* regBase = pD->regBase;
+
+ /* write palette for first color */
+ regVal = CPS_FLD_WRITE(DSITX__TVG_COLOR1, COL1_RED, regVal, col1->r);
+ regVal = CPS_FLD_WRITE(DSITX__TVG_COLOR1, COL1_GREEN, regVal, col1->g);
+ CPS_REG_WRITE(®Base->tvg_color1, regVal);
+
+ regVal = 0U;
+ regVal = CPS_FLD_WRITE(DSITX__TVG_COLOR1_BIS, COL1_BLUE, regVal, col1->b);
+ CPS_REG_WRITE(®Base->tvg_color1_bis, regVal);
+}
+
+/* internal function */
+static void setTvgConfigColor2rgb(const DSITX_PrivateData* pD, const DSITX_TestVideoModeConfig* config)
+{
+ uint32_t regVal = 0U;
+ const DSITX_Color* col2 = &config->color2;
+ DSITX_Regs* regBase = pD->regBase;
+
+ /* write palette for second color */
+ regVal = CPS_FLD_WRITE(DSITX__TVG_COLOR2, COL2_RED, regVal, col2->r);
+ regVal = CPS_FLD_WRITE(DSITX__TVG_COLOR2, COL2_GREEN, regVal, col2->g);
+ CPS_REG_WRITE(®Base->tvg_color2, regVal);
+
+ regVal = 0U;
+ regVal = CPS_FLD_WRITE(DSITX__TVG_COLOR2_BIS, COL2_BLUE, regVal, col2->b);
+ CPS_REG_WRITE(®Base->tvg_color2_bis, regVal);
+}
+
+/**
+ * Configures Test Video Generator using provided configuration. This
+ * function ignores value of 'enabled' field in config structure. New
+ * configuration can be applied only if Test Video Generator is not
+ * running.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] config Pointer to structure containing Test Video Generator configuration.
+ * Value of the enabled field is ignored. Use startTvg function to enable TVG.
+ * @return CDN_EINVAL If provided configuration contains invalid values.
+ * @return CDN_EPERM If Test Video Generator is enabled.
+ * @return CDN_EOK If Test Video Generator was successfully started.
+ */
+uint32_t DSITX_SetTvgConfig(const DSITX_PrivateData* pD, const DSITX_TestVideoModeConfig* config)
+{
+ uint32_t status;
+
+ /* check params */
+ if (DSITX_SetTvgConfigSF(pD, config) != CDN_EOK) {
+ status = CDN_EINVAL;
+ } else if (config->enabled != 0U) {
+ status = CDN_EINVAL;
+ } else {
+ DSITX_Regs* regBase = pD->regBase;
+
+ uint32_t regVal = CPS_REG_READ(®Base->tvg_sts);
+
+ if ((CPS_FLD_READ(DSITX__TVG_STS, TVG_RUNNING, regVal)) != 0U) {
+ /* TVG is running. Configuration was not set. */
+ status = CDN_EPERM;
+ } else {
+ /* set image parameters */
+ regVal = 0;
+ regVal = CPS_FLD_WRITE(DSITX__TVG_IMG_SIZE, TVG_LINE_SIZE, regVal, config->bytesPerLine);
+ regVal = CPS_FLD_WRITE(DSITX__TVG_IMG_SIZE, TVG_NBLINE, regVal, config->linesPerFrame);
+ CPS_REG_WRITE(®Base->tvg_img_size, regVal);
+
+ /* set both colors */
+ setTvgConfigColor1rgb(pD, config);
+ setTvgConfigColor2rgb(pD, config);
+
+ /* set pattern */
+ regVal = 0;
+ regVal = CPS_FLD_WRITE(DSITX__TVG_CTL, TVG_STRIPE_SIZE, regVal, (uint32_t)config->stripeSize);
+ regVal = CPS_FLD_WRITE(DSITX__TVG_CTL, TVG_MODE, regVal, (uint32_t)config->displayMode);
+ regVal = CPS_FLD_WRITE(DSITX__TVG_CTL, TVG_STOPMODE, regVal, (uint32_t)config->stopMode);
+ CPS_REG_WRITE(®Base->tvg_ctl, regVal);
+
+ status = CDN_EOK;
+ }
+ }
+ return status;
+}
+
+/* internal function */
+static void getTvgConfigColor1rgb(DSITX_PrivateData* pD, DSITX_TestVideoModeConfig* config)
+{
+ uint32_t regVal;
+
+ /* read palette for 1st colour */
+ regVal = CPS_REG_READ(&pD->regBase->tvg_color1);
+ config->color1.r = (uint16_t)CPS_FLD_READ(DSITX__TVG_COLOR1, COL1_RED, regVal);
+ config->color1.g = (uint16_t)CPS_FLD_READ(DSITX__TVG_COLOR1, COL1_GREEN, regVal);
+
+ regVal = CPS_REG_READ(&pD->regBase->tvg_color1_bis);
+ config->color1.b = (uint16_t)CPS_FLD_READ(DSITX__TVG_COLOR1_BIS, COL1_BLUE, regVal);
+}
+
+/* internal function */
+static void getTvgConfigColor2rgb(DSITX_PrivateData* pD, DSITX_TestVideoModeConfig* config)
+{
+ uint32_t regVal;
+
+ /* read palette for 2nd colour */
+ regVal = CPS_REG_READ(&pD->regBase->tvg_color2);
+ config->color2.r = (uint16_t)CPS_FLD_READ(DSITX__TVG_COLOR2, COL2_RED, regVal);
+ config->color2.g = (uint16_t)CPS_FLD_READ(DSITX__TVG_COLOR2, COL2_GREEN, regVal);
+
+ regVal = CPS_REG_READ(&pD->regBase->tvg_color2_bis);
+ config->color2.b = (uint16_t)CPS_FLD_READ(DSITX__TVG_COLOR2_BIS, COL2_BLUE, regVal);
+}
+
+/* internal function */
+static uint32_t getTvgConfigCtl(DSITX_PrivateData* pD, DSITX_TestVideoModeConfig* config)
+{
+ uint32_t regVal;
+ uint32_t status;
+
+ /* read TVG settings from register */
+ regVal = CPS_REG_READ(&pD->regBase->tvg_ctl);
+
+ status = getTvgDisplayModeEnum(CPS_FLD_READ(DSITX__TVG_CTL, TVG_MODE, regVal), &config->displayMode);
+ status |= getTvgStripeSizeEnum(CPS_FLD_READ(DSITX__TVG_CTL, TVG_STRIPE_SIZE, regVal), &config->stripeSize);
+ status |= getTvgStopModeEnum(CPS_FLD_READ(DSITX__TVG_CTL, TVG_STOPMODE, regVal), &config->stopMode);
+
+ config->enabled = valToBool(CPS_FLD_READ(DSITX__TVG_CTL, TVG_RUN, regVal));
+
+ return status;
+}
+
+/**
+ * Reads Test Video Generator configuration.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] config Pointer to structure to which received Test Video Generator
+ * configuration will be written.
+ * @return CDN_EINVAL If pD or config is NULL.
+ * @return CDN_EOK If Test Video Generator configuration was successfully read.
+ */
+uint32_t DSITX_GetTvgConfig(DSITX_PrivateData* pD, DSITX_TestVideoModeConfig* config)
+{
+ uint32_t regVal;
+ uint32_t status;
+
+ /* check params */
+ if (DSITX_GetTvgConfigSF(pD, config) != CDN_EOK) {
+ status = CDN_EINVAL;
+ } else {
+ /* get config */
+ status = getTvgConfigCtl(pD, config);
+
+ if (CDN_EOK == status) {
+ /* get palette for both tvg colors */
+ getTvgConfigColor1rgb(pD, config);
+ getTvgConfigColor2rgb(pD, config);
+
+ /* extract image parameters */
+ regVal = CPS_REG_READ(&pD->regBase->tvg_img_size);
+ config->bytesPerLine = (uint16_t)CPS_FLD_READ(DSITX__TVG_IMG_SIZE, TVG_LINE_SIZE, regVal);
+ config->linesPerFrame = (uint16_t)CPS_FLD_READ(DSITX__TVG_IMG_SIZE, TVG_NBLINE, regVal);
+ }
+ }
+ return status;
+}
+
+/**
+ * Enables Test Video Generator.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] wait Determines if function will wait until Test Video Generator is started
+ * (true) or will exit immediately (false) and raise TVG Event (if enabled)
+ * when TVG starts.
+ * @return CDN_EINVAL If pD is NULL.
+ * @return CDN_EIO On timeout.
+ * @return CDN_EOK If operation was successful.
+ */
+uint32_t DSITX_StartTvg(DSITX_PrivateData* pD, bool wait)
+{
+ uint32_t regVal;
+ uint32_t timeout = REG_POOL_TIMEOUT;
+ uint32_t status;
+
+ if (DSITX_StartTvgSF(pD) != CDN_EOK) {
+ status = CDN_EINVAL;
+ } else {
+ /* Enabling TVG */
+ if (CPS_FLD_READ(DSITX__MCTL_MAIN_EN, IF1_EN, CPS_REG_READ(&pD->regBase->mctl_main_en)) != 0U) {
+ /* TVG cannot be enabled while Video Interface is running */
+ status = CDN_EINVAL;
+ } else {
+
+ regVal = CPS_REG_READ(&pD->regBase->tvg_ctl);
+ regVal = CPS_FLD_WRITE(DSITX__TVG_CTL, TVG_RUN, regVal, 1);
+ CPS_REG_WRITE(&pD->regBase->tvg_ctl, regVal);
+
+ status = CDN_EOK;
+
+ if (wait != 0U) { /* add watchdog in case of TBG never starting? */
+ /* Waiting for TVG to start. */
+ do {
+ regVal = CPS_REG_READ(&pD->regBase->tvg_sts);
+ --timeout;
+ } while ((CPS_FLD_READ(DSITX__TVG_STS, TVG_RUNNING, regVal) == 0U) && (timeout != 0U));
+
+ if (timeout == 0U) {
+ /* Failed to start TVG */
+ status = CDN_EIO;
+ }
+ }
+ }
+ }
+ return status;
+}
+
+/**
+ * Stops Test Video Generator. If stop mode is 'stop immediate' then
+ * the VSG needs to be stopped and video system restarted.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] wait Determines if function will wait until Test Video Generator is in
+ * stopped state (true) or will exit immediately (false).
+ * @return CDN_EINVAL If pD is NULL.
+ * @return CDN_EPERM If TVG stop mode is set to 'stop immediate'.
+ * @return CDN_EIO On timeout.
+ * @return CDN_EOK If operation was successful.
+ */
+uint32_t DSITX_StopTvg(DSITX_PrivateData* pD, bool wait)
+{
+ uint32_t regVal = 0;
+ uint32_t timeout = REG_POOL_TIMEOUT;
+ uint32_t status = CDN_EOK;
+
+ if (DSITX_StopTvgSF(pD) != CDN_EOK) {
+ status = CDN_EINVAL;
+ }
+
+ if (status == CDN_EOK) {
+ regVal = CPS_REG_READ(&pD->regBase->tvg_ctl);
+
+ if ((CPS_FLD_READ(DSITX__TVG_CTL, TVG_STOPMODE, regVal) == (uint32_t)DSITX_TVG_STOP_MODE_IMMEDIATE)) {
+ /* In current stop mode (immediate) */
+ /* whole video system needs to be restarted in order to stop TVG */
+ status = CDN_EPERM;
+ }
+ }
+
+ if (status == CDN_EOK) {
+ /* Disabling TVG */
+ regVal = CPS_REG_READ(&pD->regBase->tvg_ctl);
+ regVal = CPS_FLD_WRITE(DSITX__TVG_CTL, TVG_RUN, regVal, 0);
+ CPS_REG_WRITE(&pD->regBase->tvg_ctl, regVal);
+
+ if (wait != 0U) {
+ /* Waiting for TVG to stop */
+ do {
+ regVal = CPS_REG_READ(&pD->regBase->tvg_sts);
+ --timeout;
+ } while ((CPS_FLD_READ(DSITX__TVG_STS, TVG_RUNNING, regVal) != 0U) && (timeout != 0U));
+
+ if (timeout == 0U) {
+ /* Failed to stop TVG */
+ status = CDN_EIO;
+ }
+ }
+ }
+ return status;
+}
+
+static uint8_t clampDcrCmdSize(const DSITX_PrivateData* pD, const DSITX_DirectCommandRequest* dcr)
+{
+ /* Direct Command size limits are described in the Table 31 of User Guide */
+ uint8_t size = dcr->cmdSize;
+
+ if ((dcr->type == DSITX_DCR_TYPE_WRITE) && (size > pD->ip.directCmdFifoDepth)) {
+ /* CMD size too large. Setting to directCmdFifoDepth */
+ size = (uint8_t) pD->ip.directCmdFifoDepth;
+ } else if (((dcr->type) == (DSITX_DCR_TYPE_READ)) && (size > 2U)) {
+ /* CMD size too large. Setting to 2 */
+ size = 2;
+ } else {
+ /* size was within range - don't modify it */
+ }
+ return size;
+}
+
+static uint32_t sendDirectCmdReadWrite(DSITX_PrivateData* pD, DSITX_DirectCommandRequest* dcr, uint32_t* regVal)
+{
+ uint32_t status = CDN_EOK;
+
+ dcr->cmdSize = clampDcrCmdSize(pD, dcr);
+
+ uint8_t* ptr = dcr->cmdData;
+ uint32_t size = dcr->cmdSize;
+
+ if ((size != 0U) && (ptr == NULL)) {
+ /* No command data provided */
+ status = CDN_EINVAL;
+ }
+
+ if (status == CDN_EOK) {
+ /* Set common R/W cmd parameters */
+ *regVal = CPS_FLD_WRITE(DSITX__DIRECT_CMD_MAIN_SETTINGS, CMD_HEAD, *regVal, dcr->head);
+ *regVal = CPS_FLD_WRITE(DSITX__DIRECT_CMD_MAIN_SETTINGS, CMD_ID, *regVal, dcr->vcId);
+ *regVal = CPS_FLD_WRITE(DSITX__DIRECT_CMD_MAIN_SETTINGS, CMD_SIZE, *regVal, dcr->cmdSize);
+
+ /* Reset FIFO write pointer */
+ CPS_REG_WRITE(&pD->regBase->direct_cmd_fifo_rst, 1);
+ uint32_t data;
+ uint8_t index = 0;
+ while (size != 0U) {
+ data = ReadFromBuff32le(&ptr[index], size);
+ CPS_REG_WRITE(&pD->regBase->direct_cmd_wrdat, data);
+ index += 4U;
+ size -= min(size, (uint32_t) (sizeof(uint32_t)));
+ };
+
+ if (dcr->type == DSITX_DCR_TYPE_READ) {
+ if (dcr->recData == NULL) {
+ /* No buffer for storing data */
+ status = CDN_EINVAL;
+ } else {
+ if (dcr->wait != 0U) {
+ /* Disable read interrupts/events and wait for STS */
+ CPS_REG_WRITE(&pD->regBase->direct_cmd_rd_sts_ctl, 0);
+ } else {
+ /* Enable read interrupts/events required by user */
+ CPS_REG_WRITE(&pD->regBase->direct_cmd_rd_sts_ctl, dcr->enRdEvents);
+ }
+ }
+ }
+ }
+ return status;
+}
+
+/* internal function */
+static uint32_t sendDirectCmdTrigger(const DSITX_DirectCommandRequest* dcr, uint32_t* regVal)
+{
+ uint32_t status = CDN_EOK;
+
+ if ((((uint32_t)dcr->triggerValue) & ((uint32_t)dcr->triggerValue - 1U)) != 0U) {
+ /* Only one of the Trigger Value bits can be set */
+ status = CDN_EINVAL;
+ } else {
+ *regVal = CPS_FLD_WRITE(DSITX__DIRECT_CMD_MAIN_SETTINGS, TRIGGER_VAL, *regVal, (uint32_t)dcr->triggerValue);
+ }
+ return status;
+}
+
+/* internal function */
+static uint32_t sendDirectCmdFinalStatus(DSITX_PrivateData* pD, DSITX_DirectCommandRequest* dcr)
+{
+ uint32_t status = CDN_EOK;
+ uint32_t timeout = DIRECT_CMD_TIMEOUT;
+
+ /* wait for bit DCR_STS_TRANSMISSION */
+ do {
+ dcr->status = CPS_REG_READ(&pD->regBase->direct_cmd_sts);
+ --timeout;
+ } while (((dcr->status & (uint32_t)DSITX_DCR_STS_TRANSMISSION) == 1U) && (timeout != 0U));
+
+ pD->processingDcr = false;
+
+ if (timeout != 0U) {
+ dcr->ackVal = (uint8_t)CPS_FLD_READ(DSITX__DIRECT_CMD_STS, ACK_VAL, dcr->status);
+ /* Remove ACK value from status bits; may be removed in case of performance drop */
+ dcr->status = dcr->status & (~DSITX__DIRECT_CMD_STS__ACK_VAL_MASK);
+ if (dcr->type == DSITX_DCR_TYPE_READ) {
+ status = readDCRData(pD, dcr);
+ }
+ } else {
+ status = CDN_EIO;
+ }
+ return status;
+}
+
+/* internal function */
+static uint32_t validateSendDcrPrecndtns(const DSITX_PrivateData* pD, const DSITX_DirectCommandRequest* dcr)
+{
+ uint32_t status;
+
+ if (pD->processingDcr != 0U) {
+ /* Cannot send request before previous completes. */
+ status = CDN_EINPROGRESS;
+ } else if ((dcr->lpMode == 0U) && ((CPS_FLD_READ(DSITX__MCTL_MAIN_EN, PLL_START, CPS_REG_READ(&pD->regBase->mctl_main_en))) == 0U)) {
+ /* HS mode requires enabled PLL, return CDN_EINVAL if PLL is not enabled */
+ status = CDN_EINVAL;
+ } else {
+ status = CDN_EOK;
+ }
+ return status;
+}
+
+/* internal function */
+static uint32_t sendDirectCmdCfg(DSITX_PrivateData* pD, DSITX_DirectCommandRequest* dcr)
+{
+ uint32_t status;
+
+ dcr->status = (uint32_t)DSITX_DIRECT_COMMAND_STATUS_BITS_INIT;
+ dcr->rdStatus = (uint32_t)DSITX_DIRECT_COMMAND_READ_STATUS_BITS_INIT;
+ pD->dcr = dcr;
+ pD->processingDcr = true;
+
+ DSITX_DirectCommandType dcrType = dcr->type;
+ DSITX_Regs* regBase = pD->regBase;
+ uint32_t regVal = 0;
+
+ /* Clear all status bits by setting up all bits in clr registers to 1. */
+ CPS_REG_WRITE(®Base->direct_cmd_sts_clr, ~DSITX__DIRECT_CMD_STS_CLR_WRITE_MASK);
+ CPS_REG_WRITE(®Base->direct_cmd_rd_sts_clr, ~DSITX__DIRECT_CMD_RD_STS_CLR_WRITE_MASK);
+
+ /* Set common configuration */
+ regVal = CPS_FLD_WRITE(DSITX__DIRECT_CMD_MAIN_SETTINGS, CMD_NAT, regVal, (uint32_t)dcrType);
+ regVal = CPS_FLD_WRITE(DSITX__DIRECT_CMD_MAIN_SETTINGS, CMD_LP_EN, regVal, boolToVal(dcr->lpMode));
+ regVal = CPS_FLD_WRITE(DSITX__DIRECT_CMD_MAIN_SETTINGS, CMD_LONGNOTSHORT, regVal, boolToVal(dcr->longPacket));
+
+ /* for various command types call appropriate function */
+ if ((dcrType == DSITX_DCR_TYPE_WRITE) || (dcrType == DSITX_DCR_TYPE_READ)) {
+ status = sendDirectCmdReadWrite(pD, dcr, ®Val);
+ } else if ((dcrType == DSITX_DCR_TYPE_TRIGGER) != 0U) {
+ status = sendDirectCmdTrigger(dcr, ®Val);
+ } else {
+ /* skip this operation for other types */
+ status = CDN_EOK;
+ }
+
+ CPS_REG_WRITE(®Base->direct_cmd_main_settings, regVal);
+
+ return status;
+}
+
+/* internal function */
+static uint32_t sendDirectCmdIrq(DSITX_PrivateData* pD, DSITX_DirectCommandRequest* dcr)
+{
+ uint32_t status = CDN_EOK;
+
+ if (dcr->wait != 0U) {
+ /* Disable interrupts/events */
+ CPS_REG_WRITE(&pD->regBase->direct_cmd_sts_ctl, 0);
+ } else {
+ /* Enable interrupts/events required by user */
+ CPS_REG_WRITE(&pD->regBase->direct_cmd_sts_ctl, dcr->enEvents);
+ }
+
+ /* Start Direct Command */
+ CPS_REG_WRITE(&pD->regBase->direct_cmd_send, 1);
+ if (dcr->wait != 0U) {
+ status = sendDirectCmdFinalStatus(pD, dcr);
+ }
+
+ return status;
+}
+
+/**
+ * Sends Direct Command Request. Only one request can be sent at a
+ * time. After sending command request user shall not make changes to
+ * request structure unless request structure is provided to user in
+ * the callback function.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] dcr Pointer to structure containing detailed information about command.
+ * This structure will be updated by Core Driver during command
+ * execution. After passing it to Core Driver user shall not make
+ * any changes to its content until dcr status is set to completed
+ * or it is presented in callback function.
+ * @return CDN_EINVAL If pD NULL.
+ * @return CDN_EPERM If dcr cannot be sent due to state of the DSITX link (e.g. TVG enabled).
+ * @return CDN_EINPROGRESS If processing of other request has not yet been completed.
+ * @return CDN_EOK If Direct Command is accepted and pending execution.
+ */
+uint32_t DSITX_SendDirectCmd(DSITX_PrivateData* pD, DSITX_DirectCommandRequest* dcr)
+{
+ uint32_t status;
+
+ /* check params */
+ if (DSITX_SendDirectCmdSF(pD, dcr) != CDN_EOK) {
+ status = CDN_EINVAL;
+ } else {
+ status = validateSendDcrPrecndtns(pD, dcr);
+ /* if dcr is correct set configuration */
+ if (status == CDN_EOK) {
+ status = sendDirectCmdCfg(pD, dcr);
+ }
+
+ /* if set config finished successfully set interrupts */
+ if (status == CDN_EOK) {
+ status = sendDirectCmdIrq(pD, dcr);
+ }
+ }
+
+ return status;
+}
+
+/**
+ * Sets DSITX Link Event Handler function and informs Core Driver
+ * which events should be reported to user.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] enabledEvents Specifies which DSITX Link events should be reported by Core Driver.
+ * @param[in] callback Pointer to function that will be called when event occurs.
+ * When value of this pointer is set to NULL then all events for
+ * DSITX Link will be disabled and value of the events argument is ignored.
+ */
+uint32_t DSITX_SetDsiLinkEventHandler(DSITX_PrivateData *pD, uint32_t enabledEvents, DSITX_DsiLinkEventHandler callback)
+{
+ uint32_t regVal = 0U;
+ uint32_t status = CDN_EOK;
+
+ /* check params */
+ if (DSITX_SetDsiLinkEventHandlerSF(pD) != CDN_EOK) {
+ status = CDN_EINVAL;
+ } else {
+ pD->fnDsiLinkCallback = callback;
+ pD->enDsiLinkStsBits = enabledEvents;
+
+ if (callback != NULL) {
+ /* if callback is provided build new settings */
+ regVal = CPS_REG_READ(&pD->regBase->mctl_main_sts_ctl)
+ | (enabledEvents & 0x0000FFFFU);
+ }
+ /* write link event settings to register */
+ CPS_REG_WRITE(&pD->regBase->mctl_main_sts_ctl, regVal);
+ }
+ return status;
+}
+
+/**
+ * Sets Command Mode Event Handler function and informs Core Driver
+ * which events should be reported to user.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] enabledEvents Specifies which Command Mode events should be reported by Core Driver.
+ * @param[in] callback Pointer to function that will be called when Command Mode event occurs.
+ * When value of this pointer is set to NULL then all events for
+ * Command Mode will be disabled and value of the events argument is ignored.
+ * @return CDN_EINVAL If pD NULL.
+ * @return CDN_EOK If Direct Command is accepted and pending execution.
+ */
+uint32_t DSITX_SetCmdModeEventHandler(DSITX_PrivateData *pD, uint32_t enabledEvents, DSITX_CmdModeEventHandler callback)
+{
+ uint32_t regVal = 0U;
+ uint32_t status = CDN_EOK;
+
+ /* check params */
+ if (DSITX_SetCmdModeEventHandlerSF(pD) != CDN_EOK) {
+ status = CDN_EINVAL;
+ } else {
+ pD->fnCmdModeCallback = callback;
+ pD->enCmdModeStsBits = enabledEvents;
+
+ if (callback != NULL) {
+ /* if callback is provided build new settings */
+ const uint32_t cmdModeStsCtl = CPS_REG_READ(&pD->regBase->cmd_mode_sts_ctl);
+ regVal = cmdModeStsCtl
+ | (enabledEvents & 0x0000FFFFU);
+ }
+ /* write command mode event settings to register */
+ CPS_REG_WRITE(&pD->regBase->cmd_mode_sts_ctl, regVal);
+ }
+ return status;
+}
+
+/**
+ * Sets Video Mode Event Handler function and informs Core Driver
+ * which events should be reported to user.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] enabledEvents Specifies which Video Mode events should be reported by Core Driver.
+ * @param[in] callback Pointer to function that will be called when Video Mode event occurs.
+ * When value of this pointer is set to NULL then all events for
+ * Video Mode will be disabled and value of the events argument is ignored.
+ * @return CDN_EINVAL If pD NULL.
+ * @return CDN_EOK If Direct Command is accepted and pending execution.
+ */
+uint32_t DSITX_SetVidModeEventHandler(DSITX_PrivateData *pD, uint32_t enabledEvents, DSITX_VidModeEventHandler callback)
+{
+ uint32_t regVal = 0U;
+ uint32_t status = CDN_EOK;
+
+ /* check params */
+ if (DSITX_SetVidModeEventHandlerSF(pD) != CDN_EOK) {
+ status = CDN_EINVAL;
+ } else {
+ pD->fnVidModeCallback = callback;
+ pD->enVidModeStsBits = enabledEvents;
+
+ if (callback != NULL) {
+ /* if callback is provided build new settings */
+ const uint32_t vidModeStsCtl = CPS_REG_READ(&pD->regBase->vid_mode_sts_ctl);
+ regVal = vidModeStsCtl
+ | (enabledEvents & 0x0000FFFFU);
+ }
+ /* write video mode event settings to register */
+ CPS_REG_WRITE(&pD->regBase->vid_mode_sts_ctl, regVal);
+ }
+ return status;
+}
+
+/**
+ * Sets Test Video Generator Event Handler function and informs Core
+ * Driver which events should be reported to the user.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] enabledEvents Specifies which Test Video Generator events should be reported by Core Driver.
+ * @param[in] callback Pointer to function that will be called when Test Video Generator event occurs.
+ * When value of this pointer is set to NULL then all events for
+ * Test Video Generator will be disabled and value of events argument is ignored.
+ * @return CDN_EINVAL If pD NULL.
+ * @return CDN_EOK If Direct Command is accepted and pending execution.
+ */
+uint32_t DSITX_SetTvgEventHandler(DSITX_PrivateData *pD, uint32_t enabledEvents, DSITX_TvgEventHandler callback)
+{
+ uint32_t regVal;
+ uint32_t status = CDN_EOK;
+
+ /* check params */
+ if (DSITX_SetTvgEventHandlerSF(pD) != CDN_EOK) {
+ status = CDN_EINVAL;
+ } else {
+ pD->fnTvgCallback = callback;
+ pD->enTvgStsBits = enabledEvents;
+
+ /* read current settings */
+ regVal = CPS_REG_READ(&pD->regBase->tvg_sts_ctl);
+
+ /* new settings accordingly to callback */
+ if (callback != NULL) {
+ regVal |= enabledEvents & 0x0000FFFFU;
+ } else {
+ regVal &= ~(DSITX__TVG_STS_CTL__TVG_STS_EN_MASK | DSITX__TVG_STS_CTL__TVG_STS_EDGE_MASK);
+ }
+ /* write settings to register */
+ CPS_REG_WRITE(&pD->regBase->tvg_sts_ctl, regVal);
+ }
+ return status;
+}
+
+/**
+ * Sets DPHY Error Event Handler function and informs Core Driver
+ * which events should be reported to user.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] enabledEvents Specifies which DPHY errors should be reported by Core Driver.
+ * @param[in] callback Pointer to function that will be called when DPHY error occurs.
+ * When value of this pointer is set to NULL then all error events for
+ * DPHY will be disabled and value of the events argument is ignored.
+ * @return CDN_EINVAL If pD NULL.
+ * @return CDN_EOK If Direct Command is accepted and pending execution.
+ */
+uint32_t DSITX_SetDphyErrorEventHandler(DSITX_PrivateData *pD, uint32_t enabledEvents, DSITX_DphyErrorEventHandler callback)
+{
+ uint32_t regVal = 0U;
+ uint32_t status = CDN_EOK;
+
+ /* check params */
+ if (DSITX_SetDphyErrorEventHandlSF(pD) != CDN_EOK) {
+ status = CDN_EINVAL;
+ } else {
+ pD->fnDphyErrCallback = callback;
+ pD->enDphyErrBits = enabledEvents;
+
+ /* write new settings to registers */
+ if (callback == NULL) {
+ /* if collback is not given, disable error reporting */
+ CPS_REG_WRITE(&pD->regBase->mctl_dphy_err_ctl1, regVal);
+ CPS_REG_WRITE(&pD->regBase->mctl_dphy_err_ctl2, regVal);
+ } else {
+ /* otherwise enable elements */
+ const uint32_t mctlDphyErrCtl1 = CPS_REG_READ(&pD->regBase->mctl_dphy_err_ctl1);
+ regVal = mctlDphyErrCtl1 | (enabledEvents);
+ CPS_REG_WRITE(&pD->regBase->mctl_dphy_err_ctl1, regVal);
+ }
+ }
+ return status;
+}
+
+/**
+ * Sets DPI Event Handler function and informs Core Driver which
+ * events should be reported to user.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] enabledEvents Specifies which DPI events should be reported by Core Driver.
+ * @param[in] callback Pointer to function that will be called when DPI interrupt occurs.
+ * When value of this pointer is set to NULL then all events for DPI
+ * will be disabled and value of the events argument is ignored.
+ * @return CDN_EINVAL If pD NULL.
+ * @return CDN_EOK If Direct Command is accepted and pending execution.
+ */
+uint32_t DSITX_SetDpiEventHandler(DSITX_PrivateData* pD, uint32_t enabledEvents, DSITX_DpiEventHandler callback)
+{
+ uint32_t regVal = 0U;
+ uint32_t status = CDN_EOK;
+
+ /* check params */
+ if (DSITX_SetDpiEventHandlerSF(pD) != CDN_EOK) {
+ status = CDN_EINVAL;
+ } else {
+ pD->fnDpiCallback = callback;
+ pD->enDpiStsBits = enabledEvents;
+
+ /* if callback is given, build register value */
+ if (callback != NULL) {
+ const uint32_t dpiIrqEn = CPS_REG_READ(&pD->regBase->dpi_irq_en);
+ regVal = dpiIrqEn | enabledEvents;
+ }
+
+ /* write value to the register */
+ CPS_REG_WRITE(&pD->regBase->dpi_irq_en, regVal);
+ }
+ return status;
+}
+
+/**
+ * Sets DSITX Test register.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] test Pointer to structure containing control configuration.
+ * @return CDN_EINVAL If pD NULL.
+ * @return CDN_EOK On success.
+ */
+uint32_t DSITX_SetTestGeneric(DSITX_PrivateData *pD, DSITX_TestGeneric const *test)
+{
+ uint32_t regVal;
+ uint32_t status;
+
+ /* check params */
+ if (DSITX_SetTestGenericSF(pD, test) != CDN_EOK) {
+ status = CDN_EINVAL;
+ } else {
+ /* combine structure fields to register */
+ regVal = 0;
+ regVal = CPS_FLD_WRITE(DSITX__TEST_GENERIC, CTRL, regVal, (uint32_t)test->ctrl);
+ /* write register */
+ CPS_REG_WRITE(&pD->regBase->test_generic, regVal);
+ status = CDN_EOK;
+ }
+ return status;
+}
+
+/**
+ * Obtains DSITX Test register value.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] test Pointer to structure to which control configuration will be
+ * written.
+ * @return CDN_EINVAL If pD NULL.
+ * @return CDN_EOK On success.
+ */
+uint32_t DSITX_GetTestGeneric(DSITX_PrivateData *pD, DSITX_TestGeneric *test)
+{
+ uint32_t regVal;
+ uint32_t status;
+
+ /* check params */
+ if (DSITX_GetTestGenericSF(pD, test) != CDN_EOK) {
+ status = CDN_EINVAL;
+ } else {
+ /* read register */
+ regVal = CPS_REG_READ(&pD->regBase->test_generic);
+
+ /* split register value to structure fields */
+ test->ctrl = (uint16_t) CPS_FLD_READ(DSITX__TEST_GENERIC, CTRL, regVal);
+ test->status = (uint16_t) CPS_FLD_READ(DSITX__TEST_GENERIC, STATUS, regVal);
+
+ status = CDN_EOK;
+ }
+ return status;
+}
+
+
+
+/**
+ * Sets Video 3D configuration.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] cfg Video 3D configuration.
+ * @return CDN_EINVAL If pD or value is NULL.
+ * @return CDN_EOK On success.
+ */
+uint32_t DSITX_SetVideo3dConfig(DSITX_PrivateData *pD, const DSITX_Video3dConfig *cfg)
+{
+ uint32_t status = CDN_EOK;
+ uint32_t regVal;
+
+ /* check params */
+ if ((DSITX_SetVideo3dConfigSF(pD, cfg)) != CDN_EOK) {
+ status = CDN_EINVAL;
+ } else {
+ /* build register value from structure fields */
+ regVal = CPS_REG_READ(&pD->regBase->mctl_3dvideo_ctl);
+ regVal = CPS_FLD_WRITE(DSITX__MCTL_3DVIDEO_CTL, VID_VSYNC_3DMODE, regVal, cfg->vidSync3dMode);
+ regVal = CPS_FLD_WRITE(DSITX__MCTL_3DVIDEO_CTL, VID_VSYNC_3DFORMAT, regVal, cfg->vidSync3dFormat);
+ regVal = CPS_FLD_WRITE(DSITX__MCTL_3DVIDEO_CTL, VID_VSYNC_3D_SECOND_EN, regVal, boolToVal(cfg->vidVsync3dSecondEnable));
+ regVal = CPS_FLD_WRITE(DSITX__MCTL_3DVIDEO_CTL, VID_VSYNC_3D_LR, regVal, cfg->vidVsync3dLr);
+ regVal = CPS_FLD_WRITE(DSITX__MCTL_3DVIDEO_CTL, VID_VSYNC_3D_EN, regVal, boolToVal(cfg->vidVsync3dEnable));
+ /* write calculated regVal to appropriate register */
+ CPS_REG_WRITE(&pD->regBase->mctl_3dvideo_ctl, regVal);
+ }
+ return status;
+}
+
+/**
+ * Gets Video 3D configuration.
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] cfg Video 3D configuration.
+ * @return CDN_EINVAL If pD or value is NULL.
+ * @return CDN_EOK On success.
+ */
+uint32_t DSITX_GetVideo3dConfig(DSITX_PrivateData *pD, DSITX_Video3dConfig *cfg)
+{
+ uint32_t status = CDN_EOK;
+
+ /* check params */
+ if ((DSITX_GetVideo3dConfigSF(pD, cfg)) != CDN_EOK) {
+ status = CDN_EINVAL;
+ } else {
+ /* read register value */
+ uint32_t regVal = CPS_REG_READ(&pD->regBase->mctl_3dvideo_ctl);
+ /* split value to stucture fields */
+ status = getVidSync3dModeEnum(CPS_FLD_READ(DSITX__MCTL_3DVIDEO_CTL, VID_VSYNC_3DMODE, regVal), &cfg->vidSync3dMode);
+ status |= getVidVsync3dLrEnum(CPS_FLD_READ(DSITX__MCTL_3DVIDEO_CTL, VID_VSYNC_3D_LR, regVal), &cfg->vidVsync3dLr);
+ status |= getVidSync3dFormatEnum(CPS_FLD_READ(DSITX__MCTL_3DVIDEO_CTL, VID_VSYNC_3DFORMAT, regVal), &cfg->vidSync3dFormat);
+
+ cfg->vidVsync3dSecondEnable = valToBool(CPS_FLD_READ(DSITX__MCTL_3DVIDEO_CTL, VID_VSYNC_3D_SECOND_EN , regVal));
+ cfg->vidVsync3dEnable = valToBool(CPS_FLD_READ(DSITX__MCTL_3DVIDEO_CTL, VID_VSYNC_3D_EN, regVal));
+ }
+ return status;
+}
+
+/**
+ * Retrieves ASF information from DSITX controller.
+ * @param[in] pD Pointer to driver's private data object.
+ * @param[out] asfInfo Pointer to ASF information structure.
+ * @return CDN_EINVAL If pD or asfInfo is NULL.
+ * @return CDN_EOK On success.
+ */
+uint32_t DSITX_GetAsfInfo(const DSITX_PrivateData *pD, DSITX_AsfInfo* asfInfo)
+{
+ uint32_t status = CDN_EOK;
+
+ if (DSITX_GetAsfInfoSF(pD, asfInfo) != CDN_EOK) {
+ status = CDN_EINVAL;
+ } else {
+ asfInfo->regBase = &(pD->regBase->asf_int_status);
+ }
+ return status;
+}
+
+// parasoft-end-suppress METRICS-36-3
diff --git a/packages/ti/drv/dss/src/csl/dsi/src/dsitx_cfg.h b/packages/ti/drv/dss/src/csl/dsi/src/dsitx_cfg.h
--- /dev/null
@@ -0,0 +1,98 @@
+/******************************************************************************
+ * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * MIPI DSITX Host and its Core Driver default configuration file.
+ *
+ *****************************************************************************/
+
+#ifndef DSITX_CFG_H_
+# define DSITX_CFG_H_
+
+# include <dsitx_if.h>
+
+/******************************************************************************
+ * Defines and macros.
+ *****************************************************************************/
+
+#define DSITX_VID_BYTES_PER_PIXEL 3
+
+/** Maximum interface number starting from 0. This value depends on number of
+ * interfaces supported by DSITX Host. */
+# define DSITX_MAX_INTERFACE_NUMBER 1
+
+# define DSITX_MAIN_PHY_CLK_CONTINUOUS 0
+
+# define DSITX_VID_PIXEL_MODE DSITX_VID_PIXEL_MODE_RGB_24
+# define DSITX_VID_VC_ID 0
+# define DSITX_VID_SYNC_PULSE_ACTIVE 0
+# define DSITX_VID_SYNC_PULSE_HORIZONTAL 0
+# define DSITX_VID_BLK_MODE_LINE DSITX_VID_BLK_MODE_LP
+# define DSITX_VID_BLK_MODE_EOL DSITX_VID_BLK_MODE_LP
+# define DSITX_VID_RECOVERY_MODE DSITX_VID_RECOVERY_MODE_CONTINUE_TILL_NEXT_HSYNC
+
+# define DSITX_VID_SIZE_VSA 1
+# define DSITX_VID_SIZE_VBP 0
+# define DSITX_VID_SIZE_VFP 1
+# define DSITX_VID_SIZE_VACT 320
+# define DSITX_VID_SIZE_HSA 0
+# define DSITX_VID_SIZE_HBP 0
+# define DSITX_VID_SIZE_HFP 0
+# define DSITX_VID_SIZE_RGB (480 * DSITX_VID_BYTES_PER_PIXEL)
+
+# define DSITX_VID_BURST_LP 0
+
+// Below values are taken from example in specification
+# define DSITX_VID_WAKEUP_TIME_CL ((DSITX_MAIN_PHY_CLK_CONTINUOUS) ? 0x1 : 0x27)
+# define DSITX_VID_WAKEUP_TIME_DL 0xA
+# define DSITX_VID_WAKEUP_TIME_DSI 0x13
+# define DSITX_VID_WAKEUP_TIME (DSITX_VID_WAKEUP_TIME_CL + DSITX_VID_WAKEUP_TIME_DL + DSITX_VID_WAKEUP_TIME_DSI)
+
+# define DSITX_TVG_STRIPE_SIZE 5 // 2^5==32
+# define DSITX_TVG_DISPLAY_MODE DSITX_TVG_MODE_HORIZONTAL_STRIPES
+# define DSITX_TVG_STOP_MODE DSITX_TVG_STOP_MODE_AT_END_OF_LINE
+# define DSITX_TVG_LINES_PER_FRAME 240
+# define DSITX_TVG_PIXELS_PER_LINE 320
+
+# define DSITX_TBG_MODE DSITX_TBG_MODE_START_BURST_STOP
+# define DSITX_TBG_USE_PROGRAMMED_DATA 1
+# define DSITX_TBG_HS_TRANSFER 1
+# define DSITX_TBG_DATA 0xCADE4ECE
+
+# define DSITX_DSC_PPS_BUFFER_SIZE 32
+
+/* DPHY Timeouts */
+# define DSITX_DPHY_TIME_CLK_DIV_RATIO 1
+# define DSITX_DPHY_TIME_HS_TX_TIMEOUT 30000
+# define DSITX_DPHY_TIME_LP_RX_TIMEOUT 30000
+
+/* PHY config */
+# define DSITX_PHY_WAIT_BURST_TIME 10
+
+# define DSITX_ULP_MODE_ENABLED 0
+
+#endif
+
diff --git a/packages/ti/drv/dss/src/csl/dsi/src/dsitx_sanity.c b/packages/ti/drv/dss/src/csl/dsi/src/dsitx_sanity.c
--- /dev/null
@@ -0,0 +1,1794 @@
+/**********************************************************************
+ * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ **********************************************************************
+ * WARNING: This file is auto-generated using api-generator utility.
+ * api-generator: 13.00.31660be
+ * Do not edit it manually.
+ **********************************************************************
+ * Cadence Core Driver for MIPI DSITX Host Controller
+ **********************************************************************/
+
+/* parasoft-begin-suppress METRICS-18-3 "Follow the Cyclomatic Complexity limit of 10" */
+/* parasoft-begin-suppress METRICS-36-3 "A function should not be called from more than 5 different functions" */
+/* parasoft-begin-suppress METRICS-39-3 "The value of VOCF metric for a function should not be higher than 4" */
+/* parasoft-begin-suppress METRICS-41-3 "Number of blocks of comments per statement" */
+/* parasoft-begin-suppress MISRA2012-RULE-8_7 "Functions and objects should not be defined with external linkage if they are referenced in only one translation unit" */
+
+/**
+ * This file contains sanity API functions. The purpose of sanity functions
+ * is to check input parameters validity. They take the same parameters as
+ * original API functions and return 0 on success or CDN_EINVAL on wrong parameter
+ * value(s).
+ */
+
+#include "src/csl/dsi/csl_dsi.h"
+#include "dsitx_priv.h"
+#include "dsitx_sanity.h"
+
+/**
+ * Function to validate struct DphyPwrRstConfig
+ *
+ * @param[in] obj pointer to struct to be verified
+ * @returns 0 for valid
+ * @returns CDN_EINVAL for invalid
+ */
+uint32_t DSITX_DphyPwrRstConfigSF(const DSITX_DphyPwrRstConfig *obj)
+{
+ uint32_t ret = 0;
+
+ if (obj == NULL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ if (obj->dphyDRstb > (0xFU))
+ {
+ ret = CDN_EINVAL;
+ }
+ if (obj->dphyDPdn > (0xFU))
+ {
+ ret = CDN_EINVAL;
+ }
+ }
+
+ return ret;
+}
+
+
+/**
+ * Function to validate struct DphyConfig
+ *
+ * @param[in] obj pointer to struct to be verified
+ * @returns 0 for valid
+ * @returns CDN_EINVAL for invalid
+ */
+uint32_t DSITX_DphyConfigSF(const DSITX_DphyConfig *obj)
+{
+ uint32_t ret = 0;
+
+ if (obj == NULL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ if (obj->clkDivisionRatio > (0xBU))
+ {
+ ret = CDN_EINVAL;
+ }
+ if (obj->hstxTimeout > (0x3FFFFU))
+ {
+ ret = CDN_EINVAL;
+ }
+ if (obj->lprxTimeout > (0x3FFFFU))
+ {
+ ret = CDN_EINVAL;
+ }
+ if (obj->clkLaneUlpTimeout > (0x1FFU))
+ {
+ ret = CDN_EINVAL;
+ }
+ if (obj->dataLaneUlpTimeout > (0x1FFU))
+ {
+ ret = CDN_EINVAL;
+ }
+ }
+
+ return ret;
+}
+
+
+/**
+ * Function to validate struct DataPathConfig
+ *
+ * @param[in] obj pointer to struct to be verified
+ * @returns 0 for valid
+ * @returns CDN_EINVAL for invalid
+ */
+uint32_t DSITX_DataPathConfigSF(const DSITX_DataPathConfig *obj)
+{
+ uint32_t ret = 0;
+
+ if (obj == NULL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ if (
+ (obj->interfaceMode != DSITX_IF_MODE_COMMAND) &&
+ (obj->interfaceMode != DSITX_IF_MODE_VIDEO)
+ )
+ {
+ ret = CDN_EINVAL;
+ }
+ if (
+ (obj->videoIfSelect != DSITX_VID_IF_SELECT_IF1) &&
+ (obj->videoIfSelect != DSITX_VID_IF_SELECT_IF2) &&
+ (obj->videoIfSelect != DSITX_VID_IF_SELECT_IF3)
+ )
+ {
+ ret = CDN_EINVAL;
+ }
+ }
+
+ return ret;
+}
+
+
+/**
+ * Function to validate struct PhyConfig
+ *
+ * @param[in] obj pointer to struct to be verified
+ * @returns 0 for valid
+ * @returns CDN_EINVAL for invalid
+ */
+uint32_t DSITX_PhyConfigSF(const DSITX_PhyConfig *obj)
+{
+ uint32_t ret = 0;
+
+ if (obj == NULL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ if ((obj->waitBurstTime < (0x1U)) || (obj->waitBurstTime > (0xFU)))
+ {
+ ret = CDN_EINVAL;
+ }
+ }
+
+ return ret;
+}
+
+
+/**
+ * Function to validate struct Video3dConfig
+ *
+ * @param[in] obj pointer to struct to be verified
+ * @returns 0 for valid
+ * @returns CDN_EINVAL for invalid
+ */
+uint32_t DSITX_Video3dConfigSF(const DSITX_Video3dConfig *obj)
+{
+ uint32_t ret = 0;
+
+ if (obj == NULL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ if (
+ (obj->vidSync3dMode != DSITX_VIDEO_MODE_2D) &&
+ (obj->vidSync3dMode != DSITX_VIDEO_MODE_PORTRAIT) &&
+ (obj->vidSync3dMode != DSITX_VIDEO_MODE_LANDSCAPE)
+ )
+ {
+ ret = CDN_EINVAL;
+ }
+ if (
+ (obj->vidSync3dFormat != DSITX_VIDEO_FORMAT_LINE) &&
+ (obj->vidSync3dFormat != DSITX_VIDEO_FORMAT_FRAME) &&
+ (obj->vidSync3dFormat != DSITX_VIDEO_FORMAT_PIXEL)
+ )
+ {
+ ret = CDN_EINVAL;
+ }
+ if (
+ (obj->vidVsync3dLr != DSITX_VIDEO_START_LEFT) &&
+ (obj->vidVsync3dLr != DSITX_VIDEO_START_RIGHT)
+ )
+ {
+ ret = CDN_EINVAL;
+ }
+ }
+
+ return ret;
+}
+
+
+/**
+ * Function to validate struct CommandModeSettings
+ *
+ * @param[in] obj pointer to struct to be verified
+ * @returns 0 for valid
+ * @returns CDN_EINVAL for invalid
+ */
+uint32_t DSITX_CommandModeSettingsSF(const DSITX_CommandModeSettings *obj)
+{
+ uint32_t ret = 0;
+
+ if (obj == NULL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ if (obj->vcIdIf1 > (0x3U))
+ {
+ ret = CDN_EINVAL;
+ }
+ if (obj->vcIdIf3 > (0x3U))
+ {
+ ret = CDN_EINVAL;
+ }
+ if (obj->teTimeout > (0x0FFFU))
+ {
+ ret = CDN_EINVAL;
+ }
+ if (
+ (obj->arbPriority != DSITX_CMD_ARB_PRIORITY_INIT) &&
+ (obj->arbPriority != DSITX_CMD_ARB_PRIORITY_SDI) &&
+ (obj->arbPriority != DSITX_CMD_ARB_PRIORITY_DSC)
+ )
+ {
+ ret = CDN_EINVAL;
+ }
+ if (
+ (obj->arbMode != DSITX_CMD_ARBITRATION_MODE_FIXED) &&
+ (obj->arbMode != DSITX_CMD_ARBITRATION_MODE_ROUND_ROBIN)
+ )
+ {
+ ret = CDN_EINVAL;
+ }
+ }
+
+ return ret;
+}
+
+
+/**
+ * Function to validate struct VideoSize
+ *
+ * @param[in] obj pointer to struct to be verified
+ * @returns 0 for valid
+ * @returns CDN_EINVAL for invalid
+ */
+uint32_t DSITX_VideoSizeSF(const DSITX_VideoSize *obj)
+{
+ uint32_t ret = 0;
+
+ if (obj == NULL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ if ((obj->vsa < (0x1U)) || (obj->vsa > (0x3FU)))
+ {
+ ret = CDN_EINVAL;
+ }
+ if (obj->vbp > (0x3FU))
+ {
+ ret = CDN_EINVAL;
+ }
+ if (obj->vfp < (0x1U))
+ {
+ ret = CDN_EINVAL;
+ }
+ if ((obj->vact < (0x1U)) || (obj->vact > (0x1FFFU)))
+ {
+ ret = CDN_EINVAL;
+ }
+ if (obj->hsa > (0x3FFU))
+ {
+ ret = CDN_EINVAL;
+ }
+ if (obj->hfp > (0x7FFU))
+ {
+ ret = CDN_EINVAL;
+ }
+ if (obj->rgb > (0x7FFFU))
+ {
+ ret = CDN_EINVAL;
+ }
+ if (obj->blkEolPacket > (0x7FFFU))
+ {
+ ret = CDN_EINVAL;
+ }
+ if (obj->blkLineEventPacket > (0x7FFFU))
+ {
+ ret = CDN_EINVAL;
+ }
+ if (obj->blkLinePulsePacket > (0x7FFFU))
+ {
+ ret = CDN_EINVAL;
+ }
+ }
+
+ return ret;
+}
+
+
+/**
+ * Function to validate struct VcaConfig
+ *
+ * @param[in] obj pointer to struct to be verified
+ * @returns 0 for valid
+ * @returns CDN_EINVAL for invalid
+ */
+uint32_t DSITX_VcaConfigSF(const DSITX_VcaConfig *obj)
+{
+ uint32_t ret = 0;
+
+ if (obj == NULL)
+ {
+ ret = CDN_EINVAL;
+ }
+
+ return ret;
+}
+
+
+/**
+ * Function to validate struct VideoModeSettings
+ *
+ * @param[in] obj pointer to struct to be verified
+ * @returns 0 for valid
+ * @returns CDN_EINVAL for invalid
+ */
+uint32_t DSITX_VideoModeSettingsSF(const DSITX_VideoModeSettings *obj)
+{
+ uint32_t ret = 0;
+
+ if (obj == NULL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ if (
+ (obj->startMode != DSITX_VID_START_MODE_START_ON_VSYNC)
+ )
+ {
+ ret = CDN_EINVAL;
+ }
+ if (
+ (obj->stopMode != DSITX_VID_STOP_MODE_STOP_INIT) &&
+ (obj->stopMode != DSITX_VID_STOP_MODE_STOP_JUST_BEFORE_VSYNC)
+ )
+ {
+ ret = CDN_EINVAL;
+ }
+ if (obj->vidId > (0x3U))
+ {
+ ret = CDN_EINVAL;
+ }
+ if (obj->vidIdSdfd > (0x3U))
+ {
+ ret = CDN_EINVAL;
+ }
+ if (
+ (obj->header != DSITX_VID_DATA_TYPE_DEFAULT) &&
+ (obj->header != DSITX_VID_DATA_TYPE_YCBCR_20) &&
+ (obj->header != DSITX_VID_DATA_TYPE_YCBCR_24) &&
+ (obj->header != DSITX_VID_DATA_TYPE_YCBCR_16) &&
+ (obj->header != DSITX_VID_DATA_TYPE_RGB_30) &&
+ (obj->header != DSITX_VID_DATA_TYPE_RGB_36) &&
+ (obj->header != DSITX_VID_DATA_TYPE_YCBCR_12) &&
+ (obj->header != DSITX_VID_DATA_TYPE_RGB_16) &&
+ (obj->header != DSITX_VID_DATA_TYPE_RGB_18) &&
+ (obj->header != DSITX_VID_DATA_TYPE_RGB_18_LOOSELY) &&
+ (obj->header != DSITX_VID_DATA_TYPE_RGB_24)
+ )
+ {
+ ret = CDN_EINVAL;
+ }
+ if (
+ (obj->vidPixelMode != DSITX_VID_PIXEL_MODE_RGB_16) &&
+ (obj->vidPixelMode != DSITX_VID_PIXEL_MODE_RGB_18) &&
+ (obj->vidPixelMode != DSITX_VID_PIXEL_MODE_RGB_18_LOOSELY) &&
+ (obj->vidPixelMode != DSITX_VID_PIXEL_MODE_RGB_24) &&
+ (obj->vidPixelMode != DSITX_VID_PIXEL_MODE_RGB_30) &&
+ (obj->vidPixelMode != DSITX_VID_PIXEL_MODE_RGB_36) &&
+ (obj->vidPixelMode != DSITX_VID_PIXEL_MODE_YCBCR_12) &&
+ (obj->vidPixelMode != DSITX_VID_PIXEL_MODE_YCBCR_16) &&
+ (obj->vidPixelMode != DSITX_VID_PIXEL_MODE_YCBCR_20) &&
+ (obj->vidPixelMode != DSITX_VID_PIXEL_MODE_YCBCR_24)
+ )
+ {
+ ret = CDN_EINVAL;
+ }
+ if (
+ (obj->blkLineMode != DSITX_VID_BLK_MODE_NULL_PACKET) &&
+ (obj->blkLineMode != DSITX_VID_BLK_MODE_BLANKING_PACKET) &&
+ (obj->blkLineMode != DSITX_VID_BLK_MODE_LP)
+ )
+ {
+ ret = CDN_EINVAL;
+ }
+ if (
+ (obj->blkEolMode != DSITX_VID_BLK_MODE_NULL_PACKET) &&
+ (obj->blkEolMode != DSITX_VID_BLK_MODE_BLANKING_PACKET) &&
+ (obj->blkEolMode != DSITX_VID_BLK_MODE_LP)
+ )
+ {
+ ret = CDN_EINVAL;
+ }
+ if (
+ (obj->recoveryMode != DSITX_CONTINUE_TILL_NEXT_HSYNC) &&
+ (obj->recoveryMode != DSITX_CONTINUE_UNTIL_NEXT_STOP_POINT) &&
+ (obj->recoveryMode != DSITX_CONTINUE_TILL_NEXT_VSYNC)
+ )
+ {
+ ret = CDN_EINVAL;
+ }
+ if (obj->fieldSwitch > (0x1U))
+ {
+ ret = CDN_EINVAL;
+ }
+ if (obj->blkEolDuration > (0x7FFFU))
+ {
+ ret = CDN_EINVAL;
+ }
+ if (DSITX_ErrorColorSF(&obj->errColor) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ if (obj->regWakeupTime > (0x7FFU))
+ {
+ ret = CDN_EINVAL;
+ }
+ if (obj->regLineDuration > (0x1FFFFU))
+ {
+ ret = CDN_EINVAL;
+ }
+ }
+
+ return ret;
+}
+
+
+/**
+ * Function to validate struct TestVideoModeConfig
+ *
+ * @param[in] obj pointer to struct to be verified
+ * @returns 0 for valid
+ * @returns CDN_EINVAL for invalid
+ */
+uint32_t DSITX_TestVideoModeConfigSF(const DSITX_TestVideoModeConfig *obj)
+{
+ uint32_t ret = 0;
+
+ if (obj == NULL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ if (
+ (obj->stripeSize != DSITX_TVG_STRIPE_SIZE_1) &&
+ (obj->stripeSize != DSITX_TVG_STRIPE_SIZE_2) &&
+ (obj->stripeSize != DSITX_TVG_STRIPE_SIZE_4) &&
+ (obj->stripeSize != DSITX_TVG_STRIPE_SIZE_8) &&
+ (obj->stripeSize != DSITX_TVG_STRIPE_SIZE_16) &&
+ (obj->stripeSize != DSITX_TVG_STRIPE_SIZE_32) &&
+ (obj->stripeSize != DSITX_TVG_STRIPE_SIZE_64) &&
+ (obj->stripeSize != DSITX_TVG_STRIPE_SIZE_128)
+ )
+ {
+ ret = CDN_EINVAL;
+ }
+ if (
+ (obj->displayMode != DSITX_TVG_MODE_SINGLE_COLOR) &&
+ (obj->displayMode != DSITX_TVG_MODE_VERTICAL_STRIPES) &&
+ (obj->displayMode != DSITX_TVG_MODE_HORIZONTAL_STRIPES)
+ )
+ {
+ ret = CDN_EINVAL;
+ }
+ if (
+ (obj->stopMode != DSITX_TVG_STOP_MODE_AT_END_OF_FRAME) &&
+ (obj->stopMode != DSITX_TVG_STOP_MODE_AT_END_OF_LINE) &&
+ (obj->stopMode != DSITX_TVG_STOP_MODE_IMMEDIATE)
+ )
+ {
+ ret = CDN_EINVAL;
+ }
+ if (obj->linesPerFrame > (0x1FFFU))
+ {
+ ret = CDN_EINVAL;
+ }
+ if (obj->bytesPerLine > (0x7FFFU))
+ {
+ ret = CDN_EINVAL;
+ }
+ if (DSITX_ColorSF(&obj->color1) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ if (DSITX_ColorSF(&obj->color2) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ }
+
+ return ret;
+}
+
+
+/**
+ * Function to validate struct DsiLinkConfig
+ *
+ * @param[in] obj pointer to struct to be verified
+ * @returns 0 for valid
+ * @returns CDN_EINVAL for invalid
+ */
+uint32_t DSITX_DsiLinkConfigSF(const DSITX_DsiLinkConfig *obj)
+{
+ uint32_t ret = 0;
+
+ if (obj == NULL)
+ {
+ ret = CDN_EINVAL;
+ }
+
+ return ret;
+}
+
+
+/**
+ * Function to validate struct DirectCommandRequest
+ *
+ * @param[in] obj pointer to struct to be verified
+ * @returns 0 for valid
+ * @returns CDN_EINVAL for invalid
+ */
+uint32_t DSITX_DirectCommandRequestSF(const DSITX_DirectCommandRequest *obj)
+{
+ uint32_t ret = 0;
+
+ if (obj == NULL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ if (obj->vcId > (0x3U))
+ {
+ ret = CDN_EINVAL;
+ }
+ if (obj->cmdSize > (0x10U))
+ {
+ ret = CDN_EINVAL;
+ }
+ if (obj->head > (0x3FU))
+ {
+ ret = CDN_EINVAL;
+ }
+ if (
+ (obj->type != DSITX_DCR_TYPE_WRITE) &&
+ (obj->type != DSITX_DCR_TYPE_READ) &&
+ (obj->type != DSITX_DCR_TYPE_TE) &&
+ (obj->type != DSITX_DCR_TYPE_TRIGGER) &&
+ (obj->type != DSITX_DCR_TYPE_BTA)
+ )
+ {
+ ret = CDN_EINVAL;
+ }
+ }
+
+ return ret;
+}
+
+
+/**
+ * Function to validate struct TestGeneric
+ *
+ * @param[in] obj pointer to struct to be verified
+ * @returns 0 for valid
+ * @returns CDN_EINVAL for invalid
+ */
+uint32_t DSITX_TestGenericSF(const DSITX_TestGeneric *obj)
+{
+ uint32_t ret = 0;
+
+ if (obj == NULL)
+ {
+ ret = CDN_EINVAL;
+ }
+
+ return ret;
+}
+
+
+/**
+ * Function to validate struct Config
+ *
+ * @param[in] obj pointer to struct to be verified
+ * @returns 0 for valid
+ * @returns CDN_EINVAL for invalid
+ */
+uint32_t DSITX_ConfigSF(const DSITX_Config *obj)
+{
+ uint32_t ret = 0;
+
+ if (obj == NULL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ if ((obj->numOfLanes < (0x1U)) || (obj->numOfLanes > (0x4U)))
+ {
+ ret = CDN_EINVAL;
+ }
+ }
+
+ return ret;
+}
+
+
+/**
+ * Function to validate struct PrivateData
+ *
+ * @param[in] obj pointer to struct to be verified
+ * @returns 0 for valid
+ * @returns CDN_EINVAL for invalid
+ */
+uint32_t DSITX_PrivateDataSF(const DSITX_PrivateData *obj)
+{
+ uint32_t ret = 0;
+
+ if (obj == NULL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ if (obj->numOfLanes > (0x4U))
+ {
+ ret = CDN_EINVAL;
+ }
+ }
+
+ return ret;
+}
+
+
+/**
+ * Function to validate struct Color
+ *
+ * @param[in] obj pointer to struct to be verified
+ * @returns 0 for valid
+ * @returns CDN_EINVAL for invalid
+ */
+uint32_t DSITX_ColorSF(const DSITX_Color *obj)
+{
+ uint32_t ret = 0;
+
+ if (obj == NULL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ if (obj->r > (0xFFFU))
+ {
+ ret = CDN_EINVAL;
+ }
+ if (obj->g > (0xFFFU))
+ {
+ ret = CDN_EINVAL;
+ }
+ if (obj->b > (0xFFFU))
+ {
+ ret = CDN_EINVAL;
+ }
+ }
+
+ return ret;
+}
+
+
+/**
+ * Function to validate struct ErrorColor
+ *
+ * @param[in] obj pointer to struct to be verified
+ * @returns 0 for valid
+ * @returns CDN_EINVAL for invalid
+ */
+uint32_t DSITX_ErrorColorSF(const DSITX_ErrorColor *obj)
+{
+ uint32_t ret = 0;
+
+ if (obj == NULL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ if (obj->r > (0xFFFU))
+ {
+ ret = CDN_EINVAL;
+ }
+ if (obj->g > (0xFFFU))
+ {
+ ret = CDN_EINVAL;
+ }
+ if (obj->b > (0xFFFU))
+ {
+ ret = CDN_EINVAL;
+ }
+ if (obj->padValue > (0xFFFU))
+ {
+ ret = CDN_EINVAL;
+ }
+ }
+
+ return ret;
+}
+
+
+/**
+ * A common function to check the validity of API functions with
+ * following parameter types
+ * @param[in] config Proposed driver/hardware configuration.
+ * @param[out] sysReq Returns the memory requirements for given configuration in field privDataSize.
+ * @return 0 success
+ * @return CDN_EINVAL invalid parameters
+ */
+uint32_t DSITX_SanityFunction1(const DSITX_Config* config, const DSITX_SysReq* sysReq)
+{
+ /* Declaring return variable */
+ uint32_t ret = 0;
+
+ if (sysReq == NULL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (DSITX_ConfigSF(config) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ /*
+ * All 'if ... else if' constructs shall be terminated with an 'else' statement
+ * (MISRA2012-RULE-15_7-3)
+ */
+ }
+
+ return ret;
+}
+
+
+/**
+ * A common function to check the validity of API functions with
+ * following parameter types
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] config Specifies driver/hardware configuration.
+ * @return 0 success
+ * @return CDN_EINVAL invalid parameters
+ */
+uint32_t DSITX_SanityFunction2(const DSITX_PrivateData* pD, const DSITX_Config* config)
+{
+ /* Declaring return variable */
+ uint32_t ret = 0;
+
+ if (DSITX_PrivateDataSF(pD) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (DSITX_ConfigSF(config) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ /*
+ * All 'if ... else if' constructs shall be terminated with an 'else' statement
+ * (MISRA2012-RULE-15_7-3)
+ */
+ }
+
+ return ret;
+}
+
+
+/**
+ * A common function to check the validity of API functions with
+ * following parameter types
+ * @param[in] pD Driver instance data filled by init.
+ * @return 0 success
+ * @return CDN_EINVAL invalid parameters
+ */
+uint32_t DSITX_SanityFunction3(const DSITX_PrivateData* pD)
+{
+ /* Declaring return variable */
+ uint32_t ret = 0;
+
+ if (DSITX_PrivateDataSF(pD) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+
+ return ret;
+}
+
+
+/**
+ * A common function to check the validity of API functions with
+ * following parameter types
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] config Pointer to structure which specifies DPHY configuration.
+ * @return 0 success
+ * @return CDN_EINVAL invalid parameters
+ */
+uint32_t DSITX_SanityFunction7(const DSITX_PrivateData* pD, const DSITX_DphyConfig* config)
+{
+ /* Declaring return variable */
+ uint32_t ret = 0;
+
+ if (DSITX_PrivateDataSF(pD) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (DSITX_DphyConfigSF(config) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ /*
+ * All 'if ... else if' constructs shall be terminated with an 'else' statement
+ * (MISRA2012-RULE-15_7-3)
+ */
+ }
+
+ return ret;
+}
+
+
+/**
+ * A common function to check the validity of API functions with
+ * following parameter types
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] config Pointer to structure to which DPHY configuration will be written.
+ * @return 0 success
+ * @return CDN_EINVAL invalid parameters
+ */
+uint32_t DSITX_SanityFunction8(const DSITX_PrivateData* pD, const DSITX_DphyConfig* config)
+{
+ /* Declaring return variable */
+ uint32_t ret = 0;
+
+ if (config == NULL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (DSITX_PrivateDataSF(pD) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ /*
+ * All 'if ... else if' constructs shall be terminated with an 'else' statement
+ * (MISRA2012-RULE-15_7-3)
+ */
+ }
+
+ return ret;
+}
+
+
+/**
+ * A common function to check the validity of API functions with
+ * following parameter types
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] config Pointer to structure containing Data Path configuration.
+ * @return 0 success
+ * @return CDN_EINVAL invalid parameters
+ */
+uint32_t DSITX_SanityFunction9(const DSITX_PrivateData* pD, const DSITX_DataPathConfig* config)
+{
+ /* Declaring return variable */
+ uint32_t ret = 0;
+
+ if (DSITX_PrivateDataSF(pD) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (DSITX_DataPathConfigSF(config) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ /*
+ * All 'if ... else if' constructs shall be terminated with an 'else' statement
+ * (MISRA2012-RULE-15_7-3)
+ */
+ }
+
+ return ret;
+}
+
+
+/**
+ * A common function to check the validity of API functions with
+ * following parameter types
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] config Pointer to structure to which Data Path configuration will be written.
+ * @return 0 success
+ * @return CDN_EINVAL invalid parameters
+ */
+uint32_t DSITX_SanityFunction10(const DSITX_PrivateData* pD, const DSITX_DataPathConfig* config)
+{
+ /* Declaring return variable */
+ uint32_t ret = 0;
+
+ if (config == NULL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (DSITX_PrivateDataSF(pD) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ /*
+ * All 'if ... else if' constructs shall be terminated with an 'else' statement
+ * (MISRA2012-RULE-15_7-3)
+ */
+ }
+
+ return ret;
+}
+
+
+/**
+ * A common function to check the validity of API functions with
+ * following parameter types
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] config Pointer to structure containing PHY configuration.
+ * @return 0 success
+ * @return CDN_EINVAL invalid parameters
+ */
+uint32_t DSITX_SanityFunction11(const DSITX_PrivateData* pD, const DSITX_PhyConfig* config)
+{
+ /* Declaring return variable */
+ uint32_t ret = 0;
+
+ if (DSITX_PrivateDataSF(pD) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (DSITX_PhyConfigSF(config) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ /*
+ * All 'if ... else if' constructs shall be terminated with an 'else' statement
+ * (MISRA2012-RULE-15_7-3)
+ */
+ }
+
+ return ret;
+}
+
+
+/**
+ * A common function to check the validity of API functions with
+ * following parameter types
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] config Pointer to structure to which PHY configuration will be written.
+ * @return 0 success
+ * @return CDN_EINVAL invalid parameters
+ */
+uint32_t DSITX_SanityFunction12(const DSITX_PrivateData* pD, const DSITX_PhyConfig* config)
+{
+ /* Declaring return variable */
+ uint32_t ret = 0;
+
+ if (config == NULL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (DSITX_PrivateDataSF(pD) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ /*
+ * All 'if ... else if' constructs shall be terminated with an 'else' statement
+ * (MISRA2012-RULE-15_7-3)
+ */
+ }
+
+ return ret;
+}
+
+
+/**
+ * A common function to check the validity of API functions with
+ * following parameter types
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] cfg Pointer to structure containing configuration.
+ * @return 0 success
+ * @return CDN_EINVAL invalid parameters
+ */
+uint32_t DSITX_SanityFunction13(const DSITX_PrivateData* pD, const DSITX_DphyPwrRstConfig* cfg)
+{
+ /* Declaring return variable */
+ uint32_t ret = 0;
+
+ if (DSITX_PrivateDataSF(pD) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (DSITX_DphyPwrRstConfigSF(cfg) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ /*
+ * All 'if ... else if' constructs shall be terminated with an 'else' statement
+ * (MISRA2012-RULE-15_7-3)
+ */
+ }
+
+ return ret;
+}
+
+
+/**
+ * A common function to check the validity of API functions with
+ * following parameter types
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] cfg Pointer to structure to which DPHY Power and Reset Control
+ * configuration will be written.
+ * @return 0 success
+ * @return CDN_EINVAL invalid parameters
+ */
+uint32_t DSITX_SanityFunction14(const DSITX_PrivateData* pD, const DSITX_DphyPwrRstConfig* cfg)
+{
+ /* Declaring return variable */
+ uint32_t ret = 0;
+
+ if (cfg == NULL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (DSITX_PrivateDataSF(pD) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ /*
+ * All 'if ... else if' constructs shall be terminated with an 'else' statement
+ * (MISRA2012-RULE-15_7-3)
+ */
+ }
+
+ return ret;
+}
+
+
+/**
+ * A common function to check the validity of API functions with
+ * following parameter types
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] config Pointer to structure containing DSITX Link configuration.
+ * @return 0 success
+ * @return CDN_EINVAL invalid parameters
+ */
+uint32_t DSITX_SanityFunction15(const DSITX_PrivateData* pD, const DSITX_DsiLinkConfig* config)
+{
+ /* Declaring return variable */
+ uint32_t ret = 0;
+
+ if (DSITX_PrivateDataSF(pD) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (DSITX_DsiLinkConfigSF(config) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ /*
+ * All 'if ... else if' constructs shall be terminated with an 'else' statement
+ * (MISRA2012-RULE-15_7-3)
+ */
+ }
+
+ return ret;
+}
+
+
+/**
+ * A common function to check the validity of API functions with
+ * following parameter types
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] config Pointer to structure to which DSITX Link setup will be stored.
+ * @return 0 success
+ * @return CDN_EINVAL invalid parameters
+ */
+uint32_t DSITX_SanityFunction16(const DSITX_PrivateData* pD, const DSITX_DsiLinkConfig* config)
+{
+ /* Declaring return variable */
+ uint32_t ret = 0;
+
+ if (config == NULL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (DSITX_PrivateDataSF(pD) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ /*
+ * All 'if ... else if' constructs shall be terminated with an 'else' statement
+ * (MISRA2012-RULE-15_7-3)
+ */
+ }
+
+ return ret;
+}
+
+
+/**
+ * A common function to check the validity of API functions with
+ * following parameter types
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] config Pointer to structure to which DSITX IP configuration will be stored.
+ * @return 0 success
+ * @return CDN_EINVAL invalid parameters
+ */
+uint32_t DSITX_SanityFunction17(const DSITX_PrivateData* pD, const DSITX_IpConf* config)
+{
+ /* Declaring return variable */
+ uint32_t ret = 0;
+
+ if (config == NULL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (DSITX_PrivateDataSF(pD) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ /*
+ * All 'if ... else if' constructs shall be terminated with an 'else' statement
+ * (MISRA2012-RULE-15_7-3)
+ */
+ }
+
+ return ret;
+}
+
+
+/**
+ * A common function to check the validity of API functions with
+ * following parameter types
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] id Pointer to structure where DSITX version information will be stored.
+ * @return 0 success
+ * @return CDN_EINVAL invalid parameters
+ */
+uint32_t DSITX_SanityFunction18(const DSITX_PrivateData* pD, const DSITX_HwIdAndVersion* id)
+{
+ /* Declaring return variable */
+ uint32_t ret = 0;
+
+ if (id == NULL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (DSITX_PrivateDataSF(pD) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ /*
+ * All 'if ... else if' constructs shall be terminated with an 'else' statement
+ * (MISRA2012-RULE-15_7-3)
+ */
+ }
+
+ return ret;
+}
+
+
+/**
+ * A common function to check the validity of API functions with
+ * following parameter types
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] cmdMode Pointer to structure containing detailed information about
+ * Command Mode configuration.
+ * @return 0 success
+ * @return CDN_EINVAL invalid parameters
+ */
+uint32_t DSITX_SanityFunction19(const DSITX_PrivateData* pD, const DSITX_CommandModeSettings* cmdMode)
+{
+ /* Declaring return variable */
+ uint32_t ret = 0;
+
+ if (DSITX_PrivateDataSF(pD) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (DSITX_CommandModeSettingsSF(cmdMode) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ /*
+ * All 'if ... else if' constructs shall be terminated with an 'else' statement
+ * (MISRA2012-RULE-15_7-3)
+ */
+ }
+
+ return ret;
+}
+
+
+/**
+ * A common function to check the validity of API functions with
+ * following parameter types
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] cmdMode Pointer to structure to which detailed information about
+ * Command Mode configuration will be written.
+ * @return 0 success
+ * @return CDN_EINVAL invalid parameters
+ */
+uint32_t DSITX_SanityFunction20(const DSITX_PrivateData* pD, const DSITX_CommandModeSettings* cmdMode)
+{
+ /* Declaring return variable */
+ uint32_t ret = 0;
+
+ if (cmdMode == NULL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (DSITX_PrivateDataSF(pD) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ /*
+ * All 'if ... else if' constructs shall be terminated with an 'else' statement
+ * (MISRA2012-RULE-15_7-3)
+ */
+ }
+
+ return ret;
+}
+
+
+/**
+ * A common function to check the validity of API functions with
+ * following parameter types
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] vidMode Pointer to structure containing Video Mode configuration.
+ * @return 0 success
+ * @return CDN_EINVAL invalid parameters
+ */
+uint32_t DSITX_SanityFunction21(const DSITX_PrivateData* pD, const DSITX_VideoModeSettings* vidMode)
+{
+ /* Declaring return variable */
+ uint32_t ret = 0;
+
+ if (DSITX_PrivateDataSF(pD) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (DSITX_VideoModeSettingsSF(vidMode) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ /*
+ * All 'if ... else if' constructs shall be terminated with an 'else' statement
+ * (MISRA2012-RULE-15_7-3)
+ */
+ }
+
+ return ret;
+}
+
+
+/**
+ * A common function to check the validity of API functions with
+ * following parameter types
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] vidMode Pointer to structure to which Video Mode configuration will be written.
+ * @return 0 success
+ * @return CDN_EINVAL invalid parameters
+ */
+uint32_t DSITX_SanityFunction22(const DSITX_PrivateData* pD, const DSITX_VideoModeSettings* vidMode)
+{
+ /* Declaring return variable */
+ uint32_t ret = 0;
+
+ if (vidMode == NULL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (DSITX_PrivateDataSF(pD) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ /*
+ * All 'if ... else if' constructs shall be terminated with an 'else' statement
+ * (MISRA2012-RULE-15_7-3)
+ */
+ }
+
+ return ret;
+}
+
+
+/**
+ * A common function to check the validity of API functions with
+ * following parameter types
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] vca Pointer to structure containing Video Command Arbiter configuration.
+ * @return 0 success
+ * @return CDN_EINVAL invalid parameters
+ */
+uint32_t DSITX_SanityFunction23(const DSITX_PrivateData* pD, const DSITX_VcaConfig* vca)
+{
+ /* Declaring return variable */
+ uint32_t ret = 0;
+
+ if (DSITX_PrivateDataSF(pD) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (DSITX_VcaConfigSF(vca) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ /*
+ * All 'if ... else if' constructs shall be terminated with an 'else' statement
+ * (MISRA2012-RULE-15_7-3)
+ */
+ }
+
+ return ret;
+}
+
+
+/**
+ * A common function to check the validity of API functions with
+ * following parameter types
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] vca Pointer to structure to which Video Command Arbiter configuration will be written.
+ * @return 0 success
+ * @return CDN_EINVAL invalid parameters
+ */
+uint32_t DSITX_SanityFunction24(const DSITX_PrivateData* pD, const DSITX_VcaConfig* vca)
+{
+ /* Declaring return variable */
+ uint32_t ret = 0;
+
+ if (vca == NULL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (DSITX_PrivateDataSF(pD) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ /*
+ * All 'if ... else if' constructs shall be terminated with an 'else' statement
+ * (MISRA2012-RULE-15_7-3)
+ */
+ }
+
+ return ret;
+}
+
+
+/**
+ * A common function to check the validity of API functions with
+ * following parameter types
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] vidSize Pointer to structure containing Video Size configuration.
+ * @return 0 success
+ * @return CDN_EINVAL invalid parameters
+ */
+uint32_t DSITX_SanityFunction25(const DSITX_PrivateData* pD, const DSITX_VideoSize* vidSize)
+{
+ /* Declaring return variable */
+ uint32_t ret = 0;
+
+ if (DSITX_PrivateDataSF(pD) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (DSITX_VideoSizeSF(vidSize) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ /*
+ * All 'if ... else if' constructs shall be terminated with an 'else' statement
+ * (MISRA2012-RULE-15_7-3)
+ */
+ }
+
+ return ret;
+}
+
+
+/**
+ * A common function to check the validity of API functions with
+ * following parameter types
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] vidSize Pointer to structure to which Video Size configuration will be written.
+ * @return 0 success
+ * @return CDN_EINVAL invalid parameters
+ */
+uint32_t DSITX_SanityFunction26(const DSITX_PrivateData* pD, const DSITX_VideoSize* vidSize)
+{
+ /* Declaring return variable */
+ uint32_t ret = 0;
+
+ if (vidSize == NULL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (DSITX_PrivateDataSF(pD) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ /*
+ * All 'if ... else if' constructs shall be terminated with an 'else' statement
+ * (MISRA2012-RULE-15_7-3)
+ */
+ }
+
+ return ret;
+}
+
+
+/**
+ * A common function to check the validity of API functions with
+ * following parameter types
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] config Pointer to structure containing Test Video Generator configuration.
+ * Value of the enabled field is ignored. Use startTvg function to enable TVG.
+ * @return 0 success
+ * @return CDN_EINVAL invalid parameters
+ */
+uint32_t DSITX_SanityFunction27(const DSITX_PrivateData* pD, const DSITX_TestVideoModeConfig* config)
+{
+ /* Declaring return variable */
+ uint32_t ret = 0;
+
+ if (DSITX_PrivateDataSF(pD) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (DSITX_TestVideoModeConfigSF(config) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ /*
+ * All 'if ... else if' constructs shall be terminated with an 'else' statement
+ * (MISRA2012-RULE-15_7-3)
+ */
+ }
+
+ return ret;
+}
+
+
+/**
+ * A common function to check the validity of API functions with
+ * following parameter types
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] config Pointer to structure to which received Test Video Generator
+ * configuration will be written.
+ * @return 0 success
+ * @return CDN_EINVAL invalid parameters
+ */
+uint32_t DSITX_SanityFunction28(const DSITX_PrivateData* pD, const DSITX_TestVideoModeConfig* config)
+{
+ /* Declaring return variable */
+ uint32_t ret = 0;
+
+ if (config == NULL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (DSITX_PrivateDataSF(pD) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ /*
+ * All 'if ... else if' constructs shall be terminated with an 'else' statement
+ * (MISRA2012-RULE-15_7-3)
+ */
+ }
+
+ return ret;
+}
+
+
+/**
+ * A common function to check the validity of API functions with
+ * following parameter types
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] dcr Pointer to structure containing detailed information about command.
+ * This structure will be updated by Core Driver during command
+ * execution. After passing it to Core Driver user shall not make
+ * any changes to its content until dcr status is set to completed
+ * or it is presented in callback function.
+ * @return 0 success
+ * @return CDN_EINVAL invalid parameters
+ */
+uint32_t DSITX_SanityFunction31(const DSITX_PrivateData* pD, const DSITX_DirectCommandRequest* dcr)
+{
+ /* Declaring return variable */
+ uint32_t ret = 0;
+
+ if (DSITX_PrivateDataSF(pD) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (DSITX_DirectCommandRequestSF(dcr) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ /*
+ * All 'if ... else if' constructs shall be terminated with an 'else' statement
+ * (MISRA2012-RULE-15_7-3)
+ */
+ }
+
+ return ret;
+}
+
+
+/**
+ * A common function to check the validity of API functions with
+ * following parameter types
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] test Pointer to structure containing control configuration.
+ * @return 0 success
+ * @return CDN_EINVAL invalid parameters
+ */
+uint32_t DSITX_SanityFunction38(const DSITX_PrivateData* pD, const DSITX_TestGeneric* test)
+{
+ /* Declaring return variable */
+ uint32_t ret = 0;
+
+ if (DSITX_PrivateDataSF(pD) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (DSITX_TestGenericSF(test) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ /*
+ * All 'if ... else if' constructs shall be terminated with an 'else' statement
+ * (MISRA2012-RULE-15_7-3)
+ */
+ }
+
+ return ret;
+}
+
+
+/**
+ * A common function to check the validity of API functions with
+ * following parameter types
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] test Pointer to structure to which control configuration will be
+ * written.
+ * @return 0 success
+ * @return CDN_EINVAL invalid parameters
+ */
+uint32_t DSITX_SanityFunction39(const DSITX_PrivateData* pD, const DSITX_TestGeneric* test)
+{
+ /* Declaring return variable */
+ uint32_t ret = 0;
+
+ if (test == NULL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (DSITX_PrivateDataSF(pD) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ /*
+ * All 'if ... else if' constructs shall be terminated with an 'else' statement
+ * (MISRA2012-RULE-15_7-3)
+ */
+ }
+
+ return ret;
+}
+
+
+/**
+ * A common function to check the validity of API functions with
+ * following parameter types
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[in] cfg Video 3D configuration.
+ * @return 0 success
+ * @return CDN_EINVAL invalid parameters
+ */
+uint32_t DSITX_SanityFunction40(const DSITX_PrivateData* pD, const DSITX_Video3dConfig* cfg)
+{
+ /* Declaring return variable */
+ uint32_t ret = 0;
+
+ if (DSITX_PrivateDataSF(pD) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (DSITX_Video3dConfigSF(cfg) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ /*
+ * All 'if ... else if' constructs shall be terminated with an 'else' statement
+ * (MISRA2012-RULE-15_7-3)
+ */
+ }
+
+ return ret;
+}
+
+
+/**
+ * A common function to check the validity of API functions with
+ * following parameter types
+ * @param[in] pD Driver state info specific to this instance.
+ * @param[out] cfg Video 3D configuration.
+ * @return 0 success
+ * @return CDN_EINVAL invalid parameters
+ */
+uint32_t DSITX_SanityFunction41(const DSITX_PrivateData* pD, const DSITX_Video3dConfig* cfg)
+{
+ /* Declaring return variable */
+ uint32_t ret = 0;
+
+ if (cfg == NULL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (DSITX_PrivateDataSF(pD) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ /*
+ * All 'if ... else if' constructs shall be terminated with an 'else' statement
+ * (MISRA2012-RULE-15_7-3)
+ */
+ }
+
+ return ret;
+}
+
+
+/**
+ * A common function to check the validity of API functions with
+ * following parameter types
+ * @param[in] pD Pointer to driver's private data object.
+ * @param[out] asfInfo Pointer to ASF information structure.
+ * @return 0 success
+ * @return CDN_EINVAL invalid parameters
+ */
+uint32_t DSITX_SanityFunction42(const DSITX_PrivateData* pD, const DSITX_AsfInfo* asfInfo)
+{
+ /* Declaring return variable */
+ uint32_t ret = 0;
+
+ if (asfInfo == NULL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else if (DSITX_PrivateDataSF(pD) == CDN_EINVAL)
+ {
+ ret = CDN_EINVAL;
+ }
+ else
+ {
+ /*
+ * All 'if ... else if' constructs shall be terminated with an 'else' statement
+ * (MISRA2012-RULE-15_7-3)
+ */
+ }
+
+ return ret;
+}
+
+/* parasoft-end-suppress MISRA2012-RULE-8_7 */
+/* parasoft-end-suppress METRICS-41-3 */
+/* parasoft-end-suppress METRICS-39-3 */
+/* parasoft-end-suppress METRICS-36-3 */
+/* parasoft-end-suppress METRICS-18-3 */
diff --git a/packages/ti/drv/dss/src/csl/dsi/src/dsitx_sanity.h b/packages/ti/drv/dss/src/csl/dsi/src/dsitx_sanity.h
--- /dev/null
@@ -0,0 +1,154 @@
+/**********************************************************************
+ * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ **********************************************************************
+ * WARNING: This file is auto-generated using api-generator utility.
+ * api-generator: 13.00.31660be
+ * Do not edit it manually.
+ **********************************************************************
+ * Cadence Core Driver for MIPI DSITX Host Controller
+ **********************************************************************/
+
+/* parasoft-begin-suppress METRICS-18-3 "Follow the Cyclomatic Complexity limit of 10" */
+/* parasoft-begin-suppress METRICS-36-3 "A function should not be called from more than 5 different functions" */
+/* parasoft-begin-suppress METRICS-39-3 "The value of VOCF metric for a function should not be higher than 4" */
+/* parasoft-begin-suppress METRICS-41-3 "Number of blocks of comments per statement" */
+/* parasoft-begin-suppress MISRA2012-RULE-8_7 "Functions and objects should not be defined with external linkage if they are referenced in only one translation unit" */
+
+/**
+ * This file contains sanity API functions. The purpose of sanity functions
+ * is to check input parameters validity. They take the same parameters as
+ * original API functions and return 0 on success or CDN_EINVAL on wrong parameter
+ * value(s).
+ */
+
+#ifndef DSITX_SANITY_H
+#define DSITX_SANITY_H
+
+
+uint32_t DSITX_ColorSF(const DSITX_Color *obj);
+uint32_t DSITX_CommandModeSettingsSF(const DSITX_CommandModeSettings *obj);
+uint32_t DSITX_ConfigSF(const DSITX_Config *obj);
+uint32_t DSITX_DataPathConfigSF(const DSITX_DataPathConfig *obj);
+uint32_t DSITX_DirectCommandRequestSF(const DSITX_DirectCommandRequest *obj);
+uint32_t DSITX_DphyConfigSF(const DSITX_DphyConfig *obj);
+uint32_t DSITX_DphyPwrRstConfigSF(const DSITX_DphyPwrRstConfig *obj);
+uint32_t DSITX_DsiLinkConfigSF(const DSITX_DsiLinkConfig *obj);
+uint32_t DSITX_ErrorColorSF(const DSITX_ErrorColor *obj);
+uint32_t DSITX_PhyConfigSF(const DSITX_PhyConfig *obj);
+uint32_t DSITX_PrivateDataSF(const DSITX_PrivateData *obj);
+uint32_t DSITX_TestGenericSF(const DSITX_TestGeneric *obj);
+uint32_t DSITX_TestVideoModeConfigSF(const DSITX_TestVideoModeConfig *obj);
+uint32_t DSITX_VcaConfigSF(const DSITX_VcaConfig *obj);
+uint32_t DSITX_Video3dConfigSF(const DSITX_Video3dConfig *obj);
+uint32_t DSITX_VideoModeSettingsSF(const DSITX_VideoModeSettings *obj);
+uint32_t DSITX_VideoSizeSF(const DSITX_VideoSize *obj);
+
+uint32_t DSITX_SanityFunction1(const DSITX_Config* config, const DSITX_SysReq* sysReq);
+uint32_t DSITX_SanityFunction2(const DSITX_PrivateData* pD, const DSITX_Config* config);
+uint32_t DSITX_SanityFunction3(const DSITX_PrivateData* pD);
+uint32_t DSITX_SanityFunction7(const DSITX_PrivateData* pD, const DSITX_DphyConfig* config);
+uint32_t DSITX_SanityFunction8(const DSITX_PrivateData* pD, const DSITX_DphyConfig* config);
+uint32_t DSITX_SanityFunction9(const DSITX_PrivateData* pD, const DSITX_DataPathConfig* config);
+uint32_t DSITX_SanityFunction10(const DSITX_PrivateData* pD, const DSITX_DataPathConfig* config);
+uint32_t DSITX_SanityFunction11(const DSITX_PrivateData* pD, const DSITX_PhyConfig* config);
+uint32_t DSITX_SanityFunction12(const DSITX_PrivateData* pD, const DSITX_PhyConfig* config);
+uint32_t DSITX_SanityFunction13(const DSITX_PrivateData* pD, const DSITX_DphyPwrRstConfig* cfg);
+uint32_t DSITX_SanityFunction14(const DSITX_PrivateData* pD, const DSITX_DphyPwrRstConfig* cfg);
+uint32_t DSITX_SanityFunction15(const DSITX_PrivateData* pD, const DSITX_DsiLinkConfig* config);
+uint32_t DSITX_SanityFunction16(const DSITX_PrivateData* pD, const DSITX_DsiLinkConfig* config);
+uint32_t DSITX_SanityFunction17(const DSITX_PrivateData* pD, const DSITX_IpConf* config);
+uint32_t DSITX_SanityFunction18(const DSITX_PrivateData* pD, const DSITX_HwIdAndVersion* id);
+uint32_t DSITX_SanityFunction19(const DSITX_PrivateData* pD, const DSITX_CommandModeSettings* cmdMode);
+uint32_t DSITX_SanityFunction20(const DSITX_PrivateData* pD, const DSITX_CommandModeSettings* cmdMode);
+uint32_t DSITX_SanityFunction21(const DSITX_PrivateData* pD, const DSITX_VideoModeSettings* vidMode);
+uint32_t DSITX_SanityFunction22(const DSITX_PrivateData* pD, const DSITX_VideoModeSettings* vidMode);
+uint32_t DSITX_SanityFunction23(const DSITX_PrivateData* pD, const DSITX_VcaConfig* vca);
+uint32_t DSITX_SanityFunction24(const DSITX_PrivateData* pD, const DSITX_VcaConfig* vca);
+uint32_t DSITX_SanityFunction25(const DSITX_PrivateData* pD, const DSITX_VideoSize* vidSize);
+uint32_t DSITX_SanityFunction26(const DSITX_PrivateData* pD, const DSITX_VideoSize* vidSize);
+uint32_t DSITX_SanityFunction27(const DSITX_PrivateData* pD, const DSITX_TestVideoModeConfig* config);
+uint32_t DSITX_SanityFunction28(const DSITX_PrivateData* pD, const DSITX_TestVideoModeConfig* config);
+uint32_t DSITX_SanityFunction31(const DSITX_PrivateData* pD, const DSITX_DirectCommandRequest* dcr);
+uint32_t DSITX_SanityFunction38(const DSITX_PrivateData* pD, const DSITX_TestGeneric* test);
+uint32_t DSITX_SanityFunction39(const DSITX_PrivateData* pD, const DSITX_TestGeneric* test);
+uint32_t DSITX_SanityFunction40(const DSITX_PrivateData* pD, const DSITX_Video3dConfig* cfg);
+uint32_t DSITX_SanityFunction41(const DSITX_PrivateData* pD, const DSITX_Video3dConfig* cfg);
+uint32_t DSITX_SanityFunction42(const DSITX_PrivateData* pD, const DSITX_AsfInfo* asfInfo);
+
+#define DSITX_ProbeSF DSITX_SanityFunction1
+#define DSITX_InitSF DSITX_SanityFunction2
+#define DSITX_IsrSF DSITX_SanityFunction3
+#define DSITX_StartSF DSITX_SanityFunction3
+#define DSITX_StopSF DSITX_SanityFunction3
+#define DSITX_DestroySF DSITX_SanityFunction3
+#define DSITX_SetDphyConfigSF DSITX_SanityFunction7
+#define DSITX_GetDphyConfigSF DSITX_SanityFunction8
+#define DSITX_SetDataPathConfigSF DSITX_SanityFunction9
+#define DSITX_GetDataPathConfigSF DSITX_SanityFunction10
+#define DSITX_SetPhyConfigSF DSITX_SanityFunction11
+#define DSITX_GetPhyConfigSF DSITX_SanityFunction12
+#define DSITX_SetDphyPwrAndRstCtrlSF DSITX_SanityFunction13
+#define DSITX_GetDphyPwrAndRstCtrlSF DSITX_SanityFunction14
+#define DSITX_SetDsiLinkConfigSF DSITX_SanityFunction15
+#define DSITX_GetDsiLinkConfigSF DSITX_SanityFunction16
+#define DSITX_GetIpConfSF DSITX_SanityFunction17
+#define DSITX_GetHwIdAndVersionSF DSITX_SanityFunction18
+#define DSITX_SetCommandModeSF DSITX_SanityFunction19
+#define DSITX_GetCommandModeSF DSITX_SanityFunction20
+#define DSITX_SetVideoModeSF DSITX_SanityFunction21
+#define DSITX_GetVideoModeSF DSITX_SanityFunction22
+#define DSITX_SetVcaConfigSF DSITX_SanityFunction23
+#define DSITX_GetVcaConfigSF DSITX_SanityFunction24
+#define DSITX_SetVideoSizeSF DSITX_SanityFunction25
+#define DSITX_GetVideoSizeSF DSITX_SanityFunction26
+#define DSITX_SetTvgConfigSF DSITX_SanityFunction27
+#define DSITX_GetTvgConfigSF DSITX_SanityFunction28
+#define DSITX_StartTvgSF DSITX_SanityFunction3
+#define DSITX_StopTvgSF DSITX_SanityFunction3
+#define DSITX_SendDirectCmdSF DSITX_SanityFunction31
+#define DSITX_SetDsiLinkEventHandlerSF DSITX_SanityFunction3
+#define DSITX_SetCmdModeEventHandlerSF DSITX_SanityFunction3
+#define DSITX_SetVidModeEventHandlerSF DSITX_SanityFunction3
+#define DSITX_SetTvgEventHandlerSF DSITX_SanityFunction3
+#define DSITX_SetDphyErrorEventHandlSF DSITX_SanityFunction3
+#define DSITX_SetDpiEventHandlerSF DSITX_SanityFunction3
+#define DSITX_SetTestGenericSF DSITX_SanityFunction38
+#define DSITX_GetTestGenericSF DSITX_SanityFunction39
+#define DSITX_SetVideo3dConfigSF DSITX_SanityFunction40
+#define DSITX_GetVideo3dConfigSF DSITX_SanityFunction41
+#define DSITX_GetAsfInfoSF DSITX_SanityFunction42
+#define DSITX_CheckLanesStateSF DSITX_SanityFunction3
+#define DSITX_WaitForPllLockSF DSITX_SanityFunction3
+
+
+#endif /* DSITX_SANITY_H */
+
+/* parasoft-end-suppress MISRA2012-RULE-8_7 */
+/* parasoft-end-suppress METRICS-41-3 */
+/* parasoft-end-suppress METRICS-39-3 */
+/* parasoft-end-suppress METRICS-36-3 */
+/* parasoft-end-suppress METRICS-18-3 */
diff --git a/packages/ti/drv/dss/src/csl/dsi/src/dsitx_utils.c b/packages/ti/drv/dss/src/csl/dsi/src/dsitx_utils.c
--- /dev/null
@@ -0,0 +1,106 @@
+/******************************************************************************
+ * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Core Driver helper functions implementation for MIPI DSITX Host Controller.
+ * This functions are mainly dedicated for Core Driver internal use.
+ *
+ *****************************************************************************/
+
+#include <src/csl/dsi/csl_dsi.h>
+#include "dsitx_utils.h"
+
+
+/**
+ * Reads 1 to 4 bytes from given address and returns them in
+ * 32-bit little endian format.
+ * This function helps the driver write data to the FIFO registers
+ * from the data buffer.
+ * @param buff Pointer to buffer from which bytes will be read.
+ * @param size Number of bytes to read from buffer.
+ */
+uint32_t ReadFromBuff32le(const uint8_t *buff, uint32_t size)
+{
+ uint32_t val = 0U;
+
+ /* check buffer address */
+ if (buff == NULL) {
+ val = 0U;
+ } else {
+
+ /* get value from each byte of buffer */
+ if (size > 0U) {
+ val = buff[0U];
+ }
+
+ if (size > 1U) {
+ val |= (((uint32_t)buff[1U]) << 8U);
+ }
+
+ if (size > 2U) {
+ val |= (((uint32_t)buff[2U]) << 16U);
+ }
+
+ if (size > 3U) {
+ val |= (((uint32_t)buff[3U]) << 24U);
+ }
+ }
+ return val;
+}
+
+/**
+ * Writes 1 to 4 bytes to given address from the given 32-bit value.
+ * This function helps the driver read data from the FIFO registers
+ * to the data buffer.
+ * @param buff Pointer to buffer to which bytes will be written in the
+ * little endian format.
+ * @param size Number of bytes to write to buffer from the val value.
+ * @param val Value to write.
+ */
+void WriteToBuff32le(uint8_t *buff, uint32_t size, uint32_t val)
+{
+ /* check buffer address */
+ if (buff != NULL) {
+
+ /* set value to each byte of buffer */
+ if (size > 0U) {
+ buff[0U] = (uint8_t)val;
+ }
+
+ if (size > 1U) {
+ buff[1U] = (uint8_t)(val >> 8U);
+ }
+
+ if (size > 2U) {
+ buff[2U] = (uint8_t)(val >> 16U);
+ }
+
+ if (size > 3U) {
+ buff[3U] = (uint8_t)(val >> 24U);
+ }
+ }
+ return;
+}
diff --git a/packages/ti/drv/dss/src/csl/dsi/src/dsitx_utils.h b/packages/ti/drv/dss/src/csl/dsi/src/dsitx_utils.h
--- /dev/null
@@ -0,0 +1,59 @@
+/******************************************************************************
+ * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Private declarations for MIPI DSITX Host Core Driver helper functions.
+ * These functions are mainly dedicated for Core Driver internal use.
+ *
+ *****************************************************************************/
+
+#ifndef DSITX_UTILS_H_
+# define DSITX_UTILS_H_
+
+
+
+/**
+ * Reads 1 to 4 bytes from given address and returns them in
+ * 32-bit little endian format.
+ * This function helps the driver write data to the FIFO registers
+ * from the data buffer.
+ * @param buff Pointer to buffer from which bytes will be read.
+ * @param size Number of bytes to read from buffer.
+ */
+uint32_t ReadFromBuff32le(const uint8_t *buff, uint32_t size);
+
+/**
+ * Writes 1 to 4 bytes to given address from the given 32-bit value.
+ * This function helps the driver read data from the FIFO registers
+ * to the data buffer.
+ * @param buff Pointer to buffer to which bytes will be written in the
+ * little endian format.
+ * @param size Number of bytes to write to buffer from the val value.
+ * @param val Value to write.
+ */
+void WriteToBuff32le(uint8_t *buff, uint32_t size, uint32_t val);
+
+#endif /* DSITX_UTILS_H_ */
diff --git a/packages/ti/drv/dss/src/csl/dsi/src/src_files_dsi.mk b/packages/ti/drv/dss/src/csl/dsi/src/src_files_dsi.mk
--- /dev/null
@@ -0,0 +1,3 @@
+SRCDIR += src/csl/dsi/src
+INCDIR += src/csl/dsi/include src/csl/dsi/src
+SRCS_COMMON +=
\ No newline at end of file
diff --git a/packages/ti/drv/dss/src/csl/src_files_csl.mk b/packages/ti/drv/dss/src/csl/src_files_csl.mk
--- /dev/null
@@ -0,0 +1,9 @@
+ifneq ($(SOC),$(filter $(SOC), am65xx))
+SRCDIR += src/csl src/csl/dp src/csl/dp_sd0801
+INCDIR += . src/csl/common
+
+PACKAGE_SRCS_COMMON += src/csl/dp src/csl/dp_sd0801 src/csl/common src/csl/csl_priv.c
+SRCS_COMMON += csl_priv.c
+include src/csl/dp/src/src_files_dp.mk
+include src/csl/dp_sd0801/src/src_files_sd0801.mk
+endif
diff --git a/packages/ti/drv/dss/src/drv/common/dss_evtMgr.c b/packages/ti/drv/dss/src/drv/common/dss_evtMgr.c
--- /dev/null
@@ -0,0 +1,827 @@
+/*
+ * Copyright (c) Texas Instruments Incorporated 2018
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * \file dss_evtMgr.c
+ *
+ * \brief File containing the DSS event manager implementation.
+ *
+ */
+
+/* ========================================================================== */
+/* Include Files */
+/* ========================================================================== */
+
+#include <ti/drv/dss/dss.h>
+#include <ti/drv/dss/src/drv/common/dss_evtMgr.h>
+#include <dss_soc_priv.h>
+
+/* ========================================================================== */
+/* Macros & Typedefs */
+/* ========================================================================== */
+
+/**
+ * \brief Flags used by event info structure memory pool manager to
+ * indicate availability of pool memory
+ */
+#define DSS_EVT_MGR_MEM_FLAG_FREE ((uint32_t) 0xFFFFFFFFU)
+#define DSS_EVT_MGR_MEM_FLAG_ALLOC ((uint32_t) 0x00000000U)
+
+/* ========================================================================== */
+/* Structure Declarations */
+/* ========================================================================== */
+
+/**
+ * \brief Structure containing common variables of event manager
+ */
+typedef struct
+{
+ uint32_t isInitDone;
+ /**< Flag to indicate that the object is initialized */
+ Dss_EvtMgrInfo evtMgrMemPool[DSS_EVT_MGR_MAX_CLIENTS];
+ /**< Pool of memory for the event manager info structure */
+ uint32_t evtMgrMemFlag[DSS_EVT_MGR_MAX_CLIENTS];
+ /**< Flags for each instance to indicate whether it is free or allocated */
+ Fvid2Utils_Node nodePool[DSS_EVT_MGR_MAX_CLIENTS];
+ /**< Pool of memory for the node */
+ SemaphoreP_Handle lockSem;
+ /**< Semaphore handle */
+} Dss_EvtMgrCommonObj;
+
+/* ========================================================================== */
+/* Function Declarations */
+/* ========================================================================== */
+
+static void Dss_evtMgrMasterIsr(uintptr_t arg);
+
+static int32_t Dss_evtMgrFillInfo(Dss_EvtMgrInfo *evtMgrInfo,
+ uint32_t eventGroup,
+ const uint32_t *event,
+ uint32_t numEvents,
+ Dss_evtMgrCbFxn callback,
+ void *arg);
+
+static void Dss_evtMgrDeleteInfo(const Dss_EvtMgrInfo *evtMgrInfo);
+
+static Dss_EvtMgrInfo *Dss_evtMgrCreateInfo(Fvid2Utils_Node **node);
+
+static void Dss_evtMgrAddNode(Fvid2Utils_Node *newNode);
+
+static void Dss_evtMgrDeleteNode(const Fvid2Utils_Node *emNode);
+
+static Dss_EvtMgrInstObj *Dss_evtMgrGetInstObj(uint32_t instId);
+
+/* ========================================================================== */
+/* Global Variables */
+/* ========================================================================== */
+
+static Dss_EvtMgrInstObj gDss_EvtMgrInstObj[DSS_EVT_MGR_INST_ID_MAX];
+static Dss_EvtMgrCommonObj gDss_EvtMgrCommonObj = {FALSE};
+
+/* ========================================================================== */
+/* Internal/Private Function Declarations */
+/* ========================================================================== */
+
+
+/* ========================================================================== */
+/* Function Definitions */
+/* ========================================================================== */
+
+int32_t Dss_evtMgrInit(const Dss_EvtMgrInitParams *initParams)
+{
+ int32_t retVal = FVID2_SOK;
+ uint32_t cnt;
+ Dss_EvtMgrInstObj *instObj;
+ SemaphoreP_Params semParams;
+ HwiP_Params hwiParams;
+
+ /* Check for errors */
+ GT_assert(DssTrace, (NULL != initParams));
+ GT_assert(DssTrace, (initParams->numIrq <= DSS_EVT_MGR_INST_ID_MAX));
+ GT_assert(DssTrace,
+ (initParams->dssCommonRegionId < CSL_DSS_COMM_REG_ID_MAX));
+
+ if(FALSE == gDss_EvtMgrCommonObj.isInitDone)
+ {
+ /* Initialize objects and mark flags as free */
+ for(cnt=0U; cnt<DSS_EVT_MGR_INST_ID_MAX; cnt++)
+ {
+ Fvid2Utils_memset(&gDss_EvtMgrInstObj[cnt],
+ 0U,
+ sizeof (gDss_EvtMgrInstObj[cnt]));
+ gDss_EvtMgrInstObj[cnt].instId = DSS_EVT_MGR_INST_ID_INVALID;
+ Fvid2Utils_initTsPrfLog(&gDss_EvtMgrInstObj[cnt].isrPrfLog);
+ }
+ Fvid2Utils_memset(&gDss_EvtMgrCommonObj,
+ 0U,
+ sizeof (gDss_EvtMgrCommonObj));
+
+ for(cnt=0U; cnt<DSS_EVT_MGR_MAX_CLIENTS; cnt++)
+ {
+ gDss_EvtMgrCommonObj.evtMgrMemFlag[cnt] =
+ DSS_EVT_MGR_MEM_FLAG_FREE;
+ }
+
+ /* Initialize the semaphore parameters and create semaphore pool */
+ SemaphoreP_Params_init(&semParams);
+ semParams.mode = SemaphoreP_Mode_BINARY;
+ gDss_EvtMgrCommonObj.lockSem = SemaphoreP_create(1U, &semParams);
+
+ if(NULL == gDss_EvtMgrCommonObj.lockSem)
+ {
+ retVal = FVID2_EALLOC;
+ }
+
+ if(FVID2_SOK == retVal)
+ {
+ /* Initialize instance object members */
+ for(cnt=0U; cnt<initParams->numIrq; cnt++)
+ {
+ instObj = &gDss_EvtMgrInstObj[cnt];
+ instObj->dssCommonRegionId = initParams->dssCommonRegionId;
+ instObj->irqNum = initParams->irqNum[cnt];
+ instObj->instId = initParams->instId[cnt];
+ instObj->isInitDone = TRUE;
+ instObj->headNode = NULL;
+ instObj->numIntr = 0U;
+
+ /* Clear out any pending interrupts */
+ HwiP_clearInterrupt(instObj->irqNum);
+
+ /* Populate the interrupt parameters */
+ HwiP_Params_init(&hwiParams);
+ hwiParams.arg = (uintptr_t) instObj;
+
+ /* Initialize head node and number of interrupts */
+ instObj->headNode = NULL;
+ instObj->numIntr = 0U;
+
+ /* Register interrupt */
+ instObj->intrHandle = HwiP_create(instObj->irqNum,
+ &Dss_evtMgrMasterIsr,
+ &hwiParams);
+
+ if(NULL == instObj->intrHandle)
+ {
+ retVal = FVID2_EALLOC;
+ GT_1trace(DssTrace,
+ GT_ERR,
+ "%s: Cannot Register IRQ", __FUNCTION__);
+ }
+ }
+ }
+
+ if(retVal != FVID2_SOK)
+ {
+ retVal+= Dss_evtMgrDeInit();
+ }
+ }
+ return (retVal);
+}
+
+int32_t Dss_evtMgrDeInit(void)
+{
+ uint32_t cnt;
+ Dss_EvtMgrInstObj *instObj;
+ Fvid2Utils_Node *tempNode;
+ Fvid2Utils_Node *emNode;
+
+ for(cnt=0U; cnt<DSS_EVT_MGR_INST_ID_MAX; cnt++)
+ {
+ instObj = &gDss_EvtMgrInstObj[cnt];
+ instObj->isInitDone = FALSE;
+
+ if(instObj->intrHandle != NULL)
+ {
+ /* Un-register interrupt */
+ HwiP_delete(instObj->intrHandle);
+ instObj->intrHandle = NULL;
+ }
+
+ /* Free Entire Linked List */
+ tempNode = instObj->headNode;
+ while (NULL != tempNode)
+ {
+ emNode = tempNode;
+ tempNode = tempNode->next;
+ Dss_evtMgrDeleteInfo((Dss_EvtMgrInfo *) emNode->data);
+ Dss_evtMgrDeleteNode(emNode);
+ }
+ }
+
+ if(gDss_EvtMgrCommonObj.lockSem != NULL)
+ {
+ SemaphoreP_delete(gDss_EvtMgrCommonObj.lockSem);
+ gDss_EvtMgrCommonObj.lockSem = NULL;
+ }
+
+ return (FVID2_SOK);
+}
+
+void *Dss_evtMgrRegister(uint32_t instId,
+ uint32_t eventGroup,
+ const uint32_t *event,
+ uint32_t numEvents,
+ Dss_evtMgrCbFxn callback,
+ void *arg)
+{
+ int32_t retVal = FVID2_SOK;
+ Dss_EvtMgrInstObj *instObj;
+ Fvid2Utils_Node *newNode = NULL;
+ Dss_EvtMgrInfo *evtMgrInfo = NULL;
+
+ /* Check for the error conditions */
+ GT_assert(DssTrace, (NULL != event));
+ GT_assert(DssTrace, (0U != numEvents));
+ GT_assert(DssTrace, (NULL != callback));
+
+ instObj = Dss_evtMgrGetInstObj(instId);
+ GT_assert(DssTrace, (NULL != instObj));
+
+ if(TRUE != instObj->isInitDone)
+ {
+ retVal = FVID2_EBADARGS;
+ }
+
+ if(FVID2_SOK == retVal)
+ {
+ (void) SemaphoreP_pend(gDss_EvtMgrCommonObj.lockSem,
+ SemaphoreP_WAIT_FOREVER);
+
+ /* Allocate memory for the event manager info structure */
+ evtMgrInfo = Dss_evtMgrCreateInfo(&newNode);
+
+ if((NULL != evtMgrInfo) && (NULL != newNode))
+ {
+ newNode->data = (void *) evtMgrInfo;
+
+ evtMgrInfo->instObj = instObj;
+ evtMgrInfo->numIntr = 0U;
+
+ /* Fill up the details about events in the client info structure */
+ retVal = Dss_evtMgrFillInfo(evtMgrInfo,
+ eventGroup,
+ event,
+ numEvents,
+ callback,
+ arg);
+
+ /* Add the node in the linked list as per the priority */
+ Dss_evtMgrAddNode(newNode);
+ }
+
+ (void) SemaphoreP_post(gDss_EvtMgrCommonObj.lockSem);
+ }
+
+ return ((void *) newNode);
+}
+
+int32_t Dss_evtMgrUnRegister(void *handle)
+{
+ uint32_t found = FALSE;
+ uint32_t cnt, event, regVal;
+ uint32_t eventGroup;
+ Dss_EvtMgrInstObj *instObj = NULL;
+ Fvid2Utils_Node *tempNode = NULL;
+ Fvid2Utils_Node *emNode = NULL;
+ Dss_EvtMgrInfo *evtMgrInfo = NULL;
+
+ /* Error condition Checking */
+ GT_assert(DssTrace, (NULL != handle));
+ tempNode = (Fvid2Utils_Node *) handle;
+ GT_assert(DssTrace, (NULL != tempNode->data));
+ instObj = ((Dss_EvtMgrInfo *) (tempNode->data))->instObj;
+ GT_assert(DssTrace, (NULL != instObj));
+
+ /* Check to see if the node given is in the linked list */
+ emNode = instObj->headNode;
+ GT_assert(DssTrace, (NULL != emNode));
+
+ while (NULL != emNode)
+ {
+ if(tempNode == emNode)
+ {
+ found = TRUE;
+ break;
+ }
+ emNode = emNode->next;
+ }
+ GT_assert(DssTrace, (FALSE != found));
+
+ evtMgrInfo = (Dss_EvtMgrInfo *) tempNode->data;
+ GT_assert(DssTrace, (NULL != evtMgrInfo));
+
+ (void) SemaphoreP_pend(gDss_EvtMgrCommonObj.lockSem,
+ SemaphoreP_WAIT_FOREVER);
+
+ /* Delete the Node */
+ Dss_evtMgrDeleteNode(tempNode);
+
+ /* Disable events in the DSS registers */
+ eventGroup = evtMgrInfo->eventGroup;
+
+ for(cnt=0U; cnt<evtMgrInfo->numEvents; cnt++)
+ {
+ event = evtMgrInfo->allEvents[cnt];
+
+ /* Disable the interrupts at the level 1 */
+ regVal = CSL_REG32_RD(evtMgrInfo->l1EnableReg[cnt]);
+ regVal &= (~event);
+ CSL_REG32_WR(evtMgrInfo->l1EnableReg[cnt], regVal);
+
+ /* Clear the status of the interrupt */
+ CSL_REG32_WR(evtMgrInfo->l1StatusReg[cnt],
+ evtMgrInfo->l1Mask[cnt]);
+
+ evtMgrInfo->l1EnableReg[cnt] = 0x0U;
+ evtMgrInfo->l1StatusReg[cnt] = 0x0U;
+ evtMgrInfo->l1Mask[cnt] = 0x0U;
+ }
+
+ /* Disable the interrupt */
+ regVal = eventGroup;
+ CSL_REG32_WR(evtMgrInfo->l0DisableReg, regVal);
+
+ /* Clear the status of interrupt */
+ regVal = eventGroup;
+ CSL_REG32_WR(evtMgrInfo->l0StatusReg, regVal);
+
+ evtMgrInfo->l0EnableReg = 0x0U;
+ evtMgrInfo->l0StatusReg = 0x0U;
+ evtMgrInfo->l0DisableReg = 0x0U;
+ evtMgrInfo->l0Mask = 0x0U;
+ evtMgrInfo->clientCb = NULL;
+ evtMgrInfo->arg = NULL;
+ evtMgrInfo->instObj = NULL;
+ evtMgrInfo->numEvents = 0U;
+
+ /* Free up memory allocated to event arrays and evtMgrInfo structure */
+ Dss_evtMgrDeleteInfo(evtMgrInfo);
+
+ (void) SemaphoreP_post(gDss_EvtMgrCommonObj.lockSem);
+
+ return (FVID2_SOK);
+}
+
+int32_t Dss_evtMgrEnable(void *handle)
+{
+ uint32_t found = FALSE;
+ uint32_t cnt, regVal;
+ uint32_t eventGroup, event;
+ Dss_EvtMgrInstObj *instObj = NULL;
+ Fvid2Utils_Node *tempNode = NULL;
+ Fvid2Utils_Node *emNode = NULL;
+ Dss_EvtMgrInfo *evtMgrInfo = NULL;
+
+ /* Error condition Checking */
+ GT_assert(DssTrace, (NULL != handle));
+ tempNode = (Fvid2Utils_Node *) handle;
+ GT_assert(DssTrace, (NULL != tempNode->data));
+ instObj = ((Dss_EvtMgrInfo *) (tempNode->data))->instObj;
+ GT_assert(DssTrace, (NULL != instObj));
+
+ /* Check to see if the node given is in the linked list */
+ emNode = instObj->headNode;
+ GT_assert(DssTrace, (NULL != emNode));
+
+ while (NULL != emNode)
+ {
+ if(tempNode == emNode)
+ {
+ found = TRUE;
+ break;
+ }
+ emNode = emNode->next;
+ }
+ GT_assert(DssTrace, (FALSE != found));
+
+ evtMgrInfo = (Dss_EvtMgrInfo *) tempNode->data;
+ GT_assert(DssTrace, (NULL != evtMgrInfo));
+
+ (void) SemaphoreP_pend(gDss_EvtMgrCommonObj.lockSem,
+ SemaphoreP_WAIT_FOREVER);
+
+ eventGroup = evtMgrInfo->eventGroup;
+
+ for(cnt=0U; cnt<evtMgrInfo->numEvents; cnt++)
+ {
+ event = evtMgrInfo->allEvents[cnt];
+
+ /* Clear the status of the interrupt */
+ CSL_REG32_WR(evtMgrInfo->l1StatusReg[cnt],
+ evtMgrInfo->l1Mask[cnt]);
+
+ /* Enable the interrupts at the level 1 */
+ regVal = CSL_REG32_RD(evtMgrInfo->l1EnableReg[cnt]);
+ regVal |= event;
+ CSL_REG32_WR(evtMgrInfo->l1EnableReg[cnt], regVal);
+ }
+
+ /* Clear the status of interrupt */
+ regVal = CSL_REG32_RD(evtMgrInfo->l0StatusReg);
+ regVal |= eventGroup;
+ CSL_REG32_WR(evtMgrInfo->l0StatusReg, regVal);
+
+ /* Enable the interrupt */
+ regVal = CSL_REG32_RD(evtMgrInfo->l0EnableReg);
+ regVal |= eventGroup;
+ CSL_REG32_WR(evtMgrInfo->l0EnableReg, regVal);
+
+ (void) SemaphoreP_post(gDss_EvtMgrCommonObj.lockSem);
+
+ return (FVID2_SOK);
+}
+
+int32_t Dss_evtMgrDisable(void *handle)
+{
+ uint32_t found = FALSE;
+ uint32_t cnt, regVal;
+ uint32_t eventGroup, event;
+ Dss_EvtMgrInstObj *instObj = NULL;
+ Fvid2Utils_Node *tempNode = NULL;
+ Fvid2Utils_Node *emNode = NULL;
+ Dss_EvtMgrInfo *evtMgrInfo = NULL;
+
+ /* Error condition Checking */
+ GT_assert(DssTrace, (NULL != handle));
+ tempNode = (Fvid2Utils_Node *) handle;
+ GT_assert(DssTrace, (NULL != tempNode->data));
+ instObj = ((Dss_EvtMgrInfo *) (tempNode->data))->instObj;
+ GT_assert(DssTrace, (NULL != instObj));
+
+ /* Check to see if the node given is in the linked list */
+ emNode = instObj->headNode;
+ GT_assert(DssTrace, (NULL != emNode));
+
+ while (NULL != emNode)
+ {
+ if(tempNode == emNode)
+ {
+ found = TRUE;
+ break;
+ }
+ emNode = emNode->next;
+ }
+ GT_assert(DssTrace, (FALSE != found));
+
+ evtMgrInfo = (Dss_EvtMgrInfo *) tempNode->data;
+ GT_assert(DssTrace, (NULL != evtMgrInfo));
+
+ (void) SemaphoreP_pend(gDss_EvtMgrCommonObj.lockSem,
+ SemaphoreP_WAIT_FOREVER);
+
+ eventGroup = evtMgrInfo->eventGroup;
+
+ for(cnt=0U; cnt<evtMgrInfo->numEvents; cnt++)
+ {
+ event = evtMgrInfo->allEvents[cnt];
+
+ /* Disable the interrupts at the level 1 */
+ regVal = CSL_REG32_RD(evtMgrInfo->l1EnableReg[cnt]);
+ regVal &= (~event);
+ CSL_REG32_WR(evtMgrInfo->l1EnableReg[cnt], regVal);
+
+ /* Clear the status of the interrupt */
+ CSL_REG32_WR(evtMgrInfo->l1StatusReg[cnt],
+ evtMgrInfo->l1Mask[cnt]);
+ }
+
+ /* Disable the interrupt */
+ regVal = CSL_REG32_RD(evtMgrInfo->l0DisableReg);
+ regVal |= eventGroup;
+ CSL_REG32_WR(evtMgrInfo->l0DisableReg, regVal);
+
+ /* Clear the status of interrupt */
+ regVal = CSL_REG32_RD(evtMgrInfo->l0StatusReg);
+ regVal |= eventGroup;
+ CSL_REG32_WR(evtMgrInfo->l0StatusReg, regVal);
+
+ (void) SemaphoreP_post(gDss_EvtMgrCommonObj.lockSem);
+
+ return (FVID2_SOK);
+}
+
+/* ========================================================================== */
+/* Static Function Definitions */
+/* ========================================================================== */
+
+static void Dss_evtMgrMasterIsr(uintptr_t arg)
+{
+ uint32_t cnt;
+ uint32_t regVal, numEvents;
+ Fvid2Utils_Node *tempNode;
+ Dss_EvtMgrInfo *evtMgrInfo = NULL;
+ Dss_EvtMgrInstObj *instObj;
+ instObj = (Dss_EvtMgrInstObj *) arg;
+
+ Fvid2Utils_startTsPrfLog(&instObj->isrPrfLog);
+
+ /* Traverse through the entire list of registered clients */
+ tempNode = instObj->headNode;
+ while (NULL != tempNode)
+ {
+ evtMgrInfo = (Dss_EvtMgrInfo *) tempNode->data;
+ GT_assert(DssTrace, (NULL != evtMgrInfo));
+
+ regVal = CSL_REG32_RD(evtMgrInfo->l0StatusReg);
+ if(evtMgrInfo->l0Mask == (evtMgrInfo->l0Mask & regVal))
+ {
+ CSL_REG32_WR(evtMgrInfo->l0StatusReg,
+ evtMgrInfo->l0Mask);
+ }
+
+ /* Move to the next client */
+ tempNode = tempNode->next;
+ }
+
+ /* Traverse through the entire list of registered clients */
+ tempNode = instObj->headNode;
+ while (NULL != tempNode)
+ {
+ evtMgrInfo = (Dss_EvtMgrInfo *) tempNode->data;
+ GT_assert(DssTrace, (NULL != evtMgrInfo));
+ numEvents = 0U;
+
+ for(cnt=0U; cnt<evtMgrInfo->numEvents; cnt++)
+ {
+ regVal = CSL_REG32_RD(evtMgrInfo->l1StatusReg[cnt]);
+
+ if(0U != (regVal & (evtMgrInfo->l1Mask[cnt])))
+ {
+ evtMgrInfo->setEvents[numEvents] =
+ evtMgrInfo->allEvents[cnt];
+ numEvents++;
+ /* Clear the status */
+ CSL_REG32_WR(evtMgrInfo->l1StatusReg[cnt],
+ evtMgrInfo->l1Mask[cnt]);
+ }
+ }
+
+ /* Call callback if any event occurs for the client */
+ if(0U != numEvents)
+ {
+ if(NULL != evtMgrInfo->clientCb)
+ {
+ evtMgrInfo->clientCb(evtMgrInfo->setEvents,
+ numEvents,
+ evtMgrInfo->arg);
+ }
+
+ /* Increment total number of interrupts */
+ evtMgrInfo->numIntr++;
+ }
+
+ /* Move to the next client */
+ tempNode = tempNode->next;
+ }
+
+ /* Increment total number of interrupts */
+ instObj->numIntr++;
+
+ Fvid2Utils_endTsPrfLog(&instObj->isrPrfLog);
+
+ return;
+}
+
+static int32_t Dss_evtMgrFillInfo(Dss_EvtMgrInfo *evtMgrInfo,
+ uint32_t eventGroup,
+ const uint32_t *event,
+ uint32_t numEvents,
+ Dss_evtMgrCbFxn callback,
+ void *arg)
+{
+ int32_t retVal = FVID2_SOK;
+ uint32_t cnt, regVal;
+ uint32_t dssCommonRegionId;
+ CSL_dss_commRegs *commRegs;
+ const Dss_SocInfo *socInfo;
+ Dss_EvtMgrClientInfo *evtMgrClientInfo =
+ (Dss_EvtMgrClientInfo *)(arg);
+
+ GT_assert(DssTrace, (NULL != evtMgrInfo));
+ GT_assert(DssTrace, (NULL != event));
+ GT_assert(DssTrace, (NULL != callback));
+
+ evtMgrInfo->eventGroup = eventGroup;
+ evtMgrInfo->numEvents = numEvents;
+ evtMgrInfo->arg = arg;
+ dssCommonRegionId = evtMgrInfo->instObj->dssCommonRegionId;
+ /* Get common register space */
+ socInfo = Dss_getSocInfo();
+ commRegs = socInfo->commRegs[dssCommonRegionId];
+ GT_assert(DssTrace, (NULL != commRegs));
+
+ for(cnt=0U; cnt<numEvents; cnt++)
+ {
+ retVal = Dss_enableL1Event(evtMgrInfo,
+ dssCommonRegionId,
+ eventGroup,
+ event[cnt],
+ cnt);
+
+ GT_assert(DssTrace, (FVID2_SOK == retVal));
+ }
+
+ /* Clear the status of interrupt */
+ regVal = CSL_REG32_RD(&commRegs->DISPC_IRQSTATUS);
+ regVal |= eventGroup;
+ CSL_REG32_WR(&commRegs->DISPC_IRQSTATUS, regVal);
+
+ /* Enable Interrupt at the top level */
+ regVal = CSL_REG32_RD(&commRegs->DISPC_IRQENABLE_SET);
+ regVal |= eventGroup;
+ CSL_REG32_WR(&commRegs->DISPC_IRQENABLE_SET, regVal);
+
+ /* Store the register address in evtMgrInfo instance */
+ evtMgrInfo->l0DisableReg = &commRegs->DISPC_IRQENABLE_CLR;
+ evtMgrInfo->l0EnableReg = &commRegs->DISPC_IRQENABLE_SET;
+ evtMgrInfo->l0StatusReg = &commRegs->DISPC_IRQSTATUS;
+ evtMgrInfo->l0Mask = eventGroup;
+
+ evtMgrClientInfo->eventGroup = eventGroup;
+ evtMgrInfo->clientCb = callback;
+
+ return (retVal);
+}
+
+static Dss_EvtMgrInfo *Dss_evtMgrCreateInfo(Fvid2Utils_Node **node)
+{
+ uint32_t cnt;
+ Dss_EvtMgrInfo *evtMgrInfo = NULL;
+
+ for(cnt=0U; cnt<DSS_EVT_MGR_MAX_CLIENTS; cnt++)
+ {
+ if(DSS_EVT_MGR_MEM_FLAG_FREE ==
+ gDss_EvtMgrCommonObj.evtMgrMemFlag[cnt])
+ {
+ evtMgrInfo = &(gDss_EvtMgrCommonObj.evtMgrMemPool[cnt]);
+ *node = &gDss_EvtMgrCommonObj.nodePool[cnt];
+ gDss_EvtMgrCommonObj.evtMgrMemFlag[cnt] =
+ DSS_EVT_MGR_MEM_FLAG_ALLOC;
+ break;
+ }
+ }
+
+ return (evtMgrInfo);
+}
+
+static void Dss_evtMgrDeleteInfo(const Dss_EvtMgrInfo *evtMgrInfo)
+{
+ uint32_t cnt;
+
+ GT_assert(DssTrace, (NULL != evtMgrInfo));
+
+ for(cnt=0U; cnt<DSS_EVT_MGR_MAX_CLIENTS; cnt++)
+ {
+ if(evtMgrInfo == &(gDss_EvtMgrCommonObj.evtMgrMemPool[cnt]))
+ {
+ gDss_EvtMgrCommonObj.evtMgrMemFlag[cnt] = DSS_EVT_MGR_MEM_FLAG_FREE;
+ break;
+ }
+ }
+
+ return;
+}
+
+static void Dss_evtMgrAddNode(Fvid2Utils_Node *newNode)
+{
+ uint32_t cookie;
+ Dss_EvtMgrInstObj *instObj = NULL;
+ Fvid2Utils_Node *curr = NULL;
+ Fvid2Utils_Node *prev = NULL;
+
+ GT_assert(DssTrace, (NULL != newNode));
+
+ /* Disable interrupts before updating node list */
+ cookie = HwiP_disable();
+
+ instObj = ((Dss_EvtMgrInfo *) (newNode->data))->instObj;
+ GT_assert(DssTrace, (NULL != instObj));
+
+ newNode->prev = NULL;
+ newNode->next = NULL;
+
+ curr = instObj->headNode;
+ prev = NULL;
+
+ /* Search for place to insert new node */
+ while (NULL != curr)
+ {
+ prev = curr;
+ curr = curr->next;
+ }
+
+ /* Update pointers */
+ newNode->next = curr;
+ newNode->prev = prev;
+
+ if(NULL == prev)
+ {
+ instObj->headNode = newNode;
+ }
+ else
+ {
+ prev->next = newNode;
+ }
+
+ /* Restore interrupts after updating node list */
+ HwiP_restore(cookie);
+
+ return;
+}
+
+static void Dss_evtMgrDeleteNode(const Fvid2Utils_Node *emNode)
+{
+ uint32_t cookie;
+ Dss_EvtMgrInstObj *instObj = NULL;
+ Fvid2Utils_Node *curr = NULL;
+ Fvid2Utils_Node *prev = NULL;
+
+ GT_assert(DssTrace, (NULL != emNode));
+
+ /* Disable interrupts before updating node list */
+ cookie = HwiP_disable();
+
+ instObj = ((Dss_EvtMgrInfo *) (emNode->data))->instObj;
+ prev = emNode->prev;
+ curr = emNode->next;
+
+ if(NULL != prev)
+ {
+ if(NULL != curr)
+ {
+ prev->next = curr;
+ }
+ else
+ {
+ prev->next = NULL;
+ }
+ }
+ else
+ {
+ instObj->headNode = curr;
+ if(NULL != instObj->headNode)
+ {
+ instObj->headNode->prev = NULL;
+ }
+ }
+ if(NULL != curr)
+ {
+ curr->prev = prev;
+ }
+
+ /* Restore interrupts after updating node list */
+ HwiP_restore(cookie);
+
+ return;
+}
+
+static Dss_EvtMgrInstObj *Dss_evtMgrGetInstObj(uint32_t instId)
+{
+ uint32_t cnt;
+ Dss_EvtMgrInstObj *instObj = NULL;
+
+ if(instId < DSS_EVT_MGR_INST_ID_MAX)
+ {
+ for(cnt=0U; cnt<DSS_EVT_MGR_INST_ID_MAX; cnt++)
+ {
+ if(gDss_EvtMgrInstObj[instId].instId == instId)
+ {
+ instObj = &gDss_EvtMgrInstObj[instId];
+ break;
+ }
+ }
+ }
+
+ return (instObj);
+}
diff --git a/packages/ti/drv/dss/src/drv/common/dss_evtMgr.h b/packages/ti/drv/dss/src/drv/common/dss_evtMgr.h
--- /dev/null
@@ -0,0 +1,214 @@
+/*
+ * Copyright (c) Texas Instruments Incorporated 2018
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * \file dss_evtMgr.h
+ *
+ * \brief DSS driver event manager interface file.
+ */
+
+#ifndef DSS_EVTMGR_H_
+#define DSS_EVTMGR_H_
+
+/* ========================================================================== */
+/* Include Files */
+/* ========================================================================== */
+
+#include <ti/drv/dss/dss.h>
+#include <dss_soc_priv.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* ========================================================================== */
+/* Macros & Typedefs */
+/* ========================================================================== */
+
+/**
+ * \brief This typedef defines the Event manager callback function prototype.
+ * Client registers this callback with the event manager and when event
+ * occurs, event manager calls this callback.
+ *
+ * \param event This is an array of events occurred when interrupt came.
+ * Event manager passes this list to the client.
+ * \param numEvents This tells number of events occurred.
+ * \param arg Client's Private Data
+ */
+typedef void (*Dss_evtMgrCbFxn)(const uint32_t *event,
+ uint32_t numEvents,
+ void *arg);
+
+/* ========================================================================== */
+/* Structure Declarations */
+/* ========================================================================== */
+
+struct Dss_EvtMgrInitParams_t
+{
+ uint32_t dssCommonRegionId;
+ /**< DSS Common Region Id. Refer \ref CSL_DssCommRegId for values */
+ uint32_t numIrq;
+ /**< Number of valid entries in below two arrays */
+ uint32_t instId[DSS_EVT_MGR_INST_ID_MAX];
+ /**< Instance Ids */
+ uint32_t irqNum[DSS_EVT_MGR_INST_ID_MAX];
+ /**< Interrupt numbers */
+};
+
+typedef struct
+{
+ uint32_t eventGroup;
+ /**< This tells the event group into which registered event belongs. Refer
+ \ref Dss_EventGroup for values*/
+} Dss_EvtMgrClientInfo;
+
+/**
+ * \brief structure containing instance specific information, there should be
+ * one instance object for each independent IRQ
+ */
+typedef struct
+{
+ uint32_t isInitDone;
+ /**< Flag to indicate that the instance is initialized */
+ uint32_t dssCommonRegionId;
+ /**< DSS Common Region Id. Refer \ref CSL_DssCommRegId for values */
+ uint32_t instId;
+ /**< Event manager Instance Id. Refer \ref Dss_EvtMgrInstId for values */
+ uint32_t irqNum;
+ /**< IRQ number at CPU level INTC */
+ Fvid2Utils_Node *headNode;
+ /**< Pointer to the head node of the priority linked list. */
+ HwiP_Handle intrHandle;
+ /**< Handle to Hardware Interrupt */
+ uint32_t numIntr;
+ /**< Total number of interrupts occurred since last initialization */
+ Fvid2Utils_TsPrfLog isrPrfLog;
+ /**< ISR duration performance log. */
+} Dss_EvtMgrInstObj;
+
+struct Dss_EvtMgrInfo_t
+{
+ volatile void *l0EnableReg;
+ /**< Address of the level 0 enable register */
+ volatile void *l0StatusReg;
+ /**< Address of the level 0 status register */
+ volatile void *l0DisableReg;
+ /**< Address of the level 0 disable register */
+ uint32_t l0Mask;
+ /**< Bit mask for checking and clearing the level 0 status */
+ volatile void *l1EnableReg[DSS_EVT_MGR_MAX_CLIENT_EVENTS];
+ /**< Address of the level 1 enable register */
+ volatile void *l1StatusReg[DSS_EVT_MGR_MAX_CLIENT_EVENTS];
+ /**< Address of the level 1 status register */
+ uint32_t l1Mask[DSS_EVT_MGR_MAX_CLIENT_EVENTS];
+ /**< Bit mask for checking and clearing the status of the event/IRQ */
+ Dss_evtMgrCbFxn clientCb;
+ /**< Client's callback function. This function will be called by the
+ * event manager whenever client registered event occurs */
+ void *arg;
+ /**< Client's private data to be passed to it when callback function is
+ * called */
+ uint32_t eventGroup;
+ /**< This tells the event group into which registered event belongs. Refer
+ * \ref Dss_EventGroup for values */
+ uint32_t numIntr;
+ /**< Number of interrupts occurred for this client */
+ Dss_EvtMgrInstObj *instObj;
+ /**< Pointer to the Instance Object */
+ uint32_t allEvents[DSS_EVT_MGR_MAX_CLIENT_EVENTS];
+ /**< List of events for which client has registered callback */
+ uint32_t setEvents[DSS_EVT_MGR_MAX_CLIENT_EVENTS];
+ /**< This array contains the list of events occurred at the time of
+ * interrupt. It will be passed down to the clients.*/
+ uint32_t numEvents;
+ /**< Count of events for client has registered callback. */
+};
+
+/* ========================================================================== */
+/* Internal/Private Function Declarations */
+/* ========================================================================== */
+
+/**
+ * \brief Dss_EvtMgrInitParams structure init function.
+ *
+ * \param evtMgrParams Pointer to #Dss_EvtMgrInitParams structure.
+ *
+ * \return None
+ */
+static inline void Dss_evtMgrInitParamsInit(Dss_EvtMgrInitParams *evtMgrParams);
+
+/* ========================================================================== */
+/* Function Declarations */
+/* ========================================================================== */
+
+int32_t Dss_evtMgrInit(const Dss_EvtMgrInitParams *initPrms);
+
+int32_t Dss_evtMgrDeInit(void);
+
+void *Dss_evtMgrRegister(uint32_t instId,
+ uint32_t eventGroup,
+ const uint32_t *event,
+ uint32_t numEvents,
+ Dss_evtMgrCbFxn callback,
+ void *arg);
+
+int32_t Dss_evtMgrUnRegister(void *handle);
+
+int32_t Dss_evtMgrDisable(void *handle);
+
+int32_t Dss_evtMgrEnable(void *handle);
+
+/* ========================================================================== */
+/* Static Function Definitions */
+/* ========================================================================== */
+
+static inline void Dss_evtMgrInitParamsInit(Dss_EvtMgrInitParams *evtMgrParams)
+{
+ uint32_t i;
+ if(NULL != evtMgrParams)
+ {
+ evtMgrParams->dssCommonRegionId = CSL_DSS_COMM_REG_ID_0;
+ evtMgrParams->numIrq = 0U;
+ for(i=0U; i<DSS_EVT_MGR_INST_ID_MAX; i++)
+ {
+ evtMgrParams->instId[i] = 0x0U;
+ evtMgrParams->irqNum[i] = 0x0U;
+ }
+ }
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #ifndef DSS_EVTMGR_H_ */
diff --git a/packages/ti/drv/dss/src/drv/common/dss_init.c b/packages/ti/drv/dss/src/drv/common/dss_init.c
--- /dev/null
@@ -0,0 +1,172 @@
+/*
+ * Copyright (c) Texas Instruments Incorporated 2018
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * \file dss_init.c
+ *
+ * \brief File containing the DSS initialization APIs.
+ *
+ */
+
+/* ========================================================================== */
+/* Include Files */
+/* ========================================================================== */
+
+#include <ti/drv/dss/dss.h>
+#include <dss_soc_priv.h>
+#include <ti/drv/dss/src/drv/common/dss_evtMgr.h>
+#include <ti/drv/dss/src/drv/dctrl/dss_dctrlDrv.h>
+#include <ti/drv/dss/src/drv/disp/dss_dispDrv.h>
+
+/* ========================================================================== */
+/* Macros & Typedefs */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/* Structure Declarations */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/* Function Declarations */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/* Global Variables */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/* Function Definitions */
+/* ========================================================================== */
+
+void Dss_initParamsInit(Dss_InitParams *dssParams)
+{
+ if(NULL != dssParams)
+ {
+ Dss_socParamsInit(&(dssParams->socParams));
+ }
+}
+
+int32_t Dss_init(const Dss_InitParams *initParams)
+{
+ int32_t retVal = FVID2_SOK;
+ uint32_t i, numInst = 0U;
+ uint32_t isPipeAvailable[CSL_DSS_VID_PIPE_ID_MAX];
+ uint32_t isPortAvailable[CSL_DSS_VP_ID_MAX];
+ Dss_DctrlDrvInitParams dctrlInitParams;
+ Dss_EvtMgrInitParams evtMgrInitParams;
+ Dss_DispDrvInitParams dispInitParams[CSL_DSS_VID_PIPE_ID_MAX];
+ Dss_RmInfo *rmInfo;
+ Dss_IrqParams *irqParams;
+
+ /* Check for NULL pointers and invalid arguments */
+ if(NULL == initParams)
+ {
+ GT_0trace(DssTrace, GT_ERR, "Invalid arguments\r\n");
+ retVal = FVID2_EBADARGS;
+ }
+
+ if(FVID2_SOK == retVal)
+ {
+ rmInfo = (Dss_RmInfo *)(&(initParams->socParams.rmInfo));
+ Dss_fillSocInfo(rmInfo);
+
+ /* Initialize event manager */
+ irqParams = (Dss_IrqParams *)(&(initParams->socParams.irqParams));
+ Dss_evtMgrInitParamsInit(&evtMgrInitParams);
+ retVal = Dss_fillEvtMgrInitInfo(&evtMgrInitParams, irqParams);
+ retVal += Dss_evtMgrInit(
+ (const Dss_EvtMgrInitParams *) &evtMgrInitParams);
+ }
+
+ if(FVID2_SOK == retVal)
+ {
+ /* Initialize display controller driver */
+ dctrlInitParams.drvInstId = DSS_DCTRL_INST_0;
+ dctrlInitParams.numAvailablePorts = 0U;
+ for(i=CSL_DSS_VP_ID_1; i<CSL_DSS_VP_ID_MAX; i++)
+ {
+ isPortAvailable[i] =
+ initParams->socParams.rmInfo.isPortAvailable[i];
+
+ if(TRUE == isPortAvailable[i])
+ {
+ dctrlInitParams.availablePortId[
+ dctrlInitParams.numAvailablePorts] = i;
+ dctrlInitParams.numAvailablePorts++;
+ }
+ }
+
+#if defined(SOC_J721E)
+ dctrlInitParams.dpInitParams.isAvailable = initParams->socParams.dpInitParams.isAvailable;
+ dctrlInitParams.dpInitParams.isHpdSupported = initParams->socParams.dpInitParams.isHpdSupported;
+#endif
+ retVal = Dss_dctrlDrvInit(&dctrlInitParams);
+ }
+
+ if(FVID2_SOK == retVal)
+ {
+ /* Initialize display driver */
+ for(i=0U; i<CSL_DSS_VID_PIPE_ID_MAX; i++)
+ {
+ isPipeAvailable[i] =
+ initParams->socParams.rmInfo.isPipeAvailable[i];
+
+ if(TRUE == isPipeAvailable[i])
+ {
+ dispInitParams[numInst].drvInstId = i;
+ numInst++;
+ }
+ }
+ retVal += Dss_dispDrvInit(numInst, dispInitParams);
+ }
+
+ return retVal;
+}
+
+int32_t Dss_deInit(void)
+{
+ int32_t retVal = FVID2_SOK;
+
+ retVal = Dss_dispDrvDeInit();
+ retVal += Dss_dctrlDrvDeInit();
+ retVal += Dss_evtMgrDeInit();
+ return retVal;
+}
diff --git a/packages/ti/drv/dss/src/drv/common/src_files_common.mk b/packages/ti/drv/dss/src/drv/common/src_files_common.mk
--- /dev/null
@@ -0,0 +1 @@
+SRCS_COMMON += dss_init.c dss_evtMgr.c
\ No newline at end of file
diff --git a/packages/ti/drv/dss/src/drv/dctrl/dss_dctrlApi.c b/packages/ti/drv/dss/src/drv/dctrl/dss_dctrlApi.c
--- /dev/null
@@ -0,0 +1,2264 @@
+/*
+ * Copyright (c) Texas Instruments Incorporated 2018
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * \file dss_dctrlApi.c
+ *
+ * \brief File containing the DSS Controller driver implementation.
+ *
+ */
+
+/* ========================================================================== */
+/* Include Files */
+/* ========================================================================== */
+
+#include <ti/drv/dss/dss.h>
+#include <ti/drv/dss/src/drv/common/dss_evtMgr.h>
+#include <ti/drv/dss/src/drv/dctrl/dss_dctrlDrv.h>
+#include <ti/drv/dss/src/drv/dctrl/dss_dctrlIntr.h>
+#include <ti/drv/dss/src/drv/dctrl/dss_dctrlPriv.h>
+#include <dss_soc_priv.h>
+
+/* ========================================================================== */
+/* Macros & Typedefs */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/* Structure Declarations */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/* Function Declarations */
+/* ========================================================================== */
+
+/**
+ * Below ifdef __cplusplus is added so that C++ build passes without
+ * typecasting. This is because the prototype is build as C type
+ * whereas this file is build as CPP file. Hence we get C++ build error.
+ * Also if typecasting is used, then we get MisraC error Rule 11.1.
+ */
+#ifdef __cplusplus
+extern "C" {
+#endif
+/*
+ * Display Controller APIs
+ */
+static Fdrv_Handle Dss_dctrlDrvCreate(uint32_t drvId,
+ uint32_t instId,
+ void *createArgs,
+ void *createStatusArgs,
+ const Fvid2_DrvCbParams *fdmCbParams);
+static int32_t Dss_dctrlDrvDelete(Fdrv_Handle handle, void *reserved);
+static int32_t Dss_dctrlDrvControl(Fdrv_Handle handle,
+ uint32_t cmd,
+ void *cmdArgs,
+ void *cmdStatusArgs);
+#ifdef __cplusplus
+}
+#endif
+
+/* ========================================================================== */
+/* Global Variables */
+/* ========================================================================== */
+
+Dss_DctrlDrvCommonObj gDss_DctrlDrvCommonObj;
+Dss_DctrlDrvInstObj gDss_DctrlDrvInstObj;
+
+Dss_DctrlDrvGraphObj gDss_DctrlDrvGraphObj;
+Dss_DctrlDrvInfo gDss_DctrlDrvInfo;
+Dss_EvtMgrClientInfo gDss_DctrlEvtMgrClientInfo[DSS_DCTRL_EVT_MGR_MAX_CLIENTS];
+
+/* ========================================================================== */
+/* Internal/Private Function Declarations */
+/* ========================================================================== */
+
+static int32_t Dss_dctrlDrvSetPathIoctl(Dss_DctrlDrvInstObj *instObj,
+ const Dss_DctrlPathInfo *pathInfo);
+static int32_t Dss_dctrlDrvClearPathIoctl(Dss_DctrlDrvInstObj *instObj,
+ const Dss_DctrlPathInfo *pathInfo);
+static int32_t Dss_dctrlDrvSetVpParamsIoctl(
+ Dss_DctrlDrvInstObj *instObj,
+ const Dss_DctrlVpParams *vpParams);
+static int32_t Dss_dctrlDrvSetOverlayParamsIoctl(
+ Dss_DctrlDrvInstObj *instObj,
+ const Dss_DctrlOverlayParams *overlayParams);
+static int32_t Dss_dctrlDrvSetLayerParamsIoctl(
+ Dss_DctrlDrvInstObj *instObj,
+ const Dss_DctrlOverlayLayerParams *layerParams);
+static int32_t Dss_dctrlDrvSetVpCscCoeffIoctl(
+ Dss_DctrlDrvInstObj *instObj,
+ const Dss_DctrlVpCscCoeff *vpCscCoeff);
+static int32_t Dss_dctrlDrvSetAdvVpParamsIoctl(
+ Dss_DctrlDrvInstObj *instObj,
+ const Dss_DctrlAdvVpParams *advVpParams);
+static int32_t Dss_dctrlDrvSetLcdBlankTimingIoctl(
+ Dss_DctrlDrvInstObj *instObj,
+ const Dss_DctrlLcdBlankTimingParams *timingParams);
+static int32_t Dss_dctrlDrvSetVpSafetyChkParamsIoctl(
+ Dss_DctrlDrvInstObj *instObj,
+ const Dss_DctrlVpSafetyChkParams *safetyChkParams);
+static int32_t Dss_dctrlDrvGetErrorStatsIoctl(
+ Dss_DctrlDrvInstObj *instObj,
+ Dss_DctrlVpErrorStats *vpErrStats);
+static int32_t Dss_dctrlDrvSetGlobalDssParamsIoctl(
+ Dss_DctrlDrvInstObj *instObj,
+ const Dss_DctrlGlobalDssParams *globalDssParams);
+static int32_t Dss_dctrlDrvStopVpIoctl(Dss_DctrlDrvInstObj *instObj,
+ const Dss_DctrlVpParams *vpParams);
+static int32_t Dss_dctrlDrvSetSyncLostCbParamsIoctl(
+ Dss_DctrlDrvInstObj *instObj,
+ const Dss_DctrlSyncLostCbParams *syncLostCbParams);
+static int32_t Dss_dctrlDrvSetLineNumCbParamsIoctl(
+ Dss_DctrlDrvInstObj *instObj,
+ const Dss_DctrlLineNumCbParams *lineNumCbParams);
+static void Dss_dctrlFuncCbFxn(const uint32_t *event,
+ uint32_t numEvents,
+ void *arg);
+static void Dss_dctrlErrCbFxn(const uint32_t *event,
+ uint32_t numEvents,
+ void *arg);
+static void Dss_dctrlSafetyErrCbFxn(const uint32_t *event,
+ uint32_t numEvents,
+ void *arg);
+static int32_t Dss_dctrlConnectNodes(uint32_t inputNode, uint32_t outNode);
+
+#if defined (SOC_AM65XX)
+static int32_t Dss_dctrlDrvSetOldiParamsIoctl(
+ Dss_DctrlDrvInstObj *instObj,
+ const Dss_DctrlOldiParams *oldiParams);
+#endif
+#if defined (SOC_J721E)
+static uint32_t Dss_dctrlDrvIsOutputDP(uint32_t vpId);
+static int32_t Dss_dctrlDrvSetDpHpdCbParamsIoctl(
+ Dss_DctrlDrvInstObj *instObj,
+ const Dss_DctrlDpHpdCbParams *dpHpdCbParams);
+static int32_t Dss_dctrlDrvProcessDpHpdIoctl(
+ Dss_DctrlDrvInstObj *instObj,
+ const uint32_t *dpProcessHpdParams);
+#endif
+
+static void Dss_dctrlVpSetGoBit(uint32_t vpId);
+static void Dss_dctrlVpReset(uint32_t vpId);
+static void Dss_dctrlVpEnable(uint32_t vpId, uint32_t enable);
+
+/* ========================================================================== */
+/* Function Definitions */
+/* ========================================================================== */
+
+int32_t Dss_dctrlDrvInit(const Dss_DctrlDrvInitParams *drvInitParams)
+{
+ int32_t retVal = FVID2_SOK;
+ uint32_t i, cnt, eventGroup, vpId, numHandle, numEvents, evtMgrId;
+ uint32_t enabledEvents[DSS_EVT_MGR_MAX_CLIENT_EVENTS];
+ Dss_DctrlDrvInfo *pDrvInfo;
+ Dss_DctrlDrvCommonObj *pObj;
+ Dss_DctrlDrvGraphObj *pGraphObj;
+ Dss_DctrlDrvInstObj *pDrvInstObj;
+ Dss_EvtMgrClientInfo *pClientInfo;
+ SemaphoreP_Params semParams;
+
+ pDrvInfo = &gDss_DctrlDrvInfo;
+ pObj = &gDss_DctrlDrvCommonObj;
+ pGraphObj = &gDss_DctrlDrvGraphObj;
+ pDrvInstObj = &gDss_DctrlDrvInstObj;
+
+ Fvid2Utils_memset(pObj, 0U, sizeof (Dss_DctrlDrvCommonObj));
+ Fvid2Utils_memset(pGraphObj, 0U, sizeof (Dss_DctrlDrvGraphObj));
+ Fvid2Utils_memset(pDrvInfo, 0U, sizeof (Dss_DctrlDrvInfo));
+ Fvid2Utils_memset(pDrvInstObj, 0U, sizeof (Dss_DctrlDrvInstObj));
+
+ for(i=0U; i<DSS_DCTRL_EVT_MGR_MAX_CLIENTS; i++)
+ {
+ pClientInfo = &gDss_DctrlEvtMgrClientInfo[i];
+ Fvid2Utils_memset(pClientInfo, 0U, sizeof (Dss_EvtMgrClientInfo));
+ }
+ /* Initialize instance object members */
+ pObj->instObj = &gDss_DctrlDrvInstObj;
+ pObj->instObj->drvInstId = drvInitParams->drvInstId;
+
+ /* Initialize graph object */
+ (void) Dss_dctrlDrvGraphInit(pGraphObj);
+
+ if(FVID2_SOK == retVal)
+ {
+ /* Allocate instance semaphore */
+ SemaphoreP_Params_init(&semParams);
+ semParams.mode = SemaphoreP_Mode_BINARY;
+ pObj->instObj->lockSem = SemaphoreP_create(1U, &semParams);
+ if(NULL == pObj->instObj->lockSem)
+ {
+ GT_0trace(DssTrace,
+ GT_ERR,
+ "Instance semaphore create failed!!\r\n");
+ retVal = FVID2_EALLOC;
+ }
+
+ for(i=0U; i<CSL_DSS_VID_PIPE_ID_MAX; i++)
+ {
+ /* Allocate instance semaphore */
+ pDrvInfo->pipeInfo[i].stopSem = SemaphoreP_create(0U, &semParams);
+ if(NULL == pDrvInfo->pipeInfo[i].stopSem)
+ {
+ GT_0trace(DssTrace,
+ GT_ERR,
+ "Sync Stop semaphore create failed!!\r\n");
+ retVal = FVID2_EALLOC;
+ }
+ }
+
+ for(i=0U; i<CSL_DSS_VP_ID_MAX; i++)
+ {
+ pDrvInfo->vpState[i] = DSS_DCTRL_VP_IDLE;
+ }
+
+ pObj->instObj->drvState.isInit = TRUE;
+ pObj->instObj->drvState.isOpened = FALSE;
+ pObj->instObj->drvState.isStarted = FALSE;
+ }
+
+ if(FVID2_SOK == retVal)
+ {
+ /* Register for Video Port events */
+ for(cnt=0U; cnt<drvInitParams->numAvailablePorts; cnt++)
+ {
+ vpId = drvInitParams->availablePortId[cnt];
+ Dss_convModuletoEventGroup(&eventGroup,
+ vpId,
+ DSS_EVENT_GROUP_TYPE_VP);
+ GT_assert(DssTrace, (DSS_EVENT_GROUP_INVALID != eventGroup));
+
+ /* Register functional events */
+ Dss_getEnabledVpFuncEvents(&enabledEvents[0U], &numEvents);
+ numHandle = pObj->instObj->numRegEvtHandle;
+ evtMgrId = Dss_getEvtMgrFuncIntrId();
+ pObj->instObj->evtGroupHandle[pObj->instObj->numRegEvtHandle] =
+ Dss_evtMgrRegister(
+ evtMgrId,
+ eventGroup,
+ (const uint32_t *)&enabledEvents[0U],
+ numEvents,
+ Dss_dctrlFuncCbFxn,
+ (void *)&gDss_DctrlEvtMgrClientInfo[numHandle]);
+ pObj->instObj->numRegEvtHandle++;
+
+ /* Register error events */
+ Dss_getEnabledVpErrEvents(&enabledEvents[0U], &numEvents);
+ numHandle = pObj->instObj->numRegEvtHandle;
+ pObj->instObj->evtGroupHandle[pObj->instObj->numRegEvtHandle] =
+ Dss_evtMgrRegister(
+ evtMgrId,
+ eventGroup,
+ (const uint32_t *)&enabledEvents[0U],
+ numEvents,
+ Dss_dctrlErrCbFxn,
+ (void *)&gDss_DctrlEvtMgrClientInfo[numHandle]);
+ pObj->instObj->numRegEvtHandle++;
+ }
+ }
+
+#if defined (SOC_J721E)
+ if((FVID2_SOK == retVal) &&
+ (TRUE == drvInitParams->dpInitParams.isAvailable))
+ {
+ retVal = Dss_dctrlDrvInitDp(drvInitParams->dpInitParams.isHpdSupported);
+ }
+#endif
+
+ if(FVID2_SOK == retVal)
+ {
+ /* Initialize Driver operations */
+ Fvid2DrvOps_init(&pObj->fvidDrvOps);
+
+ pObj->fvidDrvOps.drvId = DSS_DCTRL_DRV_ID;
+ pObj->fvidDrvOps.createFxn = &Dss_dctrlDrvCreate;
+ pObj->fvidDrvOps.deleteFxn = &Dss_dctrlDrvDelete;
+ pObj->fvidDrvOps.controlFxn = &Dss_dctrlDrvControl;
+
+ retVal = Fvid2_registerDriver(&pObj->fvidDrvOps);
+ if(FVID2_SOK != retVal)
+ {
+ GT_0trace(DssTrace,
+ GT_ERR,
+ "Registering to FVID2 driver manager failed\r\n");
+ }
+ else
+ {
+ /* Init successful */
+ pObj->isRegistered = TRUE;
+ }
+ }
+
+ return (retVal);
+}
+
+int32_t Dss_dctrlDrvDeInit(void)
+{
+ int32_t retVal = FVID2_SOK;
+ uint32_t cnt, numRegEvtHandle, i, vpFound = FALSE;;
+ Dss_DctrlDrvCommonObj *pObj;
+ Dss_DctrlDrvInstObj *instObj;
+ Dss_DctrlDrvGraphObj *pGraphObj;
+ Dss_DctrlDrvInfo *pDrvInfo;
+ pObj = &gDss_DctrlDrvCommonObj;
+ pGraphObj = &gDss_DctrlDrvGraphObj;
+ pDrvInfo = &gDss_DctrlDrvInfo;
+ if(NULL != pObj->instObj)
+ {
+ instObj = pObj->instObj;
+ if(instObj->drvState.isOpened == TRUE)
+ {
+ GT_0trace(DssTrace,
+ GT_ERR,
+ "Can't de-initialize when an instance is active\r\n");
+ retVal = FVID2_EFAIL;
+ }
+
+ for(i=0U; i<CSL_DSS_VP_ID_MAX; i++)
+ {
+ if(DSS_DCTRL_VP_IDLE != pDrvInfo->vpState[i])
+ {
+ vpFound = TRUE;
+ break;
+ }
+ }
+ if(TRUE == vpFound)
+ {
+ GT_0trace(DssTrace,
+ GT_ERR,
+ "Can't de-initialize when a VP is running\r\n");
+ retVal = FVID2_EFAIL;
+ }
+
+ /* Delete the graph object */
+ Dss_dctrlDrvGraphDeInit((void *) pGraphObj);
+
+ numRegEvtHandle = instObj->numRegEvtHandle;
+ /* Unregister event groups and delete object */
+ for(cnt=0U; cnt<numRegEvtHandle; cnt++)
+ {
+ (void) Dss_evtMgrUnRegister(instObj->evtGroupHandle[cnt]);
+ instObj->numRegEvtHandle--;
+ }
+
+ /* Delete the instance semaphore */
+ if(NULL != instObj->lockSem)
+ {
+ (void) SemaphoreP_delete(instObj->lockSem);
+ instObj->lockSem = NULL;
+ }
+
+ for(i=0U; i<CSL_DSS_VID_PIPE_ID_MAX; i++)
+ {
+ /* Delete instance semaphore */
+ if(NULL != pDrvInfo->pipeInfo[i].stopSem)
+ {
+ (void) SemaphoreP_delete(pDrvInfo->pipeInfo[i].stopSem);
+ pDrvInfo->pipeInfo[i].stopSem = NULL;
+ }
+ }
+
+ instObj->drvState.isInit = FALSE;
+ pObj->instObj = NULL;
+ }
+
+ if(TRUE == pObj->isRegistered)
+ {
+ /* Unregister from driver manager */
+ retVal = Fvid2_unRegisterDriver(&pObj->fvidDrvOps);
+ if(FVID2_SOK != retVal)
+ {
+ GT_0trace(DssTrace,
+ GT_ERR,
+ "Unregistering from FVID2 driver manager failed\r\n");
+ }
+ pObj->isRegistered = FALSE;
+ }
+
+ return (retVal);
+}
+
+DssDctrlDrvClientHandle Dss_dctrlDrvRegisterClient(
+ uint32_t nodeId,
+ const Dss_DctrlDrvClientInfo *clientInfo)
+{
+ uint32_t i;
+ DssDctrlDrvClientHandle clientHandle = NULL;
+ GT_assert(DssTrace, (NULL != clientInfo));
+ GT_assert(DssTrace,
+ (gDss_DctrlDrvInfo.numValidPipes <= CSL_DSS_VID_PIPE_ID_MAX));
+
+ for(i=0U; i<gDss_DctrlDrvInfo.numValidPipes; i++)
+ {
+ if(gDss_DctrlDrvInfo.pipeInfo[i].pipeNodeId == nodeId)
+ {
+ gDss_DctrlDrvInfo.pipeInfo[i].gClientInfo.cbFxn = clientInfo->cbFxn;
+ gDss_DctrlDrvInfo.pipeInfo[i].gClientInfo.arg = clientInfo->arg;
+ gDss_DctrlDrvInfo.pipeInfo[i].pipeState = DSS_DCTRL_PIPE_OPENED;
+ clientHandle = &gDss_DctrlDrvInfo.pipeInfo[i];
+ break;
+ }
+ }
+
+ return clientHandle;
+}
+
+int32_t Dss_dctrlDrvUnRegisterClient(DssDctrlDrvClientHandle handle)
+{
+ int32_t retVal = FVID2_SOK;
+ Dss_DctrlDrvPipeInfo *pipeInfo;
+ GT_assert(DssTrace, (NULL != handle));
+
+ pipeInfo = (Dss_DctrlDrvPipeInfo *) handle;
+ pipeInfo->gClientInfo.cbFxn = NULL;
+ pipeInfo->gClientInfo.arg = NULL;
+ pipeInfo->pipeState = DSS_DCTRL_PIPE_IDLE;
+
+ return retVal;
+}
+
+int32_t Dss_dctrlDrvStartClient(DssDctrlDrvClientHandle handle,
+ uint32_t dummyStart)
+{
+ int32_t retVal = FVID2_SOK;
+ uint32_t cookie;
+ Dss_DctrlDrvPipeInfo *pipeInfo;
+ GT_assert(DssTrace, (NULL != handle));
+
+ cookie = HwiP_disable();
+
+ pipeInfo = (Dss_DctrlDrvPipeInfo *) handle;
+ if(TRUE == dummyStart)
+ {
+ pipeInfo->pipeState = DSS_DCTRL_PIPE_STARTING;
+ }
+ else
+ {
+ pipeInfo->pipeState = DSS_DCTRL_PIPE_STARTED;
+ }
+
+ if(FALSE == dummyStart)
+ {
+ retVal = Dss_dctrlDrvSetGoBit(handle);
+ }
+
+ HwiP_restore(cookie);
+
+ return retVal;
+}
+
+int32_t Dss_dctrlDrvStopClient(DssDctrlDrvClientHandle handle,
+ uint32_t syncStop)
+{
+ int32_t retVal = FVID2_SOK;
+ uint32_t cookie;
+ Dss_DctrlDrvPipeInfo *pipeInfo;
+ GT_assert(DssTrace, (NULL != handle));
+
+ cookie = HwiP_disable();
+ pipeInfo = (Dss_DctrlDrvPipeInfo *) handle;
+ if(TRUE == syncStop)
+ {
+ pipeInfo->pipeState = DSS_DCTRL_PIPE_STOPPING;
+ }
+ else
+ {
+ pipeInfo->pipeState = DSS_DCTRL_PIPE_STOPPED;
+ }
+
+ if(FALSE == syncStop)
+ {
+ retVal = Dss_dctrlDrvSetGoBit(handle);
+ }
+
+ HwiP_restore(cookie);
+
+ /* Take the stop semaphore */
+ (void) SemaphoreP_pend(pipeInfo->stopSem, SemaphoreP_WAIT_FOREVER);
+ return retVal;
+}
+
+int32_t Dss_dctrlDrvGetVpParams(DssDctrlDrvClientHandle handle,
+ Dss_DctrlVpParams *vpParams)
+{
+ int32_t retVal = FVID2_SOK;
+ uint32_t i;
+ Dss_DctrlDrvPipeInfo *pipeInfo;
+ Dss_DctrlDrvInstObj *instObj;
+ Dss_DctrlDrvCommonObj *pObj = &gDss_DctrlDrvCommonObj;
+ GT_assert(DssTrace, (NULL != handle));
+
+ instObj = pObj->instObj;
+
+ /* Take the instance semaphore */
+ (void) SemaphoreP_pend(instObj->lockSem, SemaphoreP_WAIT_FOREVER);
+
+ /* Get VP Params */
+ pipeInfo = (Dss_DctrlDrvPipeInfo *) handle;
+ for(i=0U; i<CSL_DSS_VP_ID_MAX; i++)
+ {
+ if(pipeInfo->vpId == gDss_DctrlDrvInfo.vpParams[i].vpId)
+ {
+ vpParams->lcdOpTimingCfg.mInfo.scanFormat =
+ gDss_DctrlDrvInfo.vpParams[i].lcdOpTimingCfg.mInfo.scanFormat;
+ vpParams->lcdOpTimingCfg.mInfo.standard =
+ gDss_DctrlDrvInfo.vpParams[i].lcdOpTimingCfg.mInfo.standard;
+ vpParams->lcdOpTimingCfg.mInfo.width =
+ gDss_DctrlDrvInfo.vpParams[i].lcdOpTimingCfg.mInfo.width;
+ vpParams->lcdOpTimingCfg.mInfo.height =
+ gDss_DctrlDrvInfo.vpParams[i].lcdOpTimingCfg.mInfo.height;
+ vpParams->vpId = gDss_DctrlDrvInfo.vpParams[i].vpId;
+ break;
+ }
+ }
+
+ /* Post the instance semaphore */
+ (void) SemaphoreP_post(instObj->lockSem);
+
+ return retVal;
+}
+
+int32_t Dss_dctrlDrvSetGoBit(DssDctrlDrvClientHandle handle)
+{
+ int32_t retVal = FVID2_SOK;
+ Dss_DctrlDrvPipeInfo *pipeInfo;
+ GT_assert(DssTrace, (NULL != handle));
+
+ pipeInfo = (Dss_DctrlDrvPipeInfo *) handle;
+
+ /* Set Go Bit */
+ Dss_dctrlVpSetGoBit(pipeInfo->vpId);
+
+ return (retVal);
+}
+
+uint32_t Dss_dctrlDrvIsSafeToPush(DssDctrlDrvClientHandle handle)
+{
+ uint32_t retVal = FALSE, cookie;
+ Dss_DctrlDrvPipeInfo *pipeInfo;
+ GT_assert(DssTrace, (NULL != handle));
+
+ pipeInfo = (Dss_DctrlDrvPipeInfo *) handle;
+ cookie = HwiP_disable();
+ retVal = gDss_DctrlDrvInfo.isPushSafe[pipeInfo->vpId];
+ HwiP_restore(cookie);
+
+ return retVal;
+}
+
+Dss_DctrlDrvPipeInfo *Dss_dctrlDrvGetPipeInfo(DssDctrlDrvClientHandle handle)
+{
+ uint32_t i;
+ Dss_DctrlDrvPipeInfo *pipeInfo;
+ GT_assert(DssTrace, (NULL != handle));
+
+ pipeInfo = (Dss_DctrlDrvPipeInfo *) handle;
+ for(i=0U; i<gDss_DctrlDrvInfo.numValidPipes; i++)
+ {
+ if((gDss_DctrlDrvInfo.pipeInfo[i].pipeId == pipeInfo->pipeId) &&
+ ((gDss_DctrlDrvInfo.pipeInfo[i].pipeState ==
+ DSS_DCTRL_PIPE_OPENED) ||
+ (gDss_DctrlDrvInfo.pipeInfo[i].pipeState ==
+ DSS_DCTRL_PIPE_STARTING) ||
+ (gDss_DctrlDrvInfo.pipeInfo[i].pipeState ==
+ DSS_DCTRL_PIPE_STARTED) ||
+ (gDss_DctrlDrvInfo.pipeInfo[i].pipeState ==
+ DSS_DCTRL_PIPE_RUNNING) ||
+ (gDss_DctrlDrvInfo.pipeInfo[i].pipeState ==
+ DSS_DCTRL_PIPE_STOPPING) ||
+ (gDss_DctrlDrvInfo.pipeInfo[i].pipeState ==
+ DSS_DCTRL_PIPE_STOPPED)))
+ {
+ break;
+ }
+ }
+ return &gDss_DctrlDrvInfo.pipeInfo[i];
+}
+
+/* ========================================================================== */
+/* Static Function Definitions */
+/* ========================================================================== */
+
+static Fdrv_Handle Dss_dctrlDrvCreate(uint32_t drvId,
+ uint32_t instId,
+ void *createArgs,
+ void *createStatusArgs,
+ const Fvid2_DrvCbParams *fdmCbParams)
+{
+ int32_t retVal = FVID2_SOK;
+ Fdrv_Handle drvHandle = NULL;
+ Dss_DctrlDrvInstObj *instObj = NULL;
+ Dss_DctrlDrvCommonObj *pObj;
+
+ pObj = &gDss_DctrlDrvCommonObj;
+
+ GT_assert(DssTrace, (NULL != pObj));
+ GT_assert(DssTrace, (NULL != pObj->instObj));
+
+ instObj = pObj->instObj;
+
+ if(NULL == instObj)
+ {
+ GT_0trace(DssTrace, GT_ERR, "Invalid instance ID\r\n");
+ retVal = FVID2_EINVALID_PARAMS;
+ }
+
+ if(NULL != instObj)
+ {
+ /* Take the instance semaphore */
+ (void) SemaphoreP_pend(instObj->lockSem, SemaphoreP_WAIT_FOREVER);
+ }
+
+ if(FVID2_SOK == retVal)
+ {
+ /* Initialize instance variables */
+ if(0U == instObj->numOpenDrvHandle)
+ {
+ instObj->drvState.isOpened = TRUE;
+ }
+ instObj->numOpenDrvHandle++;
+ drvHandle = instObj;
+ }
+
+ if(NULL != instObj)
+ {
+ /* Post the instance semaphore */
+ (void) SemaphoreP_post(instObj->lockSem);
+ }
+
+ return (drvHandle);
+}
+
+static int32_t Dss_dctrlDrvDelete(Fdrv_Handle handle, void *reserved)
+{
+ int32_t retVal = FVID2_SOK;
+
+ Dss_DctrlDrvInstObj *instObj = NULL, *pInstObj = NULL;
+ Dss_DctrlDrvCommonObj *pObj;
+
+ /* Check for NULL pointers and invalid arguments */
+ if(NULL == handle)
+ {
+ GT_0trace(DssTrace, GT_ERR, "Invalid arguments\r\n");
+ retVal = FVID2_EBADARGS;
+ }
+ else
+ {
+ instObj = (Dss_DctrlDrvInstObj *) handle;
+ pObj = &gDss_DctrlDrvCommonObj;
+ pInstObj = pObj->instObj;
+ }
+
+ if(instObj != pInstObj)
+ {
+ GT_0trace(DssTrace, GT_ERR, "Invalid arguments\r\n");
+ retVal = FVID2_EBADARGS;
+ }
+
+ if((NULL != instObj) && (FVID2_SOK == retVal))
+ {
+ /* Take the instance semaphore */
+ (void) SemaphoreP_pend(instObj->lockSem, SemaphoreP_WAIT_FOREVER);
+
+ /* Check if already opened. */
+ if(TRUE != instObj->drvState.isOpened)
+ {
+ GT_0trace(DssTrace, GT_ERR, "ERROR: Driver not opened\r\n");
+ retVal = FVID2_EFAIL;
+ }
+ }
+
+ if(FVID2_SOK == retVal)
+ {
+ /* Reset other variables */
+ instObj->numOpenDrvHandle--;
+ if(0U == instObj->numOpenDrvHandle)
+ {
+ instObj->drvState.isOpened = FALSE;
+ instObj->drvState.isStarted = FALSE;
+ }
+ }
+
+ if(NULL != instObj)
+ {
+ /* Post the instance semaphore */
+ (void) SemaphoreP_post(instObj->lockSem);
+ }
+
+ return (retVal);
+}
+
+static int32_t Dss_dctrlDrvControl(Fdrv_Handle handle,
+ uint32_t cmd,
+ void *cmdArgs,
+ void *cmdStatusArgs)
+{
+ int32_t retVal = FVID2_SOK;
+ Dss_DctrlDrvInstObj *instObj;
+
+ /* Check for NULL pointers */
+ if((NULL == handle) || (NULL == cmdArgs))
+ {
+ GT_0trace(DssTrace, GT_ERR, "Invalid argument!!\r\n");
+ retVal = FVID2_EBADARGS;
+ }
+
+ if(FVID2_SOK == retVal)
+ {
+ instObj = (Dss_DctrlDrvInstObj *) handle;
+ switch (cmd)
+ {
+ case IOCTL_DSS_DCTRL_SET_PATH:
+ retVal = Dss_dctrlDrvSetPathIoctl(
+ instObj,
+ (const Dss_DctrlPathInfo*) cmdArgs);
+ break;
+ case IOCTL_DSS_DCTRL_CLEAR_PATH:
+ retVal = Dss_dctrlDrvClearPathIoctl(
+ instObj,
+ (const Dss_DctrlPathInfo*) cmdArgs);
+ break;
+ case IOCTL_DSS_DCTRL_SET_VP_PARAMS:
+ retVal = Dss_dctrlDrvSetVpParamsIoctl(
+ instObj,
+ (const Dss_DctrlVpParams*) cmdArgs);
+ break;
+ case IOCTL_DSS_DCTRL_SET_OVERLAY_PARAMS:
+ retVal = Dss_dctrlDrvSetOverlayParamsIoctl(
+ instObj,
+ (const Dss_DctrlOverlayParams*) cmdArgs);
+ break;
+ case IOCTL_DSS_DCTRL_SET_LAYER_PARAMS:
+ retVal = Dss_dctrlDrvSetLayerParamsIoctl(
+ instObj,
+ (const Dss_DctrlOverlayLayerParams*) cmdArgs);
+ break;
+ case IOCTL_DSS_DCTRL_SET_VP_CSC_COEFF:
+ retVal = Dss_dctrlDrvSetVpCscCoeffIoctl(
+ instObj,
+ (const Dss_DctrlVpCscCoeff*) cmdArgs);
+ break;
+ case IOCTL_DSS_DCTRL_SET_ADV_VP_PARAMS:
+ retVal = Dss_dctrlDrvSetAdvVpParamsIoctl(
+ instObj,
+ (const Dss_DctrlAdvVpParams*) cmdArgs);
+ break;
+ case IOCTL_DSS_DCTRL_SET_LCD_BLANK_TIMING_PARAMS:
+ retVal = Dss_dctrlDrvSetLcdBlankTimingIoctl(
+ instObj,
+ (const Dss_DctrlLcdBlankTimingParams*) cmdArgs);
+ break;
+ case IOCTL_DSS_DCTRL_SET_VP_SAFETY_CHK_PARAMS:
+ retVal = Dss_dctrlDrvSetVpSafetyChkParamsIoctl(
+ instObj,
+ (const Dss_DctrlVpSafetyChkParams*) cmdArgs);
+ break;
+ case IOCTL_DSS_DCTRL_GET_VP_ERROR_STATS:
+ retVal = Dss_dctrlDrvGetErrorStatsIoctl(
+ instObj,
+ (Dss_DctrlVpErrorStats*) cmdArgs);
+ break;
+ case IOCTL_DSS_DCTRL_SET_GLOBAL_DSS_PARAMS:
+ retVal = Dss_dctrlDrvSetGlobalDssParamsIoctl(
+ instObj,
+ (const Dss_DctrlGlobalDssParams*) cmdArgs);
+ break;
+ case IOCTL_DSS_DCTRL_STOP_VP:
+ retVal = Dss_dctrlDrvStopVpIoctl(
+ instObj,
+ (const Dss_DctrlVpParams*) cmdArgs);
+ break;
+ case IOCTL_DSS_DCTRL_REGISTER_SYNCLOST_CB:
+ retVal = Dss_dctrlDrvSetSyncLostCbParamsIoctl(
+ instObj,
+ (const Dss_DctrlSyncLostCbParams*) cmdArgs);
+ break;
+ case IOCTL_DSS_DCTRL_REGISTER_LINENUM_CB:
+ retVal = Dss_dctrlDrvSetLineNumCbParamsIoctl(
+ instObj,
+ (const Dss_DctrlLineNumCbParams*) cmdArgs);
+ break;
+#if defined (SOC_AM65XX)
+ case IOCTL_DSS_DCTRL_SET_OLDI_PARAMS:
+ retVal = Dss_dctrlDrvSetOldiParamsIoctl(
+ instObj,
+ (const Dss_DctrlOldiParams*) cmdArgs);
+ break;
+#endif
+#if defined (SOC_J721E)
+ case IOCTL_DSS_DCTRL_PROCESS_DP_HPD:
+ retVal = Dss_dctrlDrvProcessDpHpdIoctl(
+ instObj,
+ (const uint32_t*) cmdArgs);
+ break;
+ case IOCTL_DSS_DCTRL_REGISTER_DP_HPD_CB:
+ retVal = Dss_dctrlDrvSetDpHpdCbParamsIoctl(
+ instObj,
+ (const Dss_DctrlDpHpdCbParams*) cmdArgs);
+ break;
+#endif
+ default:
+ GT_0trace(DssTrace,
+ GT_ERR,
+ "UNSUPPORTED_CMD: IOCTL not supported\r\n");
+ retVal = FVID2_EUNSUPPORTED_CMD;
+ break;
+ }
+ }
+
+ return (retVal);
+}
+
+static int32_t Dss_dctrlDrvSetPathIoctl(Dss_DctrlDrvInstObj *instObj,
+ const Dss_DctrlPathInfo *pathInfo)
+{
+ int32_t retVal = FVID2_SOK;
+ uint32_t i, j, k, moduleId, currPipeNum;
+ Fvid2_GraphEdgeInfo *currEdge, *vpEdge, *outEdge;
+ Dss_DctrlDrvPipeInfo *pPipeInfo;
+
+ /* Check for NULL pointers */
+ GT_assert(DssTrace, (NULL != instObj));
+ GT_assert(DssTrace, (NULL != pathInfo));
+
+ /* Take the instance semaphore */
+ (void) SemaphoreP_pend(instObj->lockSem, SemaphoreP_WAIT_FOREVER);
+
+ gDss_DctrlDrvInfo.numValidPipes = 0;
+
+ if(0U != pathInfo->numEdges)
+ {
+ retVal = Dss_dctrlDrvCreateEdgeList(&gDss_DctrlDrvGraphObj,
+ pathInfo);
+ }
+
+ if((FVID2_SOK == retVal) && (0U != pathInfo->numEdges))
+ {
+ for(i=0U; i<gDss_DctrlDrvGraphObj.dctrlEdgeList.numEdges; i++)
+ {
+ currEdge = &gDss_DctrlDrvGraphObj.dctrlEdgeList.list[i];
+
+ if(TRUE == Dss_dctrlIsPipeNode(currEdge->startNode))
+ {
+ /* Start graph construction from pipe */
+ currPipeNum = gDss_DctrlDrvInfo.numValidPipes;
+ pPipeInfo = &gDss_DctrlDrvInfo.pipeInfo[currPipeNum];
+ GT_assert(DssTrace, (currPipeNum <= CSL_DSS_VID_PIPE_ID_MAX));
+ pPipeInfo->pipeNodeId = currEdge->startNode;
+ /* Get Pipe Id */
+ retVal = Dss_convNodetoModule(currEdge->startNode, &moduleId);
+ GT_assert(DssTrace,
+ ((CSL_DSS_MODULE_INVALID != moduleId) ||
+ (FVID2_SOK == retVal)));
+ pPipeInfo->pipeId = moduleId;
+ pPipeInfo->pipeState = DSS_DCTRL_PIPE_IDLE;
+ /* Assign overlay node & overlay id */
+ pPipeInfo->overlayNodeId = currEdge->endNode;
+ retVal = Dss_convNodetoModule(currEdge->endNode, &moduleId);
+ GT_assert(DssTrace,
+ ((CSL_DSS_MODULE_INVALID != moduleId) ||
+ (FVID2_SOK == retVal)));
+ pPipeInfo->overlayId = moduleId;
+ retVal = Dss_dctrlConnectNodes(pPipeInfo->pipeNodeId,
+ pPipeInfo->overlayNodeId);
+ GT_assert(DssTrace, (FVID2_SOK == retVal));
+
+ /* Find video port connected to overlay */
+ for(j=0U; j<gDss_DctrlDrvGraphObj.dctrlEdgeList.numEdges; j++)
+ {
+ vpEdge = &gDss_DctrlDrvGraphObj.dctrlEdgeList.list[j];
+ if(vpEdge->startNode == currEdge->endNode)
+ {
+ /* Assign video port node and video port id */
+ pPipeInfo->vpNodeId = vpEdge->endNode;
+ retVal = Dss_convNodetoModule(vpEdge->endNode,
+ &moduleId);
+ GT_assert(DssTrace,
+ ((CSL_DSS_MODULE_INVALID != moduleId) ||
+ (FVID2_SOK == retVal)));
+ pPipeInfo->vpId = moduleId;
+ retVal = Dss_dctrlConnectNodes(pPipeInfo->overlayNodeId,
+ pPipeInfo->vpNodeId);
+ GT_assert(DssTrace, (FVID2_SOK == retVal));
+
+ /* Find output node connected to video port */
+ for(k=0U; k<gDss_DctrlDrvGraphObj.dctrlEdgeList.numEdges; k++)
+ {
+ /* Assign output node */
+ outEdge = &gDss_DctrlDrvGraphObj.dctrlEdgeList.list[k];
+ if(outEdge->startNode == vpEdge->endNode)
+ {
+ pPipeInfo->outNodeId = outEdge->endNode;
+ retVal = Dss_dctrlConnectNodes(
+ pPipeInfo->vpNodeId,
+ pPipeInfo->outNodeId);
+ GT_assert(DssTrace, (FVID2_SOK == retVal));
+ }
+ }
+ }
+ }
+ gDss_DctrlDrvInfo.numValidPipes++;
+ }
+ }
+ }
+
+ if(FVID2_SOK != retVal)
+ {
+ GT_0trace(DssTrace, GT_ERR, "Set Path IOCTL failed\r\n");
+ }
+
+ /* Post the instance semaphore */
+ (void) SemaphoreP_post(instObj->lockSem);
+
+ return retVal;
+}
+
+static int32_t Dss_dctrlDrvClearPathIoctl(Dss_DctrlDrvInstObj *instObj,
+ const Dss_DctrlPathInfo *pathInfo)
+{
+ int32_t retVal = FVID2_SOK;
+
+ /* Check for NULL pointers */
+ GT_assert(DssTrace, (NULL != instObj));
+ GT_assert(DssTrace, (NULL != pathInfo));
+
+ /* Take the instance semaphore */
+ (void) SemaphoreP_pend(instObj->lockSem, SemaphoreP_WAIT_FOREVER);
+
+ Dss_dctrlDrvFreeEdgeList(&gDss_DctrlDrvGraphObj);
+
+ if(FVID2_SOK != retVal)
+ {
+ GT_0trace(DssTrace, GT_ERR, "Clear Path IOCTL failed\r\n");
+ }
+
+ /* Post the instance semaphore */
+ (void) SemaphoreP_post(instObj->lockSem);
+
+ return retVal;
+}
+
+static int32_t Dss_dctrlDrvSetVpParamsIoctl(
+ Dss_DctrlDrvInstObj *instObj,
+ const Dss_DctrlVpParams *vpParams)
+{
+ int32_t retVal = FVID2_SOK;
+ uint32_t i, vpId, syncVpId, vpFound = FALSE;
+ CSL_dss_vpRegs *vpRegs;
+ const Dss_SocInfo *socInfo;
+ const CSL_DssVpLcdOpTimingCfg *lcdOpTimingCfg;
+ const CSL_DssVpLcdSignalPolarityCfg *lcdPolarityCfg;
+ const CSL_DssVpLcdTdmCfg *lcdTdmCfg;
+ const Dss_DctrlSyncOpCfg *syncOpCfg;
+ Dss_DctrlVpParams *pVpParams;
+ Dss_DctrlDrvInfo *pDrvInfo;
+
+ pDrvInfo = &gDss_DctrlDrvInfo;
+
+ /* Check for NULL pointers */
+ GT_assert(DssTrace, (NULL != instObj));
+ GT_assert(DssTrace, (NULL != vpParams));
+
+ /* Check for wrong inputs */
+ if(vpParams->vpId >= CSL_DSS_VP_ID_MAX)
+ {
+ GT_0trace(DssTrace, GT_ERR, "Invalid argument!!\r\n");
+ retVal = FVID2_EBADARGS;
+ }
+
+ /* Take the instance semaphore */
+ (void) SemaphoreP_pend(instObj->lockSem, SemaphoreP_WAIT_FOREVER);
+
+ if(FVID2_SOK == retVal)
+ {
+ /* Check if VP was already running */
+ vpId = vpParams->vpId;
+ for(i = 0U; i < CSL_DSS_VP_ID_MAX; i++)
+ {
+ if((gDss_DctrlDrvInfo.vpParams[i].vpId == vpId) &&
+ (DSS_DCTRL_VP_IDLE != gDss_DctrlDrvInfo.vpState[vpId]))
+ {
+ retVal = FVID2_EDEVICE_INUSE;
+ GT_0trace(DssTrace, GT_ERR, "VP is already in use!!\r\n");
+ break;
+ }
+ }
+ }
+
+ if(FVID2_SOK == retVal)
+ {
+ /* Assign input parameters */
+ lcdOpTimingCfg = &vpParams->lcdOpTimingCfg;
+ lcdPolarityCfg = &vpParams->lcdPolarityCfg;
+ lcdTdmCfg = &vpParams->lcdTdmCfg;
+ syncOpCfg = &vpParams->syncOpCfg;
+ pVpParams = &gDss_DctrlDrvInfo.vpParams[vpId];
+
+ pVpParams->syncOpCfg.enabled = syncOpCfg->enabled;
+ pVpParams->syncOpCfg.isPrimary = syncOpCfg->isPrimary;
+ pVpParams->syncOpCfg.numSyncVpIds = syncOpCfg->numSyncVpIds;
+ for(i = 0; i < syncOpCfg->numSyncVpIds; i++)
+ {
+ pVpParams->syncOpCfg.syncVpIds[i] = syncOpCfg->syncVpIds[i];
+ }
+
+ pVpParams->lcdOpTimingCfg.mInfo.scanFormat =
+ lcdOpTimingCfg->mInfo.scanFormat;
+ pVpParams->lcdOpTimingCfg.mInfo.standard =
+ lcdOpTimingCfg->mInfo.standard;
+ pVpParams->lcdOpTimingCfg.mInfo.height =
+ lcdOpTimingCfg->mInfo.height;
+ pVpParams->lcdOpTimingCfg.mInfo.width =
+ lcdOpTimingCfg->mInfo.width;
+ pVpParams->vpId = vpId;
+ }
+
+ if((FVID2_SOK == retVal) &&
+ (TRUE == vpParams->syncOpCfg.enabled) &&
+ (TRUE == vpParams->syncOpCfg.isPrimary))
+ {
+ syncOpCfg = &vpParams->syncOpCfg;
+
+ for(i = 0; i < syncOpCfg->numSyncVpIds; i++)
+ {
+ syncVpId = syncOpCfg->syncVpIds[i];
+
+ if(DSS_DCTRL_VP_STARTING != pDrvInfo->vpState[syncVpId])
+ {
+ vpFound = TRUE;
+ break;
+ }
+ }
+ if(TRUE == vpFound)
+ {
+ retVal = FVID2_EBADARGS;
+ GT_0trace(DssTrace, GT_ERR, "Secondary sync VPs not started!!\r\n");
+ }
+ }
+
+ if(FVID2_SOK == retVal)
+ {
+ /* Get video port registers */
+ socInfo = Dss_getSocInfo();
+ vpRegs = socInfo->vpRegs[vpId];
+ GT_assert(DssTrace, (NULL != vpRegs));
+
+ /* Not safe to push */
+ gDss_DctrlDrvInfo.isPushSafe[vpId] = FALSE;
+
+ /* Call CSL APIs */
+ CSL_dssVpSetLcdSignalPolarityConfig(vpRegs, lcdPolarityCfg);
+ CSL_dssVpSetLcdTdmConfig(vpRegs, lcdTdmCfg);
+ retVal = CSL_dssVpSetLcdOpTimingConfig(vpRegs, lcdOpTimingCfg);
+
+ if(FVID2_SOK != retVal)
+ {
+ GT_assert(DssTrace, FALSE);
+ }
+
+ if(lcdOpTimingCfg->mInfo.height > 5U)
+ {
+ CSL_dssVpSetLcdLineNum(vpRegs, lcdOpTimingCfg->mInfo.height - 5U);
+ }
+
+ Dss_dctrlVpEnable(vpId, TRUE);
+ }
+
+#if defined (SOC_J721E)
+ if((FVID2_SOK == retVal) &&
+ (TRUE == Dss_dctrlDrvIsOutputDP(vpId)))
+ {
+ retVal = Dss_dctrlDrvEnableVideoDP(&lcdOpTimingCfg->mInfo,
+ lcdPolarityCfg->hsPolarity,
+ lcdPolarityCfg->vsPolarity);
+ }
+#endif
+
+ if(FVID2_SOK != retVal)
+ {
+ GT_0trace(DssTrace, GT_ERR, "Set VP parameters IOCTL failed\r\n");
+ }
+
+ /* Post the instance semaphore */
+ (void) SemaphoreP_post(instObj->lockSem);
+
+ return retVal;
+}
+
+#if defined (SOC_J721E)
+static int32_t Dss_dctrlDrvProcessDpHpdIoctl(
+ Dss_DctrlDrvInstObj *instObj,
+ const uint32_t *dpProcessHpdParams)
+{
+ int32_t retVal = FVID2_SOK;
+ uint32_t hpdState;
+
+ /* Check for NULL pointers */
+ GT_assert(DssTrace, (NULL != instObj));
+ GT_assert(DssTrace, (NULL != dpProcessHpdParams));
+
+ hpdState = *dpProcessHpdParams;
+
+ if(FVID2_SOK == retVal)
+ {
+ retVal = Dss_dctrlDrvProcessHpdDp(hpdState);
+ }
+
+ return retVal;
+}
+
+static int32_t Dss_dctrlDrvSetDpHpdCbParamsIoctl(
+ Dss_DctrlDrvInstObj *instObj,
+ const Dss_DctrlDpHpdCbParams *dpHpdCbParams)
+{
+ int32_t retVal = FVID2_SOK;
+
+ /* Check for NULL pointers */
+ GT_assert(DssTrace, (NULL != instObj));
+ GT_assert(DssTrace, (NULL != dpHpdCbParams));
+
+ if(FVID2_SOK == retVal)
+ {
+ retVal = Dss_dctrlDrvRegisterHpdCb(dpHpdCbParams);
+ }
+
+ if(FVID2_SOK != retVal)
+ {
+ GT_0trace(DssTrace,
+ GT_ERR,
+ "Register Display port HPD CB Params IOCTL failed\r\n");
+ }
+
+ return retVal;
+}
+
+static uint32_t Dss_dctrlDrvIsOutputDP(uint32_t vpId)
+{
+ int32_t retVal;
+ uint32_t i;
+ uint32_t nodeId, vpFound = FALSE;
+ Fvid2_GraphEdgeInfo *currEdge;
+
+ retVal = Dss_convModuletoNode(&nodeId, vpId, DSS_DCTRL_NODE_TYPE_VP);
+ GT_assert(DssTrace,
+ ((DSS_DCTRL_NODE_INVALID != nodeId) ||
+ (FVID2_SOK == retVal)));
+
+ for(i=0U; i<gDss_DctrlDrvGraphObj.dctrlEdgeList.numEdges; i++)
+ {
+ currEdge = &gDss_DctrlDrvGraphObj.dctrlEdgeList.list[i];
+ if((DSS_DCTRL_NODE_EDP_DPI0 == currEdge->endNode) &&
+ (nodeId == currEdge->startNode))
+ {
+ vpFound = TRUE;
+ break;
+ }
+ }
+
+ return vpFound;
+}
+#endif
+
+
+static int32_t Dss_dctrlDrvSetOverlayParamsIoctl(
+ Dss_DctrlDrvInstObj *instObj,
+ const Dss_DctrlOverlayParams *overlayParams)
+{
+ int32_t retVal = FVID2_SOK;
+ uint32_t vpId, overlayId = overlayParams->overlayId;
+ CSL_dss_overlayRegs *overlayRegs;
+ const Dss_SocInfo *socInfo;
+ const CSL_DssOverlayCfg *overlayCfg;
+
+ /* Check for NULL pointers */
+ GT_assert(DssTrace, (NULL != instObj));
+ GT_assert(DssTrace, (NULL != overlayParams));
+
+ /* Check for wrong inputs */
+ if(overlayId >= CSL_DSS_OVERLAY_ID_MAX)
+ {
+ GT_0trace(DssTrace, GT_ERR, "Invalid argument!!\r\n");
+ retVal = FVID2_EBADARGS;
+ }
+
+ /* Take the instance semaphore */
+ (void) SemaphoreP_pend(instObj->lockSem, SemaphoreP_WAIT_FOREVER);
+
+ if(FVID2_SOK == retVal)
+ {
+ /* Get overlay registers */
+ socInfo = Dss_getSocInfo();
+ overlayRegs = socInfo->overlayRegs[overlayId];
+ GT_assert(DssTrace, (NULL != overlayRegs));
+
+ /* Get video port registers */
+ vpId = Dss_getVpConnId(overlayId);
+ GT_assert(DssTrace, (CSL_DSS_MODULE_INVALID != vpId));
+
+ /* Assign input parameters */
+ overlayCfg = &overlayParams->overlayCfg;
+
+ /* Call CSL APIs */
+ if(FALSE == overlayParams->colorbarEnable)
+ {
+ CSL_dssOverlayColorBarEnable(overlayRegs, FALSE);
+ CSL_dssOverlaySetConfig(overlayRegs, overlayCfg);
+ }
+ else
+ {
+ CSL_dssOverlayColorBarEnable(overlayRegs, TRUE);
+ Dss_dctrlVpSetGoBit(vpId);
+ }
+ }
+
+ if(FVID2_SOK != retVal)
+ {
+ GT_0trace(DssTrace, GT_ERR, "Set overlay parameters IOCTL failed\r\n");
+ }
+
+ /* Post the instance semaphore */
+ (void) SemaphoreP_post(instObj->lockSem);
+
+ return retVal;
+}
+
+static int32_t Dss_dctrlDrvSetLayerParamsIoctl(
+ Dss_DctrlDrvInstObj *instObj,
+ const Dss_DctrlOverlayLayerParams *layerParams)
+{
+ int32_t retVal = FVID2_SOK;
+ uint32_t i, overlayId = layerParams->overlayId;
+ CSL_dss_overlayRegs *overlayRegs;
+ const Dss_SocInfo *socInfo;
+ CSL_DssOverlayLayerCfg layerCfg;
+
+ /* Check for NULL pointers */
+ GT_assert(DssTrace, (NULL != instObj));
+ GT_assert(DssTrace, (NULL != layerParams));
+
+ /* Check for wrong inputs */
+ if(overlayId >= CSL_DSS_OVERLAY_ID_MAX)
+ {
+ GT_0trace(DssTrace, GT_ERR, "Invalid argument!!\r\n");
+ retVal = FVID2_EBADARGS;
+ }
+
+ /* Take the instance semaphore */
+ (void) SemaphoreP_pend(instObj->lockSem, SemaphoreP_WAIT_FOREVER);
+
+ if(FVID2_SOK == retVal)
+ {
+ /* Initialize layer configuration */
+ CSL_dssOverlayLayerCfgInit(&layerCfg);
+
+ /* Get overlay registers */
+ socInfo = Dss_getSocInfo();
+ overlayRegs = socInfo->overlayRegs[overlayId];
+ GT_assert(DssTrace, (NULL != overlayRegs));
+
+ /* Call CSL APIs */
+ for(i=0U; i<CSL_DSS_VID_PIPE_ID_MAX; i++)
+ {
+ if(CSL_DSS_OVERLAY_LAYER_INVALID != layerParams->pipeLayerNum[i])
+ {
+ layerCfg.layerEnable = TRUE;
+ layerCfg.layerNum = layerParams->pipeLayerNum[i];
+ layerCfg.inputPipe = i;
+ CSL_dssOverlaySetLayerConfig(
+ overlayRegs,
+ (const CSL_DssOverlayLayerCfg *) &layerCfg);
+ }
+ }
+ }
+
+ if(FVID2_SOK != retVal)
+ {
+ GT_0trace(DssTrace, GT_ERR, "Set layer parameters IOCTL failed\r\n");
+ }
+
+ /* Post the instance semaphore */
+ (void) SemaphoreP_post(instObj->lockSem);
+
+ return retVal;
+}
+
+static int32_t Dss_dctrlDrvSetVpCscCoeffIoctl(
+ Dss_DctrlDrvInstObj *instObj,
+ const Dss_DctrlVpCscCoeff *vpCscCoeff)
+{
+ int32_t retVal = FVID2_SOK;
+ uint32_t cscPos, vpId;
+ CSL_dss_vpRegs *vpRegs;
+ const Dss_SocInfo *socInfo;
+ const CSL_DssCscCoeff *cscCoeff;
+
+ /* Check for NULL pointers */
+ GT_assert(DssTrace, (NULL != instObj));
+ GT_assert(DssTrace, (NULL != vpCscCoeff));
+
+ /* Take the instance semaphore */
+ (void) SemaphoreP_pend(instObj->lockSem, SemaphoreP_WAIT_FOREVER);
+
+ /* Get video port registers */
+ vpId = vpCscCoeff->vpId;
+ socInfo = Dss_getSocInfo();
+ vpRegs = socInfo->vpRegs[vpId];
+ GT_assert(DssTrace, (NULL != vpRegs));
+
+ /* Assign input parameters */
+ cscPos = vpCscCoeff->cscPos;
+ cscCoeff = &vpCscCoeff->cscCoeff;
+
+ /* Call CSL API */
+ if(FVID2_SOK == retVal)
+ {
+ CSL_dssVpSetCSCCoeff(vpRegs, cscCoeff, cscPos, TRUE);
+ }
+
+ if(FVID2_SOK != retVal)
+ {
+ GT_0trace(DssTrace, GT_ERR, "Set VP CSC coefficients IOCTL failed\r\n");
+ }
+
+ /* Post the instance semaphore */
+ (void) SemaphoreP_post(instObj->lockSem);
+
+ return retVal;
+}
+
+static int32_t Dss_dctrlDrvSetAdvVpParamsIoctl(
+ Dss_DctrlDrvInstObj *instObj,
+ const Dss_DctrlAdvVpParams *advVpParams)
+{
+ int32_t retVal = FVID2_SOK;
+ CSL_dss_vpRegs *vpRegs;
+ const Dss_SocInfo *socInfo;
+ const CSL_DssVpLcdAdvSignalCfg *lcdAdvSignalCfg;
+
+ /* Check for NULL pointers */
+ GT_assert(DssTrace, (NULL != instObj));
+ GT_assert(DssTrace, (NULL != advVpParams));
+
+ /* Check for wrong inputs */
+ if(advVpParams->vpId >= CSL_DSS_VP_ID_MAX)
+ {
+ GT_0trace(DssTrace, GT_ERR, "Invalid argument!!\r\n");
+ retVal = FVID2_EBADARGS;
+ }
+
+ /* Take the instance semaphore */
+ (void) SemaphoreP_pend(instObj->lockSem, SemaphoreP_WAIT_FOREVER);
+
+ if(FVID2_SOK == retVal)
+ {
+ /* Get video port registers */
+ socInfo = Dss_getSocInfo();
+ vpRegs = socInfo->vpRegs[advVpParams->vpId];
+ GT_assert(DssTrace, (NULL != vpRegs));
+
+ /* Assign input parameters */
+ lcdAdvSignalCfg = &advVpParams->lcdAdvSignalCfg;
+
+ /* Call CSL APIs */
+ CSL_dssVpSetLcdAdvSignalConfig(vpRegs, lcdAdvSignalCfg);
+ }
+
+ if(FVID2_SOK != retVal)
+ {
+ GT_0trace(DssTrace,
+ GT_ERR,
+ "Set advance VP parameters IOCTL failed\r\n");
+ }
+
+ /* Post the instance semaphore */
+ (void) SemaphoreP_post(instObj->lockSem);
+
+ return retVal;
+}
+
+static int32_t Dss_dctrlDrvSetLcdBlankTimingIoctl(
+ Dss_DctrlDrvInstObj *instObj,
+ const Dss_DctrlLcdBlankTimingParams *timingParams)
+{
+ int32_t retVal = FVID2_SOK;
+ uint32_t vpId, scanFormat;
+ CSL_dss_vpRegs *vpRegs;
+ const Dss_SocInfo *socInfo;
+ const CSL_DssVpLcdBlankTimingCfg *lcdBlankTimingCfg;
+
+ /* Check for NULL pointers */
+ GT_assert(DssTrace, (NULL != instObj));
+ GT_assert(DssTrace, (NULL != timingParams));
+
+ /* Check for wrong inputs */
+ if(timingParams->vpId >= CSL_DSS_VP_ID_MAX)
+ {
+ GT_0trace(DssTrace, GT_ERR, "Invalid argument!!\r\n");
+ retVal = FVID2_EBADARGS;
+ }
+
+ /* Take the instance semaphore */
+ (void) SemaphoreP_pend(instObj->lockSem, SemaphoreP_WAIT_FOREVER);
+
+ if(FVID2_SOK == retVal)
+ {
+ /* Assign input parameters */
+ vpId = timingParams->vpId;
+ lcdBlankTimingCfg = &timingParams->lcdBlankTimingCfg;
+
+ /* Get scan format */
+ scanFormat = gDss_DctrlDrvInfo.vpParams[vpId].lcdOpTimingCfg.mInfo.scanFormat;
+
+ /* Get video port registers */
+ socInfo = Dss_getSocInfo();
+ vpRegs = socInfo->vpRegs[vpId];
+ GT_assert(DssTrace, (NULL != vpRegs));
+
+ /* Call CSL APIs */
+ retVal = CSL_dssVpSetLcdBlankTiming(
+ vpRegs,
+ lcdBlankTimingCfg,
+ timingParams->dvoFormat,
+ scanFormat,
+ TRUE);
+ }
+
+ if(FVID2_SOK != retVal)
+ {
+ GT_0trace(DssTrace, GT_ERR, "Set LCD blank timing IOCTL failed\r\n");
+ }
+
+ /* Post the instance semaphore */
+ (void) SemaphoreP_post(instObj->lockSem);
+
+ return retVal;
+}
+
+static int32_t Dss_dctrlDrvSetVpSafetyChkParamsIoctl(
+ Dss_DctrlDrvInstObj *instObj,
+ const Dss_DctrlVpSafetyChkParams *safetyChkParams)
+{
+ int32_t retVal = FVID2_SOK;
+ uint32_t vpId, regionId, eventGroup, numHandle, evtMgrId, safetyEvt;
+ Dss_DctrlDrvCommonObj *pObj;
+ CSL_dss_vpRegs *vpRegs;
+ const Dss_SocInfo *socInfo;
+ const CSL_DssSafetyChkCfg *safetyChkCfg;
+
+ /* Check for NULL pointers */
+ GT_assert(DssTrace, (NULL != instObj));
+ GT_assert(DssTrace, (NULL != safetyChkParams));
+
+ /* Assign inputs */
+ pObj = &gDss_DctrlDrvCommonObj;
+ vpId = safetyChkParams->vpId;
+ regionId = safetyChkParams->regionSafetyChkCfg.regionId;
+ /* Check for wrong inputs */
+ if((vpId >= CSL_DSS_VP_ID_MAX)||(regionId >= CSL_DSS_VP_SAFETY_REGION_MAX))
+ {
+ GT_0trace(DssTrace, GT_ERR, "Invalid argument!!\r\n");
+ retVal = FVID2_EBADARGS;
+ }
+ else
+ {
+ /* Get video port registers */
+ socInfo = Dss_getSocInfo();
+ vpRegs = socInfo->vpRegs[vpId];
+ GT_assert(DssTrace, (NULL != vpRegs));
+ }
+
+ /* Take the instance semaphore */
+ (void) SemaphoreP_pend(instObj->lockSem, SemaphoreP_WAIT_FOREVER);
+
+ if(FVID2_SOK == retVal)
+ {
+ Fvid2Utils_memcpy(
+ &gDss_DctrlDrvInfo.safetyChkParams[regionId][vpId],
+ safetyChkParams,
+ sizeof (Dss_DctrlVpSafetyChkParams));
+
+ /* Register for Safety Error Events */
+ Dss_convModuletoEventGroup(&eventGroup,
+ vpId,
+ DSS_EVENT_GROUP_TYPE_VP);
+ GT_assert(DssTrace, (DSS_EVENT_GROUP_INVALID != eventGroup));
+ numHandle = pObj->instObj->numRegEvtHandle;
+ evtMgrId = Dss_getEvtMgrSafetyIntrId();
+ safetyEvt = Dss_dctrlGetVpSafetyEvtId(regionId);
+ GT_assert(DssTrace, (DSS_VP_EVENT_INVALID != safetyEvt));
+ pObj->instObj->evtGroupHandle[pObj->instObj->numRegEvtHandle] =
+ Dss_evtMgrRegister(
+ evtMgrId,
+ eventGroup,
+ (const uint32_t *)(&safetyEvt),
+ 1U,
+ Dss_dctrlSafetyErrCbFxn,
+ (void *)&gDss_DctrlEvtMgrClientInfo[numHandle]);
+ pObj->instObj->numRegEvtHandle++;
+
+ /* Call CSL APIs */
+ if(0U != safetyChkParams->safetySignSeedVal)
+ {
+ CSL_dssVpSetSafetySignSeedVal(vpRegs,
+ safetyChkParams->safetySignSeedVal);
+ }
+ if(CSL_DSS_SAFETY_CHK_DATA_INTEGRITY ==
+ safetyChkParams->regionSafetyChkCfg.safetyChkCfg.safetyChkMode)
+ {
+ CSL_dssVpSetSafetyReferenceSign(
+ vpRegs,
+ safetyChkParams->regionSafetyChkCfg.referenceSign,
+ regionId);
+ }
+ safetyChkCfg = &safetyChkParams->regionSafetyChkCfg.safetyChkCfg;
+ CSL_dssVpSetSafetyChkConfig(vpRegs, safetyChkCfg, regionId);
+ }
+
+ if(FVID2_SOK != retVal)
+ {
+ GT_0trace(DssTrace,
+ GT_ERR,
+ "Register Safety Error Cb Params IOCTL failed\r\n");
+ }
+
+ /* Post the instance semaphore */
+ (void) SemaphoreP_post(instObj->lockSem);
+
+ return retVal;
+}
+
+static int32_t Dss_dctrlDrvGetErrorStatsIoctl(
+ Dss_DctrlDrvInstObj *instObj,
+ Dss_DctrlVpErrorStats *vpErrStats)
+{
+ int32_t retVal = FVID2_SOK;
+ uint32_t i, vpFound = FALSE;
+
+ /* Check for NULL pointers */
+ GT_assert(DssTrace, (NULL != instObj));
+ GT_assert(DssTrace, (NULL != vpErrStats));
+
+ /* Check for wrong inputs */
+ if(vpErrStats->vpId >= CSL_DSS_VP_ID_MAX)
+ {
+ GT_0trace(DssTrace, GT_ERR, "Invalid argument!!\r\n");
+ retVal = FVID2_EBADARGS;
+ }
+
+ /* Take the instance semaphore */
+ (void) SemaphoreP_pend(instObj->lockSem, SemaphoreP_WAIT_FOREVER);
+
+ if(FVID2_SOK == retVal)
+ {
+ /* Check if Video Port is valid */
+ for(i=0U; i<CSL_DSS_VP_ID_MAX; i++)
+ {
+ if(gDss_DctrlDrvInfo.vpParams[i].vpId == vpErrStats->vpId)
+ {
+ vpFound = TRUE;
+ break;
+ }
+ }
+
+ if(TRUE == vpFound)
+ {
+ retVal = FVID2_SOK;
+ vpErrStats->syncLost =
+ gDss_DctrlDrvInfo.errorCnt.vpsyncLost[vpErrStats->vpId];
+ for(i=0U; i<CSL_DSS_VP_SAFETY_REGION_MAX; i++)
+ {
+ vpErrStats->safetyViolation[i] =
+ gDss_DctrlDrvInfo.errorCnt.vpSafetyViolation[i][vpErrStats->vpId];
+ }
+
+ vpErrStats->securityViolation =
+ gDss_DctrlDrvInfo.errorCnt.vpSecurityViolation[vpErrStats->vpId];
+ }
+ }
+
+ if(FVID2_SOK != retVal)
+ {
+ GT_0trace(DssTrace, GT_ERR, "GET VP error stat IOCTL failed\r\n");
+ }
+
+ /* Post the instance semaphore */
+ (void) SemaphoreP_post(instObj->lockSem);
+
+ return retVal;
+}
+
+static int32_t Dss_dctrlDrvSetGlobalDssParamsIoctl(
+ Dss_DctrlDrvInstObj *instObj,
+ const Dss_DctrlGlobalDssParams *globalDssParams)
+{
+ int32_t retVal = FVID2_SOK;
+ CSL_dss_commRegs *commRegs;
+ const Dss_SocInfo *socInfo;
+ const CSL_DssGlobalMFlagCfg *globalMflagCfg;
+ const CSL_DssCbaCfg *cbaCfg;
+
+ /* Check for NULL pointers */
+ GT_assert(DssTrace, (NULL != instObj));
+ GT_assert(DssTrace, (NULL != globalDssParams));
+
+ /* Take the instance semaphore */
+ (void) SemaphoreP_pend(instObj->lockSem, SemaphoreP_WAIT_FOREVER);
+
+ /* Get common registers */
+ socInfo = Dss_getSocInfo();
+ commRegs = socInfo->commRegs[CSL_DSS_COMM_REG_ID_0];
+ GT_assert(DssTrace, (NULL != commRegs));
+
+ /* Assign input parameters */
+ globalMflagCfg = &globalDssParams->globalMflagCfg;
+ cbaCfg = &globalDssParams->cbaCfg;
+
+ /* Call CSL APIs */
+ if(FVID2_SOK == retVal)
+ {
+ CSL_dssSetGlobalMflagConfig(commRegs, globalMflagCfg);
+ CSL_dssSetCbaConfig(commRegs, cbaCfg);
+ }
+
+ if(FVID2_SOK != retVal)
+ {
+ GT_0trace(DssTrace, GT_ERR, "Set global parameters IOCTL failed\r\n");
+ }
+
+ /* Post the instance semaphore */
+ (void) SemaphoreP_post(instObj->lockSem);
+
+ return retVal;
+}
+
+#if defined (SOC_AM65XX)
+static int32_t Dss_dctrlDrvSetOldiParamsIoctl(
+ Dss_DctrlDrvInstObj *instObj,
+ const Dss_DctrlOldiParams *oldiParams)
+{
+ int32_t retVal = FVID2_SOK;
+ uint32_t resetOldi = FALSE;
+ CSL_dss_commRegs *commRegs;
+ CSL_dss_vpRegs *vpRegs;
+ const Dss_SocInfo *socInfo;
+ const CSL_DssVpOldiCfg *oldiCfg;
+
+ /* Check for NULL pointers */
+ GT_assert(DssTrace, (NULL != instObj));
+ GT_assert(DssTrace, (NULL != oldiParams));
+
+ /* Take the instance semaphore */
+ (void) SemaphoreP_pend(instObj->lockSem, SemaphoreP_WAIT_FOREVER);
+
+ /* Get video port registers */
+ socInfo = Dss_getSocInfo();
+ vpRegs = socInfo->vpRegs[oldiParams->vpId];
+ GT_assert(DssTrace, (NULL != vpRegs));
+
+ /* Get common registers */
+ commRegs = socInfo->commRegs[CSL_DSS_COMM_REG_ID_0];
+ GT_assert(DssTrace, (NULL != commRegs));
+
+ /* Assign input parameters */
+ oldiCfg = &oldiParams->oldiCfg;
+
+ /* Call CSL APIs */
+ CSL_dssVpOldiReset(vpRegs);
+ do
+ {
+ resetOldi = CSL_dssIsOldiResetDone(commRegs);
+ } while (TRUE != resetOldi);
+
+ CSL_dssVpSetOldiConfig(vpRegs, oldiCfg);
+ CSL_dssVpOldiEnable(vpRegs, TRUE);
+
+ if(FVID2_SOK != retVal)
+ {
+ GT_0trace(DssTrace, GT_ERR, "Set OLDI parameters IOCTL failed\r\n");
+ }
+
+ /* Post the instance semaphore */
+ (void) SemaphoreP_post(instObj->lockSem);
+
+ return retVal;
+}
+#endif
+
+static int32_t Dss_dctrlDrvStopVpIoctl(Dss_DctrlDrvInstObj *instObj,
+ const Dss_DctrlVpParams *vpParams)
+{
+ int32_t retVal = FVID2_SOK;
+ uint32_t i, vpId, syncVpId;
+ uint32_t vpFound = FALSE;
+ uint32_t cookie;
+ Dss_DctrlVpParams *sVpParams = NULL;
+
+ /* Check for NULL pointers */
+ GT_assert(DssTrace, (NULL != instObj));
+ GT_assert(DssTrace, (NULL != vpParams));
+ GT_assert(DssTrace, (vpParams->vpId < CSL_DSS_VP_ID_MAX));
+
+ vpId = vpParams->vpId;
+ sVpParams = &gDss_DctrlDrvInfo.vpParams[vpId];
+
+ /* Check for wrong inputs */
+ if(vpParams->vpId >= CSL_DSS_VP_ID_MAX)
+ {
+ GT_0trace(DssTrace, GT_ERR, "Invalid argument!!\r\n");
+ retVal = FVID2_EBADARGS;
+ }
+
+ /* Take the instance semaphore */
+ (void) SemaphoreP_pend(instObj->lockSem, SemaphoreP_WAIT_FOREVER);
+
+ if(FVID2_SOK == retVal)
+ {
+ if((DSS_DCTRL_VP_RUNNING != gDss_DctrlDrvInfo.vpState[vpId]) &&
+ (DSS_DCTRL_VP_STARTING != gDss_DctrlDrvInfo.vpState[vpId]))
+ {
+ GT_0trace(DssTrace, GT_ERR, "VP not started!!\r\n");
+ retVal = FVID2_EBADARGS;
+ }
+ }
+
+ if((FVID2_SOK == retVal) &&
+ (TRUE == sVpParams->syncOpCfg.enabled) &&
+ (TRUE == sVpParams->syncOpCfg.isPrimary))
+ {
+ for(i = 0; i < sVpParams->syncOpCfg.numSyncVpIds; i++)
+ {
+ syncVpId = sVpParams->syncOpCfg.syncVpIds[i];
+
+ if(DSS_DCTRL_VP_STOPPING != gDss_DctrlDrvInfo.vpState[syncVpId])
+ {
+ vpFound = TRUE;
+ }
+ }
+
+ if(TRUE == vpFound)
+ {
+ GT_0trace(DssTrace, GT_ERR, "Secondary sync VPs not stopped!!\r\n");
+ retVal = FVID2_EBADARGS;
+ }
+ }
+
+#if defined (SOC_J721E)
+ if((FVID2_SOK == retVal) && (TRUE == Dss_dctrlDrvIsOutputDP(vpId)))
+ {
+ retVal = Dss_dctrlDrvDisableVideoDP();
+ }
+#endif
+
+ if(FVID2_SOK == retVal)
+ {
+ cookie = HwiP_disable();
+ Dss_dctrlVpEnable(vpId, FALSE);
+ HwiP_restore(cookie);
+
+ Dss_dctrlVpReset(vpId);
+
+ if((TRUE == sVpParams->syncOpCfg.enabled) &&
+ (TRUE == sVpParams->syncOpCfg.isPrimary))
+ {
+ for(i = 0; i < sVpParams->syncOpCfg.numSyncVpIds; i++)
+ {
+ syncVpId = sVpParams->syncOpCfg.syncVpIds[i];
+ Dss_dctrlVpReset(syncVpId);
+ }
+ }
+ }
+
+ if(FVID2_SOK != retVal)
+ {
+ GT_0trace(DssTrace, GT_ERR, "Stop VP IOCTL failed\r\n");
+ }
+
+ /* Post the instance semaphore */
+ (void) SemaphoreP_post(instObj->lockSem);
+
+ return retVal;
+}
+
+static int32_t Dss_dctrlDrvSetSyncLostCbParamsIoctl(
+ Dss_DctrlDrvInstObj *instObj,
+ const Dss_DctrlSyncLostCbParams *syncLostCbParams)
+{
+ int32_t retVal = FVID2_SOK;
+ uint32_t vpId;
+
+ /* Check for NULL pointers */
+ GT_assert(DssTrace, (NULL != instObj));
+ GT_assert(DssTrace, (NULL != syncLostCbParams));
+
+ /* Check for wrong inputs */
+ if(syncLostCbParams->vpId >= CSL_DSS_VP_ID_MAX)
+ {
+ GT_0trace(DssTrace, GT_ERR, "Invalid argument!!\r\n");
+ retVal = FVID2_EBADARGS;
+ }
+
+ /* Take the instance semaphore */
+ (void) SemaphoreP_pend(instObj->lockSem, SemaphoreP_WAIT_FOREVER);
+
+ if(FVID2_SOK == retVal)
+ {
+ vpId = syncLostCbParams->vpId;
+ Fvid2Utils_memcpy(&gDss_DctrlDrvInfo.syncLostCbParams[vpId],
+ syncLostCbParams,
+ sizeof (Dss_DctrlSyncLostCbParams));
+ }
+
+ if(FVID2_SOK != retVal)
+ {
+ GT_0trace(DssTrace,
+ GT_ERR,
+ "Register Sync Lost Cb Params IOCTL failed\r\n");
+ }
+
+ /* Post the instance semaphore */
+ (void) SemaphoreP_post(instObj->lockSem);
+
+ return retVal;
+}
+
+static int32_t Dss_dctrlDrvSetLineNumCbParamsIoctl(
+ Dss_DctrlDrvInstObj *instObj,
+ const Dss_DctrlLineNumCbParams *lineNumCbParams)
+{
+ int32_t retVal = FVID2_SOK;
+ uint32_t vpId = lineNumCbParams->vpId;
+
+ /* Check for NULL pointers */
+ GT_assert(DssTrace, (NULL != instObj));
+ GT_assert(DssTrace, (NULL != lineNumCbParams));
+
+ /* Check for wrong inputs */
+ if(vpId >= CSL_DSS_VP_ID_MAX)
+ {
+ GT_0trace(DssTrace, GT_ERR, "Invalid argument!!\r\n");
+ retVal = FVID2_EBADARGS;
+ }
+
+ /* Take the instance semaphore */
+ (void) SemaphoreP_pend(instObj->lockSem, SemaphoreP_WAIT_FOREVER);
+
+ if(FVID2_SOK == retVal)
+ {
+ Fvid2Utils_memcpy(&gDss_DctrlDrvInfo.lineNumCbParams[vpId],
+ lineNumCbParams,
+ sizeof (Dss_DctrlLineNumCbParams));
+ }
+
+ if(FVID2_SOK != retVal)
+ {
+ GT_0trace(DssTrace,
+ GT_ERR,
+ "Register Line Num Cb Params IOCTL failed\r\n");
+ }
+
+ /* Post the instance semaphore */
+ (void) SemaphoreP_post(instObj->lockSem);
+
+ return retVal;
+}
+
+static void Dss_dctrlFuncCbFxn(const uint32_t *event,
+ uint32_t numEvents,
+ void *arg)
+{
+ uint32_t i, j, currEvent, vpId = 0U, activePipeNum;
+ Dss_EvtMgrClientInfo *pClientObj = (Dss_EvtMgrClientInfo *)arg;
+
+ GT_assert(DssTrace,
+ (gDss_DctrlDrvInfo.numValidPipes <= CSL_DSS_VID_PIPE_ID_MAX));
+
+ uint32_t eventGroup = pClientObj->eventGroup;
+ Dss_convEventGrouptoModule(eventGroup, &vpId);
+ GT_assert(DssTrace, (CSL_DSS_MODULE_INVALID != vpId));
+
+ for(i=0U; i<numEvents; i++)
+ {
+ currEvent = event[i];
+ if(DSS_VP_EVENT_LINE_NUM == currEvent)
+ {
+ gDss_DctrlDrvInfo.isPushSafe[vpId] = FALSE;
+ if(NULL != gDss_DctrlDrvInfo.lineNumCbParams[vpId].lineNumCbFxn)
+ {
+ gDss_DctrlDrvInfo.lineNumCbParams[vpId].lineNumCbFxn(
+ vpId,
+ gDss_DctrlDrvInfo.lineNumCbParams[vpId].appData);
+ }
+ }
+ else if(DSS_VP_EVENT_VSYNC == currEvent)
+ {
+ activePipeNum = 0U;
+ for(j=0U; j<gDss_DctrlDrvInfo.numValidPipes; j++)
+ {
+ if(gDss_DctrlDrvInfo.pipeInfo[j].vpId == vpId)
+ {
+ if((gDss_DctrlDrvInfo.pipeInfo[j].pipeState ==
+ DSS_DCTRL_PIPE_STARTING) ||
+ (gDss_DctrlDrvInfo.pipeInfo[j].pipeState ==
+ DSS_DCTRL_PIPE_STARTED) ||
+ (gDss_DctrlDrvInfo.pipeInfo[j].pipeState ==
+ DSS_DCTRL_PIPE_RUNNING) ||
+ (gDss_DctrlDrvInfo.pipeInfo[j].pipeState ==
+ DSS_DCTRL_PIPE_STOPPING))
+ {
+ activePipeNum++;
+ if(gDss_DctrlDrvInfo.pipeInfo[j].pipeState ==
+ DSS_DCTRL_PIPE_STARTING)
+ {
+ /* This is the first VSync for dummy start i.e.
+ * either start is synchronous or start was called
+ * close to VSYNC */
+ gDss_DctrlDrvInfo.pipeInfo[j].pipeState =
+ DSS_DCTRL_PIPE_STARTED;
+ }
+ if(gDss_DctrlDrvInfo.pipeInfo[j].pipeState ==
+ DSS_DCTRL_PIPE_STARTED)
+ {
+ /* This is the first actual VSync where the buffer
+ * B1's display has started */
+ gDss_DctrlDrvInfo.pipeInfo[j].pipeState =
+ DSS_DCTRL_PIPE_RUNNING;
+ }
+ if(gDss_DctrlDrvInfo.pipeInfo[j].pipeState ==
+ DSS_DCTRL_PIPE_STOPPING)
+ {
+ /* This is the VSYNC before synchronous stop */
+ gDss_DctrlDrvInfo.pipeInfo[j].pipeState =
+ DSS_DCTRL_PIPE_STOPPED;
+ }
+ gDss_DctrlDrvInfo.isPushSafe[vpId] = TRUE;
+ GT_assert(DssTrace,
+ (NULL !=
+ gDss_DctrlDrvInfo.pipeInfo[j].gClientInfo.cbFxn));
+ gDss_DctrlDrvInfo.pipeInfo[j].gClientInfo.cbFxn(
+ gDss_DctrlDrvInfo.pipeInfo[j].gClientInfo.arg);
+ }
+ else if(gDss_DctrlDrvInfo.pipeInfo[j].pipeState ==
+ DSS_DCTRL_PIPE_STOPPED)
+ {
+ /* This is the actual stop */
+ gDss_DctrlDrvInfo.pipeInfo[j].pipeState =
+ DSS_DCTRL_PIPE_OPENED;
+ (void) SemaphoreP_post(gDss_DctrlDrvInfo.pipeInfo[j].stopSem);
+ }
+ else {
+ /* To fix MISRAC issue - this is a valid else - do nothing */
+ }
+ }
+ }
+
+ if(activePipeNum > 0U)
+ {
+ Dss_dctrlVpSetGoBit(vpId);
+ }
+ }
+ else
+ {
+ GT_assert(DssTrace, FALSE);
+ }
+ }
+
+ return;
+}
+
+static void Dss_dctrlErrCbFxn(const uint32_t *event,
+ uint32_t numEvents,
+ void *arg)
+{
+ uint32_t i, currEvent, vpId = 0U;
+ Dss_EvtMgrClientInfo *pClientObj = (Dss_EvtMgrClientInfo *)arg;
+ uint32_t eventGroup = pClientObj->eventGroup;
+ Dss_DctrlDrvErrorCount *pErrorCnt;
+
+ pErrorCnt = &gDss_DctrlDrvInfo.errorCnt;
+ Dss_convEventGrouptoModule(eventGroup, &vpId);
+ GT_assert(DssTrace, (CSL_DSS_MODULE_INVALID != vpId));
+
+ for(i=0U; i<numEvents; i++)
+ {
+ currEvent = event[i];
+ if(DSS_VP_EVENT_SYNC_LOST == currEvent)
+ {
+ pErrorCnt->vpsyncLost[vpId]++;
+ if(NULL != gDss_DctrlDrvInfo.syncLostCbParams[vpId].syncLostCbFxn)
+ {
+ gDss_DctrlDrvInfo.syncLostCbParams[vpId].syncLostCbFxn(
+ vpId,
+ gDss_DctrlDrvInfo.syncLostCbParams[vpId].appData);
+ }
+ }
+ else
+ {
+ GT_assert(DssTrace, FALSE);
+ }
+ }
+
+ return;
+}
+
+static void Dss_dctrlSafetyErrCbFxn(const uint32_t *event,
+ uint32_t numEvents,
+ void *arg)
+{
+ uint32_t i, currEvent, vpId = 0U, regionId;
+ Dss_EvtMgrClientInfo *pClientObj = (Dss_EvtMgrClientInfo *)arg;
+ uint32_t eventGroup = pClientObj->eventGroup;
+ Dss_DctrlDrvErrorCount *pErrorCnt;
+ Dss_DctrlVpSafetyChkParams *pSafetyChkParams;
+ CSL_dss_vpRegs *vpRegs;
+ const Dss_SocInfo *socInfo;
+
+ pErrorCnt = &gDss_DctrlDrvInfo.errorCnt;
+ Dss_convEventGrouptoModule(eventGroup, &vpId);
+ GT_assert(DssTrace, (CSL_DSS_MODULE_INVALID != vpId));
+
+ /* Get video port registers */
+ socInfo = Dss_getSocInfo();
+ vpRegs = socInfo->vpRegs[vpId];
+ GT_assert(DssTrace, (NULL != vpRegs));
+
+ for(i=0U; i<numEvents; i++)
+ {
+ currEvent = event[i];
+ if(TRUE == Dss_dctrlIsSafetyEvent(currEvent))
+ {
+ regionId = Dss_dctrlGetVpSafetyRegionId(currEvent);
+ GT_assert(DssTrace, (CSL_DSS_VP_SAFETY_REGION_INVALID != regionId));
+ pErrorCnt->vpSafetyViolation[regionId][vpId]++;
+ pSafetyChkParams = &gDss_DctrlDrvInfo.safetyChkParams[regionId][vpId];
+ pSafetyChkParams->safetyCbData.regionId = regionId;
+ if(CSL_DSS_SAFETY_CHK_DATA_INTEGRITY ==
+ pSafetyChkParams->regionSafetyChkCfg.safetyChkCfg.safetyChkMode)
+ {
+ pSafetyChkParams->safetyCbData.capturedSign =
+ CSL_dssVpGetSafetySign(vpRegs, regionId);
+ }
+
+ if(NULL != pSafetyChkParams->safetyErrCbFxn)
+ {
+ pSafetyChkParams->safetyErrCbFxn(vpId,
+ pSafetyChkParams->safetyCbData,
+ pSafetyChkParams->appData);
+ }
+ }
+ else
+ {
+ GT_assert(DssTrace, FALSE);
+ }
+ }
+
+ return;
+}
+
+static int32_t Dss_dctrlConnectNodes(uint32_t inputNode, uint32_t outNode)
+{
+ int32_t retVal = FVID2_SOK;
+
+ if((FALSE == Dss_dctrlIsValidNode(inputNode)) ||
+ (FALSE == Dss_dctrlIsValidNode(outNode)))
+ {
+ retVal = FVID2_EBADARGS;
+ }
+
+ if(TRUE == Dss_dctrlIsVideoMuxNeeded(inputNode, outNode))
+ {
+ retVal = Dss_dctrlProgramVideoMux(inputNode,
+ outNode);
+ GT_assert(DssTrace, (FVID2_SOK == retVal));
+ }
+
+ return (retVal);
+}
+
+static void Dss_dctrlVpSetGoBit(uint32_t vpId)
+{
+ CSL_dss_vpRegs *vpRegs;
+ CSL_dss_commRegs *commRegs;
+ const Dss_SocInfo *socInfo;
+ const Dss_DctrlVpParams *vpParams;
+ uint32_t syncVpId;
+ uint32_t vpMask;
+ uint32_t i;
+
+ socInfo = Dss_getSocInfo();
+
+ /* Get video port registers */
+ vpRegs = socInfo->vpRegs[vpId];
+ GT_assert(DssTrace, (NULL != vpRegs));
+
+ /* Get DSS common_m / common_0 registers */
+ /* XXX if common_0/m is not enabled in rmInfo? */
+ commRegs = socInfo->commRegs[0U];
+ GT_assert(DssTrace, (NULL != commRegs));
+
+ vpParams = &gDss_DctrlDrvInfo.vpParams[vpId];
+
+ if(TRUE == vpParams->syncOpCfg.enabled)
+ {
+ if(TRUE == vpParams->syncOpCfg.isPrimary)
+ {
+ vpMask = (uint32_t)(1U << vpId);
+ for(i = 0U; i < vpParams->syncOpCfg.numSyncVpIds; i++)
+ {
+ syncVpId = vpParams->syncOpCfg.syncVpIds[i];
+ vpMask |= (uint32_t)(1U << syncVpId);
+ }
+
+ CSL_dssGlobalVpGoBitEnable(commRegs, vpMask);
+ }
+ }
+ else
+ {
+ CSL_dssVpSetGoBit(vpRegs);
+ }
+}
+
+static void Dss_dctrlVpReset(uint32_t vpId)
+{
+ CSL_dss_vpRegs *vpRegs;
+ const Dss_SocInfo *socInfo;
+ CSL_DssVpLcdSignalPolarityCfg lcdPolarityCfg;
+ CSL_DssVpLcdOpTimingCfg lcdOpTimingCfg;
+ CSL_DssVpLcdTdmCfg lcdTdmCfg;
+
+ socInfo = Dss_getSocInfo();
+
+ /* Get video port registers */
+ vpRegs = socInfo->vpRegs[vpId];
+ GT_assert(DssTrace, (NULL != vpRegs));
+
+ CSL_dssVpLcdTdmCfgInit(&lcdTdmCfg);
+ CSL_dssVpLcdSignalPolarityCfgInit(&lcdPolarityCfg);
+ CSL_dssVpLcdOpTimingCfgInit(&lcdOpTimingCfg);
+
+ CSL_dssVpSetLcdSignalPolarityConfig(
+ vpRegs,
+ (const CSL_DssVpLcdSignalPolarityCfg *)(&lcdPolarityCfg));
+ CSL_dssVpSetLcdTdmConfig(
+ vpRegs,
+ (const CSL_DssVpLcdTdmCfg *)(&lcdTdmCfg));
+
+ /* There is no point in checking the result here. We are resetting */
+ (void) CSL_dssVpSetLcdOpTimingConfig(vpRegs, &lcdOpTimingCfg);
+}
+
+static void Dss_dctrlVpEnable(uint32_t vpId, uint32_t enable)
+{
+ CSL_dss_vpRegs *vpRegs;
+ CSL_dss_commRegs *commRegs;
+ const Dss_SocInfo *socInfo;
+ const Dss_DctrlVpParams *vpParams;
+ uint32_t syncVpId;
+ uint32_t vpMask;
+ uint32_t i;
+
+ socInfo = Dss_getSocInfo();
+
+ /* Get video port registers */
+ vpRegs = socInfo->vpRegs[vpId];
+ GT_assert(DssTrace, (NULL != vpRegs));
+
+ /* Get DSS common_m / common_0 registers */
+ /* XXX if common_0/m is not enabled in rmInfo? */
+ commRegs = socInfo->commRegs[0U];
+ GT_assert(DssTrace, (NULL != commRegs));
+
+ vpParams = &gDss_DctrlDrvInfo.vpParams[vpId];
+
+ if(TRUE == vpParams->syncOpCfg.enabled)
+ {
+ if(TRUE == vpParams->syncOpCfg.isPrimary)
+ {
+ vpMask = (uint32_t)(1U << vpId);
+ for(i = 0U; i < vpParams->syncOpCfg.numSyncVpIds; i++)
+ {
+ syncVpId = vpParams->syncOpCfg.syncVpIds[i];
+ vpMask |= (uint32_t)(1U << syncVpId);
+ }
+
+ CSL_dssGlobalVpEnable(commRegs, vpMask, enable);
+
+ if(TRUE == enable)
+ {
+ gDss_DctrlDrvInfo.vpState[vpId] = DSS_DCTRL_VP_RUNNING;
+ }
+ else
+ {
+ gDss_DctrlDrvInfo.vpState[vpId] = DSS_DCTRL_VP_IDLE;
+ }
+
+ for(i = 0U; i < vpParams->syncOpCfg.numSyncVpIds; i++)
+ {
+ syncVpId = vpParams->syncOpCfg.syncVpIds[i];
+ if(TRUE == enable)
+ {
+ gDss_DctrlDrvInfo.vpState[syncVpId] = DSS_DCTRL_VP_RUNNING;
+ }
+ else
+ {
+ gDss_DctrlDrvInfo.vpState[syncVpId] = DSS_DCTRL_VP_IDLE;
+ }
+ }
+ }
+ else
+ {
+ if(TRUE == enable)
+ {
+ gDss_DctrlDrvInfo.vpState[vpId] = DSS_DCTRL_VP_STARTING;
+ }
+ else
+ {
+ gDss_DctrlDrvInfo.vpState[vpId] = DSS_DCTRL_VP_STOPPING;
+ }
+ }
+ }
+ else
+ {
+ CSL_dssVpEnable(vpRegs, enable);
+ if(TRUE == enable)
+ {
+ gDss_DctrlDrvInfo.vpState[vpId] = DSS_DCTRL_VP_RUNNING;
+ }
+ else
+ {
+ gDss_DctrlDrvInfo.vpState[vpId] = DSS_DCTRL_VP_IDLE;
+ }
+ }
+}
diff --git a/packages/ti/drv/dss/src/drv/dctrl/dss_dctrlDrv.h b/packages/ti/drv/dss/src/drv/dctrl/dss_dctrlDrv.h
--- /dev/null
@@ -0,0 +1,123 @@
+/*
+ * Copyright (c) Texas Instruments Incorporated 2018
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * \file dss_dctrlDrv.h
+ *
+ * \brief DSS Controller driver internal interface file.
+ */
+
+#ifndef DSS_DCTRLDRV_H_
+#define DSS_DCTRLDRV_H_
+
+/* ========================================================================== */
+/* Include Files */
+/* ========================================================================== */
+
+/* None */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* ========================================================================== */
+/* Macros & Typedefs */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/* Structure Declarations */
+/* ========================================================================== */
+
+/**
+ * \brief DSS Controller Driver initialization parameters.
+ */
+typedef struct
+{
+ uint32_t drvInstId;
+ /**< Driver Instance Id */
+ uint32_t numAvailablePorts;
+ /**< Number of video ports available to driver */
+ uint32_t availablePortId[CSL_DSS_VP_ID_MAX];
+ /**< Id of available video ports */
+#if defined(SOC_J721E)
+ Dss_DpInitParams dpInitParams;
+ /**< DP init parameters */
+#endif
+} Dss_DctrlDrvInitParams;
+
+/* ========================================================================== */
+/* Internal/Private Function Declarations */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/* Function Declarations */
+/* ========================================================================== */
+
+/**
+ * \brief DSS controller driver initialization function.
+ * This function gets called as a part of Dss_init(). It Initializes internal
+ * data structures and common system level resources related to display.
+ *
+ * \param drvInitParams Pointer to a #Dss_DctrlDrvInitParams structure
+ * containing the driver init configuration
+ *
+ * \return FVID2_SOK if successful, else suitable error code
+ */
+int32_t Dss_dctrlDrvInit(const Dss_DctrlDrvInitParams *drvInitParams);
+
+/**
+ * \brief DSS controller driver de-initialization function.
+ *
+ * This API free all resources allocated during Dss_dctrlDrvInit().
+ *
+ * \param None
+ *
+ * \return FVID2_SOK if successful, else suitable error code
+ */
+int32_t Dss_dctrlDrvDeInit(void);
+
+/* ========================================================================== */
+/* Static Function Definitions */
+/* ========================================================================== */
+
+/* None */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #ifndef DSS_DCTRLDRV_H_ */
diff --git a/packages/ti/drv/dss/src/drv/dctrl/dss_dctrlExtended.c b/packages/ti/drv/dss/src/drv/dctrl/dss_dctrlExtended.c
--- /dev/null
@@ -0,0 +1,833 @@
+/*
+ * Copyright (c) Texas Instruments Incorporated 2018
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * \file dss_dctrlExtended.c
+ *
+ * \brief File containing the DSS Controller APIs for extended peripherals
+ * like eDP, DSI.
+ *
+ */
+
+/* ========================================================================== */
+/* Include Files */
+/* ========================================================================== */
+
+#include <ti/drv/dss/dss.h>
+#include <ti/drv/dss/src/csl/dp/csl_dp.h>
+#include <ti/drv/dss/src/csl/dp_sd0801/csl_dp_sd0801.h>
+#include <ti/drv/dss/src/drv/common/dss_evtMgr.h>
+#include <ti/drv/dss/src/drv/dctrl/dss_dctrlDrv.h>
+#include <ti/drv/dss/src/drv/dctrl/dss_dctrlIntr.h>
+#include <ti/drv/dss/src/drv/dctrl/dss_dctrlPriv.h>
+#include <dss_soc_priv.h>
+
+/* ========================================================================== */
+/* Macros & Typedefs */
+/* ========================================================================== */
+
+typedef enum
+{
+ DP_VIDEO_STATE_IDLE = 0U,
+ DP_VIDEO_STATE_REQUESTED = 1U,
+ DP_VIDEO_STATE_RUNNING = 2U,
+} Dss_DctrlDisplayPortVideoState;
+
+#define DP_PRIVATE_DATA_SIZE (131072U)
+#define DP_PHY_PRIVATE_DATA_SIZE (1024U)
+#define DP_INTR (64U)
+#define ADDR_AFE (0x05050000)
+
+/* ========================================================================== */
+/* Structure Declarations */
+/* ========================================================================== */
+
+typedef struct
+{
+ uint32_t width;
+ uint32_t height;
+ uint32_t hfp;
+ uint32_t hsw;
+ uint32_t hbp;
+ uint32_t vfp;
+ uint32_t vsw;
+ uint32_t vbp;
+ uint32_t pclk;
+ uint32_t scanMode;
+ uint32_t hsyncPol;
+ uint32_t vsyncPol;
+} Dss_DctrlDisplayPortVideoMode;
+
+typedef struct
+{
+ DP_Config dpCfg;
+ DP_SD0801_Config dpPhyCfg;
+ DP_FirmwareImage dpFWImage;
+ DP_PrivateData *dpPrivData;
+ DP_SD0801_PrivateData *dpPhyPrivData;
+ DP_Callbacks dpCbInfo;
+ DP_UcpuClock dpClkInfo;
+ DP_SourceDeviceCapabilities srcCaps;
+ HwiP_Handle intrHandle;
+ uint32_t isConnected;
+ uint32_t hpdInProgress;
+ uint32_t hpdPending;
+ Dss_DctrlDisplayPortVideoState videoState;
+ Dss_DctrlDisplayPortVideoMode videoMode;
+ uint32_t isHpdSupported;
+ Dss_DctrlDpHpdCbFxn hpdCbFxn;
+ void *hpdCbData;
+} Dss_DctrlDisplayPortDrvObj;
+
+/* ========================================================================== */
+/* Function Declarations */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/* Global Variables */
+/* ========================================================================== */
+
+extern uint8_t gDctrlDpDram[DCTRL_DP_DMEM_SIZE];
+extern uint8_t gDctrlDpIram[DCTRL_DP_IMEM_SIZE];
+
+static uint8_t gDssDctrlDisplayPortDpPrivateData[DP_PRIVATE_DATA_SIZE];
+static uint8_t gDssDctrlDisplayPortDpPhyPrivateData[DP_PHY_PRIVATE_DATA_SIZE];
+
+static Dss_DctrlDisplayPortDrvObj gDssDctrlDisplayPortDrvObj;
+
+Fvid2_ModeInfo gDpStdModeInfo[] = {
+ {FVID2_STD_1080P_60, 1920, 1080, FVID2_SF_PROGRESSIVE, 148500, 60,
+ 88, 148, 44, 4, 36, 5}
+};
+
+/* ========================================================================== */
+/* Internal/Private Function Declarations */
+/* ========================================================================== */
+
+static int32_t Dss_dctrlDrvInitDPTX(uint32_t isHpdSupported);
+static void Dss_dctrlDrvDpIntr(uintptr_t arg);
+static int32_t Dss_dctrlDrvDpStartVideo(Dss_DctrlDisplayPortDrvObj *pObj);
+static int32_t Dss_dctrlDrvDpStopVideo(Dss_DctrlDisplayPortDrvObj *pObj);
+static int32_t Dss_dctrlDrvDetectDp(void);
+
+/* ========================================================================== */
+/* Function Definitions */
+/* ========================================================================== */
+
+int32_t Dss_dctrlDrvDisableVideoDP(void)
+{
+ int32_t retVal = FVID2_SOK;
+ uint32_t cookie;
+ Dss_DctrlDisplayPortDrvObj *pObj = &gDssDctrlDisplayPortDrvObj;
+
+ cookie = HwiP_disable();
+
+ /*
+ * We cannot be IDLE when this function is called.
+ * Valid states are REQUESTED || RUNNING
+ *
+ * If state == REQUESTED, HPD never happened, and we
+ * never went to RUNNING. So just go back to IDLE
+ *
+ * If state == RUNNING, we stop video and go to IDLE
+ *
+ * There is nothing we can do if stopVideo fails, so
+ * dont bother
+ */
+ if((DP_VIDEO_STATE_REQUESTED == pObj->videoState) ||
+ (DP_VIDEO_STATE_RUNNING == pObj->videoState))
+ {
+ if(DP_VIDEO_STATE_RUNNING == pObj->videoState)
+ {
+ Dss_dctrlDrvDpStopVideo(pObj);
+ }
+ pObj->videoState = DP_VIDEO_STATE_IDLE;
+ }
+
+ HwiP_restore(cookie);
+
+ return retVal;
+}
+
+int32_t Dss_dctrlDrvEnableVideoDP(const Fvid2_ModeInfo *mInfo,
+ uint32_t hsyncPolarity,
+ uint32_t vsyncPolarity)
+{
+ int32_t retVal = FVID2_SOK;
+ uint32_t cookie;
+ Dss_DctrlDisplayPortDrvObj *pObj = &gDssDctrlDisplayPortDrvObj;
+ uint32_t numStdModes, modeCnt;
+
+ if(FALSE == pObj->isHpdSupported)
+ {
+ retVal = Dss_dctrlDrvDetectDp();
+ }
+
+ cookie = HwiP_disable();
+
+ if((FVID2_SOK == retVal) &&
+ (FALSE == pObj->isHpdSupported))
+ {
+ pObj->isConnected = TRUE;
+ }
+
+ /*
+ * Copy the video mode parameters to be
+ * used by subsequent videoStart calls
+ *
+ * XXX bring in EDID support so that we can validate
+ * params passed by app, and when all parameters not
+ * provided, make a good guess whether to continue or not
+ */
+ if(FVID2_STD_CUSTOM != mInfo->standard)
+ {
+ numStdModes = sizeof (gDpStdModeInfo) / sizeof (Fvid2_ModeInfo);
+ for (modeCnt = 0U; modeCnt < numStdModes; modeCnt++)
+ {
+ if (mInfo->standard == gDpStdModeInfo[modeCnt].standard)
+ {
+ pObj->videoMode.width = gDpStdModeInfo[modeCnt].width;
+ pObj->videoMode.height = gDpStdModeInfo[modeCnt].height;
+ pObj->videoMode.hfp = gDpStdModeInfo[modeCnt].hFrontPorch;
+ pObj->videoMode.hsw = gDpStdModeInfo[modeCnt].hSyncLen;
+ pObj->videoMode.hbp = gDpStdModeInfo[modeCnt].hBackPorch;
+ pObj->videoMode.vfp = gDpStdModeInfo[modeCnt].vFrontPorch;
+ pObj->videoMode.vsw = gDpStdModeInfo[modeCnt].vSyncLen;
+ pObj->videoMode.vbp = gDpStdModeInfo[modeCnt].vBackPorch;
+ pObj->videoMode.pclk = gDpStdModeInfo[modeCnt].pixelClock;
+ pObj->videoMode.scanMode = gDpStdModeInfo[modeCnt].scanFormat;
+ break;
+ }
+ }
+ if (modeCnt == numStdModes)
+ {
+ retVal = FVID2_EFAIL;
+ }
+ }
+ else
+ {
+ pObj->videoMode.width = mInfo->width;
+ pObj->videoMode.height = mInfo->height;
+ pObj->videoMode.hfp = mInfo->hFrontPorch;
+ pObj->videoMode.hsw = mInfo->hSyncLen;
+ pObj->videoMode.hbp = mInfo->hBackPorch;
+ pObj->videoMode.vfp = mInfo->vFrontPorch;
+ pObj->videoMode.vsw = mInfo->vSyncLen;
+ pObj->videoMode.vbp = mInfo->vBackPorch;
+ pObj->videoMode.pclk = mInfo->pixelClock;
+ pObj->videoMode.scanMode = mInfo->scanFormat;
+ }
+
+ pObj->videoMode.hsyncPol = hsyncPolarity;
+ pObj->videoMode.vsyncPol = vsyncPolarity;
+
+ /*
+ * We are supposed to be IDLE when this function is called
+ *
+ * If HPD didnt happen yet, we set to REQUESTED, HDP will
+ * start video later if this flag is set, and then set us
+ * to RUNNING
+ *
+ * If HPD happend, and LT was successful, we start video
+ * and set to RUNNING
+ *
+ * If startVideo fails, we stay at REQUESTED. reason:
+ * startVideo can fail because the connected monitor
+ * does not support the timings provided. So we hope
+ * that when another monitor is connected, we are at
+ * REQUESTED, and HPD takes us to RUNNING
+ *
+ * XXX check the timings, match with EDID and print a trace
+ * accordingly
+ */
+ if((FVID2_SOK == retVal) &&
+ (DP_VIDEO_STATE_IDLE == pObj->videoState))
+ {
+ pObj->videoState = DP_VIDEO_STATE_REQUESTED;
+ if(TRUE == pObj->isConnected)
+ {
+ retVal = Dss_dctrlDrvDpStartVideo(pObj);
+ if(FVID2_SOK == retVal)
+ {
+ pObj->videoState = DP_VIDEO_STATE_RUNNING;
+ }
+ }
+ }
+
+ HwiP_restore(cookie);
+
+ return retVal;
+}
+
+int32_t Dss_dctrlDrvInitDp(uint32_t isHpdSupported)
+{
+ uint32_t retVal = FVID2_SOK;
+
+ /*
+ * XXX push this things to some CSL kind of functions
+ */
+
+ /* HPD Pin Mux */
+ CSL_REG32_WR(CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_PADCONFIG0 + 0x1c4, 0x00040005);
+
+ /* Select EDP PHY CLK source */
+ CSL_REG32_WR(CSL_CTRL_MMR0_CFG0_BASE + CSL_MAIN_CTRL_MMR_CFG0_EDP_PHY0_CLKSEL, 0x0);
+
+ /* Set DPTX_SRC_CFG, 0:vif0_en, 1:vif_1_en, 2:vif_2_en, 3: vif_3_en, 4: vif_0_sel, TBD */
+ CSL_REG32_WR(CSL_DSS_EDP0_INTG_CFG_VP_BASE + CSL_DPTX_DPTX_SRC_CFG, 0x1F);
+
+ /* WIZ PHY */
+ CSL_REG32_WR(ADDR_AFE + 0x408, 0x30000000);
+ CSL_REG32_WR(ADDR_AFE + 0x40c, 0x39000000);
+ CSL_REG32_WR(ADDR_AFE + 0x480, 0x70000000);
+ CSL_REG32_WR(ADDR_AFE + 0x4c0, 0x80000000);
+ CSL_REG32_WR(ADDR_AFE + 0x500, 0x80000000);
+ CSL_REG32_WR(ADDR_AFE + 0x540, 0x80000000);
+ CSL_REG32_WR(ADDR_AFE + 0x484, 0x10001 );
+ CSL_REG32_WR(ADDR_AFE + 0x4c4, 0x10001 );
+ CSL_REG32_WR(ADDR_AFE + 0x504, 0x10001 );
+ CSL_REG32_WR(ADDR_AFE + 0x544, 0x10001 );
+
+ retVal = Dss_dctrlDrvInitDPTX(isHpdSupported);
+
+ return retVal;
+}
+
+int32_t Dss_dctrlDrvRegisterHpdCb(const Dss_DctrlDpHpdCbParams *cbParams)
+{
+ int32_t retVal = FVID2_SOK;
+ uint32_t cookie;
+ Dss_DctrlDisplayPortDrvObj *pObj = &gDssDctrlDisplayPortDrvObj;
+
+ if(NULL == cbParams)
+ {
+ retVal = FVID2_EFAIL;
+ }
+
+ cookie = HwiP_disable();
+
+ if(FVID2_SOK == retVal)
+ {
+ pObj->hpdCbFxn = cbParams->hpdCbFxn;
+ pObj->hpdCbData = cbParams->appData;
+ }
+
+ if((NULL != pObj->hpdCbFxn) &&
+ (TRUE == pObj->hpdPending))
+ {
+ pObj->hpdPending = FALSE;
+ pObj->hpdInProgress = TRUE;
+ pObj->hpdCbFxn(TRUE, pObj->hpdCbData);
+ }
+
+ HwiP_restore(cookie);
+
+ return retVal;
+}
+
+int32_t Dss_dctrlDrvProcessHpdDp(uint32_t hpdState)
+{
+ uint32_t retVal = FVID2_SOK, dpApiRet;
+ uint32_t cookie;
+ uint32_t isConnected = FALSE;
+ Dss_DctrlDisplayPortDrvObj *pObj = &gDssDctrlDisplayPortDrvObj;
+ DP_TrainingStatus trainingResult;
+
+ if(TRUE == hpdState)
+ {
+ dpApiRet = DP_LinkTraining(pObj->dpPrivData, &trainingResult);
+ if ((CDN_EOK == dpApiRet) &&
+ (trainingResult == DP_LT_OK))
+ {
+ isConnected = TRUE;
+ }
+ }
+
+ /*
+ * It is a little bit of unknown ATM whether all these
+ * MBOX transactions to enable DP video takes sufficiently
+ * insignificant time so that they can be safely called
+ * inside a HWI disable/restore block.
+ *
+ * Keep them as is for the time being. We will see if
+ * anyone comes back reporting issues!
+ */
+ cookie = HwiP_disable();
+ pObj->isConnected = isConnected;
+
+ /*
+ * If we just connected, check if REQUESTED or RUNNING
+ *
+ * If RUNNING, then start video
+ * If startVideo fails, go back to REQUESTED, so that we
+ * do not do anything unexpected when stopVideo is called
+ *
+ * If REQUESTED, then start video, and if it passes,
+ * set to RUNNING
+ *
+ * If we just disconnected, and we were previously RUNNING,
+ * we set to REQUESTED and stop video
+ */
+ if(TRUE == pObj->isConnected)
+ {
+ if((DP_VIDEO_STATE_REQUESTED == pObj->videoState) ||
+ (DP_VIDEO_STATE_RUNNING == pObj->videoState))
+ {
+ retVal = Dss_dctrlDrvDpStartVideo(pObj);
+ if(FVID2_SOK == retVal)
+ {
+ if(DP_VIDEO_STATE_REQUESTED == pObj->videoState)
+ {
+ pObj->videoState = DP_VIDEO_STATE_RUNNING;
+ }
+ }
+ else
+ {
+ if(DP_VIDEO_STATE_RUNNING == pObj->videoState)
+ {
+ pObj->videoState = DP_VIDEO_STATE_REQUESTED;
+ }
+ }
+ }
+ }
+ else
+ {
+ if(DP_VIDEO_STATE_RUNNING == pObj->videoState)
+ {
+ Dss_dctrlDrvDpStopVideo(pObj);
+ pObj->videoState = DP_VIDEO_STATE_REQUESTED;
+ }
+ }
+
+ pObj->hpdInProgress = FALSE;
+ HwiP_restore(cookie);
+
+ return retVal;
+}
+
+/* ========================================================================== */
+/* Static Function Definitions */
+/* ========================================================================== */
+
+static int32_t Dss_dctrlDrvDetectDp()
+{
+ int32_t retVal = FVID2_SOK, dpApiRet;
+ bool hpdState;
+ DP_TrainingStatus trainingResult;
+ Dss_DctrlDisplayPortDrvObj *pObj = &gDssDctrlDisplayPortDrvObj;
+
+ if(FVID2_SOK == retVal)
+ {
+ dpApiRet = DP_GetHpdStatus(pObj->dpPrivData, &hpdState);
+ if((CDN_EOK != dpApiRet) ||
+ (true != hpdState))
+ {
+ retVal = FVID2_EFAIL;
+ }
+ }
+
+ if(FVID2_SOK == retVal)
+ {
+ dpApiRet = DP_LinkTraining(pObj->dpPrivData, &trainingResult);
+ if ((CDN_EOK != dpApiRet) ||
+ (trainingResult != DP_LT_OK))
+ {
+ retVal = FVID2_EFAIL;
+ }
+ }
+
+ return retVal;
+}
+
+static void Dss_dctrlDrvDpIntr(uintptr_t arg)
+{
+ Dss_DctrlDisplayPortDrvObj *pObj = (Dss_DctrlDisplayPortDrvObj *)arg;
+ uint32_t evt;
+ uint32_t retVal;
+ uint8_t hpdEvents = 0u;
+
+ retVal = DP_GetEvent(pObj->dpPrivData, &evt);
+
+ if((CDN_EOK == retVal) &&
+ (0 != (evt & DP_TX_HPD_EVENT)))
+ {
+ retVal = DP_ReadHpdEvent(pObj->dpPrivData, &hpdEvents);
+ }
+
+ if((CDN_EOK == retVal) &&
+ (FALSE == pObj->hpdInProgress))
+ {
+
+ if((0U != (hpdEvents & DP_HPD_STATE)) &&
+ (0U != (hpdEvents & DP_HPD_TO_HIGH)))
+ {
+ if(NULL != pObj->hpdCbFxn)
+ {
+ pObj->hpdInProgress = TRUE;
+ pObj->hpdCbFxn(TRUE, pObj->hpdCbData);
+ }
+ else
+ {
+ pObj->hpdPending = TRUE;
+ }
+ }
+ else if((0U == (hpdEvents & DP_HPD_STATE)) &&
+ (0U != (hpdEvents & DP_HPD_TO_LOW)))
+ {
+ if(NULL != pObj->hpdCbFxn)
+ {
+ pObj->hpdInProgress = TRUE;
+ pObj->hpdCbFxn(FALSE, pObj->hpdCbData);
+ }
+ else
+ {
+ pObj->hpdPending = FALSE;
+ }
+ }
+ }
+}
+
+static int32_t Dss_dctrlDrvDpStopVideo(Dss_DctrlDisplayPortDrvObj *pObj)
+{
+ /* XXX framer off */
+ return FVID2_SOK;
+}
+
+static int32_t Dss_dctrlDrvDpStartVideo(Dss_DctrlDisplayPortDrvObj *pObj)
+{
+ int32_t retVal = FVID2_SOK;
+ int32_t dpApiRet = CDN_EOK;
+ DP_AudioVideoClkCfg clkCfg;
+ DP_VideoParameters videoParams;
+
+ clkCfg.videoClockEnable = true;
+ clkCfg.audioClockEnable = true;
+ clkCfg.pktDataClockEnable = true;
+
+ videoParams.bitsPerSubpixel = 8;
+ videoParams.pxEncFormat = DP_PXENC_PXL_RGB;
+ videoParams.stereoVidAttr = DP_STEREO_VIDEO_LEFT;
+ videoParams.btType = DP_BT_601;
+ videoParams.forceMiscIgnoreBit = false;
+ videoParams.alignment = DP_ALIGN_MSB;
+ videoParams.dscEnable = 0;
+
+ /* fill the ones the driver does not care about */
+ videoParams.vicParams.vic = 0U;
+ videoParams.vicParams.hFreq = 0.0;
+ videoParams.vicParams.vFreq = 0,0;
+ videoParams.vicParams.vicR = 0;
+ videoParams.vicParams.vicPR = 0;
+
+ /* and, now the actually important ones */
+ videoParams.vicParams.hActive = pObj->videoMode.width;
+ videoParams.vicParams.hSync = pObj->videoMode.hsw;
+ videoParams.vicParams.hFrontPorch = pObj->videoMode.hfp;
+ videoParams.vicParams.hBackPorch = pObj->videoMode.hbp;
+ videoParams.vicParams.hBlank = pObj->videoMode.hbp + pObj->videoMode.hfp + pObj->videoMode.hsw;
+ videoParams.vicParams.hTotal = videoParams.vicParams.hBlank + videoParams.vicParams.hActive;
+ videoParams.vicParams.vActive = pObj->videoMode.height;
+ videoParams.vicParams.vSync = pObj->videoMode.vsw;
+ videoParams.vicParams.vFrontPorch = pObj->videoMode.vfp;
+ videoParams.vicParams.vBackPorch = pObj->videoMode.vbp;
+ videoParams.vicParams.vBlank = pObj->videoMode.vbp + pObj->videoMode.vfp + pObj->videoMode.vsw;
+ videoParams.vicParams.vTotal = videoParams.vicParams.vBlank + videoParams.vicParams.vActive;
+ videoParams.vicParams.pxlFreq = pObj->videoMode.pclk / (float64_t)1000;
+ videoParams.vicParams.scanMode = ((FVID2_SF_PROGRESSIVE == pObj->videoMode.scanMode) ? DP_SM_PROGRESSIVE : DP_SM_INTERLACED);
+ videoParams.vicParams.hSyncPolarity = ((FVID2_POL_HIGH == pObj->videoMode.hsyncPol) ? DP_SP_ACTIVE_HIGH : DP_SP_ACTIVE_LOW);
+ videoParams.vicParams.vSyncPolarity = ((FVID2_POL_HIGH == pObj->videoMode.vsyncPol) ? DP_SP_ACTIVE_HIGH : DP_SP_ACTIVE_LOW);
+
+ if(CDN_EOK == dpApiRet)
+ {
+ dpApiRet = DP_SetVic(pObj->dpPrivData, 0, &videoParams);
+ if(CDN_EOK != dpApiRet)
+ {
+ GT_0trace(DssTrace, GT_ERR, "error : DP_SetVic\r\n");
+ retVal = FVID2_EFAIL;
+ }
+ }
+
+ if(CDN_EOK == dpApiRet)
+ {
+ dpApiRet = DP_SetAudioVideoClkCfg(pObj->dpPrivData, 0, &clkCfg);
+ if(CDN_EOK != dpApiRet)
+ {
+ GT_0trace(DssTrace, GT_ERR, "error : DP_SetAudioVideoClkCfg\r\n");
+ retVal = FVID2_EFAIL;
+ }
+ }
+
+ if(CDN_EOK == dpApiRet)
+ {
+ dpApiRet = DP_SetFramerEnable(pObj->dpPrivData, true);
+ if(CDN_EOK != dpApiRet)
+ {
+ GT_0trace(DssTrace, GT_ERR, "error : DP_SetFramerEnable\r\n");
+ retVal = FVID2_EFAIL;
+ }
+ }
+
+ if(CDN_EOK == dpApiRet)
+ {
+ dpApiRet = DP_SetVideoSst(pObj->dpPrivData, true);
+ if(CDN_EOK != dpApiRet)
+ {
+ GT_0trace(DssTrace, GT_ERR, "error : DP_SetVideoSst\r\n");
+ retVal = FVID2_EFAIL;
+ }
+ }
+
+ return retVal;
+}
+
+static int32_t Dss_dctrlDrvInitDPTX(uint32_t isHpdSupported)
+{
+ Dss_DctrlDisplayPortDrvObj *pObj;
+ uint32_t memReqDp, memReqDpPhy;
+ HwiP_Params hwiParams;
+ uint32_t dpApiRet;
+ int32_t retVal = FVID2_SOK;
+
+ pObj = &gDssDctrlDisplayPortDrvObj;
+
+ pObj->dpCfg.regBase = (struct MHDP_ApbRegs_s *)CSL_DSS_EDP0_V2A_CORE_VP_REGS_APB_BASE;
+ pObj->dpCfg.regBaseSapb = (struct MHDP_ApbRegs_s *)CSL_DSS_EDP0_V2A_S_CORE_VP_REGS_SAPB_BASE;
+
+ pObj->dpPhyCfg.regBase = (uint32_t*)CSL_SERDES_10G0_BASE;
+ pObj->dpPhyCfg.regBaseDp = (struct DP_Regs_s *)CSL_DSS_EDP0_V2A_CORE_VP_REGS_APB_BASE;
+
+ pObj->dpFWImage.iMem = gDctrlDpIram;
+ pObj->dpFWImage.iMemSize = DCTRL_DP_IMEM_SIZE;
+ pObj->dpFWImage.dMem = gDctrlDpDram;
+ pObj->dpFWImage.dMemSize = DCTRL_DP_DMEM_SIZE;
+
+ pObj->dpCbInfo.event = NULL;
+ pObj->dpClkInfo.mhz = 125;
+
+ pObj->srcCaps.maxLinkRate = DP_LINK_RATE_8_10;
+ pObj->srcCaps.laneCount = 4;
+ pObj->srcCaps.ssc = false;
+ pObj->srcCaps.scramblerDisable = false;
+ pObj->srcCaps.tps3 = true;
+ pObj->srcCaps.tps4 = true;
+ pObj->srcCaps.fastLinkTraining = false;
+ pObj->srcCaps.maxVoltageSwing = 3;
+ pObj->srcCaps.maxPreemphasis = 3;
+ pObj->srcCaps.forceVoltageSwing = false;
+ pObj->srcCaps.forcePreemphasis = false;
+ pObj->srcCaps.laneMapping = DP_LANE_MAPPING_SINGLE_REGULAR;
+ pObj->srcCaps.controllersPerPhy = DP_SINGLE_CONTROLLER;
+
+ pObj->isConnected = FALSE;
+ pObj->videoState = DP_VIDEO_STATE_IDLE;
+
+ pObj->isHpdSupported = isHpdSupported;
+
+ pObj->hpdPending = FALSE;
+ pObj->hpdInProgress = FALSE;
+
+ if(FVID2_SOK == retVal)
+ {
+ dpApiRet = DP_Probe(&pObj->dpCfg, &memReqDp);
+ if((CDN_EOK != dpApiRet) ||
+ (memReqDp > DP_PRIVATE_DATA_SIZE))
+ {
+ GT_0trace(DssTrace, GT_ERR, "error : DP_Probe\r\n");
+ retVal = FVID2_EFAIL;
+ }
+ }
+
+ if(FVID2_SOK == retVal)
+ {
+ dpApiRet = DP_SD0801_Probe(&pObj->dpPhyCfg, &memReqDpPhy);
+ if ((CDN_EOK != dpApiRet) ||
+ (memReqDpPhy > DP_PHY_PRIVATE_DATA_SIZE))
+ {
+ GT_0trace(DssTrace, GT_ERR, "error : DP_SD0801_Probe\r\n");
+ retVal = FVID2_EFAIL;
+ }
+ }
+
+ if(FVID2_SOK == retVal)
+ {
+ pObj->dpPrivData = (DP_PrivateData *)(&gDssDctrlDisplayPortDpPrivateData[0]);
+ pObj->dpPhyPrivData = (DP_SD0801_PrivateData *)(&gDssDctrlDisplayPortDpPhyPrivateData[0]);
+
+ dpApiRet = DP_Init(pObj->dpPrivData, &pObj->dpCfg, &pObj->dpCbInfo);
+ if (CDN_EOK != dpApiRet)
+ {
+ GT_0trace(DssTrace, GT_ERR, "error : DP_Init\r\n");
+ retVal = FVID2_EFAIL;
+ }
+ }
+
+ if(FVID2_SOK == retVal)
+ {
+ dpApiRet = DP_SD0801_Init(pObj->dpPhyPrivData, &pObj->dpPhyCfg);
+ if (CDN_EOK != dpApiRet)
+ {
+ GT_0trace(DssTrace, GT_ERR, "error : DP_SD0801_Init\r\n");
+ retVal = FVID2_EFAIL;
+ }
+ }
+
+ if(FVID2_SOK == retVal)
+ {
+ dpApiRet = DP_SetPhyPd(pObj->dpPrivData, pObj->dpPhyPrivData);
+ if (CDN_EOK != dpApiRet)
+ {
+ GT_0trace(DssTrace, GT_ERR, "error : DP_SetPhyPd\r\n");
+ retVal = FVID2_EFAIL;
+ }
+ }
+
+ if(FVID2_SOK == retVal)
+ {
+ dpApiRet = DP_LoadFirmware(pObj->dpPrivData, &pObj->dpFWImage);
+ if (CDN_EOK != dpApiRet)
+ {
+ GT_0trace(DssTrace, GT_ERR, "error : DP_LoadFirmware\r\n");
+ retVal = FVID2_EFAIL;
+ }
+ }
+
+ if(FVID2_SOK == retVal)
+ {
+ dpApiRet = DP_SetClock(pObj->dpPrivData, &pObj->dpClkInfo);
+ if (CDN_EOK != dpApiRet)
+ {
+ GT_0trace(DssTrace, GT_ERR, "error : DP_SetClock\r\n");
+ retVal = FVID2_EFAIL;
+ }
+ }
+
+ if(FVID2_SOK == retVal)
+ {
+ dpApiRet = DP_StartUcpu(pObj->dpPrivData);
+ if(CDN_EOK != dpApiRet)
+ {
+ GT_0trace(DssTrace, GT_ERR, "error : DP_StartUcpu\r\n");
+ retVal = FVID2_EFAIL;
+ }
+ }
+
+ if(FVID2_SOK == retVal)
+ {
+ dpApiRet = DP_WaitAlive(pObj->dpPrivData);
+ if (CDN_EOK != dpApiRet)
+ {
+ GT_0trace(DssTrace, GT_ERR, "error : DP_WaitAlive\r\n");
+ retVal = FVID2_EFAIL;
+ }
+ }
+
+ if(FVID2_SOK == retVal)
+ {
+ uint8_t mainCtrlResp;
+
+ dpApiRet = DP_MainControl(pObj->dpPrivData, true, &mainCtrlResp);
+ if (CDN_EOK != dpApiRet)
+ {
+ GT_0trace(DssTrace, GT_ERR, "error : DP_MainControl\r\n");
+ retVal = FVID2_EFAIL;
+ }
+ }
+
+ if(FVID2_SOK == retVal)
+ {
+ dpApiRet = DP_ConfigurePhyAuxCtrl(pObj->dpPrivData);
+ if (CDN_EOK != dpApiRet)
+ {
+ GT_0trace(DssTrace, GT_ERR, "error : DP_ConfigurePhyAuxCtrl\r\n");
+ retVal = FVID2_EFAIL;
+ }
+ }
+
+ if(FVID2_SOK == retVal)
+ {
+ dpApiRet = DP_ConfigurePhyStartUp(pObj->dpPrivData,
+ pObj->srcCaps.laneCount,
+ pObj->srcCaps.maxLinkRate);
+ if(CDN_EOK != dpApiRet)
+ {
+ GT_0trace(DssTrace, GT_ERR, "error : DP_ConfigurePhyStartUp\r\n");
+ retVal = FVID2_EFAIL;
+ }
+ }
+
+ if(FVID2_SOK == retVal)
+ {
+ dpApiRet = DP_SetSourceCapabilities(pObj->dpPrivData, &pObj->srcCaps);
+ if (CDN_EOK != dpApiRet)
+ {
+ GT_0trace(DssTrace, GT_ERR, "error : DP_SetSourceCapabilities\r\n");
+ retVal = FVID2_EFAIL;
+ }
+ }
+
+ if((FVID2_SOK == retVal) &&
+ (TRUE == pObj->isHpdSupported))
+ {
+ dpApiRet = DP_Start(pObj->dpPrivData);
+ if(CDN_EOK != dpApiRet)
+ {
+ GT_0trace(DssTrace, GT_ERR, "error : DP_Start\r\n");
+ retVal = FVID2_EFAIL;
+ }
+ }
+
+ if((FVID2_SOK == retVal) &&
+ (TRUE == pObj->isHpdSupported))
+ {
+ HwiP_clearInterrupt(DP_INTR);
+
+ HwiP_Params_init(&hwiParams);
+ hwiParams.arg = (uintptr_t) pObj;
+
+ pObj->intrHandle = HwiP_create(DP_INTR,
+ &Dss_dctrlDrvDpIntr,
+ &hwiParams);
+
+ if(NULL == pObj->intrHandle)
+ {
+ GT_0trace(DssTrace,
+ GT_ERR,
+ "Cannot Register IRQ");
+ retVal = FVID2_EALLOC;
+ }
+ }
+
+ return retVal;
+}
diff --git a/packages/ti/drv/dss/src/drv/dctrl/dss_dctrlGraph.c b/packages/ti/drv/dss/src/drv/dctrl/dss_dctrlGraph.c
--- /dev/null
@@ -0,0 +1,206 @@
+/*
+ * Copyright (c) Texas Instruments Incorporated 2018
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * \file dss_dctrlGraph.c
+ *
+ * \brief File containing the DSS Controller graph APIs.
+ *
+ */
+
+/* ========================================================================== */
+/* Include Files */
+/* ========================================================================== */
+
+#include <ti/drv/dss/dss.h>
+#include <dss_soc_priv.h>
+#include <ti/drv/dss/include/dss_dctrl.h>
+#include <ti/drv/dss/src/drv/dctrl/dss_dctrlDrv.h>
+#include <ti/drv/dss/src/drv/dctrl/dss_dctrlPriv.h>
+
+/* ========================================================================== */
+/* Macros & Typedefs */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/* Structure Declarations */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/* Function Declarations */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/* Global Variables */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/* Internal/Private Function Declarations */
+/* ========================================================================== */
+
+static void Dss_dctrlDrvGraphInitInternal(
+ const Fvid2_GraphNodeList *nodeList,
+ const Fvid2_GraphEdgeList *edgeList,
+ Dss_DctrlDrvGraphObj *pDctrlDrvGraphObj);
+
+/* ========================================================================== */
+/* Function Definitions */
+/* ========================================================================== */
+
+void *Dss_dctrlDrvGraphInit(Dss_DctrlDrvGraphObj *newGraphObj)
+{
+ const Fvid2_GraphEdgeInfo *graphEdgeInfo;
+ const Fvid2_GraphNodeInfo *graphNodeInfo;
+ uint32_t graphEdgeInfoSize = 0U, graphNodeInfoSize = 0U;
+ if(NULL != newGraphObj)
+ {
+ /* Create default tree with all edges disabled
+ * This tree will handle resource management
+ */
+ graphEdgeInfo = Dss_dctrlGetDefaultEdgeInfo(&graphEdgeInfoSize);
+ graphNodeInfo = Dss_dctrlGetDefaultNodeInfo(&graphNodeInfoSize);
+
+ Fvid2Utils_memcpy(newGraphObj->allDctrlNodes,
+ graphNodeInfo,
+ graphNodeInfoSize);
+ newGraphObj->dctrlNodeList.numNodes = DSS_DCTRL_MAX_NODES;
+ newGraphObj->dctrlNodeList.list = newGraphObj->allDctrlNodes;
+
+ Fvid2Utils_memcpy(newGraphObj->allEdgeInfo,
+ graphEdgeInfo,
+ graphEdgeInfoSize);
+ newGraphObj->dctrlEdgeList.numEdges = DSS_DCTRL_MAX_EDGES;
+ newGraphObj->dctrlEdgeList.list = newGraphObj->allEdgeInfo;
+
+ Dss_dctrlDrvGraphInitInternal(&newGraphObj->dctrlNodeList,
+ &newGraphObj->dctrlEdgeList,
+ newGraphObj);
+ }
+ else
+ {
+ GT_0trace(DssTrace,
+ GT_ERR,
+ "Allocation of display graph failed \r\n");
+ }
+
+ return (void *) newGraphObj;
+}
+
+void Dss_dctrlDrvGraphDeInit(void *dssHandle)
+{
+ Dss_DctrlDrvGraphObj *pDctrlGraphObj = (Dss_DctrlDrvGraphObj *) dssHandle;
+
+ if(NULL != pDctrlGraphObj)
+ {
+ Fvid2_graphDeInit((Fvid2_GraphInfo *) pDctrlGraphObj->graph);
+ }
+}
+
+int32_t Dss_dctrlDrvCreateEdgeList(Dss_DctrlDrvGraphObj *graphObj,
+ const Dss_DctrlPathInfo *pathInfo)
+{
+ Fvid2_GraphEdgeList tmpEdgeList;
+ Dss_DctrlDrvGraphObj *pDctrlGraphObj = (Dss_DctrlDrvGraphObj *) graphObj;
+ Fvid2_GraphInfo *dctrlGraph = (Fvid2_GraphInfo *) (pDctrlGraphObj->graph);
+ int32_t retVal = FVID2_SOK;
+
+ tmpEdgeList.numEdges = pathInfo->numEdges;
+ tmpEdgeList.list = (Fvid2_GraphEdgeInfo *) &pathInfo->edgeInfo[0U];
+
+ /* Try to allocate nodes in the complete graph */
+ if(FVID2_SOK == Fvid2_graphAllocNodes(dctrlGraph->nodeList,
+ &tmpEdgeList,
+ FVID2_GRAPH_NODE_MODE_CHECK))
+ {
+ Fvid2_graphAllocNodes(dctrlGraph->nodeList,
+ &tmpEdgeList,
+ FVID2_GRAPH_NODE_MODE_ENABLE);
+
+ graphObj->dctrlNodeList.list = graphObj->dctrlNodeObj;
+ graphObj->dctrlEdgeList.list = graphObj->dctrlEdgeObj;
+ Fvid2_graphGetPath(dctrlGraph->nodeList,
+ &tmpEdgeList,
+ &graphObj->dctrlNodeList,
+ &graphObj->dctrlEdgeList,
+ sizeof (graphObj->dctrlNodeObj) /
+ sizeof (Fvid2_GraphNodeInfo),
+ sizeof (graphObj->dctrlEdgeObj) /
+ sizeof (Fvid2_GraphEdgeInfo));
+ }
+ else
+ {
+ Fvid2_graphAllocNodes(dctrlGraph->nodeList,
+ &tmpEdgeList,
+ FVID2_GRAPH_NODE_MODE_DISABLE);
+ retVal = FVID2_EFAIL;
+ }
+
+ return retVal;
+}
+
+void Dss_dctrlDrvFreeEdgeList(Dss_DctrlDrvGraphObj *graphObj)
+{
+ Dss_DctrlDrvGraphObj *pDctrlGraphObj = (Dss_DctrlDrvGraphObj *) graphObj;
+ Fvid2_GraphInfo *dctrlGraph = (Fvid2_GraphInfo *) (pDctrlGraphObj->graph);
+
+ Fvid2_graphAllocNodes(dctrlGraph->nodeList,
+ &(graphObj->dctrlEdgeList),
+ FVID2_GRAPH_NODE_MODE_DISABLE);
+
+ Fvid2_graphFreePath(&graphObj->dctrlNodeList, &graphObj->dctrlEdgeList);
+}
+
+/* ========================================================================== */
+/* Static Function Definitions */
+/* ========================================================================== */
+
+static void Dss_dctrlDrvGraphInitInternal(
+ const Fvid2_GraphNodeList *nodeList,
+ const Fvid2_GraphEdgeList *edgeList,
+ Dss_DctrlDrvGraphObj *pDctrlDrvGraphObj)
+{
+ pDctrlDrvGraphObj->graphObj.nodeList = &pDctrlDrvGraphObj->graphObjNodeList;
+ pDctrlDrvGraphObj->graphObj.edgeList = &pDctrlDrvGraphObj->graphObjEdgeList;
+ pDctrlDrvGraphObj->graph = &pDctrlDrvGraphObj->graphObj;
+ Fvid2_graphInit(nodeList,
+ edgeList,
+ (Fvid2_GraphInfo *) pDctrlDrvGraphObj->graph);
+}
diff --git a/packages/ti/drv/dss/src/drv/dctrl/dss_dctrlIntr.h b/packages/ti/drv/dss/src/drv/dctrl/dss_dctrlIntr.h
--- /dev/null
@@ -0,0 +1,180 @@
+/*
+ * Copyright (c) Texas Instruments Incorporated 2018
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * \file dss_dctrlIntr.h
+ *
+ * \brief DSS Controller driver internal interface file. These APIs are called
+ * by display driver
+ */
+
+#ifndef DSS_DCTRLINTR_H_
+#define DSS_DCTRLINTR_H_
+
+/* ========================================================================== */
+/* Include Files */
+/* ========================================================================== */
+
+/* None */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* ========================================================================== */
+/* Macros & Typedefs */
+/* ========================================================================== */
+
+/**
+ * \anchor Dss_DctrlPipeState
+ * \name Video Pipe State
+ *
+ * @{
+ */
+/** \brief Video Pipe is Idle */
+#define DSS_DCTRL_PIPE_IDLE ((uint32_t) 0U)
+/** \brief Video Pipe is opened by Display driver */
+#define DSS_DCTRL_PIPE_OPENED ((uint32_t) 1U)
+/** \brief Video Pipe is dummy started by Display driver */
+#define DSS_DCTRL_PIPE_STARTING ((uint32_t) 2U)
+/** \brief Video Pipe is started by Display driver */
+#define DSS_DCTRL_PIPE_STARTED ((uint32_t) 3U)
+/** \brief Video Pipe is running and first buffer is being displayed */
+#define DSS_DCTRL_PIPE_RUNNING ((uint32_t) 4U)
+/** \brief Video Pipe is dummy stopped by Display driver */
+#define DSS_DCTRL_PIPE_STOPPING ((uint32_t) 5U)
+/** \brief Video Pipe is stopped by Display driver */
+#define DSS_DCTRL_PIPE_STOPPED ((uint32_t) 6U)
+/* @} */
+
+/* Typedef for display controller client handle */
+typedef void *DssDctrlDrvClientHandle;
+
+/**
+ * \brief Client call back function
+ */
+typedef void (*Dss_dctrlDrvClientCbFxn)(void *arg);
+
+/* ========================================================================== */
+/* Structure Declarations */
+/* ========================================================================== */
+
+/**
+ * \brief Structure containing client information. All inputs are
+ * considered as clients to the display controller driver. Each client
+ * registers with the display controller driver by passing pointer to this
+ * structure.
+ */
+typedef struct
+{
+ Dss_dctrlDrvClientCbFxn cbFxn;
+ /**< Client call back function, which will be called by Display Controller
+ * to update buffer pointers */
+ void *arg;
+ /**< Private data of the client */
+} Dss_DctrlDrvClientInfo;
+
+/**
+ * \brief Display controller pipe object.
+ */
+typedef struct
+{
+ uint32_t pipeId;
+ /**< Video Pipe Id */
+ uint32_t pipeNodeId;
+ /**< Information of the pipe connected */
+ uint32_t pipeState;
+ /**< State of connected video pipe. Refer \ref Dss_DctrlPipeState for
+ * values */
+ uint32_t startX;
+ /**< X position of video buffer */
+ uint32_t startY;
+ /**< Y position of video buffer */
+ uint32_t overlayId;
+ /**< Overlay Id */
+ uint32_t overlayNodeId;
+ /**< Information of the overlay connected */
+ uint32_t vpId;
+ /**< Video port Id */
+ uint32_t vpNodeId;
+ /**< Information of the video port connected */
+ uint32_t outNodeId;
+ /**< Information of output node connected */
+ Dss_DctrlDrvClientInfo gClientInfo;
+ /**< DSS client call back function */
+ SemaphoreP_Handle stopSem;
+ /**< Semaphore to make FVID2 Stop as a blocking call */
+} Dss_DctrlDrvPipeInfo;
+
+/* ========================================================================== */
+/* Internal/Private Function Declarations */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/* Function Declarations */
+/* ========================================================================== */
+
+DssDctrlDrvClientHandle Dss_dctrlDrvRegisterClient(
+ uint32_t nodeId,
+ const Dss_DctrlDrvClientInfo *clientInfo);
+
+int32_t Dss_dctrlDrvUnRegisterClient(DssDctrlDrvClientHandle handle);
+
+int32_t Dss_dctrlDrvStartClient(DssDctrlDrvClientHandle handle,
+ uint32_t dummyStart);
+
+int32_t Dss_dctrlDrvStopClient(DssDctrlDrvClientHandle handle,
+ uint32_t syncStop);
+
+int32_t Dss_dctrlDrvGetVpParams(DssDctrlDrvClientHandle handle,
+ Dss_DctrlVpParams *vpParams);
+
+int32_t Dss_dctrlDrvSetGoBit(DssDctrlDrvClientHandle handle);
+
+uint32_t Dss_dctrlDrvIsSafeToPush(DssDctrlDrvClientHandle handle);
+
+Dss_DctrlDrvPipeInfo *Dss_dctrlDrvGetPipeInfo(DssDctrlDrvClientHandle handle);
+
+/* ========================================================================== */
+/* Static Function Definitions */
+/* ========================================================================== */
+
+/* None */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #ifndef DSS_DCTRLINTR_H_ */
diff --git a/packages/ti/drv/dss/src/drv/dctrl/dss_dctrlPriv.h b/packages/ti/drv/dss/src/drv/dctrl/dss_dctrlPriv.h
--- /dev/null
@@ -0,0 +1,232 @@
+/*
+ * Copyright (c) Texas Instruments Incorporated 2018
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * \file dss_dctrlPriv.h
+ *
+ * \brief DSS Controller driver private header file.
+ */
+
+#ifndef DSS_DCTRLPRIV_H_
+#define DSS_DCTRLPRIV_H_
+
+/* ========================================================================== */
+/* Include Files */
+/* ========================================================================== */
+
+#include <ti/drv/dss/dss.h>
+#include <ti/drv/dss/src/drv/dctrl/dss_dctrlIntr.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* ========================================================================== */
+/* Macros & Typedefs */
+/* ========================================================================== */
+
+/** @brief Enumeration for video port run states
+ *
+ * This is internally used for starting or stopping video ports
+ * synchronously
+ */
+typedef enum {
+ /** Secondary VP START command */
+ DSS_DCTRL_VP_STARTING = 0,
+ /** primary VP START command */
+ DSS_DCTRL_VP_RUNNING = 1,
+ /** secondary VP STOP command */
+ DSS_DCTRL_VP_STOPPING = 2,
+ /** primary VP STOP command */
+ DSS_DCTRL_VP_IDLE = 3,
+} Dss_DctrlVpState;
+
+/* ========================================================================== */
+/* Structure Declarations */
+/* ========================================================================== */
+
+/**
+ * \brief Different states of the controller driver.
+ */
+typedef struct
+{
+ uint32_t isInit;
+ /**< Flag to indicate initialization is done or not for an instance */
+ uint32_t isOpened;
+ /**< Flag to indicate whether the instance is opened or not */
+ uint32_t isStarted;
+ /**< Flag to indicate whether the display has started or not */
+} Dss_DctrlDrvState;
+
+/** \brief Forward declaration for instance object. */
+typedef struct Dss_DctrlDrvInstObj_t Dss_DctrlDrvInstObj;
+
+/**
+ * \brief Display controller driver common object.
+ */
+typedef struct
+{
+ Fvid2_DrvOps fvidDrvOps;
+ /**< FVID2 driver ops */
+ uint32_t isRegistered;
+ /**< FVID2 registration complete flag */
+ Dss_DctrlDrvInstObj *instObj;
+ /**< Display instance objects pointer */
+} Dss_DctrlDrvCommonObj;
+
+/**
+ * \brief Display controller instance information.
+ */
+struct Dss_DctrlDrvInstObj_t
+{
+ uint32_t drvInstId;
+ /**< Driver Instance ID */
+ Dss_DctrlDrvState drvState;
+ /**< Instance state */
+ uint32_t numOpenDrvHandle;
+ /**< Number of open handles to the driver */
+ uint32_t numRegEvtHandle;
+ /**< Number of registered event group handles */
+ void *evtGroupHandle[DSS_DCTRL_EVT_MGR_MAX_CLIENTS];
+ /**< Handle to registered event groups */
+ SemaphoreP_Handle lockSem;
+ /**< Semaphore to protect the open/close calls and other memory
+ * allocation per instance */
+};
+
+/**
+ * \brief Display controller graph object.
+ */
+typedef struct
+{
+ void *graph;
+ /**< Pointer to graph object */
+ Fvid2_GraphInfo graphObj;
+ /**< Graph object */
+ Fvid2_GraphNodeList graphObjNodeList;
+ /**< Graph object node list */
+ Fvid2_GraphEdgeList graphObjEdgeList;
+ /**< Graph object edge list */
+ Fvid2_GraphNodeList dctrlNodeList;
+ /**< Display controller node list */
+ Fvid2_GraphEdgeList dctrlEdgeList;
+ /**< Display controller edge list */
+ Fvid2_GraphNodeInfo dctrlNodeObj[DSS_DCTRL_MAX_NODES];
+ /**< Display controller node object list */
+ Fvid2_GraphEdgeInfo dctrlEdgeObj[DSS_DCTRL_MAX_EDGES];
+ /**< Display controller edge object list */
+ Fvid2_GraphNodeInfo allDctrlNodes[DSS_DCTRL_MAX_NODES];
+ /**< All display controller node list */
+ Fvid2_GraphEdgeInfo allEdgeInfo[DSS_DCTRL_MAX_EDGES];
+ /**< All display controller edge list */
+} Dss_DctrlDrvGraphObj;
+
+/**
+ * \brief Display controller driver error count.
+ */
+typedef struct
+{
+ uint32_t vpsyncLost[CSL_DSS_VP_ID_MAX];
+ /**< SyncLost error count for video Port */
+ uint32_t vpSafetyViolation[CSL_DSS_VP_SAFETY_REGION_MAX][CSL_DSS_VP_ID_MAX];
+ /**< Safety violation count for video Port */
+ uint32_t vpSecurityViolation[CSL_DSS_VP_ID_MAX];
+ /**< Security violation count for video Port */
+} Dss_DctrlDrvErrorCount;
+
+/**
+ * \brief Display controller driver information.
+ */
+typedef struct
+{
+ uint32_t numValidPipes;
+ /**< Number of valid video pipes */
+ Dss_DctrlDrvPipeInfo pipeInfo[CSL_DSS_VID_PIPE_ID_MAX];
+ /**< Information about the connected video pipe */
+ Dss_DctrlVpParams vpParams[CSL_DSS_VP_ID_MAX];
+ /**< Information about the Video Port */
+ Dss_DctrlVpState vpState[CSL_DSS_VP_ID_MAX];
+ /**< Flag to indicate whether Video Port is running or not. */
+ uint32_t isPushSafe[CSL_DSS_VP_ID_MAX];
+ /**< Flag to indicate if buffer push is safe */
+ Dss_DctrlSyncLostCbParams syncLostCbParams[CSL_DSS_VP_ID_MAX];
+ /**< Video port sync lost callback parameters */
+ Dss_DctrlLineNumCbParams lineNumCbParams[CSL_DSS_VP_ID_MAX];
+ /**< Video port line number callback parameters */
+ Dss_DctrlVpSafetyChkParams safetyChkParams[CSL_DSS_VP_SAFETY_REGION_MAX][CSL_DSS_VP_ID_MAX];
+ /**< Video port safety error callback parameters */
+ Dss_DctrlDrvErrorCount errorCnt;
+ /**< Display controller driver error count */
+} Dss_DctrlDrvInfo;
+
+/* ========================================================================== */
+/* Internal/Private Function Declarations */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/* Function Declarations */
+/* ========================================================================== */
+
+void *Dss_dctrlDrvGraphInit(Dss_DctrlDrvGraphObj *newGraphObj);
+
+void Dss_dctrlDrvGraphDeInit(void *dssHandle);
+
+int32_t Dss_dctrlDrvCreateEdgeList(Dss_DctrlDrvGraphObj *graphObj,
+ const Dss_DctrlPathInfo *pathInfo);
+
+void Dss_dctrlDrvFreeEdgeList(Dss_DctrlDrvGraphObj *graphObj);
+
+#if defined(SOC_J721E)
+int32_t Dss_dctrlDrvDisableVideoDP(void);
+int32_t Dss_dctrlDrvEnableVideoDP(const Fvid2_ModeInfo *mInfo,
+ uint32_t hsyncPolarity,
+ uint32_t vsyncPolarity);
+
+int32_t Dss_dctrlDrvInitDp(uint32_t isHpdSupported);
+int32_t Dss_dctrlDrvProcessHpdDp(uint32_t hpdState);
+int32_t Dss_dctrlDrvRegisterHpdCb(const Dss_DctrlDpHpdCbParams *cbParams);
+#endif
+
+/* ========================================================================== */
+/* Static Function Definitions */
+/* ========================================================================== */
+
+/* None */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #ifndef DSS_DCTRLPRIV_H_ */
diff --git a/packages/ti/drv/dss/src/drv/dctrl/src_files_dctrl.mk b/packages/ti/drv/dss/src/drv/dctrl/src_files_dctrl.mk
--- /dev/null
@@ -0,0 +1,5 @@
+SRCS_COMMON += dss_dctrlGraph.c dss_dctrlApi.c
+
+ifeq ($(SOC),$(filter $(SOC), j721e))
+SRCS_COMMON += dss_dctrlExtended.c
+endif
\ No newline at end of file
diff --git a/packages/ti/drv/dss/src/drv/disp/dss_dispApi.c b/packages/ti/drv/dss/src/drv/disp/dss_dispApi.c
--- /dev/null
@@ -0,0 +1,2137 @@
+/*
+ * Copyright (c) Texas Instruments Incorporated 2018
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * \file dss_dispApi.c
+ *
+ * \brief File containing the DSS display driver implementation.
+ *
+ */
+
+/* ========================================================================== */
+/* Include Files */
+/* ========================================================================== */
+
+#include <ti/drv/dss/dss.h>
+#include <ti/drv/dss/src/drv/common/dss_evtMgr.h>
+#include <ti/drv/dss/src/drv/disp/dss_dispDrv.h>
+#include <ti/drv/dss/src/drv/disp/dss_dispPriv.h>
+#include <dss_soc_priv.h>
+
+/* ========================================================================== */
+/* Macros & Typedefs */
+/* ========================================================================== */
+
+/* Number of lines for which time duration before VSYNC is considered to be too
+ * small for DSS operations to finish */
+#define DSS_DISP_NUM_LINES_NEAR_VSYNC ((uint32_t) 5U)
+
+/* ========================================================================== */
+/* Structure Declarations */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/* Function Declarations */
+/* ========================================================================== */
+
+/**
+ * Below ifdef __cplusplus is added so that C++ build passes without
+ * typecasting. This is because the prototype is build as C type
+ * whereas this file is build as CPP file. Hence we get C++ build error.
+ * Also if typecasting is used, then we get MisraC error Rule 11.1.
+ */
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * Display APIs
+ */
+static Fdrv_Handle Dss_dispDrvCreate(uint32_t drvId,
+ uint32_t instId,
+ void *createArgs,
+ void *createStatusArgs,
+ const Fvid2_DrvCbParams *fdmCbParams);
+static int32_t Dss_dispDrvDelete(Fdrv_Handle handle, void *reserved);
+static int32_t Dss_dispDrvQueue(Fdrv_Handle handle,
+ Fvid2_FrameList *frmList,
+ uint32_t streamId);
+static int32_t Dss_dispDrvDequeue(Fdrv_Handle handle,
+ Fvid2_FrameList *frmList,
+ uint32_t streamId,
+ uint32_t timeout);
+static int32_t Dss_dispDrvControl(Fdrv_Handle handle,
+ uint32_t cmd,
+ void *cmdArgs,
+ void *cmdStatusArgs);
+
+#ifdef __cplusplus
+}
+#endif
+
+/* ========================================================================== */
+/* Global Variables */
+/* ========================================================================== */
+
+extern Dss_EvtMgrClientInfo gDss_DispEvtMgrClientInfo[DSS_DISP_EVT_MGR_MAX_CLIENTS];
+
+/* ========================================================================== */
+/* Internal/Private Function Declarations */
+/* ========================================================================== */
+
+/*
+ * Display IOCTLs
+ */
+static void Dss_dispDrvClientCb(void *arg0);
+static int32_t Dss_dispDrvStartIoctl(Dss_DispDrvInstObj *instObj);
+static int32_t Dss_dispDrvStopIoctl(Dss_DispDrvInstObj *instObj);
+static int32_t Dss_dispDrvSetDssParamsIoctl(Dss_DispDrvInstObj *instObj,
+ const Dss_DispParams *dispParams);
+static int32_t Dss_dispDrvSetMflagParamsIoctl(
+ Dss_DispDrvInstObj *instObj,
+ const Dss_DispPipeMflagParams *mflagParams);
+static int32_t Dss_dispDrvGetStatusIoctl(Dss_DispDrvInstObj *instObj,
+ Dss_DispCurrentStatus *dispStatus);
+static int32_t Dss_dispDrvSetPipeSafetyParamsIoctl(
+ Dss_DispDrvInstObj *instObj,
+ const Dss_DispPipeSafetyChkParams *safetyChkParams);
+static int32_t Dss_dispDrvSetPipeCscParamsIoctl(
+ Dss_DispDrvInstObj *instObj,
+ const CSL_DssCscCoeff *cscCoeff);
+static int32_t Dss_dispDrvSetBufPrgmCbParamsIoctl(
+ Dss_DispDrvInstObj *instObj,
+ const Dss_DispBufPrgmCbParams *bufPrgmCbParams);
+static int32_t Dss_dispDrvSetPipePrgmCbParamsIoctl(
+ Dss_DispDrvInstObj *instObj,
+ const Dss_DispPipePrgmCbParams *pipePrgmCbParams);
+static int32_t Dss_dispDrvSetPipeUnderFlowCbParamsIoctl(
+ Dss_DispDrvInstObj *instObj,
+ const Dss_DispUnderFlowCbParams *underFlowCbParams);
+static int32_t Dss_dispDrvValidateDssParams(const Dss_DispDrvInstObj *instObj,
+ const Dss_DispParams *dispParams);
+static int32_t Dss_dispDrvValidateRtParams(const Dss_DispDrvInstObj *instObj,
+ const Dss_DispRtParams *rtParams);
+static int32_t Dss_dispDrvApplyRtParams(Dss_DispDrvInstObj *instObj,
+ const Dss_DispRtParams *rtParams);
+static void Dss_dispSafetyErrCbFxn(const uint32_t *event,
+ uint32_t numEvents,
+ void *arg);
+static uint32_t Dss_dispIsFarFromVsync(const Dss_DispDrvInstObj *instObj);
+
+/* ========================================================================== */
+/* Function Definitions */
+/* ========================================================================== */
+
+int32_t Dss_dispDrvInit(uint32_t numInst,
+ const Dss_DispDrvInitParams *initParams)
+{
+ int32_t retVal = FVID2_SOK;
+ Dss_DispDrvCommonObj *pObj;
+
+ retVal = Dss_dispDrvPrivInit(numInst, initParams);
+ if(FVID2_SOK == retVal)
+ {
+ pObj = &gDss_DispDrvCommonObj;
+ GT_assert(DssTrace, (NULL != pObj));
+
+ /* Initialize Driver operations */
+ Fvid2DrvOps_init(&pObj->fvidDrvOps);
+
+ pObj->fvidDrvOps.drvId = DSS_DISP_DRV_ID;
+ pObj->fvidDrvOps.createFxn = &Dss_dispDrvCreate;
+ pObj->fvidDrvOps.deleteFxn = &Dss_dispDrvDelete;
+ pObj->fvidDrvOps.controlFxn = &Dss_dispDrvControl;
+ pObj->fvidDrvOps.queueFxn = &Dss_dispDrvQueue;
+ pObj->fvidDrvOps.dequeueFxn = &Dss_dispDrvDequeue;
+
+ retVal = Fvid2_registerDriver(&pObj->fvidDrvOps);
+ if(FVID2_SOK != retVal)
+ {
+ GT_0trace(DssTrace, GT_ERR,
+ "Registering to FVID2 driver manager failed\r\n");
+ /* Un-initialize the internal objects if error occurs */
+ retVal += Dss_dispDrvPrivDeInit();
+ }
+ else
+ {
+ /* Init successful */
+ pObj->isRegistered = TRUE;
+ pObj->numInst = numInst;
+ }
+ }
+
+ return (retVal);
+}
+
+int32_t Dss_dispDrvDeInit(void)
+{
+ int32_t retVal = FVID2_SOK;
+ Dss_DispDrvCommonObj *pObj;
+
+ pObj = &gDss_DispDrvCommonObj;
+ GT_assert(DssTrace, (NULL != pObj));
+
+ if(TRUE == pObj->isRegistered)
+ {
+ /* Unregister from driver manager */
+ retVal = Fvid2_unRegisterDriver(&pObj->fvidDrvOps);
+ if(FVID2_SOK != retVal)
+ {
+ GT_0trace(DssTrace, GT_ERR,
+ "Unregistering from FVID2 driver manager failed\r\n");
+ }
+ pObj->isRegistered = FALSE;
+ }
+
+ retVal += Dss_dispDrvPrivDeInit();
+
+ return (retVal);
+}
+
+/* ========================================================================== */
+/* Static Function Definitions */
+/* ========================================================================== */
+
+static Fdrv_Handle Dss_dispDrvCreate(uint32_t drvId,
+ uint32_t instId,
+ void *createArgs,
+ void *createStatusArgs,
+ const Fvid2_DrvCbParams *fdmCbParams)
+{
+ int32_t retVal = FVID2_SOK, tempRetVal;
+ uint32_t instCreateFlag = FALSE, nodeId;
+ Fdrv_Handle drvHandle = NULL;
+ Dss_DispDrvInstObj *instObj = NULL;
+ Dss_DispCreateParams *createParams;
+ Dss_DispCreateStatus *createStatus;
+ Dss_DctrlDrvClientInfo clientInfo;
+ Dss_DctrlVpParams vpParams;
+
+ /* Check for NULL pointers and invalid arguments */
+ if((NULL == createArgs) ||
+ (NULL == createStatusArgs) ||
+ (NULL == fdmCbParams) ||
+ (DSS_DISP_DRV_ID != drvId))
+ {
+ GT_0trace(DssTrace, GT_ERR, "Invalid arguments\r\n");
+ retVal = FVID2_EBADARGS;
+ }
+ else
+ {
+ /* Get the instance object for this instance */
+ instObj = Dss_dispDrvGetInstObj(instId);
+ if(NULL == instObj)
+ {
+ GT_0trace(DssTrace, GT_ERR, "Invalid instance ID\r\n");
+ retVal = FVID2_EINVALID_PARAMS;
+ }
+ }
+
+ if(NULL != instObj)
+ {
+ /* Take the instance semaphore */
+ (void) SemaphoreP_pend(instObj->lockSem, SemaphoreP_WAIT_FOREVER);
+
+ /* Check if the instance is already opened */
+ if(TRUE == instObj->drvState.isOpened)
+ {
+ GT_0trace(DssTrace,
+ GT_ERR,
+ "Driver instance already created!!\r\n");
+ retVal = FVID2_EDEVICE_INUSE;
+ }
+ }
+
+ if(FVID2_SOK == retVal)
+ {
+ /* Check for valid create parameters and copy them */
+ createParams = (Dss_DispCreateParams *) createArgs;
+ Fvid2Utils_memcpy(&instObj->createParams,
+ createParams,
+ sizeof (Dss_DispCreateParams));
+ }
+
+ if(FVID2_SOK == retVal)
+ {
+ retVal = Dss_dispDrvCreateInstObj(instObj);
+ if(FVID2_SOK != retVal)
+ {
+ GT_0trace(DssTrace, GT_ERR,
+ "Channel object create failed!!\r\n");
+ }
+ else
+ {
+ instCreateFlag = TRUE;
+ }
+ }
+
+ if(FVID2_SOK == retVal)
+ {
+ instObj->pipeId = instId;
+ retVal = Dss_convModuletoNode(&nodeId, instObj->pipeId,
+ DSS_DCTRL_NODE_TYPE_PIPE);
+ GT_assert(DssTrace,
+ ((DSS_DCTRL_NODE_INVALID != nodeId) ||
+ (FVID2_SOK == retVal)));
+ instObj->pipeNodeId = nodeId;
+ }
+
+ if(FVID2_SOK == retVal)
+ {
+ /* Initialize instance variables */
+ Fvid2Utils_memcpy(
+ &instObj->fdmCbParams,
+ fdmCbParams,
+ sizeof (Fvid2_DrvCbParams));
+
+ instObj->drvState.isOpened = TRUE;
+ instObj->isPrevBufRep = FALSE;
+ instObj->isInIsrContext = FALSE;
+ drvHandle = instObj;
+ }
+
+ if(FVID2_SOK == retVal)
+ {
+ clientInfo.cbFxn = &Dss_dispDrvClientCb;
+ clientInfo.arg = instObj;
+ instObj->dctrlHandle = Dss_dctrlDrvRegisterClient(instObj->pipeNodeId,
+ &clientInfo);
+ if(NULL == instObj->dctrlHandle)
+ {
+ GT_0trace(DssTrace,
+ GT_ERR,
+ "Display Controller registration failed for DSS");
+ retVal = FVID2_EALLOC;
+ }
+ else
+ {
+ retVal = Dss_dctrlDrvGetVpParams(instObj->dctrlHandle, &vpParams);
+ if(FVID2_SOK != retVal)
+ {
+ GT_0trace(DssTrace,
+ GT_ERR,
+ "Getting information from Display controller failed");
+ }
+ else
+ {
+ instObj->standard = vpParams.lcdOpTimingCfg.mInfo.standard;
+ instObj->dispWidth = vpParams.lcdOpTimingCfg.mInfo.width;
+ instObj->dispHeight = vpParams.lcdOpTimingCfg.mInfo.height;
+ instObj->dispScanFormat =
+ vpParams.lcdOpTimingCfg.mInfo.scanFormat;
+ instObj->vpId = vpParams.vpId;
+ }
+ }
+ }
+
+ if(FVID2_SOK != retVal)
+ {
+ if((NULL != instObj) && (NULL != instObj->dctrlHandle))
+ {
+ retVal += Dss_dctrlDrvUnRegisterClient(instObj->dctrlHandle);
+ }
+ }
+
+ /* Return the status if possible */
+ if(NULL != createStatusArgs)
+ {
+ createStatus = (Dss_DispCreateStatus *) createStatusArgs;
+ createStatus->retVal = retVal;
+ if(NULL != instObj)
+ {
+ createStatus->standard = instObj->standard;
+ createStatus->dispWidth = instObj->dispWidth;
+ createStatus->dispHeight = instObj->dispHeight;
+ createStatus->minNumPrimeBuf = DSS_DISP_DRV_MIN_PRIME_BUFFERS;
+ }
+ }
+
+ if(NULL != instObj)
+ {
+ /* Deallocate if error occurs */
+ if(FVID2_SOK != retVal)
+ {
+ if(TRUE == instCreateFlag)
+ {
+ tempRetVal = Dss_dispDrvDeleteInstObj(instObj);
+ GT_assert(DssTrace, (FVID2_SOK == tempRetVal));
+ }
+ }
+
+ /* Post the instance semaphore */
+ (void) SemaphoreP_post(instObj->lockSem);
+ }
+
+ return (drvHandle);
+}
+
+static int32_t Dss_dispDrvDelete(Fdrv_Handle handle, void *reserved)
+{
+ int32_t retVal = FVID2_SOK;
+ Dss_DispDrvInstObj *instObj = NULL;
+
+ /* Check for NULL pointers and invalid arguments */
+ if(NULL == handle)
+ {
+ GT_0trace(DssTrace, GT_ERR, "Invalid arguments\r\n");
+ retVal = FVID2_EBADARGS;
+ }
+ else
+ {
+ instObj = (Dss_DispDrvInstObj *) handle;
+ }
+
+ if(NULL != instObj)
+ {
+ /* Take the instance semaphore */
+ (void) SemaphoreP_pend(instObj->lockSem, SemaphoreP_WAIT_FOREVER);
+
+ /* Check if already opened. */
+ if(TRUE != instObj->drvState.isOpened)
+ {
+ GT_0trace(DssTrace, GT_ERR, "Driver not opened\r\n");
+ retVal = FVID2_EFAIL;
+ }
+ }
+
+ if(FVID2_SOK == retVal)
+ {
+ /* If already started, stop it. */
+ if(TRUE == instObj->drvState.isStarted)
+ {
+ retVal = Dss_dispDrvStopIoctl(instObj);
+ if(FVID2_SOK != retVal)
+ {
+ GT_0trace(DssTrace, GT_ERR, "Stop display failed\r\n");
+ }
+ }
+ }
+
+ if(FVID2_SOK == retVal)
+ {
+ if(NULL != instObj->dctrlHandle)
+ {
+ retVal = Dss_dctrlDrvUnRegisterClient(instObj->dctrlHandle);
+ }
+ retVal += Dss_dispDrvDeleteInstObj(instObj);
+ GT_assert(DssTrace, (FVID2_SOK == retVal));
+
+ /* Reset other variables */
+ instObj->drvState.isOpened = FALSE;
+ instObj->drvState.isStarted = FALSE;
+ instObj->currStatus.queueCount = 0U;
+ instObj->currStatus.dequeueCount = 0U;
+ instObj->currStatus.dispFrmCount = 0U;
+ instObj->currStatus.repeatFrmCount = 0U;
+
+ instObj->fdmCbParams.fdmCbFxn = NULL;
+ instObj->fdmCbParams.fdmErrCbFxn = NULL;
+ instObj->fdmCbParams.handle = NULL;
+ instObj->fdmCbParams.errList = NULL;
+ instObj->fdmCbParams.fdmData = NULL;
+ }
+
+ if(NULL != instObj)
+ {
+ /* Post the instance semaphore */
+ (void) SemaphoreP_post(instObj->lockSem);
+ }
+
+ return (retVal);
+}
+
+static int32_t Dss_dispDrvQueue(Fdrv_Handle handle,
+ Fvid2_FrameList *frmList,
+ uint32_t streamId)
+{
+ int32_t retVal = FVID2_SOK;
+ uint32_t frmCnt, cookie;
+ uint32_t reqQCnt, isSafe;
+ uint32_t isBufAccepted = TRUE;
+ Fvid2_Frame *frm, *newFrm;
+ Dss_DispDrvInstObj *instObj;
+ Dss_DispDrvQueObj *qObj, *qObjTemp;
+ CSL_dss_pipeRegs *pipeRegs;
+ const Dss_SocInfo *socInfo;
+ Dss_DispRtParams *rtParams;
+ int32_t rtParamsRetVal = FVID2_SOK;
+
+ /* Check for NULL pointers */
+ if((NULL == handle) || (NULL == frmList))
+ {
+ GT_0trace(DssTrace, GT_ERR, "NULL pointer\r\n");
+ retVal = FVID2_EBADARGS;
+ }
+
+ if(FVID2_SOK == retVal)
+ {
+ instObj = (Dss_DispDrvInstObj *) handle;
+
+ /* Check frame list for error and NULL pointer check */
+ retVal = Fvid2_checkFrameList(frmList, (uint32_t) FVID2_MAX_FRAME_PTR);
+ if(FVID2_SOK != retVal)
+ {
+ GT_0trace(DssTrace, GT_ERR, "Check frame list error\r\n");
+ }
+
+ if(FALSE == instObj->drvState.isOpened)
+ {
+ /* If driver handle is not open then skip this frame queue */
+ GT_0trace(DssTrace,
+ GT_ERR,
+ "Can't queue to an un-opened instance!!\r\n");
+ retVal = FVID2_EFAIL;
+ }
+ /* Only one frame submit supported per instance */
+ if(frmList->numFrames > 1U)
+ {
+ GT_0trace(DssTrace,
+ GT_ERR,
+ "Only one frame submit supported in current design\r\n");
+ retVal = FVID2_EFAIL;
+ }
+ }
+
+ if(FVID2_SOK == retVal)
+ {
+ /* For all frames that need to be queued. The loop is dummy */
+ for(frmCnt=0U; frmCnt<frmList->numFrames; frmCnt++)
+ {
+ /* Get FVID2 frame pointer - NULL check is already done in
+ * check frame list function */
+ frm = frmList->frames[frmCnt];
+ GT_assert(DssTrace, (NULL != frm));
+
+ cookie = HwiP_disable();
+
+ /* Allocate a free queue object from the pool */
+ qObj = (Dss_DispDrvQueObj *) Fvid2Utils_dequeue(
+ instObj->bmObj.freeQ);
+ if(NULL == qObj)
+ {
+ HwiP_restore(cookie);
+ GT_0trace(DssTrace,
+ GT_ERR,
+ "Q object allocation failed\r\n");
+ retVal = FVID2_EALLOC;
+ break;
+ }
+
+ /* Copy the frame to the driver's queue object */
+ qObj->frm = frm;
+ /* Initial credit count should be zero!! */
+ GT_assert(DssTrace, (0U == qObj->creditCnt));
+
+ /* Push mechanism */
+ /* 1. Check if the new frame should be updated immediately in case
+ * of frame repeat.
+ * 2. Check if the previous frame was repeated
+ * 3. Check if request queue is empty
+ * 4. If request queue is not empty then put it in the request
+ * queue and exit.
+ * 5. If request queue is empty then push the buffer to hardware
+ * 6. If hardware accepts then put the buffer in current queue and
+ * update the credit count
+ * 7. If hardware accepts the buffer then make the prevRepBuf as
+ * false. This is required if two back to back buffers are
+ * queued in same frame period. (The second buffer should not be
+ * pushed if first once is accepted)
+ * 8. If hardware doesn't accept the buffer then put it in the
+ * request queue.
+ * 9. In Vsync call back we set the prevBufRepeated flag
+ * appropriately.
+ * a. Set to true if no buffer is available in request queue
+ * b. Set to false if buffer is given to hardware
+ * 10. Here we will overwrite the buffer present in the currQ with
+ * the new one. Basically what needs to done is to revert what
+ * is being done in Vsync callback function when the buffer
+ * is repeated. So peak the current queue and decrement
+ * the credit count. It will automatically moved to doneQ in
+ * next Vsync Call back.
+ */
+ reqQCnt = Fvid2Utils_getNumQElem(instObj->bmObj.reqQ);
+ if((0U == reqQCnt) &&
+ (FALSE == instObj->createParams.progPipeVsyncEnable) &&
+ (TRUE == instObj->isPrevBufRep) &&
+ /* Don't program if queue is called from ISR callback context.
+ * Just push to request queue */
+ (FALSE == instObj->isInIsrContext))
+ {
+ /* Call the user buffer program callback */
+ if(NULL != instObj->bufPrgmCbParams.bufPrgmCbFxn)
+ {
+ newFrm = instObj->bufPrgmCbParams.bufPrgmCbFxn(
+ instObj->fdmCbParams.handle,
+ qObj->frm,
+ FALSE,
+ qObj->creditCnt);
+ if(NULL != newFrm)
+ {
+ /* Swap the current frame */
+ qObj->frm = newFrm;
+ }
+ }
+
+ /* Query display controller to check if it is safe to push */
+ isSafe = Dss_dispIsFarFromVsync(instObj);
+
+ if((retVal == FVID2_SOK) && (isSafe == TRUE))
+ {
+ instObj->progFrame = qObj->frm;
+
+ /* Get video pipe registers */
+ socInfo = Dss_getSocInfo();
+ pipeRegs = socInfo->pipeRegs[instObj->pipeId];
+ GT_assert(DssTrace, (NULL != pipeRegs));
+
+ if(NULL != instObj->progFrame->perFrameCfg)
+ {
+ rtParams =
+ (Dss_DispRtParams *)(instObj->progFrame->perFrameCfg);
+ rtParamsRetVal = Dss_dispDrvValidateRtParams(instObj,
+ rtParams);
+ if(FVID2_SOK == rtParamsRetVal)
+ {
+ Dss_dispDrvApplyRtParams(instObj, rtParams);
+ }
+ }
+
+ CSL_dssVidPipeSetBuffAddr(pipeRegs,
+ FVID2_FID_TOP,
+ instObj->progFrame->addr[0U],
+ instObj->progFrame->addr[1U]);
+
+ if(instObj->inScanFormat == FVID2_SF_INTERLACED)
+ {
+ CSL_dssVidPipeSetBuffAddr(pipeRegs,
+ FVID2_FID_BOTTOM,
+ instObj->progFrame->addr[3U],
+ instObj->progFrame->addr[4U]);
+ }
+ if(NULL != instObj->pipePrgmCbParams.pipePrgmCbFxn)
+ {
+ /* Give callback to application that buffer has been
+ * programmed
+ */
+ instObj->pipePrgmCbParams.pipePrgmCbFxn(
+ instObj->progFrame,
+ instObj->pipePrgmCbParams.appData);
+ }
+
+ retVal = Dss_dctrlDrvSetGoBit(instObj->dctrlHandle);
+ }
+
+ isBufAccepted = isSafe;
+
+ if(TRUE == isBufAccepted)
+ {
+ /* Decrement the credit count of previously repeated buffer,
+ * This is not a repeat now as we are overwriting the
+ * buffer */
+ qObjTemp = (Dss_DispDrvQueObj *) Fvid2Utils_peakTail(
+ instObj->bmObj.currQ);
+ /* This can't return NULL unless there is a bug in the
+ * buffer management */
+ GT_assert(DssTrace, (NULL != qObjTemp));
+ qObjTemp->creditCnt--;
+
+ Fvid2Utils_queue(instObj->bmObj.currQ, &qObj->qElem, qObj);
+ qObj->creditCnt++;
+ instObj->isPrevBufRep = FALSE;
+ /* This is like a queue only, so increment the count*/
+ instObj->currStatus.queueCount++;
+ }
+ else
+ {
+ /* Add the queue object in driver's request queue */
+ Fvid2Utils_queue(instObj->bmObj.reqQ, &qObj->qElem, qObj);
+ instObj->currStatus.queueCount++;
+ }
+ }
+ else
+ {
+ /* Add the queue object in driver's request queue */
+ Fvid2Utils_queue(instObj->bmObj.reqQ, &qObj->qElem, qObj);
+ instObj->currStatus.queueCount++;
+ }
+
+ HwiP_restore(cookie);
+
+ /* Mark frame in frmList as NULL */
+ frmList->frames[frmCnt] = NULL;
+ }
+ }
+
+ return (retVal);
+}
+
+static int32_t Dss_dispDrvDequeue(Fdrv_Handle handle,
+ Fvid2_FrameList *frmList,
+ uint32_t streamId,
+ uint32_t timeout)
+{
+ int32_t retVal = FVID2_SOK;
+ uint32_t cookie;
+ Dss_DispDrvInstObj *instObj;
+ Dss_DispDrvQueObj *qObj;
+ Dss_DispDrvBufManObj *bmObj;
+
+ /* Check for NULL pointers */
+ if((NULL == handle) || (NULL == frmList) || (streamId > 0U))
+ {
+ GT_0trace(DssTrace, GT_ERR, "Invalid argument!!\r\n");
+ retVal = FVID2_EBADARGS;
+ }
+
+ if(FVID2_SOK == retVal)
+ {
+ instObj = (Dss_DispDrvInstObj *) handle;
+ bmObj = &instObj->bmObj;
+
+ if(FALSE == instObj->drvState.isOpened)
+ {
+ GT_0trace(
+ DssTrace,
+ GT_ERR,
+ "Invalid Driver state: Can't dequeue to an un-opened instance!!\r\n");
+ retVal = FVID2_EFAIL;
+ }
+ }
+
+ if(FVID2_SOK == retVal)
+ {
+ /* Init frame list fields */
+ frmList->numFrames = 0U;
+ frmList->perListCfg = NULL;
+
+ cookie = HwiP_disable();
+
+ /* Get a completed queue object from driver's done queue */
+ qObj = (Dss_DispDrvQueObj *) Fvid2Utils_dequeue(bmObj->doneQ);
+ if(NULL == qObj)
+ {
+ /* When display is stopped, give back all the driver owned buffer
+ * including the current programmed and the buffers in request
+ * queue */
+ if(TRUE != instObj->drvState.isStarted)
+ {
+ /* Give the buffers in current state */
+ qObj = (Dss_DispDrvQueObj *) Fvid2Utils_dequeue(bmObj->currQ);
+ if(NULL == qObj)
+ {
+ /* At last give back the buffers in request queue as well */
+ qObj = (Dss_DispDrvQueObj *) Fvid2Utils_dequeue(
+ bmObj->reqQ);
+ }
+
+ /* Check if all these operation has failed */
+ if(NULL == qObj)
+ {
+ GT_0trace(DssTrace,
+ GT_DEBUG,
+ "NO_MORE_BUFFERS: No more buffers with driver\n");
+ retVal = FVID2_ENO_MORE_BUFFERS;
+ }
+ }
+ else
+ {
+ GT_0trace(DssTrace,
+ GT_DEBUG,
+ "AGAIN: Out queue Empty. Try again\r\n");
+ retVal = FVID2_EAGAIN;
+ }
+ }
+
+ HwiP_restore(cookie);
+
+ /* Copy the driver's frame list to application's frame list */
+ if(NULL != qObj)
+ {
+ cookie = HwiP_disable();
+
+ GT_assert(DssTrace, (NULL != qObj->frm));
+ frmList->frames[frmList->numFrames] = qObj->frm;
+ frmList->numFrames++;
+
+ /* Give back the queue object back to the free pool */
+ qObj->frm = NULL;
+ /* At time of dequeue, credit should be zero!! */
+ GT_assert(DssTrace, (0U == qObj->creditCnt));
+ Fvid2Utils_queue(bmObj->freeQ, &qObj->qElem, qObj);
+ instObj->currStatus.dequeueCount++;
+
+ HwiP_restore(cookie);
+ }
+ }
+
+ return (retVal);
+}
+
+static int32_t Dss_dispDrvControl(Fdrv_Handle handle,
+ uint32_t cmd,
+ void *cmdArgs,
+ void *cmdStatusArgs)
+{
+ int32_t retVal = FVID2_SOK;
+ Dss_DispDrvInstObj *instObj;
+
+ /* Check for NULL pointers */
+ if(NULL == handle)
+ {
+ GT_0trace(DssTrace, GT_ERR, "Invalid argument!!\r\n");
+ retVal = FVID2_EBADARGS;
+ }
+
+ if(FVID2_SOK == retVal)
+ {
+ instObj = (Dss_DispDrvInstObj *) handle;
+ switch (cmd)
+ {
+ case FVID2_START:
+ retVal = Dss_dispDrvStartIoctl(instObj);
+ break;
+ case FVID2_STOP:
+ retVal = Dss_dispDrvStopIoctl(instObj);
+ break;
+ case IOCTL_DSS_DISP_SET_DSS_PARAMS:
+ retVal = Dss_dispDrvSetDssParamsIoctl(
+ instObj,
+ (const Dss_DispParams *) cmdArgs);
+ break;
+ case IOCTL_DSS_DISP_SET_PIPE_MFLAG_PARAMS:
+ retVal = Dss_dispDrvSetMflagParamsIoctl(
+ instObj,
+ (const Dss_DispPipeMflagParams *) cmdArgs);
+ break;
+ case IOCTL_DSS_DISP_GET_CURRENT_STATUS:
+ retVal = Dss_dispDrvGetStatusIoctl(
+ instObj,
+ (Dss_DispCurrentStatus *) cmdArgs);
+ break;
+ case IOCTL_DSS_DISP_SET_PIPE_SAFETY_CHK_PARAMS:
+ retVal = Dss_dispDrvSetPipeSafetyParamsIoctl(
+ instObj,
+ (const Dss_DispPipeSafetyChkParams *) cmdArgs);
+ break;
+ case IOCTL_DSS_DISP_SET_PIPE_CSC_COEFF:
+ retVal = Dss_dispDrvSetPipeCscParamsIoctl(
+ instObj,
+ (const CSL_DssCscCoeff *) cmdArgs);
+ break;
+ case IOCTL_DSS_DISP_REGISTER_BUF_PRGM_CB:
+ retVal = Dss_dispDrvSetBufPrgmCbParamsIoctl(
+ instObj,
+ (const Dss_DispBufPrgmCbParams *) cmdArgs);
+ break;
+ case IOCTL_DSS_DISP_REGISTER_PIPE_PRGM_CB:
+ retVal = Dss_dispDrvSetPipePrgmCbParamsIoctl(
+ instObj,
+ (const Dss_DispPipePrgmCbParams *) cmdArgs);
+ break;
+ case IOCTL_DSS_DISP_REGISTER_PIPE_UNDERFLOW_CB:
+ retVal = Dss_dispDrvSetPipeUnderFlowCbParamsIoctl(
+ instObj,
+ (const Dss_DispUnderFlowCbParams *) cmdArgs);
+ break;
+ default:
+ GT_0trace(DssTrace, GT_ERR,
+ "UNSUPPORTED_CMD: IOCTL not supported\r\n");
+ retVal = FVID2_EUNSUPPORTED_CMD;
+ break;
+ }
+ }
+
+ return (retVal);
+}
+
+static void Dss_dispDrvClientCb(void *arg0)
+{
+ Dss_DispDrvInstObj *instObj;
+ Dss_DispDrvQueObj *qObj, *qObjTemp;
+ uint32_t currQCnt, reqQCnt, cookie;
+ uint32_t frmQueuedToDoneQ = FALSE;
+ CSL_dss_pipeRegs *pipeRegs;
+ const Dss_SocInfo *socInfo;
+ Fvid2_Frame *newFrm;
+ Dss_DispRtParams *rtParams;
+ int32_t rtParamsRetVal = FVID2_SOK;
+
+ GT_assert(DssTrace, (NULL != arg0));
+ instObj = (Dss_DispDrvInstObj *)arg0;
+
+ if(TRUE == instObj->drvState.isStarted)
+ {
+ cookie = HwiP_disable();
+
+ if(NULL != instObj->currFrame)
+ {
+ /* Update channel statistics */
+ instObj->currStatus.dispFrmCount++;
+ /* Get current queue head */
+ qObj = (Dss_DispDrvQueObj *) Fvid2Utils_peakHead(instObj->bmObj.currQ);
+ GT_assert(DssTrace, (NULL != qObj));
+
+ /* Decrement credit count as frame display is complete - credit can't
+ * be zero */
+ GT_assert(DssTrace, (qObj->creditCnt > 0U));
+ qObj->creditCnt--;
+ if(qObj->creditCnt > 0U)
+ {
+ instObj->currStatus.repeatFrmCount++;
+ }
+
+ /* Get the current queue counts */
+ currQCnt = Fvid2Utils_getNumQElem(instObj->bmObj.currQ);
+ reqQCnt = Fvid2Utils_getNumQElem(instObj->bmObj.reqQ);
+
+ if(0U == qObj->creditCnt)
+ {
+ qObjTemp = (Dss_DispDrvQueObj *) Fvid2Utils_dequeue(
+ instObj->bmObj.currQ);
+ /* Head node and qObj should match */
+ GT_assert(DssTrace, (qObj == qObjTemp));
+
+ /* In last frame repeat mode, we could return all the frames to
+ * the application if credit becomes 0 and there are some more
+ * request in the current or request queue. Current queue is
+ * checked for 1 element as the current frame is still present
+ * in the queue. */
+ if((currQCnt > 1U) || (reqQCnt > 0U))
+ {
+ /* Return the frame to done queue */
+ GT_assert(DssTrace, (NULL != qObj->frm));
+ Fvid2Utils_queue(instObj->bmObj.doneQ, &qObj->qElem, qObj);
+ frmQueuedToDoneQ = TRUE;
+ }
+ /* In last frame repeat mode, if credit becomes 0 and there are
+ * no more request in the current and request queues, take this
+ * request and queue it back to request queue so that when
+ * the hardware asks for next buffer, we repeat the frame
+ * automatically. This is needed because the user could
+ * queue a request in between and this frame will end-up
+ * in the current queue!!
+ * Also increment the repeat frame counter here. */
+ else if((currQCnt == 1U) && (reqQCnt == 0U))
+ {
+ instObj->currStatus.repeatFrmCount++;
+ Fvid2Utils_queue(instObj->bmObj.reqQ, &qObj->qElem, qObj);
+ }
+ else
+ {
+ /* This can't happen as currQCnt can't be zero!! */
+ GT_assert(DssTrace, FALSE);
+ }
+ }
+ }
+
+ if(NULL != instObj->fdmCbParams.fdmCbFxn)
+ {
+ /* Give callback to application if periodic call back is enabled or
+ * if frame is put in done queue */
+ if((TRUE == instObj->createParams.periodicCbEnable) ||
+ (TRUE == frmQueuedToDoneQ))
+ {
+ instObj->isInIsrContext = TRUE;
+ instObj->fdmCbParams.fdmCbFxn(instObj->fdmCbParams.fdmData);
+ instObj->isInIsrContext = FALSE;
+ }
+ }
+
+ instObj->currFrame = instObj->progFrame;
+
+ /* Get new frame from request queue or repeat frame */
+ qObj = (Dss_DispDrvQueObj *) Fvid2Utils_dequeue(instObj->bmObj.reqQ);
+ if(NULL != qObj)
+ {
+ /*
+ * Buffer available in request queue
+ */
+ /* Increment credit */
+ qObj->creditCnt++;
+ Fvid2Utils_queue(instObj->bmObj.currQ, &qObj->qElem, qObj);
+ instObj->isPrevBufRep = FALSE;
+ }
+ else
+ {
+ /*
+ * No more buffers available in request queue.
+ * Repeat the last frame queued.
+ */
+ qObj = (Dss_DispDrvQueObj *) Fvid2Utils_peakTail(
+ instObj->bmObj.currQ);
+ /* This can't return NULL unless there is a bug in the buffer
+ * management */
+ GT_assert(DssTrace, (NULL != qObj));
+ /* Increment credit */
+ qObj->creditCnt++;
+ /* Mark the buffer as repeated */
+ instObj->isPrevBufRep = TRUE;
+ }
+
+ /* Call the user buffer program callback */
+ if(NULL != instObj->bufPrgmCbParams.bufPrgmCbFxn)
+ {
+ newFrm = instObj->bufPrgmCbParams.bufPrgmCbFxn(
+ instObj->fdmCbParams.handle,
+ qObj->frm,
+ instObj->isPrevBufRep,
+ qObj->creditCnt);
+ if(NULL != newFrm)
+ {
+ /* Swap the current frame */
+ qObj->frm = newFrm;
+ }
+ }
+
+ /* Set frame to be programmed */
+ instObj->progFrame = qObj->frm;
+ /* Driver should always give the buffers when requested */
+ GT_assert(DssTrace, (instObj->progFrame != NULL));
+ /* Get video pipe registers */
+ socInfo = Dss_getSocInfo();
+ pipeRegs = socInfo->pipeRegs[instObj->pipeId];
+ GT_assert(DssTrace, (NULL != pipeRegs));
+
+ if(NULL != instObj->progFrame->perFrameCfg)
+ {
+ rtParams = (Dss_DispRtParams *)(instObj->progFrame->perFrameCfg);
+ rtParamsRetVal = Dss_dispDrvValidateRtParams(instObj, rtParams);
+ if(FVID2_SOK == rtParamsRetVal)
+ {
+ Dss_dispDrvApplyRtParams(instObj, rtParams);
+ }
+ }
+
+ CSL_dssVidPipeSetBuffAddr(pipeRegs,
+ FVID2_FID_TOP,
+ instObj->progFrame->addr[0U],
+ instObj->progFrame->addr[1U]);
+
+ if(instObj->inScanFormat == FVID2_SF_INTERLACED)
+ {
+ CSL_dssVidPipeSetBuffAddr(pipeRegs,
+ FVID2_FID_BOTTOM,
+ instObj->progFrame->addr[3U],
+ instObj->progFrame->addr[4U]);
+ }
+
+ if(NULL != instObj->pipePrgmCbParams.pipePrgmCbFxn)
+ {
+ /* Give callback to application that buffer has been programmed */
+ instObj->pipePrgmCbParams.pipePrgmCbFxn(
+ instObj->progFrame,
+ instObj->pipePrgmCbParams.appData);
+ }
+
+ HwiP_restore(cookie);
+ }
+ else if(TRUE == instObj->drvState.isStarting)
+ {
+ cookie = HwiP_disable();
+
+ /* Start display */
+ instObj->drvState.isStarted = TRUE;
+ qObj = (Dss_DispDrvQueObj *) Fvid2Utils_dequeue(instObj->bmObj.reqQ);
+ if(NULL != qObj)
+ {
+ /*
+ * Buffer available in request queue
+ */
+ /* Increment credit */
+ qObj->creditCnt++;
+ Fvid2Utils_queue(instObj->bmObj.currQ, &qObj->qElem, qObj);
+ instObj->isPrevBufRep = FALSE;
+ instObj->progFrame = qObj->frm;
+ }
+ else
+ {
+ /* This can't return NULL unless application has made a mistake */
+ GT_assert(DssTrace, (NULL != qObj));
+ }
+
+ /* Driver should always give the buffers when requested */
+ GT_assert(DssTrace, (instObj->progFrame != NULL));
+
+ /* Get video pipe registers */
+ socInfo = Dss_getSocInfo();
+ pipeRegs = socInfo->pipeRegs[instObj->pipeId];
+ GT_assert(DssTrace, (NULL != pipeRegs));
+
+ CSL_dssVidPipeSetBuffAddr(pipeRegs,
+ FVID2_FID_TOP,
+ instObj->progFrame->addr[0U],
+ instObj->progFrame->addr[1U]);
+
+ if(instObj->inScanFormat == FVID2_SF_INTERLACED)
+ {
+ CSL_dssVidPipeSetBuffAddr(pipeRegs,
+ FVID2_FID_BOTTOM,
+ instObj->progFrame->addr[3U],
+ instObj->progFrame->addr[4U]);
+ }
+
+ CSL_dssVidPipeEnable(pipeRegs, TRUE);
+ instObj->drvState.isStarting = FALSE;
+
+ if(NULL != instObj->pipePrgmCbParams.pipePrgmCbFxn)
+ {
+ /* Give callback to application that buffer has been programmed */
+ instObj->pipePrgmCbParams.pipePrgmCbFxn(
+ instObj->progFrame,
+ instObj->pipePrgmCbParams.appData);
+ }
+
+ HwiP_restore(cookie);
+ }
+ else if(TRUE == instObj->drvState.isStopping)
+ {
+ cookie = HwiP_disable();
+
+ /* Get video pipe registers */
+ socInfo = Dss_getSocInfo();
+ pipeRegs = socInfo->pipeRegs[instObj->pipeId];
+ GT_assert(DssTrace, (NULL != pipeRegs));
+
+ /* Disable Video Pipe */
+ CSL_dssVidPipeEnable(pipeRegs, FALSE);
+ instObj->currFrame = NULL;
+ instObj->progFrame = NULL;
+ instObj->drvState.isStopping = FALSE;
+
+ /* Take the buffers in current state and push them in to the request
+ * queue so that the next start will use those buffers */
+ qObj = (Dss_DispDrvQueObj *) Fvid2Utils_dequeue(instObj->bmObj.currQ);
+ while (NULL != qObj)
+ {
+ qObj->creditCnt = 0U;
+ /* Push it to the request queue */
+ Fvid2Utils_queueBack(instObj->bmObj.reqQ, &qObj->qElem, qObj);
+ qObj = (Dss_DispDrvQueObj *) Fvid2Utils_dequeue(
+ instObj->bmObj.currQ);
+ };
+
+ if(NULL != instObj->pipePrgmCbParams.pipePrgmCbFxn)
+ {
+ /* Give callback to application that buffer has been programmed */
+ instObj->pipePrgmCbParams.pipePrgmCbFxn(
+ instObj->progFrame,
+ instObj->pipePrgmCbParams.appData);
+ }
+
+ HwiP_restore(cookie);
+ }
+ else
+ {
+ /* Should never execute this */
+ GT_assert(DssTrace, FALSE);
+ }
+}
+
+static int32_t Dss_dispDrvStartIoctl(Dss_DispDrvInstObj *instObj)
+{
+ int32_t retVal = FVID2_SOK;
+ uint32_t numElemInReqQ, isSafe, dummyStart;
+ Dss_DispDrvBufManObj *bmObj;
+ Dss_DispDrvQueObj *qObj;
+ uint32_t cookie;
+ CSL_dss_pipeRegs *pipeRegs;
+ const Dss_SocInfo *socInfo;
+
+ /* Check for NULL pointers */
+ GT_assert(DssTrace, (NULL != instObj));
+
+ /* Take the instance semaphore */
+ (void) SemaphoreP_pend(instObj->lockSem, SemaphoreP_WAIT_FOREVER);
+
+ bmObj = &instObj->bmObj;
+
+ /* Initialize instance variables that needs to be reset in stop/start
+ * sequence */
+ instObj->currStatus.dispFrmCount = 0U;
+ instObj->currStatus.repeatFrmCount = 0U;
+ bmObj->expectedFid = 0U;
+ bmObj->curFid = 0U;
+
+ /* Check if the number of elements in the queue is sufficient to prime */
+ numElemInReqQ = Fvid2Utils_getNumQElem(instObj->bmObj.reqQ);
+ if(numElemInReqQ < DSS_DISP_DRV_MIN_PRIME_BUFFERS)
+ {
+ GT_0trace(DssTrace, GT_ERR, "Insufficient buffers queued\r\n");
+ retVal = FVID2_EFAIL;
+ }
+
+ if(FVID2_SOK == retVal)
+ {
+ if(FALSE == instObj->createParams.progPipeVsyncEnable)
+ {
+ /* Get video pipe registers */
+ socInfo = Dss_getSocInfo();
+ pipeRegs = socInfo->pipeRegs[instObj->pipeId];
+ GT_assert(DssTrace, (NULL != pipeRegs));
+
+ cookie = HwiP_disable();
+ /* Check if it is safe to start or start is too near to VSYNC */
+ isSafe = Dss_dispIsFarFromVsync(instObj);
+ if(TRUE == isSafe)
+ {
+ qObj = (Dss_DispDrvQueObj *) Fvid2Utils_dequeue(
+ instObj->bmObj.reqQ);
+ if(NULL != qObj)
+ {
+ /*
+ * Buffer available in request queue
+ */
+ /* Increment credit */
+ qObj->creditCnt++;
+ Fvid2Utils_queue(instObj->bmObj.currQ, &qObj->qElem, qObj);
+ instObj->isPrevBufRep = FALSE;
+ instObj->progFrame = qObj->frm;
+ }
+ else
+ {
+ /*
+ * No more buffers available in request queue.
+ * Repeat the last frame queued.
+ */
+ qObj = (Dss_DispDrvQueObj *) Fvid2Utils_peakTail(
+ instObj->bmObj.currQ);
+ /* This can't return NULL unless there is a bug in the
+ * buffer management */
+ GT_assert(DssTrace, (NULL != qObj));
+ /* Increment credit */
+ qObj->creditCnt++;
+ /* Mark the buffer as repeated */
+ instObj->isPrevBufRep = TRUE;
+ instObj->progFrame = qObj->frm;
+ }
+
+ /* Driver should always give the buffers when requested */
+ GT_assert(DssTrace, (instObj->progFrame != NULL));
+
+ CSL_dssVidPipeSetBuffAddr(pipeRegs,
+ FVID2_FID_TOP,
+ instObj->progFrame->addr[0U],
+ instObj->progFrame->addr[1U]);
+
+ if(instObj->inScanFormat == FVID2_SF_INTERLACED)
+ {
+ CSL_dssVidPipeSetBuffAddr(pipeRegs,
+ FVID2_FID_BOTTOM,
+ instObj->progFrame->addr[3U],
+ instObj->progFrame->addr[4U]);
+ }
+
+ /* Start display */
+ instObj->drvState.isStarted = TRUE;
+ dummyStart = FALSE;
+ CSL_dssVidPipeEnable(pipeRegs, TRUE);
+ if(NULL != instObj->pipePrgmCbParams.pipePrgmCbFxn)
+ {
+ /* Give callback to application that buffer has been
+ * programmed */
+ instObj->pipePrgmCbParams.pipePrgmCbFxn(
+ instObj->progFrame,
+ instObj->pipePrgmCbParams.appData);
+ }
+ }
+ else
+ {
+ instObj->drvState.isStarting = TRUE;
+ dummyStart = TRUE;
+ }
+
+ HwiP_restore(cookie);
+ retVal = Dss_dctrlDrvStartClient(instObj->dctrlHandle, dummyStart);
+
+ if(FVID2_SOK != retVal)
+ {
+ instObj->drvState.isStarted = FALSE;
+ instObj->drvState.isStarting = FALSE;
+ CSL_dssVidPipeEnable(pipeRegs, FALSE);
+ Dss_dctrlDrvStopClient(instObj->dctrlHandle, dummyStart);
+ GT_0trace(DssTrace, GT_ERR, "Driver start failed!!\r\n");
+ }
+ }
+ else
+ {
+ instObj->drvState.isStarting = TRUE;
+ retVal = Dss_dctrlDrvStartClient(instObj->dctrlHandle, TRUE);
+ if(FVID2_SOK != retVal)
+ {
+ instObj->drvState.isStarting = FALSE;
+ Dss_dctrlDrvStopClient(instObj->dctrlHandle, TRUE);
+ GT_0trace(DssTrace, GT_ERR, "Driver start failed!!\r\n");
+ }
+ }
+ }
+
+ if(FVID2_SOK != retVal)
+ {
+ GT_0trace(DssTrace, GT_ERR, "Fvid2 start failed\r\n");
+ }
+
+ /* Post the instance semaphore */
+ (void) SemaphoreP_post(instObj->lockSem);
+
+ return (retVal);
+}
+
+static int32_t Dss_dispDrvStopIoctl(Dss_DispDrvInstObj *instObj)
+{
+ int32_t retVal = FVID2_SOK;
+ uint32_t cookie;
+ Dss_DispDrvQueObj *qObj;
+ CSL_dss_pipeRegs *pipeRegs;
+ const Dss_SocInfo *socInfo;
+
+ /* Check for NULL pointers */
+ GT_assert(DssTrace, (NULL != instObj));
+
+ /* Take the instance semaphore */
+ (void) SemaphoreP_pend(instObj->lockSem, SemaphoreP_WAIT_FOREVER);
+
+ if(FALSE == instObj->createParams.progPipeVsyncEnable)
+ {
+ /* Get video pipe registers */
+ socInfo = Dss_getSocInfo();
+ pipeRegs = socInfo->pipeRegs[instObj->pipeId];
+ GT_assert(DssTrace, (NULL != pipeRegs));
+
+ /* Disable Video Pipe */
+ CSL_dssVidPipeEnable(pipeRegs, FALSE);
+ instObj->currFrame = NULL;
+ instObj->progFrame = NULL;
+ retVal = Dss_dctrlDrvStopClient(instObj->dctrlHandle, FALSE);
+
+ if(FVID2_SOK == retVal)
+ {
+ cookie = HwiP_disable();
+
+ instObj->drvState.isStarted = FALSE;
+
+ /* Take the buffers in current state and push them in to the request
+ * queue so that the next start will use those buffers */
+ qObj = (Dss_DispDrvQueObj *) Fvid2Utils_dequeue(
+ instObj->bmObj.currQ);
+ while (NULL != qObj)
+ {
+ qObj->creditCnt = 0U;
+ /* Push it to the request queue */
+ Fvid2Utils_queueBack(instObj->bmObj.reqQ, &qObj->qElem, qObj);
+ qObj = (Dss_DispDrvQueObj *) Fvid2Utils_dequeue(
+ instObj->bmObj.currQ);
+ };
+
+ HwiP_restore(cookie);
+ }
+ }
+ else
+ {
+ instObj->drvState.isStopping = TRUE;
+ instObj->drvState.isStarted = FALSE;
+ retVal = Dss_dctrlDrvStopClient(instObj->dctrlHandle, TRUE);
+ }
+
+ if(FVID2_SOK != retVal)
+ {
+ GT_0trace(DssTrace, GT_ERR, "Fvid2 stop failed\r\n");
+ }
+
+ /* Post the instance semaphore */
+ (void) SemaphoreP_post(instObj->lockSem);
+
+ return (retVal);
+}
+
+static int32_t Dss_dispDrvSetDssParamsIoctl(Dss_DispDrvInstObj *instObj,
+ const Dss_DispParams *dispParams)
+{
+ int32_t retVal = FVID2_SOK;
+ uint32_t layerNum;
+ CSL_DssOverlayPipePosCfg overlayPosCfg;
+ CSL_dss_pipeRegs *pipeRegs;
+ CSL_dss_overlayRegs *overlayRegs;
+ const Dss_SocInfo *socInfo;
+ Dss_DctrlDrvPipeInfo *pipeInfo;
+ Dss_DispParams *pipeParams;
+
+ GT_assert(DssTrace, (NULL != instObj));
+
+ /* Check for wrong inputs */
+ if((instObj->drvInstId >= DSS_DISP_INST_MAX) || (NULL == dispParams))
+ {
+ GT_0trace(DssTrace, GT_ERR, "Invalid argument!!\r\n");
+ retVal = FVID2_EBADARGS;
+ }
+
+ /* Take the instance semaphore */
+ (void) SemaphoreP_pend(instObj->lockSem, SemaphoreP_WAIT_FOREVER);
+
+ if(FVID2_SOK == retVal)
+ {
+ pipeInfo = Dss_dctrlDrvGetPipeInfo(instObj->dctrlHandle);
+ pipeParams = &instObj->pipeParams[instObj->pipeId];
+
+ /* Get video pipe registers */
+ socInfo = Dss_getSocInfo();
+ pipeRegs = socInfo->pipeRegs[instObj->pipeId];
+ GT_assert(DssTrace, (NULL != pipeRegs));
+
+ /* Get overlay registers */
+ overlayRegs = socInfo->overlayRegs[pipeInfo->overlayId];
+ GT_assert(DssTrace, (NULL != overlayRegs));
+
+ retVal = Dss_dispDrvValidateDssParams(
+ (const Dss_DispDrvInstObj *)instObj,
+ (const Dss_DispParams *)dispParams);
+ }
+
+ if(FVID2_SOK == retVal)
+ {
+ Fvid2Utils_memcpy(pipeParams, dispParams, sizeof(Dss_DispParams));
+ retVal = CSL_dssVidPipeSetConfig(
+ pipeRegs,
+ (const CSL_DssVidPipeCfg *)(&dispParams->pipeCfg),
+ (const CSL_DssVidPipeVC1Cfg *)(&dispParams->vc1Cfg));
+ }
+
+ if(FVID2_SOK == retVal)
+ {
+ instObj->inScanFormat = dispParams->pipeCfg.inFmt.scanFormat;
+ CSL_dssVidPipeSetDmaConfig(
+ pipeRegs,
+ (const CSL_DssVidPipeDmaCfg *)(&dispParams->dmaCfg));
+
+ CSL_dssVidPipeSetAlphaConfig(
+ pipeRegs,
+ (const CSL_DssVidPipeAlphaCfg *)(&dispParams->alphaCfg));
+
+#if defined (SOC_J721E)
+ CSL_dssVidPipeSetCropConfig(
+ pipeRegs,
+ (const Fvid2_EdgeCropConfig *)(&dispParams->cropParams.cropCfg),
+ dispParams->cropParams.cropEnable);
+#endif
+
+ layerNum = CSL_dssOverlayGetEnabledPipeLayerNum(overlayRegs,
+ pipeInfo->pipeId);
+ GT_assert(DssTrace, (layerNum < CSL_DSS_OVERLAY_LAYER_MAX));
+ overlayPosCfg.layerPos.startX = dispParams->layerPos.startX;
+ overlayPosCfg.layerPos.startY = dispParams->layerPos.startY;
+ CSL_dssOverlaySetPipePosConfig(
+ overlayRegs,
+ (const CSL_DssOverlayPipePosCfg *)(&overlayPosCfg),
+ layerNum);
+ pipeInfo->startX = dispParams->layerPos.startX;
+ pipeInfo->startY = dispParams->layerPos.startY;
+ }
+
+ if(FVID2_SOK != retVal)
+ {
+ GT_0trace(DssTrace, GT_ERR, "Set DSS parameter IOCTL failed\r\n");
+ }
+
+ /* Post the instance semaphore */
+ (void) SemaphoreP_post(instObj->lockSem);
+
+ return (retVal);
+}
+
+static int32_t Dss_dispDrvSetMflagParamsIoctl(
+ Dss_DispDrvInstObj *instObj,
+ const Dss_DispPipeMflagParams *mflagParams)
+{
+ int32_t retVal = FVID2_SOK;
+ CSL_dss_pipeRegs *pipeRegs;
+ const Dss_SocInfo *socInfo;
+
+ GT_assert(DssTrace, (NULL != instObj));
+
+ /* Check for wrong inputs */
+ if((instObj->drvInstId >= DSS_DISP_INST_MAX) || (NULL == mflagParams))
+ {
+ GT_0trace(DssTrace, GT_ERR, "Invalid argument!!\r\n");
+ retVal = FVID2_EBADARGS;
+ }
+
+ /* Take the instance semaphore */
+ (void) SemaphoreP_pend(instObj->lockSem, SemaphoreP_WAIT_FOREVER);
+
+ if(FVID2_SOK == retVal)
+ {
+ /* Get video pipe registers */
+ socInfo = Dss_getSocInfo();
+ pipeRegs = socInfo->pipeRegs[instObj->pipeId];
+ GT_assert(DssTrace, (NULL != pipeRegs));
+
+ if(TRUE == instObj->drvState.isStarted)
+ {
+ retVal = FVID2_EDEVICE_INUSE;
+ GT_0trace(DssTrace,
+ GT_ERR,
+ "Cannot set MFLAG parameters while display is in use\r\n");
+ }
+
+ CSL_dssVidPipeSetMflagConfig(
+ pipeRegs,
+ (const CSL_DssVidPipeMFlagCfg *)(&mflagParams->mflagCfg));
+ }
+
+ if(FVID2_SOK != retVal)
+ {
+ GT_0trace(DssTrace, GT_ERR, "Set MFLAG parameters IOCTL failed\r\n");
+ }
+
+ /* Post the instance semaphore */
+ (void) SemaphoreP_post(instObj->lockSem);
+
+ return (retVal);
+}
+
+static int32_t Dss_dispDrvGetStatusIoctl(Dss_DispDrvInstObj *instObj,
+ Dss_DispCurrentStatus *dispStatus)
+{
+ int32_t retVal = FVID2_SOK;
+
+ GT_assert(DssTrace, (NULL != instObj));
+
+ /* Check for wrong inputs */
+ if((instObj->drvInstId >= DSS_DISP_INST_MAX) || (NULL == dispStatus))
+ {
+ GT_0trace(DssTrace, GT_ERR, "Invalid argument!!\r\n");
+ retVal = FVID2_EBADARGS;
+ }
+
+ /* Take the instance semaphore */
+ (void) SemaphoreP_pend(instObj->lockSem, SemaphoreP_WAIT_FOREVER);
+
+ if(FVID2_SOK == retVal)
+ {
+ Fvid2Utils_memcpy(dispStatus,
+ &instObj->currStatus,
+ sizeof(Dss_DispCurrentStatus));
+ }
+
+ if(FVID2_SOK != retVal)
+ {
+ GT_0trace(DssTrace, GT_ERR, "Get status IOCTL failed\r\n");
+ }
+
+ /* Post the instance semaphore */
+ (void) SemaphoreP_post(instObj->lockSem);
+
+ return (retVal);
+}
+
+static int32_t Dss_dispDrvSetPipeSafetyParamsIoctl(
+ Dss_DispDrvInstObj *instObj,
+ const Dss_DispPipeSafetyChkParams *safetyChkParams)
+{
+ int32_t retVal = FVID2_SOK;
+ uint32_t eventGroup, numHandle, evtMgrId, safetyEvt;
+ CSL_dss_pipeRegs *pipeRegs;
+ const Dss_SocInfo *socInfo;
+ const CSL_DssSafetyChkCfg *safetyChkCfg;
+
+ /* Check for NULL pointers */
+ GT_assert(DssTrace, (NULL != instObj));
+ /* Check for wrong inputs */
+ if((instObj->drvInstId >= DSS_DISP_INST_MAX) || (NULL == safetyChkParams))
+ {
+ GT_0trace(DssTrace, GT_ERR, "Invalid argument!!\r\n");
+ retVal = FVID2_EBADARGS;
+ }
+
+ /* Take the instance semaphore */
+ (void) SemaphoreP_pend(instObj->lockSem, SemaphoreP_WAIT_FOREVER);
+
+ if(FVID2_SOK == retVal)
+ {
+ /* Get video pipe registers */
+ socInfo = Dss_getSocInfo();
+ pipeRegs = socInfo->pipeRegs[instObj->pipeId];
+ GT_assert(DssTrace, (NULL != pipeRegs));
+
+ Fvid2Utils_memcpy(&instObj->safetyChkParams,
+ safetyChkParams,
+ sizeof (Dss_DispPipeSafetyChkParams));
+
+ /* Register for Safety Error Events */
+ Dss_convModuletoEventGroup(&eventGroup,
+ instObj->drvInstId,
+ DSS_EVENT_GROUP_TYPE_PIPE);
+ GT_assert(DssTrace, (DSS_EVENT_GROUP_INVALID != eventGroup));
+ safetyEvt = DSS_PIPE_EVENT_SAFETY_VIOLATION;
+ numHandle = instObj->numRegEvtHandle;
+ evtMgrId = Dss_getEvtMgrSafetyIntrId();
+ instObj->evtGroupHandle[instObj->numRegEvtHandle] =
+ Dss_evtMgrRegister(
+ evtMgrId,
+ eventGroup,
+ (const uint32_t *)&safetyEvt,
+ 1U,
+ Dss_dispSafetyErrCbFxn,
+ (void *)&gDss_DispEvtMgrClientInfo[numHandle]);
+ instObj->numRegEvtHandle++;
+
+ /* Call CSL APIs */
+ if(0U != safetyChkParams->safetySignSeedVal)
+ {
+ CSL_dssVidPipeSetSafetySignSeedVal(
+ pipeRegs,
+ safetyChkParams->safetySignSeedVal);
+ }
+ if(CSL_DSS_SAFETY_CHK_DATA_INTEGRITY ==
+ safetyChkParams->safetyChkCfg.safetyChkMode)
+ {
+ CSL_dssVidPipeSetSafetyReferenceSign(
+ pipeRegs,
+ safetyChkParams->referenceSign);
+ }
+ safetyChkCfg = &safetyChkParams->safetyChkCfg;
+ CSL_dssVidPipeSetSafetyChkConfig(pipeRegs, safetyChkCfg);
+ }
+
+ if(FVID2_SOK != retVal)
+ {
+ GT_0trace(DssTrace,
+ GT_ERR,
+ "Register Safety Error Cb Params IOCTL failed\r\n");
+ }
+
+ /* Post the instance semaphore */
+ (void) SemaphoreP_post(instObj->lockSem);
+
+ return retVal;
+}
+
+static int32_t Dss_dispDrvSetPipeCscParamsIoctl(
+ Dss_DispDrvInstObj *instObj,
+ const CSL_DssCscCoeff *cscCoeff)
+{
+ int32_t retVal = FVID2_SOK;
+ CSL_dss_pipeRegs *pipeRegs;
+ const Dss_SocInfo *socInfo;
+
+ GT_assert(DssTrace, (NULL != instObj));
+
+ /* Check for wrong inputs */
+ if((instObj->drvInstId >= DSS_DISP_INST_MAX) || (NULL == cscCoeff))
+ {
+ GT_0trace(DssTrace, GT_ERR, "Invalid argument!!\r\n");
+ retVal = FVID2_EBADARGS;
+ }
+
+ /* Take the instance semaphore */
+ (void) SemaphoreP_pend(instObj->lockSem, SemaphoreP_WAIT_FOREVER);
+
+ if(FVID2_SOK == retVal)
+ {
+ /* Get video pipe registers */
+ socInfo = Dss_getSocInfo();
+ pipeRegs = socInfo->pipeRegs[instObj->pipeId];
+ GT_assert(DssTrace, (NULL != pipeRegs));
+
+ CSL_dssVidPipeSetCSCCoeff(
+ pipeRegs,
+ (const CSL_DssCscCoeff *)(cscCoeff));
+ }
+
+ if(FVID2_SOK != retVal)
+ {
+ GT_0trace(DssTrace, GT_ERR, "Set CSC coefficients IOCTL failed\r\n");
+ }
+
+ /* Post the instance semaphore */
+ (void) SemaphoreP_post(instObj->lockSem);
+
+ return (retVal);
+}
+
+static int32_t Dss_dispDrvSetBufPrgmCbParamsIoctl(
+ Dss_DispDrvInstObj *instObj,
+ const Dss_DispBufPrgmCbParams *bufPrgmCbParams)
+{
+ int32_t retVal = FVID2_SOK;
+
+ /* Check for NULL pointers */
+ GT_assert(DssTrace, (NULL != instObj));
+
+ /* Check for wrong inputs */
+ if((instObj->drvInstId >= DSS_DISP_INST_MAX) || (NULL == bufPrgmCbParams))
+ {
+ GT_0trace(DssTrace, GT_ERR, "Invalid argument!!\r\n");
+ retVal = FVID2_EBADARGS;
+ }
+
+ /* Take the instance semaphore */
+ (void) SemaphoreP_pend(instObj->lockSem, SemaphoreP_WAIT_FOREVER);
+
+ if(FVID2_SOK == retVal)
+ {
+ /* IOCTL supported only when display is stopped */
+ if(TRUE == instObj->drvState.isStarted)
+ {
+ GT_0trace(DssTrace, GT_ERR, "Display in progress!!\r\n");
+ retVal = FVID2_EFAIL;
+ }
+ }
+
+ if(FVID2_SOK == retVal)
+ {
+ instObj->bufPrgmCbParams.bufPrgmCbFxn = bufPrgmCbParams->bufPrgmCbFxn;
+ }
+
+ if(FVID2_SOK != retVal)
+ {
+ GT_0trace(DssTrace,
+ GT_ERR,
+ "Set buffer program callback IOCTL failed\r\n");
+ }
+
+ /* Post the instance semaphore */
+ (void) SemaphoreP_post(instObj->lockSem);
+
+ return (retVal);
+}
+
+static int32_t Dss_dispDrvSetPipePrgmCbParamsIoctl(
+ Dss_DispDrvInstObj *instObj,
+ const Dss_DispPipePrgmCbParams *pipePrgmCbParams)
+{
+ int32_t retVal = FVID2_SOK;
+
+ /* Check for NULL pointers */
+ GT_assert(DssTrace, (NULL != instObj));
+
+ /* Check for wrong inputs */
+ if((instObj->drvInstId >= DSS_DISP_INST_MAX) || (NULL == pipePrgmCbParams))
+ {
+ GT_0trace(DssTrace, GT_ERR, "Invalid argument!!\r\n");
+ retVal = FVID2_EBADARGS;
+ }
+
+ /* Take the instance semaphore */
+ (void) SemaphoreP_pend(instObj->lockSem, SemaphoreP_WAIT_FOREVER);
+
+ if(FVID2_SOK == retVal)
+ {
+ /* IOCTL supported only when display is stopped */
+ if(TRUE == instObj->drvState.isStarted)
+ {
+ GT_0trace(DssTrace, GT_ERR, "Display in progress!!\r\n");
+ retVal = FVID2_EFAIL;
+ }
+ }
+
+ if(FVID2_SOK == retVal)
+ {
+ Fvid2Utils_memcpy(&instObj->pipePrgmCbParams,
+ pipePrgmCbParams,
+ sizeof (Dss_DispPipePrgmCbParams));
+ }
+
+ if(FVID2_SOK != retVal)
+ {
+ GT_0trace(DssTrace,
+ GT_ERR,
+ "Set pipe program callback IOCTL failed\r\n");
+ }
+
+ /* Post the instance semaphore */
+ (void) SemaphoreP_post(instObj->lockSem);
+
+ return (retVal);
+}
+
+static int32_t Dss_dispDrvSetPipeUnderFlowCbParamsIoctl(
+ Dss_DispDrvInstObj *instObj,
+ const Dss_DispUnderFlowCbParams *underFlowCbParams)
+{
+ int32_t retVal = FVID2_SOK;
+
+ /* Check for NULL pointers */
+ GT_assert(DssTrace, (NULL != instObj));
+
+ /* Check for wrong inputs */
+ if((instObj->drvInstId >= DSS_DISP_INST_MAX) || (NULL == underFlowCbParams))
+ {
+ GT_0trace(DssTrace, GT_ERR, "Invalid argument!!\r\n");
+ retVal = FVID2_EBADARGS;
+ }
+
+ /* Take the instance semaphore */
+ (void) SemaphoreP_pend(instObj->lockSem, SemaphoreP_WAIT_FOREVER);
+
+ if(FVID2_SOK == retVal)
+ {
+ /* IOCTL supported only when display is stopped */
+ if(TRUE == instObj->drvState.isStarted)
+ {
+ GT_0trace(DssTrace, GT_ERR, "Display in progress!!\r\n");
+ retVal = FVID2_EFAIL;
+ }
+ }
+
+ if(FVID2_SOK == retVal)
+ {
+ Fvid2Utils_memcpy(&instObj->underFlowCbParams,
+ underFlowCbParams,
+ sizeof (Dss_DispUnderFlowCbParams));
+ }
+
+ if(FVID2_SOK != retVal)
+ {
+ GT_0trace(DssTrace,
+ GT_ERR,
+ "Set pipe underflow callback IOCTL failed\r\n");
+ }
+
+ /* Post the instance semaphore */
+ (void) SemaphoreP_post(instObj->lockSem);
+
+ return (retVal);
+}
+
+static int32_t Dss_dispDrvValidateDssParams(const Dss_DispDrvInstObj *instObj,
+ const Dss_DispParams *dispParams)
+{
+ int32_t retVal = FVID2_SOK;
+
+ if((FALSE == Dss_dispIsVidInst(instObj->drvInstId)) &&
+ (FALSE == Dss_dispIsVidLInst(instObj->drvInstId)))
+ {
+ GT_0trace(DssTrace,
+ GT_ERR,
+ "Invalid Driver Id\r\n");
+ retVal = FVID2_EINVALID_PARAMS;
+ }
+ if(((dispParams->pipeCfg.outWidth + dispParams->layerPos.startX) >
+ instObj->dispWidth) ||
+ ((dispParams->pipeCfg.outHeight + dispParams->layerPos.startY) >
+ instObj->dispHeight))
+ {
+ GT_0trace(DssTrace,
+ GT_ERR,
+ "Input width+startX/height+startY > display width/height\r\n");
+ retVal = FVID2_EINVALID_PARAMS;
+ }
+
+ /* Interlaced to progressive or vice versa*/
+ if(dispParams->pipeCfg.inFmt.scanFormat != instObj->dispScanFormat)
+ {
+ GT_0trace(DssTrace,
+ GT_ERR,
+ "Format(interlaced/progressive) conversion not supported\r\n");
+ retVal = FVID2_EINVALID_PARAMS;
+ }
+
+ /* Scaling ratio check */
+ if(((dispParams->pipeCfg.inFmt.height * 16U) <
+ (dispParams->pipeCfg.outHeight)) ||
+ ((dispParams->pipeCfg.inFmt.width * 16U) <
+ (dispParams->pipeCfg.outWidth)))
+ {
+ GT_0trace(DssTrace,
+ GT_ERR,
+ "Upscaling ratio is more than 16x \r\n");
+ retVal = FVID2_EINVALID_PARAMS;
+ }
+ if(((dispParams->pipeCfg.inFmt.height) >
+ (dispParams->pipeCfg.outHeight * 4U)) ||
+ ((dispParams->pipeCfg.inFmt.width) >
+ (dispParams->pipeCfg.outWidth * 4U)))
+ {
+ GT_0trace(DssTrace,
+ GT_ERR,
+ "Downscaling ratio is more than 0.25x \r\n");
+ retVal = FVID2_EINVALID_PARAMS;
+ }
+
+ if((dispParams->pipeCfg.inFmt.height != dispParams->pipeCfg.outHeight) ||
+ (dispParams->pipeCfg.inFmt.width != dispParams->pipeCfg.outWidth))
+ {
+ if(TRUE == Dss_dispIsVidLInst(instObj->drvInstId))
+ {
+ GT_0trace(DssTrace,
+ GT_ERR,
+ "Scaling cant be enabled for video lite pipe \r\n");
+ retVal = FVID2_EINVALID_PARAMS;
+ }
+ if(FALSE == dispParams->pipeCfg.scEnable)
+ {
+ GT_0trace(DssTrace,
+ GT_ERR,
+ "Scaling should be enabled \r\n");
+ retVal = FVID2_EINVALID_PARAMS;
+ }
+ }
+
+ if((dispParams->cropParams.cropCfg.cropTop >= 32U) ||
+ (dispParams->cropParams.cropCfg.cropBottom >= 32U) ||
+ (dispParams->cropParams.cropCfg.cropLeft >= 32U) ||
+ (dispParams->cropParams.cropCfg.cropRight >= 32U))
+ {
+ GT_0trace(DssTrace,
+ GT_ERR,
+ "Crop Parameter(s) should be less than 32 \r\n");
+ retVal = FVID2_EINVALID_PARAMS;
+ }
+
+ if(((dispParams->pipeCfg.flipType == FVID2_FLIP_TYPE_V) ||
+ (dispParams->pipeCfg.flipType == FVID2_FLIP_TYPE_H)) &&
+ ((dispParams->pipeCfg.inFmt.dataFormat == FVID2_DF_RGB24_888) ||
+ (dispParams->pipeCfg.inFmt.dataFormat == FVID2_DF_BGR24_888)))
+ {
+ GT_0trace(DssTrace,
+ GT_ERR,
+ "Flip Parameter(s) should not be used for 24-bit RGB/BGR formats \r\n");
+ retVal = FVID2_EINVALID_PARAMS;
+ }
+
+ /* There is a limitation with scaling in DSS, where maximum scaling ratio
+ * supported is the ratio of the DSS functional clock and Pixel Clock.
+ * Driver can't check this condition as it is unaware of Pixel Clock.
+ * So it should be checked by the application.
+ */
+ return retVal;
+}
+
+static int32_t Dss_dispDrvValidateRtParams(const Dss_DispDrvInstObj *instObj,
+ const Dss_DispRtParams *rtParams)
+{
+ int32_t retVal = FVID2_SOK;
+ const Dss_DispParams *pipeParams;
+ const Dss_FrameRtParams *frameRtParams;
+
+ if(NULL != rtParams->outFrmParams)
+ {
+ if(((rtParams->outFrmParams->width + rtParams->posCfg->startX) >
+ instObj->dispWidth) ||
+ ((rtParams->outFrmParams->height + rtParams->posCfg->startY) >
+ instObj->dispHeight))
+ {
+ retVal = FVID2_EINVALID_PARAMS;
+ }
+ }
+
+ if((NULL != rtParams->outFrmParams) && (NULL != rtParams->inFrmParams))
+ {
+ /* Scaling ratio check */
+ if(((rtParams->inFrmParams->height * 16U) <
+ (rtParams->outFrmParams->height)) ||
+ ((rtParams->inFrmParams->width * 16U) <
+ (rtParams->outFrmParams->width)))
+ {
+ retVal = FVID2_EINVALID_PARAMS;
+ }
+ if(((rtParams->inFrmParams->height) >
+ (rtParams->outFrmParams->height * 4U)) ||
+ ((rtParams->inFrmParams->width) >
+ (rtParams->outFrmParams->width * 4U)))
+ {
+ retVal = FVID2_EINVALID_PARAMS;
+ }
+ if((rtParams->inFrmParams->height != rtParams->outFrmParams->height) ||
+ (rtParams->inFrmParams->width != rtParams->outFrmParams->width))
+ {
+ if(TRUE == Dss_dispIsVidLInst(instObj->drvInstId))
+ {
+ retVal = FVID2_EINVALID_PARAMS;
+ }
+ }
+ }
+
+ if(NULL != rtParams->inFrmParams)
+ {
+ pipeParams = &instObj->pipeParams[instObj->pipeId];
+ frameRtParams = rtParams->inFrmParams;
+ if(((pipeParams->pipeCfg.flipType == FVID2_FLIP_TYPE_V) ||
+ (pipeParams->pipeCfg.flipType == FVID2_FLIP_TYPE_H)) &&
+ ((frameRtParams->dataFormat == FVID2_DF_RGB24_888) ||
+ (frameRtParams->dataFormat == FVID2_DF_BGR24_888)))
+ {
+ GT_0trace(DssTrace,
+ GT_ERR,
+ "Flip Parameter(s) should not be used for 24-bit RGB/BGR formats \r\n");
+ retVal = FVID2_EINVALID_PARAMS;
+ }
+ }
+
+ /* There is a limitation with scaling in DSS, where maximum scaling ratio
+ * supported is the ratio of the DSS functional clock and Pixel Clock.
+ * Driver can't check this condition as it is unaware of Pixel Clock.
+ * So it should be checked by the application.
+ */
+ return retVal;
+}
+
+static int32_t Dss_dispDrvApplyRtParams(Dss_DispDrvInstObj *instObj,
+ const Dss_DispRtParams *rtParams)
+{
+ int32_t rtParamsRetVal = FVID2_SOK;
+ uint32_t i, layerNum;
+ CSL_dss_pipeRegs *pipeRegs;
+ CSL_dss_overlayRegs *overlayRegs;
+ const Dss_SocInfo *socInfo;
+ uint32_t pipeRtUpdate = FALSE;
+ Dss_DctrlDrvPipeInfo *pipeInfo;
+ CSL_DssOverlayPipePosCfg overlayPosCfg;
+ Dss_DispParams *pipeParams;
+
+ /* Get video pipe registers */
+ socInfo = Dss_getSocInfo();
+ pipeRegs = socInfo->pipeRegs[instObj->pipeId];
+ GT_assert(DssTrace, (NULL != pipeRegs));
+
+ pipeParams = &instObj->pipeParams[instObj->pipeId];
+ if(NULL != rtParams->scParams)
+ {
+ pipeRtUpdate = TRUE;
+ pipeParams->pipeCfg.pixelInc = rtParams->scParams->pixelInc;
+ }
+ if(NULL != rtParams->inFrmParams)
+ {
+ pipeRtUpdate = TRUE;
+ pipeParams->pipeCfg.inFmt.width = rtParams->inFrmParams->width;
+ pipeParams->pipeCfg.inFmt.height = rtParams->inFrmParams->height;
+ pipeParams->pipeCfg.inFmt.dataFormat =
+ rtParams->inFrmParams->dataFormat;
+ for(i=0U; i<FVID2_MAX_PLANES; i++)
+ {
+ pipeParams->pipeCfg.inFmt.pitch[i] =
+ rtParams->inFrmParams->pitch[i];
+ }
+ }
+ if((NULL != rtParams->outFrmParams) &&
+ (TRUE == Dss_dispIsVidInst(instObj->drvInstId)))
+ {
+ pipeRtUpdate = TRUE;
+ pipeParams->pipeCfg.outWidth = rtParams->outFrmParams->width;
+ pipeParams->pipeCfg.outHeight = rtParams->outFrmParams->height;
+ }
+ if(TRUE == pipeRtUpdate)
+ {
+ rtParamsRetVal =
+ CSL_dssVidPipeSetConfig(
+ pipeRegs,
+ (const CSL_DssVidPipeCfg *)(&pipeParams->pipeCfg),
+ (const CSL_DssVidPipeVC1Cfg *)(&pipeParams->vc1Cfg));
+ GT_assert(DssTrace, (FVID2_SOK == rtParamsRetVal));
+ }
+ if(NULL != rtParams->posCfg)
+ {
+ pipeInfo = Dss_dctrlDrvGetPipeInfo(instObj->dctrlHandle);
+ /* Get overlay registers */
+ overlayRegs = socInfo->overlayRegs[pipeInfo->overlayId];
+ GT_assert(DssTrace, (NULL != overlayRegs));
+ layerNum = CSL_dssOverlayGetEnabledPipeLayerNum(overlayRegs,
+ pipeInfo->pipeId);
+ GT_assert(DssTrace, (layerNum < CSL_DSS_OVERLAY_LAYER_MAX));
+ overlayPosCfg.layerPos.startX = rtParams->posCfg->startX;
+ overlayPosCfg.layerPos.startY = rtParams->posCfg->startY;
+ CSL_dssOverlaySetPipePosConfig(
+ overlayRegs,
+ (const CSL_DssOverlayPipePosCfg *)(&overlayPosCfg),
+ layerNum);
+ pipeInfo->startX = rtParams->posCfg->startX;
+ pipeInfo->startY = rtParams->posCfg->startY;
+ }
+ return rtParamsRetVal;
+}
+
+static void Dss_dispSafetyErrCbFxn(const uint32_t *event,
+ uint32_t numEvents,
+ void *arg)
+{
+ uint32_t i, currEvent, pipeId = 0U;
+ Dss_EvtMgrClientInfo *pClientObj = (Dss_EvtMgrClientInfo *)arg;
+ uint32_t eventGroup = pClientObj->eventGroup;
+ Dss_DispDrvInstObj *instObj;
+ CSL_dss_pipeRegs *pipeRegs;
+ const Dss_SocInfo *socInfo;
+
+ /* Get pipe id */
+ Dss_convEventGrouptoModule(eventGroup, &pipeId);
+ GT_assert(DssTrace, (CSL_DSS_MODULE_INVALID != pipeId));
+ instObj = Dss_dispDrvGetInstObj(pipeId);
+ /* Instobj cannot be NULL */
+ GT_assert(DssTrace, (NULL != instObj));
+ /* Get video pipe registers */
+ socInfo = Dss_getSocInfo();
+ pipeRegs = socInfo->pipeRegs[pipeId];
+ GT_assert(DssTrace, (NULL != pipeRegs));
+
+ for(i=0U; i<numEvents; i++)
+ {
+ currEvent = event[i];
+ if(DSS_PIPE_EVENT_SAFETY_VIOLATION == currEvent)
+ {
+ instObj->currStatus.safetyViolationCount++;
+ if(CSL_DSS_SAFETY_CHK_DATA_INTEGRITY ==
+ instObj->safetyChkParams.safetyChkCfg.safetyChkMode)
+ {
+ instObj->safetyChkParams.capturedSign =
+ CSL_dssVidPipeGetSafetySign(pipeRegs);
+ }
+ if(NULL != instObj->safetyChkParams.safetyErrCbFxn)
+ {
+ instObj->safetyChkParams.safetyErrCbFxn(
+ instObj->safetyChkParams.capturedSign,
+ instObj->safetyChkParams.appData);
+ }
+ }
+ else
+ {
+ GT_assert(DssTrace, FALSE);
+ }
+ }
+
+ return;
+}
+
+static uint32_t Dss_dispIsFarFromVsync(const Dss_DispDrvInstObj *instObj)
+{
+ uint32_t isFarFromVsync = FALSE;
+
+ isFarFromVsync = Dss_dctrlDrvIsSafeToPush(instObj->dctrlHandle);
+
+ if(instObj->dispHeight <= DSS_DISP_NUM_LINES_NEAR_VSYNC)
+ {
+ isFarFromVsync = FALSE;
+ }
+
+ return isFarFromVsync;
+}
diff --git a/packages/ti/drv/dss/src/drv/disp/dss_dispDrv.h b/packages/ti/drv/dss/src/drv/disp/dss_dispDrv.h
--- /dev/null
@@ -0,0 +1,117 @@
+/*
+ * Copyright (c) Texas Instruments Incorporated 2018
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * \file dss_dispDrv.h
+ *
+ * \brief DSS Display driver internal interface file.
+ */
+
+#ifndef DSS_DISPDRV_H_
+#define DSS_DISPDRV_H_
+
+/* ========================================================================== */
+/* Include Files */
+/* ========================================================================== */
+
+/* None */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* ========================================================================== */
+/* Macros & Typedefs */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/* Structure Declarations */
+/* ========================================================================== */
+
+/**
+ * \brief DSS Display Driver initialization parameters.
+ */
+typedef struct
+{
+ uint32_t drvInstId;
+ /**< Driver Instance Id */
+} Dss_DispDrvInitParams;
+
+/* ========================================================================== */
+/* Internal/Private Function Declarations */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/* Function Declarations */
+/* ========================================================================== */
+
+/**
+ * \brief DSS display driver initialization function.
+ * This function gets called as a part of Dss_init(). It Initializes internal
+ * data structures and common system level resources related to display.
+ *
+ * \param numInst Number of instance objects to be initialized.
+ * \param drvInitParams Pointer to a #Dss_DispDrvInitParams structure
+ * containing the driver init configuration
+ *
+ * \return FVID2_SOK if successful, else suitable error code
+ */
+int32_t Dss_dispDrvInit(uint32_t numInst,
+ const Dss_DispDrvInitParams *drvInitParams);
+
+/**
+ * \brief DSS display driver de-initialization function.
+ *
+ * This API free all resources allocated during Dss_dispDrvInit().
+ *
+ * \param None
+ *
+ * \return FVID2_SOK if successful, else suitable error code
+ */
+int32_t Dss_dispDrvDeInit(void);
+
+/* ========================================================================== */
+/* Static Function Definitions */
+/* ========================================================================== */
+
+/* None */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #ifndef DSS_DISPDRV_H_ */
diff --git a/packages/ti/drv/dss/src/drv/disp/dss_dispPriv.c b/packages/ti/drv/dss/src/drv/disp/dss_dispPriv.c
--- /dev/null
@@ -0,0 +1,427 @@
+/*
+ * Copyright (c) Texas Instruments Incorporated 2018
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * \file dss_dispPriv.c
+ *
+ * \brief File containing the DSS display driver private APIs.
+ *
+ */
+
+/* ========================================================================== */
+/* Include Files */
+/* ========================================================================== */
+
+#include <ti/drv/dss/dss.h>
+#include <ti/drv/dss/src/drv/common/dss_evtMgr.h>
+#include <ti/drv/dss/src/drv/disp/dss_dispDrv.h>
+#include <ti/drv/dss/src/drv/disp/dss_dispPriv.h>
+
+/* ========================================================================== */
+/* Macros & Typedefs */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/* Structure Declarations */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/* Function Declarations */
+/* ========================================================================== */
+
+static void Dss_dispErrCbFxn(const uint32_t *event,
+ uint32_t numEvents,
+ void *arg);
+
+/* ========================================================================== */
+/* Global Variables */
+/* ========================================================================== */
+
+Dss_DispDrvCommonObj gDss_DispDrvCommonObj;
+Dss_DispDrvInstObj gDss_DispDrvInstObj[CSL_DSS_VID_PIPE_ID_MAX];
+Dss_EvtMgrClientInfo gDss_DispEvtMgrClientInfo[DSS_DISP_EVT_MGR_MAX_CLIENTS];
+
+/* ========================================================================== */
+/* Function Definitions */
+/* ========================================================================== */
+
+int32_t Dss_dispDrvPrivInit(uint32_t numInst,
+ const Dss_DispDrvInitParams *initParams)
+{
+ int32_t retVal = FVID2_SOK;
+ uint32_t instCnt;
+ uint32_t i, eventGroup, numHandle, numEvents, evtMgrId;
+ uint32_t enabledEvents[DSS_EVT_MGR_MAX_CLIENT_EVENTS];
+ Dss_DispDrvInstObj *instObj;
+ Dss_DispDrvCommonObj *pObj;
+ Dss_EvtMgrClientInfo *pClientInfo;
+ SemaphoreP_Params semParams;
+
+ /* Check for errors */
+ GT_assert(DssTrace, (numInst <= DSS_DISP_INST_MAX));
+ GT_assert(DssTrace, (NULL != initParams));
+
+ /* Initialize common object */
+ pObj = &gDss_DispDrvCommonObj;
+ Fvid2Utils_memset(pObj, 0U, sizeof (Dss_DispDrvCommonObj));
+
+ /* Initialize instance object members */
+ if(numInst > CSL_DSS_VID_PIPE_ID_MAX)
+ {
+ /* Number of instances exceeds the global variable used to store the
+ * instance object */
+ GT_0trace(DssTrace,
+ GT_ERR,
+ "Number of instances exceeds the global array size!!\r\n");
+ retVal = FVID2_EALLOC;
+ }
+ else
+ {
+ pObj->instObj = &gDss_DispDrvInstObj[0];
+ Fvid2Utils_memset(pObj->instObj, 0U, sizeof (gDss_DispDrvInstObj));
+ for(i=0U; i<DSS_DISP_EVT_MGR_MAX_CLIENTS; i++)
+ {
+ pClientInfo = &gDss_DispEvtMgrClientInfo[i];
+ Fvid2Utils_memset(pClientInfo, 0U, sizeof (Dss_EvtMgrClientInfo));
+ }
+ }
+
+ if(FVID2_SOK == retVal)
+ {
+ pObj->numInst = numInst;
+ instObj = pObj->instObj;
+ for(instCnt=0U; instCnt<numInst; instCnt++)
+ {
+ /* Copy the information */
+ instObj->drvInstId = initParams->drvInstId;
+
+ /* Allocate instance semaphore */
+ SemaphoreP_Params_init(&semParams);
+ semParams.mode = SemaphoreP_Mode_BINARY;
+ instObj->lockSem = SemaphoreP_create(1U, &semParams);
+ if(NULL == instObj->lockSem)
+ {
+ GT_0trace(DssTrace,
+ GT_ERR,
+ "Instance semaphore create failed!!\r\n");
+ retVal = FVID2_EALLOC;
+ break;
+ }
+
+ if(FVID2_SOK == retVal)
+ {
+ Dss_convModuletoEventGroup(&eventGroup,
+ instObj->drvInstId,
+ DSS_EVENT_GROUP_TYPE_PIPE);
+ GT_assert(DssTrace, (DSS_EVENT_GROUP_INVALID != eventGroup));
+
+ /* Register functional events */
+ Dss_getEnabledPipeErrEvents(&enabledEvents[0U], &numEvents);
+ evtMgrId = Dss_getEvtMgrFuncIntrId();
+ numHandle = instObj->numRegEvtHandle;
+ instObj->evtGroupHandle[instObj->numRegEvtHandle] =
+ Dss_evtMgrRegister(
+ evtMgrId,
+ eventGroup,
+ (const uint32_t *)&enabledEvents[0U],
+ numEvents,
+ Dss_dispErrCbFxn,
+ (void *)&gDss_DispEvtMgrClientInfo[numHandle]);
+ instObj->numRegEvtHandle++;
+ }
+
+ instObj->drvState.isInit = TRUE;
+ instObj->drvState.isOpened = FALSE;
+ instObj->drvState.isStarted = FALSE;
+ instObj->drvState.isStarting = FALSE;
+ instObj->drvState.isStopping = FALSE;
+
+ initParams++;
+ instObj++;
+ }
+ }
+
+ if(FVID2_SOK != retVal)
+ {
+ /* Un initialize the internal objects if error occurs */
+ retVal += Dss_dispDrvPrivDeInit();
+ }
+
+ return (retVal);
+}
+
+int32_t Dss_dispDrvPrivDeInit(void)
+{
+ int32_t retVal = FVID2_SOK;
+ uint32_t instCnt, cnt, numRegEvtHandle;
+ Dss_DispDrvInstObj *instObj;
+ Dss_DispDrvCommonObj *pObj;
+
+ pObj = &gDss_DispDrvCommonObj;
+ if(NULL != pObj->instObj)
+ {
+ instObj = pObj->instObj;
+ for(instCnt=0U; instCnt<pObj->numInst; instCnt++)
+ {
+ if(TRUE == instObj->drvState.isOpened)
+ {
+ GT_0trace(DssTrace, GT_ERR,
+ "Can't de-initialize when an instance is active\r\n");
+ retVal = FVID2_EFAIL;
+ break;
+ }
+
+ /* Delete the instance semaphore */
+ if(NULL != instObj->lockSem)
+ {
+ SemaphoreP_delete(instObj->lockSem);
+ instObj->lockSem = NULL;
+ }
+
+ instObj->drvState.isInit = FALSE;
+ numRegEvtHandle = instObj->numRegEvtHandle;
+ /* Unregister event groups and delete object */
+ for(cnt=0U; cnt<numRegEvtHandle; cnt++)
+ {
+ retVal += Dss_evtMgrUnRegister(instObj->evtGroupHandle[cnt]);
+ instObj->numRegEvtHandle--;
+ }
+ Fvid2Utils_memset(pObj->instObj, 0U, sizeof (Dss_DispDrvInstObj));
+
+ instObj++;
+ }
+ if(retVal == FVID2_SOK)
+ {
+ pObj->instObj = NULL;
+ pObj->numInst = 0U;
+ }
+ }
+ return (retVal);
+}
+
+Dss_DispDrvInstObj *Dss_dispDrvGetInstObj(uint32_t instId)
+{
+ uint32_t instCnt;
+ Dss_DispDrvInstObj *instObj = NULL;
+ Dss_DispDrvCommonObj *pObj;
+
+ /* Find out the instance */
+ pObj = &gDss_DispDrvCommonObj;
+ GT_assert(DssTrace, (NULL != pObj));
+ GT_assert(DssTrace, (NULL != pObj->instObj));
+ for(instCnt=0U; instCnt<pObj->numInst; instCnt++)
+ {
+ if((TRUE == pObj->instObj[instCnt].drvState.isInit) &&
+ (pObj->instObj[instCnt].drvInstId == instId))
+ {
+ instObj = &pObj->instObj[instCnt];
+ break;
+ }
+ }
+
+ return (instObj);
+}
+
+int32_t Dss_dispDrvCreateInstObj(Dss_DispDrvInstObj *instObj)
+{
+ int32_t retVal = FVID2_SOK, tempRetVal;
+ uint32_t qCnt;
+ Dss_DispDrvBufManObj *bmObj;
+ Dss_DispDrvQueObj *qObj;
+
+ GT_assert(DssTrace, (NULL != instObj));
+ bmObj = &instObj->bmObj;
+
+ instObj->bufPrgmCbParams.bufPrgmCbFxn = NULL;
+ instObj->currStatus.queueCount = 0U;
+ instObj->currStatus.dequeueCount = 0U;
+ instObj->currStatus.dispFrmCount = 0U;
+ instObj->currStatus.repeatFrmCount = 0U;
+ instObj->currStatus.underflowCount = 0U;
+ instObj->currStatus.safetyViolationCount = 0U;
+
+ bmObj->isProgressive = TRUE;
+ bmObj->curFid = 0U;
+ bmObj->expectedFid = 0U;
+ bmObj->fieldMerged = TRUE;
+ bmObj->freeQ = NULL;
+ bmObj->reqQ = NULL;
+ bmObj->currQ = NULL;
+ bmObj->doneQ = NULL;
+
+ /* Create Queues */
+ retVal = Fvid2Utils_constructQ(&bmObj->freeLlObj);
+ GT_assert(DssTrace, (retVal == FVID2_SOK));
+ bmObj->freeQ = &bmObj->freeLlObj;
+
+ retVal = Fvid2Utils_constructQ(&bmObj->reqLlObj);
+ GT_assert(DssTrace, (retVal == FVID2_SOK));
+ bmObj->reqQ = &bmObj->reqLlObj;
+
+ retVal = Fvid2Utils_constructQ(&bmObj->curLlObj);
+ GT_assert(DssTrace, (retVal == FVID2_SOK));
+ bmObj->currQ = &bmObj->curLlObj;
+
+ retVal = Fvid2Utils_constructQ(&bmObj->doneLlObj);
+ GT_assert(DssTrace, (retVal == FVID2_SOK));
+ bmObj->doneQ = &bmObj->doneLlObj;
+
+ if(FVID2_SOK == retVal)
+ {
+ /* Initialize and queue the allocate queue object to free Q */
+ for(qCnt=0U; qCnt<DSS_DEF_QUEUE_LEN_PER_INST; qCnt++)
+ {
+ qObj = &bmObj->dispQObj[qCnt];
+ qObj->instObj = instObj;
+ qObj->frm = NULL;
+ qObj->creditCnt = 0U;
+ Fvid2Utils_queue(bmObj->freeQ, &qObj->qElem, qObj);
+ }
+ }
+
+ /* Deallocate if error occurs */
+ if(FVID2_SOK != retVal)
+ {
+ tempRetVal = Dss_dispDrvDeleteInstObj(instObj);
+ GT_assert(DssTrace, (FVID2_SOK == tempRetVal));
+ }
+
+ return (retVal);
+}
+
+int32_t Dss_dispDrvDeleteInstObj(Dss_DispDrvInstObj *instObj)
+{
+ int32_t retVal = FVID2_SOK;
+ Dss_DispDrvQueObj *qObj;
+ Dss_DispDrvBufManObj *bmObj;
+
+ /* NULL pointer check */
+ GT_assert(DssTrace, (NULL != instObj));
+ bmObj = &instObj->bmObj;
+
+ bmObj->isProgressive = TRUE;
+ bmObj->curFid = 0U;
+ bmObj->expectedFid = 0U;
+ bmObj->fieldMerged = TRUE;
+
+ if(NULL != bmObj->freeQ)
+ {
+ /* Free-up all the queued free queue objects */
+ do
+ {
+ qObj = (Dss_DispDrvQueObj *) Fvid2Utils_dequeue(bmObj->freeQ);
+ } while (NULL != qObj);
+
+ /* Delete the free Q */
+ Fvid2Utils_destructQ(bmObj->freeQ);
+ bmObj->freeQ = NULL;
+ }
+
+ if(NULL != bmObj->reqQ)
+ {
+ /* Free-up all object from request queue */
+ do
+ {
+ qObj = (Dss_DispDrvQueObj *) Fvid2Utils_dequeue(bmObj->reqQ);
+ } while (NULL != qObj);
+
+ /* Delete the request Q */
+ Fvid2Utils_destructQ(bmObj->reqQ);
+ bmObj->reqQ = NULL;
+ }
+
+ if(NULL != bmObj->currQ)
+ {
+ /* Free-up all object from current queue */
+ do
+ {
+ qObj = (Dss_DispDrvQueObj *) Fvid2Utils_dequeue(bmObj->currQ);
+ } while (NULL != qObj);
+
+ /* Delete the free Q */
+ Fvid2Utils_destructQ(bmObj->currQ);
+ bmObj->currQ = NULL;
+ }
+
+ if(NULL != bmObj->doneQ)
+ {
+ /* Free-up all object from done queue */
+ do
+ {
+ qObj = (Dss_DispDrvQueObj *) Fvid2Utils_dequeue(bmObj->doneQ);
+ } while (NULL != qObj);
+
+ /* Delete the done Q */
+ Fvid2Utils_destructQ(bmObj->doneQ);
+ bmObj->doneQ = NULL;
+ }
+
+ return (retVal);
+}
+
+static void Dss_dispErrCbFxn(const uint32_t *event,
+ uint32_t numEvents,
+ void *arg)
+{
+ uint32_t i, currEvent, pipeId = 0U;
+ Dss_EvtMgrClientInfo *pClientObj = (Dss_EvtMgrClientInfo *)arg;
+ uint32_t eventGroup = pClientObj->eventGroup;
+ Dss_DispDrvInstObj *instObj;
+
+ Dss_convEventGrouptoModule(eventGroup, &pipeId);
+ GT_assert(DssTrace, (CSL_DSS_MODULE_INVALID != pipeId));
+ instObj = &gDss_DispDrvInstObj[pipeId];
+ for(i=0U; i<numEvents; i++)
+ {
+ currEvent = event[i];
+ if(DSS_PIPE_EVENT_BUFF_UNDERFLOW == currEvent)
+ {
+ instObj->currStatus.underflowCount++;
+ if(NULL != instObj->underFlowCbParams.underFlowCbFxn)
+ {
+ instObj->underFlowCbParams.underFlowCbFxn(
+ instObj->underFlowCbParams.appData);
+ }
+ }
+ else
+ {
+ GT_assert(DssTrace, FALSE);
+ }
+ }
+
+ return;
+}
diff --git a/packages/ti/drv/dss/src/drv/disp/dss_dispPriv.h b/packages/ti/drv/dss/src/drv/disp/dss_dispPriv.h
--- /dev/null
@@ -0,0 +1,271 @@
+/*
+ * Copyright (c) Texas Instruments Incorporated 2018
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * \file dss_dispPriv.h
+ *
+ * \brief DSS Display driver private header file.
+ */
+
+#ifndef DSS_DISPPRIV_H_
+#define DSS_DISPPRIV_H_
+
+/* ========================================================================== */
+/* Include Files */
+/* ========================================================================== */
+
+#include <ti/drv/dss/dss.h>
+#include <ti/drv/dss/src/drv/dctrl/dss_dctrlIntr.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* ========================================================================== */
+/* Macros & Typedefs */
+/* ========================================================================== */
+
+/**
+ * \brief Minimum number of buffers needed for starting the display operation.
+ */
+#define DSS_DISP_DRV_MIN_PRIME_BUFFERS (1U)
+
+/* ========================================================================== */
+/* Structure Declarations */
+/* ========================================================================== */
+
+/**
+ * \brief Different states of the display driver.
+ */
+typedef struct
+{
+ uint32_t isInit;
+ /**< Flag to indicate initialization is done or not for an instance */
+ uint32_t isOpened;
+ /**< Flag to indicate whether the instance is opened or not */
+ uint32_t isStarted;
+ /**< Flag to indicate whether the display has started or not */
+ uint32_t isStarting;
+ /**< Flag to indicate whether the display is going to start */
+ uint32_t isStopping;
+ /**< Flag to indicate whether the display is going to stop */
+} Dss_DispDrvState;
+
+/** \brief Forward declaration for instance object. */
+typedef struct Dss_DispDrvInstObj_t Dss_DispDrvInstObj;
+
+/**
+ * \brief Structure defining the queue object used in queue/dequeue operation.
+ * Instead of creating frame objects, this is used so that any other
+ * information could be queued/dequeued along with the frame.
+ * Already qElem is added to avoid dynamic allocation of Queue nodes.
+ */
+typedef struct
+{
+ Fvid2Utils_QElem qElem;
+ /**< FVID2 Utils queue element used in node addition */
+ Dss_DispDrvInstObj *instObj;
+ /**< Reference to the instance object for this queue object */
+ Fvid2_Frame *frm;
+ /**< #FVID2_frame to store the incoming/outgoing IO packets */
+ uint32_t creditCnt;
+ /**< Number of times the frame is queued for display. This counter is used
+ * to determine the number of times the frame is repeated. Initial value
+ * of the counter is zero. For every queue the counter is incremented.
+ * For every dequeue the counter is decremented. When the counter becomes
+ * 0 in dequeue, the frame is ready to be given to the application
+ * depending on the buffer mode selected. */
+} Dss_DispDrvQueObj;
+
+/**
+ * \brief Structure to store the buffer management functionality variables.
+ */
+typedef struct
+{
+ uint32_t isProgressive;
+ /**< Flag to indicate whether the display is progressive or interlaced */
+ uint32_t curFid;
+ /**< Indicates current field ID. Used in interlaced display */
+ uint32_t expectedFid;
+ /**< Indicates the next set field expected. This is used to check if
+ * display is occurring at proper sequence without any field misses */
+ uint32_t fieldMerged;
+ /**< This variable is used to specify whether two fields are merged for
+ * frame display or they in separate planes */
+ /*
+ * Initially all the queue elements will be in freeQ.
+ *
+ * For every application queue operation, freeQ -> reqQ
+ * For every request submitted to hardware, reqQ -> currQ
+ * For every request completion from hardware, currQ -> doneQ (per Instance)
+ * For every application dequeue operation, doneQ -> freeQ
+ */
+ Fvid2UtilsLinkListObj *freeQ;
+ /**< Queue for queuing all the free queue objects */
+ Fvid2UtilsLinkListObj *reqQ;
+ /**< Queue object to put the input requests */
+ Fvid2UtilsLinkListObj *currQ;
+ /**< Buffers that are queued to hardware but not yet fully displayed */
+ Fvid2UtilsLinkListObj *doneQ;
+ /**< Queue object to put the displayed output requests */
+ Fvid2UtilsLinkListObj freeLlObj;
+ /**< Linked List object for freeQ */
+ Fvid2UtilsLinkListObj reqLlObj;
+ /**< Linked List object for reqQ */
+ Fvid2UtilsLinkListObj curLlObj;
+ /**< Linked List object for currQ */
+ Fvid2UtilsLinkListObj doneLlObj;
+ /**< Linked List object for doneQ */
+ Dss_DispDrvQueObj dispQObj[DSS_DEF_QUEUE_LEN_PER_INST];
+ /**< Display queue objects */
+} Dss_DispDrvBufManObj;
+
+/**
+ * \brief Display driver instance information.
+ */
+struct Dss_DispDrvInstObj_t
+{
+ uint32_t drvInstId;
+ /**< Driver Instance ID */
+ uint32_t numRegEvtHandle;
+ /**< Number of registered event group handles */
+ void *evtGroupHandle[DSS_DISP_INST_EVT_MGR_MAX_CLIENTS];
+ /**< Handle to registered event groups */
+ Dss_DispCreateParams createParams;
+ /**< Display driver create parameters */
+ Fvid2_DrvCbParams fdmCbParams;
+ /**< FVID2 driver manager callback function parameters */
+ Dss_DispBufPrgmCbParams bufPrgmCbParams;
+ /**< Display buffer program callback parameters */
+ Dss_DispPipePrgmCbParams pipePrgmCbParams;
+ /**< Video pipe program callback parameters */
+ Dss_DispUnderFlowCbParams underFlowCbParams;
+ /**< Video pipe underflow callback parameters */
+ Dss_DispPipeSafetyChkParams safetyChkParams;
+ /**< Video pipe safety error callback parameters */
+ Dss_DispDrvState drvState;
+ /**< Instance state */
+ Dss_DispDrvBufManObj bmObj;
+ /**< Channel buffer management object */
+ Dss_DispCurrentStatus currStatus;
+ /**< Instance statistics object */
+ DssDctrlDrvClientHandle dctrlHandle;
+ /**< Handle to display controller */
+ Dss_DispParams pipeParams[CSL_DSS_VID_PIPE_ID_MAX];
+ /**< Display Configuration of video pipe */
+ uint32_t standard;
+ /**< Video Port Output Standard like NTSC, 1080p etc to which the display
+ * driver path is connected. For valid values see #FVID2_Standard */
+ uint32_t dispWidth;
+ /**< Width of the display at the Video Port Output in pixels to which the
+ * display driver path is connected */
+ uint32_t dispHeight;
+ /**< Height of the display at the Video Port Output in lines to which the
+ * display driver path is connected */
+ uint32_t dispScanFormat;
+ /**< Scan format of the display at the Video Port Output in lines to which
+ * the display driver path is connected */
+ uint32_t pipeId;
+ /**< Video Pipe Id. Refer \ref CSL_DssVidPipeId for values */
+ uint32_t pipeNodeId;
+ /**< Information of the pipe connected */
+ uint32_t vpId;
+ /**< Video Port ID to which this display instance is connected. */
+ Fvid2_Frame *progFrame;
+ /**< Pointer to Programmed Frame buffer structure.
+ * This frame will be programmed in the shadowed registers. */
+ Fvid2_Frame *currFrame;
+ /**< Pointer to Current Frame buffer structure.
+ * This frame is currently being displayed. */
+ uint32_t isPrevBufRep;
+ /**< Flag to check if previous buffer is repeated */
+ volatile uint32_t isInIsrContext;
+ /**< Flag to check if queue operation is called from the DSS ISR callback
+ * context */
+ uint32_t inScanFormat;
+ /**< Input scan format, for valid values check #Fvid2_ScanFormat */
+ SemaphoreP_Handle lockSem;
+ /**< Semaphore to protect the open/close calls and other memory
+ * allocation per instance */
+};
+
+/**
+ * \brief Display driver global/common driver object.
+ */
+typedef struct
+{
+ Fvid2_DrvOps fvidDrvOps;
+ /**< FVID2 driver ops */
+ uint32_t isRegistered;
+ /**< FVID2 registration complete flag */
+ uint32_t numInst;
+ /**< Number of valid instance */
+ Dss_DispDrvInstObj *instObj;
+ /**< Display instance objects pointer */
+} Dss_DispDrvCommonObj;
+
+/* ========================================================================== */
+/* Internal/Private Function Declarations */
+/* ========================================================================== */
+
+/* None */
+
+/* ========================================================================== */
+/* Function Declarations */
+/* ========================================================================== */
+
+/*
+ * Global variables
+ */
+extern Dss_DispDrvCommonObj gDss_DispDrvCommonObj;
+
+int32_t Dss_dispDrvPrivInit(uint32_t numInst,
+ const Dss_DispDrvInitParams *initParams);
+int32_t Dss_dispDrvPrivDeInit(void);
+
+Dss_DispDrvInstObj *Dss_dispDrvGetInstObj(uint32_t instId);
+
+int32_t Dss_dispDrvCreateInstObj(Dss_DispDrvInstObj *instObj);
+int32_t Dss_dispDrvDeleteInstObj(Dss_DispDrvInstObj *instObj);
+
+/* ========================================================================== */
+/* Static Function Definitions */
+/* ========================================================================== */
+
+/* None */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #ifndef DSS_DISPPRIV_H_ */
diff --git a/packages/ti/drv/dss/src/drv/disp/src_files_disp.mk b/packages/ti/drv/dss/src/drv/disp/src_files_disp.mk
--- /dev/null
@@ -0,0 +1 @@
+SRCS_COMMON += dss_dispPriv.c dss_dispApi.c
diff --git a/packages/ti/drv/dss/src/drv/src_files_drv.mk b/packages/ti/drv/dss/src/drv/src_files_drv.mk
--- /dev/null
@@ -0,0 +1,9 @@
+SRCDIR += src/drv/common src/drv/dctrl src/drv/disp
+INCDIR += .
+
+PACKAGE_SRCS_COMMON += src/drv/common src/drv/dctrl src/drv/disp
+# Common driver source files across all platforms and cores
+SRCS_COMMON +=
+include src/drv/common/src_files_common.mk
+include src/drv/dctrl/src_files_dctrl.mk
+include src/drv/disp/src_files_disp.mk
\ No newline at end of file
diff --git a/packages/ti/drv/dss/src/makefile b/packages/ti/drv/dss/src/makefile
--- /dev/null
@@ -0,0 +1,59 @@
+#
+# This file is the makefile for building DSS driver library.
+#
+ifeq ($(RULES_MAKE), )
+include $(PDK_INSTALL_PATH)/ti/build/Rules.make
+else
+include $(RULES_MAKE)
+endif
+
+MODULE_NAME = dss
+
+SRCDIR = .
+INCDIR = .
+ifeq ($(SOC),$(filter $(SOC), am65xx))
+ SRCDIR += soc/V0
+ INCDIR += soc/V0
+ PACKAGE_SRCS_COMMON = soc/V0
+endif
+ifeq ($(SOC),$(filter $(SOC), j721e))
+ SRCDIR += soc/V1
+ INCDIR += soc/V1
+ PACKAGE_SRCS_COMMON = soc/V1
+ CFLAGS_LOCAL_COMMON = -DREF_CLK_19_2MHz -DHAVE_CMN_PLL1
+endif
+
+# List all the external components/interfaces, whose interface header files
+# need to be included for this component
+INCLUDE_EXTERNAL_INTERFACES = pdk
+INCLUDE_INTERNAL_INTERFACES = csl
+
+# Common source files and CFLAGS across all platforms and cores
+SRCS_COMMON +=
+include soc/src_files_soc.mk
+include src/csl/src_files_csl.mk
+include src/drv/src_files_drv.mk
+
+PACKAGE_SRCS_COMMON += dss.h dss_component.mk makefile .gitignore include docs src/makefile
+PACKAGE_SRCS_COMMON += soc/dss_soc.h soc/src_files_soc.mk src/csl/src_files_csl.mk src/drv/src_files_drv.mk
+PACKAGE_SRCS_COMMON += config_mk.bld package.bld package.xdc package.xs
+PACKAGE_SRCS_COMMON += Settings.xdc.xdt dssver.h dssver.h.xdt
+CFLAGS_LOCAL_COMMON += $(PDK_CFLAGS) $(DSS_CFLAGS)
+
+# Core/SoC/platform specific source files and CFLAGS
+# Example:
+# SRCS_<core/SoC/platform-name> =
+# CFLAGS_LOCAL_<core/SoC/platform-name> =
+
+# Include common make files
+ifeq ($(MAKERULEDIR), )
+#Makerule path not defined, define this and assume relative path from ROOTDIR
+ MAKERULEDIR := $(ROOTDIR)/ti/build/makerules
+ export MAKERULEDIR
+endif
+include $(MAKERULEDIR)/common.mk
+
+# OBJs and libraries are built by using rule defined in rules_<target>.mk
+# and need not be explicitly specified here
+
+# Nothing beyond this point