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raw | patch | inline | side by side (parent: ef47d1a)
raw | patch | inline | side by side (parent: ef47d1a)
author | Vishal Mahaveer <vishalm@ti.com> | |
Thu, 26 Nov 2020 15:49:51 +0000 (09:49 -0600) | ||
committer | Sivaraj R <sivaraj@ti.com> | |
Fri, 27 Nov 2020 03:52:07 +0000 (21:52 -0600) |
Add RAT offset to baseaddress of MCSPI registers.
Signed-off-by: Vishal Mahaveer <vishalm@ti.com>
Signed-off-by: Vishal Mahaveer <vishalm@ti.com>
packages/ti/drv/spi/soc/am64x/SPI_soc.c | patch | blob | history |
index 94e9bebc3de3b8adedcd8ecb18400e7270f7675f..5ff12ddfeb5a4ae2dd6e6ea5e9084c7f4ea552f2 100644 (file)
#define OSPI_PER_CNT (1U)
#define SPI_PER_CNT (MCSPI_PER_CNT + OSPI_PER_CNT)
+#if defined (BUILD_M4F)
+#define MCSPI_RAT_MAP_ADDR (0x60000000U) /* RAT map address for MCSPI */
+#endif
+
/* SPI configuration structure */
SPI_v1_HWAttrs spiInitCfg[MCSPI_PER_CNT] =
{
{
#if defined (BUILD_M4F)
/* McSPI0 on the MCU channel */
- CSL_MCU_MCSPI0_CFG_BASE, /* baseAddr */
+ CSL_MCU_MCSPI0_CFG_BASE + MCSPI_RAT_MAP_ADDR, /* baseAddr */
#else
/* McSPI0 on the Main domain */
CSL_MCSPI0_CFG_BASE, /* baseAddr */
{
#if defined (BUILD_M4F)
/* McSPI1 on the MCU channel */
- CSL_MCU_MCSPI1_CFG_BASE,
+ CSL_MCU_MCSPI1_CFG_BASE + MCSPI_RAT_MAP_ADDR,
#else
/* McSPI1 on the Main domain */
CSL_MCSPI1_CFG_BASE,