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raw | patch | inline | side by side (parent: db32dd2)
raw | patch | inline | side by side (parent: db32dd2)
author | M V Pratap Reddy <x0257344@ti.com> | |
Wed, 13 May 2020 10:47:15 +0000 (16:17 +0530) | ||
committer | M V Pratap Reddy <x0257344@ti.com> | |
Wed, 13 May 2020 10:47:15 +0000 (16:17 +0530) |
packages/ti/board/src/am64x_evm/AM64xx_pinmux.h | [new file with mode: 0755] | patch | blob |
packages/ti/board/src/am64x_evm/AM64xx_pinmux_data.c | [new file with mode: 0755] | patch | blob |
packages/ti/board/src/am64x_evm/board_pinmux.c | patch | blob | history | |
packages/ti/board/src/am64x_evm/include/board_pinmux.h | patch | blob | history | |
packages/ti/board/src/am64x_evm/include/pinmux.h | [new file with mode: 0755] | patch | blob |
packages/ti/board/src/am64x_evm/src_files_am64x_evm.mk | patch | blob | history |
diff --git a/packages/ti/board/src/am64x_evm/AM64xx_pinmux.h b/packages/ti/board/src/am64x_evm/AM64xx_pinmux.h
--- /dev/null
@@ -0,0 +1,339 @@
+/**\r
+ * Note: This file was auto-generated by TI PinMux on 5/13/2020 at 3:46:53 PM.\r
+ *\r
+ * \file AM65xx_pinmux.h\r
+ *\r
+ * \brief This file contains pad configure register offsets and bit-field \r
+ * value macros for different configurations,\r
+ *\r
+ * BIT[20:19] BUFFERCLASS set the pin's output driver characteristics\r
+ * BIT[18] RXACTIVE enable the pin's input buffer (typically kept enabled)\r
+ * BIT[17] PULLTYPESEL set the iternal resistor pull direction high or low (if enabled)\r
+ * BIT[16] PULLUDEN internal resistor disable (0 = enabled / 1 = disabled)\r
+ * BIT[3:0] MUXMODE select the desired function on the given pin\r
+ *\r
+ * \copyright Copyright (CU) 2020 Texas Instruments Incorporated - \r
+ * http://www.ti.com/\r
+ */\r
+\r
+#ifndef _AM64XX_PIN_MUX_H_\r
+#define _AM64XX_PIN_MUX_H_\r
+\r
+/* ========================================================================== */\r
+/* Include Files */\r
+/* ========================================================================== */\r
+\r
+#include "ti/board/src/am64x_evm/include/pinmux.h"\r
+#include "ti/csl/csl_types.h"\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+/* ========================================================================== */\r
+/* Macros & Typedefs */\r
+/* ========================================================================== */\r
+#define PIN_MODE(mode) (mode)\r
+#define PINMUX_END (-1)\r
+\r
+/** \brief Active mode configurations */\r
+/** \brief Resistor disable */\r
+#define PIN_PULL_DISABLE (0x1U << 16U) \r
+/** \brief Pull direction */\r
+#define PIN_PULL_DIRECTION (0x1U << 17U)\r
+/** \brief Receiver enable */\r
+#define PIN_INPUT_ENABLE (0x1U << 18U)\r
+/** \brief Driver disable */\r
+#define PIN_OUTPUT_DISABLE (0x1U << 21U)\r
+/** \brief Wakeup enable */\r
+#define PIN_WAKEUP_ENABLE (0x1U << 29U)\r
+\r
+\r
+\r
+/** \brief Pad config register offset in control module */\r
+enum pinMainOffsets\r
+{\r
+ PIN_GPMC0_AD0 = 0x0000U,\r
+ PIN_GPMC0_AD1 = 0x0004U,\r
+ PIN_GPMC0_AD2 = 0x0008U,\r
+ PIN_GPMC0_AD3 = 0x000CU,\r
+ PIN_GPMC0_AD4 = 0x0010U,\r
+ PIN_GPMC0_AD5 = 0x0014U,\r
+ PIN_GPMC0_AD6 = 0x0018U,\r
+ PIN_GPMC0_AD7 = 0x001CU,\r
+ PIN_GPMC0_AD8 = 0x0020U,\r
+ PIN_GPMC0_AD9 = 0x0024U,\r
+ PIN_GPMC0_AD10 = 0x0028U,\r
+ PIN_GPMC0_AD11 = 0x002CU,\r
+ PIN_GPMC0_AD12 = 0x0030U,\r
+ PIN_GPMC0_AD13 = 0x0034U,\r
+ PIN_GPMC0_AD14 = 0x0038U,\r
+ PIN_GPMC0_AD15 = 0x003CU,\r
+ PIN_GPMC0_CLK = 0x0040U,\r
+ PIN_GPMC0_ADVN_ALE = 0x0044U,\r
+ PIN_GPMC0_OEN_REN = 0x0048U,\r
+ PIN_GPMC0_WEN = 0x004CU,\r
+ PIN_GPMC0_BE0N_CLE = 0x0050U,\r
+ PIN_GPMC0_BE1N = 0x0054U,\r
+ PIN_GPMC0_WAIT0 = 0x0058U,\r
+ PIN_GPMC0_WAIT1 = 0x005CU,\r
+ PIN_GPMC0_WPN = 0x0060U,\r
+ PIN_GPMC0_DIR = 0x0064U,\r
+ PIN_GPMC0_CSN0 = 0x0068U,\r
+ PIN_GPMC0_CSN1 = 0x006CU,\r
+ PIN_GPMC0_CSN2 = 0x0070U,\r
+ PIN_GPMC0_CSN3 = 0x0074U,\r
+ PIN_PRG2_PRU0_GPO0 = 0x0078U,\r
+ PIN_PRG2_PRU0_GPO1 = 0x007CU,\r
+ PIN_PRG2_PRU0_GPO2 = 0x0080U,\r
+ PIN_PRG2_PRU0_GPO3 = 0x0084U,\r
+ PIN_PRG2_PRU0_GPO4 = 0x0088U,\r
+ PIN_PRG2_PRU0_GPO5 = 0x008CU,\r
+ PIN_PRG2_PRU0_GPO6 = 0x0090U,\r
+ PIN_PRG2_PRU0_GPO7 = 0x0094U,\r
+ PIN_PRG2_PRU0_GPO8 = 0x0098U,\r
+ PIN_PRG2_PRU0_GPO9 = 0x009CU,\r
+ PIN_PRG2_PRU0_GPO10 = 0x00A0U,\r
+ PIN_PRG2_PRU0_GPO11 = 0x00A4U,\r
+ PIN_PRG2_PRU0_GPO16 = 0x00A8U,\r
+ PIN_PRG2_PRU1_GPO0 = 0x00ACU,\r
+ PIN_PRG2_PRU1_GPO1 = 0x00B0U,\r
+ PIN_PRG2_PRU1_GPO2 = 0x00B4U,\r
+ PIN_PRG2_PRU1_GPO3 = 0x00B8U,\r
+ PIN_PRG2_PRU1_GPO4 = 0x00BCU,\r
+ PIN_PRG2_PRU1_GPO5 = 0x00C0U,\r
+ PIN_PRG2_PRU1_GPO6 = 0x00C4U,\r
+ PIN_PRG2_PRU1_GPO7 = 0x00C8U,\r
+ PIN_PRG2_PRU1_GPO8 = 0x00CCU,\r
+ PIN_PRG2_PRU1_GPO9 = 0x00D0U,\r
+ PIN_PRG2_PRU1_GPO10 = 0x00D4U,\r
+ PIN_PRG2_PRU1_GPO11 = 0x00D8U,\r
+ PIN_PRG2_PRU1_GPO16 = 0x00DCU,\r
+ PIN_PRG1_PRU0_GPO0 = 0x00E0U,\r
+ PIN_PRG1_PRU0_GPO1 = 0x00E4U,\r
+ PIN_PRG1_PRU0_GPO2 = 0x00E8U,\r
+ PIN_PRG1_PRU0_GPO3 = 0x00ECU,\r
+ PIN_PRG1_PRU0_GPO4 = 0x00F0U,\r
+ PIN_PRG1_PRU0_GPO5 = 0x00F4U,\r
+ PIN_PRG1_PRU0_GPO6 = 0x00F8U,\r
+ PIN_PRG1_PRU0_GPO7 = 0x00FCU,\r
+ PIN_PRG1_PRU0_GPO8 = 0x0100U,\r
+ PIN_PRG1_PRU0_GPO9 = 0x0104U,\r
+ PIN_PRG1_PRU0_GPO10 = 0x0108U,\r
+ PIN_PRG1_PRU0_GPO11 = 0x010CU,\r
+ PIN_PRG1_PRU0_GPO12 = 0x0110U,\r
+ PIN_PRG1_PRU0_GPO13 = 0x0114U,\r
+ PIN_PRG1_PRU0_GPO14 = 0x0118U,\r
+ PIN_PRG1_PRU0_GPO15 = 0x011CU,\r
+ PIN_PRG1_PRU0_GPO16 = 0x0120U,\r
+ PIN_PRG1_PRU0_GPO17 = 0x0124U,\r
+ PIN_PRG1_PRU0_GPO18 = 0x0128U,\r
+ PIN_PRG1_PRU0_GPO19 = 0x012CU,\r
+ PIN_PRG1_PRU1_GPO0 = 0x0130U,\r
+ PIN_PRG1_PRU1_GPO1 = 0x0134U,\r
+ PIN_PRG1_PRU1_GPO2 = 0x0138U,\r
+ PIN_PRG1_PRU1_GPO3 = 0x013CU,\r
+ PIN_PRG1_PRU1_GPO4 = 0x0140U,\r
+ PIN_PRG1_PRU1_GPO5 = 0x0144U,\r
+ PIN_PRG1_PRU1_GPO6 = 0x0148U,\r
+ PIN_PRG1_PRU1_GPO7 = 0x014CU,\r
+ PIN_PRG1_PRU1_GPO8 = 0x0150U,\r
+ PIN_PRG1_PRU1_GPO9 = 0x0154U,\r
+ PIN_PRG1_PRU1_GPO10 = 0x0158U,\r
+ PIN_PRG1_PRU1_GPO11 = 0x015CU,\r
+ PIN_PRG1_PRU1_GPO12 = 0x0160U,\r
+ PIN_PRG1_PRU1_GPO13 = 0x0164U,\r
+ PIN_PRG1_PRU1_GPO14 = 0x0168U,\r
+ PIN_PRG1_PRU1_GPO15 = 0x016CU,\r
+ PIN_PRG1_PRU1_GPO16 = 0x0170U,\r
+ PIN_PRG1_PRU1_GPO17 = 0x0174U,\r
+ PIN_PRG1_PRU1_GPO18 = 0x0178U,\r
+ PIN_PRG1_PRU1_GPO19 = 0x017CU,\r
+ PIN_PRG1_MDIO0_MDIO = 0x0180U,\r
+ PIN_PRG1_MDIO0_MDC = 0x0184U,\r
+ PIN_MMC0_DAT7 = 0x0188U,\r
+ PIN_MMC0_DAT6 = 0x018CU,\r
+ PIN_MMC0_DAT5 = 0x0190U,\r
+ PIN_MMC0_DAT4 = 0x0194U,\r
+ PIN_MMC0_DAT3 = 0x0198U,\r
+ PIN_MMC0_DAT2 = 0x019CU,\r
+ PIN_MMC0_DAT1 = 0x01A0U,\r
+ PIN_MMC0_DAT0 = 0x01A4U,\r
+ PIN_MMC0_CLK = 0x01A8U,\r
+ PIN_MMC0_CMD = 0x01ACU,\r
+ PIN_MMC0_DS = 0x01B0U,\r
+ PIN_MMC0_SDCD = 0x01B4U,\r
+ PIN_MMC0_SDWP = 0x01B8U,\r
+ PIN_SPI0_CS0 = 0x01BCU,\r
+ PIN_SPI0_CS1 = 0x01C0U,\r
+ PIN_SPI0_CLK = 0x01C4U,\r
+ PIN_SPI0_D0 = 0x01C8U,\r
+ PIN_SPI0_D1 = 0x01CCU,\r
+ PIN_SPI1_CS0 = 0x01D0U,\r
+ PIN_SPI1_CS1 = 0x01D4U,\r
+ PIN_SPI1_CLK = 0x01D8U,\r
+ PIN_SPI1_D0 = 0x01DCU,\r
+ PIN_SPI1_D1 = 0x01E0U,\r
+ PIN_UART0_RXD = 0x01E4U,\r
+ PIN_UART0_TXD = 0x01E8U,\r
+ PIN_UART0_CTSN = 0x01ECU,\r
+ PIN_UART0_RTSN = 0x01F0U,\r
+ PIN_PRG0_PRU0_GPO0 = 0x01F4U,\r
+ PIN_PRG0_PRU0_GPO1 = 0x01F8U,\r
+ PIN_PRG0_PRU0_GPO2 = 0x01FCU,\r
+ PIN_PRG0_PRU0_GPO3 = 0x0200U,\r
+ PIN_PRG0_PRU0_GPO4 = 0x0204U,\r
+ PIN_PRG0_PRU0_GPO5 = 0x0208U,\r
+ PIN_PRG0_PRU0_GPO6 = 0x020CU,\r
+ PIN_PRG0_PRU0_GPO7 = 0x0210U,\r
+ PIN_PRG0_PRU0_GPO8 = 0x0214U,\r
+ PIN_PRG0_PRU0_GPO9 = 0x0218U,\r
+ PIN_PRG0_PRU0_GPO10 = 0x021CU,\r
+ PIN_PRG0_PRU0_GPO11 = 0x0220U,\r
+ PIN_PRG0_PRU0_GPO12 = 0x0224U,\r
+ PIN_PRG0_PRU0_GPO13 = 0x0228U,\r
+ PIN_PRG0_PRU0_GPO14 = 0x022CU,\r
+ PIN_PRG0_PRU0_GPO15 = 0x0230U,\r
+ PIN_PRG0_PRU0_GPO16 = 0x0234U,\r
+ PIN_PRG0_PRU0_GPO17 = 0x0238U,\r
+ PIN_PRG0_PRU0_GPO18 = 0x023CU,\r
+ PIN_PRG0_PRU0_GPO19 = 0x0240U,\r
+ PIN_PRG0_PRU1_GPO0 = 0x0244U,\r
+ PIN_PRG0_PRU1_GPO1 = 0x0248U,\r
+ PIN_PRG0_PRU1_GPO2 = 0x024CU,\r
+ PIN_PRG0_PRU1_GPO3 = 0x0250U,\r
+ PIN_PRG0_PRU1_GPO4 = 0x0254U,\r
+ PIN_PRG0_PRU1_GPO5 = 0x0258U,\r
+ PIN_PRG0_PRU1_GPO6 = 0x025CU,\r
+ PIN_PRG0_PRU1_GPO7 = 0x0260U,\r
+ PIN_PRG0_PRU1_GPO8 = 0x0264U,\r
+ PIN_PRG0_PRU1_GPO9 = 0x0268U,\r
+ PIN_PRG0_PRU1_GPO10 = 0x026CU,\r
+ PIN_PRG0_PRU1_GPO11 = 0x0270U,\r
+ PIN_PRG0_PRU1_GPO12 = 0x0274U,\r
+ PIN_PRG0_PRU1_GPO13 = 0x0278U,\r
+ PIN_PRG0_PRU1_GPO14 = 0x027CU,\r
+ PIN_PRG0_PRU1_GPO15 = 0x0280U,\r
+ PIN_PRG0_PRU1_GPO16 = 0x0284U,\r
+ PIN_PRG0_PRU1_GPO17 = 0x0288U,\r
+ PIN_PRG0_PRU1_GPO18 = 0x028CU,\r
+ PIN_PRG0_PRU1_GPO19 = 0x0290U,\r
+ PIN_PRG0_MDIO0_MDIO = 0x0294U,\r
+ PIN_PRG0_MDIO0_MDC = 0x0298U,\r
+ PIN_NMIN = 0x029CU,\r
+ PIN_RESETZ = 0x02A0U,\r
+ PIN_RESETSTATZ = 0x02A4U,\r
+ PIN_PORZ_OUT = 0x02A8U,\r
+ PIN_SOC_SAFETY_ERRORN = 0x02ACU,\r
+ PIN_TDI = 0x02B0U,\r
+ PIN_TDO = 0x02B4U,\r
+ PIN_TMS = 0x02B8U,\r
+ PIN_USB0_DRVVBUS = 0x02BCU,\r
+ PIN_USB1_DRVVBUS = 0x02C0U,\r
+ PIN_MMC1_DAT3 = 0x02C4U,\r
+ PIN_MMC1_DAT2 = 0x02C8U,\r
+ PIN_MMC1_DAT1 = 0x02CCU,\r
+ PIN_MMC1_DAT0 = 0x02D0U,\r
+ PIN_MMC1_CLK = 0x02D4U,\r
+ PIN_MMC1_CMD = 0x02D8U,\r
+ PIN_MMC1_SDCD = 0x02DCU,\r
+ PIN_MMC1_SDWP = 0x02E0U,\r
+ PIN_I2C0_SCL = 0x02E8U,\r
+ PIN_I2C0_SDA = 0x02ECU,\r
+ PIN_I2C1_SCL = 0x02F0U,\r
+ PIN_I2C1_SDA = 0x02F4U,\r
+ PIN_ECAP0_IN_APWM_OUT = 0x02F8U,\r
+ PIN_EXT_REFCLK1 = 0x02FCU,\r
+ PIN_TIMER_IO0 = 0x0300U,\r
+ PIN_TIMER_IO1 = 0x0304U,\r
+ PIN_PORZ = 0x0308U,\r
+};\r
+\r
+enum pinWkupOffsets\r
+{\r
+ PIN_MCU_OSPI0_CLK = 0x0000U,\r
+ PIN_MCU_OSPI0_LBCLKO = 0x0004U,\r
+ PIN_MCU_OSPI0_DQS = 0x0008U,\r
+ PIN_MCU_OSPI0_D0 = 0x000CU,\r
+ PIN_MCU_OSPI0_D1 = 0x0010U,\r
+ PIN_MCU_OSPI0_D2 = 0x0014U,\r
+ PIN_MCU_OSPI0_D3 = 0x0018U,\r
+ PIN_MCU_OSPI0_D4 = 0x001CU,\r
+ PIN_MCU_OSPI0_D5 = 0x0020U,\r
+ PIN_MCU_OSPI0_D6 = 0x0024U,\r
+ PIN_MCU_OSPI0_D7 = 0x0028U,\r
+ PIN_MCU_OSPI0_CSN0 = 0x002CU,\r
+ PIN_MCU_OSPI0_CSN1 = 0x0030U,\r
+ PIN_MCU_OSPI1_CLK = 0x0034U,\r
+ PIN_MCU_OSPI1_LBCLKO = 0x0038U,\r
+ PIN_MCU_OSPI1_DQS = 0x003CU,\r
+ PIN_MCU_OSPI1_D0 = 0x0040U,\r
+ PIN_MCU_OSPI1_D1 = 0x0044U,\r
+ PIN_MCU_OSPI1_D2 = 0x0048U,\r
+ PIN_MCU_OSPI1_D3 = 0x004CU,\r
+ PIN_MCU_OSPI1_CSN0 = 0x0050U,\r
+ PIN_MCU_OSPI1_CSN1 = 0x0054U,\r
+ PIN_MCU_RGMII1_TX_CTL = 0x0058U,\r
+ PIN_MCU_RGMII1_RX_CTL = 0x005CU,\r
+ PIN_MCU_RGMII1_TD3 = 0x0060U,\r
+ PIN_MCU_RGMII1_TD2 = 0x0064U,\r
+ PIN_MCU_RGMII1_TD1 = 0x0068U,\r
+ PIN_MCU_RGMII1_TD0 = 0x006CU,\r
+ PIN_MCU_RGMII1_TXC = 0x0070U,\r
+ PIN_MCU_RGMII1_RXC = 0x0074U,\r
+ PIN_MCU_RGMII1_RD3 = 0x0078U,\r
+ PIN_MCU_RGMII1_RD2 = 0x007CU,\r
+ PIN_MCU_RGMII1_RD1 = 0x0080U,\r
+ PIN_MCU_RGMII1_RD0 = 0x0084U,\r
+ PIN_MCU_MDIO0_MDIO = 0x0088U,\r
+ PIN_MCU_MDIO0_MDC = 0x008CU,\r
+ PIN_MCU_SPI0_CLK = 0x0090U,\r
+ PIN_MCU_SPI0_D0 = 0x0094U,\r
+ PIN_MCU_SPI0_D1 = 0x0098U,\r
+ PIN_MCU_SPI0_CS0 = 0x009CU,\r
+ PIN_WKUP_UART0_RXD = 0x00A0U,\r
+ PIN_WKUP_UART0_TXD = 0x00A4U,\r
+ PIN_MCU_MCAN0_TX = 0x00A8U,\r
+ PIN_MCU_MCAN0_RX = 0x00ACU,\r
+ PIN_WKUP_GPIO0_0 = 0x00B0U,\r
+ PIN_WKUP_GPIO0_1 = 0x00B4U,\r
+ PIN_WKUP_GPIO0_2 = 0x00B8U,\r
+ PIN_WKUP_GPIO0_3 = 0x00BCU,\r
+ PIN_WKUP_GPIO0_4 = 0x00C0U,\r
+ PIN_WKUP_GPIO0_5 = 0x00C4U,\r
+ PIN_WKUP_GPIO0_6 = 0x00C8U,\r
+ PIN_WKUP_GPIO0_7 = 0x00CCU,\r
+ PIN_WKUP_GPIO0_8 = 0x00D0U,\r
+ PIN_WKUP_GPIO0_9 = 0x00D4U,\r
+ PIN_WKUP_GPIO0_10 = 0x00D8U,\r
+ PIN_WKUP_GPIO0_11 = 0x00DCU,\r
+ PIN_WKUP_I2C0_SCL = 0x00E0U,\r
+ PIN_WKUP_I2C0_SDA = 0x00E4U,\r
+ PIN_MCU_I2C0_SCL = 0x00E8U,\r
+ PIN_MCU_I2C0_SDA = 0x00ECU,\r
+ PIN_PMIC_POWER_EN1 = 0x00F0U,\r
+ PIN_MCU_SAFETY_ERRORN = 0x00F4U,\r
+ PIN_MCU_RESETZ = 0x00F8U,\r
+ PIN_MCU_RESETSTATZ = 0x00FCU,\r
+ PIN_MCU_PORZ_OUT = 0x0100U,\r
+ PIN_TCK = 0x0104U,\r
+ PIN_TRSTN = 0x0108U,\r
+ PIN_EMU0 = 0x010CU,\r
+ PIN_EMU1 = 0x0110U,\r
+ PIN_PMIC_POWER_EN0 = 0x0114U,\r
+};\r
+\r
+\r
+/* ========================================================================== */\r
+/* Global Variables */\r
+/* ========================================================================== */\r
+\r
+/** \brief Pinmux configuration data for the board. Auto-generated from \r
+ Pinmux tool. */\r
+extern pinmuxBoardCfg_t gAM64xxMainPinmuxData[];\r
+extern pinmuxBoardCfg_t gAM64xxWkupPinmuxData[];\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif /* __cplusplus */\r
+#endif /* _AM64XX_PIN_MUX_H_ */\r
diff --git a/packages/ti/board/src/am64x_evm/AM64xx_pinmux_data.c b/packages/ti/board/src/am64x_evm/AM64xx_pinmux_data.c
--- /dev/null
@@ -0,0 +1,104 @@
+/**\r
+* Note: This file was auto-generated by TI PinMux on 5/13/2020 at 3:46:58 PM.\r
+*\r
+* \file AM64xx_pinmux_data.c\r
+*\r
+* \brief This file contains the pin mux configurations for the boards.\r
+* These are prepared based on how the peripherals are extended on\r
+* the boards.\r
+*\r
+* \copyright Copyright (CU) 2020 Texas Instruments Incorporated -\r
+* http://www.ti.com/\r
+*/\r
+\r
+/* ========================================================================== */\r
+/* Include Files */\r
+/* ========================================================================== */\r
+\r
+#include "AM64xx_pinmux.h"\r
+\r
+/** Peripheral Pin Configurations */\r
+\r
+\r
+static pinmuxPerCfg_t gOspi00PinCfg[] =\r
+{\r
+ /* MyOSPI01 -> OSPI0_CLK -> N20 */\r
+ {\r
+ PIN_MCU_OSPI0_CLK, PIN_MODE(0) | \\r
+ ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+ },\r
+ /* MyOSPI01 -> OSPI0_LBCLKO -> N21 */\r
+ {\r
+ PIN_MCU_OSPI0_LBCLKO, PIN_MODE(0) | \\r
+ ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+ },\r
+ /* MyOSPI01 -> OSPI0_DQS -> N19 */\r
+ {\r
+ PIN_MCU_OSPI0_DQS, PIN_MODE(0) | \\r
+ ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+ },\r
+ /* MyOSPI01 -> OSPI0_D0 -> M18 */\r
+ {\r
+ PIN_MCU_OSPI0_D0, PIN_MODE(0) | \\r
+ ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+ },\r
+ /* MyOSPI01 -> OSPI0_D1 -> M19 */\r
+ {\r
+ PIN_MCU_OSPI0_D1, PIN_MODE(0) | \\r
+ ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+ },\r
+ /* MyOSPI01 -> OSPI0_D2 -> M21 */\r
+ {\r
+ PIN_MCU_OSPI0_D2, PIN_MODE(0) | \\r
+ ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+ },\r
+ /* MyOSPI01 -> OSPI0_D3 -> M20 */\r
+ {\r
+ PIN_MCU_OSPI0_D3, PIN_MODE(0) | \\r
+ ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+ },\r
+ /* MyOSPI01 -> OSPI0_D4 -> P21 */\r
+ {\r
+ PIN_MCU_OSPI0_D4, PIN_MODE(0) | \\r
+ ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+ },\r
+ /* MyOSPI01 -> OSPI0_D5 -> P20 */\r
+ {\r
+ PIN_MCU_OSPI0_D5, PIN_MODE(0) | \\r
+ ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+ },\r
+ /* MyOSPI01 -> OSPI0_D6 -> N18 */\r
+ {\r
+ PIN_MCU_OSPI0_D6, PIN_MODE(0) | \\r
+ ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+ },\r
+ /* MyOSPI01 -> OSPI0_D7 -> M17 */\r
+ {\r
+ PIN_MCU_OSPI0_D7, PIN_MODE(0) | \\r
+ ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+ },\r
+ /* MyOSPI01 -> OSPI0_CSn0 -> L18 */\r
+ {\r
+ PIN_MCU_OSPI0_CSN0, PIN_MODE(0) | \\r
+ ((PIN_PULL_DISABLE) & (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE))\r
+ },\r
+ {PINMUX_END}\r
+};\r
+\r
+static pinmuxModuleCfg_t gOspi0PinCfg[] =\r
+{\r
+ {0, TRUE, gOspi00PinCfg},\r
+ {PINMUX_END}\r
+};\r
+\r
+\r
+pinmuxBoardCfg_t gAM64xxMainPinmuxData[] =\r
+{\r
+ {0, gOspi0PinCfg},\r
+ {PINMUX_END}\r
+};\r
+\r
+pinmuxBoardCfg_t gAM64xxWkupPinmuxData[] =\r
+{\r
+ {PINMUX_END}\r
+};\r
diff --git a/packages/ti/board/src/am64x_evm/board_pinmux.c b/packages/ti/board/src/am64x_evm/board_pinmux.c
index 5389d1fd902af0af1178c5e54ff779a1a4f55f5f..f5d7ece5eb8e934b87797715fa9613031075c459 100644 (file)
void writeToPadConfigReg(pinmux_t * arrayPtr, uint32_t mmr_reg_value);\r
uint32_t readFromPadConfigReg(pinmux_t * arrayPtr);\r
\r
+#ifdef BOARD_QT_MANUAL_PINMUX_SETUP\r
static const pinmux_t OSPI_COMPLETE_PINMUX_array [] = {\r
//Pinmux Region, Offset, Muxmode, TX, RX, Pull Up/Down/None, Drive Strength, Schmitt Trigger, Debounce Period\r
{PINMUX_REGION_MAIN, 0x0000, PINMUX_MUX_MODE_0, PINMUX_TX_ENABLE, PINMUX_RX_DISABLE, PINMUX_PULLTYPE_PULLDOWN, PINMUX_DRIVE_STRENGTH_IGNORE, PINMUX_SCHMITT_TRIG_IGNORE, PINMUX_DEBOUNCE_PERIOD_IGNORE}, //OSPI0 CLK\r
{PINMUX_REGION_MAIN, 0x0034, PINMUX_MUX_MODE_2, PINMUX_TX_ENABLE, PINMUX_RX_DISABLE, PINMUX_PULLTYPE_PULLUP, PINMUX_DRIVE_STRENGTH_IGNORE, PINMUX_SCHMITT_TRIG_IGNORE, PINMUX_DEBOUNCE_PERIOD_IGNORE}, //OSPI RESET_OUT1\r
{PINMUX_REGION_MAIN, 0x0038, PINMUX_MUX_MODE_1, PINMUX_TX_ENABLE, PINMUX_RX_DISABLE, PINMUX_PULLTYPE_PULLUP, PINMUX_DRIVE_STRENGTH_IGNORE, PINMUX_SCHMITT_TRIG_IGNORE, PINMUX_DEBOUNCE_PERIOD_IGNORE}, //OSPI RESET_OUT0\r
};\r
+#endif\r
\r
void set_pinmux(pinmux_t *Array, uint8_t arraysize){\r
uint32_t c = 0;\r
\r
Board_STATUS Board_pinmuxConfig (void)\r
{\r
+#ifdef BOARD_QT_MANUAL_PINMUX_SETUP\r
MAIN_PADCONFIG_MMR_unlock_all();\r
set_pinmux((pinmux_t *)&OSPI_COMPLETE_PINMUX_array, (sizeof(OSPI_COMPLETE_PINMUX_array)/sizeof(pinmux_t)) );\r
+#else\r
+ pinmuxModuleCfg_t* pModuleData = NULL;\r
+ pinmuxPerCfg_t* pInstanceData = NULL;\r
+ int32_t i, j, k;\r
+\r
+ MAIN_PADCONFIG_MMR_unlock_all();\r
+\r
+ for(i = 0; PINMUX_END != gAM64xxMainPinmuxData[i].moduleId; i++)\r
+ {\r
+ pModuleData = gAM64xxMainPinmuxData[i].modulePinCfg;\r
+ for(j = 0; (PINMUX_END != pModuleData[j].modInstNum); j++)\r
+ {\r
+ if(pModuleData[j].doPinConfig == TRUE)\r
+ {\r
+ pInstanceData = pModuleData[j].instPins;\r
+ for(k = 0; (PINMUX_END != pInstanceData[k].pinOffset); k++)\r
+ {\r
+ HW_WR_REG32((MAIN_PADCONFIG_MMR_BASE_ADDRESS + pInstanceData[k].pinOffset),\r
+ (pInstanceData[k].pinSettings));\r
+ }\r
+ }\r
+ }\r
+ }\r
+\r
+ for(i = 0; PINMUX_END != gAM64xxWkupPinmuxData[i].moduleId; i++)\r
+ {\r
+ pModuleData = gAM64xxWkupPinmuxData[i].modulePinCfg;\r
+ for(j = 0; (PINMUX_END != pModuleData[j].modInstNum); j++)\r
+ {\r
+ if(pModuleData[j].doPinConfig == TRUE)\r
+ {\r
+ pInstanceData = pModuleData[j].instPins;\r
+ for(k = 0; (PINMUX_END != pInstanceData[k].pinOffset); k++)\r
+ {\r
+ HW_WR_REG32((MCU_PADCONFIG_MMR_BASE_ADDRESS + pInstanceData[k].pinOffset),\r
+ (pInstanceData[k].pinSettings));\r
+ }\r
+ }\r
+ }\r
+ }\r
+\r
+#endif\r
\r
return BOARD_SOK;\r
}\r
diff --git a/packages/ti/board/src/am64x_evm/include/board_pinmux.h b/packages/ti/board/src/am64x_evm/include/board_pinmux.h
index cff021d73c3219c168c5161b66ed509d610ce0bc..b489ee986c29fbf4bf6faed672cb9c53e001effa 100644 (file)
*\r
*****************************************************************************/\r
\r
-#ifndef PINMUX_H\r
-#define PINMUX_H\r
+#ifndef _BOARD_PINMUX_H_\r
+#define _BOARD_PINMUX_H_\r
\r
#ifdef __cplusplus\r
extern "C" {\r
*/\r
\r
#include <ti/csl/tistdtypes.h>\r
+#include "AM64xx_pinmux.h"\r
\r
/* ========================================================================== */\r
/* Structures and Enums */\r
/* ========================================================================== */\r
\r
-/**\r
- * \brief Structure defining the pin configuration parameters.\r
- *\r
- */\r
-typedef struct pinmuxPerCfg\r
-{\r
- int16_t pinOffset;\r
- /**< Register offset for configuring the pin */\r
- int32_t pinSettings;\r
- /**< Value to be configured,\r
- - Active mode configurations like mux mode, pull resistor, and buffer mode\r
- */\r
-}pinmuxPerCfg_t;\r
-\r
-/**\r
- * \brief Structure defining the pin configuration for different instances of\r
- * a module.\r
- */\r
-typedef struct pinmuxModuleCfg\r
-{\r
- int16_t modInstNum;\r
- /**< Instance number of the ip */\r
- int16_t doPinConfig;\r
- /**< Flag indicating whether this instance has to be configured. This flag\r
- can be altered with separate API (PinMuxConfigEnable()).\r
- Default configuration will be set to TRUE, but can be altered for\r
- different scenarios (like power management). */\r
- pinmuxPerCfg_t* instPins;\r
- /**< Pointer to list of pins corresponding to this instance */\r
-}pinmuxModuleCfg_t;\r
-\r
-/**\r
- * \brief Structure defining the pin configuration of a board.\r
- */\r
-typedef struct pinmuxBoardCfg\r
-{\r
- int32_t moduleId;\r
- /**< Module ID */\r
- pinmuxModuleCfg_t* modulePinCfg;\r
- /**< Pin config info of a module: #pinmuxModuleCfg_t */\r
-}pinmuxBoardCfg_t;\r
\r
#ifdef __cplusplus\r
}\r
#endif /* __cplusplus */\r
\r
-#endif\r
+#endif /* _BOARD_PINMUX_H_ */\r
diff --git a/packages/ti/board/src/am64x_evm/include/pinmux.h b/packages/ti/board/src/am64x_evm/include/pinmux.h
--- /dev/null
@@ -0,0 +1,102 @@
+/******************************************************************************
+ * Copyright (c) 2017 Texas Instruments Incorporated - http://www.ti.com
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *****************************************************************************/
+
+#ifndef PINMUX_H
+#define PINMUX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \file pinmux.h
+ *
+ * \brief AM65x EVM board pinmux header file
+ *
+ * This file includes the structures to enable the pinmux configurations
+ *
+ */
+
+#include <ti/csl/tistdtypes.h>
+
+/* ========================================================================== */
+/* Structures and Enums */
+/* ========================================================================== */
+
+/**
+ * \brief Structure defining the pin configuration parameters.
+ *
+ */
+typedef struct pinmuxPerCfg
+{
+ int16_t pinOffset;
+ /**< Register offset for configuring the pin */
+ int32_t pinSettings;
+ /**< Value to be configured,
+ - Active mode configurations like mux mode, pull resistor, and buffer mode
+ */
+}pinmuxPerCfg_t;
+
+/**
+ * \brief Structure defining the pin configuration for different instances of
+ * a module.
+ */
+typedef struct pinmuxModuleCfg
+{
+ int16_t modInstNum;
+ /**< Instance number of the ip */
+ int16_t doPinConfig;
+ /**< Flag indicating whether this instance has to be configured. This flag
+ can be altered with separate API (PinMuxConfigEnable()).
+ Default configuration will be set to TRUE, but can be altered for
+ different scenarios (like power management). */
+ pinmuxPerCfg_t* instPins;
+ /**< Pointer to list of pins corresponding to this instance */
+}pinmuxModuleCfg_t;
+
+/**
+ * \brief Structure defining the pin configuration of a board.
+ */
+typedef struct pinmuxBoardCfg
+{
+ int32_t moduleId;
+ /**< Module ID */
+ pinmuxModuleCfg_t* modulePinCfg;
+ /**< Pin config info of a module: #pinmuxModuleCfg_t */
+}pinmuxBoardCfg_t;
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif
diff --git a/packages/ti/board/src/am64x_evm/src_files_am64x_evm.mk b/packages/ti/board/src/am64x_evm/src_files_am64x_evm.mk
index fdfcd18f03457a7f6bb51a4f5fd4cd3ddeced1ab..13c98e63d23c9ecb037177c0a2d543954b60dcb1 100644 (file)
\r
# Common source files across all platforms and cores\r
SRCS_COMMON += board_init.c board_lld_init.c board_clock.c board_mmr.c board_pll.c\r
-SRCS_COMMON += board_ddr.c board_info.c board_ethernet_config.c board_pinmux.c board_serdes_cfg.c\r
+SRCS_COMMON += board_ddr.c board_info.c board_ethernet_config.c board_pinmux.c board_serdes_cfg.c AM64xx_pinmux_data.c\r
\r
PACKAGE_SRCS_COMMON = src/am64x_evm/src_files_am64x_evm.mk\r