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raw | patch | inline | side by side (parent: babab6d)
raw | patch | inline | side by side (parent: babab6d)
author | Praveen Rao <prao@ti.com> | |
Wed, 24 Feb 2021 03:03:41 +0000 (21:03 -0600) | ||
committer | Praveen Rao <prao@ti.com> | |
Mon, 15 Mar 2021 20:08:17 +0000 (15:08 -0500) |
Signed-off-by: Praveen Rao <prao@ti.com>
15 files changed:
index b529d45c47020475ce5499c05dc3fd65d6665552..96b45fa96cc73f4cef8b4a926a8ff6762287c56d 100644 (file)
/** \brief Default ring order ID */
#define UDMA_DEFAULT_RING_ORDER_ID (0U)
+#ifdef QNX_OS
+/** \brief Default channel address type */
+#define UDMA_DEFAULT_CH_ATYPE_INVALID (0xFF)
+#endif
+
/** \brief Default TX channel DMA priority */
#define UDMA_DEFAULT_TX_CH_DMA_PRIORITY \
(TISCI_MSG_VALUE_RM_UDMAP_CH_SCHED_PRIOR_MEDHIGH)
index 9b4dc952dad41c375ffc26f8c1a2fabfeaa3d323..88d1db100b00437ca605c96279238863f2933bc3 100644 (file)
#include <ti/drv/udma/src/udma_priv.h>
+#ifdef QNX_OS
+// #define QNX_UDMA_DEBUG_CSL_REGS
+#endif
+
/* ========================================================================== */
/* Macros & Typedefs */
/* ========================================================================== */
pUdmapRegs = &drvHandle->udmapRegs;
if(UDMA_INST_ID_MCU_0 == instId)
{
+#ifndef QNX_OS
pUdmapRegs->pGenCfgRegs = ((CSL_udmap_gcfgRegs *) UDMA_MCU_NAVSS0_UDMASS_UDMAP0_CFG_GCFG_BASE);
pUdmapRegs->pRxFlowCfgRegs = ((CSL_udmap_rxfcfgRegs *) UDMA_MCU_NAVSS0_UDMASS_UDMAP0_CFG_RFLOW_BASE);
pUdmapRegs->pTxChanCfgRegs = ((CSL_udmap_txccfgRegs *) UDMA_MCU_NAVSS0_UDMASS_UDMAP0_TCHAN_BASE);
pUdmapRegs->pRxChanCfgRegs = ((CSL_udmap_rxccfgRegs *) UDMA_MCU_NAVSS0_UDMASS_UDMAP0_RCHAN_BASE);
pUdmapRegs->pTxChanRtRegs = ((CSL_udmap_txcrtRegs *) UDMA_MCU_NAVSS0_UDMASS_UDMAP_TCHANRT_BASE);
pUdmapRegs->pRxChanRtRegs = ((CSL_udmap_rxcrtRegs *) UDMA_MCU_NAVSS0_UDMASS_UDMAP_RCHANRT_BASE);
+#else
+ pUdmapRegs->pGenCfgRegs = ((CSL_udmap_gcfgRegs *) mmap_device_memory(0,
+ CSL_MCU_NAVSS0_UDMASS_UDMAP0_CFG_GCFG_SIZE, PROT_READ|PROT_WRITE|PROT_NOCACHE, 0, UDMA_MCU_NAVSS0_UDMASS_UDMAP0_CFG_GCFG_BASE));
+ pUdmapRegs->pRxFlowCfgRegs = ((CSL_udmap_rxfcfgRegs *) mmap_device_memory(0,
+ CSL_MCU_NAVSS0_UDMASS_UDMAP0_CFG_RFLOW_SIZE, PROT_READ|PROT_WRITE|PROT_NOCACHE, 0, UDMA_MCU_NAVSS0_UDMASS_UDMAP0_CFG_RFLOW_BASE));
+ pUdmapRegs->pTxChanCfgRegs = ((CSL_udmap_txccfgRegs *) mmap_device_memory(0,
+ CSL_MCU_NAVSS0_UDMASS_UDMAP0_TCHAN_SIZE, PROT_READ|PROT_WRITE|PROT_NOCACHE, 0, UDMA_MCU_NAVSS0_UDMASS_UDMAP0_TCHAN_BASE));
+ pUdmapRegs->pRxChanCfgRegs = ((CSL_udmap_rxccfgRegs *) mmap_device_memory(0,
+ CSL_MCU_NAVSS0_UDMASS_UDMAP0_RCHAN_SIZE, PROT_READ|PROT_WRITE|PROT_NOCACHE, 0, UDMA_MCU_NAVSS0_UDMASS_UDMAP0_RCHAN_BASE));
+ pUdmapRegs->pTxChanRtRegs = ((CSL_udmap_txcrtRegs *) mmap_device_memory(0,
+ CSL_MCU_NAVSS0_UDMASS_UDMAP_TCHANRT_SIZE, PROT_READ|PROT_WRITE|PROT_NOCACHE, 0, UDMA_MCU_NAVSS0_UDMASS_UDMAP_TCHANRT_BASE));
+ pUdmapRegs->pRxChanRtRegs = ((CSL_udmap_rxcrtRegs *) mmap_device_memory(0,
+ CSL_MCU_NAVSS0_UDMASS_UDMAP_RCHANRT_SIZE, PROT_READ|PROT_WRITE|PROT_NOCACHE, 0, UDMA_MCU_NAVSS0_UDMASS_UDMAP_RCHANRT_BASE));
+
+#ifdef QNX_UDMA_DEBUG_CSL_REGS
+ printf( "%s: pUdmapRegs->pGenCfgRegs phys/0x%lx virt/0x%p size/%ld\n",__FUNCTION__,
+ UDMA_MCU_NAVSS0_UDMASS_UDMAP0_CFG_GCFG_BASE, pUdmapRegs->pGenCfgRegs, CSL_MCU_NAVSS0_UDMASS_UDMAP0_CFG_GCFG_SIZE);
+ printf( "%s: pUdmapRegs->pRxFlowCfgRegs phys/0x%lx virt/0x%p size/%ld\n",__FUNCTION__,
+ UDMA_MCU_NAVSS0_UDMASS_UDMAP0_CFG_RFLOW_BASE, pUdmapRegs->pRxFlowCfgRegs, CSL_MCU_NAVSS0_UDMASS_UDMAP0_CFG_RFLOW_SIZE);
+ printf( "%s: pUdmapRegs->pTxChanCfgRegs phys/0x%lx virt/0x%p size/%ld\n",__FUNCTION__,
+ UDMA_MCU_NAVSS0_UDMASS_UDMAP0_TCHAN_BASE, pUdmapRegs->pTxChanCfgRegs, CSL_MCU_NAVSS0_UDMASS_UDMAP0_TCHAN_SIZE);
+ printf( "%s: pUdmapRegs->pRxChanCfgRegs phys/0x%lx virt/0x%p size/%ld\n",__FUNCTION__,
+ UDMA_MCU_NAVSS0_UDMASS_UDMAP0_RCHAN_BASE, pUdmapRegs->pRxChanCfgRegs, CSL_MCU_NAVSS0_UDMASS_UDMAP0_RCHAN_SIZE);
+ printf( "%s: pUdmapRegs->pTxChanRtRegs phys/0x%lx virt/0x%p size/%ld\n",__FUNCTION__,
+ UDMA_MCU_NAVSS0_UDMASS_UDMAP_TCHANRT_BASE, pUdmapRegs->pTxChanRtRegs, CSL_MCU_NAVSS0_UDMASS_UDMAP_TCHANRT_SIZE);
+ printf( "%s: pUdmapRegs->pRxChanRtRegs phys/0x%lx virt/0x%p size/%ld\n",__FUNCTION__,
+ UDMA_MCU_NAVSS0_UDMASS_UDMAP_RCHANRT_BASE, pUdmapRegs->pRxChanRtRegs, CSL_MCU_NAVSS0_UDMASS_UDMAP_RCHANRT_SIZE);
+#endif
+
+#endif
drvHandle->trigGemOffset = CSL_NAVSS_GEM_MCU_UDMA_TRIGGER_OFFSET;
}
else
{
+#ifndef QNX_OS
pUdmapRegs->pGenCfgRegs = ((CSL_udmap_gcfgRegs *) UDMA_NAVSS0_UDMASS_UDMAP0_CFG_BASE);
pUdmapRegs->pRxFlowCfgRegs = ((CSL_udmap_rxfcfgRegs *) UDMA_NAVSS0_UDMASS_UDMAP0_CFG_RFLOW_BASE);
pUdmapRegs->pTxChanCfgRegs = ((CSL_udmap_txccfgRegs *) UDMA_NAVSS0_UDMASS_UDMAP0_CFG_TCHAN_BASE);
pUdmapRegs->pRxChanCfgRegs = ((CSL_udmap_rxccfgRegs *) UDMA_NAVSS0_UDMASS_UDMAP0_CFG_RCHAN_BASE);
pUdmapRegs->pTxChanRtRegs = ((CSL_udmap_txcrtRegs *) UDMA_NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT_BASE);
pUdmapRegs->pRxChanRtRegs = ((CSL_udmap_rxcrtRegs *) UDMA_NAVSS0_UDMASS_UDMAP0_CFG_RCHANRT_BASE);
+#else
+ pUdmapRegs->pGenCfgRegs = ((CSL_udmap_gcfgRegs *) mmap_device_memory(0,
+ CSL_NAVSS0_UDMASS_UDMAP0_CFG_SIZE, PROT_READ|PROT_WRITE|PROT_NOCACHE, 0, UDMA_NAVSS0_UDMASS_UDMAP0_CFG_BASE));
+ pUdmapRegs->pRxFlowCfgRegs = ((CSL_udmap_rxfcfgRegs *) mmap_device_memory(0,
+ CSL_NAVSS0_UDMASS_UDMAP0_CFG_RFLOW_SIZE, PROT_READ|PROT_WRITE|PROT_NOCACHE, 0, UDMA_NAVSS0_UDMASS_UDMAP0_CFG_RFLOW_BASE));
+ pUdmapRegs->pTxChanCfgRegs = ((CSL_udmap_txccfgRegs *) mmap_device_memory(0,
+ CSL_NAVSS0_UDMASS_UDMAP0_CFG_TCHAN_SIZE, PROT_READ|PROT_WRITE|PROT_NOCACHE, 0, UDMA_NAVSS0_UDMASS_UDMAP0_CFG_TCHAN_BASE));
+ pUdmapRegs->pRxChanCfgRegs = ((CSL_udmap_rxccfgRegs *) mmap_device_memory(0,
+ CSL_NAVSS0_UDMASS_UDMAP0_CFG_RCHAN_SIZE, PROT_READ|PROT_WRITE|PROT_NOCACHE, 0, UDMA_NAVSS0_UDMASS_UDMAP0_CFG_RCHAN_BASE));
+ pUdmapRegs->pTxChanRtRegs = ((CSL_udmap_txcrtRegs *) mmap_device_memory(0,
+ CSL_NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT_SIZE, PROT_READ|PROT_WRITE|PROT_NOCACHE, 0, UDMA_NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT_BASE));
+ pUdmapRegs->pRxChanRtRegs = ((CSL_udmap_rxcrtRegs *) mmap_device_memory(0,
+ CSL_NAVSS0_UDMASS_UDMAP0_CFG_RCHANRT_SIZE, PROT_READ|PROT_WRITE|PROT_NOCACHE, 0, UDMA_NAVSS0_UDMASS_UDMAP0_CFG_RCHANRT_BASE));
+
+#ifdef QNX_UDMA_DEBUG_CSL_REGS
+ printf( "%s: pUdmapRegs->pGenCfgRegs phys/0x%lx virt/0x%p size/%ld\n",__FUNCTION__,
+ CSL_NAVSS0_UDMASS_UDMAP0_CFG_BASE, pUdmapRegs->pGenCfgRegs, CSL_NAVSS0_UDMASS_UDMAP0_CFG_SIZE);
+ printf( "%s: pUdmapRegs->pRxFlowCfgRegs phys/0x%lx virt/0x%p size/%ld\n",__FUNCTION__,
+ UDMA_NAVSS0_UDMASS_UDMAP0_CFG_RFLOW_BASE, pUdmapRegs->pRxFlowCfgRegs, CSL_NAVSS0_UDMASS_UDMAP0_CFG_RFLOW_SIZE);
+ printf( "%s: pUdmapRegs->pTxChanCfgRegs phys/0x%lx virt/0x%p size/%ld\n",__FUNCTION__,
+ UDMA_NAVSS0_UDMASS_UDMAP0_CFG_TCHAN_BASE, pUdmapRegs->pTxChanCfgRegs, CSL_NAVSS0_UDMASS_UDMAP0_CFG_TCHAN_SIZE);
+ printf( "%s: pUdmapRegs->pRxChanCfgRegs phys/0x%lx virt/0x%p size/%ld\n",__FUNCTION__,
+ UDMA_NAVSS0_UDMASS_UDMAP0_CFG_RCHAN_BASE, pUdmapRegs->pRxChanCfgRegs, CSL_NAVSS0_UDMASS_UDMAP0_CFG_RCHAN_SIZE);
+ printf( "%s: pUdmapRegs->pTxChanRtRegs phys/0x%lx virt/0x%p size/%ld\n",__FUNCTION__,
+ UDMA_NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT_BASE, pUdmapRegs->pTxChanRtRegs, CSL_NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT_SIZE);
+ printf( "%s: pUdmapRegs->pRxChanRtRegs phys/0x%lx virt/0x%p size/%ld\n",__FUNCTION__,
+ UDMA_NAVSS0_UDMASS_UDMAP0_CFG_RCHANRT_BASE, pUdmapRegs->pRxChanRtRegs, CSL_NAVSS0_UDMASS_UDMAP0_CFG_RCHANRT_SIZE);
+#endif
+
+#endif
drvHandle->trigGemOffset = CSL_NAVSS_GEM_MAIN_UDMA_TRIGGER_OFFSET;
}
drvHandle->clecRegs = NULL;
pRaRegs = &drvHandle->raRegs;
if(UDMA_INST_ID_MCU_0 == instId)
{
+#ifndef QNX_OS
pRaRegs->pGlbRegs = (CSL_ringacc_gcfgRegs *) UDMA_MCU_NAVSS0_UDMASS_RINGACC0_CFG_GCFG_BASE;
pRaRegs->pCfgRegs = (CSL_ringacc_cfgRegs *) UDMA_MCU_NAVSS0_UDMASS_RINGACC0_CFG_BASE;
pRaRegs->pRtRegs = (CSL_ringacc_rtRegs *) UDMA_MCU_NAVSS0_UDMASS_RINGACC0_CFG_RT_BASE;
pRaRegs->pMonRegs = (CSL_ringacc_monitorRegs *) UDMA_MCU_NAVSS0_UDMASS_RINGACC0_CFG_MON_BASE;
pRaRegs->pFifoRegs = (CSL_ringacc_fifosRegs *) UDMA_MCU_NAVSS0_UDMASS_RINGACC0_FIFOS_BASE;
pRaRegs->pIscRegs = (CSL_ringacc_iscRegs *) UDMA_MCU_NAVSS0_UDMASS_RINGACC0_ISC_ISC_BASE;
+#else
+ pRaRegs->pGlbRegs = (CSL_ringacc_gcfgRegs *) mmap_device_memory(0,
+ CSL_MCU_NAVSS0_UDMASS_RINGACC0_CFG_GCFG_SIZE, PROT_READ|PROT_WRITE|PROT_NOCACHE, 0, UDMA_MCU_NAVSS0_UDMASS_RINGACC0_CFG_GCFG_BASE);
+ pRaRegs->pCfgRegs = (CSL_ringacc_cfgRegs *) mmap_device_memory(0,
+ CSL_MCU_NAVSS0_UDMASS_RINGACC0_CFG_SIZE, PROT_READ|PROT_WRITE|PROT_NOCACHE, 0, UDMA_MCU_NAVSS0_UDMASS_RINGACC0_CFG_BASE);
+ pRaRegs->pRtRegs = (CSL_ringacc_rtRegs *) mmap_device_memory(0,
+ CSL_MCU_NAVSS0_UDMASS_RINGACC0_CFG_RT_SIZE, PROT_READ|PROT_WRITE|PROT_NOCACHE, 0, UDMA_MCU_NAVSS0_UDMASS_RINGACC0_CFG_RT_BASE);
+ pRaRegs->pMonRegs = (CSL_ringacc_monitorRegs *) mmap_device_memory(0,
+ CSL_MCU_NAVSS0_UDMASS_RINGACC0_CFG_MON_SIZE, PROT_READ|PROT_WRITE|PROT_NOCACHE, 0, UDMA_MCU_NAVSS0_UDMASS_RINGACC0_CFG_MON_BASE);
+ pRaRegs->pFifoRegs = (CSL_ringacc_fifosRegs *) mmap_device_memory(0,
+ CSL_MCU_NAVSS0_UDMASS_RINGACC0_FIFOS_SIZE, PROT_READ|PROT_WRITE|PROT_NOCACHE, 0, UDMA_MCU_NAVSS0_UDMASS_RINGACC0_FIFOS_BASE);
+ pRaRegs->pIscRegs = (CSL_ringacc_iscRegs *) mmap_device_memory(0,
+ CSL_MCU_NAVSS0_UDMASS_RINGACC0_ISC_SIZE, PROT_READ|PROT_WRITE|PROT_NOCACHE, 0, UDMA_MCU_NAVSS0_UDMASS_RINGACC0_ISC_ISC_BASE);
+
+#ifdef QNX_UDMA_DEBUG_CSL_REGS
+ printf( "%s: pRaRegs->pGlbRegs phys/0x%lx virt/0x%p size/%ld\n",__FUNCTION__,
+ UDMA_MCU_NAVSS0_UDMASS_RINGACC0_CFG_GCFG_BASE, pRaRegs->pGlbRegs, CSL_MCU_NAVSS0_UDMASS_RINGACC0_CFG_GCFG_SIZE);
+ printf( "%s: pRaRegs->pCfgRegs phys/0x%lx virt/0x%p size/%ld\n",__FUNCTION__,
+ UDMA_MCU_NAVSS0_UDMASS_RINGACC0_CFG_BASE, pRaRegs->pCfgRegs, CSL_MCU_NAVSS0_UDMASS_RINGACC0_CFG_SIZE);
+ printf( "%s: pRaRegs->pRtRegs phys/0x%lx virt/0x%p size/%ld\n",__FUNCTION__,
+ UDMA_MCU_NAVSS0_UDMASS_RINGACC0_CFG_RT_BASE, pRaRegs->pRtRegs, CSL_MCU_NAVSS0_UDMASS_RINGACC0_CFG_RT_SIZE);
+ printf( "%s: pRaRegs->pMonRegs phys/0x%lx virt/0x%p size/%ld\n",__FUNCTION__,
+ UDMA_MCU_NAVSS0_UDMASS_RINGACC0_CFG_MON_BASE, pRaRegs->pMonRegs, CSL_MCU_NAVSS0_UDMASS_RINGACC0_CFG_MON_SIZE);
+ printf( "%s: pRaRegs->pFifoRegs phys/0x%lx virt/0x%p size/%ld\n",__FUNCTION__,
+ UDMA_MCU_NAVSS0_UDMASS_RINGACC0_FIFOS_BASE, pRaRegs->pFifoRegs, CSL_MCU_NAVSS0_UDMASS_RINGACC0_FIFOS_SIZE);
+ printf( "%s: pRaRegs->pIscRegs phys/0x%lx virt/0x%p size/%ld\n",__FUNCTION__,
+ UDMA_MCU_NAVSS0_UDMASS_RINGACC0_ISC_ISC_BASE, pRaRegs->pIscRegs, CSL_MCU_NAVSS0_UDMASS_RINGACC0_ISC_SIZE);
+#endif
+
+#endif
pRaRegs->maxRings = CSL_NAVSS_MCU_RINGACC_RING_CNT;
}
else
{
+#ifndef QNX_OS
pRaRegs->pGlbRegs = (CSL_ringacc_gcfgRegs *) UDMA_NAVSS0_UDMASS_RINGACC0_GCFG_BASE;
pRaRegs->pCfgRegs = (CSL_ringacc_cfgRegs *) UDMA_NAVSS0_UDMASS_RINGACC0_CFG_BASE;
pRaRegs->pRtRegs = (CSL_ringacc_rtRegs *) UDMA_NAVSS0_UDMASS_RINGACC0_CFG_RT_BASE;
pRaRegs->pMonRegs = (CSL_ringacc_monitorRegs *) UDMA_NAVSS0_UDMASS_RINGACC0_CFG_MON_BASE;
pRaRegs->pFifoRegs = (CSL_ringacc_fifosRegs *) UDMA_NAVSS0_UDMASS_RINGACC0_SRC_FIFOS_BASE;
pRaRegs->pIscRegs = (CSL_ringacc_iscRegs *) UDMA_NAVSS0_UDMASS_RINGACC0_ISC_ISC_BASE;
+#else
+ pRaRegs->pGlbRegs = (CSL_ringacc_gcfgRegs *) mmap_device_memory(0,
+ CSL_NAVSS0_UDMASS_RINGACC0_GCFG_SIZE, PROT_READ|PROT_WRITE|PROT_NOCACHE, 0, CSL_NAVSS0_UDMASS_RINGACC0_GCFG_BASE);
+ pRaRegs->pCfgRegs = (CSL_ringacc_cfgRegs *) mmap_device_memory(0,
+ CSL_NAVSS0_UDMASS_RINGACC0_CFG_SIZE, PROT_READ|PROT_WRITE|PROT_NOCACHE, 0, CSL_NAVSS0_UDMASS_RINGACC0_CFG_BASE);
+ pRaRegs->pRtRegs = (CSL_ringacc_rtRegs *) mmap_device_memory(0,
+ CSL_NAVSS0_UDMASS_RINGACC0_CFG_RT_SIZE, PROT_READ|PROT_WRITE|PROT_NOCACHE, 0, CSL_NAVSS0_UDMASS_RINGACC0_CFG_RT_BASE);
+ pRaRegs->pMonRegs = (CSL_ringacc_monitorRegs *) mmap_device_memory(0,
+ CSL_NAVSS0_UDMASS_RINGACC0_CFG_MON_SIZE, PROT_READ|PROT_WRITE|PROT_NOCACHE, 0, CSL_NAVSS0_UDMASS_RINGACC0_CFG_MON_BASE);
+ pRaRegs->pFifoRegs = (CSL_ringacc_fifosRegs *) mmap_device_memory(0,
+ CSL_NAVSS0_UDMASS_RINGACC0_SRC_FIFOS_SIZE, PROT_READ|PROT_WRITE|PROT_NOCACHE, 0, CSL_NAVSS0_UDMASS_RINGACC0_SRC_FIFOS_BASE);
+ pRaRegs->pIscRegs = (CSL_ringacc_iscRegs *) mmap_device_memory(0,
+ CSL_NAVSS0_UDMASS_RINGACC0_ISC_SIZE, PROT_READ|PROT_WRITE|PROT_NOCACHE, 0, CSL_NAVSS0_UDMASS_RINGACC0_ISC_BASE);
+
+#ifdef QNX_UDMA_DEBUG_CSL_REGS
+ printf( "%s: pRaRegs->pGlbRegs phys/0x%lx virt/0x%p size/%ld\n",__FUNCTION__,
+ UDMA_NAVSS0_UDMASS_RINGACC0_GCFG_BASE, pRaRegs->pGlbRegs, CSL_NAVSS0_UDMASS_RINGACC0_GCFG_SIZE);
+ printf( "%s: pRaRegs->pCfgRegs phys/0x%lx virt/0x%p size/%ld\n",__FUNCTION__,
+ UDMA_NAVSS0_UDMASS_RINGACC0_CFG_BASE, pRaRegs->pCfgRegs, CSL_NAVSS0_UDMASS_RINGACC0_CFG_SIZE);
+ printf( "%s: pRaRegs->pRtRegs phys/0x%lx virt/0x%p size/%ld\n",__FUNCTION__,
+ UDMA_NAVSS0_UDMASS_RINGACC0_CFG_RT_BASE, pRaRegs->pRtRegs, CSL_NAVSS0_UDMASS_RINGACC0_CFG_RT_SIZE);
+ printf( "%s: pRaRegs->pMonRegs phys/0x%lx virt/0x%p size/%ld\n",__FUNCTION__,
+ UDMA_NAVSS0_UDMASS_RINGACC0_CFG_MON_BASE, pRaRegs->pMonRegs, CSL_NAVSS0_UDMASS_RINGACC0_CFG_MON_SIZE);
+ printf( "%s: pRaRegs->pFifoRegs phys/0x%lx virt/0x%p size/%ld\n",__FUNCTION__,
+ CSL_NAVSS0_UDMASS_RINGACC0_SRC_FIFOS_BASE, pRaRegs->pFifoRegs, CSL_NAVSS0_UDMASS_RINGACC0_SRC_FIFOS_SIZE);
+ printf( "%s: pRaRegs->pIscRegs phys/0x%lx virt/0x%p size/%ld\n",__FUNCTION__,
+ UDMA_NAVSS0_UDMASS_RINGACC0_ISC_ISC_BASE, pRaRegs->pIscRegs, CSL_NAVSS0_UDMASS_RINGACC0_ISC_SIZE);
+#endif
+
+#endif
pRaRegs->maxRings = CSL_NAVSS_MAIN_RINGACC_RING_CNT;
}
pRaRegs->maxMonitors = CSL_RINGACC_MAX_MONITORS;
#if defined (BUILD_MCU1_0) || defined (BUILD_MCU1_1)
/* IA config init */
pIaRegs = &drvHandle->iaRegs;
+#ifndef QNX_OS
pIaRegs->pCfgRegs = (CSL_intaggr_cfgRegs *) UDMA_MCU_NAVSS0_UDMASS_INTA0_CFG_BASE;
pIaRegs->pImapRegs = (CSL_intaggr_imapRegs *) UDMA_MCU_NAVSS0_UDMASS_INTA0_IMAP_BASE;
pIaRegs->pIntrRegs = (CSL_intaggr_intrRegs *) UDMA_MCU_NAVSS0_UDMASS_INTA0_INTR_BASE;
pIaRegs->pMcastRegs = (CSL_intaggr_mcastRegs *) UDMA_MCU_NAVSS0_UDMASS_INTA0_MCAST_BASE;
pIaRegs->pGcntCfgRegs = (CSL_intaggr_gcntcfgRegs *) UDMA_MCU_NAVSS0_UDMASS_INTA0_GCNT_BASE;
pIaRegs->pGcntRtiRegs = (CSL_intaggr_gcntrtiRegs *) UDMA_MCU_NAVSS0_UDMASS_INTA0_GCNTRTI_BASE;
+#else
+ pIaRegs->pCfgRegs = (CSL_intaggr_cfgRegs *) mmap_device_memory(0,
+ CSL_MCU_NAVSS0_UDMASS_INTA0_CFG_SIZE, PROT_READ|PROT_WRITE|PROT_NOCACHE, 0, UDMA_MCU_NAVSS0_UDMASS_INTA0_CFG_BASE);
+ pIaRegs->pImapRegs = (CSL_intaggr_imapRegs *) mmap_device_memory(0,
+ CSL_MCU_NAVSS0_UDMASS_INTA0_IMAP_SIZE, PROT_READ|PROT_WRITE|PROT_NOCACHE, 0, UDMA_MCU_NAVSS0_UDMASS_INTA0_IMAP_BASE);
+ pIaRegs->pIntrRegs = (CSL_intaggr_intrRegs *) mmap_device_memory(0,
+ CSL_MCU_NAVSS0_UDMASS_INTA0_INTR_SIZE, PROT_READ|PROT_WRITE|PROT_NOCACHE, 0, UDMA_MCU_NAVSS0_UDMASS_INTA0_INTR_BASE);
+ pIaRegs->pL2gRegs = (CSL_intaggr_l2gRegs *) mmap_device_memory(0,
+ CSL_MCU_NAVSS0_PAR_UDMASS_UDMASS_INTA0_CFG_L2G_SIZE, PROT_READ|PROT_WRITE|PROT_NOCACHE, 0, UDMA_MCU_NAVSS0_PAR_UDMASS_UDMASS_INTA0_CFG_L2G_BASE);
+ pIaRegs->pMcastRegs = (CSL_intaggr_mcastRegs *) mmap_device_memory(0,
+ CSL_MCU_NAVSS0_UDMASS_INTA0_MCAST_SIZE, PROT_READ|PROT_WRITE|PROT_NOCACHE, 0, UDMA_MCU_NAVSS0_UDMASS_INTA0_MCAST_BASE);
+ pIaRegs->pGcntCfgRegs = (CSL_intaggr_gcntcfgRegs *) mmap_device_memory(0,
+ CSL_MCU_NAVSS0_UDMASS_INTA0_GCNT_SIZE, PROT_READ|PROT_WRITE|PROT_NOCACHE, 0, UDMA_MCU_NAVSS0_UDMASS_INTA0_GCNT_BASE);
+ pIaRegs->pGcntRtiRegs = (CSL_intaggr_gcntrtiRegs *) mmap_device_memory(0,
+ CSL_MCU_NAVSS0_UDMASS_INTA0_GCNTRTI_SIZE, PROT_READ|PROT_WRITE|PROT_NOCACHE, 0, UDMA_MCU_NAVSS0_UDMASS_INTA0_GCNTRTI_BASE);
+
+#ifdef QNX_UDMA_DEBUG_CSL_REGS
+ printf( "%s: pIaRegs->pCfgRegs phys/0x%lx virt/0x%p size/%ld\n",__FUNCTION__,
+ UDMA_MCU_NAVSS0_UDMASS_INTA0_CFG_BASE, pIaRegs->pCfgRegs, CSL_MCU_NAVSS0_UDMASS_INTA0_CFG_SIZE);
+ printf( "%s: pIaRegs->pImapRegs phys/0x%lx virt/0x%p size/%ld\n",__FUNCTION__,
+ UDMA_MCU_NAVSS0_UDMASS_INTA0_IMAP_BASE, pIaRegs->pImapRegs, CSL_MCU_NAVSS0_UDMASS_INTA0_IMAP_SIZE);
+ printf( "%s: pIaRegs->pIntrRegs phys/0x%lx virt/0x%p size/%ld\n",__FUNCTION__,
+ UDMA_MCU_NAVSS0_UDMASS_INTA0_INTR_BASE, pIaRegs->pIntrRegs, CSL_MCU_NAVSS0_UDMASS_INTA0_INTR_SIZE);
+ printf( "%s: pIaRegs->pL2gRegs phys/0x%lx virt/0x%p size/%ld\n",__FUNCTION__,
+ UDMA_MCU_NAVSS0_PAR_UDMASS_UDMASS_INTA0_CFG_L2G_BASE, pIaRegs->pL2gRegs, CSL_MCU_NAVSS0_PAR_UDMASS_UDMASS_INTA0_CFG_L2G_SIZE);
+ printf( "%s: pIaRegs->pMcastRegs phys/0x%lx virt/0x%p size/%ld\n",__FUNCTION__,
+ UDMA_MCU_NAVSS0_UDMASS_INTA0_MCAST_BASE, pIaRegs->pMcastRegs, CSL_MCU_NAVSS0_UDMASS_INTA0_MCAST_SIZE);
+ printf( "%s: pIaRegs->pGcntCfgRegs phys/0x%lx virt/0x%p size/%ld\n",__FUNCTION__,
+ UDMA_MCU_NAVSS0_UDMASS_INTA0_GCNT_BASE, pIaRegs->pGcntCfgRegs, CSL_MCU_NAVSS0_UDMASS_INTA0_GCNT_SIZE);
+ printf( "%s: pIaRegs->pGcntRtiRegs phys/0x%lx virt/0x%p size/%ld\n",__FUNCTION__,
+ UDMA_MCU_NAVSS0_UDMASS_INTA0_GCNTRTI_BASE, pIaRegs->pGcntRtiRegs, CSL_MCU_NAVSS0_UDMASS_INTA0_GCNTRTI_SIZE);
+#endif
+
+#endif
CSL_intaggrGetCfg(pIaRegs);
drvHandle->iaGemOffset = CSL_NAVSS_GEM_MCU_UDMA_INTA0_SEVI_OFFSET;
#else
/* IA config init */
pIaRegs = &drvHandle->iaRegs;
+#ifndef QNX_OS
pIaRegs->pCfgRegs = (CSL_intaggr_cfgRegs *) UDMA_NAVSS0_UDMASS_INTA0_CFG_BASE;
pIaRegs->pImapRegs = (CSL_intaggr_imapRegs *) UDMA_NAVSS0_UDMASS_INTA0_IMAP_BASE;
pIaRegs->pIntrRegs = (CSL_intaggr_intrRegs *) UDMA_NAVSS0_UDMASS_INTA0_CFG_INTR_BASE;
pIaRegs->pMcastRegs = (CSL_intaggr_mcastRegs *) UDMA_NAVSS0_UDMASS_INTA0_CFG_MCAST_BASE;
pIaRegs->pGcntCfgRegs = (CSL_intaggr_gcntcfgRegs *) UDMA_NAVSS0_UDMASS_INTA0_CFG_GCNTCFG_BASE;
pIaRegs->pGcntRtiRegs = (CSL_intaggr_gcntrtiRegs *) UDMA_NAVSS0_UDMASS_INTA0_CFG_GCNTRTI_BASE;
+#else
+ pIaRegs->pCfgRegs = (CSL_intaggr_cfgRegs *) mmap_device_memory(0,
+ CSL_NAVSS0_UDMASS_INTA0_CFG_SIZE, PROT_READ|PROT_WRITE|PROT_NOCACHE, 0, CSL_NAVSS0_UDMASS_INTA0_CFG_BASE);
+ pIaRegs->pImapRegs = (CSL_intaggr_imapRegs *) mmap_device_memory(0,
+ CSL_NAVSS0_UDMASS_INTA0_IMAP_SIZE, PROT_READ|PROT_WRITE|PROT_NOCACHE, 0, CSL_NAVSS0_UDMASS_INTA0_IMAP_BASE);
+ pIaRegs->pIntrRegs = (CSL_intaggr_intrRegs *) mmap_device_memory(0,
+ CSL_NAVSS0_UDMASS_INTA0_CFG_INTR_SIZE, PROT_READ|PROT_WRITE|PROT_NOCACHE, 0, CSL_NAVSS0_UDMASS_INTA0_CFG_INTR_BASE);
+ pIaRegs->pL2gRegs = (CSL_intaggr_l2gRegs *) mmap_device_memory(0,
+ CSL_NAVSS0_UDMASS_INTA0_CFG_L2G_SIZE, PROT_READ|PROT_WRITE|PROT_NOCACHE, 0, CSL_NAVSS0_UDMASS_INTA0_CFG_L2G_BASE);
+ pIaRegs->pMcastRegs = (CSL_intaggr_mcastRegs *) mmap_device_memory(0,
+ CSL_NAVSS0_UDMASS_INTA0_CFG_MCAST_SIZE, PROT_READ|PROT_WRITE|PROT_NOCACHE, 0, CSL_NAVSS0_UDMASS_INTA0_CFG_MCAST_BASE);
+ pIaRegs->pGcntCfgRegs = (CSL_intaggr_gcntcfgRegs *) mmap_device_memory(0,
+ CSL_NAVSS0_UDMASS_INTA0_CFG_GCNTCFG_SIZE, PROT_READ|PROT_WRITE|PROT_NOCACHE, 0, CSL_NAVSS0_UDMASS_INTA0_CFG_GCNTCFG_BASE);
+ pIaRegs->pGcntRtiRegs = (CSL_intaggr_gcntrtiRegs *) mmap_device_memory(0,
+ CSL_NAVSS0_UDMASS_INTA0_CFG_GCNTRTI_SIZE, PROT_READ|PROT_WRITE|PROT_NOCACHE, 0, CSL_NAVSS0_UDMASS_INTA0_CFG_GCNTRTI_BASE);
+
+#ifdef QNX_UDMA_DEBUG_CSL_REGS
+ printf( "%s: pIaRegs->pCfgRegs phys/0x%lx virt/0x%p size/%ld\n",__FUNCTION__,
+ CSL_NAVSS0_UDMASS_INTA0_CFG_BASE, pIaRegs->pCfgRegs, CSL_NAVSS0_UDMASS_INTA0_CFG_SIZE);
+ printf( "%s: pIaRegs->pImapRegs phys/0x%lx virt/0x%p size/%ld\n",__FUNCTION__,
+ CSL_NAVSS0_UDMASS_INTA0_IMAP_BASE, pIaRegs->pImapRegs, CSL_NAVSS0_UDMASS_INTA0_IMAP_SIZE);
+ printf( "%s: pIaRegs->pIntrRegs phys/0x%lx virt/0x%p size/%ld\n",__FUNCTION__,
+ CSL_NAVSS0_UDMASS_INTA0_CFG_INTR_BASE, pIaRegs->pIntrRegs, CSL_NAVSS0_UDMASS_INTA0_CFG_INTR_SIZE);
+ printf( "%s: pIaRegs->pL2gRegs phys/0x%lx virt/0x%p size/%ld\n",__FUNCTION__,
+ CSL_NAVSS0_UDMASS_INTA0_CFG_L2G_BASE, pIaRegs->pL2gRegs, CSL_NAVSS0_UDMASS_INTA0_CFG_L2G_SIZE);
+ printf( "%s: pIaRegs->pMcastRegs phys/0x%lx virt/0x%p size/%ld\n",__FUNCTION__,
+ CSL_NAVSS0_UDMASS_INTA0_CFG_MCAST_BASE, pIaRegs->pMcastRegs, CSL_NAVSS0_UDMASS_INTA0_CFG_MCAST_SIZE);
+ printf( "%s: pIaRegs->pGcntCfgRegs phys/0x%lx virt/0x%p size/%ld\n",__FUNCTION__,
+ CSL_NAVSS0_UDMASS_INTA0_CFG_GCNTCFG_BASE, pIaRegs->pGcntCfgRegs, CSL_NAVSS0_UDMASS_INTA0_CFG_GCNTCFG_SIZE);
+ printf( "%s: pIaRegs->pGcntRtiRegs phys/0x%lx virt/0x%p size/%ld\n",__FUNCTION__,
+ CSL_NAVSS0_UDMASS_INTA0_CFG_GCNTRTI_BASE, pIaRegs->pGcntRtiRegs, CSL_NAVSS0_UDMASS_INTA0_CFG_GCNTRTI_SIZE);
+#endif
+
+#endif
CSL_intaggrGetCfg(pIaRegs);
drvHandle->iaGemOffset = CSL_NAVSS_GEM_MAIN_UDMA_INTA0_SEVI_OFFSET;
pProxyTargetRing = &drvHandle->proxyTargetRing;
if(UDMA_INST_ID_MCU_0 == instId)
{
+#ifdef QNX_OS
+ pProxyTargetRing->pTargetRegs = (CSL_proxy_target0Regs *) (CSL_proxyRegs *) mmap_device_memory(0,
+ CSL_MCU_NAVSS0_PROXY0_TARGET0_DATA_SIZE, PROT_READ|PROT_WRITE|PROT_NOCACHE, 0, CSL_MCU_NAVSS0_PROXY0_TARGET0_DATA_BASE);
+
+#ifdef QNX_UDMA_DEBUG_CSL_REGS
+ printf( "%s: pTargetRegs phys/0x%lx virt/0x%p size/%ld\n",__FUNCTION__,
+ CSL_MCU_NAVSS0_PROXY0_TARGET0_DATA_BASE, pProxyTargetRing->pTargetRegs, CSL_MCU_NAVSS0_PROXY0_TARGET0_DATA_SIZE);
+#endif
+
+#else
pProxyTargetRing->pTargetRegs = (CSL_proxy_target0Regs *) CSL_MCU_NAVSS0_PROXY0_TARGET0_DATA_BASE;
+#endif
pProxyTargetRing->numChns = CSL_NAVSS_MCU_PROXY_TARGET_RINGACC0_NUM_CHANNELS;
pProxyTargetRing->chnSizeBytes = CSL_NAVSS_MCU_PROXY_TARGET_RINGACC0_NUM_CHANNEL_SIZE_BYTES;
+#ifdef QNX_OS
+ pProxyCfg->pGlbRegs = (CSL_proxyRegs *) mmap_device_memory(0,
+ CSL_MCU_NAVSS0_PROXY_CFG_GCFG_SIZE, PROT_READ|PROT_WRITE|PROT_NOCACHE, 0, CSL_MCU_NAVSS0_PROXY_CFG_GCFG_BASE);
+ pProxyCfg->pCfgRegs = (CSL_proxy_cfgRegs *) mmap_device_memory(0,
+ CSL_MCU_NAVSS0_PROXY0_BUF_CFG_SIZE, PROT_READ|PROT_WRITE|PROT_NOCACHE, 0, CSL_MCU_NAVSS0_PROXY0_BUF_CFG_BASE);
+
+#ifdef QNX_UDMA_DEBUG_CSL_REGS
+ printf( "%s: pProxyCfg->pGlbRegs phys/0x%lx virt/0x%p size/%ld\n",__FUNCTION__,
+ CSL_MCU_NAVSS0_PROXY_CFG_GCFG_BASE, pProxyCfg->pGlbRegs, CSL_MCU_NAVSS0_PROXY_CFG_GCFG_SIZE);
+ printf( "%s: pProxyCfg->pCfgRegs phys/0x%lx virt/0x%p size/%ld\n",__FUNCTION__,
+ CSL_MCU_NAVSS0_PROXY0_BUF_CFG_BASE, pProxyCfg->pCfgRegs, CSL_MCU_NAVSS0_PROXY0_BUF_CFG_SIZE);
+#endif
+
+#else
pProxyCfg->pGlbRegs = (CSL_proxyRegs *) CSL_MCU_NAVSS0_PROXY_CFG_GCFG_BASE;
pProxyCfg->pCfgRegs = (CSL_proxy_cfgRegs *) CSL_MCU_NAVSS0_PROXY0_BUF_CFG_BASE;
+#endif
pProxyCfg->bufferSizeBytes = CSL_NAVSS_MCU_PROXY_BUFFER_SIZE_BYTES;
pProxyCfg->numTargets = 1U;
pProxyCfg->pProxyTargetParams = pProxyTargetRing;
}
else
{
+#ifdef QNX_OS
+ pProxyTargetRing->pTargetRegs = (CSL_proxy_target0Regs *) (CSL_proxyRegs *) mmap_device_memory(0,
+ CSL_NAVSS0_PROXY_TARGET0_DATA_SIZE, PROT_READ|PROT_WRITE|PROT_NOCACHE, 0, CSL_NAVSS0_PROXY_TARGET0_DATA_BASE);
+
+#ifdef QNX_UDMA_DEBUG_CSL_REGS
+ printf( "%s: pTargetRegs phys/0x%lx virt/0x%p size/%ld\n",__FUNCTION__,
+ CSL_NAVSS0_PROXY_TARGET0_DATA_BASE, pProxyTargetRing->pTargetRegs, CSL_NAVSS0_PROXY_TARGET0_DATA_SIZE);
+#endif
+
+#else
pProxyTargetRing->pTargetRegs = (CSL_proxy_target0Regs *) CSL_NAVSS0_PROXY_TARGET0_DATA_BASE;
+#endif
pProxyTargetRing->numChns = CSL_NAVSS_MAIN_PROXY_TARGET_RINGACC0_NUM_CHANNELS;
pProxyTargetRing->chnSizeBytes = CSL_NAVSS_MAIN_PROXY_TARGET_RINGACC0_NUM_CHANNEL_SIZE_BYTES;
+#ifdef QNX_OS
+ pProxyCfg->pGlbRegs = (CSL_proxyRegs *) mmap_device_memory(0,
+ CSL_NAVSS0_PROXY0_CFG_BUF_CFG_SIZE, PROT_READ|PROT_WRITE|PROT_NOCACHE, 0, CSL_NAVSS0_PROXY0_CFG_BUF_CFG_BASE);
+ pProxyCfg->pCfgRegs = (CSL_proxy_cfgRegs *) mmap_device_memory(0,
+ CSL_NAVSS0_PROXY0_BUF_CFG_SIZE, PROT_READ|PROT_WRITE|PROT_NOCACHE, 0, CSL_NAVSS0_PROXY0_BUF_CFG_BASE);
+
+#ifdef QNX_UDMA_DEBUG_CSL_REGS
+ printf( "%s: pProxyCfg->pGlbRegs phys/0x%lx virt/0x%p size/%ld\n",__FUNCTION__,
+ CSL_NAVSS0_PROXY0_CFG_BUF_CFG_BASE, pProxyCfg->pGlbRegs, CSL_NAVSS0_PROXY0_CFG_BUF_CFG_SIZE);
+ printf( "%s: pProxyCfg->pCfgRegs phys/0x%lx virt/0x%p size/%ld\n",__FUNCTION__,
+ CSL_NAVSS0_PROXY0_BUF_CFG_BASE, pProxyCfg->pCfgRegs, CSL_NAVSS0_PROXY0_BUF_CFG_SIZE);
+#endif
+
+#else
pProxyCfg->pGlbRegs = (CSL_proxyRegs *) CSL_NAVSS0_PROXY0_CFG_BUF_CFG_BASE;
pProxyCfg->pCfgRegs = (CSL_proxy_cfgRegs *) CSL_NAVSS0_PROXY0_BUF_CFG_BASE;
+#endif
pProxyCfg->bufferSizeBytes = CSL_NAVSS_MAIN_PROXY_BUFFER_SIZE_BYTES;
pProxyCfg->numTargets = 1U;
pProxyCfg->pProxyTargetParams = pProxyTargetRing;
index f0d61f0dc8cf5428719754df46074e848fa0281c..ffb423d292ffaf4101af433c0532d5ef71a08c79 100755 (executable)
#include <ti/drv/udma/src/udma_priv.h>
+#ifdef QNX_OS
+// #define QNX_UDMA_DEBUG_CSL_REGS
+#endif
+
/* ========================================================================== */
/* Macros & Typedefs */
/* ========================================================================== */
CSL_ProxyTargetParams *pProxyTargetRing;
instId = drvHandle->initPrms.instId;
-
+
drvHandle->instType = UDMA_INST_TYPE_NORMAL;
-
+
#if defined (HOST_EMULATION)
gHost_udmap_gcfgRegs.CAP0 = 0x000B800F;
gHost_udmap_gcfgRegs.CAP1 = 0;
pUdmapRegs = &drvHandle->udmapRegs;
if(UDMA_INST_ID_MCU_0 == instId)
{
+#ifndef QNX_OS
pUdmapRegs->pGenCfgRegs = ((CSL_udmap_gcfgRegs *) UDMA_MCU_NAVSS0_UDMASS_UDMAP0_CFG_GCFG_BASE);
pUdmapRegs->pRxFlowCfgRegs = ((CSL_udmap_rxfcfgRegs *) UDMA_MCU_NAVSS0_UDMASS_UDMAP0_CFG_RFLOW_BASE);
pUdmapRegs->pTxChanCfgRegs = ((CSL_udmap_txccfgRegs *) UDMA_MCU_NAVSS0_UDMASS_UDMAP0_TCHAN_BASE);
pUdmapRegs->pRxChanCfgRegs = ((CSL_udmap_rxccfgRegs *) UDMA_MCU_NAVSS0_UDMASS_UDMAP0_RCHAN_BASE);
pUdmapRegs->pTxChanRtRegs = ((CSL_udmap_txcrtRegs *) UDMA_MCU_NAVSS0_UDMASS_UDMAP_TCHANRT_BASE);
pUdmapRegs->pRxChanRtRegs = ((CSL_udmap_rxcrtRegs *) UDMA_MCU_NAVSS0_UDMASS_UDMAP_RCHANRT_BASE);
+#else
+ pUdmapRegs->pGenCfgRegs = ((CSL_udmap_gcfgRegs *) mmap_device_memory(0,
+ CSL_MCU_NAVSS0_UDMASS_UDMAP0_CFG_GCFG_SIZE, PROT_READ|PROT_WRITE|PROT_NOCACHE, 0, UDMA_MCU_NAVSS0_UDMASS_UDMAP0_CFG_GCFG_BASE));
+ pUdmapRegs->pRxFlowCfgRegs = ((CSL_udmap_rxfcfgRegs *) mmap_device_memory(0,
+ CSL_MCU_NAVSS0_UDMASS_UDMAP0_CFG_RFLOW_SIZE, PROT_READ|PROT_WRITE|PROT_NOCACHE, 0, UDMA_MCU_NAVSS0_UDMASS_UDMAP0_CFG_RFLOW_BASE));
+ pUdmapRegs->pTxChanCfgRegs = ((CSL_udmap_txccfgRegs *) mmap_device_memory(0,
+ CSL_MCU_NAVSS0_UDMASS_UDMAP0_TCHAN_SIZE, PROT_READ|PROT_WRITE|PROT_NOCACHE, 0, UDMA_MCU_NAVSS0_UDMASS_UDMAP0_TCHAN_BASE));
+ pUdmapRegs->pRxChanCfgRegs = ((CSL_udmap_rxccfgRegs *) mmap_device_memory(0,
+ CSL_MCU_NAVSS0_UDMASS_UDMAP0_RCHAN_SIZE, PROT_READ|PROT_WRITE|PROT_NOCACHE, 0, UDMA_MCU_NAVSS0_UDMASS_UDMAP0_RCHAN_BASE));
+ pUdmapRegs->pTxChanRtRegs = ((CSL_udmap_txcrtRegs *) mmap_device_memory(0,
+ CSL_MCU_NAVSS0_UDMASS_UDMAP_TCHANRT_SIZE, PROT_READ|PROT_WRITE|PROT_NOCACHE, 0, UDMA_MCU_NAVSS0_UDMASS_UDMAP_TCHANRT_BASE));
+ pUdmapRegs->pRxChanRtRegs = ((CSL_udmap_rxcrtRegs *) mmap_device_memory(0,
+ CSL_MCU_NAVSS0_UDMASS_UDMAP_RCHANRT_SIZE, PROT_READ|PROT_WRITE|PROT_NOCACHE, 0, UDMA_MCU_NAVSS0_UDMASS_UDMAP_RCHANRT_BASE));
+
+#ifdef QNX_UDMA_DEBUG_CSL_REGS
+ printf( "%s: pUdmapRegs->pGenCfgRegs phys/0x%lx virt/0x%p size/%ld\n",__FUNCTION__,
+ UDMA_MCU_NAVSS0_UDMASS_UDMAP0_CFG_GCFG_BASE, pUdmapRegs->pGenCfgRegs, CSL_MCU_NAVSS0_UDMASS_UDMAP0_CFG_GCFG_SIZE);
+ printf( "%s: pUdmapRegs->pRxFlowCfgRegs phys/0x%lx virt/0x%p size/%ld\n",__FUNCTION__,
+ UDMA_MCU_NAVSS0_UDMASS_UDMAP0_CFG_RFLOW_BASE, pUdmapRegs->pRxFlowCfgRegs, CSL_MCU_NAVSS0_UDMASS_UDMAP0_CFG_RFLOW_SIZE);
+ printf( "%s: pUdmapRegs->pTxChanCfgRegs phys/0x%lx virt/0x%p size/%ld\n",__FUNCTION__,
+ UDMA_MCU_NAVSS0_UDMASS_UDMAP0_TCHAN_BASE, pUdmapRegs->pTxChanCfgRegs, CSL_MCU_NAVSS0_UDMASS_UDMAP0_TCHAN_SIZE);
+ printf( "%s: pUdmapRegs->pRxChanCfgRegs phys/0x%lx virt/0x%p size/%ld\n",__FUNCTION__,
+ UDMA_MCU_NAVSS0_UDMASS_UDMAP0_RCHAN_BASE, pUdmapRegs->pRxChanCfgRegs, CSL_MCU_NAVSS0_UDMASS_UDMAP0_RCHAN_SIZE);
+ printf( "%s: pUdmapRegs->pTxChanRtRegs phys/0x%lx virt/0x%p size/%ld\n",__FUNCTION__,
+ UDMA_MCU_NAVSS0_UDMASS_UDMAP_TCHANRT_BASE, pUdmapRegs->pTxChanRtRegs, CSL_MCU_NAVSS0_UDMASS_UDMAP_TCHANRT_SIZE);
+ printf( "%s: pUdmapRegs->pRxChanRtRegs phys/0x%lx virt/0x%p size/%ld\n",__FUNCTION__,
+ UDMA_MCU_NAVSS0_UDMASS_UDMAP_RCHANRT_BASE, pUdmapRegs->pRxChanRtRegs, CSL_MCU_NAVSS0_UDMASS_UDMAP_RCHANRT_SIZE);
+#endif
+
+#endif
drvHandle->trigGemOffset = CSL_NAVSS_GEM_MCU_UDMA_TRIGGER_OFFSET;
}
else
{
+#ifndef QNX_OS
pUdmapRegs->pGenCfgRegs = ((CSL_udmap_gcfgRegs *) UDMA_NAVSS0_UDMASS_UDMAP0_CFG_BASE);
pUdmapRegs->pRxFlowCfgRegs = ((CSL_udmap_rxfcfgRegs *) UDMA_NAVSS0_UDMASS_UDMAP0_CFG_RFLOW_BASE);
pUdmapRegs->pTxChanCfgRegs = ((CSL_udmap_txccfgRegs *) UDMA_NAVSS0_UDMASS_UDMAP0_CFG_TCHAN_BASE);
pUdmapRegs->pRxChanCfgRegs = ((CSL_udmap_rxccfgRegs *) UDMA_NAVSS0_UDMASS_UDMAP0_CFG_RCHAN_BASE);
pUdmapRegs->pTxChanRtRegs = ((CSL_udmap_txcrtRegs *) UDMA_NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT_BASE);
pUdmapRegs->pRxChanRtRegs = ((CSL_udmap_rxcrtRegs *) UDMA_NAVSS0_UDMASS_UDMAP0_CFG_RCHANRT_BASE);
+#else
+ pUdmapRegs->pGenCfgRegs = ((CSL_udmap_gcfgRegs *) mmap_device_memory(0,
+ CSL_NAVSS0_UDMASS_UDMAP0_CFG_SIZE, PROT_READ|PROT_WRITE|PROT_NOCACHE, 0, UDMA_NAVSS0_UDMASS_UDMAP0_CFG_BASE));
+ pUdmapRegs->pRxFlowCfgRegs = ((CSL_udmap_rxfcfgRegs *) mmap_device_memory(0,
+ CSL_NAVSS0_UDMASS_UDMAP0_CFG_RFLOW_SIZE, PROT_READ|PROT_WRITE|PROT_NOCACHE, 0, UDMA_NAVSS0_UDMASS_UDMAP0_CFG_RFLOW_BASE));
+ pUdmapRegs->pTxChanCfgRegs = ((CSL_udmap_txccfgRegs *) mmap_device_memory(0,
+ CSL_NAVSS0_UDMASS_UDMAP0_CFG_TCHAN_SIZE, PROT_READ|PROT_WRITE|PROT_NOCACHE, 0, UDMA_NAVSS0_UDMASS_UDMAP0_CFG_TCHAN_BASE));
+ pUdmapRegs->pRxChanCfgRegs = ((CSL_udmap_rxccfgRegs *) mmap_device_memory(0,
+ CSL_NAVSS0_UDMASS_UDMAP0_CFG_RCHAN_SIZE, PROT_READ|PROT_WRITE|PROT_NOCACHE, 0, UDMA_NAVSS0_UDMASS_UDMAP0_CFG_RCHAN_BASE));
+ pUdmapRegs->pTxChanRtRegs = ((CSL_udmap_txcrtRegs *) mmap_device_memory(0,
+ CSL_NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT_SIZE, PROT_READ|PROT_WRITE|PROT_NOCACHE, 0, UDMA_NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT_BASE));
+ pUdmapRegs->pRxChanRtRegs = ((CSL_udmap_rxcrtRegs *) mmap_device_memory(0,
+ CSL_NAVSS0_UDMASS_UDMAP0_CFG_RCHANRT_SIZE, PROT_READ|PROT_WRITE|PROT_NOCACHE, 0, UDMA_NAVSS0_UDMASS_UDMAP0_CFG_RCHANRT_BASE));
+
+#ifdef QNX_UDMA_DEBUG_CSL_REGS
+ printf( "%s: pUdmapRegs->pGenCfgRegs phys/0x%lx virt/0x%p size/%ld\n",__FUNCTION__,
+ CSL_NAVSS0_UDMASS_UDMAP0_CFG_BASE, pUdmapRegs->pGenCfgRegs, CSL_NAVSS0_UDMASS_UDMAP0_CFG_SIZE);
+ printf( "%s: pUdmapRegs->pRxFlowCfgRegs phys/0x%lx virt/0x%p size/%ld\n",__FUNCTION__,
+ UDMA_NAVSS0_UDMASS_UDMAP0_CFG_RFLOW_BASE, pUdmapRegs->pRxFlowCfgRegs, CSL_NAVSS0_UDMASS_UDMAP0_CFG_RFLOW_SIZE);
+ printf( "%s: pUdmapRegs->pTxChanCfgRegs phys/0x%lx virt/0x%p size/%ld\n",__FUNCTION__,
+ UDMA_NAVSS0_UDMASS_UDMAP0_CFG_TCHAN_BASE, pUdmapRegs->pTxChanCfgRegs, CSL_NAVSS0_UDMASS_UDMAP0_CFG_TCHAN_SIZE);
+ printf( "%s: pUdmapRegs->pRxChanCfgRegs phys/0x%lx virt/0x%p size/%ld\n",__FUNCTION__,
+ UDMA_NAVSS0_UDMASS_UDMAP0_CFG_RCHAN_BASE, pUdmapRegs->pRxChanCfgRegs, CSL_NAVSS0_UDMASS_UDMAP0_CFG_RCHAN_SIZE);
+ printf( "%s: pUdmapRegs->pTxChanRtRegs phys/0x%lx virt/0x%p size/%ld\n",__FUNCTION__,
+ UDMA_NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT_BASE, pUdmapRegs->pTxChanRtRegs, CSL_NAVSS0_UDMASS_UDMAP0_CFG_TCHANRT_SIZE);
+ printf( "%s: pUdmapRegs->pRxChanRtRegs phys/0x%lx virt/0x%p size/%ld\n",__FUNCTION__,
+ UDMA_NAVSS0_UDMASS_UDMAP0_CFG_RCHANRT_BASE, pUdmapRegs->pRxChanRtRegs, CSL_NAVSS0_UDMASS_UDMAP0_CFG_RCHANRT_SIZE);
+#endif
+
+#endif
drvHandle->trigGemOffset = CSL_NAVSS_GEM_MAIN_UDMA_TRIGGER_OFFSET;
}
+#ifndef QNX_OS
drvHandle->clecRegs = (CSL_CLEC_EVTRegs *) UDMA_COMPUTE_CLUSTER0_CLEC_REGS_BASE;
+#else
+ drvHandle->clecRegs = (CSL_CLEC_EVTRegs *) mmap_device_memory(0,
+ CSL_COMPUTE_CLUSTER0_CLEC_REGS_SIZE, PROT_READ|PROT_WRITE|PROT_NOCACHE, 0, UDMA_COMPUTE_CLUSTER0_CLEC_REGS_BASE);
+
+#ifdef QNX_UDMA_DEBUG_CSL_REGS
+ printf( "%s: clecRegs phys/0x%lx virt/0x%p size/%ld\n",__FUNCTION__,
+ UDMA_COMPUTE_CLUSTER0_CLEC_REGS_BASE, drvHandle->clecRegs, CSL_COMPUTE_CLUSTER0_CLEC_REGS_SIZE);
+#endif
+
+#endif
/* UDMA not present in CC QT build. Only DRU is present */
#ifndef CC_QT_BUILD
/* Fill other SOC specific parameters by reading from UDMA config
pRaRegs = &drvHandle->raRegs;
if(UDMA_INST_ID_MCU_0 == instId)
{
+#ifndef QNX_OS
pRaRegs->pGlbRegs = (CSL_ringacc_gcfgRegs *) UDMA_MCU_NAVSS0_UDMASS_RINGACC0_CFG_GCFG_BASE;
pRaRegs->pCfgRegs = (CSL_ringacc_cfgRegs *) UDMA_MCU_NAVSS0_UDMASS_RINGACC0_CFG_BASE;
pRaRegs->pRtRegs = (CSL_ringacc_rtRegs *) UDMA_MCU_NAVSS0_UDMASS_RINGACC0_CFG_RT_BASE;
pRaRegs->pMonRegs = (CSL_ringacc_monitorRegs *) UDMA_MCU_NAVSS0_UDMASS_RINGACC0_CFG_MON_BASE;
pRaRegs->pFifoRegs = (CSL_ringacc_fifosRegs *) UDMA_MCU_NAVSS0_UDMASS_RINGACC0_FIFOS_BASE;
pRaRegs->pIscRegs = (CSL_ringacc_iscRegs *) UDMA_MCU_NAVSS0_UDMASS_RINGACC0_ISC_ISC_BASE;
+#else
+ pRaRegs->pGlbRegs = (CSL_ringacc_gcfgRegs *) mmap_device_memory(0,
+ CSL_MCU_NAVSS0_UDMASS_RINGACC0_CFG_GCFG_SIZE, PROT_READ|PROT_WRITE|PROT_NOCACHE, 0, UDMA_MCU_NAVSS0_UDMASS_RINGACC0_CFG_GCFG_BASE);
+ pRaRegs->pCfgRegs = (CSL_ringacc_cfgRegs *) mmap_device_memory(0,
+ CSL_MCU_NAVSS0_UDMASS_RINGACC0_CFG_SIZE, PROT_READ|PROT_WRITE|PROT_NOCACHE, 0, UDMA_MCU_NAVSS0_UDMASS_RINGACC0_CFG_BASE);
+ pRaRegs->pRtRegs = (CSL_ringacc_rtRegs *) mmap_device_memory(0,
+ CSL_MCU_NAVSS0_UDMASS_RINGACC0_CFG_RT_SIZE, PROT_READ|PROT_WRITE|PROT_NOCACHE, 0, UDMA_MCU_NAVSS0_UDMASS_RINGACC0_CFG_RT_BASE);
+ pRaRegs->pMonRegs = (CSL_ringacc_monitorRegs *) mmap_device_memory(0,
+ CSL_MCU_NAVSS0_UDMASS_RINGACC0_CFG_MON_SIZE, PROT_READ|PROT_WRITE|PROT_NOCACHE, 0, UDMA_MCU_NAVSS0_UDMASS_RINGACC0_CFG_MON_BASE);
+ pRaRegs->pFifoRegs = (CSL_ringacc_fifosRegs *) mmap_device_memory(0,
+ CSL_MCU_NAVSS0_UDMASS_RINGACC0_FIFOS_SIZE, PROT_READ|PROT_WRITE|PROT_NOCACHE, 0, UDMA_MCU_NAVSS0_UDMASS_RINGACC0_FIFOS_BASE);
+ pRaRegs->pIscRegs = (CSL_ringacc_iscRegs *) mmap_device_memory(0,
+ CSL_MCU_NAVSS0_UDMASS_RINGACC0_ISC_SIZE, PROT_READ|PROT_WRITE|PROT_NOCACHE, 0, UDMA_MCU_NAVSS0_UDMASS_RINGACC0_ISC_ISC_BASE);
+
+#ifdef QNX_UDMA_DEBUG_CSL_REGS
+ printf( "%s: pRaRegs->pGlbRegs phys/0x%lx virt/0x%p size/%ld\n",__FUNCTION__,
+ UDMA_MCU_NAVSS0_UDMASS_RINGACC0_CFG_GCFG_BASE, pRaRegs->pGlbRegs, CSL_MCU_NAVSS0_UDMASS_RINGACC0_CFG_GCFG_SIZE);
+ printf( "%s: pRaRegs->pCfgRegs phys/0x%lx virt/0x%p size/%ld\n",__FUNCTION__,
+ UDMA_MCU_NAVSS0_UDMASS_RINGACC0_CFG_BASE, pRaRegs->pCfgRegs, CSL_MCU_NAVSS0_UDMASS_RINGACC0_CFG_SIZE);
+ printf( "%s: pRaRegs->pRtRegs phys/0x%lx virt/0x%p size/%ld\n",__FUNCTION__,
+ UDMA_MCU_NAVSS0_UDMASS_RINGACC0_CFG_RT_BASE, pRaRegs->pRtRegs, CSL_MCU_NAVSS0_UDMASS_RINGACC0_CFG_RT_SIZE);
+ printf( "%s: pRaRegs->pMonRegs phys/0x%lx virt/0x%p size/%ld\n",__FUNCTION__,
+ UDMA_MCU_NAVSS0_UDMASS_RINGACC0_CFG_MON_BASE, pRaRegs->pMonRegs, CSL_MCU_NAVSS0_UDMASS_RINGACC0_CFG_MON_SIZE);
+ printf( "%s: pRaRegs->pFifoRegs phys/0x%lx virt/0x%p size/%ld\n",__FUNCTION__,
+ UDMA_MCU_NAVSS0_UDMASS_RINGACC0_FIFOS_BASE, pRaRegs->pFifoRegs, CSL_MCU_NAVSS0_UDMASS_RINGACC0_FIFOS_SIZE);
+ printf( "%s: pRaRegs->pIscRegs phys/0x%lx virt/0x%p size/%ld\n",__FUNCTION__,
+ UDMA_MCU_NAVSS0_UDMASS_RINGACC0_ISC_ISC_BASE, pRaRegs->pIscRegs, CSL_MCU_NAVSS0_UDMASS_RINGACC0_ISC_SIZE);
+#endif
+
+#endif
pRaRegs->maxRings = CSL_NAVSS_MCU_RINGACC_RING_CNT;
}
else
{
+#ifndef QNX_OS
pRaRegs->pGlbRegs = (CSL_ringacc_gcfgRegs *) UDMA_NAVSS0_UDMASS_RINGACC0_GCFG_BASE;
pRaRegs->pCfgRegs = (CSL_ringacc_cfgRegs *) UDMA_NAVSS0_UDMASS_RINGACC0_CFG_BASE;
pRaRegs->pRtRegs = (CSL_ringacc_rtRegs *) UDMA_NAVSS0_UDMASS_RINGACC0_CFG_RT_BASE;
pRaRegs->pMonRegs = (CSL_ringacc_monitorRegs *) UDMA_NAVSS0_UDMASS_RINGACC0_CFG_MON_BASE;
pRaRegs->pFifoRegs = (CSL_ringacc_fifosRegs *) UDMA_NAVSS0_UDMASS_RINGACC0_SRC_FIFOS_BASE;
pRaRegs->pIscRegs = (CSL_ringacc_iscRegs *) UDMA_NAVSS0_UDMASS_RINGACC0_ISC_ISC_BASE;
+#else
+ pRaRegs->pGlbRegs = (CSL_ringacc_gcfgRegs *) mmap_device_memory(0,
+ CSL_NAVSS0_UDMASS_RINGACC0_GCFG_SIZE, PROT_READ|PROT_WRITE|PROT_NOCACHE, 0, CSL_NAVSS0_UDMASS_RINGACC0_GCFG_BASE);
+ pRaRegs->pCfgRegs = (CSL_ringacc_cfgRegs *) mmap_device_memory(0,
+ CSL_NAVSS0_UDMASS_RINGACC0_CFG_SIZE, PROT_READ|PROT_WRITE|PROT_NOCACHE, 0, CSL_NAVSS0_UDMASS_RINGACC0_CFG_BASE);
+ pRaRegs->pRtRegs = (CSL_ringacc_rtRegs *) mmap_device_memory(0,
+ CSL_NAVSS0_UDMASS_RINGACC0_CFG_RT_SIZE, PROT_READ|PROT_WRITE|PROT_NOCACHE, 0, CSL_NAVSS0_UDMASS_RINGACC0_CFG_RT_BASE);
+ pRaRegs->pMonRegs = (CSL_ringacc_monitorRegs *) mmap_device_memory(0,
+ CSL_NAVSS0_UDMASS_RINGACC0_CFG_MON_SIZE, PROT_READ|PROT_WRITE|PROT_NOCACHE, 0, CSL_NAVSS0_UDMASS_RINGACC0_CFG_MON_BASE);
+ pRaRegs->pFifoRegs = (CSL_ringacc_fifosRegs *) mmap_device_memory(0,
+ CSL_NAVSS0_UDMASS_RINGACC0_SRC_FIFOS_SIZE, PROT_READ|PROT_WRITE|PROT_NOCACHE, 0, CSL_NAVSS0_UDMASS_RINGACC0_SRC_FIFOS_BASE);
+ pRaRegs->pIscRegs = (CSL_ringacc_iscRegs *) mmap_device_memory(0,
+ CSL_NAVSS0_UDMASS_RINGACC0_ISC_SIZE, PROT_READ|PROT_WRITE|PROT_NOCACHE, 0, CSL_NAVSS0_UDMASS_RINGACC0_ISC_BASE);
+
+#ifdef QNX_UDMA_DEBUG_CSL_REGS
+ printf( "%s: pRaRegs->pGlbRegs phys/0x%lx virt/0x%p size/%ld\n",__FUNCTION__,
+ UDMA_NAVSS0_UDMASS_RINGACC0_GCFG_BASE, pRaRegs->pGlbRegs, CSL_NAVSS0_UDMASS_RINGACC0_GCFG_SIZE);
+ printf( "%s: pRaRegs->pCfgRegs phys/0x%lx virt/0x%p size/%ld\n",__FUNCTION__,
+ UDMA_NAVSS0_UDMASS_RINGACC0_CFG_BASE, pRaRegs->pCfgRegs, CSL_NAVSS0_UDMASS_RINGACC0_CFG_SIZE);
+ printf( "%s: pRaRegs->pRtRegs phys/0x%lx virt/0x%p size/%ld\n",__FUNCTION__,
+ UDMA_NAVSS0_UDMASS_RINGACC0_CFG_RT_BASE, pRaRegs->pRtRegs, CSL_NAVSS0_UDMASS_RINGACC0_CFG_RT_SIZE);
+ printf( "%s: pRaRegs->pMonRegs phys/0x%lx virt/0x%p size/%ld\n",__FUNCTION__,
+ UDMA_NAVSS0_UDMASS_RINGACC0_CFG_MON_BASE, pRaRegs->pMonRegs, CSL_NAVSS0_UDMASS_RINGACC0_CFG_MON_SIZE);
+ printf( "%s: pRaRegs->pFifoRegs phys/0x%lx virt/0x%p size/%ld\n",__FUNCTION__,
+ CSL_NAVSS0_UDMASS_RINGACC0_SRC_FIFOS_BASE, pRaRegs->pFifoRegs, CSL_NAVSS0_UDMASS_RINGACC0_SRC_FIFOS_SIZE);
+ printf( "%s: pRaRegs->pIscRegs phys/0x%lx virt/0x%p size/%ld\n",__FUNCTION__,
+ UDMA_NAVSS0_UDMASS_RINGACC0_ISC_ISC_BASE, pRaRegs->pIscRegs, CSL_NAVSS0_UDMASS_RINGACC0_ISC_SIZE);
+#endif
+
+#endif
pRaRegs->maxRings = CSL_NAVSS_MAIN_RINGACC_RING_CNT;
}
pRaRegs->maxMonitors = CSL_RINGACC_MAX_MONITORS;
#if defined (BUILD_MCU1_0) || defined (BUILD_MCU1_1)
/* IA config init */
pIaRegs = &drvHandle->iaRegs;
+#ifndef QNX_OS
pIaRegs->pCfgRegs = (CSL_intaggr_cfgRegs *) UDMA_MCU_NAVSS0_UDMASS_INTA0_CFG_BASE;
pIaRegs->pImapRegs = (CSL_intaggr_imapRegs *) UDMA_MCU_NAVSS0_UDMASS_INTA0_IMAP_BASE;
pIaRegs->pIntrRegs = (CSL_intaggr_intrRegs *) UDMA_MCU_NAVSS0_UDMASS_INTA0_INTR_BASE;
pIaRegs->pMcastRegs = (CSL_intaggr_mcastRegs *) UDMA_MCU_NAVSS0_UDMASS_INTA0_MCAST_BASE;
pIaRegs->pGcntCfgRegs = (CSL_intaggr_gcntcfgRegs *) UDMA_MCU_NAVSS0_UDMASS_INTA0_GCNT_BASE;
pIaRegs->pGcntRtiRegs = (CSL_intaggr_gcntrtiRegs *) UDMA_MCU_NAVSS0_UDMASS_INTA0_GCNTRTI_BASE;
+#else
+ pIaRegs->pCfgRegs = (CSL_intaggr_cfgRegs *) mmap_device_memory(0,
+ CSL_MCU_NAVSS0_UDMASS_INTA0_CFG_SIZE, PROT_READ|PROT_WRITE|PROT_NOCACHE, 0, UDMA_MCU_NAVSS0_UDMASS_INTA0_CFG_BASE);
+ pIaRegs->pImapRegs = (CSL_intaggr_imapRegs *) mmap_device_memory(0,
+ CSL_MCU_NAVSS0_UDMASS_INTA0_IMAP_SIZE, PROT_READ|PROT_WRITE|PROT_NOCACHE, 0, UDMA_MCU_NAVSS0_UDMASS_INTA0_IMAP_BASE);
+ pIaRegs->pIntrRegs = (CSL_intaggr_intrRegs *) mmap_device_memory(0,
+ CSL_MCU_NAVSS0_UDMASS_INTA0_INTR_SIZE, PROT_READ|PROT_WRITE|PROT_NOCACHE, 0, UDMA_MCU_NAVSS0_UDMASS_INTA0_INTR_BASE);
+ pIaRegs->pL2gRegs = (CSL_intaggr_l2gRegs *) mmap_device_memory(0,
+ CSL_MCU_NAVSS0_PAR_UDMASS_UDMASS_INTA0_CFG_L2G_SIZE, PROT_READ|PROT_WRITE|PROT_NOCACHE, 0, UDMA_MCU_NAVSS0_PAR_UDMASS_UDMASS_INTA0_CFG_L2G_BASE);
+ pIaRegs->pMcastRegs = (CSL_intaggr_mcastRegs *) mmap_device_memory(0,
+ CSL_MCU_NAVSS0_UDMASS_INTA0_MCAST_SIZE, PROT_READ|PROT_WRITE|PROT_NOCACHE, 0, UDMA_MCU_NAVSS0_UDMASS_INTA0_MCAST_BASE);
+ pIaRegs->pGcntCfgRegs = (CSL_intaggr_gcntcfgRegs *) mmap_device_memory(0,
+ CSL_MCU_NAVSS0_UDMASS_INTA0_GCNT_SIZE, PROT_READ|PROT_WRITE|PROT_NOCACHE, 0, UDMA_MCU_NAVSS0_UDMASS_INTA0_GCNT_BASE);
+ pIaRegs->pGcntRtiRegs = (CSL_intaggr_gcntrtiRegs *) mmap_device_memory(0,
+ CSL_MCU_NAVSS0_UDMASS_INTA0_GCNTRTI_SIZE, PROT_READ|PROT_WRITE|PROT_NOCACHE, 0, UDMA_MCU_NAVSS0_UDMASS_INTA0_GCNTRTI_BASE);
+
+#ifdef QNX_UDMA_DEBUG_CSL_REGS
+ printf( "%s: pIaRegs->pCfgRegs phys/0x%lx virt/0x%p size/%ld\n",__FUNCTION__,
+ UDMA_MCU_NAVSS0_UDMASS_INTA0_CFG_BASE, pIaRegs->pCfgRegs, CSL_MCU_NAVSS0_UDMASS_INTA0_CFG_SIZE);
+ printf( "%s: pIaRegs->pImapRegs phys/0x%lx virt/0x%p size/%ld\n",__FUNCTION__,
+ UDMA_MCU_NAVSS0_UDMASS_INTA0_IMAP_BASE, pIaRegs->pImapRegs, CSL_MCU_NAVSS0_UDMASS_INTA0_IMAP_SIZE);
+ printf( "%s: pIaRegs->pIntrRegs phys/0x%lx virt/0x%p size/%ld\n",__FUNCTION__,
+ UDMA_MCU_NAVSS0_UDMASS_INTA0_INTR_BASE, pIaRegs->pIntrRegs, CSL_MCU_NAVSS0_UDMASS_INTA0_INTR_SIZE);
+ printf( "%s: pIaRegs->pL2gRegs phys/0x%lx virt/0x%p size/%ld\n",__FUNCTION__,
+ UDMA_MCU_NAVSS0_PAR_UDMASS_UDMASS_INTA0_CFG_L2G_BASE, pIaRegs->pL2gRegs, CSL_MCU_NAVSS0_PAR_UDMASS_UDMASS_INTA0_CFG_L2G_SIZE);
+ printf( "%s: pIaRegs->pMcastRegs phys/0x%lx virt/0x%p size/%ld\n",__FUNCTION__,
+ UDMA_MCU_NAVSS0_UDMASS_INTA0_MCAST_BASE, pIaRegs->pMcastRegs, CSL_MCU_NAVSS0_UDMASS_INTA0_MCAST_SIZE);
+ printf( "%s: pIaRegs->pGcntCfgRegs phys/0x%lx virt/0x%p size/%ld\n",__FUNCTION__,
+ UDMA_MCU_NAVSS0_UDMASS_INTA0_GCNT_BASE, pIaRegs->pGcntCfgRegs, CSL_MCU_NAVSS0_UDMASS_INTA0_GCNT_SIZE);
+ printf( "%s: pIaRegs->pGcntRtiRegs phys/0x%lx virt/0x%p size/%ld\n",__FUNCTION__,
+ UDMA_MCU_NAVSS0_UDMASS_INTA0_GCNTRTI_BASE, pIaRegs->pGcntRtiRegs, CSL_MCU_NAVSS0_UDMASS_INTA0_GCNTRTI_SIZE);
+#endif
+
+#endif
CSL_intaggrGetCfg(pIaRegs);
drvHandle->iaGemOffset = CSL_NAVSS_GEM_MCU_UDMA_INTA0_SEVI_OFFSET;
#else
/* IA config init */
pIaRegs = &drvHandle->iaRegs;
+#ifndef QNX_OS
pIaRegs->pCfgRegs = (CSL_intaggr_cfgRegs *) UDMA_NAVSS0_UDMASS_INTA0_CFG_BASE;
pIaRegs->pImapRegs = (CSL_intaggr_imapRegs *) UDMA_NAVSS0_UDMASS_INTA0_IMAP_BASE;
pIaRegs->pIntrRegs = (CSL_intaggr_intrRegs *) UDMA_NAVSS0_UDMASS_INTA0_CFG_INTR_BASE;
pIaRegs->pMcastRegs = (CSL_intaggr_mcastRegs *) UDMA_NAVSS0_UDMASS_INTA0_CFG_MCAST_BASE;
pIaRegs->pGcntCfgRegs = (CSL_intaggr_gcntcfgRegs *) UDMA_NAVSS0_UDMASS_INTA0_CFG_GCNTCFG_BASE;
pIaRegs->pGcntRtiRegs = (CSL_intaggr_gcntrtiRegs *) UDMA_NAVSS0_UDMASS_INTA0_CFG_GCNTRTI_BASE;
+#else
+ pIaRegs->pCfgRegs = (CSL_intaggr_cfgRegs *) mmap_device_memory(0,
+ CSL_NAVSS0_UDMASS_INTA0_CFG_SIZE, PROT_READ|PROT_WRITE|PROT_NOCACHE, 0, CSL_NAVSS0_UDMASS_INTA0_CFG_BASE);
+ pIaRegs->pImapRegs = (CSL_intaggr_imapRegs *) mmap_device_memory(0,
+ CSL_NAVSS0_UDMASS_INTA0_IMAP_SIZE, PROT_READ|PROT_WRITE|PROT_NOCACHE, 0, CSL_NAVSS0_UDMASS_INTA0_IMAP_BASE);
+ pIaRegs->pIntrRegs = (CSL_intaggr_intrRegs *) mmap_device_memory(0,
+ CSL_NAVSS0_UDMASS_INTA0_CFG_INTR_SIZE, PROT_READ|PROT_WRITE|PROT_NOCACHE, 0, CSL_NAVSS0_UDMASS_INTA0_CFG_INTR_BASE);
+ pIaRegs->pL2gRegs = (CSL_intaggr_l2gRegs *) mmap_device_memory(0,
+ CSL_NAVSS0_UDMASS_INTA0_CFG_L2G_SIZE, PROT_READ|PROT_WRITE|PROT_NOCACHE, 0, CSL_NAVSS0_UDMASS_INTA0_CFG_L2G_BASE);
+ pIaRegs->pMcastRegs = (CSL_intaggr_mcastRegs *) mmap_device_memory(0,
+ CSL_NAVSS0_UDMASS_INTA0_CFG_MCAST_SIZE, PROT_READ|PROT_WRITE|PROT_NOCACHE, 0, CSL_NAVSS0_UDMASS_INTA0_CFG_MCAST_BASE);
+ pIaRegs->pGcntCfgRegs = (CSL_intaggr_gcntcfgRegs *) mmap_device_memory(0,
+ CSL_NAVSS0_UDMASS_INTA0_CFG_GCNTCFG_SIZE, PROT_READ|PROT_WRITE|PROT_NOCACHE, 0, CSL_NAVSS0_UDMASS_INTA0_CFG_GCNTCFG_BASE);
+ pIaRegs->pGcntRtiRegs = (CSL_intaggr_gcntrtiRegs *) mmap_device_memory(0,
+ CSL_NAVSS0_UDMASS_INTA0_CFG_GCNTRTI_SIZE, PROT_READ|PROT_WRITE|PROT_NOCACHE, 0, CSL_NAVSS0_UDMASS_INTA0_CFG_GCNTRTI_BASE);
+
+#ifdef QNX_UDMA_DEBUG_CSL_REGS
+ printf( "%s: pIaRegs->pCfgRegs phys/0x%lx virt/0x%p size/%ld\n",__FUNCTION__,
+ CSL_NAVSS0_UDMASS_INTA0_CFG_BASE, pIaRegs->pCfgRegs, CSL_NAVSS0_UDMASS_INTA0_CFG_SIZE);
+ printf( "%s: pIaRegs->pImapRegs phys/0x%lx virt/0x%p size/%ld\n",__FUNCTION__,
+ CSL_NAVSS0_UDMASS_INTA0_IMAP_BASE, pIaRegs->pImapRegs, CSL_NAVSS0_UDMASS_INTA0_IMAP_SIZE);
+ printf( "%s: pIaRegs->pIntrRegs phys/0x%lx virt/0x%p size/%ld\n",__FUNCTION__,
+ CSL_NAVSS0_UDMASS_INTA0_CFG_INTR_BASE, pIaRegs->pIntrRegs, CSL_NAVSS0_UDMASS_INTA0_CFG_INTR_SIZE);
+ printf( "%s: pIaRegs->pL2gRegs phys/0x%lx virt/0x%p size/%ld\n",__FUNCTION__,
+ CSL_NAVSS0_UDMASS_INTA0_CFG_L2G_BASE, pIaRegs->pL2gRegs, CSL_NAVSS0_UDMASS_INTA0_CFG_L2G_SIZE);
+ printf( "%s: pIaRegs->pMcastRegs phys/0x%lx virt/0x%p size/%ld\n",__FUNCTION__,
+ CSL_NAVSS0_UDMASS_INTA0_CFG_MCAST_BASE, pIaRegs->pMcastRegs, CSL_NAVSS0_UDMASS_INTA0_CFG_MCAST_SIZE);
+ printf( "%s: pIaRegs->pGcntCfgRegs phys/0x%lx virt/0x%p size/%ld\n",__FUNCTION__,
+ CSL_NAVSS0_UDMASS_INTA0_CFG_GCNTCFG_BASE, pIaRegs->pGcntCfgRegs, CSL_NAVSS0_UDMASS_INTA0_CFG_GCNTCFG_SIZE);
+ printf( "%s: pIaRegs->pGcntRtiRegs phys/0x%lx virt/0x%p size/%ld\n",__FUNCTION__,
+ CSL_NAVSS0_UDMASS_INTA0_CFG_GCNTRTI_BASE, pIaRegs->pGcntRtiRegs, CSL_NAVSS0_UDMASS_INTA0_CFG_GCNTRTI_SIZE);
+#endif
+
+#endif
/* UDMA not present in CC QT build. Only DRU is present */
#ifndef CC_QT_BUILD
CSL_intaggrGetCfg(pIaRegs);
pProxyTargetRing = &drvHandle->proxyTargetRing;
if(UDMA_INST_ID_MCU_0 == instId)
{
+#ifdef QNX_OS
+ pProxyTargetRing->pTargetRegs = (CSL_proxy_target0Regs *) (CSL_proxyRegs *) mmap_device_memory(0,
+ CSL_MCU_NAVSS0_PROXY0_TARGET0_DATA_SIZE, PROT_READ|PROT_WRITE|PROT_NOCACHE, 0, CSL_MCU_NAVSS0_PROXY0_TARGET0_DATA_BASE);
+
+#ifdef QNX_UDMA_DEBUG_CSL_REGS
+ printf( "%s: pTargetRegs phys/0x%lx virt/0x%p size/%ld\n",__FUNCTION__,
+ CSL_MCU_NAVSS0_PROXY0_TARGET0_DATA_BASE, pProxyTargetRing->pTargetRegs, CSL_MCU_NAVSS0_PROXY0_TARGET0_DATA_SIZE);
+#endif
+
+#else
pProxyTargetRing->pTargetRegs = (CSL_proxy_target0Regs *) CSL_MCU_NAVSS0_PROXY0_TARGET0_DATA_BASE;
+#endif
pProxyTargetRing->numChns = CSL_NAVSS_MCU_PROXY_TARGET_RINGACC0_NUM_CHANNELS;
pProxyTargetRing->chnSizeBytes = CSL_NAVSS_MCU_PROXY_TARGET_RINGACC0_NUM_CHANNEL_SIZE_BYTES;
+#ifdef QNX_OS
+ pProxyCfg->pGlbRegs = (CSL_proxyRegs *) mmap_device_memory(0,
+ CSL_MCU_NAVSS0_PROXY_CFG_GCFG_SIZE, PROT_READ|PROT_WRITE|PROT_NOCACHE, 0, CSL_MCU_NAVSS0_PROXY_CFG_GCFG_BASE);
+ pProxyCfg->pCfgRegs = (CSL_proxy_cfgRegs *) mmap_device_memory(0,
+ CSL_MCU_NAVSS0_PROXY0_BUF_CFG_SIZE, PROT_READ|PROT_WRITE|PROT_NOCACHE, 0, CSL_MCU_NAVSS0_PROXY0_BUF_CFG_BASE);
+
+#ifdef QNX_UDMA_DEBUG_CSL_REGS
+ printf( "%s: pProxyCfg->pGlbRegs phys/0x%lx virt/0x%p size/%ld\n",__FUNCTION__,
+ CSL_MCU_NAVSS0_PROXY_CFG_GCFG_BASE, pProxyCfg->pGlbRegs, CSL_MCU_NAVSS0_PROXY_CFG_GCFG_SIZE);
+ printf( "%s: pProxyCfg->pCfgRegs phys/0x%lx virt/0x%p size/%ld\n",__FUNCTION__,
+ CSL_MCU_NAVSS0_PROXY0_BUF_CFG_BASE, pProxyCfg->pCfgRegs, CSL_MCU_NAVSS0_PROXY0_BUF_CFG_SIZE);
+#endif
+
+#else
pProxyCfg->pGlbRegs = (CSL_proxyRegs *) CSL_MCU_NAVSS0_PROXY_CFG_GCFG_BASE;
pProxyCfg->pCfgRegs = (CSL_proxy_cfgRegs *) CSL_MCU_NAVSS0_PROXY0_BUF_CFG_BASE;
+#endif
pProxyCfg->bufferSizeBytes = CSL_NAVSS_MCU_PROXY_BUFFER_SIZE_BYTES;
pProxyCfg->numTargets = 1U;
pProxyCfg->pProxyTargetParams = pProxyTargetRing;
}
else
{
+#ifdef QNX_OS
+ pProxyTargetRing->pTargetRegs = (CSL_proxy_target0Regs *) (CSL_proxyRegs *) mmap_device_memory(0,
+ CSL_NAVSS0_PROXY_TARGET0_DATA_SIZE, PROT_READ|PROT_WRITE|PROT_NOCACHE, 0, CSL_NAVSS0_PROXY_TARGET0_DATA_BASE);
+
+#ifdef QNX_UDMA_DEBUG_CSL_REGS
+ printf( "%s: pTargetRegs phys/0x%lx virt/0x%p size/%ld\n",__FUNCTION__,
+ CSL_NAVSS0_PROXY_TARGET0_DATA_BASE, pProxyTargetRing->pTargetRegs, CSL_NAVSS0_PROXY_TARGET0_DATA_SIZE);
+#endif
+
+#else
pProxyTargetRing->pTargetRegs = (CSL_proxy_target0Regs *) CSL_NAVSS0_PROXY_TARGET0_DATA_BASE;
+#endif
pProxyTargetRing->numChns = CSL_NAVSS_MAIN_PROXY_TARGET_RINGACC0_NUM_CHANNELS;
pProxyTargetRing->chnSizeBytes = CSL_NAVSS_MAIN_PROXY_TARGET_RINGACC0_NUM_CHANNEL_SIZE_BYTES;
+#ifdef QNX_OS
+ pProxyCfg->pGlbRegs = (CSL_proxyRegs *) mmap_device_memory(0,
+ CSL_NAVSS0_PROXY0_CFG_BUF_CFG_SIZE, PROT_READ|PROT_WRITE|PROT_NOCACHE, 0, CSL_NAVSS0_PROXY0_CFG_BUF_CFG_BASE);
+ pProxyCfg->pCfgRegs = (CSL_proxy_cfgRegs *) mmap_device_memory(0,
+ CSL_NAVSS0_PROXY0_BUF_CFG_SIZE, PROT_READ|PROT_WRITE|PROT_NOCACHE, 0, CSL_NAVSS0_PROXY0_BUF_CFG_BASE);
+
+#ifdef QNX_UDMA_DEBUG_CSL_REGS
+ printf( "%s: pProxyCfg->pGlbRegs phys/0x%lx virt/0x%p size/%ld\n",__FUNCTION__,
+ CSL_NAVSS0_PROXY0_CFG_BUF_CFG_BASE, pProxyCfg->pGlbRegs, CSL_NAVSS0_PROXY0_CFG_BUF_CFG_SIZE);
+ printf( "%s: pProxyCfg->pCfgRegs phys/0x%lx virt/0x%p size/%ld\n",__FUNCTION__,
+ CSL_NAVSS0_PROXY0_BUF_CFG_BASE, pProxyCfg->pCfgRegs, CSL_NAVSS0_PROXY0_BUF_CFG_SIZE);
+#endif
+
+#else
pProxyCfg->pGlbRegs = (CSL_proxyRegs *) CSL_NAVSS0_PROXY0_CFG_BUF_CFG_BASE;
pProxyCfg->pCfgRegs = (CSL_proxy_cfgRegs *) CSL_NAVSS0_PROXY0_BUF_CFG_BASE;
+#endif
pProxyCfg->bufferSizeBytes = CSL_NAVSS_MAIN_PROXY_BUFFER_SIZE_BYTES;
pProxyCfg->numTargets = 1U;
pProxyCfg->pProxyTargetParams = pProxyTargetRing;
drvHandle->devIdPsil = TISCI_DEV_NAVSS0;
}
drvHandle->srcIdRingIrq = drvHandle->devIdRing;
- drvHandle->blkCopyRingIrqOffset = TISCI_RINGACC0_OES_IRQ_SRC_IDX_START;
+ drvHandle->blkCopyRingIrqOffset = TISCI_RINGACC0_OES_IRQ_SRC_IDX_START;
drvHandle->txRingIrqOffset = TISCI_RINGACC0_OES_IRQ_SRC_IDX_START;
drvHandle->rxRingIrqOffset = TISCI_RINGACC0_OES_IRQ_SRC_IDX_START;
drvHandle->srcIdTrIrq = drvHandle->devIdUdma;
- drvHandle->blkCopyTrIrqOffset = TISCI_UDMAP0_RX_OES_IRQ_SRC_IDX_START;
+ drvHandle->blkCopyTrIrqOffset = TISCI_UDMAP0_RX_OES_IRQ_SRC_IDX_START;
drvHandle->txTrIrqOffset = TISCI_UDMAP0_TX_OES_IRQ_SRC_IDX_START;
drvHandle->rxTrIrqOffset = TISCI_UDMAP0_RX_OES_IRQ_SRC_IDX_START;
drvHandle->txChOffset = 0U;
index 1a3cba42bdfa90c4f9c13d304f23d638c6be5814..cf3b734954d04007b6fcd27dd64e3b8c3ca0c126 100644 (file)
SRCDIR += soc/$(SOC)
INCDIR =
+# Added for QNX
+INCDIR = $(QNX_INSTALL_PATH)/resmgr/udma_qnx_rsmgr/resmgr/src $(QNX_INSTALL_PATH)/resmgr/udma_qnx_rsmgr/usr
+
# List all the external components/interfaces, whose interface header files
# need to be included for this component
INCLUDE_EXTERNAL_INTERFACES = pdk
index 5510fbecb54794dd1b2efe15027e53df976a5b97..8fd45e0dde5a185739301bc2d55e1b06982c19b2 100644 (file)
{
int32_t retVal = UDMA_SOK;
#if (UDMA_SOC_CFG_PROXY_PRESENT == 1)
+#ifndef QNX_OS
struct tisci_msg_rm_proxy_cfg_req req;
+#endif
#endif
if((drvHandle == NULL_PTR) || (initPrms == NULL_PTR))
}
#if (UDMA_SOC_CFG_PROXY_PRESENT == 1)
+#ifndef QNX_OS
if(UDMA_SOK == retVal)
{
/* Setup channelized firewall for default core proxy */
Udma_printf(drvHandle, "[Error] SciClient Set proxy config failed!!!\n");
}
}
+#endif
#endif
if(UDMA_SOK == retVal)
index f2fec3f83ace30197cfa5533f8dced8592857370..2cdc0834fda60b73b86c0bb1e16684475a3b9998 100644 (file)
/* ========================================================================== */
#include <ti/drv/udma/src/udma_priv.h>
-
+#ifdef QNX_OS
+#include <udma_resmgr.h>
+#endif
/* ========================================================================== */
/* Macros & Typedefs */
/* ========================================================================== */
/* Copy params */
rmUdmaTxReq.valid_params = TISCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID |
+#ifndef QNX_OS
TISCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_VALID |
+#endif
TISCI_MSG_VALUE_RM_UDMAP_CH_CHAN_TYPE_VALID |
TISCI_MSG_VALUE_RM_UDMAP_CH_FETCH_SIZE_VALID |
TISCI_MSG_VALUE_RM_UDMAP_CH_CQ_QNUM_VALID |
rmUdmaTxReq.tx_pause_on_err = txPrms->pauseOnError;
rmUdmaTxReq.tx_filt_einfo = txPrms->filterEinfo;
rmUdmaTxReq.tx_filt_pswords = txPrms->filterPsWords;
+#ifndef QNX_OS
rmUdmaTxReq.tx_atype = txPrms->addrType;
+#endif
rmUdmaTxReq.tx_chan_type = txPrms->chanType;
rmUdmaTxReq.tx_fetch_size = txPrms->fetchWordSize;
rmUdmaTxReq.tx_priority = txPrms->busPriority;
rmUdmaTxReq.tx_burst_size = txPrms->burstSize;
rmUdmaTxReq.tx_sched_priority = txPrms->dmaPriority;
rmUdmaTxReq.tx_credit_count = txPrms->txCredit;
+#ifdef QNX_OS
+ if(UDMA_DEFAULT_CH_ATYPE_INVALID != txPrms->addrType)
+ {
+ rmUdmaTxReq.valid_params |= TISCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_VALID;
+ rmUdmaTxReq.tx_atype = txPrms->addrType;
+ Udma_printf(drvHandle, "%s: rmUdmaTxReq.tx_atype=txPrms->addrType=0x%x\n",__FUNCTION__, rmUdmaTxReq.tx_atype);
+ }
+#endif
#if (UDMA_SOC_CFG_LCDMA_PRESENT == 1)
if(UDMA_INST_TYPE_LCDMA_BCDMA == drvHandle->instType)
{
/* Copy params */
rmUdmaRxReq.valid_params = TISCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID |
+#ifndef QNX_OS
TISCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_VALID |
+#endif
TISCI_MSG_VALUE_RM_UDMAP_CH_CHAN_TYPE_VALID |
TISCI_MSG_VALUE_RM_UDMAP_CH_FETCH_SIZE_VALID |
TISCI_MSG_VALUE_RM_UDMAP_CH_CQ_QNUM_VALID |
rmUdmaRxReq.nav_id = drvHandle->devIdUdma;
rmUdmaRxReq.index = (uint16_t)chHandle->rxChNum;
rmUdmaRxReq.rx_pause_on_err = rxPrms->pauseOnError;
+#ifndef QNX_OS
rmUdmaRxReq.rx_atype = rxPrms->addrType;
+#endif
rmUdmaRxReq.rx_chan_type = rxPrms->chanType;
rmUdmaRxReq.rx_fetch_size = rxPrms->fetchWordSize;
rmUdmaRxReq.rx_priority = rxPrms->busPriority;
rmUdmaRxReq.rx_ignore_short = rxPrms->ignoreShortPkts;
rmUdmaRxReq.rx_ignore_long = rxPrms->ignoreLongPkts;
rmUdmaRxReq.rx_burst_size = rxPrms->burstSize;
+#ifdef QNX_OS
+ if(UDMA_DEFAULT_CH_ATYPE_INVALID != rxPrms->addrType)
+ {
+ rmUdmaRxReq.valid_params |= TISCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_VALID;
+ rmUdmaRxReq.rx_atype = rxPrms->addrType;
+ Udma_printf(drvHandle, "%s: rmUdmaTxReq.tx_atype=txPrms->addrType=0x%x\n",__FUNCTION__, rmUdmaRxReq.rx_atype);
+ }
+#endif
if(NULL_PTR != chHandle->tdCqRing)
{
Udma_assert(drvHandle,
txPrms->pauseOnError = TISCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERROR_DISABLED;
txPrms->filterEinfo = TISCI_MSG_VALUE_RM_UDMAP_TX_CH_FILT_EINFO_DISABLED;
txPrms->filterPsWords = TISCI_MSG_VALUE_RM_UDMAP_TX_CH_FILT_PSWORDS_DISABLED;
+#ifdef QNX_OS
+ txPrms->addrType = UDMA_DEFAULT_CH_ATYPE_INVALID;
+#else
txPrms->addrType = TISCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_PHYS;
+#endif
txPrms->chanType = TISCI_MSG_VALUE_RM_UDMAP_CH_TYPE_PACKET;
if((chType & UDMA_CH_FLAG_BLK_COPY) == UDMA_CH_FLAG_BLK_COPY)
{
if(NULL_PTR != rxPrms)
{
rxPrms->pauseOnError = TISCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERROR_DISABLED;
+#ifdef QNX_OS
+ rxPrms->addrType = UDMA_DEFAULT_CH_ATYPE_INVALID;
+#else
rxPrms->addrType = TISCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_PHYS;
+#endif
rxPrms->chanType = TISCI_MSG_VALUE_RM_UDMAP_CH_TYPE_PACKET;
if((chType & UDMA_CH_FLAG_BLK_COPY) == UDMA_CH_FLAG_BLK_COPY)
{
{
if((chHandle->chType & UDMA_CH_FLAG_HC) == UDMA_CH_FLAG_HC)
{
+#ifdef QNX_OS
+ chHandle->txChNum =
+ Udma_resmgr_rmAllocBlkCopyHcCh(chHandle->chPrms.chNum, drvHandle);
+#else
chHandle->txChNum =
Udma_rmAllocBlkCopyHcCh(chHandle->chPrms.chNum, drvHandle);
+#endif
}
else if((chHandle->chType & UDMA_CH_FLAG_UHC) == UDMA_CH_FLAG_UHC)
{
+#ifdef QNX_OS
+ chHandle->txChNum =
+ Udma_resmgr_rmAllocBlkCopyUhcCh(chHandle->chPrms.chNum, drvHandle);
+#else
chHandle->txChNum =
Udma_rmAllocBlkCopyUhcCh(chHandle->chPrms.chNum, drvHandle);
+#endif
}
else
{
+#ifdef QNX_OS
+ chHandle->txChNum =
+ Udma_resmgr_rmAllocBlkCopyCh(chHandle->chPrms.chNum, drvHandle);
+#else
chHandle->txChNum =
Udma_rmAllocBlkCopyCh(chHandle->chPrms.chNum, drvHandle);
+#endif
}
if(UDMA_DMA_CH_INVALID == chHandle->txChNum)
{
utcInfo = chHandle->utcInfo;
Udma_assert(drvHandle, utcInfo != NULL_PTR);
/* Allocate external channel */
+#ifdef QNX_OS
+ chHandle->extChNum = Udma_resmgr_rmAllocExtCh(
+ chHandle->chPrms.chNum,
+ drvHandle,
+ utcInfo);
+#else
chHandle->extChNum = Udma_rmAllocExtCh(
chHandle->chPrms.chNum,
drvHandle,
utcInfo);
+#endif
if(UDMA_DMA_CH_INVALID == chHandle->extChNum)
{
retVal = UDMA_EALLOC;
{
if((chHandle->chType & UDMA_CH_FLAG_HC) == UDMA_CH_FLAG_HC)
{
+#ifdef QNX_OS
+ chHandle->txChNum =
+ Udma_resmgr_rmAllocTxHcCh(chHandle->chPrms.chNum, drvHandle);
+#else
chHandle->txChNum =
Udma_rmAllocTxHcCh(chHandle->chPrms.chNum, drvHandle);
+#endif
}
#if (UDMA_NUM_MAPPED_TX_GROUP > 0)
else if((chHandle->chType & UDMA_CH_FLAG_MAPPED) == UDMA_CH_FLAG_MAPPED)
#endif
else if((chHandle->chType & UDMA_CH_FLAG_UHC) == UDMA_CH_FLAG_UHC)
{
+#ifdef QNX_OS
+ chHandle->txChNum =
+ Udma_resmgr_rmAllocTxUhcCh(chHandle->chPrms.chNum, drvHandle);
+#else
chHandle->txChNum =
Udma_rmAllocTxUhcCh(chHandle->chPrms.chNum, drvHandle);
+#endif
}
else
{
+#ifdef QNX_OS
+ chHandle->txChNum =
+ Udma_resmgr_rmAllocTxCh(chHandle->chPrms.chNum, drvHandle);
+#else
chHandle->txChNum =
Udma_rmAllocTxCh(chHandle->chPrms.chNum, drvHandle);
+#endif
}
if(UDMA_DMA_CH_INVALID == chHandle->txChNum)
{
{
if((chHandle->chType & UDMA_CH_FLAG_HC) == UDMA_CH_FLAG_HC)
{
+#ifdef QNX_OS
+ chHandle->rxChNum =
+ Udma_resmgr_rmAllocRxHcCh(chHandle->chPrms.chNum, drvHandle);
+#else
chHandle->rxChNum =
Udma_rmAllocRxHcCh(chHandle->chPrms.chNum, drvHandle);
+#endif
}
#if (UDMA_NUM_MAPPED_RX_GROUP > 0)
else if((chHandle->chType & UDMA_CH_FLAG_MAPPED) == UDMA_CH_FLAG_MAPPED)
#endif
else if((chHandle->chType & UDMA_CH_FLAG_UHC) == UDMA_CH_FLAG_UHC)
{
+#ifdef QNX_OS
+ chHandle->rxChNum =
+ Udma_resmgr_rmAllocRxUhcCh(chHandle->chPrms.chNum, drvHandle);
+#else
chHandle->rxChNum =
Udma_rmAllocRxUhcCh(chHandle->chPrms.chNum, drvHandle);
+#endif
}
else
{
+#ifdef QNX_OS
+ chHandle->rxChNum =
+ Udma_resmgr_rmAllocRxCh(chHandle->chPrms.chNum, drvHandle);
+#else
chHandle->rxChNum =
Udma_rmAllocRxCh(chHandle->chPrms.chNum, drvHandle);
+#endif
}
if(UDMA_DMA_CH_INVALID == chHandle->rxChNum)
{
/* TX channel free */
if((chHandle->chType & UDMA_CH_FLAG_HC) == UDMA_CH_FLAG_HC)
{
+#ifdef QNX_OS
+ Udma_resmgr_rmFreeBlkCopyHcCh(chHandle->txChNum, drvHandle);
+#else
Udma_rmFreeBlkCopyHcCh(chHandle->txChNum, drvHandle);
+#endif
}
else if((chHandle->chType & UDMA_CH_FLAG_UHC) == UDMA_CH_FLAG_UHC)
{
+#ifdef QNX_OS
+ Udma_resmgr_rmFreeBlkCopyUhcCh(chHandle->txChNum, drvHandle);
+#else
Udma_rmFreeBlkCopyUhcCh(chHandle->txChNum, drvHandle);
+#endif
}
else
{
+#ifdef QNX_OS
+ Udma_resmgr_rmFreeBlkCopyCh(chHandle->txChNum, drvHandle);
+#else
Udma_rmFreeBlkCopyCh(chHandle->txChNum, drvHandle);
+#endif
}
chHandle->txChNum = UDMA_DMA_CH_INVALID;
chHandle->rxChNum = UDMA_DMA_CH_INVALID;
/* TX channel free */
if((chHandle->chType & UDMA_CH_FLAG_HC) == UDMA_CH_FLAG_HC)
{
+#ifdef QNX_OS
+ Udma_resmgr_rmFreeTxHcCh(chHandle->txChNum, drvHandle);
+#else
Udma_rmFreeTxHcCh(chHandle->txChNum, drvHandle);
+#endif
}
#if (UDMA_NUM_MAPPED_TX_GROUP > 0)
else if((chHandle->chType & UDMA_CH_FLAG_MAPPED) == UDMA_CH_FLAG_MAPPED)
#endif
else if((chHandle->chType & UDMA_CH_FLAG_UHC) == UDMA_CH_FLAG_UHC)
{
+#ifdef QNX_OS
+ Udma_resmgr_rmFreeTxUhcCh(chHandle->txChNum, drvHandle);
+#else
Udma_rmFreeTxUhcCh(chHandle->txChNum, drvHandle);
+#endif
}
else
{
+#ifdef QNX_OS
+ Udma_resmgr_rmFreeTxCh(chHandle->txChNum, drvHandle);
+#else
Udma_rmFreeTxCh(chHandle->txChNum, drvHandle);
+#endif
}
chHandle->txChNum = UDMA_DMA_CH_INVALID;
}
/* RX channel free */
if((chHandle->chType & UDMA_CH_FLAG_HC) == UDMA_CH_FLAG_HC)
{
+#ifdef QNX_OS
+ Udma_resmgr_rmFreeRxHcCh(chHandle->rxChNum, drvHandle);
+#else
Udma_rmFreeRxHcCh(chHandle->rxChNum, drvHandle);
+#endif
}
#if (UDMA_NUM_MAPPED_RX_GROUP > 0)
else if((chHandle->chType & UDMA_CH_FLAG_MAPPED) == UDMA_CH_FLAG_MAPPED)
#endif
else if((chHandle->chType & UDMA_CH_FLAG_UHC) == UDMA_CH_FLAG_UHC)
{
+#ifdef QNX_OS
+ Udma_resmgr_rmFreeRxUhcCh(chHandle->rxChNum, drvHandle);
+#else
Udma_rmFreeRxUhcCh(chHandle->rxChNum, drvHandle);
+#endif
}
else
{
+#ifdef QNX_OS
+ Udma_resmgr_rmFreeRxCh(chHandle->rxChNum, drvHandle);
+#else
Udma_rmFreeRxCh(chHandle->rxChNum, drvHandle);
+#endif
}
chHandle->rxChNum = UDMA_DMA_CH_INVALID;
}
if(UDMA_DMA_CH_INVALID != chHandle->extChNum)
{
/* External channel free */
+#ifdef QNX_OS
+ Udma_resmgr_rmFreeExtCh(chHandle->extChNum, drvHandle, chHandle->utcInfo);
+#else
Udma_rmFreeExtCh(chHandle->extChNum, drvHandle, chHandle->utcInfo);
+#endif
chHandle->extChNum = UDMA_DMA_CH_INVALID;
}
#endif
index 2c39e202659e82ea9b4886ef1d06c80a784ddf35..918253a1fbbcb3754737b8761f52a7db473793a0 100755 (executable)
/* ========================================================================== */
#include <ti/drv/udma/src/udma_priv.h>
+#ifdef QNX_OS
+#include <udma_resmgr.h>
+#endif
/* ========================================================================== */
/* Macros & Typedefs */
/* Allocate event irrespective of all modes except global master event */
if(UDMA_EVENT_TYPE_MASTER != eventPrms->eventType)
{
+#ifdef QNX_OS
+ eventHandle->globalEvent = Udma_resmgr_rmAllocEvent(drvHandle);
+#else
eventHandle->globalEvent = Udma_rmAllocEvent(drvHandle);
+#endif
if(UDMA_EVENT_INVALID == eventHandle->globalEvent)
{
retVal = UDMA_EALLOC;
((UDMA_EVENT_MODE_SHARED == eventPrms->eventMode) &&
(NULL_PTR == eventPrms->masterEventHandle)))
{
+#ifdef QNX_OS
+ eventHandle->vintrNum = Udma_resmgr_rmAllocVintr(drvHandle);
+#else
eventHandle->vintrNum = Udma_rmAllocVintr(drvHandle);
+#endif
if(UDMA_EVENT_INVALID == eventHandle->vintrNum)
{
retVal = UDMA_EALLOC;
/* Allocate IA bit for all event modes except global master event */
if(UDMA_EVENT_TYPE_MASTER != eventPrms->eventType)
{
+#ifdef QNX_OS
+ eventHandle->vintrBitNum = Udma_resmgr_rmAllocVintrBit(drvHandle, eventHandle);
+#else
eventHandle->vintrBitNum = Udma_rmAllocVintrBit(eventHandle);
+#endif
if(UDMA_EVENT_INVALID == eventHandle->vintrBitNum)
{
retVal = UDMA_EALLOC;
}
if(UDMA_INTR_INVALID != preferredIrIntrNum)
{
+#ifdef QNX_OS
+ eventHandle->irIntrNum =
+ Udma_resmgr_rmAllocIrIntr(preferredIrIntrNum, drvHandle);
+#else
eventHandle->irIntrNum =
Udma_rmAllocIrIntr(preferredIrIntrNum, drvHandle);
+#endif
if(UDMA_INTR_INVALID != eventHandle->irIntrNum)
{
eventHandle->coreIntrNum = Udma_rmTranslateIrOutput(drvHandle, eventHandle->irIntrNum);
-
}
}
if(UDMA_INTR_INVALID == eventHandle->coreIntrNum)
}
if(UDMA_INTR_INVALID != eventHandle->irIntrNum)
{
+#ifdef QNX_OS
+ Udma_resmgr_rmFreeIrIntr(eventHandle->irIntrNum, drvHandle);
+#else
Udma_rmFreeIrIntr(eventHandle->irIntrNum, drvHandle);
+#endif
eventHandle->irIntrNum = UDMA_INTR_INVALID;
eventHandle->coreIntrNum = UDMA_INTR_INVALID;
}
{
/* Reset steering */
Udma_eventResetSteering(drvHandle, eventHandle);
+#ifdef QNX_OS
+ Udma_resmgr_rmFreeEvent(eventHandle->globalEvent, drvHandle);
+#else
Udma_rmFreeEvent(eventHandle->globalEvent, drvHandle);
+#endif
eventHandle->globalEvent = UDMA_EVENT_INVALID;
}
if(UDMA_EVENT_INVALID != eventHandle->vintrBitNum)
{
+#ifdef QNX_OS
+ Udma_resmgr_rmFreeVintrBit(eventHandle->vintrBitNum, drvHandle, eventHandle);
+#else
Udma_rmFreeVintrBit(eventHandle->vintrBitNum, drvHandle, eventHandle);
+#endif
eventHandle->vintrBitNum = UDMA_EVENT_INVALID;
}
if(UDMA_EVENT_INVALID != eventHandle->vintrNum)
{
+#ifdef QNX_OS
+ Udma_resmgr_rmFreeVintr(eventHandle->vintrNum, drvHandle);
+#else
Udma_rmFreeVintr(eventHandle->vintrNum, drvHandle);
+#endif
eventHandle->vintrNum = UDMA_EVENT_INVALID;
}
index a50b5e014ff20dbeda3cc36f173ae54fc5032c0b..19cca3cbf05be8bc3db1904d4d011f53937b4e2d 100755 (executable)
intrPrms.corepacConfig.corepacEventNum = (int32_t)0;
intrPrms.corepacConfig.intVecNum = (int32_t)coreIntrNum;
#endif
-
+#ifdef QNX_OS
+ intrPrms.corepacConfig.intAutoEnable = 1;
+#endif
/* Register interrupts */
osalRetVal = Osal_RegisterInterrupt(&intrPrms, &hwiHandle);
if(OSAL_INT_SUCCESS != osalRetVal)
index ae1f6d39f4a7252abf4a7ab8fd991bebbf3603f5..b0752fc1bbde8acc80eaba795671ddd027d32366 100644 (file)
/* This is needed for memset/memcpy */
#include <string.h>
#include <ti/drv/udma/udma.h>
+#ifdef QNX_OS
+#include <stdio.h>
+#include <sys/mman.h>
+#include <unistd.h>
+#include <hw/inout.h>
+#endif
#ifdef __cplusplus
extern "C" {
@@ -353,12 +359,24 @@ int32_t Udma_rmSetSharedResRmInitPrms(const Udma_RmSharedResPrms *rmSharedResPrm
uint32_t *num);
/* Utils APIs */
+#ifdef QNX_OS
+uint64_t Udma_virtToPhyFxn(const void *virtAddr,
+ uint32_t virtAddrSize,
+ Udma_DrvHandle drvHandle,
+ Udma_ChHandle chHandle);
+void *Udma_phyToVirtFxn(uint64_t phyAddr,
+ uint32_t phyAddrSize,
+ Udma_DrvHandle drvHandle,
+ Udma_ChHandle chHandle);
+#else
uint64_t Udma_virtToPhyFxn(const void *virtAddr,
Udma_DrvHandle drvHandle,
Udma_ChHandle chHandle);
void *Udma_phyToVirtFxn(uint64_t phyAddr,
Udma_DrvHandle drvHandle,
Udma_ChHandle chHandle);
+#endif
+
/**
* \brief Prints to Shared memory and CCS console
*
index 45482760e7398c18d5c01bcbcaf130972553de25..8d9e2c9598c9f701bcd84b52edade09cb34e9493 100755 (executable)
/* ========================================================================== */
#include <ti/drv/udma/src/udma_priv.h>
+#ifdef QNX_OS
+#include <udma_resmgr.h>
+#endif
/* ========================================================================== */
/* Macros & Typedefs */
if(UDMA_SOK == retVal)
{
+#ifdef QNX_OS
+ if(proxyNum >= drvHandle->maxProxy)
+ {
+ Udma_printf(drvHandle, "[Error] Out of range proxy index!!!\n");
+ retVal = UDMA_EINVALID_PARAMS;
+ }
+ else
+ {
+ proxyHandle->proxyNum = Udma_resmgr_rmAllocProxy(proxyNum, drvHandle);
+ if(UDMA_PROXY_INVALID == proxyHandle->proxyNum)
+ {
+ retVal = UDMA_EALLOC;
+ }
+ }
+#else
if(UDMA_PROXY_ANY == proxyNum)
{
/* Alloc free proxy */
proxyHandle->proxyNum = proxyNum;
}
}
+#endif
}
if(UDMA_SOK == retVal)
if(UDMA_SOK != retVal)
{
Udma_printf(drvHandle, "[Error] SciClient Set proxy config failed!!!\n");
+#ifdef QNX_OS
+ Udma_resmgr_rmFreeProxy(proxyHandle->proxyNum, drvHandle);
+#else
if (UDMA_PROXY_ANY == proxyNum)
{
/* Free-up resources */
Udma_rmFreeProxy(proxyHandle->proxyNum, drvHandle);
}
+#endif
}
}
{
/* Free-up resources */
Udma_assert(drvHandle, proxyHandle->proxyNum != UDMA_PROXY_INVALID);
+#ifdef QNX_OS
+ Udma_resmgr_rmFreeProxy(proxyHandle->proxyNum, drvHandle);
+#else
Udma_rmFreeProxy(proxyHandle->proxyNum, drvHandle);
+#endif
proxyHandle->drvHandle = (Udma_DrvHandle) NULL_PTR;
proxyHandle->proxyNum = UDMA_PROXY_INVALID;
proxyHandle->proxyAddr = 0U;
diff --git a/packages/ti/drv/udma/src/udma_ring_common.c b/packages/ti/drv/udma/src/udma_ring_common.c
index 8d029b50ce4b2b4d440033d9215baad37781f69f..4a92e8111f8789edb6b671740865b21aaa8f3326 100755 (executable)
/* ========================================================================== */
#include <ti/drv/udma/src/udma_priv.h>
+#ifdef QNX_OS
+#include <udma_resmgr.h>
+#endif
/* ========================================================================== */
/* Macros & Typedefs */
/* Alloc free ring */
if(UDMA_MAPPED_GROUP_INVALID == ringPrms->mappedRingGrp)
{
+#ifdef QNX_OS
+ ringHandle->ringNum = Udma_resmgr_rmAllocFreeRing(drvHandle);
+#else
ringHandle->ringNum = Udma_rmAllocFreeRing(drvHandle);
+#endif
}
#if((UDMA_NUM_MAPPED_TX_GROUP + UDMA_NUM_MAPPED_RX_GROUP) > 0)
else
TISCI_MSG_VALUE_RM_RING_ASEL_VALID;
rmRingReq.nav_id = drvHandle->devIdRing;
rmRingReq.index = ringHandle->ringNum;
+#ifdef QNX_OS
+ physBase = Udma_virtToPhyFxn(ringPrms->ringMem, ringPrms->ringMemSize, drvHandle, (Udma_ChHandle) NULL_PTR);
+#else
physBase = Udma_virtToPhyFxn(ringPrms->ringMem, drvHandle, (Udma_ChHandle) NULL_PTR);
+#endif
rmRingReq.addr_lo = (uint32_t)physBase;
rmRingReq.addr_hi = (uint32_t)(physBase >> 32UL);
rmRingReq.count = ringPrms->elemCnt;
{
rmRingReq.valid_params |= TISCI_MSG_VALUE_RM_RING_VIRTID_VALID;
rmRingReq.virtid = ringPrms->virtId;
+#ifdef QNX_OS
+ Udma_printf(drvHandle, "%s: rmRingReq.virtid=ringPrms->virtId;=0x%x\n",__FUNCTION__, rmRingReq.virtid);
+#endif
}
retVal = Sciclient_rmRingCfg(
{
if(UDMA_MAPPED_GROUP_INVALID == ringPrms->mappedRingGrp)
{
+#ifdef QNX_OS
+ Udma_resmgr_rmFreeFreeRing(ringHandle->ringNum, drvHandle);
+#else
Udma_rmFreeFreeRing(ringHandle->ringNum, drvHandle);
+#endif
}
#if((UDMA_NUM_MAPPED_TX_GROUP + UDMA_NUM_MAPPED_RX_GROUP) > 0)
else
Udma_assert(drvHandle, ringHandle->ringNum != UDMA_RING_INVALID);
if(UDMA_MAPPED_GROUP_INVALID == ringHandle->mappedRingGrp)
{
+#ifdef QNX_OS
+ Udma_resmgr_rmFreeFreeRing(ringHandle->ringNum, drvHandle);
+#else
Udma_rmFreeFreeRing(ringHandle->ringNum, drvHandle);
+#endif
}
#if((UDMA_NUM_MAPPED_TX_GROUP + UDMA_NUM_MAPPED_RX_GROUP) > 0)
else
if(UDMA_RING_MON_ANY == ringMonNum)
{
/* Alloc free ring MONITOR */
+#ifdef QNX_OS
+ monHandle->ringMonNum = Udma_resmgr_rmAllocRingMon(drvHandle);
+#else
monHandle->ringMonNum = Udma_rmAllocRingMon(drvHandle);
+#endif
if(UDMA_RING_MON_INVALID == monHandle->ringMonNum)
{
retVal = UDMA_EALLOC;
/* Error. Free-up resource if allocated */
if(((uint32_t) TRUE) == allocDone)
{
+#ifdef QNX_OS
+ Udma_resmgr_rmFreeRingMon(monHandle->ringMonNum, drvHandle);
+#else
Udma_rmFreeRingMon(monHandle->ringMonNum, drvHandle);
+#endif
}
}
#else
{
/* Free-up event resources */
Udma_assert(drvHandle, monHandle->ringMonNum != UDMA_RING_MON_INVALID);
+#ifdef QNX_OS
+ Udma_resmgr_rmFreeRingMon(monHandle->ringMonNum, drvHandle);
+#else
Udma_rmFreeRingMon(monHandle->ringMonNum, drvHandle);
+#endif
monHandle->drvHandle = (Udma_DrvHandle) NULL_PTR;
monHandle->ringMonNum = UDMA_RING_MON_INVALID;
monHandle->pMonRegs = (volatile CSL_ringacc_monitorRegs_mon *) NULL_PTR;
diff --git a/packages/ti/drv/udma/src/udma_ring_lcdma.c b/packages/ti/drv/udma/src/udma_ring_lcdma.c
index 3d368398b4f5ec1863e28c542534b151225a0edd..b436befbe6ac35118968eb5fb0c2fa1020bec901 100644 (file)
if(NULL_PTR != ringPrms)
{
lcdmaRingCfg->virtBase = (void *) ringPrms->ringMem;
+#ifdef QNX_OS
+ lcdmaRingCfg->physBase =
+ Udma_virtToPhyFxn(ringPrms->ringMem, ringPrms->ringMemSize, drvHandle, (Udma_ChHandle) NULL_PTR);
+#else
lcdmaRingCfg->physBase =
Udma_virtToPhyFxn(ringPrms->ringMem, drvHandle, (Udma_ChHandle) NULL_PTR);
+#endif
lcdmaRingCfg->mode = ringPrms->mode;
lcdmaRingCfg->elCnt = ringPrms->elemCnt;
/* CSL expects ring size in bytes */
addrLo = CSL_REG32_FEXT(&ringHandle->pLcdmaCfgRegs->BA_LO, LCDMA_RINGACC_RING_CFG_RING_BA_LO_ADDR_LO);
lcdmaRingCfg->physBase = (uint64_t)((((uint64_t) addrHi) << 32UL) |
((uint64_t) addrLo));
+#ifdef QNX_OS
+ lcdmaRingCfg->virtBase = Udma_phyToVirtFxn(lcdmaRingCfg->physBase, /*TODO*/4096, drvHandle, (Udma_ChHandle) NULL_PTR);
+#else
lcdmaRingCfg->virtBase = Udma_phyToVirtFxn(lcdmaRingCfg->physBase, drvHandle, (Udma_ChHandle) NULL_PTR);
+#endif
lcdmaRingCfg->mode = CSL_REG32_FEXT(&ringHandle->pLcdmaCfgRegs->SIZE, LCDMA_RINGACC_RING_CFG_RING_SIZE_QMODE);
lcdmaRingCfg->elCnt = CSL_REG32_FEXT(&ringHandle->pLcdmaCfgRegs->SIZE, LCDMA_RINGACC_RING_CFG_RING_SIZE_ELCNT);
/* CSL expects ring size in bytes; ring_elsize for AM64x is hardcoded as 1=8bytes*/
diff --git a/packages/ti/drv/udma/src/udma_ring_normal.c b/packages/ti/drv/udma/src/udma_ring_normal.c
index a6ad6fdf770f0b95bf4752c32afcfa1ee4fa3548..5339b01c04faabd901af4c56b881a45b1d01c1c6 100644 (file)
ringCfg = &ringHandle->cfg;
if(NULL_PTR != ringPrms)
{
+#ifdef QNX_OS
+ ringCfg->physBase =
+ Udma_virtToPhyFxn(ringPrms->ringMem, ringPrms->ringMemSize, drvHandle, (Udma_ChHandle) NULL_PTR);
+#else
ringCfg->physBase =
Udma_virtToPhyFxn(ringPrms->ringMem, drvHandle, (Udma_ChHandle) NULL_PTR);
+#endif
ringCfg->virtBase = (void *) ringPrms->ringMem;
ringCfg->mode = ringPrms->mode;
ringCfg->elCnt = ringPrms->elemCnt;
addrLo = CSL_REG32_FEXT(&ringHandle->pCfgRegs->BA_LO, RINGACC_CFG_RING_BA_LO_ADDR_LO);
ringCfg->physBase = (uint64_t)((((uint64_t) addrHi) << 32UL) |
((uint64_t) addrLo));
+#ifdef QNX_OS
+ ringCfg->virtBase = Udma_phyToVirtFxn(ringCfg->physBase, /*TODO*/4096, drvHandle, (Udma_ChHandle) NULL_PTR);
+#else
ringCfg->virtBase = Udma_phyToVirtFxn(ringCfg->physBase, drvHandle, (Udma_ChHandle) NULL_PTR);
+#endif
ringCfg->mode = CSL_REG32_FEXT(&ringHandle->pCfgRegs->SIZE, RINGACC_CFG_RING_SIZE_QMODE);
ringCfg->elCnt = CSL_REG32_FEXT(&ringHandle->pCfgRegs->SIZE, RINGACC_CFG_RING_SIZE_ELCNT);
elemSize = CSL_REG32_FEXT(&ringHandle->pCfgRegs->SIZE, RINGACC_CFG_RING_SIZE_ELSIZE);
index f1f78023122b3bb048275cdf2842054cce766063..5d8e5de938d0ceea935b29dcb888c8cdaabeec18 100755 (executable)
return (trSize);
}
+#ifndef QNX_OS
uint64_t Udma_virtToPhyFxn(const void *virtAddr,
Udma_DrvHandle drvHandle,
Udma_ChHandle chHandle)
return (virtAddr);
}
+#else
+uint64_t Udma_virtToPhyFxn(const void *virtAddr,
+ uint32_t virtAddrSize,
+ Udma_DrvHandle drvHandle,
+ Udma_ChHandle chHandle)
+{
+ uint32_t chNum = UDMA_DMA_CH_INVALID;
+ void * appData = &virtAddrSize;
+ uint64_t phyAddr = 0;
+
+ if(NULL_PTR != chHandle)
+ {
+ chNum = chHandle->chPrms.chNum;
+ }
+
+ //Udma_printf(drvHandle, "Udma_phyToVirtFxn - 0x%x- %d!\n", virtAddr, virtAddrSize);
+ if((Udma_VirtToPhyFxn) NULL_PTR != drvHandle->initPrms.virtToPhyFxn)
+ {
+ phyAddr = drvHandle->initPrms.virtToPhyFxn(virtAddr, chNum, appData);
+
+ if (phyAddr == 0)
+ {
+ Udma_printf(drvHandle, "Error: virtToPhyFxn FAILED!\n");
+ Udma_assert(drvHandle, FALSE);
+ }
+ }
+ else
+ {
+ Udma_printf(drvHandle, "Error: virtToPhyFxn not set!\n");
+ Udma_assert(drvHandle, FALSE);
+ }
+
+ return (phyAddr);
+}
+
+void *Udma_phyToVirtFxn(uint64_t phyAddr,
+ uint32_t phyAddrSize,
+ Udma_DrvHandle drvHandle,
+ Udma_ChHandle chHandle)
+{
+ uint32_t chNum = UDMA_DMA_CH_INVALID;
+ void * appData = &phyAddrSize;
+ void * virtAddr = NULL;
+
+ if(NULL_PTR != chHandle)
+ {
+ chNum = chHandle->chPrms.chNum;
+ }
+
+ //Udma_printf(drvHandle, "Udma_phyToVirtFxn - 0x%lx- %d!\n", phyAddr, phyAddrSize);
+ if((Udma_PhyToVirtFxn) NULL_PTR != drvHandle->initPrms.phyToVirtFxn)
+ {
+ virtAddr = drvHandle->initPrms.phyToVirtFxn(phyAddr, chNum, appData);
+
+ if (virtAddr == 0)
+ {
+ Udma_printf(drvHandle, "Error: phyToVirtFxn FAILED!\n");
+ Udma_assert(drvHandle, FALSE);
+ }
+ }
+ else
+ {
+ Udma_printf(drvHandle, "Error: phyToVirtFxn not set!\n");
+ Udma_assert(drvHandle, FALSE);
+ }
+
+ return (virtAddr);
+}
+#endif
void Udma_printf(Udma_DrvHandle drvHandle, const char *format, ...)
{
index 377a3a8c2d2c7b21850f6d9fc30da27533ee99b2..7bfce77925f941f9aaa90944dd3f12ac6b876216 100644 (file)
drvudma_am65xx_example_CORELIST = mpu1_0 mcu1_0
drvudma_am64x_example_CORELIST = mcu1_0 mcu1_1 mcu2_0 mcu2_1 mpu1_0 #m4f for baremetal examples only
endif
+ifeq ($(BUILD_OS_TYPE), qnx)
+drvudma_j721e_CORELIST += qnx_mpu1_0
+drvudma_j7200_CORELIST += qnx_mpu1_0
+endif
############################
# udma package