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raw | patch | inline | side by side (parent: ab53056)
raw | patch | inline | side by side (parent: ab53056)
author | Prasad Konnur <prasadkonnur@ti.com> | |
Wed, 4 Nov 2020 15:14:59 +0000 (20:44 +0530) | ||
committer | Sivaraj R <sivaraj@ti.com> | |
Thu, 5 Nov 2020 06:55:59 +0000 (00:55 -0600) |
Signed-off-by: Prasad Konnur <prasadkonnur@ti.com>
index e5063265f1c071bd604525bc3208dfbc8e2e761b..69e13deb563d396a69e0e40832709d0082c5bd54 100644 (file)
Clock.timerId = 2;
}
+/* Sysbios supports workaround for Silicon issue https://jira.itg.ti.com/browse/K3_OPEN_SI-148
+ * Details of silicon issue : https://confluence.itg.ti.com/display/PROCIPDEV/%2310+The+same+interrupt+cannot+be+nested+back-2-back+within+another+interrupt
+ * Sysbios Requirement Details: https://jira.itg.ti.com/browse/SYSBIOS-1419
+ * Workaround requires use of a resevred dummyIRQ.
+ * Using DummyIRQ#383 as per cslr_intr_mss.h it is a reserved interrupt not connected to any
+ * peripheral interrupt sources
+ */
+Hwi.dummyIRQ = 352;
+
index 30d0c52c45f8536136fccf2780e0d5503de81283..bd6bb9b668f2d24819c94307125ea50d0fc9ba1a 100755 (executable)
Hwi.vimBaseAddress = 0x0ff80000;
}
+/* Sysbios supports workaround for Silicon issue https://jira.itg.ti.com/browse/K3_OPEN_SI-148
+ * Details of silicon issue : https://confluence.itg.ti.com/display/PROCIPDEV/%2310+The+same+interrupt+cannot+be+nested+back-2-back+within+another+interrupt
+ * Sysbios Requirement Details: https://jira.itg.ti.com/browse/SYSBIOS-1419
+ * Workaround requires use of a resevred dummyIRQ.
+ * Using DummyIRQ#383 as per cslr_intr_mss.h it is a reserved interrupt not connected to any
+ * peripheral interrupt sources
+ */
+if((coreId=="mcu1_0") || (coreId=="mcu1_1"))
+{
+ Hwi.dummyIRQ = 383;
+}
+if((coreId=="mcu2_0") || (coreId=="mcu2_1"))
+{
+ Hwi.dummyIRQ = 511;
+}
+
var Reset = xdc.useModule("xdc.runtime.Reset");
Reset.fxns[Reset.fxns.length++] = "&utilsCopyVecs2ATcm";
index 7ea5863609462721dee3cb653b0c0d4dde00773c..76fcaf0540e62e0575b63652b028b18304ae8b2f 100644 (file)
@@ -209,6 +209,22 @@ if((coreId=="mcu2_0") || (coreId=="mcu2_1") || (coreId=="mcu3_0") || (coreId=="m
Hwi.vimBaseAddress = 0x0ff80000;
}
+/* Sysbios supports workaround for Silicon issue https://jira.itg.ti.com/browse/K3_OPEN_SI-148
+ * Details of silicon issue : https://confluence.itg.ti.com/display/PROCIPDEV/%2310+The+same+interrupt+cannot+be+nested+back-2-back+within+another+interrupt
+ * Sysbios Requirement Details: https://jira.itg.ti.com/browse/SYSBIOS-1419
+ * Workaround requires use of a resevred dummyIRQ.
+ * Using DummyIRQ#383 as per cslr_intr_mss.h it is a reserved interrupt not connected to any
+ * peripheral interrupt sources
+ */
+if((coreId=="mcu1_0") || (coreId=="mcu1_1"))
+{
+ Hwi.dummyIRQ = 383;
+}
+if((coreId=="mcu2_0") || (coreId=="mcu2_1") || (coreId=="mcu3_0") || (coreId=="mcu3_1"))
+{
+ Hwi.dummyIRQ = 511;
+}
+
var Reset = xdc.useModule("xdc.runtime.Reset");
Reset.fxns[Reset.fxns.length++] = "&utilsCopyVecs2ATcm";
index 67b72358a05986b463a6d52520ffa3fc33b14a93..c9d0be959e145edbb318f0c45a6e69256570e6ae 100755 (executable)
Osal_RegisterInterrupt_initParams(&interruptRegParams);
interruptRegParams.corepacConfig.name=NULL;
-#ifndef __TI_ARM_V7R5__
+#ifdef __TI_ARM_V7R5__
interruptRegParams.corepacConfig.priority=0x8U;
#else
interruptRegParams.corepacConfig.priority=0x20U;
index 596b12fdadbd31b432de25b51a78b3656ab407c1..842feee85dd3283d5b8f2a34145972e54b82ade8 100755 (executable)
Osal_RegisterInterrupt_initParams(&interruptRegParams);
interruptRegParams.corepacConfig.name=NULL;
-#ifdef __TI_ARM_V7R4
+#ifdef __TI_ARM_V7R4__
interruptRegParams.corepacConfig.priority=0x8U;
#else
interruptRegParams.corepacConfig.priority=0x20U;