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| author | Jacob Stiffler <j-stiffler@ti.com> | |
| Fri, 1 Nov 2019 18:58:11 +0000 (14:58 -0400) | ||
| committer | Jacob Stiffler <j-stiffler@ti.com> | |
| Fri, 1 Nov 2019 18:58:11 +0000 (14:58 -0400) |
Development of bcp-lld has been relocated here from:
* Repo: https://git.ti.com/keystone-rtos/bcp-lld
* Branch: master
* Commit ID: 2a13d5e3b26180dd4f1010327f1daed9b3330752
Signed-off-by: Jacob Stiffler <j-stiffler@ti.com>
* Repo: https://git.ti.com/keystone-rtos/bcp-lld
* Branch: master
* Commit ID: 2a13d5e3b26180dd4f1010327f1daed9b3330752
Signed-off-by: Jacob Stiffler <j-stiffler@ti.com>
140 files changed:
diff --git a/packages/ti/drv/bcp/.gitignore b/packages/ti/drv/bcp/.gitignore
--- /dev/null
@@ -0,0 +1,23 @@
+*.swp
+*~
+*.bak
+.dlls
+.executables
+.interfaces
+.libraries
+.xdcenv.mak
+Settings.h
+Settings.xdc
+build/c66/
+docs/Doxyfile
+docs/doxygen/
+docs/fftcDocs.chm
+eclipseDocs/sample.xml
+bcpver.h
+lib/
+makefile
+package.mak
+package/
+packages/
+build/c66/
+
diff --git a/packages/ti/drv/bcp/Settings.xdc.xdt b/packages/ti/drv/bcp/Settings.xdc.xdt
--- /dev/null
@@ -0,0 +1,37 @@
+\r
+%%{\r
+/*!\r
+ * This template implements the Settings.xdc\r
+ */ \r
+ /* Versioning */\r
+ var ver = this;\r
+ for each(i=0;i<ver.length;i++)\r
+ {\r
+ if(String(ver[i]).length < 2)\r
+ {\r
+ ver[i]="0"+ver[i];\r
+ }\r
+ }\r
+ \r
+ var packageVersion = "\""+ver[0]+"."+ver[1]+"."+ver[2]+"."+ver[3]+"\"";\r
+\r
+%%}\r
+\r
+module Settings\r
+{\r
+ config string bcpVersionString = `packageVersion`;\r
+\r
+ /*! This variable is to control the device type selection.\r
+ * By default this variable is set to NULL.\r
+ * \r
+ * To use Qmss for the selected device, add the following lines to config\r
+ * file and set the deviceType correctly:\r
+ * \r
+ * var Qmss = xdc.useModule ('ti.drv.qmss.Settings');\r
+ * Qmss.deviceType = "tci6634";\r
+ * \r
+ * List of supported devices can be found in package.xs file.\r
+ */\r
+ metaonly config string deviceType = "";\r
+}\r
+\r
diff --git a/packages/ti/drv/bcp/bcp.h b/packages/ti/drv/bcp/bcp.h
--- /dev/null
@@ -0,0 +1,501 @@
+/** \r
+ * @file bcp.h\r
+ *\r
+ * @brief \r
+ * Header file with data structure and API declarations for BCP High\r
+ * level driver.\r
+ * \r
+ * \par\r
+ * ============================================================================\r
+ * @n (C) Copyright 2010, Texas Instruments, Inc.\r
+ * \r
+ * Redistribution and use in source and binary forms, with or without \r
+ * modification, are permitted provided that the following conditions \r
+ * are met:\r
+ *\r
+ * Redistributions of source code must retain the above copyright \r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the \r
+ * documentation and/or other materials provided with the \r
+ * distribution.\r
+ *\r
+ * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \r
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT \r
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT \r
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \r
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT \r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT \r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE \r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+*/\r
+#ifndef _BCP_H_\r
+#define _BCP_H_\r
+\r
+/* BCP LLD and MMR includes */\r
+#include <ti/drv/bcp/bcp_lld.h>\r
+#include <ti/drv/bcp/bcp_mmr.h>\r
+\r
+/* QMSS LLD include */\r
+#include <ti/drv/qmss/qmss_drv.h>\r
+\r
+/* CPPI LLD include */\r
+#include <ti/drv/cppi/cppi_drv.h>\r
+#include <ti/drv/cppi/cppi_desc.h>\r
+\r
+/* CHIP module include */\r
+#include <ti/csl/csl_chip.h>\r
+\r
+/* BCP driver version header file */\r
+#include <ti/drv/bcp/bcpver.h>\r
+\r
+/** @defgroup BCP_API BCP Higher Layer Data Structures & APIs\r
+ *\r
+ * @section Introduction\r
+ *\r
+ * @subsection xxx Overview\r
+ * The BCP Driver is divided into 2 layers:\r
+ * -# Low Level Driver APIs\r
+ * -# High Level APIs\r
+ * \r
+ * The Low Level Driver APIs provide BCP MMR access by \r
+ * exporting register read/write APIs and also provides\r
+ * some useful helper APIs in putting together BCP global\r
+ * and submodule headers required by the hardware.\r
+ *\r
+ * The BCP Higher Layer provide APIs useful in submitting\r
+ * BCP requests and retrieving their results from the BCP. \r
+ *\r
+ * This section of documentation covers the Higher Layer\r
+ * APIs and data structures.\r
+ */\r
+\r
+/**\r
+@defgroup BCP_SYMBOL BCP Higher Layer Symbols Defined\r
+@ingroup BCP_API\r
+*/\r
+\r
+/**\r
+@defgroup BCP_DATASTRUCT BCP Higher Layer Data Structures\r
+@ingroup BCP_API\r
+*/\r
+\r
+/**\r
+@defgroup BCP_FUNCTION BCP Higher Layer Functions\r
+@ingroup BCP_API\r
+*/\r
+\r
+/**\r
+@defgroup BCP_OSAL_FUNCTION BCP OS Abstraction Layer Functions\r
+@ingroup BCP_API\r
+*/\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+/**\r
+@addtogroup BCP_SYMBOL\r
+@{\r
+*/\r
+\r
+/** @brief\r
+ * The number of BCP instances in the SoC.\r
+ */ \r
+#define BCP_MAX_NUM_INSTANCES (CSL_BCP_PER_CNT)\r
+\r
+/** @brief\r
+ * The number of CPPI flows reserved for each BCP instance.\r
+ */\r
+#define BCP_MAX_NUM_FLOWS (64)\r
+\r
+/** @brief\r
+ * The maximum number of Rx objects that will be tracked\r
+ * by the driver globally in the system across all cores.\r
+ */\r
+#define BCP_MAX_NUM_RXOBJECTS (64) \r
+\r
+/** @brief \r
+ *\r
+ * When returned this, indicates the API succeeded in \r
+ * its intent.\r
+ */\r
+#define BCP_RETVAL_SUCCESS (0)\r
+\r
+/** @brief \r
+ *\r
+ * When returned this, indicates that the handle passed\r
+ * to the API was invalid.\r
+ */\r
+#define BCP_RETVAL_EBAD_HANDLE (-1)\r
+\r
+/** @brief \r
+ *\r
+ * When returned this, indicates that the input configuration\r
+ * passed to the API is invalid.\r
+ */\r
+#define BCP_RETVAL_EINVALID_PARAMS (-2)\r
+\r
+/** @brief \r
+ *\r
+ * When returned this, indicates that the API's attempt to\r
+ * allocate memory or retrieve descriptors failed and \r
+ * is out of memory/descriptors.\r
+ */\r
+#define BCP_RETVAL_ENO_MEM (-3)\r
+\r
+/** @brief \r
+ *\r
+ * When returned this, indicates that there is no pending\r
+ * BCP processed output available for the application's Rx object.\r
+ */\r
+#define BCP_RETVAL_ENO_RESULT (-4)\r
+\r
+/** @brief \r
+ *\r
+ * When returned this, indicates that the API doesnt support\r
+ * the feature requested for the inputs passed.\r
+ */\r
+#define BCP_RETVAL_ENOT_SUPPORTED (-5)\r
+\r
+/** @brief \r
+ *\r
+ * When returned this, indicates a general error.\r
+ */\r
+#define BCP_RETVAL_EFAILURE (-6)\r
+\r
+/**\r
+@}\r
+*/\r
+\r
+/** @addtogroup BCP_DATASTRUCT\r
+ @{ */\r
+\r
+/** \r
+ * @brief Bcp_DrvHandle\r
+ * \r
+ * BCP driver handle.\r
+ */ \r
+typedef void* Bcp_DrvHandle;\r
+\r
+/** \r
+ * @brief Bcp_TxHandle\r
+ * \r
+ * BCP Tx object handle.\r
+ */ \r
+typedef void* Bcp_TxHandle;\r
+\r
+/** \r
+ * @brief Bcp_RxHandle\r
+ * \r
+ * BCP Rx object handle.\r
+ */ \r
+typedef void* Bcp_RxHandle;\r
+\r
+/** \r
+ * @brief Bcp_DrvBufferHandle\r
+ * \r
+ * BCP driver buffer object handle.\r
+ */ \r
+typedef void* Bcp_DrvBufferHandle;\r
+\r
+/** \r
+ * @brief Bcp_RetVal\r
+ * \r
+ * Holds the various error codes reported by \r
+ * the BCP driver.\r
+ *\r
+ * Please refer to BCP_RETVAL_* definitions for \r
+ * the various error codes reported by this driver.\r
+ */ \r
+typedef int32_t Bcp_RetVal;\r
+\r
+/** \r
+ * @brief Bcp_DrvMode\r
+ *\r
+ * Enumeration for specifying the BCP driver\r
+ * operational modes. Indicates if BCP is present\r
+ * locally on the SoC this driver is being used on\r
+ * or if it is remote.\r
+ */ \r
+typedef enum \r
+{\r
+ /** BCP is local to the device. \r
+ *\r
+ * BCP is present on the device (SoC) on which driver is being used\r
+ * currently. \r
+ */\r
+ Bcp_DrvMode_LOCAL = 0,\r
+\r
+ /** BCP is remotely accessible to the device. \r
+ *\r
+ * BCP is not present on the device (SoC) on which driver is being used\r
+ * currently. It can be accessed via SRIO.\r
+ */\r
+ Bcp_DrvMode_REMOTE = 1\r
+} Bcp_DrvMode;\r
+\r
+/** \r
+ * @brief Bcp_InitCfg\r
+ *\r
+ * BCP Peripheral Initialization configuration.\r
+ */ \r
+typedef struct _Bcp_InitCfg\r
+{\r
+ /** CPDMA Number corresponding to this BCP instance. */\r
+ Cppi_CpDma cpdmaNum;\r
+\r
+ /** Tx queue number base for this BCP instance. */\r
+ uint32_t baseTxQueueNum;\r
+\r
+ /** Base address for BCP configuration registers for this instance. */\r
+ uint32_t cfgRegsBaseAddress;\r
+\r
+ /** Callback functions to BCP transport layer. */\r
+\r
+ /** Called from Bcp_txOpen () API to initialize one endpoint of the Tx tunnel\r
+ * between device having BCP and remote device. Application developer should \r
+ * implement the necessary logic here to perform any setup required to send \r
+ * packets to BCP on the same/remote device as this device.\r
+ */\r
+ void* (*BcpTunnel_txOpen) (void* txEpCfg);\r
+\r
+ /** Called from Bcp_txClose () API to close a BCP tunnel Tx endpoint. */\r
+ int32_t (*BcpTunnel_txClose) (void* hTxEpInfo);\r
+\r
+ /** Called from Bcp_rxOpen () API to initialize one endpoint of the Rx tunnel\r
+ * between device having BCP and remote device. Application developer should \r
+ * implement the necessary logic here to perform any setup required to receive\r
+ * packets from BCP on the same/remote device as this device.\r
+ */\r
+ void* (*BcpTunnel_rxOpen) (void* rxEpCfg);\r
+\r
+ /** Called from Bcp_rxClose () API to close a BCP tunnel Rx endpoint. */\r
+ int32_t (*BcpTunnel_rxClose) (void* hRxEpInfo);\r
+\r
+ /** Called from Bcp_send () API to send out a packet through the tunnel\r
+ * to a remote BCP device. Invoked by BCP driver only if it was initialized in \r
+ * "remote" mode.\r
+ */\r
+ int32_t (*BcpTunnel_send) (void* hTxEpInfo, void* pPkt, uint32_t pktSize, void* pDestnDev);\r
+\r
+ /** Called from Bcp_recv () API to receive output from BCP using tunnel from a remote device.\r
+ * Invoked by BCP driver only if it was initialized in "remote" mode.\r
+ */\r
+ int32_t (*BcpTunnel_recv) (void* hRxEpInfo, void** pPkt);\r
+\r
+ /** Called from Bcp_rxFreeRecvBuffer () API to free an Rx packet obtained using Bcp_recv ()\r
+ * API. Invoked by BCP driver only if it was initialized in "remote" mode.\r
+ */\r
+ int32_t (*BcpTunnel_freeRecvBuffer) (void* hRxEpInfo, void* pPkt, uint32_t pktSize);\r
+} Bcp_InitCfg;\r
+\r
+\r
+/** \r
+ * @brief Bcp_DrvCfg\r
+ *\r
+ * BCP Driver configuration.\r
+ */ \r
+typedef struct _Bcp_DrvCfg\r
+{\r
+ uint32_t dummy; \r
+} Bcp_DrvCfg;\r
+\r
+/** \r
+ * @brief Bcp_TxCfg\r
+ *\r
+ * BCP Tx object configuration.\r
+ */ \r
+typedef struct _Bcp_TxCfg\r
+{\r
+ /** BCP Tx queue number to use for sending data to BCP. \r
+ *\r
+ * Valid values are 0 - BCP_MAX_NUM_TXQUEUES\r
+ */ \r
+ Bcp_QueueId txQNum;\r
+} Bcp_TxCfg;\r
+\r
+/** \r
+ * @brief Bcp_RxCfg\r
+ *\r
+ * BCP Rx object configuration.\r
+ */ \r
+typedef struct _Bcp_RxCfg\r
+{\r
+ /** Rx queue number on which data from BCP must be\r
+ * received. \r
+ *\r
+ * This can be set to -1 to let the driver pick a Rx\r
+ * queue number.\r
+ */ \r
+ int32_t rxQNum;\r
+\r
+ /** CPPI Receive flow configuration. */ \r
+ Cppi_RxFlowCfg flowCfg;\r
+\r
+ /** Corresponding BCP Traffic Manager flow configuration */\r
+ Bcp_TmFlowEntry tmFlowCfg;\r
+\r
+ /** Boolean flag to indicate whether if interrupt support is \r
+ * required for this Rx object.\r
+ *\r
+ * When set to 1, indicates that accumulation interrupts must \r
+ * be used for this Rx object.\r
+ */\r
+ uint8_t bUseInterrupts;\r
+\r
+ /* Accumulator configuration to use for this Rx object. */\r
+ Qmss_AccCmdCfg accumCfg;\r
+} Bcp_RxCfg;\r
+\r
+/**\r
+@}\r
+*/\r
+\r
+extern uint32_t Bcp_getVersionID \r
+( \r
+ void\r
+);\r
+\r
+extern const char* Bcp_getVersionStr \r
+(\r
+ void\r
+);\r
+\r
+extern Bcp_RetVal Bcp_init\r
+(\r
+ uint8_t instNum, \r
+ Bcp_DrvMode mode,\r
+ Bcp_InitCfg* pBcpInitCfg\r
+);\r
+\r
+extern Bcp_RetVal Bcp_deInit \r
+(\r
+ uint8_t instNum\r
+);\r
+\r
+extern uint8_t Bcp_isInitialized\r
+(\r
+ uint8_t instNum\r
+);\r
+\r
+extern Bcp_LldObj* Bcp_getLLDHandle \r
+(\r
+ uint8_t instNum\r
+);\r
+\r
+extern Bcp_DrvHandle Bcp_open \r
+(\r
+ uint8_t instNum,\r
+ Bcp_DrvCfg* pBcpDrvCfg,\r
+ Bcp_RetVal* pRetVal\r
+);\r
+\r
+extern Bcp_RetVal Bcp_close \r
+(\r
+ Bcp_DrvHandle hBcp\r
+);\r
+\r
+extern Bcp_TxHandle Bcp_txOpen\r
+(\r
+ Bcp_DrvHandle hBcp,\r
+ Bcp_TxCfg* pBcpTxCfg,\r
+ void* pTxEndpointCfg\r
+);\r
+\r
+extern Bcp_RetVal Bcp_txClose \r
+(\r
+ Bcp_TxHandle hBcpTxInfo\r
+);\r
+\r
+extern Bcp_RxHandle Bcp_rxOpen\r
+(\r
+ Bcp_DrvHandle hBcp,\r
+ Bcp_RxCfg* pBcpRxCfg,\r
+ void* pRxEndpointCfg\r
+);\r
+\r
+extern Bcp_RetVal Bcp_rxClose \r
+(\r
+ Bcp_RxHandle hBcpRxInfo\r
+);\r
+\r
+extern Bcp_RetVal Bcp_rxGetRxQueueNumber\r
+(\r
+ Bcp_RxHandle hBcpRxInfo\r
+);\r
+\r
+extern Bcp_RetVal Bcp_rxGetFlowId\r
+(\r
+ Bcp_RxHandle hBcpRxInfo\r
+);\r
+\r
+extern Bcp_RetVal Bcp_findFlowIdByQueueNumber\r
+(\r
+ Bcp_DrvHandle hBcp,\r
+ uint32_t rxQueueNumber\r
+);\r
+\r
+extern Bcp_RetVal Bcp_send \r
+(\r
+ Bcp_TxHandle hBcpTxInfo,\r
+ Bcp_DrvBufferHandle hDrvBuffer,\r
+ uint32_t drvBufferLen,\r
+ void* pDestnAddress\r
+);\r
+\r
+extern int32_t Bcp_rxGetNumOutputEntries \r
+(\r
+ Bcp_RxHandle hBcpRxInfo\r
+);\r
+\r
+extern Bcp_RetVal Bcp_recv\r
+(\r
+ Bcp_RxHandle hBcpRxInfo,\r
+ Bcp_DrvBufferHandle* phDrvBuffer,\r
+ uint8_t** ppDataBuffer,\r
+ uint32_t* pDataBufferLen, \r
+ uint8_t** ppPSInfo,\r
+ uint32_t* pPSInfoLen,\r
+ uint8_t* pFlowId,\r
+ uint8_t* pSrcId,\r
+ uint16_t* pDestnTagInfo\r
+);\r
+\r
+extern Bcp_RetVal Bcp_rxProcessDesc \r
+(\r
+ Bcp_RxHandle hBcpRxInfo,\r
+ Cppi_Desc* pCppiDesc,\r
+ Bcp_DrvBufferHandle* phDrvBuffer,\r
+ uint8_t** ppDataBuffer,\r
+ uint32_t* pDataBufferLen, \r
+ uint8_t** ppPSInfo,\r
+ uint32_t* pPSInfoLen,\r
+ uint8_t* pFlowId,\r
+ uint8_t* pSrcId,\r
+ uint16_t* pDestnTagInfo\r
+);\r
+\r
+extern Bcp_RetVal Bcp_rxFreeRecvBuffer\r
+(\r
+ Bcp_RxHandle hBcpRxInfo,\r
+ Bcp_DrvBufferHandle hDrvBuffer,\r
+ uint32_t drvBufferLen\r
+);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __BCP_H__ */\r
+\r
diff --git a/packages/ti/drv/bcp/bcp_lld.h b/packages/ti/drv/bcp/bcp_lld.h
--- /dev/null
@@ -0,0 +1,2298 @@
+/** \r
+ * @file bcp_lld.h\r
+ *\r
+ * @brief \r
+ * Header file with data structure and API declarations for BCP Low\r
+ * Level Driver (LLD).\r
+ * \r
+ * \par\r
+ * ============================================================================\r
+ * @n (C) Copyright 2010, Texas Instruments, Inc.\r
+ * \r
+ * Redistribution and use in source and binary forms, with or without \r
+ * modification, are permitted provided that the following conditions \r
+ * are met:\r
+ *\r
+ * Redistributions of source code must retain the above copyright \r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the \r
+ * documentation and/or other materials provided with the \r
+ * distribution.\r
+ *\r
+ * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \r
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT \r
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT \r
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \r
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT \r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT \r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE \r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+*/\r
+\r
+/** @defgroup BCP_LLD_API BCP LLD Data Structures & APIs\r
+ *\r
+ * @section Introduction\r
+ *\r
+ * @subsection xxx Overview\r
+ * The bit coprocessor (BCP) is an acceleration engine for wireless \r
+ * infrastructure. It accelerates the otherwise DSP intensive bit processing \r
+ * functions like encoding, scrambling, interleaving, rate matching, soft slicing\r
+ * and modulation in hardware. The BCP supports LTE, FDD WCDMA, TD-SDCDMA, and\r
+ * WiMax 802.16-2009.\r
+ *\r
+ * This section of the documentation covers the BCP Low Level Driver (LLD)\r
+ * APIs that include BCP MMR access APIs and some utility APIs for building\r
+ * the BCP Global and Sub module headers.\r
+ *\r
+ * @subsection References\r
+ * -# BCP Users Guide\r
+ */\r
+#ifndef _BCP_LLD_H_\r
+#define _BCP_LLD_H_\r
+\r
+/* BCP CSL Register file and CSL definitions include */\r
+#include <ti/csl/csl.h>\r
+#include <ti/csl/cslr_bcp.h>\r
+#include <ti/csl/soc.h>\r
+\r
+/**\r
+@defgroup BCP_LLD_SYMBOL BCP LLD Symbols Defined\r
+@ingroup BCP_LLD_API\r
+*/\r
+\r
+/**\r
+@defgroup BCP_LLD_DATASTRUCT BCP LLD Data Structures\r
+@ingroup BCP_LLD_API\r
+*/\r
+\r
+/**\r
+@defgroup BCP_LLD_FUNCTION BCP LLD Functions\r
+@ingroup BCP_LLD_API\r
+*/\r
+\r
+#ifdef __cplusplus\r
+extern "C"\r
+{\r
+#endif\r
+\r
+/**\r
+@addtogroup BCP_LLD_SYMBOL\r
+@{\r
+*/\r
+\r
+/** @brief\r
+ * Maximum number of BCP Tx queues available.\r
+ */ \r
+#define BCP_MAX_NUM_TXQUEUES (8)\r
+\r
+/** @brief\r
+ * Maximum number of TM Flow entries available.\r
+ */ \r
+#define BCP_MAX_NUM_TM_FLOWS (64)\r
+\r
+/** @brief\r
+ * Maximum number of PS Info words (32 bit words) supported \r
+ * by the BCP.\r
+ */ \r
+#define BCP_MAX_NUM_PS_WORDS (8) \r
+\r
+/** @brief\r
+ * Maximum number of User Info words (32 bit words) supported \r
+ * by the BCP.\r
+ */ \r
+#define BCP_MAX_NUM_USER_INFO_WORDS (124) \r
+\r
+/** Well know submodule engine header lengths. */ \r
+#define BCP_TM_HDR_LEN (1)\r
+\r
+/** Number of Submodules in BCP */\r
+#define BCP_NUM_SUBMODULES (14) \r
+\r
+/**\r
+@}\r
+*/\r
+\r
+/** @addtogroup BCP_LLD_DATASTRUCT\r
+ @{ */\r
+\r
+typedef CSL_Bcp_encRegs* Bcp_EncRegsOvly;\r
+typedef CSL_Bcp_corRegs* Bcp_CorRegsOvly;\r
+typedef CSL_Bcp_tmRegs* Bcp_TmRegsOvly;\r
+typedef CSL_Bcp_dioRegs* Bcp_DioRegsOvly;\r
+typedef CSL_Bcp_IntRegs* Bcp_IntRegsOvly;\r
+typedef CSL_Bcp_DataLoggerRegs* Bcp_DlgRegsOvly;\r
+typedef CSL_Bcp_DataLoggerRAM* Bcp_DlgRamRegsOvly;\r
+\r
+\r
+typedef struct _Bcp_LldObj\r
+{\r
+ /** BCP Peripheral instance number */\r
+ uint8_t instNum;\r
+\r
+ /** Config Registers Base address for each of submodules */\r
+ void* modCfgRegs [BCP_NUM_SUBMODULES]; \r
+\r
+ /** Interrupt Registers Base address for each of submodules */\r
+ Bcp_IntRegsOvly modIntRegs [BCP_NUM_SUBMODULES]; \r
+\r
+ /** Data Logger Registers Base address for each of submodules */\r
+ Bcp_DlgRegsOvly modDlgRegs [BCP_NUM_SUBMODULES];\r
+\r
+ /** Data Logger RAM Registers Base address for each of submodules */\r
+ Bcp_DlgRamRegsOvly modDlgRamRegs [BCP_NUM_SUBMODULES];\r
+} Bcp_LldObj;\r
+\r
+/** \r
+ * @brief Bcp_QueueId\r
+ *\r
+ * Enumeration for specifying the BCP Tx Queues.\r
+ */ \r
+typedef enum \r
+{\r
+ /** BCP Tx Queue 0 */\r
+ Bcp_QueueId_0 = 0,\r
+ /** BCP Tx Queue 1 */\r
+ Bcp_QueueId_1 = 1,\r
+ /** BCP Tx Queue 2 */\r
+ Bcp_QueueId_2 = 2,\r
+ /** BCP Tx Queue 3 */\r
+ Bcp_QueueId_3 = 3,\r
+ /** BCP Tx Queue 4 */\r
+ Bcp_QueueId_4 = 4,\r
+ /** BCP Tx Queue 5 */\r
+ Bcp_QueueId_5 = 5,\r
+ /** BCP Tx Queue 6 */\r
+ Bcp_QueueId_6 = 6,\r
+ /** BCP Tx Queue 7 */\r
+ Bcp_QueueId_7 = 7\r
+} Bcp_QueueId;\r
+\r
+/** \r
+ * @brief Bcp_ModuleId\r
+ *\r
+ * Enumeration for specifying the Ids for various\r
+ * BCP submodule engines.\r
+ */ \r
+typedef enum \r
+{\r
+ /** TM */\r
+ Bcp_ModuleId_TM = 0,\r
+ /** Interleaver engine (4) */\r
+ Bcp_ModuleId_INT = 4,\r
+ /** Rate Modulation engine (5) */\r
+ Bcp_ModuleId_RM = 5,\r
+ /** Encoder engine (6) */\r
+ Bcp_ModuleId_ENC = 6,\r
+ /** Modulation engine (7) */\r
+ Bcp_ModuleId_MOD = 7,\r
+ /** CRC engine (8) */\r
+ Bcp_ModuleId_CRC = 8,\r
+ /** Soft Slicer engine (9) */\r
+ Bcp_ModuleId_SSL = 9,\r
+ /** Rate de-matcher engine (10) */\r
+ Bcp_ModuleId_RD = 10,\r
+ /** Correlation engine (11) */\r
+ Bcp_ModuleId_COR = 11,\r
+ /** De-interleaver engine (12) */\r
+ Bcp_ModuleId_DNT = 12,\r
+ /** Direct Input Output (13) */\r
+ Bcp_ModuleId_DIO = 13\r
+} Bcp_ModuleId;\r
+\r
+/** \r
+ * @brief Bcp_PacketType\r
+ *\r
+ * Enumeration for specifying the packet type.\r
+ */ \r
+typedef enum \r
+{\r
+ /** Normal Packet */\r
+ Bcp_PacketType_Normal = 0,\r
+ /** Start of multi-packet packet */\r
+ Bcp_PacketType_SOM = 1,\r
+ /** Middle of multi-packet packet */\r
+ Bcp_PacketType_MOM = 2,\r
+ /** End of multi-packet packet */\r
+ Bcp_PacketType_EOM = 3\r
+} Bcp_PacketType;\r
+\r
+/** \r
+ * @brief Bcp_RadioStd\r
+ *\r
+ * Enumeration for specifying the radio standard\r
+ * to be used for the packet.\r
+ */ \r
+typedef enum \r
+{\r
+ /** LTE */\r
+ Bcp_RadioStd_LTE = 0,\r
+ /** WiMax 802.16e */\r
+ Bcp_RadioStd_WIMAX_802_16E = 2,\r
+ /** WCDMA R99 */\r
+ Bcp_RadioStd_WCDMA_R99 = 4,\r
+ /** HSPA */\r
+ Bcp_RadioStd_HSPA = 5\r
+} Bcp_RadioStd;\r
+\r
+/** \r
+ * @brief Bcp_EndianFormat\r
+ *\r
+ * Enumeration for specifying BCP/TM input/output\r
+ * endian formats.\r
+ */ \r
+typedef enum \r
+{\r
+ /** 128 bit words */\r
+ Bcp_EndianFormat_128 = 0,\r
+ /** 32 bit words */\r
+ Bcp_EndianFormat_32 = 1,\r
+ /** 16 bit words */\r
+ Bcp_EndianFormat_16 = 2,\r
+ /** 8 bit words */\r
+ Bcp_EndianFormat_8 = 3\r
+} Bcp_EndianFormat;\r
+\r
+/** \r
+ * @brief Bcp_DataFormat\r
+ *\r
+ * Enumeration for specifying BCP/TM input/output\r
+ * data formats.\r
+ */ \r
+typedef enum \r
+{\r
+ /** No change */\r
+ Bcp_DataFormat_NoChange = 0,\r
+ /** Reverse 32 bit words */\r
+ Bcp_DataFormat_Reverse32 = 1,\r
+ /** Reverse 16 bit words */\r
+ Bcp_DataFormat_Reverse16 = 2,\r
+ /** Reverse 8 bit words */\r
+ Bcp_DataFormat_Reverse8 = 3,\r
+ /** Swap 32 bit words */\r
+ Bcp_DataFormat_Swap32 = 5,\r
+ /** Swap 16 bit words */\r
+ Bcp_DataFormat_Swap16 = 6,\r
+ /** Swap 8 bit words */\r
+ Bcp_DataFormat_Swap8 = 7\r
+} Bcp_DataFormat;\r
+\r
+/** \r
+ * @brief Bcp_GlobalHdrCfg\r
+ *\r
+ * Structure to specify the BCP global header \r
+ * configuration parameters.\r
+ */ \r
+typedef struct _Bcp_GlobalHdrCfg\r
+{\r
+ /** Global Header Word 0 */ \r
+ \r
+ /** Packet type */ \r
+ Bcp_PacketType pkt_type;\r
+\r
+ /** Flush bit. When enabled stops Tx arbitration of \r
+ * QFIFO until the CDMAHP finishes writing the resulting\r
+ * packet back into memory.\r
+ */\r
+ uint8_t flush;\r
+\r
+ /** Drop bit. Used to fill CDMAHP_FIFO with unused data \r
+ * so flush does not end with stale data in CDMAHP_FIFO.\r
+ */\r
+ uint8_t drop;\r
+\r
+ /** Halt bit. When set, generates a soft stop with \r
+ * an interrupt when BCP goes idle.\r
+ */\r
+ uint8_t halt;\r
+\r
+ /** Radio standard to use for the flow */\r
+ Bcp_RadioStd radio_standard;\r
+\r
+ /** Number of 32 bit words with header information. */\r
+ uint8_t hdr_end_ptr;\r
+\r
+ /** Flow Id */\r
+ uint8_t flow_id;\r
+\r
+ /** Global Header Word 1 */ \r
+ \r
+ /** Application defined destination tag info to be\r
+ * passed to Rx end. \r
+ *\r
+ * Can be set to a unique sequence number to identify \r
+ * the packet.\r
+ */\r
+ uint16_t destn_tag;\r
+} Bcp_GlobalHdrCfg;\r
+\r
+/** \r
+ * @brief Bcp_TmHdrCfg\r
+ *\r
+ * Structure to specify the Traffic Manager (TM) header \r
+ * configuration parameters.\r
+ */ \r
+typedef struct _Bcp_TmHdrCfg\r
+{\r
+ /** Number of 32 bit words of PS data to be streamed across \r
+ *\r
+ * Valid values are: 0 - 8\r
+ */ \r
+ uint8_t ps_data_size;\r
+\r
+ /** Number of 128 bit words of information. \r
+ *\r
+ * Valid values are: 0 - 31\r
+ */\r
+ uint8_t info_data_size;\r
+} Bcp_TmHdrCfg;\r
+ \r
+/** \r
+ * @brief Bcp_CrcFormat\r
+ *\r
+ * Enumeration for specifying the CRC\r
+ * formats.\r
+ */ \r
+typedef enum \r
+{\r
+ /** CRC 0 */\r
+ Bcp_CrcFormat_Crc0 = 0,\r
+ /** CRC 8 */\r
+ Bcp_CrcFormat_Crc8 = 1,\r
+ /** CRC 12 */\r
+ Bcp_CrcFormat_Crc12 = 2,\r
+ /** CRC 16 */\r
+ Bcp_CrcFormat_Crc16 = 3,\r
+ /** CRC 16w */\r
+ Bcp_CrcFormat_Crc16w = 4,\r
+ /** CRC 24a */\r
+ Bcp_CrcFormat_Crc24a = 5,\r
+ /** CRC 24b */\r
+ Bcp_CrcFormat_Crc24b = 6,\r
+ /** CRC 32 */\r
+ Bcp_CrcFormat_Crc32 = 7\r
+} Bcp_CrcFormat;\r
+\r
+/** \r
+ * @brief Bcp_CrcHdrCfg\r
+ *\r
+ * Structure to specify the CRC header configuration\r
+ * parameters.\r
+ */ \r
+typedef struct _Bcp_CrcHdrCfg\r
+{\r
+ /** CRC Header Word 0 */ \r
+\r
+ /** Local header length (Not including Header word 0). \r
+ *\r
+ * Set to 8 for Long header format and all the 8 words of\r
+ * configuration will be used in CRC header. Set to 3 for\r
+ * Short header format and only the first 3 words of configuration\r
+ * are used in CRC header. \r
+ */\r
+ uint8_t local_hdr_len; \r
+\r
+ /** Number of filler bits to use.\r
+ *\r
+ * Number of filler bits (zeros) to insert at beginning of \r
+ * each packet payload. Can range between 0-255.\r
+ */\r
+ uint8_t filler_bits;\r
+\r
+ /** Boolean flag to indicate if CRC bits must be appended\r
+ * in LTE / WCDMA order.\r
+ *\r
+ * Set to 1 for LTE order and 0 for WCDMA.\r
+ */\r
+ uint8_t bit_order;\r
+\r
+ /** DTX Data format.\r
+ *\r
+ * Set to 1 for 2-bit data (DTX:data) and 0 for 1-bit\r
+ * data (data only).\r
+ */\r
+ uint8_t dtx_format;\r
+\r
+ /** CRC Header Word 1 */ \r
+\r
+ /** Scrambler initialization value for 8bits/clock. */\r
+ uint32_t num_scramble_sys;\r
+\r
+ /** CRC Header Word 2 */ \r
+\r
+ /** CRC Method 2 Id. */\r
+ uint32_t method2_id;\r
+\r
+ /** CRC Header Word 3 */ \r
+\r
+ /** Voice A Transport Block Length. \r
+ *\r
+ * Must be set to number of data bits in each transport block\r
+ * of the transport channel.\r
+ */\r
+ uint32_t va_blk_len;\r
+\r
+ /** Voice A CRC format. */\r
+ Bcp_CrcFormat va_crc;\r
+\r
+ /** Voice A Blocks - Number of transport blocks in this transport\r
+ * channel.\r
+ *\r
+ * Can be any value between 0-255.\r
+ */\r
+ uint8_t va_blks;\r
+\r
+ /** CRC Header Word 4 */ \r
+\r
+ /** Voice B Transport Block Length. \r
+ *\r
+ * Must be set to number of data bits in each transport block\r
+ * of the transport channel.\r
+ */\r
+ uint32_t vb_blk_len;\r
+\r
+ /** Voice B CRC format. */\r
+ Bcp_CrcFormat vb_crc;\r
+\r
+ /** Voice B Blocks - Number of transport blocks in this transport\r
+ * channel.\r
+ *\r
+ * Can be any value between 0-255.\r
+ */\r
+ uint8_t vb_blks;\r
+\r
+ /** CRC Header Word 5 */ \r
+\r
+ /** Voice C Transport Block Length. \r
+ *\r
+ * Must be set to number of data bits in each transport block\r
+ * of the transport channel.\r
+ */\r
+ uint32_t vc_blk_len;\r
+\r
+ /** Voice C CRC format. */\r
+ Bcp_CrcFormat vc_crc;\r
+\r
+ /** Voice C Blocks - Number of transport blocks in this transport\r
+ * channel.\r
+ *\r
+ * Can be any value between 0-255.\r
+ */\r
+ uint8_t vc_blks;\r
+\r
+ /** CRC Header Word 6 */ \r
+\r
+ /** Data 1 Transport Block Length. \r
+ *\r
+ * Must be set to number of data bits in each transport block\r
+ * of the transport channel.\r
+ */\r
+ uint32_t d1_blk_len;\r
+\r
+ /** Data 1 CRC format. */\r
+ Bcp_CrcFormat d1_crc;\r
+\r
+ /** Data 1 Blocks - Number of transport blocks in this transport\r
+ * channel.\r
+ *\r
+ * Can be any value between 0-255.\r
+ */\r
+ uint8_t d1_blks;\r
+\r
+ /** CRC Header Word 7 */ \r
+\r
+ /** Data 2 Transport Block Length. \r
+ *\r
+ * Must be set to number of data bits in each transport block\r
+ * of the transport channel.\r
+ */\r
+ uint32_t d2_blk_len;\r
+\r
+ /** Data 2 CRC format. */\r
+ Bcp_CrcFormat d2_crc;\r
+\r
+ /** Data 2 Blocks - Number of transport blocks in this transport\r
+ * channel.\r
+ *\r
+ * Can be any value between 0-255.\r
+ */\r
+ uint8_t d2_blks;\r
+\r
+ /** CRC Header Word 8 */ \r
+\r
+ /** DCCH Transport Block Length. \r
+ *\r
+ * Must be set to number of data bits in each transport block\r
+ * of the transport channel.\r
+ */\r
+ uint32_t dc_blk_len;\r
+\r
+ /** DCCH CRC format. */\r
+ Bcp_CrcFormat dc_crc;\r
+\r
+ /** DCCH Blocks - Number of transport blocks in this transport\r
+ * channel.\r
+ *\r
+ * Can be any value between 0-255.\r
+ */\r
+ uint8_t dc_blks;\r
+} Bcp_CrcHdrCfg;\r
+\r
+/** \r
+ * @brief Bcp_RmHdr_ChannelCfg\r
+ *\r
+ * Structure to specify/hold the WCDMA/TD-SCDMA \r
+ * Rate Modulation (RM) Header Channel configuration \r
+ * parameters.\r
+ */ \r
+typedef struct _Bcp_RmHdr_ChannelCfg\r
+{\r
+ /** Channel 'n' length before rate matching */\r
+ uint16_t sys_len;\r
+\r
+ /** Channel 'n' initial value for 2nd rate matching loop */\r
+ uint16_t sys_init2;\r
+\r
+ /** Channel 'n' minus value for 2nd rate matching loop */\r
+ uint16_t sys_minus2;\r
+\r
+ /** Channel 'n' plus value for 2nd rate matching loop */\r
+ uint16_t sys_plus2;\r
+\r
+ /** Channel 'n' TD-SCDMA alpha value for bit separation */\r
+ uint8_t sys_aplha;\r
+\r
+ /** Channel 'n' TD-SCDMA beta value for bit separation */\r
+ uint8_t sys_beta;\r
+\r
+ /** Puncture flag \r
+ *\r
+ * Set to:\r
+ * 0 - Perform repeat in second rate matching loop\r
+ * 1 - Perform puncture in second rate matching loop\r
+ */\r
+ uint8_t sys_puncture;\r
+\r
+ /** Channel type.\r
+ *\r
+ * Set to:\r
+ * 0 - Convolutional or Rel-99 Turbo Repeat\r
+ * 1 - Rel-99 style Turbo puncture, use p0 parity params\r
+ * 2 - Rel-99 style Turbo puncture, use p1 parity params\r
+ */\r
+ uint8_t sys_turbo;\r
+}Bcp_RmHdr_ChannelCfg;\r
+\r
+/** \r
+ * @brief Bcp_RmHdr_xCdmaCfg\r
+ *\r
+ * Structure to specify/hold the WCDMA/TD-SCDMA \r
+ * Rate Modulation (RM) Header configuration parameters.\r
+ */ \r
+typedef struct _Bcp_RmHdr_xCdmaCfg\r
+{\r
+ /** RM Header Word 0 */ \r
+\r
+ /** Local header length (Not including Header word 0). \r
+ *\r
+ * Can be 20, 23, 26, 29, 32, 35, 39.\r
+ */\r
+ uint8_t local_hdr_len; \r
+\r
+ /** Input ordering mode.\r
+ *\r
+ * Set to:\r
+ * 0 - Bit interleaved from Interleaver module.\r
+ * 1 - Quad word interleaved from Encoder module.\r
+ */\r
+ uint8_t input_order;\r
+\r
+ /** Input encoding.\r
+ *\r
+ * Set to:\r
+ * 0 - 1/3 rate convolution or turbo encoded.\r
+ * 1 - 1/2 rate convolution encoded.\r
+ */\r
+ uint8_t half_rate;\r
+\r
+ /** RM Header Word 1 */\r
+\r
+ /** Collect columns - Number of columns in bit collection table. */\r
+ uint32_t collect_cols;\r
+\r
+ /** Collect rows - Number of rows in bit collection table. */\r
+ uint8_t collect_rows;\r
+\r
+ /** RM Header Word 2 */\r
+\r
+ /** Scrambler initialization value for TD-SCDMA systematic HSDPA. */\r
+ uint16_t num_scram;\r
+\r
+ /** RM Header Word 3 */\r
+ /** Sys0 length before rate-matching. */\r
+ uint32_t sys0_len;\r
+\r
+ /** RM Header Word 4 */\r
+ /** Sys0 initial value for 2nd rate matching loop. */\r
+ uint32_t sys0_init2;\r
+\r
+ /** RM Header Word 5 */\r
+ /** Sys0 minus value for 2nd rate matching loop. */\r
+ uint32_t sys0_minus2;\r
+\r
+ /** RM Header Word 6 */\r
+ /** Sys0 plus value for 2nd rate matching loop. */\r
+ uint32_t sys0_plus2;\r
+\r
+ /** Sys0 TD-SDCDMA aplha value for bit separation. */\r
+ uint8_t sys0_alpha;\r
+\r
+ /** Sys0 TD-SDCDMA beta value for bit separation. */\r
+ uint8_t sys0_beta;\r
+\r
+ /** Puncture flag \r
+ *\r
+ * Set to:\r
+ * 0 - Perform repeat in second rate matching loop\r
+ * 1 - Perform puncture in second rate matching loop\r
+ */\r
+ uint8_t sys0_puncture;\r
+\r
+ /** Channel type.\r
+ *\r
+ * Set to:\r
+ * 0 - Convolutional or Rel-99 Turbo Repeat\r
+ * 1 - Rel-99 style Turbo puncture, use p0 parity params\r
+ * 2 - Rel-99 style Turbo puncture, use p1 parity params\r
+ * 3 - HSDPA style turbo channel, use p0 params.\r
+ */\r
+ uint8_t sys0_turbo;\r
+\r
+ /** RM Header Word 7 */\r
+ /** p0 Parity1 length before rate matching */\r
+ uint32_t p0_par1_len;\r
+\r
+ /** RM Header Word 8 */\r
+ /** p0 Parity1 initial value for 1st rate matching loop */\r
+ uint32_t p0_par1_init1;\r
+\r
+ /** RM Header Word 9 */\r
+ /** p0 Parity1 minus value for 1st rate matching loop */\r
+ uint32_t p0_par1_minus1;\r
+\r
+ /** RM Header Word 10 */\r
+ /** p0 Parity1 plus value for 1st rate matching loop */\r
+ uint32_t p0_par1_plus1;\r
+\r
+ /** RM Header Word 11 */\r
+ /** p0 Parity1 initial value for 2nd rate matching loop */\r
+ uint32_t p0_par1_init2;\r
+\r
+ /** RM Header Word 12 */\r
+ /** p0 Parity1 minus value for 2nd rate matching loop */\r
+ uint32_t p0_par1_minus2;\r
+\r
+ /** RM Header Word 13 */\r
+ /** p0 Parity1 plus value for 2nd rate matching loop */\r
+ uint32_t p0_par1_plus2;\r
+\r
+ /** RM Header Word 14 */\r
+ /** p0 Parity2 length before rate matching */\r
+ uint32_t p0_par2_len;\r
+\r
+ /** RM Header Word 15 */\r
+ /** p0 Parity2 initial value for 1st rate matching loop */\r
+ uint32_t p0_par2_init1;\r
+\r
+ /** RM Header Word 16 */\r
+ /** p0 Parity2 minus value for 1st rate matching loop */\r
+ uint32_t p0_par2_minus1;\r
+\r
+ /** RM Header Word 17 */\r
+ /** p0 Parity2 plus value for 1st rate matching loop */\r
+ uint32_t p0_par2_plus1;\r
+\r
+ /** RM Header Word 18 */\r
+ /** p0 Parity2 initial value for 2nd rate matching loop */\r
+ uint32_t p0_par2_init2;\r
+\r
+ /** RM Header Word 19 */\r
+ /** p0 Parity2 minus value for 2nd rate matching loop */\r
+ uint32_t p0_par2_minus2;\r
+\r
+ /** RM Header Word 20 */\r
+ /** p0 Parity2 plus value for 2nd rate matching loop */\r
+ uint32_t p0_par2_plus2;\r
+\r
+ /** RM Header Word 21-35 */\r
+ Bcp_RmHdr_ChannelCfg channelCfg [5];\r
+\r
+ /** RM Header Word 36 */\r
+ /** p1 Parity1 length before rate matching */\r
+ uint16_t p1_par1_len;\r
+\r
+ /** p1 Parity1 initial value for 2nd rate matching loop */\r
+ uint16_t p1_par1_init2;\r
+\r
+ /** RM Header Word 37 */\r
+ /** p1 Parity1 minus value for 2nd rate matching loop */\r
+ uint16_t p1_par1_minus2;\r
+\r
+ /** p1 Parity1 plus value for 2nd rate matching loop */\r
+ uint16_t p1_par1_plus2;\r
+\r
+ /** RM Header Word 38 */\r
+ /** p1 Parity2 length before rate matching */\r
+ uint16_t p1_par2_len;\r
+\r
+ /** p1 Parity2 initial value for 2nd rate matching loop */\r
+ uint16_t p1_par2_init2;\r
+\r
+ /** RM Header Word 39 */\r
+ /** p1 Parity2 minus value for 2nd rate matching loop */\r
+ uint16_t p1_par2_minus2;\r
+\r
+ /** p1 Parity2 plus value for 2nd rate matching loop */\r
+ uint16_t p1_par2_plus2;\r
+} Bcp_RmHdr_xCdmaCfg;\r
+\r
+/** \r
+ * @brief Bcp_RmHdr_LteCfg\r
+ *\r
+ * Structure to specify/hold the LTE Rate Modulation (RM)\r
+ * Header configuration parameters.\r
+ */ \r
+typedef struct _Bcp_RmHdr_LteCfg\r
+{ \r
+ /** RM Header Word 0 */ \r
+\r
+ /** Local header length (Not including Header word 0). */\r
+ uint8_t local_hdr_len; \r
+\r
+ /** RM Header Word 1 */ \r
+\r
+ /** LTE channel type.\r
+ *\r
+ * Set to:\r
+ * 0 - Shared channel\r
+ * 1 - Control channel\r
+ */\r
+ uint8_t channel_type;\r
+\r
+ /** Input bit format.\r
+ *\r
+ * Set to:\r
+ * 0 - Input bits are hard bits stored in packet\r
+ * format as one bit per stream bit.\r
+ * 1 - Input bits are soft bits stored as one soft\r
+ * bit per stream byte.\r
+ */\r
+ uint8_t input_bit_format;\r
+\r
+ /** Output bit format. */\r
+ uint8_t output_bit_format;\r
+\r
+ /** Number of filler bits (F) in the first code block. \r
+ *\r
+ * Valid values: 0-63\r
+ */\r
+ uint8_t num_filler_bits_f;\r
+\r
+ uint8_t rv_start_column1;\r
+ uint8_t rv_start_column2;\r
+\r
+ /** RM Header word 2 */\r
+\r
+ uint8_t param_ncb1_column;\r
+ uint16_t param_ncb1_row;\r
+ uint8_t param_ncb2_column;\r
+ uint16_t param_ncb2_row;\r
+\r
+ /** RM Header word 3 */\r
+\r
+ uint8_t num_code_blocks_c1;\r
+ uint16_t block_size_k1;\r
+\r
+ /** RM Header word 4 */\r
+\r
+ uint8_t num_code_blocks_ce1;\r
+ uint16_t block_size_e1;\r
+\r
+ /** RM Header word 5 */\r
+\r
+ uint8_t num_code_blocks_c2;\r
+ uint16_t block_size_k2;\r
+\r
+ /** RM Header word 6 */\r
+\r
+ uint8_t num_code_blocks_ce2;\r
+ uint16_t block_size_e2;\r
+} Bcp_RmHdr_LteCfg;\r
+\r
+/** \r
+ * @brief Bcp_RmHdr_WiMaxCfg\r
+ *\r
+ * Structure to specify/hold the WiMax Rate Modulation (RM)\r
+ * Header configuration parameters.\r
+ */ \r
+typedef struct _Bcp_RmHdr_WiMaxCfg\r
+{ \r
+ /** RM Header Word 0 */ \r
+\r
+ /** Local header length (Not including Header word 0). */\r
+ uint8_t local_hdr_len; \r
+\r
+ /** RM Header Word 1 */ \r
+\r
+ /** Number of code blocks C1 of size K1 */\r
+ uint8_t num_code_blocks_c1;\r
+\r
+ /** Code block size K1 */\r
+ uint16_t block_size_k1;\r
+\r
+ /** RM Header Word 2 */ \r
+\r
+ /** Sub-block interleaver parameter 'm' for codeblock of size K1 */\r
+ uint8_t param_m1;\r
+\r
+ /** Sub-block interleaver parameter 'j' for codeblock of size K1 */\r
+ uint8_t param_j1;\r
+\r
+ /** Output size E1 */\r
+ uint16_t block_size_e1;\r
+\r
+ /** RM Header Word 3 */ \r
+\r
+ /** Number of code blocks C2 of size K2 */\r
+ uint8_t num_code_blocks_c2;\r
+\r
+ /** Code block size K2 */\r
+ uint16_t block_size_k2;\r
+\r
+ /** RM Header Word 4 */ \r
+\r
+ /** Sub-block interleaver parameter 'm' for codeblock of size K2 */\r
+ uint8_t param_m2;\r
+\r
+ /** Sub-block interleaver parameter 'j' for codeblock of size K2 */\r
+ uint8_t param_j2;\r
+\r
+ /** Output size E2 */\r
+ uint16_t block_size_e2;\r
+\r
+ /** RM Header Word 5 */ \r
+\r
+ /** Number of code blocks C3 of size K3 */\r
+ uint8_t num_code_blocks_c3;\r
+\r
+ /** Code block size K3 */\r
+ uint16_t block_size_k3;\r
+\r
+ /** RM Header Word 6 */ \r
+\r
+ /** Sub-block interleaver parameter 'm' for codeblock of size K3 */\r
+ uint8_t param_m3;\r
+\r
+ /** Sub-block interleaver parameter 'j' for codeblock of size K3 */\r
+ uint8_t param_j3;\r
+\r
+ /** Output size E3 */\r
+ uint16_t block_size_e3;\r
+} Bcp_RmHdr_WiMaxCfg;\r
+\r
+typedef struct _Bcp_EncBlockCfg\r
+{\r
+ /** Size of this block in bits - upto 8192 bits */ \r
+ uint16_t block_size;\r
+\r
+ /** Number of code blocks of this size block */\r
+ uint16_t num_code_blks;\r
+\r
+ /** Interleaver generator parameter\r
+ * \r
+ * WCDMA: Set to 0\r
+ * LTE: Interleaver param f1\r
+ * WIMAX: Interleaver param P0\r
+ */\r
+ uint16_t intvpar0;\r
+\r
+ /** Interleaver generator parameter\r
+ * \r
+ * WCDMA: Set to 0\r
+ * LTE: Interleaver param f2\r
+ * WIMAX: Interleaver param P1\r
+ */\r
+ uint16_t intvpar1;\r
+\r
+ /** Interleaver generator parameter\r
+ * \r
+ * WCDMA: Set to 0\r
+ * LTE: Set to 0\r
+ * WIMAX: Interleaver param P2\r
+ */\r
+ uint16_t intvpar2;\r
+\r
+ /** Interleaver generator parameter\r
+ * \r
+ * WCDMA: Set to 0\r
+ * LTE: Set to 0\r
+ * WIMAX: Interleaver param P3\r
+ */\r
+ uint16_t intvpar3;\r
+} Bcp_EncBlockCfg; \r
+\r
+/** \r
+ * @brief Bcp_EncHdrCfg\r
+ *\r
+ * Structure to specify/hold the Encoder module\r
+ * header configuration parameters.\r
+ */ \r
+typedef struct _Bcp_EncHdrCfg\r
+{ \r
+ /** ENC Header Word 0 */ \r
+\r
+ /** Local header length (Not including Header word 0). */\r
+ uint8_t local_hdr_len; \r
+\r
+ /** Specify if data needs to be turbo on convolutional\r
+ * encoded.\r
+ *\r
+ * Set to 0 for convolutional and 1 for turbo encoding\r
+ */\r
+ uint8_t turbo_conv_sel;\r
+\r
+ /** Scrambler/CRC configuration. Set to:\r
+ * 0 - Do not generate Scrambler/CRC for code blocks\r
+ * 1 - Generate scrambler/CRC-24\r
+ * 2 - Generate scrambler/CRC-16\r
+ * 3 - Generate scrambler\r
+ */\r
+ uint8_t scr_crc_en;\r
+\r
+ /** Convolutional code rate. Valid only for convolutional encoding.\r
+ *\r
+ * Set to 0 for convolutional code rate 1/3\r
+ * and 1 for convolutional code rate 1/2\r
+ */\r
+ uint8_t code_rate_flag;\r
+\r
+ /** ENC Header Word 1-9 */\r
+ Bcp_EncBlockCfg blockCfg [3];\r
+} Bcp_EncHdrCfg;\r
+\r
+/** \r
+ * @brief Bcp_ModulationMode\r
+ *\r
+ * Enumeration for specifying the Modulation\r
+ * modes.\r
+ */ \r
+typedef enum \r
+{\r
+ /** Hard modulation (uncompressed) */\r
+ Bcp_ModulationMode_HardUncompressed = 0,\r
+ /** Hard modulation (compressed) */\r
+ Bcp_ModulationMode_HardCompressed = 1,\r
+ /** Soft modulation */\r
+ Bcp_ModulationMode_Soft = 2\r
+} Bcp_ModulationMode;\r
+\r
+/** \r
+ * @brief Bcp_ModulationType\r
+ *\r
+ * Enumeration for specifying the Modulation\r
+ * types.\r
+ */ \r
+typedef enum \r
+{\r
+ /** BPSK */\r
+ Bcp_ModulationType_BPSK = 0,\r
+ /** QPSK */\r
+ Bcp_ModulationType_QPSK = 1,\r
+ /** 16 QAM */\r
+ Bcp_ModulationType_16QAM = 2,\r
+ /** 64 QAM */\r
+ Bcp_ModulationType_64QAM = 3,\r
+ /** 256 QAM */\r
+ Bcp_ModulationType_256QAM = 4,\r
+ /** 4 PAM */\r
+ Bcp_ModulationType_4PAM = 5\r
+} Bcp_ModulationType;\r
+\r
+/** \r
+ * @brief Bcp_CmuxLength\r
+ *\r
+ * Enumeration for specifying the Cmux length.\r
+ */ \r
+typedef enum \r
+{\r
+ /** 9 columns (Extended w/ SRS) */\r
+ Bcp_CmuxLength_9 = 0,\r
+ /** 10 columns (Extended w/o SRS) */\r
+ Bcp_CmuxLength_10 = 1,\r
+ /** 11 columns (Normal w/ SRS) */\r
+ Bcp_CmuxLength_11 = 2,\r
+ /** 12 columns (Normal w/o SRS) */\r
+ Bcp_CmuxLength_12 = 3\r
+} Bcp_CmuxLength;\r
+\r
+/** \r
+ * @brief Bcp_QFormat\r
+ *\r
+ * Enumeration for specifying the LLR Q Format.\r
+ */ \r
+typedef enum \r
+{\r
+ /** Q0 */\r
+ Bcp_QFormat_Q0 = 0,\r
+ /** Q1 */\r
+ Bcp_QFormat_Q1 = 1,\r
+ /** Q2 */\r
+ Bcp_QFormat_Q2 = 2,\r
+ /** Q3 */\r
+ Bcp_QFormat_Q3 = 3\r
+} Bcp_QFormat;\r
+\r
+/** \r
+ * @brief Bcp_ModHdrCfg\r
+ *\r
+ * Structure to specify/hold the Modulator module\r
+ * header configuration parameters.\r
+ */ \r
+typedef struct _Bcp_ModHdrCfg\r
+{ \r
+ /** MOD Header Word 0 */ \r
+\r
+ /** Local header length (Not including Header word 0). */\r
+ uint8_t local_hdr_len; \r
+\r
+ /** Unit value 'a' for soft and hard modulation */\r
+ uint16_t uva_val;\r
+ \r
+ /** MOD Header Word 1 */\r
+\r
+ /** Modulation mode select */\r
+ Bcp_ModulationMode sh_mod_sel;\r
+\r
+ /** Transport block 2-layer split.\r
+ *\r
+ * Valid for soft modulation mode only.\r
+ *\r
+ * Set to:\r
+ * 0 - Disable split mode\r
+ * 1 - Enable split mode\r
+ */\r
+ uint8_t split_mode_en;\r
+\r
+ /** Scrambling enable.\r
+ *\r
+ * Valid for soft and hard modulation LTE.\r
+ *\r
+ * Set to:\r
+ * 0 - Bypass scrambling\r
+ * 1 - Enable scrambling\r
+ */\r
+ uint8_t scr_en;\r
+\r
+ /** Modulation type select. */\r
+ Bcp_ModulationType mod_type_sel;\r
+\r
+ /** Cmux length select. Valid for soft modulation only */\r
+ Bcp_CmuxLength cmux_ln;\r
+\r
+ /** LLR Q format select. Valid for soft modulation only */\r
+ Bcp_QFormat q_format;\r
+\r
+ /** Index into 'B' tables of initial vectors to create 'B' matrices \r
+ *\r
+ * Valid for soft modulation only.\r
+ */\r
+ uint8_t b_table_index;\r
+\r
+ /** IQ Output reverse.\r
+ *\r
+ * Set to:\r
+ * 0 - Output Q as LSB then I\r
+ * 1 - Output I as LSB then Q\r
+ */\r
+ uint8_t jack_bit;\r
+\r
+ /** MOD Header Word 2 */\r
+\r
+ /** Cinit value for scrambling P2 sequence generator. */\r
+ uint32_t cinit_p2;\r
+\r
+ /** MOD Header Word 3 */\r
+\r
+ /** Rmux length. \r
+ *\r
+ * Valid values are (increments of 12):\r
+ * 12-1320 - Transport block in one layer \r
+ * 12-2640 - Transport block in two layers\r
+ */\r
+ uint16_t rmux_ln;\r
+\r
+ /** Number of CQI symbols to insert. */\r
+ uint16_t cqi_ln;\r
+\r
+ /** MOD Header Word 4 */\r
+\r
+ /** Number of RI symbols to insert. */\r
+ uint16_t ri_ln;\r
+\r
+ /** Number of ACK symbols to overwrite. */\r
+ uint16_t ack_ln;\r
+} Bcp_ModHdrCfg;\r
+\r
+/** \r
+ * @brief Bcp_IntDntTableCfg\r
+ *\r
+ * Structure to specify/hold the Interleaver/De-Interleaver \r
+ * table configuration.\r
+ */ \r
+typedef struct _Bcp_IntDntTableCfg\r
+{\r
+ /** Number of rows in interleaver table per frame */\r
+ uint16_t num_r2_length;\r
+\r
+ /** Number of dummy symbols per frame in last Row */\r
+ uint8_t num_dummy;\r
+\r
+ /** Input data format */\r
+ uint8_t num_data_format_in;\r
+}Bcp_IntDntTableCfg;\r
+\r
+/** \r
+ * @brief Bcp_IntHdrCfg\r
+ *\r
+ * Structure to specify/hold the Interleaver module\r
+ * header configuration parameters.\r
+ */ \r
+typedef struct _Bcp_IntHdrCfg\r
+{ \r
+ /** INT Header Word 0 */ \r
+\r
+ /** Local header length (Not including Header word 0). */\r
+ uint8_t local_hdr_len; \r
+\r
+ /** PPB configuration header */\r
+ uint8_t ppb_config_header; \r
+\r
+ /** INT Header Word 1 */\r
+\r
+ /** Constellation rearrangement format for 4/6 bit output symbol */\r
+ uint8_t num_constellation;\r
+\r
+ /** Flag to indicate if the input is coming directly from the encoder\r
+ * instead of rate matcher or CRC submodules.\r
+ */\r
+ uint8_t flag_in_order;\r
+\r
+ /** Flag to indicate if the data is 1/2 rate convolution data. */\r
+ uint8_t flag_half_rate;\r
+\r
+ /** Output data format. */\r
+ uint8_t num_data_format_out;\r
+\r
+ /** Frame count. */\r
+ uint8_t num_frame_count;\r
+\r
+ /** Number of columns in interleaver matrix. \r
+ *\r
+ * 1,2,4, or 8 selects 1st interleaving operation and refers to number of\r
+ * columns in the matrix. 30 selects 2nd interleaving operation and always\r
+ * has 30 fixed columns.\r
+ */\r
+ uint8_t num_int_ways;\r
+\r
+ /** INT header Word 2 */\r
+\r
+ /** Number of DTX to be appended to end of last frame */\r
+ uint16_t num_add_dtx;\r
+\r
+ /** INT header Words 3-8 */\r
+ Bcp_IntDntTableCfg tblCfg [6];\r
+} Bcp_IntHdrCfg;\r
+\r
+/** \r
+ * @brief Bcp_CorPuchhDespread_Sel\r
+ *\r
+ * Enumeration for specifying the packet format\r
+ * for packets being sent to the correlation engine.\r
+ */ \r
+typedef enum \r
+{\r
+ /** PUCCH */\r
+ Bcp_CorPuchhDespread_Sel_PUCHH = 0,\r
+ /** De-spreading */\r
+ Bcp_CorPucchDespread_Sel_DESPREAD = 1\r
+} Bcp_CorPuchhDespread_Sel;\r
+\r
+/** \r
+ * @brief Bcp_CorDespread_Cplx\r
+ *\r
+ * Enumeration for specifying the De-spreading\r
+ * input format.\r
+ */ \r
+typedef enum \r
+{\r
+ /** Inputs are 16-bit real numbers */\r
+ Bcp_CorDespread_Cplx_16REAL = 0,\r
+ /** Inputs are 32-bit complex numbers */\r
+ Bcp_CorDespread_Cplx_32COMPLEX = 1\r
+}Bcp_CorDespread_Cplx;\r
+\r
+/** \r
+ * @brief Bcp_CorBlockParams\r
+ *\r
+ * Structure to specify the correlation parameters \r
+ * for each physical block.\r
+ */ \r
+typedef struct _Bcp_CorBlockParams\r
+{ \r
+ /** Number of samples given for de-spreading. Largest possible\r
+ * for is 2^16 = 65,536 samples.\r
+ */\r
+ uint16_t despreading_length;\r
+\r
+ /** De-spreading ratio. */\r
+ uint8_t sf_ratio;\r
+} Bcp_CorBlockParams;\r
+\r
+/** \r
+ * @brief Bcp_CorHdrCfg\r
+ *\r
+ * Structure to specify/hold the Correlation engine\r
+ * header configuration parameters.\r
+ */ \r
+typedef struct _Bcp_CorHdrCfg\r
+{ \r
+ /** COR Header Word 0 */ \r
+\r
+ /** Local header length (Not including Header word 0). */\r
+ uint8_t local_hdr_len; \r
+\r
+ /** Mode flag to select between Pucch correlation packet\r
+ * or De-spreading packet.\r
+ */\r
+ Bcp_CorPuchhDespread_Sel pucch_despread_sel;\r
+\r
+ /** Indicates if de-spreading inputs are 16-bit real or 32-bit\r
+ * complex numbers.\r
+ */\r
+ Bcp_CorDespread_Cplx despread_flag_cplx;\r
+ \r
+ /** COR Header Word 1 */\r
+\r
+ /** Number of user bits. */\r
+ uint8_t pucch_a;\r
+\r
+ /** Scrambling code. */\r
+ uint32_t pucch_scr_seq;\r
+\r
+ /** Number of Antennas */\r
+ uint8_t pucch_nr;\r
+\r
+ /** Operational mode. */\r
+ uint8_t pucch_mode;\r
+\r
+ /** COR Header Word 2-7 */\r
+\r
+ /** Correlation parameters for each physical block */\r
+ Bcp_CorBlockParams block_params [6];\r
+} Bcp_CorHdrCfg;\r
+\r
+/** \r
+ * @brief Bcp_SslFddTdd_Sel\r
+ *\r
+ * Enumeration for specifying FDD/TDD format\r
+ * to Soft Slicer engine.\r
+ */ \r
+typedef enum \r
+{\r
+ /** FDD */\r
+ Bcp_SslFddTdd_Sel_FDD = 0,\r
+ /** TDD */\r
+ Bcp_SslFddTdd_Sel_TDD = 1\r
+}Bcp_SslFddTdd_Sel;\r
+\r
+/** \r
+ * @brief Bcp_Tti_Sel\r
+ *\r
+ * Enumeration for specifying TTI length.\r
+ */ \r
+typedef enum \r
+{\r
+ /** 2ms TTI */\r
+ Bcp_Tti_Sel_2ms = 0,\r
+ /** 10ms TTI */\r
+ Bcp_Tti_Sel_10ms = 1\r
+}Bcp_Tti_Sel;\r
+\r
+/** \r
+ * @brief Bcp_SslHdr_ModeSelCfg\r
+ *\r
+ * Structure to specify/hold the Soft Slicer (SSL) \r
+ * engine header's mode selection configuration \r
+ * parameters. \r
+ */ \r
+typedef struct _Bcp_SslHdr_ModeSelCfg\r
+{ \r
+ /** SSL Header Word 1 */\r
+\r
+ /** Mode flag to select FDD/TDD. */\r
+ Bcp_SslFddTdd_Sel fdd_tdd_sel;\r
+\r
+ /** Transport block 2-layer split \r
+ * \r
+ * Set to:\r
+ * 0 - Split mode disabled\r
+ * 1 - Split mode enabled\r
+ */\r
+ uint8_t split_mode_en;\r
+\r
+ /** IQ Output reverse.\r
+ *\r
+ * Set to:\r
+ * 0 - Output Q as LSB then I\r
+ * 1 - Output I as LSB then Q\r
+ */\r
+ uint8_t jack_bit;\r
+\r
+ /** LTE descrambling enable.\r
+ *\r
+ * Set to:\r
+ * 0 - Descrambling bypassed\r
+ * 1 - Descrambling enabled\r
+ */\r
+ uint8_t lte_descrambler_en;\r
+\r
+ /** Modulation type select */\r
+ Bcp_ModulationType mod_type_sel;\r
+\r
+ /** WCDMA output from SSL slot packing mode.\r
+ *\r
+ * Set to:\r
+ * 0 - slots aligned on 128 bit boundaries\r
+ * 1 - slots not aligned on 128 bit boundaries, i.e., packed\r
+ */\r
+ uint8_t tdd_output_pack;\r
+\r
+ /** Cmux length select. Valid for soft modulation only */\r
+ Bcp_CmuxLength cmux_ln;\r
+\r
+ /** LLR Q format select. Valid for soft modulation only */\r
+ Bcp_QFormat q_format;\r
+\r
+ /** Index into 'B' tables of initial vectors to create 'B' matrices */\r
+ uint8_t b_matrix_sel;\r
+\r
+ /** TTI selection. Valid only for WCDMA(FDD) only. */\r
+ Bcp_Tti_Sel tti_2ms_10ms_sel;\r
+\r
+ /** Number of WCMDA (TD-SCDMA) slots. */\r
+ uint8_t wcdma_num_slots;\r
+\r
+ /** Number of physical channels for WCDMA (FDD) */\r
+ uint8_t wcmda_num_phy_ch;\r
+\r
+ /** Rmux length index. \r
+ *\r
+ * Index into rmux length tables. Valid for LTE only.\r
+ */\r
+ uint16_t rmux_ln_index; \r
+\r
+} Bcp_SslHdr_ModeSelCfg;\r
+\r
+/** \r
+ * @brief Bcp_SslHdr_LteCfg\r
+ *\r
+ * Structure to specify/hold the Soft Slicer (SSL) \r
+ * engine configuration for LTE packets. \r
+ */ \r
+typedef struct _Bcp_SslHdr_LteCfg\r
+{\r
+ /** SSL Header Word 0 */ \r
+\r
+ /** Local header length (Not including Header word 0). */\r
+ uint8_t local_hdr_len; \r
+\r
+ /** Soft slicer Unit Value.\r
+ *\r
+ * Valid values are:\r
+ * 2-PAM: 0-16383 (QPSK & BPSK)\r
+ * 4-PAM: 0-10922 (16 QAM & 4-PAM)\r
+ * 6-PAM: 0-4681 (64 QAM)\r
+ * 8-PAM: 0-2184 (256 QAM)\r
+ */\r
+ uint16_t uva;\r
+\r
+ /** SSL Header Word 1 */ \r
+\r
+ /** SSL Header Mode selection Configuration */ \r
+ Bcp_SslHdr_ModeSelCfg modeSelCfg; \r
+\r
+ /** SSL Header Word 2 */ \r
+\r
+ /** Number of RI LLRs of Qw soft bits to puncture \r
+ *\r
+ * Valid values are:\r
+ * 0-5184: Normal mode\r
+ * 0-10368: Split mode \r
+ */\r
+ uint16_t ri_ln;\r
+\r
+ /** Number of ACK LLRs of Qw soft bits to overwrite \r
+ *\r
+ * Valid values are:\r
+ * 0-5184: Normal mode\r
+ * 0-10368: Split mode \r
+ */\r
+ uint16_t ack_ln;\r
+\r
+ /** SSL Header Word 3 */ \r
+\r
+ /** Cinit value for descrambler P2 sequence generator. */\r
+ uint32_t cinit_p2;\r
+\r
+ /** SSL Header Word 4-15 */ \r
+\r
+ /** Noise scaling factor for Column 'n' in LTE single layer mode\r
+ * if cmux_ln=12 or Column '0,n' in LTE split mode if cmux_ln=12\r
+ */\r
+ uint32_t scale_c0[12];\r
+\r
+ /** SSL Header Word 16-27 */ \r
+\r
+ /** Noise scaling factor for Column '1,n' in LTE split mode if cmux_ln=12 \r
+ *\r
+ * Valid for LTE split mode only.\r
+ */\r
+ uint32_t scale_c1[12];\r
+} Bcp_SslHdr_LteCfg;\r
+\r
+/** \r
+ * @brief Bcp_SslHdr_WcdmaFddCfg\r
+ *\r
+ * Structure to specify/hold the Soft Slicer (SSL) \r
+ * engine configuration for WCDMA FDD packets. \r
+ */ \r
+typedef struct _Bcp_SslHdr_WcdmaFddCfg\r
+{\r
+ /** SSL Header Word 0 */ \r
+\r
+ /** Local header length (Not including Header word 0). */\r
+ uint8_t local_hdr_len; \r
+\r
+ /** WCDMA (FDD) Number of symbols per segment */\r
+ uint16_t wcdma_symb_seq;\r
+\r
+ /** SSL Header Word 1 */ \r
+\r
+ /** SSL Header Mode selection Configuration */ \r
+ Bcp_SslHdr_ModeSelCfg modeSelCfg; \r
+\r
+ /** SSL Header Word 2-20 */ \r
+\r
+ /** Soft slicer Unit Value.\r
+ *\r
+ * Valid values are:\r
+ * 2-PAM: 0-16383 (QPSK & BPSK)\r
+ * 4-PAM: 0-10922 (16 QAM & 4-PAM)\r
+ */\r
+ uint16_t uva [12];\r
+\r
+ /** Noise scaling factor for Segment 'n' in WCDMA FDD */\r
+ uint32_t scale_c0[12];\r
+} Bcp_SslHdr_WcdmaFddCfg;\r
+\r
+/** \r
+ * @brief Bcp_SslHdr_WcdmaTdScdmaCfg\r
+ *\r
+ * Structure to specify/hold the Soft Slicer (SSL) \r
+ * engine configuration for WCDMA TD-SCDMA packets. \r
+ */ \r
+typedef struct _Bcp_SslHdr_WcdmaTdScdmaCfg\r
+{\r
+ /** SSL Header Word 0 */ \r
+\r
+ /** Local header length (Not including Header word 0). */\r
+ uint8_t local_hdr_len; \r
+\r
+ /** SSL Header Word 1 */ \r
+\r
+ /** SSL Header Mode selection Configuration */ \r
+ Bcp_SslHdr_ModeSelCfg modeSelCfg; \r
+\r
+ /** SSL Header Word 2-13 */ \r
+\r
+ /** Soft slicer Unit Value.\r
+ *\r
+ * Valid values are:\r
+ * 2-PAM: 0-16383 (QPSK & BPSK)\r
+ * 4-PAM: 0-10922 (16 QAM & 4-PAM)\r
+ * 6-PAM: 0-4681 (64 QAM)\r
+ */\r
+ uint16_t uva [6];\r
+\r
+ /** Number of symbols for slot 'n' */ \r
+ uint16_t wcdma_size_slot [6]; \r
+\r
+ /** Noise scaling factor for Slot 'n' in WCDMA TD-SCDMA */\r
+ uint32_t scale_c0[6];\r
+} Bcp_SslHdr_WcdmaTdScdmaCfg;\r
+\r
+\r
+/** \r
+ * @brief Bcp_SslHdr_WiMaxCfg\r
+ *\r
+ * Structure to specify/hold the Soft Slicer (SSL) \r
+ * engine configuration for WiMax packets. \r
+ */ \r
+typedef struct _Bcp_SslHdr_WiMaxCfg\r
+{\r
+ /** SSL Header Word 0 */ \r
+\r
+ /** Local header length (Not including Header word 0). */\r
+ uint8_t local_hdr_len; \r
+\r
+ /** Rmux length. \r
+ *\r
+ * Valid values are (increments of 12):\r
+ * 12-1320 - Transport block in one layer \r
+ * 12-2640 - Transport block in two layers\r
+ */\r
+ uint16_t rmux_ln;\r
+\r
+ /** Soft slicer Unit Value.\r
+ *\r
+ * Valid values are:\r
+ * 2-PAM: 0-16383 (QPSK & BPSK)\r
+ * 4-PAM: 0-10922 (16 QAM & 4-PAM)\r
+ * 6-PAM: 0-4681 (64 QAM)\r
+ * 8-PAM: 0-2184 (256 QAM)\r
+ */\r
+ uint16_t uva;\r
+\r
+ /** SSL Header Word 1 */ \r
+\r
+ /** SSL Header Mode selection Configuration */ \r
+ Bcp_SslHdr_ModeSelCfg modeSelCfg; \r
+} Bcp_SslHdr_WiMaxCfg;\r
+\r
+\r
+/** \r
+ * @brief Bcp_DntHdrCfg\r
+ *\r
+ * Structure to specify/hold the De-interleaver (DNT) \r
+ * engine configuration. \r
+ */ \r
+typedef struct _Bcp_DntHdrCfg\r
+{\r
+ /** DNT Header Word 0 */ \r
+\r
+ /** Local header length (Not including Header word 0). */\r
+ uint8_t local_hdr_len; \r
+\r
+ /** PPB configuration header */\r
+ uint8_t ppb_config_header; \r
+\r
+ /** DNT Header Word 1 */ \r
+\r
+ /** Constellation re-arrangement for 16QAM. Valid values are 0-3 */\r
+ uint8_t num_constellation;\r
+\r
+ uint8_t num_frame_count;\r
+\r
+ /** Descrambler generator initialization value */\r
+ uint16_t num_descramble;\r
+\r
+ /** DNT Header Word 2 */ \r
+\r
+ /** Number of symbols per packet. */\r
+ uint32_t num_data_value;\r
+\r
+ /** DNT Header Word 3-8 */ \r
+ Bcp_IntDntTableCfg tblCfg[6];\r
+} Bcp_DntHdrCfg;\r
+\r
+/** \r
+ * @brief Bcp_RdHdr_LteCfg\r
+ *\r
+ * Structure to specify/hold the Rate Dematcher (RD) \r
+ * engine configuration for LTE packets.\r
+ */ \r
+typedef struct _Bcp_RdHdr_LteCfg\r
+{\r
+ /** RD Header Word 0 */ \r
+\r
+ /** Local header length (Not including Header word 0). */\r
+ uint8_t local_hdr_len; \r
+\r
+ /** Enable HARQ input flag. \r
+ *\r
+ * Set to:\r
+ * 0 - To indicate to engine not to use history data in \r
+ * LLR combining\r
+ * 1 - To indicate to engine to use history data\r
+ */\r
+ uint8_t enable_harq_input;\r
+\r
+ /** Enable HARQ output flag.\r
+ * \r
+ * Set to:\r
+ * 0 - To indicate to engine not to write back updated history \r
+ * data.\r
+ * 1 - To indicate to engine to write back whole TB history data. \r
+ */\r
+ uint8_t enable_harq_output;\r
+\r
+ /** Unsigned scale factor in Q4 format. */\r
+ uint8_t tcp3d_scale_factor;\r
+\r
+ /** Turbo decoder LLR range \r
+ *\r
+ * Set to:\r
+ * 0 - LLRs towards turbo decoder are in range +/-31\r
+ * 1 - LLRs towards turbo decoder are in range +/-127\r
+ */\r
+ uint8_t tcp3d_dyn_range;\r
+\r
+ /** RD Header Word 1 */ \r
+\r
+ /** Control data flag.\r
+ * \r
+ * Set to:\r
+ * 0 - for CQI bits to be rate dematched\r
+ * 1 - for bypassing rate dematching of CQI data\r
+ */\r
+ uint8_t cqi_pass_through;\r
+\r
+ /** Starting column in the writing phase to dual matrix. */\r
+ uint8_t rv_start_column;\r
+\r
+ /** Number of filler bits F in the first code block. */\r
+ uint8_t num_filler_bits_f;\r
+\r
+ /** Starting value for flow Id counter. */\r
+ uint8_t init_cb_flowId;\r
+\r
+ /** Max value for flow Id counter */\r
+ uint8_t flowId_hi;\r
+\r
+ /** Offset for CQI CB only. */\r
+ uint8_t flowId_cqi_offset;\r
+\r
+ /** RD Header word 2 */\r
+\r
+ /** Number of code blocks C1 of size K1 */\r
+ uint8_t num_code_blocks_c1;\r
+\r
+ /** Number of code blocks Ce1 of transmitted size E1 */\r
+ uint8_t num_code_blocks_ce1;\r
+\r
+ /** Number of code blocks C2 of size K2 */\r
+ uint8_t num_code_blocks_c2;\r
+\r
+ /** Number of code blocks Ce2 with transmitted size E2 */\r
+ uint8_t num_code_blocks_ce2;\r
+\r
+ /** RD Header word 3 */\r
+\r
+ /** Code block size K1 */\r
+ uint16_t block_size_k1;\r
+\r
+ /** Transmitted size E1 */\r
+ uint16_t block_size_e1;\r
+\r
+ /** RD Header word 4 */\r
+\r
+ /** Code block size K2 */\r
+ uint16_t block_size_k2;\r
+\r
+ /** Transmitted size E2 */\r
+ uint16_t block_size_e2;\r
+\r
+ /** RD Header word 5 */\r
+\r
+ /** Payload size of CQI data */\r
+ uint16_t block_size_outq_cqi;\r
+\r
+ /** Transmitted size of CQI data */\r
+ uint16_t block_size_inq_cqi;\r
+\r
+ /** RD Header word 6 */\r
+\r
+ /** Address of HARQ input data */\r
+ uint32_t harq_input_address;\r
+\r
+ /** RD Header word 7 */\r
+\r
+ /** Address of HARQ output data */\r
+ uint32_t harq_output_address;\r
+} Bcp_RdHdr_LteCfg;\r
+\r
+/** \r
+ * @brief Bcp_RdHdr_ChannelCfg\r
+ *\r
+ * Structure to specify/hold the WCDMA/TD-SCDMA \r
+ * Rate De-modulation (RD) Header Channel configuration \r
+ * parameters.\r
+ */ \r
+typedef struct _Bcp_RdHdr_ChannelCfg\r
+{\r
+ /** Channel 'n' length after rate de-matching */\r
+ uint16_t sys_len;\r
+\r
+ /** Channel 'n' initial value for rate de-matching */\r
+ uint16_t sys_init2;\r
+\r
+ /** Channel 'n' minus value for rate de-matching */\r
+ uint16_t sys_minus2;\r
+\r
+ /** Channel 'n' plus value for rate de-matching */\r
+ uint16_t sys_plus2;\r
+\r
+ /** Channel 'n' TD-SCDMA alpha value for bit separation */\r
+ uint8_t sys_aplha;\r
+\r
+ /** Channel 'n' TD-SCDMA beta value for bit separation */\r
+ uint8_t sys_beta;\r
+\r
+ /** Puncture flag \r
+ *\r
+ * Set to:\r
+ * 0 - Perform un-repeat during rate de-matching\r
+ * 1 - Perform un-puncture during rate de-matching\r
+ */\r
+ uint8_t sys_puncture;\r
+\r
+ /** Channel type.\r
+ *\r
+ * Set to:\r
+ * 0 - Convolutional or Rel-99 Turbo Repeat\r
+ * 1 - Rel-99 style Turbo puncture, use p0 parity params\r
+ * 2 - Rel-99 style Turbo puncture, use p1 parity params\r
+ */\r
+ uint8_t sys_turbo;\r
+}Bcp_RdHdr_ChannelCfg;\r
+\r
+\r
+/** \r
+ * @brief Bcp_RdHdr_xCdmaCfg\r
+ *\r
+ * Structure to specify/hold the Rate Dematcher (RD) \r
+ * engine configuration for WCDMA and TD-SCDMA packets.\r
+ */ \r
+typedef struct _Bcp_RdHdr_xCdmaCfg\r
+{\r
+ /** RD Header Word 0 */ \r
+\r
+ /** Local header length (Not including Header word 0). \r
+ *\r
+ * Possible values are 41 for Long header format and 22\r
+ * for short header format.\r
+ */\r
+ uint8_t local_hdr_len; \r
+\r
+ /** Un-collection method for HSUPA channels\r
+ *\r
+ * Set to:\r
+ * 0 - Perform HSPA un-collection.\r
+ * 1 - Perform Rel-99 un-collection.\r
+ */\r
+ uint8_t fdd;\r
+\r
+ /** Enable history data for LLR combining\r
+ *\r
+ * Set to:\r
+ * 0 - Do not use history data.\r
+ * 1 - Use history data.\r
+ */\r
+ uint8_t en_harq_in;\r
+\r
+ /** Enable storing of history data for future LLR combining\r
+ *\r
+ * Set to:\r
+ * 0 - Do not store history data.\r
+ * 1 - Store history data.\r
+ */\r
+ uint8_t en_harq_out;\r
+\r
+ /** Turbo decoder LLR range \r
+ *\r
+ * Set to:\r
+ * 0 - LLRs towards turbo decoder are in range +/-31\r
+ * 1 - LLRs towards turbo decoder are in range +/-127\r
+ */\r
+ uint8_t tcp3d_dyn_range;\r
+\r
+ /** Scale factor that determines how 6 bits of LLR data are \r
+ * extracted from 8 HARQ bits for sending to TCP3d.\r
+ */\r
+ uint8_t tcp3d_scale_factor;\r
+\r
+ /** RD Header Word 1 */\r
+\r
+ /** Collect columns - Number of columns in bit collection table. */\r
+ uint32_t collect_cols;\r
+\r
+ /** Collect rows - Number of rows in bit collection table. */\r
+ uint8_t collect_rows;\r
+\r
+ /** RD Header Word 2 */\r
+ \r
+ /** Length of each turbo code block (after rate de-matching) including\r
+ * tail bits.\r
+ */\r
+ uint16_t turbo_length;\r
+\r
+ /** Number of turbo code blocks to output */\r
+ uint8_t turbo_count;\r
+\r
+ /** Starting value of CB flow Id counter */\r
+ uint8_t flow_id_init;\r
+\r
+ /** Maximum value of CB Flow id counter */\r
+ uint8_t flow_id_max;\r
+\r
+ /** RD Header Word 3 */\r
+ /** Starting address of HARQ history data input */\r
+ uint32_t harq_in_addr;\r
+\r
+ /** RD Header Word 4 */\r
+ /** Starting address of HARQ history data output */\r
+ uint32_t harq_out_addr;\r
+\r
+ /** RD Header Word 5 */\r
+ /** Channel 0 length after rate de-matching. */\r
+ uint32_t sys0_len;\r
+\r
+ /** RD Header Word 6 */\r
+ /** Channel 0 initial value for 2nd rate matching loop and rate de-matching . */\r
+ uint32_t sys0_init2;\r
+\r
+ /** RDD Header Word 7 */\r
+ /** Channel 0 minus value for 2nd rate matching loop and rate de-matching. */\r
+ uint32_t sys0_minus2;\r
+\r
+ /** RD Header Word 8 */\r
+ /** Channel 0 plus value for 2nd rate matching loop and rate de-matching. */\r
+ uint32_t sys0_plus2;\r
+\r
+ /** Channel 0 TD-SDCDMA aplha value for bit separation. */\r
+ uint8_t sys0_alpha;\r
+\r
+ /** Channel 0 TD-SDCDMA beta value for bit separation. */\r
+ uint8_t sys0_beta;\r
+\r
+ /** Channel 0 Puncture flag \r
+ *\r
+ * Set to:\r
+ * 0 - Perform un-repeat during rate de-matching\r
+ * 1 - Perform un-puncture during rate de-matching\r
+ */\r
+ uint8_t sys0_puncture;\r
+\r
+ /** Channel type.\r
+ *\r
+ * Set to:\r
+ * 0 - Convolutional or Rel-99 Turbo Repeat\r
+ * 1 - Rel-99 style Turbo puncture, use p0 parity params\r
+ * 2 - Rel-99 style Turbo puncture, use p1 parity params\r
+ * 3 - HSUPA style turbo channel, use p0 params.\r
+ */\r
+ uint8_t sys0_turbo;\r
+\r
+ /** RD Header Word 9 */\r
+ /** P0 Parity1 length after rate de-matching */\r
+ uint32_t p0_par1_len;\r
+\r
+ /** RD Header Word 10 */\r
+ /** P0 Parity1 initial value for 1st rate matching loop */\r
+ uint32_t p0_par1_init1;\r
+\r
+ /** RD Header Word 11 */\r
+ /** P0 Parity1 minus value for 1st rate matching loop */\r
+ uint32_t p0_par1_minus1;\r
+\r
+ /** RD Header Word 12 */\r
+ /** P0 Parity1 plus value for 1st rate matching loop */\r
+ uint32_t p0_par1_plus1;\r
+\r
+ /** RD Header Word 13 */\r
+ /** P0 Parity1 initial value for 2nd rate matching loop and rate de-matching */\r
+ uint32_t p0_par1_init2;\r
+\r
+ /** RD Header Word 14 */\r
+ /** P0 Parity1 minus value for 2nd rate matching loop and rate de-matching */\r
+ uint32_t p0_par1_minus2;\r
+\r
+ /** RD Header Word 15 */\r
+ /** P0 Parity1 plus value for 2nd rate matching loop and rate de-matching */\r
+ uint32_t p0_par1_plus2;\r
+\r
+ /** RD Header Word 16 */\r
+ /** P0 Parity2 length after rate de-matching */\r
+ uint32_t p0_par2_len;\r
+\r
+ /** RD Header Word 17 */\r
+ /** P0 Parity2 initial value for 1st rate matching loop */\r
+ uint32_t p0_par2_init1;\r
+\r
+ /** RD Header Word 18 */\r
+ /** P0 Parity2 minus value for 1st rate matching loop */\r
+ uint32_t p0_par2_minus1;\r
+\r
+ /** RD Header Word 19 */\r
+ /** P0 Parity2 plus value for 1st rate matching loop */\r
+ uint32_t p0_par2_plus1;\r
+\r
+ /** RD Header Word 20 */\r
+ /** P0 Parity2 initial value for 2nd rate matching loop and rate de-matching */\r
+ uint32_t p0_par2_init2;\r
+\r
+ /** RD Header Word 21 */\r
+ /** P0 Parity2 minus value for 2nd rate matching loop and rate de-matching */\r
+ uint32_t p0_par2_minus2;\r
+\r
+ /** RD Header Word 22 */\r
+ /** P0 Parity2 plus value for 2nd rate matching loop and rate de-matching */\r
+ uint32_t p0_par2_plus2;\r
+\r
+ /** RD Header Words 23-37 */\r
+ Bcp_RdHdr_ChannelCfg channelCfg[5];\r
+\r
+ /** RD Header Word 38 */\r
+ /** p1 Parity1 length after rate de-matching */\r
+ uint16_t p1_par1_len;\r
+\r
+ /** p1 Parity1 initial value for 2nd rate matching loop and rate de-matching */\r
+ uint16_t p1_par1_init2;\r
+\r
+ /** RD Header Word 39 */\r
+ /** p1 Parity1 minus value for 2nd rate matching loop and rate de-matching */\r
+ uint16_t p1_par1_minus2;\r
+\r
+ /** p1 Parity1 plus value for 2nd rate matching loop and rate de-matching */\r
+ uint16_t p1_par1_plus2;\r
+\r
+ /** RM Header Word 40 */\r
+ /** p1 Parity2 length after rate de-matching */\r
+ uint16_t p1_par2_len;\r
+\r
+ /** p1 Parity2 initial value for 2nd rate matching loop and rate de-matching */\r
+ uint16_t p1_par2_init2;\r
+\r
+ /** RM Header Word 41 */\r
+ /** p1 Parity2 minus value for 2nd rate matching loop and rate de-matching */\r
+ uint16_t p1_par2_minus2;\r
+\r
+ /** p1 Parity2 plus value for 2nd rate matching loop and rate de-matching */\r
+ uint16_t p1_par2_plus2;\r
+} Bcp_RdHdr_xCdmaCfg;\r
+\r
+/** \r
+ * @brief Bcp_RdHdr_WiMaxCfg\r
+ *\r
+ * Structure to specify/hold the Rate Dematcher (RD) \r
+ * engine configuration for WiMax packets.\r
+ */ \r
+typedef struct _Bcp_RdHdr_WiMaxCfg\r
+{\r
+ /** RD Header Word 0 */ \r
+\r
+ /** Local header length (Not including Header word 0). */\r
+ uint8_t local_hdr_len; \r
+\r
+ /** Enable HARQ input flag. \r
+ *\r
+ * Set to:\r
+ * 0 - To indicate to engine not to use history data in \r
+ * LLR combining\r
+ * 1 - To indicate to engine to use history data\r
+ */\r
+ uint8_t enable_harq_input;\r
+\r
+ /** Enable HARQ output flag.\r
+ * \r
+ * Set to:\r
+ * 0 - To indicate to engine not to write back updated history \r
+ * data.\r
+ * 1 - To indicate to engine to write back whole TB history data. \r
+ */\r
+ uint8_t enable_harq_output;\r
+\r
+ /** Turbo decoder LLR range \r
+ *\r
+ * Set to:\r
+ * 0 - LLRs towards turbo decoder are in range +/-31\r
+ * 1 - LLRs towards turbo decoder are in range +/-127\r
+ */\r
+ uint8_t tcp3d_dyn_range;\r
+\r
+ /** Unsigned scale factor in Q4 format. */\r
+ uint8_t tcp3d_scale_factor;\r
+\r
+ /** RD Header Word 1 */ \r
+\r
+ /** Number of code blocks C1 of size K1 */\r
+ uint8_t num_code_blocks_c1;\r
+\r
+ /** Starting value for flow Id Offset value. */\r
+ uint8_t flowId_starting_offset;\r
+\r
+ /** Flow Id ending offset */\r
+ uint8_t flowId_ending_offset;\r
+\r
+ /** Code block size K1 */\r
+ uint16_t block_size_k1;\r
+\r
+ /** RD Header Word 2 */ \r
+\r
+ /** Sub-block interleaver parameter 'm' for CBs of size K1 */\r
+ uint8_t param_m1;\r
+\r
+ /** Sub-block interleaver parameter 'j' for CBs of size K1 */\r
+ uint8_t param_j1;\r
+\r
+ /** Transmitted size E1 */\r
+ uint16_t block_size_e1;\r
+\r
+ /** RD Header Word 3 */ \r
+\r
+ /** Number of code blocks C2 of size K2 */\r
+ uint8_t num_code_blocks_c2;\r
+\r
+ /** Code block size K2 */\r
+ uint16_t block_size_k2;\r
+\r
+ /** RD Header Word 4 */ \r
+\r
+ /** Sub-block interleaver parameter 'm' for CBs of size K2 */\r
+ uint8_t param_m2;\r
+\r
+ /** Sub-block interleaver parameter 'j' for CBs of size K2 */\r
+ uint8_t param_j2;\r
+\r
+ /** Transmitted size E2 */\r
+ uint16_t block_size_e2;\r
+\r
+ /** RD Header Word 5 */ \r
+\r
+ /** Number of code blocks C3 of size K3 */\r
+ uint8_t num_code_blocks_c3;\r
+\r
+ /** Code block size K3 */\r
+ uint16_t block_size_k3;\r
+\r
+ /** RD Header Word 6 */ \r
+\r
+ /** Sub-block interleaver parameter 'm' for CBs of size K3 */\r
+ uint8_t param_m3;\r
+\r
+ /** Sub-block interleaver parameter 'j' for CBs of size K3 */\r
+ uint8_t param_j3;\r
+\r
+ /** Transmitted size E3 */\r
+ uint16_t block_size_e3;\r
+\r
+ /** RD Header word 7 */\r
+\r
+ /** Address of HARQ input data */\r
+ uint32_t harq_input_address;\r
+\r
+ /** RD Header word 8 */\r
+\r
+ /** Address of HARQ output data */\r
+ uint32_t harq_output_address;\r
+} Bcp_RdHdr_WiMaxCfg;\r
+\r
+/** \r
+ * @brief Bcp_DioDmaBlkCfg\r
+ *\r
+ * Structure to specify the BCP DIO DMA\r
+ * block operation parameters.\r
+ */ \r
+typedef struct _Bcp_DioDmaBlkCfg\r
+{\r
+ /** Address of the DMA block. Must be aligned on 16 byte boundary */\r
+ uint32_t dio_addr;\r
+\r
+ /** Number of bytes to access. Must be a multiple of 16 bytes */\r
+ uint32_t dio_cnt;\r
+} Bcp_DioDmaBlkCfg;\r
+\r
+/** \r
+ * @brief Bcp_DioHdrCfg\r
+ *\r
+ * Structure to specify the BCP Direct Input-Output (DIO)\r
+ * header configuration parameters.\r
+ */ \r
+typedef struct _Bcp_DioHdrCfg\r
+{\r
+ /** DIO Header Word 0 */ \r
+\r
+ /** Local header length (Not including Header word 0). */\r
+ uint8_t local_hdr_len; \r
+ \r
+ /** Endian swap control */ \r
+ Bcp_EndianFormat dio_endian;\r
+\r
+ /** Read/Write control. Set to 1 for Read operation, 0 otherwise */\r
+ uint8_t dio_rd_wr;\r
+\r
+ /** Number of DMA blocks for the operation */\r
+ uint8_t dio_blk_cnt;\r
+\r
+ /** DIO Header Words 1-12 */ \r
+\r
+ /** DIO DMA block configuration. */\r
+ Bcp_DioDmaBlkCfg dio_dmablk_cfg [6];\r
+} Bcp_DioHdrCfg;\r
+\r
+\r
+/**\r
+@}\r
+*/\r
+\r
+extern int32_t Bcp_addGlobalHeader (\r
+ Bcp_GlobalHdrCfg* pBcpGlobalHdrCfg, \r
+ uint8_t* pData,\r
+ uint32_t* pLen\r
+);\r
+\r
+extern int32_t Bcp_addTMHeader (\r
+ Bcp_TmHdrCfg* pTmHdrCfg, \r
+ uint8_t* pData,\r
+ uint32_t* pLen\r
+);\r
+\r
+extern int32_t Bcp_addCRCHeader (\r
+ Bcp_CrcHdrCfg* pCrcHdrCfg, \r
+ uint8_t* pData,\r
+ uint32_t* pLen\r
+);\r
+\r
+extern int32_t Bcp_addxCdma_RMHeader (\r
+ Bcp_RmHdr_xCdmaCfg* pRmHdrCfg, \r
+ uint8_t* pData,\r
+ uint32_t* pLen\r
+);\r
+\r
+extern int32_t Bcp_addLte_RMHeader (\r
+ Bcp_RmHdr_LteCfg* pRmHdrCfg, \r
+ uint8_t* pData,\r
+ uint32_t* pLen\r
+);\r
+\r
+extern int32_t Bcp_addWiMax_RMHeader (\r
+ Bcp_RmHdr_WiMaxCfg* pRmHdrCfg, \r
+ uint8_t* pData,\r
+ uint32_t* pLen\r
+);\r
+\r
+extern int32_t Bcp_addEncoderHeader (\r
+ Bcp_EncHdrCfg* pEncHdrCfg, \r
+ uint8_t* pData,\r
+ uint32_t* pLen\r
+);\r
+\r
+extern int32_t Bcp_addModulatorHeader (\r
+ Bcp_ModHdrCfg* pModHdrCfg, \r
+ uint8_t* pData,\r
+ uint32_t* pLen\r
+);\r
+ \r
+extern int32_t Bcp_addInterleaverHeader (\r
+ Bcp_IntHdrCfg* pIntHdrCfg, \r
+ uint8_t* pData,\r
+ uint32_t* pLen\r
+);\r
+\r
+extern int32_t Bcp_addCorrelationHeader (\r
+ Bcp_CorHdrCfg* pCorHdrCfg, \r
+ uint8_t* pData,\r
+ uint32_t* pLen\r
+);\r
+\r
+extern int32_t Bcp_addLTE_SSLHeader (\r
+ Bcp_SslHdr_LteCfg* pSslHdrCfg, \r
+ uint8_t* pData,\r
+ uint32_t* pLen\r
+);\r
+\r
+extern int32_t Bcp_addWCDMAFDD_SSLHeader (\r
+ Bcp_SslHdr_WcdmaFddCfg* pSslHdrCfg, \r
+ uint8_t* pData,\r
+ uint32_t* pLen\r
+);\r
+\r
+extern int32_t Bcp_addWCDMATDSCDMA_SSLHeader (\r
+ Bcp_SslHdr_WcdmaTdScdmaCfg* pSslHdrCfg, \r
+ uint8_t* pData,\r
+ uint32_t* pLen\r
+);\r
+\r
+extern int32_t Bcp_addWiMax_SSLHeader (\r
+ Bcp_SslHdr_WiMaxCfg* pSslHdrCfg, \r
+ uint8_t* pData,\r
+ uint32_t* pLen\r
+);\r
+\r
+extern int32_t Bcp_addDeinterleaverHeader (\r
+ Bcp_DntHdrCfg* pDntHdrCfg, \r
+ uint8_t* pData,\r
+ uint32_t* pLen\r
+);\r
+\r
+extern int32_t Bcp_addLTE_RDHeader (\r
+ Bcp_RdHdr_LteCfg* pRdHdrCfg, \r
+ uint8_t* pData,\r
+ uint32_t* pLen\r
+);\r
+\r
+extern int32_t Bcp_addxCdma_RDHeader (\r
+ Bcp_RdHdr_xCdmaCfg* pRdHdrCfg, \r
+ uint8_t* pData,\r
+ uint32_t* pLen\r
+);\r
+\r
+extern int32_t Bcp_addWiMax_RDHeader (\r
+ Bcp_RdHdr_WiMaxCfg* pRdHdrCfg, \r
+ uint8_t* pData,\r
+ uint32_t* pLen\r
+);\r
+\r
+extern int32_t Bcp_addDIOHeader (\r
+ Bcp_DioHdrCfg* pDioHdrCfg, \r
+ uint8_t* pData,\r
+ uint32_t* pLen\r
+);\r
+\r
+extern int32_t Bcp_lldOpen \r
+(\r
+ uint8_t instNum,\r
+ uint32_t cfgRegsBaseAddress,\r
+ Bcp_LldObj* pBcpLldObj\r
+);\r
+\r
+extern int32_t Bcp_lldClose \r
+(\r
+ Bcp_LldObj* pBcpLldObj\r
+);\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __BCP_LLD_H__ */\r
+\r
diff --git a/packages/ti/drv/bcp/bcp_mmr.h b/packages/ti/drv/bcp/bcp_mmr.h
--- /dev/null
@@ -0,0 +1,5133 @@
+/** \r
+ * @file bcp_mmr.h\r
+ *\r
+ * @brief \r
+ * Header file with BCP Memory Mapped Register (MMR) access functions.\r
+ * \r
+ * \par\r
+ * ============================================================================\r
+ * @n (C) Copyright 2010, Texas Instruments, Inc.\r
+ * \r
+ * Redistribution and use in source and binary forms, with or without \r
+ * modification, are permitted provided that the following conditions \r
+ * are met:\r
+ *\r
+ * Redistributions of source code must retain the above copyright \r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the \r
+ * documentation and/or other materials provided with the \r
+ * distribution.\r
+ *\r
+ * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \r
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT \r
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT \r
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, \r
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT \r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT \r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE \r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+*/\r
+\r
+#ifndef _BCP_MMR_H_\r
+#define _BCP_MMR_H_\r
+\r
+#include <ti/drv/bcp/bcp_lld.h>\r
+\r
+/** @addtogroup BCP_LLD_DATASTRUCT\r
+ @{ */\r
+\r
+/** \r
+ * @brief Bcp_PeripheralIdParams\r
+ * \r
+ * Configuration structure to hold BCP \r
+ * Peripheral ID Register contents.\r
+ */\r
+typedef struct _Bcp_PeripheralIdParams\r
+{\r
+ /** Minor Version Number (Y) */\r
+ uint8_t minorNum;\r
+ /** Custom Version Number */\r
+ uint8_t customNum;\r
+ /** Major Version Number (X) */\r
+ uint8_t majorNum;\r
+ /** RTL Version Number (R) */\r
+ uint8_t rtlVersion;\r
+ /** Fixed module ID. */ \r
+ uint16_t function;\r
+ /** Scheme. */ \r
+ uint8_t scheme;\r
+} Bcp_PeripheralIdParams;\r
+\r
+/** \r
+ * @brief Bcp_ModuleIdleStatus\r
+ * \r
+ * Configuration structure to hold the idle\r
+ * status of various BCP submodules.\r
+ */\r
+typedef struct _Bcp_ModuleIdleStatus\r
+{\r
+ uint8_t tm_idle_status; \r
+ uint8_t dio_idle_status; \r
+ uint8_t crc_idle_status; \r
+ uint8_t enc_idle_status; \r
+ uint8_t rm_idle_status; \r
+ uint8_t mod_idle_status; \r
+ uint8_t int_idle_status; \r
+ uint8_t cor_idle_status; \r
+ uint8_t ssl_idle_status; \r
+ uint8_t rd_idle_status; \r
+ uint8_t dnt_idle_status; \r
+ uint8_t all_idle_status; \r
+} Bcp_ModuleIdleStatus;\r
+\r
+/** \r
+ * @brief Bcp_ModuleCfg\r
+ * \r
+ * Structure to hold the configuration\r
+ * parameters for various BCP submodules.\r
+ */\r
+typedef struct _Bcp_ModuleCfg\r
+{\r
+ uint8_t tm; \r
+ uint8_t dio; \r
+ uint8_t crc; \r
+ uint8_t enc; \r
+ uint8_t rm; \r
+ uint8_t mod; \r
+ uint8_t intleaver; \r
+ uint8_t cor; \r
+ uint8_t ssl; \r
+ uint8_t rd; \r
+ uint8_t dnt; \r
+} Bcp_ModuleCfg;\r
+\r
+/** \r
+ * @brief Bcp_TmIntCfg\r
+ * \r
+ * Structure to hold the configuration\r
+ * parameters/status for Traffic Manager (TM)\r
+ * Interrupts.\r
+ */\r
+typedef struct _Bcp_TmIntCfg\r
+{\r
+ uint8_t ppb_error; \r
+ uint8_t dlg_done_int; \r
+ uint8_t eng_error; \r
+} Bcp_TmIntCfg;\r
+\r
+/** \r
+ * @brief Bcp_TmFlowEntry\r
+ * \r
+ * Structure to hold the configuration\r
+ * parameters of a TM Flow table entry.\r
+ */\r
+typedef struct _Bcp_TmFlowEntry\r
+{\r
+ /** Input data endian format */\r
+ Bcp_EndianFormat endian_in; \r
+\r
+ /** Input data format */\r
+ Bcp_DataFormat format_in; \r
+\r
+ /** Packet type to put in Info Word 0 on Rx */\r
+ uint8_t pkt_type;\r
+\r
+ /** Which DSP to interrupt */\r
+ uint8_t dsp_int_sel;\r
+\r
+ /** Output data endian format */\r
+ Bcp_EndianFormat endian_out; \r
+\r
+ /** Output data format */\r
+ Bcp_DataFormat format_out; \r
+\r
+ /** Output QFIFO to use */\r
+ uint8_t qfifo_out;\r
+\r
+ /** PS flags to configure in packet Info word 0 */\r
+ uint8_t ps_flags;\r
+} Bcp_TmFlowEntry;\r
+\r
+/** \r
+ * @brief Bcp_DlgCtrlMode\r
+ *\r
+ * Enumeration for specifying the DLG control modes.\r
+ */ \r
+typedef enum \r
+{\r
+ /** Idle Mode.\r
+ * \r
+ * Data logger does not capture any information and write pointer\r
+ * is reset to address 0.\r
+ */\r
+ Bcp_DlgCtrlMode_Idle = 0,\r
+ /** Errors only Mode.\r
+ * \r
+ * Data logger stores information only on errored packets. Write counter\r
+ * is allowed to wrap so writes continue indefinitely.\r
+ */\r
+ Bcp_DlgCtrlMode_ErrorsOnly = 1,\r
+ /** Start On Error Mode.\r
+ * \r
+ * Data logger starts capturing data on next error and captures info\r
+ * for all following packets until all memory locations have been written.\r
+ */\r
+ Bcp_DlgCtrlMode_StartOnError = 2,\r
+ /** Stop On Error Mode.\r
+ * \r
+ * Data logger stores data from all packets until an error occurs.\r
+ * When the error occurs it stores that packets data and stops \r
+ * collecting data.\r
+ */\r
+ Bcp_DlgCtrlMode_StopOnError = 3,\r
+ /** Free Run Mode.\r
+ * \r
+ * Data logger stores data from all packets. Write counter is allowed\r
+ * to wrap so writes continue indefinitely.\r
+ */\r
+ Bcp_DlgCtrlMode_FreeRun = 4,\r
+ /** One Shot Mode.\r
+ * \r
+ * Data logger stores data from all packets starting at location 0\r
+ * and continues until all memory has been written and then stops.\r
+ */\r
+ Bcp_DlgCtrlMode_OneShot = 5,\r
+ /** Hold Mode.\r
+ * \r
+ * Data logger does not store any more information but does not clear\r
+ * the write pointer.\r
+ */\r
+ Bcp_DlgCtrlMode_Hold = 7\r
+} Bcp_DlgCtrlMode;\r
+\r
+/** @brief\r
+ * Maximum number of Data logger RAM entries in any BCP Submodule\r
+ */ \r
+#define BCP_MAX_NUM_DLG_RAM_ENTRIES (256) \r
+\r
+/** \r
+ * @brief Bcp_DlgRamEntry\r
+ * \r
+ * Structure to hold the DLG RAM entry contents.\r
+ */\r
+typedef struct _Bcp_DlgRamEntry\r
+{\r
+ /** Global Header field contents */\r
+ uint32_t global_hdr_val; \r
+\r
+ /** Software Timestamp value */\r
+ uint32_t sw_timestamp_val; \r
+\r
+ /** Hardware Timestamp value */\r
+ uint8_t hw_timestamp_val; \r
+\r
+ /** Engine error field value */\r
+ uint8_t engine_error_val; \r
+} Bcp_DlgRamEntry;\r
+\r
+\r
+/**\r
+@}\r
+*/\r
+\r
+\r
+/** @addtogroup BCP_LLD_FUNCTION\r
+ @{ \r
+ */\r
+\r
+/****************** Encoder Engine MMR ******************/\r
+\r
+/**\r
+ * ============================================================================\r
+ * @n@b Bcp_getEncPolyCoef1Reg\r
+ *\r
+ * @b brief\r
+ * @n This API returns the contents of POLY_COEF1 register. The POLY_COEF1 \r
+ * register contains the convolutional encoder coefficient for \r
+ * WCDMA Code Rate 1/2.\r
+ *\r
+ * @param[in] \r
+ pBcpLldObj BCP LLD instance object.\r
+\r
+ * @return int32_t\r
+ * @li -1 - Invalid BCP instance handle passed.\r
+ * @li >=0 - Contents of POLY_COEF1 register.\r
+ *\r
+ * @pre\r
+ * @n @a Bcp_lldOpen () must be called to obtain the register overlay handle for \r
+ * BCP instance before calling this API. \r
+ *\r
+ * @post\r
+ * @n None.\r
+ * ============================================================================\r
+ */\r
+static inline int32_t Bcp_getEncPolyCoef1Reg \r
+(\r
+ Bcp_LldObj* pBcpLldObj\r
+)\r
+{\r
+ CSL_Bcp_encRegs* pEncRegs;\r
+\r
+ if (!pBcpLldObj || !pBcpLldObj->modCfgRegs[0])\r
+ return -1;\r
+\r
+ pEncRegs = (CSL_Bcp_encRegs *) (pBcpLldObj->modCfgRegs[Bcp_ModuleId_ENC]);\r
+\r
+ return CSL_FEXT (pEncRegs->POLY_COEF1, BCP_ENC_POLY_COEF1_POLYCOEF1);\r
+}\r
+\r
+/**\r
+ * ============================================================================\r
+ * @n@b Bcp_setEncPolyCoef1Reg\r
+ *\r
+ * @b brief\r
+ * @n This API populates the contents of POLY_COEF1 register. The POLY_COEF1 \r
+ * register contains the convolutional encoder coefficient for \r
+ * WCDMA Code Rate 1/2.\r
+ *\r
+ * @param[in] \r
+ pBcpLldObj BCP LLD instance object.\r
+\r
+ * @param[in] \r
+ polyCoefVal Value to configure in POLY_COEF1 register.\r
+\r
+ * @return int32_t\r
+ * @li -1 - Invalid BCP instance handle passed.\r
+ * @li 0 - Encoder engine's POLY_COEF1 register successfully\r
+ * configured.\r
+ *\r
+ * @pre\r
+ * @n @a Bcp_lldOpen () must be called to obtain the register overlay handle for \r
+ * BCP instance before calling this API. \r
+ *\r
+ * @post\r
+ * @n POLY_COEF1 register configured.\r
+ * ============================================================================\r
+ */\r
+static inline int32_t Bcp_setEncPolyCoef1Reg \r
+(\r
+ Bcp_LldObj* pBcpLldObj,\r
+ uint32_t polyCoefVal\r
+)\r
+{\r
+ CSL_Bcp_encRegs* pEncRegs;\r
+\r
+ if (!pBcpLldObj || !pBcpLldObj->modCfgRegs[0])\r
+ return -1;\r
+\r
+ pEncRegs = (CSL_Bcp_encRegs *) (pBcpLldObj->modCfgRegs[Bcp_ModuleId_ENC]);\r
+\r
+ CSL_FINS (pEncRegs->POLY_COEF1, BCP_ENC_POLY_COEF1_POLYCOEF1, polyCoefVal);\r
+\r
+ /* Return success */\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * ============================================================================\r
+ * @n@b Bcp_getEncPolyCoef2Reg\r
+ *\r
+ * @b brief\r
+ * @n This API returns the contents of POLY_COEF2 register. The POLY_COEF2 \r
+ * register contains the convolutional encoder coefficient for \r
+ * WCDMA Code Rate 1/3.\r
+ *\r
+ * @param[in] \r
+ pBcpLldObj BCP LLD instance object.\r
+\r
+ * @return int32_t\r
+ * @li -1 - Invalid BCP instance handle passed.\r
+ * @li >=0 - Contents of POLY_COEF2 register.\r
+ *\r
+ * @pre\r
+ * @n @a Bcp_lldOpen () must be called to obtain the register overlay handle for \r
+ * BCP instance before calling this API. \r
+ *\r
+ * @post\r
+ * @n None.\r
+ * ============================================================================\r
+ */\r
+static inline int32_t Bcp_getEncPolyCoef2Reg \r
+(\r
+ Bcp_LldObj* pBcpLldObj\r
+)\r
+{\r
+ CSL_Bcp_encRegs* pEncRegs;\r
+\r
+ if (!pBcpLldObj || !pBcpLldObj->modCfgRegs[0])\r
+ return -1;\r
+\r
+ pEncRegs = (CSL_Bcp_encRegs *) (pBcpLldObj->modCfgRegs[Bcp_ModuleId_ENC]);\r
+\r
+ return CSL_FEXT (pEncRegs->POLY_COEF2, BCP_ENC_POLY_COEF2_POLYCOEF2);\r
+}\r
+\r
+/**\r
+ * ============================================================================\r
+ * @n@b Bcp_setEncPolyCoef2Reg\r
+ *\r
+ * @b brief\r
+ * @n This API populates the contents of POLY_COEF2 register. The POLY_COEF2 \r
+ * register contains the convolutional encoder coefficient for \r
+ * WCDMA Code Rate 1/3.\r
+ *\r
+ * @param[in] \r
+ pBcpLldObj BCP LLD instance object.\r
+\r
+ * @param[in] \r
+ polyCoefVal Value to configure in POLY_COEF2 register.\r
+\r
+ * @return int32_t\r
+ * @li -1 - Invalid BCP instance handle passed.\r
+ * @li 0 - Success.\r
+ *\r
+ * @pre\r
+ * @n @a Bcp_lldOpen () must be called to obtain the register overlay handle for \r
+ * BCP instance before calling this API. \r
+ *\r
+ * @post\r
+ * @n POLY_COEF2 register configured.\r
+ * ============================================================================\r
+ */\r
+static inline int32_t Bcp_setEncPolyCoef2Reg \r
+(\r
+ Bcp_LldObj* pBcpLldObj,\r
+ uint32_t polyCoefVal\r
+)\r
+{\r
+ CSL_Bcp_encRegs* pEncRegs;\r
+\r
+ if (!pBcpLldObj || !pBcpLldObj->modCfgRegs[0])\r
+ return -1;\r
+\r
+ pEncRegs = (CSL_Bcp_encRegs *) (pBcpLldObj->modCfgRegs[Bcp_ModuleId_ENC]);\r
+\r
+ CSL_FINS (pEncRegs->POLY_COEF2, BCP_ENC_POLY_COEF2_POLYCOEF2, polyCoefVal);\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * ============================================================================\r
+ * @n@b Bcp_getEncPolyCoef3Reg\r
+ *\r
+ * @b brief\r
+ * @n This API returns the contents of POLY_COEF3 register. The POLY_COEF3 \r
+ * register contains the convolutional encoder coefficient for \r
+ * LTE Code Rate 1/3.\r
+ *\r
+ * @param[in] \r
+ pBcpLldObj BCP LLD instance object.\r
+\r
+ * @return int32_t\r
+ * @li -1 - Invalid BCP instance handle passed.\r
+ * @li >=0 - Contents of POLY_COEF3 register.\r
+ *\r
+ * @pre\r
+ * @n @a Bcp_lldOpen () must be called to obtain the register overlay handle for \r
+ * BCP instance before calling this API. \r
+ *\r
+ * @post\r
+ * @n None.\r
+ * ============================================================================\r
+ */\r
+static inline int32_t Bcp_getEncPolyCoef3Reg \r
+(\r
+ Bcp_LldObj* pBcpLldObj\r
+)\r
+{\r
+ CSL_Bcp_encRegs* pEncRegs;\r
+\r
+ if (!pBcpLldObj || !pBcpLldObj->modCfgRegs[0])\r
+ return -1;\r
+\r
+ pEncRegs = (CSL_Bcp_encRegs *) (pBcpLldObj->modCfgRegs[Bcp_ModuleId_ENC]);\r
+\r
+\r
+ return CSL_FEXT (pEncRegs->POLY_COEF3, BCP_ENC_POLY_COEF3_POLYCOEF3);\r
+}\r
+\r
+/**\r
+ * ============================================================================\r
+ * @n@b Bcp_setEncPolyCoef3Reg\r
+ *\r
+ * @b brief\r
+ * @n This API populates the contents of POLY_COEF3 register. The POLY_COEF3 \r
+ * register contains the convolutional encoder coefficient for \r
+ * LTE Code Rate 1/3.\r
+ *\r
+ * @param[in] \r
+ pBcpLldObj BCP LLD instance object.\r
+\r
+ * @param[in] \r
+ polyCoefVal Value to configure in POLY_COEF3 register.\r
+\r
+ * @return void\r
+ * @li -1 - Invalid BCP instance handle passed.\r
+ * @li 0 - Success.\r
+ *\r
+ * @pre\r
+ * @n @a Bcp_lldOpen () must be called to obtain the register overlay handle for \r
+ * BCP instance before calling this API. \r
+ *\r
+ * @post\r
+ * @n POLY_COEF3 register configured.\r
+ * ============================================================================\r
+ */\r
+static inline int32_t Bcp_setEncPolyCoef3Reg \r
+(\r
+ Bcp_LldObj* pBcpLldObj,\r
+ uint32_t polyCoefVal\r
+)\r
+{\r
+ CSL_Bcp_encRegs* pEncRegs;\r
+\r
+ if (!pBcpLldObj || !pBcpLldObj->modCfgRegs[0])\r
+ return -1;\r
+\r
+ pEncRegs = (CSL_Bcp_encRegs *) (pBcpLldObj->modCfgRegs[Bcp_ModuleId_ENC]);\r
+\r
+ CSL_FINS (pEncRegs->POLY_COEF3, BCP_ENC_POLY_COEF3_POLYCOEF3, polyCoefVal);\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * ============================================================================\r
+ * @n@b Bcp_getEncScrInit0Reg\r
+ *\r
+ * @b brief\r
+ * @n This API returns the contents of SCR_INIT_0 register. The SCR_INIT_0 \r
+ * register contains the WiMax randomizer initialization value.\r
+ *\r
+ * @param[in] \r
+ pBcpLldObj BCP LLD instance object.\r
+\r
+ * @return int32_t\r
+ * @li -1 - Invalid BCP instance handle passed.\r
+ * @li >=0 - Contents of SCR_INIT_0 register.\r
+ *\r
+ * @pre\r
+ * @n @a Bcp_lldOpen () must be called to obtain the register overlay handle for \r
+ * BCP instance before calling this API. \r
+ *\r
+ * @post\r
+ * @n None.\r
+ * ============================================================================\r
+ */\r
+static inline int32_t Bcp_getEncScrInit0Reg \r
+(\r
+ Bcp_LldObj* pBcpLldObj\r
+)\r
+{\r
+ CSL_Bcp_encRegs* pEncRegs;\r
+\r
+ if (!pBcpLldObj || !pBcpLldObj->modCfgRegs[0])\r
+ return -1;\r
+\r
+ pEncRegs = (CSL_Bcp_encRegs *) (pBcpLldObj->modCfgRegs[Bcp_ModuleId_ENC]);\r
+\r
+ return CSL_FEXT (pEncRegs->SCR_INIT_0, BCP_ENC_SCR_INIT_0_SCRINIT);\r
+}\r
+\r
+/**\r
+ * ============================================================================\r
+ * @n@b Bcp_setEncScrInit0Reg\r
+ *\r
+ * @b brief\r
+ * @n This API populates the contents of SCR_INIT_0 register. The SCR_INIT_0 \r
+ * register contains the WiMax randomizer initialization value.\r
+ *\r
+ * @param[in] \r
+ pBcpLldObj BCP LLD instance object.\r
+\r
+ * @param[in] \r
+ initVal Value to configure in SCR_INIT_0 register.\r
+\r
+ * @return int32_t\r
+ * @li -1 - Invalid BCP instance handle passed.\r
+ * @li 0 - Success.\r
+ *\r
+ * @pre\r
+ * @n @a Bcp_lldOpen () must be called to obtain the register overlay handle for \r
+ * BCP instance before calling this API. \r
+ *\r
+ * @post\r
+ * @n SCR_INIT_0 register configured.\r
+ * ============================================================================\r
+ */\r
+static inline int32_t Bcp_setEncScrInit0Reg \r
+(\r
+ Bcp_LldObj* pBcpLldObj,\r
+ uint32_t initVal\r
+)\r
+{\r
+ CSL_Bcp_encRegs* pEncRegs;\r
+\r
+ if (!pBcpLldObj || !pBcpLldObj->modCfgRegs[0])\r
+ return -1;\r
+\r
+ pEncRegs = (CSL_Bcp_encRegs *) (pBcpLldObj->modCfgRegs[Bcp_ModuleId_ENC]);\r
+\r
+ CSL_FINS (pEncRegs->SCR_INIT_0, BCP_ENC_SCR_INIT_0_SCRINIT, initVal);\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * ============================================================================\r
+ * @n@b Bcp_getEncScrPoly0Reg\r
+ *\r
+ * @b brief\r
+ * @n This API returns the contents of SCR_POLY_0 register. The SCR_POLY_0 \r
+ * register contains the WiMax randomizer polynomial value.\r
+ *\r
+ * @param[in] \r
+ pBcpLldObj BCP LLD instance object.\r
+\r
+ * @return int32_t\r
+ * @li -1 - Invalid BCP instance handle passed.\r
+ * @li >=0 - Contents of SCR_POLY_0 register.\r
+ *\r
+ * @pre\r
+ * @n @a Bcp_lldOpen () must be called to obtain the register overlay handle for \r
+ * BCP instance before calling this API. \r
+ *\r
+ * @post\r
+ * @n None.\r
+ * ============================================================================\r
+ */\r
+static inline int32_t Bcp_getEncScrPoly0Reg \r
+(\r
+ Bcp_LldObj* pBcpLldObj\r
+)\r
+{\r
+ CSL_Bcp_encRegs* pEncRegs;\r
+\r
+ if (!pBcpLldObj || !pBcpLldObj->modCfgRegs[0])\r
+ return -1;\r
+\r
+ pEncRegs = (CSL_Bcp_encRegs *) (pBcpLldObj->modCfgRegs[Bcp_ModuleId_ENC]);\r
+\r
+ return CSL_FEXT (pEncRegs->SCR_POLY_0, BCP_ENC_SCR_POLY_0_SCRPOLY);\r
+}\r
+\r
+/**\r
+ * ============================================================================\r
+ * @n@b Bcp_setEncScrPoly0Reg\r
+ *\r
+ * @b brief\r
+ * @n This API populates the contents of SCR_POLY_0 register. The SCR_POLY_0 \r
+ * register contains the WiMax randomizer polynomial value.\r
+ *\r
+ * @param[in] \r
+ pBcpLldObj BCP LLD instance object.\r
+\r
+ * @param[in] \r
+ polyVal Value to configure in SCR_POLY_0 register.\r
+\r
+ * @return int32_t\r
+ * @li -1 - Invalid BCP instance handle passed.\r
+ * @li 0 - Success.\r
+ *\r
+ * @pre\r
+ * @n @a Bcp_lldOpen () must be called to obtain the register overlay handle for \r
+ * BCP instance before calling this API. \r
+ *\r
+ * @post\r
+ * @n SCR_POLY_0 register configured.\r
+ * ============================================================================\r
+ */\r
+static inline int32_t Bcp_setEncScrPoly0Reg \r
+(\r
+ Bcp_LldObj* pBcpLldObj,\r
+ uint32_t polyVal\r
+)\r
+{\r
+ CSL_Bcp_encRegs* pEncRegs;\r
+\r
+ if (!pBcpLldObj || !pBcpLldObj->modCfgRegs[0])\r
+ return -1;\r
+\r
+ pEncRegs = (CSL_Bcp_encRegs *) (pBcpLldObj->modCfgRegs[Bcp_ModuleId_ENC]);\r
+\r
+ CSL_FINS (pEncRegs->SCR_POLY_0, BCP_ENC_SCR_POLY_0_SCRPOLY, polyVal);\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * ============================================================================\r
+ * @n@b Bcp_getEncCrc24Init0Reg\r
+ *\r
+ * @b brief\r
+ * @n This API returns the contents of CRC24_INIT_0 register. The CRC24_INIT_0 \r
+ * register contains the CRC-24 initialization value.\r
+ *\r
+ * @param[in] \r
+ pBcpLldObj BCP LLD instance object.\r
+\r
+ * @return int32_t\r
+ * @li -1 - Invalid BCP instance handle passed.\r
+ * @li >=0 - Contents of CRC24_INIT_0 register.\r
+ *\r
+ * @pre\r
+ * @n @a Bcp_lldOpen () must be called to obtain the register overlay handle for \r
+ * BCP instance before calling this API. \r
+ *\r
+ * @post\r
+ * @n None.\r
+ * ============================================================================\r
+ */\r
+static inline int32_t Bcp_getEncCrc24Init0Reg \r
+(\r
+ Bcp_LldObj* pBcpLldObj\r
+)\r
+{\r
+ CSL_Bcp_encRegs* pEncRegs;\r
+\r
+ if (!pBcpLldObj || !pBcpLldObj->modCfgRegs[0])\r
+ return -1;\r
+\r
+ pEncRegs = (CSL_Bcp_encRegs *) (pBcpLldObj->modCfgRegs[Bcp_ModuleId_ENC]);\r
+\r
+ return CSL_FEXT (pEncRegs->CRC24_INIT_0, BCP_ENC_CRC24_INIT_0_CRC24INIT);\r
+}\r
+\r
+/**\r
+ * ============================================================================\r
+ * @n@b Bcp_setEncCrc24Init0Reg\r
+ *\r
+ * @b brief\r
+ * @n This API populates the contents of CRC24_INIT_0 register. The CRC24_INIT_0 \r
+ * register contains the CRC-24 initialization value.\r
+ *\r
+ * @param[in] \r
+ pBcpLldObj BCP LLD instance object.\r
+\r
+ * @param[in] \r
+ initVal Value to configure in CRC24_INIT_0 register.\r
+\r
+ * @return int32_t\r
+ * @li -1 - Invalid BCP instance handle passed.\r
+ * @li 0 - Success.\r
+ *\r
+ * @pre\r
+ * @n @a Bcp_lldOpen () must be called to obtain the register overlay handle for \r
+ * BCP instance before calling this API. \r
+ *\r
+ * @post\r
+ * @n CRC24_INIT_0 register configured.\r
+ * ============================================================================\r
+ */\r
+static inline int32_t Bcp_setEncCrc24Init0Reg \r
+(\r
+ Bcp_LldObj* pBcpLldObj,\r
+ uint32_t initVal\r
+)\r
+{\r
+ CSL_Bcp_encRegs* pEncRegs;\r
+\r
+ if (!pBcpLldObj || !pBcpLldObj->modCfgRegs[0])\r
+ return -1;\r
+\r
+ pEncRegs = (CSL_Bcp_encRegs *) (pBcpLldObj->modCfgRegs[Bcp_ModuleId_ENC]);\r
+\r
+ CSL_FINS (pEncRegs->CRC24_INIT_0, BCP_ENC_CRC24_INIT_0_CRC24INIT, initVal);\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * ============================================================================\r
+ * @n@b Bcp_getEncCrc24Poly0Reg\r
+ *\r
+ * @b brief\r
+ * @n This API returns the contents of CRC24_POLY_0 register. The CRC24_POLY_0 \r
+ * register contains the CRC-24 polynomial value.\r
+ *\r
+ * @param[in] \r
+ pBcpLldObj BCP LLD instance object.\r
+\r
+ * @return int32_t\r
+ * @li -1 - Invalid BCP instance handle passed.\r
+ * @li >=0 - Contents of CRC24_POLY_0 register.\r
+ *\r
+ * @pre\r
+ * @n @a Bcp_lldOpen () must be called to obtain the register overlay handle for \r
+ * BCP instance before calling this API. \r
+ *\r
+ * @post\r
+ * @n None.\r
+ * ============================================================================\r
+ */\r
+static inline int32_t Bcp_getEncCrc24Poly0Reg \r
+(\r
+ Bcp_LldObj* pBcpLldObj\r
+)\r
+{\r
+ CSL_Bcp_encRegs* pEncRegs;\r
+\r
+ if (!pBcpLldObj || !pBcpLldObj->modCfgRegs[0])\r
+ return -1;\r
+\r
+ pEncRegs = (CSL_Bcp_encRegs *) (pBcpLldObj->modCfgRegs[Bcp_ModuleId_ENC]);\r
+\r
+ return CSL_FEXT (pEncRegs->CRC24_POLY_0, BCP_ENC_CRC24_POLY_0_CRC24POLY);\r
+}\r
+\r
+/**\r
+ * ============================================================================\r
+ * @n@b Bcp_setEncCrc24Poly0Reg\r
+ *\r
+ * @b brief\r
+ * @n This API populates the contents of CRC24_POLY_0 register. The CRC24_POLY_0 \r
+ * register contains the CRC-24 polynomial value.\r
+ *\r
+ * @param[in] \r
+ pBcpLldObj BCP LLD instance object.\r
+\r
+ * @param[in] \r
+ polyVal Value to configure in CRC24_POLY_0 register.\r
+\r
+ * @return int32_t\r
+ * @li -1 - Invalid BCP instance handle passed.\r
+ * @li 0 - Success.\r
+ *\r
+ * @pre\r
+ * @n @a Bcp_lldOpen () must be called to obtain the register overlay handle for \r
+ * BCP instance before calling this API. \r
+ *\r
+ * @post\r
+ * @n CRC24_POLY_0 register configured.\r
+ * ============================================================================\r
+ */\r
+static inline int32_t Bcp_setEncCrc24Poly0Reg \r
+(\r
+ Bcp_LldObj* pBcpLldObj,\r
+ uint32_t polyVal\r
+)\r
+{\r
+ CSL_Bcp_encRegs* pEncRegs;\r
+\r
+ if (!pBcpLldObj || !pBcpLldObj->modCfgRegs[0])\r
+ return -1;\r
+\r
+ pEncRegs = (CSL_Bcp_encRegs *) (pBcpLldObj->modCfgRegs[Bcp_ModuleId_ENC]);\r
+\r
+ CSL_FINS (pEncRegs->CRC24_POLY_0, BCP_ENC_CRC24_POLY_0_CRC24POLY, polyVal);\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * ============================================================================\r
+ * @n@b Bcp_getEncScrInit1Reg\r
+ *\r
+ * @b brief\r
+ * @n This API returns the contents of SCR_INIT_1 register. The SCR_INIT_1 \r
+ * register contains the WiMax randomizer initialization value.\r
+ *\r
+ * @param[in] \r
+ pBcpLldObj BCP LLD instance object.\r
+\r
+ * @return int32_t\r
+ * @li -1 - Invalid BCP instance handle passed.\r
+ * @li >=0 - Contents of SCR_INIT_1 register.\r
+ *\r
+ * @pre\r
+ * @n @a Bcp_lldOpen () must be called to obtain the register overlay handle for \r
+ * BCP instance before calling this API. \r
+ *\r
+ * @post\r
+ * @n None.\r
+ * ============================================================================\r
+ */\r
+static inline int32_t Bcp_getEncScrInit1Reg \r
+(\r
+ Bcp_LldObj* pBcpLldObj\r
+)\r
+{\r
+ CSL_Bcp_encRegs* pEncRegs;\r
+\r
+ if (!pBcpLldObj || !pBcpLldObj->modCfgRegs[0])\r
+ return -1;\r
+\r
+ pEncRegs = (CSL_Bcp_encRegs *) (pBcpLldObj->modCfgRegs[Bcp_ModuleId_ENC]);\r
+\r
+ return CSL_FEXT (pEncRegs->SCR_INIT_1, BCP_ENC_SCR_INIT_1_SCRINIT);\r
+}\r
+\r
+/**\r
+ * ============================================================================\r
+ * @n@b Bcp_setEncScrInit1Reg\r
+ *\r
+ * @b brief\r
+ * @n This API populates the contents of SCR_INIT_1 register. The SCR_INIT_1 \r
+ * register contains the WiMax randomizer initialization value.\r
+ *\r
+ * @param[in] \r
+ pBcpLldObj BCP LLD instance object.\r
+\r
+ * @param[in] \r
+ initVal Value to configure in SCR_INIT_1 register.\r
+\r
+ * @return int32_t\r
+ * @li -1 - Invalid BCP instance handle passed.\r
+ * @li 0 - Success.\r
+ *\r
+ * @pre\r
+ * @n @a Bcp_lldOpen () must be called to obtain the register overlay handle for \r
+ * BCP instance before calling this API. \r
+ *\r
+ * @post\r
+ * @n SCR_INIT_1 register configured.\r
+ * ============================================================================\r
+ */\r
+static inline int32_t Bcp_setEncScrInit1Reg \r
+(\r
+ Bcp_LldObj* pBcpLldObj,\r
+ uint32_t initVal\r
+)\r
+{\r
+ CSL_Bcp_encRegs* pEncRegs;\r
+\r
+ if (!pBcpLldObj || !pBcpLldObj->modCfgRegs[0])\r
+ return -1;\r
+\r
+ pEncRegs = (CSL_Bcp_encRegs *) (pBcpLldObj->modCfgRegs[Bcp_ModuleId_ENC]);\r
+\r
+ CSL_FINS (pEncRegs->SCR_INIT_1, BCP_ENC_SCR_INIT_1_SCRINIT, initVal);\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * ============================================================================\r
+ * @n@b Bcp_getEncScrPoly1Reg\r
+ *\r
+ * @b brief\r
+ * @n This API returns the contents of SCR_POLY_1 register. The SCR_POLY_1 \r
+ * register contains the WiMax randomizer polynomial value.\r
+ *\r
+ * @param[in] \r
+ pBcpLldObj BCP LLD instance object.\r
+\r
+ * @return int32_t\r
+ * @li -1 - Invalid BCP instance handle passed.\r
+ * @li >=0 - Contents of SCR_POLY_1 register.\r
+ *\r
+ * @pre\r
+ * @n @a Bcp_lldOpen () must be called to obtain the register overlay handle for \r
+ * BCP instance before calling this API. \r
+ *\r
+ * @post\r
+ * @n None.\r
+ * ============================================================================\r
+ */\r
+static inline int32_t Bcp_getEncScrPoly1Reg \r
+(\r
+ Bcp_LldObj* pBcpLldObj\r
+)\r
+{\r
+ CSL_Bcp_encRegs* pEncRegs;\r
+\r
+ if (!pBcpLldObj || !pBcpLldObj->modCfgRegs[0])\r
+ return -1;\r
+\r
+ pEncRegs = (CSL_Bcp_encRegs *) (pBcpLldObj->modCfgRegs[Bcp_ModuleId_ENC]);\r
+\r
+ return CSL_FEXT (pEncRegs->SCR_POLY_1, BCP_ENC_SCR_POLY_1_SCRPOLY);\r
+}\r
+\r
+/**\r
+ * ============================================================================\r
+ * @n@b Bcp_setEncScrPoly1Reg\r
+ *\r
+ * @b brief\r
+ * @n This API populates the contents of SCR_POLY_1 register. The SCR_POLY_1 \r
+ * register contains the WiMax randomizer polynomial value.\r
+ *\r
+ * @param[in] \r
+ pBcpLldObj BCP LLD instance object.\r
+\r
+ * @param[in] \r
+ polyVal Value to configure in SCR_POLY_1 register.\r
+\r
+ * @return int32_t\r
+ * @li -1 - Invalid BCP instance handle passed.\r
+ * @li 0 - Success.\r
+ *\r
+ * @pre\r
+ * @n @a Bcp_lldOpen () must be called to obtain the register overlay handle for \r
+ * BCP instance before calling this API. \r
+ *\r
+ * @post\r
+ * @n SCR_POLY_1 register configured.\r
+ * ============================================================================\r
+ */\r
+static inline int32_t Bcp_setEncScrPoly1Reg \r
+(\r
+ Bcp_LldObj* pBcpLldObj,\r
+ uint32_t polyVal\r
+)\r
+{\r
+ CSL_Bcp_encRegs* pEncRegs;\r
+\r
+ if (!pBcpLldObj || !pBcpLldObj->modCfgRegs[0])\r
+ return -1;\r
+\r
+ pEncRegs = (CSL_Bcp_encRegs *) (pBcpLldObj->modCfgRegs[Bcp_ModuleId_ENC]);\r
+\r
+ CSL_FINS (pEncRegs->SCR_POLY_1, BCP_ENC_SCR_POLY_1_SCRPOLY, polyVal);\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * ============================================================================\r
+ * @n@b Bcp_getEncCrc16Init1Reg\r
+ *\r
+ * @b brief\r
+ * @n This API returns the contents of CRC16_INIT_1 register. The CRC16_INIT_1 \r
+ * register contains the CRC-16 initialization value.\r
+ *\r
+ * @param[in] \r
+ pBcpLldObj BCP LLD instance object.\r
+\r
+ * @return int32_t\r
+ * @li -1 - Invalid BCP instance handle passed.\r
+ * @li >=0 - Contents of CRC16_INIT_1 register.\r
+ *\r
+ * @pre\r
+ * @n @a Bcp_lldOpen () must be called to obtain the register overlay handle for \r
+ * BCP instance before calling this API. \r
+ *\r
+ * @post\r
+ * @n None.\r
+ * ============================================================================\r
+ */\r
+static inline int32_t Bcp_getEncCrc16Init1Reg \r
+(\r
+ Bcp_LldObj* pBcpLldObj\r
+)\r
+{\r
+ CSL_Bcp_encRegs* pEncRegs;\r
+\r
+ if (!pBcpLldObj || !pBcpLldObj->modCfgRegs[0])\r
+ return -1;\r
+\r
+ pEncRegs = (CSL_Bcp_encRegs *) (pBcpLldObj->modCfgRegs[Bcp_ModuleId_ENC]);\r
+\r
+ return CSL_FEXT (pEncRegs->CRC16_INIT_1, BCP_ENC_CRC16_INIT_1_CRC16INIT);\r
+}\r
+\r
+/**\r
+ * ============================================================================\r
+ * @n@b Bcp_setEncCrc16Init1Reg\r
+ *\r
+ * @b brief\r
+ * @n This API populates the contents of CRC16_INIT_1 register. The CRC16_INIT_1 \r
+ * register contains the CRC-16 initialization value.\r
+ *\r
+ * @param[in] \r
+ pBcpLldObj BCP LLD instance object.\r
+\r
+ * @param[in] \r
+ initVal Value to configure in CRC16_INIT_1 register.\r
+\r
+ * @return int32_t\r
+ * @li -1 - Invalid BCP instance handle passed.\r
+ * @li 0 - Success.\r
+ *\r
+ * @pre\r
+ * @n @a Bcp_lldOpen () must be called to obtain the register overlay handle for \r
+ * BCP instance before calling this API. \r
+ *\r
+ * @post\r
+ * @n CRC16_INIT_1 register configured.\r
+ * ============================================================================\r
+ */\r
+static inline int32_t Bcp_setEncCrc16Init1Reg \r
+(\r
+ Bcp_LldObj* pBcpLldObj,\r
+ uint32_t initVal\r
+)\r
+{\r
+ CSL_Bcp_encRegs* pEncRegs;\r
+\r
+ if (!pBcpLldObj || !pBcpLldObj->modCfgRegs[0])\r
+ return -1;\r
+\r
+ pEncRegs = (CSL_Bcp_encRegs *) (pBcpLldObj->modCfgRegs[Bcp_ModuleId_ENC]);\r
+\r
+ CSL_FINS (pEncRegs->CRC16_INIT_1, BCP_ENC_CRC16_INIT_1_CRC16INIT, initVal);\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * ============================================================================\r
+ * @n@b Bcp_getEncCrc16Poly1Reg\r
+ *\r
+ * @b brief\r
+ * @n This API returns the contents of CRC16_POLY_1 register. The CRC16_POLY_1 \r
+ * register contains the CRC-16 polynomial value.\r
+ *\r
+ * @param[in] \r
+ pBcpLldObj BCP LLD instance object.\r
+\r
+ * @return int32_t\r
+ * @li -1 - Invalid BCP instance handle passed.\r
+ * @li >=0 - Contents of CRC16_POLY_1 register.\r
+ *\r
+ * @pre\r
+ * @n @a Bcp_lldOpen () must be called to obtain the register overlay handle for \r
+ * BCP instance before calling this API. \r
+ *\r
+ * @post\r
+ * @n None.\r
+ * ============================================================================\r
+ */\r
+static inline int32_t Bcp_getEncCrc16Poly1Reg \r
+(\r
+ Bcp_LldObj* pBcpLldObj\r
+)\r
+{\r
+ CSL_Bcp_encRegs* pEncRegs;\r
+\r
+ if (!pBcpLldObj || !pBcpLldObj->modCfgRegs[0])\r
+ return -1;\r
+\r
+ pEncRegs = (CSL_Bcp_encRegs *) (pBcpLldObj->modCfgRegs[Bcp_ModuleId_ENC]);\r
+\r
+ return CSL_FEXT (pEncRegs->CRC16_POLY_1, BCP_ENC_CRC16_POLY_1_CRC16POLY);\r
+}\r
+\r
+/**\r
+ * ============================================================================\r
+ * @n@b Bcp_setEncCrc16Poly1Reg\r
+ *\r
+ * @b brief\r
+ * @n This API populates the contents of CRC16_POLY_1 register. The CRC16_POLY_1 \r
+ * register contains the CRC-16 polynomial value.\r
+ *\r
+ * @param[in] \r
+ pBcpLldObj BCP LLD instance object.\r
+\r
+ * @param[in] \r
+ polyVal Value to configure in CRC16_POLY_1 register.\r
+\r
+ * @return int32_t\r
+ * @li -1 - Invalid BCP instance handle passed.\r
+ * @li 0 - Success.\r
+ *\r
+ * @pre\r
+ * @n @a Bcp_lldOpen () must be called to obtain the register overlay handle for \r
+ * BCP instance before calling this API. \r
+ *\r
+ * @post\r
+ * @n CRC16_POLY_1 register configured.\r
+ * ============================================================================\r
+ */\r
+static inline int32_t Bcp_setEncCrc16Poly1Reg \r
+(\r
+ Bcp_LldObj* pBcpLldObj,\r
+ uint32_t polyVal\r
+)\r
+{\r
+ CSL_Bcp_encRegs* pEncRegs;\r
+\r
+ if (!pBcpLldObj || !pBcpLldObj->modCfgRegs[0])\r
+ return -1;\r
+\r
+ pEncRegs = (CSL_Bcp_encRegs *) (pBcpLldObj->modCfgRegs[Bcp_ModuleId_ENC]);\r
+\r
+ CSL_FINS (pEncRegs->CRC16_POLY_1, BCP_ENC_CRC16_POLY_1_CRC16POLY, polyVal);\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * ============================================================================\r
+ * @n@b Bcp_getEncScrInit2Reg\r
+ *\r
+ * @b brief\r
+ * @n This API returns the contents of SCR_INIT_2 register. The SCR_INIT_2 \r
+ * register contains the WiMax randomizer initialization value.\r
+ *\r
+ * @param[in] \r
+ pBcpLldObj BCP LLD instance object.\r
+\r
+ * @return int32_t\r
+ * @li -1 - Invalid BCP instance handle passed.\r
+ * @li >=0 - Contents of SCR_INIT_2 register.\r
+ *\r
+ * @pre\r
+ * @n @a Bcp_lldOpen () must be called to obtain the register overlay handle for \r
+ * BCP instance before calling this API. \r
+ *\r
+ * @post\r
+ * @n None.\r
+ * ============================================================================\r
+ */\r
+static inline int32_t Bcp_getEncScrInit2Reg \r
+(\r
+ Bcp_LldObj* pBcpLldObj\r
+)\r
+{\r
+ CSL_Bcp_encRegs* pEncRegs;\r
+\r
+ if (!pBcpLldObj || !pBcpLldObj->modCfgRegs[0])\r
+ return -1;\r
+\r
+ pEncRegs = (CSL_Bcp_encRegs *) (pBcpLldObj->modCfgRegs[Bcp_ModuleId_ENC]);\r
+\r
+ return CSL_FEXT (pEncRegs->SCR_INIT_2, BCP_ENC_SCR_INIT_2_SCRINIT);\r
+}\r
+\r
+/**\r
+ * ============================================================================\r
+ * @n@b Bcp_setEncScrInit2Reg\r
+ *\r
+ * @b brief\r
+ * @n This API populates the contents of SCR_INIT_2 register. The SCR_INIT_2 \r
+ * register contains the WiMax randomizer initialization value.\r
+ *\r
+ * @param[in] \r
+ pBcpLldObj BCP LLD instance object.\r
+\r
+ * @param[in] \r
+ initVal Value to configure in SCR_INIT_2 register.\r
+\r
+ * @return int32_t\r
+ * @li -1 - Invalid BCP instance handle passed.\r
+ * @li 0 - Success.\r
+ *\r
+ * @pre\r
+ * @n @a Bcp_lldOpen () must be called to obtain the register overlay handle for \r
+ * BCP instance before calling this API. \r
+ *\r
+ * @post\r
+ * @n SCR_INIT_2 register configured.\r
+ * ============================================================================\r
+ */\r
+static inline int32_t Bcp_setEncScrInit2Reg \r
+(\r
+ Bcp_LldObj* pBcpLldObj,\r
+ uint32_t initVal\r
+)\r
+{\r
+ CSL_Bcp_encRegs* pEncRegs;\r
+\r
+ if (!pBcpLldObj || !pBcpLldObj->modCfgRegs[0])\r
+ return -1;\r
+\r
+ pEncRegs = (CSL_Bcp_encRegs *) (pBcpLldObj->modCfgRegs[Bcp_ModuleId_ENC]);\r
+\r
+ CSL_FINS (pEncRegs->SCR_INIT_2, BCP_ENC_SCR_INIT_2_SCRINIT, initVal);\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * ============================================================================\r
+ * @n@b Bcp_getEncScrPoly2Reg\r
+ *\r
+ * @b brief\r
+ * @n This API returns the contents of SCR_POLY_2 register. The SCR_POLY_2 \r
+ * register contains the WiMax randomizer polynomial value.\r
+ *\r
+ * @param[in] \r
+ pBcpLldObj BCP LLD instance object.\r
+\r
+ * @return int32_t\r
+ * @li -1 - Invalid BCP instance handle passed.\r
+ * @li >=0 - Contents of SCR_POLY_2 register.\r
+ *\r
+ * @pre\r
+ * @n @a Bcp_lldOpen () must be called to obtain the register overlay handle for \r
+ * BCP instance before calling this API. \r
+ *\r
+ * @post\r
+ * @n None.\r
+ * ============================================================================\r
+ */\r
+static inline int32_t Bcp_getEncScrPoly2Reg \r
+(\r
+ Bcp_LldObj* pBcpLldObj\r
+)\r
+{\r
+ CSL_Bcp_encRegs* pEncRegs;\r
+\r
+ if (!pBcpLldObj || !pBcpLldObj->modCfgRegs[0])\r
+ return -1;\r
+\r
+ pEncRegs = (CSL_Bcp_encRegs *) (pBcpLldObj->modCfgRegs[Bcp_ModuleId_ENC]);\r
+\r
+ return CSL_FEXT (pEncRegs->SCR_POLY_2, BCP_ENC_SCR_POLY_2_SCRPOLY);\r
+}\r
+\r
+/**\r
+ * ============================================================================\r
+ * @n@b Bcp_setEncScrPoly2Reg\r
+ *\r
+ * @b brief\r
+ * @n This API populates the contents of SCR_POLY_2 register. The SCR_POLY_2 \r
+ * register contains the WiMax randomizer polynomial value.\r
+ *\r
+ * @param[in] \r
+ pBcpLldObj BCP LLD instance object.\r
+\r
+ * @param[in] \r
+ polyVal Value to configure in SCR_POLY_2 register.\r
+\r
+ * @return int32_t\r
+ * @li -1 - Invalid BCP instance handle passed.\r
+ * @li 0 - Success.\r
+ *\r
+ * @pre\r
+ * @n @a Bcp_lldOpen () must be called to obtain the register overlay handle for \r
+ * BCP instance before calling this API. \r
+ *\r
+ * @post\r
+ * @n SCR_POLY_2 register configured.\r
+ * ============================================================================\r
+ */\r
+static inline int32_t Bcp_setEncScrPoly2Reg \r
+(\r
+ Bcp_LldObj* pBcpLldObj,\r
+ uint32_t polyVal\r
+)\r
+{\r
+ CSL_Bcp_encRegs* pEncRegs;\r
+\r
+ if (!pBcpLldObj || !pBcpLldObj->modCfgRegs[0])\r
+ return -1;\r
+\r
+ pEncRegs = (CSL_Bcp_encRegs *) (pBcpLldObj->modCfgRegs[Bcp_ModuleId_ENC]);\r
+\r
+ CSL_FINS (pEncRegs->SCR_POLY_2, BCP_ENC_SCR_POLY_2_SCRPOLY, polyVal);\r
+\r
+ return 0;\r
+}\r
+\r
+/****************** Correlation Engine MMR ******************/\r
+\r
+/**\r
+ * ============================================================================\r
+ * @n@b Bcp_getCorReedMullerTableColumn\r
+ *\r
+ * @b brief\r
+ * @n This API returns the contents of M register. Each of the M register \r
+ * corresponds to a Reed Muller Table column.\r
+ *\r
+ * @param[in] \r
+ pBcpLldObj BCP LLD instance object.\r
+\r
+ * @param[in] \r
+ colNum Column number to be read.\r
+\r
+ * @return int32_t\r
+ * @li -1 - Invalid BCP instance handle passed.\r
+ * @li >=0 - Contents of M register corresponding to the\r
+ * column number specified.\r
+ *\r
+ * @pre\r
+ * @n @a Bcp_lldOpen () must be called to obtain the register overlay handle for \r
+ * BCP instance before calling this API. \r
+ *\r
+ * @post\r
+ * @n None.\r
+ * ============================================================================\r
+ */\r
+static inline int32_t Bcp_getCorReedMullerTableColumn\r
+(\r
+ Bcp_LldObj* pBcpLldObj,\r
+ uint32_t colNum\r
+)\r
+{\r
+ CSL_Bcp_corRegs* pCorRegs;\r
+ int32_t retVal;\r
+\r
+ if (!pBcpLldObj || !pBcpLldObj->modCfgRegs[0])\r
+ return -1;\r
+\r
+ pCorRegs = (CSL_Bcp_corRegs *) (pBcpLldObj->modCfgRegs[Bcp_ModuleId_COR]);\r
+\r
+ switch(colNum)\r
+ {\r
+ case 0:\r
+ retVal = CSL_FEXT (pCorRegs->M0, BCP_COR_M0_MOD_EN);\r
+ break;\r
+ case 1:\r
+ retVal = CSL_FEXT (pCorRegs->M1, BCP_COR_M1_MOD_EN);\r
+ break;\r
+ case 2:\r
+ retVal = CSL_FEXT (pCorRegs->M2, BCP_COR_M2_MOD_EN);\r
+ break;\r
+ case 3:\r
+ retVal = CSL_FEXT (pCorRegs->M3, BCP_COR_M3_MOD_EN);\r
+ break;\r
+ case 4:\r
+ retVal = CSL_FEXT (pCorRegs->M4, BCP_COR_M4_MOD_EN);\r
+ break;\r
+ case 5:\r
+ retVal = CSL_FEXT (pCorRegs->M5, BCP_COR_M5_MOD_EN);\r
+ break;\r
+ case 6:\r
+ retVal = CSL_FEXT (pCorRegs->M6, BCP_COR_M6_MOD_EN);\r
+ break;\r
+ case 7:\r
+ retVal = CSL_FEXT (pCorRegs->M7, BCP_COR_M7_MOD_EN);\r
+ break;\r
+ case 8:\r
+ retVal = CSL_FEXT (pCorRegs->M8, BCP_COR_M8_MOD_EN);\r
+ break;\r
+ case 9:\r
+ retVal = CSL_FEXT (pCorRegs->M9, BCP_COR_M9_MOD_EN);\r
+ break;\r
+ case 10:\r
+ retVal = CSL_FEXT (pCorRegs->M10, BCP_COR_M10_MOD_EN);\r
+ break;\r
+ case 11:\r
+ retVal = CSL_FEXT (pCorRegs->M11, BCP_COR_M11_MOD_EN);\r
+ break;\r
+ case 12:\r
+ retVal = CSL_FEXT (pCorRegs->M12, BCP_COR_M12_MOD_EN);\r
+ break;\r
+ default:\r
+ retVal = 0; \r
+ break;\r
+ }\r
+\r
+ return retVal;\r
+}\r
+\r
+/**\r
+ * ============================================================================\r
+ * @n@b Bcp_setCorReedMullerTableColumn\r
+ *\r
+ * @b brief\r
+ * @n This API populates the contents of M register. Each of the M register \r
+ * corresponds to a Reed Muller Table column.\r
+ *\r
+ * @param[in] \r
+ pBcpLldObj BCP LLD instance object.\r
+\r
+ * @param[in] \r
+ colNum Column number to be updated.\r
+\r
+ * @param[in] \r
+ mVal Value to configure in the register.\r
+\r
+ * @return int32_t\r
+ * @li -1 - Invalid BCP instance handle passed.\r
+ * @li 0 - Success.\r
+ *\r
+ * @pre\r
+ * @n @a Bcp_lldOpen () must be called to obtain the register overlay handle for \r
+ * BCP instance before calling this API. \r
+ *\r
+ * @post\r
+ * @n M register corresponding to column number specified configured.\r
+ * ============================================================================\r
+ */\r
+static inline int32_t Bcp_setCorReedMullerTableColumn\r
+(\r
+ Bcp_LldObj* pBcpLldObj,\r
+ uint32_t colNum,\r
+ uint32_t mVal\r
+)\r
+{\r
+ CSL_Bcp_corRegs* pCorRegs;\r
+\r
+ if (!pBcpLldObj || !pBcpLldObj->modCfgRegs[0])\r
+ return -1;\r
+\r
+ pCorRegs = (CSL_Bcp_corRegs *) (pBcpLldObj->modCfgRegs[Bcp_ModuleId_COR]);\r
+\r
+ switch(colNum)\r
+ {\r
+ case 0:\r
+ CSL_FINS (pCorRegs->M0, BCP_COR_M0_MOD_EN, mVal);\r
+ break;\r
+ case 1:\r
+ CSL_FINS (pCorRegs->M1, BCP_COR_M1_MOD_EN, mVal);\r
+ break;\r
+ case 2:\r
+ CSL_FINS (pCorRegs->M2, BCP_COR_M2_MOD_EN, mVal);\r
+ break;\r
+ case 3:\r
+ CSL_FINS (pCorRegs->M3, BCP_COR_M3_MOD_EN, mVal);\r
+ break;\r
+ case 4:\r
+ CSL_FINS (pCorRegs->M4, BCP_COR_M4_MOD_EN, mVal);\r
+ break;\r
+ case 5:\r
+ CSL_FINS (pCorRegs->M5, BCP_COR_M5_MOD_EN, mVal);\r
+ break;\r
+ case 6:\r
+ CSL_FINS (pCorRegs->M6, BCP_COR_M6_MOD_EN, mVal);\r
+ break;\r
+ case 7:\r
+ CSL_FINS (pCorRegs->M7, BCP_COR_M7_MOD_EN, mVal);\r
+ break;\r
+ case 8:\r
+ CSL_FINS (pCorRegs->M8, BCP_COR_M8_MOD_EN, mVal);\r
+ break;\r
+ case 9:\r
+ CSL_FINS (pCorRegs->M9, BCP_COR_M9_MOD_EN, mVal);\r
+ break;\r
+ case 10:\r
+ CSL_FINS (pCorRegs->M10, BCP_COR_M10_MOD_EN, mVal);\r
+ break;\r
+ case 11:\r
+ CSL_FINS (pCorRegs->M11, BCP_COR_M11_MOD_EN, mVal);\r
+ break;\r
+ case 12:\r
+ CSL_FINS (pCorRegs->M12, BCP_COR_M12_MOD_EN, mVal);\r
+ break;\r
+ default: \r
+ break;\r
+ }\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * ============================================================================\r
+ * @n@b Bcp_getCorControlReg\r
+ *\r
+ * @b brief\r
+ * @n This API returns the contents of Correlation engine control register. \r
+ *\r
+ * @param[in] \r
+ pBcpLldObj BCP LLD instance object.\r
+\r
+ * @param[out] \r
+ pQpskMap00 Value read from QPSK Map 00 field.\r
+\r
+ * @param[out] \r
+ pQpskMap01 Value read from QPSK Map 01 field.\r
+\r
+ * @param[out] \r
+ pQpskMap10 Value read from QPSK Map 10 field.\r
+\r
+ * @param[out] \r
+ pQpskMap11 Value read from QPSK Map 11 field.\r
+\r
+ * @return int32_t \r
+ * @li -1 - Invalid BCP instance handle passed.\r
+ * @li 0 - Success. Correlation engine control\r
+ * contents loaded into the output params passed.\r
+ *\r
+ * @pre\r
+ * @n @a Bcp_lldOpen () must be called to obtain the register overlay handle for \r
+ * BCP instance before calling this API. \r
+ *\r
+ * @post\r
+ * @n None.\r
+ * ============================================================================\r
+ */\r
+static inline int32_t Bcp_getCorControlReg\r
+(\r
+ Bcp_LldObj* pBcpLldObj,\r
+ uint8_t* pQpskMap00,\r
+ uint8_t* pQpskMap01,\r
+ uint8_t* pQpskMap10,\r
+ uint8_t* pQpskMap11\r
+)\r
+{\r
+ CSL_Bcp_corRegs* pCorRegs;\r
+\r
+ if (!pBcpLldObj || !pBcpLldObj->modCfgRegs[0] || !pQpskMap00 || !pQpskMap01 || !pQpskMap10 || !pQpskMap11)\r
+ return -1;\r
+\r
+ pCorRegs = (CSL_Bcp_corRegs *) (pBcpLldObj->modCfgRegs[Bcp_ModuleId_COR]);\r
+\r
+ *pQpskMap00 = CSL_FEXT (pCorRegs->CONTROL_REGISTER, BCP_COR_CONTROL_REGISTER_QPSK_MAPPING_C2K10_C2K0);\r
+ *pQpskMap01 = CSL_FEXT (pCorRegs->CONTROL_REGISTER, BCP_COR_CONTROL_REGISTER_QPSK_MAPPING_C2K10_C2K1);\r
+ *pQpskMap10 = CSL_FEXT (pCorRegs->CONTROL_REGISTER, BCP_COR_CONTROL_REGISTER_QPSK_MAPPING_C2K11_C2K0);\r
+ *pQpskMap11 = CSL_FEXT (pCorRegs->CONTROL_REGISTER, BCP_COR_CONTROL_REGISTER_QPSK_MAPPING_C2K11_C2K1);\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * ============================================================================\r
+ * @n@b Bcp_setCorControlReg\r
+ *\r
+ * @b brief\r
+ * @n This API populates the contents of Correlation engine control register. \r
+ *\r
+ * @param[in] \r
+ pBcpLldObj BCP LLD instance object.\r
+\r
+ * @param[out] \r
+ qpskMap00 Value to be written to QPSK Map 00 field.\r
+\r
+ * @param[out] \r
+ qpskMap01 Value to be written to QPSK Map 01 field.\r
+\r
+ * @param[out] \r
+ qpskMap10 Value to be written to QPSK Map 10 field.\r
+\r
+ * @param[out] \r
+ qpskMap11 Value to be written to QPSK Map 11 field.\r
+\r
+ * @return int32_t\r
+ * @li -1 - Invalid BCP instance handle passed.\r
+ * @li 0 - Correlation engine Control register \r
+ * succesfully configured.\r
+ *\r
+ * @pre\r
+ * @n @a Bcp_lldOpen () must be called to obtain the register overlay handle for \r
+ * BCP instance before calling this API. \r
+ *\r
+ * @post\r
+ * @n Correlation engine control register CONTROL configured.\r
+ * ============================================================================\r
+ */\r
+static inline int32_t Bcp_setCorControlReg\r
+(\r
+ Bcp_LldObj* pBcpLldObj,\r
+ uint8_t qpskMap00,\r
+ uint8_t qpskMap01,\r
+ uint8_t qpskMap10,\r
+ uint8_t qpskMap11\r
+)\r
+{\r
+ CSL_Bcp_corRegs* pCorRegs;\r
+\r
+ if (!pBcpLldObj || !pBcpLldObj->modCfgRegs[0])\r
+ return -1;\r
+\r
+ pCorRegs = (CSL_Bcp_corRegs *) (pBcpLldObj->modCfgRegs[Bcp_ModuleId_COR]);\r
+\r
+ CSL_FINS (pCorRegs->CONTROL_REGISTER, BCP_COR_CONTROL_REGISTER_QPSK_MAPPING_C2K10_C2K0, qpskMap00);\r
+ CSL_FINS (pCorRegs->CONTROL_REGISTER, BCP_COR_CONTROL_REGISTER_QPSK_MAPPING_C2K10_C2K1, qpskMap01);\r
+ CSL_FINS (pCorRegs->CONTROL_REGISTER, BCP_COR_CONTROL_REGISTER_QPSK_MAPPING_C2K11_C2K0, qpskMap10);\r
+ CSL_FINS (pCorRegs->CONTROL_REGISTER, BCP_COR_CONTROL_REGISTER_QPSK_MAPPING_C2K11_C2K1, qpskMap11);\r
+\r
+ return 0;\r
+}\r
+\r
+/****************** Traffic Manager MMR ******************/\r
+\r
+/**\r
+ * ============================================================================\r
+ * @n@b Bcp_getPIDReg\r
+ *\r
+ * @b brief\r
+ * @n This API returns the contents of BCP PID Register.\r
+ *\r
+ * @param[in] \r
+ pBcpLldObj BCP LLD instance object.\r
+\r
+ * @param[out] \r
+ pPIDParams BCP PID Params object handle.\r
+\r
+ * @return int32_t\r
+ * @li -1 - Invalid BCP instance handle passed.\r
+ * @li >=0 - Contents of BCP PID register.\r
+ *\r
+ * @pre\r
+ * @n @a Bcp_lldOpen () must be called to obtain the register overlay handle for \r
+ * BCP instance before calling this API. \r
+ *\r
+ * @post\r
+ * @n None.\r
+ * ============================================================================\r
+ */\r
+static inline int32_t Bcp_getPIDReg \r
+(\r
+ Bcp_LldObj* pBcpLldObj,\r
+ Bcp_PeripheralIdParams* pPIDParams\r
+)\r
+{\r
+ CSL_Bcp_tmRegs* pTmRegs;\r
+\r
+ if (!pBcpLldObj || !pBcpLldObj->modCfgRegs[0] || !pPIDParams)\r
+ return -1;\r
+\r
+ pTmRegs = (CSL_Bcp_tmRegs *) (pBcpLldObj->modCfgRegs[Bcp_ModuleId_TM]);\r
+\r
+ pPIDParams->minorNum = CSL_FEXT (pTmRegs->BCP_PID, BCP_TM_BCP_PID_BCP_PID_MINOR);\r
+ pPIDParams->customNum = CSL_FEXT (pTmRegs->BCP_PID, BCP_TM_BCP_PID_BCP_PID_CUSTOM);\r
+ pPIDParams->majorNum = CSL_FEXT (pTmRegs->BCP_PID, BCP_TM_BCP_PID_BCP_PID_MAJOR);\r
+ pPIDParams->rtlVersion = CSL_FEXT (pTmRegs->BCP_PID, BCP_TM_BCP_PID_BCP_PID_RTL);\r
+ pPIDParams->function = CSL_FEXT (pTmRegs->BCP_PID, BCP_TM_BCP_PID_BCP_PID_FUNC);\r
+ pPIDParams->scheme = CSL_FEXT (pTmRegs->BCP_PID, BCP_TM_BCP_PID_BCP_PID_SCHEME);\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * ============================================================================\r
+ * @n@b Bcp_doSoftwareReset\r
+ *\r
+ * @b brief\r
+ * @n This API configures the BCP Soft Reset Register element "soft_rst" to\r
+ * perform a software reset on the entire BCP engine other than the\r
+ * CDMAHP and VBUSM interfaces.\r
+ * \r
+ * @param[in] \r
+ pBcpLldObj BCP LLD instance object.\r
+ * \r
+ * @return int32_t\r
+ * @li -1 - Invalid BCP instance handle passed.\r
+ * @li 0 - Software reset succesfully initiated.\r
+ *\r
+ * @pre\r
+ * @n @a Bcp_lldOpen () must be called to obtain the register overlay handle for \r
+ * BCP instance before calling this API.\r
+ *\r
+ * @post\r
+ * @n BCP Soft Reset Register's 'software reset' bit configured\r
+ * ============================================================================\r
+ */\r
+static inline int32_t Bcp_doSoftwareReset \r
+(\r
+ Bcp_LldObj* pBcpLldObj\r
+)\r
+{\r
+ CSL_Bcp_tmRegs* pTmRegs;\r
+\r
+ if (!pBcpLldObj || !pBcpLldObj->modCfgRegs[0])\r
+ return -1;\r
+\r
+ pTmRegs = (CSL_Bcp_tmRegs *) (pBcpLldObj->modCfgRegs[Bcp_ModuleId_TM]);\r
+\r
+ CSL_FINS (pTmRegs->BCP_SOFT_RESET, BCP_TM_BCP_SOFT_RESET_SOFT_RESET, 1); \r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * ============================================================================\r
+ * @n@b Bcp_doSoftResetRxTeardown\r
+ *\r
+ * @b brief\r
+ * @n This API configures the BCP Soft Reset Register element "Rx_teardown"\r
+ * to stop processing any packets in Rx path. If a port had an active\r
+ * packet it will send an EOP word to the QFIFO to finish off the packet\r
+ * to the CDMAHP.\r
+ * \r
+ * @param[in] \r
+ pBcpLldObj BCP LLD instance object.\r
+ * \r
+ * @return int32_t\r
+ * @li -1 - Invalid BCP instance handle passed.\r
+ * @li 0 - Rx Teardown succesfully initiated.\r
+ *\r
+ * @pre\r
+ * @n @a Bcp_lldOpen () must be called to obtain the register overlay handle for \r
+ * BCP instance before calling this API.\r
+ *\r
+ * @post\r
+ * @n BCP Soft Reset Register's bits configured as passed.\r
+ * ============================================================================\r
+ */\r
+static inline int32_t Bcp_doSoftResetRxTeardown\r
+(\r
+ Bcp_LldObj* pBcpLldObj\r
+)\r
+{\r
+ CSL_Bcp_tmRegs* pTmRegs;\r
+\r
+ if (!pBcpLldObj || !pBcpLldObj->modCfgRegs[0])\r
+ return -1;\r
+\r
+ pTmRegs = (CSL_Bcp_tmRegs *) (pBcpLldObj->modCfgRegs[Bcp_ModuleId_TM]);\r
+\r
+ CSL_FINS (pTmRegs->BCP_SOFT_RESET, BCP_TM_BCP_SOFT_RESET_RX_TEARDOWN, 1); \r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * ============================================================================\r
+ * @n@b Bcp_doSoftResetTxTeardown\r
+ *\r
+ * @b brief\r
+ * @n This API configures the BCP Soft Reset Register element "Tx_teardown"\r
+ * to stop passing CDMAHP data to the QFIFOs in Tx path. Any CDMAHP Tx\r
+ * queue that has data will be read with the data dropped so the CDMAHP\r
+ * can process the full packet.\r
+ * \r
+ * @param[in] \r
+ pBcpLldObj BCP LLD instance object.\r
+ * \r
+ * @return int32_t\r
+ * @li -1 - Invalid BCP instance handle passed.\r
+ * @li 0 - Tx Teardown succesfully initiated.\r
+ *\r
+ * @pre\r
+ * @n @a Bcp_lldOpen () must be called to obtain the register overlay handle for \r
+ * BCP instance before calling this API.\r
+ *\r
+ * @post\r
+ * @n BCP Soft Reset Register's bits configured as passed.\r
+ * ============================================================================\r
+ */\r
+static inline int32_t Bcp_doSoftResetTxTeardown\r
+(\r
+ Bcp_LldObj* pBcpLldObj\r
+)\r
+{\r
+ CSL_Bcp_tmRegs* pTmRegs;\r
+\r
+ if (!pBcpLldObj || !pBcpLldObj->modCfgRegs[0])\r
+ return -1;\r
+\r
+ pTmRegs = (CSL_Bcp_tmRegs *) (pBcpLldObj->modCfgRegs[Bcp_ModuleId_TM]);\r
+\r
+ CSL_FINS (pTmRegs->BCP_SOFT_RESET, BCP_TM_BCP_SOFT_RESET_TX_TEARDOWN, 1);\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * ============================================================================\r
+ * @n@b Bcp_doSoftResetClockGateDisable\r
+ *\r
+ * @b brief\r
+ * @n This API configures the BCP Soft Reset Register element "clkgate_disable"\r
+ * to disable the clock gating done by PPBs when the engines are idle.\r
+ * \r
+ * @param[in] \r
+ pBcpLldObj BCP LLD instance object.\r
+ * \r
+ * @return int32_t\r
+ * @li -1 - Invalid BCP instance handle passed.\r
+ * @li 0 - Clock Gate disable succesfully initiated.\r
+ *\r
+ * @pre\r
+ * @n @a Bcp_lldOpen () must be called to obtain the register overlay handle for \r
+ * BCP instance before calling this API.\r
+ *\r
+ * @post\r
+ * @n BCP Soft Reset Register's bits configured as passed.\r
+ * ============================================================================\r
+ */\r
+static inline int32_t Bcp_doSoftResetClockGateDisable\r
+(\r
+ Bcp_LldObj* pBcpLldObj\r
+)\r
+{\r
+ CSL_Bcp_tmRegs* pTmRegs;\r
+\r
+ if (!pBcpLldObj || !pBcpLldObj->modCfgRegs[0])\r
+ return -1;\r
+\r
+ pTmRegs = (CSL_Bcp_tmRegs *) (pBcpLldObj->modCfgRegs[Bcp_ModuleId_TM]);\r
+\r
+ CSL_FINS (pTmRegs->BCP_SOFT_RESET, BCP_TM_BCP_SOFT_RESET_CLKGATE_DISABLE, 1);\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * ============================================================================\r
+ * @n@b Bcp_clearTMHalt\r
+ *\r
+ * @b brief\r
+ * @n Given a BCP Tx Queue Number, this API sets the "clear_halt" bit \r
+ * corresponding to it in the TM_HALT_CTRL register. This in turn\r
+ * clears the halt for the corresponding queue.\r
+ * \r
+ * @param[in] \r
+ pBcpLldObj BCP LLD instance object.\r
+\r
+ * @param[in] \r
+ txQNum BCP Tx Queue Number for which the TM halt bit must\r
+ be cleared.\r
+ * \r
+ * @return int32_t\r
+ * @li -1 - Invalid BCP instance handle passed.\r
+ * @li 0 - Success.\r
+ *\r
+ * @pre\r
+ * @n @a Bcp_lldOpen () must be called to obtain the register overlay handle for \r
+ * BCP instance before calling this API.\r
+ *\r
+ * @post\r
+ * @n BCP TM Halt Control Register's 'clear_halt' bit set to initiate a clear operation.\r
+ * ============================================================================\r
+ */\r
+static inline int32_t Bcp_clearTMHalt \r
+(\r
+ Bcp_LldObj* pBcpLldObj,\r
+ Bcp_QueueId txQNum\r
+)\r
+{\r
+ CSL_Bcp_tmRegs* pTmRegs;\r
+\r
+ if (!pBcpLldObj || !pBcpLldObj->modCfgRegs[0])\r
+ return -1;\r
+\r
+ pTmRegs = (CSL_Bcp_tmRegs *) (pBcpLldObj->modCfgRegs[Bcp_ModuleId_TM]);\r
+\r
+ CSL_FINSR (pTmRegs->TM_HALT_CTRL, txQNum, txQNum, 1); \r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * ============================================================================\r
+ * @n@b Bcp_getTMHaltStatus\r
+ *\r
+ * @b brief\r
+ * @n This API returns the contents of BCP TM Halt Status register (TM_HALT_STATUS).\r
+ *\r
+ * @param[in] \r
+ pBcpLldObj BCP LLD instance object.\r
+\r
+ * @return int32_t\r
+ * @li -1 - Invalid BCP instance handle passed.\r
+ * @li >=0 - Contents of TM_HALT_STATUS register.\r
+ *\r
+ * @pre\r
+ * @n @a Bcp_lldOpen () must be called to obtain the register overlay handle for \r
+ * BCP instance before calling this API. \r
+ *\r
+ * @post\r
+ * @n None.\r
+ * ============================================================================\r
+ */\r
+static inline int32_t Bcp_getTMHaltStatus \r
+(\r
+ Bcp_LldObj* pBcpLldObj\r
+)\r
+{\r
+ CSL_Bcp_tmRegs* pTmRegs;\r
+\r
+ if (!pBcpLldObj || !pBcpLldObj->modCfgRegs[0])\r
+ return -1;\r
+\r
+ pTmRegs = (CSL_Bcp_tmRegs *) (pBcpLldObj->modCfgRegs[Bcp_ModuleId_TM]);\r
+\r
+ return CSL_FEXT (pTmRegs->TM_HALT_STATUS, BCP_TM_TM_HALT_STATUS_HALT_STATUS);\r
+}\r
+\r
+/**\r
+ * ============================================================================\r
+ * @n@b Bcp_getEmulationClockStopStatus\r
+ *\r
+ * @b brief\r
+ * @n This API returns the contents of BCP Emulation clock stop status register.\r
+ * The contents of register indicate the idle status of each of the BCP \r
+ * sub-modules.\r
+ *\r
+ * @param[in] \r
+ pBcpLldObj BCP LLD instance object.\r
+\r
+ * @param[out] \r
+ pIdleStatus Structure to be filled with the Idle status read \r
+ from H/w.\r
+\r
+ * @return int32_t\r
+ * @li -1 - Invalid BCP instance handle passed.\r
+ * @li 0 - Success.\r
+ *\r
+ * @pre\r
+ * @n @a Bcp_lldOpen () must be called to obtain the register overlay handle for \r
+ * BCP instance before calling this API. \r
+ *\r
+ * @post\r
+ * @n None.\r
+ * ============================================================================\r
+ */\r
+static inline int32_t Bcp_getEmulationClockStopStatus \r
+(\r
+ Bcp_LldObj* pBcpLldObj,\r
+ Bcp_ModuleIdleStatus* pIdleStatus\r
+)\r
+{\r
+ CSL_Bcp_tmRegs* pTmRegs;\r
+ uint32_t word;\r
+\r
+ if (!pBcpLldObj || !pIdleStatus || !pBcpLldObj->modCfgRegs[0])\r
+ return -1;\r
+\r
+ pTmRegs = (CSL_Bcp_tmRegs *) (pBcpLldObj->modCfgRegs[Bcp_ModuleId_TM]);\r
+ word = pTmRegs->BCP_EMU_CLKSTOP_STATUS;\r
+\r
+ pIdleStatus->tm_idle_status = CSL_FEXT (word, BCP_TM_BCP_EMU_CLKSTOP_STATUS_TM_ENG_IDLE);\r
+ pIdleStatus->dio_idle_status = CSL_FEXT (word, BCP_TM_BCP_EMU_CLKSTOP_STATUS_DIO_ENG_IDLE);\r
+ pIdleStatus->crc_idle_status = CSL_FEXT (word, BCP_TM_BCP_EMU_CLKSTOP_STATUS_CRC_ENG_IDLE);\r
+ pIdleStatus->enc_idle_status = CSL_FEXT (word, BCP_TM_BCP_EMU_CLKSTOP_STATUS_ENC_ENG_IDLE);\r
+ pIdleStatus->rm_idle_status = CSL_FEXT (word, BCP_TM_BCP_EMU_CLKSTOP_STATUS_RM_ENG_IDLE);\r
+ pIdleStatus->mod_idle_status = CSL_FEXT (word, BCP_TM_BCP_EMU_CLKSTOP_STATUS_MOD_ENG_IDLE);\r
+ pIdleStatus->int_idle_status = CSL_FEXT (word, BCP_TM_BCP_EMU_CLKSTOP_STATUS_INT_ENG_IDLE);\r
+ pIdleStatus->cor_idle_status = CSL_FEXT (word, BCP_TM_BCP_EMU_CLKSTOP_STATUS_COR_ENG_IDLE);\r
+ pIdleStatus->ssl_idle_status = CSL_FEXT (word, BCP_TM_BCP_EMU_CLKSTOP_STATUS_SSL_ENG_IDLE);\r
+ pIdleStatus->rd_idle_status = CSL_FEXT (word, BCP_TM_BCP_EMU_CLKSTOP_STATUS_RD_ENG_IDLE);\r
+ pIdleStatus->dnt_idle_status = CSL_FEXT (word, BCP_TM_BCP_EMU_CLKSTOP_STATUS_DNT_ENG_IDLE);\r
+ pIdleStatus->all_idle_status = CSL_FEXT (word, BCP_TM_BCP_EMU_CLKSTOP_STATUS_ALL_ENG_IDLE);\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * ============================================================================\r
+ * @n@b Bcp_getEmulationClockStopControlReg\r
+ *\r
+ * @b brief\r
+ * @n This API returns the contents of BCP Emulation clock control stop register.\r
+ *\r
+ * @param[in] \r
+ pBcpLldObj BCP LLD instance object.\r
+\r
+ * @param[out] \r
+ pEmuRtSel Holds emulation suspend signal selection bit.\r
+\r
+ * @param[out] \r
+ pEmuFreeRun Indicates if the hardware responds to/ignores the emulation\r
+ suspend signal.\r
+\r
+ * @return int32_t\r
+ * @li -1 - Invalid BCP instance handle passed.\r
+ * @li 0 - Success.\r
+ *\r
+ * @pre\r
+ * @n @a Bcp_lldOpen () must be called to obtain the register overlay handle for \r
+ * BCP instance before calling this API. \r
+ *\r
+ * @post\r
+ * @n None.\r
+ * ============================================================================\r
+ */\r
+static inline int32_t Bcp_getEmulationClockStopControlReg \r
+(\r
+ Bcp_LldObj* pBcpLldObj,\r
+ uint8_t* pEmuRtSel,\r
+ uint8_t* pEmuFreeRun\r
+)\r
+{\r
+ CSL_Bcp_tmRegs* pTmRegs;\r
+\r
+ if (!pBcpLldObj || !pBcpLldObj->modCfgRegs[0] || !pEmuRtSel || !pEmuFreeRun)\r
+ return -1;\r
+\r
+ pTmRegs = (CSL_Bcp_tmRegs *) (pBcpLldObj->modCfgRegs[Bcp_ModuleId_TM]);\r
+\r
+ *pEmuRtSel = CSL_FEXT (pTmRegs->BCP_EMU_CLKSTOP_CTRL, BCP_TM_BCP_EMU_CLKSTOP_CTRL_BCP_EMU_RT_SEL);\r
+ *pEmuFreeRun= CSL_FEXT (pTmRegs->BCP_EMU_CLKSTOP_CTRL, BCP_TM_BCP_EMU_CLKSTOP_CTRL_BCP_EMU_FREERUN);\r
+\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * ============================================================================\r
+ * @n@b Bcp_setEmulationClockStopControlReg\r
+ *\r
+ * @b brief\r
+ * @n This API sets up the contents of BCP Emulation clock control stop register.\r
+ *\r
+ * @param[in] \r
+ pBcpLldObj BCP LLD instance object.\r
+\r
+ * @param[in] \r
+ emuRtSel Emulation suspend signal selection to configure. Set to\r
+ 0 for BCP to monitor "emu_dbgsusp" signal and 1 for \r
+ BCP to monitor "emu_dbgsusp_rt" signal.\r
+\r
+ * @param[in] \r
+ emuFreeRun Set to 0 for BCP to act upon the emulation suspend\r
+ signal and to 1 for BCP to ignore the signal and \r
+ run normally.\r
+\r
+ * @return int32_t\r
+ * @li -1 - Invalid BCP instance handle passed.\r
+ * @li 0 - Success.\r
+ *\r
+ * @pre\r
+ * @n @a Bcp_lldOpen () must be called to obtain the register overlay handle for \r
+ * BCP instance before calling this API. \r
+ *\r
+ * @post\r
+ * @n None.\r
+ * ============================================================================\r
+ */\r
+static inline int32_t Bcp_setEmulationClockStopControlReg \r
+(\r
+ Bcp_LldObj* pBcpLldObj,\r
+ uint8_t emuRtSel,\r
+ uint8_t emuFreeRun\r
+)\r
+{\r
+ CSL_Bcp_tmRegs* pTmRegs;\r
+\r
+ if (!pBcpLldObj || !pBcpLldObj->modCfgRegs[0])\r
+ return -1;\r
+\r
+ pTmRegs = (CSL_Bcp_tmRegs *) (pBcpLldObj->modCfgRegs[Bcp_ModuleId_TM]);\r
+ \r
+ pTmRegs->BCP_EMU_CLKSTOP_CTRL = CSL_FMK (BCP_TM_BCP_EMU_CLKSTOP_CTRL_BCP_EMU_RT_SEL, emuRtSel) |\r
+ CSL_FMK (BCP_TM_BCP_EMU_CLKSTOP_CTRL_BCP_EMU_FREERUN, emuFreeRun);\r
+\r
+ return 0;\r
+}\r
+\r
+\r
+/**\r
+ * ============================================================================\r
+ * @n@b Bcp_getDlgSwTimeStampReg\r
+ *\r
+ * @b brief\r
+ * @n This API returns the contents of BCP Data logger Software time stamp\r
+ * register.\r
+ *\r
+ * @param[in] \r
+ pBcpLldObj BCP LLD instance object.\r
+\r
+ * @return int32_t\r
+ * @li -1 - Invalid BCP instance handle passed.\r
+ * @li >=0 - Contents of BCP_DLG_SW_TIMESTAMP register.\r
+ *\r
+ * @pre\r
+ * @n @a Bcp_lldOpen () must be called to obtain the register overlay handle for \r
+ * BCP instance before calling this API. \r
+ *\r
+ * @post\r
+ * @n BCP_DLG_SW_TIMESTAMP register configured.\r
+ * ============================================================================\r
+ */\r
+static inline int32_t Bcp_getDlgSwTimeStampReg \r
+(\r
+ Bcp_LldObj* pBcpLldObj\r
+)\r
+{\r
+ CSL_Bcp_tmRegs* pTmRegs;\r
+\r
+ if (!pBcpLldObj || !pBcpLldObj->modCfgRegs[0])\r
+ return -1;\r
+\r
+ pTmRegs = (CSL_Bcp_tmRegs *) (pBcpLldObj->modCfgRegs[Bcp_ModuleId_TM]);\r
+ \r
+ return CSL_FEXT (pTmRegs->BCP_DLG_SW_TIMESTAMP, BCP_TM_BCP_DLG_SW_TIMESTAMP_BCP_DLG_SW_TIMESTAMP);\r
+}\r
+\r
+/**\r
+ * ============================================================================\r
+ * @n@b Bcp_setDlgSwTimeStampReg\r
+ *\r
+ * @b brief\r
+ * @n This API populates the contents of BCP Data logger Software time stamp\r
+ * register.\r
+ *\r
+ * @param[in] \r
+ pBcpLldObj BCP LLD instance object.\r
+\r
+ * @param[in] \r
+ tsVal Software timestamp value to configure in BCP_DLG_SW_TIMESTAMP\r
+ register.\r
+\r
+ * @return int32_t\r
+ * @li -1 - Invalid BCP instance handle passed.\r
+ * @li 0 - Success.\r
+ *\r
+ * @pre\r
+ * @n @a Bcp_lldOpen () must be called to obtain the register overlay handle for \r
+ * BCP instance before calling this API. \r
+ *\r
+ * @post\r
+ * @n None.\r
+ * ============================================================================\r
+ */\r
+static inline int32_t Bcp_setDlgSwTimeStampReg \r
+(\r
+ Bcp_LldObj* pBcpLldObj,\r
+ uint32_t tsVal\r
+)\r
+{\r
+ CSL_Bcp_tmRegs* pTmRegs;\r
+\r
+ if (!pBcpLldObj || !pBcpLldObj->modCfgRegs[0])\r
+ return -1;\r
+\r
+ pTmRegs = (CSL_Bcp_tmRegs *) (pBcpLldObj->modCfgRegs[Bcp_ModuleId_TM]);\r
+ \r
+ CSL_FINS (pTmRegs->BCP_DLG_SW_TIMESTAMP, BCP_TM_BCP_DLG_SW_TIMESTAMP_BCP_DLG_SW_TIMESTAMP, tsVal);\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * ============================================================================\r
+ * @n@b Bcp_getDlgHwTimeStampReg\r
+ *\r
+ * @b brief\r
+ * @n This API returns the contents of BCP Data logger Hardware time stamp\r
+ * register.\r
+ *\r
+ * @param[in] \r
+ pBcpLldObj BCP LLD instance object.\r
+\r
+ * @return int32_t\r
+ * @li -1 - Invalid BCP instance handle passed.\r
+ * @li >=0 - Contents of BCP_DLG_HW_TIMESTAMP register.\r
+ *\r
+ * @pre\r
+ * @n @a Bcp_lldOpen () must be called to obtain the register overlay handle for \r
+ * BCP instance before calling this API. \r
+ *\r
+ * @post\r
+ * @n None.\r
+ * ============================================================================\r
+ */\r
+static inline int32_t Bcp_getDlgHwTimeStampReg \r
+(\r
+ Bcp_LldObj* pBcpLldObj\r
+)\r
+{\r
+ CSL_Bcp_tmRegs* pTmRegs;\r
+\r
+ if (!pBcpLldObj || !pBcpLldObj->modCfgRegs[0])\r
+ return -1;\r
+\r
+ pTmRegs = (CSL_Bcp_tmRegs *) (pBcpLldObj->modCfgRegs[Bcp_ModuleId_TM]);\r
+ \r
+ return CSL_FEXT (pTmRegs->BCP_DLG_HW_TIMESTAMP, BCP_TM_BCP_DLG_HW_TIMESTAMP_BCP_DLG_HW_TIMESTAMP);\r
+}\r
+\r
+/**\r
+ * ============================================================================\r
+ * @n@b Bcp_resetDlgHwTimeStampReg\r
+ *\r
+ * @b brief\r
+ * @n This API initiates a reset on the Hardware timestamp control register by\r
+ * writing 1 to the BCP_DLG_HW_TIMESTAMP_CTRL register. \r
+ *\r
+ * @param[in] \r
+ pBcpLldObj BCP LLD instance object.\r
+\r
+ * @return int32_t\r
+ * @li -1 - Invalid BCP instance handle passed.\r
+ * @li 0 - Success. Hardware timestamp register contents\r
+ * reset to 0.\r
+ *\r
+ * @pre\r
+ * @n @a Bcp_lldOpen () must be called to obtain the register overlay handle for \r
+ * BCP instance before calling this API. \r
+ *\r
+ * @post\r
+ * @n Hardware timestamp register BCP_DLG_HW_TIMESTAMP reset to 0.\r
+ * ============================================================================\r
+ */\r
+static inline int32_t Bcp_resetDlgHwTimeStampReg \r
+(\r
+ Bcp_LldObj* pBcpLldObj\r
+)\r
+{\r
+ CSL_Bcp_tmRegs* pTmRegs;\r
+\r
+ if (!pBcpLldObj || !pBcpLldObj->modCfgRegs[0])\r
+ return -1;\r
+\r
+ pTmRegs = (CSL_Bcp_tmRegs *) (pBcpLldObj->modCfgRegs[Bcp_ModuleId_TM]);\r
+ \r
+ CSL_FINS (pTmRegs->BCP_DLG_HW_TIMESTAMP_CTRL, BCP_TM_BCP_DLG_HW_TIMESTAMP_CTRL_BCP_DLG_HW_TIMESTAMP_RUN, 1);\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * ============================================================================\r
+ * @n@b Bcp_setDlgHold\r
+ *\r
+ * @b brief\r
+ * @n This API puts data logger in hold state (DLG_HOLD) for all the BCP \r
+ * sub modules specified. It does so by writing 1 to the 'hold' bit in the \r
+ * BCP_DLG_HOLD_RST register corresponding to each of the modules that need\r
+ * to be put in hold.\r
+ *\r
+ * @param[in] \r
+ pBcpLldObj BCP LLD instance object.\r
+\r
+ * @param[in] \r
+ pDlgHoldCfg Hold bit configuration for all the modules. To put\r
+ a specific module in hold, set its corresponding bit\r
+ in the structure to 1 and set to 0 otherwise.\r
+\r
+ * @return int32_t\r
+ * @li -1 - Invalid BCP instance handle passed/Hold\r
+ * configuration handle passed.\r
+ * @li 0 - Success.\r
+ *\r
+ * @pre\r
+ * @n @a Bcp_lldOpen () must be called to obtain the register overlay handle for \r
+ * BCP instance before calling this API. \r
+ *\r
+ * @post\r
+ * @n 'hold' bits set to 1 in BCP_DLG_HOLD_RST register according to \r
+ * configuration specified.\r
+ * ============================================================================\r
+ */\r
+static inline int32_t Bcp_setDlgHold \r
+(\r
+ Bcp_LldObj* pBcpLldObj,\r
+ Bcp_ModuleCfg* pDlgHoldCfg\r
+)\r
+{\r
+ CSL_Bcp_tmRegs* pTmRegs;\r
+ uint16_t holdVal;\r
+\r
+ if (!pBcpLldObj || !pBcpLldObj->modCfgRegs[0] || !pDlgHoldCfg)\r
+ return -1;\r
+\r
+ pTmRegs = (CSL_Bcp_tmRegs *) (pBcpLldObj->modCfgRegs[Bcp_ModuleId_TM]);\r
+\r
+ holdVal = CSL_FMK (BCP_TM_BCP_DLG_HOLD_RST_TM_DLG_HOLD, pDlgHoldCfg->tm) |\r
+ CSL_FMK (BCP_TM_BCP_DLG_HOLD_RST_DIO_DLG_HOLD, pDlgHoldCfg->dio) |\r
+ CSL_FMK (BCP_TM_BCP_DLG_HOLD_RST_CRC_DLG_HOLD, pDlgHoldCfg->crc) |\r
+ CSL_FMK (BCP_TM_BCP_DLG_HOLD_RST_ENC_DLG_HOLD, pDlgHoldCfg->enc) |\r
+ CSL_FMK (BCP_TM_BCP_DLG_HOLD_RST_RM_DLG_HOLD, pDlgHoldCfg->rm) |\r
+ CSL_FMK (BCP_TM_BCP_DLG_HOLD_RST_MOD_DLG_HOLD, pDlgHoldCfg->mod) |\r
+ CSL_FMK (BCP_TM_BCP_DLG_HOLD_RST_INT_DLG_HOLD, pDlgHoldCfg->intleaver) |\r
+ CSL_FMK (BCP_TM_BCP_DLG_HOLD_RST_COR_DLG_HOLD, pDlgHoldCfg->cor) |\r
+ CSL_FMK (BCP_TM_BCP_DLG_HOLD_RST_SSL_DLG_HOLD, pDlgHoldCfg->ssl) |\r
+ CSL_FMK (BCP_TM_BCP_DLG_HOLD_RST_RD_DLG_HOLD, pDlgHoldCfg->rd) |\r
+ CSL_FMK (BCP_TM_BCP_DLG_HOLD_RST_DNT_DLG_HOLD, pDlgHoldCfg->dnt);\r
+ \r
+ CSL_FINSR (pTmRegs->BCP_DLG_HOLD_RST, 26, 16, holdVal);\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * ============================================================================\r
+ * @n@b Bcp_getDlgHoldStatus\r
+ *\r
+ * @b brief\r
+ * @n This API returns the data logger hold status for all BCP submodules by \r
+ * reading the 'hold' bits from the BCP_DLG_HOLD_RST register.\r
+ * \r
+ * @param[in] \r
+ pBcpLldObj BCP LLD instance object.\r
+\r
+ * @param[in] \r
+ pDlgHoldStatus Hold bit configuration read from H/w for BCP submodules. \r
+ \r
+\r
+ * @return int32_t\r
+ * @li -1 - Invalid BCP instance handle passed/Invalid \r
+ * DLG configuration handle passed.\r
+ * \r
+ * @li =0 - Success. Data logger hold status passed back in \r
+ * the handle specified.\r
+ *\r
+ * @pre\r
+ * @n @a Bcp_lldOpen () must be called to obtain the register overlay handle for \r
+ * BCP instance before calling this API. \r
+ *\r
+ * @post\r
+ * @n None.\r
+ * ============================================================================\r
+ */\r
+static inline int32_t Bcp_getDlgHoldStatus \r
+(\r
+ Bcp_LldObj* pBcpLldObj,\r
+ Bcp_ModuleCfg* pDlgHoldStatus\r
+)\r
+{\r
+ CSL_Bcp_tmRegs* pTmRegs;\r
+ uint16_t holdVal;\r
+\r
+ if (!pBcpLldObj || !pBcpLldObj->modCfgRegs[0] || !pDlgHoldStatus)\r
+ return -1;\r
+\r
+ pTmRegs = (CSL_Bcp_tmRegs *) (pBcpLldObj->modCfgRegs[Bcp_ModuleId_TM]);\r
+ \r
+ holdVal = CSL_FEXTR (pTmRegs->BCP_DLG_HOLD_RST, 26, 16);\r
+ \r
+ pDlgHoldStatus->tm = CSL_FEXT (holdVal, BCP_TM_BCP_DLG_HOLD_RST_TM_DLG_HOLD);\r
+ pDlgHoldStatus->dio = CSL_FEXT (holdVal, BCP_TM_BCP_DLG_HOLD_RST_DIO_DLG_HOLD);\r
+ pDlgHoldStatus->crc = CSL_FEXT (holdVal, BCP_TM_BCP_DLG_HOLD_RST_CRC_DLG_HOLD);\r
+ pDlgHoldStatus->enc = CSL_FEXT (holdVal, BCP_TM_BCP_DLG_HOLD_RST_ENC_DLG_HOLD);\r
+ pDlgHoldStatus->rm = CSL_FEXT (holdVal, BCP_TM_BCP_DLG_HOLD_RST_RM_DLG_HOLD);\r
+ pDlgHoldStatus->mod = CSL_FEXT (holdVal, BCP_TM_BCP_DLG_HOLD_RST_MOD_DLG_HOLD);\r
+ pDlgHoldStatus->intleaver = CSL_FEXT (holdVal, BCP_TM_BCP_DLG_HOLD_RST_INT_DLG_HOLD);\r
+ pDlgHoldStatus->cor = CSL_FEXT (holdVal, BCP_TM_BCP_DLG_HOLD_RST_COR_DLG_HOLD);\r
+ pDlgHoldStatus->ssl = CSL_FEXT (holdVal, BCP_TM_BCP_DLG_HOLD_RST_SSL_DLG_HOLD);\r
+ pDlgHoldStatus->rd = CSL_FEXT (holdVal, BCP_TM_BCP_DLG_HOLD_RST_RD_DLG_HOLD);\r
+ pDlgHoldStatus->dnt = CSL_FEXT (holdVal, BCP_TM_BCP_DLG_HOLD_RST_DNT_DLG_HOLD);\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * ============================================================================\r
+ * @n@b Bcp_setDlgIdle\r
+ *\r
+ * @b brief\r
+ * @n This API sets up data logger in idle state (DLG_IDLE) as per the Idle\r
+ * configuration specified for all BCP submodules. It does so by writing 1 \r
+ * to the 'reset' bit in the BCP_DLG_HOLD_RST register corresponding to \r
+ * each of the modules that need to be put in idle state.\r
+ *\r
+ * @param[in] \r
+ pBcpLldObj BCP LLD instance object.\r
+\r
+ * @param[in] \r
+ pDlgIdleCfg Idle bit configuration for all the modules. To put\r
+ a specific module in idle state, set its corresponding \r
+ bit in the structure to 1 and set to 0 otherwise.\r
+\r
+ * @return int32_t\r
+ * @li -1 - Invalid BCP instance handle passed/DLG Idle state\r
+ * configuration handle passed.\r
+ * @li 0 - Success.\r
+ *\r
+ * @pre\r
+ * @n @a Bcp_lldOpen () must be called to obtain the register overlay handle for \r
+ * BCP instance before calling this API. \r
+ *\r
+ * @post\r
+ * @n Corresponding 'reset' bit set to 1 in BCP_DLG_HOLD_RST register.\r
+ * ============================================================================\r
+ */\r
+static inline int32_t Bcp_setDlgIdle \r
+(\r
+ Bcp_LldObj* pBcpLldObj,\r
+ Bcp_ModuleCfg* pDlgIdleCfg\r
+)\r
+{\r
+ CSL_Bcp_tmRegs* pTmRegs;\r
+ uint16_t idleVal;\r
+\r
+ if (!pBcpLldObj || !pBcpLldObj->modCfgRegs[0] || !pDlgIdleCfg)\r
+ return -1;\r
+\r
+ pTmRegs = (CSL_Bcp_tmRegs *) (pBcpLldObj->modCfgRegs[Bcp_ModuleId_TM]);\r
+\r
+ idleVal = CSL_FMK (BCP_TM_BCP_DLG_HOLD_RST_TM_DLG_RST, pDlgIdleCfg->tm) |\r
+ CSL_FMK (BCP_TM_BCP_DLG_HOLD_RST_DIO_DLG_RST, pDlgIdleCfg->dio) |\r
+ CSL_FMK (BCP_TM_BCP_DLG_HOLD_RST_CRC_DLG_RST, pDlgIdleCfg->crc) |\r
+ CSL_FMK (BCP_TM_BCP_DLG_HOLD_RST_ENC_DLG_RST, pDlgIdleCfg->enc) |\r
+ CSL_FMK (BCP_TM_BCP_DLG_HOLD_RST_RM_DLG_RST, pDlgIdleCfg->rm) |\r
+ CSL_FMK (BCP_TM_BCP_DLG_HOLD_RST_MOD_DLG_RST, pDlgIdleCfg->mod) |\r
+ CSL_FMK (BCP_TM_BCP_DLG_HOLD_RST_INT_DLG_RST, pDlgIdleCfg->intleaver) |\r
+ CSL_FMK (BCP_TM_BCP_DLG_HOLD_RST_COR_DLG_RST, pDlgIdleCfg->cor) |\r
+ CSL_FMK (BCP_TM_BCP_DLG_HOLD_RST_SSL_DLG_RST, pDlgIdleCfg->ssl) |\r
+ CSL_FMK (BCP_TM_BCP_DLG_HOLD_RST_RD_DLG_RST, pDlgIdleCfg->rd) |\r
+ CSL_FMK (BCP_TM_BCP_DLG_HOLD_RST_DNT_DLG_RST, pDlgIdleCfg->dnt);\r
+ \r
+ CSL_FINSR (pTmRegs->BCP_DLG_HOLD_RST, 10, 0, idleVal);\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * ============================================================================\r
+ * @n@b Bcp_getDlgIdleStatus\r
+ *\r
+ * @b brief\r
+ * @n This API returns the data logger idle status for all BCP submodules by\r
+ * reading the 'reset' bit from the BCP_DLG_HOLD_RST register.\r
+ *\r
+ * @param[in] \r
+ pBcpLldObj BCP LLD instance object.\r
+\r
+ * @param[in] \r
+ pDlgIdleStatus Reset/Idle bit configuration read from H/w for all BCP \r
+ submodules.\r
+\r
+ * @return int32_t\r
+ * @li -1 - Invalid BCP instance handle passed/Invalid DLG\r
+ * Idle status handle passed.\r
+ * @li =0 - Data logger idle status returned in the handle\r
+ * passed.\r
+ *\r
+ * @pre\r
+ * @n @a Bcp_lldOpen () must be called to obtain the register overlay handle for \r
+ * BCP instance before calling this API. \r
+ *\r
+ * @post\r
+ * @n None.\r
+ * ============================================================================\r
+ */\r
+static inline int32_t Bcp_getDlgIdleStatus \r
+(\r
+ Bcp_LldObj* pBcpLldObj,\r
+ Bcp_ModuleCfg* pDlgIdleStatus\r
+)\r
+{\r
+ CSL_Bcp_tmRegs* pTmRegs;\r
+ uint16_t idleVal;\r
+\r
+ if (!pBcpLldObj || !pBcpLldObj->modCfgRegs[0] || !pDlgIdleStatus)\r
+ return -1;\r
+\r
+ pTmRegs = (CSL_Bcp_tmRegs *) (pBcpLldObj->modCfgRegs[Bcp_ModuleId_TM]);\r
+\r
+ idleVal = CSL_FEXTR (pTmRegs->BCP_DLG_HOLD_RST, 10, 0);\r
+ \r
+ pDlgIdleStatus->tm = CSL_FEXT (idleVal, BCP_TM_BCP_DLG_HOLD_RST_TM_DLG_RST);\r
+ pDlgIdleStatus->dio = CSL_FEXT (idleVal, BCP_TM_BCP_DLG_HOLD_RST_DIO_DLG_RST);\r
+ pDlgIdleStatus->crc = CSL_FEXT (idleVal, BCP_TM_BCP_DLG_HOLD_RST_CRC_DLG_RST);\r
+ pDlgIdleStatus->enc = CSL_FEXT (idleVal, BCP_TM_BCP_DLG_HOLD_RST_ENC_DLG_RST);\r
+ pDlgIdleStatus->rm = CSL_FEXT (idleVal, BCP_TM_BCP_DLG_HOLD_RST_RM_DLG_RST);\r
+ pDlgIdleStatus->mod = CSL_FEXT (idleVal, BCP_TM_BCP_DLG_HOLD_RST_MOD_DLG_RST);\r
+ pDlgIdleStatus->intleaver = CSL_FEXT (idleVal, BCP_TM_BCP_DLG_HOLD_RST_INT_DLG_RST);\r
+ pDlgIdleStatus->cor = CSL_FEXT (idleVal, BCP_TM_BCP_DLG_HOLD_RST_COR_DLG_RST);\r
+ pDlgIdleStatus->ssl = CSL_FEXT (idleVal, BCP_TM_BCP_DLG_HOLD_RST_SSL_DLG_RST);\r
+ pDlgIdleStatus->rd = CSL_FEXT (idleVal, BCP_TM_BCP_DLG_HOLD_RST_RD_DLG_RST);\r
+ pDlgIdleStatus->dnt = CSL_FEXT (idleVal, BCP_TM_BCP_DLG_HOLD_RST_DNT_DLG_RST);\r
+ \r
+ return 0;\r
+}\r
+\r
+/**\r
+ * ============================================================================\r
+ * @n@b Bcp_setDlgHoldResetReg\r
+ *\r
+ * @b brief\r
+ * @n This API can be used to configure the hold and reset/idle settings in \r
+ * BCP_DLG_HOLD_RST register for all BCP modules at once.\r
+ *\r
+ * @param[in] \r
+ pBcpLldObj BCP LLD instance object.\r
+\r
+ * @param[in] \r
+ holdResetVal 32-bit value to configure to the BCP Data logger Hold\r
+ Reset register.\r
+\r
+ * @return int32_t\r
+ * @li -1 - Invalid BCP instance handle passed.\r
+ * @li 0 - Success.\r
+ *\r
+ * @pre\r
+ * @n @a Bcp_lldOpen () must be called to obtain the register overlay handle for \r
+ * BCP instance before calling this API. \r
+ *\r
+ * @post\r
+ * @n BCP_DLG_HOLD_RST register configured with the value passed.\r
+ * ============================================================================\r
+ */\r
+static inline int32_t Bcp_setDlgHoldResetReg \r
+(\r
+ Bcp_LldObj* pBcpLldObj,\r
+ uint32_t holdResetVal\r
+)\r
+{\r
+ CSL_Bcp_tmRegs* pTmRegs;\r
+\r
+ if (!pBcpLldObj || !pBcpLldObj->modCfgRegs[0])\r
+ return -1;\r
+\r
+ pTmRegs = (CSL_Bcp_tmRegs *) (pBcpLldObj->modCfgRegs[Bcp_ModuleId_TM]);\r
+ \r
+ pTmRegs->BCP_DLG_HOLD_RST = holdResetVal;\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * ============================================================================\r
+ * @n@b Bcp_getDlgHoldResetReg\r
+ *\r
+ * @b brief\r
+ * @n This API returns the contents of BCP_DLG_HOLD_RST register. This API\r
+ * can be used to retrieve the hold and idle status of all BCP modules\r
+ * at once.\r
+ *\r
+ * @param[in] \r
+ pBcpLldObj BCP LLD instance object.\r
+\r
+ * @return int32_t\r
+ * @li -1 - Invalid BCP instance handle passed.\r
+ * @li >=0 - Contents of BCP_DLG_HOLD_RST register.\r
+ *\r
+ * @pre\r
+ * @n @a Bcp_lldOpen () must be called to obtain the register overlay handle for \r
+ * BCP instance before calling this API. \r
+ *\r
+ * @post\r
+ * @n None.\r
+ * ============================================================================\r
+ */\r
+static inline int32_t Bcp_getDlgHoldResetReg \r
+(\r
+ Bcp_LldObj* pBcpLldObj\r
+)\r
+{\r
+ CSL_Bcp_tmRegs* pTmRegs;\r
+\r
+ if (!pBcpLldObj || !pBcpLldObj->modCfgRegs[0])\r
+ return -1;\r
+\r
+ pTmRegs = (CSL_Bcp_tmRegs *) (pBcpLldObj->modCfgRegs[Bcp_ModuleId_TM]);\r
+ \r
+ return pTmRegs->BCP_DLG_HOLD_RST;\r
+}\r
+\r
+/**\r
+ * ============================================================================\r
+ * @n@b Bcp_setCdmaHpSrcId\r
+ *\r
+ * @b brief\r
+ * @n This API sets up the Source Id for CDMAHP Info word.\r
+ *\r
+ * @param[in] \r
+ pBcpLldObj BCP LLD instance object.\r
+\r
+ * @param[in] \r
+ srcId Source Id to use for BCP CDMAHP.\r
+\r
+ * @return int32_t\r
+ * @li -1 - Invalid BCP instance handle passed.\r
+ * @li 0 - Success.\r
+ *\r
+ * @pre\r
+ * @n @a Bcp_lldOpen () must be called to obtain the register overlay handle for \r
+ * BCP instance before calling this API. \r
+ *\r
+ * @post\r
+ * @n TM_CONTROL register configured with the value passed.\r
+ * ============================================================================\r
+ */\r
+static inline int32_t Bcp_setCdmaHpSrcId \r
+(\r
+ Bcp_LldObj* pBcpLldObj,\r
+ uint8_t srcId\r
+)\r
+{\r
+ CSL_Bcp_tmRegs* pTmRegs;\r
+\r
+ if (!pBcpLldObj || !pBcpLldObj->modCfgRegs[0])\r
+ return -1;\r
+\r
+ pTmRegs = (CSL_Bcp_tmRegs *) (pBcpLldObj->modCfgRegs[Bcp_ModuleId_TM]);\r
+ \r
+ CSL_FINS (pTmRegs->TM_CONTROL, BCP_TM_TM_CONTROL_CDMAHP_SRC_ID, srcId);\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * ============================================================================\r
+ * @n@b Bcp_getCdmaHpSrcId\r
+ *\r
+ * @b brief\r
+ * @n This API returns the Source Id setup for BCP CDMAHP.\r
+ *\r
+ * @param[in] \r
+ pBcpLldObj BCP LLD instance object.\r
+\r
+ * @return int32_t\r
+ * @li -1 - Invalid BCP instance handle passed.\r
+ * @li >=0 - Source Id read from TM_CONTROL register.\r
+ *\r
+ * @pre\r
+ * @n @a Bcp_lldOpen () must be called to obtain the register overlay handle for \r
+ * BCP instance before calling this API. \r
+ *\r
+ * @post\r
+ * @n None.\r
+ * ============================================================================\r
+ */\r
+static inline int32_t Bcp_getCdmaHpSrcId \r
+(\r
+ Bcp_LldObj* pBcpLldObj\r
+)\r
+{\r
+ CSL_Bcp_tmRegs* pTmRegs;\r
+\r
+ if (!pBcpLldObj || !pBcpLldObj->modCfgRegs[0])\r
+ return -1;\r
+\r
+ pTmRegs = (CSL_Bcp_tmRegs *) (pBcpLldObj->modCfgRegs[Bcp_ModuleId_TM]);\r
+ \r
+ return CSL_FEXT (pTmRegs->TM_CONTROL, BCP_TM_TM_CONTROL_CDMAHP_SRC_ID);\r
+}\r
+\r
+/**\r
+ * ============================================================================\r
+ * @n@b Bcp_enableCdmaHp\r
+ *\r
+ * @b brief\r
+ * @n This API enables BCP CDMAHP.\r
+ *\r
+ * @param[in] \r
+ pBcpLldObj BCP LLD instance object.\r
+\r
+ * @return int32_t\r
+ * @li -1 - Invalid BCP instance handle passed.\r
+ * @li 0 - Success.\r
+ *\r
+ * @pre\r
+ * @n @a Bcp_lldOpen () must be called to obtain the register overlay handle for \r
+ * BCP instance before calling this API. \r
+ *\r
+ * @post\r
+ * @n TM_CONTROL register configured with the value passed. BCP CDMAHP turned on.\r
+ * ============================================================================\r
+ */\r
+static inline int32_t Bcp_enableCdmaHp \r
+(\r
+ Bcp_LldObj* pBcpLldObj\r
+)\r
+{\r
+ CSL_Bcp_tmRegs* pTmRegs;\r
+\r
+ if (!pBcpLldObj || !pBcpLldObj->modCfgRegs[0])\r
+ return -1;\r
+\r
+ pTmRegs = (CSL_Bcp_tmRegs *) (pBcpLldObj->modCfgRegs[Bcp_ModuleId_TM]);\r
+ \r
+ CSL_FINS (pTmRegs->TM_CONTROL, BCP_TM_TM_CONTROL_CDMAHP_DISABLE, 0);\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * ============================================================================\r
+ * @n@b Bcp_disableCdmaHp\r
+ *\r
+ * @b brief\r
+ * @n This API disables BCP CDMAHP, i.e., all signals from CDMAHP are masked off.\r
+ * Suitable for using the BCP CDMAHP in loopback mode.\r
+ *\r
+ * @param[in] \r
+ pBcpLldObj BCP LLD instance object.\r
+\r
+ * @return int32_t\r
+ * @li -1 - Invalid BCP instance handle passed.\r
+ * @li 0 - Success.\r
+ *\r
+ * @pre\r
+ * @n @a Bcp_lldOpen () must be called to obtain the register overlay handle for \r
+ * BCP instance before calling this API. \r
+ *\r
+ * @post\r
+ * @n TM_CONTROL register configured with the value passed. BCP CDMAHP turned off.\r
+ * ============================================================================\r
+ */\r
+static inline int32_t Bcp_disableCdmaHp \r
+(\r
+ Bcp_LldObj* pBcpLldObj\r
+)\r
+{\r
+ CSL_Bcp_tmRegs* pTmRegs;\r
+\r
+ if (!pBcpLldObj || !pBcpLldObj->modCfgRegs[0])\r
+ return -1;\r
+\r
+ pTmRegs = (CSL_Bcp_tmRegs *) (pBcpLldObj->modCfgRegs[Bcp_ModuleId_TM]);\r
+ \r
+ CSL_FINS (pTmRegs->TM_CONTROL, BCP_TM_TM_CONTROL_CDMAHP_DISABLE, 1);\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * ============================================================================\r
+ * @n@b Bcp_isCdmaHpEnabled\r
+ *\r
+ * @b brief\r
+ * @n This API returns 1 if BCP CDMA HP is enabled, 0 otherwise.\r
+ *\r
+ * @param[in] \r
+ pBcpLldObj BCP LLD instance object.\r
+\r
+ * @return int32_t\r
+ * @li -1 - Invalid BCP instance handle passed.\r
+ * @li 0/1 - Reads CDMAHP enable status from TM_CONTROL register.\r
+ * Returns 0 to indicate CDMAHP is disabled and 1\r
+ * to indicate it is enabled.\r
+ *\r
+ * @pre\r
+ * @n @a Bcp_lldOpen () must be called to obtain the register overlay handle for \r
+ * BCP instance before calling this API. \r
+ *\r
+ * @post\r
+ * @n None.\r
+ * ============================================================================\r
+ */\r
+static inline int32_t Bcp_isCdmaHpEnabled \r
+(\r
+ Bcp_LldObj* pBcpLldObj\r
+)\r
+{\r
+ uint8_t bIsCdmaHpDisabled; \r
+ CSL_Bcp_tmRegs* pTmRegs;\r
+\r
+ if (!pBcpLldObj || !pBcpLldObj->modCfgRegs[0])\r
+ return -1;\r
+\r
+ pTmRegs = (CSL_Bcp_tmRegs *) (pBcpLldObj->modCfgRegs[Bcp_ModuleId_TM]);\r
+ \r
+ bIsCdmaHpDisabled = CSL_FEXT (pTmRegs->TM_CONTROL, BCP_TM_TM_CONTROL_CDMAHP_DISABLE);\r
+\r
+ return (bIsCdmaHpDisabled == 0 ? 1 : 0);\r
+}\r
+\r
+/**\r
+ * ============================================================================\r
+ * @n@b Bcp_enableForcePayloadEndian\r
+ *\r
+ * @b brief\r
+ * @n This API enables forcing the payliod to follow the endian swapping\r
+ * settings regardless if it is in big or little endian.\r
+ *\r
+ * @param[in] \r
+ pBcpLldObj BCP LLD instance object.\r
+\r
+ * @return int32_t\r
+ * @li -1 - Invalid BCP instance handle passed.\r
+ * @li 0 - Success.\r
+ *\r
+ * @pre\r
+ * @n @a Bcp_lldOpen () must be called to obtain the register overlay handle for \r
+ * BCP instance before calling this API. \r
+ *\r
+ * @post\r
+ * @n TM_CONTROL register configured with the value passed.\r
+ * ============================================================================\r
+ */\r
+static inline int32_t Bcp_enableForcePayloadEndian \r
+(\r
+ Bcp_LldObj* pBcpLldObj\r
+)\r
+{\r
+ CSL_Bcp_tmRegs* pTmRegs;\r
+\r
+ if (!pBcpLldObj || !pBcpLldObj->modCfgRegs[0])\r
+ return -1;\r
+\r
+ pTmRegs = (CSL_Bcp_tmRegs *) (pBcpLldObj->modCfgRegs[Bcp_ModuleId_TM]);\r
+ \r
+ CSL_FINS (pTmRegs->TM_CONTROL, BCP_TM_TM_CONTROL_FRC_PAYLOAD_ENDIAN, 1);\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * ============================================================================\r
+ * @n@b Bcp_disableForcePayloadEndian\r
+ *\r
+ * @b brief\r
+ * @n This API clears forcing the payliod to follow the endian swapping\r
+ * settings regardless if it is in big or little endian.\r
+ *\r
+ * @param[in] \r
+ pBcpLldObj BCP LLD instance object.\r
+\r
+ * @return int32_t\r
+ * @li -1 - Invalid BCP instance handle passed.\r
+ * @li 0 - Success.\r
+ *\r
+ * @pre\r
+ * @n @a Bcp_lldOpen () must be called to obtain the register overlay handle for \r
+ * BCP instance before calling this API. \r
+ *\r
+ * @post\r
+ * @n TM_CONTROL register configured with the value passed.\r
+ * ============================================================================\r
+ */\r
+static inline int32_t Bcp_disableForcePayloadEndian \r
+(\r
+ Bcp_LldObj* pBcpLldObj\r
+)\r
+{\r
+ CSL_Bcp_tmRegs* pTmRegs;\r
+\r
+ if (!pBcpLldObj || !pBcpLldObj->modCfgRegs[0])\r
+ return -1;\r
+\r
+ pTmRegs = (CSL_Bcp_tmRegs *) (pBcpLldObj->modCfgRegs[Bcp_ModuleId_TM]);\r
+ \r
+ CSL_FINS (pTmRegs->TM_CONTROL, BCP_TM_TM_CONTROL_FRC_PAYLOAD_ENDIAN, 0);\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * ============================================================================\r
+ * @n@b Bcp_isForcePayloadEndianEnabled\r
+ *\r
+ * @b brief\r
+ * @n This API returns the value read from the "frc_payload_enable" field in\r
+ * the TM_CONTROL registration.\r
+ *\r
+ * @param[in] \r
+ pBcpLldObj BCP LLD instance object.\r
+\r
+ * @return int32_t\r
+ * @li -1 - Invalid BCP instance handle passed.\r
+ * @li 0/1 - Value read from register field.\r
+ *\r
+ * @pre\r
+ * @n @a Bcp_lldOpen () must be called to obtain the register overlay handle for \r
+ * BCP instance before calling this API. \r
+ *\r
+ * @post\r
+ * @n None.\r
+ * ============================================================================\r
+ */\r
+static inline int32_t Bcp_isForcePayloadEndianEnabled \r
+(\r
+ Bcp_LldObj* pBcpLldObj\r
+)\r
+{\r
+ CSL_Bcp_tmRegs* pTmRegs;\r
+\r
+ if (!pBcpLldObj || !pBcpLldObj->modCfgRegs[0])\r
+ return -1;\r
+\r
+ pTmRegs = (CSL_Bcp_tmRegs *) (pBcpLldObj->modCfgRegs[Bcp_ModuleId_TM]);\r
+ \r
+ return CSL_FEXT (pTmRegs->TM_CONTROL, BCP_TM_TM_CONTROL_FRC_PAYLOAD_ENDIAN);\r
+}\r
+\r
+/**\r
+ * ============================================================================\r
+ * @n@b Bcp_enableTxCdmaHpReadArbPrio\r
+ *\r
+ * @b brief\r
+ * @n This API enables raising priority of Tx CDMAHP paths with active packets.\r
+ *\r
+ * @param[in] \r
+ pBcpLldObj BCP LLD instance object.\r
+\r
+ * @return int32_t\r
+ * @li -1 - Invalid BCP instance handle passed.\r
+ * @li 0 - Success.\r
+ *\r
+ * @pre\r
+ * @n @a Bcp_lldOpen () must be called to obtain the register overlay handle for \r
+ * BCP instance before calling this API. \r
+ *\r
+ * @post\r
+ * @n TM_CONTROL register configured with the value passed.\r
+ * ============================================================================\r
+ */\r
+static inline int32_t Bcp_enableTxCdmaHpReadArbPrio \r
+(\r
+ Bcp_LldObj* pBcpLldObj\r
+)\r
+{\r
+ CSL_Bcp_tmRegs* pTmRegs;\r
+\r
+ if (!pBcpLldObj || !pBcpLldObj->modCfgRegs[0])\r
+ return -1;\r
+\r
+ pTmRegs = (CSL_Bcp_tmRegs *) (pBcpLldObj->modCfgRegs[Bcp_ModuleId_TM]);\r
+ \r
+ CSL_FINS (pTmRegs->TM_CONTROL, BCP_TM_TM_CONTROL_TX_CDMAHP_RD_ARB_HPRIORITY, 1);\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * ============================================================================\r
+ * @n@b Bcp_disableTxCdmaHpReadArbPrio\r
+ *\r
+ * @b brief\r
+ * @n This API disables raising priority of Tx CDMAHP paths with active packets.\r
+ *\r
+ * @param[in] \r
+ pBcpLldObj BCP LLD instance object.\r
+\r
+ * @return int32_t\r
+ * @li -1 - Invalid BCP instance handle passed.\r
+ * @li 0 - Success.\r
+ *\r
+ * @pre\r
+ * @n @a Bcp_lldOpen () must be called to obtain the register overlay handle for \r
+ * BCP instance before calling this API. \r
+ *\r
+ * @post\r
+ * @n TM_CONTROL register configured with the value passed.\r
+ * ============================================================================\r
+ */\r
+static inline int32_t Bcp_disableTxCdmaHpReadArbPrio \r
+(\r
+ Bcp_LldObj* pBcpLldObj\r
+)\r
+{\r
+ CSL_Bcp_tmRegs* pTmRegs;\r
+\r
+ if (!pBcpLldObj || !pBcpLldObj->modCfgRegs[0])\r
+ return -1;\r
+\r
+ pTmRegs = (CSL_Bcp_tmRegs *) (pBcpLldObj->modCfgRegs[Bcp_ModuleId_TM]);\r
+ \r
+ CSL_FINS (pTmRegs->TM_CONTROL, BCP_TM_TM_CONTROL_TX_CDMAHP_RD_ARB_HPRIORITY, 0);\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * ============================================================================\r
+ * @n@b Bcp_isTxCdmaHpReadArbPrioEnabled\r
+ *\r
+ * @b brief\r
+ * @n This API returns 1 if BCP Tx CDMAHP read arbitration priority is enabled.\r
+ *\r
+ * @param[in] \r
+ pBcpLldObj BCP LLD instance object.\r
+\r
+ * @return int32_t\r
+ * @li -1 - Invalid BCP instance handle passed.\r
+ * @li 0/1 - Reads Tx CDMAHP read arbitration priority enable \r
+ * status from TM_CONTROL register.\r
+ * Returns 0 to indicate priority raise disabled and 1\r
+ * to indicate it is enabled.\r
+ *\r
+ * @pre\r
+ * @n @a Bcp_lldOpen () must be called to obtain the register overlay handle for \r
+ * BCP instance before calling this API. \r
+ *\r
+ * @post\r
+ * @n None.\r
+ * ============================================================================\r
+ */\r
+static inline int32_t Bcp_isTxCdmaHpReadArbPrioEnabled \r
+(\r
+ Bcp_LldObj* pBcpLldObj\r
+)\r
+{\r
+ CSL_Bcp_tmRegs* pTmRegs;\r
+\r
+ if (!pBcpLldObj || !pBcpLldObj->modCfgRegs[0])\r
+ return -1;\r
+\r
+ pTmRegs = (CSL_Bcp_tmRegs *) (pBcpLldObj->modCfgRegs[Bcp_ModuleId_TM]);\r
+ \r
+ return CSL_FEXT (pTmRegs->TM_CONTROL, BCP_TM_TM_CONTROL_TX_CDMAHP_RD_ARB_HPRIORITY);\r
+}\r
+\r
+/**\r
+ * ============================================================================\r
+ * @n@b Bcp_setTMControlReg\r
+ *\r
+ * @b brief\r
+ * @n This API sets up the contents of TM_CONTROL register.\r
+ *\r
+ * @param[in] \r
+ pBcpLldObj BCP LLD instance object.\r
+\r
+ * @param[in] \r
+ srcId Source Id to use for BCP CDMAHP.\r
+\r
+ * @param[in] \r
+ bCdmaDisable Set to 1 to disable BCP CDMAHP and 0 otherwise.\r
+\r
+ * @param[in] \r
+ bFrcPayloadEndianDisable Set to 1 to enable raising priority of Rx QFIFO and \r
+ 0 otherwise.\r
+\r
+ * @param[in] \r
+ bTxRdArbPrioEnable Set to 1 to enable raising priority of Tx CDMAHP paths and \r
+ 0 otherwise.\r
+\r
+\r
+ * @return int32_t\r
+ * @li -1 - Invalid BCP instance handle passed.\r
+ * @li 0 - Success.\r
+ *\r
+ * @pre\r
+ * @n @a Bcp_lldOpen () must be called to obtain the register overlay handle for \r
+ * BCP instance before calling this API. \r
+ *\r
+ * @post\r
+ * @n TM_CONTROL register configured with the value passed.\r
+ * ============================================================================\r
+ */\r
+static inline int32_t Bcp_setTMControlReg \r
+(\r
+ Bcp_LldObj* pBcpLldObj,\r
+ uint8_t srcId,\r
+ uint8_t bCdmaDisable,\r
+ uint8_t bFrcPayloadEndianDisable,\r
+ uint8_t bTxRdArbPrioEnable\r
+)\r
+{\r
+ CSL_Bcp_tmRegs* pTmRegs;\r
+\r
+ if (!pBcpLldObj || !pBcpLldObj->modCfgRegs[0])\r
+ return -1;\r
+\r
+ pTmRegs = (CSL_Bcp_tmRegs *) (pBcpLldObj->modCfgRegs[Bcp_ModuleId_TM]);\r
+ \r
+ pTmRegs->TM_CONTROL = CSL_FMK (BCP_TM_TM_CONTROL_CDMAHP_SRC_ID, srcId) |\r
+ CSL_FMK (BCP_TM_TM_CONTROL_CDMAHP_DISABLE, bCdmaDisable) |\r
+ CSL_FMK (BCP_TM_TM_CONTROL_FRC_PAYLOAD_ENDIAN, bFrcPayloadEndianDisable) |\r
+ CSL_FMK (BCP_TM_TM_CONTROL_TX_CDMAHP_RD_ARB_HPRIORITY, bTxRdArbPrioEnable);\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * ============================================================================\r
+ * @n@b Bcp_getTMControlReg\r
+ *\r
+ * @b brief\r
+ * @n This API returns the contents of the TM_CONTROL register.\r
+ *\r
+ * @param[in] \r
+ pBcpLldObj BCP LLD instance object.\r
+\r
+ * @param[out] \r
+ pSrcId BCP CDMAHP Source Id.\r
+\r
+ * @param[out] \r
+ pIsCdmaDisabled CDMAHP disable status. 0 returned when CDMAHP enabled\r
+ and 1 otherwise.\r
+\r
+ * @param[out] \r
+ pIsFrcPayloadEndianDisabled Indicates if Rx priority raise is enabled.\r
+\r
+ * @param[out] \r
+ pIsTxRdArbPrioEnabled Indicates if Tx priority raise is enabled.\r
+\r
+\r
+ * @return int32_t\r
+ * @li -1 - Invalid BCP instance handle passed.\r
+ * @li 0 - Succesfully populated output params.\r
+ *\r
+ * @pre\r
+ * @n @a Bcp_lldOpen () must be called to obtain the register overlay handle for \r
+ * BCP instance before calling this API. \r
+ *\r
+ * @post\r
+ * @n None.\r
+ * ============================================================================\r
+ */\r
+static inline int32_t Bcp_getTMControlReg \r
+(\r
+ Bcp_LldObj* pBcpLldObj,\r
+ uint8_t* pSrcId,\r
+ uint8_t* pIsCdmaDisabled,\r
+ uint8_t* pIsFrcPayloadEndianDisabled,\r
+ uint8_t* pIsTxRdArbPrioEnabled\r
+)\r
+{\r
+ uint32_t tmpWord; \r
+ CSL_Bcp_tmRegs* pTmRegs;\r
+\r
+ if (!pBcpLldObj || !pBcpLldObj->modCfgRegs[0] || !pSrcId || !pIsCdmaDisabled || !pIsFrcPayloadEndianDisabled || !pIsTxRdArbPrioEnabled)\r
+ return -1;\r
+\r
+ pTmRegs = (CSL_Bcp_tmRegs *) (pBcpLldObj->modCfgRegs[Bcp_ModuleId_TM]);\r
+ tmpWord = pTmRegs->TM_CONTROL;\r
+ \r
+ *pSrcId = CSL_FEXT (tmpWord, BCP_TM_TM_CONTROL_CDMAHP_SRC_ID);\r
+ *pIsCdmaDisabled = CSL_FEXT (tmpWord, BCP_TM_TM_CONTROL_CDMAHP_DISABLE);\r
+ *pIsFrcPayloadEndianDisabled = CSL_FEXT (tmpWord, BCP_TM_TM_CONTROL_FRC_PAYLOAD_ENDIAN);\r
+ *pIsTxRdArbPrioEnabled = CSL_FEXT (tmpWord, BCP_TM_TM_CONTROL_TX_CDMAHP_RD_ARB_HPRIORITY);\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * ============================================================================\r
+ * @n@b Bcp_setTxCdmaHpReadPrioReg\r
+ *\r
+ * @b brief\r
+ * @n This API sets up the contents of TM_TX_CDMAHP_READ_PRIORITY register.\r
+ *\r
+ * @param[in] \r
+ pBcpLldObj BCP LLD instance object.\r
+\r
+ * @param[in] \r
+ prioVal Array of priority values to configure for reading CDMAHP for\r
+ QFIFOs 0..7.\r
+\r
+ * @return int32_t\r
+ * @li -1 - Invalid BCP instance handle passed.\r
+ * @li 0 - Success.\r
+ *\r
+ * @pre\r
+ * @n @a Bcp_lldOpen () must be called to obtain the register overlay handle for \r
+ * BCP instance before calling this API. \r
+ *\r
+ * @post\r
+ * @n TM_TX_CDMAHP_READ_PRIORITY register configured with the values passed.\r
+ * ============================================================================\r
+ */\r
+static inline int32_t Bcp_setTxCdmaHpReadPrioReg \r
+(\r
+ Bcp_LldObj* pBcpLldObj,\r
+ uint8_t prioVal[8]\r
+)\r
+{\r
+ CSL_Bcp_tmRegs* pTmRegs;\r
+\r
+ if (!pBcpLldObj || !pBcpLldObj->modCfgRegs[0])\r
+ return -1;\r
+\r
+ pTmRegs = (CSL_Bcp_tmRegs *) (pBcpLldObj->modCfgRegs[Bcp_ModuleId_TM]);\r
+ \r
+ pTmRegs->TM_TX_CDMAHP_READ_PRIORITY = \r
+ CSL_FMK (BCP_TM_TM_TX_CDMAHP_READ_PRIORITY_TX_CDMAHP_RD_ARB_PRIORITY_0, prioVal[0]) |\r
+ CSL_FMK (BCP_TM_TM_TX_CDMAHP_READ_PRIORITY_TX_CDMAHP_RD_ARB_PRIORITY_1, prioVal[1]) |\r
+ CSL_FMK (BCP_TM_TM_TX_CDMAHP_READ_PRIORITY_TX_CDMAHP_RD_ARB_PRIORITY_2, prioVal[2]) |\r
+ CSL_FMK (BCP_TM_TM_TX_CDMAHP_READ_PRIORITY_TX_CDMAHP_RD_ARB_PRIORITY_3, prioVal[3]) |\r
+ CSL_FMK (BCP_TM_TM_TX_CDMAHP_READ_PRIORITY_TX_CDMAHP_RD_ARB_PRIORITY_4, prioVal[4]) |\r
+ CSL_FMK (BCP_TM_TM_TX_CDMAHP_READ_PRIORITY_TX_CDMAHP_RD_ARB_PRIORITY_5, prioVal[5]) |\r
+ CSL_FMK (BCP_TM_TM_TX_CDMAHP_READ_PRIORITY_TX_CDMAHP_RD_ARB_PRIORITY_6, prioVal[6]) |\r
+ CSL_FMK (BCP_TM_TM_TX_CDMAHP_READ_PRIORITY_TX_CDMAHP_RD_ARB_PRIORITY_7, prioVal[7]);\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * ============================================================================\r
+ * @n@b Bcp_getTxCdmaHpReadPrioReg\r
+ *\r
+ * @b brief\r
+ * @n This API returns the contents of TM_TX_CDMAHP_READ_PRIORITY register.\r
+ *\r
+ * @param[in] \r
+ pBcpLldObj BCP LLD instance object.\r
+\r
+ * @param[out] \r
+ prioVal CDMAHP read priorities for QFIFOs 0..7 returned from \r
+ hardware.\r
+\r
+ * @return int32_t\r
+ * @li -1 - Invalid BCP instance handle passed.\r
+ * @li 0 - Success.\r
+ *\r
+ * @pre\r
+ * @n @a Bcp_lldOpen () must be called to obtain the register overlay handle for \r
+ * BCP instance before calling this API. \r
+ *\r
+ * @post\r
+ * @n None.\r
+ * ============================================================================\r
+ */\r
+static inline int32_t Bcp_getTxCdmaHpReadPrioReg \r
+(\r
+ Bcp_LldObj* pBcpLldObj,\r
+ uint8_t prioVal[8]\r
+)\r
+{\r
+ uint32_t tmpWord;\r
+ CSL_Bcp_tmRegs* pTmRegs;\r
+\r
+ if (!pBcpLldObj || !pBcpLldObj->modCfgRegs[0])\r
+ return -1;\r
+\r
+ pTmRegs = (CSL_Bcp_tmRegs *) (pBcpLldObj->modCfgRegs[Bcp_ModuleId_TM]);\r
+ tmpWord = pTmRegs->TM_TX_CDMAHP_READ_PRIORITY;\r
+\r
+ prioVal[0] = CSL_FEXT (tmpWord, BCP_TM_TM_TX_CDMAHP_READ_PRIORITY_TX_CDMAHP_RD_ARB_PRIORITY_0);\r
+ prioVal[1] = CSL_FEXT (tmpWord, BCP_TM_TM_TX_CDMAHP_READ_PRIORITY_TX_CDMAHP_RD_ARB_PRIORITY_1);\r
+ prioVal[2] = CSL_FEXT (tmpWord, BCP_TM_TM_TX_CDMAHP_READ_PRIORITY_TX_CDMAHP_RD_ARB_PRIORITY_2);\r
+ prioVal[3] = CSL_FEXT (tmpWord, BCP_TM_TM_TX_CDMAHP_READ_PRIORITY_TX_CDMAHP_RD_ARB_PRIORITY_3);\r
+ prioVal[4] = CSL_FEXT (tmpWord, BCP_TM_TM_TX_CDMAHP_READ_PRIORITY_TX_CDMAHP_RD_ARB_PRIORITY_4);\r
+ prioVal[5] = CSL_FEXT (tmpWord, BCP_TM_TM_TX_CDMAHP_READ_PRIORITY_TX_CDMAHP_RD_ARB_PRIORITY_5);\r
+ prioVal[6] = CSL_FEXT (tmpWord, BCP_TM_TM_TX_CDMAHP_READ_PRIORITY_TX_CDMAHP_RD_ARB_PRIORITY_6);\r
+ prioVal[7] = CSL_FEXT (tmpWord, BCP_TM_TM_TX_CDMAHP_READ_PRIORITY_TX_CDMAHP_RD_ARB_PRIORITY_7);\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * ============================================================================\r
+ * @n@b Bcp_setTxQfifoReadDestSelReg\r
+ *\r
+ * @b brief\r
+ * @n This API sets up the contents of TM_TX_QFIFO_RD_DEST_SEL register.\r
+ *\r
+ * @param[in] \r
+ pBcpLldObj BCP LLD instance object.\r
+\r
+ * @param[in] \r
+ destSel Destination select values for QFIFOs 0..7\r
+\r
+ * @param[in] \r
+ prioVal Priority values to configure for reading QFIFOs 0..7.\r
+\r
+ * @return int32_t\r
+ * @li -1 - Invalid BCP instance handle passed.\r
+ * @li 0 - Success.\r
+ *\r
+ * @pre\r
+ * @n @a Bcp_lldOpen () must be called to obtain the register overlay handle for \r
+ * BCP instance before calling this API. \r
+ *\r
+ * @post\r
+ * @n TM_TX_QFIFO_RD_DEST_SEL register configured with the values passed.\r
+ * ============================================================================\r
+ */\r
+static inline int32_t Bcp_setTxQfifoReadDestSelReg \r
+(\r
+ Bcp_LldObj* pBcpLldObj,\r
+ uint8_t destSel[8],\r
+ uint8_t prioVal[8]\r
+)\r
+{\r
+ CSL_Bcp_tmRegs* pTmRegs;\r
+\r
+ if (!pBcpLldObj || !pBcpLldObj->modCfgRegs[0])\r
+ return -1;\r
+\r
+ pTmRegs = (CSL_Bcp_tmRegs *) (pBcpLldObj->modCfgRegs[Bcp_ModuleId_TM]);\r
+ \r
+ pTmRegs->TM_TX_QFIFO_RD_DEST_SEL = \r
+ CSL_FMK (BCP_TM_TM_TX_QFIFO_RD_DEST_SEL_TX_QFIFO_RD_DEST_SEL_0, destSel[0]) |\r
+ CSL_FMK (BCP_TM_TM_TX_QFIFO_RD_DEST_SEL_TX_QFIFO_RD_DEST_SEL_1, destSel[1]) |\r
+ CSL_FMK (BCP_TM_TM_TX_QFIFO_RD_DEST_SEL_TX_QFIFO_RD_DEST_SEL_2, destSel[2]) |\r
+ CSL_FMK (BCP_TM_TM_TX_QFIFO_RD_DEST_SEL_TX_QFIFO_RD_DEST_SEL_3, destSel[3]) |\r
+ CSL_FMK (BCP_TM_TM_TX_QFIFO_RD_DEST_SEL_TX_QFIFO_RD_DEST_SEL_4, destSel[4]) |\r
+ CSL_FMK (BCP_TM_TM_TX_QFIFO_RD_DEST_SEL_TX_QFIFO_RD_DEST_SEL_5, destSel[5]) |\r
+ CSL_FMK (BCP_TM_TM_TX_QFIFO_RD_DEST_SEL_TX_QFIFO_RD_DEST_SEL_6, destSel[6]) |\r
+ CSL_FMK (BCP_TM_TM_TX_QFIFO_RD_DEST_SEL_TX_QFIFO_RD_DEST_SEL_7, destSel[7]) |\r
+\r
+ CSL_FMK (BCP_TM_TM_TX_QFIFO_RD_DEST_SEL_TX_QFIFO_RD_ARB_PRIORITY_0, prioVal[0]) |\r
+ CSL_FMK (BCP_TM_TM_TX_QFIFO_RD_DEST_SEL_TX_QFIFO_RD_ARB_PRIORITY_1, prioVal[1]) |\r
+ CSL_FMK (BCP_TM_TM_TX_QFIFO_RD_DEST_SEL_TX_QFIFO_RD_ARB_PRIORITY_2, prioVal[2]) |\r
+ CSL_FMK (BCP_TM_TM_TX_QFIFO_RD_DEST_SEL_TX_QFIFO_RD_ARB_PRIORITY_3, prioVal[3]) |\r
+ CSL_FMK (BCP_TM_TM_TX_QFIFO_RD_DEST_SEL_TX_QFIFO_RD_ARB_PRIORITY_4, prioVal[4]) |\r
+ CSL_FMK (BCP_TM_TM_TX_QFIFO_RD_DEST_SEL_TX_QFIFO_RD_ARB_PRIORITY_5, prioVal[5]) |\r
+ CSL_FMK (BCP_TM_TM_TX_QFIFO_RD_DEST_SEL_TX_QFIFO_RD_ARB_PRIORITY_6, prioVal[6]) |\r
+ CSL_FMK (BCP_TM_TM_TX_QFIFO_RD_DEST_SEL_TX_QFIFO_RD_ARB_PRIORITY_7, prioVal[7]);\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * ============================================================================\r
+ * @n@b Bcp_getTxQfifoReadDestSelReg\r
+ *\r
+ * @b brief\r
+ * @n This API returns the contents of TM_TX_QFIFO_RD_DEST_SEL register.\r
+ *\r
+ * @param[in] \r
+ pBcpLldObj BCP LLD instance object.\r
+\r
+ * @param[out] \r
+ destSel Destination select values for QFIFOs 0..7\r
+\r
+ * @param[out] \r
+ prioVal Priority values for reading QFIFOs 0..7.\r
+\r
+ * @return int32_t\r
+ * @li -1 - Invalid BCP instance handle passed.\r
+ * @li 0 - Success.\r
+ *\r
+ * @pre\r
+ * @n @a Bcp_lldOpen () must be called to obtain the register overlay handle for \r
+ * BCP instance before calling this API. \r
+ *\r
+ * @post\r
+ * @n None.\r
+ * ============================================================================\r
+ */\r
+static inline int32_t Bcp_getTxQfifoReadDestSelReg \r
+(\r
+ Bcp_LldObj* pBcpLldObj,\r
+ uint8_t destSel[8],\r
+ uint8_t prioVal[8]\r
+)\r
+{\r
+ uint32_t tmpWord;\r
+ CSL_Bcp_tmRegs* pTmRegs;\r
+\r
+ if (!pBcpLldObj || !pBcpLldObj->modCfgRegs[0])\r
+ return -1;\r
+\r
+ pTmRegs = (CSL_Bcp_tmRegs *) (pBcpLldObj->modCfgRegs[Bcp_ModuleId_TM]);\r
+ tmpWord = pTmRegs->TM_TX_QFIFO_RD_DEST_SEL;\r
+\r
+ destSel[0] = CSL_FEXT (tmpWord, BCP_TM_TM_TX_QFIFO_RD_DEST_SEL_TX_QFIFO_RD_DEST_SEL_0);\r
+ destSel[1] = CSL_FEXT (tmpWord, BCP_TM_TM_TX_QFIFO_RD_DEST_SEL_TX_QFIFO_RD_DEST_SEL_1);\r
+ destSel[2] = CSL_FEXT (tmpWord, BCP_TM_TM_TX_QFIFO_RD_DEST_SEL_TX_QFIFO_RD_DEST_SEL_2);\r
+ destSel[3] = CSL_FEXT (tmpWord, BCP_TM_TM_TX_QFIFO_RD_DEST_SEL_TX_QFIFO_RD_DEST_SEL_3);\r
+ destSel[4] = CSL_FEXT (tmpWord, BCP_TM_TM_TX_QFIFO_RD_DEST_SEL_TX_QFIFO_RD_DEST_SEL_4);\r
+ destSel[5] = CSL_FEXT (tmpWord, BCP_TM_TM_TX_QFIFO_RD_DEST_SEL_TX_QFIFO_RD_DEST_SEL_5);\r
+ destSel[6] = CSL_FEXT (tmpWord, BCP_TM_TM_TX_QFIFO_RD_DEST_SEL_TX_QFIFO_RD_DEST_SEL_6);\r
+ destSel[7] = CSL_FEXT (tmpWord, BCP_TM_TM_TX_QFIFO_RD_DEST_SEL_TX_QFIFO_RD_DEST_SEL_7);\r
+\r
+ prioVal[0] = CSL_FEXT (tmpWord, BCP_TM_TM_TX_QFIFO_RD_DEST_SEL_TX_QFIFO_RD_ARB_PRIORITY_0);\r
+ prioVal[1] = CSL_FEXT (tmpWord, BCP_TM_TM_TX_QFIFO_RD_DEST_SEL_TX_QFIFO_RD_ARB_PRIORITY_1);\r
+ prioVal[2] = CSL_FEXT (tmpWord, BCP_TM_TM_TX_QFIFO_RD_DEST_SEL_TX_QFIFO_RD_ARB_PRIORITY_2);\r
+ prioVal[3] = CSL_FEXT (tmpWord, BCP_TM_TM_TX_QFIFO_RD_DEST_SEL_TX_QFIFO_RD_ARB_PRIORITY_3);\r
+ prioVal[4] = CSL_FEXT (tmpWord, BCP_TM_TM_TX_QFIFO_RD_DEST_SEL_TX_QFIFO_RD_ARB_PRIORITY_4);\r
+ prioVal[5] = CSL_FEXT (tmpWord, BCP_TM_TM_TX_QFIFO_RD_DEST_SEL_TX_QFIFO_RD_ARB_PRIORITY_5);\r
+ prioVal[6] = CSL_FEXT (tmpWord, BCP_TM_TM_TX_QFIFO_RD_DEST_SEL_TX_QFIFO_RD_ARB_PRIORITY_6);\r
+ prioVal[7] = CSL_FEXT (tmpWord, BCP_TM_TM_TX_QFIFO_RD_DEST_SEL_TX_QFIFO_RD_ARB_PRIORITY_7);\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * ============================================================================\r
+ * @n@b Bcp_setRxQFifoWriteArbPrioReg\r
+ *\r
+ * @b brief\r
+ * @n This API sets up the contents of TM_RX_QFIFO_WR_ARB_PRIORITY_3_0 and\r
+ * TM_RX_QFIFO_WR_ARB_PRIORITY_7_4 registers. This API sets priority for \r
+ * data from each PPB to the 8 BCP Tx queues.\r
+ *\r
+ * @param[in] \r
+ pBcpLldObj BCP LLD instance object.\r
+\r
+ * @param[in] \r
+ prioVal Priority values for writing QFIFO 0...7 from PPB 0..3\r
+\r
+ * @return int32_t\r
+ * @li -1 - Invalid BCP instance handle passed.\r
+ * @li 0 - Success.\r
+ *\r
+ * @pre\r
+ * @n @a Bcp_lldOpen () must be called to obtain the register overlay handle for \r
+ * BCP instance before calling this API. \r
+ *\r
+ * @post\r
+ * @n TM_RX_QFIFO_WR_ARB_PRIORITY_3_0 and TM_RX_QFIFO_WR_ARB_PRIORITY_7_4 \r
+ * registers configured with the values passed.\r
+ * ============================================================================\r
+ */\r
+static inline int32_t Bcp_setRxQFifoWriteArbPrioReg \r
+(\r
+ Bcp_LldObj* pBcpLldObj,\r
+ uint8_t prioVal[4][8]\r
+)\r
+{\r
+ CSL_Bcp_tmRegs* pTmRegs;\r
+\r
+ if (!pBcpLldObj || !pBcpLldObj->modCfgRegs[0])\r
+ return -1;\r
+\r
+ pTmRegs = (CSL_Bcp_tmRegs *) (pBcpLldObj->modCfgRegs[Bcp_ModuleId_TM]);\r
+ \r
+ pTmRegs->TM_RX_QFIFO_WR_ARB_PRIORITY_3_0 = \r
+ CSL_FMK (BCP_TM_TM_RX_QFIFO_WR_ARB_PRIORITY_3_0_TX_QFIFO_0_WR_ARB_PRIORITY_0, prioVal[0][0]) |\r
+ CSL_FMK (BCP_TM_TM_RX_QFIFO_WR_ARB_PRIORITY_3_0_TX_QFIFO_0_WR_ARB_PRIORITY_1, prioVal[1][0]) |\r
+ CSL_FMK (BCP_TM_TM_RX_QFIFO_WR_ARB_PRIORITY_3_0_TX_QFIFO_0_WR_ARB_PRIORITY_2, prioVal[2][0]) |\r
+ CSL_FMK (BCP_TM_TM_RX_QFIFO_WR_ARB_PRIORITY_3_0_TX_QFIFO_0_WR_ARB_PRIORITY_3, prioVal[3][0]) |\r
+ CSL_FMK (BCP_TM_TM_RX_QFIFO_WR_ARB_PRIORITY_3_0_TX_QFIFO_1_WR_ARB_PRIORITY_0, prioVal[0][1]) |\r
+ CSL_FMK (BCP_TM_TM_RX_QFIFO_WR_ARB_PRIORITY_3_0_TX_QFIFO_1_WR_ARB_PRIORITY_1, prioVal[1][1]) |\r
+ CSL_FMK (BCP_TM_TM_RX_QFIFO_WR_ARB_PRIORITY_3_0_TX_QFIFO_1_WR_ARB_PRIORITY_2, prioVal[2][1]) |\r
+ CSL_FMK (BCP_TM_TM_RX_QFIFO_WR_ARB_PRIORITY_3_0_TX_QFIFO_1_WR_ARB_PRIORITY_3, prioVal[3][1]) |\r
+ CSL_FMK (BCP_TM_TM_RX_QFIFO_WR_ARB_PRIORITY_3_0_TX_QFIFO_2_WR_ARB_PRIORITY_0, prioVal[0][2]) |\r
+ CSL_FMK (BCP_TM_TM_RX_QFIFO_WR_ARB_PRIORITY_3_0_TX_QFIFO_2_WR_ARB_PRIORITY_1, prioVal[1][2]) |\r
+ CSL_FMK (BCP_TM_TM_RX_QFIFO_WR_ARB_PRIORITY_3_0_TX_QFIFO_2_WR_ARB_PRIORITY_2, prioVal[2][2]) |\r
+ CSL_FMK (BCP_TM_TM_RX_QFIFO_WR_ARB_PRIORITY_3_0_TX_QFIFO_2_WR_ARB_PRIORITY_3, prioVal[3][2]) |\r
+ CSL_FMK (BCP_TM_TM_RX_QFIFO_WR_ARB_PRIORITY_3_0_TX_QFIFO_3_WR_ARB_PRIORITY_0, prioVal[0][3]) |\r
+ CSL_FMK (BCP_TM_TM_RX_QFIFO_WR_ARB_PRIORITY_3_0_TX_QFIFO_3_WR_ARB_PRIORITY_1, prioVal[1][3]) |\r
+ CSL_FMK (BCP_TM_TM_RX_QFIFO_WR_ARB_PRIORITY_3_0_TX_QFIFO_3_WR_ARB_PRIORITY_2, prioVal[2][3]) |\r
+ CSL_FMK (BCP_TM_TM_RX_QFIFO_WR_ARB_PRIORITY_3_0_TX_QFIFO_3_WR_ARB_PRIORITY_3, prioVal[3][3]);\r
+\r
+ pTmRegs->TM_RX_QFIFO_WR_ARB_PRIORITY_7_4 = \r
+ CSL_FMK (BCP_TM_TM_RX_QFIFO_WR_ARB_PRIORITY_7_4_TX_QFIFO_4_WR_ARB_PRIORITY_0, prioVal[0][4]) |\r
+ CSL_FMK (BCP_TM_TM_RX_QFIFO_WR_ARB_PRIORITY_7_4_TX_QFIFO_4_WR_ARB_PRIORITY_1, prioVal[1][4]) |\r
+ CSL_FMK (BCP_TM_TM_RX_QFIFO_WR_ARB_PRIORITY_7_4_TX_QFIFO_4_WR_ARB_PRIORITY_2, prioVal[2][4]) |\r
+ CSL_FMK (BCP_TM_TM_RX_QFIFO_WR_ARB_PRIORITY_7_4_TX_QFIFO_4_WR_ARB_PRIORITY_3, prioVal[3][4]) |\r
+ CSL_FMK (BCP_TM_TM_RX_QFIFO_WR_ARB_PRIORITY_7_4_TX_QFIFO_5_WR_ARB_PRIORITY_0, prioVal[0][5]) |\r
+ CSL_FMK (BCP_TM_TM_RX_QFIFO_WR_ARB_PRIORITY_7_4_TX_QFIFO_5_WR_ARB_PRIORITY_1, prioVal[1][5]) |\r
+ CSL_FMK (BCP_TM_TM_RX_QFIFO_WR_ARB_PRIORITY_7_4_TX_QFIFO_5_WR_ARB_PRIORITY_2, prioVal[2][5]) |\r
+ CSL_FMK (BCP_TM_TM_RX_QFIFO_WR_ARB_PRIORITY_7_4_TX_QFIFO_5_WR_ARB_PRIORITY_3, prioVal[3][5]) |\r
+ CSL_FMK (BCP_TM_TM_RX_QFIFO_WR_ARB_PRIORITY_7_4_TX_QFIFO_6_WR_ARB_PRIORITY_0, prioVal[0][6]) |\r
+ CSL_FMK (BCP_TM_TM_RX_QFIFO_WR_ARB_PRIORITY_7_4_TX_QFIFO_6_WR_ARB_PRIORITY_1, prioVal[1][6]) |\r
+ CSL_FMK (BCP_TM_TM_RX_QFIFO_WR_ARB_PRIORITY_7_4_TX_QFIFO_6_WR_ARB_PRIORITY_2, prioVal[2][6]) |\r
+ CSL_FMK (BCP_TM_TM_RX_QFIFO_WR_ARB_PRIORITY_7_4_TX_QFIFO_6_WR_ARB_PRIORITY_3, prioVal[3][6]) |\r
+ CSL_FMK (BCP_TM_TM_RX_QFIFO_WR_ARB_PRIORITY_7_4_TX_QFIFO_7_WR_ARB_PRIORITY_0, prioVal[0][7]) |\r
+ CSL_FMK (BCP_TM_TM_RX_QFIFO_WR_ARB_PRIORITY_7_4_TX_QFIFO_7_WR_ARB_PRIORITY_1, prioVal[1][7]) |\r
+ CSL_FMK (BCP_TM_TM_RX_QFIFO_WR_ARB_PRIORITY_7_4_TX_QFIFO_7_WR_ARB_PRIORITY_2, prioVal[2][7]) |\r
+ CSL_FMK (BCP_TM_TM_RX_QFIFO_WR_ARB_PRIORITY_7_4_TX_QFIFO_7_WR_ARB_PRIORITY_3, prioVal[3][7]);\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * ============================================================================\r
+ * @n@b Bcp_getRxQFifoWriteArbPrioReg\r
+ *\r
+ * @b brief\r
+ * @n This API returns the contents of TM_RX_QFIFO_WR_ARB_PRIORITY_3_0 and\r
+ * TM_RX_QFIFO_WR_ARB_PRIORITY_7_4 registers. This API retrieves priorities \r
+ * configured for data from each PPB to the 8 BCP Tx queues.\r
+ *\r
+ * @param[in] \r
+ pBcpLldObj BCP LLD instance object.\r
+\r
+ * @param[out] \r
+ prioVal Priority values for writing QFIFO 0...7 from PPB 0..3\r
+\r
+ * @return int32_t\r
+ * @li -1 - Invalid BCP instance handle passed.\r
+ * @li 0 - Success.\r
+ *\r
+ * @pre\r
+ * @n @a Bcp_lldOpen () must be called to obtain the register overlay handle for \r
+ * BCP instance before calling this API. \r
+ *\r
+ * @post\r
+ * @n None.\r
+ * ============================================================================\r
+ */\r
+static inline int32_t Bcp_getRxQFifoWriteArbPrioReg \r
+(\r
+ Bcp_LldObj* pBcpLldObj,\r
+ uint8_t prioVal[4][8]\r
+)\r
+{\r
+ uint32_t tmpWord [2]; \r
+ CSL_Bcp_tmRegs* pTmRegs;\r
+\r
+ if (!pBcpLldObj || !pBcpLldObj->modCfgRegs[0])\r
+ return -1;\r
+\r
+ pTmRegs = (CSL_Bcp_tmRegs *) (pBcpLldObj->modCfgRegs[Bcp_ModuleId_TM]);\r
+ tmpWord [0] = pTmRegs->TM_RX_QFIFO_WR_ARB_PRIORITY_3_0;\r
+ tmpWord [1] = pTmRegs->TM_RX_QFIFO_WR_ARB_PRIORITY_7_4;\r
+\r
+ prioVal[0][0] = CSL_FEXT (tmpWord [0], BCP_TM_TM_RX_QFIFO_WR_ARB_PRIORITY_3_0_TX_QFIFO_0_WR_ARB_PRIORITY_0);\r
+ prioVal[1][0] = CSL_FEXT (tmpWord [0], BCP_TM_TM_RX_QFIFO_WR_ARB_PRIORITY_3_0_TX_QFIFO_0_WR_ARB_PRIORITY_1);\r
+ prioVal[2][0] = CSL_FEXT (tmpWord [0], BCP_TM_TM_RX_QFIFO_WR_ARB_PRIORITY_3_0_TX_QFIFO_0_WR_ARB_PRIORITY_2);\r
+ prioVal[3][0] = CSL_FEXT (tmpWord [0], BCP_TM_TM_RX_QFIFO_WR_ARB_PRIORITY_3_0_TX_QFIFO_0_WR_ARB_PRIORITY_3);\r
+ prioVal[0][1] = CSL_FEXT (tmpWord [0], BCP_TM_TM_RX_QFIFO_WR_ARB_PRIORITY_3_0_TX_QFIFO_1_WR_ARB_PRIORITY_0);\r
+ prioVal[1][1] = CSL_FEXT (tmpWord [0], BCP_TM_TM_RX_QFIFO_WR_ARB_PRIORITY_3_0_TX_QFIFO_1_WR_ARB_PRIORITY_1);\r
+ prioVal[2][1] = CSL_FEXT (tmpWord [0], BCP_TM_TM_RX_QFIFO_WR_ARB_PRIORITY_3_0_TX_QFIFO_1_WR_ARB_PRIORITY_2);\r
+ prioVal[3][1] = CSL_FEXT (tmpWord [0], BCP_TM_TM_RX_QFIFO_WR_ARB_PRIORITY_3_0_TX_QFIFO_1_WR_ARB_PRIORITY_3);\r
+ prioVal[0][2] = CSL_FEXT (tmpWord [0], BCP_TM_TM_RX_QFIFO_WR_ARB_PRIORITY_3_0_TX_QFIFO_2_WR_ARB_PRIORITY_0);\r
+ prioVal[1][2] = CSL_FEXT (tmpWord [0], BCP_TM_TM_RX_QFIFO_WR_ARB_PRIORITY_3_0_TX_QFIFO_2_WR_ARB_PRIORITY_1);\r
+ prioVal[2][2] = CSL_FEXT (tmpWord [0], BCP_TM_TM_RX_QFIFO_WR_ARB_PRIORITY_3_0_TX_QFIFO_2_WR_ARB_PRIORITY_2);\r
+ prioVal[3][2] = CSL_FEXT (tmpWord [0], BCP_TM_TM_RX_QFIFO_WR_ARB_PRIORITY_3_0_TX_QFIFO_2_WR_ARB_PRIORITY_3);\r
+ prioVal[0][3] = CSL_FEXT (tmpWord [0], BCP_TM_TM_RX_QFIFO_WR_ARB_PRIORITY_3_0_TX_QFIFO_3_WR_ARB_PRIORITY_0);\r
+ prioVal[1][3] = CSL_FEXT (tmpWord [0], BCP_TM_TM_RX_QFIFO_WR_ARB_PRIORITY_3_0_TX_QFIFO_3_WR_ARB_PRIORITY_1);\r
+ prioVal[2][3] = CSL_FEXT (tmpWord [0], BCP_TM_TM_RX_QFIFO_WR_ARB_PRIORITY_3_0_TX_QFIFO_3_WR_ARB_PRIORITY_2);\r
+ prioVal[3][3] = CSL_FEXT (tmpWord [0], BCP_TM_TM_RX_QFIFO_WR_ARB_PRIORITY_3_0_TX_QFIFO_3_WR_ARB_PRIORITY_3);\r
+\r
+ prioVal[0][4] = CSL_FEXT (tmpWord [1], BCP_TM_TM_RX_QFIFO_WR_ARB_PRIORITY_7_4_TX_QFIFO_4_WR_ARB_PRIORITY_0);\r
+ prioVal[1][4] = CSL_FEXT (tmpWord [1], BCP_TM_TM_RX_QFIFO_WR_ARB_PRIORITY_7_4_TX_QFIFO_4_WR_ARB_PRIORITY_1);\r
+ prioVal[2][4] = CSL_FEXT (tmpWord [1], BCP_TM_TM_RX_QFIFO_WR_ARB_PRIORITY_7_4_TX_QFIFO_4_WR_ARB_PRIORITY_2);\r
+ prioVal[3][4] = CSL_FEXT (tmpWord [1], BCP_TM_TM_RX_QFIFO_WR_ARB_PRIORITY_7_4_TX_QFIFO_4_WR_ARB_PRIORITY_3);\r
+ prioVal[0][5] = CSL_FEXT (tmpWord [1], BCP_TM_TM_RX_QFIFO_WR_ARB_PRIORITY_7_4_TX_QFIFO_5_WR_ARB_PRIORITY_0);\r
+ prioVal[1][5] = CSL_FEXT (tmpWord [1], BCP_TM_TM_RX_QFIFO_WR_ARB_PRIORITY_7_4_TX_QFIFO_5_WR_ARB_PRIORITY_1);\r
+ prioVal[2][5] = CSL_FEXT (tmpWord [1], BCP_TM_TM_RX_QFIFO_WR_ARB_PRIORITY_7_4_TX_QFIFO_5_WR_ARB_PRIORITY_2);\r
+ prioVal[3][5] = CSL_FEXT (tmpWord [1], BCP_TM_TM_RX_QFIFO_WR_ARB_PRIORITY_7_4_TX_QFIFO_5_WR_ARB_PRIORITY_3);\r
+ prioVal[0][6] = CSL_FEXT (tmpWord [1], BCP_TM_TM_RX_QFIFO_WR_ARB_PRIORITY_7_4_TX_QFIFO_6_WR_ARB_PRIORITY_0);\r
+ prioVal[1][6] = CSL_FEXT (tmpWord [1], BCP_TM_TM_RX_QFIFO_WR_ARB_PRIORITY_7_4_TX_QFIFO_6_WR_ARB_PRIORITY_1);\r
+ prioVal[2][6] = CSL_FEXT (tmpWord [1], BCP_TM_TM_RX_QFIFO_WR_ARB_PRIORITY_7_4_TX_QFIFO_6_WR_ARB_PRIORITY_2);\r
+ prioVal[3][6] = CSL_FEXT (tmpWord [1], BCP_TM_TM_RX_QFIFO_WR_ARB_PRIORITY_7_4_TX_QFIFO_6_WR_ARB_PRIORITY_3);\r
+ prioVal[0][7] = CSL_FEXT (tmpWord [1], BCP_TM_TM_RX_QFIFO_WR_ARB_PRIORITY_7_4_TX_QFIFO_7_WR_ARB_PRIORITY_0);\r
+ prioVal[1][7] = CSL_FEXT (tmpWord [1], BCP_TM_TM_RX_QFIFO_WR_ARB_PRIORITY_7_4_TX_QFIFO_7_WR_ARB_PRIORITY_1);\r
+ prioVal[2][7] = CSL_FEXT (tmpWord [1], BCP_TM_TM_RX_QFIFO_WR_ARB_PRIORITY_7_4_TX_QFIFO_7_WR_ARB_PRIORITY_2);\r
+ prioVal[3][7] = CSL_FEXT (tmpWord [1], BCP_TM_TM_RX_QFIFO_WR_ARB_PRIORITY_7_4_TX_QFIFO_7_WR_ARB_PRIORITY_3);\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * ============================================================================\r
+ * @n@b Bcp_setRxCdmaWriteArbPrioReg\r
+ *\r
+ * @b brief\r
+ * @n This API sets up the contents of TM_RX_CDMAHP_WR_ARB_PRIORITY register.\r
+ * This API sets up priorities for cdmahp_wr_arb writes to the\r
+ * CDMAHPs.\r
+ *\r
+ * @param[in] \r
+ pBcpLldObj BCP LLD instance object.\r
+\r
+ * @param[in] \r
+ prioVal Priority values to configure for writing CDMAHP for\r
+ BCP Tx queues 0..7\r
+\r
+ * @return int32_t\r
+ * @li -1 - Invalid BCP instance handle passed.\r
+ * @li 0 - Success.\r
+ *\r
+ * @pre\r
+ * @n @a Bcp_lldOpen () must be called to obtain the register overlay handle for \r
+ * BCP instance before calling this API. \r
+ *\r
+ * @post\r
+ * @n TM_RX_CDMAHP_WR_ARB_PRIORITY register configured with the values passed.\r
+ * ============================================================================\r
+ */\r
+static inline int32_t Bcp_setRxCdmaWriteArbPrioReg \r
+(\r
+ Bcp_LldObj* pBcpLldObj,\r
+ uint8_t prioVal[8]\r
+)\r
+{\r
+ CSL_Bcp_tmRegs* pTmRegs;\r
+\r
+ if (!pBcpLldObj || !pBcpLldObj->modCfgRegs[0])\r
+ return -1;\r
+\r
+ pTmRegs = (CSL_Bcp_tmRegs *) (pBcpLldObj->modCfgRegs[Bcp_ModuleId_TM]);\r
+ \r
+ pTmRegs->TM_RX_CDMAHP_WR_ARB_PRIORITY = \r
+ CSL_FMK (BCP_TM_TM_RX_CDMAHP_WR_ARBPRIORITY_RX_CDMAHP_WR_ARB_PRIORITY_0, prioVal[0]) |\r
+ CSL_FMK (BCP_TM_TM_RX_CDMAHP_WR_ARBPRIORITY_RX_CDMAHP_WR_ARB_PRIORITY_1, prioVal[1]) |\r
+ CSL_FMK (BCP_TM_TM_RX_CDMAHP_WR_ARBPRIORITY_RX_CDMAHP_WR_ARB_PRIORITY_2, prioVal[2]) |\r
+ CSL_FMK (BCP_TM_TM_RX_CDMAHP_WR_ARBPRIORITY_RX_CDMAHP_WR_ARB_PRIORITY_3, prioVal[3]) |\r
+ CSL_FMK (BCP_TM_TM_RX_CDMAHP_WR_ARBPRIORITY_RX_CDMAHP_WR_ARB_PRIORITY_4, prioVal[4]) |\r
+ CSL_FMK (BCP_TM_TM_RX_CDMAHP_WR_ARBPRIORITY_RX_CDMAHP_WR_ARB_PRIORITY_5, prioVal[5]) |\r
+ CSL_FMK (BCP_TM_TM_RX_CDMAHP_WR_ARBPRIORITY_RX_CDMAHP_WR_ARB_PRIORITY_6, prioVal[6]) |\r
+ CSL_FMK (BCP_TM_TM_RX_CDMAHP_WR_ARBPRIORITY_RX_CDMAHP_WR_ARB_PRIORITY_7, prioVal[7]);\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * ============================================================================\r
+ * @n@b Bcp_getRxCdmaWriteArbPrioReg\r
+ *\r
+ * @b brief\r
+ * @n This API returns the contents of TM_RX_CDMAHP_WR_ARB_PRIORITY register.\r
+ *\r
+ * @param[in] \r
+ pBcpLldObj BCP LLD instance object.\r
+\r
+ * @param[out] \r
+ prioVal Priority values for writing CDMAHP for Tx queues 0..7.\r
+\r
+ * @return int32_t\r
+ * @li -1 - Invalid BCP instance handle passed.\r
+ * @li 0 - Success.\r
+ *\r
+ * @pre\r
+ * @n @a Bcp_lldOpen () must be called to obtain the register overlay handle for \r
+ * BCP instance before calling this API. \r
+ *\r
+ * @post\r
+ * @n None.\r
+ * ============================================================================\r
+ */\r
+static inline int32_t Bcp_getRxCdmaWriteArbPrioReg \r
+(\r
+ Bcp_LldObj* pBcpLldObj,\r
+ uint8_t prioVal[8]\r
+)\r
+{\r
+ uint32_t tmpWord;\r
+ CSL_Bcp_tmRegs* pTmRegs;\r
+\r
+ if (!pBcpLldObj || !pBcpLldObj->modCfgRegs[0])\r
+ return -1;\r
+\r
+ pTmRegs = (CSL_Bcp_tmRegs *) (pBcpLldObj->modCfgRegs[Bcp_ModuleId_TM]);\r
+ tmpWord = pTmRegs->TM_RX_CDMAHP_WR_ARB_PRIORITY;\r
+\r
+ prioVal[0] = CSL_FEXT (tmpWord, BCP_TM_TM_RX_CDMAHP_WR_ARBPRIORITY_RX_CDMAHP_WR_ARB_PRIORITY_0);\r
+ prioVal[1] = CSL_FEXT (tmpWord, BCP_TM_TM_RX_CDMAHP_WR_ARBPRIORITY_RX_CDMAHP_WR_ARB_PRIORITY_1);\r
+ prioVal[2] = CSL_FEXT (tmpWord, BCP_TM_TM_RX_CDMAHP_WR_ARBPRIORITY_RX_CDMAHP_WR_ARB_PRIORITY_2);\r
+ prioVal[3] = CSL_FEXT (tmpWord, BCP_TM_TM_RX_CDMAHP_WR_ARBPRIORITY_RX_CDMAHP_WR_ARB_PRIORITY_3);\r
+ prioVal[4] = CSL_FEXT (tmpWord, BCP_TM_TM_RX_CDMAHP_WR_ARBPRIORITY_RX_CDMAHP_WR_ARB_PRIORITY_4);\r
+ prioVal[5] = CSL_FEXT (tmpWord, BCP_TM_TM_RX_CDMAHP_WR_ARBPRIORITY_RX_CDMAHP_WR_ARB_PRIORITY_5);\r
+ prioVal[6] = CSL_FEXT (tmpWord, BCP_TM_TM_RX_CDMAHP_WR_ARBPRIORITY_RX_CDMAHP_WR_ARB_PRIORITY_6);\r
+ prioVal[7] = CSL_FEXT (tmpWord, BCP_TM_TM_RX_CDMAHP_WR_ARBPRIORITY_RX_CDMAHP_WR_ARB_PRIORITY_7);\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * ============================================================================\r
+ * @n@b Bcp_getCdmaDescStarveStatus\r
+ *\r
+ * @b brief\r
+ * @n This API returns the contents of Starve_Status field from the register \r
+ * CDMA_DESC_STARVE_STATUS.\r
+ *\r
+ * @param[in]\r
+ pBcpLldObj BCP LLD instance object.\r
+\r
+ * @param[in]\r
+ rxChNum Rx Channel number for which the descriptor\r
+ starvation status. Takes values from 0..7.\r
+\r
+ * @return int32_t\r
+ * @li -1 - Invalid BCP instance handle passed.\r
+ * @li 0 - Success.\r
+ *\r
+ * @pre\r
+ * @n @a Bcp_lldOpen () must be called to obtain the register overlay handle for \r
+ * BCP instance before calling this API. \r
+ *\r
+ * @post\r
+ * @n None.\r
+ * ============================================================================\r
+ */\r
+static inline int32_t Bcp_getCdmaDescStarveStatus\r
+(\r
+ Bcp_LldObj* pBcpLldObj,\r
+ uint8_t rxChNum\r
+)\r
+{\r
+ CSL_Bcp_tmRegs* pTmRegs;\r
+ int32_t retVal;\r
+\r
+ if (!pBcpLldObj || !pBcpLldObj->modCfgRegs[0] || (rxChNum > 7))\r
+ return -1;\r
+\r
+ pTmRegs = (CSL_Bcp_tmRegs *) (pBcpLldObj->modCfgRegs[Bcp_ModuleId_TM]);\r
+\r
+ switch(rxChNum)\r
+ {\r
+ case 0:\r
+ retVal = CSL_FEXT (pTmRegs->CDMA_DESC_STARVE_STATUS, BCP_TM_CDMA_DESC_STARVE_STATUS_DESC_STARVE_0);\r
+ break;\r
+ case 1:\r
+ retVal = CSL_FEXT (pTmRegs->CDMA_DESC_STARVE_STATUS, BCP_TM_CDMA_DESC_STARVE_STATUS_DESC_STARVE_1);\r
+ break;\r
+ case 2:\r
+ retVal = CSL_FEXT (pTmRegs->CDMA_DESC_STARVE_STATUS, BCP_TM_CDMA_DESC_STARVE_STATUS_DESC_STARVE_2);\r
+ break;\r
+ case 3:\r
+ retVal = CSL_FEXT (pTmRegs->CDMA_DESC_STARVE_STATUS, BCP_TM_CDMA_DESC_STARVE_STATUS_DESC_STARVE_3);\r
+ break;\r
+ case 4:\r
+ retVal = CSL_FEXT (pTmRegs->CDMA_DESC_STARVE_STATUS, BCP_TM_CDMA_DESC_STARVE_STATUS_DESC_STARVE_4);\r
+ break;\r
+ case 5:\r
+ retVal = CSL_FEXT (pTmRegs->CDMA_DESC_STARVE_STATUS, BCP_TM_CDMA_DESC_STARVE_STATUS_DESC_STARVE_5);\r
+ break;\r
+ case 6:\r
+ retVal = CSL_FEXT (pTmRegs->CDMA_DESC_STARVE_STATUS, BCP_TM_CDMA_DESC_STARVE_STATUS_DESC_STARVE_6);\r
+ break;\r
+ case 7:\r
+ retVal = CSL_FEXT (pTmRegs->CDMA_DESC_STARVE_STATUS, BCP_TM_CDMA_DESC_STARVE_STATUS_DESC_STARVE_7);\r
+ break;\r
+ default:\r
+ retVal = 0;\r
+ break;\r
+ }\r
+\r
+ return retVal;\r
+}\r
+\r
+/**\r
+ * ============================================================================\r
+ * @n@b Bcp_setCdmaDescStarveClear\r
+ *\r
+ * @b brief\r
+ * @n This API force clear the specified RX channel description starvation\r
+ in "Starve_Status" field in the register CDMA_DESC_STARVE_STATUS.\r
+ *\r
+ * @param[in]\r
+ pBcpLldObj BCP LLD instance object.\r
+\r
+ * @param[in]\r
+ rxChNum Rx Channel number for which the descriptor\r
+ starvation status. Takes values from 0..7.\r
+\r
+ * @return int32_t\r
+ * @li -1 - Invalid BCP instance handle passed.\r
+ * @li 0 - Success.\r
+ *\r
+ * @pre\r
+ * @n @a Bcp_lldOpen () must be called to obtain the register overlay handle for \r
+ * BCP instance before calling this API. \r
+ *\r
+ * @post\r
+ * @n None.\r
+ * ============================================================================\r
+ */\r
+static inline int32_t Bcp_setCdmaDescStarveClear\r
+(\r
+ Bcp_LldObj* pBcpLldObj,\r
+ uint8_t rxChNum\r
+)\r
+{\r
+ CSL_Bcp_tmRegs* pTmRegs;\r
+\r
+ if (!pBcpLldObj || !pBcpLldObj->modCfgRegs[0] || (rxChNum > 7))\r
+ return -1;\r
+\r
+ pTmRegs = (CSL_Bcp_tmRegs *) (pBcpLldObj->modCfgRegs[Bcp_ModuleId_TM]);\r
+\r
+ switch(rxChNum)\r
+ {\r
+ case 0:\r
+ CSL_FINS (pTmRegs->CDMA_DESC_STARVE_CLEAR, BCP_TM_CDMA_DESC_STARVE_CLEAR_DESC_STARVE_0, 1);\r
+ break;\r
+ case 1:\r
+ CSL_FINS (pTmRegs->CDMA_DESC_STARVE_CLEAR, BCP_TM_CDMA_DESC_STARVE_CLEAR_DESC_STARVE_1, 1);\r
+ break;\r
+ case 2:\r
+ CSL_FINS (pTmRegs->CDMA_DESC_STARVE_CLEAR, BCP_TM_CDMA_DESC_STARVE_CLEAR_DESC_STARVE_2, 1);\r
+ break;\r
+ case 3:\r
+ CSL_FINS (pTmRegs->CDMA_DESC_STARVE_CLEAR, BCP_TM_CDMA_DESC_STARVE_CLEAR_DESC_STARVE_3, 1);\r
+ break;\r
+ case 4:\r
+ CSL_FINS (pTmRegs->CDMA_DESC_STARVE_CLEAR, BCP_TM_CDMA_DESC_STARVE_CLEAR_DESC_STARVE_4, 1);\r
+ break;\r
+ case 5:\r
+ CSL_FINS (pTmRegs->CDMA_DESC_STARVE_CLEAR, BCP_TM_CDMA_DESC_STARVE_CLEAR_DESC_STARVE_5, 1);\r
+ break;\r
+ case 6:\r
+ CSL_FINS (pTmRegs->CDMA_DESC_STARVE_CLEAR, BCP_TM_CDMA_DESC_STARVE_CLEAR_DESC_STARVE_6, 1);\r
+ break;\r
+ case 7:\r
+ CSL_FINS (pTmRegs->CDMA_DESC_STARVE_CLEAR, BCP_TM_CDMA_DESC_STARVE_CLEAR_DESC_STARVE_7, 1);\r
+ break;\r
+ default: \r
+ break;\r
+ }\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * ============================================================================\r
+ * @n@b Bcp_setCdmaDescStarveSet\r
+ *\r
+ * @b brief\r
+ * @n This API force set the specified RX channel description starvation\r
+ in "Starve_Status" field in the register CDMA_DESC_STARVE_STATUS.\r
+ *\r
+ * @param[in]\r
+ pBcpLldObj BCP LLD instance object.\r
+\r
+ * @param[in]\r
+ rxChNum Rx Channel number for which the descriptor\r
+ starvation status. Takes values from 0..7.\r
+\r
+ * @return int32_t\r
+ * @li -1 - Invalid BCP instance handle passed.\r
+ * @li 0 - Success.\r
+ *\r
+ * @pre\r
+ * @n @a Bcp_lldOpen () must be called to obtain the register overlay handle for \r
+ * BCP instance before calling this API. \r
+ *\r
+ * @post\r
+ * @n None.\r
+ * ============================================================================\r
+ */\r
+static inline int32_t Bcp_setCdmaDescStarveSet\r
+(\r
+ Bcp_LldObj* pBcpLldObj,\r
+ uint8_t rxChNum\r
+)\r
+{\r
+ CSL_Bcp_tmRegs* pTmRegs;\r
+\r
+ if (!pBcpLldObj || !pBcpLldObj->modCfgRegs[0] || (rxChNum > 7))\r
+ return -1;\r
+\r
+ pTmRegs = (CSL_Bcp_tmRegs *) (pBcpLldObj->modCfgRegs[Bcp_ModuleId_TM]);\r
+\r
+ switch(rxChNum)\r
+ {\r
+ case 0:\r
+ CSL_FINS (pTmRegs->CDMA_DESC_STARVE_SET, BCP_TM_CDMA_DESC_STARVE_SET_DESC_STARVE_0, 1);\r
+ break;\r
+ case 1:\r
+ CSL_FINS (pTmRegs->CDMA_DESC_STARVE_SET, BCP_TM_CDMA_DESC_STARVE_SET_DESC_STARVE_1, 1);\r
+ break;\r
+ case 2:\r
+ CSL_FINS (pTmRegs->CDMA_DESC_STARVE_SET, BCP_TM_CDMA_DESC_STARVE_SET_DESC_STARVE_2, 1);\r
+ break; \r
+ case 3:\r
+ CSL_FINS (pTmRegs->CDMA_DESC_STARVE_SET, BCP_TM_CDMA_DESC_STARVE_SET_DESC_STARVE_3, 1);\r
+ break;\r
+ case 4:\r
+ CSL_FINS (pTmRegs->CDMA_DESC_STARVE_SET, BCP_TM_CDMA_DESC_STARVE_SET_DESC_STARVE_4, 1);\r
+ break;\r
+ case 5:\r
+ CSL_FINS (pTmRegs->CDMA_DESC_STARVE_SET, BCP_TM_CDMA_DESC_STARVE_SET_DESC_STARVE_5, 1);\r
+ break;\r
+ case 6:\r
+ CSL_FINS (pTmRegs->CDMA_DESC_STARVE_SET, BCP_TM_CDMA_DESC_STARVE_SET_DESC_STARVE_6, 1);\r
+ break;\r
+ case 7:\r
+ CSL_FINS (pTmRegs->CDMA_DESC_STARVE_SET, BCP_TM_CDMA_DESC_STARVE_SET_DESC_STARVE_7, 1);\r
+ break;\r
+ default:\r
+ break;\r
+ }\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * ============================================================================\r
+ * @n@b Bcp_setCdmaDescStarveInterruptSelect\r
+ *\r
+ * @b brief\r
+ * @n This API force set the specified RX channel description starvation\r
+ in "Starve_Status" field in the register CDMA_DESC_STARVE_INTR_SEL.\r
+ *\r
+ * @param[in]\r
+ pBcpLldObj BCP LLD instance object.\r
+\r
+ * @param[in]\r
+ rxChNum Rx Channel number selection from 0..7.\r
+\r
+ * @param[in]\r
+ dspNum DSP number from 0..3.\r
+\r
+ * @return int32_t\r
+ * @li -1 - Invalid BCP instance handle passed.\r
+ * @li 0 - Success.\r
+ *\r
+ * @pre\r
+ * @n @a Bcp_lldOpen () must be called to obtain the register overlay handle for \r
+ * BCP instance before calling this API. \r
+ *\r
+ * @post\r
+ * @n None.\r
+ * ============================================================================\r
+ */\r
+static inline int32_t Bcp_setCdmaDescStarveInterruptSelect\r
+(\r
+ Bcp_LldObj* pBcpLldObj,\r
+ uint8_t rxChNum,\r
+ uint8_t dspNum\r
+)\r
+{\r
+ CSL_Bcp_tmRegs* pTmRegs;\r
+\r
+ if (!pBcpLldObj || !pBcpLldObj->modCfgRegs[0] || (rxChNum > 7) || (dspNum > 3))\r
+ return -1;\r
+\r
+ pTmRegs = (CSL_Bcp_tmRegs *) (pBcpLldObj->modCfgRegs[Bcp_ModuleId_TM]);\r
+\r
+ switch(rxChNum)\r
+ {\r
+ case 0:\r
+ CSL_FINS (pTmRegs->CDMA_DESC_STARVE_INTR_SEL, BCP_TM_CDMA_DESC_STARVE_INTR_SEL_DESC_STARVE_0, 1 << dspNum);\r
+ break;\r
+ case 1:\r
+ CSL_FINS (pTmRegs->CDMA_DESC_STARVE_INTR_SEL, BCP_TM_CDMA_DESC_STARVE_INTR_SEL_DESC_STARVE_1, 1 << dspNum);\r
+ break;\r
+ case 2:\r
+ CSL_FINS (pTmRegs->CDMA_DESC_STARVE_INTR_SEL, BCP_TM_CDMA_DESC_STARVE_INTR_SEL_DESC_STARVE_2, 1 << dspNum);\r
+ break;\r
+ case 3:\r
+ CSL_FINS (pTmRegs->CDMA_DESC_STARVE_INTR_SEL, BCP_TM_CDMA_DESC_STARVE_INTR_SEL_DESC_STARVE_3, 1 << dspNum);\r
+ break;\r
+ case 4:\r
+ CSL_FINS (pTmRegs->CDMA_DESC_STARVE_INTR_SEL, BCP_TM_CDMA_DESC_STARVE_INTR_SEL_DESC_STARVE_4, 1 << dspNum);\r
+ break;\r
+ case 5:\r
+ CSL_FINS (pTmRegs->CDMA_DESC_STARVE_INTR_SEL, BCP_TM_CDMA_DESC_STARVE_INTR_SEL_DESC_STARVE_5, 1 << dspNum);\r
+ break;\r
+ case 6:\r
+ CSL_FINS (pTmRegs->CDMA_DESC_STARVE_INTR_SEL, BCP_TM_CDMA_DESC_STARVE_INTR_SEL_DESC_STARVE_6, 1 << dspNum);\r
+ break;\r
+ case 7:\r
+ CSL_FINS (pTmRegs->CDMA_DESC_STARVE_INTR_SEL, BCP_TM_CDMA_DESC_STARVE_INTR_SEL_DESC_STARVE_7, 1 << dspNum);\r
+ break;\r
+ default: \r
+ break;\r
+ }\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * ============================================================================\r
+ * @n@b Bcp_setHaltOnErrorReg\r
+ *\r
+ * @b brief\r
+ * @n This API sets up the contents of BCP_HALT_ON_ERROR register.\r
+ *\r
+ * @param[in] \r
+ pBcpLldObj BCP LLD instance object.\r
+\r
+ * @param[in] \r
+ index Indicates which of the 4 Halt on error registers\r
+ to configure.\r
+\r
+ * @param[in] \r
+ pHaltCfg Halt on error settings for all BCP submodules\r
+\r
+* @param[in] \r
+ bForceHalt Boolean flag that indicates if a forced halt must\r
+ be initiated.\r
+\r
+ * @return int32_t\r
+ * @li -1 - Invalid BCP instance handle passed.\r
+ * @li 0 - Success.\r
+ *\r
+ * @pre\r
+ * @n @a Bcp_lldOpen () must be called to obtain the register overlay handle for \r
+ * BCP instance before calling this API. \r
+ *\r
+ * @post\r
+ * @n BCP_HALT_ON_ERROR register configured with the values passed.\r
+ * ============================================================================\r
+ */\r
+static inline int32_t Bcp_setHaltOnErrorReg \r
+(\r
+ Bcp_LldObj* pBcpLldObj,\r
+ uint8_t index,\r
+ Bcp_ModuleCfg* pHaltCfg,\r
+ uint8_t bForceHalt\r
+)\r
+{\r
+ CSL_Bcp_tmRegs* pTmRegs;\r
+\r
+ if (!pBcpLldObj || !pBcpLldObj->modCfgRegs[0]|| !pHaltCfg)\r
+ return -1;\r
+\r
+ pTmRegs = (CSL_Bcp_tmRegs *) (pBcpLldObj->modCfgRegs[Bcp_ModuleId_TM]);\r
+ \r
+ pTmRegs->TM_SPECIAL_INTERRUPT_REGISTERS[index].BCP_HALT_ON_ERROR = \r
+ CSL_FMK (BCP_TM_BCP_HALT_ON_ERROR_TM_HALT_ON_ERROR, pHaltCfg->tm) |\r
+ CSL_FMK (BCP_TM_BCP_HALT_ON_ERROR_DIO_HALT_ON_ERROR, pHaltCfg->dio) |\r
+ CSL_FMK (BCP_TM_BCP_HALT_ON_ERROR_CRC_HALT_ON_ERROR, pHaltCfg->crc) |\r
+ CSL_FMK (BCP_TM_BCP_HALT_ON_ERROR_ENC_HALT_ON_ERROR, pHaltCfg->enc) |\r
+ CSL_FMK (BCP_TM_BCP_HALT_ON_ERROR_RM_HALT_ON_ERROR, pHaltCfg->rm) |\r
+ CSL_FMK (BCP_TM_BCP_HALT_ON_ERROR_MOD_HALT_ON_ERROR, pHaltCfg->mod) |\r
+ CSL_FMK (BCP_TM_BCP_HALT_ON_ERROR_INT_HALT_ON_ERROR, pHaltCfg->intleaver) |\r
+ CSL_FMK (BCP_TM_BCP_HALT_ON_ERROR_COR_HALT_ON_ERROR, pHaltCfg->cor) |\r
+ CSL_FMK (BCP_TM_BCP_HALT_ON_ERROR_SSL_HALT_ON_ERROR, pHaltCfg->ssl) |\r
+ CSL_FMK (BCP_TM_BCP_HALT_ON_ERROR_RD_HALT_ON_ERROR, pHaltCfg->rd) |\r
+ CSL_FMK (BCP_TM_BCP_HALT_ON_ERROR_DNT_HALT_ON_ERROR, pHaltCfg->dnt) |\r
+ CSL_FMK (BCP_TM_BCP_HALT_ON_ERROR_FRC_HALT_ON_ERROR, bForceHalt);\r
+\r
+ return 0;\r
+}\r
+\r
+/**\r
+ * ============================================================================\r
+ * @n@b Bcp_getHaltOnErrorReg\r
+ *\r
+ * @b brief\r
+ * @n This API returns the contents of BCP_HALT_ON_ERROR register.\r
+ *\r
+ * @param[in] \r
+ pBcpLldObj BCP LLD instance object.\r
+\r
+ * @param[in] \r
+ index Indicates which of the 4 Halt on error registers\r
+ to read.\r
+\r
+ * @param[out] \r
+ pHaltCfg Halt on error settings for all BCP submodules\r
+\r
+* @param[out] \r
+ pForceHaltEnabled 1 indicates Forced halt is enabled and 0 indicates\r<