qspi/tpr12: bug fixes for DMA mode support
authorBadri S <badri@ti.com>
Wed, 28 Oct 2020 23:02:54 +0000 (04:32 +0530)
committerSivaraj R <sivaraj@ti.com>
Sat, 31 Oct 2020 04:09:47 +0000 (23:09 -0500)
Bug fix for DMA mode support for QSPI and
resolve the SoC reset when SBL runs in
release mode

Signed-off-by: Badri S <badri@ti.com>
packages/ti/board/src/flash/nor/qspi/nor_qspi.h [changed mode: 0755->0644]
packages/ti/boot/sbl/board/evmTPR12/sbl_main.c
packages/ti/boot/sbl/soc/tpr12/sbl_slave_core_boot.c
packages/ti/boot/sbl/src/qspi/sbl_qspi_boardflash.c
packages/ti/drv/spi/soc/QSPI_v1.h
packages/ti/drv/spi/soc/dma/v3/QSPI_dma.c
packages/ti/drv/spi/test/qspi_flash/src/main_qspi_flash_test.c

old mode 100755 (executable)
new mode 100644 (file)
index 899bd1581a68ab2ea41a93ba67de01880f77f6da..ecdebf1da5912394e198ee3168eeda1cc03fcda8 100644 (file)
@@ -193,9 +193,9 @@ const CSL_ArmR5MpuRegionCfg gCslR5MpuCfg[CSL_ARM_R5F_MPU_REGIONS_MAX] =
         .exeNeverControl  = 1U,
         .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,
         .shareable        = 0U,
-        .cacheable        = (uint32_t)TRUE,
-        .cachePolicy      = CSL_ARM_R5_MEM_ATTR_CACHED_WT_NO_WA,
-        .memAttr          = 0U,
+        .cacheable        = (uint32_t)FALSE,
+        .cachePolicy      = 0U,
+        .memAttr          = CSL_ARM_R5_MEM_ATTR_STRONGLY_ORDERED,
     },
     {
         /* Region 8 configuration: QSPI register space */
@@ -315,7 +315,6 @@ int main()
 {
     cpu_core_id_t core_id;
 
-
     SBL_ADD_PROFILE_POINT;
     Board_init(BOARD_INIT_UNLOCK_MMR);
 
index 24f9c13c0bd4cdee098634c90d0bf68c0b10e0bd..87092a7acd7d8ba2f81a19b6aa50db17c9b1daca 100644 (file)
@@ -115,8 +115,7 @@ static void SBL_c66xWakeup(void)
     CSL_FINS(dssRcmRegs->DSP_PD_WAKEUP_MASK0, DSS_RCM_DSP_PD_WAKEUP_MASK0_DSP_PD_WAKEUP_MASK0_WAKEUP_MASK0, 0xFFFEFFFF);
     CSL_FINS(dssRcmRegs->DSP_PD_TRIGGER_WAKUP,DSS_RCM_DSP_PD_TRIGGER_WAKUP_DSP_PD_TRIGGER_WAKUP_WAKEUP_TRIGGER, 0x1);
 
-    while((CSL_FEXT(dssRcmRegs->DSP_PD_STATUS, DSS_RCM_DSP_PD_STATUS_DSP_PD_STATUS_PD_STATUS) & 0x1) != 1U);
-    (void)Osal_delay(1);
+    while((CSL_FEXT(dssRcmRegs->DSP_PD_STATUS, DSS_RCM_DSP_PD_STATUS_DSP_PD_STATUS_PROC_HALTED) & 0x1) != 1U);
 }
 
 static void SBL_c66xStart(void)
index 7db9ed0bf6b724d3a1fe14acc04e1d7bc333a9cb..ada732018913c4add4fba1bf3028d5688873b2eb 100644 (file)
@@ -189,7 +189,7 @@ int32_t SBL_qspiInit(void *handle)
     SBL_log(SBL_LOG_MAX, "qspiFunClk = %d Hz \n", qspi_cfg.funcClk);
 
 #if SBL_USE_DMA
-    qspi_cfg.dmaEnable = false;
+    qspi_cfg.dmaEnable = true;
     retVal = Qspi_edma_init();
     DebugP_assert(retVal == EDMA_NO_ERROR);
     qspi_cfg.edmaHandle =  gEdmaHandle;
@@ -228,7 +228,7 @@ int32_t SBL_qspiFlashRead(void *handle, uint8_t *dst, uint32_t length,
     uint32_t end_time = 0;
 
 #if !defined(SBL_BYPASS_QSPI_DRIVER)
-#if 0
+#if SBL_USE_DMA
     if (length > 4 * 1024)
     {
         Board_flashHandle h = *(const Board_flashHandle *) handle;
@@ -241,12 +241,14 @@ int32_t SBL_qspiFlashRead(void *handle, uint8_t *dst, uint32_t length,
 
         SBL_DCacheClean((void *)dst, length);
 
+        dst = (uint8_t *)((uintptr_t)(CSL_locToGlobAddr((uintptr_t)dst)));
         if ((non_aligned_bytes) && (Board_flashRead(h, offset, dst, non_aligned_bytes, (void *)(&ioMode))))
         {
             SBL_log(SBL_LOG_ERR, "Board_flashRead failed!\n");
             SblErrLoop(__FILE__, __LINE__);
         }
 
+        dma_dst = (uint8_t *)((uintptr_t)(CSL_locToGlobAddr((uintptr_t)dma_dst)));
         if (Board_flashRead(h, dma_offset, dma_dst, dma_len, (void *)(&ioMode)))
         {
             SBL_log(SBL_LOG_ERR, "Board_flashRead failed!\n");
index 711aeff7b046a91b9e313efc4c0c3b83fea4e316..6266f8f4b43e0c1ad24f206200eb00d509dc1662 100644 (file)
@@ -212,7 +212,7 @@ typedef struct QSPI_v1_Object_s {
     bool                  isOpen;         /* flag to indicate module is open */
 
     SPI_Transaction      *transaction;    /* transacation pointer */
-
+    volatile bool        intermediateDmaXferInitiated; /* Remaining transaction bytes */
 } QSPI_v1_Object;
 
 #ifdef SPI_DMA_ENABLE
index efe9ea08cde65e43544b58315420362e129e364a..ae7d77cfb32b116161b6c4e4ddd02885bc7c70dc 100644 (file)
@@ -92,6 +92,8 @@ int32_t QSPI_dmaConfig(SPI_Handle handle)
     return status;
 }
 
+#define QSPI_DMA_MAX_XFER_SIZE (31U * 1024U)
+
 int32_t QSPI_dmaTransfer(SPI_Handle             handle,
                          const SPI_Transaction *transaction)
 {
@@ -108,11 +110,23 @@ int32_t QSPI_dmaTransfer(SPI_Handle             handle,
 
     if(SPI_TRANSACTION_TYPE_READ == object->transactionType)
     {
-        /* RX Mode */
-        status = QSPI_dmaMemcpy(handle,
-                                (uintptr_t)transaction->rxBuf,
-                                (uintptr_t)dataPtr,
-                                transaction->count);
+        uint32_t i;
+
+        for (i = 0; i < transaction->count; i += QSPI_DMA_MAX_XFER_SIZE)
+        {
+            uint32_t xferLen = CSL_NEXT_MULTIPLE_OF(CSL_MIN((transaction->count - i), QSPI_DMA_MAX_XFER_SIZE), 4);
+
+            if (transaction->count > (i + xferLen))
+            {
+                object->intermediateDmaXferInitiated = true;
+            }
+            /* RX Mode */
+            status = QSPI_dmaMemcpy(handle,
+                                    ((uintptr_t)transaction->rxBuf + i),
+                                    ((uintptr_t)dataPtr + i),
+                                    xferLen);
+            while (object->intermediateDmaXferInitiated == true);
+        }
     }
     else
     {
@@ -158,15 +172,24 @@ static void QSPI_dmaIsrHandler (uintptr_t appData, uint8_t tcc)
     object   = (QSPI_v1_Object*)handle->object;
     hwAttrs  = (QSPI_HwAttrs*)handle->hwAttrs;
 
-    object->transaction->status = SPI_TRANSFER_COMPLETED;
-
+    if (object->intermediateDmaXferInitiated == false)
+    {
+        object->transaction->status = SPI_TRANSFER_COMPLETED;
+    }
     /* EDMA is done - disable the DMA channel */
     EDMA_disableChannel(hwAttrs->edmaHandle,
                         tcc,
                         EDMA3_CHANNEL_TYPE_DMA);
 
-    /* Call the transfer completion callback function */
-    object->qspiParams.transferCallbackFxn(handle, object->transaction);
+    if (object->intermediateDmaXferInitiated == false)
+    {
+        /* Call the transfer completion callback function */
+        object->qspiParams.transferCallbackFxn(handle, object->transaction);
+    }
+    else
+    {
+        object->intermediateDmaXferInitiated = false;
+    }
 }
 
 static void QSPI_edmaParamInit(EDMA_paramSetConfig_t *param, uint8_t tcc, uint8_t xferType)
@@ -259,16 +282,9 @@ static int32_t QSPI_dmaMemcpy(SPI_Handle     handle,
      * bCnt holds the number of such arrays to be transferred.
      * cCnt holds the number of frames of aCnt*bBcnt bytes to be transferred
      */
-    if (length < 0x8000U)
-    {
-        paramSet.paramSetConfig.bCount = (uint16_t)length;
-        paramSet.paramSetConfig.cCount = (uint16_t)1;
-    }
-    else
-    {
-        paramSet.paramSetConfig.bCount = (uint16_t)0x4000;
-        paramSet.paramSetConfig.cCount = (uint16_t)(length / paramSet.paramSetConfig.bCount);
-    }
+    DebugP_assert (length < 0x8000U);
+    paramSet.paramSetConfig.bCount = (uint16_t)length;
+    paramSet.paramSetConfig.cCount = (uint16_t)1;
     cIdx = (int32_t)paramSet.paramSetConfig.bCount;
 
     /**
index f410d89034d9d7de32a78dc7253600d05d387373..2d35ca936c42dfe1a6457d905feaa0800f05b21c 100644 (file)
@@ -699,12 +699,12 @@ int32_t QSPI_test_readInputFile(S25FL_Handle flashHandle, QSPI_Tests *test, bool
             {
                 SPI_log("\tRead flash memory at 0x%x, checking flashed content...\n", offsetAddr);
             }
-            for (i = 0; i<len; i+=4)
+            for (i = 0; i<len; i++)
             {
-                if ( (*(uint32_t *) (fileLoadBuffer + i)) != (*(uint32_t *) (fileReadBuffer + i)) )
+                if ( (*(uint8_t *) (fileLoadBuffer + i)) != (*(uint8_t *) (fileReadBuffer + i)) )
                 {
-                    SPI_log("\t\tMismatched data at offset 0x%x, expected = 0x%08x, read = 0x%08x\n",
-                        i, (*(uint32_t *) (fileLoadBuffer + i)), (*(uint32_t *) (fileReadBuffer + i)));
+                    SPI_log("\t\tMismatched data at offset 0x%x, expected = 0x%02x, read = 0x%02x\n",
+                        i, (*(uint8_t *) (fileLoadBuffer + i)), (*(uint8_t *) (fileReadBuffer + i)));
                     ret = -7;
                 }
             }
@@ -780,7 +780,7 @@ QSPI_Tests qspi_tests[] =
 #ifdef SPI_DMA_ENABLE
     {QSPI_test_func, QSPI_TEST_ID_MMAP_DMA, false,   true,   true,   "\r\n QSPI flash memory map mode with DMA enabled test", },
 #endif
-    {QSPI_test_func_file_write, QSPI_TEST_ID_MMAP_DMA, false,   false,   true,   "\r\n QSPI file write to flash and verify in mmap mode test", },
+    {QSPI_test_func_file_write, QSPI_TEST_ID_MMAP_DMA, false,   true,   true,   "\r\n QSPI file write to flash and verify in mmap mode test", },
     {NULL, },
 };