Merge pull request #31 in PROCESSOR-SDK/pdk from prsdk-7319 to master
authorMahesh Radhakrishnan <a0875154@ti.com>
Tue, 19 Nov 2019 19:05:18 +0000 (13:05 -0600)
committerMahesh Radhakrishnan <a0875154@ti.com>
Tue, 19 Nov 2019 19:05:18 +0000 (13:05 -0600)
* commit 'ad4702a862a3bc98f5f7c3bd1143ffbaf145c8b5':
  dm f/w: prsdk-7319: don't call PSI_ABORT
  dm f/w: prsdk-7319: skip PROINFO chunk as well

53 files changed:
packages/ti/board/src/am65xx_evm/am65xx_evm.c
packages/ti/board/src/am65xx_idk/am65xx_idk.c
packages/ti/board/src/evmKeystone3/board_clock.c
packages/ti/board/src/j721e_evm/board_clock.c
packages/ti/board/src/j721e_evm/board_init.c
packages/ti/build/Rules.make
packages/ti/drv/emac/build/makefile.mk
packages/ti/drv/emac/emac_component.mk
packages/ti/drv/emac/firmware/icss_dualmac/src/hd_helper.h [moved from packages/ti/drv/emac/firmware/icss_dualmac/src/psiloop.h with 53% similarity]
packages/ti/drv/emac/firmware/icss_dualmac/src/iep.h
packages/ti/drv/emac/firmware/icss_dualmac/src/makefile
packages/ti/drv/emac/firmware/icss_dualmac/src/pa_stat.h [moved from packages/ti/drv/emac/firmware/icss_dualmac/src/rtu_psi_loopback.h with 66% similarity]
packages/ti/drv/emac/firmware/icss_dualmac/src/reg_alias.h
packages/ti/drv/emac/firmware/icss_dualmac/src/rtu_psi.h
packages/ti/drv/emac/firmware/icss_dualmac/src/rtu_v2.asm
packages/ti/drv/emac/firmware/icss_dualmac/src/rxl2_txl2.asm
packages/ti/drv/emac/firmware/icss_dualmac/src/scheduler.h
packages/ti/drv/emac/firmware/icss_dualmac/src/smem.h
packages/ti/drv/emac/firmware/icss_dualmac/src/tx.h
packages/ti/drv/emac/firmware/icss_dualmac/src/xfr2vbus_widget.h
packages/ti/drv/emac/src/src_files_common.mk
packages/ti/drv/emac/src/v5/emac_drv_v5.c
packages/ti/drv/emac/src/v5/emac_ioctl.c
packages/ti/drv/emac/src/v5/emac_osal_v5.h
packages/ti/drv/emac/src/v5/emac_utils.c
packages/ti/drv/emac/test/EmacLoopbackTest/test_utils_k3.c
packages/ti/drv/gpio/test/led_blink/src/GPIO_board.h
packages/ti/drv/i2c/test/eeprom_read/src/main_test.c
packages/ti/drv/ipc/ipc.h
packages/ti/drv/ipc/soc/V0/ipc_soc.c
packages/ti/drv/ipc/soc/V1/ipc_soc.c
packages/ti/drv/ipc/soc/ipc_soc.h
packages/ti/drv/ipc/src/ipc_api.c
packages/ti/drv/pruss/example/apps/icssg_pwm/firmware/src/iepPwmHwRegs.h
packages/ti/transport/ndk/nimu/build/makefile.mk
packages/ti/transport/ndk/nimu/build/makefile_profile.mk
packages/ti/transport/ndk/nimu/example/helloWorld/src/helloWorld.c
packages/ti/transport/ndk/nimu/makefile
packages/ti/transport/ndk/nimu/nimu_ver.h
packages/ti/transport/ndk/nimu/src/NIMU_drv_log.h
packages/ti/transport/ndk/nimu/src/v2/nimu_eth.c
packages/ti/transport/ndk/nimu/src/v3/nimu_eth.c
packages/ti/transport/ndk/nimu/src/v5/nimu_eth.c
packages/ti/transport/ndk/nimu/src/v5/nimu_internal.h
packages/ti/transport/ndk/nimu/src/v7/nimu_eth.c
packages/ti/transport/ndk/nimu_icss/build/makefile_indp.mk
packages/ti/transport/ndk/nimu_icss/build/makefile_profile_indp.mk
packages/ti/transport/ndk/nimu_icss/config.bld
packages/ti/transport/ndk/nimu_icss/makefile
packages/ti/transport/ndk/nimu_icss/nimu_icssEth.h
packages/ti/transport/ndk/nimu_icss/src/nimu_icssEth.c
packages/ti/transport/ndk/nimu_icss/src/nimu_icssSwitchEmac.c
packages/ti/utils/profiling/src/profilingHooksR5.c

index 447e00fd3050fdd0468add0d8c559effdff44dd1..2102fae64bd7b5cf8911c22fb8f2d4936e7a6fd5 100644 (file)
@@ -76,36 +76,6 @@ static Board_STATUS Board_sysInit(void)
     {
         Sciclient_configPrmsInit(&config);
         ret = Sciclient_init(&config);
-
-#if defined(__TI_ARM_V7R4__)
-        uint64_t mcuClkFreq;
-
-        if(ret == 0)
-        {
-            ret = Sciclient_pmGetModuleClkFreq(TISCI_DEV_MCU_ARMSS0_CPU0,
-                                               TISCI_DEV_MCU_ARMSS0_CPU0_BUS_CPU_CLK,
-                                               &mcuClkFreq,
-                                               SCICLIENT_SERVICE_WAIT_FOREVER);
-        }
-        if(ret == 0)
-        {
-            Osal_HwAttrs  hwAttrs;
-            uint32_t      ctrlBitmap;
-
-            ret = Osal_getHwAttrs(&hwAttrs);
-            if(ret == 0)
-            {
-                /*
-                 * Change the timer input clock frequency configuration
-                   based on R5 CPU clock configured
-                 */
-                hwAttrs.cpuFreqKHz = (int32_t)(mcuClkFreq/1000U);
-                ctrlBitmap         = OSAL_HWATTR_SET_CPU_FREQ;
-                ret = Osal_setHwAttrs(ctrlBitmap, &hwAttrs);
-            }
-        }
-#endif
-
         if(ret != 0)
         {
             status = BOARD_FAIL;
index fefa0e3937cfeeb40757ac1219c2ee063a827cfb..ecbc59a2d7937ee53279025016eb44d3c6077643 100644 (file)
@@ -76,36 +76,6 @@ static Board_STATUS Board_sysInit(void)
     {
         Sciclient_configPrmsInit(&config);
         ret = Sciclient_init(&config);
-
-#if defined(__TI_ARM_V7R4__)
-        uint64_t mcuClkFreq;
-
-        if(ret == 0)
-        {
-            ret = Sciclient_pmGetModuleClkFreq(TISCI_DEV_MCU_ARMSS0_CPU0,
-                                               TISCI_DEV_MCU_ARMSS0_CPU0_BUS_CPU_CLK,
-                                               &mcuClkFreq,
-                                               SCICLIENT_SERVICE_WAIT_FOREVER);
-        }
-        if(ret == 0)
-        {
-            Osal_HwAttrs  hwAttrs;
-            uint32_t      ctrlBitmap;
-
-            ret = Osal_getHwAttrs(&hwAttrs);
-            if(ret == 0)
-            {
-                /*
-                 * Change the timer input clock frequency configuration
-                   based on R5 CPU clock configured
-                 */
-                hwAttrs.cpuFreqKHz = (int32_t)(mcuClkFreq/1000U);
-                ctrlBitmap         = OSAL_HWATTR_SET_CPU_FREQ;
-                ret = Osal_setHwAttrs(ctrlBitmap, &hwAttrs);
-            }
-        }
-#endif
-
         if(ret != 0)
         {
             status = BOARD_FAIL;
index 761aa2f0bfe978123c994e35894ed28c1412ef21..99dde0bce02af8cc13cc52b9779aa86b2fdb4d2b 100644 (file)
@@ -372,9 +372,44 @@ Board_STATUS Board_moduleClockInit(void)
         status = Board_moduleClockEnable(gBoardClkModuleID[index]);
         if(status != BOARD_SOK)
         {
-            return BOARD_INIT_CLOCK_FAIL;
+            status = BOARD_INIT_CLOCK_FAIL;
+            break;
+        }
+    }
+
+#if defined(__TI_ARM_V7R4__)
+    if(status == BOARD_SOK)
+    {
+        int32_t  ret;
+        uint64_t mcuClkFreq;
+
+        ret = Sciclient_pmGetModuleClkFreq(TISCI_DEV_MCU_ARMSS0_CPU0,
+                                           TISCI_DEV_MCU_ARMSS0_CPU0_BUS_CPU_CLK,
+                                           &mcuClkFreq,
+                                           SCICLIENT_SERVICE_WAIT_FOREVER);
+        if(ret == 0)
+        {
+            Osal_HwAttrs  hwAttrs;
+            uint32_t      ctrlBitmap;
+
+            ret = Osal_getHwAttrs(&hwAttrs);
+            if(ret == 0)
+            {
+                /*
+                 * Change the timer input clock frequency configuration
+                   based on R5 CPU clock configured
+                 */
+                hwAttrs.cpuFreqKHz = (int32_t)(mcuClkFreq/1000U);
+                ctrlBitmap         = OSAL_HWATTR_SET_CPU_FREQ;
+                ret = Osal_setHwAttrs(ctrlBitmap, &hwAttrs);
+            }
+        }
+        if(ret != 0)
+        {
+            status = BOARD_INIT_CLOCK_FAIL;
         }
     }
+#endif
 
     return status;
 }
index 8a413710aafba6f83e0d7dbadad9f342230a9e2e..0f73964a804faddac4157b78dbb26deeb389740a 100755 (executable)
@@ -281,9 +281,44 @@ Board_STATUS Board_moduleClockInitMcu(void)
         status = Board_moduleClockEnable(gBoardClkModuleMcuID[index]);
         if(status != BOARD_SOK)
         {
-            return BOARD_INIT_CLOCK_FAIL;
+            status = BOARD_INIT_CLOCK_FAIL;
+            break;
+        }
+    }
+
+#if defined(BUILD_MCU)
+    if(status == BOARD_SOK)
+    {
+        int32_t  ret;
+        uint64_t mcuClkFreq;
+
+        ret = Sciclient_pmGetModuleClkFreq(TISCI_DEV_MCU_R5FSS0_CORE0,
+                                           TISCI_DEV_MCU_R5FSS0_CORE0_CPU_CLK,
+                                           &mcuClkFreq,
+                                           SCICLIENT_SERVICE_WAIT_FOREVER);
+        if(ret == 0)
+        {
+            Osal_HwAttrs  hwAttrs;
+            uint32_t      ctrlBitmap;
+
+            ret = Osal_getHwAttrs(&hwAttrs);
+            if(ret == 0)
+            {
+                /*
+                 * Change the timer input clock frequency configuration
+                   based on R5 CPU clock configured
+                 */
+                hwAttrs.cpuFreqKHz = (int32_t)(mcuClkFreq/1000U);
+                ctrlBitmap         = OSAL_HWATTR_SET_CPU_FREQ;
+                ret = Osal_setHwAttrs(ctrlBitmap, &hwAttrs);
+            }
+        }
+        if(ret != 0)
+        {
+            status = BOARD_INIT_CLOCK_FAIL;
         }
     }
+#endif
 
     return status;
 }
index 25dab8e151f3a8b94a8f1719d4e0a71d632f9e4b..b5d4373cf8cf150a6ea4a40035ea3435081c785f 100755 (executable)
@@ -89,35 +89,6 @@ static Board_STATUS Board_sysInit(void)
         Sciclient_configPrmsInit(&config);
         ret = Sciclient_init(&config);
 
-#if defined(BUILD_MCU)
-        uint64_t mcuClkFreq;
-
-        if(ret == 0)
-        {
-            ret = Sciclient_pmGetModuleClkFreq(TISCI_DEV_MCU_R5FSS0_CORE0,
-                                               TISCI_DEV_MCU_R5FSS0_CORE0_CPU_CLK,
-                                               &mcuClkFreq,
-                                               SCICLIENT_SERVICE_WAIT_FOREVER);
-        }
-        if(ret == 0)
-        {
-            Osal_HwAttrs  hwAttrs;
-            uint32_t      ctrlBitmap;
-
-            ret = Osal_getHwAttrs(&hwAttrs);
-            if(ret == 0)
-            {
-                /*
-                 * Change the timer input clock frequency configuration
-                   based on R5 CPU clock configured
-                 */
-                hwAttrs.cpuFreqKHz = (int32_t)(mcuClkFreq/1000U);
-                ctrlBitmap         = OSAL_HWATTR_SET_CPU_FREQ;
-                ret = Osal_setHwAttrs(ctrlBitmap, &hwAttrs);
-            }
-        }
-#endif
-
         if(ret != 0)
         {
             status = BOARD_FAIL;
index 0ab5e1002ba95dbd6b6d002c06a01fe17d8ec301..a5fa041f8131649f83efa13863e1a3017389c59d 100755 (executable)
@@ -157,12 +157,8 @@ endif
   CG_XML_VERSION=2.61.00
 
   #Component versions for non-TDA builds
-  BIOS_VERSION=6_76_02_02
-  XDC_VERSION=3_55_02_22_core
-
-ifeq ($(BOARD),$(filter $(BOARD), $(BOARD_LIST_J7_TDA)))
   BIOS_VERSION=6_76_03_01
-endif
+  XDC_VERSION=3_55_02_22_core
 
   EDMA_VERSION=2_12_05_30E
   SECDEV_VERSION=01_06_00_05
index 19ebb140641ea80d886e6bcf0acba38c8c8ffd19..15b17e01f9f45cf197271123ad0a6b9a5332864b 100644 (file)
@@ -60,7 +60,7 @@ ifeq ($(MAKERULEDIR), )
 endif
 include $(MAKERULEDIR)/common.mk
 
-ifeq ($(SOC), $(filter $(SOC), am65xx j721e))
+ifeq ($(SOC), $(filter $(SOC), am65xx))
 ifeq ($(CORE), $(filter $(CORE), mpu1_0))
 .PHONY: dualmac_fw
 
index e40bcb6229bff98598b34abeca8be5ae9cc2f49c..be90f56c3e0b0da13487b7ef9fa8dbe405a477a4 100644 (file)
@@ -220,26 +220,19 @@ Emac_Icssg_TestApp_PATH = $(PDK_EMAC_COMP_PATH)/test/EmacLoopbackTest
 Emac_Icssg_TestApp_BOARD_DEPENDENCY = yes
 Emac_Icssg_TestApp_CORE_DEPENDENCY = no
 Emac_Icssg_TestApp_XDC_CONFIGURO = yes
-ifeq ($(SOC),$(filter $(SOC), j721e))
-Emac_Icssg_TestApp_MAKEFILE = -f j721e/icssg/makefile_dualmac
-else
 Emac_Icssg_TestApp_MAKEFILE = -f am65xx/icssg/makefile_dualmac
-endif
 export Emac_Icssg_TestApp_MAKEFILE
 export Emac_Icssg_TestApp_board_dependency
 export Emac_Icssg_TestApp_core_dependency
 export Emac_Icssg_TestApp_xdc_configuro
 Emac_Icssg_TestApp_PKG_LIST = Emac_Icssg_TestApp
 Emac_Icssg_TestApp_INCLUDE = $(Emac_Icssg_TestApp_PATH)
-Emac_Icssg_TestApp_BOARDLIST = am65xx_evm am65xx_idk j721e_sim j721e_evm
+Emac_Icssg_TestApp_BOARDLIST = am65xx_evm am65xx_idk
 export Emac_Icssg_TestApp_BOARDLIST
 Emac_Icssg_TestApp_$(SOC)_CORELIST = $(drvemac_$(SOC)_CORELIST)
 export Emac_Icssg_TestApp_$(SOC)_CORELIST
 
 Emac_Icssg_TestApp_SBL_APPIMAGEGEN = yes
-ifeq ($(SOC),$(filter $(SOC), j721e))
-Emac_Icssg_TestApp_SBL_APPIMAGEGEN = no
-endif
 export Emac_Icssg_TestApp_SBL_APPIMAGEGEN
 
 # EMAC unit test app CPSW
similarity index 53%
rename from packages/ti/drv/emac/firmware/icss_dualmac/src/psiloop.h
rename to packages/ti/drv/emac/firmware/icss_dualmac/src/hd_helper.h
index 58bc4f889adcf199393b62c863f67bc2c75cc84d..10dc555a30ec2875d101bcbff65bdc011a4bb909 100644 (file)
 ;  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
 ;  EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-;---------------------
-; File:psiloop.h
-;PSI LOOPBACK ROUTINES
-;  (diagnostics)
-; PSI LOOPBACK runs on
-; BG on PRU, but looks
-;  like a tx task
-;   (e.g. will use
-;    tx task registers)
-; if this runs, no TX Will run
-; and no RX should run since this is
-;  grabing PSI widget for its use
-;   always uses unit 0
-;---------------------
+READ_RGMII_CFG .macro rtmp, speed_flags
+       TM_DISABLE
+       lbco    &rtmp, c9, 0x4, 4
+       and     rtmp.b0, rtmp.b0, f_mask_o ; takes only speed/duplex related bits
+       and     speed_flags, speed_flags, f_mask_a ; clean old status
+       or      speed_flags, speed_flags, rtmp.b0
+       TM_ENABLE
+       .endm
 
-;'tx' init for psi loopback
-PSILOOP_TX_INIT        .macro   r_d, runit
-       flip_tx_r10_r23
-       mov     TxRegs.ds_flags, r_d.w2 ;descriptor2(flags, etc)
-       mov     GRegs.tx.b.len, r_d.w0  ;save length we are expecting to transmit
-       ldi     GRegs.tx.b.state, TX_S_LOOP
-       PSILOOP_TX_POLL runit, nd_lab?, eop_lab?
-nd_lab?:
-eop_lab?:
-       flip_tx_r10_r23
- .endm
+; most likely IPG and backoff is the same timer
+; so, we will need only one macro 
+if_ipg_not_expired     .macro then_go
+       ; TODO check IPG
+       ; if not expired jmp then_go
+       ldi32   r2, FW_CONFIG
+       lbbo    &r3, r2, TX_IPG, 4 ;
+       lbco    &r4, c11, 0x0c, 4  ; read cycle counte
+       qbgt    then_go, r4, r3    ; not expired yet
+       clr     GRegs.speed_f, GRegs.speed_f, f_wait_ipg
      .endm
 
-;poll routine for bg.  If dma present, it will process it
-PSILOOP_TX_POLL        .macro   runit, no_data_label,eop_label
-       XFR2VBUS_POLL_READ runit
-       qbbc    no_data_label, r18, 2
+; touch r2, r3, r4
+reset_cycle_cnt .macro
+       lbco    &r2, c11, 0x0, 4 ; disable cycle counter
+       clr     r2.t3
+       sbco    &r2, c11, 0x0, 4
+       zero    &r3, 4           ; reset cycle counter
+       sbco    &r3, c11, 0xc, 4
+       set     r2.t3            ; enable cycle counter
+       sbco    &r2, c11, 0x0, 4
+       .endm
 
-;have data ready
-       qbge    tx_cont1a?, GRegs.tx.b.len, 64
-;read the 64 bytes & write to PSI in 4 transactions
-       XFR2VBUS_READ64_RESULT runit
-       ldi32   r1, MD_DATA0
-       PSI_WRITE
-       LEBE2_5_swap_6_9
-       PSI_WRITE
-       LEBE2_9_swap_10_17
-       LEBE2_5_swap_6_9
-       PSI_WRITE
-       LEBE2_5_swap_6_9
-       PSI_WRITE
-       sub     GRegs.tx.b.len, GRegs.tx.b.len, 64
-       jmp     tx_done?
+IPG_10MBPS     .set 2400 ; (12 * 8 * 100) nsec / 4
+IPG_10MBPS7    .set 3800 ; ((12 + 7) * 8 * 100) nsec / 4
+IPG_10MBPS_ADJ .set 600  ; (3 * 8 * 100) / 4
+IPG_100MBPS_ADJ        .set 60   ; (3 * 8 * 10) / 4
+
+start_backoff_timer .macro num
+       reset_cycle_cnt
+       mov     r2, num
+       qbge    $3, r2, 9
+       ldi     r2, 9
+$3:    ldi     r3, 1           ; create mask
+       not     r3, r3          ;
+       lsl     r3, r3, r2      ;
+       not     r3, r3          ;
+       GET_IEP_CNT     r4      ;
+       xor     r4.w0, r4.w0, r4.w2
+       ldi32   r2, FW_CONFIG      ; read value from SEED
+       lbbo    &r5, r2, CFG_SEED, 4    ; get seed
+       xor     r4, r4, r5      ; xor time with seed 
+       and     r4, r4, r3      ; mask with backoff interval
+       qbbc    $1, GRegs.speed_f, f_100mbps
+       ; for 100 mbps multiply on 5.12 usec (r4 << 7) 
+       lsl     r3, r4, 7
+       ldi     r5, IPG_100MBPS_ADJ ;
+       qba     $2
+$1:    ; for 10 mbps multiply on 51.2 usec (r4 << 10) + (r4 << 8)
+       lsl     r3, r4, 10
+       lsl     r4, r4, 8
+       add     r3, r3, r4
+       ; for 10 MBPS we need to maintain IPG manually
+       ; so if r3 is 0 then set it to 9.6 usec
+       qbne    $2, r3, 0
+       ldi     r3, IPG_10MBPS
+       ldi     r5, IPG_10MBPS_ADJ ;
+$2:    add     r3, r3, r5
+       sbbo    &r3, r2, TX_IPG, 4 ; store it to TX_IPG
+       set     GRegs.speed_f, GRegs.speed_f, f_wait_ipg
+       .endm
+
+start_ipg_timer .macro
+       reset_cycle_cnt
+       ldi32   r2, FW_CONFIG      ;
+       ldi     r4, IPG_10MBPS7
+       sbbo    &r4, r2, TX_IPG, 4 ; store it to TX_IPG
+       set     GRegs.speed_f, GRegs.speed_f, f_wait_ipg
+       .endm
+
+
+; read 8bytes from smem offset to reg and reg+1
+; we use r0
+read_bd_from_smem .macro reg, offset
+       ldi32   r0, FW_CONFIG + offset
+       lbbo    &reg, r0, 0, 8
+       .endm
+
+write_bd_to_smem .macro reg, offset
+       ldi32   r0, FW_CONFIG + offset
+       sbbo    &reg, r0, 0, 8
+       .endm
+
+update_col_status .macro
+ .if $defined("SLICE0")
+       lbco    &r2, c27, 0x38, 4
+ .else
+       lbco    &r2, c27, 0x3c, 4
+ .endif
+       qbbc    $1, r2, 1
+       set     GRegs.speed_f, GRegs.speed_f, f_col_detected
+$1:
+       .endm
+
+read_col_status .macro reg
+ .if $defined("SLICE0")
+       lbco    &reg, c27, 0x38, 4
+ .else
+       lbco    &reg, c27, 0x3c, 4
+ .endif
+       .endm
 
-tx_cont1a?:   ;eop, (again always using unit a)
-       XFR2VBUS_CANCEL_READ_AUTO_64_CMD (runit)
-       XFR2VBUS_READ64_RESULT (runit)
-       qble    mt16?, GRegs.tx.b.len, 16
-;just have 16bytes or less
-       ldi32   r1, MD_DATA1
-       add     r0.b0, GRegs.tx.b.len, 4
-       PSI_WRITE_N
-       jmp     tx_done2?
-mt16?:
-       qble    mt32?, GRegs.tx.b.len, 32
-;just have 32bytes or less
-       ldi32   r0, MD_DATA0
-       PSI_WRITE
-       LEBE2_5_swap_6_9
-       ldi32   r1, MD_DATA1
-       sub     GRegs.tx.b.len, GRegs.tx.b.len,16
-       add     r0.b0, GRegs.tx.b.len, 4
-       PSI_WRITE_N
-       jmp     tx_done2?
-mt32?:
-       qble    mt48?, GRegs.tx.b.len, 48
-;just have 48bytes or less
-       ldi32   r0, MD_DATA0
-       PSI_WRITE
-       LEBE2_5_swap_6_9
-       PSI_WRITE
-       LEBE2_9_swap_10_17
-       LEBE2_5_swap_6_9
-       ldi32   r1, MD_DATA1
-       sub     GRegs.tx.b.len, GRegs.tx.b.len,32
-       add     r0.b0, GRegs.tx.b.len, 4
-       PSI_WRITE_N
-       jmp     tx_done2?
-mt48?:
-;have more than 48
-       ldi32   r0, MD_DATA0
-       PSI_WRITE
-       LEBE2_5_swap_6_9
-       PSI_WRITE
-       LEBE2_9_swap_10_17
-       LEBE2_5_swap_6_9
-       PSI_WRITE
-       LEBE2_5_swap_6_9
-       ldi32   r1, MD_DATA1
-       sub     GRegs.tx.b.len, GRegs.tx.b.len,48
-       add     r0.b0, GRegs.tx.b.len, 4
-       PSI_WRITE_N
-tx_done2?:
-;say we are done
-       SPIN_SET_LOCK_LOC PRU_RTU_EOD_P_FLAG
-       SPIN_CLR_LOCK_LOC PRU_RTU_EOD_P_FLAG
-;set tx state
-       ldi     GRegs.tx.b.state, TX_S_IDLE
-       jmp eop_label
-tx_done?:
- .endm
index 6582a3db2f12aa3d2837470379fc3597c5991eaf..843d7dbbab8703a57afe022823ebb0a7ea001875 100644 (file)
@@ -72,8 +72,8 @@ IEP_BASE1     .set    0x2f000
 IEP_CFG1_BASEx .set     (0x26000+0x30)
 
 IEP_GCFG       .set    0x00
-IEP_C64_HI     .set    0x10
-IEP_C64_LO     .set    0x14
+IEP_C64_HI     .set    0x14
+IEP_C64_LO     .set    0x10
 IEP_CAP_RX_S0  .set    0x20
 IEP_CAP_RX_S1  .set    0x30
 IEP_CAP_TX_S0  .set    0x40
@@ -173,3 +173,12 @@ GET_PKT_TX_TS      .macro   r_ts_h
        lbbo    &r_ts_h, r0, 0, 8
  .endm
 
+GET_IEP_CNT    .macro reg
+ .if $isdefed("SLICE0")
+       ldi32   r0, (IEP_BASE0+IEP_C64_LO)
+ .else ; slice1
+       ldi32   r0, (IEP_BASE1+IEP_C64_LO)
+ .endif
+       lbbo    &reg, r0, 0, 4
+ .endm
+
index ea787984d1ad4143152b87e5af6248bbef71c940..9c179c90fe2a95c6a2048490999e32971848be2b 100644 (file)
@@ -91,17 +91,17 @@ CL_FLAGS = --endian=little \
           --diag_wrap=off \
           --diag_warning=225 \
           --display_error_number \
+          --hardware_mac=on \
            --code_address_listing_unit=word \
-          --hardware_mac=on
 
 FLAGS = -al \
        --preproc_with_compile \
        -eo.opru \
 
-EF_PRU0 = -DMAC  -DSLICE0 
-EF_PRU1 = -DMAC  -DSLICE1
-EF_RTU0 = -DMAC  -DSLICE0 -DDO_PSI_ABORT
-EF_RTU1 = -DMAC  -DSLICE1 -DDO_PSI_ABORT
+EF_PRU0 = -DMAC  -DSLICE0 -DPRU0
+EF_PRU1 = -DMAC  -DSLICE1 -DPRU1
+EF_RTU0 = -DMAC  -DSLICE0 -DRTU0 -DDO_PSI_ABORT
+EF_RTU1 = -DMAC  -DSLICE1 -DRTU1 -DDO_PSI_ABORT
 
 APP_DEFS = --define=RGMII \
           -z \
similarity index 66%
rename from packages/ti/drv/emac/firmware/icss_dualmac/src/rtu_psi_loopback.h
rename to packages/ti/drv/emac/firmware/icss_dualmac/src/pa_stat.h
index 58c61e019673f615d406fc47b281c53b858db098..3a2acc8a416a722c195b8e647ae8e7e1d2306c52 100644 (file)
@@ -1,7 +1,7 @@
 ;
 ;  TEXAS INSTRUMENTS TEXT FILE LICENSE
 ;
-;   Copyright (c) 2018-2019 Texas Instruments Incorporated
+;   Copyright (c) 2019 Texas Instruments Incorporated
 ;
 ;  All rights reserved not granted herein.
 ;
 ;  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
 ;  EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-;-------------------------------------------------
-;---file: rtu_psi_loopback.h
-;---purpose:  loopback macros for rtu_psi 
-;---------------------------------------------------
+TX_COL_RETRIES .set    80
+TX_COL_DROPPED .set    81
 
-;#define LOOPBACK_TEST  ;direct attach between pru/rtu loopback
-;LOOPBACK_TEST2        .set    1 ;direct attach to host loopback
-
-;if loopback, define one of these 4
-SL_P0  .set    1 ;this port
-;#define SL_P1   ;other port
-;#define SL_P01  ;both
-;#define SL_DROP ;no port
-
-loopback_test_forward .macro
- .if $isdefed("LOOPBACK_TEST")
-
-;force drop
- .if $isdefed("SL_DROP")
-       clr     r_pix0.b1.t1 ;f_port0
-       clr     r_pix0.b1.t2 ;f_port1
- .endif
-
-;force it to stay local
- .if $isdefed("SL_P0")
- .if $isdefed("SLICE0")
-       clr     r_pix0.b1.t1 ;f_port0
- .else
-       clr     r_pix0.b1.t2 ;f_port1
- .endif
-
- .endif
-
-;force it to other slice
- .if $isdefed("SL_P1")
- .if $isdefed("SLICE0")
-       clr     r_pix0.b1.t2 ;f_port1
- .else
-       clr     r_pix0.b1.t1 ;f_port0
+; index is just a number but not an offset.
+m_inc_stat .macro reg, index
+ .if $defined("PRU0")
+       ldi     reg, index
+       sbco    &reg, c9, 0x40, 1
  .endif
+ .if $defined("PRU1")
+       ldi     reg, (index + 128)
+       sbco    &reg, c9, 0x44, 1
  .endif
-
-;leave it set for both
- .if $isdefed("SL_P01")
+ .if $defined("RTU0")
+       ldi     reg, index
+       sbco    &reg, c9, 0x48, 1
  .endif
+ .if $defined("RTU1")
+       ldi     reg, (index + 128)
+       sbco    &reg, c9, 0x4c, 1
  .endif
- .endm
-
-loopback_test2_forward .macro
- .if $isdefed("LOOPBACK_TEST2")
-
-;force drop
- .if $isdefed("SL_DROP")
-       clr     r_pix0.b1.t1 ;f_port0
-       clr     r_pix0.b1.t2 ;f_port1
- .endif
-
-;force it to stay local
- .if $isdefed("SL_P0")
- .if $isdefed("SLICE0")
-       clr     r_pix0.b1.t1 ;f_port0
- .else
-       clr     r_pix0.b1.t2 ;f_port1
- .endif
- .endif
-
-;force it to other slice
- .if $isdefed("SL_P1")
- .if $isdefed("SLICE0")
-       clr     r_pix0.b1.t2 ;f_port1
- .else
-       clr     r_pix0.b1.t1 ;f_port0
- .endif
- .endif
-
-;leave it set for both
- .if $isdefed("SL_P01")
- .endif
- .endif
- .endm
-
+       .endm
index e8acb266361cc48ff780f2d1c227ea7cf0ab73de..e4e4da568f1d77e35e135a9a58b79d528f29495c 100644 (file)
@@ -98,16 +98,10 @@ res         .ushort
 ds_flags       .ushort ;descriptor info
 stash_ds_flags .ushort
 stash_tx_len   .ushort
-pp_afs_tx      .ubyte  ;cnt of bytes sent so far
-pp_afs_rem     .ubyte  ;addFragSz of remote  (64-256)
-pp_ppok                .ubyte  ;flags
-pp_count       .ubyte  ;[256] counter of preemptions
+;
+res2           .uint
        .endstruct ;Struct_TXTASK
 
-f_pp_active    .set    0  ;preemption featue active  on this port
-f_pp_enufsent  .set    1  ;enough bytes sent
-f_pp_enufleft  .set    2  ;enough bytes remain
-PPOK           .set    0x7
 
 TxRegs .sassign r21, Struct_TXTASK
 
@@ -123,7 +117,7 @@ bg_cnt              .uint   ; BG loop counter
 psi2h_active   .ubyte  ; 1 - active, 0 - idle
 res9           .ubyte  ;
 len2host       .ushort ;
-borg_limit     .ushort ;
+res10          .ushort ;
 len_orig       .ushort ;
        .endstruct ;Struct_BGTASK
 
@@ -144,7 +138,10 @@ pkt_len                    .ushort
                .endstruct
        .endunion ;rx
 
-scratch        .uint
+speed_f        .ubyte          ; speed/duplex flags
+ret_cnt        .ubyte          ; retransmission counter
+tx_blk .ubyte          ; tx 64 byte blocks counter
+res    .ubyte          ; 
 
 tx     .union
 x              .uint
@@ -186,6 +183,32 @@ res                        .ubyte
 
 GRegs  .sassign r24, Struct_GLOBAL
 
+; 100/10Mbps/half duplex port flags. That is mirror of the correcponding bits
+; of the ICSSG_RGMII_CFG register
+ .if $isdefed("SLICE0")
+f_100mbps      .set    1
+f_1gbps                .set    2
+f_half_d       .set    3
+f_mask_o       .set    0xe
+f_mask_a       .set    0xf1
+
+f_col_detected .set    4
+f_stopped_due_col .set 5
+f_wait_ipg     .set    6
+
+
+ .else
+f_100mbps      .set    5
+f_1gbps                .set    6
+f_half_d       .set    7
+f_mask_o       .set    0xe0
+f_mask_a       .set    0x1f
+
+f_col_detected .set    0
+f_stopped_due_col .set 1
+f_wait_ipg     .set    2
+ .endif
+
 ;RX flags
 f_tohost       .set 0
 f_rx_sof       .set 7
@@ -306,7 +329,9 @@ other_port  .set    1
 Struct_RTU_GLOBAL .struct
 ;-1-
 ret_addr       .ushort
-res1           .ushort
+res            .ubyte
+speed_f                .ubyte
+
 ;-2-
 StallMask      .ubyte
 ActThrdNum     .ubyte
index cc3c8230d4d4e10bbbf4b502001fede47f1bf9d5..f48b0d343aa53507b944da4acd4323029d450cf3 100644 (file)
@@ -58,7 +58,6 @@
 ;---------------------------------------------------
 
 ;----------------------DEFINES------------------------
- .include "rtu_psi_loopback.h"
 
 ;global PSI state
        .asg    b0, ssmask  ; mask of threads that are stalled.
@@ -180,24 +179,10 @@ $7:       qbbc    $1, r2, 23       ; r2.t23
        set     Ctx.ippc_flags, Ctx.ippc_flags, f_crcinpkt
 
 $1:
- .if $isdefed("LOOPBACK_TEST")
-       set     Ctx.ippc_flags, Ctx.ippc_flags, f_crcinpkt
- .endif
- .if $isdefed("LOOPBACK_TEST2")
-       clr     Ctx.ippc_flags, Ctx.ippc_flags, f_crcinpkt ;crc not in pkt
- .endif
-
        set     Ctx.ippc_forward, Ctx.ippc_forward, our_port ;to keep it local
        ;//set portq
        and     Ctx.ippc_res, r4.b3, 0x07  ;ippc_res set to dst tag hi 
        mov     Ctx.ippc_totlen, r3.w0 ;check rate
- .if $isdefed("PSILOOP")
-       add     Ctx.ippc_totlen, Ctx.ippc_totlen, 4   ;add 'crc' bytes
- .endif
- .if $isdefed("LOOPBACK_TEST")
-       mov     Ctx.ippc_totlen, 512  ;hard code because it will be 0xffff
- .endif
-
  .if $isdefed("TX_RATE_LIMITER")
        mov     r3, GRrtu.ActThrdNum
        qbbc    $6, Ctx.he_flags, r3
@@ -409,9 +394,6 @@ DO_WRITE64  .macro  unit, len
 DO_EOP .macro  stall_exit
 ;build common parts of descriptor
        mov     r8.w0, Ctx.ippc_curlen        ;len
- .if $isdefed("PSILOOP")
-       add r8.w0, r8.w0, 4  ;include 'dummy' crc
- .endif
        ldi     r8.b2, FROM_US_V
        qbbs    no_crc?, Ctx.ippc_flags, f_crcinpkt
        set     r8.t16 ;force tx to get hw to do crc
index 2ced3430bdf6fde35cbc7e1cb50b0c69d9d437f9..8ad95931f7758b87cf22ea7ddf2b527bce0222a5 100644 (file)
@@ -75,6 +75,7 @@ RX_RAW        .set    1
  .include "portq.h"
  .include "lebe.h"
  .include "bpool.h"
+ .include "hd_helper.h"
  .include "scheduler.h"
  .include "ipc.h"
  .include "filter.h"
@@ -82,7 +83,6 @@ RX_RAW        .set    1
  .include "txrate.h"
  .include "rtu_psi.h"
  .include "iep.h"
- .include "psiloop.h"
 
 loop_here .macro
 here?: jmp     here?
@@ -270,6 +270,7 @@ $3: qbbc    no_psi, r1, 3
 
 no_psi: jmp psi_idle2
 psi_idle3:
+       READ_RGMII_CFG  r1, GRrtu.speed_f
        CALL_SUB        sstate_00, psi_idle
        jmp     psi_idle
 
index 463d7521ce78046853ea410ce5f2e0ba365f92dd..11bb90c5e2a6e41a7bd5ce80b97c8d16b61b507a 100644 (file)
@@ -62,7 +62,6 @@
 ; SLICE0 or SLICE1 must be defined  (but not both)
 ; WAIT_FOR_DEBUGGER:  wait for debugger to attach
 ; VLAN_ENABLED
-; PSILOOP
 DATA_ONLY      .set    1 ;control path moved to RTU
 
 ; sanity check ;{{{1
@@ -89,9 +88,10 @@ DATA_ONLY    .set    1 ;control path moved to RTU
  .include "filter.h"
  .include "lebe.h"
  .include "ipc.h"
- .include "psiloop.h"
  .include "iep.h"
  .include "psisandf.h"
+ .include "hd_helper.h"
+ .include "pa_stat.h"
 
 loop_here      .macro
 here?: jmp     here?
@@ -203,6 +203,29 @@ $1:        qbeq    $1, r11, 0
  .endif
  .endm
 
+; we need to read DMA back only if there is ongoing transfer
+; assume when we read DMA status it shouldn't be 0,
+; otherwise let's think it is already stopped  
+flush_dma .macro unit
+       XFR2VBUS_CANCEL_READ_AUTO_64_CMD unit
+       nop
+$1:    xin     unit, &r18, 4
+       qbeq    $2, r18.w0, 0
+       qbne    $1, r18.w0, 0x5
+       XFR2VBUS_READ64_RESULT unit
+$2:
+       .endm
+
+stop_tx_due_colission .macro
+       qbbc    $1, GRegs.tx.b.flags, f_next_dma
+       flush_dma       XFR2VBUS_XID_READ0
+       qba     $2 ;
+$1:    flush_dma       XFR2VBUS_XID_READ1
+$2:    set     r31, r31, 29            ;tx.eof
+       set     GRegs.speed_f, GRegs.speed_f, f_stopped_due_col
+       ldi     GRegs.tx.b.state, TX_S_W_EOF
+       .endm
+
 ; Code starts {{{1
  .retain     ; Required forbuilding    .out with assembly file
  .retainrefs ; Required forbuilding    .out with assembly file
@@ -211,6 +234,10 @@ $1:        qbeq    $1, r11, 0
 
 Start:
        TM_DISABLE
+       ldi32   r0, 0x80000000  ;TODO: driver has to enable PA_STAT
+       ldi32   r1, 0x3c000
+       sbbo    &r0, r1, 8, 4
+
        zero    &r0, 124
        P2P_IPC_ZAP     ;zap IPC area
        xout    XFR2VBUS_XID_READ0, &r18, 4 ;disable xfr2vbus autoread mode
@@ -262,7 +289,6 @@ RX:
        ldi     GRegs.snf.b.rd_cur, MINPS
        ldi     r30, 1522  ;todo - make a parameter
        ldi32   r10, FW_CONFIG
-       lbbo    &r2, r10, CFG_N_BURST, 4
 
 ; set pru ready status
        ldi32   r0, PRU_READY
@@ -278,19 +304,13 @@ wait_rtu_ready:
 ;BG TASK:     r24-r29  are global ;{{{1
 ;-------------------------------------------------------------------------
        zero    &r18, 24
-       mov     BgRegs.borg_limit, r2 ; GS_NBURST ;
 
+       ldi     GRegs.ret_cnt, 0
+;================================
+; BG LOOP:  until cmd cancel seen
 ;================================
-; BG LOOP:  stay here until we see
-;            GRegs.pkt_cnt.w.tx == BgRegs.borg_limit if in borg mode
-;            until cmd cancel seen
-;=================================
 bg_loop:
        add     BgRegs.bg_cnt, BgRegs.bg_cnt, 1 ;loop count
-;can we exit?
-       qbeq    skip_chk, BgRegs.borg_limit, 0
-       qbeq    bg_done, GRegs.pkt_cnt.w.tx, BgRegs.borg_limit ; done
-skip_chk:
 ; if RTU started shutdown process - disable TM and loop forever
        ldi32   r0, FW_CONFIG
        ldi32   r1, RTU_STARTED_SHUTDOWN
@@ -335,58 +355,85 @@ th_schedule0:
 ;schedule TX2WIRE ?
 ;----------------------
 scheduler:
+       READ_RGMII_CFG  r2, GRegs.speed_f               ; update speed/duplex fields
+       sbco    &r25, c28, 0x20, 4
+       qbbs    sch_10, GRegs.speed_f, f_half_d ; don't check col if full duplex
+; if TX is idle and colission is set, probably it is from the
+; previouse packet. Just wait
+       read_col_status r2
+       qbne    sch_05, GRegs.tx.b.state, TX_S_IDLE ; TODO: check error case
+       qbbs    bg_loop, r2, 1  ; still active
+sch_05: qbbc   sch_10,  r2, 1  ;
+; we came here if TX is active and collission is detected
+; we need to cancel the current TX and schedule retransmission
+       qbbs    sch_10, GRegs.speed_f, f_stopped_due_col ; don't stop twice
        TM_DISABLE
-       qbeq    bg_schedule0, GRegs.tx.b.state, TX_S_IDLE ;if tx state is idle, check IPC for new descriptor
-       qbeq    bg_schedule1, GRegs.tx.b.state, TX_S_ERR ;if tx state is idle, check IPC for new descriptor
- .if $isdefed("PSILOOP")
-       qbeq    bg_schedulePL, GRegs.tx.b.state, TX_S_LOOP ;if psi loopback
- .endif
-
-;TX ACTIVE.
+       set     GRegs.speed_f, GRegs.speed_f, f_col_detected
+       flip_tx_r0_r23
+       stop_tx_due_colission
+       flip_tx_r0_r23
+       TM_ENABLE
+sch_10:
+       TM_DISABLE
+       ;if tx state is idle, check IPC for new descriptor
+       qbeq    bg_schedule0, GRegs.tx.b.state, TX_S_IDLE
+       qbne    sched_done, GRegs.tx.b.state, TX_S_ERR
+;error case (underflow)
+;todo
+       ldi     GRegs.tx.b.state, TX_S_IDLE
 sched_done:
        TM_ENABLE
        jmp     bg_loop
 
 bg_schedule0:
-;non PSA case only check expected next dma
+       ldi     GRegs.tx_blk, 0
+       clr     GRegs.speed_f, GRegs.speed_f, f_col_detected
+       clr     GRegs.speed_f, GRegs.speed_f, f_stopped_due_col
+       qbbs    bg_new_pkt, GRegs.speed_f, f_1gbps      ; process as usual
+       qbbc    bg_half_duplex, GRegs.speed_f, f_half_d ;
+bg_schedule1:
+       qbbs    bg_new_pkt, GRegs.speed_f, f_100mbps    ;
+       if_ipg_not_expired      sched_done
+       qba     bg_new_pkt
+
+bg_half_duplex:
+       qbne    sched_done, GRegs.rx.b.state, RX_STATE_IDLE ; we have active RX,don't start TX
+       qbeq    bg_schedule1, GRegs.ret_cnt, 0  ; just new packet
+       if_ipg_not_expired sched_done
+; OK we need to restart transmition of the same packet
+; use the same dma, which was used for the packet
+       qbbc    retr_1, GRegs.tx.b.flags, f_next_dma
+       read_bd_from_smem  r2, BD_OFS_0
+       XFR2VBUS_ISSUE_READ_AUTO_64_CMD XFR2VBUS_XID_READ0, r2, ADDR_HI
+       TM_ENABLE
+       XFR2VBUS_WAIT4READY     XFR2VBUS_XID_READ0
+       qba     retr_2
+retr_1:
+       read_bd_from_smem  r2, BD_OFS_1
+       XFR2VBUS_ISSUE_READ_AUTO_64_CMD XFR2VBUS_XID_READ1, r2, ADDR_HI
+       TM_ENABLE
+       XFR2VBUS_WAIT4READY     XFR2VBUS_XID_READ1
+
+retr_2:        TM_DISABLE
+       TX_TASK_INIT2_shell     r3
+       TM_ENABLE
+       jmp     bg_loop
+
+bg_new_pkt:
+       ldi     GRegs.ret_cnt, 0
        qbbs    bg_chk1, GRegs.tx.b.flags, f_next_dma
-;check dma0
        PRU_IPC_RX_CH0Q sched_done, r2, XFR2VBUS_XID_READ0
-; have new packet in r2= len-flags
- .if $isdefed("PSILOOP")
-       PSILOOP_TX_INIT r2, XFR2VBUS_XID_READ0
-;don't pingpong with PSILOOP!
- .else
        TX_TASK_INIT2_shell     r2
        set     GRegs.tx.b.flags, GRegs.tx.b.flags, f_next_dma
- .endif
        TM_ENABLE
        jmp     bg_loop
 bg_chk1:
-;check 2nd dma
        PRU_IPC_RX_CH0Q sched_done, r3, XFR2VBUS_XID_READ1
        TX_TASK_INIT2_shell     r3
        clr     GRegs.tx.b.flags, GRegs.tx.b.flags, f_next_dma
        TM_ENABLE
        jmp     bg_loop
 
-bg_schedule1:
-;error case (underflow)
-;todo
-       ldi     GRegs.tx.b.state, TX_S_IDLE
-       TM_ENABLE
-       jmp     bg_loop
- .if $isdefed("PSILOOP")
-bg_schedulePL:
-;psi loopback
-       flip_tx_r10_r23
-       PSILOOP_TX_POLL XFR2VBUS_XID_READ0, psi_poll_done, psi_poll_done
-psi_poll_done:
-       flip_tx_r10_r23
-       TM_ENABLE
-       jmp     bg_loop
- .endif
-
 ;-------------------------------------
 ; done with packets.
 ;-------------------------------------
@@ -413,57 +460,87 @@ bg_done:
 
 ;---------------------------------------------------------------------
 ; TX_EOF  EvENT {{{1
-;----------------------------------------------------------------------
+;---------------------------------------------------------------------
 TX_EOF:
        qbne    tx_underflow, GRegs.tx.b.state, TX_S_W_EOF
-; TX TS processing
        flip_tx_r0_r23
+       m_inc_stat      r0.b0, 82
+       qbbs    tx_proc_col, GRegs.speed_f, f_stopped_due_col
+; TX TS processing
        qbbc    no_tx_ts, TxRegs.ds_flags, 5 ; we don't need tx_ts
        GET_PKT_TX_TS   r2
        ldi32   r10, FW_CONFIG + TX_TS_BASE
        sbbo    &r2, r10, 0, 8
        SPIN_TOG_LOCK_LOC       PRU_RTU_TX_TS_READY
 no_tx_ts:
-       flip_tx_r0_r23
+;      if half duplex IPC to RTU
+       qbbs    tx_eof_0, GRegs.speed_f, f_half_d
+       qbbs    tx_eof_ipc1, GRegs.tx.b.flags, f_next_dma       
+       SPIN_TOG_LOCK_LOC PRU_RTU_EOD_P_FLAG
+       qba     tx_eof_0
+tx_eof_ipc1:
+       SPIN_TOG_LOCK_LOC PRU_RTU_EOD_E_FLAG
+; we don't check if the next packet scheduled for 10Mbps 
+tx_eof_0:
+       qbbs    tx_eof_1, GRegs.speed_f, f_1gbps
+       qbbc    no_new_tx_10mbps, GRegs.speed_f, f_100mbps
+tx_eof_1:      
+       ldi     GRegs.tx_blk, 0
+       clr     GRegs.speed_f, GRegs.speed_f, f_col_detected
+       clr     GRegs.speed_f, GRegs.speed_f, f_stopped_due_col
+       ldi     GRegs.ret_cnt, 0
 
-;-----------------------------
-;Legit EOF. Restore registers
-;-----------------------------
-legit_tx_eof:
-       flip_tx_r0_r23
        qbbs    teof_chk1, GRegs.tx.b.flags, f_next_dma
-;check dma0
        PRU_IPC_RX_CH0Q no_new_tx, r2, XFR2VBUS_XID_READ0
-; have new packet in r2= len-flags
        TX_TASK_INIT2   r2
        set     GRegs.tx.b.flags, GRegs.tx.b.flags, f_next_dma 
        jmp     tx_eof_on_deck_done
 teof_chk1:
-;check 2nd dma
        PRU_IPC_RX_CH0Q no_new_tx, r3, XFR2VBUS_XID_READ1
        TX_TASK_INIT2   r3
        clr     GRegs.tx.b.flags, GRegs.tx.b.flags, f_next_dma
 
-;started next pkt, terminate task
 tx_eof_on_deck_done:
        TM_YIELD
-;these next 2 instructions are done in delayed branch fashion
        flip_tx_r0_r23
        add     GRegs.pkt_cnt.w.tx, GRegs.pkt_cnt.w.tx, 1
        loop_here
 
-;---------------------------------------------
-;eof w/ no new packet to TX
-;---------------------------------------------
+no_new_tx_10mbps:
+       ldi     GRegs.tx_blk, 0
+       clr     GRegs.speed_f, GRegs.speed_f, f_col_detected
+       clr     GRegs.speed_f, GRegs.speed_f, f_stopped_due_col
+       ldi     GRegs.ret_cnt, 0
+       start_ipg_timer 
+
 no_new_tx:
        ldi     GRegs.tx.b.state, TX_S_IDLE
-       TM_YIELD
-       add     GRegs.pkt_cnt.w.tx, GRegs.pkt_cnt.w.tx, 1
-       flip_tx_r0_r23
-       loop_here
-
+       qba     tx_eof_on_deck_done
+;
+; we came here due to collision, so we are in half duplex mode.
+; We either retranssmit or drop the packet
+;  
+tx_proc_col:
+       m_inc_stat      r1.b0, TX_COL_RETRIES
+       qble    txp_max_retry, GRegs.ret_cnt, 16 ; todo: define
+       qblt    txp_max_retry, GRegs.tx_blk, 2   ; TODO: update for late col
+       start_backoff_timer GRegs.ret_cnt
+       add     GRegs.ret_cnt, GRegs.ret_cnt, 1
+       qba     no_new_tx 
+txp_max_retry:
+       m_inc_stat      r1.b0, TX_COL_DROPPED
+       qbbs    txp_max_01, GRegs.tx.b.flags, f_next_dma        
+       SPIN_TOG_LOCK_LOC PRU_RTU_EOD_P_FLAG
+       qba     txp_max_02
+txp_max_01:
+       SPIN_TOG_LOCK_LOC PRU_RTU_EOD_E_FLAG
+txp_max_02:
+       start_ipg_timer
+       ldi     GRegs.ret_cnt, 0
+       qbbc    no_new_tx_10mbps, GRegs.speed_f, f_100mbps
+       qba     no_new_tx
+       
 ;------exception cases------
-;underflow case:
 tx_underflow:
        ldi     GRegs.tx.b.state, TX_S_ERR
        TM_YIELD
@@ -479,49 +556,27 @@ tx_underflow:
 ;----------------------------------------------------------------------
 TX_FIFO:
        qbeq    handle_portq, GRegs.tx.b.state, TX_S_ACTIVE
-;ignore rest
        TM_YIELD
        loop_here
 
-;----------------------
-; FROM PORTQ CASE
-;----------------------
 handle_portq:
        flip_tx_r0_r23
-;
-;check to see if need to preempt!
-; conditions:  preempt enabled on port and pkt is preemptible
-;              and enuf bytes sent and  enuf bytes left and
-;              (hold set or Express Frame waiting )
-;if not preemptible pkt skip all
-       qbbs    skip_preempt, TxRegs.ds_flags, 4 ; R_TX_D1.f_desc_express
-       qbne    skip_preempt, TxRegs.pp_ppok, PPOK
-       qbbs    do_preempt, GRegs.tx.b.flags, f_tx_hold
-       qbbs    do_preempt, GRegs.tx.b.flags, f_tx_efq
-       qbbc    skip_preempt, GRegs.tx.b.flags, f_tx_efqd
-do_preempt:
-       END_TX_MCRC     ;send MCRC
-       mov     TxRegs.stash_ds_flags, TxRegs.ds_flags
-       mov     TxRegs.stash_tx_len, GRegs.tx.b.len
-
-       set     GRegs.tx.b.flags, GRegs.tx.b.flags, f_tx_stash ;so we know
-       ldi     GRegs.tx.b.state, TX_S_W_PEOF
-       TM_YIELD
-       flip_tx_r0_r23
-       add     TxRegs.pp_count, TxRegs.pp_count, 1
-       loop_here
-
-skip_preempt:
-;assume data is here
+       add     GRegs.tx_blk, GRegs.tx_blk, 1
+       qbbs    tx_fifo1, GRegs.speed_f, f_half_d
+       qbbs    txf_90, GRegs.speed_f, f_stopped_due_col ; don't stop twice
+       
+       update_col_status
+       qbbc    tx_fifo1, GRegs.speed_f, f_col_detected
+       ; collision was detected, we need to stop pushing to TXL2
+       stop_tx_due_colission
+       qba     txf_90
+
+tx_fifo1:
        TX_FILL_FIFO    XFR2VBUS_XID_READ0
-       TM_YIELD
+txf_90:        TM_YIELD
        flip_tx_r0_r23
        loop_here
 
-;-------------------------------------------------------------------------
-; End TX_FIFO  EVENT
-;-------------------------------------------------------------------------
-
 ;-------------------------------------------------------------------------
 ;RXTX_ERR EVENT  ; {{{1
 ; assume rx issue.
index 0077fad07204867f3e8fb4c8c7a1cc550e96efcf..38b24917645b6f1108d4761dfa6a1eeb0670a242 100644 (file)
@@ -119,21 +119,10 @@ $3:       ; non_empty00
        clr     r8.t20
        mov     r20, r0
        mov     r2, r8
-       RTU_IPC_TX_CH0_PPKT
-
-;PSILOOPBACK ..
- .if $isdefed("PSILOOP")
-;read iep for 'rx timestamp' (raw iep counter)
-       GET_FW_TS r2
-       clr     GRrtu.flags, GRrtu.flags, f_dmau  ;!! in PSI loopback we use just 1 dma !!
- .endif
+       qbbs    $5, GRrtu.speed_f, f_half_d
+       write_bd_to_smem  r7, BD_OFS_0
+$5:    RTU_IPC_TX_CH0_PPKT
        PAGE_SAVE2 SCHED_MAIN
- .if $isdefed("PSILOOP")
-       PAGE_RESTORE2_REG RTU_GSTATE, 32
-       mov r11.w0, GS_DEF_FLOW
-       PSI_GET_INFO2 PSI_INFO_SLOT, r11.w0
-       PSI_WRITEG
- .endif
        jmp     done?
 
 use_dma1?:
@@ -144,7 +133,9 @@ use_dma1?:
        set     GRrtu.flags, GRrtu.flags, f_dma1
        mov     r20, r0
        mov     r3, r8
-       RTU_IPC_TX_CH0_EPKT
+       qbbs    $6, GRrtu.speed_f, f_half_d
+       write_bd_to_smem  r7, BD_OFS_1
+$6:    RTU_IPC_TX_CH0_EPKT
        PAGE_SAVE2 SCHED_MAIN2
        jmp     done?
 
index 6f63a69df5d32666f0e37107595220adedeea858..0afdd5d7d52e230e8610d1577fd90b9d43a03572 100644 (file)
@@ -89,6 +89,14 @@ CFG_FLAGS    .set CFG_MGR_FLOW + 4
 CFG_N_BURST    .set CFG_FLAGS + 4 ;just for debug
 CFG_RTU_STATUS .set CFG_N_BURST + 4 ; only RTU can write here
 CFG_OUT                .set CFG_RTU_STATUS + 4
+CFG_RES                .set CFG_OUT + 4
+
+CFG_SEED       .set CFG_RES + 4 ; seed to calculate random value
+BD_OFS_0       .set CFG_SEED + 4;
+BD_OFS_1       .set BD_OFS_0 + 8
+TX_IPG         .set BD_OFS_1 + 8
+BD_FREE                .set TX_IPG + 4
+
 
 TX_TS_BASE     .set 0x300
 
index 078272e1b71df51ca07124d63d3662174cf37fc7..6af0291b66d96ac1ea38fb845f35e3f6235f69eb 100644 (file)
@@ -60,9 +60,6 @@
 ;for TX_Q
 ; see bsram_pru.h for slot/size
 
-;need_to_preempt
-;(f_tx_hold || f_tx_efq ) && f_pp_active && TX_S_ACTIVE && f_frame_preemptible && (PP_afs_tx> PP_afs_rem) &&(tx_len>64)
-
 ;macros to end tx
 
 ;end w/ CRC
@@ -152,7 +149,6 @@ TX_TASK_INIT2_shell .macro  r_d
 ;main macro to initialize TX from s&f IPC 'queue'
 ; r_d  holds descriptor
 TX_TASK_INIT2  .macro  r_d
-
 ;temporary
        mov     TxRegs.ds_flags, r_d.w2 ;descriptor2(flags, etc)
        mov     GRegs.tx.b.len, r_d.w0  ;save length we are expecting to transmit
@@ -160,30 +156,29 @@ TX_TASK_INIT2     .macro  r_d
 ;start things off
 ;set TX fifo mode according to TX_D1 flags..  todo
  .if $isdefed("VLAN_ENABLED")
-       qbbc no_pa0?, TxRegs.pp_ppok, f_pp_active
-       qbbs no_pa0?, TxRegs.ds_flags, 4;f_desc_express
-       ldi     TxRegs.pp_afs_tx, 0  ;clear bytes sent so far
-       set     TxRegs.pp_ppok, TxRegs.pp_ppok, f_pp_enufleft  ;enuf bytes left to preempt
-       clr     TxRegs.pp_ppok, TxRegs.pp_ppok, f_pp_enufsent  ;NOT enuf bytes sent to preempt yet
-       SOP_TAG_STUFF_PP load_fifo?
-       jmp load_fifo?
-no_pa0?:
        SOP_TAG_STUFF load_fifo?
- .else
-;P-pkt
-       qbbc    no_pa?, TxRegs.pp_ppok, f_pp_active
-       qbbs    no_pa?, TxRegs.ds_flags, 4 ;f_desc_express
-       ldi     TxRegs.pp_afs_tx, 0;clear bytes sent so far
-       set     TxRegs.pp_ppok, TxRegs.pp_ppok, f_pp_enufleft ;enuf bytes left to preempt
-       clr     TxRegs.pp_ppok, TxRegs.pp_ppok, f_pp_enufsent ;NOT enuf bytes sent to preempt yet
-       TX_START_PRE
-no_pa?:
  .endif
 load_fifo?:
        ldi     GRegs.tx.b.state, TX_S_ACTIVE
        TX_FILL_FIFO XFR2VBUS_XID_READ0
  .endm
 
+
+FROM_DMA_TO_TXL2 .macro runit
+       XFR2VBUS_WAIT4READY runit
+       XFR2VBUS_READ64_RESULT runit
+$1:    xin     TXL2, &r19, 4
+       qbne    $1, r19.b2, 0
+       xout    TXL2, &r2, 64
+       .endm
+
+LAST_DMA_TO_TXL2 .macro runit
+       XFR2VBUS_WAIT4READY runit
+       XFR2VBUS_CANCEL_READ_AUTO_64_CMD (runit)
+       nop
+       XFR2VBUS_READ64_RESULT (runit)
+       BN_TX_N GRegs.tx.b.len
+       .endm
 ;------------------------------------
 ;basic macro for TX fifo filling from MSMC
 ; portQ
@@ -194,47 +189,23 @@ TX_FILL_FIFO      .macro  runit
 ;read in data (now in r2 -r17)  [note: on eop some of this may be garbage]
        qbbs    $2, TxRegs.ds_flags, 4   ; TxRegs.ds_flags.f_desc_read_unit
        qbge    $4, GRegs.tx.b.len, 64
-       XFR2VBUS_WAIT4READY runit
-       XFR2VBUS_READ64_RESULT runit
-wait1?: xin    TXL2, &r19, 4
-       qbne    wait1?, r19.b2, 0
-       xout    TXL2, &r2, 64
+       FROM_DMA_TO_TXL2 runit
        jmp     $3
-$2:
-       qbge    $5, GRegs.tx.b.len, 64
-       XFR2VBUS_WAIT4READY (runit + 1)
-       XFR2VBUS_READ64_RESULT (runit+1)
-wait2?: xin    TXL2, &r19, 4
-       qbne    wait2?, r19.b2, 0
-       xout    TXL2, &r2, 64
-$3:
-;output data
-       sub     GRegs.tx.b.len, GRegs.tx.b.len, 64
-       qblt    $9, GRegs.tx.b.len, 64
-       clr     TxRegs.pp_ppok, TxRegs.pp_ppok, f_pp_enufleft
+$2:    qbge    $5, GRegs.tx.b.len, 64
+       FROM_DMA_TO_TXL2 (runit + 1)
+$3:    sub     GRegs.tx.b.len, GRegs.tx.b.len, 64
        jmp     $9
 
-$4:   ;eop, unit a
-       XFR2VBUS_WAIT4READY runit
-       XFR2VBUS_CANCEL_READ_AUTO_64_CMD (runit)
-       nop
-       XFR2VBUS_READ64_RESULT (runit)
-       BN_TX_N GRegs.tx.b.len
-       SPIN_SET_LOCK_LOC PRU_RTU_EOD_P_FLAG
-       SPIN_CLR_LOCK_LOC PRU_RTU_EOD_P_FLAG
+$4:    LAST_DMA_TO_TXL2 runit
+       qbbc    $6, GRegs.speed_f, f_half_d ; don't tell RTU yet 
+       SPIN_TOG_LOCK_LOC PRU_RTU_EOD_P_FLAG
        jmp     $6
-$5:   ;eop, unit b
-       XFR2VBUS_WAIT4READY (runit + 1)
-       XFR2VBUS_CANCEL_READ_AUTO_64_CMD (runit+1)
-       nop
-       XFR2VBUS_READ64_RESULT (runit+1)
-       BN_TX_N GRegs.tx.b.len
-       SPIN_SET_LOCK_LOC PRU_RTU_EOD_E_FLAG
-       SPIN_CLR_LOCK_LOC PRU_RTU_EOD_E_FLAG
-$6:
-;close out tx
-       qbbs    $7, TxRegs.ds_flags, 0   ;TxRegs.ds_flags.f_desc_do_crc
-       set     r31, r31, 29 ;tx.eof
+$5:    LAST_DMA_TO_TXL2 (runit + 1)
+       qbbc    $6, GRegs.speed_f, f_half_d ; don't tell RTU yet 
+       SPIN_TOG_LOCK_LOC PRU_RTU_EOD_E_FLAG
+$6:    ;close out tx
+       qbbs    $7, TxRegs.ds_flags, 0  ;f_desc_do_crc
+       set     r31, r31, 29            ;tx.eof
        jmp     $8
 
 $7:    or      r31.b3, r31.b3, 0x2c
index 3e050872d6bfbc26f459f37d277638199c46d057..4de59b5cd66f7af421c39edb2ff3f8c3520c5628 100644 (file)
@@ -111,8 +111,7 @@ XFR2VBUS_READ64_RESULT      .macro   rnum
 
 XFR2VBUS_WAIT4READY .macro rnum
 $1:    xin     rnum, &r18, 4
-       qbeq    $2, r18.w0, 0x5
-$2:
+       qbne    $1, r18.w0, 0x5
  .endm
 
 ;read in data8
index 0145d8ac20208567469a567c455f550fb5b3c6a7..9ea847cb9f7580ba1fbec1230e1099229f9025a4 100644 (file)
@@ -27,7 +27,7 @@ PACKAGE_SRCS_COMMON += src/v5 soc/emac_soc_v5.h
 endif
 
 PACKAGE_SRCS_COMMON += makefile emac_component.mk nss_if.h \
-                      emac_hwcfg.h emac_drv.h emacver.h \
+                      emac_hwcfg.h emac_drv.h emac_ioctl.h emacver.h \
                       src/emac_osal.h \
                       build/makefile.mk \
                      build/makefile_indp.mk \
index 182d415f00d1b38487e7d3fbf4f5ca3983e7dbed..0faf5ad799a13c1c42b9c66add6eb31bcba8c537 100644 (file)
@@ -531,17 +531,17 @@ emac_open_udma_channel_tx(uint32_t portNum,EMAC_PER_CHANNEL_CFG_TX*pChCfg)
     chPrms.cqRingPrms.elemCnt   = pChCfg->elementCount;
 
     /* Open TX channel for transmit */
-    retVal = Udma_chOpen(emac_mcb.port_cb[portNum].udmaHandle, pChCfg->chHandle, UDMA_CH_TYPE_TX, &chPrms);
+    retVal = Udma_chOpen(emac_mcb.port_cb[portNum].udmaHandle, (Udma_ChHandle)(pChCfg->chHandle), UDMA_CH_TYPE_TX, &chPrms);
 
     if(UDMA_SOK == retVal)
     {
         UdmaChTxPrms_init(&txPrms, UDMA_CH_TYPE_TX);
         txPrms.filterPsWords = TISCI_MSG_VALUE_RM_UDMAP_TX_CH_FILT_PSWORDS_ENABLED;
         txPrms.dmaPriority = UDMA_DEFAULT_UTC_CH_DMA_PRIORITY;
-        retVal = Udma_chConfigTx(pChCfg->chHandle, &txPrms);
+        retVal = Udma_chConfigTx((Udma_ChHandle)(pChCfg->chHandle), &txPrms);
         if(UDMA_SOK == retVal)
         {
-            retVal = Udma_chEnable(pChCfg->chHandle);
+            retVal = Udma_chEnable((Udma_ChHandle)(pChCfg->chHandle));
             if (UDMA_SOK == retVal)
             {
                 retVal =  EMAC_DRV_RESULT_OK;
@@ -583,7 +583,7 @@ emac_setup_udma_channel_interrupt(uint32_t portNum, EMAC_PER_CHANNEL_CFG_RX*pChC
     UdmaEventPrms_init(&eventPrms);
     eventPrms.eventType         = UDMA_EVENT_TYPE_DMA_COMPLETION;
     eventPrms.eventMode         = UDMA_EVENT_MODE_SHARED;
-    eventPrms.chHandle          = pChCfg->chHandle;
+    eventPrms.chHandle          = (Udma_ChHandle)(pChCfg->chHandle);
     eventPrms.masterEventHandle = NULL;
 
     pRxChannel->subChan[0].eventHandle = eventHandle;
@@ -603,10 +603,10 @@ emac_setup_udma_channel_interrupt(uint32_t portNum, EMAC_PER_CHANNEL_CFG_RX*pChC
     {
         EMAC_osalSemParamsInit(&semParams);
         semParams.mode = SemaphoreP_Mode_BINARY;
-        semParams.name= "rxSemaphore";
+        semParams.name= (char*)("rxSemaphore");
         if (eventType == EMAC__RX_PKT_CHAN)
         {
-            semParams.name= "rxSemaphore";
+            semParams.name= (char*)("rxSemaphore");
             EMAC_GLOBAL_RX_SEM_HANDLE(portNum, ringNum) =  EMAC_osalCreateBlockingLock(0,&semParams);
             if((EMAC_GLOBAL_RX_SEM_HANDLE(portNum, ringNum)) ==  NULL)
             {
@@ -615,7 +615,7 @@ emac_setup_udma_channel_interrupt(uint32_t portNum, EMAC_PER_CHANNEL_CFG_RX*pChC
         }
         else
         {
-            semParams.name= "rxMgmtSemaphore";
+            semParams.name= (char*)("rxMgmtSemaphore");
             EMAC_GLOBAL_RX_MGMT_SEM_HANDLE(portNum, ringNum) =  EMAC_osalCreateBlockingLock(0,&semParams);
             if((EMAC_GLOBAL_RX_MGMT_SEM_HANDLE(portNum, ringNum)) ==  NULL)
             {
@@ -648,8 +648,8 @@ emac_setup_additional_flows(uint32_t portNum, EMAC_PER_CHANNEL_CFG_RX*pChCfg, ui
             /* subChan 0 is the default flow, start with subChan 1 for additinal flows*/
             for (subChanNum = 1; subChanNum < pChCfg->nsubChan;subChanNum++)
             {
-                 freeRingHandle = pChCfg->subChan[subChanNum].freeRingHandle[0];
-                 completionRingHandle = pChCfg->subChan[subChanNum].compRingHandle;
+                 freeRingHandle = (Udma_RingHandle)(pChCfg->subChan[subChanNum].freeRingHandle[0]);
+                 completionRingHandle = (Udma_RingHandle)(pChCfg->subChan[subChanNum].compRingHandle);
  
                 if (channelType == EMAC__RX_PKT_CHAN)
                 {
@@ -756,7 +756,7 @@ emac_setup_udma_channel_rx(uint32_t portNum,EMAC_PER_CHANNEL_CFG_RX* pChCfg, uin
     uint32_t regVal;
 
     UTILS_trace(UTIL_TRACE_LEVEL_INFO, emac_mcb.drv_trace_cb, "port: %d: ENTER",portNum);
-    chHandle = pChCfg->chHandle;
+    chHandle = (Udma_ChHandle)(pChCfg->chHandle);
 
     if (pChCfg->nsubChan > 0)
     {
@@ -989,7 +989,7 @@ static int32_t
 emac_close_tx_subsystem (uint32_t port_num)
 {
     EMAC_CPPI_DESC_T *pCppiDesc;
-    int32_t chanNum;
+    uint32_t chanNum;
     Udma_ChHandle txChHandle;
     UTILS_trace(UTIL_TRACE_LEVEL_INFO, emac_mcb.drv_trace_cb, "port: %d: ENTER",port_num);
 
@@ -1127,7 +1127,7 @@ void emac_cleanup_free_ring(uint32_t portNum, uint64_t *pRingMem)
 static int32_t
 emac_close_rx_subsystem (uint32_t port_num)
 {
-    int32_t subChanNum ;
+    uint32_t subChanNum ;
     Udma_RingHandle ringHandle = NULL;
 
     uint32_t numSubChan;
@@ -1136,11 +1136,11 @@ emac_close_rx_subsystem (uint32_t port_num)
     if (emac_mcb.port_cb[port_num].mode_of_operation == EMAC_MODE_INTERRUPT)
     {
         EMAC_osalDeleteBlockingLock(EMAC_GLOBAL_RX_SEM_HANDLE(port_num, subChanNum));
-        Udma_eventUnRegister(emac_mcb.port_cb[port_num].rxPktCh.subChan[subChanNum].eventHandle);
+        Udma_eventUnRegister((Udma_EventHandle)(emac_mcb.port_cb[port_num].rxPktCh.subChan[subChanNum].eventHandle));
         if (port_num != EMAC_CPSW_PORT_NUM)
         {
             EMAC_osalDeleteBlockingLock(EMAC_GLOBAL_RX_MGMT_SEM_HANDLE(port_num, subChanNum));
-            Udma_eventUnRegister(emac_mcb.port_cb[port_num].rxMgmtCh.subChan[subChanNum].eventHandle);
+            Udma_eventUnRegister((Udma_EventHandle)(emac_mcb.port_cb[port_num].rxMgmtCh.subChan[subChanNum].eventHandle));
         }
     }
 
@@ -1149,19 +1149,19 @@ emac_close_rx_subsystem (uint32_t port_num)
     {
         Udma_chClose(emac_mcb.port_cb[port_num].rxPktCh.rxChHandle);
         emac_cleanup_comp_ring(port_num, emac_mcb.port_cb[port_num].rxPktCh.rxChHandle->cqRing);
-        emac_cleanup_free_ring(port_num, emac_mcb.port_cb[port_num].rxPktCh.subChan[0].freeRingMem[0]);
+        emac_cleanup_free_ring(port_num, (uint64_t *)(emac_mcb.port_cb[port_num].rxPktCh.subChan[0].freeRingMem[0]));
         numSubChan = emac_mcb.port_cb[port_num].rxPktCh.nsubChan;
         if (numSubChan > 1)
         {
             Udma_flowFree(emac_mcb.port_cb[port_num].rxPktCh.flowHandle);
-            for(subChanNum = 1;subChanNum < numSubChan;subChanNum++)
+            for(subChanNum = 1; subChanNum < numSubChan;subChanNum++)
             {
                 ringHandle = emac_mcb.port_cb[port_num].pollTable.rxPkt[subChanNum].compRingHandle;
                 emac_cleanup_comp_ring(port_num, ringHandle);
                 Udma_ringFree(ringHandle);
 
                 ringHandle = emac_mcb.port_cb[port_num].pollTable.rxPkt[subChanNum].freeRingHandle;
-                emac_cleanup_free_ring(port_num, emac_mcb.port_cb[port_num].rxPktCh.subChan[subChanNum].freeRingMem[0]);
+                emac_cleanup_free_ring(port_num, (uint64_t *)(emac_mcb.port_cb[port_num].rxPktCh.subChan[subChanNum].freeRingMem[0]));
                 Udma_ringFree(ringHandle);
             }
         }
@@ -1171,7 +1171,7 @@ emac_close_rx_subsystem (uint32_t port_num)
     if (emac_mcb.port_cb[port_num].rxMgmtCh2.rxChHandle)
     {
         Udma_chClose(emac_mcb.port_cb[port_num].rxMgmtCh2.rxChHandle);
-        emac_cleanup_free_ring(port_num, emac_mcb.port_cb[port_num].rxMgmtCh2.subChan[0].freeRingMem[0]);
+        emac_cleanup_free_ring(port_num, (uint64_t *)(emac_mcb.port_cb[port_num].rxMgmtCh2.subChan[0].freeRingMem[0]));
     }
 
     /* free up resources for rx mgmt channel and sub-channels */
@@ -1179,7 +1179,7 @@ emac_close_rx_subsystem (uint32_t port_num)
     {
         Udma_chClose(emac_mcb.port_cb[port_num].rxMgmtCh.rxChHandle);
         emac_cleanup_comp_ring(port_num, emac_mcb.port_cb[port_num].rxMgmtCh.rxChHandle->cqRing);
-        emac_cleanup_free_ring(port_num, emac_mcb.port_cb[port_num].rxMgmtCh.subChan[0].freeRingMem[0]);
+        emac_cleanup_free_ring(port_num, (uint64_t *)(emac_mcb.port_cb[port_num].rxMgmtCh.subChan[0].freeRingMem[0]));
         numSubChan = emac_mcb.port_cb[port_num].rxMgmtCh.nsubChan;
         if (numSubChan > 1)
         {
@@ -1191,7 +1191,7 @@ emac_close_rx_subsystem (uint32_t port_num)
                 Udma_ringFree(ringHandle);
     
                 ringHandle = emac_mcb.port_cb[port_num].pollTable.rxMgmt[subChanNum].freeRingHandle;
-                emac_cleanup_free_ring(port_num, emac_mcb.port_cb[port_num].rxMgmtCh.subChan[subChanNum].freeRingMem[0]);
+                emac_cleanup_free_ring(port_num, (uint64_t *)(emac_mcb.port_cb[port_num].rxMgmtCh.subChan[subChanNum].freeRingMem[0]));
                 Udma_ringFree(ringHandle);
             }
         }
@@ -1267,7 +1267,7 @@ static EMAC_DRV_ERR_E emac_interposer_setup_switch(uint32_t port_num,  EMAC_OPEN
  */
 static void emac_config_icssg_dual_mac_fw(uint32_t port_num, EMAC_HwAttrs_V5 *hwAttrs)
 {
-    int32_t bufferPoolNum;
+    uint32_t bufferPoolNum;
     EMAC_PER_PORT_ICSSG_FW_CFG *pEmacFwCfg;
     EMAC_PRU_CFG_T pruCfg;
     Udma_FlowHandle flowHandle;
@@ -1324,9 +1324,9 @@ static void emac_config_icssg_dual_mac_fw(uint32_t port_num, EMAC_HwAttrs_V5 *hw
             pruCfg.mgr_flow= Udma_flowGetNum( flowHandle);
         }
 
-        for (bufferPoolNum = 8; bufferPoolNum < EMAC_NUM_TRANSMIT_FW_QUEUES*2;bufferPoolNum++)
+        for (bufferPoolNum = 8U; bufferPoolNum < EMAC_NUM_TRANSMIT_FW_QUEUES*2;bufferPoolNum++)
         {
-            pruCfg.tx_bs[bufferPoolNum] = pDmFwCfg->txHostQueueSize[bufferPoolNum-8];
+            pruCfg.tx_bs[bufferPoolNum] = pDmFwCfg->txHostQueueSize[bufferPoolNum-8U];
         }
     
         emac_hw_mem_write(hwAttrs->portCfg[port_num].icssSharedRamBaseAddr, &(pruCfg),(sizeof(EMAC_PRU_CFG_T)/4));
@@ -1806,11 +1806,11 @@ static EMAC_DRV_ERR_E EMAC_get_stats_v5(uint32_t port_num, EMAC_STATISTICS_T*
 /*
  *  ======== emac_read_icssg_hw_stats ========
  */
-void emac_read_icssg_hw_stats(uintptr_t statsBaseAddr, uint32_t* statPtr, int8_t statsOffset, bool clear)
+void emac_read_icssg_hw_stats(uintptr_t statsBaseAddr, uint32_t* statPtr, uint8_t statsOffset, bool clear)
 
 {
     uint32_t *tempStatsPtr = (uint32_t*)statPtr;
-    int8_t i;
+    uint8_t i;
     for (i = statsOffset;  i < sizeof(EMAC_STATISTICS_ICSSG_T)/4; i++)
     {
         *tempStatsPtr = CSL_REG32_RD(statsBaseAddr+ (i *4));
@@ -1851,7 +1851,7 @@ static EMAC_DRV_ERR_E EMAC_get_stats_icssg_v5(uint32_t port_num, EMAC_STATISTICS
                 if ((emac_is_port_open(0,3) == true))
                 {
                     /* need to query port 0 for RX*/
-                    emac_read_icssg_hw_stats(emac_mcb.port_cb[0].icssgCfgRegBaseAddr +  CSL_ICSS_G_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_RX_STAT_GOOD_PRU0, statPtr, 0, clear);
+                    emac_read_icssg_hw_stats(emac_mcb.port_cb[0].icssgCfgRegBaseAddr +  CSL_ICSS_G_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_RX_STAT_GOOD_PRU0, statPtr, 0U, clear);
                     /* need to query port 3 for TX*/
                     statPtr = (uint32_t*)p_stats + EMAC_ICSSG_TX_STATS_OFFSET ;
                     emac_read_icssg_hw_stats(emac_mcb.port_cb[3].icssgCfgRegBaseAddr +  CSL_ICSS_G_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_RX_STAT_GOOD_PRU1, (uint32_t*)p_stats + EMAC_ICSSG_TX_STATS_OFFSET, EMAC_ICSSG_TX_STATS_OFFSET, clear);
@@ -1863,7 +1863,7 @@ static EMAC_DRV_ERR_E EMAC_get_stats_icssg_v5(uint32_t port_num, EMAC_STATISTICS
                 if ((emac_is_port_open(2,1) == true))
                 {
                     /* need to query port 2 for RX */
-                    emac_read_icssg_hw_stats(emac_mcb.port_cb[2].icssgCfgRegBaseAddr +  CSL_ICSS_G_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_RX_STAT_GOOD_PRU0, statPtr, 0, clear);
+                    emac_read_icssg_hw_stats(emac_mcb.port_cb[2].icssgCfgRegBaseAddr +  CSL_ICSS_G_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_RX_STAT_GOOD_PRU0, statPtr, 0U, clear);
                     /* need to query port 1 for TX */
                     statPtr = (uint32_t*)p_stats + EMAC_ICSSG_TX_STATS_OFFSET;
                     emac_read_icssg_hw_stats(emac_mcb.port_cb[1].icssgCfgRegBaseAddr + CSL_ICSS_G_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_RX_STAT_GOOD_PRU1, (uint32_t*)p_stats + EMAC_ICSSG_TX_STATS_OFFSET , EMAC_ICSSG_TX_STATS_OFFSET, clear);
@@ -1875,7 +1875,7 @@ static EMAC_DRV_ERR_E EMAC_get_stats_icssg_v5(uint32_t port_num, EMAC_STATISTICS
                 if ((emac_is_port_open(0,3) == true))
                 {
                     /* need to query port 0 for RX*/
-                    emac_read_icssg_hw_stats(emac_mcb.port_cb[0].icssgCfgRegBaseAddr +  CSL_ICSS_G_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_RX_STAT_GOOD_PRU0, statPtr, 0, clear);
+                    emac_read_icssg_hw_stats(emac_mcb.port_cb[0].icssgCfgRegBaseAddr +  CSL_ICSS_G_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_RX_STAT_GOOD_PRU0, statPtr, 0U, clear);
                     /* need to query port 3 for TX*/
                     statPtr = (uint32_t*)p_stats + EMAC_ICSSG_TX_STATS_OFFSET;
                     emac_read_icssg_hw_stats(emac_mcb.port_cb[3].icssgCfgRegBaseAddr +  CSL_ICSS_G_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_RX_STAT_GOOD_PRU1, (uint32_t*)p_stats + EMAC_ICSSG_TX_STATS_OFFSET, EMAC_ICSSG_TX_STATS_OFFSET, clear);
@@ -1887,7 +1887,7 @@ static EMAC_DRV_ERR_E EMAC_get_stats_icssg_v5(uint32_t port_num, EMAC_STATISTICS
                 if ((emac_is_port_open(1,1) == true))
                 {
                     /* need to query port 2 for RX*/
-                    emac_read_icssg_hw_stats(emac_mcb.port_cb[2].icssgCfgRegBaseAddr +  CSL_ICSS_G_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_RX_STAT_GOOD_PRU0, statPtr, 0, clear);
+                    emac_read_icssg_hw_stats(emac_mcb.port_cb[2].icssgCfgRegBaseAddr +  CSL_ICSS_G_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_RX_STAT_GOOD_PRU0, statPtr, 0U, clear);
                     /* need to query port 1 for TX*/
                     statPtr = (uint32_t*)p_stats + EMAC_ICSSG_TX_STATS_OFFSET;
                     emac_read_icssg_hw_stats(emac_mcb.port_cb[1].icssgCfgRegBaseAddr +  CSL_ICSS_G_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_RX_STAT_GOOD_PRU1, (uint32_t*)p_stats + EMAC_ICSSG_TX_STATS_OFFSET , EMAC_ICSSG_TX_STATS_OFFSET, clear);
@@ -1902,11 +1902,11 @@ static EMAC_DRV_ERR_E EMAC_get_stats_icssg_v5(uint32_t port_num, EMAC_STATISTICS
                     {
                         if ((port_num & 1) == 0)
                         {
-                            emac_read_icssg_hw_stats(emac_mcb.port_cb[port_num].icssgCfgRegBaseAddr +  CSL_ICSS_G_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_RX_STAT_GOOD_PRU0, statPtr, 0, clear);
+                            emac_read_icssg_hw_stats(emac_mcb.port_cb[port_num].icssgCfgRegBaseAddr +  CSL_ICSS_G_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_RX_STAT_GOOD_PRU0, statPtr, 0U, clear);
                         }
                         else
                         {
-                            emac_read_icssg_hw_stats(emac_mcb.port_cb[port_num].icssgCfgRegBaseAddr +  CSL_ICSS_G_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_RX_STAT_GOOD_PRU1, statPtr, 0, clear);
+                            emac_read_icssg_hw_stats(emac_mcb.port_cb[port_num].icssgCfgRegBaseAddr +  CSL_ICSS_G_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_RX_STAT_GOOD_PRU1, statPtr, 0U, clear);
                         }
                         retVal = EMAC_DRV_RESULT_OK;
                     }
index 8a92f53135eb87b1f4477b4defd80cf797efa680..771dc963c392ac98ce8a656cbce69849d01d0a78 100644 (file)
@@ -593,7 +593,7 @@ void emac_ioctl_vlan_ctrl_set_default_tbl(uint32_t port_num, void* ctrl)
     EMAC_PER_PORT_ICSSG_FW_CFG *pEmacFwCfg;
     EMAC_ICSSG_SWITCH_FW_CFG *pSwitchFwCfg;
     EMAC_IOCTL_VLAN_FID_PARAMS *pVlanTblEntryParams = (EMAC_IOCTL_VLAN_FID_PARAMS*)ctrl;
-    int32_t count;
+    uint32_t count;
     uint16_t vlanEntry;
 
     UTILS_trace(UTIL_TRACE_LEVEL_INFO, emac_mcb.drv_trace_cb, "port: %d: ENTER",port_num);
@@ -609,9 +609,9 @@ void emac_ioctl_vlan_ctrl_set_default_tbl(uint32_t port_num, void* ctrl)
         vlanEntry  |=  (pVlanTblEntryParams->fid << 8);
 
         /* Initialize VLAN-FID table */
-        for(count=0; count < (EMAC_VLAN_TBL_MAX_ENTRIES-1); count++)
+        for(count=0U; count < (EMAC_VLAN_TBL_MAX_ENTRIES-1U); count++)
         {
-            CSL_REG16_WR(( emac_mcb.port_cb[port_num].icssSharedRamBaseAddr+ pSwitchFwCfg->defaultVlanTblOffset) +count*2, vlanEntry);
+            CSL_REG16_WR(( emac_mcb.port_cb[port_num].icssSharedRamBaseAddr+ pSwitchFwCfg->defaultVlanTblOffset) +count*2U, vlanEntry);
         }
     }
     UTILS_trace(UTIL_TRACE_LEVEL_INFO, emac_mcb.drv_trace_cb, "port: %d: EXIT",port_num);
@@ -783,8 +783,7 @@ void emac_ioctl_port_prio_mapping_ctrl(uint32_t port_num, void*  ctrl)
     uint32_t gateConfig = 0x50;
     uint32_t tempReg = 0;
     EMAC_FILTER3_CONFIG ft3ConfigPcp = {0xc, 0, 0, 0, 0, 5, 0, 0xff1f0000, 0, 0, 0xffffffff, 0xffffffff};
-    int8_t p;
-    int8_t c;
+    uint8_t pcp;
     uint8_t finalPrioQueueMap[EMAC_IOCTL_PRIO_MAX]={0};
 
     UTILS_trace(UTIL_TRACE_LEVEL_INFO, emac_mcb.drv_trace_cb, "port: %d: ENTER",port_num);
@@ -810,12 +809,12 @@ void emac_ioctl_port_prio_mapping_ctrl(uint32_t port_num, void*  ctrl)
         */
 
         /* set up filter type 3's to match pcp bits */
-        for (p = 0; p < EMAC_IOCTL_PRIO_MAX; p++)
+        for (pcp = 0U; pcp < EMAC_IOCTL_PRIO_MAX; pcp++)
         {
             /*Setup FT3[0:7] to detect PCP0 - PCP7 */
-            ft3Type = (uint32_t)((((uint32_t)p) << 21) | 0x00000081);
+            ft3Type = (uint32_t)((((uint32_t)pcp) << 21U) | 0x00000081U);
             ft3ConfigPcp.ft3Type = ft3Type;
-            emac_icssg_filter3_config(port_num, 0, p, &ft3ConfigPcp);
+            emac_icssg_filter3_config(port_num, 0, pcp, &ft3ConfigPcp);
         }
 
         /*Get the Queue mapping value from DRAM0 and calculate incoming PCP to Queue mapping*/
@@ -823,47 +822,47 @@ void emac_ioctl_port_prio_mapping_ctrl(uint32_t port_num, void*  ctrl)
         pSwitchFwCfg = (EMAC_ICSSG_SWITCH_FW_CFG*) pEmacFwCfg->pFwPortCfg;
         prioRegenMapOffset = pSwitchFwCfg->prioRegenTableOffset;
 
-        for(p = 0; p < EMAC_IOCTL_PRIO_MAX; p++)
+        for(pcp = 0U; pcp < EMAC_IOCTL_PRIO_MAX; pcp++)
         {
             /* Get regenerated value for PCP = p*/
-            tempVal = CSL_REG8_RD(icssgBaseAddr + prioRegenMapOffset + (p*4));
+            tempVal = CSL_REG8_RD(icssgBaseAddr + prioRegenMapOffset + (pcp*4U));
             /*Shift PCP value by 5 to get the value*/
             tempVal = tempVal >> 5;
 
-            finalPrioQueueMap[p] = (uint8_t)pPrioMap->portPrioMap[tempVal];
+            finalPrioQueueMap[pcp] = (uint8_t)pPrioMap->portPrioMap[tempVal];
         }
 
         /* Build up the or lists */
-        for (p = 0; p < EMAC_IOCTL_PRIO_MAX; p++)
+        for (pcp = 0U; pcp < EMAC_IOCTL_PRIO_MAX; pcp++)
         {
-            classSelect = finalPrioQueueMap[p];
-            orEnable[classSelect] |= (1 << p);
+            classSelect = finalPrioQueueMap[pcp];
+            orEnable[classSelect] |= (1U << pcp);
         }
 
         /* now program classifier c */
-        for (c = 0; c<EMAC_IOCTL_PRIO_MAX;c++ )
+        for (pcp = 0U; pcp < EMAC_IOCTL_PRIO_MAX;pcp++ )
         {
             /* Configure OR Enable*/
-            CSL_REG32_WR((baseAddr + CSL_ICSS_G_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_RX_CLASS0_OR_EN_PRU0 + (8*c)), orEnable[c]);
+            CSL_REG32_WR((baseAddr + CSL_ICSS_G_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_RX_CLASS0_OR_EN_PRU0 + (8U*pcp)), orEnable[pcp]);
             /* Configure AND Enable */
-            CSL_REG32_WR((baseAddr + CSL_ICSS_G_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_RX_CLASS0_AND_EN_PRU0 + (8*c)), andEnable[c]);
+            CSL_REG32_WR((baseAddr + CSL_ICSS_G_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_RX_CLASS0_AND_EN_PRU0 + (8U*pcp)), andEnable[pcp]);
             tempReg = CSL_REG32_RD(baseAddr + CSL_ICSS_G_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_RX_CLASS_CFG1_PRU0);
-            tempReg &= ~(0x3 << (c * 2));
+            tempReg &= ~(0x3U << (pcp * 2U));
             CSL_REG32_WR((baseAddr + CSL_ICSS_G_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_RX_CLASS_CFG1_PRU0), tempReg);
             /* Configure NV Enable */
             /* Configure NV Enable bits (1 bit in upper16, 1bit in lower16 */
             tempReg = CSL_REG32_RD(baseAddr + CSL_ICSS_G_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_RX_CLASS_CFG2_PRU0);
-            if (orNvEnable[c])
-                tempReg |= 1 << (c + 16);
+            if (orNvEnable[pcp])
+                tempReg |= 1U << (pcp + 16U);
             else
-                tempReg &= ~(1 << (c + 16));
-            if (andNvEnable[c])
-                tempReg |= 1 << (c);
+                tempReg &= ~(1U << (pcp + 16U));
+            if (andNvEnable[pcp])
+                tempReg |= 1U << (pcp);
             else
-                tempReg &= ~(1 << (c));
+                tempReg &= ~(1U << (pcp));
             CSL_REG32_WR((baseAddr + CSL_ICSS_G_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_RX_CLASS_CFG2_PRU0), tempReg);
             /* Configure class gate */
-            CSL_REG32_WR((baseAddr + CSL_ICSS_G_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_RX_CLASS_GATES0_PRU0 + (4*c)), gateConfig);
+            CSL_REG32_WR((baseAddr + CSL_ICSS_G_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_RX_CLASS_GATES0_PRU0 + (4U * pcp)), gateConfig);
         }
 
         /* Update Deafult Queue number for untagged packet*/
@@ -1072,7 +1071,7 @@ EMAC_DRV_ERR_E emac_ioctl_fdb_entry_ctrl(uint32_t port_num, void* p_params)
     uint16_t broadSideSlot;
 
     UTILS_trace(UTIL_TRACE_LEVEL_INFO, emac_mcb.drv_trace_cb, "port: %d: ENTER",port_num);
-    if ((entry->vlanId < (EMAC_VLAN_TBL_MAX_ENTRIES)) || (entry->vlanId == EMAC_VLAN_UNTAGGED))
+    if ((entry->vlanId < (int16_t)(EMAC_VLAN_TBL_MAX_ENTRIES)) || (entry->vlanId == EMAC_VLAN_UNTAGGED))
     {
         vlanDefaultTblAddr = emac_get_vlan_tbl_addr(port_num);
         emac_get_vlan_id(port_num, entry);
@@ -1213,17 +1212,16 @@ EMAC_DRV_ERR_E emac_ioctl_prio_regen_mapping_ctrl(uint32_t port_num, void*  ctrl
         uint32_t gateConfig = 0x50;
         uint32_t tempReg = 0;
         EMAC_FILTER3_CONFIG ft3ConfigPcp = {0xc, 0, 0, 0, 0, 5, 0, 0xff1f0000, 0, 0, 0xffffffff, 0xffffffff};
-        int8_t p;
-        int8_t c;
+        uint8_t pcp;
         uint8_t finalPrioQueueMap[EMAC_IOCTL_PRIO_MAX]={0};
 
         /* set up filter type 3's to match pcp bits */
-        for (p = 0; p < EMAC_IOCTL_PRIO_MAX; p++)
+        for (pcp = 0U; pcp < EMAC_IOCTL_PRIO_MAX; pcp++)
         {
             /*Setup FT3[0:7] to detect PCP0 - PCP7 */
-            ft3Type = (uint32_t)((((uint32_t)p) << 21) | 0x00000081);
+            ft3Type = (uint32_t)((((uint32_t)pcp) << 21U) | 0x00000081U);
             ft3ConfigPcp.ft3Type = ft3Type;
-            emac_icssg_filter3_config(port_num, 0, p, &ft3ConfigPcp);
+            emac_icssg_filter3_config(port_num, 0, pcp, &ft3ConfigPcp);
         }
 
         /*Get the Queue mapping value from DRAM0 and calculate incoming PCP to Queue mapping*/
@@ -1231,41 +1229,41 @@ EMAC_DRV_ERR_E emac_ioctl_prio_regen_mapping_ctrl(uint32_t port_num, void*  ctrl
         pSwitchFwCfg = (EMAC_ICSSG_SWITCH_FW_CFG*) pEmacFwCfg->pFwPortCfg;
         prioMapOffset = pSwitchFwCfg->prioMappingTableOffset;
         icssgBaseAddr = emac_mcb.port_cb[port_num].icssDram0BaseAddr;
-        for(p = 0; p < EMAC_IOCTL_PRIO_MAX; p++)
+        for(pcp = 0U; pcp < EMAC_IOCTL_PRIO_MAX; pcp++)
         {
-            finalPrioQueueMap[p] = CSL_REG8_RD(icssgBaseAddr + prioMapOffset + (pPrioRegenMap->prioRegenMap[p]));
+            finalPrioQueueMap[pcp] = CSL_REG8_RD(icssgBaseAddr + prioMapOffset + (pPrioRegenMap->prioRegenMap[pcp]));
         }
         /* Build up the or lists */
-        for (p = 0; p < EMAC_IOCTL_PRIO_MAX; p++)
+        for (pcp = 0U; pcp < EMAC_IOCTL_PRIO_MAX; pcp++)
         {
-            classSelect = finalPrioQueueMap[p];
-            orEnable[classSelect] |= (1 << p);
+            classSelect = finalPrioQueueMap[pcp];
+            orEnable[classSelect] |= (1U << pcp);
         }
 
         /* now program classifier c */
-        for (c = 0; c<EMAC_IOCTL_PRIO_MAX;c++ )
+        for (pcp = 0U; pcp < EMAC_IOCTL_PRIO_MAX; pcp++ )
         {
             /* Configure OR Enable*/
-            CSL_REG32_WR((baseAddr + CSL_ICSS_G_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_RX_CLASS0_OR_EN_PRU0 + (8*c)), orEnable[c]);
+            CSL_REG32_WR((baseAddr + CSL_ICSS_G_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_RX_CLASS0_OR_EN_PRU0 + (8U * pcp)), orEnable[pcp]);
             /* Configure AND Enable */
-            CSL_REG32_WR((baseAddr + CSL_ICSS_G_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_RX_CLASS0_AND_EN_PRU0 + (8*c)), andEnable[c]);
+            CSL_REG32_WR((baseAddr + CSL_ICSS_G_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_RX_CLASS0_AND_EN_PRU0 + (8U * pcp)), andEnable[pcp]);
             tempReg = CSL_REG32_RD(baseAddr + CSL_ICSS_G_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_RX_CLASS_CFG1_PRU0);
-            tempReg &= ~(0x3 << (c * 2));
+            tempReg &= ~(0x3U << (pcp * 2U));
             CSL_REG32_WR((baseAddr + CSL_ICSS_G_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_RX_CLASS_CFG1_PRU0), tempReg);
             /* Configure NV Enable */
             /* Configure NV Enable bits (1 bit in upper16, 1bit in lower16 */
             tempReg = CSL_REG32_RD(baseAddr + CSL_ICSS_G_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_RX_CLASS_CFG2_PRU0);
-            if (orNvEnable[c])
-                tempReg |= 1 << (c + 16);
+            if (orNvEnable[pcp])
+                tempReg |= 1U << (pcp + 16U);
             else
-                tempReg &= ~(1 << (c + 16));
-            if (andNvEnable[c])
-                tempReg |= 1 << (c);
+                tempReg &= ~(1U << (pcp + 16U));
+            if (andNvEnable[pcp])
+                tempReg |= 1U << (pcp);
             else
-                tempReg &= ~(1 << (c));
+                tempReg &= ~(1U << (pcp));
             CSL_REG32_WR((baseAddr + CSL_ICSS_G_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_RX_CLASS_CFG2_PRU0), tempReg);
             /* Configure class gate */
-            CSL_REG32_WR((baseAddr + CSL_ICSS_G_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_RX_CLASS_GATES0_PRU0 + (4*c)), gateConfig);
+            CSL_REG32_WR((baseAddr + CSL_ICSS_G_PR1_MII_RT_PR1_MII_RT_G_CFG_REGS_G_RX_CLASS_GATES0_PRU0 + (4U * pcp)), gateConfig);
         }
 
         emac_ioctl_get_fw_config(port_num, &pEmacFwCfg);
@@ -1439,7 +1437,7 @@ EMAC_DRV_ERR_E emac_ioctl_configure_cut_through_or_prempt_select_ctrl(uint32_t p
     }
     else
     {
-        int8_t queue_num;
+        uint8_t queue_num;
         uint8_t temp_byte;
         uintptr_t expressPremptiveQueueAddr;
         EMAC_IOCTL_PARAMS *pParams = (EMAC_IOCTL_PARAMS*) p_params;
@@ -1452,10 +1450,10 @@ EMAC_DRV_ERR_E emac_ioctl_configure_cut_through_or_prempt_select_ctrl(uint32_t p
             emac_mcb.port_cb[port_num].getFwCfg(port_num,&pEmacFwCfg);
             pSwitchFwCfg = (EMAC_ICSSG_SWITCH_FW_CFG*) pEmacFwCfg->pFwPortCfg;
             expressPremptiveQueueAddr = emac_mcb.port_cb[port_num].icssDram0BaseAddr + pSwitchFwCfg->expressPremptiveQueueOffset;
-            for (queue_num = 0; queue_num < EMAC_IOCTL_PRIO_MAX; queue_num++)
+            for (queue_num = 0U; queue_num < EMAC_IOCTL_PRIO_MAX; queue_num++)
             {
-                temp_byte = (entry->pcpPreemptMap[queue_num] << 4) | (entry->pcpCutThroughMap[queue_num] << 7);   /*as per bit order in descriptor flags. Helps save PRU cycles*/
-                CSL_REG8_WR(expressPremptiveQueueAddr+(queue_num*4), temp_byte);
+                temp_byte = (entry->pcpPreemptMap[queue_num] << 4U) | (entry->pcpCutThroughMap[queue_num] << 7U);   /*as per bit order in descriptor flags. Helps save PRU cycles*/
+                CSL_REG8_WR(expressPremptiveQueueAddr+(queue_num*4U), temp_byte);
             }
         }
     }
index 01a927eaf8df38955dbc43e6c9b9694530995194..55581501c9ea8e9c699a1db9616be56b8e14634a 100644 (file)
 #ifndef EMAC_OSAL_V5_H
 #define EMAC_OSAL_V5_H
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /* include TI OSAL library interface header files */
 #include <ti/osal/osal.h>
 #include <ti/drv/emac/src/emac_osal.h>
@@ -107,9 +111,7 @@ static inline void Emac_osalFreeAlign
     void *result = (void *)*(aligned - 1);
     Osal_free(result, size);
 }
-//typedef uint64_t physptr_t;
 
-#if 1
 #if defined (__aarch64__)
 typedef uint64_t physptr_t;
 #else
@@ -117,9 +119,9 @@ typedef uint32_t physptr_t;
 #endif
 #endif
 
+
+#ifdef __cplusplus
+}
 #endif
 
-/**
-@}
-*/
-#endif /* __EMAC_OSAL_H__ */
+#endif /* EMAC_OSAL_V5_H */
index a013d451b02240c644eccd82cfa2d4023fd508e2..87f211668b13c24f18e142118f20af94365301e0 100644 (file)
@@ -435,7 +435,7 @@ uint32_t *emac_util_get_R30_info(EMAC_IOctlR30Cmd cmd, uint32_t port, EMAC_Icssg
  */
 void emac_hw_mem_write(uint32_t addr, const void *ptr, uint32_t element_count)
 {
-    int i;
+    uint32_t  i;
     volatile uint32_t *dst = (volatile uint32_t *)(uintptr_t)addr;
     uint32_t *src = (uint32_t *)ptr;
     for (i = 0; i < element_count; i++)
index c6ea8ca9c0f9a6a0978138428f64be3ebce37b94..2ec07ceaf9e21f6a5082a4528de8ff9143d604b9 100644 (file)
@@ -58,8 +58,6 @@
 
 #include <ti/drv/emac/src/emac_osal.h>
 #include <ti/drv/emac/emac_ioctl.h>
-#include <ti/drv/emac/firmware/icss_dualmac/config/emac_fw_config_dual_mac.h>
-#include <ti/drv/emac/firmware/icss_switch/config/emac_fw_config_switch.h>
 /* SOC Include Files. */
 #include <ti/drv/emac/soc/emac_soc_v5.h>
 
@@ -76,6 +74,8 @@
 #endif
 
 #ifdef EMAC_TEST_APP_ICSSG
+#include <ti/drv/emac/firmware/icss_dualmac/config/emac_fw_config_dual_mac.h>
+#include <ti/drv/emac/firmware/icss_switch/config/emac_fw_config_switch.h>
 /* PRUSS Driver Header File. */
 #include <ti/drv/pruss/pruicss.h>
 #include <ti/drv/pruss/soc/pruicss_v1.h>
@@ -1208,6 +1208,7 @@ int32_t app_test_send_receive(uint32_t startP, uint32_t endP, uint32_t displayRe
     return status;
 }
 
+#ifdef EMAC_TEST_APP_ICSSG
 #define TX_BUFF_POOL_SIZE 0X1800u
 #define TX_BUFF_POOL_TOTAL_DUAL_MAC (TX_BUFF_POOL_SIZE + 0x80) * 8U /* //50176 per PORT, total of 100352 */
 void app_test_setup_fw_dualmac(uint32_t port_num, EMAC_HwAttrs_V5 *pEmacCfg)
@@ -1231,6 +1232,7 @@ void app_test_setup_fw_dualmac(uint32_t port_num, EMAC_HwAttrs_V5 *pEmacCfg)
     pEmacCfg->portCfg[port_num].getFwCfg = &emacGetDualMacFwConfig;
 
 }
+#endif
 
 int32_t app_test_emac_open(uint32_t mode)
 {
@@ -1474,17 +1476,51 @@ void emac_test_get_cpsw_stats(void)
     UART_printf("EMAC_UT_%d  collecting cpsw stats passed\n", app_test_id);
 }
 
+#define APP_TEST_AM65XX_PG1_0_VERSION (0x0BB5A02FU)
+
 void app_test_udma_init(void)
 {
     int32_t         retVal = UDMA_SOK;
     Udma_InitPrms   initPrms;
     uint32_t        instId;
 
-#ifdef EMAC_TEST_APP_CPSW
+#if defined (SOC_AM65XX)
+#if defined (EMAC_TEST_APP_CPSW)
+    /* if A53 and pg 1.0 use mcu navss due to hw errata*/
+    uint32_t pgVersion = CSL_REG32_RD(CSL_WKUP_CTRL_MMR0_CFG0_BASE + CSL_WKUP_CTRL_MMR_CFG0_JTAGID);
+#if defined (BUILD_MPU1_0)
+    if (pgVersion == APP_TEST_AM65XX_PG1_0_VERSION)
+    {
+        instId = UDMA_INST_ID_MCU_0;
+    }
+    else
+    {
+        instId = UDMA_INST_ID_MAIN_0;
+    }
+#else
     instId = UDMA_INST_ID_MCU_0;
-    UdmaInitPrms_init(instId, &initPrms);
+#endif
 #else
+    /* icssg use case */
     instId = UDMA_INST_ID_MAIN_0;
+#endif
+#endif
+
+#if defined (SOC_J721E)
+#if defined (EMAC_TEST_APP_CPSW)
+#if defined (BUILD_MPU1_0)
+    instId = UDMA_INST_ID_MAIN_0;
+#elif defined (BUILD_MCU1_0)
+    instId = UDMA_INST_ID_MCU_0;
+#else
+    instId = UDMA_INST_ID_MAIN_0;
+#endif
+#else
+    /* icssg use case */
+    instId = UDMA_INST_ID_MAIN_0;
+#endif
+#endif
+
     UdmaInitPrms_init(instId, &initPrms);
 
     initPrms.rmInitPrms.numIrIntr = EMAC_MAX_PORTS*8;
@@ -1496,7 +1532,7 @@ void app_test_udma_init(void)
 
     initPrms.rmInitPrms.startFreeRing= 2;
     initPrms.rmInitPrms.numFreeRing = 300;
-#endif
+
     /* UDMA driver init */
     retVal = Udma_init(&gUdmaDrvObj, &initPrms);
     if(UDMA_SOK == retVal)
index cae93d3070cd7d9bb4742caf7f2320172cec3776..6f74ab2f6552e1e3e994fbe78f4e8b97d602c99b 100644 (file)
@@ -60,8 +60,6 @@ extern "C" {
 
 #if defined (SOC_AM65XX)
 #include <ti/csl/src/ip/intr_router/V0/csl_intr_router.h>
-#include <ti/csl/src/ip/fss/V0/cslr_fss.h>
-#include <ti/csl/src/ip/rat/V0/csl_rat.h>
 #include <ti/csl/soc/am65xx/src/cslr_soc_baseaddress.h>
 #include <ti/csl/soc/am65xx/src/cslr_mcu_ctrl_mmr.h>
 #include <ti/csl/soc/am65xx/src/cslr_mcu_pll_mmr.h>
@@ -70,8 +68,6 @@ extern "C" {
 
 #if defined (SOC_J721E)
 #include <ti/csl/src/ip/intr_router/V0/csl_intr_router.h>
-#include <ti/csl/src/ip/fss/V0/cslr_fss.h>
-#include <ti/csl/src/ip/rat/V0/csl_rat.h>
 #include <ti/csl/soc/j721e/src/cslr_soc_baseaddress.h>
 #include <ti/csl/soc/j721e/src/cslr_mcu_ctrl_mmr.h>
 #include <ti/csl/soc/j721e/src/cslr_mcu_pll_mmr.h>
index f89d71ab159b6ad924d7db2a09b759c7cababaaf..7da19f2a1129428bfdeea3e1be1f9308f1cb1cd9 100755 (executable)
 #include "I2C_log.h"
 #include "I2C_board.h"
 #ifdef SOC_AM65XX
-#include <ti/csl/src/ip/fss/V0/cslr_fss.h>
-#include <ti/csl/src/ip/rat/V0/csl_rat.h>
-#include <ti/csl/soc/am65xx/src/cslr_soc_baseaddress.h>
-#include <ti/csl/soc/am65xx/src/cslr_mcu_ctrl_mmr.h>
-#include <ti/csl/soc/am65xx/src/cslr_mcu_pll_mmr.h>
-#include <ti/csl/soc/am65xx/src/cslr_wkup_ctrl_mmr.h>
+#include <ti/csl/soc.h>
 #include <ti/drv/sciclient/sciclient.h>
 #endif
 
 #ifdef SOC_J721E
-#include <ti/csl/src/ip/fss/V0/cslr_fss.h>
-#include <ti/csl/src/ip/rat/V0/csl_rat.h>
 #include <ti/csl/soc.h>
 #if defined (BUILD_DSP_1) || defined (BUILD_DSP_2)
 #include <ti/csl/csl_chipAux.h>
index 2640837eeb7dbe852ad6509b933973b34f924da0..43e91fc2db073ac505bb00af227453a633f4c6b1 100644 (file)
@@ -117,7 +117,7 @@ typedef struct Ipc_InitPrms_s
      *   If NULL, the driver will assume a one-one mapping.
      *
      *   Note: The init fxn will initialize this to the default one-one map
-     *   function #Ipc_defaultPhyToVirtFxn
+     *   function Ipc_defaultPhyToVirtFxn
      */
     Ipc_VirtToPhyFxn        virtToPhyFxn;
     /**< If not NULL, this function will be called to convert virtual address
@@ -125,7 +125,7 @@ typedef struct Ipc_InitPrms_s
      *   If NULL, the driver will assume a one-one mapping.
      *
      *   Note: The init fxn will initialize this to the default one-one map
-     *   function #Ipc_defaultVirtToPhyFxn
+     *   function Ipc_defaultVirtToPhyFxn
      */
     Ipc_OsalPrms            osalPrms;
     /**< OSAL callback  parameters */
@@ -204,6 +204,9 @@ uint32_t RPMessage_getObjMemRequired(void);
  *  Can be called from Main or Task context.  Must be called before
  *  calling any other RPMessage function;
  *
+ *  \param params [IN] Address of the RPMessage_Params structure
+ *                used to create the RPMessage
+ *
  *  \return      #IPC_SOK or #IPC_EFAIL
  */
 int32_t RPMessage_init(RPMessage_Params *params);
@@ -215,6 +218,8 @@ int32_t RPMessage_init(RPMessage_Params *params);
  *  calling RPMessage_init. Must be called before any other RPMessage
  *  function to communicate with this proc;
  *
+ *  \param proc [IN] Remote Proc ID
+ *
  *  \return      #IPC_SOK or #IPC_EFAIL
  */
 int32_t RPMessage_lateInit(uint32_t proc);
@@ -336,7 +341,7 @@ int32_t RPMessage_recv(RPMessage_Handle handle, void* data, uint16_t *len,
  *  \ref RPMessage_send
  */
 int32_t RPMessage_recvNb(RPMessage_Handle handle, void* data, uint16_t *len,
-                   uint32_t *rplyEndPt, uint32_t *rplyProcId);
+                   uint32_t *rplyEndPt, uint32_t *fromProcId);
 
 /**
  *  \brief Sends data to a remote processor.
@@ -455,7 +460,7 @@ int32_t RPMessage_announce(uint32_t remoteProcId, uint32_t endPt,
  *  It's expected that user of this driver shall invoke this function, on
  *  reception of interrupt from the mailbox associated with remote processor
  *
- *  \param remoteProcId    [IN] The remote processor ID
+ *  \param srcProcId    [IN] The remote processor ID
  *
  *  \return     - None
  *
@@ -466,8 +471,8 @@ void Ipc_newMessageIsr(uint32_t srcProcId);
  *
  *  \warning To be used only when built for baremetal
  *
- *  \param  uint16_t    Remote Processor Identifier
- *  \param  uint16_t    Own Proc ID
+ *  \param  selfId    Self Processor Identifier
+ *  \param  remoteProcId Remote Processor ID
  *
  *  \return None
  */
@@ -477,8 +482,8 @@ void Ipc_mailboxEnableNewMsgInt(uint16_t selfId, uint16_t remoteProcId);
  *
  *  \warning To be used only when built for baremetal
  *
- *  \param  uint16_t    Remote Processor Identifier
- *  \param  uint16_t    Own Proc ID
+ *  \param  selfId    Self Processor Identifier
+ *  \param  remoteProcId    Remote Processor ID
  *
  *  \return None
  */
index 9dca9644fac5bc243b0c3327282e99fbe9e8b2b3..bdb04f289e79eade29061977aec58a45edf6dd4f 100644 (file)
@@ -399,3 +399,20 @@ int32_t Ipc_sciclientIrqSet(uint16_t coreId, uint32_t clusterId,
 }
 
 #endif
+
+uint32_t Ipc_getCoreId(void)
+{
+    uint32_t selfId =  IPC_INVALID_PROCID;
+
+#if defined(BUILD_MPU1_0)
+    selfId = IPC_MPU1_0;
+#elif defined(BUILD_MCU1_0)
+    selfId = IPC_MCU1_0;
+#elif defined(BUILD_MCU1_1)
+    selfId = IPC_MCU1_1;
+#else
+#error "Unsupported core Id"
+#endif
+
+    return (selfId);
+}
index 42deb30dd9ac1529cb537a1da089527f37b24cae..5ed5c78cc5c8e58c21b3f0e302df9f3d7c60c71c 100644 (file)
@@ -421,7 +421,7 @@ int32_t Ipc_getMailboxIntrRouterCfg(uint32_t selfId, uint32_t clusterId,
 
 const char* Ipc_getCoreName(uint32_t procId)
 {
-    char*     p = (void*)0;
+    char*     p = (char*)0;
     uint32_t id = procId;
 
     if(id < IPC_MAX_PROCS)
@@ -610,3 +610,34 @@ int32_t Ipc_sciclientIrqSet(uint16_t coreId, uint32_t clusterId,
 }
 
 #endif
+
+uint32_t Ipc_getCoreId(void)
+{
+    uint32_t selfId =  IPC_INVALID_PROCID;
+
+#if defined(BUILD_MPU1_0)
+    selfId = IPC_MPU1_0;
+#elif defined(BUILD_MCU1_0)
+    selfId = IPC_MCU1_0;
+#elif defined(BUILD_MCU1_1)
+    selfId = IPC_MCU1_1;
+#elif defined(BUILD_MCU2_0)
+    selfId = IPC_MCU2_0;
+#elif defined(BUILD_MCU2_1)
+    selfId = IPC_MCU2_1;
+#elif defined(BUILD_MCU3_0)
+    selfId = IPC_MCU3_0;
+#elif defined(BUILD_MCU3_1)
+    selfId = IPC_MCU3_1;
+#elif defined(BUILD_C66X_1)
+    selfId = IPC_C66X_1;
+#elif defined(BUILD_C66X_2)
+    selfId = IPC_C66X_2;
+#elif defined(BUILD_C7X_1)
+    selfId = IPC_C7X_1;
+#else
+#error "Unsupported core Id"
+#endif
+
+    return (selfId);
+}
index 0dcfb91ec72fc4d8b377245e4419f003dea70751..fc7a46f13c8e56289a7a07830f0845b359ce9dc9 100644 (file)
@@ -44,6 +44,8 @@
 extern "C" {
 #endif
 
+#define    IPC_INVALID_PROCID (0XFFU)   /**< Invalid Proc ID */
+
 /* ========================================================================== */
 /*                             Include Files                                  */
 /* ========================================================================== */
@@ -68,8 +70,24 @@ int32_t Ipc_getMailboxInfoRx(uint32_t selfId, uint32_t remoteId,
 int32_t Ipc_getMailboxIntrRouterCfg(uint32_t selfId, uint32_t clusterId,
                  uint32_t userId, Ipc_MbConfig* cfg, uint32_t cnt);
 uint32_t Ipc_getMailboxBaseAddr(uint32_t custerId);
+
+/**
+ * \brief Returns the core name for get core id
+ *
+ * \param procId [IN] Id of desired core.
+ *
+ * \return name of the given core id
+ * */
 const char* Ipc_getCoreName(uint32_t procId);
 
+/**
+ * \brief Returns Core ID based on core build flag
+ *
+ * \return Code ID of the current core
+ **/
+uint32_t Ipc_getCoreId(void);
+
+
 /* For Maxwell Device */
 #if defined (SOC_AM65XX)
 #include <ti/drv/ipc/soc/V0/ipc_soc.h>
index b9de032bc49651cf39f960316b28c5d061e4948e..a0df7837db3f92378fbd6f11d096e3f6984996de 100755 (executable)
@@ -64,7 +64,8 @@
 #define SERVICENAMELEN         32U
 #define HEAPALIGNMENT          8U
 
-typedef struct RPMessage_Object*            RPMessage_EndptPool[MAXENDPOINTS];
+struct RPMessage_Object_s;
+typedef struct RPMessage_Object_s*            RPMessage_EndptPool[MAXENDPOINTS];
 
 /* ========================================================================== */
 /*                         Structure Declarations                             */
index 61ed1f7abd65b7ef84771ffd7477a7bd500d8fed..5331ede59db55057cd86d7a34d31376ffc421d04 100644 (file)
@@ -38,8 +38,8 @@
 #include <ti/csl/soc.h>
 
 /* IEP0/1 HW register base addresses */
-#define ICSS_IEP0_CFG_BASE  ( CSL_ICSS_IEP_CFG_BASE )
-#define ICSS_IEP1_CFG_BASE  ( ICSS_IEP0_CFG_BASE + CSL_ICSS_IEP_CFG_SIZE )
+#define ICSS_IEP0_CFG_BASE  ( CSL_ICSS_IEP0_CFG_BASE )
+#define ICSS_IEP1_CFG_BASE  ( CSL_ICSS_IEP1_CFG_BASE )
 
 /* PWM trip reset event mask */
 #define PWM_TRIP_RESET_MASK ( CSL_ICSSCFG_PWM0_PWM0_TRIP_RESET_MASK )
index 7470a4d15506653768da919a86968ab5cf19f02d..c6dfd155f2c69ea79a99cb1b0d8c1a042e1f5eaf 100644 (file)
@@ -33,7 +33,7 @@
 include $(PDK_INSTALL_PATH)/ti/build/Rules.make
 
 MODULE_NAME = nimu
-CFLAGS_LOCAL_COMMON =
+CFLAGS_LOCAL_COMMON = -DNDK_NOUSERAPIS
 
 ifeq ($(SOC),$(filter $(SOC), am571x am572x am574x am437x am335x dra72x dra75x dra78x))
 include $(PDK_NIMU_COMP_PATH)/src/v4/src_files_v4.mk
index a4b13a20275384ac4c4dd5017658901b50fc5bb7..131d25c884e66868e998998b77539a7e03d3960d 100644 (file)
@@ -33,7 +33,7 @@
 include $(PDK_INSTALL_PATH)/ti/build/Rules.make
 
 MODULE_NAME = nimu_profile
-CFLAGS_LOCAL_COMMON =
+CFLAGS_LOCAL_COMMON = -DNDK_NOUSERAPIS
 
 ifeq ($(SOC),$(filter $(SOC), am571x am572x am574x am437x am335x dra72x dra72x dra75x dra78x))
 include $(PDK_NIMU_COMP_PATH)/src/v4/src_files_v4.mk
index 5f85f9a7e04d8fded73f4fc4a38cfb40dc80c53d..42e7c9cdb57011e7d50c2b4082d0ba241c0b964a 100644 (file)
@@ -112,6 +112,10 @@ char *DNSServer   = "0.0.0.0";          // Used when set to anything but zero
 \r
 Uint8 clientMACAddress [6] = {0xd4, 0xbe, 0xd9, 0x3d, 0xb6, 0xb8}; /* MAC address for my PC */\r
 \r
+void System_flush(void)\r
+{\r
+    fflush(stdout);\r
+}\r
 \r
 //---------------------------------------------------------------------\r
 // Main Entry Point\r
index dee25d041c6a1e2a88cd75b965acf8579151ed86..201360c1615db97951532ded69603a5d0d788c08 100644 (file)
@@ -38,11 +38,6 @@ endif
 
 COMP = drvnimu
 
-# Temporary override since this component has known warnings for listed SOCS
-ifeq ($(SOC),$(filter $(SOC), dra72x dra75x am574x am572x am571x k2h k2k k2l k2e k2g am437x am335x dra78x omapl137 omapl138 ))
-override TREAT_WARNINGS_AS_ERROR=no
-export TREAT_WARNINGS_AS_ERROR
-endif
 lib_$(COMP)_BUILD_DEPENDENCY = soc
 
 $(COMP)_DOXYGEN_SUPPORT = no
index 90279b1a074bc273c00d84802c5497f412a33f18..9ba0342ee020ea204a7d55ad6bf8d52ff6c026c8 100644 (file)
@@ -11,7 +11,7 @@ extern "C" {
  *
  *   path  ti/transport/ndk/nimu/nimu_ver.h
  *
- *   @brief  nimu for CPSW transport Version Definitions
+ *   @brief  nimu Driver Version Definitions
  *
  *  ============================================================
  *  Copyright (c) Texas Instruments Incorporated 2015-2019
@@ -47,17 +47,17 @@ extern "C" {
 */
 
 /**
- * @brief   This is the nimu Transport Version. Versions numbers are encoded in the following 
+ * @brief   This is the nimu Driver Version. Versions numbers are encoded in the following 
  * format:
  *  0xAABBCCDD -> Arch (AA); API Changes (BB); Major (CC); Minor (DD)
  */
 #define NIMU_TRANSPORT_VERSION_ID                     (0x01000011)
 
 /**
- * @brief   This is the version string which describes the nimu transport along with the
+ * @brief   This is the version string which describes the nimu driver along with the
  * date and build information.
  */
-#define NIMU_TRANSPORT_VERSION_STR                    "nimu tranport Revision: 01.00.00.17"
+#define NIMU_TRANSPORT_VERSION_STR                    "nimu Driver Revision: 01.00.00.17"
 
 
 #ifdef __cplusplus
index 26aa48b2037de565fe9dc7fdd39f479b2910fbb3..61dfeab28961a3e171a5de360db94fcce654d50e 100644 (file)
@@ -46,7 +46,6 @@
 extern "C" {
 #endif
 
-#include <stdio.h>
 
 /**********************************************************************
  ************************** Global Variables **************************
index 633023e8e249ab96d964fc9c74ee5eb7a0ab102a..e243e76a3da6804230fee59a8651997158c7ec85 100644 (file)
  *
  */
 
-#include <stdio.h> /* to use printf */
-#include <stdint.h>
-
-
-
-
-
 #include <ti/csl/csl_chip.h>
 #include <ti/csl/csl_semAux.h>
 #include <ti/csl/csl_bootcfgAux.h>
@@ -140,12 +133,6 @@ void CycleDelay (int32_t iCount)
 #endif
 }
 
-void System_flush(void)
-{
-    fflush(stdout);
-}
-
-
 int32_t  NIMU_getEmacInfo(uint32_t port_num, NIMU_EMAC_EXT_info * emac_info)
 {
     uint32_t mac_addr2, mac_addr1;
@@ -166,8 +153,6 @@ int32_t  NIMU_getEmacInfo(uint32_t port_num, NIMU_EMAC_EXT_info * emac_info)
 
 }
 
-
-
 int32_t
 NIMU_qmssQPop
 (
@@ -2127,9 +2112,13 @@ void Init_SGMII (uint32_t macPortNum)
 
     /* Reset the port before configuring it */
     CSL_SGMII_doSoftReset (macPortNum);
-    while (CSL_SGMII_getSoftResetStatus (macPortNum) != 0);
+    while (CSL_SGMII_getSoftResetStatus (macPortNum) != 0)
+    {
+        CycleDelay(1);
+    }
 
-     if (macPortNum < 2) {
+     if (macPortNum < 2) 
+     {
         /* Hold the port in soft reset and set up
          * the SGMII control register:
          *      (1) Enable Master Mode
@@ -2147,6 +2136,7 @@ void Init_SGMII (uint32_t macPortNum)
          */
         sgmiiCfg.linkSpeed      =   CSL_SGMII_1000_MBPS;
         sgmiiCfg.duplexMode     =   CSL_SGMII_FULL_DUPLEX;
+        sgmiiCfg.bLinkUp        =   1;
         CSL_SGMII_setAdvAbility (macPortNum, &sgmiiCfg);
 
         do
index a1d6c8eaa0f50e0e7fa3676d2396f34035de59af..ebea6b1330b73ea31d7a2446b9ec8666e81870e2 100644 (file)
  *
  */
 
-#include <stdio.h> /* to use printf */
-#include <stdint.h>
-
-
-
-
-
 #include <ti/csl/csl_chip.h>
 #include <ti/csl/csl_semAux.h>
 #include <ti/csl/csl_bootcfgAux.h>
@@ -145,10 +138,6 @@ void CycleDelay (int32_t iCount)
 #endif
 }
 
-void System_flush(void)
-{
-    fflush(stdout);
-}
 int32_t  NIMU_getEmacInfo(uint32_t port_num, NIMU_EMAC_EXT_info * emac_info)
 {
     uint32_t mac_addr2, mac_addr1;
@@ -2211,9 +2200,13 @@ void Init_SGMII (uint32_t macPortNum)
 
     /* Reset the port before configuring it */
     CSL_SGMII_doSoftReset (macPortNum);
-    while (CSL_SGMII_getSoftResetStatus (macPortNum) != 0);
+    while (CSL_SGMII_getSoftResetStatus (macPortNum) != 0)
+    {
+        CycleDelay(1);
+    }
 
-     if (macPortNum < 2) {
+     if (macPortNum < 2) 
+     {
         /* Hold the port in soft reset and set up
          * the SGMII control register:
          *      (1) Enable Master Mode
@@ -2230,6 +2223,7 @@ void Init_SGMII (uint32_t macPortNum)
          */
         sgmiiCfg.linkSpeed      =   CSL_SGMII_1000_MBPS;
         sgmiiCfg.duplexMode     =   CSL_SGMII_FULL_DUPLEX;
+        sgmiiCfg.bLinkUp        =   1;
         CSL_SGMII_setAdvAbility (macPortNum, &sgmiiCfg);
 
         CSL_SGMII_enableAutoNegotiation (macPortNum);
index 28e6956233113b40ae83490e1b27872b484cfe0b..e618ab30cbcac983ee996d4a1cab809b1eab6194 100644 (file)
  *
  */
 
-#include <stdio.h> /* to use printf */
-#include <stdint.h>
-
-
-
-
-
 #include <ti/csl/csl_chip.h>
 #include <ti/csl/csl_semAux.h>
 #include <ti/csl/csl_bootcfgAux.h>
@@ -155,12 +148,6 @@ void CycleDelay (int32_t iCount)
 #endif
 }
 
-void System_flush(void)
-{
-    fflush(stdout);
-}
-
-
 void nimu_task_poll_link(unsigned int* arg0, unsigned int* arg1)
 {
 
@@ -789,7 +776,7 @@ nimu_alloc_pkt
     Uint32              pkt_size
 )
 {
-    PBM_Handle pbmHandle;
+    PBM_Handle pbmHandle = NULL;
     EMAC_PKT_DESC_T*    p_pkt_desc = NULL;
      uint8_t* bufferPtr;
 
index c02de91f307455275ea6b9853cb25e402c95c399..b972982a481f7e9236a892329f4189d914592821 100644 (file)
@@ -45,7 +45,6 @@
 #ifndef _NIMU_INTERNAL_H_
 #define _NIMU_INTERNAL_H_
 
-//#include <ti/csl/tistdtypes.h>
 #include <ti/ndk/inc/stkmain.h>
 
 /* CSL EMAC include */
index 4d12dc99c1cda0fd63d39edf81440ae19fe9c278..21e9f5f0b2876a5f9ce1998c393f3b26e469c66b 100644 (file)
@@ -35,7 +35,7 @@
  *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  */
-
+#include <string.h>
 #include <ti/csl/soc.h>
 #include <ti/csl/hw_types.h>
 
@@ -79,6 +79,7 @@ extern void Osal_free(void*       ptr, uint32_t      num_bytes);
 extern void Osal_TaskSleep(uint32_t sleepTime);
 
 #define NIMU_CPSW_PORT_NUM ((uint32_t)6U)
+#define NIMU_PORT_NAME_LEN ((uint32_t)5U)
 
 #define     NIMU_PKT_MTU_DEFAULT             1518
 
@@ -489,12 +490,13 @@ int32_t NimuEmacInit(uint32_t portNum, STKEVENT_Handle hEvent)
 {
     int32_t retVal = 0;
     NIMU_EMAC_DATA*      ptr_pvt_data;
+    char names[NIMU_CPSW_PORT_NUM][NIMU_PORT_NAME_LEN]={"eth0","eth1","eth2","eth3","eth4","eth5"};
 
     /* memset netif device struct */
     mmZeroInit((void*)(&ptr_device[portNum]), sizeof(NETIF_DEVICE));
 
     /* Allocate memory for the private data */
-    ptr_pvt_data = mmAlloc(sizeof(NIMU_EMAC_DATA));
+    ptr_pvt_data = (NIMU_EMAC_DATA*)(mmAlloc(sizeof(NIMU_EMAC_DATA)));
     if (ptr_pvt_data == NULL)
     {
         NIMU_drv_log ("Error: Unable to allocate private memory data\n");
@@ -515,8 +517,7 @@ int32_t NimuEmacInit(uint32_t portNum, STKEVENT_Handle hEvent)
         /* MCast List is EMPTY */
         ptr_pvt_data->pdi.mCastCnt    = 0;
         ptr_pvt_data->pdi.portNum = portNum;
-        sprintf(ptr_device[portNum].name,"eth%d\n", portNum);
-
+        strcpy(ptr_device[portNum].name, names[portNum]);
         ptr_device[portNum].mtu         = ETH_MAX_PAYLOAD - ETHHDR_SIZE;
         ptr_device[portNum].pvt_data    = (void *)ptr_pvt_data;
     
index cb2e2203b963e5dc2f74206e1461ce3ebbf708d0..b8dda5bd908b3d104c25a188834a5473872577f0 100644 (file)
@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2016, Texas Instruments Incorporated
+# Copyright (c) 2016-2019, Texas Instruments Incorporated
 # All rights reserved.
 #
 # Redistribution and use in source and binary forms, with or without
@@ -39,7 +39,7 @@ MODULE_NAME = nimu_icss_indp
 #  need to be included for this component
 INCLUDE_EXTERNAL_INTERFACES = xdc pdk ndk bios
 
-CFLAGS_LOCAL_COMMON = $(PDK_CFLAGS)
+CFLAGS_LOCAL_COMMON = $(PDK_CFLAGS) -DNDK_NOUSERAPIS
 
 # Include common make files
 ifeq ($(MAKERULEDIR), )
index 69ce8180c189c971eb4ca1d091b0b68fc4eb4f47..8ba94071892486f41cc8744d65833ce7923467b8 100644 (file)
@@ -1,5 +1,5 @@
 #
-# Copyright (c) 2016, Texas Instruments Incorporated
+# Copyright (c) 2016-2019, Texas Instruments Incorporated
 # All rights reserved.
 #
 # Redistribution and use in source and binary forms, with or without
@@ -35,15 +35,16 @@ include $(PDK_NIMU_ICSS_COMP_PATH)/src/src_files_common.mk
 
 MODULE_NAME = nimu_icss_profile_indp
 
+CFLAGS_LOCAL_COMMON = $(PDK_CFLAGS) -DNDK_NOUSERAPIS 
 # List all the external components/interfaces, whose interface header files
 #  need to be included for this component
 INCLUDE_EXTERNAL_INTERFACES = xdc pdk ndk bios
 
 ifeq ($(BUILDTYPE),$(filter $(BUILDTYPE), profile profiledma))
   ifeq ($(CORE),$(filter $(CORE), a15_0 a9host a8host))
-    CFLAGS_LOCAL_COMMON = $(PDK_CFLAGS) -finstrument-functions -gdwarf-3 -g -D_ENABLE_BM
+    CFLAGS_LOCAL_COMMON += -finstrument-functions -gdwarf-3 -g -D_ENABLE_BM
   else
-    CFLAGS_LOCAL_COMMON = $(PDK_CFLAGS) --entry_parm=address --exit_hook=ti_utils_exit --exit_parm=address --entry_hook=ti_utils_entry -g -D_ENABLE_BM
+    CFLAGS_LOCAL_COMMON += --entry_parm=address --exit_hook=ti_utils_exit --exit_parm=address --entry_hook=ti_utils_entry -g -D_ENABLE_BM
   endif
 endif
 
index 72a345c4a767bf05c10beece277851e3c26598c9..b8384fcb6c6898e1dd67319a7383d5754a59cef6 100644 (file)
@@ -58,7 +58,6 @@ M4LE.ccOpts.prefix  = "-o4 -qq -pdsw255 -DMAKEFILE_BUILD";
 var A9LE            = xdc.useModule('gnu.targets.arm.A9F');\r
 A9LE.rootDir        = a9ToolsBaseDir;\r
 A9LE.ccOpts.prefix  = "-mno-unaligned-access -c -mtune=cortex-a9 -marm -g -gstrict-dwarf -Wall -D__ARMv7 -D_LITTLE_ENDIAN=1";\r
-/* A9LE.ccOpts.prefix  = "-c -mcpu=cortex-a9 -mtune=cortex-a9 -march=armv7-a -mfpu=neon -mfloat-abi=hard -eo.$(OBJEXT) -ea.$(ASMEXT) -mlong-calls -fdata-sections -funsigned-char -ffunction-sections -Wall -Dgcc -Darmv7a -D_LITTLE_ENDIAN=1 -D SUPPORT_UNALIGNED -MD -MF $(DEPFILE).P "; */\r
 \r
 /* ARMv7 A8 compiler configuration */\r
 var A8LE            = xdc.useModule('gnu.targets.arm.A8F');\r
index f15ab4545a5a8e71876ae5719f01982b2742368a..fbddd45e75d0e7d3fefdf5178b76c3aa2642b89d 100644 (file)
@@ -38,9 +38,6 @@ endif
 
 COMP = drvnimu_icss
 
-override TREAT_WARNINGS_AS_ERROR=no
-export TREAT_WARNINGS_AS_ERROR
-
 lib_$(COMP)_BUILD_DEPENDENCY = soc
 
 $(COMP)_DOXYGEN_SUPPORT = no
index eb697d15f185a17fdae1546e6dba56cb15d2a757..04ff3a073f0e3452ea70387dff9ac51d2f880014 100644 (file)
@@ -41,7 +41,6 @@
 \r
 #include <stdint.h>\r
 #include "ti/ndk/inc/stkmain.h"\r
-#include "ti/ndk/inc/os/osif.h"\r
 #include "ti/drv/icss_emac/icss_emacDrv.h"\r
 \r
 #ifdef __cplusplus\r
@@ -91,7 +90,7 @@ typedef struct NIMU_IcssPdInfo_s
 \r
     uint32_t            PhysIdx;      /**< Physical index of this device (0 to n-1) */\r
     void*          hEther;       /**< Handle to logical driver */\r
-    STKEVENT_Handle hEvent;            /**< Semaphore handle used by NDK stack and driver to communicate any\r
+    void* hEvent;            /**< Semaphore handle used by NDK stack and driver to communicate any\r
                                          pending Rx events that need to be serviced by NDK ethernet stack */\r
     uint8_t           bMacAddr[6U];    /**< MAC Address*/\r
     uint32_t            Filter;            /**< Current RX filter */\r
index f73bb2608ba8a123ac53fdd8bfcfc1b89e0da157..d4b45cfac71bf3530440f51d14b4d110b4fefb20 100644 (file)
@@ -41,7 +41,6 @@
 /* ========================================================================== */
 /*                             Include Files                                  */
 /* ========================================================================== */
-#include <stdio.h>
 #include "ti/transport/ndk/nimu_icss/nimu_icssEth.h"
 #include "ti/transport/ndk/nimu_icss/src/nimu_icssEthDriver.h"
 #include "ti/drv/icss_emac/icss_emacFwInit.h"
index d3586c4d4db499e0931e647d4948b8976128a733..75c6f33ae693a00ab9dd948194ad53fc1d721322 100644 (file)
 #include "ti/drv/icss_emac/icss_emacStormControl.h"
 #include "ti/transport/ndk/nimu_icss/nimu_icssEth.h"
 
-#include <ti/ndk/inc/stkmain.h>
-#include <ti/ndk/inc/os/osif.h>
-
-
 /* ========================================================================== */
 /*                            Global Variables                                */
 /* ========================================================================== */
index 6defed375ff387e9316b92d844b6efaf5b2f77c6..55e8c52bf51440d4f54e4661160cabd3e811ac29 100644 (file)
@@ -102,8 +102,12 @@ utilsProfilingElem elemlog[MAX_LOG] = {{0}};
  *  used by the instrumentation functions themselves. This is recorded and
  *  passed into post-processing for a more accurate result.
  */
-#pragma FUNC_CANNOT_INLINE(empty_fn);
 void empty_fn(void); /*for misra warnings*/
+#ifdef __cplusplus
+#pragma FUNC_CANNOT_INLINE
+#else
+#pragma FUNC_CANNOT_INLINE(empty_fn);
+#endif
 void empty_fn(void){
 }
 
@@ -178,8 +182,12 @@ void ti_utils_exit(void (* func_addr)(void)){
     }
 }
 
-#pragma NO_HOOKS (TaskRegisterId)
 void TaskRegisterId(int32_t hookSetId); /*for misra warnings*/
+#ifdef __cplusplus
+#pragma NO_HOOKS
+#else
+#pragma NO_HOOKS(TaskRegisterId);
+#endif
 void TaskRegisterId(int32_t hookSetId)
 {
        CurrentTaskHookSetId = hookSetId;
@@ -191,8 +199,12 @@ void TaskRegisterId(int32_t hookSetId)
 
 /* ======== mySwitch ========
 * invoked whenever a Task switch occurs/is made ready to run */
-#pragma NO_HOOKS (mySwitch)
 void mySwitch(const void* prev, const void* next); /*for misra warnings*/
+#ifdef __cplusplus
+#pragma NO_HOOKS
+#else
+#pragma NO_HOOKS(mySwitch);
+#endif
 void mySwitch(const void* prev, const void* next)
 {
     if (log_idx < MAX_LOG){