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| author | Jacob Stiffler <j-stiffler@ti.com> | |
| Fri, 1 Nov 2019 18:54:11 +0000 (14:54 -0400) | ||
| committer | Jacob Stiffler <j-stiffler@ti.com> | |
| Fri, 1 Nov 2019 18:54:11 +0000 (14:54 -0400) |
Development of processor-pdk-build has been relocated here from:
* Repo: https://git.ti.com/keystone-rtos/processor-pdk-build
* Branch: master
* Commit ID: ace03765311d61234e86f6ba04912ab808d37d30
Signed-off-by: Jacob Stiffler <j-stiffler@ti.com>
* Repo: https://git.ti.com/keystone-rtos/processor-pdk-build
* Branch: master
* Commit ID: ace03765311d61234e86f6ba04912ab808d37d30
Signed-off-by: Jacob Stiffler <j-stiffler@ti.com>
140 files changed:
diff --git a/packages/ti/build/COPYING.txt b/packages/ti/build/COPYING.txt
--- /dev/null
@@ -0,0 +1,31 @@
+#
+# Copyright (c) 2013-present, Texas Instruments Incorporated
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# * Redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer.
+#
+# * Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution.
+#
+# * Neither the name of Texas Instruments Incorporated nor the names of
+# its contributors may be used to endorse or promote products derived
+# from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+# OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+# EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
diff --git a/packages/ti/build/Rules.make b/packages/ti/build/Rules.make
--- /dev/null
@@ -0,0 +1,341 @@
+#
+# Copyright (c) 2013-2018, Texas Instruments Incorporated
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# * Redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer.
+#
+# * Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution.
+#
+# * Neither the name of Texas Instruments Incorporated nor the names of
+# its contributors may be used to endorse or promote products derived
+# from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+# OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+# EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+
+#Default build environment, (Windows_NT / linux)
+#if nothing is defined, default to linux as in windows this variable is defined
+export OS ?= linux
+
+SDK_INSTALL_PATH ?= $(abspath ../../../../)
+TOOLS_INSTALL_PATH ?= $(SDK_INSTALL_PATH)
+
+#Default BUILD_OS_TYPE (tirtos/baremetal/qnx)
+export BUILD_OS_TYPE ?= tirtos
+
+# Default board
+# Supported values are printed in "make -s help" option. Below are the list for reference.
+# evmDRA72x, evmDRA75x, evmDRA78x,
+# evmAM572x, idkAM571x, idkAM572x idkAM574x
+# evmK2H, evmK2K, evmK2E, evmK2L, evmK2G, evmC6678, evmC6657,
+# evmAM335x, icev2AM335x, iceAMIC110, skAM335x, bbbAM335x,
+# evmAM437x idkAM437x skAM437x evmOMAPL137 lcdkOMAPL138
+# And also refer $(BOARD_LIST_J6_TDA) below
+#
+ifeq ($(LIMIT_BOARDS),)
+ # TDA parts do not define this environment variable, default board and soc for TDA parts
+ export BOARD ?= j721e_evm
+ export SOC ?= j721e
+else
+ifeq ($(LIMIT_BOARDS), j721e_evm)
+ export BOARD = j721e_evm
+ export SOC = j721e
+else
+ifeq ($(LIMIT_BOARDS), j721e_sim)
+ export BOARD = j721e_sim
+ export SOC = j721e
+else
+ # default board and soc for Catalog parts
+ export BOARD ?= idkAM572x
+ export SOC ?= am572x
+endif
+endif
+endif
+################################################################################
+# Other user configurable variables
+################################################################################
+
+# Default to m4 build depending on BOARD selected!!
+ifeq ($(BOARD),$(filter $(BOARD), evmAM572x idkAM572x idkAM571x idkAM574x))
+ CORE ?= a15_0
+endif
+ifeq ($(BOARD),$(filter $(BOARD), am65xx_sim am65xx_evm am65xx_idk j721e_sim j721e_vhwazebu j721e_qt j721e_evm j7200_evm j7200_sim am64x_evm))
+ CORE ?= mcu1_0
+endif
+ifeq ($(BOARD),$(filter $(BOARD), j721e_ccqt j721e_loki))
+ CORE ?= c7x_1
+endif
+ifeq ($(BOARD),$(filter $(BOARD), j721e_hostemu j7200_hostemu))
+ CORE = c7x-hostemu
+endif
+CORE ?= ipu1_0
+export CORE
+
+# Default Build Profile
+# Supported Values: debug | release
+export BUILD_PROFILE ?= release
+
+# Treat compiler warning as error
+# Supported Values: yes | no
+export TREAT_WARNINGS_AS_ERROR ?= yes
+
+#Various boards support for J6 TDA family of devices
+BOARD_LIST_J6_TDA = tda2xx-evm tda2ex-evm tda3xx-evm tda2px-evm
+BOARD_LIST_J6_TDA += tda2xx-evm-radar tda2px-evm-radar tda3xx-evm-radar
+BOARD_LIST_J6_TDA += tda3xx-ar12-booster tda3xx-ar12-alps tda3xx-ar12-rvp
+BOARD_LIST_J6_TDA += tda2ex-eth-srv tda2xx-rvp tda3xx-rvp
+BOARD_LIST_J6_TDA += tda2xx-cascade-radar
+export BOARD_LIST_J6_TDA
+
+#Various boards support for J7 TDA family of devices
+BOARD_LIST_J7_TDA = j721e_sim j721e_hostemu j721e_ccqt j721e_loki j721e_qt j721e_vhwazebu j721e_evm
+BOARD_LIST_J7_TDA += j7200_sim j7200_hostemu j7200_evm am64x_evm
+export BOARD_LIST_J7_TDA
+
+################################################################################
+# Configure toolchain paths
+################################################################################
+ifeq ($(BOARD),$(filter $(BOARD), $(BOARD_LIST_J6_TDA)))
+ # This section applies to J6 TDA SOCs in Processor SDK VISION release.
+ # For remaining SOC/BOARDS skip to the else part.
+ # SoC & Version of PDK for TDA builds
+ PDK_SOC=
+ PDK_VERSION=01_09_00_00
+
+ #Tool versions for TDA builds
+ GCC_CROSS_TOOL_PREFIX=arm-none-eabi-
+ GCC_CROSS_TOOL_TAG=4_9-2015q3
+ CGT_VERSION=7.4.2
+ GCC_VERSION_FPULIB=4.9.3
+ CGT_ARM_VERSION=16.9.2.LTS
+ CGT_ARP32_VERSION=1.0.7
+
+ #Component versions for TDA builds
+ BIOS_VERSION=6_46_04_53
+ EDMA_VERSION=02_12_00_20
+ XDC_VERSION=3_32_01_22_core
+ MSHIELD_VERSION=4_5_3
+ export mmwavelink_version=mmwave_dfp_01_01_00_00
+
+ export GCC_FLOAT_PATH ?= FPU
+else
+ # This section applies to all broader set of boards with SOCs beyond TDA class
+ # in Processor SDK RTOS release
+ PDK_VERSION_STR=_$(PDK_SOC)_$(PDK_VERSION)
+ifeq ($(PDK_VERSION),)
+ PDK_VERSION_STR=
+endif
+
+ #Tool versions for non-TDA builds
+ GCC_CROSS_TOOL_PREFIX=arm-none-eabi-
+ GCC_CROSS_TOOL_TAG=7-2018-q2-update
+ GCC_ARCH64_VERSION=7.2.1-2017.11
+ CGT_VERSION=8.3.2
+
+ CGT_C7X_VERSION=1.2.0.STS
+ CGT_ARM_VERSION=18.12.1.LTS
+ GCC_VERSION_HARDLIB=7.3.1
+
+ CGT_ARP32_VERSION=1.0.8
+ CG_XML_VERSION=2.61.00
+
+ #Component versions for non-TDA builds
+ BIOS_VERSION=6_76_02_02
+ XDC_VERSION=3_55_02_22_core
+
+ifeq ($(BOARD),$(filter $(BOARD), $(BOARD_LIST_J7_TDA)))
+ BIOS_VERSION=6_76_03_01
+endif
+
+ EDMA_VERSION=2_12_05_30E
+ SECDEV_VERSION=01_06_00_05
+ CGT_PRU_VERSION=2.3.2
+
+ #Hardcode IPC version if it is not set already
+ IPC_VERSION ?= 3_47_01_00
+ NDK_VERSION=3_61_01_01
+ NS_VERSION=2_60_01_06
+
+ UIA_VERSION=2_30_01_02
+ XDAIS_VERSION=7_24_00_04
+ AER_VERSION=17_0_0_0
+
+ # C674x DSP libraries sould be used for OMAPL13x platform
+ifeq ($(SOC),$(filter $(SOC), omapl137 omapl138))
+ DSPLIB_VERSION ?= c674x_3_4_0_3
+ IMGLIB_VERSION ?= c674x_3_1_1_0
+ MATHLIB_VERSION ?= c674x_3_1_2_3
+else
+ DSPLIB_VERSION ?= c66x_3_4_0_3
+ IMGLIB_VERSION ?= c66x_3_1_1_0
+ MATHLIB_VERSION ?= c66x_3_1_2_3
+endif
+
+ export GCC_FLOAT_PATH ?= HARD
+endif
+
+################################################################################
+# Dependent toolchain paths variables
+################################################################################
+# Version of GCC
+GCC_VERSION=$(GCC_CROSS_TOOL_PREFIX)$(GCC_CROSS_TOOL_TAG)
+GCC_VERSION_ARM_A15=$(GCC_CROSS_TOOL_PREFIX)$(GCC_CROSS_TOOL_TAG)
+ifeq ($(BOARD),$(filter $(BOARD), $(BOARD_LIST_J6_TDA)))
+ # This section applies to J6 TDA SOCs in Processor SDK VISION release.
+ # For remaining SOC/BOARDS skip to the else part.
+ ifeq ($(OS),Windows_NT)
+ OS_FOLDER=windows
+ else
+ OS_FOLDER=linux
+ endif
+ export TOOLCHAIN_PATH_GCC ?= $(SDK_INSTALL_PATH)/ti_components/cg_tools/$(OS_FOLDER)/gcc-$(GCC_VERSION)
+ export TOOLCHAIN_PATH_A15 ?= $(SDK_INSTALL_PATH)/ti_components/cg_tools/$(OS_FOLDER)/gcc-$(GCC_VERSION_ARM_A15)
+ export TOOLCHAIN_PATH_M4 ?= $(SDK_INSTALL_PATH)/ti_components/cg_tools/$(OS_FOLDER)/ti-cgt-arm_$(CGT_ARM_VERSION)
+ export C6X_GEN_INSTALL_PATH ?= $(SDK_INSTALL_PATH)/ti_components/cg_tools/$(OS_FOLDER)/C6000_$(CGT_VERSION)
+ export TOOLCHAIN_PATH_EVE ?= $(SDK_INSTALL_PATH)/ti_components/cg_tools/$(OS_FOLDER)/arp32_$(CGT_ARP32_VERSION)
+ export PDK_INSTALL_PATH ?= $(SDK_INSTALL_PATH)/ti_components/drivers/pdk_$(PDK_VERSION)/packages
+ export EDMA3LLD_BIOS6_INSTALLDIR ?= $(SDK_INSTALL_PATH)/ti_components/drivers/edma3_lld_$(EDMA_VERSION)
+ export BIOS_INSTALL_PATH ?= $(SDK_INSTALL_PATH)/ti_components/os_tools/bios_$(BIOS_VERSION)
+ export XDC_INSTALL_PATH ?= $(SDK_INSTALL_PATH)/ti_components/os_tools/$(OS_FOLDER)/xdctools_$(XDC_VERSION)
+ export RADARLINK_INSTALL_PATH ?= $(SDK_INSTALL_PATH)/ti_components/radar/$(mmwavelink_version)
+ export MSHIELD_DK_DIR ?= $(SDK_INSTALL_PATH)/ti_components/mshield-dk_std_$(MSHIELD_VERSION)
+ export TI_SECURE_DEV_PKG := $(MSHIELD_DK_DIR)
+else
+ export GCC_VERSION_ARM_A8=$(GCC_CROSS_TOOL_PREFIX)$(GCC_CROSS_TOOL_TAG)
+ export GCC_VERSION_ARM_A9=$(GCC_CROSS_TOOL_PREFIX)$(GCC_CROSS_TOOL_TAG)
+ export CROSS_TOOL_PRFX ?= $(GCC_CROSS_TOOL_PREFIX)
+ export C6X_GEN_INSTALL_PATH ?= $(TOOLS_INSTALL_PATH)/ti-cgt-c6000_$(CGT_VERSION)
+ export C7X_GEN_INSTALL_PATH ?= $(TOOLS_INSTALL_PATH)/ti-cgt-c7000_$(CGT_C7X_VERSION)
+ export CL_PRU_INSTALL_PATH ?= $(TOOLS_INSTALL_PATH)/ti-cgt-pru_$(CGT_PRU_VERSION)
+ export TOOLCHAIN_PATH_A8 ?= $(TOOLS_INSTALL_PATH)/gcc-$(GCC_VERSION_ARM_A8)
+ export TOOLCHAIN_PATH_A9 ?= $(TOOLS_INSTALL_PATH)/gcc-$(GCC_VERSION_ARM_A9)
+ export TOOLCHAIN_PATH_Arm9 ?= $(TOOLS_INSTALL_PATH)/ti-cgt-arm_$(CGT_ARM_VERSION)
+ export TOOLCHAIN_PATH_A15 ?= $(TOOLS_INSTALL_PATH)/gcc-$(GCC_VERSION_ARM_A15)
+ifeq ($(OS),Windows_NT)
+ #Paths for windows machine
+ export TOOLCHAIN_PATH_GCC_ARCH64 ?= $(TOOLS_INSTALL_PATH)/gcc-linaro-$(GCC_ARCH64_VERSION)-i686-mingw32_aarch64-elf
+else
+ #Paths for linux machine
+ export TOOLCHAIN_PATH_GCC_ARCH64 ?= $(TOOLS_INSTALL_PATH)/gcc-linaro-$(GCC_ARCH64_VERSION)-x86_64_aarch64-elf
+endif
+
+ export TOOLCHAIN_PATH_QNX_A72 ?= $(QNX_HOST)/usr/bin
+ export TOOLCHAIN_PATH_A53 ?= $(TOOLCHAIN_PATH_GCC_ARCH64)
+ export TOOLCHAIN_PATH_A72 ?= $(TOOLCHAIN_PATH_GCC_ARCH64)
+ export TOOLCHAIN_PATH_EVE ?= $(TOOLS_INSTALL_PATH)/arp32_$(CGT_ARP32_VERSION)
+ export TOOLCHAIN_PATH_M4 ?= $(TOOLS_INSTALL_PATH)/ti-cgt-arm_$(CGT_ARM_VERSION)
+ export TOOLCHAIN_PATH_R5 ?= $(TOOLS_INSTALL_PATH)/ti-cgt-arm_$(CGT_ARM_VERSION)
+ export BIOS_INSTALL_PATH ?= $(SDK_INSTALL_PATH)/bios_$(BIOS_VERSION)
+ export DSPLIB_INSTALL_PATH ?= $(SDK_INSTALL_PATH)/dsplib_$(DSPLIB_VERSION)
+ export EDMA3LLD_BIOS6_INSTALLDIR ?= $(SDK_INSTALL_PATH)/edma3_lld_$(EDMA_VERSION)
+ export IMGLIB_INSTALL_PATH ?= $(SDK_INSTALL_PATH)/imglib_$(IMGLIB_VERSION)
+ export IPC_INSTALL_PATH ?= $(SDK_INSTALL_PATH)/ipc_$(IPC_VERSION)
+ export MATHLIB_INSTALL_PATH ?= $(SDK_INSTALL_PATH)/mathlib_$(MATHLIB_VERSION)
+ export NDK_INSTALL_PATH ?= $(SDK_INSTALL_PATH)/ndk_$(NDK_VERSION)
+ export NS_INSTALL_PATH ?= $(SDK_INSTALL_PATH)/ns_$(NS_VERSION)
+ export PDK_INSTALL_PATH ?= $(SDK_INSTALL_PATH)/pdk$(PDK_VERSION_STR)/packages
+ export UIA_INSTALL_PATH ?= $(SDK_INSTALL_PATH)/uia_$(UIA_VERSION)
+ export XDC_INSTALL_PATH ?= $(SDK_INSTALL_PATH)/xdctools_$(XDC_VERSION)
+ export UTILS_INSTALL_DIR ?= $(XDC_INSTALL_PATH)/bin
+ export RADARLINK_INSTALL_PATH ?= $(SDK_INSTALL_PATH)/$(mmwavelink_version)
+ export CG_XML_BIN_INSTALL_PATH ?= $(SDK_INSTALL_PATH)/cg_xml_$(CG_XML_VERSION)/bin
+ export TI_SECURE_DEV_PKG ?= $(SDK_INSTALL_PATH)/proc-sdk-secdev_$(SECDEV_VERSION)
+ export XDAIS_INSTALL_PATH ?= $(SDK_INSTALL_PATH)/xdais_$(XDAIS_VERSION)
+ export AER_INSTALL_PATH ?= $(SDK_INSTALL_PATH)/aer_c64Px_obj_$(AER_VERSION)
+ export GCC_ARM_NONE_TOOLCHAIN ?= $(SDK_INSTALL_PATH)/gcc-$(GCC_CROSS_TOOL_PREFIX)$(GCC_CROSS_TOOL_TAG)
+ export TI_CGT6x_INSTALL_DIR ?= $(SDK_INSTALL_PATH)/c6000_7.4.16
+ export M4_TOOLCHAIN_INSTALL_DIR ?= $(TOOLCHAIN_PATH_M4)
+endif
+
+ifeq ($(SOC),$(filter $(SOC), am335x))
+ export HARDLIB_PATH ?= $(TOOLCHAIN_PATH_A8)/lib/gcc/arm-none-eabi/$(GCC_VERSION_HARDLIB)/hard
+ export FPULIB_PATH ?= $(TOOLCHAIN_PATH_A8)/lib/gcc/arm-none-eabi/$(GCC_VERSION_FPULIB)/fpu
+else ifeq ($(SOC),$(filter $(SOC), am437x))
+ export HARDLIB_PATH ?= $(TOOLCHAIN_PATH_A9)/lib/gcc/arm-none-eabi/$(GCC_VERSION_HARDLIB)/hard
+ export FPULIB_PATH ?= $(TOOLCHAIN_PATH_A9)/lib/gcc/arm-none-eabi/$(GCC_VERSION_FPULIB)/fpu
+else
+ export HARDLIB_PATH ?= $(TOOLCHAIN_PATH_A15)/lib/gcc/arm-none-eabi/$(GCC_VERSION_HARDLIB)/hard
+ export FPULIB_PATH ?= $(TOOLCHAIN_PATH_A15)/lib/gcc/arm-none-eabi/$(GCC_VERSION_FPULIB)/fpu
+endif
+
+export CGTOOLS=$(C6X_GEN_INSTALL_PATH)
+export XDCCGROOT=$(C6X_GEN_INSTALL_PATH)
+
+# Utilities directory. This is required only if the build machine is Windows.
+# - specify the installation directory of utility which supports POSIX commands
+# (eg: Cygwin installation or MSYS installation).
+# This could be in CCS install directory as in c:/ti/ccsv<ver>/utils/cygwin or
+# the XDC install bin folder represented by $(UTILS_INSTALL_DIR)
+ifeq ($(OS),Windows_NT)
+ export utils_PATH ?= $(UTILS_INSTALL_DIR)
+endif
+
+################################################################################
+# Other advanced configurable variables
+################################################################################
+
+# Set Core Build Profile depending on BUILD_PROFILE value
+export BUILD_PROFILE_$(CORE) ?= $(BUILD_PROFILE)
+
+# Default PACKAGE_SELECT build flag
+# Supported values: all, vps-hal-only, vps-vip-only, vps-vpe-only, vps-dss-only, vps-vip-dss, vps-vip-vpe
+export PACKAGE_SELECT ?= all
+
+# Disable recursive building of example dependencies
+export DISABLE_RECURSE_DEPS ?= no
+
+# Default C++ build flag, yes or no
+export CPLUSPLUS_BUILD ?= no
+
+#use <module>_PATH variable as makefile internally expects PATH variable this way for external component path
+export pdk_PATH := $(PDK_INSTALL_PATH)
+export bios_PATH := $(BIOS_INSTALL_PATH)
+export xdc_PATH := $(XDC_INSTALL_PATH)
+export edma3_lld_PATH := $(EDMA3LLD_BIOS6_INSTALLDIR)
+export ndk_PATH := $(NDK_INSTALL_PATH)
+export radarLink_PATH := $(RADARLINK_INSTALL_PATH)
+
+export ROOTDIR := $(pdk_PATH)
+XDCPATH =
+ifeq ($(BUILD_OS_TYPE),tirtos)
+ XDCPATH = $(bios_PATH)/packages;$(xdc_PATH)/packages;$(edma3_lld_PATH)/packages;$(ndk_PATH)/packages;$(pdk_PATH);
+endif
+export XDCPATH
+
+#Default SECTTI SIZE INFORMATION
+export SECTTI_SIZE_INFO ?= no
+
+#Default SECTTI tool
+export SECTTI ?= $(CG_XML_BIN_INSTALL_PATH)/sectti
+
+# Build for HS devices if secdev package is found
+ifneq ("$(wildcard $(TI_SECURE_DEV_PKG)/scripts/secure-binary-image.sh)","")
+ export SECUREMODE ?= yes
+endif
+
+# include other dependent files
+include $(PDK_INSTALL_PATH)/ti/build/comp_paths.mk
+ifeq ($(MAKERULEDIR), )
+ #Makerule path not defined, define this and assume relative path from ROOTDIR
+ export MAKERULEDIR := $(ROOTDIR)/ti/build/makerules
+endif
+include $(MAKERULEDIR)/build_config.mk
+include $(MAKERULEDIR)/platform.mk
+include $(MAKERULEDIR)/env.mk
diff --git a/packages/ti/build/am335x/config_am335x_a8.bld b/packages/ti/build/am335x/config_am335x_a8.bld
--- /dev/null
@@ -0,0 +1,184 @@
+/*
+* Copyright (c) 2016, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* * Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* * Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the distribution.
+*
+* * Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+/*
+ * ======== config_am335x_a8.bld ========
+ * Build configuration script for BSP drivers
+ */
+/* load the required modules for the configuration */
+var A8 = xdc.useModule('gnu.targets.arm.A8F');
+/* A8 compiler directory path */
+A8.rootDir = java.lang.System.getenv("CGTOOLS_A8");
+
+/* Read the current board */
+var CurrentPlatform = java.lang.System.getenv("BOARD");
+
+if (CurrentPlatform == null)
+{
+ /* The env variable is probably not set while running inside CCS */
+ CurrentPlatform = java.lang.System.getProperty("BOARD");
+}
+
+/*add bspLib to support SemiHosting to enable system_printf on A8*/
+/* GCC bare metal targets */
+var gccArmTargets = xdc.loadPackage('gnu.targets.arm');
+gccArmTargets.A8F.bspLib = "rdimon";
+
+
+/*
+Memory map
+
+DDR: 0x80000000 (Ist 512MB - Cached)
+
+NOTE: APP_CACHED_DATA_BLK1_MEM is used to route sections which needs to be in a
+separate section preferably at the end of 512 MB memory.
+For example:
+Frame buffer memory can be less at runtime depending on boards with lesser DDR (as in TDA 12x12 POP boards).
+If the same is routed to APP_CACHED_DATA_MEM section then the linker will
+place the frame buffer before other data section and the other data will fall into
+region outside the DDR in the board. Hence separate section is used!!
+
++-----------------------------+
+| APP_CODE_MEM | 2MB
++-----------------------------+
+| APP_CACHED_DATA_BLK0_MEM | 1MB
++-----------------------------+
+| APP_CACHED_DATA_MEM | 20MB
++-----------------------------+
+| APP_CACHED_DATA_BLK1_MEM | 244MB
++-----------------------------+
+| APP_CACHED_DATA_BLK2_MEM | 128MB
++-----------------------------+
+| NOT USED | Remaining MB
++-----------------------------+
+
+DDR: 0xA0000000 (2nd 512MB - Non-Cached)
++-----------------------------+
+| |
+| APP_UNCACHED_DATA_BLK3_MEM | 2MB
++-----------------------------+
+| NOT USED | Remaining MB
++-----------------------------+
+
+*/
+
+var KB=1024;
+var MB=KB*KB;
+
+var DDR3_ADDR_0;
+var DDR3_ADDR_1;
+
+var APP_CODE_ADDR;
+var APP_CODE_SIZE;
+
+var APP_CACHED_DATA_ADDR;
+var APP_CACHED_DATA_SIZE;
+
+var APP_UNCACHED_DATA_BLK3_ADDR;
+var APP_UNCACHED_DATA_BLK3_SIZE;
+
+var APP_CACHED_DATA_BLK0_ADDR;
+var APP_CACHED_DATA_BLK0_SIZE;
+
+var APP_CACHED_DATA_BLK1_ADDR;
+var APP_CACHED_DATA_BLK1_SIZE;
+
+var APP_CACHED_DATA_BLK2_ADDR;
+var APP_CACHED_DATA_BLK2_SIZE;
+
+DDR3_ADDR_0 = 0x80000000;
+DDR3_ADDR_1 = 0xA0000000;
+
+APP_CODE_SIZE = 2*MB;
+APP_CACHED_DATA_BLK0_SIZE = 1*MB;
+APP_CACHED_DATA_SIZE = 20*MB;
+APP_CACHED_DATA_BLK1_SIZE = 244*MB;
+APP_CACHED_DATA_BLK2_SIZE = 128*MB;
+APP_UNCACHED_DATA_BLK3_SIZE = 2*MB;
+
+APP_CODE_ADDR = DDR3_ADDR_0;
+APP_CACHED_DATA_BLK0_ADDR = APP_CODE_ADDR + APP_CODE_SIZE;
+APP_CACHED_DATA_ADDR = APP_CACHED_DATA_BLK0_ADDR + APP_CACHED_DATA_BLK0_SIZE;
+APP_CACHED_DATA_BLK1_ADDR = APP_CACHED_DATA_ADDR + APP_CACHED_DATA_SIZE;
+APP_CACHED_DATA_BLK2_ADDR = APP_CACHED_DATA_BLK1_ADDR + APP_CACHED_DATA_BLK1_SIZE;
+APP_UNCACHED_DATA_BLK3_ADDR = DDR3_ADDR_1;
+
+
+
+myplatform = "ti.platforms.evmAM3359";
+
+
+Build.platformTable[myplatform] =
+{
+ externalMemoryMap:
+ [
+ ["APP_CODE_MEM", {
+ comment : "APP_CODE_MEM",
+ name : "APP_CODE_MEM",
+ base : APP_CODE_ADDR,
+ len : APP_CODE_SIZE
+ }],
+ ["APP_CACHED_DATA_BLK0_MEM", {
+ comment : "APP_CACHED_DATA_BLK0_MEM",
+ name : "APP_CACHED_DATA_BLK0_MEM",
+ base : APP_CACHED_DATA_BLK0_ADDR,
+ len : APP_CACHED_DATA_BLK0_SIZE
+ }],
+ ["APP_CACHED_DATA_MEM", {
+ comment : "APP_CACHED_DATA_MEM",
+ name : "APP_CACHED_DATA_MEM",
+ base : APP_CACHED_DATA_ADDR,
+ len : APP_CACHED_DATA_SIZE
+ }],
+ ["APP_UNCACHED_DATA_BLK3_MEM", {
+ comment : "APP_UNCACHED_DATA_BLK3_MEM",
+ name : "APP_UNCACHED_DATA_BLK3_MEM",
+ base : APP_UNCACHED_DATA_BLK3_ADDR,
+ len : APP_UNCACHED_DATA_BLK3_SIZE
+ }],
+ ["APP_CACHED_DATA_BLK1_MEM", {
+ comment : "APP_CACHED_DATA_BLK1_MEM",
+ name : "APP_CACHED_DATA_BLK1_MEM",
+ base : APP_CACHED_DATA_BLK1_ADDR,
+ len : APP_CACHED_DATA_BLK1_SIZE
+ }],
+ ["APP_CACHED_DATA_BLK2_MEM", {
+ comment : "APP_CACHED_DATA_BLK2_MEM",
+ name : "APP_CACHED_DATA_BLK2_MEM",
+ base : APP_CACHED_DATA_BLK2_ADDR,
+ len : APP_CACHED_DATA_BLK2_SIZE
+ }],
+ ],
+ codeMemory: "APP_CODE_MEM",
+ dataMemory: "APP_CACHED_DATA_MEM",
+ stackMemory: "APP_CACHED_DATA_MEM"
+};
diff --git a/packages/ti/build/am437x/config_am437x_a9.bld b/packages/ti/build/am437x/config_am437x_a9.bld
--- /dev/null
@@ -0,0 +1,181 @@
+/*
+* Copyright (c) 2016, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* * Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* * Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the distribution.
+*
+* * Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+/*
+ * ======== config_am437x_a9.bld ========
+ * Build configuration script for BSP drivers
+ */
+/* load the required modules for the configuration */
+var A9 = xdc.useModule('gnu.targets.arm.A9F');
+/* A9 compiler directory path */
+A9.rootDir = java.lang.System.getenv("CGTOOLS_A9");
+
+/* Read the current board */
+var CurrentPlatform = java.lang.System.getenv("BOARD");
+
+if (CurrentPlatform == null)
+{
+ /* The env variable is probably not set while running inside CCS */
+ CurrentPlatform = java.lang.System.getProperty("BOARD");
+}
+
+/*add bspLib to support SemiHosting to enable system_printf on A9*/
+/* GCC bare metal targets */
+var gccArmTargets = xdc.loadPackage('gnu.targets.arm');
+gccArmTargets.A9F.bspLib = "rdimon";
+
+/*
+Memory map
+
+DDR: 0x80000000 (Ist 512MB - Cached)
+
+NOTE: APP_CACHED_DATA_BLK1_MEM is used to route sections which needs to be in a
+separate section preferably at the end of 512 MB memory.
+For example:
+Frame buffer memory can be less at runtime depending on boards with lesser DDR (as in TDA 12x12 POP boards).
+If the same is routed to APP_CACHED_DATA_MEM section then the linker will
+place the frame buffer before other data section and the other data will fall into
+region outside the DDR in the board. Hence separate section is used!!
+
++-----------------------------+
+| APP_CODE_MEM | 2MB
++-----------------------------+
+| APP_CACHED_DATA_BLK0_MEM | 1MB
++-----------------------------+
+| APP_CACHED_DATA_MEM | 20MB
++-----------------------------+
+| APP_CACHED_DATA_BLK1_MEM | 244MB
++-----------------------------+
+| APP_CACHED_DATA_BLK2_MEM | 128MB
++-----------------------------+
+| NOT USED | Remaining MB
++-----------------------------+
+
+DDR: 0xA0000000 (2nd 512MB - Non-Cached)
++-----------------------------+
+| |
+| APP_UNCACHED_DATA_BLK3_MEM | 2MB
++-----------------------------+
+| NOT USED | Remaining MB
++-----------------------------+
+
+*/
+
+var KB=1024;
+var MB=KB*KB;
+
+var DDR3_ADDR_0;
+var DDR3_ADDR_1;
+
+var APP_CODE_ADDR;
+var APP_CODE_SIZE;
+
+var APP_CACHED_DATA_ADDR;
+var APP_CACHED_DATA_SIZE;
+
+var APP_UNCACHED_DATA_BLK3_ADDR;
+var APP_UNCACHED_DATA_BLK3_SIZE;
+
+var APP_CACHED_DATA_BLK0_ADDR;
+var APP_CACHED_DATA_BLK0_SIZE;
+
+var APP_CACHED_DATA_BLK1_ADDR;
+var APP_CACHED_DATA_BLK1_SIZE;
+
+var APP_CACHED_DATA_BLK2_ADDR;
+var APP_CACHED_DATA_BLK2_SIZE;
+
+DDR3_ADDR_0 = 0x80000000;
+DDR3_ADDR_1 = 0xA0000000;
+
+APP_CODE_SIZE = 2*MB;
+APP_CACHED_DATA_BLK0_SIZE = 1*MB;
+APP_CACHED_DATA_SIZE = 20*MB;
+APP_CACHED_DATA_BLK1_SIZE = 244*MB;
+APP_CACHED_DATA_BLK2_SIZE = 128*MB;
+APP_UNCACHED_DATA_BLK3_SIZE = 2*MB;
+
+APP_CODE_ADDR = DDR3_ADDR_0;
+APP_CACHED_DATA_BLK0_ADDR = APP_CODE_ADDR + APP_CODE_SIZE;
+APP_CACHED_DATA_ADDR = APP_CACHED_DATA_BLK0_ADDR + APP_CACHED_DATA_BLK0_SIZE;
+APP_CACHED_DATA_BLK1_ADDR = APP_CACHED_DATA_ADDR + APP_CACHED_DATA_SIZE;
+APP_CACHED_DATA_BLK2_ADDR = APP_CACHED_DATA_BLK1_ADDR + APP_CACHED_DATA_BLK1_SIZE;
+APP_UNCACHED_DATA_BLK3_ADDR = DDR3_ADDR_1;
+
+
+myplatform = "ti.platforms.evmAM437X";
+
+Build.platformTable[myplatform] =
+{
+ externalMemoryMap:
+ [
+ ["APP_CODE_MEM", {
+ comment : "APP_CODE_MEM",
+ name : "APP_CODE_MEM",
+ base : APP_CODE_ADDR,
+ len : APP_CODE_SIZE
+ }],
+ ["APP_CACHED_DATA_BLK0_MEM", {
+ comment : "APP_CACHED_DATA_BLK0_MEM",
+ name : "APP_CACHED_DATA_BLK0_MEM",
+ base : APP_CACHED_DATA_BLK0_ADDR,
+ len : APP_CACHED_DATA_BLK0_SIZE
+ }],
+ ["APP_CACHED_DATA_MEM", {
+ comment : "APP_CACHED_DATA_MEM",
+ name : "APP_CACHED_DATA_MEM",
+ base : APP_CACHED_DATA_ADDR,
+ len : APP_CACHED_DATA_SIZE
+ }],
+ ["APP_UNCACHED_DATA_BLK3_MEM", {
+ comment : "APP_UNCACHED_DATA_BLK3_MEM",
+ name : "APP_UNCACHED_DATA_BLK3_MEM",
+ base : APP_UNCACHED_DATA_BLK3_ADDR,
+ len : APP_UNCACHED_DATA_BLK3_SIZE
+ }],
+ ["APP_CACHED_DATA_BLK1_MEM", {
+ comment : "APP_CACHED_DATA_BLK1_MEM",
+ name : "APP_CACHED_DATA_BLK1_MEM",
+ base : APP_CACHED_DATA_BLK1_ADDR,
+ len : APP_CACHED_DATA_BLK1_SIZE
+ }],
+ ["APP_CACHED_DATA_BLK2_MEM", {
+ comment : "APP_CACHED_DATA_BLK2_MEM",
+ name : "APP_CACHED_DATA_BLK2_MEM",
+ base : APP_CACHED_DATA_BLK2_ADDR,
+ len : APP_CACHED_DATA_BLK2_SIZE
+ }],
+ ],
+ codeMemory: "APP_CODE_MEM",
+ dataMemory: "APP_CACHED_DATA_MEM",
+ stackMemory: "APP_CACHED_DATA_MEM"
+};
diff --git a/packages/ti/build/am571x/config_am571x.bld b/packages/ti/build/am571x/config_am571x.bld
--- /dev/null
@@ -0,0 +1,157 @@
+/*
+* Copyright (c) 2016, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* * Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* * Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the distribution.
+*
+* * Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+/*
+ * ======== config.bld ========
+ * Build configuration script for BSP drivers
+ */
+
+/* load the required modules for the configuration */
+var M4 = xdc.useModule('ti.targets.arm.elf.M4');
+/* M4 compiler directory path */
+M4.rootDir = java.lang.System.getenv("CGTOOLS");
+
+var CurrentPlatform = java.lang.System.getenv("BOARD");
+
+/*
+Memory map
+
+DDR: 0x80000000 (Ist 512MB - Cached)
+
+NOTE: APP_CACHED_DATA_BLK1_MEM is used to route sections which needs to be in a
+separate section preferably at the end of 512 MB memory.
+For example:
+Frame buffer memory can be less at runtime depending on boards with lesser DDR (as in TDA 12x12 POP boards).
+If the same is routed to APP_CACHED_DATA_MEM section then the linker will
+place the frame buffer before other data section and the other data will fall into
+region outside the DDR in the board. Hence separate section is used!!
+
++-----------------------------+
+| APP_CODE_MEM | 3MB
++-----------------------------+
+| APP_CACHED_DATA_MEM | 20MB
++-----------------------------+
+| APP_CACHED_DATA_BLK1_MEM | 244MB
++-----------------------------+
+| APP_CACHED_DATA_BLK2_MEM | 128MB
++-----------------------------+
+| NOT USED | Remaining MB
++-----------------------------+
+
+DDR: 0xA0000000 (2nd 512MB - Non-Cached)
++-----------------------------+
+| |
+| APP_UNCACHED_DATA_BLK3_MEM | 2MB
++-----------------------------+
+| NOT USED | Remaining MB
++-----------------------------+
+
+*/
+
+var KB=1024;
+var MB=KB*KB;
+
+var DDR3_ADDR_0;
+var DDR3_ADDR_1;
+
+var APP_CODE_ADDR;
+var APP_CODE_SIZE;
+
+var APP_CACHED_DATA_ADDR;
+var APP_CACHED_DATA_SIZE;
+
+var APP_UNCACHED_DATA_BLK3_ADDR;
+var APP_UNCACHED_DATA_BLK3_SIZE;
+
+var APP_CACHED_DATA_BLK1_ADDR;
+var APP_CACHED_DATA_BLK1_SIZE;
+
+var APP_CACHED_DATA_BLK2_ADDR;
+var APP_CACHED_DATA_BLK2_SIZE;
+
+/* First 4KB reserved for components such as SBL */
+SBL_SIZE = 4*KB;
+DDR3_ADDR_0 = 0x80000000 + SBL_SIZE;
+DDR3_ADDR_1 = 0xA0000000;
+
+APP_CODE_SIZE = 3*MB - SBL_SIZE;
+APP_CACHED_DATA_SIZE = 20*MB;
+APP_CACHED_DATA_BLK1_SIZE = 244*MB;
+APP_CACHED_DATA_BLK2_SIZE = 128*MB;
+APP_UNCACHED_DATA_BLK3_SIZE = 2*MB;
+
+APP_CODE_ADDR = DDR3_ADDR_0;
+APP_CACHED_DATA_ADDR = APP_CODE_ADDR + APP_CODE_SIZE;
+APP_CACHED_DATA_BLK1_ADDR = APP_CACHED_DATA_ADDR + APP_CACHED_DATA_SIZE;
+APP_CACHED_DATA_BLK2_ADDR = APP_CACHED_DATA_BLK1_ADDR + APP_CACHED_DATA_BLK1_SIZE;
+APP_UNCACHED_DATA_BLK3_ADDR = DDR3_ADDR_1;
+
+myplatform = "ti.platforms.idkAM571X";
+
+Build.platformTable[myplatform] =
+{
+ externalMemoryMap:
+ [
+ ["APP_CODE_MEM", {
+ comment : "APP_CODE_MEM",
+ name : "APP_CODE_MEM",
+ base : APP_CODE_ADDR,
+ len : APP_CODE_SIZE
+ }],
+ ["APP_CACHED_DATA_MEM", {
+ comment : "APP_CACHED_DATA_MEM",
+ name : "APP_CACHED_DATA_MEM",
+ base : APP_CACHED_DATA_ADDR,
+ len : APP_CACHED_DATA_SIZE
+ }],
+ ["APP_UNCACHED_DATA_BLK3_MEM", {
+ comment : "APP_UNCACHED_DATA_BLK3_MEM",
+ name : "APP_UNCACHED_DATA_BLK3_MEM",
+ base : APP_UNCACHED_DATA_BLK3_ADDR,
+ len : APP_UNCACHED_DATA_BLK3_SIZE
+ }],
+ ["APP_CACHED_DATA_BLK1_MEM", {
+ comment : "APP_CACHED_DATA_BLK1_MEM",
+ name : "APP_CACHED_DATA_BLK1_MEM",
+ base : APP_CACHED_DATA_BLK1_ADDR,
+ len : APP_CACHED_DATA_BLK1_SIZE
+ }],
+ ["APP_CACHED_DATA_BLK2_MEM", {
+ comment : "APP_CACHED_DATA_BLK2_MEM",
+ name : "APP_CACHED_DATA_BLK2_MEM",
+ base : APP_CACHED_DATA_BLK2_ADDR,
+ len : APP_CACHED_DATA_BLK2_SIZE
+ }],
+ ],
+ codeMemory: "APP_CODE_MEM",
+ dataMemory: "APP_CACHED_DATA_MEM",
+ stackMemory: "APP_CACHED_DATA_MEM"
+};
diff --git a/packages/ti/build/am571x/config_am571x_a15.bld b/packages/ti/build/am571x/config_am571x_a15.bld
--- /dev/null
@@ -0,0 +1,169 @@
+/*
+* Copyright (c) 2016, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* * Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* * Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the distribution.
+*
+* * Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+/*
+ * ======== config_am572x_a15.bld ========
+ * Build configuration script for BSP drivers
+ */
+/* load the required modules for the configuration */
+var A15 = xdc.useModule('gnu.targets.arm.A15F');
+/* A15 compiler directory path */
+A15.rootDir = java.lang.System.getenv("CGTOOLS_A15");
+
+/* Read the current board */
+var CurrentPlatform = java.lang.System.getenv("BOARD");
+
+if (CurrentPlatform == null)
+{
+ /* The env variable is probably not set while running inside CCS */
+ CurrentPlatform = java.lang.System.getProperty("BOARD");
+}
+
+/*add bspLib to support SemiHosting to enable system_printf on A15*/
+/* GCC bare metal targets */
+var gccArmTargets = xdc.loadPackage('gnu.targets.arm');
+gccArmTargets.A15F.bspLib = "rdimon";
+
+/*
+Memory map
+
+DDR: 0x80000000 (Ist 512MB - Cached)
+
+NOTE: APP_CACHED_DATA_BLK1_MEM is used to route sections which needs to be in a
+separate section preferably at the end of 512 MB memory.
+For example:
+Frame buffer memory can be less at runtime depending on boards with lesser DDR (as in TDA 12x12 POP boards).
+If the same is routed to APP_CACHED_DATA_MEM section then the linker will
+place the frame buffer before other data section and the other data will fall into
+region outside the DDR in the board. Hence separate section is used!!
+
++-----------------------------+
+| APP_CODE_MEM | 3MB
++-----------------------------+
+| APP_CACHED_DATA_MEM | 20MB
++-----------------------------+
+| APP_CACHED_DATA_BLK1_MEM | 244MB
++-----------------------------+
+| APP_CACHED_DATA_BLK2_MEM | 128MB
++-----------------------------+
+| NOT USED | Remaining MB
++-----------------------------+
+
+DDR: 0xA0000000 (2nd 512MB - Non-Cached)
++-----------------------------+
+| |
+| APP_UNCACHED_DATA_BLK3_MEM | 2MB
++-----------------------------+
+| NOT USED | Remaining MB
++-----------------------------+
+
+*/
+
+var KB=1024;
+var MB=KB*KB;
+
+var DDR3_ADDR_0;
+var DDR3_ADDR_1;
+
+var APP_CODE_ADDR;
+var APP_CODE_SIZE;
+
+var APP_CACHED_DATA_ADDR;
+var APP_CACHED_DATA_SIZE;
+
+var APP_UNCACHED_DATA_BLK3_ADDR;
+var APP_UNCACHED_DATA_BLK3_SIZE;
+
+var APP_CACHED_DATA_BLK1_ADDR;
+var APP_CACHED_DATA_BLK1_SIZE;
+
+var APP_CACHED_DATA_BLK2_ADDR;
+var APP_CACHED_DATA_BLK2_SIZE;
+
+/* First 4KB reserved for components such as SBL */
+SBL_SIZE = 4*KB;
+DDR3_ADDR_0 = 0x80000000 + SBL_SIZE;
+DDR3_ADDR_1 = 0xA0000000;
+
+APP_CODE_SIZE = 3*MB - SBL_SIZE;
+APP_CACHED_DATA_SIZE = 20*MB;
+APP_CACHED_DATA_BLK1_SIZE = 244*MB;
+APP_CACHED_DATA_BLK2_SIZE = 128*MB;
+APP_UNCACHED_DATA_BLK3_SIZE = 2*MB;
+
+APP_CODE_ADDR = DDR3_ADDR_0;
+APP_CACHED_DATA_ADDR = APP_CODE_ADDR + APP_CODE_SIZE;
+APP_CACHED_DATA_BLK1_ADDR = APP_CACHED_DATA_ADDR + APP_CACHED_DATA_SIZE;
+APP_CACHED_DATA_BLK2_ADDR = APP_CACHED_DATA_BLK1_ADDR + APP_CACHED_DATA_BLK1_SIZE;
+APP_UNCACHED_DATA_BLK3_ADDR = DDR3_ADDR_1;
+
+myplatform = "ti.platforms.idkAM571X";
+
+Build.platformTable[myplatform] =
+{
+ externalMemoryMap:
+ [
+ ["APP_CODE_MEM", {
+ comment : "APP_CODE_MEM",
+ name : "APP_CODE_MEM",
+ base : APP_CODE_ADDR,
+ len : APP_CODE_SIZE
+ }],
+ ["APP_CACHED_DATA_MEM", {
+ comment : "APP_CACHED_DATA_MEM",
+ name : "APP_CACHED_DATA_MEM",
+ base : APP_CACHED_DATA_ADDR,
+ len : APP_CACHED_DATA_SIZE
+ }],
+ ["APP_UNCACHED_DATA_BLK3_MEM", {
+ comment : "APP_UNCACHED_DATA_BLK3_MEM",
+ name : "APP_UNCACHED_DATA_BLK3_MEM",
+ base : APP_UNCACHED_DATA_BLK3_ADDR,
+ len : APP_UNCACHED_DATA_BLK3_SIZE
+ }],
+ ["APP_CACHED_DATA_BLK1_MEM", {
+ comment : "APP_CACHED_DATA_BLK1_MEM",
+ name : "APP_CACHED_DATA_BLK1_MEM",
+ base : APP_CACHED_DATA_BLK1_ADDR,
+ len : APP_CACHED_DATA_BLK1_SIZE
+ }],
+ ["APP_CACHED_DATA_BLK2_MEM", {
+ comment : "APP_CACHED_DATA_BLK2_MEM",
+ name : "APP_CACHED_DATA_BLK2_MEM",
+ base : APP_CACHED_DATA_BLK2_ADDR,
+ len : APP_CACHED_DATA_BLK2_SIZE
+ }],
+ ],
+ codeMemory: "APP_CODE_MEM",
+ dataMemory: "APP_CACHED_DATA_MEM",
+ stackMemory: "APP_CACHED_DATA_MEM"
+};
diff --git a/packages/ti/build/am571x/config_am571x_c66.bld b/packages/ti/build/am571x/config_am571x_c66.bld
--- /dev/null
@@ -0,0 +1,160 @@
+/*
+* Copyright (c) 2016, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* * Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* * Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the distribution.
+*
+* * Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+/*
+ * ======== config.bld ========
+ * Sample Build configuration script
+ */
+
+/* load the required modules for the configuration */
+var C66 = xdc.useModule('ti.targets.elf.C66');
+/* C66 compiler directory path */
+C66.rootDir = java.lang.System.getenv("CGTOOLS_DSP");
+
+/* compiler options */
+C66.ccOpts.suffix += " -mi10 -mo ";
+
+var CurrentPlatform = java.lang.System.getenv("BOARD");
+
+/*
+Memory map
+
+DDR: 0x80000000 (Ist 512MB - Cached)
+
+NOTE: APP_CACHED_DATA_BLK1_MEM is used to route sections which needs to be in a
+separate section preferably at the end of 512 MB memory.
+For example:
+Frame buffer memory can be less at runtime depending on boards with lesser DDR (as in TDA 12x12 POP boards).
+If the same is routed to APP_CACHED_DATA_MEM section then the linker will
+place the frame buffer before other data section and the other data will fall into
+region outside the DDR in the board. Hence separate section is used!!
+
++-----------------------------+
+| APP_CODE_MEM | 3MB
++-----------------------------+
+| APP_CACHED_DATA_MEM | 20MB
++-----------------------------+
+| APP_CACHED_DATA_BLK1_MEM | 244MB
++-----------------------------+
+| APP_CACHED_DATA_BLK2_MEM | 128MB
++-----------------------------+
+| NOT USED | Remaining MB
++-----------------------------+
+
+DDR: 0xA0000000 (2nd 512MB - Non-Cached)
++-----------------------------+
+| |
+| APP_UNCACHED_DATA_BLK3_MEM | 2MB
++-----------------------------+
+| NOT USED | Remaining MB
++-----------------------------+
+
+*/
+
+var KB=1024;
+var MB=KB*KB;
+
+var DDR3_ADDR_0;
+var DDR3_ADDR_1;
+
+var APP_CODE_ADDR;
+var APP_CODE_SIZE;
+
+var APP_CACHED_DATA_ADDR;
+var APP_CACHED_DATA_SIZE;
+
+var APP_UNCACHED_DATA_BLK3_ADDR;
+var APP_UNCACHED_DATA_BLK3_SIZE;
+
+var APP_CACHED_DATA_BLK1_ADDR;
+var APP_CACHED_DATA_BLK1_SIZE;
+
+var APP_CACHED_DATA_BLK2_ADDR;
+var APP_CACHED_DATA_BLK2_SIZE;
+
+/* First 4KB reserved for components such as SBL */
+SBL_SIZE = 4*KB;
+DDR3_ADDR_0 = 0x80000000 + SBL_SIZE;
+DDR3_ADDR_1 = 0xA0000000;
+
+APP_CODE_SIZE = 3*MB - SBL_SIZE;
+APP_CACHED_DATA_SIZE = 20*MB;
+APP_CACHED_DATA_BLK1_SIZE = 244*MB;
+APP_CACHED_DATA_BLK2_SIZE = 128*MB;
+APP_UNCACHED_DATA_BLK3_SIZE = 2*MB;
+
+APP_CODE_ADDR = DDR3_ADDR_0;
+APP_CACHED_DATA_ADDR = APP_CODE_ADDR + APP_CODE_SIZE;
+APP_CACHED_DATA_BLK1_ADDR = APP_CACHED_DATA_ADDR + APP_CACHED_DATA_SIZE;
+APP_CACHED_DATA_BLK2_ADDR = APP_CACHED_DATA_BLK1_ADDR + APP_CACHED_DATA_BLK1_SIZE;
+APP_UNCACHED_DATA_BLK3_ADDR = DDR3_ADDR_1;
+
+myplatform = "ti.platforms.idkAM571X";
+
+Build.platformTable[myplatform] =
+{
+ externalMemoryMap:
+ [
+ ["APP_CODE_MEM", {
+ comment : "APP_CODE_MEM",
+ name : "APP_CODE_MEM",
+ base : APP_CODE_ADDR,
+ len : APP_CODE_SIZE
+ }],
+ ["APP_CACHED_DATA_MEM", {
+ comment : "APP_CACHED_DATA_MEM",
+ name : "APP_CACHED_DATA_MEM",
+ base : APP_CACHED_DATA_ADDR,
+ len : APP_CACHED_DATA_SIZE
+ }],
+ ["APP_UNCACHED_DATA_BLK3_MEM", {
+ comment : "APP_UNCACHED_DATA_BLK3_MEM",
+ name : "APP_UNCACHED_DATA_BLK3_MEM",
+ base : APP_UNCACHED_DATA_BLK3_ADDR,
+ len : APP_UNCACHED_DATA_BLK3_SIZE
+ }],
+ ["APP_CACHED_DATA_BLK1_MEM", {
+ comment : "APP_CACHED_DATA_BLK1_MEM",
+ name : "APP_CACHED_DATA_BLK1_MEM",
+ base : APP_CACHED_DATA_BLK1_ADDR,
+ len : APP_CACHED_DATA_BLK1_SIZE
+ }],
+ ["APP_CACHED_DATA_BLK2_MEM", {
+ comment : "APP_CACHED_DATA_BLK2_MEM",
+ name : "APP_CACHED_DATA_BLK2_MEM",
+ base : APP_CACHED_DATA_BLK2_ADDR,
+ len : APP_CACHED_DATA_BLK2_SIZE
+ }],
+ ],
+ codeMemory: "APP_CODE_MEM",
+ dataMemory: "APP_CACHED_DATA_MEM",
+ stackMemory: "APP_CACHED_DATA_MEM"
+};
diff --git a/packages/ti/build/am571x/mem_segment_definition_1024mb_bios.xs b/packages/ti/build/am571x/mem_segment_definition_1024mb_bios.xs
--- /dev/null
@@ -0,0 +1,261 @@
+/*
+* Copyright (c) 2016, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* * Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* * Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the distribution.
+*
+* * Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+/*
+ * ======== mem_segment_definition.xs ========
+ * ======== Single file for the memory map configuration of all cores =========
+ */
+
+KB=1024;
+MB=KB*KB;
+
+DDR3_ADDR = 0x80000000;
+DDR3_SIZE = 1024*MB;
+
+DDR3_BASE_ADDR_0 = 0x80000000;
+DDR3_BASE_SIZE_0 = 512*MB;
+
+/* The start address of the second mem section should be 16MB aligned.
+ * for REMOTE_LOG_MEM sections.
+ * tlb_config_eveX.c need to be modified otherwise
+ */
+DDR3_BASE_ADDR_1 = 0xA0000000;
+DDR3_BASE_SIZE_1 = 512*MB;
+
+OCMC1_ADDR = 0x40300000;
+OCMC1_SIZE = 512*KB;
+
+DSP1_L2_SRAM_ADDR = 0x40800000;
+DSP1_L2_SRAM_SIZE = 288*KB;
+
+TOTAL_MEM_SIZE = (DDR3_SIZE);
+
+/* First 512 MB - cached */
+/* EVE vecs space should be align with 16MB boundary, and if possible try to fit
+ * the entire vecs+code+data in 16MB section.
+ * tlb_config_eveX.c need to be modified if any of these EVE memory sections or
+ * SR1_FRAME_BUFFER_MEM section is modified.
+ */
+IPU1_1_CODE_SIZE = 2*MB;
+IPU1_1_BSS_SIZE = 6*MB;
+IPU1_1_DATA_SIZE = 4*MB;
+IPU1_0_CODE_SIZE = 6*MB;
+IPU1_0_BSS_SIZE = 10*MB;
+IPU1_0_DATA_SIZE = 4*MB;
+SR1_FRAME_BUFFER_SIZE = 256*MB;
+DSP1_CODE_SIZE = 2*MB;
+DSP1_DATA_SIZE = 64*MB;
+/* A15_0_CODE_SIZE reduced since it is not used in .bld file.
+ * Check .bld for details. Originally 2 + 14 MB.
+ */
+A15_0_NDK_DATA_SIZE = 4*MB;
+A15_0_DATA_SIZE = 16*MB - A15_0_NDK_DATA_SIZE;
+
+
+
+/* Second 512 MB - non-cached */
+/* The start address of the second mem section should be 16MB aligned.
+ * This alignment is a must as a single 16MB mapping is used for EMOTE_LOG_MEM sections.
+ * tlb_config_eveX.c need to be modified otherwise
+ */
+REMOTE_LOG_SIZE = 160*KB;
+SYSTEM_IPC_SHM_SIZE = 224*KB;
+LINK_STATS_SIZE = 256*KB;
+HDVPSS_DESC_SIZE = 1024*KB;
+SR0_SIZE = 128*KB;
+
+
+/* Cached Section */
+/* EVE vecs space should be align with 16MB boundary, and if possible try to fit
+ * the entire vecs+code+data in 16MB section.
+ * SR1_FRAME_BUFFER_MEM section is modified.
+ */
+IPU1_1_CODE_ADDR = DDR3_BASE_ADDR_0;
+IPU1_1_DATA_ADDR = IPU1_1_CODE_ADDR + IPU1_1_CODE_SIZE;
+IPU1_1_BSS_ADDR = IPU1_1_DATA_ADDR + IPU1_1_DATA_SIZE;
+IPU1_0_CODE_ADDR = IPU1_1_BSS_ADDR + IPU1_1_BSS_SIZE;
+IPU1_0_DATA_ADDR = IPU1_0_CODE_ADDR + IPU1_0_CODE_SIZE;
+IPU1_0_BSS_ADDR = IPU1_0_DATA_ADDR + IPU1_0_DATA_SIZE;
+SR1_FRAME_BUFFER_ADDR = IPU1_0_BSS_ADDR + IPU1_0_BSS_SIZE;
+DSP1_CODE_ADDR = SR1_FRAME_BUFFER_ADDR + SR1_FRAME_BUFFER_SIZE;
+DSP1_DATA_ADDR = DSP1_CODE_ADDR + DSP1_CODE_SIZE;
+A15_0_NDK_DATA_ADDR = DSP1_DATA_ADDR + DSP1_DATA_SIZE;
+A15_0_DATA_ADDR = A15_0_NDK_DATA_ADDR + A15_0_NDK_DATA_SIZE;
+
+
+/* Non Cached Section */
+/* The start address of the second mem section should be 16MB aligned.
+ * This alignment is a must as a single 16MB mapping is used for EMOTE_LOG_MEM sections.
+ * tlb_config_eveX.c need to be modified otherwise
+ */
+SR0_ADDR = DDR3_BASE_ADDR_1;
+REMOTE_LOG_ADDR = SR0_ADDR + SR0_SIZE;
+LINK_STATS_ADDR = REMOTE_LOG_ADDR + REMOTE_LOG_SIZE;
+SYSTEM_IPC_SHM_ADDR = LINK_STATS_ADDR + LINK_STATS_SIZE;
+HDVPSS_DESC_ADDR = SYSTEM_IPC_SHM_ADDR + SYSTEM_IPC_SHM_SIZE;
+
+if ((A15_0_DATA_ADDR + A15_0_DATA_SIZE) > (DDR3_BASE_ADDR_0 + DDR3_BASE_SIZE_0))
+{
+ throw xdc.$$XDCException("MEMORY_MAP OVERFLOW ERROR ",
+ "\nRegion End: " + "0x" + java.lang.Long.toHexString(DDR3_BASE_ADDR_0 + DDR3_BASE_SIZE_0) +
+ "\nActual End: " + "0x" + java.lang.Long.toHexString(A15_0_DATA_ADDR + A15_0_DATA_SIZE));
+}
+
+if ((HDVPSS_DESC_ADDR + HDVPSS_DESC_SIZE) > (DDR3_BASE_ADDR_1 + DDR3_BASE_SIZE_1))
+{
+ throw xdc.$$XDCException("MEMORY_MAP OVERFLOW ERROR ",
+ "\nRegion End: " + "0x" + java.lang.Long.toHexString(DDR3_BASE_ADDR_1 + DDR3_BASE_SIZE_1) +
+ "\nActual End: " + "0x" + java.lang.Long.toHexString(HDVPSS_DESC_ADDR + HDVPSS_DESC_SIZE));
+}
+
+if ((DDR3_BASE_SIZE_1 + DDR3_BASE_SIZE_0) > (TOTAL_MEM_SIZE))
+{
+ throw xdc.$$XDCException("MEMORY_MAP EXCEEDS DDR SIZE ERROR ",
+ "\nRegion End: " + "0x" + java.lang.Long.toHexString(DDR3_BASE_SIZE_1 + DDR3_BASE_SIZE_0) +
+ "\nActual End: " + "0x" + java.lang.Long.toHexString(TOTAL_MEM_SIZE));
+}
+
+
+function getMemSegmentDefinition_external(core)
+{
+ var memory = new Array();
+ var index = 0;
+
+ memory[index++] = ["IPU1_1_CODE_MEM", {
+ comment : "IPU1_1_CODE_MEM",
+ name : "IPU1_1_CODE_MEM",
+ base : IPU1_1_CODE_ADDR,
+ len : IPU1_1_CODE_SIZE
+ }];
+ memory[index++] = ["IPU1_1_DATA_MEM", {
+ comment : "IPU1_1_DATA_MEM",
+ name : "IPU1_1_DATA_MEM",
+ base : IPU1_1_DATA_ADDR,
+ len : IPU1_1_DATA_SIZE
+ }];
+ memory[index++] = ["IPU1_1_BSS_MEM", {
+ comment : "IPU1_1_BSS_MEM",
+ name : "IPU1_1_BSS_MEM",
+ base : IPU1_1_BSS_ADDR,
+ len : IPU1_1_BSS_SIZE
+ }];
+ memory[index++] = ["IPU1_0_CODE_MEM", {
+ comment : "IPU1_0_CODE_MEM",
+ name : "IPU1_0_CODE_MEM",
+ base : IPU1_0_CODE_ADDR,
+ len : IPU1_0_CODE_SIZE
+ }];
+ memory[index++] = ["IPU1_0_DATA_MEM", {
+ comment : "IPU1_0_DATA_MEM",
+ name : "IPU1_0_DATA_MEM",
+ base : IPU1_0_DATA_ADDR,
+ len : IPU1_0_DATA_SIZE
+ }];
+ memory[index++] = ["IPU1_0_BSS_MEM", {
+ comment : "IPU1_0_BSS_MEM",
+ name : "IPU1_0_BSS_MEM",
+ base : IPU1_0_BSS_ADDR,
+ len : IPU1_0_BSS_SIZE
+ }];
+ memory[index++] = ["DSP1_CODE_MEM", {
+ comment : "DSP1_CODE_MEM",
+ name : "DSP1_CODE_MEM",
+ base : DSP1_CODE_ADDR,
+ len : DSP1_CODE_SIZE
+ }];
+ memory[index++] = ["DSP1_DATA_MEM", {
+ comment : "DSP1_DATA_MEM",
+ name : "DSP1_DATA_MEM",
+ base : DSP1_DATA_ADDR,
+ len : DSP1_DATA_SIZE
+ }];
+
+ memory[index++] = ["A15_0_NDK_MEM", {
+ comment : "A15_0_NDK_MEM",
+ name : "A15_0_NDK_MEM",
+ base : A15_0_NDK_DATA_ADDR,
+ len : A15_0_NDK_DATA_SIZE
+ }];
+ memory[index++] = ["A15_0_DATA_MEM", {
+ comment : "A15_0_DATA_MEM",
+ name : "A15_0_DATA_MEM",
+ base : A15_0_DATA_ADDR,
+ len : A15_0_DATA_SIZE
+ }];
+ memory[index++] = ["SR1_FRAME_BUFFER_MEM", {
+ comment : "SR1_FRAME_BUFFER_MEM",
+ name : "SR1_FRAME_BUFFER_MEM",
+ base : SR1_FRAME_BUFFER_ADDR,
+ len : SR1_FRAME_BUFFER_SIZE
+ }];
+ memory[index++] = ["SR0", {
+ comment : "SR0",
+ name : "SR0",
+ base : SR0_ADDR,
+ len : SR0_SIZE
+ }];
+ memory[index++] = ["HDVPSS_DESC_MEM", {
+ comment : "HDVPSS_DESC_MEM",
+ name : "HDVPSS_DESC_MEM",
+ base : HDVPSS_DESC_ADDR,
+ len : HDVPSS_DESC_SIZE
+ }];
+ memory[index++] = ["REMOTE_LOG_MEM", {
+ comment : "REMOTE_LOG_MEM",
+ name : "REMOTE_LOG_MEM",
+ base : REMOTE_LOG_ADDR,
+ len : REMOTE_LOG_SIZE
+ }];
+ memory[index++] = ["LINK_STATS_MEM", {
+ comment : "LINK_STATS_MEM",
+ name : "LINK_STATS_MEM",
+ base : LINK_STATS_ADDR,
+ len : LINK_STATS_SIZE
+ }];
+ memory[index++] = ["SYSTEM_IPC_SHM_MEM", {
+ comment : "SYSTEM_IPC_SHM_MEM",
+ name : "SYSTEM_IPC_SHM_MEM",
+ base : SYSTEM_IPC_SHM_ADDR,
+ len : SYSTEM_IPC_SHM_SIZE
+ }];
+
+ xdc.print("# !!! Core is [" + core + "] !!!" );
+
+ memory[index++] = ["DSP1_L2_SRAM", {
+ comment: "DSP1_L2_SRAM",
+ name: "DSP1_L2_SRAM",
+ base: DSP1_L2_SRAM_ADDR,
+ len: DSP1_L2_SRAM_SIZE
+ }];
+
+ return (memory);
+}
diff --git a/packages/ti/build/am572x/config_am572x.bld b/packages/ti/build/am572x/config_am572x.bld
--- /dev/null
@@ -0,0 +1,182 @@
+/*
+* Copyright (c) 2016, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* * Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* * Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the distribution.
+*
+* * Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+/*
+ * ======== config.bld ========
+ * Build configuration script for BSP drivers
+ */
+
+/* load the required modules for the configuration */
+var M4 = xdc.useModule('ti.targets.arm.elf.M4');
+/* M4 compiler directory path */
+M4.rootDir = java.lang.System.getenv("CGTOOLS");
+
+var CurrentPlatform = java.lang.System.getenv("BOARD");
+
+/*
+Memory map
+
+DDR: 0x80000000 (Ist 512MB - Cached)
+
+NOTE: APP_CACHED_DATA_BLK1_MEM is used to route sections which needs to be in a
+separate section preferably at the end of 512 MB memory.
+For example:
+Frame buffer memory can be less at runtime depending on boards with lesser DDR (as in TDA 12x12 POP boards).
+If the same is routed to APP_CACHED_DATA_MEM section then the linker will
+place the frame buffer before other data section and the other data will fall into
+region outside the DDR in the board. Hence separate section is used!!
+
+NOTE: APP_CACHED_DATA_BLK0_MEM is only used for AM572 with REV1 PRU-ICSS.
+ .. This section will be referenced in the REV1 linker CMD file needed
+ .. by AM3xx and AM4xx. It is (counterintuitively) the final section
+ .. so as to not disturb the preferred section ordering.
+
++-----------------------------+
+| APP_CODE_MEM | 2MB
++-----------------------------+
+| APP_CACHED_DATA_MEM | 20MB
++-----------------------------+
+| APP_CACHED_DATA_BLK1_MEM | 244MB
++-----------------------------+
+| APP_CACHED_DATA_BLK2_MEM | 128MB
++-----------------------------+
+| APP_CACHED_DATA_BLK0_MEM | 1MB
++-----------------------------+
+| NOT USED | Remaining MB
++-----------------------------+
+
+DDR: 0xA0000000 (2nd 512MB - Non-Cached)
++-----------------------------+
+| |
+| APP_UNCACHED_DATA_BLK3_MEM | 2MB
++-----------------------------+
+| NOT USED | Remaining MB
++-----------------------------+
+
+*/
+
+var KB=1024;
+var MB=KB*KB;
+
+var DDR3_ADDR_0;
+var DDR3_ADDR_1;
+
+var APP_CODE_ADDR;
+var APP_CODE_SIZE;
+
+var APP_CACHED_DATA_ADDR;
+var APP_CACHED_DATA_SIZE;
+
+var APP_UNCACHED_DATA_BLK3_ADDR;
+var APP_UNCACHED_DATA_BLK3_SIZE;
+
+var APP_CACHED_DATA_BLK0_ADDR;
+var APP_CACHED_DATA_BLK0_SIZE;
+
+var APP_CACHED_DATA_BLK1_ADDR;
+var APP_CACHED_DATA_BLK1_SIZE;
+
+var APP_CACHED_DATA_BLK2_ADDR;
+var APP_CACHED_DATA_BLK2_SIZE;
+
+/* First 4KB reserved for components such as SBL */
+SBL_SIZE = 4*KB;
+DDR3_ADDR_0 = 0x80000000 + SBL_SIZE;
+DDR3_ADDR_1 = 0xA0000000;
+
+APP_CODE_SIZE = 3*MB - SBL_SIZE;
+APP_CACHED_DATA_SIZE = 20*MB;
+APP_CACHED_DATA_BLK0_SIZE = 1*MB;
+APP_CACHED_DATA_BLK1_SIZE = 244*MB;
+APP_CACHED_DATA_BLK2_SIZE = 128*MB;
+APP_UNCACHED_DATA_BLK3_SIZE = 2*MB;
+
+APP_CODE_ADDR = DDR3_ADDR_0;
+APP_CACHED_DATA_ADDR = APP_CODE_ADDR + APP_CODE_SIZE;
+APP_CACHED_DATA_BLK1_ADDR = APP_CACHED_DATA_ADDR + APP_CACHED_DATA_SIZE;
+APP_CACHED_DATA_BLK2_ADDR = APP_CACHED_DATA_BLK1_ADDR + APP_CACHED_DATA_BLK1_SIZE;
+APP_CACHED_DATA_BLK0_ADDR = APP_CACHED_DATA_BLK2_ADDR + APP_CACHED_DATA_BLK2_SIZE;
+APP_UNCACHED_DATA_BLK3_ADDR = DDR3_ADDR_1;
+
+if (CurrentPlatform == "evmAM572x")
+{
+ myplatform = "ti.platforms.evmAM572X";
+}
+else
+{
+ myplatform = "ti.platforms.idkAM572X";
+}
+
+Build.platformTable[myplatform] =
+{
+ externalMemoryMap:
+ [
+ ["APP_CODE_MEM", {
+ comment : "APP_CODE_MEM",
+ name : "APP_CODE_MEM",
+ base : APP_CODE_ADDR,
+ len : APP_CODE_SIZE
+ }],
+ ["APP_CACHED_DATA_BLK0_MEM", {
+ comment : "APP_CACHED_DATA_BLK0_MEM",
+ name : "APP_CACHED_DATA_BLK0_MEM",
+ base : APP_CACHED_DATA_BLK0_ADDR,
+ len : APP_CACHED_DATA_BLK0_SIZE
+ }],
+ ["APP_CACHED_DATA_MEM", {
+ comment : "APP_CACHED_DATA_MEM",
+ name : "APP_CACHED_DATA_MEM",
+ base : APP_CACHED_DATA_ADDR,
+ len : APP_CACHED_DATA_SIZE
+ }],
+ ["APP_UNCACHED_DATA_BLK3_MEM", {
+ comment : "APP_UNCACHED_DATA_BLK3_MEM",
+ name : "APP_UNCACHED_DATA_BLK3_MEM",
+ base : APP_UNCACHED_DATA_BLK3_ADDR,
+ len : APP_UNCACHED_DATA_BLK3_SIZE
+ }],
+ ["APP_CACHED_DATA_BLK1_MEM", {
+ comment : "APP_CACHED_DATA_BLK1_MEM",
+ name : "APP_CACHED_DATA_BLK1_MEM",
+ base : APP_CACHED_DATA_BLK1_ADDR,
+ len : APP_CACHED_DATA_BLK1_SIZE
+ }],
+ ["APP_CACHED_DATA_BLK2_MEM", {
+ comment : "APP_CACHED_DATA_BLK2_MEM",
+ name : "APP_CACHED_DATA_BLK2_MEM",
+ base : APP_CACHED_DATA_BLK2_ADDR,
+ len : APP_CACHED_DATA_BLK2_SIZE
+ }],
+ ],
+ codeMemory: "APP_CODE_MEM",
+ dataMemory: "APP_CACHED_DATA_MEM",
+ stackMemory: "APP_CACHED_DATA_MEM"
+};
diff --git a/packages/ti/build/am572x/config_am572x_a15.bld b/packages/ti/build/am572x/config_am572x_a15.bld
--- /dev/null
@@ -0,0 +1,194 @@
+/*
+* Copyright (c) 2016, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* * Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* * Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the distribution.
+*
+* * Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+/*
+ * ======== config_am572x_a15.bld ========
+ * Build configuration script for BSP drivers
+ */
+/* load the required modules for the configuration */
+var A15 = xdc.useModule('gnu.targets.arm.A15F');
+/* A15 compiler directory path */
+A15.rootDir = java.lang.System.getenv("CGTOOLS_A15");
+
+/* Read the current board */
+var CurrentPlatform = java.lang.System.getenv("BOARD");
+
+if (CurrentPlatform == null)
+{
+ /* The env variable is probably not set while running inside CCS */
+ CurrentPlatform = java.lang.System.getProperty("BOARD");
+}
+
+/*add bspLib to support SemiHosting to enable system_printf on A15*/
+/* GCC bare metal targets */
+var gccArmTargets = xdc.loadPackage('gnu.targets.arm');
+gccArmTargets.A15F.bspLib = "rdimon";
+
+/*
+Memory map
+
+DDR: 0x80000000 (Ist 512MB - Cached)
+
+NOTE: APP_CACHED_DATA_BLK1_MEM is used to route sections which needs to be in a
+separate section preferably at the end of 512 MB memory.
+For example:
+Frame buffer memory can be less at runtime depending on boards with lesser DDR (as in TDA 12x12 POP boards).
+If the same is routed to APP_CACHED_DATA_MEM section then the linker will
+place the frame buffer before other data section and the other data will fall into
+region outside the DDR in the board. Hence separate section is used!!
+
+NOTE: APP_CACHED_DATA_BLK0_MEM is only used for AM572 with REV1 PRU-ICSS.
+ .. This section will be referenced in the REV1 linker CMD file needed
+ .. by AM3xx and AM4xx. It is (counterintuitively) the final section
+ .. so as to not disturb the preferred section ordering.
+
++-----------------------------+
+| APP_CODE_MEM | 3MB
++-----------------------------+
+| APP_CACHED_DATA_MEM | 20MB
++-----------------------------+
+| APP_CACHED_DATA_BLK1_MEM | 244MB
++-----------------------------+
+| APP_CACHED_DATA_BLK2_MEM | 128MB
++-----------------------------+
+| APP_CACHED_DATA_BLK0_MEM | 1MB
++-----------------------------+
+| NOT USED | Remaining MB
++-----------------------------+
+
+DDR: 0xA0000000 (2nd 512MB - Non-Cached)
++-----------------------------+
+| |
+| APP_UNCACHED_DATA_BLK3_MEM | 2MB
++-----------------------------+
+| NOT USED | Remaining MB
++-----------------------------+
+
+*/
+
+var KB=1024;
+var MB=KB*KB;
+
+var DDR3_ADDR_0;
+var DDR3_ADDR_1;
+
+var APP_CODE_ADDR;
+var APP_CODE_SIZE;
+
+var APP_CACHED_DATA_ADDR;
+var APP_CACHED_DATA_SIZE;
+
+var APP_UNCACHED_DATA_BLK3_ADDR;
+var APP_UNCACHED_DATA_BLK3_SIZE;
+
+var APP_CACHED_DATA_BLK0_ADDR;
+var APP_CACHED_DATA_BLK0_SIZE;
+
+var APP_CACHED_DATA_BLK1_ADDR;
+var APP_CACHED_DATA_BLK1_SIZE;
+
+var APP_CACHED_DATA_BLK2_ADDR;
+var APP_CACHED_DATA_BLK2_SIZE;
+
+/* First 4KB reserved for components such as SBL */
+SBL_SIZE = 4*KB;
+DDR3_ADDR_0 = 0x80000000 + SBL_SIZE;
+DDR3_ADDR_1 = 0xA0000000;
+
+APP_CODE_SIZE = 3*MB - SBL_SIZE;
+APP_CACHED_DATA_SIZE = 20*MB;
+APP_CACHED_DATA_BLK0_SIZE = 1*MB;
+APP_CACHED_DATA_BLK1_SIZE = 244*MB;
+APP_CACHED_DATA_BLK2_SIZE = 128*MB;
+APP_UNCACHED_DATA_BLK3_SIZE = 2*MB;
+
+APP_CODE_ADDR = DDR3_ADDR_0;
+APP_CACHED_DATA_ADDR = APP_CODE_ADDR + APP_CODE_SIZE;
+APP_CACHED_DATA_BLK1_ADDR = APP_CACHED_DATA_ADDR + APP_CACHED_DATA_SIZE;
+APP_CACHED_DATA_BLK2_ADDR = APP_CACHED_DATA_BLK1_ADDR + APP_CACHED_DATA_BLK1_SIZE;
+APP_CACHED_DATA_BLK0_ADDR = APP_CACHED_DATA_BLK2_ADDR + APP_CACHED_DATA_BLK2_SIZE;
+APP_UNCACHED_DATA_BLK3_ADDR = DDR3_ADDR_1;
+
+if (CurrentPlatform == "evmAM572x")
+{
+ myplatform = "ti.platforms.evmAM572X";
+}
+else
+{
+ myplatform = "ti.platforms.idkAM572X";
+}
+
+Build.platformTable[myplatform] =
+{
+ externalMemoryMap:
+ [
+ ["APP_CODE_MEM", {
+ comment : "APP_CODE_MEM",
+ name : "APP_CODE_MEM",
+ base : APP_CODE_ADDR,
+ len : APP_CODE_SIZE
+ }],
+ ["APP_CACHED_DATA_BLK0_MEM", {
+ comment : "APP_CACHED_DATA_BLK0_MEM",
+ name : "APP_CACHED_DATA_BLK0_MEM",
+ base : APP_CACHED_DATA_BLK0_ADDR,
+ len : APP_CACHED_DATA_BLK0_SIZE
+ }],
+ ["APP_CACHED_DATA_MEM", {
+ comment : "APP_CACHED_DATA_MEM",
+ name : "APP_CACHED_DATA_MEM",
+ base : APP_CACHED_DATA_ADDR,
+ len : APP_CACHED_DATA_SIZE
+ }],
+ ["APP_UNCACHED_DATA_BLK3_MEM", {
+ comment : "APP_UNCACHED_DATA_BLK3_MEM",
+ name : "APP_UNCACHED_DATA_BLK3_MEM",
+ base : APP_UNCACHED_DATA_BLK3_ADDR,
+ len : APP_UNCACHED_DATA_BLK3_SIZE
+ }],
+ ["APP_CACHED_DATA_BLK1_MEM", {
+ comment : "APP_CACHED_DATA_BLK1_MEM",
+ name : "APP_CACHED_DATA_BLK1_MEM",
+ base : APP_CACHED_DATA_BLK1_ADDR,
+ len : APP_CACHED_DATA_BLK1_SIZE
+ }],
+ ["APP_CACHED_DATA_BLK2_MEM", {
+ comment : "APP_CACHED_DATA_BLK2_MEM",
+ name : "APP_CACHED_DATA_BLK2_MEM",
+ base : APP_CACHED_DATA_BLK2_ADDR,
+ len : APP_CACHED_DATA_BLK2_SIZE
+ }],
+ ],
+ codeMemory: "APP_CODE_MEM",
+ dataMemory: "APP_CACHED_DATA_MEM",
+ stackMemory: "APP_CACHED_DATA_MEM"
+};
diff --git a/packages/ti/build/am572x/config_am572x_c66.bld b/packages/ti/build/am572x/config_am572x_c66.bld
--- /dev/null
@@ -0,0 +1,167 @@
+/*
+* Copyright (c) 2016, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* * Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* * Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the distribution.
+*
+* * Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+/*
+ * ======== config.bld ========
+ * Sample Build configuration script
+ */
+
+/* load the required modules for the configuration */
+var C66 = xdc.useModule('ti.targets.elf.C66');
+/* C66 compiler directory path */
+C66.rootDir = java.lang.System.getenv("CGTOOLS_DSP");
+
+/* compiler options */
+C66.ccOpts.suffix += " -mi10 -mo ";
+
+var CurrentPlatform = java.lang.System.getenv("BOARD");
+
+/*
+Memory map
+
+DDR: 0x80000000 (Ist 512MB - Cached)
+
+NOTE: APP_CACHED_DATA_BLK1_MEM is used to route sections which needs to be in a
+separate section preferably at the end of 512 MB memory.
+For example:
+Frame buffer memory can be less at runtime depending on boards with lesser DDR (as in TDA 12x12 POP boards).
+If the same is routed to APP_CACHED_DATA_MEM section then the linker will
+place the frame buffer before other data section and the other data will fall into
+region outside the DDR in the board. Hence separate section is used!!
+
++-----------------------------+
+| APP_CODE_MEM | 3MB
++-----------------------------+
+| APP_CACHED_DATA_MEM | 20MB
++-----------------------------+
+| APP_CACHED_DATA_BLK1_MEM | 244MB
++-----------------------------+
+| APP_CACHED_DATA_BLK2_MEM | 128MB
++-----------------------------+
+| NOT USED | Remaining MB
++-----------------------------+
+
+DDR: 0xA0000000 (2nd 512MB - Non-Cached)
++-----------------------------+
+| |
+| APP_UNCACHED_DATA_BLK3_MEM | 2MB
++-----------------------------+
+| NOT USED | Remaining MB
++-----------------------------+
+
+*/
+
+var KB=1024;
+var MB=KB*KB;
+
+var DDR3_ADDR_0;
+var DDR3_ADDR_1;
+
+var APP_CODE_ADDR;
+var APP_CODE_SIZE;
+
+var APP_CACHED_DATA_ADDR;
+var APP_CACHED_DATA_SIZE;
+
+var APP_UNCACHED_DATA_BLK3_ADDR;
+var APP_UNCACHED_DATA_BLK3_SIZE;
+
+var APP_CACHED_DATA_BLK1_ADDR;
+var APP_CACHED_DATA_BLK1_SIZE;
+
+var APP_CACHED_DATA_BLK2_ADDR;
+var APP_CACHED_DATA_BLK2_SIZE;
+
+/* First 4KB reserved for components such as SBL */
+SBL_SIZE = 4*KB;
+DDR3_ADDR_0 = 0x80000000 + SBL_SIZE;
+DDR3_ADDR_1 = 0xA0000000;
+
+APP_CODE_SIZE = 3*MB - SBL_SIZE;
+APP_CACHED_DATA_SIZE = 20*MB;
+APP_CACHED_DATA_BLK1_SIZE = 244*MB;
+APP_CACHED_DATA_BLK2_SIZE = 128*MB;
+APP_UNCACHED_DATA_BLK3_SIZE = 2*MB;
+
+APP_CODE_ADDR = DDR3_ADDR_0;
+APP_CACHED_DATA_ADDR = APP_CODE_ADDR + APP_CODE_SIZE;
+APP_CACHED_DATA_BLK1_ADDR = APP_CACHED_DATA_ADDR + APP_CACHED_DATA_SIZE;
+APP_CACHED_DATA_BLK2_ADDR = APP_CACHED_DATA_BLK1_ADDR + APP_CACHED_DATA_BLK1_SIZE;
+APP_UNCACHED_DATA_BLK3_ADDR = DDR3_ADDR_1;
+
+if (CurrentPlatform == "evmAM572x")
+{
+ myplatform = "ti.platforms.evmAM572X";
+}
+else
+{
+ myplatform = "ti.platforms.idkAM572X";
+}
+
+Build.platformTable[myplatform] =
+{
+ externalMemoryMap:
+ [
+ ["APP_CODE_MEM", {
+ comment : "APP_CODE_MEM",
+ name : "APP_CODE_MEM",
+ base : APP_CODE_ADDR,
+ len : APP_CODE_SIZE
+ }],
+ ["APP_CACHED_DATA_MEM", {
+ comment : "APP_CACHED_DATA_MEM",
+ name : "APP_CACHED_DATA_MEM",
+ base : APP_CACHED_DATA_ADDR,
+ len : APP_CACHED_DATA_SIZE
+ }],
+ ["APP_UNCACHED_DATA_BLK3_MEM", {
+ comment : "APP_UNCACHED_DATA_BLK3_MEM",
+ name : "APP_UNCACHED_DATA_BLK3_MEM",
+ base : APP_UNCACHED_DATA_BLK3_ADDR,
+ len : APP_UNCACHED_DATA_BLK3_SIZE
+ }],
+ ["APP_CACHED_DATA_BLK1_MEM", {
+ comment : "APP_CACHED_DATA_BLK1_MEM",
+ name : "APP_CACHED_DATA_BLK1_MEM",
+ base : APP_CACHED_DATA_BLK1_ADDR,
+ len : APP_CACHED_DATA_BLK1_SIZE
+ }],
+ ["APP_CACHED_DATA_BLK2_MEM", {
+ comment : "APP_CACHED_DATA_BLK2_MEM",
+ name : "APP_CACHED_DATA_BLK2_MEM",
+ base : APP_CACHED_DATA_BLK2_ADDR,
+ len : APP_CACHED_DATA_BLK2_SIZE
+ }],
+ ],
+ codeMemory: "APP_CODE_MEM",
+ dataMemory: "APP_CACHED_DATA_MEM",
+ stackMemory: "APP_CACHED_DATA_MEM"
+};
diff --git a/packages/ti/build/am572x/mem_segment_definition_1024mb_bios.xs b/packages/ti/build/am572x/mem_segment_definition_1024mb_bios.xs
--- /dev/null
@@ -0,0 +1,538 @@
+/*
+* Copyright (c) 2016, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* * Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* * Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the distribution.
+*
+* * Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+/*
+ * ======== mem_segment_definition.xs ========
+ * ======== Single file for the memory map configuration of all cores =========
+ */
+
+var KB=1024;
+var MB=KB*KB;
+
+var DDR3_ADDR;
+var DDR3_SIZE;
+
+var DDR3_BASE_ADDR_0;
+var DDR3_BASE_SIZE_0;
+var DDR3_BASE_ADDR_1;
+var DDR3_BASE_SIZE_1;
+
+var OCMC1_ADDR;
+var OCMC2_ADDR;
+var OCMC3_ADDR;
+
+var OCMC1_SIZE;
+var OCMC2_SIZE;
+var OCMC3_SIZE;
+
+var DSP1_L2_SRAM_ADDR;
+var DSP1_L2_SRAM_SIZE;
+
+var DSP2_L2_SRAM_ADDR;
+var DSP2_L2_SRAM_SIZE;
+
+var EVE1_SRAM_ADDR;
+var EVE1_SRAM_SIZE;
+
+var EVE2_SRAM_ADDR;
+var EVE2_SRAM_SIZE;
+
+var EVE3_SRAM_ADDR;
+var EVE3_SRAM_SIZE;
+
+var EVE4_SRAM_ADDR;
+var EVE4_SRAM_SIZE;
+
+var SR0_ADDR;
+var SR0_SIZE;
+
+var IPU1_1_CODE_ADDR;
+var IPU1_1_CODE_SIZE;
+
+var IPU1_1_DATA_ADDR;
+var IPU1_1_DATA_SIZE;
+
+var IPU1_1_BSS_ADDR;
+var IPU1_1_BSS_SIZE;
+
+var SR1_FRAME_BUFFER_ADDR;
+var SR1_FRAME_BUFFER_SIZE;
+
+var IPU1_0_CODE_ADDR;
+var IPU1_0_CODE_SIZE;
+
+var IPU1_0_DATA_ADDR;
+var IPU1_0_DATA_SIZE;
+
+var IPU1_0_BSS_ADDR;
+var IPU1_0_BSS_SIZE;
+
+var DSP1_CODE_ADDR;
+var DSP1_CODE_SIZE;
+
+var DSP1_DATA_ADDR;
+var DSP1_DATA_SIZE;
+
+var DSP2_CODE_ADDR;
+var DSP2_CODE_SIZE;
+
+var DSP2_DATA_ADDR;
+var DSP2_DATA_SIZE;
+
+var EVE1_CODE_ADDR;
+var EVE1_CODE_SIZE;
+
+var EVE1_DATA_ADDR;
+var EVE1_DATA_SIZE;
+
+var EVE1_VECS_ADDR;
+var EVE1_VECS_SIZE;
+
+var EVE2_CODE_ADDR;
+var EVE2_CODE_SIZE;
+
+var EVE2_DATA_ADDR;
+var EVE2_DATA_SIZE;
+
+var EVE2_VECS_ADDR;
+var EVE2_VECS_SIZE;
+
+var EVE3_CODE_ADDR;
+var EVE3_CODE_SIZE;
+
+var EVE3_DATA_ADDR;
+var EVE3_DATA_SIZE;
+
+var EVE3_VECS_ADDR;
+var EVE3_VECS_SIZE;
+
+var EVE4_CODE_ADDR;
+var EVE4_CODE_SIZE;
+
+var EVE4_DATA_ADDR;
+var EVE4_DATA_SIZE;
+
+var EVE4_VECS_ADDR;
+var EVE4_VECS_SIZE;
+
+var A15_0_CODE_ADDR;
+var A15_0_CODE_SIZE;
+
+var A15_0_DATA_ADDR;
+var A15_0_DATA_SIZE;
+
+var HDVPSS_DESC_ADDR;
+var HDVPSS_DESC_SIZE;
+
+var REMOTE_LOG_ADDR;
+var REMOTE_LOG_SIZE;
+
+DDR3_ADDR = 0x80000000;
+DDR3_SIZE = 1024*MB;
+
+DDR3_BASE_ADDR_0 = 0x80000000;
+DDR3_BASE_SIZE_0 = 512*MB;
+
+/* The start address of the second mem section should be 16MB aligned.
+ * This alignment is a must as a single 16MB mapping is used for EVE
+ * to map SR0, REMOTE_LOG_MEM sections.
+ * tlb_config_eveX.c need to be modified otherwise
+ */
+DDR3_BASE_ADDR_1 = 0xA0000000;
+DDR3_BASE_SIZE_1 = 512*MB;
+
+OCMC1_ADDR = 0x40300000;
+OCMC1_SIZE = 512*KB;
+
+OCMC2_ADDR = 0x40400000;
+OCMC2_SIZE = 1*MB;
+
+OCMC3_ADDR = 0x40500000;
+OCMC3_SIZE = 1*MB;
+
+DSP1_L2_SRAM_ADDR = 0x40800000;
+DSP1_L2_SRAM_SIZE = 288*KB;
+
+DSP2_L2_SRAM_ADDR = 0x41000000;
+DSP2_L2_SRAM_SIZE = 288*KB;
+
+EVE1_SRAM_ADDR = 0x42000000;
+EVE1_SRAM_SIZE = 1*MB;
+
+EVE2_SRAM_ADDR = 0x42100000;
+EVE2_SRAM_SIZE = 1*MB;
+
+EVE3_SRAM_ADDR = 0x42200000;
+EVE3_SRAM_SIZE = 1*MB;
+
+EVE4_SRAM_ADDR = 0x42300000;
+EVE4_SRAM_SIZE = 1*MB;
+
+var TOTAL_MEM_SIZE = (DDR3_SIZE);
+
+/* First 512 MB - cached */
+/* EVE vecs space should be align with 16MB boundary, and if possible try to fit
+ * the entire vecs+code+data in 16MB section. In this case a single TLB map would
+ * be enough to map vecs+code+data of an EVE.
+ * tlb_config_eveX.c need to be modified if any of these EVE memory sections or
+ * SR1_FRAME_BUFFER_MEM section is modified.
+ */
+EVE1_VECS_SIZE = 0.5*MB;
+EVE1_CODE_SIZE = 2*MB;
+EVE1_DATA_SIZE =13.5*MB;
+EVE2_VECS_SIZE = 0.5*MB;
+EVE2_CODE_SIZE = 2*MB;
+EVE2_DATA_SIZE =13.5*MB;
+EVE3_VECS_SIZE = 0.5*MB;
+EVE3_CODE_SIZE = 2*MB;
+EVE3_DATA_SIZE =13.5*MB;
+EVE4_VECS_SIZE = 0.5*MB;
+EVE4_CODE_SIZE = 2*MB;
+EVE4_DATA_SIZE =13.5*MB;
+IPU1_1_CODE_SIZE = 2*MB;
+IPU1_1_BSS_SIZE = 8*MB;
+IPU1_1_DATA_SIZE = 4*MB;
+IPU1_0_CODE_SIZE = 6*MB;
+IPU1_0_BSS_SIZE = 8*MB;
+IPU1_0_DATA_SIZE = 4*MB;
+SR1_FRAME_BUFFER_SIZE = 256*MB;
+DSP1_CODE_SIZE = 2*MB;
+DSP1_DATA_SIZE = 64*MB;
+DSP2_CODE_SIZE = 2*MB;
+DSP2_DATA_SIZE = 64*MB;
+A15_0_CODE_SIZE = 2*MB;
+A15_0_DATA_SIZE = 14*MB;
+
+
+
+/* Second 512 MB - non-cached */
+/* The start address of the second mem section should be 16MB aligned.
+ * This alignment is a must as a single 16MB mapping is used for EVE
+ * to map SR0, EMOTE_LOG_MEM sections.
+ * tlb_config_eveX.c need to be modified otherwise
+ */
+SR0_SIZE = 13*MB;
+REMOTE_LOG_SIZE =1024*KB;
+HDVPSS_DESC_SIZE = 2*MB;
+
+
+/* Cached Section */
+/* EVE vecs space should be align with 16MB boundary, and if possible try to fit
+ * the entire vecs+code+data in 16MB section. In this case a single TLB map would
+ * be enough to map vecs+code+data of an EVE.
+ * tlb_config_eveX.c need to be modified if any of these EVE memory sections or
+ * SR1_FRAME_BUFFER_MEM section is modified.
+ */
+EVE1_VECS_ADDR = DDR3_BASE_ADDR_0;
+EVE1_CODE_ADDR = EVE1_VECS_ADDR + EVE1_VECS_SIZE;
+EVE1_DATA_ADDR = EVE1_CODE_ADDR + EVE1_CODE_SIZE;
+EVE2_VECS_ADDR = EVE1_DATA_ADDR + EVE1_DATA_SIZE;
+EVE2_CODE_ADDR = EVE2_VECS_ADDR + EVE2_VECS_SIZE;
+EVE2_DATA_ADDR = EVE2_CODE_ADDR + EVE2_CODE_SIZE;
+EVE3_VECS_ADDR = EVE2_DATA_ADDR + EVE2_DATA_SIZE;
+EVE3_CODE_ADDR = EVE3_VECS_ADDR + EVE3_VECS_SIZE;
+EVE3_DATA_ADDR = EVE3_CODE_ADDR + EVE3_CODE_SIZE;
+EVE4_VECS_ADDR = EVE3_DATA_ADDR + EVE3_DATA_SIZE;
+EVE4_CODE_ADDR = EVE4_VECS_ADDR + EVE4_VECS_SIZE;
+EVE4_DATA_ADDR = EVE4_CODE_ADDR + EVE4_CODE_SIZE;
+IPU1_1_CODE_ADDR = EVE4_DATA_ADDR + EVE4_DATA_SIZE;
+IPU1_1_DATA_ADDR = IPU1_1_CODE_ADDR + IPU1_1_CODE_SIZE;
+IPU1_1_BSS_ADDR = IPU1_1_DATA_ADDR + IPU1_1_DATA_SIZE;
+IPU1_0_CODE_ADDR = IPU1_1_BSS_ADDR + IPU1_1_BSS_SIZE;
+IPU1_0_DATA_ADDR = IPU1_0_CODE_ADDR + IPU1_0_CODE_SIZE;
+IPU1_0_BSS_ADDR = IPU1_0_DATA_ADDR + IPU1_0_DATA_SIZE;
+SR1_FRAME_BUFFER_ADDR = IPU1_0_BSS_ADDR + IPU1_0_BSS_SIZE;
+DSP1_CODE_ADDR = SR1_FRAME_BUFFER_ADDR + SR1_FRAME_BUFFER_SIZE;
+DSP1_DATA_ADDR = DSP1_CODE_ADDR + DSP1_CODE_SIZE;
+DSP2_CODE_ADDR = DSP1_DATA_ADDR + DSP1_DATA_SIZE;
+DSP2_DATA_ADDR = DSP2_CODE_ADDR + DSP2_CODE_SIZE;
+A15_0_CODE_ADDR = DSP2_DATA_ADDR + DSP2_DATA_SIZE;
+A15_0_DATA_ADDR = A15_0_CODE_ADDR + A15_0_CODE_SIZE;
+
+
+/* Non Cached Section */
+/* The start address of the second mem section should be 16MB aligned.
+ * This alignment is a must as a single 16MB mapping is used for EVE
+ * to map SR0, EMOTE_LOG_MEM sections.
+ * tlb_config_eveX.c need to be modified otherwise
+ */
+SR0_ADDR = DDR3_BASE_ADDR_1;
+REMOTE_LOG_ADDR = SR0_ADDR + SR0_SIZE;
+HDVPSS_DESC_ADDR = REMOTE_LOG_ADDR + REMOTE_LOG_SIZE;
+
+if ((A15_0_DATA_ADDR + A15_0_DATA_SIZE) > (DDR3_BASE_ADDR_0 + DDR3_BASE_SIZE_0))
+{
+ throw xdc.$$XDCException("MEMORY_MAP OVERFLOW ERROR ",
+ "\nRegion End: " + "0x" + java.lang.Long.toHexString(DDR3_BASE_ADDR_0 + DDR3_BASE_SIZE_0) +
+ "\nActual End: " + "0x" + java.lang.Long.toHexString(A15_0_DATA_ADDR + A15_0_DATA_SIZE));
+}
+
+if ((HDVPSS_DESC_ADDR + HDVPSS_DESC_SIZE) > (DDR3_BASE_ADDR_1 + DDR3_BASE_SIZE_1))
+{
+ throw xdc.$$XDCException("MEMORY_MAP OVERFLOW ERROR ",
+ "\nRegion End: " + "0x" + java.lang.Long.toHexString(DDR3_BASE_ADDR_1 + DDR3_BASE_SIZE_1) +
+ "\nActual End: " + "0x" + java.lang.Long.toHexString(HDVPSS_DESC_ADDR + HDVPSS_DESC_SIZE));
+}
+
+if ((DDR3_BASE_SIZE_1 + DDR3_BASE_SIZE_0) > (TOTAL_MEM_SIZE))
+{
+ throw xdc.$$XDCException("MEMORY_MAP EXCEEDS 256mb ERROR ",
+ "\nRegion End: " + "0x" + java.lang.Long.toHexString(DDR3_BASE_SIZE_1 + DDR3_BASE_SIZE_0) +
+ "\nActual End: " + "0x" + java.lang.Long.toHexString(TOTAL_MEM_SIZE));
+}
+
+
+function getMemSegmentDefinition_external(core)
+{
+ var memory = new Array();
+ var index = 0;
+
+ memory[index++] = ["IPU1_1_CODE_MEM", {
+ comment : "IPU1_1_CODE_MEM",
+ name : "IPU1_1_CODE_MEM",
+ base : IPU1_1_CODE_ADDR,
+ len : IPU1_1_CODE_SIZE
+ }];
+ memory[index++] = ["IPU1_1_DATA_MEM", {
+ comment : "IPU1_1_DATA_MEM",
+ name : "IPU1_1_DATA_MEM",
+ base : IPU1_1_DATA_ADDR,
+ len : IPU1_1_DATA_SIZE
+ }];
+ memory[index++] = ["IPU1_1_BSS_MEM", {
+ comment : "IPU1_1_BSS_MEM",
+ name : "IPU1_1_BSS_MEM",
+ base : IPU1_1_BSS_ADDR,
+ len : IPU1_1_BSS_SIZE
+ }];
+ memory[index++] = ["IPU1_0_CODE_MEM", {
+ comment : "IPU1_0_CODE_MEM",
+ name : "IPU1_0_CODE_MEM",
+ base : IPU1_0_CODE_ADDR,
+ len : IPU1_0_CODE_SIZE
+ }];
+ memory[index++] = ["IPU1_0_DATA_MEM", {
+ comment : "IPU1_0_DATA_MEM",
+ name : "IPU1_0_DATA_MEM",
+ base : IPU1_0_DATA_ADDR,
+ len : IPU1_0_DATA_SIZE
+ }];
+ memory[index++] = ["IPU1_0_BSS_MEM", {
+ comment : "IPU1_0_BSS_MEM",
+ name : "IPU1_0_BSS_MEM",
+ base : IPU1_0_BSS_ADDR,
+ len : IPU1_0_BSS_SIZE
+ }];
+ memory[index++] = ["DSP1_CODE_MEM", {
+ comment : "DSP1_CODE_MEM",
+ name : "DSP1_CODE_MEM",
+ base : DSP1_CODE_ADDR,
+ len : DSP1_CODE_SIZE
+ }];
+ memory[index++] = ["DSP1_DATA_MEM", {
+ comment : "DSP1_DATA_MEM",
+ name : "DSP1_DATA_MEM",
+ base : DSP1_DATA_ADDR,
+ len : DSP1_DATA_SIZE
+ }];
+
+ memory[index++] = ["DSP2_CODE_MEM", {
+ comment : "DSP2_CODE_MEM",
+ name : "DSP2_CODE_MEM",
+ base : DSP2_CODE_ADDR,
+ len : DSP2_CODE_SIZE
+ }];
+ memory[index++] = ["DSP2_DATA_MEM", {
+ comment : "DSP2_DATA_MEM",
+ name : "DSP2_DATA_MEM",
+ base : DSP2_DATA_ADDR,
+ len : DSP2_DATA_SIZE
+ }];
+
+ memory[index++] = ["A15_0_CODE_MEM", {
+ comment : "A15_0_CODE_MEM",
+ name : "A15_0_CODE_MEM",
+ base : A15_0_CODE_ADDR,
+ len : A15_0_CODE_SIZE
+ }];
+ memory[index++] = ["A15_0_DATA_MEM", {
+ comment : "A15_0_DATA_MEM",
+ name : "A15_0_DATA_MEM",
+ base : A15_0_DATA_ADDR,
+ len : A15_0_DATA_SIZE
+ }];
+
+
+ memory[index++] = ["EVE1_VECS_MEM", {
+ comment : "EVE1_VECS_MEM",
+ name : "EVE1_VECS_MEM",
+ base : EVE1_VECS_ADDR,
+ len : EVE1_VECS_SIZE
+ }];
+ memory[index++] = ["EVE1_CODE_MEM", {
+ comment : "EVE1_CODE_MEM",
+ name : "EVE1_CODE_MEM",
+ base : EVE1_CODE_ADDR,
+ len : EVE1_CODE_SIZE
+ }];
+ memory[index++] = ["EVE1_DATA_MEM", {
+ comment : "EVE1_DATA_MEM",
+ name : "EVE1_DATA_MEM",
+ base : EVE1_DATA_ADDR,
+ len : EVE1_DATA_SIZE
+ }];
+ memory[index++] = ["EVE2_VECS_MEM", {
+ comment : "EVE2_VECS_MEM",
+ name : "EVE2_VECS_MEM",
+ base : EVE2_VECS_ADDR,
+ len : EVE2_VECS_SIZE
+ }];
+ memory[index++] = ["EVE2_CODE_MEM", {
+ comment : "EVE2_CODE_MEM",
+ name : "EVE2_CODE_MEM",
+ base : EVE2_CODE_ADDR,
+ len : EVE2_CODE_SIZE
+ }];
+ memory[index++] = ["EVE2_DATA_MEM", {
+ comment : "EVE2_DATA_MEM",
+ name : "EVE2_DATA_MEM",
+ base : EVE2_DATA_ADDR,
+ len : EVE2_DATA_SIZE
+ }];
+ memory[index++] = ["EVE3_VECS_MEM", {
+ comment : "EVE3_VECS_MEM",
+ name : "EVE3_VECS_MEM",
+ base : EVE3_VECS_ADDR,
+ len : EVE3_VECS_SIZE
+ }];
+ memory[index++] = ["EVE3_CODE_MEM", {
+ comment : "EVE3_CODE_MEM",
+ name : "EVE3_CODE_MEM",
+ base : EVE3_CODE_ADDR,
+ len : EVE3_CODE_SIZE
+ }];
+ memory[index++] = ["EVE3_DATA_MEM", {
+ comment : "EVE3_DATA_MEM",
+ name : "EVE3_DATA_MEM",
+ base : EVE3_DATA_ADDR,
+ len : EVE3_DATA_SIZE
+ }];
+ memory[index++] = ["EVE4_VECS_MEM", {
+ comment : "EVE4_VECS_MEM",
+ name : "EVE4_VECS_MEM",
+ base : EVE4_VECS_ADDR,
+ len : EVE4_VECS_SIZE
+ }];
+ memory[index++] = ["EVE4_CODE_MEM", {
+ comment : "EVE4_CODE_MEM",
+ name : "EVE4_CODE_MEM",
+ base : EVE4_CODE_ADDR,
+ len : EVE4_CODE_SIZE
+ }];
+ memory[index++] = ["EVE4_DATA_MEM", {
+ comment : "EVE4_DATA_MEM",
+ name : "EVE4_DATA_MEM",
+ base : EVE4_DATA_ADDR,
+ len : EVE4_DATA_SIZE
+ }];
+ memory[index++] = ["SR1_FRAME_BUFFER_MEM", {
+ comment : "SR1_FRAME_BUFFER_MEM",
+ name : "SR1_FRAME_BUFFER_MEM",
+ base : SR1_FRAME_BUFFER_ADDR,
+ len : SR1_FRAME_BUFFER_SIZE
+ }];
+ memory[index++] = ["SR0", {
+ comment : "SR0",
+ name : "SR0",
+ base : SR0_ADDR,
+ len : SR0_SIZE
+ }];
+ memory[index++] = ["HDVPSS_DESC_MEM", {
+ comment : "HDVPSS_DESC_MEM",
+ name : "HDVPSS_DESC_MEM",
+ base : HDVPSS_DESC_ADDR,
+ len : HDVPSS_DESC_SIZE
+ }];
+ memory[index++] = ["REMOTE_LOG_MEM", {
+ comment : "REMOTE_LOG_MEM",
+ name : "REMOTE_LOG_MEM",
+ base : REMOTE_LOG_ADDR,
+ len : REMOTE_LOG_SIZE
+ }];
+
+/* Memory name OCMC_RAM1, 2 & 3 are defined internally in evmDRA7XX platform
+ So no need to specify them explicitly for IPU1, A15
+*/
+ xdc.print("# !!! Core is [" + core + "] !!!" );
+
+ if( core == "c66xdsp_1" ||
+ core == "c66xdsp_2" ||
+ core == "arp32_1" ||
+ core == "arp32_2" ||
+ core == "arp32_3" ||
+ core == "arp32_4"
+ )
+ {
+ memory[index++] = ["OCMC_RAM1", {
+ comment: "OCMC_RAM1",
+ name: "OCMC_RAM1",
+ base: OCMC1_ADDR,
+ len: OCMC1_SIZE
+ }];
+ memory[index++] = ["OCMC_RAM2", {
+ comment: "OCMC_RAM2",
+ name: "OCMC_RAM2",
+ base: OCMC2_ADDR,
+ len: OCMC2_SIZE
+ }];
+ memory[index++] = ["OCMC_RAM3", {
+ comment: "OCMC_RAM3",
+ name: "OCMC_RAM3",
+ base: OCMC3_ADDR,
+ len: OCMC3_SIZE
+ }];
+ }
+ memory[index++] = ["DSP1_L2_SRAM", {
+ comment: "DSP1_L2_SRAM",
+ name: "DSP1_L2_SRAM",
+ base: DSP1_L2_SRAM_ADDR,
+ len: DSP1_L2_SRAM_SIZE
+ }];
+ memory[index++] = ["DSP2_L2_SRAM", {
+ comment: "DSP2_L2_SRAM",
+ name: "DSP2_L2_SRAM",
+ base: DSP2_L2_SRAM_ADDR,
+ len: DSP2_L2_SRAM_SIZE
+ }];
+
+ return (memory);
+}
diff --git a/packages/ti/build/am574x/config_am574x.bld b/packages/ti/build/am574x/config_am574x.bld
--- /dev/null
@@ -0,0 +1,157 @@
+/*
+* Copyright (c) 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* * Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* * Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the distribution.
+*
+* * Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+/*
+ * ======== config.bld ========
+ * Build configuration script for BSP drivers
+ */
+
+/* load the required modules for the configuration */
+var M4 = xdc.useModule('ti.targets.arm.elf.M4');
+/* M4 compiler directory path */
+M4.rootDir = java.lang.System.getenv("CGTOOLS");
+
+var CurrentPlatform = java.lang.System.getenv("BOARD");
+
+/*
+Memory map
+
+DDR: 0x80000000 (Ist 512MB - Cached)
+
+NOTE: APP_CACHED_DATA_BLK1_MEM is used to route sections which needs to be in a
+separate section preferably at the end of 512 MB memory.
+For example:
+Frame buffer memory can be less at runtime depending on boards with lesser DDR (as in TDA 12x12 POP boards).
+If the same is routed to APP_CACHED_DATA_MEM section then the linker will
+place the frame buffer before other data section and the other data will fall into
+region outside the DDR in the board. Hence separate section is used!!
+
++-----------------------------+
+| APP_CODE_MEM | 3MB
++-----------------------------+
+| APP_CACHED_DATA_MEM | 20MB
++-----------------------------+
+| APP_CACHED_DATA_BLK1_MEM | 244MB
++-----------------------------+
+| APP_CACHED_DATA_BLK2_MEM | 128MB
++-----------------------------+
+| NOT USED | Remaining MB
++-----------------------------+
+
+DDR: 0xA0000000 (2nd 512MB - Non-Cached)
++-----------------------------+
+| |
+| APP_UNCACHED_DATA_BLK3_MEM | 2MB
++-----------------------------+
+| NOT USED | Remaining MB
++-----------------------------+
+
+*/
+
+var KB=1024;
+var MB=KB*KB;
+
+var DDR3_ADDR_0;
+var DDR3_ADDR_1;
+
+var APP_CODE_ADDR;
+var APP_CODE_SIZE;
+
+var APP_CACHED_DATA_ADDR;
+var APP_CACHED_DATA_SIZE;
+
+var APP_UNCACHED_DATA_BLK3_ADDR;
+var APP_UNCACHED_DATA_BLK3_SIZE;
+
+var APP_CACHED_DATA_BLK1_ADDR;
+var APP_CACHED_DATA_BLK1_SIZE;
+
+var APP_CACHED_DATA_BLK2_ADDR;
+var APP_CACHED_DATA_BLK2_SIZE;
+
+/* First 4KB reserved for components such as SBL */
+SBL_SIZE = 4*KB;
+DDR3_ADDR_0 = 0x80000000 + SBL_SIZE;
+DDR3_ADDR_1 = 0xA0000000;
+
+APP_CODE_SIZE = 3*MB - SBL_SIZE;
+APP_CACHED_DATA_SIZE = 20*MB;
+APP_CACHED_DATA_BLK1_SIZE = 244*MB;
+APP_CACHED_DATA_BLK2_SIZE = 128*MB;
+APP_UNCACHED_DATA_BLK3_SIZE = 2*MB;
+
+APP_CODE_ADDR = DDR3_ADDR_0;
+APP_CACHED_DATA_ADDR = APP_CODE_ADDR + APP_CODE_SIZE;
+APP_CACHED_DATA_BLK1_ADDR = APP_CACHED_DATA_ADDR + APP_CACHED_DATA_SIZE;
+APP_CACHED_DATA_BLK2_ADDR = APP_CACHED_DATA_BLK1_ADDR + APP_CACHED_DATA_BLK1_SIZE;
+APP_UNCACHED_DATA_BLK3_ADDR = DDR3_ADDR_1;
+
+myplatform = "ti.platforms.idkAM572X";
+
+Build.platformTable[myplatform] =
+{
+ externalMemoryMap:
+ [
+ ["APP_CODE_MEM", {
+ comment : "APP_CODE_MEM",
+ name : "APP_CODE_MEM",
+ base : APP_CODE_ADDR,
+ len : APP_CODE_SIZE
+ }],
+ ["APP_CACHED_DATA_MEM", {
+ comment : "APP_CACHED_DATA_MEM",
+ name : "APP_CACHED_DATA_MEM",
+ base : APP_CACHED_DATA_ADDR,
+ len : APP_CACHED_DATA_SIZE
+ }],
+ ["APP_UNCACHED_DATA_BLK3_MEM", {
+ comment : "APP_UNCACHED_DATA_BLK3_MEM",
+ name : "APP_UNCACHED_DATA_BLK3_MEM",
+ base : APP_UNCACHED_DATA_BLK3_ADDR,
+ len : APP_UNCACHED_DATA_BLK3_SIZE
+ }],
+ ["APP_CACHED_DATA_BLK1_MEM", {
+ comment : "APP_CACHED_DATA_BLK1_MEM",
+ name : "APP_CACHED_DATA_BLK1_MEM",
+ base : APP_CACHED_DATA_BLK1_ADDR,
+ len : APP_CACHED_DATA_BLK1_SIZE
+ }],
+ ["APP_CACHED_DATA_BLK2_MEM", {
+ comment : "APP_CACHED_DATA_BLK2_MEM",
+ name : "APP_CACHED_DATA_BLK2_MEM",
+ base : APP_CACHED_DATA_BLK2_ADDR,
+ len : APP_CACHED_DATA_BLK2_SIZE
+ }],
+ ],
+ codeMemory: "APP_CODE_MEM",
+ dataMemory: "APP_CACHED_DATA_MEM",
+ stackMemory: "APP_CACHED_DATA_MEM"
+};
diff --git a/packages/ti/build/am574x/config_am574x_a15.bld b/packages/ti/build/am574x/config_am574x_a15.bld
--- /dev/null
@@ -0,0 +1,169 @@
+/*
+* Copyright (c) 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* * Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* * Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the distribution.
+*
+* * Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+/*
+ * ======== config_am574x_a15.bld ========
+ * Build configuration script for BSP drivers
+ */
+/* load the required modules for the configuration */
+var A15 = xdc.useModule('gnu.targets.arm.A15F');
+/* A15 compiler directory path */
+A15.rootDir = java.lang.System.getenv("CGTOOLS_A15");
+
+/* Read the current board */
+var CurrentPlatform = java.lang.System.getenv("BOARD");
+
+if (CurrentPlatform == null)
+{
+ /* The env variable is probably not set while running inside CCS */
+ CurrentPlatform = java.lang.System.getProperty("BOARD");
+}
+
+/*add bspLib to support SemiHosting to enable system_printf on A15*/
+/* GCC bare metal targets */
+var gccArmTargets = xdc.loadPackage('gnu.targets.arm');
+gccArmTargets.A15F.bspLib = "rdimon";
+
+/*
+Memory map
+
+DDR: 0x80000000 (Ist 512MB - Cached)
+
+NOTE: APP_CACHED_DATA_BLK1_MEM is used to route sections which needs to be in a
+separate section preferably at the end of 512 MB memory.
+For example:
+Frame buffer memory can be less at runtime depending on boards with lesser DDR (as in TDA 12x12 POP boards).
+If the same is routed to APP_CACHED_DATA_MEM section then the linker will
+place the frame buffer before other data section and the other data will fall into
+region outside the DDR in the board. Hence separate section is used!!
+
++-----------------------------+
+| APP_CODE_MEM | 3MB
++-----------------------------+
+| APP_CACHED_DATA_MEM | 20MB
++-----------------------------+
+| APP_CACHED_DATA_BLK1_MEM | 244MB
++-----------------------------+
+| APP_CACHED_DATA_BLK2_MEM | 128MB
++-----------------------------+
+| NOT USED | Remaining MB
++-----------------------------+
+
+DDR: 0xA0000000 (2nd 512MB - Non-Cached)
++-----------------------------+
+| |
+| APP_UNCACHED_DATA_BLK3_MEM | 2MB
++-----------------------------+
+| NOT USED | Remaining MB
++-----------------------------+
+
+*/
+
+var KB=1024;
+var MB=KB*KB;
+
+var DDR3_ADDR_0;
+var DDR3_ADDR_1;
+
+var APP_CODE_ADDR;
+var APP_CODE_SIZE;
+
+var APP_CACHED_DATA_ADDR;
+var APP_CACHED_DATA_SIZE;
+
+var APP_UNCACHED_DATA_BLK3_ADDR;
+var APP_UNCACHED_DATA_BLK3_SIZE;
+
+var APP_CACHED_DATA_BLK1_ADDR;
+var APP_CACHED_DATA_BLK1_SIZE;
+
+var APP_CACHED_DATA_BLK2_ADDR;
+var APP_CACHED_DATA_BLK2_SIZE;
+
+/* First 4KB reserved for components such as SBL */
+SBL_SIZE = 4*KB;
+DDR3_ADDR_0 = 0x80000000 + SBL_SIZE;
+DDR3_ADDR_1 = 0xA0000000;
+
+APP_CODE_SIZE = 3*MB - SBL_SIZE;
+APP_CACHED_DATA_SIZE = 20*MB;
+APP_CACHED_DATA_BLK1_SIZE = 244*MB;
+APP_CACHED_DATA_BLK2_SIZE = 128*MB;
+APP_UNCACHED_DATA_BLK3_SIZE = 2*MB;
+
+APP_CODE_ADDR = DDR3_ADDR_0;
+APP_CACHED_DATA_ADDR = APP_CODE_ADDR + APP_CODE_SIZE;
+APP_CACHED_DATA_BLK1_ADDR = APP_CACHED_DATA_ADDR + APP_CACHED_DATA_SIZE;
+APP_CACHED_DATA_BLK2_ADDR = APP_CACHED_DATA_BLK1_ADDR + APP_CACHED_DATA_BLK1_SIZE;
+APP_UNCACHED_DATA_BLK3_ADDR = DDR3_ADDR_1;
+
+myplatform = "ti.platforms.idkAM572X";
+
+Build.platformTable[myplatform] =
+{
+ externalMemoryMap:
+ [
+ ["APP_CODE_MEM", {
+ comment : "APP_CODE_MEM",
+ name : "APP_CODE_MEM",
+ base : APP_CODE_ADDR,
+ len : APP_CODE_SIZE
+ }],
+ ["APP_CACHED_DATA_MEM", {
+ comment : "APP_CACHED_DATA_MEM",
+ name : "APP_CACHED_DATA_MEM",
+ base : APP_CACHED_DATA_ADDR,
+ len : APP_CACHED_DATA_SIZE
+ }],
+ ["APP_UNCACHED_DATA_BLK3_MEM", {
+ comment : "APP_UNCACHED_DATA_BLK3_MEM",
+ name : "APP_UNCACHED_DATA_BLK3_MEM",
+ base : APP_UNCACHED_DATA_BLK3_ADDR,
+ len : APP_UNCACHED_DATA_BLK3_SIZE
+ }],
+ ["APP_CACHED_DATA_BLK1_MEM", {
+ comment : "APP_CACHED_DATA_BLK1_MEM",
+ name : "APP_CACHED_DATA_BLK1_MEM",
+ base : APP_CACHED_DATA_BLK1_ADDR,
+ len : APP_CACHED_DATA_BLK1_SIZE
+ }],
+ ["APP_CACHED_DATA_BLK2_MEM", {
+ comment : "APP_CACHED_DATA_BLK2_MEM",
+ name : "APP_CACHED_DATA_BLK2_MEM",
+ base : APP_CACHED_DATA_BLK2_ADDR,
+ len : APP_CACHED_DATA_BLK2_SIZE
+ }],
+ ],
+ codeMemory: "APP_CODE_MEM",
+ dataMemory: "APP_CACHED_DATA_MEM",
+ stackMemory: "APP_CACHED_DATA_MEM"
+};
diff --git a/packages/ti/build/am574x/config_am574x_c66.bld b/packages/ti/build/am574x/config_am574x_c66.bld
--- /dev/null
@@ -0,0 +1,160 @@
+/*
+* Copyright (c) 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* * Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* * Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the distribution.
+*
+* * Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+/*
+ * ======== config.bld ========
+ * Sample Build configuration script
+ */
+
+/* load the required modules for the configuration */
+var C66 = xdc.useModule('ti.targets.elf.C66');
+/* C66 compiler directory path */
+C66.rootDir = java.lang.System.getenv("CGTOOLS_DSP");
+
+/* compiler options */
+C66.ccOpts.suffix += " -mi10 -mo ";
+
+var CurrentPlatform = java.lang.System.getenv("BOARD");
+
+/*
+Memory map
+
+DDR: 0x80000000 (Ist 512MB - Cached)
+
+NOTE: APP_CACHED_DATA_BLK1_MEM is used to route sections which needs to be in a
+separate section preferably at the end of 512 MB memory.
+For example:
+Frame buffer memory can be less at runtime depending on boards with lesser DDR (as in TDA 12x12 POP boards).
+If the same is routed to APP_CACHED_DATA_MEM section then the linker will
+place the frame buffer before other data section and the other data will fall into
+region outside the DDR in the board. Hence separate section is used!!
+
++-----------------------------+
+| APP_CODE_MEM | 3MB
++-----------------------------+
+| APP_CACHED_DATA_MEM | 20MB
++-----------------------------+
+| APP_CACHED_DATA_BLK1_MEM | 244MB
++-----------------------------+
+| APP_CACHED_DATA_BLK2_MEM | 128MB
++-----------------------------+
+| NOT USED | Remaining MB
++-----------------------------+
+
+DDR: 0xA0000000 (2nd 512MB - Non-Cached)
++-----------------------------+
+| |
+| APP_UNCACHED_DATA_BLK3_MEM | 2MB
++-----------------------------+
+| NOT USED | Remaining MB
++-----------------------------+
+
+*/
+
+var KB=1024;
+var MB=KB*KB;
+
+var DDR3_ADDR_0;
+var DDR3_ADDR_1;
+
+var APP_CODE_ADDR;
+var APP_CODE_SIZE;
+
+var APP_CACHED_DATA_ADDR;
+var APP_CACHED_DATA_SIZE;
+
+var APP_UNCACHED_DATA_BLK3_ADDR;
+var APP_UNCACHED_DATA_BLK3_SIZE;
+
+var APP_CACHED_DATA_BLK1_ADDR;
+var APP_CACHED_DATA_BLK1_SIZE;
+
+var APP_CACHED_DATA_BLK2_ADDR;
+var APP_CACHED_DATA_BLK2_SIZE;
+
+/* First 4KB reserved for components such as SBL */
+SBL_SIZE = 4*KB;
+DDR3_ADDR_0 = 0x80000000 + SBL_SIZE;
+DDR3_ADDR_1 = 0xA0000000;
+
+APP_CODE_SIZE = 3*MB - SBL_SIZE;
+APP_CACHED_DATA_SIZE = 20*MB;
+APP_CACHED_DATA_BLK1_SIZE = 244*MB;
+APP_CACHED_DATA_BLK2_SIZE = 128*MB;
+APP_UNCACHED_DATA_BLK3_SIZE = 2*MB;
+
+APP_CODE_ADDR = DDR3_ADDR_0;
+APP_CACHED_DATA_ADDR = APP_CODE_ADDR + APP_CODE_SIZE;
+APP_CACHED_DATA_BLK1_ADDR = APP_CACHED_DATA_ADDR + APP_CACHED_DATA_SIZE;
+APP_CACHED_DATA_BLK2_ADDR = APP_CACHED_DATA_BLK1_ADDR + APP_CACHED_DATA_BLK1_SIZE;
+APP_UNCACHED_DATA_BLK3_ADDR = DDR3_ADDR_1;
+
+myplatform = "ti.platforms.idkAM572X";
+
+Build.platformTable[myplatform] =
+{
+ externalMemoryMap:
+ [
+ ["APP_CODE_MEM", {
+ comment : "APP_CODE_MEM",
+ name : "APP_CODE_MEM",
+ base : APP_CODE_ADDR,
+ len : APP_CODE_SIZE
+ }],
+ ["APP_CACHED_DATA_MEM", {
+ comment : "APP_CACHED_DATA_MEM",
+ name : "APP_CACHED_DATA_MEM",
+ base : APP_CACHED_DATA_ADDR,
+ len : APP_CACHED_DATA_SIZE
+ }],
+ ["APP_UNCACHED_DATA_BLK3_MEM", {
+ comment : "APP_UNCACHED_DATA_BLK3_MEM",
+ name : "APP_UNCACHED_DATA_BLK3_MEM",
+ base : APP_UNCACHED_DATA_BLK3_ADDR,
+ len : APP_UNCACHED_DATA_BLK3_SIZE
+ }],
+ ["APP_CACHED_DATA_BLK1_MEM", {
+ comment : "APP_CACHED_DATA_BLK1_MEM",
+ name : "APP_CACHED_DATA_BLK1_MEM",
+ base : APP_CACHED_DATA_BLK1_ADDR,
+ len : APP_CACHED_DATA_BLK1_SIZE
+ }],
+ ["APP_CACHED_DATA_BLK2_MEM", {
+ comment : "APP_CACHED_DATA_BLK2_MEM",
+ name : "APP_CACHED_DATA_BLK2_MEM",
+ base : APP_CACHED_DATA_BLK2_ADDR,
+ len : APP_CACHED_DATA_BLK2_SIZE
+ }],
+ ],
+ codeMemory: "APP_CODE_MEM",
+ dataMemory: "APP_CACHED_DATA_MEM",
+ stackMemory: "APP_CACHED_DATA_MEM"
+};
diff --git a/packages/ti/build/am574x/mem_segment_definition_1024mb_bios.xs b/packages/ti/build/am574x/mem_segment_definition_1024mb_bios.xs
--- /dev/null
@@ -0,0 +1,261 @@
+/*
+* Copyright (c) 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* * Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* * Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the distribution.
+*
+* * Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+/*
+ * ======== mem_segment_definition.xs ========
+ * ======== Single file for the memory map configuration of all cores =========
+ */
+
+KB=1024;
+MB=KB*KB;
+
+DDR3_ADDR = 0x80000000;
+DDR3_SIZE = 1024*MB;
+
+DDR3_BASE_ADDR_0 = 0x80000000;
+DDR3_BASE_SIZE_0 = 512*MB;
+
+/* The start address of the second mem section should be 16MB aligned.
+ * for REMOTE_LOG_MEM sections.
+ * tlb_config_eveX.c need to be modified otherwise
+ */
+DDR3_BASE_ADDR_1 = 0xA0000000;
+DDR3_BASE_SIZE_1 = 512*MB;
+
+OCMC1_ADDR = 0x40300000;
+OCMC1_SIZE = 512*KB;
+
+DSP1_L2_SRAM_ADDR = 0x40800000;
+DSP1_L2_SRAM_SIZE = 288*KB;
+
+TOTAL_MEM_SIZE = (DDR3_SIZE);
+
+/* First 512 MB - cached */
+/* EVE vecs space should be align with 16MB boundary, and if possible try to fit
+ * the entire vecs+code+data in 16MB section.
+ * tlb_config_eveX.c need to be modified if any of these EVE memory sections or
+ * SR1_FRAME_BUFFER_MEM section is modified.
+ */
+IPU1_1_CODE_SIZE = 2*MB;
+IPU1_1_BSS_SIZE = 6*MB;
+IPU1_1_DATA_SIZE = 4*MB;
+IPU1_0_CODE_SIZE = 6*MB;
+IPU1_0_BSS_SIZE = 10*MB;
+IPU1_0_DATA_SIZE = 4*MB;
+SR1_FRAME_BUFFER_SIZE = 256*MB;
+DSP1_CODE_SIZE = 2*MB;
+DSP1_DATA_SIZE = 64*MB;
+/* A15_0_CODE_SIZE reduced since it is not used in .bld file.
+ * Check .bld for details. Originally 2 + 14 MB.
+ */
+A15_0_NDK_DATA_SIZE = 4*MB;
+A15_0_DATA_SIZE = 16*MB - A15_0_NDK_DATA_SIZE;
+
+
+
+/* Second 512 MB - non-cached */
+/* The start address of the second mem section should be 16MB aligned.
+ * This alignment is a must as a single 16MB mapping is used for EMOTE_LOG_MEM sections.
+ * tlb_config_eveX.c need to be modified otherwise
+ */
+REMOTE_LOG_SIZE = 160*KB;
+SYSTEM_IPC_SHM_SIZE = 224*KB;
+LINK_STATS_SIZE = 256*KB;
+HDVPSS_DESC_SIZE = 1024*KB;
+SR0_SIZE = 128*KB;
+
+
+/* Cached Section */
+/* EVE vecs space should be align with 16MB boundary, and if possible try to fit
+ * the entire vecs+code+data in 16MB section.
+ * SR1_FRAME_BUFFER_MEM section is modified.
+ */
+IPU1_1_CODE_ADDR = DDR3_BASE_ADDR_0;
+IPU1_1_DATA_ADDR = IPU1_1_CODE_ADDR + IPU1_1_CODE_SIZE;
+IPU1_1_BSS_ADDR = IPU1_1_DATA_ADDR + IPU1_1_DATA_SIZE;
+IPU1_0_CODE_ADDR = IPU1_1_BSS_ADDR + IPU1_1_BSS_SIZE;
+IPU1_0_DATA_ADDR = IPU1_0_CODE_ADDR + IPU1_0_CODE_SIZE;
+IPU1_0_BSS_ADDR = IPU1_0_DATA_ADDR + IPU1_0_DATA_SIZE;
+SR1_FRAME_BUFFER_ADDR = IPU1_0_BSS_ADDR + IPU1_0_BSS_SIZE;
+DSP1_CODE_ADDR = SR1_FRAME_BUFFER_ADDR + SR1_FRAME_BUFFER_SIZE;
+DSP1_DATA_ADDR = DSP1_CODE_ADDR + DSP1_CODE_SIZE;
+A15_0_NDK_DATA_ADDR = DSP1_DATA_ADDR + DSP1_DATA_SIZE;
+A15_0_DATA_ADDR = A15_0_NDK_DATA_ADDR + A15_0_NDK_DATA_SIZE;
+
+
+/* Non Cached Section */
+/* The start address of the second mem section should be 16MB aligned.
+ * This alignment is a must as a single 16MB mapping is used for EMOTE_LOG_MEM sections.
+ * tlb_config_eveX.c need to be modified otherwise
+ */
+SR0_ADDR = DDR3_BASE_ADDR_1;
+REMOTE_LOG_ADDR = SR0_ADDR + SR0_SIZE;
+LINK_STATS_ADDR = REMOTE_LOG_ADDR + REMOTE_LOG_SIZE;
+SYSTEM_IPC_SHM_ADDR = LINK_STATS_ADDR + LINK_STATS_SIZE;
+HDVPSS_DESC_ADDR = SYSTEM_IPC_SHM_ADDR + SYSTEM_IPC_SHM_SIZE;
+
+if ((A15_0_DATA_ADDR + A15_0_DATA_SIZE) > (DDR3_BASE_ADDR_0 + DDR3_BASE_SIZE_0))
+{
+ throw xdc.$$XDCException("MEMORY_MAP OVERFLOW ERROR ",
+ "\nRegion End: " + "0x" + java.lang.Long.toHexString(DDR3_BASE_ADDR_0 + DDR3_BASE_SIZE_0) +
+ "\nActual End: " + "0x" + java.lang.Long.toHexString(A15_0_DATA_ADDR + A15_0_DATA_SIZE));
+}
+
+if ((HDVPSS_DESC_ADDR + HDVPSS_DESC_SIZE) > (DDR3_BASE_ADDR_1 + DDR3_BASE_SIZE_1))
+{
+ throw xdc.$$XDCException("MEMORY_MAP OVERFLOW ERROR ",
+ "\nRegion End: " + "0x" + java.lang.Long.toHexString(DDR3_BASE_ADDR_1 + DDR3_BASE_SIZE_1) +
+ "\nActual End: " + "0x" + java.lang.Long.toHexString(HDVPSS_DESC_ADDR + HDVPSS_DESC_SIZE));
+}
+
+if ((DDR3_BASE_SIZE_1 + DDR3_BASE_SIZE_0) > (TOTAL_MEM_SIZE))
+{
+ throw xdc.$$XDCException("MEMORY_MAP EXCEEDS DDR SIZE ERROR ",
+ "\nRegion End: " + "0x" + java.lang.Long.toHexString(DDR3_BASE_SIZE_1 + DDR3_BASE_SIZE_0) +
+ "\nActual End: " + "0x" + java.lang.Long.toHexString(TOTAL_MEM_SIZE));
+}
+
+
+function getMemSegmentDefinition_external(core)
+{
+ var memory = new Array();
+ var index = 0;
+
+ memory[index++] = ["IPU1_1_CODE_MEM", {
+ comment : "IPU1_1_CODE_MEM",
+ name : "IPU1_1_CODE_MEM",
+ base : IPU1_1_CODE_ADDR,
+ len : IPU1_1_CODE_SIZE
+ }];
+ memory[index++] = ["IPU1_1_DATA_MEM", {
+ comment : "IPU1_1_DATA_MEM",
+ name : "IPU1_1_DATA_MEM",
+ base : IPU1_1_DATA_ADDR,
+ len : IPU1_1_DATA_SIZE
+ }];
+ memory[index++] = ["IPU1_1_BSS_MEM", {
+ comment : "IPU1_1_BSS_MEM",
+ name : "IPU1_1_BSS_MEM",
+ base : IPU1_1_BSS_ADDR,
+ len : IPU1_1_BSS_SIZE
+ }];
+ memory[index++] = ["IPU1_0_CODE_MEM", {
+ comment : "IPU1_0_CODE_MEM",
+ name : "IPU1_0_CODE_MEM",
+ base : IPU1_0_CODE_ADDR,
+ len : IPU1_0_CODE_SIZE
+ }];
+ memory[index++] = ["IPU1_0_DATA_MEM", {
+ comment : "IPU1_0_DATA_MEM",
+ name : "IPU1_0_DATA_MEM",
+ base : IPU1_0_DATA_ADDR,
+ len : IPU1_0_DATA_SIZE
+ }];
+ memory[index++] = ["IPU1_0_BSS_MEM", {
+ comment : "IPU1_0_BSS_MEM",
+ name : "IPU1_0_BSS_MEM",
+ base : IPU1_0_BSS_ADDR,
+ len : IPU1_0_BSS_SIZE
+ }];
+ memory[index++] = ["DSP1_CODE_MEM", {
+ comment : "DSP1_CODE_MEM",
+ name : "DSP1_CODE_MEM",
+ base : DSP1_CODE_ADDR,
+ len : DSP1_CODE_SIZE
+ }];
+ memory[index++] = ["DSP1_DATA_MEM", {
+ comment : "DSP1_DATA_MEM",
+ name : "DSP1_DATA_MEM",
+ base : DSP1_DATA_ADDR,
+ len : DSP1_DATA_SIZE
+ }];
+
+ memory[index++] = ["A15_0_NDK_MEM", {
+ comment : "A15_0_NDK_MEM",
+ name : "A15_0_NDK_MEM",
+ base : A15_0_NDK_DATA_ADDR,
+ len : A15_0_NDK_DATA_SIZE
+ }];
+ memory[index++] = ["A15_0_DATA_MEM", {
+ comment : "A15_0_DATA_MEM",
+ name : "A15_0_DATA_MEM",
+ base : A15_0_DATA_ADDR,
+ len : A15_0_DATA_SIZE
+ }];
+ memory[index++] = ["SR1_FRAME_BUFFER_MEM", {
+ comment : "SR1_FRAME_BUFFER_MEM",
+ name : "SR1_FRAME_BUFFER_MEM",
+ base : SR1_FRAME_BUFFER_ADDR,
+ len : SR1_FRAME_BUFFER_SIZE
+ }];
+ memory[index++] = ["SR0", {
+ comment : "SR0",
+ name : "SR0",
+ base : SR0_ADDR,
+ len : SR0_SIZE
+ }];
+ memory[index++] = ["HDVPSS_DESC_MEM", {
+ comment : "HDVPSS_DESC_MEM",
+ name : "HDVPSS_DESC_MEM",
+ base : HDVPSS_DESC_ADDR,
+ len : HDVPSS_DESC_SIZE
+ }];
+ memory[index++] = ["REMOTE_LOG_MEM", {
+ comment : "REMOTE_LOG_MEM",
+ name : "REMOTE_LOG_MEM",
+ base : REMOTE_LOG_ADDR,
+ len : REMOTE_LOG_SIZE
+ }];
+ memory[index++] = ["LINK_STATS_MEM", {
+ comment : "LINK_STATS_MEM",
+ name : "LINK_STATS_MEM",
+ base : LINK_STATS_ADDR,
+ len : LINK_STATS_SIZE
+ }];
+ memory[index++] = ["SYSTEM_IPC_SHM_MEM", {
+ comment : "SYSTEM_IPC_SHM_MEM",
+ name : "SYSTEM_IPC_SHM_MEM",
+ base : SYSTEM_IPC_SHM_ADDR,
+ len : SYSTEM_IPC_SHM_SIZE
+ }];
+
+ xdc.print("# !!! Core is [" + core + "] !!!" );
+
+ memory[index++] = ["DSP1_L2_SRAM", {
+ comment: "DSP1_L2_SRAM",
+ name: "DSP1_L2_SRAM",
+ base: DSP1_L2_SRAM_ADDR,
+ len: DSP1_L2_SRAM_SIZE
+ }];
+
+ return (memory);
+}
diff --git a/packages/ti/build/am64x/config_am64x_a53.bld b/packages/ti/build/am64x/config_am64x_a53.bld
--- /dev/null
@@ -0,0 +1,42 @@
+/*
+* Copyright (c) 2019, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* * Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* * Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the distribution.
+*
+* * Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+/*
+ * ======== config_am64x_a53.bld ========
+ * Common build configuration script for BIOS
+ */
+
+var gccArmTargets = xdc.loadPackage('gnu.targets.arm');
+gccArmTargets.A53F.rootDir = java.lang.System.getenv("CGTOOLS_A53");
+gccArmTargets.A53F.bspLib = "rdimon";
+
+Build.targets = [ gccArmTargets.A53F ];
diff --git a/packages/ti/build/am64x/config_am64x_r5f.bld b/packages/ti/build/am64x/config_am64x_r5f.bld
--- /dev/null
@@ -0,0 +1,40 @@
+/*
+* Copyright (c) 2019, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* * Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* * Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the distribution.
+*
+* * Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+/*
+ * ======== config_am64x_r5.bld ========
+ * Build configuration script for BSP drivers
+ */
+/* load the required modules for the configuration */
+var R5F = xdc.useModule('ti.targets.arm.elf.R5F');
+/* R5F compiler directory path */
+R5F.rootDir = java.lang.System.getenv("CGTOOLS");
diff --git a/packages/ti/build/am64x/linker_a53.lds b/packages/ti/build/am64x/linker_a53.lds
--- /dev/null
@@ -0,0 +1,197 @@
+__STACK_SIZE = 0x20000;
+__TI_STACK_SIZE = __STACK_SIZE;
+
+MEMORY
+{
+ OCMCRAM : ORIGIN = 0x000041C00000, LENGTH = 0x00080000 /* MCUSS-OCMC RAM - 512KB */
+
+
+ DDR_MPU1 (RWX) : ORIGIN = 0x80000000, LENGTH = 0x08000000
+ DDR_IPC (RWX) : ORIGIN = 0x90000000, LENGTH = 0x02000000
+
+ /* am64x MCMS3 locations */
+ /* am64x Reserved Memory for ARM Trusted Firmware */
+ MSMC3_ARM_FW (RWIX) : ORIGIN = 0x000070000000, LENGTH = 0x40000 /* 256KB */
+ BOOTVECTOR : ORIGIN = 0x000070040000, LENGTH = 0x1000 /* 4KB */
+ BOOTVECTOR_EL3 : ORIGIN = 0x000070041000, LENGTH = 0x1000 /* 4KB */
+ MSMC_MPU1 (RWX) : ORIGIN = 0x000070042000, LENGTH = 0x7AE000 /* 7864KB */
+ /* am64x Reserved Memory for DMSC Firmware */
+ MSMC3_DMSC_FW (RWIX) : ORIGIN = 0x0000707F0000, LENGTH = 0x10000 /* 64KB */
+}
+REGION_ALIAS("REGION_TEXT_EL3", DDR_MPU1);
+REGION_ALIAS("REGION_TEXT", DDR_MPU1);
+REGION_ALIAS("REGION_BSS", DDR_MPU1);
+REGION_ALIAS("REGION_DATA", DDR_MPU1);
+REGION_ALIAS("REGION_STACK", DDR_MPU1);
+REGION_ALIAS("REGION_HEAP", DDR_MPU1);
+REGION_ALIAS("REGION_ARM_EXIDX", DDR_MPU1);
+REGION_ALIAS("REGION_ARM_EXTAB", DDR_MPU1);
+REGION_ALIAS("REGION_TEXT_STARTUP", DDR_MPU1);
+REGION_ALIAS("REGION_DATA_BUFFER", DDR_MPU1);
+REGION_ALIAS("IPC_DATA_BUFFER_1", DDR_MPU1);
+
+SECTIONS {
+
+ .vecs : {
+ *(.vecs)
+ } > BOOTVECTOR AT> BOOTVECTOR
+
+ .vectors : {
+ *(.vectors)
+ } > BOOTVECTOR_EL3 AT> BOOTVECTOR_EL3
+ .text.el3 : {
+ *(.text.el3)
+ /* Ensure 8-byte alignment for descriptors and ensure inclusion */
+ . = ALIGN(8);
+ __RT_SVC_DESCS_START__ = .;
+ KEEP(*(rt_svc_descs))
+ __RT_SVC_DESCS_END__ = .;
+ } > REGION_TEXT_EL3 AT> REGION_TEXT_EL3
+
+ .text.csl_a72_startup : {
+ *(.text.csl_a72_startup)
+ *(.Entry)
+ } > REGION_TEXT_STARTUP AT> REGION_TEXT_STARTUP
+
+ .text : {
+ CREATE_OBJECT_SYMBOLS
+ *(.text)
+ *(.text.*)
+ . = ALIGN(0x8);
+ KEEP (*(.ctors))
+ . = ALIGN(0x4);
+ KEEP (*(.dtors))
+ . = ALIGN(0x8);
+ __init_array_start = .;
+ KEEP (*(.init_array*))
+ __init_array_end = .;
+ *(.init)
+ *(.fini*)
+ } > REGION_TEXT AT> REGION_TEXT
+
+ PROVIDE (__etext = .);
+ PROVIDE (_etext = .);
+ PROVIDE (etext = .);
+
+ .rodata : {
+ *(.rodata)
+ *(.rodata*)
+ } > REGION_TEXT AT> REGION_TEXT
+
+ .data_buffer : ALIGN (8) {
+ __data_buffer_load__ = LOADADDR (.data_buffer);
+ __data_buffer_start__ = .;
+ *(.data_buffer)
+ *(.data_buffer*)
+ . = ALIGN (8);
+ __data_buffer_end__ = .;
+ } > REGION_DATA_BUFFER AT> REGION_DATA_BUFFER
+
+ .data : ALIGN (8) {
+ __data_load__ = LOADADDR (.data);
+ __data_start__ = .;
+ *(.data)
+ *(.data*)
+ . = ALIGN (8);
+ __data_end__ = .;
+ } > REGION_DATA AT> REGION_TEXT
+
+ .ARM.exidx : {
+ __exidx_start = .;
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ __exidx_end = .;
+ } > REGION_ARM_EXIDX AT> REGION_ARM_EXIDX
+
+ .ARM.extab : {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > REGION_ARM_EXTAB AT> REGION_ARM_EXTAB
+
+ .bss:extMemCache:ramdisk : {
+ } > DDR_MPU1 /* MSMC_MPU1 */
+
+ /* USB or any other LLD buffer for benchmarking */
+ .benchmark_buffer (NOLOAD) : ALIGN (32) {
+ } > DDR_MPU1
+
+ .bss:frameBuffer (NOLOAD) : ALIGN (32) {
+ } > DDR_MPU1
+
+ ipc_data_buffer (NOLOAD) : ALIGN (32) {
+ } > IPC_DATA_BUFFER_1
+
+ /* For NDK packet memory, we need to map this sections before .bss*/
+ .bss:NDK_PACKETMEM (NOLOAD) : ALIGN (128) {} > DDR_MPU1
+ .bss:NDK_MMBUFFER (NOLOAD) : ALIGN (128) {} > DDR_MPU1
+
+ .bss : {
+ __bss_start__ = .;
+ *(.shbss)
+ *(.bss)
+ *(.bss.*)
+ . = ALIGN (8);
+ __bss_end__ = .;
+ . = ALIGN (8);
+ *(COMMON)
+ } > REGION_BSS AT> REGION_BSS
+
+ .heap : {
+ __heap_start__ = .;
+ end = __heap_start__;
+ _end = end;
+ __end = end;
+ KEEP(*(.heap))
+ __heap_end__ = .;
+ __HeapLimit = __heap_end__;
+ } > REGION_HEAP AT> REGION_HEAP
+
+ .stack (NOLOAD) : ALIGN(16) {
+ _stack = .;
+ __stack = .;
+ KEEP(*(.stack))
+ } > REGION_STACK AT> REGION_STACK
+
+ __TI_STACK_BASE = __stack;
+
+ /* Stabs debugging sections. */
+ .stab 0 : { *(.stab) }
+ .stabstr 0 : { *(.stabstr) }
+ .stab.excl 0 : { *(.stab.excl) }
+ .stab.exclstr 0 : { *(.stab.exclstr) }
+ .stab.index 0 : { *(.stab.index) }
+ .stab.indexstr 0 : { *(.stab.indexstr) }
+ .comment 0 : { *(.comment) }
+ /*
+ * DWARF debug sections.
+ * Symbols in the DWARF debugging sections are relative to the beginning
+ * of the section so we begin them at 0.
+ */
+ /* DWARF 1 */
+ .debug 0 : { *(.debug) }
+ .line 0 : { *(.line) }
+ /* GNU DWARF 1 extensions */
+ .debug_srcinfo 0 : { *(.debug_srcinfo) }
+ .debug_sfnames 0 : { *(.debug_sfnames) }
+ /* DWARF 1.1 and DWARF 2 */
+ .debug_aranges 0 : { *(.debug_aranges) }
+ .debug_pubnames 0 : { *(.debug_pubnames) }
+ /* DWARF 2 */
+ .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
+ .debug_abbrev 0 : { *(.debug_abbrev) }
+ .debug_line 0 : { *(.debug_line .debug_line.* .debug_line_end ) }
+ .debug_frame 0 : { *(.debug_frame) }
+ .debug_str 0 : { *(.debug_str) }
+ .debug_loc 0 : { *(.debug_loc) }
+ .debug_macinfo 0 : { *(.debug_macinfo) }
+ /* SGI/MIPS DWARF 2 extensions */
+ .debug_weaknames 0 : { *(.debug_weaknames) }
+ .debug_funcnames 0 : { *(.debug_funcnames) }
+ .debug_typenames 0 : { *(.debug_typenames) }
+ .debug_varnames 0 : { *(.debug_varnames) }
+ /* DWARF 3 */
+ .debug_pubtypes 0 : { *(.debug_pubtypes) }
+ .debug_ranges 0 : { *(.debug_ranges) }
+ /* DWARF Extension. */
+ .debug_macro 0 : { *(.debug_macro) }
+ .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }
+ /DISCARD/ : { *(.note.GNU-stack) *(.gnu_debuglink) *(.gnu.lto_*) }
+}
diff --git a/packages/ti/build/am64x/linker_r5.lds b/packages/ti/build/am64x/linker_r5.lds
--- /dev/null
@@ -0,0 +1,97 @@
+/* Linker Settings */
+--retain="*(.bootCode)"
+--retain="*(.startupCode)"
+--retain="*(.startupData)"
+--retain="*(.intvecs)"
+--retain="*(.intc_text)"
+--retain="*(.rstvectors)"
+--retain="*(.irqStack)"
+--retain="*(.fiqStack)"
+--retain="*(.abortStack)"
+--retain="*(.undStack)"
+--retain="*(.svcStack)"
+--fill_value=0
+--stack_size=0x2000
+--heap_size=0x1000
+--entry_point=_resetvectors /* Default C RTS boot.asm */
+
+-stack 0x2000 /* SOFTWARE STACK SIZE */
+-heap 0x2000 /* HEAP AREA SIZE */
+
+/* Stack Sizes for various modes */
+__IRQ_STACK_SIZE = 0x1000;
+__FIQ_STACK_SIZE = 0x1000;
+__ABORT_STACK_SIZE = 0x1000;
+__UND_STACK_SIZE = 0x1000;
+__SVC_STACK_SIZE = 0x1000;
+
+/* Memory Map */
+MEMORY
+{
+ VECTORS (X) : origin=0x41C7F000 length=0x1000
+ /* Reset Vectors base address(RESET_VECTORS) should be 64 bytes aligned */
+ RESET_VECTORS (X) : origin=0x41C00000 length=0x100
+ /* MCU0_R5F_0 local view */
+ MCU0_R5F_TCMA_SBL_RSVD (X) : origin=0x0 length=0x100
+ MCU0_R5F_TCMA (X) : origin=0x100 length=0x8000 - 0x100
+ MCU0_R5F_TCMB0 (RWIX) : origin=0x41010000 length=0x8000
+
+ /* MCU0_R5F_1 SoC view */
+ MCU0_R5F1_ATCM (RWIX) : origin=0x41400000 length=0x8000
+ MCU0_R5F1_BTCM (RWIX) : origin=0x41410000 length=0x8000
+
+ /* MCU0 share locations */
+ OCMRAM (RWIX) : origin=0x41C00100 length=0x80000 - 0x1100 /* ~510KB */
+
+ /* am64x MCMS3 locations */
+ /* am64x Reserved Memory for ARM Trusted Firmware */
+ MSMC3_ARM_FW (RWIX) : origin=0x70000000 length=0x40000 /* 256KB */
+ MSMC3 (RWIX) : origin=0x70040000 length=0x7B0000 /* 8MB - 320KB */
+ /* am64x Reserved Memory for DMSC Firmware */
+ MSMC3_DMSC_FW (RWIX) : origin=0x707F0000 length=0x10000 /* 64KB */
+
+ DDR0 (RWIX) : origin=0x80000000 length=0x80000000 /* 2GB */
+}
+
+/* Section Configuration */
+SECTIONS
+{
+ /* 'intvecs' and 'intc_text' sections shall be placed within */
+ /* a range of +\- 16 MB */
+ .intvecs : {} palign(8) > VECTORS
+ .intc_text : {} palign(8) > VECTORS
+ .rstvectors : {} palign(8) > RESET_VECTORS
+ .bootCode : {} palign(8) > MSMC3
+ .startupCode : {} palign(8) > MSMC3
+ .startupData : {} palign(8) > MSMC3, type = NOINIT
+ .text : {} palign(8) > DDR0
+ .const : {} palign(8) > DDR0
+ .cinit : {} palign(8) > DDR0
+ .pinit : {} palign(8) > DDR0
+ .bss : {} align(4) > DDR0
+ .far : {} align(4) > DDR0
+ .data : {} palign(128) > DDR0
+ .boardcfg_data : {} palign(128) > MSMC3
+ .sysmem : {} > DDR0
+ .data_buffer : {} palign(128) > DDR0
+
+ /* USB or any other LLD buffer for benchmarking */
+ .benchmark_buffer (NOLOAD) {} ALIGN (8) > DDR0
+
+ .stack : {} align(4) > DDR0 (HIGH)
+ .irqStack : {. = . + __IRQ_STACK_SIZE;} align(4) > DDR0 (HIGH)
+ RUN_START(__IRQ_STACK_START)
+ RUN_END(__IRQ_STACK_END)
+ .fiqStack : {. = . + __FIQ_STACK_SIZE;} align(4) > DDR0 (HIGH)
+ RUN_START(__FIQ_STACK_START)
+ RUN_END(__FIQ_STACK_END)
+ .abortStack : {. = . + __ABORT_STACK_SIZE;} align(4) > DDR0 (HIGH)
+ RUN_START(__ABORT_STACK_START)
+ RUN_END(__ABORT_STACK_END)
+ .undStack : {. = . + __UND_STACK_SIZE;} align(4) > DDR0 (HIGH)
+ RUN_START(__UND_STACK_START)
+ RUN_END(__UND_STACK_END)
+ .svcStack : {. = . + __SVC_STACK_SIZE;} align(4) > DDR0 (HIGH)
+ RUN_START(__SVC_STACK_START)
+ RUN_END(__SVC_STACK_END)
+}
diff --git a/packages/ti/build/am64x/linker_r5_sysbios.lds b/packages/ti/build/am64x/linker_r5_sysbios.lds
--- /dev/null
@@ -0,0 +1,37 @@
+/* linker options */
+--fill_value=0
+--stack_size=0x2000
+--heap_size=0x1000
+
+-e __VECS_ENTRY_POINT
+
+MEMORY
+{
+ R5F_TCMA_SBL_RSVD(X): ORIGIN = 0x00000000 , LENGTH = 0x100
+ RESET_VECTORS(X) : ORIGIN = 0x41c40000 , LENGTH = 0x100 /* Bottom 256 KB used by SBL */
+ R5F_TCMB0(RWIX) : ORIGIN = 0x41010000 , LENGTH = 0x00008000
+ DDR0 (RWIX) : ORIGIN = 0x80000000 , LENGTH = 0x80000000
+}
+
+SECTIONS
+{
+ .vecs : {
+ __VECS_ENTRY_POINT = .;
+ } palign(8) > RESET_VECTORS
+ .text_boot {
+ *boot.aer5f<*boot.o*>(.text)
+ } palign(8) > R5F_TCMB0
+ .text:xdc_runtime_Startup_reset__I : {} palign(8) > R5F_TCMB0
+ .text:ti_sysbios_family_arm_v7r_Cache* : {} palign(8) > R5F_TCMB0
+ .text:ti_sysbios_family_arm_MPU* : {} palign(8) > R5F_TCMB0
+
+ .text : {} palign(8) > DDR0
+ .cinit : {} palign(8) > DDR0
+ .bss : {} align(8) > DDR0
+ .far : {} align(8) > DDR0
+ .const : {} palign(8) > DDR0
+ .data : {} palign(128) > DDR0
+ .sysmem : {} align(8) > DDR0
+ .stack : {} align(4) > DDR0
+ .data_buffer: {} palign(128) > DDR0
+}
\ No newline at end of file
diff --git a/packages/ti/build/am64x/r5_mpu.xs b/packages/ti/build/am64x/r5_mpu.xs
--- /dev/null
@@ -0,0 +1,159 @@
+/*
+ * Copyright (c) 2019, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/*
+ * ======== event_MPU.xs ========
+ * MPU Settings for am64x device's Cortex-R5F
+ */
+
+/*
+ * -------------------------------------------------------------------------------------------------------------
+ * | Id | Base Address | Size | En | Cacheable | XN | AccPerm | Mask |
+ * |----|--------------|------|----|-------------------------------------------|----|---------------------|------|
+ * | 0 | 0x00000000 | 4GB | T | uncacheable, Shareable | F | RW at PL 1 & PL 2 | 0x0 |
+ * |----|--------------|------|----|-------------------------------------------|----|---------------------|------|
+ * | 1 | 0 (local TCM)| 32K | T | Write-Back, Write-Allocate, Non-Shareable | F | RW at PL 1 | 0x0 |
+ * |----|--------------|------|----|-------------------------------------------|----|---------------------|------|
+ * | 2 | 0x41000000 | 32K | T | Write-Back, Write-Allocate, Non-Shareable | F | RW at PL 1 | 0x0 |
+ * |----|--------------|------|----|-------------------------------------------|----|---------------------|------|
+ * | 3 | 0x41010000 | 32K | T | Write-Back, Write-Allocate, Non-Shareable | F | RW at PL 1 | 0x0 |
+ * |----|--------------|------|----|-------------------------------------------|----|---------------------|------|
+ * | 4 | 0x41C00000 | 1MB | T | Write-Back, Write-Allocate, Non-Shareable | F | RW at PL 1 | 0x0 |
+ * -------------------------------------------------------------------------------------------------------------
+ * | 5 | 0x70000000 | 8MB | T | MSMC Ram - Cachable | F | RW at PL 1 | 0x0 |
+ * -------------------------------------------------------------------------------------------------------------
+ * | 6 | 0x80000000 | 2GB | T | DDR - Strongly Ordered, Shareable | F | RW at PL 1 & PL 3 | 0x0 |
+ * -------------------------------------------------------------------------------------------------------------
+ * | 7 | 0xAA000000 | 32MB | T | DDR (VRing Buffer) - Uncacheble | F | RW at PL 1 & PL 3 | 0x0 |
+ * |-------------------------------------------------------------------------------------------------------------|
+ */
+
+/*
+ * Note: Marking a region as shareable will cause the region to behave as outer shareable with write through
+ * no write-allocate caching policy irrespective of the actual cache policy set. Therefore, only select
+ * regions that are actually shared outside the R5 CPUSS must be marked as shared.
+ */
+
+var MPU = xdc.useModule('ti.sysbios.family.arm.MPU');
+MPU.enableMPU = true;
+MPU.enableBackgroundRegion = true;
+
+var attrs = new MPU.RegionAttrs();
+MPU.initRegionAttrsMeta(attrs);
+
+/* This entry covers the whole 32 bit memory range
+ Address: 0x00000000-0xffffffff */
+attrs.enable = true;
+attrs.bufferable = false;
+attrs.cacheable = false;
+attrs.shareable = true;
+attrs.noExecute = true;
+attrs.accPerm = 1; /* RW at PL1 */
+attrs.tex = 0;
+attrs.subregionDisableMask = 0;
+MPU.setRegionMeta(0, 0x00000000, MPU.RegionSize_4G, attrs);
+
+/* This entry covers the ATCM mapped to 0 */
+attrs.enable = true;
+attrs.bufferable = true;
+attrs.cacheable = true;
+attrs.shareable = true;
+attrs.noExecute = false;
+attrs.accPerm = 1; /* RW at PL1 */
+attrs.tex = 1;
+attrs.subregionDisableMask = 0;
+MPU.setRegionMeta(1, 0x00000000, MPU.RegionSize_32K, attrs);
+
+/* This entry covers ATCM if mapped to 0x41000000 */
+attrs.enable = true;
+attrs.bufferable = true;
+attrs.cacheable = true;
+attrs.shareable = false;
+attrs.noExecute = false;
+attrs.accPerm = 1; /* RW at PL1 */
+attrs.tex = 1;
+attrs.subregionDisableMask = 0;
+MPU.setRegionMeta(2, 0x41000000, MPU.RegionSize_32K, attrs);
+
+/* This entry covers BTCM if mapped to 0x41010000 */
+attrs.enable = true;
+attrs.bufferable = true;
+attrs.cacheable = true;
+attrs.shareable = false;
+attrs.noExecute = false;
+attrs.accPerm = 1; /* RW at PL1 */
+attrs.tex = 1;
+attrs.subregionDisableMask = 0x0;
+MPU.setRegionMeta(3, 0x41010000, MPU.RegionSize_32K, attrs);
+
+/* This entry covers RAM0 */
+attrs.enable = true;
+attrs.bufferable = true;
+attrs.cacheable = true;
+attrs.shareable = false;
+attrs.noExecute = false;
+attrs.accPerm = 1; /* RW at PL1 */
+attrs.tex = 1;
+attrs.subregionDisableMask = 0;
+MPU.setRegionMeta(4, 0x41C00000, MPU.RegionSize_1M, attrs);
+
+/* This entry covers MSMC SRAM */
+attrs.enable = true;
+attrs.bufferable = true;
+attrs.cacheable = true;
+attrs.shareable = false;
+attrs.noExecute = false;
+attrs.accPerm = 1; /* RW at PL1 */
+attrs.tex = 1;
+attrs.subregionDisableMask = 0;
+MPU.setRegionMeta(5, 0x70000000, MPU.RegionSize_8M, attrs);
+
+/* This entry covers DDR memory */
+attrs.enable = true;
+attrs.bufferable = true;
+attrs.cacheable = true;
+attrs.shareable = false;
+attrs.noExecute = false;
+attrs.accPerm = 0x3; /* RW at PL1 & PL2 */
+attrs.tex = 1;
+attrs.subregionDisableMask = 0;
+MPU.setRegionMeta(6, 0x80000000, MPU.RegionSize_2G, attrs);
+
+/* Ring Buffer uncached.... */
+attrs.enable = true;
+attrs.bufferable = false;
+attrs.cacheable = false;
+attrs.shareable = true;
+attrs.noExecute = true;
+attrs.accPerm = 3; /* RW at PL1 */
+attrs.tex = 0;
+attrs.subregionDisableMask = 0;
+MPU.setRegionMeta(7, 0xAA000000, MPU.RegionSize_32M, attrs);
diff --git a/packages/ti/build/am64x/sbl_mcux_0_dummy_app.rprc b/packages/ti/build/am64x/sbl_mcux_0_dummy_app.rprc
new file mode 100644 (file)
index 0000000..bfd581f
Binary files /dev/null and b/packages/ti/build/am64x/sbl_mcux_0_dummy_app.rprc differ
index 0000000..bfd581f
Binary files /dev/null and b/packages/ti/build/am64x/sbl_mcux_0_dummy_app.rprc differ
diff --git a/packages/ti/build/am64x/sysbios_a53.cfg b/packages/ti/build/am64x/sysbios_a53.cfg
--- /dev/null
@@ -0,0 +1,173 @@
+
+/* =============================================================================
+ * Copyright (c) Texas Instruments Incorporated 2019
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+var Defaults = xdc.useModule('xdc.runtime.Defaults');
+var Diags = xdc.useModule('xdc.runtime.Diags');
+var Error = xdc.useModule('xdc.runtime.Error');
+var Log = xdc.useModule('xdc.runtime.Log');
+var LoggerBuf = xdc.useModule('xdc.runtime.LoggerBuf');
+var Main = xdc.useModule('xdc.runtime.Main');
+var Memory = xdc.useModule('xdc.runtime.Memory');
+var System = xdc.useModule('xdc.runtime.System');
+var Text = xdc.useModule('xdc.runtime.Text');
+var Clock = xdc.useModule('ti.sysbios.knl.Clock');
+var Task = xdc.useModule('ti.sysbios.knl.Task');
+var Semaphore = xdc.useModule('ti.sysbios.knl.Semaphore');
+var HeapBuf = xdc.useModule('ti.sysbios.heaps.HeapBuf');
+var GateSwi = xdc.useModule('ti.sysbios.gates.GateSwi');
+
+var BIOS = xdc.useModule('ti.sysbios.BIOS');
+var Hwi = xdc.useModule('ti.sysbios.hal.Hwi');
+var HeapMem = xdc.useModule('ti.sysbios.heaps.HeapMem');
+var SysMin = xdc.useModule('xdc.runtime.SysMin');
+
+var Cache = xdc.module("ti.sysbios.hal.Cache");
+Cache.CacheProxy = xdc.useModule("ti.sysbios.family.arm.v8a.Cache");
+
+var Mmu = xdc.useModule('ti.sysbios.family.arm.v8a.Mmu');
+Mmu.initFunc = "&InitMmu";
+Mmu.tableArrayLen = 24;
+
+/*
+ * Direct CIO to UART
+ */
+/* System.SupportProxy = SysUart; */
+System.SupportProxy = SysMin;
+
+System.extendedFormats += "%f";
+/*
+ * Program.argSize sets the size of the .args section.
+ * The examples don't use command line args so argSize is set to 0.
+ */
+Program.argSize = 0x0;
+
+
+/* System stack size (used by ISRs and Swis) */
+Program.stack = 0x4000;
+
+Task.defaultStackSize = 0x4000;
+/*
+ * Uncomment this line to globally disable Asserts.
+ * All modules inherit the default from the 'Defaults' module. You
+ * can override these defaults on a per-module basis using Module.common$.
+ * Disabling Asserts will save code space and improve runtime performance.
+Defaults.common$.diags_ASSERT = Diags.ALWAYS_OFF;
+ */
+
+/*
+ * Uncomment this line to keep module names from being loaded on the target.
+ * The module name strings are placed in the .const section. Setting this
+ * parameter to false will save space in the .const section. Error and
+ * Assert messages will contain an "unknown module" prefix instead
+ * of the actual module name.
+Defaults.common$.namedModule = false;
+ */
+
+/* Create default heap and hook it into Memory */
+var heapMemParams = new HeapMem.Params;
+heapMemParams.size = 16384*5;
+var heap0 = HeapMem.create(heapMemParams);
+
+Memory.defaultHeapInstance = heap0;
+
+/*
+ * Minimize exit handler array in System. The System module includes
+ * an array of functions that are registered with System_atexit() to be
+ * called by System_exit().
+ */
+System.maxAtexitHandlers = 4;
+
+/*
+ * Uncomment this line to disable the Error print function.
+ * We lose error information when this is disabled since the errors are
+ * not printed. Disabling the raiseHook will save some code space if
+ * your app is not using System_printf() since the Error_print() function
+ * calls System_printf().
+Error.raiseHook = null;
+ */
+
+/*
+ * Uncomment this line to keep Error, Assert, and Log strings from being
+ * loaded on the target. These strings are placed in the .const section.
+ * Setting this parameter to false will save space in the .const section.
+ * Error, Assert and Log message will print raw ids and args instead of
+ * a formatted message.
+Text.isLoaded = false;
+ */
+
+/*
+ * Uncomment this line to disable the output of characters by SysMin
+ * when the program exits. SysMin writes characters to a circular buffer.
+ * This buffer can be viewed using the SysMin Output view in ROV.
+SysMin.flushAtExit = false;
+ */
+
+/*
+ * Create and install logger for the whole system
+ */
+var loggerBufParams = new LoggerBuf.Params();
+loggerBufParams.numEntries = 32;
+var logger0 = LoggerBuf.create(loggerBufParams);
+Defaults.common$.logger = logger0;
+Main.common$.diags_INFO = Diags.ALWAYS_ON;
+
+BIOS.libType = BIOS.LibType_Custom;
+BIOS.cpuFreq.lo = 2000000000;
+BIOS.cpuFreq.hi = 0;
+
+var Timer = xdc.useModule('ti.sysbios.family.arm.v8a.Timer');
+Timer.intFreq.lo = 250000000;
+Timer.intFreq.hi = 0;
+
+var DMTimer = xdc.useModule('ti.sysbios.timers.dmtimer.Timer');
+DMTimer.checkFrequency = false;
+for (var i=0; i < DMTimer.numTimerDevices; i++) {
+ DMTimer.intFreqs[i].lo = 19200000;
+ DMTimer.intFreqs[i].hi = 0;
+}
+
+var Load = xdc.useModule('ti.sysbios.utils.Load');
+
+/* load calculation related settings */
+Load.swiEnabled = true;
+Load.hwiEnabled = true;
+Load.taskEnabled = true;
+Load.updateInIdle = false;
+
+/* Check if application needs to update with custom configuration options */
+/* Caution: This should be at the end of this file after all other common cfg */
+var cfgUpdate = java.lang.System.getenv("XDC_CFG_UPDATE");
+if ((cfgUpdate != '')&&(cfgUpdate != null))
+{
+ xdc.print("Loading configuration update " + cfgUpdate);
+ xdc.loadCapsule(cfgUpdate);
+}
diff --git a/packages/ti/build/am64x/sysbios_r5f.cfg b/packages/ti/build/am64x/sysbios_r5f.cfg
--- /dev/null
@@ -0,0 +1,234 @@
+
+/* =============================================================================
+ * Copyright (c) Texas Instruments Incorporated 2019
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+var Defaults = xdc.useModule('xdc.runtime.Defaults');
+var Diags = xdc.useModule('xdc.runtime.Diags');
+var Error = xdc.useModule('xdc.runtime.Error');
+var Log = xdc.useModule('xdc.runtime.Log');
+var LoggerBuf = xdc.useModule('xdc.runtime.LoggerBuf');
+var Main = xdc.useModule('xdc.runtime.Main');
+var Memory = xdc.useModule('xdc.runtime.Memory')
+var System = xdc.useModule('xdc.runtime.System');
+var Text = xdc.useModule('xdc.runtime.Text');
+var Clock = xdc.useModule('ti.sysbios.knl.Clock');
+var Task = xdc.useModule('ti.sysbios.knl.Task');
+var Semaphore = xdc.useModule('ti.sysbios.knl.Semaphore');
+var HeapBuf = xdc.useModule('ti.sysbios.heaps.HeapBuf');
+var GateSwi = xdc.useModule('ti.sysbios.gates.GateSwi');
+
+var BIOS = xdc.useModule('ti.sysbios.BIOS');
+var Hwi = xdc.useModule('ti.sysbios.family.arm.v7r.keystone3.Hwi');
+var Core = xdc.useModule('ti.sysbios.family.arm.v7r.keystone3.Core');
+var HeapMem = xdc.useModule('ti.sysbios.heaps.HeapMem');
+var SysMin = xdc.useModule('xdc.runtime.SysMin');
+
+/* System stack size (used by ISRs and Swis) */
+Program.stack = 0x2000;
+
+/* Place vector table in separate section - by default this goes to 0x0 which
+ * is reserved by SBL */
+Program.sectMap[".vecs"] = "RESET_VECTORS";
+
+var Task = xdc.useModule('ti.sysbios.knl.Task');
+Task.defaultStackSize = 0x4000;
+Task.common$.namedInstance = true;
+Task.common$.namedModule = true;
+
+/* Enable cache */
+var Cache = xdc.useModule('ti.sysbios.family.arm.v7r.Cache');
+Cache.enableCache = true;
+
+/*
+ * Direct CIO to UART
+ */
+/* System.SupportProxy = SysUart; */
+System.SupportProxy = SysMin;
+System.extendedFormats += "%f";
+/*
+ * Program.argSize sets the size of the .args section.
+ * The examples don't use command line args so argSize is set to 0.
+ */
+Program.argSize = 0x0;
+
+/*
+ * Uncomment this line to globally disable Asserts.
+ * All modules inherit the default from the 'Defaults' module. You
+ * can override these defaults on a per-module basis using Module.common$.
+ * Disabling Asserts will save code space and improve runtime performance.
+Defaults.common$.diags_ASSERT = Diags.ALWAYS_OFF;
+ */
+
+/*
+ * Uncomment this line to keep module names from being loaded on the target.
+ * The module name strings are placed in the .const section. Setting this
+ * parameter to false will save space in the .const section. Error and
+ * Assert messages will contain an "unknown module" prefix instead
+ * of the actual module name.
+Defaults.common$.namedModule = false;
+ */
+
+/* Create default heap and hook it into Memory */
+var heapMemParams = new HeapMem.Params;
+heapMemParams.size = 16384*4;
+var heap0 = HeapMem.create(heapMemParams);
+
+Memory.defaultHeapInstance = heap0;
+
+/*
+ * Minimize exit handler array in System. The System module includes
+ * an array of functions that are registered with System_atexit() to be
+ * called by System_exit().
+ */
+System.maxAtexitHandlers = 4;
+
+/*
+ * Uncomment this line to disable the Error print function.
+ * We lose error information when this is disabled since the errors are
+ * not printed. Disabling the raiseHook will save some code space if
+ * your app is not using System_printf() since the Error_print() function
+ * calls System_printf().
+Error.raiseHook = null;
+ */
+
+/*
+ * Uncomment this line to keep Error, Assert, and Log strings from being
+ * loaded on the target. These strings are placed in the .const section.
+ * Setting this parameter to false will save space in the .const section.
+ * Error, Assert and Log message will print raw ids and args instead of
+ * a formatted message.
+Text.isLoaded = false;
+ */
+
+/*
+ * Uncomment this line to disable the output of characters by SysMin
+ * when the program exits. SysMin writes characters to a circular buffer.
+ * This buffer can be viewed using the SysMin Output view in ROV.
+SysMin.flushAtExit = false;
+ */
+
+/*
+ * Create and install logger for the whole system
+ */
+var loggerBufParams = new LoggerBuf.Params();
+loggerBufParams.numEntries = 32;
+var logger0 = LoggerBuf.create(loggerBufParams);
+Defaults.common$.logger = logger0;
+Main.common$.diags_INFO = Diags.ALWAYS_ON;
+
+BIOS.libType = BIOS.LibType_Custom;
+BIOS.cpuFreq.lo = 1000000000;
+BIOS.cpuFreq.hi = 0;
+
+var coreId = java.lang.System.getenv("CORE");
+
+var DMTimer = xdc.useModule('ti.sysbios.timers.dmtimer.Timer');
+DMTimer.checkFrequency = false;
+for (var i=0; i < DMTimer.numTimerDevices; i++) {
+ DMTimer.intFreqs[i].lo = 19200000;
+ DMTimer.intFreqs[i].hi = 0;
+}
+
+if(coreId=="mcu1_0")
+{
+ Core.id = 0;
+ /* DM timer cfg */
+ Clock.timerId = 1;
+}
+if(coreId=="mcu1_1")
+{
+ Core.id = 1;
+ /* DM timer cfg */
+ Clock.timerId = 2;
+}
+if(coreId=="mcu2_0")
+{
+ Core.id = 0;
+ Clock.timerId = 0;
+ /* DMTimer #12 - in general, address is 0x024x0000 where x is timer # */
+ DMTimer.timerSettings[0].baseAddr = 0x024c0000;
+ DMTimer.timerSettings[0].intNum = 168;
+}
+if(coreId=="mcu2_1")
+{
+ Core.id = 1;
+ Clock.timerId = 1;
+ /* DMTimer #13 - in general, address is 0x024x0000 where x is timer # */
+ DMTimer.timerSettings[1].baseAddr = 0x024d0000;
+ DMTimer.timerSettings[1].intNum = 169;
+}
+if(coreId=="mcu3_0")
+{
+ Core.id = 0;
+ Clock.timerId = 2;
+ /* DMTimer #14 - in general, address is 0x024x0000 where x is timer # */
+ DMTimer.timerSettings[2].baseAddr = 0x024e0000;
+ DMTimer.timerSettings[2].intNum = 170;
+}
+if(coreId=="mcu3_1")
+{
+ Core.id = 1;
+ Clock.timerId = 3;
+ /* DMTimer #15 - in general, address is 0x024x0000 where x is timer # */
+ DMTimer.timerSettings[3].baseAddr = 0x024f0000;
+ DMTimer.timerSettings[3].intNum = 171;
+}
+
+/* Set base address of Vector Interrupt Manager */
+if((coreId=="mcu2_0") || (coreId=="mcu2_1") || (coreId=="mcu3_0") || (coreId=="mcu3_1"))
+{
+ var Hwi = xdc.useModule('ti.sysbios.family.arm.v7r.keystone3.Hwi');
+ Hwi.vimBaseAddress = 0x0ff80000;
+}
+
+/*
+ * Initialize MPU and enable it
+ *
+ * Note: MPU must be enabled and properly configured for caching to work.
+ */
+xdc.loadCapsule("r5_mpu.xs");
+
+var Load = xdc.useModule('ti.sysbios.utils.Load');
+
+/* load calculation related settings */
+Load.swiEnabled = true;
+Load.hwiEnabled = true;
+Load.taskEnabled = true;
+Load.updateInIdle = false;
+
+/* Check if application needs to update with custom configuration options */
+/* Caution: This should be at the end of this file after all other common cfg */
+var cfgUpdate = java.lang.System.getenv("XDC_CFG_UPDATE")
+if ((cfgUpdate != '')&&(cfgUpdate != null))
+{
+ xdc.print("Loading configuration update " + cfgUpdate);
+ xdc.loadCapsule(cfgUpdate);
+}
diff --git a/packages/ti/build/am65xx/config_am65xx_a53.bld b/packages/ti/build/am65xx/config_am65xx_a53.bld
--- /dev/null
@@ -0,0 +1,40 @@
+/*
+* Copyright (c) 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* * Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* * Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the distribution.
+*
+* * Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+/*
+ * ======== config_am65xx_a53.bld ========
+ * Common build configuration script for BIOS
+ */
+/* load the required modules for the configuration */
+var A53F = xdc.useModule('gnu.targets.arm.A53F');
+/* A53F compiler directory path */
+A53F.rootDir = java.lang.System.getenv("CGTOOLS_A53");
diff --git a/packages/ti/build/am65xx/config_am65xx_r5f.bld b/packages/ti/build/am65xx/config_am65xx_r5f.bld
--- /dev/null
@@ -0,0 +1,40 @@
+/*
+* Copyright (c) 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* * Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* * Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the distribution.
+*
+* * Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+/*
+ * ======== config_am65xx_r5.bld ========
+ * Build configuration script for BSP drivers
+ */
+/* load the required modules for the configuration */
+var R5F = xdc.useModule('ti.targets.arm.elf.R5F');
+/* R5F compiler directory path */
+R5F.rootDir = java.lang.System.getenv("CGTOOLS");
diff --git a/packages/ti/build/am65xx/linker_a53.lds b/packages/ti/build/am65xx/linker_a53.lds
--- /dev/null
@@ -0,0 +1,195 @@
+/* File: linker_a53.lds
+ * Semihosting supported gcc Linker script for AM65XX A53 for QT
+ * Purpose: single core A53 C app
+*/
+__STACK_SIZE = 0x10000;
+__TI_STACK_SIZE = __STACK_SIZE;
+
+MEMORY
+{
+ MCU_RESVD : ORIGIN = 0x000041C00000, LENGTH = 0x00060000 /* MCUSS-OCMC RAM RESERVED FOR MCUSS & SOC Boot - 384KB */
+ OCMCRAM : ORIGIN = 0x000041C60000, LENGTH = 0x00020000 /* MCUSS-OCMC RAM - 128KB */
+ BOOTVECTOR : ORIGIN = 0x000070000100, LENGTH = 0x00001000 - 0x100 /* MSMC RAM INIT CODE (4 KB) */
+ MSMC_SRAM : ORIGIN = 0x000070001000, LENGTH = 0xEF000 /* MSMC RAM GENERAL USE */
+ MSMC_SRAM_H : ORIGIN = 0x000070100000, LENGTH = 0xE2000 /* MSMC RAM GENERAL USE - High memory */
+ MSMC_DMSC : ORIGIN = 0x0000701F0000, LENGTH = 0x10000 /* Reserved for DMSC */
+
+ DDR_0 (RWX) : ORIGIN = 0x80000000, LENGTH = 0x10000000
+ DDR_1 (RWX) : ORIGIN = 0x90000000, LENGTH = 0x10000000
+ DDR_2 (RWX) : ORIGIN = 0xA0000000, LENGTH = 0x60000000
+}
+
+REGION_ALIAS("REGION_TEXT", MSMC_SRAM);
+REGION_ALIAS("REGION_BSS", MSMC_SRAM);
+REGION_ALIAS("REGION_DATA", MSMC_SRAM);
+REGION_ALIAS("REGION_STACK", MSMC_SRAM);
+REGION_ALIAS("REGION_HEAP", MSMC_SRAM);
+REGION_ALIAS("REGION_ARM_EXIDX", MSMC_SRAM);
+REGION_ALIAS("REGION_ARM_EXTAB", MSMC_SRAM);
+REGION_ALIAS("REGION_TEXT_STARTUP", MSMC_SRAM);
+REGION_ALIAS("REGION_DATA_BUFFER", DDR_0);
+REGION_ALIAS("REGION_FAR", DDR_0);
+
+SECTIONS {
+
+ .vecs : {
+ *(.vecs)
+ } > BOOTVECTOR AT> BOOTVECTOR
+
+ .text.csl_a53_startup : {
+ *(.text.csl_a53_startup)
+ *(.Entry)
+ } > REGION_TEXT_STARTUP AT> REGION_TEXT_STARTUP
+
+ .text : {
+ CREATE_OBJECT_SYMBOLS
+ *(.text)
+ *(.text.*)
+ . = ALIGN(0x8);
+ KEEP (*(.ctors))
+ . = ALIGN(0x4);
+ KEEP (*(.dtors))
+ . = ALIGN(0x8);
+ __init_array_start = .;
+ KEEP (*(.init_array*))
+ __init_array_end = .;
+ *(.init)
+ *(.fini*)
+ } > REGION_TEXT AT> REGION_TEXT
+
+ PROVIDE (__etext = .);
+ PROVIDE (_etext = .);
+ PROVIDE (etext = .);
+
+ .rodata : {
+ *(.rodata)
+ *(.rodata*)
+ } > REGION_TEXT AT> REGION_TEXT
+
+ .data_buffer : ALIGN (8) {
+ __data_buffer_load__ = LOADADDR (.data_buffer);
+ __data_buffer_start__ = .;
+ *(.data_buffer)
+ *(.data_buffer*)
+ . = ALIGN (8);
+ __data_buffer_end__ = .;
+ } > REGION_DATA_BUFFER AT> REGION_DATA_BUFFER
+
+ .data : ALIGN (8) {
+ __data_load__ = LOADADDR (.data);
+ __data_start__ = .;
+ *(.data)
+ *(.data*)
+ . = ALIGN (8);
+ __data_end__ = .;
+ } > REGION_DATA AT> REGION_TEXT
+
+ .ARM.exidx : {
+ __exidx_start = .;
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ __exidx_end = .;
+ } > REGION_ARM_EXIDX AT> REGION_ARM_EXIDX
+
+ .ARM.extab : {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > REGION_ARM_EXTAB AT> REGION_ARM_EXTAB
+
+ /* usb application ramdisk buffer */
+ .bss:extMemCache:ramdisk (NOLOAD) : ALIGN (32) {
+ } > DDR_0
+
+ /* For NDK packet memory, we need to map this sections before .bss*/
+ .bss:NDK_PACKETMEM (NOLOAD) : ALIGN (128) {} > DDR_0
+ .bss:NDK_MMBUFFER (NOLOAD) : ALIGN (128) {} > DDR_0
+
+ /* USB or any other LLD buffer for benchmarking */
+ .benchmark_buffer (NOLOAD) : ALIGN (32) {
+ } > DDR_0
+
+ /* cal's application buffer */
+ .bss:frameBuffer (NOLOAD) : ALIGN (32) {
+ } > DDR_0
+
+
+ .bss : {
+ __bss_start__ = .;
+ *(.shbss)
+ *(.bss)
+ *(.bss.*)
+ . = ALIGN (8);
+ __bss_end__ = .;
+ . = ALIGN (8);
+ *(COMMON)
+ } > REGION_BSS AT> REGION_BSS
+
+ .far : {
+ __far_start__ = .;
+ *(.far)
+ *(.far:*)
+ *(.far.*)
+ . = ALIGN (8);
+ __far_end__ = .;
+ . = ALIGN (8);
+ } > REGION_FAR AT> REGION_FAR
+
+ .heap : {
+ __heap_start__ = .;
+ end = __heap_start__;
+ _end = end;
+ __end = end;
+ KEEP(*(.heap))
+ __heap_end__ = .;
+ __HeapLimit = __heap_end__;
+ } > REGION_HEAP AT> REGION_HEAP
+
+ .stack (NOLOAD) : ALIGN(16) {
+ _stack = .;
+ __stack = .;
+ KEEP(*(.stack))
+ } > REGION_STACK AT> REGION_STACK
+
+ __TI_STACK_BASE = __stack;
+
+ /* Stabs debugging sections. */
+ .stab 0 : { *(.stab) }
+ .stabstr 0 : { *(.stabstr) }
+ .stab.excl 0 : { *(.stab.excl) }
+ .stab.exclstr 0 : { *(.stab.exclstr) }
+ .stab.index 0 : { *(.stab.index) }
+ .stab.indexstr 0 : { *(.stab.indexstr) }
+ .comment 0 : { *(.comment) }
+ /*
+ * DWARF debug sections.
+ * Symbols in the DWARF debugging sections are relative to the beginning
+ * of the section so we begin them at 0.
+ */
+ /* DWARF 1 */
+ .debug 0 : { *(.debug) }
+ .line 0 : { *(.line) }
+ /* GNU DWARF 1 extensions */
+ .debug_srcinfo 0 : { *(.debug_srcinfo) }
+ .debug_sfnames 0 : { *(.debug_sfnames) }
+ /* DWARF 1.1 and DWARF 2 */
+ .debug_aranges 0 : { *(.debug_aranges) }
+ .debug_pubnames 0 : { *(.debug_pubnames) }
+ /* DWARF 2 */
+ .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
+ .debug_abbrev 0 : { *(.debug_abbrev) }
+ .debug_line 0 : { *(.debug_line .debug_line.* .debug_line_end ) }
+ .debug_frame 0 : { *(.debug_frame) }
+ .debug_str 0 : { *(.debug_str) }
+ .debug_loc 0 : { *(.debug_loc) }
+ .debug_macinfo 0 : { *(.debug_macinfo) }
+ /* SGI/MIPS DWARF 2 extensions */
+ .debug_weaknames 0 : { *(.debug_weaknames) }
+ .debug_funcnames 0 : { *(.debug_funcnames) }
+ .debug_typenames 0 : { *(.debug_typenames) }
+ .debug_varnames 0 : { *(.debug_varnames) }
+ /* DWARF 3 */
+ .debug_pubtypes 0 : { *(.debug_pubtypes) }
+ .debug_ranges 0 : { *(.debug_ranges) }
+ /* DWARF Extension. */
+ .debug_macro 0 : { *(.debug_macro) }
+ .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }
+ /DISCARD/ : { *(.note.GNU-stack) *(.gnu_debuglink) *(.gnu.lto_*) }
+}
diff --git a/packages/ti/build/am65xx/linker_r5.lds b/packages/ti/build/am65xx/linker_r5.lds
--- /dev/null
@@ -0,0 +1,133 @@
+/*----------------------------------------------------------------------------*/
+/* File: k3m4_r5f_linker.cmd */
+/* Description: */
+/* Link command file for AM65XX M4 MCU 0 view */
+/* TI ARM Compiler version 15.12.3 LTS or later */
+/* */
+/* Platform: QT */
+/* (c) Texas Instruments 2017, All rights reserved. */
+/*----------------------------------------------------------------------------*/
+/* History: *'
+/* Aug 26th, 2016 Original version .......................... Loc Truong */
+/* Aug 01th, 2017 new TCM mem map .......................... Loc Truong */
+/* Nov 07th, 2017 Changes for R5F Init Code.................. Vivek Dhande */
+/*----------------------------------------------------------------------------*/
+/* Linker Settings */
+/* Standard linker options */
+--retain="*(.intvecs)"
+--retain="*(.intc_text)"
+--retain="*(.rstvectors)"
+--retain="*(.irqStack)"
+--retain="*(.fiqStack)"
+--retain="*(.abortStack)"
+--retain="*(.undStack)"
+--retain="*(.svcStack)"
+--fill_value=0
+--stack_size=0x2000
+--heap_size=0x1000
+--entry_point=_resetvectors /* Default C RTS boot.asm */
+
+-stack 0x2000 /* SOFTWARE STACK SIZE */
+-heap 0x2000 /* HEAP AREA SIZE */
+
+/* Stack Sizes for various modes */
+__IRQ_STACK_SIZE = 0x1000;
+__FIQ_STACK_SIZE = 0x1000;
+__ABORT_STACK_SIZE = 0x1000;
+__UND_STACK_SIZE = 0x1000;
+__SVC_STACK_SIZE = 0x1000;
+
+/*----------------------------------------------------------------------------*/
+/* Memory Map */
+MEMORY
+{
+ VECTORS (X) : origin=0x41C7F000 length=0x1000
+ /* Reset Vectors base address(RESET_VECTORS) should be 64 bytes aligned */
+ RESET_VECTORS (X) : origin=0x41C00000 length=0x100
+ /* MCU0_R5F_0 local view */
+ MCU0_R5F_TCMA_SBL_RSVD (X) : origin=0x0 length=0x100
+ MCU0_R5F_TCMA (X) : origin=0x100 length=0x8000 - 0x100
+ MCU0_R5F_TCMB0 (RWIX) : origin=0x41010000 length=0x8000
+
+ /* MCU0_R5F_1 SoC view */
+ MCU0_R5F1_ATCM (RWIX) : origin=0x41400000 length=0x8000
+ MCU0_R5F1_BTCM (RWIX) : origin=0x41410000 length=0x8000
+
+ /* Fully avaialble for apps. Used by SBL to load SYSFW */
+ OCMRAM_LOW (RWIX) : origin=0x41C00100 length=0x40600 - 0x100 /* ~257KB */
+
+ /* MCU0 memory used for SBL. Avaiable after boot for app starts for dynamic use */
+ SBL_RESERVED (RWIX) : origin=0x41C40600 length=0x60000 - 0x40600 /* ~126KB */
+
+ /* MCU0 share locations */
+ OCMRAM (RWIX) : origin=0x41C60000 length=0x20000 - 0x1000 /* ~124KB */
+
+
+ /* AM65XX M4 locations */
+ MSMC3 (RWIX) : origin=0x70000000 length=0xF0000 /* 1MB - 64K */
+ MSMC3_H (RWIX) : origin=0x70100000 length=0xE2000 /* 1MB -56K */
+
+ /* Reserved for DMSC */
+ MSMC3_DMSC (RWIX) : origin=0x701F0000 length=0x10000 /* 64K */
+
+ DDR0 (RWIX) : origin=0x80000000 length=0x80000000 /* 2GB */
+
+/* Additional memory settings */
+
+} /* end of MEMORY */
+
+/*----------------------------------------------------------------------------*/
+/* Section Configuration */
+
+SECTIONS
+{
+/* 'intvecs' and 'intc_text' sections shall be placed within */
+/* a range of +\- 16 MB */
+ .intvecs : {} palign(8) > VECTORS
+ .intc_text : {} palign(8) > VECTORS
+ .rstvectors : {} palign(8) > RESET_VECTORS
+ .bootCode : {} palign(8) > MSMC3
+ .startupCode : {} palign(8) > MSMC3
+ .startupData : {} palign(8) > MSMC3, type = NOINIT
+ .text : {} palign(8) > MSMC3
+ .const : {} palign(8) > MSMC3
+ .cinit : {} palign(8) > MSMC3
+ .pinit : {} palign(8) > MSMC3
+ .bss : {} align(4) > MSMC3
+ .far : {} align(4) > DDR0
+ .data : {} palign(128) > MSMC3
+ .boardcfg_data : {} palign(128) > MSMC3
+ .sysmem : {} > MSMC3
+
+ /* USB ram disk dev-msc example */
+ .bss:extMemCache:ramdisk : {} align (32) > DDR0
+
+ /* USB or any other LLD buffer for benchmarking */
+ .benchmark_buffer (NOLOAD) {} ALIGN (8) > DDR0
+
+ .stack : {} align(4) > MSMC3 (HIGH)
+ .irqStack : {. = . + __IRQ_STACK_SIZE;} align(4) > MSMC3 (HIGH)
+ RUN_START(__IRQ_STACK_START)
+ RUN_END(__IRQ_STACK_END)
+ .fiqStack : {. = . + __FIQ_STACK_SIZE;} align(4) > MSMC3 (HIGH)
+ RUN_START(__FIQ_STACK_START)
+ RUN_END(__FIQ_STACK_END)
+ .abortStack : {. = . + __ABORT_STACK_SIZE;} align(4) > MSMC3 (HIGH)
+ RUN_START(__ABORT_STACK_START)
+ RUN_END(__ABORT_STACK_END)
+ .undStack : {. = . + __UND_STACK_SIZE;} align(4) > MSMC3 (HIGH)
+ RUN_START(__UND_STACK_START)
+ RUN_END(__UND_STACK_END)
+ .svcStack : {. = . + __SVC_STACK_SIZE;} align(4) > MSMC3 (HIGH)
+ RUN_START(__SVC_STACK_START)
+ RUN_END(__SVC_STACK_END)
+
+/* Additional sections settings */
+
+} /* end of SECTIONS */
+
+/*----------------------------------------------------------------------------*/
+/* Misc linker settings */
+
+
+/*-------------------------------- END ---------------------------------------*/
diff --git a/packages/ti/build/am65xx/linker_r5_sysbios.lds b/packages/ti/build/am65xx/linker_r5_sysbios.lds
--- /dev/null
@@ -0,0 +1,98 @@
+/*----------------------------------------------------------------------------*/
+/* File: k3m4_r5f_linker.cmd */
+/* Description: */
+/* Link command file for AM65XX M4 MCU 0 view */
+/* TI ARM Compiler version 15.12.3 LTS or later */
+/* */
+/* Platform: QT */
+/* (c) Texas Instruments 2017, All rights reserved. */
+/*----------------------------------------------------------------------------*/
+/* History: *'
+/* Aug 26th, 2016 Original version .......................... Loc Truong */
+/* Aug 01th, 2017 new TCM mem map .......................... Loc Truong */
+/* Nov 07th, 2017 Changes for R5F Init Code.................. Vivek Dhande */
+/*----------------------------------------------------------------------------*/
+/* Linker Settings */
+/* Standard linker options */
+--retain="*(.intvecs)"
+--retain="*(.intc_text)"
+--retain="*(.rstvectors)"
+--fill_value=0
+--entry_point=ti_sysbios_family_arm_v7r_keystone3_Hwi_vectors /* Default BIOS */
+
+/*----------------------------------------------------------------------------*/
+/* Memory Map */
+MEMORY
+{
+ VECTORS (X) : origin=0x41C7F000 length=0x1000
+ /* Reset Vectors base address(RESET_VECTORS) should be 64 bytes aligned */
+ RESET_VECTORS (X) : origin=0x41C00000 length=0x100
+ /* MCU0_R5F_0 local view */
+ MCU0_R5F_TCMA_SBL_RSVD (X) : origin=0x0 length=0x100
+ MCU0_R5F_TCMA (X) : origin=0x100 length=0x8000 - 0x100
+ MCU0_R5F_TCMB0 (RWIX) : origin=0x41010000 length=0x8000
+
+ /* MCU0_R5F_1 SoC view */
+ MCU0_R5F1_ATCM (RWIX) : origin=0x41400000 length=0x8000
+ MCU0_R5F1_BTCM (RWIX) : origin=0x41410000 length=0x8000
+
+ /* Fully avaialble for apps. Used by SBL to load SYSFW */
+ OCMRAM_LOW (RWIX) : origin=0x41C00100 length=0x40600 - 0x100 /* ~257KB */
+
+ /* MCU0 memory used for SBL. Avaiable after boot for app starts for dynamic use */
+ SBL_RESERVED (RWIX) : origin=0x41C40600 length=0x60000 - 0x40600 /* ~126KB */
+
+ /* MCU0 share locations */
+ OCMRAM (RWIX) : origin=0x41C60000 length=0x20000 - 0x1000 /* ~124KB */
+
+ /* AM65XX M4 locations */
+ MSMC3 (RWIX) : origin=0x70000000 length=0xF0000 /* 1MB - 64K */
+ MSMC3_H (RWIX) : origin=0x70100000 length=0xE2000 /* 1MB -56K */
+
+ /* Reserved for DMSC */
+ MSMC3_DMSC (RWIX) : origin=0x701F0000 length=0x10000 /* 64K */
+
+ DDR0 (RWIX) : origin=0x80000000 length=0x80000000 /* 2GB */
+
+/* Additional memory settings */
+
+} /* end of MEMORY */
+
+/*----------------------------------------------------------------------------*/
+/* Section Configuration */
+
+SECTIONS
+{
+/* 'intvecs' and 'intc_text' sections shall be placed within */
+/* a range of +\- 16 MB */
+ .intvecs : {} palign(8) > VECTORS
+ .intc_text : {} palign(8) > VECTORS
+ .rstvectors : {} palign(8) > RESET_VECTORS
+ .text : {} palign(8) > MSMC3
+ .const : {} palign(8) > MSMC3
+ .cinit : {} palign(8) > MSMC3
+ .pinit : {} palign(8) > MSMC3
+
+ /* For NDK packet memory, we need to map this sections before .bss*/
+ .bss:NDK_MMBUFFER (NOLOAD) {} ALIGN (128) > DDR0
+ .bss:NDK_PACKETMEM (NOLOAD) {} ALIGN (128) > DDR0
+
+ .bss : {} align(4) > MSMC3
+ .far : {} align(4) > DDR0
+ .data : {} palign(128) > MSMC3
+ .boardcfg_data : {} palign(128) > MSMC3
+ .sysmem : {} > MSMC3
+ .stack : {} align(4) > MSMC3 (HIGH)
+
+ /* USB or any other LLD buffer for benchmarking */
+ .benchmark_buffer (NOLOAD) {} ALIGN (8) > DDR0
+
+/* Additional sections settings */
+
+} /* end of SECTIONS */
+
+/*----------------------------------------------------------------------------*/
+/* Misc linker settings */
+
+
+/*-------------------------------- END ---------------------------------------*/
diff --git a/packages/ti/build/am65xx/r5_mpu.xs b/packages/ti/build/am65xx/r5_mpu.xs
--- /dev/null
@@ -0,0 +1,135 @@
+/*
+ * Copyright (c) 2018, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/*
+ * ======== event_MPU.xs ========
+ * MPU Settings for AM65XX device's Cortex-R5F
+ */
+
+/*
+ * -------------------------------------------------------------------------------------------------------------
+ * | Id | Base Address | Size | En | Cacheable | XN | AccPerm | Mask |
+ * |-------------------------------------------------------------------------------------------------------------|
+ * | 0 | 0x00000000 | 4GB | T | Strongly Ordered, Shareable | T | RW at PL 1 | 0x0 |
+ * |----|--------------|------|----|-------------------------------------------|----|---------------------|------|
+ * | 1 | 0x00000000 | 1K | T | Write-Back, Write-Allocate, Non-Shareable | F | RW at PL 1 | 0x0 |
+ * |----|--------------|------|----|-------------------------------------------|----|---------------------|------|
+ * | 2 | 0x41000000 | 32K | T | Write-Back, Write-Allocate, Non-Shareable | F | RW at PL 1 | 0x0 |
+ * |----|--------------|------|----|-------------------------------------------|----|---------------------|------|
+ * | 3 | 0x41010000 | 32K | T | Write-Back, Write-Allocate, Non-Shareable | F | RW at PL 1 | 0x0 |
+ * |----|--------------|------|----|-------------------------------------------|----|---------------------|------|
+ * | 4 | 0x41C00000 | 512K | T | Write-Back, Write-Allocate, Non-Shareable | F | RW at PL 1 | 0x0 |
+ * -------------------------------------------------------------------------------------------------------------
+ */
+
+/*
+ * Note: Marking a region as shareable will cause the region to behave as outer shareable with write through
+ * no write-allocate caching policy irrespective of the actual cache policy set. Therefore, only select
+ * regions that are actually shared outside the R5 CPUSS must be marked as shared.
+ */
+
+var MPU = xdc.useModule('ti.sysbios.family.arm.MPU');
+MPU.enableMPU = true;
+MPU.enableBackgroundRegion = true;
+
+var attrs = new MPU.RegionAttrs();
+MPU.initRegionAttrsMeta(attrs);
+
+attrs.enable = true;
+attrs.bufferable = false;
+attrs.cacheable = false;
+attrs.shareable = true;
+attrs.noExecute = true;
+attrs.accPerm = 1; /* RW at PL1 */
+attrs.tex = 0;
+attrs.subregionDisableMask = 0;
+MPU.setRegionMeta(0, 0x00000000, MPU.RegionSize_4G, attrs);
+
+attrs.enable = true;
+attrs.bufferable = true;
+attrs.cacheable = true;
+attrs.shareable = false;
+attrs.noExecute = false;
+attrs.accPerm = 1; /* RW at PL1 */
+attrs.tex = 1;
+attrs.subregionDisableMask = 0;
+MPU.setRegionMeta(1, 0x00000000, MPU.RegionSize_32K, attrs);
+
+attrs.enable = true;
+attrs.bufferable = true;
+attrs.cacheable = true;
+attrs.shareable = false;
+attrs.noExecute = false;
+attrs.accPerm = 1; /* RW at PL1 */
+attrs.tex = 1;
+attrs.subregionDisableMask = 0;
+MPU.setRegionMeta(2, 0x41000000, MPU.RegionSize_32K, attrs);
+
+attrs.enable = true;
+attrs.bufferable = true;
+attrs.cacheable = true;
+attrs.shareable = false;
+attrs.noExecute = false;
+attrs.accPerm = 1; /* RW at PL1 */
+attrs.tex = 1;
+attrs.subregionDisableMask = 0x0;
+MPU.setRegionMeta(3, 0x41010000, MPU.RegionSize_32K, attrs);
+
+attrs.enable = true;
+attrs.bufferable = true;
+attrs.cacheable = true;
+attrs.shareable = false;
+attrs.noExecute = false;
+attrs.accPerm = 1; /* RW at PL1 */
+attrs.tex = 1;
+attrs.subregionDisableMask = 0;
+MPU.setRegionMeta(4, 0x41C00000, MPU.RegionSize_512K, attrs);
+
+attrs.enable = true;
+attrs.bufferable = true;
+attrs.cacheable = true;
+attrs.shareable = false;
+attrs.noExecute = false;
+attrs.accPerm = 1; /* RW at PL1 */
+attrs.tex = 1;
+attrs.subregionDisableMask = 0;
+MPU.setRegionMeta(5, 0x70000000, MPU.RegionSize_2M, attrs);
+
+
+attrs.enable = true;
+attrs.bufferable = true;
+attrs.cacheable = true;
+attrs.shareable = false;
+attrs.noExecute = false;
+attrs.accPerm = 1; /* RW at PL1 */
+attrs.tex = 1;
+attrs.subregionDisableMask = 0;
+MPU.setRegionMeta(6, 0x80000000, MPU.RegionSize_2G, attrs);
diff --git a/packages/ti/build/am65xx/sysbios_a53.cfg b/packages/ti/build/am65xx/sysbios_a53.cfg
--- /dev/null
@@ -0,0 +1,148 @@
+
+/* =============================================================================
+ * Copyright (c) Texas Instruments Incorporated 2018
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+var Defaults = xdc.useModule('xdc.runtime.Defaults');
+var Diags = xdc.useModule('xdc.runtime.Diags');
+var Error = xdc.useModule('xdc.runtime.Error');
+var Log = xdc.useModule('xdc.runtime.Log');
+var LoggerBuf = xdc.useModule('xdc.runtime.LoggerBuf');
+var Main = xdc.useModule('xdc.runtime.Main');
+var Memory = xdc.useModule('xdc.runtime.Memory');
+var System = xdc.useModule('xdc.runtime.System');
+var Text = xdc.useModule('xdc.runtime.Text');
+var Clock = xdc.useModule('ti.sysbios.knl.Clock');
+var Task = xdc.useModule('ti.sysbios.knl.Task');
+var Semaphore = xdc.useModule('ti.sysbios.knl.Semaphore');
+
+var BIOS = xdc.useModule('ti.sysbios.BIOS');
+var Hwi = xdc.useModule('ti.sysbios.hal.Hwi');
+var HeapMem = xdc.useModule('ti.sysbios.heaps.HeapMem');
+var SysMin = xdc.useModule('xdc.runtime.SysMin');
+
+var Cache = xdc.module("ti.sysbios.hal.Cache");
+Cache.CacheProxy = xdc.useModule("ti.sysbios.family.arm.v8a.Cache");
+
+var Mmu = xdc.useModule('ti.sysbios.family.arm.v8a.Mmu');
+Mmu.initFunc = "&InitMmu";
+Mmu.tableArrayLen = 24;
+Program.sectMap[".ti_sysbios_family_arm_v8a_Mmu_tableArray"] = "MSMC_SRAM";
+
+/*
+ * Direct CIO to UART
+ */
+/* System.SupportProxy = SysUart; */
+System.SupportProxy = SysMin;
+
+/*
+ * Program.argSize sets the size of the .args section.
+ * The examples don't use command line args so argSize is set to 0.
+ */
+Program.argSize = 0x0;
+
+/*
+ * Uncomment this line to globally disable Asserts.
+ * All modules inherit the default from the 'Defaults' module. You
+ * can override these defaults on a per-module basis using Module.common$.
+ * Disabling Asserts will save code space and improve runtime performance.
+Defaults.common$.diags_ASSERT = Diags.ALWAYS_OFF;
+ */
+
+/*
+ * Uncomment this line to keep module names from being loaded on the target.
+ * The module name strings are placed in the .const section. Setting this
+ * parameter to false will save space in the .const section. Error and
+ * Assert messages will contain an "unknown module" prefix instead
+ * of the actual module name.
+Defaults.common$.namedModule = false;
+ */
+
+/* Create default heap and hook it into Memory */
+var heapMemParams = new HeapMem.Params;
+heapMemParams.size = 16384*3;
+var heap0 = HeapMem.create(heapMemParams);
+
+Memory.defaultHeapInstance = heap0;
+
+/*
+ * Minimize exit handler array in System. The System module includes
+ * an array of functions that are registered with System_atexit() to be
+ * called by System_exit().
+ */
+System.maxAtexitHandlers = 4;
+
+/*
+ * Uncomment this line to disable the Error print function.
+ * We lose error information when this is disabled since the errors are
+ * not printed. Disabling the raiseHook will save some code space if
+ * your app is not using System_printf() since the Error_print() function
+ * calls System_printf().
+Error.raiseHook = null;
+ */
+
+/*
+ * Uncomment this line to keep Error, Assert, and Log strings from being
+ * loaded on the target. These strings are placed in the .const section.
+ * Setting this parameter to false will save space in the .const section.
+ * Error, Assert and Log message will print raw ids and args instead of
+ * a formatted message.
+Text.isLoaded = false;
+ */
+
+/*
+ * Uncomment this line to disable the output of characters by SysMin
+ * when the program exits. SysMin writes characters to a circular buffer.
+ * This buffer can be viewed using the SysMin Output view in ROV.
+SysMin.flushAtExit = false;
+ */
+
+/*
+ * Create and install logger for the whole system
+ */
+var loggerBufParams = new LoggerBuf.Params();
+loggerBufParams.numEntries = 32;
+var logger0 = LoggerBuf.create(loggerBufParams);
+Defaults.common$.logger = logger0;
+Main.common$.diags_INFO = Diags.ALWAYS_ON;
+
+BIOS.libType = BIOS.LibType_Custom;
+
+/* Disable Timer frequency check, workaround for QT test */
+var Timer = xdc.useModule('ti.sysbios.timers.dmtimer.Timer');
+Timer.checkFrequency = false;
+
+/* Check if application needs to update with custom configuration options */
+var cfgUpdate = java.lang.System.getenv("XDC_CFG_UPDATE")
+if(cfgUpdate != '' && cfgUpdate != null)
+{
+ xdc.print("Loading configuration update " + cfgUpdate);
+ xdc.loadCapsule(cfgUpdate);
+}
diff --git a/packages/ti/build/am65xx/sysbios_r5f.cfg b/packages/ti/build/am65xx/sysbios_r5f.cfg
--- /dev/null
@@ -0,0 +1,158 @@
+
+/* =============================================================================
+ * Copyright (c) Texas Instruments Incorporated 2018
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+var Defaults = xdc.useModule('xdc.runtime.Defaults');
+var Diags = xdc.useModule('xdc.runtime.Diags');
+var Error = xdc.useModule('xdc.runtime.Error');
+var Log = xdc.useModule('xdc.runtime.Log');
+var LoggerBuf = xdc.useModule('xdc.runtime.LoggerBuf');
+var Main = xdc.useModule('xdc.runtime.Main');
+var Memory = xdc.useModule('xdc.runtime.Memory')
+var System = xdc.useModule('xdc.runtime.System');
+var Text = xdc.useModule('xdc.runtime.Text');
+var Clock = xdc.useModule('ti.sysbios.knl.Clock');
+var Task = xdc.useModule('ti.sysbios.knl.Task');
+var Semaphore = xdc.useModule('ti.sysbios.knl.Semaphore');
+
+var BIOS = xdc.useModule('ti.sysbios.BIOS');
+var Hwi = xdc.useModule('ti.sysbios.family.arm.v7r.keystone3.Hwi');
+var HeapMem = xdc.useModule('ti.sysbios.heaps.HeapMem');
+var SysMin = xdc.useModule('xdc.runtime.SysMin');
+
+/* System stack size (used by ISRs and Swis) */
+Program.stack = 0x2000;
+var Task = xdc.useModule('ti.sysbios.knl.Task');
+Task.defaultStackSize = 0x4000;
+Task.common$.namedInstance = true;
+Task.common$.namedModule = true;
+
+/* Enable cache */
+var Cache = xdc.useModule('ti.sysbios.family.arm.v7r.Cache');
+Cache.enableCache = true;
+
+/*
+ * Direct CIO to UART
+ */
+/* System.SupportProxy = SysUart; */
+System.SupportProxy = SysMin;
+
+/*
+ * Program.argSize sets the size of the .args section.
+ * The examples don't use command line args so argSize is set to 0.
+ */
+Program.argSize = 0x0;
+
+/*
+ * Uncomment this line to globally disable Asserts.
+ * All modules inherit the default from the 'Defaults' module. You
+ * can override these defaults on a per-module basis using Module.common$.
+ * Disabling Asserts will save code space and improve runtime performance.
+Defaults.common$.diags_ASSERT = Diags.ALWAYS_OFF;
+ */
+
+/*
+ * Uncomment this line to keep module names from being loaded on the target.
+ * The module name strings are placed in the .const section. Setting this
+ * parameter to false will save space in the .const section. Error and
+ * Assert messages will contain an "unknown module" prefix instead
+ * of the actual module name.
+Defaults.common$.namedModule = false;
+ */
+
+/* Create default heap and hook it into Memory */
+var heapMemParams = new HeapMem.Params;
+heapMemParams.size = 16384*3;
+var heap0 = HeapMem.create(heapMemParams);
+
+Memory.defaultHeapInstance = heap0;
+
+/*
+ * Minimize exit handler array in System. The System module includes
+ * an array of functions that are registered with System_atexit() to be
+ * called by System_exit().
+ */
+System.maxAtexitHandlers = 4;
+
+/*
+ * Uncomment this line to disable the Error print function.
+ * We lose error information when this is disabled since the errors are
+ * not printed. Disabling the raiseHook will save some code space if
+ * your app is not using System_printf() since the Error_print() function
+ * calls System_printf().
+Error.raiseHook = null;
+ */
+
+/*
+ * Uncomment this line to keep Error, Assert, and Log strings from being
+ * loaded on the target. These strings are placed in the .const section.
+ * Setting this parameter to false will save space in the .const section.
+ * Error, Assert and Log message will print raw ids and args instead of
+ * a formatted message.
+Text.isLoaded = false;
+ */
+
+/*
+ * Uncomment this line to disable the output of characters by SysMin
+ * when the program exits. SysMin writes characters to a circular buffer.
+ * This buffer can be viewed using the SysMin Output view in ROV.
+SysMin.flushAtExit = false;
+ */
+
+/*
+ * Create and install logger for the whole system
+ */
+var loggerBufParams = new LoggerBuf.Params();
+loggerBufParams.numEntries = 32;
+var logger0 = LoggerBuf.create(loggerBufParams);
+Defaults.common$.logger = logger0;
+Main.common$.diags_INFO = Diags.ALWAYS_ON;
+
+BIOS.libType = BIOS.LibType_Custom;
+
+/* Disable Timer frequency check, workaround for QT test */
+var Timer = xdc.useModule('ti.sysbios.timers.dmtimer.Timer');
+Timer.checkFrequency = false;
+
+/*
+ * Initialize MPU and enable it
+ *
+ * Note: MPU must be enabled and properly configured for caching to work.
+ */
+xdc.loadCapsule("r5_mpu.xs");
+
+/* Check if application needs to update with custom configuration options */
+var cfgUpdate = java.lang.System.getenv("XDC_CFG_UPDATE")
+if(cfgUpdate != '' && cfgUpdate != null)
+{
+ xdc.print("Loading configuration update " + cfgUpdate);
+ xdc.loadCapsule(cfgUpdate);
+}
diff --git a/packages/ti/build/am65xx/sysbios_smp_a53.cfg b/packages/ti/build/am65xx/sysbios_smp_a53.cfg
--- /dev/null
@@ -0,0 +1,157 @@
+
+/* =============================================================================
+ * Copyright (c) Texas Instruments Incorporated 2019
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+var Defaults = xdc.useModule('xdc.runtime.Defaults');
+var Diags = xdc.useModule('xdc.runtime.Diags');
+var Error = xdc.useModule('xdc.runtime.Error');
+var Log = xdc.useModule('xdc.runtime.Log');
+var LoggerBuf = xdc.useModule('ti.sysbios.smp.LoggerBuf');
+var Main = xdc.useModule('xdc.runtime.Main');
+var Memory = xdc.useModule('xdc.runtime.Memory');
+var System = xdc.useModule('xdc.runtime.System');
+var Text = xdc.useModule('xdc.runtime.Text');
+var Clock = xdc.useModule('ti.sysbios.knl.Clock');
+var Task = xdc.useModule('ti.sysbios.knl.Task');
+var Semaphore = xdc.useModule('ti.sysbios.knl.Semaphore');
+
+var BIOS = xdc.useModule('ti.sysbios.BIOS');
+var Hwi = xdc.useModule('ti.sysbios.hal.Hwi');
+var HeapMem = xdc.useModule('ti.sysbios.heaps.HeapMem');
+var SysMin = xdc.useModule('ti.sysbios.smp.SysMin');
+var Core = xdc.useModule('ti.sysbios.family.arm.v8a.smp.Core');
+
+var Mmu = xdc.useModule('ti.sysbios.family.arm.v8a.Mmu');
+Mmu.initFunc = "&InitMmu";
+Mmu.tableArrayLen = 24;
+Program.sectMap[".ti_sysbios_family_arm_v8a_Mmu_tableArray"] = "MSMC_SRAM";
+
+/*Enabling BIOS SMP mode */
+BIOS.smpEnabled = true;
+
+/* Enable cache */
+var Cache = xdc.module("ti.sysbios.hal.Cache");
+
+/*
+ * Direct CIO to UART
+ */
+/* System.SupportProxy = SysUart; */
+System.SupportProxy = SysMin;
+
+/*
+ * Program.argSize sets the size of the .args section.
+ * The examples don't use command line args so argSize is set to 0.
+ */
+Program.argSize = 0x0;
+
+/*
+ * Uncomment this line to globally disable Asserts.
+ * All modules inherit the default from the 'Defaults' module. You
+ * can override these defaults on a per-module basis using Module.common$.
+ * Disabling Asserts will save code space and improve runtime performance.
+Defaults.common$.diags_ASSERT = Diags.ALWAYS_OFF;
+ */
+
+/*
+ * Uncomment this line to keep module names from being loaded on the target.
+ * The module name strings are placed in the .const section. Setting this
+ * parameter to false will save space in the .const section. Error and
+ * Assert messages will contain an "unknown module" prefix instead
+ * of the actual module name.
+Defaults.common$.namedModule = false;
+ */
+
+/* Create default heap and hook it into Memory */
+var heapMemParams = new HeapMem.Params;
+heapMemParams.size = 16384*18;
+var heap0 = HeapMem.create(heapMemParams);
+
+Memory.defaultHeapInstance = heap0;
+
+/*
+ * Minimize exit handler array in System. The System module includes
+ * an array of functions that are registered with System_atexit() to be
+ * called by System_exit().
+ */
+System.maxAtexitHandlers = 4;
+
+/*
+ * Uncomment this line to disable the Error print function.
+ * We lose error information when this is disabled since the errors are
+ * not printed. Disabling the raiseHook will save some code space if
+ * your app is not using System_printf() since the Error_print() function
+ * calls System_printf().
+Error.raiseHook = null;
+ */
+
+/*
+ * Uncomment this line to keep Error, Assert, and Log strings from being
+ * loaded on the target. These strings are placed in the .const section.
+ * Setting this parameter to false will save space in the .const section.
+ * Error, Assert and Log message will print raw ids and args instead of
+ * a formatted message.
+Text.isLoaded = false;
+ */
+
+/*
+ * Uncomment this line to disable the output of characters by SysMin
+ * when the program exits. SysMin writes characters to a circular buffer.
+ * This buffer can be viewed using the SysMin Output view in ROV.
+SysMin.flushAtExit = false;
+ */
+
+/*
+ * Create and install logger for the whole system
+ */
+var loggerBufParams = new LoggerBuf.Params();
+loggerBufParams.numEntries = 32;
+var logger0 = LoggerBuf.create(loggerBufParams);
+Defaults.common$.logger = logger0;
+Main.common$.diags_INFO = Diags.ALWAYS_ON;
+
+BIOS.libType = BIOS.LibType_Custom;
+
+/* System stack size (used by ISRs and Swis) */
+Program.stack = 0x10000;
+
+Task.defaultStackSize = 0x4000;
+
+/* Disable Timer frequency check, workaround for QT test */
+var Timer = xdc.useModule('ti.sysbios.timers.dmtimer.Timer');
+Timer.checkFrequency = false;
+
+/* Check if application needs to update with custom configuration options */
+var cfgUpdate = java.lang.System.getenv("XDC_CFG_UPDATE")
+if(cfgUpdate != '' && cfgUpdate != null)
+{
+ xdc.print("Loading configuration update " + cfgUpdate);
+ xdc.loadCapsule(cfgUpdate);
+}
diff --git a/packages/ti/build/comp_paths.mk b/packages/ti/build/comp_paths.mk
--- /dev/null
@@ -0,0 +1,123 @@
+################################################################################
+# Individual component path, needed to build a component in a different location
+# as that of PDK
+################################################################################
+
+PDK_SDL_ROOT_PATH ?= $(pdk_PATH)
+export PDK_SDL_COMP_PATH = $(PDK_SDL_ROOT_PATH)/ti/sdl
+PDK_CSL_ROOT_PATH ?= $(pdk_PATH)
+export PDK_CSL_COMP_PATH = $(PDK_CSL_ROOT_PATH)/ti/csl
+PDK_CSL2_ROOT_PATH ?= $(pdk_PATH)
+export PDK_CSL2_COMP_PATH = $(PDK_CSL2_ROOT_PATH)/ti/csl
+PDK_PM_ROOT_PATH ?= $(pdk_PATH)
+export PDK_PM_COMP_PATH = $(PDK_PM_ROOT_PATH)/ti/drv/pm
+PDK_OSAL_ROOT_PATH ?= $(pdk_PATH)
+export PDK_OSAL_COMP_PATH = $(PDK_OSAL_ROOT_PATH)/ti/osal
+PDK_I2C_ROOT_PATH ?= $(pdk_PATH)
+export PDK_I2C_COMP_PATH = $(PDK_I2C_ROOT_PATH)/ti/drv/i2c
+PDK_VPS_ROOT_PATH ?= $(pdk_PATH)
+export PDK_VPS_COMP_PATH = $(PDK_VPS_ROOT_PATH)/ti/drv/vps
+PDK_GPIO_ROOT_PATH ?= $(pdk_PATH)
+export PDK_GPIO_COMP_PATH = $(PDK_GPIO_ROOT_PATH)/ti/drv/gpio
+PDK_FATFS_ROOT_PATH ?= $(pdk_PATH)
+export PDK_FATFS_COMP_PATH = $(PDK_FATFS_ROOT_PATH)/ti/fs/fatfs
+PDK_MMCSD_ROOT_PATH ?= $(pdk_PATH)
+export PDK_MMCSD_COMP_PATH = $(PDK_MMCSD_ROOT_PATH)/ti/drv/mmcsd
+PDK_PCIE_ROOT_PATH ?= $(pdk_PATH)
+export PDK_PCIE_COMP_PATH = $(PDK_PCIE_ROOT_PATH)/ti/drv/pcie
+PDK_USB_ROOT_PATH ?= $(pdk_PATH)
+export PDK_USB_COMP_PATH = $(PDK_USB_ROOT_PATH)/ti/drv/usb
+PDK_SERDES_DIAG_ROOT_PATH ?= $(pdk_PATH)
+export PDK_SERDES_DIAG_COMP_PATH = $(PDK_SERDES_DIAG_ROOT_PATH)/ti/diag/serdes_diag
+PDK_MCASP_ROOT_PATH ?= $(pdk_PATH)
+export PDK_MCASP_COMP_PATH = $(PDK_MCASP_ROOT_PATH)/ti/drv/mcasp
+PDK_MCBSP_ROOT_PATH ?= $(pdk_PATH)
+export PDK_MCBSP_COMP_PATH = $(PDK_MCBSP_ROOT_PATH)/ti/drv/mcbsp
+PDK_PROFILING_ROOT_PATH ?= $(pdk_PATH)
+export PDK_PROFILING_COMP_PATH = $(PDK_PROFILING_ROOT_PATH)/ti/utils/profiling
+PDK_TRACE_ROOT_PATH ?= $(pdk_PATH)
+export PDK_TRACE_COMP_PATH = $(PDK_TRACE_ROOT_PATH)/ti/utils/trace
+PDK_PRUSS_ROOT_PATH ?= $(pdk_PATH)
+export PDK_PRUSS_COMP_PATH = $(PDK_PRUSS_ROOT_PATH)/ti/drv/pruss
+PDK_NIMU_ROOT_PATH ?= $(pdk_PATH)
+export PDK_NIMU_COMP_PATH = $(PDK_NIMU_ROOT_PATH)/ti/transport/ndk/nimu
+PDK_NIMU_ICSS_ROOT_PATH ?= $(pdk_PATH)
+export PDK_NIMU_ICSS_COMP_PATH = $(PDK_NIMU_ICSS_ROOT_PATH)/ti/transport/ndk/nimu_icss
+PDK_TIMESYNC_ROOT_PATH ?= $(pdk_PATH)
+export PDK_TIMESYNC_COMP_PATH = $(PDK_TIMESYNC_ROOT_PATH)/ti/transport/timeSync
+PDK_ICSS_EMAC_ROOT_PATH ?= $(pdk_PATH)
+export PDK_ICSS_EMAC_COMP_PATH = $(PDK_ICSS_EMAC_ROOT_PATH)/ti/drv/icss_emac
+PDK_EMAC_ROOT_PATH ?= $(pdk_PATH)
+export PDK_EMAC_COMP_PATH = $(PDK_EMAC_ROOT_PATH)/ti/drv/emac
+PDK_UART_ROOT_PATH ?= $(pdk_PATH)
+export PDK_UART_COMP_PATH = $(PDK_UART_ROOT_PATH)/ti/drv/uart
+PDK_SPI_ROOT_PATH ?= $(pdk_PATH)
+export PDK_SPI_COMP_PATH = $(PDK_SPI_ROOT_PATH)/ti/drv/spi
+PDK_BOARD_ROOT_PATH ?= $(pdk_PATH)
+export PDK_BOARD_COMP_PATH = $(PDK_BOARD_ROOT_PATH)/ti/board
+PDK_GPMC_ROOT_PATH ?= $(pdk_PATH)
+export PDK_GPMC_COMP_PATH = $(PDK_GPMC_ROOT_PATH)/ti/drv/gpmc
+PDK_AUD_ROOT_PATH ?= $(pdk_PATH)
+export PDK_AUD_COMP_PATH = $(PDK_AUD_ROOT_PATH)/ti/addon/aud
+PDK_SBL_ROOT_PATH ?= $(pdk_PATH)
+export PDK_SBL_COMP_PATH = $(PDK_SBL_ROOT_PATH)/ti/boot/sbl
+PDK_SBL_AUTO_ROOT_PATH ?= $(pdk_PATH)
+export PDK_SBL_AUTO_COMP_PATH = $(PDK_SBL_AUTO_ROOT_PATH)/ti/boot/sbl_auto
+PDK_CMB_ROOT_PATH ?= $(pdk_PATH)
+export PDK_CMB_COMP_PATH = $(PDK_CMB_ROOT_PATH)/ti/addon/cmb
+PDK_BOARD_IND_ROOT_PATH ?= $(pdk_PATH)
+export PDK_BOARD_IND_COMP_PATH = $(PDK_BOARD_IND_ROOT_PATH)/ti/addon/board_ind
+PDK_BOARD_UTILS_ROOT_PATH ?= $(pdk_PATH)
+export PDK_BOARD_UTILS_COMP_PATH = $(PDK_BOARD_UTILS_ROOT_PATH)/ti/board/utils
+PDK_BOARD_DIAG_ROOT_PATH ?= $(pdk_PATH)
+export PDK_BOARD_DIAG_COMP_PATH = $(PDK_BOARD_DIAG_ROOT_PATH)/ti/board/diag
+
+PDK_SA_ROOT_PATH ?= $(pdk_PATH)
+export PDK_SA_COMP_PATH = $(PDK_SA_ROOT_PATH)/ti/drv/sa
+
+PDK_IOLINK_ROOT_PATH ?= $(pdk_PATH)
+export PDK_IOLINK_COMP_PATH = $(PDK_IOLINK_ROOT_PATH)/ti/drv/iolink
+
+#Below applicable only for K3 devices
+PDK_UDMA_ROOT_PATH ?= $(pdk_PATH)
+export PDK_UDMA_COMP_PATH = $(PDK_UDMA_ROOT_PATH)/ti/drv/udma
+PDK_DSS_ROOT_PATH ?= $(pdk_PATH)
+export PDK_DSS_COMP_PATH = $(PDK_DSS_ROOT_PATH)/ti/drv/dss
+PDK_SCICLIENT_ROOT_PATH ?= $(pdk_PATH)
+export PDK_SCICLIENT_COMP_PATH = $(PDK_SCICLIENT_ROOT_PATH)/ti/drv/sciclient
+PDK_FVID2_ROOT_PATH ?= $(pdk_PATH)
+export PDK_FVID2_COMP_PATH = $(PDK_FVID2_ROOT_PATH)/ti/drv/fvid2
+PDK_CAL_ROOT_PATH ?= $(pdk_PATH)
+export PDK_CAL_COMP_PATH = $(PDK_CAL_ROOT_PATH)/ti/drv/cal
+PDK_VHWA_ROOT_PATH ?= $(pdk_PATH)
+export PDK_VHWA_COMP_PATH = $(PDK_VHWA_ROOT_PATH)/ti/drv/vhwa
+PDK_CSIRX_ROOT_PATH ?= $(pdk_PATH)
+export PDK_CSIRX_COMP_PATH = $(PDK_CSIRX_ROOT_PATH)/ti/drv/csirx
+PDK_IPC_ROOT_PATH ?= $(pdk_PATH)
+export PDK_IPC_COMP_PATH = $(pdk_PATH)/ti/drv/ipc
+PDK_CPSW_ROOT_PATH ?= $(pdk_PATH)
+export PDK_CPSW_COMP_PATH = $(PDK_CPSW_ROOT_PATH)/ti/drv/cpsw
+
+#Below applicable only for K3 DMSC; not applicable for PRSDK
+DMSC_ROOT_PATH ?= $(pdk_PATH)
+export DMSC_COMP_PATH = $(DMSC_ROOT_PATH)/ti/dmsc
+
+#Below applicable only for TDA devices
+PDK_DIAG_ROOT_PATH ?= $(pdk_PATH)
+export PDK_DIAG_COMP_PATH = $(PDK_DIAG_ROOT_PATH)/ti/diag
+PDK_FIREWALL_L3L4_ROOT_PATH ?= $(pdk_PATH)
+export PDK_FIREWALL_L3L4_COMP_PATH = $(PDK_FIREWALL_L3L4_ROOT_PATH)/ti/drv/fw_l3l4
+PDK_IPCLITE_ROOT_PATH ?= $(pdk_PATH)
+export PDK_IPCLITE_COMP_PATH = $(PDK_IPCLITE_ROOT_PATH)/ti/drv/ipc_lite
+PDK_TDA3X_SECURITY_ROOT_PATH ?= $(pdk_PATH)
+export PDK_TDA3X_SECURITY_COMP_PATH = $(PDK_TDA3X_SECURITY_ROOT_PATH)/ti/boot/sbl_auto/security
+
+#Below applicable only for TDA devices for backward compatibility;not applicable for PRSDK
+PDK_NORFLASH_ROOT_PATH ?= $(pdk_PATH)
+export PDK_NORFLASH_COMP_PATH = $(PDK_NORFLASH_ROOT_PATH)/ti/boot/sbl_auto/norflash
+PDK_QSPIFLASH_ROOT_PATH ?= $(pdk_PATH)
+export PDK_QSPIFLASH_COMP_PATH = $(PDK_QSPIFLASH_ROOT_PATH)/ti/boot/sbl_auto/qspiflash
+PDK_STW_LLD_ROOT_PATH ?= $(pdk_PATH)
+export PDK_STW_LLD_COMP_PATH = $(PDK_STW_LLD_ROOT_PATH)/ti/drv/stw_lld
+PDK_BSP_LLD_ROOT_PATH ?= $(pdk_PATH)
+export PDK_BSP_LLD_COMP_PATH = $(PDK_BSP_LLD_ROOT_PATH)/ti/drv/bsp_lld
diff --git a/packages/ti/build/comp_top.mk b/packages/ti/build/comp_top.mk
--- /dev/null
@@ -0,0 +1,427 @@
+# ============================================================================
+# (C) Copyright 2016-2018 Texas Instruments, Inc.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# Redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer.
+#
+# Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the
+# distribution.
+#
+# Neither the name of Texas Instruments Incorporated nor the names of
+# its contributors may be used to endorse or promote products derived
+# from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# ============================================================================
+
+XDC = $(XDC_INSTALL_PATH)/xdc
+
+#options for sphinx documentation
+SPHINXBUILD = sphinx-build
+DESIGNDOC_ROOT = docs/design
+ALLSPHINXOPTS = -d $(DESIGNDOC_ROOT)/build/doctrees $(PAPEROPT_$(PAPER)) $(SPHINXOPTS) $(DESIGNDOC_ROOT)
+
+# check if we need to limit the Build to limitted SOCS
+ifdef LIMIT_BOARDS
+ BOARD_LIST_ALL = $(filter $(LIMIT_BOARDS), $($(COMP)_BOARDLIST))
+else
+ BOARD_LIST_ALL = $($(COMP)_BOARDLIST)
+endif
+
+# check if we need to limit the Build to limitted SOCS
+ifdef LIMIT_SOCS
+ SOC_LIST_ALL = $(filter $(LIMIT_SOCS), $($(COMP)_SOCLIST))
+else
+ SOC_LIST_ALL = $($(COMP)_SOCLIST)
+endif
+
+# check if we need to limit the build to limitted cores
+ifdef LIMIT_CORES
+ CORE_LIST_ALL = $(filter $(LIMIT_CORES), $($(COMP)_$(SOC)_CORELIST))
+else
+ CORE_LIST_ALL = $($(COMP)_$(SOC)_CORELIST)
+endif
+
+# For core indpendent libraries, chose the 'base' core the other cores' target can depend on
+LIM_CORE_BASE_LIST := $(foreach core_type,$(DEFAULT_CORE_TYPES),$(firstword $(filter $(core_type)%,$(CORE_LIST_ALL))))
+# The rest of the cores, i.e (CORE_LIST_ALL - LIM_CORE_BASE_LIST). These will depend on the LIM_CORE_BASE_LIST
+LIM_CORE_REST_LIST := $(filter-out $(LIM_CORE_BASE_LIST),$(CORE_LIST_ALL))
+
+PRUCORE_LIST = pru_0 pru_1
+
+# If the component enables this, parallel builds are disabled for this component
+ifeq ($($(COMP)_DISABLE_PARALLEL_MAKE),yes)
+.NOTPARALLEL:
+endif
+
+ifeq ($(lib_$(COMP)_BUILD_DEPENDENCY),soc)
+ lib_BOARD_SOC_LIST_ALL = $(addsuffix _lib, $(SOC_LIST_ALL))
+endif
+ifeq ($(lib_$(COMP)_BUILD_DEPENDENCY),board)
+ lib_BOARD_SOC_LIST_ALL = $(addsuffix _lib, $(BOARD_LIST_ALL))
+endif
+lib_CORE_LIST_ALL = $(addsuffix _lib, $(filter-out $(PRUCORE_LIST),$(CORE_LIST_ALL)))
+lib_CORE_LIST_BASE = $(addsuffix _lib, $(filter-out $(PRUCORE_LIST),$(LIM_CORE_BASE_LIST)))
+lib_CORE_LIST_REST = $(addsuffix _lib, $(filter-out $(PRUCORE_LIST),$(LIM_CORE_REST_LIST)))
+
+lib_LIB_ENDIAN_LIST = $(addsuffix _lib, $(LIB_ENDIAN_LIST))
+ifeq ($(lib_$(COMP)_BUILD_DEPENDENCY),soc)
+ lib_BOARD_SOC_LIST_ALL_CLEAN = $(addsuffix _lclean, $(SOC_LIST_ALL))
+endif
+ifeq ($(lib_$(COMP)_BUILD_DEPENDENCY),board)
+ lib_BOARD_SOC_LIST_ALL_CLEAN = $(addsuffix _lclean, $(BOARD_LIST_ALL))
+endif
+lib_CORE_LIST_ALL_CLEAN = $(addsuffix _lclean, $(filter-out $(PRUCORE_LIST),$(CORE_LIST_ALL)))
+lib_LIB_ENDIAN_LIST_CLEAN = $(addsuffix _lclean, $(LIB_ENDIAN_LIST))
+
+app_lib_BOARD_SOC_LIST_ALL = $(addsuffix _app_lib, $(BOARD_LIST_ALL))
+app_lib_CORE_LIST_ALL = $(addsuffix _app_lib, $(CORE_LIST_ALL))
+app_lib_LIB_ENDIAN_LIST = $(addsuffix _app_lib, $(LIB_ENDIAN_LIST))
+
+app_lib_BOARD_SOC_LIST_ALL_CLEAN = $(addsuffix _app_lclean, $(BOARD_LIST_ALL))
+app_lib_CORE_LIST_ALL_CLEAN = $(addsuffix _app_lclean, $(CORE_LIST_ALL))
+app_lib_LIB_ENDIAN_LIST_CLEAN = $(addsuffix _app_lclean, $(LIB_ENDIAN_LIST))
+
+app_BOARD_LIST_ALL = $(addsuffix _app, $(BOARD_LIST_ALL))
+app_CORE_LIST_ALL = $(addsuffix _app, $(CORE_LIST_ALL))
+
+app_LIB_ENDIAN_LIST = $(addsuffix _app, $(LIB_ENDIAN_LIST))
+app_LIB_BOARD_LIST = $(addsuffix _app, $(BOARD_LIST_ALL))
+app_LIB_SOC_LIST = $(addsuffix _app, $(SOC_LIST_ALL))
+
+app_BOARD_LIST_ALL_CLEAN = $(addsuffix _aclean, $(BOARD_LIST_ALL))
+app_CORE_LIST_ALL_CLEAN = $(addsuffix _aclean, $(CORE_LIST_ALL))
+app_LIB_ENDIAN_LIST_CLEAN = $(addsuffix _aclean, $(LIB_ENDIAN_LIST))
+
+firm_SOC_LIST_ALL = $(addsuffix _firm, $(SOC_LIST_ALL))
+firm_CORE_LIST_ALL = $(addsuffix _firm, $(filter $(PRUCORE_LIST),$(CORE_LIST_ALL)))
+firm_HOST_CORE_LIST = $(addsuffix _firm, $(filter-out $(PRUCORE_LIST),$(CORE_LIST_ALL)))
+firm_VERSION_LIST_ALL = $(addsuffix _firm, $(PRU_VERSION_LIST))
+firm_SOC_LIST_ALL_CLEAN = $(addsuffix _fclean, $(SOC_LIST_ALL))
+firm_CORE_LIST_ALL_CLEAN = $(addsuffix _fclean, $(filter $(PRUCORE_LIST),$(CORE_LIST_ALL)))
+firm_HOST_CORE_LIST_CLEAN = $(addsuffix _fclean, $(filter-out $(PRUCORE_LIST),$(CORE_LIST_ALL)))
+firm_VERSION_LIST_ALL_CLEAN = $(addsuffix _fclean, $(PRU_VERSION_LIST))
+
+comp_PKG_LIST_ALL = $($(COMP)_EXAMPLE_LIST) $($(COMP)_DUP_EXAMPLE_LIST) $($(COMP)_APP_LIB_LIST) $($(COMP)_LIB_LIST) $($(COMP)_FIRM_LIST)
+comp_LIB_LIST_CLEAN = $(addsuffix _clean, $($(COMP)_LIB_LIST))
+comp_APP_LIB_LIST_CLEAN = $(addsuffix _clean, $($(COMP)_APP_LIB_LIST))
+comp_EXAMPLE_LIST_CLEAN = $(addsuffix _clean, $($(COMP)_EXAMPLE_LIST))
+comp_FIRM_LIST_CLEAN = $(addsuffix _clean, $($(COMP)_FIRM_LIST))
+comp_PKG_LIST_ALL_CLEAN = $(addsuffix _clean, $(comp_PKG_LIST_ALL))
+comp_PKG_LIST_PACKAGE = $(addsuffix _package, $(comp_PKG_LIST_ALL))
+
+# If the component enables doxygen, this will evaluate to "yesyes" and doxygen
+# will be built. If this value is overridden by the user to any other value, or
+# $(COMP)_DOXYGEN_SUPPORT is not "yes", doxygen is not built.
+DOXYGEN_SUPPORT ?= yes$($(COMP)_DOXYGEN_SUPPORT)
+
+.PHONY : apps appcores app_clean clean_appcores \
+ lib libcores lib_allendians lib_clean clean_libcores clean_lib_allendians \
+ all all_cpp comp_libs comp_libs_clean examples examples_clean clean package $(comp_PKG_LIST_ALL) \
+ doxygen release tar lib lib_clean \
+ $(lib_BOARD_SOC_LIST_ALL) $(lib_CORE_LIST_ALL) $(lib_LIB_ENDIAN_LIST) $(lib_BOARD_SOC_LIST_ALL_CLEAN) \
+ $(lib_CORE_LIST_ALL_CLEAN) $(lib_LIB_ENDIAN_LIST_CLEAN) \
+ $(app_lib_BOARD_SOC_LIST_ALL) $(app_lib_CORE_LIST_ALL) $(app_lib_LIB_ENDIAN_LIST) \
+ $(firm_SOC_LIST_ALL) $(firm_CORE_LIST_ALL) $(firm_VERSION_LIST_ALL) $(firm_VERSION_LIST_ALL_CLEAN) $(firm_SOC_LIST_ALL_CLEAN) $(firm_CORE_LIST_ALL_CLEAN) \
+ $(app_lib_BOARD_SOC_LIST_ALL_CLEAN) $(app_lib_CORE_LIST_ALL_CLEAN) $(app_lib_LIB_ENDIAN_LIST_CLEAN) \
+ $(app_BOARD_LIST_ALL) $(app_CORE_LIST_ALL) $(app_BOARD_LIST_ALL_CLEAN) $(app_CORE_LIST_ALL_CLEAN)
+
+
+all: lib firm app_lib apps
+
+clean: lib_clean firm_clean app_lib_clean app_clean
+
+ifeq ($(lib_$(COMP)_BUILD_DEPENDENCY),soc)
+$(lib_BOARD_SOC_LIST_ALL):
+ $(MAKE) libcores SOC=$(subst _lib,,$@)
+endif
+ifeq ($(lib_$(COMP)_BUILD_DEPENDENCY),board)
+$(lib_BOARD_SOC_LIST_ALL):
+ $(MAKE) libcores BOARD=$(subst _lib,,$@)
+endif
+
+all_cpp: lib app_lib
+
+$(lib_CORE_LIST_ALL):
+ $(MAKE) lib_allendians CORE=$(subst _lib,,$@) BUILD_PROFILE_$(subst _lib,,$@)=$(BUILD_PROFILE)
+
+$(lib_LIB_ENDIAN_LIST):
+ $(MAKE) comp_libs ENDIAN=$(subst _lib,,$@)
+
+ifeq ($(lib_$(COMP)_BUILD_DEPENDENCY),soc)
+$(lib_BOARD_SOC_LIST_ALL_CLEAN):
+ $(MAKE) clean_libcores SOC=$(subst _lclean,,$@)
+endif
+ifeq ($(lib_$(COMP)_BUILD_DEPENDENCY),board)
+$(lib_BOARD_SOC_LIST_ALL_CLEAN):
+ $(MAKE) clean_libcores BOARD=$(subst _lclean,,$@)
+endif
+
+$(lib_CORE_LIST_ALL_CLEAN):
+ $(MAKE) clean_lib_allendians CORE=$(subst _lclean,,$@) BUILD_PROFILE_$(subst _lclean,,$@)=$(BUILD_PROFILE)
+
+$(lib_LIB_ENDIAN_LIST_CLEAN):
+ $(MAKE) comp_libs_clean ENDIAN=$(subst _lclean,,$@)
+
+$(app_lib_BOARD_SOC_LIST_ALL):
+ $(MAKE) app_libcores BOARD=$(subst _app_lib,,$@)
+
+$(firm_SOC_LIST_ALL):
+ $(MAKE) firmcores SOC=$(subst _firm,,$@)
+
+$(firm_CORE_LIST_ALL):
+ $(MAKE) firm_allhostcores CORE=$(subst _firm,,$@)
+
+$(firm_HOST_CORE_LIST):
+ $(MAKE) firm_allversion HOSTCORE=$(subst _firm,,$@)
+
+$(firm_VERSION_LIST_ALL):
+ $(MAKE) comp_firm PRUVERSION=$(subst _firm,,$@)
+
+$(app_lib_CORE_LIST_ALL):
+ $(MAKE) app_lib_allendians CORE=$(subst _app_lib,,$@) BUILD_PROFILE_$(subst _app_lib,,$@)=$(BUILD_PROFILE)
+$(firm_SOC_LIST_ALL_CLEAN):
+ $(MAKE) clean_firmcores SOC=$(subst _fclean,,$@)
+
+$(app_lib_LIB_ENDIAN_LIST):
+ $(MAKE) comp_app_libs ENDIAN=$(subst _app_lib,,$@)
+$(firm_CORE_LIST_ALL_CLEAN):
+ $(MAKE) clean_firm_allhostcores CORE=$(subst _fclean,,$@)
+
+$(firm_HOST_CORE_LIST_CLEAN):
+ $(MAKE) clean_firm_allversion HOSTCORE=$(subst _fclean,,$@)
+
+$(firm_VERSION_LIST_ALL_CLEAN):
+ $(MAKE) comp_firm_clean PRUVERSION=$(subst _fclean,,$@)
+
+$(app_lib_BOARD_SOC_LIST_ALL_CLEAN):
+ $(MAKE) clean_app_libcores BOARD=$(subst _app_lclean,,$@)
+
+$(app_lib_CORE_LIST_ALL_CLEAN):
+ $(MAKE) clean_app_lib_allendians CORE=$(subst _app_lclean,,$@) BUILD_PROFILE_$(subst _app_lclean,,$@)=$(BUILD_PROFILE)
+
+$(app_lib_LIB_ENDIAN_LIST_CLEAN):
+ $(MAKE) comp_app_libs_clean ENDIAN=$(subst _app_lclean,,$@)
+
+$(app_BOARD_LIST_ALL):
+ $(MAKE) appcores BOARD=$(subst _app,,$@)
+
+$(app_CORE_LIST_ALL):
+ifeq ($(CPLUSPLUS_BUILD), yes)
+ $(ECHO) "Skipping the application build for C++"
+else
+ $(MAKE) examples CORE=$(subst _app,,$@) BUILD_PROFILE_$(subst _app,,$@)=$(BUILD_PROFILE)
+endif
+
+$(app_BOARD_LIST_ALL_CLEAN):
+ $(MAKE) clean_appcores BOARD=$(subst _aclean,,$@)
+
+$(app_CORE_LIST_ALL_CLEAN):
+ $(MAKE) examples_clean CORE=$(subst _aclean,,$@) BUILD_PROFILE_$(subst _aclean,,$@)=$(BUILD_PROFILE)
+
+xdc_meta:
+ $(XDC) XDCBUILDCFG=config_mk.bld
+
+xdc_meta_clean:
+ $(XDC) clean XDCBUILDCFG=config_mk.bld
+
+.PHONY: designdoc_html
+designdoc_html:
+ $(SPHINXBUILD) -b html $(ALLSPHINXOPTS) $(DESIGNDOC_ROOT)/build/html
+ @echo
+ @echo "Build finished. The HTML pages are in $(DESIGNDOC_ROOT)/build/html."
+
+.PHONY: designdoc_singlehtml
+designdoc_singlehtml:
+ $(SPHINXBUILD) -b singlehtml $(ALLSPHINXOPTS) $(DESIGNDOC_ROOT)/build/singlehtml
+ @echo
+ @echo "Build finished. The HTML page is in $(DESIGNDOC_ROOT)/build/singlehtml."
+
+.PHONY: designdoc_latexpdf
+designdoc_latexpdf:
+ $(SPHINXBUILD) -b latex $(ALLSPHINXOPTS) $(DESIGNDOC_ROOT)/build/latex
+ @echo "Running LaTeX files through pdflatex..."
+ $(MAKE) -C $(DESIGNDOC_ROOT)/build/latex all-pdf
+ @echo "pdflatex finished; the PDF files are in $(DESIGNDOC_ROOT)/build/latex."
+
+.PHONY: designdoc
+designdoc:
+#For design documentation
+ifeq ($(OS),linux)
+ifeq ($($(COMP)_DESIGNDOC_HTML_SUPPORT),yes)
+ $(ECHO) Creating html design documentation ...
+ make designdoc_html
+endif
+ifeq ($($(COMP)_DESIGNDOC_SINGLEHTML_SUPPORT),yes)
+ $(ECHO) Creating singlehtml design documentation ...
+ make designdoc_singlehtml
+endif
+ifeq ($($(COMP)_DESIGNDOC_LATEXPDF_SUPPORT),yes)
+ $(ECHO) Creating latexpdf design documentation ...
+ make designdoc_latexpdf
+endif
+endif
+
+.PHONY: designdoc_clean
+designdoc_clean:
+#For design documentation
+ifeq ($(OS),linux)
+ rm -rf $(DESIGNDOC_ROOT)/build/*
+endif
+
+doxygen:
+ifeq ($(DOXYGEN_SUPPORT),yesyes)
+ $(ECHO) Creating Doxygen API guide ...
+ @doxygen docs/Doxyfile
+else
+ $(ECHO) No Doxygen Support available ...
+endif
+
+clean_doxygen:
+ifeq ($(DOXYGEN_SUPPORT),yesyes)
+ $(ECHO) cleaned Doxygen API guide ...
+ $(RM) -rf docs/doxygen
+else
+ $(ECHO) No Doxygen Support available ...
+endif
+
+tar: lib firm xdc_meta doxygen
+ $(ECHO) Creating the Release Tar ball for $(COMP)...
+ $(XDC) clean XDCBUILDCFG=config_mk.bld
+ $(XDC) release XDCBUILDCFG=config_mk.bld
+ $(ECHO) please check $(COMP)/packages folder for the release tarball
+
+lib: $(lib_BOARD_SOC_LIST_ALL)
+
+# First build the libraries for base cores, then followed by the rest
+libcores: libcores_base_cores
+ $(MAKE) libcores_rest_cores
+
+libcores_base_cores: $(lib_CORE_LIST_BASE)
+libcores_rest_cores: $(lib_CORE_LIST_REST)
+
+lib_allendians: $(lib_LIB_ENDIAN_LIST)
+
+lib_clean: $(lib_BOARD_SOC_LIST_ALL_CLEAN)
+
+clean_libcores:$(lib_CORE_LIST_ALL_CLEAN)
+
+clean_lib_allendians: $(lib_LIB_ENDIAN_LIST_CLEAN)
+
+app_lib: $(app_lib_BOARD_SOC_LIST_ALL)
+
+firm: $(firm_SOC_LIST_ALL)
+
+app_libcores: $(app_lib_CORE_LIST_ALL)
+firmcores: $(firm_CORE_LIST_ALL)
+
+app_lib_allendians: $(app_lib_LIB_ENDIAN_LIST)
+firm_allhostcores: $(firm_HOST_CORE_LIST)
+firm_allversion: $(firm_VERSION_LIST_ALL)
+app_lib_clean: $(app_lib_BOARD_SOC_LIST_ALL_CLEAN)
+firm_clean: $(firm_SOC_LIST_ALL_CLEAN)
+
+clean_app_libcores:$(app_lib_CORE_LIST_ALL_CLEAN)
+clean_firmcores: $(firm_CORE_LIST_ALL_CLEAN)
+clean_firm_allversion: $(firm_VERSION_LIST_ALL_CLEAN)
+clean_app_lib_allendians: $(app_lib_LIB_ENDIAN_LIST_CLEAN)
+clean_firm_allhostcores: $(firm_HOST_CORE_LIST_CLEAN)
+
+apps: $(app_BOARD_LIST_ALL)
+
+appcores: $(app_CORE_LIST_ALL)
+
+app_clean: $(app_BOARD_LIST_ALL_CLEAN)
+
+clean_appcores: $(app_CORE_LIST_ALL_CLEAN)
+
+comp_all: lib_allendians app_lib_allendians examples firm_allhostcores
+
+comp_clean: clean_lib_allendians clean_app_lib_allendians examples_clean clean_firm_allhostcores
+
+comp_libs: $($(COMP)_LIB_LIST)
+
+comp_libs_clean: $(comp_LIB_LIST_CLEAN)
+
+comp_app_libs: $($(COMP)_APP_LIB_LIST)
+comp_firm: $($(COMP)_FIRM_LIST)
+
+comp_app_libs_clean: $(comp_APP_LIB_LIST_CLEAN)
+comp_firm_clean: $(comp_FIRM_LIST_CLEAN)
+
+examples: $($(COMP)_EXAMPLE_LIST)
+
+examples_clean: $(comp_EXAMPLE_LIST_CLEAN)
+
+package: $(comp_PKG_LIST_PACKAGE)
+
+release: lib tar firm
+
+#=================================================================
+#COMP libs app_libs and apps
+$(comp_PKG_LIST_ALL):
+ $(if $(filter $(SOC), $(subst emptyreplacement,,$($@_SOCLIST))),\
+ $(if $(filter $(CORE), $(subst emptyreplacement,,$($@_$(SOC)_CORELIST))),\
+ $(if $(filter yes, $(subst emptyreplacement,,$($@_XDC_CONFIGURO))),\
+ $(MAKE) -C $($@_PATH) $($@_MAKEFILE) xdc_configuro,),),\
+ $(if $(filter $(BOARD), $(subst emptyreplacement,,$($@_BOARDLIST))),\
+ $(if $(filter $(CORE), $(subst emptyreplacement,,$($@_$(SOC)_CORELIST))),\
+ $(if $(filter yes, $(subst emptyreplacement,,$($@_XDC_CONFIGURO))),\
+ $(MAKE) -C $($@_PATH) $($@_MAKEFILE) xdc_configuro,),),))
+ $(if $(filter $(SOC), $(subst emptyreplacement,,$($@_SOCLIST))),\
+ $(if $(filter $(CORE), $(subst emptyreplacement,,$($@_$(SOC)_CORELIST))),\
+ $(MAKE) -C $($@_PATH) $($@_MAKEFILE),$(ECHO) Nothing to be done for $(SOC) $(CORE) $@),\
+ $(if $(filter $(BOARD), $(subst emptyreplacement,,$($@_BOARDLIST))),\
+ $(if $(filter $(CORE), $(subst emptyreplacement,,$($@_$(SOC)_CORELIST))),\
+ $(MAKE) -C $($@_PATH) $($@_MAKEFILE),$(ECHO) Nothing to be done for $(BOARD) $(SOC) $(CORE) $@),$(ECHO) Nothing to be done for $(SOC) $@))
+ $(if $(filter $(SOC), $(subst emptyreplacement,,$($@_SOCLIST))),\
+ $(if $(filter $(CORE), $(subst emptyreplacement,,$($@_$(SOC)_CORELIST))),\
+ $(if $(filter yes, $(subst emptyreplacement,,$($@_SBL_IMAGEGEN))),\
+ $(MAKE) -C $($@_PATH) $($@_MAKEFILE) sbl_imagegen,),),\
+ $(if $(filter $(BOARD), $(subst emptyreplacement,,$($@_BOARDLIST))),\
+ $(if $(filter $(CORE), $(subst emptyreplacement,,$($@_$(SOC)_CORELIST))),\
+ $(if $(filter yes, $(subst emptyreplacement,,$($@_SBL_IMAGEGEN))),\
+ $(MAKE) -C $($@_PATH) $($@_MAKEFILE) sbl_imagegen,),),))
+ $(if $(filter $(SOC), $(subst emptyreplacement,,$($@_SOCLIST))),\
+ $(if $(filter $(CORE), $(subst emptyreplacement,,$($@_$(SOC)_CORELIST))),\
+ $(if $(filter yes, $(subst emptyreplacement,,$($@_SBL_APPIMAGEGEN))),\
+ $(MAKE) -C $($@_PATH) $($@_MAKEFILE) sbl_appimagegen,),),\
+ $(if $(filter $(BOARD), $(subst emptyreplacement,,$($@_BOARDLIST))),\
+ $(if $(filter $(CORE), $(subst emptyreplacement,,$($@_$(SOC)_CORELIST))),\
+ $(if $(filter yes, $(subst emptyreplacement,,$($@_SBL_APPIMAGEGEN))),\
+ $(MAKE) -C $($@_PATH) $($@_MAKEFILE) sbl_appimagegen,),),))
+
+$(comp_PKG_LIST_ALL_CLEAN):
+ $(if $(filter $(SOC), $(subst emptyreplacement,,$($(subst _clean,,$@)_SOCLIST))),\
+ $(MAKE) -C $($(subst _clean,,$@)_PATH) $($(subst _clean,,$@)_MAKEFILE) clean,\
+ $(if $(filter $(BOARD), $(subst emptyreplacement,,$($(subst _clean,,$@)_BOARDLIST))),\
+ $(MAKE) -C $($(subst _clean,,$@)_PATH) $($(subst _clean,,$@)_MAKEFILE) clean,))
+
+$(comp_PKG_LIST_PACKAGE):
+ $(if $(filter $(SOC), $(subst emptyreplacement,,$($(subst _package,,$@)_SOCLIST))),\
+ $(MAKE) -C $($(subst _package,,$@)_PATH) $($(subst _package,,$@)_MAKEFILE) package,\
+ $(if $(filter $(BOARD), $(subst emptyreplacement,,$($(subst _package,,$@)_BOARDLIST))),\
+ $(MAKE) -C $($(subst _package,,$@)_PATH) $($(subst _package,,$@)_MAKEFILE) package,$(ECHO) Nothing to be done for $(SOC) $(subst _package,,$@)))
+
+#Below is used only for checking c++ build errors during development, not to be used for any other purpose
+cplusplus_build:
+ $(MAKE) all_cpp BUILD_PROFILE=debug CPLUSPLUS_BUILD=yes
+
+# Nothing beyond this point
diff --git a/packages/ti/build/docs/PDK_build_SoftwareManifest.doc b/packages/ti/build/docs/PDK_build_SoftwareManifest.doc
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diff --git a/packages/ti/build/docs/makerules_spec.doc b/packages/ti/build/docs/makerules_spec.doc
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diff --git a/packages/ti/build/dra7xx/linkcmd.xdt b/packages/ti/build/dra7xx/linkcmd.xdt
--- /dev/null
@@ -0,0 +1,52 @@
+%/*
+% * ======== linkcmd.xdt ========
+% * This is template file illustrates how one can filter the linker command
+% * file that is normally generated from the template supplied by the
+% * executable's platform. This allows one to update the platform without
+% * having to update this file.
+% *
+% * This template is expanded after the configuration script runs and the
+% * results placed in a file (with extension .xdl) associated with the
+% * executable.
+% *
+% * Linker templates are passed the following arguments:
+% * $out - an open file stream for the generated linker
+% * command file
+% * $args - an array of zero or more libraries that should be linked
+% * with (in the order they appear in the argument list)
+% *
+% * These arguments are available via the standard Javascript arguments
+% * array; the first argument can also be accessed via the name "$out".
+% * In addition to these arguments, there is a global variable named
+% * 'this' that is set as follows:
+% * this - the program object
+% */
+%/* generate original command file from template into orig.xdl */
+%var tfile = this.platform.getLinkTemplate(this);
+%var template = xdc.loadTemplate(tfile);
+%template.genFile("orig.xdl", this, $args);
+%
+%/* read and output generated linker command file */
+%var line;
+//%var dir;
+%var file = new java.io.BufferedReader(java.io.FileReader("orig.xdl"));
+
+%while ((line = file.readLine()) != null)
+%{
+ `String(line)`
+%}
+%/* Output the always required libraries to the linker command file */
+
+/* Provide virtual address locations for OCMC_RAM used by IPU applications
+ * using AMMU.
+ */
+MEMORY
+{
+ /* OCMC_RAM1 mapped to 0x40300000 */
+ OCMC_RAM1_VIRT: org = 0x00300000 len = 0x00040000
+%if (Program.build.cfgArgs.SOC.toLowerCase() == "dra75x")
+%{
+ /* OCMC_RAM2 mapped to 0x40400000 */
+ OCMC_RAM2_VIRT: org = 0x00400000 len = 0x00040000
+%}
+}
diff --git a/packages/ti/build/j7200/config_j7200_a72.bld b/packages/ti/build/j7200/config_j7200_a72.bld
--- /dev/null
@@ -0,0 +1,42 @@
+/*
+* Copyright (c) 2019, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* * Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* * Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the distribution.
+*
+* * Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+/*
+ * ======== config_j7200_a72.bld ========
+ * Common build configuration script for BIOS
+ */
+
+var gccArmTargets = xdc.loadPackage('gnu.targets.arm');
+gccArmTargets.A53F.rootDir = java.lang.System.getenv("CGTOOLS_A72");
+gccArmTargets.A53F.bspLib = "rdimon";
+
+Build.targets = [ gccArmTargets.A53F ];
diff --git a/packages/ti/build/j7200/config_j7200_c7x.bld b/packages/ti/build/j7200/config_j7200_c7x.bld
--- /dev/null
@@ -0,0 +1,40 @@
+/*
+* Copyright (c) 2019, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* * Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* * Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the distribution.
+*
+* * Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+/*
+ * ======== config_j7200_c7x.bld ========
+ * Build configuration script for BSP drivers
+ */
+/* load the required modules for the configuration */
+var C7x = xdc.useModule('ti.targets.elf.C71');
+/* C7x compiler directory path */
+C7x.rootDir = java.lang.System.getenv("C7X_GEN_INSTALL_PATH");
diff --git a/packages/ti/build/j7200/config_j7200_r5f.bld b/packages/ti/build/j7200/config_j7200_r5f.bld
--- /dev/null
@@ -0,0 +1,40 @@
+/*
+* Copyright (c) 2019, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* * Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* * Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the distribution.
+*
+* * Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+/*
+ * ======== config_j7200_r5.bld ========
+ * Build configuration script for BSP drivers
+ */
+/* load the required modules for the configuration */
+var R5F = xdc.useModule('ti.targets.arm.elf.R5F');
+/* R5F compiler directory path */
+R5F.rootDir = java.lang.System.getenv("CGTOOLS");
diff --git a/packages/ti/build/j7200/linker_a72_mpu1_0.lds b/packages/ti/build/j7200/linker_a72_mpu1_0.lds
--- /dev/null
@@ -0,0 +1,197 @@
+__STACK_SIZE = 0x20000;
+__TI_STACK_SIZE = __STACK_SIZE;
+
+MEMORY
+{
+ OCMCRAM : ORIGIN = 0x000041C00000, LENGTH = 0x00080000 /* MCUSS-OCMC RAM - 512KB */
+
+
+ DDR_MPU1 (RWX) : ORIGIN = 0x80000000, LENGTH = 0x08000000
+ DDR_IPC (RWX) : ORIGIN = 0x90000000, LENGTH = 0x02000000
+
+ /* j7200 MCMS3 locations */
+ /* j7200 Reserved Memory for ARM Trusted Firmware */
+ MSMC3_ARM_FW (RWIX) : ORIGIN = 0x000070000000, LENGTH = 0x40000 /* 256KB */
+ BOOTVECTOR : ORIGIN = 0x000070040000, LENGTH = 0x1000 /* 4KB */
+ BOOTVECTOR_EL3 : ORIGIN = 0x000070041000, LENGTH = 0x1000 /* 4KB */
+ MSMC_MPU1 (RWX) : ORIGIN = 0x000070042000, LENGTH = 0x7AE000 /* 7864KB */
+ /* j7200 Reserved Memory for DMSC Firmware */
+ MSMC3_DMSC_FW (RWIX) : ORIGIN = 0x0000707F0000, LENGTH = 0x10000 /* 64KB */
+}
+REGION_ALIAS("REGION_TEXT_EL3", DDR_MPU1);
+REGION_ALIAS("REGION_TEXT", DDR_MPU1);
+REGION_ALIAS("REGION_BSS", DDR_MPU1);
+REGION_ALIAS("REGION_DATA", DDR_MPU1);
+REGION_ALIAS("REGION_STACK", DDR_MPU1);
+REGION_ALIAS("REGION_HEAP", DDR_MPU1);
+REGION_ALIAS("REGION_ARM_EXIDX", DDR_MPU1);
+REGION_ALIAS("REGION_ARM_EXTAB", DDR_MPU1);
+REGION_ALIAS("REGION_TEXT_STARTUP", DDR_MPU1);
+REGION_ALIAS("REGION_DATA_BUFFER", DDR_MPU1);
+REGION_ALIAS("IPC_DATA_BUFFER_1", DDR_MPU1);
+
+SECTIONS {
+
+ .vecs : {
+ *(.vecs)
+ } > BOOTVECTOR AT> BOOTVECTOR
+
+ .vectors : {
+ *(.vectors)
+ } > BOOTVECTOR_EL3 AT> BOOTVECTOR_EL3
+ .text.el3 : {
+ *(.text.el3)
+ /* Ensure 8-byte alignment for descriptors and ensure inclusion */
+ . = ALIGN(8);
+ __RT_SVC_DESCS_START__ = .;
+ KEEP(*(rt_svc_descs))
+ __RT_SVC_DESCS_END__ = .;
+ } > REGION_TEXT_EL3 AT> REGION_TEXT_EL3
+
+ .text.csl_a72_startup : {
+ *(.text.csl_a72_startup)
+ *(.Entry)
+ } > REGION_TEXT_STARTUP AT> REGION_TEXT_STARTUP
+
+ .text : {
+ CREATE_OBJECT_SYMBOLS
+ *(.text)
+ *(.text.*)
+ . = ALIGN(0x8);
+ KEEP (*(.ctors))
+ . = ALIGN(0x4);
+ KEEP (*(.dtors))
+ . = ALIGN(0x8);
+ __init_array_start = .;
+ KEEP (*(.init_array*))
+ __init_array_end = .;
+ *(.init)
+ *(.fini*)
+ } > REGION_TEXT AT> REGION_TEXT
+
+ PROVIDE (__etext = .);
+ PROVIDE (_etext = .);
+ PROVIDE (etext = .);
+
+ .rodata : {
+ *(.rodata)
+ *(.rodata*)
+ } > REGION_TEXT AT> REGION_TEXT
+
+ .data_buffer : ALIGN (8) {
+ __data_buffer_load__ = LOADADDR (.data_buffer);
+ __data_buffer_start__ = .;
+ *(.data_buffer)
+ *(.data_buffer*)
+ . = ALIGN (8);
+ __data_buffer_end__ = .;
+ } > REGION_DATA_BUFFER AT> REGION_DATA_BUFFER
+
+ .data : ALIGN (8) {
+ __data_load__ = LOADADDR (.data);
+ __data_start__ = .;
+ *(.data)
+ *(.data*)
+ . = ALIGN (8);
+ __data_end__ = .;
+ } > REGION_DATA AT> REGION_TEXT
+
+ .ARM.exidx : {
+ __exidx_start = .;
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ __exidx_end = .;
+ } > REGION_ARM_EXIDX AT> REGION_ARM_EXIDX
+
+ .ARM.extab : {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > REGION_ARM_EXTAB AT> REGION_ARM_EXTAB
+
+ .bss:extMemCache:ramdisk : {
+ } > DDR_MPU1 /* MSMC_MPU1 */
+
+ /* USB or any other LLD buffer for benchmarking */
+ .benchmark_buffer (NOLOAD) : ALIGN (32) {
+ } > DDR_MPU1
+
+ .bss:frameBuffer (NOLOAD) : ALIGN (32) {
+ } > DDR_MPU1
+
+ ipc_data_buffer (NOLOAD) : ALIGN (32) {
+ } > IPC_DATA_BUFFER_1
+
+ /* For NDK packet memory, we need to map this sections before .bss*/
+ .bss:NDK_PACKETMEM (NOLOAD) : ALIGN (128) {} > DDR_MPU1
+ .bss:NDK_MMBUFFER (NOLOAD) : ALIGN (128) {} > DDR_MPU1
+
+ .bss : {
+ __bss_start__ = .;
+ *(.shbss)
+ *(.bss)
+ *(.bss.*)
+ . = ALIGN (8);
+ __bss_end__ = .;
+ . = ALIGN (8);
+ *(COMMON)
+ } > REGION_BSS AT> REGION_BSS
+
+ .heap : {
+ __heap_start__ = .;
+ end = __heap_start__;
+ _end = end;
+ __end = end;
+ KEEP(*(.heap))
+ __heap_end__ = .;
+ __HeapLimit = __heap_end__;
+ } > REGION_HEAP AT> REGION_HEAP
+
+ .stack (NOLOAD) : ALIGN(16) {
+ _stack = .;
+ __stack = .;
+ KEEP(*(.stack))
+ } > REGION_STACK AT> REGION_STACK
+
+ __TI_STACK_BASE = __stack;
+
+ /* Stabs debugging sections. */
+ .stab 0 : { *(.stab) }
+ .stabstr 0 : { *(.stabstr) }
+ .stab.excl 0 : { *(.stab.excl) }
+ .stab.exclstr 0 : { *(.stab.exclstr) }
+ .stab.index 0 : { *(.stab.index) }
+ .stab.indexstr 0 : { *(.stab.indexstr) }
+ .comment 0 : { *(.comment) }
+ /*
+ * DWARF debug sections.
+ * Symbols in the DWARF debugging sections are relative to the beginning
+ * of the section so we begin them at 0.
+ */
+ /* DWARF 1 */
+ .debug 0 : { *(.debug) }
+ .line 0 : { *(.line) }
+ /* GNU DWARF 1 extensions */
+ .debug_srcinfo 0 : { *(.debug_srcinfo) }
+ .debug_sfnames 0 : { *(.debug_sfnames) }
+ /* DWARF 1.1 and DWARF 2 */
+ .debug_aranges 0 : { *(.debug_aranges) }
+ .debug_pubnames 0 : { *(.debug_pubnames) }
+ /* DWARF 2 */
+ .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
+ .debug_abbrev 0 : { *(.debug_abbrev) }
+ .debug_line 0 : { *(.debug_line .debug_line.* .debug_line_end ) }
+ .debug_frame 0 : { *(.debug_frame) }
+ .debug_str 0 : { *(.debug_str) }
+ .debug_loc 0 : { *(.debug_loc) }
+ .debug_macinfo 0 : { *(.debug_macinfo) }
+ /* SGI/MIPS DWARF 2 extensions */
+ .debug_weaknames 0 : { *(.debug_weaknames) }
+ .debug_funcnames 0 : { *(.debug_funcnames) }
+ .debug_typenames 0 : { *(.debug_typenames) }
+ .debug_varnames 0 : { *(.debug_varnames) }
+ /* DWARF 3 */
+ .debug_pubtypes 0 : { *(.debug_pubtypes) }
+ .debug_ranges 0 : { *(.debug_ranges) }
+ /* DWARF Extension. */
+ .debug_macro 0 : { *(.debug_macro) }
+ .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }
+ /DISCARD/ : { *(.note.GNU-stack) *(.gnu_debuglink) *(.gnu.lto_*) }
+}
diff --git a/packages/ti/build/j7200/linker_c7x.lds b/packages/ti/build/j7200/linker_c7x.lds
--- /dev/null
@@ -0,0 +1,121 @@
+/*
+ *
+ * Copyright (c) 2018 Texas Instruments Incorporated
+ *
+ * All rights reserved not granted herein.
+ *
+ * Limited License.
+ *
+ * Texas Instruments Incorporated grants a world-wide, royalty-free, non-exclusive
+ * license under copyrights and patents it now or hereafter owns or controls to make,
+ * have made, use, import, offer to sell and sell ("Utilize") this software subject to the
+ * terms herein. With respect to the foregoing patent license, such license is granted
+ * solely to the extent that any such patent is necessary to Utilize the software alone.
+ * The patent license shall not apply to any combinations which include this software,
+ * other than combinations with devices manufactured by or for TI ("TI Devices").
+ * No hardware patent is licensed hereunder.
+ *
+ * Redistributions must preserve existing copyright notices and reproduce this license
+ * (including the above copyright notice and the disclaimer and (if applicable) source
+ * code license limitations below) in the documentation and/or other materials provided
+ * with the distribution
+ *
+ * Redistribution and use in binary form, without modification, are permitted provided
+ * that the following conditions are met:
+ *
+ * * No reverse engineering, decompilation, or disassembly of this software is
+ * permitted with respect to any software provided in binary form.
+ *
+ * * any redistribution and use are licensed by TI for use only with TI Devices.
+ *
+ * * Nothing shall obligate TI to provide you with source code for the software
+ * licensed and provided to you in object code.
+ *
+ * If software source code is provided to you, modification and redistribution of the
+ * source code are permitted provided that the following conditions are met:
+ *
+ * * any redistribution and use of the source code, including any resulting derivative
+ * works, are licensed by TI for use only with TI Devices.
+ *
+ * * any redistribution and use of any object code compiled from the source code
+ * and any resulting derivative works, are licensed by TI for use only with TI Devices.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of its suppliers
+ *
+ * may be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * DISCLAIMER.
+ *
+ * THIS SOFTWARE IS PROVIDED BY TI AND TI'S LICENSORS "AS IS" AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL TI AND TI'S LICENSORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+-c
+-heap 0x20000
+-stack 0x20000
+--args 0x1000
+--diag_suppress=10068 /* "no matching section" */
+--cinit_compression=off
+--retain="*(xdc.meta)"
+
+#define DDR0_ALLOCATED_START 0xA0000000
+#define C7X_ALLOCATED_START DDR0_ALLOCATED_START + 0x08000000
+
+#define C7X_EXT_DATA_BASE (C7X_ALLOCATED_START + 0x00100000)
+#define C7X_MEM_TEXT_BASE (C7X_ALLOCATED_START + 0x00200000)
+#define C7X_MEM_DATA_BASE (C7X_ALLOCATED_START + 0x00300000)
+#define C7X_DDR_SPACE_BASE (C7X_ALLOCATED_START + 0x00400000)
+
+MEMORY
+{
+ L2SRAM (RWX): org = 0x64800000, len = 0x00070000
+ DDR0_RESERVED: org = 0x80000000, len = 0x20000000 /* 512MB Reserved for A72 OS */
+ C7X_IPC_D: org = C7X_ALLOCATED_START, len = 0x00100000 /* 1MB DDR */
+ C7X_EXT_D: org = C7X_EXT_DATA_BASE, len = 0x00100000 /* 1MB DDR */
+ C7X_TEXT: org = C7X_MEM_TEXT_BASE, len = 0x00100000 /* 1MB DDR */
+ C7X_DATA: org = C7X_MEM_DATA_BASE, len = 0x00100000 /* 1MB DDR */
+ C7X_DDR_SPACE: org = C7X_DDR_SPACE_BASE, len = 0x00C00000 /* 12MB DDR */
+}
+
+SECTIONS
+{
+ xdc.meta (COPY): { } > C7X_DDR_SPACE
+ boot:
+ {
+ boot.*<boot.oe71>(.text)
+ } load > C7X_TEXT ALIGN(0x200000)
+ .vecs > C7X_DDR_SPACE ALIGN(0x400000)
+ .text > C7X_DDR_SPACE ALIGN(0x200000)
+
+ .bss > C7X_DDR_SPACE /* Zero-initialized data */
+ .data > C7X_DDR_SPACE /* Initialized data */
+
+ .cinit > C7X_DDR_SPACE /* could be part of const */
+ .init_array > C7X_DDR_SPACE /* C++ initializations */
+ .stack > C7X_DDR_SPACE ALIGN(0x2000)
+ .args > C7X_DDR_SPACE
+ .cio > C7X_DDR_SPACE
+ .const > C7X_DDR_SPACE
+ .switch > C7X_DDR_SPACE /* For exception handling. */
+ .sysmem > C7X_DDR_SPACE /* heap */
+
+ GROUP: > C7X_DDR_SPACE
+ {
+ .data.ti_sysbios_family_c7x_Mmu_tableArray : type=NOINIT
+ .data.ti_sysbios_family_c7x_Mmu_tableArraySlot : type=NOINIT
+ .data.ti_sysbios_family_c7x_Mmu_level1Table : type=NOINIT
+ }
+
+ ipc_data_buffer: > C7X_DDR_SPACE
+ .resource_table: { __RESOURCE_TABLE = .;} > C7X_EXT_D
+}
diff --git a/packages/ti/build/j7200/linker_r5.lds b/packages/ti/build/j7200/linker_r5.lds
--- /dev/null
@@ -0,0 +1,97 @@
+/* Linker Settings */
+--retain="*(.bootCode)"
+--retain="*(.startupCode)"
+--retain="*(.startupData)"
+--retain="*(.intvecs)"
+--retain="*(.intc_text)"
+--retain="*(.rstvectors)"
+--retain="*(.irqStack)"
+--retain="*(.fiqStack)"
+--retain="*(.abortStack)"
+--retain="*(.undStack)"
+--retain="*(.svcStack)"
+--fill_value=0
+--stack_size=0x2000
+--heap_size=0x1000
+--entry_point=_resetvectors /* Default C RTS boot.asm */
+
+-stack 0x2000 /* SOFTWARE STACK SIZE */
+-heap 0x2000 /* HEAP AREA SIZE */
+
+/* Stack Sizes for various modes */
+__IRQ_STACK_SIZE = 0x1000;
+__FIQ_STACK_SIZE = 0x1000;
+__ABORT_STACK_SIZE = 0x1000;
+__UND_STACK_SIZE = 0x1000;
+__SVC_STACK_SIZE = 0x1000;
+
+/* Memory Map */
+MEMORY
+{
+ VECTORS (X) : origin=0x41C7F000 length=0x1000
+ /* Reset Vectors base address(RESET_VECTORS) should be 64 bytes aligned */
+ RESET_VECTORS (X) : origin=0x41C00000 length=0x100
+ /* MCU0_R5F_0 local view */
+ MCU0_R5F_TCMA_SBL_RSVD (X) : origin=0x0 length=0x100
+ MCU0_R5F_TCMA (X) : origin=0x100 length=0x8000 - 0x100
+ MCU0_R5F_TCMB0 (RWIX) : origin=0x41010000 length=0x8000
+
+ /* MCU0_R5F_1 SoC view */
+ MCU0_R5F1_ATCM (RWIX) : origin=0x41400000 length=0x8000
+ MCU0_R5F1_BTCM (RWIX) : origin=0x41410000 length=0x8000
+
+ /* MCU0 share locations */
+ OCMRAM (RWIX) : origin=0x41C00100 length=0x80000 - 0x1100 /* ~510KB */
+
+ /* j7200 MCMS3 locations */
+ /* j7200 Reserved Memory for ARM Trusted Firmware */
+ MSMC3_ARM_FW (RWIX) : origin=0x70000000 length=0x40000 /* 256KB */
+ MSMC3 (RWIX) : origin=0x70040000 length=0x7B0000 /* 8MB - 320KB */
+ /* j7200 Reserved Memory for DMSC Firmware */
+ MSMC3_DMSC_FW (RWIX) : origin=0x707F0000 length=0x10000 /* 64KB */
+
+ DDR0 (RWIX) : origin=0x80000000 length=0x80000000 /* 2GB */
+}
+
+/* Section Configuration */
+SECTIONS
+{
+ /* 'intvecs' and 'intc_text' sections shall be placed within */
+ /* a range of +\- 16 MB */
+ .intvecs : {} palign(8) > VECTORS
+ .intc_text : {} palign(8) > VECTORS
+ .rstvectors : {} palign(8) > RESET_VECTORS
+ .bootCode : {} palign(8) > MSMC3
+ .startupCode : {} palign(8) > MSMC3
+ .startupData : {} palign(8) > MSMC3, type = NOINIT
+ .text : {} palign(8) > DDR0
+ .const : {} palign(8) > DDR0
+ .cinit : {} palign(8) > DDR0
+ .pinit : {} palign(8) > DDR0
+ .bss : {} align(4) > DDR0
+ .far : {} align(4) > DDR0
+ .data : {} palign(128) > DDR0
+ .boardcfg_data : {} palign(128) > MSMC3
+ .sysmem : {} > DDR0
+ .data_buffer : {} palign(128) > DDR0
+
+ /* USB or any other LLD buffer for benchmarking */
+ .benchmark_buffer (NOLOAD) {} ALIGN (8) > DDR0
+
+ .stack : {} align(4) > DDR0 (HIGH)
+ .irqStack : {. = . + __IRQ_STACK_SIZE;} align(4) > DDR0 (HIGH)
+ RUN_START(__IRQ_STACK_START)
+ RUN_END(__IRQ_STACK_END)
+ .fiqStack : {. = . + __FIQ_STACK_SIZE;} align(4) > DDR0 (HIGH)
+ RUN_START(__FIQ_STACK_START)
+ RUN_END(__FIQ_STACK_END)
+ .abortStack : {. = . + __ABORT_STACK_SIZE;} align(4) > DDR0 (HIGH)
+ RUN_START(__ABORT_STACK_START)
+ RUN_END(__ABORT_STACK_END)
+ .undStack : {. = . + __UND_STACK_SIZE;} align(4) > DDR0 (HIGH)
+ RUN_START(__UND_STACK_START)
+ RUN_END(__UND_STACK_END)
+ .svcStack : {. = . + __SVC_STACK_SIZE;} align(4) > DDR0 (HIGH)
+ RUN_START(__SVC_STACK_START)
+ RUN_END(__SVC_STACK_END)
+}
diff --git a/packages/ti/build/j7200/linker_r5_sysbios.lds b/packages/ti/build/j7200/linker_r5_sysbios.lds
--- /dev/null
@@ -0,0 +1,37 @@
+/* linker options */
+--fill_value=0
+--stack_size=0x2000
+--heap_size=0x1000
+
+-e __VECS_ENTRY_POINT
+
+MEMORY
+{
+ R5F_TCMA_SBL_RSVD(X): ORIGIN = 0x00000000 , LENGTH = 0x100
+ RESET_VECTORS(X) : ORIGIN = 0x41c40000 , LENGTH = 0x100 /* Bottom 256 KB used by SBL */
+ R5F_TCMB0(RWIX) : ORIGIN = 0x41010000 , LENGTH = 0x00008000
+ DDR0 (RWIX) : ORIGIN = 0x80000000 , LENGTH = 0x80000000
+}
+
+SECTIONS
+{
+ .vecs : {
+ __VECS_ENTRY_POINT = .;
+ } palign(8) > RESET_VECTORS
+ .text_boot {
+ *boot.aer5f<*boot.o*>(.text)
+ } palign(8) > R5F_TCMB0
+ .text:xdc_runtime_Startup_reset__I : {} palign(8) > R5F_TCMB0
+ .text:ti_sysbios_family_arm_v7r_Cache* : {} palign(8) > R5F_TCMB0
+ .text:ti_sysbios_family_arm_MPU* : {} palign(8) > R5F_TCMB0
+
+ .text : {} palign(8) > DDR0
+ .cinit : {} palign(8) > DDR0
+ .bss : {} align(8) > DDR0
+ .far : {} align(8) > DDR0
+ .const : {} palign(8) > DDR0
+ .data : {} palign(128) > DDR0
+ .sysmem : {} align(8) > DDR0
+ .stack : {} align(4) > DDR0
+ .data_buffer: {} palign(128) > DDR0
+}
\ No newline at end of file
diff --git a/packages/ti/build/j7200/r5_mpu.xs b/packages/ti/build/j7200/r5_mpu.xs
--- /dev/null
@@ -0,0 +1,159 @@
+/*
+ * Copyright (c) 2019, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/*
+ * ======== event_MPU.xs ========
+ * MPU Settings for J7200 device's Cortex-R5F
+ */
+
+/*
+ * -------------------------------------------------------------------------------------------------------------
+ * | Id | Base Address | Size | En | Cacheable | XN | AccPerm | Mask |
+ * |----|--------------|------|----|-------------------------------------------|----|---------------------|------|
+ * | 0 | 0x00000000 | 4GB | T | uncacheable, Shareable | F | RW at PL 1 & PL 2 | 0x0 |
+ * |----|--------------|------|----|-------------------------------------------|----|---------------------|------|
+ * | 1 | 0 (local TCM)| 32K | T | Write-Back, Write-Allocate, Non-Shareable | F | RW at PL 1 | 0x0 |
+ * |----|--------------|------|----|-------------------------------------------|----|---------------------|------|
+ * | 2 | 0x41000000 | 32K | T | Write-Back, Write-Allocate, Non-Shareable | F | RW at PL 1 | 0x0 |
+ * |----|--------------|------|----|-------------------------------------------|----|---------------------|------|
+ * | 3 | 0x41010000 | 32K | T | Write-Back, Write-Allocate, Non-Shareable | F | RW at PL 1 | 0x0 |
+ * |----|--------------|------|----|-------------------------------------------|----|---------------------|------|
+ * | 4 | 0x41C00000 | 1MB | T | Write-Back, Write-Allocate, Non-Shareable | F | RW at PL 1 | 0x0 |
+ * -------------------------------------------------------------------------------------------------------------
+ * | 5 | 0x70000000 | 8MB | T | MSMC Ram - Cachable | F | RW at PL 1 | 0x0 |
+ * -------------------------------------------------------------------------------------------------------------
+ * | 6 | 0x80000000 | 2GB | T | DDR - Strongly Ordered, Shareable | F | RW at PL 1 & PL 3 | 0x0 |
+ * -------------------------------------------------------------------------------------------------------------
+ * | 7 | 0xAA000000 | 32MB | T | DDR (VRing Buffer) - Uncacheble | F | RW at PL 1 & PL 3 | 0x0 |
+ * |-------------------------------------------------------------------------------------------------------------|
+ */
+
+/*
+ * Note: Marking a region as shareable will cause the region to behave as outer shareable with write through
+ * no write-allocate caching policy irrespective of the actual cache policy set. Therefore, only select
+ * regions that are actually shared outside the R5 CPUSS must be marked as shared.
+ */
+
+var MPU = xdc.useModule('ti.sysbios.family.arm.MPU');
+MPU.enableMPU = true;
+MPU.enableBackgroundRegion = true;
+
+var attrs = new MPU.RegionAttrs();
+MPU.initRegionAttrsMeta(attrs);
+
+/* This entry covers the whole 32 bit memory range
+ Address: 0x00000000-0xffffffff */
+attrs.enable = true;
+attrs.bufferable = false;
+attrs.cacheable = false;
+attrs.shareable = true;
+attrs.noExecute = true;
+attrs.accPerm = 1; /* RW at PL1 */
+attrs.tex = 0;
+attrs.subregionDisableMask = 0;
+MPU.setRegionMeta(0, 0x00000000, MPU.RegionSize_4G, attrs);
+
+/* This entry covers the ATCM mapped to 0 */
+attrs.enable = true;
+attrs.bufferable = true;
+attrs.cacheable = true;
+attrs.shareable = true;
+attrs.noExecute = false;
+attrs.accPerm = 1; /* RW at PL1 */
+attrs.tex = 1;
+attrs.subregionDisableMask = 0;
+MPU.setRegionMeta(1, 0x00000000, MPU.RegionSize_32K, attrs);
+
+/* This entry covers ATCM if mapped to 0x41000000 */
+attrs.enable = true;
+attrs.bufferable = true;
+attrs.cacheable = true;
+attrs.shareable = false;
+attrs.noExecute = false;
+attrs.accPerm = 1; /* RW at PL1 */
+attrs.tex = 1;
+attrs.subregionDisableMask = 0;
+MPU.setRegionMeta(2, 0x41000000, MPU.RegionSize_32K, attrs);
+
+/* This entry covers BTCM if mapped to 0x41010000 */
+attrs.enable = true;
+attrs.bufferable = true;
+attrs.cacheable = true;
+attrs.shareable = false;
+attrs.noExecute = false;
+attrs.accPerm = 1; /* RW at PL1 */
+attrs.tex = 1;
+attrs.subregionDisableMask = 0x0;
+MPU.setRegionMeta(3, 0x41010000, MPU.RegionSize_32K, attrs);
+
+/* This entry covers RAM0 */
+attrs.enable = true;
+attrs.bufferable = true;
+attrs.cacheable = true;
+attrs.shareable = false;
+attrs.noExecute = false;
+attrs.accPerm = 1; /* RW at PL1 */
+attrs.tex = 1;
+attrs.subregionDisableMask = 0;
+MPU.setRegionMeta(4, 0x41C00000, MPU.RegionSize_1M, attrs);
+
+/* This entry covers MSMC SRAM */
+attrs.enable = true;
+attrs.bufferable = true;
+attrs.cacheable = true;
+attrs.shareable = false;
+attrs.noExecute = false;
+attrs.accPerm = 1; /* RW at PL1 */
+attrs.tex = 1;
+attrs.subregionDisableMask = 0;
+MPU.setRegionMeta(5, 0x70000000, MPU.RegionSize_8M, attrs);
+
+/* This entry covers DDR memory */
+attrs.enable = true;
+attrs.bufferable = true;
+attrs.cacheable = true;
+attrs.shareable = false;
+attrs.noExecute = false;
+attrs.accPerm = 0x3; /* RW at PL1 & PL2 */
+attrs.tex = 1;
+attrs.subregionDisableMask = 0;
+MPU.setRegionMeta(6, 0x80000000, MPU.RegionSize_2G, attrs);
+
+/* Ring Buffer uncached.... */
+attrs.enable = true;
+attrs.bufferable = false;
+attrs.cacheable = false;
+attrs.shareable = true;
+attrs.noExecute = true;
+attrs.accPerm = 3; /* RW at PL1 */
+attrs.tex = 0;
+attrs.subregionDisableMask = 0;
+MPU.setRegionMeta(7, 0xAA000000, MPU.RegionSize_32M, attrs);
diff --git a/packages/ti/build/j7200/sbl_mcux_0_dummy_app.rprc b/packages/ti/build/j7200/sbl_mcux_0_dummy_app.rprc
new file mode 100644 (file)
index 0000000..bfd581f
Binary files /dev/null and b/packages/ti/build/j7200/sbl_mcux_0_dummy_app.rprc differ
index 0000000..bfd581f
Binary files /dev/null and b/packages/ti/build/j7200/sbl_mcux_0_dummy_app.rprc differ
diff --git a/packages/ti/build/j7200/sysbios_a72.cfg b/packages/ti/build/j7200/sysbios_a72.cfg
--- /dev/null
@@ -0,0 +1,173 @@
+
+/* =============================================================================
+ * Copyright (c) Texas Instruments Incorporated 2018
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+var Defaults = xdc.useModule('xdc.runtime.Defaults');
+var Diags = xdc.useModule('xdc.runtime.Diags');
+var Error = xdc.useModule('xdc.runtime.Error');
+var Log = xdc.useModule('xdc.runtime.Log');
+var LoggerBuf = xdc.useModule('xdc.runtime.LoggerBuf');
+var Main = xdc.useModule('xdc.runtime.Main');
+var Memory = xdc.useModule('xdc.runtime.Memory');
+var System = xdc.useModule('xdc.runtime.System');
+var Text = xdc.useModule('xdc.runtime.Text');
+var Clock = xdc.useModule('ti.sysbios.knl.Clock');
+var Task = xdc.useModule('ti.sysbios.knl.Task');
+var Semaphore = xdc.useModule('ti.sysbios.knl.Semaphore');
+var HeapBuf = xdc.useModule('ti.sysbios.heaps.HeapBuf');
+var GateSwi = xdc.useModule('ti.sysbios.gates.GateSwi');
+
+var BIOS = xdc.useModule('ti.sysbios.BIOS');
+var Hwi = xdc.useModule('ti.sysbios.hal.Hwi');
+var HeapMem = xdc.useModule('ti.sysbios.heaps.HeapMem');
+var SysMin = xdc.useModule('xdc.runtime.SysMin');
+
+var Cache = xdc.module("ti.sysbios.hal.Cache");
+Cache.CacheProxy = xdc.useModule("ti.sysbios.family.arm.v8a.Cache");
+
+var Mmu = xdc.useModule('ti.sysbios.family.arm.v8a.Mmu');
+Mmu.initFunc = "&InitMmu";
+Mmu.tableArrayLen = 24;
+
+/*
+ * Direct CIO to UART
+ */
+/* System.SupportProxy = SysUart; */
+System.SupportProxy = SysMin;
+
+System.extendedFormats += "%f";
+/*
+ * Program.argSize sets the size of the .args section.
+ * The examples don't use command line args so argSize is set to 0.
+ */
+Program.argSize = 0x0;
+
+
+/* System stack size (used by ISRs and Swis) */
+Program.stack = 0x4000;
+
+Task.defaultStackSize = 0x4000;
+/*
+ * Uncomment this line to globally disable Asserts.
+ * All modules inherit the default from the 'Defaults' module. You
+ * can override these defaults on a per-module basis using Module.common$.
+ * Disabling Asserts will save code space and improve runtime performance.
+Defaults.common$.diags_ASSERT = Diags.ALWAYS_OFF;
+ */
+
+/*
+ * Uncomment this line to keep module names from being loaded on the target.
+ * The module name strings are placed in the .const section. Setting this
+ * parameter to false will save space in the .const section. Error and
+ * Assert messages will contain an "unknown module" prefix instead
+ * of the actual module name.
+Defaults.common$.namedModule = false;
+ */
+
+/* Create default heap and hook it into Memory */
+var heapMemParams = new HeapMem.Params;
+heapMemParams.size = 16384*5;
+var heap0 = HeapMem.create(heapMemParams);
+
+Memory.defaultHeapInstance = heap0;
+
+/*
+ * Minimize exit handler array in System. The System module includes
+ * an array of functions that are registered with System_atexit() to be
+ * called by System_exit().
+ */
+System.maxAtexitHandlers = 4;
+
+/*
+ * Uncomment this line to disable the Error print function.
+ * We lose error information when this is disabled since the errors are
+ * not printed. Disabling the raiseHook will save some code space if
+ * your app is not using System_printf() since the Error_print() function
+ * calls System_printf().
+Error.raiseHook = null;
+ */
+
+/*
+ * Uncomment this line to keep Error, Assert, and Log strings from being
+ * loaded on the target. These strings are placed in the .const section.
+ * Setting this parameter to false will save space in the .const section.
+ * Error, Assert and Log message will print raw ids and args instead of
+ * a formatted message.
+Text.isLoaded = false;
+ */
+
+/*
+ * Uncomment this line to disable the output of characters by SysMin
+ * when the program exits. SysMin writes characters to a circular buffer.
+ * This buffer can be viewed using the SysMin Output view in ROV.
+SysMin.flushAtExit = false;
+ */
+
+/*
+ * Create and install logger for the whole system
+ */
+var loggerBufParams = new LoggerBuf.Params();
+loggerBufParams.numEntries = 32;
+var logger0 = LoggerBuf.create(loggerBufParams);
+Defaults.common$.logger = logger0;
+Main.common$.diags_INFO = Diags.ALWAYS_ON;
+
+BIOS.libType = BIOS.LibType_Custom;
+BIOS.cpuFreq.lo = 2000000000;
+BIOS.cpuFreq.hi = 0;
+
+var Timer = xdc.useModule('ti.sysbios.family.arm.v8a.Timer');
+Timer.intFreq.lo = 250000000;
+Timer.intFreq.hi = 0;
+
+var DMTimer = xdc.useModule('ti.sysbios.timers.dmtimer.Timer');
+DMTimer.checkFrequency = false;
+for (var i=0; i < DMTimer.numTimerDevices; i++) {
+ DMTimer.intFreqs[i].lo = 19200000;
+ DMTimer.intFreqs[i].hi = 0;
+}
+
+var Load = xdc.useModule('ti.sysbios.utils.Load');
+
+/* load calculation related settings */
+Load.swiEnabled = true;
+Load.hwiEnabled = true;
+Load.taskEnabled = true;
+Load.updateInIdle = false;
+
+/* Check if application needs to update with custom configuration options */
+/* Caution: This should be at the end of this file after all other common cfg */
+var cfgUpdate = java.lang.System.getenv("XDC_CFG_UPDATE");
+if ((cfgUpdate != '')&&(cfgUpdate != null))
+{
+ xdc.print("Loading configuration update " + cfgUpdate);
+ xdc.loadCapsule(cfgUpdate);
+}
diff --git a/packages/ti/build/j7200/sysbios_c7x.cfg b/packages/ti/build/j7200/sysbios_c7x.cfg
--- /dev/null
@@ -0,0 +1,113 @@
+/*
+ * Copyright (c) Texas Instruments Incorporated 2018
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+var Defaults = xdc.useModule('xdc.runtime.Defaults');
+var Diags = xdc.useModule('xdc.runtime.Diags');
+var Error = xdc.useModule('xdc.runtime.Error');
+var Log = xdc.useModule('xdc.runtime.Log');
+var LoggerBuf = xdc.useModule('xdc.runtime.LoggerBuf');
+var Main = xdc.useModule('xdc.runtime.Main');
+var Memory = xdc.useModule('xdc.runtime.Memory');
+var System = xdc.useModule('xdc.runtime.System');
+var Text = xdc.useModule('xdc.runtime.Text');
+var Clock = xdc.useModule('ti.sysbios.knl.Clock');
+var Task = xdc.useModule('ti.sysbios.knl.Task');
+var Semaphore = xdc.useModule('ti.sysbios.knl.Semaphore');
+var BIOS = xdc.useModule('ti.sysbios.BIOS');
+var Hwi = xdc.useModule('ti.sysbios.hal.Hwi');
+var HeapMem = xdc.useModule('ti.sysbios.heaps.HeapMem');
+var SysMin = xdc.useModule('xdc.runtime.SysMin');
+var HeapBuf = xdc.useModule('ti.sysbios.heaps.HeapBuf');
+var GateSwi = xdc.useModule('ti.sysbios.gates.GateSwi');
+
+/* Enable cache */
+var Cache = xdc.useModule('ti.sysbios.hal.Cache');
+
+System.SupportProxy = SysMin;
+
+/*
+ * Program.argSize sets the size of the .args section.
+ * The examples don't use command line args so argSize is set to 0.
+ */
+Program.argSize = 0x0;
+
+/* Minimum required to be 16K aligned to avoid BIOS build warning */
+Program.stack = 0x4000;
+
+/*
+ * Minimize exit handler array in System. The System module includes
+ * an array of functions that are registered with System_atexit() to be
+ * called by System_exit().
+ */
+System.maxAtexitHandlers = 4;
+
+/* Create and install logger for the whole system */
+var loggerBufParams = new LoggerBuf.Params();
+loggerBufParams.numEntries = 32;
+var logger0 = LoggerBuf.create(loggerBufParams);
+Defaults.common$.logger = logger0;
+Main.common$.diags_INFO = Diags.ALWAYS_ON;
+
+BIOS.libType = BIOS.LibType_Custom;
+BIOS.cpuFreq.lo = 1000000000;
+BIOS.cpuFreq.hi = 0;
+
+var DMTimer = xdc.useModule('ti.sysbios.timers.dmtimer.Timer');
+DMTimer.checkFrequency = false;
+for (var i=0; i < DMTimer.numTimerDevices; i++) {
+ DMTimer.intFreqs[i].lo = 19200000;
+ DMTimer.intFreqs[i].hi = 0;
+}
+
+var Mmu = xdc.useModule('ti.sysbios.family.c7x.Mmu');
+Mmu.initFunc = "&InitMmu";
+Mmu.tableMemory = "";
+
+var Hwi = xdc.useModule('ti.sysbios.hal.Hwi');
+Hwi.initStackFlag = false;
+
+Memory.defaultHeapSize = 256*1024;
+
+/* Check if application needs to update with custom configuration options */
+var cfgUpdate = java.lang.System.getenv("XDC_CFG_UPDATE")
+if(cfgUpdate != '')
+{
+ xdc.print("Loading configuration update " + cfgUpdate);
+ xdc.loadCapsule(cfgUpdate);
+}
+
+var Load = xdc.useModule('ti.sysbios.utils.Load');
+
+/* load calculation related settings */
+Load.swiEnabled = true;
+Load.hwiEnabled = true;
+Load.taskEnabled = true;
+Load.updateInIdle = false;
diff --git a/packages/ti/build/j7200/sysbios_r5f.cfg b/packages/ti/build/j7200/sysbios_r5f.cfg
--- /dev/null
@@ -0,0 +1,234 @@
+
+/* =============================================================================
+ * Copyright (c) Texas Instruments Incorporated 2018
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+var Defaults = xdc.useModule('xdc.runtime.Defaults');
+var Diags = xdc.useModule('xdc.runtime.Diags');
+var Error = xdc.useModule('xdc.runtime.Error');
+var Log = xdc.useModule('xdc.runtime.Log');
+var LoggerBuf = xdc.useModule('xdc.runtime.LoggerBuf');
+var Main = xdc.useModule('xdc.runtime.Main');
+var Memory = xdc.useModule('xdc.runtime.Memory')
+var System = xdc.useModule('xdc.runtime.System');
+var Text = xdc.useModule('xdc.runtime.Text');
+var Clock = xdc.useModule('ti.sysbios.knl.Clock');
+var Task = xdc.useModule('ti.sysbios.knl.Task');
+var Semaphore = xdc.useModule('ti.sysbios.knl.Semaphore');
+var HeapBuf = xdc.useModule('ti.sysbios.heaps.HeapBuf');
+var GateSwi = xdc.useModule('ti.sysbios.gates.GateSwi');
+
+var BIOS = xdc.useModule('ti.sysbios.BIOS');
+var Hwi = xdc.useModule('ti.sysbios.family.arm.v7r.keystone3.Hwi');
+var Core = xdc.useModule('ti.sysbios.family.arm.v7r.keystone3.Core');
+var HeapMem = xdc.useModule('ti.sysbios.heaps.HeapMem');
+var SysMin = xdc.useModule('xdc.runtime.SysMin');
+
+/* System stack size (used by ISRs and Swis) */
+Program.stack = 0x2000;
+
+/* Place vector table in separate section - by default this goes to 0x0 which
+ * is reserved by SBL */
+Program.sectMap[".vecs"] = "RESET_VECTORS";
+
+var Task = xdc.useModule('ti.sysbios.knl.Task');
+Task.defaultStackSize = 0x4000;
+Task.common$.namedInstance = true;
+Task.common$.namedModule = true;
+
+/* Enable cache */
+var Cache = xdc.useModule('ti.sysbios.family.arm.v7r.Cache');
+Cache.enableCache = true;
+
+/*
+ * Direct CIO to UART
+ */
+/* System.SupportProxy = SysUart; */
+System.SupportProxy = SysMin;
+System.extendedFormats += "%f";
+/*
+ * Program.argSize sets the size of the .args section.
+ * The examples don't use command line args so argSize is set to 0.
+ */
+Program.argSize = 0x0;
+
+/*
+ * Uncomment this line to globally disable Asserts.
+ * All modules inherit the default from the 'Defaults' module. You
+ * can override these defaults on a per-module basis using Module.common$.
+ * Disabling Asserts will save code space and improve runtime performance.
+Defaults.common$.diags_ASSERT = Diags.ALWAYS_OFF;
+ */
+
+/*
+ * Uncomment this line to keep module names from being loaded on the target.
+ * The module name strings are placed in the .const section. Setting this
+ * parameter to false will save space in the .const section. Error and
+ * Assert messages will contain an "unknown module" prefix instead
+ * of the actual module name.
+Defaults.common$.namedModule = false;
+ */
+
+/* Create default heap and hook it into Memory */
+var heapMemParams = new HeapMem.Params;
+heapMemParams.size = 16384*4;
+var heap0 = HeapMem.create(heapMemParams);
+
+Memory.defaultHeapInstance = heap0;
+
+/*
+ * Minimize exit handler array in System. The System module includes
+ * an array of functions that are registered with System_atexit() to be
+ * called by System_exit().
+ */
+System.maxAtexitHandlers = 4;
+
+/*
+ * Uncomment this line to disable the Error print function.
+ * We lose error information when this is disabled since the errors are
+ * not printed. Disabling the raiseHook will save some code space if
+ * your app is not using System_printf() since the Error_print() function
+ * calls System_printf().
+Error.raiseHook = null;
+ */
+
+/*
+ * Uncomment this line to keep Error, Assert, and Log strings from being
+ * loaded on the target. These strings are placed in the .const section.
+ * Setting this parameter to false will save space in the .const section.
+ * Error, Assert and Log message will print raw ids and args instead of
+ * a formatted message.
+Text.isLoaded = false;
+ */
+
+/*
+ * Uncomment this line to disable the output of characters by SysMin
+ * when the program exits. SysMin writes characters to a circular buffer.
+ * This buffer can be viewed using the SysMin Output view in ROV.
+SysMin.flushAtExit = false;
+ */
+
+/*
+ * Create and install logger for the whole system
+ */
+var loggerBufParams = new LoggerBuf.Params();
+loggerBufParams.numEntries = 32;
+var logger0 = LoggerBuf.create(loggerBufParams);
+Defaults.common$.logger = logger0;
+Main.common$.diags_INFO = Diags.ALWAYS_ON;
+
+BIOS.libType = BIOS.LibType_Custom;
+BIOS.cpuFreq.lo = 1000000000;
+BIOS.cpuFreq.hi = 0;
+
+var coreId = java.lang.System.getenv("CORE");
+
+var DMTimer = xdc.useModule('ti.sysbios.timers.dmtimer.Timer');
+DMTimer.checkFrequency = false;
+for (var i=0; i < DMTimer.numTimerDevices; i++) {
+ DMTimer.intFreqs[i].lo = 19200000;
+ DMTimer.intFreqs[i].hi = 0;
+}
+
+if(coreId=="mcu1_0")
+{
+ Core.id = 0;
+ /* DM timer cfg */
+ Clock.timerId = 1;
+}
+if(coreId=="mcu1_1")
+{
+ Core.id = 1;
+ /* DM timer cfg */
+ Clock.timerId = 2;
+}
+if(coreId=="mcu2_0")
+{
+ Core.id = 0;
+ Clock.timerId = 0;
+ /* DMTimer #12 - in general, address is 0x024x0000 where x is timer # */
+ DMTimer.timerSettings[0].baseAddr = 0x024c0000;
+ DMTimer.timerSettings[0].intNum = 168;
+}
+if(coreId=="mcu2_1")
+{
+ Core.id = 1;
+ Clock.timerId = 1;
+ /* DMTimer #13 - in general, address is 0x024x0000 where x is timer # */
+ DMTimer.timerSettings[1].baseAddr = 0x024d0000;
+ DMTimer.timerSettings[1].intNum = 169;
+}
+if(coreId=="mcu3_0")
+{
+ Core.id = 0;
+ Clock.timerId = 2;
+ /* DMTimer #14 - in general, address is 0x024x0000 where x is timer # */
+ DMTimer.timerSettings[2].baseAddr = 0x024e0000;
+ DMTimer.timerSettings[2].intNum = 170;
+}
+if(coreId=="mcu3_1")
+{
+ Core.id = 1;
+ Clock.timerId = 3;
+ /* DMTimer #15 - in general, address is 0x024x0000 where x is timer # */
+ DMTimer.timerSettings[3].baseAddr = 0x024f0000;
+ DMTimer.timerSettings[3].intNum = 171;
+}
+
+/* Set base address of Vector Interrupt Manager */
+if((coreId=="mcu2_0") || (coreId=="mcu2_1") || (coreId=="mcu3_0") || (coreId=="mcu3_1"))
+{
+ var Hwi = xdc.useModule('ti.sysbios.family.arm.v7r.keystone3.Hwi');
+ Hwi.vimBaseAddress = 0x0ff80000;
+}
+
+/*
+ * Initialize MPU and enable it
+ *
+ * Note: MPU must be enabled and properly configured for caching to work.
+ */
+xdc.loadCapsule("r5_mpu.xs");
+
+var Load = xdc.useModule('ti.sysbios.utils.Load');
+
+/* load calculation related settings */
+Load.swiEnabled = true;
+Load.hwiEnabled = true;
+Load.taskEnabled = true;
+Load.updateInIdle = false;
+
+/* Check if application needs to update with custom configuration options */
+/* Caution: This should be at the end of this file after all other common cfg */
+var cfgUpdate = java.lang.System.getenv("XDC_CFG_UPDATE")
+if ((cfgUpdate != '')&&(cfgUpdate != null))
+{
+ xdc.print("Loading configuration update " + cfgUpdate);
+ xdc.loadCapsule(cfgUpdate);
+}
diff --git a/packages/ti/build/j721e/config_j721e_a72.bld b/packages/ti/build/j721e/config_j721e_a72.bld
--- /dev/null
@@ -0,0 +1,42 @@
+/*
+* Copyright (c) 2018, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* * Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* * Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the distribution.
+*
+* * Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+/*
+ * ======== config_j721e_a72.bld ========
+ * Common build configuration script for BIOS
+ */
+
+var gccArmTargets = xdc.loadPackage('gnu.targets.arm');
+gccArmTargets.A53F.rootDir = java.lang.System.getenv("CGTOOLS_A72");
+gccArmTargets.A53F.bspLib = "rdimon";
+
+Build.targets = [ gccArmTargets.A53F ];
diff --git a/packages/ti/build/j721e/config_j721e_c66.bld b/packages/ti/build/j721e/config_j721e_c66.bld
--- /dev/null
@@ -0,0 +1,40 @@
+/*
+* Copyright (c) 2018, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* * Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* * Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the distribution.
+*
+* * Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+/*
+ * ======== config_j721e_c66.bld ========
+ * Build configuration script for BSP drivers
+ */
+/* load the required modules for the configuration */
+var C66 = xdc.useModule('ti.targets.elf.C66');
+/* C66 compiler directory path */
+C66.rootDir = java.lang.System.getenv("C6X_GEN_INSTALL_PATH");
diff --git a/packages/ti/build/j721e/config_j721e_c7x.bld b/packages/ti/build/j721e/config_j721e_c7x.bld
--- /dev/null
@@ -0,0 +1,40 @@
+/*
+* Copyright (c) 2018, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* * Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* * Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the distribution.
+*
+* * Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+/*
+ * ======== config_j721e_c7x.bld ========
+ * Build configuration script for BSP drivers
+ */
+/* load the required modules for the configuration */
+var C7x = xdc.useModule('ti.targets.elf.C71');
+/* C7x compiler directory path */
+C7x.rootDir = java.lang.System.getenv("C7X_GEN_INSTALL_PATH");
diff --git a/packages/ti/build/j721e/config_j721e_r5f.bld b/packages/ti/build/j721e/config_j721e_r5f.bld
--- /dev/null
@@ -0,0 +1,40 @@
+/*
+* Copyright (c) 2017, Texas Instruments Incorporated
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* * Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* * Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the distribution.
+*
+* * Neither the name of Texas Instruments Incorporated nor the names of
+* its contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+/*
+ * ======== config_j721e_r5.bld ========
+ * Build configuration script for BSP drivers
+ */
+/* load the required modules for the configuration */
+var R5F = xdc.useModule('ti.targets.arm.elf.R5F');
+/* R5F compiler directory path */
+R5F.rootDir = java.lang.System.getenv("CGTOOLS");
diff --git a/packages/ti/build/j721e/linker_a72_mpu1_0.lds b/packages/ti/build/j721e/linker_a72_mpu1_0.lds
--- /dev/null
@@ -0,0 +1,197 @@
+__STACK_SIZE = 0x20000;
+__TI_STACK_SIZE = __STACK_SIZE;
+
+MEMORY
+{
+ OCMCRAM : ORIGIN = 0x000041C00000, LENGTH = 0x00080000 /* MCUSS-OCMC RAM - 512KB */
+
+
+ DDR_MPU1 (RWX) : ORIGIN = 0x80000000, LENGTH = 0x08000000
+ DDR_IPC (RWX) : ORIGIN = 0x90000000, LENGTH = 0x02000000
+
+ /* j721e MCMS3 locations */
+ /* j721e Reserved Memory for ARM Trusted Firmware */
+ MSMC3_ARM_FW (RWIX) : ORIGIN = 0x000070000000, LENGTH = 0x40000 /* 256KB */
+ BOOTVECTOR : ORIGIN = 0x000070040000, LENGTH = 0x1000 /* 4KB */
+ BOOTVECTOR_EL3 : ORIGIN = 0x000070041000, LENGTH = 0x1000 /* 4KB */
+ MSMC_MPU1 (RWX) : ORIGIN = 0x000070042000, LENGTH = 0x7AE000 /* 7864KB */
+ /* j721e Reserved Memory for DMSC Firmware */
+ MSMC3_DMSC_FW (RWIX) : ORIGIN = 0x0000707F0000, LENGTH = 0x10000 /* 64KB */
+}
+REGION_ALIAS("REGION_TEXT_EL3", DDR_MPU1);
+REGION_ALIAS("REGION_TEXT", DDR_MPU1);
+REGION_ALIAS("REGION_BSS", DDR_MPU1);
+REGION_ALIAS("REGION_DATA", DDR_MPU1);
+REGION_ALIAS("REGION_STACK", DDR_MPU1);
+REGION_ALIAS("REGION_HEAP", DDR_MPU1);
+REGION_ALIAS("REGION_ARM_EXIDX", DDR_MPU1);
+REGION_ALIAS("REGION_ARM_EXTAB", DDR_MPU1);
+REGION_ALIAS("REGION_TEXT_STARTUP", DDR_MPU1);
+REGION_ALIAS("REGION_DATA_BUFFER", DDR_MPU1);
+REGION_ALIAS("IPC_DATA_BUFFER_1", DDR_MPU1);
+
+SECTIONS {
+
+ .vecs : {
+ *(.vecs)
+ } > BOOTVECTOR AT> BOOTVECTOR
+
+ .vectors : {
+ *(.vectors)
+ } > BOOTVECTOR_EL3 AT> BOOTVECTOR_EL3
+ .text.el3 : {
+ *(.text.el3)
+ /* Ensure 8-byte alignment for descriptors and ensure inclusion */
+ . = ALIGN(8);
+ __RT_SVC_DESCS_START__ = .;
+ KEEP(*(rt_svc_descs))
+ __RT_SVC_DESCS_END__ = .;
+ } > REGION_TEXT_EL3 AT> REGION_TEXT_EL3
+
+ .text.csl_a72_startup : {
+ *(.text.csl_a72_startup)
+ *(.Entry)
+ } > REGION_TEXT_STARTUP AT> REGION_TEXT_STARTUP
+
+ .text : {
+ CREATE_OBJECT_SYMBOLS
+ *(.text)
+ *(.text.*)
+ . = ALIGN(0x8);
+ KEEP (*(.ctors))
+ . = ALIGN(0x4);
+ KEEP (*(.dtors))
+ . = ALIGN(0x8);
+ __init_array_start = .;
+ KEEP (*(.init_array*))
+ __init_array_end = .;
+ *(.init)
+ *(.fini*)
+ } > REGION_TEXT AT> REGION_TEXT
+
+ PROVIDE (__etext = .);
+ PROVIDE (_etext = .);
+ PROVIDE (etext = .);
+
+ .rodata : {
+ *(.rodata)
+ *(.rodata*)
+ } > REGION_TEXT AT> REGION_TEXT
+
+ .data_buffer : ALIGN (8) {
+ __data_buffer_load__ = LOADADDR (.data_buffer);
+ __data_buffer_start__ = .;
+ *(.data_buffer)
+ *(.data_buffer*)
+ . = ALIGN (8);
+ __data_buffer_end__ = .;
+ } > REGION_DATA_BUFFER AT> REGION_DATA_BUFFER
+
+ .data : ALIGN (8) {
+ __data_load__ = LOADADDR (.data);
+ __data_start__ = .;
+ *(.data)
+ *(.data*)
+ . = ALIGN (8);
+ __data_end__ = .;
+ } > REGION_DATA AT> REGION_TEXT
+
+ .ARM.exidx : {
+ __exidx_start = .;
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ __exidx_end = .;
+ } > REGION_ARM_EXIDX AT> REGION_ARM_EXIDX
+
+ .ARM.extab : {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > REGION_ARM_EXTAB AT> REGION_ARM_EXTAB
+
+ .bss:extMemCache:ramdisk : {
+ } > DDR_MPU1 /* MSMC_MPU1 */
+
+ /* USB or any other LLD buffer for benchmarking */
+ .benchmark_buffer (NOLOAD) : ALIGN (32) {
+ } > DDR_MPU1
+
+ .bss:frameBuffer (NOLOAD) : ALIGN (32) {
+ } > DDR_MPU1
+
+ ipc_data_buffer (NOLOAD) : ALIGN (32) {
+ } > IPC_DATA_BUFFER_1
+
+ /* For NDK packet memory, we need to map this sections before .bss*/
+ .bss:NDK_PACKETMEM (NOLOAD) : ALIGN (128) {} > DDR_MPU1
+ .bss:NDK_MMBUFFER (NOLOAD) : ALIGN (128) {} > DDR_MPU1
+
+ .bss : {
+ __bss_start__ = .;
+ *(.shbss)
+ *(.bss)
+ *(.bss.*)
+ . = ALIGN (8);
+ __bss_end__ = .;
+ . = ALIGN (8);
+ *(COMMON)
+ } > REGION_BSS AT> REGION_BSS
+
+ .heap : {
+ __heap_start__ = .;
+ end = __heap_start__;
+ _end = end;
+ __end = end;
+ KEEP(*(.heap))
+ __heap_end__ = .;
+ __HeapLimit = __heap_end__;
+ } > REGION_HEAP AT> REGION_HEAP
+
+ .stack (NOLOAD) : ALIGN(16) {
+ _stack = .;
+ __stack = .;
+ KEEP(*(.stack))
+ } > REGION_STACK AT> REGION_STACK
+
+ __TI_STACK_BASE = __stack;
+
+ /* Stabs debugging sections. */
+ .stab 0 : { *(.stab) }
+ .stabstr 0 : { *(.stabstr) }
+ .stab.excl 0 : { *(.stab.excl) }
+ .stab.exclstr 0 : { *(.stab.exclstr) }
+ .stab.index 0 : { *(.stab.index) }
+ .stab.indexstr 0 : { *(.stab.indexstr) }
+ .comment 0 : { *(.comment) }
+ /*
+ * DWARF debug sections.
+ * Symbols in the DWARF debugging sections are relative to the beginning
+ * of the section so we begin them at 0.
+ */
+ /* DWARF 1 */
+ .debug 0 : { *(.debug) }
+ .line 0 : { *(.line) }
+ /* GNU DWARF 1 extensions */
+ .debug_srcinfo 0 : { *(.debug_srcinfo) }
+ .debug_sfnames 0 : { *(.debug_sfnames) }
+ /* DWARF 1.1 and DWARF 2 */
+ .debug_aranges 0 : { *(.debug_aranges) }
+ .debug_pubnames 0 : { *(.debug_pubnames) }
+ /* DWARF 2 */
+ .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
+ .debug_abbrev 0 : { *(.debug_abbrev) }
+ .debug_line 0 : { *(.debug_line .debug_line.* .debug_line_end ) }
+ .debug_frame 0 : { *(.debug_frame) }
+ .debug_str 0 : { *(.debug_str) }
+ .debug_loc 0 : { *(.debug_loc) }
+ .debug_macinfo 0 : { *(.debug_macinfo) }
+ /* SGI/MIPS DWARF 2 extensions */
+ .debug_weaknames 0 : { *(.debug_weaknames) }
+ .debug_funcnames 0 : { *(.debug_funcnames) }
+ .debug_typenames 0 : { *(.debug_typenames) }
+ .debug_varnames 0 : { *(.debug_varnames) }
+ /* DWARF 3 */
+ .debug_pubtypes 0 : { *(.debug_pubtypes) }
+ .debug_ranges 0 : { *(.debug_ranges) }
+ /* DWARF Extension. */
+ .debug_macro 0 : { *(.debug_macro) }
+ .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }
+ /DISCARD/ : { *(.note.GNU-stack) *(.gnu_debuglink) *(.gnu.lto_*) }
+}
diff --git a/packages/ti/build/j721e/linker_c66.cmd b/packages/ti/build/j721e/linker_c66.cmd
--- /dev/null
@@ -0,0 +1,97 @@
+/*
+ * Copyright (c) 2018, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* This file is a copied and modified version of the J7ES.cmd provided from
+ * bios_6_73_00_12/packages/ti/sysbios/platforms/c6x/include/
+ *
+ * Default linker command file places all sections into L2SRAM which causes
+ * linker failures in the event of an entire program being larger than 288KB.
+ *
+ * Eventually this file should be deleted when J7ES platform is fully supported
+ * by the BIOS package.
+ */
+
+MEMORY
+{
+ L2SRAM: o = 0x00800000 l = 0x00048000 /* 288KB LOCAL L2/SRAM */
+ L1PSRAM: o = 0x00E00000 l = 0x00008000 /* 32KB LOCAL L1P/SRAM */
+ L1DSRAM: o = 0x00F00000 l = 0x00008000 /* 32KB LOCAL L1D/SRAM */
+ DDR0: o = 0x80000000 l = 0x20000000 /* 512MB DDR0 NAVSS */
+ /* j721e MSMC3 Memory */
+ /* j721e Reserved Memory for ARM Trusted Firmware */
+ MSMC3_ARM_FW (RWIX) : o = 0x70000000, l = 0x40000 /* 256KB */
+ MSMC3 (RWIX) : o = 0x70040000 l = 0x7B0000 /* 8MB - 320KB */
+ /* j721e Reserved Memory for DMSC Firmware */
+ MSMC3_DMSC_FW (RWIX) : o = 0x707F0000, l = 0x10000 /* 64KB */
+}
+
+-stack 0x2000 /* SOFTWARE STACK SIZE */
+-heap 0x2000 /* HEAP AREA SIZE */
+
+/* Set L1D, L1P and L2 Cache Sizes */
+ti_sysbios_family_c66_Cache_l1dSize = 32768;
+ti_sysbios_family_c66_Cache_l1pSize = 32768;
+ti_sysbios_family_c66_Cache_l2Size = 32768;
+
+SECTIONS
+{
+ .vecs: load > DDR0 ALIGN(0x10000)
+ .text:_c_int00 load > DDR0 ALIGN(0x10000)
+ .text: load > DDR0
+ .stack: load > DDR0
+ GROUP: load > DDR0
+ {
+ .bss:
+ .neardata:
+ .rodata:
+ }
+ .cio: load > DDR0
+ .const: load > DDR0
+ .data: load > DDR0
+ .switch: load > DDR0
+ .sysmem: load > DDR0
+ .far: load > DDR0
+ .args: load > DDR0
+
+ /* COFF sections */
+ .pinit: load > DDR0
+ .cinit: load > DDR0
+
+ /* EABI sections */
+ .binit: load > DDR0
+ .init_array: load > DDR0
+ .fardata: load > DDR0
+ .c6xabi.exidx: load > DDR0
+ .c6xabi.extab: load > DDR0
+
+ .csl_vect: load > L2SRAM
+}
diff --git a/packages/ti/build/j721e/linker_c7x.lds b/packages/ti/build/j721e/linker_c7x.lds
--- /dev/null
@@ -0,0 +1,121 @@
+/*
+ *
+ * Copyright (c) 2018 Texas Instruments Incorporated
+ *
+ * All rights reserved not granted herein.
+ *
+ * Limited License.
+ *
+ * Texas Instruments Incorporated grants a world-wide, royalty-free, non-exclusive
+ * license under copyrights and patents it now or hereafter owns or controls to make,
+ * have made, use, import, offer to sell and sell ("Utilize") this software subject to the
+ * terms herein. With respect to the foregoing patent license, such license is granted
+ * solely to the extent that any such patent is necessary to Utilize the software alone.
+ * The patent license shall not apply to any combinations which include this software,
+ * other than combinations with devices manufactured by or for TI ("TI Devices").
+ * No hardware patent is licensed hereunder.
+ *
+ * Redistributions must preserve existing copyright notices and reproduce this license
+ * (including the above copyright notice and the disclaimer and (if applicable) source
+ * code license limitations below) in the documentation and/or other materials provided
+ * with the distribution
+ *
+ * Redistribution and use in binary form, without modification, are permitted provided
+ * that the following conditions are met:
+ *
+ * * No reverse engineering, decompilation, or disassembly of this software is
+ * permitted with respect to any software provided in binary form.
+ *
+ * * any redistribution and use are licensed by TI for use only with TI Devices.
+ *
+ * * Nothing shall obligate TI to provide you with source code for the software
+ * licensed and provided to you in object code.
+ *
+ * If software source code is provided to you, modification and redistribution of the
+ * source code are permitted provided that the following conditions are met:
+ *
+ * * any redistribution and use of the source code, including any resulting derivative
+ * works, are licensed by TI for use only with TI Devices.
+ *
+ * * any redistribution and use of any object code compiled from the source code
+ * and any resulting derivative works, are licensed by TI for use only with TI Devices.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of its suppliers
+ *
+ * may be used to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * DISCLAIMER.
+ *
+ * THIS SOFTWARE IS PROVIDED BY TI AND TI'S LICENSORS "AS IS" AND ANY EXPRESS
+ * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL TI AND TI'S LICENSORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+ * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+-c
+-heap 0x20000
+-stack 0x20000
+--args 0x1000
+--diag_suppress=10068 /* "no matching section" */
+--cinit_compression=off
+--retain="*(xdc.meta)"
+
+#define DDR0_ALLOCATED_START 0xA0000000
+#define C7X_ALLOCATED_START DDR0_ALLOCATED_START + 0x08000000
+
+#define C7X_EXT_DATA_BASE (C7X_ALLOCATED_START + 0x00100000)
+#define C7X_MEM_TEXT_BASE (C7X_ALLOCATED_START + 0x00200000)
+#define C7X_MEM_DATA_BASE (C7X_ALLOCATED_START + 0x00300000)
+#define C7X_DDR_SPACE_BASE (C7X_ALLOCATED_START + 0x00400000)
+
+MEMORY
+{
+ L2SRAM (RWX): org = 0x64800000, len = 0x00070000
+ DDR0_RESERVED: org = 0x80000000, len = 0x20000000 /* 512MB Reserved for A72 OS */
+ C7X_IPC_D: org = C7X_ALLOCATED_START, len = 0x00100000 /* 1MB DDR */
+ C7X_EXT_D: org = C7X_EXT_DATA_BASE, len = 0x00100000 /* 1MB DDR */
+ C7X_TEXT: org = C7X_MEM_TEXT_BASE, len = 0x00100000 /* 1MB DDR */
+ C7X_DATA: org = C7X_MEM_DATA_BASE, len = 0x00100000 /* 1MB DDR */
+ C7X_DDR_SPACE: org = C7X_DDR_SPACE_BASE, len = 0x00C00000 /* 12MB DDR */
+}
+
+SECTIONS
+{
+ xdc.meta (COPY): { } > C7X_DDR_SPACE
+ boot:
+ {
+ boot.*<boot.oe71>(.text)
+ } load > C7X_TEXT ALIGN(0x200000)
+ .vecs > C7X_DDR_SPACE ALIGN(0x400000)
+ .text > C7X_DDR_SPACE ALIGN(0x200000)
+
+ .bss > C7X_DDR_SPACE /* Zero-initialized data */
+ .data > C7X_DDR_SPACE /* Initialized data */
+
+ .cinit > C7X_DDR_SPACE /* could be part of const */
+ .init_array > C7X_DDR_SPACE /* C++ initializations */
+ .stack > C7X_DDR_SPACE ALIGN(0x2000)
+ .args > C7X_DDR_SPACE
+ .cio > C7X_DDR_SPACE
+ .const > C7X_DDR_SPACE
+ .switch > C7X_DDR_SPACE /* For exception handling. */
+ .sysmem > C7X_DDR_SPACE /* heap */
+
+ GROUP: > C7X_DDR_SPACE
+ {
+ .data.ti_sysbios_family_c7x_Mmu_tableArray : type=NOINIT
+ .data.ti_sysbios_family_c7x_Mmu_tableArraySlot : type=NOINIT
+ .data.ti_sysbios_family_c7x_Mmu_level1Table : type=NOINIT
+ }
+
+ ipc_data_buffer: > C7X_DDR_SPACE
+ .resource_table: { __RESOURCE_TABLE = .;} > C7X_EXT_D
+}
diff --git a/packages/ti/build/j721e/linker_r5.lds b/packages/ti/build/j721e/linker_r5.lds
--- /dev/null
@@ -0,0 +1,97 @@
+/* Linker Settings */
+--retain="*(.bootCode)"
+--retain="*(.startupCode)"
+--retain="*(.startupData)"
+--retain="*(.intvecs)"
+--retain="*(.intc_text)"
+--retain="*(.rstvectors)"
+--retain="*(.irqStack)"
+--retain="*(.fiqStack)"
+--retain="*(.abortStack)"
+--retain="*(.undStack)"
+--retain="*(.svcStack)"
+--fill_value=0
+--stack_size=0x2000
+--heap_size=0x1000
+--entry_point=_resetvectors /* Default C RTS boot.asm */
+
+-stack 0x2000 /* SOFTWARE STACK SIZE */
+-heap 0x2000 /* HEAP AREA SIZE */
+
+/* Stack Sizes for various modes */
+__IRQ_STACK_SIZE = 0x1000;
+__FIQ_STACK_SIZE = 0x1000;
+__ABORT_STACK_SIZE = 0x1000;
+__UND_STACK_SIZE = 0x1000;
+__SVC_STACK_SIZE = 0x1000;
+
+/* Memory Map */
+MEMORY
+{
+ VECTORS (X) : origin=0x41C7F000 length=0x1000
+ /* Reset Vectors base address(RESET_VECTORS) should be 64 bytes aligned */
+ RESET_VECTORS (X) : origin=0x41C00000 length=0x100
+ /* MCU0_R5F_0 local view */
+ MCU0_R5F_TCMA_SBL_RSVD (X) : origin=0x0 length=0x100
+ MCU0_R5F_TCMA (X) : origin=0x100 length=0x8000 - 0x100
+ MCU0_R5F_TCMB0 (RWIX) : origin=0x41010000 length=0x8000
+
+ /* MCU0_R5F_1 SoC view */
+ MCU0_R5F1_ATCM (RWIX) : origin=0x41400000 length=0x8000
+ MCU0_R5F1_BTCM (RWIX) : origin=0x41410000 length=0x8000
+
+ /* MCU0 share locations */
+ OCMRAM (RWIX) : origin=0x41C00100 length=0x80000 - 0x1100 /* ~510KB */
+
+ /* j721e MCMS3 locations */
+ /* j721e Reserved Memory for ARM Trusted Firmware */
+ MSMC3_ARM_FW (RWIX) : origin=0x70000000 length=0x40000 /* 256KB */
+ MSMC3 (RWIX) : origin=0x70040000 length=0x7B0000 /* 8MB - 320KB */
+ /* j721e Reserved Memory for DMSC Firmware */
+ MSMC3_DMSC_FW (RWIX) : origin=0x707F0000 length=0x10000 /* 64KB */
+
+ DDR0 (RWIX) : origin=0x80000000 length=0x80000000 /* 2GB */
+}
+
+/* Section Configuration */
+SECTIONS
+{
+ /* 'intvecs' and 'intc_text' sections shall be placed within */
+ /* a range of +\- 16 MB */
+ .intvecs : {} palign(8) > VECTORS
+ .intc_text : {} palign(8) > VECTORS
+ .rstvectors : {} palign(8) > RESET_VECTORS
+ .bootCode : {} palign(8) > MSMC3
+ .startupCode : {} palign(8) > MSMC3
+ .startupData : {} palign(8) > MSMC3, type = NOINIT
+ .text : {} palign(8) > DDR0
+ .const : {} palign(8) > DDR0
+ .cinit : {} palign(8) > DDR0
+ .pinit : {} palign(8) > DDR0
+ .bss : {} align(4) > DDR0
+ .far : {} align(4) > DDR0
+ .data : {} palign(128) > DDR0
+ .boardcfg_data : {} palign(128) > MSMC3
+ .sysmem : {} > DDR0
+ .data_buffer : {} palign(128) > DDR0
+
+ /* USB or any other LLD buffer for benchmarking */
+ .benchmark_buffer (NOLOAD) {} ALIGN (8) > DDR0
+
+ .stack : {} align(4) > DDR0 (HIGH)
+ .irqStack : {. = . + __IRQ_STACK_SIZE;} align(4) > DDR0 (HIGH)
+ RUN_START(__IRQ_STACK_START)
+ RUN_END(__IRQ_STACK_END)
+ .fiqStack : {. = . + __FIQ_STACK_SIZE;} align(4) > DDR0 (HIGH)
+ RUN_START(__FIQ_STACK_START)
+ RUN_END(__FIQ_STACK_END)
+ .abortStack : {. = . + __ABORT_STACK_SIZE;} align(4) > DDR0 (HIGH)
+ RUN_START(__ABORT_STACK_START)
+ RUN_END(__ABORT_STACK_END)
+ .undStack : {. = . + __UND_STACK_SIZE;} align(4) > DDR0 (HIGH)
+ RUN_START(__UND_STACK_START)
+ RUN_END(__UND_STACK_END)
+ .svcStack : {. = . + __SVC_STACK_SIZE;} align(4) > DDR0 (HIGH)
+ RUN_START(__SVC_STACK_START)
+ RUN_END(__SVC_STACK_END)
+}
diff --git a/packages/ti/build/j721e/linker_r5_sysbios.lds b/packages/ti/build/j721e/linker_r5_sysbios.lds
--- /dev/null
@@ -0,0 +1,37 @@
+/* linker options */
+--fill_value=0
+--stack_size=0x2000
+--heap_size=0x1000
+
+-e __VECS_ENTRY_POINT
+
+MEMORY
+{
+ R5F_TCMA_SBL_RSVD(X): ORIGIN = 0x00000000 , LENGTH = 0x100
+ RESET_VECTORS(X) : ORIGIN = 0x41c40000 , LENGTH = 0x100 /* Bottom 256 KB used by SBL */
+ R5F_TCMB0(RWIX) : ORIGIN = 0x41010000 , LENGTH = 0x00008000
+ DDR0 (RWIX) : ORIGIN = 0x80000000 , LENGTH = 0x80000000
+}
+
+SECTIONS
+{
+ .vecs : {
+ __VECS_ENTRY_POINT = .;
+ } palign(8) > RESET_VECTORS
+ .text_boot {
+ *boot.aer5f<*boot.o*>(.text)
+ } palign(8) > R5F_TCMB0
+ .text:xdc_runtime_Startup_reset__I : {} palign(8) > R5F_TCMB0
+ .text:ti_sysbios_family_arm_v7r_Cache* : {} palign(8) > R5F_TCMB0
+ .text:ti_sysbios_family_arm_MPU* : {} palign(8) > R5F_TCMB0
+
+ .text : {} palign(8) > DDR0
+ .cinit : {} palign(8) > DDR0
+ .bss : {} align(8) > DDR0
+ .far : {} align(8) > DDR0
+ .const : {} palign(8) > DDR0
+ .data : {} palign(128) > DDR0
+ .sysmem : {} align(8) > DDR0
+ .stack : {} align(4) > DDR0
+ .data_buffer: {} palign(128) > DDR0
+}
\ No newline at end of file
diff --git a/packages/ti/build/j721e/r5_mpu.xs b/packages/ti/build/j721e/r5_mpu.xs
--- /dev/null
@@ -0,0 +1,159 @@
+/*
+ * Copyright (c) 2019, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/*
+ * ======== event_MPU.xs ========
+ * MPU Settings for J721E device's Cortex-R5F
+ */
+
+/*
+ * -------------------------------------------------------------------------------------------------------------
+ * | Id | Base Address | Size | En | Cacheable | XN | AccPerm | Mask |
+ * |----|--------------|------|----|-------------------------------------------|----|---------------------|------|
+ * | 0 | 0x00000000 | 4GB | T | uncacheable, Shareable | F | RW at PL 1 & PL 2 | 0x0 |
+ * |----|--------------|------|----|-------------------------------------------|----|---------------------|------|
+ * | 1 | 0 (local TCM)| 32K | T | Write-Back, Write-Allocate, Non-Shareable | F | RW at PL 1 | 0x0 |
+ * |----|--------------|------|----|-------------------------------------------|----|---------------------|------|
+ * | 2 | 0x41000000 | 32K | T | Write-Back, Write-Allocate, Non-Shareable | F | RW at PL 1 | 0x0 |
+ * |----|--------------|------|----|-------------------------------------------|----|---------------------|------|
+ * | 3 | 0x41010000 | 32K | T | Write-Back, Write-Allocate, Non-Shareable | F | RW at PL 1 | 0x0 |
+ * |----|--------------|------|----|-------------------------------------------|----|---------------------|------|
+ * | 4 | 0x41C00000 | 1MB | T | Write-Back, Write-Allocate, Non-Shareable | F | RW at PL 1 | 0x0 |
+ * -------------------------------------------------------------------------------------------------------------
+ * | 5 | 0x70000000 | 8MB | T | MSMC Ram - Cachable | F | RW at PL 1 | 0x0 |
+ * -------------------------------------------------------------------------------------------------------------
+ * | 6 | 0x80000000 | 2GB | T | DDR - Strongly Ordered, Shareable | F | RW at PL 1 & PL 3 | 0x0 |
+ * -------------------------------------------------------------------------------------------------------------
+ * | 7 | 0xAA000000 | 32MB | T | DDR (VRing Buffer) - Uncacheble | F | RW at PL 1 & PL 3 | 0x0 |
+ * |-------------------------------------------------------------------------------------------------------------|
+ */
+
+/*
+ * Note: Marking a region as shareable will cause the region to behave as outer shareable with write through
+ * no write-allocate caching policy irrespective of the actual cache policy set. Therefore, only select
+ * regions that are actually shared outside the R5 CPUSS must be marked as shared.
+ */
+
+var MPU = xdc.useModule('ti.sysbios.family.arm.MPU');
+MPU.enableMPU = true;
+MPU.enableBackgroundRegion = true;
+
+var attrs = new MPU.RegionAttrs();
+MPU.initRegionAttrsMeta(attrs);
+
+/* This entry covers the whole 32 bit memory range
+ Address: 0x00000000-0xffffffff */
+attrs.enable = true;
+attrs.bufferable = false;
+attrs.cacheable = false;
+attrs.shareable = true;
+attrs.noExecute = true;
+attrs.accPerm = 1; /* RW at PL1 */
+attrs.tex = 0;
+attrs.subregionDisableMask = 0;
+MPU.setRegionMeta(0, 0x00000000, MPU.RegionSize_4G, attrs);
+
+/* This entry covers the ATCM mapped to 0 */
+attrs.enable = true;
+attrs.bufferable = true;
+attrs.cacheable = true;
+attrs.shareable = true;
+attrs.noExecute = false;
+attrs.accPerm = 1; /* RW at PL1 */
+attrs.tex = 1;
+attrs.subregionDisableMask = 0;
+MPU.setRegionMeta(1, 0x00000000, MPU.RegionSize_32K, attrs);
+
+/* This entry covers ATCM if mapped to 0x41000000 */
+attrs.enable = true;
+attrs.bufferable = true;
+attrs.cacheable = true;
+attrs.shareable = false;
+attrs.noExecute = false;
+attrs.accPerm = 1; /* RW at PL1 */
+attrs.tex = 1;
+attrs.subregionDisableMask = 0;
+MPU.setRegionMeta(2, 0x41000000, MPU.RegionSize_32K, attrs);
+
+/* This entry covers BTCM if mapped to 0x41010000 */
+attrs.enable = true;
+attrs.bufferable = true;
+attrs.cacheable = true;
+attrs.shareable = false;
+attrs.noExecute = false;
+attrs.accPerm = 1; /* RW at PL1 */
+attrs.tex = 1;
+attrs.subregionDisableMask = 0x0;
+MPU.setRegionMeta(3, 0x41010000, MPU.RegionSize_32K, attrs);
+
+/* This entry covers RAM0 */
+attrs.enable = true;
+attrs.bufferable = true;
+attrs.cacheable = true;
+attrs.shareable = false;
+attrs.noExecute = false;
+attrs.accPerm = 1; /* RW at PL1 */
+attrs.tex = 1;
+attrs.subregionDisableMask = 0;
+MPU.setRegionMeta(4, 0x41C00000, MPU.RegionSize_1M, attrs);
+
+/* This entry covers MSMC SRAM */
+attrs.enable = true;
+attrs.bufferable = true;
+attrs.cacheable = true;
+attrs.shareable = false;
+attrs.noExecute = false;
+attrs.accPerm = 1; /* RW at PL1 */
+attrs.tex = 1;
+attrs.subregionDisableMask = 0;
+MPU.setRegionMeta(5, 0x70000000, MPU.RegionSize_8M, attrs);
+
+/* This entry covers DDR memory */
+attrs.enable = true;
+attrs.bufferable = true;
+attrs.cacheable = true;
+attrs.shareable = false;
+attrs.noExecute = false;
+attrs