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raw | patch | inline | side by side (parent: af9e017)
raw | patch | inline | side by side (parent: af9e017)
author | M V Pratap Reddy <x0257344@ti.com> | |
Fri, 27 Nov 2020 03:54:01 +0000 (09:24 +0530) | ||
committer | Sivaraj R <sivaraj@ti.com> | |
Fri, 27 Nov 2020 06:28:10 +0000 (00:28 -0600) |
packages/ti/board/diag/automation_header/src/automation_header_test.c | patch | blob | history | |
packages/ti/board/diag/automation_header/src/automation_header_test.h | patch | blob | history |
diff --git a/packages/ti/board/diag/automation_header/src/automation_header_test.c b/packages/ti/board/diag/automation_header/src/automation_header_test.c
index 0281bff35608d5b747e90f5fc8399d3c06631d50..6bcdbd87ab5248f236b86f3bfdf10f6ea55a8958 100755 (executable)
return -1;
}
-#if (!(defined(SOC_J721E) || defined(SOC_J7200)))
+#if (!(defined(SOC_J721E) || defined(SOC_J7200) || defined(SOC_AM64X)))
UART_printf("\n\rWriting the output PORT2 register value "
"of I2C Boot mode buffer...\n\r");
ret = BoardDiag_write_register(handle,
{
return -1;
}
-#if (defined(SOC_J721E) || defined(SOC_J7200) || defined(SOC_AM65XX) || defined(SOC_AM64X)) && !defined (__aarch64__)
+#if (defined(SOC_J721E) || defined(SOC_J7200) || defined(SOC_AM65XX)) && !defined (__aarch64__)
/* MCU I2C instance will be active by default for R5 core.
* Need update HW attrs to enable MAIN I2C instance.
*/
diff --git a/packages/ti/board/diag/automation_header/src/automation_header_test.h b/packages/ti/board/diag/automation_header/src/automation_header_test.h
index 30bd6ca748c40950c87f9d9b8bee80d60a58591f..b19865da0cf391c8dd87d2379e876676b18b1445 100755 (executable)
#define BOOTMODE_CFG_SET1_PIN_POS (0x00U)
#define BOOTMODE_CFG_SET2_PIN_POS (0x07U)
#elif defined(SOC_AM64X)
-#define BOOTMODE_CFG_SET1_PIN_POS (0x06U) /* SW3 */ //AM64X_TODO: Need to update the value
-#define BOOTMODE_CFG_SET2_PIN_POS (0x10U) /* SW2 */ //AM64X_TODO: Need to update the value
+#define BOOTMODE_CFG_SET1_PIN_POS (0x3BU) /* SW2 */
+#define BOOTMODE_CFG_SET2_PIN_POS (0x00U) /* SW3 */
#else
#define BOOTMODE_CFG_SET1_PIN_POS (0x06U) /* SW3 */
#define BOOTMODE_CFG_SET2_PIN_POS (0x10U) /* SW2 */