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raw | patch | inline | side by side (parent: d1cfb8a)
| author | Jacob Stiffler <j-stiffler@ti.com> | |
| Fri, 1 Nov 2019 18:58:27 +0000 (14:58 -0400) | ||
| committer | Jacob Stiffler <j-stiffler@ti.com> | |
| Fri, 1 Nov 2019 18:58:27 +0000 (14:58 -0400) |
Development of dfe-lld has been relocated here from:
* Repo: https://git.ti.com/keystone-rtos/dfe-lld
* Branch: master
* Commit ID: 023af1b39ec1df7f463797cb8be94e5985dbaefd
Signed-off-by: Jacob Stiffler <j-stiffler@ti.com>
* Repo: https://git.ti.com/keystone-rtos/dfe-lld
* Branch: master
* Commit ID: 023af1b39ec1df7f463797cb8be94e5985dbaefd
Signed-off-by: Jacob Stiffler <j-stiffler@ti.com>
194 files changed:
diff --git a/packages/ti/drv/dfe/.cdtproject b/packages/ti/drv/dfe/.cdtproject
--- /dev/null
@@ -0,0 +1,56 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<?eclipse-cdt version="2.0"?>
+
+<cdtproject id="org.eclipse.cdt.make.core.make">
+<extension id="com.ti.ccstudio.binaryparser.CoffParser" point="org.eclipse.cdt.core.BinaryParser"/>
+<data>
+<item id="scannerConfiguration">
+<autodiscovery enabled="false" problemReportingEnabled="true" selectedProfileId="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile"/>
+<profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">
+<buildOutputProvider>
+<openAction enabled="true" filePath=""/>
+<parser enabled="true"/>
+</buildOutputProvider>
+<scannerInfoProvider id="specsFile">
+<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+<parser enabled="true"/>
+</scannerInfoProvider>
+</profile>
+<profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">
+<buildOutputProvider>
+<openAction enabled="false" filePath=""/>
+<parser enabled="true"/>
+</buildOutputProvider>
+<scannerInfoProvider id="makefileGenerator">
+<runAction arguments="-f ${project_name}_scd.mk" command="make" useDefault="true"/>
+<parser enabled="false"/>
+</scannerInfoProvider>
+</profile>
+<profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
+<buildOutputProvider>
+<openAction enabled="false" filePath=""/>
+<parser enabled="true"/>
+</buildOutputProvider>
+<scannerInfoProvider id="specsFile">
+<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+<parser enabled="false"/>
+</scannerInfoProvider>
+</profile>
+<profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+<buildOutputProvider>
+<openAction enabled="false" filePath=""/>
+<parser enabled="true"/>
+</buildOutputProvider>
+<scannerInfoProvider id="specsFile">
+<runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+<parser enabled="false"/>
+</scannerInfoProvider>
+</profile>
+</item>
+<item id="org.eclipse.cdt.core.pathentry">
+<pathentry kind="src" path=""/>
+<pathentry kind="out" path=""/>
+<pathentry kind="con" path="org.eclipse.cdt.make.core.DISCOVERED_SCANNER_INFO"/>
+</item>
+</data>
+</cdtproject>
diff --git a/packages/ti/drv/dfe/.cproject b/packages/ti/drv/dfe/.cproject
--- /dev/null
@@ -0,0 +1,71 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?>
+
+<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+ <storageModule moduleId="org.eclipse.cdt.core.settings">
+ <cconfiguration id="converted.config.873220660">
+ <storageModule moduleId="scannerConfiguration">
+ <autodiscovery enabled="false" problemReportingEnabled="true" selectedProfileId="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile"/>
+ <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerProjectProfile">
+ <buildOutputProvider>
+ <openAction enabled="true" filePath=""/>
+ <parser enabled="true"/>
+ </buildOutputProvider>
+ <scannerInfoProvider id="specsFile">
+ <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+ <parser enabled="true"/>
+ </scannerInfoProvider>
+ </profile>
+ <profile id="org.eclipse.cdt.make.core.GCCStandardMakePerFileProfile">
+ <buildOutputProvider>
+ <openAction enabled="false" filePath=""/>
+ <parser enabled="true"/>
+ </buildOutputProvider>
+ <scannerInfoProvider id="makefileGenerator">
+ <runAction arguments="-f ${project_name}_scd.mk" command="make" useDefault="true"/>
+ <parser enabled="false"/>
+ </scannerInfoProvider>
+ </profile>
+ <profile id="org.eclipse.cdt.managedbuilder.core.GCCManagedMakePerProjectProfile">
+ <buildOutputProvider>
+ <openAction enabled="false" filePath=""/>
+ <parser enabled="true"/>
+ </buildOutputProvider>
+ <scannerInfoProvider id="specsFile">
+ <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+ <parser enabled="false"/>
+ </scannerInfoProvider>
+ </profile>
+ <profile id="org.eclipse.cdt.managedbuilder.core.GCCWinManagedMakePerProjectProfile">
+ <buildOutputProvider>
+ <openAction enabled="false" filePath=""/>
+ <parser enabled="true"/>
+ </buildOutputProvider>
+ <scannerInfoProvider id="specsFile">
+ <runAction arguments="-E -P -v -dD ${plugin_state_location}/${specs_file}" command="gcc" useDefault="true"/>
+ <parser enabled="false"/>
+ </scannerInfoProvider>
+ </profile>
+ </storageModule>
+ <storageModule buildSystemId="org.eclipse.cdt.core.defaultConfigDataProvider" id="converted.config.873220660" moduleId="org.eclipse.cdt.core.settings" name="convertedConfig">
+ <externalSettings/>
+ <extensions>
+ <extension id="com.ti.ccstudio.binaryparser.CoffParser" point="org.eclipse.cdt.core.BinaryParser"/>
+ </extensions>
+ </storageModule>
+ <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+ </cconfiguration>
+ </storageModule>
+ <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+ <storageModule moduleId="org.eclipse.cdt.internal.ui.text.commentOwnerProjectMappings"/>
+ <storageModule moduleId="org.eclipse.cdt.core.pathentry">
+ <pathentry include="C:/ti/keystone-2-csl-lld-lamarr" kind="inc" path="" system="true"/>
+ <pathentry include="C:/ccs55/ccsv5/tools/compiler/c6000_7.4.4/include" kind="inc" path="" system="true"/>
+ <pathentry kind="mac" name="_TMS320C6600" path="" value="TRUE"/>
+ <pathentry kind="mac" name="_TMS320C6X" path="" value="TRUE"/>
+ <pathentry kind="mac" name="K2" path="" value="TRUE"/>
+ <pathentry kind="src" path=""/>
+ <pathentry kind="out" path=""/>
+ <pathentry kind="con" path="org.eclipse.cdt.make.core.DISCOVERED_SCANNER_INFO"/>
+ </storageModule>
+</cproject>
diff --git a/packages/ti/drv/dfe/.gitignore b/packages/ti/drv/dfe/.gitignore
--- /dev/null
@@ -0,0 +1,39 @@
+#### Files to ignore ###
+
+*.obj
+*.geany
+*.mak
+*.project
+*.cproject
+*.cdtproject
+*.settings/
+s2qk
+s7c
+s2ic
+sbg
+*.ae6*
+s3ck
+*.dlls
+*.executables
+*.interfaces
+*.libraries
+*.ccsproject
+*.cproject
+*.project
+*.xdchelp
+*.png
+*.css
+*.chm
+package/
+*definePathVariable.ini
+*exe/
+*Settings.h
+*Settings.xdc
+*Doxyfile
+.metadata/
+packages/
+lib/
+docs/doxygen/
+docs/doxygen/html/
+bin/
+obj/
diff --git a/packages/ti/drv/dfe/.project b/packages/ti/drv/dfe/.project
--- /dev/null
@@ -0,0 +1,86 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+ <name>ti.drv.dfe</name>
+ <comment></comment>
+ <projects>
+ </projects>
+ <buildSpec>
+ <buildCommand>
+ <name>org.eclipse.cdt.make.core.makeBuilder</name>
+ <triggers>clean,full,incremental,</triggers>
+ <arguments>
+ <dictionary>
+ <key>org.eclipse.cdt.make.core.build.arguments</key>
+ <value></value>
+ </dictionary>
+ <dictionary>
+ <key>org.eclipse.cdt.core.errorOutputParser</key>
+ <value>org.eclipse.rtsc.xdctools.ui.RTSCErrorParser;com.ti.ccstudio.errorparser.CoffErrorParser;com.ti.ccstudio.errorparser.AsmErrorParser;com.ti.ccstudio.errorparser.LinkErrorParser;org.eclipse.cdt.core.MakeErrorParser;org.eclipse.cdt.core.GCCErrorParser;org.eclipse.cdt.core.GASErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.VCErrorParser;</value>
+ </dictionary>
+ <dictionary>
+ <key>org.eclipse.cdt.make.core.enableAutoBuild</key>
+ <value>false</value>
+ </dictionary>
+ <dictionary>
+ <key>org.eclipse.cdt.make.core.environment</key>
+ <value></value>
+ </dictionary>
+ <dictionary>
+ <key>org.eclipse.cdt.make.core.enableFullBuild</key>
+ <value>true</value>
+ </dictionary>
+ <dictionary>
+ <key>org.eclipse.cdt.make.core.build.target.inc</key>
+ <value>all</value>
+ </dictionary>
+ <dictionary>
+ <key>org.eclipse.cdt.make.core.enabledIncrementalBuild</key>
+ <value>true</value>
+ </dictionary>
+ <dictionary>
+ <key>org.eclipse.cdt.make.core.build.location</key>
+ <value></value>
+ </dictionary>
+ <dictionary>
+ <key>org.eclipse.cdt.make.core.build.target.clean</key>
+ <value>clean</value>
+ </dictionary>
+ <dictionary>
+ <key>org.eclipse.cdt.make.core.build.command</key>
+ <value>XDC</value>
+ </dictionary>
+ <dictionary>
+ <key>org.eclipse.cdt.make.core.enableCleanBuild</key>
+ <value>true</value>
+ </dictionary>
+ <dictionary>
+ <key>org.eclipse.cdt.make.core.append_environment</key>
+ <value>true</value>
+ </dictionary>
+ <dictionary>
+ <key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
+ <value>false</value>
+ </dictionary>
+ <dictionary>
+ <key>org.eclipse.cdt.make.core.build.target.auto</key>
+ <value>all</value>
+ </dictionary>
+ <dictionary>
+ <key>org.eclipse.cdt.make.core.stopOnError</key>
+ <value>false</value>
+ </dictionary>
+ </arguments>
+ </buildCommand>
+ <buildCommand>
+ <name>org.eclipse.cdt.make.core.ScannerConfigBuilder</name>
+ <arguments>
+ </arguments>
+ </buildCommand>
+ </buildSpec>
+ <natures>
+ <nature>org.eclipse.cdt.core.cnature</nature>
+ <nature>org.eclipse.cdt.make.core.makeNature</nature>
+ <nature>org.eclipse.cdt.make.core.ScannerConfigNature</nature>
+ <nature>org.eclipse.cdt.core.ccnature</nature>
+ </natures>
+</projectDescription>
diff --git a/packages/ti/drv/dfe/COPYING.txt b/packages/ti/drv/dfe/COPYING.txt
--- /dev/null
@@ -0,0 +1,33 @@
+/* Copyright (c) 2014, Texas Instruments Incorporated
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of the Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+ * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
diff --git a/packages/ti/drv/dfe/Settings.xdc.xdt b/packages/ti/drv/dfe/Settings.xdc.xdt
--- /dev/null
@@ -0,0 +1,25 @@
+
+%%{
+/*!
+ * This template implements the Settings.xdc
+ */
+ /* Versioning */
+ var ver = this;
+ for each(i=0;i<ver.length;i++)
+ {
+ if(String(ver[i]).length < 2)
+ {
+ ver[i]="0"+ver[i];
+ }
+ }
+
+ var packageVersion = "\""+ver[0]+"."+ver[1]+"."+ver[2]+"."+ver[3]+"\"";
+
+%%}
+
+module Settings
+{
+ config string dfelldVersionString = `packageVersion`;
+
+}
+
diff --git a/packages/ti/drv/dfe/build/armv7/libdfe_aearmv7.mk b/packages/ti/drv/dfe/build/armv7/libdfe_aearmv7.mk
--- /dev/null
@@ -0,0 +1,184 @@
+#*******************************************************************************
+#* FILE PURPOSE: Lower level makefile for Creating Component Libraries for ARMv7
+#*******************************************************************************
+#* FILE NAME: ./lib/libdfe_aearmv7.mk
+#*
+#* DESCRIPTION: Defines Source Files, Compilers flags and build rules
+#*
+#*******************************************************************************
+#
+
+#
+# Macro definitions referenced below
+#
+empty =
+space =$(empty) $(empty)
+
+# Output for prebuilt generated libraries
+ARMV7LIBDIR ?= ./lib
+ARMV7OBJDIR ?= ./obj
+ARMV7OBJDIR := $(ARMV7OBJDIR)/dfe/lib
+ARMV7OBJDIR_SO := $(ARMV7OBJDIR)/dfe/lib_so
+ARMV7BINDIR ?= ./bin
+DEBUG_FLAG ?= -O2
+
+ifdef CROSS_TOOL_INSTALL_PATH
+# Support backwards compatibility with KeyStone1 approach
+ CC = $(CROSS_TOOL_INSTALL_PATH)/$(CROSS_TOOL_PRFX)gcc
+ AC = $(CROSS_TOOL_INSTALL_PATH)/$(CROSS_TOOL_PRFX)as
+ AR = $(CROSS_TOOL_INSTALL_PATH)/$(CROSS_TOOL_PRFX)ar
+ LD = $(CROSS_TOOL_INSTALL_PATH)/$(CROSS_TOOL_PRFX)gcc
+endif
+
+INCS = -I. -I$(strip $(subst ;, -I,$(subst $(space),\$(space),$(INCDIR))))
+
+INTERNALDEFS = -D__ARMv7 -D_LITTLE_ENDIAN=1 -D_VIRTUAL_ADDR_SUPPORT -DMAKEFILE_BUILD -D__LINUX_USER_SPACE__
+
+CFLAGS += $(INTERNALDEFS) $(DEBUG_FLAG)
+
+OBJEXT = o
+INTERNALLINKDEFS =
+SRCDIR = ./src
+
+VPATH=$(SRCDIR)
+
+#List the COMMONSRC Files
+COMMONSRCC = \
+ dfefl/dfe_fl_Close.c \
+ dfefl/dfe_fl_Init.c \
+ dfefl/dfe_fl_Open.c \
+ dfefl/dfe_fl_autocpClose.c \
+ dfefl/dfe_fl_autocppGetHwStatus.c \
+ dfefl/dfe_fl_autocppHwControl.c \
+ dfefl/dfe_fl_autocppOpen.c \
+ dfefl/dfe_fl_bbClose.c \
+ dfefl/dfe_fl_bbGetHwStatus.c \
+ dfefl/dfe_fl_bbHwControl.c \
+ dfefl/dfe_fl_bbOpen.c \
+ dfefl/dfe_fl_cbClose.c \
+ dfefl/dfe_fl_cbGetHwStatus.c \
+ dfefl/dfe_fl_cbHwControl.c \
+ dfefl/dfe_fl_cbOpen.c \
+ dfefl/dfe_fl_cdfrClose.c \
+ dfefl/dfe_fl_cdfrGetHwStatus.c \
+ dfefl/dfe_fl_cdfrHwControl.c \
+ dfefl/dfe_fl_cdfrOpen.c \
+ dfefl/dfe_fl_cfrClose.c \
+ dfefl/dfe_fl_cfrGetHwStatus.c \
+ dfefl/dfe_fl_cfrHwControl.c \
+ dfefl/dfe_fl_cfrOpen.c \
+ dfefl/dfe_fl_cppDescripClose.c \
+ dfefl/dfe_fl_cppDescripControl.c \
+ dfefl/dfe_fl_cppDescripOpen.c \
+ dfefl/dfe_fl_cppDescripStatus.c \
+ dfefl/dfe_fl_cppDmaClose.c \
+ dfefl/dfe_fl_cppDmaControl.c \
+ dfefl/dfe_fl_cppDmaOpen.c \
+ dfefl/dfe_fl_cppDmaStatus.c \
+ dfefl/dfe_fl_dducClose.c \
+ dfefl/dfe_fl_dducGetHwStatus.c \
+ dfefl/dfe_fl_dducHwControl.c \
+ dfefl/dfe_fl_dducOpen.c \
+ dfefl/dfe_fl_dpdClose.c \
+ dfefl/dfe_fl_dpdGetHwStatus.c \
+ dfefl/dfe_fl_dpdHwControl.c \
+ dfefl/dfe_fl_dpdOpen.c \
+ dfefl/dfe_fl_dpdaClose.c \
+ dfefl/dfe_fl_dpdaGetHwStatus.c \
+ dfefl/dfe_fl_dpdaHwControl.c \
+ dfefl/dfe_fl_dpdaOpen.c \
+ dfefl/dfe_fl_fbClose.c \
+ dfefl/dfe_fl_fbGetHwStatus.c \
+ dfefl/dfe_fl_fbHwControl.c \
+ dfefl/dfe_fl_fbOpen.c \
+ dfefl/dfe_fl_jesdClose.c \
+ dfefl/dfe_fl_jesdGetHwStatus.c \
+ dfefl/dfe_fl_jesdHwControl.c \
+ dfefl/dfe_fl_jesdOpen.c \
+ dfefl/dfe_fl_miscClose.c \
+ dfefl/dfe_fl_miscGetHwStatus.c \
+ dfefl/dfe_fl_miscHwControl.c \
+ dfefl/dfe_fl_miscOpen.c \
+ dfefl/dfe_fl_rxClose.c \
+ dfefl/dfe_fl_rxGetHwStatus.c \
+ dfefl/dfe_fl_rxHwControl.c \
+ dfefl/dfe_fl_rxOpen.c \
+ dfefl/dfe_fl_summerClose.c \
+ dfefl/dfe_fl_summerGetHwStatus.c \
+ dfefl/dfe_fl_summerHwControl.c \
+ dfefl/dfe_fl_summerOpen.c \
+ dfefl/dfe_fl_txClose.c \
+ dfefl/dfe_fl_txGetHwStatus.c \
+ dfefl/dfe_fl_txHwControl.c \
+ dfefl/dfe_fl_txOpen.c \
+ dfelld/DFE_bb.c \
+ dfelld/DFE_cb.c \
+ dfelld/DFE_cfr.c \
+ dfelld/DFE_dduc.c \
+ dfelld/DFE_device.c \
+ dfelld/DFE_dpd.c \
+ dfelld/DFE_dpda.c \
+ dfelld/DFE_excep.c \
+ dfelld/DFE_fb.c \
+ dfelld/DFE_jesd.c \
+ dfelld/DFE_misc.c \
+ dfelld/DFE_open.c \
+ dfelld/DFE_rx.c \
+ dfelld/DFE_summer.c \
+ dfelld/DFE_sync.c \
+ dfelld/DFE_tx.c
+
+
+
+# FLAGS for the COMMONSRC Files
+COMMONSRCCFLAGS = $(DEBUG_FLAG) -I$(SRCDIR) -I.
+CFLAGS += $(COMMONSRCCFLAGS)
+
+# Make Rule for the COMMONSRC Files
+COMMONSRCCOBJS = $(patsubst %.c, $(ARMV7OBJDIR)/%.$(OBJEXT), $(COMMONSRCC))
+COMMONSRCCOBJS_SO = $(patsubst %.c, $(ARMV7OBJDIR_SO)/%.$(OBJEXT), $(COMMONSRCC))
+
+$(COMMONSRCCOBJS): $(ARMV7OBJDIR)/%.$(OBJEXT): %.c $(ARMV7OBJDIR)/.created
+ -@echo compiling $< ...
+ @$(CC) -c $(CFLAGS) $(INCS) $< -o $@
+
+$(COMMONSRCCOBJS_SO): $(ARMV7OBJDIR_SO)/%.$(OBJEXT): %.c $(ARMV7OBJDIR_SO)/.created
+ -@echo compiling $< ...
+ @$(CC) -c $(CFLAGS) -fPIC $(INCS) $< -o $@
+
+$(ARMV7LIBDIR)/libdfe.a: $(COMMONSRCCOBJS) $(ARMV7LIBDIR)/.created
+ @echo archiving $? into $@ ...
+ @$(AR) -r $@ $?
+
+libdfe.so: $(COMMONSRCCOBJS_SO)
+ @echo archiving $? into $(ARMV7LIBDIR)/$@.1 ...
+ @$(CC) $(DEBUG_FLAG) -ggdb2 -Wl,-soname=$@.1 -shared -fPIC ${LDFLAGS} -o $@.1.0.0 $^
+ @ln -s $@.1.0.0 $@.1
+ @ln -s $@.1 $@
+ @mv -f $@.1.0.0 $(ARMV7LIBDIR)/$@.1.0.0
+ @mv -f $@.1 $(ARMV7LIBDIR)/$@.1
+ @mv -f $@ $(ARMV7LIBDIR)/$@
+
+$(ARMV7OBJDIR)/.created:
+ @mkdir -p $(ARMV7OBJDIR)
+ @mkdir -p $(ARMV7OBJDIR)/dfefl
+ @mkdir -p $(ARMV7OBJDIR)/dfelld
+ @touch $(ARMV7OBJDIR)/.created
+ @touch $(ARMV7OBJDIR)/dfefl/.created
+ @touch $(ARMV7OBJDIR)/dfelld/.created
+
+$(ARMV7OBJDIR_SO)/.created:
+ @mkdir -p $(ARMV7OBJDIR_SO)
+ @mkdir -p $(ARMV7OBJDIR_SO)/dfefl
+ @mkdir -p $(ARMV7OBJDIR_SO)/dfelld
+ @touch $(ARMV7OBJDIR_SO)/.created
+ @touch $(ARMV7OBJDIR_SO)/dfefl/.created
+ @touch $(ARMV7OBJDIR_SO)/dfelld/.created
+
+$(ARMV7LIBDIR)/.created:
+ @mkdir -p $(ARMV7LIBDIR)
+ @touch $(ARMV7LIBDIR)/.created
+
+clean:
+ @$(RMDIR) $(ARMV7OBJDIR)
+
diff --git a/packages/ti/drv/dfe/build/buildlib.xs b/packages/ti/drv/dfe/build/buildlib.xs
--- /dev/null
@@ -0,0 +1,553 @@
+/******************************************************************************
+ * FILE PURPOSE: Build Library Utilities
+ ******************************************************************************
+ * FILE NAME: buildlib.xs
+ *
+ * DESCRIPTION:
+ * This file contains common routines that are used by the various DFE
+ * components.
+ *
+ * Copyright (C) 2012-13, Texas Instruments, Inc.
+ *****************************************************************************/
+
+/**************************************************************************
+ * FUNCTION NAME : listAllFiles
+ **************************************************************************
+ * DESCRIPTION :
+ * Utility function which lists all files with a specific extension
+ * present in a directory and any directory inside it.
+ **************************************************************************/
+function listAllFiles(ext, dir, recurse)
+{
+ var srcFile = [];
+ var d;
+
+ /* If recurse parameter is not specified we default to recursive search. */
+ if (recurse == null)
+ recurse = true;
+
+ if (dir == undefined)
+ d = ".";
+ else
+ d = dir;
+
+ /* Get access to the current directory. */
+ var file = new java.io.File(d);
+
+ /* Check if the file exists and it is a directory. */
+ if (file.exists() && file.isDirectory())
+ {
+ /* Get a list of all files in the specific directory. */
+ var fileList = file.listFiles();
+ for (var i = 0; i < fileList.length; i++)
+ {
+ /* Dont add the generated directory 'package' and any of its files
+ * to the list here. */
+ if (fileList[i].getName().matches("package") == false)
+ {
+ /* Check if the detected file is a directory */
+ if (fileList[i].isDirectory())
+ {
+ /* We will recurse into the subdirectory only if required to do so. */
+ if (recurse == true)
+ {
+ /* Generate the directory Name in which we will recurse. */
+ var directoryName = d + "/" + fileList[i].getName();
+
+ /* Get a list of all files in this directory */
+ var fileListing = listAllFiles (ext, directoryName, recurse);
+ if (fileListing != null)
+ {
+ /* Return a list of all file names in the directory. */
+ for (var j = 0 ; j < fileListing.length; j++)
+ srcFile[srcFile.length++] = fileListing[j];
+ }
+ }
+ }
+ else
+ {
+ /* This was a file. Check if the file name matches the extension */
+ if (fileList[i].getName().endsWith(ext) == true)
+ srcFile[srcFile.length++] = d + "/" + fileList[i].getName();
+ }
+ }
+ }
+
+ return srcFile;
+ }
+ return null;
+}
+
+
+function createMake(makefile)
+{
+ /* Create the main make file */
+ var fileModule = xdc.module('xdc.services.io.File');
+ if(makefile==undefined)
+ {
+ try{
+ makefile = fileModule.open("makefile", "w");
+ } catch (ex)
+ {
+ print("makefile cannot be written to. Please check Writing Permissions.");
+ java.lang.System.exit(1);
+ }
+
+ Pkg.makePrologue += "\ninclude makefile\n";
+
+ Pkg.makeEpilogue += "\nclean::\n\t-$(RM) makefile\n";
+ makefile.writeLine("#*******************************************************************************");
+ makefile.writeLine("#* FILE PURPOSE: Top level makefile for Creating Component Libraries");
+ makefile.writeLine("#*******************************************************************************");
+ makefile.writeLine("#* FILE NAME: makefile");
+ makefile.writeLine("#*");
+ makefile.writeLine("#* DESCRIPTION: Defines Compiler tools paths, libraries , Build Options ");
+ makefile.writeLine("#*");
+ makefile.writeLine("#*");
+ makefile.writeLine("#*******************************************************************************");
+ makefile.writeLine("#*");
+ makefile.writeLine("# (Mandatory) Specify where various tools are installed.");
+
+ var file = xdc.module('xdc.services.io.File');
+
+ var xdcTargetType = java.lang.System.getenv("XDCTARGET");
+ var toolsBaseDir = java.lang.System.getenv("XDCCGROOT");
+
+ makefile.writeLine("\n# Output for prebuilt generated libraries");
+ makefile.writeLine("export LIBDIR ?= ./lib");
+ /* use sectti.exe from path */
+ makefile.writeLine("export SECTTI ?= sectti");
+
+ /* Create INCDIR from XDCPATH */
+
+ /* copy the environment array from the current environment */
+ var env = java.lang.System.getenv();
+ var getxdcpath=String(java.lang.System.getenv("XDCPATH"));
+ getxdcpath= getxdcpath.replace(/\\/g,"/");
+ var keys = env.keySet().toArray();
+ var key;
+ var stat={};
+ var env_j=[];
+ var listxdcpath = new Array();
+ for (var i = 0; i < keys.length; i++) {
+ key = String(keys[i]);
+ if((key.match("INSTALL_PATH")) || (key.match("INSTALLDIR")))
+ {
+ var keyPath=String(env.get(key));
+ keyPath=keyPath.replace(/\\/g,"/");
+ var file = xdc.module('xdc.services.io.File');
+ keyPath=file.getDOSPath(keyPath);
+ if(getxdcpath.toString().match(keyPath))
+ {
+ listxdcpath.push({keyname: key,keypath: keyPath});
+ while(getxdcpath.toString().match(keyPath))
+ {
+ getxdcpath=getxdcpath.toString().replace(keyPath,"$("+key+")");
+ }
+ }
+ }
+
+ }
+ var pkgroot="..";
+ for (var i = Pkg.name.split('.').length; i > 1; i--) {
+ pkgroot+="/..";
+ }
+
+ makefile.writeLine("\n# ROOT Directory");
+ makefile.writeLine("export ROOTDIR := "+pkgroot);
+
+ makefile.writeLine("\n# Include Rules.make");
+ makefile.writeLine("ifndef PDK_INSTALL_DIR_RECIPE");
+ makefile.writeLine("ifeq ($(RULES_MAKE),)");
+ makefile.writeLine("include $(PDK_INSTALL_PATH)/ti/build/Rules.make");
+ makefile.writeLine("else");
+ makefile.writeLine("include $(RULES_MAKE)");
+ makefile.writeLine("endif");
+ makefile.writeLine("endif");
+
+ makefile.writeLine("\n# INCLUDE Directory");
+ makefile.writeLine("export INCDIR := "+getxdcpath+";$(ROOTDIR)");
+
+ makefile.writeLine("\n# Common Macros used in make");
+ makefile.writeLine("\nifndef RM");
+ makefile.writeLine("export RM = rm -f");
+ makefile.writeLine("endif");
+
+ makefile.writeLine("\nifndef CP");
+ makefile.writeLine("export CP = cp -p");
+ makefile.writeLine("endif");
+
+ makefile.writeLine("\nexport MKDIR = mkdir -p");
+
+ makefile.writeLine("\nifndef RMDIR");
+ makefile.writeLine("export RMDIR = rm -rf");
+ makefile.writeLine("endif");
+
+ makefile.writeLine("\nifndef SED");
+ makefile.writeLine("export SED = sed");
+ makefile.writeLine("endif");
+
+ makefile.writeLine("\nifndef MAKE");
+ makefile.writeLine("export MAKE = make");
+ makefile.writeLine("endif");
+
+ makefile.writeLine("\n# PHONY Targets");
+ makefile.writeLine(".PHONY: all clean cleanall ");
+
+ makefile.writeLine("\n# FORCE Targets");
+ makefile.writeLine("FORCE: ");
+
+ makefile.writeLine("\n# all rule");
+ makefile.writeLine("all: .executables");
+ makefile.writeLine(".executables: .libraries");
+ makefile.writeLine(".libraries:");
+
+ makefile.writeLine("\n# Clean Rule");
+ makefile.writeLine("clean:: clean_package");
+ makefile.writeLine("# Clean Top Level Object Directory ");
+ makefile.writeLine("clean_package :\n\t$(RMDIR) $(LIBDIR)/*/");
+ makefile.writeLine("\t$(RMDIR) package/cfg");
+ }
+ else
+ {
+ try{
+ makefile = fileModule.open("makefile", "a");
+ } catch (ex)
+ {
+ print("makefile cannot be written to. Please check Writing Permissions.");
+ java.lang.System.exit(1);
+ }
+
+ }
+
+ return makefile;
+}
+
+function createLibMake(makelibname,targetname, objectPath)
+{
+ var tooldir;
+ var stringname=String(targetname).replace("(xdc.bld.ITarget.Module)","");
+ if(stringname.match("ARM11"))
+ {
+ tooldir="TI_ARM11_GEN_INSTALL_PATH";
+ }
+ else
+ {
+ tooldir="C6X_GEN_INSTALL_PATH";
+ }
+ switch(stringname)
+ {
+ case String(C66LE):
+ targetname=C66LE;
+ break;
+
+ }
+ var fileModule = xdc.module('xdc.services.io.File');
+ try{
+ var dstFile = new java.io.File(makelibname);
+ dstFile.getParentFile().mkdirs();
+ libmakefile = fileModule.open(makelibname, "w");
+ /* Add to Archive list */
+ } catch (ex)
+ {
+ print(makelibname+" cannot be written to. Please check Writing Permissions.");
+ java.lang.System.exit(1);
+ }
+ libmakefile.writeLine("#*******************************************************************************");
+ libmakefile.writeLine("#* FILE PURPOSE: Lower level makefile for Creating Component Libraries");
+ libmakefile.writeLine("#*******************************************************************************");
+ libmakefile.writeLine("#* FILE NAME: "+makelibname);
+ libmakefile.writeLine("#*");
+ libmakefile.writeLine("#* DESCRIPTION: Defines Source Files, Compilers flags and build rules");
+ libmakefile.writeLine("#*");
+ libmakefile.writeLine("#*");
+ libmakefile.writeLine("#*******************************************************************************");
+ libmakefile.writeLine("#");
+ libmakefile.writeLine("");
+ libmakefile.writeLine("#");
+ libmakefile.writeLine("# Macro definitions referenced below");
+ libmakefile.writeLine("#");
+ libmakefile.writeLine("empty =");
+ libmakefile.writeLine("space =$(empty) $(empty)");
+
+ if(stringname.match("ti.targets"))
+ {
+
+ var rtslibtemp = targetname.lnkOpts.suffix.toString().split("/");
+ var rtslib;
+ for(n=0;n<rtslibtemp.length;n++)
+ {
+ if(rtslibtemp[n].match(".lib"))
+ {
+ rtslib=rtslibtemp[n];
+ }
+ }
+
+ libmakefile.writeLine("CC = $("+tooldir+")/bin/"+targetname.cc.cmd +" "+targetname.ccOpts.prefix+" "+targetname.cc.opts);
+ libmakefile.writeLine("AC = $("+tooldir+")/bin/"+targetname.asm.cmd +" "+targetname.asmOpts.prefix+" "+targetname.asm.opts);
+ libmakefile.writeLine("ARIN = $("+tooldir+")/bin/"+targetname.ar.cmd +" "+targetname.ar.opts);
+ libmakefile.writeLine("LD = $("+tooldir+")/bin/"+targetname.lnk.cmd +" "+targetname.lnk.opts);
+ libmakefile.writeLine("RTSLIB = -l $("+tooldir+")/lib/"+rtslib);
+ }
+ else
+ {
+ print("Error: Non-TI targets are not currently supported ");
+ java.lang.System.exit(1);
+
+ }
+
+ libmakefile.writeLine("INCS = -I. -I$(strip $(subst ;, -I,$(subst $(space),\\$(space),$(INCDIR)))) -I$("+tooldir+")/include");
+ libmakefile.writeLine("OBJEXT = o"+targetname.suffix);
+ libmakefile.writeLine("AOBJEXT = s"+targetname.suffix);
+ /* libmakefile.writeLine("INTERNALDEFS = -D"+stringname.replace(/\./g,"_")+" -Dxdc_target_types__=ti/targets/std.h -DMAKEFILE_BUILD -eo.$(OBJEXT) -ea.$(AOBJEXT) -fr=$(@D) -fs=$(@D) -ppa -ppd=$@.dep");*/
+ libmakefile.writeLine("INTERNALDEFS = -D"+stringname.replace(/\./g,"_")+" -DMAKEFILE_BUILD -eo.$(OBJEXT) -ea.$(AOBJEXT) -fr=$(@D) -fs=$(@D) -ppa -ppd=$@.dep");
+ libmakefile.writeLine("INTERNALLINKDEFS = -o $@ -m $@.map");
+ libmakefile.writeLine("OBJDIR = $(LIBDIR)/obj");
+
+ return libmakefile;
+
+}
+
+function makeAddObjects(srcString, makefilename, srcfiles, flags,fileExt, targetName)
+{
+ var sourcestring = (srcString + fileExt).toString().toUpperCase();
+ var compileflagstring = sourcestring + "FLAGS";
+ var objectliststring = sourcestring + "OBJS";
+ /* List all the source files */
+ makefilename.writeLine("\n#List the "+srcString+" Files");
+ makefilename.writeLine(sourcestring + "= \\");
+ for(var i=0;i<srcfiles.length-1;i++)
+ {
+ makefilename.writeLine(" "+srcfiles[i]+"\\");
+ }
+ makefilename.writeLine(" "+srcfiles[i]+"\n");
+
+ /* Flags for the source files */
+ makefilename.writeLine("# FLAGS for the "+srcString+" Files");
+ var compileflags="";
+ if(fileExt == "asm" && flags.aopts != undefined)
+ {
+ compileflags+=" "+flags.aopts;
+ }
+ else if((fileExt == "c" || fileExt == "sa")&& flags.copts != undefined)
+ {
+ compileflags+=" "+flags.copts;
+ }
+
+ if(flags.incs != undefined)
+ {
+ compileflags+=" "+flags.incs;
+ }
+
+
+ makefilename.writeLine(compileflagstring+" = "+compileflags +" \n");
+ makefilename.writeLine("# Make Rule for the "+srcString+" Files");
+
+ makefilename.writeLine(objectliststring +" = $(patsubst %."+fileExt+", $(OBJDIR)/%.$(OBJEXT), $(" + sourcestring + "))");
+ makefilename.writeLine("\n$("+objectliststring+"): $(OBJDIR)/%.$(OBJEXT): %."+fileExt);
+ if(fileExt == "c")
+ {
+ makefilename.writeLine("\t-@echo cl"+targetName.suffix +" $< ...");
+ }
+ else
+ {
+ makefilename.writeLine("\t-@echo asm"+targetName.suffix +" $< ...");
+ }
+ makefilename.writeLine("\tif [ ! -d $(@D) ]; then $(MKDIR) $(@D) ; fi;");
+
+ if(fileExt == "c")
+ {
+ makefilename.writeLine("\t$(RM) $@.dep");
+ makefilename.writeLine("\t$(CC) $("+compileflagstring+") $(INTERNALDEFS) $(INCS) -fc $< ");
+ makefilename.writeLine("\t-@$(CP) $@.dep $@.pp; \\");
+ makefilename.writeLine(" $(SED) -e 's/#.*//' -e 's/^[^:]*: *//' -e 's/ *\\\\$$//' \\");
+ makefilename.writeLine(" -e '/^$$/ d' -e 's/$$/ :/' < $@.pp >> $@.dep; \\");
+ makefilename.writeLine(" $(RM) $@.pp ");
+ }
+ else if(fileExt == "asm")
+ {
+ makefilename.writeLine("\t$(AC) $("+compileflagstring+") $(INTERNALDEFS) $(INCS) -fa $< ");
+ }
+ else if(fileExt == "sa")
+ {
+ makefilename.writeLine("\t$(AC) $("+compileflagstring+") $(INTERNALDEFS) $(INCS) $< ");
+ }
+ makefilename.writeLine("\n#Create Empty rule for dependency");
+ makefilename.writeLine("$("+objectliststring+"):"+makefilename.$private.fd);
+ makefilename.writeLine(makefilename.$private.fd+":");
+ makefilename.writeLine("\n#Include Depedency for "+srcString+" Files");
+ makefilename.writeLine("ifneq (clean,$(MAKECMDGOALS))");
+ makefilename.writeLine(" -include $("+objectliststring+":%.$(OBJEXT)=%.$(OBJEXT).dep)");
+ makefilename.writeLine("endif");
+
+}
+
+/**************************************************************************
+ * FUNCTION NAME : buildLibrary
+ **************************************************************************
+ * DESCRIPTION :
+ * Utility function which will build a specific library
+ **************************************************************************/
+var makefilelocal;
+function buildLibrary (libOptions, libName, target, libFiles)
+{
+ var lldFullLibraryPath = "./lib/c66/" + libName;
+ var lldFullBuildPath = "./build/c66/" + libName;
+ var lldFullLibraryPathMake = "$(LIBDIR)/" + "c66/" + libName;
+
+ /* Create Main make file in the root of package folder */
+ makefilelocal = createMake(makefilelocal);
+
+ /* Write the rule to make library in main makefile */
+ lib = lldFullBuildPath+".a"+target.suffix;
+ libMake = lldFullLibraryPathMake+".a"+target.suffix;
+ var objectPath= "./package/"+lldFullBuildPath;
+ makefilelocal.writeLine("\n\n# Make rule to create "+libMake+" library");
+ makefilelocal.writeLine(".libraries: "+ libMake);
+ makefilelocal.writeLine(libMake+": FORCE\n\t$(MAKE) -f "+lib+".mk $@");
+
+ /* Create Library make file in the lib folder */
+ var makefilelib= createLibMake(lib+".mk",target,objectPath);
+
+ /* Rule to clean library in main makefile */
+ makefilelocal.writeLine("# Rule to clean "+libMake+" library");
+ makefilelocal.writeLine("clean ::\n\t$(RM) "+ libMake);
+ librule="\n\n"+libMake+" :";
+
+ /* Add files to be compiled */
+ /* Separate out the C and assembly files */
+ var cfiles= new Array();
+ var afiles= new Array();
+ var safiles= new Array();
+ for each(var srcFile in libFiles)
+ {
+ var srcFile=String(srcFile);
+ var dot = srcFile.lastIndexOf(".");
+ var extension = srcFile.substr(dot,srcFile.length);
+ if(extension == ".c")
+ {
+ cfiles.push(srcFile);
+ }
+ else if(extension == ".sa")
+ {
+ safiles.push(srcFile);
+ }
+ else if(extension == ".asm")
+ {
+ afiles.push(srcFile);
+ }
+ else
+ {
+ print("ERROR: Unsupported file extension");
+ java.lang.System.exit(1);
+ }
+ }
+ if(cfiles.length > 0)
+ {
+ makeAddObjects("COMMONSRC",makefilelib,cfiles,libOptions,"c",target);
+ librule += " $(COMMONSRCCOBJS)";
+ }
+ if(afiles.length > 0)
+ {
+ makeAddObjects("COMMONSRC",makefilelib,afiles,libOptions,"asm",target);
+ librule += " $(COMMONSRCASMOBJS)";
+ }
+ if(safiles.length > 0)
+ {
+ makeAddObjects("COMMONSRC",makefilelib,safiles,libOptions,"sa",target);
+ librule += " $(COMMONSRCSAOBJS)";
+ }
+
+ makefilelib.writeLine(librule);
+ makefilelib.writeLine("\t@echo archiving $? into $@ ...");
+ makefilelib.writeLine("\tif [ ! -d $(LIBDIR)/c66 ]; then $(MKDIR) $(LIBDIR)/c66 ; fi;");
+ makefilelib.writeLine("\t$(ARIN) $@ $?");
+ makefilelib.close();
+
+ /* Create the Epilogue; which executes after all the builds are completed.
+ * This is used to generate the benchmark information for the built library.
+ * Also add the benchmarking information file to the package. */
+
+ /* Put the temp file in object directory since javascript doesn't have a built in tmpname,
+ * and don't want --jobs=# with # > 1 to result in collisions */
+ var libFullName = lldFullLibraryPath + ".a" + target.suffix;
+ var tempFile = libFullName + ".xml";
+ Pkg.makeEpilogue += ".libraries: " + libFullName + "_size.txt\n";
+ Pkg.makeEpilogue += libFullName + "_size.txt: " + libFullName + "\n";
+ Pkg.makeEpilogue += "\n\t $(C6X_GEN_INSTALL_PATH)/bin/ofd6x -x " + libFullName + " > " + tempFile;
+ Pkg.makeEpilogue += "\n\t $(SECTTI) " + tempFile + " > " + libFullName + "_size.txt";
+ Pkg.makeEpilogue += "\n\t $(RM) " + tempFile + "\n\n";
+ Pkg.otherFiles[Pkg.otherFiles.length++] = lldFullLibraryPath + ".a" + target.suffix + "_size.txt";
+ Pkg.otherFiles[Pkg.otherFiles.length++] = lldFullBuildPath + ".a" + target.suffix + ".mk";
+ Pkg.otherFiles[Pkg.otherFiles.length++] = lldFullLibraryPath + ".a" + target.suffix;
+
+ /* We need to clean after ourselves; extend the 'clean' target to take care of this. */
+ Pkg.makeEpilogue += "clean::\n";
+ Pkg.makeEpilogue += "\t$(RM) " + lldFullBuildPath + ".a" + target.suffix + "_size.txt\n";
+ Pkg.makeEpilogue += "\t$(RMDIR) " + "$(LIBDIR)/" + "c66/ \n\n";
+
+ return lib;
+}
+
+/**************************************************************************
+ * FUNCTION NAME : createMiniPkg
+ **************************************************************************
+ * DESCRIPTION :
+ * The function is responsible for creating the mini tar package
+ * The MINI package has the following files:-
+ * - Driver Source Files.
+ * - Header files (exported and internal driver files)
+ * - Simple Makefiles.
+ **************************************************************************/
+function createMiniPkg(pkgName)
+{
+ /* Get the package Name. */
+ var packageRepository = xdc.getPackageRepository(Pkg.name);
+ var packageBase = xdc.getPackageBase(Pkg.name);
+ var packageName = packageBase.substring(packageRepository.length + 1);
+
+ /* Convert the Package name by replacing back slashes with forward slashes. This is required because
+ * otherwise with long names the tar is unable to change directory. */
+ var newPkgName = new java.lang.String(packageRepository);
+ var newPkgRep = newPkgName.replace('\\', '/');
+
+ /* Step1: Create the MINI Package and add the simple Big and Little Endian Makefiles to the package */
+ Pkg.makeEpilogue += "release: mini_pkg\n";
+ Pkg.makeEpilogue += "mini_pkg:\n";
+ Pkg.makeEpilogue += "\t tar -C " + "\"" + newPkgRep + "\"" + " -cf packages/" + pkgName + "_mini.tar " +
+ packageName + "simpleC66LE.mak " + "\n";
+
+
+ /* Step2: Add the exported header files to the package */
+ var includeFiles = libUtility.listAllFiles (".h", ".", false);
+ for (var k = 0 ; k < includeFiles.length; k++)
+ Pkg.makeEpilogue += "\t tar -C " + "\"" + newPkgRep + "\"" + " -rf packages/" + pkgName + "_mini.tar " +
+ packageName + includeFiles[k] + "\n";
+
+ /* Step3: Add the internal header files to the package */
+ includeFiles = libUtility.listAllFiles (".h", "include", true);
+ for (var k = 0 ; k < includeFiles.length; k++)
+ Pkg.makeEpilogue += "\t tar -C " + "\"" + newPkgRep + "\"" + " -rf packages/" + pkgName + "_mini.tar " +
+ packageName + includeFiles[k] + "\n";
+
+ /* Step4: Add the PDSP firmware files to the package */
+ includeFiles = libUtility.listAllFiles (".h", "firmware", true);
+ for (var k = 0 ; k < includeFiles.length; k++)
+ Pkg.makeEpilogue += "\t tar -C " + "\"" + newPkgRep + "\"" + " -rf packages/" + pkgName + "_mini.tar " +
+ packageName + includeFiles[k] + "\n";
+
+ /* Step5: Add the device specific files to the package */
+ includeFiles = libUtility.listAllFiles (".c", "device", true);
+ for (var k = 0 ; k < includeFiles.length; k++)
+ Pkg.makeEpilogue += "\t tar -C " + "\"" + newPkgRep + "\"" + " -rf packages/" + pkgName + "_mini.tar " +
+ packageName + includeFiles[k] + "\n";
+
+ /* Step4: Add the driver source files to the package; the filter should have generated a source listing */
+ Pkg.makeEpilogue += "\t tar -C " + "\"" + newPkgRep + "\"" + " -T src.lst -rf packages/" + pkgName + "_mini.tar " + "\n";
+
+ /* Ensure that we clean up the mini package */
+ Pkg.makeEpilogue += "clean::\n";
+ Pkg.makeEpilogue += "\t $(RM) packages/" + pkgName + "_mini.tar\n";
+}
+
+
diff --git a/packages/ti/drv/dfe/build/c66/ti.drv.dfe.ae66.mk b/packages/ti/drv/dfe/build/c66/ti.drv.dfe.ae66.mk
--- /dev/null
@@ -0,0 +1,144 @@
+#*******************************************************************************
+#* FILE PURPOSE: Lower level makefile for Creating Component Libraries
+#*******************************************************************************
+#* FILE NAME: ./build/c66/ti.drv.dfe.ae66.mk
+#*
+#* DESCRIPTION: Defines Source Files, Compilers flags and build rules
+#*
+#*
+#*******************************************************************************
+#
+
+#
+# Macro definitions referenced below
+#
+empty =
+space =$(empty) $(empty)
+CC = $(C6X_GEN_INSTALL_PATH)/bin/cl6x -c -mo -g -mn -o1 -ms2 -k -eo.o --verbose_diagnostics --display_error_number --diag_error=225 --diag_error=9 --diag_warning=179 --diag_remark=880 --diag_remark=188 --mem_model:data=far -mv6600 --abi=eabi
+AC = $(C6X_GEN_INSTALL_PATH)/bin/cl6x -c -qq -mv6600 --abi=eabi
+ARIN = $(C6X_GEN_INSTALL_PATH)/bin/ar6x rq
+LD = $(C6X_GEN_INSTALL_PATH)/bin/lnk6x --abi=eabi
+RTSLIB = -l $(C6X_GEN_INSTALL_PATH)/lib/undefined
+INCS = -I. -I$(strip $(subst ;, -I,$(subst $(space),\$(space),$(INCDIR))))
+OBJEXT = oe66
+AOBJEXT = se66
+INTERNALDEFS = -Dti_targets_elf_C66 -DMAKEFILE_BUILD -eo.$(OBJEXT) -ea.$(AOBJEXT) -fr=$(@D) -fs=$(@D) -ppa -ppd=$@.dep
+INTERNALLINKDEFS = -o $@ -m $@.map
+OBJDIR = $(LIBDIR)/obj
+
+#List the COMMONSRC Files
+COMMONSRCC= \
+ src/dfefl/dfe_fl_Close.c\
+ src/dfefl/dfe_fl_Init.c\
+ src/dfefl/dfe_fl_Open.c\
+ src/dfefl/dfe_fl_autocpClose.c\
+ src/dfefl/dfe_fl_autocppGetHwStatus.c\
+ src/dfefl/dfe_fl_autocppHwControl.c\
+ src/dfefl/dfe_fl_autocppOpen.c\
+ src/dfefl/dfe_fl_bbClose.c\
+ src/dfefl/dfe_fl_bbGetHwStatus.c\
+ src/dfefl/dfe_fl_bbHwControl.c\
+ src/dfefl/dfe_fl_bbOpen.c\
+ src/dfefl/dfe_fl_cbClose.c\
+ src/dfefl/dfe_fl_cbGetHwStatus.c\
+ src/dfefl/dfe_fl_cbHwControl.c\
+ src/dfefl/dfe_fl_cbOpen.c\
+ src/dfefl/dfe_fl_cdfrClose.c\
+ src/dfefl/dfe_fl_cdfrGetHwStatus.c\
+ src/dfefl/dfe_fl_cdfrHwControl.c\
+ src/dfefl/dfe_fl_cdfrOpen.c\
+ src/dfefl/dfe_fl_cfrClose.c\
+ src/dfefl/dfe_fl_cfrGetHwStatus.c\
+ src/dfefl/dfe_fl_cfrHwControl.c\
+ src/dfefl/dfe_fl_cfrOpen.c\
+ src/dfefl/dfe_fl_cppDescripClose.c\
+ src/dfefl/dfe_fl_cppDescripControl.c\
+ src/dfefl/dfe_fl_cppDescripOpen.c\
+ src/dfefl/dfe_fl_cppDescripStatus.c\
+ src/dfefl/dfe_fl_cppDmaClose.c\
+ src/dfefl/dfe_fl_cppDmaControl.c\
+ src/dfefl/dfe_fl_cppDmaOpen.c\
+ src/dfefl/dfe_fl_cppDmaStatus.c\
+ src/dfefl/dfe_fl_dducClose.c\
+ src/dfefl/dfe_fl_dducGetHwStatus.c\
+ src/dfefl/dfe_fl_dducHwControl.c\
+ src/dfefl/dfe_fl_dducOpen.c\
+ src/dfefl/dfe_fl_dpdClose.c\
+ src/dfefl/dfe_fl_dpdGetHwStatus.c\
+ src/dfefl/dfe_fl_dpdHwControl.c\
+ src/dfefl/dfe_fl_dpdOpen.c\
+ src/dfefl/dfe_fl_dpdaClose.c\
+ src/dfefl/dfe_fl_dpdaGetHwStatus.c\
+ src/dfefl/dfe_fl_dpdaHwControl.c\
+ src/dfefl/dfe_fl_dpdaOpen.c\
+ src/dfefl/dfe_fl_fbClose.c\
+ src/dfefl/dfe_fl_fbGetHwStatus.c\
+ src/dfefl/dfe_fl_fbHwControl.c\
+ src/dfefl/dfe_fl_fbOpen.c\
+ src/dfefl/dfe_fl_jesdClose.c\
+ src/dfefl/dfe_fl_jesdGetHwStatus.c\
+ src/dfefl/dfe_fl_jesdHwControl.c\
+ src/dfefl/dfe_fl_jesdOpen.c\
+ src/dfefl/dfe_fl_miscClose.c\
+ src/dfefl/dfe_fl_miscGetHwStatus.c\
+ src/dfefl/dfe_fl_miscHwControl.c\
+ src/dfefl/dfe_fl_miscOpen.c\
+ src/dfefl/dfe_fl_rxClose.c\
+ src/dfefl/dfe_fl_rxGetHwStatus.c\
+ src/dfefl/dfe_fl_rxHwControl.c\
+ src/dfefl/dfe_fl_rxOpen.c\
+ src/dfefl/dfe_fl_summerClose.c\
+ src/dfefl/dfe_fl_summerGetHwStatus.c\
+ src/dfefl/dfe_fl_summerHwControl.c\
+ src/dfefl/dfe_fl_summerOpen.c\
+ src/dfefl/dfe_fl_txClose.c\
+ src/dfefl/dfe_fl_txGetHwStatus.c\
+ src/dfefl/dfe_fl_txHwControl.c\
+ src/dfefl/dfe_fl_txOpen.c\
+ src/dfelld/DFE_bb.c\
+ src/dfelld/DFE_cb.c\
+ src/dfelld/DFE_cfr.c\
+ src/dfelld/DFE_dduc.c\
+ src/dfelld/DFE_dpd.c\
+ src/dfelld/DFE_dpda.c\
+ src/dfelld/DFE_device.c\
+ src/dfelld/DFE_excep.c\
+ src/dfelld/DFE_fb.c\
+ src/dfelld/DFE_jesd.c\
+ src/dfelld/DFE_misc.c\
+ src/dfelld/DFE_open.c\
+ src/dfelld/DFE_rx.c\
+ src/dfelld/DFE_summer.c\
+ src/dfelld/DFE_sync.c\
+ src/dfelld/DFE_tx.c
+
+# FLAGS for the COMMONSRC Files
+COMMONSRCCFLAGS = -DDEVICE_K2L
+
+# Make Rule for the COMMONSRC Files
+COMMONSRCCOBJS = $(patsubst %.c, $(OBJDIR)/%.$(OBJEXT), $(COMMONSRCC))
+
+$(COMMONSRCCOBJS): $(OBJDIR)/%.$(OBJEXT): %.c
+ -@echo cle66 $< ...
+ if [ ! -d $(@D) ]; then $(MKDIR) $(@D) ; fi;
+ $(RM) $@.dep
+ $(CC) $(COMMONSRCCFLAGS) $(INTERNALDEFS) $(INCS) -fc $<
+ -@$(CP) $@.dep $@.pp; \
+ $(SED) -e 's/#.*//' -e 's/^[^:]*: *//' -e 's/ *\\$$//' \
+ -e '/^$$/ d' -e 's/$$/ :/' < $@.pp >> $@.dep; \
+ $(RM) $@.pp
+
+#Create Empty rule for dependency
+$(COMMONSRCCOBJS):./build/c66/ti.drv.dfe.ae66.mk
+./build/c66/ti.drv.dfe.ae66.mk:
+
+#Include Depedency for COMMONSRC Files
+ifneq (clean,$(MAKECMDGOALS))
+ -include $(COMMONSRCCOBJS:%.$(OBJEXT)=%.$(OBJEXT).dep)
+endif
+
+
+$(LIBDIR)/c66/ti.drv.dfe.ae66 : $(COMMONSRCCOBJS)
+ @echo archiving $? into $@ ...
+ if [ ! -d $(LIBDIR)/c66 ]; then $(MKDIR) $(LIBDIR)/c66 ; fi;
+ $(ARIN) $@ $?
diff --git a/packages/ti/drv/dfe/build/c66/ti.drv.dfe.ae66e.mk b/packages/ti/drv/dfe/build/c66/ti.drv.dfe.ae66e.mk
--- /dev/null
@@ -0,0 +1,144 @@
+#*******************************************************************************
+#* FILE PURPOSE: Lower level makefile for Creating Component Libraries
+#*******************************************************************************
+#* FILE NAME: ./build/c66/ti.drv.dfe.ae66e.mk
+#*
+#* DESCRIPTION: Defines Source Files, Compilers flags and build rules
+#*
+#*
+#*******************************************************************************
+#
+
+#
+# Macro definitions referenced below
+#
+empty =
+space =$(empty) $(empty)
+CC = $(C6X_GEN_INSTALL_PATH)/bin/cl6x -c -mo -g -mn -o1 -ms2 -eo.o -DBIGENDIAN --verbose_diagnostics --display_error_number --diag_error=225 --diag_error=9 --diag_warning=179 --diag_remark=880 --diag_remark=188 --mem_model:data=far -me -mv6600 --abi=eabi
+AC = $(C6X_GEN_INSTALL_PATH)/bin/cl6x -c -qq -me -mv6600 --abi=eabi
+ARIN = $(C6X_GEN_INSTALL_PATH)/bin/ar6x rq
+LD = $(C6X_GEN_INSTALL_PATH)/bin/lnk6x --abi=eabi
+RTSLIB = -l $(C6X_GEN_INSTALL_PATH)/lib/undefined
+INCS = -I. -I$(strip $(subst ;, -I,$(subst $(space),\$(space),$(INCDIR))))
+OBJEXT = oe66e
+AOBJEXT = se66e
+INTERNALDEFS = -Dti_targets_elf_C66_big_endian -DMAKEFILE_BUILD -eo.$(OBJEXT) -ea.$(AOBJEXT) -fr=$(@D) -fs=$(@D) -ppa -ppd=$@.dep
+INTERNALLINKDEFS = -o $@ -m $@.map
+OBJDIR = $(LIBDIR)/obj
+
+#List the COMMONSRC Files
+COMMONSRCC= \
+ src/dfefl/dfe_fl_Close.c\
+ src/dfefl/dfe_fl_Init.c\
+ src/dfefl/dfe_fl_Open.c\
+ src/dfefl/dfe_fl_autocpClose.c\
+ src/dfefl/dfe_fl_autocppGetHwStatus.c\
+ src/dfefl/dfe_fl_autocppHwControl.c\
+ src/dfefl/dfe_fl_autocppOpen.c\
+ src/dfefl/dfe_fl_bbClose.c\
+ src/dfefl/dfe_fl_bbGetHwStatus.c\
+ src/dfefl/dfe_fl_bbHwControl.c\
+ src/dfefl/dfe_fl_bbOpen.c\
+ src/dfefl/dfe_fl_cbClose.c\
+ src/dfefl/dfe_fl_cbGetHwStatus.c\
+ src/dfefl/dfe_fl_cbHwControl.c\
+ src/dfefl/dfe_fl_cbOpen.c\
+ src/dfefl/dfe_fl_cdfrClose.c\
+ src/dfefl/dfe_fl_cdfrGetHwStatus.c\
+ src/dfefl/dfe_fl_cdfrHwControl.c\
+ src/dfefl/dfe_fl_cdfrOpen.c\
+ src/dfefl/dfe_fl_cfrClose.c\
+ src/dfefl/dfe_fl_cfrGetHwStatus.c\
+ src/dfefl/dfe_fl_cfrHwControl.c\
+ src/dfefl/dfe_fl_cfrOpen.c\
+ src/dfefl/dfe_fl_cppDescripClose.c\
+ src/dfefl/dfe_fl_cppDescripControl.c\
+ src/dfefl/dfe_fl_cppDescripOpen.c\
+ src/dfefl/dfe_fl_cppDescripStatus.c\
+ src/dfefl/dfe_fl_cppDmaClose.c\
+ src/dfefl/dfe_fl_cppDmaControl.c\
+ src/dfefl/dfe_fl_cppDmaOpen.c\
+ src/dfefl/dfe_fl_cppDmaStatus.c\
+ src/dfefl/dfe_fl_dducClose.c\
+ src/dfefl/dfe_fl_dducGetHwStatus.c\
+ src/dfefl/dfe_fl_dducHwControl.c\
+ src/dfefl/dfe_fl_dducOpen.c\
+ src/dfefl/dfe_fl_dpdClose.c\
+ src/dfefl/dfe_fl_dpdGetHwStatus.c\
+ src/dfefl/dfe_fl_dpdHwControl.c\
+ src/dfefl/dfe_fl_dpdOpen.c\
+ src/dfefl/dfe_fl_dpdaClose.c\
+ src/dfefl/dfe_fl_dpdaGetHwStatus.c\
+ src/dfefl/dfe_fl_dpdaHwControl.c\
+ src/dfefl/dfe_fl_dpdaOpen.c\
+ src/dfefl/dfe_fl_fbClose.c\
+ src/dfefl/dfe_fl_fbGetHwStatus.c\
+ src/dfefl/dfe_fl_fbHwControl.c\
+ src/dfefl/dfe_fl_fbOpen.c\
+ src/dfefl/dfe_fl_jesdClose.c\
+ src/dfefl/dfe_fl_jesdGetHwStatus.c\
+ src/dfefl/dfe_fl_jesdHwControl.c\
+ src/dfefl/dfe_fl_jesdOpen.c\
+ src/dfefl/dfe_fl_miscClose.c\
+ src/dfefl/dfe_fl_miscGetHwStatus.c\
+ src/dfefl/dfe_fl_miscHwControl.c\
+ src/dfefl/dfe_fl_miscOpen.c\
+ src/dfefl/dfe_fl_rxClose.c\
+ src/dfefl/dfe_fl_rxGetHwStatus.c\
+ src/dfefl/dfe_fl_rxHwControl.c\
+ src/dfefl/dfe_fl_rxOpen.c\
+ src/dfefl/dfe_fl_summerClose.c\
+ src/dfefl/dfe_fl_summerGetHwStatus.c\
+ src/dfefl/dfe_fl_summerHwControl.c\
+ src/dfefl/dfe_fl_summerOpen.c\
+ src/dfefl/dfe_fl_txClose.c\
+ src/dfefl/dfe_fl_txGetHwStatus.c\
+ src/dfefl/dfe_fl_txHwControl.c\
+ src/dfefl/dfe_fl_txOpen.c\
+ src/dfelld/DFE_bb.c\
+ src/dfelld/DFE_cb.c\
+ src/dfelld/DFE_cfr.c\
+ src/dfelld/DFE_dduc.c\
+ src/dfelld/DFE_dpd.c\
+ src/dfelld/DFE_dpda.c\
+ src/dfelld/DFE_device.c\
+ src/dfelld/DFE_excep.c\
+ src/dfelld/DFE_fb.c\
+ src/dfelld/DFE_jesd.c\
+ src/dfelld/DFE_misc.c\
+ src/dfelld/DFE_open.c\
+ src/dfelld/DFE_rx.c\
+ src/dfelld/DFE_summer.c\
+ src/dfelld/DFE_sync.c\
+ src/dfelld/DFE_tx.c
+
+# FLAGS for the COMMONSRC Files
+COMMONSRCCFLAGS = -DDEVICE_K2L
+
+# Make Rule for the COMMONSRC Files
+COMMONSRCCOBJS = $(patsubst %.c, $(OBJDIR)/%.$(OBJEXT), $(COMMONSRCC))
+
+$(COMMONSRCCOBJS): $(OBJDIR)/%.$(OBJEXT): %.c
+ -@echo cle66e $< ...
+ if [ ! -d $(@D) ]; then $(MKDIR) $(@D) ; fi;
+ $(RM) $@.dep
+ $(CC) $(COMMONSRCCFLAGS) $(INTERNALDEFS) $(INCS) -fc $<
+ -@$(CP) $@.dep $@.pp; \
+ $(SED) -e 's/#.*//' -e 's/^[^:]*: *//' -e 's/ *\\$$//' \
+ -e '/^$$/ d' -e 's/$$/ :/' < $@.pp >> $@.dep; \
+ $(RM) $@.pp
+
+#Create Empty rule for dependency
+$(COMMONSRCCOBJS):./build/c66/ti.drv.dfe.ae66e.mk
+./build/c66/ti.drv.dfe.ae66e.mk:
+
+#Include Depedency for COMMONSRC Files
+ifneq (clean,$(MAKECMDGOALS))
+ -include $(COMMONSRCCOBJS:%.$(OBJEXT)=%.$(OBJEXT).dep)
+endif
+
+
+$(LIBDIR)/c66/ti.drv.dfe.ae66e : $(COMMONSRCCOBJS)
+ @echo archiving $? into $@ ...
+ if [ ! -d $(LIBDIR)/c66 ]; then $(MKDIR) $(LIBDIR)/c66 ; fi;
+ $(ARIN) $@ $?
diff --git a/packages/ti/drv/dfe/config.bld b/packages/ti/drv/dfe/config.bld
--- /dev/null
@@ -0,0 +1,83 @@
+/******************************************************************************
+ * FILE PURPOSE: Build configuration Script for the DFE LLD
+ ******************************************************************************
+ * FILE NAME: config.bld
+ *
+ * DESCRIPTION:
+ * This file contains the build configuration script for DFE LLD
+ * and is responsible for configuration of the paths for the various tools
+ * required to build DFE LLD.
+ *
+ * Copyright (C) 2012-2013, Texas Instruments, Inc.
+ *****************************************************************************/
+
+/* Get the Tools Base directory from the Environment Variable. */
+var toolsBaseDir = java.lang.System.getenv("C6X_GEN_INSTALL_PATH");
+
+/* Get the base directory for the DFE LLD Package */
+var lldPath = new java.io.File(".//").getPath();
+
+var lldInstallType;
+
+/* Read the part number from the environment variable. */
+var lldPartNumber = java.lang.System.getenv("PARTNO");
+
+/* Include Path */
+/* var lldIncludePath = " -i" + lldPath + "/src" + " -i" + lldPath + " -i" + lldPath + "/test";*/
+var lldIncludePath = " ";
+
+/* Configure the DFE LLD Release Version Information */
+/* 3 steps: remove SPACE and TAB, convert to string and split to make array */
+var lldReleaseVersion = (""+Pkg.version.replace(/\s/g, "")).split(',');
+
+/* DFE LLD Coverity Analysis: Check the environment variable to determine if Static
+ * Analysis has to be done on the DFE LLD Code base or not? */
+var lldCoverityAnalysis = java.lang.System.getenv("LLDCOV");
+
+/* C66 ELF compiler configuration for Little Endian Mode. */
+var C66LE = xdc.useModule('ti.targets.elf.C66');
+C66LE.rootDir = toolsBaseDir;
+C66LE.ccOpts.prefix = "-mo -g -mn -o1 -ms2 -k -eo.o --verbose_diagnostics --display_error_number --diag_error=225 --diag_error=9 --diag_warning=179 --diag_remark=880 --diag_remark=188 --mem_model:data=far";
+
+/* Check if we need to run the STATIC Analysis or not? */
+var coverityAnalysis = java.lang.System.getenv("STATIC_ANALYZE");
+
+/* Setup the Coverity Filters to perform Static Analysis. */
+if (coverityAnalysis == "ON") {
+ var coverityInstallPath = java.lang.System.getenv("STATIC_ANALYZE_PATH");
+ var cfgBase = xdc.getPackageBase("tisb.coverity.filters") + "cfg";
+
+ var coverityFilter = [
+ {
+ moduleName: "tisb.coverity.filters.Coverity",
+ params: {
+ cfgDir: cfgBase, // The Coverity configuration file directory
+ rootDir: coverityInstallPath,
+ outDir: xdc.csd() + "cov_out",
+ analyzeLibs: true
+ }
+ },
+ ];
+
+ /* Run the coverity filters on the LE Build only. */
+ C66LE.profiles["release"].filters = coverityFilter;
+}
+
+/* Check if we need to create the Makefiles? */
+var miniBuild = java.lang.System.getenv("MINI_PACKAGE");
+if (miniBuild == "ON")
+{
+ /* Add the filter for simple Makefile generation. */
+
+ var makeC66LEFilter = {
+ moduleName: "build.filter.Make",
+ params: {
+ makefileName: "simpleC66LE.mak",
+ }
+ };
+ C66LE.profiles["release"].filters[C66LE.profiles["release"].filters.length++] = makeC66LEFilter;
+
+}
+
+/* List all the build targets here. */
+Build.targets = [ C66LE ];
diff --git a/packages/ti/drv/dfe/create_dfe_lld_src_code_patch_from_git.sh b/packages/ti/drv/dfe/create_dfe_lld_src_code_patch_from_git.sh
--- /dev/null
@@ -0,0 +1,44 @@
+#!/bin/bash
+
+set -e # Stop on the first error
+#set -x # Echo on
+
+# Use input arg as LLD version to put in patch filename
+LLD_VERSION=$1
+OUTPUT_FILENAME=dfe_pdklinuxdevkit_src_patch_3_01_04_07_ver_${LLD_VERSION}.tar.gz
+
+# Print usage instructions
+if [ "$LLD_VERSION" == "" ]
+then
+ echo "Script to create DFE LLD source code patch from DFE LLD GIT repo which can be un-tarred"
+ echo "in the MCSDK install directory before rebuilding the DFE LLD libraries for ARM and DSP."
+ echo ""
+ echo "Usage: $0 <LLD_version_number_to_use_in_patch_filename>"
+ echo " i.e. $0 01_00_00_08"
+ exit
+else
+ echo "Creating source code patch file with name $OUTPUT_FILENAME"
+fi
+
+# Remove previous temp_patch_dir and create new one
+rm -rf temp_patch_dir
+mkdir -p temp_patch_dir
+
+# Copy PDK directory patched source files
+mkdir -p temp_patch_dir/pdk_keystone2_3_01_04_07/packages/ti/drv/dfe
+cp --parents -t temp_patch_dir/pdk_keystone2_3_01_04_07/packages/ti/drv/dfe build/armv7/*.mk build/c66/*.mk docs/ReleaseNotes_DFE_LLD.pdf src/*/*.c *.h package.xdc
+
+# Copy mcsdk_linux directory patched source files
+mkdir -p temp_patch_dir/mcsdk_linux_3_01_04_07/linux-devkit/sysroots/cortexa15t2hf-vfp-neon-linux-gnueabi/usr/include/ti/drv/dfe
+cp --parents -t temp_patch_dir/mcsdk_linux_3_01_04_07/linux-devkit/sysroots/cortexa15t2hf-vfp-neon-linux-gnueabi/usr/include/ti/drv/dfe *.h
+
+# Copy script that will be used later to rebuild the LLD from the MCSDK and create the full patch file including libraries
+cp --parents -t temp_patch_dir rebuild_dfe_lld_from_mcsdk_and_create_full_patch.sh
+
+# Create tar.gz file with all patched source files
+cd temp_patch_dir
+tar czf $OUTPUT_FILENAME *
+cd ..
+mv temp_patch_dir/$OUTPUT_FILENAME .
+rm -rf temp_patch_dir
+
diff --git a/packages/ti/drv/dfe/device/Module.xs b/packages/ti/drv/dfe/device/Module.xs
--- /dev/null
@@ -0,0 +1,28 @@
+/******************************************************************************
+ * FILE PURPOSE: IQN2 LLD device specific files.
+ ******************************************************************************
+ * FILE NAME: Module.xs
+ *
+ * DESCRIPTION:
+ * This file contains the module specification for IQN2 LLD device specific files.
+ *
+ * Copyright (C) 2012-2013, Texas Instruments, Inc.
+ *****************************************************************************/
+
+/* Load the library utility. */
+var libUtility = xdc.loadCapsule ("../build/buildlib.xs");
+
+/**************************************************************************
+ * FUNCTION NAME : modBuild
+ **************************************************************************
+ * DESCRIPTION :
+ * The function is used to add all the source files in the device
+ * directory into the package.
+ **************************************************************************/
+function modBuild()
+{
+ /* Add all the .c files to the release package. */
+ var configFiles = libUtility.listAllFiles (".c", "device", true);
+ for (var k = 0 ; k < configFiles.length; k++)
+ Pkg.otherFiles[Pkg.otherFiles.length++] = configFiles[k];
+}
diff --git a/packages/ti/drv/dfe/device/k2l/src/device_dfe.c b/packages/ti/drv/dfe/device/k2l/src/device_dfe.c
--- /dev/null
@@ -0,0 +1,97 @@
+/**
+ * @file device_dfe.c
+ *
+ * @brief
+ * The DFE Device specific code. The DFE LLD calls out
+ * this code to initialize the DFE IP block. The file is provided as
+ * a sample configuration and should be modified by customers for
+ * their own platforms and configurations.
+ *
+ * \par
+ * NOTE:
+ * (C) Copyright 2012-2013 Texas Instruments, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * \par
+ */
+
+/* DFE LLD Includes. */
+#include <ti/drv/dfe/dfe_types.h>
+#include <ti/drv/dfe/dfe_drv.h>
+
+/* CSL DFE Functional Layer */
+#include <ti/csl/csl_dfe.h>
+
+/**********************************************************************
+ ************************* LOCAL Definitions **************************
+ **********************************************************************/
+
+
+/**********************************************************************
+ ************************* Extern Definitions *************************
+ **********************************************************************/
+
+
+/**********************************************************************
+ *********************** DEVICE DFE FUNCTIONS ***********************
+ **********************************************************************/
+
+/** @addtogroup DFE_DEVICE_API
+ @{ */
+
+/**
+ * @b Description
+ * @n
+ * The function provides the initialization sequence for the DFE IP
+ * block. This can be modified by customers for their application and
+ * configuration.
+ *
+ * @retval
+ * Success - 0
+ * @retval
+ * Error - <0
+ */
+#pragma CODE_SECTION(Iqn2Device_init, ".text:Iqn2Device_init");
+int32_t Iqn2Device_init (void)
+{
+ CSL_Iqn2Handle hIqn2;
+
+ /* Get the CSL DFE Handle. */
+ hIqn2 = CSL_dfeOpen (0);
+ if (hIqn2 == NULL)
+ return -1;
+
+ /* Initialization has been completed. */
+ return 0;
+}
+
+/**
+@}
+*/
diff --git a/packages/ti/drv/dfe/dfe.h b/packages/ti/drv/dfe/dfe.h
--- /dev/null
@@ -0,0 +1,40 @@
+/********************************************************************
+ * Copyright (C) 2013 Texas Instruments Incorporated.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+#ifndef DFE_H_
+#define DFE_H_
+
+#include <ti/csl/csl.h>
+#include <ti/drv/dfe/dfe_drv.h>
+#include <ti/drv/dfe/dfe_fl.h>
+
+#endif /* DFE_H_*/
diff --git a/packages/ti/drv/dfe/dfe_drv.h b/packages/ti/drv/dfe/dfe_drv.h
--- /dev/null
@@ -0,0 +1,1943 @@
+/********************************************************************
+ * Copyright (C) 2015 Texas Instruments Incorporated.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+#ifndef __DFE_DRV_H__
+#define __DFE_DRV_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include <stdint.h>
+#include <ti/drv/dfe/dfe_fl.h>
+#include <ti/drv/dfe/dfe_fl_bb.h>
+#include <ti/drv/dfe/dfe_fl_dduc.h>
+#include <ti/drv/dfe/dfe_fl_summer.h>
+#include <ti/drv/dfe/dfe_fl_autocp.h>
+#include <ti/drv/dfe/dfe_fl_cfr.h>
+#include <ti/drv/dfe/dfe_fl_cdfr.h>
+#include <ti/drv/dfe/dfe_fl_dpd.h>
+#include <ti/drv/dfe/dfe_fl_dpda.h>
+#include <ti/drv/dfe/dfe_fl_tx.h>
+#include <ti/drv/dfe/dfe_fl_jesd.h>
+#include <ti/drv/dfe/dfe_fl_rx.h>
+#include <ti/drv/dfe/dfe_fl_fb.h>
+#include <ti/drv/dfe/dfe_fl_cb.h>
+#include <ti/drv/dfe/dfe_fl_misc.h>
+#include <ti/drv/dfe/dfe_fl_cpp.h>
+
+/**
+ * @defgroup DFE_LLD_API DFE LLD
+ */
+/**
+ * @defgroup DFE_LLD_DATASTRUCT DFE LLD Data Structures
+ * @ingroup DFE_LLD_API
+ */
+
+/**
+ * @defgroup DFE_LLD_SYMBOL DFE LLD Symbols Defined
+ * @ingroup DFE_LLD_API
+ */
+
+/**
+ * @defgroup DFE_LLD_FUNCTION DFE LLD Functions
+ * @ingroup DFE_LLD_API
+ *
+ * To properly configure DFE, the following sequence must be followed:
+ *
+ *
+ * | Step | Description | DFE LLD API |
+ * | ---- | -------------------------------------------------- | ---------------- |
+ * | 1 | Program DFE PLL to correct operation rate | |
+ * | 2 | Power up IQN2 and DFE power domains | |
+ * | 3 | Program SERDES to corresponding rate | |
+ * | 4 | Open DFE LLD | Dfe_open() |
+ * | 5 | Load DFE target configuration | Dfe_loadTgtCfg() |
+ * | | Soft Reset DFE peripheral | Dfe_softReset() |
+ * | | Check and wait SERDES PLL_OK | |
+ * | 6 | IQN2 configuration and enable | |
+ * | 7 | Do DFE initialization sequence for transmit path | Dfe_initTgtTx() |
+ * | 8 | Program analogue front-end which connects with DFE | |
+ * | | Check and wait SERDES OK and !LOSS | |
+ * | | Do DFE initialization sequence for receive path | Dfe_initTgtRx() |
+ * | 9 | QMSS, CPPI configuration | |
+ *
+ */
+
+/** @brief DFE error status code
+ * @ingroup DFE_LLD_DATASTRUCT
+ */
+typedef enum
+{
+ /// no error
+ DFE_ERR_NONE = 0,
+ /// mmap fail
+ DFE_ERR_HW_MMAP,
+ /// CSL Hardware control error
+ DFE_ERR_HW_CTRL,
+ /// CSL hardware query error
+ DFE_ERR_HW_QUERY,
+ /// invalid parameters
+ DFE_ERR_INVALID_PARAMS,
+ /// invalid device access
+ DFE_ERR_INVALID_DEVICE,
+ /// device already opened, cannot open again
+ DFE_ERR_ALREADY_OPENED,
+ /// an invalid handle value, such as NULL
+ DFE_ERR_INVALID_HANDLE,
+ /// callback function is NULL
+ DFE_ERR_CALLBACKFXN_IS_NULL,
+ /// waiting condition not met when timed out
+ DFE_ERR_TIMEDOUT,
+ /// sync event not come
+ DFE_ERR_SYNC_NOT_COME,
+ /// SERDES TX not ready
+ DFE_ERR_SERDES_TX_NOT_READY,
+ /// SERDES RX not ready
+ DFE_ERR_SERDES_RX_NOT_READY,
+ /// CPP/DMA channel not valid
+ DFE_ERR_CPP_DMA_NOT_VALID,
+ /// CPP/DMA channel not available
+ DFE_ERR_CPP_DMA_NOT_AVAILABLE,
+ /// CPP/Descriptor not available
+ DFE_ERR_CPP_DESCRIP_NOT_AVAILABLE,
+
+ /// DDUC MIXER NCO can not be updated
+ DFE_ERR_DDUC_MIXER_NCO,
+ /// CFR is busy, the coeffs can not be updated
+ DFE_ERR_CFR_BUSY,
+// // FB pre cb output select is not valid
+// DFE_ERR_FB_PRECB_GAIN,
+ DFE_ERR_END
+} DFE_Err;
+
+/** @brief Generic CPP/DMA Read/Write mode
+ * @ingroup DFE_LLD_DATASTRUCT
+ */
+typedef enum
+{
+ /// Write single 32-bit words to DFE
+ DFE_GENERIC_DMA_RW_MODE_WRITE_SINGLE_WORD = 0,
+ /// Write multiple 32-bits words to DFE
+ DFE_GENERIC_DMA_RW_MODE_WRITE_MULTI_WORDS,
+ /// Read from DFE
+ DFE_GENERIC_DMA_RW_MODE_READ
+} DFE_GenericDmaReadWriteMode;
+
+/** @brief DFE clock speed as configured by the DFE PLL procedure
+ * @ingroup DFE_LLD_DATASTRUCT
+ */
+typedef enum
+{
+ /// Selects the DFE at 245.76 MHz
+ DFE_SPEED_245_76 = 0,
+ /// Selects the DFE at 368.64 MHz
+ DFE_SPEED_368_64,
+ /// Selects the DFE at a custom speed
+ DFE_SPEED_CUSTOM
+} DFE_Speed;
+
+/** @brief (addr, data) register pair
+ * @ingroup DFE_LLD_DATASTRUCT
+ */
+typedef struct
+{
+ /// offset address from DFE base address
+ uint32_t addr;
+ /// data to/from addr
+ uint32_t data;
+} DFE_RegPair;
+
+/** @brief DFE Device information
+ * @ingroup DFE_LLD_DATASTRUCT
+ */
+typedef struct
+{
+ /// DFE peripheral ID
+ uint32_t pid;
+ /// DFE peripheral base address
+ void *baseAddr;
+ /// DFE LLD version
+ uint32_t version;
+} DFE_DevInfo;
+
+/** @brief BBTX power meter configuration
+ * @ingroup DFE_LLD_DATASTRUCT
+ */
+typedef struct
+{
+ /// Enable power meter function
+ DfeFl_BbPowMtrEnable enable;
+ /// Output format of the power meter
+ DfeFl_BbPowMtrOutFormat outFormat;
+ /// DFE carrier type
+ uint32_t countSource;
+ /// Power meter input source
+ DfeFl_BbPowMtrInSource inSource;
+ /// TDD mode
+ DfeFl_BbPowMtrTddMode tddMode;
+ /// Delay from sync expressed in number of samples
+ uint32_t syncDly;
+ /// Meter interval expressed in number of samples
+ uint32_t interval;
+ /// Integration period expressed in number of samples
+ uint32_t intgPd;
+ /// Count of measurements, i.e. count of intervals
+ uint32_t powUptIntvl;
+} DFE_BbtxPowmtrConfig;
+
+/** @brief BBRX power meter configuration
+ * @ingroup DFE_LLD_DATASTRUCT
+ */
+typedef struct
+{
+ /// Enable power meter function
+ DfeFl_BbPowMtrEnable enable;
+ /// Output format of the power meter
+ DfeFl_BbPowMtrOutFormat outFormat;
+ /// DFE carrier type
+ uint32_t countSource;
+ /// Power meter input source
+ DfeFl_BbPowMtrInSource inSource;
+ /// TDD mode
+ DfeFl_BbPowMtrTddMode tddMode;
+ /// Delay from sync expressed in number of samples
+ uint32_t syncDly;
+ /// Meter interval expressed in number of samples
+ uint32_t interval;
+ /// Integration period expressed in number of samples
+ uint32_t intgPd;
+ /// Count of measurements, i.e. count of intervals
+ uint32_t powUptIntvl;
+ /// RX Maximum full scale power in dB for the programmed power interval time.
+ // Used by feed forward power update.
+ // Value is in units of 0.05dB resolution
+ uint32_t maxdB;
+} DFE_BbrxPowmtrConfig;
+
+typedef struct
+{
+ // square clipper threshold
+ uint32_t threshold;
+ // clipper counter threshold (C1)
+ uint32_t cc_thr;
+ // peak threshold (TH0)
+ uint32_t TH0;
+ // peak counter threshold (C0)
+ uint32_t peak_thr;
+ // peakgain counter threshold (C2)
+ uint32_t peakgain_thr;
+} DFE_TxPAprotPeak;
+
+typedef struct
+{
+ // mu_p for IIR
+ uint32_t mu0;
+ // mu_q for IIR
+ uint32_t mu1;
+ // RMS threshold to reduce CFR gain(TH1)
+ uint32_t TH1;
+ // RMS threshold to shut down (TH2)
+ uint32_t TH2;
+ // RMS threshold to peak approaching saturation (TH4)
+ uint32_t TH4;
+ // threshold selection for a1
+ uint32_t th1Sel;
+ // threshold selection for a2
+ uint32_t th2Sel;
+ // threshold selection for a6
+ uint32_t th6Sel;
+} DFE_TxPAprotRms;
+
+typedef struct
+{
+ // maximum magnitude of D3
+ uint32_t mag;
+ // IIR output at D50
+ uint32_t d50;
+ // IIR output at D51
+ uint32_t d51;
+} DFE_TxPAprotPwrStatus;
+
+// Jesd Tx bus to lane map
+typedef struct
+{
+ // bus#, one of DfeFl_JesdTxTxBus (I0, Q0, I1, Q1)
+ uint32_t bus;
+ // slot#, 0 ~ 3
+ uint32_t busPos;
+} DFE_JesdTxLaneMapPos;
+
+// Jesd Tx link status
+typedef struct
+{
+ // first sync request received for the link
+ // 0 \96 not seen first sync request
+ // 1 \96 seen first sync request
+ uint32_t firstSyncRequest[DFE_FL_JESD_NUM_LINK];
+ // error count as reported over SYNC~ interface.
+ uint32_t syncErrCount[DFE_FL_JESD_NUM_LINK];
+ // SYSREF alignment counter bits
+ uint32_t sysrefAlignCount;
+ // captured interrupt bit for sysref_request_assert
+ // 0 \96 sysref request not asserted
+ // 1 \96 sysref request asserted
+ uint32_t sysrefReqAssert;
+ // captured interrupt bit for sysref_request_deassert
+ // 0 \96 sysref request not de-asserted
+ // 1 \96 sysref request de-asserted
+ uint32_t sysrefReqDeassert;
+ // captured interrupt bit for sysref_err on the link
+ // 0 \96 no sysref error
+ // 1 \96 sysref error
+ uint32_t sysrefErr[DFE_FL_JESD_NUM_LINK];
+} DFE_JesdTxLinkStatus;
+
+// Jesd Tx lane status
+typedef struct
+{
+ // synchronization state machine status for lane
+ uint32_t syncState[DFE_FL_JESD_NUM_LANE];
+ // FIFO status
+ // 0 - fifo not empty; 1 - fifo has been empty
+ uint32_t fifoEmpty[DFE_FL_JESD_NUM_LANE];
+ // 0 - no read error; 1 - fifo read error
+ uint32_t fifoReadErr[DFE_FL_JESD_NUM_LANE];
+ // 0 - fifo not full; 1 - fifo has been full
+ uint32_t fifoFull[DFE_FL_JESD_NUM_LANE];
+ // 0 - no write error; 1 - fifo write error
+ uint32_t fifoWriteErr[DFE_FL_JESD_NUM_LANE];
+} DFE_JesdTxLaneStatus;
+
+// Jesd Rx link status
+typedef struct
+{
+ // error count as reported over SYNC~ interface.
+ uint32_t syncErrCount[DFE_FL_JESD_NUM_LINK];
+ // SYSREF alignment counter bits
+ uint32_t sysrefAlignCount;
+ // captured interrupt bit for sysref_request_assert
+ // 0 \96 sysref request not asserted
+ // 1 \96 sysref request asserted
+ uint32_t sysrefReqAssert;
+ // captured interrupt bit for sysref_request_deassert
+ // 0 \96 sysref request not de-asserted
+ // 1 \96 sysref request de-asserted
+ uint32_t sysrefReqDeassert;
+ // captured interrupt bit for sysref_err on the link
+ // 0 \96 no sysref error
+ // 1 \96 sysref error
+ uint32_t sysrefErr[DFE_FL_JESD_NUM_LINK];
+} DFE_JesdRxLinkStatus;
+
+// Jesd Rx lane status
+typedef struct
+{
+ // code group synchronization state machine status for lane
+ uint32_t codeState[DFE_FL_JESD_NUM_LANE];
+ // frame synchronization state machine status for lane
+ uint32_t frameState[DFE_FL_JESD_NUM_LANE];
+ // 0 - no error; 1 - 8B/10B disparity error
+ uint32_t decDispErr[DFE_FL_JESD_NUM_LANE];
+ // 0 - no error; 1 - 8B/10B not-in-table code error
+ uint32_t decCodeErr[DFE_FL_JESD_NUM_LANE];
+ // 0 - no error; 1 - code group sync error
+ uint32_t codeSyncErr[DFE_FL_JESD_NUM_LANE];
+ // 0 - no error; 1 - elastic buffer match error
+ //(first non-/K/ doesn't match match_ctrl and match_data)
+ uint32_t bufMatchErr[DFE_FL_JESD_NUM_LANE];
+ // 0 - no error; 1 - elastic buffer overflow error (bad RBD value)
+ uint32_t bufOverflowErr[DFE_FL_JESD_NUM_LANE];
+ // 0 - no error; 1 - link configuration error
+ uint32_t linkConfigErr[DFE_FL_JESD_NUM_LANE];
+ // 0 - no error; 1 - frame alignment error
+ uint32_t frameAlignErr[DFE_FL_JESD_NUM_LANE];
+ // 0 - no error; 1 - multiframe alignment error
+ uint32_t multiframeAlignErr[DFE_FL_JESD_NUM_LANE];
+ // FIFO status
+ // 0 - normal; 1 - fifo empty
+ uint32_t fifoEmpty[DFE_FL_JESD_NUM_LANE];
+ // 0 - normal; 1 - fifo read error
+ uint32_t fifoReadErr[DFE_FL_JESD_NUM_LANE];
+ // 0 - normal; 1 - fifo full
+ uint32_t fifoFull[DFE_FL_JESD_NUM_LANE];
+ // 0 - normal; 1 - fifo write error
+ uint32_t fifoWriteErr[DFE_FL_JESD_NUM_LANE];
+ // 0 - normal; 1 - test sequence verification failed
+ uint32_t testSeqErr[DFE_FL_JESD_NUM_LANE];
+} DFE_JesdRxLaneStatus;
+
+// Jesd Rx lane to bus map
+typedef struct
+{
+ // Rx lane#, 0 ~ 3
+ uint32_t lane;
+ // lane time slot, 0 ~ 3
+ uint32_t lanePos;
+ // if zero data
+ uint32_t zeroBits;
+} DFE_JesdRxBusMapPos;
+
+// Rx Equalizer Taps
+typedef struct
+{
+ float taps_ii[DFE_FL_RX_EQR_LEN];
+ float taps_iq[DFE_FL_RX_EQR_LEN];
+ float taps_qi[DFE_FL_RX_EQR_LEN];
+ float taps_qq[DFE_FL_RX_EQR_LEN];
+} DFE_RxEqrTaps;
+
+// Fb Equalizer Taps
+typedef struct
+{
+ float taps_ii[DFE_FL_FB_EQR_LEN];
+ float taps_iq[DFE_FL_FB_EQR_LEN];
+ float taps_qi[DFE_FL_FB_EQR_LEN];
+ float taps_qq[DFE_FL_FB_EQR_LEN];
+} DFE_FbEqrTaps;
+
+
+// CB buf configuration
+typedef struct
+{
+ // cb buf mode set
+ DfeFl_CbModeSet cbSet;
+ // cb buf delay from sync
+ uint32_t dly;
+ // 0 = 1s/1c mode; 1 = 2s/1c mode
+ uint32_t rate_mode;
+ // capture buffer A fractional counter length minus 1; range 0-15; value depends on the relative sampling rates for different buffers
+ uint32_t frac_cnt;
+ // fractional counter sync select
+ uint32_t frac_cnt_ssel;
+ // length counter sync select
+ uint32_t len_cnt_ssel;
+ // cb buf length, upto 8192 complex data
+ uint32_t length;
+} DFE_CbBufCfg;
+
+/**
+ * @brief CB data
+ * @ingroup DFE_LLD_DATASTRUCT
+ */
+typedef struct
+{
+ /// I data
+ uint32_t Idata;
+ /// Q data
+ uint32_t Qdata;
+} DFE_CbData;
+
+/**
+ * @brief CPP/DMA resource reserved table
+ * @ingroup DFE_LLD_DATASTRUCT
+ */
+typedef struct _DFE_CppResTbl
+{
+ /// reserved dma bitmask
+ uint32_t dmaRsvd;
+
+ /// discrete trigger out
+ uint32_t discreteTrig[DFE_FL_CPP_NUM_DISCRETE_TRIGGERS];
+
+ /// four 32-bits words, each bit corresponding to one descriptor
+ /// reserved descriptor bitmask
+ uint32_t descripRsvd[4];
+
+} DFE_CppResTbl;
+
+typedef struct _DFE_DpdData
+{
+ /// lutGain
+ DfeFl_DpdComplexInt lutGain;
+ /// lutSlope
+ DfeFl_DpdComplexInt lutSlope;
+} DFE_DpdData;
+
+typedef struct _DFE_DpdCfg
+{
+ /// subchip mode
+ uint32_t subchip_mode;
+ /// subsample
+ uint32_t subsample;
+ /// dpd input scale
+ uint32_t dpdInputScale;
+ /// x2 sqrt
+ uint32_t x2_sqrt;
+} DFE_DpdCfg;
+
+/**
+ * @brief DDUC Exception Status
+ * @ingroup DFE_LLD_DATASTRUCT
+ */
+typedef struct _DFE_EeDducStatus
+{
+ /// Dduc cicov error
+ uint32_t cicovErr;
+ /// Dduc hop rollover error
+ uint32_t hopRolloverErr;
+ /// Dduc hop halfway error
+ uint32_t hopHalfwayErr;
+} DFE_EeDducStatus;
+
+/**
+ * @brief CFR PDC Exception Status
+ * @ingroup DFE_LLD_DATASTRUCT
+ */
+typedef struct _DFE_EeCfrPdcStatus
+{
+ /// a0s0 error interrupt
+ uint32_t a0s0Err;
+ /// a0s1 error interrupt
+ uint32_t a0s1Err;
+ /// a1s0 error interrupt
+ uint32_t a1s0Err;
+ /// a1s1 error interrupt
+ uint32_t a1s1Err;
+} DFE_EeCfrPdcStatus;
+
+/**
+ * @brief CFR Exception Status
+ * @ingroup DFE_LLD_DATASTRUCT
+ */
+typedef struct _DFE_EeCfrStatus
+{
+ /// AxSx error interrupt
+ DFE_EeCfrPdcStatus cfrPdc[2];
+ /// AGC inout interrupt min in threshold antenna x
+ uint32_t cfrAgcMinInThErr[2];
+ /// AGC inout interrupt min out threshold antenna x
+ uint32_t cfrAgcMinOutThErr[2];
+ /// AGC inout interrupt max in threshold antenna x
+ uint32_t cfrAgcMaxInThErr[2];
+ /// AGC inout interrupt max out threshold antenna x
+ uint32_t cfrAgcMaxOutThErr[2];
+ /// AGC syncX error interrupt
+ uint32_t cfrAgcSyncErr[2][2];
+ /// DTH power change error interrupt
+ uint32_t cfrDthPwrCngErr[2];
+ /// DTH sync0 error interrupt
+ uint32_t cfrDthSync0Err[2];
+} DFE_EeCfrStatus;
+
+/**
+ * @brief JESD TX Lane Exception Status
+ * @ingroup DFE_LLD_DATASTRUCT
+ */
+typedef struct _DFE_EeJesdTxlaneStatus
+{
+ /// fifo empty
+ uint32_t fifoEmptyIntr;
+ /// fifo read error because fifo empty
+ uint32_t fifoReadErrIntr;
+ /// fifo full
+ uint32_t fifoFullIntr;
+ /// fifo write error because fifo full
+ uint32_t fifoWriteErrIntr;
+} DFE_EeJesdTxlaneStatus;
+
+/**
+ * @brief JESD RX Lane Exception Status
+ * @ingroup DFE_LLD_DATASTRUCT
+ */
+typedef struct _DFE_EeJesdRxlaneStatus
+{
+ /// captured interrupt bit for 8b/10b disparity error
+ uint32_t decDispErrIntr;
+ /// captured interrupt bit for 8b/10b not-in-table code error
+ uint32_t decCodeErrIntr;
+ /// captured interrupt bit for code synchronization error
+ uint32_t codeSyncErrIntr;
+ /// captured interrupt bit for elastic buffer match error (first non-/K/ doesn't match match_ctrl and match_data)
+ uint32_t bufMatchErrIntr;
+ /// captured interrupt bit for elastic buffer overflow error (bad RBD value)
+ uint32_t bufOverflowErrIntr;
+ /// captured interrupt bit for link configuration error
+ uint32_t linkConfigErrIntr;
+ /// captured interrupt bit for frame alignment error
+ uint32_t frameAlignErrIntr;
+ /// captured interrupt bit for multiframe alignment error
+ uint32_t multiframeAlignErrIntr;
+ /// captured interrupt bit for FIFO empty flag (write 0 to clear)
+ uint32_t fifoEmptyIntr;
+ /// captured interrupt bit for FIFO read error (write 0 to clear)
+ uint32_t fifoReadErrIntr;
+ /// captured interrupt bit for FIFO full flag (write 0 to clear)
+ uint32_t fifoFullIntr;
+ /// captured interrupt bit for FIFO write error (write 0 to clear)
+ uint32_t fifoWriteErrIntr;
+ /// captured interrupt bit for test sequence verification fail
+ uint32_t testSeqErrIntr;
+} DFE_EeJesdRxlaneStatus;
+
+/**
+ * @brief MISC Exception Status
+ * @ingroup DFE_LLD_DATASTRUCT
+ */
+typedef struct _DFE_EeMiscCppIntStatus
+{
+ /// Sync bus captured interrupt bits
+ uint32_t syncSigInt[16];
+ /// CPP DMA captured interrupt bits
+ uint32_t cppDmaDoneInt[32];
+ /// Other misc captured interrupt bit
+ DfeFl_MiscMiscIntrGroup arbGpio;
+} DFE_EeMiscCppIntStatus;
+
+/**
+ * @brief This structure contains all the DFE exception counters.
+ * @ingroup DFE_LLD_DATASTRUCT
+ */
+typedef struct _DFE_EeCountObj {
+ /** Holds counters for dfe BB error interrupts */
+ DfeFl_BbGeneralIntrGroup bbErr;
+ /** Holds counters for dfe Tx power meter error interrupts */
+ uint32_t bbtxpmErr[16];
+ /** Holds counters for dfe Tx gain update error interrupts */
+ uint32_t bbtxgainErr[16];
+ /** Holds counters for dfe Tx power meter error interrupts */
+ uint32_t bbrxpmErr[16];
+ /** Holds counters for dfe Tx gain update error interrupts */
+ uint32_t bbrxgainErr[16];
+ /** Holds counters for dfe DDUC error interrupts */
+ DFE_EeDducStatus dducErr[4];
+ /** Holds counters for dfe CFR error interrupts */
+ DFE_EeCfrStatus cfrErr[2];
+ /** tx X antenna Y power is approaching saturation error interrupt */
+ uint32_t txPaPowerErr[2][2];
+ /** tx X antenna Y peak is approaching saturation error interrupt */
+ uint32_t txPaPeakErr[2][2];
+ /** Holds counters for dfe Jesd Tx SysRef error interrupts */
+ DfeFl_JesdTxSysrefIntrs jesdTxSysref;
+ /** Holds counters for dfe Jesd Rx SysRef error interrupts */
+ DfeFl_JesdRxSysrefIntrs jesdRxSysref;
+ /** Holds counters for dfe Jesd Tx lane error interrupts */
+ DFE_EeJesdTxlaneStatus jesdTxLaneErr[4];
+ /** Holds counters for dfe Jesd Rx lane error interrupts */
+ DFE_EeJesdRxlaneStatus jesdRxLaneErr[4];
+ /** Holds counters for dfe Dpda error interrupts */
+ DfeFl_DpdaIntrStatus dpdaErr;
+ /** Holds counters for dfe Rx Ibpm error interrupts */
+ uint32_t rxIbpmInt[4];
+ /** Holds counters for dfe capture buffer done interrupts */
+ uint32_t cbDoneInterrupt;
+ /** Holds counters for dfe Misc error interrupts */
+ DFE_EeMiscCppIntStatus miscErr;
+ /** Holds counters for dfe Misc error interrupts */
+ DfeFl_MiscMasterHiPriIntrGroup masterHiPrioErr;
+ /** Holds a flag telling whether any of the enabled exceptions occurred, 0 if none, 1 if any */
+ uint32_t eeFlag;
+ /** Holds a flag telling whether any of the enabled information flags occurred, 0 if none, 1 if any */
+ uint32_t infoFlag;
+} DFE_EeCountObj, *DFE_EeCountHandle;
+
+/** @brief DFE device instance context
+ * @ingroup DFE_LLD_DATASTRUCT
+ */
+typedef struct _DFE_Obj
+{
+
+ /// DFE CSL context
+ DfeFl_Context dfeCtx;
+ /// DFE CSL param
+ DfeFl_Param dfeParam;
+ /// DFE clock speed
+ DFE_Speed dfeSpeed;
+ /// DFE custom clock speed in KHz
+ uint32_t dfeCustomSpeed;
+ /// DFE CSL Handle
+ DfeFl_Handle hDfe;
+ /// DFE_BB CSL Handle
+ DfeFl_BbHandle hDfeBb[DFE_FL_BB_PER_CNT];
+ /// DFE_DDUC CSL Handle
+ DfeFl_DducHandle hDfeDduc[DFE_FL_DDUC_PER_CNT];
+ /// DFE_SUMMER CSL Handle
+ DfeFl_SummerHandle hDfeSummer[DFE_FL_SUMMER_PER_CNT];
+ /// DFE_AUTOCP CSL Handle
+ DfeFl_AutocpHandle hDfeAutocp[DFE_FL_AUTOCP_PER_CNT];
+ /// DFE_CFR CSL Handle
+ DfeFl_CfrHandle hDfeCfr[DFE_FL_CFR_PER_CNT];
+ /// DFE_CDFR CSL Handle
+ DfeFl_CdfrHandle hDfeCdfr[DFE_FL_CDFR_PER_CNT];
+ /// DFE_DPD CSL Handle
+ DfeFl_DpdHandle hDfeDpd[DFE_FL_DPD_PER_CNT];
+ /// DFE_DPD disabled flag: 0 on TIC6630K2L devices, 1 on 66AK2L06
+ uint32_t dpdIsDisabled;
+ /// DFE_DPDA CSL Handle
+ DfeFl_DpdaHandle hDfeDpda[DFE_FL_DPDA_PER_CNT];
+ /// DFE_DPDA disabled flag: 0 on TIC6630K2L devices, 1 on 66AK2L06
+ uint32_t dpdaIsDisabled;
+ /// DFE_TX CSL Handle
+ DfeFl_TxHandle hDfeTx[DFE_FL_TX_PER_CNT];
+ /// DFE_RX CSL Handle
+ DfeFl_RxHandle hDfeRx[DFE_FL_RX_PER_CNT];
+ /// DFE_CB CSL Handle
+ DfeFl_CbHandle hDfeCb[DFE_FL_CB_PER_CNT];
+ /// DFE_JESD CSL Handle
+ DfeFl_JesdHandle hDfeJesd[DFE_FL_JESD_PER_CNT];
+ /// DFE_FB CSL Handle
+ DfeFl_FbHandle hDfeFb[DFE_FL_FB_PER_CNT];
+ /// DFE_MISC CSL Handle
+ DfeFl_MiscHandle hDfeMisc[DFE_FL_MISC_PER_CNT];
+ /// DFE_CPP CSL resource manager
+ DfeFl_CppResMgr cppResMgr;
+ /// BBTX power meter for CPP/DMA
+ uint32_t bbtxPowmtr;
+ /// dma handle for BBTX power meter
+ DfeFl_CppDmaHandle hDmaBbtxPowmtr;
+ /// descriptor handle for BBTX power meter
+ DfeFl_CppDescriptorHandle hDescripBbtxPowmtr;
+ /// IQN2 CTL Ingress Channel for BBTX power meter
+ uint32_t bbtxPowmtrIqnChnl;
+ /// BBRX power meter for CPP/DMA
+ uint32_t bbrxPowmtr;
+ /// dma handle for BBRX power meter
+ DfeFl_CppDmaHandle hDmaBbrxPowmtr;
+ /// descriptor handle for BBRX power meter
+ DfeFl_CppDescriptorHandle hDescripBbrxPowmtr;
+ /// descriptor handle for BBTX power meter
+ uint32_t bbrxPowmtrIqnChnl;
+ /// flag to read all 18 bit Cb
+ uint32_t flag_18bit;
+ /// dma handle for cb
+ DfeFl_CppDmaHandle hDmaCb;
+ /// descriptor handle for cb
+ DfeFl_CppDescriptorHandle hDescripCb[8];
+ /// IQN2 CTL Channel
+ uint32_t cbIqnChnl;
+ /// sync counter ssel
+ DfeFl_MiscSyncGenSig sync_cnter_ssel;
+ /// bbtx siggen ssel
+ uint32_t bbtx_siggen_ssel;
+ /// bbrx checksum ssel
+ uint32_t bbrx_chksum_ssel;
+ /// ulStrobe strobe
+ DfeFl_MiscSyncGenSig ulStrobe_Sync;
+ /// RX IBPM Unity Magnitude Sqaure value (=I^2 + Q^2)
+ uint64_t rxIbpmUnityMagsq;
+ /// generic DMA hndle
+ DfeFl_CppDmaHandle hDmaGeneric;
+ /// IQN2 CTL Egress channel for generic writing DMA
+ uint32_t genericDmaIqnChnlDl;
+ /// IQN2 CTL Ingress channel for generic reading DMA
+ uint32_t genericDmaIqnChnlUl;
+ /// Exception counters - updated when exception are enabled
+ DFE_EeCountObj dfeEeCount;
+ /// DFE CSL object
+ DfeFl_Obj objDfe;
+ /// DFE_BB CSL object
+ DfeFl_BbObj objDfeBb[DFE_FL_BB_PER_CNT];
+ /// DFE_DDUC CSL object
+ DfeFl_DducObj objDfeDduc[DFE_FL_DDUC_PER_CNT];
+ /// DFE_SUMMER CSL object
+ DfeFl_SummerObj objDfeSummer[DFE_FL_SUMMER_PER_CNT];
+ /// DFE_AUTOCP CSL object
+ DfeFl_AutocpObj objDfeAutocp[DFE_FL_AUTOCP_PER_CNT];
+ /// DFE_CFR CSL object
+ DfeFl_CfrObj objDfeCfr[DFE_FL_CFR_PER_CNT];
+ /// DFE_CDFR CSL object
+ DfeFl_CdfrObj objDfeCdfr[DFE_FL_CDFR_PER_CNT];
+ /// DFE_DPD CSL object
+ DfeFl_DpdObj objDfeDpd[DFE_FL_DPD_PER_CNT];
+ /// DFE_DPDA CSL object
+ DfeFl_DpdaObj objDfeDpda[DFE_FL_DPDA_PER_CNT];
+ /// DFE_TX CSL object
+ DfeFl_TxObj objDfeTx[DFE_FL_TX_PER_CNT];
+ /// DFE_RX CSL object
+ DfeFl_RxObj objDfeRx[DFE_FL_RX_PER_CNT];
+ /// DFE_CB CSL object
+ DfeFl_CbObj objDfeCb[DFE_FL_CB_PER_CNT];
+ /// DFE_JESD CSL object
+ DfeFl_JesdObj objDfeJesd[DFE_FL_JESD_PER_CNT];
+ /// DFE_FB CSL object
+ DfeFl_FbObj objDfeFb[DFE_FL_FB_PER_CNT];
+ /// DFE_MISC CSL object
+ DfeFl_MiscObj objDfeMisc[DFE_FL_MISC_PER_CNT];
+
+} DFE_Obj;
+typedef DFE_Obj * DFE_Handle;
+
+// callback context
+typedef void * DFE_CallbackContext;
+
+/** @brief Callback function for waiting sync signal
+ * @ingroup DFE_LLD_DATASTRUCT
+ *
+ * return DFE_ERR_OK if sync signal come properly
+ * return DFE_ERR_SYNC_NO_COME if sync signal not come before timed out
+ */
+typedef DFE_Err (*DFE_CallbackWaitSync)
+(
+ /// callback context
+ DFE_CallbackContext cbkCtx,
+ /// DFE device handle
+ DFE_Handle hDfe,
+ /// sync signal to be waiting
+ DfeFl_MiscSyncGenSig syncSig
+);
+
+// Open DFE LLD device.
+DFE_Handle Dfe_open
+(
+ int dfeInst,
+ DFE_Obj *dfeObj,
+ DFE_CppResTbl *dfeResTbl,
+ uint32_t baseAddress,
+ DFE_Err *err
+);
+
+// Close DFE LLD device opened by Dfe_open().
+DFE_Err Dfe_close
+(
+ DFE_Handle hDfe
+);
+
+// Load DFE target configuration, i.e. registers contents.
+DFE_Err Dfe_loadTgtCfg
+(
+ DFE_Handle hDfe,
+ DFE_RegPair tgtCfgPairs[]
+);
+
+// Do soft reset
+DFE_Err Dfe_softReset
+(
+ DFE_Handle hDfe
+);
+
+// DFE initialization sequence for tx path, BB => DDUC => CFR => DPD => TX => JESDTX
+DFE_Err Dfe_initTgtTx
+(
+ DFE_Handle hDfe,
+ DFE_CallbackContext waitSyncCtx,
+ DFE_CallbackWaitSync waitSyncFxn
+);
+
+// DFE initialization sequence for tx path, BB <= DDUC <= RX/FB <= JESDRX
+DFE_Err Dfe_initTgtRx
+(
+ DFE_Handle hDfe,
+ DFE_CallbackContext waitSyncCtx,
+ DFE_CallbackWaitSync waitSyncFxn
+);
+
+// Get back DFE device information, such as PID, base address etc.
+DFE_Err Dfe_getDevInfo
+(
+ DFE_Handle hDfe,
+ DFE_DevInfo *devInfo
+);
+
+// Issue a sync signal.
+DFE_Err Dfe_issueSync
+(
+ DFE_Handle hDfe,
+ DfeFl_MiscSyncGenSig syncSig,
+ uint32_t waitCnt
+);
+
+// Get a sync signal status.
+DFE_Err Dfe_getSyncStatus
+(
+ DFE_Handle hDfe,
+ DfeFl_MiscSyncGenSig syncSig,
+ uint32_t *signaled
+);
+
+// Program a sync counter
+DFE_Err Dfe_progSyncCounter
+(
+ DFE_Handle hDfe,
+ DfeFl_MiscSyncGenCntr cntr,
+ uint32_t delay,
+ uint32_t period,
+ uint32_t pulseWidth,
+ uint32_t repeat,
+ uint32_t invert
+);
+
+// Issue sync to start the sync counter, and return without waiting.
+DFE_Err Dfe_issueSyncStartSyncCounter
+(
+ DFE_Handle hDfe,
+ DfeFl_MiscSyncGenCntr cntr,
+ DfeFl_MiscSyncGenSig ssel
+);
+
+// Program BBTX AxCs\92 gains.
+DFE_Err Dfe_progBbtxGain
+(
+ DFE_Handle hDfe,
+ uint32_t numAxCs,
+ uint32_t axc[],
+ float gain[]
+);
+
+// Issue sync to update BBTX gain
+DFE_Err Dfe_issueSyncUpdateBbtxGain
+(
+ DFE_Handle hDfe,
+ uint32_t ct,
+ DfeFl_MiscSyncGenSig ssel
+);
+
+// Get BBTX gain update complete
+DFE_Err Dfe_getBbtxGainUpdateComplete
+(
+ DFE_Handle hDfe,
+ uint32_t ct,
+ uint32_t *complete
+);
+
+// Clear BBTX gain update complete interrupt status
+DFE_Err Dfe_clearBbtxGainUpdateCompleteIntrStatus
+(
+ DFE_Handle hDfe,
+ uint32_t ct
+);
+
+// Program BBTX power meter
+DFE_Err Dfe_progBbtxPowmtr
+(
+ DFE_Handle hDfe,
+ uint32_t pmId,
+ DFE_BbtxPowmtrConfig *mtrCfg
+);
+
+// Issue sync to update BBTX power meter
+DFE_Err Dfe_issueSyncUpdateBbtxPowmtr
+(
+ DFE_Handle hDfe,
+ uint32_t pmId,
+ DfeFl_MiscSyncGenSig ssel
+);
+
+// Clear BBTX power meter complete interrupt status
+DFE_Err Dfe_clearBbtxPowmtrDoneIntrStatus
+(
+ DFE_Handle hDfe,
+ uint32_t pmId
+);
+
+// Get BBTX power meter complete interrupt status
+DFE_Err Dfe_getBbtxPowmtrDoneIntrStatus
+(
+ DFE_Handle hDfe,
+ uint32_t pmId,
+ uint32_t *complete
+);
+
+// Read BBTX power meter via CPU
+DFE_Err Dfe_readBbtxPowmtr
+(
+ DFE_Handle hDfe,
+ uint32_t pmId,
+ float *peak,
+ float *rms
+);
+
+// Open CPP/DMA for BBTX power meters
+DFE_Err Dfe_openBbtxPowmtrDma
+(
+ DFE_Handle hDfe,
+ uint32_t cppDmaId,
+ uint32_t cppDescripId,
+ uint32_t iqnChnl
+);
+
+// Close CPP/DMA for BBTX power meters
+DFE_Err Dfe_closeBbtxPowmtrDma
+(
+ DFE_Handle hDfe
+);
+
+// Enable CPP/DMA for BBTX power meters
+DFE_Err Dfe_enableBbtxPowmtrDma
+(
+ DFE_Handle hDfe,
+ uint32_t pmId
+);
+
+// disable CPP/DMA for BBTX power meters
+DFE_Err Dfe_disableBbtxPowmtrDma
+(
+ DFE_Handle hDfe
+);
+
+// Program BBRX AxCs\92 gains.
+DFE_Err Dfe_progBbrxGain
+(
+ DFE_Handle hDfe,
+ uint32_t numAxCs,
+ uint32_t axc[],
+ float gain[]
+);
+
+// Issue sync to update BBRX gain
+DFE_Err Dfe_issueSyncUpdateBbrxGain
+(
+ DFE_Handle hDfe,
+ uint32_t ct,
+ DfeFl_MiscSyncGenSig ssel
+);
+
+// Get BBRX gain update complete
+DFE_Err Dfe_getBbrxGainUpdateComplete
+(
+ DFE_Handle hDfe,
+ uint32_t ct,
+ uint32_t *complete
+);
+
+// Clear BBRX gain update complete interrupt status
+DFE_Err Dfe_clearBbrxGainUpdateCompleteIntrStatus
+(
+ DFE_Handle hDfe,
+ uint32_t ct
+);
+
+// Program BBRX power meter
+DFE_Err Dfe_progBbrxPowmtr
+(
+ DFE_Handle hDfe,
+ uint32_t pmId,
+ DFE_BbrxPowmtrConfig *mtrCfg
+);
+
+// Issue sync to update BBRX power meter
+DFE_Err Dfe_issueSyncUpdateBbrxPowmtr
+(
+ DFE_Handle hDfe,
+ uint32_t pmId,
+ DfeFl_MiscSyncGenSig ssel
+);
+
+// Clear BBRX power meter complete interrupt status
+DFE_Err Dfe_clearBbrxPowmtrDoneIntrStatus
+(
+ DFE_Handle hDfe,
+ uint32_t pmId
+);
+
+// Get BBRX power meter complete interrupt status
+DFE_Err Dfe_getBbrxPowmtrDoneIntrStatus
+(
+ DFE_Handle hDfe,
+ uint32_t pmId,
+ uint32_t *complete
+);
+
+// Read BBTX power meter via CPU
+DFE_Err Dfe_readBbrxPowmtr
+(
+ DFE_Handle hDfe,
+ uint32_t pmId,
+ float *peak,
+ float *rms
+);
+
+// Open CPP/DMA for BBRX power meters
+DFE_Err Dfe_openBbrxPowmtrDma
+(
+ DFE_Handle hDfe,
+ uint32_t cppDmaId,
+ uint32_t cppDescripId,
+ uint32_t iqnChnl
+);
+
+// Close CPP/DMA for BBRX power meters
+DFE_Err Dfe_closeBbrxPowmtrDma
+(
+ DFE_Handle hDfe
+);
+
+// Enable CPP/DMA for BBRX power meters
+DFE_Err Dfe_enableBbrxPowmtrDma
+(
+ DFE_Handle hDfe,
+ uint32_t pmId
+);
+
+// disable CPP/DMA for BBRX power meters
+DFE_Err Dfe_disableBbrxPowmtrDma
+(
+ DFE_Handle hDfe
+);
+
+// enable/disable BB AID loopback
+DFE_Err Dfe_enableDisableBbaidLoopback
+(
+ DFE_Handle hDfe,
+ uint32_t enable
+);
+
+// Program BB Buf Loopback
+DFE_Err Dfe_progBbbufLoopback
+(
+ DFE_Handle hDfe,
+ DfeFl_BbLoopbackConfig *bufLoopback
+);
+
+// Set BB AID UL strobe delay
+DFE_Err Dfe_setBbaidUlstrobeDelay
+(
+ DFE_Handle hDfe,
+ uint32_t ct,
+ uint32_t dly
+);
+
+// Program BB Signal Generator
+DFE_Err Dfe_progBbsigGenRamp
+(
+ DFE_Handle hDfe,
+ DfeFl_BbTestGenDev sigGenDev,
+ uint32_t enable,
+ int16_t startIq[2],
+ int16_t stopIq[2],
+ int16_t slopeIq[2]
+);
+
+// Issue Sync to Update BB SigGen
+DFE_Err Dfe_issueSyncUpdateBbsigGen
+(
+ DFE_Handle hDfe,
+ DfeFl_BbTestGenDev sigGenDev,
+ DfeFl_MiscSyncGenSig ssel
+);
+
+// Program BB testbus
+DFE_Err Dfe_progBbtestbus
+(
+ DFE_Handle hDfe,
+ DfeFl_BbTestCbCtrl testCbCtrl,
+ uint32_t testCbAxc
+);
+
+// Program DDUC Mixer NCO frequency
+DFE_Err Dfe_progDducMixerNCO
+(
+ DFE_Handle hDfe,
+ uint32_t dducDev,
+ float refClock,
+ float freq[12]
+);
+
+// Issue Sync to update DDUC Mixer NCO frequency
+DFE_Err Dfe_issueSyncUpdateDducMixerNCO
+(
+ DFE_Handle hDfe,
+ uint32_t dducDev,
+ DfeFl_MiscSyncGenSig ssel
+);
+
+// Program DDUC Mixer Phase
+DFE_Err Dfe_progDducMixerPhase
+(
+ DFE_Handle hDfe,
+ uint32_t dducDev,
+ float phase[12]
+);
+
+// Issue Sync to update DDUC Mixer phase
+DFE_Err Dfe_issueSyncUpdateDducMixerPhase
+(
+ DFE_Handle hDfe,
+ uint32_t dducDev,
+ DfeFl_MiscSyncGenSig ssel
+);
+
+// Program DDUC Farrow phase
+DFE_Err Dfe_progDducFarrowPhase
+(
+ DFE_Handle hDfe,
+ uint32_t dducDev,
+ uint32_t fifo[12],
+ float phase[12]
+);
+
+// Issue Sync to update DDUC Farrow phase
+DFE_Err Dfe_issueSyncUpdateDducFarrowPhase
+(
+ DFE_Handle hDfe,
+ uint32_t dducDev,
+ DfeFl_MiscSyncGenSig ssel
+);
+
+// Program Distributor Map
+DFE_Err Dfe_progDducDistMap
+(
+ DFE_Handle hDfe,
+ uint32_t dducDev,
+ uint32_t rxSel[12],
+ uint32_t chanSel[12]
+);
+
+// Issue Sync to update Distributor map
+DFE_Err Dfe_issueSyncUpdateDducDistMap
+(
+ DFE_Handle hDfe,
+ uint32_t dducDev,
+ DfeFl_MiscSyncGenSig ssel
+);
+
+// Program Summer shift
+DFE_Err Dfe_progSummerShift
+(
+ DFE_Handle hDfe,
+ uint32_t cfrId,
+ uint32_t strId,
+ int gain
+);
+
+// Program Summer map
+DFE_Err Dfe_progSummerMap
+(
+ DFE_Handle hDfe,
+ uint32_t cfrId,
+ uint32_t strId,
+ uint32_t sumMap[4]
+);
+
+// Issue Sync to update Summer map
+DFE_Err Dfe_issueSyncUpdateSummerMap
+(
+ DFE_Handle hDfe,
+ DfeFl_MiscSyncGenSig ssel
+);
+
+// Program Cfr coefficients
+DFE_Err Dfe_progCfrCoeff
+(
+ DFE_Handle hDfe,
+ uint32_t cfrDev,
+ uint32_t numCoeffs,
+ uint32_t *cfrCoeff_i,
+ uint32_t *cfrCoeff_q
+);
+
+// Issue Sync Update Cfr coefficients
+DFE_Err Dfe_issueSyncUpdateCfrCoeff
+(
+ DFE_Handle hDfe,
+ uint32_t cfrDev,
+ uint32_t coeffType,
+ DfeFl_MiscSyncGenSig ssel
+);
+
+// Program Cfr preGain
+DFE_Err Dfe_progCfrPreGain
+(
+ DFE_Handle hDfe,
+ uint32_t cfrDev,
+ DfeFl_CfrPath cfrPath,
+ float gain
+);
+
+// Issue Sync Update Cfr preGain
+DFE_Err Dfe_issueSyncUpdatCfrPreGain
+(
+ DFE_Handle hDfe,
+ uint32_t cfrDev,
+ DfeFl_CfrPath cfrPath,
+ DfeFl_MiscSyncGenSig ssel
+);
+
+// Program Cfr postGain
+DFE_Err Dfe_progCfrPostGain
+(
+ DFE_Handle hDfe,
+ uint32_t cfrDev,
+ DfeFl_CfrPath cfrPath,
+ float gain
+);
+
+// Issue Sync Update Cfr postGain
+DFE_Err Dfe_issueSyncUpdatCfrPostGain
+(
+ DFE_Handle hDfe,
+ uint32_t cfrDev,
+ DfeFl_CfrPath cfrPath,
+ DfeFl_MiscSyncGenSig ssel
+);
+
+// Program Cfr protection gain
+DFE_Err Dfe_progCfrProtGain
+(
+ DFE_Handle hDfe,
+ uint32_t cfrDev,
+ DfeFl_CfrPath cfrPath,
+ float gain
+);
+
+// Program Tx Mixer
+DFE_Err Dfe_progTxMixer
+(
+ DFE_Handle hDfe,
+ DfeFl_TxPath txPath,
+ float refClock,
+ float freq[2]
+);
+
+// Issue sync to update Tx Mixer
+DFE_Err Dfe_issueSyncUpdateTxMixer
+(
+ DFE_Handle hDfe,
+ DfeFl_TxPath txPath,
+ DfeFl_MiscSyncGenSig ssel
+);
+
+// Program Tx PA protection
+DFE_Err Dfe_progTxPaProtection
+(
+ DFE_Handle hDfe,
+ DfeFl_TxDev txDev,
+ DFE_TxPAprotPeak txPAprotPeak,
+ DFE_TxPAprotRms txPAprotRms,
+ uint32_t mask
+);
+
+// Get Tx PA protection interrupt status
+DFE_Err Dfe_getTxPAprotIntrStatus
+(
+ DFE_Handle hDfe,
+ DfeFl_TxPaIntrpt *txPAprotIntr
+);
+
+// Clear Tx PA protection interrupt status
+DFE_Err Dfe_clearTxPAprotIntrStatus
+(
+ DFE_Handle hDfe,
+ DfeFl_TxDev txDev
+);
+
+// Read Tx PA protection power status
+DFE_Err Dfe_getTxPAprotPwrStatus
+(
+ DFE_Handle hDfe,
+ DfeFl_TxDev txDev,
+ uint32_t clrRead,
+ DFE_TxPAprotPwrStatus *txPAprotPwrStatus
+);
+
+
+// Get JESDTX lane enable status
+DFE_Err Dfe_getJesdTxLaneEnable
+(
+ DFE_Handle hDfe,
+ uint32_t laneEnable[4],
+ uint32_t linkAssign[4]
+);
+
+// Program JESD Tx bus to lane map.
+DFE_Err Dfe_mapJesdTx2Lane
+(
+ DFE_Handle hDfe,
+ uint32_t lane,
+ DFE_JesdTxLaneMapPos laneMap[4]
+);
+
+// Program JESDTX Signal Generator to produce a ramp.
+DFE_Err Dfe_progJesdTxSigGenRamp
+(
+ DFE_Handle hDfe,
+ DfeFl_JesdTxSignalGen sigGenDev,
+ uint32_t enable,
+ int32_t start,
+ int32_t stop,
+ int32_t slope
+);
+// Issue sync update JESDTX Signal Generator.
+DFE_Err Dfe_issueSyncUpdateJesdTxSigGen
+(
+ DFE_Handle hDfe,
+ DfeFl_JesdTxSignalGen sigGenDev,
+ DfeFl_MiscSyncGenSig ssel
+);
+
+// Program JESD Tx testbus
+DFE_Err Dfe_progJesdTxTestbus
+(
+ DFE_Handle hDfe,
+ DfeFl_JesdTxTestBusSel tp
+);
+
+// Get JESD Tx link status
+DFE_Err Dfe_getJesdTxLinkStatus
+(
+ DFE_Handle hDfe,
+ DFE_JesdTxLinkStatus *linkStatus
+);
+
+// Get JESD Tx lane status
+DFE_Err Dfe_getJesdTxLaneStatus
+(
+ DFE_Handle hDfe,
+ DFE_JesdTxLaneStatus *laneStatus
+);
+
+// Clear JESD Tx link error
+DFE_Err Dfe_clearJesdTxLinkErrors
+(
+ DFE_Handle hDfe
+);
+
+// Clear JESD Tx lane error
+DFE_Err Dfe_clearJesdTxLaneErrors
+(
+ DFE_Handle hDfe
+);
+
+// Get JESD RX lane enable status
+DFE_Err Dfe_getJesdRxLaneEnable
+(
+ DFE_Handle hDfe,
+ uint32_t laneEnable[4],
+ uint32_t linkAssign[4]
+);
+
+// program JESD lane to Rx map
+DFE_Err Dfe_mapJesdLane2Rx
+(
+ DFE_Handle hDfe,
+ uint32_t rxBus,
+ DFE_JesdRxBusMapPos busMap[4]
+);
+
+// Program JESD Rx testbus
+DFE_Err Dfe_progJesdRxTestbus
+(
+ DFE_Handle hDfe,
+ DfeFl_JesdRxTestBusSel tp
+);
+
+// Init JESD tx state machine.
+DFE_Err Dfe_initJesdTx
+(
+ DFE_Handle hDfe
+);
+
+// Init JESD rx state machine.
+DFE_Err Dfe_initJesdRx
+(
+ DFE_Handle hDfe
+);
+
+// Program JESD loopbacks for sync_n, lanes or links.
+DFE_Err Dfe_progJesdLoopback
+(
+ DFE_Handle hDfe,
+ uint32_t lpbkSync[DFE_FL_JESD_NUM_LINK],
+ DfeFl_JesdRxLoopbackConfig *lpbkLaneLink
+);
+
+// Get current JESD loopbacks for sync_n, lanes or links.
+DFE_Err Dfe_getJesdLoopback
+(
+ DFE_Handle hDfe,
+ uint32_t lpbkSync[DFE_FL_JESD_NUM_LINK],
+ DfeFl_JesdRxLoopbackConfig *lpbkLaneLink
+);
+
+// Get JESD Rx link status
+DFE_Err Dfe_getJesdRxLinkStatus
+(
+ DFE_Handle hDfe,
+ DFE_JesdRxLinkStatus *linkStatus
+);
+
+// Get JESD Rx lane status
+DFE_Err Dfe_getJesdRxLaneStatus
+(
+ DFE_Handle hDfe,
+ DFE_JesdRxLaneStatus *laneStatus
+);
+
+// Clear JESD Rx link error
+DFE_Err Dfe_clearJesdRxLinkErrors
+(
+ DFE_Handle hDfe
+);
+
+// Clear JESD Rx lane error
+DFE_Err Dfe_clearJesdRxLaneErrors
+(
+ DFE_Handle hDfe
+);
+
+// Program RX IBPM global
+DFE_Err Dfe_progRxIbpmGlobal
+(
+ DFE_Handle hDfe,
+ DfeFl_RxPowmtrReadMode readMode,
+ float histThresh1,
+ float histThresh2,
+ uint64_t unityMagsq
+);
+
+// Program individual RX IBPM
+DFE_Err Dfe_progRxIbpm
+(
+ DFE_Handle hDfe,
+ uint32_t pmId,
+ uint32_t oneShot,
+ uint32_t meterMode,
+ uint32_t syncDelay,
+ uint32_t nSamples,
+ uint32_t interval
+);
+
+// Issue Sync Update Rx Ibpm
+DFE_Err Dfe_issueSyncUpdateRxIbpm
+(
+ DFE_Handle hDfe,
+ uint32_t pmId,
+ DfeFl_MiscSyncGenSig ssel
+);
+
+// Issue Read Request to Rx Ibpm
+DFE_Err Dfe_issueRxIbpmReadRequest
+(
+ DFE_Handle hDfe,
+ uint32_t pmId
+);
+
+// Get Rx Ibpm read ack
+DFE_Err Dfe_getRxIbpmReadAck
+(
+ DFE_Handle hDfe,
+ uint32_t pmId,
+ uint32_t *ackRead
+);
+
+// Read Rx IBPM result
+DFE_Err Dfe_readRxIbpmResult
+(
+ DFE_Handle hDfe,
+ uint32_t pmId,
+ float *power,
+ float *peak,
+ uint32_t *histCount1,
+ uint32_t *histCount2
+);
+
+// Clear Read Request to Rx Ibpm
+DFE_Err Dfe_clearRxIbpmReadRequest
+(
+ DFE_Handle hDfe,
+ uint32_t pmId
+);
+
+// Program Rx Equalizer
+DFE_Err Dfe_progRxEqr
+(
+ DFE_Handle hDfe,
+ uint32_t rxDev,
+ uint32_t shift,
+ uint32_t numCoeff,
+ DFE_RxEqrTaps *RxEqrTaps
+);
+
+// Issue Sync to update Rx Equalizer
+DFE_Err Dfe_issueSyncUpdateRxEqr
+(
+ DFE_Handle hDfe,
+ uint32_t rxDev,
+ DfeFl_MiscSyncGenSig ssel
+);
+
+// Program Rx Mixer NCO
+DFE_Err Dfe_progRxMixerNCO
+(
+ DFE_Handle hDfe,
+ uint32_t rxDev,
+ float refClock,
+ float freq
+);
+
+// Issue Sync to update Rx Mixer NCO
+DFE_Err Dfe_issueSyncUpdateRxMixerNCO
+(
+ DFE_Handle hDfe,
+ DfeFl_MiscSyncGenSig ssel
+);
+
+// Program Rx Testbus
+DFE_Err Dfe_progRxTestbus
+(
+ DFE_Handle hDfe,
+ uint32_t top_ctrl,
+ uint32_t imb_ctrl,
+ uint32_t feagc_dc_ctrl
+);
+
+// Program Fb Equalizer
+DFE_Err Dfe_progFbEqr
+(
+ DFE_Handle hDfe,
+ DfeFl_FbBlk FbBlkId,
+ uint32_t numCoeff,
+ DFE_FbEqrTaps *FbEqrTaps
+);
+
+// Issue sync update Fb Equalizer
+DFE_Err Dfe_issueSyncUpdateFbEqr
+(
+ DFE_Handle hDfe,
+ DfeFl_MiscSyncGenSig ssel
+);
+
+// Program Fb Mixer NCO
+DFE_Err Dfe_progFbMixerNCO
+(
+ DFE_Handle hDfe,
+ DfeFl_FbBlk FbBlkId,
+ float refClock,
+ float freq
+);
+
+// Issue sync update Fb Mixer NCO
+DFE_Err Dfe_issueSyncUpdateFbMixerNCO
+(
+ DFE_Handle hDfe,
+ DfeFl_MiscSyncGenSig ssel
+);
+
+// Program Fb IO Mux
+DFE_Err Dfe_progFbIOMux
+(
+ DFE_Handle hDfe,
+ DfeFl_FbIoMux ioMux
+);
+
+// Program Fb pre-cb gain
+DFE_Err Dfe_progFbGain
+(
+ DFE_Handle hDfe,
+ DfeFl_FbBlk FbBlkId,
+ float FbGain[2]
+);
+
+// Issue sync update Fb gain
+DFE_Err Dfe_issueSyncUpdateFbGain
+(
+ DFE_Handle hDfe,
+ DfeFl_MiscSyncGenSig ssel
+);
+
+// Program CB node configuration
+DFE_Err Dfe_progCbNodecfg
+(
+ DFE_Handle hDfe,
+ DfeFl_CbNodeCfg *nodeCfg
+);
+
+// Program CB buf configuration
+DFE_Err Dfe_progCbBufcfg
+(
+ DFE_Handle hDfe,
+ DFE_CbBufCfg *bufCfg
+);
+
+// Arm CB and Issue Sync
+DFE_Err Dfe_armCbIssueSync
+(
+ DFE_Handle hDfe,
+ DfeFl_MiscSyncGenSig ssel
+);
+
+// Get CB done status
+DFE_Err Dfe_getCbDoneStatus
+(
+ DFE_Handle hDfe,
+ DfeFl_CbArm *cbDoneStatus
+);
+
+// Read Cb Buf and Status
+DFE_Err Dfe_readCbBuf
+(
+ DFE_Handle hDfe,
+ DfeFl_CbBuf cbBufId,
+ uint32_t cbLength,
+ uint32_t flag_18bit,
+ DfeFl_CbComplexInt *cbTemp,
+ DfeFl_CbStatus *cbStatus,
+ DFE_CbData *cbData
+);
+
+// Open CB buf DMA for reading CB buf
+DFE_Err Dfe_openCbBufDma
+(
+ DFE_Handle hDfe,
+ uint32_t flag_18bit,
+ uint32_t cppDmaId,
+ uint32_t cppDescripId[8],
+ uint32_t iqnChnl
+);
+
+// Close CB buf DMA
+DFE_Err Dfe_closeCbBufDma
+(
+ DFE_Handle hDfe
+);
+
+// Enable CB buf DMA
+DFE_Err Dfe_enableCbBufDma
+(
+ DFE_Handle hDfe
+);
+
+// Disable CB buf DMA
+DFE_Err Dfe_disableCbBufDma
+(
+ DFE_Handle hDfe
+);
+
+// Disable All Testbus Probes
+DFE_Err Dfe_disableAllTestbus
+(
+ DFE_Handle hDfe
+);
+
+// program pinmux of a DFE GPIO pin
+DFE_Err Dfe_progGpioPinMux
+(
+ DFE_Handle hDfe,
+ DfeFl_MiscGpioPin pinId,
+ DfeFl_MiscGpioMux muxSel
+);
+
+// Set DFE GPIO Sync Out Source
+DFE_Err Dfe_setGpioSyncOutSource
+(
+ DFE_Handle hDfe,
+ uint32_t syncoutId,
+ DfeFl_MiscSyncGenSig ssel
+);
+
+// Set DFE GPIO Bank Output
+DFE_Err Dfe_setGpioBankOutput
+(
+ DFE_Handle hDfe,
+ uint32_t bankOutput
+);
+
+// Get DFE GPIO Bank Input
+DFE_Err Dfe_getGpioBankInput
+(
+ DFE_Handle hDfe,
+ uint32_t *bankInput
+);
+
+// Open Cpp/DMA for Generic IO
+DFE_Err Dfe_openGenericDma
+(
+ DFE_Handle hDfe,
+ uint32_t cppDmaId,
+ uint32_t iqnChnlDl,
+ uint32_t iqnChnlUl
+);
+
+// Close Cpp/DMA for Generic IO
+DFE_Err Dfe_closeGenericDma
+(
+ DFE_Handle hDfe
+);
+
+// Prepare CPP/DMA embeded header
+DFE_Err Dfe_prepareGenericDmaHeader
+(
+ DFE_Handle hDfe,
+ uint32_t *header,
+ DFE_GenericDmaReadWriteMode rwMode,
+ uint32_t offsetAddrInDref,
+ uint32_t sizeOrData
+);
+
+// Enable toggle for one dpd block
+DFE_Err Dfe_enableDpdToggle
+(
+ DFE_Handle hDfe,
+ uint32_t blkId
+);
+
+// Set sync selection for one dpd block
+DFE_Err Dfe_setDpdSyncSel
+(
+ DFE_Handle hDfe,
+ uint32_t blkId,
+ uint32_t synch
+);
+
+// Issue sync update lut
+DFE_Err Dfe_issueSyncUpdateDpdLut
+(
+ DFE_Handle hDfe,
+ uint32_t numBlks,
+ uint32_t blkId[],
+ DfeFl_MiscSyncGenSig ssel
+);
+
+// Get current lut memory index status for one dpd block
+DFE_Err Dfe_getDpdLutIdx
+(
+ DFE_Handle hDfe,
+ uint32_t blkId,
+ uint32_t *LutIdx
+);
+
+// program lut for one dpd cell
+DFE_Err Dfe_progDpdLutTable
+(
+ DFE_Handle hDfe,
+ uint32_t blkId,
+ uint32_t rowId,
+ uint32_t cellId,
+ DFE_DpdData *DpdData
+);
+
+// get dpd configuration
+DFE_Err Dfe_getDpdCfg
+(
+ DFE_Handle hDfe,
+ DFE_DpdCfg *dpdCfg
+);
+
+// start DPDA
+DFE_Err Dfe_startDpda(
+ DFE_Handle hDfe,
+ uint16_t startAddress
+);
+
+// load the DPDA image
+DFE_Err Dfe_loadDpda(
+ DFE_Handle hDfe,
+ uint32_t imageSize,
+ DFE_RegPair *imagePtr
+);
+
+// write DPDA scalar register
+DFE_Err Dfe_writeDpdaScalar(
+ DFE_Handle hDfe,
+ uint8_t scalarId,
+ float iScalar,
+ float qScalar
+);
+
+// write value to DPDA IG register file
+DFE_Err Dfe_writeDpdaIg(
+ DFE_Handle hDfe,
+ uint8_t igId,
+ uint32_t ig
+);
+
+// write samples to capture buffer
+DFE_Err Dfe_writeDpdaSamples(
+ DFE_Handle hDfe,
+ DfeFl_CbBuf cbBufId,
+ uint8_t fbFlag,
+ uint16_t cbLength,
+ DfeFl_CbComplexInt *cbTemp,
+ DFE_CbData *cbData
+);
+
+DFE_Err Dfe_readDpdaScalar(
+ DFE_Handle hDfe,
+ uint8_t scalarId,
+ float *iScalarPtr,
+ float *qScalarPtr
+);
+
+DFE_Err Dfe_readDpdaIg(
+ DFE_Handle hDfe,
+ uint8_t igId,
+ uint32_t *igPtr
+);
+
+DFE_Err Dfe_readDpdaParams(
+ DFE_Handle hDfe,
+ uint16_t lineId,
+ uint16_t lineNum,
+ float *paramTbl
+);
+
+/* Reset DFE Errors and Alarms counters */
+void Dfe_resetException(
+ DFE_Handle hDfe
+);
+
+/* Capture and copy DFE Errors and Alarms counters */
+void Dfe_captureException (
+ DFE_Handle hDfe,
+ DFE_EeCountObj *capturePtr
+);
+
+/* Enable DFE Errors and Alarms */
+DFE_Err Dfe_enableException(
+ DFE_Handle hDfe
+);
+
+/* Disable DFE Errors and Alarms */
+DFE_Err Dfe_disableException(
+ DFE_Handle hDfe
+);
+
+/* Get Dfe Errors and Alarms status and clear */
+DFE_Err Dfe_getException(
+ DFE_Handle hDfe
+);
+
+void Dfe_printException(
+ DFE_Handle hDfe
+);
+
+DFE_Err Dfe_enableCbException(
+ DFE_Handle hDfe
+);
+
+DFE_Err Dfe_disableCbException(
+ DFE_Handle hDfe
+);
+
+DFE_Err Dfe_enableCppDmaDoneException(
+ DFE_Handle hDfe,
+ uint32_t cppDmaChannelNum
+);
+
+DFE_Err Dfe_disableCppDmaDoneException(
+ DFE_Handle hDfe,
+ uint32_t cppDmaChannelNum
+);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __DFE_DRV_H__ */
diff --git a/packages/ti/drv/dfe/dfe_fl.h b/packages/ti/drv/dfe/dfe_fl.h
--- /dev/null
@@ -0,0 +1,395 @@
+/********************************************************************
+* Copyright (C) 2012-2013 Texas Instruments Incorporated.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+/**
+ * @defgroup DFE_FL_API DFE FL
+ */
+/** @file dfe_fl.h
+ *
+ * @path $(CSLPATH)\inc
+ *
+ * @brief Header file for functional layer of DFE CSL
+ *
+ * Description
+ * - Function level symbolic constants, enumerations, structure definitions
+ * and function prototype declarations
+ *
+ */
+
+/**
+ * @defgroup DFE_FL_DATASTRUCT DFE Data Structures
+ * @ingroup DFE_FL_API
+ */
+
+/**
+ * @defgroup DFE_FL_SYMBOL DFE Symbols Defined
+ * @ingroup DFE_FL_API
+ */
+
+/**
+ * @defgroup DFE_FL_FUNCTION DFE Functions
+ * @ingroup DFE_FL_API
+ */
+
+
+#ifndef _DFE_FL_H_
+#define _DFE_FL_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+//#include <ti/csl/csl.h>
+#include <ti/csl/cslr.h>
+
+/**
+ * @addtogroup DFE_FL_SYMBOL
+ * @{
+ */
+
+/**************************************************************************
+* Peripheral Instance counts
+**************************************************************************/
+/// total BB blocks
+#define DFE_FL_BB_PER_CNT 1
+/// total DDUC blocks
+#define DFE_FL_DDUC_PER_CNT 4
+/// total SUMMER blocks
+#define DFE_FL_SUMMER_PER_CNT 1
+/// total AUTOCP blocks
+#define DFE_FL_AUTOCP_PER_CNT 1
+/// total CFR blocks
+#define DFE_FL_CFR_PER_CNT 2
+/// total CDFR blocks
+#define DFE_FL_CDFR_PER_CNT 1
+/// total DPD blocks
+#define DFE_FL_DPD_PER_CNT 1
+/// total DPDA blocks
+#define DFE_FL_DPDA_PER_CNT 1
+/// total TX blocks
+#define DFE_FL_TX_PER_CNT 1
+/// total RX blocks
+#define DFE_FL_RX_PER_CNT 1
+/// total CB blocks
+#define DFE_FL_CB_PER_CNT 1
+/// total JESD blocks
+#define DFE_FL_JESD_PER_CNT 1
+/// total FB blocks
+#define DFE_FL_FB_PER_CNT 1
+/// total MISC blocks
+#define DFE_FL_MISC_PER_CNT 1
+
+/**************************************************************************\
+* Peripheral Instance definitions.
+\**************************************************************************/
+
+/** @brief Instance number of BB */
+#define DFE_FL_BB_0 0
+
+/** @brief Instance number of DDUC0 */
+#define DFE_FL_DDUC_0 0
+/** @brief Instance number of DDUC1 */
+#define DFE_FL_DDUC_1 1
+/** @brief Instance number of DDUC2 */
+#define DFE_FL_DDUC_2 2
+/** @brief Instance number of DDUC3 */
+#define DFE_FL_DDUC_3 3
+
+/** @brief Instance number of SUMMER */
+#define DFE_FL_SUMMER_0 0
+
+/** @brief Instance number of AUTOCP */
+#define DFE_FL_AUTOCP_0 0
+
+/** @brief Instance number of CFR0 */
+#define DFE_FL_CFR_0 0
+/** @brief Instance number of CFR1 */
+#define DFE_FL_CFR_1 1
+
+/** @brief Instance number of CDFR */
+#define DFE_FL_CDFR_0 0
+
+/** @brief Instance number of DPD */
+#define DFE_FL_DPD_0 0
+
+/** @brief Instance number of DPDA */
+#define DFE_FL_DPDA_0 0
+
+/** @brief Instance number of TX */
+#define DFE_FL_TX_0 0
+
+/** @brief Instance number of RX */
+#define DFE_FL_RX_0 0
+
+/** @brief Instance number of CB */
+#define DFE_FL_CB_0 0
+
+/** @brief Instance number of JESD */
+#define DFE_FL_JESD_0 0
+
+/** @brief Instance number of FB */
+#define DFE_FL_FB_0 0
+
+/** @brief Instance number of MISC */
+#define DFE_FL_MISC_0 0
+
+/**************************************************************************\
+* Peripheral Offset within DFE
+\**************************************************************************/
+
+/** @brief offset of BB instance */
+#define DFE_FL_BB_0_OFFSET 0x0000000
+
+/** @brief offset of DDUC1 instance */
+#define DFE_FL_DDUC_0_OFFSET 0x0100000
+/** @brief offset of DDUC2 instance */
+#define DFE_FL_DDUC_1_OFFSET 0x0180000
+/** @brief offset of DDUC3 instance */
+#define DFE_FL_DDUC_2_OFFSET 0x0200000
+/** @brief offset of DDUC4 instance */
+#define DFE_FL_DDUC_3_OFFSET 0x0280000
+
+/** @brief offset of SUMMEr instance */
+#define DFE_FL_SUMMER_0_OFFSET 0x0900000
+
+/** @brief offset of CFR0 instance */
+#define DFE_FL_CFR_0_OFFSET 0x0b00000
+/** @brief offset of CFR1 instance */
+#define DFE_FL_CFR_1_OFFSET 0x0b80000
+
+/** @brief offset of SUMMEr instance */
+#define DFE_FL_AUTOCP_0_OFFSET 0x0f00000
+
+/** @brief offset of CDFR instance */
+#define DFE_FL_CDFR_0_OFFSET 0x1000000
+
+/** @brief offset of DPD instance */
+#define DFE_FL_DPD_0_OFFSET 0x1300000
+
+/** @brief offset of DPDA instance */
+#define DFE_FL_DPDA_0_OFFSET 0x1500000
+
+/** @brief offset of TX instance */
+#define DFE_FL_TX_0_OFFSET 0x1600000
+
+/** @brief offset of RX instance */
+#define DFE_FL_RX_0_OFFSET 0x1a00000
+
+/** @brief offset of CB instance */
+#define DFE_FL_CB_0_OFFSET 0x1c00000
+
+/** @brief offset of JESD instance */
+#define DFE_FL_JESD_0_OFFSET 0x1d00000
+
+/** @brief offset of FB instance */
+#define DFE_FL_FB_0_OFFSET 0x1e80000
+
+/** @brief offset of MISC instance */
+#define DFE_FL_MISC_0_OFFSET 0x1f00000
+
+/**************************************************************************
+* DFE error code (no more than 32 codes)
+**************************************************************************/
+//#define EDFE_FL_SYNC_TIMEOUT (CSL_EDFE_FIRST - 0)
+
+#ifndef NULL
+#define NULL ((void*)0)
+#endif
+
+/**
+ * @}
+ */
+
+/**
+ * @addtogroup DFE_FL_DATASTRUCT
+ * @{
+ */
+
+typedef int16_t DfeFl_InstNum;
+
+
+/**
+ *
+ * @brief dfe fl return and error codes
+ *
+ * */
+typedef enum
+{
+ /** Sync timeout */
+ DFE_FL_SYNC_TIMEOUT = -10,
+ /** Action not supported */
+ DFE_FL_NOTSUPPORTED = -9,
+ /** Invalid query */
+ DFE_FL_INVQUERY = -8,
+ /** Invalid command */
+ DFE_FL_INVCMD = -7,
+ /** Invalid parameters */
+ DFE_FL_INVPARAMS = -6,
+ /** Handle passed to DFE FL was invalid */
+ DFE_FL_BADHANDLE = -5,
+ /** Encoutered DFE FL system resource overflow */
+ DFE_FL_OVFL = -4,
+ /** Unused code */
+ DFE_FL_UNUSED = -3,
+ /** DFE FL Peripheral resource is already in use */
+ DFE_FL_INUSE = -2,
+ /** DFE FL Generic Failure */
+ DFE_FL_FAIL = -1,
+ /** DFE FL successful return code */
+ DFE_FL_SOK = 1
+} DfeFl_Status;
+
+/**************************************************************************\
+* DFE top level structs
+\**************************************************************************/
+typedef volatile uint32_t * DfeFl_RegsOvly;
+
+/**
+ * @brief Sub-block inits config
+ */
+typedef struct {
+ uint32_t ssel;
+ uint32_t initClkGate;
+ uint32_t initState;
+ uint32_t clearData;
+} DfeFl_SublkInitsConfig;
+
+/**
+ * @brief clock gate
+ */
+typedef struct
+{
+ uint32_t timeStep;
+ uint32_t resetInterval;
+ uint32_t tddPeriod;
+ uint32_t tddOn0;
+ uint32_t tddOff0;
+ uint32_t tddOn1;
+ uint32_t tddOff1;
+} DfeFl_ClockGateConfig;
+
+/**
+ * @brief Module specific context information.
+ */
+typedef struct {
+ /**
+ * The below declaration is just a place-holder for future implementation.
+ */
+ uint32_t contextInfo;
+} DfeFl_Context;
+
+/** @brief Module specific parameters.
+ */
+typedef struct {
+ /** Bit mask to be used for module specific parameters. The below
+ * declaration is just a place-holder for future implementation.
+ */
+ uint32_t flags;
+} DfeFl_Param;
+
+/** @brief This structure contains the base-address information for the
+ * peripheral instance
+ */
+typedef struct {
+ /** Base-address of the configuration registers of the peripheral
+ */
+ DfeFl_RegsOvly regs;
+} DfeFl_BaseAddress;
+
+/**
+ * @brief DFE object structure.
+ */
+typedef struct {
+ /** Pointer to the register overlay structure of the DFE */
+ DfeFl_RegsOvly regs;
+
+ /** Instance of DFE being referred by this object */
+ DfeFl_InstNum dfeNum;
+} DfeFl_Obj;
+
+
+/**
+ * @brief This data type is used to return the handle to the CSL of DFE
+ */
+typedef DfeFl_Obj *DfeFl_Handle;
+
+/**
+ * @}
+ */
+
+/**
+ * @addtogroup DFE_FL_FUNCTION
+ * @{
+ */
+
+/**************************************************************************\
+* DFE top level APIs
+\**************************************************************************/
+extern DfeFl_Status dfeFl_Init (
+ DfeFl_Context *pContext
+);
+
+extern DfeFl_Handle dfeFl_Open (
+ DfeFl_Obj *pDfeObj,
+ DfeFl_InstNum dfeNum,
+ DfeFl_Param *pDfeParam,
+ uint32_t dfeBaseAddr,
+ DfeFl_Status *status
+
+);
+
+extern DfeFl_Status dfeFl_GetBaseAddress (
+ DfeFl_InstNum dfeNum,
+ DfeFl_Param *pDfeParam,
+ DfeFl_BaseAddress *pBaseAddress
+);
+
+extern DfeFl_Status dfeFl_GetPID (
+ DfeFl_Handle hDfe,
+ uint32_t *pid
+);
+
+extern DfeFl_Status dfeFl_Close (
+ DfeFl_Handle hDfe
+);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _DFE_FL_H_ */
diff --git a/packages/ti/drv/dfe/dfe_fl_autocp.h b/packages/ti/drv/dfe/dfe_fl_autocp.h
--- /dev/null
@@ -0,0 +1,179 @@
+/********************************************************************
+* Copyright (C) 2012-2013 Texas Instruments Incorporated.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+/**
+ * @defgroup DFE_FL_AUTOCP_API AUTOCP
+ * @ingroup DFE_FL_API
+ */
+
+/** @file dfe_fl_autocp.h
+ *
+ * @path $(CSLPATH)\inc
+ *
+ * @brief Header file for functional layer of DFE_AUTOCP CSL
+ *
+ * Description
+ * - Function level symbolic constants, enumerations, structure definitions
+ * and function prototype declarations
+ *
+ */
+/* =============================================================================
+ * Revision History
+ * ===============
+ *
+ *
+ * =============================================================================
+ */
+
+/**
+ * @defgroup DFE_FL_AUTOCP_DATASTRUCT DFE Autocp Data Structures
+ * @ingroup DFE_FL_AUTOCP_API
+ */
+
+/**
+ * @defgroup DFE_FL_AUTOCP_ENUM DFE Autocp Enumverated Data Types
+ * @ingroup DFE_FL_AUTOCP_API
+ */
+
+/**
+ * @defgroup DFE_FL_AUTOCP_FUNCTION DFE Autocp Functions
+ * @ingroup DFE_FL_AUTOCP_API
+ */
+#ifndef _DFE_FL_AUTOCP_H_
+#define _DFE_FL_AUTOCP_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <ti/drv/dfe/dfe_fl.h>
+#include <ti/csl/cslr_dfe_autocp.h>
+
+/**
+ * @addtogroup DFE_FL_AUTOCP_ENUM
+ * @{
+ */
+
+/** @brief control commands
+ */
+typedef enum
+{
+ /**
+ * init
+ */
+ DFE_FL_AUTOCP_CMD_CFG_INITS,
+
+
+ DFE_FL_AUTOCP_CMD_MAX_VALUE
+} DfeFl_AutocpHwControlCmd;
+
+/** @brief query commands
+ */
+typedef enum
+{
+ DFE_FL_AUTOCP_QUERY_MAX_VALUE
+} DfeFl_AutocpHwStatusQuery;
+
+/**
+ * @}
+ */
+
+/**
+ * @addtogroup DFE_FL_AUTOCP_DATASTRUCT
+ * @{
+ */
+
+/** @brief overlay register pointer to AUTOCP instance
+ */
+typedef CSL_DFE_AUTOCP_REGS *DfeFl_AutocpRegsOvly;
+
+/** @brief AUTOCP Object of Digital radio Front End (DFE) */
+typedef struct
+{
+ /// handle to DFE global
+ DfeFl_Handle hDfe;
+
+ /// pointer to register base address of a AUTOCP instance
+ DfeFl_AutocpRegsOvly regs;
+
+ /// This is the instance of AUTOCP being referred to by this object
+ DfeFl_InstNum perNum;
+
+} DfeFl_AutocpObj;
+
+/** @brief handle pointer to AUTOCP object
+ */
+typedef DfeFl_AutocpObj *DfeFl_AutocpHandle;
+
+/**
+ * @}
+ */
+
+/**
+ * @addtogroup DFE_FL_AUTOCP_FUNCTION
+ * @{
+ */
+
+DfeFl_AutocpHandle dfeFl_AutocpOpen
+(
+ DfeFl_Handle hDfe,
+ DfeFl_AutocpObj *pDfeAutocpObj,
+ DfeFl_InstNum perNum,
+ DfeFl_Status *pStatus
+);
+
+DfeFl_Status dfeFl_AutocpClose(DfeFl_AutocpHandle hDfeAutocp);
+
+DfeFl_Status dfeFl_AutocpHwControl
+(
+ DfeFl_AutocpHandle hDfeAutocp,
+ DfeFl_AutocpHwControlCmd ctrlCmd,
+ void *arg
+);
+
+DfeFl_Status dfeFl_AutocpGetHwStatus
+(
+ DfeFl_AutocpHandle hDfeAutocp,
+ DfeFl_AutocpHwStatusQuery queryId,
+ void *arg
+);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _DFE_FL_AUTOCP_H_ */
diff --git a/packages/ti/drv/dfe/dfe_fl_autocpAux.h b/packages/ti/drv/dfe/dfe_fl_autocpAux.h
--- /dev/null
@@ -0,0 +1,108 @@
+/********************************************************************
+* Copyright (C) 2012-2013 Texas Instruments Incorporated.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+/** @file dfe_fl_autocpAux.h
+ *
+ * @path $(CSLPATH)\inc
+ *
+ * @brief Header file for functional layer of DFE_AUTOCP CSL
+ *
+ * Description
+ * - Function level symbolic constants, enumerations, structure definitions
+ * and function prototype declarations
+ *
+ */
+#ifndef _DFE_FL_AUTOCPAUX_H_
+#define _DFE_FL_AUTOCPAUX_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <ti/csl/csl.h>
+#include <ti/drv/dfe/dfe_fl_autocp.h>
+
+/** ============================================================================
+ * @n@b dfeFl_AutocpConfigInits
+ *
+ * @b Description
+ * @n [add content]
+ *
+ * @b Arguments
+ * @verbatim
+ hAutocp [add content]
+ arg [add content]
+ @endverbatim
+ *
+ * <b> Return Value </b> None
+ *
+ * <b> Pre Condition </b>
+ * @n [add content]
+ *
+ * <b> Post Condition </b>
+ * @n [add content]
+ *
+ * @b Reads
+ * @n None
+ *
+ * @b Writes
+ * @n see below,
+ * DFE_AUTOCP_INITS_REG_INIT_CLK_GATE
+ * DFE_AUTOCP_INITS_REG_INITS_SSEL
+ * DFE_AUTOCP_INITS_REG_INIT_STATE
+ * DFE_AUTOCP_INITS_REG_CLEAR_DATA
+ *
+ * @b Example
+ * @verbatim
+ [add content]
+ @endverbatim
+ * ===========================================================================
+ */
+CSL_IDEF_INLINE void
+dfeFl_AutocpConfigInits(DfeFl_AutocpHandle hAutocp, DfeFl_SublkInitsConfig * arg)
+{
+ uint32_t data = hAutocp->regs->inits;
+
+ CSL_FINS(data, DFE_AUTOCP_INITS_REG_INITS_SSEL, arg->ssel);
+ CSL_FINS(data, DFE_AUTOCP_INITS_REG_INIT_CLK_GATE, arg->initClkGate);
+ CSL_FINS(data, DFE_AUTOCP_INITS_REG_INIT_STATE, arg->initState);
+ CSL_FINS(data, DFE_AUTOCP_INITS_REG_CLEAR_DATA, arg->clearData);
+
+ hAutocp->regs->inits = data;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _DFE_FL_AUTOCPAUX_H_ */
diff --git a/packages/ti/drv/dfe/dfe_fl_bb.h b/packages/ti/drv/dfe/dfe_fl_bb.h
--- /dev/null
@@ -0,0 +1,1433 @@
+/********************************************************************
+* Copyright (C) 2012-2013 Texas Instruments Incorporated.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+/**
+ * @defgroup DFE_FL_BB_API BB
+ * @ingroup DFE_FL_API
+ */
+
+/** @file dfe_fl_bb.h
+ *
+ * @path $(CSLPATH)\inc
+ *
+ * @brief Header file for functional layer of DFE_BB CSL
+ *
+ * Description
+ * - Function level symbolic constants, enumerations, structure definitions
+ * and function prototype declarations
+ *
+ */
+/* =============================================================================
+ * Revision History
+ * ===============
+ *
+ *
+ * =============================================================================
+ */
+
+/**
+ * @defgroup DFE_FL_BB_SYMBOL DFE Bb Symbols
+ * @ingroup DFE_FL_BB_API
+ */
+
+/**
+ * @defgroup DFE_FL_BB_DATASTRUCT DFE Bb Data Structures
+ * @ingroup DFE_FL_BB_API
+ */
+
+/**
+ * @defgroup DFE_FL_BB_ENUM DFE Bb Enumverated Data Types
+ * @ingroup DFE_FL_BB_API
+ */
+
+/**
+ * @defgroup DFE_FL_BB_FUNCTION DFE Bb Functions
+ * @ingroup DFE_FL_BB_API
+ */
+
+#ifndef _DFE_FL_BB_H_
+#define _DFE_FL_BB_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//#include <ti/csl/csl.h>
+#include <ti/csl/cslr_dfe_bb.h>
+#include <ti/drv/dfe/dfe_fl.h>
+
+/**
+ * @addtogroup DFE_FL_BB_SYMBOL
+ * @{
+ */
+
+#define DFE_FL_BB_MAX_AID_STREAM_ID 256
+#define DFE_FL_BB_MAX_SLOTS 256
+#define DFE_FL_BB_MAX_DL_XLATES 256
+#define DFE_FL_BB_MAX_UL_XLATES 48
+/// max supported carrier types
+#define DFE_FL_BB_MAX_CARRIER_TYPES 16
+#define DFE_FL_BB_AXC_MAX_SLOTS 16
+/// max supported BB power meters each direction
+#define DFE_FL_BB_MAX_POWMTRS 16
+/// max supported AxCs per antenna
+#define DFE_FL_BB_ANTENNA_MAX_AXCS 16
+
+/**
+ * @}
+ */
+
+/**
+ * @addtogroup DFE_FL_BB_ENUM
+ * @{
+ */
+/** @brief control commands
+ */
+typedef enum
+{
+ /// BB inits
+ DFE_FL_BB_CMD_CFG_INITS,
+ /// enable aid loopback
+ DFE_FL_BB_CMD_ENB_AID_LOOPBACK,
+ /// disable aid loopback
+ DFE_FL_BB_CMD_DIS_AID_LOOPBACK,
+ /// buf loopback config
+ DFE_FL_BB_CMD_CFG_LOOPBACK,
+ /// capture buffer config
+ DFE_FL_BB_CMD_CFG_CAPBUFF,
+ /// test signal generation config
+ DFE_FL_BB_CMD_CFG_TESTGEN,
+ /// test signal generation sync selection
+ DFE_FL_BB_CMD_SET_TESTGEN_SSEL,
+ /// config chksum
+ DFE_FL_BB_CMD_CFG_CHKSUM,
+ /// select checksum sync source
+ DFE_FL_BB_CMD_SET_CHKSUM_SSEL,
+ /// select carrier type UL sync strobe
+ DFE_FL_BB_CMD_CFG_CT_UL_SYNC_STROBE,
+ /// set AID UL strobe delay
+ DFE_FL_BB_CMD_CFG_AID_ULSTROBE_DLY,
+
+ /// config TXIF_AXC
+ DFE_FL_BB_CMD_CFG_TXIF_AXC,
+ /// config RXIF_AXC
+ DFE_FL_BB_CMD_CFG_RXIF_AXC,
+ /// config sync selection for tx gain update
+ DFE_FL_BB_CMD_SET_TXGAIN_SSEL,
+ /// update TX gain of axc
+ DFE_FL_BB_CMD_UPD_TXGAIN,
+ /// enable txgain update interrupt
+ DFE_FL_BB_CMD_ENB_TXGAIN_INTR,
+ /// disable txgain update interrupt
+ DFE_FL_BB_CMD_DIS_TXGAIN_INTR,
+ /// clear txgain update interrupt status
+ DFE_FL_BB_CMD_CLR_TXGAIN_INTR_STATUS,
+ /// force set txgain update interrupt
+ DFE_FL_BB_CMD_SET_FORCE_TXGAIN_INTR,
+ /// clear set txgain update interrupt
+ DFE_FL_BB_CMD_CLR_FORCE_TXGAIN_INTR,
+
+ /// TX TDD timer config
+ DFE_FL_BB_CMD_CFG_TXTDD,
+ /// TX TDD timer config sync selection
+ DFE_FL_BB_CMD_SET_TXTDD_SSEL,
+ /// RX TDD timer config
+ DFE_FL_BB_CMD_CFG_RXTDD,
+ /// RX TDD timer config sync selection
+ DFE_FL_BB_CMD_SET_RXTDD_SSEL,
+
+ /** TX power meter commands
+ */
+ /// config a tx power meter
+ DFE_FL_BB_CMD_CFG_TXPM,
+ /// config a tx power meter ssel
+ DFE_FL_BB_CMD_SET_TXPM_SSEL,
+ /// disable update of a tx power meter
+ DFE_FL_BB_CMD_DIS_TXPM_UPDATE,
+ /// enable interrupt of a tx power meter
+ DFE_FL_BB_CMD_ENB_TXPM_INTR,
+ /// enable interrupt of a tx power meter
+ DFE_FL_BB_CMD_DIS_TXPM_INTR,
+ /// clear interrupt status of a tx power meter
+ DFE_FL_BB_CMD_CLR_TXPM_INTR_STATUS,
+ /// force setting interrupt status of a tx power meter
+ DFE_FL_BB_CMD_SET_FORCE_TXPM_INTR,
+ /// clear forcing interrupt status of a tx power meter
+ DFE_FL_BB_CMD_CLR_FORCE_TXPM_INTR,
+ /// enable interrupt to the cpp
+ DFE_FL_BB_CMD_ENB_TXPM_AUXINTR,
+ /// disable interrupt to the cpp
+ DFE_FL_BB_CMD_DIS_TXPM_AUXINTR,
+
+ /** RX power meter commands
+ */
+ /// config a BBRX power meter
+ DFE_FL_BB_CMD_CFG_RXPM,
+ /// select sync source for BBRX power meter
+ DFE_FL_BB_CMD_SET_RXPM_SSEL,
+ /// disable a BBRX power meter update
+ DFE_FL_BB_CMD_DIS_RXPM_UPDATE,
+ /// enable a BBRX power meter interrupt
+ DFE_FL_BB_CMD_ENB_RXPM_INTR,
+ /// disable a BBRX power meter interrupt
+ DFE_FL_BB_CMD_DIS_RXPM_INTR,
+ /// clear status of a BBRX power mter interrupt
+ DFE_FL_BB_CMD_CLR_RXPM_INTR_STATUS,
+ /// force generating a BBRX power meter interrupt
+ DFE_FL_BB_CMD_SET_FORCE_RXPM_INTR,
+ /// clear force generating a BBRX power meter interrupt
+ DFE_FL_BB_CMD_CLR_FORCE_RXPM_INTR,
+ /// enable BBRX aux interrupts
+ DFE_FL_BB_CMD_ENB_RXPM_AUXINTR,
+ /// disable BBRX aux interrupts
+ DFE_FL_BB_CMD_DIS_RXPM_AUXINTR,
+
+ /** Antenna Calibration
+ */
+ /// config antenna calibration global
+ DFE_FL_BB_CMD_CFG_ANTCAL_GLOBAL,
+ /// config antenna calibration
+ DFE_FL_BB_CMD_CFG_ANTCAL,
+
+
+
+ /** Rx gain control
+ */
+ /// config sync selection for tx gain update
+ DFE_FL_BB_CMD_SET_RXGAIN_SSEL,
+ /// update RX gain of axc
+ DFE_FL_BB_CMD_UPD_RXGAIN,
+ /// enable rx gain update interrupt
+ DFE_FL_BB_CMD_ENB_RXGAIN_INTR,
+ /// disable rx gain update interrupt
+ DFE_FL_BB_CMD_DIS_RXGAIN_INTR,
+ /// clear rx gain update interrupt status
+ DFE_FL_BB_CMD_CLR_RXGAIN_INTR_STATUS,
+ /// force setting rx gain update interrupt status
+ DFE_FL_BB_CMD_SET_FORCE_RXGAIN_INTR,
+ /// clear force setting rx gain update interrupt status
+ DFE_FL_BB_CMD_CLR_FORCE_RXGAIN_INTR,
+
+ /** beAGC control
+ */
+ /// config beAGC globals
+ DFE_FL_BB_CMD_CFG_BEAGC_GLOBAL,
+ /// config a beAGC control loop
+ DFE_FL_BB_CMD_CFG_BEAGC,
+ /// config a beAGC control loop ssel
+ DFE_FL_BB_CMD_SET_BEAGC_SSEL,
+
+ /** Rx Notch filter
+ */
+ /// config Rx Notch filter globals
+ DFE_FL_BB_CMD_CFG_RXNOTCH_GLOBAL,
+ /// Rx Notch ssel
+ DFE_FL_BB_CMD_SET_RXNOTCH_SSEL,
+ /// config a Rx Notch filter
+ DFE_FL_BB_CMD_CFG_RXNOTCH,
+
+ /** BB general interrupts
+ */
+ /// enable a BB general interrupt
+ DFE_FL_BB_CMD_ENB_GENERAL_INTR,
+ /// disable a BB general interrupt
+ DFE_FL_BB_CMD_DIS_GENERAL_INTR,
+ /// clear status of a BB general interrupt
+ DFE_FL_BB_CMD_CLR_GENERAL_INTR_STATUS,
+ /// force generating a BB general interrupt
+ DFE_FL_BB_CMD_SET_FORCE_GENERAL_INTR,
+ /// clear force generating a BB general interrupt
+ DFE_FL_BB_CMD_CLR_FORCE_GENERAL_INTR,
+ /// enable group of BB general interrupts
+ DFE_FL_BB_CMD_ENB_GENERAL_INTRGRP,
+ /// disable group of BB general interrupts
+ DFE_FL_BB_CMD_DIS_GENERAL_INTRGRP,
+ /// clear status of group of BB general interrupts
+ DFE_FL_BB_CMD_CLR_GENERAL_INTRGRP_STATUS,
+ /// force generating group of BB general interrupts
+ DFE_FL_BB_CMD_SET_FORCE_GENERAL_INTRGRP,
+ /// clear force generating group of BB general interrupts
+ DFE_FL_BB_CMD_CLR_FORCE_GENERAL_INTRGRP,
+
+
+ DFE_FL_BB_CMD_MAX_VALUE
+} DfeFl_BbHwControlCmd;
+
+/** @brief query commands
+ */
+typedef enum
+{
+ /// AID loopback config
+ DFE_FL_BB_QUERY_AID_LOOPBACK_CFG = 0,
+ /// loopback config
+ DFE_FL_BB_QUERY_LOOPBACK_CFG,
+ /// capture buffer config
+ DFE_FL_BB_QUERY_CAPBUFF_CFG,
+ /// test signal generation config
+ DFE_FL_BB_QUERY_TESTGEN_CFG,
+ /// test signal generation sync selection
+ DFE_FL_BB_QUERY_TESTGEN_SSEL,
+ /// chksum ssel
+ DFE_FL_BB_QUERY_CHKSUM_SSEL,
+ /// chksum result
+ DFE_FL_BB_QUERY_CHKSUM_RESULT,
+ /// get carrier type UL sync strobe
+ DFE_FL_BB_QUERY_CT_UL_SYNC_STROBE,
+ // get BB AID UL strobe delay
+ DFE_FL_BB_QUERY_AID_ULSTROBE_DLY,
+
+ /// TX GAIN upadte status
+ DFE_FL_BB_QUERY_TXGAIN_UPDATE_STATUS,
+ /// config sync selection for tx gain update
+ DFE_FL_BB_QUERY_TXGAIN_SSEL,
+ /// TX gain config
+ DFE_FL_BB_QUERY_TXGAIN_INTR_STATUS,
+
+ /// TX TDD timer config
+ DFE_FL_BB_QUERY_TXTDD_CFG,
+ /// TX TDD timer sync selection
+ DFE_FL_BB_QUERY_TXTDD_SSEL,
+ /// RX TDD timer config
+ DFE_FL_BB_QUERY_RXTDD_CFG,
+ /// RX TDD timer sync selection
+ DFE_FL_BB_QUERY_RXTDD_SSEL,
+
+ /** TX power meter queries
+ */
+ /// get BBTX power meter config
+ DFE_FL_BB_QUERY_TXPM_CFG,
+ /// get BBTX power meter sync select
+ DFE_FL_BB_QUERY_TXPM_SSEL,
+ /// get if BBTX power meter update disabled
+ DFE_FL_BB_QUERY_DIS_TXPM_UPDATE,
+ /// get status of BBTX power meter
+ DFE_FL_BB_QUERY_TXPM_INTR_STATUS,
+ /// get result of BBTX power meter
+ DFE_FL_BB_QUERY_TXPM_RESULT,
+
+ /** RX power meter queries
+ */
+ /// get BBRX power meter config
+ DFE_FL_BB_QUERY_RXPM_CFG,
+ /// get BBRX power meter sync select
+ DFE_FL_BB_QUERY_RXPM_SSEL,
+ /// get if BBRX power meter update disabled
+ DFE_FL_BB_QUERY_DIS_RXPM_UPDATE,
+ /// get status of BBRX power meter
+ DFE_FL_BB_QUERY_RXPM_INTR_STATUS,
+ /// get result of BBRX power meter
+ DFE_FL_BB_QUERY_RXPM_RESULT,
+
+ /** Antenna Calibration queries
+ */
+ /// get global config of antenna calibration
+ DFE_FL_BB_QUERY_ANTCAL_GLOBAL_CFG,
+ /// get config of antenna calibration
+ DFE_FL_BB_QUERY_ANTCAL_CFG,
+ /// get result of antenna calibration
+ DFE_FL_BB_QUERY_ANTCAL_RESULT,
+
+ /// RX GAIN upadte status
+ DFE_FL_BB_QUERY_RXGAIN_UPDATE_STATUS,
+ /// config sync selection for rx gain update
+ DFE_FL_BB_QUERY_RXGAIN_SSEL,
+ /// query rx gain update interrupt status
+ DFE_FL_BB_QUERY_RXGAIN_INTR_STATUS,
+ /// config beAGC globals
+ DFE_FL_BB_QUERY_BEAGC_GLOBAL_CFG,
+ /// config a beAGC control loop
+ DFE_FL_BB_QUERY_BEAGC_CFG,
+ /// config a beAGC control loop ssel
+ DFE_FL_BB_QUERY_BEAGC_SSEL,
+
+ /** Rx Notch filter
+ */
+ /// config Rx Notch filter globals
+ DFE_FL_BB_QUERY_RXNOTCH_GLOBAL_CFG,
+ /// Rx Notch ssel
+ DFE_FL_BB_QUERY_RXNOTCH_SSEL,
+ /// config a Rx Notch filter
+ DFE_FL_BB_QUERY_RXNOTCH_CFG,
+
+ /// get status of BB general interrupt
+ DFE_FL_BB_QUERY_GENERAL_INTR_STATUS,
+ /// get status of group of BB general interrupts
+ DFE_FL_BB_QUERY_GENERAL_INTRGRP_STATUS,
+
+ DFE_FL_BB_QUERY_MAX_VALUE
+} DfeFl_BbHwStatusQuery;
+
+/** @brief carrier type */
+typedef enum
+{
+ /// carrier type 0
+ DFE_FL_BB_CARRIER_TYPE_0 = 0,
+ /// carrier type 1
+ DFE_FL_BB_CARRIER_TYPE_1,
+ /// carrier type 2
+ DFE_FL_BB_CARRIER_TYPE_2,
+ /// carrier type 3
+ DFE_FL_BB_CARRIER_TYPE_3,
+ /// carrier type 4
+ DFE_FL_BB_CARRIER_TYPE_4,
+ /// carrier type 5
+ DFE_FL_BB_CARRIER_TYPE_5,
+ /// carrier type 6
+ DFE_FL_BB_CARRIER_TYPE_6,
+ /// carrier type 7
+ DFE_FL_BB_CARRIER_TYPE_7,
+ /// carrier type 8
+ DFE_FL_BB_CARRIER_TYPE_8,
+ /// carrier type 9
+ DFE_FL_BB_CARRIER_TYPE_9,
+ /// carrier type 10
+ DFE_FL_BB_CARRIER_TYPE_10,
+ /// carrier type 11
+ DFE_FL_BB_CARRIER_TYPE_11,
+ /// carrier type 12
+ DFE_FL_BB_CARRIER_TYPE_12,
+ /// carrier type 13
+ DFE_FL_BB_CARRIER_TYPE_13,
+ /// carrier type 14
+ DFE_FL_BB_CARRIER_TYPE_14,
+ /// carrier type 15
+ DFE_FL_BB_CARRIER_TYPE_15,
+
+ /// carrier type ALL
+ DFE_FL_BB_CARRIER_TYPE_ALL = 0xffff
+} DfeFl_BbCarrierType;
+
+/** @brief test_cb_control selection */
+typedef enum
+{
+ /// BB testbus probe, disabled (normal)
+ DFE_FL_BB_TEST_CB_CTRL_DISABLE = 0x00,
+ /// BB testbus probe, BBTX AID AxC single
+ DFE_FL_BB_TEST_CB_CTRL_TX_AID_S = 0x01,
+ /// BB testbus probe, BBTX AID AxC all
+ DFE_FL_BB_TEST_CB_CTRL_TX_AID_A = 0x03,
+ /// BB testbus probe, BBTX buffer memory single
+ DFE_FL_BB_TEST_CB_CTRL_TX_BUFMEM_S = 0x05,
+ /// BB testbus probe, BBTX buffer memory all
+ DFE_FL_BB_TEST_CB_CTRL_TX_BUFMEM_A = 0x07,
+ /// BB testbus probe, BBTX DDUC interface single
+ DFE_FL_BB_TEST_CB_CTRL_TX_DDUCIF_S = 0x09,
+ /// BB testbus probe, BBTX DDUC interface all
+ DFE_FL_BB_TEST_CB_CTRL_TX_DDUCIF_A = 0x0B,
+ /// BB testbus probe, BB JESDTX AxC single
+ DFE_FL_BB_TEST_CB_CTRL_JTX_AID_S = 0x0D,
+ /// BB testbus probe, BB JESDTX AxC all
+ DFE_FL_BB_TEST_CB_CTRL_JTX_AID_A = 0x0F,
+
+ /// BB testbus probe, BBRX AID AxC single
+ DFE_FL_BB_TEST_CB_CTRL_RX_AID_S = 0x21,
+ /// BB testbus probe, BBRX AID AxC all
+ DFE_FL_BB_TEST_CB_CTRL_RX_AID_A = 0x23,
+ /// BB testbus probe, BBRX buffer memory single
+ DFE_FL_BB_TEST_CB_CTRL_RX_BUFMEM_S = 0x25,
+ /// BB testbus probe, BBRX buffer memory all
+ DFE_FL_BB_TEST_CB_CTRL_RX_BUFMEM_A = 0x27,
+ /// BB testbus probe, BBRX DDUC interface single
+ DFE_FL_BB_TEST_CB_CTRL_RX_DDUCIF_S = 0x29,
+ /// BB testbus probe, BBRX DDUC interface all
+ DFE_FL_BB_TEST_CB_CTRL_RX_DDUCIF_A = 0x2B,
+ /// BB testbus probe, BB JESDRX AID AxC single
+ DFE_FL_BB_TEST_CB_CTRL_JRX_AID_S = 0x2D,
+ /// BB testbus probe, BB JESDRX AID AxC all
+ DFE_FL_BB_TEST_CB_CTRL_JRX_AID_A = 0x2F
+
+} DfeFl_BbTestCbCtrl;
+
+/** @brief BB general interrupt */
+typedef enum
+{
+ /// BB general interrupt, TXPM_LDERR
+ DFE_FL_BB_GENERAL_INTR_TXPM_LDERR = 0,
+ /// BB general interrupt, RXPM_LDERR
+ DFE_FL_BB_GENERAL_INTR_RXPM_LDERR = 1,
+ /// BB general interrupt, ANTCAL
+ DFE_FL_BB_GENERAL_INTR_ANTCAL = 2,
+ /// BB general interrupt, RXNOTCH_DONE
+ DFE_FL_BB_GENERAL_INTR_RXNOTCH_DONE = 3,
+ /// BB general interrupt, RXNOTCH_ERR
+ DFE_FL_BB_GENERAL_INTR_RXNOTCH_ERR = 4,
+
+ /// BB general interrupt, BUFMEM0_OUF (overflow/underflow)
+ DFE_FL_BB_GENERAL_INTR_BUFMEM0_OUF = 8,
+ /// BB general interrupt, BUFMEM1_OUF (overflow/underflow)
+ DFE_FL_BB_GENERAL_INTR_BUFMEM1_OUF = 9,
+ /// BB general interrupt, BUFMEM2_OUF (overflow/underflow)
+ DFE_FL_BB_GENERAL_INTR_BUFMEM2_OUF = 10,
+ /// BB general interrupt, BUFMEM3_OUF (overflow/underflow)
+ DFE_FL_BB_GENERAL_INTR_BUFMEM3_OUF = 11,
+ /// BB general interrupt, BUFMEM4_OUF (overflow/underflow)
+ DFE_FL_BB_GENERAL_INTR_BUFMEM4_OUF = 12,
+ /// BB general interrupt, BUFMEM5_OUF (overflow/underflow)
+ DFE_FL_BB_GENERAL_INTR_BUFMEM5_OUF = 13,
+ /// BB general interrupt, BUFMEM6_OUF (overflow/underflow)
+ DFE_FL_BB_GENERAL_INTR_BUFMEM6_OUF = 14,
+ /// BB general interrupt, BUFMEM7_OUF (overflow/underflow)
+ DFE_FL_BB_GENERAL_INTR_BUFMEM7_OUF = 15,
+ /// BB general interrupt, RXAID_SYNCERR
+ DFE_FL_BB_GENERAL_INTR_RXAID_SYNCERR = 16,
+ /// BB general interrupt, TXAID_UDF (under flow)
+ DFE_FL_BB_GENERAL_INTR_TXAID_UDF = 17,
+ /// BB general interrupt, TXAID_OVF (over flow)
+ DFE_FL_BB_GENERAL_INTR_TXAID_OVF = 18,
+ /// BB general interrupt, JESDRX_SYNCERR
+ DFE_FL_BB_GENERAL_INTR_JESDRX_SYNCERR = 19,
+ /// BB general interrupt, JESDTX_UDF (under flow)
+ DFE_FL_BB_GENERAL_INTR_JESDTX_UDF = 20,
+ /// BB general interrupt, JESDTX_OVF (over flow)
+ DFE_FL_BB_GENERAL_INTR_JESDTX_OVF = 21
+
+} DfeFl_BbGeneralIntr;
+
+/** @brief BB Test Signal Generation Device
+ */
+typedef enum
+{
+ /// TESTGEN for DDUC0 buffer
+ DFE_FL_BB_DDUC_TESTGEN_0 = 0,
+ /// TESTGEN for DDUC1 buffer
+ DFE_FL_BB_DDUC_TESTGEN_1,
+ /// TESTGEN for DDUC2 buffer
+ DFE_FL_BB_DDUC_TESTGEN_2,
+ /// TESTGEN for DDUC3 buffer
+ DFE_FL_BB_DDUC_TESTGEN_3,
+ /// TESTGEN for DDUC4 buffer
+ DFE_FL_BB_DDUC_TESTGEN_4,
+ /// TESTGEN for DDUC5 buffer
+ DFE_FL_BB_DDUC_TESTGEN_5,
+ /// TESTGEN for DDUC6 buffer
+ DFE_FL_BB_DDUC_TESTGEN_6,
+ /// TESTGEN for DDUC7 buffer
+ DFE_FL_BB_DDUC_TESTGEN_7,
+
+ /// TESTGEN for AID A buffer
+ DFE_FL_BB_AID_TESTGEN_A = 8,
+ /// TESTGEN for AID B buffer
+ DFE_FL_BB_AID_TESTGEN_B = 9,
+
+ DFE_FL_BB_MAX_TESTGENS = 10
+} DfeFl_BbTestGenDev;
+
+/** @brief BB Test Signal Generation ramp mode
+ */
+typedef enum
+{
+ /// LFSR
+ DFE_FL_BB_TESTGEN_RAMP_MODE_LFSR = 0,
+ /// RAMP
+ DFE_FL_BB_TESTGEN_RAMP_MODE_RAMP = 1
+} DfeFl_BbTestGenRampMode;
+
+/** @brief BB checksum device
+ */
+typedef enum
+{
+ /// CHKSUM for DDUC0 buffer
+ DFE_FL_BB_DDUC_CHKSUM_0 = 0,
+ /// CHKSUM for DDUC1 buffer
+ DFE_FL_BB_DDUC_CHKSUM_1,
+ /// CHKSUM for DDUC2 buffer
+ DFE_FL_BB_DDUC_CHKSUM_2,
+ /// CHKSUM for DDUC3 buffer
+ DFE_FL_BB_DDUC_CHKSUM_3,
+ /// CHKSUM for DDUC4 buffer
+ DFE_FL_BB_DDUC_CHKSUM_4,
+ /// CHKSUM for DDUC5 buffer
+ DFE_FL_BB_DDUC_CHKSUM_5,
+ /// CHKSUM for DDUC6 buffer
+ DFE_FL_BB_DDUC_CHKSUM_6,
+ /// CHKSUM for DDUC7 buffer
+ DFE_FL_BB_DDUC_CHKSUM_7,
+
+ /// CHKSUM for AID A buffer
+ DFE_FL_BB_AID_CHKSUM_A = 8,
+ /// CHKSUM for AID B buffer
+ DFE_FL_BB_AID_CHKSUM_B = 9,
+
+ DFE_FL_BB_MAX_CHKSUMS = 10
+} DfeFl_BbChksumDev;
+
+/** @brief BB checksum return mode */
+typedef enum
+{
+ /// BB checksum return checksum value
+ DFE_FL_BB_CHKSUM_MODE_RETURN_CHKSUM = 0,
+ /// BB checksum return latency value
+ DFE_FL_BB_CHKSUM_MODE_RETURN_LATENCY
+} DfeFl_BbChksumMode;
+
+/** @brief data mode for Tx/Rx TDD
+ */
+typedef enum
+{
+ /// TX: UL data passthru unchanged
+ DFE_FL_BB_TXTDD_DATAMODE_PASSTHRU = 0,
+ /// TX: UL data is zeroed and buffer memory stalled
+ DFE_FL_BB_TXTDD_DATAMODE_ZEROED = 1,
+
+ /// RX: DL data is zeroed at notch filter input
+ DFE_FL_BB_RXTDD_DATAMODE_ZEROED_AT_NOTCHFILETR_INPUT = 0,
+ /// RX: DL data is zeroed at formatter
+ DFE_FL_BB_RXTDD_DATAMODE_ZEROED_AT_FORMATTER = 1,
+ /// RX: DL data is zeroed at input of BB and buffer memory stalled
+ DFE_FL_BB_RXTDD_DATAMODE_ZEROED_AT_BUFFER_INPUT = 2
+} DfeFl_BbTddDataMode;
+
+/** @brief BB power meter enable mode
+ */
+typedef enum
+{
+ /// power meter is off
+ DFE_FL_BB_POWMETR_OFF = 0,
+ /// run one interval and then stop per sync
+ DFE_FL_BB_POWMETR_SINGLE_POWER_MEASUREMENT,
+ /// run multi intervals and then stop per sync
+ DFE_FL_BB_POWMETR_SINGLE_POWER_UPDATE_INTERVAL,
+ /// run continuouslly, restart per sync
+ DFE_FL_BB_POWMETR_CONTINUOUS_POWER_MESURE
+} DfeFl_BbPowMtrEnable;
+/** @brief BB power meter result or output format
+ */
+typedef enum
+{
+ /// float format, 10.16e6
+ DFE_FL_BB_POWMTR_OUTFMT_FLOAT_10P16E6 = 0,
+ /// starting from 0, in 0.1dB unit step
+ DFE_FL_BB_POWMTR_OUTFMT_STEP_0P1DB = 2
+} DfeFl_BbPowMtrOutFormat;
+/** @brief BB power meter input source
+ */
+typedef enum
+{
+ /// at BB input
+ /// tx: before tx gain
+ /// rx: before notch filter
+ DFE_FL_BB_POWMTR_INSRC_INPUT = 0,
+ /// at BB output
+ /// tx: after circular clipper
+ /// rx: after beAGC
+ DFE_FL_BB_POWMTR_INSRC_OUTPUT,
+ /// at tx gain output
+ DFE_FL_BB_POWMTR_INSRC_TX_GAIN_OUTPUT = 2,
+ /// at rx notch filter output
+ DFE_FL_BB_POWMTR_INSRC_RX_FILTER_OUTPUT = 2
+} DfeFl_BbPowMtrInSource;
+/** @brief BB power meter tdd mode
+ */
+typedef enum
+{
+ /// tdd mode disabled
+ DFE_FL_BB_POWMTR_TDDMODE_DISABLED = 0,
+ /// txpm: halt when UL period
+ DFE_FL_BB_POWMTR_TDDMODE_TX_HALT_UL = 1,
+ /// rxpm: halt when DL period
+ DFE_FL_BB_POWMTR_TDDMODE_RX_HALT_DL = 1,
+ /// txpm: reset when UL period
+ DFE_FL_BB_POWMTR_TDDMODE_TX_RESET_UL = 2,
+ /// rxpm: reset when DL period
+ DFE_FL_BB_POWMTR_TDDMODE_RX_RESET_DL = 2
+} DfeFl_BbPowMtrTddMode;
+
+/**
+ * @}
+ */
+
+/**
+ * @addtogroup DFE_FL_BB_DATASTRUCT
+ * @{
+ */
+
+/** @brief argument for runtime control,
+ * DFE_FL_BB_CMD_CFG_LOOPBACK
+ * DFE_FL_BB_QUERY_LOOPBACK_CFG
+ */
+typedef struct
+{
+ /// BB buf loopback, dduc0 to dduc1
+ uint32_t duc0ToDdc1;
+ /// BB buf loopback, dduc1 to dduc2
+ uint32_t duc1ToDdc2;
+ /// BB buf loopback, dduc0 to dduc3
+ uint32_t duc0ToDdc3;
+ /// BB buf loopback, dduc3 to dduc4
+ uint32_t duc3ToDdc4;
+ /// BB buf loopback, dduc2 to dduc5
+ uint32_t duc2ToDdc5;
+ /// BB buf loopback, dduc1 to dduc6
+ uint32_t duc1ToDdc6;
+ /// BB buf loopback, dduc0 to dduc7
+ uint32_t duc0ToDdc7;
+} DfeFl_BbLoopbackConfig;
+
+/** @brief argument for runtime control,
+ * DFE_FL_BB_CMD_CFG_CAPBUFF
+ * DFE_FL_BB_QUERY_CAPBUFF_CFG
+ */
+typedef struct
+{
+#ifdef _BIG_ENDIAN
+/// BIG ENDIAN format
+ /// rsvd1
+ uint32_t rsvd1 : 16;
+ /// axc# or buf# for single mode
+ uint32_t testCbAxc : 8;
+ /// rsvd0
+ uint32_t rsvd0 : 2;
+ /// testbus probe
+ uint32_t testCbCtrl : 6;
+#else
+/// LITTLE ENDIAN format
+ /// testbus probe
+ uint32_t testCbCtrl : 6;
+ /// rsvd0
+ uint32_t rsvd0 : 2;
+ /// axc# or buf# for single mode
+ uint32_t testCbAxc : 8;
+ /// rsvd1
+ uint32_t rsvd1 : 16;
+#endif
+} DfeFl_BbCapBuffConfig;
+
+/** @brief argument for runtime control,
+ * DFE_FL_BB_CMD_CFG_TESTGEN
+ * DFE_FL_BB_QUERY_TESTGEN_CFG
+ */
+typedef struct
+{
+ /// test gen device
+ DfeFl_BbTestGenDev tgDev;
+ /// only valid for AID
+ uint32_t testEnable;
+ /// enable data generation
+ uint32_t genData;
+ /// enbale frame generation
+ uint32_t genFrame;
+ /// ramp (1), or LFSR (0)
+ DfeFl_BbTestGenRampMode rampMode;
+ /// seed
+ uint32_t seed;
+ /// number of clocks per frame minus 1
+ uint32_t frameLenM1;
+ /// ramp starting value
+ uint32_t rampStart;
+ /// ramp stop value
+ uint32_t rampStop;
+ /// ramp slop value
+ uint32_t slope;
+ /// 0 = generate data forever, n = generate data for n clock cycles
+ uint32_t genTimer;
+ /// number of data bits inverted (read-only)
+ uint32_t numDataBits;
+} DfeFl_BbTestGenConfig;
+
+/** @brief argument for runtime control,
+ * DFE_FL_BB_CMD_SET_TESTGEN_SSEL
+ * DFE_FL_BB_QUERY_TESTGEN_SSEL
+ */
+typedef struct
+{
+ /// test gen device
+ DfeFl_BbTestGenDev tgDev;
+ /// sync select
+ uint32_t ssel;
+} DfeFl_BbTestGenSsel;
+
+/** @brief argument for runtime control,
+ * DFE_FL_BB_CMD_CFG_CHKSUM
+ */
+typedef struct
+{
+ /// checksum device
+ uint32_t chksumDev;
+ /// checksum mode
+ uint32_t chksumMode;
+ /// latency mode config
+ struct
+ {
+ /// stable length
+ uint32_t stableLen;
+ /// signal length
+ uint32_t signalLen;
+ /// channel select
+ uint32_t chanSel;
+ } latencyMode;
+} DfeFl_BbChksumConfig;
+
+/** @brief argument for runtime control,
+ * DFE_FL_BB_CMD_SET_CHKSUM_SSEL
+ */
+typedef struct
+{
+ /// checksum device
+ uint32_t chksumDev;
+ /// sync selection
+ uint32_t ssel;
+} DfeFl_BbChksumSsel;
+
+/** @brief argument for runtime control,
+ * DFE_FL_BB_QUERY_CHKSUM_RESULT
+ */
+typedef struct
+{
+ /// checksum device
+ uint32_t chksumDev;
+ /// result
+ uint32_t result;
+} DfeFl_BbChksumResult;
+
+/** @brief argument for runtime control,
+ * DFE_FL_BB_CMD_CFG_CT_UL_SYNC_STROBE
+ * DFE_FL_BB_QUERY_CT_UL_SYNC_STROBE
+ */
+typedef struct
+{
+ /// carrier type
+ uint32_t ct;
+ /// UL sync strobe
+ uint32_t strobe;
+} DfeFl_BbCarrierTypeUlSyncStrobeConfig;
+
+/** @brief argument for runtime control,
+ * DFE_FL_BB_CMD_CFG_AID_ULSTROBE_DLY
+ * DFE_FL_BB_QUERY_AID_ULSTROBE_DLY
+ */
+typedef struct
+{
+ /// carrier type
+ uint32_t ct;
+ /// UL strobe delay
+ uint32_t dly;
+} DfeFl_BbAidUlStrobeDelayConfig;
+
+/** @brief argument for runtime control,
+ * DFE_FL_BB_CMD_CFG_TXIF_AXC
+ */
+typedef struct
+{
+ /// Per antenna carrier index into buffer memory the carrier is assigned to
+ uint32_t bufferIndex;
+ /// Per antenna carrier buffer the carrier is assigned to
+ uint32_t bufferNum;
+ /// Per antenna carrier selection of 1 of 16 power meter configurations the carrier is assigned to.
+ uint32_t pmConfigSel;
+ /// Per antenna carrier enable of power meter function
+ uint32_t pmEn;
+ /// Per antenna carrier enable of the circular clipper function
+ uint32_t clEn;
+ /// Per antenna carrier enable of the gain function (otherwise unity gain)
+ uint32_t gainEn;
+ /// Per antenna carrier enable. When disabled carrier is ignored
+ uint32_t axcValid;
+ /// Per antenna carrier 1/T value to be used when circular clipper is enabled.
+ uint32_t cl1OverT;
+ /// Per antenna carrier antenna calibration select.
+ uint32_t antcalSel;
+ /// Per antenna carrier antenna calibration enable
+ uint32_t antcalEn;
+ /// Per antenna carrier enable of autoCP mode.
+ uint32_t autocpEn;
+ /// Per antenna carrier selection of autoCP timer (one of two choices).
+ uint32_t autocpSel;
+} DfeFl_BbTxifAxc;
+typedef struct
+{
+ /// total AxCs for array of txifAxc[]
+ uint32_t numAxCs;
+ struct {
+ /// axc id#
+ uint32_t axc;
+ /// per antenna carrier config
+ DfeFl_BbTxifAxc txif;
+ } txifAxc[DFE_FL_BB_ANTENNA_MAX_AXCS];
+} DfeFl_BbTxifAxcConfig;
+
+/** @brief argument for runtime control,
+ * DFE_FL_BB_CMD_CFG_RXIF_AXC
+ */
+typedef struct
+{
+ /// Per antenna carrier index into buffer memory the carrier is assigned to
+ uint32_t bufferIndex;
+ /// Per antenna carrier buffer the carrier is assigned to
+ uint32_t bufferNum;
+ /// Per antenna carrier assignment of the carrier type.
+ uint32_t carrierType;
+ /// Per antenna carrier selection of AGC mode.
+ uint32_t beagcMode;
+ /// Per antenna carrier enable. When disabled carrier is ignored even if there is a slot assigned to it.
+ uint32_t axcValid;
+ /// Per antenna carrier selection of 1 of 16 power meter configurations the carrier is assigned to.
+ uint32_t pmConfigSel;
+ /// Per antenna carrier enable of power meter function
+ uint32_t pmEn;
+ /// Per antenna carrier selection of input notch filter configuration
+ uint32_t notchEn;
+ /// Per antenna carrier selection of 16 bit output packing (instead of 32 bit format)
+ uint32_t outPacked;
+ /// Per antenna carrier selection of number of floating point bits when in float mode (set by fixedorfloat)
+ uint32_t outFloatMode;
+ /// Per antenna carrier selection of floating point mode for output
+ uint32_t fixedOrFloat;
+ /// Per antenna carrier selection of number of mantissa bits +1 the output will be rounded to.
+ uint32_t outNumBits;
+ /// Selects which of 16 antenna calibration configurations to use for the carrier
+ uint32_t antcalSel;
+ /// Per antenna carrier enable of antenna calibration noise enable
+ uint32_t antcalEn;
+ /// Per antenna carrier power backoff value used when in power managed gain control mode
+ uint32_t beagcPowerBackoff;
+
+ /// Per antenna carrier force output to zero when tdd is in DL
+ uint32_t tdd0;
+ /// Per antenna carrier number of t3 intervals to run gain loop. 0=forever
+ uint32_t beagcT3ActvCnt;
+ /// Per antenna carrier selection of 1 of 8 beagc loop configurations to be used when in beagc mode
+ uint32_t beagcConfigSel;
+ /// Per antenna carrier t1 interval when in beagc closed loop gain mode
+ uint32_t beagcT1Interval;
+ /// Per antenna carrier t2 interval when in beagc closed loop gain mode
+ uint32_t beagcT2Interval;
+} DfeFl_BbRxifAxc;
+typedef struct
+{
+ /// total AxCs for array of rxifAxc[]
+ uint32_t numAxCs;
+ struct {
+ /// axc id#
+ uint32_t axc;
+ /// per antenna carrier config
+ DfeFl_BbRxifAxc rxif;
+ } rxifAxc[DFE_FL_BB_ANTENNA_MAX_AXCS];
+} DfeFl_BbRxifAxcConfig;
+
+/** @brief argument for runtime control,
+ * DFE_FL_BB_CMD_UPD_TXIF_AXC_GAIN
+ */
+typedef struct
+{
+ /// number of AxCs whose gains need updating
+ uint32_t numAxCs;
+ /// axc gain update table
+ struct
+ {
+ /// axc id#
+ uint32_t axc;
+ /// real part gain word for the axc
+ uint32_t gainI;
+ /// image part gain word for the axc
+ uint32_t gainQ;
+ } axcGain[DFE_FL_BB_ANTENNA_MAX_AXCS];
+} DfeFl_BbTxGainConfig;
+
+/** @brief argument for runtime control,
+ * DFE_FL_BB_QUERY_TXGAIN_INTR_STATUS
+ * DFE_FL_BB_QUERY_RXGAIN_INTR_STATUS
+ * DFE_FL_BB_QUERY_TXGAIN_UPDATE_STATUS
+ * DFE_FL_BB_QUERY_RXGAIN_UPDATE_STATUS
+ * DFE_FL_BB_CMD_SET_RXGAIN_SSEL
+ * DFE_FL_BB_CMD_SET_TXGAIN_SSEL
+ * DFE_FL_BB_QUERY_TXGAIN_SSEL
+ * DFE_FL_BB_QUERY_RXGAIN_SSEL
+ */
+typedef struct
+{
+ /// carrier type
+ uint32_t ct;
+ /// set/get value
+ uint32_t data;
+} DfeFl_BbTxRxGainCarrierTypeData;
+
+
+/** @brief argument for runtime control,
+ * DFE_FL_BB_CMD_CFG_TXTDD
+ * DFE_FL_BB_CMD_CFG_RXTDD
+ * DFE_FL_BB_QUERY_TXTDD_CFG
+ * DFE_FL_BB_QUERY_RXTDD_CFG
+ */
+typedef struct
+{
+ /// enable
+ uint32_t enable;
+ /// data mode
+ DfeFl_BbTddDataMode dataMode;
+ /// carrier type
+ uint32_t carrierType;
+ /// delay from sync
+ uint32_t syncDly;
+ /// DL1 interval
+ uint32_t dl1Interval;
+ /// UL1 interval
+ uint32_t ul1Interval;
+ /// DL2 interval
+ uint32_t dl2Interval;
+ /// UL2 interval
+ uint32_t ul2Interval;
+ /// DL3 interval
+ uint32_t dl3Interval;
+ /// UL3 interval
+ uint32_t ul3Interval;
+} DfeFl_BbTddConfig;
+
+
+/** @brief argument for runtime control,
+ * DFE_FL_BB_CMD_CFG_TXPM
+ * DFE_FL_BB_CMD_CFG_RXPM
+ * DFE_FL_BB_QUERY_TXPM_CFG
+ * DFE_FL_BB_QUERY_RXPM_CFG
+ */
+typedef struct
+{
+ /// power meter Id
+ uint32_t pmId;
+ /// enable power meter function
+ DfeFl_BbPowMtrEnable enable;
+ /// result output format
+ DfeFl_BbPowMtrOutFormat outFormat;
+ /// carrier type
+ uint32_t countSource;
+ /// power meter input source
+ DfeFl_BbPowMtrInSource inSource;
+ /// tdd mode
+ DfeFl_BbPowMtrTddMode tddMode;
+ /// delay from sync
+ uint32_t syncDly;
+ /// meter interval
+ uint32_t interval;
+ /// integration period
+ uint32_t intgPd;
+ /// count of measurements, i.e. count of intervals
+ uint32_t pwrUpdate;
+ /// for RXPM only, max dB value assuming full power of power interval
+ uint32_t maxDb;
+} DfeFl_BbPowerMeterConfig;
+
+/** @brief argument for runtime control,
+ * DFE_FL_BB_CMD_SET_TXPM_SSEL
+ * DFE_FL_BB_CMD_SET_RXPM_SSEL
+ * DFE_FL_BB_QUERY_TXPM_SSEL
+ * DFE_FL_BB_QUERY_RXPM_SSEL
+ */
+typedef struct
+{
+ /// power meter Id
+ uint32_t pmId;
+ /// sync selection
+ uint32_t ssel;
+} DfeFl_BbPowerMeterSsel;
+
+/** @brief argument for runtime control,
+ * DFE_FL_BB_CMD_DIS_TXPM_UPDATE
+ * DFE_FL_BB_CMD_DIS_RXPM_UPDATE
+ * DFE_FL_BB_QUERY_DIS_TXPM_UPDATE
+ * DFE_FL_BB_QUERY_DIS_RXPM_UPDATE
+ */
+typedef struct
+{
+ /// power meter Id
+ uint32_t pmId;
+ /// disable update
+ uint32_t disableUpdate;
+} DfeFl_BbDisablePowMterUpdateConfig;
+
+
+/** @brief argument for runtime control,
+ * DFE_FL_BB_QUERY_TXPM_INTR_STATUS
+ * DFE_FL_BB_QUERY_RXPM_INTR_STATUS
+ */
+typedef struct
+{
+ /// power meter Id
+ uint32_t pmId;
+ /// complete status
+ uint32_t status;
+} DfeFl_BbPowMtrIntrStatus;
+
+/** @brief argument for runtime control,
+ * DFE_FL_BB_QUERY_TXPM_RESULT
+ * DFE_FL_BB_QUERY_RXPM_RESULT
+ */
+typedef struct
+{
+ /// power meter Id
+ uint32_t pmId;
+ /// peak power main value
+ uint32_t peakPower;
+ /// peak power extended value
+ uint32_t peakPower_extend;
+ /// RMS power main value
+ uint32_t rmsPower;
+ /// RMS power extended value
+ uint32_t rmsPower_extend;
+} DfeFl_BbPowMtrResult;
+
+/** @brief argument for runtime control,
+ * DFE_FL_BB_CMD_CFG_ANTCAL_GLOBAL
+ * DFE_FL_BB_QUERY_ANTCAL_GLOBAL_CFG
+ */
+typedef struct
+{
+ /// tx carrier type selection
+ uint32_t txCarrierTypeSel;
+ /// rx carrier type selection
+ uint32_t rxCarrierTypeSel;
+ /// tx sync selection
+ uint32_t txSsel;
+ /// rx sync selection
+ uint32_t rxSsel;
+ /// enable antenna calibartion
+ uint32_t enable;
+ /// number of samples to collect noise correlation values
+ uint32_t interval;
+} DfeFl_BbAntCalGlobalConfig;
+
+/** @brief argument for runtime control,
+ * DFE_FL_BB_CMD_CFG_ANTCAL
+ * DFE_FL_BB_QUERY_ANTCAL_CFG
+ */
+typedef struct
+{
+ /// antenna calibration device
+ uint32_t antcal;
+ /// Antenna Calibration PN sequencer Initial value
+ uint32_t pnInit;
+ /// Antenna Calibration PN sequencer tap configuration
+ uint32_t pnTapConfig;
+ /// Antenna Calibration TX noise level
+ uint32_t txNoise;
+ /// Antenna Calibration RX correlation delay in samples
+ uint32_t rxCorrDelay;
+ /// Antenna Calibration RX oversampled. When 1 AxC is 2x oversampled
+ uint32_t rxOverSample;
+} DfeFl_BbAntCalConfig;
+
+/** @brief argument for runtime control,
+ * DFE_FL_BB_QUERY_GENERAL_INTR_STATUS
+ */
+typedef struct
+{
+ /// general interrupt
+ uint32_t intr;
+ /// result
+ uint32_t result;
+} DfeFl_BbGeneralIntrQuery;
+
+/** @brief argument for runtime control,
+ * DFE_FL_BB_CMD_ENB_GENERAL_INTRGRP
+ * DFE_FL_BB_CMD_DIS_GENERAL_INTRGRP
+ * DFE_FL_BB_CMD_CLR_GENERAL_INTRGRP_STATUS
+ * DFE_FL_BB_CMD_SET_FORCE_GENERAL_INTRGRP
+ * DFE_FL_BB_CMD_CLR_FORCE_GENERAL_INTRGRP
+ * DFE_FL_BB_QUERY_GENERAL_INTRGRP_STATUS
+ */
+typedef struct
+{
+ /// BB general interrupt, TXPM_LDERR
+ uint32_t txpmLoadErr;
+ /// BB general interrupt, RXPM_LDERR
+ uint32_t rxpmLoadErr;
+ /// BB general interrupt, ANTCAL
+ uint32_t antcal;
+ /// BB general interrupt, RXNOTCH_DONE
+ uint32_t rxNotchDone;
+ /// BB general interrupt, RXNOTCH_ERR
+ uint32_t rxNotchErr;
+
+ /// BB general interrupt, BUFMEM_OUF (overflow/underflow)
+ uint32_t bufErr[8];
+ /// BB general interrupt, RXAID_SYNCERR
+ uint32_t rxaidSyncErr;
+ /// BB general interrupt, TXAID_UDF (under flow)
+ uint32_t txaidUnderflow;
+ /// BB general interrupt, TXAID_OVF (over flow)
+ uint32_t txaidOverflow;
+ /// BB general interrupt, JESDRX_SYNCERR
+ uint32_t jesdrxSyncErr;
+ /// BB general interrupt, JESDTX_UDF (under flow)
+ uint32_t jesdtxUnderflow;
+ /// BB general interrupt, JESDTX_OVF (over flow)
+ uint32_t jesdtxOverflow;
+} DfeFl_BbGeneralIntrGroup;
+
+
+/** @brief argument for runtime control,
+ * DFE_FL_BB_CMD_UPD_RXGAIN
+ */
+typedef struct
+{
+ /// number of AxCs whose gains need updating
+ uint32_t numAxCs;
+ /// axc gain update table
+ struct
+ {
+ /// axc id#
+ uint32_t axc;
+ /// integer part gain word for the axc
+ uint32_t gainInteger;
+ /// fractional part gain word for the axc
+ uint32_t gainFraction;
+ } axcGain[DFE_FL_BB_ANTENNA_MAX_AXCS];
+} DfeFl_BbRxGainConfig;
+
+
+/** @brief argument for runtime control,
+ * DFE_FL_BB_CMD_CFG_BEAGC_GLOBAL
+ * DFE_FL_BB_QUERY_BEAGC_GLOBAL_CFG
+ */
+typedef struct
+{
+ /// When set beagc gain loop emphasizes saturation by incrementing sat counter by 1 when I or Q is sat
+ uint32_t loop_config_sat;
+ /// TDD timer configuration for beAGC. 0:tdd halt on DL, 1: tdd reset on DL
+ uint32_t tdd_config;
+} DfeFl_BbBeagcGlobalConfig;
+
+/** @brief argument for runtime control,
+ * DFE_FL_BB_CMD_CFG_BEAGC
+ * DFE_FL_BB_QUERY_BEAGC_CFG
+ */
+typedef struct
+{
+ /// beagc device id
+ uint32_t beagc;
+ /// Select which buffer sync is the source of the interval counter for configuration 0 in closed loop mode.
+ uint32_t intervalSource;
+ /// master t3 interval
+ uint32_t t3Interval;
+ /// enable/disbale tdd mode
+ uint32_t tdd_enable;
+ /// beagc control loop configuration threshold value of AGC unsigned
+ uint32_t thresh;
+ /// beagc control loop configuration zero_mask masks lower 4 bits for zero count, a 0 will mask off zero calculation
+ uint32_t zeroMask;
+ /// beagc control loop configuration zero count threshold
+ uint32_t zeroCountThresh;
+ /// beagc control loop configuration saturation count threshold;
+ uint32_t satCountThresh;
+ /// beagc control loop configuration shift value for below threshold. 0=shift of 2 ... 15=shift of 17
+ uint32_t dBelow;
+ /// beagc control loop configuration shift value for above threshold. 0=shift of 2 ... 15=shift of 17
+ uint32_t dAbove;
+ /// beagc control loop configuration shift value for saturation case. 0=shift of 2 ... 15=shift of 17
+ uint32_t dSat;
+ /// beagc control loop configuration shift value for zero case. 0=shift of 2 ... 15=shift of 17
+ uint32_t dZero;
+ /// beagc control loop configuration maximum allowed gain adjustment value. Adjustment stops at g(k)=G + amax Amax format is signed (1,16,7)
+ uint32_t amax;
+ /// beagc control loop configuration minimum allowed gain adjustment value. Adjustment stops at g(k)=G + amin. Amin format is signed (1,16,7)
+ uint32_t amin;
+} DfeFl_BbBeagcConfig;
+
+/** @brief argument for runtime control,
+ * DFE_FL_BB_CMD_SET_BEAGC_SSEL
+ * DFE_FL_BB_QUERY_BEAGC_SSEL
+ */
+typedef struct
+{
+ /// beagc device id
+ uint32_t beagc;
+ /// sync selection
+ uint32_t ssel;
+} DfeFl_BbBeagcSsel;
+
+/** @brief argument for runtime control,
+ * DFE_FL_BB_CMD_CFG_RXNOTCH_GLOBAL
+ * DFE_FL_BB_QUERY_RXNOTCH_GLOBAL_CFG
+ */
+typedef struct
+{
+ /// carrier type
+ uint32_t carrierType;
+ /// tdd mode
+ uint32_t tddMode;
+} DfeFl_BbRxNotchGlobalConfig;
+
+/** @brief argument for runtime control,
+ * DFE_FL_BB_CMD_CFG_RXNOTCH
+ * DFE_FL_BB_QUERY_RXNOTCH_CFG
+ */
+typedef struct
+{
+ /// axc Id
+ uint32_t axc;
+ /// filter mode
+ uint32_t mode;
+ /// filter1 tap select
+ uint32_t filter1;
+ /// filter2 tap select
+ uint32_t filter2;
+ /// filter3 tap select
+ uint32_t filter3;
+ /// filter4 tap select
+ uint32_t filter4;
+ /// Notch filter 0
+ uint32_t tap0I;
+ uint32_t tap0Q;
+ uint32_t tap0Width;
+ /// Notch filter 1
+ uint32_t tap1I;
+ uint32_t tap1Q;
+ uint32_t tap1Width;
+} DfeFl_BbRxNotch;
+
+/** @brief AID DL translate
+ */
+typedef struct
+{
+#ifdef _BIG_ENDIAN
+ uint32_t rsvd0 : 22;
+ uint32_t strobeType : 3;
+ uint32_t axc : 7;
+#else
+ uint32_t axc : 7;
+ uint32_t strobeType : 3;
+ uint32_t rsvd0 : 22;
+#endif
+} DfeFl_BbAidDlXlate;
+
+/** @brief AID UL translate
+ */
+typedef struct
+{
+#ifdef _BIG_ENDIAN
+ uint32_t rsvd1 : 20;
+ uint32_t carrierType : 4;
+ uint32_t rsvd0 : 2;
+ uint32_t axc : 6;
+#else
+ uint32_t axc : 6;
+ uint32_t rsvd0 : 2;
+ uint32_t carrierType : 4;
+ uint32_t rsvd1 : 20;
+#endif
+} DfeFl_BbAidUlXlate;
+
+/** @brief TXIF slot map
+ */
+typedef struct
+{
+#ifdef _BIG_ENDIAN
+ uint32_t rsvd0 : 20;
+ uint32_t carrierType : 4;
+ uint32_t unassigned : 1;
+ uint32_t axc : 7;
+#else
+ uint32_t axc : 7;
+ uint32_t unassigned : 1;
+ uint32_t carrierType : 4;
+ uint32_t rsvd0 : 20;
+#endif
+} DfeFl_BbTxifSlot;
+
+/** @brief RXIF slot map
+ */
+typedef struct
+{
+#ifdef _BIG_ENDIAN
+ uint32_t rsvd0 : 25;
+ uint32_t unassigned : 1;
+ uint32_t axc : 6;
+#else
+ uint32_t axc : 6;
+ uint32_t unassigned : 1;
+ uint32_t rsvd0 : 25;
+#endif
+} DfeFl_BbRxifSlot;
+
+/** @brief overlay register pointer to BB instance
+ */
+typedef CSL_DFE_BB_REGS *DfeFl_BbRegsOvly;
+
+/** @brief a BaseBand (BB) Object of Digital radio Front End (DFE) */
+typedef struct
+{
+ /// handle to DFE global
+ DfeFl_Handle hDfe;
+
+ /// pointer to register base address of a BB instance
+ DfeFl_BbRegsOvly regs;
+
+ /// This is the instance of BB being referred to by this object
+ DfeFl_InstNum perNum;
+
+} DfeFl_BbObj;
+
+/** @brief handle pointer to BB object
+ */
+typedef DfeFl_BbObj *DfeFl_BbHandle;
+
+/**
+ * @}
+ */
+
+/**
+ * @addtogroup DFE_FL_BB_FUNCTION
+ * @{
+ */
+
+DfeFl_BbHandle dfeFl_BbOpen
+(
+ DfeFl_Handle hDfe,
+ DfeFl_BbObj *pDfeBbObj,
+ DfeFl_InstNum bbNum,
+ DfeFl_Status *pStatus
+);
+
+DfeFl_Status dfeFl_BbClose(DfeFl_BbHandle hDfeBb);
+
+DfeFl_Status dfeFl_BbHwControl
+(
+ DfeFl_BbHandle hDfeBb,
+ DfeFl_BbHwControlCmd ctrlCmd,
+ void *arg
+);
+
+DfeFl_Status dfeFl_BbGetHwStatus
+(
+ DfeFl_BbHandle hDfeBb,
+ DfeFl_BbHwStatusQuery queryId,
+ void *arg
+);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _DFE_FL_BB_H_ */
diff --git a/packages/ti/drv/dfe/dfe_fl_bbAux.h b/packages/ti/drv/dfe/dfe_fl_bbAux.h
--- /dev/null
@@ -0,0 +1,5905 @@
+/********************************************************************
+* Copyright (C) 2012-2013 Texas Instruments Incorporated.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+*/
+
+/** @file dfe_fl_bbAux.h
+ *
+ * @path $(CSLPATH)\inc
+ *
+ * @brief Header file for functional layer of DFE_BB CSL
+ *
+ * Description
+ * - Function level symbolic constants, enumerations, structure definitions
+ * and function prototype declarations
+ *
+ */
+#ifndef _DFE_FL_BBAUX_H_
+#define _DFE_FL_BBAUX_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <ti/csl/csl.h>
+#include <ti/drv/dfe/dfe_fl_bb.h>
+
+/** ============================================================================
+ * @n@b dfeFl_BbConfigInits
+ *
+ * @b Description
+ * @n [add content]
+ *
+ * @b Arguments
+ * @verbatim
+ hDfeBb [add content]
+ arg [add content]
+ @endverbatim
+ *
+ * <b> Return Value </b> None
+ *
+ * <b> Pre Condition </b>
+ * @n [add content]
+ *
+ * <b> Post Condition </b>
+ * @n [add content]
+ *
+ * @b Reads
+ * @n None
+ *
+ * @b Writes
+ * @n see below,
+ * DFE_BB_CFG13_REG_INITS_CLK_GATE
+ * DFE_BB_CFG13_REG_CLEAR_DATA
+ * DFE_BB_CFG13_REG_INITS_STATE
+ * DFE_BB_CFG13_REG_INITS_SSEL
+ *
+ * @b Example
+ * @verbatim
+ [add content]
+ @endverbatim
+ * ===========================================================================
+ */
+CSL_IDEF_INLINE void
+dfeFl_BbConfigInits(DfeFl_BbHandle hDfeBb, DfeFl_SublkInitsConfig * arg)
+{
+ uint32_t data = hDfeBb->regs->cfg13;
+
+ CSL_FINS(data, DFE_BB_CFG13_REG_INITS_SSEL, arg->ssel);
+ CSL_FINS(data, DFE_BB_CFG13_REG_INITS_CLK_GATE, arg->initClkGate);
+ CSL_FINS(data, DFE_BB_CFG13_REG_INITS_STATE, arg->initState);
+ CSL_FINS(data, DFE_BB_CFG13_REG_CLEAR_DATA, arg->clearData);
+
+ hDfeBb->regs->cfg13 = data;
+}
+
+/** ============================================================================
+ * @n@b dfeFl_BbEnableAidLoopback
+ *
+ * @b Description
+ * @n [add content]
+ *
+ * @b Arguments
+ * @verbatim
+ hDfeBb [add content]
+ @endverbatim
+ *
+ * <b> Return Value </b> None
+ *
+ * <b> Pre Condition </b>
+ * @n [add content]
+ *
+ * <b> Post Condition </b>
+ * @n [add content]
+ *
+ * @b Reads
+ * @n None
+ *
+ * @b Writes
+ * @n cfg88.bit11
+ *
+ * @b Example
+ * @verbatim
+ [add content]
+ @endverbatim
+ * ===========================================================================
+ */
+CSL_IDEF_INLINE void
+dfeFl_BbEnableAidLoopback(DfeFl_BbHandle hDfeBb)
+{
+ uint32_t data = hDfeBb->regs->cfg88;
+
+ data |= 0x800u;
+
+ hDfeBb->regs->cfg88 = data;
+}
+
+/** ============================================================================
+ * @n@b dfeFl_BbDisableAidLoopback
+ *
+ * @b Description
+ * @n [add content]
+ *
+ * @b Arguments
+ * @verbatim
+ hDfeBb [add content]
+ @endverbatim
+ *
+ * <b> Return Value </b> None
+ *
+ * <b> Pre Condition </b>
+ * @n [add content]
+ *
+ * <b> Post Condition </b>
+ * @n [add content]
+ *
+ * @b Reads
+ * @n None
+ *
+ * @b Writes
+ * @n cfg88.bit11
+ *
+ * @b Example
+ * @verbatim
+ [add content]
+ @endverbatim
+ * ===========================================================================
+ */
+CSL_IDEF_INLINE void
+dfeFl_BbDisableAidLoopback(DfeFl_BbHandle hDfeBb)
+{
+ uint32_t data = hDfeBb->regs->cfg88;
+
+ data &= ~0x800u;
+
+ hDfeBb->regs->cfg88 = data;
+}
+
+/** ============================================================================
+ * @n@b dfeFl_BbGetAidLoopbackStatus
+ *
+ * @b Description
+ * @n [add content]
+ *
+ * @b Arguments
+ * @verbatim
+ hDfeBb [add content]
+ status [add content]
+ @endverbatim
+ *
+ * <b> Return Value </b> None
+ *
+ * <b> Pre Condition </b>
+ * @n [add content]
+ *
+ * <b> Post Condition </b>
+ * @n [add content]
+ *
+ * @b Reads
+ * @n None
+ *
+ * @b Writes
+ * @n None
+ *
+ * @b Example
+ * @verbatim
+ [add content]
+ @endverbatim
+ * ===========================================================================
+ */
+CSL_IDEF_INLINE void
+dfeFl_BbQueryAidLoopbackConfig(DfeFl_BbHandle hDfeBb, uint32_t *status)
+{
+ *status = CSL_FEXT(hDfeBb->regs->cfg88, DFE_BB_CFG88_REG_AID_IF_CONFIG);
+ *status &= (uint32_t)0x00000800;
+ *status >>= 11;
+}
+
+/** ============================================================================
+ * @n@b dfeFl_BbConfigLoopback
+ *
+ * @b Description
+ * @n [add content]
+ *
+ * @b Arguments
+ * @verbatim
+ hDfeBb [add content]
+ arg [add content]
+ @endverbatim
+ *
+ * <b> Return Value </b> None
+ *
+ * <b> Pre Condition </b>
+ * @n [add content]
+ *
+ * <b> Post Condition </b>
+ * @n [add content]
+ *
+ * @b Reads
+ * @n None
+ *
+ * @b Writes
+ * @n None
+ *
+ * @b Example
+ * @verbatim
+ [add content]
+ @endverbatim
+ * ===========================================================================
+ */
+CSL_IDEF_INLINE void
+dfeFl_BbConfigLoopback(DfeFl_BbHandle hDfeBb, DfeFl_BbLoopbackConfig * arg)
+{
+ uint32_t data=0;
+
+ data = (((arg->duc0ToDdc1) << 1) & 2)
+ | (((arg->duc1ToDdc2) << 2) & 4)
+ | (((arg->duc0ToDdc3) << 3) & 8)
+ | (((arg->duc3ToDdc4) << 4) & 16)
+ | (((arg->duc2ToDdc5) << 5) & 32)
+ | (((arg->duc1ToDdc6) << 6) & 64)
+ | (((arg->duc0ToDdc7) << 7) & 128);
+
+ hDfeBb->regs->cfg2 = data;
+}
+
+/** ============================================================================
+ * @n@b dfeFl_BbQueryLoopbackConfig
+ *
+ * @b Description
+ * @n [add content]
+ *
+ * @b Arguments
+ * @verbatim
+ hDfeBb [add content]
+ arg [add content]
+ @endverbatim
+ *
+ * <b> Return Value </b> None
+ *
+ * <b> Pre Condition </b>
+ * @n [add content]
+ *
+ * <b> Post Condition </b>
+ * @n [add content]
+ *
+ * @b Reads
+ * @n None
+ *
+ * @b Writes
+ * @n None
+ *
+ * @b Example
+ * @verbatim
+ [add content]
+ @endverbatim
+ * ===========================================================================
+ */
+CSL_IDEF_INLINE void
+dfeFl_BbQueryLoopbackConfig(DfeFl_BbHandle hDfeBb, DfeFl_BbLoopbackConfig * arg)
+{
+ uint32_t data;
+
+ data = hDfeBb->regs->cfg2;
+ arg->duc0ToDdc1 = (((data) & 2) >> 1);
+ arg->duc1ToDdc2 = (((data) & 4) >> 2);
+ arg->duc0ToDdc3 = (((data) & 8) >> 3);
+ arg->duc3ToDdc4 = (((data) & 16) >> 4);
+ arg->duc2ToDdc5 = (((data) & 32) >> 5);
+ arg->duc1ToDdc6 = (((data) & 64) >> 6);
+ arg->duc0ToDdc7 = (((data) & 128) >> 7);
+}
+
+/** ============================================================================
+ * @n@b dfeFl_BbConfigCapBuff
+ *
+ * @b Description
+ * @n [add content]
+ *
+ * @b Arguments
+ * @verbatim
+ hDfeBb [add content]
+ arg [add content]
+ @endverbatim
+ *
+ * <b> Return Value </b> None
+ *
+ * <b> Pre Condition </b>
+ * @n [add content]
+ *
+ * <b> Post Condition </b>
+ * @n [add content]
+ *
+ * @b Reads
+ * @n None
+ *
+ * @b Writes
+ * @n None
+ *
+ * @b Example
+ * @verbatim
+ [add content]
+ @endverbatim
+ * ===========================================================================
+ */
+CSL_IDEF_INLINE void
+dfeFl_BbConfigCapBuff(DfeFl_BbHandle hDfeBb, DfeFl_BbCapBuffConfig * arg)
+{
+ hDfeBb->regs->cfg1 = *(uint32_t *)arg;
+}
+
+/** ============================================================================
+ * @n@b dfeFl_BbQueryCapBuffConfig
+ *
+ * @b Description
+ * @n [add content]
+ *
+ * @b Arguments
+ * @verbatim
+ hDfeBb [add content]
+ arg [add content]
+ @endverbatim
+ *
+ * <b> Return Value </b> None
+ *
+ * <b> Pre Condition </b>
+ * @n [add content]
+ *
+ * <b> Post Condition </b>
+ * @n [add content]
+ *
+ * @b Reads
+ * @n None
+ *
+ * @b Writes
+ * @n None
+ *
+ * @b Example
+ * @verbatim
+ [add content]
+ @endverbatim
+ * ===========================================================================
+ */
+CSL_IDEF_INLINE void
+dfeFl_BbQueryCapBuffConfig(DfeFl_BbHandle hDfeBb, DfeFl_BbCapBuffConfig * arg)
+{
+ *(uint32_t *)arg = hDfeBb->regs->cfg1;
+}
+
+/** ============================================================================
+ * @n@b dfeFl_BbConfigTestGen
+ *
+ * @b Description
+ * @n [add content]
+ *
+ * @b Arguments
+ * @verbatim
+ hDfeBb [add content]
+ arg [add content]
+ @endverbatim
+ *
+ * <b> Return Value </b> None
+ *
+ * <b> Pre Condition </b>
+ * @n [add content]
+ *
+ * <b> Post Condition </b>
+ * @n [add content]
+ *
+ * @b Reads
+ * @n None
+ *
+ * @b Writes
+ * @n see below,
+ * DFE_BB_SIGNAL_GEN0_GEN_TIMER_REG_GEN_TIMER
+ * DFE_BB_SIGNAL_GEN0_RAMP_SLOPE_LO_REG_RAMP_SLOPE_15_0
+ * DFE_BB_SIGNAL_GEN0_RAMP_START_HI_REG_RAMP_START_31_16
+ * DFE_BB_SIGNAL_GEN0_RAMP_STOP_LO_REG_RAMP_STOP_15_0
+ * DFE_BB_GCCK_DDUC0_GENERAL_REG_RAMP_MODE
+ * DFE_BB_SIGNAL_GEN0_RAMP_SLOPE_HI_REG_RAMP_SLOPE_31_16
+ * DFE_BB_GCCK_DDUC0_GENERAL_REG_GEN_DATA
+ * DFE_BB_CK_SUMA_CTRL1_REG_AID_SIG_GEN_TEST_ENABLE
+ * DFE_BB_GCCK_DDUC0_GENERAL_REG_SEED
+ * DFE_BB_GCCK_DDUC0_GENERAL_REG_FRAME_LEN_M1
+ * DFE_BB_GCCK_DDUC0_GENERAL_REG_GEN_FRAME
+ * DFE_BB_SIGNAL_GEN0_RAMP_START_LO_REG_RAMP_START_15_0
+ * DFE_BB_SIGNAL_GEN0_RAMP_STOP_HI_REG_RAMP_STOP_31_16
+ *
+ * @b Example
+ * @verbatim
+ [add content]
+ @endverbatim
+ * ===========================================================================
+ */
+CSL_IDEF_INLINE void
+dfeFl_BbConfigTestGen(DfeFl_BbHandle hDfeBb, DfeFl_BbTestGenConfig * arg)
+{
+ uint32_t data;
+ volatile uint32_t *regs;
+
+ switch(arg->tgDev)
+ {
+ // TESTGEN for DDUC0 buffer
+ case DFE_FL_BB_DDUC_TESTGEN_0:
+ regs = &hDfeBb->regs->gcck_dduc0_general;
+ break;
+ // TESTGEN for DDUC1 buffer
+ case DFE_FL_BB_DDUC_TESTGEN_1:
+ regs = &hDfeBb->regs->gcck_dduc1_general;
+ break;
+ // TESTGEN for DDUC2 buffer
+ case DFE_FL_BB_DDUC_TESTGEN_2:
+ regs = &hDfeBb->regs->gcck_dduc2_general;
+ break;
+ // TESTGEN for DDUC3 buffer
+ case DFE_FL_BB_DDUC_TESTGEN_3:
+ regs = &hDfeBb->regs->gcck_dduc3_general;
+ break;
+ // TESTGEN for DDUC4 buffer
+ case DFE_FL_BB_DDUC_TESTGEN_4:
+ regs = &hDfeBb->regs->gcck_dduc4_general;
+ break;
+ // TESTGEN for DDUC5 buffer
+ case DFE_FL_BB_DDUC_TESTGEN_5:
+ regs = &hDfeBb->regs->gcck_dduc5_general;
+ break;
+ // TESTGEN for DDUC6 buffer
+ case DFE_FL_BB_DDUC_TESTGEN_6:
+ regs = &hDfeBb->regs->gcck_dduc6_general;
+ break;
+ // TESTGEN for DDUC7 buffer
+ case DFE_FL_BB_DDUC_TESTGEN_7:
+ regs = &hDfeBb->regs->gcck_dduc7_general;
+ break;
+
+ // TESTGEN for AID A buffer
+ case DFE_FL_BB_AID_TESTGEN_A:
+ regs = &hDfeBb->regs->gcck_aida_general;
+ break;
+ // TESTGEN for AID B buffer
+ case DFE_FL_BB_AID_TESTGEN_B:
+ regs = &hDfeBb->regs->gcck_aidb_general;
+ break;
+
+ default:
+ return;
+ }
+
+ // general
+ regs[0] = CSL_FMK(DFE_BB_GCCK_DDUC0_GENERAL_REG_GEN_DATA, arg->genData)
+ | CSL_FMK(DFE_BB_GCCK_DDUC0_GENERAL_REG_GEN_FRAME, arg->genFrame)
+ | CSL_FMK(DFE_BB_GCCK_DDUC0_GENERAL_REG_RAMP_MODE, arg->rampMode)
+ | CSL_FMK(DFE_BB_GCCK_DDUC0_GENERAL_REG_SEED, arg->seed)
+ | CSL_FMK(DFE_BB_GCCK_DDUC0_GENERAL_REG_FRAME_LEN_M1, arg->frameLenM1);
+ // ramp start
+ regs[1] = CSL_FMK(DFE_BB_SIGNAL_GEN0_RAMP_START_LO_REG_RAMP_START_15_0, arg->rampStart);
+ regs[2] = CSL_FMK(DFE_BB_SIGNAL_GEN0_RAMP_START_HI_REG_RAMP_START_31_16, arg->rampStart >> 16);
+ // ramp stop
+ regs[3] = CSL_FMK(DFE_BB_SIGNAL_GEN0_RAMP_STOP_LO_REG_RAMP_STOP_15_0, arg->rampStop);
+ regs[4] = CSL_FMK(DFE_BB_SIGNAL_GEN0_RAMP_STOP_HI_REG_RAMP_STOP_31_16, arg->rampStop >> 16);
+ // ramp slope
+ regs[5] = CSL_FMK(DFE_BB_SIGNAL_GEN0_RAMP_SLOPE_LO_REG_RAMP_SLOPE_15_0, arg->slope);
+ regs[6] = CSL_FMK(DFE_BB_SIGNAL_GEN0_RAMP_SLOPE_HI_REG_RAMP_SLOPE_31_16, arg->slope >> 16);
+ // gen timer
+ regs[7] = CSL_FMK(DFE_BB_SIGNAL_GEN0_GEN_TIMER_REG_GEN_TIMER, arg->genTimer);
+
+ // ssel
+ data = regs[-1];
+ if(arg->tgDev == DFE_FL_BB_AID_TESTGEN_A || arg->tgDev == DFE_FL_BB_AID_TESTGEN_B)
+ {
+ CSL_FINS(data, DFE_BB_CK_SUMA_CTRL1_REG_AID_SIG_GEN_TEST_ENABLE, arg->testEnable);
+ }
+ regs[-1] = data;
+
+}
+
+/** ============================================================================
+ * @n@b dfeFl_BbQueryTestGenConfig
+ *
+ * @b Description
+ * @n [add content]
+ *
+ * @b Arguments
+ * @verbatim
+ hDfeBb [add content]
+ arg [add content]
+ @endverbatim
+ *
+ * <b> Return Value </b> None
+ *
+ * <b> Pre Condition </b>
+ * @n [add content]
+ *
+ * <b> Post Condition </b>
+ * @n [add content]
+ *
+ * @b Reads
+ * @n see below,
+ * DFE_BB_GCCK_DDUC0_GENERAL_REG_RAMP_MODE
+ * DFE_BB_GCCK_DDUC0_GENERAL_REG_GEN_DATA
+ * DFE_BB_CK_SUMA_CTRL1_REG_AID_SIG_GEN_TEST_ENABLE
+ * DFE_BB_GCCK_DDUC0_GENERAL_REG_SEED
+ * DFE_BB_GCCK_DDUC0_GENERAL_REG_FRAME_LEN_M1
+ * DFE_BB_GCCK_DDUC0_GENERAL_REG_GEN_FRAME
+ *
+ * @b Writes
+ * @n None
+ *
+ * @b Example
+ * @verbatim
+ [add content]
+ @endverbatim
+ * ===========================================================================
+ */
+CSL_IDEF_INLINE void
+dfeFl_BbQueryTestGenConfig(DfeFl_BbHandle hDfeBb, DfeFl_BbTestGenConfig * arg)
+{
+ uint32_t data;
+ volatile uint32_t *regs;
+
+ switch(arg->tgDev)
+ {
+ // TESTGEN for DDUC0 buffer
+ case DFE_FL_BB_DDUC_TESTGEN_0:
+ regs = &hDfeBb->regs->gcck_dduc0_general;
+ break;
+ // TESTGEN for DDUC1 buffer
+ case DFE_FL_BB_DDUC_TESTGEN_1:
+ regs = &hDfeBb->regs->gcck_dduc1_general;
+ break;
+ // TESTGEN for DDUC2 buffer
+ case DFE_FL_BB_DDUC_TESTGEN_2:
+ regs = &hDfeBb->regs->gcck_dduc2_general;
+ break;
+ // TESTGEN for DDUC3 buffer
+ case DFE_FL_BB_DDUC_TESTGEN_3:
+ regs = &hDfeBb->regs->gcck_dduc3_general;
+ break;
+ // TESTGEN for DDUC4 buffer
+ case DFE_FL_BB_DDUC_TESTGEN_4:
+ regs = &hDfeBb->regs->gcck_dduc4_general;
+ break;
+ // TESTGEN for DDUC5 buffer
+ case DFE_FL_BB_DDUC_TESTGEN_5:
+ regs = &hDfeBb->regs->gcck_dduc5_general;
+ break;
+ // TESTGEN for DDUC6 buffer
+ case DFE_FL_BB_DDUC_TESTGEN_6:
+ regs = &hDfeBb->regs->gcck_dduc6_general;
+ break;
+ // TESTGEN for DDUC7 buffer
+ case DFE_FL_BB_DDUC_TESTGEN_7:
+ regs = &hDfeBb->regs->gcck_dduc7_general;
+ break;
+
+ // TESTGEN for AID A buffer
+ case DFE_FL_BB_AID_TESTGEN_A:
+ regs = &hDfeBb->regs->gcck_aida_general;
+ break;
+ // TESTGEN for AID B buffer
+ case DFE_FL_BB_AID_TESTGEN_B:
+ regs = &hDfeBb->regs->gcck_aidb_general;
+ break;
+
+ default:
+ return;
+ }
+
+ // general
+ data = regs[0];
+ arg->genData = CSL_FEXT(data, DFE_BB_GCCK_DDUC0_GENERAL_REG_GEN_DATA);
+ arg->genFrame = CSL_FEXT(data, DFE_BB_GCCK_DDUC0_GENERAL_REG_GEN_FRAME);
+ arg->rampMode = (DfeFl_BbTestGenRampMode)CSL_FEXT(data, DFE_BB_GCCK_DDUC0_GENERAL_REG_RAMP_MODE);
+ arg->seed = CSL_FEXT(data, DFE_BB_GCCK_DDUC0_GENERAL_REG_SEED);
+ arg->frameLenM1 = CSL_FEXT(data, DFE_BB_GCCK_DDUC0_GENERAL_REG_FRAME_LEN_M1);
+ // ramp start
+ arg->rampStart = regs[1] | (regs[2] << 16);
+ // ramp stop
+ arg->rampStop = regs[3] | (regs[4] << 16);
+ // ramp slope
+ arg->slope = regs[5] | (regs[6] << 16);
+ // gen timer
+ arg->genTimer = regs[7];
+
+ // ssel
+ data = regs[-1];
+ if(arg->tgDev == DFE_FL_BB_AID_TESTGEN_A || arg->tgDev == DFE_FL_BB_AID_TESTGEN_B)
+ {
+ arg->testEnable = CSL_FEXT(data, DFE_BB_CK_SUMA_CTRL1_REG_AID_SIG_GEN_TEST_ENABLE);
+ }
+ else
+ arg->testEnable = 0;
+}
+
+/** ============================================================================
+ * @n@b dfeFl_BbSetTestGenSsel
+ *
+ * @b Description
+ * @n [add content]
+ *
+ * @b Arguments
+ * @verbatim
+ hDfeBb [add content]
+ tgDev [add content]
+ ssel [add content]
+ @endverbatim
+ *
+ * <b> Return Value </b> None
+ *
+ * <b> Pre Condition </b>
+ * @n [add content]
+ *
+ * <b> Post Condition </b>
+ * @n [add content]
+ *
+ * @b Reads
+ * @n None
+ *
+ * @b Writes
+ * @n see below,
+ * DFE_BB_CK_DDUC0_DDUC0_SSEL_REG_SIG_GEN_SSEL
+ *
+ * @b Example
+ * @verbatim
+ [add content]
+ @endverbatim
+ * ===========================================================================
+ */
+CSL_IDEF_INLINE void
+dfeFl_BbSetTestGenSsel(DfeFl_BbHandle hDfeBb, uint32_t tgDev, uint32_t ssel)
+{
+ uint32_t data;
+ volatile uint32_t *regs;
+
+ switch(tgDev)
+ {
+ // TESTGEN for DDUC0 buffer
+ case DFE_FL_BB_DDUC_TESTGEN_0:
+ regs = &hDfeBb->regs->gcck_dduc0_general;
+ break;
+ // TESTGEN for DDUC1 buffer
+ case DFE_FL_BB_DDUC_TESTGEN_1:
+ regs = &hDfeBb->regs->gcck_dduc1_general;
+ break;
+ // TESTGEN for DDUC2 buffer
+ case DFE_FL_BB_DDUC_TESTGEN_2:
+ regs = &hDfeBb->regs->gcck_dduc2_general;
+ break;
+ // TESTGEN for DDUC3 buffer
+ case DFE_FL_BB_DDUC_TESTGEN_3:
+ regs = &hDfeBb->regs->gcck_dduc3_general;
+ break;
+ // TESTGEN for DDUC4 buffer
+ case DFE_FL_BB_DDUC_TESTGEN_4:
+ regs = &hDfeBb->regs->gcck_dduc4_general;
+ break;
+ // TESTGEN for DDUC5 buffer
+ case DFE_FL_BB_DDUC_TESTGEN_5:
+ regs = &hDfeBb->regs->gcck_dduc5_general;
+ break;
+ // TESTGEN for DDUC6 buffer
+ case DFE_FL_BB_DDUC_TESTGEN_6:
+ regs = &hDfeBb->regs->gcck_dduc6_general;
+ break;
+ // TESTGEN for DDUC7 buffer
+ case DFE_FL_BB_DDUC_TESTGEN_7:
+ regs = &hDfeBb->regs->gcck_dduc7_general;
+ break;
+
+ // TESTGEN for AID A buffer
+ case DFE_FL_BB_AID_TESTGEN_A:
+ regs = &hDfeBb->regs->gcck_aida_general;
+ break;
+ // TESTGEN for AID B buffer
+ case DFE_FL_BB_AID_TESTGEN_B:
+ regs = &hDfeBb->regs->gcck_aidb_general;
+ break;
+
+ default:
+ return;
+ }
+
+ // ssel
+ data = regs[-1];
+ CSL_FINS(data, DFE_BB_CK_DDUC0_DDUC0_SSEL_REG_SIG_GEN_SSEL, ssel);
+ regs[-1] = data;
+}
+
+/** ============================================================================
+ * @n@b dfeFl_BbGetTestGenSsel
+ *
+ * @b Description
+ * @n [add content]
+ *
+ * @b Arguments
+ * @verbatim
+ hDfeBb [add content]
+ tgDev [add content]
+ ssel [add content]
+ @endverbatim
+ *
+ * <b> Return Value </b> None
+ *
+ * <b> Pre Condition </b>
+ * @n [add content]
+ *
+ * <b> Post Condition </b>
+ * @n [add content]
+ *
+ * @b Reads
+ * @n see below,
+ * DFE_BB_CK_DDUC0_DDUC0_SSEL_REG_SIG_GEN_SSEL
+ *
+ * @b Writes
+ * @n None
+ *
+ * @b Example
+ * @verbatim
+ [add content]
+ @endverbatim
+ * ===========================================================================
+ */
+CSL_IDEF_INLINE void
+dfeFl_BbGetTestGenSsel(DfeFl_BbHandle hDfeBb, uint32_t tgDev, uint32_t *ssel)
+{
+ uint32_t data;
+ volatile uint32_t *regs;
+
+ switch(tgDev)
+ {
+ // TESTGEN for DDUC0 buffer
+ case DFE_FL_BB_DDUC_TESTGEN_0:
+ regs = &hDfeBb->regs->gcck_dduc0_general;
+ break;
+ // TESTGEN for DDUC1 buffer
+ case DFE_FL_BB_DDUC_TESTGEN_1:
+ regs = &hDfeBb->regs->gcck_dduc1_general;
+ break;
+ // TESTGEN for DDUC2 buffer
+ case DFE_FL_BB_DDUC_TESTGEN_2:
+ regs = &hDfeBb->regs->gcck_dduc2_general;
+ break;
+ // TESTGEN for DDUC3 buffer
+ case DFE_FL_BB_DDUC_TESTGEN_3:
+ regs = &hDfeBb->regs->gcck_dduc3_general;
+ break;
+ // TESTGEN for DDUC4 buffer
+ case DFE_FL_BB_DDUC_TESTGEN_4:
+ regs = &hDfeBb->regs->gcck_dduc4_general;
+ break;
+ // TESTGEN for DDUC5 buffer
+ case DFE_FL_BB_DDUC_TESTGEN_5:
+ regs = &hDfeBb->regs->gcck_dduc5_general;
+ break;
+ // TESTGEN for DDUC6 buffer
+ case DFE_FL_BB_DDUC_TESTGEN_6:
+ regs = &hDfeBb->regs->gcck_dduc6_general;
+ break;
+ // TESTGEN for DDUC7 buffer
+ case DFE_FL_BB_DDUC_TESTGEN_7:
+ regs = &hDfeBb->regs->gcck_dduc7_general;
+ break;
+
+ // TESTGEN for AID A buffer
+ case DFE_FL_BB_AID_TESTGEN_A:
+ regs = &hDfeBb->regs->gcck_aida_general;
+ break;
+ // TESTGEN for AID B buffer
+ case DFE_FL_BB_AID_TESTGEN_B:
+ regs = &hDfeBb->regs->gcck_aidb_general;
+ break;
+
+ default:
+ return;
+ }
+
+ // ssel
+ data = regs[-1];
+ *ssel = CSL_FEXT(data, DFE_BB_CK_DDUC0_DDUC0_SSEL_REG_SIG_GEN_SSEL);
+}
+
+/** ============================================================================
+ * @n@b dfeFl_BbConfigChksum
+ *
+ * @b Description
+ * @n [add content]
+ *
+ * @b Arguments
+ * @verbatim
+ hDfeBb [add content]
+ arg [add content]
+ @endverbatim
+ *
+ * <b> Return Value </b> None
+ *
+ * <b> Pre Condition </b>
+ * @n [add content]
+ *
+ * <b> Post Condition </b>
+ * @n [add content]
+ *
+ * @b Reads
+ * @n None
+ *
+ * @b Writes
+ * @n see below,
+ * DFE_BB_CK_SUMA_CTRL0_REG_STABLE_LEN
+ * DFE_BB_CK_SUMA_CTRL0_REG_MODE
+ * DFE_BB_CK_SUMA_CHAN_SEL_REG_CHAN_SEL
+ * DFE_BB_CK_SUMA_SIGNAL_LEN_REG_SIGNAL_LEN
+ *
+ * @b Example
+ * @verbatim
+ [add content]
+ @endverbatim
+ * ===========================================================================
+ */
+CSL_IDEF_INLINE void
+dfeFl_BbConfigChksum(DfeFl_BbHandle hDfeBb, DfeFl_BbChksumConfig *arg)
+{
+ volatile uint32_t *regs;
+
+ switch(arg->chksumDev)
+ {
+ // CHKSUM for DDUC0 buffer
+ case DFE_FL_BB_DDUC_CHKSUM_0:
+ regs = &hDfeBb->regs->signal_gen0_ctrl0;
+ break;
+ // CHKSUM for DDUC1 buffer
+ case DFE_FL_BB_DDUC_CHKSUM_1:
+ regs = &hDfeBb->regs->signal_gen1_ctrl0;
+ break;
+ // CHKSUM for DDUC2 buffer
+ case DFE_FL_BB_DDUC_CHKSUM_2:
+ regs = &hDfeBb->regs->signal_gen2_ctrl0;
+ break;
+ // CHKSUM for DDUC3 buffer
+ case DFE_FL_BB_DDUC_CHKSUM_3:
+ regs = &hDfeBb->regs->signal_gen3_ctrl0;
+ break;
+ // CHKSUM for DDUC4 buffer
+ case DFE_FL_BB_DDUC_CHKSUM_4:
+ regs = &hDfeBb->regs->signal_gen4_ctrl0;
+ break;
+ // CHKSUM for DDUC5 buffer
+ case DFE_FL_BB_DDUC_CHKSUM_5:
+ regs = &hDfeBb->regs->signal_gen5_ctrl0;
+ break;
+ // CHKSUM for DDUC6 buffer
+ case DFE_FL_BB_DDUC_CHKSUM_6:
+ regs = &hDfeBb->regs->signal_gen6_ctrl0;
+ break;
+ // CHKSUM for DDUC7 buffer
+ case DFE_FL_BB_DDUC_CHKSUM_7:
+ regs = &hDfeBb->regs->signal_gen7_ctrl0;
+ break;
+
+ // CHKSUM for AID A buffer
+ case DFE_FL_BB_AID_CHKSUM_A:
+ regs = &hDfeBb->regs->ck_suma_ctrl0;
+ break;
+ // CHKSUM for AID B buffer
+ case DFE_FL_BB_AID_CHKSUM_B:
+ regs = &hDfeBb->regs->ck_sumb_ctrl0;
+ break;
+
+ default:
+ return;
+ }
+
+ // ctrl0, stable_len
+ regs[0] = CSL_FMK(DFE_BB_CK_SUMA_CTRL0_REG_MODE, arg->chksumMode)
+ | CSL_FMK(DFE_BB_CK_SUMA_CTRL0_REG_STABLE_LEN, arg->latencyMode.stableLen);
+
+ // signal_len
+ regs[1] = CSL_FMK(DFE_BB_CK_SUMA_SIGNAL_LEN_REG_SIGNAL_LEN, arg->latencyMode.signalLen);
+
+ // chan_sel
+ regs[2] = CSL_FMK(DFE_BB_CK_SUMA_CHAN_SEL_REG_CHAN_SEL, arg->latencyMode.chanSel);
+}
+
+/** ============================================================================
+ * @n@b dfeFl_BbSetChksumSsel
+ *
+ * @b Description
+ * @n [add content]
+ *
+ * @b Arguments
+ * @verbatim
+ hDfeBb [add content]
+ arg [add content]
+ @endverbatim
+ *
+ * <b> Return Value </b> None
+ *
+ * <b> Pre Condition </b>
+ * @n [add content]
+ *
+ * <b> Post Condition </b>
+ * @n [add content]
+ *
+ * @b Reads
+ * @n None
+ *
+ * @b Writes
+ * @n see below,
+ * DFE_BB_CK_SUMA_CTRL1_REG_CHKSUM_SSEL
+ *
+ * @b Example
+ * @verbatim
+ [add content]
+ @endverbatim
+ * ===========================================================================
+ */
+CSL_IDEF_INLINE void
+dfeFl_BbSetChksumSsel(DfeFl_BbHandle hDfeBb, DfeFl_BbChksumSsel *arg)
+{
+ volatile uint32_t *regs;
+
+ switch(arg->chksumDev)
+ {
+ // CHKSUM for DDUC0 buffer
+ case DFE_FL_BB_DDUC_CHKSUM_0:
+ regs = &hDfeBb->regs->signal_gen0_ctrl0;
+ break;
+ // CHKSUM for DDUC1 buffer
+ case DFE_FL_BB_DDUC_CHKSUM_1:
+ regs = &hDfeBb->regs->signal_gen1_ctrl0;
+ break;
+ // CHKSUM for DDUC2 buffer
+ case DFE_FL_BB_DDUC_CHKSUM_2:
+ regs = &hDfeBb->regs->signal_gen2_ctrl0;
+ break;
+ // CHKSUM for DDUC3 buffer
+ case DFE_FL_BB_DDUC_CHKSUM_3:
+ regs = &hDfeBb->regs->signal_gen3_ctrl0;
+ break;
+ // CHKSUM for DDUC4 buffer
+ case DFE_FL_BB_DDUC_CHKSUM_4:
+ regs = &hDfeBb->regs->signal_gen4_ctrl0;
+ break;
+ // CHKSUM for DDUC5 buffer
+ case DFE_FL_BB_DDUC_CHKSUM_5:
+ regs = &hDfeBb->regs->signal_gen5_ctrl0;
+ break;
+ // CHKSUM for DDUC6 buffer
+ case DFE_FL_BB_DDUC_CHKSUM_6:
+ regs = &hDfeBb->regs->signal_gen6_ctrl0;
+ break;
+ // CHKSUM for DDUC7 buffer
+ case DFE_FL_BB_DDUC_CHKSUM_7:
+ regs = &hDfeBb->regs->signal_gen7_ctrl0;
+ break;
+
+ // CHKSUM for AID A buffer
+ case DFE_FL_BB_AID_CHKSUM_A:
+ regs = &hDfeBb->regs->ck_suma_ctrl0;
+ break;
+ // CHKSUM for AID B buffer
+ case DFE_FL_BB_AID_CHKSUM_B:
+ regs = &hDfeBb->regs->ck_sumb_ctrl0;
+ break;
+
+ default:
+ return;
+ }
+
+ CSL_FINS(regs[5], DFE_BB_CK_SUMA_CTRL1_REG_CHKSUM_SSEL, arg->ssel);
+}
+
+/** ============================================================================
+ * @n@b dfeFl_BbGetChksumSsel
+ *
+ * @b Description
+ * @n [add content]
+ *
+ * @b Arguments
+ * @verbatim
+ hDfeBb [add content]
+ arg [add content]
+ @endverbatim
+ *
+ * <b> Return Value </b> None
+ *
+ * <b> Pre Condition </b>
+ * @n [add content]
+ *
+ * <b> Post Condition </b>
+ * @n [add content]
+ *
+ * @b Reads
+ * @n DFE_BB_CK_SUMA_CTRL1_REG_CHKSUM_SSEL
+ *
+ * @b Writes
+ * @n None
+ *
+ * @b Example
+ * @verbatim
+ [add content]
+ @endverbatim
+ * ===========================================================================
+ */
+CSL_IDEF_INLINE void
+dfeFl_BbGetChksumSsel(DfeFl_BbHandle hDfeBb, DfeFl_BbChksumSsel *arg)
+{
+ volatile uint32_t *regs;
+
+ switch(arg->chksumDev)
+ {
+ // CHKSUM for DDUC0 buffer
+ case DFE_FL_BB_DDUC_CHKSUM_0:
+ regs = &hDfeBb->regs->signal_gen0_ctrl0;
+ break;
+ // CHKSUM for DDUC1 buffer
+ case DFE_FL_BB_DDUC_CHKSUM_1:
+ regs = &hDfeBb->regs->signal_gen1_ctrl0;
+ break;
+ // CHKSUM for DDUC2 buffer
+ case DFE_FL_BB_DDUC_CHKSUM_2:
+ regs = &hDfeBb->regs->signal_gen2_ctrl0;
+ break;
+ // CHKSUM for DDUC3 buffer
+ case DFE_FL_BB_DDUC_CHKSUM_3:
+ regs = &hDfeBb->regs->signal_gen3_ctrl0;
+ break;
+ // CHKSUM for DDUC4 buffer
+ case DFE_FL_BB_DDUC_CHKSUM_4:
+ regs = &hDfeBb->regs->signal_gen4_ctrl0;
+ break;
+ // CHKSUM for DDUC5 buffer
+ case DFE_FL_BB_DDUC_CHKSUM_5:
+ regs = &hDfeBb->regs->signal_gen5_ctrl0;
+ break;
+ // CHKSUM for DDUC6 buffer
+ case DFE_FL_BB_DDUC_CHKSUM_6:
+ regs = &hDfeBb->regs->signal_gen6_ctrl0;
+ break;
+ // CHKSUM for DDUC7 buffer
+ case DFE_FL_BB_DDUC_CHKSUM_7:
+ regs = &hDfeBb->regs->signal_gen7_ctrl0;
+ break;
+
+ // CHKSUM for AID A buffer
+ case DFE_FL_BB_AID_CHKSUM_A:
+ regs = &hDfeBb->regs->ck_suma_ctrl0;
+ break;
+ // CHKSUM for AID B buffer
+ case DFE_FL_BB_AID_CHKSUM_B:
+ regs = &hDfeBb->regs->ck_sumb_ctrl0;
+ break;
+
+ default:
+ return;
+ }
+
+ arg->ssel = CSL_FEXT(regs[5], DFE_BB_CK_SUMA_CTRL1_REG_CHKSUM_SSEL);
+}
+
+/** ============================================================================
+ * @n@b dfeFl_BbGetChksumResult
+ *
+ * @b Description
+ * @n [add content]
+ *
+ * @b Arguments
+ * @verbatim
+ hDfeBb [add content]
+ arg [add content]
+ @endverbatim
+ *
+ * <b> Return Value </b> None
+ *
+ * <b> Pre Condition </b>
+ * @n [add content]
+ *
+ * <b> Post Condition </b>
+ * @n [add content]
+ *
+ * @b Reads
+ * @n see below,
+ * DFE_BB_CK_SUMA_RESULT_LO_REG_RESULT_15_0
+ * DFE_BB_CK_SUMA_RESULT_HI_REG_RESULT_31_16
+ *
+ * @b Writes
+ * @n None
+ *
+ * @b Example
+ * @verbatim
+ [add content]
+ @endverbatim
+ * ===========================================================================
+ */
+CSL_IDEF_INLINE void
+dfeFl_BbGetChksumResult(DfeFl_BbHandle hDfeBb, DfeFl_BbChksumResult *arg)
+{
+ volatile uint32_t *regs;
+
+ switch(arg->chksumDev)
+ {
+ // CHKSUM for DDUC0 buffer
+ case DFE_FL_BB_DDUC_CHKSUM_0:
+ regs = &hDfeBb->regs->signal_gen0_ctrl0;
+ break;
+ // CHKSUM for DDUC1 buffer
+ case DFE_FL_BB_DDUC_CHKSUM_1:
+ regs = &hDfeBb->regs->signal_gen1_ctrl0;
+ break;
+ // CHKSUM for DDUC2 buffer
+ case DFE_FL_BB_DDUC_CHKSUM_2:
+ regs = &hDfeBb->regs->signal_gen2_ctrl0;
+ break;
+ // CHKSUM for DDUC3 buffer
+ case DFE_FL_BB_DDUC_CHKSUM_3:
+ regs = &hDfeBb->regs->signal_gen3_ctrl0;
+ break;
+ // CHKSUM for DDUC4 buffer
+ case DFE_FL_BB_DDUC_CHKSUM_4:
+ regs = &hDfeBb->regs->signal_gen4_ctrl0;
+ break;
+ // CHKSUM for DDUC5 buffer
+ case DFE_FL_BB_DDUC_CHKSUM_5:
+ regs = &hDfeBb->regs->signal_gen5_ctrl0;
+ break;
+ // CHKSUM for DDUC6 buffer
+ case DFE_FL_BB_DDUC_CHKSUM_6:
+ regs = &hDfeBb->regs->signal_gen6_ctrl0;
+ break;
+ // CHKSUM for DDUC7 buffer
+ case DFE_FL_BB_DDUC_CHKSUM_7:
+ regs = &hDfeBb->regs->signal_gen7_ctrl0;
+ break;
+
+ // CHKSUM for AID A buffer
+ case DFE_FL_BB_AID_CHKSUM_A:
+ regs = &hDfeBb->regs->ck_suma_ctrl0;
+ break;
+ // CHKSUM for AID B buffer
+ case DFE_FL_BB_AID_CHKSUM_B:
+ regs = &hDfeBb->regs->ck_sumb_ctrl0;
+ break;
+
+ default:
+ return;
+ }
+
+ arg->result = CSL_FEXT(regs[3], DFE_BB_CK_SUMA_RESULT_LO_REG_RESULT_15_0);
+ arg->result |= CSL_FEXT(regs[4], DFE_BB_CK_SUMA_RESULT_HI_REG_RESULT_31_16) << 16;
+}
+
+/** ============================================================================
+ * @n@b dfeFl_BbCfgTxifAxc
+ *
+ * @b Description
+ * @n [add content]
+ *
+ * @b Arguments
+ * @verbatim
+ hDfeBb [add content]
+ axc [add content]
+ txif [add content]
+ @endverbatim
+ *
+ * <b> Return Value </b> None
+ *
+ * <b> Pre Condition </b>
+ * @n [add content]
+ *
+ * <b> Post Condition </b>
+ * @n [add content]
+ *
+ * @b Reads
+ * @n None
+ *
+ * @b Writes
+ * @n see below,
+ * DFE_BB_BBTXIF_AXC_CONFIG2_REG_AUTOCP_SEL
+ * DFE_BB_BBTXIF_AXC_CONFIG0_REG_GAIN_EN
+ * DFE_BB_BBTXIF_AXC_CONFIG0_REG_BUFFER_INDEX
+ * DFE_BB_BBTXIF_AXC_CONFIG2_REG_ANTCAL_SEL
+ * DFE_BB_BBTXIF_AXC_CONFIG0_REG_CL_EN
+ * DFE_BB_BBTXIF_AXC_CONFIG1_REG_CL_1OVERT
+ * DFE_BB_BBTXIF_AXC_CONFIG0_REG_PM_CONFIG_SEL
+ * DFE_BB_BBTXIF_AXC_CONFIG0_REG_PM_EN
+ * DFE_BB_BBTXIF_AXC_CONFIG2_REG_AUTOCP_EN
+ * DFE_BB_BBTXIF_AXC_CONFIG0_REG_AXC_VALID
+ * DFE_BB_BBTXIF_AXC_CONFIG0_REG_BUFFER_NUM
+ * DFE_BB_BBTXIF_AXC_CONFIG2_REG_ANTCAL_EN
+ *
+ * @b Example
+ * @verbatim
+ [add content]
+ @endverbatim
+ * ===========================================================================
+ */
+CSL_IDEF_INLINE void
+dfeFl_BbCfgTxifAxc(DfeFl_BbHandle hDfeBb, uint32_t axc, DfeFl_BbTxifAxc *txif)
+{
+ hDfeBb->regs->bbtxif_axc[axc].config0 = \
+ CSL_FMK(DFE_BB_BBTXIF_AXC_CONFIG0_REG_BUFFER_INDEX, txif->bufferIndex) | \
+ CSL_FMK(DFE_BB_BBTXIF_AXC_CONFIG0_REG_BUFFER_NUM, txif->bufferNum) | \
+ CSL_FMK(DFE_BB_BBTXIF_AXC_CONFIG0_REG_PM_CONFIG_SEL, txif->pmConfigSel) | \
+ CSL_FMK(DFE_BB_BBTXIF_AXC_CONFIG0_REG_PM_EN, txif->pmEn) | \
+ CSL_FMK(DFE_BB_BBTXIF_AXC_CONFIG0_REG_CL_EN, txif->clEn) | \
+ CSL_FMK(DFE_BB_BBTXIF_AXC_CONFIG0_REG_GAIN_EN, txif->gainEn) | \
+ CSL_FMK(DFE_BB_BBTXIF_AXC_CONFIG0_REG_AXC_VALID, txif->axcValid);
+ hDfeBb->regs->bbtxif_axc[axc].config1 = \
+ CSL_FMK(DFE_BB_BBTXIF_AXC_CONFIG1_REG_CL_1OVERT, txif->cl1OverT);
+ hDfeBb->regs->bbtxif_axc[axc].config2 = \
+ CSL_FMK(DFE_BB_BBTXIF_AXC_CONFIG2_REG_ANTCAL_SEL, txif->antcalSel) | \
+ CSL_FMK(DFE_BB_BBTXIF_AXC_CONFIG2_REG_ANTCAL_EN, txif->antcalEn) | \
+ CSL_FMK(DFE_BB_BBTXIF_AXC_CONFIG2_REG_AUTOCP_EN, txif->autocpEn) | \
+ CSL_FMK(DFE_BB_BBTXIF_AXC_CONFIG2_REG_AUTOCP_SEL, txif->autocpSel);
+}
+
+/** ============================================================================
+ * @n@b dfeFl_BbCfgRxifAxc
+ *
+ * @b Description
+ * @n [add content]
+ *
+ * @b Arguments
+ * @verbatim
+ hDfeBb [add content]
+ axc [add content]
+ rxif [add content]
+ @endverbatim
+ *
+ * <b> Return Value </b> None
+ *
+ * <b> Pre Condition </b>
+ * @n [add content]
+ *
+ * <b> Post Condition </b>
+ * @n [add content]
+ *
+ * @b Reads
+ * @n None
+ *
+ * @b Writes
+ * @n see below,
+ * DFE_BB_BBRXIF_AXC_CONFIG4_REG_BEAGC_T1_INTERVAL_7_0
+ * DFE_BB_BBRXIF_AXC_CONFIG0_REG_BEAGC_MODE
+ * DFE_BB_BBRXIF_AXC_CONFIG0_REG_AXC_VALID
+ * DFE_BB_BBRXIF_AXC_CONFIG5_REG_BEAGC_T1_INTERVAL_23_8
+ * DFE_BB_BBRXIF_AXC_CONFIG7_REG_BEAGC_T2_INTERVAL_23_16
+ * DFE_BB_BBRXIF_AXC_CONFIG2_REG_BEAGC_POWER_BACKOFF
+ * DFE_BB_BBRXIF_AXC_CONFIG1_REG_PM_EN
+ * DFE_BB_BBRXIF_AXC_CONFIG1_REG_OUT_NUM_BITS
+ * DFE_BB_BBRXIF_AXC_CONFIG1_REG_OUT_PACKED
+ * DFE_BB_BBRXIF_AXC_CONFIG1_REG_OUT_FLOAT_MODE
+ * DFE_BB_BBRXIF_AXC_CONFIG1_REG_NOTCH_EN
+ * DFE_BB_BBRXIF_AXC_CONFIG4_REG_BEAGC_T3_ACTV_CNT
+ * DFE_BB_BBRXIF_AXC_CONFIG0_REG_CARRIER_TYPE
+ * DFE_BB_BBRXIF_AXC_CONFIG2_REG_ANT_CAL_SEL
+ * DFE_BB_BBRXIF_AXC_CONFIG2_REG_ANT_CAL_EN
+ * DFE_BB_BBRXIF_AXC_CONFIG0_REG_BUFFER_INDEX
+ * DFE_BB_BBRXIF_AXC_CONFIG1_REG_PM_CONFIG_SEL
+ * DFE_BB_BBRXIF_AXC_CONFIG2_REG_TDD0
+ * DFE_BB_BBRXIF_AXC_CONFIG0_REG_BUFFER_NUM
+ * DFE_BB_BBRXIF_AXC_CONFIG1_REG_FIXEDORFLOAT
+ * DFE_BB_BBRXIF_AXC_CONFIG6_REG_BEAGC_T2_INTERVAL_15_0
+ * DFE_BB_BBRXIF_AXC_CONFIG4_REG_BEAGC_CONFIG_SEL
+ *
+ * @b Example
+ * @verbatim
+ [add content]
+ @endverbatim
+ * ===========================================================================
+ */
+CSL_IDEF_INLINE void
+dfeFl_BbCfgRxifAxc(DfeFl_BbHandle hDfeBb, uint32_t axc, DfeFl_BbRxifAxc *rxif)
+{
+ hDfeBb->regs->bbrxif_axc[axc].config0 = \
+ CSL_FMK(DFE_BB_BBRXIF_AXC_CONFIG0_REG_BUFFER_INDEX, rxif->bufferIndex) | \
+ CSL_FMK(DFE_BB_BBRXIF_AXC_CONFIG0_REG_BUFFER_NUM, rxif->bufferNum) | \
+ CSL_FMK(DFE_BB_BBRXIF_AXC_CONFIG0_REG_CARRIER_TYPE, rxif->carrierType) | \
+ CSL_FMK(DFE_BB_BBRXIF_AXC_CONFIG0_REG_BEAGC_MODE, rxif->beagcMode) | \
+ CSL_FMK(DFE_BB_BBRXIF_AXC_CONFIG0_REG_AXC_VALID, rxif->axcValid);
+ hDfeBb->regs->bbrxif_axc[axc].config1 = \
+ CSL_FMK(DFE_BB_BBRXIF_AXC_CONFIG1_REG_PM_CONFIG_SEL, rxif->pmConfigSel) | \
+ CSL_FMK(DFE_BB_BBRXIF_AXC_CONFIG1_REG_PM_EN, rxif->pmEn) | \
+ CSL_FMK(DFE_BB_BBRXIF_AXC_CONFIG1_REG_NOTCH_EN, rxif->notchEn) | \
+ CSL_FMK(DFE_BB_BBRXIF_AXC_CONFIG1_REG_OUT_PACKED, rxif->outPacked) | \
+ CSL_FMK(DFE_BB_BBRXIF_AXC_CONFIG1_REG_OUT_FLOAT_MODE, rxif->outFloatMode) | \
+ CSL_FMK(DFE_BB_BBRXIF_AXC_CONFIG1_REG_FIXEDORFLOAT, rxif->fixedOrFloat) | \
+ CSL_FMK(DFE_BB_BBRXIF_AXC_CONFIG1_REG_OUT_NUM_BITS, rxif->outNumBits);
+ hDfeBb->regs->bbrxif_axc[axc].config2 = \
+ CSL_FMK(DFE_BB_BBRXIF_AXC_CONFIG2_REG_ANT_CAL_SEL, rxif->antcalSel) | \
+ CSL_FMK(DFE_BB_BBRXIF_AXC_CONFIG2_REG_ANT_CAL_EN, rxif->antcalEn) | \
+ CSL_FMK(DFE_BB_BBRXIF_AXC_CONFIG2_REG_BEAGC_POWER_BACKOFF, rxif->beagcPowerBackoff) | \
+ CSL_FMK(DFE_BB_BBRXIF_AXC_CONFIG2_REG_TDD0, rxif->tdd0);
+ hDfeBb->regs->bbrxif_axc[axc].config4 = \
+ CSL_FMK(DFE_BB_BBRXIF_AXC_CONFIG4_REG_BEAGC_T3_ACTV_CNT, rxif->beagcT3ActvCnt) | \
+ CSL_FMK(DFE_BB_BBRXIF_AXC_CONFIG4_REG_BEAGC_CONFIG_SEL, rxif->beagcConfigSel) | \
+ CSL_FMK(DFE_BB_BBRXIF_AXC_CONFIG4_REG_BEAGC_T1_INTERVAL_7_0, rxif->beagcT1Interval);
+ hDfeBb->regs->bbrxif_axc[axc].config5 = \
+ CSL_FMK(DFE_BB_BBRXIF_AXC_CONFIG5_REG_BEAGC_T1_INTERVAL_23_8, rxif->beagcT1Interval >> 8);
+ hDfeBb->regs->bbrxif_axc[axc].config6 = \
+ CSL_FMK(DFE_BB_BBRXIF_AXC_CONFIG6_REG_BEAGC_T2_INTERVAL_15_0, rxif->beagcT2Interval);
+ hDfeBb->regs->bbrxif_axc[axc].config7 = \
+ CSL_FMK(DFE_BB_BBRXIF_AXC_CONFIG7_REG_BEAGC_T2_INTERVAL_23_16, rxif->beagcT1Interval >> 16);
+}
+
+/** ============================================================================
+ * @n@b dfeFl_BbGetTxGainUpdateStatus
+ *
+ * @b Description
+ * @n [add content]
+ *
+ * @b Arguments
+ * @verbatim
+ hDfeBb [add content]
+ ct [add content]
+ status [add content]
+ @endverbatim
+ *
+ * <b> Return Value </b> None
+ *
+ * <b> Pre Condition </b>
+ * @n [add content]
+ *
+ * <b> Post Condition </b>
+ * @n [add content]
+ *
+ * @b Reads
+ * @n None
+ *
+ * @b Writes
+ * @n None
+ *
+ * @b Example
+ * @verbatim
+ [add content]
+ @endverbatim
+ * ===========================================================================
+ */
+CSL_IDEF_INLINE void
+dfeFl_BbGetTxGainUpdateStatus(DfeFl_BbHandle hDfeBb, uint32_t ct, uint32_t *status)
+{
+ *status = CSL_FEXTR(hDfeBb->regs->cfg85, ct, ct);
+}
+
+/** ============================================================================
+ * @n@b dfeFl_BbUpdateTxGain
+ *
+ * @b Description
+ * @n [add content]
+ *
+ * @b Arguments
+ * @verbatim
+ hDfeBb [add content]
+ axc [add content]
+ gainI [add content]
+ gainQ [add content]
+ @endverbatim
+ *
+ * <b> Return Value </b> None
+ *
+ * <b> Pre Condition </b>
+ * @n [add content]
+ *
+ * <b> Post Condition </b>
+ * @n [add content]
+ *
+ * @b Reads
+ * @n None
+ *
+ * @b Writes
+ * @n see below,
+ * DFE_BB_BBTXGAIN_I_REG_INPHASE
+ * DFE_BB_BBTXGAIN_Q_REG_QUADRATURE
+ *
+ * @b Example
+ * @verbatim
+ [add content]
+ @endverbatim
+ * ===========================================================================
+ */
+CSL_IDEF_INLINE void
+dfeFl_BbUpdateTxGain(DfeFl_BbHandle hDfeBb, uint32_t axc, uint32_t gainI, uint32_t gainQ)
+{
+ hDfeBb->regs->bbtxgain[axc].i = CSL_FMK(DFE_BB_BBTXGAIN_I_REG_INPHASE, gainI);
+ hDfeBb->regs->bbtxgain[axc].q = CSL_FMK(DFE_BB_BBTXGAIN_Q_REG_QUADRATURE, gainQ);
+}
+
+/** ============================================================================
+ * @n@b dfeFl_BbQueryTxGain
+ *
+ * @b Description
+ * @n [add content]
+ *
+ * @b Arguments
+ * @verbatim
+ hDfeBb [add content]
+ axc [add content]
+ gainI [add content]
+ gainQ [add content]
+ @endverbatim
+ *
+ * <b> Return Value </b> None
+ *
+ * <b> Pre Condition </b>
+ * @n [add content]
+ *
+ * <b> Post Condition </b>
+ * @n [add content]
+ *
+ * @b Reads
+ * @n see below,
+ * DFE_BB_BBTXGAIN_I_REG_INPHASE
+ * DFE_BB_BBTXGAIN_Q_REG_QUADRATURE
+ *
+ * @b Writes
+ * @n None
+ *
+ * @b Example
+ * @verbatim
+ [add content]
+ @endverbatim
+ * ===========================================================================
+ */
+CSL_IDEF_INLINE void
+dfeFl_BbQueryTxGain(DfeFl_BbHandle hDfeBb, uint32_t axc, uint32_t *gainI, uint32_t *gainQ)
+{
+ *gainI = CSL_FEXT(hDfeBb->regs->bbtxgain[axc].i, DFE_BB_BBTXGAIN_I_REG_INPHASE);
+ *gainQ = CSL_FEXT(hDfeBb->regs->bbtxgain[axc].q, DFE_BB_BBTXGAIN_Q_REG_QUADRATURE);
+}
+
+/** ============================================================================
+ * @n@b dfeFl_BbSetTxGainCtSsel
+ *
+ * @b Description
+ * @n [add content]
+ *
+ * @b Arguments
+ * @verbatim
+ hDfeBb [add content]
+ ct [add content]
+ ssel [add content]
+ @endverbatim
+ *
+ * <b> Return Value </b> None
+ *
+ * <b> Pre Condition </b>
+ * @n [add content]
+ *
+ * <b> Post Condition </b>
+ * @n [add content]
+ *
+ * @b Reads
+ * @n None
+ *
+ * @b Writes
+ * @n None
+ *
+ * @b Example
+ * @verbatim
+ [add content]
+ @endverbatim
+ * ===========================================================================
+ */
+CSL_IDEF_INLINE void
+dfeFl_BbSetTxGainCtSsel(DfeFl_BbHandle hDfeBb, uint32_t ct, uint32_t ssel)
+{
+ volatile uint32_t *regs = &hDfeBb->regs->cfg60;
+ uint32_t r = ct / 4;
+ uint32_t b = (ct % 4) * 4;
+
+ CSL_FINSR(regs[r], b+3, b, ssel);
+}
+
+/** ============================================================================
+ * @n@b dfeFl_BbGetTxGainCtSsel
+ *
+ * @b Description
+ * @n [add content]
+ *
+ * @b Arguments
+ * @verbatim
+ hDfeBb [add content]
+ ct [add content]
+ ssel [add content]
+ @endverbatim
+ *
+ * <b> Return Value </b> None
+ *
+ * <b> Pre Condition </b>
+ * @n [add content]
+ *
+ * <b> Post Condition </b>
+ * @n [add content]
+ *
+ * @b Reads
+ * @n None
+ *
+ * @b Writes
+ * @n None
+ *
+ * @b Example
+ * @verbatim
+ [add content]
+ @endverbatim
+ * ===========================================================================
+ */
+CSL_IDEF_INLINE void
+dfeFl_BbGetTxGainCtSsel(DfeFl_BbHandle hDfeBb, uint32_t ct, uint32_t *ssel)
+{
+ volatile uint32_t *regs = &hDfeBb->regs->cfg60;
+ uint32_t r = ct / 4;
+ uint32_t b = (ct % 4) * 4;
+
+ *ssel = CSL_FEXTR(regs[r], b+3, b);
+}
+
+/** ============================================================================
+ * @n@b dfeFl_BbEnableTxGainIntr
+ *
+ * @b Description
+ * @n [add content]
+ *
+ * @b Arguments
+ * @verbatim
+ hDfeBb [add content]
+ ct [add content]
+ @endverbatim
+ *
+ * <b> Return Value </b> None
+ *
+ * <b> Pre Condition </b>
+ * @n [add content]
+ *
+ * <b> Post Condition </b>
+ * @n [add content]
+ *
+ * @b Reads
+ * @n None
+ *
+ * @b Writes
+ * @n None
+ *
+ * @b Example
+ * @verbatim
+ [add content]
+ @endverbatim
+ * ===========================================================================
+ */
+CSL_IDEF_INLINE void
+dfeFl_BbEnableTxGainIntr(DfeFl_BbHandle hDfeBb, uint32_t ct)
+{
+ CSL_FINSR(hDfeBb->regs->intmask2, ct, ct, 1);
+}
+
+/** ============================================================================
+ * @n@b dfeFl_BbDisableTxGainIntr
+ *
+ * @b Description
+ * @n [add content]
+ *
+ * @b Arguments
+ * @verbatim
+ hDfeBb [add content]
+ ct [add content]
+ @endverbatim
+ *
+ * <b> Return Value </b> None
+ *
+ * <b> Pre Condition </b>
+ * @n [add content]
+ *
+ * <b> Post Condition </b>
+ * @n [add content]
+ *
+ * @b Reads
+ * @n None
+ *
+ * @b Writes
+ * @n None
+ *
+ * @b Example
+ * @verbatim
+ [add content]
+ @endverbatim
+ * ===========================================================================
+ */
+CSL_IDEF_INLINE void
+dfeFl_BbDisableTxGainIntr(DfeFl_BbHandle hDfeBb, uint32_t ct)
+{
+ CSL_FINSR(hDfeBb->regs->intmask2, ct, ct, 0);
+}
+
+/** ============================================================================
+ * @n@b dfeFl_BbClearTxGainIntrStatus
+ *
+ * @b Description
+ * @n [add content]
+ *
+ * @b Arguments
+ * @verbatim
+ hDfeBb [add content]
+ ct [add content]
+ @endverbatim
+ *
+ * <b> Return Value </b> None
+ *
+ * <b> Pre Condition </b>
+ * @n [add content]
+ *
+ * <b> Post Condition </b>
+ * @n [add content]
+ *
+ * @b Reads
+ * @n None
+ *
+ * @b Writes
+ * @n None
+ *
+ * @b Example
+ * @verbatim
+ [add content]
+ @endverbatim
+ * ===========================================================================
+ */
+CSL_IDEF_INLINE void
+dfeFl_BbClearTxGainIntrStatus(DfeFl_BbHandle hDfeBb, uint32_t ct)
+{
+ hDfeBb->regs->intstatus2 = ~(1u << ct);
+}
+
+/** ============================================================================
+ * @n@b dfeFl_BbQueryTxGainIntrStatus
+ *
+ * @b Description
+ * @n [add content]
+ *
+ * @b Arguments
+ * @verbatim
+ hDfeBb [add content]
+ ct [add content]
+ status [add content]
+ @endverbatim
+ *
+ * <b> Return Value </b> None
+ *
+ * <b> Pre Condition </b>
+ * @n [add content]
+ *
+ * <b> Post Condition </b>
+ * @n [add content]
+ *
+ * @b Reads
+ * @n None
+ *
+ * @b Writes
+ * @n None
+ *
+ * @b Example
+ * @verbatim
+ [add content]
+ @endverbatim
+ * ===========================================================================
+ */
+CSL_IDEF_INLINE void
+dfeFl_BbQueryTxGainIntrStatus(DfeFl_BbHandle hDfeBb, uint32_t ct, uint32_t *status)
+{
+ *status = CSL_FEXTR(hDfeBb->regs->intstatus2, ct, ct);
+}
+
+/** ============================================================================
+ * @n@b dfeFl_BbSetForceTxGainIntr
+ *
+ * @b Description
+ * @n [add content]
+ *
+ * @b Arguments
+ * @verbatim
+ hDfeBb [add content]
+ ct [add content]
+ @endverbatim
+ *
+ * <b> Return Value </b> None
+ *
+ * <b> Pre Condition </b>
+ * @n [add content]
+ *
+ * <b> Post Condition </b>
+ * @n [add content]
+ *
+ * @b Reads
+ * @n None
+ *
+ * @b Writes
+ * @n None
+ *
+ * @b Example
+ * @verbatim
+ [add content]
+ @endverbatim
+ * ===========================================================================
+ */
+CSL_IDEF_INLINE void
+dfeFl_BbSetForceTxGainIntr(DfeFl_BbHandle hDfeBb, uint32_t ct)
+{
+ CSL_FINSR(hDfeBb->regs->intforce2, ct, ct, 1);
+}
+
+/** ============================================================================
+ * @n@b dfeFl_BbClearForceTxGainIntr
+ *
+ * @b Description
+ * @n [add content]
+ *
+ * @b Arguments
+ * @verbatim
+ hDfeBb [add content]
+ ct [add content]
+ @endverbatim
+ *
+ * <b> Return Value </b> None
+ *
+ * <b> Pre Condition </b>
+ * @n [add content]
+ *
+ * <b> Post Condition </b>
+ * @n [add content]
+ *
+ * @b Reads
+ * @n None
+ *
+ * @b Writes
+ * @n None
+ *
+ * @b Example
+ * @verbatim
+ [add content]
+ @endverbatim
+ * ===========================================================================
+ */
+CSL_IDEF_INLINE void
+dfeFl_BbClearForceTxGainIntr(DfeFl_BbHandle hDfeBb, uint32_t ct)
+{
+ CSL_FINSR(hDfeBb->regs->intforce2, ct, ct, 0);
+}
+
+/** ============================================================================
+ * @n@b dfeFl_BbConfigTxTdd
+ *
+ * @b Description
+ * @n [add content]
+ *
+ * @b Arguments
+ * @verbatim
+ hDfeBb [add content]
+ arg [add content]
+ @endverbatim
+ *
+ * <b> Return Value </b> None
+ *
+ * <b> Pre Condition </b>
+ * @n [add content]
+ *
+ * <b> Post Condition </b>
+ * @n [add content]
+ *
+ * @b Reads
+ * @n see below,
+ * DFE_BB_CFG1168_REG_TXTDD_SSEL
+ *
+ * @b Writes
+ * @n see below,
+ * DFE_BB_CFG1173_REG_TXTDD_TIMER_UL1_23_16
+ * DFE_BB_CFG1168_REG_TXTDD_DATAMODE
+ * DFE_BB_CFG1172_REG_TXTDD_TIMER_UL1_15_0
+ * DFE_BB_CFG1170_REG_TXTDD_TIMER_DL1_23_16
+ * DFE_BB_CFG1171_REG_TXTDD_TIMER_DL1_15_0
+ * DFE_BB_CFG1177_REG_TXTDD_TIMER_DL3_15_0
+ * DFE_BB_CFG1176_REG_TXTDD_TIMER_UL2_23_16
+ * DFE_BB_CFG1168_REG_TXTDD_SSEL
+ * DFE_BB_CFG1169_REG_TXTDD_DELAYFROMSYNC_15_0
+ * DFE_BB_CFG1168_REG_TXTDD_CT_TYPE
+ * DFE_BB_CFG1168_REG_TXTDD_EN
+ * DFE_BB_CFG1170_REG_TXTDD_DELAYFROMSYNC_23_16
+ * DFE_BB_CFG1173_REG_TXTDD_TIMER_DL2_23_16
+ * DFE_BB_CFG1175_REG_TXTDD_TIMER_UL2_15_0
+ * DFE_BB_CFG1174_REG_TXTDD_TIMER_DL2_15_0
+ * DFE_BB_CFG1176_REG_TXTDD_TIMER_DL3_23_16
+ *
+ * @b Example
+ * @verbatim
+ [add content]
+ @endverbatim
+ * ===========================================================================
+ */
+CSL_IDEF_INLINE void
+dfeFl_BbConfigTxTdd(DfeFl_BbHandle hDfeBb, DfeFl_BbTddConfig * arg)
+{
+ uint32_t data;
+
+ hDfeBb->regs->cfg1169 = CSL_FMK(DFE_BB_CFG1169_REG_TXTDD_DELAYFROMSYNC_15_0, arg->syncDly);
+ hDfeBb->regs->cfg1170 = CSL_FMK(DFE_BB_CFG1170_REG_TXTDD_DELAYFROMSYNC_23_16, arg->syncDly >> 16)
+ | CSL_FMK(DFE_BB_CFG1170_REG_TXTDD_TIMER_DL1_23_16, arg->dl1Interval >> 16);
+ hDfeBb->regs->cfg1171 = CSL_FMK(DFE_BB_CFG1171_REG_TXTDD_TIMER_DL1_15_0, arg->dl1Interval);
+ hDfeBb->regs->cfg1172 = CSL_FMK(DFE_BB_CFG1172_REG_TXTDD_TIMER_UL1_15_0, arg->ul1Interval);
+ hDfeBb->regs->cfg1173 = CSL_FMK(DFE_BB_CFG1173_REG_TXTDD_TIMER_UL1_23_16, arg->ul1Interval >> 16)
+ | CSL_FMK(DFE_BB_CFG1173_REG_TXTDD_TIMER_DL2_23_16, arg->dl2Interval >> 16);
+ hDfeBb->regs->cfg1174 = CSL_FMK(DFE_BB_CFG1174_REG_TXTDD_TIMER_DL2_15_0, arg->dl2Interval);
+ hDfeBb->regs->cfg1175 = CSL_FMK(DFE_BB_CFG1175_REG_TXTDD_TIMER_UL2_15_0, arg->ul2Interval);
+ hDfeBb->regs->cfg1176 = CSL_FMK(DFE_BB_CFG1176_REG_TXTDD_TIMER_UL2_23_16, arg->ul2Interval >> 16)
+ | CSL_FMK(DFE_BB_CFG1176_REG_TXTDD_TIMER_DL3_23_16, arg->dl3Interval >> 16);
+ hDfeBb->regs->cfg1177 = CSL_FMK(DFE_BB_CFG1177_REG_TXTDD_TIMER_DL3_15_0, arg->dl3Interval);
+
+ // ssel
+ data = CSL_FEXT(hDfeBb->regs->cfg1168, DFE_BB_CFG1168_REG_TXTDD_SSEL);
+ hDfeBb->regs->cfg1168 = CSL_FMK(DFE_BB_CFG1168_REG_TXTDD_EN, arg->enable)
+ | CSL_FMK(DFE_BB_CFG1168_REG_TXTDD_DATAMODE, arg->dataMode)
+ | CSL_FMK(DFE_BB_CFG1168_REG_TXTDD_CT_TYPE, arg->carrierType)
+ | CSL_FMK(DFE_BB_CFG1168_REG_TXTDD_SSEL, data);
+
+}
+
+/** ============================================================================
+ * @n@b dfeFl_BbQueryTxTddConfig
+ *
+ * @b Description
+ * @n [add content]
+ *
+ * @b Arguments
+ * @verbatim
+ hDfeBb [add content]
+ arg [add content]
+ @endverbatim
+ *
+ * <b> Return Value </b> None
+ *
+ * <b> Pre Condition </b>
+ * @n [add content]
+ *
+ * <b> Post Condition </b>
+ * @n [add content]
+ *
+ * @b Reads
+ * @n see below,
+ * DFE_BB_CFG1173_REG_TXTDD_TIMER_UL1_23_16
+ * DFE_BB_CFG1168_REG_TXTDD_DATAMODE
+ * DFE_BB_CFG1172_REG_TXTDD_TIMER_UL1_15_0
+ * DFE_BB_CFG1170_REG_TXTDD_TIMER_DL1_23_16
+ * DFE_BB_CFG1171_REG_TXTDD_TIMER_DL1_15_0
+ * DFE_BB_CFG1176_REG_TXTDD_TIMER_UL2_23_16
+ * DFE_BB_CFG1169_REG_TXTDD_DELAYFROMSYNC_15_0
+ * DFE_BB_CFG1168_REG_TXTDD_CT_TYPE
+ * DFE_BB_CFG1168_REG_TXTDD_EN
+ * DFE_BB_CFG1170_REG_TXTDD_DELAYFROMSYNC_23_16
+ * DFE_BB_CFG1173_REG_TXTDD_TIMER_DL2_23_16
+ * DFE_BB_CFG1175_REG_TXTDD_TIMER_UL2_15_0
+ * DFE_BB_CFG1176_REG_TXTDD_TIMER_DL3_23_16
+ * DFE_BB_CFG1174_REG_TXTDD_TIMER_DL2_15_0
+ * DFE_BB_CFG1177_REG_TXTDD_TIMER_DL3_15_0
+ *
+ * @b Writes
+ * @n None
+ *
+ * @b Example
+ * @verbatim
+ [add content]
+ @endverbatim
+ * ===========================================================================
+ */
+CSL_IDEF_INLINE void
+dfeFl_BbQueryTxTddConfig(DfeFl_BbHandle hDfeBb, DfeFl_BbTddConfig * arg)
+{
+ uint32_t data;
+
+ arg->syncDly = CSL_FEXT(hDfeBb->regs->cfg1169, DFE_BB_CFG1169_REG_TXTDD_DELAYFROMSYNC_15_0)
+ |(CSL_FEXT(hDfeBb->regs->cfg1170, DFE_BB_CFG1170_REG_TXTDD_DELAYFROMSYNC_23_16) << 16);
+ arg->dl1Interval = CSL_FEXT(hDfeBb->regs->cfg1171, DFE_BB_CFG1171_REG_TXTDD_TIMER_DL1_15_0)
+ |(CSL_FEXT(hDfeBb->regs->cfg1170, DFE_BB_CFG1170_REG_TXTDD_TIMER_DL1_23_16) << 16);
+ arg->ul1Interval = CSL_FEXT(hDfeBb->regs->cfg1172, DFE_BB_CFG1172_REG_TXTDD_TIMER_UL1_15_0)
+ |(CSL_FEXT(hDfeBb->regs->cfg1173, DFE_BB_CFG1173_REG_TXTDD_TIMER_UL1_23_16) << 16);
+ arg->dl2Interval = CSL_FEXT(hDfeBb->regs->cfg1174, DFE_BB_CFG1174_REG_TXTDD_TIMER_DL2_15_0)
+ |(CSL_FEXT(hDfeBb->regs->cfg1173, DFE_BB_CFG1173_REG_TXTDD_TIMER_DL2_23_16) << 16);
+ arg->ul2Interval = CSL_FEXT(hDfeBb->regs->cfg1175, DFE_BB_CFG1175_REG_TXTDD_TIMER_UL2_15_0)
+ |(CSL_FEXT(hDfeBb->regs->cfg1176, DFE_BB_CFG1176_REG_TXTDD_TIMER_UL2_23_16) << 16);
+ arg->dl3Interval = CSL_FEXT(hDfeBb->regs->cfg1177, DFE_BB_CFG1177_REG_TXTDD_TIMER_DL3_15_0)
+ |(CSL_FEXT(hDfeBb->regs->cfg1176, DFE_BB_CFG1176_REG_TXTDD_TIMER_DL3_23_16) << 16);
+
+ data = hDfeBb->regs->cfg1168;
+ arg->enable = CSL_FEXT(data, DFE_BB_CFG1168_REG_TXTDD_EN);
+ arg->dataMode = (DfeFl_BbTddDataMode)CSL_FEXT(data, DFE_BB_CFG1168_REG_TXTDD_DATAMODE);
+ arg->carrierType = CSL_FEXT(data, DFE_BB_CFG1168_REG_TXTDD_CT_TYPE);
+}
+
+/** ============================================================================
+ * @n@b dfeFl_BbSetTxTddSsel
+ *
+ * @b Description
+ * @n [add content]
+ *
+ * @b Arguments
+ * @verbatim
+ hDfeBb [add content]
+ ssel [add content]
+ @endverbatim
+ *
+ * <b> Return Value </b> None
+ *
+ * <b> Pre Condition </b>
+ * @n [add content]
+ *
+ * <b> Post Condition </b>
+ * @n [add content]
+ *
+ * @b Reads
+ * @n None
+ *
+ * @b Writes
+ * @n see below,
+ * DFE_BB_CFG1168_REG_TXTDD_SSEL
+ *
+ * @b Example
+ * @verbatim
+ [add content]
+ @endverbatim
+ * ===========================================================================
+ */
+CSL_IDEF_INLINE void
+dfeFl_BbSetTxTddSsel(DfeFl_BbHandle hDfeBb, uint32_t ssel)
+{
+ CSL_FINS(hDfeBb->regs->cfg1168, DFE_BB_CFG1168_REG_TXTDD_SSEL, ssel);
+}
+
+/** ============================================================================
+ * @n@b dfeFl_BbGetTxTddSsel
+ *
+ * @b Description
+ * @n [add content]
+ *
+ * @b Arguments
+ * @verbatim
+ hDfeBb [add content]
+ ssel [add content]
+ @endverbatim
+ *
+ * <b> Return Value </b> None
+ *
+ * <b> Pre Condition </b>
+ * @n [add content]
+ *
+ * <b> Post Condition </b>
+ * @n [add content]
+ *
+ * @b Reads
+ * @n see below,
+ * DFE_BB_CFG1168_REG_TXTDD_SSEL
+ *
+ * @b Writes
+ * @n None
+ *
+ * @b Example
+ * @verbatim
+ [add content]
+ @endverbatim
+ * ===========================================================================
+ */
+CSL_IDEF_INLINE void
+dfeFl_BbGetTxTddSsel(DfeFl_BbHandle hDfeBb, uint32_t *ssel)
+{
+ *ssel = CSL_FEXT(hDfeBb->regs->cfg1168, DFE_BB_CFG1168_REG_TXTDD_SSEL);
+}
+
+/** ============================================================================
+ * @n@b dfeFl_BbConfigRxTdd
+ *
+ * @b Description
+ * @n [add content]
+ *
+ * @b Arguments
+ * @verbatim
+ hDfeBb [add content]
+ arg [add content]
+ @endverbatim
+ *
+ * <b> Return Value </b> None
+ *
+ * <b> Pre Condition </b>
+ * @n [add content]
+ *
+ * <b> Post Condition </b>
+ * @n [add content]
+ *
+ * @b Reads
+ * @n see below,
+ * DFE_BB_CFG1184_REG_RXTDD_SSEL
+ *
+ * @b Writes
+ * @n see below,
+ * DFE_BB_CFG1184_REG_RXTDD_SSEL
+ * DFE_BB_CFG1184_REG_RXTDD_DATAMODE
+ * DFE_BB_CFG1188_REG_RXTDD_TIMER_UL1_15_0
+ * DFE_BB_CFG1190_REG_RXTDD_TIMER_DL2_15_0
+ * DFE_BB_CFG1189_REG_RXTDD_TIMER_UL1_23_16
+ * DFE_BB_CFG1193_REG_RXTDD_TIMER_DL3_15_0
+ * DFE_BB_CFG1189_REG_RXTDD_TIMER_DL2_23_16
+ * DFE_BB_CFG1192_REG_RXTDD_TIMER_UL2_23_16
+ * DFE_BB_CFG1186_REG_RXTDD_TIMER_DL1_23_16
+ * DFE_BB_CFG1191_REG_RXTDD_TIMER_UL2_15_0
+ * DFE_BB_CFG1184_REG_RXTDD_CT_TYPE
+ * DFE_BB_CFG1186_REG_RXTDD_DELAYFROMSYNC_23_16
+ * DFE_BB_CFG1184_REG_RXTDD_EN
+ * DFE_BB_CFG1192_REG_RXTDD_TIMER_DL3_23_16
+ * DFE_BB_CFG1187_REG_RXTDD_TIMER_DL1_15_0
+ * DFE_BB_CFG1185_REG_RXTDD_DELAYFROMSYNC_15_0
+ *
+ * @b Example
+ * @verbatim
+ [add content]
+ @endverbatim
+ * ===========================================================================
+ */
+CSL_IDEF_INLINE void
+dfeFl_BbConfigRxTdd(DfeFl_BbHandle hDfeBb, DfeFl_BbTddConfig * arg)
+{
+ uint32_t data;
+
+ hDfeBb->regs->cfg1185 = CSL_FMK(DFE_BB_CFG1185_REG_RXTDD_DELAYFROMSYNC_15_0, arg->syncDly);
+ hDfeBb->regs->cfg1186 = CSL_FMK(DFE_BB_CFG1186_REG_RXTDD_DELAYFROMSYNC_23_16, arg->syncDly >> 16)
+ | CSL_FMK(DFE_BB_CFG1186_REG_RXTDD_TIMER_DL1_23_16, arg->dl1Interval >> 16);
+ hDfeBb->regs->cfg1187 = CSL_FMK(DFE_BB_CFG1187_REG_RXTDD_TIMER_DL1_15_0, arg->dl1Interval);
+ hDfeBb->regs->cfg1188 = CSL_FMK(DFE_BB_CFG1188_REG_RXTDD_TIMER_UL1_15_0, arg->ul1Interval);
+ hDfeBb->regs->cfg1189 = CSL_FMK(DFE_BB_CFG1189_REG_RXTDD_TIMER_UL1_23_16, arg->ul1Interval >> 16)
+ | CSL_FMK(DFE_BB_CFG1189_REG_RXTDD_TIMER_DL2_23_16, arg->dl2Interval >> 16);
+ hDfeBb->regs->cfg1190 = CSL_FMK(DFE_BB_CFG1190_REG_RXTDD_TIMER_DL2_15_0, arg->dl2Interval);
+ hDfeBb->regs->cfg1191 = CSL_FMK(DFE_BB_CFG1191_REG_RXTDD_TIMER_UL2_15_0, arg->ul2Interval);
+ hDfeBb->regs->cfg1192 = CSL_FMK(DFE_BB_CFG1192_REG_RXTDD_TIMER_UL2_23_16, arg->ul2Interval >> 16)
+ | CSL_FMK(DFE_BB_CFG1192_REG_RXTDD_TIMER_DL3_23_16, arg->dl3Interval >> 16);
+ hDfeBb->regs->cfg1193 = CSL_FMK(DFE_BB_CFG1193_REG_RXTDD_TIMER_DL3_15_0, arg->dl3Interval);
+
+ // ssel
+ data = CSL_FEXT(hDfeBb->regs->cfg1184, DFE_BB_CFG1184_REG_RXTDD_SSEL);
+ hDfeBb->regs->cfg1184 = CSL_FMK(DFE_BB_CFG1184_REG_RXTDD_EN, arg->enable)
+ | CSL_FMK(DFE_BB_CFG1184_REG_RXTDD_DATAMODE, arg->dataMode)
+ | CSL_FMK(DFE_BB_CFG1184_REG_RXTDD_CT_TYPE, arg->carrierType)
+ | CSL_FMK(DFE_BB_CFG1184_REG_RXTDD_SSEL, data);
+
+
+}
+
+/** ============================================================================
+ * @n@b dfeFl_BbQueryRxTddConfig
+ *
+ * @b Description
+ * @n [add content]
+ *
+ * @b Arguments
+ * @verbatim
+ hDfeBb [add content]
+ arg [add content]
+ @endverbatim
+ *
+ * <b> Return Value </b> None
+ *
+ * <b> Pre Condition </b>
+ * @n [add content]
+ *
+ * <b> Post Condition </b>
+ * @n [add content]
+ *
+ * @b Reads
+ * @n see below,
+ * DFE_BB_CFG1184_REG_RXTDD_DATAMODE
+ * DFE_BB_CFG1188_REG_RXTDD_TIMER_UL1_15_0
+ * DFE_BB_CFG1190_REG_RXTDD_TIMER_DL2_15_0
+ * DFE_BB_CFG1189_REG_RXTDD_TIMER_UL1_23_16
+ * DFE_BB_CFG1193_REG_RXTDD_TIMER_DL3_15_0
+ * DFE_BB_CFG1189_REG_RXTDD_TIMER_DL2_23_16
+ * DFE_BB_CFG1192_REG_RXTDD_TIMER_UL2_23_16
+ * DFE_BB_CFG1186_REG_RXTDD_TIMER_DL1_23_16
+ * DFE_BB_CFG1191_REG_RXTDD_TIMER_UL2_15_0
+ * DFE_BB_CFG1184_REG_RXTDD_CT_TYPE
+ * DFE_BB_CFG1186_REG_RXTDD_DELAYFROMSYNC_23_16
+ * DFE_BB_CFG1184_REG_RXTDD_EN
+ * DFE_BB_CFG1192_REG_RXTDD_TIMER_DL3_23_16
+ * DFE_BB_CFG1187_REG_RXTDD_TIMER_DL1_15_0
+ * DFE_BB_CFG1185_REG_RXTDD_DELAYFROMSYNC_15_0
+ *
+ * @b Writes
+ * @n None
+ *
+ * @b Example
+ * @verbatim
+ [add content]
+ @endverbatim
+ * ===========================================================================
+ */
+CSL_IDEF_INLINE void
+dfeFl_BbQueryRxTddConfig(DfeFl_BbHandle hDfeBb, DfeFl_BbTddConfig * arg)
+{
+ uint32_t data;
+
+ arg->syncDly = CSL_FEXT(hDfeBb->regs->cfg1185, DFE_BB_CFG1185_REG_RXTDD_DELAYFROMSYNC_15_0)
+ |(CSL_FEXT(hDfeBb->regs->cfg1186, DFE_BB_CFG1186_REG_RXTDD_DELAYFROMSYNC_23_16) << 16);
+ arg->dl1Interval = CSL_FEXT(hDfeBb->regs->cfg1187, DFE_BB_CFG1187_REG_RXTDD_TIMER_DL1_15_0)
+ |(CSL_FEXT(hDfeBb->regs->cfg1186, DFE_BB_CFG1186_REG_RXTDD_TIMER_DL1_23_16) << 16);
+ arg->ul1Interval = CSL_FEXT(hDfeBb->regs->cfg1188, DFE_BB_CFG1188_REG_RXTDD_TIMER_UL1_15_0)
+ |(CSL_FEXT(hDfeBb->regs->cfg1189, DFE_BB_CFG1189_REG_RXTDD_TIMER_UL1_23_16) << 16);
+ arg->dl2Interval = CSL_FEXT(hDfeBb->regs->cfg1190, DFE_BB_CFG1190_REG_RXTDD_TIMER_DL2_15_0)
+ |(CSL_FEXT(hDfeBb->regs->cfg1189, DFE_BB_CFG1189_REG_RXTDD_TIMER_DL2_23_16) << 16);
+ arg->ul2Interval = CSL_FEXT(hDfeBb->regs->cfg1191, DFE_BB_CFG1191_REG_RXTDD_TIMER_UL2_15_0)
+ |(CSL_FEXT(hDfeBb->regs->cfg1192, DFE_BB_CFG1192_REG_RXTDD_TIMER_UL2_23_16) << 16);
+ arg->dl3Interval = CSL_FEXT(hDfeBb->regs->cfg1193, DFE_BB_CFG1193_REG_RXTDD_TIMER_DL3_15_0)
+ |(CSL_FEXT(hDfeBb->regs->cfg1192, DFE_BB_CFG1192_REG_RXTDD_TIMER_DL3_23_16) << 16);
+
+ data = hDfeBb->regs->cfg1184;
+ arg->enable = CSL_FEXT(data, DFE_BB_CFG1184_REG_RXTDD_EN);
+ arg->dataMode = (DfeFl_BbTddDataMode)CSL_FEXT(data, DFE_BB_CFG1184_REG_RXTDD_DATAMODE);
+ arg->carrierType = CSL_FEXT(data, DFE_BB_CFG1184_REG_RXTDD_CT_TYPE);
+}
+
+/** ============================================================================
+ * @n@b dfeFl_BbSetRxTddSsel
+ *
+ * @b Description
+ * @n [add content]
+ *
+ * @b Arguments
+ * @verbatim
+ hDfeBb [add content]
+ ssel [add content]
+ @endverbatim
+ *
+ * <b> Return Value </b> None
+ *
+ * <b> Pre Condition </b>
+ * @n [add content]
+ *
+ * <b> Post Condition </b>
+ * @n [add content]
+ *
+ * @b Reads
+ * @n None
+ *
+ * @b Writes
+ * @n see below,
+ * DFE_BB_CFG1184_REG_RXTDD_SSEL
+ *
+ * @b Example
+ * @verbatim
+ [add content]
+ @endverbatim
+ * ===========================================================================
+ */
+CSL_IDEF_INLINE void
+dfeFl_BbSetRxTddSsel(DfeFl_BbHandle hDfeBb, uint32_t ssel)
+{
+ CSL_FINS(hDfeBb->regs->cfg1184, DFE_BB_CFG1184_REG_RXTDD_SSEL, ssel);
+}
+
+/** ============================================================================
+ * @n@b dfeFl_BbGetRxTddSsel
+ *
+ * @b Description
+ * @n [add content]
+ *
+ * @b Arguments
+ * @verbatim
+ hDfeBb [add content]
+ ssel [add content]
+ @endverbatim
+ *
+ * <b> Return Value </b> None
+ *
+ * <b> Pre Condition </b>
+ * @n [add content]
+ *
+ * <b> Post Condition </b>
+ * @n [add content]
+ *
+ * @b Reads
+ * @n see below,
+ * DFE_BB_CFG1184_REG_RXTDD_SSEL
+ *
+ * @b Writes
+ * @n None
+ *
+ * @b Example
+ * @verbatim
+ [add content]
+ @endverbatim
+ * ===========================================================================
+ */
+CSL_IDEF_INLINE void
+dfeFl_BbGetRxTddSsel(DfeFl_BbHandle hDfeBb, uint32_t *ssel)
+{
+ *ssel = CSL_FEXT(hDfeBb->regs->cfg1184, DFE_BB_CFG1184_REG_RXTDD_SSEL);
+}
+
+/** ============================================================================
+ * @n@b dfeFl_BbConfigTxpm
+ *
+ * @b Description
+ * @n [add content]
+ *
+ * @b Arguments
+ * @verbatim
+ hDfeBb [add content]
+ arg [add content]
+ @endverbatim
+ *
+ * <b> Return Value </b> None
+ *
+ * <b> Pre Condition </b>
+ * @n [add content]
+ *
+ * <b> Post Condition </b>
+ * @n [add content]
+ *
+ * @b Reads
+ * @n None
+ *
+ * @b Writes
+ * @n see below,
+ * DFE_BB_SYNCDLY_TXPM0_REG_SYNC_DLY_15_0
+ * DFE_BB_CFG_TXPM0_REG_IN_SOURCE
+ * DFE_BB_CFG_TXPM0_REG_OUT_FORMAT
+ * DFE_BB_SYNC_PWR_TXPM0_REG_PWR_UPDATE
+ * DFE_BB_PDINTERVAL_HI_TXPM0_REG_INTG_PD_23_16
+ * DFE_BB_CFG_TXPM0_REG_TDDMODE
+ * DFE_BB_INTERVAL_LO_TXPM0_REG_INTERVAL_15_0
+ * DFE_BB_CFG_TXPM0_REG_ENABLE
+ * DFE_BB_PDINTERVAL_HI_TXPM0_REG_INTERVAL_23_16
+ * DFE_BB_SYNC_PWR_TXPM0_REG_SYNC_DLY_23_16
+ * DFE_BB_CFG_TXPM0_REG_COUNT_SOURCE
+ * DFE_BB_PD_LO_TXPM0_REG_INTG_PD_15_0
+ *
+ * @b Example
+ * @verbatim
+ [add content]
+ @endverbatim
+ * ===========================================================================
+ */
+CSL_IDEF_INLINE void
+dfeFl_BbConfigTxpm(DfeFl_BbHandle hDfeBb, DfeFl_BbPowerMeterConfig * arg)
+{
+ volatile uint32_t *regs = &hDfeBb->regs->cfg_txpm0 + arg->pmId * 8;
+
+ // enable, out_format, ct, in_source, tdd_mode
+ regs[0] = CSL_FMK(DFE_BB_CFG_TXPM0_REG_ENABLE, arg->enable)
+ | CSL_FMK(DFE_BB_CFG_TXPM0_REG_OUT_FORMAT, arg->outFormat)
+ | CSL_FMK(DFE_BB_CFG_TXPM0_REG_COUNT_SOURCE, arg->countSource)
+ | CSL_FMK(DFE_BB_CFG_TXPM0_REG_IN_SOURCE, arg->inSource)
+ | CSL_FMK(DFE_BB_CFG_TXPM0_REG_TDDMODE, arg->tddMode);
+ // sync dly [15:0]
+ regs[1] = CSL_FMK(DFE_BB_SYNCDLY_TXPM0_REG_SYNC_DLY_15_0, arg->syncDly);
+ // interval [15:0]
+ regs[2] = CSL_FMK(DFE_BB_INTERVAL_LO_TXPM0_REG_INTERVAL_15_0, arg->interval);
+ // interval [23:16], intg_pd [23:16]
+ regs[3] = CSL_FMK(DFE_BB_PDINTERVAL_HI_TXPM0_REG_INTERVAL_23_16, arg->interval >> 16)
+ | CSL_FMK(DFE_BB_PDINTERVAL_HI_TXPM0_REG_INTG_PD_23_16, arg->intgPd >> 16);
+ // intg_pd [15:0]
+ regs[4] = CSL_FMK(DFE_BB_PD_LO_TXPM0_REG_INTG_PD_15_0, arg->intgPd);
+ // pwr_update, sync_dly [23:16]
+ regs[5] = CSL_FMK(DFE_BB_SYNC_PWR_TXPM0_REG_PWR_UPDATE, arg->pwrUpdate)
+ | CSL_FMK(DFE_BB_SYNC_PWR_TXPM0_REG_SYNC_DLY_23_16, arg->syncDly >> 16);
+
+}
+
+/** ============================================================================
+ * @n@b dfeFl_BbQueryTxpmConfig
+ *
+ * @b Description
+ * @n [add content]
+ *
+ * @b Arguments
+ * @verbatim
+ hDfeBb [add content]
+ arg [add content]
+ @endverbatim
+ *
+ * <b> Return Value </b> None
+ *
+ * <b> Pre Condition </b>
+ * @n [add content]
+ *
+ * <b> Post Condition </b>
+ * @n [add content]
+ *
+ * @b Reads
+ * @n see below,
+ * DFE_BB_SYNCDLY_TXPM0_REG_SYNC_DLY_15_0
+ * DFE_BB_CFG_TXPM0_REG_IN_SOURCE
+ * DFE_BB_CFG_TXPM0_REG_OUT_FORMAT
+ * DFE_BB_SYNC_PWR_TXPM0_REG_PWR_UPDATE
+ * DFE_BB_PDINTERVAL_HI_TXPM0_REG_INTG_PD_23_16
+ * DFE_BB_CFG_TXPM0_REG_TDDMODE
+ * DFE_BB_INTERVAL_LO_TXPM0_REG_INTERVAL_15_0
+ * DFE_BB_CFG_TXPM0_REG_ENABLE
+ * DFE_BB_PDINTERVAL_HI_TXPM0_REG_INTERVAL_23_16
+ * DFE_BB_SYNC_PWR_TXPM0_REG_SYNC_DLY_23_16
+ * DFE_BB_CFG_TXPM0_REG_COUNT_SOURCE
+ * DFE_BB_PD_LO_TXPM0_REG_INTG_PD_15_0
+ *
+ * @b Writes
+ * @n None
+ *
+ * @b Example
+ * @verbatim
+ [add content]
+ @endverbatim
+ * ===========================================================================
+ */
+CSL_IDEF_INLINE void
+dfeFl_BbQueryTxpmConfig(DfeFl_BbHandle hDfeBb, DfeFl_BbPowerMeterConfig * arg)
+{
+ uint32_t data;
+ volatile uint32_t *regs = &hDfeBb->regs->cfg_txpm0 + arg->pmId * 8;
+
+ // enable, out_format, ct, in_source, tdd_mode
+ data = regs[0];
+ arg->enable = (DfeFl_BbPowMtrEnable)CSL_FEXT(data, DFE_BB_CFG_TXPM0_REG_ENABLE);
+ arg->outFormat = (DfeFl_BbPowMtrOutFormat)CSL_FEXT(data, DFE_BB_CFG_TXPM0_REG_OUT_FORMAT);
+ arg->countSource = CSL_FEXT(data, DFE_BB_CFG_TXPM0_REG_COUNT_SOURCE);
+ arg->inSource = (DfeFl_BbPowMtrInSource)CSL_FEXT(data, DFE_BB_CFG_TXPM0_REG_IN_SOURCE);
+ arg->tddMode = (DfeFl_BbPowMtrTddMode)CSL_FEXT(data, DFE_BB_CFG_TXPM0_REG_TDDMODE);
+
+ // sync dly [15:0]
+ data = regs[1];
+ arg->syncDly = CSL_FEXT(data, DFE_BB_SYNCDLY_TXPM0_REG_SYNC_DLY_15_0);
+ // interval [15:0]
+ data = regs[2];
+ arg->interval = CSL_FEXT(data, DFE_BB_INTERVAL_LO_TXPM0_REG_INTERVAL_15_0);
+ // interval [23:16], intg_pd [23:16]
+ data = regs[3];
+ arg->interval |= CSL_FEXT(data, DFE_BB_PDINTERVAL_HI_TXPM0_REG_INTERVAL_23_16) << 16;
+ arg->intgPd = CSL_FEXT(data, DFE_BB_PDINTERVAL_HI_TXPM0_REG_INTG_PD_23_16) << 16;
+ // intg_pd [15:0]
+ data = regs[4];
+ arg->intgPd |= CSL_FEXT(data, DFE_BB_PD_LO_TXPM0_REG_INTG_PD_15_0);
+
+ // pwr_update, sync_dly [23:16]
+ data = regs[5];
+ arg->pwrUpdate = CSL_FEXT(data, DFE_BB_SYNC_PWR_TXPM0_REG_PWR_UPDATE);
+ arg->syncDly |= CSL_FEXT(data, DFE_BB_SYNC_PWR_TXPM0_REG_SYNC_DLY_23_16) << 16;
+}
+
+/** ============================================================================
+ * @n@b dfeFl_BbSetTxpmSsel
+ *
+ * @b Description
+ * @n [add content]
+ *
+ * @b Arguments
+ * @verbatim
+ hDfeBb [add content]
+ pmId [add content]
+ ssel [add content]
+ @endverbatim
+ *
+ * <b> Return Value </b> None
+ *
+ * <b> Pre Condition </b>
+ * @n [add content]
+ *
+ * <b> Post Condition </b>
+ * @n [add content]
+ *
+ * @b Reads
+ * @n None
+ *
+ * @b Writes
+ * @n None
+ *
+ * @b Example
+ * @verbatim
+ [add content]
+ @endverbatim
+ * ===========================================================================
+ */
+CSL_IDEF_INLINE void
+dfeFl_BbSetTxpmSsel(DfeFl_BbHandle hDfeBb, uint32_t pmId, uint32_t ssel)
+{
+ volatile uint32_t *regs = &hDfeBb->regs->cfg48;
+ uint32_t r = pmId / 4;
+ uint32_t b = (pmId % 4) * 4;
+
+ CSL_FINSR(regs[r], b+3, b, ssel);
+}
+
+/** ============================================================================
+ * @n@b dfeFl_BbGetTxpmSsel
+ *
+ * @b Description
+ * @n [add content]
+ *
+ * @b Arguments
+ * @verbatim
+ hDfeBb [add content]
+ pmId [add content]
+ ssel [add content]
+ @endverbatim
+ *
+ * <b> Return Value </b> None
+ *
+ * <b> Pre Condition </b>
+ * @n [add content]
+ *
+ * <b> Post Condition </b>
+ * @n [add content]
+ *
+ * @b Reads
+ * @n None
+ *
+ * @b Writes
+ * @n None
+ *
+ * @b Example
+ * @verbatim
+ [add content]
+ @endverbatim
+ * ===========================================================================
+ */
+CSL_IDEF_INLINE void
+dfeFl_BbGetTxpmSsel(DfeFl_BbHandle hDfeBb, uint32_t pmId, uint32_t *ssel)
+{
+ volatile uint32_t *regs = &hDfeBb->regs->cfg48;
+ uint32_t r = pmId / 4;
+ uint32_t b = (pmId % 4) * 4;
+
+ *ssel = CSL_FEXTR(regs[r], b+3, b);
+}
+
+/** ============================================================================
+ * @n@b dfeFl_BbConfigRxpm
+ *
+ * @b Description
+ * @n [add content]
+ *
+ * @b Arguments
+ * @verbatim
+ hDfeBb [add content]
+ arg [add content]
+ @endverbatim
+ *
+ * <b> Return Value </b> None
+ *
+ * <b> Pre Condition </b>
+ * @n [add content]
+ *
+ * <b> Post Condition </b>
+ * @n [add content]
+ *
+ * @b Reads
+ * @n None
+ *
+ * @b Writes
+ * @n see below,
+ * DFE_BB_CFG_RXPM0_REG_OUT_FORMAT
+ * DFE_BB_SYNC_PWR_RXPM0_REG_SYNC_DLY_23_16
+ * DFE_BB_PDINTERVAL_HI_RXPM0_REG_INTG_PD_23_16
+ * DFE_BB_PDINTERVAL_HI_RXPM0_REG_INTERVAL_23_16
+ * DFE_BB_INTERVAL_LO_RXPM0_REG_INTERVAL_15_0
+ * DFE_BB_SYNCDLY_RXPM0_REG_SYNC_DLY_15_0
+ * DFE_BB_SYNC_PWR_RXPM0_REG_PWR_UPDATE
+ * DFE_BB_RXPM_MAX_DB0_REG_MAX_DB
+ * DFE_BB_CFG_RXPM0_REG_COUNT_SOURCE
+ * DFE_BB_CFG_RXPM0_REG_TDDMODE
+ * DFE_BB_PD_LO_RXPM0_REG_INTG_PD_15_0
+ * DFE_BB_CFG_RXPM0_REG_IN_SOURCE
+ * DFE_BB_CFG_RXPM0_REG_ENABLE
+ *
+ * @b Example
+ * @verbatim
+ [add content]
+ @endverbatim
+ * ===========================================================================
+ */
+CSL_IDEF_INLINE void
+dfeFl_BbConfigRxpm(DfeFl_BbHandle hDfeBb, DfeFl_BbPowerMeterConfig * arg)
+{
+ volatile uint32_t *regs = &hDfeBb->regs->cfg_rxpm0 + arg->pmId * 8;
+
+ // enable, out_format, ct, in_source, tdd_mode
+ regs[0] = CSL_FMK(DFE_BB_CFG_RXPM0_REG_ENABLE, arg->enable)
+ | CSL_FMK(DFE_BB_CFG_RXPM0_REG_OUT_FORMAT, arg->outFormat)
+ | CSL_FMK(DFE_BB_CFG_RXPM0_REG_COUNT_SOURCE, arg->countSource)
+ | CSL_FMK(DFE_BB_CFG_RXPM0_REG_IN_SOURCE, arg->inSource)
+ | CSL_FMK(DFE_BB_CFG_RXPM0_REG_TDDMODE, arg->tddMode);
+ // sync dly [15:0]
+ regs[1] = CSL_FMK(DFE_BB_SYNCDLY_RXPM0_REG_SYNC_DLY_15_0, arg->syncDly);
+ // interval [15:0]
+ regs[2] = CSL_FMK(DFE_BB_INTERVAL_LO_RXPM0_REG_INTERVAL_15_0, arg->interval);
+ // interval [23:16], intg_pd [23:16]
+ regs[3] = CSL_FMK(DFE_BB_PDINTERVAL_HI_RXPM0_REG_INTERVAL_23_16, arg->interval >> 16)
+ | CSL_FMK(DFE_BB_PDINTERVAL_HI_RXPM0_REG_INTG_PD_23_16, arg->intgPd >> 16);
+ // intg_pd [15:0]
+ regs[4] = CSL_FMK(DFE_BB_PD_LO_RXPM0_REG_INTG_PD_15_0, arg->intgPd);
+ // pwr_update, sync_dly [23:16]
+ regs[5] = CSL_FMK(DFE_BB_SYNC_PWR_RXPM0_REG_PWR_UPDATE, arg->pwrUpdate)
+ | CSL_FMK(DFE_BB_SYNC_PWR_RXPM0_REG_SYNC_DLY_23_16, arg->syncDly >> 16);
+ // max_db
+ regs[6] = CSL_FMK(DFE_BB_RXPM_MAX_DB0_REG_MAX_DB, arg->maxDb);
+}
+
+/** ============================================================================
+ * @n@b dfeFl_BbQueryRxpmConfig
+ *
+ * @b Description
+ * @n [add content]
+ *
+ * @b Arguments
+ * @verbatim
+ hDfeBb [add content]
+ arg [add content]
+ @endverbatim
+ *
+ * <b> Return Value </b> None
+ *
+ * <b> Pre Condition </b>
+ * @n [add content]
+ *
+ * <b> Post Condition </b>
+ * @n [add content]
+ *
+ * @b Reads
+ * @n see below,
+ * DFE_BB_CFG_RXPM0_REG_OUT_FORMAT
+ * DFE_BB_SYNC_PWR_RXPM0_REG_SYNC_DLY_23_16
+ * DFE_BB_PDINTERVAL_HI_RXPM0_REG_INTG_PD_23_16
+ * DFE_BB_PDINTERVAL_HI_RXPM0_REG_INTERVAL_23_16
+ * DFE_BB_INTERVAL_LO_RXPM0_REG_INTERVAL_15_0
+ * DFE_BB_SYNCDLY_RXPM0_REG_SYNC_DLY_15_0
+ * DFE_BB_SYNC_PWR_RXPM0_REG_PWR_UPDATE
+ * DFE_BB_RXPM_MAX_DB0_REG_MAX_DB
+ * DFE_BB_CFG_RXPM0_REG_COUNT_SOURCE
+ * DFE_BB_CFG_RXPM0_REG_TDDMODE
+ * DFE_BB_PD_LO_RXPM0_REG_INTG_PD_15_0
+ * DFE_BB_CFG_RXPM0_REG_IN_SOURCE
+ * DFE_BB_CFG_RXPM0_REG_ENABLE
+ *
+ * @b Writes
+ * @n None
+ *
+ * @b Example
+ * @verbatim
+ [add content]
+ @endverbatim
+ * ===========================================================================
+ */
+CSL_IDEF_INLINE void
+dfeFl_BbQueryRxpmConfig(DfeFl_BbHandle hDfeBb, DfeFl_BbPowerMeterConfig * arg)
+{
+ uint32_t data;
+ volatile uint32_t *regs = &hDfeBb->regs->cfg_rxpm0 + arg->pmId * 8;
+
+ // enable, out_format, ct, in_source, tdd_mode
+ data = regs[0];
+ arg->enable = (DfeFl_BbPowMtrEnable)CSL_FEXT(data, DFE_BB_CFG_RXPM0_REG_ENABLE);
+ arg->outFormat = (DfeFl_BbPowMtrOutFormat)CSL_FEXT(data, DFE_BB_CFG_RXPM0_REG_OUT_FORMAT);
+ arg->countSource = CSL_FEXT(data, DFE_BB_CFG_RXPM0_REG_COUNT_SOURCE);
+ arg->inSource = (DfeFl_BbPowMtrInSource)CSL_FEXT(data, DFE_BB_CFG_RXPM0_REG_IN_SOURCE);
+ arg->tddMode = (DfeFl_BbPowMtrTddMode)CSL_FEXT(data, DFE_BB_CFG_RXPM0_REG_TDDMODE);
+
+ // sync dly [15:0]
+ data = regs[1];
+ arg->syncDly = CSL_FEXT(data, DFE_BB_SYNCDLY_RXPM0_REG_SYNC_DLY_15_0);
+ // interval [15:0]
+ data = regs[2];
+ arg->interval = CSL_FEXT(data, DFE_BB_INTERVAL_LO_RXPM0_REG_INTERVAL_15_0);
+ // interval [23:16], intg_pd [23:16]
+ data = regs[3];
+ arg->interval |= CSL_FEXT(data, DFE_BB_PDINTERVAL_HI_RXPM0_REG_INTERVAL_23_16) << 16;
+ arg->intgPd = CSL_FEXT(data, DFE_BB_PDINTERVAL_HI_RXPM0_REG_INTG_PD_23_16) << 16;
+ // intg_pd [15:0]
+ data = regs[4];
+ arg->intgPd |= CSL_FEXT(data, DFE_BB_PD_LO_RXPM0_REG_INTG_PD_15_0);
+
+ // pwr_update, sync_dly [23:16]
+ data = regs[5];
+ arg->pwrUpdate = CSL_FEXT(data, DFE_BB_SYNC_PWR_RXPM0_REG_PWR_UPDATE);
+ arg->syncDly |= CSL_FEXT(data, DFE_BB_SYNC_PWR_RXPM0_REG_SYNC_DLY_23_16) << 16;
+ // max_db
+ data = regs[6];
+ arg->maxDb = CSL_FEXT(data, DFE_BB_RXPM_MAX_DB0_REG_MAX_DB);
+
+}
+
+/** ============================================================================
+ * @n@b dfeFl_BbSetRxpmSsel
+ *
+ * @b Description
+ * @n [add content]
+ *
+ * @b Arguments
+ * @verbatim
+ hDfeBb [add content]
+ pmId [add content]
+ ssel [add content]
+ @endverbatim
+ *
+ * <b> Return Value </b> None
+ *
+ * <b> Pre Condition </b>
+ * @n [add content]
+ *
+ * <b> Post Condition </b>
+ * @n [add content]
+ *
+ * @b Reads
+ * @n None
+ *
+ * @b Writes
+ * @n None
+ *
+ * @b Example
+ * @verbatim
+ [add content]
+ @endverbatim
+ * ===========================================================================
+ */
+CSL_IDEF_INLINE void
+dfeFl_BbSetRxpmSsel(DfeFl_BbHandle hDfeBb, uint32_t pmId, uint32_t ssel)
+{
+ volatile uint32_t *regs = &hDfeBb->regs->cfg52;
+ uint32_t r = pmId / 4;
+ uint32_t b = (pmId % 4) * 4;
+
+ CSL_FINSR(regs[r], b+3, b, ssel);
+}
+
+/** ============================================================================
+ * @n@b dfeFl_BbGetRxpmSsel
+ *
+ * @b Description
+ * @n [add content]
+ *
+ * @b Arguments
+ * @verbatim
+ hDfeBb [add content]
+ pmId [add content]
+ ssel [add content]
+ @endverbatim
+ *
+ * <b> Return Value </b> None
+ *
+ * <b> Pre Condition </b>
+ * @n [add content]
+ *
+ * <b> Post Condition </b>
+ * @n [add content]
+ *
+ * @b Reads
+ * @n None
+ *
+ * @b Writes
+ * @n None
+ *
+ * @b Example
+ * @verbatim
+ [add content]
+ @endverbatim
+ * ===========================================================================
+ */
+CSL_IDEF_INLINE void
+dfeFl_BbGetRxpmSsel(DfeFl_BbHandle hDfeBb, uint32_t pmId, uint32_t *ssel)
+{
+ volatile uint32_t *regs = &hDfeBb->regs->cfg52;
+ uint32_t r = pmId / 4;
+ uint32_t b = (pmId % 4) * 4;
+
+ *ssel = CSL_FEXTR(regs[r], b+3, b);
+}
+
+/** ============================================================================
+ * @n@b dfeFl_BbDisableTxpmUpdate
+ *
+ * @b Description
+ * @n [add content]
+ *
+ * @b Arguments
+ * @verbatim
+ hDfeBb [add content]
+ arg [add content]
+ @endverbatim
+ *
+ * <b> Return Value </b> None
+ *
+ * <b> Pre Condition </b>
+ * @n [add content]
+ *
+ * <b> Post Condition </b>
+ * @n [add content]
+ *
+ * @b Reads
+ * @n None
+ *
+ * @b Writes
+ * @n None
+ *
+ * @b Example
+ * @verbatim
+ [add content]
+ @endverbatim
+ * ===========================================================================
+ */
+CSL_IDEF_INLINE void
+dfeFl_BbDisableTxpmUpdate(DfeFl_BbHandle hDfeBb, DfeFl_BbDisablePowMterUpdateConfig * arg)
+{
+ CSL_FINSR(hDfeBb->regs->txpm_update_disable, arg->pmId, arg->pmId, arg->disableUpdate);
+}
+
+/** ============================================================================
+ * @n@b dfeFl_BbQueryDisableTxpmUpdate
+ *
+ * @b Description
+ * @n [add content]
+ *
+ * @b Arguments
+ * @verbatim
+ hDfeBb [add content]
+ arg [add content]
+ @endverbatim
+ *
+ * <b> Return Value </b> None
+ *
+ * <b> Pre Condition </b>
+ * @n [add content]
+ *
+ * <b> Post Condition </b>
+ * @n [add content]
+ *
+ * @b Reads
+ * @n None
+ *
+ * @b Writes
+ * @n None
+ *
+ * @b Example
+ * @verbatim
+ [add content]
+ @endverbatim
+ * ===========================================================================
+ */
+CSL_IDEF_INLINE void
+dfeFl_BbQueryDisableTxpmUpdate(DfeFl_BbHandle hDfeBb, DfeFl_BbDisablePowMterUpdateConfig * arg)
+{
+ arg->disableUpdate = CSL_FEXTR(hDfeBb->regs->txpm_update_disable, arg->pmId, arg->pmId);
+}
+
+/** ============================================================================
+ * @n@b dfeFl_BbDisableRxpmUpdate
+ *
+ * @b Description
+ * @n [add content]
+ *
+ * @b Arguments
+ * @verbatim
+ hDfeBb [add content]
+ arg [add content]
+ @endverbatim
+ *
+ * <b> Return Value </b> None
+ *
+ * <b> Pre Condition </b>
+ * @n [add content]
+ *
+ * <b> Post Condition </b>
+ * @n [add content]
+ *
+ * @b Reads
+ * @n None
+ *
+ * @b Writes
+ * @n None
+ *
+ * @b Example
+ * @verbatim
+ [add content]
+ @endverbatim
+ * ===========================================================================
+ */
+CSL_IDEF_INLINE void
+dfeFl_BbDisableRxpmUpdate(DfeFl_BbHandle hDfeBb, DfeFl_BbDisablePowMterUpdateConfig * arg)
+{
+ CSL_FINSR(hDfeBb->regs->rxpm_update_disable, arg->pmId, arg->pmId, arg->disableUpdate);
+}
+
+/** ============================================================================
+ * @n@b dfeFl_BbQueryDisableRxpmUpdate
+ *
+ * @b Description
+ * @n [add content]
+ *
+ * @b Arguments
+ * @verbatim
+ hDfeBb [add content]
+ arg [add content]
+ @endverbatim
+ *
+ * <b> Return Value </b> None
+ *
+ * <b> Pre Condition </b>
+ * @n [add content]
+ *
+ * <b> Post Condition </b>
+ * @n [add content]
+ *
+ * @b Reads
+ * @n None
+ *
+ * @b Writes
+ * @n None
+ *
+ * @b Example
+ * @verbatim
+ [add content]
+ @endverbatim
+ * ===========================================================================
+ */
+CSL_IDEF_INLINE void
+dfeFl_BbQueryDisableRxpmUpdate(DfeFl_BbHandle hDfeBb, DfeFl_BbDisablePowMterUpdateConfig * arg)
+{
+ arg->disableUpdate = CSL_FEXTR(hDfeBb->regs->rxpm_update_disable, arg->pmId, arg->pmId);
+}
+
+/** ============================================================================
+ * @n@b dfeFl_BbEnableTxpmIntr
+ *
+ * @b Description
+ * @n [add content]
+ *
+ * @b Arguments
+ * @verbatim
+ hDfeBb [add content]
+ pmId [add content]
+ @endverbatim
+ *
+ * <b> Return Value </b> None
+ *
+ * <b> Pre Condition </b>
+ * @n [add content]
+ *
+ * <b> Post Condition </b>
+ * @n [add content]
+ *
+ * @b Reads
+ * @n None
+ *
+ * @b Writes
+ * @n None
+ *
+ * @b Example
+ * @verbatim
+ [add content]
+ @endverbatim
+ * ===========================================================================
+ */
+CSL_IDEF_INLINE void
+dfeFl_BbEnableTxpmIntr(DfeFl_BbHandle hDfeBb, uint32_t pmId)
+{
+ CSL_FINSR(hDfeBb->regs->intmask0, pmId, pmId, 1);
+}
+
+/** ============================================================================
+ * @n@b dfeFl_BbDisableTxpmIntr
+ *
+ * @b Description
+ * @n [add content]
+ *
+ * @b Arguments
+ * @verbatim
+ hDfeBb [add content]
+ pmId [add content]
+ @endverbatim
+ *
+ * <b> Return Value </b> None
+ *
+ * <b> Pre Condition </b>
+ * @n [add content]
+ *
+ * <b> Post Condition </b>
+ * @n [add content]
+ *
+ * @b Reads
+ * @n None
+ *
+ * @b Writes
+ * @n None
+ *
+ * @b Example
+ * @verbatim
+ [add content]
+ @endverbatim
+ * ===========================================================================
+ */
+CSL_IDEF_INLINE void
+dfeFl_BbDisableTxpmIntr(DfeFl_BbHandle hDfeBb, uint32_t pmId)
+{
+ CSL_FINSR(hDfeBb->regs->intmask0, pmId, pmId, 0);
+}
+
+/** ============================================================================
+ * @n@b dfeFl_BbEnableTxpmAuxIntr
+ *
+ * @b Description
+ * @n [add content]
+ *
+ * @b Arguments
+ * @verbatim
+ hDfeBb [add content]
+ pmId [add content]
+ @endverbatim
+ *
+ * <b> Return Value </b> None
+ *
+ * <b> Pre Condition </b>
+ * @n [add content]
+ *
+ * <b> Post Condition </b>
+ * @n [add content]
+ *
+ * @b Reads
+ * @n None
+ *
+ * @b Writes
+ * @n None
+ *
+ * @b Example
+ * @verbatim
+ [add content]
+ @endverbatim
+ * ===========================================================================
+ */
+CSL_IDEF_INLINE void
+dfeFl_BbEnableTxpmAuxIntr(DfeFl_BbHandle hDfeBb, uint32_t pmId)
+{
+ CSL_FINSR(hDfeBb->regs->txpm_auxint_mask, pmId, pmId, 1);
+}
+
+/** ============================================================================
+ * @n@b dfeFl_BbDisableTxpmAuxIntr
+ *
+ * @b Description
+ * @n [add content]
+ *
+ * @b Arguments
+ * @verbatim
+ hDfeBb [add content]
+ pmId [add content]
+ @endverbatim
+ *
+ * <b> Return Value </b> None
+ *
+ * <b> Pre Condition </b>
+ * @n [add content]
+ *
+ * <b> Post Condition </b>
+ * @n [add content]
+ *
+ * @b Reads
+ * @n None
+ *
+ * @b Writes
+ * @n None
+ *
+ * @b Example
+ * @verbatim
+ [add content]
+ @endverbatim
+ * ===========================================================================
+ */
+CSL_IDEF_INLINE void
+dfeFl_BbDisableTxpmAuxIntr(DfeFl_BbHandle hDfeBb, uint32_t pmId)
+{
+ CSL_FINSR(hDfeBb->regs->txpm_auxint_mask, pmId, pmId, 0);
+}
+
+/** ============================================================================
+ * @n@b dfeFl_BbEnableRxpmIntr
+ *
+ * @b Description
+ * @n [add content]
+ *
+ * @b Arguments
+ * @verbatim
+ hDfeBb [add content]
+ pmId [add content]
+ @endverbatim
+ *
+ * <b> Return Value </b> None
+ *
+ * <b> Pre Condition </b>
+ * @n [add content]
+ *
+ * <b> Post Condition </b>
+ * @n [add content]
+ *
+ * @b Reads
+ * @n None
+ *
+ * @b Writes
+ * @n None
+ *
+ * @b Example
+ * @verbatim
+ [add content]
+ @endverbatim
+ * ===========================================================================
+ */
+CSL_IDEF_INLINE void
+dfeFl_BbEnableRxpmIntr(DfeFl_BbHandle hDfeBb, uint32_t pmId)
+{
+ CSL_FINSR(hDfeBb->regs->intmask1, pmId, pmId, 1);
+}
+
+/** ============================================================================
+ * @n@b dfeFl_BbDisableRxpmIntr
+ *
+ * @b Description
+ * @n [add content]
+ *
+ * @b Arguments
+ * @verbatim
+ hDfeBb [add content]
+ pmId [add content]
+ @endverbatim
+ *
+ * <b> Return Value </b> None
+ *
+ * <b> Pre Condition </b>
+ * @n [add content]
+ *
+ * <b> Post Condition </b>
+ * @n [add content]
+ *
+ * @b Reads
+ * @n None
+ *
+ * @b Writes
+ * @n None
+ *
+ * @b Example
+ * @verbatim
+ [add content]
+ @endverbatim
+ * ===========================================================================
+ */
+CSL_IDEF_INLINE void
+dfeFl_BbDisableRxpmIntr(DfeFl_BbHandle hDfeBb, uint32_t pmId)
+{
+ CSL_FINSR(hDfeBb->regs->intmask1, pmId, pmId, 0);
+}
+
+/** ============================================================================
+ * @n@b dfeFl_BbEnableRxpmAuxIntr
+ *
+ * @b Description
+ * @n [add content]
+ *
+ * @b Arguments
+ * @verbatim
+ hDfeBb [add content]
+ pmId [add content]
+ @endverbatim
+ *
+ * <b> Return Value </b> None
+ *
+ * <b> Pre Condition </b>
+ * @n [add content]
+ *
+ * <b> Post Condition </b>
+ * @n [add content]
+ *
+ * @b Reads
+ * @n None
+ *
+ * @b Writes
+ * @n None
+ *
+ * @b Example
+ * @verbatim
+ [add content]
+ @endverbatim
+ * ===========================================================================
+ */
+CSL_IDEF_INLINE void
+dfeFl_BbEnableRxpmAuxIntr(DfeFl_BbHandle hDfeBb, uint32_t pmId)
+{
+ CSL_FINSR(hDfeBb->regs->rxpm_auxint_mask, pmId, pmId, 1);
+}
+
+/** ============================================================================
+ * @n@b dfeFl_BbDisableRxpmAuxIntr
+ *
+ * @b Description
+ * @n [add content]
+ *
+ * @b Arguments
+ * @verbatim
+ hDfeBb [add content]
+ pmId [add content]
+ @endverbatim
+ *
+ * <b> Return Value </b> None
+ *
+ * <b> Pre Condition </b>
+ * @n [add content]
+ *
+ * <b> Post Condition </b>
+ * @n [add content]
+ *
+ * @b Reads
+ * @n None
+ *
+ * @b Writes
+ * @n None
+ *
+ * @b Example
+ * @verbatim
+ [add content]
+ @endverbatim
+ * ===========================================================================
+ */
+CSL_IDEF_INLINE void
+dfeFl_BbDisableRxpmAuxIntr(DfeFl_BbHandle hDfeBb, uint32_t pmId)
+{
+ CSL_FINSR(hDfeBb->regs->rxpm_auxint_mask, pmId, pmId, 0);
+}
+
+/** ============================================================================
+ * @n@b dfeFl_BbClearTxpmIntrStatus
+ *
+ * @b Description
+ * @n [add content]
+ *
+ * @b Arguments
+ * @verbatim
+ hDfeBb [add content]
+ pmId [add content]
+ @endverbatim
+ *
+ * <b> Return Value </b> None
+ *
+ * <b> Pre Condition </b>
+ * @n [add content]
+ *
+ * <b> Post Condition </b>
+ * @n [add content]
+ *
+ * @b Reads
+ * @n None
+ *
+ * @b Writes
+ * @n None
+ *
+ * @b Example
+ * @verbatim
+ [add content]
+ @endverbatim
+ * ===========================================================================
+ */
+CSL_IDEF_INLINE void
+dfeFl_BbClearTxpmIntrStatus(DfeFl_BbHandle hDfeBb, uint32_t pmId)
+{
+ hDfeBb->regs->intstatus0 = ~(1u << pmId);
+}
+
+/** ============================================================================
+ * @n@b dfeFl_BbClearRxpmIntrStatus
+ *
+ * @b Description
+ * @n [add content]
+ *
+ * @b Arguments
+ * @verbatim
+ hDfeBb [add content]
+ pmId [add content]
+ @endverbatim
+ *
+ * <b> Return Value </b> None
+ *
+ * <b> Pre Condition </b>
+ * @n [add content]
+ *
+ * <b> Post Condition </b>
+ * @n [add content]
+ *
+ * @b Reads
+ * @n None
+ *
+ * @b Writes
+ * @n None
+ *
+ * @b Example
+ * @verbatim
+ [add content]
+ @endverbatim
+ * ===========================================================================
+ */
+CSL_IDEF_INLINE void
+dfeFl_BbClearRxpmIntrStatus(DfeFl_BbHandle hDfeBb, uint32_t pmId)
+{
+ hDfeBb->regs->intstatus1 = ~(1u << pmId);
+}
+
+/** ============================================================================
+ * @n@b dfeFl_BbQueryTxpmIntrStatus
+ *
+ * @b Description
+ * @n [add content]
+ *
+ * @b Arguments
+ * @verbatim
+ hDfeBb [add content]
+ pmId [add content]
+ status [add content]
+ @endverbatim
+ *
+ * <b> Return Value </b> None
+ *
+ * <b> Pre Condition </b>
+ * @n [add content]
+ *
+ * <b> Post Condition </b>
+ * @n [add content]
+ *
+ * @b Reads
+ * @n None
+ *
+ * @b Writes
+ * @n None
+ *
+ * @b Example
+ * @verbatim
+ [add content]
+ @endverbatim
+ * ===========================================================================
+ */
+CSL_IDEF_INLINE void
+dfeFl_BbQueryTxpmIntrStatus(DfeFl_BbHandle hDfeBb, uint32_t pmId, uint32_t *status)
+{
+ *status = CSL_FEXTR(hDfeBb->regs->intstatus0, pmId, pmId);
+}
+
+/** ============================================================================
+ * @n@b dfeFl_BbQueryRxpmIntrStatus
+ *
+ * @b Description
+ * @n [add content]
+ *
+ * @b Arguments
+ * @verbatim
+ hDfeBb [add content]
+ pmId [add content]
+ status [add content]
+ @endverbatim
+ *
+ * <b> Return Value </b> None
+ *
+ * <b> Pre Condition </b>
+ * @n [add content]
+ *
+ * <b> Post Condition </b>
+ * @n [add content]
+ *
+ * @b Reads
+ * @n None
+ *
+ * @b Writes
+ * @n None
+ *
+ * @b Example
+ * @verbatim
+ [add content]
+ @endverbatim
+ * ===========================================================================
+ */
+CSL_IDEF_INLINE void
+dfeFl_BbQueryRxpmIntrStatus(DfeFl_BbHandle hDfeBb, uint32_t pmId, uint32_t *status)
+{
+ *status = CSL_FEXTR(hDfeBb->regs->intstatus1, pmId, pmId);
+}
+
+/** ============================================================================
+ * @n@b dfeFl_BbSetForceTxpmIntr
+ *
+ * @b Description
+ * @n [add content]
+ *
+ * @b Arguments
+ * @verbatim
+ hDfeBb [add content]
+ pmId [add content]
+ @endverbatim
+ *
+ * <b> Return Value </b> None
+ *
+ * <b> Pre Condition </b>
+ * @n [add content]
+ *
+ * <b> Post Condition </b>
+ * @n [add content]
+ *
+ * @b Reads
+ * @n None
+ *
+ * @b Writes
+ * @n None
+ *
+ * @b Example
+ * @verbatim
+ [add content]
+ @endverbatim
+ * ===========================================================================
+ */
+CSL_IDEF_INLINE void
+dfeFl_BbSetForceTxpmIntr(DfeFl_BbHandle hDfeBb, uint32_t pmId)
+{
+ CSL_FINSR(hDfeBb->regs->intforce0, pmId, pmId, 1);
+}
+
+/** ============================================================================
+ * @n@b dfeFl_BbClearForceTxpmIntr
+ *
+ * @b Description
+ * @n [add content]
+ *
+ * @b Arguments
+ * @verbatim
+ hDfeBb [add content]
+ pmId [add content]
+ @endverbatim
+ *
+ * <b> Return Value </b> None
+ *
+ * <b> Pre Condition </b>
+ * @n [add content]
+ *
+ * <b> Post Condition </b>
+ * @n [add content]
+ *
+ * @b Reads
+ * @n None
+ *
+ * @b Writes
+ * @n None
+ *
+ * @b Example
+ * @verbatim
+ [add content]
+ @endverbatim
+ * ===========================================================================
+ */
+CSL_IDEF_INLINE void
+dfeFl_BbClearForceTxpmIntr(DfeFl_BbHandle hDfeBb, uint32_t pmId)
+{
+ CSL_FINSR(hDfeBb->regs->intforce0, pmId, pmId, 0);
+}
+
+/** ============================================================================
+ * @n@b dfeFl_BbSetForceRxpmIntr
+ *
+ * @b Description
+ * @n [add content]
+ *
+ * @b Arguments
+ * @verbatim
+ hDfeBb [add content]
+ pmId [add content]
+ @endverbatim
+ *
+ * <b> Return Value </b> None
+ *
+ * <b> Pre Condition </b>
+ * @n [add content]
+ *
+ * <b> Post Condition </b>
+ * @n [add content]
+ *
+ * @b Reads
+ * @n None
+ *
+ * @b Writes
+ * @n None
+ *
+ * @b Example
+ * @verbatim
+ [add content]
+ @endverbatim
+ * ===========================================================================
+ */
+CSL_IDEF_INLINE void
+dfeFl_BbSetForceRxpmIntr(DfeFl_BbHandle hDfeBb, uint32_t pmId)
+{
+ CSL_FINSR(hDfeBb->regs->intforce1, pmId, pmId, 1);
+}
+
+/** ============================================================================
+ * @n@b dfeFl_BbClearForceRxpmIntr
+ *
+ * @b Description
+ * @n [add content]
+ *
+ * @b Arguments
+ * @verbatim
+ hDfeBb [add content]
+ pmId [add content]
+ @endverbatim
+ *
+ * <b> Return Value </b> None
+ *
+ * <b> Pre Condition </b>
+ * @n [add content]
+ *
+ * <b> Post Condition </b>
+ * @n [add content]
+ *
+ * @b Reads
+ * @n None
+ *
+ * @b Writes
+ * @n None
+ *
+ * @b Example
+ * @verbatim
+ [add content]
+ @endverbatim
+ * ===========================================================================
+ */
+CSL_IDEF_INLINE void
+dfeFl_BbClearForceRxpmIntr(DfeFl_BbHandle hDfeBb, uint32_t pmId)
+{
+ CSL_FINSR(hDfeBb->regs->intforce1, pmId, pmId, 0);
+}
+
+/** ============================================================================
+ * @n@b dfeFl_BbQueryTxpmResult
+ *
+ * @b Description
+ * @n [add content]
+ *
+ * @b Arguments
+ * @verbatim
+ hDfeBb [add content]
+ arg [add content]
+ @endverbatim
+ *
+ * <b> Return Value </b> None
+ *
+ * <b> Pre Condition </b>
+ * @n [add content]
+ *
+ * <b> Post Condition </b>
+ * @n [add content]
+ *
+ * @b Reads
+ * @n None
+ *
+ * @b Writes
+ * @n None
+ *
+ * @b Example
+ * @verbatim
+ [add content]
+ @endverbatim
+ * ===========================================================================
+ */
+CSL_IDEF_INLINE void
+dfeFl_BbQueryTxpmResult(DfeFl_BbHandle hDfeBb, DfeFl_BbPowMtrResult *arg)
+{
+ CSL_DFE_BB_BBTXPWRMETER_REGS data;
+
+ data = hDfeBb->regs->bbtxpwrmeter[arg->pmId];
+ arg->peakPower = data.r0;
+ arg->peakPower_extend = data.r1;
+ arg->rmsPower = data.r2;
+ arg->rmsPower_extend = data.r3;
+}
+
+/** ============================================================================
+ * @n@b dfeFl_BbQueryRxpmResult
+ *
+ * @b Description
+ * @n [add content]
+ *
+ * @b Arguments
+ * @verbatim
+ hDfeBb [add content]
+ arg [add content]
+ @endverbatim
+ *
+ * <b> Return Value </b> None
+ *
+ * <b> Pre Condition </b>
+ * @n [add content]
+ *
+ * <b> Post Condition </b>
+ * @n [add content]
+ *
+ * @b Reads
+ * @n None
+ *
+ * @b Writes
+ * @n None
+ *
+ * @b Example
+ * @verbatim
+ [add content]
+ @endverbatim
+ * ===========================================================================
+ */
+CSL_IDEF_INLINE void
+dfeFl_BbQueryRxpmResult(DfeFl_BbHandle hDfeBb, DfeFl_BbPowMtrResult *arg)
+{
+ CSL_DFE_BB_BBRXPWRMETER_REGS data;
+
+ data = hDfeBb->regs->bbrxpwrmeter[arg->pmId];
+ arg->peakPower = data.r0;
+ arg->peakPower_extend = data.r1;
+ arg->rmsPower = data.r2;
+ arg->rmsPower_extend = data.r3;
+}
+
+/** ============================================================================
+ * @n@b dfeFl_BbConfigAntcalGlobal
+ *
+ * @b Description
+ * @n [add content]
+ *
+ * @b Arguments
+ * @verbatim
+ hDfeBb [add content]
+ arg [add content]
+ @endverbatim
+ *
+ * <b> Return Value </b> None
+ *
+ * <b> Pre Condition </b>
+ * @n [add content]
+ *
+ * <b> Post Condition </b>
+ * @n [add content]
+ *
+ * @b Reads
+ * @n None
+ *
+ * @b Writes
+ * @n see below,
+ * DFE_BB_CFG120_REG_ANTCAL_INTERVAL_15_0
+ * DFE_BB_CFG121_REG_ANTCAL_INTERVAL_31_16
+ * DFE_BB_CFG122_REG_ANTCAL_TX_CT_SEL
+ * DFE_BB_CFG122_REG_ANTCAL_RX_SSEL
+ * DFE_BB_CFG123_REG_ANTCAL_EN
+ * DFE_BB_CFG122_REG_ANTCAL_TX_SSEL
+ * DFE_BB_CFG122_REG_ANTCAL_RX_CT_SEL
+ *
+ * @b Example
+ * @verbatim
+ [add content]
+ @endverbatim
+ * ===========================================================================
+ */
+CSL_IDEF_INLINE void
+dfeFl_BbConfigAntcalGlobal(DfeFl_BbHandle hDfeBb, DfeFl_BbAntCalGlobalConfig * arg)
+{
+ hDfeBb->regs->cfg120 = CSL_FMK(DFE_BB_CFG120_REG_ANTCAL_INTERVAL_15_0, arg->interval);
+ hDfeBb->regs->cfg121 = CSL_FMK(DFE_BB_CFG121_REG_ANTCAL_INTERVAL_31_16, arg->interval >> 16);
+ hDfeBb->regs->cfg122 = CSL_FMK(DFE_BB_CFG122_REG_ANTCAL_TX_CT_SEL, arg->txCarrierTypeSel)
+ | CSL_FMK(DFE_BB_CFG122_REG_ANTCAL_RX_CT_SEL, arg->rxCarrierTypeSel)
+ | CSL_FMK(DFE_BB_CFG122_REG_ANTCAL_TX_SSEL, arg->txSsel)
+ | CSL_FMK(DFE_BB_CFG122_REG_ANTCAL_RX_SSEL, arg->rxSsel);
+
+ hDfeBb->regs->cfg123 = CSL_FMK(DFE_BB_CFG123_REG_ANTCAL_EN, arg->enable);
+}
+
+/** ============================================================================
+ * @n@b dfeFl_BbQueryAntcalGlobalConfig
+ *
+ * @b Description
+ * @n [add content]
+ *
+ * @b Arguments
+ * @verbatim
+ hDfeBb [add content]
+ arg [add content]
+ @endverbatim
+ *
+ * <b> Return Value </b> None
+ *
+ * <b> Pre Condition </b>
+ * @n [add content]
+ *
+ * <b> Post Condition </b>
+ * @n [add content]
+ *
+ * @b Reads
+ * @n see below,
+ * DFE_BB_CFG122_REG_ANTCAL_RX_SSEL
+ * DFE_BB_CFG123_REG_ANTCAL_EN
+ * DFE_BB_CFG122_REG_ANTCAL_TX_CT_SEL
+ * DFE_BB_CFG122_REG_ANTCAL_TX_SSEL
+ * DFE_BB_CFG122_REG_ANTCAL_RX_CT_SEL
+ *
+ * @b Writes
+ * @n None
+ *
+ * @b Example
+ * @verbatim
+ [add content]
+ @endverbatim
+ * ===========================================================================
+ */
+CSL_IDEF_INLINE void
+dfeFl_BbQueryAntcalGlobalConfig(DfeFl_BbHandle hDfeBb, DfeFl_BbAntCalGlobalConfig * arg)
+{
+ uint32_t data;
+ arg->interval = hDfeBb->regs->cfg120 | (hDfeBb->regs->cfg121 << 16);
+
+ data = hDfeBb->regs->cfg122;
+ arg->txCarrierTypeSel = CSL_FEXT(data, DFE_BB_CFG122_REG_ANTCAL_TX_CT_SEL);
+ arg->rxCarrierTypeSel = CSL_FEXT(data, DFE_BB_CFG122_REG_ANTCAL_RX_CT_SEL);
+ arg->txSsel = CSL_FEXT(data, DFE_BB_CFG122_REG_ANTCAL_TX_SSEL);
+ arg->rxSsel = CSL_FEXT(data, DFE_BB_CFG122_REG_ANTCAL_RX_SSEL);
+
+ data = hDfeBb->regs->cfg123;
+ arg->enable = CSL_FEXT(data, DFE_BB_CFG123_REG_ANTCAL_EN);
+}
+
+/** ============================================================================
+ * @n@b dfeFl_BbConfigAntcal
+ *
+ * @b Description
+ * @n [add content]
+ *
+ * @b Arguments
+ * @verbatim
+ hDfeBb [add content]
+ arg [add content]
+ @endverbatim
+ *
+ * <b> Return Value </b> None
+ *
+ * <b> Pre Condition </b>
+ * @n [add content]
+ *
+ * <b> Post Condition </b>
+ * @n [add content]
+ *
+ * @b Reads
+ * @n None
+ *
+ * @b Writes
+ * @n see below,
+ * DFE_BB_ANTCAL_TX_NOISE_REG_ANTCAL_TX_NOISE
+ * DFE_BB_ANTCAL_RX_REG_ANTCAL_RX_CORR_DELAY
+ * DFE_BB_ANTCAL_PN_TAPCONFIG_REG_ANTCAL_PN_TAPCONFIG
+ * DFE_BB_ANTCAL_RX_REG_ANTCAL_RX_OVERSAMPLE
+ * DFE_BB_ANTCAL_PN_INIT_REG_ANTCAL_PN_INIT
+ *
+ * @b Example
+ * @verbatim
+ [add content]
+ @endverbatim
+ * ===========================================================================
+ */
+CSL_IDEF_INLINE void
+dfeFl_BbConfigAntcal(DfeFl_BbHandle hDfeBb, DfeFl_BbAntCalConfig * arg)
+{
+ hDfeBb->regs->antcal[arg->antcal].pn_init =
+ CSL_FMK(DFE_BB_ANTCAL_PN_INIT_REG_ANTCAL_PN_INIT, arg->pnInit);
+ hDfeBb->regs->antcal[arg->antcal].pn_tapconfig =
+ CSL_FMK(DFE_BB_ANTCAL_PN_TAPCONFIG_REG_ANTCAL_PN_TAPCONFIG, arg->pnTapConfig);
+ hDfeBb->regs->antcal[arg->antcal].tx_noise =
+ CSL_FMK(DFE_BB_ANTCAL_TX_NOISE_REG_ANTCAL_TX_NOISE, arg->txNoise);
+ hDfeBb->regs->antcal[arg->antcal].rx \
+ = CSL_FMK(DFE_BB_ANTCAL_RX_REG_ANTCAL_RX_CORR_DELAY, arg->rxCorrDelay)
+ | CSL_FMK(DFE_BB_ANTCAL_RX_REG_ANTCAL_RX_OVERSAMPLE, arg->rxOverSample);
+}
+
+/** ============================================================================
+ * @n@b dfeFl_BbQueryAntcalConfig
+ *
+ * @b Description
+ * @n [add content]
+ *
+ * @b Arguments
+ * @verbatim
+ hDfeBb [add content]
+ arg [add content]
+ @endverbatim
+ *
+ * <b> Return Value </b> None
+ *
+ * <b> Pre Condition </b>
+ * @n [add content]
+ *
+ * <b> Post Condition </b>
+ * @n [add content]
+ *
+ * @b Reads
+ * @n see below,
+ * DFE_BB_ANTCAL_TX_NOISE_REG_ANTCAL_TX_NOISE
+ * DFE_BB_ANTCAL_RX_REG_ANTCAL_RX_CORR_DELAY
+ * DFE_BB_ANTCAL_PN_TAPCONFIG_REG_ANTCAL_PN_TAPCONFIG
+ * DFE_BB_ANTCAL_RX_REG_ANTCAL_RX_OVERSAMPLE
+ * DFE_BB_ANTCAL_PN_INIT_REG_ANTCAL_PN_INIT
+ *
+ * @b Writes
+ * @n None
+ *
+ * @b Example
+ * @verbatim
+ [add content]
+ @endverbatim
+ * ===========================================================================
+ */
+CSL_IDEF_INLINE void
+dfeFl_BbQueryAntcalConfig(DfeFl_BbHandle hDfeBb, DfeFl_BbAntCalConfig * arg)
+{
+ uint32_t data;
+
+ data = hDfeBb->regs->antcal[arg->antcal].pn_init;
+ arg->pnInit = CSL_FEXT(data, DFE_BB_ANTCAL_PN_INIT_REG_ANTCAL_PN_INIT);
+
+ data = hDfeBb->regs->antcal[arg->antcal].pn_tapconfig;
+ arg->pnTapConfig = CSL_FEXT(data, DFE_BB_ANTCAL_PN_TAPCONFIG_REG_ANTCAL_PN_TAPCONFIG);
+
+ data = hDfeBb->regs->antcal[arg->antcal].tx_noise;
+ arg->txNoise = CSL_FEXT(data, DFE_BB_ANTCAL_TX_NOISE_REG_ANTCAL_TX_NOISE);
+
+ data = hDfeBb->regs->antcal[arg->antcal].rx;
+ arg->rxCorrDelay = CSL_FEXT(data, DFE_BB_ANTCAL_RX_REG_ANTCAL_RX_CORR_DELAY);
+ arg->rxOverSample = CSL_FEXT(data, DFE_BB_ANTCAL_RX_REG_ANTCAL_RX_OVERSAMPLE);
+}
+
+/** ============================================================================
+ * @n@b dfeFl_BbEnableGeneralIntr
+ *
+ * @b Description
+ * @n [add content]
+ *
+ * @b Arguments
+ * @verbatim
+ hDfeBb [add content]
+ intr [add content]
+ @endverbatim
+ *
+ * <b> Return Value </b> None
+ *
+ * <b> Pre Condition </b>
+ * @n [add content]
+ *
+ * <b> Post Condition </b>
+ * @n [add content]
+ *
+ * @b Reads
+ * @n None
+ *
+ * @b Writes
+ * @n None
+ *
+ * @b Example
+ * @verbatim
+ [add content]
+ @endverbatim
+ * ===========================================================================
+ */
+CSL_IDEF_INLINE void
+dfeFl_BbEnableGeneralIntr(DfeFl_BbHandle hDfeBb, uint32_t intr)
+{
+ if(intr < 16)
+ CSL_FINSR(hDfeBb->regs->intmask4, intr, intr, 1);
+ else
+ CSL_FINSR(hDfeBb->regs->intmask4a, intr-16, intr-16, 1);
+}
+
+/** ============================================================================
+ * @n@b dfeFl_BbDisableGeneralIntr
+ *
+ * @b Description
+ * @n [add content]
+ *
+ * @b Arguments
+ * @verbatim
+ hDfeBb [add content]
+ intr [add content]
+ @endverbatim
+ *
+ * <b> Return Value </b> None
+ *
+ * <b> Pre Condition </b>
+ * @n [add content]
+ *
+ * <b> Post Condition </b>
+ * @n [add content]
+ *
+ * @b Reads
+ * @n None
+ *
+ * @b Writes
+ * @n None
+ *
+ * @b Example
+ * @verbatim
+ [add content]
+ @endverbatim
+ * ===========================================================================
+ */
+CSL_IDEF_INLINE void
+dfeFl_BbDisableGeneralIntr(DfeFl_BbHandle hDfeBb, uint32_t intr)
+{
+ if(intr < 16)
+ CSL_FINSR(hDfeBb->regs->intmask4, intr, intr, 0);
+ else
+ CSL_FINSR(hDfeBb->regs->intmask4a, intr-16, intr-16, 0);
+}
+
+/** ============================================================================
+ * @n@b dfeFl_BbClearGeneralIntrStatus
+ *
+ * @b Description
+ * @n [add content]
+ *
+ * @b Arguments
+ * @verbatim
+ hDfeBb [add content]
+ intr [add content]
+ @endverbatim
+ *
+ * <b> Return Value </b> None
+ *
+ * <b> Pre Condition </b>
+ * @n [add content]
+ *
+ * <b> Post Condition </b>
+ * @n [add content]
+ *
+ * @b Reads
+ * @n None
+ *
+ * @b Writes
+ * @n None
+ *
+ * @b Example
+ * @verbatim
+ [add content]
+ @endverbatim
+ * ===========================================================================
+ */
+CSL_IDEF_INLINE void
+dfeFl_BbClearGeneralIntrStatus(DfeFl_BbHandle hDfeBb, uint32_t intr)
+{
+ if(intr < 16)
+ hDfeBb->regs->intstatus4 = ~(1u << intr);
+ else
+ hDfeBb->regs->intstatus4a = ~(1u << (intr - 16));
+}
+
+/** ============================================================================
+ * @n@b dfeFl_BbQueryGeneralIntrStatus
+ *
+ * @b Description
+ * @n [add content]
+ *
+ * @b Arguments
+ * @verbatim
+ hDfeBb [add content]
+ intr [add content]
+ status [add content]
+ @endverbatim
+ *
+ * <b> Return Value </b> None
+ *
+ * <b> Pre Condition </b>
+ * @n [add content]
+ *
+ * <b> Post Condition </b>
+ * @n [add content]
+ *
+ * @b Reads
+ * @n None
+ *
+ * @b Writes
+ * @n None
+ *
+ * @b Example
+ * @verbatim
+ [add content]
+ @endverbatim
+ * ===========================================================================
+ */
+CSL_IDEF_INLINE void
+dfeFl_BbQueryGeneralIntrStatus(DfeFl_BbHandle hDfeBb, uint32_t intr, uint32_t *status)
+{
+ if(intr < 16)
+ *status = CSL_FEXTR(hDfeBb->regs->intstatus4, intr, intr);
+ else
+ *status = CSL_FEXTR(hDfeBb->regs->intstatus4a, intr-16, intr-16);
+}
+
+/** ============================================================================
+ * @n@b dfeFl_BbSetForceGeneralIntr
+ *
+ * @b Description
+ * @n [add content]
+ *
+ * @b Arguments
+ * @verbatim
+ hDfeBb [add content]
+ intr [add content]
+ @endverbatim
+ *
+ * <b> Return Value </b> None
+ *
+ * <b> Pre Condition </b>
+ * @n [add content]
+ *
+ * <b> Post Condition </b>
+ * @n [add content]
+ *
+ * @b Reads
+ * @n None
+ *
+ * @b Writes
+ * @n None
+ *
+ * @b Example
+ * @verbatim
+ [add content]
+ @endverbatim
+ * ===========================================================================
+ */
+CSL_IDEF_INLINE void
+dfeFl_BbSetForceGeneralIntr(DfeFl_BbHandle hDfeBb, uint32_t intr)
+{
+ if(intr < 16)
+ CSL_FINSR(hDfeBb->regs->intforce4, intr, intr, 1);
+ else
+ CSL_FINSR(hDfeBb->regs->intforce4a, intr-16, intr-16, 1);
+}
+
+/** ============================================================================
+ * @n@b dfeFl_BbClearForceGeneralIntr
+ *
+ * @b Description
+ * @n [add content]
+ *
+ * @b Arguments
+ * @verbatim
+ hDfeBb [add content]
+ intr [add content]
+ @endverbatim
+ *
+ * <b> Return Value </b> None
+ *
+ * <b> Pre Condition </b>
+ * @n [add content]
+ *
+ * <b> Post Condition </b>
+ * @n [add content]
+ *
+ * @b Reads
+ * @n None
+ *
+ * @b Writes
+ * @n None
+ *
+ * @b Example
+ * @verbatim
+ [add content]
+ @endverbatim
+ * ===========================================================================
+ */
+CSL_IDEF_INLINE void
+dfeFl_BbClearForceGeneralIntr(DfeFl_BbHandle hDfeBb, uint32_t intr)
+{
+ if(intr < 16)
+ CSL_FINSR(hDfeBb->regs->intforce4, intr, intr, 0);
+ else
+ CSL_FINSR(hDfeBb->regs->intforce4a, intr-16, intr-16, 0);
+}
+
+/** ============================================================================
+ * @n@b dfeFl_BbEnableGeneralIntrGroup
+ *
+ * @b Description
+ * @n [add content]
+ *
+ * @b Arguments
+ * @verbatim
+ hDfeBb [add content]
+ intrGrp [add content]
+ @endverbatim
+ *
+ * <b> Return Value </b> None
+ *
+ * <b> Pre Condition </b>
+ * @n [add content]
+ *
+ * <b> Post Condition </b>
+ * @n [add content]
+ *
+ * @b Reads
+ * @n None
+ *
+ * @b Writes
+ * @n None
+ *
+ * @b Example
+ * @verbatim
+ [add content]
+ @endverbatim
+ * ===========================================================================
+ */
+CSL_IDEF_INLINE void
+dfeFl_BbEnableGeneralIntrGroup(DfeFl_BbHandle hDfeBb, DfeFl_BbGeneralIntrGroup *intrGrp)
+{
+ uint32_t data = 0;
+ uint32_t data2 = 0;
+
+ CSL_FINSR(data, DFE_FL_BB_GENERAL_INTR_TXPM_LDERR, DFE_FL_BB_GENERAL_INTR_TXPM_LDERR, intrGrp->txpmLoadErr);
+ CSL_FINSR(data, DFE_FL_BB_GENERAL_INTR_RXPM_LDERR, DFE_FL_BB_GENERAL_INTR_RXPM_LDERR, intrGrp->rxpmLoadErr);
+ CSL_FINSR(data, DFE_FL_BB_GENERAL_INTR_ANTCAL, DFE_FL_BB_GENERAL_INTR_ANTCAL, intrGrp->antcal);
+ CSL_FINSR(data, DFE_FL_BB_GENERAL_INTR_RXNOTCH_DONE, DFE_FL_BB_GENERAL_INTR_RXNOTCH_DONE, intrGrp->rxNotchDone);
+ CSL_FINSR(data, DFE_FL_BB_GENERAL_INTR_RXNOTCH_ERR, DFE_FL_BB_GENERAL_INTR_RXNOTCH_ERR, intrGrp->rxNotchErr);
+ CSL_FINSR(data, DFE_FL_BB_GENERAL_INTR_BUFMEM0_OUF, DFE_FL_BB_GENERAL_INTR_BUFMEM0_OUF, intrGrp->bufErr[0]);
+ CSL_FINSR(data, DFE_FL_BB_GENERAL_INTR_BUFMEM1_OUF, DFE_FL_BB_GENERAL_INTR_BUFMEM1_OUF, intrGrp->bufErr[1]);
+ CSL_FINSR(data, DFE_FL_BB_GENERAL_INTR_BUFMEM2_OUF, DFE_FL_BB_GENERAL_INTR_BUFMEM2_OUF, intrGrp->bufErr[2]);
+ CSL_FINSR(data, DFE_FL_BB_GENERAL_INTR_BUFMEM3_OUF, DFE_FL_BB_GENERAL_INTR_BUFMEM3_OUF, intrGrp->bufErr[3]);
+ CSL_FINSR(data, DFE_FL_BB_GENERAL_INTR_BUFMEM4_OUF, DFE_FL_BB_GENERAL_INTR_BUFMEM4_OUF, intrGrp->bufErr[4]);
+ CSL_FINSR(data, DFE_FL_BB_GENERAL_INTR_BUFMEM5_OUF, DFE_FL_BB_GENERAL_INTR_BUFMEM5_OUF, intrGrp->bufErr[5]);
+ CSL_FINSR(data, DFE_FL_BB_GENERAL_INTR_BUFMEM6_OUF, DFE_FL_BB_GENERAL_INTR_BUFMEM6_OUF, intrGrp->bufErr[6]);
+ CSL_FINSR(data, DFE_FL_BB_GENERAL_INTR_BUFMEM7_OUF, DFE_FL_BB_GENERAL_INTR_BUFMEM7_OUF, intrGrp->bufErr[7]);
+
+ CSL_FINSR(data2, DFE_FL_BB_GENERAL_INTR_RXAID_SYNCERR-16, DFE_FL_BB_GENERAL_INTR_RXAID_SYNCERR-16, intrGrp->rxaidSyncErr);
+ CSL_FINSR(data2, DFE_FL_BB_GENERAL_INTR_TXAID_UDF-16, DFE_FL_BB_GENERAL_INTR_TXAID_UDF-16, intrGrp->txaidUnderflow);
+ CSL_FINSR(data2, DFE_FL_BB_GENERAL_INTR_TXAID_OVF-16, DFE_FL_BB_GENERAL_INTR_TXAID_OVF-16, intrGrp->txaidOverflow);
+ CSL_FINSR(data2, DFE_FL_BB_GENERAL_INTR_JESDRX_SYNCERR-16, DFE_FL_BB_GENERAL_INTR_JESDRX_SYNCERR-16, intrGrp->jesdrxSyncErr);
+ CSL_FINSR(data2, DFE_FL_BB_GENERAL_INTR_JESDTX_UDF-16, DFE_FL_BB_GENERAL_INTR_JESDTX_UDF-16, intrGrp->jesdtxUnderflow);
+ CSL_FINSR(data2, DFE_FL_BB_GENERAL_INTR_JESDTX_OVF-16, DFE_FL_BB_GENERAL_INTR_JESDTX_OVF-16, intrGrp->jesdtxOverflow);
+
+ hDfeBb->regs->intmask4 |= data;
+ hDfeBb->regs->intmask4a |= data2;
+}
+
+/** ============================================================================
+ * @n@b dfeFl_BbDisableGeneralIntrGroup
+ *
+ * @b Description
+ * @n [add content]
+ *
+ * @b Arguments
+ * @verbatim
+ hDfeBb [add content]
+ intrGrp [add content]
+ @endverbatim
+ *
+ * <b> Return Value </b> None
+ *
+ * <b> Pre Condition </b>
+ * @n [add content]
+ *
+ * <b> Post Condition </b>
+ * @n [add content]
+ *
+ * @b Reads
+ * @n None
+ *
+ * @b Writes
+ * @n None
+ *
+ * @b Example
+ * @verbatim
+ [add content]
+ @endverbatim
+ * ===========================================================================
+ */
+CSL_IDEF_INLINE void
+dfeFl_BbDisableGeneralIntrGroup(DfeFl_BbHandle hDfeBb, DfeFl_BbGeneralIntrGroup *intrGrp)
+{
+ uint32_t data = 0;
+ uint32_t data2 = 0;
+
+ CSL_FINSR(data, DFE_FL_BB_GENERAL_INTR_TXPM_LDERR, DFE_FL_BB_GENERAL_INTR_TXPM_LDERR, intrGrp->txpmLoadErr);
+ CSL_FINSR(data, DFE_FL_BB_GENERAL_INTR_RXPM_LDERR, DFE_FL_BB_GENERAL_INTR_RXPM_LDERR, intrGrp->rxpmLoadErr);
+ CSL_FINSR(data, DFE_FL_BB_GENERAL_INTR_ANTCAL, DFE_FL_BB_GENERAL_INTR_ANTCAL, intrGrp->antcal);
+ CSL_FINSR(data, DFE_FL_BB_GENERAL_INTR_RXNOTCH_DONE, DFE_FL_BB_GENERAL_INTR_RXNOTCH_DONE, intrGrp->rxNotchDone);
+ CSL_FINSR(data, DFE_FL_BB_GENERAL_INTR_RXNOTCH_ERR, DFE_FL_BB_GENERAL_INTR_RXNOTCH_ERR, intrGrp->rxNotchErr);
+ CSL_FINSR(data, DFE_FL_BB_GENERAL_INTR_BUFMEM0_OUF, DFE_FL_BB_GENERAL_INTR_BUFMEM0_OUF, intrGrp->bufErr[0]);
+ CSL_FINSR(data, DFE_FL_BB_GENERAL_INTR_BUFMEM1_OUF, DFE_FL_BB_GENERAL_INTR_BUFMEM1_OUF, intrGrp->bufErr[1]);
+ CSL_FINSR(data, DFE_FL_BB_GENERAL_INTR_BUFMEM2_OUF, DFE_FL_BB_GENERAL_INTR_BUFMEM2_OUF, intrGrp->bufErr[2]);
+ CSL_FINSR(data, DFE_FL_BB_GENERAL_INTR_BUFMEM3_OUF, DFE_FL_BB_GENERAL_INTR_BUFMEM3_OUF, intrGrp->bufErr[3]);
+ CSL_FINSR(data, DFE_FL_BB_GENERAL_INTR_BUFMEM4_OUF, DFE_FL_BB_GENERAL_INTR_BUFMEM4_OUF, intrGrp->bufErr[4]);
+ CSL_FINSR(data, DFE_FL_BB_GENERAL_INTR_BUFMEM5_OUF, DFE_FL_BB_GENERAL_INTR_BUFMEM5_OUF, intrGrp->bufErr[5]);
+ CSL_FINSR(data, DFE_FL_BB_GENERAL_INTR_BUFMEM6_OUF, DFE_FL_BB_GENERAL_INTR_BUFMEM6_OUF, intrGrp->bufErr[6]);
+ CSL_FINSR(data, DFE_FL_BB_GENERAL_INTR_BUFMEM7_OUF, DFE_FL_BB_GENERAL_INTR_BUFMEM7_OUF, intrGrp->bufErr[7]);
+
+ CSL_FINSR(data2, DFE_FL_BB_GENERAL_INTR_RXAID_SYNCERR-16, DFE_FL_BB_GENERAL_INTR_RXAID_SYNCERR-16, intrGrp->rxaidSyncErr);
+ CSL_FINSR(data2, DFE_FL_BB_GENERAL_INTR_TXAID_UDF-16, DFE_FL_BB_GENERAL_INTR_TXAID_UDF-16, intrGrp->txaidUnderflow);
+ CSL_FINSR(data2, DFE_FL_BB_GENERAL_INTR_TXAID_OVF-16, DFE_FL_BB_GENERAL_INTR_TXAID_OVF-16, intrGrp->txaidOverflow);
+ CSL_FINSR(data2, DFE_FL_BB_GENERAL_INTR_JESDRX_SYNCERR-16, DFE_FL_BB_GENERAL_INTR_JESDRX_SYNCERR-16, intrGrp->jesdrxSyncErr);
+&nb