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raw | patch | inline | side by side (parent: 96b8ee3)
raw | patch | inline | side by side (parent: 96b8ee3)
| author | Vivek Dhande <a0132295@ti.com> | |
| Thu, 29 Jul 2021 16:47:18 +0000 (22:17 +0530) | ||
| committer | Vivek Dhande <a0132295@ti.com> | |
| Thu, 14 Oct 2021 05:20:08 +0000 (10:50 +0530) |
[TI CLANG Migration][PDK-9370]Enable build for R5 core
- Initial commit to port compiler to TI CLNAG
- able to compile few files/.asm
Signed-off-by: Vivek Dhande <a0132295@ti.com>
[TI CLANG Migration]After compiling 'csl' with some warnings suppressed
Signed-off-by: Vivek Dhande <a0132295@ti.com>
[TI CLANG Migration][PDK-9551]OSAL updates
- This commit also includes some changes for build, board, sciclient, GPIO and UART
Signed-off-by: Vivek Dhande <a0132295@ti.com>
[TI CLANG Migration][OSAL][SBL][Board]
Signed-off-by: Vivek Dhande <a0132295@ti.com>
[TI Clang Migration][PDK-9370][PDK-9550][PDK-9551]
- Additional OSAL changes
- freeRTOS changes
- Liker command file changes for freeRTOS
Signed-off-by: Vivek Dhande <a0132295@ti.com>
[TI CLANG Migration][PDK-9554] DSS Driver changes - Patch 2
- OSAL changes for TIRTOS
- these are enough as auto-generated files by XDS tools also throws errors
- includes '.gitignore' changes to ignore '*.d', '*.o'
Signed-off-by: Vivek Dhande <a0132295@ti.com>
[PDK-9555][TI CLANG Migration] R5 Drivers Updates and Testing: IPC, VISS, LDC, NF, SDE, MSC, DOF: Patch-1
- IPC driver changes
- Additional warnings ignored
Signed-off-by: Vivek Dhande <a0132295@ti.com>
[TI Clang Migration][Board]Porting to Clang
- increased OCMC memory size to 1MB for J721E for /packages/ti/board/utils/uniflash/target/soc/k3/linker_j7.cmd
Signed-off-by: Vivek Dhande <a0132295@ti.com>
[TI Clang Migration][SBL]Porting to Clang
Signed-off-by: Vivek Dhande <a0132295@ti.com>
[TI Clang Migration][SBL]Porting to Clang patch-2
- Increased memory section size for SBL OCM section, took the extra space from reserved 'OCMRAM_SBL_RESERVED_CUST_BOOT' section
- check if this is OK?
Signed-off-by: Vivek Dhande <a0132295@ti.com>
[TI Clang Migration][Build]Added options for additional warning suppression
Signed-off-by: Vivek Dhande <a0132295@ti.com>
[TI Clang Migration][Build]Disabled mcu core for TIRTOS build
- Disabled NIMU as it is only built for TIRTOS
Signed-off-by: Vivek Dhande <a0132295@ti.com>
- Initial commit to port compiler to TI CLNAG
- able to compile few files/.asm
Signed-off-by: Vivek Dhande <a0132295@ti.com>
[TI CLANG Migration]After compiling 'csl' with some warnings suppressed
Signed-off-by: Vivek Dhande <a0132295@ti.com>
[TI CLANG Migration][PDK-9551]OSAL updates
- This commit also includes some changes for build, board, sciclient, GPIO and UART
Signed-off-by: Vivek Dhande <a0132295@ti.com>
[TI CLANG Migration][OSAL][SBL][Board]
Signed-off-by: Vivek Dhande <a0132295@ti.com>
[TI Clang Migration][PDK-9370][PDK-9550][PDK-9551]
- Additional OSAL changes
- freeRTOS changes
- Liker command file changes for freeRTOS
Signed-off-by: Vivek Dhande <a0132295@ti.com>
[TI CLANG Migration][PDK-9554] DSS Driver changes - Patch 2
- OSAL changes for TIRTOS
- these are enough as auto-generated files by XDS tools also throws errors
- includes '.gitignore' changes to ignore '*.d', '*.o'
Signed-off-by: Vivek Dhande <a0132295@ti.com>
[PDK-9555][TI CLANG Migration] R5 Drivers Updates and Testing: IPC, VISS, LDC, NF, SDE, MSC, DOF: Patch-1
- IPC driver changes
- Additional warnings ignored
Signed-off-by: Vivek Dhande <a0132295@ti.com>
[TI Clang Migration][Board]Porting to Clang
- increased OCMC memory size to 1MB for J721E for /packages/ti/board/utils/uniflash/target/soc/k3/linker_j7.cmd
Signed-off-by: Vivek Dhande <a0132295@ti.com>
[TI Clang Migration][SBL]Porting to Clang
Signed-off-by: Vivek Dhande <a0132295@ti.com>
[TI Clang Migration][SBL]Porting to Clang patch-2
- Increased memory section size for SBL OCM section, took the extra space from reserved 'OCMRAM_SBL_RESERVED_CUST_BOOT' section
- check if this is OK?
Signed-off-by: Vivek Dhande <a0132295@ti.com>
[TI Clang Migration][Build]Added options for additional warning suppression
Signed-off-by: Vivek Dhande <a0132295@ti.com>
[TI Clang Migration][Build]Disabled mcu core for TIRTOS build
- Disabled NIMU as it is only built for TIRTOS
Signed-off-by: Vivek Dhande <a0132295@ti.com>
89 files changed:
diff --git a/.gitignore b/.gitignore
index a31e9940e5cc63fa91ec5ef86c4ee42a05bd3d61..d51fd5d266a9442c737fb04b75165250a72c99cd 100755 (executable)
--- a/.gitignore
+++ b/.gitignore
packages/ti/diag/serdes_diag/
packages/ti/kernel/freertos/FreeRTOS-LTS/
packages/ti/kernel/freertos/FreeRTOS-Labs/
-
+*.d
+*.o
\ No newline at end of file
diff --git a/packages/ti/board/diag/common/j721e/diag_entry_r5.asm b/packages/ti/board/diag/common/j721e/diag_entry_r5.asm
index 24efffeb04a42485f9f6b33a53f9fae62ac0fae1..410892fc6a6346c5b1dc273a3f06387ab3fb8d14 100755 (executable)
.asg __TI_auto_init, AUTO_INIT_RTN\r
.asg _args_main, ARGS_MAIN_RTN\r
.asg exit, EXIT_RTN\r
- .asg main_func_sp, MAIN_FUNC_SP\r
+ .asg __stack, MAIN_FUNC_SP\r
.else ; COFF TI ARM9 ABI\r
.asg __system_pre_init, PRE_INIT_RTN\r
.asg __TI_auto_init, AUTO_INIT_RTN ; NOTE does not use COFF prefix\r
.asg __args_main, ARGS_MAIN_RTN\r
.asg _exit, EXIT_RTN\r
- .asg _main_func_sp, MAIN_FUNC_SP\r
+ .asg ___stack, MAIN_FUNC_SP\r
.endif\r
\r
.if .TMS470_16BIS\r
diff --git a/packages/ti/board/diag/common/j721e/framework_linker_r5.lds b/packages/ti/board/diag/common/j721e/framework_linker_r5.lds
index 849c569d85c6bf010094f0d42978e63381a22f9d..5dc5f4f152d45d2f77440f7a77d733050ba603f0 100755 (executable)
.startupData : {} palign(8) > MSMC3, type = NOINIT\r
.text : {} palign(8) > MSMC3\r
.const : {} palign(8) > MSMC3\r
+ .rodata : {} palign(8) > MSMC3\r
.cinit : {} palign(8) > MSMC3\r
.pinit : {} palign(8) > MSMC3\r
.bss : {} align(4) > MSMC3\r
diff --git a/packages/ti/board/diag/common/j721e/linker_mcu1_0.lds b/packages/ti/board/diag/common/j721e/linker_mcu1_0.lds
index 8b7384bfd74a3f58c00595f472a0598aefbe4d1d..6f980a37bc5abd5d07bbbaf2ccd52b53b18b6948 100755 (executable)
.startupData : {} palign(8) > MSMC3, type = NOINIT
.text : {} palign(8) > MSMC3
.const : {} palign(8) > MSMC3
+ .rodata : {} palign(8) > MSMC3
.cinit : {} palign(8) > MSMC3
.pinit : {} palign(8) > MSMC3
.bss : {} align(4) > MSMC3
diff --git a/packages/ti/board/diag/csirx/src/csirx_test.c b/packages/ti/board/diag/csirx/src/csirx_test.c
index f7d8151988ad16b5b705fcf3715d2540e47ef054..f9ca9b564fc62ffb2e3e6ccad7cad618b070ead7 100755 (executable)
\r
BoardDiag_CsirxObj gCsirxObj;\r
/* Memory buffer to hold data */\r
-#pragma DATA_SECTION(gFrms, ".data_buffer")\r
-#pragma DATA_ALIGN(gFrms, 128)\r
static uint8_t gFrmDropBuf[(BOARD_DIAG_CSIRX_FRAME_WIDTH * BOARD_DIAG_CSIRX_FRAME_BPP)] __attribute__(( aligned(128), section(".data_buffer")));\r
uint8_t gFrms[(BOARD_DIAG_CSIRX_FRAMES_PER_CH * BOARD_DIAG_CSIRX_MAX_CH)][BOARD_DIAG_CSIRX_FRAME_SIZE] __attribute__(( aligned(128), section(".data_buffer")));\r
\r
/* Disable Error Events */\r
retVal = Fvid2_control(csirxObj->drvHandle,\r
IOCTL_CSIRX_UNREGISTER_EVENT,\r
- CSIRX_EVENT_GROUP_ERROR,\r
+ (void *)CSIRX_EVENT_GROUP_ERROR,\r
NULL);\r
if(retVal != FVID2_SOK)\r
{\r
diff --git a/packages/ti/board/diag/current_monitor/src/current_monitor_test.c b/packages/ti/board/diag/current_monitor/src/current_monitor_test.c
index f8e38db056d1191f0f25af7863e33d2bb082e24c..0e071eb99dc00928cb213d2df733e3dadd02cf9e 100755 (executable)
ret = BoardDiag_set_calibration(handle,
inaDevice[index].slaveAddr,
inaDevice[index].inaCalParams.currentLsb,
- inaDevice[index].inaCalParams.maxRShunt,
+ (uint8_t)inaDevice[index].inaCalParams.maxRShunt,
inaDevice[index].inaCalParams.calibrartion);
if(ret != 0)
{
diff --git a/packages/ti/board/diag/current_monitor/src/current_monitor_test.h b/packages/ti/board/diag/current_monitor/src/current_monitor_test.h
index 0925a70d99a3f396f1bfbfa29c08795f759786fd..fb391733fb92cd1b90e42612d4bfbd9390e406d5 100755 (executable)
* \brief Structure defining INA Device calibration parameters.
*/
typedef struct CalibrationParams{
- uint8_t maxRShunt;
+ float maxRShunt;
float shuntVolLsb;
float busVolLsb;
float powerLsb;
diff --git a/packages/ti/board/diag/fpd_lib/src/fpd_main.c b/packages/ti/board/diag/fpd_lib/src/fpd_main.c
index 9afd5be6fd08d2bdc93478ca3df753ba5c79cf70..fa4d0c003160bdc8f5ae41c4f2e67200c86d4397 100755 (executable)
UART_printf("* FPD LIB TEST *\n");
UART_printf("*********************************************\n");
#if defined(j721e_evm)
- while ((userInput != 1) || (userInput != 2))
{
UART_printf("\n1.FPD DSI (ds90ub941 & ds90ub924)\n");
UART_printf ("2.FPD TUNER (ds90ub926 & ds90ub925)\n");
diff --git a/packages/ti/board/src/j721e_evm/board_ddrtempmonitor.c b/packages/ti/board/src/j721e_evm/board_ddrtempmonitor.c
index d596c7294af59257c85ed4dd4c95c65a2565d1c1..553c30a51e3220eb2b61db7cb7fe0b2860d6c1fd 100644 (file)
uint16_t devIdIr;
} Board_DDRThermalMgmtInstance_t;
-#ifdef __cplusplus
-#pragma DATA_SECTION(".data:BOARD_DDR_thermalManagement");
-#else
-#pragma DATA_SECTION(gBoard_DDRThermalMgmtInstance, ".data:BOARD_DDR_thermalManagement");
-#endif
-static Board_DDRThermalMgmtInstance_t gBoard_DDRThermalMgmtInstance;
+static Board_DDRThermalMgmtInstance_t __attribute__((section(".data:BOARD_DDR_thermalManagement"))) gBoard_DDRThermalMgmtInstance;
/* Local defines */
#define BOARD_SCICLIENT_RESP_TIMEOUT 1000000
-#ifdef __cplusplus
-#pragma DATA_SECTION(".const:BOARD_DDR_thermalManagement");
-#else
-#pragma DATA_SECTION(gRefreshRateMultFactor, ".const:BOARD_DDR_thermalManagement");
-#endif
/* Multiplication factors assumes scaling by 8 */
-static const uint32_t gRefreshRateMultFactor[BOARD_MAX_TEMP_CHECK_REFRESH_RATE_VALUE+1] =
+static const uint32_t __attribute__((section(".const:BOARD_DDR_thermalManagement"))) gRefreshRateMultFactor[BOARD_MAX_TEMP_CHECK_REFRESH_RATE_VALUE+1] =
{
32U, /* 4 x */
32U, /* 4 x */
@@ -75,26 +65,15 @@ static const uint32_t gRefreshRateMultFactor[BOARD_MAX_TEMP_CHECK_REFRESH_RATE_V
2U, /* 0.25 x with derating */
2U, /* 0.25 x with derating */
};
-#ifdef __cplusplus
-#pragma DATA_SECTION(".const:BOARD_DDR_thermalManagement");
-#else
-#pragma DATA_SECTION(gBoardDDRFSPNum, ".const:BOARD_DDR_thermalManagement");
-#endif
-static const LPDDR4_CtlFspNum gBoardDDRFSPNum[LPDDR4_FSP_2+1] =
+static const LPDDR4_CtlFspNum __attribute__((section(".const:BOARD_DDR_thermalManagement"))) gBoardDDRFSPNum[LPDDR4_FSP_2+1] =
{
LPDDR4_FSP_0,
LPDDR4_FSP_1,
LPDDR4_FSP_2,
};
-#ifdef __cplusplus
-#pragma CODE_SECTION(".text:BOARD_DDR_thermalManagement");
-#else
-#pragma CODE_SECTION(Board_updateRefreshRate, ".text:BOARD_DDR_thermalManagement");
-#endif
-
-void Board_updateRefreshRate(const LPDDR4_CtlFspNum fsNum, uint32_t refreshMultFactor)
+void __attribute__((section(".text:BOARD_DDR_thermalManagement"))) Board_updateRefreshRate(const LPDDR4_CtlFspNum fsNum, uint32_t refreshMultFactor)
{
uint32_t refreshRate;
uint32_t trasMax;
@@ -114,13 +93,7 @@ void Board_updateRefreshRate(const LPDDR4_CtlFspNum fsNum, uint32_t refreshMultF
}
}
-#ifdef __cplusplus
-#pragma CODE_SECTION(".text:BOARD_DDR_thermalManagement");
-#else
-#pragma CODE_SECTION(Board_DDRSetDevId, ".text:BOARD_DDR_thermalManagement");
-#endif
-
-static void Board_DDRSetDevId()
+static void __attribute__((section(".text:BOARD_DDR_thermalManagement"))) Board_DDRSetDevId()
{
CSL_ArmR5CPUInfo info;
return;
}
-#ifdef __cplusplus
-#pragma CODE_SECTION(".text:BOARD_DDR_thermalManagement");
-#else
-#pragma CODE_SECTION(Board_DDRGetIntNum, ".text:BOARD_DDR_thermalManagement");
-#endif
-
-static Board_STATUS Board_DDRGetIntNum(uint16_t *coreInterruptIdx)
+static Board_STATUS __attribute__((section(".text:BOARD_DDR_thermalManagement"))) Board_DDRGetIntNum(uint16_t *coreInterruptIdx)
{
Board_STATUS status = BOARD_SOK;
uint16_t irIntrIdx;
return status;
}
-#ifdef __cplusplus
-#pragma CODE_SECTION(".text:BOARD_DDR_thermalManagement");
-#else
-#pragma CODE_SECTION(Board_updateAllRefreshRate, ".text:BOARD_DDR_thermalManagement");
-#endif
-
-void Board_updateAllRefreshRate(uint32_t refreshMultFactor)
+void __attribute__((section(".text:BOARD_DDR_thermalManagement"))) Board_updateAllRefreshRate(uint32_t refreshMultFactor)
{
Board_updateRefreshRate(LPDDR4_FSP_0, refreshMultFactor);
Board_updateRefreshRate(LPDDR4_FSP_2, refreshMultFactor);
}
-#ifdef __cplusplus
-#pragma CODE_SECTION(".text:BOARD_DDR_thermalManagement");
-#else
-#pragma CODE_SECTION(Board_DDRInterruptHandler, ".text:BOARD_DDR_thermalManagement");
-#endif
/**
* \brief Interrupt handler for DDR events
*
* \return BOARD_SOK in case of success or appropriate error code
*
*/
-void Board_DDRInterruptHandler(uintptr_t arg)
+void __attribute__((section(".text:BOARD_DDR_thermalManagement"))) Board_DDRInterruptHandler(uintptr_t arg)
{
bool irqStatus;
uint32_t regValue;
diff --git a/packages/ti/board/src/j721e_evm/include/board_cfg.h b/packages/ti/board/src/j721e_evm/include/board_cfg.h
index 7433c63e004fcfa9678f46680866142c69622c67..6287dd323063066e2232c01558e6ed0d9fc7a7ea 100755 (executable)
#define BOARD_I2C_DOMAIN_INSTANCE_MAX (2U)
/* SoC domain used by UART module */
-#if defined (__TI_ARM_V7R5__)
+#if (__ARM_ARCH == 7) && (__ARM_ARCH_PROFILE == 'R') && defined(__ARM_FEATURE_IDIV)
#define BOARD_UART_SOC_DOMAIN (BOARD_SOC_DOMAIN_MCU)
#else
#define BOARD_UART_SOC_DOMAIN (BOARD_SOC_DOMAIN_MAIN)
diff --git a/packages/ti/board/utils/uniflash/target/soc/k3/linker_am65xx.cmd b/packages/ti/board/utils/uniflash/target/soc/k3/linker_am65xx.cmd
index ee789bedd8fa85f8a705ed811559a3fc08bfa4f8..28af1271618cf24b23c8bee2064fa720466795b5 100644 (file)
.startupData : {} palign(8) > OCMRAM, type = NOINIT
.text : {} palign(8) > OCMRAM
.const : {} palign(8) > OCMRAM
+ .rodata : {} palign(8) > OCMRAM
.cinit : {} palign(8) > OCMRAM
.pinit : {} palign(8) > OCMRAM
.boardcfg_data : {} palign(128) > OCMRAM
diff --git a/packages/ti/board/utils/uniflash/target/soc/k3/linker_j7.cmd b/packages/ti/board/utils/uniflash/target/soc/k3/linker_j7.cmd
index 91d47c7cf3ef3622448d1928f0d3f9b122d0f4f6..e76f1d3a37229123c3d3b8b788f080a2ccd236c5 100755 (executable)
/* MCU0 memory used for Uniflash programmer. Available to app for dynamic use ~160KB */
/* RBL uses 0x41C58000 and beyond. UFP, at load cannot cross this */
- OCMRAM (RWIX) : origin=0x41C00200 length=0x58000-0x200
+ OCMRAM (RWIX) : origin=0x41C00200 length=0xD8000-0x200
/* Used by UFP at runtime to load SYSFW. Available to app for dynamic use */
- OCMRAM_SYSFW (RWIX) : origin=0x41C58000 length=0x41000
+ OCMRAM_SYSFW (RWIX) : origin=0x41CD8000 length=0x41000
} /* end of MEMORY */
.startupData : {} palign(8) > OCMRAM, type = NOINIT
.text : {} palign(8) > OCMRAM
.const : {} palign(8) > OCMRAM
+ .rodata : {} palign(8) > OCMRAM
.cinit : {} palign(8) > OCMRAM
.pinit : {} palign(8) > OCMRAM
.boardcfg_data : {} palign(128) > OCMRAM
diff --git a/packages/ti/board/utils/uniflash/target/src/uart_main.c b/packages/ti/board/utils/uniflash/target/src/uart_main.c
index 7c432d176381cae058bee216bc921f044c2f5070..f48f63c1cfc26e8e3d0d2554dfbc2bacd3c68752 100644 (file)
};
#if defined(am65xx_evm) || defined(am65xx_idk) || defined(j721e_evm) || defined(j7200_evm) || defined(am64x_evm)
-#pragma DATA_SECTION(gSysFirmware, ".firmware")
-uint32_t gSysFirmware[1];
+uint32_t gSysFirmware[1] __attribute((section(".firmware")));
#endif
/* ========================================================================== */
diff --git a/packages/ti/board/utils/uniflash/target/src/xmodem.c b/packages/ti/board/utils/uniflash/target/src/xmodem.c
index 07a584cbc1b878ed984fd31356c8b3067925908e..273fd957825a5edf30372d5bed23abd0fe917f5d 100755 (executable)
int32_t c;
uint16_t len = 0;
uint16_t i, bufsz;
- uint8_t retry;
+ uint16_t retry;
uint32_t retrans = MAXRETRANS + 1;
int8_t ret;
unsigned char xbuff[1030]; /* 1024 for XModem 1k + 3 head chars + 2 crc + nul */
uint16_t len = 0;
uint32_t offset = 0;
uint16_t i, bufsz;
- uint8_t retry;
+ uint16_t retry;
uint32_t retrans = MAXRETRANS + 1;
int8_t ret;
unsigned char xbuff[1030]; /* 1024 for XModem 1k + 3 head chars + 2 crc + nul */
uint32_t len = 0;
int32_t c;
uint16_t i, bufsz;
- uint8_t retry;
+ uint16_t retry;
uint32_t retrans = MAXRETRANS+1;
unsigned char xbuff[1030]; /* 1024 for XModem 1k + 3 head chars + 2 crc + nul */
unsigned char *p;
index 227e601b8024b95fdccda68c28fb9249a562b392..1033c4c7ffcc7b2f282629916d6c066f8f251d8a 100755 (executable)
extern uint32_t sblProfileLogIndx;
extern uint32_t sblProfileLogOvrFlw;
-#pragma DATA_SECTION(sblProfileLogAddr, ".sbl_profile_info")
-volatile sblProfileInfo_t * sblProfileLogAddr;
+volatile sblProfileInfo_t * sblProfileLogAddr __attribute__((section(".sbl_profile_info")));
-#pragma DATA_SECTION(sblProfileLogIndxAddr, ".sbl_profile_info")
-volatile uint32_t *sblProfileLogIndxAddr;
+volatile uint32_t *sblProfileLogIndxAddr __attribute__((section(".sbl_profile_info")));
-#pragma DATA_SECTION(sblProfileLogOvrFlwAddr, ".sbl_profile_info")
-volatile uint32_t *sblProfileLogOvrFlwAddr;
+volatile uint32_t *sblProfileLogOvrFlwAddr __attribute__((section(".sbl_profile_info")));
sblEntryPoint_t k3xx_evmEntry;
#if defined(SOC_AM64X)
{
/* Try booting all MAIN domain cores except the Cortex-A cores */
if (k3xx_evmEntry.CpuEntryPoint[core_id] != SBL_INVALID_ENTRY_ADDR)
- SBL_SlaveCoreBoot(core_id, NULL, &k3xx_evmEntry, SBL_REQUEST_CORE);
+ SBL_SlaveCoreBoot(core_id, (uint32_t)NULL, &k3xx_evmEntry, SBL_REQUEST_CORE);
}
Board_releaseResource(BOARD_RESOURCE_MODULE_CLOCK);
{
/* Try booting all cores other than the cluster running the SBL */
if (k3xx_evmEntry.CpuEntryPoint[core_id] != SBL_INVALID_ENTRY_ADDR)
- SBL_SlaveCoreBoot(core_id, NULL, &k3xx_evmEntry, SBL_REQUEST_CORE);
+ SBL_SlaveCoreBoot(core_id, (uint32_t)NULL, &k3xx_evmEntry, SBL_REQUEST_CORE);
}
#endif
diff --git a/packages/ti/boot/sbl/example/k3MulticoreApp/sbl_amp_multicore_sections.h b/packages/ti/boot/sbl/example/k3MulticoreApp/sbl_amp_multicore_sections.h
index 0592ee607c9dc050b8ed71ba35cd264ac894ed48..ac1a7d60f0e5de607ddf89032617cd334a5ce35b 100644 (file)
#define CORE_NAME "MCU1_0"
#define BOOT_DELAY (0x2A0000)
#define POKE_MEM_ADDR (POKE_MEM_ADDR_MCU1_0)
- #pragma SET_CODE_SECTION(".sbl_mcu_1_0_resetvector")
+ __attribute__((section(".sbl_mcu_1_0_resetvector"))) void sbl_puts(char *str);
#endif
#ifdef BUILD_MCU1_1
#define CORE_NAME "MCU1_1"
#define BOOT_DELAY (0x80000)
#define POKE_MEM_ADDR (POKE_MEM_ADDR_MCU1_1)
- #pragma SET_CODE_SECTION(".sbl_mcu_1_1_resetvector")
+ __attribute__((section(".sbl_mcu_1_1_resetvector"))) void sbl_puts(char *str);
#endif
#ifdef BUILD_MCU2_0
#define CORE_NAME "MCU2_0"
#define BOOT_DELAY (0xA0000)
#define POKE_MEM_ADDR (POKE_MEM_ADDR_MCU2_0)
- #pragma SET_CODE_SECTION(".sbl_mcu_2_0_resetvector")
+ __attribute__((section(".sbl_mcu_2_0_resetvector"))) void sbl_puts(char *str);
#endif
#ifdef BUILD_MCU2_1
#define CORE_NAME "MCU2_1"
#define BOOT_DELAY (0xC0000)
#define POKE_MEM_ADDR (POKE_MEM_ADDR_MCU2_1)
- #pragma SET_CODE_SECTION(".sbl_mcu_2_1_resetvector")
+ __attribute__((section(".sbl_mcu_2_1_resetvector"))) void sbl_puts(char *str);
#endif
#ifdef BUILD_MCU3_0
#define CORE_NAME "MCU3_0"
#define BOOT_DELAY (0xE0000)
#define POKE_MEM_ADDR (POKE_MEM_ADDR_MCU3_0)
- #pragma SET_CODE_SECTION(".sbl_mcu_3_0_resetvector")
+ __attribute__((section(".sbl_mcu_3_0_resetvector"))) void sbl_puts(char *str);
#endif
#ifdef BUILD_MCU3_1
#define CORE_NAME "MCU3_1"
#define BOOT_DELAY (0x100000)
#define POKE_MEM_ADDR (POKE_MEM_ADDR_MCU3_1)
- #pragma SET_CODE_SECTION(".sbl_mcu_3_1_resetvector")
+ __attribute__((section(".sbl_mcu_3_1_resetvector"))) void sbl_puts(char *str);
#endif
#ifdef BUILD_C66X_1
int sblTestmain(void) __attribute__((section(".sbl_mpu_2_1_resetvector")));
#endif
-void sbl_puts(char *str);
diff --git a/packages/ti/boot/sbl/example/k3MulticoreApp/sbl_printf.c b/packages/ti/boot/sbl/example/k3MulticoreApp/sbl_printf.c
index 2da4559265ac8f1ad40102cf3523d283cbf9714c..7cc627801f4743130a95fb4b2fc0f2325c1db7df 100644 (file)
*/
#ifdef BUILD_MCU1_0
- #pragma CODE_SECTION(sbl_putc, ".sbl_mcu_1_0_resetvector")
- #pragma CODE_SECTION(sbl_puts, ".sbl_mcu_1_0_resetvector")
- #pragma CODE_SECTION(sbl_putbyte, ".sbl_mcu_1_0_resetvector")
- #pragma CODE_SECTION(sbl_putui, ".sbl_mcu_1_0_resetvector")
- #pragma CODE_SECTION(sbl_putsui, ".sbl_mcu_1_0_resetvector")
+ void sbl_putc(unsigned char c) __attribute__((section(".sbl_mcu_1_0_resetvector")));
+ void sbl_puts(char *str) __attribute__((section(".sbl_mcu_1_0_resetvector")));
+ void sbl_putbyte(unsigned char b) __attribute__((section(".sbl_mcu_1_0_resetvector")));
+ void sbl_putui(unsigned int ul) __attribute__((section(".sbl_mcu_1_0_resetvector")));
+ void sbl_putsui(char *s, unsigned int ui, int crlf) __attribute__((section(".sbl_mcu_1_0_resetvector")));
#endif
#ifdef BUILD_MCU1_1
- #pragma CODE_SECTION(sbl_putc, ".sbl_mcu_1_1_resetvector")
- #pragma CODE_SECTION(sbl_puts, ".sbl_mcu_1_1_resetvector")
- #pragma CODE_SECTION(sbl_putbyte, ".sbl_mcu_1_1_resetvector")
- #pragma CODE_SECTION(sbl_putui, ".sbl_mcu_1_1_resetvector")
- #pragma CODE_SECTION(sbl_putsui, ".sbl_mcu_1_1_resetvector")
+ void sbl_putc(unsigned char c) __attribute__((section(".sbl_mcu_1_1_resetvector")));
+ void sbl_puts(char *str) __attribute__((section(".sbl_mcu_1_1_resetvector")));
+ void sbl_putbyte(unsigned char b) __attribute__((section(".sbl_mcu_1_1_resetvector")));
+ void sbl_putui(unsigned int ul) __attribute__((section(".sbl_mcu_1_1_resetvector")));
+ void sbl_putsui(char *s, unsigned int ui, int crlf) __attribute__((section(".sbl_mcu_1_1_resetvector")));
#endif
#ifdef BUILD_MCU2_0
- #pragma CODE_SECTION(sbl_putc, ".sbl_mcu_2_0_resetvector")
- #pragma CODE_SECTION(sbl_puts, ".sbl_mcu_2_0_resetvector")
- #pragma CODE_SECTION(sbl_putbyte, ".sbl_mcu_2_0_resetvector")
- #pragma CODE_SECTION(sbl_putui, ".sbl_mcu_2_0_resetvector")
- #pragma CODE_SECTION(sbl_putsui, ".sbl_mcu_2_0_resetvector")
+ void sbl_putc(unsigned char c) __attribute__((section(".sbl_mcu_2_0_resetvector")));
+ void sbl_puts(char *str) __attribute__((section(".sbl_mcu_2_0_resetvector")));
+ void sbl_putbyte(unsigned char b) __attribute__((section(".sbl_mcu_2_0_resetvector")));
+ void sbl_putui(unsigned int ul) __attribute__((section(".sbl_mcu_2_0_resetvector")));
+ void sbl_putsui(char *s, unsigned int ui, int crlf) __attribute__((section(".sbl_mcu_2_0_resetvector")));
#endif
#ifdef BUILD_MCU2_1
- #pragma CODE_SECTION(sbl_putc, ".sbl_mcu_2_1_resetvector")
- #pragma CODE_SECTION(sbl_puts, ".sbl_mcu_2_1_resetvector")
- #pragma CODE_SECTION(sbl_putbyte, ".sbl_mcu_2_1_resetvector")
- #pragma CODE_SECTION(sbl_putui, ".sbl_mcu_2_1_resetvector")
- #pragma CODE_SECTION(sbl_putsui, ".sbl_mcu_2_1_resetvector")
+ void sbl_putc(unsigned char c) __attribute__((section(".sbl_mcu_2_1_resetvector")));
+ void sbl_puts(char *str) __attribute__((section(".sbl_mcu_2_1_resetvector")));
+ void sbl_putbyte(unsigned char b) __attribute__((section(".sbl_mcu_2_1_resetvector")));
+ void sbl_putui(unsigned int ul) __attribute__((section(".sbl_mcu_2_1_resetvector")));
+ void sbl_putsui(char *s, unsigned int ui, int crlf) __attribute__((section(".sbl_mcu_2_1_resetvector")));
#endif
#ifdef BUILD_MCU3_0
- #pragma CODE_SECTION(sbl_putc, ".sbl_mcu_3_0_resetvector")
- #pragma CODE_SECTION(sbl_puts, ".sbl_mcu_3_0_resetvector")
- #pragma CODE_SECTION(sbl_putbyte, ".sbl_mcu_3_0_resetvector")
- #pragma CODE_SECTION(sbl_putui, ".sbl_mcu_3_0_resetvector")
- #pragma CODE_SECTION(sbl_putsui, ".sbl_mcu_3_0_resetvector")
+ void sbl_putc(unsigned char c) __attribute__((section(".sbl_mcu_3_0_resetvector")));
+ void sbl_puts(char *str) __attribute__((section(".sbl_mcu_3_0_resetvector")));
+ void sbl_putbyte(unsigned char b) __attribute__((section(".sbl_mcu_3_0_resetvector")));
+ void sbl_putui(unsigned int ul) __attribute__((section(".sbl_mcu_3_0_resetvector")));
+ void sbl_putsui(char *s, unsigned int ui, int crlf) __attribute__((section(".sbl_mcu_3_0_resetvector")));
#endif
#ifdef BUILD_MCU3_1
- #pragma CODE_SECTION(sbl_putc, ".sbl_mcu_3_1_resetvector")
- #pragma CODE_SECTION(sbl_puts, ".sbl_mcu_3_1_resetvector")
- #pragma CODE_SECTION(sbl_putbyte, ".sbl_mcu_3_1_resetvector")
- #pragma CODE_SECTION(sbl_putui, ".sbl_mcu_3_1_resetvector")
- #pragma CODE_SECTION(sbl_putsui, ".sbl_mcu_3_1_resetvector")
+ void sbl_putc(unsigned char c) __attribute__((section(".sbl_mcu_3_1_resetvector")));
+ void sbl_puts(char *str) __attribute__((section(".sbl_mcu_3_1_resetvector")));
+ void sbl_putbyte(unsigned char b) __attribute__((section(".sbl_mcu_3_1_resetvector")));
+ void sbl_putui(unsigned int ul) __attribute__((section(".sbl_mcu_3_1_resetvector")));
+ void sbl_putsui(char *s, unsigned int ui, int crlf) __attribute__((section(".sbl_mcu_3_1_resetvector")));
#endif
#ifdef BUILD_MPU1_0
diff --git a/packages/ti/boot/sbl/example/k3MulticoreApp/xip_stub.c b/packages/ti/boot/sbl/example/k3MulticoreApp/xip_stub.c
index 54a56ae5e782ca5944914eefa6f683810f8aee74..3a757329313f360d437b3bea11c50eab1f266d7d 100644 (file)
* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
-#pragma SET_CODE_SECTION(".xip_entry")
+__attribute__((section(".xip_entry"))) void xip_stub_c(void);
+
void xip_stub_c(void)
{
return;
diff --git a/packages/ti/boot/sbl/soc/k3/j721e/linker.cmd b/packages/ti/boot/sbl/soc/k3/j721e/linker.cmd
index ccc1e38f546445af42edc38eaea2ad6181415492..9afcc9e4890364f82bb25236debcb029769923a0 100755 (executable)
/* MCU0 memory used for SBL. Available to app for dynamic use ~160KB */
/* RBL uses 0x41CC0000 and beyond. SBL, at load cannot cross this */
- OCMRAM_SBL (RWIX) : origin=0x41C00200 length=0x80000-0x200
+ OCMRAM_SBL (RWIX) : origin=0x41C00200 length=0x90000-0x200
/* Used by SBL at runtime to load SYSFW. Available to app for dynamic use
* Populate the SCISERVER Board configuration paramters at 0x41C80000
* after SYSFW is done.
* Location of all board configurations: 0x41c80040 after SYSFW is done.
*/
- OCMRAM_SBL_SYSFW (RWIX) : origin=0x41C80000 length=0x40000
+ OCMRAM_SBL_SYSFW (RWIX) : origin=0x41C90000 length=0x40000
/* This is the maximum required by custom boot app. Do not use. */
- OCMRAM_SBL_RESERVED_CUST_BOOT (RWIX) : origin=0x41CC0000 length=0x40000 - 0x500
+ OCMRAM_SBL_RESERVED_CUST_BOOT (RWIX) : origin=0x41CD0000 length=0x30000 - 0x500
/* X509 Header to be left behind by CCS Init for Sciserver to read */
OCMC_RAM_X509_HEADER (RWIX) : ORIGIN = 0x41cffb00 , LENGTH = 0x500
.startupData : {} palign(8) > OCMRAM_SBL, type = NOINIT
.sbl_profile_info : {} palign(8) > RESET_VECTORS (HIGH)
.text : {} palign(8) > OCMRAM_SBL
+ .rodata : {} palign(8) > OCMRAM_SBL
.const : {} palign(8) > OCMRAM_SBL
.const.devgroup.MCU_WAKEUP : {} align(4) > OCMRAM_SBL
.const.devgroup.MAIN : {} align(4) > OCMRAM_SBL
diff --git a/packages/ti/boot/sbl/soc/k3/sbl_err_trap.h b/packages/ti/boot/sbl/soc/k3/sbl_err_trap.h
index 644f423abfd30d0a7affbc323e0f6da6e16e42c7..faad878493eb2d70a91dcdb48494bb1050e6a607 100644 (file)
*/\r
\r
#ifndef SBL_ERR_TRAP_H\r
-#define SBL_ERR_TRAP_H_\r
+#define SBL_ERR_TRAP_H\r
\r
/* ========================================================================== */\r
/* Include Files */\r
index 29bb4e33d22606a52a86ee2d6abc4c1346109a9d..53bfcfa983f49232cf76addde98397b13ccea1e4 100644 (file)
*/\r
\r
#ifndef SBL_LOG_H\r
-#define SBL_LOG_H_\r
+#define SBL_LOG_H\r
/* ========================================================================== */\r
/* Include Files */\r
/* ========================================================================== */\r
diff --git a/packages/ti/boot/sbl/soc/k3/sbl_sci_client.c b/packages/ti/boot/sbl/soc/k3/sbl_sci_client.c
index 4aafcc9b96556cf4ada75cba87c5db6df6d1713b..0f07c7fd47cf070db5dd7f57111ca38467129725 100755 (executable)
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
+#include <string.h>
#include <ti/csl/tistdtypes.h>
#include <ti/csl/soc.h>
#include <ti/csl/arch/csl_arch.h>
#include <sbl_err_trap.h>
#include <sbl_sci_client.h>
-#ifdef __cplusplus
-#pragma DATA_SECTION(".firmware")
-#else
-#pragma WEAK (SBL_ReadSysfwImage)
-#pragma DATA_SECTION(gSciclient_firmware, ".firmware")
-#endif
-uint32_t gSciclient_firmware[1];
+extern int32_t SBL_ReadSysfwImage(void **pBuffer, uint32_t num_bytes);
+uint32_t __attribute__((section(".firmware"))) gSciclient_firmware[1];
#if SCICLIENT_FIRMWARE_SIZE_IN_BYTES > SBL_SYSFW_MAX_SIZE
#error "SYSFW too large...update SBL_SYSFW_MAX_SIZE"
index 193cfbbc6e6373aa35365e964f4ff569938c34ca..7bf31c6bade0ad5695d323481fc2932265d73ffe 100644 (file)
*/
#ifndef SBL_SOC_H
-#define SBL_SOC_H_
+#define SBL_SOC_H
/* ========================================================================== */
/* Include Files */
diff --git a/packages/ti/boot/sbl/src/uart/sbl_xmodem.c b/packages/ti/boot/sbl/src/uart/sbl_xmodem.c
index cedcb56ff0dda06222f3a61336e89425112261c2..b81f4b10ef50515d74b5bc26abe00891664631ed 100644 (file)
/* ========================================================================== */
/* Include Files */
/* ========================================================================== */
+#include <string.h>
#include "sbl_uart.h"
/* ========================================================================== */
/* Global Variables */
index f4385facb21b075c1b5c6d5269c82a94ecb6a8ed..535ba29d45039926d06e859d63b65270bc30ecfc 100755 (executable)
.startupData : {} palign(8) > MSMC3, type = NOINIT
.text : {} palign(8) > DDR0
.const : {} palign(8) > DDR0
+ .rodata : {} palign(8) > DDR0
.cinit : {} palign(8) > DDR0
.pinit : {} palign(8) > DDR0
.bss : {} align(4) > DDR0
diff --git a/packages/ti/build/j721e/linker_r5_freertos.lds b/packages/ti/build/j721e/linker_r5_freertos.lds
index e145f65eb5d7a4331fa92fca5f3bff75280dd6a2..882a527ec60dbb8b3883ec22f689eec92a79cf56 100644 (file)
.text.boot : palign(8)
} > DDR0
.const : {} palign(8) > DDR0
+ .rodata : {} palign(8) > DDR0
.cinit : {} palign(8) > DDR0
.bss : {} align(4) > DDR0
.far : {} align(4) > DDR0
diff --git a/packages/ti/build/makerules/build_config.mk b/packages/ti/build/makerules/build_config.mk
index 8e43e6e1f956a0200c89b281c92e1fed460fdb9a..c3a8d3d03be3a30058dfa9a694a48bac5af3a010 100644 (file)
# MCU Cores
ifeq ($(CORE),$(filter $(CORE), mcu1_0 mcu1_1 mcu2_0 mcu2_1 mcu3_0 mcu3_1 m4f_0))
- CFLAGS_GLOBAL_$(CORE) = -g -ms -DMAKEFILE_BUILD
- LNKFLAGS_GLOBAL_$(CORE) = -x --zero_init=on
+ CFLAGS_GLOBAL_$(CORE) = -g -DMAKEFILE_BUILD
+ LNKFLAGS_GLOBAL_$(CORE) = -Xlinker -x -Xlinker --zero_init=on
endif
# MPU Cores
endif
# ipu1_0 - Benelli - Core 1 (Cortex-M4)
-CFLAGS_GLOBAL_ipu1_0 = -g -ms -DMAKEFILE_BUILD
+CFLAGS_GLOBAL_ipu1_0 = -g -DMAKEFILE_BUILD
LNKFLAGS_GLOBAL_ipu1_0 = -x --zero_init=on
# m4f_0 - Cortex M4F
-CFLAGS_GLOBAL_m4f_0 = -g -ms -DMAKEFILE_BUILD
+CFLAGS_GLOBAL_m4f_0 = -g -DMAKEFILE_BUILD
LNKFLAGS_GLOBAL_m4f_0 = -x --zero_init=on
# ipu1_1 - Benneli - Core 0 (Cortex-M4)
-CFLAGS_GLOBAL_ipu1_1 = -g -ms -DMAKEFILE_BUILD
+CFLAGS_GLOBAL_ipu1_1 = -g -DMAKEFILE_BUILD
LNKFLAGS_GLOBAL_ipu1_1 = -x --zero_init=on
# ipu2_0 - Benelli - Core 1 (Cortex-M4)
-CFLAGS_GLOBAL_ipu2_0 = -g -ms -DMAKEFILE_BUILD
+CFLAGS_GLOBAL_ipu2_0 = -g -DMAKEFILE_BUILD
LNKFLAGS_GLOBAL_ipu2_0 = -x --zero_init=on
# ipu2_1 - Benneli - Core 0 (Cortex-M4)
-CFLAGS_GLOBAL_ipu2_1 = -g -ms -DMAKEFILE_BUILD
+CFLAGS_GLOBAL_ipu2_1 = -g -DMAKEFILE_BUILD
LNKFLAGS_GLOBAL_ipu2_1 = -x --zero_init=on
# m3 - (Cortex-M3)
-CFLAGS_GLOBAL_m3 = -g -ms -DMAKEFILE_BUILD
+CFLAGS_GLOBAL_m3 = -g -DMAKEFILE_BUILD
LNKFLAGS_GLOBAL_m3 = -x --zero_init=on
# arp32_1 - EVE
index 4287c42b3be41d5185c4d8955fe6ec10b640fba3..73ae5b110823253b3b58907706970f3ad54dc4f4 100644 (file)
# DEFAULT_$(SOC)_CORELIST_<rtos_type> is a subset of all the cores and is used for building components for the particular 'rtos_type'.
-DEFAULT_$(SOC)_CORELIST_tirtos = $(DEFAULT_$(SOC)_CORELIST)
-
-
ifeq ($(SOC),$(filter $(SOC), j721e j7200 j721s2 am65xx tpr12 awr294x))
DEFAULT_CORELIST_EXCLUDE_CORES_freertos =
ifeq ($(SOC),$(filter $(SOC), j721e j7200 j721s2 am65xx))
# FreeRTOS is not supported on mpu core
DEFAULT_CORELIST_EXCLUDE_CORES_freertos += mpu1_0
+# Excluding R5 cores from build for TIRTOS as this won't be supported for TI ARM CLANG Toolchain
+DEFAULT_CORELIST_EXCLUDE_CORES_tirtos += mcu1_0 mcu1_1
endif
ifeq ($(SOC),$(filter $(SOC), j721e j721s2))
# FreeRTOS is not currently supported on J7 c66x/c7x cores
DEFAULT_CORELIST_EXCLUDE_CORES_freertos += c7x_2 c7x-hostemu
+# Excluding R5 cores from build for TIRTOS as this won't be supported for TI ARM CLANG Toolchain
+DEFAULT_CORELIST_EXCLUDE_CORES_tirtos += mcu2_0 mcu2_1 mcu3_0 mcu3_1
endif
else
#FreeRTOS is not supported on other SOCs
DEFAULT_$(SOC)_CORELIST_freertos = $(filter-out $(DEFAULT_CORELIST_EXCLUDE_CORES_freertos), $(DEFAULT_$(SOC)_CORELIST))
+DEFAULT_$(SOC)_CORELIST_tirtos = $(filter-out $(DEFAULT_CORELIST_EXCLUDE_CORES_tirtos), $(DEFAULT_$(SOC)_CORELIST))
ifeq ($(SOC),$(filter $(SOC), tpr12 awr294x))
# SafeRTOS is not currently supported on mcu cores
endif
# - used to ignore include if component not present
--include $(PDK_NIMU_COMP_PATH)/nimu_component.mk
-ifneq ($(nimu_LIB_LIST),)
- pdk_LIB_LIST += $(nimu_LIB_LIST)
-endif
-ifneq ($(nimu_APP_LIB_LIST),)
- pdk_APP_LIB_LIST += $(nimu_APP_LIB_LIST)
-endif
-ifneq ($(nimu_EXAMPLE_LIST),)
- pdk_EXAMPLE_LIST += $(nimu_EXAMPLE_LIST)
-endif
+#-include $(PDK_NIMU_COMP_PATH)/nimu_component.mk
+#ifneq ($(nimu_LIB_LIST),)
+# pdk_LIB_LIST += $(nimu_LIB_LIST)
+#endif
+#ifneq ($(nimu_APP_LIB_LIST),)
+# pdk_APP_LIB_LIST += $(nimu_APP_LIB_LIST)
+#endif
+#ifneq ($(nimu_EXAMPLE_LIST),)
+# pdk_EXAMPLE_LIST += $(nimu_EXAMPLE_LIST)
+#endif
# - used to ignore include if component not present
-include $(PDK_FATFS_COMP_PATH)/fatfs_component.mk
diff --git a/packages/ti/build/makerules/rules_ti_cgt_arm.mk b/packages/ti/build/makerules/rules_ti_cgt_arm.mk
index a5c9cdc88631e89e78b177f92154203283ad4ef4..1bf5e6cc53a3d6c44740913ec4c9c0118ce2211f 100644 (file)
endif
CODEGEN_INCLUDE = $(TOOLCHAIN_PATH_$(CGT_ISA_PATH_PRFX))/include
-CC = $(TOOLCHAIN_PATH_$(CGT_ISA_PATH_PRFX))/bin/armcl
-AR = $(TOOLCHAIN_PATH_$(CGT_ISA_PATH_PRFX))/bin/armar
-LNK = $(TOOLCHAIN_PATH_$(CGT_ISA_PATH_PRFX))/bin/armcl
-STRP = $(TOOLCHAIN_PATH_$(CGT_ISA_PATH_PRFX))/bin/armstrip
-SIZE = $(TOOLCHAIN_PATH_$(CGT_ISA_PATH_PRFX))/bin/armofd
+CC = $(TOOLCHAIN_PATH_$(CGT_ISA_PATH_PRFX))/bin/tiarmclang
+AR = $(TOOLCHAIN_PATH_$(CGT_ISA_PATH_PRFX))/bin/tiarmar
+LNK = $(TOOLCHAIN_PATH_$(CGT_ISA_PATH_PRFX))/bin/tiarmclang
+STRP = $(TOOLCHAIN_PATH_$(CGT_ISA_PATH_PRFX))/bin/tiarmstrip
+SIZE = $(TOOLCHAIN_PATH_$(CGT_ISA_PATH_PRFX))/bin/tiarmsize
# Derive a part of RTS Library name based on ENDIAN: little/big
ifeq ($(ENDIAN),little)
- RTSLIB_ENDIAN = le
+ RTSLIB_ENDIAN = EL
+
else
- RTSLIB_ENDIAN = be
+ RTSLIB_ENDIAN = EB
endif
# Derive compiler switch and part of RTS Library name based on FORMAT: COFF/ELF
RTSLIB_FORMAT = eabi
endif
-LNKFLAGS_INTERNAL_COMMON += -O4
-LNKFLAGS_INTERNAL_COMMON += --run_linker
+LNKFLAGS_INTERNAL_COMMON += -Xlinker -o4
+SUPRESS_WARNINGS_FLAG = -Wno-extra -Wno-exceptions -ferror-limit=100 -Wno-parentheses-equality -Wno-unused-command-line-argument -Wno-gnu-variable-sized-type-not-at-end -Wno-unused-function -Wno-inconsistent-missing-override -Wno-address-of-packed-member -Wno-self-assign -Wno-ignored-attributes -Wno-bitfield-constant-conversion -Wno-unused-const-variable -Wno-unused-variable -Wno-format-security -Wno-excess-initializers -Wno-sometimes-uninitialized -Wno-empty-body -Wno-extern-initializer -Wno-absolute-value -Wno-missing-braces -Wno-ti-macros -Wno-pointer-sign -Wno-macro-redefined -Wno-main-return-type
# Internal CFLAGS - normally doesn't change
ifeq ($(CGT_ISA),$(filter $(CGT_ISA), M4 R5 M3))
- CFLAGS_INTERNAL = -c -qq -pdsw225 --endian=$(ENDIAN) -mv7$(CGT_ISA) --abi=$(CSWITCH_FORMAT) -eo.$(OBJEXT) -ea.$(ASMEXT) --symdebug:dwarf --embed_inline_assembly
+ CFLAGS_INTERNAL = -c -Wall -Werror $(SUPRESS_WARNINGS_FLAG) -$(RTSLIB_ENDIAN) -eo.$(OBJEXT) -ea.$(ASMEXT) -g -mfloat-abi=hard
ifeq ($(CGT_ISA),$(filter $(CGT_ISA), R5))
- CFLAGS_INTERNAL += --float_support=vfpv3d16
- # Enabling thumb2 mode
- CFLAGS_INTERNAL += --code_state=16
+ CFLAGS_INTERNAL += -mfpu=vfpv3-d16 -mcpu=cortex-r5 -march=armv7-r
+ # Enabling thumb2 mode
+ CFLAGS_INTERNAL +=
else
- CFLAGS_INTERNAL += --float_support=vfplib
+ CFLAGS_INTERNAL += -mfpu=vfplib
endif
else ifeq ($(CGT_ISA), Arm9)
- CFLAGS_INTERNAL = -c -qq -pdsw225 --endian=$(ENDIAN) -mv5e --float_support=vfplib --abi=$(CSWITCH_FORMAT) -eo.$(OBJEXT) -ea.$(ASMEXT) --symdebug:dwarf --embed_inline_assembly
+ CFLAGS_INTERNAL = -c -Wall -Werror $(SUPRESS_WARNINGS_FLAG) --endian=$(ENDIAN) -mv5e --float_support=vfplib -eo.$(OBJEXT) -ea.$(ASMEXT) -g
endif
# Reset the CFLAGS_INTERNAL flag for M4F
ifeq ($(CGT_ISA), M4F)
- CFLAGS_INTERNAL = -c -qq -pdsw225 --endian=$(ENDIAN) -mv7M4 --abi=$(CSWITCH_FORMAT) -eo.$(OBJEXT) -ea.$(ASMEXT) --symdebug:dwarf --embed_inline_assembly
- CFLAGS_INTERNAL += --float_support=FPv4SPD16
+ CFLAGS_INTERNAL = -mcpu=cortex-m4 -c -Wall -Werror $(SUPRESS_WARNINGS_FLAG) --endian=$(ENDIAN) -mv7M4 -eo.$(OBJEXT) -ea.$(ASMEXT) -g
+ CFLAGS_INTERNAL += -mfpu=fpv4-sp-d16
endif
ifeq ($(TREAT_WARNINGS_AS_ERROR), yes)
- CFLAGS_INTERNAL += --emit_warnings_as_errors
- LNKFLAGS_INTERNAL_COMMON += --emit_warnings_as_errors
+ CFLAGS_INTERNAL += -Werror
+ LNKFLAGS_INTERNAL_COMMON += -Xlinker -Werror
endif
-CFLAGS_DIROPTS = -fr=$(OBJDIR) -fs=$(OBJDIR)
+CFLAGS_DIROPTS = -c
ifeq ($(CGT_ISA),$(filter $(CGT_ISA),R5))
EXTERNAL_LNKCMD_FILE = $(EXTERNAL_LNKCMD_FILE_LOCAL)
else
EXTERNAL_LNKCMD_FILE = $(CONFIG_BLD_LNK_r5f)
- endif
+ endif
else
XDC_TARGET_NAME=$(CGT_ISA)
endif
EXTERNAL_LNKCMD_FILE = $(EXTERNAL_LNKCMD_FILE_LOCAL)
else
EXTERNAL_LNKCMD_FILE = $(CONFIG_BLD_LNK_m4f)
- endif
+ endif
endif
XDC_HFILE_NAME = $(basename $(notdir $(XDC_CFG_FILE_$(CORE))))
endif
ifeq ($(BUILD_PROFILE_$(CORE)), release)
ifeq ($(CGT_ISA),$(filter $(CGT_ISA), M4 R5 M3))
- LNKFLAGS_INTERNAL_BUILD_PROFILE = -qq --diag_warning=225 --diag_suppress=23000 $(LNKFLAGS_GLOBAL_$(CORE))
+ LNKFLAGS_INTERNAL_BUILD_PROFILE = $(LNKFLAGS_GLOBAL_$(CORE))
ifeq ($(CGT_ISA),$(filter $(CGT_ISA), R5))
- CFLAGS_INTERNAL += -ms -O4 -s
+ CFLAGS_INTERNAL += -O3 -s
else
- CFLAGS_INTERNAL += -ms -O4 -op0 -os --optimize_with_debug --inline_recursion_limit=20
+ CFLAGS_INTERNAL += -O3 -op0 -os --optimize_with_debug --inline_recursion_limit=20
endif
CFLAGS_XDCINTERNAL = -Dxdc_target_name__=$(XDC_TARGET_NAME) -Dxdc_target_types__=ti/targets/arm/elf/std.h -Dxdc_bld__profile_release
ifndef MODULE_NAME
endif
endif
ifeq ($(CGT_ISA), Arm9)
- LNKFLAGS_INTERNAL_BUILD_PROFILE = -qq --diag_warning=225 --diag_suppress=23000 $(LNKFLAGS_GLOBAL_$(CORE))
- CFLAGS_INTERNAL += -ms -oe -O3 -op0 -os --optimize_with_debug --inline_recursion_limit=20
+ LNKFLAGS_INTERNAL_BUILD_PROFILE = --diag_warning=225 --diag_suppress=23000 $(LNKFLAGS_GLOBAL_$(CORE))
+ CFLAGS_INTERNAL += -oe -O3 -op0 -os --optimize_with_debug --inline_recursion_limit=20
CFLAGS_XDCINTERNAL = -Dxdc_target_name__=$(XDC_TARGET_NAME) -Dxdc_target_types__=ti/targets/arm/elf/std.h -Dxdc_bld__profile_release
ifndef MODULE_NAME
CFLAGS_XDCINTERNAL += -Dxdc_cfg__header__='$(CONFIGURO_DIR)/package/cfg/$(XDC_HFILE_NAME)_$(XDC_HFILE_EXT).h'
endif
endif
ifeq ($(CGT_ISA),$(filter $(CGT_ISA), M4F))
- # LNKFLAGS_INTERNAL_BUILD_PROFILE = --opt='--float_support=FPv4SPD16 --endian=$(ENDIAN) -mv7M4 --abi=$(CSWITCH_FORMAT) -qq -pdsw225 $(CFLAGS_GLOBAL_$(CORE)) -oe --symdebug:dwarf -ms -op2 -O3 -os --optimize_with_debug --inline_recursion_limit=20 --diag_suppress=23000' --strict_compatibility=on
- LNKFLAGS_INTERNAL_BUILD_PROFILE = -qq --diag_warning=225 --diag_suppress=23000 $(LNKFLAGS_GLOBAL_$(CORE))
- CFLAGS_INTERNAL += -ms -oe -O3 -op0 -os --optimize_with_debug --inline_recursion_limit=20
+ # LNKFLAGS_INTERNAL_BUILD_PROFILE = --opt='--float_support=FPv4SPD16 --endian=$(ENDIAN) -mv7M4 -Wno-gnu-variable-sized-type-not-at-end -Wno-unused-function $(CFLAGS_GLOBAL_$(CORE)) -oe -g -op2 -O3 -os --optimize_with_debug --inline_recursion_limit=20 --diag_suppress=23000' --strict_compatibility=on
+ LNKFLAGS_INTERNAL_BUILD_PROFILE = --diag_warning=225 --diag_suppress=23000 $(LNKFLAGS_GLOBAL_$(CORE))
+ CFLAGS_INTERNAL += -oe -O3 -op0 -os --optimize_with_debug --inline_recursion_limit=20
endif
endif
endif
# Decide the compile mode
-COMPILEMODE = -fc
+COMPILEMODE = -x c
ifeq ($(CPLUSPLUS_BUILD), yes)
COMPILEMODE = -fg
endif
# The first $(CC) generates the dependency make files for each of the objects
# The second $(CC) compiles the source to generate object
$(OBJ_PATHS): $(OBJDIR)/%.$(OBJEXT): %.c $(GEN_FILE) | $(OBJDIR) $(DEPDIR)
- $(ECHO) \# Compiling $(PRINT_MESSAGE): $<
+ $(ECHO) \# Compiling $(PRINT_MESSAGE):$<
$(MKDIR) -p $(dir $@)
- $(CC) -ppd=$(DEPFILE).P $(_CFLAGS) $(INCLUDES) -fr=$(dir $@) -fs=$(dir $@) $(COMPILEMODE) $<
- $(CC) $(_CFLAGS) $(INCLUDES) -fr=$(dir $@) -fs=$(dir $@) $(COMPILEMODE) $<
+ $(CC) -MMD $(_CFLAGS) $(INCLUDES) -c $(COMPILEMODE) $<
+ $(CC) $(_CFLAGS) $(INCLUDES) -c $(COMPILEMODE) $< -o $@
+
#TODO: Check ASMFLAGS if really required
-ASMFLAGS = -me -g --code_state=16 --diag_warning=225
+ASMFLAGS = -me -g -mthumb --diag_warning=225
# Object file creation
$(OBJ_PATHS_ASM): $(OBJDIR)/%.$(OBJEXT): %.asm $(GEN_FILE) | $(OBJDIR) $(DEPDIR)
$(ECHO) \# Compiling $(PRINT_MESSAGE): $<
- $(CC) -ppd=$(DEPFILE).P $(_CFLAGS) $(INCLUDES) $(CFLAGS_DIROPTS) -fa $<
- $(CC) $(_CFLAGS) $(INCLUDES) $(CFLAGS_DIROPTS) -fa $<
+ $(CC) -MMD $(_CFLAGS) $(INCLUDES) $(CFLAGS_DIROPTS) -x ti-asm $<
+ $(CC) $(_CFLAGS) $(INCLUDES) $(CFLAGS_DIROPTS) -x ti-asm $< -o $@
$(PACKAGE_PATHS): $(PACKAGEDIR)/%: %
$(ECHO) \# Copying to $(PACKAGE_RELPATH)/$($(APP_NAME)$(MODULE_NAME)_RELPATH)/$<
$(CP) --parents -rf $< $(PACKAGE_ROOT)/$($(APP_NAME)$(MODULE_NAME)_RELPATH)
# Archive flags - normally doesn't change
-ARFLAGS = rq
+ARFLAGS = rc
# Archive/library file creation
$(LIBDIR)/$(LIBNAME).$(LIBEXT) : $(OBJ_PATHS_ASM) $(OBJ_PATHS) $(GEN_FILE) | $(LIBDIR)
$(RM) $@temp
# Linker options and rules
-LNKFLAGS_INTERNAL_COMMON += -w -q -u _c_int00
+LNKFLAGS_INTERNAL_COMMON += -Xlinker -q -Xlinker -u -Xlinker _c_int00
ifeq ($(BOARD),$(filter $(BOARD), qtJ7))
- LNKFLAGS_INTERNAL_COMMON += -cr --ram_model
+ LNKFLAGS_INTERNAL_COMMON += -Xlinker -cr -Xlinker --ram_model
else
- LNKFLAGS_INTERNAL_COMMON += -c
+ LNKFLAGS_INTERNAL_COMMON += -Xlinker -c
endif
ifeq ($(CGT_ISA), R5)
- LNKFLAGS_INTERNAL_COMMON += -mv7R5
+ LNKFLAGS_INTERNAL_COMMON += -Xlinker -mcpu=cortex-r5 -Xlinker -march=armv7-r
#--diag_suppress=10063 supresses 'warning: entry point other than _c_int00 specified'
- LNKFLAGS_INTERNAL_COMMON += --diag_suppress=10063
else
ifeq ($(CGT_ISA), M4F)
- LNKFLAGS_INTERNAL_COMMON +=
+ LNKFLAGS_INTERNAL_COMMON += -Xlinker --mcpu=cortex-m4
else
ifeq ($(CGT_ISA), Arm9)
LNKFLAGS_INTERNAL_COMMON +=
else
- LNKFLAGS_INTERNAL_COMMON += --silicon_version=7$(CGT_ISA)
+ LNKFLAGS_INTERNAL_COMMON += -Xlinker --silicon_version=7$(CGT_ISA)
endif
endif
endif
NUM_PROCS = $(shell grep -c ^processor /proc/cpuinfo)
endif
-ifneq ($(findstring mcu,$(CORE)),)
-RTSLIB_NAME = rtsv7R4_T_le_v3D16_eabi.lib
-BUILD_LIB_ONCE = $(CGT_PATH)/lib/$(RTSLIB_NAME)
-$(BUILD_LIB_ONCE):
- $(ECHO) \# $@ not found, building $@ ...
- $(CGT_PATH)/lib/mklib --pattern=$(RTSLIB_NAME) --parallel=$(NUM_PROCS) --compiler_bin_dir=$(CGT_PATH)/bin
-endif
+# Commenting this out as these are already available with compiler
+#ifneq ($(findstring mcu,$(CORE)),)
+#RTSLIB_NAME = rtsv7R4_T_le_v3D16_eabi.lib
+#BUILD_LIB_ONCE = $(CGT_PATH)/lib/$(RTSLIB_NAME)
+#$(BUILD_LIB_ONCE):
+# $(ECHO) \# $@ not found, building $@ ...
+# $(CGT_PATH)/lib/mklib --pattern=$(RTSLIB_NAME) --parallel=$(NUM_PROCS) --compiler_bin_dir=$(CGT_PATH)/bin
+#endif
ifneq ($(XDC_CFG_FILE_$(CORE)),)
$(EXE_NAME) : $(OBJ_PATHS_ASM) $(OBJ_PATHS) $(LIB_PATHS) $(LNKCMD_FILE) $(OBJDIR)/$(CFG_COBJ_XDC) $(BUILD_LIB_ONCE)
ifneq ($(XDC_CFG_FILE_$(CORE)),)
$(CP) $(OBJDIR)/$(CFG_COBJ_XDC) $(CONFIGURO_DIR)/package/cfg
ifeq ($(BUILD_PROFILE_$(CORE)),whole_program_debug)
- $(LNK) $(_LNKFLAGS) $(OBJ_PATHS_ASM) $(OBJ_PATHS) $(OBJDIR)/$(CFG_COBJ_XDC) $(LNKCMD_FILE) $(EXTERNAL_LNKCMD_FILE) $(APPEND_LNKCMD_FILE) -o $@ -m $@.map $(LNK_LIBS) $(RTSLIB_PATH)
+ $(LNK) $(_LNKFLAGS) $(OBJ_PATHS_ASM) $(OBJ_PATHS) $(OBJDIR)/$(CFG_COBJ_XDC) $(LNKCMD_FILE) $(EXTERNAL_LNKCMD_FILE) $(APPEND_LNKCMD_FILE) -o $@ -Xlinker -map_file=$@.map $(LNK_LIBS) $(RTSLIB_PATH)
else
$(LNK) $(_LNKFLAGS) $(OBJ_PATHS_ASM) $(OBJ_PATHS) $(LNKCMD_FILE) $(EXTERNAL_LNKCMD_FILE) $(APPEND_LNKCMD_FILE) -o $@ -m $@.map $(LNK_LIBS) $(RTSLIB_PATH)
endif
else
- $(LNK) $(_LNKFLAGS) $(OBJ_PATHS_ASM) $(OBJ_PATHS) $(LNKCMD_FILE) $(EXTERNAL_LNKCMD_FILE) $(APPEND_LNKCMD_FILE) -o $@ -m $@.map $(LNK_LIBS) $(RTSLIB_PATH)
+ $(LNK) $(_LNKFLAGS) $(OBJ_PATHS_ASM) $(OBJ_PATHS) -Xlinker $(LNKCMD_FILE) $(EXTERNAL_LNKCMD_FILE) $(APPEND_LNKCMD_FILE) -Xlinker --map_file=$@.map -Xlinker --output_file=$@ $(LNK_LIBS) $(RTSLIB_PATH)
endif
$(ECHO) \#
$(ECHO) \# $@ created.
ifndef MODULE_NAME
$(OBJDIR)/$(CFG_COBJ_XDC) : $(CFG_C_XDC)
$(ECHO) \# Compiling generated $(CFG_COBJ_XDC)
- $(CC) -ppd=$(DEPFILE).P $(CFG_C_XDC_CFLAGS) $(INCLUDES) $(CFLAGS_DIROPTS) -fc $(CFG_C_XDC)
- $(CC) $(CFG_C_XDC_CFLAGS) $(INCLUDES) $(CFLAGS_DIROPTS) -fc $(CFG_C_XDC)
+ $(CC) -M $(CFG_C_XDC_CFLAGS) $(INCLUDES) $(CFLAGS_DIROPTS) -x c $(CFG_C_XDC)
+ $(CC) $(CFG_C_XDC_CFLAGS) $(INCLUDES) $(CFLAGS_DIROPTS) -x c $(CFG_C_XDC)
endif
endif
index 27eaf71bc8dcf804d20b0c93f33c3acbfad9c201..2c4799fe45329ff37e9e78fc0aaecbcf390abc98 100644 (file)
CGT_C7X_VERSION=1.4.2.LTS
CGT_ARM_VERSION=20.2.0.LTS
+ CGT_ARMLLVM_VERSION=1.3.0.LTS
GCC_VERSION_HARDLIB=9.2.1
CGT_ARP32_VERSION=1.0.8
export TOOLCHAIN_PATH_A72 ?= $(TOOLCHAIN_PATH_GCC_ARCH64)
export TOOLCHAIN_PATH_EVE ?= $(TOOLS_INSTALL_PATH)/arp32_$(CGT_ARP32_VERSION)
export TOOLCHAIN_PATH_M4 ?= $(TOOLS_INSTALL_PATH)/ti-cgt-arm_$(CGT_ARM_VERSION)
- export TOOLCHAIN_PATH_R5 ?= $(TOOLS_INSTALL_PATH)/ti-cgt-arm_$(CGT_ARM_VERSION)
+ export TOOLCHAIN_PATH_R5 ?= $(TOOLS_INSTALL_PATH)/ti-cgt-armllvm_$(CGT_ARMLLVM_VERSION)
export BIOS_INSTALL_PATH ?= $(SDK_INSTALL_PATH)/bios_$(BIOS_VERSION)
export DSPLIB_INSTALL_PATH ?= $(SDK_INSTALL_PATH)/dsplib_$(DSPLIB_VERSION)
export EDMA3LLD_BIOS6_INSTALLDIR ?= $(SDK_INSTALL_PATH)/edma3_lld_$(EDMA_VERSION)
diff --git a/packages/ti/commit.patch b/packages/ti/commit.patch
--- /dev/null
+++ b/packages/ti/commit.patch
@@ -0,0 +1,622 @@
+commit 63829f8ef9a2766a234dfd77eaa83c24e8ff50cc
+Author: Vivek Dhande <a0132295@ti.com>
+Date: Wed Oct 13 20:20:20 2021 +0530
+
+ [TI Clang Migration][Build Fix]
+
+ Signed-off-by: Vivek Dhande <a0132295@ti.com>
+
+commit 8f936d0adda4887698dbe00390dc2e75312b72fe
+Author: Vivek Dhande <a0132295@ti.com>
+Date: Tue Oct 12 18:39:57 2021 +0530
+
+ [TI Clang Migration][Build Fix]Fixed warning while compiling assembly file
+
+ - Enabled sci-server testapp for both debug and release mode
+ - Updated sci-server testapp linker command file
+
+ Signed-off-by: Vivek Dhande <a0132295@ti.com>
+
+commit 8182e12510296db792b2b817018760f7fd7d0afc
+Author: Vivek Dhande <a0132295@ti.com>
+Date: Mon Oct 11 20:32:49 2021 +0530
+
+ [TI Clang Migration][Build Fix]Disabled Sci-server testapp for debug build to unblock Jenkins
+
+ Signed-off-by: Vivek Dhande <a0132295@ti.com>
+
+commit 9c7c8b82ba7d123d0e281d6c31e8ff41ef5f7231
+Author: Vivek Dhande <a0132295@ti.com>
+Date: Mon Oct 11 20:31:17 2021 +0530
+
+ [TI Clang Migration][Build options]Updated build option after aligning with Compiler team
+
+ - Added '-O1' option for debug build
+ - Checked in new ccs init and sci-server testapp bins
+
+ Signed-off-by: Vivek Dhande <a0132295@ti.com>
+
+commit 5321c7b16bebb2ff9adfb3a6aba8d9421d01e48c
+Author: Misael Lopez Cruz <misael.lopez@ti.com>
+Date: Thu Oct 7 12:25:50 2021 -0500
+
+ [TI Clang Migration] Re-enable lwIP in makefile
+
+ Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
+
+commit c9eff352053c35400fa13cae7e544c66b801bee1
+Author: Vivek Dhande <a0132295@ti.com>
+Date: Wed Oct 6 23:23:39 2021 +0530
+
+ [TI Clang Migration][Sci-client]Fixed issue with sci-server testApp
+
+ - Fixed miss-aligned caused due to misplaced sections 'OCMC_RAM_X509_HEADER1' and 'OCMC_RAM_X509_HEADER2'
+
+ Signed-off-by: Vivek Dhande <a0132295@ti.com>
+
+commit e88fafc1948fa109690c620079998433748f80bd
+Author: Vivek Dhande <a0132295@ti.com>
+Date: Wed Oct 6 23:22:10 2021 +0530
+
+ [TI Clang Migration][Link Warnings Fixed]warning: entry-point symbol other than "_c_int00" specified:
+
+ Signed-off-by: Vivek Dhande <a0132295@ti.com>
+
+commit 1097fe682fc57abe8cf5ce404943f157f26774a3
+Author: Vivek Dhande <a0132295@ti.com>
+Date: Wed Oct 6 23:20:12 2021 +0530
+
+ [TI Clang Migration][Compile Warnings Fixed]Removed '.asmfunc' and '.endasmfunc' to fix compiler warnings
+
+ Signed-off-by: Vivek Dhande <a0132295@ti.com>
+
+commit 7527994d85dfae33c0b13e28f545bcdb7ecbefdb
+Author: Vivek Dhande <a0132295@ti.com>
+Date: Tue Oct 5 17:47:08 2021 +0530
+
+ [TI Clang Migration][SafeRTOS]Disabled build for safeRTOS
+
+ - This is not ported yet by WHIS team
+
+ Signed-off-by: Vivek Dhande <a0132295@ti.com>
+
+commit a767a48d0a18271d9b7c2725e7d8b22e566b6b57
+Author: Vivek Dhande <a0132295@ti.com>
+Date: Fri Oct 1 13:53:47 2021 +0530
+
+ [TI Clang Migration][Fixed Review Comments][IPC]
+
+ Signed-off-by: Vivek Dhande <a0132295@ti.com>
+
+commit f20808b2800225d8628b397e3649265c5e05f9da
+Author: Vivek Dhande <a0132295@ti.com>
+Date: Fri Oct 1 08:32:52 2021 +0530
+
+ [TI Clang Migration][IPC]Porting + Build Fix
+
+ - Re-enabled freeRTOS for TIRTOS as this is supported on other cores
+ - Fixed IPC multi-core app build
+
+ Signed-off-by: Vivek Dhande <a0132295@ti.com>
+
+commit 42c4390f55cd8e6a20f08083547c64b81ca30ecb
+Author: Vivek Dhande <a0132295@ti.com>
+Date: Thu Sep 30 16:20:49 2021 +0530
+
+ [TI Clang Migration][Build]Porting + Build Fix
+
+ - Switched from '-O3' to '-Oz' optimization level to reduce code size
+ - Some applications on mcu1_0 were not able to fit into OCMCRAM due to increase in code size because of '-O3'
+ - Added option to chose between '-O3' and '-Oz'
+
+ Signed-off-by: Vivek Dhande <a0132295@ti.com>
+
+commit d4c3c1748c77f46d69e92239aadb5e19c9418149
+Author: Vivek Dhande <a0132295@ti.com>
+Date: Thu Sep 30 15:37:31 2021 +0530
+
+ [AM65xx][TI Clang Migration][SBL]Minot Linker Command update
+
+ Signed-off-by: Vivek Dhande <a0132295@ti.com>
+
+commit 654515b1b92e220a6e0f8b508a853406a2767a11
+Author: Vivek Dhande <a0132295@ti.com>
+Date: Thu Sep 30 15:34:10 2021 +0530
+
+ [AM65xx][TI Clang Migration][EMAC]Disabled EMAC as it is only supported on TIRTOS
+
+ Signed-off-by: Vivek Dhande <a0132295@ti.com>
+
+commit a0c9294bb117a3ed95a63085a5a3b17cd2846781
+Author: Vivek Dhande <a0132295@ti.com>
+Date: Thu Sep 30 15:32:43 2021 +0530
+
+ [AM65xx][TI Clang Migration][NIMU]Disabled NIMU as it is only supported on TIRTOS
+
+ Signed-off-by: Vivek Dhande <a0132295@ti.com>
+
+commit eb88453ac51859591e02ec53f299efc13db07836
+Author: Vivek Dhande <a0132295@ti.com>
+Date: Thu Sep 30 15:25:29 2021 +0530
+
+ [AM65xx][TI Clang Migration][FREERTOS]Porting + Build Fix
+
+ Signed-off-by: Vivek Dhande <a0132295@ti.com>
+
+commit c16543ea6bdb745cb499353ce3ff32f5d43d2e67
+Author: Vivek Dhande <a0132295@ti.com>
+Date: Thu Sep 30 15:24:36 2021 +0530
+
+ [AM65xx][TI Clang Migration][Diag/SDR]Porting + Build Fix
+
+ Signed-off-by: Vivek Dhande <a0132295@ti.com>
+
+commit 3700ec4e94a7214b95e1018a66b721d9d418154e
+Author: Vivek Dhande <a0132295@ti.com>
+Date: Thu Sep 30 15:23:50 2021 +0530
+
+ [J7200][TI Clang Migration][SBL]One minor linker command file change
+
+ Signed-off-by: Vivek Dhande <a0132295@ti.com>
+
+commit 4510f832778e495eb4fab6a5b40b579e7d8bc52b
+Author: Vivek Dhande <a0132295@ti.com>
+Date: Thu Sep 30 15:21:31 2021 +0530
+
+ [AM65xx][TI Clang Migration][USB]Porting + Build Fix
+
+ Signed-off-by: Vivek Dhande <a0132295@ti.com>
+
+commit 14c42b66ec61be68154f69b6db4139216297d6b3
+Author: Vivek Dhande <a0132295@ti.com>
+Date: Thu Sep 30 15:19:41 2021 +0530
+
+ [AM65xx][TI Clang Migration][PCIe]Porting + Build Fix
+
+ - Removed <module>_profile libs due to PDK utils issue
+
+ Signed-off-by: Vivek Dhande <a0132295@ti.com>
+
+commit c328b6e5afb5e534596517b786be53a4fb6d05f9
+Author: Vivek Dhande <a0132295@ti.com>
+Date: Thu Sep 30 15:15:43 2021 +0530
+
+ [AM65xx][TI Clang Migration][Board]Porting + Build Fix
+
+ - Disabled EMAC related Diag tests
+
+ Signed-off-by: Vivek Dhande <a0132295@ti.com>
+
+commit 6868b9f6de37d56c7dab6b1d697f74ae837be374
+Author: Vivek Dhande <a0132295@ti.com>
+Date: Wed Sep 29 12:45:50 2021 +0530
+
+ [J7200][TI Clang Migration][IPC]Porting + Build Fix
+
+ - Updated for TIRTOS apps build
+
+ Signed-off-by: Vivek Dhande <a0132295@ti.com>
+
+commit 77df47c5ca0992098e4d192a7f678a4ae3ceb1eb
+Author: Vivek Dhande <a0132295@ti.com>
+Date: Wed Sep 29 12:44:23 2021 +0530
+
+ [J7200][TI Clang Migration][LWIP/EMAC]Porting + Build Fix
+
+ Signed-off-by: Vivek Dhande <a0132295@ti.com>
+
+commit 33ddc0d214f8f55c9e5ebdeaf2f7cab7c517af5e
+Author: Vivek Dhande <a0132295@ti.com>
+Date: Wed Sep 29 12:42:38 2021 +0530
+
+ [J7200][TI Clang Migration][Build]Porting + Build Fix
+
+ - Disabled mcu2_0 and mcu2_1 cores for TIRTOS/SYSBIOS
+
+ Signed-off-by: Vivek Dhande <a0132295@ti.com>
+
+commit e570ba3f57697de6059e53246f294cd151ab6f35
+Author: Vivek Dhande <a0132295@ti.com>
+Date: Wed Sep 29 12:41:27 2021 +0530
+
+ [J7200][TI Clang Migration][PCIe]Porting + Build Fix
+
+ Signed-off-by: Vivek Dhande <a0132295@ti.com>
+
+commit 06707f11dfda5af220ee96b4ebb4924458800270
+Author: Vivek Dhande <a0132295@ti.com>
+Date: Wed Sep 29 12:25:54 2021 +0530
+
+ [J7200][TI Clang Migration][Board]Porting + Build Fix
+
+ Signed-off-by: Vivek Dhande <a0132295@ti.com>
+
+commit 157d32524ae63f521abd059020f6b40c7e94b047
+Author: Vivek Dhande <a0132295@ti.com>
+Date: Thu Sep 23 16:30:45 2021 +0530
+
+ [TI Clang Migration][Sci-client]Build Fix
+
+ - Linker command file changes
+
+ Signed-off-by: Vivek Dhande <a0132295@ti.com>
+
+commit cd48f5371de1bb6a465a9cd51ee981945d160a99
+Author: Vivek Dhande <a0132295@ti.com>
+Date: Thu Sep 23 16:29:15 2021 +0530
+
+ [TI Clang Migration][Sci-client]Porting to Clang
+
+ Signed-off-by: Vivek Dhande <a0132295@ti.com>
+
+commit e4bcc95c26fa6166f4dfc8d5712df0addbed4cdd
+Author: Vivek Dhande <a0132295@ti.com>
+Date: Thu Sep 23 16:26:28 2021 +0530
+
+ [TI Clang Migration][SBL]Porting to Clang patch-4
+
+ - Fixed mcu1_0, mcu1_1 builds: increased MSMC3 memory size
+
+ Signed-off-by: Vivek Dhande <a0132295@ti.com>
+
+commit 4ea94c04e9b4c82a89c6cb2c7568431ab7d721ec
+Author: Vivek Dhande <a0132295@ti.com>
+Date: Thu Sep 23 16:25:25 2021 +0530
+
+ [TI Clang Migration][SBL]Porting to Clang patch-3
+
+ - Fixed mcu1_0, mcu1_1 builds
+
+ Signed-off-by: Vivek Dhande <a0132295@ti.com>
+
+commit c863c1020ba91927aa08297053bc86a348c96490
+Author: Vivek Dhande <a0132295@ti.com>
+Date: Thu Sep 23 16:21:03 2021 +0530
+
+ [TI Clang Migration][Keywriter]
+
+ Signed-off-by: Vivek Dhande <a0132295@ti.com>
+
+commit 450301eb77b021909c2024caa78668faa7446d85
+Author: Vivek Dhande <a0132295@ti.com>
+Date: Thu Sep 23 16:19:34 2021 +0530
+
+ [Keywriter]Disabled application for TI Clang Migration, for build fix
+
+ Signed-off-by: Vivek Dhande <a0132295@ti.com>
+
+commit 09e2b3322ccf1425f51b1188dc9fe3464d9e950c
+Author: Vivek Dhande <a0132295@ti.com>
+Date: Wed Sep 22 00:29:00 2021 +0530
+
+ [TI Clang Migration][Sci-client]Porting to Clang
+
+ Signed-off-by: Vivek Dhande <a0132295@ti.com>
+
+commit 3fe25dc6ecaf2e95965949851dec0d8d4a4615ee
+Author: Vivek Dhande <a0132295@ti.com>
+Date: Wed Sep 22 00:25:51 2021 +0530
+
+ [TI Clang Migration]Porting to Clang
+
+ - Added '*.d' and '*.o' for ignoring these compiler generated files
+
+ Signed-off-by: Vivek Dhande <a0132295@ti.com>
+
+commit bda595e741d406266ea927bb2d19313346359d64
+Author: Vivek Dhande <a0132295@ti.com>
+Date: Wed Sep 22 00:24:29 2021 +0530
+
+ [TI Clang Migration][PDK Utils]Disabled PDK Utils based libs/apps
+ - disabling this as entry/exit hook arguments are not supported by clang
+
+ Signed-off-by: Vivek Dhande <a0132295@ti.com>
+
+commit 7e1cb051c07df0f7bfb8462a1e3a320ffefd89b1
+Author: Vivek Dhande <a0132295@ti.com>
+Date: Wed Sep 22 00:23:08 2021 +0530
+
+ [TI Clang Migration][PDK Utils][Transport]Disabled PDK Utils based libs/apps
+ - Disabled NIMU as it is only built for TIRTOS
+
+ Signed-off-by: Vivek Dhande <a0132295@ti.com>
+
+commit bae28a2773a63d7cb41c91c7824964d162211af7
+Author: Vivek Dhande <a0132295@ti.com>
+Date: Wed Sep 22 00:22:01 2021 +0530
+
+ [TI Clang Migration][Transport]Porting to Clang
+
+ Signed-off-by: Vivek Dhande <a0132295@ti.com>
+
+commit 59c896eb9e5b7785f61f211901b91ed356e1e35c
+Author: Vivek Dhande <a0132295@ti.com>
+Date: Wed Sep 22 00:19:59 2021 +0530
+
+ [TI Clang Migration][PDK Utils][OSAL]Disabled PDK Utils based libs/apps
+
+ - disabling this as entry/exit hook arguments are not supported by clang
+ - disabling mcu build for TIRTOS
+
+ Signed-off-by: Vivek Dhande <a0132295@ti.com>
+
+commit 5be24ce0571308dd9e7b48d91d5247396a0416d5
+Author: Vivek Dhande <a0132295@ti.com>
+Date: Wed Sep 22 00:18:55 2021 +0530
+
+ [TI Clang Migration][OSAL]Porting to Clang
+
+ Signed-off-by: Vivek Dhande <a0132295@ti.com>
+
+commit e5b86ebac2dda8fb179b37f775e6b131d875319f
+Author: Vivek Dhande <a0132295@ti.com>
+Date: Wed Sep 22 00:17:21 2021 +0530
+
+ [TI Clang Migration][FreeRTOS]Disabled C99 build as it does not supprot 'asm()'
+
+ Signed-off-by: Vivek Dhande <a0132295@ti.com>
+
+commit 093c340e172d671928c2124c597e37b90b9710ce
+Author: Vivek Dhande <a0132295@ti.com>
+Date: Wed Sep 22 00:14:40 2021 +0530
+
+ [TI Clang Migration][PDK Utils][FATFS]Disabled PDK Utils based libs/apps
+
+ - disabling this as entry/exit hook arguments are not supported by clang
+
+ Signed-off-by: Vivek Dhande <a0132295@ti.com>
+
+commit 48d1d96ed1a9d64103fddb7312a5cb7f6ee7ce95
+Author: Vivek Dhande <a0132295@ti.com>
+Date: Wed Sep 22 00:12:24 2021 +0530
+
+ [TI Clang Migration][FATFS]Porting to Clang
+
+ Signed-off-by: Vivek Dhande <a0132295@ti.com>
+
+commit 8b030fc4033834252a827142751beaa6152da9cb
+Author: Vivek Dhande <a0132295@ti.com>
+Date: Wed Sep 22 00:10:01 2021 +0530
+
+ [PDK-9552][TI CLANG Migration] R5 Drivers Updates and Testing: UDMA
+
+ Signed-off-by: Vivek Dhande <a0132295@ti.com>
+
+commit b0488dd5f2223ce6fa521cba09078abbaf1b7498
+Author: Vivek Dhande <a0132295@ti.com>
+Date: Wed Sep 22 00:08:40 2021 +0530
+
+ [TI Clang Migration][PDK Utils][UART]Disabled PDK Utils based libs/apps
+
+ - disabling this as entry/exit hook arguments are not supported by clang
+
+ Signed-off-by: Vivek Dhande <a0132295@ti.com>
+
+commit 1f08e9621f6691d06d8f31fadb573bfae2ea8f6d
+Author: Vivek Dhande <a0132295@ti.com>
+Date: Wed Sep 22 00:08:06 2021 +0530
+
+ [PDK-9554][TI CLANG Migration] R5 Drivers Updates and Testing: UART
+
+ Signed-off-by: Vivek Dhande <a0132295@ti.com>
+
+commit 7de025b55bc2b009c492b93c64b376e6ab325904
+Author: Vivek Dhande <a0132295@ti.com>
+Date: Wed Sep 22 00:06:45 2021 +0530
+
+ [TI Clang Migration][PDK Utils][SPI]Disabled PDK Utils based libs/apps
+
+ - disabling this as entry/exit hook arguments are not supported by clang
+
+ Signed-off-by: Vivek Dhande <a0132295@ti.com>
+
+commit c925225e79d57d8f9c0cf37946cbc7e6df681bd7
+Author: Vivek Dhande <a0132295@ti.com>
+Date: Wed Sep 22 00:06:00 2021 +0530
+
+ [PDK-9556][TI CLANG Migration] R5 Drivers Updates and Testing: SPI
+
+ Signed-off-by: Vivek Dhande <a0132295@ti.com>
+
+commit 971674400ff1df3331fb00b1c897f3b8f56bb1bd
+Author: Vivek Dhande <a0132295@ti.com>
+Date: Tue Sep 21 23:57:35 2021 +0530
+
+ [TI Clang Migration][Sci-Sclient]Porting to Clang
+
+ Signed-off-by: Vivek Dhande <a0132295@ti.com>
+
+commit 7f6bad56a1604f90b25a56ae7c926676d4768bc7
+Author: Vivek Dhande <a0132295@ti.com>
+Date: Tue Sep 21 23:54:33 2021 +0530
+
+ [TI Clang Migration][PDK Utils][PRUSS]Disabled PDK Utils based libs/apps
+
+ - disabling this as entry/exit hook arguments are not supported by clang
+
+ Signed-off-by: Vivek Dhande <a0132295@ti.com>
+
+commit 660662568dc0b2c2b8dc68e29c60196794779d01
+Author: Vivek Dhande <a0132295@ti.com>
+Date: Tue Sep 21 23:53:30 2021 +0530
+
+ [TI Clang Migration][PDK Utils][MMCSD]Disabled PDK Utils based libs/apps
+
+ - disabling this as entry/exit hook arguments are not supported by clang
+ Signed-off-by: Vivek Dhande <a0132295@ti.com>
+
+commit 738df0c1cce9ecf7697ee7454402e54bbcd2f261
+Author: Vivek Dhande <a0132295@ti.com>
+Date: Tue Sep 21 23:52:37 2021 +0530
+
+ [PDK-9554][TI CLANG Migration] R5 Drivers Updates and Testing: MMCSD
+
+ Signed-off-by: Vivek Dhande <a0132295@ti.com>
+
+commit 0dd70107235bc713774887efbbec0db2096d7c65
+Author: Vivek Dhande <a0132295@ti.com>
+Date: Tue Sep 21 23:50:10 2021 +0530
+
+ [TI Clang Migration][PDK Utils][McASP]Disabled PDK Utils based libs/apps
+
+ - disabling this as entry/exit hook arguments are not supported by clang
+
+ Signed-off-by: Vivek Dhande <a0132295@ti.com>
+
+commit 1ac33d82c55da50e53e00a06bbdb7b8d04bd0ade
+Author: Vivek Dhande <a0132295@ti.com>
+Date: Tue Sep 21 23:49:18 2021 +0530
+
+ [TI Clang Migration][McASP]Porting to Clang
+
+ Signed-off-by: Vivek Dhande <a0132295@ti.com>
+
+commit 025f02b3865f8fb7226d09fef999a1b364f2f520
+Author: Vivek Dhande <a0132295@ti.com>
+Date: Tue Sep 21 23:46:58 2021 +0530
+
+ [TI Clang Migration][PDK Utils][EMAC]Disabled PDK Utils based libs/apps
+
+ - disabling this as entry/exit hook arguments are not supported by clang
+
+ Signed-off-by: Vivek Dhande <a0132295@ti.com>
+
+commit be3ca97c01283d9ba52aba27aa1fbc909281a8bd
+Author: Vivek Dhande <a0132295@ti.com>
+Date: Tue Sep 21 23:45:09 2021 +0530
+
+ [TI Clang Migration][PDK Utils][DSS]Disabled PDK Utils based libs/apps
+
+ - disabling this as entry/exit hook arguments are not supported by clang
+
+ Signed-off-by: Vivek Dhande <a0132295@ti.com>
+
+commit 0e5cef91bd595e235bdb76ed50b9ce119f8bffaf
+Author: Vivek Dhande <a0132295@ti.com>
+Date: Tue Sep 21 23:42:52 2021 +0530
+
+ [TI Clang Migration][DIAG/SDR]Porting to Clang
+
+ Signed-off-by: Vivek Dhande <a0132295@ti.com>
+
+commit cd89fbc9ba5d5529565b1cfa40a45a3fffb5c21e
+Author: Vivek Dhande <a0132295@ti.com>
+Date: Tue Sep 21 23:40:04 2021 +0530
+
+ [TI Clang Migration][Build]Disabled mcu core for TIRTOS build
+
+ - Disabled NIMU as it is only built for TIRTOS
+
+ Signed-off-by: Vivek Dhande <a0132295@ti.com>
+
+commit a6aad1e0d7a4100d5ae79271f8a7c91aca18ab40
+Author: Vivek Dhande <a0132295@ti.com>
+Date: Tue Sep 21 23:38:42 2021 +0530
+
+ [TI Clang Migration][Build]Added options for additional warning suppression
+
+ Signed-off-by: Vivek Dhande <a0132295@ti.com>
+
+commit 4914486c04650235c5a2328d4213676f6bd0fd82
+Author: Vivek Dhande <a0132295@ti.com>
+Date: Tue Sep 21 23:36:10 2021 +0530
+
+ [TI Clang Migration][SBL]Porting to Clang patch-2
+
+ - Increased memory section size for SBL OCM section, took the extra space from reserved 'OCMRAM_SBL_RESERVED_CUST_BOOT' section
+ - check if this is OK?
+
+ Signed-off-by: Vivek Dhande <a0132295@ti.com>
+
+commit 653d7b6ba14319f89b7b679809b468c9cca72c6b
+Author: Vivek Dhande <a0132295@ti.com>
+Date: Tue Sep 21 23:33:56 2021 +0530
+
+ [TI Clang Migration][SBL]Porting to Clang
+
+ Signed-off-by: Vivek Dhande <a0132295@ti.com>
+
+commit 53ed046f625855db7e441566de63c42399b19662
+Author: Vivek Dhande <a0132295@ti.com>
+Date: Tue Sep 21 23:30:39 2021 +0530
+
+ [TI Clang Migration][Board]Porting to Clang
+
+ - increased OCMC memory size to 1MB for J721E for /packages/ti/board/utils/uniflash/target/soc/k3/linker_j7.cmd
+
+ Signed-off-by: Vivek Dhande <a0132295@ti.com>
+
+commit 938ce270cdca7e8cf93e25ae7ce51cb55fb63dad
+Author: Vivek Dhande <a0132295@ti.com>
+Date: Mon Sep 6 09:51:44 2021 +0530
+
+ [PDK-9555][TI CLANG Migration] R5 Drivers Updates and Testing: IPC, VISS, LDC, NF, SDE, MSC, DOF: Patch-1
+
+ - IPC driver changes
+ - Additional warnings ignored
+
+ Signed-off-by: Vivek Dhande <a0132295@ti.com>
+
+commit 96b8ee392a91e9e8c6bb76dfdf1e7753f2a35dcd
+Author: Aditya Wadhwa <a0485151@ti.com>
+Date: Tue Oct 12 12:49:41 2021 +0530
+
+ LPM: Add docs/ folder
+
+ Signed-off-by: Aditya Wadhwa <a0485151@ti.com>
+
+commit 5025b2132186db8462a771f295355a47d334eff4
+Author: Parth Nagpal <x1080849@ti.com>
+Date: Tue Oct 5 17:02:18 2021 +0530
+
+ Changing sbl_component.mk as per comment
+
+commit efe7eb5872b91fe719edfa6e91cac2212e13ffba
+Author: Parth Nagpal <x1080849@ti.com>
+Date: Tue Sep 14 19:24:17 2021 +0530
+
+ sbl_cust_img not booting mcu1_1
+ Issue is fixed by removing SBL_SKIP_MCU_RESET flag
+
+ Signed-off-by: Parth Nagpal <x1080849@ti.com>
+
+ Changes for turning off rti module
+ RTI module turned off for AM65xx when SBL_SKIP_MCU_RESET is defined
+
+ Signed-off-by: Parth Nagpal <x1080849@ti.com>
+
+commit 05ef6eeab18b883f44d291474be20aa057c82e6e
+Author: Potluri Krishna <x1082264@ti.com>
+Date: Wed Oct 13 15:39:36 2021 +0530
+
+ updating the core list to mcu1_0 for enet icssg diag test
+
+commit 25e1a62dafa7f38a09704789bef11fe60c34a725
+Author: Ankur <a0132173@ti.com>
+Date: Wed Oct 13 09:39:30 2021 +0530
+
+ Diabling enetIcssg due to build error
+
+ Signed-off-by: Ankur <a0132173@ti.com>
+
+commit 20182042ce1edd30be56e8b25dda11264c92ec2d
+Author: Potluri Krishna <x1082264@ti.com>
+Date: Tue Oct 12 21:43:52 2021 +0530
+
+ updating the size of tx and rx frames inside memset
+
+commit de0fd2fa5bd56af6ada782d62390650687f4c11c
+Author: Ankur <a0132173@ti.com>
+Date: Tue Oct 12 01:33:41 2021 +0530
+
+ Diable LPM due to build issue
+
+ Signed-off-by: Ankur <a0132173@ti.com>
+
+commit 35dbaf1a1adb46aa807b96960bafecbd24ec5e4d
+Author: Aditya Wadhwa <a0485151@ti.com>
+Date: Mon Oct 11 22:23:33 2021 +0530
+
+ LPM: Function and variable name fixes
+
+ Signed-off-by: Aditya Wadhwa <a0485151@ti.com>
diff --git a/packages/ti/drv/dss/examples/dss_display_test/main_rtos.c b/packages/ti/drv/dss/examples/dss_display_test/main_rtos.c
index f86052b5c2f1ab9578c1793210c2e6ab6ade4348..7ba59f657c41b7f8ab25003ea94586ed1c7a4704 100755 (executable)
}
else
{
- printf("\nDisplay Test Task - Load: < 1% \n");
+ printf("\nDisplay Test Task - Load: < 1%% \n");
}
/* Query CPU Load */
diff --git a/packages/ti/drv/dss/examples/dss_m2m_test/dss_m2m_test.c b/packages/ti/drv/dss/examples/dss_m2m_test/dss_m2m_test.c
index 891bcf98c163d94b095e0b846f6db3dfeafd04a1..cf3a7aa6ba0ee4c101535abc78f96e61f53facbc 100755 (executable)
M2MApp_AppObj gM2MAppObj;
uint32_t gTestStopTime, gTestStartTime;
-#ifdef __cplusplus
-#pragma DATA_SECTION(".data_buffer")
-#pragma DATA_ALIGN(128)
-#else
-#pragma DATA_SECTION(gOutFrms, ".data_buffer")
-#pragma DATA_ALIGN(gOutFrms, 128)
-#endif /* #ifdef __cplusplus */
/* This buffer will be used to store RGB or Y */
static uint8_t gOutFrms[(APP_DSS_M2M_CH_NUM * APP_DSS_M2M_DSS_PIPE_NUM)][(APP_DSS_M2M_OUT_FRAME_PITCH * APP_DSS_M2M_OUT_FRAME_HEIGHT)] __attribute__(( aligned(128), section(".data_buffer")));
/* This buffer will be used to store UV */
index 9f9c3dbda626070262c0df6b4d26534746b47c60..05eba89ad5b2fefa6aebf5169a04fcc8914621a2 100644 (file)
#if defined (__aarch64__)
interruptRegParams.corepacConfig.triggerSensitivity = (uint32_t)OSAL_ARM_GIC_TRIG_TYPE_EDGE; /* interrupt edge triggered */
#endif
-#if defined (__TI_ARM_V7R4__)
+#if (__ARM_ARCH == 7) && (__ARM_ARCH_PROFILE == 'R') /* R5F */
interruptRegParams.corepacConfig.triggerSensitivity = (uint32_t)OSAL_ARM_GIC_TRIG_TYPE_EDGE;
#endif
/* Configure SOC interrupt path if any */
diff --git a/packages/ti/drv/gpio/test/led_blink/am64x/GPIO_board.c b/packages/ti/drv/gpio/test/led_blink/am64x/GPIO_board.c
index 5ba4d33d6abaa01a810feed6dfbff8006deb2c65..0e9aa4d6d3ddaff5075769b15adf424c4fcb3ffd 100644 (file)
gpioCallbackFunctions,
sizeof(gpioPinConfigs) / sizeof(GPIO_PinConfig),
sizeof(gpioCallbackFunctions) / sizeof(GPIO_CallbackFxn),
-#ifdef __TI_ARM_V7R4__
+#if (__ARM_ARCH == 7) && (__ARM_ARCH_PROFILE == 'R') /* R5F */
0x8U
#else
0x20U
diff --git a/packages/ti/drv/gpio/test/led_blink/am65xx/GPIO_board.c b/packages/ti/drv/gpio/test/led_blink/am65xx/GPIO_board.c
index f38eed6261821e5d392a56d0dd254db46ff86a45..a0642ba5a9f07564ea2e42a31263385f2c9353c2 100644 (file)
gpioCallbackFunctions,
sizeof(gpioPinConfigs) / sizeof(GPIO_PinConfig),
sizeof(gpioCallbackFunctions) / sizeof(GPIO_CallbackFxn),
-#ifdef __TI_ARM_V7R4__
+#if (__ARM_ARCH == 7) && (__ARM_ARCH_PROFILE == 'R') /* R5F */
0x8U
#else
0x20U
diff --git a/packages/ti/drv/gpio/test/led_blink/j7200/GPIO_board.c b/packages/ti/drv/gpio/test/led_blink/j7200/GPIO_board.c
index c0ee2a1f08daa95c53b49575e78145fbad5216b1..cf9744507348d02ec945f32151a0ca2863b0bcac 100644 (file)
gpioCallbackFunctions,
sizeof(gpioPinConfigs) / sizeof(GPIO_PinConfig),
sizeof(gpioCallbackFunctions) / sizeof(GPIO_CallbackFxn),
-#ifdef __TI_ARM_V7R4__
+#if (__ARM_ARCH == 7) && (__ARM_ARCH_PROFILE == 'R') /* R5F */
0x8U
#else
0x20U
diff --git a/packages/ti/drv/gpio/test/led_blink/j721e/GPIO_board.c b/packages/ti/drv/gpio/test/led_blink/j721e/GPIO_board.c
index 5f4645bdddbcf18f2c1bf53768371a71633d65fe..afa55585febb82e7a7453b517cd0610fb16e4dc0 100644 (file)
gpioCallbackFunctions,
sizeof(gpioPinConfigs) / sizeof(GPIO_PinConfig),
sizeof(gpioCallbackFunctions) / sizeof(GPIO_CallbackFxn),
-#ifdef __TI_ARM_V7R4__
+#if (__ARM_ARCH == 7) && (__ARM_ARCH_PROFILE == 'R') /* R5F */
0x8U
#else
#if defined(__C7100__)
diff --git a/packages/ti/drv/gpio/test/led_blink/src/GPIO_board.h b/packages/ti/drv/gpio/test/led_blink/src/GPIO_board.h
index b9317c0bc49ca8aae3005c9b2355355387f12da2..c51805f47a938a8149127961342d8ffec026a9ce 100644 (file)
Driver defines the macros for each of the GPIO pins of the SoC.
The application needs to pass these macros for each of the GPIO APIs as the
index value. */
-#if defined (__TI_ARM_V7R4__)
+#if (__ARM_ARCH == 7) && (__ARM_ARCH_PROFILE == 'R') /* R5F */
/* tpr12: Use MSS GIO port 0 pin 1 and pin 2 for testing on QT.
MSS GIO port 0 pin1 and pin2 are connected to PADAC and PADAZ.
These are internally connected to TB_GIO port 0 pin 0 and 1.
Driver defines the macros for each of the GPIO pins of the SoC.
The application needs to pass these macros for each of the GPIO APIs as the
index value. */
-#if defined (__TI_ARM_V7R4__)
+#if (__ARM_ARCH == 7) && (__ARM_ARCH_PROFILE == 'R') /* R5F */
/* tpr12: Use MSS GIO port 0 pin 1 and pin 2 for testing on QT.
MSS GIO port 0 pin1 and pin2 are connected to PADAC and PADAZ.
These are internally connected to TB_GIO port 0 pin 0 and 1.
diff --git a/packages/ti/drv/ipc/examples/common/j721e/freertos/linker_r5f_freertos_common.inc b/packages/ti/drv/ipc/examples/common/j721e/freertos/linker_r5f_freertos_common.inc
index d1754141292b1aa9c8e6d0536204843807783bb4..376b279eedd7c3d0cc451622a65ae6af7cb39543 100644 (file)
.text : {} palign(8) > __CORE_DDR_SPACE
.const : {} palign(8) > __CORE_DDR_SPACE
+ .rodata : {} palign(8) > __CORE_DDR_SPACE
.cinit : {} palign(8) > __CORE_DDR_SPACE
.bss : {} align(4) > __CORE_DDR_SPACE
.far : {} align(4) > __CORE_DDR_SPACE
diff --git a/packages/ti/drv/ipc/examples/common/j721e/linker_r5f_mcu1_0.lds b/packages/ti/drv/ipc/examples/common/j721e/linker_r5f_mcu1_0.lds
index adb73e5a1cd5f8756d1dbaf7a18ec94fe7d2c3e8..5937d44a85ddbf10e690b91999f8c33d7198f986 100644 (file)
.startupData : {} palign(8) > MCU0_R5F_TCMA, type = NOINIT
.text : {} palign(8) > MCU1_0_DDR_SPACE
.const : {} palign(8) > MCU1_0_DDR_SPACE
+ .rodata : {} palign(8) > MCU1_0_DDR_SPACE
.cinit : {} palign(8) > MCU1_0_DDR_SPACE
.pinit : {} palign(8) > MCU1_0_DDR_SPACE
.bss : {} align(4) > MCU1_0_DDR_SPACE
diff --git a/packages/ti/drv/ipc/examples/common/j721e/linker_r5f_mcu1_0_btcm.lds b/packages/ti/drv/ipc/examples/common/j721e/linker_r5f_mcu1_0_btcm.lds
index d161dc41804b934afd8a157f002419abfac614d9..80c2848ea885491bcb1016d333daf563396e22a7 100644 (file)
.startupData : {} palign(8) > MCU1_R5F0_BTCM, type = NOINIT
.text : {} palign(8) > MCU1_0_DDR_SPACE
.const : {} palign(8) > MCU1_0_DDR_SPACE
+ .rodata : {} palign(8) > MCU1_0_DDR_SPACE
.cinit : {} palign(8) > MCU1_0_DDR_SPACE
.pinit : {} palign(8) > MCU1_0_DDR_SPACE
.bss : {} align(4) > MCU1_0_DDR_SPACE
diff --git a/packages/ti/drv/ipc/examples/common/j721e/linker_r5f_mcu1_0_btcm_sysbios.lds b/packages/ti/drv/ipc/examples/common/j721e/linker_r5f_mcu1_0_btcm_sysbios.lds
index 0f609387516c6026348e50def052d7742a13db9d..f23515d5a13c29d9b5eb363a85d0b7b22366ae45 100644 (file)
.ipcCopyVecsToExc : {} palign(8) > MCU1_R5F0_BTCM
.text : {} palign(8) > MCU1_0_DDR_SPACE
.const : {} palign(8) > MCU1_0_DDR_SPACE
+ .rodata : {} palign(8) > MCU1_0_DDR_SPACE
.cinit : {} palign(8) > MCU1_0_DDR_SPACE
.pinit : {} palign(8) > MCU1_0_DDR_SPACE
.bss : {} align(4) > MCU1_0_DDR_SPACE
diff --git a/packages/ti/drv/ipc/examples/common/j721e/linker_r5f_mcu1_0_sbl_sysbios.lds b/packages/ti/drv/ipc/examples/common/j721e/linker_r5f_mcu1_0_sbl_sysbios.lds
index d0c8e9e10f2205fc5d56dc4cf03255fa45cd0caf..20a4b96be0abbd4e88aa2750d46a3861f0b95768 100644 (file)
.startupData : {} palign(8) > MCU1_R5F0_BTCM, type = NOINIT
.text : {} palign(8) > MCU1_0_DDR_SPACE
.const : {} palign(8) > MCU1_0_DDR_SPACE
+ .rodata : {} palign(8) > MCU1_0_DDR_SPACE
.cinit : {} palign(8) > MCU1_0_DDR_SPACE
.pinit : {} palign(8) > MCU1_0_DDR_SPACE
.bss : {} align(4) > MCU1_0_DDR_SPACE
diff --git a/packages/ti/drv/ipc/examples/common/j721e/linker_r5f_mcu1_0_sysbios.lds b/packages/ti/drv/ipc/examples/common/j721e/linker_r5f_mcu1_0_sysbios.lds
index d0c8e9e10f2205fc5d56dc4cf03255fa45cd0caf..20a4b96be0abbd4e88aa2750d46a3861f0b95768 100644 (file)
.startupData : {} palign(8) > MCU1_R5F0_BTCM, type = NOINIT
.text : {} palign(8) > MCU1_0_DDR_SPACE
.const : {} palign(8) > MCU1_0_DDR_SPACE
+ .rodata : {} palign(8) > MCU1_0_DDR_SPACE
.cinit : {} palign(8) > MCU1_0_DDR_SPACE
.pinit : {} palign(8) > MCU1_0_DDR_SPACE
.bss : {} align(4) > MCU1_0_DDR_SPACE
diff --git a/packages/ti/drv/ipc/examples/common/j721e/linker_r5f_mcu1_1.lds b/packages/ti/drv/ipc/examples/common/j721e/linker_r5f_mcu1_1.lds
index b6950ec8c57b3f9bf0c11a5b4ef59d0ac972230b..e649784c8607ba90dc88e5ded8dbc9a3df5eb6e6 100644 (file)
.startupData : {} palign(8) > MCU0_R5F_TCMA, type = NOINIT
.text : {} palign(8) > MCU1_1_DDR_SPACE
.const : {} palign(8) > MCU1_1_DDR_SPACE
+ .rodata : {} palign(8) > MCU1_1_DDR_SPACE
.cinit : {} palign(8) > MCU1_1_DDR_SPACE
.pinit : {} palign(8) > MCU1_1_DDR_SPACE
.bss : {} align(4) > MCU1_1_DDR_SPACE
diff --git a/packages/ti/drv/ipc/examples/common/j721e/linker_r5f_mcu1_1_btcm_sysbios.lds b/packages/ti/drv/ipc/examples/common/j721e/linker_r5f_mcu1_1_btcm_sysbios.lds
index 34f100dc293527a9522d896b7b32b92a137fab96..49cb3843c77df987de01681dafcb096dad9337c8 100644 (file)
.startupData : {} palign(8) > MCU1_R5F1_TCMB1, type = NOINIT
.text : {} palign(8) > MCU1_1_DDR_SPACE
.const : {} palign(8) > MCU1_1_DDR_SPACE
+ .rodata : {} palign(8) > MCU1_1_DDR_SPACE
.cinit : {} palign(8) > MCU1_1_DDR_SPACE
.pinit : {} palign(8) > MCU1_1_DDR_SPACE
.bss : {} align(4) > MCU1_1_DDR_SPACE
diff --git a/packages/ti/drv/ipc/examples/common/j721e/linker_r5f_mcu1_1_sysbios.lds b/packages/ti/drv/ipc/examples/common/j721e/linker_r5f_mcu1_1_sysbios.lds
index 5f703f001e0847725ebb34f7db15ce7ca618d7c5..680eb306c92ca60118c9c9945301cc9e36b2fbc3 100644 (file)
.startupData : {} palign(8) > MCU_ATCM, type = NOINIT
.text : {} palign(8) > MCU1_1_DDR_SPACE
.const : {} palign(8) > MCU1_1_DDR_SPACE
+ .rodata : {} palign(8) > MCU1_1_DDR_SPACE
.cinit : {} palign(8) > MCU1_1_DDR_SPACE
.pinit : {} palign(8) > MCU1_1_DDR_SPACE
.bss : {} align(4) > MCU1_1_DDR_SPACE
diff --git a/packages/ti/drv/ipc/examples/common/j721e/linker_r5f_mcu2_0.lds b/packages/ti/drv/ipc/examples/common/j721e/linker_r5f_mcu2_0.lds
index daf31e5ec0f29174fd70a7c729d3d0acb335317c..dec899871dba1507e38bdd7fb9583bc01893be06 100644 (file)
.startupData : {} palign(8) > MCU0_R5F_TCMA, type = NOINIT
.text : {} palign(8) > MCU2_0_DDR_SPACE
.const : {} palign(8) > MCU2_0_DDR_SPACE
+ .rodata : {} palign(8) > MCU2_0_DDR_SPACE
.cinit : {} palign(8) > MCU2_0_DDR_SPACE
.pinit : {} palign(8) > MCU2_0_DDR_SPACE
.bss : {} align(4) > MCU2_0_DDR_SPACE
diff --git a/packages/ti/drv/ipc/examples/common/j721e/linker_r5f_mcu2_0_btcm_sysbios.lds b/packages/ti/drv/ipc/examples/common/j721e/linker_r5f_mcu2_0_btcm_sysbios.lds
index c58d86bc940c120e07447dcacb4119d6a2a62417..2aac8678cb0a3b2677248a1c7147fc5976c09716 100644 (file)
.startupData : {} palign(8) > MCU2_R5F0_TCMB0, type = NOINIT
.text : {} palign(8) > MCU2_0_DDR_SPACE
.const : {} palign(8) > MCU2_0_DDR_SPACE
+ .rodata : {} palign(8) > MCU2_0_DDR_SPACE
.cinit : {} palign(8) > MCU2_0_DDR_SPACE
.pinit : {} palign(8) > MCU2_0_DDR_SPACE
.bss : {} align(4) > MCU2_0_DDR_SPACE
diff --git a/packages/ti/drv/ipc/examples/common/j721e/linker_r5f_mcu2_0_sysbios.lds b/packages/ti/drv/ipc/examples/common/j721e/linker_r5f_mcu2_0_sysbios.lds
index 32581cbe46c6046dd5e78a2d610b8cf45634a053..4111f9ca2131a79d2af81f951deaba9ef5d99e69 100644 (file)
.startupData : {} palign(8) > MCU_ATCM, type = NOINIT
.text : {} palign(8) > MCU2_0_DDR_SPACE
.const : {} palign(8) > MCU2_0_DDR_SPACE
+ .rodata : {} palign(8) > MCU2_0_DDR_SPACE
.cinit : {} palign(8) > MCU2_0_DDR_SPACE
.pinit : {} palign(8) > MCU2_0_DDR_SPACE
.bss : {} align(4) > MCU2_0_DDR_SPACE
diff --git a/packages/ti/drv/ipc/examples/common/j721e/linker_r5f_mcu2_1.lds b/packages/ti/drv/ipc/examples/common/j721e/linker_r5f_mcu2_1.lds
index 823a2ca956553226831f1471050a49d0459f42ef..f7801fa6252562bed16ef9e4786115e502a52856 100644 (file)
.startupData : {} palign(8) > MCU0_R5F_TCMA, type = NOINIT
.text : {} palign(8) > MCU2_1_DDR_SPACE
.const : {} palign(8) > MCU2_1_DDR_SPACE
+ .rodata : {} palign(8) > MCU2_1_DDR_SPACE
.cinit : {} palign(8) > MCU2_1_DDR_SPACE
.pinit : {} palign(8) > MCU2_1_DDR_SPACE
.bss : {} align(4) > MCU2_1_DDR_SPACE
diff --git a/packages/ti/drv/ipc/examples/common/j721e/linker_r5f_mcu2_1_btcm_sysbios.lds b/packages/ti/drv/ipc/examples/common/j721e/linker_r5f_mcu2_1_btcm_sysbios.lds
index 98e7d8c9cedc8bce562e25f3c5f280f566ff4203..8fddf078ad13cb5191db29b2a099df3cacf3a060 100644 (file)
.startupData : {} palign(8) > MCU2_R5F1_TCMB1, type = NOINIT
.text : {} palign(8) > MCU2_1_DDR_SPACE
.const : {} palign(8) > MCU2_1_DDR_SPACE
+ .rodata : {} palign(8) > MCU2_1_DDR_SPACE
.cinit : {} palign(8) > MCU2_1_DDR_SPACE
.pinit : {} palign(8) > MCU2_1_DDR_SPACE
.bss : {} align(4) > MCU2_1_DDR_SPACE
diff --git a/packages/ti/drv/ipc/examples/common/j721e/linker_r5f_mcu2_1_sysbios.lds b/packages/ti/drv/ipc/examples/common/j721e/linker_r5f_mcu2_1_sysbios.lds
index b83f8d8414efe8a308a41cda3d106e1243024f92..444a5075bd2dcc633e56e25f36a50c35a31018eb 100644 (file)
.startupData : {} palign(8) > MCU_ATCM, type = NOINIT
.text : {} palign(8) > MCU2_1_DDR_SPACE
.const : {} palign(8) > MCU2_1_DDR_SPACE
+ .rodata : {} palign(8) > MCU2_1_DDR_SPACE
.cinit : {} palign(8) > MCU2_1_DDR_SPACE
.pinit : {} palign(8) > MCU2_1_DDR_SPACE
.bss : {} align(4) > MCU2_1_DDR_SPACE
diff --git a/packages/ti/drv/ipc/examples/common/j721e/linker_r5f_mcu3_0.lds b/packages/ti/drv/ipc/examples/common/j721e/linker_r5f_mcu3_0.lds
index e2e9507bea35f3fc6eb3a353af7c8d58d619eabc..ddb9bad824718196b62439776ffa57174d7bd079 100644 (file)
.startupData : {} palign(8) > MCU0_R5F_TCMA, type = NOINIT
.text : {} palign(8) > MCU3_0_DDR_SPACE
.const : {} palign(8) > MCU3_0_DDR_SPACE
+ .rodata : {} palign(8) > MCU3_0_DDR_SPACE
.cinit : {} palign(8) > MCU3_0_DDR_SPACE
.pinit : {} palign(8) > MCU3_0_DDR_SPACE
.bss : {} align(4) > MCU3_0_DDR_SPACE
diff --git a/packages/ti/drv/ipc/examples/common/j721e/linker_r5f_mcu3_0_btcm_sysbios.lds b/packages/ti/drv/ipc/examples/common/j721e/linker_r5f_mcu3_0_btcm_sysbios.lds
index 565afbd3376bb368a6fcea030ccc89bebd38e816..f4354670eb01186702896e9a57b5ff4219aa385f 100644 (file)
.startupData : {} palign(8) > MCU3_R5F0_TCMB0, type = NOINIT
.text : {} palign(8) > MCU3_0_DDR_SPACE
.const : {} palign(8) > MCU3_0_DDR_SPACE
+ .rodata : {} palign(8) > MCU3_0_DDR_SPACE
.cinit : {} palign(8) > MCU3_0_DDR_SPACE
.pinit : {} palign(8) > MCU3_0_DDR_SPACE
.bss : {} align(4) > MCU3_0_DDR_SPACE
diff --git a/packages/ti/drv/ipc/examples/common/j721e/linker_r5f_mcu3_0_sysbios.lds b/packages/ti/drv/ipc/examples/common/j721e/linker_r5f_mcu3_0_sysbios.lds
index 5575ebf91d3c56c3d48d257502339dd90533bd1f..a477512b6bc898d766a6b8ebb12fcc5258f31d34 100644 (file)
.startupData : {} palign(8) > MCU_ATCM, type = NOINIT
.text : {} palign(8) > MCU3_0_DDR_SPACE
.const : {} palign(8) > MCU3_0_DDR_SPACE
+ .rodata : {} palign(8) > MCU3_0_DDR_SPACE
.cinit : {} palign(8) > MCU3_0_DDR_SPACE
.pinit : {} palign(8) > MCU3_0_DDR_SPACE
.bss : {} align(4) > MCU3_0_DDR_SPACE
diff --git a/packages/ti/drv/ipc/examples/common/j721e/linker_r5f_mcu3_1.lds b/packages/ti/drv/ipc/examples/common/j721e/linker_r5f_mcu3_1.lds
index cb7f980d37ac6c11487687eb9a950a383929104c..cb52bc53bea1dbce98d660593d178e1c156259c2 100644 (file)
.startupData : {} palign(8) > MCU0_R5F_TCMA, type = NOINIT
.text : {} palign(8) > MCU3_1_DDR_SPACE
.const : {} palign(8) > MCU3_1_DDR_SPACE
+ .rodata : {} palign(8) > MCU3_1_DDR_SPACE
.cinit : {} palign(8) > MCU3_1_DDR_SPACE
.pinit : {} palign(8) > MCU3_1_DDR_SPACE
.bss : {} align(4) > MCU3_1_DDR_SPACE
diff --git a/packages/ti/drv/ipc/examples/common/j721e/linker_r5f_mcu3_1_btcm_sysbios.lds b/packages/ti/drv/ipc/examples/common/j721e/linker_r5f_mcu3_1_btcm_sysbios.lds
index 15cbb633ce1e0b193c3b38a6aba9fda5151e552c..941964f362f7dcd8e7ada6258cca5e1baa1ea137 100644 (file)
.startupData : {} palign(8) > MCU3_R5F1_TCMB1, type = NOINIT
.text : {} palign(8) > MCU3_1_DDR_SPACE
.const : {} palign(8) > MCU3_1_DDR_SPACE
+ .rodata : {} palign(8) > MCU3_1_DDR_SPACE
.cinit : {} palign(8) > MCU3_1_DDR_SPACE
.pinit : {} palign(8) > MCU3_1_DDR_SPACE
.bss : {} align(4) > MCU3_1_DDR_SPACE
diff --git a/packages/ti/drv/ipc/examples/common/j721e/linker_r5f_mcu3_1_sysbios.lds b/packages/ti/drv/ipc/examples/common/j721e/linker_r5f_mcu3_1_sysbios.lds
index df2b194ff1ae8e194a80ee00742ce0f28e0f6273..735407f60d0e14773759053c9c53a1a93887e41c 100644 (file)
.startupData : {} palign(8) > MCU_ATCM, type = NOINIT
.text : {} palign(8) > MCU3_1_DDR_SPACE
.const : {} palign(8) > MCU3_1_DDR_SPACE
+ .rodata : {} palign(8) > MCU3_1_DDR_SPACE
.cinit : {} palign(8) > MCU3_1_DDR_SPACE
.pinit : {} palign(8) > MCU3_1_DDR_SPACE
.bss : {} align(4) > MCU3_1_DDR_SPACE
diff --git a/packages/ti/drv/ipc/examples/common/src/ipc_rsctable.h b/packages/ti/drv/ipc/examples/common/src/ipc_rsctable.h
index 186c5248689b39b1c991057c567cadd5161465c1..8222ba01652e9247abfd3ffb8e41245324dfed26 100644 (file)
const Ipc_ResourceTable ti_ipc_remoteproc_ResourceTable __attribute__ ((section (".resource_table"), aligned (4096))) =
{
- 1U, /* we're the first version that implements this */
- NUM_ENTRIES, /* number of entries in the table */
- 0U, 0U, /* reserved, must be zero */
+ {
+ 1U, /* we're the first version that implements this */
+ NUM_ENTRIES, /* number of entries in the table */
+ {
+ 0U,
+ 0U, /* reserved, must be zero */
+ }
+ },
/* offsets to entries */
{
diff --git a/packages/ti/drv/ipc/examples/common/src/ipc_trace.c b/packages/ti/drv/ipc/examples/common/src/ipc_trace.c
index b2dcd1b5ac67e7d429fa0b79f37d51ae3e1c468b..0625be2fd2f06314bcf836568f9abbd9ec87c718 100644 (file)
#include "ipc_trace.h"
#if defined(BUILD_MCU)
-#pragma DATA_SECTION(Ipc_traceBuffer, ".tracebuf");
-#endif
+char Ipc_traceBuffer[IPC_TRACE_BUFFER_MAX_SIZE] __attribute__((section(".tracebuf")));
+static __attribute__((section(".tracebuf"))) uint32_t gTraceBufIndex = 0U;
+#else
char Ipc_traceBuffer[IPC_TRACE_BUFFER_MAX_SIZE];
-
static uint32_t gTraceBufIndex = 0U;
+#endif
+
int32_t Ipc_Trace_printf(const char *format, ...)
{
diff --git a/packages/ti/drv/ipc/examples/common/src/main_rtos.c b/packages/ti/drv/ipc/examples/common/src/main_rtos.c
index 9da9c9272416fc6503109ce9cccbf364f95ff715..056ef9693d7f54b750fe20d021e939aef49d349d 100644 (file)
#include <stdio.h>
#include <stdint.h>
+#include <string.h>
#include <ti/drv/ipc/examples/common/src/ipc_setup.h>
diff --git a/packages/ti/drv/sciclient/soc/sysfw/include/tisci/security/tisci_keywriter.h b/packages/ti/drv/sciclient/soc/sysfw/include/tisci/security/tisci_keywriter.h
index fb60794e7f138a2441d921e813f6b21e30cb04bc..558b86c244ab3f63d3e03d61f3ab223915de44fc 100644 (file)
* Copyright (C) 2019-2021 Texas Instruments Incorporated - http://www.ti.com/
*/
#ifndef KEYWRITER_H
-#define KEYWRTIER_H
+#define KEYWRITER_H
/**
*
index 130140c892cc5e7a5589739c11659014943709c4..e3920dc84c1c7ddfd37754fd5b3f532825ec2f82 100755 (executable)
interruptRegParams.corepacConfig.arg=(uintptr_t)handle;
interruptRegParams.corepacConfig.name=NULL;
interruptRegParams.corepacConfig.isrRoutine=UART_v1_hwiIntFxn;
-#ifdef __TI_ARM_V7R4__
+#if (__ARM_ARCH == 7) && (__ARM_ARCH_PROFILE == 'R') /* R5F */
interruptRegParams.corepacConfig.priority=0x8U;
#else
#ifdef __C7100__
diff --git a/packages/ti/kernel/freertos/portable/TI_CGT/r5f/portmacro.h b/packages/ti/kernel/freertos/portable/TI_CGT/r5f/portmacro.h
index 04440b88ec39ec260c2629eaf46f84199757c755..80c748f802bde5575a69c03f3d2a873241c1ad11 100644 (file)
#endif
#include <ti/osal/HwiP.h>
+#include <arm_acle.h>
/*-----------------------------------------------------------
* Port specific definitions.
index 57efcbdbf3a5d1f85131cc8bef26d76763ac1d16..797bcf06e1bba218180e75c8f1c9d5e63770bd56 100644 (file)
--- a/packages/ti/osal/HwiP.h
+++ b/packages/ti/osal/HwiP.h
uint32_t enableIntr; /*!< When set to TRUE, interrupt is enabled after the create
otherwise interrupt is disabled after HwiP_Create */
uint32_t evtId; /*!< Event Id associated */
-#if defined (__ARM_ARCH_7A__) || defined(__aarch64__) || defined (__TI_ARM_V7R4__)
+#if defined (__ARM_ARCH_7A__) || defined(__aarch64__) || ((__ARM_ARCH == 7) && (__ARM_ARCH_PROFILE == 'R'))
uint32_t triggerSensitivity; /*!< Set an interrupt's trigger sensitivity for
ARM cortex-A Generic Interrupt Controller(GIC)
v2.0 specific implementations as @ref OSAL_armGicTrigType_t
index f3b85d932f3412c1114e1a9653eb8e0e41adb1a9..ad29760e215381fbf378585f1ec08a711990a551 100644 (file)
#pragma GCC diagnostic ignored "-Wunused-variable"
#else
/* TI compiler */
-#pragma diag_suppress 179
+#pragma clang diagnostic warning "-Wunused"
#endif
OSAL_COMPILE_TIME_SIZE_CHECK (sizeof(HwiP_nonOs),OSAL_NONOS_HWIP_SIZE_BYTES);
#if defined(__GNUC__) && !defined(__ti__)
index 018ee1196ec06209a5c818d4f883872334a6f52a..e99e722d2ada8ec3b46301f8bb7a33f125852947 100755 (executable)
#pragma GCC diagnostic ignored "-Wunused-variable"
#else
/* TI compiler */
-#pragma diag_suppress 179
+#pragma clang diagnostic warning "-Wunused"
#endif
OSAL_COMPILE_TIME_SIZE_CHECK ((uint32_t)sizeof(HwiP_nonOs),OSAL_NONOS_HWIP_SIZE_BYTES);
#if defined(__GNUC__) && !defined(__ti__)
static bool gHwiInitialized = (bool)false;
static CSL_vimRegs *gVimRegs;
-static TimeStamp_Struct gTimeStamp = {NULL,NULL};
+static TimeStamp_Struct gTimeStamp = {(uint32_t)NULL,(uint32_t)NULL};
static HwiP_Handle gHwiPHandle;
/* This function enables the interrupt for a given interrupt number */
diff --git a/packages/ti/osal/soc/am65xx/TimerP_default.c b/packages/ti/osal/soc/am65xx/TimerP_default.c
index 8f791d1a2f14c2686122143a26feae381cb58599..cced2fa0c356ebe8a4611b6cd44b71f7be3747d5 100644 (file)
#include <ti/osal/src/nonos/Nonos_config.h>
/* This information is derived from sysbios timer implmentation for multiple SoCs */
-#if defined (__TI_ARM_V7R4__)
+#if (__ARM_ARCH == 7) && (__ARM_ARCH_PROFILE == 'R')
TimerP_dmTimerDefault gDmTimerPInfoTbl[TimerP_numTimerDevices] = {
/* Timer ID 0 */
{
index 305214e88a5b9d23230a50c023d94236437c530b..4d6ef74c8f0d70d5a1fe4b5ba1d61e641f4fa652 100755 (executable)
#define TIMERP_TIMER_FREQ_LO ((int32_t) 25000000)
#define TIMERP_TIMER_FREQ_HI ((int32_t) 0)
-#if defined (__TI_ARM_V7R4__)
+#if (__ARM_ARCH == 7) && (__ARM_ARCH_PROFILE == 'R')
#define TimerP_numTimerDevices ((uint32_t) 4 )
#define TIMERP_ANY_MASK ((uint32_t) 0x000F)
#define TIMERP_AVAILABLE_MASK ((uint32_t)(0x000F))
diff --git a/packages/ti/osal/src/freertos/MemoryP_freertos.c b/packages/ti/osal/src/freertos/MemoryP_freertos.c
index 6e53f98724e5c4c6e544f4be7343e00166654464..5983ed4ffd8e43a60ed09750bd1c837c3ea9ec68 100644 (file)
}\r
}\r
memoryTrackAddress = (MemoryTrack_t *)((uintptr_t)allocAddress - sizeof(MemoryTrack_t));\r
- DebugP_assert(memoryTrackAddress >= origAllocAddress);\r
+ DebugP_assert((void *)memoryTrackAddress >= origAllocAddress);\r
memoryTrackAddress->allocKey = 0xDEADBEEF;\r
memoryTrackAddress->origAllocAddress = origAllocAddress;\r
memoryTrackAddress->origAllocSize = size + alignment + sizeof(MemoryTrack_t);\r
diff --git a/packages/ti/osal/src/freertos/SemaphoreP_freertos.c b/packages/ti/osal/src/freertos/SemaphoreP_freertos.c
index 843607ba47638be760919344720f188f0b036dd7..d1f5d65fe7513afffdabc11b5729c365d6cbb972 100644 (file)
#pragma GCC diagnostic ignored "-Wunused-variable"
#else
/* TI compiler */
-#pragma diag_suppress 179
+#pragma clang diagnostic warning "-Wunused"
#endif
OSAL_COMPILE_TIME_SIZE_CHECK ((uint32_t)sizeof(SemaphoreP_freertos),OSAL_FREERTOS_SEMAPHOREP_SIZE_BYTES);
#if defined(__GNUC__) && !defined(__ti__)
diff --git a/packages/ti/osal/src/freertos/TaskP_freertos.c b/packages/ti/osal/src/freertos/TaskP_freertos.c
index 1af9b93bd0fe1ddd897207cf30518b7a7b0672c0..4a0bdcfb93fe5d14b5af3dcb5527a805daa07c03 100644 (file)
#pragma GCC diagnostic ignored "-Wunused-variable"
#else
/* TI compiler */
-#pragma diag_suppress 179
+#pragma clang diagnostic warning "-Wunused"
#endif
OSAL_COMPILE_TIME_SIZE_CHECK ((uint32_t)sizeof(TaskP_freertos),OSAL_FREERTOS_TASKP_SIZE_BYTES);
#if defined(__GNUC__) && !defined(__ti__)
index 1ad024a088e7f21323d71b47eb9e9917995a37ff..4d8a07bd42e7912176c6b3997b9c5d2eb4d45399 100644 (file)
params->priority = HWIP_USE_DEFAULT_PRIORITY;
params->evtId = 0;
params->enableIntr = TRUE;
-#if defined (__ARM_ARCH_7A__) || defined(__aarch64__) || defined (__TI_ARM_V7R4__)
+#if defined (__ARM_ARCH_7A__) || defined(__aarch64__) || ((__ARM_ARCH == 7) && (__ARM_ARCH_PROFILE == 'R'))
params->triggerSensitivity = (uint32_t)OSAL_ARM_GIC_TRIG_TYPE_LEVEL;
-#if !defined (SOC_AM437x) && !defined(SOC_AM335x) && !defined (__TI_ARM_V7R4__)
+#if !defined (SOC_AM437x) && !defined(SOC_AM335x) && !((__ARM_ARCH == 7) && (__ARM_ARCH_PROFILE == 'R'))
{
Osal_HwAttrs hwAttrs;
(void)Osal_getHwAttrs(&hwAttrs);
index 036d554bc49946a76d2441f95e959750e4fac32a..bb6e818b02e76d9fa47d05b51494f58072b847a2 100644 (file)
uint32_t intNum;
CSL_ArmGicIntrParams_t gicParams;
} Hwi_Struct;
-#elif defined (__TI_ARM_V7R4__)
+#elif (__ARM_ARCH == 7) && (__ARM_ARCH_PROFILE == 'R')
#include <ti/csl/arch/csl_arch.h>
typedef struct hwi_struct {
uint32_t intNum;
} Hwi_Struct;
-#elif defined (__TI_ARM_V7M4__) || defined(__TI_ARM_V5__)
+#elif (__ARM_ARCH == 7) && (__ARM_ARCH_PROFILE == 'M') && defined(__ARM_FEATURE_SIMD32)
#include <ti/csl/arch/csl_arch.h>
#include <ti/csl/soc.h>
#if defined(__TI_ARM_V7M4__) && !defined(BUILD_M4F)
diff --git a/packages/ti/osal/src/nonos/RegisterIntr_nonos.c b/packages/ti/osal/src/nonos/RegisterIntr_nonos.c
index 0c93bde065efe9706e41f3e9d85e2a8c3672492a..cebd9df48bae2061357538f03a5db44605eb6b8c 100644 (file)
interruptRegParams->corepacConfig.triggerSensitivity = 0x3; /* interrupt edge triggered */
#endif
-#if defined(__aarch64__) || defined (__TI_ARM_V7R4__)
+#if defined(__aarch64__) || ((__ARM_ARCH == 7) && (__ARM_ARCH_PROFILE == 'R') )
interruptRegParams->corepacConfig.triggerSensitivity = (uint32_t)OSAL_ARM_GIC_TRIG_TYPE_LEVEL; /* interrupt level triggered */
#endif
/* SOC Mux Config */
@@ -104,7 +104,7 @@ OsalInterruptRetCode_e Osal_RegisterInterrupt(OsalRegisterIntrParams_t *interrup
hwiInputParams.priority = interruptRegParams->corepacConfig.priority;
hwiInputParams.evtId = (uint32_t)interruptRegParams->corepacConfig.corepacEventNum;
hwiInputParams.enableIntr = interruptRegParams->corepacConfig.enableIntr;
-#if defined (__ARM_ARCH_7A__) || defined (__aarch64__) || defined (__TI_ARM_V7R4__)
+#if defined (__ARM_ARCH_7A__) || defined (__aarch64__) || ((__ARM_ARCH == 7) && (__ARM_ARCH_PROFILE == 'R') )
hwiInputParams.triggerSensitivity = interruptRegParams->corepacConfig.triggerSensitivity;
#endif
@@ -219,7 +219,7 @@ OsalInterruptRetCode_e Osal_RegisterInterruptDirect(OsalRegisterIntrParams_t *in
hwiInputParams.priority = interruptRegParams->corepacConfig.priority;
hwiInputParams.evtId = (uint32_t)interruptRegParams->corepacConfig.corepacEventNum;
hwiInputParams.enableIntr = interruptRegParams->corepacConfig.enableIntr;
-#if defined (__ARM_ARCH_7A__) || defined (__aarch64__) || defined (__TI_ARM_V7R4__)
+#if defined (__ARM_ARCH_7A__) || defined (__aarch64__) || ((__ARM_ARCH == 7) && (__ARM_ARCH_PROFILE == 'R') )
hwiInputParams.triggerSensitivity = interruptRegParams->corepacConfig.triggerSensitivity;
#endif
diff --git a/packages/ti/osal/src/nonos/SemaphoreP_nonos.c b/packages/ti/osal/src/nonos/SemaphoreP_nonos.c
index 08eee3b76b415de20676e1f071dadacdd55e8fe9..a1da745d96798f3e91bb1340872235ef41d6ee0b 100644 (file)
#pragma GCC diagnostic ignored "-Wunused-variable"
#else
/* TI compiler */
-#pragma diag_suppress 179
+#pragma clang diagnostic warning "-Wunused"
#endif
OSAL_COMPILE_TIME_SIZE_CHECK ((uint32_t)sizeof(Sem_Struct),OSAL_NONOS_SEMAPHOREP_SIZE_BYTES);
#if defined(__GNUC__) && !defined(__ti__)
diff --git a/packages/ti/osal/src/nonos/timer/v1/TimerP_nonos.c b/packages/ti/osal/src/nonos/timer/v1/TimerP_nonos.c
index 55f5681b80b57c5ea071920087ad43fffcead64b..5bcc6675ef39d9e6cd2635c339b22da0842df981 100755 (executable)
@@ -583,7 +583,7 @@ static TimerP_Status TimerP_dmTimerInstanceInit(TimerP_Struct *timer, uint32_t i
interruptRegParams.corepacConfig.name=(char *) NULL_PTR;
interruptRegParams.corepacConfig.isrRoutine=TimerP_dmTimerStub;
-#if defined (__ARM_ARCH_7A__) || defined (__aarch64__) || defined (__TI_ARM_V7R4__)
+#if defined (__ARM_ARCH_7A__) || defined (__aarch64__) || ((__ARM_ARCH == 7) && (__ARM_ARCH_PROFILE == 'R') )
#if defined(SOC_AM335x) || defined(SOC_AM437x) || defined(SOC_AM65XX) || defined(SOC_J721E) || defined(SOC_J7200) || defined(SOC_AM64X) || defined(SOC_J721S2)
interruptRegParams.corepacConfig.triggerSensitivity = (uint32_t)OSAL_ARM_GIC_TRIG_TYPE_HIGH_LEVEL;
interruptRegParams.corepacConfig.priority = 0x20U;
diff --git a/packages/ti/osal/src/nonos/timer/v2/TimerP_nonos.c b/packages/ti/osal/src/nonos/timer/v2/TimerP_nonos.c
index 9057462167b59e1169dd14ca532953fe297338f9..cc199e19e270bb1f3fa14f2d3462086eb0d84215 100644 (file)
interruptRegParams.corepacConfig.name=(char *) NULL_PTR;
interruptRegParams.corepacConfig.isrRoutine=TimerP_rtiTimerStub;
-#if defined (__ARM_ARCH_7A__) || defined (__aarch64__) || defined (__TI_ARM_V7R4__)
+#if defined (__ARM_ARCH_7A__) || defined (__aarch64__) || ((__ARM_ARCH == 7) && (__ARM_ARCH_PROFILE == 'R') )
#if defined(SOC_AM335x) || defined(SOC_AM437x) || defined(SOC_AM65XX) || defined(SOC_J721E) || defined(SOC_J7200) || defined(SOC_J721S2)
interruptRegParams.corepacConfig.triggerSensitivity = (uint32_t)OSAL_ARM_GIC_TRIG_TYPE_HIGH_LEVEL;
interruptRegParams.corepacConfig.priority = 0x20U;
diff --git a/packages/ti/osal/src/safertos/SemaphoreP_SafeRTOS.c b/packages/ti/osal/src/safertos/SemaphoreP_SafeRTOS.c
index e4b2f0523fef5a92addbc3673d333a881cdbf706..a0239e3ea7850cf8d0033c7d5d50940c3840b75f 100644 (file)
#pragma GCC diagnostic ignored "-Wunused-variable"
#else
/* TI compiler */
-#pragma diag_suppress 179
+#pragma clang diagnostic warning "-Wunused"
#endif
OSAL_COMPILE_TIME_SIZE_CHECK ( ( uint32_t )sizeof( SemaphoreP_safertos ),OSAL_SAFERTOS_SEMAPHOREP_SIZE_BYTES );
#if defined( __GNUC__ ) && !defined( __ti__ )
diff --git a/packages/ti/osal/src/safertos/TaskP_SafeRTOS.c b/packages/ti/osal/src/safertos/TaskP_SafeRTOS.c
index a1932f72685fd572fbb83d7adac9e0a71d1e6c70..611af4a1a8e5c0748c9bbcf22e72b8b7ee1681f3 100644 (file)
#pragma GCC diagnostic ignored "-Wunused-variable"
#else
/* TI compiler */
-#pragma diag_suppress 179
+#pragma clang diagnostic warning "-Wunused"
#endif
OSAL_COMPILE_TIME_SIZE_CHECK ( ( uint32_t )sizeof( TaskP_SafeRTOS ),OSAL_SAFERTOS_TASKP_SIZE_BYTES );
#if defined( __GNUC__ ) && !defined( __ti__ )
diff --git a/packages/ti/osal/src/tirtos/CacheP_tirtos.c b/packages/ti/osal/src/tirtos/CacheP_tirtos.c
index fdd38c4f57ef4e689fd2aa4b2eb98557992f4611..eca6a8f0c9e044e08abb090ba21f38698e4c7f08 100644 (file)
#include <ti/sysbios/BIOS.h>
#if defined (_TMS320C6X) && !(defined (SOC_OMAPL137) || defined (SOC_OMAPL138))
#include <ti/sysbios/family/c66/Cache.h>
-#elif defined (__TI_ARM_V7M4__)
+#elif (__ARM_ARCH == 7) && (__ARM_ARCH_PROFILE == 'M') && defined(__ARM_FEATURE_SIMD32)
#include <ti/sysbios/hal/unicache/Cache.h>
#else
#include <ti/sysbios/hal/Cache.h>
diff --git a/packages/ti/osal/src/tirtos/CycleprofilerP_tirtos.c b/packages/ti/osal/src/tirtos/CycleprofilerP_tirtos.c
index 485996ca4158254416225bde0181489fbcfe63c0..cce7bb7cd2a51baa5d6303aacd433f0d162cba1e 100644 (file)
}
#endif
-#if defined(__ARM_ARCH_7A__) || defined(__TI_ARM_V7R4__)
+#if defined(__ARM_ARCH_7A__) || ((__ARM_ARCH == 7) && (__ARM_ARCH_PROFILE == 'R') )
#include <ti/sysbios/family/arm/v7a/Pmu.h>
void CycleprofilerP_init(void)
{
index 1b6aa58e0bf150c2d2c64714ac1408170ba075ab..ee2c7c7cc33eacab68de6855c5eee066e3de3dcd 100644 (file)
#else
#ifdef _TMS320C6X
#include <ti/sysbios/family/c64p/Hwi.h>
-#elif defined(__TI_ARM_V7R4__)
+#elif (__ARM_ARCH == 7) && (__ARM_ARCH_PROFILE == 'R')
#include <ti/sysbios/family/arm/v7r/keystone3/Hwi.h>
#else
#include <ti/sysbios/hal/Hwi.h>
#pragma GCC diagnostic ignored "-Wunused-variable"
#else
/* TI compiler */
-#pragma diag_suppress 179
+#pragma clang diagnostic warning "-Wunused"
#endif
OSAL_COMPILE_TIME_SIZE_CHECK ((uint32_t)sizeof(HwiP_tiRtos),OSAL_TIRTOS_HWIP_SIZE_BYTES);
#if defined(__GNUC__) && !defined(__ti__)
}
#endif
#endif
-#if defined (__TI_ARM_V7R4__)
+#if (__ARM_ARCH == 7) && (__ARM_ARCH_PROFILE == 'R')
/* Set the trigger type */
if ((params->triggerSensitivity == (uint32_t)OSAL_ARM_GIC_TRIG_TYPE_HIGH_LEVEL) ||
(params->triggerSensitivity == (uint32_t)OSAL_ARM_GIC_TRIG_TYPE_LEVEL) ||
params->priority = HWIP_USE_DEFAULT_PRIORITY;
params->evtId = 0;
params->enableIntr = TRUE;
-#if defined (__ARM_ARCH_7A__) || defined(__aarch64__) || defined (__TI_ARM_V7R4__) || defined(gnu_targets_arm_A15F) || defined(gnu_targets_arm_A9F)
+#if defined (__ARM_ARCH_7A__) || defined(__aarch64__) || ((__ARM_ARCH == 7) && (__ARM_ARCH_PROFILE == 'R') ) || defined(gnu_targets_arm_A15F) || defined(gnu_targets_arm_A9F)
params->triggerSensitivity = (uint32_t)OSAL_ARM_GIC_TRIG_TYPE_LEVEL;
#endif
diff --git a/packages/ti/osal/src/tirtos/RegisterIntr_tirtos.c b/packages/ti/osal/src/tirtos/RegisterIntr_tirtos.c
index b650c730fe1b012a80dff29ecb9b68e23bb31edd..4d2f6d83175c7a3a38abdb0a5f697fb1ca777aeb 100644 (file)
interruptRegParams->corepacConfig.arg=(uintptr_t)NULL_PTR;
interruptRegParams->corepacConfig.enableIntr=TRUE;
-#ifdef __TI_ARM_V7R4__
+#if (__ARM_ARCH == 7) && (__ARM_ARCH_PROFILE == 'R')
interruptRegParams->corepacConfig.priority=0x15U; /* Default */
#else
#if defined(__C7100__) || defined(BUILD_DSP_1) || defined(BUILD_DSP_2)
@@ -103,7 +103,7 @@ void Osal_RegisterInterrupt_initParams(OsalRegisterIntrParams_t *interruptRegPar
interruptRegParams->corepacConfig.triggerSensitivity = 0x3; /* interrupt edge triggered */
#endif
-#if defined(__aarch64__) || defined (__TI_ARM_V7R4__)
+#if defined(__aarch64__) || ((__ARM_ARCH == 7) && (__ARM_ARCH_PROFILE == 'R') )
interruptRegParams->corepacConfig.triggerSensitivity = (uint32_t)OSAL_ARM_GIC_TRIG_TYPE_LEVEL; /* interrupt level triggered */
#endif
@@ -140,7 +140,7 @@ OsalInterruptRetCode_e Osal_RegisterInterrupt(OsalRegisterIntrParams_t *interrup
hwiInputParams.evtId = (uint32_t)interruptRegParams->corepacConfig.corepacEventNum;
hwiInputParams.enableIntr = interruptRegParams->corepacConfig.enableIntr;
-#if defined (__ARM_ARCH_7A__) || defined(__aarch64__) || defined (__TI_ARM_V7R4__)
+#if defined (__ARM_ARCH_7A__) || defined(__aarch64__) || ((__ARM_ARCH == 7) && (__ARM_ARCH_PROFILE == 'R') )
hwiInputParams.triggerSensitivity = interruptRegParams->corepacConfig.triggerSensitivity;
#endif
diff --git a/packages/ti/osal/src/tirtos/SemaphoreP_tirtos.c b/packages/ti/osal/src/tirtos/SemaphoreP_tirtos.c
index d9f651088e84d8a92a86eca24494b378fddeef2c..7b41d8286e3d18f9505e810cda517431209357e6 100644 (file)
#pragma GCC diagnostic ignored "-Wunused-variable"
#else
/* TI compiler */
-#pragma diag_suppress 179
+#pragma clang diagnostic warning "-Wunused"
#endif
OSAL_COMPILE_TIME_SIZE_CHECK ((uint32_t)sizeof(SemaphoreP_tiRtos),OSAL_TIRTOS_SEMAPHOREP_SIZE_BYTES);
#if defined(__GNUC__) && !defined(__ti__)
diff --git a/packages/ti/osal/src/tirtos/tirtos_config.h b/packages/ti/osal/src/tirtos/tirtos_config.h
index 2c08e678e3a0eaa8151b97693c6e19c0f43a172c..abf5ee2d0774433efa2524214f68224ce28aa95a 100644 (file)
#else
#ifdef _TMS320C6X
#include <ti/sysbios/family/c64p/Hwi.h>
-#elif defined(__TI_ARM_V7R4__)
+#elif (__ARM_ARCH == 7) && (__ARM_ARCH_PROFILE == 'R')
#include <ti/sysbios/family/arm/v7r/keystone3/Hwi.h>
#else
#include <ti/sysbios/hal/Hwi.h>
diff --git a/packages/ti/osal/test/src/main_osal_test.c b/packages/ti/osal/test/src/main_osal_test.c
index 123bd79b5e2c6d22fdaa7148e1b0f9edc314b8f9..953b768014e27251ec5e896fba903dd2911bdb42 100644 (file)
#elif defined(SOC_AM65XX)
UT_Timer_Type_t timer_type = UT_Timer_DMTIMER;
- #if defined (__TI_ARM_V7R4__)
+ #if (__ARM_ARCH == 7) && (__ARM_ARCH_PROFILE == 'R')
#define OSAL_TEST_TIMER_ID (1U)
#define OSAL_TEST_TIMER_ID2 (2U)
#define OSAL_TEST_TIMER_PERIOD (5000U)
#define OSAL_TEST_TIMER_ID (2U)
#define OSAL_TEST_TIMER_ID2 (3U)
#define OSAL_TEST_TIMER_PERIOD (5000U)
- #elif defined (__TI_ARM_V7R4__)
+ #elif (__ARM_ARCH == 7) && (__ARM_ARCH_PROFILE == 'R')
#define OSAL_TEST_TIMER_ID (1U)
#define OSAL_TEST_TIMER_ID2 (2U)
#define OSAL_TEST_TIMER_PERIOD (5000U)
#define OSAL_TEST_TIMER_ID (2U)
#define OSAL_TEST_TIMER_ID2 (3U)
#define OSAL_TEST_TIMER_PERIOD (5000U)
- #elif defined (__TI_ARM_V7R4__)
+ #elif (__ARM_ARCH == 7) && (__ARM_ARCH_PROFILE == 'R')
#define OSAL_TEST_TIMER_ID (1U)
#define OSAL_TEST_TIMER_ID2 (2U)
#define OSAL_TEST_TIMER_PERIOD (5000U)