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raw | patch | inline | side by side (parent: 8fd8c0b)
raw | patch | inline | side by side (parent: 8fd8c0b)
author | Lohith Kumar <l-kumar@ti.com> | |
Sat, 28 Jan 2023 11:56:09 +0000 (17:26 +0530) | ||
committer | Rishabh Garg <rishabh@ti.com> | |
Mon, 30 Jan 2023 15:39:52 +0000 (09:39 -0600) |
Configure Phy to operate on master mode or bypass mode basing on
input provided by user. By default the operating mode of PHY will
be programmed basing on OSPI clk.
User can override phyOpMode parameter in OSPI_Params to choose
the operating mode of PHY.
Fixes: PDK-12406
Signed-off-by: Lohith Kumar <l-kumar@ti.com>
input provided by user. By default the operating mode of PHY will
be programmed basing on OSPI clk.
User can override phyOpMode parameter in OSPI_Params to choose
the operating mode of PHY.
Fixes: PDK-12406
Signed-off-by: Lohith Kumar <l-kumar@ti.com>
index 0160435210704f4a8f63a83d620e2897d2af4d2b..feb7aa2e0cba8b486651bc0f2b50fd6d6e05c02a 100755 (executable)
#else
(uintptr_t)CSL_MCU_FSS0_DAT_REG1_BASE,
#endif
+ CSL_OSPI_CFG_PHY_OP_MODE_DEFAULT, /* PHY operating mode */
OSPI_MODULE_CLOCK, /* Input frequency */
#if defined(BUILD_MPU)
CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_MCU_FSS0_OSPI_0_OSPI_LVL_INTR_0,
#else
(uintptr_t)(CSL_MCU_FSS0_DAT_REG1_BASE + 0x08000000U),
#endif
+ CSL_OSPI_CFG_PHY_OP_MODE_DEFAULT, /* PHY operating mode */
OSPI_MODULE_CLOCK,
#if defined(BUILD_MPU)
CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_MCU_FSS0_OSPI_1_OSPI_LVL_INTR_0,
index ad67d8ccc2a3548358b9fa855e83b5b27345b787..873baa5b3a2b3b38302b06f2cadec54604f3e013 100755 (executable)
#else
(uintptr_t)CSL_MCU_FSS0_DAT_REG1_BASE,
#endif
+ CSL_OSPI_CFG_PHY_OP_MODE_DEFAULT, /* PHY operating mode */
OSPI_MODULE_CLOCK, /* Input frequency */
#if defined(BUILD_MPU)
CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_MCU_FSS0_OSPI_0_OSPI_LVL_INTR_0,
#else
(uintptr_t)(CSL_MCU_FSS0_DAT_REG1_BASE + 0x08000000U),
#endif
+ CSL_OSPI_CFG_PHY_OP_MODE_DEFAULT, /* PHY operating mode */
OSPI_MODULE_CLOCK,
#if defined(BUILD_MPU)
CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_MCU_FSS0_OSPI_1_OSPI_LVL_INTR_0,
index 2dd0be85d7bb57b5892c7b1451bfaf8551917780..a80e9de63ccdb4ae1e2198279a63b545d8f5649d 100644 (file)
#else
(uintptr_t)CSL_MCU_FSS0_DAT_REG1_BASE,
#endif
+ CSL_OSPI_CFG_PHY_OP_MODE_DEFAULT, /* PHY operating mode */
OSPI_MODULE_CLOCK, /* Input frequency */
#if defined(BUILD_MPU)
CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_MCU_FSS0_OSPI_0_OSPI_LVL_INTR_0,
#else
(uintptr_t)(CSL_MCU_FSS0_DAT_REG1_BASE + 0x08000000U),
#endif
+ CSL_OSPI_CFG_PHY_OP_MODE_DEFAULT, /* PHY operating mode */
OSPI_MODULE_CLOCK,
#if defined(BUILD_MPU)
CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_MCU_FSS0_OSPI_1_OSPI_LVL_INTR_0,
index d213ab1fbfc98710324340d8987c8e909837c53c..ba4d68f547accb934cacf985dfe51b82476780ea 100644 (file)
#else
(uintptr_t)CSL_MCU_FSS0_DAT_REG1_BASE,
#endif
+ CSL_OSPI_CFG_PHY_OP_MODE_DEFAULT, /* PHY operating mode */
OSPI_MODULE_CLOCK, /* Input frequency */
#if defined(BUILD_MPU)
CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_MCU_FSS0_OSPI_0_OSPI_LVL_INTR_0,
#else
(uintptr_t)(CSL_MCU_FSS0_DAT_REG1_BASE + 0x08000000U),
#endif
+ CSL_OSPI_CFG_PHY_OP_MODE_DEFAULT, /* PHY operating mode */
OSPI_MODULE_CLOCK,
#if defined(BUILD_MPU)
CSLR_COMPUTE_CLUSTER0_GIC500SS_SPI_MCU_FSS0_OSPI_1_OSPI_LVL_INTR_0,
index a095be63aa71d1836cafcfdb6c83ca7b66dabef6..b12874506bcb361eb28c1d2c6b437b21e5e85d79 100755 (executable)
@@ -1677,6 +1677,7 @@ static int32_t OSPI_control_v0(OSPI_Handle handle, uint32_t cmd, const void *arg
{
OSPI_v0_HwAttrs *hwAttrs; /* OSPI hardware attributes */
OSPI_v0_Object *object; /* OSPI object */
+ uint32_t phyOpMode;
int32_t retVal = SPI_STATUS_ERROR;
const uint32_t *ctrlData = (const uint32_t *)arg;
uint32_t nvcrCmd;
@@ -1828,8 +1829,9 @@ static int32_t OSPI_control_v0(OSPI_Handle handle, uint32_t cmd, const void *arg
uint32_t txDelay = *ctrlData++;
uint32_t rxDelay = *ctrlData;
uint32_t funcClk = hwAttrs->funcClk;
+ phyOpMode = hwAttrs->phyOpMode;
CSL_ospiConfigPhyDLL((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr),
- txDelay, rxDelay, funcClk);
+ txDelay, rxDelay, phyOpMode, funcClk);
}
else
{
index 792f9a5aa2a512d5d2d89c14b65d11c89fbaddc9..4b682e4e2eea8d55bd9a8e1423031785faa219de 100755 (executable)
uintptr_t baseAddr;
/*! OSPI Data base address */
uintptr_t dataAddr;
+ /*!< OSPI PHY dll in master mode/bypass mode */
+ uint32_t phyOpMode;
/*! OSPI IP V0 functional clock */
uint32_t funcClk;
/*! OSPI IP V0 Peripheral CorePac interrupt vector */
diff --git a/packages/ti/drv/spi/test/ospi_flash/src/main_ospi_flash_test.c b/packages/ti/drv/spi/test/ospi_flash/src/main_ospi_flash_test.c
index 7d0adc9b264d0747c13b95ba4b6ffaf8b7ebbaa7..ea764e05466f706cf275970d9102155f747ff553 100755 (executable)
bool dacMode;
bool dmaMode;
bool norFlash;
+ uint32_t phyOpMode;
uint32_t clk;
char testDesc[80];
#define OSPI_NAND_TEST_ID_INDAC_166M 12 /* OSPI flash test in Indirect Acess Controller mode at 166MHz RCLK */
#define OSPI_NAND_TEST_ID_DAC_DMA_166M 13 /* OSPI flash test in Direct Acess Controller DMA mode at 166MHz RCLK */
#define OSPI_NAND_TEST_ID_DAC_133M_SPI 14 /* OSPI flash test in Direct Acess Controller legacy SPI mode at 133MHz RCLK */
+#define OSPI_TEST_ID_PHY_CFG_MASTER 15 /* OSPI Phy Config Master mode test */
+#define OSPI_TEST_ID_PHY_CFG_BYPASS 16 /* OSPI Phy Config Bypass mode test */
/* OSPI NOR flash offset address for read/write test */
#define TEST_ADDR_OFFSET (0U)
/*
* ======== OSPI unit test function ========
*/
+
+static bool OSPI_phyConfigTest(void *arg)
+{
+ OSPI_Params spiParams; /* SPI params structure */
+ OSPI_Handle hwHandle; /* SPI handle */
+ OSPI_v0_HwAttrs ospiCfg;
+ bool retVal = true;
+ int32_t status = SPI_STATUS_SUCCESS;
+ OSPI_Tests *test = (OSPI_Tests *)arg;
+ uint32_t data[3];
+ uint32_t phyOpMode;
+
+#if defined (BUILD_MCU)
+ /* Change interrupt number based on core */
+ status = OSPI_socInit();
+ if(status != SPI_STATUS_SUCCESS)
+ {
+ SPI_log("\nOSPI_socInit failed!!\n");
+ retVal = false;
+ }
+ else
+#endif
+ {
+ /* Get the OSPI SoC configurations */
+ status = OSPI_socGetInitCfg(BOARD_OSPI_DOMAIN, BOARD_OSPI_NOR_INSTANCE, &ospiCfg);
+ if(status != SPI_STATUS_SUCCESS)
+ {
+ SPI_log("\nOSPI_socGetInitCfg failed!!\n");
+ retVal = false;
+ }
+ else
+ {
+ ospiCfg.phyOpMode = test->phyOpMode;
+
+ status = OSPI_socSetInitCfg(BOARD_OSPI_DOMAIN, BOARD_OSPI_NOR_INSTANCE, &ospiCfg);
+ if(status != SPI_STATUS_SUCCESS)
+ {
+ SPI_log("\nOSPI_socGetInitCfg failed!!\n");
+ retVal = false;
+ }
+ else
+ {
+ /* Use default SPI config params if no params provided */
+ OSPI_Params_init(&spiParams);
+ hwHandle = (OSPI_Handle)OSPI_open(BOARD_OSPI_DOMAIN, BOARD_OSPI_NOR_INSTANCE, &spiParams);
+
+ if(hwHandle == NULL)
+ {
+ SPI_log("\nOSPI_open failed!!\n");
+ retVal = false;
+ }
+ else
+ {
+ OSPI_v0_HwAttrs const *hwAttrs= (OSPI_v0_HwAttrs const *)hwHandle->hwAttrs;
+ const CSL_ospi_flash_cfgRegs *pRegs = (const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr);
+
+ data[0] = TRUE;
+ data[1] = 0U;
+ data[2] = 0U;
+
+ status = OSPI_control(hwHandle, OSPI_V0_CMD_CFG_PHY, (void *)data);
+
+ if(status != SPI_STATUS_SUCCESS)
+ {
+ SPI_log("\nOSPI_control failed!!\n");
+ retVal = false;
+ }
+ else
+ {
+ phyOpMode = CSL_REG32_FEXT(&pRegs->PHY_MASTER_CONTROL_REG,
+ OSPI_FLASH_CFG_PHY_MASTER_CONTROL_REG_PHY_MASTER_BYPASS_MODE_FLD);
+
+ if((test->phyOpMode == CSL_OSPI_CFG_PHY_OP_MODE_MASTER))
+ {
+ if(phyOpMode != 0U)
+ {
+ SPI_log("\nFAIL: PHY not configured in master mode\n");
+ retVal = false;
+ }
+ else
+ {
+ SPI_log("\nPHY configured in master mode\n");
+ retVal = true;
+ }
+ }
+ if((test->phyOpMode == CSL_OSPI_CFG_PHY_OP_MODE_BYPASS))
+ {
+ if(phyOpMode != 1U)
+ {
+ SPI_log("\nFAIL: PHY not configured in bypass mode\n");
+ retVal = false;
+ }
+ else
+ {
+ SPI_log("\nPHY configured in bypass mode\n");
+ retVal = true;
+ }
+ }
+ }
+ OSPI_close(hwHandle);
+ }
+ }
+ }
+ }
+ return retVal;
+}
static bool OSPI_flash_test(void *arg)
{
Board_flashHandle boardHandle;
{
#ifdef OSPI_WRITE_TUNING
#if defined(SOC_J7200) || defined(SOC_AM64X) || defined(SOC_J721S2) || defined(SOC_J784S4)
- /* testFunc testID dacMode dmaMode norFlash clk testDesc */
- {OSPI_flash_test, OSPI_TEST_ID_WR_TUNING, false, false, true, OSPI_MODULE_CLK_133M, "\r\n OSPI flash test slave to write tuning data to flash"},
+ /* testFunc testID dacMode dmaMode norFlash phyOpMode clk testDesc */
+ {OSPI_flash_test, OSPI_TEST_ID_WR_TUNING, false, false, true, CSL_OSPI_CFG_PHY_OP_MODE_DEFAULT, OSPI_MODULE_CLK_133M, "\r\n OSPI flash test slave to write tuning data to flash"},
#else
- {OSPI_flash_test, OSPI_TEST_ID_WR_TUNING, true, false, true, OSPI_MODULE_CLK_133M, "\r\n OSPI flash test slave to write tuning data to flash"},
+ {OSPI_flash_test, OSPI_TEST_ID_WR_TUNING, true, false, true, CSL_OSPI_CFG_PHY_OP_MODE_DEFAULT, OSPI_MODULE_CLK_133M, "\r\n OSPI flash test slave to write tuning data to flash"},
#endif
#endif
- {OSPI_flash_test, OSPI_TEST_ID_DAC_133M, true, false, true, OSPI_MODULE_CLK_133M, "\r\n OSPI flash test slave in DAC mode at 133MHz RCLK"},
- {OSPI_flash_test, OSPI_TEST_ID_INDAC_133M, false, false, true, OSPI_MODULE_CLK_133M, "\r\n OSPI flash test slave in INDAC mode at 133MHz RCLK"},
+ {OSPI_flash_test, OSPI_TEST_ID_DAC_133M, true, false, true, CSL_OSPI_CFG_PHY_OP_MODE_DEFAULT, OSPI_MODULE_CLK_133M, "\r\n OSPI flash test slave in DAC mode at 133MHz RCLK"},
+ {OSPI_flash_test, OSPI_TEST_ID_INDAC_133M, false, false, true, CSL_OSPI_CFG_PHY_OP_MODE_DEFAULT, OSPI_MODULE_CLK_133M, "\r\n OSPI flash test slave in INDAC mode at 133MHz RCLK"},
#ifdef SPI_DMA_ENABLE
- {OSPI_flash_test, OSPI_TEST_ID_DAC_DMA_133M, true, true, true, OSPI_MODULE_CLK_133M, "\r\n OSPI flash test slave in DAC DMA mode at 133MHz RCLK"},
+ {OSPI_flash_test, OSPI_TEST_ID_DAC_DMA_133M, true, true, true, CSL_OSPI_CFG_PHY_OP_MODE_DEFAULT, OSPI_MODULE_CLK_133M, "\r\n OSPI flash test slave in DAC DMA mode at 133MHz RCLK"},
#endif
- {OSPI_flash_test, OSPI_TEST_ID_DAC_166M, true, false, true, OSPI_MODULE_CLK_166M, "\r\n OSPI flash test slave in DAC mode at 166MHz RCLK"},
- {OSPI_flash_test, OSPI_TEST_ID_INDAC_166M, false, false, true, OSPI_MODULE_CLK_166M, "\r\n OSPI flash test slave in INDAC mode at 166MHz RCLK"},
+ {OSPI_flash_test, OSPI_TEST_ID_DAC_166M, true, false, true, CSL_OSPI_CFG_PHY_OP_MODE_DEFAULT, OSPI_MODULE_CLK_166M, "\r\n OSPI flash test slave in DAC mode at 166MHz RCLK"},
+ {OSPI_flash_test, OSPI_TEST_ID_INDAC_166M, false, false, true, CSL_OSPI_CFG_PHY_OP_MODE_DEFAULT, OSPI_MODULE_CLK_166M, "\r\n OSPI flash test slave in INDAC mode at 166MHz RCLK"},
#ifdef SPI_DMA_ENABLE
- {OSPI_flash_test, OSPI_TEST_ID_DAC_DMA_166M, true, true, true, OSPI_MODULE_CLK_166M, "\r\n OSPI flash test slave in DAC DMA mode at 166MHz RCLK"},
+ {OSPI_flash_test, OSPI_TEST_ID_DAC_DMA_166M, true, true, true, CSL_OSPI_CFG_PHY_OP_MODE_DEFAULT, OSPI_MODULE_CLK_166M, "\r\n OSPI flash test slave in DAC DMA mode at 166MHz RCLK"},
#endif
- {OSPI_flash_test, OSPI_TEST_ID_DAC_133M_SPI, true, false, true, OSPI_MODULE_CLK_133M, "\r\n OSPI flash test slave in DAC Legacy SPI mode at 133MHz RCLK"},
+ {OSPI_flash_test, OSPI_TEST_ID_DAC_133M_SPI, true, false, true, CSL_OSPI_CFG_PHY_OP_MODE_DEFAULT, OSPI_MODULE_CLK_133M, "\r\n OSPI flash test slave in DAC Legacy SPI mode at 133MHz RCLK"},
#if defined(SOC_J721S2) || defined(SOC_J784S4)
- {OSPI_flash_test, OSPI_NAND_TEST_ID_INDAC_166M, false, false, false, OSPI_MODULE_CLK_166M, "\r\n OSPI NAND flash test slave in INDAC mode at 166MHz RCLK"},
- {OSPI_flash_test, OSPI_NAND_TEST_ID_DAC_133M_SPI, true, false, false, OSPI_MODULE_CLK_133M, "\r\n OSPI NAND flash test slave in DAC Legacy SPI mode at 133MHz RCLK"},
- {OSPI_flash_test, OSPI_NAND_TEST_ID_INDAC_133M, false, false, false, OSPI_MODULE_CLK_133M, "\r\n OSPI NAND flash test slave in INDAC mode at 133MHz RCLK"},
- {OSPI_flash_test, OSPI_NAND_TEST_ID_DAC_133M, true, false, false, OSPI_MODULE_CLK_133M, "\r\n OSPI NAND flash test slave in DAC mode at 133MHz RCLK"},
+ {OSPI_flash_test, OSPI_NAND_TEST_ID_INDAC_166M, false, false, false, CSL_OSPI_CFG_PHY_OP_MODE_DEFAULT, OSPI_MODULE_CLK_166M, "\r\n OSPI NAND flash test slave in INDAC mode at 166MHz RCLK"},
+ {OSPI_flash_test, OSPI_NAND_TEST_ID_DAC_133M_SPI, true, false, false, CSL_OSPI_CFG_PHY_OP_MODE_DEFAULT, OSPI_MODULE_CLK_133M, "\r\n OSPI NAND flash test slave in DAC Legacy SPI mode at 133MHz RCLK"},
+ {OSPI_flash_test, OSPI_NAND_TEST_ID_INDAC_133M, false, false, false, CSL_OSPI_CFG_PHY_OP_MODE_DEFAULT, OSPI_MODULE_CLK_133M, "\r\n OSPI NAND flash test slave in INDAC mode at 133MHz RCLK"},
+ {OSPI_flash_test, OSPI_NAND_TEST_ID_DAC_133M, true, false, false, CSL_OSPI_CFG_PHY_OP_MODE_DEFAULT, OSPI_MODULE_CLK_133M, "\r\n OSPI NAND flash test slave in DAC mode at 133MHz RCLK"},
#ifdef SPI_DMA_ENABLE
- {OSPI_flash_test, OSPI_NAND_TEST_ID_DAC_DMA_133M, true, true, false, OSPI_MODULE_CLK_133M, "\r\n OSPI NAND flash test slave in DAC DMA mode at 133MHz RCLK"},
+ {OSPI_flash_test, OSPI_NAND_TEST_ID_DAC_DMA_133M, true, true, false, CSL_OSPI_CFG_PHY_OP_MODE_DEFAULT, OSPI_MODULE_CLK_133M, "\r\n OSPI NAND flash test slave in DAC DMA mode at 133MHz RCLK"},
#endif
- {OSPI_flash_test, OSPI_NAND_TEST_ID_DAC_166M, true, false, false, OSPI_MODULE_CLK_166M, "\r\n OSPI NAND flash test slave in DAC mode at 166MHz RCLK"},
+ {OSPI_flash_test, OSPI_NAND_TEST_ID_DAC_166M, true, false, false, CSL_OSPI_CFG_PHY_OP_MODE_DEFAULT, OSPI_MODULE_CLK_166M, "\r\n OSPI NAND flash test slave in DAC mode at 166MHz RCLK"},
#ifdef SPI_DMA_ENABLE
- {OSPI_flash_test, OSPI_NAND_TEST_ID_DAC_DMA_166M, true, true, false, OSPI_MODULE_CLK_166M, "\r\n OSPI NAND flash test slave in DAC DMA mode at 166MHz RCLK"},
+ {OSPI_flash_test, OSPI_NAND_TEST_ID_DAC_DMA_166M, true, true, false, CSL_OSPI_CFG_PHY_OP_MODE_DEFAULT, OSPI_MODULE_CLK_166M, "\r\n OSPI NAND flash test slave in DAC DMA mode at 166MHz RCLK"},
#endif
#endif
+ {OSPI_phyConfigTest, OSPI_TEST_ID_PHY_CFG_MASTER, true, false, true, CSL_OSPI_CFG_PHY_OP_MODE_MASTER, OSPI_MODULE_CLK_133M, "\r\n OSPI Phy Config Master mode test"},
+ {OSPI_phyConfigTest, OSPI_TEST_ID_PHY_CFG_BYPASS, true, false, true, CSL_OSPI_CFG_PHY_OP_MODE_BYPASS, OSPI_MODULE_CLK_133M, "\r\n OSPI Phy Config bypass mode test"},
{NULL, }
};