OSPI: AM65XX OSPI Test Cases Fix

Signed-off-by: Aditya Wadhwa <a0485151@ti.com>

diff --git a/packages/ti/drv/spi/spi_component.mk b/packages/ti/drv/spi/spi_component.mk
index 97b201d807ab20127e8a7624350774452dca1679..986c8a030a8612537d743bb7dad1a19facc2979a 100755 (executable)
--- a/packages/ti/drv/spi/spi_component.mk
+++ b/packages/ti/drv/spi/spi_component.mk
@@ -94,6 +94,7 @@ drvspi_dra72x_CORELIST = c66x a15_0 ipu1_0
 drvspi_dra75x_CORELIST = c66x a15_0 ipu1_0
 drvspi_dra78x_CORELIST = c66x ipu1_0
 drvspi_am65xx_CORELIST = mpu1_0 mcu1_0
+drvspi_am65xx_CORELIST_CACHE = mpu1_0 mcu1_0
 drvspi_j721e_CORELIST  = $(DEFAULT_j721e_CORELIST)
 drvspi_j721e_CORELISTARM  = mpu1_0 mcu1_0 mcu1_1 mcu2_0 mcu2_1 mcu3_0 mcu3_1
 drvspi_j721e_CORELISTARM_CACHE  = mcu1_0 mcu1_1 mcu2_0 mcu2_1 mcu3_0 mcu3_1

diff --git a/packages/ti/drv/spi/test/ospi_flash/am65xx/cached/baremetal_mpu_config.c b/packages/ti/drv/spi/test/ospi_flash/am65xx/cached/baremetal_mpu_config.c
new file mode 100755 (executable)
index 0000000..aeffbaa
--- /dev/null
+++ b/packages/ti/drv/spi/test/ospi_flash/am65xx/cached/baremetal_mpu_config.c
@@ -0,0 +1,182 @@
+/**\r
+ *  \file   baremetal_mpu_config.c\r
+ *\r
+ *  \brief  File to override the mpu config in baremetal builds\r
+ *\r
+ */\r
+\r
+/*\r
+ * Copyright (C) 2017 - 2021 Texas Instruments Incorporated - http://www.ti.com/\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the\r
+ * distribution.\r
+ *\r
+ * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ */\r
+\r
+#include <ti/csl/arch/csl_arch.h>\r
+\r
+const CSL_ArmR5MpuRegionCfg gCslR5MpuCfg[CSL_ARM_R5F_MPU_REGIONS_MAX] =\r
+{\r
+    {\r
+        /* Region 0 configuration: complete 32 bit address space = 4Gbits */\r
+        .regionId         = 0U,\r
+        .enable           = 1U,\r
+        .baseAddr         = 0x0U,\r
+        .size             = CSL_ARM_R5_MPU_REGION_SIZE_4GB,\r
+        .subRegionEnable  = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,\r
+        .exeNeverControl  = 1U,\r
+        .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,\r
+        .shareable        = 0U,\r
+        .cacheable        = (uint32_t)FALSE,\r
+        .cachePolicy      = 0U,\r
+        .memAttr          = 0U,\r
+    },\r
+    {\r
+        /* Region 1 configuration: 128 bytes memory for exception vector execution */\r
+        .regionId         = 1U,\r
+        .enable           = 1U,\r
+        .baseAddr         = 0x0U,\r
+        .size             = CSL_ARM_R5_MPU_REGION_SIZE_128B,\r
+        .subRegionEnable  = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,\r
+        .exeNeverControl  = 0U,\r
+        .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,\r
+        .shareable        = 0U,\r
+        .cacheable        = (uint32_t)TRUE,\r
+        .cachePolicy      = CSL_ARM_R5_CACHE_POLICY_WB_WA,\r
+        .memAttr          = 0U,\r
+    },\r
+    {\r
+        /* Region 2 configuration: 1MB KB MCU MSRAM */\r
+        .regionId         = 2U,\r
+        .enable           = 1U,\r
+        .baseAddr         = 0x41C00000,\r
+        .size             = CSL_ARM_R5_MPU_REGION_SIZE_512KB,\r
+        .subRegionEnable  = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,\r
+        .exeNeverControl  = 0U,\r
+        .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,\r
+        .shareable        = 0U,\r
+        .cacheable        = (uint32_t)TRUE,\r
+        .cachePolicy      = CSL_ARM_R5_CACHE_POLICY_WB_WA,\r
+        .memAttr          = 0U,\r
+    },\r
+    {\r
+        /* Region 3 configuration: 2 MB MCMS3 RAM */\r
+        .regionId         = 3U,\r
+        .enable           = 1U,\r
+        .baseAddr         = 0x70000000,\r
+        .size             = CSL_ARM_R5_MPU_REGION_SIZE_2MB,\r
+        .subRegionEnable  = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,\r
+        .exeNeverControl  = 0U,\r
+        .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,\r
+        .shareable        = 0U,\r
+        .cacheable        = (uint32_t)TRUE,\r
+        .cachePolicy      = CSL_ARM_R5_CACHE_POLICY_WB_WA,\r
+        .memAttr          = 0U,\r
+    },\r
+    {\r
+        /* Region 4 configuration: 2 GB DDR RAM */\r
+        .regionId         = 4U,\r
+        .enable           = 1U,\r
+        .baseAddr         = 0x80000000,\r
+        .size             = CSL_ARM_R5_MPU_REGION_SIZE_2GB,\r
+        .subRegionEnable  = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,\r
+        .exeNeverControl  = 0U,\r
+        .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,\r
+        .shareable        = 0U,\r
+        .cacheable        = (uint32_t)TRUE,\r
+        .cachePolicy      = CSL_ARM_R5_CACHE_POLICY_WB_WA,\r
+        .memAttr          = 0U,\r
+    },\r
+    {\r
+        /* Region 5 configuration: 32 KB BTCM */\r
+        /* Address of ATCM/BTCM are configured via MCU_SEC_MMR registers\r
+           It can either be '0x0' or '0x41010000'. Application/Boot-loader shall\r
+           take care this configurations and linker command file shall be\r
+           in sync with this. For either of the above configurations,\r
+           MPU configurations will not changes as both regions will have same\r
+           set of permissions in almost all scenarios.\r
+           Application can chose to overwrite this MPU configuration if needed.\r
+           The same is true for the region corresponding to ATCM. */\r
+        .regionId         = 5U,\r
+        .enable           = 1U,\r
+        .baseAddr         = 0x41010000,\r
+        .size             = CSL_ARM_R5_MPU_REGION_SIZE_32KB,\r
+        .subRegionEnable  = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,\r
+        .exeNeverControl  = 0U,\r
+        .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,\r
+        .shareable        = 0U,\r
+        .cacheable        = (uint32_t)TRUE,\r
+        .cachePolicy      = CSL_ARM_R5_CACHE_POLICY_NON_CACHEABLE,\r
+        .memAttr          = 0U,\r
+    },\r
+    {\r
+        /* Region 6 configuration: 32 KB ATCM */\r
+        .regionId         = 6U,\r
+        .enable           = 1U,\r
+        .baseAddr         = 0x0,\r
+        .size             = CSL_ARM_R5_MPU_REGION_SIZE_32KB,\r
+        .subRegionEnable  = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,\r
+        .exeNeverControl  = 0U,\r
+        .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,\r
+        .shareable        = 0U,\r
+        .cacheable        = (uint32_t)TRUE,\r
+        .cachePolicy      = CSL_ARM_R5_CACHE_POLICY_NON_CACHEABLE,\r
+        .memAttr          = 0U,\r
+    },\r
+    {\r
+        /* Region 7 configuration: Covers first 64MB of EVM Flash (FSS DAT0) */\r
+        .regionId         = 7U,\r
+        .enable           = 1U,\r
+        .baseAddr         = 0x50000000,\r
+        .size             = CSL_ARM_R5_MPU_REGION_SIZE_64MB,\r
+        .subRegionEnable  = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,\r
+        .exeNeverControl  = 0U,\r
+        .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,\r
+        .shareable        = 0U,\r
+        .cacheable        = (uint32_t)TRUE,\r
+        .cachePolicy      = CSL_ARM_R5_CACHE_POLICY_WB_WA,\r
+        .memAttr          = 0U,\r
+    },\r
+    {\r
+        /* Region 8 configuration: Covers last 128KB of EVM Flash (FSS DAT0) */\r
+        /* OSPI PHY tuning algorithm which runs in DAC mode needs\r
+         * cache to be disabled for this section of FSS data region.\r
+         */\r
+        .regionId         = 8U,\r
+        .enable           = 1U,\r
+        .baseAddr         = 0x53FE0000,\r
+        .size             = CSL_ARM_R5_MPU_REGION_SIZE_128KB,\r
+        .subRegionEnable  = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,\r
+        .exeNeverControl  = 0U,\r
+        .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,\r
+        .shareable        = 0U,\r
+        .cacheable        = (uint32_t)FALSE,\r
+        .cachePolicy      = 0U,\r
+        .memAttr          = 0U,\r
+    },\r
+};\r

diff --git a/packages/ti/drv/spi/test/ospi_flash/am65xx/cached/mpu.xs b/packages/ti/drv/spi/test/ospi_flash/am65xx/cached/mpu.xs
new file mode 100755 (executable)
index 0000000..4c23dae
--- /dev/null
+++ b/packages/ti/drv/spi/test/ospi_flash/am65xx/cached/mpu.xs
@@ -0,0 +1,148 @@
+/*
+ * Copyright (c) 2018, Texas Instruments Incorporated
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * *  Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ * *  Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * *  Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+/*
+ *  ======== event_MPU.xs ========
+ *  MPU Settings for SIMMAXWELL device's Cortex-R5F
+ */
+
+/*
+ *  -------------------------------------------------------------------------------------------------------------
+ * | Id | Base Address | Size | En | Cacheable                                 | XN | AccPerm             | Mask |
+ * |-------------------------------------------------------------------------------------------------------------|
+ * | 0  | 0x00000000   | 4GB  | T  | Strongly Ordered, Shareable               | T  | RW at PL 1          | 0x0  |
+ * |----|--------------|------|----|-------------------------------------------|----|---------------------|------|
+ * | 1  | 0x00000000   | 1K   | T  | Write-Back, Write-Allocate, Non-Shareable | F  | RW at PL 1          | 0x0  |
+ * |----|--------------|------|----|-------------------------------------------|----|---------------------|------|
+ * | 2  | 0x41000000   | 32K  | T  | Write-Back, Write-Allocate, Non-Shareable | F  | RW at PL 1          | 0x0  |
+ * |----|--------------|------|----|-------------------------------------------|----|---------------------|------|
+ * | 3  | 0x41010000   | 32K  | T  | Write-Back, Write-Allocate, Non-Shareable | F  | RW at PL 1          | 0x0  |
+ * |----|--------------|------|----|-------------------------------------------|----|---------------------|------|
+ * | 4  | 0x41C00000   | 512K | T  | Write-Back, Write-Allocate, Non-Shareable | F  | RW at PL 1          | 0x0  |
+ * |----|--------------|------|----|-------------------------------------------|----|---------------------|------|
+ * | 5  | 0x50000000   | 64MB | T  | OSPI flash memory - Cacheable             | F  | RW at PL 1 & PL 2   | 0x0  |
+ * |----|--------------|------|----|-------------------------------------------|----|---------------------|------|
+ * | 6  | 0x53FE0000   | 128KB| T  | OSPI flash memory - UnCacheable           | F  | RW at PL 1 & PL 2   | 0x0  |
+ *  --------------------------------------------------------------------------------------------------------------
+ */
+
+/*
+ * Note: Marking a region as shareable will cause the region to behave as outer shareable with write through
+ *       no write-allocate caching policy irrespective of the actual cache policy set. Therefore, only select
+ *       regions that are actually shared outside the R5 CPUSS must be marked as shared.
+ */
+
+var MPU = xdc.useModule('ti.sysbios.family.arm.MPU');
+MPU.enableMPU = true;
+MPU.enableBackgroundRegion = true;
+
+var attrs = new MPU.RegionAttrs();
+MPU.initRegionAttrsMeta(attrs);
+
+attrs.enable = true;
+attrs.bufferable = false;
+attrs.cacheable = false;
+attrs.shareable = true;
+attrs.noExecute = true;
+attrs.accPerm = 1;          /* RW at PL1 */
+attrs.tex = 0;
+attrs.subregionDisableMask = 0;
+MPU.setRegionMeta(0, 0x00000000, MPU.RegionSize_4G, attrs);
+
+attrs.enable = true;
+attrs.bufferable = true;
+attrs.cacheable = true;
+attrs.shareable = false;
+attrs.noExecute = false;
+attrs.accPerm = 1;          /* RW at PL1 */
+attrs.tex = 1;
+attrs.subregionDisableMask = 0;
+MPU.setRegionMeta(1, 0x00000000, MPU.RegionSize_32K, attrs);
+
+attrs.enable = true;
+attrs.bufferable = true;
+attrs.cacheable = true;
+attrs.shareable = false;
+attrs.noExecute = false;
+attrs.accPerm = 1;          /* RW at PL1 */
+attrs.tex = 1;
+attrs.subregionDisableMask = 0;
+MPU.setRegionMeta(2, 0x41000000, MPU.RegionSize_32K, attrs);
+
+attrs.enable = true;
+attrs.bufferable = true;
+attrs.cacheable = true;
+attrs.shareable = false;
+attrs.noExecute = false;
+attrs.accPerm = 1;          /* RW at PL1 */
+attrs.tex = 1;
+attrs.subregionDisableMask = 0x0;
+MPU.setRegionMeta(3, 0x41010000, MPU.RegionSize_32K, attrs);
+
+attrs.enable = true;
+attrs.bufferable = true;
+attrs.cacheable = true;
+attrs.shareable = false;
+attrs.noExecute = false;
+attrs.accPerm = 1;          /* RW at PL1 */
+attrs.tex = 1;
+attrs.subregionDisableMask = 0;
+MPU.setRegionMeta(4, 0x41C00000, MPU.RegionSize_512K, attrs);
+
+attrs.enable = true;
+attrs.bufferable = true;
+attrs.cacheable = true;
+attrs.shareable = false;
+attrs.noExecute = false;
+attrs.accPerm = 1;          /* RW at PL1 */
+attrs.tex = 1;
+attrs.subregionDisableMask = 0;
+MPU.setRegionMeta(5, 0x70000000, MPU.RegionSize_2M, attrs);
+
+attrs.enable = true;
+attrs.bufferable = true;
+attrs.cacheable = true;
+attrs.shareable = false;
+attrs.noExecute = false;
+attrs.accPerm = 3;          /* RW at PL1 & PL2*/
+attrs.tex = 1;
+attrs.subregionDisableMask = 0;
+MPU.setRegionMeta(6, 0x50000000, MPU.RegionSize_64M, attrs);
+
+attrs.enable = true;
+attrs.bufferable = false;
+attrs.cacheable = false;
+attrs.shareable = false;
+attrs.noExecute = false;
+attrs.accPerm = 3;          /* RW at PL1 & PL2 */
+attrs.tex = 0;
+attrs.subregionDisableMask = 0;
+MPU.setRegionMeta(7, 0x53FE0000, MPU.RegionSize_128K, attrs);

diff --git a/packages/ti/drv/spi/test/ospi_flash/am65xx/ospiFlashTest_a53.cfg b/packages/ti/drv/spi/test/ospi_flash/am65xx/cached/ospiFlashTest_a53.cfg
old mode 100644 (file)
new mode 100755 (executable)
similarity index 100%
rename from packages/ti/drv/spi/test/ospi_flash/am65xx/ospiFlashTest_a53.cfg
rename to packages/ti/drv/spi/test/ospi_flash/am65xx/cached/ospiFlashTest_a53.cfg

diff --git a/packages/ti/drv/spi/test/ospi_flash/am65xx/ospiFlashTest_r5.cfg b/packages/ti/drv/spi/test/ospi_flash/am65xx/cached/ospiFlashTest_r5.cfg
similarity index 100%
rename from packages/ti/drv/spi/test/ospi_flash/am65xx/ospiFlashTest_r5.cfg
rename to packages/ti/drv/spi/test/ospi_flash/am65xx/cached/ospiFlashTest_r5.cfg

diff --git a/packages/ti/drv/spi/test/ospi_flash/am65xx/non_cached/baremetal_mpu_config.c b/packages/ti/drv/spi/test/ospi_flash/am65xx/non_cached/baremetal_mpu_config.c
new file mode 100755 (executable)
index 0000000..5cda7ce
--- /dev/null
+++ b/packages/ti/drv/spi/test/ospi_flash/am65xx/non_cached/baremetal_mpu_config.c
@@ -0,0 +1,151 @@
+/**\r
+ *  \file   baremetal_mpu_config.c\r
+ *\r
+ *  \brief  File to override the mpu config in baremetal builds\r
+ *\r
+ */\r
+\r
+/*\r
+ * Copyright (C) 2017 - 2021 Texas Instruments Incorporated - http://www.ti.com/\r
+ *\r
+ * Redistribution and use in source and binary forms, with or without\r
+ * modification, are permitted provided that the following conditions\r
+ * are met:\r
+ *\r
+ * Redistributions of source code must retain the above copyright\r
+ * notice, this list of conditions and the following disclaimer.\r
+ *\r
+ * Redistributions in binary form must reproduce the above copyright\r
+ * notice, this list of conditions and the following disclaimer in the\r
+ * documentation and/or other materials provided with the\r
+ * distribution.\r
+ *\r
+ * Neither the name of Texas Instruments Incorporated nor the names of\r
+ * its contributors may be used to endorse or promote products derived\r
+ * from this software without specific prior written permission.\r
+ *\r
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS\r
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT\r
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR\r
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT\r
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,\r
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY\r
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE\r
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+ *\r
+ */\r
+\r
+#include <ti/csl/arch/csl_arch.h>\r
+\r
+const CSL_ArmR5MpuRegionCfg gCslR5MpuCfg[CSL_ARM_R5F_MPU_REGIONS_MAX] =\r
+{\r
+    {\r
+        /* Region 0 configuration: complete 32 bit address space = 4Gbits */\r
+        .regionId         = 0U,\r
+        .enable           = 1U,\r
+        .baseAddr         = 0x0U,\r
+        .size             = CSL_ARM_R5_MPU_REGION_SIZE_4GB,\r
+        .subRegionEnable  = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,\r
+        .exeNeverControl  = 1U,\r
+        .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,\r
+        .shareable        = 0U,\r
+        .cacheable        = (uint32_t)FALSE,\r
+        .cachePolicy      = 0U,\r
+        .memAttr          = 0U,\r
+    },\r
+    {\r
+        /* Region 1 configuration: 128 bytes memory for exception vector execution */\r
+        .regionId         = 1U,\r
+        .enable           = 1U,\r
+        .baseAddr         = 0x0U,\r
+        .size             = CSL_ARM_R5_MPU_REGION_SIZE_128B,\r
+        .subRegionEnable  = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,\r
+        .exeNeverControl  = 0U,\r
+        .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,\r
+        .shareable        = 0U,\r
+        .cacheable        = (uint32_t)TRUE,\r
+        .cachePolicy      = CSL_ARM_R5_CACHE_POLICY_WB_WA,\r
+        .memAttr          = 0U,\r
+    },\r
+    {\r
+        /* Region 2 configuration: 1MB KB MCU MSRAM */\r
+        .regionId         = 2U,\r
+        .enable           = 1U,\r
+        .baseAddr         = 0x41C00000,\r
+        .size             = CSL_ARM_R5_MPU_REGION_SIZE_512KB,\r
+        .subRegionEnable  = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,\r
+        .exeNeverControl  = 0U,\r
+        .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,\r
+        .shareable        = 0U,\r
+        .cacheable        = (uint32_t)TRUE,\r
+        .cachePolicy      = CSL_ARM_R5_CACHE_POLICY_WB_WA,\r
+        .memAttr          = 0U,\r
+    },\r
+    {\r
+        /* Region 3 configuration: 2 MB MCMS3 RAM */\r
+        .regionId         = 3U,\r
+        .enable           = 1U,\r
+        .baseAddr         = 0x70000000,\r
+        .size             = CSL_ARM_R5_MPU_REGION_SIZE_2MB,\r
+        .subRegionEnable  = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,\r
+        .exeNeverControl  = 0U,\r
+        .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,\r
+        .shareable        = 0U,\r
+        .cacheable        = (uint32_t)TRUE,\r
+        .cachePolicy      = CSL_ARM_R5_CACHE_POLICY_WB_WA,\r
+        .memAttr          = 0U,\r
+    },\r
+    {\r
+        /* Region 4 configuration: 2 GB DDR RAM */\r
+        .regionId         = 4U,\r
+        .enable           = 1U,\r
+        .baseAddr         = 0x80000000,\r
+        .size             = CSL_ARM_R5_MPU_REGION_SIZE_2GB,\r
+        .subRegionEnable  = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,\r
+        .exeNeverControl  = 0U,\r
+        .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,\r
+        .shareable        = 0U,\r
+        .cacheable        = (uint32_t)TRUE,\r
+        .cachePolicy      = CSL_ARM_R5_CACHE_POLICY_WB_WA,\r
+        .memAttr          = 0U,\r
+    },\r
+    {\r
+        /* Region 5 configuration: 32 KB BTCM */\r
+        /* Address of ATCM/BTCM are configured via MCU_SEC_MMR registers\r
+           It can either be '0x0' or '0x41010000'. Application/Boot-loader shall\r
+           take care this configurations and linker command file shall be\r
+           in sync with this. For either of the above configurations,\r
+           MPU configurations will not changes as both regions will have same\r
+           set of permissions in almost all scenarios.\r
+           Application can chose to overwrite this MPU configuration if needed.\r
+           The same is true for the region corresponding to ATCM. */\r
+        .regionId         = 5U,\r
+        .enable           = 1U,\r
+        .baseAddr         = 0x41010000,\r
+        .size             = CSL_ARM_R5_MPU_REGION_SIZE_32KB,\r
+        .subRegionEnable  = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,\r
+        .exeNeverControl  = 0U,\r
+        .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,\r
+        .shareable        = 0U,\r
+        .cacheable        = (uint32_t)TRUE,\r
+        .cachePolicy      = CSL_ARM_R5_CACHE_POLICY_NON_CACHEABLE,\r
+        .memAttr          = 0U,\r
+    },\r
+    {\r
+        /* Region 6 configuration: 32 KB ATCM */\r
+        .regionId         = 6U,\r
+        .enable           = 1U,\r
+        .baseAddr         = 0x0,\r
+        .size             = CSL_ARM_R5_MPU_REGION_SIZE_32KB,\r
+        .subRegionEnable  = CSL_ARM_R5_MPU_SUB_REGION_ENABLE_ALL,\r
+        .exeNeverControl  = 0U,\r
+        .accessPermission = CSL_ARM_R5_ACC_PERM_PRIV_USR_RD_WR,\r
+        .shareable        = 0U,\r
+        .cacheable        = (uint32_t)TRUE,\r
+        .cachePolicy      = CSL_ARM_R5_CACHE_POLICY_NON_CACHEABLE,\r
+        .memAttr          = 0U,\r
+    },\r
+};\r

diff --git a/packages/ti/drv/spi/test/ospi_flash/am65xx/mpu.xs b/packages/ti/drv/spi/test/ospi_flash/am65xx/non_cached/mpu.xs
old mode 100644 (file)
new mode 100755 (executable)
similarity index 100%
rename from packages/ti/drv/spi/test/ospi_flash/am65xx/mpu.xs
rename to packages/ti/drv/spi/test/ospi_flash/am65xx/non_cached/mpu.xs

diff --git a/packages/ti/drv/spi/test/ospi_flash/am65xx/non_cached/ospiFlashTest_a53.cfg b/packages/ti/drv/spi/test/ospi_flash/am65xx/non_cached/ospiFlashTest_a53.cfg
new file mode 100755 (executable)
index 0000000..38fba51
--- /dev/null
+++ b/packages/ti/drv/spi/test/ospi_flash/am65xx/non_cached/ospiFlashTest_a53.cfg
@@ -0,0 +1,175 @@
+
+/* =============================================================================
+ *   Copyright (c) Texas Instruments Incorporated 2017 - 2019
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+var Defaults = xdc.useModule('xdc.runtime.Defaults');
+var Diags = xdc.useModule('xdc.runtime.Diags');
+var Error = xdc.useModule('xdc.runtime.Error');
+var Log = xdc.useModule('xdc.runtime.Log');
+var LoggerBuf = xdc.useModule('xdc.runtime.LoggerBuf');
+var Main = xdc.useModule('xdc.runtime.Main');
+var Memory = xdc.useModule('xdc.runtime.Memory');
+var System = xdc.useModule('xdc.runtime.System');
+var Text = xdc.useModule('xdc.runtime.Text');
+var Clock = xdc.useModule('ti.sysbios.knl.Clock');
+var Task = xdc.useModule('ti.sysbios.knl.Task');
+var Semaphore = xdc.useModule('ti.sysbios.knl.Semaphore');
+
+var BIOS = xdc.useModule('ti.sysbios.BIOS');
+var Hwi = xdc.useModule('ti.sysbios.hal.Hwi');
+var HeapMem = xdc.useModule('ti.sysbios.heaps.HeapMem');
+var SysMin = xdc.useModule('xdc.runtime.SysMin');
+
+var Mmu = xdc.useModule('ti.sysbios.family.arm.v8a.Mmu');
+Mmu.initFunc = "&InitMmu";
+Mmu.tableArrayLen = 24;
+
+BIOS.cpuFreq.lo = 800000000;
+BIOS.cpuFreq.hi = 0;
+
+/* Enable SMP mode in BIOS if SMP is enabled from makefile */
+var smp = java.lang.System.getenv("SMP")
+if(smp == 'enable')
+{
+    xdc.print("Enabling BIOS SMP mode");
+       BIOS.smpEnabled = true;
+       /* Enable cache */
+       var Cache = xdc.module("ti.sysbios.hal.Cache");
+}
+
+var Timer = xdc.useModule('ti.sysbios.family.arm.v8a.Timer');
+Timer.intFreq.lo = 200000000;
+Timer.intFreq.hi = 0;
+
+var dmTimer = xdc.useModule('ti.sysbios.timers.dmtimer.Timer');
+for (var i = 0; i < 12; i++) {
+    dmTimer.intFreqs[i].lo = 25000000;
+    dmTimer.intFreqs[i].hi = 0;
+}
+
+/*
+ * Direct CIO to UART
+ */
+/* System.SupportProxy = SysUart; */
+System.SupportProxy = SysMin;
+
+/*
+ * Program.argSize sets the size of the .args section.
+ * The examples don't use command line args so argSize is set to 0.
+ */
+Program.argSize = 0x0;
+
+/*
+ * Uncomment this line to globally disable Asserts.
+ * All modules inherit the default from the 'Defaults' module.  You
+ * can override these defaults on a per-module basis using Module.common$.
+ * Disabling Asserts will save code space and improve runtime performance.
+Defaults.common$.diags_ASSERT = Diags.ALWAYS_OFF;
+ */
+
+/*
+ * Uncomment this line to keep module names from being loaded on the target.
+ * The module name strings are placed in the .const section. Setting this
+ * parameter to false will save space in the .const section.  Error and
+ * Assert messages will contain an "unknown module" prefix instead
+ * of the actual module name.
+Defaults.common$.namedModule = false;
+ */
+
+/* Create default heap and hook it into Memory */
+var heapMemParams = new HeapMem.Params;
+heapMemParams.size = 16384*3;
+var heap0 = HeapMem.create(heapMemParams);
+
+Memory.defaultHeapInstance = heap0;
+
+/*
+ * Minimize exit handler array in System.  The System module includes
+ * an array of functions that are registered with System_atexit() to be
+ * called by System_exit().
+ */
+System.maxAtexitHandlers = 4;
+
+/*
+ * Uncomment this line to disable the Error print function.
+ * We lose error information when this is disabled since the errors are
+ * not printed.  Disabling the raiseHook will save some code space if
+ * your app is not using System_printf() since the Error_print() function
+ * calls System_printf().
+Error.raiseHook = null;
+ */
+
+/*
+ * Uncomment this line to keep Error, Assert, and Log strings from being
+ * loaded on the target.  These strings are placed in the .const section.
+ * Setting this parameter to false will save space in the .const section.
+ * Error, Assert and Log message will print raw ids and args instead of
+ * a formatted message.
+Text.isLoaded = false;
+ */
+
+/*
+ * Uncomment this line to disable the output of characters by SysMin
+ * when the program exits.  SysMin writes characters to a circular buffer.
+ * This buffer can be viewed using the SysMin Output view in ROV.
+SysMin.flushAtExit = false;
+ */
+
+/*
+ * The BIOS module will create the default heap for the system.
+ * Specify the size of this default heap.
+ *
+ * BIOS.heapSize = 0x2000; */
+
+/* System stack size (used by ISRs and Swis) */
+Program.stack = 0x4000;
+
+Task.defaultStackSize = 0x4000;
+
+/*
+ * Create and install logger for the whole system
+ */
+var loggerBufParams = new LoggerBuf.Params();
+loggerBufParams.numEntries = 32;
+var logger0 = LoggerBuf.create(loggerBufParams);
+Defaults.common$.logger = logger0;
+Main.common$.diags_INFO = Diags.ALWAYS_ON;
+
+BIOS.libType = BIOS.LibType_Custom;
+
+var Load = xdc.useModule('ti.sysbios.utils.Load');
+
+/* load calculation related settings */
+Load.swiEnabled   = true;
+Load.hwiEnabled   = true;
+Load.taskEnabled  = true;
+Load.updateInIdle = false;
+

diff --git a/packages/ti/drv/spi/test/ospi_flash/am65xx/non_cached/ospiFlashTest_r5.cfg b/packages/ti/drv/spi/test/ospi_flash/am65xx/non_cached/ospiFlashTest_r5.cfg
new file mode 100755 (executable)
index 0000000..050b1f7
--- /dev/null
+++ b/packages/ti/drv/spi/test/ospi_flash/am65xx/non_cached/ospiFlashTest_r5.cfg
@@ -0,0 +1,172 @@
+
+/* =============================================================================
+ *   Copyright (c) Texas Instruments Incorporated 2017 - 2018
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions
+ *  are met:
+ *
+ *    Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *    Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *    Neither the name of Texas Instruments Incorporated nor the names of
+ *    its contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+var Defaults = xdc.useModule('xdc.runtime.Defaults');
+var Diags = xdc.useModule('xdc.runtime.Diags');
+var Error = xdc.useModule('xdc.runtime.Error');
+var Log = xdc.useModule('xdc.runtime.Log');
+var LoggerBuf = xdc.useModule('xdc.runtime.LoggerBuf');
+var Main = xdc.useModule('xdc.runtime.Main');
+var Memory = xdc.useModule('xdc.runtime.Memory')
+var System = xdc.useModule('xdc.runtime.System');
+var Text = xdc.useModule('xdc.runtime.Text');
+var Clock = xdc.useModule('ti.sysbios.knl.Clock');
+var Task = xdc.useModule('ti.sysbios.knl.Task');
+var Semaphore = xdc.useModule('ti.sysbios.knl.Semaphore');
+
+var BIOS = xdc.useModule('ti.sysbios.BIOS');
+var Hwi = xdc.useModule('ti.sysbios.family.arm.v7r.keystone3.Hwi');
+var HeapMem = xdc.useModule('ti.sysbios.heaps.HeapMem');
+var SysMin = xdc.useModule('xdc.runtime.SysMin');
+
+Clock.timerId = 1;
+
+BIOS.cpuFreq.lo = 400000000;
+BIOS.cpuFreq.hi = 0;
+
+var dmtimer = xdc.useModule('ti.sysbios.timers.dmtimer.Timer');
+for (var i = 0; i < 4; i++) {
+    dmtimer.intFreqs[i].lo = 25000000;
+    dmtimer.intFreqs[i].hi = 0;
+}
+
+var Reset = xdc.useModule("xdc.runtime.Reset");
+Reset.fxns[Reset.fxns.length++] = "&utilsCopyVecs2ATcm";
+
+/* Enable cache */
+var Cache = xdc.useModule('ti.sysbios.family.arm.v7r.Cache');
+Cache.enableCache = true;
+
+/*
+ * Direct CIO to UART
+ */
+/* System.SupportProxy = SysUart; */
+System.SupportProxy = SysMin;
+
+/* 
+ * Program.argSize sets the size of the .args section. 
+ * The examples don't use command line args so argSize is set to 0.
+ */
+Program.argSize = 0x0;
+
+/*
+ * Uncomment this line to globally disable Asserts.
+ * All modules inherit the default from the 'Defaults' module.  You
+ * can override these defaults on a per-module basis using Module.common$. 
+ * Disabling Asserts will save code space and improve runtime performance.
+Defaults.common$.diags_ASSERT = Diags.ALWAYS_OFF;
+ */
+
+/*
+ * Uncomment this line to keep module names from being loaded on the target.
+ * The module name strings are placed in the .const section. Setting this
+ * parameter to false will save space in the .const section.  Error and
+ * Assert messages will contain an "unknown module" prefix instead
+ * of the actual module name.
+Defaults.common$.namedModule = false;
+ */
+
+/* Create default heap and hook it into Memory */
+var heapMemParams = new HeapMem.Params;
+heapMemParams.size = 16384*3;
+var heap0 = HeapMem.create(heapMemParams);
+
+Memory.defaultHeapInstance = heap0;
+
+/*
+ * Minimize exit handler array in System.  The System module includes
+ * an array of functions that are registered with System_atexit() to be
+ * called by System_exit().
+ */
+System.maxAtexitHandlers = 4;       
+
+/* 
+ * Uncomment this line to disable the Error print function.  
+ * We lose error information when this is disabled since the errors are
+ * not printed.  Disabling the raiseHook will save some code space if
+ * your app is not using System_printf() since the Error_print() function
+ * calls System_printf().
+Error.raiseHook = null;
+ */
+
+/* 
+ * Uncomment this line to keep Error, Assert, and Log strings from being
+ * loaded on the target.  These strings are placed in the .const section.
+ * Setting this parameter to false will save space in the .const section.
+ * Error, Assert and Log message will print raw ids and args instead of
+ * a formatted message.
+Text.isLoaded = false;
+ */
+
+/*
+ * Uncomment this line to disable the output of characters by SysMin
+ * when the program exits.  SysMin writes characters to a circular buffer.
+ * This buffer can be viewed using the SysMin Output view in ROV.
+SysMin.flushAtExit = false;
+ */
+
+/* 
+ * The BIOS module will create the default heap for the system.
+ * Specify the size of this default heap.
+ *
+ * BIOS.heapSize = 0x2000; */
+
+/* System stack size (used by ISRs and Swis) */
+Program.stack = 0x4000;
+
+Task.defaultStackSize = 0x4000;
+
+/* 
+ * Create and install logger for the whole system
+ */
+var loggerBufParams = new LoggerBuf.Params();
+loggerBufParams.numEntries = 32;
+var logger0 = LoggerBuf.create(loggerBufParams);
+Defaults.common$.logger = logger0;
+Main.common$.diags_INFO = Diags.ALWAYS_ON;
+
+BIOS.libType = BIOS.LibType_Custom;
+
+/*
+ * Initialize MPU and enable it
+ *
+ * Note: MPU must be enabled and properly configured for caching to work.
+ */
+xdc.loadCapsule("mpu.xs");
+
+var Load = xdc.useModule('ti.sysbios.utils.Load');
+
+/* load calculation related settings */
+Load.swiEnabled   = true;
+Load.hwiEnabled   = true;
+Load.taskEnabled  = true;
+Load.updateInIdle = false;

diff --git a/packages/ti/drv/spi/test/ospi_flash/makefile b/packages/ti/drv/spi/test/ospi_flash/makefile
index 45d67c25e61f70414b01b0f3f07de1fa205ac820..c3da036b7dfe4b684e007ca5400876e1d1cc1f19 100755 (executable)
--- a/packages/ti/drv/spi/test/ospi_flash/makefile
+++ b/packages/ti/drv/spi/test/ospi_flash/makefile
@@ -11,7 +11,7 @@ XDC_CFG_FILE_mpu1_0 =
 XDC_CFG_FILE_mcu1_0 =
 SRCDIR += . src
 SRCS_COMMON += main_ospi_flash_test.c 
-ifeq ($(SOC),$(filter $(SOC), j7200 j721e am64x))
+ifeq ($(SOC),$(filter $(SOC), j7200 j721e am64x am65xx))
     ifeq ($(CACHE), enable)
         ifeq ($(CORE),$(filter $(CORE), mcu1_0 mcu1_1 mcu2_0 mcu2_1 mcu3_0 mcu3_1))
             SRCS_COMMON += ./$(SOC)/cached/baremetal_mpu_config.c
@@ -36,8 +36,13 @@ INCDIR = . src
 
 
 ifeq ($(SOC),$(filter $(SOC), am65xx))
-XDC_CFG_FILE_mpu1_0 = ./$(SOC)/ospiFlashTest_a53.cfg
-XDC_CFG_FILE_mcu1_0 = ./$(SOC)/ospiFlashTest_r5.cfg
+    ifeq ($(CACHE), enable)
+        XDC_CFG_FILE_mpu1_0 = ./$(SOC)/cached/ospiFlashTest_a53.cfg
+        XDC_CFG_FILE_mcu1_0 = ./$(SOC)/cached/ospiFlashTest_r5.cfg
+    else
+        XDC_CFG_FILE_mpu1_0 = ./$(SOC)/non_cached/ospiFlashTest_a53.cfg
+        XDC_CFG_FILE_mcu1_0 = ./$(SOC)/non_cached/ospiFlashTest_r5.cfg
+    endif
 endif
 ifeq ($(SOC),$(filter $(SOC), j7200 j721e am64x))
     ifeq ($(CACHE), enable)