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raw | patch | inline | side by side (parent: 6e7c384)
raw | patch | inline | side by side (parent: 6e7c384)
author | Sivaraj R <sivaraj@ti.com> | |
Sat, 7 Nov 2020 10:14:21 +0000 (15:44 +0530) | ||
committer | Sivaraj R <sivaraj@ti.com> | |
Mon, 9 Nov 2020 09:31:21 +0000 (03:31 -0600) |
- Enabled the QoS settings for Non-HS
- For HS issue, we can track this seperately
- Also used CSLR register write macro instead of
writel which was not using the volatile keyward for
reg access - but not sure if this caused any issues
- The R5F QOS is still disabled as this is causing the
DRU testcases to hang
Signed-off-by: Sivaraj R <sivaraj@ti.com>
- For HS issue, we can track this seperately
- Also used CSLR register write macro instead of
writel which was not using the volatile keyward for
reg access - but not sure if this caused any issues
- The R5F QOS is still disabled as this is causing the
DRU testcases to hang
Signed-off-by: Sivaraj R <sivaraj@ti.com>
diff --git a/packages/ti/boot/sbl/board/evmTPR12/sbl_main.c b/packages/ti/boot/sbl/board/evmTPR12/sbl_main.c
index f9e1a069c50b3c7ebe5cdad6aa14f7cbf107c62e..238aed24d68cf7bbf4faa1a4469798ab56ac2667 100644 (file)
Board_init(BOARD_INIT_UNLOCK_MMR);
/* Any SoC specific Init. */
- SBL_SocEarlyInit();
+ SBL_SocEarlyInit(FALSE);
if (SBL_LOG_LEVEL > SBL_LOG_ERR)
{
#if defined(SBL_ENABLE_PLL)
{
Rcm_PllHsDivOutConfig hsDivCfg;
-
+
SBL_log(SBL_LOG_MAX, "Initlialzing PLLs ...");
SBL_ADD_PROFILE_POINT;
SBL_RcmDspApllConfig(RCM_PLL_FOUT_FREQID_CLK_900MHZ, &hsDivCfg);
hsDivCfg.hsdivOutEnMask = (RCM_PLL_HSDIV_OUTPUT_ENABLE_1 |
- RCM_PLL_HSDIV_OUTPUT_ENABLE_2 |
+ RCM_PLL_HSDIV_OUTPUT_ENABLE_2 |
RCM_PLL_HSDIV_OUTPUT_ENABLE_3);
/* Configure CLKOUT1 to DSS PLL Fout/2. Divider is hsDivOut + 1 so set 1 */
hsDivCfg.hsDivOutFreqHz[RCM_PLL_HSDIV_OUTPUT_IDX1] = SBL_FREQ_MHZ2HZ(192U);
index c436622eada6deb3ed6f89d8aba886167fe1fe06..ebcb272c0990960704b2db81d95a1b932cd71eeb 100644 (file)
#if defined(SBL_ENABLE_HLOS_BOOT) && (defined(SOC_J721E) || defined(SOC_J7200))
cpu_core_id_t core_id;
#endif
+ uint32_t isBuildHs;
SBL_ADD_PROFILE_POINT;
/* Any SoC specific Init. */
- SBL_SocEarlyInit();
+#if defined (SBL_BUILD_HS)
+ isBuildHs = TRUE;
+#else
+ isBuildHs = FALSE;
+#endif
+ SBL_SocEarlyInit(isBuildHs);
if (SBL_LOG_LEVEL > SBL_LOG_ERR)
{
index afa9397ae66dd5cf745a45fe6c44f9e5313fc626..b930f8aca7e8669d0ef5044b44303e8f01661f1e 100644 (file)
ifeq ($(HLOS_BOOT),yes)
SBL_CFLAGS += -DSBL_ENABLE_HLOS_BOOT -DSBL_HLOS_OWNS_FLASH
endif
-
+ifeq ($(BUILD_HS),yes)
+ SBL_CFLAGS += -DSBL_BUILD_HS
+endif
# BOOTMODE specific CFLAGS
ifeq ($(BOOTMODE), mmcsd)
SBL_CFLAGS += -DBOOT_MMCSD
index 261d55877ad337f861bfea92bb0159cafe9beb86..81aadc4d1d70807097970f62c1cbd352ec2d36f1 100644 (file)
*/
#include <stdint.h>
+#include <ti/csl/cslr.h>
#if defined(SOC_J721E)
/* NAVSS North Bridge (NB) */
-#define NAVSS0_NBSS_NB0_CFG_MMRS 0x3802000
-#define NAVSS0_NBSS_NB1_CFG_MMRS 0x3803000
-#define NAVSS0_NBSS_NB0_CFG_NB_THREADMAP (NAVSS0_NBSS_NB0_CFG_MMRS + 0x10)
-#define NAVSS0_NBSS_NB1_CFG_NB_THREADMAP (NAVSS0_NBSS_NB1_CFG_MMRS + 0x10)
+#define NAVSS0_NBSS_NB0_CFG_MMRS 0x3802000
+#define NAVSS0_NBSS_NB1_CFG_MMRS 0x3803000
+#define NAVSS0_NBSS_NB0_CFG_NB_THREADMAP (NAVSS0_NBSS_NB0_CFG_MMRS + 0x10)
+#define NAVSS0_NBSS_NB1_CFG_NB_THREADMAP (NAVSS0_NBSS_NB1_CFG_MMRS + 0x10)
/* CBASS */
-#define QOS_C66SS0_MDMA 0x45d81000
-#define QOS_C66SS0_MDMA_NUM_J_CH 3
-#define QOS_C66SS0_MDMA_NUM_I_CH 1
-#define QOS_C66SS0_MDMA_CBASS_GRP_MAP1(j) (QOS_C66SS0_MDMA + 0x0 + (j) * 8)
-#define QOS_C66SS0_MDMA_CBASS_GRP_MAP2(j) (QOS_C66SS0_MDMA + 0x4 + (j) * 8)
-#define QOS_C66SS0_MDMA_CBASS_MAP(i) (QOS_C66SS0_MDMA + 0x100 + (i) * 4)
-
-#define QOS_C66SS1_MDMA 0x45d81400
-#define QOS_C66SS1_MDMA_NUM_J_CH 3
-#define QOS_C66SS1_MDMA_NUM_I_CH 1
-#define QOS_C66SS1_MDMA_CBASS_GRP_MAP1(j) (QOS_C66SS1_MDMA + 0x0 + (j) * 8)
-#define QOS_C66SS1_MDMA_CBASS_GRP_MAP2(j) (QOS_C66SS1_MDMA + 0x4 + (j) * 8)
-#define QOS_C66SS1_MDMA_CBASS_MAP(i) (QOS_C66SS1_MDMA + 0x100 + (i) * 4)
-
-#define QOS_R5FSS0_CORE0_MEM_RD 0x45d84000
-#define QOS_R5FSS0_CORE0_MEM_RD_NUM_J_CH 3
-#define QOS_R5FSS0_CORE0_MEM_RD_NUM_I_CH 1
+#define QOS_C66SS0_MDMA 0x45d81000
+#define QOS_C66SS0_MDMA_NUM_J_CH 3
+#define QOS_C66SS0_MDMA_NUM_I_CH 1
+#define QOS_C66SS0_MDMA_CBASS_GRP_MAP1(j) (QOS_C66SS0_MDMA + 0x0 + (j) * 8)
+#define QOS_C66SS0_MDMA_CBASS_GRP_MAP2(j) (QOS_C66SS0_MDMA + 0x4 + (j) * 8)
+#define QOS_C66SS0_MDMA_CBASS_MAP(i) (QOS_C66SS0_MDMA + 0x100 + (i) * 4)
+
+#define QOS_C66SS1_MDMA 0x45d81400
+#define QOS_C66SS1_MDMA_NUM_J_CH 3
+#define QOS_C66SS1_MDMA_NUM_I_CH 1
+#define QOS_C66SS1_MDMA_CBASS_GRP_MAP1(j) (QOS_C66SS1_MDMA + 0x0 + (j) * 8)
+#define QOS_C66SS1_MDMA_CBASS_GRP_MAP2(j) (QOS_C66SS1_MDMA + 0x4 + (j) * 8)
+#define QOS_C66SS1_MDMA_CBASS_MAP(i) (QOS_C66SS1_MDMA + 0x100 + (i) * 4)
+
+#define QOS_R5FSS0_CORE0_MEM_RD 0x45d84000
+#define QOS_R5FSS0_CORE0_MEM_RD_NUM_J_CH 3
+#define QOS_R5FSS0_CORE0_MEM_RD_NUM_I_CH 1
#define QOS_R5FSS0_CORE0_MEM_RD_CBASS_GRP_MAP1(j) (QOS_R5FSS0_CORE0_MEM_RD + 0x0 + (j) * 8)
#define QOS_R5FSS0_CORE0_MEM_RD_CBASS_GRP_MAP2(j) (QOS_R5FSS0_CORE0_MEM_RD + 0x4 + (j) * 8)
-#define QOS_R5FSS0_CORE0_MEM_RD_CBASS_MAP(i) (QOS_R5FSS0_CORE0_MEM_RD + 0x100 + (i) * 4)
+#define QOS_R5FSS0_CORE0_MEM_RD_CBASS_MAP(i) (QOS_R5FSS0_CORE0_MEM_RD + 0x100 + (i) * 4)
-#define QOS_R5FSS0_CORE1_MEM_RD 0x45d84400
-#define QOS_R5FSS0_CORE1_MEM_RD_NUM_J_CH 3
-#define QOS_R5FSS0_CORE1_MEM_RD_NUM_I_CH 1
+#define QOS_R5FSS0_CORE1_MEM_RD 0x45d84400
+#define QOS_R5FSS0_CORE1_MEM_RD_NUM_J_CH 3
+#define QOS_R5FSS0_CORE1_MEM_RD_NUM_I_CH 1
#define QOS_R5FSS0_CORE1_MEM_RD_CBASS_GRP_MAP1(j) (QOS_R5FSS0_CORE1_MEM_RD + 0x0 + (j) * 8)
#define QOS_R5FSS0_CORE1_MEM_RD_CBASS_GRP_MAP2(j) (QOS_R5FSS0_CORE1_MEM_RD + 0x4 + (j) * 8)
-#define QOS_R5FSS0_CORE1_MEM_RD_CBASS_MAP(i) (QOS_R5FSS0_CORE1_MEM_RD + 0x100 + (i) * 4)
+#define QOS_R5FSS0_CORE1_MEM_RD_CBASS_MAP(i) (QOS_R5FSS0_CORE1_MEM_RD + 0x100 + (i) * 4)
-#define QOS_R5FSS0_CORE0_MEM_WR 0x45d84800
-#define QOS_R5FSS0_CORE0_MEM_WR_NUM_J_CH 3
-#define QOS_R5FSS0_CORE0_MEM_WR_NUM_I_CH 1
+#define QOS_R5FSS0_CORE0_MEM_WR 0x45d84800
+#define QOS_R5FSS0_CORE0_MEM_WR_NUM_J_CH 3
+#define QOS_R5FSS0_CORE0_MEM_WR_NUM_I_CH 1
#define QOS_R5FSS0_CORE0_MEM_WR_CBASS_GRP_MAP1(j) (QOS_R5FSS0_CORE0_MEM_WR + 0x0 + (j) * 8)
#define QOS_R5FSS0_CORE0_MEM_WR_CBASS_GRP_MAP2(j) (QOS_R5FSS0_CORE0_MEM_WR + 0x4 + (j) * 8)
-#define QOS_R5FSS0_CORE0_MEM_WR_CBASS_MAP(i) (QOS_R5FSS0_CORE0_MEM_WR + 0x100 + (i) * 4)
+#define QOS_R5FSS0_CORE0_MEM_WR_CBASS_MAP(i) (QOS_R5FSS0_CORE0_MEM_WR + 0x100 + (i) * 4)
-#define QOS_R5FSS0_CORE1_MEM_WR 0x45d84C00
-#define QOS_R5FSS0_CORE1_MEM_WR_NUM_J_CH 3
-#define QOS_R5FSS0_CORE1_MEM_WR_NUM_I_CH 1
+#define QOS_R5FSS0_CORE1_MEM_WR 0x45d84C00
+#define QOS_R5FSS0_CORE1_MEM_WR_NUM_J_CH 3
+#define QOS_R5FSS0_CORE1_MEM_WR_NUM_I_CH 1
#define QOS_R5FSS0_CORE1_MEM_WR_CBASS_GRP_MAP1(j) (QOS_R5FSS0_CORE1_MEM_WR + 0x0 + (j) * 8)
#define QOS_R5FSS0_CORE1_MEM_WR_CBASS_GRP_MAP2(j) (QOS_R5FSS0_CORE1_MEM_WR + 0x4 + (j) * 8)
-#define QOS_R5FSS0_CORE1_MEM_WR_CBASS_MAP(i) (QOS_R5FSS0_CORE1_MEM_WR + 0x100 + (i) * 4)
-
-#define QOS_ENCODER0_WR 0x45dc1000
-#define QOS_ENCODER0_WR_NUM_J_CH 2
-#define QOS_ENCODER0_WR_NUM_I_CH 5
-#define QOS_ENCODER0_WR_CBASS_GRP_MAP1(j) (QOS_ENCODER0_WR + 0x0 + (j) * 8)
-#define QOS_ENCODER0_WR_CBASS_GRP_MAP2(j) (QOS_ENCODER0_WR + 0x4 + (j) * 8)
-#define QOS_ENCODER0_WR_CBASS_MAP(i) (QOS_ENCODER0_WR + 0x100 + (i) * 4)
-
-#define QOS_DECODER0_RD 0x45dc0400
-#define QOS_DECODER0_RD_NUM_J_CH 2
-#define QOS_DECODER0_RD_NUM_I_CH 1
-#define QOS_DECODER0_RD_CBASS_GRP_MAP1(j) (QOS_DECODER0_RD + 0x0 + (j) * 8)
-#define QOS_DECODER0_RD_CBASS_GRP_MAP2(j) (QOS_DECODER0_RD + 0x4 + (j) * 8)
-#define QOS_DECODER0_RD_CBASS_MAP(i) (QOS_DECODER0_RD + 0x100 + (i) * 4)
-
-#define QOS_DECODER0_WR 0x45dc0800
-#define QOS_DECODER0_WR_NUM_J_CH 2
-#define QOS_DECODER0_WR_NUM_I_CH 1
-#define QOS_DECODER0_WR_CBASS_GRP_MAP1(j) (QOS_DECODER0_WR + 0x0 + (j) * 8)
-#define QOS_DECODER0_WR_CBASS_GRP_MAP2(j) (QOS_DECODER0_WR + 0x4 + (j) * 8)
-#define QOS_DECODER0_WR_CBASS_MAP(i) (QOS_DECODER0_WR + 0x100 + (i) * 4)
-
-#define QOS_VPAC0_DATA0 0x45dc1500
-#define QOS_VPAC0_DATA0_NUM_I_CH 32
-#define QOS_VPAC0_DATA0_CBASS_MAP(i) (QOS_VPAC0_DATA0 + (i) * 4)
-
-#define QOS_DMPAC0_DATA 0x45dc0100
-#define QOS_DMPAC0_DATA_NUM_I_CH 32
-#define QOS_DMPAC0_DATA_CBASS_MAP(i) (QOS_DMPAC0_DATA + (i) * 4)
-
-#define QOS_ENCODER0_RD 0x45dc0c00
-#define QOS_ENCODER0_RD_NUM_J_CH 2
-#define QOS_ENCODER0_RD_NUM_I_CH 5
-#define QOS_ENCODER0_RD_CBASS_GRP_MAP1(j) (QOS_ENCODER0_RD + 0x0 + (j) * 8)
-#define QOS_ENCODER0_RD_CBASS_GRP_MAP2(j) (QOS_ENCODER0_RD + 0x4 + (j) * 8)
-#define QOS_ENCODER0_RD_CBASS_MAP(i) (QOS_ENCODER0_RD + 0x100 + (i) * 4)
-
-#define QOS_VPAC0_DATA1 0x45dc1900
-#define QOS_VPAC0_DATA1_NUM_I_CH 64
-#define QOS_VPAC0_DATA1_CBASS_MAP(i) (QOS_VPAC0_DATA1 + (i) * 4)
-
-#define QOS_VPAC0_LDC0 0x45dc1c00
-#define QOS_VPAC0_LDC0_NUM_J_CH 2
-#define QOS_VPAC0_LDC0_NUM_I_CH 3
-#define QOS_VPAC0_LDC0_CBASS_GRP_MAP1(j) (QOS_VPAC0_LDC0 + 0x0 + (j) * 8)
-#define QOS_VPAC0_LDC0_CBASS_GRP_MAP2(j) (QOS_VPAC0_LDC0 + 0x4 + (j) * 8)
-#define QOS_VPAC0_LDC0_CBASS_MAP(i) (QOS_VPAC0_LDC0 + 0x100 + (i) * 4)
-
-#define QOS_DSS0_DMA 0x45dc2000
-#define QOS_DSS0_DMA_NUM_J_CH 2
-#define QOS_DSS0_DMA_NUM_I_CH 10
-#define QOS_DSS0_DMA_CBASS_GRP_MAP1(j) (QOS_DSS0_DMA + 0x0 + (j) * 8)
-#define QOS_DSS0_DMA_CBASS_GRP_MAP2(j) (QOS_DSS0_DMA + 0x4 + (j) * 8)
-#define QOS_DSS0_DMA_CBASS_MAP(i) (QOS_DSS0_DMA + 0x100 + (i) * 4)
-
-#define QOS_DSS0_FBDC 0x45dc2400
-#define QOS_DSS0_FBDC_NUM_J_CH 2
-#define QOS_DSS0_FBDC_NUM_I_CH 10
-#define QOS_DSS0_FBDC_CBASS_GRP_MAP1(j) (QOS_DSS0_FBDC + 0x0 + (j) * 8)
-#define QOS_DSS0_FBDC_CBASS_GRP_MAP2(j) (QOS_DSS0_FBDC + 0x4 + (j) * 8)
-#define QOS_DSS0_FBDC_CBASS_MAP(i) (QOS_DSS0_FBDC + 0x100 + (i) * 4)
-
-#define QOS_GPU0_M0_RD 0x45dc5000
-#define QOS_GPU0_M0_RD_NUM_J_CH 2
-#define QOS_GPU0_M0_RD_NUM_I_CH 48
-#define QOS_GPU0_M0_RD_CBASS_GRP_MAP1(j) (QOS_GPU0_M0_RD + 0x0 + (j) * 8)
-#define QOS_GPU0_M0_RD_CBASS_GRP_MAP2(j) (QOS_GPU0_M0_RD + 0x4 + (j) * 8)
-#define QOS_GPU0_M0_RD_CBASS_MAP(i) (QOS_GPU0_M0_RD + 0x100 + (i) * 4)
-
-#define QOS_GPU0_M0_WR 0x45dc5800
-#define QOS_GPU0_M0_WR_NUM_J_CH 2
-#define QOS_GPU0_M0_WR_NUM_I_CH 48
-#define QOS_GPU0_M0_WR_CBASS_GRP_MAP1(j) (QOS_GPU0_M0_WR + 0x0 + (j) * 8)
-#define QOS_GPU0_M0_WR_CBASS_GRP_MAP2(j) (QOS_GPU0_M0_WR + 0x4 + (j) * 8)
-#define QOS_GPU0_M0_WR_CBASS_MAP(i) (QOS_GPU0_M0_WR + 0x100 + (i) * 4)
-
-#define QOS_GPU0_M1_RD 0x45dc6000
-#define QOS_GPU0_M1_RD_NUM_J_CH 2
-#define QOS_GPU0_M1_RD_NUM_I_CH 48
-#define QOS_GPU0_M1_RD_CBASS_GRP_MAP1(j) (QOS_GPU0_M1_RD + 0x0 + (j) * 8)
-#define QOS_GPU0_M1_RD_CBASS_GRP_MAP2(j) (QOS_GPU0_M1_RD + 0x4 + (j) * 8)
-#define QOS_GPU0_M1_RD_CBASS_MAP(i) (QOS_GPU0_M1_RD + 0x100 + (i) * 4)
-
-#define QOS_GPU0_M1_WR 0x45dc6800
-#define QOS_GPU0_M1_WR_NUM_J_CH 2
-#define QOS_GPU0_M1_WR_NUM_I_CH 48
-#define QOS_GPU0_M1_WR_CBASS_GRP_MAP1(j) (QOS_GPU0_M1_WR + 0x0 + (j) * 8)
-#define QOS_GPU0_M1_WR_CBASS_GRP_MAP2(j) (QOS_GPU0_M1_WR + 0x4 + (j) * 8)
-#define QOS_GPU0_M1_WR_CBASS_MAP(i) (QOS_GPU0_M1_WR + 0x100 + (i) * 4)
-
-#define QOS_MMC0_RD_CBASS_MAP(i) (0x45d9a100 + (i) * 4)
-#define QOS_MMC0_WR_CBASS_MAP(i) (0x45d9a500 + (i) * 4)
-#define QOS_MMC1_RD_CBASS_MAP(i) (0x45d82100 + (i) * 4)
-#define QOS_MMC1_WR_CBASS_MAP(i) (0x45d82500 + (i) * 4)
-
-#define QOS_D5520_RD_CBASS_MAP(i) (0x45dc0500 + (i) * 4)
-#define QOS_D5520_WR_CBASS_MAP(i) (0x45dc0900 + (i) * 4)
-
-#define writel(x,y) (*((uint32_t *)(y))=(x))
+#define QOS_R5FSS0_CORE1_MEM_WR_CBASS_MAP(i) (QOS_R5FSS0_CORE1_MEM_WR + 0x100 + (i) * 4)
+
+#define QOS_ENCODER0_WR 0x45dc1000
+#define QOS_ENCODER0_WR_NUM_J_CH 2
+#define QOS_ENCODER0_WR_NUM_I_CH 5
+#define QOS_ENCODER0_WR_CBASS_GRP_MAP1(j) (QOS_ENCODER0_WR + 0x0 + (j) * 8)
+#define QOS_ENCODER0_WR_CBASS_GRP_MAP2(j) (QOS_ENCODER0_WR + 0x4 + (j) * 8)
+#define QOS_ENCODER0_WR_CBASS_MAP(i) (QOS_ENCODER0_WR + 0x100 + (i) * 4)
+
+#define QOS_DECODER0_RD 0x45dc0400
+#define QOS_DECODER0_RD_NUM_J_CH 2
+#define QOS_DECODER0_RD_NUM_I_CH 1
+#define QOS_DECODER0_RD_CBASS_GRP_MAP1(j) (QOS_DECODER0_RD + 0x0 + (j) * 8)
+#define QOS_DECODER0_RD_CBASS_GRP_MAP2(j) (QOS_DECODER0_RD + 0x4 + (j) * 8)
+#define QOS_DECODER0_RD_CBASS_MAP(i) (QOS_DECODER0_RD + 0x100 + (i) * 4)
+
+#define QOS_DECODER0_WR 0x45dc0800
+#define QOS_DECODER0_WR_NUM_J_CH 2
+#define QOS_DECODER0_WR_NUM_I_CH 1
+#define QOS_DECODER0_WR_CBASS_GRP_MAP1(j) (QOS_DECODER0_WR + 0x0 + (j) * 8)
+#define QOS_DECODER0_WR_CBASS_GRP_MAP2(j) (QOS_DECODER0_WR + 0x4 + (j) * 8)
+#define QOS_DECODER0_WR_CBASS_MAP(i) (QOS_DECODER0_WR + 0x100 + (i) * 4)
+
+#define QOS_VPAC0_DATA0 0x45dc1500
+#define QOS_VPAC0_DATA0_NUM_I_CH 32
+#define QOS_VPAC0_DATA0_CBASS_MAP(i) (QOS_VPAC0_DATA0 + (i) * 4)
+
+#define QOS_DMPAC0_DATA 0x45dc0100
+#define QOS_DMPAC0_DATA_NUM_I_CH 32
+#define QOS_DMPAC0_DATA_CBASS_MAP(i) (QOS_DMPAC0_DATA + (i) * 4)
+
+#define QOS_ENCODER0_RD 0x45dc0c00
+#define QOS_ENCODER0_RD_NUM_J_CH 2
+#define QOS_ENCODER0_RD_NUM_I_CH 5
+#define QOS_ENCODER0_RD_CBASS_GRP_MAP1(j) (QOS_ENCODER0_RD + 0x0 + (j) * 8)
+#define QOS_ENCODER0_RD_CBASS_GRP_MAP2(j) (QOS_ENCODER0_RD + 0x4 + (j) * 8)
+#define QOS_ENCODER0_RD_CBASS_MAP(i) (QOS_ENCODER0_RD + 0x100 + (i) * 4)
+
+#define QOS_VPAC0_DATA1 0x45dc1900
+#define QOS_VPAC0_DATA1_NUM_I_CH 64
+#define QOS_VPAC0_DATA1_CBASS_MAP(i) (QOS_VPAC0_DATA1 + (i) * 4)
+
+#define QOS_VPAC0_LDC0 0x45dc1c00
+#define QOS_VPAC0_LDC0_NUM_J_CH 2
+#define QOS_VPAC0_LDC0_NUM_I_CH 3
+#define QOS_VPAC0_LDC0_CBASS_GRP_MAP1(j) (QOS_VPAC0_LDC0 + 0x0 + (j) * 8)
+#define QOS_VPAC0_LDC0_CBASS_GRP_MAP2(j) (QOS_VPAC0_LDC0 + 0x4 + (j) * 8)
+#define QOS_VPAC0_LDC0_CBASS_MAP(i) (QOS_VPAC0_LDC0 + 0x100 + (i) * 4)
+
+#define QOS_DSS0_DMA 0x45dc2000
+#define QOS_DSS0_DMA_NUM_J_CH 2
+#define QOS_DSS0_DMA_NUM_I_CH 10
+#define QOS_DSS0_DMA_CBASS_GRP_MAP1(j) (QOS_DSS0_DMA + 0x0 + (j) * 8)
+#define QOS_DSS0_DMA_CBASS_GRP_MAP2(j) (QOS_DSS0_DMA + 0x4 + (j) * 8)
+#define QOS_DSS0_DMA_CBASS_MAP(i) (QOS_DSS0_DMA + 0x100 + (i) * 4)
+
+#define QOS_DSS0_FBDC 0x45dc2400
+#define QOS_DSS0_FBDC_NUM_J_CH 2
+#define QOS_DSS0_FBDC_NUM_I_CH 10
+#define QOS_DSS0_FBDC_CBASS_GRP_MAP1(j) (QOS_DSS0_FBDC + 0x0 + (j) * 8)
+#define QOS_DSS0_FBDC_CBASS_GRP_MAP2(j) (QOS_DSS0_FBDC + 0x4 + (j) * 8)
+#define QOS_DSS0_FBDC_CBASS_MAP(i) (QOS_DSS0_FBDC + 0x100 + (i) * 4)
+
+#define QOS_GPU0_M0_RD 0x45dc5000
+#define QOS_GPU0_M0_RD_NUM_J_CH 2
+#define QOS_GPU0_M0_RD_NUM_I_CH 48
+#define QOS_GPU0_M0_RD_CBASS_GRP_MAP1(j) (QOS_GPU0_M0_RD + 0x0 + (j) * 8)
+#define QOS_GPU0_M0_RD_CBASS_GRP_MAP2(j) (QOS_GPU0_M0_RD + 0x4 + (j) * 8)
+#define QOS_GPU0_M0_RD_CBASS_MAP(i) (QOS_GPU0_M0_RD + 0x100 + (i) * 4)
+
+#define QOS_GPU0_M0_WR 0x45dc5800
+#define QOS_GPU0_M0_WR_NUM_J_CH 2
+#define QOS_GPU0_M0_WR_NUM_I_CH 48
+#define QOS_GPU0_M0_WR_CBASS_GRP_MAP1(j) (QOS_GPU0_M0_WR + 0x0 + (j) * 8)
+#define QOS_GPU0_M0_WR_CBASS_GRP_MAP2(j) (QOS_GPU0_M0_WR + 0x4 + (j) * 8)
+#define QOS_GPU0_M0_WR_CBASS_MAP(i) (QOS_GPU0_M0_WR + 0x100 + (i) * 4)
+
+#define QOS_GPU0_M1_RD 0x45dc6000
+#define QOS_GPU0_M1_RD_NUM_J_CH 2
+#define QOS_GPU0_M1_RD_NUM_I_CH 48
+#define QOS_GPU0_M1_RD_CBASS_GRP_MAP1(j) (QOS_GPU0_M1_RD + 0x0 + (j) * 8)
+#define QOS_GPU0_M1_RD_CBASS_GRP_MAP2(j) (QOS_GPU0_M1_RD + 0x4 + (j) * 8)
+#define QOS_GPU0_M1_RD_CBASS_MAP(i) (QOS_GPU0_M1_RD + 0x100 + (i) * 4)
+
+#define QOS_GPU0_M1_WR 0x45dc6800
+#define QOS_GPU0_M1_WR_NUM_J_CH 2
+#define QOS_GPU0_M1_WR_NUM_I_CH 48
+#define QOS_GPU0_M1_WR_CBASS_GRP_MAP1(j) (QOS_GPU0_M1_WR + 0x0 + (j) * 8)
+#define QOS_GPU0_M1_WR_CBASS_GRP_MAP2(j) (QOS_GPU0_M1_WR + 0x4 + (j) * 8)
+#define QOS_GPU0_M1_WR_CBASS_MAP(i) (QOS_GPU0_M1_WR + 0x100 + (i) * 4)
+
+#define QOS_MMC0_RD_CBASS_MAP(i) (0x45d9a100 + (i) * 4)
+#define QOS_MMC0_WR_CBASS_MAP(i) (0x45d9a500 + (i) * 4)
+#define QOS_MMC1_RD_CBASS_MAP(i) (0x45d82100 + (i) * 4)
+#define QOS_MMC1_WR_CBASS_MAP(i) (0x45d82500 + (i) * 4)
+
+#define QOS_D5520_RD_CBASS_MAP(i) (0x45dc0500 + (i) * 4)
+#define QOS_D5520_WR_CBASS_MAP(i) (0x45dc0900 + (i) * 4)
#define QOS_C66SS0_MDMA_ATYPE (0U)
#define QOS_C66SS1_MDMA_ATYPE (0U)
void setup_navss_nb(void)
{
/* Map orderid 8-15 to VBUSM.C thread 2 (real-time traffic) */
- writel(2, NAVSS0_NBSS_NB0_CFG_NB_THREADMAP);
- writel(2, NAVSS0_NBSS_NB1_CFG_NB_THREADMAP);
+ CSL_REG32_WR(NAVSS0_NBSS_NB0_CFG_NB_THREADMAP, 2);
+ CSL_REG32_WR(NAVSS0_NBSS_NB1_CFG_NB_THREADMAP, 2);
}
void setup_vpac_qos(void)
{
- unsigned int channel, group;
-
- /* vpac data master 0 */
- for (channel = 0; channel < QOS_VPAC0_DATA0_NUM_I_CH; ++channel) {
-
- writel((QOS_VPAC0_DATA0_ATYPE << 28), QOS_VPAC0_DATA0_CBASS_MAP(channel));
- }
-
- /* vpac data master 1 */
- for (channel = 0; channel < QOS_VPAC0_DATA1_NUM_I_CH; ++channel) {
-
- writel((QOS_VPAC0_DATA1_ATYPE << 28), QOS_VPAC0_DATA1_CBASS_MAP(channel));
- }
-
- /* vpac ldc0 */
- for (group = 0; group < QOS_VPAC0_LDC0_NUM_J_CH; ++group) {
- writel(0x76543210, QOS_VPAC0_LDC0_CBASS_GRP_MAP1(group));
- writel(0xfedcba98, QOS_VPAC0_LDC0_CBASS_GRP_MAP2(group));
- }
-
- for (channel = 0; channel < QOS_VPAC0_LDC0_NUM_I_CH; ++channel) {
-
- writel((QOS_VPAC0_LDC0_ATYPE << 28) | (QOS_VPAC0_LDC0_PRIORITY << 12) | (QOS_VPAC0_LDC0_ORDER_ID << 4), QOS_VPAC0_LDC0_CBASS_MAP(channel));
- }
+ unsigned int channel, group;
+
+ /* vpac data master 0 */
+ for (channel = 0; channel < QOS_VPAC0_DATA0_NUM_I_CH; ++channel)
+ {
+ CSL_REG32_WR(QOS_VPAC0_DATA0_CBASS_MAP(channel), (QOS_VPAC0_DATA0_ATYPE << 28));
+ }
+
+ /* vpac data master 1 */
+ for (channel = 0; channel < QOS_VPAC0_DATA1_NUM_I_CH; ++channel)
+ {
+ CSL_REG32_WR(QOS_VPAC0_DATA1_CBASS_MAP(channel), (QOS_VPAC0_DATA1_ATYPE << 28));
+ }
+
+ /* vpac ldc0 */
+ for (group = 0; group < QOS_VPAC0_LDC0_NUM_J_CH; ++group)
+ {
+ CSL_REG32_WR(QOS_VPAC0_LDC0_CBASS_GRP_MAP1(group), 0x76543210);
+ CSL_REG32_WR(QOS_VPAC0_LDC0_CBASS_GRP_MAP2(group), 0xfedcba98);
+ }
+
+ for (channel = 0; channel < QOS_VPAC0_LDC0_NUM_I_CH; ++channel)
+ {
+ CSL_REG32_WR(QOS_VPAC0_LDC0_CBASS_MAP(channel), (QOS_VPAC0_LDC0_ATYPE << 28) | (QOS_VPAC0_LDC0_PRIORITY << 12) | (QOS_VPAC0_LDC0_ORDER_ID << 4));
+ }
}
void setup_dmpac_qos(void)
{
- unsigned int channel;
-
- /* dmpac data */
- for (channel = 0; channel < QOS_DMPAC0_DATA_NUM_I_CH; ++channel) {
+ unsigned int channel;
- writel((QOS_DMPAC0_DATA_ATYPE << 28), QOS_DMPAC0_DATA_CBASS_MAP(channel));
- }
+ /* dmpac data */
+ for (channel = 0; channel < QOS_DMPAC0_DATA_NUM_I_CH; ++channel)
+ {
+ CSL_REG32_WR(QOS_DMPAC0_DATA_CBASS_MAP(channel), (QOS_DMPAC0_DATA_ATYPE << 28));
+ }
}
void setup_dss_qos(void)
{
- unsigned int channel, group;
-
- /* two master ports: dma and fbdc */
- /* two groups: SRAM and DDR */
- /* 10 channels: (pipe << 1) | is_second_buffer */
-
- /* master port 1 (dma) */
- for (group = 0; group < QOS_DSS0_DMA_NUM_J_CH; ++group) {
- writel(0x76543210, QOS_DSS0_DMA_CBASS_GRP_MAP1(group));
- writel(0xfedcba98, QOS_DSS0_DMA_CBASS_GRP_MAP2(group));
- }
-
- for (channel = 0; channel < QOS_DSS0_DMA_NUM_I_CH; ++channel) {
-
- writel((QOS_DSS0_DMA_ATYPE << 28) | (QOS_DSS0_DMA_PRIORITY << 12) | (QOS_DSS0_DMA_ORDER_ID << 4), QOS_DSS0_DMA_CBASS_MAP(channel));
- }
-
- /* master port 2 (fbdc) */
- for (group = 0; group < QOS_DSS0_FBDC_NUM_J_CH; ++group) {
- writel(0x76543210, QOS_DSS0_FBDC_CBASS_GRP_MAP1(group));
- writel(0xfedcba98, QOS_DSS0_FBDC_CBASS_GRP_MAP2(group));
- }
-
- for (channel = 0; channel < QOS_DSS0_FBDC_NUM_I_CH; ++channel) {
-
- writel((QOS_DSS0_FBDC_ATYPE << 28) | (QOS_DSS0_FBDC_PRIORITY << 12) | (QOS_DSS0_FBDC_ORDER_ID << 4), QOS_DSS0_FBDC_CBASS_MAP(channel));
- }
+ unsigned int channel, group;
+
+ /* two master ports: dma and fbdc */
+ /* two groups: SRAM and DDR */
+ /* 10 channels: (pipe << 1) | is_second_buffer */
+
+ /* master port 1 (dma) */
+ for (group = 0; group < QOS_DSS0_DMA_NUM_J_CH; ++group)
+ {
+ CSL_REG32_WR(QOS_DSS0_DMA_CBASS_GRP_MAP1(group), 0x76543210);
+ CSL_REG32_WR(QOS_DSS0_DMA_CBASS_GRP_MAP2(group), 0xfedcba98);
+ }
+
+ for (channel = 0; channel < QOS_DSS0_DMA_NUM_I_CH; ++channel)
+ {
+ CSL_REG32_WR(QOS_DSS0_DMA_CBASS_MAP(channel), (QOS_DSS0_DMA_ATYPE << 28) | (QOS_DSS0_DMA_PRIORITY << 12) | (QOS_DSS0_DMA_ORDER_ID << 4));
+ }
+
+ /* master port 2 (fbdc) */
+ for (group = 0; group < QOS_DSS0_FBDC_NUM_J_CH; ++group)
+ {
+ CSL_REG32_WR(QOS_DSS0_FBDC_CBASS_GRP_MAP1(group), 0x76543210);
+ CSL_REG32_WR(QOS_DSS0_FBDC_CBASS_GRP_MAP2(group), 0xfedcba98);
+ }
+
+ for (channel = 0; channel < QOS_DSS0_FBDC_NUM_I_CH; ++channel)
+ {
+ CSL_REG32_WR(QOS_DSS0_FBDC_CBASS_MAP(channel), (QOS_DSS0_FBDC_ATYPE << 28) | (QOS_DSS0_FBDC_PRIORITY << 12) | (QOS_DSS0_FBDC_ORDER_ID << 4));
+ }
}
void setup_gpu_qos(void)
{
- unsigned int channel, group;
-
- /* gpu m0 rd */
- for (group = 0; group < QOS_GPU0_M0_RD_NUM_J_CH; ++group) {
- writel(0x76543210, QOS_GPU0_M0_RD_CBASS_GRP_MAP1(group));
- writel(0xfedcba98, QOS_GPU0_M0_RD_CBASS_GRP_MAP2(group));
- }
-
- for (channel = 0; channel < QOS_GPU0_M0_RD_NUM_I_CH; ++channel) {
-
- if(channel == 0)
- {
- writel((QOS_GPU0_M0_RD_ATYPE << 28) | (QOS_GPU0_M0_RD_MMU_PRIORITY << 12) | (QOS_GPU0_M0_RD_ORDER_ID << 4), QOS_GPU0_M0_RD_CBASS_MAP(channel));
- }
- else
- {
- writel((QOS_GPU0_M0_RD_ATYPE << 28) | (QOS_GPU0_M0_RD_PRIORITY << 12) | (QOS_GPU0_M0_RD_ORDER_ID << 4), QOS_GPU0_M0_RD_CBASS_MAP(channel));
- }
- }
-
- /* gpu m0 wr */
- for (group = 0; group < QOS_GPU0_M0_WR_NUM_J_CH; ++group) {
- writel(0x76543210, QOS_GPU0_M0_WR_CBASS_GRP_MAP1(group));
- writel(0xfedcba98, QOS_GPU0_M0_WR_CBASS_GRP_MAP2(group));
- }
-
- for (channel = 0; channel < QOS_GPU0_M0_WR_NUM_I_CH; ++channel) {
-
- writel((QOS_GPU0_M0_WR_ATYPE << 28) | (QOS_GPU0_M0_WR_PRIORITY << 12) | (QOS_GPU0_M0_WR_ORDER_ID << 4), QOS_GPU0_M0_WR_CBASS_MAP(channel));
- }
-
- /* gpu m1 rd */
- for (group = 0; group < QOS_GPU0_M1_RD_NUM_J_CH; ++group) {
- writel(0x76543210, QOS_GPU0_M1_RD_CBASS_GRP_MAP1(group));
- writel(0xfedcba98, QOS_GPU0_M1_RD_CBASS_GRP_MAP2(group));
- }
-
- for (channel = 0; channel < QOS_GPU0_M1_RD_NUM_I_CH; ++channel) {
-
- if(channel == 0)
- {
- writel((QOS_GPU0_M1_RD_ATYPE << 28) | (QOS_GPU0_M1_RD_MMU_PRIORITY << 12) | (QOS_GPU0_M1_RD_ORDER_ID << 4), QOS_GPU0_M1_RD_CBASS_MAP(channel));
- }
- else
- {
- writel((QOS_GPU0_M1_RD_ATYPE << 28) | (QOS_GPU0_M1_RD_PRIORITY << 12) | (QOS_GPU0_M1_RD_ORDER_ID << 4), QOS_GPU0_M1_RD_CBASS_MAP(channel));
- }
- }
-
- /* gpu m1 wr */
- for (group = 0; group < QOS_GPU0_M1_WR_NUM_J_CH; ++group) {
- writel(0x76543210, QOS_GPU0_M1_WR_CBASS_GRP_MAP1(group));
- writel(0xfedcba98, QOS_GPU0_M1_WR_CBASS_GRP_MAP2(group));
- }
-
- for (channel = 0; channel < QOS_GPU0_M1_WR_NUM_I_CH; ++channel) {
-
- writel((QOS_GPU0_M1_WR_ATYPE << 28) | (QOS_GPU0_M1_WR_PRIORITY << 12) | (QOS_GPU0_M1_WR_ORDER_ID << 4), QOS_GPU0_M1_WR_CBASS_MAP(channel));
- }
+ unsigned int channel, group;
+
+ /* gpu m0 rd */
+ for (group = 0; group < QOS_GPU0_M0_RD_NUM_J_CH; ++group)
+ {
+ CSL_REG32_WR(QOS_GPU0_M0_RD_CBASS_GRP_MAP1(group), 0x76543210);
+ CSL_REG32_WR(QOS_GPU0_M0_RD_CBASS_GRP_MAP2(group), 0xfedcba98);
+ }
+
+ for (channel = 0; channel < QOS_GPU0_M0_RD_NUM_I_CH; ++channel)
+ {
+ if(channel == 0)
+ {
+ CSL_REG32_WR(QOS_GPU0_M0_RD_CBASS_MAP(channel), (QOS_GPU0_M0_RD_ATYPE << 28) | (QOS_GPU0_M0_RD_MMU_PRIORITY << 12) | (QOS_GPU0_M0_RD_ORDER_ID << 4));
+ }
+ else
+ {
+ CSL_REG32_WR(QOS_GPU0_M0_RD_CBASS_MAP(channel), (QOS_GPU0_M0_RD_ATYPE << 28) | (QOS_GPU0_M0_RD_PRIORITY << 12) | (QOS_GPU0_M0_RD_ORDER_ID << 4));
+ }
+ }
+
+ /* gpu m0 wr */
+ for (group = 0; group < QOS_GPU0_M0_WR_NUM_J_CH; ++group)
+ {
+ CSL_REG32_WR(QOS_GPU0_M0_WR_CBASS_GRP_MAP1(group), 0x76543210);
+ CSL_REG32_WR(QOS_GPU0_M0_WR_CBASS_GRP_MAP2(group), 0xfedcba98);
+ }
+
+ for (channel = 0; channel < QOS_GPU0_M0_WR_NUM_I_CH; ++channel)
+ {
+ CSL_REG32_WR(QOS_GPU0_M0_WR_CBASS_MAP(channel), (QOS_GPU0_M0_WR_ATYPE << 28) | (QOS_GPU0_M0_WR_PRIORITY << 12) | (QOS_GPU0_M0_WR_ORDER_ID << 4));
+ }
+
+ /* gpu m1 rd */
+ for (group = 0; group < QOS_GPU0_M1_RD_NUM_J_CH; ++group)
+ {
+ CSL_REG32_WR(QOS_GPU0_M1_RD_CBASS_GRP_MAP1(group), 0x76543210);
+ CSL_REG32_WR(QOS_GPU0_M1_RD_CBASS_GRP_MAP2(group), 0xfedcba98);
+ }
+
+ for (channel = 0; channel < QOS_GPU0_M1_RD_NUM_I_CH; ++channel)
+ {
+ if(channel == 0)
+ {
+ CSL_REG32_WR(QOS_GPU0_M1_RD_CBASS_MAP(channel), (QOS_GPU0_M1_RD_ATYPE << 28) | (QOS_GPU0_M1_RD_MMU_PRIORITY << 12) | (QOS_GPU0_M1_RD_ORDER_ID << 4));
+ }
+ else
+ {
+ CSL_REG32_WR(QOS_GPU0_M1_RD_CBASS_MAP(channel), (QOS_GPU0_M1_RD_ATYPE << 28) | (QOS_GPU0_M1_RD_PRIORITY << 12) | (QOS_GPU0_M1_RD_ORDER_ID << 4));
+ }
+ }
+
+ /* gpu m1 wr */
+ for (group = 0; group < QOS_GPU0_M1_WR_NUM_J_CH; ++group)
+ {
+ CSL_REG32_WR(QOS_GPU0_M1_WR_CBASS_GRP_MAP1(group), 0x76543210);
+ CSL_REG32_WR(QOS_GPU0_M1_WR_CBASS_GRP_MAP2(group), 0xfedcba98);
+ }
+
+ for (channel = 0; channel < QOS_GPU0_M1_WR_NUM_I_CH; ++channel)
+ {
+ CSL_REG32_WR(QOS_GPU0_M1_WR_CBASS_MAP(channel), (QOS_GPU0_M1_WR_ATYPE << 28) | (QOS_GPU0_M1_WR_PRIORITY << 12) | (QOS_GPU0_M1_WR_ORDER_ID << 4));
+ }
}
void setup_encoder_qos(void)
{
- unsigned int channel, group;
-
- /* encoder rd */
- for (group = 0; group < QOS_ENCODER0_RD_NUM_J_CH; ++group) {
- writel(0x76543210, QOS_ENCODER0_RD_CBASS_GRP_MAP1(group));
- writel(0xfedcba98, QOS_ENCODER0_RD_CBASS_GRP_MAP2(group));
- }
-
- for (channel = 0; channel < QOS_ENCODER0_RD_NUM_I_CH; ++channel) {
-
- writel((QOS_ENCODER0_RD_ATYPE << 28) | (QOS_ENCODER0_RD_PRIORITY << 12) | (QOS_ENCODER0_RD_ORDER_ID << 4), QOS_ENCODER0_RD_CBASS_MAP(channel));
- }
-
- /* encoder wr */
- for (group = 0; group < QOS_ENCODER0_WR_NUM_J_CH; ++group) {
- writel(0x76543210, QOS_ENCODER0_WR_CBASS_GRP_MAP1(group));
- writel(0xfedcba98, QOS_ENCODER0_WR_CBASS_GRP_MAP2(group));
- }
-
- for (channel = 0; channel < QOS_ENCODER0_WR_NUM_I_CH; ++channel) {
-
- writel((QOS_ENCODER0_WR_ATYPE << 28) | (QOS_ENCODER0_WR_PRIORITY << 12) | (QOS_ENCODER0_WR_ORDER_ID << 4), QOS_ENCODER0_WR_CBASS_MAP(channel));
- }
+ unsigned int channel, group;
+
+ /* encoder rd */
+ for (group = 0; group < QOS_ENCODER0_RD_NUM_J_CH; ++group)
+ {
+ CSL_REG32_WR(QOS_ENCODER0_RD_CBASS_GRP_MAP1(group), 0x76543210);
+ CSL_REG32_WR(QOS_ENCODER0_RD_CBASS_GRP_MAP2(group), 0xfedcba98);
+ }
+
+ for (channel = 0; channel < QOS_ENCODER0_RD_NUM_I_CH; ++channel)
+ {
+ CSL_REG32_WR(QOS_ENCODER0_RD_CBASS_MAP(channel), (QOS_ENCODER0_RD_ATYPE << 28) | (QOS_ENCODER0_RD_PRIORITY << 12) | (QOS_ENCODER0_RD_ORDER_ID << 4));
+ }
+
+ /* encoder wr */
+ for (group = 0; group < QOS_ENCODER0_WR_NUM_J_CH; ++group)
+ {
+ CSL_REG32_WR(QOS_ENCODER0_WR_CBASS_GRP_MAP1(group), 0x76543210);
+ CSL_REG32_WR(QOS_ENCODER0_WR_CBASS_GRP_MAP2(group), 0xfedcba98);
+ }
+
+ for (channel = 0; channel < QOS_ENCODER0_WR_NUM_I_CH; ++channel)
+ {
+ CSL_REG32_WR(QOS_ENCODER0_WR_CBASS_MAP(channel), (QOS_ENCODER0_WR_ATYPE << 28) | (QOS_ENCODER0_WR_PRIORITY << 12) | (QOS_ENCODER0_WR_ORDER_ID << 4));
+ }
}
void setup_decoder_qos(void)
{
- unsigned int channel, group;
-
- /* decoder rd */
- for (group = 0; group < QOS_DECODER0_RD_NUM_J_CH; ++group) {
- writel(0x76543210, QOS_DECODER0_RD_CBASS_GRP_MAP1(group));
- writel(0xfedcba98, QOS_DECODER0_RD_CBASS_GRP_MAP2(group));
- }
-
- for (channel = 0; channel < QOS_DECODER0_RD_NUM_I_CH; ++channel) {
-
- writel((QOS_DECODER0_RD_ATYPE << 28) | (QOS_DECODER0_RD_PRIORITY << 12) | (QOS_DECODER0_RD_ORDER_ID << 4), QOS_DECODER0_RD_CBASS_MAP(channel));
- }
-
- /* decoder wr */
- for (group = 0; group < QOS_DECODER0_WR_NUM_J_CH; ++group) {
- writel(0x76543210, QOS_DECODER0_WR_CBASS_GRP_MAP1(group));
- writel(0xfedcba98, QOS_DECODER0_WR_CBASS_GRP_MAP2(group));
- }
-
- for (channel = 0; channel < QOS_DECODER0_WR_NUM_I_CH; ++channel) {
-
- writel((QOS_DECODER0_WR_ATYPE << 28) | (QOS_DECODER0_WR_PRIORITY << 12) | (QOS_DECODER0_WR_ORDER_ID << 4), QOS_DECODER0_WR_CBASS_MAP(channel));
- }
+ unsigned int channel, group;
+
+ /* decoder rd */
+ for (group = 0; group < QOS_DECODER0_RD_NUM_J_CH; ++group)
+ {
+ CSL_REG32_WR(QOS_DECODER0_RD_CBASS_GRP_MAP1(group), 0x76543210);
+ CSL_REG32_WR(QOS_DECODER0_RD_CBASS_GRP_MAP2(group), 0xfedcba98);
+ }
+
+ for (channel = 0; channel < QOS_DECODER0_RD_NUM_I_CH; ++channel)
+ {
+ CSL_REG32_WR(QOS_DECODER0_RD_CBASS_MAP(channel), (QOS_DECODER0_RD_ATYPE << 28) | (QOS_DECODER0_RD_PRIORITY << 12) | (QOS_DECODER0_RD_ORDER_ID << 4));
+ }
+
+ /* decoder wr */
+ for (group = 0; group < QOS_DECODER0_WR_NUM_J_CH; ++group)
+ {
+ CSL_REG32_WR(QOS_DECODER0_WR_CBASS_GRP_MAP1(group), 0x76543210);
+ CSL_REG32_WR(QOS_DECODER0_WR_CBASS_GRP_MAP2(group), 0xfedcba98);
+ }
+
+ for (channel = 0; channel < QOS_DECODER0_WR_NUM_I_CH; ++channel)
+ {
+ CSL_REG32_WR(QOS_DECODER0_WR_CBASS_MAP(channel), (QOS_DECODER0_WR_ATYPE << 28) | (QOS_DECODER0_WR_PRIORITY << 12) | (QOS_DECODER0_WR_ORDER_ID << 4));
+ }
}
void setup_c66_qos(void)
{
- unsigned int channel, group;
-
- /* c66_0 mdma */
- for (group = 0; group < QOS_C66SS0_MDMA_NUM_J_CH; ++group) {
- writel(0x76543210, QOS_C66SS0_MDMA_CBASS_GRP_MAP1(group));
- writel(0xfedcba98, QOS_C66SS0_MDMA_CBASS_GRP_MAP2(group));
- }
-
- for (channel = 0; channel < QOS_C66SS0_MDMA_NUM_I_CH; ++channel) {
-
- writel((QOS_C66SS0_MDMA_ATYPE << 28) | (QOS_C66SS0_MDMA_PRIORITY << 12) | (QOS_C66SS0_MDMA_ORDER_ID << 4), QOS_C66SS0_MDMA_CBASS_MAP(channel));
- }
-
- /* c66_1 mdma */
- for (group = 0; group < QOS_C66SS1_MDMA_NUM_J_CH; ++group) {
- writel(0x76543210, QOS_C66SS1_MDMA_CBASS_GRP_MAP1(group));
- writel(0xfedcba98, QOS_C66SS1_MDMA_CBASS_GRP_MAP2(group));
- }
-
- for (channel = 0; channel < QOS_C66SS1_MDMA_NUM_I_CH; ++channel) {
-
- writel((QOS_C66SS1_MDMA_ATYPE << 28) | (QOS_C66SS1_MDMA_PRIORITY << 12) | (QOS_C66SS1_MDMA_ORDER_ID << 4), QOS_C66SS1_MDMA_CBASS_MAP(channel));
- }
+ unsigned int channel, group;
+
+ /* c66_0 mdma */
+ for (group = 0; group < QOS_C66SS0_MDMA_NUM_J_CH; ++group)
+ {
+ CSL_REG32_WR(QOS_C66SS0_MDMA_CBASS_GRP_MAP1(group), 0x76543210);
+ CSL_REG32_WR(QOS_C66SS0_MDMA_CBASS_GRP_MAP2(group), 0xfedcba98);
+ }
+
+ for (channel = 0; channel < QOS_C66SS0_MDMA_NUM_I_CH; ++channel)
+ {
+ CSL_REG32_WR(QOS_C66SS0_MDMA_CBASS_MAP(channel), (QOS_C66SS0_MDMA_ATYPE << 28) | (QOS_C66SS0_MDMA_PRIORITY << 12) | (QOS_C66SS0_MDMA_ORDER_ID << 4));
+ }
+
+ /* c66_1 mdma */
+ for (group = 0; group < QOS_C66SS1_MDMA_NUM_J_CH; ++group)
+ {
+ CSL_REG32_WR(QOS_C66SS1_MDMA_CBASS_GRP_MAP1(group), 0x76543210);
+ CSL_REG32_WR(QOS_C66SS1_MDMA_CBASS_GRP_MAP2(group), 0xfedcba98);
+ }
+
+ for (channel = 0; channel < QOS_C66SS1_MDMA_NUM_I_CH; ++channel)
+ {
+ CSL_REG32_WR(QOS_C66SS1_MDMA_CBASS_MAP(channel), (QOS_C66SS1_MDMA_ATYPE << 28) | (QOS_C66SS1_MDMA_PRIORITY << 12) | (QOS_C66SS1_MDMA_ORDER_ID << 4));
+ }
}
void setup_main_r5f_qos(void)
{
- unsigned int channel, group;
-
- /* R5FSS0 core0 - read */
- for (group = 0; group < QOS_R5FSS0_CORE0_MEM_RD_NUM_J_CH; ++group) {
- writel(0x76543210, QOS_R5FSS0_CORE0_MEM_RD_CBASS_GRP_MAP1(group));
- writel(0xfedcba98, QOS_R5FSS0_CORE0_MEM_RD_CBASS_GRP_MAP2(group));
- }
-
- for (channel = 0; channel < QOS_R5FSS0_CORE0_MEM_RD_NUM_I_CH; ++channel) {
-
- writel((QOS_R5FSS0_CORE0_MEM_RD_ATYPE << 28) | (QOS_R5FSS0_CORE0_MEM_RD_PRIORITY << 12) | (QOS_R5FSS0_CORE0_MEM_RD_ORDER_ID << 4), QOS_R5FSS0_CORE0_MEM_RD_CBASS_MAP(channel));
- }
-
- /* R5FSS0 core0 - write */
- for (group = 0; group < QOS_R5FSS0_CORE0_MEM_WR_NUM_J_CH; ++group) {
- writel(0x76543210, QOS_R5FSS0_CORE0_MEM_WR_CBASS_GRP_MAP1(group));
- writel(0xfedcba98, QOS_R5FSS0_CORE0_MEM_WR_CBASS_GRP_MAP2(group));
- }
-
- for (channel = 0; channel < QOS_R5FSS0_CORE0_MEM_WR_NUM_I_CH; ++channel) {
-
- writel((QOS_R5FSS0_CORE0_MEM_WR_ATYPE << 28) | (QOS_R5FSS0_CORE0_MEM_WR_PRIORITY << 12) | (QOS_R5FSS0_CORE0_MEM_RD_ORDER_ID << 4), QOS_R5FSS0_CORE0_MEM_WR_CBASS_MAP(channel));
- }
-
- /* R5FSS0 core1 - read */
- for (group = 0; group < QOS_R5FSS0_CORE1_MEM_RD_NUM_J_CH; ++group) {
- writel(0x76543210, QOS_R5FSS0_CORE1_MEM_RD_CBASS_GRP_MAP1(group));
- writel(0xfedcba98, QOS_R5FSS0_CORE1_MEM_RD_CBASS_GRP_MAP2(group));
- }
-
- for (channel = 0; channel < QOS_R5FSS0_CORE1_MEM_RD_NUM_I_CH; ++channel) {
-
- writel((QOS_R5FSS0_CORE1_MEM_RD_ATYPE << 28) | (QOS_R5FSS0_CORE1_MEM_RD_PRIORITY << 12) | (QOS_R5FSS0_CORE0_MEM_RD_ORDER_ID << 4), QOS_R5FSS0_CORE1_MEM_RD_CBASS_MAP(channel));
- }
-
- /* R5FSS0 core1 - write */
- for (group = 0; group < QOS_R5FSS0_CORE1_MEM_WR_NUM_J_CH; ++group) {
- writel(0x76543210, QOS_R5FSS0_CORE1_MEM_WR_CBASS_GRP_MAP1(group));
- writel(0xfedcba98, QOS_R5FSS0_CORE1_MEM_WR_CBASS_GRP_MAP2(group));
- }
-
- for (channel = 0; channel < QOS_R5FSS0_CORE1_MEM_WR_NUM_I_CH; ++channel) {
-
- writel((QOS_R5FSS0_CORE1_MEM_WR_ATYPE << 28) | (QOS_R5FSS0_CORE1_MEM_WR_PRIORITY << 12) | (QOS_R5FSS0_CORE1_MEM_RD_ORDER_ID << 4), QOS_R5FSS0_CORE1_MEM_WR_CBASS_MAP(channel));
- }
-
+ unsigned int channel, group;
+
+ /* R5FSS0 core0 - read */
+ for (group = 0; group < QOS_R5FSS0_CORE0_MEM_RD_NUM_J_CH; ++group)
+ {
+ CSL_REG32_WR(QOS_R5FSS0_CORE0_MEM_RD_CBASS_GRP_MAP1(group), 0x76543210);
+ CSL_REG32_WR(QOS_R5FSS0_CORE0_MEM_RD_CBASS_GRP_MAP2(group), 0xfedcba98);
+ }
+
+ for (channel = 0; channel < QOS_R5FSS0_CORE0_MEM_RD_NUM_I_CH; ++channel)
+ {
+ CSL_REG32_WR(QOS_R5FSS0_CORE0_MEM_RD_CBASS_MAP(channel), (QOS_R5FSS0_CORE0_MEM_RD_ATYPE << 28) | (QOS_R5FSS0_CORE0_MEM_RD_PRIORITY << 12) | (QOS_R5FSS0_CORE0_MEM_RD_ORDER_ID << 4));
+ }
+
+ /* R5FSS0 core0 - write */
+ for (group = 0; group < QOS_R5FSS0_CORE0_MEM_WR_NUM_J_CH; ++group)
+ {
+ CSL_REG32_WR(QOS_R5FSS0_CORE0_MEM_WR_CBASS_GRP_MAP1(group), 0x76543210);
+ CSL_REG32_WR(QOS_R5FSS0_CORE0_MEM_WR_CBASS_GRP_MAP2(group), 0xfedcba98);
+ }
+
+ for (channel = 0; channel < QOS_R5FSS0_CORE0_MEM_WR_NUM_I_CH; ++channel)
+ {
+ CSL_REG32_WR(QOS_R5FSS0_CORE0_MEM_WR_CBASS_MAP(channel), (QOS_R5FSS0_CORE0_MEM_WR_ATYPE << 28) | (QOS_R5FSS0_CORE0_MEM_WR_PRIORITY << 12) | (QOS_R5FSS0_CORE0_MEM_RD_ORDER_ID << 4));
+ }
+
+ /* R5FSS0 core1 - read */
+ for (group = 0; group < QOS_R5FSS0_CORE1_MEM_RD_NUM_J_CH; ++group)
+ {
+ CSL_REG32_WR(QOS_R5FSS0_CORE1_MEM_RD_CBASS_GRP_MAP1(group), 0x76543210);
+ CSL_REG32_WR(QOS_R5FSS0_CORE1_MEM_RD_CBASS_GRP_MAP2(group), 0xfedcba98);
+ }
+
+ for (channel = 0; channel < QOS_R5FSS0_CORE1_MEM_RD_NUM_I_CH; ++channel)
+ {
+ CSL_REG32_WR(QOS_R5FSS0_CORE1_MEM_RD_CBASS_MAP(channel), (QOS_R5FSS0_CORE1_MEM_RD_ATYPE << 28) | (QOS_R5FSS0_CORE1_MEM_RD_PRIORITY << 12) | (QOS_R5FSS0_CORE0_MEM_RD_ORDER_ID << 4));
+ }
+
+ /* R5FSS0 core1 - write */
+ for (group = 0; group < QOS_R5FSS0_CORE1_MEM_WR_NUM_J_CH; ++group)
+ {
+ CSL_REG32_WR(QOS_R5FSS0_CORE1_MEM_WR_CBASS_GRP_MAP1(group), 0x76543210);
+ CSL_REG32_WR(QOS_R5FSS0_CORE1_MEM_WR_CBASS_GRP_MAP2(group), 0xfedcba98);
+ }
+
+ for (channel = 0; channel < QOS_R5FSS0_CORE1_MEM_WR_NUM_I_CH; ++channel)
+ {
+ CSL_REG32_WR(QOS_R5FSS0_CORE1_MEM_WR_CBASS_MAP(channel), (QOS_R5FSS0_CORE1_MEM_WR_ATYPE << 28) | (QOS_R5FSS0_CORE1_MEM_WR_PRIORITY << 12) | (QOS_R5FSS0_CORE1_MEM_RD_ORDER_ID << 4));
+ }
}
-static void J721E_SetupQoS(void)
+static void J721E_SetupQoS(uint32_t isBuildHs)
{
/* Workaround to unblock HS device boot
* setup_navss_nb() causes problem with load of TIFS
* So, we comment out the following. */
- /* setup_navss_nb(); */
+ if(isBuildHs != TRUE)
+ {
+ setup_navss_nb();
+ }
setup_c66_qos();
- /* Workaround to unblock PDK-8359 .
- * setup_main_r5f_qos() results in crashing the UDMA DRU examples on
- * mcu2_0(with SBL uart boot mode) during CSL_REG64_WR(&pRegs->DRUQueues.CFG[queueId], regVal);
- * Hence commenting out the following. */
- /* setup_main_r5f_qos(); */
+ /* Workaround to unblock PDK-8359 .
+ * setup_main_r5f_qos() results in crashing the UDMA DRU examples on
+ * mcu2_0(with SBL uart boot mode) during CSL_REG64_WR(&pRegs->DRUQueues.CFG[queueId], regVal);
+ * Hence commenting out the following. */
+ //setup_main_r5f_qos();
setup_vpac_qos();
setup_dmpac_qos();
setup_dss_qos();
#endif
/* This function is to be called from other apps (e.g., mcusw boot app) to set QoS settings */
-void SBL_SetQoS(void)
+void SBL_SetQoS(uint32_t isBuildHs)
{
#if defined(SOC_J721E)
- J721E_SetupQoS();
+ J721E_SetupQoS(isBuildHs);
#endif
}
index a51b15569fe9b0a6f08e6aff91b978bdfa298d63..78665fd56e1de64145e73f1a9be77c7ecb30d7ef 100644 (file)
#ifndef _SBL_QOS_H_
#define _SBL_QOS_H_
-void SBL_SetQoS(void);
+void SBL_SetQoS(uint32_t isBuildHs);
#endif /* _SBL_QOS_H_ */
index 551bf24e56ec41783a1f0f6135c586a6bb5cfa13..95ccecb13835acd8d52513d18177ad3af94913ef 100755 (executable)
{0, 0, 0}
};
-void SBL_SocEarlyInit(void)
+void SBL_SocEarlyInit(uint32_t isBuildHs)
{
}
}
}
-void SBL_SocEarlyInit(void)
+void SBL_SocEarlyInit(uint32_t isBuildHs)
{
J721E_SetupLvCmosDriveStrength();
J721E_UART_InitPwrClk();
#if !defined(SBL_ENABLE_DEV_GRP_MCU) && !defined(SBL_USE_MCU_DOMAIN_ONLY)
- SBL_SetQoS();
+ SBL_SetQoS(isBuildHs);
#endif
}
HW_WR_REG32(SBL_UART_PLL_BASE + SBL_UART_PLL_KICK1_OFFSET, SBL_UART_PLL_KICK_LOCK_VAL);
}
-void SBL_SocEarlyInit(void)
+void SBL_SocEarlyInit(uint32_t isBuildHs)
{
J7200_UART_InitPwrClk();
}
#if defined(SOC_AM64X)
#include <ti/board/src/am64x_evm/include/board_internal.h>
-void SBL_SocEarlyInit(void)
+void SBL_SocEarlyInit(uint32_t isBuildHs)
{
}
index f042b926aff67b7e9c19daaa172682febc66e878..fa14cbce4ea63966723a5bb27d02bb1b33ea4795 100755 (executable)
#define SBL_DEV_ID_M4F_CLUSTER0 (TISCI_DEV_MCU_M4FSS0_CORE0)
-#define SBL_PROC_ID_MPU1_CPU0 (SCICLIENT_PROCID_A53_CL0_C0)
+#define SBL_PROC_ID_MPU1_CPU0 (SCICLIENT_PROCID_A53_CL0_C0)
#define SBL_DEV_ID_MPU1_CPU0 (TISCI_DEV_A53SS0_CORE_0)
#define SBL_CLK_ID_MPU1_CPU0 (TISCI_DEV_A53SS0_COREPAC_ARM_CLK_CLK)
#define SBL_MPU1_CPU0_FREQ_HZ (800000000)
-#define SBL_PROC_ID_MPU1_CPU1 (SCICLIENT_PROCID_A53_CL0_C1)
+#define SBL_PROC_ID_MPU1_CPU1 (SCICLIENT_PROCID_A53_CL0_C1)
#define SBL_DEV_ID_MPU1_CPU1 (TISCI_DEV_A53SS0_CORE_1)
#define SBL_CLK_ID_MPU1_CPU1 (TISCI_DEV_A53SS0_COREPAC_ARM_CLK_CLK)
#define SBL_MPU1_CPU1_FREQ_HZ (800000000)
/* Function Declarations */
/* ========================================================================== */
void SBL_RAT_Config(sblRatCfgInfo_t *remap_list);
-void SBL_SocEarlyInit(void);
+void SBL_SocEarlyInit(uint32_t isBuildHs);
void SBL_SocLateInit(void);
#endif
index 02b36a5846c98d56ac65b34c86f4ed0e1f9704e2..bd1aa1554cabeb9d9b7a0364ffa20ee98a969e8b 100644 (file)
******************* SoC Specific Initilization ***********************
**********************************************************************/
-void SBL_SocEarlyInit(void)
+void SBL_SocEarlyInit(uint32_t isBuildHs)
{
//SetupLvCmosDriveStrength();
diff --git a/packages/ti/boot/sbl/soc/tpr12/sbl_soc_cfg.h b/packages/ti/boot/sbl/soc/tpr12/sbl_soc_cfg.h
index b2876b9a73a8e78518b3b9a8cbbb730522590867..b180978cecab16d40c9cb852462270f78bde554e 100644 (file)
/* ========================================================================== */
/* Function Declarations */
/* ========================================================================== */
-void SBL_SocEarlyInit(void);
+void SBL_SocEarlyInit(uint32_t isBuildHs);
void SBL_SocLateInit(void);
extern void SBL_moduleClockInit(void);