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raw | patch | inline | side by side (parent: 15a87ea)
author | Angela Stegmaier <angelabaker@ti.com> | |
Wed, 29 Jan 2020 21:43:03 +0000 (15:43 -0600) | ||
committer | Mahesh Radhakrishnan <a0875154@ti.com> | |
Mon, 3 Feb 2020 15:30:59 +0000 (09:30 -0600) |
The Vring memory that is used for C66x cores communication with
A72 Linux needs to be set as Non-cached as this is shared memory
between the two cores. Without this, communication with Linux
on A72 did not happen properly when L1D/L2 cache was enabled
on the C66x cores. This was due to stale values in the
shared vring memory.
Additionally, to make sure the trace buffer is readable from
Linux debugfs trace, the trace buffer needs to be flushed
periodically when cache is enabled. Add a function that will
run when entering idle that will flush the contents of the
trace buffer to memory.
Signed-off-by: Angela Stegmaier <angelabaker@ti.com>
A72 Linux needs to be set as Non-cached as this is shared memory
between the two cores. Without this, communication with Linux
on A72 did not happen properly when L1D/L2 cache was enabled
on the C66x cores. This was due to stale values in the
shared vring memory.
Additionally, to make sure the trace buffer is readable from
Linux debugfs trace, the trace buffer needs to be flushed
periodically when cache is enabled. Add a function that will
run when entering idle that will flush the contents of the
trace buffer to memory.
Signed-off-by: Angela Stegmaier <angelabaker@ti.com>
diff --git a/packages/ti/drv/ipc/examples/common/j721e/ipc_override.cfg b/packages/ti/drv/ipc/examples/common/j721e/ipc_override.cfg
index a80c2e9527e2161054998e07608ecc599b1a8899..c83101d65959ca19069521c292753149dd575f68 100644 (file)
Task.enableIdleTask = true;
}
+if(coreId=="c66xdsp_1" || coreId=="c66xdsp_2")
+{
+ /* TraceBuf Idle Function */
+ Idle.addFunc('&traceBuf_cacheWb');
+}
+
/* Set ipc/VRing buffer as uncached */
if(coreId=="c66xdsp_1" || coreId =="c66xdsp_2" )
{
Cache.setMarMeta(0xAA000000, 0x1C00000, Cache.Mar_DISABLE);
}
+/* Set ipc/VRing buffer as uncached - Linux on A72 */
+if(coreId=="c66xdsp_1" )
+{
+ Cache.setMarMeta(0xA7000000, 0x1000000, Cache.Mar_DISABLE);
+}
+
+if(coreId=="c66xdsp_2")
+{
+ Cache.setMarMeta(0xA6000000, 0x1000000, Cache.Mar_DISABLE)
+}
+
if(coreId=="mpu1_0")
{
var Mmu = xdc.module('ti.sysbios.family.arm.v8a.Mmu');
diff --git a/packages/ti/drv/ipc/examples/common/src/ipc_utils.c b/packages/ti/drv/ipc/examples/common/src/ipc_utils.c
index b08c0f6bfbfc909d0ad2def2f75ab1c0a929f114..03d189ad6c977ad613e7ab07e5771f7086a6bff1 100644 (file)
#include <xdc/std.h>
#include <xdc/runtime/Error.h>
#include <xdc/runtime/System.h>
+#include <xdc/runtime/Timestamp.h>
+#include <xdc/runtime/Types.h>
#include <xdc/runtime/Memory.h>
/* BIOS Header files */
#include <ti/sysbios/knl/Task.h>
#include <ti/drv/ipc/ipc.h>
+#include <ti/osal/osal.h>
+
+#define CACHE_WB_TICK_PERIOD 5
+
void SetManualBreak()
{
asm(" wfi");
#endif
}
+
+/*
+ * ======== traceBuf_cacheWb ========
+ *
+ * Used for flushing SysMin trace buffer.
+ */
+
+static uint8_t *traceBufAddr = 0U;
+
+Void traceBuf_cacheWb()
+{
+ static uint64_t oldticks;
+ uint64_t newticks;
+ Types_Timestamp64 bios_timestamp64;
+
+ Timestamp_get64(&bios_timestamp64);
+ newticks = ((uint64_t) bios_timestamp64.hi << 32) | bios_timestamp64.lo;
+ /* Don't keep flusing cache */
+ if ((newticks - oldticks) >= (uint64_t)CACHE_WB_TICK_PERIOD) {
+ oldticks = newticks;
+
+ /* Flush the cache of the SysMin buffer only: */
+ if (traceBufAddr == NULL) {
+ traceBufAddr = Ipc_getResourceTraceBufPtr();
+ }
+ if (traceBufAddr != NULL) {
+ CacheP_wb((const void *)traceBufAddr, 0x80000);
+ }
+ }
+}
diff --git a/packages/ti/drv/ipc/examples/common/src/ipc_utils.h b/packages/ti/drv/ipc/examples/common/src/ipc_utils.h
index 1dd2b1637a567a119be61759ba30596fb5134d57..0d96062f58f64d6702f017494a23976ee0d26b48 100644 (file)
void SetManualBreak();
void sysIdleLoop(void);
+void traceBuf_cacheWb(void);
#ifdef __cplusplus
}
index c1850e9c2f4361094a433f3ae2879fd4d5a3715c..ff7cc7343d8c2159abc4f1a0b8c48618615c4eda 100644 (file)
*/
int32_t Ipc_loadResourceTable(void *rsctable);
+/**
+ * \brief Gets the address of the trace buffer.
+ *
+ * \return Address of the trace buffer.
+ */
+void * Ipc_getResourceTraceBufPtr(void);
+
/**
* \brief Checks if remote is ready
*
index c9ef502951a0929fd9b63dd067d485b485b953b9..f63d4f624b9ae67781be628e0f8757bc05d6bdcc 100644 (file)
return IPC_SOK;
}
+/*
+ * \brief Gets the trace buffer pointer from
+ * the resource table
+ */
+void * Ipc_getResourceTraceBufPtr()
+{
+ Ipc_ResourceTable *rsc = NULL;
+ uint32_t i;
+ uintptr_t offset;
+ uint32_t type;
+ Ipc_Trace *entry = NULL;
+ void *tracePtr = NULL;
+
+ if (rscTable != NULL) {
+ rsc = (Ipc_ResourceTable*)rscTable;
+
+ for (i = 0; i < rsc->base.num; i++) {
+ offset = (uintptr_t)((uint8_t *)rsc + rsc->offset[i]);
+ type = *(uint32_t *)offset;
+ if (type == TYPE_TRACE) {
+ entry = (Ipc_Trace *)offset;
+ tracePtr = (void *)((uintptr_t)entry->da);
+ break;
+ }
+ }
+ }
+
+ return tracePtr;
+}
+
/**
* \brief Placeholder for MMU Address translation
*/