Board: Remoaved SIM_BUILD configurations in am64x board
authorM V Pratap Reddy <x0257344@ti.com>
Thu, 19 Nov 2020 14:57:43 +0000 (20:27 +0530)
committerM V Pratap Reddy <x0257344@ti.com>
Thu, 19 Nov 2020 19:00:34 +0000 (00:30 +0530)
 - Conifgurations enabled using SIM_BUILD macro are used for QT/Zebu
   testing. Need to disable these configs for testing on EVM.

13 files changed:
packages/ti/board/src/am64x_evm/AM64x_pinmux_data.c
packages/ti/board/src/am64x_evm/am64x_evm.syscfg [new file with mode: 0644]
packages/ti/board/src/am64x_evm/board_clock.c
packages/ti/board/src/am64x_evm/board_mmr.c
packages/ti/board/src/am64x_evm/board_pinmux.c
packages/ti/board/src/am64x_evm/include/board_cfg.h
packages/ti/board/src/flash/nor/nor.c
packages/ti/board/src/flash/nor/ospi/nor_ospi.h
packages/ti/board/src/flash/nor/ospi/nor_xspi.c
packages/ti/board/src/flash/nor/ospi/nor_xspi.h
packages/ti/board/src/flash/src_files_flash.mk
packages/ti/build/makerules/build_config.mk
packages/ti/drv/spi/test/ospi_flash/src/main_ospi_flash_test.c

index ba09b8af8c42bc8ba268e4a757523df6e20042e4..8fcfd150052f077f63cb46522735472641293aab 100755 (executable)
@@ -1,5 +1,5 @@
 /**\r
-* Note: This file was auto-generated by TI PinMux on 10/23/2020 at 6:39:51 PM.\r
+* Note: This file was auto-generated by TI PinMux on 11/19/2020 at 8:18:21 PM.\r
 *\r
 * \file  AM64x_pinmux_data.c\r
 *\r
diff --git a/packages/ti/board/src/am64x_evm/am64x_evm.syscfg b/packages/ti/board/src/am64x_evm/am64x_evm.syscfg
new file mode 100644 (file)
index 0000000..42474ba
--- /dev/null
@@ -0,0 +1,482 @@
+/**
+ * These arguments were used when this file was generated. They will be automatically applied on subsequent loads
+ * via the GUI or CLI. Run CLI with '--help' for additional information on how to override these arguments.
+ * @cliArgs --device "AM64x_beta" --package "ALV" --part "Default"
+ * @versions {"data":"20201003","timestamp":"2020071713","tool":"1.5.0+1397","templates":"20190604"}
+ */
+
+/**
+ * These are the peripherals and settings in this configuration
+ */
+const iADC1                            = scripting.addPeripheral("ADC");
+iADC1.$name                            = "MyADC1";
+iADC1.$assign                          = "ADC0";
+iADC1.AIN0.$assign                     = "ADC0_AIN0";
+iADC1.AIN0.$used                       = true;
+iADC1.AIN1.$assign                     = "ADC0_AIN1";
+iADC1.AIN1.$used                       = true;
+iADC1.AIN2.$assign                     = "ADC0_AIN2";
+iADC1.AIN2.$used                       = true;
+iADC1.AIN3.$assign                     = "ADC0_AIN3";
+iADC1.AIN3.$used                       = true;
+iADC1.AIN4.$assign                     = "ADC0_AIN4";
+iADC1.AIN4.$used                       = true;
+iADC1.AIN5.$assign                     = "ADC0_AIN5";
+iADC1.AIN5.$used                       = true;
+iADC1.AIN6.$assign                     = "ADC0_AIN6";
+iADC1.AIN6.$used                       = true;
+iADC1.AIN7.$assign                     = "ADC0_AIN7";
+iADC1.AIN7.$used                       = true;
+iADC1.EXT_TRIGGER0.$used               = false;
+iADC1.EXT_TRIGGER1.$used               = false;
+const iDDRSS1                          = scripting.addPeripheral("DDRSS");
+iDDRSS1.$name                          = "MyDDRSS1";
+iDDRSS1.$assign                        = "DDR0";
+const iFSI_RX1                         = scripting.addPeripheral("FSI_RX");
+iFSI_RX1.$name                         = "MyFSI_RX1";
+iFSI_RX1.$assign                       = "FSI_RX0";
+iFSI_RX1.CLK.$assign                   = "GPMC0_AD8";
+iFSI_RX1.D0.$assign                    = "GPMC0_AD9";
+iFSI_RX1.D1.$assign                    = "GPMC0_AD10";
+const iFSI_TX1                         = scripting.addPeripheral("FSI_TX");
+iFSI_TX1.$name                         = "MyFSI_TX1";
+iFSI_TX1.CLK.$assign                   = "GPMC0_BE1n";
+iFSI_TX1.D0.$assign                    = "GPMC0_AD14";
+iFSI_TX1.D1.$assign                    = "GPMC0_AD15";
+const iGPIO1                           = scripting.addPeripheral("GPIO");
+iGPIO1["1"].$assign                    = "OSPI0_LBCLKO";
+iGPIO1["12"].$assign                   = "OSPI0_CSn1";
+iGPIO1["12"].$used                     = true;
+iGPIO1["13"].$assign                   = "OSPI0_CSn2";
+iGPIO1["13"].$used                     = true;
+iGPIO1["14"].$assign                   = "OSPI0_CSn3";
+iGPIO1["14"].$used                     = true;
+iGPIO1.$name                           = "MyGPIO1";
+iGPIO1.$assign                         = "GPIO0";
+const iGPIO2                           = scripting.addPeripheral("GPIO");
+iGPIO2["43"].$used                     = true;
+iGPIO2["70"].$assign                   = "EXTINTn";
+iGPIO2["70"].$used                     = true;
+iGPIO2["78"].$assign                   = "MMC1_SDWP";
+iGPIO2["78"].$used                     = true;
+iGPIO2.$name                           = "MyGPIO2";
+iGPIO2.$assign                         = "GPIO1";
+const iI2C1                            = scripting.addPeripheral("I2C");
+iI2C1.$name                            = "MyI2C1";
+iI2C1.$assign                          = "I2C0";
+iI2C1.SCL.$assign                      = "I2C0_SCL";
+iI2C1.SDA.$assign                      = "I2C0_SDA";
+const iI2C2                            = scripting.addPeripheral("I2C");
+iI2C2.$name                            = "MyI2C2";
+iI2C2.$assign                          = "I2C1";
+iI2C2.SCL.$assign                      = "I2C1_SCL";
+iI2C2.SDA.$assign                      = "I2C1_SDA";
+const iMCAN1                           = scripting.addPeripheral("MCAN");
+iMCAN1.$name                           = "MyMCAN1";
+iMCAN1.$assign                         = "MCAN0";
+iMCAN1.RX.$assign                      = "MCAN0_RX";
+iMCAN1.TX.$assign                      = "MCAN0_TX";
+const iMCAN2                           = scripting.addPeripheral("MCAN");
+iMCAN2.$name                           = "MyMCAN2";
+iMCAN2.$assign                         = "MCAN1";
+iMCAN2.RX.$assign                      = "MCAN1_RX";
+iMCAN2.TX.$assign                      = "MCAN1_TX";
+const iMCU_GPIO1                       = scripting.addPeripheral("MCU_GPIO");
+iMCU_GPIO1["0"].$used                  = false;
+iMCU_GPIO1["1"].$assign                = "MCU_SPI0_CS1";
+iMCU_GPIO1["1"].$used                  = false;
+iMCU_GPIO1["2"].$used                  = false;
+iMCU_GPIO1["3"].$used                  = false;
+iMCU_GPIO1["4"].$used                  = false;
+iMCU_GPIO1["5"].$assign                = "MCU_SPI1_CS0";
+iMCU_GPIO1["6"].$used                  = false;
+iMCU_GPIO1["7"].$used                  = false;
+iMCU_GPIO1["8"].$used                  = false;
+iMCU_GPIO1["9"].$used                  = false;
+iMCU_GPIO1["10"].$used                 = false;
+iMCU_GPIO1["11"].$used                 = false;
+iMCU_GPIO1["12"].$used                 = false;
+iMCU_GPIO1["13"].$used                 = false;
+iMCU_GPIO1["14"].$used                 = false;
+iMCU_GPIO1["15"].$used                 = false;
+iMCU_GPIO1["16"].$used                 = false;
+iMCU_GPIO1["17"].$used                 = false;
+iMCU_GPIO1["18"].$used                 = false;
+iMCU_GPIO1["19"].$used                 = false;
+iMCU_GPIO1["20"].$used                 = false;
+iMCU_GPIO1["21"].$used                 = false;
+iMCU_GPIO1["22"].$used                 = false;
+iMCU_GPIO1.$name                       = "MyMCU_GPIO1";
+iMCU_GPIO1.$assign                     = "MCU_GPIO0";
+const iMCU_I2C1                        = scripting.addPeripheral("MCU_I2C");
+iMCU_I2C1.$name                        = "MyMCU_I2C1";
+iMCU_I2C1.$assign                      = "MCU_I2C0";
+iMCU_I2C1.SCL.pu_pd                    = "pu";
+iMCU_I2C1.SCL.$assign                  = "MCU_I2C0_SCL";
+iMCU_I2C1.SDA.pu_pd                    = "pu";
+iMCU_I2C1.SDA.$assign                  = "MCU_I2C0_SDA";
+const iMCU_I2C2                        = scripting.addPeripheral("MCU_I2C");
+iMCU_I2C2.$name                        = "MyMCU_I2C2";
+iMCU_I2C2.$assign                      = "MCU_I2C1";
+iMCU_I2C2.SCL.pu_pd                    = "pu";
+iMCU_I2C2.SCL.$assign                  = "MCU_I2C1_SCL";
+iMCU_I2C2.SDA.pu_pd                    = "pu";
+iMCU_I2C2.SDA.$assign                  = "MCU_I2C1_SDA";
+const iMCU_SYSTEM1                     = scripting.addPeripheral("MCU_SYSTEM");
+iMCU_SYSTEM1.$name                     = "MyMCU_SYSTEM1";
+iMCU_SYSTEM1.MCU_EXT_REFCLK0.$used     = false;
+iMCU_SYSTEM1.MCU_OBSCLK0.$used         = false;
+iMCU_SYSTEM1.MCU_PORz.$assign          = "MCU_PORz";
+iMCU_SYSTEM1.MCU_RESETSTATz.$assign    = "MCU_RESETSTATz";
+iMCU_SYSTEM1.MCU_RESETz.$assign        = "MCU_RESETz";
+iMCU_SYSTEM1.MCU_SAFETY_ERRORn.$assign = "MCU_SAFETY_ERRORn";
+iMCU_SYSTEM1.MCU_SYSCLKOUT0.$used      = false;
+const iMCU_UART1                       = scripting.addPeripheral("MCU_UART");
+iMCU_UART1.$name                       = "MyMCU_UART1";
+iMCU_UART1.$assign                     = "MCU_USART0";
+iMCU_UART1.CTSn.$assign                = "MCU_UART0_CTSn";
+iMCU_UART1.RTSn.$assign                = "MCU_UART0_RTSn";
+iMCU_UART1.RXD.$assign                 = "MCU_UART0_RXD";
+iMCU_UART1.TXD.$assign                 = "MCU_UART0_TXD";
+const iMCU_UART2                       = scripting.addPeripheral("MCU_UART");
+iMCU_UART2.$name                       = "MyMCU_UART2";
+iMCU_UART2.$assign                     = "MCU_USART1";
+iMCU_UART2.CTSn.$assign                = "MCU_UART1_CTSn";
+iMCU_UART2.RTSn.$assign                = "MCU_UART1_RTSn";
+iMCU_UART2.RXD.$assign                 = "MCU_UART1_RXD";
+iMCU_UART2.TXD.$assign                 = "MCU_UART1_TXD";
+const iMDIO1                           = scripting.addPeripheral("MDIO");
+iMDIO1.$name                           = "MyMDIO1";
+iMDIO1.$assign                         = "MDIO0";
+iMDIO1.MDC.$assign                     = "PRG0_PRU1_GPO19";
+iMDIO1.MDIO.$assign                    = "PRG0_PRU1_GPO18";
+const iMMC01                           = scripting.addPeripheral("MMC0");
+iMMC01.$name                           = "MyMMC01";
+iMMC01.$assign                         = "MMC0";
+iMMC01.CMD.$assign                     = "MMC0_CMD";
+iMMC01.CLK.$assign                     = "MMC0_CLK";
+iMMC01.DS.$assign                      = "MMC0_DS";
+iMMC01.DAT0.$assign                    = "MMC0_DAT0";
+iMMC01.DAT1.$assign                    = "MMC0_DAT1";
+iMMC01.DAT2.$assign                    = "MMC0_DAT2";
+iMMC01.DAT3.$assign                    = "MMC0_DAT3";
+iMMC01.DAT4.$assign                    = "MMC0_DAT4";
+iMMC01.DAT5.$assign                    = "MMC0_DAT5";
+iMMC01.DAT6.$assign                    = "MMC0_DAT6";
+iMMC01.DAT7.$assign                    = "MMC0_DAT7";
+const iMMC11                           = scripting.addPeripheral("MMC1");
+iMMC11.$name                           = "MyMMC11";
+iMMC11.$assign                         = "MMC1";
+iMMC11.CMD.$assign                     = "MMC1_CMD";
+iMMC11.CLK.$assign                     = "MMC1_CLK";
+iMMC11.DAT0.$assign                    = "MMC1_DAT0";
+iMMC11.DAT1.$assign                    = "MMC1_DAT1";
+iMMC11.DAT2.$assign                    = "MMC1_DAT2";
+iMMC11.DAT3.$assign                    = "MMC1_DAT3";
+iMMC11.SDCD.$assign                    = "MMC1_SDCD";
+iMMC11.SDWP.$assign                    = "MMC1_SDWP";
+iMMC11.SDWP.$used                      = false;
+const iOSPI1                           = scripting.addPeripheral("OSPI");
+iOSPI1.$name                           = "MyOSPI1";
+iOSPI1.$assign                         = "OSPI0";
+iOSPI1.CLK.$assign                     = "OSPI0_CLK";
+iOSPI1.CSn0.$assign                    = "OSPI0_CSn0";
+iOSPI1.CSn1.$used                      = false;
+iOSPI1.CSn2.$used                      = false;
+iOSPI1.CSn3.$used                      = false;
+iOSPI1.D0.$assign                      = "OSPI0_D0";
+iOSPI1.D1.$assign                      = "OSPI0_D1";
+iOSPI1.D2.$assign                      = "OSPI0_D2";
+iOSPI1.D3.$assign                      = "OSPI0_D3";
+iOSPI1.D4.$assign                      = "OSPI0_D4";
+iOSPI1.D5.$assign                      = "OSPI0_D5";
+iOSPI1.D6.$assign                      = "OSPI0_D6";
+iOSPI1.D7.$assign                      = "OSPI0_D7";
+iOSPI1.DQS.$assign                     = "OSPI0_DQS";
+iOSPI1.LBCLKO.$assign                  = "OSPI0_LBCLKO";
+iOSPI1.LBCLKO.$used                    = false;
+iOSPI1.ECC_FAIL.$used                  = false;
+iOSPI1.RESET_OUT0.$used                = false;
+iOSPI1.RESET_OUT1.$used                = false;
+const iPRU_ICSSG0_MDIO1                = scripting.addPeripheral("PRU_ICSSG0_MDIO");
+iPRU_ICSSG0_MDIO1.$name                = "MyPRU_ICSSG0_MDIO1";
+iPRU_ICSSG0_MDIO1.$assign              = "PRU_ICSSG0_MDIO0";
+iPRU_ICSSG0_MDIO1.MDC.$assign          = "PRG0_MDIO0_MDC";
+iPRU_ICSSG0_MDIO1.MDIO.$assign         = "PRG0_MDIO0_MDIO";
+const iPRU_ICSSG0_PRU1                 = scripting.addPeripheral("PRU_ICSSG0_PRU");
+iPRU_ICSSG0_PRU1.$name                 = "MyPRU_ICSSG0_PRU1";
+iPRU_ICSSG0_PRU1.$assign               = "PRU_ICSSG0_PRU0";
+iPRU_ICSSG0_PRU1.GPI0.$used            = false;
+iPRU_ICSSG0_PRU1.GPI1.$used            = false;
+iPRU_ICSSG0_PRU1.GPI10.$used           = false;
+iPRU_ICSSG0_PRU1.GPI11.$used           = false;
+iPRU_ICSSG0_PRU1.GPI12.$used           = false;
+iPRU_ICSSG0_PRU1.GPI13.$used           = false;
+iPRU_ICSSG0_PRU1.GPI14.$used           = false;
+iPRU_ICSSG0_PRU1.GPI15.$used           = false;
+iPRU_ICSSG0_PRU1.GPI16.$used           = false;
+iPRU_ICSSG0_PRU1.GPI17.$used           = false;
+iPRU_ICSSG0_PRU1.GPI18.$used           = false;
+iPRU_ICSSG0_PRU1.GPI19.$used           = false;
+iPRU_ICSSG0_PRU1.GPI2.$used            = false;
+iPRU_ICSSG0_PRU1.GPI3.$used            = false;
+iPRU_ICSSG0_PRU1.GPI4.$used            = false;
+iPRU_ICSSG0_PRU1.GPI5.$used            = false;
+iPRU_ICSSG0_PRU1.GPI6.$used            = false;
+iPRU_ICSSG0_PRU1.GPI7.$used            = false;
+iPRU_ICSSG0_PRU1.GPI8.$used            = false;
+iPRU_ICSSG0_PRU1.GPI9.$used            = false;
+iPRU_ICSSG0_PRU1.GPO0.$used            = false;
+iPRU_ICSSG0_PRU1.GPO1.$used            = false;
+iPRU_ICSSG0_PRU1.GPO10.$used           = false;
+iPRU_ICSSG0_PRU1.GPO11.$used           = false;
+iPRU_ICSSG0_PRU1.GPO12.$used           = false;
+iPRU_ICSSG0_PRU1.GPO13.$used           = false;
+iPRU_ICSSG0_PRU1.GPO14.$used           = false;
+iPRU_ICSSG0_PRU1.GPO15.$used           = false;
+iPRU_ICSSG0_PRU1.GPO16.$used           = false;
+iPRU_ICSSG0_PRU1.GPO17.$used           = false;
+iPRU_ICSSG0_PRU1.GPO18.$used           = false;
+iPRU_ICSSG0_PRU1.GPO19.$used           = false;
+iPRU_ICSSG0_PRU1.GPO2.$used            = false;
+iPRU_ICSSG0_PRU1.GPO3.$used            = false;
+iPRU_ICSSG0_PRU1.GPO4.$used            = false;
+iPRU_ICSSG0_PRU1.GPO5.$used            = false;
+iPRU_ICSSG0_PRU1.GPO6.$used            = false;
+iPRU_ICSSG0_PRU1.GPO7.$used            = false;
+iPRU_ICSSG0_PRU1.GPO8.$assign          = "PRG0_PRU0_GPO8";
+iPRU_ICSSG0_PRU1.GPO9.$used            = false;
+const iPRU_ICSSG0_PRU2                 = scripting.addPeripheral("PRU_ICSSG0_PRU");
+iPRU_ICSSG0_PRU2.$name                 = "MyPRU_ICSSG0_PRU2";
+iPRU_ICSSG0_PRU2.$assign               = "PRU_ICSSG0_PRU1";
+iPRU_ICSSG0_PRU2.GPI0.$used            = false;
+iPRU_ICSSG0_PRU2.GPI1.$used            = false;
+iPRU_ICSSG0_PRU2.GPI10.$used           = false;
+iPRU_ICSSG0_PRU2.GPI11.$used           = false;
+iPRU_ICSSG0_PRU2.GPI12.$used           = false;
+iPRU_ICSSG0_PRU2.GPI13.$used           = false;
+iPRU_ICSSG0_PRU2.GPI14.$used           = false;
+iPRU_ICSSG0_PRU2.GPI15.$used           = false;
+iPRU_ICSSG0_PRU2.GPI16.$used           = false;
+iPRU_ICSSG0_PRU2.GPI17.$used           = false;
+iPRU_ICSSG0_PRU2.GPI18.$used           = false;
+iPRU_ICSSG0_PRU2.GPI19.$used           = false;
+iPRU_ICSSG0_PRU2.GPI2.$used            = false;
+iPRU_ICSSG0_PRU2.GPI3.$used            = false;
+iPRU_ICSSG0_PRU2.GPI4.$used            = false;
+iPRU_ICSSG0_PRU2.GPI5.$used            = false;
+iPRU_ICSSG0_PRU2.GPI6.$used            = false;
+iPRU_ICSSG0_PRU2.GPI7.$used            = false;
+iPRU_ICSSG0_PRU2.GPI8.$used            = false;
+iPRU_ICSSG0_PRU2.GPI9.$used            = false;
+iPRU_ICSSG0_PRU2.GPO0.$used            = false;
+iPRU_ICSSG0_PRU2.GPO1.$used            = false;
+iPRU_ICSSG0_PRU2.GPO10.$used           = false;
+iPRU_ICSSG0_PRU2.GPO11.$used           = false;
+iPRU_ICSSG0_PRU2.GPO12.$used           = false;
+iPRU_ICSSG0_PRU2.GPO13.$used           = false;
+iPRU_ICSSG0_PRU2.GPO14.$used           = false;
+iPRU_ICSSG0_PRU2.GPO15.$used           = false;
+iPRU_ICSSG0_PRU2.GPO16.$used           = false;
+iPRU_ICSSG0_PRU2.GPO17.$used           = false;
+iPRU_ICSSG0_PRU2.GPO18.$used           = false;
+iPRU_ICSSG0_PRU2.GPO19.$used           = false;
+iPRU_ICSSG0_PRU2.GPO2.$used            = false;
+iPRU_ICSSG0_PRU2.GPO3.$used            = false;
+iPRU_ICSSG0_PRU2.GPO4.$used            = false;
+iPRU_ICSSG0_PRU2.GPO5.$used            = false;
+iPRU_ICSSG0_PRU2.GPO6.$used            = false;
+iPRU_ICSSG0_PRU2.GPO7.$used            = false;
+iPRU_ICSSG0_PRU2.GPO8.$assign          = "PRG0_PRU1_GPO8";
+iPRU_ICSSG0_PRU2.GPO9.$used            = false;
+const iPRU_ICSSG1_MDIO1                = scripting.addPeripheral("PRU_ICSSG1_MDIO");
+iPRU_ICSSG1_MDIO1.$name                = "MyPRU_ICSSG1_MDIO1";
+iPRU_ICSSG1_MDIO1.$assign              = "PRU_ICSSG1_MDIO0";
+iPRU_ICSSG1_MDIO1.MDC.$assign          = "PRG1_MDIO0_MDC";
+iPRU_ICSSG1_MDIO1.MDIO.$assign         = "PRG1_MDIO0_MDIO";
+const iPRU_ICSSG1_RGMII1               = scripting.addPeripheral("PRU_ICSSG1_RGMII");
+iPRU_ICSSG1_RGMII1.$name               = "MyPRU_ICSSG1_RGMII1";
+iPRU_ICSSG1_RGMII1.$assign             = "PRU_ICSSG1_RGMII1";
+iPRU_ICSSG1_RGMII1.RD0.$assign         = "PRG1_PRU0_GPO0";
+iPRU_ICSSG1_RGMII1.RD1.$assign         = "PRG1_PRU0_GPO1";
+iPRU_ICSSG1_RGMII1.RD2.$assign         = "PRG1_PRU0_GPO2";
+iPRU_ICSSG1_RGMII1.RD3.$assign         = "PRG1_PRU0_GPO3";
+iPRU_ICSSG1_RGMII1.RXC.$assign         = "PRG1_PRU0_GPO6";
+iPRU_ICSSG1_RGMII1.RX_CTL.$assign      = "PRG1_PRU0_GPO4";
+iPRU_ICSSG1_RGMII1.TD0.$assign         = "PRG1_PRU0_GPO11";
+iPRU_ICSSG1_RGMII1.TD1.$assign         = "PRG1_PRU0_GPO12";
+iPRU_ICSSG1_RGMII1.TD2.$assign         = "PRG1_PRU0_GPO13";
+iPRU_ICSSG1_RGMII1.TD3.$assign         = "PRG1_PRU0_GPO14";
+iPRU_ICSSG1_RGMII1.TXC.$assign         = "PRG1_PRU0_GPO16";
+iPRU_ICSSG1_RGMII1.TX_CTL.$assign      = "PRG1_PRU0_GPO15";
+const iPRU_ICSSG1_RGMII2               = scripting.addPeripheral("PRU_ICSSG1_RGMII");
+iPRU_ICSSG1_RGMII2.$name               = "MyPRU_ICSSG1_RGMII2";
+iPRU_ICSSG1_RGMII2.$assign             = "PRU_ICSSG1_RGMII2";
+iPRU_ICSSG1_RGMII2.RD0.$assign         = "PRG1_PRU1_GPO0";
+iPRU_ICSSG1_RGMII2.RD1.$assign         = "PRG1_PRU1_GPO1";
+iPRU_ICSSG1_RGMII2.RD2.$assign         = "PRG1_PRU1_GPO2";
+iPRU_ICSSG1_RGMII2.RD3.$assign         = "PRG1_PRU1_GPO3";
+iPRU_ICSSG1_RGMII2.RXC.$assign         = "PRG1_PRU1_GPO6";
+iPRU_ICSSG1_RGMII2.RX_CTL.$assign      = "PRG1_PRU1_GPO4";
+iPRU_ICSSG1_RGMII2.TD0.$assign         = "PRG1_PRU1_GPO11";
+iPRU_ICSSG1_RGMII2.TD1.$assign         = "PRG1_PRU1_GPO12";
+iPRU_ICSSG1_RGMII2.TD2.$assign         = "PRG1_PRU1_GPO13";
+iPRU_ICSSG1_RGMII2.TD3.$assign         = "PRG1_PRU1_GPO14";
+iPRU_ICSSG1_RGMII2.TXC.$assign         = "PRG1_PRU1_GPO16";
+iPRU_ICSSG1_RGMII2.TX_CTL.$assign      = "PRG1_PRU1_GPO15";
+const iRGMII1                          = scripting.addPeripheral("RGMII");
+iRGMII1.$name                          = "MyRGMII1";
+iRGMII1.$assign                        = "RGMII1";
+iRGMII1.RD0.$assign                    = "PRG0_PRU1_GPO7";
+iRGMII1.RD1.$assign                    = "PRG0_PRU1_GPO9";
+iRGMII1.RD2.$assign                    = "PRG0_PRU1_GPO10";
+iRGMII1.RD3.$assign                    = "PRG0_PRU1_GPO17";
+iRGMII1.RXC.$assign                    = "PRG0_PRU0_GPO10";
+iRGMII1.RX_CTL.$assign                 = "PRG0_PRU0_GPO9";
+iRGMII1.TD0.$assign                    = "PRG1_PRU1_GPO7";
+iRGMII1.TD1.$assign                    = "PRG1_PRU1_GPO9";
+iRGMII1.TD2.$assign                    = "PRG1_PRU1_GPO10";
+iRGMII1.TD3.$assign                    = "PRG1_PRU1_GPO17";
+iRGMII1.TXC.$assign                    = "PRG1_PRU0_GPO10";
+iRGMII1.TX_CTL.$assign                 = "PRG1_PRU0_GPO9";
+const iSERDES1                         = scripting.addPeripheral("SERDES");
+iSERDES1.$name                         = "MySERDES1";
+iSERDES1.REFCLK0N.$assign              = "SERDES0_REFCLK0N";
+iSERDES1.REFCLK0P.$assign              = "SERDES0_REFCLK0P";
+iSERDES1.RXN0.$assign                  = "SERDES0_RXN0";
+iSERDES1.RXP0.$assign                  = "SERDES0_RXP0";
+iSERDES1.TXN0.$assign                  = "SERDES0_TXN0";
+iSERDES1.TXP0.$assign                  = "SERDES0_TXP0";
+const iSPI1                            = scripting.addPeripheral("SPI");
+iSPI1.$name                            = "MySPI1";
+iSPI1.$assign                          = "SPI0";
+iSPI1.CLK.$assign                      = "SPI0_CLK";
+iSPI1.CS0.$assign                      = "SPI0_CS0";
+iSPI1.CS1.$used                        = false;
+iSPI1.CS2.$used                        = false;
+iSPI1.CS3.$used                        = false;
+iSPI1.D0.$assign                       = "SPI0_D0";
+iSPI1.D1.$assign                       = "SPI0_D1";
+const iSYSTEM1                         = scripting.addPeripheral("SYSTEM");
+iSYSTEM1.$name                         = "MySYSTEM1";
+iSYSTEM1.CLKOUT0.$assign               = "EXT_REFCLK1";
+iSYSTEM1.CLKOUT0.$used                 = false;
+iSYSTEM1.EXTINTn.$used                 = false;
+iSYSTEM1.EXT_REFCLK1.$assign           = "EXT_REFCLK1";
+iSYSTEM1.OBSCLK0.$used                 = false;
+iSYSTEM1.SYNC0_OUT.$assign             = "ECAP0_IN_APWM_OUT";
+iSYSTEM1.SYNC1_OUT.$used               = false;
+iSYSTEM1.SYNC2_OUT.$used               = false;
+iSYSTEM1.SYNC3_OUT.$used               = false;
+iSYSTEM1.SYSCLKOUT0.$used              = false;
+iSYSTEM1.RMII_REF_CLK.$used            = false;
+const iUART1                           = scripting.addPeripheral("UART");
+iUART1.$name                           = "MyUART1";
+iUART1.CTSn.$assign                    = "UART0_CTSn";
+iUART1.DCDn.$used                      = false;
+iUART1.DSRn.$used                      = false;
+iUART1.DTRn.$used                      = false;
+iUART1.RIn.$used                       = false;
+iUART1.RTSn.$assign                    = "UART0_RTSn";
+iUART1.RXD.$assign                     = "UART0_RXD";
+iUART1.TXD.$assign                     = "UART0_TXD";
+const iUART2                           = scripting.addPeripheral("UART");
+iUART2.$name                           = "MyUART2";
+iUART2.$assign                         = "USART1";
+iUART2.CTSn.$used                      = false;
+iUART2.DCDn.$used                      = false;
+iUART2.DSRn.$used                      = false;
+iUART2.DTRn.$used                      = false;
+iUART2.RIn.$used                       = false;
+iUART2.RTSn.$used                      = false;
+iUART2.RXD.$assign                     = "UART1_RXD";
+iUART2.TXD.$assign                     = "UART1_TXD";
+const iUART3                           = scripting.addPeripheral("UART");
+iUART3.$name                           = "MyUART3";
+iUART3.$assign                         = "USART3";
+iUART3.CTSn.$used                      = false;
+iUART3.DCDn.$used                      = false;
+iUART3.DSRn.$used                      = false;
+iUART3.DTRn.$used                      = false;
+iUART3.RIn.$used                       = false;
+iUART3.RTSn.$used                      = false;
+iUART3.RXD.$assign                     = "UART1_CTSn";
+iUART3.TXD.$assign                     = "UART1_RTSn";
+const iUSB1                            = scripting.addPeripheral("USB");
+iUSB1.$name                            = "MyUSB1";
+iUSB1.$assign                          = "USB0";
+iUSB1.DM.$assign                       = "USB0_DM";
+iUSB1.DP.$assign                       = "USB0_DP";
+iUSB1.DRVVBUS.$assign                  = "USB0_DRVVBUS";
+iUSB1.ID.$assign                       = "USB0_ID";
+iUSB1.VBUS.$assign                     = "USB0_VBUS";
+
+/**
+ * Pinmux solution for unlocked pins/peripherals. This ensures that minor changes to the automatic solver in a future
+ * version of the tool will not impact the pinmux you originally saw.  These lines can be completely deleted in order to
+ * re-solve from scratch.
+ */
+iDDRSS1.A0.$suggestSolution          = "DDR0_A0";
+iDDRSS1.A1.$suggestSolution          = "DDR0_A1";
+iDDRSS1.A10.$suggestSolution         = "DDR0_A10";
+iDDRSS1.A11.$suggestSolution         = "DDR0_A11";
+iDDRSS1.A12.$suggestSolution         = "DDR0_A12";
+iDDRSS1.A13.$suggestSolution         = "DDR0_A13";
+iDDRSS1.A2.$suggestSolution          = "DDR0_A2";
+iDDRSS1.A3.$suggestSolution          = "DDR0_A3";
+iDDRSS1.A4.$suggestSolution          = "DDR0_A4";
+iDDRSS1.A5.$suggestSolution          = "DDR0_A5";
+iDDRSS1.A6.$suggestSolution          = "DDR0_A6";
+iDDRSS1.A7.$suggestSolution          = "DDR0_A7";
+iDDRSS1.A8.$suggestSolution          = "DDR0_A8";
+iDDRSS1.A9.$suggestSolution          = "DDR0_A9";
+iDDRSS1.ACT_n.$suggestSolution       = "DDR0_ACT_n";
+iDDRSS1.ALERT_n.$suggestSolution     = "DDR0_ALERT_n";
+iDDRSS1.BA0.$suggestSolution         = "DDR0_BA0";
+iDDRSS1.BA1.$suggestSolution         = "DDR0_BA1";
+iDDRSS1.BG0.$suggestSolution         = "DDR0_BG0";
+iDDRSS1.BG1.$suggestSolution         = "DDR0_BG1";
+iDDRSS1.CAS_n.$suggestSolution       = "DDR0_CAS_n";
+iDDRSS1.CK0.$suggestSolution         = "DDR0_CK0";
+iDDRSS1.CK0_n.$suggestSolution       = "DDR0_CK0_n";
+iDDRSS1.CKE0.$suggestSolution        = "DDR0_CKE0";
+iDDRSS1.CKE1.$suggestSolution        = "DDR0_CKE1";
+iDDRSS1.CS0_n.$suggestSolution       = "DDR0_CS0_n";
+iDDRSS1.CS1_n.$suggestSolution       = "DDR0_CS1_n";
+iDDRSS1.DM0.$suggestSolution         = "DDR0_DM0";
+iDDRSS1.DM1.$suggestSolution         = "DDR0_DM1";
+iDDRSS1.DQ0.$suggestSolution         = "DDR0_DQ0";
+iDDRSS1.DQ1.$suggestSolution         = "DDR0_DQ1";
+iDDRSS1.DQ10.$suggestSolution        = "DDR0_DQ10";
+iDDRSS1.DQ11.$suggestSolution        = "DDR0_DQ11";
+iDDRSS1.DQ12.$suggestSolution        = "DDR0_DQ12";
+iDDRSS1.DQ13.$suggestSolution        = "DDR0_DQ13";
+iDDRSS1.DQ14.$suggestSolution        = "DDR0_DQ14";
+iDDRSS1.DQ15.$suggestSolution        = "DDR0_DQ15";
+iDDRSS1.DQ2.$suggestSolution         = "DDR0_DQ2";
+iDDRSS1.DQ3.$suggestSolution         = "DDR0_DQ3";
+iDDRSS1.DQ4.$suggestSolution         = "DDR0_DQ4";
+iDDRSS1.DQ5.$suggestSolution         = "DDR0_DQ5";
+iDDRSS1.DQ6.$suggestSolution         = "DDR0_DQ6";
+iDDRSS1.DQ7.$suggestSolution         = "DDR0_DQ7";
+iDDRSS1.DQ8.$suggestSolution         = "DDR0_DQ8";
+iDDRSS1.DQ9.$suggestSolution         = "DDR0_DQ9";
+iDDRSS1.DQS0.$suggestSolution        = "DDR0_DQS0";
+iDDRSS1.DQS0_n.$suggestSolution      = "DDR0_DQS0_n";
+iDDRSS1.DQS1.$suggestSolution        = "DDR0_DQS1";
+iDDRSS1.DQS1_n.$suggestSolution      = "DDR0_DQS1_n";
+iDDRSS1.ODT0.$suggestSolution        = "DDR0_ODT0";
+iDDRSS1.ODT1.$suggestSolution        = "DDR0_ODT1";
+iDDRSS1.PAR.$suggestSolution         = "DDR0_PAR";
+iDDRSS1.RAS_n.$suggestSolution       = "DDR0_RAS_n";
+iDDRSS1.RESET0_n.$suggestSolution    = "DDR0_RESET0_n";
+iDDRSS1.WE_n.$suggestSolution        = "DDR0_WE_n";
+iFSI_TX1.$suggestSolution            = "FSI_TX0";
+iGPIO2["43"].$suggestSolution        = "SPI0_CS1";
+iMCU_SYSTEM1.$suggestSolution        = "MCU_SYSTEM0";
+iSERDES1.$suggestSolution            = "SERDES0";
+iSYSTEM1.$suggestSolution            = "SYSTEM0";
+iSYSTEM1.FCLK_MUX.$suggestSolution   = "GPMC0_CLK";
+iSYSTEM1.PORz_OUT.$suggestSolution   = "PORz_OUT";
+iSYSTEM1.RESETSTATz.$suggestSolution = "RESETSTATz";
+iUART1.$suggestSolution              = "USART0";
index 86aaab2936cd22c5f8a211a6f24e7e3d38af34a6..71cda90e08c3a144ba2f246484fad2487461ce78 100644 (file)
 #include "board_clock.h"\r
 #include <ti/drv/sciclient/sciclient.h>\r
 \r
-#ifdef ENABLE_PSC_REG_ACCESS\r
-#if defined(BUILD_MPU) || defined(BUILD_MCU)\r
-/* power domain indices */\r
-#define GP_CORE_CTL      0\r
-#define PD_A53_CLUSTER_0 1\r
-#define PD_A53_0         2\r
-#define PD_A53_1         3\r
-#define PD_PULSAR_0      4\r
-#define PD_PULSAR_1      5\r
-#define PD_ICSSG_0       6\r
-#define PD_ICSSG_1       7\r
-#define PD_CPSW          9\r
-\r
-/* lpsc indices */\r
-#define LPSC_MAIN_ALWAYSON        0\r
-#define LPSC_MAIN_TEST            1\r
-#define LPSC_MAIN_PBIST           2\r
-#define LPSC_DMSC                 3\r
-#define LPSC_EMMC_4B              4\r
-#define LPSC_EMMC_8B              5\r
-#define LPSC_USB                  6\r
-#define LPSC_ADC                  7\r
-#define LPSC_DEBUGSS              8\r
-#define LPSC_GPMC                 9\r
-#define LPSC_EMIF_CFG            10\r
-#define LPSC_EMIF_DATA           11\r
-#define LPSC_MCAN_0              12\r
-#define LPSC_MCAN_1              13\r
-#define LPSC_SA2UL               14\r
-#define LPSC_SERDES_0            15\r
-#define LPSC_PCIE_0              16\r
-#define LPSC_A53_CLUSTER_0       20\r
-#define LPSC_A53_CLUSTER_0_PBIST 21\r
-#define LPSC_A53_0               22\r
-#define LPSC_A53_1               23\r
-#define LPSC_PULSAR_0_R5_0       24\r
-#define LPSC_PULSAR_0_R5_1       25\r
-#define LPSC_PULSAR_PBIST_0      26\r
-#define LPSC_PULSAR_1_R5_0       27\r
-#define LPSC_PULSAR_1_R5_1       28\r
-#define LPSC_PULSAR_PBIST_1      29\r
-#define LPSC_ICSSG_0             30\r
-#define LPSC_ICSSG_1             31\r
-#define LPSC_CPSW3G              33\r
-\r
-/*\r
- * macro definitions for the MCU_PSC\r
-*/\r
-\r
-/* power domain indices */\r
-#define GP_CORE_CTL_MCU          0\r
-#define PD_M4F                   1\r
-\r
-/* lpsc indices */\r
-#define LPSC_MCU_ALWAYSON 0\r
-#define LPSC_TEST 2\r
-#define LPSC_MAIN2MCU 3\r
-#define LPSC_MCU2MAIN 4\r
-#define LPSC_M4F 7\r
-\r
-// PSC Register Definitions\r
-//#define PSC_PID                     (0x44827A00)\r
-//#define M3_SOC_OFFSET               (0x60000000)\r
-//#define M3_RAT_CTRL                 (0x44200020)\r
-\r
-#define MCU_PSC_BASE                (0x04000000)\r
-#define MAIN_PSC_BASE               (0x00400000)\r
-\r
-\r
-\r
-#define MAIN_PSC_INDEX              0\r
-#define MCU_PSC_INDEX               1\r
-\r
-#define PSC_MDCTL00                 (0xA00)\r
-#define PSC_MDSTAT00                (0x800)\r
-#define PSC_PDCTL00                 (0x300)\r
-#define PSC_PDSTAT00                (0x200)\r
-#define PSC_PTCMD                   (0x120)\r
-#define PSC_PTSTAT                  (0x128)\r
-\r
-#define PSC_PD_OFF                  (0x0)\r
-#define PSC_PD_ON                   (0x1)\r
-\r
-#define PSC_SYNCRESETDISABLE        (0x0)\r
-#define PSC_SYNCRESET               (0x1)\r
-#define PSC_DISABLE                 (0x2)\r
-#define PSC_ENABLE                  (0x3)\r
-\r
-#define PSC_TIMEOUT                 (100)\r
-\r
-#define MCU_PSC_MDCTL_BASE          MCU_PSC_BASE + PSC_MDCTL00\r
-#define MCU_PSC_MDSTAT_BASE         MCU_PSC_BASE + PSC_MDSTAT00\r
-#define MCU_PSC_PDCTL_BASE          MCU_PSC_BASE + PSC_PDCTL00\r
-#define MCU_PSC_PDSTAT_BASE         MCU_PSC_BASE + PSC_PDSTAT00\r
-#define MCU_PSC_PTCMD_BASE          MCU_PSC_BASE + PSC_PTCMD\r
-#define MCU_PSC_PTSTAT_BASE         MCU_PSC_BASE + PSC_PTSTAT\r
-#define MCU_PSC_PTCMD               MCU_PSC_PTCMD_BASE\r
-#define MCU_PSC_PTSTAT              MCU_PSC_PTSTAT_BASE\r
-\r
-#define MAIN_PSC_MDCTL_BASE         MAIN_PSC_BASE + PSC_MDCTL00\r
-#define MAIN_PSC_MDSTAT_BASE        MAIN_PSC_BASE + PSC_MDSTAT00\r
-#define MAIN_PSC_PDCTL_BASE         MAIN_PSC_BASE + PSC_PDCTL00\r
-#define MAIN_PSC_PDSTAT_BASE        MAIN_PSC_BASE + PSC_PDSTAT00\r
-#define MAIN_PSC_PTCMD_BASE         MAIN_PSC_BASE + PSC_PTCMD\r
-#define MAIN_PSC_PTSTAT_BASE        MAIN_PSC_BASE + PSC_PTSTAT\r
-#define MAIN_PSC_PTCMD              MAIN_PSC_PTCMD_BASE\r
-#define MAIN_PSC_PTSTAT             MAIN_PSC_PTSTAT_BASE\r
-\r
-Board_STATUS Set_MAIN_PSC_State(unsigned int pd_id, unsigned int md_id, unsigned int pd_state, unsigned int md_state)\r
-{\r
-    unsigned int* mdctl;\r
-    unsigned int* mdstat;\r
-    unsigned int* pdctl;\r
-    unsigned int* pdstat;\r
-\r
-    unsigned int loop_cnt = 0;\r
-    Board_STATUS ret = BOARD_SOK;\r
-\r
-    unsigned int address_offset = 0;\r
-\r
-    address_offset = 0; //offset 0x80000000 on M3 core\r
-\r
-    mdctl = (unsigned int*)(MAIN_PSC_MDCTL_BASE + ( 4 * md_id ) + address_offset);\r
-    mdstat = (unsigned int*)(MAIN_PSC_MDSTAT_BASE + ( 4 * md_id )+ address_offset);\r
-    pdctl = (unsigned int*)(MAIN_PSC_PDCTL_BASE + ( 4 * pd_id ) + address_offset);\r
-    pdstat = (unsigned int*)(MAIN_PSC_PDSTAT_BASE + ( 4 * pd_id )+ address_offset);\r
-\r
-    // If state is already set, do nothing\r
-    if ( (( *pdstat & 0x1 ) == pd_state) && (( *mdstat & 0x1f ) == md_state) )\r
-    {\r
-        return ret;\r
-    }\r
-\r
-    // Wait for GOSTAT to clear\r
-    while( (loop_cnt < PSC_TIMEOUT) && (*(unsigned int*)(MAIN_PSC_PTSTAT+address_offset) & (0x1 << pd_id)) != 0 )\r
-    {\r
-        loop_cnt++;\r
-    }\r
-\r
-    // Check if we got timeout error while waiting\r
-    if (loop_cnt >= PSC_TIMEOUT)\r
-    {\r
-        ret = BOARD_FAIL;\r
-        return ret;\r
-    }\r
-\r
-    // Set PDCTL NEXT to new state\r
-    *pdctl = ((*pdctl) & ~(0x1)) | pd_state;\r
-\r
-    // Set MDCTL NEXT to new state\r
-    *mdctl = ((*mdctl) & ~(0x1f)) | md_state;\r
-\r
-    // Start power transition by setting PTCMD GO to 1\r
-    *((unsigned int*)(MAIN_PSC_PTCMD+address_offset)) = (*(unsigned int*)(MAIN_PSC_PTCMD+address_offset)) | (0x1<<pd_id);\r
-\r
-    loop_cnt = 0;\r
-\r
-    // Wait for PTSTAT GOSTAT to clear\r
-    while( (loop_cnt < PSC_TIMEOUT) && (*(unsigned int*)(MAIN_PSC_PTSTAT+address_offset) & (0x1 << pd_id)) != 0 )\r
-    {\r
-        loop_cnt++;\r
-    }\r
-\r
-    // Check if we got timeout error while waiting\r
-    if (loop_cnt >= PSC_TIMEOUT)\r
-    {\r
-        ret = BOARD_FAIL;\r
-        return ret;\r
-    }\r
-\r
-    // Verify power domain and module domain state got changed\r
-    if (( *pdstat & 0x1 ) != pd_state)\r
-    {\r
-        ret = BOARD_FAIL;\r
-        return ret;\r
-    }\r
-    if (( *mdstat & 0x1f ) != md_state)\r
-    {\r
-        ret = BOARD_FAIL;\r
-    }\r
-\r
-    return ret;\r
-}\r
-\r
-Board_STATUS GP_CORE_CTL_PowerUp()\r
-{\r
-    Board_STATUS status = BOARD_SOK;\r
-\r
-    status |= Set_MAIN_PSC_State( GP_CORE_CTL, LPSC_EMIF_CFG, PSC_PD_ON, PSC_ENABLE);\r
-    status |= Set_MAIN_PSC_State( GP_CORE_CTL, LPSC_EMIF_DATA, PSC_PD_ON, PSC_ENABLE);\r
-    return status;\r
-}\r
-\r
-Board_STATUS PD_A53_CLUSTER_0_PowerUp()\r
-{\r
-    Board_STATUS status = BOARD_SOK;\r
-\r
-    status |= Set_MAIN_PSC_State( PD_A53_CLUSTER_0, LPSC_A53_CLUSTER_0, PSC_PD_ON, PSC_ENABLE);\r
-\r
-    return status;\r
-}\r
-\r
-Board_STATUS PD_A53_0_PowerUp()\r
-{\r
-    Board_STATUS status = BOARD_SOK;\r
-\r
-    status |= Set_MAIN_PSC_State( PD_A53_0, LPSC_A53_0, PSC_PD_ON, PSC_ENABLE);\r
-\r
-    return status;\r
-}\r
-\r
-Board_STATUS PD_PULSAR_0_PowerUp()\r
-{\r
-    Board_STATUS status = BOARD_SOK;\r
-\r
-    //status |= Set_MAIN_PSC_State( PD_PULSAR_0,LPSC_PULSAR_0_R5_0, PSC_PD_ON, PSC_ENABLE);\r
-    //status |= Set_MAIN_PSC_State( PD_PULSAR_0,LPSC_PULSAR_0_R5_1, PSC_PD_ON, PSC_ENABLE);\r
-\r
-    return status;\r
-}\r
-\r
-Board_STATUS MAIN_PSC_Peripheral_PowerUp()\r
-{\r
-    Board_STATUS status = BOARD_SOK;\r
-\r
-    status |= GP_CORE_CTL_PowerUp();\r
-    status |= PD_A53_CLUSTER_0_PowerUp();\r
-    status |= PD_A53_0_PowerUp();\r
-    status |= PD_PULSAR_0_PowerUp();\r
-\r
-    return status;\r
-}\r
-\r
-Board_STATUS Set_MCU_PSC_State(unsigned int pd_id, unsigned int md_id, unsigned int pd_state, unsigned int md_state)\r
-{\r
-   unsigned int* mdctl;\r
-   unsigned int* mdstat;\r
-   unsigned int* pdctl;\r
-   unsigned int* pdstat;\r
-\r
-   unsigned int loop_cnt = 0;\r
-   Board_STATUS ret = BOARD_SOK;\r
-\r
-   unsigned int address_offset = 0;\r
-\r
-   address_offset = 0; // offset is 0x80000000 on M3 core\r
-\r
-   mdctl  = (unsigned int*)(MCU_PSC_MDCTL_BASE + ( 4 * md_id ) + address_offset);\r
-   mdstat = (unsigned int*)(MCU_PSC_MDSTAT_BASE + ( 4 * md_id ) + address_offset);\r
-   pdctl  = (unsigned int*)(MCU_PSC_PDCTL_BASE + ( 4 * pd_id ) + address_offset);\r
-   pdstat = (unsigned int*)(MCU_PSC_PDSTAT_BASE + ( 4 * pd_id ) + address_offset);\r
-\r
-   // If state is already set, do nothing\r
-   if ( (( *pdstat & 0x1 ) == pd_state) && (( *mdstat & 0x1f ) == md_state) )\r
-   {\r
-       return ret;\r
-   }\r
-\r
-   // Wait for GOSTAT to clear\r
-   while( (loop_cnt < PSC_TIMEOUT) && (*((unsigned int*)(MCU_PSC_PTSTAT+address_offset)) & (0x1 << pd_id)) != 0 )\r
-   {\r
-       loop_cnt++;\r
-   }\r
-\r
-   // Check if we got timeout error while waiting\r
-   if (loop_cnt >= PSC_TIMEOUT)\r
-   {\r
-       ret = BOARD_FAIL;\r
-       return ret;\r
-   }\r
-\r
-   // Set PDCTL NEXT to new state\r
-   *pdctl = ((*pdctl) & ~(0x1)) | pd_state;\r
-\r
-   // Set MDCTL NEXT to new state\r
-   *mdctl = ((*mdctl) & ~(0x1f)) | md_state;\r
-\r
-   // Start power transition by setting PTCMD GO to 1\r
-   (*(unsigned int*)(MCU_PSC_PTCMD + address_offset)) = (*(unsigned int*)(MCU_PSC_PTCMD + address_offset)) | (0x1<<pd_id);\r
-\r
-   loop_cnt = 0;\r
-\r
-   // Wait for PTSTAT GOSTAT to clear\r
-   while( (loop_cnt < PSC_TIMEOUT) && (*((unsigned int*)(MCU_PSC_PTSTAT+address_offset)) & (0x1 << pd_id)) != 0 )\r
-   {\r
-       loop_cnt++;\r
-   }\r
-\r
-   // Check if we got timeout error while waiting\r
-   if (loop_cnt >= PSC_TIMEOUT)\r
-   {\r
-       ret = BOARD_FAIL;\r
-       return ret;\r
-   }\r
-\r
-   // Verify power domain and module domain state got changed\r
-   if (( *pdstat & 0x1 ) != pd_state)\r
-   {\r
-       ret = BOARD_FAIL;\r
-       return ret;\r
-   }\r
-   if (( *mdstat & 0x1f ) != md_state)\r
-   {\r
-       ret = BOARD_FAIL;\r
-       return ret;\r
-   }\r
-\r
-   return ret;\r
-}\r
-\r
-Board_STATUS GP_Core_CTL_MCU_PowerUp()\r
-{\r
-    Board_STATUS status = BOARD_SOK;\r
-\r
-    status |= Set_MCU_PSC_State( GP_CORE_CTL_MCU, LPSC_MAIN2MCU, PSC_PD_ON, PSC_ENABLE);\r
-    status |= Set_MCU_PSC_State( GP_CORE_CTL_MCU, LPSC_MCU2MAIN, PSC_PD_ON, PSC_ENABLE);\r
-\r
-    return status;\r
-}\r
-\r
-Board_STATUS PD_M4F_PowerUp()\r
-{\r
-    Board_STATUS status = BOARD_SOK;\r
-\r
-    status |= Set_MCU_PSC_State( PD_M4F, LPSC_M4F, PSC_PD_ON, PSC_ENABLE);\r
-\r
-    return status;\r
-}\r
-\r
-Board_STATUS MCU_PSC_Peripheral_PowerUp()\r
-{\r
-    Board_STATUS status = BOARD_SOK;\r
-\r
-    return status;\r
-}\r
-#endif /* #ifdef BUILD_MPU/MCU */\r
-\r
-/**\r
- * \brief wkup PSC configuration parameters\r
- *\r
- *  This structure provides the device-level view with module association to\r
- *  the clock, power, and voltage domains.\r
- * \r
- *  The PSC provides the user with an interface to control several important\r
- *  power and clock operations. The device has two PSC - WKUP_PSC0 and PSC0\r
- *  in WKUPSS and MAIN SoC, respectively.\r
- * \r
- *  PSC: The Power Sleep Controller is the device has several power domains\r
- *  that can be turned ON for operation or OFF to minimize power dissipation,\r
- *  which includes a Global Power Sleep Controller(GPSC) and Local Power \r
- *  Sleep Controller(LPSC).\r
- * \r
- *  GPSC: Global Power Sleep Controller, is used to control the power gating\r
- *  of various power domains.\r
- * \r
- *  LPSC: Local Power Sleep Controller, manages the clock gating for to each \r
- *  logic block. For modules with a dedicated clock or multiple clocks, the \r
- *  LPSC communicates with the PLL controller to enable and disable that\r
- *  module's clock(s) at the source. For modules that share a clock with\r
- *  other modules, the LPSC controls the clock gating logic for each module.    \r
- */\r
-const pscConfig wkupPscConfigs[] =\r
-{\r
-\r
-};\r
-\r
-/**\r
- * \brief main PSC configuration parameters\r
- *\r
- *  This structure provides the device-level view with module association to\r
- *  the clock, power, and voltage domains.\r
- * \r
- *  The PSC provides the user with an interface to control several important\r
- *  power and clock operations. The device has two PSC - WKUP_PSC0 and PSC0\r
- *  in WKUPSS and MAIN SoC, respectively.\r
- * \r
- *  PSC: The Power Sleep Controller is the device has several power domains\r
- *  that can be turned ON for operation or OFF to minimize power dissipation,\r
- *  which includes a Global Power Sleep Controller(GPSC) and Local Power \r
- *  Sleep Controller(LPSC).\r
- * \r
- *  GPSC: Global Power Sleep Controller, is used to control the power gating\r
- *  of various power domains.\r
- * \r
- *  LPSC: Local Power Sleep Controller, manages the clock gating for to each \r
- *  logic block. For modules with a dedicated clock or multiple clocks, the \r
- *  LPSC communicates with the PLL controller to enable and disable that\r
- *  module's clock(s) at the source. For modules that share a clock with\r
- *  other modules, the LPSC controls the clock gating logic for each module.    \r
- */\r
-const pscConfig mainPscConfigs[] =\r
-{\r
-\r
-};\r
-\r
-/**\r
- *  \brief    This function is used to get the number of \\r
- *            wkup PSC configs exists.\r
- *\r
- * \return\r
- * \n         uint32_t - Number of wkup PSC configs.\r
- */\r
-uint32_t Board_getNumWkupPscCconfigs(void)\r
-{\r
-    return (sizeof(wkupPscConfigs) / sizeof(pscConfig));\r
-}\r
-\r
-/**\r
- *  \brief    This function is used to get the number of \\r
- *            main PSC configs exists.\r
- *\r
- * \return\r
- * \n         uint32_t - Number of main PSC configs.\r
- */\r
-uint32_t Board_getNumMainPscCconfigs(void)\r
-{\r
-    return (sizeof(mainPscConfigs) / sizeof(pscConfig));\r
-}\r
-\r
-#else /*  #ifdef ENABLE_PSC_REG_ACCESS */\r
-\r
 #include <ti/drv/sciclient/sciclient.h>\r
 \r
 uint32_t gBoardClkModuleID[] = {\r
@@ -620,7 +199,6 @@ Board_STATUS Board_moduleClockEnable(uint32_t moduleId)
 \r
     return retVal;\r
 }\r
-#endif /* #ifdef ENABLE_PSC_REG_ACCESS */\r
 \r
 Board_STATUS Board_moduleClockInit(void)\r
 {\r
@@ -681,18 +259,6 @@ Board_STATUS Board_moduleClockInit(void)
         status = BOARD_INIT_CLOCK_FAIL;\r
     }\r
 \r
-#ifdef ENABLE_PSC_REG_ACCESS   \r
-#ifdef SIM_BUILD\r
-#ifdef BUILD_MPU\r
-    status |= Board_unlockMMR();\r
-    status |= MAIN_PSC_Peripheral_PowerUp();\r
-#endif\r
-#ifdef BUILD_MCU\r
-    status |= Board_unlockMMR();\r
-    status |= MCU_PSC_Peripheral_PowerUp();\r
-#endif\r
-#endif\r
-#else\r
     if( status == BOARD_SOK)\r
     {\r
         loopCount = sizeof(gBoardClkModuleID) / sizeof(uint32_t);\r
@@ -706,6 +272,6 @@ Board_STATUS Board_moduleClockInit(void)
             }\r
         }\r
     }\r
-#endif /* #ifdef ENABLE_PSC_REG_ACCESS */\r
+\r
     return status;\r
 }\r
index c6aae2f348016660af1b293a945e057e7520bd34..9da407d04ab78794174174c70b778e2f1c6c60ae 100644 (file)
@@ -45,7 +45,6 @@
 #include <ti/csl/soc/am64x/src/cslr_mcu_pll_mmr.h>\r
 #include "board_internal.h"\r
 \r
-#ifdef SIM_BUILD\r
 #define AVV_PASS   (1U)\r
 #define AVV_FAIL   (0U)\r
 \r
@@ -283,7 +282,6 @@ uint32_t MCU_PLL_MMR_change_all_locks(mmr_lock_actions_t target_state);
         if(errors==0) { return AVV_PASS; }\r
         else          { return AVV_FAIL; }\r
     }\r
-#endif\r
 \r
 /**\r
  * \brief  Unlocks MMR registers\r
@@ -292,9 +290,7 @@ uint32_t MCU_PLL_MMR_change_all_locks(mmr_lock_actions_t target_state);
  */\r
 Board_STATUS Board_unlockMMR(void)\r
 {\r
-#ifdef SIM_BUILD\r
     MAIN_PADCONFIG_MMR_unlock_all();\r
-#endif\r
     return BOARD_SOK;\r
 }\r
 \r
index b4cbb78bbeb17e006b83352e0bdacc1dbee3c079..06bb4f7e9d3ab118a7b75297a3bc8126f5cfedb4 100644 (file)
 #include "board_internal.h"\r
 #include "board_pinmux.h"\r
 \r
-#ifndef BUILD_M4F\r
-#ifdef SIM_BUILD\r
-/* am64xx_main_padcfg_ctrl_mmr */\r
 #define MAIN_PADCONFIG_CTRL_BASE    0x000F0000\r
 #define CTRL_MMR0_PARTITION_SIZE    0x4000\r
 #define MAIN_CTRL_PINCFG_BASE       (MAIN_PADCONFIG_CTRL_BASE + (1 * CTRL_MMR0_PARTITION_SIZE))\r
 \r
-#define MAIN_UART0_RXD  0x0230\r
-#define MAIN_UART0_TXD  0x0234\r
-#define MAIN_UART0_CTSn 0x0238\r
-#define MAIN_UART0_RTSn 0x023c\r
-#define MAIN_UART1_RXD  0x0240\r
-#define MAIN_UART1_TXD  0x0244\r
-#define MAIN_UART1_CTSn 0x0248\r
-#define MAIN_UART1_RTSn 0x024c\r
-\r
-#define MAIN_SPI0_CS0   0x0208U\r
-\r
-#define MAIN_GPMC0_AD0  0x003cU\r
-\r
-#ifdef SIM_BUILD\r
-// PinMux Changes\r
-#include <stdint.h>\r
-\r
-//Region of pinmux padconfigs\r
-//Can't find the CSL defines for the padconfig0 offset, need to replace\r
-//The offsets were found from the AM64X MAIN and MCU padcfg_ctrl pdf documents\r
-#define TEMP_REPLACE_WITH_CSL_MAIN_PADCONFIG0_OFFSET    (0x4000)\r
-#define PINMUX_MAIN_REG_BASE                            (CSL_PADCFG_CTRL0_CFG0_BASE + TEMP_REPLACE_WITH_CSL_MAIN_PADCONFIG0_OFFSET)\r
-\r
-//All defaults except:\r
-//Receiver Disabled\r
-//High-Z\r
-#define PINMUX_DEFAULT_REG_VALUE        (0x08010000U)\r
-#define PINMUX_DEFAULT                  (0xffU)\r
-\r
-//Pullup/down/none\r
-#define PINMUX_PD                       (0x0U)\r
-#define PINMUX_PU                       (0x2U)\r
-#define PINMUX_NP                       (0x1U)\r
-\r
-#define PINMUX_DRIVESTRENGTH_0          (0x0U)\r
-#define PINMUX_DRIVESTRENGTH_1          (0x1U)\r
-#define PINMUX_DRIVESTRENGTH_2          (0x2U)\r
-#define PINMUX_DRIVESTRENGTH_3          (0x3U)\r
-\r
-//The pinmux mmrs are stupid about this:\r
-#define PINMUX_RX_ACTIVE                (0x1U)\r
-#define PINMUX_RX_DISABLE               (0x0U)\r
-#define PINMUX_TX_ACTIVE                (0x0U)\r
-#define PINMUX_TX_DISABLE               (0x1U)\r
-\r
-typedef enum {\r
-    PINMUX_MUX_MODE_0 = 0,\r
-    PINMUX_MUX_MODE_1,\r
-    PINMUX_MUX_MODE_2,\r
-    PINMUX_MUX_MODE_3,\r
-    PINMUX_MUX_MODE_4,\r
-    PINMUX_MUX_MODE_5,\r
-    PINMUX_MUX_MODE_6,\r
-    PINMUX_MUX_MODE_7,\r
-    PINMUX_MUX_MODE_8,\r
-    PINMUX_MUX_MODE_9,\r
-    PINMUX_MUX_MODE_10,\r
-    PINMUX_MUX_MODE_11,\r
-    PINMUX_MUX_MODE_12,\r
-    PINMUX_MUX_MODE_13,\r
-    PINMUX_MUX_MODE_14,\r
-    PINMUX_MUX_MODE_15,\r
-}muxmode_t;\r
-\r
-typedef struct{\r
-    uint32_t    mmrBaseAddress;\r
-    uint32_t    pinmuxRegOffset;\r
-    muxmode_t   muxmode; //0 through 15\r
-    uint8_t     pu_pd;\r
-    uint8_t     driveStrength;\r
-    uint8_t     rx;\r
-    uint8_t     tx;\r
-} pinmux_t;\r
-\r
-\r
-pinmux_t PINMUX_MAIN_ICSSG0_MII0_APP2_array_board [] = {\r
-//pinmux reg base,  Reg offset, Muxmode,  PUPD,    DRIVE_STRENGTH,    RX,  TX\r
-\r
-{PINMUX_MAIN_REG_BASE, 0x0160, PINMUX_MUX_MODE_1, PINMUX_DEFAULT, PINMUX_DEFAULT, PINMUX_RX_ACTIVE , PINMUX_TX_DISABLE}, //PAD ->PRG0_PRU0GPO0 ; PIN ->PRG0_MII0_RD0 ; PINMUX_MUX_MODE_ ->PINMUX_MUX_MODE_1, PADCONFIG88\r
-{PINMUX_MAIN_REG_BASE, 0x0164, PINMUX_MUX_MODE_1, PINMUX_DEFAULT, PINMUX_DEFAULT, PINMUX_RX_ACTIVE , PINMUX_TX_DISABLE}, //PAD ->PRG0_PRU0GPO1 ; PIN ->PRG0_MII0_RD1 ; PINMUX_MUX_MODE_ ->PINMUX_MUX_MODE_1, PADCONFIG89\r
-{PINMUX_MAIN_REG_BASE, 0x0168, PINMUX_MUX_MODE_1, PINMUX_DEFAULT, PINMUX_DEFAULT, PINMUX_RX_ACTIVE , PINMUX_TX_DISABLE}, //PAD ->PRG0_PRU0GPO2 ; PIN ->PRG0_MII0_RD2 ; PINMUX_MUX_MODE_ ->PINMUX_MUX_MODE_1, PADCONFIG90\r
-{PINMUX_MAIN_REG_BASE, 0x016C, PINMUX_MUX_MODE_1, PINMUX_DEFAULT, PINMUX_DEFAULT, PINMUX_RX_ACTIVE , PINMUX_TX_DISABLE}, //PAD ->PRG0_PRU0GPO3 ; PIN ->PRG0_MII0_RD3 ; PINMUX_MUX_MODE_ ->PINMUX_MUX_MODE_1, PADCONFIG91\r
-{PINMUX_MAIN_REG_BASE, 0x0170, PINMUX_MUX_MODE_1, PINMUX_DEFAULT, PINMUX_DEFAULT, PINMUX_RX_ACTIVE , PINMUX_TX_DISABLE}, //PAD ->PRG0_PRU0GPO4 ; PIN ->PRG0_MII0_RX_CTL ; PINMUX_MUX_MODE_ ->PINMUX_MUX_MODE_1, PADCONFIG92\r
-{PINMUX_MAIN_REG_BASE, 0x0174, PINMUX_MUX_MODE_1, PINMUX_DEFAULT, PINMUX_DEFAULT, PINMUX_RX_ACTIVE , PINMUX_TX_DISABLE}, //PAD ->PRG0_PRU0GPO5 ; PIN ->PRG0_MII0_RXER ; PINMUX_MUX_MODE_ ->PINMUX_MUX_MODE_1, PADCONFIG93\r
-{PINMUX_MAIN_REG_BASE, 0x0178, PINMUX_MUX_MODE_1, PINMUX_DEFAULT, PINMUX_DEFAULT, PINMUX_RX_ACTIVE , PINMUX_TX_DISABLE}, //PAD ->PRG0_PRU0GPO6 ; PIN ->PRG0_MII0_RXC ; PINMUX_MUX_MODE_ ->PINMUX_MUX_MODE_1, PADCONFIG94\r
-{PINMUX_MAIN_REG_BASE, 0x0180, PINMUX_MUX_MODE_1, PINMUX_DEFAULT, PINMUX_DEFAULT, PINMUX_RX_ACTIVE , PINMUX_TX_DISABLE}, //PAD ->PRG0_PRU0GPO8 ; PIN ->PRG0_MII0_RXLINK ; PINMUX_MUX_MODE_ ->PINMUX_MUX_MODE_1, PADCONFIG96\r
-{PINMUX_MAIN_REG_BASE, 0x018C, PINMUX_MUX_MODE_0, PINMUX_DEFAULT, PINMUX_DEFAULT, PINMUX_RX_DISABLE, PINMUX_TX_ACTIVE }, //PAD ->PRG0_PRU0GPO11 ; PIN ->PRG0_MII0_TD0 ; PINMUX_MUX_MODE_ ->PINMUX_MUX_MODE_0, PADCONFIG99\r
-{PINMUX_MAIN_REG_BASE, 0x0190, PINMUX_MUX_MODE_0, PINMUX_DEFAULT, PINMUX_DEFAULT, PINMUX_RX_DISABLE, PINMUX_TX_ACTIVE }, //PAD ->PRG0_PRU0GPO12 ; PIN ->PRG0_MII0_TD1 ; PINMUX_MUX_MODE_ ->PINMUX_MUX_MODE_0, PADCONFIG100\r
-{PINMUX_MAIN_REG_BASE, 0x0194, PINMUX_MUX_MODE_0, PINMUX_DEFAULT, PINMUX_DEFAULT, PINMUX_RX_DISABLE, PINMUX_TX_ACTIVE }, //PAD ->PRG0_PRU0GPO13 ; PIN ->PRG0_MII0_TD2 ; PINMUX_MUX_MODE_ ->PINMUX_MUX_MODE_0, PADCONFIG101\r
-{PINMUX_MAIN_REG_BASE, 0x0198, PINMUX_MUX_MODE_0, PINMUX_DEFAULT, PINMUX_DEFAULT, PINMUX_RX_DISABLE, PINMUX_TX_ACTIVE }, //PAD ->PRG0_PRU0GPO14 ; PIN ->PRG0_MII0_TD3 ; PINMUX_MUX_MODE_ ->PINMUX_MUX_MODE_0, PADCONFIG102\r
-{PINMUX_MAIN_REG_BASE, 0x019C, PINMUX_MUX_MODE_0, PINMUX_DEFAULT, PINMUX_DEFAULT, PINMUX_RX_DISABLE, PINMUX_TX_ACTIVE }, //PAD ->PRG0_PRU0GPO15 ; PIN ->PRG0_MII0_TX_CTL ; PINMUX_MUX_MODE_ ->PINMUX_MUX_MODE_0, PADCONFIG103\r
-{PINMUX_MAIN_REG_BASE, 0x01A0, PINMUX_MUX_MODE_1, PINMUX_DEFAULT, PINMUX_DEFAULT, PINMUX_RX_ACTIVE , PINMUX_TX_DISABLE}  //PAD ->PRG0_PRU0GPO16 ; PIN ->PRG0_MII0_TXC ; PINMUX_MUX_MODE_ ->PINMUX_MUX_MODE_1, PADCONFIG104\r
-};\r
-\r
-pinmux_t PINMUX_MAIN_ICSSG0_MII1_APP2_array_board [] = {\r
-//pinmux reg base,  Reg offset, Muxmode,  PUPD,    DRIVE_STRENGTH,    RX,  TX\r
-\r
-{PINMUX_MAIN_REG_BASE, 0x01B0, PINMUX_MUX_MODE_1, PINMUX_DEFAULT, PINMUX_DEFAULT, PINMUX_RX_ACTIVE , PINMUX_TX_DISABLE},  //PAD ->PRG0_PRU1GPO0 ; PIN ->PRG0_MII1_RD0 ; PINMUX_MUX_MODE_ ->PINMUX_MUX_MODE_1, PADCONFIG108\r
-{PINMUX_MAIN_REG_BASE, 0x01B4, PINMUX_MUX_MODE_1, PINMUX_DEFAULT, PINMUX_DEFAULT, PINMUX_RX_ACTIVE , PINMUX_TX_DISABLE}, //PAD ->PRG0_PRU1GPO1 ; PIN ->PRG0_MII1_RD1 ; PINMUX_MUX_MODE_ ->PINMUX_MUX_MODE_1, PADCONFIG109\r
-{PINMUX_MAIN_REG_BASE, 0x01B8, PINMUX_MUX_MODE_1, PINMUX_DEFAULT, PINMUX_DEFAULT, PINMUX_RX_ACTIVE , PINMUX_TX_DISABLE}, //PAD ->PRG0_PRU1GPO2 ; PIN ->PRG0_MII1_RD2 ; PINMUX_MUX_MODE_ ->PINMUX_MUX_MODE_1, PADCONFIG110\r
-{PINMUX_MAIN_REG_BASE, 0x01BC, PINMUX_MUX_MODE_1, PINMUX_DEFAULT, PINMUX_DEFAULT, PINMUX_RX_ACTIVE , PINMUX_TX_DISABLE}, //PAD ->PRG0_PRU1GPO3 ; PIN ->PRG0_MII1_RD3 ; PINMUX_MUX_MODE_ ->PINMUX_MUX_MODE_1, PADCONFIG111\r
-{PINMUX_MAIN_REG_BASE, 0x01C0, PINMUX_MUX_MODE_1, PINMUX_DEFAULT, PINMUX_DEFAULT, PINMUX_RX_ACTIVE , PINMUX_TX_DISABLE}, //PAD ->PRG0_PRU1GPO4 ; PIN ->PRG0_MII1_RX_CTL ; PINMUX_MUX_MODE_ ->PINMUX_MUX_MOdE_1, PADCONFIG112\r
-{PINMUX_MAIN_REG_BASE, 0x01C4, PINMUX_MUX_MODE_1, PINMUX_DEFAULT, PINMUX_DEFAULT, PINMUX_RX_ACTIVE , PINMUX_TX_DISABLE}, //PAD ->PRG0_PRU1GPO5 ; PIN ->PRG0_MII1_RXER ; PINMUX_MUX_MODE_ ->PINMUX_MUX_MODE_1, PADCONFIG113\r
-{PINMUX_MAIN_REG_BASE, 0x01C8, PINMUX_MUX_MODE_1, PINMUX_DEFAULT, PINMUX_DEFAULT, PINMUX_RX_ACTIVE , PINMUX_TX_DISABLE}, //PAD ->PRG0_PRU1GPO6 ; PIN ->PRG0_MII1_RXC ; PINMUX_MUX_MODE_ ->PINMUX_MUX_MODE_1, PADCONFIG114\r
-{PINMUX_MAIN_REG_BASE, 0x01d0, PINMUX_MUX_MODE_1, PINMUX_DEFAULT, PINMUX_DEFAULT, PINMUX_RX_ACTIVE , PINMUX_TX_DISABLE}, //PAD ->PRG0_PRU1GPO8 ; PIN ->PRG0_MII1_RXLINK ; PINMUX_MUX_MODE_ ->PINMUX_MUX_MODE_1, PADCONFIG116\r
-{PINMUX_MAIN_REG_BASE, 0x01DC, PINMUX_MUX_MODE_0, PINMUX_DEFAULT, PINMUX_DEFAULT, PINMUX_RX_DISABLE, PINMUX_TX_ACTIVE }, //PAD ->PRG0_PRU1GPO11 ; PIN ->PRG0_MII1_TD0 ; PINMUX_MUX_MODE_ ->PINMUX_MUX_MODE_0, PADCONFIG119\r
-{PINMUX_MAIN_REG_BASE, 0x01E0, PINMUX_MUX_MODE_0, PINMUX_DEFAULT, PINMUX_DEFAULT, PINMUX_RX_DISABLE, PINMUX_TX_ACTIVE }, //PAD ->PRG0_PRU1GPO12 ; PIN ->PRG0_MII1_TD1 ; PINMUX_MUX_MODE_ ->PINMUX_MUX_MODE_0, PADCONFIG120\r
-{PINMUX_MAIN_REG_BASE, 0x01E4, PINMUX_MUX_MODE_0, PINMUX_DEFAULT, PINMUX_DEFAULT, PINMUX_RX_DISABLE, PINMUX_TX_ACTIVE }, //PAD ->PRG0_PRU1GPO13 ; PIN ->PRG0_MII1_TD2 ; PINMUX_MUX_MODE_ ->PINMUX_MUX_MODE_0, PADCONFIG121\r
-{PINMUX_MAIN_REG_BASE, 0x01E8, PINMUX_MUX_MODE_0, PINMUX_DEFAULT, PINMUX_DEFAULT, PINMUX_RX_DISABLE, PINMUX_TX_ACTIVE }, //PAD ->PRG0_PRU1GPO14 ; PIN ->PRG0_MII1_TD3 ; PINMUX_MUX_MODE_ ->PINMUX_MUX_MODE_0, PADCONFIG122\r
-{PINMUX_MAIN_REG_BASE, 0x01EC, PINMUX_MUX_MODE_0, PINMUX_DEFAULT, PINMUX_DEFAULT, PINMUX_RX_DISABLE, PINMUX_TX_ACTIVE }, //PAD ->PRG0_PRU1GPO15 ; PIN ->PRG0_MII1_TX_CTL ; PINMUX_MUX_MODE_ ->PINMUX_MUX_MODE_0, PADCONFIG123\r
-{PINMUX_MAIN_REG_BASE, 0x01F0, PINMUX_MUX_MODE_1, PINMUX_DEFAULT, PINMUX_DEFAULT, PINMUX_RX_ACTIVE , PINMUX_TX_DISABLE}  //PAD ->PRG0_PRU1GPO16 ; PIN ->PRG0_MII1_TXC ; PINMUX_MUX_MODE_ ->PINMUX_MUX_MODE_1, PADCONFIG124\r
-};\r
-\r
-void set_pinmux_board(pinmux_t *Array, uint8_t arraysize){\r
-    uint32_t c = 0;\r
-    uint32_t i = 0;\r
-    uint32_t mmr_reg_value = 0;\r
-    uint32_t errors = 0;\r
-\r
-    //Pointer for loop\r
-    pinmux_t * arrayPtr = NULL;\r
-    arrayPtr = Array;\r
-\r
-    //Loop on each pinmux_t struct\r
-    for (i = 0; i < arraysize; i++){\r
-        //Set PADCONFIG register to defined PINMUX_DEFAULTs\r
-        *(volatile uint32_t *)(uintptr_t)(arrayPtr->mmrBaseAddress + arrayPtr->pinmuxRegOffset) = PINMUX_DEFAULT_REG_VALUE;\r
-\r
-        //Read the PADCONFIG register\r
-        mmr_reg_value = *(volatile uint32_t *)(uintptr_t)(arrayPtr->mmrBaseAddress + arrayPtr->pinmuxRegOffset);\r
-\r
-        //Mux mode slection\r
-        if(arrayPtr->muxmode != PINMUX_DEFAULT){\r
-            mmr_reg_value  &= (0xFFFFFFF0);     // Mux mode\r
-            mmr_reg_value  |= (arrayPtr->muxmode & 0x0000000F);\r
-        }\r
-\r
-        //PU-PD Selection\r
-        if(arrayPtr->pu_pd != PINMUX_DEFAULT){\r
-            mmr_reg_value &= (0xFFFCFFFF);       // PU-PD\r
-            mmr_reg_value |= ((arrayPtr->pu_pd) << 16);\r
-        }\r
-\r
-        //Drive strength selection\r
-        if(arrayPtr->driveStrength != PINMUX_DEFAULT){\r
-            mmr_reg_value &= (0xFFE7FFFF);       // Drive strength\r
-            mmr_reg_value |= ((arrayPtr->driveStrength) << 19);\r
-        }\r
-\r
-        //Receive enable/disable\r
-        if(arrayPtr->rx != PINMUX_DEFAULT){\r
-            mmr_reg_value &= (0xFFFBFFFF);       // Drive strength\r
-            mmr_reg_value |= ((arrayPtr->rx) << 18);\r
-        }\r
-\r
-        //Transmit enable/disable\r
-        if(arrayPtr->tx != PINMUX_DEFAULT){\r
-            mmr_reg_value &= (0xFFDFFFFF);       // Drive strength\r
-            mmr_reg_value |= ((arrayPtr->tx) << 21);\r
-        }\r
-\r
-        //Writing to Padconfig register\r
-        *(volatile uint32_t *)(uintptr_t)(arrayPtr->mmrBaseAddress + arrayPtr->pinmuxRegOffset) = mmr_reg_value;\r
-\r
-        for(c = 0; c < 20; c++);\r
-\r
-        //Verify write\r
-        if((*(volatile uint32_t *)(uintptr_t)(arrayPtr->mmrBaseAddress + arrayPtr->pinmuxRegOffset)) != mmr_reg_value) errors++;\r
-\r
-        arrayPtr++;\r
-    }\r
-}\r
-\r
-//PinMux change End\r
-#endif /* ifdef SIM_BUILD */\r
-\r
-void Board_uartPinmxCfg()\r
-{\r
-    volatile uint32_t *addr = (volatile uint32_t *)(MAIN_CTRL_PINCFG_BASE + MAIN_UART0_RXD);\r
-    uint32_t i;\r
-\r
-    for (i = 0; i < 8; i++)\r
-    {\r
-        *addr++ = 0x54000;\r
-    }\r
-}\r
-\r
-void Board_ospiPinmxCfg()\r
-{\r
-    volatile uint32_t *addr = (volatile uint32_t *)MAIN_CTRL_PINCFG_BASE;\r
-    uint32_t ospiData[15] =\r
-    {\r
-        0x24000, 0x64000, 0x264000, 0x54000,\r
-        0x54000, 0x54000, 0x054000, 0x54000,\r
-        0x54000, 0x54000, 0x054000, 0x14000,\r
-        0x14000, 0x04002, 0x4001\r
-    };\r
-    uint32_t i;\r
-\r
-    for (i = 0; i < 15; i++)\r
-    {\r
-        *addr++ = ospiData[i];\r
-    }\r
-}\r
-\r
-void Board_spiPinmxCfg()\r
-{\r
-    volatile uint32_t *addr = (volatile uint32_t *)(MAIN_CTRL_PINCFG_BASE + MAIN_SPI0_CS0);\r
-    uint32_t spiData[5] =\r
-    {\r
-        PIN_MODE(0) | ((~PIN_PULL_DISABLE) & (PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE)), /* SPI0_CS0 */\r
-        PIN_MODE(0) | ((~PIN_PULL_DISABLE) & (PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE)), /* SPI0_CS1 */\r
-        PIN_MODE(0) | ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION)),  /* SPI0_CLK */\r
-        PIN_MODE(0) | ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION)),  /* SPI0_D0 */\r
-        PIN_MODE(0) | ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION))   /* SPI0_D1 */\r
-     };\r
-    uint32_t i;\r
-\r
-    for (i = 0; i < 5; i++)\r
-    {\r
-        *addr++ = spiData[i];\r
-    }\r
-}\r
-\r
-void Board_gpmcPinmxCfg()\r
-{\r
-    volatile uint32_t *addr = (volatile uint32_t *)(MAIN_CTRL_PINCFG_BASE + MAIN_GPMC0_AD0);\r
-    uint32_t gpmcData[69] =\r
-    {\r
-        0x50000, 0x50000, 0x50000, 0x50000,\r
-        0x40000, 0x40000, 0x50000, 0x50000,\r
-        0x50000, 0x50000, 0x50000, 0x50000,\r
-        0x50000, 0x50000, 0x50000, 0x50000,\r
-        0x50004, 0x50000, 0x40000, 0x40000,\r
-        0x40000, 0x40000, 0x40000, 0x60000,\r
-        0x60000, 0x40000, 0x50000, 0x40000,\r
-        0x40000, 0x40000, 0x40000, 0x50008,\r
-        0x50008, 0x50008, 0x50008, 0x50008,\r
-        0x50008, 0x50008, 0x50008, 0x50008,\r
-        0x50008, 0x50008, 0x50008, 0x50008,\r
-        0x50008, 0x50008, 0x50008, 0x40008,\r
-        0x50008, 0x50008, 0x40008, 0x60008,\r
-        0x40008, 0x40008, 0x40008, 0x40008,\r
-        0x40008, 0x40008, 0x40008, 0x40008,\r
-        0x40008, 0x40008, 0x40008, 0x40008,\r
-        0x40008, 0x40008, 0x40008, 0x40008,\r
-        0x40008\r
-    };\r
-    uint32_t i;\r
-\r
-    for (i = 0; i < 69; i++)\r
-    {\r
-        *addr++ = gpmcData[i];\r
-    }\r
-}\r
-\r
-#endif  /* #ifdef SIM_BUILD */\r
-#endif  /* #ifndef BUILD_M4F */\r
-\r
 /* Default pinmux configuration of UART Tx pin used by ROM/SBL */\r
 #define BOARD_UART_TX_PINMUX_VAL            (PIN_MODE(0) | ((PIN_PULL_DISABLE) & \\r
                                                  (~PIN_PULL_DIRECTION & ~PIN_INPUT_ENABLE)))\r
@@ -324,14 +62,6 @@ Board_STATUS Board_pinmuxConfig (void)
     HW_WR_REG32(BOARD_UART_TX_LOCK_KICK_ADDR, KICK0_UNLOCK_VAL);\r
     HW_WR_REG32(BOARD_UART_TX_LOCK_KICK_ADDR + 4U, KICK1_UNLOCK_VAL);\r
 \r
-#ifdef SIM_BUILD\r
-    Board_uartPinmxCfg();\r
-    Board_ospiPinmxCfg();\r
-    Board_spiPinmxCfg();\r
-    Board_gpmcPinmxCfg();\r
-       set_pinmux_board(PINMUX_MAIN_ICSSG0_MII0_APP2_array_board, (sizeof(PINMUX_MAIN_ICSSG0_MII0_APP2_array_board)/sizeof(pinmux_t)));\r
-       set_pinmux_board(PINMUX_MAIN_ICSSG0_MII1_APP2_array_board, (sizeof(PINMUX_MAIN_ICSSG0_MII1_APP2_array_board)/sizeof(pinmux_t)));\r
-#else\r
     pinmuxModuleCfg_t* pModuleData = NULL;\r
     pinmuxPerCfg_t* pInstanceData = NULL;\r
     int32_t i, j, k;\r
@@ -369,7 +99,6 @@ Board_STATUS Board_pinmuxConfig (void)
             }\r
         }\r
     }\r
-#endif /* #ifdef SIM_BUILD */\r
 #endif /* #ifndef BUILD_M4F */\r
     return BOARD_SOK;\r
 }\r
index d981625db753cca8d7b1d38142682d539d8e34db..20b9c27108474216f4961ed0ee9d1810de3c995e 100644 (file)
@@ -53,15 +53,6 @@ extern "C" {
 \r
 #define BOARD_SOC_DDR_START_ADDR                        (0x80000000U)\r
 \r
-#ifdef SIM_BUILD\r
-/* Memory sections */\r
-#define BOARD_DDR_START_ADDR                            (0x90000000U)\r
-#define BOARD_DDR_SIZE                                  (512* 1024 * 1024UL)\r
-#define BOARD_DDR_END_ADDR                              (0x900FFFFFU)\r
-\r
-/* Note with ECC enabled, all memory is not usable: 1/8 memory used for inline ECC */\r
-#define BOARD_DDR_ECC_END_ADDR                          (0x9006FFFFU)\r
-#else\r
 /* Memory sections */\r
 #define BOARD_DDR_START_ADDR                            (0x80000000U)\r
 #define BOARD_DDR_SIZE                                  (2048 * 1024 * 1024UL)\r
@@ -69,7 +60,6 @@ extern "C" {
 \r
 /* Note with ECC enabled, all memory is not usable: 1/8 memory used for inline ECC */\r
 #define BOARD_DDR_ECC_END_ADDR                          (0xF1FFFFFFU)\r
-#endif /* SIM_BUILD */\r
 \r
 /* UART LLD instance number for MAIN UART0 port */\r
 #define BOARD_UART0_INSTANCE                            (0U)\r
@@ -81,15 +71,10 @@ extern "C" {
 #define BOARD_UART3_INSTANCE                            (3U)\r
 /* UART LLD instance number for MCU UART0 port */\r
 #define BOARD_MCU_UART0_INSTANCE                        (7U)\r
+/* MCU UART LLD instance number 1 */\r
+#define BOARD_MCU_UART1_INSTANCE                        (8U)\r
 \r
 /* UART LLD instance number for primary UART port */\r
-#ifdef SIM_BUILD\r
-#if defined (BUILD_MCU)\r
-#define BOARD_UART_INSTANCE                             (BOARD_UART0_INSTANCE)\r
-#else\r
-#define BOARD_UART_INSTANCE                             (BOARD_UART1_INSTANCE)\r
-#endif\r
-#else\r
 #if defined (BUILD_MCU)\r
 #define BOARD_UART_INSTANCE (BOARD_UART0_INSTANCE)\r
 #elif defined (BUILD_MPU)\r
@@ -99,7 +84,6 @@ extern "C" {
 #else\r
 #define BOARD_UART_INSTANCE (BOARD_UART0_INSTANCE)  /* Use MAIN UART0 by default */\r
 #endif\r
-#endif\r
 \r
 /* Clock frequency for UART module */\r
 #define BOARD_UART_CLK_MAIN                             (48000000U)\r
@@ -124,7 +108,7 @@ extern "C" {
 #define BOARD_I2C_EEPROM_ADDR                           (0x51U)\r
 \r
 /* QSPI instance number */\r
-#define BOARD_SPI_NOR_INSTANCE                          (1U)\r
+#define BOARD_SPI_NOR_INSTANCE                          (0U)\r
 \r
 /* I2C Instance connected to clock generator */\r
 #define BOARD_CLOCK_GENERATOR_INSTANCE                  (0U)\r
@@ -139,7 +123,7 @@ extern "C" {
 #define BOARD_OSPI_NOR_INSTANCE                         (0U)\r
 \r
 /* I2C instance connected to IO Expander */\r
-#define BOARD_I2C_IOEXP_DEVICE1_INSTANCE                (0U)\r
+#define BOARD_I2C_IOEXP_DEVICE1_INSTANCE                (1U)\r
 #define BOARD_I2C_IOEXP_DEVICE2_INSTANCE                (0U)\r
 #define BOARD_I2C_IOEXP_DEVICE3_INSTANCE                (3U)\r
 #define BOARD_I2C_IOEXP_DEVICE4_INSTANCE                (0U)\r
@@ -148,13 +132,9 @@ extern "C" {
 #define BOARD_I2C_VIDEO_IOEXP_DEVICE_INSTANCE           (0U)\r
 \r
 /* I2C IO Expander Slave devices */\r
-#define BOARD_I2C_IOEXP_DEVICE1_ADDR                    (0x20U)\r
-#define BOARD_I2C_IOEXP_DEVICE2_ADDR                    (0x22U)\r
-#define BOARD_I2C_IOEXP_DEVICE3_ADDR                    (0x20U)\r
-#define BOARD_I2C_IOEXP_DEVICE4_ADDR                    (0x20U)\r
-#define BOARD_I2C_IOEXP_DEVICE5_ADDR                    (0x20U)\r
-#define BOARD_I2C_AUDIO_IOEXP_DEVICE_ADDR               (0x21U)\r
-#define BOARD_I2C_VIDEO_IOEXP_DEVICE_ADDR               (0x21U)\r
+#define BOARD_I2C_IOEXP_DEVICE1_ADDR                    (0x22U)\r
+/* Used to configure Ethernet PHY LED's */\r
+#define BOARD_I2C_IOEXP_DEVICE2_ADDR                    (0x60U)\r
 \r
 /* OSPI instance number */\r
 #define BOARD_OSPI_INSTANCE                             (0)\r
@@ -180,13 +160,20 @@ extern "C" {
 /* I2C address Board Presence Circuit */\r
 #define BOARD_PRES_DETECT_SLAVE_ADDR                    (0x38U)\r
 \r
+/* Pin and port numbers for TEST_LED1 on CP board */\r
+#define BOARD_GPIO_TEST_LED1_PORT_NUM                      (0)       /* Port 0 */\r
+#define BOARD_GPIO_TEST_LED1_PIN_NUM                    (0x01)    /* Pin 1  */\r
+/* Pin and port numbers for TEST_LED2 on CP board */\r
+#define BOARD_MCU_GPIO_TEST_LED2_PORT_NUM               (0)       /* Port 0 */\r
+#define BOARD_MCU_GPIO_TEST_LED2_PIN_NUM                (0x05)    /* Pin 5  */\r
+\r
 /* User LED Pin Details */\r
 #define BOARD_I2C_USER_LED_INSTANCE                     (0U)\r
 \r
 #define BOARD_USER_LED1                                 (1U) /* Main GPIO0_1 */\r
 #define BOARD_USER_LED2                                 (1U) /* MCU GPIO0_1 */\r
 \r
-#define BOARD_ICSS_EMAC_PORT_START                      (0X0U)\r
+#define BOARD_ICSS_EMAC_PORT_START                      (0x0U)\r
 #define BOARD_ICSS_EMAC_PORT_END                        (0x5U)\r
 #define BOARD_ICSS_EMAC_PORT_MAX                        (0x6U)\r
 #define BOARD_MCU_EMAC_PORT_MAX                         (0x1U)\r
@@ -194,80 +181,84 @@ extern "C" {
 \r
 \r
 /* ICSS2 EMAC PHY register address */\r
-#define BOARD_ICSS2_EMAC_PHY0_ADDR                      (0x0) //J7ES_TODO: need to update\r
-#define BOARD_ICSS2_EMAC_PHY1_ADDR                      (0x3u) //J7ES_TODO: need to update\r
+#define BOARD_ICSS2_EMAC_PHY0_ADDR                      (0x0)\r
+#define BOARD_ICSS2_EMAC_PHY1_ADDR                      (0x3u)\r
+\r
 \r
+/* PRG1_RGMII2_RESETn */\r
+#define BOARD_GPIO_IOEXP_ICSS1_EMAC_RST_PORT_NUM        (0)\r
+#define BOARD_GPIO_IOEXP_ICSS1_EMAC_RST_PIN_NUM         (4)\r
 \r
-/* PRG2_RGMII_RESETn */\r
+/* PRG1_RGMII1_RESETn */\r
 #define BOARD_GPIO_IOEXP_ICSS2_EMAC_RST_PORT_NUM        (0)\r
 #define BOARD_GPIO_IOEXP_ICSS2_EMAC_RST_PIN_NUM         (3)\r
 \r
-/* PRG2_RGMII_INTn */\r
-#define BOARD_GPIO_ICSS2_EMAC_INT_PORT_NUM              (0) /* WKUP_GPIO0_24  */ //J7ES_TODO: need to update\r
-#define BOARD_GPIO_ICSS2_EMAC_INT_PIN_NUM               (0x46) //J7ES_TODO: need to update\r
+/* PRG1_RGMII_INTn */\r
+#define BOARD_GPIO_ICSS2_EMAC_INT_PORT_NUM              (0) /* GPIO1_70  */\r
+#define BOARD_GPIO_ICSS2_EMAC_INT_PIN_NUM               (0x46)\r
 \r
-/* PRG2_ETH1_LED_LINK */\r
-#define BOARD_GPIO_ICSS2_EMAC_PHY0_LED_LINK_PORT_NUM    (0) /* GPIO1_13 */ //J7ES_TODO: need to update\r
-#define BOARD_GPIO_ICSS2_EMAC_PHY0_LED_LINK_PIN_NUM     (0) //J7ES_TODO: need to update\r
+/* PRG1_ETH1_LED_LINK */\r
+#define BOARD_GPIO_ICSS2_EMAC_PHY0_LED_LINK_PORT_NUM    (0)  /* PRG1_PRU0_GPO8 - GPIO0_53 */\r
+#define BOARD_GPIO_ICSS2_EMAC_PHY0_LED_LINK_PIN_NUM     (35)\r
 \r
-/* PRG2_ETH2_LED_LINK */\r
-#define BOARD_GPIO_ICSS2_EMAC_PHY1_LED_LINK_PORT_NUM    (0) /* GPIO1_14 */ //J7ES_TODO: need to update\r
-#define BOARD_GPIO_ICSS2_EMAC_PHY1_LED_LINK_PIN_NUM     (0) //J7ES_TODO: need to update\r
+/* PRG1_ETH2_LED_LINK */\r
+#define BOARD_GPIO_ICSS2_EMAC_PHY1_LED_LINK_PORT_NUM    (0)  /* PRG1_PRU1_GPO8 - GPIO0_73 */\r
+#define BOARD_GPIO_ICSS2_EMAC_PHY1_LED_LINK_PIN_NUM     (49)\r
 \r
 /* GPIO to drive PRG2 LED0 */\r
-#define BOARD_GPIO_ICSS2_EMAC_LED0_PORT_NUM             (0) /* WKUP_GPIO0_13 */ //J7ES_TODO: need to update\r
-#define BOARD_GPIO_ICSS2_EMAC_LED0_PIN_NUM              (0) //J7ES_TODO: need to update\r
+#define BOARD_GPIO_ICSS2_EMAC_LED0_PORT_NUM             (0) //AM64x_TODO: need to update\r
+#define BOARD_GPIO_ICSS2_EMAC_LED0_PIN_NUM              (0) //AM64x_TODO: need to update\r
 \r
 /* GPIO to drive PRG2 LED1 */\r
-#define BOARD_GPIO_ICSS2_EMAC_LED1_PORT_NUM             (0) /* WKUP_GPIO0_0 */ //J7ES_TODO: need to update\r
-#define BOARD_GPIO_ICSS2_EMAC_LED1_PIN_NUM              (0) //J7ES_TODO: need to update\r
+#define BOARD_GPIO_ICSS2_EMAC_LED1_PORT_NUM             (0) //AM64x_TODO: need to update\r
+#define BOARD_GPIO_ICSS2_EMAC_LED1_PIN_NUM              (0) //AM64x_TODO: need to update\r
 \r
 /* GPIO to drive PRG2 LED2 */\r
-#define BOARD_GPIO_ICSS2_EMAC_LED2_PORT_NUM             (0) /* WKUP_GPIO0_1 */ //J7ES_TODO: need to update\r
-#define BOARD_GPIO_ICSS2_EMAC_LED2_PIN_NUM              (0) //J7ES_TODO: need to update\r
+#define BOARD_GPIO_ICSS2_EMAC_LED2_PORT_NUM             (0) //AM64x_TODO: need to update\r
+#define BOARD_GPIO_ICSS2_EMAC_LED2_PIN_NUM              (0) //AM64x_TODO: need to update\r
 \r
 /* GPIO to drive PRG2 LED3 */\r
-#define BOARD_GPIO_ICSS2_EMAC_LED3_PORT_NUM             (0) /* WKUP_GPIO0_27 */ //J7ES_TODO: need to update\r
-#define BOARD_GPIO_ICSS2_EMAC_LED3_PIN_NUM              (0) //J7ES_TODO: need to update\r
+#define BOARD_GPIO_ICSS2_EMAC_LED3_PORT_NUM             (0) //AM64x_TODO: need to update\r
+#define BOARD_GPIO_ICSS2_EMAC_LED3_PIN_NUM              (0) //AM64x_TODO: need to update\r
 \r
 /* MCU EMAC PHY MDIO address */\r
-#define BOARD_MCU_EMAC_PHY_ADDR                         (0U) //J7ES_TODO: need to update\r
+#define BOARD_MCU_EMAC_PHY_ADDR                         (0U)\r
 \r
 /* MCU EMAC MAX REG DUMP */\r
-#define BOARD_MCU_EMAC_REG_DUMP_MAX                     (0) //J7ES_TODO: need to update\r
+#define BOARD_MCU_EMAC_REG_DUMP_MAX                     (16)\r
 \r
 /* MCU EMAC PHY register address definitions for reading strap values */\r
-#define BOARD_MCU_EMAC_STRAP_STS1_ADDR                  (0) //J7ES_TODO: need to update\r
-#define BOARD_MCU_EMAC_STRAP_STS2_ADDR                  (0) //J7ES_TODO: need to update\r
+#define BOARD_MCU_EMAC_STRAP_STS1_ADDR                  (0x6EU)\r
+#define BOARD_MCU_EMAC_STRAP_STS2_ADDR                  (0x6FU)\r
 \r
 /* MCU EMAC PHY register address definitions for reading strap values */\r
-#define BOARD_ICSS_EMAC_STRAP_STS1_ADDR                 (0) //J7ES_TODO: need to update\r
-#define BOARD_ICSS_EMAC_STRAP_STS2_ADDR                 (0) //J7ES_TODO: need to update\r
+#define BOARD_ICSS_EMAC_STRAP_STS1_ADDR                 (0x6EU)\r
+#define BOARD_ICSS_EMAC_STRAP_STS2_ADDR                 (0x6FU)\r
 \r
-/* MCU_ETH1_RESETn */\r
-#define BOARD_GPIO_IOEXP_MCU_EMAC_RST_PORT_NUM          (0) //J7ES_TODO: need to update\r
-#define BOARD_GPIO_IOEXP_MCU_EMAC_RST_PIN_NUM           (0) //J7ES_TODO: need to update\r
+/* MCU_ETH1_RESETn --> GPIO_CPSW1_RST */\r
+#define BOARD_GPIO_IOEXP_MCU_EMAC_RST_PORT_NUM          (0)\r
+#define BOARD_GPIO_IOEXP_MCU_EMAC_RST_PIN_NUM           (2)\r
 \r
-/* MCU_ETH1_INTn */\r
-#define BOARD_GPIO_MCU_EMAC_INT_PORT_NUM                (0) /* WKUP_GPIO0_32 */ //J7ES_TODO: need to update\r
-#define BOARD_GPIO_MCU_EMAC_INT_PIN_NUM                 (0) //J7ES_TODO: need to update\r
+/* MCU_ETH1_INTn -> CPSW_RGMII_INTn */\r
+#define BOARD_GPIO_MCU_EMAC_INT_PORT_NUM                (1) /* EXTINTn - GPIO1_70 */\r
+#define BOARD_GPIO_MCU_EMAC_INT_PIN_NUM                 (46)\r
 \r
 /* AUTOMATION HEADER */\r
-#define BOARD_TEST_HEADER_I2C_INSTANCE                  (2U)\r
+#define BOARD_TEST_HEADER_I2C_INSTANCE                  (1U)\r
 #define BOARD_I2C_BOOT_MODE_SW_ADDR                     (0x22U)\r
 \r
-/* TEST_GPIO1 */\r
-#define BOARD_GPIO_IOEXP_TEST_PORT_NUM                  (0) //J7ES_TODO: need to update\r
-#define BOARD_GPIO_IOEXP_TEST_PIN_NUM                   (0) //J7ES_TODO: need to update\r
+/* TEST_GPIO2 */\r
+#define BOARD_GPIO_IOEXP_TEST_PORT_NUM                  (1)\r
+#define BOARD_GPIO_IOEXP_TEST_PIN_NUM                   (5)\r
 \r
 /* Temperature sensor i2c instance */\r
-#define BOARD_TEMP_SENSOR_I2C_INSTANCE                  (2U)\r
+#define BOARD_TEMP_SENSOR_I2C_INSTANCE                  (1U)\r
 \r
 /* Temperature sensor slave device addresses */\r
 #define BOARD_TEMP_SENSOR_I2C_SLAVE_DEVICE1_ADDR        (0x48U)\r
 #define BOARD_TEMP_SENSOR_I2C_SLAVE_DEVICE2_ADDR        (0x49U)\r
 \r
-#define BOARD_I2C_CURRENT_MONITOR_INSTANCE              (2U)\r
+#define BOARD_I2C_CURRENT_MONITOR_INSTANCE              (1U)\r
 \r
 /* I2C instance connected to OLED DISPLAY */\r
 #define BOARD_OLED_DISPLAY_INSTANCE                     (1)\r
@@ -326,6 +317,21 @@ extern "C" {
 \r
 #define BOARD_EEPROM_HEADER_ADDR                        (0U)\r
 \r
+/* I2C instance connected to OLED DISPLAY */\r
+#define BOARD_OLED_DISPLAY_INSTANCE                     (1)\r
+\r
+/* PinMux data to be programmed to configure a pin to be a GPIO */\r
+#define PINMUX_GPIO_CFG                                 (0x00050007U)\r
+\r
+/* Clock frequency for UART module */\r
+#define BOARD_UART_CLK_MAIN                             (48000000U) //AM64x_TODO: Need to cross check\r
+\r
+/** @brief Number of UART instances */\r
+#define BOARD_UART_PER_CNT                              (6U) //AM64x_TODO: Need to verify the Value\r
+\r
+/* SPI instance connected to LED Driver */\r
+#define BOARD_SPI1_INSTANCE                              (1U)\r
+\r
 /* PinMux data to be programmed to configure a pin to be a GPIO */\r
 #define PINMUX_GPIO_CFG                                 (0x00050007U)\r
 \r
index d609c6f03d94c470d6c56c4050e0d1e3db127ce1..4210be6e6dd42a41a000cdb95bcdfae29d4775de 100755 (executable)
@@ -93,7 +93,7 @@ NOR_Config Nor_config[BOARD_FLASH_NOR_INTF_MAX] =
         NULL
     }
 };
-#elif defined (am64x_evm) || defined(am64x_svb)
+#elif defined(am64x_svb)
 NOR_Config Nor_config[BOARD_FLASH_NOR_INTF_MAX] =
 {
     {
@@ -150,6 +150,25 @@ NOR_Config Nor_config[BOARD_FLASH_NOR_INTF_MAX] =
         &Nor_hpfFxnTable
     }
 };
+#elif defined(am64x_evm)
+NOR_Config Nor_config[BOARD_FLASH_NOR_INTF_MAX] =
+{
+    {
+        NULL
+    },
+    {
+        NULL
+    },
+    {
+        NULL
+    },
+    {
+        &Nor_xspiFxnTable
+    },
+    {
+        NULL
+    }
+};
 #elif defined (tpr12_evm) || defined (tpr12_qt)
 NOR_Config Nor_config[BOARD_FLASH_NOR_INTF_MAX] =
 {
index 4a84d462989b430f099c2de8f971b6d703492df5..a2b7b7be1635301894a6a630b8a0c99af3a6f6a6 100644 (file)
 #include <ti/board/src/flash/nor/nor.h>
 #include <ti/drv/spi/SPI.h>
 #include <ti/drv/spi/soc/SPI_soc.h>
-#if defined(am64x_evm) || defined(am64x_svb)
-#include <ti/board/src/flash/nor/device/m35xu256.h>
-#else
 #include <ti/board/src/flash/nor/device/m35xu512.h>
-#endif
 #include <ti/board/src/flash/nor/ospi/nor_spi_phy_tune.h>
 
 /**************************************************************************
index 402c5bf71f31850f2bc4d8f7a9f24fda54def5b7..ff2e3f97ff68cdb569c3d1554de4636a8b7c6b21 100755 (executable)
 #include <ti/drv/spi/soc/SPI_soc.h>\r
 #include <ti/csl/soc.h>\r
 \r
-#if defined (j7200_evm)\r
+#if defined (j7200_evm) \r
 /* SPI entry offset is at index 5 of SPI config array */\r
 #define SPI_CONFIG_OFFSET     (5U)\r
+#elif defined (am64x_evm) \r
+/* SPI entry offset is at index 7 of SPI config array */\r
+#define SPI_CONFIG_OFFSET     (7U)\r
 #else\r
 #define SPI_CONFIG_OFFSET     CSL_MCSPI_PER_CNT\r
 #endif\r
index da6ad4919c61a32ebc61cc05a9c7cb3acc964864..28ddde5696d52b9164b72ba0351c0639ad14bcdf 100755 (executable)
@@ -47,7 +47,7 @@
 #include <ti/board/src/flash/nor/nor.h>\r
 #include <ti/drv/spi/SPI.h>\r
 #include <ti/drv/spi/soc/SPI_soc.h>\r
-#if defined(j7200_evm)\r
+#if defined(j7200_evm) || defined(am64x_evm)\r
 #include <ti/board/src/flash/nor/device/s28hs512t.h>\r
 #endif\r
 #include <ti/board/src/flash/nor/ospi/nor_spi_phy_tune.h>\r
index 55d2f6e3fcf976485dd11fd446d01f11bc93a4f8..296b0a6cbea80ad551378e697a45fae50d0667e9 100755 (executable)
@@ -75,7 +75,7 @@ endif
 endif
 
 
-ifeq ($(BOARD),$(filter $(BOARD), am65xx_idk am65xx_evm j721e_sim j721e_evm am64x_evm am64x_svb))
+ifeq ($(BOARD),$(filter $(BOARD), am65xx_idk am65xx_evm j721e_sim j721e_evm am64x_svb))
 SRCDIR += src/flash/nor src/flash/nor/device src/flash/nor/ospi
 INCDIR += src/flash/nor src/flash/nor/device src/flash/nor/ospi
 SRCS_COMMON += nor_ospi.c nor.c nor_spi_patterns.c nor_spi_phy_tune.c
@@ -83,14 +83,14 @@ PACKAGE_SRCS_COMMON += src/flash/nor/nor.c src/flash/nor/nor.h
 PACKAGE_SRCS_COMMON += src/flash/nor/ospi/nor_ospi.c src/flash/nor/ospi/nor_ospi.h
 PACKAGE_SRCS_COMMON += src/flash/nor/ospi/nor_spi_patterns.c src/flash/nor/ospi/nor_spi_patterns.h
 PACKAGE_SRCS_COMMON += src/flash/nor/ospi/nor_spi_phy_tune.c src/flash/nor/ospi/nor_spi_phy_tune.h
-ifeq ($(BOARD),$(filter $(BOARD), am64x_evm am64x_svb))
+ifeq ($(BOARD),$(filter $(BOARD), am64x_svb))
 PACKAGE_SRCS_COMMON += src/flash/nor/device/m35xu256.h
 else
 PACKAGE_SRCS_COMMON += src/flash/nor/device/m35xu512.h
 endif
 endif
 
-ifeq ($(BOARD),$(filter $(BOARD), j7200_evm))
+ifeq ($(BOARD),$(filter $(BOARD), j7200_evm am64x_evm))
 SRCDIR += src/flash/nor src/flash/nor/device src/flash/nor/ospi
 INCDIR += src/flash/nor src/flash/nor/device src/flash/nor/ospi
 SRCS_COMMON += nor_xspi.c nor.c nor_spi_patterns.c nor_spi_phy_tune.c
index 81720209e596bf8f7eda57ff7526cbe2619cfd3d..a0b567a0791ebc9168c40240f7de4a5ddef595d2 100644 (file)
@@ -147,8 +147,6 @@ CFLAGS_GLOBAL_j7200          = -DSOC_J7200
 CFLAGS_GLOBAL_am64x          = -DSOC_AM64X
 CFLAGS_GLOBAL_tpr12          = -DSOC_TPR12
 # The below flags are only defined for testing on VLAB or QT/Zebu and will need to be removed when testing on EVM
-CFLAGS_GLOBAL_am64x         += -DSIM_BUILD
-CFLAGS_GLOBAL_am64x_evm     += -DSIM_BUILD
 CFLAGS_GLOBAL_am64x_svb     += -DSIM_BUILD
 CFLAGS_GLOBAL_tpr12_qt      += -DSIM_BUILD
 
index bb3a5f84255157009a4159c027461f1998b068ae..1413eff58d3d14e7874caa9d47837700f27d2877 100755 (executable)
@@ -67,7 +67,7 @@
 #include <ti/board/board_cfg.h>
 #include <ti/board/src/flash/include/board_flash.h>
 #include <ti/board/src/flash/nor/ospi/nor_spi_patterns.h>
-#if defined(SOC_J7200)
+#if defined(SOC_J7200) || defined(SOC_AM64X)
 #include <ti/board/src/flash/nor/ospi/nor_xspi.h>
 #else
 #include <ti/board/src/flash/nor/ospi/nor_ospi.h>
@@ -85,9 +85,7 @@
 #ifdef SPI_DMA_ENABLE
 #include <ti/drv/udma/udma.h>
 #endif
-#if defined(SOC_AM64X)
-#include <ti/board/src/flash/nor/device/m35xu256.h>
-#elif defined(SOC_J7200)
+#if defined(SOC_AM64X) || defined(SOC_J7200)
 #include <ti/board/src/flash/nor/device/s28hs512t.h>
 #else
 #include <ti/board/src/flash/nor/device/m35xu512.h>