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raw | patch | inline | side by side (parent: 8348f39)
| author | Jonathan Bergsagel <jbergsagel@ti.com> | |
| Thu, 15 Oct 2020 23:15:07 +0000 (18:15 -0500) | ||
| committer | Jonathan Bergsagel <jbergsagel@ti.com> | |
| Fri, 16 Oct 2020 04:02:56 +0000 (23:02 -0500) |
Bootloader image sizes are larger now, with the added code
for sciclient and rm_pm_hal, due to required HSM rearch.
SBL image size was going beyond its original allotted space
in the flash, so we have to update the flash locations to
the following now:
Location Image
-------- ------------------------
00_0000 SBL (tiboot3.bin)
08_0000 SYSFW (sysfw.bin)
10_0000 APP (*.appimage)
1C_0000 (optional) XIP boot test
This also allows us to align image locations with multiples
of 256KB sections in the flash for better flash arrangement.
Signed-off-by: Jonathan Bergsagel <jbergsagel@ti.com>
for sciclient and rm_pm_hal, due to required HSM rearch.
SBL image size was going beyond its original allotted space
in the flash, so we have to update the flash locations to
the following now:
Location Image
-------- ------------------------
00_0000 SBL (tiboot3.bin)
08_0000 SYSFW (sysfw.bin)
10_0000 APP (*.appimage)
1C_0000 (optional) XIP boot test
This also allows us to align image locations with multiples
of 256KB sections in the flash for better flash arrangement.
Signed-off-by: Jonathan Bergsagel <jbergsagel@ti.com>
diff --git a/packages/ti/boot/sbl/example/k3MulticoreApp/am65xx/mcuXiplinker.lds b/packages/ti/boot/sbl/example/k3MulticoreApp/am65xx/mcuXiplinker.lds
index 3d1a605c9c1e1b8a12f6acfd1fed0ea6531f6728..60c02da35ac86b532d2ce4096ab7ac04867abbba 100644 (file)
MEMORY
{
- OSPI_MCU1_CPU0_XIP_VEC : origin=0x500e0000 length=0x40 /* 64B */
- OSPI_MCU1_CPU0_XIP : origin=0x500e0040 length=0x2000 - 0x40 /* 8KB - 64B*/
+ OSPI_MCU1_CPU0_XIP_VEC : origin=0x501c0000 length=0x40 /* 64B */
+ OSPI_MCU1_CPU0_XIP : origin=0x501c0040 length=0x2000 - 0x40 /* 8KB - 64B*/
OCMRAM_SBL_SYSFW : origin=0x41C3E000 length=0x2000 - 0x800 /* 8KB */
}
diff --git a/packages/ti/boot/sbl/example/k3MulticoreApp/am65xx/xip_entry.lds b/packages/ti/boot/sbl/example/k3MulticoreApp/am65xx/xip_entry.lds
index e69d1a5cf2f425bad3d7922e8a05224b1c4b5041..99fec714dc0e04006f9507498b7a98214d45bc2c 100644 (file)
/* (c) Texas Instruments 2019, All rights reserved. */
/*----------------------------------------------------------------------------*/
-_xipAppEntry=0x500e0000;
+_xipAppEntry=0x501c0000;
--entry_point=_xipAppEntry
--retain="_xipAppEntry"
--retain="_xip_stub"
diff --git a/packages/ti/boot/sbl/example/k3MulticoreApp/j7200/mcuXiplinker.lds b/packages/ti/boot/sbl/example/k3MulticoreApp/j7200/mcuXiplinker.lds
index 3d1a605c9c1e1b8a12f6acfd1fed0ea6531f6728..60c02da35ac86b532d2ce4096ab7ac04867abbba 100644 (file)
MEMORY
{
- OSPI_MCU1_CPU0_XIP_VEC : origin=0x500e0000 length=0x40 /* 64B */
- OSPI_MCU1_CPU0_XIP : origin=0x500e0040 length=0x2000 - 0x40 /* 8KB - 64B*/
+ OSPI_MCU1_CPU0_XIP_VEC : origin=0x501c0000 length=0x40 /* 64B */
+ OSPI_MCU1_CPU0_XIP : origin=0x501c0040 length=0x2000 - 0x40 /* 8KB - 64B*/
OCMRAM_SBL_SYSFW : origin=0x41C3E000 length=0x2000 - 0x800 /* 8KB */
}
diff --git a/packages/ti/boot/sbl/example/k3MulticoreApp/j7200/xip_entry.lds b/packages/ti/boot/sbl/example/k3MulticoreApp/j7200/xip_entry.lds
index e69d1a5cf2f425bad3d7922e8a05224b1c4b5041..99fec714dc0e04006f9507498b7a98214d45bc2c 100644 (file)
/* (c) Texas Instruments 2019, All rights reserved. */
/*----------------------------------------------------------------------------*/
-_xipAppEntry=0x500e0000;
+_xipAppEntry=0x501c0000;
--entry_point=_xipAppEntry
--retain="_xipAppEntry"
--retain="_xip_stub"
diff --git a/packages/ti/boot/sbl/example/k3MulticoreApp/j721e/mcuXiplinker.lds b/packages/ti/boot/sbl/example/k3MulticoreApp/j721e/mcuXiplinker.lds
index 3d1a605c9c1e1b8a12f6acfd1fed0ea6531f6728..60c02da35ac86b532d2ce4096ab7ac04867abbba 100644 (file)
MEMORY
{
- OSPI_MCU1_CPU0_XIP_VEC : origin=0x500e0000 length=0x40 /* 64B */
- OSPI_MCU1_CPU0_XIP : origin=0x500e0040 length=0x2000 - 0x40 /* 8KB - 64B*/
+ OSPI_MCU1_CPU0_XIP_VEC : origin=0x501c0000 length=0x40 /* 64B */
+ OSPI_MCU1_CPU0_XIP : origin=0x501c0040 length=0x2000 - 0x40 /* 8KB - 64B*/
OCMRAM_SBL_SYSFW : origin=0x41C3E000 length=0x2000 - 0x800 /* 8KB */
}
diff --git a/packages/ti/boot/sbl/example/k3MulticoreApp/j721e/xip_entry.lds b/packages/ti/boot/sbl/example/k3MulticoreApp/j721e/xip_entry.lds
index e69d1a5cf2f425bad3d7922e8a05224b1c4b5041..99fec714dc0e04006f9507498b7a98214d45bc2c 100644 (file)
/* (c) Texas Instruments 2019, All rights reserved. */
/*----------------------------------------------------------------------------*/
-_xipAppEntry=0x500e0000;
+_xipAppEntry=0x501c0000;
--entry_point=_xipAppEntry
--retain="_xipAppEntry"
--retain="_xip_stub"
diff --git a/packages/ti/boot/sbl/src/hyperflash/sbl_hyperflash.c b/packages/ti/boot/sbl/src/hyperflash/sbl_hyperflash.c
index 8f2458587c024ce75874dd0e18183225ed7e2de4..1a6e9a0998f3c9cd732d8a58d30bf8ae7fcbd601 100644 (file)
/* Macro representing the offset where the App Image has to be written/Read from
* the HyperFlash.
*/
-#define HYPERFLASH_OFFSET_SI (0xC0000U)
-#define HYPERFLASH_OFFSET_SYSFW (0x40000U)
+#define HYPERFLASH_OFFSET_SI (0x100000U)
+#define HYPERFLASH_OFFSET_SYSFW (0x80000U)
uint32_t gBaseAddress = SBL_HYPERFLASH_BASE_ADDRESS;
index e4b0efedd2977bfaeac951de9fed08f4fcb5e95c..f1631c7308f2c1680a8308cb42f127225c8f6be9 100755 (executable)
/* Macro representing the offset where the App Image has to be written/Read from
the OSPI Flash.
*/
-#define OSPI_OFFSET_SI (0xA0000U)
-#define OSPI_OFFSET_SYSFW (0x40000U)
+#define OSPI_OFFSET_SI (0x100000U)
+#define OSPI_OFFSET_SYSFW (0x80000U)
#define OSPI_MPU_REGION_NUM (0x6)
#define OSPI_MPU_ENABLE_REGION (0x1)