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raw | patch | inline | side by side (parent: d137cf2)
raw | patch | inline | side by side (parent: d137cf2)
author | Aditya Wadhwa <a0485151@ti.com> | |
Wed, 10 Mar 2021 17:59:57 +0000 (23:29 +0530) | ||
committer | Ankur <ankurbaranwal@ti.com> | |
Thu, 11 Mar 2021 19:25:54 +0000 (13:25 -0600) |
- switched to macro instead of hard-coded values
- flag not working
Signed-off-by: Aditya Wadhwa <a0485151@ti.com>
- flag not working
Signed-off-by: Aditya Wadhwa <a0485151@ti.com>
packages/ti/drv/spi/src/v0/OSPI_v0.c | patch | blob | history | |
packages/ti/drv/spi/test/ospi_flash/src/main_ospi_flash_test.c | patch | blob | history |
index 322aead0057536259cd48254ad6e1390b8939cf4..545f102e512388de1cfee598e2f5524f245b914a 100755 (executable)
#define OSPI_CALIBRATE_DELAY (20U)
#define OSPI_XIP_SETUP_DELAY (250U)
#define OSPI_CALIBRATE_DELAY (20U)
#define OSPI_XIP_SETUP_DELAY (250U)
+/* Set the indirect trigger address offset at a non-cached location */
+#ifdef SPI_CACHE_ENABLE
+#if defined(SOC_J7200) || defined(SOC_AM64X)
+ #define OSPI_INDAC_TRIG_ADDR (0x3FC0000)
+#else
+ #define OSPI_INDAC_TRIG_ADDR (0x3FE0000)
+#endif
+#else
+ #define OSPI_INDAC_TRIG_ADDR (0x0000000)
+#endif
+
/* OSPI AM57x functions */
static void OSPI_close_v0(SPI_Handle handle);
static void OSPI_init_v0(SPI_Handle handle);
/* OSPI AM57x functions */
static void OSPI_close_v0(SPI_Handle handle);
static void OSPI_init_v0(SPI_Handle handle);
rdBytes = (rdBytes > object->readCountIdx) ? object->readCountIdx : rdBytes;
/* Read data from FIFO */
rdBytes = (rdBytes > object->readCountIdx) ? object->readCountIdx : rdBytes;
/* Read data from FIFO */
- CSL_ospiReadFifoData(hwAttrs->dataAddr+0x3FE0000, object->readBufIdx, rdBytes);
+ CSL_ospiReadFifoData(hwAttrs->dataAddr + OSPI_INDAC_TRIG_ADDR, object->readBufIdx, rdBytes);
object->readBufIdx += rdBytes;
object->readCountIdx -= rdBytes;
object->readBufIdx += rdBytes;
object->readCountIdx -= rdBytes;
}
}
rdBytes = object->readCountIdx;
}
}
rdBytes = object->readCountIdx;
- CSL_ospiReadFifoData(hwAttrs->dataAddr+0x3FE0000, object->readBufIdx, rdBytes);
+ CSL_ospiReadFifoData(hwAttrs->dataAddr + OSPI_INDAC_TRIG_ADDR, object->readBufIdx, rdBytes);
object->readBufIdx += rdBytes;
object->readCountIdx -= rdBytes;
}
object->readBufIdx += rdBytes;
object->readCountIdx -= rdBytes;
}
wrBytes = (wrBytes > object->writeCountIdx) ? object->writeCountIdx : wrBytes;
/* Write data to FIFO */
wrBytes = (wrBytes > object->writeCountIdx) ? object->writeCountIdx : wrBytes;
/* Write data to FIFO */
- CSL_ospiWriteFifoData(hwAttrs->dataAddr+0x3FE0000, object->writeBufIdx, wrBytes);
+ CSL_ospiWriteFifoData(hwAttrs->dataAddr + OSPI_INDAC_TRIG_ADDR, object->writeBufIdx, wrBytes);
object->writeBufIdx += wrBytes;
object->writeCountIdx -= wrBytes;
object->writeBufIdx += wrBytes;
object->writeCountIdx -= wrBytes;
(object->writeCountIdx <= (sramLevel * CSL_OSPI_FIFO_WIDTH)))
{
wrBytes = object->writeCountIdx;
(object->writeCountIdx <= (sramLevel * CSL_OSPI_FIFO_WIDTH)))
{
wrBytes = object->writeCountIdx;
- CSL_ospiWriteFifoData(hwAttrs->dataAddr+0x3FE0000, object->writeBufIdx, wrBytes);
+ CSL_ospiWriteFifoData(hwAttrs->dataAddr + OSPI_INDAC_TRIG_ADDR, object->writeBufIdx, wrBytes);
object->writeBufIdx += wrBytes;
object->writeCountIdx -= wrBytes;
}
object->writeBufIdx += wrBytes;
object->writeCountIdx -= wrBytes;
}
if (hwAttrs->dacEnable)
{
CSL_ospiSetIndTrigAddr((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr),
if (hwAttrs->dacEnable)
{
CSL_ospiSetIndTrigAddr((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr),
- 0x4000000);
+ 0x4000000);
}
else
{
CSL_ospiSetIndTrigAddr((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr),
}
else
{
CSL_ospiSetIndTrigAddr((const CSL_ospi_flash_cfgRegs *)(hwAttrs->baseAddr),
- 0x3FE0000);
+ OSPI_INDAC_TRIG_ADDR);
}
/* Disable write completion auto polling */
}
/* Disable write completion auto polling */
rdBytes = (rdBytes > remaining) ? remaining : rdBytes;
/* Read data from FIFO */
rdBytes = (rdBytes > remaining) ? remaining : rdBytes;
/* Read data from FIFO */
- CSL_ospiReadFifoData(hwAttrs->dataAddr+0x3FE0000, pDst, rdBytes);
+ CSL_ospiReadFifoData(hwAttrs->dataAddr + OSPI_INDAC_TRIG_ADDR, pDst, rdBytes);
pDst += rdBytes;
remaining -= rdBytes;
pDst += rdBytes;
remaining -= rdBytes;
CSL_archMemoryFence();
#endif
}
CSL_archMemoryFence();
#endif
}
+#ifdef SPI_CACHE_ENABLE
CacheP_wbInv((void *)(hwAttrs->dataAddr + offset), transaction->count);
CacheP_wbInv((void *)(hwAttrs->dataAddr + offset), transaction->count);
+#endif
}
return (0);
}
return (0);
wrBytes = (wrBytes > remaining) ? remaining : wrBytes;
/* Write data to FIFO */
wrBytes = (wrBytes > remaining) ? remaining : wrBytes;
/* Write data to FIFO */
- CSL_ospiWriteFifoData(hwAttrs->dataAddr+0x3FE0000, pSrc, wrBytes);
+ CSL_ospiWriteFifoData(hwAttrs->dataAddr + OSPI_INDAC_TRIG_ADDR, pSrc, wrBytes);
pSrc += wrBytes;
remaining -= wrBytes;
pSrc += wrBytes;
remaining -= wrBytes;
}
}
}
}
}
}
+#ifdef SPI_CACHE_ENABLE
CacheP_wbInv((void *)(hwAttrs->dataAddr + offset), transaction->count);
CacheP_wbInv((void *)(hwAttrs->dataAddr + offset), transaction->count);
+#endif
return (retVal);
}
return (retVal);
}
diff --git a/packages/ti/drv/spi/test/ospi_flash/src/main_ospi_flash_test.c b/packages/ti/drv/spi/test/ospi_flash/src/main_ospi_flash_test.c
index bffdcacd58f3ffbdf171cf8083f24bba9f1e8875..9f9dd828f4d2ad57bfac05aa1099ffe3baab413a 100755 (executable)
/* Init SPI driver */
SPI_init();
/* Init SPI driver */
SPI_init();
- while(1)
+ for (i = 0; ; i++)
{
{
- UART_printf("\r\n Which UT would you like to run? (9 to exit)\n");
- i = 0;
- UART_scanFmt("%d", &i);
-
- if(i == 9)
- {
- break;
- }
-
test = &Ospi_tests[i];
if (test->testFunc == NULL)
{
test = &Ospi_tests[i];
if (test->testFunc == NULL)
{
- UART_printf("\r\n Invalid number entered\n");
- continue;
- }
- else
- {
- UART_printf("\r\n Running UT %d\n", i);
+ break;
}
OSPI_configClk(test->clk, true);
}
OSPI_configClk(test->clk, true);
{
SPI_log("\r\n %s have failed\r\n", test->testDesc);
testFail = true;
{
SPI_log("\r\n %s have failed\r\n", test->testDesc);
testFail = true;
- //break;
+ break;
}
}
}
}
Board_init(boardCfg);
Board_init(boardCfg);
- volatile int loop = 0;
- while(loop)
- {
- /* wait for CCS connection */
- }
-
#ifdef USE_BIOS
Error_init(&eb);
#ifdef USE_BIOS
Error_init(&eb);
{
match = 0;
SPI_log("Data mismatch at idx %d\n", idx);
{
match = 0;
SPI_log("Data mismatch at idx %d\n", idx);
- SPI_log("\r\n expData \t rxData \n");
- SPI_log("\r\n %d \t %d \n", *expData, *rxData);
}
expData++;
rxData++;
}
expData++;
rxData++;