PDK-6948: Board: Updated am64x icss core clock to 250MHz
authorM V Pratap Reddy <x0257344@ti.com>
Fri, 27 Nov 2020 13:02:29 +0000 (18:32 +0530)
committerM V Pratap Reddy <x0257344@ti.com>
Fri, 27 Nov 2020 13:02:29 +0000 (18:32 +0530)
packages/ti/board/src/am64x_evm/board_pll.c

index 1aec47411550163c3ac0de85107a3e92a38c07c1..cc615a5591d50b47897cf576fe84508b0e2cb566 100644 (file)
@@ -65,18 +65,18 @@ static Board_PllClkCfg_t gBoardPllClkCfg[] =
    166666666\r
  }, //MAIN_PLL0_HSDIV1_CLKOUT,\r
 \r
- { TISCI_DEV_PRU_ICSSG0,\r
-   TISCI_DEV_PRU_ICSSG0_CORE_CLK,\r
-   225000000\r
- }, //MAIN_PLL2_HSDIV0_CLKOUT,\r
+ { TISCI_DEV_PRU_ICSSG1,\r
+   TISCI_DEV_PRU_ICSSG1_CORE_CLK,\r
+   250000000\r
+ }, //MAIN_PLL0_HSDIV9_CLKOUT,\r
 \r
- { TISCI_DEV_PRU_ICSSG0,\r
-   TISCI_DEV_PRU_ICSSG0_UCLK_CLK,\r
+ { TISCI_DEV_PRU_ICSSG1,\r
+   TISCI_DEV_PRU_ICSSG1_UCLK_CLK,\r
    192000000\r
  }, //MAIN_PLL1_HSDIV0_CLKOUT,\r
 \r
- { TISCI_DEV_PRU_ICSSG0,\r
-   TISCI_DEV_PRU_ICSSG0_RGMII_MHZ_250_CLK,\r
+ { TISCI_DEV_PRU_ICSSG1,\r
+   TISCI_DEV_PRU_ICSSG1_RGMII_MHZ_250_CLK,\r
    250000000\r
  }, //MAIN_PLL0_HSDIV4_CLKOUT,\r
 \r